opcodes/ChangeLog

   1 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
   2
   3         * micromips-opc.c (micromips_opcodes): Swap the two "dmtc1"
   4         entries with each other.
   5
   6 2021-05-27  Peter Bergner  <bergner@linux.ibm.com>
   7
   8         * ppc-opc.c (powerpc_opcodes) <xxmr, xxlnot>: New extended mnemonics.
   9
  10 2021-05-25  Alan Modra  <amodra@gmail.com>
  11
  12         * cris-desc.c: Regenerate.
  13         * cris-desc.h: Regenerate.
  14         * cris-opc.h: Regenerate.
  15         * po/POTFILES.in: Regenerate.
  16
  17 2021-05-24  Mike Frysinger  <vapier@gentoo.org>
  18
  19         * Makefile.am (HFILES): Add cris-desc.h & cris-opc.h.
  20         (TARGET_LIBOPCODES_CFILES): Add cris-desc.c.
  21         (CGEN_CPUS): Add cris.
  22         (CRIS_DEPS): Define.
  23         (stamp-cris): New rule.
  24         * cgen.sh: Handle desc action.
  25         * configure.ac (bfd_cris_arch): Add cris-desc.lo.
  26         * Makefile.in, configure: Regenerate.
  27
  28 2021-05-18  Job Noorman  <mtvec@pm.me>
  29
  30         PR 27814
  31         * riscv-dis.c (riscv_get_disassembler): Get elf attributes only for
  32         the elf objects.
  33
  34 2021-05-17  Alex Coplan  <alex.coplan@arm.com>
  35
  36         * arm-dis.c (mve_opcodes): Fix disassembly of
  37         MVE_VMOV2_GP_TO_VEC_LANE when idx == 1.
  38         (is_mve_encoding_conflict): MVE vector loads should not match
  39         when P = W = 0.
  40         (is_mve_unpredictable): It's not unpredictable to use the same
  41         source register twice (for MVE_VMOV2_GP_TO_VEC_LANE).
  42
  43 2021-05-11  Nick Clifton  <nickc@redhat.com>
  44
  45         PR 27840
  46         * tic30-dis.c (print_insn_tic30): Prevent attempts to read beyond
  47         the end of the code buffer.
  48
  49 2021-05-06  Stafford Horne  <shorne@gmail.com>
  50
  51         PR 21464
  52         * or1k-asm.c: Regenerate.
  53
  54 2021-05-01  Max Filippov  <jcmvbkbc@gmail.com>
  55
  56         * xtensa-dis.c (print_insn_xtensa): Fill in info->insn_type and
  57         info->insn_info_valid.
  58
  59 2021-04-26  Jan Beulich  <jbeulich@suse.com>
  60
  61         * i386-opc.tbl (lea): Add Optimize.
  62         * opcodes/i386-tbl.h: Re-generate.
  63
  64 2020-04-23  Max Filippov  <jcmvbkbc@gmail.com>
  65
  66         * xtensa-dis.c (print_xtensa_operand): For PC-relative operand
  67         of l32r fetch and display referenced literal value.
  68
  69 2021-04-23  Max Filippov  <jcmvbkbc@gmail.com>
  70
  71         * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk
  72         to 4 for literal disassembly.
  73
  74 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
  75
  76         * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support
  77         for TLBI instruction.
  78
  79 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
  80
  81         * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
  82         DC instruction.
  83
  84 2021-04-19  Jan Beulich  <jbeulich@suse.com>
  85
  86         * aarch64-asm.c (encode_asimd_fcvt): Add initializer for
  87         "qualifier".
  88         (convert_mov_to_movewide): Add initializer for "value".
  89
  90 2021-04-16  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
  91
  92         * aarch64-opc.c: Add RME system registers.
  93
  94 2021-04-16  Lifang Xia <lifang_xia@c-sky.com>
  95
  96         * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress
  97         "addi d,CV,z" to "c.mv d,CV".
  98
  99 2021-04-12  Alan Modra  <amodra@gmail.com>
 100
 101         * configure.ac (--enable-checking): Add support.
 102         * config.in: Regenerate.
 103         * configure: Regenerate.
 104
 105 2021-04-09  Tejas Belagod  <tejas.belagod@arm.com>
 106
 107         * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
 108         LD64/ST64 instructions to lse_atomic instead of ldstexcl.
 109
 110 2021-04-09  Alan Modra  <amodra@gmail.com>
 111
 112         * ppc-dis.c (struct dis_private): Add "special".
 113         (POWERPC_DIALECT): Delete.  Replace uses with..
 114         (private_data): ..this.  New inline function.
 115         (disassemble_init_powerpc): Init "special" names.
 116         (skip_optional_operands): Add is_pcrel arg, set when detecting R
 117         field of prefix instructions.
 118         (bsearch_reloc, print_got_plt): New functions.
 119         (print_insn_powerpc): For pcrel instructions, print target address
 120         and symbol if known, and decode plt and got loads too.
 121
 122 2021-04-08  Alan Modra  <amodra@gmail.com>
 123
 124         PR 27684
 125         * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
 126
 127 2021-04-08  Alan Modra  <amodra@gmail.com>
 128
 129         PR 27676
 130         * ppc-opc.c (DCBT_EO): Move earlier.
 131         (insert_thct, extract_thct, insert_thds, extract_thds): New functions.
 132         (powerpc_operands): Add THCT and THDS entries.
 133         (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
 134
 135 2021-04-06  Alan Modra  <amodra@gmail.com>
 136
 137         * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
 138         * s12z-dis.c (decode_possible_symbol): Use symbol returned from
 139         symbol_at_address_func.
 140
 141 2021-04-05  Alan Modra  <amodra@gmail.com>
 142
 143         * configure.ac: Don't check for limits.h, string.h, strings.h or
 144         stdlib.h.
 145         (AC_ISC_POSIX): Don't invoke.
 146         * sysdep.h: Include stdlib.h and string.h unconditionally.
 147         * i386-opc.h: Include limits.h unconditionally.
 148         * wasm32-dis.c: Likewise.
 149         * cgen-opc.c: Don't include alloca-conf.h.
 150         * config.in: Regenerate.
 151         * configure: Regenerate.
 152
 153 2021-04-01  Martin Liska  <mliska@suse.cz>
 154
 155         * arm-dis.c (strneq): Remove strneq and use startswith.
 156         * cr16-dis.c (print_insn_cr16): Likewise.
 157         * score-dis.c (streq): Likewise.
 158         (strneq): Likewise.
 159         * score7-dis.c (strneq): Likewise.
 160
 161 2021-04-01  Alan Modra  <amodra@gmail.com>
 162
 163         PR 27675
 164         * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
 165
 166 2021-03-31  Alan Modra  <amodra@gmail.com>
 167
 168         * sysdep.h (POISON_BFD_BOOLEAN): Define.
 169         * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
 170         * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
 171         * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
 172         * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
 173         * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
 174         * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
 175         * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
 176         * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
 177         * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
 178         * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
 179         * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
 180         * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
 181         * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
 182         and TRUE with true throughout.
 183
 184 2021-03-31  Alan Modra  <amodra@gmail.com>
 185
 186         * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
 187         * aarch64-dis.h: Likewise.
 188         * aarch64-opc.c: Likewise.
 189         * avr-dis.c: Likewise.
 190         * csky-dis.c: Likewise.
 191         * nds32-asm.c: Likewise.
 192         * nds32-dis.c: Likewise.
 193         * nfp-dis.c: Likewise.
 194         * riscv-dis.c: Likewise.
 195         * s12z-dis.c: Likewise.
 196         * wasm32-dis.c: Likewise.
 197
 198 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 199
 200         * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
 201         (i386_seg_prefixes): New.
 202         * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
 203         (i386_seg_prefixes): Declare.
 204
 205 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 206
 207         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
 208
 209 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 210
 211         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
 212         * i386-reg.tbl (st): Move down.
 213         (st(0)): Delete. Extend comment.
 214         * i386-tbl.h: Re-generate.
 215
 216 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 217
 218         * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
 219         (cmpsd): Move next to cmps.
 220         (movsd): Move next to movs.
 221         (cmpxchg16b): Move to separate section.
 222         (fisttp, fisttpll): Likewise.
 223         (monitor, mwait): Likewise.
 224         * i386-tbl.h: Re-generate.
 225
 226 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 227
 228         * i386-opc.tbl (psadbw): Add <sse2:comm>.
 229         (vpsadbw): Add C.
 230         * i386-tbl.h: Re-generate.
 231
 232 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 233
 234         * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
 235         pclmul, gfni): New templates. Use them wherever possible. Move
 236         SSE4.1 pextrw into respective section.
 237         * i386-tbl.h: Re-generate.
 238
 239 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 240
 241         * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
 242         strtoull(). Bump upper loop bound. Widen masks. Sanity check
 243         "length".
 244         * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
 245         Convert all of their uses to representation in opcode.
 246
 247 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 248
 249         * i386-opc.h (struct insn_template): Shrink base_opcode to 16
 250         bits. Shrink extension_opcode to 9 bits. Make it signed. Change
 251         value of None. Shrink operands to 3 bits.
 252
 253 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 254
 255         * i386-gen.c (process_i386_opcode_modifier): New parameter
 256         "space".
 257         (output_i386_opcode): New local variable "space". Adjust
 258         process_i386_opcode_modifier() invocation.
 259         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 260         invocation.
 261         * i386-tbl.h: Re-generate.
 262
 263 2021-03-29  Alan Modra  <amodra@gmail.com>
 264
 265         * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
 266         (fp_qualifier_p, get_data_pattern): Likewise.
 267         (aarch64_get_operand_modifier_from_value): Likewise.
 268         (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
 269         (operand_variant_qualifier_p): Likewise.
 270         (qualifier_value_in_range_constraint_p): Likewise.
 271         (aarch64_get_qualifier_esize): Likewise.
 272         (aarch64_get_qualifier_nelem): Likewise.
 273         (aarch64_get_qualifier_standard_value): Likewise.
 274         (get_lower_bound, get_upper_bound): Likewise.
 275         (aarch64_find_best_match, match_operands_qualifier): Likewise.
 276         (aarch64_print_operand): Likewise.
 277         * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
 278         (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
 279         (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
 280         * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
 281         * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
 282         (print_insn_tic6x): Likewise.
 283
 284 2021-03-29  Alan Modra  <amodra@gmail.com>
 285
 286         * arc-dis.c (extract_operand_value): Correct NULL cast.
 287         * frv-opc.h: Regenerate.
 288
 289 2021-03-26  Jan Beulich  <jbeulich@suse.com>
 290
 291         * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
 292         MMX form.
 293         * i386-tbl.h: Re-generate.
 294
 295 2021-03-25  Abid Qadeer  <abidh@codesourcery.com>
 296
 297         * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
 298         immediate in br.n instruction.
 299
 300 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 301
 302         * i386-dis.c (XMGatherD, VexGatherD): New.
 303         (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
 304         (print_insn): Check masking for S/G insns.
 305         (OP_E_memory): New local variable check_gather. Extend mandatory
 306         SIB check. Check register conflicts for (EVEX-encoded) gathers.
 307         Extend check for disallowed 16-bit addressing.
 308         (OP_VEX): New local variables modrm_reg and sib_index. Convert
 309         if()s to switch(). Check register conflicts for (VEX-encoded)
 310         gathers. Drop no longer reachable cases.
 311         * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
 312         vgatherdp*.
 313
 314 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 315
 316         * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
 317         zeroing-masking without masking.
 318
 319 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 320
 321         * i386-opc.tbl (invlpgb): Fix multi-operand form.
 322         (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
 323         single-operand forms as deprecated.
 324         * i386-tbl.h: Re-generate.
 325
 326 2021-03-25  Alan Modra  <amodra@gmail.com>
 327
 328         PR 27647
 329         * ppc-opc.c (XLOCB_MASK): Delete.
 330         (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
 331         XLBH_MASK.
 332         (powerpc_opcodes): Accept a BH field on all extended forms of
 333         bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
 334
 335 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 336
 337         * i386-gen.c (output_i386_opcode): Drop processing of
 338         opcode_length. Calculate length from base_opcode. Adjust prefix
 339         encoding determination.
 340         (process_i386_opcodes): Drop output of fake opcode_length.
 341         * i386-opc.h (struct insn_template): Drop opcode_length field.
 342         * i386-opc.tbl: Drop opcode length field from all templates.
 343         * i386-tbl.h: Re-generate.
 344
 345 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 346
 347         * i386-gen.c (process_i386_opcode_modifier): Return void. New
 348         parameter "prefix". Drop local variable "regular_encoding".
 349         Record prefix setting / check for consistency.
 350         (output_i386_opcode): Parse opcode_length and base_opcode
 351         earlier. Derive prefix encoding. Drop no longer applicable
 352         consistency checking. Adjust process_i386_opcode_modifier()
 353         invocation.
 354         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 355         invocation.
 356         * i386-tbl.h: Re-generate.
 357
 358 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 359
 360         * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
 361         check.
 362         * i386-opc.h (Prefix_*): Move #define-s.
 363         * i386-opc.tbl: Move pseudo prefix enumerator values to
 364         extension opcode field. Introduce pseudopfx template.
 365         * i386-tbl.h: Re-generate.
 366
 367 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 368
 369         * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
 370         comment.
 371         * i386-tbl.h: Re-generate.
 372
 373 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 374
 375         * i386-opc.h (struct insn_template): Move cpu_flags field past
 376         opcode_modifier one.
 377         * i386-tbl.h: Re-generate.
 378
 379 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 380
 381         * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
 382         * i386-opc.h (OpcodeSpace): New enumerator.
 383         (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
 384         (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
 385         SPACE_XOP09, SPACE_XOP0A): ... respectively.
 386         (struct i386_opcode_modifier): New field opcodespace. Shrink
 387         opcodeprefix field.
 388         i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
 389         SpaceXOP09, SpaceXOP0A): Define. Use them to replace
 390         OpcodePrefix uses.
 391         * i386-tbl.h: Re-generate.
 392
 393 2021-03-22  Martin Liska  <mliska@suse.cz>
 394
 395         * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
 396         * arc-dis.c (parse_option): Likewise.
 397         * arm-dis.c (parse_arm_disassembler_options): Likewise.
 398         * cris-dis.c (print_with_operands): Likewise.
 399         * h8300-dis.c (bfd_h8_disassemble): Likewise.
 400         * i386-dis.c (print_insn): Likewise.
 401         * ia64-gen.c (fetch_insn_class): Likewise.
 402         (parse_resource_users): Likewise.
 403         (in_iclass): Likewise.
 404         (lookup_specifier): Likewise.
 405         (insert_opcode_dependencies): Likewise.
 406         * mips-dis.c (parse_mips_ase_option): Likewise.
 407         (parse_mips_dis_option): Likewise.
 408         * s390-dis.c (disassemble_init_s390): Likewise.
 409         * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
 410
 411 2021-03-16  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
 412
 413         * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
 414
 415 2021-03-12  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 416
 417         * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
 418         icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
 419
 420 2021-03-12  Alan Modra  <amodra@gmail.com>
 421
 422         * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
 423
 424 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 425
 426         * i386-dis.c (OP_XMM): Re-order checks.
 427
 428 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 429
 430         * i386-dis.c (putop): Drop need_vex check when also checking
 431         vex.evex.
 432         (intel_operand_size, OP_E_memory): Drop vex.evex check when also
 433         checking vex.b.
 434
 435 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 436
 437         * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
 438         checks. Move case label past broadcast check.
 439
 440 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 441
 442         * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
 443         vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
 444         REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
 445         EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
 446         EVEX_W_0F38C7_M_0_L_2): Delete.
 447         (REG_EVEX_0F38C7_M_0_L_2): New.
 448         (intel_operand_size): Handle VEX and EVEX the same for
 449         vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
 450         vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
 451         (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
 452         vex_vsib_q_w_d_mode uses.
 453         * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
 454         0F38A1, and 0F38A3 entries.
 455         * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
 456         entry.
 457         * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
 458         * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
 459         0F38A3 entries.
 460
 461 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 462
 463         * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
 464         REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
 465         MOD_VEX_0FXOP_09_12): Rename to ...
 466         (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
 467         REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
 468         (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
 469         RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
 470         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 471         X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
 472         (reg_table): Adjust comments.
 473         (x86_64_table): Move X86_64_0F24, X86_64_0F26,
 474         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 475         X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
 476         (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
 477         (vex_len_table): Adjust opcode 0A_12 entry.
 478         (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
 479         MOD_C5_32BIT, and MOD_XOP_09_12 entries.
 480         (rm_table): Move hreset entry.
 481
 482 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 483
 484         * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
 485         EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
 486         EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
 487         EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
 488         EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
 489         (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
 490         (get_valid_dis386): Also handle 512-bit vector length when
 491         vectoring into vex_len_table[].
 492         * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
 493         0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
 494         entries.
 495         * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
 496         0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
 497         * i386-dis-evex-prefix.h: Adjust 0F7E entry.
 498         * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
 499         entries.
 500
 501 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 502
 503         * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
 504         Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
 505         EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
 506         * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
 507         entries.
 508         * i386-dis-evex-len.h (evex_len_table): Likewise.
 509         * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
 510
 511 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 512
 513         * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
 514         MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
 515         MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
 516         MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
 517         MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
 518         MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 519         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
 520         MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
 521         EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
 522         EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
 523         EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
 524         EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
 525         EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
 526         EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
 527         EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
 528         EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
 529         EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
 530         EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
 531         EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
 532         EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
 533         EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
 534         EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
 535         EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
 536         EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
 537         EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
 538         EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
 539         EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
 540         EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
 541         EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
 542         EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
 543         EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
 544         EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
 545         REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
 546         REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
 547         MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
 548         MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
 549         EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
 550         EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
 551         EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
 552         EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
 553         EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
 554         EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
 555         EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
 556         EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
 557         EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
 558         EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
 559         EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
 560         EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
 561         EVEX_W_0F3A43_L_n): New.
 562         * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
 563         0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
 564         0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
 565         * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
 566         for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
 567         0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
 568         0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
 569         * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
 570         0F385B, 0F38C6, and 0F38C7 entries.
 571         * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
 572         0F38C6 and 0F38C7.
 573         * i386-dis-evex-w.h: No longer link to evex_len_table[] for
 574         opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
 575         0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
 576         evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
 577
 578 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 579
 580         * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
 581         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 582         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 583         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 584         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 585         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 586         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 587         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 588         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 589         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 590         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 591         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 592         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 593         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 594         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 595         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 596         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 597         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 598         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 599         MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
 600         MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
 601         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 602         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 603         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 604         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 605         PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 606         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
 607         PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
 608         PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 609         PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
 610         VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
 611         VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
 612         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
 613         VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
 614         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
 615         VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
 616         VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
 617         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
 618         VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
 619         VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
 620         VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
 621         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
 622         VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
 623         VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
 624         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
 625         VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
 626         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
 627         VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
 628         VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
 629         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
 630         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
 631         VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
 632         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
 633         VEX_W_0F99_P_2_LEN_0): Delete.
 634         MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
 635         MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
 636         MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
 637         MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
 638         MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
 639         PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
 640         PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
 641         PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
 642         PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
 643         PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
 644         PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
 645         PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
 646         PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
 647         PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
 648         PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
 649         PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
 650         PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
 651         PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
 652         PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
 653         VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
 654         VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
 655         VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
 656         VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
 657         VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
 658         VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
 659         VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
 660         VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
 661         (prefix_table): No longer link to vex_len_table[] for opcodes
 662         0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
 663         0F92, 0F93, 0F98, and 0F99.
 664         (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
 665         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 666         0F98, and 0F99.
 667         (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
 668         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 669         0F98, and 0F99.
 670         (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
 671         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 672         0F98, and 0F99.
 673         (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
 674         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 675         0F98, and 0F99.
 676
 677 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 678
 679         * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
 680         Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
 681         REG_VEX_0F73_M_0 respectively.
 682         (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
 683         MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
 684         MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
 685         MOD_VEX_0F73_REG_7): Delete.
 686         (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
 687         (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
 688         PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
 689         PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
 690         PREFIX_VEX_0F3AF0_L_0 respectively.
 691         (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
 692         VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
 693         VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
 694         VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
 695         (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
 696         VEX_LEN_0F38F7): New.
 697         (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
 698         (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
 699         0F72, and 0F73. No longer link to vex_len_table[] for opcode
 700         0F38F3.
 701         (prefix_table): No longer link to vex_len_table[] for opcodes
 702         0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 703         (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
 704         0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
 705         0F38F6, 0F38F7, and 0F3AF0.
 706         (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
 707         prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 708         (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
 709         0F73.
 710
 711 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 712
 713         * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
 714         REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
 715         (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
 716         MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
 717         MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
 718         (MOD_0F71, MOD_0F72, MOD_0F73): New.
 719         (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
 720         73.
 721         (reg_table): No longer link to mod_table[] for opcodes 0F71,
 722         0F72, and 0F73.
 723         (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
 724         0F73.
 725
 726 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 727
 728         * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
 729         MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
 730         (reg_table): Don't link to mod_table[] where not needed. Add
 731         PREFIX_IGNORED to nop entries.
 732         (prefix_table): Replace PREFIX_OPCODE in nop entries.
 733         (mod_table): Add nop entries next to prefetch ones. Drop
 734         MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
 735         MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
 736         (rm_table): Add PREFIX_IGNORED to nop entries. Drop
 737         PREFIX_OPCODE from endbr* entries.
 738         (get_valid_dis386): Also consider entry's name when zapping
 739         vindex.
 740         (print_insn): Handle PREFIX_IGNORED.
 741
 742 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 743
 744         * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
 745         IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
 746         element.
 747         * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
 748         HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
 749         (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
 750         PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
 751         (struct i386_opcode_modifier): Delete notrackprefixok,
 752         islockable, hleprefixok, and repprefixok fields. Add prefixok
 753         field.
 754         * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
 755         HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
 756         (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
 757         not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
 758         Replace HLEPrefixOk.
 759         * opcodes/i386-tbl.h: Re-generate.
 760
 761 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 762
 763         * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
 764         * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
 765         64-bit form.
 766         * opcodes/i386-tbl.h: Re-generate.
 767
 768 2021-03-03  Jan Beulich  <jbeulich@suse.com>
 769
 770         * i386-gen.c (output_i386_opcode): Don't get operand count. Look
 771         for {} instead of {0}. Don't look for '0'.
 772         * i386-opc.tbl: Drop operand count field. Drop redundant operand
 773         size specifiers.
 774
 775 2021-02-19  Nelson Chu  <nelson.chu@sifive.com>
 776
 777         PR 27158
 778         * riscv-dis.c (print_insn_args): Updated encoding macros.
 779         * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
 780         (match_c_addi16sp): Updated encoding macros.
 781         (match_c_lui): Likewise.
 782         (match_c_lui_with_hint): Likewise.
 783         (match_c_addi4spn): Likewise.
 784         (match_c_slli): Likewise.
 785         (match_slli_as_c_slli): Likewise.
 786         (match_c_slli64): Likewise.
 787         (match_srxi_as_c_srxi): Likewise.
 788         (riscv_insn_types): Added .insn css/cl/cs.
 789
 790 2021-02-18  Nelson Chu  <nelson.chu@sifive.com>
 791
 792         * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
 793         (default_priv_spec): Updated type to riscv_spec_class.
 794         (parse_riscv_dis_option): Updated.
 795         * riscv-opc.c: Moved stuff and make the file tidy.
 796
 797 2021-02-17  Alan Modra  <amodra@gmail.com>
 798
 799         * wasm32-dis.c: Include limits.h.
 800         (CHAR_BIT): Provide backup define.
 801         (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
 802         Correct signed overflow checking.
 803
 804 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 805
 806         * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
 807         * i386-tbl.h: Re-generate.
 808
 809 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 810
 811         * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
 812         Oword.
 813         * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
 814
 815 2021-02-15  Andreas Krebbel  <krebbel@linux.ibm.com>
 816
 817         * s390-mkopc.c (main): Accept arch14 as cpu string.
 818         * s390-opc.txt: Add new arch14 instructions.
 819
 820 2021-02-04  Nick Alcock  <nick.alcock@oracle.com>
 821
 822         * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
 823         favour of LIBINTL.
 824         * configure: Regenerated.
 825
 826 2021-02-08  Mike Frysinger  <vapier@gentoo.org>
 827
 828         * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
 829         * tic54x-opc.c (regs): Rename to ...
 830         (tic54x_regs): ... this.
 831         (mmregs): Rename to ...
 832         (tic54x_mmregs): ... this.
 833         (condition_codes): Rename to ...
 834         (tic54x_condition_codes): ... this.
 835         (cc2_codes): Rename to ...
 836         (tic54x_cc2_codes): ... this.
 837         (cc3_codes): Rename to ...
 838         (tic54x_cc3_codes): ... this.
 839         (status_bits): Rename to ...
 840         (tic54x_status_bits): ... this.
 841         (misc_symbols): Rename to ...
 842         (tic54x_misc_symbols): ... this.
 843
 844 2021-02-04  Nelson Chu  <nelson.chu@sifive.com>
 845
 846         * riscv-opc.c (MASK_RVB_IMM): Removed.
 847         (riscv_opcodes): Removed zb* instructions.
 848         (riscv_ext_version_table): Removed versions for zb*.
 849
 850 2021-01-26  Alan Modra  <amodra@gmail.com>
 851
 852         * i386-gen.c (parse_template): Ensure entire template_instance
 853         is initialised.
 854
 855 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 856
 857         * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
 858         (riscv_fpr_names_abi): Likewise.
 859         (riscv_opcodes): Likewise.
 860         (riscv_insn_types): Likewise.
 861
 862 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 863
 864         * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
 865
 866 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 867
 868         * riscv-dis.c: Comments tidy and improvement.
 869         * riscv-opc.c: Likewise.
 870
 871 2021-01-13  Alan Modra  <amodra@gmail.com>
 872
 873         * Makefile.in: Regenerate.
 874
 875 2021-01-12  H.J. Lu  <hongjiu.lu@intel.com>
 876
 877         PR binutils/26792
 878         * configure.ac: Use GNU_MAKE_JOBSERVER.
 879         * aclocal.m4: Regenerated.
 880         * configure: Likewise.
 881
 882 2021-01-12  Nick Clifton  <nickc@redhat.com>
 883
 884         * po/sr.po: Updated Serbian translation.
 885
 886 2021-01-11  H.J. Lu  <hongjiu.lu@intel.com>
 887
 888         PR ld/27173
 889         * configure: Regenerated.
 890
 891 2021-01-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 892
 893         * aarch64-asm-2.c: Regenerate.
 894         * aarch64-dis-2.c: Likewise.
 895         * aarch64-opc-2.c: Likewise.
 896         * aarch64-opc.c (aarch64_print_operand):
 897         Delete handling of AARCH64_OPND_CSRE_CSR.
 898         * aarch64-tbl.h (aarch64_feature_csre): Delete.
 899         (CSRE): Likewise.
 900         (_CSRE_INSN): Likewise.
 901         (aarch64_opcode_table): Delete csr.
 902
 903 2021-01-11  Nick Clifton  <nickc@redhat.com>
 904
 905         * po/de.po: Updated German translation.
 906         * po/fr.po: Updated French translation.
 907         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 908         * po/sv.po: Updated Swedish translation.
 909         * po/uk.po: Updated Ukranian translation.
 910
 911 2021-01-09  H.J. Lu  <hongjiu.lu@intel.com>
 912
 913         * configure: Regenerated.
 914
 915 2021-01-09  Nick Clifton  <nickc@redhat.com>
 916
 917         * configure: Regenerate.
 918         * po/opcodes.pot: Regenerate.
 919
 920 2021-01-09  Nick Clifton  <nickc@redhat.com>
 921
 922         * 2.36 release branch crated.
 923
 924 2021-01-08  Peter Bergner  <bergner@linux.ibm.com>
 925
 926         * ppc-opc.c (insert_dw, (extract_dw): New functions.
 927         (DW, (XRC_MASK): Define.
 928         (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
 929
 930 2021-01-09  Alan Modra  <amodra@gmail.com>
 931
 932         * configure: Regenerate.
 933
 934 2021-01-08  Nick Clifton  <nickc@redhat.com>
 935
 936         * po/sv.po: Updated Swedish translation.
 937
 938 2021-01-08  Nick Clifton  <nickc@redhat.com>
 939
 940         PR 27129
 941         * aarch64-dis.c (determine_disassembling_preference): Move call to
 942         aarch64_match_operands_constraint outside of the assertion.
 943         * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
 944         Replace with a return of FALSE.
 945
 946         PR 27139
 947         * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
 948         core system register.
 949
 950 2021-01-07  Samuel Thibault  <samuel.thibault@gnu.org>
 951
 952         * configure: Regenerate.
 953
 954 2021-01-07  Nick Clifton  <nickc@redhat.com>
 955
 956         * po/fr.po: Updated French translation.
 957
 958 2021-01-07  Fredrik Noring  <noring@nocrew.org>
 959
 960         * m68k-opc.c (chkl): Change minimum architecture requirement to
 961         m68020.
 962
 963 2021-01-07  Philipp Tomsich  <prt@gnu.org>
 964
 965         * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
 966
 967 2021-01-07  Claire Xenia Wolf  <claire@symbioticeda.com>
 968             Jim Wilson  <jimw@sifive.com>
 969             Andrew Waterman  <andrew@sifive.com>
 970             Maxim Blinov  <maxim.blinov@embecosm.com>
 971             Kito Cheng  <kito.cheng@sifive.com>
 972             Nelson Chu  <nelson.chu@sifive.com>
 973
 974         * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
 975         (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
 976
 977 2021-01-01  Alan Modra  <amodra@gmail.com>
 978
 979         Update year range in copyright notice of all files.
 980
 981 For older changes see ChangeLog-2020
 982 \f
 983 Copyright (C) 2021 Free Software Foundation, Inc.
 984
 985 Copying and distribution of this file, with or without modification,
 986 are permitted in any medium without royalty provided the copyright
 987 notice and this notice are preserved.
 988
 989 Local Variables:
 990 mode: change-log
 991 left-margin: 8
 992 fill-column: 74
 993 version-control: never
 994 End: