opcodes/ChangeLog

   1 2022-03-06  Sagar Patel  <sagarmp@cs.unc.edu>
   2             Maciej W. Rozycki  <macro@orcam.me.uk>
   3
   4         * mips-opc.c (mips_builtin_opcodes): Fix INSN2_ALIAS annotation
   5         for "bal", "beqz", "beqzl", "bnez" and "bnezl" instructions.
   6         * micromips-opc.c (micromips_opcodes): Likewise for "beqz" and
   7         "bnez" instructions.
   8
   9 2022-02-17  Nick Clifton  <nickc@redhat.com>
  10
  11         * po/sr.po: Updated Serbian translation.
  12
  13 2022-02-14  Sergei Trofimovich  <siarheit@google.com>
  14
  15         * microblaze-opcm.h: Renamed 'fsqrt' to 'microblaze_fsqrt'.
  16         * microblaze-opc.h: Follow 'fsqrt' rename.
  17
  18 2022-01-24  Nick Clifton  <nickc@redhat.com>
  19
  20         * po/ro.po: Updated Romanian translation.
  21         * po/uk.po: Updated Ukranian translation.
  22
  23 2022-01-22  Nick Clifton  <nickc@redhat.com>
  24
  25         * configure: Regenerate.
  26         * po/opcodes.pot: Regenerate.
  27
  28 2022-01-22  Nick Clifton  <nickc@redhat.com>
  29
  30         * 2.38 release branch created.
  31
  32 2022-01-17  Nick Clifton  <nickc@redhat.com>
  33
  34         * Makefile.in: Regenerate.
  35         * po/opcodes.pot: Regenerate.
  36
  37 2021-12-02  Marcus Nilsson  <brainbomb@gmail.com>
  38
  39         * avr-dis.c (avr_operand); Pass in disassemble_info and fill
  40         in insn_type on branching instructions.
  41
  42 2021-11-25  Andrew Burgess  <aburgess@redhat.com>
  43             Simon Cook  <simon.cook@embecosm.com>
  44
  45         * riscv-dis.c (enum riscv_option_arg_t): New enum typedef.
  46         (riscv_options): New static global.
  47         (disassembler_options_riscv): New function.
  48         (print_riscv_disassembler_options): Rewrite to use
  49         disassembler_options_riscv.
  50
  51 2021-11-25  Nick Clifton  <nickc@redhat.com>
  52
  53         PR 28614
  54         * aarch64-asm.c: Replace assert(0) with real code.
  55         * aarch64-dis.c: Likewise.
  56         * aarch64-opc.c: Likewise.
  57
  58 2021-11-25  Nick Clifton  <nickc@redhat.com>
  59
  60         * po/fr.po; Updated French translation.
  61
  62 2021-10-27  Maciej W. Rozycki  <macro@embecosm.com>
  63
  64         * Makefile.am: Remove obsolete comment.
  65         * configure.ac: Refer `libbfd.la' to link shared BFD library
  66         except for Cygwin.
  67         * Makefile.in: Regenerate.
  68         * configure: Regenerate.
  69
  70 2021-09-27  Nick Alcock  <nick.alcock@oracle.com>
  71
  72         * configure: Regenerate.
  73
  74 2021-09-25  Peter Bergner  <bergner@linux.ibm.com>
  75
  76         * ppc-opc.c (powerpc_opcodes) <mfppr, mfppr32, mtppr, mtppr32>: Enable
  77         on POWER5 and later.
  78
  79 2021-09-20  Andrew Burgess  <andrew.burgess@embecosm.com>
  80
  81         * riscv-dis.c (riscv_disassemble_insn): Print a .%dbyte opcode
  82         before an unknown instruction, '%d' is replaced with the
  83         instruction length.
  84
  85 2021-09-02  Nick Clifton  <nickc@redhat.com>
  86
  87         PR 28292
  88         * v850-opc.c (D16): Use BFD_RELOC_V850_LO16_SPLIT_OFFSET in place
  89         of BFD_RELOC_16.
  90
  91 2021-08-17  Shahab Vahedi <shahab@synopsys.com>
  92
  93         * arc-regs.h (DEF): Fix the register numbers.
  94
  95 2021-08-10  Nick Clifton  <nickc@redhat.com>
  96
  97         * po/sr.po: Updated Serbian translation.
  98
  99 2021-07-26  Chenghua Xu  <xuchenghua@loongson.cn>
 100
 101         * mips-dis.c (mips_arch_choices): Correct gs264e bfd_mach.
 102
 103 2021-06-07  Andreas Krebbel  <krebbel@linux.ibm.com>
 104
 105         * s390-opc.txt: Add qpaci.
 106
 107 2021-07-03  Nick Clifton  <nickc@redhat.com>
 108
 109         * configure: Regenerate.
 110         * po/opcodes.pot: Regenerate.
 111
 112 2021-07-03  Nick Clifton  <nickc@redhat.com>
 113
 114         * 2.37 release branch created.
 115
 116 2021-07-02  Alan Modra  <amodra@gmail.com>
 117
 118         * nds32-dis.c (nds32_find_reg_keyword): Constify arg and return.
 119         (nds32_parse_audio_ext, nds32_parse_opcode): Constify psys_reg.
 120         (nds32_field_table, nds32_opcode_table, nds32_keyword_table),
 121         (nds32_opcodes, nds32_operand_fields, nds32_keywords),
 122         (nds32_keyword_gpr): Move declarations to..
 123         * nds32-asm.h: ..here, constifying to match definitions.
 124
 125 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 126
 127         * Makefile.am (GUILE): New variable.
 128         (CGEN): Use $(GUILE).
 129         * Makefile.in: Regenerate.
 130
 131 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 132
 133         * mep-asm.c (macros): Mark static & const.
 134         (lookup_macro): Change return & m to const.
 135         (expand_macro): Change mac to const.
 136         (expand_string): Change pmacro to const.
 137
 138 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 139
 140         * nds32-asm.c (operand_fields): Rename to ...
 141         (nds32_operand_fields): ... this.
 142         (keyword_gpr): Rename to ...
 143         (nds32_keyword_gpr): ... this.
 144         (keyword_usr, keyword_dxr, keyword_sr, keyword_cp, keyword_cpr,
 145         keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm,
 146         keyword_dpref_st, keyword_cctl_lv, keyword_standby_st,
 147         keyword_msync_st, keyword_im5_i, keyword_im5_m, keyword_accumulator,
 148         keyword_aridx, keyword_aridx2, keyword_aridxi, keyword_aridxi_mx):
 149         Mark static.
 150         (keywords): Rename to ...
 151         (nds32_keywords): ... this.
 152         * nds32-dis.c: Rename operand_fields to nds32_operand_fields,
 153         keywords to nds32_keywords, and keyword_gpr to nds32_keyword_gpr.
 154
 155 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 156
 157         * z80-dis.c (opc_ed): Make const.
 158         (pref_ed): Make p const.
 159
 160 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 161
 162         * microblaze-dis.c (get_field_special): Make op const.
 163         (read_insn_microblaze): Make opr & op const.  Rename opcodes to
 164         microblaze_opcodes.
 165         (print_insn_microblaze): Make op & pop const.
 166         (get_insn_microblaze): Make op const.  Rename opcodes to
 167         microblaze_opcodes.
 168         (microblaze_get_target_address): Likewise.
 169         * microblaze-opc.h (struct op_code_struct): Make const.
 170         Rename opcodes to microblaze_opcodes.
 171
 172 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 173
 174         * aarch64-gen.c (aarch64_opcode_table): Add const.
 175         * aarch64-tbl.h (aarch64_opcode_table): Likewise.
 176
 177 2021-06-22  Andrew Burgess  <andrew.burgess@embecosm.com>
 178
 179         * cgen-dis.c (count_decodable_bits): Use __builtin_popcount when
 180         available.
 181
 182 2021-06-22  Alan Modra  <amodra@gmail.com>
 183
 184         * pj-dis.c (print_insn_pj): Don't print trailing tab.  Do
 185         print separator for pcrel insns.
 186
 187 2021-06-19  Alan Modra  <amodra@gmail.com>
 188
 189         * vax-dis.c (print_insn_vax): Avoid pointer overflow.
 190
 191 2021-06-19  Alan Modra  <amodra@gmail.com>
 192
 193         * tic30-dis.c (get_register_operand): Don't ask strncpy to fill
 194         entire buffer.
 195
 196 2021-06-17  Alan Modra  <amodra@gmail.com>
 197
 198         * ppc-opc.c (powerpc_opcodes): Move cell db*cyc to proper location
 199         in table.
 200
 201 2021-06-03  Alan Modra  <amodra@gmail.com>
 202
 203         PR 1202
 204         * mcore-dis.c (print_insn_mcore): Correct loopt disassembly.
 205         Use unsigned int for inst.
 206
 207 2021-06-02  Shahab Vahedi  <shahab@synopsys.com>
 208
 209         * arc-dis.c (arc_option_arg_t): New enumeration.
 210         (arc_options): New variable.
 211         (disassembler_options_arc): New function.
 212         (print_arc_disassembler_options): Reimplement in terms of
 213         "disassembler_options_arc".
 214
 215 2021-05-29  Alan Modra  <amodra@gmail.com>
 216
 217         * ppc-dis.c (lookup_powerpc): Test deprecated field when -Many.
 218         Don't special case PPC_OPCODE_RAW.
 219         (lookup_prefix): Likewise.
 220         (lookup_vle, lookup_spe2): Similarly.  Add dialect parameter and..
 221         (print_insn_powerpc): ..update caller.
 222         * ppc-opc.c (EXT): Define.
 223         (powerpc_opcodes): Mark extended mnemonics with EXT.
 224         (prefix_opcodes, vle_opcodes): Likewise.
 225         (XISEL, XISEL_MASK): Add cr field and simplify.
 226         (powerpc_opcodes): Use XISEL with extended isel mnemonics and sort
 227         all isel variants to where the base mnemonic belongs.  Sort dstt,
 228         dststt and dssall.
 229
 230 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 231
 232         * mips-opc.c (mips_builtin_opcodes): Reorder legacy COP0, COP2,
 233         COP3 opcode instructions.
 234
 235 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 236
 237         * mips-opc.c (mips_builtin_opcodes): Update exclusion list for
 238         "ldc2", "ldc3", "lwc0", "lwc2", "lwc3", "sdc2", "sdc3", "swc0",
 239         "swc2", "swc3", "cfc0", "ctc0", "bc2f", "bc2fl", "bc2t",
 240         "bc2tl", "cfc2", "ctc2", "dmfc2", "dmtc2", "mfc2", "mtc2",
 241         "bc3f", "bc3fl", "bc3t", "bc3tl", "cfc3", "ctc3", "mfc3",
 242         "mtc3", "bc0f", "bc0fl", "bc0t", "bc0tl", "rfe", "c2", "c3",
 243         "cop2", and "cop3" entries.
 244
 245 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 246
 247         * mips-opc.c (mips_builtin_opcodes): Remove "dmfc3" and "dmtc3"
 248         entries and associated comments.
 249
 250 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 251
 252         * mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead
 253         of "c0".
 254
 255 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 256
 257         * mips-dis.c (mips_cp1_names_mips): New variable.
 258         (mips_arch_choices): Use it rather than `mips_cp1_names_numeric'
 259         for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120",
 260         "r4300", "r4400", "r4600", "r4650", "r5000", "vr5400", "vr5500",
 261         "r5900", "r6000", "rm7000", "rm9000", "r8000", "r10000",
 262         "r12000", "r14000", "r16000", "mips5", "loongson2e", and
 263         "loongson2f".
 264
 265 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 266
 267         * mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register
 268         handling code over to...
 269         <OP_REG_CONTROL>: ... this new case.
 270         * mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases.
 271         (mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2",
 272         "cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries
 273         replacing the `G' operand code with `g'.  Update "cftc1" and
 274         "cftc2" entries replacing the `E' operand code with `y'.
 275         * micromips-opc.c (decode_micromips_operand) <'g'>: New case.
 276         (micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2"
 277         entries replacing the `G' operand code with `g'.
 278
 279 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 280
 281         * mips-dis.c (mips_cp0_names_r3900): New variable.
 282         (mips_arch_choices): Use it rather than `mips_cp0_names_numeric'
 283         for "r3900".
 284
 285 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 286
 287         * mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2",
 288         and "mtthc2" to using the `G' rather than `g' operand code for
 289         the coprocessor control register referred.
 290
 291 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 292
 293         * micromips-opc.c (micromips_opcodes): Swap the two "dmtc1"
 294         entries with each other.
 295
 296 2021-05-27  Peter Bergner  <bergner@linux.ibm.com>
 297
 298         * ppc-opc.c (powerpc_opcodes) <xxmr, xxlnot>: New extended mnemonics.
 299
 300 2021-05-25  Alan Modra  <amodra@gmail.com>
 301
 302         * cris-desc.c: Regenerate.
 303         * cris-desc.h: Regenerate.
 304         * cris-opc.h: Regenerate.
 305         * po/POTFILES.in: Regenerate.
 306
 307 2021-05-24  Mike Frysinger  <vapier@gentoo.org>
 308
 309         * Makefile.am (HFILES): Add cris-desc.h & cris-opc.h.
 310         (TARGET_LIBOPCODES_CFILES): Add cris-desc.c.
 311         (CGEN_CPUS): Add cris.
 312         (CRIS_DEPS): Define.
 313         (stamp-cris): New rule.
 314         * cgen.sh: Handle desc action.
 315         * configure.ac (bfd_cris_arch): Add cris-desc.lo.
 316         * Makefile.in, configure: Regenerate.
 317
 318 2021-05-18  Job Noorman  <mtvec@pm.me>
 319
 320         PR 27814
 321         * riscv-dis.c (riscv_get_disassembler): Get elf attributes only for
 322         the elf objects.
 323
 324 2021-05-17  Alex Coplan  <alex.coplan@arm.com>
 325
 326         * arm-dis.c (mve_opcodes): Fix disassembly of
 327         MVE_VMOV2_GP_TO_VEC_LANE when idx == 1.
 328         (is_mve_encoding_conflict): MVE vector loads should not match
 329         when P = W = 0.
 330         (is_mve_unpredictable): It's not unpredictable to use the same
 331         source register twice (for MVE_VMOV2_GP_TO_VEC_LANE).
 332
 333 2021-05-11  Nick Clifton  <nickc@redhat.com>
 334
 335         PR 27840
 336         * tic30-dis.c (print_insn_tic30): Prevent attempts to read beyond
 337         the end of the code buffer.
 338
 339 2021-05-06  Stafford Horne  <shorne@gmail.com>
 340
 341         PR 21464
 342         * or1k-asm.c: Regenerate.
 343
 344 2021-05-01  Max Filippov  <jcmvbkbc@gmail.com>
 345
 346         * xtensa-dis.c (print_insn_xtensa): Fill in info->insn_type and
 347         info->insn_info_valid.
 348
 349 2021-04-26  Jan Beulich  <jbeulich@suse.com>
 350
 351         * i386-opc.tbl (lea): Add Optimize.
 352         * opcodes/i386-tbl.h: Re-generate.
 353
 354 2020-04-23  Max Filippov  <jcmvbkbc@gmail.com>
 355
 356         * xtensa-dis.c (print_xtensa_operand): For PC-relative operand
 357         of l32r fetch and display referenced literal value.
 358
 359 2021-04-23  Max Filippov  <jcmvbkbc@gmail.com>
 360
 361         * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk
 362         to 4 for literal disassembly.
 363
 364 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 365
 366         * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support
 367         for TLBI instruction.
 368
 369 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 370
 371         * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
 372         DC instruction.
 373
 374 2021-04-19  Jan Beulich  <jbeulich@suse.com>
 375
 376         * aarch64-asm.c (encode_asimd_fcvt): Add initializer for
 377         "qualifier".
 378         (convert_mov_to_movewide): Add initializer for "value".
 379
 380 2021-04-16  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 381
 382         * aarch64-opc.c: Add RME system registers.
 383
 384 2021-04-16  Lifang Xia <lifang_xia@c-sky.com>
 385
 386         * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress
 387         "addi d,CV,z" to "c.mv d,CV".
 388
 389 2021-04-12  Alan Modra  <amodra@gmail.com>
 390
 391         * configure.ac (--enable-checking): Add support.
 392         * config.in: Regenerate.
 393         * configure: Regenerate.
 394
 395 2021-04-09  Tejas Belagod  <tejas.belagod@arm.com>
 396
 397         * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
 398         LD64/ST64 instructions to lse_atomic instead of ldstexcl.
 399
 400 2021-04-09  Alan Modra  <amodra@gmail.com>
 401
 402         * ppc-dis.c (struct dis_private): Add "special".
 403         (POWERPC_DIALECT): Delete.  Replace uses with..
 404         (private_data): ..this.  New inline function.
 405         (disassemble_init_powerpc): Init "special" names.
 406         (skip_optional_operands): Add is_pcrel arg, set when detecting R
 407         field of prefix instructions.
 408         (bsearch_reloc, print_got_plt): New functions.
 409         (print_insn_powerpc): For pcrel instructions, print target address
 410         and symbol if known, and decode plt and got loads too.
 411
 412 2021-04-08  Alan Modra  <amodra@gmail.com>
 413
 414         PR 27684
 415         * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
 416
 417 2021-04-08  Alan Modra  <amodra@gmail.com>
 418
 419         PR 27676
 420         * ppc-opc.c (DCBT_EO): Move earlier.
 421         (insert_thct, extract_thct, insert_thds, extract_thds): New functions.
 422         (powerpc_operands): Add THCT and THDS entries.
 423         (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
 424
 425 2021-04-06  Alan Modra  <amodra@gmail.com>
 426
 427         * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
 428         * s12z-dis.c (decode_possible_symbol): Use symbol returned from
 429         symbol_at_address_func.
 430
 431 2021-04-05  Alan Modra  <amodra@gmail.com>
 432
 433         * configure.ac: Don't check for limits.h, string.h, strings.h or
 434         stdlib.h.
 435         (AC_ISC_POSIX): Don't invoke.
 436         * sysdep.h: Include stdlib.h and string.h unconditionally.
 437         * i386-opc.h: Include limits.h unconditionally.
 438         * wasm32-dis.c: Likewise.
 439         * cgen-opc.c: Don't include alloca-conf.h.
 440         * config.in: Regenerate.
 441         * configure: Regenerate.
 442
 443 2021-04-01  Martin Liska  <mliska@suse.cz>
 444
 445         * arm-dis.c (strneq): Remove strneq and use startswith.
 446         * cr16-dis.c (print_insn_cr16): Likewise.
 447         * score-dis.c (streq): Likewise.
 448         (strneq): Likewise.
 449         * score7-dis.c (strneq): Likewise.
 450
 451 2021-04-01  Alan Modra  <amodra@gmail.com>
 452
 453         PR 27675
 454         * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
 455
 456 2021-03-31  Alan Modra  <amodra@gmail.com>
 457
 458         * sysdep.h (POISON_BFD_BOOLEAN): Define.
 459         * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
 460         * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
 461         * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
 462         * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
 463         * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
 464         * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
 465         * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
 466         * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
 467         * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
 468         * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
 469         * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
 470         * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
 471         * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
 472         and TRUE with true throughout.
 473
 474 2021-03-31  Alan Modra  <amodra@gmail.com>
 475
 476         * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
 477         * aarch64-dis.h: Likewise.
 478         * aarch64-opc.c: Likewise.
 479         * avr-dis.c: Likewise.
 480         * csky-dis.c: Likewise.
 481         * nds32-asm.c: Likewise.
 482         * nds32-dis.c: Likewise.
 483         * nfp-dis.c: Likewise.
 484         * riscv-dis.c: Likewise.
 485         * s12z-dis.c: Likewise.
 486         * wasm32-dis.c: Likewise.
 487
 488 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 489
 490         * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
 491         (i386_seg_prefixes): New.
 492         * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
 493         (i386_seg_prefixes): Declare.
 494
 495 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 496
 497         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
 498
 499 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 500
 501         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
 502         * i386-reg.tbl (st): Move down.
 503         (st(0)): Delete. Extend comment.
 504         * i386-tbl.h: Re-generate.
 505
 506 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 507
 508         * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
 509         (cmpsd): Move next to cmps.
 510         (movsd): Move next to movs.
 511         (cmpxchg16b): Move to separate section.
 512         (fisttp, fisttpll): Likewise.
 513         (monitor, mwait): Likewise.
 514         * i386-tbl.h: Re-generate.
 515
 516 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 517
 518         * i386-opc.tbl (psadbw): Add <sse2:comm>.
 519         (vpsadbw): Add C.
 520         * i386-tbl.h: Re-generate.
 521
 522 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 523
 524         * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
 525         pclmul, gfni): New templates. Use them wherever possible. Move
 526         SSE4.1 pextrw into respective section.
 527         * i386-tbl.h: Re-generate.
 528
 529 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 530
 531         * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
 532         strtoull(). Bump upper loop bound. Widen masks. Sanity check
 533         "length".
 534         * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
 535         Convert all of their uses to representation in opcode.
 536
 537 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 538
 539         * i386-opc.h (struct insn_template): Shrink base_opcode to 16
 540         bits. Shrink extension_opcode to 9 bits. Make it signed. Change
 541         value of None. Shrink operands to 3 bits.
 542
 543 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 544
 545         * i386-gen.c (process_i386_opcode_modifier): New parameter
 546         "space".
 547         (output_i386_opcode): New local variable "space". Adjust
 548         process_i386_opcode_modifier() invocation.
 549         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 550         invocation.
 551         * i386-tbl.h: Re-generate.
 552
 553 2021-03-29  Alan Modra  <amodra@gmail.com>
 554
 555         * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
 556         (fp_qualifier_p, get_data_pattern): Likewise.
 557         (aarch64_get_operand_modifier_from_value): Likewise.
 558         (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
 559         (operand_variant_qualifier_p): Likewise.
 560         (qualifier_value_in_range_constraint_p): Likewise.
 561         (aarch64_get_qualifier_esize): Likewise.
 562         (aarch64_get_qualifier_nelem): Likewise.
 563         (aarch64_get_qualifier_standard_value): Likewise.
 564         (get_lower_bound, get_upper_bound): Likewise.
 565         (aarch64_find_best_match, match_operands_qualifier): Likewise.
 566         (aarch64_print_operand): Likewise.
 567         * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
 568         (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
 569         (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
 570         * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
 571         * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
 572         (print_insn_tic6x): Likewise.
 573
 574 2021-03-29  Alan Modra  <amodra@gmail.com>
 575
 576         * arc-dis.c (extract_operand_value): Correct NULL cast.
 577         * frv-opc.h: Regenerate.
 578
 579 2021-03-26  Jan Beulich  <jbeulich@suse.com>
 580
 581         * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
 582         MMX form.
 583         * i386-tbl.h: Re-generate.
 584
 585 2021-03-25  Abid Qadeer  <abidh@codesourcery.com>
 586
 587         * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
 588         immediate in br.n instruction.
 589
 590 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 591
 592         * i386-dis.c (XMGatherD, VexGatherD): New.
 593         (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
 594         (print_insn): Check masking for S/G insns.
 595         (OP_E_memory): New local variable check_gather. Extend mandatory
 596         SIB check. Check register conflicts for (EVEX-encoded) gathers.
 597         Extend check for disallowed 16-bit addressing.
 598         (OP_VEX): New local variables modrm_reg and sib_index. Convert
 599         if()s to switch(). Check register conflicts for (VEX-encoded)
 600         gathers. Drop no longer reachable cases.
 601         * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
 602         vgatherdp*.
 603
 604 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 605
 606         * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
 607         zeroing-masking without masking.
 608
 609 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 610
 611         * i386-opc.tbl (invlpgb): Fix multi-operand form.
 612         (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
 613         single-operand forms as deprecated.
 614         * i386-tbl.h: Re-generate.
 615
 616 2021-03-25  Alan Modra  <amodra@gmail.com>
 617
 618         PR 27647
 619         * ppc-opc.c (XLOCB_MASK): Delete.
 620         (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
 621         XLBH_MASK.
 622         (powerpc_opcodes): Accept a BH field on all extended forms of
 623         bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
 624
 625 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 626
 627         * i386-gen.c (output_i386_opcode): Drop processing of
 628         opcode_length. Calculate length from base_opcode. Adjust prefix
 629         encoding determination.
 630         (process_i386_opcodes): Drop output of fake opcode_length.
 631         * i386-opc.h (struct insn_template): Drop opcode_length field.
 632         * i386-opc.tbl: Drop opcode length field from all templates.
 633         * i386-tbl.h: Re-generate.
 634
 635 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 636
 637         * i386-gen.c (process_i386_opcode_modifier): Return void. New
 638         parameter "prefix". Drop local variable "regular_encoding".
 639         Record prefix setting / check for consistency.
 640         (output_i386_opcode): Parse opcode_length and base_opcode
 641         earlier. Derive prefix encoding. Drop no longer applicable
 642         consistency checking. Adjust process_i386_opcode_modifier()
 643         invocation.
 644         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 645         invocation.
 646         * i386-tbl.h: Re-generate.
 647
 648 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 649
 650         * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
 651         check.
 652         * i386-opc.h (Prefix_*): Move #define-s.
 653         * i386-opc.tbl: Move pseudo prefix enumerator values to
 654         extension opcode field. Introduce pseudopfx template.
 655         * i386-tbl.h: Re-generate.
 656
 657 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 658
 659         * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
 660         comment.
 661         * i386-tbl.h: Re-generate.
 662
 663 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 664
 665         * i386-opc.h (struct insn_template): Move cpu_flags field past
 666         opcode_modifier one.
 667         * i386-tbl.h: Re-generate.
 668
 669 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 670
 671         * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
 672         * i386-opc.h (OpcodeSpace): New enumerator.
 673         (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
 674         (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
 675         SPACE_XOP09, SPACE_XOP0A): ... respectively.
 676         (struct i386_opcode_modifier): New field opcodespace. Shrink
 677         opcodeprefix field.
 678         i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
 679         SpaceXOP09, SpaceXOP0A): Define. Use them to replace
 680         OpcodePrefix uses.
 681         * i386-tbl.h: Re-generate.
 682
 683 2021-03-22  Martin Liska  <mliska@suse.cz>
 684
 685         * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
 686         * arc-dis.c (parse_option): Likewise.
 687         * arm-dis.c (parse_arm_disassembler_options): Likewise.
 688         * cris-dis.c (print_with_operands): Likewise.
 689         * h8300-dis.c (bfd_h8_disassemble): Likewise.
 690         * i386-dis.c (print_insn): Likewise.
 691         * ia64-gen.c (fetch_insn_class): Likewise.
 692         (parse_resource_users): Likewise.
 693         (in_iclass): Likewise.
 694         (lookup_specifier): Likewise.
 695         (insert_opcode_dependencies): Likewise.
 696         * mips-dis.c (parse_mips_ase_option): Likewise.
 697         (parse_mips_dis_option): Likewise.
 698         * s390-dis.c (disassemble_init_s390): Likewise.
 699         * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
 700
 701 2021-03-16  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
 702
 703         * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
 704
 705 2021-03-12  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 706
 707         * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
 708         icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
 709
 710 2021-03-12  Alan Modra  <amodra@gmail.com>
 711
 712         * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
 713
 714 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 715
 716         * i386-dis.c (OP_XMM): Re-order checks.
 717
 718 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 719
 720         * i386-dis.c (putop): Drop need_vex check when also checking
 721         vex.evex.
 722         (intel_operand_size, OP_E_memory): Drop vex.evex check when also
 723         checking vex.b.
 724
 725 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 726
 727         * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
 728         checks. Move case label past broadcast check.
 729
 730 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 731
 732         * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
 733         vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
 734         REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
 735         EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
 736         EVEX_W_0F38C7_M_0_L_2): Delete.
 737         (REG_EVEX_0F38C7_M_0_L_2): New.
 738         (intel_operand_size): Handle VEX and EVEX the same for
 739         vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
 740         vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
 741         (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
 742         vex_vsib_q_w_d_mode uses.
 743         * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
 744         0F38A1, and 0F38A3 entries.
 745         * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
 746         entry.
 747         * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
 748         * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
 749         0F38A3 entries.
 750
 751 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 752
 753         * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
 754         REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
 755         MOD_VEX_0FXOP_09_12): Rename to ...
 756         (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
 757         REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
 758         (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
 759         RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
 760         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 761         X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
 762         (reg_table): Adjust comments.
 763         (x86_64_table): Move X86_64_0F24, X86_64_0F26,
 764         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 765         X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
 766         (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
 767         (vex_len_table): Adjust opcode 0A_12 entry.
 768         (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
 769         MOD_C5_32BIT, and MOD_XOP_09_12 entries.
 770         (rm_table): Move hreset entry.
 771
 772 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 773
 774         * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
 775         EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
 776         EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
 777         EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
 778         EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
 779         (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
 780         (get_valid_dis386): Also handle 512-bit vector length when
 781         vectoring into vex_len_table[].
 782         * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
 783         0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
 784         entries.
 785         * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
 786         0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
 787         * i386-dis-evex-prefix.h: Adjust 0F7E entry.
 788         * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
 789         entries.
 790
 791 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 792
 793         * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
 794         Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
 795         EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
 796         * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
 797         entries.
 798         * i386-dis-evex-len.h (evex_len_table): Likewise.
 799         * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
 800
 801 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 802
 803         * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
 804         MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
 805         MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
 806         MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
 807         MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
 808         MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 809         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
 810         MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
 811         EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
 812         EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
 813         EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
 814         EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
 815         EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
 816         EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
 817         EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
 818         EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
 819         EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
 820         EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
 821         EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
 822         EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
 823         EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
 824         EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
 825         EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
 826         EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
 827         EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
 828         EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
 829         EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
 830         EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
 831         EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
 832         EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
 833         EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
 834         EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
 835         REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
 836         REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
 837         MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
 838         MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
 839         EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
 840         EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
 841         EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
 842         EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
 843         EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
 844         EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
 845         EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
 846         EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
 847         EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
 848         EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
 849         EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
 850         EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
 851         EVEX_W_0F3A43_L_n): New.
 852         * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
 853         0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
 854         0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
 855         * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
 856         for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
 857         0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
 858         0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
 859         * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
 860         0F385B, 0F38C6, and 0F38C7 entries.
 861         * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
 862         0F38C6 and 0F38C7.
 863         * i386-dis-evex-w.h: No longer link to evex_len_table[] for
 864         opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
 865         0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
 866         evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
 867
 868 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 869
 870         * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
 871         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 872         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 873         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 874         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 875         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 876         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 877         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 878         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 879         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 880         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 881         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 882         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 883         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 884         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 885         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 886         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 887         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 888         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 889         MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
 890         MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
 891         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 892         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 893         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 894         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 895         PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 896         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
 897         PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
 898         PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 899         PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
 900         VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
 901         VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
 902         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
 903         VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
 904         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
 905         VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
 906         VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
 907         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
 908         VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
 909         VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
 910         VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
 911         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
 912         VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
 913         VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
 914         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
 915         VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
 916         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
 917         VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
 918         VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
 919         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
 920         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
 921         VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
 922         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
 923         VEX_W_0F99_P_2_LEN_0): Delete.
 924         MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
 925         MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
 926         MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
 927         MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
 928         MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
 929         PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
 930         PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
 931         PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
 932         PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
 933         PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
 934         PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
 935         PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
 936         PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
 937         PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
 938         PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
 939         PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
 940         PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
 941         PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
 942         PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
 943         VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
 944         VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
 945         VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
 946         VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
 947         VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
 948         VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
 949         VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
 950         VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
 951         (prefix_table): No longer link to vex_len_table[] for opcodes
 952         0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
 953         0F92, 0F93, 0F98, and 0F99.
 954         (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
 955         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 956         0F98, and 0F99.
 957         (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
 958         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 959         0F98, and 0F99.
 960         (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
 961         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 962         0F98, and 0F99.
 963         (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
 964         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 965         0F98, and 0F99.
 966
 967 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 968
 969         * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
 970         Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
 971         REG_VEX_0F73_M_0 respectively.
 972         (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
 973         MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
 974         MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
 975         MOD_VEX_0F73_REG_7): Delete.
 976         (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
 977         (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
 978         PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
 979         PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
 980         PREFIX_VEX_0F3AF0_L_0 respectively.
 981         (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
 982         VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
 983         VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
 984         VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
 985         (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
 986         VEX_LEN_0F38F7): New.
 987         (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
 988         (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
 989         0F72, and 0F73. No longer link to vex_len_table[] for opcode
 990         0F38F3.
 991         (prefix_table): No longer link to vex_len_table[] for opcodes
 992         0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 993         (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
 994         0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
 995         0F38F6, 0F38F7, and 0F3AF0.
 996         (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
 997         prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 998         (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
 999         0F73.
1000
1001 2021-03-10  Jan Beulich  <jbeulich@suse.com>
1002
1003         * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
1004         REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
1005         (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
1006         MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
1007         MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
1008         (MOD_0F71, MOD_0F72, MOD_0F73): New.
1009         (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
1010         73.
1011         (reg_table): No longer link to mod_table[] for opcodes 0F71,
1012         0F72, and 0F73.
1013         (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
1014         0F73.
1015
1016 2021-03-10  Jan Beulich  <jbeulich@suse.com>
1017
1018         * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
1019         MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
1020         (reg_table): Don't link to mod_table[] where not needed. Add
1021         PREFIX_IGNORED to nop entries.
1022         (prefix_table): Replace PREFIX_OPCODE in nop entries.
1023         (mod_table): Add nop entries next to prefetch ones. Drop
1024         MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
1025         MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
1026         (rm_table): Add PREFIX_IGNORED to nop entries. Drop
1027         PREFIX_OPCODE from endbr* entries.
1028         (get_valid_dis386): Also consider entry's name when zapping
1029         vindex.
1030         (print_insn): Handle PREFIX_IGNORED.
1031
1032 2021-03-09  Jan Beulich  <jbeulich@suse.com>
1033
1034         * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
1035         IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
1036         element.
1037         * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
1038         HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
1039         (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
1040         PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
1041         (struct i386_opcode_modifier): Delete notrackprefixok,
1042         islockable, hleprefixok, and repprefixok fields. Add prefixok
1043         field.
1044         * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
1045         HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
1046         (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
1047         not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
1048         Replace HLEPrefixOk.
1049         * opcodes/i386-tbl.h: Re-generate.
1050
1051 2021-03-09  Jan Beulich  <jbeulich@suse.com>
1052
1053         * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
1054         * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
1055         64-bit form.
1056         * opcodes/i386-tbl.h: Re-generate.
1057
1058 2021-03-03  Jan Beulich  <jbeulich@suse.com>
1059
1060         * i386-gen.c (output_i386_opcode): Don't get operand count. Look
1061         for {} instead of {0}. Don't look for '0'.
1062         * i386-opc.tbl: Drop operand count field. Drop redundant operand
1063         size specifiers.
1064
1065 2021-02-19  Nelson Chu  <nelson.chu@sifive.com>
1066
1067         PR 27158
1068         * riscv-dis.c (print_insn_args): Updated encoding macros.
1069         * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
1070         (match_c_addi16sp): Updated encoding macros.
1071         (match_c_lui): Likewise.
1072         (match_c_lui_with_hint): Likewise.
1073         (match_c_addi4spn): Likewise.
1074         (match_c_slli): Likewise.
1075         (match_slli_as_c_slli): Likewise.
1076         (match_c_slli64): Likewise.
1077         (match_srxi_as_c_srxi): Likewise.
1078         (riscv_insn_types): Added .insn css/cl/cs.
1079
1080 2021-02-18  Nelson Chu  <nelson.chu@sifive.com>
1081
1082         * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
1083         (default_priv_spec): Updated type to riscv_spec_class.
1084         (parse_riscv_dis_option): Updated.
1085         * riscv-opc.c: Moved stuff and make the file tidy.
1086
1087 2021-02-17  Alan Modra  <amodra@gmail.com>
1088
1089         * wasm32-dis.c: Include limits.h.
1090         (CHAR_BIT): Provide backup define.
1091         (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
1092         Correct signed overflow checking.
1093
1094 2021-02-16  Jan Beulich  <jbeulich@suse.com>
1095
1096         * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
1097         * i386-tbl.h: Re-generate.
1098
1099 2021-02-16  Jan Beulich  <jbeulich@suse.com>
1100
1101         * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
1102         Oword.
1103         * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
1104
1105 2021-02-15  Andreas Krebbel  <krebbel@linux.ibm.com>
1106
1107         * s390-mkopc.c (main): Accept arch14 as cpu string.
1108         * s390-opc.txt: Add new arch14 instructions.
1109
1110 2021-02-04  Nick Alcock  <nick.alcock@oracle.com>
1111
1112         * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
1113         favour of LIBINTL.
1114         * configure: Regenerated.
1115
1116 2021-02-08  Mike Frysinger  <vapier@gentoo.org>
1117
1118         * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
1119         * tic54x-opc.c (regs): Rename to ...
1120         (tic54x_regs): ... this.
1121         (mmregs): Rename to ...
1122         (tic54x_mmregs): ... this.
1123         (condition_codes): Rename to ...
1124         (tic54x_condition_codes): ... this.
1125         (cc2_codes): Rename to ...
1126         (tic54x_cc2_codes): ... this.
1127         (cc3_codes): Rename to ...
1128         (tic54x_cc3_codes): ... this.
1129         (status_bits): Rename to ...
1130         (tic54x_status_bits): ... this.
1131         (misc_symbols): Rename to ...
1132         (tic54x_misc_symbols): ... this.
1133
1134 2021-02-04  Nelson Chu  <nelson.chu@sifive.com>
1135
1136         * riscv-opc.c (MASK_RVB_IMM): Removed.
1137         (riscv_opcodes): Removed zb* instructions.
1138         (riscv_ext_version_table): Removed versions for zb*.
1139
1140 2021-01-26  Alan Modra  <amodra@gmail.com>
1141
1142         * i386-gen.c (parse_template): Ensure entire template_instance
1143         is initialised.
1144
1145 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
1146
1147         * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
1148         (riscv_fpr_names_abi): Likewise.
1149         (riscv_opcodes): Likewise.
1150         (riscv_insn_types): Likewise.
1151
1152 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
1153
1154         * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
1155
1156 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
1157
1158         * riscv-dis.c: Comments tidy and improvement.
1159         * riscv-opc.c: Likewise.
1160
1161 2021-01-13  Alan Modra  <amodra@gmail.com>
1162
1163         * Makefile.in: Regenerate.
1164
1165 2021-01-12  H.J. Lu  <hongjiu.lu@intel.com>
1166
1167         PR binutils/26792
1168         * configure.ac: Use GNU_MAKE_JOBSERVER.
1169         * aclocal.m4: Regenerated.
1170         * configure: Likewise.
1171
1172 2021-01-12  Nick Clifton  <nickc@redhat.com>
1173
1174         * po/sr.po: Updated Serbian translation.
1175
1176 2021-01-11  H.J. Lu  <hongjiu.lu@intel.com>
1177
1178         PR ld/27173
1179         * configure: Regenerated.
1180
1181 2021-01-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
1182
1183         * aarch64-asm-2.c: Regenerate.
1184         * aarch64-dis-2.c: Likewise.
1185         * aarch64-opc-2.c: Likewise.
1186         * aarch64-opc.c (aarch64_print_operand):
1187         Delete handling of AARCH64_OPND_CSRE_CSR.
1188         * aarch64-tbl.h (aarch64_feature_csre): Delete.
1189         (CSRE): Likewise.
1190         (_CSRE_INSN): Likewise.
1191         (aarch64_opcode_table): Delete csr.
1192
1193 2021-01-11  Nick Clifton  <nickc@redhat.com>
1194
1195         * po/de.po: Updated German translation.
1196         * po/fr.po: Updated French translation.
1197         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1198         * po/sv.po: Updated Swedish translation.
1199         * po/uk.po: Updated Ukranian translation.
1200
1201 2021-01-09  H.J. Lu  <hongjiu.lu@intel.com>
1202
1203         * configure: Regenerated.
1204
1205 2021-01-09  Nick Clifton  <nickc@redhat.com>
1206
1207         * configure: Regenerate.
1208         * po/opcodes.pot: Regenerate.
1209
1210 2021-01-09  Nick Clifton  <nickc@redhat.com>
1211
1212         * 2.36 release branch crated.
1213
1214 2021-01-08  Peter Bergner  <bergner@linux.ibm.com>
1215
1216         * ppc-opc.c (insert_dw, (extract_dw): New functions.
1217         (DW, (XRC_MASK): Define.
1218         (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
1219
1220 2021-01-09  Alan Modra  <amodra@gmail.com>
1221
1222         * configure: Regenerate.
1223
1224 2021-01-08  Nick Clifton  <nickc@redhat.com>
1225
1226         * po/sv.po: Updated Swedish translation.
1227
1228 2021-01-08  Nick Clifton  <nickc@redhat.com>
1229
1230         PR 27129
1231         * aarch64-dis.c (determine_disassembling_preference): Move call to
1232         aarch64_match_operands_constraint outside of the assertion.
1233         * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
1234         Replace with a return of FALSE.
1235
1236         PR 27139
1237         * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
1238         core system register.
1239
1240 2021-01-07  Samuel Thibault  <samuel.thibault@gnu.org>
1241
1242         * configure: Regenerate.
1243
1244 2021-01-07  Nick Clifton  <nickc@redhat.com>
1245
1246         * po/fr.po: Updated French translation.
1247
1248 2021-01-07  Fredrik Noring  <noring@nocrew.org>
1249
1250         * m68k-opc.c (chkl): Change minimum architecture requirement to
1251         m68020.
1252
1253 2021-01-07  Philipp Tomsich  <prt@gnu.org>
1254
1255         * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
1256
1257 2021-01-07  Claire Xenia Wolf  <claire@symbioticeda.com>
1258             Jim Wilson  <jimw@sifive.com>
1259             Andrew Waterman  <andrew@sifive.com>
1260             Maxim Blinov  <maxim.blinov@embecosm.com>
1261             Kito Cheng  <kito.cheng@sifive.com>
1262             Nelson Chu  <nelson.chu@sifive.com>
1263
1264         * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
1265         (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
1266
1267 2021-01-01  Alan Modra  <amodra@gmail.com>
1268
1269         Update year range in copyright notice of all files.
1270
1271 For older changes see ChangeLog-2020
1272 \f
1273 Copyright (C) 2021-2022 Free Software Foundation, Inc.
1274
1275 Copying and distribution of this file, with or without modification,
1276 are permitted in any medium without royalty provided the copyright
1277 notice and this notice are preserved.
1278
1279 Local Variables:
1280 mode: change-log
1281 left-margin: 8
1282 fill-column: 74
1283 version-control: never
1284 End: