opcodes/ChangeLog

   1 2015-06-01  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-tbl.h: Regenerate.
   4
   5 2015-06-01  Jan Beulich  <jbeulich@suse.com>
   6
   7         * i386-dis.c (print_insn): Swap rounding mode specifier and
   8         general purpose register in Intel mode.
   9
  10 2015-06-01  Jan Beulich  <jbeulich@suse.com>
  11
  12         * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
  13         * i386-tbl.h: Regenerate.
  14
  15 2015-05-18  H.J. Lu  <hongjiu.lu@intel.com>
  16
  17         * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
  18         * i386-init.h: Regenerated.
  19
  20 2015-05-15  H.J. Lu  <hongjiu.lu@intel.com>
  21
  22         PR binutis/18386
  23         * i386-dis.c: Add comments for '@'.
  24         (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
  25         (enum x86_64_isa): New.
  26         (isa64): Likewise.
  27         (print_i386_disassembler_options): Add amd64 and intel64.
  28         (print_insn): Handle amd64 and intel64.
  29         (putop): Handle '@'.
  30         (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
  31         * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
  32         * i386-opc.h (AMD64): New.
  33         (CpuIntel64): Likewise.
  34         (i386_cpu_flags): Add cpuamd64 and cpuintel64.
  35         * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
  36         Mark direct call/jmp without Disp16|Disp32 as Intel64.
  37         * i386-init.h: Regenerated.
  38         * i386-tbl.h: Likewise.
  39
  40 2015-05-14  Peter Bergner  <bergner@vnet.ibm.com>
  41
  42         * ppc-opc.c (IH) New define.
  43         (powerpc_opcodes) <wait>: Do not enable for POWER7.
  44         <tlbie>: Add RS operand for POWER7.
  45         <slbia>: Add IH operand for POWER6.
  46
  47 2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>
  48
  49         * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
  50         direct branch.
  51         (jmp): Likewise.
  52         * i386-tbl.h: Regenerated.
  53
  54 2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>
  55
  56         * configure.ac: Support bfd_iamcu_arch.
  57         * disassemble.c (disassembler): Support bfd_iamcu_arch.
  58         * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
  59         CPU_IAMCU_COMPAT_FLAGS.
  60         (cpu_flags): Add CpuIAMCU.
  61         * i386-opc.h (CpuIAMCU): New.
  62         (i386_cpu_flags): Add cpuiamcu.
  63         * configure: Regenerated.
  64         * i386-init.h: Likewise.
  65         * i386-tbl.h: Likewise.
  66
  67 2015-05-08  H.J. Lu  <hongjiu.lu@intel.com>
  68
  69         PR binutis/18386
  70         * i386-dis.c (X86_64_E8): New.
  71         (X86_64_E9): Likewise.
  72         Update comments on 'T', 'U', 'V'.  Add comments for '^'.
  73         (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
  74         (x86_64_table): Add X86_64_E8 and X86_64_E9.
  75         (mod_table): Replace {T|} with ^ on Jcall/Jmp.
  76         (putop): Handle '^'.
  77         (OP_J): Ignore the operand size prefix in 64-bit.  Don't check
  78         REX_W.
  79
  80 2015-04-30  DJ Delorie  <dj@redhat.com>
  81
  82         * disassemble.c (disassembler): Choose suitable disassembler based
  83         on E_ABI.
  84         * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter.  Use
  85         it to decode mul/div insns.
  86         * rl78-decode.c: Regenerate.
  87         * rl78-dis.c (print_insn_rl78): Rename to...
  88         (print_insn_rl78_common): ...this, take ISA parameter.
  89         (print_insn_rl78): New.
  90         (print_insn_rl78_g10): New.
  91         (print_insn_rl78_g13): New.
  92         (print_insn_rl78_g14): New.
  93         (rl78_get_disassembler): New.
  94
  95 2015-04-29  Nick Clifton  <nickc@redhat.com>
  96
  97         * po/fr.po: Updated French translation.
  98
  99 2015-04-27  Peter Bergner  <bergner@vnet.ibm.com>
 100
 101         * ppc-opc.c (DCBT_EO): New define.
 102         (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
 103         <lharx>: Likewise.
 104         <stbcx.>: Likewise.
 105         <sthcx.>: Likewise.
 106         <waitrsv>: Do not enable for POWER7 and later.
 107         <waitimpl>: Likewise.
 108         <dcbt>: Default to the two operand form of the instruction for all
 109         "old" cpus.  For "new" cpus, use the operand ordering that matches
 110         whether the cpu is server or embedded.
 111         <dcbtst>: Likewise.
 112
 113 2015-04-27  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 114
 115         * s390-opc.c: New instruction type VV0UU2.
 116         * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
 117         and WFC.
 118
 119 2015-04-23  Jan Beulich  <jbeulich@suse.com>
 120
 121         * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
 122         * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
 123         vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
 124         (vfpclasspd, vfpclassps): Add %XZ.
 125
 126 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 127
 128         * i386-dis.c (PREFIX_UD_SHIFT): Removed.
 129         (PREFIX_UD_REPZ): Likewise.
 130         (PREFIX_UD_REPNZ): Likewise.
 131         (PREFIX_UD_DATA): Likewise.
 132         (PREFIX_UD_ADDR): Likewise.
 133         (PREFIX_UD_LOCK): Likewise.
 134
 135 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 136
 137         * i386-dis.c (prefix_requirement): Removed.
 138         (print_insn): Don't set prefix_requirement.  Check
 139         dp->prefix_requirement instead of prefix_requirement.
 140
 141 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 142
 143         PR binutils/17898
 144         * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
 145         (PREFIX_MOD_0_0FC7_REG_6): This.
 146         (PREFIX_MOD_3_0FC7_REG_6): New.
 147         (PREFIX_MOD_3_0FC7_REG_7): Likewise.
 148         (prefix_table): Replace PREFIX_0FC7_REG_6 with
 149         PREFIX_MOD_0_0FC7_REG_6.  Add PREFIX_MOD_3_0FC7_REG_6 and
 150         PREFIX_MOD_3_0FC7_REG_7.
 151         (mod_table): Replace PREFIX_0FC7_REG_6 with
 152         PREFIX_MOD_0_0FC7_REG_6.  Use PREFIX_MOD_3_0FC7_REG_6 and
 153         PREFIX_MOD_3_0FC7_REG_7.
 154
 155 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 156
 157         * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
 158         (PREFIX_MANDATORY_REPNZ): Likewise.
 159         (PREFIX_MANDATORY_DATA): Likewise.
 160         (PREFIX_MANDATORY_ADDR): Likewise.
 161         (PREFIX_MANDATORY_LOCK): Likewise.
 162         (PREFIX_MANDATORY): Likewise.
 163         (PREFIX_UD_SHIFT): Set to 8
 164         (PREFIX_UD_REPZ): Updated.
 165         (PREFIX_UD_REPNZ): Likewise.
 166         (PREFIX_UD_DATA): Likewise.
 167         (PREFIX_UD_ADDR): Likewise.
 168         (PREFIX_UD_LOCK): Likewise.
 169         (PREFIX_IGNORED_SHIFT): New.
 170         (PREFIX_IGNORED_REPZ): Likewise.
 171         (PREFIX_IGNORED_REPNZ): Likewise.
 172         (PREFIX_IGNORED_DATA): Likewise.
 173         (PREFIX_IGNORED_ADDR): Likewise.
 174         (PREFIX_IGNORED_LOCK): Likewise.
 175         (PREFIX_OPCODE): Likewise.
 176         (PREFIX_IGNORED): Likewise.
 177         (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
 178         (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
 179         (three_byte_table): Likewise.
 180         (mod_table): Likewise.
 181         (mandatory_prefix): Renamed to ...
 182         (prefix_requirement): This.
 183         (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
 184         Update PREFIX_90 entry.
 185         (get_valid_dis386): Check prefix_requirement to see if a prefix
 186         should be ignored.
 187         (print_insn): Replace mandatory_prefix with prefix_requirement.
 188
 189 2015-04-15  Renlin Li  <renlin.li@arm.com>
 190
 191         * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
 192         use it for ssat and ssat16.
 193         (print_insn_thumb32): Add handle case for 'D' control code.
 194
 195 2015-04-06  Ilya Tocar  <ilya.tocar@intel.com>
 196             H.J. Lu  <hongjiu.lu@intel.com>
 197
 198         * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
 199         * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
 200         PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
 201         PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
 202         PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
 203         (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
 204         Fill prefix_requirement field.
 205         (struct dis386): Add prefix_requirement field.
 206         (dis386): Fill prefix_requirement field.
 207         (dis386_twobyte): Ditto.
 208         (twobyte_has_mandatory_prefix_: Remove.
 209         (reg_table): Fill prefix_requirement field.
 210         (prefix_table): Ditto.
 211         (x86_64_table): Ditto.
 212         (three_byte_table): Ditto.
 213         (xop_table): Ditto.
 214         (vex_table): Ditto.
 215         (vex_len_table): Ditto.
 216         (vex_w_table): Ditto.
 217         (mod_table): Ditto.
 218         (bad_opcode): Ditto.
 219         (print_insn): Use prefix_requirement.
 220         (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
 221         FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
 222         (float_reg): Ditto.
 223
 224 2015-03-30  Mike Frysinger  <vapier@gentoo.org>
 225
 226         * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
 227
 228 2015-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 229
 230         * Makefile.in: Regenerated.
 231
 232 2015-03-25  Anton Blanchard  <anton@samba.org>
 233
 234         * ppc-dis.c (disassemble_init_powerpc): Only initialise
 235         powerpc_opcd_indices and vle_opcd_indices once.
 236
 237 2015-03-25  Anton Blanchard  <anton@samba.org>
 238
 239         * ppc-opc.c (powerpc_opcodes): Add slbfee.
 240
 241 2015-03-24  Terry Guo  <terry.guo@arm.com>
 242
 243         * arm-dis.c (opcode32): Updated to use new arm feature struct.
 244         (opcode16): Likewise.
 245         (coprocessor_opcodes): Replace bit with feature struct.
 246         (neon_opcodes): Likewise.
 247         (arm_opcodes): Likewise.
 248         (thumb_opcodes): Likewise.
 249         (thumb32_opcodes): Likewise.
 250         (print_insn_coprocessor): Likewise.
 251         (print_insn_arm): Likewise.
 252         (select_arm_features): Follow new feature struct.
 253
 254 2015-03-17  Ganesh Gopalasubramanian  <Ganesh.Gopalasubramanian@amd.com>
 255
 256         * i386-dis.c (rm_table): Add clzero.
 257         * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
 258         Add CPU_CLZERO_FLAGS.
 259         (cpu_flags): Add CpuCLZERO.
 260         * i386-opc.h: Add CpuCLZERO.
 261         * i386-opc.tbl: Add clzero.
 262         * i386-init.h: Re-generated.
 263         * i386-tbl.h: Re-generated.
 264
 265 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
 266
 267         * mips-opc.c (decode_mips_operand): Fix constraint issues
 268         with u and y operands.
 269
 270 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
 271
 272         * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
 273
 274 2015-03-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 275
 276         * s390-opc.c: Add new IBM z13 instructions.
 277         * s390-opc.txt: Likewise.
 278
 279 2015-03-10  Renlin Li  <renlin.li@arm.com>
 280
 281         * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
 282         stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
 283         related alias.
 284         * aarch64-asm-2.c: Regenerate.
 285         * aarch64-dis-2.c: Likewise.
 286         * aarch64-opc-2.c: Likewise.
 287
 288 2015-03-03  Jiong Wang  <jiong.wang@arm.com>
 289
 290         * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
 291
 292 2015-02-25  Oleg Endo  <olegendo@gcc.gnu.org>
 293
 294         * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
 295         arch_sh_up.
 296         (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
 297         arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
 298
 299 2015-02-23  Vinay  <Vinay.G@kpit.com>
 300
 301         * rl78-decode.opc (MOV): Added space between two operands for
 302         'mov' instruction in index addressing mode.
 303         * rl78-decode.c: Regenerate.
 304
 305 2015-02-19  Pedro Alves  <palves@redhat.com>
 306
 307         * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
 308
 309 2015-02-10  Pedro Alves  <palves@redhat.com>
 310             Tom Tromey  <tromey@redhat.com>
 311
 312         * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
 313         microblaze_and, microblaze_xor.
 314         * microblaze-opc.h (opcodes): Adjust.
 315
 316 2015-01-28  James Bowman  <james.bowman@ftdichip.com>
 317
 318         * Makefile.am: Add FT32 files.
 319         * configure.ac: Handle FT32.
 320         * disassemble.c (disassembler): Call print_insn_ft32.
 321         * ft32-dis.c: New file.
 322         * ft32-opc.c: New file.
 323         * Makefile.in: Regenerate.
 324         * configure: Regenerate.
 325         * po/POTFILES.in: Regenerate.
 326
 327 2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
 328
 329         * nds32-asm.c (keyword_sr): Add new system registers.
 330
 331 2015-01-16  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 332
 333         * s390-dis.c (s390_extract_operand): Support vector register
 334         operands.
 335         (s390_print_insn_with_opcode): Support new operands types and add
 336         new handling of optional operands.
 337         * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
 338         and include opcode/s390.h instead.
 339         (struct op_struct): New field `flags'.
 340         (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
 341         (dumpTable): Dump flags.
 342         (main): Parse flags from the s390-opc.txt file.  Add z13 as cpu
 343         string.
 344         * s390-opc.c: Add new operands types, instruction formats, and
 345         instruction masks.
 346         (s390_opformats): Add new formats for .insn.
 347         * s390-opc.txt: Add new instructions.
 348
 349 2015-01-01  Alan Modra  <amodra@gmail.com>
 350
 351         Update year range in copyright notice of all files.
 352
 353 For older changes see ChangeLog-2014
 354 \f
 355 Copyright (C) 2015 Free Software Foundation, Inc.
 356
 357 Copying and distribution of this file, with or without modification,
 358 are permitted in any medium without royalty provided the copyright
 359 notice and this notice are preserved.
 360
 361 Local Variables:
 362 mode: change-log
 363 left-margin: 8
 364 fill-column: 74
 365 version-control: never
 366 End: