opcodes/ChangeLog

   1 2014-11-28  Sandra Loosemore  <sandra@codesourcery.com>
   2
   3         * nios2-opc.c (nios2_r1_opcodes): Remove deleted attributes
   4         from descriptors.
   5
   6 2014-11-28  Alan Modra  <amodra@gmail.com>
   7
   8         * ppc-opc.c (powerpc_opcodes <mftb>): Don't deprecate for power7.
   9         (TB): Delete.
  10         (insert_tbr, extract_tbr): Validate tbr number.
  11
  12 2014-11-24  H.J. Lu  <hongjiu.lu@intel.com>
  13
  14         * configure: Regenerated.
  15
  16 2014-11-17  Ilya Tocar  <ilya.tocar@intel.com>
  17
  18         * i386-dis-evex.c (evex_table): Add vpermi2b, vpermt2b, vpermb,
  19         vpmultishiftqb.
  20         * i386-dis.c (PREFIX enum): Add PREFIX_EVEX_0F3883, EVEX_W_0F3883_P_2.
  21         * i386-gen.c (cpu_flag_init): Add CPU_AVX512VBMI_FLAGS.
  22         (cpu_flags): Add CpuAVX512VBMI.
  23         * i386-opc.h (enum): Add CpuAVX512VBMI.
  24         (i386_cpu_flags): Add cpuavx512vbmi.
  25         * i386-opc.tbl: Add vpmadd52luq, vpmultishiftqb, vpermb, vpermi2b,
  26         vpermt2b.
  27         * i386-init.h: Regenerated.
  28         * i386-tbl.h: Likewise.
  29
  30 2014-11-17  Ilya Tocar  <ilya.tocar@intel.com>
  31
  32         * i386-dis-evex.c (evex_table): Add vpmadd52luq, vpmadd52huq.
  33         * i386-dis.c (PREFIX enum): Add PREFIX_EVEX_0F38B4,
  34         PREFIX_EVEX_0F38B5.
  35         * i386-gen.c (cpu_flag_init): Add CPU_AVX512IFMA_FLAGS.
  36         (cpu_flags): Add CpuAVX512IFMA.
  37         * i386-opc.h (enum): Add CpuAVX512IFMA.
  38         (i386_cpu_flags): Add cpuavx512ifma.
  39         * i386-opc.tbl: Add vpmadd52huq, vpmadd52luq.
  40         * i386-init.h: Regenerated.
  41         * i386-tbl.h: Likewise.
  42
  43 2014-11-17  Ilya Tocar  <ilya.tocar@intel.com>
  44
  45         * i386-dis.c (PREFIX enum): Add PREFIX_RM_0_0FAE_REG_7.
  46         (prefix_table): Add pcommit.
  47         * i386-gen.c (cpu_flag_init): Add CPU_PCOMMIT_FLAGS.
  48         (cpu_flags): Add CpuPCOMMIT.
  49         * i386-opc.h (enum): Add CpuPCOMMIT.
  50         (i386_cpu_flags): Add cpupcommit.
  51         * i386-opc.tbl: Add pcommit.
  52         * i386-init.h: Regenerated.
  53         * i386-tbl.h: Likewise.
  54
  55 2014-11-17  Ilya Tocar  <ilya.tocar@intel.com>
  56
  57         * i386-dis.c (PREFIX enum): Add PREFIX_0FAE_REG_6.
  58         (prefix_table): Add clwb.
  59         * i386-gen.c (cpu_flag_init): Add CPU_CLWB_FLAGS.
  60         (cpu_flags): Add CpuCLWB.
  61         * i386-opc.h (enum): Add CpuCLWB.
  62         (i386_cpu_flags): Add cpuclwb.
  63         * i386-opc.tbl: Add clwb.
  64         * i386-init.h: Regenerated.
  65         * i386-tbl.h: Likewise.
  66
  67 2014-11-06  Sandra Loosemore  <sandra@codesourcery.com>
  68
  69         * nios2-dis.c (nios2_find_opcode_hash): Add mach parameter.
  70         (nios2_disassemble): Adjust call to nios2_find_opcode_hash.
  71
  72 2014-11-03  Nick Clifton  <nickc@redhat.com>
  73
  74         * po/fi.po: Updated Finnish translation.
  75
  76 2014-10-31  Andrew Pinski  <apinski@cavium.com>
  77             Naveen H.S  <Naveen.Hurugalawadi@caviumnetworks.com>
  78
  79         * mips-dis.c (mips_arch_choices): Add octeon3.
  80         * mips-opc.c (IOCT): Include INSN_OCTEON3.
  81         (IOCT2): Likewise.
  82         (IOCT3): New define.
  83         (IVIRT): New define.
  84         (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
  85         tlbinv, tlbinvf, tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp, tlti
  86         IVIRT instructions.
  87         Extend mtm0, mtm1, mtm2, mtp0, mtp1, mtp2 instructions to take another
  88         operand for IOCT3.
  89
  90 2014-10-29  Nick Clifton  <nickc@redhat.com>
  91
  92         * po/de.po: Updated German translation.
  93
  94 2014-10-23  Sandra Loosemore  <sandra@codesourcery.com>
  95
  96         * nios2-opc.c (nios2_builtin_regs): Add regtype field initializers.
  97         (nios2_builtin_opcodes): Rename to nios2_r1_opcodes.  Use new
  98         MATCH_R1_<insn> and MASK_R1_<insn> macros in initializers.  Add
  99         size and format initializers.  Merge 'b' arguments into 'j'.
 100         (NIOS2_NUM_OPCODES): Adjust definition.
 101         (bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
 102         (nios2_opcodes): Adjust.
 103         (bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
 104         * nios2-dis.c (INSNLEN): Update comment.
 105         (nios2_hash_init, nios2_hash): Delete.
 106         (OPCODE_HASH_SIZE): New.
 107         (nios2_r1_extract_opcode): New.
 108         (nios2_disassembler_state): New.
 109         (nios2_r1_disassembler_state): New.
 110         (nios2_init_opcode_hash): Add state parameter.  Adjust to use it.
 111         (nios2_find_opcode_hash): Use state object.
 112         (bad_opcode): New.
 113         (nios2_print_insn_arg): Add op parameter.  Use it to access
 114         format.  Remove 'b' case.
 115         (nios2_disassemble): Remove special case for nop.  Remove
 116         hard-coded instruction size.
 117
 118 2014-10-21  Jan Beulich  <jbeulich@suse.com>
 119
 120         * ppc-opc.c (powerpc_opcodes): Enable msgclr and msgsnd on Power8.
 121
 122 2014-10-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 123
 124         * sparc-opc.c (sparc-opcodes): Fix several misplaced hwcap
 125         entries.
 126         Annotate several instructions with the HWCAP2_VIS3B hwcap.
 127
 128 2014-10-15  Tristan Gingold  <gingold@adacore.com>
 129
 130         * configure: Regenerate.
 131
 132 2014-10-09  Jose E. Marchesi  &lt;jose.marchesi@oracle.com&gt;
 133
 134         * sparc-opc.c (sparc-opcodes): Remove instructions `chkpt',
 135         `commit', `random', `wr r,r,%cps', `wr r,i,%cps' and `rd %cps,r'.
 136         Annotate table with HWCAP2 bits.
 137         Add instructions xmontmul, xmontsqr, xmpmul.
 138         (sparc-opcodes): Add the `mwait',  `wr r,r,%mwait', `wr
 139         r,i,%mwait' and `rd %mwait,r' instructions.
 140         Add rd/wr instructions for accessing the %mcdper ancillary state
 141         register.
 142         (sparc-opcodes): Add sparc5/vis4.0 instructions:
 143         subxc, subxccc, fpadd8, fpadds8, fpaddus8, fpaddus16, fpcmple8,
 144         fpcmpgt8, fpcmpule16, fpcmpugt16, fpcmpule32, fpcmpugt32, fpmax8,
 145         fpmax16, fpmax32, fpmaxu8, fpmaxu16, fpmaxu32, fpmin8, fpmin16,
 146         fpmin32, fpminu8, fpminu16, fpminu32, fpsub8, fpsubs8, fpsubus8,
 147         fpsubus16, and faligndatai.
 148         * sparc-dis.c (v9a_asr_reg_names): Add the %mwait (%asr28)
 149         ancillary state register to the table.
 150         (print_insn_sparc): Handle the %mcdper ancillary state register.
 151         (print_insn_sparc): Handle new operand type '}'.
 152
 153 2014-09-22  H.J. Lu  <hongjiu.lu@intel.com>
 154
 155         * i386-dis.c (MOD_0F20): Removed.
 156         (MOD_0F21): Likewise.
 157         (MOD_0F22): Likewise.
 158         (MOD_0F23): Likewise.
 159         (dis386_twobyte): Replace MOD_0F20, MOD_0F21, MOD_0F22 and
 160         MOD_0F23 with "movZ".
 161         (mod_table): Remove MOD_0F20, MOD_0F21, MOD_0F22 and MOD_0F23.
 162         (OP_R): Check mod/rm byte and call OP_E_register.
 163
 164 2014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
 165
 166         * nds32-asm.c (nds32_opcodes, operand_fields, keyword_im5_i,
 167         keyword_im5_m, keyword_accumulator, keyword_aridx, keyword_aridx2,
 168         keyword_aridxi): Add audio ISA extension.
 169         (keyword_gpr, keyword_usr, keyword_sr, keyword_cp, keyword_cpr,
 170         keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm, keyword_dpref_st,
 171         keyword_cctl_lv, keyword_standby_st, keyword_msync_st): Adjust scrope
 172         for nds32-dis.c using.
 173         (build_opcode_syntax): Remove dead code.
 174         (parse_re, parse_a30b20, parse_rt21, parse_rte_start, parse_rte_end,
 175         parse_rte69_start, parse_rte69_end, parse_im5_ip, parse_im5_mr,
 176         parse_im6_ip, parse_im6_iq, parse_im6_mr, parse_im6_ms): Add audio ISA
 177         operand parser.
 178         * nds32-asm.h: Declare.
 179         * nds32-dis.c: Use array nds32_opcodes to disassemble instead of
 180         decoding by switch.
 181
 182 2014-09-15  Andrew Bennett  <andrew.bennett@imgtec.com>
 183             Matthew Fortune  <matthew.fortune@imgtec.com>
 184
 185         * mips-dis.c (mips_arch_choices): Add entries for mips32r6 and
 186         mips64r6.
 187         (parse_mips_dis_option): Allow MSA and virtualization support for
 188         mips64r6.
 189         (mips_print_arg_state): Add fields dest_regno and seen_dest.
 190         (mips_seen_register): New function.
 191         (print_insn_arg): Refactored code to use mips_seen_register
 192         function.  Add support for OP_SAME_RS_RT, OP_CHECK_PREV and
 193         OP_NON_ZERO_REG.  Changed OP_REPEAT_DEST_REG case to print out
 194         the register rather than aborting.
 195         (print_insn_args): Add length argument.  Add code to correctly
 196         calculate the instruction address for pc relative instructions.
 197         (validate_insn_args): New static function.
 198         (print_insn_mips): Prevent jalx disassembling for r6.  Use
 199         validate_insn_args.
 200         (print_insn_micromips): Use validate_insn_args.
 201         all the arguments are valid.
 202         * mips-formats.h (PREV_CHECK): New define.
 203         * mips-opc.c (decode_mips_operand): Add support for -a, -b, -d, -s,
 204         -t, -u, -v, -w, -x, -y, -A, -B, +I, +O, +R, +:, +\, +", +;
 205         (RD_pc): New define.
 206         (FS): New define.
 207         (I37): New define.
 208         (I69): New define.
 209         (mips_builtin_opcodes): Add MIPS R6 instructions.  Exclude recoded
 210         MIPS R6 instructions from MIPS R2 instructions.
 211
 212 2014-09-10  H.J. Lu  <hongjiu.lu@intel.com>
 213
 214         * i386-dis.c (dis386): Replace "P" with "%LP" for iret and sysret.
 215         (putop): Handle "%LP".
 216
 217 2014-09-03  Jiong Wang  <jiong.wang@arm.com>
 218
 219         * aarch64-tbl.h (aarch64_opcode_table): Update encoding for mrs/msr.
 220         * aarch64-dis-2.c: Update auto-generated file.
 221
 222 2014-09-03  Jiong Wang  <jiong.wang@arm.com>
 223
 224         * aarch64-tbl.h (QL_R4NIL): New qualifiers.
 225         (aarch64_feature_lse): New feature added.
 226         (LSE): New Added.
 227         (aarch64_opcode_table): New LSE instructions added.  Improve
 228         descriptions for ldarb/ldarh/ldar.
 229         (aarch64_opcode_table): Describe PAIRREG.
 230         * aarch64-opc.h (aarch64_field_kind): Add FLD_lse_sz.
 231         * aarch64-opc.c (fields): Add entry for F_LSE_SZ.
 232         (aarch64_print_operand): Recognize PAIRREG.
 233         (operand_general_constraint_met_p): Check reg pair constraints for CASP
 234         instructions.
 235         * aarch64-dis.c (aarch64_ext_regno_pair): New extractor for paired reg.
 236         (do_special_decoding): Recognize F_LSE_SZ.
 237         * aarch64-asm.c (do_special_encoding): Recognize F_LSE_SZ.
 238
 239 2014-08-26  Maciej W. Rozycki  <macro@codesourcery.com>
 240
 241         * micromips-opc.c (decode_micromips_operand): Rename `B' to `+J'.
 242         (micromips_opcodes): Use "+J" in place of "B" for "hypcall",
 243         "sdbbp", "syscall" and "wait".
 244
 245 2014-08-21  Nathan Sidwell  <nathan@codesourcery.com>
 246             Maciej W. Rozycki  <macro@codesourcery.com>
 247
 248         * arm-dis.c (print_arm_address): Negate the GPR-relative offset
 249         returned if the U bit is set.
 250
 251 2014-08-21  Maciej W. Rozycki  <macro@codesourcery.com>
 252
 253         * micromips-opc.c (micromips_opcodes): Remove #ifdef-ed out
 254         48-bit "li" encoding.
 255
 256 2014-08-19  Andreas Arnez  <arnez@linux.vnet.ibm.com>
 257
 258         * s390-dis.c (s390_insn_length, s390_insn_matches_opcode)
 259         (s390_print_insn_with_opcode, opcode_mask_more_specific): New
 260         static functions, code was moved from...
 261         (print_insn_s390): ...here.
 262         (s390_extract_operand): Adjust comment.  Change type of first
 263         parameter from 'unsigned char *' to 'const bfd_byte *'.
 264         (union operand_value): New.
 265         (s390_extract_operand): Change return type to union operand_value.
 266         Also avoid integer overflow in sign-extension.
 267         (s390_print_insn_with_opcode): Adjust to changed return value from
 268         s390_extract_operand().  Change "%i" printf format to "%u" for
 269         unsigned values.
 270         (init_disasm): Simplify initialization of opc_index[].  This also
 271         fixes an access after the last element of s390_opcodes[].
 272         (print_insn_s390): Simplify the opcode search loop.
 273         Check architecture mask against all searched opcodes, not just the
 274         first matching one.
 275         (s390_print_insn_with_opcode): Drop function pointer dereferences
 276         without effect.
 277         (print_insn_s390): Likewise.
 278         (s390_insn_length): Simplify formula for return value.
 279         (s390_print_insn_with_opcode): Avoid special handling for the
 280         separator before the first operand.  Use new local variable
 281         'flags' in place of 'operand->flags'.
 282
 283 2014-08-14  Mike Frysinger  <vapier@gentoo.org>
 284
 285         * bfin-dis.c (struct private): Change int's to bfd_boolean's.
 286         (decode_LOGI2op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
 287         decode_dagMODik_0, decode_LDIMMhalf_0, decode_linkage_0):
 288         Change assignment of 1 to priv->comment to TRUE.
 289         (print_insn_bfin): Change legal to a bfd_boolean.  Change
 290         assignment of 0/1 with priv comment and parallel and legal
 291         to FALSE/TRUE.
 292
 293 2014-08-14  Mike Frysinger  <vapier@gentoo.org>
 294
 295         * bfin-dis.c (OUT): Define.
 296         (decode_CC2stat_0): Declare new op_names array.
 297         Replace multiple if statements with a single one.
 298
 299 2014-08-14  Mike Frysinger  <vapier@gentoo.org>
 300
 301         * bfin-dis.c (struct private): Add iw0.
 302         (_print_insn_bfin): Assign iw0 to priv.iw0.
 303         (print_insn_bfin): Drop ifetch and use priv.iw0.
 304
 305 2014-08-13  Mike Frysinger  <vapier@gentoo.org>
 306
 307         * bfin-dis.c (comment, parallel): Move from global scope ...
 308         (struct private): ... to this new struct.
 309         (decode_ProgCtrl_0, decode_CaCTRL_0, decode_PushPopReg_0,
 310         decode_PushPopMultiple_0, decode_ccMV_0, decode_CCflag_0,
 311         decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
 312         decode_LOGI2op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
 313         decode_dagMODik_0, decode_LoopSetup_0, decode_LDIMMhalf_0,
 314         decode_CALLa_0, decode_linkage_0, decode_pseudoDEBUG_0,
 315         decode_pseudoOChar_0, decode_pseudodbg_assert_0, _print_insn_bfin,
 316         print_insn_bfin): Declare private struct.  Use priv's comment and
 317         parallel members.
 318
 319 2014-08-13  Mike Frysinger  <vapier@gentoo.org>
 320
 321         * bfin-dis.c (ifetch): Do not align pc to 2 bytes.
 322         (_print_insn_bfin): Add check for unaligned pc.
 323
 324 2014-08-13  Mike Frysinger  <vapier@gentoo.org>
 325
 326         * bfin-dis.c (ifetch): New function.
 327         (_print_insn_bfin, print_insn_bfin): Call new ifetch and return
 328         -1 when it errors.
 329
 330 2014-07-29  Matthew Fortune  <matthew.fortune@imgtec.com>
 331
 332         * micromips-opc.c (COD): Rename throughout to...
 333         (CM): New define, update to use INSN_COPROC_MOVE.
 334         (LCD): Rename throughout to...
 335         (LC): New define, update to use INSN_LOAD_COPROC.
 336         * mips-opc.c: Likewise.
 337
 338 2014-07-29  Matthew Fortune  <matthew.fortune@imgtec.com>
 339
 340         * micromips-opc.c (COD, LCD) New macros.
 341         (cfc1, ctc1): Remove FP_S attribute.
 342         (dmfc1, mfc1, mfhc1): Add LCD attribute.
 343         (dmtc1, mtc1, mthc1): Add COD attribute.
 344         * mips-opc.c (cfc1, cftc1, ctc, cttc1): Remove FP_S attribute.
 345
 346 2014-07-22  Sergey Guriev  <sergey.s.guriev@intel.com>
 347             Alexander Ivchenko  <alexander.ivchenko@intel.com>
 348             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 349             Sergey Lega  <sergey.s.lega@intel.com>
 350             Anna Tikhonova  <anna.tikhonova@intel.com>
 351             Ilya Tocar  <ilya.tocar@intel.com>
 352             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 353             Ilya Verbin  <ilya.verbin@intel.com>
 354             Kirill Yukhin  <kirill.yukhin@intel.com>
 355             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 356
 357         * i386-dis-evex.h: Updated.
 358         * i386-dis.c (PREFIX enum): Add PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
 359         PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0F3A16,
 360         PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A50, PREFIX_EVEX_0F3A51,
 361         PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
 362         PREFIX_EVEX_0F3A67.
 363         (VEX_LEN enum): Add VEX_LEN_0F92_P_2, VEX_LEN_0F93_P_2,
 364         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_2_LEN_0.
 365         (VEX_W enum): Add EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
 366         EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2, EVEX_W_0F57_P_0,
 367         EVEX_W_0F57_P_2, EVEX_W_0F78_P_2, EVEX_W_0F79_P_2, EVEX_W_0F7A_P_2,
 368         EVEX_W_0F7B_P_2, EVEX_W_0F3838_P_1, EVEX_W_0F3839_P_1,
 369         EVEX_W_0F3A16_P_2, EVEX_W_0F3A22_P_2, EVEX_W_0F3A50_P_2,
 370         EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2, EVEX_W_0F3A57_P_2,
 371         EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2.
 372         (prefix_table): Add entries for new instructions.
 373         (vex_len_table): Ditto.
 374         (vex_w_table): Ditto.
 375         (OP_E_memory): Update xmmq_mode handling.
 376         * i386-gen.c (cpu_flag_init): Add CPU_AVX512DQ_FLAGS.
 377         (cpu_flags): Add CpuAVX512DQ.
 378         * i386-init.h: Regenerared.
 379         * i386-opc.h (CpuAVX512DQ): New.
 380         (i386_cpu_flags): Add cpuavx512dq.
 381         * i386-opc.tbl: Add AVX512DQ instructions.
 382         * i386-tbl.h: Regenerate.
 383
 384 2014-07-22  Sergey Guriev  <sergey.s.guriev@intel.com>
 385             Alexander Ivchenko  <alexander.ivchenko@intel.com>
 386             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 387             Sergey Lega  <sergey.s.lega@intel.com>
 388             Anna Tikhonova  <anna.tikhonova@intel.com>
 389             Ilya Tocar  <ilya.tocar@intel.com>
 390             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 391             Ilya Verbin  <ilya.verbin@intel.com>
 392             Kirill Yukhin  <kirill.yukhin@intel.com>
 393             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 394
 395         * i386-dis-evex.h: Add new instructions (prefixes bellow).
 396         * i386-dis.c (fetch_data): Add EdqwS, Edb, Edw, MaskBDE.
 397         (enum): Add dqw_swap_mode, db_mode, dw_mode, mask_bd_mode, REG_EVEX_0F71.
 398         (PREFIX enum): Add PREFIX_VEX_0F4A, PREFIX_VEX_0F99, PREFIX_VEX_0F3A31,
 399         PREFIX_VEX_0F3A33, PREFIX_EVEX_0F60, PREFIX_EVEX_0F61, PREFIX_EVEX_0F63,
 400         PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
 401         PREFIX_EVEX_0F69, PREFIX_EVEX_0F6B, PREFIX_EVEX_0F71_REG_2, PREFIX_EVEX_0F71_REG_4,
 402         PREFIX_EVEX_0F71_REG_6, PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_7,
 403         PREFIX_EVEX_0F74, PREFIX_EVEX_0F75, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
 404         PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5, PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9,
 405         PREFIX_EVEX_0FDA, PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
 406         PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3, PREFIX_EVEX_0FE4,
 407         PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8, PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA,
 408         PREFIX_EVEX_0FEC, PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
 409         PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8, PREFIX_EVEX_0FF9,
 410         PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD, PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804,
 411         PREFIX_EVEX_0F380B, PREFIX_EVEX_0F3810, PREFIX_EVEX_0F381C, PREFIX_EVEX_0F381D,
 412         PREFIX_EVEX_0F3820, PREFIX_EVEX_0F3826, PREFIX_EVEX_0F382B, PREFIX_EVEX_0F3830,
 413         PREFIX_EVEX_0F3838, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E, PREFIX_EVEX_0F3866,
 414         PREFIX_EVEX_0F3875, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879, PREFIX_EVEX_0F387A,
 415         PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387D, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F3A0F,
 416         PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15, PREFIX_EVEX_0F3A20, PREFIX_EVEX_0F3A3E,
 417         PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A42.
 418         (VEX_LEN enum): Add VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_2, VEX_LEN_0F44_P_2,
 419         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_2, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
 420         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_2,
 421         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_2, VEX_LEN_0F99_P_0,
 422         VEX_LEN_0F99_P_2, VEX_LEN_0F3A31_P_2, VEX_LEN_0F3A33_P_2, VEX_W_0F41_P_2_LEN_1,
 423         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_2_LEN_1,
 424         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
 425         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1, VEX_W_0F90_P_2_LEN_0,
 426         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_3_LEN_0, VEX_W_0F93_P_3_LEN_0,
 427         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0, VEX_W_0F99_P_2_LEN_0,
 428         VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A33_P_2_LEN_0.
 429         (VEX_W enum): Add EVEX_W_0F6B_P_2, EVEX_W_0F6F_P_3, EVEX_W_0F7F_P_3,
 430         EVEX_W_0F3810_P_1, EVEX_W_0F3810_P_2, EVEX_W_0F3811_P_2, EVEX_W_0F3812_P_2,
 431         EVEX_W_0F3820_P_1, EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2, EVEX_W_0F3828_P_1,
 432         EVEX_W_0F3829_P_1, EVEX_W_0F382B_P_2, EVEX_W_0F3830_P_1, EVEX_W_0F3866_P_2,
 433         EVEX_W_0F3875_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F387A_P_2,
 434         EVEX_W_0F387B_P_2, EVEX_W_0F387D_P_2, EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2,
 435         EVEX_W_0F3A3F_P_2, EVEX_W_0F3A42_P_2.
 436         (prefix_table): Add entries for new instructions.
 437         (vex_table) : Ditto.
 438         (vex_len_table): Ditto.
 439         (vex_w_table): Ditto.
 440         (intel_operand_size): Add db_mode, dw_mode, dqw_swap_mode,
 441         mask_bd_mode handling.
 442         (OP_E_register): Add dqw_swap_mode, dw_mode, db_mode, mask_bd_mode
 443         handling.
 444         (OP_E_memory): Add dqw_mode, dw_mode, dqw_swap_mode, dqb_mode, db_mode
 445         handling.
 446         (OP_G): Add db_mode, dw_mode, dqw_swap_mode, mask_bd_mode handling.
 447         (OP_EX): Add dqw_swap_mode handling.
 448         (OP_VEX): Add mask_bd_mode handling.
 449         (OP_Mask): Add mask_bd_mode handling.
 450         * i386-gen.c (cpu_flag_init): Add CPU_AVX512BW_FLAGS.
 451         (cpu_flags): Add CpuAVX512BW.
 452         * i386-init.h: Regenerated.
 453         * i386-opc.h (CpuAVX512BW): New.
 454         (i386_cpu_flags): Add cpuavx512bw.
 455         * i386-opc.tbl: Add AVX512BW instructions.
 456         * i386-tbl.h: Regenerate.
 457
 458 2014-07-22  Sergey Guriev  <sergey.s.guriev@intel.com>
 459             Alexander Ivchenko  <alexander.ivchenko@intel.com>
 460             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 461             Sergey Lega  <sergey.s.lega@intel.com>
 462             Anna Tikhonova  <anna.tikhonova@intel.com>
 463             Ilya Tocar  <ilya.tocar@intel.com>
 464             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 465             Ilya Verbin  <ilya.verbin@intel.com>
 466             Kirill Yukhin  <kirill.yukhin@intel.com>
 467             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 468
 469         * i386-opc.tbl: Add AVX512VL and AVX512CD instructions.
 470         * i386-tbl.h: Regenerate.
 471
 472 2014-07-22  Sergey Guriev  <sergey.s.guriev@intel.com>
 473             Alexander Ivchenko  <alexander.ivchenko@intel.com>
 474             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 475             Sergey Lega  <sergey.s.lega@intel.com>
 476             Anna Tikhonova  <anna.tikhonova@intel.com>
 477             Ilya Tocar  <ilya.tocar@intel.com>
 478             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 479             Ilya Verbin  <ilya.verbin@intel.com>
 480             Kirill Yukhin  <kirill.yukhin@intel.com>
 481             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 482
 483         * i386-dis.c (intel_operand_size): Support 128/256 length in
 484         vex_vsib_q_w_dq_mode.
 485         (OP_E_memory): Add ymmq_mode handling, handle new broadcast.
 486         * i386-gen.c (cpu_flag_init): Add CPU_AVX512VL_FLAGS.
 487         (cpu_flags): Add CpuAVX512VL.
 488         * i386-init.h: Regenerated.
 489         * i386-opc.h (CpuAVX512VL): New.
 490         (i386_cpu_flags): Add cpuavx512vl.
 491         (BROADCAST_1TO4, BROADCAST_1TO2): Define.
 492         * i386-opc.tbl: Add AVX512VL instructions.
 493         * i386-tbl.h: Regenerate.
 494
 495 2014-07-20  Stefan Kristiansson  <stefan.kristiansson@saunalahti.fi>
 496
 497         * or1k-desc.c, * or1k-desc.h, * or1k-opc.c, * or1k-opc.h,
 498         * or1k-opinst.c: Regenerate.
 499
 500 2014-07-08  Ilya Tocar  <ilya.tocar@intel.com>
 501
 502         * i386-dis-evex.h (EVEX_W_0F10_P_1_M_1): Fix vmovss.
 503         (EVEX_W_0F10_P_3_M_1): Fix vmovsd.
 504
 505 2014-07-04  Alan Modra  <amodra@gmail.com>
 506
 507         * configure.ac: Rename from configure.in.
 508         * Makefile.in: Regenerate.
 509         * config.in: Regenerate.
 510
 511 2014-07-04  Alan Modra  <amodra@gmail.com>
 512
 513         * configure.in: Include bfd/version.m4.
 514         (AC_INIT, AM_INIT_AUTOMAKE): Use modern form.
 515         (BFD_VERSION): Delete.
 516         * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Remove bfd/configure.in.
 517         * configure: Regenerate.
 518         * Makefile.in: Regenerate.
 519
 520 2014-07-01  Barney Stratford   <barney_stratford@fastmail.fm>
 521             Senthil Kumar Selvaraj  <senthil_kumar.selvaraj@atmel.com>
 522             Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
 523             Soundararajan  <Sounderarajan.D@atmel.com>
 524
 525         * avr-dis.c (avr_operand): Handle constraint j for 16 bit lds/sts.
 526         (print_insn_avr): Do not select opcode if insn ISA is avrtiny and
 527         machine is not avrtiny.
 528
 529 2014-06-26  Philippe De Muyter <phdm@macqel.be>
 530
 531         * or1k-desc.h (spr_field_masks): Add U suffix to the end of long
 532         constants.
 533
 534 2014-06-12  Alan Modra  <amodra@gmail.com>
 535
 536         * or1k-asm.c, * or1k-desc.c, * or1k-desc.h, * or1k-dis.c,
 537         * or1k-ibld.c, * or1k-opc.c, * or1k-opc.h, * or1k-opinst.c: Regenerate.
 538
 539 2014-06-10  H.J. Lu  <hongjiu.lu@intel.com>
 540
 541         * i386-dis.c (fwait_prefix): New.
 542         (ckprefix): Set fwait_prefix.
 543         (print_insn): Properly print prefixes before fwait.
 544
 545 2014-06-07  Alan Modra  <amodra@gmail.com>
 546
 547         * ppc-opc.c (UISIGNOPT): Define and use with cmpli.
 548
 549 2014-06-05  Joel Brobecker  <brobecker@adacore.com>
 550
 551         * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Add dependency on
 552         bfd's development.sh.
 553         * Makefile.in, configure: Regenerate.
 554
 555 2014-06-03  Nick Clifton  <nickc@redhat.com>
 556
 557         * msp430-dis.c (msp430_doubleoperand): Use extension_word to
 558         decide when extended addressing is being used.
 559
 560 2014-06-02  Eric Botcazou  <ebotcazou@adacore.com>
 561
 562         * sparc-opc.c (cas): Disable for LEON.
 563         (casl): Likewise.
 564
 565 2014-05-20  Alan Modra  <amodra@gmail.com>
 566
 567         * m68k-dis.c: Don't include setjmp.h.
 568
 569 2014-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 570
 571         * i386-dis.c (ADDR16_PREFIX): Removed.
 572         (ADDR32_PREFIX): Likewise.
 573         (DATA16_PREFIX): Likewise.
 574         (DATA32_PREFIX): Likewise.
 575         (prefix_name): Updated.
 576         (print_insn): Simplify data and address size prefixes processing.
 577
 578 2014-05-08  Stefan Kristiansson  <stefan.kristiansson@saunalahti.fi>
 579
 580         * or1k-desc.c: Regenerated.
 581         * or1k-desc.h: Likewise.
 582         * or1k-opc.c: Likewise.
 583         * or1k-opc.h: Likewise.
 584         * or1k-opinst.c: Likewise.
 585
 586 2014-05-07  Andrew Bennett  <andrew.bennett@imgtec.com>
 587
 588         * mips-opc.c (mips_builtin_opcodes): Add MIPS32r5 eretnc instruction.
 589         (I34): New define.
 590         (I36): New define.
 591         (I66): New define.
 592         (I68): New define.
 593         * mips-dis.c (mips_arch_choices): Add mips32r3, mips32r5, mips64r3 and
 594         mips64r5.
 595         (parse_mips_dis_option): Update MSA and virtualization support to
 596         allow mips64r3 and mips64r5.
 597
 598 2014-05-07  Andrew Bennett  <andrew.bennett@imgtec.com>
 599
 600         * mips-opc.c (G3): Remove I4.
 601
 602 2014-05-05  H.J. Lu  <hongjiu.lu@intel.com>
 603
 604         PR binutils/16893
 605         * i386-dis.c (twobyte_has_mandatory_prefix): New variable.
 606         (end_codep): Likewise.
 607         (mandatory_prefix): Likewise.
 608         (active_seg_prefix): Likewise.
 609         (ckprefix): Set active_seg_prefix to the active segment register
 610         prefix.
 611         (seg_prefix): Removed.
 612         (get_valid_dis386): Use the last of PREFIX_REPNZ and PREFIX_REPZ
 613         for prefix index.  Ignore the index if it is invalid and the
 614         mandatory prefix isn't required.
 615         (print_insn): Set mandatory_prefix if the PREFIX_XXX prefix is
 616         mandatory.  Don't set PREFIX_REPZ/PREFIX_REPNZ/PREFIX_LOCK bits
 617         in used_prefixes here.  Don't print unused prefixes.  Check
 618         active_seg_prefix for the active segment register prefix.
 619         Restore the DFLAG bit in sizeflag if the data size prefix is
 620         unused.  Check the unused mandatory PREFIX_XXX prefixes
 621         (append_seg): Only print the segment register which gets used.
 622         (OP_E_memory): Check active_seg_prefix for the segment register
 623         prefix.
 624         (OP_OFF): Likewise.
 625         (OP_OFF64): Likewise.
 626         (OP_DSreg): Set active_seg_prefix to PREFIX_DS if it is unset.
 627
 628 2014-05-02  H.J. Lu  <hongjiu.lu@intel.com>
 629
 630         PR binutils/16886
 631         * config.in: Regenerated.
 632         * configure: Likewise.
 633         * configure.in: Check if sigsetjmp is available.
 634         * h8500-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
 635         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 636         (print_insn_h8500): Replace setjmp with OPCODES_SIGSETJMP.
 637         * i386-dis.c (dis_private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
 638         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 639         (print_insn): Replace setjmp with OPCODES_SIGSETJMP.
 640         * ns32k-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
 641         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 642         (print_insn_ns32k): Replace setjmp with OPCODES_SIGSETJMP.
 643         * sysdep.h (OPCODES_SIGJMP_BUF): New macro.
 644         (OPCODES_SIGSETJMP): Likewise.
 645         (OPCODES_SIGLONGJMP): Likewise.
 646         * vax-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
 647         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 648         (print_insn_vax): Replace setjmp with OPCODES_SIGSETJMP.
 649         * xtensa-dis.c (dis_private): Replace jmp_buf with
 650         OPCODES_SIGJMP_BUF.
 651         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 652         (print_insn_xtensa): Replace setjmp with OPCODES_SIGSETJMP.
 653         * z8k-dis.c(instr_data_s): Replace jmp_buf with OPCODES_SIGJMP_BUF.
 654         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 655         (print_insn_z8k): Replace setjmp with OPCODES_SIGSETJMP.
 656
 657 2014-05-01  H.J. Lu  <hongjiu.lu@intel.com>
 658
 659         PR binutils/16891
 660         * i386-dis.c (print_insn): Handle prefixes before fwait.
 661
 662 2014-04-26  Alan Modra  <amodra@gmail.com>
 663
 664         * po/POTFILES.in: Regenerate.
 665
 666 2014-04-23  Andrew Bennett  <andrew.bennett@imgtec.com>
 667
 668         * mips-dis.c (mips_arch_choices): Update mips32r2 and mips64r2
 669         to allow the MIPS XPA ASE.
 670         (parse_mips_dis_option): Process the -Mxpa option.
 671         * mips-opc.c (XPA): New define.
 672         (mips_builtin_opcodes): Add MIPS XPA instructions and move the
 673         locations of the ctc0 and cfc0 instructions.
 674
 675 2014-04-22  Christian Svensson  <blue@cmd.nu>
 676
 677         * Makefile.am: Remove openrisc and or32 support.  Add support for or1k.
 678         * configure.in: Likewise.
 679         * disassemble.c: Likewise.
 680         * or1k-asm.c: New file.
 681         * or1k-desc.c: New file.
 682         * or1k-desc.h: New file.
 683         * or1k-dis.c: New file.
 684         * or1k-ibld.c: New file.
 685         * or1k-opc.c: New file.
 686         * or1k-opc.h: New file.
 687         * or1k-opinst.c: New file.
 688         * Makefile.in: Regenerate.
 689         * configure: Regenerate.
 690         * openrisc-asm.c: Delete.
 691         * openrisc-desc.c: Delete.
 692         * openrisc-desc.h: Delete.
 693         * openrisc-dis.c: Delete.
 694         * openrisc-ibld.c: Delete.
 695         * openrisc-opc.c: Delete.
 696         * openrisc-opc.h: Delete.
 697         * or32-dis.c: Delete.
 698         * or32-opc.c: Delete.
 699
 700 2014-04-04  Ilya Tocar  <ilya.tocar@intel.com>
 701
 702         * i386-dis.c (rm_table): Add encls, enclu.
 703         * i386-gen.c (cpu_flag_init): Add CPU_SE1_FLAGS,
 704         (cpu_flags): Add CpuSE1.
 705         * i386-opc.h (enum): Add CpuSE1.
 706         (i386_cpu_flags): Add cpuse1.
 707         * i386-opc.tbl: Add encls, enclu.
 708         * i386-init.h: Regenerated.
 709         * i386-tbl.h: Likewise.
 710
 711 2014-04-02  Anthony Green  <green@moxielogic.com>
 712
 713         * moxie-opc.c (moxie_form1_opc_info): Add sign-extension
 714         instructions, sex.b and sex.s.
 715
 716 2014-03-26  Jiong Wang  <jiong.wang@arm.com>
 717
 718         * aarch64-dis.c (aarch64_ext_ldst_elemlist): Check H/S undefined
 719         instructions.
 720
 721 2014-03-20  Ilya Tocar  <ilya.tocar@intel.com>
 722
 723         * i386-opc.tbl: Change memory size for vgatherpf0qps, vgatherpf1qps,
 724         vscatterpf0qps, vscatterpf1qps, vgatherqps, vpgatherqd, vpscatterqd,
 725         vscatterqps.
 726         * i386-tbl.h: Regenerate.
 727
 728 2014-03-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 729
 730         * sparc-dis.c (v9_hpriv_reg_names): Names for %hstick_offset and
 731         %hstick_enable added.
 732
 733 2014-03-19  Nick Clifton  <nickc@redhat.com>
 734
 735         * rx-decode.opc (bwl): Allow for bogus instructions with a size
 736         field of 3.
 737         (sbwl, ubwl, SCALE): Likewise.
 738         * rx-decode.c: Regenerate.
 739
 740 2014-03-12  Alan Modra  <amodra@gmail.com>
 741
 742         * Makefile.in: Regenerate.
 743
 744 2014-03-05  Alan Modra  <amodra@gmail.com>
 745
 746         Update copyright years.
 747
 748 2014-03-04  Heiher  <r@hev.cc>
 749
 750         * mips-dis.c (mips_arch_choices): Usee ISA_MIPS64R2 for Loongson-3A.
 751
 752 2014-03-04  Richard Sandiford  <rdsandiford@googlemail.com>
 753
 754         * mips-opc.c (mips_builtin_opcodes): Move the udi* instructions
 755         so that they come after the Loongson extensions.
 756
 757 2014-03-03  Alan Modra  <amodra@gmail.com>
 758
 759         * i386-gen.c (process_copyright): Emit copyright notice on one line.
 760
 761 2014-02-28  Alan Modra  <amodra@gmail.com>
 762
 763         * msp430-decode.c: Regenerate.
 764
 765 2014-02-27  Jiong Wang  <jiong.wang@arm.com>
 766
 767         * aarch64-tbl.h (aarch64_opcode_table): Replace IMM0 with
 768         FPIMM0 for fcmeq, fcmgt, fcmge, fcmlt and fcmle.
 769
 770 2014-02-27  Yufeng Zhang  <yufeng.zhang@arm.com>
 771
 772         * aarch64-opc.c (print_register_offset_address): Call
 773         get_int_reg_name to prepare the register name.
 774
 775 2014-02-25  Ilya Tocar  <ilya.tocar@intel.com>
 776
 777         * i386-opc.tbl: Remove wrong variant of vcvtps2ph
 778         * i386-tbl.h: Regenerate.
 779
 780 2014-02-20  Ilya Tocar  <ilya.tocar@intel.com>
 781
 782         * i386-gen.c (cpu_flag_init): Add CPU_PREFETCHWT1_FLAGS/
 783         (cpu_flags): Add CpuPREFETCHWT1.
 784         * i386-init.h: Regenerate.
 785         * i386-opc.h (CpuPREFETCHWT1): New.
 786         (i386_cpu_flags): Add cpuprefetchwt1.
 787         * i386-opc.tbl: Cahnge CPU of prefetchwt1 from CpuAVX512PF to CpuPREFETCHWT1.
 788         * i386-tbl.h: Regenerate.
 789
 790 2014-02-20  Ilya Tocar  <ilya.tocar@intel.com>
 791
 792         * i386-opc.tbl: Change CPU of vptestnmq, vptestnmd from CpuAVX512CD,
 793         to CpuAVX512F.
 794         * i386-tbl.h: Regenerate.
 795
 796 2014-02-19  H.J. Lu  <hongjiu.lu@intel.com>
 797
 798         * i386-gen.c (output_cpu_flags): Don't output trailing space.
 799         (output_opcode_modifier): Likewise.
 800         (output_operand_type): Likewise.
 801         * i386-init.h: Regenerated.
 802         * i386-tbl.h: Likewise.
 803
 804 2014-02-12  Ilya Tocar  <ilya.tocar@intel.com>
 805
 806         * i386-dis.c (MOD enum): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4,
 807         MOD_0FC7_REG_5.
 808         (PREFIX enum): Add PREFIX_0FAE_REG_7.
 809         (reg_table): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4 MOD_0FC7_REG_5.
 810         (prefix_table): Add clflusopt.
 811         (mod_table): Add xrstors, xsavec, xsaves.
 812         * i386-gen.c (cpu_flag_init): Add CPU_CLFLUSHOPT_FLAGS,
 813         CPU_XSAVES_FLAGS, CPU_XSAVEC_FLAGS.
 814         (cpu_flags): Add CpuClflushOpt, CpuXSAVES, CpuXSAVEC.
 815         * i386-init.h: Regenerate.
 816         * i386-opc.tbl: Add clflushopt, xrstors, xrstors64, xsaves,
 817         xsaves64, xsavec, xsavec64.
 818         * i386-tbl.h: Regenerate.
 819
 820 2014-02-10  Alan Modra  <amodra@gmail.com>
 821
 822         * po/POTFILES.in: Regenerate.
 823         * po/opcodes.pot: Regenerate.
 824
 825 2014-01-30  Michael Zolotukhin  <michael.v.zolotukhin@gmail.com>
 826             Jan Beulich  <jbeulich@suse.com>
 827
 828         PR binutils/16490
 829         * i386-dis.c (OP_E_memory): Fix shift computation for
 830         vex_vsib_q_w_dq_mode.
 831
 832 2014-01-09  Bradley Nelson  <bradnelson@google.com>
 833             Roland McGrath  <mcgrathr@google.com>
 834
 835         * i386-dis.c (print_insn): Do not touch all_prefixes[-1] when
 836         last_rex_prefix is -1.
 837
 838 2014-01-08  H.J. Lu  <hongjiu.lu@intel.com>
 839
 840         * i386-gen.c (process_copyright): Update copyright year to 2014.
 841
 842 2014-01-03  Maciej W. Rozycki  <macro@codesourcery.com>
 843
 844         * nds32-asm.c (parse_operand): Fix out-of-range integer constant.
 845
 846 For older changes see ChangeLog-2013
 847 \f
 848 Copyright (C) 2014 Free Software Foundation, Inc.
 849
 850 Copying and distribution of this file, with or without modification,
 851 are permitted in any medium without royalty provided the copyright
 852 notice and this notice are preserved.
 853
 854 Local Variables:
 855 mode: change-log
 856 left-margin: 8
 857 fill-column: 74
 858 version-control: never
 859 End: