opcodes/ChangeLog

   1 2014-10-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
   2
   3         * sparc-opc.c (sparc-opcodes): Fix several misplaced hwcap
   4         entries.
   5
   6 2014-10-15  Tristan Gingold  <gingold@adacore.com>
   7
   8         * configure: Regenerate.
   9
  10 2014-10-09  Jose E. Marchesi  &lt;jose.marchesi@oracle.com&gt;
  11
  12         * sparc-opc.c (sparc-opcodes): Remove instructions `chkpt',
  13         `commit', `random', `wr r,r,%cps', `wr r,i,%cps' and `rd %cps,r'.
  14         Annotate table with HWCAP2 bits.
  15         Add instructions xmontmul, xmontsqr, xmpmul.
  16         (sparc-opcodes): Add the `mwait',  `wr r,r,%mwait', `wr
  17         r,i,%mwait' and `rd %mwait,r' instructions.
  18         Add rd/wr instructions for accessing the %mcdper ancillary state
  19         register.
  20         (sparc-opcodes): Add sparc5/vis4.0 instructions:
  21         subxc, subxccc, fpadd8, fpadds8, fpaddus8, fpaddus16, fpcmple8,
  22         fpcmpgt8, fpcmpule16, fpcmpugt16, fpcmpule32, fpcmpugt32, fpmax8,
  23         fpmax16, fpmax32, fpmaxu8, fpmaxu16, fpmaxu32, fpmin8, fpmin16,
  24         fpmin32, fpminu8, fpminu16, fpminu32, fpsub8, fpsubs8, fpsubus8,
  25         fpsubus16, and faligndatai.
  26         * sparc-dis.c (v9a_asr_reg_names): Add the %mwait (%asr28)
  27         ancillary state register to the table.
  28         (print_insn_sparc): Handle the %mcdper ancillary state register.
  29         (print_insn_sparc): Handle new operand type '}'.
  30
  31 2014-09-22  H.J. Lu  <hongjiu.lu@intel.com>
  32
  33         * i386-dis.c (MOD_0F20): Removed.
  34         (MOD_0F21): Likewise.
  35         (MOD_0F22): Likewise.
  36         (MOD_0F23): Likewise.
  37         (dis386_twobyte): Replace MOD_0F20, MOD_0F21, MOD_0F22 and
  38         MOD_0F23 with "movZ".
  39         (mod_table): Remove MOD_0F20, MOD_0F21, MOD_0F22 and MOD_0F23.
  40         (OP_R): Check mod/rm byte and call OP_E_register.
  41
  42 2014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
  43
  44         * nds32-asm.c (nds32_opcodes, operand_fields, keyword_im5_i,
  45         keyword_im5_m, keyword_accumulator, keyword_aridx, keyword_aridx2,
  46         keyword_aridxi): Add audio ISA extension.
  47         (keyword_gpr, keyword_usr, keyword_sr, keyword_cp, keyword_cpr,
  48         keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm, keyword_dpref_st,
  49         keyword_cctl_lv, keyword_standby_st, keyword_msync_st): Adjust scrope
  50         for nds32-dis.c using.
  51         (build_opcode_syntax): Remove dead code.
  52         (parse_re, parse_a30b20, parse_rt21, parse_rte_start, parse_rte_end,
  53         parse_rte69_start, parse_rte69_end, parse_im5_ip, parse_im5_mr,
  54         parse_im6_ip, parse_im6_iq, parse_im6_mr, parse_im6_ms): Add audio ISA
  55         operand parser.
  56         * nds32-asm.h: Declare.
  57         * nds32-dis.c: Use array nds32_opcodes to disassemble instead of
  58         decoding by switch.
  59
  60 2014-09-15  Andrew Bennett  <andrew.bennett@imgtec.com>
  61             Matthew Fortune  <matthew.fortune@imgtec.com>
  62
  63         * mips-dis.c (mips_arch_choices): Add entries for mips32r6 and
  64         mips64r6.
  65         (parse_mips_dis_option): Allow MSA and virtualization support for
  66         mips64r6.
  67         (mips_print_arg_state): Add fields dest_regno and seen_dest.
  68         (mips_seen_register): New function.
  69         (print_insn_arg): Refactored code to use mips_seen_register
  70         function.  Add support for OP_SAME_RS_RT, OP_CHECK_PREV and
  71         OP_NON_ZERO_REG.  Changed OP_REPEAT_DEST_REG case to print out
  72         the register rather than aborting.
  73         (print_insn_args): Add length argument.  Add code to correctly
  74         calculate the instruction address for pc relative instructions.
  75         (validate_insn_args): New static function.
  76         (print_insn_mips): Prevent jalx disassembling for r6.  Use
  77         validate_insn_args.
  78         (print_insn_micromips): Use validate_insn_args.
  79         all the arguments are valid.
  80         * mips-formats.h (PREV_CHECK): New define.
  81         * mips-opc.c (decode_mips_operand): Add support for -a, -b, -d, -s,
  82         -t, -u, -v, -w, -x, -y, -A, -B, +I, +O, +R, +:, +\, +", +;
  83         (RD_pc): New define.
  84         (FS): New define.
  85         (I37): New define.
  86         (I69): New define.
  87         (mips_builtin_opcodes): Add MIPS R6 instructions.  Exclude recoded
  88         MIPS R6 instructions from MIPS R2 instructions.
  89
  90 2014-09-10  H.J. Lu  <hongjiu.lu@intel.com>
  91
  92         * i386-dis.c (dis386): Replace "P" with "%LP" for iret and sysret.
  93         (putop): Handle "%LP".
  94
  95 2014-09-03  Jiong Wang  <jiong.wang@arm.com>
  96
  97         * aarch64-tbl.h (aarch64_opcode_table): Update encoding for mrs/msr.
  98         * aarch64-dis-2.c: Update auto-generated file.
  99
 100 2014-09-03  Jiong Wang  <jiong.wang@arm.com>
 101
 102         * aarch64-tbl.h (QL_R4NIL): New qualifiers.
 103         (aarch64_feature_lse): New feature added.
 104         (LSE): New Added.
 105         (aarch64_opcode_table): New LSE instructions added.  Improve
 106         descriptions for ldarb/ldarh/ldar.
 107         (aarch64_opcode_table): Describe PAIRREG.
 108         * aarch64-opc.h (aarch64_field_kind): Add FLD_lse_sz.
 109         * aarch64-opc.c (fields): Add entry for F_LSE_SZ.
 110         (aarch64_print_operand): Recognize PAIRREG.
 111         (operand_general_constraint_met_p): Check reg pair constraints for CASP
 112         instructions.
 113         * aarch64-dis.c (aarch64_ext_regno_pair): New extractor for paired reg.
 114         (do_special_decoding): Recognize F_LSE_SZ.
 115         * aarch64-asm.c (do_special_encoding): Recognize F_LSE_SZ.
 116
 117 2014-08-26  Maciej W. Rozycki  <macro@codesourcery.com>
 118
 119         * micromips-opc.c (decode_micromips_operand): Rename `B' to `+J'.
 120         (micromips_opcodes): Use "+J" in place of "B" for "hypcall",
 121         "sdbbp", "syscall" and "wait".
 122
 123 2014-08-21  Nathan Sidwell  <nathan@codesourcery.com>
 124             Maciej W. Rozycki  <macro@codesourcery.com>
 125
 126         * arm-dis.c (print_arm_address): Negate the GPR-relative offset
 127         returned if the U bit is set.
 128
 129 2014-08-21  Maciej W. Rozycki  <macro@codesourcery.com>
 130
 131         * micromips-opc.c (micromips_opcodes): Remove #ifdef-ed out
 132         48-bit "li" encoding.
 133
 134 2014-08-19  Andreas Arnez  <arnez@linux.vnet.ibm.com>
 135
 136         * s390-dis.c (s390_insn_length, s390_insn_matches_opcode)
 137         (s390_print_insn_with_opcode, opcode_mask_more_specific): New
 138         static functions, code was moved from...
 139         (print_insn_s390): ...here.
 140         (s390_extract_operand): Adjust comment.  Change type of first
 141         parameter from 'unsigned char *' to 'const bfd_byte *'.
 142         (union operand_value): New.
 143         (s390_extract_operand): Change return type to union operand_value.
 144         Also avoid integer overflow in sign-extension.
 145         (s390_print_insn_with_opcode): Adjust to changed return value from
 146         s390_extract_operand().  Change "%i" printf format to "%u" for
 147         unsigned values.
 148         (init_disasm): Simplify initialization of opc_index[].  This also
 149         fixes an access after the last element of s390_opcodes[].
 150         (print_insn_s390): Simplify the opcode search loop.
 151         Check architecture mask against all searched opcodes, not just the
 152         first matching one.
 153         (s390_print_insn_with_opcode): Drop function pointer dereferences
 154         without effect.
 155         (print_insn_s390): Likewise.
 156         (s390_insn_length): Simplify formula for return value.
 157         (s390_print_insn_with_opcode): Avoid special handling for the
 158         separator before the first operand.  Use new local variable
 159         'flags' in place of 'operand->flags'.
 160
 161 2014-08-14  Mike Frysinger  <vapier@gentoo.org>
 162
 163         * bfin-dis.c (struct private): Change int's to bfd_boolean's.
 164         (decode_LOGI2op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
 165         decode_dagMODik_0, decode_LDIMMhalf_0, decode_linkage_0):
 166         Change assignment of 1 to priv->comment to TRUE.
 167         (print_insn_bfin): Change legal to a bfd_boolean.  Change
 168         assignment of 0/1 with priv comment and parallel and legal
 169         to FALSE/TRUE.
 170
 171 2014-08-14  Mike Frysinger  <vapier@gentoo.org>
 172
 173         * bfin-dis.c (OUT): Define.
 174         (decode_CC2stat_0): Declare new op_names array.
 175         Replace multiple if statements with a single one.
 176
 177 2014-08-14  Mike Frysinger  <vapier@gentoo.org>
 178
 179         * bfin-dis.c (struct private): Add iw0.
 180         (_print_insn_bfin): Assign iw0 to priv.iw0.
 181         (print_insn_bfin): Drop ifetch and use priv.iw0.
 182
 183 2014-08-13  Mike Frysinger  <vapier@gentoo.org>
 184
 185         * bfin-dis.c (comment, parallel): Move from global scope ...
 186         (struct private): ... to this new struct.
 187         (decode_ProgCtrl_0, decode_CaCTRL_0, decode_PushPopReg_0,
 188         decode_PushPopMultiple_0, decode_ccMV_0, decode_CCflag_0,
 189         decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
 190         decode_LOGI2op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
 191         decode_dagMODik_0, decode_LoopSetup_0, decode_LDIMMhalf_0,
 192         decode_CALLa_0, decode_linkage_0, decode_pseudoDEBUG_0,
 193         decode_pseudoOChar_0, decode_pseudodbg_assert_0, _print_insn_bfin,
 194         print_insn_bfin): Declare private struct.  Use priv's comment and
 195         parallel members.
 196
 197 2014-08-13  Mike Frysinger  <vapier@gentoo.org>
 198
 199         * bfin-dis.c (ifetch): Do not align pc to 2 bytes.
 200         (_print_insn_bfin): Add check for unaligned pc.
 201
 202 2014-08-13  Mike Frysinger  <vapier@gentoo.org>
 203
 204         * bfin-dis.c (ifetch): New function.
 205         (_print_insn_bfin, print_insn_bfin): Call new ifetch and return
 206         -1 when it errors.
 207
 208 2014-07-29  Matthew Fortune  <matthew.fortune@imgtec.com>
 209
 210         * micromips-opc.c (COD): Rename throughout to...
 211         (CM): New define, update to use INSN_COPROC_MOVE.
 212         (LCD): Rename throughout to...
 213         (LC): New define, update to use INSN_LOAD_COPROC.
 214         * mips-opc.c: Likewise.
 215
 216 2014-07-29  Matthew Fortune  <matthew.fortune@imgtec.com>
 217
 218         * micromips-opc.c (COD, LCD) New macros.
 219         (cfc1, ctc1): Remove FP_S attribute.
 220         (dmfc1, mfc1, mfhc1): Add LCD attribute.
 221         (dmtc1, mtc1, mthc1): Add COD attribute.
 222         * mips-opc.c (cfc1, cftc1, ctc, cttc1): Remove FP_S attribute.
 223
 224 2014-07-22  Sergey Guriev  <sergey.s.guriev@intel.com>
 225             Alexander Ivchenko  <alexander.ivchenko@intel.com>
 226             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 227             Sergey Lega  <sergey.s.lega@intel.com>
 228             Anna Tikhonova  <anna.tikhonova@intel.com>
 229             Ilya Tocar  <ilya.tocar@intel.com>
 230             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 231             Ilya Verbin  <ilya.verbin@intel.com>
 232             Kirill Yukhin  <kirill.yukhin@intel.com>
 233             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 234
 235         * i386-dis-evex.h: Updated.
 236         * i386-dis.c (PREFIX enum): Add PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
 237         PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0F3A16,
 238         PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A50, PREFIX_EVEX_0F3A51,
 239         PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
 240         PREFIX_EVEX_0F3A67.
 241         (VEX_LEN enum): Add VEX_LEN_0F92_P_2, VEX_LEN_0F93_P_2,
 242         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_2_LEN_0.
 243         (VEX_W enum): Add EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
 244         EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2, EVEX_W_0F57_P_0,
 245         EVEX_W_0F57_P_2, EVEX_W_0F78_P_2, EVEX_W_0F79_P_2, EVEX_W_0F7A_P_2,
 246         EVEX_W_0F7B_P_2, EVEX_W_0F3838_P_1, EVEX_W_0F3839_P_1,
 247         EVEX_W_0F3A16_P_2, EVEX_W_0F3A22_P_2, EVEX_W_0F3A50_P_2,
 248         EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2, EVEX_W_0F3A57_P_2,
 249         EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2.
 250         (prefix_table): Add entries for new instructions.
 251         (vex_len_table): Ditto.
 252         (vex_w_table): Ditto.
 253         (OP_E_memory): Update xmmq_mode handling.
 254         * i386-gen.c (cpu_flag_init): Add CPU_AVX512DQ_FLAGS.
 255         (cpu_flags): Add CpuAVX512DQ.
 256         * i386-init.h: Regenerared.
 257         * i386-opc.h (CpuAVX512DQ): New.
 258         (i386_cpu_flags): Add cpuavx512dq.
 259         * i386-opc.tbl: Add AVX512DQ instructions.
 260         * i386-tbl.h: Regenerate.
 261
 262 2014-07-22  Sergey Guriev  <sergey.s.guriev@intel.com>
 263             Alexander Ivchenko  <alexander.ivchenko@intel.com>
 264             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 265             Sergey Lega  <sergey.s.lega@intel.com>
 266             Anna Tikhonova  <anna.tikhonova@intel.com>
 267             Ilya Tocar  <ilya.tocar@intel.com>
 268             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 269             Ilya Verbin  <ilya.verbin@intel.com>
 270             Kirill Yukhin  <kirill.yukhin@intel.com>
 271             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 272
 273         * i386-dis-evex.h: Add new instructions (prefixes bellow).
 274         * i386-dis.c (fetch_data): Add EdqwS, Edb, Edw, MaskBDE.
 275         (enum): Add dqw_swap_mode, db_mode, dw_mode, mask_bd_mode, REG_EVEX_0F71.
 276         (PREFIX enum): Add PREFIX_VEX_0F4A, PREFIX_VEX_0F99, PREFIX_VEX_0F3A31,
 277         PREFIX_VEX_0F3A33, PREFIX_EVEX_0F60, PREFIX_EVEX_0F61, PREFIX_EVEX_0F63,
 278         PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
 279         PREFIX_EVEX_0F69, PREFIX_EVEX_0F6B, PREFIX_EVEX_0F71_REG_2, PREFIX_EVEX_0F71_REG_4,
 280         PREFIX_EVEX_0F71_REG_6, PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_7,
 281         PREFIX_EVEX_0F74, PREFIX_EVEX_0F75, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
 282         PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5, PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9,
 283         PREFIX_EVEX_0FDA, PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
 284         PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3, PREFIX_EVEX_0FE4,
 285         PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8, PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA,
 286         PREFIX_EVEX_0FEC, PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
 287         PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8, PREFIX_EVEX_0FF9,
 288         PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD, PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804,
 289         PREFIX_EVEX_0F380B, PREFIX_EVEX_0F3810, PREFIX_EVEX_0F381C, PREFIX_EVEX_0F381D,
 290         PREFIX_EVEX_0F3820, PREFIX_EVEX_0F3826, PREFIX_EVEX_0F382B, PREFIX_EVEX_0F3830,
 291         PREFIX_EVEX_0F3838, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E, PREFIX_EVEX_0F3866,
 292         PREFIX_EVEX_0F3875, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879, PREFIX_EVEX_0F387A,
 293         PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387D, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F3A0F,
 294         PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15, PREFIX_EVEX_0F3A20, PREFIX_EVEX_0F3A3E,
 295         PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A42.
 296         (VEX_LEN enum): Add VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_2, VEX_LEN_0F44_P_2,
 297         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_2, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
 298         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_2,
 299         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_2, VEX_LEN_0F99_P_0,
 300         VEX_LEN_0F99_P_2, VEX_LEN_0F3A31_P_2, VEX_LEN_0F3A33_P_2, VEX_W_0F41_P_2_LEN_1,
 301         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_2_LEN_1,
 302         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
 303         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1, VEX_W_0F90_P_2_LEN_0,
 304         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_3_LEN_0, VEX_W_0F93_P_3_LEN_0,
 305         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0, VEX_W_0F99_P_2_LEN_0,
 306         VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A33_P_2_LEN_0.
 307         (VEX_W enum): Add EVEX_W_0F6B_P_2, EVEX_W_0F6F_P_3, EVEX_W_0F7F_P_3,
 308         EVEX_W_0F3810_P_1, EVEX_W_0F3810_P_2, EVEX_W_0F3811_P_2, EVEX_W_0F3812_P_2,
 309         EVEX_W_0F3820_P_1, EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2, EVEX_W_0F3828_P_1,
 310         EVEX_W_0F3829_P_1, EVEX_W_0F382B_P_2, EVEX_W_0F3830_P_1, EVEX_W_0F3866_P_2,
 311         EVEX_W_0F3875_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F387A_P_2,
 312         EVEX_W_0F387B_P_2, EVEX_W_0F387D_P_2, EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2,
 313         EVEX_W_0F3A3F_P_2, EVEX_W_0F3A42_P_2.
 314         (prefix_table): Add entries for new instructions.
 315         (vex_table) : Ditto.
 316         (vex_len_table): Ditto.
 317         (vex_w_table): Ditto.
 318         (intel_operand_size): Add db_mode, dw_mode, dqw_swap_mode,
 319         mask_bd_mode handling.
 320         (OP_E_register): Add dqw_swap_mode, dw_mode, db_mode, mask_bd_mode
 321         handling.
 322         (OP_E_memory): Add dqw_mode, dw_mode, dqw_swap_mode, dqb_mode, db_mode
 323         handling.
 324         (OP_G): Add db_mode, dw_mode, dqw_swap_mode, mask_bd_mode handling.
 325         (OP_EX): Add dqw_swap_mode handling.
 326         (OP_VEX): Add mask_bd_mode handling.
 327         (OP_Mask): Add mask_bd_mode handling.
 328         * i386-gen.c (cpu_flag_init): Add CPU_AVX512BW_FLAGS.
 329         (cpu_flags): Add CpuAVX512BW.
 330         * i386-init.h: Regenerated.
 331         * i386-opc.h (CpuAVX512BW): New.
 332         (i386_cpu_flags): Add cpuavx512bw.
 333         * i386-opc.tbl: Add AVX512BW instructions.
 334         * i386-tbl.h: Regenerate.
 335
 336 2014-07-22  Sergey Guriev  <sergey.s.guriev@intel.com>
 337             Alexander Ivchenko  <alexander.ivchenko@intel.com>
 338             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 339             Sergey Lega  <sergey.s.lega@intel.com>
 340             Anna Tikhonova  <anna.tikhonova@intel.com>
 341             Ilya Tocar  <ilya.tocar@intel.com>
 342             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 343             Ilya Verbin  <ilya.verbin@intel.com>
 344             Kirill Yukhin  <kirill.yukhin@intel.com>
 345             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 346
 347         * i386-opc.tbl: Add AVX512VL and AVX512CD instructions.
 348         * i386-tbl.h: Regenerate.
 349
 350 2014-07-22  Sergey Guriev  <sergey.s.guriev@intel.com>
 351             Alexander Ivchenko  <alexander.ivchenko@intel.com>
 352             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 353             Sergey Lega  <sergey.s.lega@intel.com>
 354             Anna Tikhonova  <anna.tikhonova@intel.com>
 355             Ilya Tocar  <ilya.tocar@intel.com>
 356             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 357             Ilya Verbin  <ilya.verbin@intel.com>
 358             Kirill Yukhin  <kirill.yukhin@intel.com>
 359             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 360
 361         * i386-dis.c (intel_operand_size): Support 128/256 length in
 362         vex_vsib_q_w_dq_mode.
 363         (OP_E_memory): Add ymmq_mode handling, handle new broadcast.
 364         * i386-gen.c (cpu_flag_init): Add CPU_AVX512VL_FLAGS.
 365         (cpu_flags): Add CpuAVX512VL.
 366         * i386-init.h: Regenerated.
 367         * i386-opc.h (CpuAVX512VL): New.
 368         (i386_cpu_flags): Add cpuavx512vl.
 369         (BROADCAST_1TO4, BROADCAST_1TO2): Define.
 370         * i386-opc.tbl: Add AVX512VL instructions.
 371         * i386-tbl.h: Regenerate.
 372
 373 2014-07-20  Stefan Kristiansson  <stefan.kristiansson@saunalahti.fi>
 374
 375         * or1k-desc.c, * or1k-desc.h, * or1k-opc.c, * or1k-opc.h,
 376         * or1k-opinst.c: Regenerate.
 377
 378 2014-07-08  Ilya Tocar  <ilya.tocar@intel.com>
 379
 380         * i386-dis-evex.h (EVEX_W_0F10_P_1_M_1): Fix vmovss.
 381         (EVEX_W_0F10_P_3_M_1): Fix vmovsd.
 382
 383 2014-07-04  Alan Modra  <amodra@gmail.com>
 384
 385         * configure.ac: Rename from configure.in.
 386         * Makefile.in: Regenerate.
 387         * config.in: Regenerate.
 388
 389 2014-07-04  Alan Modra  <amodra@gmail.com>
 390
 391         * configure.in: Include bfd/version.m4.
 392         (AC_INIT, AM_INIT_AUTOMAKE): Use modern form.
 393         (BFD_VERSION): Delete.
 394         * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Remove bfd/configure.in.
 395         * configure: Regenerate.
 396         * Makefile.in: Regenerate.
 397
 398 2014-07-01  Barney Stratford   <barney_stratford@fastmail.fm>
 399             Senthil Kumar Selvaraj  <senthil_kumar.selvaraj@atmel.com>
 400             Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
 401             Soundararajan  <Sounderarajan.D@atmel.com>
 402
 403         * avr-dis.c (avr_operand): Handle constraint j for 16 bit lds/sts.
 404         (print_insn_avr): Do not select opcode if insn ISA is avrtiny and
 405         machine is not avrtiny.
 406
 407 2014-06-26  Philippe De Muyter <phdm@macqel.be>
 408
 409         * or1k-desc.h (spr_field_masks): Add U suffix to the end of long
 410         constants.
 411
 412 2014-06-12  Alan Modra  <amodra@gmail.com>
 413
 414         * or1k-asm.c, * or1k-desc.c, * or1k-desc.h, * or1k-dis.c,
 415         * or1k-ibld.c, * or1k-opc.c, * or1k-opc.h, * or1k-opinst.c: Regenerate.
 416
 417 2014-06-10  H.J. Lu  <hongjiu.lu@intel.com>
 418
 419         * i386-dis.c (fwait_prefix): New.
 420         (ckprefix): Set fwait_prefix.
 421         (print_insn): Properly print prefixes before fwait.
 422
 423 2014-06-07  Alan Modra  <amodra@gmail.com>
 424
 425         * ppc-opc.c (UISIGNOPT): Define and use with cmpli.
 426
 427 2014-06-05  Joel Brobecker  <brobecker@adacore.com>
 428
 429         * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Add dependency on
 430         bfd's development.sh.
 431         * Makefile.in, configure: Regenerate.
 432
 433 2014-06-03  Nick Clifton  <nickc@redhat.com>
 434
 435         * msp430-dis.c (msp430_doubleoperand): Use extension_word to
 436         decide when extended addressing is being used.
 437
 438 2014-06-02  Eric Botcazou  <ebotcazou@adacore.com>
 439
 440         * sparc-opc.c (cas): Disable for LEON.
 441         (casl): Likewise.
 442
 443 2014-05-20  Alan Modra  <amodra@gmail.com>
 444
 445         * m68k-dis.c: Don't include setjmp.h.
 446
 447 2014-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 448
 449         * i386-dis.c (ADDR16_PREFIX): Removed.
 450         (ADDR32_PREFIX): Likewise.
 451         (DATA16_PREFIX): Likewise.
 452         (DATA32_PREFIX): Likewise.
 453         (prefix_name): Updated.
 454         (print_insn): Simplify data and address size prefixes processing.
 455
 456 2014-05-08  Stefan Kristiansson  <stefan.kristiansson@saunalahti.fi>
 457
 458         * or1k-desc.c: Regenerated.
 459         * or1k-desc.h: Likewise.
 460         * or1k-opc.c: Likewise.
 461         * or1k-opc.h: Likewise.
 462         * or1k-opinst.c: Likewise.
 463
 464 2014-05-07  Andrew Bennett  <andrew.bennett@imgtec.com>
 465
 466         * mips-opc.c (mips_builtin_opcodes): Add MIPS32r5 eretnc instruction.
 467         (I34): New define.
 468         (I36): New define.
 469         (I66): New define.
 470         (I68): New define.
 471         * mips-dis.c (mips_arch_choices): Add mips32r3, mips32r5, mips64r3 and
 472         mips64r5.
 473         (parse_mips_dis_option): Update MSA and virtualization support to
 474         allow mips64r3 and mips64r5.
 475
 476 2014-05-07  Andrew Bennett  <andrew.bennett@imgtec.com>
 477
 478         * mips-opc.c (G3): Remove I4.
 479
 480 2014-05-05  H.J. Lu  <hongjiu.lu@intel.com>
 481
 482         PR binutils/16893
 483         * i386-dis.c (twobyte_has_mandatory_prefix): New variable.
 484         (end_codep): Likewise.
 485         (mandatory_prefix): Likewise.
 486         (active_seg_prefix): Likewise.
 487         (ckprefix): Set active_seg_prefix to the active segment register
 488         prefix.
 489         (seg_prefix): Removed.
 490         (get_valid_dis386): Use the last of PREFIX_REPNZ and PREFIX_REPZ
 491         for prefix index.  Ignore the index if it is invalid and the
 492         mandatory prefix isn't required.
 493         (print_insn): Set mandatory_prefix if the PREFIX_XXX prefix is
 494         mandatory.  Don't set PREFIX_REPZ/PREFIX_REPNZ/PREFIX_LOCK bits
 495         in used_prefixes here.  Don't print unused prefixes.  Check
 496         active_seg_prefix for the active segment register prefix.
 497         Restore the DFLAG bit in sizeflag if the data size prefix is
 498         unused.  Check the unused mandatory PREFIX_XXX prefixes
 499         (append_seg): Only print the segment register which gets used.
 500         (OP_E_memory): Check active_seg_prefix for the segment register
 501         prefix.
 502         (OP_OFF): Likewise.
 503         (OP_OFF64): Likewise.
 504         (OP_DSreg): Set active_seg_prefix to PREFIX_DS if it is unset.
 505
 506 2014-05-02  H.J. Lu  <hongjiu.lu@intel.com>
 507
 508         PR binutils/16886
 509         * config.in: Regenerated.
 510         * configure: Likewise.
 511         * configure.in: Check if sigsetjmp is available.
 512         * h8500-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
 513         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 514         (print_insn_h8500): Replace setjmp with OPCODES_SIGSETJMP.
 515         * i386-dis.c (dis_private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
 516         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 517         (print_insn): Replace setjmp with OPCODES_SIGSETJMP.
 518         * ns32k-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
 519         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 520         (print_insn_ns32k): Replace setjmp with OPCODES_SIGSETJMP.
 521         * sysdep.h (OPCODES_SIGJMP_BUF): New macro.
 522         (OPCODES_SIGSETJMP): Likewise.
 523         (OPCODES_SIGLONGJMP): Likewise.
 524         * vax-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
 525         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 526         (print_insn_vax): Replace setjmp with OPCODES_SIGSETJMP.
 527         * xtensa-dis.c (dis_private): Replace jmp_buf with
 528         OPCODES_SIGJMP_BUF.
 529         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 530         (print_insn_xtensa): Replace setjmp with OPCODES_SIGSETJMP.
 531         * z8k-dis.c(instr_data_s): Replace jmp_buf with OPCODES_SIGJMP_BUF.
 532         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 533         (print_insn_z8k): Replace setjmp with OPCODES_SIGSETJMP.
 534
 535 2014-05-01  H.J. Lu  <hongjiu.lu@intel.com>
 536
 537         PR binutils/16891
 538         * i386-dis.c (print_insn): Handle prefixes before fwait.
 539
 540 2014-04-26  Alan Modra  <amodra@gmail.com>
 541
 542         * po/POTFILES.in: Regenerate.
 543
 544 2014-04-23  Andrew Bennett  <andrew.bennett@imgtec.com>
 545
 546         * mips-dis.c (mips_arch_choices): Update mips32r2 and mips64r2
 547         to allow the MIPS XPA ASE.
 548         (parse_mips_dis_option): Process the -Mxpa option.
 549         * mips-opc.c (XPA): New define.
 550         (mips_builtin_opcodes): Add MIPS XPA instructions and move the
 551         locations of the ctc0 and cfc0 instructions.
 552
 553 2014-04-22  Christian Svensson  <blue@cmd.nu>
 554
 555         * Makefile.am: Remove openrisc and or32 support.  Add support for or1k.
 556         * configure.in: Likewise.
 557         * disassemble.c: Likewise.
 558         * or1k-asm.c: New file.
 559         * or1k-desc.c: New file.
 560         * or1k-desc.h: New file.
 561         * or1k-dis.c: New file.
 562         * or1k-ibld.c: New file.
 563         * or1k-opc.c: New file.
 564         * or1k-opc.h: New file.
 565         * or1k-opinst.c: New file.
 566         * Makefile.in: Regenerate.
 567         * configure: Regenerate.
 568         * openrisc-asm.c: Delete.
 569         * openrisc-desc.c: Delete.
 570         * openrisc-desc.h: Delete.
 571         * openrisc-dis.c: Delete.
 572         * openrisc-ibld.c: Delete.
 573         * openrisc-opc.c: Delete.
 574         * openrisc-opc.h: Delete.
 575         * or32-dis.c: Delete.
 576         * or32-opc.c: Delete.
 577
 578 2014-04-04  Ilya Tocar  <ilya.tocar@intel.com>
 579
 580         * i386-dis.c (rm_table): Add encls, enclu.
 581         * i386-gen.c (cpu_flag_init): Add CPU_SE1_FLAGS,
 582         (cpu_flags): Add CpuSE1.
 583         * i386-opc.h (enum): Add CpuSE1.
 584         (i386_cpu_flags): Add cpuse1.
 585         * i386-opc.tbl: Add encls, enclu.
 586         * i386-init.h: Regenerated.
 587         * i386-tbl.h: Likewise.
 588
 589 2014-04-02  Anthony Green  <green@moxielogic.com>
 590
 591         * moxie-opc.c (moxie_form1_opc_info): Add sign-extension
 592         instructions, sex.b and sex.s.
 593
 594 2014-03-26  Jiong Wang  <jiong.wang@arm.com>
 595
 596         * aarch64-dis.c (aarch64_ext_ldst_elemlist): Check H/S undefined
 597         instructions.
 598
 599 2014-03-20  Ilya Tocar  <ilya.tocar@intel.com>
 600
 601         * i386-opc.tbl: Change memory size for vgatherpf0qps, vgatherpf1qps,
 602         vscatterpf0qps, vscatterpf1qps, vgatherqps, vpgatherqd, vpscatterqd,
 603         vscatterqps.
 604         * i386-tbl.h: Regenerate.
 605
 606 2014-03-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 607
 608         * sparc-dis.c (v9_hpriv_reg_names): Names for %hstick_offset and
 609         %hstick_enable added.
 610
 611 2014-03-19  Nick Clifton  <nickc@redhat.com>
 612
 613         * rx-decode.opc (bwl): Allow for bogus instructions with a size
 614         field of 3.
 615         (sbwl, ubwl, SCALE): Likewise.
 616         * rx-decode.c: Regenerate.
 617
 618 2014-03-12  Alan Modra  <amodra@gmail.com>
 619
 620         * Makefile.in: Regenerate.
 621
 622 2014-03-05  Alan Modra  <amodra@gmail.com>
 623
 624         Update copyright years.
 625
 626 2014-03-04  Heiher  <r@hev.cc>
 627
 628         * mips-dis.c (mips_arch_choices): Usee ISA_MIPS64R2 for Loongson-3A.
 629
 630 2014-03-04  Richard Sandiford  <rdsandiford@googlemail.com>
 631
 632         * mips-opc.c (mips_builtin_opcodes): Move the udi* instructions
 633         so that they come after the Loongson extensions.
 634
 635 2014-03-03  Alan Modra  <amodra@gmail.com>
 636
 637         * i386-gen.c (process_copyright): Emit copyright notice on one line.
 638
 639 2014-02-28  Alan Modra  <amodra@gmail.com>
 640
 641         * msp430-decode.c: Regenerate.
 642
 643 2014-02-27  Jiong Wang  <jiong.wang@arm.com>
 644
 645         * aarch64-tbl.h (aarch64_opcode_table): Replace IMM0 with
 646         FPIMM0 for fcmeq, fcmgt, fcmge, fcmlt and fcmle.
 647
 648 2014-02-27  Yufeng Zhang  <yufeng.zhang@arm.com>
 649
 650         * aarch64-opc.c (print_register_offset_address): Call
 651         get_int_reg_name to prepare the register name.
 652
 653 2014-02-25  Ilya Tocar  <ilya.tocar@intel.com>
 654
 655         * i386-opc.tbl: Remove wrong variant of vcvtps2ph
 656         * i386-tbl.h: Regenerate.
 657
 658 2014-02-20  Ilya Tocar  <ilya.tocar@intel.com>
 659
 660         * i386-gen.c (cpu_flag_init): Add CPU_PREFETCHWT1_FLAGS/
 661         (cpu_flags): Add CpuPREFETCHWT1.
 662         * i386-init.h: Regenerate.
 663         * i386-opc.h (CpuPREFETCHWT1): New.
 664         (i386_cpu_flags): Add cpuprefetchwt1.
 665         * i386-opc.tbl: Cahnge CPU of prefetchwt1 from CpuAVX512PF to CpuPREFETCHWT1.
 666         * i386-tbl.h: Regenerate.
 667
 668 2014-02-20  Ilya Tocar  <ilya.tocar@intel.com>
 669
 670         * i386-opc.tbl: Change CPU of vptestnmq, vptestnmd from CpuAVX512CD,
 671         to CpuAVX512F.
 672         * i386-tbl.h: Regenerate.
 673
 674 2014-02-19  H.J. Lu  <hongjiu.lu@intel.com>
 675
 676         * i386-gen.c (output_cpu_flags): Don't output trailing space.
 677         (output_opcode_modifier): Likewise.
 678         (output_operand_type): Likewise.
 679         * i386-init.h: Regenerated.
 680         * i386-tbl.h: Likewise.
 681
 682 2014-02-12  Ilya Tocar  <ilya.tocar@intel.com>
 683
 684         * i386-dis.c (MOD enum): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4,
 685         MOD_0FC7_REG_5.
 686         (PREFIX enum): Add PREFIX_0FAE_REG_7.
 687         (reg_table): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4 MOD_0FC7_REG_5.
 688         (prefix_table): Add clflusopt.
 689         (mod_table): Add xrstors, xsavec, xsaves.
 690         * i386-gen.c (cpu_flag_init): Add CPU_CLFLUSHOPT_FLAGS,
 691         CPU_XSAVES_FLAGS, CPU_XSAVEC_FLAGS.
 692         (cpu_flags): Add CpuClflushOpt, CpuXSAVES, CpuXSAVEC.
 693         * i386-init.h: Regenerate.
 694         * i386-opc.tbl: Add clflushopt, xrstors, xrstors64, xsaves,
 695         xsaves64, xsavec, xsavec64.
 696         * i386-tbl.h: Regenerate.
 697
 698 2014-02-10  Alan Modra  <amodra@gmail.com>
 699
 700         * po/POTFILES.in: Regenerate.
 701         * po/opcodes.pot: Regenerate.
 702
 703 2014-01-30  Michael Zolotukhin  <michael.v.zolotukhin@gmail.com>
 704             Jan Beulich  <jbeulich@suse.com>
 705
 706         PR binutils/16490
 707         * i386-dis.c (OP_E_memory): Fix shift computation for
 708         vex_vsib_q_w_dq_mode.
 709
 710 2014-01-09  Bradley Nelson  <bradnelson@google.com>
 711             Roland McGrath  <mcgrathr@google.com>
 712
 713         * i386-dis.c (print_insn): Do not touch all_prefixes[-1] when
 714         last_rex_prefix is -1.
 715
 716 2014-01-08  H.J. Lu  <hongjiu.lu@intel.com>
 717
 718         * i386-gen.c (process_copyright): Update copyright year to 2014.
 719
 720 2014-01-03  Maciej W. Rozycki  <macro@codesourcery.com>
 721
 722         * nds32-asm.c (parse_operand): Fix out-of-range integer constant.
 723
 724 For older changes see ChangeLog-2013
 725 \f
 726 Copyright (C) 2014 Free Software Foundation, Inc.
 727
 728 Copying and distribution of this file, with or without modification,
 729 are permitted in any medium without royalty provided the copyright
 730 notice and this notice are preserved.
 731
 732 Local Variables:
 733 mode: change-log
 734 left-margin: 8
 735 fill-column: 74
 736 version-control: never
 737 End: