1 2021-03-11 Jan Beulich <jbeulich@suse.com>
3 * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
4 checks. Move case label past broadcast check.
6 2021-03-10 Jan Beulich <jbeulich@suse.com>
8 * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
9 vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
10 REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
11 EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
12 EVEX_W_0F38C7_M_0_L_2): Delete.
13 (REG_EVEX_0F38C7_M_0_L_2): New.
14 (intel_operand_size): Handle VEX and EVEX the same for
15 vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
16 vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
17 (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
18 vex_vsib_q_w_d_mode uses.
19 * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
20 0F38A1, and 0F38A3 entries.
21 * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
23 * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
24 * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
27 2021-03-10 Jan Beulich <jbeulich@suse.com>
29 * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
30 REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
31 MOD_VEX_0FXOP_09_12): Rename to ...
32 (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
33 REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
34 (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
35 RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
36 X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
37 X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
38 (reg_table): Adjust comments.
39 (x86_64_table): Move X86_64_0F24, X86_64_0F26,
40 X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
41 X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
42 (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
43 (vex_len_table): Adjust opcode 0A_12 entry.
44 (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
45 MOD_C5_32BIT, and MOD_XOP_09_12 entries.
46 (rm_table): Move hreset entry.
48 2021-03-10 Jan Beulich <jbeulich@suse.com>
50 * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
51 EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
52 EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
53 EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
54 EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
55 (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
56 (get_valid_dis386): Also handle 512-bit vector length when
57 vectoring into vex_len_table[].
58 * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
59 0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
61 * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
62 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
63 * i386-dis-evex-prefix.h: Adjust 0F7E entry.
64 * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
67 2021-03-10 Jan Beulich <jbeulich@suse.com>
69 * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
70 Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
71 EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
72 * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
74 * i386-dis-evex-len.h (evex_len_table): Likewise.
75 * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
77 2021-03-10 Jan Beulich <jbeulich@suse.com>
79 * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
80 MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
81 MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
82 MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
83 MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
84 MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
85 MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
86 MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
87 EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
88 EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
89 EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
90 EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
91 EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
92 EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
93 EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
94 EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
95 EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
96 EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
97 EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
98 EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
99 EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
100 EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
101 EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
102 EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
103 EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
104 EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
105 EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
106 EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
107 EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
108 EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
109 EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
110 EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
111 REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
112 REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
113 MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
114 MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
115 EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
116 EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
117 EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
118 EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
119 EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
120 EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
121 EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
122 EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
123 EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
124 EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
125 EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
126 EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
127 EVEX_W_0F3A43_L_n): New.
128 * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
129 0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
130 0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
131 * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
132 for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
133 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
134 0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
135 * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
136 0F385B, 0F38C6, and 0F38C7 entries.
137 * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
139 * i386-dis-evex-w.h: No longer link to evex_len_table[] for
140 opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
141 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
142 evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
144 2021-03-10 Jan Beulich <jbeulich@suse.com>
146 * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
147 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
148 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
149 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
150 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
151 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
152 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
153 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
154 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
155 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
156 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
157 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
158 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
159 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
160 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
161 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
162 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
163 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
164 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
165 MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
166 MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
167 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
168 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
169 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
170 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
171 PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
172 PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
173 PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
174 PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
175 PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
176 VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
177 VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
178 VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
179 VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
180 VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
181 VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
182 VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
183 VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
184 VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
185 VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
186 VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
187 VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
188 VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
189 VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
190 VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
191 VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
192 VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
193 VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
194 VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
195 VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
196 VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
197 VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
198 VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
199 VEX_W_0F99_P_2_LEN_0): Delete.
200 MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
201 MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
202 MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
203 MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
204 MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
205 PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
206 PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
207 PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
208 PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
209 PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
210 PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
211 PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
212 PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
213 PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
214 PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
215 PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
216 PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
217 PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
218 PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
219 VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
220 VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
221 VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
222 VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
223 VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
224 VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
225 VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
226 VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
227 (prefix_table): No longer link to vex_len_table[] for opcodes
228 0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
229 0F92, 0F93, 0F98, and 0F99.
230 (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
231 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
233 (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
234 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
236 (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
237 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
239 (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
240 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
243 2021-03-10 Jan Beulich <jbeulich@suse.com>
245 * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
246 Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
247 REG_VEX_0F73_M_0 respectively.
248 (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
249 MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
250 MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
251 MOD_VEX_0F73_REG_7): Delete.
252 (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
253 (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
254 PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
255 PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
256 PREFIX_VEX_0F3AF0_L_0 respectively.
257 (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
258 VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
259 VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
260 VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
261 (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
262 VEX_LEN_0F38F7): New.
263 (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
264 (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
265 0F72, and 0F73. No longer link to vex_len_table[] for opcode
267 (prefix_table): No longer link to vex_len_table[] for opcodes
268 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
269 (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
270 0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
271 0F38F6, 0F38F7, and 0F3AF0.
272 (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
273 prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
274 (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
277 2021-03-10 Jan Beulich <jbeulich@suse.com>
279 * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
280 REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
281 (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
282 MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
283 MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
284 (MOD_0F71, MOD_0F72, MOD_0F73): New.
285 (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
287 (reg_table): No longer link to mod_table[] for opcodes 0F71,
289 (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
292 2021-03-10 Jan Beulich <jbeulich@suse.com>
294 * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
295 MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
296 (reg_table): Don't link to mod_table[] where not needed. Add
297 PREFIX_IGNORED to nop entries.
298 (prefix_table): Replace PREFIX_OPCODE in nop entries.
299 (mod_table): Add nop entries next to prefetch ones. Drop
300 MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
301 MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
302 (rm_table): Add PREFIX_IGNORED to nop entries. Drop
303 PREFIX_OPCODE from endbr* entries.
304 (get_valid_dis386): Also consider entry's name when zapping
306 (print_insn): Handle PREFIX_IGNORED.
308 2021-03-09 Jan Beulich <jbeulich@suse.com>
310 * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
311 IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
313 * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
314 HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
315 (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
316 PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
317 (struct i386_opcode_modifier): Delete notrackprefixok,
318 islockable, hleprefixok, and repprefixok fields. Add prefixok
320 * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
321 HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
322 (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
323 not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
325 * opcodes/i386-tbl.h: Re-generate.
327 2021-03-09 Jan Beulich <jbeulich@suse.com>
329 * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
330 * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
332 * opcodes/i386-tbl.h: Re-generate.
334 2021-03-03 Jan Beulich <jbeulich@suse.com>
336 * i386-gen.c (output_i386_opcode): Don't get operand count. Look
337 for {} instead of {0}. Don't look for '0'.
338 * i386-opc.tbl: Drop operand count field. Drop redundant operand
341 2021-02-19 Nelson Chu <nelson.chu@sifive.com>
344 * riscv-dis.c (print_insn_args): Updated encoding macros.
345 * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
346 (match_c_addi16sp): Updated encoding macros.
347 (match_c_lui): Likewise.
348 (match_c_lui_with_hint): Likewise.
349 (match_c_addi4spn): Likewise.
350 (match_c_slli): Likewise.
351 (match_slli_as_c_slli): Likewise.
352 (match_c_slli64): Likewise.
353 (match_srxi_as_c_srxi): Likewise.
354 (riscv_insn_types): Added .insn css/cl/cs.
356 2021-02-18 Nelson Chu <nelson.chu@sifive.com>
358 * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
359 (default_priv_spec): Updated type to riscv_spec_class.
360 (parse_riscv_dis_option): Updated.
361 * riscv-opc.c: Moved stuff and make the file tidy.
363 2021-02-17 Alan Modra <amodra@gmail.com>
365 * wasm32-dis.c: Include limits.h.
366 (CHAR_BIT): Provide backup define.
367 (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
368 Correct signed overflow checking.
370 2021-02-16 Jan Beulich <jbeulich@suse.com>
372 * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
373 * i386-tbl.h: Re-generate.
375 2021-02-16 Jan Beulich <jbeulich@suse.com>
377 * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
379 * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
381 2021-02-15 Andreas Krebbel <krebbel@linux.ibm.com>
383 * s390-mkopc.c (main): Accept arch14 as cpu string.
384 * s390-opc.txt: Add new arch14 instructions.
386 2021-02-04 Nick Alcock <nick.alcock@oracle.com>
388 * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
390 * configure: Regenerated.
392 2021-02-08 Mike Frysinger <vapier@gentoo.org>
394 * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
395 * tic54x-opc.c (regs): Rename to ...
396 (tic54x_regs): ... this.
397 (mmregs): Rename to ...
398 (tic54x_mmregs): ... this.
399 (condition_codes): Rename to ...
400 (tic54x_condition_codes): ... this.
401 (cc2_codes): Rename to ...
402 (tic54x_cc2_codes): ... this.
403 (cc3_codes): Rename to ...
404 (tic54x_cc3_codes): ... this.
405 (status_bits): Rename to ...
406 (tic54x_status_bits): ... this.
407 (misc_symbols): Rename to ...
408 (tic54x_misc_symbols): ... this.
410 2021-02-04 Nelson Chu <nelson.chu@sifive.com>
412 * riscv-opc.c (MASK_RVB_IMM): Removed.
413 (riscv_opcodes): Removed zb* instructions.
414 (riscv_ext_version_table): Removed versions for zb*.
416 2021-01-26 Alan Modra <amodra@gmail.com>
418 * i386-gen.c (parse_template): Ensure entire template_instance
421 2021-01-15 Nelson Chu <nelson.chu@sifive.com>
423 * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
424 (riscv_fpr_names_abi): Likewise.
425 (riscv_opcodes): Likewise.
426 (riscv_insn_types): Likewise.
428 2021-01-15 Nelson Chu <nelson.chu@sifive.com>
430 * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
432 2021-01-15 Nelson Chu <nelson.chu@sifive.com>
434 * riscv-dis.c: Comments tidy and improvement.
435 * riscv-opc.c: Likewise.
437 2021-01-13 Alan Modra <amodra@gmail.com>
439 * Makefile.in: Regenerate.
441 2021-01-12 H.J. Lu <hongjiu.lu@intel.com>
444 * configure.ac: Use GNU_MAKE_JOBSERVER.
445 * aclocal.m4: Regenerated.
446 * configure: Likewise.
448 2021-01-12 Nick Clifton <nickc@redhat.com>
450 * po/sr.po: Updated Serbian translation.
452 2021-01-11 H.J. Lu <hongjiu.lu@intel.com>
455 * configure: Regenerated.
457 2021-01-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
459 * aarch64-asm-2.c: Regenerate.
460 * aarch64-dis-2.c: Likewise.
461 * aarch64-opc-2.c: Likewise.
462 * aarch64-opc.c (aarch64_print_operand):
463 Delete handling of AARCH64_OPND_CSRE_CSR.
464 * aarch64-tbl.h (aarch64_feature_csre): Delete.
466 (_CSRE_INSN): Likewise.
467 (aarch64_opcode_table): Delete csr.
469 2021-01-11 Nick Clifton <nickc@redhat.com>
471 * po/de.po: Updated German translation.
472 * po/fr.po: Updated French translation.
473 * po/pt_BR.po: Updated Brazilian Portuguese translation.
474 * po/sv.po: Updated Swedish translation.
475 * po/uk.po: Updated Ukranian translation.
477 2021-01-09 H.J. Lu <hongjiu.lu@intel.com>
479 * configure: Regenerated.
481 2021-01-09 Nick Clifton <nickc@redhat.com>
483 * configure: Regenerate.
484 * po/opcodes.pot: Regenerate.
486 2021-01-09 Nick Clifton <nickc@redhat.com>
488 * 2.36 release branch crated.
490 2021-01-08 Peter Bergner <bergner@linux.ibm.com>
492 * ppc-opc.c (insert_dw, (extract_dw): New functions.
493 (DW, (XRC_MASK): Define.
494 (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
496 2021-01-09 Alan Modra <amodra@gmail.com>
498 * configure: Regenerate.
500 2021-01-08 Nick Clifton <nickc@redhat.com>
502 * po/sv.po: Updated Swedish translation.
504 2021-01-08 Nick Clifton <nickc@redhat.com>
507 * aarch64-dis.c (determine_disassembling_preference): Move call to
508 aarch64_match_operands_constraint outside of the assertion.
509 * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
510 Replace with a return of FALSE.
513 * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
514 core system register.
516 2021-01-07 Samuel Thibault <samuel.thibault@gnu.org>
518 * configure: Regenerate.
520 2021-01-07 Nick Clifton <nickc@redhat.com>
522 * po/fr.po: Updated French translation.
524 2021-01-07 Fredrik Noring <noring@nocrew.org>
526 * m68k-opc.c (chkl): Change minimum architecture requirement to
529 2021-01-07 Philipp Tomsich <prt@gnu.org>
531 * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
533 2021-01-07 Claire Xenia Wolf <claire@symbioticeda.com>
534 Jim Wilson <jimw@sifive.com>
535 Andrew Waterman <andrew@sifive.com>
536 Maxim Blinov <maxim.blinov@embecosm.com>
537 Kito Cheng <kito.cheng@sifive.com>
538 Nelson Chu <nelson.chu@sifive.com>
540 * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
541 (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
543 2021-01-01 Alan Modra <amodra@gmail.com>
545 Update year range in copyright notice of all files.
547 For older changes see ChangeLog-2020
549 Copyright (C) 2021 Free Software Foundation, Inc.
551 Copying and distribution of this file, with or without modification,
552 are permitted in any medium without royalty provided the copyright
553 notice and this notice are preserved.
559 version-control: never