opcodes/ChangeLog

   1 2016-06-28  Richard Sandiford  <richard.sandiford@arm.com>
   2
   3         * aarch64-opc.c (operand_general_constraint_met_p): Check the
   4         range of ldst_elemlist operands.
   5         (print_register_list): Use PRIi64 to print the index.
   6         (aarch64_print_operand): Likewise.
   7
   8 2016-06-25  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
   9
  10         * mcore-opc.h: Remove sentinal.
  11         * mcore-dis.c (print_insn_mcore): Adjust.
  12
  13 2016-06-23  Graham Markall  <graham.markall@embecosm.com>
  14
  15         * arc-opc.c: Correct description of availability of NPS400
  16         features.
  17
  18 2016-06-22  Peter Bergner <bergner@vnet.ibm.com>
  19
  20         * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
  21         (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
  22         mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
  23         xor3>: New mnemonics.
  24         <setb>: Change to a VX form instruction.
  25         (insert_sh6): Add support for rldixor.
  26         (extract_sh6): Likewise.
  27
  28 2016-06-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
  29
  30         * arc-ext.h: Wrap in extern C.
  31
  32 2016-06-21  Graham Markall  <graham.markall@embecosm.com>
  33
  34         * arc-dis.c (arc_insn_length): Add comment on instruction length.
  35         Use same method for determining instruction length on ARC700 and
  36         NPS-400.
  37         (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
  38         * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
  39         with the NPS400 subclass.
  40         * arc-opc.c: Likewise.
  41
  42 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
  43
  44         * sparc-opc.c (rdasr): New macro.
  45         (wrasr): Likewise.
  46         (rdpr): Likewise.
  47         (wrpr): Likewise.
  48         (rdhpr): Likewise.
  49         (wrhpr): Likewise.
  50         (sparc_opcodes): Use the macros above to fix and expand the
  51         definition of read/write instructions from/to
  52         asr/privileged/hyperprivileged instructions.
  53         * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
  54         %hva_mask_nz.  Prefer softint_set and softint_clear over
  55         set_softint and clear_softint.
  56         (print_insn_sparc): Support %ver in Rd.
  57
  58 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
  59
  60         * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
  61         architecture according to the hardware capabilities they require.
  62
  63 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
  64
  65         * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
  66         (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
  67         bfd_mach_sparc_v9{c,d,e,v,m}.
  68         * sparc-opc.c (MASK_V9C): Define.
  69         (MASK_V9D): Likewise.
  70         (MASK_V9E): Likewise.
  71         (MASK_V9V): Likewise.
  72         (MASK_V9M): Likewise.
  73         (v6): Add MASK_V9{C,D,E,V,M}.
  74         (v6notlet): Likewise.
  75         (v7): Likewise.
  76         (v8): Likewise.
  77         (v9): Likewise.
  78         (v9andleon): Likewise.
  79         (v9a): Likewise.
  80         (v9b): Likewise.
  81         (v9c): Define.
  82         (v9d): Likewise.
  83         (v9e): Likewise.
  84         (v9v): Likewise.
  85         (v9m): Likewise.
  86         (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
  87
  88 2016-06-15  Nick Clifton  <nickc@redhat.com>
  89
  90         * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
  91         constants to match expected behaviour.
  92         (nds32_parse_opcode): Likewise.  Also for whitespace.
  93
  94 2016-06-15  Andrew Burgess  <andrew.burgess@embecosm.com>
  95
  96         * arc-opc.c (extract_rhv1): Extract value from insn.
  97
  98 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
  99
 100         * arc-nps400-tbl.h: Add ldbit instruction.
 101         * arc-opc.c: Add flag classes required for ldbit.
 102
 103 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 104
 105         * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
 106         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
 107         support the above instructions.
 108
 109 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 110
 111         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
 112         imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
 113         csma, cbba, zncv, and hofs.
 114         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
 115         support the above instructions.
 116
 117 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 118
 119         * arc-nps400-tbl.h: Add andab and orab instructions.
 120
 121 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 122
 123         * arc-nps400-tbl.h: Add addl-like instructions.
 124
 125 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 126
 127         * arc-nps400-tbl.h: Add mxb and imxb instructions.
 128
 129 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 130
 131         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
 132         instructions.
 133
 134 2016-06-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 135
 136         * s390-dis.c (option_use_insn_len_bits_p): New file scope
 137         variable.
 138         (init_disasm): Handle new command line option "insnlength".
 139         (print_s390_disassembler_options): Mention new option in help
 140         output.
 141         (print_insn_s390): Use the encoded insn length when dumping
 142         unknown instructions.
 143
 144 2016-06-03  Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
 145
 146         * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
 147          to the address and set as symbol address for LDS/ STS immediate operands.
 148
 149 2016-06-07  Alan Modra  <amodra@gmail.com>
 150
 151         * ppc-dis.c (ppc_opts): Delete extraneous parentheses.  Default
 152         cpu for "vle" to e500.
 153         * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
 154         (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
 155         (PPCNONE): Delete, substitute throughout.
 156         (powerpc_opcodes): Remove PPCVLE from "flags".  Add to "deprecated"
 157         except for major opcode 4 and 31.
 158         (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
 159
 160 2016-06-07  Matthew Wahab  <matthew.wahab@arm.com>
 161
 162         * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
 163         ARM_EXT_RAS in relevant entries.
 164
 165 2016-06-03  Peter Bergner <bergner@vnet.ibm.com>
 166
 167         PR binutils/20196
 168         * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
 169         opcodes for E6500.
 170
 171 2016-06-03  H.J. Lu  <hongjiu.lu@intel.com>
 172
 173         PR binutis/18386
 174         * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
 175         (indir_v_mode): New.
 176         Add comments for '&'.
 177         (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
 178         (putop): Handle '&'.
 179         (intel_operand_size): Handle indir_v_mode.
 180         (OP_E_register): Likewise.
 181         * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64.  Add
 182         64-bit indirect call/jmp for AMD64.
 183         * i386-tbl.h: Regenerated
 184
 185 2016-06-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 186
 187         * arc-dis.c (struct arc_operand_iterator): New structure.
 188         (find_format_from_table): All the old content from find_format,
 189         with some minor adjustments, and parameter renaming.
 190         (find_format_long_instructions): New function.
 191         (find_format): Rewritten.
 192         (arc_insn_length): Add LSB parameter.
 193         (extract_operand_value): New function.
 194         (operand_iterator_next): New function.
 195         (print_insn_arc): Use new functions to find opcode, and iterator
 196         over operands.
 197         * arc-opc.c (insert_nps_3bit_dst_short): New function.
 198         (extract_nps_3bit_dst_short): New function.
 199         (insert_nps_3bit_src2_short): New function.
 200         (extract_nps_3bit_src2_short): New function.
 201         (insert_nps_bitop1_size): New function.
 202         (extract_nps_bitop1_size): New function.
 203         (insert_nps_bitop2_size): New function.
 204         (extract_nps_bitop2_size): New function.
 205         (insert_nps_bitop_mod4_msb): New function.
 206         (extract_nps_bitop_mod4_msb): New function.
 207         (insert_nps_bitop_mod4_lsb): New function.
 208         (extract_nps_bitop_mod4_lsb): New function.
 209         (insert_nps_bitop_dst_pos3_pos4): New function.
 210         (extract_nps_bitop_dst_pos3_pos4): New function.
 211         (insert_nps_bitop_ins_ext): New function.
 212         (extract_nps_bitop_ins_ext): New function.
 213         (arc_operands): Add new operands.
 214         (arc_long_opcodes): New global array.
 215         (arc_num_long_opcodes): New global.
 216         * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
 217
 218 2016-06-01  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 219
 220         * nds32-asm.h: Add extern "C".
 221         * sh-opc.h: Likewise.
 222
 223 2016-06-01  Graham Markall  <graham.markall@embecosm.com>
 224
 225         * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
 226         0,b,limm to the rflt instruction.
 227
 228 2016-05-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 229
 230         * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
 231         constant.
 232
 233 2016-05-29  H.J. Lu  <hongjiu.lu@intel.com>
 234
 235         PR gas/20145
 236         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
 237         CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
 238         CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
 239         CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
 240         CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
 241         * i386-init.h: Regenerated.
 242
 243 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 244
 245         PR gas/20145
 246         * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS.  Remove
 247         CpuMMX from CPU_SSE_FLAGS.  Remove AVX and AVX512 bits from
 248         CPU_ANY_SSE_FLAGS.  Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
 249         Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
 250         CpuXSAVEC.  Add CPU_AVX_FLAGS to CpuF16C.  Remove CpuMMX from
 251         CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
 252         CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
 253         Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS.   Add CPU_ANY_287_FLAGS,
 254         CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
 255         CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
 256         CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS.  Enable CpuRegMMX
 257         for MMX.  Enable CpuRegXMM for SSE, AVX and AVX512.  Enable
 258         CpuRegYMM for AVX and AVX512VL,  Enable CpuRegZMM and
 259         CpuRegMask for AVX512.
 260         (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
 261         and CpuRegMask.
 262         (set_bitfield_from_cpu_flag_init): New function.
 263         (set_bitfield): Remove const on f.  Call
 264         set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
 265         * i386-opc.h (CpuRegMMX): New.
 266         (CpuRegXMM): Likewise.
 267         (CpuRegYMM): Likewise.
 268         (CpuRegZMM): Likewise.
 269         (CpuRegMask): Likewise.
 270         (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
 271         and cpuregmask.
 272         * i386-init.h: Regenerated.
 273         * i386-tbl.h: Likewise.
 274
 275 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 276
 277         PR gas/20154
 278         * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
 279         (opcode_modifiers): Add AMD64 and Intel64.
 280         (main): Properly verify CpuMax.
 281         * i386-opc.h (CpuAMD64): Removed.
 282         (CpuIntel64): Likewise.
 283         (CpuMax): Set to CpuNo64.
 284         (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
 285         (AMD64): New.
 286         (Intel64): Likewise.
 287         (i386_opcode_modifier): Add amd64 and intel64.
 288         (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
 289         on call and jmp.
 290         * i386-init.h: Regenerated.
 291         * i386-tbl.h: Likewise.
 292
 293 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 294
 295         PR gas/20154
 296         * i386-gen.c (main): Fail if CpuMax is incorrect.
 297         * i386-opc.h (CpuMax): Set to CpuIntel64.
 298         * i386-tbl.h: Regenerated.
 299
 300 2016-05-27  Nick Clifton  <nickc@redhat.com>
 301
 302         PR target/20150
 303         * msp430-dis.c (msp430dis_read_two_bytes): New function.
 304         (msp430dis_opcode_unsigned): New function.
 305         (msp430dis_opcode_signed): New function.
 306         (msp430_singleoperand): Use the new opcode reading functions.
 307         Only disassenmble bytes if they were successfully read.
 308         (msp430_doubleoperand): Likewise.
 309         (msp430_branchinstr): Likewise.
 310         (msp430x_callx_instr): Likewise.
 311         (print_insn_msp430): Check that it is safe to read bytes before
 312         attempting disassembly.  Use the new opcode reading functions.
 313
 314 2016-05-26  Peter Bergner <bergner@vnet.ibm.com>
 315
 316         * ppc-opc.c (CY): New define.  Document it.
 317         (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
 318
 319 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 320
 321         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
 322         CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
 323         and CPU_AVX512VBMI_FLAGS.  Add CpuAVX512DQ, CpuAVX512BW,
 324         CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
 325         CPU_ANY_AVX_FLAGS.
 326         * i386-init.h: Regenerated.
 327
 328 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 329
 330         PR gas/20141
 331         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
 332         CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
 333         * i386-init.h: Regenerated.
 334
 335 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 336
 337         * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
 338         CPU_ANY_X87_FLAGS.  Add CPU_ANY_MMX_FLAGS.
 339         * i386-init.h: Regenerated.
 340
 341 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
 342
 343         * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
 344         information.
 345         (print_insn_arc): Set insn_type information.
 346         * arc-opc.c (C_CC): Add F_CLASS_COND.
 347         * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
 348         (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
 349         (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
 350         (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
 351         (brne, brne_s, jeq_s, jne_s): Likewise.
 352
 353 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
 354
 355         * arc-tbl.h (neg): New instruction variant.
 356
 357 2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>
 358
 359         * arc-dis.c (find_format, find_format, get_auxreg)
 360         (print_insn_arc): Changed.
 361         * arc-ext.h (INSERT_XOP): Likewise.
 362
 363 2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 364
 365         * tic54x-dis.c (sprint_mmr): Adjust.
 366         * tic54x-opc.c: Likewise.
 367
 368 2016-05-19  Alan Modra  <amodra@gmail.com>
 369
 370         * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
 371
 372 2016-05-19  Alan Modra  <amodra@gmail.com>
 373
 374         * ppc-opc.c: Formatting.
 375         (NSISIGNOPT): Define.
 376         (powerpc_opcodes <subis>): Use NSISIGNOPT.
 377
 378 2016-05-18  Maciej W. Rozycki  <macro@imgtec.com>
 379
 380         * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
 381         replacing references to `micromips_ase' throughout.
 382         (_print_insn_mips): Don't use file-level microMIPS annotation to
 383         determine the disassembly mode with the symbol table.
 384
 385 2016-05-13  Peter Bergner <bergner@vnet.ibm.com>
 386
 387         * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
 388
 389 2016-05-11  Andrew Bennett  <andrew.bennett@imgtec.com>
 390
 391         * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
 392         mips64r6.
 393         * mips-opc.c (D34): New macro.
 394         (mips_builtin_opcodes): Define bposge32c for DSPr3.
 395
 396 2016-05-10  Alexander Fomin  <alexander.fomin@intel.com>
 397
 398         * i386-dis.c (prefix_table): Add RDPID instruction.
 399         * i386-gen.c (cpu_flag_init): Add RDPID flag.
 400         (cpu_flags): Add RDPID bitfield.
 401         * i386-opc.h (enum): Add RDPID element.
 402         (i386_cpu_flags): Add RDPID field.
 403         * i386-opc.tbl: Add RDPID instruction.
 404         * i386-init.h: Regenerate.
 405         * i386-tbl.h: Regenerate.
 406
 407 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 408
 409         * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
 410         branch type of a symbol.
 411         (print_insn): Likewise.
 412
 413 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 414
 415         * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
 416         Mainline Security Extensions instructions.
 417         (thumb_opcodes): Add entries for narrow ARMv8-M Security
 418         Extensions instructions.
 419         (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
 420         instructions.
 421         (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
 422         special registers.
 423
 424 2016-05-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
 425
 426         * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
 427
 428 2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>
 429
 430         * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
 431         (arcExtMap_genOpcode): Likewise.
 432         * arc-opc.c (arg_32bit_rc): Define new variable.
 433         (arg_32bit_u6): Likewise.
 434         (arg_32bit_limm): Likewise.
 435
 436 2016-05-03  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 437
 438         * aarch64-gen.c (VERIFIER): Define.
 439         * aarch64-opc.c (VERIFIER): Define.
 440         (verify_ldpsw): Use static linkage.
 441         * aarch64-opc.h (verify_ldpsw): Remove.
 442         * aarch64-tbl.h: Use VERIFIER for verifiers.
 443
 444 2016-04-28  Nick Clifton  <nickc@redhat.com>
 445
 446         PR target/19722
 447         * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
 448         * aarch64-opc.c (verify_ldpsw): New function.
 449         * aarch64-opc.h (verify_ldpsw): New prototype.
 450         * aarch64-tbl.h: Add initialiser for verifier field.
 451         (LDPSW): Set verifier to verify_ldpsw.
 452
 453 2016-04-23  H.J. Lu  <hongjiu.lu@intel.com>
 454
 455         PR binutils/19983
 456         PR binutils/19984
 457         * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
 458         smaller than address size.
 459
 460 2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 461
 462         * alpha-dis.c: Regenerate.
 463         * crx-dis.c: Likewise.
 464         * disassemble.c: Likewise.
 465         * epiphany-opc.c: Likewise.
 466         * fr30-opc.c: Likewise.
 467         * frv-opc.c: Likewise.
 468         * ip2k-opc.c: Likewise.
 469         * iq2000-opc.c: Likewise.
 470         * lm32-opc.c: Likewise.
 471         * lm32-opinst.c: Likewise.
 472         * m32c-opc.c: Likewise.
 473         * m32r-opc.c: Likewise.
 474         * m32r-opinst.c: Likewise.
 475         * mep-opc.c: Likewise.
 476         * mt-opc.c: Likewise.
 477         * or1k-opc.c: Likewise.
 478         * or1k-opinst.c: Likewise.
 479         * tic80-opc.c: Likewise.
 480         * xc16x-opc.c: Likewise.
 481         * xstormy16-opc.c: Likewise.
 482
 483 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
 484
 485         * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
 486         fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
 487         calcsd, and calcxd instructions.
 488         * arc-opc.c (insert_nps_bitop_size): Delete.
 489         (extract_nps_bitop_size): Delete.
 490         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
 491         (extract_nps_qcmp_m3): Define.
 492         (extract_nps_qcmp_m2): Define.
 493         (extract_nps_qcmp_m1): Define.
 494         (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
 495         (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
 496         (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
 497         NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
 498         NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
 499         NPS_QCMP_M3.
 500
 501 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
 502
 503         * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
 504
 505 2016-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 506
 507         * Makefile.in: Regenerated with automake 1.11.6.
 508         * aclocal.m4: Likewise.
 509
 510 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
 511
 512         * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
 513         instructions.
 514         * arc-opc.c (insert_nps_cmem_uimm16): New function.
 515         (extract_nps_cmem_uimm16): New function.
 516         (arc_operands): Add NPS_XLDST_UIMM16 operand.
 517
 518 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
 519
 520         * arc-dis.c (arc_insn_length): New function.
 521         (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
 522         (find_format): Change insnLen parameter to unsigned.
 523
 524 2016-04-13  Nick Clifton  <nickc@redhat.com>
 525
 526         PR target/19937
 527         * v850-opc.c (v850_opcodes): Correct masks for long versions of
 528         the LD.B and LD.BU instructions.
 529
 530 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 531
 532         * arc-dis.c (find_format): Check for extension flags.
 533         (print_flags): New function.
 534         (print_insn_arc): Update for .extCondCode, .extCoreRegister and
 535         .extAuxRegister.
 536         * arc-ext.c (arcExtMap_coreRegName): Use
 537         LAST_EXTENSION_CORE_REGISTER.
 538         (arcExtMap_coreReadWrite): Likewise.
 539         (dump_ARC_extmap): Update printing.
 540         * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
 541         (arc_aux_regs): Add cpu field.
 542         * arc-regs.h: Add cpu field, lower case name aux registers.
 543
 544 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 545
 546         * arc-tbl.h: Add rtsc, sleep with no arguments.
 547
 548 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 549
 550         * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
 551         Initialize.
 552         (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
 553         (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
 554         (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
 555         (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
 556         (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
 557         (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
 558         (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
 559         (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
 560         (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
 561         (arc_opcode arc_opcodes): Null terminate the array.
 562         (arc_num_opcodes): Remove.
 563         * arc-ext.h (INSERT_XOP): Define.
 564         (extInstruction_t): Likewise.
 565         (arcExtMap_instName): Delete.
 566         (arcExtMap_insn): New function.
 567         (arcExtMap_genOpcode): Likewise.
 568         * arc-ext.c (ExtInstruction): Remove.
 569         (create_map): Zero initialize instruction fields.
 570         (arcExtMap_instName): Remove.
 571         (arcExtMap_insn): New function.
 572         (dump_ARC_extmap): More info while debuging.
 573         (arcExtMap_genOpcode): New function.
 574         * arc-dis.c (find_format): New function.
 575         (print_insn_arc): Use find_format.
 576         (arc_get_disassembler): Enable dump_ARC_extmap only when
 577         debugging.
 578
 579 2016-04-11  Maciej W. Rozycki  <macro@imgtec.com>
 580
 581         * mips-dis.c (print_mips16_insn_arg): Mask unused extended
 582         instruction bits out.
 583
 584 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
 585
 586         * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
 587         * arc-opc.c (arc_flag_operands): Add new flags.
 588         (arc_flag_classes): Add new classes.
 589
 590 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
 591
 592         * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
 593
 594 2016-04-05  Andrew Burgess  <andrew.burgess@embecosm.com>
 595
 596         * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
 597         encode1, rflt, crc16, and crc32 instructions.
 598         * arc-opc.c (arc_flag_operands): Add F_NPS_R.
 599         (arc_flag_classes): Add C_NPS_R.
 600         (insert_nps_bitop_size_2b): New function.
 601         (extract_nps_bitop_size_2b): Likewise.
 602         (insert_nps_bitop_uimm8): Likewise.
 603         (extract_nps_bitop_uimm8): Likewise.
 604         (arc_operands): Add new operand entries.
 605
 606 2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>
 607
 608         * arc-regs.h: Add a new subclass field.  Add double assist
 609         accumulator register values.
 610         * arc-tbl.h: Use DPA subclass to mark the double assist
 611         instructions.  Use DPX/SPX subclas to mark the FPX instructions.
 612         * arc-opc.c (RSP): Define instead of SP.
 613         (arc_aux_regs): Add the subclass field.
 614
 615 2016-04-05  Jiong Wang  <jiong.wang@arm.com>
 616
 617         * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
 618
 619 2016-03-31  Andrew Burgess  <andrew.burgess@embecosm.com>
 620
 621         * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
 622         NPS_R_SRC1.
 623
 624 2016-03-30  Andrew Burgess  <andrew.burgess@embecosm.com>
 625
 626         * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
 627         issues.  No functional changes.
 628
 629 2016-03-30  Claudiu Zissulescu  <claziss@synopsys.com>
 630
 631         * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
 632         (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
 633         (RTT): Remove duplicate.
 634         (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
 635         (PCT_CONFIG*): Remove.
 636         (D1L, D1H, D2H, D2L): Define.
 637
 638 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
 639
 640         * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
 641
 642 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
 643
 644         * arc-tbl.h (invld07): Remove.
 645         * arc-ext-tbl.h: New file.
 646         * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
 647         * arc-opc.c (arc_opcodes): Add ext-tbl include.
 648
 649 2016-03-24  Jan Kratochvil  <jan.kratochvil@redhat.com>
 650
 651         Fix -Wstack-usage warnings.
 652         * aarch64-dis.c (print_operands): Substitute size.
 653         * aarch64-opc.c (print_register_offset_address): Substitute tblen.
 654
 655 2016-03-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
 656
 657         * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
 658         to get a proper diagnostic when an invalid ASR register is used.
 659
 660 2016-03-22  Nick Clifton  <nickc@redhat.com>
 661
 662         * configure: Regenerate.
 663
 664 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 665
 666         * arc-nps400-tbl.h: New file.
 667         * arc-opc.c: Add top level comment.
 668         (insert_nps_3bit_dst): New function.
 669         (extract_nps_3bit_dst): New function.
 670         (insert_nps_3bit_src2): New function.
 671         (extract_nps_3bit_src2): New function.
 672         (insert_nps_bitop_size): New function.
 673         (extract_nps_bitop_size): New function.
 674         (arc_flag_operands): Add nps400 entries.
 675         (arc_flag_classes): Add nps400 entries.
 676         (arc_operands): Add nps400 entries.
 677         (arc_opcodes): Add nps400 include.
 678
 679 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 680
 681         * arc-opc.c (arc_flag_classes): Convert all flag classes to use
 682         the new class enum values.
 683
 684 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 685
 686         * arc-dis.c (print_insn_arc): Handle nps400.
 687
 688 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 689
 690         * arc-opc.c (BASE): Delete.
 691
 692 2016-03-18  Nick Clifton  <nickc@redhat.com>
 693
 694         PR target/19721
 695         * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
 696         of MOV insn that aliases an ORR insn.
 697
 698 2016-03-16  Jiong Wang  <jiong.wang@arm.com>
 699
 700         * arm-dis.c (neon_opcodes): Support new FP16 instructions.
 701
 702 2016-03-07  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 703
 704         * mcore-opc.h: Add const qualifiers.
 705         * microblaze-opc.h (struct op_code_struct): Likewise.
 706         * sh-opc.h: Likewise.
 707         * tic4x-dis.c (tic4x_print_indirect): Likewise.
 708         (tic4x_print_op): Likewise.
 709
 710 2016-03-02  Alan Modra  <amodra@gmail.com>
 711
 712         * or1k-desc.h: Regenerate.
 713         * fr30-ibld.c: Regenerate.
 714         * rl78-decode.c: Regenerate.
 715
 716 2016-03-01  Nick Clifton  <nickc@redhat.com>
 717
 718         PR target/19747
 719         * rl78-dis.c (print_insn_rl78_common): Fix typo.
 720
 721 2016-02-24  Renlin Li  <renlin.li@arm.com>
 722
 723         * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
 724         (print_insn_coprocessor): Support fp16 instructions.
 725
 726 2016-02-24  Renlin Li  <renlin.li@arm.com>
 727
 728         * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
 729         vminnm, vrint(mpna).
 730
 731 2016-02-24  Renlin Li  <renlin.li@arm.com>
 732
 733         * arm-dis.c (print_insn_coprocessor): Check co-processor number for
 734         cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
 735
 736 2016-02-15  H.J. Lu  <hongjiu.lu@intel.com>
 737
 738         * i386-dis.c (print_insn): Parenthesize expression to prevent
 739         truncated addresses.
 740         (OP_J): Likewise.
 741
 742 2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
 743             Janek van Oirschot  <jvanoirs@synopsys.com>
 744
 745         * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
 746         variable.
 747
 748 2016-02-04  Nick Clifton  <nickc@redhat.com>
 749
 750         PR target/19561
 751         * msp430-dis.c (print_insn_msp430): Add a special case for
 752         decoding an RRC instruction with the ZC bit set in the extension
 753         word.
 754
 755 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 756
 757         * cgen-ibld.in (insert_normal): Rework calculation of shift.
 758         * epiphany-ibld.c: Regenerate.
 759         * fr30-ibld.c: Regenerate.
 760         * frv-ibld.c: Regenerate.
 761         * ip2k-ibld.c: Regenerate.
 762         * iq2000-ibld.c: Regenerate.
 763         * lm32-ibld.c: Regenerate.
 764         * m32c-ibld.c: Regenerate.
 765         * m32r-ibld.c: Regenerate.
 766         * mep-ibld.c: Regenerate.
 767         * mt-ibld.c: Regenerate.
 768         * or1k-ibld.c: Regenerate.
 769         * xc16x-ibld.c: Regenerate.
 770         * xstormy16-ibld.c: Regenerate.
 771
 772 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 773
 774         * epiphany-dis.c: Regenerated from latest cpu files.
 775
 776 2016-02-01  Michael McConville  <mmcco@mykolab.com>
 777
 778         * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
 779         test bit.
 780
 781 2016-01-25  Renlin Li  <renlin.li@arm.com>
 782
 783         * arm-dis.c (mapping_symbol_for_insn): New function.
 784         (find_ifthen_state): Call mapping_symbol_for_insn().
 785
 786 2016-01-20  Matthew Wahab  <matthew.wahab@arm.com>
 787
 788         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
 789         of MSR UAO immediate operand.
 790
 791 2016-01-18  Maciej W. Rozycki  <macro@imgtec.com>
 792
 793         * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
 794         instruction support.
 795
 796 2016-01-17  Alan Modra  <amodra@gmail.com>
 797
 798         * configure: Regenerate.
 799
 800 2016-01-14  Nick Clifton  <nickc@redhat.com>
 801
 802         * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
 803         instructions that can support stack pointer operations.
 804         * rl78-decode.c: Regenerate.
 805         * rl78-dis.c: Fix display of stack pointer in MOVW based
 806         instructions.
 807
 808 2016-01-14  Matthew Wahab  <matthew.wahab@arm.com>
 809
 810         * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
 811         testing for RAS support.  Add checks for erxfr_el1, erxctlr_el1,
 812         erxtatus_el1 and erxaddr_el1.
 813
 814 2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>
 815
 816         * arm-dis.c (arm_opcodes): Add "esb".
 817         (thumb_opcodes): Likewise.
 818
 819 2016-01-11  Peter Bergner <bergner@vnet.ibm.com>
 820
 821         * ppc-opc.c <xscmpnedp>: Delete.
 822         <xvcmpnedp>: Likewise.
 823         <xvcmpnedp.>: Likewise.
 824         <xvcmpnesp>: Likewise.
 825         <xvcmpnesp.>: Likewise.
 826
 827 2016-01-08  Andreas Schwab  <schwab@linux-m68k.org>
 828
 829         PR gas/13050
 830         * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
 831         addition to ISA_A.
 832
 833 2016-01-01  Alan Modra  <amodra@gmail.com>
 834
 835         Update year range in copyright notice of all files.
 836
 837 For older changes see ChangeLog-2015
 838 \f
 839 Copyright (C) 2016 Free Software Foundation, Inc.
 840
 841 Copying and distribution of this file, with or without modification,
 842 are permitted in any medium without royalty provided the copyright
 843 notice and this notice are preserved.
 844
 845 Local Variables:
 846 mode: change-log
 847 left-margin: 8
 848 fill-column: 74
 849 version-control: never
 850 End: