opcodes/ChangeLog

   1 2018-09-13  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
   4         movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
   5         movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
   6         vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
   7         vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
   8         Fold load and store templates where possible, adding D. Drop
   9         IgnoreSize where it was pointlessly present. Drop redundant
  10         *word.
  11         * i386-tbl.h: Re-generate.
  12
  13 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  14
  15         * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
  16         (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
  17         (intel_operand_size): Handle v_bndmk_mode.
  18         (OP_E_memory): Likewise. Produce (bad) when also riprel.
  19
  20 2018-09-08  John Darrington  <john@darrington.wattle.id.au>
  21
  22         * disassemble.c (ARCH_s12z): Define if ARCH_all.
  23
  24 2018-08-31  Kito Cheng  <kito@andestech.com>
  25
  26         * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
  27         compressed floating point instructions.
  28
  29 2018-08-30  Kito Cheng  <kito@andestech.com>
  30
  31         * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
  32         riscv_opcode.xlen_requirement.
  33         * riscv-opc.c (riscv_opcodes): Update for struct change.
  34
  35 2018-08-29  Martin Aberg  <maberg@gaisler.com>
  36
  37         * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
  38         psr (PWRPSR) instruction.
  39
  40 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
  41
  42         * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
  43
  44 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
  45
  46         * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
  47
  48 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
  49
  50         * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
  51         loongson3a as an alias of gs464 for compatibility.
  52         * mips-opc.c (mips_opcodes): Change Comments.
  53
  54 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
  55
  56         * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
  57         option.
  58         (print_mips_disassembler_options): Document -M loongson-ext.
  59         * mips-opc.c (LEXT2): New macro.
  60         (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
  61
  62 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
  63
  64          * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
  65          descriptors.
  66          (parse_mips_ase_option): Handle -M loongson-ext option.
  67          (print_mips_disassembler_options): Document -M loongson-ext.
  68          * mips-opc.c (IL3A): Delete.
  69          * mips-opc.c (LEXT): New macro.
  70          (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
  71          instructions.
  72
  73 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
  74
  75         * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
  76         descriptors.
  77         (parse_mips_ase_option): Handle -M loongson-cam option.
  78         (print_mips_disassembler_options): Document -M loongson-cam.
  79         * mips-opc.c (LCAM): New macro.
  80         (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
  81         instructions.
  82
  83 2018-08-21  Alan Modra  <amodra@gmail.com>
  84
  85         * ppc-dis.c (operand_value_powerpc): Init "invalid".
  86         (skip_optional_operands): Count optional operands, and update
  87         ppc_optional_operand_value call.
  88         * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
  89         (extract_vlensi): Likewise.
  90         (extract_fxm): Return default value for missing optional operand.
  91         (extract_ls, extract_raq, extract_tbr): Likewise.
  92         (insert_sxl, extract_sxl): New functions.
  93         (insert_esync, extract_esync): Remove Power9 handling and simplify.
  94         (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
  95         flag and extra entry.
  96         (powerpc_operands <SXL>): Likewise, and use insert_sxl and
  97         extract_sxl.
  98
  99 2018-08-20  Alan Modra  <amodra@gmail.com>
 100
 101         * sh-opc.h (MASK): Simplify.
 102
 103 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
 104
 105         * s12z-dis.c (bm_decode): Deal with cases where the mode is
 106         BM_RESERVED0 or BM_RESERVED1
 107         (bm_rel_decode, bm_n_bytes): Ditto.
 108
 109 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
 110
 111         * s12z.h: Delete.
 112
 113 2018-08-14  H.J. Lu  <hongjiu.lu@intel.com>
 114
 115         * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
 116         address with the addr32 prefix and without base nor index
 117         registers.
 118
 119 2018-08-11  H.J. Lu  <hongjiu.lu@intel.com>
 120
 121         * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
 122         CPU_I686_FLAGS.  Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
 123         CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
 124         (cpu_flags): Add CpuCMOV and CpuFXSR.
 125         * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
 126         fxrstor and fxrstor64.  Replace Cpu686 with CpuCMOV on cmovCC.
 127         * i386-init.h: Regenerated.
 128         * i386-tbl.h: Likewise.
 129
 130 2018-08-06  Claudiu Zissulescu  <claziss@synopsys.com>
 131
 132         * arc-regs.h: Update auxiliary registers.
 133
 134 2018-08-06  Jan Beulich  <jbeulich@suse.com>
 135
 136         * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
 137         (RegIP, RegIZ): Define.
 138         * i386-reg.tbl: Adjust comments.
 139         (rip): Use Qword instead of BaseIndex. Use RegIP.
 140         (eip): Use Dword instead of BaseIndex. Use RegIP.
 141         (riz): Add Qword. Use RegIZ.
 142         (eiz): Add Dword. Use RegIZ.
 143         * i386-tbl.h: Re-generate.
 144
 145 2018-08-03  Jan Beulich  <jbeulich@suse.com>
 146
 147         * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
 148         pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
 149         vpmovzxdq, vpmovzxwd): Remove NoRex64.
 150         * i386-tbl.h: Re-generate.
 151
 152 2018-08-03  Jan Beulich  <jbeulich@suse.com>
 153
 154         * i386-gen.c (operand_types): Remove Mem field.
 155         * i386-opc.h (union i386_operand_type): Remove mem field.
 156         * i386-init.h, i386-tbl.h: Re-generate.
 157
 158 2018-08-01  Alan Modra  <amodra@gmail.com>
 159
 160         * po/POTFILES.in: Regenerate.
 161
 162 2018-07-31  Nick Clifton  <nickc@redhat.com>
 163
 164         * po/sv.po: Updated Swedish translation.
 165
 166 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 167
 168         * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
 169         * i386-init.h, i386-tbl.h: Re-generate.
 170
 171 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 172
 173         * i386-opc.h (ZEROING_MASKING) Rename to ...
 174         (DYNAMIC_MASKING): ... this. Adjust comment.
 175         * i386-opc.tbl (MaskingMorZ): Define.
 176         (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
 177         vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
 178         vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
 179         vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
 180         vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
 181         vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
 182         vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
 183         vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
 184         vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
 185
 186 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 187
 188         * i386-opc.tbl: Use element rather than vector size for AVX512*
 189         scatter/gather insns.
 190         * i386-tbl.h: Re-generate.
 191
 192 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 193
 194         * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
 195         (cpu_flags): Drop CpuVREX.
 196         * i386-opc.h (CpuVREX): Delete.
 197         (union i386_cpu_flags): Remove cpuvrex.
 198         * i386-init.h, i386-tbl.h: Re-generate.
 199
 200 2018-07-30  Jim Wilson  <jimw@sifive.com>
 201
 202         * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
 203         fields.
 204         * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
 205
 206 2018-07-30  Andrew Jenner  <andrew@codesourcery.com>
 207
 208         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
 209         * Makefile.in: Regenerated.
 210         * configure.ac: Add C-SKY.
 211         * configure: Regenerated.
 212         * csky-dis.c: New file.
 213         * csky-opc.h: New file.
 214         * disassemble.c (ARCH_csky): Define.
 215         (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
 216         * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
 217
 218 2018-07-27  Alan Modra  <amodra@gmail.com>
 219
 220         * ppc-opc.c (insert_sprbat): Correct function parameter and
 221         return type.
 222         (extract_sprbat): Likewise, variable too.
 223
 224 2018-07-26  Alex Chadwick  <Alex.Chadwick@cl.cam.ac.uk>
 225             Alan Modra  <amodra@gmail.com>
 226
 227         * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
 228         (powerpc_init_dialect): Handle bfd_mach_ppc_750.
 229         * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
 230         support disjointed BAT.
 231         (powerpc_operands): Allow extra bit in SPRBAT_MASK.  Add SPRGQR.
 232         (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
 233         (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
 234
 235 2018-07-25  H.J. Lu  <hongjiu.lu@intel.com>
 236             Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 237
 238         * i386-gen.c (adjust_broadcast_modifier): New function.
 239         (process_i386_opcode_modifier): Add an argument for operands.
 240         Adjust the Broadcast value based on operands.
 241         (output_i386_opcode): Pass operand_types to
 242         process_i386_opcode_modifier.
 243         (process_i386_opcodes): Pass NULL as operands to
 244         process_i386_opcode_modifier.
 245         * i386-opc.h (BYTE_BROADCAST): New.
 246         (WORD_BROADCAST): Likewise.
 247         (DWORD_BROADCAST): Likewise.
 248         (QWORD_BROADCAST): Likewise.
 249         (i386_opcode_modifier): Expand broadcast to 3 bits.
 250         * i386-tbl.h: Regenerated.
 251
 252 2018-07-24  Alan Modra  <amodra@gmail.com>
 253
 254         PR 23430
 255         * or1k-desc.h: Regenerate.
 256
 257 2018-07-24  Jan Beulich  <jbeulich@suse.com>
 258
 259         * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
 260         vcvtusi2ss, and vcvtusi2sd.
 261         * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
 262         Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
 263         * i386-tbl.h: Re-generate.
 264
 265 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
 266
 267         * arc-opc.c (extract_w6): Fix extending the sign.
 268
 269 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
 270
 271         * arc-tbl.h (vewt): Allow it for ARC EM family.
 272
 273 2018-07-23  Alan Modra  <amodra@gmail.com>
 274
 275         PR 23419
 276         * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
 277         opcode variants for mtspr/mfspr encodings.
 278
 279 2018-07-20  Chenghua Xu  <paul.hua.gm@gmail.com>
 280             Maciej W. Rozycki  <macro@mips.com>
 281
 282         * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
 283         loongson3a descriptors.
 284         (parse_mips_ase_option): Handle -M loongson-mmi option.
 285         (print_mips_disassembler_options): Document -M loongson-mmi.
 286         * mips-opc.c (LMMI): New macro.
 287         (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
 288         instructions.
 289
 290 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 291
 292         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 293         vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
 294         IgnoreSize and [XYZ]MMword where applicable.
 295         * i386-tbl.h: Re-generate.
 296
 297 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 298
 299         * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
 300         (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
 301         (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
 302         (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
 303         * i386-tbl.h: Re-generate.
 304
 305 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 306
 307         * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
 308         AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
 309         VPCLMULQDQ templates into their respective AVX512VL counterparts
 310         where possible, using Disp8ShiftVL and CheckRegSize instead of
 311         Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
 312         * i386-tbl.h: Re-generate.
 313
 314 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 315
 316         * i386-opc.tbl: Fold AVX512DQ templates into their respective
 317         AVX512VL counterparts where possible, using Disp8ShiftVL and
 318         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 319         IgnoreSize) as appropriate.
 320         * i386-tbl.h: Re-generate.
 321
 322 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 323
 324         * i386-opc.tbl: Fold AVX512BW templates into their respective
 325         AVX512VL counterparts where possible, using Disp8ShiftVL and
 326         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 327         IgnoreSize) as appropriate.
 328         * i386-tbl.h: Re-generate.
 329
 330 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 331
 332         * i386-opc.tbl: Fold AVX512CD templates into their respective
 333         AVX512VL counterparts where possible, using Disp8ShiftVL and
 334         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 335         IgnoreSize) as appropriate.
 336         * i386-tbl.h: Re-generate.
 337
 338 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 339
 340         * i386-opc.h (DISP8_SHIFT_VL): New.
 341         * i386-opc.tbl (Disp8ShiftVL):  Define.
 342         (various): Fold AVX512VL templates into their respective
 343         AVX512F counterparts where possible, using Disp8ShiftVL and
 344         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 345         IgnoreSize) as appropriate.
 346         * i386-tbl.h: Re-generate.
 347
 348 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 349
 350         * Makefile.am: Change dependencies and rule for
 351         $(srcdir)/i386-init.h.
 352         * Makefile.in: Re-generate.
 353         * i386-gen.c (process_i386_opcodes): New local variable
 354         "marker". Drop opening of input file. Recognize marker and line
 355         number directives.
 356         * i386-opc.tbl (OPCODE_I386_H): Define.
 357         (i386-opc.h): Include it.
 358         (None): Undefine.
 359
 360 2018-07-18  H.J. Lu  <hongjiu.lu@intel.com>
 361
 362         PR gas/23418
 363         * i386-opc.h (Byte): Update comments.
 364         (Word): Likewise.
 365         (Dword): Likewise.
 366         (Fword): Likewise.
 367         (Qword): Likewise.
 368         (Tbyte): Likewise.
 369         (Xmmword): Likewise.
 370         (Ymmword): Likewise.
 371         (Zmmword): Likewise.
 372         * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
 373         vcvttps2uqq.
 374         * i386-tbl.h: Regenerated.
 375
 376 2018-07-12  Sudakshina Das  <sudi.das@arm.com>
 377
 378         * aarch64-tbl.h (aarch64_opcode_table): Add entry for
 379         ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
 380         * aarch64-asm-2.c: Regenerate.
 381         * aarch64-dis-2.c: Regenerate.
 382         * aarch64-opc-2.c: Regenerate.
 383
 384 2018-07-12  Tamar Christina  <tamar.christina@arm.com>
 385
 386         PR binutils/23192
 387         * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
 388         mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
 389         umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
 390         sqdmulh, sqrdmulh): Use Em16.
 391
 392 2018-07-11  Sudakshina Das  <sudi.das@arm.com>
 393
 394         * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
 395         csdb together with them.
 396         (thumb32_opcodes): Likewise.
 397
 398 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 399
 400         * i386-opc.tbl (monitor, monitorx): Add 64-bit template
 401         requiring 32-bit registers as operands 2 and 3. Improve
 402         comments.
 403         (mwait, mwaitx): Fold templates. Improve comments.
 404         OPERAND_TYPE_INOUTPORTREG.
 405         * i386-tbl.h: Re-generate.
 406
 407 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 408
 409         * i386-gen.c (operand_type_init): Remove
 410         OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
 411         OPERAND_TYPE_INOUTPORTREG.
 412         * i386-init.h: Re-generate.
 413
 414 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 415
 416         * i386-opc.tbl (wrssd, wrussd): Add Dword.
 417         (wrssq, wrussq): Add Qword.
 418         * i386-tbl.h: Re-generate.
 419
 420 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 421
 422         * i386-opc.h: Rename OTMax to OTNum.
 423         (OTNumOfUints): Adjust calculation.
 424         (OTUnused): Directly alias to OTNum.
 425
 426 2018-07-09  Maciej W. Rozycki  <macro@mips.com>
 427
 428         * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
 429         `reg_xys'.
 430         (lea_reg_xys): Likewise.
 431         (print_insn_loop_primitive): Rename `reg' local variable to
 432         `reg_dxy'.
 433
 434 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
 435
 436         PR binutils/23242
 437         * aarch64-tbl.h (ldarh): Fix disassembly mask.
 438
 439 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
 440
 441         PR binutils/23369
 442         * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
 443         vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
 444
 445 2018-07-02  Maciej W. Rozycki  <macro@mips.com>
 446
 447         PR tdep/8282
 448         * mips-dis.c (mips_option_arg_t): New enumeration.
 449         (mips_options): New variable.
 450         (disassembler_options_mips): New function.
 451         (print_mips_disassembler_options): Reimplement in terms of
 452         `disassembler_options_mips'.
 453         * arm-dis.c (disassembler_options_arm): Adapt to using the
 454         `disasm_options_and_args_t' structure.
 455         * ppc-dis.c (disassembler_options_powerpc): Likewise.
 456         * s390-dis.c (disassembler_options_s390): Likewise.
 457
 458 2018-07-02  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 459
 460         * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
 461         expected result.
 462         * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
 463         * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
 464         * testsuite/ld-arm/tls-longplt.d: Likewise.
 465
 466 2018-06-29  Tamar Christina  <tamar.christina@arm.com>
 467
 468         PR binutils/23192
 469         * aarch64-asm-2.c: Regenerate.
 470         * aarch64-dis-2.c: Likewise.
 471         * aarch64-opc-2.c: Likewise.
 472         * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
 473         * aarch64-opc.c (operand_general_constraint_met_p,
 474         aarch64_print_operand): Likewise.
 475         * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
 476         smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
 477         fmlal2, fmlsl2.
 478         (AARCH64_OPERANDS): Add Em2.
 479
 480 2018-06-26  Nick Clifton  <nickc@redhat.com>
 481
 482         * po/uk.po: Updated Ukranian translation.
 483         * po/de.po: Updated German translation.
 484         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 485
 486 2018-06-26  Nick Clifton  <nickc@redhat.com>
 487
 488         * nfp-dis.c: Fix spelling mistake.
 489
 490 2018-06-24  Nick Clifton  <nickc@redhat.com>
 491
 492         * configure: Regenerate.
 493         * po/opcodes.pot: Regenerate.
 494
 495 2018-06-24  Nick Clifton  <nickc@redhat.com>
 496
 497         2.31 branch created.
 498
 499 2018-06-19  Tamar Christina  <tamar.christina@arm.com>
 500
 501         * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
 502         * aarch64-asm-2.c: Regenerate.
 503         * aarch64-dis-2.c: Likewise.
 504
 505 2018-06-21  Maciej W. Rozycki  <macro@mips.com>
 506
 507         * mips-dis.c (print_mips_disassembler_options): Fix a typo in
 508         `-M ginv' option description.
 509
 510 2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
 511
 512         PR gas/23305
 513         * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
 514         la and lla.
 515
 516 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
 517
 518         * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
 519         * configure.ac: Remove AC_PREREQ.
 520         * Makefile.in: Re-generate.
 521         * aclocal.m4: Re-generate.
 522         * configure: Re-generate.
 523
 524 2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 525
 526         * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
 527         mips64r6 descriptors.
 528         (parse_mips_ase_option): Handle -Mginv option.
 529         (print_mips_disassembler_options): Document -Mginv.
 530         * mips-opc.c (decode_mips_operand) <+\>: New operand format.
 531         (GINV): New macro.
 532         (mips_opcodes): Define ginvi and ginvt.
 533
 534 2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
 535             Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 536
 537         * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
 538         * mips-opc.c (CRC, CRC64): New macros.
 539         (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
 540         crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
 541         crc32cd for CRC64.
 542
 543 2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
 544
 545         PR 20319
 546         * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 547         (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 548
 549 2018-06-06  Alan Modra  <amodra@gmail.com>
 550
 551         * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
 552         setjmp.  Move init for some other vars later too.
 553
 554 2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
 555
 556         * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
 557         (dis_private): Add new fields for property section tracking.
 558         (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
 559         (xtensa_instruction_fits): New functions.
 560         (fetch_data): Bump minimal fetch size to 4.
 561         (print_insn_xtensa): Make struct dis_private static.
 562         Load and prepare property table on section change.
 563         Don't disassemble literals. Don't disassemble instructions that
 564         cross property table boundaries.
 565
 566 2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
 567
 568         * configure: Regenerated.
 569
 570 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 571
 572         * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
 573         * i386-tbl.h: Re-generate.
 574
 575 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 576
 577         * i386-opc.tbl (sldt, str): Add NoRex64.
 578         * i386-tbl.h: Re-generate.
 579
 580 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 581
 582         * i386-opc.tbl (invpcid): Add Oword.
 583         * i386-tbl.h: Re-generate.
 584
 585 2018-06-01  Alan Modra  <amodra@gmail.com>
 586
 587         * sysdep.h (_bfd_error_handler): Don't declare.
 588         * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
 589         * rl78-decode.opc: Likewise.
 590         * msp430-decode.c: Regenerate.
 591         * rl78-decode.c: Regenerate.
 592
 593 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
 594
 595         * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
 596         * i386-init.h : Regenerated.
 597
 598 2018-05-25  Alan Modra  <amodra@gmail.com>
 599
 600         * Makefile.in: Regenerate.
 601         * po/POTFILES.in: Regenerate.
 602
 603 2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
 604
 605         * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
 606         insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
 607         (insert_bab, extract_bab, insert_btab, extract_btab,
 608         insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
 609         (BAT, BBA VBA RBS XB6S): Delete macros.
 610         (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
 611         (BB, BD, RBX, XC6): Update for new macros.
 612         (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
 613         crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
 614         e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
 615         * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
 616
 617 2018-05-18  John Darrington  <john@darrington.wattle.id.au>
 618
 619         * Makefile.am: Add support for s12z architecture.
 620         * configure.ac: Likewise.
 621         * disassemble.c: Likewise.
 622         * disassemble.h: Likewise.
 623         * Makefile.in: Regenerate.
 624         * configure: Regenerate.
 625         * s12z-dis.c: New file.
 626         * s12z.h: New file.
 627
 628 2018-05-18  Alan Modra  <amodra@gmail.com>
 629
 630         * nfp-dis.c: Don't #include libbfd.h.
 631         (init_nfp3200_priv): Use bfd_get_section_contents.
 632         (nit_nfp6000_mecsr_sec): Likewise.
 633
 634 2018-05-17  Nick Clifton  <nickc@redhat.com>
 635
 636         * po/zh_CN.po: Updated simplified Chinese translation.
 637
 638 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
 639
 640         PR binutils/23109
 641         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
 642         * aarch64-dis-2.c: Regenerate.
 643
 644 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 645
 646         PR binutils/21446
 647         * aarch64-asm.c (opintl.h): Include.
 648         (aarch64_ins_sysreg): Enforce read/write constraints.
 649         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
 650         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
 651         (F_REG_READ, F_REG_WRITE): New.
 652         * aarch64-opc.c (aarch64_print_operand): Generate notes for
 653         AARCH64_OPND_SYSREG.
 654         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
 655         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
 656         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
 657         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
 658         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
 659         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
 660         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
 661         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
 662         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
 663         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
 664         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
 665         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
 666         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
 667         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
 668         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
 669         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
 670         msr (F_SYS_WRITE), mrs (F_SYS_READ).
 671
 672 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 673
 674         PR binutils/21446
 675         * aarch64-dis.c (no_notes: New.
 676         (parse_aarch64_dis_option): Support notes.
 677         (aarch64_decode_insn, print_operands): Likewise.
 678         (print_aarch64_disassembler_options): Document notes.
 679         * aarch64-opc.c (aarch64_print_operand): Support notes.
 680
 681 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 682
 683         PR binutils/21446
 684         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
 685         and take error struct.
 686         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
 687         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
 688         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
 689         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
 690         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
 691         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
 692         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
 693         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
 694         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
 695         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
 696         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
 697         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
 698         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
 699         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
 700         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
 701         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
 702         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
 703         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 704         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
 705         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
 706         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
 707         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
 708         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
 709         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
 710         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
 711         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
 712         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
 713         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
 714         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
 715         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
 716         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
 717         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
 718         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
 719         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
 720         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
 721         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
 722         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
 723         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
 724         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
 725         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
 726         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
 727         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
 728         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
 729         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 730         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
 731         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
 732         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
 733         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
 734         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
 735         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
 736         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
 737         (determine_disassembling_preference, aarch64_decode_insn,
 738         print_insn_aarch64_word, print_insn_data): Take errors struct.
 739         (print_insn_aarch64): Use errors.
 740         * aarch64-asm-2.c: Regenerate.
 741         * aarch64-dis-2.c: Regenerate.
 742         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
 743         boolean in aarch64_insert_operan.
 744         (print_operand_extractor): Likewise.
 745         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
 746
 747 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
 748
 749         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
 750
 751 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 752
 753         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
 754
 755 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
 756
 757         * cr16-opc.c (cr16_instruction): Comment typo fix.
 758         * hppa-dis.c (print_insn_hppa): Likewise.
 759
 760 2018-05-08  Jim Wilson  <jimw@sifive.com>
 761
 762         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
 763         (match_c_slli64, match_srxi_as_c_srxi): New.
 764         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
 765         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
 766         <c.slli, c.srli, c.srai>: Use match_s_slli.
 767         <c.slli64, c.srli64, c.srai64>: New.
 768
 769 2018-05-08  Alan Modra  <amodra@gmail.com>
 770
 771         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
 772         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
 773         partition opcode space for index lookup.
 774
 775 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 776
 777         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
 778         <insn_length>: ...with this.  Update usage.
 779         Remove duplicate call to *info->memory_error_func.
 780
 781 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 782             H.J. Lu  <hongjiu.lu@intel.com>
 783
 784         * i386-dis.c (Gva): New.
 785         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
 786         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
 787         (prefix_table): New instructions (see prefix above).
 788         (mod_table): New instructions (see prefix above).
 789         (OP_G): Handle va_mode.
 790         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
 791         CPU_MOVDIR64B_FLAGS.
 792         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
 793         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
 794         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
 795         * i386-opc.tbl: Add movidir{i,64b}.
 796         * i386-init.h: Regenerated.
 797         * i386-tbl.h: Likewise.
 798
 799 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
 800
 801         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
 802         AddrPrefixOpReg.
 803         * i386-opc.h (AddrPrefixOp0): Renamed to ...
 804         (AddrPrefixOpReg): This.
 805         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
 806         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
 807
 808 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 809
 810         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
 811         (vle_num_opcodes): Likewise.
 812         (spe2_num_opcodes): Likewise.
 813         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
 814         initialization loop.
 815         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
 816         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
 817         only once.
 818
 819 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
 820
 821         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
 822
 823 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
 824
 825         Makefile.am: Added nfp-dis.c.
 826         configure.ac: Added bfd_nfp_arch.
 827         disassemble.h: Added print_insn_nfp prototype.
 828         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
 829         nfp-dis.c: New, for NFP support.
 830         po/POTFILES.in: Added nfp-dis.c to the list.
 831         Makefile.in: Regenerate.
 832         configure: Regenerate.
 833
 834 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 835
 836         * i386-opc.tbl: Fold various non-memory operand AVX512VL
 837         templates into their base ones.
 838         * i386-tlb.h: Re-generate.
 839
 840 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 841
 842         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
 843         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
 844         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
 845         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
 846         * i386-init.h: Re-generate.
 847
 848 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 849
 850         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
 851         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
 852         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
 853         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
 854         comment.
 855         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 856         and CpuRegMask.
 857         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 858         CpuRegMask: Delete.
 859         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
 860         cpuregzmm, and cpuregmask.
 861         * i386-init.h: Re-generate.
 862         * i386-tbl.h: Re-generate.
 863
 864 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 865
 866         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
 867         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
 868         * i386-init.h: Re-generate.
 869
 870 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 871
 872         * i386-gen.c (VexImmExt): Delete.
 873         * i386-opc.h (VexImmExt, veximmext): Delete.
 874         * i386-opc.tbl: Drop all VexImmExt uses.
 875         * i386-tlb.h: Re-generate.
 876
 877 2018-04-25  Jan Beulich  <jbeulich@suse.com>
 878
 879         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
 880         register-only forms.
 881         * i386-tlb.h: Re-generate.
 882
 883 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
 884
 885         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
 886
 887 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 888
 889         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
 890         PREFIX_0F1C.
 891         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
 892         (cpu_flags): Add CpuCLDEMOTE.
 893         * i386-init.h: Regenerate.
 894         * i386-opc.h (enum): Add CpuCLDEMOTE,
 895         (i386_cpu_flags): Add cpucldemote.
 896         * i386-opc.tbl: Add cldemote.
 897         * i386-tbl.h: Regenerate.
 898
 899 2018-04-16  Alan Modra  <amodra@gmail.com>
 900
 901         * Makefile.am: Remove sh5 and sh64 support.
 902         * configure.ac: Likewise.
 903         * disassemble.c: Likewise.
 904         * disassemble.h: Likewise.
 905         * sh-dis.c: Likewise.
 906         * sh64-dis.c: Delete.
 907         * sh64-opc.c: Delete.
 908         * sh64-opc.h: Delete.
 909         * Makefile.in: Regenerate.
 910         * configure: Regenerate.
 911         * po/POTFILES.in: Regenerate.
 912
 913 2018-04-16  Alan Modra  <amodra@gmail.com>
 914
 915         * Makefile.am: Remove w65 support.
 916         * configure.ac: Likewise.
 917         * disassemble.c: Likewise.
 918         * disassemble.h: Likewise.
 919         * w65-dis.c: Delete.
 920         * w65-opc.h: Delete.
 921         * Makefile.in: Regenerate.
 922         * configure: Regenerate.
 923         * po/POTFILES.in: Regenerate.
 924
 925 2018-04-16  Alan Modra  <amodra@gmail.com>
 926
 927         * configure.ac: Remove we32k support.
 928         * configure: Regenerate.
 929
 930 2018-04-16  Alan Modra  <amodra@gmail.com>
 931
 932         * Makefile.am: Remove m88k support.
 933         * configure.ac: Likewise.
 934         * disassemble.c: Likewise.
 935         * disassemble.h: Likewise.
 936         * m88k-dis.c: Delete.
 937         * Makefile.in: Regenerate.
 938         * configure: Regenerate.
 939         * po/POTFILES.in: Regenerate.
 940
 941 2018-04-16  Alan Modra  <amodra@gmail.com>
 942
 943         * Makefile.am: Remove i370 support.
 944         * configure.ac: Likewise.
 945         * disassemble.c: Likewise.
 946         * disassemble.h: Likewise.
 947         * i370-dis.c: Delete.
 948         * i370-opc.c: Delete.
 949         * Makefile.in: Regenerate.
 950         * configure: Regenerate.
 951         * po/POTFILES.in: Regenerate.
 952
 953 2018-04-16  Alan Modra  <amodra@gmail.com>
 954
 955         * Makefile.am: Remove h8500 support.
 956         * configure.ac: Likewise.
 957         * disassemble.c: Likewise.
 958         * disassemble.h: Likewise.
 959         * h8500-dis.c: Delete.
 960         * h8500-opc.h: Delete.
 961         * Makefile.in: Regenerate.
 962         * configure: Regenerate.
 963         * po/POTFILES.in: Regenerate.
 964
 965 2018-04-16  Alan Modra  <amodra@gmail.com>
 966
 967         * configure.ac: Remove tahoe support.
 968         * configure: Regenerate.
 969
 970 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 971
 972         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
 973         umwait.
 974         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
 975         64-bit mode.
 976         * i386-tbl.h: Regenerated.
 977
 978 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 979
 980         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
 981         PREFIX_MOD_1_0FAE_REG_6.
 982         (va_mode): New.
 983         (OP_E_register): Use va_mode.
 984         * i386-dis-evex.h (prefix_table):
 985         New instructions (see prefixes above).
 986         * i386-gen.c (cpu_flag_init): Add WAITPKG.
 987         (cpu_flags): Likewise.
 988         * i386-opc.h (enum): Likewise.
 989         (i386_cpu_flags): Likewise.
 990         * i386-opc.tbl: Add umonitor, umwait, tpause.
 991         * i386-init.h: Regenerate.
 992         * i386-tbl.h: Likewise.
 993
 994 2018-04-11  Alan Modra  <amodra@gmail.com>
 995
 996         * opcodes/i860-dis.c: Delete.
 997         * opcodes/i960-dis.c: Delete.
 998         * Makefile.am: Remove i860 and i960 support.
 999         * configure.ac: Likewise.
1000         * disassemble.c: Likewise.
1001         * disassemble.h: Likewise.
1002         * Makefile.in: Regenerate.
1003         * configure: Regenerate.
1004         * po/POTFILES.in: Regenerate.
1005
1006 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
1007
1008         PR binutils/23025
1009         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1010         to 0.
1011         (print_insn): Clear vex instead of vex.evex.
1012
1013 2018-04-04  Nick Clifton  <nickc@redhat.com>
1014
1015         * po/es.po: Updated Spanish translation.
1016
1017 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1018
1019         * i386-gen.c (opcode_modifiers): Delete VecESize.
1020         * i386-opc.h (VecESize): Delete.
1021         (struct i386_opcode_modifier): Delete vecesize.
1022         * i386-opc.tbl: Drop VecESize.
1023         * i386-tlb.h: Re-generate.
1024
1025 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1026
1027         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1028         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1029         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1030         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1031         * i386-tlb.h: Re-generate.
1032
1033 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1034
1035         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1036         Fold AVX512 forms
1037         * i386-tlb.h: Re-generate.
1038
1039 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1040
1041         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1042         (vex_len_table): Drop Y for vcvt*2si.
1043         (putop): Replace plain 'Y' handling by abort().
1044
1045 2018-03-28  Nick Clifton  <nickc@redhat.com>
1046
1047         PR 22988
1048         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1049         instructions with only a base address register.
1050         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1051         handle AARHC64_OPND_SVE_ADDR_R.
1052         (aarch64_print_operand): Likewise.
1053         * aarch64-asm-2.c: Regenerate.
1054         * aarch64_dis-2.c: Regenerate.
1055         * aarch64-opc-2.c: Regenerate.
1056
1057 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1058
1059         * i386-opc.tbl: Drop VecESize from register only insn forms and
1060         memory forms not allowing broadcast.
1061         * i386-tlb.h: Re-generate.
1062
1063 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1064
1065         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1066         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1067         sha256*): Drop Disp<N>.
1068
1069 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1070
1071         * i386-dis.c (EbndS, bnd_swap_mode): New.
1072         (prefix_table): Use EbndS.
1073         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1074         * i386-opc.tbl (bndmov): Move misplaced Load.
1075         * i386-tlb.h: Re-generate.
1076
1077 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1078
1079         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1080         templates allowing memory operands and folded ones for register
1081         only flavors.
1082         * i386-tlb.h: Re-generate.
1083
1084 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1085
1086         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1087         256-bit templates. Drop redundant leftover Disp<N>.
1088         * i386-tlb.h: Re-generate.
1089
1090 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
1091
1092         * riscv-opc.c (riscv_insn_types): New.
1093
1094 2018-03-13  Nick Clifton  <nickc@redhat.com>
1095
1096         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1097
1098 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
1099
1100         * i386-opc.tbl: Add Optimize to clr.
1101         * i386-tbl.h: Regenerated.
1102
1103 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
1104
1105         * i386-gen.c (opcode_modifiers): Remove OldGcc.
1106         * i386-opc.h (OldGcc): Removed.
1107         (i386_opcode_modifier): Remove oldgcc.
1108         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1109         instructions for old (<= 2.8.1) versions of gcc.
1110         * i386-tbl.h: Regenerated.
1111
1112 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1113
1114         * i386-opc.h (EVEXDYN): New.
1115         * i386-opc.tbl: Fold various AVX512VL templates.
1116         * i386-tlb.h: Re-generate.
1117
1118 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1119
1120         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1121         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1122         vpexpandd, vpexpandq): Fold AFX512VF templates.
1123         * i386-tlb.h: Re-generate.
1124
1125 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1126
1127         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1128         Fold 128- and 256-bit VEX-encoded templates.
1129         * i386-tlb.h: Re-generate.
1130
1131 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1132
1133         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1134         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1135         vpexpandd, vpexpandq): Fold AVX512F templates.
1136         * i386-tlb.h: Re-generate.
1137
1138 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1139
1140         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1141         64-bit templates. Drop Disp<N>.
1142         * i386-tlb.h: Re-generate.
1143
1144 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1145
1146         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1147         and 256-bit templates.
1148         * i386-tlb.h: Re-generate.
1149
1150 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1151
1152         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1153         * i386-tlb.h: Re-generate.
1154
1155 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1156
1157         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1158         Drop NoAVX.
1159         * i386-tlb.h: Re-generate.
1160
1161 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1162
1163         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1164         * i386-tlb.h: Re-generate.
1165
1166 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1167
1168         * i386-gen.c (opcode_modifiers): Delete FloatD.
1169         * i386-opc.h (FloatD): Delete.
1170         (struct i386_opcode_modifier): Delete floatd.
1171         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1172         FloatD by D.
1173         * i386-tlb.h: Re-generate.
1174
1175 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1176
1177         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1178
1179 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1180
1181         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1182         * i386-tlb.h: Re-generate.
1183
1184 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1185
1186         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1187         forms.
1188         * i386-tlb.h: Re-generate.
1189
1190 2018-03-07  Alan Modra  <amodra@gmail.com>
1191
1192         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1193         bfd_arch_rs6000.
1194         * disassemble.h (print_insn_rs6000): Delete.
1195         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1196         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1197         (print_insn_rs6000): Delete.
1198
1199 2018-03-03  Alan Modra  <amodra@gmail.com>
1200
1201         * sysdep.h (opcodes_error_handler): Define.
1202         (_bfd_error_handler): Declare.
1203         * Makefile.am: Remove stray #.
1204         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
1205         EDIT" comment.
1206         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1207         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1208         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1209         opcodes_error_handler to print errors.  Standardize error messages.
1210         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1211         and include opintl.h.
1212         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1213         * i386-gen.c: Standardize error messages.
1214         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1215         * Makefile.in: Regenerate.
1216         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1217         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1218         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1219         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1220         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1221         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1222         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1223         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1224         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1225         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1226         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1227         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1228         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1229
1230 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
1231
1232         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1233         vpsub[bwdq] instructions.
1234         * i386-tbl.h: Regenerated.
1235
1236 2018-03-01  Alan Modra  <amodra@gmail.com>
1237
1238         * configure.ac (ALL_LINGUAS): Sort.
1239         * configure: Regenerate.
1240
1241 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1242
1243         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1244         macro by assignements.
1245
1246 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
1247
1248         PR gas/22871
1249         * i386-gen.c (opcode_modifiers): Add Optimize.
1250         * i386-opc.h (Optimize): New enum.
1251         (i386_opcode_modifier): Add optimize.
1252         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1253         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1254         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1255         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1256         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1257         vpxord and vpxorq.
1258         * i386-tbl.h: Regenerated.
1259
1260 2018-02-26  Alan Modra  <amodra@gmail.com>
1261
1262         * crx-dis.c (getregliststring): Allocate a large enough buffer
1263         to silence false positive gcc8 warning.
1264
1265 2018-02-22  Shea Levy <shea@shealevy.com>
1266
1267         * disassemble.c (ARCH_riscv): Define if ARCH_all.
1268
1269 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
1270
1271         * i386-opc.tbl: Add {rex},
1272         * i386-tbl.h: Regenerated.
1273
1274 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
1275
1276         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1277         (mips16_opcodes): Replace `M' with `m' for "restore".
1278
1279 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1280
1281         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1282
1283 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
1284
1285         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1286         variable to `function_index'.
1287
1288 2018-02-13  Nick Clifton  <nickc@redhat.com>
1289
1290         PR 22823
1291         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1292         about truncation of printing.
1293
1294 2018-02-12  Henry Wong <henry@stuffedcow.net>
1295
1296         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1297
1298 2018-02-05  Nick Clifton  <nickc@redhat.com>
1299
1300         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1301
1302 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1303
1304         * i386-dis.c (enum): Add pconfig.
1305         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1306         (cpu_flags): Add CpuPCONFIG.
1307         * i386-opc.h (enum): Add CpuPCONFIG.
1308         (i386_cpu_flags): Add cpupconfig.
1309         * i386-opc.tbl: Add PCONFIG instruction.
1310         * i386-init.h: Regenerate.
1311         * i386-tbl.h: Likewise.
1312
1313 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1314
1315         * i386-dis.c (enum): Add PREFIX_0F09.
1316         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1317         (cpu_flags): Add CpuWBNOINVD.
1318         * i386-opc.h (enum): Add CpuWBNOINVD.
1319         (i386_cpu_flags): Add cpuwbnoinvd.
1320         * i386-opc.tbl: Add WBNOINVD instruction.
1321         * i386-init.h: Regenerate.
1322         * i386-tbl.h: Likewise.
1323
1324 2018-01-17  Jim Wilson  <jimw@sifive.com>
1325
1326         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1327
1328 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1329
1330         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1331         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1332         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1333         (cpu_flags): Add CpuIBT, CpuSHSTK.
1334         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1335         (i386_cpu_flags): Add cpuibt, cpushstk.
1336         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1337         * i386-init.h: Regenerate.
1338         * i386-tbl.h: Likewise.
1339
1340 2018-01-16  Nick Clifton  <nickc@redhat.com>
1341
1342         * po/pt_BR.po: Updated Brazilian Portugese translation.
1343         * po/de.po: Updated German translation.
1344
1345 2018-01-15  Jim Wilson  <jimw@sifive.com>
1346
1347         * riscv-opc.c (match_c_nop): New.
1348         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1349
1350 2018-01-15  Nick Clifton  <nickc@redhat.com>
1351
1352         * po/uk.po: Updated Ukranian translation.
1353
1354 2018-01-13  Nick Clifton  <nickc@redhat.com>
1355
1356         * po/opcodes.pot: Regenerated.
1357
1358 2018-01-13  Nick Clifton  <nickc@redhat.com>
1359
1360         * configure: Regenerate.
1361
1362 2018-01-13  Nick Clifton  <nickc@redhat.com>
1363
1364         2.30 branch created.
1365
1366 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1367
1368         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1369         * i386-tbl.h: Regenerate.
1370
1371 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1372
1373         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1374         * i386-tbl.h: Re-generate.
1375
1376 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1377
1378         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1379         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1380         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1381         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1382         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1383         Disp8MemShift of AVX512VL forms.
1384         * i386-tbl.h: Re-generate.
1385
1386 2018-01-09  Jim Wilson  <jimw@sifive.com>
1387
1388         * riscv-dis.c (maybe_print_address): If base_reg is zero,
1389         then the hi_addr value is zero.
1390
1391 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1392
1393         * arm-dis.c (arm_opcodes): Add csdb.
1394         (thumb32_opcodes): Add csdb.
1395
1396 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1397
1398         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1399         * aarch64-asm-2.c: Regenerate.
1400         * aarch64-dis-2.c: Regenerate.
1401         * aarch64-opc-2.c: Regenerate.
1402
1403 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
1404
1405         PR gas/22681
1406         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1407         Remove AVX512 vmovd with 64-bit operands.
1408         * i386-tbl.h: Regenerated.
1409
1410 2018-01-05  Jim Wilson  <jimw@sifive.com>
1411
1412         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1413         jalr.
1414
1415 2018-01-03  Alan Modra  <amodra@gmail.com>
1416
1417         Update year range in copyright notice of all files.
1418
1419 2018-01-02  Jan Beulich  <jbeulich@suse.com>
1420
1421         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1422         and OPERAND_TYPE_REGZMM entries.
1423
1424 For older changes see ChangeLog-2017
1425 \f
1426 Copyright (C) 2018 Free Software Foundation, Inc.
1427
1428 Copying and distribution of this file, with or without modification,
1429 are permitted in any medium without royalty provided the copyright
1430 notice and this notice are preserved.
1431
1432 Local Variables:
1433 mode: change-log
1434 left-margin: 8
1435 fill-column: 74
1436 version-control: never
1437 End: