1 2017-12-18 Jan Beulich <jbeulich@suse.com>
3 * i386-gen.c (operand_type_shorthands): New.
4 (opcode_modifiers): Replace Reg<N> with just Reg.
5 (set_bitfield_from_cpu_flag_init): Rename to
6 set_bitfield_from_shorthand. Drop value parameter. Process
7 operand_type_shorthands.
8 (set_bitfield): Adjust call accordingly.
9 * i386-opc.h (enum of operand types): Replace Reg<N> with just
11 (union i386_operand_type): Replace reg<N> with just reg.
12 * i386-opc.tbl (extractps, pextrb, pextrw, pinsrb, pinsrw,
13 vextractps, vpextrb, vpextrw, vpinsrb, vpinsrw): Split into
14 separate register and memory forms.
15 * i386-reg.tbl (al): Drop Byte.
19 * i386-init.h, i386-tbl.h: Re-generate.
21 2017-12-15 Dimitar Dimitrov <dimitar@dinux.eu>
23 * disassemble.c (disassemble_init_for_target): Don't put PRU
24 between powerpc and rs6000 cases.
26 2017-12-15 Jan Beulich <jbeulich@suse.com>
28 * i386-opc.tbl (adc, add, and, cmp, cmps, in, ins, lods, mov,
29 movabs, movq, movs, or, out, outs, ptwrite, rcl, rcr, rol, ror,
30 sal, sar, sbb, scas, scmp, shl, shr, slod, smov, ssca, ssto,
31 stos, sub, test, xor): Drop CheckRegSize from variants not
32 allowing for two (or more) register operands.
33 * i386-tbl.h: Re-generate.
35 2017-12-13 Jim Wilson <jimw@sifive.com>
38 * riscv-opc.c (riscv_opcodes) <fsrmi, fsflagsi>: New.
40 2017-12-13 Dimitar Dimitrov <dimitar@dinux.eu>
42 * disassemble.c: Enable disassembler_needs_relocs for PRU.
44 2017-12-11 Petr Pavlu <petr.pavlu@arm.com>
45 Renlin Li <renlin.li@arm.com>
47 * aarch64-dis.c (print_insn_aarch64): Move symbol section check ...
48 (get_sym_code_type): Here.
50 2017-12-03 Alan Modra <amodra@gmail.com>
52 * ppc-opc.c (extract_li20): Rewrite.
54 2017-12-01 Peter Bergner <bergner@vnet.ibm.com>
56 * opcodes/ppc-dis.c (disassemble_init_powerpc): Fix white space.
57 (operand_value_powerpc): Update return and argument type.
58 <value, top>: Update type.
59 (skip_optional_operands): Update argument type.
60 (lookup_powerpc): Likewise.
61 (lookup_vle): Likewise.
62 <table_opcd, table_mask, insn2>: Update type.
63 (lookup_spe2): Update argument type.
64 <table_opcd, table_mask, insn2>: Update type.
65 (print_insn_powerpc) <insn, value>: Update type.
66 Use PPC_INT_FMT for printing instructions and operands.
67 * opcodes/ppc-opc.c (insert_arx, extract_arx, insert_ary, extract_ary,
68 insert_rx, extract_rx, insert_ry, extract_ry, insert_bat, extract_bat,
69 insert_bba, extract_bba, insert_bdm, extract_bdm, insert_bdp,
70 extract_bdp, valid_bo_pre_v2, valid_bo_post_v2, valid_bo, insert_bo,
71 extract_bo, insert_boe, extract_boe, insert_dcmxs, extract_dcmxs,
72 insert_dxd, extract_dxd, insert_dxdn, extract_dxdn, insert_fxm,
73 extract_fxm, insert_li20, extract_li20, insert_ls, extract_ls,
74 insert_esync, extract_esync, insert_mbe, extract_mbe, insert_mb6,
75 extract_mb6, extract_nb, insert_nbi, insert_nsi, extract_nsi,
76 insert_ral, extract_ral, insert_ram, extract_ram, insert_raq,
77 extract_raq, insert_ras, extract_ras, insert_rbs, extract_rbs,
78 insert_rbx, extract_rbx, insert_sci8, extract_sci8, insert_sci8n,
79 extract_sci8n, insert_sd4h, extract_sd4h, insert_sd4w, extract_sd4w,
80 insert_oimm, extract_oimm, insert_sh6, extract_sh6, insert_spr,
81 extract_spr, insert_sprg, extract_sprg, insert_tbr, extract_tbr,
82 insert_xt6, extract_xt6, insert_xtq6, extract_xtq6, insert_xa6,
83 extract_xa6, insert_xb6, extract_xb6, insert_xb6s, extract_xb6s,
84 insert_xc6, extract_xc6, insert_dm, extract_dm, insert_vlesi,
85 extract_vlesi, insert_vlensi, extract_vlensi, insert_vleui,
86 extract_vleui, insert_vleil, extract_vleil, insert_evuimm1_ex0,
87 extract_evuimm1_ex0, insert_evuimm2_ex0, extract_evuimm2_ex0,
88 insert_evuimm4_ex0, extract_evuimm4_ex0, insert_evuimm8_ex0,
89 extract_evuimm8_ex0, insert_evuimm_lt8, extract_evuimm_lt8,
90 insert_evuimm_lt16, extract_evuimm_lt16, insert_rD_rS_even,
91 extract_rD_rS_even, insert_off_lsp, extract_off_lsp, insert_off_spe2,
92 extract_off_spe2, insert_Ddd, extract_Ddd): Update types.
93 (OP, OPTO, OPL, OPVUP, OPVUPRT, A, AFRALFRC_MASK, B, BD8, BD8IO, BD15,
94 BD24, BBO, Y_MASK , AT1_MASK, AT2_MASK, BBOCB, C_LK, C, CTX, UCTX,
95 DX, EVSEL, IA16, I16A, I16L, IM7, LI20, MME, MD, MDS, SC, SC_MASK,
96 SCI8, SCI8BF, SD4, SE_IM5, SE_R, SE_RR, VX, VX_LSP, VX_RA_CONST,
97 VX_RB_CONST, VX_SPE_CRFD, VX_SPE2_CLR, VX_SPE2_SPLATB, VX_SPE2_OCTET,
98 VX_SPE2_DDHH, VX_SPE2_HH, VX_SPE2_EVMAR, VX_SPE2_EVMAR_MASK, VXA,
99 VXR, VXASH, X, EX, XX2, XX3, XX3RC, XX4, Z, XWRA_MASK, XLRT_MASK,
100 XRLARB_MASK, XLRAND_MASK, XRTLRA_MASK, XRTLRARB_MASK, XRTARARB_MASK,
101 XRTBFRARB_MASK, XOPL, XOPL2, XRCL, XRT, XRTRA, XCMP_MASK, XCMPL_MASK,
102 XTO, XTLB, XSYNC, XEH_MASK, XDSS, XFL, XISEL, XL, XLO, XLYLK, XLOCB,
103 XMBAR, XO, XOPS, XS, XFXM, XSPR, XUC, XW, APU): Update types in casts.
105 2017-11-29 Jan Beulich <jbeulich@suse.com>
107 * i386-gen.c (active_cpu_flags, active_isstring, enum stage):
109 (output_cpu_flags): Update active_cpu_flags.
110 (process_i386_opcode_modifier): Update active_isstring.
111 (output_operand_type): Rename "macro" parameter to "stage",
113 (process_i386_operand_type): Likewise. Track presence of
114 BaseIndex and emit DispN accordingly.
115 (output_i386_opcode, process_i386_registers,
116 process_i386_initializers): Adjust calls to
117 process_i386_operand_type() for its changed parameter type.
118 * i386-opc.tbl: Drop Disp8, Disp16, Disp32, and Disp32S from
119 all insns operands having BaseIndex set.
120 * i386-tbl.h: Re-generate.
122 2017-11-29 Jan Beulich <jbeulich@suse.com>
124 * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_VEC_DISP8
126 (operand_types): Remove Vec_Disp8 entry.
127 * i386-opc.h (Vec_Disp8): Delete.
128 (union i386_operand_type): Remove vec_disp8.
129 (i386-opc.tbl): Remove Vec_Disp8.
130 * i386-init.h, i386-tbl.h: Re-generate.
132 2017-11-29 Stefan Stroe <stroestefan@gmail.com>
134 * po/Make-in (datadir): Define as @datadir@.
135 (localedir): Define as @localedir@.
136 (gnulocaledir, gettextsrcdir): Use @datarootdir@.
138 2017-11-27 Nick Clifton <nickc@redhat.com>
140 * po/zh_CN.po: Updated simplified Chinese translation.
142 2017-11-24 Jan Beulich <jbeulich@suse.com>
144 * i386-dis.c (float_mem): Add suffixes to fi* in the "de" and
147 2017-11-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
149 * i386-opc.tbl: Add Disp8MemShift for AVX512 VAES instructions.
150 * i386-tbl.h: Regenerate.
152 2017-11-23 Jan Beulich <jbeulich@suse.com>
154 * i386-dis.c (OP_E_memory): Also shift the 8-bit immediate in
155 the 16-bit addressing case.
157 2017-11-23 Jan Beulich <jbeulich@suse.com>
159 * i386-dis.c (dis386_twobyte): Correct ud1. Add ud0.
160 (twobyte_has_modrm): Set flag for index 0xb9 and 0xff.
161 * i386-opc.tbl (ud1, ud2b): Add operands.
163 * i386-tbl.h: Re-generate.
165 2017-11-22 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
167 * i386-opc.tbl: Remove Vec_Disp8 from vgf2p8mulb.
168 * i386-tbl.h: Regenerate.
170 2017-11-22 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
172 * i386-opc.tbl: Remove Vec_Disp8 from vpcompressb and vpexpandb.
173 * i386-tbl.h: Regenerate.
175 2017-11-22 Claudiu Zissulescu <claziss@synopsys.com>
177 *arc-opc (insert_rhv2): Check h-regs range.
179 2017-11-21 Claudiu Zissulescu <claziss@synopsys.com>
181 * arc-dis.c (print_insn_arc): Pretty print pc-relative offsets.
182 * arc-opc.c (SIMM21_A16_5): Make it pc-relative.
184 2017-11-16 Tamar Christina <tamar.christina@arm.com>
186 * aarch64-tbl.h (aarch64_feature_fp_16_v8_2): Require AARCH64_FEATURE_F16_FML
187 and AARCH64_FEATURE_F16.
189 2017-11-16 Tamar Christina <tamar.christina@arm.com>
191 * aarch64-tbl.h (sha512h, sha512h2, sha512su0, sha512su1, eor3): New.
192 (rax1, xar, bcax, sm3ss1, sm3tt1a, sm3tt1b, sm3tt2a, sm3tt2b): New.
193 (sm3partw1, sm3partw2, sm4e, sm4ekey, fmlal, fmlsl): New.
194 (fmlal2, fmlsl2, cfinv, rmif, setf8, setf16, stlurb): New.
195 (ldapurb, ldapursb, stlurh, ldapurh, ldapursh, stlur): New.
196 (ldapur, ldapursw, stlur): New.
197 * aarch64-dis-2.c: Regenerate.
199 2017-11-16 Jan Beulich <jbeulich@suse.com>
201 (get_valid_dis386): Never flag bad opcode when
202 vex.register_specifier is beyond 7. Always store all four
203 bits of it. Move 16-/32-bit override in EVEX handling after
204 all to be overridden bits have been set.
205 (OP_VEX): Mask vex.register_specifier outside of 64-bit mode.
206 Use rex to determine GPR register set.
207 (OP_EX_VexReg, OP_Vex_2src_1, OP_Vex_2src_2, OP_REG_VexI4,
208 OP_LWP_E): Mask vex.register_specifier outside of 64-bit mode.
210 2017-11-15 Jan Beulich <jbeulich@suse.com>
212 * i386-dis.c (OP_VEX, OP_LWPCB_E, OP_LWP_E): Use rex to
213 determine GPR register set.
215 2017-11-15 Jan Beulich <jbeulich@suse.com>
217 * i386-dis.c (VEXI4_Fixup, VexI4): Delete.
218 (prefix_table, xop_table, vex_len_table): Remove VexI4 uses.
219 (OP_EX_VexW): Move setting of vex_w_done. Update codep on 2nd
221 (OP_REG_VexI4): Drop low 4 bits check.
223 2017-11-15 Jan Beulich <jbeulich@suse.com>
225 * i386-reg.tbl (axl): Remove Acc and Byte.
226 * i386-tbl.h: Re-generate.
228 2017-11-14 Jan Beulich <jbeulich@suse.com>
230 * i386-dis.c (VPCOM_Fixup, VPCOM, xop_cmp_op): New.
231 (vex_len_table): Use VPCOM.
233 2017-11-14 Jan Beulich <jbeulich@suse.com>
235 * i386-dis-evex.h (evex_table[EVEX_W_0F3A3E_P_2]): Use VPCMP.
236 (evex_table[EVEX_W_0F3A3F_P_2]): Likewise.
237 * i386-opc.tbl (vpcmpeqb, vpcmpgtb, vpcmpeqw, vpcmpgtw, vpcmpuw,
239 (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb, vpcmpnleb, vpcmpnltb,
240 vpcmpequb, vpcmpleub, vpcmpltub, vpcmpnequb, vpcmpnleub,
241 vpcmpnltub, vpcmpeqw, vpcmplew, vpcmpltw, vpcmpneqw, vpcmpnlew,
242 vpcmpnltw, vpcmpequw, vpcmpleuw, vpcmpltuw, vpcmpnequw, vpcmpnleuw,
244 * i386-tbl.h: Re-generate.
246 2017-11-14 Jan Beulich <jbeulich@suse.com>
248 * i386-opc.tbl (cmps, ins, lods, movs, outs, scas, scmp, slod,
249 smov, ssca, stos, ssto, xlat): Drop Disp*.
250 * i386-tbl.h: Re-generate.
252 2017-11-13 Jan Beulich <jbeulich@suse.com>
254 * i386-opc.tbl (fxsave64, fxrstor64, xsave64, xrstor64,
255 xsaveopt64): Add No_qSuf.
256 * i386-tbl.h: Re-generate.
258 2017-11-09 Tamar Christina <tamar.christina@arm.com>
260 * aarch64-opc.c (aarch64_sys_regs): Add ARMv8.4-a registers;
261 dit, vstcr_el2, vsttbr_el2, cnthvs_tval_el2, cnthvs_cval_el2,
262 cnthvs_ctl_el2, cnthps_tval_el2, cnthps_cval_el2, cnthps_ctl_el2,
263 sder32_el2, vncr_el2.
264 (aarch64_sys_reg_supported_p): Likewise.
265 (aarch64_pstatefields): Add dit register.
266 (aarch64_pstatefield_supported_p): Likewise.
267 (aarch64_sys_regs_tlbi): Add vmalle1os, vae1os, aside1os, vaae1os,
268 vale1os, vaale1os, ipas2e1os, ipas2le1os, vae2os, vale2os, vmalls12e1os,
269 vae3os, vale3os, alle2os, alle1os, alle3os, rvae1, rvaae1, rvale1,
270 rvaale1, rvae1is, rvaae1is, rvale1is, rvaale1is, rvae1os, rvaae1os,
271 rvale1os, rvaale1os, ripas2e1is, ripas2le1is, ripas2e1, ripas2le1,
272 ripas2e1os, ripas2le1os, rvae2, rvale2, rvae2is, rvale2is, rvae2os,
273 rvale2os, rvae3, rvale3, rvae3is, rvale3is, rvae3os, rvale3os.
275 2017-11-09 Tamar Christina <tamar.christina@arm.com>
277 * aarch64-tbl.h (QL_SHA512UPT, QL_V2SAME2D, QL_V3SAME2D): New.
278 (QL_V4SAME16B, QL_V4SAME4S, QL_XAR, QL_SM3TT, QL_V3FML2S): New.
279 (QL_V3FML4S, QL_V2FML2S, QL_V2FML4S, QL_RMIF, QL_SETF): New.
280 (QL_STLW, QL_STLX): New.
282 2017-11-09 Tamar Christina <tamar.christina@arm.com>
284 * aarch64-asm.h (ins_addr_offset): New.
285 * aarch64-asm.c (aarch64_ins_reglane): Add cryptosm3.
286 (aarch64_ins_addr_offset): New.
287 * aarch64-asm-2.c: Regenerate.
288 * aarch64-dis.h (ext_addr_offset): New.
289 * aarch64-dis.c (aarch64_ext_reglane): Add cryptosm3.
290 (aarch64_ext_addr_offset): New.
291 * aarch64-dis-2.c: Regenerate.
292 * aarch64-opc.h (aarch64_field_kind): Add FLD_imm6_2,
293 FLD_imm4_2 and FLD_SM3_imm2.
294 * aarch64-opc.c (fields): Add FLD_imm6_2,
295 FLD_imm4_2 and FLD_SM3_imm2.
296 (operand_general_constraint_met_p): Add AARCH64_OPND_ADDR_OFFSET.
297 (aarch64_print_operand): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2,
298 AARCH64_OPND_MASK, AARCH64_OPND_IMM_2 and AARCH64_OPND_ADDR_OFFSET.
299 * aarch64-opc-2.c (Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2): New.
301 (aarch64_opcode_table): Add Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2.
303 2017-11-09 Tamar Christina <tamar.christina@arm.com>
306 (aarch64_feature_v8_4, aarch64_feature_crypto_v8_2): New.
307 (aarch64_feature_sm4, aarch64_feature_sha3): New.
308 (aarch64_feature_fp_16_v8_2): New.
309 (ARMV8_4, SHA3, SM4, CRYPTO_V8_2, FP_F16_V8_2): New.
310 (V8_4_INSN, CRYPTO_V8_2_INSN): New.
311 (SHA3_INSN, SM4_INSN, FP16_V8_2_INSN): New.
313 2017-11-08 Tamar Christina <tamar.christina@arm.com>
315 * aarch64-tbl.h (aarch64_feature_crypto): Add AES and SHA2.
316 (aarch64_feature_sha2, aarch64_feature_aes): New.
318 (AES_INSN, SHA2_INSN): New.
319 (pmull, pmull2, aese, aesd, aesmc, aesimc): Change to AES_INS.
320 (sha1h, sha1su1, sha256su0, sha1c, sha1p,
321 sha1m, sha1su0, sha256h, sha256h2, sha256su1):
324 2017-11-08 Jiong Wang <jiong.wang@arm.com>
325 Tamar Christina <tamar.christina@arm.com>
327 * arm-dis.c (coprocessor_opcodes): New entries for ARMv8.2-A new
328 FP16 instructions, including vfmal.f16 and vfmsl.f16.
330 2017-11-07 Andrew Burgess <andrew.burgess@embecosm.com>
332 * arc-nps400-tbl.h: Change incorrect use of NONE to MISC.
334 2017-11-07 Alan Modra <amodra@gmail.com>
336 * opintl.h: Formatting, comment fixes.
337 (gettext, ngettext): Redefine when ENABLE_NLS.
338 (ngettext, dngettext, dcngettext): Define when !ENABLE_NLS.
339 (_): Define using gettext.
340 (textdomain, bindtextdomain): Use safer "do nothing".
342 2017-11-03 Claudiu Zissulescu <claziss@synopsys.com>
344 * arc-dis.c (print_hex): New variable.
345 (parse_option): Check for hex option.
346 (print_insn_arc): Use hexadecimal representation for short
347 immediate values when requested.
348 (print_arc_disassembler_options): Add hex option to the list.
350 2017-11-03 Claudiu Zissulescu <claziss@synopsys.com>
352 * arc-tbl.h (abss, abssh, adc, adcs, adds, aslacc, asls, aslsacc)
353 (asrs, asrsr, cbflyhf0r, cbflyhf1r, cmacchfr, cmacchnfr, cmachfr)
354 (cmachnfr, cmpychfr, cmpychnfr, cmpyhfmr, cmpyhfr, cmpyhnfr, divf)
355 (dmachbl, dmachbm, dmachf, dmachfr, dmacwhf, dmpyhbl, dmpyhbm)
356 (dmpyhf, dmpyhfr, dmpyhwf, dmpywhf, dsync, flagacc, getacc, macdf)
357 (macf, macfr, macwhfl, macwhflr, macwhfm, macwhfmr, macwhkl)
358 (macwhkul, macwhl, macwhul, mpydf, mpyf, mpyfr, mpywhfl, mpywhflr)
359 (mpywhfm, mpywhfmr, mpywhkl, mpywhkul, mpywhl, mpywhul, msubdf)
360 (msubf, msubfr, msubwhfl, msubwhflr, msubwhfm, msubwhfmr, mul64)
361 (negs, negsh, normacc, qmachf, qmpyh, qmpyhf, rndh, satf, sath)
362 (sbcs, setacc, sflag, sqrt, sqrtf, subs, swi_s, vabs2h, vabss2h)
363 (vadd4b, vadds2, vadds2h, vadds4h, vaddsubs, vaddsubs2h)
364 (vaddsubs4h, valgn2h, vasl2h, vasls2h, vasr2h, vasrs2h, vasrsr2h)
365 (vext2bhl, vext2bhlf, vext2bhm, vext2bhmf, vlsr2h, vmac2hf)
366 (vmac2hfr, vmac2hnfr, vmax2h, vmin2h, vmpy2h, vmpy2hf, vmpy2hfr)
367 (vmpy2hwf, vmsub2hf, vmsub2hfr, vmsub2hnfr, vneg2h, vnegs2h)
368 (vnorm2h, vpack2hbl, vpack2hblf, vpack2hbm, vpack2hbmf, vpack2hl)
369 (vpack2hm, vperm, vrep2hl, vrep2hm, vsext2bhl, vsext2bhm, vsub4b)
370 (vsubadds, vsubadds2h, vsubadds4h, vsubs2, vsubs2h, vsubs4h):
372 (prealloc, prefetch*): Place them before ld instruction.
373 * arc-opc.c (skip_this_opcode): Add ARITH class.
375 2017-10-25 Alan Modra <amodra@gmail.com>
378 * cr16-dis.c (cr16_cinvs, instruction, cr16_currInsn): Make static.
379 (cr16_words, cr16_allWords, processing_argument_number): Likewise.
380 (imm4flag, size_changed): Likewise.
381 * crx-dis.c (crx_cinvs, NUMCINVS, instruction, currInsn): Likewise.
382 (words, allWords, processing_argument_number): Likewise.
383 (cst4flag, size_changed): Likewise.
384 * crx-opc.c (crx_cst4_map): Rename from cst4_map.
385 (crx_cst4_maps): Rename from cst4_maps.
386 (crx_no_op_insn): Rename from no_op_insn.
388 2017-10-24 Andrew Waterman <andrew@sifive.com>
390 * riscv-opc.c (match_c_addi16sp) : New function.
391 (match_c_addi4spn): New function.
392 (match_c_lui): Don't allow 0-immediate encodings.
393 (riscv_opcodes) <addi>: Use the above functions.
395 <c.addi4spn>: Likewise.
396 <c.addi16sp>: Likewise.
398 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
400 * i386-init.h: Regenerate
401 * i386-tbl.h: Likewise
403 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
405 * i386-dis.c (enum): Add PREFIX_EVEX_0F3854, PREFIX_EVEX_0F388F.
406 (enum): Add EVEX_W_0F3854_P_2.
407 * i386-dis-evex.h (evex_table): Updated.
408 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BITALG,
409 CPU_ANY_AVX512_BITALG_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
410 (cpu_flags): Add CpuAVX512_BITALG.
411 * i386-opc.h (enum): Add CpuAVX512_BITALG.
412 (i386_cpu_flags): Add cpuavx512_bitalg..
413 * i386-opc.tbl: Add Intel AVX512_BITALG instructions.
414 * i386-init.h: Regenerate.
415 * i386-tbl.h: Likewise.
417 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
419 * i386-dis.c (enum): Add PREFIX_EVEX_0F3850, PREFIX_EVEX_0F3851.
420 * i386-dis-evex.h (evex_table): Updated.
421 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VNNI,
422 CPU_ANY_AVX512_VNNI_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
423 (cpu_flags): Add CpuAVX512_VNNI.
424 * i386-opc.h (enum): Add CpuAVX512_VNNI.
425 (i386_cpu_flags): Add cpuavx512_vnni.
426 * i386-opc.tbl Add Intel AVX512_VNNI instructions.
427 * i386-init.h: Regenerate.
428 * i386-tbl.h: Likewise.
430 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
432 * i386-dis.c (enum): Add PREFIX_EVEX_0F3A44.
433 (enum): Remove VEX_LEN_0F3A44_P_2.
434 (vex_len_table): Ditto.
435 (enum): Remove VEX_W_0F3A44_P_2.
436 (vew_w_table): Ditto.
437 (prefix_table): Adjust instructions (see prefixes above).
438 * i386-dis-evex.h (evex_table):
439 Add new instructions (see prefixes above).
440 * i386-gen.c (cpu_flag_init): Add VPCLMULQDQ.
441 (bitfield_cpu_flags): Ditto.
442 * i386-opc.h (enum): Ditto.
443 (i386_cpu_flags): Ditto.
444 (CpuUnused): Comment out to avoid zero-width field problem.
445 * i386-opc.tbl (vpclmulqdq): New instruction.
446 * i386-init.h: Regenerate.
449 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
451 * i386-dis.c (enum): Add PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD,
452 PREFIX_EVEX_0F38DE, PREFIX_EVEX_0F38DF.
453 (enum): Remove VEX_LEN_0F38DC_P_2, VEX_LEN_0F38DD_P_2,
454 VEX_LEN_0F38DE_P_2, VEX_LEN_0F38DF_P_2.
455 (vex_len_table): Ditto.
456 (enum): Remove VEX_W_0F38DC_P_2, VEX_W_0F38DD_P_2,
457 VEX_W_0F38DE_P_2, VEX_W_0F38DF_P_2.
458 (vew_w_table): Ditto.
459 (prefix_table): Adjust instructions (see prefixes above).
460 * i386-dis-evex.h (evex_table):
461 Add new instructions (see prefixes above).
462 * i386-gen.c (cpu_flag_init): Add VAES.
463 (bitfield_cpu_flags): Ditto.
464 * i386-opc.h (enum): Ditto.
465 (i386_cpu_flags): Ditto.
466 * i386-opc.tbl (vaes{enc,dec}{last,}): New instructions.
467 * i386-init.h: Regenerate.
470 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
472 * i386-dis.c (enum): Add PREFIX_0F38CF, PREFIX_0F3ACE, PREFIX_0F3ACF,
473 PREFIX_VEX_0F38CF, PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF,
474 PREFIX_EVEX_0F38CF, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF.
475 (enum): Add VEX_W_0F38CF_P_2, VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2,
476 EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2.
477 (prefix_table): Updated (see prefixes above).
478 (three_byte_table): Likewise.
479 (vex_w_table): Likewise.
480 * i386-dis-evex.h: Likewise.
481 * i386-gen.c (cpu_flag_init): Add CPU_GFNI_FLAGS, CpuGFNI.
482 (cpu_flags): Add CpuGFNI.
483 * i386-opc.h (enum): Add CpuGFNI.
484 (i386_cpu_flags): Add cpugfni.
485 * i386-opc.tbl: Add Intel GFNI instructions.
486 * i386-init.h: Regenerate.
487 * i386-tbl.h: Likewise.
489 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
491 * i386-dis.c (enum): Add b_scalar_mode, w_scalar_mode.
492 Define EXbScalar and EXwScalar for OP_EX.
493 (enum): Add PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863,
494 PREFIX_EVEX_0F3870, PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3872,
495 PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
496 PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73.
497 (enum): Add EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2,
498 EVEX_W_0F3870_P_2, EVEX_W_0F3871_P_2, EVEX_W_0F3872_P_2,
499 EVEX_W_0F3873_P_2, EVEX_W_0F3A70_P_2, EVEX_W_0F3A71_P_2,
500 EVEX_W_0F3A72_P_2, EVEX_W_0F3A73_P_2.
501 (intel_operand_size): Handle b_scalar_mode and w_scalar_mode.
502 (OP_E_memory): Likewise.
503 * i386-dis-evex.h: Updated.
504 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VBMI2,
505 CPU_ANY_AVX512_VBMI2_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
506 (cpu_flags): Add CpuAVX512_VBMI2.
507 * i386-opc.h (enum): Add CpuAVX512_VBMI2.
508 (i386_cpu_flags): Add cpuavx512_vbmi2.
509 * i386-opc.tbl: Add Intel AVX512_VBMI2 instructions.
510 * i386-init.h: Regenerate.
511 * i386-tbl.h: Likewise.
513 2017-10-18 Eric Botcazou <ebotcazou@adacore.com>
515 * visium-dis.c (disassem_class1) <case 0>: Print the operands.
517 2017-10-12 James Bowman <james.bowman@ftdichip.com>
519 * ft32-dis.c (print_insn_ft32): Replace FT32_FLD_K8 with K15.
520 * ft32-opc.c (ft32_opc_info): Replace FT32_FLD_K8 with
521 K15. Add jmpix pattern.
523 2017-10-09 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
525 * s390-opc.txt (prno, tpei, irbm): New instructions added.
527 2017-10-09 Heiko Carstens <heiko.carstens@de.ibm.com>
529 * s390-opc.c (INSTR_SI_RD): New macro.
530 (INSTR_S_RD): Adjust example instruction.
531 * s390-opc.txt (lpsw, ssm, ts): Change S_RD instruction format to
534 2017-10-01 Alexander Fedotov <alfedotov@gmail.com>
536 * ppc-opc.c (vle_opcodes): Add e_lmvsprw, e_lmvgprw,
537 e_lmvsrrw, e_lmvcsrrw and e_lmvcsrrw as official mnemonics for
538 VLE multimple load/store instructions. Old e_ldm* variants are
540 Add missing e_lmvmcsrrw and e_stmvmcsrrw.
542 2017-09-27 Nick Clifton <nickc@redhat.com>
545 * riscv-opc.c (riscv_opcodes): Add fmv.x.w and fmv.w.x as the new
546 names for the fmv.x.s and fmv.s.x instructions respectively.
548 2017-09-26 do <do@nerilex.org>
551 * m68k-opc.c (m68k_opcodes): Allow macw and macl instructions to
552 be used on CPUs that have emacs support.
554 2017-09-21 Sergio Durigan Junior <sergiodj@redhat.com>
556 * aarch64-opc.c (expand_fp_imm): Initialize 'imm'.
558 2017-09-09 Kamil Rytarowski <n54@gmx.com>
560 * nds32-asm.c: Rename __BIT() to N32_BIT().
561 * nds32-asm.h: Likewise.
562 * nds32-dis.c: Likewise.
564 2017-09-09 H.J. Lu <hongjiu.lu@intel.com>
566 * i386-dis.c (last_active_prefix): Removed.
567 (ckprefix): Don't set last_active_prefix.
568 (NOTRACK_Fixup): Don't check last_active_prefix.
570 2017-08-31 Nick Clifton <nickc@redhat.com>
572 * po/fr.po: Updated French translation.
574 2017-08-31 James Bowman <james.bowman@ftdichip.com>
576 * ft32-dis.c (print_insn_ft32): Correct display of non-address
579 2017-08-23 Alexander Fedotov <alexander.fedotov@nxp.com>
580 Edmar Wienskoski <edmar.wienskoski@nxp.com>
582 * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_SPE2 and
583 PPC_OPCODE_EFS2 flag to "e200z4" entry.
584 New entries efs2 and spe2.
585 Add PPC_OPCODE_SPE2 and PPC_OPCODE_EFS2 flag to "vle" entry.
586 (SPE2_OPCD_SEGS): New macro.
587 (spe2_opcd_indices): New.
588 (disassemble_init_powerpc): Handle SPE2 opcodes.
589 (lookup_spe2): New function.
590 (print_insn_powerpc): call lookup_spe2.
591 * ppc-opc.c (insert_evuimm1_ex0): New function.
592 (extract_evuimm1_ex0): Likewise.
593 (insert_evuimm_lt8): Likewise.
594 (extract_evuimm_lt8): Likewise.
595 (insert_off_spe2): Likewise.
596 (extract_off_spe2): Likewise.
597 (insert_Ddd): Likewise.
598 (extract_Ddd): Likewise.
600 (EVUIMM_LT8): Likewise.
601 (EVUIMM_LT16): Adjust.
603 (EVUIMM_1): Likewise.
604 (EVUIMM_1_EX0): Likewise.
607 (VX_OFF_SPE2): Likewise.
610 (VX_MASK_DDD): New mask.
612 (VX_RA_CONST): New macro.
613 (VX_RA_CONST_MASK): Likewise.
614 (VX_RB_CONST): Likewise.
615 (VX_RB_CONST_MASK): Likewise.
616 (VX_OFF_SPE2_MASK): Likewise.
617 (VX_SPE_CRFD): Likewise.
618 (VX_SPE_CRFD_MASK VX): Likewise.
619 (VX_SPE2_CLR): Likewise.
620 (VX_SPE2_CLR_MASK): Likewise.
621 (VX_SPE2_SPLATB): Likewise.
622 (VX_SPE2_SPLATB_MASK): Likewise.
623 (VX_SPE2_OCTET): Likewise.
624 (VX_SPE2_OCTET_MASK): Likewise.
625 (VX_SPE2_DDHH): Likewise.
626 (VX_SPE2_DDHH_MASK): Likewise.
627 (VX_SPE2_HH): Likewise.
628 (VX_SPE2_HH_MASK): Likewise.
629 (VX_SPE2_EVMAR): Likewise.
630 (VX_SPE2_EVMAR_MASK): Likewise.
633 (vle_opcodes): Add EFS2 and some missing SPE opcodes.
634 (powerpc_macros): Map old SPE instructions have new names
635 with the same opcodes. Add SPE2 instructions which just are
637 (spe2_opcodes): Add SPE2 opcodes.
639 2017-08-23 Alan Modra <amodra@gmail.com>
641 * ppc-opc.c: Formatting and comment fixes. Move insert and
642 extract functions earlier, deleting forward declarations.
643 (insert_nbi, insert_raq, insert_rbx): Expand use of RT_MASK and
646 2017-08-22 Palmer Dabbelt <palmer@dabbelt.com>
648 * riscv-opc.c (riscv_opcodes): Mark "c.nop" as an alias.
650 2017-08-21 Alexander Fedotov <alexander.fedotov@nxp.com>
651 Edmar Wienskoski <edmar.wienskoski@nxp.com>
653 * ppc-opc.c (insert_evuimm2_ex0): New function.
654 (extract_evuimm2_ex0): Likewise.
655 (insert_evuimm4_ex0): Likewise.
656 (extract_evuimm4_ex0): Likewise.
657 (insert_evuimm8_ex0): Likewise.
658 (extract_evuimm8_ex0): Likewise.
659 (insert_evuimm_lt16): Likewise.
660 (extract_evuimm_lt16): Likewise.
661 (insert_rD_rS_even): Likewise.
662 (extract_rD_rS_even): Likewise.
663 (insert_off_lsp): Likewise.
664 (extract_off_lsp): Likewise.
665 (RD_EVEN): New operand.
668 (EVUIMM_LT16): New operand.
670 (EVUIMM_2_EX0): New operand.
672 (EVUIMM_4_EX0): New operand.
674 (EVUIMM_8_EX0): New operand.
676 (VX_OFF): New operand.
678 (VX_LSP_MASK): Likewise.
679 (VX_LSP_OFF_MASK): Likewise.
680 (PPC_OPCODE_LSP): Likewise.
681 (vle_opcodes): Add LSP opcodes.
682 * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_LSP flag to "vle" entry.
684 2017-08-09 Jiong Wang <jiong.wang@arm.com>
686 * arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for
687 register operands in CRC instructions.
688 (print_insn_thumb32): Remove "<bitfield>S" support. Updated the
691 2017-08-07 H.J. Lu <hongjiu.lu@intel.com>
693 * disassemble.c (disassembler): Mark big and mach with
696 2017-08-07 Maciej W. Rozycki <macro@imgtec.com>
698 * disassemble.c (disassembler): Remove arch/mach/endian
701 2017-07-25 Nick Clifton <nickc@redhat.com>
704 * arc-opc.c (insert_rhv2): Use lower case first letter in error
706 (insert_r0): Likewise.
707 (insert_r1): Likewise.
708 (insert_r2): Likewise.
709 (insert_r3): Likewise.
710 (insert_sp): Likewise.
711 (insert_gp): Likewise.
712 (insert_pcl): Likewise.
713 (insert_blink): Likewise.
714 (insert_ilink1): Likewise.
715 (insert_ilink2): Likewise.
716 (insert_ras): Likewise.
717 (insert_rbs): Likewise.
718 (insert_rcs): Likewise.
719 (insert_simm3s): Likewise.
720 (insert_rrange): Likewise.
721 (insert_r13el): Likewise.
722 (insert_fpel): Likewise.
723 (insert_blinkel): Likewise.
724 (insert_pclel): Likewise.
725 (insert_nps_bitop_size_2b): Likewise.
726 (insert_nps_imm_offset): Likewise.
727 (insert_nps_imm_entry): Likewise.
728 (insert_nps_size_16bit): Likewise.
729 (insert_nps_##NAME##_pos): Likewise.
730 (insert_nps_##NAME): Likewise.
731 (insert_nps_bitop_ins_ext): Likewise.
732 (insert_nps_##NAME): Likewise.
733 (insert_nps_min_hofs): Likewise.
734 (insert_nps_##NAME): Likewise.
735 (insert_nps_rbdouble_64): Likewise.
736 (insert_nps_misc_imm_offset): Likewise.
737 * riscv-dis.c (print_riscv_disassembler_options): Fix typo in
740 2017-07-24 Laurent Desnogues <laurent.desnogues@arm.com>
741 Jiong Wang <jiong.wang@arm.com>
743 * aarch64-gen.c (print_decision_tree_1): Reverse the index of PATTERN to
745 * aarch64-dis-2.c: Regenerated.
747 2017-07-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
749 * s390-mkopc.c (main): Enable z14 as CPU string in the opcode
752 2017-07-20 Nick Clifton <nickc@redhat.com>
754 * po/de.po: Updated German translation.
756 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
758 * arc-regs.h (sec_stat): New aux register.
759 (aux_kernel_sp): Likewise.
760 (aux_sec_u_sp): Likewise.
761 (aux_sec_k_sp): Likewise.
762 (sec_vecbase_build): Likewise.
763 (nsc_table_top): Likewise.
764 (nsc_table_base): Likewise.
765 (ersec_stat): Likewise.
766 (aux_sec_except): Likewise.
768 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
770 * arc-opc.c (extract_uimm12_20): New function.
771 (UIMM12_20): New operand.
773 * arc-tbl.h (sjli): Add new instruction.
775 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
776 John Eric Martin <John.Martin@emmicro-us.com>
778 * arc-opc.c (UIMM10_6_S_JLIOFF): Define.
779 (UIMM3_23): Adjust accordingly.
780 * arc-regs.h: Add/correct jli_base register.
781 * arc-tbl.h (jli_s): Likewise.
783 2017-07-18 Nick Clifton <nickc@redhat.com>
786 * aarch64-opc.c: Fix spelling typos.
787 * i386-dis.c: Likewise.
789 2017-07-14 Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
791 * dis-buf.c (buffer_read_memory): Change type of end_addr_offset,
792 max_addr_offset and octets variables to size_t.
794 2017-07-12 Alan Modra <amodra@gmail.com>
796 * po/da.po: Update from translationproject.org/latest/opcodes/.
797 * po/de.po: Likewise.
798 * po/es.po: Likewise.
799 * po/fi.po: Likewise.
800 * po/fr.po: Likewise.
801 * po/id.po: Likewise.
802 * po/it.po: Likewise.
803 * po/nl.po: Likewise.
804 * po/pt_BR.po: Likewise.
805 * po/ro.po: Likewise.
806 * po/sv.po: Likewise.
807 * po/tr.po: Likewise.
808 * po/uk.po: Likewise.
809 * po/vi.po: Likewise.
810 * po/zh_CN.po: Likewise.
812 2017-07-11 Yao Qi <yao.qi@linaro.org>
813 Alan Modra <amodra@gmail.com>
815 * cgen.sh: Mark generated files read-only.
816 * epiphany-asm.c: Regenerate.
817 * epiphany-desc.c: Regenerate.
818 * epiphany-desc.h: Regenerate.
819 * epiphany-dis.c: Regenerate.
820 * epiphany-ibld.c: Regenerate.
821 * epiphany-opc.c: Regenerate.
822 * epiphany-opc.h: Regenerate.
823 * fr30-asm.c: Regenerate.
824 * fr30-desc.c: Regenerate.
825 * fr30-desc.h: Regenerate.
826 * fr30-dis.c: Regenerate.
827 * fr30-ibld.c: Regenerate.
828 * fr30-opc.c: Regenerate.
829 * fr30-opc.h: Regenerate.
830 * frv-asm.c: Regenerate.
831 * frv-desc.c: Regenerate.
832 * frv-desc.h: Regenerate.
833 * frv-dis.c: Regenerate.
834 * frv-ibld.c: Regenerate.
835 * frv-opc.c: Regenerate.
836 * frv-opc.h: Regenerate.
837 * ip2k-asm.c: Regenerate.
838 * ip2k-desc.c: Regenerate.
839 * ip2k-desc.h: Regenerate.
840 * ip2k-dis.c: Regenerate.
841 * ip2k-ibld.c: Regenerate.
842 * ip2k-opc.c: Regenerate.
843 * ip2k-opc.h: Regenerate.
844 * iq2000-asm.c: Regenerate.
845 * iq2000-desc.c: Regenerate.
846 * iq2000-desc.h: Regenerate.
847 * iq2000-dis.c: Regenerate.
848 * iq2000-ibld.c: Regenerate.
849 * iq2000-opc.c: Regenerate.
850 * iq2000-opc.h: Regenerate.
851 * lm32-asm.c: Regenerate.
852 * lm32-desc.c: Regenerate.
853 * lm32-desc.h: Regenerate.
854 * lm32-dis.c: Regenerate.
855 * lm32-ibld.c: Regenerate.
856 * lm32-opc.c: Regenerate.
857 * lm32-opc.h: Regenerate.
858 * lm32-opinst.c: Regenerate.
859 * m32c-asm.c: Regenerate.
860 * m32c-desc.c: Regenerate.
861 * m32c-desc.h: Regenerate.
862 * m32c-dis.c: Regenerate.
863 * m32c-ibld.c: Regenerate.
864 * m32c-opc.c: Regenerate.
865 * m32c-opc.h: Regenerate.
866 * m32r-asm.c: Regenerate.
867 * m32r-desc.c: Regenerate.
868 * m32r-desc.h: Regenerate.
869 * m32r-dis.c: Regenerate.
870 * m32r-ibld.c: Regenerate.
871 * m32r-opc.c: Regenerate.
872 * m32r-opc.h: Regenerate.
873 * m32r-opinst.c: Regenerate.
874 * mep-asm.c: Regenerate.
875 * mep-desc.c: Regenerate.
876 * mep-desc.h: Regenerate.
877 * mep-dis.c: Regenerate.
878 * mep-ibld.c: Regenerate.
879 * mep-opc.c: Regenerate.
880 * mep-opc.h: Regenerate.
881 * mt-asm.c: Regenerate.
882 * mt-desc.c: Regenerate.
883 * mt-desc.h: Regenerate.
884 * mt-dis.c: Regenerate.
885 * mt-ibld.c: Regenerate.
886 * mt-opc.c: Regenerate.
887 * mt-opc.h: Regenerate.
888 * or1k-asm.c: Regenerate.
889 * or1k-desc.c: Regenerate.
890 * or1k-desc.h: Regenerate.
891 * or1k-dis.c: Regenerate.
892 * or1k-ibld.c: Regenerate.
893 * or1k-opc.c: Regenerate.
894 * or1k-opc.h: Regenerate.
895 * or1k-opinst.c: Regenerate.
896 * xc16x-asm.c: Regenerate.
897 * xc16x-desc.c: Regenerate.
898 * xc16x-desc.h: Regenerate.
899 * xc16x-dis.c: Regenerate.
900 * xc16x-ibld.c: Regenerate.
901 * xc16x-opc.c: Regenerate.
902 * xc16x-opc.h: Regenerate.
903 * xstormy16-asm.c: Regenerate.
904 * xstormy16-desc.c: Regenerate.
905 * xstormy16-desc.h: Regenerate.
906 * xstormy16-dis.c: Regenerate.
907 * xstormy16-ibld.c: Regenerate.
908 * xstormy16-opc.c: Regenerate.
909 * xstormy16-opc.h: Regenerate.
911 2017-07-07 Alan Modra <amodra@gmail.com>
913 * cgen-dis.in: Include disassemble.h, not dis-asm.h.
914 * m32c-dis.c: Regenerate.
915 * mep-dis.c: Regenerate.
917 2017-07-05 Borislav Petkov <bp@suse.de>
919 * i386-dis.c: Enable ModRM.reg /6 aliases.
921 2017-07-04 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
923 * opcodes/arm-dis.c: Support MVFR2 in disassembly
926 2017-07-04 Tristan Gingold <gingold@adacore.com>
928 * configure: Regenerate.
930 2017-07-03 Tristan Gingold <gingold@adacore.com>
932 * po/opcodes.pot: Regenerate.
934 2017-06-30 Maciej W. Rozycki <macro@imgtec.com>
936 * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
937 entries to the MSA ASE instruction block.
939 2017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
940 Maciej W. Rozycki <macro@imgtec.com>
942 * micromips-opc.c (XPA, XPAVZ): New macros.
943 (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
946 2017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
947 Maciej W. Rozycki <macro@imgtec.com>
949 * micromips-opc.c (I36): New macro.
950 (micromips_opcodes): Add "eretnc".
952 2017-06-30 Maciej W. Rozycki <macro@imgtec.com>
953 Andrew Bennett <andrew.bennett@imgtec.com>
955 * mips-dis.c (mips_calculate_combination_ases): Handle the
957 (parse_mips_ase_option): New function.
958 (parse_mips_dis_option): Factor out ASE option handling to the
959 new function. Call `mips_calculate_combination_ases'.
960 * mips-opc.c (XPAVZ): New macro.
961 (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
962 "mfhgc0", "mthc0" and "mthgc0".
964 2017-06-29 Maciej W. Rozycki <macro@imgtec.com>
966 * mips-dis.c (mips_calculate_combination_ases): New function.
967 (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
968 calculation to the new function.
969 (set_default_mips_dis_options): Call the new function.
971 2017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
973 * arc-dis.c (parse_disassembler_options): Use
974 FOR_EACH_DISASSEMBLER_OPTION.
976 2017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
978 * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
979 disassembler option strings.
980 (parse_cpu_option): Likewise.
982 2017-06-28 Tamar Christina <tamar.christina@arm.com>
984 * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
985 * aarch64-dis.c (aarch64_ext_reglane): Likewise.
986 * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
987 (aarch64_feature_dotprod, DOT_INSN): New.
989 * aarch64-dis-2.c: Regenerated.
991 2017-06-28 Jiong Wang <jiong.wang@arm.com>
993 * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
995 2017-06-28 Maciej W. Rozycki <macro@imgtec.com>
996 Matthew Fortune <matthew.fortune@imgtec.com>
997 Andrew Bennett <andrew.bennett@imgtec.com>
999 * mips-formats.h (INT_BIAS): New macro.
1000 (INT_ADJ): Redefine in INT_BIAS terms.
1001 * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
1002 (mips_print_save_restore): New function.
1003 (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
1004 (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
1006 (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
1007 (print_mips16_insn_arg): Call `mips_print_save_restore' for
1008 OP_SAVE_RESTORE_LIST handling, factored out from here.
1009 * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
1010 (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
1011 (mips_builtin_opcodes): Add "restore" and "save" entries.
1012 * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
1014 (mips16_opcodes): Add "copyw" and "ucopyw" entries.
1016 2017-06-23 Andrew Waterman <andrew@sifive.com>
1018 * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
1019 alias; do not mark SLTI instruction as an alias.
1021 2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
1023 * i386-dis.c (RM_0FAE_REG_5): Removed.
1024 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
1025 (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
1026 (PREFIX_MOD_3_0FAE_REG_5): Likewise.
1027 (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1. Add
1028 PREFIX_MOD_3_0F01_REG_5_RM_0.
1029 (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5. Add
1030 PREFIX_MOD_3_0FAE_REG_5.
1031 (mod_table): Update MOD_0FAE_REG_5.
1032 (rm_table): Update RM_0F01_REG_5. Remove RM_0FAE_REG_5.
1033 * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
1034 * i386-tbl.h: Regenerated.
1036 2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
1038 * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
1039 * i386-opc.tbl: Likewise.
1040 * i386-tbl.h: Regenerated.
1042 2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
1044 * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
1046 (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
1049 2017-06-19 Nick Clifton <nickc@redhat.com>
1052 * score-dis.c (score_opcodes): Add sentinel.
1054 2017-06-16 Alan Modra <amodra@gmail.com>
1056 * rx-decode.c: Regenerate.
1058 2017-06-15 H.J. Lu <hongjiu.lu@intel.com>
1061 * i386-dis.c (OP_E_register): Check valid bnd register.
1064 2017-06-15 Nick Clifton <nickc@redhat.com>
1067 * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
1070 2017-06-15 Nick Clifton <nickc@redhat.com>
1073 * rl78-decode.opc (OP_BUF_LEN): Define.
1074 (GETBYTE): Check for the index exceeding OP_BUF_LEN.
1075 (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
1077 * rl78-decode.c: Regenerate.
1079 2017-06-15 Nick Clifton <nickc@redhat.com>
1082 * bfin-dis.c (gregs): Clip index to prevent overflow.
1084 (regs_lo): Likewise.
1085 (regs_hi): Likewise.
1087 2017-06-14 Nick Clifton <nickc@redhat.com>
1090 * score7-dis.c (score_opcodes): Add sentinel.
1092 2017-06-14 Yao Qi <yao.qi@linaro.org>
1094 * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
1095 * arm-dis.c: Likewise.
1096 * ia64-dis.c: Likewise.
1097 * mips-dis.c: Likewise.
1098 * spu-dis.c: Likewise.
1099 * disassemble.h (print_insn_aarch64): New declaration, moved from
1101 (print_insn_big_arm, print_insn_big_mips): Likewise.
1102 (print_insn_i386, print_insn_ia64): Likewise.
1103 (print_insn_little_arm, print_insn_little_mips): Likewise.
1105 2017-06-14 Nick Clifton <nickc@redhat.com>
1108 * rx-decode.opc: Include libiberty.h
1109 (GET_SCALE): New macro - validates access to SCALE array.
1110 (GET_PSCALE): New macro - validates access to PSCALE array.
1111 (DIs, SIs, S2Is, rx_disp): Use new macros.
1112 * rx-decode.c: Regenerate.
1114 2017-07-14 Andre Vieira <andre.simoesdiasvieira@arm.com>
1116 * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
1118 2017-05-30 Anton Kolesov <anton.kolesov@synopsys.com>
1120 * arc-dis.c (enforced_isa_mask): Declare.
1121 (cpu_types): Likewise.
1122 (parse_cpu_option): New function.
1123 (parse_disassembler_options): Use it.
1124 (print_insn_arc): Use enforced_isa_mask.
1125 (print_arc_disassembler_options): Document new options.
1127 2017-05-24 Yao Qi <yao.qi@linaro.org>
1129 * alpha-dis.c: Include disassemble.h, don't include
1131 * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
1132 * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
1133 * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
1134 * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
1135 * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
1136 * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
1137 * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
1138 * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
1139 * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
1140 * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
1141 * moxie-dis.c, msp430-dis.c, mt-dis.c:
1142 * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
1143 * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
1144 * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
1145 * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
1146 * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
1147 * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
1148 * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
1149 * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
1150 * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
1151 * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
1152 * z80-dis.c, z8k-dis.c: Likewise.
1153 * disassemble.h: New file.
1155 2017-05-24 Yao Qi <yao.qi@linaro.org>
1157 * rl78-dis.c (rl78_get_disassembler): If parameter abfd
1158 is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
1160 2017-05-24 Yao Qi <yao.qi@linaro.org>
1162 * disassemble.c (disassembler): Add arguments a, big and mach.
1165 2017-05-22 H.J. Lu <hongjiu.lu@intel.com>
1167 * i386-dis.c (NOTRACK_Fixup): New.
1168 (NOTRACK): Likewise.
1169 (NOTRACK_PREFIX): Likewise.
1170 (last_active_prefix): Likewise.
1171 (reg_table): Use NOTRACK on indirect call and jmp.
1172 (ckprefix): Set last_active_prefix.
1173 (prefix_name): Return "notrack" for NOTRACK_PREFIX.
1174 * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
1175 * i386-opc.h (NoTrackPrefixOk): New.
1176 (i386_opcode_modifier): Add notrackprefixok.
1177 * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
1179 * i386-tbl.h: Regenerated.
1181 2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
1183 * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
1185 (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
1186 bfd_mach_sparc_v9m8.
1187 (print_insn_sparc): Handle new operand types.
1188 * sparc-opc.c (MASK_M8): Define.
1190 (v6notlet): Likewise.
1201 (v9andleon): Likewise.
1204 (HWS2_VM8): Likewise.
1205 (sparc_opcode_archs): Add entry for "m8".
1206 (sparc_opcodes): Add OSA2017 and M8 instructions
1207 dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
1209 ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
1210 ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
1211 revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
1212 stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
1213 (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
1214 ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
1215 ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
1216 ASI_CORE_SELECT_COMMIT_NHT.
1218 2017-05-18 Alan Modra <amodra@gmail.com>
1220 * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
1221 * aarch64-dis.c: Likewise.
1222 * aarch64-gen.c: Likewise.
1223 * aarch64-opc.c: Likewise.
1225 2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
1226 Matthew Fortune <matthew.fortune@imgtec.com>
1228 * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
1229 ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
1230 (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
1231 (print_insn_arg) <OP_REG28>: Add handler.
1232 (validate_insn_args) <OP_REG28>: Handle.
1233 (print_mips16_insn_arg): Handle MIPS16 instructions that require
1234 32-bit encoding and 9-bit immediates.
1235 (print_insn_mips16): Handle MIPS16 instructions that require
1236 32-bit encoding and MFC0/MTC0 operand decoding.
1237 * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
1238 <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
1239 (RD_C0, WR_C0, E2, E2MT): New macros.
1240 (mips16_opcodes): Add entries for MIPS16e2 instructions:
1241 GP-relative "addiu" and its "addu" spelling, "andi", "cache",
1242 "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
1243 "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
1244 "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
1245 "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
1246 instructions, "swl", "swr", "sync" and its "sync_acquire",
1247 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
1248 "xori", "dmt", "dvpe", "emt" and "evpe". Add split
1249 regular/extended entries for original MIPS16 ISA revision
1250 instructions whose extended forms are subdecoded in the MIPS16e2
1251 ISA revision: "li", "sll" and "srl".
1253 2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
1255 * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
1256 reference in CP0 move operand decoding.
1258 2017-05-12 Maciej W. Rozycki <macro@imgtec.com>
1260 * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
1261 type to hexadecimal.
1262 (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
1264 2017-05-11 Maciej W. Rozycki <macro@imgtec.com>
1266 * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
1267 "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
1268 "sync_rmb" and "sync_wmb" as aliases.
1269 * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
1270 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
1272 2017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
1274 * arc-dis.c (parse_option): Update quarkse_em option..
1275 * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
1277 (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
1279 2017-05-03 Kito Cheng <kito.cheng@gmail.com>
1281 * riscv-dis.c (print_insn_args): Handle 'Co' operands.
1283 2017-05-01 Michael Clark <michaeljclark@mac.com>
1285 * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
1288 2017-05-02 Maciej W. Rozycki <macro@imgtec.com>
1290 * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
1291 and branches and not synthetic data instructions.
1293 2017-05-02 Bernd Edlinger <bernd.edlinger@hotmail.de>
1295 * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
1297 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
1299 * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
1300 * arc-opc.c (insert_r13el): New function.
1302 * arc-tbl.h: Add new enter/leave variants.
1304 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
1306 * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
1308 2017-04-25 Maciej W. Rozycki <macro@imgtec.com>
1310 * mips-dis.c (print_mips_disassembler_options): Add
1313 2017-04-25 Maciej W. Rozycki <macro@imgtec.com>
1315 * mips16-opc.c (AL): New macro.
1316 (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
1317 of "ld" and "lw" as aliases.
1319 2017-04-24 Tamar Christina <tamar.christina@arm.com>
1321 * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
1324 2017-04-22 Alexander Fedotov <alfedotov@gmail.com>
1325 Alan Modra <amodra@gmail.com>
1327 * ppc-opc.c (ELEV): Define.
1328 (vle_opcodes): Add se_rfgi and e_sc.
1329 (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
1332 2017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com>
1334 * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
1336 2017-04-21 Nick Clifton <nickc@redhat.com>
1339 * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
1342 2017-04-13 Alan Modra <amodra@gmail.com>
1344 * epiphany-desc.c: Regenerate.
1345 * fr30-desc.c: Regenerate.
1346 * frv-desc.c: Regenerate.
1347 * ip2k-desc.c: Regenerate.
1348 * iq2000-desc.c: Regenerate.
1349 * lm32-desc.c: Regenerate.
1350 * m32c-desc.c: Regenerate.
1351 * m32r-desc.c: Regenerate.
1352 * mep-desc.c: Regenerate.
1353 * mt-desc.c: Regenerate.
1354 * or1k-desc.c: Regenerate.
1355 * xc16x-desc.c: Regenerate.
1356 * xstormy16-desc.c: Regenerate.
1358 2017-04-11 Alan Modra <amodra@gmail.com>
1360 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
1361 PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set
1362 PPC_OPCODE_TMR for e6500.
1363 * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
1364 (PPCVEC3): Define as PPC_OPCODE_POWER9.
1365 (PPCVSX2): Define as PPC_OPCODE_POWER8.
1366 (PPCVSX3): Define as PPC_OPCODE_POWER9.
1367 (PPCHTM): Define as PPC_OPCODE_POWER8.
1368 (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
1370 2017-04-10 Alan Modra <amodra@gmail.com>
1372 * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
1373 * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
1374 (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
1375 removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
1377 2017-04-09 Pip Cet <pipcet@gmail.com>
1379 * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
1380 appropriate floating-point precision directly.
1382 2017-04-07 Alan Modra <amodra@gmail.com>
1384 * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
1385 lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
1386 lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
1387 lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
1388 vector instructions with E6500 not PPCVEC2.
1390 2017-04-06 Pip Cet <pipcet@gmail.com>
1392 * Makefile.am: Add wasm32-dis.c.
1393 * configure.ac: Add wasm32-dis.c to wasm32 target.
1394 * disassemble.c: Add wasm32 disassembler code.
1395 * wasm32-dis.c: New file.
1396 * Makefile.in: Regenerate.
1397 * configure: Regenerate.
1398 * po/POTFILES.in: Regenerate.
1399 * po/opcodes.pot: Regenerate.
1401 2017-04-05 Pedro Alves <palves@redhat.com>
1403 * arc-dis.c (parse_option, parse_disassembler_options): Constify.
1404 * arm-dis.c (parse_arm_disassembler_options): Constify.
1405 * ppc-dis.c (powerpc_init_dialect): Constify local.
1406 * vax-dis.c (parse_disassembler_options): Constify.
1408 2017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
1410 * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
1413 2017-03-30 Pip Cet <pipcet@gmail.com>
1415 * configure.ac: Add (empty) bfd_wasm32_arch target.
1416 * configure: Regenerate
1417 * po/opcodes.pot: Regenerate.
1419 2017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
1421 Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
1423 * opcodes/sparc-opc.c (asi_table): New ASIs.
1425 2017-03-29 Alan Modra <amodra@gmail.com>
1427 * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
1429 (lookup_powerpc): Don't special case -1 dialect. Handle
1431 (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
1432 lookup_powerpc call, pass it on second.
1434 2017-03-27 Alan Modra <amodra@gmail.com>
1437 * ppc-dis.c (struct ppc_mopt): Comment.
1438 (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
1440 2017-03-27 Rinat Zelig <rinat@mellanox.com>
1442 * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
1443 * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
1444 F_NPS_M, F_NPS_CORE, F_NPS_ALL.
1445 (insert_nps_misc_imm_offset): New function.
1446 (extract_nps_misc imm_offset): New function.
1447 (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
1448 (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
1450 2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1452 * s390-mkopc.c (main): Remove vx2 check.
1453 * s390-opc.txt: Remove vx2 instruction flags.
1455 2017-03-21 Rinat Zelig <rinat@mellanox.com>
1457 * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
1458 * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
1459 (insert_nps_imm_offset): New function.
1460 (extract_nps_imm_offset): New function.
1461 (insert_nps_imm_entry): New function.
1462 (extract_nps_imm_entry): New function.
1464 2017-03-17 Alan Modra <amodra@gmail.com>
1467 * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
1468 mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
1469 those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
1471 2017-03-14 Kito Cheng <kito.cheng@gmail.com>
1473 * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
1477 2017-03-14 Kito Cheng <kito.cheng@gmail.com>
1479 * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
1481 2017-03-13 Andrew Waterman <andrew@sifive.com>
1483 * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
1488 2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
1490 * i386-gen.c (opcode_modifiers): Replace S with Load.
1491 * i386-opc.h (S): Removed.
1493 (i386_opcode_modifier): Replace s with load.
1494 * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
1495 and {evex}. Replace S with Load.
1496 * i386-tbl.h: Regenerated.
1498 2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
1500 * i386-opc.tbl: Use CpuCET on rdsspq.
1501 * i386-tbl.h: Regenerated.
1503 2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
1505 * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
1506 <vsx>: Do not use PPC_OPCODE_VSX3;
1508 2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
1510 * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
1512 2017-03-06 H.J. Lu <hongjiu.lu@intel.com>
1514 * i386-dis.c (REG_0F1E_MOD_3): New enum.
1515 (MOD_0F1E_PREFIX_1): Likewise.
1516 (MOD_0F38F5_PREFIX_2): Likewise.
1517 (MOD_0F38F6_PREFIX_0): Likewise.
1518 (RM_0F1E_MOD_3_REG_7): Likewise.
1519 (PREFIX_MOD_0_0F01_REG_5): Likewise.
1520 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
1521 (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
1522 (PREFIX_0F1E): Likewise.
1523 (PREFIX_MOD_0_0FAE_REG_5): Likewise.
1524 (PREFIX_0F38F5): Likewise.
1525 (dis386_twobyte): Use PREFIX_0F1E.
1526 (reg_table): Add REG_0F1E_MOD_3.
1527 (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
1528 PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
1529 PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
1530 PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
1531 (three_byte_table): Use PREFIX_0F38F5.
1532 (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
1533 Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
1534 (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
1535 RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
1536 PREFIX_MOD_3_0F01_REG_5_RM_2.
1537 * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
1538 (cpu_flags): Add CpuCET.
1539 * i386-opc.h (CpuCET): New enum.
1540 (CpuUnused): Commented out.
1541 (i386_cpu_flags): Add cpucet.
1542 * i386-opc.tbl: Add Intel CET instructions.
1543 * i386-init.h: Regenerated.
1544 * i386-tbl.h: Likewise.
1546 2017-03-06 Alan Modra <amodra@gmail.com>
1549 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
1550 (extract_raq, extract_ras, extract_rbx): New functions.
1551 (powerpc_operands): Use opposite corresponding insert function.
1553 (powerpc_opcodes): Apply Q_MASK to all quad insns with even
1554 register restriction.
1556 2017-02-28 Peter Bergner <bergner@vnet.ibm.com>
1558 * disassemble.c Include "safe-ctype.h".
1559 (disassemble_init_for_target): Handle s390 init.
1560 (remove_whitespace_and_extra_commas): New function.
1561 (disassembler_options_cmp): Likewise.
1562 * arm-dis.c: Include "libiberty.h".
1564 (regnames): Use long disassembler style names.
1565 Add force-thumb and no-force-thumb options.
1566 (NUM_ARM_REGNAMES): Rename from this...
1567 (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
1568 (get_arm_regname_num_options): Delete.
1569 (set_arm_regname_option): Likewise.
1570 (get_arm_regnames): Likewise.
1571 (parse_disassembler_options): Likewise.
1572 (parse_arm_disassembler_option): Rename from this...
1573 (parse_arm_disassembler_options): ...to this. Make static.
1574 Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
1575 (print_insn): Use parse_arm_disassembler_options.
1576 (disassembler_options_arm): New function.
1577 (print_arm_disassembler_options): Handle updated regnames.
1578 * ppc-dis.c: Include "libiberty.h".
1579 (ppc_opts): Add "32" and "64" entries.
1580 (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
1581 (powerpc_init_dialect): Add break to switch statement.
1582 Use new FOR_EACH_DISASSEMBLER_OPTION macro.
1583 (disassembler_options_powerpc): New function.
1584 (print_ppc_disassembler_options): Use ARRAY_SIZE.
1585 Remove printing of "32" and "64".
1586 * s390-dis.c: Include "libiberty.h".
1587 (init_flag): Remove unneeded variable.
1588 (struct s390_options_t): New structure type.
1589 (options): New structure.
1590 (init_disasm): Rename from this...
1591 (disassemble_init_s390): ...to this. Add initializations for
1592 current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
1593 (print_insn_s390): Delete call to init_disasm.
1594 (disassembler_options_s390): New function.
1595 (print_s390_disassembler_options): Print using information from
1597 * po/opcodes.pot: Regenerate.
1599 2017-02-28 Jan Beulich <jbeulich@suse.com>
1601 * i386-dis.c (PCMPESTR_Fixup): New.
1602 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
1603 (prefix_table): Use PCMPESTR_Fixup.
1604 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
1606 (vex_w_table): Delete VPCMPESTR{I,M} entries.
1607 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
1608 Split 64-bit and non-64-bit variants.
1609 * opcodes/i386-tbl.h: Re-generate.
1611 2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
1613 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
1614 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
1615 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
1616 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
1617 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
1618 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
1619 (OP_SVE_V_HSD): New macros.
1620 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
1621 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
1622 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
1623 (aarch64_opcode_table): Add new SVE instructions.
1624 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
1625 for rotation operands. Add new SVE operands.
1626 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
1627 (ins_sve_quad_index): Likewise.
1628 (ins_imm_rotate): Split into...
1629 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
1630 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
1631 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
1633 (aarch64_ins_sve_addr_ri_s4): New function.
1634 (aarch64_ins_sve_quad_index): Likewise.
1635 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
1636 * aarch64-asm-2.c: Regenerate.
1637 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
1638 (ext_sve_quad_index): Likewise.
1639 (ext_imm_rotate): Split into...
1640 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
1641 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
1642 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
1644 (aarch64_ext_sve_addr_ri_s4): New function.
1645 (aarch64_ext_sve_quad_index): Likewise.
1646 (aarch64_ext_sve_index): Allow quad indices.
1647 (do_misc_decoding): Likewise.
1648 * aarch64-dis-2.c: Regenerate.
1649 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
1650 aarch64_field_kinds.
1651 (OPD_F_OD_MASK): Widen by one bit.
1652 (OPD_F_NO_ZR): Bump accordingly.
1653 (get_operand_field_width): New function.
1654 * aarch64-opc.c (fields): Add new SVE fields.
1655 (operand_general_constraint_met_p): Handle new SVE operands.
1656 (aarch64_print_operand): Likewise.
1657 * aarch64-opc-2.c: Regenerate.
1659 2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
1661 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
1662 (aarch64_feature_compnum): ...this.
1663 (SIMD_V8_3): Replace with...
1665 (CNUM_INSN): New macro.
1666 (aarch64_opcode_table): Use it for the complex number instructions.
1668 2017-02-24 Jan Beulich <jbeulich@suse.com>
1670 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
1672 2017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
1674 Add support for associating SPARC ASIs with an architecture level.
1675 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
1676 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
1677 decoding of SPARC ASIs.
1679 2017-02-23 Jan Beulich <jbeulich@suse.com>
1681 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
1682 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
1684 2017-02-21 Jan Beulich <jbeulich@suse.com>
1686 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
1687 1 (instead of to itself). Correct typo.
1689 2017-02-14 Andrew Waterman <andrew@sifive.com>
1691 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
1694 2017-02-15 Richard Sandiford <richard.sandiford@arm.com>
1696 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
1697 (aarch64_sys_reg_supported_p): Handle them.
1699 2017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
1701 * arc-opc.c (UIMM6_20R): Define.
1702 (SIMM12_20): Use above.
1703 (SIMM12_20R): Define.
1704 (SIMM3_5_S): Use above.
1705 (UIMM7_A32_11R_S): Define.
1706 (UIMM7_9_S): Use above.
1707 (UIMM3_13R_S): Define.
1708 (SIMM11_A32_7_S): Use above.
1710 (UIMM10_A32_8_S): Use above.
1711 (UIMM8_8R_S): Define.
1713 (arc_relax_opcodes): Use all above defines.
1715 2017-02-15 Vineet Gupta <vgupta@synopsys.com>
1717 * arc-regs.h: Distinguish some of the registers different on
1718 ARC700 and HS38 cpus.
1720 2017-02-14 Alan Modra <amodra@gmail.com>
1723 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
1724 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
1726 2017-02-11 Stafford Horne <shorne@gmail.com>
1727 Alan Modra <amodra@gmail.com>
1729 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
1730 Use insn_bytes_value and insn_int_value directly instead. Don't
1731 free allocated memory until function exit.
1733 2017-02-10 Nicholas Piggin <npiggin@gmail.com>
1735 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
1737 2017-02-03 Nick Clifton <nickc@redhat.com>
1740 * aarch64-opc.c (print_register_list): Ensure that the register
1741 list index will fir into the tb buffer.
1742 (print_register_offset_address): Likewise.
1743 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
1745 2017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
1748 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
1749 instructions when the previous fetch packet ends with a 32-bit
1752 2017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
1754 * pru-opc.c: Remove vague reference to a future GDB port.
1756 2017-01-20 Nick Clifton <nickc@redhat.com>
1758 * po/ga.po: Updated Irish translation.
1760 2017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
1762 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
1764 2017-01-13 Yao Qi <yao.qi@linaro.org>
1766 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
1767 if FETCH_DATA returns 0.
1768 (m68k_scan_mask): Likewise.
1769 (print_insn_m68k): Update code to handle -1 return value.
1771 2017-01-13 Yao Qi <yao.qi@linaro.org>
1773 * m68k-dis.c (enum print_insn_arg_error): New.
1774 (NEXTBYTE): Replace -3 with
1775 PRINT_INSN_ARG_MEMORY_ERROR.
1776 (NEXTULONG): Likewise.
1777 (NEXTSINGLE): Likewise.
1778 (NEXTDOUBLE): Likewise.
1779 (NEXTDOUBLE): Likewise.
1780 (NEXTPACKED): Likewise.
1781 (FETCH_ARG): Likewise.
1782 (FETCH_DATA): Update comments.
1783 (print_insn_arg): Update comments. Replace magic numbers with
1785 (match_insn_m68k): Likewise.
1787 2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1789 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
1790 * i386-dis-evex.h (evex_table): Updated.
1791 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
1792 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
1793 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
1794 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
1795 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
1796 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
1797 * i386-init.h: Regenerate.
1798 * i386-tbl.h: Ditto.
1800 2017-01-12 Yao Qi <yao.qi@linaro.org>
1802 * msp430-dis.c (msp430_singleoperand): Return -1 if
1803 msp430dis_opcode_signed returns false.
1804 (msp430_doubleoperand): Likewise.
1805 (msp430_branchinstr): Return -1 if
1806 msp430dis_opcode_unsigned returns false.
1807 (msp430x_calla_instr): Likewise.
1808 (print_insn_msp430): Likewise.
1810 2017-01-05 Nick Clifton <nickc@redhat.com>
1813 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
1814 could not be matched.
1815 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
1818 2017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
1820 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
1821 (aarch64_opcode_table): Use RCPC_INSN.
1823 2017-01-03 Kito Cheng <kito.cheng@gmail.com>
1825 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
1827 * riscv-opcodes/all-opcodes: Likewise.
1829 2017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
1831 * riscv-dis.c (print_insn_args): Add fall through comment.
1833 2017-01-03 Nick Clifton <nickc@redhat.com>
1835 * po/sr.po: New Serbian translation.
1836 * configure.ac (ALL_LINGUAS): Add sr.
1837 * configure: Regenerate.
1839 2017-01-02 Alan Modra <amodra@gmail.com>
1841 * epiphany-desc.h: Regenerate.
1842 * epiphany-opc.h: Regenerate.
1843 * fr30-desc.h: Regenerate.
1844 * fr30-opc.h: Regenerate.
1845 * frv-desc.h: Regenerate.
1846 * frv-opc.h: Regenerate.
1847 * ip2k-desc.h: Regenerate.
1848 * ip2k-opc.h: Regenerate.
1849 * iq2000-desc.h: Regenerate.
1850 * iq2000-opc.h: Regenerate.
1851 * lm32-desc.h: Regenerate.
1852 * lm32-opc.h: Regenerate.
1853 * m32c-desc.h: Regenerate.
1854 * m32c-opc.h: Regenerate.
1855 * m32r-desc.h: Regenerate.
1856 * m32r-opc.h: Regenerate.
1857 * mep-desc.h: Regenerate.
1858 * mep-opc.h: Regenerate.
1859 * mt-desc.h: Regenerate.
1860 * mt-opc.h: Regenerate.
1861 * or1k-desc.h: Regenerate.
1862 * or1k-opc.h: Regenerate.
1863 * xc16x-desc.h: Regenerate.
1864 * xc16x-opc.h: Regenerate.
1865 * xstormy16-desc.h: Regenerate.
1866 * xstormy16-opc.h: Regenerate.
1868 2017-01-02 Alan Modra <amodra@gmail.com>
1870 Update year range in copyright notice of all files.
1872 For older changes see ChangeLog-2016
1874 Copyright (C) 2017 Free Software Foundation, Inc.
1876 Copying and distribution of this file, with or without modification,
1877 are permitted in any medium without royalty provided the copyright
1878 notice and this notice are preserved.
1884 version-control: never