opcodes/ChangeLog

   1 2016-07-25  Andrew Jenner  <andrew@codesourcery.com>
   2         Kwok Cheung Yeung  <kcy@codesourcery.com>
   3
   4         opcodes/
   5         * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
   6         'e_cmplwi' to 'e_cmpli' instead.
   7         (OPVUPRT, OPVUPRT_MASK): Define.
   8         (powerpc_opcodes): Add E200Z4 insns.
   9         (vle_opcodes): Add context save/restore insns.
  10
  11 2016-07-27  Maciej W. Rozycki  <macro@imgtec.com>
  12
  13         * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
  14         "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
  15         "j".
  16
  17 2016-07-27  Graham Markall  <graham.markall@embecosm.com>
  18
  19         * arc-nps400-tbl.h: Change block comments to GNU format.
  20         * arc-dis.c: Add new globals addrtypenames,
  21         addrtypenames_max, and addtypeunknown.
  22         (get_addrtype): New function.
  23         (print_insn_arc): Print colons and address types when
  24         required.
  25         * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
  26         define insert and extract functions for all address types.
  27         (arc_operands): Add operands for colon and all address
  28         types.
  29         * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
  30         * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
  31         insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
  32         * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
  33         * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
  34         insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
  35
  36 2016-07-21  H.J. Lu  <hongjiu.lu@intel.com>
  37
  38         * configure: Regenerated.
  39
  40 2016-07-20  Claudiu Zissulescu  <claziss@synopsys.com>
  41
  42         * arc-dis.c (skipclass): New structure.
  43         (decodelist): New variable.
  44         (is_compatible_p): New function.
  45         (new_element): Likewise.
  46         (skip_class_p): Likewise.
  47         (find_format_from_table): Use skip_class_p function.
  48         (find_format): Decode first the extension instructions.
  49         (print_insn_arc): Select either ARCEM or ARCHS based on elf
  50         e_flags.
  51         (parse_option): New function.
  52         (parse_disassembler_options): Likewise.
  53         (print_arc_disassembler_options): Likewise.
  54         (print_insn_arc): Use parse_disassembler_options function.  Proper
  55         select ARCv2 cpu variant.
  56         * disassemble.c (disassembler_usage): Add ARC disassembler
  57         options.
  58
  59 2016-07-13  Maciej W. Rozycki  <macro@imgtec.com>
  60
  61         * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
  62         annotation from the "nal" entry and reorder it beyond "bltzal".
  63
  64 2016-07-12  Jose E. Marchesi  <jose.marchesi@oracle.com>
  65
  66         * sparc-opc.c (ldtxa): New macro.
  67         (sparc_opcodes): Use the macro defined above to add entries for
  68         the LDTXA instructions.
  69         (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
  70         instruction.
  71
  72 2016-07-07  James Bowman  <james.bowman@ftdichip.com>
  73
  74         * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
  75         and "jmpc".
  76
  77 2016-07-01  Jan Beulich  <jbeulich@suse.com>
  78
  79         * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
  80         (movzb): Adjust to cover all permitted suffixes.
  81         (movzw): New.
  82         * i386-tbl.h: Re-generate.
  83
  84 2016-07-01  Jan Beulich  <jbeulich@suse.com>
  85
  86         * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
  87         (lgdt): Remove Tbyte from non-64-bit variant.
  88         (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
  89         xsaves64, xsavec64): Remove Disp16.
  90         (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
  91         Remove Disp32S from non-64-bit variants. Remove Disp16 from
  92         64-bit variants.
  93         (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
  94         vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
  95         vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
  96         64-bit variants.
  97         * i386-tbl.h: Re-generate.
  98
  99 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 100
 101         * i386-opc.tbl (xlat): Remove RepPrefixOk.
 102         * i386-tbl.h: Re-generate.
 103
 104 2016-06-30  Yao Qi  <yao.qi@linaro.org>
 105
 106         * arm-dis.c (print_insn): Fix typo in comment.
 107
 108 2016-06-28  Richard Sandiford  <richard.sandiford@arm.com>
 109
 110         * aarch64-opc.c (operand_general_constraint_met_p): Check the
 111         range of ldst_elemlist operands.
 112         (print_register_list): Use PRIi64 to print the index.
 113         (aarch64_print_operand): Likewise.
 114
 115 2016-06-25  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 116
 117         * mcore-opc.h: Remove sentinal.
 118         * mcore-dis.c (print_insn_mcore): Adjust.
 119
 120 2016-06-23  Graham Markall  <graham.markall@embecosm.com>
 121
 122         * arc-opc.c: Correct description of availability of NPS400
 123         features.
 124
 125 2016-06-22  Peter Bergner <bergner@vnet.ibm.com>
 126
 127         * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
 128         (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
 129         mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
 130         xor3>: New mnemonics.
 131         <setb>: Change to a VX form instruction.
 132         (insert_sh6): Add support for rldixor.
 133         (extract_sh6): Likewise.
 134
 135 2016-06-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 136
 137         * arc-ext.h: Wrap in extern C.
 138
 139 2016-06-21  Graham Markall  <graham.markall@embecosm.com>
 140
 141         * arc-dis.c (arc_insn_length): Add comment on instruction length.
 142         Use same method for determining instruction length on ARC700 and
 143         NPS-400.
 144         (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
 145         * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
 146         with the NPS400 subclass.
 147         * arc-opc.c: Likewise.
 148
 149 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 150
 151         * sparc-opc.c (rdasr): New macro.
 152         (wrasr): Likewise.
 153         (rdpr): Likewise.
 154         (wrpr): Likewise.
 155         (rdhpr): Likewise.
 156         (wrhpr): Likewise.
 157         (sparc_opcodes): Use the macros above to fix and expand the
 158         definition of read/write instructions from/to
 159         asr/privileged/hyperprivileged instructions.
 160         * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
 161         %hva_mask_nz.  Prefer softint_set and softint_clear over
 162         set_softint and clear_softint.
 163         (print_insn_sparc): Support %ver in Rd.
 164
 165 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 166
 167         * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
 168         architecture according to the hardware capabilities they require.
 169
 170 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 171
 172         * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
 173         (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
 174         bfd_mach_sparc_v9{c,d,e,v,m}.
 175         * sparc-opc.c (MASK_V9C): Define.
 176         (MASK_V9D): Likewise.
 177         (MASK_V9E): Likewise.
 178         (MASK_V9V): Likewise.
 179         (MASK_V9M): Likewise.
 180         (v6): Add MASK_V9{C,D,E,V,M}.
 181         (v6notlet): Likewise.
 182         (v7): Likewise.
 183         (v8): Likewise.
 184         (v9): Likewise.
 185         (v9andleon): Likewise.
 186         (v9a): Likewise.
 187         (v9b): Likewise.
 188         (v9c): Define.
 189         (v9d): Likewise.
 190         (v9e): Likewise.
 191         (v9v): Likewise.
 192         (v9m): Likewise.
 193         (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
 194
 195 2016-06-15  Nick Clifton  <nickc@redhat.com>
 196
 197         * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
 198         constants to match expected behaviour.
 199         (nds32_parse_opcode): Likewise.  Also for whitespace.
 200
 201 2016-06-15  Andrew Burgess  <andrew.burgess@embecosm.com>
 202
 203         * arc-opc.c (extract_rhv1): Extract value from insn.
 204
 205 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 206
 207         * arc-nps400-tbl.h: Add ldbit instruction.
 208         * arc-opc.c: Add flag classes required for ldbit.
 209
 210 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 211
 212         * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
 213         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
 214         support the above instructions.
 215
 216 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 217
 218         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
 219         imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
 220         csma, cbba, zncv, and hofs.
 221         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
 222         support the above instructions.
 223
 224 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 225
 226         * arc-nps400-tbl.h: Add andab and orab instructions.
 227
 228 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 229
 230         * arc-nps400-tbl.h: Add addl-like instructions.
 231
 232 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 233
 234         * arc-nps400-tbl.h: Add mxb and imxb instructions.
 235
 236 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 237
 238         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
 239         instructions.
 240
 241 2016-06-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 242
 243         * s390-dis.c (option_use_insn_len_bits_p): New file scope
 244         variable.
 245         (init_disasm): Handle new command line option "insnlength".
 246         (print_s390_disassembler_options): Mention new option in help
 247         output.
 248         (print_insn_s390): Use the encoded insn length when dumping
 249         unknown instructions.
 250
 251 2016-06-03  Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
 252
 253         * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
 254          to the address and set as symbol address for LDS/ STS immediate operands.
 255
 256 2016-06-07  Alan Modra  <amodra@gmail.com>
 257
 258         * ppc-dis.c (ppc_opts): Delete extraneous parentheses.  Default
 259         cpu for "vle" to e500.
 260         * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
 261         (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
 262         (PPCNONE): Delete, substitute throughout.
 263         (powerpc_opcodes): Remove PPCVLE from "flags".  Add to "deprecated"
 264         except for major opcode 4 and 31.
 265         (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
 266
 267 2016-06-07  Matthew Wahab  <matthew.wahab@arm.com>
 268
 269         * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
 270         ARM_EXT_RAS in relevant entries.
 271
 272 2016-06-03  Peter Bergner <bergner@vnet.ibm.com>
 273
 274         PR binutils/20196
 275         * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
 276         opcodes for E6500.
 277
 278 2016-06-03  H.J. Lu  <hongjiu.lu@intel.com>
 279
 280         PR binutis/18386
 281         * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
 282         (indir_v_mode): New.
 283         Add comments for '&'.
 284         (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
 285         (putop): Handle '&'.
 286         (intel_operand_size): Handle indir_v_mode.
 287         (OP_E_register): Likewise.
 288         * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64.  Add
 289         64-bit indirect call/jmp for AMD64.
 290         * i386-tbl.h: Regenerated
 291
 292 2016-06-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 293
 294         * arc-dis.c (struct arc_operand_iterator): New structure.
 295         (find_format_from_table): All the old content from find_format,
 296         with some minor adjustments, and parameter renaming.
 297         (find_format_long_instructions): New function.
 298         (find_format): Rewritten.
 299         (arc_insn_length): Add LSB parameter.
 300         (extract_operand_value): New function.
 301         (operand_iterator_next): New function.
 302         (print_insn_arc): Use new functions to find opcode, and iterator
 303         over operands.
 304         * arc-opc.c (insert_nps_3bit_dst_short): New function.
 305         (extract_nps_3bit_dst_short): New function.
 306         (insert_nps_3bit_src2_short): New function.
 307         (extract_nps_3bit_src2_short): New function.
 308         (insert_nps_bitop1_size): New function.
 309         (extract_nps_bitop1_size): New function.
 310         (insert_nps_bitop2_size): New function.
 311         (extract_nps_bitop2_size): New function.
 312         (insert_nps_bitop_mod4_msb): New function.
 313         (extract_nps_bitop_mod4_msb): New function.
 314         (insert_nps_bitop_mod4_lsb): New function.
 315         (extract_nps_bitop_mod4_lsb): New function.
 316         (insert_nps_bitop_dst_pos3_pos4): New function.
 317         (extract_nps_bitop_dst_pos3_pos4): New function.
 318         (insert_nps_bitop_ins_ext): New function.
 319         (extract_nps_bitop_ins_ext): New function.
 320         (arc_operands): Add new operands.
 321         (arc_long_opcodes): New global array.
 322         (arc_num_long_opcodes): New global.
 323         * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
 324
 325 2016-06-01  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 326
 327         * nds32-asm.h: Add extern "C".
 328         * sh-opc.h: Likewise.
 329
 330 2016-06-01  Graham Markall  <graham.markall@embecosm.com>
 331
 332         * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
 333         0,b,limm to the rflt instruction.
 334
 335 2016-05-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 336
 337         * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
 338         constant.
 339
 340 2016-05-29  H.J. Lu  <hongjiu.lu@intel.com>
 341
 342         PR gas/20145
 343         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
 344         CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
 345         CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
 346         CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
 347         CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
 348         * i386-init.h: Regenerated.
 349
 350 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 351
 352         PR gas/20145
 353         * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS.  Remove
 354         CpuMMX from CPU_SSE_FLAGS.  Remove AVX and AVX512 bits from
 355         CPU_ANY_SSE_FLAGS.  Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
 356         Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
 357         CpuXSAVEC.  Add CPU_AVX_FLAGS to CpuF16C.  Remove CpuMMX from
 358         CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
 359         CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
 360         Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS.   Add CPU_ANY_287_FLAGS,
 361         CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
 362         CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
 363         CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS.  Enable CpuRegMMX
 364         for MMX.  Enable CpuRegXMM for SSE, AVX and AVX512.  Enable
 365         CpuRegYMM for AVX and AVX512VL,  Enable CpuRegZMM and
 366         CpuRegMask for AVX512.
 367         (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
 368         and CpuRegMask.
 369         (set_bitfield_from_cpu_flag_init): New function.
 370         (set_bitfield): Remove const on f.  Call
 371         set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
 372         * i386-opc.h (CpuRegMMX): New.
 373         (CpuRegXMM): Likewise.
 374         (CpuRegYMM): Likewise.
 375         (CpuRegZMM): Likewise.
 376         (CpuRegMask): Likewise.
 377         (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
 378         and cpuregmask.
 379         * i386-init.h: Regenerated.
 380         * i386-tbl.h: Likewise.
 381
 382 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 383
 384         PR gas/20154
 385         * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
 386         (opcode_modifiers): Add AMD64 and Intel64.
 387         (main): Properly verify CpuMax.
 388         * i386-opc.h (CpuAMD64): Removed.
 389         (CpuIntel64): Likewise.
 390         (CpuMax): Set to CpuNo64.
 391         (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
 392         (AMD64): New.
 393         (Intel64): Likewise.
 394         (i386_opcode_modifier): Add amd64 and intel64.
 395         (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
 396         on call and jmp.
 397         * i386-init.h: Regenerated.
 398         * i386-tbl.h: Likewise.
 399
 400 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 401
 402         PR gas/20154
 403         * i386-gen.c (main): Fail if CpuMax is incorrect.
 404         * i386-opc.h (CpuMax): Set to CpuIntel64.
 405         * i386-tbl.h: Regenerated.
 406
 407 2016-05-27  Nick Clifton  <nickc@redhat.com>
 408
 409         PR target/20150
 410         * msp430-dis.c (msp430dis_read_two_bytes): New function.
 411         (msp430dis_opcode_unsigned): New function.
 412         (msp430dis_opcode_signed): New function.
 413         (msp430_singleoperand): Use the new opcode reading functions.
 414         Only disassenmble bytes if they were successfully read.
 415         (msp430_doubleoperand): Likewise.
 416         (msp430_branchinstr): Likewise.
 417         (msp430x_callx_instr): Likewise.
 418         (print_insn_msp430): Check that it is safe to read bytes before
 419         attempting disassembly.  Use the new opcode reading functions.
 420
 421 2016-05-26  Peter Bergner <bergner@vnet.ibm.com>
 422
 423         * ppc-opc.c (CY): New define.  Document it.
 424         (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
 425
 426 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 427
 428         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
 429         CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
 430         and CPU_AVX512VBMI_FLAGS.  Add CpuAVX512DQ, CpuAVX512BW,
 431         CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
 432         CPU_ANY_AVX_FLAGS.
 433         * i386-init.h: Regenerated.
 434
 435 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 436
 437         PR gas/20141
 438         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
 439         CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
 440         * i386-init.h: Regenerated.
 441
 442 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 443
 444         * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
 445         CPU_ANY_X87_FLAGS.  Add CPU_ANY_MMX_FLAGS.
 446         * i386-init.h: Regenerated.
 447
 448 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
 449
 450         * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
 451         information.
 452         (print_insn_arc): Set insn_type information.
 453         * arc-opc.c (C_CC): Add F_CLASS_COND.
 454         * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
 455         (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
 456         (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
 457         (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
 458         (brne, brne_s, jeq_s, jne_s): Likewise.
 459
 460 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
 461
 462         * arc-tbl.h (neg): New instruction variant.
 463
 464 2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>
 465
 466         * arc-dis.c (find_format, find_format, get_auxreg)
 467         (print_insn_arc): Changed.
 468         * arc-ext.h (INSERT_XOP): Likewise.
 469
 470 2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 471
 472         * tic54x-dis.c (sprint_mmr): Adjust.
 473         * tic54x-opc.c: Likewise.
 474
 475 2016-05-19  Alan Modra  <amodra@gmail.com>
 476
 477         * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
 478
 479 2016-05-19  Alan Modra  <amodra@gmail.com>
 480
 481         * ppc-opc.c: Formatting.
 482         (NSISIGNOPT): Define.
 483         (powerpc_opcodes <subis>): Use NSISIGNOPT.
 484
 485 2016-05-18  Maciej W. Rozycki  <macro@imgtec.com>
 486
 487         * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
 488         replacing references to `micromips_ase' throughout.
 489         (_print_insn_mips): Don't use file-level microMIPS annotation to
 490         determine the disassembly mode with the symbol table.
 491
 492 2016-05-13  Peter Bergner <bergner@vnet.ibm.com>
 493
 494         * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
 495
 496 2016-05-11  Andrew Bennett  <andrew.bennett@imgtec.com>
 497
 498         * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
 499         mips64r6.
 500         * mips-opc.c (D34): New macro.
 501         (mips_builtin_opcodes): Define bposge32c for DSPr3.
 502
 503 2016-05-10  Alexander Fomin  <alexander.fomin@intel.com>
 504
 505         * i386-dis.c (prefix_table): Add RDPID instruction.
 506         * i386-gen.c (cpu_flag_init): Add RDPID flag.
 507         (cpu_flags): Add RDPID bitfield.
 508         * i386-opc.h (enum): Add RDPID element.
 509         (i386_cpu_flags): Add RDPID field.
 510         * i386-opc.tbl: Add RDPID instruction.
 511         * i386-init.h: Regenerate.
 512         * i386-tbl.h: Regenerate.
 513
 514 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 515
 516         * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
 517         branch type of a symbol.
 518         (print_insn): Likewise.
 519
 520 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 521
 522         * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
 523         Mainline Security Extensions instructions.
 524         (thumb_opcodes): Add entries for narrow ARMv8-M Security
 525         Extensions instructions.
 526         (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
 527         instructions.
 528         (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
 529         special registers.
 530
 531 2016-05-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
 532
 533         * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
 534
 535 2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>
 536
 537         * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
 538         (arcExtMap_genOpcode): Likewise.
 539         * arc-opc.c (arg_32bit_rc): Define new variable.
 540         (arg_32bit_u6): Likewise.
 541         (arg_32bit_limm): Likewise.
 542
 543 2016-05-03  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 544
 545         * aarch64-gen.c (VERIFIER): Define.
 546         * aarch64-opc.c (VERIFIER): Define.
 547         (verify_ldpsw): Use static linkage.
 548         * aarch64-opc.h (verify_ldpsw): Remove.
 549         * aarch64-tbl.h: Use VERIFIER for verifiers.
 550
 551 2016-04-28  Nick Clifton  <nickc@redhat.com>
 552
 553         PR target/19722
 554         * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
 555         * aarch64-opc.c (verify_ldpsw): New function.
 556         * aarch64-opc.h (verify_ldpsw): New prototype.
 557         * aarch64-tbl.h: Add initialiser for verifier field.
 558         (LDPSW): Set verifier to verify_ldpsw.
 559
 560 2016-04-23  H.J. Lu  <hongjiu.lu@intel.com>
 561
 562         PR binutils/19983
 563         PR binutils/19984
 564         * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
 565         smaller than address size.
 566
 567 2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 568
 569         * alpha-dis.c: Regenerate.
 570         * crx-dis.c: Likewise.
 571         * disassemble.c: Likewise.
 572         * epiphany-opc.c: Likewise.
 573         * fr30-opc.c: Likewise.
 574         * frv-opc.c: Likewise.
 575         * ip2k-opc.c: Likewise.
 576         * iq2000-opc.c: Likewise.
 577         * lm32-opc.c: Likewise.
 578         * lm32-opinst.c: Likewise.
 579         * m32c-opc.c: Likewise.
 580         * m32r-opc.c: Likewise.
 581         * m32r-opinst.c: Likewise.
 582         * mep-opc.c: Likewise.
 583         * mt-opc.c: Likewise.
 584         * or1k-opc.c: Likewise.
 585         * or1k-opinst.c: Likewise.
 586         * tic80-opc.c: Likewise.
 587         * xc16x-opc.c: Likewise.
 588         * xstormy16-opc.c: Likewise.
 589
 590 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
 591
 592         * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
 593         fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
 594         calcsd, and calcxd instructions.
 595         * arc-opc.c (insert_nps_bitop_size): Delete.
 596         (extract_nps_bitop_size): Delete.
 597         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
 598         (extract_nps_qcmp_m3): Define.
 599         (extract_nps_qcmp_m2): Define.
 600         (extract_nps_qcmp_m1): Define.
 601         (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
 602         (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
 603         (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
 604         NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
 605         NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
 606         NPS_QCMP_M3.
 607
 608 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
 609
 610         * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
 611
 612 2016-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 613
 614         * Makefile.in: Regenerated with automake 1.11.6.
 615         * aclocal.m4: Likewise.
 616
 617 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
 618
 619         * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
 620         instructions.
 621         * arc-opc.c (insert_nps_cmem_uimm16): New function.
 622         (extract_nps_cmem_uimm16): New function.
 623         (arc_operands): Add NPS_XLDST_UIMM16 operand.
 624
 625 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
 626
 627         * arc-dis.c (arc_insn_length): New function.
 628         (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
 629         (find_format): Change insnLen parameter to unsigned.
 630
 631 2016-04-13  Nick Clifton  <nickc@redhat.com>
 632
 633         PR target/19937
 634         * v850-opc.c (v850_opcodes): Correct masks for long versions of
 635         the LD.B and LD.BU instructions.
 636
 637 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 638
 639         * arc-dis.c (find_format): Check for extension flags.
 640         (print_flags): New function.
 641         (print_insn_arc): Update for .extCondCode, .extCoreRegister and
 642         .extAuxRegister.
 643         * arc-ext.c (arcExtMap_coreRegName): Use
 644         LAST_EXTENSION_CORE_REGISTER.
 645         (arcExtMap_coreReadWrite): Likewise.
 646         (dump_ARC_extmap): Update printing.
 647         * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
 648         (arc_aux_regs): Add cpu field.
 649         * arc-regs.h: Add cpu field, lower case name aux registers.
 650
 651 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 652
 653         * arc-tbl.h: Add rtsc, sleep with no arguments.
 654
 655 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 656
 657         * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
 658         Initialize.
 659         (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
 660         (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
 661         (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
 662         (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
 663         (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
 664         (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
 665         (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
 666         (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
 667         (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
 668         (arc_opcode arc_opcodes): Null terminate the array.
 669         (arc_num_opcodes): Remove.
 670         * arc-ext.h (INSERT_XOP): Define.
 671         (extInstruction_t): Likewise.
 672         (arcExtMap_instName): Delete.
 673         (arcExtMap_insn): New function.
 674         (arcExtMap_genOpcode): Likewise.
 675         * arc-ext.c (ExtInstruction): Remove.
 676         (create_map): Zero initialize instruction fields.
 677         (arcExtMap_instName): Remove.
 678         (arcExtMap_insn): New function.
 679         (dump_ARC_extmap): More info while debuging.
 680         (arcExtMap_genOpcode): New function.
 681         * arc-dis.c (find_format): New function.
 682         (print_insn_arc): Use find_format.
 683         (arc_get_disassembler): Enable dump_ARC_extmap only when
 684         debugging.
 685
 686 2016-04-11  Maciej W. Rozycki  <macro@imgtec.com>
 687
 688         * mips-dis.c (print_mips16_insn_arg): Mask unused extended
 689         instruction bits out.
 690
 691 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
 692
 693         * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
 694         * arc-opc.c (arc_flag_operands): Add new flags.
 695         (arc_flag_classes): Add new classes.
 696
 697 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
 698
 699         * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
 700
 701 2016-04-05  Andrew Burgess  <andrew.burgess@embecosm.com>
 702
 703         * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
 704         encode1, rflt, crc16, and crc32 instructions.
 705         * arc-opc.c (arc_flag_operands): Add F_NPS_R.
 706         (arc_flag_classes): Add C_NPS_R.
 707         (insert_nps_bitop_size_2b): New function.
 708         (extract_nps_bitop_size_2b): Likewise.
 709         (insert_nps_bitop_uimm8): Likewise.
 710         (extract_nps_bitop_uimm8): Likewise.
 711         (arc_operands): Add new operand entries.
 712
 713 2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>
 714
 715         * arc-regs.h: Add a new subclass field.  Add double assist
 716         accumulator register values.
 717         * arc-tbl.h: Use DPA subclass to mark the double assist
 718         instructions.  Use DPX/SPX subclas to mark the FPX instructions.
 719         * arc-opc.c (RSP): Define instead of SP.
 720         (arc_aux_regs): Add the subclass field.
 721
 722 2016-04-05  Jiong Wang  <jiong.wang@arm.com>
 723
 724         * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
 725
 726 2016-03-31  Andrew Burgess  <andrew.burgess@embecosm.com>
 727
 728         * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
 729         NPS_R_SRC1.
 730
 731 2016-03-30  Andrew Burgess  <andrew.burgess@embecosm.com>
 732
 733         * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
 734         issues.  No functional changes.
 735
 736 2016-03-30  Claudiu Zissulescu  <claziss@synopsys.com>
 737
 738         * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
 739         (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
 740         (RTT): Remove duplicate.
 741         (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
 742         (PCT_CONFIG*): Remove.
 743         (D1L, D1H, D2H, D2L): Define.
 744
 745 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
 746
 747         * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
 748
 749 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
 750
 751         * arc-tbl.h (invld07): Remove.
 752         * arc-ext-tbl.h: New file.
 753         * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
 754         * arc-opc.c (arc_opcodes): Add ext-tbl include.
 755
 756 2016-03-24  Jan Kratochvil  <jan.kratochvil@redhat.com>
 757
 758         Fix -Wstack-usage warnings.
 759         * aarch64-dis.c (print_operands): Substitute size.
 760         * aarch64-opc.c (print_register_offset_address): Substitute tblen.
 761
 762 2016-03-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
 763
 764         * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
 765         to get a proper diagnostic when an invalid ASR register is used.
 766
 767 2016-03-22  Nick Clifton  <nickc@redhat.com>
 768
 769         * configure: Regenerate.
 770
 771 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 772
 773         * arc-nps400-tbl.h: New file.
 774         * arc-opc.c: Add top level comment.
 775         (insert_nps_3bit_dst): New function.
 776         (extract_nps_3bit_dst): New function.
 777         (insert_nps_3bit_src2): New function.
 778         (extract_nps_3bit_src2): New function.
 779         (insert_nps_bitop_size): New function.
 780         (extract_nps_bitop_size): New function.
 781         (arc_flag_operands): Add nps400 entries.
 782         (arc_flag_classes): Add nps400 entries.
 783         (arc_operands): Add nps400 entries.
 784         (arc_opcodes): Add nps400 include.
 785
 786 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 787
 788         * arc-opc.c (arc_flag_classes): Convert all flag classes to use
 789         the new class enum values.
 790
 791 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 792
 793         * arc-dis.c (print_insn_arc): Handle nps400.
 794
 795 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 796
 797         * arc-opc.c (BASE): Delete.
 798
 799 2016-03-18  Nick Clifton  <nickc@redhat.com>
 800
 801         PR target/19721
 802         * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
 803         of MOV insn that aliases an ORR insn.
 804
 805 2016-03-16  Jiong Wang  <jiong.wang@arm.com>
 806
 807         * arm-dis.c (neon_opcodes): Support new FP16 instructions.
 808
 809 2016-03-07  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 810
 811         * mcore-opc.h: Add const qualifiers.
 812         * microblaze-opc.h (struct op_code_struct): Likewise.
 813         * sh-opc.h: Likewise.
 814         * tic4x-dis.c (tic4x_print_indirect): Likewise.
 815         (tic4x_print_op): Likewise.
 816
 817 2016-03-02  Alan Modra  <amodra@gmail.com>
 818
 819         * or1k-desc.h: Regenerate.
 820         * fr30-ibld.c: Regenerate.
 821         * rl78-decode.c: Regenerate.
 822
 823 2016-03-01  Nick Clifton  <nickc@redhat.com>
 824
 825         PR target/19747
 826         * rl78-dis.c (print_insn_rl78_common): Fix typo.
 827
 828 2016-02-24  Renlin Li  <renlin.li@arm.com>
 829
 830         * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
 831         (print_insn_coprocessor): Support fp16 instructions.
 832
 833 2016-02-24  Renlin Li  <renlin.li@arm.com>
 834
 835         * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
 836         vminnm, vrint(mpna).
 837
 838 2016-02-24  Renlin Li  <renlin.li@arm.com>
 839
 840         * arm-dis.c (print_insn_coprocessor): Check co-processor number for
 841         cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
 842
 843 2016-02-15  H.J. Lu  <hongjiu.lu@intel.com>
 844
 845         * i386-dis.c (print_insn): Parenthesize expression to prevent
 846         truncated addresses.
 847         (OP_J): Likewise.
 848
 849 2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
 850             Janek van Oirschot  <jvanoirs@synopsys.com>
 851
 852         * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
 853         variable.
 854
 855 2016-02-04  Nick Clifton  <nickc@redhat.com>
 856
 857         PR target/19561
 858         * msp430-dis.c (print_insn_msp430): Add a special case for
 859         decoding an RRC instruction with the ZC bit set in the extension
 860         word.
 861
 862 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 863
 864         * cgen-ibld.in (insert_normal): Rework calculation of shift.
 865         * epiphany-ibld.c: Regenerate.
 866         * fr30-ibld.c: Regenerate.
 867         * frv-ibld.c: Regenerate.
 868         * ip2k-ibld.c: Regenerate.
 869         * iq2000-ibld.c: Regenerate.
 870         * lm32-ibld.c: Regenerate.
 871         * m32c-ibld.c: Regenerate.
 872         * m32r-ibld.c: Regenerate.
 873         * mep-ibld.c: Regenerate.
 874         * mt-ibld.c: Regenerate.
 875         * or1k-ibld.c: Regenerate.
 876         * xc16x-ibld.c: Regenerate.
 877         * xstormy16-ibld.c: Regenerate.
 878
 879 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 880
 881         * epiphany-dis.c: Regenerated from latest cpu files.
 882
 883 2016-02-01  Michael McConville  <mmcco@mykolab.com>
 884
 885         * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
 886         test bit.
 887
 888 2016-01-25  Renlin Li  <renlin.li@arm.com>
 889
 890         * arm-dis.c (mapping_symbol_for_insn): New function.
 891         (find_ifthen_state): Call mapping_symbol_for_insn().
 892
 893 2016-01-20  Matthew Wahab  <matthew.wahab@arm.com>
 894
 895         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
 896         of MSR UAO immediate operand.
 897
 898 2016-01-18  Maciej W. Rozycki  <macro@imgtec.com>
 899
 900         * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
 901         instruction support.
 902
 903 2016-01-17  Alan Modra  <amodra@gmail.com>
 904
 905         * configure: Regenerate.
 906
 907 2016-01-14  Nick Clifton  <nickc@redhat.com>
 908
 909         * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
 910         instructions that can support stack pointer operations.
 911         * rl78-decode.c: Regenerate.
 912         * rl78-dis.c: Fix display of stack pointer in MOVW based
 913         instructions.
 914
 915 2016-01-14  Matthew Wahab  <matthew.wahab@arm.com>
 916
 917         * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
 918         testing for RAS support.  Add checks for erxfr_el1, erxctlr_el1,
 919         erxtatus_el1 and erxaddr_el1.
 920
 921 2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>
 922
 923         * arm-dis.c (arm_opcodes): Add "esb".
 924         (thumb_opcodes): Likewise.
 925
 926 2016-01-11  Peter Bergner <bergner@vnet.ibm.com>
 927
 928         * ppc-opc.c <xscmpnedp>: Delete.
 929         <xvcmpnedp>: Likewise.
 930         <xvcmpnedp.>: Likewise.
 931         <xvcmpnesp>: Likewise.
 932         <xvcmpnesp.>: Likewise.
 933
 934 2016-01-08  Andreas Schwab  <schwab@linux-m68k.org>
 935
 936         PR gas/13050
 937         * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
 938         addition to ISA_A.
 939
 940 2016-01-01  Alan Modra  <amodra@gmail.com>
 941
 942         Update year range in copyright notice of all files.
 943
 944 For older changes see ChangeLog-2015
 945 \f
 946 Copyright (C) 2016 Free Software Foundation, Inc.
 947
 948 Copying and distribution of this file, with or without modification,
 949 are permitted in any medium without royalty provided the copyright
 950 notice and this notice are preserved.
 951
 952 Local Variables:
 953 mode: change-log
 954 left-margin: 8
 955 fill-column: 74
 956 version-control: never
 957 End: