1 2022-03-16 Simon Marchi <simon.marchi@efficios.com>
3 * configure.ac: Handle bfd_amdgcn_arch.
4 * configure: Re-generate.
6 2022-03-06 Sagar Patel <sagarmp@cs.unc.edu>
7 Maciej W. Rozycki <macro@orcam.me.uk>
9 * mips-opc.c (mips_builtin_opcodes): Fix INSN2_ALIAS annotation
10 for "bal", "beqz", "beqzl", "bnez" and "bnezl" instructions.
11 * micromips-opc.c (micromips_opcodes): Likewise for "beqz" and
14 2022-02-17 Nick Clifton <nickc@redhat.com>
16 * po/sr.po: Updated Serbian translation.
18 2022-02-14 Sergei Trofimovich <siarheit@google.com>
20 * microblaze-opcm.h: Renamed 'fsqrt' to 'microblaze_fsqrt'.
21 * microblaze-opc.h: Follow 'fsqrt' rename.
23 2022-01-24 Nick Clifton <nickc@redhat.com>
25 * po/ro.po: Updated Romanian translation.
26 * po/uk.po: Updated Ukranian translation.
28 2022-01-22 Nick Clifton <nickc@redhat.com>
30 * configure: Regenerate.
31 * po/opcodes.pot: Regenerate.
33 2022-01-22 Nick Clifton <nickc@redhat.com>
35 * 2.38 release branch created.
37 2022-01-17 Nick Clifton <nickc@redhat.com>
39 * Makefile.in: Regenerate.
40 * po/opcodes.pot: Regenerate.
42 2021-12-02 Marcus Nilsson <brainbomb@gmail.com>
44 * avr-dis.c (avr_operand); Pass in disassemble_info and fill
45 in insn_type on branching instructions.
47 2021-11-25 Andrew Burgess <aburgess@redhat.com>
48 Simon Cook <simon.cook@embecosm.com>
50 * riscv-dis.c (enum riscv_option_arg_t): New enum typedef.
51 (riscv_options): New static global.
52 (disassembler_options_riscv): New function.
53 (print_riscv_disassembler_options): Rewrite to use
54 disassembler_options_riscv.
56 2021-11-25 Nick Clifton <nickc@redhat.com>
59 * aarch64-asm.c: Replace assert(0) with real code.
60 * aarch64-dis.c: Likewise.
61 * aarch64-opc.c: Likewise.
63 2021-11-25 Nick Clifton <nickc@redhat.com>
65 * po/fr.po; Updated French translation.
67 2021-10-27 Maciej W. Rozycki <macro@embecosm.com>
69 * Makefile.am: Remove obsolete comment.
70 * configure.ac: Refer `libbfd.la' to link shared BFD library
72 * Makefile.in: Regenerate.
73 * configure: Regenerate.
75 2021-09-27 Nick Alcock <nick.alcock@oracle.com>
77 * configure: Regenerate.
79 2021-09-25 Peter Bergner <bergner@linux.ibm.com>
81 * ppc-opc.c (powerpc_opcodes) <mfppr, mfppr32, mtppr, mtppr32>: Enable
84 2021-09-20 Andrew Burgess <andrew.burgess@embecosm.com>
86 * riscv-dis.c (riscv_disassemble_insn): Print a .%dbyte opcode
87 before an unknown instruction, '%d' is replaced with the
90 2021-09-02 Nick Clifton <nickc@redhat.com>
93 * v850-opc.c (D16): Use BFD_RELOC_V850_LO16_SPLIT_OFFSET in place
96 2021-08-17 Shahab Vahedi <shahab@synopsys.com>
98 * arc-regs.h (DEF): Fix the register numbers.
100 2021-08-10 Nick Clifton <nickc@redhat.com>
102 * po/sr.po: Updated Serbian translation.
104 2021-07-26 Chenghua Xu <xuchenghua@loongson.cn>
106 * mips-dis.c (mips_arch_choices): Correct gs264e bfd_mach.
108 2021-06-07 Andreas Krebbel <krebbel@linux.ibm.com>
110 * s390-opc.txt: Add qpaci.
112 2021-07-03 Nick Clifton <nickc@redhat.com>
114 * configure: Regenerate.
115 * po/opcodes.pot: Regenerate.
117 2021-07-03 Nick Clifton <nickc@redhat.com>
119 * 2.37 release branch created.
121 2021-07-02 Alan Modra <amodra@gmail.com>
123 * nds32-dis.c (nds32_find_reg_keyword): Constify arg and return.
124 (nds32_parse_audio_ext, nds32_parse_opcode): Constify psys_reg.
125 (nds32_field_table, nds32_opcode_table, nds32_keyword_table),
126 (nds32_opcodes, nds32_operand_fields, nds32_keywords),
127 (nds32_keyword_gpr): Move declarations to..
128 * nds32-asm.h: ..here, constifying to match definitions.
130 2021-07-01 Mike Frysinger <vapier@gentoo.org>
132 * Makefile.am (GUILE): New variable.
133 (CGEN): Use $(GUILE).
134 * Makefile.in: Regenerate.
136 2021-07-01 Mike Frysinger <vapier@gentoo.org>
138 * mep-asm.c (macros): Mark static & const.
139 (lookup_macro): Change return & m to const.
140 (expand_macro): Change mac to const.
141 (expand_string): Change pmacro to const.
143 2021-07-01 Mike Frysinger <vapier@gentoo.org>
145 * nds32-asm.c (operand_fields): Rename to ...
146 (nds32_operand_fields): ... this.
147 (keyword_gpr): Rename to ...
148 (nds32_keyword_gpr): ... this.
149 (keyword_usr, keyword_dxr, keyword_sr, keyword_cp, keyword_cpr,
150 keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm,
151 keyword_dpref_st, keyword_cctl_lv, keyword_standby_st,
152 keyword_msync_st, keyword_im5_i, keyword_im5_m, keyword_accumulator,
153 keyword_aridx, keyword_aridx2, keyword_aridxi, keyword_aridxi_mx):
155 (keywords): Rename to ...
156 (nds32_keywords): ... this.
157 * nds32-dis.c: Rename operand_fields to nds32_operand_fields,
158 keywords to nds32_keywords, and keyword_gpr to nds32_keyword_gpr.
160 2021-07-01 Mike Frysinger <vapier@gentoo.org>
162 * z80-dis.c (opc_ed): Make const.
163 (pref_ed): Make p const.
165 2021-07-01 Mike Frysinger <vapier@gentoo.org>
167 * microblaze-dis.c (get_field_special): Make op const.
168 (read_insn_microblaze): Make opr & op const. Rename opcodes to
170 (print_insn_microblaze): Make op & pop const.
171 (get_insn_microblaze): Make op const. Rename opcodes to
173 (microblaze_get_target_address): Likewise.
174 * microblaze-opc.h (struct op_code_struct): Make const.
175 Rename opcodes to microblaze_opcodes.
177 2021-07-01 Mike Frysinger <vapier@gentoo.org>
179 * aarch64-gen.c (aarch64_opcode_table): Add const.
180 * aarch64-tbl.h (aarch64_opcode_table): Likewise.
182 2021-06-22 Andrew Burgess <andrew.burgess@embecosm.com>
184 * cgen-dis.c (count_decodable_bits): Use __builtin_popcount when
187 2021-06-22 Alan Modra <amodra@gmail.com>
189 * pj-dis.c (print_insn_pj): Don't print trailing tab. Do
190 print separator for pcrel insns.
192 2021-06-19 Alan Modra <amodra@gmail.com>
194 * vax-dis.c (print_insn_vax): Avoid pointer overflow.
196 2021-06-19 Alan Modra <amodra@gmail.com>
198 * tic30-dis.c (get_register_operand): Don't ask strncpy to fill
201 2021-06-17 Alan Modra <amodra@gmail.com>
203 * ppc-opc.c (powerpc_opcodes): Move cell db*cyc to proper location
206 2021-06-03 Alan Modra <amodra@gmail.com>
209 * mcore-dis.c (print_insn_mcore): Correct loopt disassembly.
210 Use unsigned int for inst.
212 2021-06-02 Shahab Vahedi <shahab@synopsys.com>
214 * arc-dis.c (arc_option_arg_t): New enumeration.
215 (arc_options): New variable.
216 (disassembler_options_arc): New function.
217 (print_arc_disassembler_options): Reimplement in terms of
218 "disassembler_options_arc".
220 2021-05-29 Alan Modra <amodra@gmail.com>
222 * ppc-dis.c (lookup_powerpc): Test deprecated field when -Many.
223 Don't special case PPC_OPCODE_RAW.
224 (lookup_prefix): Likewise.
225 (lookup_vle, lookup_spe2): Similarly. Add dialect parameter and..
226 (print_insn_powerpc): ..update caller.
227 * ppc-opc.c (EXT): Define.
228 (powerpc_opcodes): Mark extended mnemonics with EXT.
229 (prefix_opcodes, vle_opcodes): Likewise.
230 (XISEL, XISEL_MASK): Add cr field and simplify.
231 (powerpc_opcodes): Use XISEL with extended isel mnemonics and sort
232 all isel variants to where the base mnemonic belongs. Sort dstt,
235 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
237 * mips-opc.c (mips_builtin_opcodes): Reorder legacy COP0, COP2,
238 COP3 opcode instructions.
240 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
242 * mips-opc.c (mips_builtin_opcodes): Update exclusion list for
243 "ldc2", "ldc3", "lwc0", "lwc2", "lwc3", "sdc2", "sdc3", "swc0",
244 "swc2", "swc3", "cfc0", "ctc0", "bc2f", "bc2fl", "bc2t",
245 "bc2tl", "cfc2", "ctc2", "dmfc2", "dmtc2", "mfc2", "mtc2",
246 "bc3f", "bc3fl", "bc3t", "bc3tl", "cfc3", "ctc3", "mfc3",
247 "mtc3", "bc0f", "bc0fl", "bc0t", "bc0tl", "rfe", "c2", "c3",
248 "cop2", and "cop3" entries.
250 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
252 * mips-opc.c (mips_builtin_opcodes): Remove "dmfc3" and "dmtc3"
253 entries and associated comments.
255 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
257 * mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead
260 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
262 * mips-dis.c (mips_cp1_names_mips): New variable.
263 (mips_arch_choices): Use it rather than `mips_cp1_names_numeric'
264 for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120",
265 "r4300", "r4400", "r4600", "r4650", "r5000", "vr5400", "vr5500",
266 "r5900", "r6000", "rm7000", "rm9000", "r8000", "r10000",
267 "r12000", "r14000", "r16000", "mips5", "loongson2e", and
270 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
272 * mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register
273 handling code over to...
274 <OP_REG_CONTROL>: ... this new case.
275 * mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases.
276 (mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2",
277 "cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries
278 replacing the `G' operand code with `g'. Update "cftc1" and
279 "cftc2" entries replacing the `E' operand code with `y'.
280 * micromips-opc.c (decode_micromips_operand) <'g'>: New case.
281 (micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2"
282 entries replacing the `G' operand code with `g'.
284 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
286 * mips-dis.c (mips_cp0_names_r3900): New variable.
287 (mips_arch_choices): Use it rather than `mips_cp0_names_numeric'
290 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
292 * mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2",
293 and "mtthc2" to using the `G' rather than `g' operand code for
294 the coprocessor control register referred.
296 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
298 * micromips-opc.c (micromips_opcodes): Swap the two "dmtc1"
299 entries with each other.
301 2021-05-27 Peter Bergner <bergner@linux.ibm.com>
303 * ppc-opc.c (powerpc_opcodes) <xxmr, xxlnot>: New extended mnemonics.
305 2021-05-25 Alan Modra <amodra@gmail.com>
307 * cris-desc.c: Regenerate.
308 * cris-desc.h: Regenerate.
309 * cris-opc.h: Regenerate.
310 * po/POTFILES.in: Regenerate.
312 2021-05-24 Mike Frysinger <vapier@gentoo.org>
314 * Makefile.am (HFILES): Add cris-desc.h & cris-opc.h.
315 (TARGET_LIBOPCODES_CFILES): Add cris-desc.c.
316 (CGEN_CPUS): Add cris.
318 (stamp-cris): New rule.
319 * cgen.sh: Handle desc action.
320 * configure.ac (bfd_cris_arch): Add cris-desc.lo.
321 * Makefile.in, configure: Regenerate.
323 2021-05-18 Job Noorman <mtvec@pm.me>
326 * riscv-dis.c (riscv_get_disassembler): Get elf attributes only for
329 2021-05-17 Alex Coplan <alex.coplan@arm.com>
331 * arm-dis.c (mve_opcodes): Fix disassembly of
332 MVE_VMOV2_GP_TO_VEC_LANE when idx == 1.
333 (is_mve_encoding_conflict): MVE vector loads should not match
335 (is_mve_unpredictable): It's not unpredictable to use the same
336 source register twice (for MVE_VMOV2_GP_TO_VEC_LANE).
338 2021-05-11 Nick Clifton <nickc@redhat.com>
341 * tic30-dis.c (print_insn_tic30): Prevent attempts to read beyond
342 the end of the code buffer.
344 2021-05-06 Stafford Horne <shorne@gmail.com>
347 * or1k-asm.c: Regenerate.
349 2021-05-01 Max Filippov <jcmvbkbc@gmail.com>
351 * xtensa-dis.c (print_insn_xtensa): Fill in info->insn_type and
352 info->insn_info_valid.
354 2021-04-26 Jan Beulich <jbeulich@suse.com>
356 * i386-opc.tbl (lea): Add Optimize.
357 * opcodes/i386-tbl.h: Re-generate.
359 2020-04-23 Max Filippov <jcmvbkbc@gmail.com>
361 * xtensa-dis.c (print_xtensa_operand): For PC-relative operand
362 of l32r fetch and display referenced literal value.
364 2021-04-23 Max Filippov <jcmvbkbc@gmail.com>
366 * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk
367 to 4 for literal disassembly.
369 2021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
371 * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support
372 for TLBI instruction.
374 2021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
376 * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
379 2021-04-19 Jan Beulich <jbeulich@suse.com>
381 * aarch64-asm.c (encode_asimd_fcvt): Add initializer for
383 (convert_mov_to_movewide): Add initializer for "value".
385 2021-04-16 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
387 * aarch64-opc.c: Add RME system registers.
389 2021-04-16 Lifang Xia <lifang_xia@c-sky.com>
391 * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress
392 "addi d,CV,z" to "c.mv d,CV".
394 2021-04-12 Alan Modra <amodra@gmail.com>
396 * configure.ac (--enable-checking): Add support.
397 * config.in: Regenerate.
398 * configure: Regenerate.
400 2021-04-09 Tejas Belagod <tejas.belagod@arm.com>
402 * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
403 LD64/ST64 instructions to lse_atomic instead of ldstexcl.
405 2021-04-09 Alan Modra <amodra@gmail.com>
407 * ppc-dis.c (struct dis_private): Add "special".
408 (POWERPC_DIALECT): Delete. Replace uses with..
409 (private_data): ..this. New inline function.
410 (disassemble_init_powerpc): Init "special" names.
411 (skip_optional_operands): Add is_pcrel arg, set when detecting R
412 field of prefix instructions.
413 (bsearch_reloc, print_got_plt): New functions.
414 (print_insn_powerpc): For pcrel instructions, print target address
415 and symbol if known, and decode plt and got loads too.
417 2021-04-08 Alan Modra <amodra@gmail.com>
420 * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
422 2021-04-08 Alan Modra <amodra@gmail.com>
425 * ppc-opc.c (DCBT_EO): Move earlier.
426 (insert_thct, extract_thct, insert_thds, extract_thds): New functions.
427 (powerpc_operands): Add THCT and THDS entries.
428 (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
430 2021-04-06 Alan Modra <amodra@gmail.com>
432 * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
433 * s12z-dis.c (decode_possible_symbol): Use symbol returned from
434 symbol_at_address_func.
436 2021-04-05 Alan Modra <amodra@gmail.com>
438 * configure.ac: Don't check for limits.h, string.h, strings.h or
440 (AC_ISC_POSIX): Don't invoke.
441 * sysdep.h: Include stdlib.h and string.h unconditionally.
442 * i386-opc.h: Include limits.h unconditionally.
443 * wasm32-dis.c: Likewise.
444 * cgen-opc.c: Don't include alloca-conf.h.
445 * config.in: Regenerate.
446 * configure: Regenerate.
448 2021-04-01 Martin Liska <mliska@suse.cz>
450 * arm-dis.c (strneq): Remove strneq and use startswith.
451 * cr16-dis.c (print_insn_cr16): Likewise.
452 * score-dis.c (streq): Likewise.
454 * score7-dis.c (strneq): Likewise.
456 2021-04-01 Alan Modra <amodra@gmail.com>
459 * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
461 2021-03-31 Alan Modra <amodra@gmail.com>
463 * sysdep.h (POISON_BFD_BOOLEAN): Define.
464 * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
465 * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
466 * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
467 * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
468 * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
469 * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
470 * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
471 * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
472 * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
473 * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
474 * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
475 * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
476 * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
477 and TRUE with true throughout.
479 2021-03-31 Alan Modra <amodra@gmail.com>
481 * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
482 * aarch64-dis.h: Likewise.
483 * aarch64-opc.c: Likewise.
484 * avr-dis.c: Likewise.
485 * csky-dis.c: Likewise.
486 * nds32-asm.c: Likewise.
487 * nds32-dis.c: Likewise.
488 * nfp-dis.c: Likewise.
489 * riscv-dis.c: Likewise.
490 * s12z-dis.c: Likewise.
491 * wasm32-dis.c: Likewise.
493 2021-03-30 Jan Beulich <jbeulich@suse.com>
495 * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
496 (i386_seg_prefixes): New.
497 * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
498 (i386_seg_prefixes): Declare.
500 2021-03-30 Jan Beulich <jbeulich@suse.com>
502 * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
504 2021-03-30 Jan Beulich <jbeulich@suse.com>
506 * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
507 * i386-reg.tbl (st): Move down.
508 (st(0)): Delete. Extend comment.
509 * i386-tbl.h: Re-generate.
511 2021-03-29 Jan Beulich <jbeulich@suse.com>
513 * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
514 (cmpsd): Move next to cmps.
515 (movsd): Move next to movs.
516 (cmpxchg16b): Move to separate section.
517 (fisttp, fisttpll): Likewise.
518 (monitor, mwait): Likewise.
519 * i386-tbl.h: Re-generate.
521 2021-03-29 Jan Beulich <jbeulich@suse.com>
523 * i386-opc.tbl (psadbw): Add <sse2:comm>.
525 * i386-tbl.h: Re-generate.
527 2021-03-29 Jan Beulich <jbeulich@suse.com>
529 * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
530 pclmul, gfni): New templates. Use them wherever possible. Move
531 SSE4.1 pextrw into respective section.
532 * i386-tbl.h: Re-generate.
534 2021-03-29 Jan Beulich <jbeulich@suse.com>
536 * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
537 strtoull(). Bump upper loop bound. Widen masks. Sanity check
539 * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
540 Convert all of their uses to representation in opcode.
542 2021-03-29 Jan Beulich <jbeulich@suse.com>
544 * i386-opc.h (struct insn_template): Shrink base_opcode to 16
545 bits. Shrink extension_opcode to 9 bits. Make it signed. Change
546 value of None. Shrink operands to 3 bits.
548 2021-03-29 Jan Beulich <jbeulich@suse.com>
550 * i386-gen.c (process_i386_opcode_modifier): New parameter
552 (output_i386_opcode): New local variable "space". Adjust
553 process_i386_opcode_modifier() invocation.
554 (process_i386_opcodes): Adjust process_i386_opcode_modifier()
556 * i386-tbl.h: Re-generate.
558 2021-03-29 Alan Modra <amodra@gmail.com>
560 * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
561 (fp_qualifier_p, get_data_pattern): Likewise.
562 (aarch64_get_operand_modifier_from_value): Likewise.
563 (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
564 (operand_variant_qualifier_p): Likewise.
565 (qualifier_value_in_range_constraint_p): Likewise.
566 (aarch64_get_qualifier_esize): Likewise.
567 (aarch64_get_qualifier_nelem): Likewise.
568 (aarch64_get_qualifier_standard_value): Likewise.
569 (get_lower_bound, get_upper_bound): Likewise.
570 (aarch64_find_best_match, match_operands_qualifier): Likewise.
571 (aarch64_print_operand): Likewise.
572 * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
573 (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
574 (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
575 * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
576 * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
577 (print_insn_tic6x): Likewise.
579 2021-03-29 Alan Modra <amodra@gmail.com>
581 * arc-dis.c (extract_operand_value): Correct NULL cast.
582 * frv-opc.h: Regenerate.
584 2021-03-26 Jan Beulich <jbeulich@suse.com>
586 * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
588 * i386-tbl.h: Re-generate.
590 2021-03-25 Abid Qadeer <abidh@codesourcery.com>
592 * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
593 immediate in br.n instruction.
595 2021-03-25 Jan Beulich <jbeulich@suse.com>
597 * i386-dis.c (XMGatherD, VexGatherD): New.
598 (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
599 (print_insn): Check masking for S/G insns.
600 (OP_E_memory): New local variable check_gather. Extend mandatory
601 SIB check. Check register conflicts for (EVEX-encoded) gathers.
602 Extend check for disallowed 16-bit addressing.
603 (OP_VEX): New local variables modrm_reg and sib_index. Convert
604 if()s to switch(). Check register conflicts for (VEX-encoded)
605 gathers. Drop no longer reachable cases.
606 * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
609 2021-03-25 Jan Beulich <jbeulich@suse.com>
611 * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
612 zeroing-masking without masking.
614 2021-03-25 Jan Beulich <jbeulich@suse.com>
616 * i386-opc.tbl (invlpgb): Fix multi-operand form.
617 (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
618 single-operand forms as deprecated.
619 * i386-tbl.h: Re-generate.
621 2021-03-25 Alan Modra <amodra@gmail.com>
624 * ppc-opc.c (XLOCB_MASK): Delete.
625 (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
627 (powerpc_opcodes): Accept a BH field on all extended forms of
628 bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
630 2021-03-24 Jan Beulich <jbeulich@suse.com>
632 * i386-gen.c (output_i386_opcode): Drop processing of
633 opcode_length. Calculate length from base_opcode. Adjust prefix
634 encoding determination.
635 (process_i386_opcodes): Drop output of fake opcode_length.
636 * i386-opc.h (struct insn_template): Drop opcode_length field.
637 * i386-opc.tbl: Drop opcode length field from all templates.
638 * i386-tbl.h: Re-generate.
640 2021-03-24 Jan Beulich <jbeulich@suse.com>
642 * i386-gen.c (process_i386_opcode_modifier): Return void. New
643 parameter "prefix". Drop local variable "regular_encoding".
644 Record prefix setting / check for consistency.
645 (output_i386_opcode): Parse opcode_length and base_opcode
646 earlier. Derive prefix encoding. Drop no longer applicable
647 consistency checking. Adjust process_i386_opcode_modifier()
649 (process_i386_opcodes): Adjust process_i386_opcode_modifier()
651 * i386-tbl.h: Re-generate.
653 2021-03-24 Jan Beulich <jbeulich@suse.com>
655 * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
657 * i386-opc.h (Prefix_*): Move #define-s.
658 * i386-opc.tbl: Move pseudo prefix enumerator values to
659 extension opcode field. Introduce pseudopfx template.
660 * i386-tbl.h: Re-generate.
662 2021-03-23 Jan Beulich <jbeulich@suse.com>
664 * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
666 * i386-tbl.h: Re-generate.
668 2021-03-23 Jan Beulich <jbeulich@suse.com>
670 * i386-opc.h (struct insn_template): Move cpu_flags field past
672 * i386-tbl.h: Re-generate.
674 2021-03-23 Jan Beulich <jbeulich@suse.com>
676 * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
677 * i386-opc.h (OpcodeSpace): New enumerator.
678 (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
679 (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
680 SPACE_XOP09, SPACE_XOP0A): ... respectively.
681 (struct i386_opcode_modifier): New field opcodespace. Shrink
683 i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
684 SpaceXOP09, SpaceXOP0A): Define. Use them to replace
686 * i386-tbl.h: Re-generate.
688 2021-03-22 Martin Liska <mliska@suse.cz>
690 * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
691 * arc-dis.c (parse_option): Likewise.
692 * arm-dis.c (parse_arm_disassembler_options): Likewise.
693 * cris-dis.c (print_with_operands): Likewise.
694 * h8300-dis.c (bfd_h8_disassemble): Likewise.
695 * i386-dis.c (print_insn): Likewise.
696 * ia64-gen.c (fetch_insn_class): Likewise.
697 (parse_resource_users): Likewise.
698 (in_iclass): Likewise.
699 (lookup_specifier): Likewise.
700 (insert_opcode_dependencies): Likewise.
701 * mips-dis.c (parse_mips_ase_option): Likewise.
702 (parse_mips_dis_option): Likewise.
703 * s390-dis.c (disassemble_init_s390): Likewise.
704 * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
706 2021-03-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
708 * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
710 2021-03-12 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
712 * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
713 icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
715 2021-03-12 Alan Modra <amodra@gmail.com>
717 * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
719 2021-03-11 Jan Beulich <jbeulich@suse.com>
721 * i386-dis.c (OP_XMM): Re-order checks.
723 2021-03-11 Jan Beulich <jbeulich@suse.com>
725 * i386-dis.c (putop): Drop need_vex check when also checking
727 (intel_operand_size, OP_E_memory): Drop vex.evex check when also
730 2021-03-11 Jan Beulich <jbeulich@suse.com>
732 * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
733 checks. Move case label past broadcast check.
735 2021-03-10 Jan Beulich <jbeulich@suse.com>
737 * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
738 vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
739 REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
740 EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
741 EVEX_W_0F38C7_M_0_L_2): Delete.
742 (REG_EVEX_0F38C7_M_0_L_2): New.
743 (intel_operand_size): Handle VEX and EVEX the same for
744 vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
745 vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
746 (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
747 vex_vsib_q_w_d_mode uses.
748 * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
749 0F38A1, and 0F38A3 entries.
750 * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
752 * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
753 * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
756 2021-03-10 Jan Beulich <jbeulich@suse.com>
758 * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
759 REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
760 MOD_VEX_0FXOP_09_12): Rename to ...
761 (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
762 REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
763 (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
764 RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
765 X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
766 X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
767 (reg_table): Adjust comments.
768 (x86_64_table): Move X86_64_0F24, X86_64_0F26,
769 X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
770 X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
771 (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
772 (vex_len_table): Adjust opcode 0A_12 entry.
773 (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
774 MOD_C5_32BIT, and MOD_XOP_09_12 entries.
775 (rm_table): Move hreset entry.
777 2021-03-10 Jan Beulich <jbeulich@suse.com>
779 * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
780 EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
781 EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
782 EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
783 EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
784 (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
785 (get_valid_dis386): Also handle 512-bit vector length when
786 vectoring into vex_len_table[].
787 * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
788 0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
790 * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
791 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
792 * i386-dis-evex-prefix.h: Adjust 0F7E entry.
793 * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
796 2021-03-10 Jan Beulich <jbeulich@suse.com>
798 * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
799 Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
800 EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
801 * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
803 * i386-dis-evex-len.h (evex_len_table): Likewise.
804 * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
806 2021-03-10 Jan Beulich <jbeulich@suse.com>
808 * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
809 MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
810 MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
811 MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
812 MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
813 MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
814 MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
815 MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
816 EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
817 EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
818 EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
819 EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
820 EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
821 EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
822 EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
823 EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
824 EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
825 EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
826 EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
827 EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
828 EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
829 EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
830 EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
831 EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
832 EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
833 EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
834 EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
835 EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
836 EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
837 EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
838 EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
839 EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
840 REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
841 REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
842 MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
843 MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
844 EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
845 EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
846 EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
847 EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
848 EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
849 EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
850 EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
851 EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
852 EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
853 EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
854 EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
855 EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
856 EVEX_W_0F3A43_L_n): New.
857 * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
858 0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
859 0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
860 * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
861 for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
862 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
863 0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
864 * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
865 0F385B, 0F38C6, and 0F38C7 entries.
866 * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
868 * i386-dis-evex-w.h: No longer link to evex_len_table[] for
869 opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
870 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
871 evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
873 2021-03-10 Jan Beulich <jbeulich@suse.com>
875 * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
876 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
877 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
878 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
879 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
880 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
881 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
882 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
883 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
884 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
885 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
886 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
887 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
888 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
889 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
890 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
891 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
892 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
893 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
894 MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
895 MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
896 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
897 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
898 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
899 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
900 PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
901 PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
902 PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
903 PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
904 PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
905 VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
906 VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
907 VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
908 VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
909 VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
910 VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
911 VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
912 VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
913 VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
914 VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
915 VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
916 VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
917 VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
918 VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
919 VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
920 VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
921 VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
922 VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
923 VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
924 VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
925 VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
926 VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
927 VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
928 VEX_W_0F99_P_2_LEN_0): Delete.
929 MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
930 MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
931 MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
932 MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
933 MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
934 PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
935 PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
936 PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
937 PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
938 PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
939 PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
940 PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
941 PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
942 PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
943 PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
944 PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
945 PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
946 PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
947 PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
948 VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
949 VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
950 VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
951 VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
952 VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
953 VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
954 VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
955 VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
956 (prefix_table): No longer link to vex_len_table[] for opcodes
957 0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
958 0F92, 0F93, 0F98, and 0F99.
959 (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
960 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
962 (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
963 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
965 (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
966 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
968 (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
969 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
972 2021-03-10 Jan Beulich <jbeulich@suse.com>
974 * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
975 Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
976 REG_VEX_0F73_M_0 respectively.
977 (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
978 MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
979 MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
980 MOD_VEX_0F73_REG_7): Delete.
981 (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
982 (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
983 PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
984 PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
985 PREFIX_VEX_0F3AF0_L_0 respectively.
986 (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
987 VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
988 VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
989 VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
990 (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
991 VEX_LEN_0F38F7): New.
992 (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
993 (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
994 0F72, and 0F73. No longer link to vex_len_table[] for opcode
996 (prefix_table): No longer link to vex_len_table[] for opcodes
997 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
998 (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
999 0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
1000 0F38F6, 0F38F7, and 0F3AF0.
1001 (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
1002 prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
1003 (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
1006 2021-03-10 Jan Beulich <jbeulich@suse.com>
1008 * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
1009 REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
1010 (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
1011 MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
1012 MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
1013 (MOD_0F71, MOD_0F72, MOD_0F73): New.
1014 (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
1016 (reg_table): No longer link to mod_table[] for opcodes 0F71,
1018 (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
1021 2021-03-10 Jan Beulich <jbeulich@suse.com>
1023 * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
1024 MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
1025 (reg_table): Don't link to mod_table[] where not needed. Add
1026 PREFIX_IGNORED to nop entries.
1027 (prefix_table): Replace PREFIX_OPCODE in nop entries.
1028 (mod_table): Add nop entries next to prefetch ones. Drop
1029 MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
1030 MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
1031 (rm_table): Add PREFIX_IGNORED to nop entries. Drop
1032 PREFIX_OPCODE from endbr* entries.
1033 (get_valid_dis386): Also consider entry's name when zapping
1035 (print_insn): Handle PREFIX_IGNORED.
1037 2021-03-09 Jan Beulich <jbeulich@suse.com>
1039 * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
1040 IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
1042 * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
1043 HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
1044 (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
1045 PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
1046 (struct i386_opcode_modifier): Delete notrackprefixok,
1047 islockable, hleprefixok, and repprefixok fields. Add prefixok
1049 * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
1050 HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
1051 (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
1052 not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
1053 Replace HLEPrefixOk.
1054 * opcodes/i386-tbl.h: Re-generate.
1056 2021-03-09 Jan Beulich <jbeulich@suse.com>
1058 * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
1059 * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
1061 * opcodes/i386-tbl.h: Re-generate.
1063 2021-03-03 Jan Beulich <jbeulich@suse.com>
1065 * i386-gen.c (output_i386_opcode): Don't get operand count. Look
1066 for {} instead of {0}. Don't look for '0'.
1067 * i386-opc.tbl: Drop operand count field. Drop redundant operand
1070 2021-02-19 Nelson Chu <nelson.chu@sifive.com>
1073 * riscv-dis.c (print_insn_args): Updated encoding macros.
1074 * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
1075 (match_c_addi16sp): Updated encoding macros.
1076 (match_c_lui): Likewise.
1077 (match_c_lui_with_hint): Likewise.
1078 (match_c_addi4spn): Likewise.
1079 (match_c_slli): Likewise.
1080 (match_slli_as_c_slli): Likewise.
1081 (match_c_slli64): Likewise.
1082 (match_srxi_as_c_srxi): Likewise.
1083 (riscv_insn_types): Added .insn css/cl/cs.
1085 2021-02-18 Nelson Chu <nelson.chu@sifive.com>
1087 * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
1088 (default_priv_spec): Updated type to riscv_spec_class.
1089 (parse_riscv_dis_option): Updated.
1090 * riscv-opc.c: Moved stuff and make the file tidy.
1092 2021-02-17 Alan Modra <amodra@gmail.com>
1094 * wasm32-dis.c: Include limits.h.
1095 (CHAR_BIT): Provide backup define.
1096 (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
1097 Correct signed overflow checking.
1099 2021-02-16 Jan Beulich <jbeulich@suse.com>
1101 * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
1102 * i386-tbl.h: Re-generate.
1104 2021-02-16 Jan Beulich <jbeulich@suse.com>
1106 * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
1108 * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
1110 2021-02-15 Andreas Krebbel <krebbel@linux.ibm.com>
1112 * s390-mkopc.c (main): Accept arch14 as cpu string.
1113 * s390-opc.txt: Add new arch14 instructions.
1115 2021-02-04 Nick Alcock <nick.alcock@oracle.com>
1117 * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
1119 * configure: Regenerated.
1121 2021-02-08 Mike Frysinger <vapier@gentoo.org>
1123 * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
1124 * tic54x-opc.c (regs): Rename to ...
1125 (tic54x_regs): ... this.
1126 (mmregs): Rename to ...
1127 (tic54x_mmregs): ... this.
1128 (condition_codes): Rename to ...
1129 (tic54x_condition_codes): ... this.
1130 (cc2_codes): Rename to ...
1131 (tic54x_cc2_codes): ... this.
1132 (cc3_codes): Rename to ...
1133 (tic54x_cc3_codes): ... this.
1134 (status_bits): Rename to ...
1135 (tic54x_status_bits): ... this.
1136 (misc_symbols): Rename to ...
1137 (tic54x_misc_symbols): ... this.
1139 2021-02-04 Nelson Chu <nelson.chu@sifive.com>
1141 * riscv-opc.c (MASK_RVB_IMM): Removed.
1142 (riscv_opcodes): Removed zb* instructions.
1143 (riscv_ext_version_table): Removed versions for zb*.
1145 2021-01-26 Alan Modra <amodra@gmail.com>
1147 * i386-gen.c (parse_template): Ensure entire template_instance
1150 2021-01-15 Nelson Chu <nelson.chu@sifive.com>
1152 * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
1153 (riscv_fpr_names_abi): Likewise.
1154 (riscv_opcodes): Likewise.
1155 (riscv_insn_types): Likewise.
1157 2021-01-15 Nelson Chu <nelson.chu@sifive.com>
1159 * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
1161 2021-01-15 Nelson Chu <nelson.chu@sifive.com>
1163 * riscv-dis.c: Comments tidy and improvement.
1164 * riscv-opc.c: Likewise.
1166 2021-01-13 Alan Modra <amodra@gmail.com>
1168 * Makefile.in: Regenerate.
1170 2021-01-12 H.J. Lu <hongjiu.lu@intel.com>
1173 * configure.ac: Use GNU_MAKE_JOBSERVER.
1174 * aclocal.m4: Regenerated.
1175 * configure: Likewise.
1177 2021-01-12 Nick Clifton <nickc@redhat.com>
1179 * po/sr.po: Updated Serbian translation.
1181 2021-01-11 H.J. Lu <hongjiu.lu@intel.com>
1184 * configure: Regenerated.
1186 2021-01-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
1188 * aarch64-asm-2.c: Regenerate.
1189 * aarch64-dis-2.c: Likewise.
1190 * aarch64-opc-2.c: Likewise.
1191 * aarch64-opc.c (aarch64_print_operand):
1192 Delete handling of AARCH64_OPND_CSRE_CSR.
1193 * aarch64-tbl.h (aarch64_feature_csre): Delete.
1195 (_CSRE_INSN): Likewise.
1196 (aarch64_opcode_table): Delete csr.
1198 2021-01-11 Nick Clifton <nickc@redhat.com>
1200 * po/de.po: Updated German translation.
1201 * po/fr.po: Updated French translation.
1202 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1203 * po/sv.po: Updated Swedish translation.
1204 * po/uk.po: Updated Ukranian translation.
1206 2021-01-09 H.J. Lu <hongjiu.lu@intel.com>
1208 * configure: Regenerated.
1210 2021-01-09 Nick Clifton <nickc@redhat.com>
1212 * configure: Regenerate.
1213 * po/opcodes.pot: Regenerate.
1215 2021-01-09 Nick Clifton <nickc@redhat.com>
1217 * 2.36 release branch crated.
1219 2021-01-08 Peter Bergner <bergner@linux.ibm.com>
1221 * ppc-opc.c (insert_dw, (extract_dw): New functions.
1222 (DW, (XRC_MASK): Define.
1223 (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
1225 2021-01-09 Alan Modra <amodra@gmail.com>
1227 * configure: Regenerate.
1229 2021-01-08 Nick Clifton <nickc@redhat.com>
1231 * po/sv.po: Updated Swedish translation.
1233 2021-01-08 Nick Clifton <nickc@redhat.com>
1236 * aarch64-dis.c (determine_disassembling_preference): Move call to
1237 aarch64_match_operands_constraint outside of the assertion.
1238 * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
1239 Replace with a return of FALSE.
1242 * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
1243 core system register.
1245 2021-01-07 Samuel Thibault <samuel.thibault@gnu.org>
1247 * configure: Regenerate.
1249 2021-01-07 Nick Clifton <nickc@redhat.com>
1251 * po/fr.po: Updated French translation.
1253 2021-01-07 Fredrik Noring <noring@nocrew.org>
1255 * m68k-opc.c (chkl): Change minimum architecture requirement to
1258 2021-01-07 Philipp Tomsich <prt@gnu.org>
1260 * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
1262 2021-01-07 Claire Xenia Wolf <claire@symbioticeda.com>
1263 Jim Wilson <jimw@sifive.com>
1264 Andrew Waterman <andrew@sifive.com>
1265 Maxim Blinov <maxim.blinov@embecosm.com>
1266 Kito Cheng <kito.cheng@sifive.com>
1267 Nelson Chu <nelson.chu@sifive.com>
1269 * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
1270 (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
1272 2021-01-01 Alan Modra <amodra@gmail.com>
1274 Update year range in copyright notice of all files.
1276 For older changes see ChangeLog-2020
1278 Copyright (C) 2021-2022 Free Software Foundation, Inc.
1280 Copying and distribution of this file, with or without modification,
1281 are permitted in any medium without royalty provided the copyright
1282 notice and this notice are preserved.
1288 version-control: never