opcodes/ChangeLog

   1 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
   2
   3         * arm-dis.c (arm_opcodes): Support disassembly of UDIV and SDIV in
   4         ARM state.
   5
   6 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
   7
   8         * arm-dis.c (arm_opcodes): SMC implies Security Extensions.
   9         (thumb32_opcodes): Likewise.
  10
  11 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
  12
  13         * arm-dis.c (arm_opcodes): Add support for pldw.
  14         (thumb32_opcodes): Likewise.
  15
  16 2010-09-22  Robin Getz  <robin.getz@analog.com>
  17
  18         * bfin-dis.c (fmtconst): Cast address to 32bits.
  19
  20 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
  21
  22         * bfin-dis.c (decode_REGMV_0): Rewrite valid combo checks.
  23
  24 2010-09-22  Robin Getz  <robin.getz@analog.com>
  25
  26         * bfin-dis.c (decode_ProgCtrl_0): Check for parallel insns.
  27         Reject P6/P7 to TESTSET.
  28         (decode_PushPopReg_0): Check for parallel insns.  Reject pushing
  29         SP onto the stack.
  30         (decode_PushPopMultiple_0): Check for parallel insns.  Make sure
  31         P/D fields match all the time.
  32         (decode_CCflag_0): Check for parallel insns.  Verify x/y fields
  33         are 0 for accumulator compares.
  34         (decode_CC2stat_0): Check for parallel insns.  Reject CC<op>CC.
  35         (decode_CaCTRL_0, decode_ccMV_0, decode_CC2dreg_0, decode_BRCC_0,
  36         decode_UJUMP_0, decode_LOGI2op_0, decode_COMPI2opD_0,
  37         decode_COMPI2opP_0, decode_LoopSetup_0, decode_LDIMMhalf_0,
  38         decode_CALLa_0, decode_linkage_0, decode_pseudoDEBUG_0,
  39         decode_pseudoOChar_0, decode_pseudodbg_assert_0): Check for parallel
  40         insns.
  41         (decode_dagMODim_0): Verify br field for IREG ops.
  42         (decode_LDST_0): Reject preg load into same preg.
  43         (_print_insn_bfin): Handle returns for ILLEGAL decodes.
  44         (print_insn_bfin): Likewise.
  45
  46 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
  47
  48         * bfin-dis.c (decode_PushPopMultiple_0): Return 0 when pr > 5.
  49
  50 2010-09-22  Robin Getz  <robin.getz@analog.com>
  51
  52         * bfin-dis.c (decode_dsp32shiftimm_0): Add missing "S" flag.
  53
  54 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
  55
  56         * bfin-dis.c (decode_CC2stat_0): Decode all ASTAT bits.
  57
  58 2010-09-22  Robin Getz  <robin.getz@analog.com>
  59
  60         * bfin-dis.c (IS_DREG, IS_PREG, IS_GENREG, IS_DAGREG): Reject
  61         register values greater than 8.
  62         (IS_RESERVEDREG, allreg, mostreg): New helpers.
  63         (decode_ProgCtrl_0): Call IS_DREG/IS_PREG as appropriate.
  64         (decode_PushPopReg_0): Call mostreg/allreg as appropriate.
  65         (decode_CC2dreg_0): Check valid CC register number.
  66
  67 2010-09-22  Robin Getz  <robin.getz@analog.com>
  68
  69         * bfin-dis.c (decode_pseudoDEBUG_0): Add space after DBG.
  70
  71 2010-09-22  Robin Getz  <robin.getz@analog.com>
  72
  73         * bfin-dis.c (machine_registers): Add AC0_COPY, V_COPY, and RND_MOD.
  74         (reg_names): Likewise.
  75         (decode_statbits): Likewise; while reformatting to make manageable.
  76
  77 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
  78
  79         * bfin-dis.c (decode_pseudoDEBUG_0): Add space after OUTC.
  80         (decode_pseudoOChar_0): New function.
  81         (_print_insn_bfin): Remove #if 0 and call new decode_pseudoOChar_0.
  82
  83 2010-09-22  Robin Getz  <robin.getz@analog.com>
  84
  85         * bfin-dis.c (decode_dsp32shift_0): Decode sub opcodes 2/2 as
  86         LSHIFT instead of SHIFT.
  87
  88 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
  89
  90         * bfin-dis.c (constant_formats): Constify the whole structure.
  91         (fmtconst): Add const to return value.
  92         (reg_names): Mark const.
  93         (decode_multfunc): Mark s0/s1 as const.
  94         (decode_macfunc): Mark a/sop as const.
  95
  96 2010-09-17  Tejas Belagod  <tejas.belagod@arm.com>
  97
  98         * arm_dis.c (coprocessor_opcodes): Add MRC entry for APSR_nzcv.
  99
 100 2010-09-14  Maciej W. Rozycki  <macro@codesourcery.com>
 101
 102         * mips-opc.c (mips_builtin_opcodes): Add "sync_acquire",
 103         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb".
 104
 105 2010-09-10  Pierre Muller  <muller@ics.u-strasbg.fr>
 106
 107         * src/opcodes/dlx-dis.c (print_insn_dlx): Use dlx_insn type for
 108         dlx_insn_type array.
 109
 110 2010-08-31  H.J. Lu  <hongjiu.lu@intel.com>
 111
 112         PR binutils/11960
 113         * i386-dis.c (sIv): New.
 114         (dis386): Replace Iq with sIv on "pushT".
 115         (reg_table): Replace T with {T|} on callT, JcallT, jmpT and JjmpT.
 116         (x86_64_table): Replace {T|}/{P|} with P.
 117         (putop): Add 'w' to 'T'/'P' if needed for Intel syntax.
 118         (OP_sI): Update v_mode.  Remove w_mode.
 119
 120 2010-08-27  Nathan Froyd  <froydnj@codesourcery.com>
 121
 122         * ppc-opc.c (powerpc_opcodes) [lswx,lswi,stswx,stswi]: Deprecate
 123         on E500 and E500MC.
 124
 125 2010-08-17  H.J. Lu  <hongjiu.lu@intel.com>
 126
 127         * i386-dis.c (reg_table): Replace Eb with Mb on prefetch and
 128         prefetchw.
 129
 130 2010-08-06  Quentin Neill <quentin.neill@amd.com>
 131
 132         * i386-gen.c (cpu_flag_init): Define CpuNop extension flag, add
 133         to processor flags for PENTIUMPRO processors and later.
 134         * i386-opc.h (enum): Add CpuNop.
 135         (i386_cpu_flags): Add cpunop bit.
 136         * i386-opc.tbl: Change nop cpu_flags.
 137         * i386-init.h: Regenerated.
 138         * i386-tbl.h: Likewise.
 139
 140 2010-08-06  Quentin Neill <quentin.neill@amd.com>
 141
 142         * i386-opc.h (enum): Fix typos in comments.
 143
 144 2010-08-06  Alan Modra  <amodra@gmail.com>
 145
 146         * disassemble.c: Formatting.
 147         (disassemble_init_for_target <ARCH_m32c>): Comment on endian.
 148
 149 2010-08-05  H.J. Lu  <hongjiu.lu@intel.com>
 150
 151         * i386-opc.tbl: Add Cpu186 to ud1/ud2/ud2a/ud2b.
 152         * i386-tbl.h: Regenerated.
 153
 154 2010-08-05  H.J. Lu  <hongjiu.lu@intel.com>
 155
 156         * i386-dis.c (dis386_twobyte): Replace ud2a/ud2b with ud2/ud1.
 157
 158         * i386-opc.tbl: Add ud1.  Remove Cpu686 from ud2/ud2a/ud2b.
 159         * i386-tbl.h: Regenerated.
 160
 161 2010-07-29  DJ Delorie  <dj@redhat.com>
 162
 163         * rx-decode.opc (SRR): New.
 164         (rx_decode_opcode): Use it for movbi and movbir.  Decode NOP2 (mov
 165         r0,r0) and NOP3 (max r0,r0) special cases.
 166         * rx-decode.c: Regenerate.
 167
 168 2010-07-28  H.J. Lu  <hongjiu.lu@intel.com>
 169
 170         * i386-dis.c: Add 0F to VEX opcode enums.
 171
 172 2010-07-27  DJ Delorie  <dj@redhat.com>
 173
 174         * rx-decode.opc (store_flags): Remove, replace with F_* macros.
 175         (rx_decode_opcode): Likewise.
 176         * rx-decode.c: Regenerate.
 177
 178 2010-07-23  Naveen.H.S  <naveen.S@kpitcummins.com>
 179             Ina Pandit  <ina.pandit@kpitcummins.com>
 180
 181         * v850-dis.c (v850_sreg_names): Updated structure for system
 182         registers.
 183         (float_cc_names): new structure for condition codes.
 184         (print_value): Update the function that prints value.
 185         (get_operand_value): New function to get the operand value.
 186         (disassemble): Updated to handle the disassembly of instructions.
 187         (print_insn_v850): Updated function to print instruction for different
 188         families.
 189         * opcodes/v850-opc.c (v850_msg_is_out_of_range, insert_i5div1,
 190         extract_i5div1, insert_i5div2, extract_i5div2, insert_i5div3,
 191         extract_i5div3, insert_d5_4, extract_d5_4, extract_d8_6,
 192         insert_d8_7, extract_d8_7, insert_v8, extract_v8, insert_u16_loop,
 193         extract_u16_loop, insert_d16_15, extract_d16_15, insert_d16_16,
 194         extract_d16_16, nsert_d17_16, extract_d17_16, insert_d22,
 195         extract_d22, insert_d23, extract_d23, insert_i9, extract_i9,
 196         insert_u9, extract_u9, extract_spe, insert_r4, extract_r4): New.
 197         (insert_d8_7, insert_d5_4, insert_i5div): Remove.
 198         (v850_operands): Update with the relocation name. Also update
 199         the instructions with specific set of processors.
 200
 201 2010-07-08 Tejas Belagod <tejas.belagod@arm.com>
 202
 203         * arm-dis.c (print_insn_arm): Add cases for printing more
 204         symbolic operands.
 205         (print_insn_thumb32): Likewise.
 206
 207 2010-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
 208
 209         * mips-dis.c (print_insn_mips): Correct branch instruction type
 210         determination.
 211
 212 2010-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
 213
 214         * mips-dis.c (print_mips16_insn_arg): Remove branch instruction
 215         type and delay slot determination.
 216         (print_insn_mips16): Extend branch instruction type and delay
 217         slot determination to cover all instructions.
 218         * mips16-opc.c (BR): Remove macro.
 219         (UBR, CBR): New macros.
 220         (mips16_opcodes): Update branch annotation for "b", "beqz",
 221         "bnez", "bteqz" and "btnez".  Add branch annotation for "jalrc"
 222         and "jrc".
 223
 224 2010-07-05  H.J. Lu  <hongjiu.lu@intel.com>
 225
 226         AVX Programming Reference (June, 2010)
 227         * i386-dis.c (mod_table): Replace rdrnd with rdrand.
 228         * i386-opc.tbl: Likewise.
 229         * i386-tbl.h: Regenerated.
 230
 231 2010-07-05  H.J. Lu  <hongjiu.lu@intel.com>
 232
 233         * i386-opc.h (CpuFSGSBase): Fix a typo in comments.
 234
 235 2010-07-03  Andreas Schwab  <schwab@linux-m68k.org>
 236
 237         * ppc-dis.c (powerpc_init_dialect): Cast PPC_OPCODE_xxx to
 238         ppc_cpu_t before inverting.
 239         (ppc_parse_cpu): Likewise.
 240         (print_insn_powerpc): Likewise.
 241
 242 2010-07-03  Alan Modra  <amodra@gmail.com>
 243
 244         * ppc-dis.c (ppc_opts, powerpc_init_dialect): Remove old opcode flags.
 245         * ppc-opc.c (PPC32, POWER32, COM32, CLASSIC): Delete.
 246         (PPC64, MFDEC2): Update.
 247         (NON32, NO371): Define.
 248         (powerpc_opcode): Update to not use old opcode flags, and avoid
 249         -m601 duplicates.
 250
 251 2010-07-03  DJ Delorie  <dj@delorie.com>
 252
 253         * m32c-ibld.c: Regenerate.
 254
 255 2010-07-03  Alan Modra  <amodra@gmail.com>
 256
 257         * ppc-opc.c (PWR2COM): Define.
 258         (PPCPWR2): Add PPC_OPCODE_COMMON.
 259         (powerpc_opcodes): Add "subc", "subco", "subco.", "fcir", "fcir.",
 260         "fcirz", "fcirz." to -mcom opcodes.  Remove "mfsri", "dclst",
 261         "rac" from -mcom.
 262
 263 2010-07-01  H.J. Lu  <hongjiu.lu@intel.com>
 264
 265         AVX Programming Reference (June, 2010)
 266         * i386-dis.c (PREFIX_0FAE_REG_0): New.
 267         (PREFIX_0FAE_REG_1): Likewise.
 268         (PREFIX_0FAE_REG_2): Likewise.
 269         (PREFIX_0FAE_REG_3): Likewise.
 270         (PREFIX_VEX_3813): Likewise.
 271         (PREFIX_VEX_3A1D): Likewise.
 272         (prefix_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
 273         PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3, PREFIX_VEX_3813 and
 274         PREFIX_VEX_3A1D.
 275         (vex_table): Add PREFIX_VEX_3813 and PREFIX_VEX_3A1D.
 276         (mod_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
 277         PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3 xsaveopt and rdrnd.
 278
 279         * i386-gen.c (cpu_flag_init): Add CPU_XSAVEOPT_FLAGS,
 280         CPU_FSGSBASE_FLAGS, CPU_RDRND_FLAGS and CPU_F16C_FLAGS.
 281         (cpu_flags): Add CpuXsaveopt, CpuFSGSBase, CpuRdRnd and CpuF16C.
 282
 283         * i386-opc.h (CpuXsaveopt): New.
 284         (CpuFSGSBase): Likewise.
 285         (CpuRdRnd): Likewise.
 286         (CpuF16C): Likewise.
 287         (i386_cpu_flags): Add cpuxsaveopt, cpufsgsbase, cpurdrnd and
 288         cpuf16c.
 289
 290         * i386-opc.tbl: Add xsaveopt, rdfsbase, rdgsbase, rdrnd,
 291         wrfsbase, wrgsbase, vcvtph2ps and vcvtps2ph.
 292         * i386-init.h: Regenerated.
 293         * i386-tbl.h: Likewise.
 294
 295 2010-07-01  Sebastian Andrzej Siewior  <bigeasy@linutronix.de>
 296
 297         * ppc-opc.c (powerpc_opcodes): Revert deprecation of mfocrf, mtcrf
 298         and mtocrf on EFS.
 299
 300 2010-06-29  Alan Modra  <amodra@gmail.com>
 301
 302         * maxq-dis.c: Delete file.
 303         * Makefile.am: Remove references to maxq.
 304         * configure.in: Likewise.
 305         * disassemble.c: Likewise.
 306         * Makefile.in: Regenerate.
 307         * configure: Regenerate.
 308         * po/POTFILES.in: Regenerate.
 309
 310 2010-06-29  Alan Modra  <amodra@gmail.com>
 311
 312         * mep-dis.c: Regenerate.
 313
 314 2010-06-28  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 315
 316         * arm-disc.c (parse_insn_neon):  Fix Neon alignment syntax.
 317
 318 2010-06-27  Alan Modra  <amodra@gmail.com>
 319
 320         * arc-dis.c (arc_sprintf): Delete set but unused variables.
 321         (decodeInstr): Likewise.
 322         * dlx-dis.c (print_insn_dlx): Likewise.
 323         * h8300-dis.c (bfd_h8_disassemble_init): Likewise.
 324         * maxq-dis.c (check_move, print_insn): Likewise.
 325         * mep-dis.c (mep_examine_ivc2_insns): Likewise.
 326         * msp430-dis.c (msp430_branchinstr): Likewise.
 327         * bfin-dis.c (_print_insn_bfin): Avoid set but unused warning.
 328         * cgen-asm.in (parse_insn_normal, _cgen_assemble_insn): Likewise.
 329         * sparc-dis.c (print_insn_sparc): Likewise.
 330         * fr30-asm.c: Regenerate.
 331         * frv-asm.c: Regenerate.
 332         * ip2k-asm.c: Regenerate.
 333         * iq2000-asm.c: Regenerate.
 334         * lm32-asm.c: Regenerate.
 335         * m32c-asm.c: Regenerate.
 336         * m32r-asm.c: Regenerate.
 337         * mep-asm.c: Regenerate.
 338         * mt-asm.c: Regenerate.
 339         * openrisc-asm.c: Regenerate.
 340         * xc16x-asm.c: Regenerate.
 341         * xstormy16-asm.c: Regenerate.
 342
 343 2010-06-16  Vincent Rivière  <vincent.riviere@freesbee.fr>
 344
 345         PR gas/11673
 346         * m68k-opc.c (m68k_opcodes): Remove move.l for isab and later.
 347
 348 2010-06-16  Vincent Rivière  <vincent.riviere@freesbee.fr>
 349
 350         PR binutils/11676
 351         * m68k-dis.c (print_insn_arg): Prefix float constants with #0e.
 352
 353 2010-06-14  Sebastian Andrzej Siewior  <bigeasy@linutronix.de>
 354
 355         * ppc-dis.c (ppc_opts):  Remove PPC_OPCODE_E500MC from e500 and
 356         e500x2.  Add PPC_OPCODE_E500 to e500 and e500x2
 357         * ppc-opc.c (powerpc_opcodes): Deprecate all opcodes on EFS which
 358         touch floating point regs and are enabled by COM, PPC or PPCCOM.
 359         Treat sync as msync on e500.  Treat eieio as mbar 1 on e500.
 360         Treat lwsync as msync on e500.
 361
 362 2010-06-07  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 363
 364         * arm-dis.c (thumb-opcodes): Add disassembly for movs.
 365
 366 2010-05-28  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 367
 368         * arm-dis.c (print_insn_neon):  Ensure disassembly of Neon
 369         constants is the same on 32-bit and 64-bit hosts.
 370
 371 2010-05-27  Jason Duerstock  <jason.duerstock+binutils@gmail.com>
 372
 373         * m68k-dis.c (print_insn_m68k): Emit undefined instructions as
 374         .short directives so that they can be reassembled.
 375
 376 2010-05-26  Catherine Moore <clm@codesourcery.com>
 377             David Ung  <davidu@mips.com>
 378
 379         * mips-opc.c: Change membership to I1 for instructions ssnop and
 380         ehb.
 381
 382 2010-05-26  H.J. Lu  <hongjiu.lu@intel.com>
 383
 384         * i386-dis.c (sib): New.
 385         (get_sib): Likewise.
 386         (print_insn): Call get_sib.
 387         OP_E_memory): Use sib.
 388
 389 2010-05-26  Catherine Moore  <clm@codesoourcery.com>
 390
 391         * mips-dis.c (mips_arch): Remove INSN_MIPS16.
 392         * mips-opc.c (I16): Remove.
 393         (mips_builtin_op): Reclassify jalx.
 394
 395 2010-05-19  Alan Modra  <amodra@gmail.com>
 396
 397         * ppc-opc.c (powerpc_opcodes): Enable divdeu, devweu, divde,
 398         divwe, divdeuo, divweuo, divdeo, divweo for A2.  Add icswepx.
 399
 400 2010-05-13  Alan Modra  <amodra@gmail.com>
 401
 402         * ppc-opc.c (powerpc_opcodes): Correct wclr encoding.
 403
 404 2010-05-11  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 405
 406         * arm-dis.c (thumb_opcodes): Update ldmia entry to use new %W
 407         format.
 408         (print_insn_thumb16): Add support for new %W format.
 409
 410 2010-05-07  Tristan Gingold  <gingold@adacore.com>
 411
 412         * Makefile.in: Regenerate with automake 1.11.1.
 413         * aclocal.m4: Ditto.
 414
 415 2010-05-05  Nick Clifton  <nickc@redhat.com>
 416
 417         * po/es.po: Updated Spanish translation.
 418
 419 2010-04-22  Nick Clifton  <nickc@redhat.com>
 420
 421         * po/opcodes.pot: Updated by the Translation project.
 422         * po/vi.po: Updated Vietnamese translation.
 423
 424 2010-04-16  H.J. Lu  <hongjiu.lu@intel.com>
 425
 426         * i386-dis.c (get_valid_dis386): Return bad_opcode on unknown
 427         bits in opcode.
 428
 429 2010-04-09  Nick Clifton  <nickc@redhat.com>
 430
 431         * i386-dis.c (print_insn): Remove unused variable op.
 432         (OP_sI): Remove unused variable mask.
 433
 434 2010-04-07  Alan Modra  <amodra@gmail.com>
 435
 436         * configure: Regenerate.
 437
 438 2010-04-06  Peter Bergner  <bergner@vnet.ibm.com>
 439
 440         * ppc-opc.c (RBOPT): New define.
 441         ("dccci"): Enable for PPCA2.  Make operands optional.
 442         ("iccci"): Likewise.  Do not deprecate for PPC476.
 443
 444 2010-04-02  Masaki Muranaka  <monaka@monami-software.com>
 445
 446         * cr16-opc.c (cr16_instruction): Fix typo in comment.
 447
 448 2010-03-25  Joseph Myers  <joseph@codesourcery.com>
 449
 450         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tic6x-dis.c.
 451         * Makefile.in: Regenerate.
 452         * configure.in (bfd_tic6x_arch): New.
 453         * configure: Regenerate.
 454         * disassemble.c (ARCH_tic6x): Define if ARCH_all.
 455         (disassembler): Handle TI C6X.
 456         * tic6x-dis.c: New.
 457
 458 2010-03-24  Mike Frysinger  <vapier@gentoo.org>
 459
 460         * bfin-dis.c (decode_regs_hi): Change REG_LH2 typo to REG_MH2.
 461
 462 2010-03-23  Joseph Myers  <joseph@codesourcery.com>
 463
 464         * dis-buf.c (buffer_read_memory): Give error for reading just
 465         before the start of memory.
 466
 467 2010-03-22  Sebastian Pop  <sebastian.pop@amd.com>
 468             Quentin Neill <quentin.neill@amd.com>
 469
 470         * i386-dis.c (OP_LWP_I): Removed.
 471         (reg_table): Do not use OP_LWP_I, use Iq.
 472         (OP_LWPCB_E): Remove use of names16.
 473         (OP_LWP_E): Same.
 474         * i386-opc.tbl: Removed 16bit LWP insns.  32bit LWP insns
 475         should not set the Vex.length bit.
 476         * i386-tbl.h: Regenerated.
 477
 478 2010-02-25  Edmar Wienskoski  <edmar@freescale.com>
 479
 480         * ppc-dis.c (ppc_opts): Add PPC_OPCODE_E500MC for "e500mc64".
 481
 482 2010-02-24  Nick Clifton  <nickc@redhat.com>
 483
 484         PR binutils/6773
 485         * arm-dis.c (arm_opcodes): Replace <prefix>addsubx with
 486         <prefix>asx.  Replace <prefix>subaddx with <prefix>sax.
 487         (thumb32_opcodes): Likewise.
 488
 489 2010-02-15  Nick Clifton  <nickc@redhat.com>
 490
 491         * po/vi.po: Updated Vietnamese translation.
 492
 493 2010-02-12  Doug Evans  <dje@sebabeach.org>
 494
 495         * lm32-opinst.c: Regenerate.
 496
 497 2010-02-11  Doug Evans  <dje@sebabeach.org>
 498
 499         * cgen-dis.in (print_normal): Delete CGEN_PRINT_NORMAL.
 500         (print_address): Delete CGEN_PRINT_ADDRESS.
 501         * fr30-dis.c, * frv-dis.c, * ip2k-dis.c, * iq2000-dis.c,
 502         * lm32-dis.c, * m32c-dis.c, * m32r-desc.c, * m32r-desc.h,
 503         * m32r-dis.c, * mep-dis.c, * mt-dis.c, * openrisc-dis.c,
 504         * xc16x-dis.c, * xstormy16-dis.c: Regenerate.
 505
 506         * fr30-desc.c, * fr30-desc.h, * fr30-opc.c,
 507         * frv-desc.c, * frv-desc.h, * frv-opc.c,
 508         * ip2k-desc.c, * ip2k-desc.h, * ip2k-opc.c,
 509         * iq2000-desc.c, * iq2000-desc.h, * iq2000-opc.c,
 510         * lm32-desc.c, * lm32-desc.h, * lm32-opc.c, * lm32-opinst.c,
 511         * m32c-desc.c, * m32c-desc.h, * m32c-opc.c,
 512         * m32r-desc.c, * m32r-desc.h, * m32r-opc.c, * m32r-opinst.c,
 513         * mep-desc.c, * mep-desc.h, * mep-opc.c,
 514         * mt-desc.c, * mt-desc.h, * mt-opc.c,
 515         * openrisc-desc.c, * openrisc-desc.h, * openrisc-opc.c,
 516         * xc16x-desc.c, * xc16x-desc.h, * xc16x-opc.c,
 517         * xstormy16-desc.c, * xstormy16-desc.h, * xstormy16-opc.c: Regenerate.
 518
 519 2010-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 520
 521         * i386-dis.c: Update copyright.
 522         * i386-gen.c: Likewise.
 523         * i386-opc.h: Likewise.
 524         * i386-opc.tbl: Likewise.
 525
 526 2010-02-10  Quentin Neill  <quentin.neill@amd.com>
 527             Sebastian Pop  <sebastian.pop@amd.com>
 528
 529         * i386-dis.c (OP_EX_VexImmW): Reintroduced
 530         function to handle 5th imm8 operand.
 531         (PREFIX_VEX_3A48): Added.
 532         (PREFIX_VEX_3A49): Added.
 533         (VEX_W_3A48_P_2): Added.
 534         (VEX_W_3A49_P_2): Added.
 535         (prefix table): Added entries for PREFIX_VEX_3A48
 536         and PREFIX_VEX_3A49.
 537         (vex table): Added entries for VEX_W_3A48_P_2 and
 538         and VEX_W_3A49_P_2.
 539         * i386-gen.c (operand_type_init): Added OPERAND_TYPE_VEC_IMM4
 540         for Vec_Imm4 operands.
 541         * i386-opc.h (enum): Added Vec_Imm4.
 542         (i386_operand_type): Added vec_imm4.
 543         * i386-opc.tbl: Add entries for vpermilp[ds].
 544         * i386-init.h: Regenerated.
 545         * i386-tbl.h: Regenerated.
 546
 547 2010-02-10  Richard Sandiford  <r.sandiford@uk.ibm.com>
 548
 549         * ppc-dis.c (ppc_opts): Add "pwr4", "pwr5", "pwr5x", "pwr6"
 550         and "pwr7".  Move "a2" into alphabetical order.
 551
 552 2010-02-08  Philipp Tomsich  <philipp.tomsich@theobroma-systems.com>
 553
 554         * ppc-dis.c (ppc_opts): Add titan entry.
 555         * ppc-opc.c (TITAN, MULHW): Define.
 556         (powerpc_opcodes): Support AppliedMicro Titan core (APM83xxx).
 557
 558 2010-02-03  Quentin Neill  <quentin.neill@amd.com>
 559
 560         * i386-gen.c (cpu_flag_init): Rename CPU_AMDFAM15_FLAGS
 561         to CPU_BDVER1_FLAGS
 562         * i386-init.h: Regenerated.
 563
 564 2010-02-03  Anthony Green  <green@moxielogic.com>
 565
 566         * moxie-opc.c (moxie_form1_opc_info): Move "nop" from 0x00 to
 567         0x0f, and make 0x00 an illegal instruction.
 568
 569 2010-01-29  Daniel Jacobowitz  <dan@codesourcery.com>
 570
 571         * opcodes/arm-dis.c (struct arm_private_data): New.
 572         (print_insn_coprocessor, print_insn_arm): Update to use struct
 573         arm_private_data.
 574         (is_mapping_symbol, get_map_sym_type): New functions.
 575         (get_sym_code_type): Check the symbol's section.  Do not check
 576         mapping symbols.
 577         (print_insn): Default to disassembling ARM mode code.  Check
 578         for mapping symbols separately from other symbols.  Use
 579         struct arm_private_data.
 580
 581 2010-01-28  H.J. Lu  <hongjiu.lu@intel.com>
 582
 583         * i386-dis.c (EXVexWdqScalar): New.
 584         (vex_scalar_w_dq_mode): Likewise.
 585         (prefix_table): Update entries for PREFIX_VEX_3899,
 586         PREFIX_VEX_389B, PREFIX_VEX_389D, PREFIX_VEX_389F,
 587         PREFIX_VEX_38A9, PREFIX_VEX_38AB, PREFIX_VEX_38AD,
 588         PREFIX_VEX_38AF, PREFIX_VEX_38B9, PREFIX_VEX_38BB,
 589         PREFIX_VEX_38BD and PREFIX_VEX_38BF.
 590         (intel_operand_size): Handle vex_scalar_w_dq_mode.
 591         (OP_EX): Likewise.
 592
 593 2010-01-27  H.J. Lu  <hongjiu.lu@intel.com>
 594
 595         * i386-dis.c (XMScalar): New.
 596         (EXdScalar): Likewise.
 597         (EXqScalar): Likewise.
 598         (EXqScalarS): Likewise.
 599         (VexScalar): Likewise.
 600         (EXdVexScalarS): Likewise.
 601         (EXqVexScalarS): Likewise.
 602         (XMVexScalar): Likewise.
 603         (scalar_mode): Likewise.
 604         (d_scalar_mode): Likewise.
 605         (d_scalar_swap_mode): Likewise.
 606         (q_scalar_mode): Likewise.
 607         (q_scalar_swap_mode): Likewise.
 608         (vex_scalar_mode): Likewise.
 609         (vex_len_table): Duplcate entries for VEX_LEN_10_P_1,
 610         VEX_LEN_10_P_3, VEX_LEN_11_P_1, VEX_LEN_11_P_3, VEX_LEN_2A_P_1,
 611         VEX_LEN_2A_P_3, VEX_LEN_2C_P_3, VEX_LEN_2D_P_1, VEX_LEN_2E_P_0,
 612         VEX_LEN_2E_P_2, VEX_LEN_2F_P_2, VEX_LEN_51_P_1, VEX_LEN_51_P_3,
 613         VEX_LEN_52_P_1, VEX_LEN_53_P_1, VEX_LEN_58_P_1, VEX_LEN_58_P_3,
 614         VEX_LEN_59_P_1, VEX_LEN_5A_P_1, VEX_LEN_5A_P_3, VEX_LEN_5C_P_1,
 615         VEX_LEN_5C_P_3, VEX_LEN_5D_P_1, VEX_LEN_5D_P_3, VEX_LEN_5E_P_1,
 616         VEX_LEN_5E_P_3, VEX_LEN_5F_P_1, VEX_LEN_5F_P_3, VEX_LEN_6E_P_2,
 617         VEX_LEN_7E_P_1, VEX_LEN_7E_P_2, VEX_LEN_D6_P_2, VEX_LEN_C2_P_1,
 618         VEX_LEN_C2_P_3, VEX_LEN_3A0A_P_2 and VEX_LEN_3A0B_P_2.
 619         (vex_w_table): Update entries for VEX_W_10_P_1, VEX_W_10_P_3,
 620         VEX_W_11_P_1, VEX_W_11_P_3, VEX_W_2E_P_0, VEX_W_2E_P_2,
 621         VEX_W_2F_P_0, VEX_W_2F_P_2, VEX_W_51_P_1, VEX_W_51_P_3,
 622         VEX_W_52_P_1, VEX_W_53_P_1, VEX_W_58_P_1, VEX_W_58_P_3,
 623         VEX_W_59_P_1, VEX_W_59_P_3, VEX_W_5A_P_1, VEX_W_5A_P_3,
 624         VEX_W_5C_P_1, VEX_W_5C_P_3, VEX_W_5D_P_1, VEX_W_5D_P_3,
 625         VEX_W_5E_P_1, VEX_W_5E_P_3, VEX_W_5F_P_1, VEX_W_5F_P_3,
 626         VEX_W_7E_P_1, VEX_W_D6_P_2  VEX_W_C2_P_1, VEX_W_C2_P_3,
 627         VEX_W_3A0A_P_2 and VEX_W_3A0B_P_2.
 628         (intel_operand_size): Handle d_scalar_mode, d_scalar_swap_mode,
 629         q_scalar_mode, q_scalar_swap_mode.
 630         (OP_XMM): Handle scalar_mode.
 631         (OP_EX): Handle d_scalar_mode, d_scalar_swap_mode, q_scalar_mode
 632         and q_scalar_swap_mode.
 633         (OP_VEX): Handle vex_scalar_mode.
 634
 635 2010-01-24  H.J. Lu  <hongjiu.lu@intel.com>
 636
 637         * i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }.
 638
 639 2010-01-24  H.J. Lu  <hongjiu.lu@intel.com>
 640
 641         * i386-dis.c (vex_len_table): Remove trailing { Bad_Opcode }.
 642
 643 2010-01-24  H.J. Lu  <hongjiu.lu@intel.com>
 644
 645         * i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }.
 646
 647 2010-01-24  H.J. Lu  <hongjiu.lu@intel.com>
 648
 649         * i386-dis.c (Bad_Opcode): New.
 650         (bad_opcode): Likewise.
 651         (dis386): Replace { "(bad)", { XX } } with { Bad_Opcode }.
 652         (dis386_twobyte): Likewise.
 653         (reg_table): Likewise.
 654         (prefix_table): Likewise.
 655         (x86_64_table): Likewise.
 656         (vex_len_table): Likewise.
 657         (vex_w_table): Likewise.
 658         (mod_table): Likewise.
 659         (rm_table): Likewise.
 660         (float_reg): Likewise.
 661         (reg_table): Remove trailing "(bad)" entries.
 662         (prefix_table): Likewise.
 663         (x86_64_table): Likewise.
 664         (vex_len_table): Likewise.
 665         (vex_w_table): Likewise.
 666         (mod_table): Likewise.
 667         (rm_table): Likewise.
 668         (get_valid_dis386): Handle bytemode 0.
 669
 670 2010-01-23  H.J. Lu  <hongjiu.lu@intel.com>
 671
 672         * i386-opc.h (VEXScalar): New.
 673
 674         * i386-opc.tbl: Replace "Vex" with "Vex=3" on AVX scalar
 675         instructions.
 676         * i386-tbl.h: Regenerated.
 677
 678 2010-01-21  H.J. Lu  <hongjiu.lu@intel.com>
 679
 680         * i386-dis.c (mod_table): Use FXSAVE on xsave and xrstor.
 681
 682         * i386-opc.tbl: Add xsave64 and xrstor64.
 683         * i386-tbl.h: Regenerated.
 684
 685 2010-01-20  Nick Clifton  <nickc@redhat.com>
 686
 687         PR 11170
 688         * arm-dis.c (print_arm_address): Do not ignore negative bit in PC
 689         based post-indexed addressing.
 690
 691 2010-01-15  Sebastian Pop  <sebastian.pop@amd.com>
 692
 693         * i386-opc.tbl: Support all the possible aliases for VPCOM* insns.
 694         * i386-tbl.h: Regenerated.
 695
 696 2010-01-14  H.J. Lu  <hongjiu.lu@intel.com>
 697
 698         * i386-opc.h (VexVVVV): Replace VEX.DNS with VEX.NDS in
 699         comments.
 700
 701 2010-01-14  H.J. Lu  <hongjiu.lu@intel.com>
 702
 703         * i386-dis.c (names_mm): New.
 704         (intel_names_mm): Likewise.
 705         (att_names_mm): Likewise.
 706         (names_xmm): Likewise.
 707         (intel_names_xmm): Likewise.
 708         (att_names_xmm): Likewise.
 709         (names_ymm): Likewise.
 710         (intel_names_ymm): Likewise.
 711         (att_names_ymm): Likewise.
 712         (print_insn): Set names_mm, names_xmm and names_ymm.
 713         (OP_MMX): Use names_mm, names_xmm and names_ymm.
 714         (OP_XMM): Likewise.
 715         (OP_EM): Likewise.
 716         (OP_EMC): Likewise.
 717         (OP_MXC): Likewise.
 718         (OP_EX): Likewise.
 719         (XMM_Fixup): Likewise.
 720         (OP_VEX): Likewise.
 721         (OP_EX_VexReg): Likewise.
 722         (OP_Vex_2src): Likewise.
 723         (OP_Vex_2src_1): Likewise.
 724         (OP_Vex_2src_2): Likewise.
 725         (OP_REG_VexI4): Likewise.
 726
 727 2010-01-13  H.J. Lu  <hongjiu.lu@intel.com>
 728
 729         * i386-dis.c (print_insn): Update comments.
 730
 731 2010-01-12  H.J. Lu  <hongjiu.lu@intel.com>
 732
 733         * i386-dis.c (rex_original): Removed.
 734         (ckprefix): Remove rex_original.
 735         (print_insn): Update comments.
 736
 737 2010-01-09  Ralf Wildenhues  <Ralf.Wildenhues@gmx.de>
 738
 739         * Makefile.in: Regenerate.
 740         * configure: Regenerate.
 741
 742 2010-01-07  Doug Evans  <dje@sebabeach.org>
 743
 744         * cgen-ibld.in (insert_normal, extract_normal): Minor cleanup.
 745         * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
 746         * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
 747         * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
 748         * xstormy16-ibld.c: Regenerate.
 749
 750 2010-01-06  Quentin Neill  <quentin.neill@amd.com>
 751
 752         * i386-gen.c (cpu_flag_init): Add new CPU_AMDFAM15_FLAGS.
 753         * i386-init.h: Regenerated.
 754
 755 2010-01-06  Daniel Gutson  <dgutson@codesourcery.com>
 756
 757         * arm-dis.c (print_insn): Fixed search for next symbol and data
 758         dumping condition, and the initial mapping symbol state.
 759
 760 2010-01-05  Doug Evans  <dje@sebabeach.org>
 761
 762         * cgen-ibld.in: #include "cgen/basic-modes.h".
 763         * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
 764         * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
 765         * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
 766         * xstormy16-ibld.c: Regenerate.
 767
 768 2010-01-04  Nick Clifton  <nickc@redhat.com>
 769
 770         PR 11123
 771         * arm-dis.c (print_insn_coprocessor): Initialise value.
 772
 773 2010-01-04  Edmar Wienskoski  <edmar@freescale.com>
 774
 775         * ppc-dis.c (ppc_opts): Add entry for "e500mc64".
 776
 777 2010-01-02  Doug Evans  <dje@sebabeach.org>
 778
 779         * cgen-asm.in: Update copyright year.
 780         * cgen-dis.in: Update copyright year.
 781         * cgen-ibld.in: Update copyright year.
 782         * fr30-asm.c, * fr30-desc.c, * fr30-desc.h, * fr30-dis.c,
 783         * fr30-ibld.c, * fr30-opc.c, * fr30-opc.h, * frv-asm.c, * frv-desc.c,
 784         * frv-desc.h, * frv-dis.c, * frv-ibld.c, * frv-opc.c, * frv-opc.h,
 785         * ip2k-asm.c, * ip2k-desc.c, * ip2k-desc.h, * ip2k-dis.c,
 786         * ip2k-ibld.c, * ip2k-opc.c, * ip2k-opc.h, * iq2000-asm.c,
 787         * iq2000-desc.c, * iq2000-desc.h, * iq2000-dis.c, * iq2000-ibld.c,
 788         * iq2000-opc.c, * iq2000-opc.h, * lm32-asm.c, * lm32-desc.c,
 789         * lm32-desc.h, * lm32-dis.c, * lm32-ibld.c, * lm32-opc.c, * lm32-opc.h,
 790         * lm32-opinst.c, * m32c-asm.c, * m32c-desc.c, * m32c-desc.h,
 791         * m32c-dis.c, * m32c-ibld.c, * m32c-opc.c, * m32c-opc.h, * m32r-asm.c,
 792         * m32r-desc.c, * m32r-desc.h, * m32r-dis.c, * m32r-ibld.c,
 793         * m32r-opc.c, * m32r-opc.h, * m32r-opinst.c, * mep-asm.c, * mep-desc.c,
 794         * mep-desc.h, * mep-dis.c, * mep-ibld.c, * mep-opc.c, * mep-opc.h,
 795         * mt-asm.c, * mt-desc.c, * mt-desc.h, * mt-dis.c, * mt-ibld.c,
 796         * mt-opc.c, * mt-opc.h, * openrisc-asm.c, * openrisc-desc.c,
 797         * openrisc-desc.h, * openrisc-dis.c, * openrisc-ibld.c,
 798         * openrisc-opc.c, * openrisc-opc.h, * xc16x-asm.c, * xc16x-desc.c,
 799         * xc16x-desc.h, * xc16x-dis.c, * xc16x-ibld.c, * xc16x-opc.c,
 800         * xc16x-opc.h, * xstormy16-asm.c, * xstormy16-desc.c,
 801         * xstormy16-desc.h, * xstormy16-dis.c, * xstormy16-ibld.c,
 802         * xstormy16-opc.c, * xstormy16-opc.h: Regenerate.
 803
 804 For older changes see ChangeLog-2009
 805 \f
 806 Local Variables:
 807 mode: change-log
 808 left-margin: 8
 809 fill-column: 74
 810 version-control: never
 811 End: