1 2015-04-15 Renlin Li <renlin.li@arm.com>
3 * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
4 use it for ssat and ssat16.
5 (print_insn_thumb32): Add handle case for 'D' control code.
7 2015-04-06 Ilya Tocar <ilya.tocar@intel.com>
8 H.J. Lu <hongjiu.lu@intel.com>
10 * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
11 * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
12 PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
13 PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
14 PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
15 (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
16 Fill prefix_requirement field.
17 (struct dis386): Add prefix_requirement field.
18 (dis386): Fill prefix_requirement field.
19 (dis386_twobyte): Ditto.
20 (twobyte_has_mandatory_prefix_: Remove.
21 (reg_table): Fill prefix_requirement field.
22 (prefix_table): Ditto.
23 (x86_64_table): Ditto.
24 (three_byte_table): Ditto.
27 (vex_len_table): Ditto.
31 (print_insn): Use prefix_requirement.
32 (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
33 FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
36 2015-03-30 Mike Frysinger <vapier@gentoo.org>
38 * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
40 2015-03-29 H.J. Lu <hongjiu.lu@intel.com>
42 * Makefile.in: Regenerated.
44 2015-03-25 Anton Blanchard <anton@samba.org>
46 * ppc-dis.c (disassemble_init_powerpc): Only initialise
47 powerpc_opcd_indices and vle_opcd_indices once.
49 2015-03-25 Anton Blanchard <anton@samba.org>
51 * ppc-opc.c (powerpc_opcodes): Add slbfee.
53 2015-03-24 Terry Guo <terry.guo@arm.com>
55 * arm-dis.c (opcode32): Updated to use new arm feature struct.
57 (coprocessor_opcodes): Replace bit with feature struct.
58 (neon_opcodes): Likewise.
59 (arm_opcodes): Likewise.
60 (thumb_opcodes): Likewise.
61 (thumb32_opcodes): Likewise.
62 (print_insn_coprocessor): Likewise.
63 (print_insn_arm): Likewise.
64 (select_arm_features): Follow new feature struct.
66 2015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
68 * i386-dis.c (rm_table): Add clzero.
69 * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
71 (cpu_flags): Add CpuCLZERO.
72 * i386-opc.h: Add CpuCLZERO.
73 * i386-opc.tbl: Add clzero.
74 * i386-init.h: Re-generated.
75 * i386-tbl.h: Re-generated.
77 2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
79 * mips-opc.c (decode_mips_operand): Fix constraint issues
80 with u and y operands.
82 2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
84 * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
86 2015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
88 * s390-opc.c: Add new IBM z13 instructions.
89 * s390-opc.txt: Likewise.
91 2015-03-10 Renlin Li <renlin.li@arm.com>
93 * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
94 stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
96 * aarch64-asm-2.c: Regenerate.
97 * aarch64-dis-2.c: Likewise.
98 * aarch64-opc-2.c: Likewise.
100 2015-03-03 Jiong Wang <jiong.wang@arm.com>
102 * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
104 2015-02-25 Oleg Endo <olegendo@gcc.gnu.org>
106 * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
108 (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
109 arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
111 2015-02-23 Vinay <Vinay.G@kpit.com>
113 * rl78-decode.opc (MOV): Added space between two operands for
114 'mov' instruction in index addressing mode.
115 * rl78-decode.c: Regenerate.
117 2015-02-19 Pedro Alves <palves@redhat.com>
119 * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
121 2015-02-10 Pedro Alves <palves@redhat.com>
122 Tom Tromey <tromey@redhat.com>
124 * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
125 microblaze_and, microblaze_xor.
126 * microblaze-opc.h (opcodes): Adjust.
128 2015-01-28 James Bowman <james.bowman@ftdichip.com>
130 * Makefile.am: Add FT32 files.
131 * configure.ac: Handle FT32.
132 * disassemble.c (disassembler): Call print_insn_ft32.
133 * ft32-dis.c: New file.
134 * ft32-opc.c: New file.
135 * Makefile.in: Regenerate.
136 * configure: Regenerate.
137 * po/POTFILES.in: Regenerate.
139 2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
141 * nds32-asm.c (keyword_sr): Add new system registers.
143 2015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
145 * s390-dis.c (s390_extract_operand): Support vector register
147 (s390_print_insn_with_opcode): Support new operands types and add
148 new handling of optional operands.
149 * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
150 and include opcode/s390.h instead.
151 (struct op_struct): New field `flags'.
152 (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
153 (dumpTable): Dump flags.
154 (main): Parse flags from the s390-opc.txt file. Add z13 as cpu
156 * s390-opc.c: Add new operands types, instruction formats, and
158 (s390_opformats): Add new formats for .insn.
159 * s390-opc.txt: Add new instructions.
161 2015-01-01 Alan Modra <amodra@gmail.com>
163 Update year range in copyright notice of all files.
165 For older changes see ChangeLog-2014
167 Copyright (C) 2015 Free Software Foundation, Inc.
169 Copying and distribution of this file, with or without modification,
170 are permitted in any medium without royalty provided the copyright
171 notice and this notice are preserved.
177 version-control: never