[ARM] Disassembles SSAT and SSAT16 instructions incorrectly for Thumb-2
[binutils-gdb.git] / opcodes / ChangeLog
1 2015-04-15 Renlin Li <renlin.li@arm.com>
2
3 * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
4 use it for ssat and ssat16.
5 (print_insn_thumb32): Add handle case for 'D' control code.
6
7 2015-04-06 Ilya Tocar <ilya.tocar@intel.com>
8 H.J. Lu <hongjiu.lu@intel.com>
9
10 * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
11 * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
12 PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
13 PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
14 PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
15 (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
16 Fill prefix_requirement field.
17 (struct dis386): Add prefix_requirement field.
18 (dis386): Fill prefix_requirement field.
19 (dis386_twobyte): Ditto.
20 (twobyte_has_mandatory_prefix_: Remove.
21 (reg_table): Fill prefix_requirement field.
22 (prefix_table): Ditto.
23 (x86_64_table): Ditto.
24 (three_byte_table): Ditto.
25 (xop_table): Ditto.
26 (vex_table): Ditto.
27 (vex_len_table): Ditto.
28 (vex_w_table): Ditto.
29 (mod_table): Ditto.
30 (bad_opcode): Ditto.
31 (print_insn): Use prefix_requirement.
32 (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
33 FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
34 (float_reg): Ditto.
35
36 2015-03-30 Mike Frysinger <vapier@gentoo.org>
37
38 * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
39
40 2015-03-29 H.J. Lu <hongjiu.lu@intel.com>
41
42 * Makefile.in: Regenerated.
43
44 2015-03-25 Anton Blanchard <anton@samba.org>
45
46 * ppc-dis.c (disassemble_init_powerpc): Only initialise
47 powerpc_opcd_indices and vle_opcd_indices once.
48
49 2015-03-25 Anton Blanchard <anton@samba.org>
50
51 * ppc-opc.c (powerpc_opcodes): Add slbfee.
52
53 2015-03-24 Terry Guo <terry.guo@arm.com>
54
55 * arm-dis.c (opcode32): Updated to use new arm feature struct.
56 (opcode16): Likewise.
57 (coprocessor_opcodes): Replace bit with feature struct.
58 (neon_opcodes): Likewise.
59 (arm_opcodes): Likewise.
60 (thumb_opcodes): Likewise.
61 (thumb32_opcodes): Likewise.
62 (print_insn_coprocessor): Likewise.
63 (print_insn_arm): Likewise.
64 (select_arm_features): Follow new feature struct.
65
66 2015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
67
68 * i386-dis.c (rm_table): Add clzero.
69 * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
70 Add CPU_CLZERO_FLAGS.
71 (cpu_flags): Add CpuCLZERO.
72 * i386-opc.h: Add CpuCLZERO.
73 * i386-opc.tbl: Add clzero.
74 * i386-init.h: Re-generated.
75 * i386-tbl.h: Re-generated.
76
77 2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
78
79 * mips-opc.c (decode_mips_operand): Fix constraint issues
80 with u and y operands.
81
82 2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
83
84 * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
85
86 2015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
87
88 * s390-opc.c: Add new IBM z13 instructions.
89 * s390-opc.txt: Likewise.
90
91 2015-03-10 Renlin Li <renlin.li@arm.com>
92
93 * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
94 stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
95 related alias.
96 * aarch64-asm-2.c: Regenerate.
97 * aarch64-dis-2.c: Likewise.
98 * aarch64-opc-2.c: Likewise.
99
100 2015-03-03 Jiong Wang <jiong.wang@arm.com>
101
102 * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
103
104 2015-02-25 Oleg Endo <olegendo@gcc.gnu.org>
105
106 * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
107 arch_sh_up.
108 (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
109 arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
110
111 2015-02-23 Vinay <Vinay.G@kpit.com>
112
113 * rl78-decode.opc (MOV): Added space between two operands for
114 'mov' instruction in index addressing mode.
115 * rl78-decode.c: Regenerate.
116
117 2015-02-19 Pedro Alves <palves@redhat.com>
118
119 * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
120
121 2015-02-10 Pedro Alves <palves@redhat.com>
122 Tom Tromey <tromey@redhat.com>
123
124 * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
125 microblaze_and, microblaze_xor.
126 * microblaze-opc.h (opcodes): Adjust.
127
128 2015-01-28 James Bowman <james.bowman@ftdichip.com>
129
130 * Makefile.am: Add FT32 files.
131 * configure.ac: Handle FT32.
132 * disassemble.c (disassembler): Call print_insn_ft32.
133 * ft32-dis.c: New file.
134 * ft32-opc.c: New file.
135 * Makefile.in: Regenerate.
136 * configure: Regenerate.
137 * po/POTFILES.in: Regenerate.
138
139 2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
140
141 * nds32-asm.c (keyword_sr): Add new system registers.
142
143 2015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
144
145 * s390-dis.c (s390_extract_operand): Support vector register
146 operands.
147 (s390_print_insn_with_opcode): Support new operands types and add
148 new handling of optional operands.
149 * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
150 and include opcode/s390.h instead.
151 (struct op_struct): New field `flags'.
152 (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
153 (dumpTable): Dump flags.
154 (main): Parse flags from the s390-opc.txt file. Add z13 as cpu
155 string.
156 * s390-opc.c: Add new operands types, instruction formats, and
157 instruction masks.
158 (s390_opformats): Add new formats for .insn.
159 * s390-opc.txt: Add new instructions.
160
161 2015-01-01 Alan Modra <amodra@gmail.com>
162
163 Update year range in copyright notice of all files.
164
165 For older changes see ChangeLog-2014
166 \f
167 Copyright (C) 2015 Free Software Foundation, Inc.
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