opcodes/ChangeLog

   1 2016-12-09  Maciej W. Rozycki  <macro@imgtec.com>
   2
   3         * mips16-opc.c (decode_mips16_operand) <'e'>: Use HINT rather
   4         than UINT.
   5
   6 2016-12-09  Maciej W. Rozycki  <macro@imgtec.com>
   7
   8         * mips-dis.c (print_insn_mips16): Use a tab rather than a space
   9         to separate `extend' and its uninterpreted argument output.
  10         Separate hexadecimal halves of undecoded extended instructions
  11         output.
  12
  13 2016-12-08  Maciej W. Rozycki  <macro@imgtec.com>
  14
  15         * mips-dis.c (print_mips16_insn_arg): Remove extraneous
  16         indentation space across.
  17
  18 2016-12-08  Maciej W. Rozycki  <macro@imgtec.com>
  19
  20         * mips-dis.c (print_mips16_insn_arg): Avoid delay-slot
  21         adjustment for PC-relative operations following MIPS16e compact
  22         jumps or undefined RR/J(AL)R(C) encodings.
  23
  24 2016-12-08  Maciej W. Rozycki  <macro@imgtec.com>
  25
  26         * aarch64-asm.c (aarch64_ins_reglane): Rename `index' local
  27         variable to `reglane_index'.
  28
  29 2016-12-08  Luis Machado  <lgustavo@codesourcery.com>
  30
  31         * ppc-dis.c (get_powerpc_dialect): Check NULL info->section.
  32
  33 2016-12-07  Maciej W. Rozycki  <macro@imgtec.com>
  34
  35         * mips-dis.c (print_mips16_insn_arg): Fix comment typo.
  36
  37 2016-12-07  Maciej W. Rozycki  <macro@imgtec.com>
  38
  39         * mips16-opc.c (mips16_opcodes): Update comment naming structure
  40         members.
  41
  42 2016-12-07  Maciej W. Rozycki  <macro@imgtec.com>
  43
  44         * mips-dis.c (print_mips_disassembler_options): Reformat output.
  45
  46 2016-12-05  Szabolcs Nagy  <szabolcs.nagy@arm.com>
  47
  48         * arm-dis.c (coprocessor_opcodes): Add vcmla and vcadd.
  49         (print_insn_coprocessor): Add 'V' format for neon D or Q regs.
  50
  51 2016-12-05  Szabolcs Nagy  <szabolcs.nagy@arm.com>
  52
  53         * arm-dis.c (coprocessor_opcodes): Add vjcvt.
  54
  55 2016-12-01  Nick Clifton  <nickc@redhat.com>
  56
  57         PR binutils/20893
  58         * i386-dis.c (OP_VEX): Replace call to abort with a append of bad
  59         opcode designator.
  60
  61 2016-11-29  Claudiu Zissulescu  <claziss@synopsys.com>
  62
  63         * arc-opc.c (insert_ra_chk): New function.
  64         (insert_rb_chk): Likewise.
  65         (insert_rad): Update text error message.
  66         (insert_rcd): Likewise.
  67         (insert_rhv2): Likewise.
  68         (insert_r0): Likewise.
  69         (insert_r1): Likewise.
  70         (insert_r2): Likewise.
  71         (insert_r3): Likewise.
  72         (insert_sp): Likewise.
  73         (insert_gp): Likewise.
  74         (insert_pcl): Likewise.
  75         (insert_blink): Likewise.
  76         (insert_ilink1): Likewise.
  77         (insert_ilink2): Likewise.
  78         (insert_ras): Likewise.
  79         (insert_rbs): Likewise.
  80         (insert_rcs): Likewise.
  81         (insert_simm3s): Likewise.
  82         (insert_rrange): Likewise.
  83         (insert_fpel): Likewise.
  84         (insert_blinkel): Likewise.
  85         (insert_pcel): Likewise.
  86         (insert_nps_3bit_dst): Likewise.
  87         (insert_nps_3bit_dst_short): Likewise.
  88         (insert_nps_3bit_src2_short): Likewise.
  89         (insert_nps_bitop_size_2b): Likewise.
  90         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Likewise.
  91         (RA_CHK): Define.
  92         (RB): Adjust.
  93         (RB_CHK): Define.
  94         (RC): Adjust.
  95         * arc-dis.c (print_insn_arc): Add LOAD and STORE class.
  96         * arc-tbl.h (div, divu): All instructions are DIVREM class.
  97         Change first insn argument to check for LP_COUNT usage.
  98         (rem): Likewise.
  99         (ld, ldd): All instructions are LOAD class.  Change first insn
 100         argument to check for LP_COUNT usage.
 101         (st, std): All instructions are STORE class.
 102         (mac, mpy, dmac, mul, dmpy): All instructions are MPY class.
 103         Change first insn argument to check for LP_COUNT usage.
 104         (mov): All instructions are MOVE class.  Change first insn
 105         argument to check for LP_COUNT usage.
 106
 107 2016-11-29  Claudiu Zissulescu  <claziss@synopsys.com>
 108
 109         * arc-dis.c (is_compatible_p): Remove function.
 110         (skip_this_opcode): Don't add any decoding class to decode list.
 111         Remove warning.
 112         (find_format_from_table): Go through all opcodes, and warn if we
 113         use a guessed mnemonic.
 114
 115 2016-11-28  Ramiro Polla  <ramiro@hex-rays.com>
 116             Amit Pawar  <amit.pawar@amd.com>
 117
 118         PR binutils/20637
 119         * i386-dis.c (get_valid_dis386): Ignore REX_B for 32-bit XOP
 120         instructions.
 121
 122 2016-11-22  Ambrogino Modigliani  <ambrogino.modigliani@gmail.com>
 123
 124         * configure: Regenerate.
 125
 126 2016-11-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
 127
 128         * sparc-opc.c (HWS_V8): Definition moved from
 129         gas/config/tc-sparc.c.
 130         (HWS_V9): Likewise.
 131         (HWS_VA): Likewise.
 132         (HWS_VB): Likewise.
 133         (HWS_VC): Likewise.
 134         (HWS_VD): Likewise.
 135         (HWS_VE): Likewise.
 136         (HWS_VV): Likewise.
 137         (HWS_VM): Likewise.
 138         (HWS2_VM): Likewise.
 139         (sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of
 140         existing entries.
 141
 142 2016-11-22  Claudiu Zissulescu  <claziss@synopsys.com>
 143
 144         * arc-tbl.h: Reorder conditional flags with delay flags for 'b'
 145         instructions.
 146
 147 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 148
 149         * aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define.
 150         (aarch64_feature_simd_v8_3, SIMD_V8_3): Define.
 151         (aarch64_opcode_table): Add fcmla and fcadd.
 152         (AARCH64_OPERANDS): Add IMM_ROT{1,2,3}.
 153         * aarch64-asm.h (aarch64_ins_imm_rotate): Declare.
 154         * aarch64-asm.c (aarch64_ins_imm_rotate): Define.
 155         * aarch64-dis.h (aarch64_ext_imm_rotate): Declare.
 156         * aarch64-dis.c (aarch64_ext_imm_rotate): Define.
 157         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}.
 158         * aarch64-opc.c (fields): Add FLD_rotate{1,2,3}.
 159         (operand_general_constraint_met_p): Rotate and index range check.
 160         (aarch64_print_operand): Handle rotate operand.
 161         * aarch64-asm-2.c: Regenerate.
 162         * aarch64-dis-2.c: Likewise.
 163         * aarch64-opc-2.c: Likewise.
 164
 165 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 166
 167         * aarch64-tbl.h (arch64_opcode_table): Add ldaprb, ldaprh, ldapr.
 168         * aarch64-asm-2.c: Regenerate.
 169         * aarch64-dis-2.c: Regenerate.
 170         * aarch64-opc-2.c: Regenerate.
 171
 172 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 173
 174         * aarch64-tbl.h (arch64_opcode_table): Add fjcvtzs.
 175         (QL_FP2INT_W_D, aarch64_feature_fp_v8_3, FP_V8_3): Define.
 176         * aarch64-asm-2.c: Regenerate.
 177         * aarch64-dis-2.c: Regenerate.
 178         * aarch64-opc-2.c: Regenerate.
 179
 180 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 181
 182         * aarch64-tbl.h (QL_X1NIL): New.
 183         (arch64_opcode_table): Add ldraa, ldrab.
 184         (AARCH64_OPERANDS): Add "ADDR_SIMM10".
 185         * aarch64-asm.h (aarch64_ins_addr_simm10): Declare.
 186         * aarch64-asm.c (aarch64_ins_addr_simm10): Define.
 187         * aarch64-dis.h (aarch64_ext_addr_simm10): Declare.
 188         * aarch64-dis.c (aarch64_ext_addr_simm10): Define.
 189         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_S_simm10.
 190         * aarch64-opc.c (fields): Add data for FLD_S_simm10.
 191         (operand_general_constraint_met_p): Handle AARCH64_OPND_ADDR_SIMM10.
 192         (aarch64_print_operand): Likewise.
 193         * aarch64-asm-2.c: Regenerate.
 194         * aarch64-dis-2.c: Regenerate.
 195         * aarch64-opc-2.c: Regenerate.
 196
 197 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 198
 199         * aarch64-tbl.h (arch64_opcode_table): Add braa, brab, blraa, blrab, braaz,
 200         brabz, blraaz, blrabz, retaa, retab, eretaa, eretab.
 201         * aarch64-asm-2.c: Regenerate.
 202         * aarch64-dis-2.c: Regenerate.
 203         * aarch64-opc-2.c: Regenerate.
 204
 205 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 206
 207         * aarch64-tbl.h (arch64_opcode_table): Add pacga.
 208         (AARCH64_OPERANDS): Add Rm_SP.
 209         * aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_Rm_SP.
 210         * aarch64-asm-2.c: Regenerate.
 211         * aarch64-dis-2.c: Regenerate.
 212         * aarch64-opc-2.c: Regenerate.
 213
 214 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 215
 216         * aarch64-tbl.h (arch64_opcode_table): Add pacia, pacib, pacda, pacdb, autia,
 217         autib, autda, autdb, paciza, pacizb, pacdza, pacdzb, autiza, autizb, autdza,
 218         autdzb, xpaci, xpacd.
 219         * aarch64-asm-2.c: Regenerate.
 220         * aarch64-dis-2.c: Regenerate.
 221         * aarch64-opc-2.c: Regenerate.
 222
 223 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 224
 225         * aarch64-opc.c (aarch64_sys_regs): Add apiakeylo_el1, apiakeyhi_el1,
 226         apibkeylo_el1, apibkeyhi_el1, apdakeylo_el1, apdakeyhi_el1,
 227         apdbkeylo_el1, apdbkeyhi_el1, apgakeylo_el1 and apgakeyhi_el1.
 228         (aarch64_sys_reg_supported_p): Add feature test for new registers.
 229
 230 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 231
 232         * aarch64-tbl.h (aarch64_feature_v8_3, ARMV8_3, V8_3_INSN): New.
 233         (arch64_opcode_table): Add xpaclri, pacia1716, pacib1716, autia1716,
 234         autib1716, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz,
 235         autibsp.
 236         * aarch64-asm-2.c: Regenerate.
 237         * aarch64-dis-2.c: Regenerate.
 238
 239 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 240
 241         * aarch64-gen.c (find_alias_opcode): Increase max_num_aliases to 32.
 242
 243 2016-11-09  H.J. Lu  <hongjiu.lu@intel.com>
 244
 245         PR binutils/20799
 246         * i386-dis-evex.h (evex_table): Replace EdqwS with Edqw.
 247         * i386-dis.c (EdqwS): Removed.
 248         (dqw_swap_mode): Likewise.
 249         (intel_operand_size): Don't check dqw_swap_mode.
 250         (OP_E_register): Likewise.
 251         (OP_E_memory): Likewise.
 252         (OP_G): Likewise.
 253         (OP_EX): Likewise.
 254         * i386-opc.tbl: Remove "S" from EVEX vpextrw.
 255         * i386-tbl.h: Regerated.
 256
 257 2016-11-09  H.J. Lu  <hongjiu.lu@intel.com>
 258
 259         * i386-opc.tbl: Merge AVX512F vmovq.
 260         * i386-tbl.h: Regerated.
 261
 262 2016-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 263
 264         PR binutils/20701
 265         * i386-dis.c (THREE_BYTE_0F7A): Removed.
 266         (dis386_twobyte): Don't use THREE_BYTE_0F7A.
 267         (three_byte_table): Remove THREE_BYTE_0F7A.
 268
 269 2016-11-07  H.J. Lu  <hongjiu.lu@intel.com>
 270
 271         PR binutils/20775
 272         * i386-dis.c (FGRPd9_2): Replace 0 with 1.
 273         (FGRPd9_4): Replace 1 with 2.
 274         (FGRPd9_5): Replace 2 with 3.
 275         (FGRPd9_6): Replace 3 with 4.
 276         (FGRPd9_7): Replace 4 with 5.
 277         (FGRPda_5): Replace 5 with 6.
 278         (FGRPdb_4): Replace 6 with 7.
 279         (FGRPde_3): Replace 7 with 8.
 280         (FGRPdf_4): Replace 8 with 9.
 281         (fgrps): Add an entry for Bad_Opcode.
 282
 283 2016-11-04  Andrew Burgess  <andrew.burgess@embecosm.com>
 284
 285         * arc-opc.c (arc_flag_operands): Add F_DI14.
 286         (arc_flag_classes): Add C_DI14.
 287         * arc-nps400-tbl.h: Add new exc instructions.
 288
 289 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 290
 291         * arc-dis.c (arc_insn_length): Return length 8 for instructions with
 292         major opcode 0xa.
 293         * arc-nps-400-tbl.h: Add dcmac instruction.
 294         * arc-opc.c (arc_operands): Added operands for dcmac instruction.
 295         (insert_nps_rbdouble_64): Added.
 296         (extract_nps_rbdouble_64): Added.
 297         (insert_nps_proto_size): Added.
 298         (extract_nps_proto_size): Added.
 299
 300 2016-11-03  Andrew Burgess  <andrew.burgess@embecosm.com>
 301
 302         * arc-dis.c (struct arc_operand_iterator): Remove all fields
 303         relating to long instruction processing, add new limm field.
 304         (OPCODE): Rename to...
 305         (OPCODE_32BIT_INSN): ...this.
 306         (OPCODE_AC): Delete.
 307         (skip_this_opcode): Handle different instruction lengths, update
 308         macro name.
 309         (special_flag_p): Update parameter type.
 310         (find_format_from_table): Update for more instruction lengths.
 311         (find_format_long_instructions): Delete.
 312         (find_format): Update for more instruction lengths.
 313         (arc_insn_length): Likewise.
 314         (extract_operand_value): Update for more instruction lengths.
 315         (operand_iterator_next): Remove code relating to long
 316         instructions.
 317         (arc_opcode_to_insn_type): New function.
 318         (print_insn_arc):Update for more instructions lengths.
 319         * arc-ext.c (extInstruction_t): Change argument type.
 320         * arc-ext.h (extInstruction_t): Change argument type.
 321         * arc-fxi.h: Change type unsigned to unsigned long long
 322         extensively throughout.
 323         * arc-nps400-tbl.h: Add long instructions taken from
 324         arc_long_opcodes table in arc-opc.c.
 325         * arc-opc.c: Update parameter types on insert/extract handlers.
 326         (arc_long_opcodes): Delete.
 327         (arc_num_long_opcodes): Delete.
 328         (arc_opcode_len): Update for more instruction lengths.
 329
 330 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 331
 332         * arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
 333
 334 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 335
 336         * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
 337         with arc_opcode_len.
 338         (find_format_long_instructions): Likewise.
 339         * arc-opc.c (arc_opcode_len): New function.
 340
 341 2016-11-03  Andrew Burgess  <andrew.burgess@embecosm.com>
 342
 343         * arc-nps400-tbl.h: Fix some instruction masks.
 344
 345 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 346
 347         * i386-dis.c (REG_82): Removed.
 348         (X86_64_82_REG_0): Likewise.
 349         (X86_64_82_REG_1): Likewise.
 350         (X86_64_82_REG_2): Likewise.
 351         (X86_64_82_REG_3): Likewise.
 352         (X86_64_82_REG_4): Likewise.
 353         (X86_64_82_REG_5): Likewise.
 354         (X86_64_82_REG_6): Likewise.
 355         (X86_64_82_REG_7): Likewise.
 356         (X86_64_82): New.
 357         (dis386): Use X86_64_82 instead of REG_82.
 358         (reg_table): Remove REG_82.
 359         (x86_64_table): Add X86_64_82.  Remove X86_64_82_REG_0,
 360         X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
 361         X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
 362         X86_64_82_REG_7.
 363
 364 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 365
 366         PR binutils/20754
 367         * i386-dis.c (REG_82): New.
 368         (X86_64_82_REG_0): Likewise.
 369         (X86_64_82_REG_1): Likewise.
 370         (X86_64_82_REG_2): Likewise.
 371         (X86_64_82_REG_3): Likewise.
 372         (X86_64_82_REG_4): Likewise.
 373         (X86_64_82_REG_5): Likewise.
 374         (X86_64_82_REG_6): Likewise.
 375         (X86_64_82_REG_7): Likewise.
 376         (dis386): Use REG_82.
 377         (reg_table): Add REG_82.
 378         (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
 379         X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
 380         X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
 381
 382 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 383
 384         * i386-dis.c (REG_82): Renamed to ...
 385         (REG_83): This.
 386         (dis386): Updated.
 387         (reg_table): Likewise.
 388
 389 2016-11-02  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 390
 391         * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
 392         * i386-dis-evex.h (evex_table): Updated.
 393         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
 394         CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 395         (cpu_flags): Add CpuAVX512_4VNNIW.
 396         * i386-opc.h (enum): (AVX512_4VNNIW): New.
 397         (i386_cpu_flags): Add cpuavx512_4vnniw.
 398         * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
 399         * i386-init.h: Regenerate.
 400         * i386-tbl.h: Ditto.
 401
 402 2016-11-02  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 403
 404         * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
 405         PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
 406         * i386-dis-evex.h (evex_table): Updated.
 407         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
 408         CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 409         (cpu_flags): Add CpuAVX512_4FMAPS.
 410         (opcode_modifiers): Add ImplicitQuadGroup modifier.
 411         * i386-opc.h (AVX512_4FMAP): New.
 412         (i386_cpu_flags): Add cpuavx512_4fmaps.
 413         (ImplicitQuadGroup): New.
 414         (i386_opcode_modifier): Add implicitquadgroup.
 415         * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
 416         * i386-init.h: Regenerate.
 417         * i386-tbl.h: Ditto.
 418
 419 2016-11-01  Palmer Dabbelt  <palmer@dabbelt.com>
 420             Andrew Waterman <andrew@sifive.com>
 421
 422         Add support for RISC-V architecture.
 423         * configure.ac: Add entry for bfd_riscv_arch.
 424         * configure: Regenerate.
 425         * disassemble.c (disassembler): Add support for riscv.
 426         (disassembler_usage): Likewise.
 427         * riscv-dis.c: New file.
 428         * riscv-opc.c: New file.
 429
 430 2016-10-21  H.J. Lu  <hongjiu.lu@intel.com>
 431
 432         * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
 433         (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
 434         (rm_table): Update the RM_0FAE_REG_7 entry.
 435         * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
 436         (cpu_flags): Remove CpuPCOMMIT.
 437         * i386-opc.h (CpuPCOMMIT): Removed.
 438         (i386_cpu_flags): Remove cpupcommit.
 439         * i386-opc.tbl: Remove pcommit.
 440         * i386-init.h: Regenerated.
 441         * i386-tbl.h: Likewise.
 442
 443 2016-10-20  H.J. Lu  <hongjiu.lu@intel.com>
 444
 445         PR binutis/20705
 446         * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
 447         the highest bit in VEX.vvvv for the 3-byte VEX prefix in
 448         32-bit mode.  Don't check vex.register_specifier in 32-bit
 449         mode.
 450         (OP_VEX): Check for invalid mask registers.
 451
 452 2016-10-18  H.J. Lu  <hongjiu.lu@intel.com>
 453
 454         PR binutis/20699
 455         * i386-dis.c (OP_E_memory): Check addr32flag in stead of
 456         sizeflag.
 457
 458 2016-10-18  H.J. Lu  <hongjiu.lu@intel.com>
 459
 460         PR binutis/20704
 461         * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
 462
 463 2016-10-18  Maciej W. Rozycki  <macro@imgtec.com>
 464
 465         * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
 466         local variable to `index_regno'.
 467
 468 2016-10-17  Cupertino Miranda  <cmiranda@synopsys.com>
 469
 470         * arc-tbl.h: Removed any "inv.+" instructions from the table.
 471
 472 2016-10-14  Claudiu Zissulescu  <claziss@synopsys.com>
 473
 474         * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
 475         usage on ISA basis.
 476
 477 2016-10-11  Jiong Wang  <jiong.wang@arm.com>
 478
 479         PR target/20666
 480         * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
 481
 482 2016-10-07  Jiong Wang  <jiong.wang@arm.com>
 483
 484         PR target/20667
 485         * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
 486         available.
 487
 488 2016-10-07  Alan Modra  <amodra@gmail.com>
 489
 490         * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
 491
 492 2016-10-06  Alan Modra  <amodra@gmail.com>
 493
 494         * aarch64-opc.c: Spell fall through comments consistently.
 495         * i386-dis.c: Likewise.
 496         * aarch64-dis.c: Add missing fall through comments.
 497         * aarch64-opc.c: Likewise.
 498         * arc-dis.c: Likewise.
 499         * arm-dis.c: Likewise.
 500         * i386-dis.c: Likewise.
 501         * m68k-dis.c: Likewise.
 502         * mep-asm.c: Likewise.
 503         * ns32k-dis.c: Likewise.
 504         * sh-dis.c: Likewise.
 505         * tic4x-dis.c: Likewise.
 506         * tic6x-dis.c: Likewise.
 507         * vax-dis.c: Likewise.
 508
 509 2016-10-06  Alan Modra  <amodra@gmail.com>
 510
 511         * arc-ext.c (create_map): Add missing break.
 512         * msp430-decode.opc (encode_as): Likewise.
 513         * msp430-decode.c: Regenerate.
 514
 515 2016-10-06  Alan Modra  <amodra@gmail.com>
 516
 517         * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
 518         * crx-dis.c (print_insn_crx): Likewise.
 519
 520 2016-09-30  H.J. Lu  <hongjiu.lu@intel.com>
 521
 522         PR binutils/20657
 523         * i386-dis.c (putop): Don't assign alt twice.
 524
 525 2016-09-29  Jiong Wang  <jiong.wang@arm.com>
 526
 527         PR target/20553
 528         * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
 529
 530 2016-09-29  Alan Modra  <amodra@gmail.com>
 531
 532         * ppc-opc.c (L): Make compulsory.
 533         (LOPT): New, optional form of L.
 534         (HTM_R): Define as LOPT.
 535         (L0, L1): Delete.
 536         (L32OPT): New, optional for 32-bit L.
 537         (L2OPT): New, 2-bit L for dcbf.
 538         (SVC_LEC): Update.
 539         (L2): Define.
 540         (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
 541         (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
 542         <dcbf>: Use L2OPT.
 543         <tlbiel, tlbie>: Use LOPT.
 544         <wclr, wclrall>: Use L2.
 545
 546 2016-09-26  Vlad Zakharov  <vzakhar@synopsys.com>
 547
 548         * Makefile.in: Regenerate.
 549         * configure: Likewise.
 550
 551 2016-09-26  Claudiu Zissulescu  <claziss@synopsys.com>
 552
 553         * arc-ext-tbl.h (EXTINSN2OPF): Define.
 554         (EXTINSN2OP): Use EXTINSN2OPF.
 555         (bspeekm, bspop, modapp): New extension instructions.
 556         * arc-opc.c (F_DNZ_ND): Define.
 557         (F_DNZ_D): Likewise.
 558         (F_SIZEB1): Changed.
 559         (C_DNZ_D): Define.
 560         (C_HARD): Changed.
 561         * arc-tbl.h (dbnz): New instruction.
 562         (prealloc): Allow it for ARC EM.
 563         (xbfu): Likewise.
 564
 565 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 566
 567         * aarch64-opc.c (print_immediate_offset_address): Print spaces
 568         after commas in addresses.
 569         (aarch64_print_operand): Likewise.
 570
 571 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 572
 573         * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
 574         rather than "should be" or "expected to be" in error messages.
 575
 576 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 577
 578         * aarch64-dis.c (remove_dot_suffix): New function, split out from...
 579         (print_mnemonic_name): ...here.
 580         (print_comment): New function.
 581         (print_aarch64_insn): Call it.
 582         * aarch64-opc.c (aarch64_conds): Add SVE names.
 583         (aarch64_print_operand): Print alternative condition names in
 584         a comment.
 585
 586 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 587
 588         * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
 589         (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
 590         (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
 591         (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
 592         (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
 593         (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
 594         (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
 595         (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
 596         (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
 597         (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
 598         (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
 599         (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
 600         (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
 601         (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
 602         (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
 603         (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
 604         (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
 605         (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
 606         (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
 607         (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
 608         (OP_SVE_XWU, OP_SVE_XXU): New macros.
 609         (aarch64_feature_sve): New variable.
 610         (SVE): New macro.
 611         (_SVE_INSN): Likewise.
 612         (aarch64_opcode_table): Add SVE instructions.
 613         * aarch64-opc.h (extract_fields): Declare.
 614         * aarch64-opc-2.c: Regenerate.
 615         * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
 616         * aarch64-asm-2.c: Regenerate.
 617         * aarch64-dis.c (extract_fields): Make global.
 618         (do_misc_decoding): Handle the new SVE aarch64_ops.
 619         * aarch64-dis-2.c: Regenerate.
 620
 621 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 622
 623         * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
 624         (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
 625         aarch64_field_kinds.
 626         * aarch64-opc.c (fields): Add corresponding entries.
 627         * aarch64-asm.c (aarch64_get_variant): New function.
 628         (aarch64_encode_variant_using_iclass): Likewise.
 629         (aarch64_opcode_encode): Call it.
 630         * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
 631         (aarch64_opcode_decode): Call it.
 632
 633 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 634
 635         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
 636         and FP register operands.
 637         * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
 638         (FLD_SVE_Vn): New aarch64_field_kinds.
 639         * aarch64-opc.c (fields): Add corresponding entries.
 640         (aarch64_print_operand): Handle the new SVE core and FP register
 641         operands.
 642         * aarch64-opc-2.c: Regenerate.
 643         * aarch64-asm-2.c: Likewise.
 644         * aarch64-dis-2.c: Likewise.
 645
 646 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 647
 648         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
 649         immediate operands.
 650         * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
 651         * aarch64-opc.c (fields): Add corresponding entry.
 652         (operand_general_constraint_met_p): Handle the new SVE FP immediate
 653         operands.
 654         (aarch64_print_operand): Likewise.
 655         * aarch64-opc-2.c: Regenerate.
 656         * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
 657         (ins_sve_float_zero_one): New inserters.
 658         * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
 659         (aarch64_ins_sve_float_half_two): Likewise.
 660         (aarch64_ins_sve_float_zero_one): Likewise.
 661         * aarch64-asm-2.c: Regenerate.
 662         * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
 663         (ext_sve_float_zero_one): New extractors.
 664         * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
 665         (aarch64_ext_sve_float_half_two): Likewise.
 666         (aarch64_ext_sve_float_zero_one): Likewise.
 667         * aarch64-dis-2.c: Regenerate.
 668
 669 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 670
 671         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 672         integer immediate operands.
 673         * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
 674         (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
 675         (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
 676         * aarch64-opc.c (fields): Add corresponding entries.
 677         (operand_general_constraint_met_p): Handle the new SVE integer
 678         immediate operands.
 679         (aarch64_print_operand): Likewise.
 680         (aarch64_sve_dupm_mov_immediate_p): New function.
 681         * aarch64-opc-2.c: Regenerate.
 682         * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
 683         (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
 684         * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
 685         (aarch64_ins_limm): ...here.
 686         (aarch64_ins_inv_limm): New function.
 687         (aarch64_ins_sve_aimm): Likewise.
 688         (aarch64_ins_sve_asimm): Likewise.
 689         (aarch64_ins_sve_limm_mov): Likewise.
 690         (aarch64_ins_sve_shlimm): Likewise.
 691         (aarch64_ins_sve_shrimm): Likewise.
 692         * aarch64-asm-2.c: Regenerate.
 693         * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
 694         (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
 695         * aarch64-dis.c (decode_limm): New function, split out from...
 696         (aarch64_ext_limm): ...here.
 697         (aarch64_ext_inv_limm): New function.
 698         (decode_sve_aimm): Likewise.
 699         (aarch64_ext_sve_aimm): Likewise.
 700         (aarch64_ext_sve_asimm): Likewise.
 701         (aarch64_ext_sve_limm_mov): Likewise.
 702         (aarch64_top_bit): Likewise.
 703         (aarch64_ext_sve_shlimm): Likewise.
 704         (aarch64_ext_sve_shrimm): Likewise.
 705         * aarch64-dis-2.c: Regenerate.
 706
 707 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 708
 709         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
 710         operands.
 711         * aarch64-opc.c (aarch64_operand_modifiers): Initialize
 712         the AARCH64_MOD_MUL_VL entry.
 713         (value_aligned_p): Cope with non-power-of-two alignments.
 714         (operand_general_constraint_met_p): Handle the new MUL VL addresses.
 715         (print_immediate_offset_address): Likewise.
 716         (aarch64_print_operand): Likewise.
 717         * aarch64-opc-2.c: Regenerate.
 718         * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
 719         (ins_sve_addr_ri_s9xvl): New inserters.
 720         * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
 721         (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
 722         (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
 723         * aarch64-asm-2.c: Regenerate.
 724         * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
 725         (ext_sve_addr_ri_s9xvl): New extractors.
 726         * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
 727         (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
 728         (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
 729         (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
 730         * aarch64-dis-2.c: Regenerate.
 731
 732 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 733
 734         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 735         address operands.
 736         * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
 737         (FLD_SVE_xs_22): New aarch64_field_kinds.
 738         (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
 739         (get_operand_specific_data): New function.
 740         * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
 741         FLD_SVE_xs_14 and FLD_SVE_xs_22.
 742         (operand_general_constraint_met_p): Handle the new SVE address
 743         operands.
 744         (sve_reg): New array.
 745         (get_addr_sve_reg_name): New function.
 746         (aarch64_print_operand): Handle the new SVE address operands.
 747         * aarch64-opc-2.c: Regenerate.
 748         * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
 749         (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
 750         (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
 751         * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
 752         (aarch64_ins_sve_addr_rr_lsl): Likewise.
 753         (aarch64_ins_sve_addr_rz_xtw): Likewise.
 754         (aarch64_ins_sve_addr_zi_u5): Likewise.
 755         (aarch64_ins_sve_addr_zz): Likewise.
 756         (aarch64_ins_sve_addr_zz_lsl): Likewise.
 757         (aarch64_ins_sve_addr_zz_sxtw): Likewise.
 758         (aarch64_ins_sve_addr_zz_uxtw): Likewise.
 759         * aarch64-asm-2.c: Regenerate.
 760         * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
 761         (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
 762         (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
 763         * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
 764         (aarch64_ext_sve_addr_ri_u6): Likewise.
 765         (aarch64_ext_sve_addr_rr_lsl): Likewise.
 766         (aarch64_ext_sve_addr_rz_xtw): Likewise.
 767         (aarch64_ext_sve_addr_zi_u5): Likewise.
 768         (aarch64_ext_sve_addr_zz): Likewise.
 769         (aarch64_ext_sve_addr_zz_lsl): Likewise.
 770         (aarch64_ext_sve_addr_zz_sxtw): Likewise.
 771         (aarch64_ext_sve_addr_zz_uxtw): Likewise.
 772         * aarch64-dis-2.c: Regenerate.
 773
 774 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 775
 776         * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
 777         AARCH64_OPND_SVE_PATTERN_SCALED.
 778         * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
 779         * aarch64-opc.c (fields): Add a corresponding entry.
 780         (set_multiplier_out_of_range_error): New function.
 781         (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
 782         (operand_general_constraint_met_p): Handle
 783         AARCH64_OPND_SVE_PATTERN_SCALED.
 784         (print_register_offset_address): Use PRIi64 to print the
 785         shift amount.
 786         (aarch64_print_operand): Likewise.  Handle
 787         AARCH64_OPND_SVE_PATTERN_SCALED.
 788         * aarch64-opc-2.c: Regenerate.
 789         * aarch64-asm.h (ins_sve_scale): New inserter.
 790         * aarch64-asm.c (aarch64_ins_sve_scale): New function.
 791         * aarch64-asm-2.c: Regenerate.
 792         * aarch64-dis.h (ext_sve_scale): New inserter.
 793         * aarch64-dis.c (aarch64_ext_sve_scale): New function.
 794         * aarch64-dis-2.c: Regenerate.
 795
 796 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 797
 798         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
 799         AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
 800         * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
 801         (FLD_SVE_prfop): Likewise.
 802         * aarch64-opc.c: Include libiberty.h.
 803         (aarch64_sve_pattern_array): New variable.
 804         (aarch64_sve_prfop_array): Likewise.
 805         (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
 806         (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
 807         AARCH64_OPND_SVE_PRFOP.
 808         * aarch64-asm-2.c: Regenerate.
 809         * aarch64-dis-2.c: Likewise.
 810         * aarch64-opc-2.c: Likewise.
 811
 812 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 813
 814         * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
 815         AARCH64_OPND_QLF_P_[ZM].
 816         (aarch64_print_operand): Print /z and /m where appropriate.
 817
 818 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 819
 820         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
 821         * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
 822         (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
 823         (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
 824         (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
 825         * aarch64-opc.c (fields): Add corresponding entries here.
 826         (operand_general_constraint_met_p): Check that SVE register lists
 827         have the correct length.  Check the ranges of SVE index registers.
 828         Check for cases where p8-p15 are used in 3-bit predicate fields.
 829         (aarch64_print_operand): Handle the new SVE operands.
 830         * aarch64-opc-2.c: Regenerate.
 831         * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
 832         * aarch64-asm.c (aarch64_ins_sve_index): New function.
 833         (aarch64_ins_sve_reglist): Likewise.
 834         * aarch64-asm-2.c: Regenerate.
 835         * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
 836         * aarch64-dis.c (aarch64_ext_sve_index): New function.
 837         (aarch64_ext_sve_reglist): Likewise.
 838         * aarch64-dis-2.c: Regenerate.
 839
 840 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 841
 842         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
 843         (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
 844         (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
 845         * aarch64-opc.c (aarch64_match_operands_constraint): Check for
 846         tied operands.
 847
 848 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 849
 850         * aarch64-opc.c (get_offset_int_reg_name): New function.
 851         (print_immediate_offset_address): Likewise.
 852         (print_register_offset_address): Take the base and offset
 853         registers as parameters.
 854         (aarch64_print_operand): Update caller accordingly.  Use
 855         print_immediate_offset_address.
 856
 857 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 858
 859         * aarch64-opc.c (BANK): New macro.
 860         (R32, R64): Take a register number as argument
 861         (int_reg): Use BANK.
 862
 863 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 864
 865         * aarch64-opc.c (print_register_list): Add a prefix parameter.
 866         (aarch64_print_operand): Update accordingly.
 867
 868 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 869
 870         * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
 871         for FPIMM.
 872         * aarch64-asm.h (ins_fpimm): New inserter.
 873         * aarch64-asm.c (aarch64_ins_fpimm): New function.
 874         * aarch64-asm-2.c: Regenerate.
 875         * aarch64-dis.h (ext_fpimm): New extractor.
 876         * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
 877         (aarch64_ext_fpimm): New function.
 878         * aarch64-dis-2.c: Regenerate.
 879
 880 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 881
 882         * aarch64-asm.c: Include libiberty.h.
 883         (insert_fields): New function.
 884         (aarch64_ins_imm): Use it.
 885         * aarch64-dis.c (extract_fields): New function.
 886         (aarch64_ext_imm): Use it.
 887
 888 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 889
 890         * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
 891         with an esize parameter.
 892         (operand_general_constraint_met_p): Update accordingly.
 893         Fix misindented code.
 894         * aarch64-asm.c (aarch64_ins_limm): Update call to
 895         aarch64_logical_immediate_p.
 896
 897 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 898
 899         * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
 900
 901 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 902
 903         * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
 904
 905 2016-09-15  Claudiu Zissulescu  <claziss@synopsys.com>
 906
 907         * arc-dis.c (find_format): Walk the linked list pointed by einsn.
 908
 909 2016-09-14  Peter Bergner <bergner@vnet.ibm.com>
 910
 911         * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
 912         <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
 913         xor3>: Delete mnemonics.
 914         <cp_abort>: Rename mnemonic from ...
 915         <cpabort>: ...to this.
 916         <setb>: Change to a X form instruction.
 917         <sync>: Change to 1 operand form.
 918         <copy>: Delete mnemonic.
 919         <copy_first>: Rename mnemonic from ...
 920         <copy>: ...to this.
 921         <paste, paste.>: Delete mnemonics.
 922         <paste_last>: Rename mnemonic from ...
 923         <paste.>: ...to this.
 924
 925 2016-09-14  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 926
 927         * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
 928
 929 2016-09-12  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 930
 931         * s390-mkopc.c (main): Support alternate arch strings.
 932
 933 2016-09-12  Patrick Steuer  <steuer@linux.vnet.ibm.com>
 934
 935         * s390-opc.txt: Fix kmctr instruction type.
 936
 937 2016-09-07  H.J. Lu  <hongjiu.lu@intel.com>
 938
 939         * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
 940         * i386-init.h: Regenerated.
 941
 942 2016-08-30  Cupertino Miranda  <cmiranda@synopsys.com>
 943
 944         * opcodes/arc-dis.c (print_insn_arc): Changed.
 945
 946 2016-08-26  Jose E. Marchesi  <jose.marchesi@oracle.com>
 947
 948         * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
 949         camellia_fl.
 950
 951 2016-08-26  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 952
 953         * arm-dis.c (psr_name): Use hex as case labels.  Add detection for
 954         MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
 955         FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
 956
 957 2016-08-24  H.J. Lu  <hongjiu.lu@intel.com>
 958
 959         * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
 960         (PREFIX_MOD_3_0FAE_REG_4): Likewise.
 961         (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
 962         PREFIX_MOD_3_0FAE_REG_4.
 963         (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
 964         PREFIX_MOD_3_0FAE_REG_4.
 965         * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
 966         (cpu_flags): Add CpuPTWRITE.
 967         * i386-opc.h (CpuPTWRITE): New.
 968         (i386_cpu_flags): Add cpuptwrite.
 969         * i386-opc.tbl: Add ptwrite instruction.
 970         * i386-init.h: Regenerated.
 971         * i386-tbl.h: Likewise.
 972
 973 2016-08-24  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 974
 975         * arc-dis.h: Wrap around in extern "C".
 976
 977 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 978
 979         * aarch64-tbl.h (V8_2_INSN): New macro.
 980         (aarch64_opcode_table): Use it.
 981
 982 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 983
 984         * aarch64-tbl.h (aarch64_opcode_table): Make more use of
 985         CORE_INSN, __FP_INSN and SIMD_INSN.
 986
 987 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 988
 989         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
 990         (aarch64_opcode_table): Update uses accordingly.
 991
 992 2016-07-25  Andrew Jenner  <andrew@codesourcery.com>
 993         Kwok Cheung Yeung  <kcy@codesourcery.com>
 994
 995         opcodes/
 996         * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
 997         'e_cmplwi' to 'e_cmpli' instead.
 998         (OPVUPRT, OPVUPRT_MASK): Define.
 999         (powerpc_opcodes): Add E200Z4 insns.
1000         (vle_opcodes): Add context save/restore insns.
1001
1002 2016-07-27  Maciej W. Rozycki  <macro@imgtec.com>
1003
1004         * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
1005         "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
1006         "j".
1007
1008 2016-07-27  Graham Markall  <graham.markall@embecosm.com>
1009
1010         * arc-nps400-tbl.h: Change block comments to GNU format.
1011         * arc-dis.c: Add new globals addrtypenames,
1012         addrtypenames_max, and addtypeunknown.
1013         (get_addrtype): New function.
1014         (print_insn_arc): Print colons and address types when
1015         required.
1016         * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
1017         define insert and extract functions for all address types.
1018         (arc_operands): Add operands for colon and all address
1019         types.
1020         * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
1021         * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
1022         insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
1023         * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
1024         * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
1025         insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
1026
1027 2016-07-21  H.J. Lu  <hongjiu.lu@intel.com>
1028
1029         * configure: Regenerated.
1030
1031 2016-07-20  Claudiu Zissulescu  <claziss@synopsys.com>
1032
1033         * arc-dis.c (skipclass): New structure.
1034         (decodelist): New variable.
1035         (is_compatible_p): New function.
1036         (new_element): Likewise.
1037         (skip_class_p): Likewise.
1038         (find_format_from_table): Use skip_class_p function.
1039         (find_format): Decode first the extension instructions.
1040         (print_insn_arc): Select either ARCEM or ARCHS based on elf
1041         e_flags.
1042         (parse_option): New function.
1043         (parse_disassembler_options): Likewise.
1044         (print_arc_disassembler_options): Likewise.
1045         (print_insn_arc): Use parse_disassembler_options function.  Proper
1046         select ARCv2 cpu variant.
1047         * disassemble.c (disassembler_usage): Add ARC disassembler
1048         options.
1049
1050 2016-07-13  Maciej W. Rozycki  <macro@imgtec.com>
1051
1052         * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
1053         annotation from the "nal" entry and reorder it beyond "bltzal".
1054
1055 2016-07-12  Jose E. Marchesi  <jose.marchesi@oracle.com>
1056
1057         * sparc-opc.c (ldtxa): New macro.
1058         (sparc_opcodes): Use the macro defined above to add entries for
1059         the LDTXA instructions.
1060         (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
1061         instruction.
1062
1063 2016-07-07  James Bowman  <james.bowman@ftdichip.com>
1064
1065         * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
1066         and "jmpc".
1067
1068 2016-07-01  Jan Beulich  <jbeulich@suse.com>
1069
1070         * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
1071         (movzb): Adjust to cover all permitted suffixes.
1072         (movzw): New.
1073         * i386-tbl.h: Re-generate.
1074
1075 2016-07-01  Jan Beulich  <jbeulich@suse.com>
1076
1077         * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
1078         (lgdt): Remove Tbyte from non-64-bit variant.
1079         (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
1080         xsaves64, xsavec64): Remove Disp16.
1081         (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
1082         Remove Disp32S from non-64-bit variants. Remove Disp16 from
1083         64-bit variants.
1084         (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
1085         vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
1086         vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
1087         64-bit variants.
1088         * i386-tbl.h: Re-generate.
1089
1090 2016-07-01  Jan Beulich  <jbeulich@suse.com>
1091
1092         * i386-opc.tbl (xlat): Remove RepPrefixOk.
1093         * i386-tbl.h: Re-generate.
1094
1095 2016-06-30  Yao Qi  <yao.qi@linaro.org>
1096
1097         * arm-dis.c (print_insn): Fix typo in comment.
1098
1099 2016-06-28  Richard Sandiford  <richard.sandiford@arm.com>
1100
1101         * aarch64-opc.c (operand_general_constraint_met_p): Check the
1102         range of ldst_elemlist operands.
1103         (print_register_list): Use PRIi64 to print the index.
1104         (aarch64_print_operand): Likewise.
1105
1106 2016-06-25  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1107
1108         * mcore-opc.h: Remove sentinal.
1109         * mcore-dis.c (print_insn_mcore): Adjust.
1110
1111 2016-06-23  Graham Markall  <graham.markall@embecosm.com>
1112
1113         * arc-opc.c: Correct description of availability of NPS400
1114         features.
1115
1116 2016-06-22  Peter Bergner <bergner@vnet.ibm.com>
1117
1118         * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
1119         (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
1120         mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
1121         xor3>: New mnemonics.
1122         <setb>: Change to a VX form instruction.
1123         (insert_sh6): Add support for rldixor.
1124         (extract_sh6): Likewise.
1125
1126 2016-06-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1127
1128         * arc-ext.h: Wrap in extern C.
1129
1130 2016-06-21  Graham Markall  <graham.markall@embecosm.com>
1131
1132         * arc-dis.c (arc_insn_length): Add comment on instruction length.
1133         Use same method for determining instruction length on ARC700 and
1134         NPS-400.
1135         (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
1136         * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
1137         with the NPS400 subclass.
1138         * arc-opc.c: Likewise.
1139
1140 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
1141
1142         * sparc-opc.c (rdasr): New macro.
1143         (wrasr): Likewise.
1144         (rdpr): Likewise.
1145         (wrpr): Likewise.
1146         (rdhpr): Likewise.
1147         (wrhpr): Likewise.
1148         (sparc_opcodes): Use the macros above to fix and expand the
1149         definition of read/write instructions from/to
1150         asr/privileged/hyperprivileged instructions.
1151         * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
1152         %hva_mask_nz.  Prefer softint_set and softint_clear over
1153         set_softint and clear_softint.
1154         (print_insn_sparc): Support %ver in Rd.
1155
1156 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
1157
1158         * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
1159         architecture according to the hardware capabilities they require.
1160
1161 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
1162
1163         * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
1164         (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
1165         bfd_mach_sparc_v9{c,d,e,v,m}.
1166         * sparc-opc.c (MASK_V9C): Define.
1167         (MASK_V9D): Likewise.
1168         (MASK_V9E): Likewise.
1169         (MASK_V9V): Likewise.
1170         (MASK_V9M): Likewise.
1171         (v6): Add MASK_V9{C,D,E,V,M}.
1172         (v6notlet): Likewise.
1173         (v7): Likewise.
1174         (v8): Likewise.
1175         (v9): Likewise.
1176         (v9andleon): Likewise.
1177         (v9a): Likewise.
1178         (v9b): Likewise.
1179         (v9c): Define.
1180         (v9d): Likewise.
1181         (v9e): Likewise.
1182         (v9v): Likewise.
1183         (v9m): Likewise.
1184         (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
1185
1186 2016-06-15  Nick Clifton  <nickc@redhat.com>
1187
1188         * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
1189         constants to match expected behaviour.
1190         (nds32_parse_opcode): Likewise.  Also for whitespace.
1191
1192 2016-06-15  Andrew Burgess  <andrew.burgess@embecosm.com>
1193
1194         * arc-opc.c (extract_rhv1): Extract value from insn.
1195
1196 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
1197
1198         * arc-nps400-tbl.h: Add ldbit instruction.
1199         * arc-opc.c: Add flag classes required for ldbit.
1200
1201 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
1202
1203         * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
1204         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1205         support the above instructions.
1206
1207 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
1208
1209         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
1210         imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
1211         csma, cbba, zncv, and hofs.
1212         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1213         support the above instructions.
1214
1215 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1216
1217         * arc-nps400-tbl.h: Add andab and orab instructions.
1218
1219 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1220
1221         * arc-nps400-tbl.h: Add addl-like instructions.
1222
1223 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1224
1225         * arc-nps400-tbl.h: Add mxb and imxb instructions.
1226
1227 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1228
1229         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
1230         instructions.
1231
1232 2016-06-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
1233
1234         * s390-dis.c (option_use_insn_len_bits_p): New file scope
1235         variable.
1236         (init_disasm): Handle new command line option "insnlength".
1237         (print_s390_disassembler_options): Mention new option in help
1238         output.
1239         (print_insn_s390): Use the encoded insn length when dumping
1240         unknown instructions.
1241
1242 2016-06-03  Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
1243
1244         * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
1245          to the address and set as symbol address for LDS/ STS immediate operands.
1246
1247 2016-06-07  Alan Modra  <amodra@gmail.com>
1248
1249         * ppc-dis.c (ppc_opts): Delete extraneous parentheses.  Default
1250         cpu for "vle" to e500.
1251         * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
1252         (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
1253         (PPCNONE): Delete, substitute throughout.
1254         (powerpc_opcodes): Remove PPCVLE from "flags".  Add to "deprecated"
1255         except for major opcode 4 and 31.
1256         (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
1257
1258 2016-06-07  Matthew Wahab  <matthew.wahab@arm.com>
1259
1260         * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
1261         ARM_EXT_RAS in relevant entries.
1262
1263 2016-06-03  Peter Bergner <bergner@vnet.ibm.com>
1264
1265         PR binutils/20196
1266         * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
1267         opcodes for E6500.
1268
1269 2016-06-03  H.J. Lu  <hongjiu.lu@intel.com>
1270
1271         PR binutis/18386
1272         * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
1273         (indir_v_mode): New.
1274         Add comments for '&'.
1275         (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
1276         (putop): Handle '&'.
1277         (intel_operand_size): Handle indir_v_mode.
1278         (OP_E_register): Likewise.
1279         * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64.  Add
1280         64-bit indirect call/jmp for AMD64.
1281         * i386-tbl.h: Regenerated
1282
1283 2016-06-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1284
1285         * arc-dis.c (struct arc_operand_iterator): New structure.
1286         (find_format_from_table): All the old content from find_format,
1287         with some minor adjustments, and parameter renaming.
1288         (find_format_long_instructions): New function.
1289         (find_format): Rewritten.
1290         (arc_insn_length): Add LSB parameter.
1291         (extract_operand_value): New function.
1292         (operand_iterator_next): New function.
1293         (print_insn_arc): Use new functions to find opcode, and iterator
1294         over operands.
1295         * arc-opc.c (insert_nps_3bit_dst_short): New function.
1296         (extract_nps_3bit_dst_short): New function.
1297         (insert_nps_3bit_src2_short): New function.
1298         (extract_nps_3bit_src2_short): New function.
1299         (insert_nps_bitop1_size): New function.
1300         (extract_nps_bitop1_size): New function.
1301         (insert_nps_bitop2_size): New function.
1302         (extract_nps_bitop2_size): New function.
1303         (insert_nps_bitop_mod4_msb): New function.
1304         (extract_nps_bitop_mod4_msb): New function.
1305         (insert_nps_bitop_mod4_lsb): New function.
1306         (extract_nps_bitop_mod4_lsb): New function.
1307         (insert_nps_bitop_dst_pos3_pos4): New function.
1308         (extract_nps_bitop_dst_pos3_pos4): New function.
1309         (insert_nps_bitop_ins_ext): New function.
1310         (extract_nps_bitop_ins_ext): New function.
1311         (arc_operands): Add new operands.
1312         (arc_long_opcodes): New global array.
1313         (arc_num_long_opcodes): New global.
1314         * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
1315
1316 2016-06-01  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1317
1318         * nds32-asm.h: Add extern "C".
1319         * sh-opc.h: Likewise.
1320
1321 2016-06-01  Graham Markall  <graham.markall@embecosm.com>
1322
1323         * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
1324         0,b,limm to the rflt instruction.
1325
1326 2016-05-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1327
1328         * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
1329         constant.
1330
1331 2016-05-29  H.J. Lu  <hongjiu.lu@intel.com>
1332
1333         PR gas/20145
1334         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
1335         CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
1336         CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
1337         CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
1338         CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
1339         * i386-init.h: Regenerated.
1340
1341 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1342
1343         PR gas/20145
1344         * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS.  Remove
1345         CpuMMX from CPU_SSE_FLAGS.  Remove AVX and AVX512 bits from
1346         CPU_ANY_SSE_FLAGS.  Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
1347         Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
1348         CpuXSAVEC.  Add CPU_AVX_FLAGS to CpuF16C.  Remove CpuMMX from
1349         CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
1350         CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
1351         Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS.   Add CPU_ANY_287_FLAGS,
1352         CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
1353         CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
1354         CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS.  Enable CpuRegMMX
1355         for MMX.  Enable CpuRegXMM for SSE, AVX and AVX512.  Enable
1356         CpuRegYMM for AVX and AVX512VL,  Enable CpuRegZMM and
1357         CpuRegMask for AVX512.
1358         (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
1359         and CpuRegMask.
1360         (set_bitfield_from_cpu_flag_init): New function.
1361         (set_bitfield): Remove const on f.  Call
1362         set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
1363         * i386-opc.h (CpuRegMMX): New.
1364         (CpuRegXMM): Likewise.
1365         (CpuRegYMM): Likewise.
1366         (CpuRegZMM): Likewise.
1367         (CpuRegMask): Likewise.
1368         (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
1369         and cpuregmask.
1370         * i386-init.h: Regenerated.
1371         * i386-tbl.h: Likewise.
1372
1373 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1374
1375         PR gas/20154
1376         * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
1377         (opcode_modifiers): Add AMD64 and Intel64.
1378         (main): Properly verify CpuMax.
1379         * i386-opc.h (CpuAMD64): Removed.
1380         (CpuIntel64): Likewise.
1381         (CpuMax): Set to CpuNo64.
1382         (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
1383         (AMD64): New.
1384         (Intel64): Likewise.
1385         (i386_opcode_modifier): Add amd64 and intel64.
1386         (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
1387         on call and jmp.
1388         * i386-init.h: Regenerated.
1389         * i386-tbl.h: Likewise.
1390
1391 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1392
1393         PR gas/20154
1394         * i386-gen.c (main): Fail if CpuMax is incorrect.
1395         * i386-opc.h (CpuMax): Set to CpuIntel64.
1396         * i386-tbl.h: Regenerated.
1397
1398 2016-05-27  Nick Clifton  <nickc@redhat.com>
1399
1400         PR target/20150
1401         * msp430-dis.c (msp430dis_read_two_bytes): New function.
1402         (msp430dis_opcode_unsigned): New function.
1403         (msp430dis_opcode_signed): New function.
1404         (msp430_singleoperand): Use the new opcode reading functions.
1405         Only disassenmble bytes if they were successfully read.
1406         (msp430_doubleoperand): Likewise.
1407         (msp430_branchinstr): Likewise.
1408         (msp430x_callx_instr): Likewise.
1409         (print_insn_msp430): Check that it is safe to read bytes before
1410         attempting disassembly.  Use the new opcode reading functions.
1411
1412 2016-05-26  Peter Bergner <bergner@vnet.ibm.com>
1413
1414         * ppc-opc.c (CY): New define.  Document it.
1415         (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1416
1417 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1418
1419         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1420         CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1421         and CPU_AVX512VBMI_FLAGS.  Add CpuAVX512DQ, CpuAVX512BW,
1422         CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1423         CPU_ANY_AVX_FLAGS.
1424         * i386-init.h: Regenerated.
1425
1426 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1427
1428         PR gas/20141
1429         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1430         CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1431         * i386-init.h: Regenerated.
1432
1433 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1434
1435         * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1436         CPU_ANY_X87_FLAGS.  Add CPU_ANY_MMX_FLAGS.
1437         * i386-init.h: Regenerated.
1438
1439 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
1440
1441         * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1442         information.
1443         (print_insn_arc): Set insn_type information.
1444         * arc-opc.c (C_CC): Add F_CLASS_COND.
1445         * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1446         (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1447         (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1448         (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1449         (brne, brne_s, jeq_s, jne_s): Likewise.
1450
1451 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
1452
1453         * arc-tbl.h (neg): New instruction variant.
1454
1455 2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>
1456
1457         * arc-dis.c (find_format, find_format, get_auxreg)
1458         (print_insn_arc): Changed.
1459         * arc-ext.h (INSERT_XOP): Likewise.
1460
1461 2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1462
1463         * tic54x-dis.c (sprint_mmr): Adjust.
1464         * tic54x-opc.c: Likewise.
1465
1466 2016-05-19  Alan Modra  <amodra@gmail.com>
1467
1468         * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1469
1470 2016-05-19  Alan Modra  <amodra@gmail.com>
1471
1472         * ppc-opc.c: Formatting.
1473         (NSISIGNOPT): Define.
1474         (powerpc_opcodes <subis>): Use NSISIGNOPT.
1475
1476 2016-05-18  Maciej W. Rozycki  <macro@imgtec.com>
1477
1478         * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1479         replacing references to `micromips_ase' throughout.
1480         (_print_insn_mips): Don't use file-level microMIPS annotation to
1481         determine the disassembly mode with the symbol table.
1482
1483 2016-05-13  Peter Bergner <bergner@vnet.ibm.com>
1484
1485         * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1486
1487 2016-05-11  Andrew Bennett  <andrew.bennett@imgtec.com>
1488
1489         * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1490         mips64r6.
1491         * mips-opc.c (D34): New macro.
1492         (mips_builtin_opcodes): Define bposge32c for DSPr3.
1493
1494 2016-05-10  Alexander Fomin  <alexander.fomin@intel.com>
1495
1496         * i386-dis.c (prefix_table): Add RDPID instruction.
1497         * i386-gen.c (cpu_flag_init): Add RDPID flag.
1498         (cpu_flags): Add RDPID bitfield.
1499         * i386-opc.h (enum): Add RDPID element.
1500         (i386_cpu_flags): Add RDPID field.
1501         * i386-opc.tbl: Add RDPID instruction.
1502         * i386-init.h: Regenerate.
1503         * i386-tbl.h: Regenerate.
1504
1505 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1506
1507         * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1508         branch type of a symbol.
1509         (print_insn): Likewise.
1510
1511 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1512
1513         * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1514         Mainline Security Extensions instructions.
1515         (thumb_opcodes): Add entries for narrow ARMv8-M Security
1516         Extensions instructions.
1517         (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1518         instructions.
1519         (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1520         special registers.
1521
1522 2016-05-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
1523
1524         * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1525
1526 2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>
1527
1528         * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1529         (arcExtMap_genOpcode): Likewise.
1530         * arc-opc.c (arg_32bit_rc): Define new variable.
1531         (arg_32bit_u6): Likewise.
1532         (arg_32bit_limm): Likewise.
1533
1534 2016-05-03  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1535
1536         * aarch64-gen.c (VERIFIER): Define.
1537         * aarch64-opc.c (VERIFIER): Define.
1538         (verify_ldpsw): Use static linkage.
1539         * aarch64-opc.h (verify_ldpsw): Remove.
1540         * aarch64-tbl.h: Use VERIFIER for verifiers.
1541
1542 2016-04-28  Nick Clifton  <nickc@redhat.com>
1543
1544         PR target/19722
1545         * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1546         * aarch64-opc.c (verify_ldpsw): New function.
1547         * aarch64-opc.h (verify_ldpsw): New prototype.
1548         * aarch64-tbl.h: Add initialiser for verifier field.
1549         (LDPSW): Set verifier to verify_ldpsw.
1550
1551 2016-04-23  H.J. Lu  <hongjiu.lu@intel.com>
1552
1553         PR binutils/19983
1554         PR binutils/19984
1555         * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1556         smaller than address size.
1557
1558 2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1559
1560         * alpha-dis.c: Regenerate.
1561         * crx-dis.c: Likewise.
1562         * disassemble.c: Likewise.
1563         * epiphany-opc.c: Likewise.
1564         * fr30-opc.c: Likewise.
1565         * frv-opc.c: Likewise.
1566         * ip2k-opc.c: Likewise.
1567         * iq2000-opc.c: Likewise.
1568         * lm32-opc.c: Likewise.
1569         * lm32-opinst.c: Likewise.
1570         * m32c-opc.c: Likewise.
1571         * m32r-opc.c: Likewise.
1572         * m32r-opinst.c: Likewise.
1573         * mep-opc.c: Likewise.
1574         * mt-opc.c: Likewise.
1575         * or1k-opc.c: Likewise.
1576         * or1k-opinst.c: Likewise.
1577         * tic80-opc.c: Likewise.
1578         * xc16x-opc.c: Likewise.
1579         * xstormy16-opc.c: Likewise.
1580
1581 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1582
1583         * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1584         fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1585         calcsd, and calcxd instructions.
1586         * arc-opc.c (insert_nps_bitop_size): Delete.
1587         (extract_nps_bitop_size): Delete.
1588         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1589         (extract_nps_qcmp_m3): Define.
1590         (extract_nps_qcmp_m2): Define.
1591         (extract_nps_qcmp_m1): Define.
1592         (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1593         (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1594         (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1595         NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1596         NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1597         NPS_QCMP_M3.
1598
1599 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1600
1601         * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1602
1603 2016-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1604
1605         * Makefile.in: Regenerated with automake 1.11.6.
1606         * aclocal.m4: Likewise.
1607
1608 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1609
1610         * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1611         instructions.
1612         * arc-opc.c (insert_nps_cmem_uimm16): New function.
1613         (extract_nps_cmem_uimm16): New function.
1614         (arc_operands): Add NPS_XLDST_UIMM16 operand.
1615
1616 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1617
1618         * arc-dis.c (arc_insn_length): New function.
1619         (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1620         (find_format): Change insnLen parameter to unsigned.
1621
1622 2016-04-13  Nick Clifton  <nickc@redhat.com>
1623
1624         PR target/19937
1625         * v850-opc.c (v850_opcodes): Correct masks for long versions of
1626         the LD.B and LD.BU instructions.
1627
1628 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1629
1630         * arc-dis.c (find_format): Check for extension flags.
1631         (print_flags): New function.
1632         (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1633         .extAuxRegister.
1634         * arc-ext.c (arcExtMap_coreRegName): Use
1635         LAST_EXTENSION_CORE_REGISTER.
1636         (arcExtMap_coreReadWrite): Likewise.
1637         (dump_ARC_extmap): Update printing.
1638         * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1639         (arc_aux_regs): Add cpu field.
1640         * arc-regs.h: Add cpu field, lower case name aux registers.
1641
1642 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1643
1644         * arc-tbl.h: Add rtsc, sleep with no arguments.
1645
1646 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1647
1648         * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1649         Initialize.
1650         (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1651         (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1652         (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1653         (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1654         (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1655         (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1656         (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1657         (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1658         (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1659         (arc_opcode arc_opcodes): Null terminate the array.
1660         (arc_num_opcodes): Remove.
1661         * arc-ext.h (INSERT_XOP): Define.
1662         (extInstruction_t): Likewise.
1663         (arcExtMap_instName): Delete.
1664         (arcExtMap_insn): New function.
1665         (arcExtMap_genOpcode): Likewise.
1666         * arc-ext.c (ExtInstruction): Remove.
1667         (create_map): Zero initialize instruction fields.
1668         (arcExtMap_instName): Remove.
1669         (arcExtMap_insn): New function.
1670         (dump_ARC_extmap): More info while debuging.
1671         (arcExtMap_genOpcode): New function.
1672         * arc-dis.c (find_format): New function.
1673         (print_insn_arc): Use find_format.
1674         (arc_get_disassembler): Enable dump_ARC_extmap only when
1675         debugging.
1676
1677 2016-04-11  Maciej W. Rozycki  <macro@imgtec.com>
1678
1679         * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1680         instruction bits out.
1681
1682 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1683
1684         * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1685         * arc-opc.c (arc_flag_operands): Add new flags.
1686         (arc_flag_classes): Add new classes.
1687
1688 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1689
1690         * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1691
1692 2016-04-05  Andrew Burgess  <andrew.burgess@embecosm.com>
1693
1694         * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1695         encode1, rflt, crc16, and crc32 instructions.
1696         * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1697         (arc_flag_classes): Add C_NPS_R.
1698         (insert_nps_bitop_size_2b): New function.
1699         (extract_nps_bitop_size_2b): Likewise.
1700         (insert_nps_bitop_uimm8): Likewise.
1701         (extract_nps_bitop_uimm8): Likewise.
1702         (arc_operands): Add new operand entries.
1703
1704 2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>
1705
1706         * arc-regs.h: Add a new subclass field.  Add double assist
1707         accumulator register values.
1708         * arc-tbl.h: Use DPA subclass to mark the double assist
1709         instructions.  Use DPX/SPX subclas to mark the FPX instructions.
1710         * arc-opc.c (RSP): Define instead of SP.
1711         (arc_aux_regs): Add the subclass field.
1712
1713 2016-04-05  Jiong Wang  <jiong.wang@arm.com>
1714
1715         * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1716
1717 2016-03-31  Andrew Burgess  <andrew.burgess@embecosm.com>
1718
1719         * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1720         NPS_R_SRC1.
1721
1722 2016-03-30  Andrew Burgess  <andrew.burgess@embecosm.com>
1723
1724         * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1725         issues.  No functional changes.
1726
1727 2016-03-30  Claudiu Zissulescu  <claziss@synopsys.com>
1728
1729         * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1730         (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1731         (RTT): Remove duplicate.
1732         (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1733         (PCT_CONFIG*): Remove.
1734         (D1L, D1H, D2H, D2L): Define.
1735
1736 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1737
1738         * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
1739
1740 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1741
1742         * arc-tbl.h (invld07): Remove.
1743         * arc-ext-tbl.h: New file.
1744         * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1745         * arc-opc.c (arc_opcodes): Add ext-tbl include.
1746
1747 2016-03-24  Jan Kratochvil  <jan.kratochvil@redhat.com>
1748
1749         Fix -Wstack-usage warnings.
1750         * aarch64-dis.c (print_operands): Substitute size.
1751         * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1752
1753 2016-03-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
1754
1755         * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1756         to get a proper diagnostic when an invalid ASR register is used.
1757
1758 2016-03-22  Nick Clifton  <nickc@redhat.com>
1759
1760         * configure: Regenerate.
1761
1762 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1763
1764         * arc-nps400-tbl.h: New file.
1765         * arc-opc.c: Add top level comment.
1766         (insert_nps_3bit_dst): New function.
1767         (extract_nps_3bit_dst): New function.
1768         (insert_nps_3bit_src2): New function.
1769         (extract_nps_3bit_src2): New function.
1770         (insert_nps_bitop_size): New function.
1771         (extract_nps_bitop_size): New function.
1772         (arc_flag_operands): Add nps400 entries.
1773         (arc_flag_classes): Add nps400 entries.
1774         (arc_operands): Add nps400 entries.
1775         (arc_opcodes): Add nps400 include.
1776
1777 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1778
1779         * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1780         the new class enum values.
1781
1782 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1783
1784         * arc-dis.c (print_insn_arc): Handle nps400.
1785
1786 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1787
1788         * arc-opc.c (BASE): Delete.
1789
1790 2016-03-18  Nick Clifton  <nickc@redhat.com>
1791
1792         PR target/19721
1793         * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1794         of MOV insn that aliases an ORR insn.
1795
1796 2016-03-16  Jiong Wang  <jiong.wang@arm.com>
1797
1798         * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1799
1800 2016-03-07  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1801
1802         * mcore-opc.h: Add const qualifiers.
1803         * microblaze-opc.h (struct op_code_struct): Likewise.
1804         * sh-opc.h: Likewise.
1805         * tic4x-dis.c (tic4x_print_indirect): Likewise.
1806         (tic4x_print_op): Likewise.
1807
1808 2016-03-02  Alan Modra  <amodra@gmail.com>
1809
1810         * or1k-desc.h: Regenerate.
1811         * fr30-ibld.c: Regenerate.
1812         * rl78-decode.c: Regenerate.
1813
1814 2016-03-01  Nick Clifton  <nickc@redhat.com>
1815
1816         PR target/19747
1817         * rl78-dis.c (print_insn_rl78_common): Fix typo.
1818
1819 2016-02-24  Renlin Li  <renlin.li@arm.com>
1820
1821         * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1822         (print_insn_coprocessor): Support fp16 instructions.
1823
1824 2016-02-24  Renlin Li  <renlin.li@arm.com>
1825
1826         * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1827         vminnm, vrint(mpna).
1828
1829 2016-02-24  Renlin Li  <renlin.li@arm.com>
1830
1831         * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1832         cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1833
1834 2016-02-15  H.J. Lu  <hongjiu.lu@intel.com>
1835
1836         * i386-dis.c (print_insn): Parenthesize expression to prevent
1837         truncated addresses.
1838         (OP_J): Likewise.
1839
1840 2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
1841             Janek van Oirschot  <jvanoirs@synopsys.com>
1842
1843         * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1844         variable.
1845
1846 2016-02-04  Nick Clifton  <nickc@redhat.com>
1847
1848         PR target/19561
1849         * msp430-dis.c (print_insn_msp430): Add a special case for
1850         decoding an RRC instruction with the ZC bit set in the extension
1851         word.
1852
1853 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1854
1855         * cgen-ibld.in (insert_normal): Rework calculation of shift.
1856         * epiphany-ibld.c: Regenerate.
1857         * fr30-ibld.c: Regenerate.
1858         * frv-ibld.c: Regenerate.
1859         * ip2k-ibld.c: Regenerate.
1860         * iq2000-ibld.c: Regenerate.
1861         * lm32-ibld.c: Regenerate.
1862         * m32c-ibld.c: Regenerate.
1863         * m32r-ibld.c: Regenerate.
1864         * mep-ibld.c: Regenerate.
1865         * mt-ibld.c: Regenerate.
1866         * or1k-ibld.c: Regenerate.
1867         * xc16x-ibld.c: Regenerate.
1868         * xstormy16-ibld.c: Regenerate.
1869
1870 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1871
1872         * epiphany-dis.c: Regenerated from latest cpu files.
1873
1874 2016-02-01  Michael McConville  <mmcco@mykolab.com>
1875
1876         * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1877         test bit.
1878
1879 2016-01-25  Renlin Li  <renlin.li@arm.com>
1880
1881         * arm-dis.c (mapping_symbol_for_insn): New function.
1882         (find_ifthen_state): Call mapping_symbol_for_insn().
1883
1884 2016-01-20  Matthew Wahab  <matthew.wahab@arm.com>
1885
1886         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1887         of MSR UAO immediate operand.
1888
1889 2016-01-18  Maciej W. Rozycki  <macro@imgtec.com>
1890
1891         * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1892         instruction support.
1893
1894 2016-01-17  Alan Modra  <amodra@gmail.com>
1895
1896         * configure: Regenerate.
1897
1898 2016-01-14  Nick Clifton  <nickc@redhat.com>
1899
1900         * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1901         instructions that can support stack pointer operations.
1902         * rl78-decode.c: Regenerate.
1903         * rl78-dis.c: Fix display of stack pointer in MOVW based
1904         instructions.
1905
1906 2016-01-14  Matthew Wahab  <matthew.wahab@arm.com>
1907
1908         * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1909         testing for RAS support.  Add checks for erxfr_el1, erxctlr_el1,
1910         erxtatus_el1 and erxaddr_el1.
1911
1912 2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>
1913
1914         * arm-dis.c (arm_opcodes): Add "esb".
1915         (thumb_opcodes): Likewise.
1916
1917 2016-01-11  Peter Bergner <bergner@vnet.ibm.com>
1918
1919         * ppc-opc.c <xscmpnedp>: Delete.
1920         <xvcmpnedp>: Likewise.
1921         <xvcmpnedp.>: Likewise.
1922         <xvcmpnesp>: Likewise.
1923         <xvcmpnesp.>: Likewise.
1924
1925 2016-01-08  Andreas Schwab  <schwab@linux-m68k.org>
1926
1927         PR gas/13050
1928         * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1929         addition to ISA_A.
1930
1931 2016-01-01  Alan Modra  <amodra@gmail.com>
1932
1933         Update year range in copyright notice of all files.
1934
1935 For older changes see ChangeLog-2015
1936 \f
1937 Copyright (C) 2016 Free Software Foundation, Inc.
1938
1939 Copying and distribution of this file, with or without modification,
1940 are permitted in any medium without royalty provided the copyright
1941 notice and this notice are preserved.
1942
1943 Local Variables:
1944 mode: change-log
1945 left-margin: 8
1946 fill-column: 74
1947 version-control: never
1948 End: