1 2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
3 * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
4 reference in CP0 move operand decoding.
6 2017-05-12 Maciej W. Rozycki <macro@imgtec.com>
8 * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
10 (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
12 2017-05-11 Maciej W. Rozycki <macro@imgtec.com>
14 * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
15 "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
16 "sync_rmb" and "sync_wmb" as aliases.
17 * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
18 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
20 2017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
22 * arc-dis.c (parse_option): Update quarkse_em option..
23 * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
25 (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
27 2017-05-03 Kito Cheng <kito.cheng@gmail.com>
29 * riscv-dis.c (print_insn_args): Handle 'Co' operands.
31 2017-05-01 Michael Clark <michaeljclark@mac.com>
33 * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
36 2017-05-02 Maciej W. Rozycki <macro@imgtec.com>
38 * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
39 and branches and not synthetic data instructions.
41 2017-05-02 Bernd Edlinger <bernd.edlinger@hotmail.de>
43 * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
45 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
47 * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
48 * arc-opc.c (insert_r13el): New function.
50 * arc-tbl.h: Add new enter/leave variants.
52 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
54 * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
56 2017-04-25 Maciej W. Rozycki <macro@imgtec.com>
58 * mips-dis.c (print_mips_disassembler_options): Add
61 2017-04-25 Maciej W. Rozycki <macro@imgtec.com>
63 * mips16-opc.c (AL): New macro.
64 (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
65 of "ld" and "lw" as aliases.
67 2017-04-24 Tamar Christina <tamar.christina@arm.com>
69 * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
72 2017-04-22 Alexander Fedotov <alfedotov@gmail.com>
73 Alan Modra <amodra@gmail.com>
75 * ppc-opc.c (ELEV): Define.
76 (vle_opcodes): Add se_rfgi and e_sc.
77 (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
80 2017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com>
82 * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
84 2017-04-21 Nick Clifton <nickc@redhat.com>
87 * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
90 2017-04-13 Alan Modra <amodra@gmail.com>
92 * epiphany-desc.c: Regenerate.
93 * fr30-desc.c: Regenerate.
94 * frv-desc.c: Regenerate.
95 * ip2k-desc.c: Regenerate.
96 * iq2000-desc.c: Regenerate.
97 * lm32-desc.c: Regenerate.
98 * m32c-desc.c: Regenerate.
99 * m32r-desc.c: Regenerate.
100 * mep-desc.c: Regenerate.
101 * mt-desc.c: Regenerate.
102 * or1k-desc.c: Regenerate.
103 * xc16x-desc.c: Regenerate.
104 * xstormy16-desc.c: Regenerate.
106 2017-04-11 Alan Modra <amodra@gmail.com>
108 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
109 PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set
110 PPC_OPCODE_TMR for e6500.
111 * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
112 (PPCVEC3): Define as PPC_OPCODE_POWER9.
113 (PPCVSX2): Define as PPC_OPCODE_POWER8.
114 (PPCVSX3): Define as PPC_OPCODE_POWER9.
115 (PPCHTM): Define as PPC_OPCODE_POWER8.
116 (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
118 2017-04-10 Alan Modra <amodra@gmail.com>
120 * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
121 * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
122 (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
123 removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
125 2017-04-09 Pip Cet <pipcet@gmail.com>
127 * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
128 appropriate floating-point precision directly.
130 2017-04-07 Alan Modra <amodra@gmail.com>
132 * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
133 lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
134 lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
135 lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
136 vector instructions with E6500 not PPCVEC2.
138 2017-04-06 Pip Cet <pipcet@gmail.com>
140 * Makefile.am: Add wasm32-dis.c.
141 * configure.ac: Add wasm32-dis.c to wasm32 target.
142 * disassemble.c: Add wasm32 disassembler code.
143 * wasm32-dis.c: New file.
144 * Makefile.in: Regenerate.
145 * configure: Regenerate.
146 * po/POTFILES.in: Regenerate.
147 * po/opcodes.pot: Regenerate.
149 2017-04-05 Pedro Alves <palves@redhat.com>
151 * arc-dis.c (parse_option, parse_disassembler_options): Constify.
152 * arm-dis.c (parse_arm_disassembler_options): Constify.
153 * ppc-dis.c (powerpc_init_dialect): Constify local.
154 * vax-dis.c (parse_disassembler_options): Constify.
156 2017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
158 * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
161 2017-03-30 Pip Cet <pipcet@gmail.com>
163 * configure.ac: Add (empty) bfd_wasm32_arch target.
164 * configure: Regenerate
165 * po/opcodes.pot: Regenerate.
167 2017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
169 Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
171 * opcodes/sparc-opc.c (asi_table): New ASIs.
173 2017-03-29 Alan Modra <amodra@gmail.com>
175 * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
177 (lookup_powerpc): Don't special case -1 dialect. Handle
179 (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
180 lookup_powerpc call, pass it on second.
182 2017-03-27 Alan Modra <amodra@gmail.com>
185 * ppc-dis.c (struct ppc_mopt): Comment.
186 (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
188 2017-03-27 Rinat Zelig <rinat@mellanox.com>
190 * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
191 * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
192 F_NPS_M, F_NPS_CORE, F_NPS_ALL.
193 (insert_nps_misc_imm_offset): New function.
194 (extract_nps_misc imm_offset): New function.
195 (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
196 (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
198 2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
200 * s390-mkopc.c (main): Remove vx2 check.
201 * s390-opc.txt: Remove vx2 instruction flags.
203 2017-03-21 Rinat Zelig <rinat@mellanox.com>
205 * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
206 * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
207 (insert_nps_imm_offset): New function.
208 (extract_nps_imm_offset): New function.
209 (insert_nps_imm_entry): New function.
210 (extract_nps_imm_entry): New function.
212 2017-03-17 Alan Modra <amodra@gmail.com>
215 * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
216 mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
217 those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
219 2017-03-14 Kito Cheng <kito.cheng@gmail.com>
221 * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
225 2017-03-14 Kito Cheng <kito.cheng@gmail.com>
227 * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
229 2017-03-13 Andrew Waterman <andrew@sifive.com>
231 * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
236 2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
238 * i386-gen.c (opcode_modifiers): Replace S with Load.
239 * i386-opc.h (S): Removed.
241 (i386_opcode_modifier): Replace s with load.
242 * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
243 and {evex}. Replace S with Load.
244 * i386-tbl.h: Regenerated.
246 2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
248 * i386-opc.tbl: Use CpuCET on rdsspq.
249 * i386-tbl.h: Regenerated.
251 2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
253 * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
254 <vsx>: Do not use PPC_OPCODE_VSX3;
256 2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
258 * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
260 2017-03-06 H.J. Lu <hongjiu.lu@intel.com>
262 * i386-dis.c (REG_0F1E_MOD_3): New enum.
263 (MOD_0F1E_PREFIX_1): Likewise.
264 (MOD_0F38F5_PREFIX_2): Likewise.
265 (MOD_0F38F6_PREFIX_0): Likewise.
266 (RM_0F1E_MOD_3_REG_7): Likewise.
267 (PREFIX_MOD_0_0F01_REG_5): Likewise.
268 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
269 (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
270 (PREFIX_0F1E): Likewise.
271 (PREFIX_MOD_0_0FAE_REG_5): Likewise.
272 (PREFIX_0F38F5): Likewise.
273 (dis386_twobyte): Use PREFIX_0F1E.
274 (reg_table): Add REG_0F1E_MOD_3.
275 (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
276 PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
277 PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
278 PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
279 (three_byte_table): Use PREFIX_0F38F5.
280 (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
281 Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
282 (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
283 RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
284 PREFIX_MOD_3_0F01_REG_5_RM_2.
285 * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
286 (cpu_flags): Add CpuCET.
287 * i386-opc.h (CpuCET): New enum.
288 (CpuUnused): Commented out.
289 (i386_cpu_flags): Add cpucet.
290 * i386-opc.tbl: Add Intel CET instructions.
291 * i386-init.h: Regenerated.
292 * i386-tbl.h: Likewise.
294 2017-03-06 Alan Modra <amodra@gmail.com>
297 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
298 (extract_raq, extract_ras, extract_rbx): New functions.
299 (powerpc_operands): Use opposite corresponding insert function.
301 (powerpc_opcodes): Apply Q_MASK to all quad insns with even
302 register restriction.
304 2017-02-28 Peter Bergner <bergner@vnet.ibm.com>
306 * disassemble.c Include "safe-ctype.h".
307 (disassemble_init_for_target): Handle s390 init.
308 (remove_whitespace_and_extra_commas): New function.
309 (disassembler_options_cmp): Likewise.
310 * arm-dis.c: Include "libiberty.h".
312 (regnames): Use long disassembler style names.
313 Add force-thumb and no-force-thumb options.
314 (NUM_ARM_REGNAMES): Rename from this...
315 (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
316 (get_arm_regname_num_options): Delete.
317 (set_arm_regname_option): Likewise.
318 (get_arm_regnames): Likewise.
319 (parse_disassembler_options): Likewise.
320 (parse_arm_disassembler_option): Rename from this...
321 (parse_arm_disassembler_options): ...to this. Make static.
322 Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
323 (print_insn): Use parse_arm_disassembler_options.
324 (disassembler_options_arm): New function.
325 (print_arm_disassembler_options): Handle updated regnames.
326 * ppc-dis.c: Include "libiberty.h".
327 (ppc_opts): Add "32" and "64" entries.
328 (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
329 (powerpc_init_dialect): Add break to switch statement.
330 Use new FOR_EACH_DISASSEMBLER_OPTION macro.
331 (disassembler_options_powerpc): New function.
332 (print_ppc_disassembler_options): Use ARRAY_SIZE.
333 Remove printing of "32" and "64".
334 * s390-dis.c: Include "libiberty.h".
335 (init_flag): Remove unneeded variable.
336 (struct s390_options_t): New structure type.
337 (options): New structure.
338 (init_disasm): Rename from this...
339 (disassemble_init_s390): ...to this. Add initializations for
340 current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
341 (print_insn_s390): Delete call to init_disasm.
342 (disassembler_options_s390): New function.
343 (print_s390_disassembler_options): Print using information from
345 * po/opcodes.pot: Regenerate.
347 2017-02-28 Jan Beulich <jbeulich@suse.com>
349 * i386-dis.c (PCMPESTR_Fixup): New.
350 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
351 (prefix_table): Use PCMPESTR_Fixup.
352 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
354 (vex_w_table): Delete VPCMPESTR{I,M} entries.
355 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
356 Split 64-bit and non-64-bit variants.
357 * opcodes/i386-tbl.h: Re-generate.
359 2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
361 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
362 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
363 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
364 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
365 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
366 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
367 (OP_SVE_V_HSD): New macros.
368 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
369 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
370 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
371 (aarch64_opcode_table): Add new SVE instructions.
372 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
373 for rotation operands. Add new SVE operands.
374 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
375 (ins_sve_quad_index): Likewise.
376 (ins_imm_rotate): Split into...
377 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
378 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
379 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
381 (aarch64_ins_sve_addr_ri_s4): New function.
382 (aarch64_ins_sve_quad_index): Likewise.
383 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
384 * aarch64-asm-2.c: Regenerate.
385 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
386 (ext_sve_quad_index): Likewise.
387 (ext_imm_rotate): Split into...
388 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
389 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
390 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
392 (aarch64_ext_sve_addr_ri_s4): New function.
393 (aarch64_ext_sve_quad_index): Likewise.
394 (aarch64_ext_sve_index): Allow quad indices.
395 (do_misc_decoding): Likewise.
396 * aarch64-dis-2.c: Regenerate.
397 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
399 (OPD_F_OD_MASK): Widen by one bit.
400 (OPD_F_NO_ZR): Bump accordingly.
401 (get_operand_field_width): New function.
402 * aarch64-opc.c (fields): Add new SVE fields.
403 (operand_general_constraint_met_p): Handle new SVE operands.
404 (aarch64_print_operand): Likewise.
405 * aarch64-opc-2.c: Regenerate.
407 2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
409 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
410 (aarch64_feature_compnum): ...this.
411 (SIMD_V8_3): Replace with...
413 (CNUM_INSN): New macro.
414 (aarch64_opcode_table): Use it for the complex number instructions.
416 2017-02-24 Jan Beulich <jbeulich@suse.com>
418 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
420 2017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
422 Add support for associating SPARC ASIs with an architecture level.
423 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
424 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
425 decoding of SPARC ASIs.
427 2017-02-23 Jan Beulich <jbeulich@suse.com>
429 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
430 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
432 2017-02-21 Jan Beulich <jbeulich@suse.com>
434 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
435 1 (instead of to itself). Correct typo.
437 2017-02-14 Andrew Waterman <andrew@sifive.com>
439 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
442 2017-02-15 Richard Sandiford <richard.sandiford@arm.com>
444 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
445 (aarch64_sys_reg_supported_p): Handle them.
447 2017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
449 * arc-opc.c (UIMM6_20R): Define.
450 (SIMM12_20): Use above.
451 (SIMM12_20R): Define.
452 (SIMM3_5_S): Use above.
453 (UIMM7_A32_11R_S): Define.
454 (UIMM7_9_S): Use above.
455 (UIMM3_13R_S): Define.
456 (SIMM11_A32_7_S): Use above.
458 (UIMM10_A32_8_S): Use above.
459 (UIMM8_8R_S): Define.
461 (arc_relax_opcodes): Use all above defines.
463 2017-02-15 Vineet Gupta <vgupta@synopsys.com>
465 * arc-regs.h: Distinguish some of the registers different on
466 ARC700 and HS38 cpus.
468 2017-02-14 Alan Modra <amodra@gmail.com>
471 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
472 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
474 2017-02-11 Stafford Horne <shorne@gmail.com>
475 Alan Modra <amodra@gmail.com>
477 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
478 Use insn_bytes_value and insn_int_value directly instead. Don't
479 free allocated memory until function exit.
481 2017-02-10 Nicholas Piggin <npiggin@gmail.com>
483 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
485 2017-02-03 Nick Clifton <nickc@redhat.com>
488 * aarch64-opc.c (print_register_list): Ensure that the register
489 list index will fir into the tb buffer.
490 (print_register_offset_address): Likewise.
491 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
493 2017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
496 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
497 instructions when the previous fetch packet ends with a 32-bit
500 2017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
502 * pru-opc.c: Remove vague reference to a future GDB port.
504 2017-01-20 Nick Clifton <nickc@redhat.com>
506 * po/ga.po: Updated Irish translation.
508 2017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
510 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
512 2017-01-13 Yao Qi <yao.qi@linaro.org>
514 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
515 if FETCH_DATA returns 0.
516 (m68k_scan_mask): Likewise.
517 (print_insn_m68k): Update code to handle -1 return value.
519 2017-01-13 Yao Qi <yao.qi@linaro.org>
521 * m68k-dis.c (enum print_insn_arg_error): New.
522 (NEXTBYTE): Replace -3 with
523 PRINT_INSN_ARG_MEMORY_ERROR.
524 (NEXTULONG): Likewise.
525 (NEXTSINGLE): Likewise.
526 (NEXTDOUBLE): Likewise.
527 (NEXTDOUBLE): Likewise.
528 (NEXTPACKED): Likewise.
529 (FETCH_ARG): Likewise.
530 (FETCH_DATA): Update comments.
531 (print_insn_arg): Update comments. Replace magic numbers with
533 (match_insn_m68k): Likewise.
535 2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
537 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
538 * i386-dis-evex.h (evex_table): Updated.
539 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
540 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
541 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
542 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
543 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
544 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
545 * i386-init.h: Regenerate.
548 2017-01-12 Yao Qi <yao.qi@linaro.org>
550 * msp430-dis.c (msp430_singleoperand): Return -1 if
551 msp430dis_opcode_signed returns false.
552 (msp430_doubleoperand): Likewise.
553 (msp430_branchinstr): Return -1 if
554 msp430dis_opcode_unsigned returns false.
555 (msp430x_calla_instr): Likewise.
556 (print_insn_msp430): Likewise.
558 2017-01-05 Nick Clifton <nickc@redhat.com>
561 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
562 could not be matched.
563 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
566 2017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
568 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
569 (aarch64_opcode_table): Use RCPC_INSN.
571 2017-01-03 Kito Cheng <kito.cheng@gmail.com>
573 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
575 * riscv-opcodes/all-opcodes: Likewise.
577 2017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
579 * riscv-dis.c (print_insn_args): Add fall through comment.
581 2017-01-03 Nick Clifton <nickc@redhat.com>
583 * po/sr.po: New Serbian translation.
584 * configure.ac (ALL_LINGUAS): Add sr.
585 * configure: Regenerate.
587 2017-01-02 Alan Modra <amodra@gmail.com>
589 * epiphany-desc.h: Regenerate.
590 * epiphany-opc.h: Regenerate.
591 * fr30-desc.h: Regenerate.
592 * fr30-opc.h: Regenerate.
593 * frv-desc.h: Regenerate.
594 * frv-opc.h: Regenerate.
595 * ip2k-desc.h: Regenerate.
596 * ip2k-opc.h: Regenerate.
597 * iq2000-desc.h: Regenerate.
598 * iq2000-opc.h: Regenerate.
599 * lm32-desc.h: Regenerate.
600 * lm32-opc.h: Regenerate.
601 * m32c-desc.h: Regenerate.
602 * m32c-opc.h: Regenerate.
603 * m32r-desc.h: Regenerate.
604 * m32r-opc.h: Regenerate.
605 * mep-desc.h: Regenerate.
606 * mep-opc.h: Regenerate.
607 * mt-desc.h: Regenerate.
608 * mt-opc.h: Regenerate.
609 * or1k-desc.h: Regenerate.
610 * or1k-opc.h: Regenerate.
611 * xc16x-desc.h: Regenerate.
612 * xc16x-opc.h: Regenerate.
613 * xstormy16-desc.h: Regenerate.
614 * xstormy16-opc.h: Regenerate.
616 2017-01-02 Alan Modra <amodra@gmail.com>
618 Update year range in copyright notice of all files.
620 For older changes see ChangeLog-2016
622 Copyright (C) 2017 Free Software Foundation, Inc.
624 Copying and distribution of this file, with or without modification,
625 are permitted in any medium without royalty provided the copyright
626 notice and this notice are preserved.
632 version-control: never