1 /* Instruction printing code for the ARC.
2 Copyright (C) 1994-2014 Free Software Foundation, Inc.
3 Contributed by Doug Evans (dje@cygnus.com).
5 This file is part of libopcodes.
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
23 #include "libiberty.h"
25 #include "opcode/arc.h"
38 /* Classification of the opcodes for the decoder to print
46 /* All branches other than JC. */
49 /* All loads other than immediate
55 /* All single operand instructions. */
56 CLASS_A4_OP3_SUBOPC3F
,
60 #define BIT(word,n) ((word) & (1 << n))
61 #define BITS(word,s,e) (((word) >> s) & ((1 << (e + 1 - s)) - 1))
62 #define OPCODE(word) (BITS ((word), 27, 31))
63 #define FIELDA(word) (BITS ((word), 21, 26))
64 #define FIELDB(word) (BITS ((word), 15, 20))
65 #define FIELDC(word) (BITS ((word), 9, 14))
67 /* FIELD D is signed. */
68 #define FIELDD(word) ((BITS ((word), 0, 8) ^ 0x100) - 0x100)
70 #define PUT_NEXT_WORD_IN(a) \
73 if (is_limm == 1 && !NEXT_WORD (1)) \
74 mwerror (state, _("Illegal limm reference in last instruction!\n")); \
75 a = state->words[1]; \
79 #define CHECK_FLAG_COND_NULLIFY() \
84 flag = BIT (state->words[0], 8); \
85 state->nullifyMode = BITS (state->words[0], 5, 6); \
86 cond = BITS (state->words[0], 0, 4); \
91 #define CHECK_COND() \
95 cond = BITS (state->words[0], 0, 4); \
99 #define CHECK_FIELD(field) \
106 PUT_NEXT_WORD_IN (field); \
107 limm_value = field; \
109 else if (field > 60) \
113 flag = (field == 61); \
114 field = FIELDD (state->words[0]); \
119 #define CHECK_FIELD_A() \
122 fieldA = FIELDA (state->words[0]); \
131 #define CHECK_FIELD_B() \
134 fieldB = FIELDB (state->words[0]); \
135 CHECK_FIELD (fieldB); \
139 #define CHECK_FIELD_C() \
142 fieldC = FIELDC (state->words[0]); \
143 CHECK_FIELD (fieldC); \
147 #define IS_SMALL(x) (((field##x) < 256) && ((field##x) > -257))
148 #define IS_REG(x) (field##x##isReg)
149 #define WRITE_FORMAT_LB_Rx_RB(x) WRITE_FORMAT (x, "[","]","","")
150 #define WRITE_FORMAT_x_COMMA_LB(x) WRITE_FORMAT (x, "",",[","",",[")
151 #define WRITE_FORMAT_COMMA_x_RB(x) WRITE_FORMAT (x, ",","]",",","]")
152 #define WRITE_FORMAT_x_RB(x) WRITE_FORMAT (x, "","]","","]")
153 #define WRITE_FORMAT_COMMA_x(x) WRITE_FORMAT (x, ",","",",","")
154 #define WRITE_FORMAT_x_COMMA(x) WRITE_FORMAT (x, "",",","",",")
155 #define WRITE_FORMAT_x(x) WRITE_FORMAT (x, "","","","")
156 #define WRITE_FORMAT(x,cb1,ca1,cb,ca) strcat (formatString, \
157 (IS_REG (x) ? cb1"%r"ca1 : \
158 usesAuxReg ? cb"%a"ca : \
159 IS_SMALL (x) ? cb"%d"ca : cb"%h"ca))
160 #define WRITE_FORMAT_RB() strcat (formatString, "]")
161 #define WRITE_COMMENT(str) (state->comm[state->commNum++] = (str))
162 #define WRITE_NOP_COMMENT() if (!fieldAisReg && !flag) WRITE_COMMENT ("nop");
164 #define NEXT_WORD(x) (offset += 4, state->words[x])
166 #define add_target(x) (state->targets[state->tcnt++] = (x))
168 static char comment_prefix
[] = "\t; ";
171 core_reg_name (struct arcDisState
* state
, int val
)
173 if (state
->coreRegName
)
174 return (*state
->coreRegName
)(state
->_this
, val
);
179 aux_reg_name (struct arcDisState
* state
, int val
)
181 if (state
->auxRegName
)
182 return (*state
->auxRegName
)(state
->_this
, val
);
187 cond_code_name (struct arcDisState
* state
, int val
)
189 if (state
->condCodeName
)
190 return (*state
->condCodeName
)(state
->_this
, val
);
195 instruction_name (struct arcDisState
* state
,
201 return (*state
->instName
)(state
->_this
, op1
, op2
, flags
);
206 mwerror (struct arcDisState
* state
, const char * msg
)
209 (*state
->err
)(state
->_this
, (msg
));
213 post_address (struct arcDisState
* state
, int addr
)
215 static char id
[3 * ARRAY_SIZE (state
->addresses
)];
216 int j
, i
= state
->acnt
;
218 if (i
< ((int) ARRAY_SIZE (state
->addresses
)))
220 state
->addresses
[i
] = addr
;
233 arc_sprintf (struct arcDisState
*state
, char *buf
, const char *format
, ...)
237 int size
, leading_zero
, regMap
[2];
240 va_start (ap
, format
);
252 goto DOCOMM
; /* (return) */
276 leading_zero
= 1; /* e.g. %08x */
277 while (*p
>= '0' && *p
<= '9')
279 size
= size
* 10 + *p
- '0';
284 #define inc_bp() bp = bp + strlen (bp)
288 unsigned u
= va_arg (ap
, int);
290 /* Hex. We can change the format to 0x%08x in
291 one place, here, if we wish.
292 We add underscores for easy reading. */
294 sprintf (bp
, "0x%x_%04x", u
>> 16, u
& 0xffff);
296 sprintf (bp
, "0x%x", u
);
302 int val
= va_arg (ap
, int);
306 sprintf (bp
, "%0*x", size
, val
);
308 sprintf (bp
, "%*x", size
, val
);
310 sprintf (bp
, "%x", val
);
316 int val
= va_arg (ap
, int);
319 sprintf (bp
, "%*d", size
, val
);
321 sprintf (bp
, "%d", val
);
328 int val
= va_arg (ap
, int);
330 #define REG2NAME(num, name) case num: sprintf (bp, ""name); \
331 regMap[(num < 32) ? 0 : 1] |= 1 << (num - ((num < 32) ? 0 : 32)); break;
338 REG2NAME (29, "ilink1");
339 REG2NAME (30, "ilink2");
340 REG2NAME (31, "blink");
341 REG2NAME (60, "lp_count");
346 ext
= core_reg_name (state
, val
);
348 sprintf (bp
, "%s", ext
);
350 sprintf (bp
,"r%d",val
);
360 int val
= va_arg (ap
, int);
362 #define AUXREG2NAME(num, name) case num: sprintf (bp,name); break;
366 AUXREG2NAME (0x0, "status");
367 AUXREG2NAME (0x1, "semaphore");
368 AUXREG2NAME (0x2, "lp_start");
369 AUXREG2NAME (0x3, "lp_end");
370 AUXREG2NAME (0x4, "identity");
371 AUXREG2NAME (0x5, "debug");
376 ext
= aux_reg_name (state
, val
);
378 sprintf (bp
, "%s", ext
);
380 arc_sprintf (state
, bp
, "%h", val
);
390 sprintf (bp
, "%s", va_arg (ap
, char *));
396 fprintf (stderr
, "?? format %c\n", p
[-1]);
406 write_comments_(struct arcDisState
* state
,
411 if (state
->commentBuffer
!= 0)
417 const char *name
= post_address (state
, limm_value
+ shimm
);
420 WRITE_COMMENT (name
);
422 for (i
= 0; i
< state
->commNum
; i
++)
425 strcpy (state
->commentBuffer
, comment_prefix
);
427 strcat (state
->commentBuffer
, ", ");
428 strcat (state
->commentBuffer
, state
->comm
[i
]);
433 #define write_comments2(x) write_comments_ (state, x, is_limm, limm_value)
434 #define write_comments() write_comments2 (0)
436 static const char *condName
[] =
439 "" , "z" , "nz" , "p" , "n" , "c" , "nc" , "v" ,
440 "nv" , "gt" , "ge" , "lt" , "le" , "hi" , "ls" , "pnz"
444 write_instr_name_(struct arcDisState
* state
,
445 const char * instrName
,
447 int condCodeIsPartOfName
,
453 strcpy (state
->instrBuffer
, instrName
);
459 if (!condCodeIsPartOfName
)
460 strcat (state
->instrBuffer
, ".");
465 cc
= cond_code_name (state
, cond
);
470 strcat (state
->instrBuffer
, cc
);
474 strcat (state
->instrBuffer
, ".f");
476 switch (state
->nullifyMode
)
479 strcat (state
->instrBuffer
, ".d");
481 case BR_exec_when_jump
:
482 strcat (state
->instrBuffer
, ".jd");
487 strcat (state
->instrBuffer
, ".x");
490 strcat (state
->instrBuffer
, ".a");
493 strcat (state
->instrBuffer
, ".di");
496 #define write_instr_name() \
499 write_instr_name_(state, instrName,cond, condCodeIsPartOfName, \
500 flag, signExtend, addrWriteBack, directMem); \
501 formatString[0] = '\0'; \
507 op_LD0
= 0, op_LD1
= 1, op_ST
= 2, op_3
= 3,
508 op_BC
= 4, op_BLC
= 5, op_LPC
= 6, op_JC
= 7,
509 op_ADD
= 8, op_ADC
= 9, op_SUB
= 10, op_SBC
= 11,
510 op_AND
= 12, op_OR
= 13, op_BIC
= 14, op_XOR
= 15
513 extern disassemble_info tm_print_insn_info
;
516 dsmOneArcInst (bfd_vma addr
, struct arcDisState
* state
)
518 int condCodeIsPartOfName
= 0;
519 a4_decoding_class decodingClass
;
520 const char * instrName
;
534 int addrWriteBack
= 0;
541 char formatString
[60];
543 state
->instructionLen
= 4;
544 state
->nullifyMode
= BR_exec_when_no_jump
;
548 state
->_mem_load
= 0;
549 state
->_ea_present
= 0;
550 state
->_load_len
= 0;
551 state
->ea_reg1
= no_reg
;
552 state
->ea_reg2
= no_reg
;
558 state
->_opcode
= OPCODE (state
->words
[0]);
560 decodingClass
= CLASS_A4_ARITH
; /* default! */
562 condCodeIsPartOfName
=0;
566 state
->flow
= noflow
;
569 if (state
->commentBuffer
)
570 state
->commentBuffer
[0] = '\0';
572 switch (state
->_opcode
)
575 switch (BITS (state
->words
[0],1,2))
579 state
->_load_len
= 4;
583 state
->_load_len
= 1;
587 state
->_load_len
= 2;
590 instrName
= "??? (0[3])";
591 state
->flow
= invalid_instr
;
594 decodingClass
= CLASS_A4_LD0
;
598 if (BIT (state
->words
[0],13))
601 decodingClass
= CLASS_A4_LR
;
605 switch (BITS (state
->words
[0], 10, 11))
609 state
->_load_len
= 4;
613 state
->_load_len
= 1;
617 state
->_load_len
= 2;
620 instrName
= "??? (1[3])";
621 state
->flow
= invalid_instr
;
624 decodingClass
= CLASS_A4_LD1
;
629 if (BIT (state
->words
[0], 25))
632 decodingClass
= CLASS_A4_SR
;
636 switch (BITS (state
->words
[0], 22, 23))
648 instrName
= "??? (2[3])";
649 state
->flow
= invalid_instr
;
652 decodingClass
= CLASS_A4_ST
;
657 decodingClass
= CLASS_A4_OP3_GENERAL
; /* default for opcode 3... */
658 switch (FIELDC (state
->words
[0]))
662 decodingClass
= CLASS_A4_FLAG
;
690 decodingClass
= CLASS_A4_OP3_SUBOPC3F
;
691 switch (FIELDD (state
->words
[0]))
704 state
->flow
=invalid_instr
;
710 /* ARC Extension Library Instructions
711 NOTE: We assume that extension codes are these instrs. */
713 instrName
= instruction_name (state
,
715 FIELDC (state
->words
[0]),
720 state
->flow
= invalid_instr
;
722 if (flags
& IGNORE_FIRST_OPD
)
739 if (BITS (state
->words
[0],9,9))
750 condCodeIsPartOfName
= 1;
751 decodingClass
= ((state
->_opcode
== op_JC
) ? CLASS_A4_JC
: CLASS_A4_BRANCH
);
758 repeatsOp
= (FIELDC (state
->words
[0]) == FIELDB (state
->words
[0]));
760 switch (state
->_opcode
)
763 instrName
= (repeatsOp
? "asl" : "add");
766 instrName
= (repeatsOp
? "rlc" : "adc");
769 instrName
= (repeatsOp
? "mov" : "and");
774 case op_SUB
: instrName
= "sub";
776 case op_SBC
: instrName
= "sbc";
778 case op_OR
: instrName
= "or";
780 case op_BIC
: instrName
= "bic";
784 if (state
->words
[0] == 0x7fffffff)
786 /* NOP encoded as xor -1, -1, -1. */
788 decodingClass
= CLASS_A4_OP3_SUBOPC3F
;
795 instrName
= instruction_name (state
,state
->_opcode
,0,&flags
);
796 /* if (instrName) printf("FLAGS=0x%x\n", flags); */
800 state
->flow
=invalid_instr
;
802 if (flags
& IGNORE_FIRST_OPD
)
807 fieldAisReg
= fieldBisReg
= fieldCisReg
= 1; /* Assume regs for now. */
808 flag
= cond
= is_shimm
= is_limm
= 0;
809 state
->nullifyMode
= BR_exec_when_no_jump
; /* 0 */
810 signExtend
= addrWriteBack
= directMem
= 0;
813 switch (decodingClass
)
820 CHECK_FLAG_COND_NULLIFY ();
826 WRITE_FORMAT_COMMA_x (B
);
828 WRITE_FORMAT_COMMA_x (C
);
829 WRITE_NOP_COMMENT ();
830 arc_sprintf (state
, state
->operandBuffer
, formatString
,
831 fieldA
, fieldB
, fieldC
);
837 WRITE_FORMAT_COMMA_x (C
);
838 arc_sprintf (state
, state
->operandBuffer
, formatString
,
844 case CLASS_A4_OP3_GENERAL
:
847 CHECK_FLAG_COND_NULLIFY ();
853 WRITE_FORMAT_COMMA_x (B
);
854 WRITE_NOP_COMMENT ();
855 arc_sprintf (state
, state
->operandBuffer
, formatString
,
861 arc_sprintf (state
, state
->operandBuffer
, formatString
, fieldB
);
868 CHECK_FLAG_COND_NULLIFY ();
869 flag
= 0; /* This is the FLAG instruction -- it's redundant. */
873 arc_sprintf (state
, state
->operandBuffer
, formatString
, fieldB
);
877 case CLASS_A4_BRANCH
:
878 fieldA
= BITS (state
->words
[0],7,26) << 2;
879 fieldA
= (fieldA
<< 10) >> 10; /* Make it signed. */
881 CHECK_FLAG_COND_NULLIFY ();
885 /* This address could be a label we know. Convert it. */
886 if (state
->_opcode
!= op_LPC
/* LP */)
888 add_target (fieldA
); /* For debugger. */
889 state
->flow
= state
->_opcode
== op_BLC
/* BL */
892 /* indirect calls are achieved by "lr blink,[status];
893 lr dest<- func addr; j [dest]" */
896 strcat (formatString
, "%s"); /* Address/label name. */
897 arc_sprintf (state
, state
->operandBuffer
, formatString
,
898 post_address (state
, fieldA
));
903 /* For op_JC -- jump to address specified.
904 Also covers jump and link--bit 9 of the instr. word
905 selects whether linked, thus "is_linked" is set above. */
908 CHECK_FLAG_COND_NULLIFY ();
913 fieldA
= (fieldB
>> 25) & 0x7F; /* Flags. */
914 fieldB
= (fieldB
& 0xFFFFFF) << 2;
915 state
->flow
= is_linked
? direct_call
: direct_jump
;
917 /* Screwy JLcc requires .jd mode to execute correctly
918 but we pretend it is .nd (no delay slot). */
919 if (is_linked
&& state
->nullifyMode
== BR_exec_when_jump
)
920 state
->nullifyMode
= BR_exec_when_no_jump
;
924 state
->flow
= is_linked
? indirect_call
: indirect_jump
;
925 /* We should also treat this as indirect call if NOT linked
926 but the preceding instruction was a "lr blink,[status]"
927 and we have a delay slot with "add blink,blink,2".
928 For now we can't detect such. */
929 state
->register_for_indirect_jump
= fieldB
;
933 strcat (formatString
,
934 IS_REG (B
) ? "[%r]" : "%s"); /* Address/label name. */
938 WRITE_FORMAT_COMMA_x (A
);
941 arc_sprintf (state
, state
->operandBuffer
, formatString
, fieldB
, fieldA
);
943 arc_sprintf (state
, state
->operandBuffer
, formatString
,
944 post_address (state
, fieldB
), fieldA
);
950 B and C can be regs, or one (both?) can be limm. */
955 printf ("5:b reg %d %d c reg %d %d \n",
956 fieldBisReg
,fieldB
,fieldCisReg
,fieldC
);
958 state
->_ea_present
= 1;
960 state
->ea_reg1
= fieldB
;
962 state
->_offset
+= fieldB
;
964 state
->ea_reg2
= fieldC
;
966 state
->_offset
+= fieldC
;
967 state
->_mem_load
= 1;
969 directMem
= BIT (state
->words
[0], 5);
970 addrWriteBack
= BIT (state
->words
[0], 3);
971 signExtend
= BIT (state
->words
[0], 0);
974 WRITE_FORMAT_x_COMMA_LB(A
);
975 if (fieldBisReg
|| fieldB
!= 0)
976 WRITE_FORMAT_x_COMMA (B
);
980 WRITE_FORMAT_x_RB (C
);
981 arc_sprintf (state
, state
->operandBuffer
, formatString
,
982 fieldA
, fieldB
, fieldC
);
987 /* LD instruction. */
990 fieldC
= FIELDD (state
->words
[0]);
993 printf ("6:b reg %d %d c 0x%x \n",
994 fieldBisReg
, fieldB
, fieldC
);
995 state
->_ea_present
= 1;
996 state
->_offset
= fieldC
;
997 state
->_mem_load
= 1;
999 state
->ea_reg1
= fieldB
;
1000 /* Field B is either a shimm (same as fieldC) or limm (different!)
1001 Say ea is not present, so only one of us will do the name lookup. */
1003 state
->_offset
+= fieldB
, state
->_ea_present
= 0;
1005 directMem
= BIT (state
->words
[0],14);
1006 addrWriteBack
= BIT (state
->words
[0],12);
1007 signExtend
= BIT (state
->words
[0],9);
1009 write_instr_name ();
1010 WRITE_FORMAT_x_COMMA_LB (A
);
1013 fieldB
= state
->_offset
;
1014 WRITE_FORMAT_x_RB (B
);
1019 if (fieldC
!= 0 && !BIT (state
->words
[0],13))
1022 WRITE_FORMAT_COMMA_x_RB (C
);
1027 arc_sprintf (state
, state
->operandBuffer
, formatString
,
1028 fieldA
, fieldB
, fieldC
);
1033 /* ST instruction. */
1036 fieldA
= FIELDD(state
->words
[0]); /* shimm */
1039 if (dbg
) printf("7:b reg %d %x off %x\n",
1040 fieldBisReg
,fieldB
,fieldA
);
1041 state
->_ea_present
= 1;
1042 state
->_offset
= fieldA
;
1044 state
->ea_reg1
= fieldB
;
1045 /* Field B is either a shimm (same as fieldA) or limm (different!)
1046 Say ea is not present, so only one of us will do the name lookup.
1047 (for is_limm we do the name translation here). */
1049 state
->_offset
+= fieldB
, state
->_ea_present
= 0;
1051 directMem
= BIT (state
->words
[0], 26);
1052 addrWriteBack
= BIT (state
->words
[0], 24);
1054 write_instr_name ();
1055 WRITE_FORMAT_x_COMMA_LB(C
);
1059 fieldB
= state
->_offset
;
1060 WRITE_FORMAT_x_RB (B
);
1065 if (fieldBisReg
&& fieldA
!= 0)
1068 WRITE_FORMAT_COMMA_x_RB(A
);
1073 arc_sprintf (state
, state
->operandBuffer
, formatString
,
1074 fieldC
, fieldB
, fieldA
);
1075 write_comments2 (fieldA
);
1079 /* SR instruction */
1083 write_instr_name ();
1084 WRITE_FORMAT_x_COMMA_LB(C
);
1085 /* Try to print B as an aux reg if it is not a core reg. */
1089 arc_sprintf (state
, state
->operandBuffer
, formatString
, fieldC
, fieldB
);
1093 case CLASS_A4_OP3_SUBOPC3F
:
1094 write_instr_name ();
1095 state
->operandBuffer
[0] = '\0';
1099 /* LR instruction */
1103 write_instr_name ();
1104 WRITE_FORMAT_x_COMMA_LB (A
);
1105 /* Try to print B as an aux reg if it is not a core reg. */
1109 arc_sprintf (state
, state
->operandBuffer
, formatString
, fieldA
, fieldB
);
1114 mwerror (state
, "Bad decoding class in ARC disassembler");
1118 state
->_cond
= cond
;
1119 return state
->instructionLen
= offset
;
1123 /* Returns the name the user specified core extension register. */
1126 _coreRegName(void * arg ATTRIBUTE_UNUSED
, int regval
)
1128 return arcExtMap_coreRegName (regval
);
1131 /* Returns the name the user specified AUX extension register. */
1134 _auxRegName(void *_this ATTRIBUTE_UNUSED
, int regval
)
1136 return arcExtMap_auxRegName(regval
);
1139 /* Returns the name the user specified condition code name. */
1142 _condCodeName(void *_this ATTRIBUTE_UNUSED
, int regval
)
1144 return arcExtMap_condCodeName(regval
);
1147 /* Returns the name the user specified extension instruction. */
1150 _instName (void *_this ATTRIBUTE_UNUSED
, int majop
, int minop
, int *flags
)
1152 return arcExtMap_instName(majop
, minop
, flags
);
1155 /* Decode an instruction returning the size of the instruction
1156 in bytes or zero if unrecognized. */
1159 decodeInstr (bfd_vma address
, /* Address of this instruction. */
1160 disassemble_info
* info
)
1164 struct arcDisState s
; /* ARC Disassembler state. */
1165 void *stream
= info
->stream
; /* Output stream. */
1166 fprintf_ftype func
= info
->fprintf_func
;
1168 memset (&s
, 0, sizeof(struct arcDisState
));
1170 /* read first instruction */
1171 status
= (*info
->read_memory_func
) (address
, buffer
, 4, info
);
1174 (*info
->memory_error_func
) (status
, address
, info
);
1177 if (info
->endian
== BFD_ENDIAN_LITTLE
)
1178 s
.words
[0] = bfd_getl32(buffer
);
1180 s
.words
[0] = bfd_getb32(buffer
);
1181 /* Always read second word in case of limm. */
1183 /* We ignore the result since last insn may not have a limm. */
1184 status
= (*info
->read_memory_func
) (address
+ 4, buffer
, 4, info
);
1185 if (info
->endian
== BFD_ENDIAN_LITTLE
)
1186 s
.words
[1] = bfd_getl32(buffer
);
1188 s
.words
[1] = bfd_getb32(buffer
);
1191 s
.coreRegName
= _coreRegName
;
1192 s
.auxRegName
= _auxRegName
;
1193 s
.condCodeName
= _condCodeName
;
1194 s
.instName
= _instName
;
1197 dsmOneArcInst (address
, & s
);
1199 /* Display the disassembly instruction. */
1200 (*func
) (stream
, "%08lx ", s
.words
[0]);
1201 (*func
) (stream
, " ");
1202 (*func
) (stream
, "%-10s ", s
.instrBuffer
);
1204 if (__TRANSLATION_REQUIRED (s
))
1206 bfd_vma addr
= s
.addresses
[s
.operandBuffer
[1] - '0'];
1208 (*info
->print_address_func
) ((bfd_vma
) addr
, info
);
1209 (*func
) (stream
, "\n");
1212 (*func
) (stream
, "%s",s
.operandBuffer
);
1214 return s
.instructionLen
;
1217 /* Return the print_insn function to use.
1218 Side effect: load (possibly empty) extension section */
1221 arc_get_disassembler (void *ptr
)
1224 build_ARC_extmap ((struct bfd
*) ptr
);