1 /* ARC Auxiliary register definitions
2 Copyright (C) 2015-2016 Free Software Foundation, Inc.
4 Contributed by Claudiu Zissulescu (claziss@synopsys.com)
6 This file is part of libopcodes.
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software Foundation,
20 Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
22 DEF (0x0, NONE
, STATUS
)
23 DEF (0x1, NONE
, SEMAPHORE
)
24 DEF (0x2, NONE
, LP_START
)
25 DEF (0x3, NONE
, LP_END
)
26 DEF (0x4, NONE
, IDENTITY
)
27 DEF (0x5, NONE
, DEBUG
)
32 DEF (0xA, NONE
, STATUS32
)
33 DEF (0xB, NONE
, STATUS32_L1
)
34 DEF (0xC, NONE
, STATUS32_L2
)
35 DEF (0xF, NONE
, BPU_FLUSH
)
36 DEF (0x10, NONE
, IVIC
)
37 DEF (0x10, NONE
, IC_IVIC
)
38 DEF (0x11, NONE
, CHE_MODE
)
39 DEF (0x11, NONE
, IC_CTRL
)
40 DEF (0x12, NONE
, MULHI
)
41 DEF (0x13, NONE
, LOCKLINE
)
42 DEF (0x13, NONE
, IC_LIL
)
43 DEF (0x14, NONE
, DMC_CODE_RAM
)
44 DEF (0x15, NONE
, TAG_ADDR_MASK
)
45 DEF (0x16, NONE
, TAG_DATA_MASK
)
46 DEF (0x17, NONE
, LINE_LENGTH_MASK
)
47 DEF (0x18, NONE
, AUX_LDST_RAM
)
48 DEF (0x18, NONE
, AUX_DCCM
)
49 DEF (0x19, NONE
, UNLOCKLINE
)
50 DEF (0x19, NONE
, IC_IVIL
)
51 DEF (0x1A, NONE
, IC_RAM_ADDRESS
)
52 DEF (0x1B, NONE
, IC_TAG
)
53 DEF (0x1C, NONE
, IC_WP
)
54 DEF (0x1D, NONE
, IC_DATA
)
55 DEF (0x20, NONE
, SRAM_SEQ
)
56 DEF (0x21, NONE
, COUNT0
)
57 DEF (0x22, NONE
, CONTROL0
)
58 DEF (0x23, NONE
, LIMIT0
)
59 DEF (0x24, NONE
, PCPORT
)
60 DEF (0x25, NONE
, INT_VECTOR_BASE
)
61 DEF (0x26, NONE
, AUX_VBFDW_MODE
)
62 DEF (0x26, NONE
, JLI_BASE
)
63 DEF (0x27, NONE
, AUX_VBFDW_BM0
)
64 DEF (0x28, NONE
, AUX_VBFDW_BM1
)
65 DEF (0x29, NONE
, AUX_VBFDW_ACCU
)
66 DEF (0x2A, NONE
, AUX_VBFDW_OFST
)
67 DEF (0x2B, NONE
, AUX_VBFDW_INTSTAT
)
68 DEF (0x2C, NONE
, AUX_XMAC0_24
)
69 DEF (0x2D, NONE
, AUX_XMAC1_24
)
70 DEF (0x2E, NONE
, AUX_XMAC2_24
)
71 DEF (0x2F, NONE
, AUX_FBF_STORE_16
)
74 DEF (0x32, NONE
, AUX_CRC_POLY
)
75 DEF (0x33, NONE
, AUX_CRC_MODE
)
80 DEF (0x38, NONE
, XYCONFIG
)
81 DEF (0x39, NONE
, SCRATCH_A
)
82 DEF (0x3A, NONE
, BURSTSYS
)
83 DEF (0x3A, NONE
, TSCH
)
84 DEF (0x3B, NONE
, BURSTXYM
)
85 DEF (0x3C, NONE
, BURSTSZ
)
86 DEF (0x3D, NONE
, BURSTVAL
)
87 DEF (0x40, NONE
, XTP_NEWVAL
)
88 DEF (0x41, NONE
, AUX_MACMODE
)
89 DEF (0x42, NONE
, LSP_NEWVAL
)
90 DEF (0x43, NONE
, AUX_IRQ_LV12
)
91 DEF (0x44, NONE
, AUX_XMAC0
)
92 DEF (0x45, NONE
, AUX_XMAC1
)
93 DEF (0x46, NONE
, AUX_XMAC2
)
94 DEF (0x47, NONE
, DC_IVDC
)
95 DEF (0x48, NONE
, DC_CTRL
)
96 DEF (0x49, NONE
, DC_LDL
)
97 DEF (0x4A, NONE
, DC_IVDL
)
98 DEF (0x4B, NONE
, DC_FLSH
)
99 DEF (0x4C, NONE
, DC_FLDL
)
100 DEF (0x50, NONE
, HEXDATA
)
101 DEF (0x51, NONE
, HEXCTRL
)
102 DEF (0x52, NONE
, LED
)
103 DEF (0x56, NONE
, DILSTAT
)
104 DEF (0x57, NONE
, SWSTAT
)
105 DEF (0x58, NONE
, DC_RAM_ADDR
)
106 DEF (0x59, NONE
, DC_TAG
)
107 DEF (0x5A, NONE
, DC_WP
)
108 DEF (0x5B, NONE
, DC_DATA
)
109 DEF (0x61, NONE
, DCCM_BASE_BUILD
)
110 DEF (0x62, NONE
, CRC_BUILD
)
111 DEF (0x63, NONE
, BTA_LINK_BUILD
)
112 DEF (0x64, NONE
, VBFDW_BUILD
)
113 DEF (0x65, NONE
, EA_BUILD
)
114 DEF (0x66, NONE
, DATASPACE
)
115 DEF (0x67, NONE
, MEMSUBSYS
)
116 DEF (0x68, NONE
, VECBASE_AC_BUILD
)
117 DEF (0x69, NONE
, P_BASE_ADDR
)
118 DEF (0x6A, NONE
, DATA_UNCACHED_BUILD
)
119 DEF (0x6B, NONE
, FP_BUILD
)
120 DEF (0x6C, NONE
, DPFP_BUILD
)
121 DEF (0x6D, NONE
, MPU_BUILD
)
122 DEF (0x6E, NONE
, RF_BUILD
)
123 DEF (0x6F, NONE
, MMU_BUILD
)
124 DEF (0x70, NONE
, AA2_BUILD
)
125 DEF (0x71, NONE
, VECBASE_BUILD
)
126 DEF (0x72, NONE
, D_CACHE_BUILD
)
127 DEF (0x73, NONE
, MADI_BUILD
)
128 DEF (0x74, NONE
, DCCM_BUILD
)
129 DEF (0x75, NONE
, TIMER_BUILD
)
130 DEF (0x76, NONE
, AP_BUILD
)
131 DEF (0x77, NONE
, I_CACHE_BUILD
)
132 DEF (0x78, NONE
, ICCM_BUILD
)
133 DEF (0x79, NONE
, DSPRAM_BUILD
)
134 DEF (0x7A, NONE
, MAC_BUILD
)
135 DEF (0x7B, NONE
, MULTIPLY_BUILD
)
136 DEF (0x7C, NONE
, SWAP_BUILD
)
137 DEF (0x7D, NONE
, NORM_BUILD
)
138 DEF (0x7E, NONE
, MINMAX_BUILD
)
139 DEF (0x7F, NONE
, BARREL_BUILD
)
140 DEF (0x80, NONE
, AX0
)
141 DEF (0x81, NONE
, AX1
)
142 DEF (0x82, NONE
, AX2
)
143 DEF (0x83, NONE
, AX3
)
144 DEF (0x84, NONE
, AY0
)
145 DEF (0x85, NONE
, AY1
)
146 DEF (0x86, NONE
, AY2
)
147 DEF (0x87, NONE
, AY3
)
148 DEF (0x88, NONE
, MX00
)
149 DEF (0x89, NONE
, MX01
)
150 DEF (0x8A, NONE
, MX10
)
151 DEF (0x8B, NONE
, MX11
)
152 DEF (0x8C, NONE
, MX20
)
153 DEF (0x8D, NONE
, MX21
)
154 DEF (0x8E, NONE
, MX30
)
155 DEF (0x8F, NONE
, MX31
)
156 DEF (0x90, NONE
, MY00
)
157 DEF (0x91, NONE
, MY01
)
158 DEF (0x92, NONE
, MY10
)
159 DEF (0x93, NONE
, MY11
)
160 DEF (0x94, NONE
, MY20
)
161 DEF (0x95, NONE
, MY21
)
162 DEF (0x96, NONE
, MY30
)
163 DEF (0x97, NONE
, MY31
)
164 DEF (0x98, NONE
, XYCONFIG
)
165 DEF (0x99, NONE
, BURSTSYS
)
166 DEF (0x9A, NONE
, BURSTXYM
)
167 DEF (0x9B, NONE
, BURSTSZ
)
168 DEF (0x9C, NONE
, BURSTVAL
)
169 DEF (0x9D, NONE
, XYLSBASEX
)
170 DEF (0x9E, NONE
, XYLSBASEY
)
171 DEF (0x9F, NONE
, AUX_XMACLW_H
)
172 DEF (0xA0, NONE
, AUX_XMACLW_L
)
173 DEF (0xA1, NONE
, SE_CTRL
)
174 DEF (0xA2, NONE
, SE_STAT
)
175 DEF (0xA3, NONE
, SE_ERR
)
176 DEF (0xA4, NONE
, SE_EADR
)
177 DEF (0xA5, NONE
, SE_SPC
)
178 DEF (0xA6, NONE
, SDM_BASE
)
179 DEF (0xA7, NONE
, SCM_BASE
)
180 DEF (0xA8, NONE
, SE_DBG_CTRL
)
181 DEF (0xA9, NONE
, SE_DBG_DATA0
)
182 DEF (0xAA, NONE
, SE_DBG_DATA1
)
183 DEF (0xAB, NONE
, SE_DBG_DATA2
)
184 DEF (0xAC, NONE
, SE_DBG_DATA3
)
185 DEF (0xAD, NONE
, SE_WATCH
)
186 DEF (0xC0, NONE
, BPU_BUILD
)
187 DEF (0xC1, NONE
, ARC600_BUILD_CONFIG
)
188 DEF (0xC2, NONE
, ISA_CONFIG
)
189 DEF (0xF4, NONE
, HWP_BUILD
)
190 DEF (0xF5, NONE
, PCT_BUILD
)
191 DEF (0xF6, NONE
, CC_BUILD
)
192 DEF (0xF7, NONE
, PM_BCR
)
193 DEF (0xF8, NONE
, SCQ_SWITCH_BUILD
)
194 DEF (0xF9, NONE
, VRAPTOR_BUILD
)
195 DEF (0xFA, NONE
, DMA_CONFIG
)
196 DEF (0xFB, NONE
, SIMD_CONFIG
)
197 DEF (0xFC, NONE
, VLC_BUILD
)
198 DEF (0xFD, NONE
, SIMD_DMA_BUILD
)
199 DEF (0xFE, NONE
, IFETCH_QUEUE_BUILD
)
200 DEF (0xFF, NONE
, SMART_BUILD
)
201 DEF (0x100, NONE
, COUNT1
)
202 DEF (0x101, NONE
, CONTROL1
)
203 DEF (0x102, NONE
, LIMIT1
)
204 DEF (0x103, NONE
, TIMER_XX
)
205 DEF (0x120, NONE
, ARCANGEL_PERIPH_XX
)
206 DEF (0x140, NONE
, PERIPH_XX
)
207 DEF (0x200, NONE
, AUX_IRQ_LEV
)
208 DEF (0x201, NONE
, AUX_IRQ_HINT
)
209 DEF (0x202, NONE
, AUX_INTER_CORE_INTERRUPT
)
210 DEF (0x210, NONE
, AES_AUX_0
)
211 DEF (0x211, NONE
, AES_AUX_1
)
212 DEF (0x212, NONE
, AES_AUX_2
)
213 DEF (0x213, NONE
, AES_CRYPT_MODE
)
214 DEF (0x214, NONE
, AES_AUXS
)
215 DEF (0x215, NONE
, AES_AUXI
)
216 DEF (0x216, NONE
, AES_AUX_3
)
217 DEF (0x217, NONE
, AES_AUX_4
)
218 DEF (0x218, NONE
, ARITH_CTL_AUX
)
219 DEF (0x219, NONE
, DES_AUX
)
220 DEF (0x220, NONE
, AP_AMV0
)
221 DEF (0x221, NONE
, AP_AMM0
)
222 DEF (0x222, NONE
, AP_AC0
)
223 DEF (0x223, NONE
, AP_AMV1
)
224 DEF (0x224, NONE
, AP_AMM1
)
225 DEF (0x225, NONE
, AP_AC1
)
226 DEF (0x226, NONE
, AP_AMV2
)
227 DEF (0x227, NONE
, AP_AMM2
)
228 DEF (0x228, NONE
, AP_AC2
)
229 DEF (0x229, NONE
, AP_AMV3
)
230 DEF (0x22A, NONE
, AP_AMM3
)
231 DEF (0x22B, NONE
, AP_AC3
)
232 DEF (0x22C, NONE
, AP_AMV4
)
233 DEF (0x22D, NONE
, AP_AMM4
)
234 DEF (0x22E, NONE
, AP_AC4
)
235 DEF (0x22F, NONE
, AP_AMV5
)
236 DEF (0x230, NONE
, AP_AMM5
)
237 DEF (0x231, NONE
, AP_AC5
)
238 DEF (0x232, NONE
, AP_AMV6
)
239 DEF (0x233, NONE
, AP_AMM6
)
240 DEF (0x234, NONE
, AP_AC6
)
241 DEF (0x235, NONE
, AP_AMV7
)
242 DEF (0x236, NONE
, AP_AMM7
)
243 DEF (0x237, NONE
, AP_AC7
)
244 DEF (0x278, NONE
, PCT_CONTROL
)
245 DEF (0x279, NONE
, PCT_BANK
)
246 DEF (0x300, DPX
, FP_STATUS
)
247 DEF (0x301, DPX
, AUX_DPFP1L
)
248 DEF (0x301, DPX
, D1L
)
249 DEF (0x302, DPX
, AUX_DPFP1H
)
250 DEF (0x302, DPX
, D1H
)
251 DEF (0x302, DPA
, D1L
)
252 DEF (0x303, DPX
, AUX_DPFP2L
)
253 DEF (0x303, DPX
, D2L
)
254 DEF (0x303, DPA
, D1H
)
255 DEF (0x304, DPX
, AUX_DPFP2H
)
256 DEF (0x304, DPX
, D2H
)
257 DEF (0x304, DPA
, D2L
)
258 DEF (0x305, DPX
, DPFP_STATUS
)
259 DEF (0x305, DPA
, D2H
)
260 DEF (0x306, NONE
, RTT
)
261 DEF (0x400, NONE
, ERET
)
262 DEF (0x401, NONE
, ERBTA
)
263 DEF (0x402, NONE
, ERSTATUS
)
264 DEF (0x403, NONE
, ECR
)
265 DEF (0x404, NONE
, EFA
)
266 DEF (0x405, NONE
, TLBPD0
)
267 DEF (0x406, NONE
, TLBPD1
)
268 DEF (0x407, NONE
, TLBIndex
)
269 DEF (0x408, NONE
, TLBCommand
)
270 DEF (0x409, NONE
, PID
)
271 DEF (0x409, NONE
, MPUEN
)
272 DEF (0x40A, NONE
, ICAUSE1
)
273 DEF (0x40B, NONE
, ICAUSE2
)
274 DEF (0x40C, NONE
, AUX_IENABLE
)
275 DEF (0x40D, NONE
, AUX_ITRIGGER
)
276 DEF (0x410, NONE
, XPU
)
277 DEF (0x412, NONE
, BTA
)
278 DEF (0x413, NONE
, BTA_L1
)
279 DEF (0x414, NONE
, BTA_L2
)
280 DEF (0x415, NONE
, AUX_IRQ_PULSE_CANCEL
)
281 DEF (0x416, NONE
, AUX_IRQ_PENDING
)
282 DEF (0x418, NONE
, SCRATCH_DATA0
)
283 DEF (0x420, NONE
, MPUIC
)
284 DEF (0x421, NONE
, MPUFA
)
285 DEF (0x422, NONE
, MPURDB0
)
286 DEF (0x423, NONE
, MPURDP0
)
287 DEF (0x424, NONE
, MPURDB1
)
288 DEF (0x425, NONE
, MPURDP1
)
289 DEF (0x426, NONE
, MPURDB2
)
290 DEF (0x427, NONE
, MPURDP2
)
291 DEF (0x428, NONE
, MPURDB3
)
292 DEF (0x429, NONE
, MPURDP3
)
293 DEF (0x42A, NONE
, MPURDB4
)
294 DEF (0x42B, NONE
, MPURDP4
)
295 DEF (0x42C, NONE
, MPURDB5
)
296 DEF (0x42D, NONE
, MPURDP5
)
297 DEF (0x42E, NONE
, MPURDB6
)
298 DEF (0x42F, NONE
, MPURDP6
)
299 DEF (0x430, NONE
, MPURDB7
)
300 DEF (0x431, NONE
, MPURDP7
)
301 DEF (0x432, NONE
, MPURDB8
)
302 DEF (0x433, NONE
, MPURDP8
)
303 DEF (0x434, NONE
, MPURDB9
)
304 DEF (0x435, NONE
, MPURDP9
)
305 DEF (0x436, NONE
, MPURDB10
)
306 DEF (0x437, NONE
, MPURDP10
)
307 DEF (0x438, NONE
, MPURDB11
)
308 DEF (0x439, NONE
, MPURDP11
)
309 DEF (0x43A, NONE
, MPURDB12
)
310 DEF (0x43B, NONE
, MPURDP12
)
311 DEF (0x43C, NONE
, MPURDB13
)
312 DEF (0x43D, NONE
, MPURDP13
)
313 DEF (0x43E, NONE
, MPURDB14
)
314 DEF (0x43F, NONE
, MPURDP14
)
315 DEF (0x440, NONE
, MPURDB15
)
316 DEF (0x441, NONE
, MPURDP15
)
317 DEF (0x44F, NONE
, EIA_FLAGS
)
318 DEF (0x450, NONE
, PM_STATUS
)
319 DEF (0x451, NONE
, WAKE
)
320 DEF (0x452, NONE
, DVFS_PERFORMANCE
)
321 DEF (0x453, NONE
, PWR_CTRL
)
322 DEF (0x500, NONE
, AUX_VLC_BUF_IDX
)
323 DEF (0x501, NONE
, AUX_VLC_READ_BUF
)
324 DEF (0x502, NONE
, AUX_VLC_VALID_BITS
)
325 DEF (0x503, NONE
, AUX_VLC_BUF_IN
)
326 DEF (0x504, NONE
, AUX_VLC_BUF_FREE
)
327 DEF (0x505, NONE
, AUX_VLC_IBUF_STATUS
)
328 DEF (0x506, NONE
, AUX_VLC_SETUP
)
329 DEF (0x507, NONE
, AUX_VLC_BITS
)
330 DEF (0x508, NONE
, AUX_VLC_TABLE
)
331 DEF (0x509, NONE
, AUX_VLC_GET_SYMBOL
)
332 DEF (0x50A, NONE
, AUX_VLC_READ_SYMBOL
)
333 DEF (0x510, NONE
, AUX_UCAVLC_SETUP
)
334 DEF (0x511, NONE
, AUX_UCAVLC_STATE
)
335 DEF (0x512, NONE
, AUX_CAVLC_ZERO_LEFT
)
336 DEF (0x514, NONE
, AUX_UVLC_I_STATE
)
337 DEF (0x51C, NONE
, AUX_VLC_DMA_PTR
)
338 DEF (0x51D, NONE
, AUX_VLC_DMA_END
)
339 DEF (0x51E, NONE
, AUX_VLC_DMA_ESC
)
340 DEF (0x51F, NONE
, AUX_VLC_DMA_CTRL
)
341 DEF (0x520, NONE
, AUX_VLC_GET_0BIT
)
342 DEF (0x521, NONE
, AUX_VLC_GET_1BIT
)
343 DEF (0x522, NONE
, AUX_VLC_GET_2BIT
)
344 DEF (0x523, NONE
, AUX_VLC_GET_3BIT
)
345 DEF (0x524, NONE
, AUX_VLC_GET_4BIT
)
346 DEF (0x525, NONE
, AUX_VLC_GET_5BIT
)
347 DEF (0x526, NONE
, AUX_VLC_GET_6BIT
)
348 DEF (0x527, NONE
, AUX_VLC_GET_7BIT
)
349 DEF (0x528, NONE
, AUX_VLC_GET_8BIT
)
350 DEF (0x529, NONE
, AUX_VLC_GET_9BIT
)
351 DEF (0x52A, NONE
, AUX_VLC_GET_10BIT
)
352 DEF (0x52B, NONE
, AUX_VLC_GET_11BIT
)
353 DEF (0x52C, NONE
, AUX_VLC_GET_12BIT
)
354 DEF (0x52D, NONE
, AUX_VLC_GET_13BIT
)
355 DEF (0x52E, NONE
, AUX_VLC_GET_14BIT
)
356 DEF (0x52F, NONE
, AUX_VLC_GET_15BIT
)
357 DEF (0x530, NONE
, AUX_VLC_GET_16BIT
)
358 DEF (0x531, NONE
, AUX_VLC_GET_17BIT
)
359 DEF (0x532, NONE
, AUX_VLC_GET_18BIT
)
360 DEF (0x533, NONE
, AUX_VLC_GET_19BIT
)
361 DEF (0x534, NONE
, AUX_VLC_GET_20BIT
)
362 DEF (0x535, NONE
, AUX_VLC_GET_21BIT
)
363 DEF (0x536, NONE
, AUX_VLC_GET_22BIT
)
364 DEF (0x537, NONE
, AUX_VLC_GET_23BIT
)
365 DEF (0x538, NONE
, AUX_VLC_GET_24BIT
)
366 DEF (0x539, NONE
, AUX_VLC_GET_25BIT
)
367 DEF (0x53A, NONE
, AUX_VLC_GET_26BIT
)
368 DEF (0x53B, NONE
, AUX_VLC_GET_27BIT
)
369 DEF (0x53C, NONE
, AUX_VLC_GET_28BIT
)
370 DEF (0x53D, NONE
, AUX_VLC_GET_29BIT
)
371 DEF (0x53E, NONE
, AUX_VLC_GET_30BIT
)
372 DEF (0x53F, NONE
, AUX_VLC_GET_31BIT
)
373 DEF (0x540, NONE
, AUX_CABAC_CTRL
)
374 DEF (0x541, NONE
, AUX_CABAC_CTX_STATE
)
375 DEF (0x542, NONE
, AUX_CABAC_COD_PARAM
)
376 DEF (0x543, NONE
, AUX_CABAC_MISC0
)
377 DEF (0x544, NONE
, AUX_CABAC_MISC1
)
378 DEF (0x545, NONE
, AUX_CABAC_MISC2
)
379 DEF (0x600, NONE
, ARC600_BUILD_CONFIG
)
380 DEF (0x700, NONE
, SMART_CONTROL
)
381 DEF (0x701, NONE
, SMART_DATA_0
)
382 DEF (0x701, NONE
, SMART_DATA_1
)
383 DEF (0x701, NONE
, SMART_DATA_2
)
384 DEF (0x701, NONE
, SMART_DATA_3
)