1 /* Instruction printing code for the ARM
2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
6 This file is part of libopcodes.
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
26 #include "disassemble.h"
27 #include "opcode/arm.h"
29 #include "safe-ctype.h"
30 #include "libiberty.h"
31 #include "floatformat.h"
33 /* FIXME: This shouldn't be done here. */
34 #include "coff/internal.h"
38 #include "elf/internal.h"
42 /* FIXME: Belongs in global header. */
44 #define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
47 /* Cached mapping symbol state. */
55 struct arm_private_data
57 /* The features to use when disassembling optional instructions. */
58 arm_feature_set features
;
60 /* Track the last type (although this doesn't seem to be useful) */
61 enum map_type last_type
;
63 /* Tracking symbol table information */
66 /* The end range of the current range being disassembled. */
67 bfd_vma last_stop_offset
;
68 bfd_vma last_mapping_addr
;
121 MVE_VSTRB_SCATTER_T1
,
122 MVE_VSTRH_SCATTER_T2
,
123 MVE_VSTRW_SCATTER_T3
,
124 MVE_VSTRD_SCATTER_T4
,
125 MVE_VSTRW_SCATTER_T5
,
126 MVE_VSTRD_SCATTER_T6
,
128 MVE_VCVT_BETWEEN_FP_INT
,
130 MVE_VCVT_FROM_FP_TO_INT
,
133 MVE_VMOV_GP_TO_VEC_LANE
,
136 MVE_VMOV2_VEC_LANE_TO_GP
,
137 MVE_VMOV2_GP_TO_VEC_LANE
,
138 MVE_VMOV_VEC_LANE_TO_GP
,
214 enum mve_unpredictable
216 UNPRED_IT_BLOCK
, /* Unpredictable because mve insn in it block.
218 UNPRED_FCA_0_FCB_1
, /* Unpredictable because fcA = 0 and
220 UNPRED_R13
, /* Unpredictable because r13 (sp) or
222 UNPRED_R15
, /* Unpredictable because r15 (pc) is used. */
223 UNPRED_Q_GT_4
, /* Unpredictable because
224 vec reg start > 4 (vld4/st4). */
225 UNPRED_Q_GT_6
, /* Unpredictable because
226 vec reg start > 6 (vld2/st2). */
227 UNPRED_R13_AND_WB
, /* Unpredictable becase gp reg = r13
229 UNPRED_Q_REGS_EQUAL
, /* Unpredictable because vector registers are
231 UNPRED_OS
, /* Unpredictable because offset scaled == 1. */
232 UNPRED_GP_REGS_EQUAL
, /* Unpredictable because gp registers are the
234 UNPRED_Q_REGS_EQ_AND_SIZE_1
, /* Unpredictable because q regs equal and
236 UNPRED_Q_REGS_EQ_AND_SIZE_2
, /* Unpredictable because q regs equal and
238 UNPRED_NONE
/* No unpredictable behavior. */
243 UNDEF_SIZE
, /* undefined size. */
244 UNDEF_SIZE_0
, /* undefined because size == 0. */
245 UNDEF_SIZE_2
, /* undefined because size == 2. */
246 UNDEF_SIZE_3
, /* undefined because size == 3. */
247 UNDEF_SIZE_LE_1
, /* undefined because size <= 1. */
248 UNDEF_SIZE_NOT_2
, /* undefined because size != 2. */
249 UNDEF_SIZE_NOT_3
, /* undefined because size != 3. */
250 UNDEF_NOT_UNS_SIZE_0
, /* undefined because U == 0 and
252 UNDEF_NOT_UNS_SIZE_1
, /* undefined because U == 0 and
254 UNDEF_NOT_UNSIGNED
, /* undefined because U == 0. */
255 UNDEF_VCVT_IMM6
, /* imm6 < 32. */
256 UNDEF_VCVT_FSI_IMM6
, /* fsi = 0 and 32 >= imm6 <= 47. */
257 UNDEF_BAD_OP1_OP2
, /* undefined with op2 = 2 and
259 UNDEF_BAD_U_OP1_OP2
, /* undefined with U = 1 and
260 op2 == 0 and op1 == (0 or 1). */
261 UNDEF_OP_0_BAD_CMODE
, /* undefined because op == 0 and cmode
263 UNDEF_XCHG_UNS
, /* undefined because X == 1 and U == 1. */
264 UNDEF_NONE
/* no undefined behavior. */
269 arm_feature_set arch
; /* Architecture defining this insn. */
270 unsigned long value
; /* If arch is 0 then value is a sentinel. */
271 unsigned long mask
; /* Recognise insn if (op & mask) == value. */
272 const char * assembler
; /* How to disassemble this insn. */
279 arm_feature_set arch
; /* Architecture defining this insn. */
280 enum mve_instructions mve_op
; /* Specific mve instruction for faster
282 unsigned long value
; /* If arch is 0 then value is a sentinel. */
283 unsigned long mask
; /* Recognise insn if (op & mask) == value. */
284 const char * assembler
; /* How to disassemble this insn. */
294 /* Shared (between Arm and Thumb mode) opcode. */
297 enum isa isa
; /* Execution mode instruction availability. */
298 arm_feature_set arch
; /* Architecture defining this insn. */
299 unsigned long value
; /* If arch is 0 then value is a sentinel. */
300 unsigned long mask
; /* Recognise insn if (op & mask) == value. */
301 const char * assembler
; /* How to disassemble this insn. */
306 arm_feature_set arch
; /* Architecture defining this insn. */
307 unsigned short value
, mask
; /* Recognise insn if (op & mask) == value. */
308 const char *assembler
; /* How to disassemble this insn. */
311 /* print_insn_coprocessor recognizes the following format control codes:
315 %c print condition code (always bits 28-31 in ARM mode)
316 %q print shifter argument
317 %u print condition code (unconditional in ARM mode,
318 UNPREDICTABLE if not AL in Thumb)
319 %A print address for ldc/stc/ldf/stf instruction
320 %B print vstm/vldm register list
321 %C print vscclrm register list
322 %I print cirrus signed shift immediate: bits 0..3|4..6
323 %J print register for VLDR instruction
324 %K print address for VLDR instruction
325 %F print the COUNT field of a LFM/SFM instruction.
326 %P print floating point precision in arithmetic insn
327 %Q print floating point precision in ldf/stf insn
328 %R print floating point rounding mode
330 %<bitfield>c print as a condition code (for vsel)
331 %<bitfield>r print as an ARM register
332 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
333 %<bitfield>ru as %<>r but each u register must be unique.
334 %<bitfield>d print the bitfield in decimal
335 %<bitfield>k print immediate for VFPv3 conversion instruction
336 %<bitfield>x print the bitfield in hex
337 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
338 %<bitfield>f print a floating point constant if >7 else a
339 floating point register
340 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
341 %<bitfield>g print as an iWMMXt 64-bit register
342 %<bitfield>G print as an iWMMXt general purpose or control register
343 %<bitfield>D print as a NEON D register
344 %<bitfield>Q print as a NEON Q register
345 %<bitfield>V print as a NEON D or Q register
346 %<bitfield>E print a quarter-float immediate value
348 %y<code> print a single precision VFP reg.
349 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
350 %z<code> print a double precision VFP reg
351 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
353 %<bitfield>'c print specified char iff bitfield is all ones
354 %<bitfield>`c print specified char iff bitfield is all zeroes
355 %<bitfield>?ab... select from array of values in big endian order
357 %L print as an iWMMXt N/M width field.
358 %Z print the Immediate of a WSHUFH instruction.
359 %l like 'A' except use byte offsets for 'B' & 'H'
361 %i print 5-bit immediate in bits 8,3..0
363 %r print register offset address for wldt/wstr instruction. */
365 enum opcode_sentinel_enum
367 SENTINEL_IWMMXT_START
= 1,
369 SENTINEL_GENERIC_START
372 #define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
373 #define UNKNOWN_INSTRUCTION_32BIT "\t\t; <UNDEFINED> instruction: %08x"
374 #define UNKNOWN_INSTRUCTION_16BIT "\t\t; <UNDEFINED> instruction: %04x"
375 #define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
377 /* Common coprocessor opcodes shared between Arm and Thumb-2. */
379 static const struct sopcode32 coprocessor_opcodes
[] =
381 /* XScale instructions. */
382 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
383 0x0e200010, 0x0fff0ff0,
384 "mia%c\tacc0, %0-3r, %12-15r"},
385 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
386 0x0e280010, 0x0fff0ff0,
387 "miaph%c\tacc0, %0-3r, %12-15r"},
388 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
389 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
390 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
391 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
392 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
393 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
395 /* Intel Wireless MMX technology instructions. */
396 {ANY
, ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START
, 0, "" },
397 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
398 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
399 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
400 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
401 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
402 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
403 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
404 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
405 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
406 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
407 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
408 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
409 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
410 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
411 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
412 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
413 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
414 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
415 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
416 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
417 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
418 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
419 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
420 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
421 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
422 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
423 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
424 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
425 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
426 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
427 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
428 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
429 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
430 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
431 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
432 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
433 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
434 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
435 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
436 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
437 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
438 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
439 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
440 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
441 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
442 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
443 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
444 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
445 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
446 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
447 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
448 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
449 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
450 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
451 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
452 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
453 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
454 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
455 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
456 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
457 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
458 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
459 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
460 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
461 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
462 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
463 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
464 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
465 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
466 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
467 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
468 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
469 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
470 0x0e800120, 0x0f800ff0,
471 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
472 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
473 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
474 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
475 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
476 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
477 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
478 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
479 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
480 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
481 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
482 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
483 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
484 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
485 0x0e8000a0, 0x0f800ff0,
486 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
487 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
488 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
489 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
490 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
491 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
492 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
493 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
494 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
495 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
496 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
497 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
498 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
499 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
500 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
501 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
502 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
503 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
504 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
505 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
506 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
507 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
508 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
509 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
510 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
511 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
512 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
513 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
514 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
515 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
516 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
517 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
518 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
519 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
520 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
521 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
522 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
523 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
524 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
525 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
526 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
527 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
528 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
529 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
530 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
531 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
532 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
533 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
534 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
535 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
536 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
537 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
538 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
539 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
540 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
541 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
542 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
543 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
544 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
545 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
546 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
547 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
548 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
549 {ANY
, ARM_FEATURE_CORE_LOW (0),
550 SENTINEL_IWMMXT_END
, 0, "" },
552 /* Floating point coprocessor (FPA) instructions. */
553 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
554 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
555 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
556 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
557 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
558 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
559 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
560 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
561 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
562 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
563 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
564 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
565 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
566 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
567 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
568 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
569 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
570 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
571 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
572 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
573 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
574 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
575 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
576 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
577 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
578 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
579 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
580 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
581 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
582 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
583 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
584 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
585 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
586 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
587 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
588 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
589 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
590 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
591 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
592 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
593 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
594 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
595 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
596 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
597 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
598 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
599 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
600 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
601 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
602 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
603 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
604 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
605 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
606 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
607 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
608 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
609 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
610 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
611 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
612 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
613 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
614 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
615 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
616 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
617 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
618 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
619 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
620 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
621 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
622 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
623 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
624 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
625 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
626 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
627 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
628 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
629 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
630 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
631 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
632 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
633 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
634 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
635 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
),
636 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
637 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
),
638 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
640 /* Armv8.1-M Mainline instructions. */
641 {T32
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
642 0xec9f0b00, 0xffbf0f01, "vscclrm%c\t%C"},
643 {T32
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
644 0xec9f0a00, 0xffbf0f00, "vscclrm%c\t%C"},
646 /* ARMv8-M Mainline Security Extensions instructions. */
647 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
),
648 0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
649 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
),
650 0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
652 /* Register load/store. */
653 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
654 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
655 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
656 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
657 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
658 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
659 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
660 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
661 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
662 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
663 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
664 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
665 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
666 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
667 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
668 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
669 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
670 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
671 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
672 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
673 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
674 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
675 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
676 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
677 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
678 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
679 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
680 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
681 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
682 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
683 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
684 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
685 {ANY
, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN
),
686 0xec100f80, 0xfe101f80, "vldr%c\t%J, %K"},
687 {ANY
, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN
),
688 0xec000f80, 0xfe101f80, "vstr%c\t%J, %K"},
690 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
691 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
692 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
693 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
694 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
695 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
696 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
697 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
699 /* Data transfer between ARM and NEON registers. */
700 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
701 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
702 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
703 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
704 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
705 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
706 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
707 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
708 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
709 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
710 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
711 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
712 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
713 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
714 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
715 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
716 /* Half-precision conversion instructions. */
717 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
718 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
719 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
720 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
721 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
),
722 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
723 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
),
724 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
726 /* Floating point coprocessor (VFP) instructions. */
727 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
728 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
729 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
730 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
731 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
732 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
733 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
734 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
735 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
736 0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"},
737 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
738 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
739 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
740 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
741 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
742 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
743 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
744 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
745 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
746 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
747 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
748 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
749 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
750 0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"},
751 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
752 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
753 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
754 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
755 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
756 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
757 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
758 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
759 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
760 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
761 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
762 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
763 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
764 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
765 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
766 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
767 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
768 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
769 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
770 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
771 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
772 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
773 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
774 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
775 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
776 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
777 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
778 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
779 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
780 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
781 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
782 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
783 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
784 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
785 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
786 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
787 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
788 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
789 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
790 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
791 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
792 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
793 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
794 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
795 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
796 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
797 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
798 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
799 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
800 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
801 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
802 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
803 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
804 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
805 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
),
806 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
807 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
),
808 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
809 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
810 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
811 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
812 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
813 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
),
814 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
815 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
),
816 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
817 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
818 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
819 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
),
820 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
821 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
),
822 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
823 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
),
824 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
825 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
),
826 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
827 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
),
828 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
829 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
830 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
831 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
832 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
833 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
834 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
835 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
836 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
837 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
838 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
839 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
840 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
841 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
842 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
843 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
844 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
845 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
846 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
847 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
848 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
849 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
850 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
851 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
852 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
853 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
854 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
855 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
856 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
857 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
858 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
859 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
860 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
861 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
862 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
863 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
864 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
866 /* Cirrus coprocessor instructions. */
867 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
868 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
869 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
870 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
871 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
872 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
873 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
874 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
875 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
876 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
877 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
878 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
879 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
880 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
881 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
882 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
883 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
884 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
885 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
886 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
887 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
888 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
889 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
890 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
891 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
892 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
893 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
894 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
895 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
896 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
897 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
898 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
899 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
900 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
901 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
902 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
903 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
904 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
905 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
906 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
907 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
908 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
909 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
910 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
911 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
912 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
913 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
914 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
915 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
916 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
917 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
918 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
919 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
920 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
921 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
922 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
923 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
924 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
925 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
926 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
927 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
928 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
929 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
930 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
931 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
932 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
933 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
934 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
935 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
936 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
937 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
938 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
939 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
940 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
941 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
942 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
943 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
944 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
945 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
946 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
947 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
948 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
949 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
950 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
951 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
952 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
953 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
954 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
955 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
956 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
957 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
958 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
959 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
960 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
961 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
962 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
963 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
964 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
965 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
966 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
967 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
968 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
969 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
970 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
971 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
972 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
973 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
974 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
975 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
976 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
977 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
978 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
979 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
980 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
981 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
982 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
983 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
984 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
985 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
986 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
987 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
988 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
989 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
990 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
991 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
992 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
993 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
994 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
995 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
996 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
997 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
998 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
999 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1000 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
1001 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1002 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
1003 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1004 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
1005 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1006 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
1007 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1008 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
1009 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1010 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
1011 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1012 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1013 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1014 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
1015 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1016 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1017 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1018 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
1019 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1020 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1021 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1022 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
1023 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1024 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1025 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1026 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1027 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1028 0x0e000600, 0x0ff00f10,
1029 "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1030 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1031 0x0e100600, 0x0ff00f10,
1032 "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1033 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1034 0x0e200600, 0x0ff00f10,
1035 "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
1036 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1037 0x0e300600, 0x0ff00f10,
1038 "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
1040 /* VFP Fused multiply add instructions. */
1041 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1042 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
1043 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1044 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
1045 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1046 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
1047 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1048 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
1049 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1050 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
1051 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1052 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
1053 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1054 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
1055 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1056 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
1059 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1060 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
1061 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1062 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
1063 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1064 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
1065 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1066 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
1067 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1068 0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
1069 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1070 0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
1071 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1072 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
1073 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1074 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
1075 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1076 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
1077 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1078 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
1079 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1080 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
1081 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1082 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
1084 /* Generic coprocessor instructions. */
1085 {ANY
, ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START
, 0, "" },
1086 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
1087 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
1088 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
1089 0x0c500000, 0x0ff00000,
1090 "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
1091 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1092 0x0e000000, 0x0f000010,
1093 "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
1094 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1095 0x0e10f010, 0x0f10f010,
1096 "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
1097 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1098 0x0e100010, 0x0f100010,
1099 "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1100 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1101 0x0e000010, 0x0f100010,
1102 "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
1103 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1104 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
1105 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1106 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
1108 /* V6 coprocessor instructions. */
1109 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
1110 0xfc500000, 0xfff00000,
1111 "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
1112 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
1113 0xfc400000, 0xfff00000,
1114 "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
1116 /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */
1117 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1118 0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
1119 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1120 0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
1121 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1122 0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
1123 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1124 0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
1125 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1126 0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
1127 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1128 0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
1129 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1130 0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
1131 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1132 0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"},
1133 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1134 0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
1135 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1136 0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"},
1138 /* Dot Product instructions in the space of coprocessor 13. */
1139 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
1140 0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
1141 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
1142 0xfe000d00, 0xff000f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"},
1144 /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8. */
1145 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1146 0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
1147 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1148 0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
1149 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1150 0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
1151 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1152 0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
1153 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1154 0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
1155 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1156 0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
1157 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1158 0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
1159 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1160 0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
1162 /* V5 coprocessor instructions. */
1163 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1164 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
1165 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1166 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
1167 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1168 0xfe000000, 0xff000010,
1169 "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
1170 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1171 0xfe000010, 0xff100010,
1172 "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
1173 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1174 0xfe100010, 0xff100010,
1175 "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1177 /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
1178 cp_num: bit <11:8> == 0b1001.
1179 cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */
1180 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1181 0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
1182 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1183 0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
1184 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1185 0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
1186 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1187 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
1188 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1189 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
1190 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1191 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
1192 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1193 0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
1194 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1195 0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
1196 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1197 0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
1198 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1199 0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
1200 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1201 0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
1202 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1203 0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
1204 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1205 0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
1206 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1207 0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
1208 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1209 0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
1210 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1211 0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
1212 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1213 0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
1214 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1215 0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
1216 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1217 0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
1218 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1219 0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
1220 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1221 0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
1222 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1223 0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
1224 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1225 0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
1226 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1227 0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
1228 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1229 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
1230 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1231 0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
1232 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1233 0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
1234 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1235 0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
1236 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1237 0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
1238 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1239 0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
1240 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1241 0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
1242 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1243 0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
1244 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1245 0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
1246 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1247 0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
1248 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1249 0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
1251 /* ARMv8.3 javascript conversion instruction. */
1252 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1253 0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
1255 {ANY
, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
1258 /* Neon opcode table: This does not encode the top byte -- that is
1259 checked by the print_insn_neon routine, as it depends on whether we are
1260 doing thumb32 or arm32 disassembly. */
1262 /* print_insn_neon recognizes the following format control codes:
1266 %c print condition code
1267 %u print condition code (unconditional in ARM mode,
1268 UNPREDICTABLE if not AL in Thumb)
1269 %A print v{st,ld}[1234] operands
1270 %B print v{st,ld}[1234] any one operands
1271 %C print v{st,ld}[1234] single->all operands
1273 %E print vmov, vmvn, vorr, vbic encoded constant
1274 %F print vtbl,vtbx register list
1276 %<bitfield>r print as an ARM register
1277 %<bitfield>d print the bitfield in decimal
1278 %<bitfield>e print the 2^N - bitfield in decimal
1279 %<bitfield>D print as a NEON D register
1280 %<bitfield>Q print as a NEON Q register
1281 %<bitfield>R print as a NEON D or Q register
1282 %<bitfield>Sn print byte scaled width limited by n
1283 %<bitfield>Tn print short scaled width limited by n
1284 %<bitfield>Un print long scaled width limited by n
1286 %<bitfield>'c print specified char iff bitfield is all ones
1287 %<bitfield>`c print specified char iff bitfield is all zeroes
1288 %<bitfield>?ab... select from array of values in big endian order. */
1290 static const struct opcode32 neon_opcodes
[] =
1293 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1294 0xf2b00840, 0xffb00850,
1295 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1296 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1297 0xf2b00000, 0xffb00810,
1298 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1300 /* Data transfer between ARM and NEON registers. */
1301 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1302 0x0e800b10, 0x1ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
1303 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1304 0x0e800b30, 0x1ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
1305 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1306 0x0ea00b10, 0x1ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
1307 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1308 0x0ea00b30, 0x1ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
1309 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1310 0x0ec00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
1311 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1312 0x0ee00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
1314 /* Move data element to all lanes. */
1315 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1316 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
1317 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1318 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
1319 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1320 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
1323 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1324 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1325 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1326 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1328 /* Half-precision conversions. */
1329 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
),
1330 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1331 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
),
1332 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
1334 /* NEON fused multiply add instructions. */
1335 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
),
1336 0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1337 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1338 0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1339 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
),
1340 0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1341 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1342 0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1344 /* Two registers, miscellaneous. */
1345 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
),
1346 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
1347 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1348 0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
1349 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
),
1350 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
1351 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1352 0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
1353 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1354 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1355 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1356 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1357 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1358 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1359 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1360 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1361 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1362 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1363 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1364 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1365 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1366 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1367 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1368 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1369 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1370 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1371 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1372 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1373 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1374 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1375 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1376 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1377 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1378 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1379 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1380 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1381 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1382 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1383 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1384 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1385 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1386 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1387 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1388 0xf3b20300, 0xffb30fd0,
1389 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1390 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1391 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1392 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1393 0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1394 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1395 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1396 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1397 0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1398 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1399 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1400 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1401 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1402 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1403 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1404 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1405 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1406 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1407 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1408 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1409 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1410 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1411 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1412 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1413 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1414 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1415 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1416 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1417 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1418 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1419 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1420 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1421 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1422 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1423 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1424 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1425 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1426 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1427 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1428 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1429 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1430 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1431 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1432 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1433 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1434 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1435 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1436 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1437 0xf3bb0600, 0xffbf0e10,
1438 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
1439 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1440 0xf3b70600, 0xffbf0e10,
1441 "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
1443 /* Three registers of the same length. */
1444 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1445 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1446 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1447 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1448 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1449 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1450 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1451 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1452 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1453 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1454 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1455 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1456 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1457 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1458 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
),
1459 0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1460 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1461 0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1462 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
),
1463 0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1464 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1465 0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1466 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1467 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1468 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1469 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1470 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1471 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1472 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1473 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1474 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1475 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1476 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1477 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1478 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1479 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1480 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1481 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1482 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1483 0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1484 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1485 0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1486 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1487 0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1488 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1489 0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1490 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1491 0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1492 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1493 0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1494 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1495 0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1496 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1497 0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1498 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1499 0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1500 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1501 0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1502 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1503 0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1504 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1505 0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1506 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1507 0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1508 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1509 0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1510 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1511 0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1512 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1513 0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1514 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1515 0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1516 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1517 0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1518 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1519 0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1520 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1521 0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1522 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1523 0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1524 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1525 0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1526 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1527 0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1528 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1529 0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1530 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1531 0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1532 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1533 0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1534 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1535 0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1536 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1537 0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1538 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1539 0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1540 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1541 0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1542 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1543 0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1544 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1545 0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1546 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1547 0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1548 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1549 0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1550 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1551 0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1552 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1553 0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1554 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1555 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1556 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1557 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1558 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1559 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1560 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1561 0xf2000b00, 0xff800f10,
1562 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1563 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1564 0xf2000b10, 0xff800f10,
1565 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1566 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1567 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1568 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1569 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1570 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1571 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1572 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1573 0xf3000b00, 0xff800f10,
1574 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1575 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1576 0xf2000000, 0xfe800f10,
1577 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1578 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1579 0xf2000010, 0xfe800f10,
1580 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1581 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1582 0xf2000100, 0xfe800f10,
1583 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1584 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1585 0xf2000200, 0xfe800f10,
1586 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1587 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1588 0xf2000210, 0xfe800f10,
1589 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1590 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1591 0xf2000300, 0xfe800f10,
1592 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1593 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1594 0xf2000310, 0xfe800f10,
1595 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1596 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1597 0xf2000400, 0xfe800f10,
1598 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1599 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1600 0xf2000410, 0xfe800f10,
1601 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1602 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1603 0xf2000500, 0xfe800f10,
1604 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1605 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1606 0xf2000510, 0xfe800f10,
1607 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1608 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1609 0xf2000600, 0xfe800f10,
1610 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1611 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1612 0xf2000610, 0xfe800f10,
1613 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1614 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1615 0xf2000700, 0xfe800f10,
1616 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1617 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1618 0xf2000710, 0xfe800f10,
1619 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1620 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1621 0xf2000910, 0xfe800f10,
1622 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1623 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1624 0xf2000a00, 0xfe800f10,
1625 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1626 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1627 0xf2000a10, 0xfe800f10,
1628 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1629 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
1630 0xf3000b10, 0xff800f10,
1631 "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1632 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
1633 0xf3000c10, 0xff800f10,
1634 "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1636 /* One register and an immediate value. */
1637 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1638 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1639 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1640 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1641 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1642 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1643 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1644 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1645 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1646 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1647 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1648 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1649 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1650 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1651 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1652 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1653 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1654 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1655 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1656 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1657 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1658 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1659 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1660 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1661 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1662 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
1664 /* Two registers and a shift amount. */
1665 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1666 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1667 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1668 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1669 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1670 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1671 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1672 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1673 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1674 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1675 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1676 0xf2880950, 0xfeb80fd0,
1677 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1678 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1679 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1680 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1681 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1682 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1683 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1684 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1685 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1686 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1687 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1688 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1689 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1690 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1691 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1692 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1693 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1694 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1695 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1696 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1697 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1698 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1699 0xf2900950, 0xfeb00fd0,
1700 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1701 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1702 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1703 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1704 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1705 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1706 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1707 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1708 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1709 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1710 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1711 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1712 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1713 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1714 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1715 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1716 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1717 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1718 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1719 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1720 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1721 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1722 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1723 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1724 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1725 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1726 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1727 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1728 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1729 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1730 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1731 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1732 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1733 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1734 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1735 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1736 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1737 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1738 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1739 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1740 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1741 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1742 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1743 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1744 0xf2a00950, 0xfea00fd0,
1745 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1746 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1747 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1748 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1749 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1750 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1751 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1752 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1753 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1754 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1755 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1756 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1757 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1758 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1759 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1760 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1761 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1762 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1763 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1764 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1765 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1766 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1767 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1768 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1769 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1770 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1771 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1772 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1773 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1774 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1775 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1776 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1777 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1778 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1779 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1780 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1781 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1782 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1783 0xf2a00e10, 0xfea00e90,
1784 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
1785 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1786 0xf2a00c10, 0xfea00e90,
1787 "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"},
1789 /* Three registers of different lengths. */
1790 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1791 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1792 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1793 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1794 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1795 0xf2800400, 0xff800f50,
1796 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1797 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1798 0xf2800600, 0xff800f50,
1799 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1800 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1801 0xf2800900, 0xff800f50,
1802 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1803 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1804 0xf2800b00, 0xff800f50,
1805 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1806 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1807 0xf2800d00, 0xff800f50,
1808 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1809 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1810 0xf3800400, 0xff800f50,
1811 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1812 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1813 0xf3800600, 0xff800f50,
1814 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1815 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1816 0xf2800000, 0xfe800f50,
1817 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1818 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1819 0xf2800100, 0xfe800f50,
1820 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1821 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1822 0xf2800200, 0xfe800f50,
1823 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1824 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1825 0xf2800300, 0xfe800f50,
1826 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1827 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1828 0xf2800500, 0xfe800f50,
1829 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1830 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1831 0xf2800700, 0xfe800f50,
1832 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1833 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1834 0xf2800800, 0xfe800f50,
1835 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1836 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1837 0xf2800a00, 0xfe800f50,
1838 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1839 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1840 0xf2800c00, 0xfe800f50,
1841 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1843 /* Two registers and a scalar. */
1844 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1845 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1846 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1847 0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1848 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
1849 0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
1850 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1851 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1852 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1853 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1854 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1855 0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1856 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
1857 0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
1858 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1859 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1860 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1861 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1862 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1863 0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1864 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
1865 0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
1866 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1867 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1868 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1869 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1870 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1871 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1872 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1873 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1874 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1875 0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1876 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
1877 0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1878 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1879 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1880 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1881 0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1882 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
1883 0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1884 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1885 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1886 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1887 0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1888 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
1889 0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1890 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1891 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1892 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1893 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1894 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1895 0xf2800240, 0xfe800f50,
1896 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1897 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1898 0xf2800640, 0xfe800f50,
1899 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1900 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1901 0xf2800a40, 0xfe800f50,
1902 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1903 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
1904 0xf2800e40, 0xff800f50,
1905 "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1906 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
1907 0xf2800f40, 0xff800f50,
1908 "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1909 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
1910 0xf3800e40, 0xff800f50,
1911 "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1912 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
1913 0xf3800f40, 0xff800f50,
1914 "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
1917 /* Element and structure load/store. */
1918 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1919 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
1920 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1921 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
1922 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1923 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
1924 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1925 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
1926 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1927 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
1928 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1929 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1930 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1931 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1932 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1933 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1934 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1935 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1936 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1937 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1938 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1939 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1940 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1941 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1942 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1943 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1944 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1945 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1946 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1947 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
1948 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1949 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
1950 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1951 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
1952 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1953 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
1954 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1955 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
1957 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
1960 /* mve opcode table. */
1962 /* print_insn_mve recognizes the following format control codes:
1966 %a print '+' or '-' or imm offset in vldr[bhwd] and
1968 %c print condition code
1969 %d print addr mode of MVE vldr[bhw] and vstr[bhw]
1970 %u print 'U' (unsigned) or 'S' for various mve instructions
1971 %i print MVE predicate(s) for vpt and vpst
1972 %m print rounding mode for vcvt and vrint
1973 %n print vector comparison code for predicated instruction
1974 %s print size for various vcvt instructions
1975 %v print vector predicate for instruction in predicated
1977 %o print offset scaled for vldr[hwd] and vstr[hwd]
1978 %w print writeback mode for MVE v{st,ld}[24]
1979 %B print v{st,ld}[24] any one operands
1980 %E print vmov, vmvn, vorr, vbic encoded constant
1981 %N print generic index for vmov
1982 %T print bottom ('b') or top ('t') of source register
1983 %X print exchange field in vmla* instructions
1985 %<bitfield>r print as an ARM register
1986 %<bitfield>d print the bitfield in decimal
1987 %<bitfield>A print accumulate or not
1988 %<bitfield>Q print as a MVE Q register
1989 %<bitfield>F print as a MVE S register
1990 %<bitfield>Z as %<>r but r15 is ZR instead of PC and r13 is
1992 %<bitfield>s print size for vector predicate & non VMOV instructions
1993 %<bitfield>i print immediate for vstr/vldr reg +/- imm
1994 %<bitfield>h print high half of 64-bit destination reg
1995 %<bitfield>k print immediate for vector conversion instruction
1996 %<bitfield>l print low half of 64-bit destination reg
1997 %<bitfield>o print rotate value for vcmul
1998 %<bitfield>u print immediate value for vddup/vdwdup
1999 %<bitfield>x print the bitfield in hex.
2002 static const struct mopcode32 mve_opcodes
[] =
2006 {ARM_FEATURE_COPROC (FPU_MVE
),
2008 0xfe310f4d, 0xffbf1fff,
2012 /* Floating point VPT T1. */
2013 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2015 0xee310f00, 0xefb10f50,
2016 "vpt%i.f%28s\t%n, %17-19Q, %1-3,5Q"},
2017 /* Floating point VPT T2. */
2018 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2020 0xee310f40, 0xefb10f50,
2021 "vpt%i.f%28s\t%n, %17-19Q, %0-3Z"},
2023 /* Vector VPT T1. */
2024 {ARM_FEATURE_COPROC (FPU_MVE
),
2026 0xfe010f00, 0xff811f51,
2027 "vpt%i.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2028 /* Vector VPT T2. */
2029 {ARM_FEATURE_COPROC (FPU_MVE
),
2031 0xfe010f01, 0xff811f51,
2032 "vpt%i.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2033 /* Vector VPT T3. */
2034 {ARM_FEATURE_COPROC (FPU_MVE
),
2036 0xfe011f00, 0xff811f50,
2037 "vpt%i.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2038 /* Vector VPT T4. */
2039 {ARM_FEATURE_COPROC (FPU_MVE
),
2041 0xfe010f40, 0xff811f70,
2042 "vpt%i.i%20-21s\t%n, %17-19Q, %0-3Z"},
2043 /* Vector VPT T5. */
2044 {ARM_FEATURE_COPROC (FPU_MVE
),
2046 0xfe010f60, 0xff811f70,
2047 "vpt%i.u%20-21s\t%n, %17-19Q, %0-3Z"},
2048 /* Vector VPT T6. */
2049 {ARM_FEATURE_COPROC (FPU_MVE
),
2051 0xfe011f40, 0xff811f50,
2052 "vpt%i.s%20-21s\t%n, %17-19Q, %0-3Z"},
2054 /* Vector VBIC immediate. */
2055 {ARM_FEATURE_COPROC (FPU_MVE
),
2057 0xef800070, 0xefb81070,
2058 "vbic%v.i%8-11s\t%13-15,22Q, %E"},
2060 /* Vector VBIC register. */
2061 {ARM_FEATURE_COPROC (FPU_MVE
),
2063 0xef100150, 0xffb11f51,
2064 "vbic%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2066 /* Vector VADDLV. */
2067 {ARM_FEATURE_COPROC (FPU_MVE
),
2069 0xee890f00, 0xef8f1fd1,
2070 "vaddlv%5A%v.%u32\t%13-15l, %20-22h, %1-3Q"},
2073 {ARM_FEATURE_COPROC (FPU_MVE
),
2075 0xeef10f00, 0xeff31fd1,
2076 "vaddv%5A%v.%u%18-19s\t%13-15l, %1-3Q"},
2078 /* Vector VCADD floating point. */
2079 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2081 0xfc800840, 0xfea11f51,
2082 "vcadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%24o"},
2085 {ARM_FEATURE_COPROC (FPU_MVE
),
2087 0xfe000f00, 0xff810f51,
2088 "vcadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
2091 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2093 0xfc200840, 0xfe211f51,
2094 "vcmla%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%23-24o"},
2096 /* Vector VCMP floating point T1. */
2097 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2099 0xee310f00, 0xeff1ef50,
2100 "vcmp%v.f%28s\t%n, %17-19Q, %1-3,5Q"},
2102 /* Vector VCMP floating point T2. */
2103 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2105 0xee310f40, 0xeff1ef50,
2106 "vcmp%v.f%28s\t%n, %17-19Q, %0-3Z"},
2108 /* Vector VCMP T1. */
2109 {ARM_FEATURE_COPROC (FPU_MVE
),
2111 0xfe010f00, 0xffc1ff51,
2112 "vcmp%v.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2113 /* Vector VCMP T2. */
2114 {ARM_FEATURE_COPROC (FPU_MVE
),
2116 0xfe010f01, 0xffc1ff51,
2117 "vcmp%v.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2118 /* Vector VCMP T3. */
2119 {ARM_FEATURE_COPROC (FPU_MVE
),
2121 0xfe011f00, 0xffc1ff50,
2122 "vcmp%v.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2123 /* Vector VCMP T4. */
2124 {ARM_FEATURE_COPROC (FPU_MVE
),
2126 0xfe010f40, 0xffc1ff70,
2127 "vcmp%v.i%20-21s\t%n, %17-19Q, %0-3Z"},
2128 /* Vector VCMP T5. */
2129 {ARM_FEATURE_COPROC (FPU_MVE
),
2131 0xfe010f60, 0xffc1ff70,
2132 "vcmp%v.u%20-21s\t%n, %17-19Q, %0-3Z"},
2133 /* Vector VCMP T6. */
2134 {ARM_FEATURE_COPROC (FPU_MVE
),
2136 0xfe011f40, 0xffc1ff50,
2137 "vcmp%v.s%20-21s\t%n, %17-19Q, %0-3Z"},
2140 {ARM_FEATURE_COPROC (FPU_MVE
),
2142 0xeea00b10, 0xffb10f5f,
2143 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2146 {ARM_FEATURE_COPROC (FPU_MVE
),
2148 0xff000150, 0xffd11f51,
2149 "veor%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2151 /* Vector VFMA, vector * scalar. */
2152 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2154 0xee310e40, 0xefb11f70,
2155 "vfma%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2157 /* Vector VFMA floating point. */
2158 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2160 0xef000c50, 0xffa11f51,
2161 "vfma%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2163 /* Vector VFMS floating point. */
2164 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2166 0xef200c50, 0xffa11f51,
2167 "vfms%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2169 /* Vector VFMAS, vector * scalar. */
2170 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2171 MVE_VFMAS_FP_SCALAR
,
2172 0xee311e40, 0xefb11f70,
2173 "vfmas%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2175 /* Vector VHADD T1. */
2176 {ARM_FEATURE_COPROC (FPU_MVE
),
2178 0xef000040, 0xef811f51,
2179 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2181 /* Vector VHADD T2. */
2182 {ARM_FEATURE_COPROC (FPU_MVE
),
2184 0xee000f40, 0xef811f70,
2185 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2187 /* Vector VHSUB T1. */
2188 {ARM_FEATURE_COPROC (FPU_MVE
),
2190 0xef000240, 0xef811f51,
2191 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2193 /* Vector VHSUB T2. */
2194 {ARM_FEATURE_COPROC (FPU_MVE
),
2196 0xee001f40, 0xef811f70,
2197 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2200 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2202 0xee300e00, 0xefb10f50,
2203 "vcmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%0,12o"},
2206 {ARM_FEATURE_COPROC (FPU_MVE
),
2208 0xeea00b10, 0xffb10f5f,
2209 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2211 /* Vector VRHADD. */
2212 {ARM_FEATURE_COPROC (FPU_MVE
),
2214 0xef000140, 0xef811f51,
2215 "vrhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2218 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2219 MVE_VCVT_FP_FIX_VEC
,
2220 0xef800c50, 0xef801cd1,
2221 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q, #%16-21k"},
2224 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2225 MVE_VCVT_BETWEEN_FP_INT
,
2226 0xffb30640, 0xffb31e51,
2227 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q"},
2229 /* Vector VCVT between single and half-precision float, bottom half. */
2230 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2231 MVE_VCVT_FP_HALF_FP
,
2232 0xee3f0e01, 0xefbf1fd1,
2233 "vcvtb%v.%s\t%13-15,22Q, %1-3,5Q"},
2235 /* Vector VCVT between single and half-precision float, top half. */
2236 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2237 MVE_VCVT_FP_HALF_FP
,
2238 0xee3f1e01, 0xefbf1fd1,
2239 "vcvtt%v.%s\t%13-15,22Q, %1-3,5Q"},
2242 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2243 MVE_VCVT_FROM_FP_TO_INT
,
2244 0xffb30040, 0xffb31c51,
2245 "vcvt%m%v.%s\t%13-15,22Q, %1-3,5Q"},
2248 {ARM_FEATURE_COPROC (FPU_MVE
),
2250 0xee011f6e, 0xff811f7e,
2251 "vddup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
2253 /* Vector VDWDUP. */
2254 {ARM_FEATURE_COPROC (FPU_MVE
),
2256 0xee011f60, 0xff811f70,
2257 "vdwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
2259 /* Vector VHCADD. */
2260 {ARM_FEATURE_COPROC (FPU_MVE
),
2262 0xee000f00, 0xff810f51,
2263 "vhcadd%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
2265 /* Vector VIWDUP. */
2266 {ARM_FEATURE_COPROC (FPU_MVE
),
2268 0xee010f60, 0xff811f70,
2269 "viwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
2272 {ARM_FEATURE_COPROC (FPU_MVE
),
2274 0xee010f6e, 0xff811f7e,
2275 "vidup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
2278 {ARM_FEATURE_COPROC (FPU_MVE
),
2280 0xfc901e00, 0xff901e5f,
2281 "vld2%5d.%7-8s\t%B, [%16-19r]%w"},
2284 {ARM_FEATURE_COPROC (FPU_MVE
),
2286 0xfc901e01, 0xff901e1f,
2287 "vld4%5-6d.%7-8s\t%B, [%16-19r]%w"},
2289 /* Vector VLDRB gather load. */
2290 {ARM_FEATURE_COPROC (FPU_MVE
),
2291 MVE_VLDRB_GATHER_T1
,
2292 0xec900e00, 0xefb01e50,
2293 "vldrb%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
2295 /* Vector VLDRH gather load. */
2296 {ARM_FEATURE_COPROC (FPU_MVE
),
2297 MVE_VLDRH_GATHER_T2
,
2298 0xec900e10, 0xefb01e50,
2299 "vldrh%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2301 /* Vector VLDRW gather load. */
2302 {ARM_FEATURE_COPROC (FPU_MVE
),
2303 MVE_VLDRW_GATHER_T3
,
2304 0xfc900f40, 0xffb01fd0,
2305 "vldrw%v.u32\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2307 /* Vector VLDRD gather load. */
2308 {ARM_FEATURE_COPROC (FPU_MVE
),
2309 MVE_VLDRD_GATHER_T4
,
2310 0xec900fd0, 0xefb01fd0,
2311 "vldrd%v.u64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2313 /* Vector VLDRW gather load. */
2314 {ARM_FEATURE_COPROC (FPU_MVE
),
2315 MVE_VLDRW_GATHER_T5
,
2316 0xfd101e00, 0xff111f00,
2317 "vldrw%v.u32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2319 /* Vector VLDRD gather load, variant T6. */
2320 {ARM_FEATURE_COPROC (FPU_MVE
),
2321 MVE_VLDRD_GATHER_T6
,
2322 0xfd101f00, 0xff111f00,
2323 "vldrd%v.u64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2326 {ARM_FEATURE_COPROC (FPU_MVE
),
2328 0xec100e00, 0xee581e00,
2329 "vldrb%v.%u%7-8s\t%13-15Q, %d"},
2332 {ARM_FEATURE_COPROC (FPU_MVE
),
2334 0xec180e00, 0xee581e00,
2335 "vldrh%v.%u%7-8s\t%13-15Q, %d"},
2337 /* Vector VLDRB unsigned, variant T5. */
2338 {ARM_FEATURE_COPROC (FPU_MVE
),
2340 0xec101e00, 0xfe101f80,
2341 "vldrb%v.u8\t%13-15,22Q, %d"},
2343 /* Vector VLDRH unsigned, variant T6. */
2344 {ARM_FEATURE_COPROC (FPU_MVE
),
2346 0xec101e80, 0xfe101f80,
2347 "vldrh%v.u16\t%13-15,22Q, %d"},
2349 /* Vector VLDRW unsigned, variant T7. */
2350 {ARM_FEATURE_COPROC (FPU_MVE
),
2352 0xec101f00, 0xfe101f80,
2353 "vldrw%v.u32\t%13-15,22Q, %d"},
2355 /* Vector VMLALDAV. Note must appear before VMLADAV due to instruction
2357 {ARM_FEATURE_COPROC (FPU_MVE
),
2359 0xee801e00, 0xef801f51,
2360 "vmlaldav%5Ax%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2362 {ARM_FEATURE_COPROC (FPU_MVE
),
2364 0xee800e00, 0xef801f51,
2365 "vmlalv%5A%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2367 /* Vector VMLAV T1 variant, same as VMLADAV but with X == 0. */
2368 {ARM_FEATURE_COPROC (FPU_MVE
),
2370 0xeef00e00, 0xeff01f51,
2371 "vmlav%5A%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2373 /* Vector VMLAV T2 variant, same as VMLADAV but with X == 0. */
2374 {ARM_FEATURE_COPROC (FPU_MVE
),
2376 0xeef00f00, 0xeff11f51,
2377 "vmlav%5A%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2379 /* Vector VMLADAV T1 variant. */
2380 {ARM_FEATURE_COPROC (FPU_MVE
),
2382 0xeef01e00, 0xeff01f51,
2383 "vmladav%5Ax%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2385 /* Vector VMLADAV T2 variant. */
2386 {ARM_FEATURE_COPROC (FPU_MVE
),
2388 0xeef01f00, 0xeff11f51,
2389 "vmladav%5Ax%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2392 {ARM_FEATURE_COPROC (FPU_MVE
),
2394 0xee011e40, 0xef811f70,
2395 "vmlas%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2397 /* Vector VRMLSLDAVH. Note must appear before VMLSDAV due to instruction
2399 {ARM_FEATURE_COPROC (FPU_MVE
),
2401 0xfe800e01, 0xff810f51,
2402 "vrmlsldavh%5A%X%v.s32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2404 /* Vector VMLSLDAV. Note must appear before VMLSDAV due to instruction
2406 {ARM_FEATURE_COPROC (FPU_MVE
),
2408 0xee800e01, 0xff800f51,
2409 "vmlsldav%5A%X%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2411 /* Vector VMLSDAV T1 Variant. */
2412 {ARM_FEATURE_COPROC (FPU_MVE
),
2414 0xeef00e01, 0xfff00f51,
2415 "vmlsdav%5A%X%v.s%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2417 /* Vector VMLSDAV T2 Variant. */
2418 {ARM_FEATURE_COPROC (FPU_MVE
),
2420 0xfef00e01, 0xfff10f51,
2421 "vmlsdav%5A%X%v.s8\t%13-15l, %17-19,7Q, %1-3Q"},
2423 /* Vector VMOV between gpr and half precision register, op == 0. */
2424 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2426 0xee000910, 0xfff00f7f,
2427 "vmov.f16\t%7,16-19F, %12-15r"},
2429 /* Vector VMOV between gpr and half precision register, op == 1. */
2430 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2432 0xee100910, 0xfff00f7f,
2433 "vmov.f16\t%12-15r, %7,16-19F"},
2435 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2436 MVE_VMOV_GP_TO_VEC_LANE
,
2437 0xee000b10, 0xff900f1f,
2438 "vmov%c.%5-6,21-22s\t%17-19,7Q[%N], %12-15r"},
2440 /* Vector VORR immediate to vector.
2441 NOTE: MVE_VORR_IMM must appear in the table
2442 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2443 {ARM_FEATURE_COPROC (FPU_MVE
),
2445 0xef800050, 0xefb810f0,
2446 "vorr%v.i%8-11s\t%13-15,22Q, %E"},
2448 /* Vector VQSHL T2 Variant.
2449 NOTE: MVE_VQSHL_T2 must appear in the table before
2450 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2451 {ARM_FEATURE_COPROC (FPU_MVE
),
2453 0xef800750, 0xef801fd1,
2454 "vqshl%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2456 /* Vector VQSHLU T3 Variant
2457 NOTE: MVE_VQSHL_T2 must appear in the table before
2458 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2460 {ARM_FEATURE_COPROC (FPU_MVE
),
2462 0xff800650, 0xff801fd1,
2463 "vqshlu%v.s%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2466 NOTE: MVE_VRSHR must appear in the table before
2467 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2468 {ARM_FEATURE_COPROC (FPU_MVE
),
2470 0xef800250, 0xef801fd1,
2471 "vrshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2474 NOTE: MVE_VSHL must appear in the table before
2475 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2476 {ARM_FEATURE_COPROC (FPU_MVE
),
2478 0xef800550, 0xff801fd1,
2479 "vshl%v.i%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2482 NOTE: MVE_VSHR must appear in the table before
2483 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2484 {ARM_FEATURE_COPROC (FPU_MVE
),
2486 0xef800050, 0xef801fd1,
2487 "vshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2490 NOTE: MVE_VSLI must appear in the table before
2491 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2492 {ARM_FEATURE_COPROC (FPU_MVE
),
2494 0xff800550, 0xff801fd1,
2495 "vsli%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2498 NOTE: MVE_VSRI must appear in the table before
2499 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2500 {ARM_FEATURE_COPROC (FPU_MVE
),
2502 0xff800450, 0xff801fd1,
2503 "vsri%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2505 /* Vector VMOV immediate to vector,
2506 cmode == 11x1 -> VMVN which is UNDEFINED
2507 for such a cmode. */
2508 {ARM_FEATURE_COPROC (FPU_MVE
),
2509 MVE_VMVN_IMM
, 0xef800d50, 0xefb81dd0, UNDEFINED_INSTRUCTION
},
2511 /* Vector VMOV immediate to vector. */
2512 {ARM_FEATURE_COPROC (FPU_MVE
),
2513 MVE_VMOV_IMM_TO_VEC
,
2514 0xef800050, 0xefb810d0,
2515 "vmov%v.%5,8-11s\t%13-15,22Q, %E"},
2517 /* Vector VMOV two 32-bit lanes to two gprs, idx = 0. */
2518 {ARM_FEATURE_COPROC (FPU_MVE
),
2519 MVE_VMOV2_VEC_LANE_TO_GP
,
2520 0xec000f00, 0xffb01ff0,
2521 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[2], %13-15,22Q[0]"},
2523 /* Vector VMOV two 32-bit lanes to two gprs, idx = 1. */
2524 {ARM_FEATURE_COPROC (FPU_MVE
),
2525 MVE_VMOV2_VEC_LANE_TO_GP
,
2526 0xec000f10, 0xffb01ff0,
2527 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[3], %13-15,22Q[1]"},
2529 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 0. */
2530 {ARM_FEATURE_COPROC (FPU_MVE
),
2531 MVE_VMOV2_GP_TO_VEC_LANE
,
2532 0xec100f00, 0xffb01ff0,
2533 "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
2535 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 1. */
2536 {ARM_FEATURE_COPROC (FPU_MVE
),
2537 MVE_VMOV2_GP_TO_VEC_LANE
,
2538 0xec100f10, 0xffb01ff0,
2539 "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
2541 /* Vector VMOV Vector lane to gpr. */
2542 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2543 MVE_VMOV_VEC_LANE_TO_GP
,
2544 0xee100b10, 0xff100f1f,
2545 "vmov%c.%u%5-6,21-22s\t%12-15r, %17-19,7Q[%N]"},
2547 /* Vector VSHLL T1 Variant. Note: VSHLL T1 must appear before MVE_VMOVL due
2548 to instruction opcode aliasing. */
2549 {ARM_FEATURE_COPROC (FPU_MVE
),
2551 0xeea00f40, 0xefa00fd1,
2552 "vshll%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2554 /* Vector VMOVL long. */
2555 {ARM_FEATURE_COPROC (FPU_MVE
),
2557 0xeea00f40, 0xefa70fd1,
2558 "vmovl%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q"},
2560 /* Vector VMOV and narrow. */
2561 {ARM_FEATURE_COPROC (FPU_MVE
),
2563 0xfe310e81, 0xffb30fd1,
2564 "vmovn%T%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2566 /* Floating point move extract. */
2567 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2569 0xfeb00a40, 0xffbf0fd0,
2570 "vmovx.f16\t%22,12-15F, %5,0-3F"},
2572 /* Vector VMULL integer. */
2573 {ARM_FEATURE_COPROC (FPU_MVE
),
2575 0xee010e00, 0xef810f51,
2576 "vmull%T%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2578 /* Vector VMULL polynomial. */
2579 {ARM_FEATURE_COPROC (FPU_MVE
),
2581 0xee310e00, 0xefb10f51,
2582 "vmull%T%v.%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2584 /* Vector VMVN immediate to vector. */
2585 {ARM_FEATURE_COPROC (FPU_MVE
),
2587 0xef800070, 0xefb810f0,
2588 "vmvn%v.i%8-11s\t%13-15,22Q, %E"},
2590 /* Vector VMVN register. */
2591 {ARM_FEATURE_COPROC (FPU_MVE
),
2593 0xffb005c0, 0xffbf1fd1,
2594 "vmvn%v\t%13-15,22Q, %1-3,5Q"},
2596 /* Vector VORN, vector bitwise or not. */
2597 {ARM_FEATURE_COPROC (FPU_MVE
),
2599 0xef300150, 0xffb11f51,
2600 "vorn%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2602 /* Vector VORR register. */
2603 {ARM_FEATURE_COPROC (FPU_MVE
),
2605 0xef200150, 0xffb11f51,
2606 "vorr%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2608 /* Vector VQDMULL T1 variant. */
2609 {ARM_FEATURE_COPROC (FPU_MVE
),
2611 0xee300f01, 0xefb10f51,
2612 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2614 /* Vector VQDMULL T2 variant. */
2615 {ARM_FEATURE_COPROC (FPU_MVE
),
2617 0xee300f60, 0xefb10f70,
2618 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2620 /* Vector VQMOVN. */
2621 {ARM_FEATURE_COPROC (FPU_MVE
),
2623 0xee330e01, 0xefb30fd1,
2624 "vqmovn%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q"},
2626 /* Vector VQMOVUN. */
2627 {ARM_FEATURE_COPROC (FPU_MVE
),
2629 0xee310e81, 0xffb30fd1,
2630 "vqmovun%T%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2632 /* Vector VQDMLADH. */
2633 {ARM_FEATURE_COPROC (FPU_MVE
),
2635 0xee000e00, 0xff810f51,
2636 "vqdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2638 /* Vector VQRDMLADH. */
2639 {ARM_FEATURE_COPROC (FPU_MVE
),
2641 0xee000e01, 0xff810f51,
2642 "vqrdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2644 /* Vector VQDMLAH. */
2645 {ARM_FEATURE_COPROC (FPU_MVE
),
2647 0xee000e60, 0xef811f70,
2648 "vqdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2650 /* Vector VQRDMLAH. */
2651 {ARM_FEATURE_COPROC (FPU_MVE
),
2653 0xee000e40, 0xef811f70,
2654 "vqrdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2656 /* Vector VQDMLASH. */
2657 {ARM_FEATURE_COPROC (FPU_MVE
),
2659 0xee001e60, 0xef811f70,
2660 "vqdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2662 /* Vector VQRDMLASH. */
2663 {ARM_FEATURE_COPROC (FPU_MVE
),
2665 0xee001e40, 0xef811f70,
2666 "vqrdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2668 /* Vector VQDMLSDH. */
2669 {ARM_FEATURE_COPROC (FPU_MVE
),
2671 0xfe000e00, 0xff810f51,
2672 "vqdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2674 /* Vector VQRDMLSDH. */
2675 {ARM_FEATURE_COPROC (FPU_MVE
),
2677 0xfe000e01, 0xff810f51,
2678 "vqrdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2680 /* Vector VQDMULH T1 variant. */
2681 {ARM_FEATURE_COPROC (FPU_MVE
),
2683 0xef000b40, 0xff811f51,
2684 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2686 /* Vector VQRDMULH T2 variant. */
2687 {ARM_FEATURE_COPROC (FPU_MVE
),
2689 0xff000b40, 0xff811f51,
2690 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2692 /* Vector VQDMULH T3 variant. */
2693 {ARM_FEATURE_COPROC (FPU_MVE
),
2695 0xee010e60, 0xff811f70,
2696 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2698 /* Vector VQRDMULH T4 variant. */
2699 {ARM_FEATURE_COPROC (FPU_MVE
),
2701 0xfe010e60, 0xff811f70,
2702 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2704 /* Vector VQRSHL T1 variant. */
2705 {ARM_FEATURE_COPROC (FPU_MVE
),
2707 0xef000550, 0xef811f51,
2708 "vqrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
2710 /* Vector VQRSHL T2 variant. */
2711 {ARM_FEATURE_COPROC (FPU_MVE
),
2713 0xee331ee0, 0xefb31ff0,
2714 "vqrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
2716 /* Vector VQRSHRN. */
2717 {ARM_FEATURE_COPROC (FPU_MVE
),
2719 0xee800f41, 0xefa00fd1,
2720 "vqrshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2722 /* Vector VQRSHRUN. */
2723 {ARM_FEATURE_COPROC (FPU_MVE
),
2725 0xfe800fc0, 0xffa00fd1,
2726 "vqrshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2728 /* Vector VQSHL T1 Variant. */
2729 {ARM_FEATURE_COPROC (FPU_MVE
),
2731 0xee311ee0, 0xefb31ff0,
2732 "vqshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
2734 /* Vector VQSHL T4 Variant. */
2735 {ARM_FEATURE_COPROC (FPU_MVE
),
2737 0xef000450, 0xef811f51,
2738 "vqshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
2740 /* Vector VQSHRN. */
2741 {ARM_FEATURE_COPROC (FPU_MVE
),
2743 0xee800f40, 0xefa00fd1,
2744 "vqshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2746 /* Vector VQSHRUN. */
2747 {ARM_FEATURE_COPROC (FPU_MVE
),
2749 0xee800fc0, 0xffa00fd1,
2750 "vqshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2752 /* Vector VRINT floating point. */
2753 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2755 0xffb20440, 0xffb31c51,
2756 "vrint%m%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
2758 /* Vector VRMLALDAVH. */
2759 {ARM_FEATURE_COPROC (FPU_MVE
),
2761 0xee800f00, 0xef811f51,
2762 "vrmlalvh%5A%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2764 /* Vector VRMLALDAVH. */
2765 {ARM_FEATURE_COPROC (FPU_MVE
),
2767 0xee801f00, 0xef811f51,
2768 "vrmlaldavh%5Ax%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2770 /* Vector VRSHL T1 Variant. */
2771 {ARM_FEATURE_COPROC (FPU_MVE
),
2773 0xef000540, 0xef811f51,
2774 "vrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
2776 /* Vector VRSHL T2 Variant. */
2777 {ARM_FEATURE_COPROC (FPU_MVE
),
2779 0xee331e60, 0xefb31ff0,
2780 "vrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
2782 /* Vector VRSHRN. */
2783 {ARM_FEATURE_COPROC (FPU_MVE
),
2785 0xfe800fc1, 0xffa00fd1,
2786 "vrshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2788 /* Vector VSHL T2 Variant. */
2789 {ARM_FEATURE_COPROC (FPU_MVE
),
2791 0xee311e60, 0xefb31ff0,
2792 "vshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
2794 /* Vector VSHL T3 Variant. */
2795 {ARM_FEATURE_COPROC (FPU_MVE
),
2797 0xef000440, 0xef811f51,
2798 "vshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
2801 {ARM_FEATURE_COPROC (FPU_MVE
),
2803 0xeea00fc0, 0xffa01ff0,
2804 "vshlc%v\t%13-15,22Q, %0-3r, #%16-20d"},
2806 /* Vector VSHLL T2 Variant. */
2807 {ARM_FEATURE_COPROC (FPU_MVE
),
2809 0xee310e01, 0xefb30fd1,
2810 "vshll%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q, #%18-19d"},
2813 {ARM_FEATURE_COPROC (FPU_MVE
),
2815 0xee800fc1, 0xffa00fd1,
2816 "vshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2818 /* Vector VST2 no writeback. */
2819 {ARM_FEATURE_COPROC (FPU_MVE
),
2821 0xfc801e00, 0xffb01e5f,
2822 "vst2%5d.%7-8s\t%B, [%16-19r]"},
2824 /* Vector VST2 writeback. */
2825 {ARM_FEATURE_COPROC (FPU_MVE
),
2827 0xfca01e00, 0xffb01e5f,
2828 "vst2%5d.%7-8s\t%B, [%16-19r]!"},
2830 /* Vector VST4 no writeback. */
2831 {ARM_FEATURE_COPROC (FPU_MVE
),
2833 0xfc801e01, 0xffb01e1f,
2834 "vst4%5-6d.%7-8s\t%B, [%16-19r]"},
2836 /* Vector VST4 writeback. */
2837 {ARM_FEATURE_COPROC (FPU_MVE
),
2839 0xfca01e01, 0xffb01e1f,
2840 "vst4%5-6d.%7-8s\t%B, [%16-19r]!"},
2842 /* Vector VSTRB scatter store, T1 variant. */
2843 {ARM_FEATURE_COPROC (FPU_MVE
),
2844 MVE_VSTRB_SCATTER_T1
,
2845 0xec800e00, 0xffb01e50,
2846 "vstrb%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
2848 /* Vector VSTRH scatter store, T2 variant. */
2849 {ARM_FEATURE_COPROC (FPU_MVE
),
2850 MVE_VSTRH_SCATTER_T2
,
2851 0xec800e10, 0xffb01e50,
2852 "vstrh%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2854 /* Vector VSTRW scatter store, T3 variant. */
2855 {ARM_FEATURE_COPROC (FPU_MVE
),
2856 MVE_VSTRW_SCATTER_T3
,
2857 0xec800e40, 0xffb01e50,
2858 "vstrw%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2860 /* Vector VSTRD scatter store, T4 variant. */
2861 {ARM_FEATURE_COPROC (FPU_MVE
),
2862 MVE_VSTRD_SCATTER_T4
,
2863 0xec800fd0, 0xffb01fd0,
2864 "vstrd%v.64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2866 /* Vector VSTRW scatter store, T5 variant. */
2867 {ARM_FEATURE_COPROC (FPU_MVE
),
2868 MVE_VSTRW_SCATTER_T5
,
2869 0xfd001e00, 0xff111f00,
2870 "vstrw%v.32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2872 /* Vector VSTRD scatter store, T6 variant. */
2873 {ARM_FEATURE_COPROC (FPU_MVE
),
2874 MVE_VSTRD_SCATTER_T6
,
2875 0xfd001f00, 0xff111f00,
2876 "vstrd%v.64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2879 {ARM_FEATURE_COPROC (FPU_MVE
),
2881 0xec000e00, 0xfe581e00,
2882 "vstrb%v.%7-8s\t%13-15Q, %d"},
2885 {ARM_FEATURE_COPROC (FPU_MVE
),
2887 0xec080e00, 0xfe581e00,
2888 "vstrh%v.%7-8s\t%13-15Q, %d"},
2890 /* Vector VSTRB variant T5. */
2891 {ARM_FEATURE_COPROC (FPU_MVE
),
2893 0xec001e00, 0xfe101f80,
2894 "vstrb%v.8\t%13-15,22Q, %d"},
2896 /* Vector VSTRH variant T6. */
2897 {ARM_FEATURE_COPROC (FPU_MVE
),
2899 0xec001e80, 0xfe101f80,
2900 "vstrh%v.16\t%13-15,22Q, %d"},
2902 /* Vector VSTRW variant T7. */
2903 {ARM_FEATURE_COPROC (FPU_MVE
),
2905 0xec001f00, 0xfe101f80,
2906 "vstrw%v.32\t%13-15,22Q, %d"},
2908 {ARM_FEATURE_CORE_LOW (0),
2910 0x00000000, 0x00000000, 0}
2913 /* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
2914 ordered: they must be searched linearly from the top to obtain a correct
2917 /* print_insn_arm recognizes the following format control codes:
2921 %a print address for ldr/str instruction
2922 %s print address for ldr/str halfword/signextend instruction
2923 %S like %s but allow UNPREDICTABLE addressing
2924 %b print branch destination
2925 %c print condition code (always bits 28-31)
2926 %m print register mask for ldm/stm instruction
2927 %o print operand2 (immediate or register + shift)
2928 %p print 'p' iff bits 12-15 are 15
2929 %t print 't' iff bit 21 set and bit 24 clear
2930 %B print arm BLX(1) destination
2931 %C print the PSR sub type.
2932 %U print barrier type.
2933 %P print address for pli instruction.
2935 %<bitfield>r print as an ARM register
2936 %<bitfield>T print as an ARM register + 1
2937 %<bitfield>R as %r but r15 is UNPREDICTABLE
2938 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
2939 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
2940 %<bitfield>d print the bitfield in decimal
2941 %<bitfield>W print the bitfield plus one in decimal
2942 %<bitfield>x print the bitfield in hex
2943 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
2945 %<bitfield>'c print specified char iff bitfield is all ones
2946 %<bitfield>`c print specified char iff bitfield is all zeroes
2947 %<bitfield>?ab... select from array of values in big endian order
2949 %e print arm SMI operand (bits 0..7,8..19).
2950 %E print the LSB and WIDTH fields of a BFI or BFC instruction.
2951 %V print the 16-bit immediate field of a MOVT or MOVW instruction.
2952 %R print the SPSR/CPSR or banked register of an MRS. */
2954 static const struct opcode32 arm_opcodes
[] =
2956 /* ARM instructions. */
2957 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2958 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
2959 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2960 0xe7f000f0, 0xfff000f0, "udf\t#%e"},
2962 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
),
2963 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
2964 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
2965 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
2966 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
2967 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2968 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
),
2969 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
2970 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
),
2971 0x00800090, 0x0fa000f0,
2972 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2973 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
),
2974 0x00a00090, 0x0fa000f0,
2975 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2977 /* V8.2 RAS extension instructions. */
2978 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
2979 0xe320f010, 0xffffffff, "esb"},
2981 /* V8 instructions. */
2982 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
2983 0x0320f005, 0x0fffffff, "sevl"},
2984 /* Defined in V8 but is in NOP space so available to all arch. */
2985 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2986 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
2987 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
),
2988 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
2989 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
2990 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
2991 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
2992 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
2993 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
2994 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
2995 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
2996 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
2997 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
2998 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
2999 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3000 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
3001 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3002 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
3003 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3004 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
3005 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3006 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
3007 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3008 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
3009 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3010 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
3011 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3012 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
3013 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3014 0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
3015 /* CRC32 instructions. */
3016 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
3017 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
3018 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
3019 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
3020 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
3021 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
3022 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
3023 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
3024 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
3025 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
3026 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
3027 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
3029 /* Privileged Access Never extension instructions. */
3030 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
3031 0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
3033 /* Virtualization Extension instructions. */
3034 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
), 0x0160006e, 0x0fffffff, "eret%c"},
3035 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
3037 /* Integer Divide Extension instructions. */
3038 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
3039 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
3040 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
3041 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
3043 /* MP Extension instructions. */
3044 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP
), 0xf410f000, 0xfc70f000, "pldw\t%a"},
3046 /* Speculation Barriers. */
3047 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
), 0xe320f014, 0xffffffff, "csdb"},
3048 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
), 0xf57ff040, 0xffffffff, "ssbb"},
3049 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
), 0xf57ff044, 0xffffffff, "pssbb"},
3051 /* V7 instructions. */
3052 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf450f000, 0xfd70f000, "pli\t%P"},
3053 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
3054 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
3055 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
3056 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
3057 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
3058 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf57ff060, 0xfffffff0, "isb\t%U"},
3059 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
),
3060 0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
3062 /* ARM V6T2 instructions. */
3063 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3064 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
3065 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3066 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
3067 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3068 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3069 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3070 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
3072 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3073 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION
},
3074 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3075 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
3077 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3078 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
3079 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3080 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
3081 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3082 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
3083 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3084 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
3086 /* ARM Security extension instructions. */
3087 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
3088 0x01600070, 0x0ff000f0, "smc%c\t%e"},
3090 /* ARM V6K instructions. */
3091 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3092 0xf57ff01f, 0xffffffff, "clrex"},
3093 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3094 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
3095 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3096 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
3097 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3098 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
3099 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3100 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
3101 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3102 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
3103 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3104 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
3106 /* ARMv8.5-A instructions. */
3107 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
), 0xf57ff070, 0xffffffff, "sb"},
3109 /* ARM V6K NOP hints. */
3110 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3111 0x0320f001, 0x0fffffff, "yield%c"},
3112 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3113 0x0320f002, 0x0fffffff, "wfe%c"},
3114 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3115 0x0320f003, 0x0fffffff, "wfi%c"},
3116 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3117 0x0320f004, 0x0fffffff, "sev%c"},
3118 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3119 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
3121 /* ARM V6 instructions. */
3122 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3123 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
3124 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3125 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
3126 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3127 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
3128 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3129 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
3130 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3131 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
3132 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3133 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
3134 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3135 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
3136 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3137 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
3138 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3139 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
3140 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3141 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
3142 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3143 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
3144 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3145 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
3146 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3147 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
3148 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3149 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
3150 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3151 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
3152 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3153 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
3154 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3155 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
3156 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3157 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
3158 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3159 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
3160 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3161 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
3162 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3163 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
3164 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3165 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
3166 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3167 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
3168 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3169 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
3170 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3171 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
3172 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3173 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
3174 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3175 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
3176 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3177 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
3178 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3179 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
3180 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3181 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
3182 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3183 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
3184 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3185 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
3186 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3187 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
3188 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3189 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
3190 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3191 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
3192 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3193 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
3194 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3195 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
3196 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3197 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
3198 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3199 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
3200 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3201 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
3202 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3203 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
3204 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3205 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
3206 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3207 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
3208 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3209 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
3210 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3211 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
3212 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3213 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
3214 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3215 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
3216 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3217 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
3218 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3219 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
3220 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3221 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
3222 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3223 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
3224 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3225 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
3226 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3227 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
3228 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3229 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
3230 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3231 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
3232 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3233 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
3234 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3235 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
3236 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3237 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
3238 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3239 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
3240 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3241 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
3242 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3243 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
3244 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3245 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
3246 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3247 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
3248 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3249 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
3250 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3251 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
3252 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3253 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
3254 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3255 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
3256 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3257 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
3258 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3259 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
3260 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3261 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
3262 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3263 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
3264 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3265 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
3266 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3267 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
3268 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3269 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
3270 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3271 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
3272 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3273 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3274 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3275 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3276 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3277 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3278 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3279 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
3280 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3281 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3282 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3283 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3284 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3285 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3286 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3287 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
3288 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3289 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3290 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3291 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3292 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3293 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3294 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3295 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
3296 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3297 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3298 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3299 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3300 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3301 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3302 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3303 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
3304 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3305 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3306 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3307 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3308 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3309 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
3310 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3311 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
3312 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3313 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3314 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3315 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3316 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3317 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3318 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3319 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
3320 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3321 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
3322 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3323 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
3324 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3325 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
3326 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3327 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3328 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3329 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3330 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3331 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3332 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3333 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3334 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3335 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
3336 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3337 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3338 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3339 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3340 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3341 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
3342 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3343 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
3344 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3345 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
3346 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3347 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
3348 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3349 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
3350 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3351 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
3352 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3353 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
3354 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3355 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
3356 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3357 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3358 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3359 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
3360 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3361 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
3362 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3363 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
3364 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3365 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
3367 /* V5J instruction. */
3368 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
),
3369 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
3371 /* V5 Instructions. */
3372 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
3373 0xe1200070, 0xfff000f0,
3374 "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
3375 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
3376 0xfa000000, 0xfe000000, "blx\t%B"},
3377 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
3378 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
3379 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
3380 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
3382 /* V5E "El Segundo" Instructions. */
3383 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
3384 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
3385 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
3386 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
3387 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
3388 0xf450f000, 0xfc70f000, "pld\t%a"},
3389 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3390 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3391 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3392 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3393 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3394 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3395 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3396 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
3398 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3399 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3400 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3401 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
3403 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3404 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3405 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3406 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3407 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3408 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3409 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3410 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3412 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3413 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
3414 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3415 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
3416 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3417 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
3418 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3419 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
3421 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3422 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
3423 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3424 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
3426 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3427 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"},
3428 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3429 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
3430 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3431 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"},
3432 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3433 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
3435 /* ARM Instructions. */
3436 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3437 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
3439 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3440 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
3441 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3442 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
3443 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3444 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
3445 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3446 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
3447 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3448 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
3449 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3450 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
3452 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3453 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
3454 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3455 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
3456 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3457 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
3458 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3459 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
3461 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3462 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION
},
3463 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3464 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
3465 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3466 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION
},
3467 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3468 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
3470 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3471 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
3472 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3473 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
3474 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3475 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
3477 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3478 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
3479 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3480 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
3481 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3482 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
3484 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3485 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
3486 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3487 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
3488 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3489 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
3491 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3492 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
3493 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3494 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
3495 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3496 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
3498 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3499 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
3500 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3501 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
3502 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3503 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
3505 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3506 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
3507 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3508 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
3509 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3510 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
3512 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3513 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
3514 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3515 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
3516 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3517 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
3519 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3520 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
3521 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3522 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
3523 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3524 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
3526 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
3527 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
3528 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
),
3529 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
3530 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
),
3531 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
3533 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3534 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
3535 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3536 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
3537 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3538 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
3540 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3541 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
3542 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3543 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
3544 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3545 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
3547 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3548 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
3549 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3550 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
3551 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3552 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
3554 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3555 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
3556 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3557 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
3558 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3559 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
3561 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3562 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
3563 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3564 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
3565 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3566 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
3568 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3569 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
3570 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3571 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
3572 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3573 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
3574 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3575 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
3576 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3577 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
3578 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3579 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
3580 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3581 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
3583 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3584 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
3585 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3586 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
3587 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3588 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
3590 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3591 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
3592 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3593 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
3594 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3595 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
3597 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3598 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION
},
3599 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3600 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
3602 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3603 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
3605 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3606 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
3607 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3608 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
3610 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3611 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3612 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3613 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3614 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3615 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3616 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3617 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3618 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3619 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3620 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3621 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3622 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3623 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3624 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3625 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3626 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3627 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3628 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3629 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3630 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3631 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3632 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3633 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3634 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3635 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3636 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3637 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3638 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3639 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3640 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3641 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3642 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3643 0x092d0000, 0x0fff0000, "push%c\t%m"},
3644 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3645 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
3646 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3647 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
3649 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3650 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3651 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3652 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3653 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3654 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3655 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3656 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3657 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3658 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3659 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3660 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3661 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3662 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3663 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3664 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3665 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3666 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3667 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3668 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3669 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3670 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3671 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3672 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3673 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3674 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3675 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3676 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3677 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3678 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3679 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3680 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3681 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3682 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
3683 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3684 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
3685 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3686 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
3688 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3689 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
3690 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3691 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
3694 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
),
3695 0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION
},
3696 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3697 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION
},
3698 {ARM_FEATURE_CORE_LOW (0),
3699 0x00000000, 0x00000000, 0}
3702 /* print_insn_thumb16 recognizes the following format control codes:
3704 %S print Thumb register (bits 3..5 as high number if bit 6 set)
3705 %D print Thumb register (bits 0..2 as high number if bit 7 set)
3706 %<bitfield>I print bitfield as a signed decimal
3707 (top bit of range being the sign bit)
3708 %N print Thumb register mask (with LR)
3709 %O print Thumb register mask (with PC)
3710 %M print Thumb register mask
3711 %b print CZB's 6-bit unsigned branch destination
3712 %s print Thumb right-shift immediate (6..10; 0 == 32).
3713 %c print the condition code
3714 %C print the condition code, or "s" if not conditional
3715 %x print warning if conditional an not at end of IT block"
3716 %X print "\t; unpredictable <IT:code>" if conditional
3717 %I print IT instruction suffix and operands
3718 %W print Thumb Writeback indicator for LDMIA
3719 %<bitfield>r print bitfield as an ARM register
3720 %<bitfield>d print bitfield as a decimal
3721 %<bitfield>H print (bitfield * 2) as a decimal
3722 %<bitfield>W print (bitfield * 4) as a decimal
3723 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
3724 %<bitfield>B print Thumb branch destination (signed displacement)
3725 %<bitfield>c print bitfield as a condition code
3726 %<bitnum>'c print specified char iff bit is one
3727 %<bitnum>?ab print a if bit is one else print b. */
3729 static const struct opcode16 thumb_opcodes
[] =
3731 /* Thumb instructions. */
3733 /* ARMv8-M Security Extensions instructions. */
3734 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
), 0x4784, 0xff87, "blxns\t%3-6r"},
3735 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
), 0x4704, 0xff87, "bxns\t%3-6r"},
3737 /* ARM V8 instructions. */
3738 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xbf50, 0xffff, "sevl%c"},
3739 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xba80, 0xffc0, "hlt\t%0-5x"},
3740 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
), 0xb610, 0xfff7, "setpan\t#%3-3d"},
3742 /* ARM V6K no-argument instructions. */
3743 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf00, 0xffff, "nop%c"},
3744 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf10, 0xffff, "yield%c"},
3745 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf20, 0xffff, "wfe%c"},
3746 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf30, 0xffff, "wfi%c"},
3747 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf40, 0xffff, "sev%c"},
3748 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
3750 /* ARM V6T2 instructions. */
3751 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3752 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
3753 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3754 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
3755 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xbf00, 0xff00, "it%I%X"},
3758 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
3759 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
3760 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
3761 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
3762 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
3763 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
3764 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb650, 0xfff7, "setend\t%3?ble%X"},
3765 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
3766 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
3767 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
3768 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
3770 /* ARM V5 ISA extends Thumb. */
3771 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
),
3772 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
3773 /* This is BLX(2). BLX(1) is a 32-bit instruction. */
3774 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
),
3775 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
3776 /* ARM V4T ISA (Thumb v1). */
3777 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3778 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
3780 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
3781 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
3782 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
3783 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
3784 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
3785 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
3786 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
3787 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
3788 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
3789 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
3790 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
3791 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
3792 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
3793 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
3794 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
3795 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
3797 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
3798 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
3800 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4700, 0xFF80, "bx%c\t%S%x"},
3801 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4400, 0xFF00, "add%c\t%D, %S"},
3802 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
3803 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4600, 0xFF00, "mov%c\t%D, %S"},
3805 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xB400, 0xFE00, "push%c\t%N"},
3806 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xBC00, 0xFE00, "pop%c\t%O"},
3808 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3809 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
3810 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3811 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
3812 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3813 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
3814 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3815 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
3817 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3818 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
3819 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3820 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
3821 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3822 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
3824 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3825 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
3826 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3827 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
3829 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
3830 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3831 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
3832 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
3833 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
3835 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
3836 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
3837 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
3838 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
3840 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
3841 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3843 "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
3845 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3846 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
3847 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3848 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
3849 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3850 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
3851 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3852 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
3854 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3855 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
3856 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3857 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
3859 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3860 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
3861 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3862 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
3864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3865 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
3866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3867 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
3869 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
3870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
3872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
3874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
3875 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION
},
3876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
3878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
3880 /* The E800 .. FFFF range is unconditionally redirected to the
3881 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
3882 are processed via that table. Thus, we can never encounter a
3883 bare "second half of BL/BLX(1)" instruction here. */
3884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
), 0x0000, 0x0000, UNDEFINED_INSTRUCTION
},
3885 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
3888 /* Thumb32 opcodes use the same table structure as the ARM opcodes.
3889 We adopt the convention that hw1 is the high 16 bits of .value and
3890 .mask, hw2 the low 16 bits.
3892 print_insn_thumb32 recognizes the following format control codes:
3896 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
3897 %M print a modified 12-bit immediate (same location)
3898 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
3899 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
3900 %H print a 16-bit immediate from hw2[3:0],hw1[11:0]
3901 %S print a possibly-shifted Rm
3903 %L print address for a ldrd/strd instruction
3904 %a print the address of a plain load/store
3905 %w print the width and signedness of a core load/store
3906 %m print register mask for ldm/stm
3907 %n print register mask for clrm
3909 %E print the lsb and width fields of a bfc/bfi instruction
3910 %F print the lsb and width fields of a sbfx/ubfx instruction
3911 %G print a fallback offset for Branch Future instructions
3912 %W print an offset for BF instruction
3913 %Y print an offset for BFL instruction
3914 %Z print an offset for BFCSEL instruction
3915 %Q print an offset for Low Overhead Loop instructions
3916 %P print an offset for Low Overhead Loop end instructions
3917 %b print a conditional branch offset
3918 %B print an unconditional branch offset
3919 %s print the shift field of an SSAT instruction
3920 %R print the rotation field of an SXT instruction
3921 %U print barrier type.
3922 %P print address for pli instruction.
3923 %c print the condition code
3924 %x print warning if conditional an not at end of IT block"
3925 %X print "\t; unpredictable <IT:code>" if conditional
3927 %<bitfield>d print bitfield in decimal
3928 %<bitfield>D print bitfield plus one in decimal
3929 %<bitfield>W print bitfield*4 in decimal
3930 %<bitfield>r print bitfield as an ARM register
3931 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
3932 %<bitfield>S as %<>r but r13 and r15 is UNPREDICTABLE
3933 %<bitfield>c print bitfield as a condition code
3935 %<bitfield>'c print specified char iff bitfield is all ones
3936 %<bitfield>`c print specified char iff bitfield is all zeroes
3937 %<bitfield>?ab... select from array of values in big endian order
3939 With one exception at the bottom (done because BL and BLX(1) need
3940 to come dead last), this table was machine-sorted first in
3941 decreasing order of number of bits set in the mask, then in
3942 increasing numeric order of mask, then in increasing numeric order
3943 of opcode. This order is not the clearest for a human reader, but
3944 is guaranteed never to catch a special-case bit pattern with a more
3945 general mask, which is important, because this instruction encoding
3946 makes heavy use of special-case bit patterns. */
3947 static const struct opcode32 thumb32_opcodes
[] =
3949 /* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions
3951 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3952 0xf040c001, 0xfff0f001, "wls\tlr, %16-19S, %Q"},
3953 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3954 0xf040e001, 0xfff0ffff, "dls\tlr, %16-19S"},
3955 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3956 0xf02fc001, 0xfffff001, "le\t%P"},
3957 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3958 0xf00fc001, 0xfffff001, "le\tlr, %P"},
3960 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3961 0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
3962 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3963 0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"},
3964 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3965 0xf000c001, 0xf800f001, "bfl%c\t%G, %Y"},
3966 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3967 0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"},
3968 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3969 0xf000e001, 0xf840f001, "bfcsel\t%G, %Z, %18-21c"},
3971 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3972 0xe89f0000, 0xffff2000, "clrm%c\t%n"},
3974 /* ARMv8-M and ARMv8-M Security Extensions instructions. */
3975 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
), 0xe97fe97f, 0xffffffff, "sg"},
3976 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
),
3977 0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
3978 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
),
3979 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
3980 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
),
3981 0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
3982 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
),
3983 0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
3985 /* ARM V8.2 RAS extension instructions. */
3986 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
3987 0xf3af8010, 0xffffffff, "esb"},
3989 /* V8 instructions. */
3990 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3991 0xf3af8005, 0xffffffff, "sevl%c.w"},
3992 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3993 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
3994 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3995 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
3996 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3997 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
3998 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3999 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
4000 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4001 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
4002 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4003 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
4004 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4005 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
4006 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4007 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
4008 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4009 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
4010 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4011 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
4012 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4013 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
4014 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4015 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
4016 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4017 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
4018 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4019 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
4020 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4021 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
4023 /* CRC32 instructions. */
4024 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
4025 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},
4026 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
4027 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"},
4028 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
4029 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"},
4030 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
4031 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"},
4032 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
4033 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"},
4034 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
4035 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
4037 /* Speculation Barriers. */
4038 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8014, 0xffffffff, "csdb"},
4039 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3bf8f40, 0xffffffff, "ssbb"},
4040 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3bf8f44, 0xffffffff, "pssbb"},
4042 /* V7 instructions. */
4043 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf910f000, 0xff70f000, "pli%c\t%a"},
4044 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
4045 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
4046 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
4047 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
4048 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
4049 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
4050 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
4051 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
4052 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
4053 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
4055 /* Virtualization Extension instructions. */
4056 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
4057 /* We skip ERET as that is SUBS pc, lr, #0. */
4059 /* MP Extension instructions. */
4060 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP
), 0xf830f000, 0xff70f000, "pldw%c\t%a"},
4062 /* Security extension instructions. */
4063 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
), 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
4065 /* ARMv8.5-A instructions. */
4066 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
), 0xf3bf8f70, 0xffffffff, "sb"},
4068 /* Instructions defined in the basic V6T2 set. */
4069 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8000, 0xffffffff, "nop%c.w"},
4070 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8001, 0xffffffff, "yield%c.w"},
4071 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8002, 0xffffffff, "wfe%c.w"},
4072 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8003, 0xffffffff, "wfi%c.w"},
4073 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8004, 0xffffffff, "sev%c.w"},
4074 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4075 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
4076 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
4078 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4079 0xf3bf8f2f, 0xffffffff, "clrex%c"},
4080 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4081 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
4082 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4083 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
4084 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4085 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
4086 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4087 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
4088 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4089 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
4090 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4091 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
4092 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4093 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
4094 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4095 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
4096 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4097 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
4098 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4099 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
4100 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4101 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
4102 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4103 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
4104 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4105 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
4106 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4107 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
4108 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4109 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
4110 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4111 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
4112 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4113 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
4114 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4115 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
4116 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4117 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
4118 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4119 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
4120 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4121 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
4122 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4123 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
4124 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4125 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
4126 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4127 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
4128 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4129 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
4130 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4131 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
4132 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4133 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
4134 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4135 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
4136 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4137 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
4138 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4139 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
4140 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4141 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
4142 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4143 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
4144 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4145 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
4146 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4147 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
4148 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4149 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
4150 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4151 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
4152 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4153 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
4154 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4155 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
4156 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4157 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
4158 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4159 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
4160 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4161 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
4162 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4163 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
4164 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4165 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
4166 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4167 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
4168 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4169 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
4170 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4171 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
4172 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4173 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
4174 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4175 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
4176 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4177 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
4178 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4179 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
4180 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4181 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
4182 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4183 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
4184 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4185 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
4186 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4187 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
4188 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4189 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
4190 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4191 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
4192 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4193 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
4194 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4195 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
4196 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4197 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
4198 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4199 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
4200 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4201 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
4202 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4203 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
4204 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4205 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
4206 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4207 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
4208 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4209 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
4210 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4211 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
4212 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4213 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
4214 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4215 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
4216 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4217 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
4218 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4219 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
4220 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4221 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
4222 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4223 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
4224 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4225 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
4226 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4227 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4228 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4229 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4230 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4231 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4232 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4233 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
4234 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4235 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
4236 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4237 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
4238 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4239 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
4240 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4241 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
4242 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4243 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4244 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4245 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
4246 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4247 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
4248 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4249 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4250 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4251 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4252 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4253 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4254 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4255 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4256 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4257 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4258 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4259 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4260 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4261 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4262 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4263 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
4264 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4265 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
4266 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4267 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
4268 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4269 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
4270 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4271 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
4272 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4273 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
4274 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4275 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
4276 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4277 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
4278 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4279 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
4280 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4281 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
4282 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4283 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
4284 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4285 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
4286 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4287 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4288 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4289 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4290 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4291 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4292 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4293 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4294 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4295 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4296 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4297 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4298 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4299 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4300 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4301 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4302 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4303 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
4304 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4305 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
4306 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4307 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
4308 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4309 0xf810f000, 0xff70f000, "pld%c\t%a"},
4310 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4311 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4312 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4313 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4314 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4315 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4316 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4317 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4318 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4319 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4320 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4321 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4322 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4323 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4324 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4325 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
4326 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4327 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
4328 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4329 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
4330 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4331 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
4332 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4333 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
4334 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4335 0xfb100000, 0xfff000c0,
4336 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4337 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4338 0xfbc00080, 0xfff000c0,
4339 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
4340 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4341 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
4342 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4343 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
4344 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4345 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
4346 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4347 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
4348 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4349 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
4350 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4351 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
4352 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4353 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
4354 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4355 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
4356 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4357 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
4358 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4359 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
4360 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4361 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
4362 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4363 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
4364 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4365 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
4366 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4367 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
4368 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4369 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
4370 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4371 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
4372 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4373 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
4374 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4375 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
4376 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4377 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
4378 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4379 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
4380 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4381 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
4382 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4383 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
4384 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4385 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
4386 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4387 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
4388 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4389 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
4390 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4391 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
4392 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4393 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
4394 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4395 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
4396 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4397 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
4398 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4399 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
4400 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4401 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
4402 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4403 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
4404 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4405 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
4406 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4407 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
4408 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4409 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
4410 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4411 0xe9400000, 0xff500000,
4412 "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
4413 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4414 0xe9500000, 0xff500000,
4415 "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
4416 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4417 0xe8600000, 0xff700000,
4418 "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
4419 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4420 0xe8700000, 0xff700000,
4421 "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
4422 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4423 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
4424 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4425 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
4427 /* Filter out Bcc with cond=E or F, which are used for other instructions. */
4428 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4429 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
4430 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4431 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
4432 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4433 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
4434 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4435 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
4437 /* These have been 32-bit since the invention of Thumb. */
4438 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4439 0xf000c000, 0xf800d001, "blx%c\t%B%x"},
4440 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4441 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
4444 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4445 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION
},
4446 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
4449 static const char *const arm_conditional
[] =
4450 {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
4451 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
4453 static const char *const arm_fp_const
[] =
4454 {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
4456 static const char *const arm_shift
[] =
4457 {"lsl", "lsr", "asr", "ror"};
4462 const char *description
;
4463 const char *reg_names
[16];
4467 static const arm_regname regnames
[] =
4469 { "reg-names-raw", N_("Select raw register names"),
4470 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
4471 { "reg-names-gcc", N_("Select register names used by GCC"),
4472 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
4473 { "reg-names-std", N_("Select register names used in ARM's ISA documentation"),
4474 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
4475 { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL
} },
4476 { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL
} },
4477 { "reg-names-apcs", N_("Select register names used in the APCS"),
4478 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
4479 { "reg-names-atpcs", N_("Select register names used in the ATPCS"),
4480 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
4481 { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
4482 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }}
4485 static const char *const iwmmxt_wwnames
[] =
4486 {"b", "h", "w", "d"};
4488 static const char *const iwmmxt_wwssnames
[] =
4489 {"b", "bus", "bc", "bss",
4490 "h", "hus", "hc", "hss",
4491 "w", "wus", "wc", "wss",
4492 "d", "dus", "dc", "dss"
4495 static const char *const iwmmxt_regnames
[] =
4496 { "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
4497 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
4500 static const char *const iwmmxt_cregnames
[] =
4501 { "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
4502 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
4505 static const char *const vec_condnames
[] =
4506 { "eq", "ne", "cs", "hi", "ge", "lt", "gt", "le"
4509 static const char *const mve_predicatenames
[] =
4510 { "", "ttt", "tt", "tte", "t", "tee", "te", "tet", "",
4511 "eee", "ee", "eet", "e", "ett", "et", "ete"
4514 /* Names for 2-bit size field for mve vector isntructions. */
4515 static const char *const mve_vec_sizename
[] =
4516 { "8", "16", "32", "64"};
4518 /* Indicates whether we are processing a then predicate,
4519 else predicate or none at all. */
4527 /* Information used to process a vpt block and subsequent instructions. */
4530 /* Are we in a vpt block. */
4531 bfd_boolean in_vpt_block
;
4533 /* Next predicate state if in vpt block. */
4534 enum vpt_pred_state next_pred_state
;
4536 /* Mask from vpt/vpst instruction. */
4537 long predicate_mask
;
4539 /* Instruction number in vpt block. */
4540 long current_insn_num
;
4542 /* Number of instructions in vpt block.. */
4546 static struct vpt_block vpt_block_state
=
4555 /* Default to GCC register name set. */
4556 static unsigned int regname_selected
= 1;
4558 #define NUM_ARM_OPTIONS ARRAY_SIZE (regnames)
4559 #define arm_regnames regnames[regname_selected].reg_names
4561 static bfd_boolean force_thumb
= FALSE
;
4563 /* Current IT instruction state. This contains the same state as the IT
4564 bits in the CPSR. */
4565 static unsigned int ifthen_state
;
4566 /* IT state for the next instruction. */
4567 static unsigned int ifthen_next_state
;
4568 /* The address of the insn for which the IT state is valid. */
4569 static bfd_vma ifthen_address
;
4570 #define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
4571 /* Indicates that the current Conditional state is unconditional or outside
4573 #define COND_UNCOND 16
4577 /* Extract the predicate mask for a VPT or VPST instruction.
4578 The mask is composed of bits 13-15 (Mkl) and bit 22 (Mkh). */
4581 mve_extract_pred_mask (long given
)
4583 return ((given
& 0x00400000) >> 19) | ((given
& 0xe000) >> 13);
4586 /* Return the number of instructions in a MVE predicate block. */
4588 num_instructions_vpt_block (long given
)
4590 long mask
= mve_extract_pred_mask (given
);
4597 if ((mask
& 7) == 4)
4600 if ((mask
& 3) == 2)
4603 if ((mask
& 1) == 1)
4610 mark_outside_vpt_block (void)
4612 vpt_block_state
.in_vpt_block
= FALSE
;
4613 vpt_block_state
.next_pred_state
= PRED_NONE
;
4614 vpt_block_state
.predicate_mask
= 0;
4615 vpt_block_state
.current_insn_num
= 0;
4616 vpt_block_state
.num_pred_insn
= 0;
4620 mark_inside_vpt_block (long given
)
4622 vpt_block_state
.in_vpt_block
= TRUE
;
4623 vpt_block_state
.next_pred_state
= PRED_THEN
;
4624 vpt_block_state
.predicate_mask
= mve_extract_pred_mask (given
);
4625 vpt_block_state
.current_insn_num
= 0;
4626 vpt_block_state
.num_pred_insn
= num_instructions_vpt_block (given
);
4627 assert (vpt_block_state
.num_pred_insn
>= 1);
4630 static enum vpt_pred_state
4631 invert_next_predicate_state (enum vpt_pred_state astate
)
4633 if (astate
== PRED_THEN
)
4635 else if (astate
== PRED_ELSE
)
4641 static enum vpt_pred_state
4642 update_next_predicate_state (void)
4644 long pred_mask
= vpt_block_state
.predicate_mask
;
4645 long mask_for_insn
= 0;
4647 switch (vpt_block_state
.current_insn_num
)
4665 if (pred_mask
& mask_for_insn
)
4666 return invert_next_predicate_state (vpt_block_state
.next_pred_state
);
4668 return vpt_block_state
.next_pred_state
;
4672 update_vpt_block_state (void)
4674 vpt_block_state
.current_insn_num
++;
4675 if (vpt_block_state
.current_insn_num
== vpt_block_state
.num_pred_insn
)
4677 /* No more instructions to process in vpt block. */
4678 mark_outside_vpt_block ();
4682 vpt_block_state
.next_pred_state
= update_next_predicate_state ();
4685 /* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
4686 Returns pointer to following character of the format string and
4687 fills in *VALUEP and *WIDTHP with the extracted value and number of
4688 bits extracted. WIDTHP can be NULL. */
4691 arm_decode_bitfield (const char *ptr
,
4693 unsigned long *valuep
,
4696 unsigned long value
= 0;
4704 for (start
= 0; *ptr
>= '0' && *ptr
<= '9'; ptr
++)
4705 start
= start
* 10 + *ptr
- '0';
4707 for (end
= 0, ptr
++; *ptr
>= '0' && *ptr
<= '9'; ptr
++)
4708 end
= end
* 10 + *ptr
- '0';
4714 value
|= ((insn
>> start
) & ((2ul << bits
) - 1)) << width
;
4717 while (*ptr
++ == ',');
4725 arm_decode_shift (long given
, fprintf_ftype func
, void *stream
,
4726 bfd_boolean print_shift
)
4728 func (stream
, "%s", arm_regnames
[given
& 0xf]);
4730 if ((given
& 0xff0) != 0)
4732 if ((given
& 0x10) == 0)
4734 int amount
= (given
& 0xf80) >> 7;
4735 int shift
= (given
& 0x60) >> 5;
4741 func (stream
, ", rrx");
4749 func (stream
, ", %s #%d", arm_shift
[shift
], amount
);
4751 func (stream
, ", #%d", amount
);
4753 else if ((given
& 0x80) == 0x80)
4754 func (stream
, "\t; <illegal shifter operand>");
4755 else if (print_shift
)
4756 func (stream
, ", %s %s", arm_shift
[(given
& 0x60) >> 5],
4757 arm_regnames
[(given
& 0xf00) >> 8]);
4759 func (stream
, ", %s", arm_regnames
[(given
& 0xf00) >> 8]);
4763 /* Return TRUE if the MATCHED_INSN can be inside an IT block. */
4766 is_mve_okay_in_it (enum mve_instructions matched_insn
)
4768 switch (matched_insn
)
4770 case MVE_VMOV_GP_TO_VEC_LANE
:
4771 case MVE_VMOV2_VEC_LANE_TO_GP
:
4772 case MVE_VMOV2_GP_TO_VEC_LANE
:
4773 case MVE_VMOV_VEC_LANE_TO_GP
:
4781 is_mve_architecture (struct disassemble_info
*info
)
4783 struct arm_private_data
*private_data
= info
->private_data
;
4784 arm_feature_set allowed_arches
= private_data
->features
;
4786 arm_feature_set arm_ext_v8_1m_main
4787 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
);
4789 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main
, allowed_arches
)
4790 && !ARM_CPU_IS_ANY (allowed_arches
))
4797 is_vpt_instruction (long given
)
4800 /* If mkh:mkl is '0000' then its not a vpt/vpst instruction. */
4801 if ((given
& 0x0040e000) == 0)
4804 /* VPT floating point T1 variant. */
4805 if (((given
& 0xefb10f50) == 0xee310f00 && ((given
& 0x1001) != 0x1))
4806 /* VPT floating point T2 variant. */
4807 || ((given
& 0xefb10f50) == 0xee310f40)
4808 /* VPT vector T1 variant. */
4809 || ((given
& 0xff811f51) == 0xfe010f00)
4810 /* VPT vector T2 variant. */
4811 || ((given
& 0xff811f51) == 0xfe010f01
4812 && ((given
& 0x300000) != 0x300000))
4813 /* VPT vector T3 variant. */
4814 || ((given
& 0xff811f50) == 0xfe011f00)
4815 /* VPT vector T4 variant. */
4816 || ((given
& 0xff811f70) == 0xfe010f40)
4817 /* VPT vector T5 variant. */
4818 || ((given
& 0xff811f70) == 0xfe010f60)
4819 /* VPT vector T6 variant. */
4820 || ((given
& 0xff811f50) == 0xfe011f40)
4821 /* VPST vector T variant. */
4822 || ((given
& 0xffbf1fff) == 0xfe310f4d))
4828 /* Decode a bitfield from opcode GIVEN, with starting bitfield = START
4829 and ending bitfield = END. END must be greater than START. */
4831 static unsigned long
4832 arm_decode_field (unsigned long given
, unsigned int start
, unsigned int end
)
4834 int bits
= end
- start
;
4839 return ((given
>> start
) & ((2ul << bits
) - 1));
4842 /* Decode a bitfield from opcode GIVEN, with multiple bitfields:
4843 START:END and START2:END2. END/END2 must be greater than
4846 static unsigned long
4847 arm_decode_field_multiple (unsigned long given
, unsigned int start
,
4848 unsigned int end
, unsigned int start2
,
4851 int bits
= end
- start
;
4852 int bits2
= end2
- start2
;
4853 unsigned long value
= 0;
4859 value
= arm_decode_field (given
, start
, end
);
4862 value
|= ((given
>> start2
) & ((2ul << bits2
) - 1)) << width
;
4866 /* Return TRUE if the GIVEN encoding should not be decoded as MATCHED_INSN.
4867 This helps us decode instructions that change mnemonic depending on specific
4868 operand values/encodings. */
4871 is_mve_encoding_conflict (unsigned long given
,
4872 enum mve_instructions matched_insn
)
4874 switch (matched_insn
)
4877 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) == 0)
4883 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) == 0)
4885 if ((arm_decode_field (given
, 12, 12) == 0)
4886 && (arm_decode_field (given
, 0, 0) == 1))
4891 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) == 0)
4893 if (arm_decode_field (given
, 0, 3) == 0xd)
4897 case MVE_VPT_VEC_T1
:
4898 case MVE_VPT_VEC_T2
:
4899 case MVE_VPT_VEC_T3
:
4900 case MVE_VPT_VEC_T4
:
4901 case MVE_VPT_VEC_T5
:
4902 case MVE_VPT_VEC_T6
:
4903 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) == 0)
4905 if (arm_decode_field (given
, 20, 21) == 3)
4909 case MVE_VCMP_FP_T1
:
4910 if ((arm_decode_field (given
, 12, 12) == 0)
4911 && (arm_decode_field (given
, 0, 0) == 1))
4916 case MVE_VCMP_FP_T2
:
4917 if (arm_decode_field (given
, 0, 3) == 0xd)
4937 case MVE_VQDMULH_T3
:
4938 case MVE_VQRDMULH_T4
:
4944 case MVE_VCMP_VEC_T1
:
4945 case MVE_VCMP_VEC_T2
:
4946 case MVE_VCMP_VEC_T3
:
4947 case MVE_VCMP_VEC_T4
:
4948 case MVE_VCMP_VEC_T5
:
4949 case MVE_VCMP_VEC_T6
:
4950 if (arm_decode_field (given
, 20, 21) == 3)
4959 if (arm_decode_field (given
, 7, 8) == 3)
4966 if ((arm_decode_field (given
, 24, 24) == 0)
4967 && (arm_decode_field (given
, 21, 21) == 0))
4971 else if ((arm_decode_field (given
, 7, 8) == 3))
4979 if ((arm_decode_field (given
, 24, 24) == 0)
4980 && (arm_decode_field (given
, 21, 21) == 0))
4987 case MVE_VCVT_FP_FIX_VEC
:
4988 return (arm_decode_field (given
, 16, 21) & 0x38) == 0;
4993 unsigned long cmode
= arm_decode_field (given
, 8, 11);
4995 if ((cmode
& 1) == 0)
4997 else if ((cmode
& 0xc) == 0xc)
5005 unsigned long cmode
= arm_decode_field (given
, 8, 11);
5007 if ((cmode
& 9) == 1)
5009 else if ((cmode
& 5) == 1)
5011 else if ((cmode
& 0xe) == 0xe)
5017 case MVE_VMOV_IMM_TO_VEC
:
5018 if ((arm_decode_field (given
, 5, 5) == 1)
5019 && (arm_decode_field (given
, 8, 11) != 0xe))
5026 unsigned long size
= arm_decode_field (given
, 19, 20);
5027 if ((size
== 0) || (size
== 3))
5042 if (arm_decode_field (given
, 18, 19) == 3)
5048 case MVE_VRMLSLDAVH
:
5051 if (arm_decode_field (given
, 20, 22) == 7)
5056 case MVE_VRMLALDAVH
:
5057 if ((arm_decode_field (given
, 20, 22) & 6) == 6)
5064 if ((arm_decode_field (given
, 20, 21) == 3)
5065 || (arm_decode_field (given
, 1, 3) == 7))
5072 if (arm_decode_field (given
, 16, 18) == 0)
5074 unsigned long sz
= arm_decode_field (given
, 19, 20);
5076 if ((sz
== 1) || (sz
== 2))
5091 if (arm_decode_field (given
, 19, 21) == 0)
5103 print_mve_vld_str_addr (struct disassemble_info
*info
,
5104 unsigned long given
,
5105 enum mve_instructions matched_insn
)
5107 void *stream
= info
->stream
;
5108 fprintf_ftype func
= info
->fprintf_func
;
5110 unsigned long p
, w
, gpr
, imm
, add
, mod_imm
;
5112 imm
= arm_decode_field (given
, 0, 6);
5115 switch (matched_insn
)
5119 gpr
= arm_decode_field (given
, 16, 18);
5124 gpr
= arm_decode_field (given
, 16, 18);
5130 gpr
= arm_decode_field (given
, 16, 19);
5136 gpr
= arm_decode_field (given
, 16, 19);
5142 gpr
= arm_decode_field (given
, 16, 19);
5149 p
= arm_decode_field (given
, 24, 24);
5150 w
= arm_decode_field (given
, 21, 21);
5152 add
= arm_decode_field (given
, 23, 23);
5156 /* Don't print anything for '+' as it is implied. */
5166 func (stream
, "[%s, #%s%lu]", arm_regnames
[gpr
], add_sub
, mod_imm
);
5167 /* Pre-indexed mode. */
5169 func (stream
, "[%s, #%s%lu]!", arm_regnames
[gpr
], add_sub
, mod_imm
);
5171 else if ((p
== 0) && (w
== 1))
5172 /* Post-index mode. */
5173 func (stream
, "[%s], #%s%lu", arm_regnames
[gpr
], add_sub
, mod_imm
);
5176 /* Return FALSE if GIVEN is not an undefined encoding for MATCHED_INSN.
5177 Otherwise, return TRUE and set UNDEFINED_CODE to give a reason as to why
5178 this encoding is undefined. */
5181 is_mve_undefined (unsigned long given
, enum mve_instructions matched_insn
,
5182 enum mve_undefined
*undefined_code
)
5184 *undefined_code
= UNDEF_NONE
;
5186 switch (matched_insn
)
5189 if (arm_decode_field_multiple (given
, 5, 5, 22, 22) == 3)
5191 *undefined_code
= UNDEF_SIZE_3
;
5197 case MVE_VQDMULH_T1
:
5198 case MVE_VQRDMULH_T2
:
5202 if (arm_decode_field (given
, 20, 21) == 3)
5204 *undefined_code
= UNDEF_SIZE_3
;
5211 if (arm_decode_field (given
, 7, 8) == 3)
5213 *undefined_code
= UNDEF_SIZE_3
;
5220 if (arm_decode_field (given
, 7, 8) <= 1)
5222 *undefined_code
= UNDEF_SIZE_LE_1
;
5229 if ((arm_decode_field (given
, 7, 8) == 0))
5231 *undefined_code
= UNDEF_SIZE_0
;
5238 if ((arm_decode_field (given
, 7, 8) <= 1))
5240 *undefined_code
= UNDEF_SIZE_LE_1
;
5246 case MVE_VLDRB_GATHER_T1
:
5247 if (arm_decode_field (given
, 7, 8) == 3)
5249 *undefined_code
= UNDEF_SIZE_3
;
5252 else if ((arm_decode_field (given
, 28, 28) == 0)
5253 && (arm_decode_field (given
, 7, 8) == 0))
5255 *undefined_code
= UNDEF_NOT_UNS_SIZE_0
;
5261 case MVE_VLDRH_GATHER_T2
:
5262 if (arm_decode_field (given
, 7, 8) == 3)
5264 *undefined_code
= UNDEF_SIZE_3
;
5267 else if ((arm_decode_field (given
, 28, 28) == 0)
5268 && (arm_decode_field (given
, 7, 8) == 1))
5270 *undefined_code
= UNDEF_NOT_UNS_SIZE_1
;
5273 else if (arm_decode_field (given
, 7, 8) == 0)
5275 *undefined_code
= UNDEF_SIZE_0
;
5281 case MVE_VLDRW_GATHER_T3
:
5282 if (arm_decode_field (given
, 7, 8) != 2)
5284 *undefined_code
= UNDEF_SIZE_NOT_2
;
5287 else if (arm_decode_field (given
, 28, 28) == 0)
5289 *undefined_code
= UNDEF_NOT_UNSIGNED
;
5295 case MVE_VLDRD_GATHER_T4
:
5296 if (arm_decode_field (given
, 7, 8) != 3)
5298 *undefined_code
= UNDEF_SIZE_NOT_3
;
5301 else if (arm_decode_field (given
, 28, 28) == 0)
5303 *undefined_code
= UNDEF_NOT_UNSIGNED
;
5309 case MVE_VSTRB_SCATTER_T1
:
5310 if (arm_decode_field (given
, 7, 8) == 3)
5312 *undefined_code
= UNDEF_SIZE_3
;
5318 case MVE_VSTRH_SCATTER_T2
:
5320 unsigned long size
= arm_decode_field (given
, 7, 8);
5323 *undefined_code
= UNDEF_SIZE_3
;
5328 *undefined_code
= UNDEF_SIZE_0
;
5335 case MVE_VSTRW_SCATTER_T3
:
5336 if (arm_decode_field (given
, 7, 8) != 2)
5338 *undefined_code
= UNDEF_SIZE_NOT_2
;
5344 case MVE_VSTRD_SCATTER_T4
:
5345 if (arm_decode_field (given
, 7, 8) != 3)
5347 *undefined_code
= UNDEF_SIZE_NOT_3
;
5353 case MVE_VCVT_FP_FIX_VEC
:
5355 unsigned long imm6
= arm_decode_field (given
, 16, 21);
5356 if ((imm6
& 0x20) == 0)
5358 *undefined_code
= UNDEF_VCVT_IMM6
;
5362 if ((arm_decode_field (given
, 9, 9) == 0)
5363 && ((imm6
& 0x30) == 0x20))
5365 *undefined_code
= UNDEF_VCVT_FSI_IMM6
;
5372 case MVE_VCVT_BETWEEN_FP_INT
:
5373 case MVE_VCVT_FROM_FP_TO_INT
:
5375 unsigned long size
= arm_decode_field (given
, 18, 19);
5378 *undefined_code
= UNDEF_SIZE_0
;
5383 *undefined_code
= UNDEF_SIZE_3
;
5390 case MVE_VMOV_VEC_LANE_TO_GP
:
5392 unsigned long op1
= arm_decode_field (given
, 21, 22);
5393 unsigned long op2
= arm_decode_field (given
, 5, 6);
5394 unsigned long u
= arm_decode_field (given
, 23, 23);
5396 if ((op2
== 0) && (u
== 1))
5398 if ((op1
== 0) || (op1
== 1))
5400 *undefined_code
= UNDEF_BAD_U_OP1_OP2
;
5408 if ((op1
== 0) || (op1
== 1))
5410 *undefined_code
= UNDEF_BAD_OP1_OP2
;
5420 case MVE_VMOV_GP_TO_VEC_LANE
:
5421 if (arm_decode_field (given
, 5, 6) == 2)
5423 unsigned long op1
= arm_decode_field (given
, 21, 22);
5424 if ((op1
== 0) || (op1
== 1))
5426 *undefined_code
= UNDEF_BAD_OP1_OP2
;
5435 case MVE_VMOV_IMM_TO_VEC
:
5436 if (arm_decode_field (given
, 5, 5) == 0)
5438 unsigned long cmode
= arm_decode_field (given
, 8, 11);
5440 if (((cmode
& 9) == 1) || ((cmode
& 5) == 1))
5442 *undefined_code
= UNDEF_OP_0_BAD_CMODE
;
5453 if (arm_decode_field (given
, 18, 19) == 2)
5455 *undefined_code
= UNDEF_SIZE_2
;
5461 case MVE_VRMLALDAVH
:
5462 case MVE_VMLADAV_T1
:
5463 case MVE_VMLADAV_T2
:
5465 if ((arm_decode_field (given
, 28, 28) == 1)
5466 && (arm_decode_field (given
, 12, 12) == 1))
5468 *undefined_code
= UNDEF_XCHG_UNS
;
5479 unsigned long sz
= arm_decode_field (given
, 19, 20);
5482 else if ((sz
& 2) == 2)
5486 *undefined_code
= UNDEF_SIZE
;
5500 unsigned long sz
= arm_decode_field (given
, 19, 21);
5503 else if ((sz
& 6) == 2)
5505 else if ((sz
& 4) == 4)
5509 *undefined_code
= UNDEF_SIZE
;
5516 if (arm_decode_field (given
, 19, 20) == 0)
5518 *undefined_code
= UNDEF_SIZE_0
;
5529 /* Return FALSE if GIVEN is not an unpredictable encoding for MATCHED_INSN.
5530 Otherwise, return TRUE and set UNPREDICTABLE_CODE to give a reason as to
5531 why this encoding is unpredictable. */
5534 is_mve_unpredictable (unsigned long given
, enum mve_instructions matched_insn
,
5535 enum mve_unpredictable
*unpredictable_code
)
5537 *unpredictable_code
= UNPRED_NONE
;
5539 switch (matched_insn
)
5541 case MVE_VCMP_FP_T2
:
5543 if ((arm_decode_field (given
, 12, 12) == 0)
5544 && (arm_decode_field (given
, 5, 5) == 1))
5546 *unpredictable_code
= UNPRED_FCA_0_FCB_1
;
5552 case MVE_VPT_VEC_T4
:
5553 case MVE_VPT_VEC_T5
:
5554 case MVE_VPT_VEC_T6
:
5555 case MVE_VCMP_VEC_T4
:
5556 case MVE_VCMP_VEC_T5
:
5557 case MVE_VCMP_VEC_T6
:
5558 if (arm_decode_field (given
, 0, 3) == 0xd)
5560 *unpredictable_code
= UNPRED_R13
;
5568 unsigned long gpr
= arm_decode_field (given
, 12, 15);
5571 *unpredictable_code
= UNPRED_R13
;
5574 else if (gpr
== 0xf)
5576 *unpredictable_code
= UNPRED_R15
;
5592 case MVE_VQDMULH_T3
:
5593 case MVE_VQRDMULH_T4
:
5595 case MVE_VFMA_FP_SCALAR
:
5596 case MVE_VFMAS_FP_SCALAR
:
5600 unsigned long gpr
= arm_decode_field (given
, 0, 3);
5603 *unpredictable_code
= UNPRED_R13
;
5606 else if (gpr
== 0xf)
5608 *unpredictable_code
= UNPRED_R15
;
5618 unsigned long rn
= arm_decode_field (given
, 16, 19);
5620 if ((rn
== 0xd) && (arm_decode_field (given
, 21, 21) == 1))
5622 *unpredictable_code
= UNPRED_R13_AND_WB
;
5628 *unpredictable_code
= UNPRED_R15
;
5632 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) > 6)
5634 *unpredictable_code
= UNPRED_Q_GT_6
;
5644 unsigned long rn
= arm_decode_field (given
, 16, 19);
5646 if ((rn
== 0xd) && (arm_decode_field (given
, 21, 21) == 1))
5648 *unpredictable_code
= UNPRED_R13_AND_WB
;
5654 *unpredictable_code
= UNPRED_R15
;
5658 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) > 4)
5660 *unpredictable_code
= UNPRED_Q_GT_4
;
5674 unsigned long rn
= arm_decode_field (given
, 16, 19);
5676 if ((rn
== 0xd) && (arm_decode_field (given
, 21, 21) == 1))
5678 *unpredictable_code
= UNPRED_R13_AND_WB
;
5683 *unpredictable_code
= UNPRED_R15
;
5690 case MVE_VLDRB_GATHER_T1
:
5691 if (arm_decode_field (given
, 0, 0) == 1)
5693 *unpredictable_code
= UNPRED_OS
;
5698 /* To handle common code with T2-T4 variants. */
5699 case MVE_VLDRH_GATHER_T2
:
5700 case MVE_VLDRW_GATHER_T3
:
5701 case MVE_VLDRD_GATHER_T4
:
5703 unsigned long qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
5704 unsigned long qm
= arm_decode_field_multiple (given
, 1, 3, 5, 5);
5708 *unpredictable_code
= UNPRED_Q_REGS_EQUAL
;
5712 if (arm_decode_field (given
, 16, 19) == 0xf)
5714 *unpredictable_code
= UNPRED_R15
;
5721 case MVE_VLDRW_GATHER_T5
:
5722 case MVE_VLDRD_GATHER_T6
:
5724 unsigned long qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
5725 unsigned long qm
= arm_decode_field_multiple (given
, 17, 19, 7, 7);
5729 *unpredictable_code
= UNPRED_Q_REGS_EQUAL
;
5736 case MVE_VSTRB_SCATTER_T1
:
5737 if (arm_decode_field (given
, 16, 19) == 0xf)
5739 *unpredictable_code
= UNPRED_R15
;
5742 else if (arm_decode_field (given
, 0, 0) == 1)
5744 *unpredictable_code
= UNPRED_OS
;
5750 case MVE_VSTRH_SCATTER_T2
:
5751 case MVE_VSTRW_SCATTER_T3
:
5752 case MVE_VSTRD_SCATTER_T4
:
5753 if (arm_decode_field (given
, 16, 19) == 0xf)
5755 *unpredictable_code
= UNPRED_R15
;
5761 case MVE_VMOV2_VEC_LANE_TO_GP
:
5762 case MVE_VMOV2_GP_TO_VEC_LANE
:
5763 case MVE_VCVT_BETWEEN_FP_INT
:
5764 case MVE_VCVT_FROM_FP_TO_INT
:
5766 unsigned long rt
= arm_decode_field (given
, 0, 3);
5767 unsigned long rt2
= arm_decode_field (given
, 16, 19);
5769 if ((rt
== 0xd) || (rt2
== 0xd))
5771 *unpredictable_code
= UNPRED_R13
;
5774 else if ((rt
== 0xf) || (rt2
== 0xf))
5776 *unpredictable_code
= UNPRED_R15
;
5781 *unpredictable_code
= UNPRED_GP_REGS_EQUAL
;
5788 case MVE_VMOV_HFP_TO_GP
:
5789 case MVE_VMOV_GP_TO_VEC_LANE
:
5790 case MVE_VMOV_VEC_LANE_TO_GP
:
5792 unsigned long rda
= arm_decode_field (given
, 12, 15);
5795 *unpredictable_code
= UNPRED_R13
;
5798 else if (rda
== 0xf)
5800 *unpredictable_code
= UNPRED_R15
;
5817 if (arm_decode_field (given
, 20, 21) == 2)
5819 Qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
5820 Qm
= arm_decode_field_multiple (given
, 1, 3, 5, 5);
5821 Qn
= arm_decode_field_multiple (given
, 17, 19, 7, 7);
5823 if ((Qd
== Qn
) || (Qd
== Qm
))
5825 *unpredictable_code
= UNPRED_Q_REGS_EQ_AND_SIZE_2
;
5836 case MVE_VQDMULL_T1
:
5842 if (arm_decode_field (given
, 28, 28) == 1)
5844 Qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
5845 Qm
= arm_decode_field_multiple (given
, 1, 3, 5, 5);
5846 Qn
= arm_decode_field_multiple (given
, 17, 19, 7, 7);
5848 if ((Qd
== Qn
) || (Qd
== Qm
))
5850 *unpredictable_code
= UNPRED_Q_REGS_EQ_AND_SIZE_1
;
5860 case MVE_VQDMULL_T2
:
5862 unsigned long gpr
= arm_decode_field (given
, 0, 3);
5865 *unpredictable_code
= UNPRED_R13
;
5868 else if (gpr
== 0xf)
5870 *unpredictable_code
= UNPRED_R15
;
5874 if (arm_decode_field (given
, 28, 28) == 1)
5877 = arm_decode_field_multiple (given
, 13, 15, 22, 22);
5878 unsigned long Qn
= arm_decode_field_multiple (given
, 17, 19, 7, 7);
5882 *unpredictable_code
= UNPRED_Q_REGS_EQ_AND_SIZE_1
;
5893 case MVE_VRMLSLDAVH
:
5896 if (arm_decode_field (given
, 20, 22) == 6)
5898 *unpredictable_code
= UNPRED_R13
;
5906 if (arm_decode_field (given
, 1, 3) == 6)
5908 *unpredictable_code
= UNPRED_R13
;
5917 unsigned long Qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
5918 unsigned long Qm
= arm_decode_field_multiple (given
, 1, 3, 5, 5);
5919 if ((Qd
== Qm
) && arm_decode_field (given
, 20, 21) == 2)
5921 *unpredictable_code
= UNPRED_Q_REGS_EQ_AND_SIZE_2
;
5930 unsigned long Qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
5931 unsigned long Qm
= arm_decode_field_multiple (given
, 1, 3, 5, 5);
5932 if ((Qd
== Qm
) && arm_decode_field (given
, 20, 20) == 1)
5934 *unpredictable_code
= UNPRED_Q_REGS_EQ_AND_SIZE_1
;
5947 if (arm_decode_field (given
, 20, 20) == 1)
5949 Qda
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
5950 Qm
= arm_decode_field_multiple (given
, 1, 3, 5, 5);
5951 Qn
= arm_decode_field_multiple (given
, 17, 19, 7, 7);
5953 if ((Qda
== Qn
) || (Qda
== Qm
))
5955 *unpredictable_code
= UNPRED_Q_REGS_EQ_AND_SIZE_1
;
5972 print_mve_vmov_index (struct disassemble_info
*info
, unsigned long given
)
5974 unsigned long op1
= arm_decode_field (given
, 21, 22);
5975 unsigned long op2
= arm_decode_field (given
, 5, 6);
5976 unsigned long h
= arm_decode_field (given
, 16, 16);
5977 unsigned long index
, esize
, targetBeat
, idx
;
5978 void *stream
= info
->stream
;
5979 fprintf_ftype func
= info
->fprintf_func
;
5981 if ((op1
& 0x2) == 0x2)
5986 else if (((op1
& 0x2) == 0x0) && ((op2
& 0x1) == 0x1))
5991 else if (((op1
& 0x2) == 0) && ((op2
& 0x3) == 0))
5998 func (stream
, "<undefined index>");
6002 targetBeat
= (op1
& 0x1) | (h
<< 1);
6003 idx
= index
+ targetBeat
* (32/esize
);
6005 func (stream
, "%lu", idx
);
6008 /* Print neon and mve 8-bit immediate that can be a 8, 16, 32, or 64-bits
6009 in length and integer of floating-point type. */
6011 print_simd_imm8 (struct disassemble_info
*info
, unsigned long given
,
6012 unsigned int ibit_loc
, const struct mopcode32
*insn
)
6015 int cmode
= (given
>> 8) & 0xf;
6016 int op
= (given
>> 5) & 0x1;
6017 unsigned long value
= 0, hival
= 0;
6021 void *stream
= info
->stream
;
6022 fprintf_ftype func
= info
->fprintf_func
;
6024 /* On Neon the 'i' bit is at bit 24, on mve it is
6026 bits
|= ((given
>> ibit_loc
) & 1) << 7;
6027 bits
|= ((given
>> 16) & 7) << 4;
6028 bits
|= ((given
>> 0) & 15) << 0;
6032 shift
= (cmode
>> 1) & 3;
6033 value
= (unsigned long) bits
<< (8 * shift
);
6036 else if (cmode
< 12)
6038 shift
= (cmode
>> 1) & 1;
6039 value
= (unsigned long) bits
<< (8 * shift
);
6042 else if (cmode
< 14)
6044 shift
= (cmode
& 1) + 1;
6045 value
= (unsigned long) bits
<< (8 * shift
);
6046 value
|= (1ul << (8 * shift
)) - 1;
6049 else if (cmode
== 14)
6053 /* Bit replication into bytes. */
6059 for (ix
= 7; ix
>= 0; ix
--)
6061 mask
= ((bits
>> ix
) & 1) ? 0xff : 0;
6063 value
= (value
<< 8) | mask
;
6065 hival
= (hival
<< 8) | mask
;
6071 /* Byte replication. */
6072 value
= (unsigned long) bits
;
6078 /* Floating point encoding. */
6081 value
= (unsigned long) (bits
& 0x7f) << 19;
6082 value
|= (unsigned long) (bits
& 0x80) << 24;
6083 tmp
= bits
& 0x40 ? 0x3c : 0x40;
6084 value
|= (unsigned long) tmp
<< 24;
6090 func (stream
, "<illegal constant %.8x:%x:%x>",
6096 // printU determines whether the immediate value should be printed as
6098 unsigned printU
= 0;
6099 switch (insn
->mve_op
)
6103 // We want this for instructions that don't have a 'signed' type
6107 case MVE_VMOV_IMM_TO_VEC
:
6114 func (stream
, "#%ld\t; 0x%.2lx", value
, value
);
6121 : "#%ld\t; 0x%.4lx", value
, value
);
6127 unsigned char valbytes
[4];
6130 /* Do this a byte at a time so we don't have to
6131 worry about the host's endianness. */
6132 valbytes
[0] = value
& 0xff;
6133 valbytes
[1] = (value
>> 8) & 0xff;
6134 valbytes
[2] = (value
>> 16) & 0xff;
6135 valbytes
[3] = (value
>> 24) & 0xff;
6137 floatformat_to_double
6138 (& floatformat_ieee_single_little
, valbytes
,
6141 func (stream
, "#%.7g\t; 0x%.8lx", fvalue
,
6148 : "#%ld\t; 0x%.8lx",
6149 (long) (((value
& 0x80000000L
) != 0)
6151 ? value
| ~0xffffffffL
: value
),
6156 func (stream
, "#0x%.8lx%.8lx", hival
, value
);
6166 print_mve_undefined (struct disassemble_info
*info
,
6167 enum mve_undefined undefined_code
)
6169 void *stream
= info
->stream
;
6170 fprintf_ftype func
= info
->fprintf_func
;
6172 func (stream
, "\t\tundefined instruction: ");
6174 switch (undefined_code
)
6177 func (stream
, "illegal size");
6181 func (stream
, "size equals zero");
6185 func (stream
, "size equals two");
6189 func (stream
, "size equals three");
6192 case UNDEF_SIZE_LE_1
:
6193 func (stream
, "size <= 1");
6196 case UNDEF_SIZE_NOT_2
:
6197 func (stream
, "size not equal to 2");
6200 case UNDEF_SIZE_NOT_3
:
6201 func (stream
, "size not equal to 3");
6204 case UNDEF_NOT_UNS_SIZE_0
:
6205 func (stream
, "not unsigned and size = zero");
6208 case UNDEF_NOT_UNS_SIZE_1
:
6209 func (stream
, "not unsigned and size = one");
6212 case UNDEF_NOT_UNSIGNED
:
6213 func (stream
, "not unsigned");
6216 case UNDEF_VCVT_IMM6
:
6217 func (stream
, "invalid imm6");
6220 case UNDEF_VCVT_FSI_IMM6
:
6221 func (stream
, "fsi = 0 and invalid imm6");
6224 case UNDEF_BAD_OP1_OP2
:
6225 func (stream
, "bad size with op2 = 2 and op1 = 0 or 1");
6228 case UNDEF_BAD_U_OP1_OP2
:
6229 func (stream
, "unsigned with op2 = 0 and op1 = 0 or 1");
6232 case UNDEF_OP_0_BAD_CMODE
:
6233 func (stream
, "op field equal 0 and bad cmode");
6236 case UNDEF_XCHG_UNS
:
6237 func (stream
, "exchange and unsigned together");
6247 print_mve_unpredictable (struct disassemble_info
*info
,
6248 enum mve_unpredictable unpredict_code
)
6250 void *stream
= info
->stream
;
6251 fprintf_ftype func
= info
->fprintf_func
;
6253 func (stream
, "%s: ", UNPREDICTABLE_INSTRUCTION
);
6255 switch (unpredict_code
)
6257 case UNPRED_IT_BLOCK
:
6258 func (stream
, "mve instruction in it block");
6261 case UNPRED_FCA_0_FCB_1
:
6262 func (stream
, "condition bits, fca = 0 and fcb = 1");
6266 func (stream
, "use of r13 (sp)");
6270 func (stream
, "use of r15 (pc)");
6274 func (stream
, "start register block > r4");
6278 func (stream
, "start register block > r6");
6281 case UNPRED_R13_AND_WB
:
6282 func (stream
, "use of r13 and write back");
6285 case UNPRED_Q_REGS_EQUAL
:
6287 "same vector register used for destination and other operand");
6291 func (stream
, "use of offset scaled");
6294 case UNPRED_GP_REGS_EQUAL
:
6295 func (stream
, "same general-purpose register used for both operands");
6298 case UNPRED_Q_REGS_EQ_AND_SIZE_1
:
6299 func (stream
, "use of identical q registers and size = 1");
6302 case UNPRED_Q_REGS_EQ_AND_SIZE_2
:
6303 func (stream
, "use of identical q registers and size = 1");
6311 /* Print register block operand for mve vld2/vld4/vst2/vld4. */
6314 print_mve_register_blocks (struct disassemble_info
*info
,
6315 unsigned long given
,
6316 enum mve_instructions matched_insn
)
6318 void *stream
= info
->stream
;
6319 fprintf_ftype func
= info
->fprintf_func
;
6321 unsigned long q_reg_start
= arm_decode_field_multiple (given
,
6324 switch (matched_insn
)
6328 if (q_reg_start
<= 6)
6329 func (stream
, "{q%ld, q%ld}", q_reg_start
, q_reg_start
+ 1);
6331 func (stream
, "<illegal reg q%ld>", q_reg_start
);
6336 if (q_reg_start
<= 4)
6337 func (stream
, "{q%ld, q%ld, q%ld, q%ld}", q_reg_start
,
6338 q_reg_start
+ 1, q_reg_start
+ 2,
6341 func (stream
, "<illegal reg q%ld>", q_reg_start
);
6350 print_mve_rounding_mode (struct disassemble_info
*info
,
6351 unsigned long given
,
6352 enum mve_instructions matched_insn
)
6354 void *stream
= info
->stream
;
6355 fprintf_ftype func
= info
->fprintf_func
;
6357 switch (matched_insn
)
6359 case MVE_VCVT_FROM_FP_TO_INT
:
6361 switch (arm_decode_field (given
, 8, 9))
6387 switch (arm_decode_field (given
, 7, 9))
6426 print_mve_vcvt_size (struct disassemble_info
*info
,
6427 unsigned long given
,
6428 enum mve_instructions matched_insn
)
6430 unsigned long mode
= 0;
6431 void *stream
= info
->stream
;
6432 fprintf_ftype func
= info
->fprintf_func
;
6434 switch (matched_insn
)
6436 case MVE_VCVT_FP_FIX_VEC
:
6438 mode
= (((given
& 0x200) >> 7)
6439 | ((given
& 0x10000000) >> 27)
6440 | ((given
& 0x100) >> 8));
6445 func (stream
, "f16.s16");
6449 func (stream
, "s16.f16");
6453 func (stream
, "f16.u16");
6457 func (stream
, "u16.f16");
6461 func (stream
, "f32.s32");
6465 func (stream
, "s32.f32");
6469 func (stream
, "f32.u32");
6473 func (stream
, "u32.f32");
6481 case MVE_VCVT_BETWEEN_FP_INT
:
6483 unsigned long size
= arm_decode_field (given
, 18, 19);
6484 unsigned long op
= arm_decode_field (given
, 7, 8);
6491 func (stream
, "f16.s16");
6495 func (stream
, "f16.u16");
6499 func (stream
, "s16.f16");
6503 func (stream
, "u16.f16");
6515 func (stream
, "f32.s32");
6519 func (stream
, "f32.u32");
6523 func (stream
, "s32.f32");
6527 func (stream
, "u32.f32");
6534 case MVE_VCVT_FP_HALF_FP
:
6536 unsigned long op
= arm_decode_field (given
, 28, 28);
6538 func (stream
, "f16.f32");
6540 func (stream
, "f32.f16");
6544 case MVE_VCVT_FROM_FP_TO_INT
:
6546 unsigned long size
= arm_decode_field_multiple (given
, 7, 7, 18, 19);
6551 func (stream
, "s16.f16");
6555 func (stream
, "u16.f16");
6559 func (stream
, "s32.f32");
6563 func (stream
, "u32.f32");
6578 print_mve_rotate (struct disassemble_info
*info
, unsigned long rot
,
6579 unsigned long rot_width
)
6581 void *stream
= info
->stream
;
6582 fprintf_ftype func
= info
->fprintf_func
;
6589 func (stream
, "90");
6592 func (stream
, "270");
6598 else if (rot_width
== 2)
6606 func (stream
, "90");
6609 func (stream
, "180");
6612 func (stream
, "270");
6621 print_instruction_predicate (struct disassemble_info
*info
)
6623 void *stream
= info
->stream
;
6624 fprintf_ftype func
= info
->fprintf_func
;
6626 if (vpt_block_state
.next_pred_state
== PRED_THEN
)
6628 else if (vpt_block_state
.next_pred_state
== PRED_ELSE
)
6633 print_mve_size (struct disassemble_info
*info
,
6635 enum mve_instructions matched_insn
)
6637 void *stream
= info
->stream
;
6638 fprintf_ftype func
= info
->fprintf_func
;
6640 switch (matched_insn
)
6644 case MVE_VCMP_VEC_T1
:
6645 case MVE_VCMP_VEC_T2
:
6646 case MVE_VCMP_VEC_T3
:
6647 case MVE_VCMP_VEC_T4
:
6648 case MVE_VCMP_VEC_T5
:
6649 case MVE_VCMP_VEC_T6
:
6661 case MVE_VLDRB_GATHER_T1
:
6662 case MVE_VLDRH_GATHER_T2
:
6663 case MVE_VLDRW_GATHER_T3
:
6664 case MVE_VLDRD_GATHER_T4
:
6668 case MVE_VPT_VEC_T1
:
6669 case MVE_VPT_VEC_T2
:
6670 case MVE_VPT_VEC_T3
:
6671 case MVE_VPT_VEC_T4
:
6672 case MVE_VPT_VEC_T5
:
6673 case MVE_VPT_VEC_T6
:
6682 case MVE_VQDMULH_T1
:
6683 case MVE_VQRDMULH_T2
:
6684 case MVE_VQDMULH_T3
:
6685 case MVE_VQRDMULH_T4
:
6699 case MVE_VSTRB_SCATTER_T1
:
6700 case MVE_VSTRH_SCATTER_T2
:
6701 case MVE_VSTRW_SCATTER_T3
:
6705 func (stream
, "%s", mve_vec_sizename
[size
]);
6707 func (stream
, "<undef size>");
6710 case MVE_VCMP_FP_T1
:
6711 case MVE_VCMP_FP_T2
:
6712 case MVE_VFMA_FP_SCALAR
:
6715 case MVE_VFMAS_FP_SCALAR
:
6719 func (stream
, "32");
6721 func (stream
, "16");
6727 case MVE_VMLADAV_T1
:
6729 case MVE_VMLSDAV_T1
:
6732 case MVE_VQDMULL_T1
:
6733 case MVE_VQDMULL_T2
:
6737 func (stream
, "16");
6739 func (stream
, "32");
6746 func (stream
, "16");
6753 func (stream
, "32");
6756 func (stream
, "16");
6766 case MVE_VMOV_GP_TO_VEC_LANE
:
6767 case MVE_VMOV_VEC_LANE_TO_GP
:
6771 func (stream
, "32");
6776 func (stream
, "16");
6779 case 8: case 9: case 10: case 11:
6780 case 12: case 13: case 14: case 15:
6789 case MVE_VMOV_IMM_TO_VEC
:
6792 case 0: case 4: case 8:
6793 case 12: case 24: case 26:
6794 func (stream
, "i32");
6797 func (stream
, "i16");
6800 func (stream
, "i8");
6803 func (stream
, "i64");
6806 func (stream
, "f32");
6813 case MVE_VMULL_POLY
:
6815 func (stream
, "p8");
6817 func (stream
, "p16");
6823 case 0: case 2: case 4:
6824 case 6: case 12: case 13:
6825 func (stream
, "32");
6829 func (stream
, "16");
6843 func (stream
, "32");
6847 func (stream
, "16");
6865 func (stream
, "16");
6869 func (stream
, "32");
6894 func (stream
, "16");
6897 case 4: case 5: case 6: case 7:
6898 func (stream
, "32");
6913 print_mve_shift_n (struct disassemble_info
*info
, long given
,
6914 enum mve_instructions matched_insn
)
6916 void *stream
= info
->stream
;
6917 fprintf_ftype func
= info
->fprintf_func
;
6920 = matched_insn
== MVE_VQSHL_T2
6921 || matched_insn
== MVE_VQSHLU_T3
6922 || matched_insn
== MVE_VSHL_T1
6923 || matched_insn
== MVE_VSHLL_T1
6924 || matched_insn
== MVE_VSLI
;
6926 unsigned imm6
= (given
& 0x3f0000) >> 16;
6928 if (matched_insn
== MVE_VSHLL_T1
)
6931 unsigned shiftAmount
= 0;
6932 if ((imm6
& 0x20) != 0)
6933 shiftAmount
= startAt0
? imm6
- 32 : 64 - imm6
;
6934 else if ((imm6
& 0x10) != 0)
6935 shiftAmount
= startAt0
? imm6
- 16 : 32 - imm6
;
6936 else if ((imm6
& 0x08) != 0)
6937 shiftAmount
= startAt0
? imm6
- 8 : 16 - imm6
;
6939 print_mve_undefined (info
, UNDEF_SIZE_0
);
6941 func (stream
, "%u", shiftAmount
);
6945 print_vec_condition (struct disassemble_info
*info
, long given
,
6946 enum mve_instructions matched_insn
)
6948 void *stream
= info
->stream
;
6949 fprintf_ftype func
= info
->fprintf_func
;
6952 switch (matched_insn
)
6955 case MVE_VCMP_FP_T1
:
6956 vec_cond
= (((given
& 0x1000) >> 10)
6957 | ((given
& 1) << 1)
6958 | ((given
& 0x0080) >> 7));
6959 func (stream
, "%s",vec_condnames
[vec_cond
]);
6963 case MVE_VCMP_FP_T2
:
6964 vec_cond
= (((given
& 0x1000) >> 10)
6965 | ((given
& 0x0020) >> 4)
6966 | ((given
& 0x0080) >> 7));
6967 func (stream
, "%s",vec_condnames
[vec_cond
]);
6970 case MVE_VPT_VEC_T1
:
6971 case MVE_VCMP_VEC_T1
:
6972 vec_cond
= (given
& 0x0080) >> 7;
6973 func (stream
, "%s",vec_condnames
[vec_cond
]);
6976 case MVE_VPT_VEC_T2
:
6977 case MVE_VCMP_VEC_T2
:
6978 vec_cond
= 2 | ((given
& 0x0080) >> 7);
6979 func (stream
, "%s",vec_condnames
[vec_cond
]);
6982 case MVE_VPT_VEC_T3
:
6983 case MVE_VCMP_VEC_T3
:
6984 vec_cond
= 4 | ((given
& 1) << 1) | ((given
& 0x0080) >> 7);
6985 func (stream
, "%s",vec_condnames
[vec_cond
]);
6988 case MVE_VPT_VEC_T4
:
6989 case MVE_VCMP_VEC_T4
:
6990 vec_cond
= (given
& 0x0080) >> 7;
6991 func (stream
, "%s",vec_condnames
[vec_cond
]);
6994 case MVE_VPT_VEC_T5
:
6995 case MVE_VCMP_VEC_T5
:
6996 vec_cond
= 2 | ((given
& 0x0080) >> 7);
6997 func (stream
, "%s",vec_condnames
[vec_cond
]);
7000 case MVE_VPT_VEC_T6
:
7001 case MVE_VCMP_VEC_T6
:
7002 vec_cond
= 4 | ((given
& 0x0020) >> 4) | ((given
& 0x0080) >> 7);
7003 func (stream
, "%s",vec_condnames
[vec_cond
]);
7018 #define WRITEBACK_BIT_SET (given & (1 << W_BIT))
7019 #define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
7020 #define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
7021 #define PRE_BIT_SET (given & (1 << P_BIT))
7024 /* Print one coprocessor instruction on INFO->STREAM.
7025 Return TRUE if the instuction matched, FALSE if this is not a
7026 recognised coprocessor instruction. */
7029 print_insn_coprocessor (bfd_vma pc
,
7030 struct disassemble_info
*info
,
7034 const struct sopcode32
*insn
;
7035 void *stream
= info
->stream
;
7036 fprintf_ftype func
= info
->fprintf_func
;
7038 unsigned long value
= 0;
7041 struct arm_private_data
*private_data
= info
->private_data
;
7042 arm_feature_set allowed_arches
= ARM_ARCH_NONE
;
7043 arm_feature_set arm_ext_v8_1m_main
=
7044 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
);
7046 allowed_arches
= private_data
->features
;
7048 for (insn
= coprocessor_opcodes
; insn
->assembler
; insn
++)
7050 unsigned long u_reg
= 16;
7051 bfd_boolean is_unpredictable
= FALSE
;
7052 signed long value_in_comment
= 0;
7055 if (ARM_FEATURE_ZERO (insn
->arch
))
7056 switch (insn
->value
)
7058 case SENTINEL_IWMMXT_START
:
7059 if (info
->mach
!= bfd_mach_arm_XScale
7060 && info
->mach
!= bfd_mach_arm_iWMMXt
7061 && info
->mach
!= bfd_mach_arm_iWMMXt2
)
7064 while ((! ARM_FEATURE_ZERO (insn
->arch
))
7065 && insn
->value
!= SENTINEL_IWMMXT_END
);
7068 case SENTINEL_IWMMXT_END
:
7071 case SENTINEL_GENERIC_START
:
7072 allowed_arches
= private_data
->features
;
7080 value
= insn
->value
;
7081 cp_num
= (given
>> 8) & 0xf;
7085 /* The high 4 bits are 0xe for Arm conditional instructions, and
7086 0xe for arm unconditional instructions. The rest of the
7087 encoding is the same. */
7089 value
|= 0xe0000000;
7097 /* Only match unconditional instuctions against unconditional
7099 if ((given
& 0xf0000000) == 0xf0000000)
7106 cond
= (given
>> 28) & 0xf;
7112 if ((insn
->isa
== T32
&& !thumb
)
7113 || (insn
->isa
== ARM
&& thumb
))
7116 if ((given
& mask
) != value
)
7119 if (! ARM_CPU_HAS_FEATURE (insn
->arch
, allowed_arches
))
7122 if (insn
->value
== 0xfe000010 /* mcr2 */
7123 || insn
->value
== 0xfe100010 /* mrc2 */
7124 || insn
->value
== 0xfc100000 /* ldc2 */
7125 || insn
->value
== 0xfc000000) /* stc2 */
7127 if (cp_num
== 9 || cp_num
== 10 || cp_num
== 11)
7128 is_unpredictable
= TRUE
;
7130 /* Armv8.1-M Mainline FP & MVE instructions. */
7131 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main
, allowed_arches
)
7132 && !ARM_CPU_IS_ANY (allowed_arches
)
7133 && (cp_num
== 8 || cp_num
== 14 || cp_num
== 15))
7137 else if (insn
->value
== 0x0e000000 /* cdp */
7138 || insn
->value
== 0xfe000000 /* cdp2 */
7139 || insn
->value
== 0x0e000010 /* mcr */
7140 || insn
->value
== 0x0e100010 /* mrc */
7141 || insn
->value
== 0x0c100000 /* ldc */
7142 || insn
->value
== 0x0c000000) /* stc */
7144 /* Floating-point instructions. */
7145 if (cp_num
== 9 || cp_num
== 10 || cp_num
== 11)
7148 /* Armv8.1-M Mainline FP & MVE instructions. */
7149 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main
, allowed_arches
)
7150 && !ARM_CPU_IS_ANY (allowed_arches
)
7151 && (cp_num
== 8 || cp_num
== 14 || cp_num
== 15))
7154 else if ((insn
->value
== 0xec100f80 /* vldr (system register) */
7155 || insn
->value
== 0xec000f80) /* vstr (system register) */
7156 && arm_decode_field (given
, 24, 24) == 0
7157 && arm_decode_field (given
, 21, 21) == 0)
7158 /* If the P and W bits are both 0 then these encodings match the MVE
7159 VLDR and VSTR instructions, these are in a different table, so we
7160 don't let it match here. */
7163 for (c
= insn
->assembler
; *c
; c
++)
7167 const char mod
= *++c
;
7171 func (stream
, "%%");
7177 int rn
= (given
>> 16) & 0xf;
7178 bfd_vma offset
= given
& 0xff;
7181 offset
= given
& 0x7f;
7183 func (stream
, "[%s", arm_regnames
[(given
>> 16) & 0xf]);
7185 if (PRE_BIT_SET
|| WRITEBACK_BIT_SET
)
7187 /* Not unindexed. The offset is scaled. */
7189 /* vldr.16/vstr.16 will shift the address
7190 left by 1 bit only. */
7191 offset
= offset
* 2;
7193 offset
= offset
* 4;
7195 if (NEGATIVE_BIT_SET
)
7198 value_in_comment
= offset
;
7204 func (stream
, ", #%d]%s",
7206 WRITEBACK_BIT_SET
? "!" : "");
7207 else if (NEGATIVE_BIT_SET
)
7208 func (stream
, ", #-0]");
7216 if (WRITEBACK_BIT_SET
)
7219 func (stream
, ", #%d", (int) offset
);
7220 else if (NEGATIVE_BIT_SET
)
7221 func (stream
, ", #-0");
7225 func (stream
, ", {%s%d}",
7226 (NEGATIVE_BIT_SET
&& !offset
) ? "-" : "",
7228 value_in_comment
= offset
;
7231 if (rn
== 15 && (PRE_BIT_SET
|| WRITEBACK_BIT_SET
))
7233 func (stream
, "\t; ");
7234 /* For unaligned PCs, apply off-by-alignment
7236 info
->print_address_func (offset
+ pc
7237 + info
->bytes_per_chunk
* 2
7246 int regno
= ((given
>> 12) & 0xf) | ((given
>> (22 - 4)) & 0x10);
7247 int offset
= (given
>> 1) & 0x3f;
7250 func (stream
, "{d%d}", regno
);
7251 else if (regno
+ offset
> 32)
7252 func (stream
, "{d%d-<overflow reg d%d>}", regno
, regno
+ offset
- 1);
7254 func (stream
, "{d%d-d%d}", regno
, regno
+ offset
- 1);
7260 bfd_boolean single
= ((given
>> 8) & 1) == 0;
7261 char reg_prefix
= single
? 's' : 'd';
7262 int Dreg
= (given
>> 22) & 0x1;
7263 int Vdreg
= (given
>> 12) & 0xf;
7264 int reg
= single
? ((Vdreg
<< 1) | Dreg
)
7265 : ((Dreg
<< 4) | Vdreg
);
7266 int num
= (given
>> (single
? 0 : 1)) & 0x7f;
7267 int maxreg
= single
? 31 : 15;
7268 int topreg
= reg
+ num
- 1;
7271 func (stream
, "{VPR}");
7273 func (stream
, "{%c%d, VPR}", reg_prefix
, reg
);
7274 else if (topreg
> maxreg
)
7275 func (stream
, "{%c%d-<overflow reg d%d, VPR}",
7276 reg_prefix
, reg
, single
? topreg
>> 1 : topreg
);
7278 func (stream
, "{%c%d-%c%d, VPR}", reg_prefix
, reg
,
7279 reg_prefix
, topreg
);
7284 if (cond
!= COND_UNCOND
)
7285 is_unpredictable
= TRUE
;
7289 if (cond
!= COND_UNCOND
&& cp_num
== 9)
7290 is_unpredictable
= TRUE
;
7292 func (stream
, "%s", arm_conditional
[cond
]);
7296 /* Print a Cirrus/DSP shift immediate. */
7297 /* Immediates are 7bit signed ints with bits 0..3 in
7298 bits 0..3 of opcode and bits 4..6 in bits 5..7
7303 imm
= (given
& 0xf) | ((given
& 0xe0) >> 1);
7305 /* Is ``imm'' a negative number? */
7309 func (stream
, "%d", imm
);
7317 = arm_decode_field_multiple (given
, 13, 15, 22, 22);
7322 func (stream
, "FPSCR");
7325 func (stream
, "FPSCR_nzcvqc");
7328 func (stream
, "VPR");
7331 func (stream
, "P0");
7334 func (stream
, "FPCXTNS");
7337 func (stream
, "FPCXTS");
7340 func (stream
, "<invalid reg %lu>", regno
);
7347 switch (given
& 0x00408000)
7364 switch (given
& 0x00080080)
7376 func (stream
, _("<illegal precision>"));
7382 switch (given
& 0x00408000)
7400 switch (given
& 0x60)
7416 case '0': case '1': case '2': case '3': case '4':
7417 case '5': case '6': case '7': case '8': case '9':
7421 c
= arm_decode_bitfield (c
, given
, &value
, &width
);
7427 is_unpredictable
= TRUE
;
7432 /* Eat the 'u' character. */
7436 is_unpredictable
= TRUE
;
7439 func (stream
, "%s", arm_regnames
[value
]);
7442 if (given
& (1 << 6))
7446 func (stream
, "d%ld", value
);
7451 func (stream
, "<illegal reg q%ld.5>", value
>> 1);
7453 func (stream
, "q%ld", value
>> 1);
7456 func (stream
, "%ld", value
);
7457 value_in_comment
= value
;
7461 /* Converts immediate 8 bit back to float value. */
7462 unsigned floatVal
= (value
& 0x80) << 24
7463 | (value
& 0x3F) << 19
7464 | ((value
& 0x40) ? (0xF8 << 22) : (1 << 30));
7466 /* Quarter float have a maximum value of 31.0.
7467 Get floating point value multiplied by 1e7.
7468 The maximum value stays in limit of a 32-bit int. */
7470 (78125 << (((floatVal
>> 23) & 0xFF) - 124)) *
7471 (16 + (value
& 0xF));
7473 if (!(decVal
% 1000000))
7474 func (stream
, "%ld\t; 0x%08x %c%u.%01u", value
,
7475 floatVal
, value
& 0x80 ? '-' : ' ',
7477 decVal
% 10000000 / 1000000);
7478 else if (!(decVal
% 10000))
7479 func (stream
, "%ld\t; 0x%08x %c%u.%03u", value
,
7480 floatVal
, value
& 0x80 ? '-' : ' ',
7482 decVal
% 10000000 / 10000);
7484 func (stream
, "%ld\t; 0x%08x %c%u.%07u", value
,
7485 floatVal
, value
& 0x80 ? '-' : ' ',
7486 decVal
/ 10000000, decVal
% 10000000);
7491 int from
= (given
& (1 << 7)) ? 32 : 16;
7492 func (stream
, "%ld", from
- value
);
7498 func (stream
, "#%s", arm_fp_const
[value
& 7]);
7500 func (stream
, "f%ld", value
);
7505 func (stream
, "%s", iwmmxt_wwnames
[value
]);
7507 func (stream
, "%s", iwmmxt_wwssnames
[value
]);
7511 func (stream
, "%s", iwmmxt_regnames
[value
]);
7514 func (stream
, "%s", iwmmxt_cregnames
[value
]);
7518 func (stream
, "0x%lx", (value
& 0xffffffffUL
));
7525 func (stream
, "eq");
7529 func (stream
, "vs");
7533 func (stream
, "ge");
7537 func (stream
, "gt");
7541 func (stream
, "??");
7549 func (stream
, "%c", *c
);
7553 if (value
== ((1ul << width
) - 1))
7554 func (stream
, "%c", *c
);
7557 func (stream
, "%c", c
[(1 << width
) - (int) value
]);
7569 int single
= *c
++ == 'y';
7574 case '4': /* Sm pair */
7575 case '0': /* Sm, Dm */
7576 regno
= given
& 0x0000000f;
7580 regno
+= (given
>> 5) & 1;
7583 regno
+= ((given
>> 5) & 1) << 4;
7586 case '1': /* Sd, Dd */
7587 regno
= (given
>> 12) & 0x0000000f;
7591 regno
+= (given
>> 22) & 1;
7594 regno
+= ((given
>> 22) & 1) << 4;
7597 case '2': /* Sn, Dn */
7598 regno
= (given
>> 16) & 0x0000000f;
7602 regno
+= (given
>> 7) & 1;
7605 regno
+= ((given
>> 7) & 1) << 4;
7608 case '3': /* List */
7610 regno
= (given
>> 12) & 0x0000000f;
7614 regno
+= (given
>> 22) & 1;
7617 regno
+= ((given
>> 22) & 1) << 4;
7624 func (stream
, "%c%d", single
? 's' : 'd', regno
);
7628 int count
= given
& 0xff;
7635 func (stream
, "-%c%d",
7643 func (stream
, ", %c%d", single
? 's' : 'd',
7649 switch (given
& 0x00400100)
7651 case 0x00000000: func (stream
, "b"); break;
7652 case 0x00400000: func (stream
, "h"); break;
7653 case 0x00000100: func (stream
, "w"); break;
7654 case 0x00400100: func (stream
, "d"); break;
7662 /* given (20, 23) | given (0, 3) */
7663 value
= ((given
>> 16) & 0xf0) | (given
& 0xf);
7664 func (stream
, "%d", (int) value
);
7669 /* This is like the 'A' operator, except that if
7670 the width field "M" is zero, then the offset is
7671 *not* multiplied by four. */
7673 int offset
= given
& 0xff;
7674 int multiplier
= (given
& 0x00000100) ? 4 : 1;
7676 func (stream
, "[%s", arm_regnames
[(given
>> 16) & 0xf]);
7680 value_in_comment
= offset
* multiplier
;
7681 if (NEGATIVE_BIT_SET
)
7682 value_in_comment
= - value_in_comment
;
7688 func (stream
, ", #%s%d]%s",
7689 NEGATIVE_BIT_SET
? "-" : "",
7690 offset
* multiplier
,
7691 WRITEBACK_BIT_SET
? "!" : "");
7693 func (stream
, "], #%s%d",
7694 NEGATIVE_BIT_SET
? "-" : "",
7695 offset
* multiplier
);
7704 int imm4
= (given
>> 4) & 0xf;
7705 int puw_bits
= ((given
>> 22) & 6) | ((given
>> W_BIT
) & 1);
7706 int ubit
= ! NEGATIVE_BIT_SET
;
7707 const char *rm
= arm_regnames
[given
& 0xf];
7708 const char *rn
= arm_regnames
[(given
>> 16) & 0xf];
7714 func (stream
, "[%s], %c%s", rn
, ubit
? '+' : '-', rm
);
7716 func (stream
, ", lsl #%d", imm4
);
7723 func (stream
, "[%s, %c%s", rn
, ubit
? '+' : '-', rm
);
7725 func (stream
, ", lsl #%d", imm4
);
7727 if (puw_bits
== 5 || puw_bits
== 7)
7732 func (stream
, "INVALID");
7740 imm5
= ((given
& 0x100) >> 4) | (given
& 0xf);
7741 func (stream
, "%ld", (imm5
== 0) ? 32 : imm5
);
7750 func (stream
, "%c", *c
);
7753 if (value_in_comment
> 32 || value_in_comment
< -16)
7754 func (stream
, "\t; 0x%lx", (value_in_comment
& 0xffffffffUL
));
7756 if (is_unpredictable
)
7757 func (stream
, UNPREDICTABLE_INSTRUCTION
);
7764 /* Decodes and prints ARM addressing modes. Returns the offset
7765 used in the address, if any, if it is worthwhile printing the
7766 offset as a hexadecimal value in a comment at the end of the
7767 line of disassembly. */
7770 print_arm_address (bfd_vma pc
, struct disassemble_info
*info
, long given
)
7772 void *stream
= info
->stream
;
7773 fprintf_ftype func
= info
->fprintf_func
;
7776 if (((given
& 0x000f0000) == 0x000f0000)
7777 && ((given
& 0x02000000) == 0))
7779 offset
= given
& 0xfff;
7781 func (stream
, "[pc");
7785 /* Pre-indexed. Elide offset of positive zero when
7787 if (WRITEBACK_BIT_SET
|| NEGATIVE_BIT_SET
|| offset
)
7788 func (stream
, ", #%s%d", NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
7790 if (NEGATIVE_BIT_SET
)
7795 /* Cope with the possibility of write-back
7796 being used. Probably a very dangerous thing
7797 for the programmer to do, but who are we to
7799 func (stream
, "]%s", WRITEBACK_BIT_SET
? "!" : "");
7801 else /* Post indexed. */
7803 func (stream
, "], #%s%d", NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
7805 /* Ie ignore the offset. */
7809 func (stream
, "\t; ");
7810 info
->print_address_func (offset
, info
);
7815 func (stream
, "[%s",
7816 arm_regnames
[(given
>> 16) & 0xf]);
7820 if ((given
& 0x02000000) == 0)
7822 /* Elide offset of positive zero when non-writeback. */
7823 offset
= given
& 0xfff;
7824 if (WRITEBACK_BIT_SET
|| NEGATIVE_BIT_SET
|| offset
)
7825 func (stream
, ", #%s%d", NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
7829 func (stream
, ", %s", NEGATIVE_BIT_SET
? "-" : "");
7830 arm_decode_shift (given
, func
, stream
, TRUE
);
7833 func (stream
, "]%s",
7834 WRITEBACK_BIT_SET
? "!" : "");
7838 if ((given
& 0x02000000) == 0)
7840 /* Always show offset. */
7841 offset
= given
& 0xfff;
7842 func (stream
, "], #%s%d",
7843 NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
7847 func (stream
, "], %s",
7848 NEGATIVE_BIT_SET
? "-" : "");
7849 arm_decode_shift (given
, func
, stream
, TRUE
);
7852 if (NEGATIVE_BIT_SET
)
7856 return (signed long) offset
;
7859 /* Print one neon instruction on INFO->STREAM.
7860 Return TRUE if the instuction matched, FALSE if this is not a
7861 recognised neon instruction. */
7864 print_insn_neon (struct disassemble_info
*info
, long given
, bfd_boolean thumb
)
7866 const struct opcode32
*insn
;
7867 void *stream
= info
->stream
;
7868 fprintf_ftype func
= info
->fprintf_func
;
7872 if ((given
& 0xef000000) == 0xef000000)
7874 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
7875 unsigned long bit28
= given
& (1 << 28);
7877 given
&= 0x00ffffff;
7879 given
|= 0xf3000000;
7881 given
|= 0xf2000000;
7883 else if ((given
& 0xff000000) == 0xf9000000)
7884 given
^= 0xf9000000 ^ 0xf4000000;
7885 /* vdup is also a valid neon instruction. */
7886 else if ((given
& 0xff910f5f) != 0xee800b10)
7890 for (insn
= neon_opcodes
; insn
->assembler
; insn
++)
7892 if ((given
& insn
->mask
) == insn
->value
)
7894 signed long value_in_comment
= 0;
7895 bfd_boolean is_unpredictable
= FALSE
;
7898 for (c
= insn
->assembler
; *c
; c
++)
7905 func (stream
, "%%");
7909 if (thumb
&& ifthen_state
)
7910 is_unpredictable
= TRUE
;
7914 if (thumb
&& ifthen_state
)
7915 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
7920 static const unsigned char enc
[16] =
7922 0x4, 0x14, /* st4 0,1 */
7934 int rd
= ((given
>> 12) & 0xf) | (((given
>> 22) & 1) << 4);
7935 int rn
= ((given
>> 16) & 0xf);
7936 int rm
= ((given
>> 0) & 0xf);
7937 int align
= ((given
>> 4) & 0x3);
7938 int type
= ((given
>> 8) & 0xf);
7939 int n
= enc
[type
] & 0xf;
7940 int stride
= (enc
[type
] >> 4) + 1;
7945 for (ix
= 0; ix
!= n
; ix
++)
7946 func (stream
, "%sd%d", ix
? "," : "", rd
+ ix
* stride
);
7948 func (stream
, "d%d", rd
);
7950 func (stream
, "d%d-d%d", rd
, rd
+ n
- 1);
7951 func (stream
, "}, [%s", arm_regnames
[rn
]);
7953 func (stream
, " :%d", 32 << align
);
7958 func (stream
, ", %s", arm_regnames
[rm
]);
7964 int rd
= ((given
>> 12) & 0xf) | (((given
>> 22) & 1) << 4);
7965 int rn
= ((given
>> 16) & 0xf);
7966 int rm
= ((given
>> 0) & 0xf);
7967 int idx_align
= ((given
>> 4) & 0xf);
7969 int size
= ((given
>> 10) & 0x3);
7970 int idx
= idx_align
>> (size
+ 1);
7971 int length
= ((given
>> 8) & 3) + 1;
7975 if (length
> 1 && size
> 0)
7976 stride
= (idx_align
& (1 << size
)) ? 2 : 1;
7982 int amask
= (1 << size
) - 1;
7983 if ((idx_align
& (1 << size
)) != 0)
7987 if ((idx_align
& amask
) == amask
)
7989 else if ((idx_align
& amask
) != 0)
7996 if (size
== 2 && (idx_align
& 2) != 0)
7998 align
= (idx_align
& 1) ? 16 << size
: 0;
8002 if ((size
== 2 && (idx_align
& 3) != 0)
8003 || (idx_align
& 1) != 0)
8010 if ((idx_align
& 3) == 3)
8012 align
= (idx_align
& 3) * 64;
8015 align
= (idx_align
& 1) ? 32 << size
: 0;
8023 for (i
= 0; i
< length
; i
++)
8024 func (stream
, "%sd%d[%d]", (i
== 0) ? "" : ",",
8025 rd
+ i
* stride
, idx
);
8026 func (stream
, "}, [%s", arm_regnames
[rn
]);
8028 func (stream
, " :%d", align
);
8033 func (stream
, ", %s", arm_regnames
[rm
]);
8039 int rd
= ((given
>> 12) & 0xf) | (((given
>> 22) & 1) << 4);
8040 int rn
= ((given
>> 16) & 0xf);
8041 int rm
= ((given
>> 0) & 0xf);
8042 int align
= ((given
>> 4) & 0x1);
8043 int size
= ((given
>> 6) & 0x3);
8044 int type
= ((given
>> 8) & 0x3);
8046 int stride
= ((given
>> 5) & 0x1);
8049 if (stride
&& (n
== 1))
8056 for (ix
= 0; ix
!= n
; ix
++)
8057 func (stream
, "%sd%d[]", ix
? "," : "", rd
+ ix
* stride
);
8059 func (stream
, "d%d[]", rd
);
8061 func (stream
, "d%d[]-d%d[]", rd
, rd
+ n
- 1);
8062 func (stream
, "}, [%s", arm_regnames
[rn
]);
8065 align
= (8 * (type
+ 1)) << size
;
8067 align
= (size
> 1) ? align
>> 1 : align
;
8068 if (type
== 2 || (type
== 0 && !size
))
8069 func (stream
, " :<bad align %d>", align
);
8071 func (stream
, " :%d", align
);
8077 func (stream
, ", %s", arm_regnames
[rm
]);
8083 int raw_reg
= (given
& 0xf) | ((given
>> 1) & 0x10);
8084 int size
= (given
>> 20) & 3;
8085 int reg
= raw_reg
& ((4 << size
) - 1);
8086 int ix
= raw_reg
>> size
>> 2;
8088 func (stream
, "d%d[%d]", reg
, ix
);
8093 /* Neon encoded constant for mov, mvn, vorr, vbic. */
8096 int cmode
= (given
>> 8) & 0xf;
8097 int op
= (given
>> 5) & 0x1;
8098 unsigned long value
= 0, hival
= 0;
8103 bits
|= ((given
>> 24) & 1) << 7;
8104 bits
|= ((given
>> 16) & 7) << 4;
8105 bits
|= ((given
>> 0) & 15) << 0;
8109 shift
= (cmode
>> 1) & 3;
8110 value
= (unsigned long) bits
<< (8 * shift
);
8113 else if (cmode
< 12)
8115 shift
= (cmode
>> 1) & 1;
8116 value
= (unsigned long) bits
<< (8 * shift
);
8119 else if (cmode
< 14)
8121 shift
= (cmode
& 1) + 1;
8122 value
= (unsigned long) bits
<< (8 * shift
);
8123 value
|= (1ul << (8 * shift
)) - 1;
8126 else if (cmode
== 14)
8130 /* Bit replication into bytes. */
8136 for (ix
= 7; ix
>= 0; ix
--)
8138 mask
= ((bits
>> ix
) & 1) ? 0xff : 0;
8140 value
= (value
<< 8) | mask
;
8142 hival
= (hival
<< 8) | mask
;
8148 /* Byte replication. */
8149 value
= (unsigned long) bits
;
8155 /* Floating point encoding. */
8158 value
= (unsigned long) (bits
& 0x7f) << 19;
8159 value
|= (unsigned long) (bits
& 0x80) << 24;
8160 tmp
= bits
& 0x40 ? 0x3c : 0x40;
8161 value
|= (unsigned long) tmp
<< 24;
8167 func (stream
, "<illegal constant %.8x:%x:%x>",
8175 func (stream
, "#%ld\t; 0x%.2lx", value
, value
);
8179 func (stream
, "#%ld\t; 0x%.4lx", value
, value
);
8185 unsigned char valbytes
[4];
8188 /* Do this a byte at a time so we don't have to
8189 worry about the host's endianness. */
8190 valbytes
[0] = value
& 0xff;
8191 valbytes
[1] = (value
>> 8) & 0xff;
8192 valbytes
[2] = (value
>> 16) & 0xff;
8193 valbytes
[3] = (value
>> 24) & 0xff;
8195 floatformat_to_double
8196 (& floatformat_ieee_single_little
, valbytes
,
8199 func (stream
, "#%.7g\t; 0x%.8lx", fvalue
,
8203 func (stream
, "#%ld\t; 0x%.8lx",
8204 (long) (((value
& 0x80000000L
) != 0)
8205 ? value
| ~0xffffffffL
: value
),
8210 func (stream
, "#0x%.8lx%.8lx", hival
, value
);
8221 int regno
= ((given
>> 16) & 0xf) | ((given
>> (7 - 4)) & 0x10);
8222 int num
= (given
>> 8) & 0x3;
8225 func (stream
, "{d%d}", regno
);
8226 else if (num
+ regno
>= 32)
8227 func (stream
, "{d%d-<overflow reg d%d}", regno
, regno
+ num
);
8229 func (stream
, "{d%d-d%d}", regno
, regno
+ num
);
8234 case '0': case '1': case '2': case '3': case '4':
8235 case '5': case '6': case '7': case '8': case '9':
8238 unsigned long value
;
8240 c
= arm_decode_bitfield (c
, given
, &value
, &width
);
8245 func (stream
, "%s", arm_regnames
[value
]);
8248 func (stream
, "%ld", value
);
8249 value_in_comment
= value
;
8252 func (stream
, "%ld", (1ul << width
) - value
);
8258 /* Various width encodings. */
8260 int base
= 8 << (*c
- 'S'); /* 8,16 or 32 */
8265 if (*c
>= '0' && *c
<= '9')
8267 else if (*c
>= 'a' && *c
<= 'f')
8268 limit
= *c
- 'a' + 10;
8274 if (value
< low
|| value
> high
)
8275 func (stream
, "<illegal width %d>", base
<< value
);
8277 func (stream
, "%d", base
<< value
);
8281 if (given
& (1 << 6))
8285 func (stream
, "d%ld", value
);
8290 func (stream
, "<illegal reg q%ld.5>", value
>> 1);
8292 func (stream
, "q%ld", value
>> 1);
8298 func (stream
, "%c", *c
);
8302 if (value
== ((1ul << width
) - 1))
8303 func (stream
, "%c", *c
);
8306 func (stream
, "%c", c
[(1 << width
) - (int) value
]);
8320 func (stream
, "%c", *c
);
8323 if (value_in_comment
> 32 || value_in_comment
< -16)
8324 func (stream
, "\t; 0x%lx", value_in_comment
);
8326 if (is_unpredictable
)
8327 func (stream
, UNPREDICTABLE_INSTRUCTION
);
8335 /* Print one mve instruction on INFO->STREAM.
8336 Return TRUE if the instuction matched, FALSE if this is not a
8337 recognised mve instruction. */
8340 print_insn_mve (struct disassemble_info
*info
, long given
)
8342 const struct mopcode32
*insn
;
8343 void *stream
= info
->stream
;
8344 fprintf_ftype func
= info
->fprintf_func
;
8346 for (insn
= mve_opcodes
; insn
->assembler
; insn
++)
8348 if (((given
& insn
->mask
) == insn
->value
)
8349 && !is_mve_encoding_conflict (given
, insn
->mve_op
))
8351 signed long value_in_comment
= 0;
8352 bfd_boolean is_unpredictable
= FALSE
;
8353 bfd_boolean is_undefined
= FALSE
;
8355 enum mve_unpredictable unpredictable_cond
= UNPRED_NONE
;
8356 enum mve_undefined undefined_cond
= UNDEF_NONE
;
8358 /* Most vector mve instruction are illegal in a it block.
8359 There are a few exceptions; check for them. */
8360 if (ifthen_state
&& !is_mve_okay_in_it (insn
->mve_op
))
8362 is_unpredictable
= TRUE
;
8363 unpredictable_cond
= UNPRED_IT_BLOCK
;
8365 else if (is_mve_unpredictable (given
, insn
->mve_op
,
8366 &unpredictable_cond
))
8367 is_unpredictable
= TRUE
;
8369 if (is_mve_undefined (given
, insn
->mve_op
, &undefined_cond
))
8370 is_undefined
= TRUE
;
8372 for (c
= insn
->assembler
; *c
; c
++)
8379 func (stream
, "%%");
8383 /* Don't print anything for '+' as it is implied. */
8384 if (arm_decode_field (given
, 23, 23) == 0)
8390 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
8394 print_mve_vld_str_addr (info
, given
, insn
->mve_op
);
8399 long mve_mask
= mve_extract_pred_mask (given
);
8400 func (stream
, "%s", mve_predicatenames
[mve_mask
]);
8405 print_vec_condition (info
, given
, insn
->mve_op
);
8409 if (arm_decode_field (given
, 0, 0) == 1)
8412 = arm_decode_field (given
, 4, 4)
8413 | (arm_decode_field (given
, 6, 6) << 1);
8415 func (stream
, ", uxtw #%lu", size
);
8420 print_mve_rounding_mode (info
, given
, insn
->mve_op
);
8424 print_mve_vcvt_size (info
, given
, insn
->mve_op
);
8429 unsigned long op1
= arm_decode_field (given
, 21, 22);
8431 if ((insn
->mve_op
== MVE_VMOV_VEC_LANE_TO_GP
))
8433 /* Check for signed. */
8434 if (arm_decode_field (given
, 23, 23) == 0)
8436 /* We don't print 's' for S32. */
8437 if ((arm_decode_field (given
, 5, 6) == 0)
8438 && ((op1
== 0) || (op1
== 1)))
8448 if (arm_decode_field (given
, 28, 28) == 0)
8457 print_instruction_predicate (info
);
8461 if (arm_decode_field (given
, 21, 21) == 1)
8466 print_mve_register_blocks (info
, given
, insn
->mve_op
);
8470 /* SIMD encoded constant for mov, mvn, vorr, vbic. */
8472 print_simd_imm8 (info
, given
, 28, insn
);
8476 print_mve_vmov_index (info
, given
);
8480 if (arm_decode_field (given
, 12, 12) == 0)
8487 if (arm_decode_field (given
, 12, 12) == 1)
8491 case '0': case '1': case '2': case '3': case '4':
8492 case '5': case '6': case '7': case '8': case '9':
8495 unsigned long value
;
8497 c
= arm_decode_bitfield (c
, given
, &value
, &width
);
8503 is_unpredictable
= TRUE
;
8504 else if (value
== 15)
8505 func (stream
, "zr");
8507 func (stream
, "%s", arm_regnames
[value
]);
8510 print_mve_size (info
,
8520 unsigned int odd_reg
= (value
<< 1) | 1;
8521 func (stream
, "%s", arm_regnames
[odd_reg
]);
8527 = arm_decode_field (given
, 0, 6);
8528 unsigned long mod_imm
= imm
;
8530 switch (insn
->mve_op
)
8532 case MVE_VLDRW_GATHER_T5
:
8533 case MVE_VSTRW_SCATTER_T5
:
8534 mod_imm
= mod_imm
<< 2;
8536 case MVE_VSTRD_SCATTER_T6
:
8537 case MVE_VLDRD_GATHER_T6
:
8538 mod_imm
= mod_imm
<< 3;
8545 func (stream
, "%lu", mod_imm
);
8549 func (stream
, "%lu", 64 - value
);
8553 unsigned int even_reg
= value
<< 1;
8554 func (stream
, "%s", arm_regnames
[even_reg
]);
8577 print_mve_rotate (info
, value
, width
);
8580 func (stream
, "%s", arm_regnames
[value
]);
8583 if (insn
->mve_op
== MVE_VQSHL_T2
8584 || insn
->mve_op
== MVE_VQSHLU_T3
8585 || insn
->mve_op
== MVE_VRSHR
8586 || insn
->mve_op
== MVE_VRSHRN
8587 || insn
->mve_op
== MVE_VSHL_T1
8588 || insn
->mve_op
== MVE_VSHLL_T1
8589 || insn
->mve_op
== MVE_VSHR
8590 || insn
->mve_op
== MVE_VSHRN
8591 || insn
->mve_op
== MVE_VSLI
8592 || insn
->mve_op
== MVE_VSRI
)
8593 print_mve_shift_n (info
, given
, insn
->mve_op
);
8594 else if (insn
->mve_op
== MVE_VSHLL_T2
)
8602 func (stream
, "16");
8605 print_mve_undefined (info
, UNDEF_SIZE_0
);
8614 if (insn
->mve_op
== MVE_VSHLC
&& value
== 0)
8616 func (stream
, "%ld", value
);
8617 value_in_comment
= value
;
8621 func (stream
, "s%ld", value
);
8625 func (stream
, "<illegal reg q%ld.5>", value
);
8627 func (stream
, "q%ld", value
);
8630 func (stream
, "0x%08lx", value
);
8642 func (stream
, "%c", *c
);
8645 if (value_in_comment
> 32 || value_in_comment
< -16)
8646 func (stream
, "\t; 0x%lx", value_in_comment
);
8648 if (is_unpredictable
)
8649 print_mve_unpredictable (info
, unpredictable_cond
);
8652 print_mve_undefined (info
, undefined_cond
);
8654 if ((vpt_block_state
.in_vpt_block
== FALSE
)
8656 && (is_vpt_instruction (given
) == TRUE
))
8657 mark_inside_vpt_block (given
);
8658 else if (vpt_block_state
.in_vpt_block
== TRUE
)
8659 update_vpt_block_state ();
8668 /* Return the name of a v7A special register. */
8671 banked_regname (unsigned reg
)
8675 case 15: return "CPSR";
8676 case 32: return "R8_usr";
8677 case 33: return "R9_usr";
8678 case 34: return "R10_usr";
8679 case 35: return "R11_usr";
8680 case 36: return "R12_usr";
8681 case 37: return "SP_usr";
8682 case 38: return "LR_usr";
8683 case 40: return "R8_fiq";
8684 case 41: return "R9_fiq";
8685 case 42: return "R10_fiq";
8686 case 43: return "R11_fiq";
8687 case 44: return "R12_fiq";
8688 case 45: return "SP_fiq";
8689 case 46: return "LR_fiq";
8690 case 48: return "LR_irq";
8691 case 49: return "SP_irq";
8692 case 50: return "LR_svc";
8693 case 51: return "SP_svc";
8694 case 52: return "LR_abt";
8695 case 53: return "SP_abt";
8696 case 54: return "LR_und";
8697 case 55: return "SP_und";
8698 case 60: return "LR_mon";
8699 case 61: return "SP_mon";
8700 case 62: return "ELR_hyp";
8701 case 63: return "SP_hyp";
8702 case 79: return "SPSR";
8703 case 110: return "SPSR_fiq";
8704 case 112: return "SPSR_irq";
8705 case 114: return "SPSR_svc";
8706 case 116: return "SPSR_abt";
8707 case 118: return "SPSR_und";
8708 case 124: return "SPSR_mon";
8709 case 126: return "SPSR_hyp";
8710 default: return NULL
;
8714 /* Return the name of the DMB/DSB option. */
8716 data_barrier_option (unsigned option
)
8718 switch (option
& 0xf)
8720 case 0xf: return "sy";
8721 case 0xe: return "st";
8722 case 0xd: return "ld";
8723 case 0xb: return "ish";
8724 case 0xa: return "ishst";
8725 case 0x9: return "ishld";
8726 case 0x7: return "un";
8727 case 0x6: return "unst";
8728 case 0x5: return "nshld";
8729 case 0x3: return "osh";
8730 case 0x2: return "oshst";
8731 case 0x1: return "oshld";
8732 default: return NULL
;
8736 /* Print one ARM instruction from PC on INFO->STREAM. */
8739 print_insn_arm (bfd_vma pc
, struct disassemble_info
*info
, long given
)
8741 const struct opcode32
*insn
;
8742 void *stream
= info
->stream
;
8743 fprintf_ftype func
= info
->fprintf_func
;
8744 struct arm_private_data
*private_data
= info
->private_data
;
8746 if (print_insn_coprocessor (pc
, info
, given
, FALSE
))
8749 if (print_insn_neon (info
, given
, FALSE
))
8752 for (insn
= arm_opcodes
; insn
->assembler
; insn
++)
8754 if ((given
& insn
->mask
) != insn
->value
)
8757 if (! ARM_CPU_HAS_FEATURE (insn
->arch
, private_data
->features
))
8760 /* Special case: an instruction with all bits set in the condition field
8761 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
8762 or by the catchall at the end of the table. */
8763 if ((given
& 0xF0000000) != 0xF0000000
8764 || (insn
->mask
& 0xF0000000) == 0xF0000000
8765 || (insn
->mask
== 0 && insn
->value
== 0))
8767 unsigned long u_reg
= 16;
8768 unsigned long U_reg
= 16;
8769 bfd_boolean is_unpredictable
= FALSE
;
8770 signed long value_in_comment
= 0;
8773 for (c
= insn
->assembler
; *c
; c
++)
8777 bfd_boolean allow_unpredictable
= FALSE
;
8782 func (stream
, "%%");
8786 value_in_comment
= print_arm_address (pc
, info
, given
);
8790 /* Set P address bit and use normal address
8791 printing routine. */
8792 value_in_comment
= print_arm_address (pc
, info
, given
| (1 << P_BIT
));
8796 allow_unpredictable
= TRUE
;
8799 if ((given
& 0x004f0000) == 0x004f0000)
8801 /* PC relative with immediate offset. */
8802 bfd_vma offset
= ((given
& 0xf00) >> 4) | (given
& 0xf);
8806 /* Elide positive zero offset. */
8807 if (offset
|| NEGATIVE_BIT_SET
)
8808 func (stream
, "[pc, #%s%d]\t; ",
8809 NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
8811 func (stream
, "[pc]\t; ");
8812 if (NEGATIVE_BIT_SET
)
8814 info
->print_address_func (offset
+ pc
+ 8, info
);
8818 /* Always show the offset. */
8819 func (stream
, "[pc], #%s%d",
8820 NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
8821 if (! allow_unpredictable
)
8822 is_unpredictable
= TRUE
;
8827 int offset
= ((given
& 0xf00) >> 4) | (given
& 0xf);
8829 func (stream
, "[%s",
8830 arm_regnames
[(given
>> 16) & 0xf]);
8834 if (IMMEDIATE_BIT_SET
)
8836 /* Elide offset for non-writeback
8838 if (WRITEBACK_BIT_SET
|| NEGATIVE_BIT_SET
8840 func (stream
, ", #%s%d",
8841 NEGATIVE_BIT_SET
? "-" : "", offset
);
8843 if (NEGATIVE_BIT_SET
)
8846 value_in_comment
= offset
;
8850 /* Register Offset or Register Pre-Indexed. */
8851 func (stream
, ", %s%s",
8852 NEGATIVE_BIT_SET
? "-" : "",
8853 arm_regnames
[given
& 0xf]);
8855 /* Writing back to the register that is the source/
8856 destination of the load/store is unpredictable. */
8857 if (! allow_unpredictable
8858 && WRITEBACK_BIT_SET
8859 && ((given
& 0xf) == ((given
>> 12) & 0xf)))
8860 is_unpredictable
= TRUE
;
8863 func (stream
, "]%s",
8864 WRITEBACK_BIT_SET
? "!" : "");
8868 if (IMMEDIATE_BIT_SET
)
8870 /* Immediate Post-indexed. */
8871 /* PR 10924: Offset must be printed, even if it is zero. */
8872 func (stream
, "], #%s%d",
8873 NEGATIVE_BIT_SET
? "-" : "", offset
);
8874 if (NEGATIVE_BIT_SET
)
8876 value_in_comment
= offset
;
8880 /* Register Post-indexed. */
8881 func (stream
, "], %s%s",
8882 NEGATIVE_BIT_SET
? "-" : "",
8883 arm_regnames
[given
& 0xf]);
8885 /* Writing back to the register that is the source/
8886 destination of the load/store is unpredictable. */
8887 if (! allow_unpredictable
8888 && (given
& 0xf) == ((given
>> 12) & 0xf))
8889 is_unpredictable
= TRUE
;
8892 if (! allow_unpredictable
)
8894 /* Writeback is automatically implied by post- addressing.
8895 Setting the W bit is unnecessary and ARM specify it as
8896 being unpredictable. */
8897 if (WRITEBACK_BIT_SET
8898 /* Specifying the PC register as the post-indexed
8899 registers is also unpredictable. */
8900 || (! IMMEDIATE_BIT_SET
&& ((given
& 0xf) == 0xf)))
8901 is_unpredictable
= TRUE
;
8909 bfd_vma disp
= (((given
& 0xffffff) ^ 0x800000) - 0x800000);
8910 info
->print_address_func (disp
* 4 + pc
+ 8, info
);
8915 if (((given
>> 28) & 0xf) != 0xe)
8917 arm_conditional
[(given
>> 28) & 0xf]);
8926 for (reg
= 0; reg
< 16; reg
++)
8927 if ((given
& (1 << reg
)) != 0)
8930 func (stream
, ", ");
8932 func (stream
, "%s", arm_regnames
[reg
]);
8936 is_unpredictable
= TRUE
;
8941 arm_decode_shift (given
, func
, stream
, FALSE
);
8945 if ((given
& 0x02000000) != 0)
8947 unsigned int rotate
= (given
& 0xf00) >> 7;
8948 unsigned int immed
= (given
& 0xff);
8951 a
= (((immed
<< (32 - rotate
))
8952 | (immed
>> rotate
)) & 0xffffffff);
8953 /* If there is another encoding with smaller rotate,
8954 the rotate should be specified directly. */
8955 for (i
= 0; i
< 32; i
+= 2)
8956 if ((a
<< i
| a
>> (32 - i
)) <= 0xff)
8960 func (stream
, "#%d, %d", immed
, rotate
);
8962 func (stream
, "#%d", a
);
8963 value_in_comment
= a
;
8966 arm_decode_shift (given
, func
, stream
, TRUE
);
8970 if ((given
& 0x0000f000) == 0x0000f000)
8972 arm_feature_set arm_ext_v6
=
8973 ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
8975 /* The p-variants of tst/cmp/cmn/teq are the pre-V6
8976 mechanism for setting PSR flag bits. They are
8977 obsolete in V6 onwards. */
8978 if (! ARM_CPU_HAS_FEATURE (private_data
->features
, \
8982 is_unpredictable
= TRUE
;
8987 if ((given
& 0x01200000) == 0x00200000)
8993 int offset
= given
& 0xff;
8995 value_in_comment
= offset
* 4;
8996 if (NEGATIVE_BIT_SET
)
8997 value_in_comment
= - value_in_comment
;
8999 func (stream
, "[%s", arm_regnames
[(given
>> 16) & 0xf]);
9004 func (stream
, ", #%d]%s",
9005 (int) value_in_comment
,
9006 WRITEBACK_BIT_SET
? "!" : "");
9014 if (WRITEBACK_BIT_SET
)
9017 func (stream
, ", #%d", (int) value_in_comment
);
9021 func (stream
, ", {%d}", (int) offset
);
9022 value_in_comment
= offset
;
9029 /* Print ARM V5 BLX(1) address: pc+25 bits. */
9034 if (! NEGATIVE_BIT_SET
)
9035 /* Is signed, hi bits should be ones. */
9036 offset
= (-1) ^ 0x00ffffff;
9038 /* Offset is (SignExtend(offset field)<<2). */
9039 offset
+= given
& 0x00ffffff;
9041 address
= offset
+ pc
+ 8;
9043 if (given
& 0x01000000)
9044 /* H bit allows addressing to 2-byte boundaries. */
9047 info
->print_address_func (address
, info
);
9052 if ((given
& 0x02000200) == 0x200)
9055 unsigned sysm
= (given
& 0x004f0000) >> 16;
9057 sysm
|= (given
& 0x300) >> 4;
9058 name
= banked_regname (sysm
);
9061 func (stream
, "%s", name
);
9063 func (stream
, "(UNDEF: %lu)", (unsigned long) sysm
);
9067 func (stream
, "%cPSR_",
9068 (given
& 0x00400000) ? 'S' : 'C');
9069 if (given
& 0x80000)
9071 if (given
& 0x40000)
9073 if (given
& 0x20000)
9075 if (given
& 0x10000)
9081 if ((given
& 0xf0) == 0x60)
9083 switch (given
& 0xf)
9085 case 0xf: func (stream
, "sy"); break;
9087 func (stream
, "#%d", (int) given
& 0xf);
9093 const char * opt
= data_barrier_option (given
& 0xf);
9095 func (stream
, "%s", opt
);
9097 func (stream
, "#%d", (int) given
& 0xf);
9101 case '0': case '1': case '2': case '3': case '4':
9102 case '5': case '6': case '7': case '8': case '9':
9105 unsigned long value
;
9107 c
= arm_decode_bitfield (c
, given
, &value
, &width
);
9113 is_unpredictable
= TRUE
;
9117 /* We want register + 1 when decoding T. */
9123 /* Eat the 'u' character. */
9127 is_unpredictable
= TRUE
;
9132 /* Eat the 'U' character. */
9136 is_unpredictable
= TRUE
;
9139 func (stream
, "%s", arm_regnames
[value
]);
9142 func (stream
, "%ld", value
);
9143 value_in_comment
= value
;
9146 func (stream
, "%ld", value
* 8);
9147 value_in_comment
= value
* 8;
9150 func (stream
, "%ld", value
+ 1);
9151 value_in_comment
= value
+ 1;
9154 func (stream
, "0x%08lx", value
);
9156 /* Some SWI instructions have special
9158 if ((given
& 0x0fffffff) == 0x0FF00000)
9159 func (stream
, "\t; IMB");
9160 else if ((given
& 0x0fffffff) == 0x0FF00001)
9161 func (stream
, "\t; IMBRange");
9164 func (stream
, "%01lx", value
& 0xf);
9165 value_in_comment
= value
;
9170 func (stream
, "%c", *c
);
9174 if (value
== ((1ul << width
) - 1))
9175 func (stream
, "%c", *c
);
9178 func (stream
, "%c", c
[(1 << width
) - (int) value
]);
9191 imm
= (given
& 0xf) | ((given
& 0xfff00) >> 4);
9192 func (stream
, "%d", imm
);
9193 value_in_comment
= imm
;
9198 /* LSB and WIDTH fields of BFI or BFC. The machine-
9199 language instruction encodes LSB and MSB. */
9201 long msb
= (given
& 0x001f0000) >> 16;
9202 long lsb
= (given
& 0x00000f80) >> 7;
9203 long w
= msb
- lsb
+ 1;
9206 func (stream
, "#%lu, #%lu", lsb
, w
);
9208 func (stream
, "(invalid: %lu:%lu)", lsb
, msb
);
9213 /* Get the PSR/banked register name. */
9216 unsigned sysm
= (given
& 0x004f0000) >> 16;
9218 sysm
|= (given
& 0x300) >> 4;
9219 name
= banked_regname (sysm
);
9222 func (stream
, "%s", name
);
9224 func (stream
, "(UNDEF: %lu)", (unsigned long) sysm
);
9229 /* 16-bit unsigned immediate from a MOVT or MOVW
9230 instruction, encoded in bits 0:11 and 15:19. */
9232 long hi
= (given
& 0x000f0000) >> 4;
9233 long lo
= (given
& 0x00000fff);
9234 long imm16
= hi
| lo
;
9236 func (stream
, "#%lu", imm16
);
9237 value_in_comment
= imm16
;
9246 func (stream
, "%c", *c
);
9249 if (value_in_comment
> 32 || value_in_comment
< -16)
9250 func (stream
, "\t; 0x%lx", (value_in_comment
& 0xffffffffUL
));
9252 if (is_unpredictable
)
9253 func (stream
, UNPREDICTABLE_INSTRUCTION
);
9258 func (stream
, UNKNOWN_INSTRUCTION_32BIT
, (unsigned)given
);
9262 /* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
9265 print_insn_thumb16 (bfd_vma pc
, struct disassemble_info
*info
, long given
)
9267 const struct opcode16
*insn
;
9268 void *stream
= info
->stream
;
9269 fprintf_ftype func
= info
->fprintf_func
;
9271 for (insn
= thumb_opcodes
; insn
->assembler
; insn
++)
9272 if ((given
& insn
->mask
) == insn
->value
)
9274 signed long value_in_comment
= 0;
9275 const char *c
= insn
->assembler
;
9284 func (stream
, "%c", *c
);
9291 func (stream
, "%%");
9296 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
9301 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
9310 ifthen_next_state
= given
& 0xff;
9311 for (tmp
= given
<< 1; tmp
& 0xf; tmp
<<= 1)
9312 func (stream
, ((given
^ tmp
) & 0x10) ? "e" : "t");
9313 func (stream
, "\t%s", arm_conditional
[(given
>> 4) & 0xf]);
9318 if (ifthen_next_state
)
9319 func (stream
, "\t; unpredictable branch in IT block\n");
9324 func (stream
, "\t; unpredictable <IT:%s>",
9325 arm_conditional
[IFTHEN_COND
]);
9332 reg
= (given
>> 3) & 0x7;
9333 if (given
& (1 << 6))
9336 func (stream
, "%s", arm_regnames
[reg
]);
9345 if (given
& (1 << 7))
9348 func (stream
, "%s", arm_regnames
[reg
]);
9353 if (given
& (1 << 8))
9357 if (*c
== 'O' && (given
& (1 << 8)))
9367 /* It would be nice if we could spot
9368 ranges, and generate the rS-rE format: */
9369 for (reg
= 0; (reg
< 8); reg
++)
9370 if ((given
& (1 << reg
)) != 0)
9373 func (stream
, ", ");
9375 func (stream
, "%s", arm_regnames
[reg
]);
9381 func (stream
, ", ");
9383 func (stream
, "%s", arm_regnames
[14] /* "lr" */);
9389 func (stream
, ", ");
9390 func (stream
, "%s", arm_regnames
[15] /* "pc" */);
9398 /* Print writeback indicator for a LDMIA. We are doing a
9399 writeback if the base register is not in the register
9401 if ((given
& (1 << ((given
& 0x0700) >> 8))) == 0)
9406 /* Print ARM V6T2 CZB address: pc+4+6 bits. */
9408 bfd_vma address
= (pc
+ 4
9409 + ((given
& 0x00f8) >> 2)
9410 + ((given
& 0x0200) >> 3));
9411 info
->print_address_func (address
, info
);
9416 /* Right shift immediate -- bits 6..10; 1-31 print
9417 as themselves, 0 prints as 32. */
9419 long imm
= (given
& 0x07c0) >> 6;
9422 func (stream
, "#%ld", imm
);
9426 case '0': case '1': case '2': case '3': case '4':
9427 case '5': case '6': case '7': case '8': case '9':
9429 int bitstart
= *c
++ - '0';
9432 while (*c
>= '0' && *c
<= '9')
9433 bitstart
= (bitstart
* 10) + *c
++ - '0';
9442 while (*c
>= '0' && *c
<= '9')
9443 bitend
= (bitend
* 10) + *c
++ - '0';
9446 reg
= given
>> bitstart
;
9447 reg
&= (2 << (bitend
- bitstart
)) - 1;
9452 func (stream
, "%s", arm_regnames
[reg
]);
9456 func (stream
, "%ld", (long) reg
);
9457 value_in_comment
= reg
;
9461 func (stream
, "%ld", (long) (reg
<< 1));
9462 value_in_comment
= reg
<< 1;
9466 func (stream
, "%ld", (long) (reg
<< 2));
9467 value_in_comment
= reg
<< 2;
9471 /* PC-relative address -- the bottom two
9472 bits of the address are dropped
9473 before the calculation. */
9474 info
->print_address_func
9475 (((pc
+ 4) & ~3) + (reg
<< 2), info
);
9476 value_in_comment
= 0;
9480 func (stream
, "0x%04lx", (long) reg
);
9484 reg
= ((reg
^ (1 << bitend
)) - (1 << bitend
));
9485 info
->print_address_func (reg
* 2 + pc
+ 4, info
);
9486 value_in_comment
= 0;
9490 func (stream
, "%s", arm_conditional
[reg
]);
9501 if ((given
& (1 << bitstart
)) != 0)
9502 func (stream
, "%c", *c
);
9507 if ((given
& (1 << bitstart
)) != 0)
9508 func (stream
, "%c", *c
++);
9510 func (stream
, "%c", *++c
);
9524 if (value_in_comment
> 32 || value_in_comment
< -16)
9525 func (stream
, "\t; 0x%lx", value_in_comment
);
9530 func (stream
, UNKNOWN_INSTRUCTION_16BIT
, (unsigned)given
);
9534 /* Return the name of an V7M special register. */
9537 psr_name (int regno
)
9541 case 0x0: return "APSR";
9542 case 0x1: return "IAPSR";
9543 case 0x2: return "EAPSR";
9544 case 0x3: return "PSR";
9545 case 0x5: return "IPSR";
9546 case 0x6: return "EPSR";
9547 case 0x7: return "IEPSR";
9548 case 0x8: return "MSP";
9549 case 0x9: return "PSP";
9550 case 0xa: return "MSPLIM";
9551 case 0xb: return "PSPLIM";
9552 case 0x10: return "PRIMASK";
9553 case 0x11: return "BASEPRI";
9554 case 0x12: return "BASEPRI_MAX";
9555 case 0x13: return "FAULTMASK";
9556 case 0x14: return "CONTROL";
9557 case 0x88: return "MSP_NS";
9558 case 0x89: return "PSP_NS";
9559 case 0x8a: return "MSPLIM_NS";
9560 case 0x8b: return "PSPLIM_NS";
9561 case 0x90: return "PRIMASK_NS";
9562 case 0x91: return "BASEPRI_NS";
9563 case 0x93: return "FAULTMASK_NS";
9564 case 0x94: return "CONTROL_NS";
9565 case 0x98: return "SP_NS";
9566 default: return "<unknown>";
9570 /* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
9573 print_insn_thumb32 (bfd_vma pc
, struct disassemble_info
*info
, long given
)
9575 const struct opcode32
*insn
;
9576 void *stream
= info
->stream
;
9577 fprintf_ftype func
= info
->fprintf_func
;
9578 bfd_boolean is_mve
= is_mve_architecture (info
);
9580 if (print_insn_coprocessor (pc
, info
, given
, TRUE
))
9583 if ((is_mve
== FALSE
) && print_insn_neon (info
, given
, TRUE
))
9586 if (is_mve
&& print_insn_mve (info
, given
))
9589 for (insn
= thumb32_opcodes
; insn
->assembler
; insn
++)
9590 if ((given
& insn
->mask
) == insn
->value
)
9592 bfd_boolean is_clrm
= FALSE
;
9593 bfd_boolean is_unpredictable
= FALSE
;
9594 signed long value_in_comment
= 0;
9595 const char *c
= insn
->assembler
;
9601 func (stream
, "%c", *c
);
9608 func (stream
, "%%");
9613 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
9617 if (ifthen_next_state
)
9618 func (stream
, "\t; unpredictable branch in IT block\n");
9623 func (stream
, "\t; unpredictable <IT:%s>",
9624 arm_conditional
[IFTHEN_COND
]);
9629 unsigned int imm12
= 0;
9631 imm12
|= (given
& 0x000000ffu
);
9632 imm12
|= (given
& 0x00007000u
) >> 4;
9633 imm12
|= (given
& 0x04000000u
) >> 15;
9634 func (stream
, "#%u", imm12
);
9635 value_in_comment
= imm12
;
9641 unsigned int bits
= 0, imm
, imm8
, mod
;
9643 bits
|= (given
& 0x000000ffu
);
9644 bits
|= (given
& 0x00007000u
) >> 4;
9645 bits
|= (given
& 0x04000000u
) >> 15;
9646 imm8
= (bits
& 0x0ff);
9647 mod
= (bits
& 0xf00) >> 8;
9650 case 0: imm
= imm8
; break;
9651 case 1: imm
= ((imm8
<< 16) | imm8
); break;
9652 case 2: imm
= ((imm8
<< 24) | (imm8
<< 8)); break;
9653 case 3: imm
= ((imm8
<< 24) | (imm8
<< 16) | (imm8
<< 8) | imm8
); break;
9655 mod
= (bits
& 0xf80) >> 7;
9656 imm8
= (bits
& 0x07f) | 0x80;
9657 imm
= (((imm8
<< (32 - mod
)) | (imm8
>> mod
)) & 0xffffffff);
9659 func (stream
, "#%u", imm
);
9660 value_in_comment
= imm
;
9666 unsigned int imm
= 0;
9668 imm
|= (given
& 0x000000ffu
);
9669 imm
|= (given
& 0x00007000u
) >> 4;
9670 imm
|= (given
& 0x04000000u
) >> 15;
9671 imm
|= (given
& 0x000f0000u
) >> 4;
9672 func (stream
, "#%u", imm
);
9673 value_in_comment
= imm
;
9679 unsigned int imm
= 0;
9681 imm
|= (given
& 0x000f0000u
) >> 16;
9682 imm
|= (given
& 0x00000ff0u
) >> 0;
9683 imm
|= (given
& 0x0000000fu
) << 12;
9684 func (stream
, "#%u", imm
);
9685 value_in_comment
= imm
;
9691 unsigned int imm
= 0;
9693 imm
|= (given
& 0x000f0000u
) >> 4;
9694 imm
|= (given
& 0x00000fffu
) >> 0;
9695 func (stream
, "#%u", imm
);
9696 value_in_comment
= imm
;
9702 unsigned int imm
= 0;
9704 imm
|= (given
& 0x00000fffu
);
9705 imm
|= (given
& 0x000f0000u
) >> 4;
9706 func (stream
, "#%u", imm
);
9707 value_in_comment
= imm
;
9713 unsigned int reg
= (given
& 0x0000000fu
);
9714 unsigned int stp
= (given
& 0x00000030u
) >> 4;
9715 unsigned int imm
= 0;
9716 imm
|= (given
& 0x000000c0u
) >> 6;
9717 imm
|= (given
& 0x00007000u
) >> 10;
9719 func (stream
, "%s", arm_regnames
[reg
]);
9724 func (stream
, ", lsl #%u", imm
);
9730 func (stream
, ", lsr #%u", imm
);
9736 func (stream
, ", asr #%u", imm
);
9741 func (stream
, ", rrx");
9743 func (stream
, ", ror #%u", imm
);
9750 unsigned int Rn
= (given
& 0x000f0000) >> 16;
9751 unsigned int U
= ! NEGATIVE_BIT_SET
;
9752 unsigned int op
= (given
& 0x00000f00) >> 8;
9753 unsigned int i12
= (given
& 0x00000fff);
9754 unsigned int i8
= (given
& 0x000000ff);
9755 bfd_boolean writeback
= FALSE
, postind
= FALSE
;
9758 func (stream
, "[%s", arm_regnames
[Rn
]);
9759 if (U
) /* 12-bit positive immediate offset. */
9763 value_in_comment
= offset
;
9765 else if (Rn
== 15) /* 12-bit negative immediate offset. */
9766 offset
= - (int) i12
;
9767 else if (op
== 0x0) /* Shifted register offset. */
9769 unsigned int Rm
= (i8
& 0x0f);
9770 unsigned int sh
= (i8
& 0x30) >> 4;
9772 func (stream
, ", %s", arm_regnames
[Rm
]);
9774 func (stream
, ", lsl #%u", sh
);
9780 case 0xE: /* 8-bit positive immediate offset. */
9784 case 0xC: /* 8-bit negative immediate offset. */
9788 case 0xF: /* 8-bit + preindex with wb. */
9793 case 0xD: /* 8-bit - preindex with wb. */
9798 case 0xB: /* 8-bit + postindex. */
9803 case 0x9: /* 8-bit - postindex. */
9809 func (stream
, ", <undefined>]");
9814 func (stream
, "], #%d", (int) offset
);
9818 func (stream
, ", #%d", (int) offset
);
9819 func (stream
, writeback
? "]!" : "]");
9824 func (stream
, "\t; ");
9825 info
->print_address_func (((pc
+ 4) & ~3) + offset
, info
);
9833 unsigned int U
= ! NEGATIVE_BIT_SET
;
9834 unsigned int W
= WRITEBACK_BIT_SET
;
9835 unsigned int Rn
= (given
& 0x000f0000) >> 16;
9836 unsigned int off
= (given
& 0x000000ff);
9838 func (stream
, "[%s", arm_regnames
[Rn
]);
9844 func (stream
, ", #%c%u", U
? '+' : '-', off
* 4);
9845 value_in_comment
= off
* 4 * (U
? 1 : -1);
9853 func (stream
, "], ");
9856 func (stream
, "#%c%u", U
? '+' : '-', off
* 4);
9857 value_in_comment
= off
* 4 * (U
? 1 : -1);
9861 func (stream
, "{%u}", off
);
9862 value_in_comment
= off
;
9870 unsigned int Sbit
= (given
& 0x01000000) >> 24;
9871 unsigned int type
= (given
& 0x00600000) >> 21;
9875 case 0: func (stream
, Sbit
? "sb" : "b"); break;
9876 case 1: func (stream
, Sbit
? "sh" : "h"); break;
9879 func (stream
, "??");
9882 func (stream
, "??");
9897 for (reg
= 0; reg
< 16; reg
++)
9898 if ((given
& (1 << reg
)) != 0)
9901 func (stream
, ", ");
9903 if (is_clrm
&& reg
== 13)
9904 func (stream
, "(invalid: %s)", arm_regnames
[reg
]);
9905 else if (is_clrm
&& reg
== 15)
9906 func (stream
, "%s", "APSR");
9908 func (stream
, "%s", arm_regnames
[reg
]);
9916 unsigned int msb
= (given
& 0x0000001f);
9917 unsigned int lsb
= 0;
9919 lsb
|= (given
& 0x000000c0u
) >> 6;
9920 lsb
|= (given
& 0x00007000u
) >> 10;
9921 func (stream
, "#%u, #%u", lsb
, msb
- lsb
+ 1);
9927 unsigned int width
= (given
& 0x0000001f) + 1;
9928 unsigned int lsb
= 0;
9930 lsb
|= (given
& 0x000000c0u
) >> 6;
9931 lsb
|= (given
& 0x00007000u
) >> 10;
9932 func (stream
, "#%u, #%u", lsb
, width
);
9938 unsigned int boff
= (((given
& 0x07800000) >> 23) << 1);
9939 func (stream
, "%x", boff
);
9945 unsigned int immA
= (given
& 0x001f0000u
) >> 16;
9946 unsigned int immB
= (given
& 0x000007feu
) >> 1;
9947 unsigned int immC
= (given
& 0x00000800u
) >> 11;
9950 offset
|= immA
<< 12;
9951 offset
|= immB
<< 2;
9952 offset
|= immC
<< 1;
9954 offset
= (offset
& 0x10000) ? offset
- (1 << 17) : offset
;
9956 info
->print_address_func (pc
+ 4 + offset
, info
);
9962 unsigned int immA
= (given
& 0x007f0000u
) >> 16;
9963 unsigned int immB
= (given
& 0x000007feu
) >> 1;
9964 unsigned int immC
= (given
& 0x00000800u
) >> 11;
9967 offset
|= immA
<< 12;
9968 offset
|= immB
<< 2;
9969 offset
|= immC
<< 1;
9971 offset
= (offset
& 0x40000) ? offset
- (1 << 19) : offset
;
9973 info
->print_address_func (pc
+ 4 + offset
, info
);
9979 unsigned int immA
= (given
& 0x00010000u
) >> 16;
9980 unsigned int immB
= (given
& 0x000007feu
) >> 1;
9981 unsigned int immC
= (given
& 0x00000800u
) >> 11;
9984 offset
|= immA
<< 12;
9985 offset
|= immB
<< 2;
9986 offset
|= immC
<< 1;
9988 offset
= (offset
& 0x1000) ? offset
- (1 << 13) : offset
;
9990 info
->print_address_func (pc
+ 4 + offset
, info
);
9992 unsigned int T
= (given
& 0x00020000u
) >> 17;
9993 unsigned int endoffset
= (((given
& 0x07800000) >> 23) << 1);
9994 unsigned int boffset
= (T
== 1) ? 4 : 2;
9995 func (stream
, ", ");
9996 func (stream
, "%x", endoffset
+ boffset
);
10002 unsigned int immh
= (given
& 0x000007feu
) >> 1;
10003 unsigned int imml
= (given
& 0x00000800u
) >> 11;
10006 imm32
|= immh
<< 2;
10007 imm32
|= imml
<< 1;
10009 info
->print_address_func (pc
+ 4 + imm32
, info
);
10015 unsigned int immh
= (given
& 0x000007feu
) >> 1;
10016 unsigned int imml
= (given
& 0x00000800u
) >> 11;
10019 imm32
|= immh
<< 2;
10020 imm32
|= imml
<< 1;
10022 info
->print_address_func (pc
+ 4 - imm32
, info
);
10028 unsigned int S
= (given
& 0x04000000u
) >> 26;
10029 unsigned int J1
= (given
& 0x00002000u
) >> 13;
10030 unsigned int J2
= (given
& 0x00000800u
) >> 11;
10031 bfd_vma offset
= 0;
10033 offset
|= !S
<< 20;
10034 offset
|= J2
<< 19;
10035 offset
|= J1
<< 18;
10036 offset
|= (given
& 0x003f0000) >> 4;
10037 offset
|= (given
& 0x000007ff) << 1;
10038 offset
-= (1 << 20);
10040 info
->print_address_func (pc
+ 4 + offset
, info
);
10046 unsigned int S
= (given
& 0x04000000u
) >> 26;
10047 unsigned int I1
= (given
& 0x00002000u
) >> 13;
10048 unsigned int I2
= (given
& 0x00000800u
) >> 11;
10049 bfd_vma offset
= 0;
10051 offset
|= !S
<< 24;
10052 offset
|= !(I1
^ S
) << 23;
10053 offset
|= !(I2
^ S
) << 22;
10054 offset
|= (given
& 0x03ff0000u
) >> 4;
10055 offset
|= (given
& 0x000007ffu
) << 1;
10056 offset
-= (1 << 24);
10059 /* BLX target addresses are always word aligned. */
10060 if ((given
& 0x00001000u
) == 0)
10063 info
->print_address_func (offset
, info
);
10069 unsigned int shift
= 0;
10071 shift
|= (given
& 0x000000c0u
) >> 6;
10072 shift
|= (given
& 0x00007000u
) >> 10;
10073 if (WRITEBACK_BIT_SET
)
10074 func (stream
, ", asr #%u", shift
);
10076 func (stream
, ", lsl #%u", shift
);
10077 /* else print nothing - lsl #0 */
10083 unsigned int rot
= (given
& 0x00000030) >> 4;
10086 func (stream
, ", ror #%u", rot
* 8);
10091 if ((given
& 0xf0) == 0x60)
10093 switch (given
& 0xf)
10095 case 0xf: func (stream
, "sy"); break;
10097 func (stream
, "#%d", (int) given
& 0xf);
10103 const char * opt
= data_barrier_option (given
& 0xf);
10105 func (stream
, "%s", opt
);
10107 func (stream
, "#%d", (int) given
& 0xf);
10112 if ((given
& 0xff) == 0)
10114 func (stream
, "%cPSR_", (given
& 0x100000) ? 'S' : 'C');
10116 func (stream
, "f");
10118 func (stream
, "s");
10120 func (stream
, "x");
10122 func (stream
, "c");
10124 else if ((given
& 0x20) == 0x20)
10127 unsigned sysm
= (given
& 0xf00) >> 8;
10129 sysm
|= (given
& 0x30);
10130 sysm
|= (given
& 0x00100000) >> 14;
10131 name
= banked_regname (sysm
);
10134 func (stream
, "%s", name
);
10136 func (stream
, "(UNDEF: %lu)", (unsigned long) sysm
);
10140 func (stream
, "%s", psr_name (given
& 0xff));
10145 if (((given
& 0xff) == 0)
10146 || ((given
& 0x20) == 0x20))
10149 unsigned sm
= (given
& 0xf0000) >> 16;
10151 sm
|= (given
& 0x30);
10152 sm
|= (given
& 0x00100000) >> 14;
10153 name
= banked_regname (sm
);
10156 func (stream
, "%s", name
);
10158 func (stream
, "(UNDEF: %lu)", (unsigned long) sm
);
10161 func (stream
, "%s", psr_name (given
& 0xff));
10164 case '0': case '1': case '2': case '3': case '4':
10165 case '5': case '6': case '7': case '8': case '9':
10170 c
= arm_decode_bitfield (c
, given
, &val
, &width
);
10175 func (stream
, "%lu", val
);
10176 value_in_comment
= val
;
10180 func (stream
, "%lu", val
+ 1);
10181 value_in_comment
= val
+ 1;
10185 func (stream
, "%lu", val
* 4);
10186 value_in_comment
= val
* 4;
10191 is_unpredictable
= TRUE
;
10192 /* Fall through. */
10195 is_unpredictable
= TRUE
;
10196 /* Fall through. */
10198 func (stream
, "%s", arm_regnames
[val
]);
10202 func (stream
, "%s", arm_conditional
[val
]);
10207 if (val
== ((1ul << width
) - 1))
10208 func (stream
, "%c", *c
);
10214 func (stream
, "%c", *c
);
10218 func (stream
, "%c", c
[(1 << width
) - (int) val
]);
10223 func (stream
, "0x%lx", val
& 0xffffffffUL
);
10233 /* PR binutils/12534
10234 If we have a PC relative offset in an LDRD or STRD
10235 instructions then display the decoded address. */
10236 if (((given
>> 16) & 0xf) == 0xf)
10238 bfd_vma offset
= (given
& 0xff) * 4;
10240 if ((given
& (1 << 23)) == 0)
10242 func (stream
, "\t; ");
10243 info
->print_address_func ((pc
& ~3) + 4 + offset
, info
);
10252 if (value_in_comment
> 32 || value_in_comment
< -16)
10253 func (stream
, "\t; 0x%lx", value_in_comment
);
10255 if (is_unpredictable
)
10256 func (stream
, UNPREDICTABLE_INSTRUCTION
);
10262 func (stream
, UNKNOWN_INSTRUCTION_32BIT
, (unsigned)given
);
10266 /* Print data bytes on INFO->STREAM. */
10269 print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED
,
10270 struct disassemble_info
*info
,
10273 switch (info
->bytes_per_chunk
)
10276 info
->fprintf_func (info
->stream
, ".byte\t0x%02lx", given
);
10279 info
->fprintf_func (info
->stream
, ".short\t0x%04lx", given
);
10282 info
->fprintf_func (info
->stream
, ".word\t0x%08lx", given
);
10289 /* Disallow mapping symbols ($a, $b, $d, $t etc) from
10290 being displayed in symbol relative addresses.
10292 Also disallow private symbol, with __tagsym$$ prefix,
10293 from ARM RVCT toolchain being displayed. */
10296 arm_symbol_is_valid (asymbol
* sym
,
10297 struct disassemble_info
* info ATTRIBUTE_UNUSED
)
10304 name
= bfd_asymbol_name (sym
);
10306 return (name
&& *name
!= '$' && strncmp (name
, "__tagsym$$", 10));
10309 /* Parse the string of disassembler options. */
10312 parse_arm_disassembler_options (const char *options
)
10316 FOR_EACH_DISASSEMBLER_OPTION (opt
, options
)
10318 if (CONST_STRNEQ (opt
, "reg-names-"))
10321 for (i
= 0; i
< NUM_ARM_OPTIONS
; i
++)
10322 if (disassembler_options_cmp (opt
, regnames
[i
].name
) == 0)
10324 regname_selected
= i
;
10328 if (i
>= NUM_ARM_OPTIONS
)
10329 /* xgettext: c-format */
10330 opcodes_error_handler (_("unrecognised register name set: %s"),
10333 else if (CONST_STRNEQ (opt
, "force-thumb"))
10335 else if (CONST_STRNEQ (opt
, "no-force-thumb"))
10338 /* xgettext: c-format */
10339 opcodes_error_handler (_("unrecognised disassembler option: %s"), opt
);
10346 mapping_symbol_for_insn (bfd_vma pc
, struct disassemble_info
*info
,
10347 enum map_type
*map_symbol
);
10349 /* Search back through the insn stream to determine if this instruction is
10350 conditionally executed. */
10353 find_ifthen_state (bfd_vma pc
,
10354 struct disassemble_info
*info
,
10355 bfd_boolean little
)
10357 unsigned char b
[2];
10360 /* COUNT is twice the number of instructions seen. It will be odd if we
10361 just crossed an instruction boundary. */
10364 unsigned int seen_it
;
10367 ifthen_address
= pc
;
10374 /* Scan backwards looking for IT instructions, keeping track of where
10375 instruction boundaries are. We don't know if something is actually an
10376 IT instruction until we find a definite instruction boundary. */
10379 if (addr
== 0 || info
->symbol_at_address_func (addr
, info
))
10381 /* A symbol must be on an instruction boundary, and will not
10382 be within an IT block. */
10383 if (seen_it
&& (count
& 1))
10389 status
= info
->read_memory_func (addr
, (bfd_byte
*) b
, 2, info
);
10394 insn
= (b
[0]) | (b
[1] << 8);
10396 insn
= (b
[1]) | (b
[0] << 8);
10399 if ((insn
& 0xf800) < 0xe800)
10401 /* Addr + 2 is an instruction boundary. See if this matches
10402 the expected boundary based on the position of the last
10409 if ((insn
& 0xff00) == 0xbf00 && (insn
& 0xf) != 0)
10411 enum map_type type
= MAP_ARM
;
10412 bfd_boolean found
= mapping_symbol_for_insn (addr
, info
, &type
);
10414 if (!found
|| (found
&& type
== MAP_THUMB
))
10416 /* This could be an IT instruction. */
10418 it_count
= count
>> 1;
10421 if ((insn
& 0xf800) >= 0xe800)
10424 count
= (count
+ 2) | 1;
10425 /* IT blocks contain at most 4 instructions. */
10426 if (count
>= 8 && !seen_it
)
10429 /* We found an IT instruction. */
10430 ifthen_state
= (seen_it
& 0xe0) | ((seen_it
<< it_count
) & 0x1f);
10431 if ((ifthen_state
& 0xf) == 0)
10435 /* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
10439 is_mapping_symbol (struct disassemble_info
*info
, int n
,
10440 enum map_type
*map_type
)
10444 name
= bfd_asymbol_name (info
->symtab
[n
]);
10445 if (name
[0] == '$' && (name
[1] == 'a' || name
[1] == 't' || name
[1] == 'd')
10446 && (name
[2] == 0 || name
[2] == '.'))
10448 *map_type
= ((name
[1] == 'a') ? MAP_ARM
10449 : (name
[1] == 't') ? MAP_THUMB
10457 /* Try to infer the code type (ARM or Thumb) from a mapping symbol.
10458 Returns nonzero if *MAP_TYPE was set. */
10461 get_map_sym_type (struct disassemble_info
*info
,
10463 enum map_type
*map_type
)
10465 /* If the symbol is in a different section, ignore it. */
10466 if (info
->section
!= NULL
&& info
->section
!= info
->symtab
[n
]->section
)
10469 return is_mapping_symbol (info
, n
, map_type
);
10472 /* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
10473 Returns nonzero if *MAP_TYPE was set. */
10476 get_sym_code_type (struct disassemble_info
*info
,
10478 enum map_type
*map_type
)
10480 elf_symbol_type
*es
;
10483 /* If the symbol is in a different section, ignore it. */
10484 if (info
->section
!= NULL
&& info
->section
!= info
->symtab
[n
]->section
)
10487 es
= *(elf_symbol_type
**)(info
->symtab
+ n
);
10488 type
= ELF_ST_TYPE (es
->internal_elf_sym
.st_info
);
10490 /* If the symbol has function type then use that. */
10491 if (type
== STT_FUNC
|| type
== STT_GNU_IFUNC
)
10493 if (ARM_GET_SYM_BRANCH_TYPE (es
->internal_elf_sym
.st_target_internal
)
10494 == ST_BRANCH_TO_THUMB
)
10495 *map_type
= MAP_THUMB
;
10497 *map_type
= MAP_ARM
;
10504 /* Search the mapping symbol state for instruction at pc. This is only
10505 applicable for elf target.
10507 There is an assumption Here, info->private_data contains the correct AND
10508 up-to-date information about current scan process. The information will be
10509 used to speed this search process.
10511 Return TRUE if the mapping state can be determined, and map_symbol
10512 will be updated accordingly. Otherwise, return FALSE. */
10515 mapping_symbol_for_insn (bfd_vma pc
, struct disassemble_info
*info
,
10516 enum map_type
*map_symbol
)
10518 bfd_vma addr
, section_vma
= 0;
10519 int n
, last_sym
= -1;
10520 bfd_boolean found
= FALSE
;
10521 bfd_boolean can_use_search_opt_p
= FALSE
;
10523 /* Default to DATA. A text section is required by the ABI to contain an
10524 INSN mapping symbol at the start. A data section has no such
10525 requirement, hence if no mapping symbol is found the section must
10526 contain only data. This however isn't very useful if the user has
10527 fully stripped the binaries. If this is the case use the section
10528 attributes to determine the default. If we have no section default to
10529 INSN as well, as we may be disassembling some raw bytes on a baremetal
10530 HEX file or similar. */
10531 enum map_type type
= MAP_DATA
;
10532 if ((info
->section
&& info
->section
->flags
& SEC_CODE
) || !info
->section
)
10534 struct arm_private_data
*private_data
;
10536 if (info
->private_data
== NULL
10537 || bfd_asymbol_flavour (*info
->symtab
) != bfd_target_elf_flavour
)
10540 private_data
= info
->private_data
;
10542 /* First, look for mapping symbols. */
10543 if (info
->symtab_size
!= 0)
10545 if (pc
<= private_data
->last_mapping_addr
)
10546 private_data
->last_mapping_sym
= -1;
10548 /* Start scanning at the start of the function, or wherever
10549 we finished last time. */
10550 n
= info
->symtab_pos
+ 1;
10552 /* If the last stop offset is different from the current one it means we
10553 are disassembling a different glob of bytes. As such the optimization
10554 would not be safe and we should start over. */
10555 can_use_search_opt_p
10556 = private_data
->last_mapping_sym
>= 0
10557 && info
->stop_offset
== private_data
->last_stop_offset
;
10559 if (n
>= private_data
->last_mapping_sym
&& can_use_search_opt_p
)
10560 n
= private_data
->last_mapping_sym
;
10562 /* Look down while we haven't passed the location being disassembled.
10563 The reason for this is that there's no defined order between a symbol
10564 and an mapping symbol that may be at the same address. We may have to
10565 look at least one position ahead. */
10566 for (; n
< info
->symtab_size
; n
++)
10568 addr
= bfd_asymbol_value (info
->symtab
[n
]);
10571 if (get_map_sym_type (info
, n
, &type
))
10580 n
= info
->symtab_pos
;
10581 if (n
>= private_data
->last_mapping_sym
&& can_use_search_opt_p
)
10582 n
= private_data
->last_mapping_sym
;
10584 /* No mapping symbol found at this address. Look backwards
10585 for a preceeding one, but don't go pass the section start
10586 otherwise a data section with no mapping symbol can pick up
10587 a text mapping symbol of a preceeding section. The documentation
10588 says section can be NULL, in which case we will seek up all the
10591 section_vma
= info
->section
->vma
;
10593 for (; n
>= 0; n
--)
10595 addr
= bfd_asymbol_value (info
->symtab
[n
]);
10596 if (addr
< section_vma
)
10599 if (get_map_sym_type (info
, n
, &type
))
10609 /* If no mapping symbol was found, try looking up without a mapping
10610 symbol. This is done by walking up from the current PC to the nearest
10611 symbol. We don't actually have to loop here since symtab_pos will
10612 contain the nearest symbol already. */
10615 n
= info
->symtab_pos
;
10616 if (n
>= 0 && get_sym_code_type (info
, n
, &type
))
10623 private_data
->last_mapping_sym
= last_sym
;
10624 private_data
->last_type
= type
;
10625 private_data
->last_stop_offset
= info
->stop_offset
;
10627 *map_symbol
= type
;
10631 /* Given a bfd_mach_arm_XXX value, this function fills in the fields
10632 of the supplied arm_feature_set structure with bitmasks indicating
10633 the supported base architectures and coprocessor extensions.
10635 FIXME: This could more efficiently implemented as a constant array,
10636 although it would also be less robust. */
10639 select_arm_features (unsigned long mach
,
10640 arm_feature_set
* features
)
10642 arm_feature_set arch_fset
;
10643 const arm_feature_set fpu_any
= FPU_ANY
;
10645 #undef ARM_SET_FEATURES
10646 #define ARM_SET_FEATURES(FSET) \
10648 const arm_feature_set fset = FSET; \
10649 arch_fset = fset; \
10652 /* When several architecture versions share the same bfd_mach_arm_XXX value
10653 the most featureful is chosen. */
10656 case bfd_mach_arm_2
: ARM_SET_FEATURES (ARM_ARCH_V2
); break;
10657 case bfd_mach_arm_2a
: ARM_SET_FEATURES (ARM_ARCH_V2S
); break;
10658 case bfd_mach_arm_3
: ARM_SET_FEATURES (ARM_ARCH_V3
); break;
10659 case bfd_mach_arm_3M
: ARM_SET_FEATURES (ARM_ARCH_V3M
); break;
10660 case bfd_mach_arm_4
: ARM_SET_FEATURES (ARM_ARCH_V4
); break;
10661 case bfd_mach_arm_4T
: ARM_SET_FEATURES (ARM_ARCH_V4T
); break;
10662 case bfd_mach_arm_5
: ARM_SET_FEATURES (ARM_ARCH_V5
); break;
10663 case bfd_mach_arm_5T
: ARM_SET_FEATURES (ARM_ARCH_V5T
); break;
10664 case bfd_mach_arm_5TE
: ARM_SET_FEATURES (ARM_ARCH_V5TE
); break;
10665 case bfd_mach_arm_XScale
: ARM_SET_FEATURES (ARM_ARCH_XSCALE
); break;
10666 case bfd_mach_arm_ep9312
:
10667 ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T
,
10668 ARM_CEXT_MAVERICK
| FPU_MAVERICK
));
10670 case bfd_mach_arm_iWMMXt
: ARM_SET_FEATURES (ARM_ARCH_IWMMXT
); break;
10671 case bfd_mach_arm_iWMMXt2
: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2
); break;
10672 case bfd_mach_arm_5TEJ
: ARM_SET_FEATURES (ARM_ARCH_V5TEJ
); break;
10673 case bfd_mach_arm_6
: ARM_SET_FEATURES (ARM_ARCH_V6
); break;
10674 case bfd_mach_arm_6KZ
: ARM_SET_FEATURES (ARM_ARCH_V6KZ
); break;
10675 case bfd_mach_arm_6T2
: ARM_SET_FEATURES (ARM_ARCH_V6KZT2
); break;
10676 case bfd_mach_arm_6K
: ARM_SET_FEATURES (ARM_ARCH_V6K
); break;
10677 case bfd_mach_arm_7
: ARM_SET_FEATURES (ARM_ARCH_V7VE
); break;
10678 case bfd_mach_arm_6M
: ARM_SET_FEATURES (ARM_ARCH_V6M
); break;
10679 case bfd_mach_arm_6SM
: ARM_SET_FEATURES (ARM_ARCH_V6SM
); break;
10680 case bfd_mach_arm_7EM
: ARM_SET_FEATURES (ARM_ARCH_V7EM
); break;
10681 case bfd_mach_arm_8
:
10683 /* Add bits for extensions that Armv8.5-A recognizes. */
10684 arm_feature_set armv8_5_ext_fset
10685 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
10686 ARM_SET_FEATURES (ARM_ARCH_V8_5A
);
10687 ARM_MERGE_FEATURE_SETS (arch_fset
, arch_fset
, armv8_5_ext_fset
);
10690 case bfd_mach_arm_8R
: ARM_SET_FEATURES (ARM_ARCH_V8R
); break;
10691 case bfd_mach_arm_8M_BASE
: ARM_SET_FEATURES (ARM_ARCH_V8M_BASE
); break;
10692 case bfd_mach_arm_8M_MAIN
: ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN
); break;
10693 case bfd_mach_arm_8_1M_MAIN
:
10694 ARM_SET_FEATURES (ARM_ARCH_V8_1M_MAIN
);
10697 /* If the machine type is unknown allow all architecture types and all
10699 case bfd_mach_arm_unknown
: ARM_SET_FEATURES (ARM_FEATURE_ALL
); break;
10703 #undef ARM_SET_FEATURES
10705 /* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch
10706 and thus on bfd_mach_arm_XXX value. Therefore for a given
10707 bfd_mach_arm_XXX value all coprocessor feature bits should be allowed. */
10708 ARM_MERGE_FEATURE_SETS (*features
, arch_fset
, fpu_any
);
10712 /* NOTE: There are no checks in these routines that
10713 the relevant number of data bytes exist. */
10716 print_insn (bfd_vma pc
, struct disassemble_info
*info
, bfd_boolean little
)
10718 unsigned char b
[4];
10721 int is_thumb
= FALSE
;
10722 int is_data
= FALSE
;
10724 unsigned int size
= 4;
10725 void (*printer
) (bfd_vma
, struct disassemble_info
*, long);
10726 bfd_boolean found
= FALSE
;
10727 struct arm_private_data
*private_data
;
10729 if (info
->disassembler_options
)
10731 parse_arm_disassembler_options (info
->disassembler_options
);
10733 /* To avoid repeated parsing of these options, we remove them here. */
10734 info
->disassembler_options
= NULL
;
10737 /* PR 10288: Control which instructions will be disassembled. */
10738 if (info
->private_data
== NULL
)
10740 static struct arm_private_data
private;
10742 if ((info
->flags
& USER_SPECIFIED_MACHINE_TYPE
) == 0)
10743 /* If the user did not use the -m command line switch then default to
10744 disassembling all types of ARM instruction.
10746 The info->mach value has to be ignored as this will be based on
10747 the default archictecture for the target and/or hints in the notes
10748 section, but it will never be greater than the current largest arm
10749 machine value (iWMMXt2), which is only equivalent to the V5TE
10750 architecture. ARM architectures have advanced beyond the machine
10751 value encoding, and these newer architectures would be ignored if
10752 the machine value was used.
10754 Ie the -m switch is used to restrict which instructions will be
10755 disassembled. If it is necessary to use the -m switch to tell
10756 objdump that an ARM binary is being disassembled, eg because the
10757 input is a raw binary file, but it is also desired to disassemble
10758 all ARM instructions then use "-marm". This will select the
10759 "unknown" arm architecture which is compatible with any ARM
10761 info
->mach
= bfd_mach_arm_unknown
;
10763 /* Compute the architecture bitmask from the machine number.
10764 Note: This assumes that the machine number will not change
10765 during disassembly.... */
10766 select_arm_features (info
->mach
, & private.features
);
10768 private.last_mapping_sym
= -1;
10769 private.last_mapping_addr
= 0;
10770 private.last_stop_offset
= 0;
10772 info
->private_data
= & private;
10775 private_data
= info
->private_data
;
10777 /* Decide if our code is going to be little-endian, despite what the
10778 function argument might say. */
10779 little_code
= ((info
->endian_code
== BFD_ENDIAN_LITTLE
) || little
);
10781 /* For ELF, consult the symbol table to determine what kind of code
10782 or data we have. */
10783 if (info
->symtab_size
!= 0
10784 && bfd_asymbol_flavour (*info
->symtab
) == bfd_target_elf_flavour
)
10789 enum map_type type
= MAP_ARM
;
10791 found
= mapping_symbol_for_insn (pc
, info
, &type
);
10792 last_sym
= private_data
->last_mapping_sym
;
10794 is_thumb
= (private_data
->last_type
== MAP_THUMB
);
10795 is_data
= (private_data
->last_type
== MAP_DATA
);
10797 /* Look a little bit ahead to see if we should print out
10798 two or four bytes of data. If there's a symbol,
10799 mapping or otherwise, after two bytes then don't
10803 size
= 4 - (pc
& 3);
10804 for (n
= last_sym
+ 1; n
< info
->symtab_size
; n
++)
10806 addr
= bfd_asymbol_value (info
->symtab
[n
]);
10808 && (info
->section
== NULL
10809 || info
->section
== info
->symtab
[n
]->section
))
10811 if (addr
- pc
< size
)
10816 /* If the next symbol is after three bytes, we need to
10817 print only part of the data, so that we can use either
10818 .byte or .short. */
10820 size
= (pc
& 1) ? 1 : 2;
10824 if (info
->symbols
!= NULL
)
10826 if (bfd_asymbol_flavour (*info
->symbols
) == bfd_target_coff_flavour
)
10828 coff_symbol_type
* cs
;
10830 cs
= coffsymbol (*info
->symbols
);
10831 is_thumb
= ( cs
->native
->u
.syment
.n_sclass
== C_THUMBEXT
10832 || cs
->native
->u
.syment
.n_sclass
== C_THUMBSTAT
10833 || cs
->native
->u
.syment
.n_sclass
== C_THUMBLABEL
10834 || cs
->native
->u
.syment
.n_sclass
== C_THUMBEXTFUNC
10835 || cs
->native
->u
.syment
.n_sclass
== C_THUMBSTATFUNC
);
10837 else if (bfd_asymbol_flavour (*info
->symbols
) == bfd_target_elf_flavour
10840 /* If no mapping symbol has been found then fall back to the type
10841 of the function symbol. */
10842 elf_symbol_type
* es
;
10845 es
= *(elf_symbol_type
**)(info
->symbols
);
10846 type
= ELF_ST_TYPE (es
->internal_elf_sym
.st_info
);
10849 ((ARM_GET_SYM_BRANCH_TYPE (es
->internal_elf_sym
.st_target_internal
)
10850 == ST_BRANCH_TO_THUMB
) || type
== STT_ARM_16BIT
);
10852 else if (bfd_asymbol_flavour (*info
->symbols
)
10853 == bfd_target_mach_o_flavour
)
10855 bfd_mach_o_asymbol
*asym
= (bfd_mach_o_asymbol
*)*info
->symbols
;
10857 is_thumb
= (asym
->n_desc
& BFD_MACH_O_N_ARM_THUMB_DEF
);
10865 info
->display_endian
= little
? BFD_ENDIAN_LITTLE
: BFD_ENDIAN_BIG
;
10867 info
->display_endian
= little_code
? BFD_ENDIAN_LITTLE
: BFD_ENDIAN_BIG
;
10869 info
->bytes_per_line
= 4;
10871 /* PR 10263: Disassemble data if requested to do so by the user. */
10872 if (is_data
&& ((info
->flags
& DISASSEMBLE_DATA
) == 0))
10876 /* Size was already set above. */
10877 info
->bytes_per_chunk
= size
;
10878 printer
= print_insn_data
;
10880 status
= info
->read_memory_func (pc
, (bfd_byte
*) b
, size
, info
);
10883 for (i
= size
- 1; i
>= 0; i
--)
10884 given
= b
[i
] | (given
<< 8);
10886 for (i
= 0; i
< (int) size
; i
++)
10887 given
= b
[i
] | (given
<< 8);
10889 else if (!is_thumb
)
10891 /* In ARM mode endianness is a straightforward issue: the instruction
10892 is four bytes long and is either ordered 0123 or 3210. */
10893 printer
= print_insn_arm
;
10894 info
->bytes_per_chunk
= 4;
10897 status
= info
->read_memory_func (pc
, (bfd_byte
*) b
, 4, info
);
10899 given
= (b
[0]) | (b
[1] << 8) | (b
[2] << 16) | (b
[3] << 24);
10901 given
= (b
[3]) | (b
[2] << 8) | (b
[1] << 16) | (b
[0] << 24);
10905 /* In Thumb mode we have the additional wrinkle of two
10906 instruction lengths. Fortunately, the bits that determine
10907 the length of the current instruction are always to be found
10908 in the first two bytes. */
10909 printer
= print_insn_thumb16
;
10910 info
->bytes_per_chunk
= 2;
10913 status
= info
->read_memory_func (pc
, (bfd_byte
*) b
, 2, info
);
10915 given
= (b
[0]) | (b
[1] << 8);
10917 given
= (b
[1]) | (b
[0] << 8);
10921 /* These bit patterns signal a four-byte Thumb
10923 if ((given
& 0xF800) == 0xF800
10924 || (given
& 0xF800) == 0xF000
10925 || (given
& 0xF800) == 0xE800)
10927 status
= info
->read_memory_func (pc
+ 2, (bfd_byte
*) b
, 2, info
);
10929 given
= (b
[0]) | (b
[1] << 8) | (given
<< 16);
10931 given
= (b
[1]) | (b
[0] << 8) | (given
<< 16);
10933 printer
= print_insn_thumb32
;
10938 if (ifthen_address
!= pc
)
10939 find_ifthen_state (pc
, info
, little_code
);
10943 if ((ifthen_state
& 0xf) == 0x8)
10944 ifthen_next_state
= 0;
10946 ifthen_next_state
= (ifthen_state
& 0xe0)
10947 | ((ifthen_state
& 0xf) << 1);
10953 info
->memory_error_func (status
, pc
, info
);
10956 if (info
->flags
& INSN_HAS_RELOC
)
10957 /* If the instruction has a reloc associated with it, then
10958 the offset field in the instruction will actually be the
10959 addend for the reloc. (We are using REL type relocs).
10960 In such cases, we can ignore the pc when computing
10961 addresses, since the addend is not currently pc-relative. */
10964 printer (pc
, info
, given
);
10968 ifthen_state
= ifthen_next_state
;
10969 ifthen_address
+= size
;
10975 print_insn_big_arm (bfd_vma pc
, struct disassemble_info
*info
)
10977 /* Detect BE8-ness and record it in the disassembler info. */
10978 if (info
->flavour
== bfd_target_elf_flavour
10979 && info
->section
!= NULL
10980 && (elf_elfheader (info
->section
->owner
)->e_flags
& EF_ARM_BE8
))
10981 info
->endian_code
= BFD_ENDIAN_LITTLE
;
10983 return print_insn (pc
, info
, FALSE
);
10987 print_insn_little_arm (bfd_vma pc
, struct disassemble_info
*info
)
10989 return print_insn (pc
, info
, TRUE
);
10992 const disasm_options_and_args_t
*
10993 disassembler_options_arm (void)
10995 static disasm_options_and_args_t
*opts_and_args
;
10997 if (opts_and_args
== NULL
)
10999 disasm_options_t
*opts
;
11002 opts_and_args
= XNEW (disasm_options_and_args_t
);
11003 opts_and_args
->args
= NULL
;
11005 opts
= &opts_and_args
->options
;
11006 opts
->name
= XNEWVEC (const char *, NUM_ARM_OPTIONS
+ 1);
11007 opts
->description
= XNEWVEC (const char *, NUM_ARM_OPTIONS
+ 1);
11009 for (i
= 0; i
< NUM_ARM_OPTIONS
; i
++)
11011 opts
->name
[i
] = regnames
[i
].name
;
11012 if (regnames
[i
].description
!= NULL
)
11013 opts
->description
[i
] = _(regnames
[i
].description
);
11015 opts
->description
[i
] = NULL
;
11017 /* The array we return must be NULL terminated. */
11018 opts
->name
[i
] = NULL
;
11019 opts
->description
[i
] = NULL
;
11022 return opts_and_args
;
11026 print_arm_disassembler_options (FILE *stream
)
11028 unsigned int i
, max_len
= 0;
11029 fprintf (stream
, _("\n\
11030 The following ARM specific disassembler options are supported for use with\n\
11031 the -M switch:\n"));
11033 for (i
= 0; i
< NUM_ARM_OPTIONS
; i
++)
11035 unsigned int len
= strlen (regnames
[i
].name
);
11040 for (i
= 0, max_len
++; i
< NUM_ARM_OPTIONS
; i
++)
11041 fprintf (stream
, " %s%*c %s\n",
11043 (int)(max_len
- strlen (regnames
[i
].name
)), ' ',
11044 _(regnames
[i
].description
));