1 /* Instruction printing code for the ARM
2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
6 This file is part of libopcodes.
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
26 #include "disassemble.h"
27 #include "opcode/arm.h"
29 #include "safe-ctype.h"
30 #include "libiberty.h"
31 #include "floatformat.h"
33 /* FIXME: This shouldn't be done here. */
34 #include "coff/internal.h"
38 #include "elf/internal.h"
42 /* FIXME: Belongs in global header. */
44 #define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
47 /* Cached mapping symbol state. */
55 struct arm_private_data
57 /* The features to use when disassembling optional instructions. */
58 arm_feature_set features
;
60 /* Track the last type (although this doesn't seem to be useful) */
61 enum map_type last_type
;
63 /* Tracking symbol table information */
66 /* The end range of the current range being disassembled. */
67 bfd_vma last_stop_offset
;
68 bfd_vma last_mapping_addr
;
121 MVE_VSTRB_SCATTER_T1
,
122 MVE_VSTRH_SCATTER_T2
,
123 MVE_VSTRW_SCATTER_T3
,
124 MVE_VSTRD_SCATTER_T4
,
125 MVE_VSTRW_SCATTER_T5
,
126 MVE_VSTRD_SCATTER_T6
,
128 MVE_VCVT_BETWEEN_FP_INT
,
130 MVE_VCVT_FROM_FP_TO_INT
,
133 MVE_VMOV_GP_TO_VEC_LANE
,
136 MVE_VMOV2_VEC_LANE_TO_GP
,
137 MVE_VMOV2_GP_TO_VEC_LANE
,
138 MVE_VMOV_VEC_LANE_TO_GP
,
229 enum mve_unpredictable
231 UNPRED_IT_BLOCK
, /* Unpredictable because mve insn in it block.
233 UNPRED_FCA_0_FCB_1
, /* Unpredictable because fcA = 0 and
235 UNPRED_R13
, /* Unpredictable because r13 (sp) or
237 UNPRED_R15
, /* Unpredictable because r15 (pc) is used. */
238 UNPRED_Q_GT_4
, /* Unpredictable because
239 vec reg start > 4 (vld4/st4). */
240 UNPRED_Q_GT_6
, /* Unpredictable because
241 vec reg start > 6 (vld2/st2). */
242 UNPRED_R13_AND_WB
, /* Unpredictable becase gp reg = r13
244 UNPRED_Q_REGS_EQUAL
, /* Unpredictable because vector registers are
246 UNPRED_OS
, /* Unpredictable because offset scaled == 1. */
247 UNPRED_GP_REGS_EQUAL
, /* Unpredictable because gp registers are the
249 UNPRED_Q_REGS_EQ_AND_SIZE_1
, /* Unpredictable because q regs equal and
251 UNPRED_Q_REGS_EQ_AND_SIZE_2
, /* Unpredictable because q regs equal and
253 UNPRED_NONE
/* No unpredictable behavior. */
258 UNDEF_SIZE
, /* undefined size. */
259 UNDEF_SIZE_0
, /* undefined because size == 0. */
260 UNDEF_SIZE_2
, /* undefined because size == 2. */
261 UNDEF_SIZE_3
, /* undefined because size == 3. */
262 UNDEF_SIZE_LE_1
, /* undefined because size <= 1. */
263 UNDEF_SIZE_NOT_2
, /* undefined because size != 2. */
264 UNDEF_SIZE_NOT_3
, /* undefined because size != 3. */
265 UNDEF_NOT_UNS_SIZE_0
, /* undefined because U == 0 and
267 UNDEF_NOT_UNS_SIZE_1
, /* undefined because U == 0 and
269 UNDEF_NOT_UNSIGNED
, /* undefined because U == 0. */
270 UNDEF_VCVT_IMM6
, /* imm6 < 32. */
271 UNDEF_VCVT_FSI_IMM6
, /* fsi = 0 and 32 >= imm6 <= 47. */
272 UNDEF_BAD_OP1_OP2
, /* undefined with op2 = 2 and
274 UNDEF_BAD_U_OP1_OP2
, /* undefined with U = 1 and
275 op2 == 0 and op1 == (0 or 1). */
276 UNDEF_OP_0_BAD_CMODE
, /* undefined because op == 0 and cmode
278 UNDEF_XCHG_UNS
, /* undefined because X == 1 and U == 1. */
279 UNDEF_NONE
/* no undefined behavior. */
284 arm_feature_set arch
; /* Architecture defining this insn. */
285 unsigned long value
; /* If arch is 0 then value is a sentinel. */
286 unsigned long mask
; /* Recognise insn if (op & mask) == value. */
287 const char * assembler
; /* How to disassemble this insn. */
294 arm_feature_set arch
; /* Architecture defining this insn. */
295 enum mve_instructions mve_op
; /* Specific mve instruction for faster
297 unsigned long value
; /* If arch is 0 then value is a sentinel. */
298 unsigned long mask
; /* Recognise insn if (op & mask) == value. */
299 const char * assembler
; /* How to disassemble this insn. */
309 /* Shared (between Arm and Thumb mode) opcode. */
312 enum isa isa
; /* Execution mode instruction availability. */
313 arm_feature_set arch
; /* Architecture defining this insn. */
314 unsigned long value
; /* If arch is 0 then value is a sentinel. */
315 unsigned long mask
; /* Recognise insn if (op & mask) == value. */
316 const char * assembler
; /* How to disassemble this insn. */
321 arm_feature_set arch
; /* Architecture defining this insn. */
322 unsigned short value
, mask
; /* Recognise insn if (op & mask) == value. */
323 const char *assembler
; /* How to disassemble this insn. */
326 /* print_insn_coprocessor recognizes the following format control codes:
330 %c print condition code (always bits 28-31 in ARM mode)
331 %q print shifter argument
332 %u print condition code (unconditional in ARM mode,
333 UNPREDICTABLE if not AL in Thumb)
334 %A print address for ldc/stc/ldf/stf instruction
335 %B print vstm/vldm register list
336 %C print vscclrm register list
337 %I print cirrus signed shift immediate: bits 0..3|4..6
338 %J print register for VLDR instruction
339 %K print address for VLDR instruction
340 %F print the COUNT field of a LFM/SFM instruction.
341 %P print floating point precision in arithmetic insn
342 %Q print floating point precision in ldf/stf insn
343 %R print floating point rounding mode
345 %<bitfield>c print as a condition code (for vsel)
346 %<bitfield>r print as an ARM register
347 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
348 %<bitfield>ru as %<>r but each u register must be unique.
349 %<bitfield>d print the bitfield in decimal
350 %<bitfield>k print immediate for VFPv3 conversion instruction
351 %<bitfield>x print the bitfield in hex
352 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
353 %<bitfield>f print a floating point constant if >7 else a
354 floating point register
355 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
356 %<bitfield>g print as an iWMMXt 64-bit register
357 %<bitfield>G print as an iWMMXt general purpose or control register
358 %<bitfield>D print as a NEON D register
359 %<bitfield>Q print as a NEON Q register
360 %<bitfield>V print as a NEON D or Q register
361 %<bitfield>E print a quarter-float immediate value
363 %y<code> print a single precision VFP reg.
364 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
365 %z<code> print a double precision VFP reg
366 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
368 %<bitfield>'c print specified char iff bitfield is all ones
369 %<bitfield>`c print specified char iff bitfield is all zeroes
370 %<bitfield>?ab... select from array of values in big endian order
372 %L print as an iWMMXt N/M width field.
373 %Z print the Immediate of a WSHUFH instruction.
374 %l like 'A' except use byte offsets for 'B' & 'H'
376 %i print 5-bit immediate in bits 8,3..0
378 %r print register offset address for wldt/wstr instruction. */
380 enum opcode_sentinel_enum
382 SENTINEL_IWMMXT_START
= 1,
384 SENTINEL_GENERIC_START
387 #define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
388 #define UNKNOWN_INSTRUCTION_32BIT "\t\t; <UNDEFINED> instruction: %08x"
389 #define UNKNOWN_INSTRUCTION_16BIT "\t\t; <UNDEFINED> instruction: %04x"
390 #define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
392 /* Common coprocessor opcodes shared between Arm and Thumb-2. */
394 static const struct sopcode32 coprocessor_opcodes
[] =
396 /* XScale instructions. */
397 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
398 0x0e200010, 0x0fff0ff0,
399 "mia%c\tacc0, %0-3r, %12-15r"},
400 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
401 0x0e280010, 0x0fff0ff0,
402 "miaph%c\tacc0, %0-3r, %12-15r"},
403 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
404 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
405 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
406 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
407 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
408 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
410 /* Intel Wireless MMX technology instructions. */
411 {ANY
, ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START
, 0, "" },
412 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
413 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
414 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
415 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
416 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
417 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
418 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
419 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
420 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
421 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
422 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
423 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
424 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
425 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
426 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
427 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
428 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
429 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
430 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
431 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
432 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
433 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
434 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
435 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
436 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
437 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
438 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
439 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
440 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
441 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
442 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
443 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
444 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
445 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
446 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
447 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
448 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
449 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
450 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
451 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
452 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
453 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
454 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
455 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
456 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
457 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
458 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
459 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
460 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
461 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
462 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
463 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
464 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
465 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
466 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
467 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
468 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
469 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
470 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
471 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
472 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
473 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
474 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
475 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
476 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
477 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
478 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
479 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
480 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
481 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
482 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
483 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
484 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
485 0x0e800120, 0x0f800ff0,
486 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
487 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
488 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
489 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
490 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
491 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
492 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
493 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
494 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
495 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
496 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
497 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
498 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
499 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
500 0x0e8000a0, 0x0f800ff0,
501 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
502 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
503 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
504 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
505 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
506 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
507 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
508 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
509 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
510 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
511 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
512 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
513 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
514 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
515 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
516 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
517 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
518 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
519 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
520 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
521 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
522 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
523 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
524 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
525 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
526 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
527 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
528 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
529 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
530 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
531 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
532 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
533 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
534 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
535 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
536 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
537 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
538 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
539 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
540 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
541 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
542 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
543 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
544 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
545 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
546 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
547 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
548 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
549 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
550 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
551 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
552 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
553 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
554 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
555 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
556 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
557 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
558 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
559 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
560 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
561 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
562 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
563 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
564 {ANY
, ARM_FEATURE_CORE_LOW (0),
565 SENTINEL_IWMMXT_END
, 0, "" },
567 /* Floating point coprocessor (FPA) instructions. */
568 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
569 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
570 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
571 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
572 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
573 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
574 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
575 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
576 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
577 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
578 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
579 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
580 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
581 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
582 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
583 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
584 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
585 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
586 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
587 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
588 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
589 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
590 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
591 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
592 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
593 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
594 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
595 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
596 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
597 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
598 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
599 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
600 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
601 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
602 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
603 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
604 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
605 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
606 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
607 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
608 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
609 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
610 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
611 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
612 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
613 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
614 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
615 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
616 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
617 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
618 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
619 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
620 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
621 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
622 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
623 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
624 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
625 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
626 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
627 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
628 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
629 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
630 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
631 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
632 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
633 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
634 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
635 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
636 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
637 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
638 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
639 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
640 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
641 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
642 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
643 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
644 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
645 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
646 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
647 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
648 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
649 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
650 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
),
651 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
652 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
),
653 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
655 /* Armv8.1-M Mainline instructions. */
656 {T32
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
657 0xec9f0b00, 0xffbf0f01, "vscclrm%c\t%C"},
658 {T32
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
659 0xec9f0a00, 0xffbf0f00, "vscclrm%c\t%C"},
661 /* ARMv8-M Mainline Security Extensions instructions. */
662 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
),
663 0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
664 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
),
665 0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
667 /* Register load/store. */
668 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
669 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
670 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
671 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
672 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
673 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
674 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
675 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
676 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
677 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
678 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
679 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
680 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
681 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
682 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
683 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
684 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
685 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
686 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
687 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
688 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
689 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
690 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
691 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
692 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
693 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
694 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
695 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
696 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
697 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
698 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
699 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
700 {ANY
, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN
),
701 0xec100f80, 0xfe101f80, "vldr%c\t%J, %K"},
702 {ANY
, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN
),
703 0xec000f80, 0xfe101f80, "vstr%c\t%J, %K"},
705 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
706 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
707 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
708 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
709 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
710 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
711 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
712 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
714 /* Data transfer between ARM and NEON registers. */
715 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
716 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
717 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
718 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
719 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
720 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
721 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
722 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
723 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
724 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
725 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
726 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
727 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
728 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
729 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
730 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
731 /* Half-precision conversion instructions. */
732 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
733 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
734 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
735 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
736 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
),
737 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
738 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
),
739 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
741 /* Floating point coprocessor (VFP) instructions. */
742 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
743 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
744 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
745 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
746 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
747 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
748 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
749 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
750 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
751 0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"},
752 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
753 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
754 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
755 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
756 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
757 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
758 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
759 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
760 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
761 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
762 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
763 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
764 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
765 0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"},
766 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
767 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
768 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
769 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
770 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
771 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
772 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
773 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
774 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
775 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
776 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
777 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
778 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
779 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
780 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
781 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
782 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
783 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
784 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
785 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
786 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
787 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
788 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
789 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
790 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
791 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
792 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
793 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
794 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
795 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
796 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
797 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
798 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
799 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
800 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
801 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
802 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
803 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
804 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
805 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
806 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
807 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
808 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
809 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
810 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
811 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
812 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
813 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
814 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
815 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
816 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
817 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
818 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
819 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
820 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
),
821 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
822 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
),
823 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
824 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
825 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
826 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
827 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
828 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
),
829 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
830 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
),
831 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
832 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
833 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
834 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
),
835 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
836 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
),
837 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
838 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
),
839 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
840 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
),
841 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
842 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
),
843 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
844 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
845 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
846 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
847 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
848 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
849 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
850 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
851 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
852 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
853 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
854 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
855 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
856 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
857 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
858 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
859 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
860 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
861 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
862 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
863 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
864 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
865 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
866 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
867 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
868 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
869 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
870 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
871 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
872 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
873 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
874 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
875 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
876 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
877 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
878 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
879 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
881 /* Cirrus coprocessor instructions. */
882 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
883 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
884 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
885 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
886 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
887 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
888 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
889 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
890 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
891 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
892 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
893 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
894 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
895 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
896 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
897 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
898 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
899 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
900 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
901 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
902 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
903 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
904 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
905 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
906 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
907 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
908 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
909 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
910 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
911 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
912 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
913 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
914 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
915 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
916 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
917 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
918 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
919 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
920 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
921 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
922 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
923 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
924 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
925 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
926 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
927 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
928 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
929 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
930 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
931 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
932 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
933 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
934 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
935 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
936 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
937 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
938 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
939 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
940 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
941 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
942 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
943 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
944 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
945 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
946 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
947 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
948 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
949 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
950 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
951 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
952 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
953 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
954 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
955 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
956 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
957 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
958 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
959 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
960 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
961 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
962 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
963 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
964 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
965 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
966 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
967 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
968 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
969 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
970 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
971 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
972 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
973 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
974 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
975 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
976 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
977 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
978 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
979 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
980 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
981 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
982 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
983 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
984 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
985 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
986 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
987 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
988 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
989 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
990 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
991 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
992 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
993 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
994 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
995 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
996 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
997 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
998 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
999 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
1000 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1001 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
1002 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1003 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
1004 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1005 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
1006 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1007 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
1008 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1009 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
1010 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1011 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
1012 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1013 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
1014 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1015 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
1016 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1017 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
1018 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1019 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
1020 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1021 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
1022 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1023 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
1024 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1025 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
1026 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1027 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1028 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1029 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
1030 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1031 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1032 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1033 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
1034 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1035 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1036 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1037 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
1038 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1039 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1040 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1041 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1042 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1043 0x0e000600, 0x0ff00f10,
1044 "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1045 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1046 0x0e100600, 0x0ff00f10,
1047 "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1048 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1049 0x0e200600, 0x0ff00f10,
1050 "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
1051 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1052 0x0e300600, 0x0ff00f10,
1053 "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
1055 /* VFP Fused multiply add instructions. */
1056 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1057 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
1058 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1059 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
1060 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1061 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
1062 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1063 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
1064 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1065 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
1066 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1067 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
1068 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1069 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
1070 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1071 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
1074 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1075 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
1076 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1077 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
1078 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1079 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
1080 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1081 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
1082 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1083 0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
1084 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1085 0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
1086 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1087 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
1088 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1089 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
1090 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1091 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
1092 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1093 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
1094 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1095 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
1096 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1097 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
1099 /* Generic coprocessor instructions. */
1100 {ANY
, ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START
, 0, "" },
1101 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
1102 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
1103 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
1104 0x0c500000, 0x0ff00000,
1105 "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
1106 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1107 0x0e000000, 0x0f000010,
1108 "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
1109 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1110 0x0e10f010, 0x0f10f010,
1111 "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
1112 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1113 0x0e100010, 0x0f100010,
1114 "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1115 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1116 0x0e000010, 0x0f100010,
1117 "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
1118 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1119 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
1120 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1121 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
1123 /* V6 coprocessor instructions. */
1124 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
1125 0xfc500000, 0xfff00000,
1126 "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
1127 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
1128 0xfc400000, 0xfff00000,
1129 "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
1131 /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */
1132 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1133 0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
1134 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1135 0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
1136 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1137 0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
1138 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1139 0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
1140 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1141 0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
1142 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1143 0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
1144 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1145 0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
1146 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1147 0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"},
1148 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1149 0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
1150 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1151 0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"},
1153 /* Dot Product instructions in the space of coprocessor 13. */
1154 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
1155 0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
1156 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
1157 0xfe000d00, 0xff000f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"},
1159 /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8. */
1160 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1161 0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
1162 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1163 0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
1164 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1165 0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
1166 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1167 0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
1168 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1169 0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
1170 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1171 0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
1172 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1173 0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
1174 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1175 0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
1177 /* V5 coprocessor instructions. */
1178 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1179 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
1180 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1181 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
1182 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1183 0xfe000000, 0xff000010,
1184 "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
1185 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1186 0xfe000010, 0xff100010,
1187 "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
1188 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1189 0xfe100010, 0xff100010,
1190 "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1192 /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
1193 cp_num: bit <11:8> == 0b1001.
1194 cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */
1195 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1196 0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
1197 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1198 0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
1199 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1200 0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
1201 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1202 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
1203 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1204 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
1205 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1206 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
1207 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1208 0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
1209 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1210 0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
1211 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1212 0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
1213 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1214 0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
1215 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1216 0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
1217 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1218 0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
1219 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1220 0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
1221 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1222 0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
1223 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1224 0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
1225 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1226 0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
1227 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1228 0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
1229 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1230 0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
1231 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1232 0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
1233 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1234 0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
1235 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1236 0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
1237 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1238 0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
1239 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1240 0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
1241 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1242 0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
1243 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1244 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
1245 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1246 0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
1247 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1248 0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
1249 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1250 0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
1251 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1252 0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
1253 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1254 0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
1255 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1256 0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
1257 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1258 0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
1259 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1260 0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
1261 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1262 0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
1263 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1264 0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
1266 /* ARMv8.3 javascript conversion instruction. */
1267 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1268 0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
1270 {ANY
, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
1273 /* Neon opcode table: This does not encode the top byte -- that is
1274 checked by the print_insn_neon routine, as it depends on whether we are
1275 doing thumb32 or arm32 disassembly. */
1277 /* print_insn_neon recognizes the following format control codes:
1281 %c print condition code
1282 %u print condition code (unconditional in ARM mode,
1283 UNPREDICTABLE if not AL in Thumb)
1284 %A print v{st,ld}[1234] operands
1285 %B print v{st,ld}[1234] any one operands
1286 %C print v{st,ld}[1234] single->all operands
1288 %E print vmov, vmvn, vorr, vbic encoded constant
1289 %F print vtbl,vtbx register list
1291 %<bitfield>r print as an ARM register
1292 %<bitfield>d print the bitfield in decimal
1293 %<bitfield>e print the 2^N - bitfield in decimal
1294 %<bitfield>D print as a NEON D register
1295 %<bitfield>Q print as a NEON Q register
1296 %<bitfield>R print as a NEON D or Q register
1297 %<bitfield>Sn print byte scaled width limited by n
1298 %<bitfield>Tn print short scaled width limited by n
1299 %<bitfield>Un print long scaled width limited by n
1301 %<bitfield>'c print specified char iff bitfield is all ones
1302 %<bitfield>`c print specified char iff bitfield is all zeroes
1303 %<bitfield>?ab... select from array of values in big endian order. */
1305 static const struct opcode32 neon_opcodes
[] =
1308 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1309 0xf2b00840, 0xffb00850,
1310 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1311 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1312 0xf2b00000, 0xffb00810,
1313 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1315 /* Data transfer between ARM and NEON registers. */
1316 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1317 0x0e800b10, 0x1ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
1318 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1319 0x0e800b30, 0x1ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
1320 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1321 0x0ea00b10, 0x1ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
1322 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1323 0x0ea00b30, 0x1ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
1324 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1325 0x0ec00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
1326 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1327 0x0ee00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
1329 /* Move data element to all lanes. */
1330 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1331 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
1332 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1333 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
1334 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1335 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
1338 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1339 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1340 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1341 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1343 /* Half-precision conversions. */
1344 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
),
1345 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1346 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
),
1347 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
1349 /* NEON fused multiply add instructions. */
1350 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
),
1351 0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1352 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1353 0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1354 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
),
1355 0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1356 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1357 0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1359 /* Two registers, miscellaneous. */
1360 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
),
1361 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
1362 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1363 0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
1364 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
),
1365 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
1366 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1367 0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
1368 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1369 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1370 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1371 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1372 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1373 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1374 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1375 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1376 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1377 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1378 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1379 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1380 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1381 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1382 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1383 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1384 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1385 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1386 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1387 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1388 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1389 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1390 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1391 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1392 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1393 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1394 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1395 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1396 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1397 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1398 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1399 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1400 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1401 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1402 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1403 0xf3b20300, 0xffb30fd0,
1404 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1405 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1406 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1407 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1408 0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1409 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1410 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1411 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1412 0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1413 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1414 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1415 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1416 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1417 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1418 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1419 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1420 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1421 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1422 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1423 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1424 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1425 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1426 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1427 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1428 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1429 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1430 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1431 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1432 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1433 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1434 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1435 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1436 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1437 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1438 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1439 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1440 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1441 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1442 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1443 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1444 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1445 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1446 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1447 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1448 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1449 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1450 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1451 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1452 0xf3bb0600, 0xffbf0e10,
1453 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
1454 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1455 0xf3b70600, 0xffbf0e10,
1456 "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
1458 /* Three registers of the same length. */
1459 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1460 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1461 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1462 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1463 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1464 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1465 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1466 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1467 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1468 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1469 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1470 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1471 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1472 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1473 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
),
1474 0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1475 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1476 0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1477 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
),
1478 0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1479 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1480 0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1481 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1482 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1483 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1484 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1485 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1486 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1487 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1488 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1489 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1490 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1491 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1492 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1493 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1494 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1495 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1496 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1497 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1498 0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1499 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1500 0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1501 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1502 0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1503 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1504 0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1505 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1506 0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1507 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1508 0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1509 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1510 0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1511 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1512 0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1513 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1514 0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1515 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1516 0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1517 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1518 0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1519 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1520 0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1521 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1522 0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1523 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1524 0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1525 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1526 0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1527 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1528 0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1529 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1530 0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1531 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1532 0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1533 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1534 0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1535 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1536 0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1537 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1538 0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1539 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1540 0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1541 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1542 0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1543 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1544 0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1545 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1546 0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1547 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1548 0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1549 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1550 0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1551 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1552 0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1553 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1554 0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1555 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1556 0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1557 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1558 0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1559 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1560 0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1561 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1562 0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1563 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1564 0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1565 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1566 0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1567 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1568 0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1569 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1570 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1571 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1572 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1573 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1574 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1575 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1576 0xf2000b00, 0xff800f10,
1577 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1578 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1579 0xf2000b10, 0xff800f10,
1580 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1581 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1582 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1583 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1584 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1585 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1586 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1587 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1588 0xf3000b00, 0xff800f10,
1589 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1590 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1591 0xf2000000, 0xfe800f10,
1592 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1593 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1594 0xf2000010, 0xfe800f10,
1595 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1596 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1597 0xf2000100, 0xfe800f10,
1598 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1599 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1600 0xf2000200, 0xfe800f10,
1601 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1602 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1603 0xf2000210, 0xfe800f10,
1604 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1605 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1606 0xf2000300, 0xfe800f10,
1607 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1608 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1609 0xf2000310, 0xfe800f10,
1610 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1611 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1612 0xf2000400, 0xfe800f10,
1613 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1614 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1615 0xf2000410, 0xfe800f10,
1616 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1617 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1618 0xf2000500, 0xfe800f10,
1619 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1620 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1621 0xf2000510, 0xfe800f10,
1622 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1623 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1624 0xf2000600, 0xfe800f10,
1625 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1626 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1627 0xf2000610, 0xfe800f10,
1628 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1629 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1630 0xf2000700, 0xfe800f10,
1631 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1632 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1633 0xf2000710, 0xfe800f10,
1634 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1635 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1636 0xf2000910, 0xfe800f10,
1637 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1638 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1639 0xf2000a00, 0xfe800f10,
1640 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1641 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1642 0xf2000a10, 0xfe800f10,
1643 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1644 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
1645 0xf3000b10, 0xff800f10,
1646 "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1647 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
1648 0xf3000c10, 0xff800f10,
1649 "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1651 /* One register and an immediate value. */
1652 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1653 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1654 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1655 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1656 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1657 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1658 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1659 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1660 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1661 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1662 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1663 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1664 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1665 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1666 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1667 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1668 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1669 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1670 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1671 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1672 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1673 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1674 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1675 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1676 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1677 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
1679 /* Two registers and a shift amount. */
1680 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1681 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1682 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1683 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1684 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1685 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1686 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1687 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1688 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1689 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1690 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1691 0xf2880950, 0xfeb80fd0,
1692 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1693 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1694 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1695 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1696 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1697 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1698 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1699 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1700 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1701 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1702 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1703 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1704 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1705 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1706 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1707 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1708 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1709 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1710 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1711 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1712 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1713 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1714 0xf2900950, 0xfeb00fd0,
1715 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1716 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1717 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1718 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1719 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1720 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1721 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1722 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1723 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1724 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1725 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1726 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1727 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1728 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1729 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1730 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1731 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1732 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1733 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1734 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1735 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1736 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1737 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1738 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1739 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1740 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1741 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1742 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1743 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1744 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1745 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1746 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1747 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1748 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1749 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1750 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1751 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1752 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1753 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1754 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1755 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1756 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1757 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1758 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1759 0xf2a00950, 0xfea00fd0,
1760 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1761 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1762 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1763 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1764 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1765 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1766 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1767 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1768 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1769 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1770 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1771 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1772 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1773 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1774 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1775 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1776 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1777 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1778 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1779 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1780 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1781 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1782 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1783 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1784 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1785 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1786 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1787 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1788 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1789 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1790 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1791 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1792 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1793 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1794 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1795 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1796 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1797 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1798 0xf2a00e10, 0xfea00e90,
1799 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
1800 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1801 0xf2a00c10, 0xfea00e90,
1802 "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"},
1804 /* Three registers of different lengths. */
1805 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1806 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1807 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1808 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1809 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1810 0xf2800400, 0xff800f50,
1811 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1812 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1813 0xf2800600, 0xff800f50,
1814 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1815 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1816 0xf2800900, 0xff800f50,
1817 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1818 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1819 0xf2800b00, 0xff800f50,
1820 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1821 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1822 0xf2800d00, 0xff800f50,
1823 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1824 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1825 0xf3800400, 0xff800f50,
1826 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1827 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1828 0xf3800600, 0xff800f50,
1829 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1830 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1831 0xf2800000, 0xfe800f50,
1832 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1833 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1834 0xf2800100, 0xfe800f50,
1835 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1836 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1837 0xf2800200, 0xfe800f50,
1838 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1839 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1840 0xf2800300, 0xfe800f50,
1841 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1842 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1843 0xf2800500, 0xfe800f50,
1844 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1845 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1846 0xf2800700, 0xfe800f50,
1847 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1848 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1849 0xf2800800, 0xfe800f50,
1850 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1851 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1852 0xf2800a00, 0xfe800f50,
1853 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1854 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1855 0xf2800c00, 0xfe800f50,
1856 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1858 /* Two registers and a scalar. */
1859 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1860 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1861 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1862 0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1863 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
1864 0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
1865 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1866 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1867 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1868 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1869 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1870 0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1871 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
1872 0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
1873 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1874 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1875 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1876 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1877 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1878 0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1879 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
1880 0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
1881 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1882 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1883 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1884 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1885 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1886 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1887 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1888 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1889 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1890 0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1891 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
1892 0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1893 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1894 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1895 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1896 0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1897 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
1898 0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1899 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1900 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1901 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1902 0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1903 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
1904 0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1905 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1906 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1907 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1908 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1909 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1910 0xf2800240, 0xfe800f50,
1911 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1912 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1913 0xf2800640, 0xfe800f50,
1914 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1915 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1916 0xf2800a40, 0xfe800f50,
1917 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1918 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
1919 0xf2800e40, 0xff800f50,
1920 "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1921 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
1922 0xf2800f40, 0xff800f50,
1923 "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1924 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
1925 0xf3800e40, 0xff800f50,
1926 "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1927 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
1928 0xf3800f40, 0xff800f50,
1929 "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
1932 /* Element and structure load/store. */
1933 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1934 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
1935 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1936 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
1937 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1938 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
1939 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1940 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
1941 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1942 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
1943 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1944 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1945 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1946 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1947 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1948 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1949 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1950 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1951 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1952 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1953 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1954 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1955 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1956 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1957 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1958 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1959 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1960 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1961 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1962 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
1963 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1964 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
1965 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1966 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
1967 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1968 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
1969 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1970 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
1972 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
1975 /* mve opcode table. */
1977 /* print_insn_mve recognizes the following format control codes:
1981 %a print '+' or '-' or imm offset in vldr[bhwd] and
1983 %c print condition code
1984 %d print addr mode of MVE vldr[bhw] and vstr[bhw]
1985 %u print 'U' (unsigned) or 'S' for various mve instructions
1986 %i print MVE predicate(s) for vpt and vpst
1987 %m print rounding mode for vcvt and vrint
1988 %n print vector comparison code for predicated instruction
1989 %s print size for various vcvt instructions
1990 %v print vector predicate for instruction in predicated
1992 %o print offset scaled for vldr[hwd] and vstr[hwd]
1993 %w print writeback mode for MVE v{st,ld}[24]
1994 %B print v{st,ld}[24] any one operands
1995 %E print vmov, vmvn, vorr, vbic encoded constant
1996 %N print generic index for vmov
1997 %T print bottom ('b') or top ('t') of source register
1998 %X print exchange field in vmla* instructions
2000 %<bitfield>r print as an ARM register
2001 %<bitfield>d print the bitfield in decimal
2002 %<bitfield>A print accumulate or not
2003 %<bitfield>Q print as a MVE Q register
2004 %<bitfield>F print as a MVE S register
2005 %<bitfield>Z as %<>r but r15 is ZR instead of PC and r13 is
2007 %<bitfield>s print size for vector predicate & non VMOV instructions
2008 %<bitfield>I print carry flag or not
2009 %<bitfield>i print immediate for vstr/vldr reg +/- imm
2010 %<bitfield>h print high half of 64-bit destination reg
2011 %<bitfield>k print immediate for vector conversion instruction
2012 %<bitfield>l print low half of 64-bit destination reg
2013 %<bitfield>o print rotate value for vcmul
2014 %<bitfield>u print immediate value for vddup/vdwdup
2015 %<bitfield>x print the bitfield in hex.
2018 static const struct mopcode32 mve_opcodes
[] =
2022 {ARM_FEATURE_COPROC (FPU_MVE
),
2024 0xfe310f4d, 0xffbf1fff,
2028 /* Floating point VPT T1. */
2029 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2031 0xee310f00, 0xefb10f50,
2032 "vpt%i.f%28s\t%n, %17-19Q, %1-3,5Q"},
2033 /* Floating point VPT T2. */
2034 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2036 0xee310f40, 0xefb10f50,
2037 "vpt%i.f%28s\t%n, %17-19Q, %0-3Z"},
2039 /* Vector VPT T1. */
2040 {ARM_FEATURE_COPROC (FPU_MVE
),
2042 0xfe010f00, 0xff811f51,
2043 "vpt%i.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2044 /* Vector VPT T2. */
2045 {ARM_FEATURE_COPROC (FPU_MVE
),
2047 0xfe010f01, 0xff811f51,
2048 "vpt%i.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2049 /* Vector VPT T3. */
2050 {ARM_FEATURE_COPROC (FPU_MVE
),
2052 0xfe011f00, 0xff811f50,
2053 "vpt%i.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2054 /* Vector VPT T4. */
2055 {ARM_FEATURE_COPROC (FPU_MVE
),
2057 0xfe010f40, 0xff811f70,
2058 "vpt%i.i%20-21s\t%n, %17-19Q, %0-3Z"},
2059 /* Vector VPT T5. */
2060 {ARM_FEATURE_COPROC (FPU_MVE
),
2062 0xfe010f60, 0xff811f70,
2063 "vpt%i.u%20-21s\t%n, %17-19Q, %0-3Z"},
2064 /* Vector VPT T6. */
2065 {ARM_FEATURE_COPROC (FPU_MVE
),
2067 0xfe011f40, 0xff811f50,
2068 "vpt%i.s%20-21s\t%n, %17-19Q, %0-3Z"},
2070 /* Vector VBIC immediate. */
2071 {ARM_FEATURE_COPROC (FPU_MVE
),
2073 0xef800070, 0xefb81070,
2074 "vbic%v.i%8-11s\t%13-15,22Q, %E"},
2076 /* Vector VBIC register. */
2077 {ARM_FEATURE_COPROC (FPU_MVE
),
2079 0xef100150, 0xffb11f51,
2080 "vbic%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2083 {ARM_FEATURE_COPROC (FPU_MVE
),
2085 0xee800f01, 0xefc10f51,
2086 "vabav%v.%u%20-21s\t%12-15r, %17-19,7Q, %1-3,5Q"},
2088 /* Vector VABD floating point. */
2089 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2091 0xff200d40, 0xffa11f51,
2092 "vabd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2095 {ARM_FEATURE_COPROC (FPU_MVE
),
2097 0xef000740, 0xef811f51,
2098 "vabd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2100 /* Vector VABS floating point. */
2101 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2103 0xFFB10740, 0xFFB31FD1,
2104 "vabs%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
2106 {ARM_FEATURE_COPROC (FPU_MVE
),
2108 0xffb10340, 0xffb31fd1,
2109 "vabs%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2111 /* Vector VADD floating point T1. */
2112 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2114 0xef000d40, 0xffa11f51,
2115 "vadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2116 /* Vector VADD floating point T2. */
2117 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2119 0xee300f40, 0xefb11f70,
2120 "vadd%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2121 /* Vector VADD T1. */
2122 {ARM_FEATURE_COPROC (FPU_MVE
),
2124 0xef000840, 0xff811f51,
2125 "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2126 /* Vector VADD T2. */
2127 {ARM_FEATURE_COPROC (FPU_MVE
),
2129 0xee010f40, 0xff811f70,
2130 "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2132 /* Vector VADDLV. */
2133 {ARM_FEATURE_COPROC (FPU_MVE
),
2135 0xee890f00, 0xef8f1fd1,
2136 "vaddlv%5A%v.%u32\t%13-15l, %20-22h, %1-3Q"},
2139 {ARM_FEATURE_COPROC (FPU_MVE
),
2141 0xeef10f00, 0xeff31fd1,
2142 "vaddv%5A%v.%u%18-19s\t%13-15l, %1-3Q"},
2145 {ARM_FEATURE_COPROC (FPU_MVE
),
2147 0xee300f00, 0xffb10f51,
2148 "vadc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2150 /* Vector VCADD floating point. */
2151 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2153 0xfc800840, 0xfea11f51,
2154 "vcadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%24o"},
2157 {ARM_FEATURE_COPROC (FPU_MVE
),
2159 0xfe000f00, 0xff810f51,
2160 "vcadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
2163 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2165 0xfc200840, 0xfe211f51,
2166 "vcmla%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%23-24o"},
2168 /* Vector VCMP floating point T1. */
2169 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2171 0xee310f00, 0xeff1ef50,
2172 "vcmp%v.f%28s\t%n, %17-19Q, %1-3,5Q"},
2174 /* Vector VCMP floating point T2. */
2175 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2177 0xee310f40, 0xeff1ef50,
2178 "vcmp%v.f%28s\t%n, %17-19Q, %0-3Z"},
2180 /* Vector VCMP T1. */
2181 {ARM_FEATURE_COPROC (FPU_MVE
),
2183 0xfe010f00, 0xffc1ff51,
2184 "vcmp%v.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2185 /* Vector VCMP T2. */
2186 {ARM_FEATURE_COPROC (FPU_MVE
),
2188 0xfe010f01, 0xffc1ff51,
2189 "vcmp%v.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2190 /* Vector VCMP T3. */
2191 {ARM_FEATURE_COPROC (FPU_MVE
),
2193 0xfe011f00, 0xffc1ff50,
2194 "vcmp%v.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2195 /* Vector VCMP T4. */
2196 {ARM_FEATURE_COPROC (FPU_MVE
),
2198 0xfe010f40, 0xffc1ff70,
2199 "vcmp%v.i%20-21s\t%n, %17-19Q, %0-3Z"},
2200 /* Vector VCMP T5. */
2201 {ARM_FEATURE_COPROC (FPU_MVE
),
2203 0xfe010f60, 0xffc1ff70,
2204 "vcmp%v.u%20-21s\t%n, %17-19Q, %0-3Z"},
2205 /* Vector VCMP T6. */
2206 {ARM_FEATURE_COPROC (FPU_MVE
),
2208 0xfe011f40, 0xffc1ff50,
2209 "vcmp%v.s%20-21s\t%n, %17-19Q, %0-3Z"},
2212 {ARM_FEATURE_COPROC (FPU_MVE
),
2214 0xeea00b10, 0xffb10f5f,
2215 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2218 {ARM_FEATURE_COPROC (FPU_MVE
),
2220 0xff000150, 0xffd11f51,
2221 "veor%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2223 /* Vector VFMA, vector * scalar. */
2224 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2226 0xee310e40, 0xefb11f70,
2227 "vfma%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2229 /* Vector VFMA floating point. */
2230 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2232 0xef000c50, 0xffa11f51,
2233 "vfma%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2235 /* Vector VFMS floating point. */
2236 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2238 0xef200c50, 0xffa11f51,
2239 "vfms%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2241 /* Vector VFMAS, vector * scalar. */
2242 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2243 MVE_VFMAS_FP_SCALAR
,
2244 0xee311e40, 0xefb11f70,
2245 "vfmas%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2247 /* Vector VHADD T1. */
2248 {ARM_FEATURE_COPROC (FPU_MVE
),
2250 0xef000040, 0xef811f51,
2251 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2253 /* Vector VHADD T2. */
2254 {ARM_FEATURE_COPROC (FPU_MVE
),
2256 0xee000f40, 0xef811f70,
2257 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2259 /* Vector VHSUB T1. */
2260 {ARM_FEATURE_COPROC (FPU_MVE
),
2262 0xef000240, 0xef811f51,
2263 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2265 /* Vector VHSUB T2. */
2266 {ARM_FEATURE_COPROC (FPU_MVE
),
2268 0xee001f40, 0xef811f70,
2269 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2272 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2274 0xee300e00, 0xefb10f50,
2275 "vcmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%0,12o"},
2278 {ARM_FEATURE_COPROC (FPU_MVE
),
2280 0xeea00b10, 0xffb10f5f,
2281 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2283 /* Vector VRHADD. */
2284 {ARM_FEATURE_COPROC (FPU_MVE
),
2286 0xef000140, 0xef811f51,
2287 "vrhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2290 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2291 MVE_VCVT_FP_FIX_VEC
,
2292 0xef800c50, 0xef801cd1,
2293 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q, #%16-21k"},
2296 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2297 MVE_VCVT_BETWEEN_FP_INT
,
2298 0xffb30640, 0xffb31e51,
2299 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q"},
2301 /* Vector VCVT between single and half-precision float, bottom half. */
2302 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2303 MVE_VCVT_FP_HALF_FP
,
2304 0xee3f0e01, 0xefbf1fd1,
2305 "vcvtb%v.%s\t%13-15,22Q, %1-3,5Q"},
2307 /* Vector VCVT between single and half-precision float, top half. */
2308 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2309 MVE_VCVT_FP_HALF_FP
,
2310 0xee3f1e01, 0xefbf1fd1,
2311 "vcvtt%v.%s\t%13-15,22Q, %1-3,5Q"},
2314 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2315 MVE_VCVT_FROM_FP_TO_INT
,
2316 0xffb30040, 0xffb31c51,
2317 "vcvt%m%v.%s\t%13-15,22Q, %1-3,5Q"},
2320 {ARM_FEATURE_COPROC (FPU_MVE
),
2322 0xee011f6e, 0xff811f7e,
2323 "vddup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
2325 /* Vector VDWDUP. */
2326 {ARM_FEATURE_COPROC (FPU_MVE
),
2328 0xee011f60, 0xff811f70,
2329 "vdwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
2331 /* Vector VHCADD. */
2332 {ARM_FEATURE_COPROC (FPU_MVE
),
2334 0xee000f00, 0xff810f51,
2335 "vhcadd%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
2337 /* Vector VIWDUP. */
2338 {ARM_FEATURE_COPROC (FPU_MVE
),
2340 0xee010f60, 0xff811f70,
2341 "viwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
2344 {ARM_FEATURE_COPROC (FPU_MVE
),
2346 0xee010f6e, 0xff811f7e,
2347 "vidup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
2350 {ARM_FEATURE_COPROC (FPU_MVE
),
2352 0xfc901e00, 0xff901e5f,
2353 "vld2%5d.%7-8s\t%B, [%16-19r]%w"},
2356 {ARM_FEATURE_COPROC (FPU_MVE
),
2358 0xfc901e01, 0xff901e1f,
2359 "vld4%5-6d.%7-8s\t%B, [%16-19r]%w"},
2361 /* Vector VLDRB gather load. */
2362 {ARM_FEATURE_COPROC (FPU_MVE
),
2363 MVE_VLDRB_GATHER_T1
,
2364 0xec900e00, 0xefb01e50,
2365 "vldrb%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
2367 /* Vector VLDRH gather load. */
2368 {ARM_FEATURE_COPROC (FPU_MVE
),
2369 MVE_VLDRH_GATHER_T2
,
2370 0xec900e10, 0xefb01e50,
2371 "vldrh%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2373 /* Vector VLDRW gather load. */
2374 {ARM_FEATURE_COPROC (FPU_MVE
),
2375 MVE_VLDRW_GATHER_T3
,
2376 0xfc900f40, 0xffb01fd0,
2377 "vldrw%v.u32\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2379 /* Vector VLDRD gather load. */
2380 {ARM_FEATURE_COPROC (FPU_MVE
),
2381 MVE_VLDRD_GATHER_T4
,
2382 0xec900fd0, 0xefb01fd0,
2383 "vldrd%v.u64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2385 /* Vector VLDRW gather load. */
2386 {ARM_FEATURE_COPROC (FPU_MVE
),
2387 MVE_VLDRW_GATHER_T5
,
2388 0xfd101e00, 0xff111f00,
2389 "vldrw%v.u32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2391 /* Vector VLDRD gather load, variant T6. */
2392 {ARM_FEATURE_COPROC (FPU_MVE
),
2393 MVE_VLDRD_GATHER_T6
,
2394 0xfd101f00, 0xff111f00,
2395 "vldrd%v.u64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2398 {ARM_FEATURE_COPROC (FPU_MVE
),
2400 0xec100e00, 0xee581e00,
2401 "vldrb%v.%u%7-8s\t%13-15Q, %d"},
2404 {ARM_FEATURE_COPROC (FPU_MVE
),
2406 0xec180e00, 0xee581e00,
2407 "vldrh%v.%u%7-8s\t%13-15Q, %d"},
2409 /* Vector VLDRB unsigned, variant T5. */
2410 {ARM_FEATURE_COPROC (FPU_MVE
),
2412 0xec101e00, 0xfe101f80,
2413 "vldrb%v.u8\t%13-15,22Q, %d"},
2415 /* Vector VLDRH unsigned, variant T6. */
2416 {ARM_FEATURE_COPROC (FPU_MVE
),
2418 0xec101e80, 0xfe101f80,
2419 "vldrh%v.u16\t%13-15,22Q, %d"},
2421 /* Vector VLDRW unsigned, variant T7. */
2422 {ARM_FEATURE_COPROC (FPU_MVE
),
2424 0xec101f00, 0xfe101f80,
2425 "vldrw%v.u32\t%13-15,22Q, %d"},
2427 /* Vector VMLALDAV. Note must appear before VMLADAV due to instruction
2429 {ARM_FEATURE_COPROC (FPU_MVE
),
2431 0xee801e00, 0xef801f51,
2432 "vmlaldav%5Ax%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2434 {ARM_FEATURE_COPROC (FPU_MVE
),
2436 0xee800e00, 0xef801f51,
2437 "vmlalv%5A%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2439 /* Vector VMLAV T1 variant, same as VMLADAV but with X == 0. */
2440 {ARM_FEATURE_COPROC (FPU_MVE
),
2442 0xeef00e00, 0xeff01f51,
2443 "vmlav%5A%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2445 /* Vector VMLAV T2 variant, same as VMLADAV but with X == 0. */
2446 {ARM_FEATURE_COPROC (FPU_MVE
),
2448 0xeef00f00, 0xeff11f51,
2449 "vmlav%5A%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2451 /* Vector VMLADAV T1 variant. */
2452 {ARM_FEATURE_COPROC (FPU_MVE
),
2454 0xeef01e00, 0xeff01f51,
2455 "vmladav%5Ax%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2457 /* Vector VMLADAV T2 variant. */
2458 {ARM_FEATURE_COPROC (FPU_MVE
),
2460 0xeef01f00, 0xeff11f51,
2461 "vmladav%5Ax%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2464 {ARM_FEATURE_COPROC (FPU_MVE
),
2466 0xee011e40, 0xef811f70,
2467 "vmlas%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2469 /* Vector VRMLSLDAVH. Note must appear before VMLSDAV due to instruction
2471 {ARM_FEATURE_COPROC (FPU_MVE
),
2473 0xfe800e01, 0xff810f51,
2474 "vrmlsldavh%5A%X%v.s32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2476 /* Vector VMLSLDAV. Note must appear before VMLSDAV due to instruction
2478 {ARM_FEATURE_COPROC (FPU_MVE
),
2480 0xee800e01, 0xff800f51,
2481 "vmlsldav%5A%X%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2483 /* Vector VMLSDAV T1 Variant. */
2484 {ARM_FEATURE_COPROC (FPU_MVE
),
2486 0xeef00e01, 0xfff00f51,
2487 "vmlsdav%5A%X%v.s%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2489 /* Vector VMLSDAV T2 Variant. */
2490 {ARM_FEATURE_COPROC (FPU_MVE
),
2492 0xfef00e01, 0xfff10f51,
2493 "vmlsdav%5A%X%v.s8\t%13-15l, %17-19,7Q, %1-3Q"},
2495 /* Vector VMOV between gpr and half precision register, op == 0. */
2496 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2498 0xee000910, 0xfff00f7f,
2499 "vmov.f16\t%7,16-19F, %12-15r"},
2501 /* Vector VMOV between gpr and half precision register, op == 1. */
2502 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2504 0xee100910, 0xfff00f7f,
2505 "vmov.f16\t%12-15r, %7,16-19F"},
2507 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2508 MVE_VMOV_GP_TO_VEC_LANE
,
2509 0xee000b10, 0xff900f1f,
2510 "vmov%c.%5-6,21-22s\t%17-19,7Q[%N], %12-15r"},
2512 /* Vector VORR immediate to vector.
2513 NOTE: MVE_VORR_IMM must appear in the table
2514 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2515 {ARM_FEATURE_COPROC (FPU_MVE
),
2517 0xef800050, 0xefb810f0,
2518 "vorr%v.i%8-11s\t%13-15,22Q, %E"},
2520 /* Vector VQSHL T2 Variant.
2521 NOTE: MVE_VQSHL_T2 must appear in the table before
2522 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2523 {ARM_FEATURE_COPROC (FPU_MVE
),
2525 0xef800750, 0xef801fd1,
2526 "vqshl%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2528 /* Vector VQSHLU T3 Variant
2529 NOTE: MVE_VQSHL_T2 must appear in the table before
2530 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2532 {ARM_FEATURE_COPROC (FPU_MVE
),
2534 0xff800650, 0xff801fd1,
2535 "vqshlu%v.s%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2538 NOTE: MVE_VRSHR must appear in the table before
2539 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2540 {ARM_FEATURE_COPROC (FPU_MVE
),
2542 0xef800250, 0xef801fd1,
2543 "vrshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2546 NOTE: MVE_VSHL must appear in the table before
2547 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2548 {ARM_FEATURE_COPROC (FPU_MVE
),
2550 0xef800550, 0xff801fd1,
2551 "vshl%v.i%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2554 NOTE: MVE_VSHR must appear in the table before
2555 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2556 {ARM_FEATURE_COPROC (FPU_MVE
),
2558 0xef800050, 0xef801fd1,
2559 "vshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2562 NOTE: MVE_VSLI must appear in the table before
2563 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2564 {ARM_FEATURE_COPROC (FPU_MVE
),
2566 0xff800550, 0xff801fd1,
2567 "vsli%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2570 NOTE: MVE_VSRI must appear in the table before
2571 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2572 {ARM_FEATURE_COPROC (FPU_MVE
),
2574 0xff800450, 0xff801fd1,
2575 "vsri%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2577 /* Vector VMOV immediate to vector,
2578 cmode == 11x1 -> VMVN which is UNDEFINED
2579 for such a cmode. */
2580 {ARM_FEATURE_COPROC (FPU_MVE
),
2581 MVE_VMVN_IMM
, 0xef800d50, 0xefb81dd0, UNDEFINED_INSTRUCTION
},
2583 /* Vector VMOV immediate to vector. */
2584 {ARM_FEATURE_COPROC (FPU_MVE
),
2585 MVE_VMOV_IMM_TO_VEC
,
2586 0xef800050, 0xefb810d0,
2587 "vmov%v.%5,8-11s\t%13-15,22Q, %E"},
2589 /* Vector VMOV two 32-bit lanes to two gprs, idx = 0. */
2590 {ARM_FEATURE_COPROC (FPU_MVE
),
2591 MVE_VMOV2_VEC_LANE_TO_GP
,
2592 0xec000f00, 0xffb01ff0,
2593 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[2], %13-15,22Q[0]"},
2595 /* Vector VMOV two 32-bit lanes to two gprs, idx = 1. */
2596 {ARM_FEATURE_COPROC (FPU_MVE
),
2597 MVE_VMOV2_VEC_LANE_TO_GP
,
2598 0xec000f10, 0xffb01ff0,
2599 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[3], %13-15,22Q[1]"},
2601 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 0. */
2602 {ARM_FEATURE_COPROC (FPU_MVE
),
2603 MVE_VMOV2_GP_TO_VEC_LANE
,
2604 0xec100f00, 0xffb01ff0,
2605 "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
2607 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 1. */
2608 {ARM_FEATURE_COPROC (FPU_MVE
),
2609 MVE_VMOV2_GP_TO_VEC_LANE
,
2610 0xec100f10, 0xffb01ff0,
2611 "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
2613 /* Vector VMOV Vector lane to gpr. */
2614 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2615 MVE_VMOV_VEC_LANE_TO_GP
,
2616 0xee100b10, 0xff100f1f,
2617 "vmov%c.%u%5-6,21-22s\t%12-15r, %17-19,7Q[%N]"},
2619 /* Vector VSHLL T1 Variant. Note: VSHLL T1 must appear before MVE_VMOVL due
2620 to instruction opcode aliasing. */
2621 {ARM_FEATURE_COPROC (FPU_MVE
),
2623 0xeea00f40, 0xefa00fd1,
2624 "vshll%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2626 /* Vector VMOVL long. */
2627 {ARM_FEATURE_COPROC (FPU_MVE
),
2629 0xeea00f40, 0xefa70fd1,
2630 "vmovl%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q"},
2632 /* Vector VMOV and narrow. */
2633 {ARM_FEATURE_COPROC (FPU_MVE
),
2635 0xfe310e81, 0xffb30fd1,
2636 "vmovn%T%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2638 /* Floating point move extract. */
2639 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2641 0xfeb00a40, 0xffbf0fd0,
2642 "vmovx.f16\t%22,12-15F, %5,0-3F"},
2644 /* Vector VMULL integer. */
2645 {ARM_FEATURE_COPROC (FPU_MVE
),
2647 0xee010e00, 0xef810f51,
2648 "vmull%T%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2650 /* Vector VMULL polynomial. */
2651 {ARM_FEATURE_COPROC (FPU_MVE
),
2653 0xee310e00, 0xefb10f51,
2654 "vmull%T%v.%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2656 /* Vector VMVN immediate to vector. */
2657 {ARM_FEATURE_COPROC (FPU_MVE
),
2659 0xef800070, 0xefb810f0,
2660 "vmvn%v.i%8-11s\t%13-15,22Q, %E"},
2662 /* Vector VMVN register. */
2663 {ARM_FEATURE_COPROC (FPU_MVE
),
2665 0xffb005c0, 0xffbf1fd1,
2666 "vmvn%v\t%13-15,22Q, %1-3,5Q"},
2668 /* Vector VORN, vector bitwise or not. */
2669 {ARM_FEATURE_COPROC (FPU_MVE
),
2671 0xef300150, 0xffb11f51,
2672 "vorn%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2674 /* Vector VORR register. */
2675 {ARM_FEATURE_COPROC (FPU_MVE
),
2677 0xef200150, 0xffb11f51,
2678 "vorr%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2680 /* Vector VQDMULL T1 variant. */
2681 {ARM_FEATURE_COPROC (FPU_MVE
),
2683 0xee300f01, 0xefb10f51,
2684 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2686 /* Vector VQDMULL T2 variant. */
2687 {ARM_FEATURE_COPROC (FPU_MVE
),
2689 0xee300f60, 0xefb10f70,
2690 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2692 /* Vector VQMOVN. */
2693 {ARM_FEATURE_COPROC (FPU_MVE
),
2695 0xee330e01, 0xefb30fd1,
2696 "vqmovn%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q"},
2698 /* Vector VQMOVUN. */
2699 {ARM_FEATURE_COPROC (FPU_MVE
),
2701 0xee310e81, 0xffb30fd1,
2702 "vqmovun%T%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2704 /* Vector VQDMLADH. */
2705 {ARM_FEATURE_COPROC (FPU_MVE
),
2707 0xee000e00, 0xff810f51,
2708 "vqdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2710 /* Vector VQRDMLADH. */
2711 {ARM_FEATURE_COPROC (FPU_MVE
),
2713 0xee000e01, 0xff810f51,
2714 "vqrdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2716 /* Vector VQDMLAH. */
2717 {ARM_FEATURE_COPROC (FPU_MVE
),
2719 0xee000e60, 0xef811f70,
2720 "vqdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2722 /* Vector VQRDMLAH. */
2723 {ARM_FEATURE_COPROC (FPU_MVE
),
2725 0xee000e40, 0xef811f70,
2726 "vqrdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2728 /* Vector VQDMLASH. */
2729 {ARM_FEATURE_COPROC (FPU_MVE
),
2731 0xee001e60, 0xef811f70,
2732 "vqdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2734 /* Vector VQRDMLASH. */
2735 {ARM_FEATURE_COPROC (FPU_MVE
),
2737 0xee001e40, 0xef811f70,
2738 "vqrdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2740 /* Vector VQDMLSDH. */
2741 {ARM_FEATURE_COPROC (FPU_MVE
),
2743 0xfe000e00, 0xff810f51,
2744 "vqdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2746 /* Vector VQRDMLSDH. */
2747 {ARM_FEATURE_COPROC (FPU_MVE
),
2749 0xfe000e01, 0xff810f51,
2750 "vqrdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2752 /* Vector VQDMULH T1 variant. */
2753 {ARM_FEATURE_COPROC (FPU_MVE
),
2755 0xef000b40, 0xff811f51,
2756 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2758 /* Vector VQRDMULH T2 variant. */
2759 {ARM_FEATURE_COPROC (FPU_MVE
),
2761 0xff000b40, 0xff811f51,
2762 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2764 /* Vector VQDMULH T3 variant. */
2765 {ARM_FEATURE_COPROC (FPU_MVE
),
2767 0xee010e60, 0xff811f70,
2768 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2770 /* Vector VQRDMULH T4 variant. */
2771 {ARM_FEATURE_COPROC (FPU_MVE
),
2773 0xfe010e60, 0xff811f70,
2774 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2776 /* Vector VQRSHL T1 variant. */
2777 {ARM_FEATURE_COPROC (FPU_MVE
),
2779 0xef000550, 0xef811f51,
2780 "vqrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
2782 /* Vector VQRSHL T2 variant. */
2783 {ARM_FEATURE_COPROC (FPU_MVE
),
2785 0xee331ee0, 0xefb31ff0,
2786 "vqrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
2788 /* Vector VQRSHRN. */
2789 {ARM_FEATURE_COPROC (FPU_MVE
),
2791 0xee800f41, 0xefa00fd1,
2792 "vqrshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2794 /* Vector VQRSHRUN. */
2795 {ARM_FEATURE_COPROC (FPU_MVE
),
2797 0xfe800fc0, 0xffa00fd1,
2798 "vqrshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2800 /* Vector VQSHL T1 Variant. */
2801 {ARM_FEATURE_COPROC (FPU_MVE
),
2803 0xee311ee0, 0xefb31ff0,
2804 "vqshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
2806 /* Vector VQSHL T4 Variant. */
2807 {ARM_FEATURE_COPROC (FPU_MVE
),
2809 0xef000450, 0xef811f51,
2810 "vqshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
2812 /* Vector VQSHRN. */
2813 {ARM_FEATURE_COPROC (FPU_MVE
),
2815 0xee800f40, 0xefa00fd1,
2816 "vqshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2818 /* Vector VQSHRUN. */
2819 {ARM_FEATURE_COPROC (FPU_MVE
),
2821 0xee800fc0, 0xffa00fd1,
2822 "vqshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2824 /* Vector VRINT floating point. */
2825 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2827 0xffb20440, 0xffb31c51,
2828 "vrint%m%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
2830 /* Vector VRMLALDAVH. */
2831 {ARM_FEATURE_COPROC (FPU_MVE
),
2833 0xee800f00, 0xef811f51,
2834 "vrmlalvh%5A%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2836 /* Vector VRMLALDAVH. */
2837 {ARM_FEATURE_COPROC (FPU_MVE
),
2839 0xee801f00, 0xef811f51,
2840 "vrmlaldavh%5Ax%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2842 /* Vector VRSHL T1 Variant. */
2843 {ARM_FEATURE_COPROC (FPU_MVE
),
2845 0xef000540, 0xef811f51,
2846 "vrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
2848 /* Vector VRSHL T2 Variant. */
2849 {ARM_FEATURE_COPROC (FPU_MVE
),
2851 0xee331e60, 0xefb31ff0,
2852 "vrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
2854 /* Vector VRSHRN. */
2855 {ARM_FEATURE_COPROC (FPU_MVE
),
2857 0xfe800fc1, 0xffa00fd1,
2858 "vrshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2861 {ARM_FEATURE_COPROC (FPU_MVE
),
2863 0xfe300f00, 0xffb10f51,
2864 "vsbc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2866 /* Vector VSHL T2 Variant. */
2867 {ARM_FEATURE_COPROC (FPU_MVE
),
2869 0xee311e60, 0xefb31ff0,
2870 "vshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
2872 /* Vector VSHL T3 Variant. */
2873 {ARM_FEATURE_COPROC (FPU_MVE
),
2875 0xef000440, 0xef811f51,
2876 "vshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
2879 {ARM_FEATURE_COPROC (FPU_MVE
),
2881 0xeea00fc0, 0xffa01ff0,
2882 "vshlc%v\t%13-15,22Q, %0-3r, #%16-20d"},
2884 /* Vector VSHLL T2 Variant. */
2885 {ARM_FEATURE_COPROC (FPU_MVE
),
2887 0xee310e01, 0xefb30fd1,
2888 "vshll%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q, #%18-19d"},
2891 {ARM_FEATURE_COPROC (FPU_MVE
),
2893 0xee800fc1, 0xffa00fd1,
2894 "vshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2896 /* Vector VST2 no writeback. */
2897 {ARM_FEATURE_COPROC (FPU_MVE
),
2899 0xfc801e00, 0xffb01e5f,
2900 "vst2%5d.%7-8s\t%B, [%16-19r]"},
2902 /* Vector VST2 writeback. */
2903 {ARM_FEATURE_COPROC (FPU_MVE
),
2905 0xfca01e00, 0xffb01e5f,
2906 "vst2%5d.%7-8s\t%B, [%16-19r]!"},
2908 /* Vector VST4 no writeback. */
2909 {ARM_FEATURE_COPROC (FPU_MVE
),
2911 0xfc801e01, 0xffb01e1f,
2912 "vst4%5-6d.%7-8s\t%B, [%16-19r]"},
2914 /* Vector VST4 writeback. */
2915 {ARM_FEATURE_COPROC (FPU_MVE
),
2917 0xfca01e01, 0xffb01e1f,
2918 "vst4%5-6d.%7-8s\t%B, [%16-19r]!"},
2920 /* Vector VSTRB scatter store, T1 variant. */
2921 {ARM_FEATURE_COPROC (FPU_MVE
),
2922 MVE_VSTRB_SCATTER_T1
,
2923 0xec800e00, 0xffb01e50,
2924 "vstrb%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
2926 /* Vector VSTRH scatter store, T2 variant. */
2927 {ARM_FEATURE_COPROC (FPU_MVE
),
2928 MVE_VSTRH_SCATTER_T2
,
2929 0xec800e10, 0xffb01e50,
2930 "vstrh%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2932 /* Vector VSTRW scatter store, T3 variant. */
2933 {ARM_FEATURE_COPROC (FPU_MVE
),
2934 MVE_VSTRW_SCATTER_T3
,
2935 0xec800e40, 0xffb01e50,
2936 "vstrw%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2938 /* Vector VSTRD scatter store, T4 variant. */
2939 {ARM_FEATURE_COPROC (FPU_MVE
),
2940 MVE_VSTRD_SCATTER_T4
,
2941 0xec800fd0, 0xffb01fd0,
2942 "vstrd%v.64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2944 /* Vector VSTRW scatter store, T5 variant. */
2945 {ARM_FEATURE_COPROC (FPU_MVE
),
2946 MVE_VSTRW_SCATTER_T5
,
2947 0xfd001e00, 0xff111f00,
2948 "vstrw%v.32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2950 /* Vector VSTRD scatter store, T6 variant. */
2951 {ARM_FEATURE_COPROC (FPU_MVE
),
2952 MVE_VSTRD_SCATTER_T6
,
2953 0xfd001f00, 0xff111f00,
2954 "vstrd%v.64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2957 {ARM_FEATURE_COPROC (FPU_MVE
),
2959 0xec000e00, 0xfe581e00,
2960 "vstrb%v.%7-8s\t%13-15Q, %d"},
2963 {ARM_FEATURE_COPROC (FPU_MVE
),
2965 0xec080e00, 0xfe581e00,
2966 "vstrh%v.%7-8s\t%13-15Q, %d"},
2968 /* Vector VSTRB variant T5. */
2969 {ARM_FEATURE_COPROC (FPU_MVE
),
2971 0xec001e00, 0xfe101f80,
2972 "vstrb%v.8\t%13-15,22Q, %d"},
2974 /* Vector VSTRH variant T6. */
2975 {ARM_FEATURE_COPROC (FPU_MVE
),
2977 0xec001e80, 0xfe101f80,
2978 "vstrh%v.16\t%13-15,22Q, %d"},
2980 /* Vector VSTRW variant T7. */
2981 {ARM_FEATURE_COPROC (FPU_MVE
),
2983 0xec001f00, 0xfe101f80,
2984 "vstrw%v.32\t%13-15,22Q, %d"},
2986 /* Vector VSUB floating point T1 variant. */
2987 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2989 0xef200d40, 0xffa11f51,
2990 "vsub%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2992 /* Vector VSUB floating point T2 variant. */
2993 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2995 0xee301f40, 0xefb11f70,
2996 "vsub%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2998 /* Vector VSUB T1 variant. */
2999 {ARM_FEATURE_COPROC (FPU_MVE
),
3001 0xff000840, 0xff811f51,
3002 "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3004 /* Vector VSUB T2 variant. */
3005 {ARM_FEATURE_COPROC (FPU_MVE
),
3007 0xee011f40, 0xff811f70,
3008 "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3010 {ARM_FEATURE_CORE_LOW (0),
3012 0x00000000, 0x00000000, 0}
3015 /* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
3016 ordered: they must be searched linearly from the top to obtain a correct
3019 /* print_insn_arm recognizes the following format control codes:
3023 %a print address for ldr/str instruction
3024 %s print address for ldr/str halfword/signextend instruction
3025 %S like %s but allow UNPREDICTABLE addressing
3026 %b print branch destination
3027 %c print condition code (always bits 28-31)
3028 %m print register mask for ldm/stm instruction
3029 %o print operand2 (immediate or register + shift)
3030 %p print 'p' iff bits 12-15 are 15
3031 %t print 't' iff bit 21 set and bit 24 clear
3032 %B print arm BLX(1) destination
3033 %C print the PSR sub type.
3034 %U print barrier type.
3035 %P print address for pli instruction.
3037 %<bitfield>r print as an ARM register
3038 %<bitfield>T print as an ARM register + 1
3039 %<bitfield>R as %r but r15 is UNPREDICTABLE
3040 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
3041 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
3042 %<bitfield>d print the bitfield in decimal
3043 %<bitfield>W print the bitfield plus one in decimal
3044 %<bitfield>x print the bitfield in hex
3045 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
3047 %<bitfield>'c print specified char iff bitfield is all ones
3048 %<bitfield>`c print specified char iff bitfield is all zeroes
3049 %<bitfield>?ab... select from array of values in big endian order
3051 %e print arm SMI operand (bits 0..7,8..19).
3052 %E print the LSB and WIDTH fields of a BFI or BFC instruction.
3053 %V print the 16-bit immediate field of a MOVT or MOVW instruction.
3054 %R print the SPSR/CPSR or banked register of an MRS. */
3056 static const struct opcode32 arm_opcodes
[] =
3058 /* ARM instructions. */
3059 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3060 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
3061 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3062 0xe7f000f0, 0xfff000f0, "udf\t#%e"},
3064 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
),
3065 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
3066 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
3067 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
3068 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
3069 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3070 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
),
3071 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
3072 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
),
3073 0x00800090, 0x0fa000f0,
3074 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3075 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
),
3076 0x00a00090, 0x0fa000f0,
3077 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3079 /* V8.2 RAS extension instructions. */
3080 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
3081 0xe320f010, 0xffffffff, "esb"},
3083 /* V8 instructions. */
3084 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3085 0x0320f005, 0x0fffffff, "sevl"},
3086 /* Defined in V8 but is in NOP space so available to all arch. */
3087 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3088 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
3089 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
),
3090 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
3091 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3092 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
3093 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3094 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
3095 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3096 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
3097 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3098 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
3099 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3100 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
3101 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3102 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
3103 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3104 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
3105 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3106 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
3107 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3108 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
3109 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3110 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
3111 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3112 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
3113 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3114 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
3115 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3116 0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
3117 /* CRC32 instructions. */
3118 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
3119 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
3120 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
3121 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
3122 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
3123 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
3124 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
3125 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
3126 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
3127 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
3128 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
3129 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
3131 /* Privileged Access Never extension instructions. */
3132 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
3133 0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
3135 /* Virtualization Extension instructions. */
3136 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
), 0x0160006e, 0x0fffffff, "eret%c"},
3137 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
3139 /* Integer Divide Extension instructions. */
3140 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
3141 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
3142 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
3143 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
3145 /* MP Extension instructions. */
3146 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP
), 0xf410f000, 0xfc70f000, "pldw\t%a"},
3148 /* Speculation Barriers. */
3149 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
), 0xe320f014, 0xffffffff, "csdb"},
3150 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
), 0xf57ff040, 0xffffffff, "ssbb"},
3151 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
), 0xf57ff044, 0xffffffff, "pssbb"},
3153 /* V7 instructions. */
3154 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf450f000, 0xfd70f000, "pli\t%P"},
3155 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
3156 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
3157 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
3158 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
3159 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
3160 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf57ff060, 0xfffffff0, "isb\t%U"},
3161 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
),
3162 0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
3164 /* ARM V6T2 instructions. */
3165 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3166 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
3167 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3168 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
3169 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3170 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3171 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3172 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
3174 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3175 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION
},
3176 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3177 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
3179 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3180 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
3181 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3182 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
3183 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3184 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
3185 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3186 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
3188 /* ARM Security extension instructions. */
3189 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
3190 0x01600070, 0x0ff000f0, "smc%c\t%e"},
3192 /* ARM V6K instructions. */
3193 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3194 0xf57ff01f, 0xffffffff, "clrex"},
3195 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3196 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
3197 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3198 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
3199 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3200 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
3201 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3202 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
3203 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3204 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
3205 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3206 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
3208 /* ARMv8.5-A instructions. */
3209 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
), 0xf57ff070, 0xffffffff, "sb"},
3211 /* ARM V6K NOP hints. */
3212 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3213 0x0320f001, 0x0fffffff, "yield%c"},
3214 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3215 0x0320f002, 0x0fffffff, "wfe%c"},
3216 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3217 0x0320f003, 0x0fffffff, "wfi%c"},
3218 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3219 0x0320f004, 0x0fffffff, "sev%c"},
3220 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3221 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
3223 /* ARM V6 instructions. */
3224 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3225 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
3226 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3227 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
3228 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3229 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
3230 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3231 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
3232 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3233 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
3234 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3235 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
3236 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3237 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
3238 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3239 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
3240 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3241 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
3242 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3243 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
3244 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3245 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
3246 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3247 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
3248 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3249 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
3250 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3251 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
3252 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3253 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
3254 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3255 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
3256 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3257 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
3258 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3259 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
3260 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3261 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
3262 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3263 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
3264 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3265 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
3266 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3267 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
3268 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3269 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
3270 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3271 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
3272 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3273 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
3274 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3275 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
3276 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3277 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
3278 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3279 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
3280 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3281 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
3282 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3283 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
3284 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3285 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
3286 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3287 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
3288 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3289 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
3290 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3291 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
3292 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3293 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
3294 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3295 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
3296 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3297 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
3298 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3299 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
3300 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3301 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
3302 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3303 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
3304 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3305 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
3306 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3307 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
3308 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3309 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
3310 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3311 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
3312 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3313 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
3314 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3315 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
3316 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3317 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
3318 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3319 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
3320 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3321 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
3322 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3323 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
3324 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3325 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
3326 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3327 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
3328 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3329 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
3330 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3331 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
3332 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3333 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
3334 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3335 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
3336 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3337 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
3338 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3339 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
3340 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3341 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
3342 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3343 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
3344 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3345 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
3346 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3347 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
3348 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3349 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
3350 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3351 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
3352 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3353 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
3354 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3355 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
3356 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3357 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
3358 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3359 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
3360 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3361 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
3362 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3363 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
3364 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3365 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
3366 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3367 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
3368 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3369 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
3370 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3371 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
3372 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3373 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
3374 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3375 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3376 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3377 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3378 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3379 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3380 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3381 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
3382 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3383 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3384 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3385 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3386 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3387 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3388 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3389 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
3390 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3391 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3392 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3393 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3394 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3395 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3396 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3397 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
3398 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3399 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3400 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3401 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3402 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3403 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3404 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3405 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
3406 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3407 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3408 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3409 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3410 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3411 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
3412 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3413 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
3414 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3415 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3416 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3417 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3418 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3419 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3420 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3421 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
3422 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3423 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
3424 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3425 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
3426 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3427 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
3428 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3429 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3430 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3431 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3432 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3433 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3434 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3435 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3436 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3437 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
3438 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3439 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3440 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3441 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3442 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3443 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
3444 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3445 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
3446 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3447 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
3448 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3449 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
3450 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3451 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
3452 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3453 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
3454 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3455 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
3456 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3457 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
3458 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3459 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3460 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3461 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
3462 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3463 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
3464 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3465 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
3466 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3467 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
3469 /* V5J instruction. */
3470 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
),
3471 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
3473 /* V5 Instructions. */
3474 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
3475 0xe1200070, 0xfff000f0,
3476 "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
3477 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
3478 0xfa000000, 0xfe000000, "blx\t%B"},
3479 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
3480 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
3481 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
3482 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
3484 /* V5E "El Segundo" Instructions. */
3485 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
3486 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
3487 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
3488 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
3489 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
3490 0xf450f000, 0xfc70f000, "pld\t%a"},
3491 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3492 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3493 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3494 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3495 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3496 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3497 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3498 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
3500 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3501 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3502 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3503 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
3505 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3506 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3507 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3508 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3509 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3510 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3511 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3512 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3514 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3515 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
3516 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3517 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
3518 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3519 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
3520 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3521 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
3523 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3524 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
3525 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3526 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
3528 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3529 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"},
3530 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3531 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
3532 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3533 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"},
3534 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3535 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
3537 /* ARM Instructions. */
3538 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3539 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
3541 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3542 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
3543 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3544 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
3545 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3546 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
3547 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3548 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
3549 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3550 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
3551 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3552 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
3554 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3555 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
3556 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3557 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
3558 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3559 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
3560 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3561 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
3563 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3564 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION
},
3565 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3566 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
3567 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3568 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION
},
3569 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3570 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
3572 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3573 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
3574 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3575 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
3576 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3577 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
3579 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3580 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
3581 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3582 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
3583 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3584 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
3586 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3587 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
3588 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3589 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
3590 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3591 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
3593 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3594 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
3595 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3596 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
3597 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3598 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
3600 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3601 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
3602 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3603 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
3604 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3605 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
3607 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3608 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
3609 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3610 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
3611 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3612 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
3614 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3615 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
3616 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3617 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
3618 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3619 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
3621 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3622 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
3623 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3624 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
3625 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3626 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
3628 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
3629 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
3630 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
),
3631 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
3632 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
),
3633 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
3635 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3636 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
3637 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3638 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
3639 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3640 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
3642 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3643 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
3644 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3645 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
3646 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3647 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
3649 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3650 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
3651 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3652 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
3653 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3654 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
3656 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3657 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
3658 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3659 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
3660 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3661 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
3663 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3664 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
3665 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3666 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
3667 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3668 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
3670 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3671 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
3672 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3673 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
3674 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3675 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
3676 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3677 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
3678 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3679 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
3680 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3681 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
3682 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3683 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
3685 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3686 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
3687 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3688 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
3689 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3690 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
3692 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3693 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
3694 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3695 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
3696 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3697 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
3699 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3700 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION
},
3701 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3702 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
3704 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3705 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
3707 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3708 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
3709 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3710 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
3712 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3713 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3714 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3715 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3716 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3717 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3718 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3719 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3720 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3721 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3722 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3723 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3724 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3725 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3726 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3727 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3728 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3729 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3730 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3731 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3732 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3733 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3734 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3735 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3736 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3737 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3738 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3739 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3740 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3741 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3742 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3743 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3744 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3745 0x092d0000, 0x0fff0000, "push%c\t%m"},
3746 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3747 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
3748 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3749 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
3751 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3752 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3753 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3754 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3755 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3756 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3757 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3758 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3759 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3760 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3761 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3762 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3763 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3764 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3765 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3766 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3767 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3768 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3769 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3770 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3771 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3772 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3773 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3774 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3775 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3776 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3777 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3778 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3779 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3780 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3781 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3782 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3783 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3784 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
3785 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3786 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
3787 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3788 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
3790 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3791 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
3792 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3793 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
3796 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
),
3797 0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION
},
3798 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3799 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION
},
3800 {ARM_FEATURE_CORE_LOW (0),
3801 0x00000000, 0x00000000, 0}
3804 /* print_insn_thumb16 recognizes the following format control codes:
3806 %S print Thumb register (bits 3..5 as high number if bit 6 set)
3807 %D print Thumb register (bits 0..2 as high number if bit 7 set)
3808 %<bitfield>I print bitfield as a signed decimal
3809 (top bit of range being the sign bit)
3810 %N print Thumb register mask (with LR)
3811 %O print Thumb register mask (with PC)
3812 %M print Thumb register mask
3813 %b print CZB's 6-bit unsigned branch destination
3814 %s print Thumb right-shift immediate (6..10; 0 == 32).
3815 %c print the condition code
3816 %C print the condition code, or "s" if not conditional
3817 %x print warning if conditional an not at end of IT block"
3818 %X print "\t; unpredictable <IT:code>" if conditional
3819 %I print IT instruction suffix and operands
3820 %W print Thumb Writeback indicator for LDMIA
3821 %<bitfield>r print bitfield as an ARM register
3822 %<bitfield>d print bitfield as a decimal
3823 %<bitfield>H print (bitfield * 2) as a decimal
3824 %<bitfield>W print (bitfield * 4) as a decimal
3825 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
3826 %<bitfield>B print Thumb branch destination (signed displacement)
3827 %<bitfield>c print bitfield as a condition code
3828 %<bitnum>'c print specified char iff bit is one
3829 %<bitnum>?ab print a if bit is one else print b. */
3831 static const struct opcode16 thumb_opcodes
[] =
3833 /* Thumb instructions. */
3835 /* ARMv8-M Security Extensions instructions. */
3836 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
), 0x4784, 0xff87, "blxns\t%3-6r"},
3837 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
), 0x4704, 0xff87, "bxns\t%3-6r"},
3839 /* ARM V8 instructions. */
3840 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xbf50, 0xffff, "sevl%c"},
3841 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xba80, 0xffc0, "hlt\t%0-5x"},
3842 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
), 0xb610, 0xfff7, "setpan\t#%3-3d"},
3844 /* ARM V6K no-argument instructions. */
3845 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf00, 0xffff, "nop%c"},
3846 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf10, 0xffff, "yield%c"},
3847 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf20, 0xffff, "wfe%c"},
3848 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf30, 0xffff, "wfi%c"},
3849 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf40, 0xffff, "sev%c"},
3850 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
3852 /* ARM V6T2 instructions. */
3853 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3854 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
3855 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3856 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
3857 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xbf00, 0xff00, "it%I%X"},
3860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
3861 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
3862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
3863 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
3864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
3865 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
3866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb650, 0xfff7, "setend\t%3?ble%X"},
3867 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
3868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
3869 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
3870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
3872 /* ARM V5 ISA extends Thumb. */
3873 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
),
3874 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
3875 /* This is BLX(2). BLX(1) is a 32-bit instruction. */
3876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
),
3877 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
3878 /* ARM V4T ISA (Thumb v1). */
3879 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3880 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
3882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
3883 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
3884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
3885 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
3886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
3887 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
3888 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
3889 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
3890 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
3891 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
3892 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
3893 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
3894 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
3895 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
3896 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
3897 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
3899 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
3900 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
3902 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4700, 0xFF80, "bx%c\t%S%x"},
3903 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4400, 0xFF00, "add%c\t%D, %S"},
3904 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
3905 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4600, 0xFF00, "mov%c\t%D, %S"},
3907 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xB400, 0xFE00, "push%c\t%N"},
3908 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xBC00, 0xFE00, "pop%c\t%O"},
3910 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3911 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
3912 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3913 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
3914 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3915 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
3916 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3917 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
3919 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3920 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
3921 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3922 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
3923 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3924 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
3926 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3927 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
3928 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3929 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
3931 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
3932 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3933 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
3934 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
3935 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
3937 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
3938 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
3939 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
3940 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
3942 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
3943 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3945 "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
3947 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3948 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
3949 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3950 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
3951 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3952 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
3953 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3954 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
3956 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3957 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
3958 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3959 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
3961 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3962 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
3963 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3964 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
3966 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3967 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
3968 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3969 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
3971 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
3972 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
3974 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
3976 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
3977 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION
},
3978 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
3980 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
3982 /* The E800 .. FFFF range is unconditionally redirected to the
3983 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
3984 are processed via that table. Thus, we can never encounter a
3985 bare "second half of BL/BLX(1)" instruction here. */
3986 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
), 0x0000, 0x0000, UNDEFINED_INSTRUCTION
},
3987 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
3990 /* Thumb32 opcodes use the same table structure as the ARM opcodes.
3991 We adopt the convention that hw1 is the high 16 bits of .value and
3992 .mask, hw2 the low 16 bits.
3994 print_insn_thumb32 recognizes the following format control codes:
3998 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
3999 %M print a modified 12-bit immediate (same location)
4000 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
4001 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
4002 %H print a 16-bit immediate from hw2[3:0],hw1[11:0]
4003 %S print a possibly-shifted Rm
4005 %L print address for a ldrd/strd instruction
4006 %a print the address of a plain load/store
4007 %w print the width and signedness of a core load/store
4008 %m print register mask for ldm/stm
4009 %n print register mask for clrm
4011 %E print the lsb and width fields of a bfc/bfi instruction
4012 %F print the lsb and width fields of a sbfx/ubfx instruction
4013 %G print a fallback offset for Branch Future instructions
4014 %W print an offset for BF instruction
4015 %Y print an offset for BFL instruction
4016 %Z print an offset for BFCSEL instruction
4017 %Q print an offset for Low Overhead Loop instructions
4018 %P print an offset for Low Overhead Loop end instructions
4019 %b print a conditional branch offset
4020 %B print an unconditional branch offset
4021 %s print the shift field of an SSAT instruction
4022 %R print the rotation field of an SXT instruction
4023 %U print barrier type.
4024 %P print address for pli instruction.
4025 %c print the condition code
4026 %x print warning if conditional an not at end of IT block"
4027 %X print "\t; unpredictable <IT:code>" if conditional
4029 %<bitfield>d print bitfield in decimal
4030 %<bitfield>D print bitfield plus one in decimal
4031 %<bitfield>W print bitfield*4 in decimal
4032 %<bitfield>r print bitfield as an ARM register
4033 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
4034 %<bitfield>S as %<>r but r13 and r15 is UNPREDICTABLE
4035 %<bitfield>c print bitfield as a condition code
4037 %<bitfield>'c print specified char iff bitfield is all ones
4038 %<bitfield>`c print specified char iff bitfield is all zeroes
4039 %<bitfield>?ab... select from array of values in big endian order
4041 With one exception at the bottom (done because BL and BLX(1) need
4042 to come dead last), this table was machine-sorted first in
4043 decreasing order of number of bits set in the mask, then in
4044 increasing numeric order of mask, then in increasing numeric order
4045 of opcode. This order is not the clearest for a human reader, but
4046 is guaranteed never to catch a special-case bit pattern with a more
4047 general mask, which is important, because this instruction encoding
4048 makes heavy use of special-case bit patterns. */
4049 static const struct opcode32 thumb32_opcodes
[] =
4051 /* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions
4053 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4054 0xf00fe001, 0xffffffff, "lctp%c"},
4055 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4056 0xf02fc001, 0xfffff001, "le\t%P"},
4057 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4058 0xf00fc001, 0xfffff001, "le\tlr, %P"},
4059 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4060 0xf01fc001, 0xfffff001, "letp\tlr, %P"},
4061 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4062 0xf040c001, 0xfff0f001, "wls\tlr, %16-19S, %Q"},
4063 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4064 0xf000c001, 0xffc0f001, "wlstp.%20-21s\tlr, %16-19S, %Q"},
4065 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4066 0xf040e001, 0xfff0ffff, "dls\tlr, %16-19S"},
4067 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4068 0xf000e001, 0xffc0ffff, "dlstp.%20-21s\tlr, %16-19S"},
4070 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4071 0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
4072 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4073 0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"},
4074 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4075 0xf000c001, 0xf800f001, "bfl%c\t%G, %Y"},
4076 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4077 0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"},
4078 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4079 0xf000e001, 0xf840f001, "bfcsel\t%G, %Z, %18-21c"},
4081 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4082 0xe89f0000, 0xffff2000, "clrm%c\t%n"},
4084 /* ARMv8-M and ARMv8-M Security Extensions instructions. */
4085 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
), 0xe97fe97f, 0xffffffff, "sg"},
4086 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
),
4087 0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
4088 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
),
4089 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
4090 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
),
4091 0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
4092 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
),
4093 0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
4095 /* ARM V8.2 RAS extension instructions. */
4096 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
4097 0xf3af8010, 0xffffffff, "esb"},
4099 /* V8 instructions. */
4100 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4101 0xf3af8005, 0xffffffff, "sevl%c.w"},
4102 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4103 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
4104 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4105 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
4106 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4107 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
4108 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4109 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
4110 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4111 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
4112 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4113 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
4114 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4115 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
4116 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4117 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
4118 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4119 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
4120 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4121 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
4122 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4123 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
4124 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4125 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
4126 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4127 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
4128 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4129 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
4130 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4131 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
4133 /* CRC32 instructions. */
4134 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
4135 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},
4136 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
4137 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"},
4138 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
4139 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"},
4140 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
4141 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"},
4142 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
4143 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"},
4144 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
4145 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
4147 /* Speculation Barriers. */
4148 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8014, 0xffffffff, "csdb"},
4149 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3bf8f40, 0xffffffff, "ssbb"},
4150 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3bf8f44, 0xffffffff, "pssbb"},
4152 /* V7 instructions. */
4153 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf910f000, 0xff70f000, "pli%c\t%a"},
4154 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
4155 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
4156 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
4157 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
4158 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
4159 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
4160 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
4161 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
4162 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
4163 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
4165 /* Virtualization Extension instructions. */
4166 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
4167 /* We skip ERET as that is SUBS pc, lr, #0. */
4169 /* MP Extension instructions. */
4170 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP
), 0xf830f000, 0xff70f000, "pldw%c\t%a"},
4172 /* Security extension instructions. */
4173 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
), 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
4175 /* ARMv8.5-A instructions. */
4176 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
), 0xf3bf8f70, 0xffffffff, "sb"},
4178 /* Instructions defined in the basic V6T2 set. */
4179 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8000, 0xffffffff, "nop%c.w"},
4180 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8001, 0xffffffff, "yield%c.w"},
4181 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8002, 0xffffffff, "wfe%c.w"},
4182 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8003, 0xffffffff, "wfi%c.w"},
4183 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8004, 0xffffffff, "sev%c.w"},
4184 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4185 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
4186 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
4188 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4189 0xf3bf8f2f, 0xffffffff, "clrex%c"},
4190 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4191 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
4192 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4193 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
4194 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4195 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
4196 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4197 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
4198 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4199 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
4200 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4201 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
4202 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4203 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
4204 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4205 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
4206 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4207 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
4208 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4209 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
4210 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4211 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
4212 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4213 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
4214 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4215 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
4216 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4217 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
4218 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4219 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
4220 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4221 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
4222 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4223 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
4224 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4225 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
4226 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4227 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
4228 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4229 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
4230 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4231 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
4232 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4233 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
4234 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4235 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
4236 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4237 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
4238 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4239 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
4240 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4241 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
4242 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4243 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
4244 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4245 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
4246 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4247 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
4248 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4249 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
4250 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4251 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
4252 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4253 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
4254 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4255 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
4256 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4257 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
4258 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4259 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
4260 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4261 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
4262 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4263 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
4264 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4265 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
4266 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4267 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
4268 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4269 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
4270 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4271 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
4272 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4273 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
4274 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4275 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
4276 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4277 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
4278 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4279 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
4280 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4281 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
4282 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4283 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
4284 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4285 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
4286 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4287 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
4288 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4289 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
4290 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4291 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
4292 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4293 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
4294 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4295 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
4296 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4297 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
4298 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4299 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
4300 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4301 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
4302 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4303 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
4304 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4305 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
4306 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4307 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
4308 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4309 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
4310 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4311 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
4312 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4313 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
4314 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4315 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
4316 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4317 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
4318 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4319 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
4320 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4321 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
4322 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4323 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
4324 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4325 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
4326 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4327 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
4328 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4329 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
4330 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4331 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
4332 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4333 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
4334 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4335 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
4336 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4337 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4338 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4339 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4340 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4341 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4342 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4343 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
4344 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4345 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
4346 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4347 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
4348 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4349 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
4350 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4351 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
4352 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4353 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4354 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4355 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
4356 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4357 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
4358 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4359 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4360 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4361 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4362 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4363 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4364 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4365 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4366 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4367 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4368 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4369 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4370 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4371 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4372 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4373 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
4374 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4375 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
4376 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4377 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
4378 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4379 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
4380 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4381 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
4382 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4383 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
4384 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4385 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
4386 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4387 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
4388 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4389 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
4390 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4391 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
4392 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4393 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
4394 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4395 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
4396 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4397 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4398 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4399 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4400 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4401 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4402 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4403 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4404 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4405 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4406 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4407 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4408 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4409 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4410 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4411 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4412 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4413 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
4414 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4415 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
4416 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4417 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
4418 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4419 0xf810f000, 0xff70f000, "pld%c\t%a"},
4420 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4421 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4422 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4423 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4424 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4425 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4426 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4427 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4428 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4429 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4430 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4431 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4432 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4433 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4434 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4435 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
4436 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4437 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
4438 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4439 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
4440 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4441 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
4442 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4443 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
4444 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4445 0xfb100000, 0xfff000c0,
4446 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4447 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4448 0xfbc00080, 0xfff000c0,
4449 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
4450 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4451 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
4452 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4453 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
4454 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4455 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
4456 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4457 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
4458 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4459 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
4460 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4461 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
4462 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4463 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
4464 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4465 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
4466 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4467 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
4468 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4469 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
4470 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4471 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
4472 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4473 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
4474 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4475 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
4476 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4477 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
4478 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4479 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
4480 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4481 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
4482 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4483 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
4484 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4485 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
4486 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4487 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
4488 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4489 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
4490 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4491 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
4492 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4493 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
4494 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4495 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
4496 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4497 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
4498 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4499 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
4500 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4501 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
4502 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4503 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
4504 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4505 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
4506 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4507 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
4508 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4509 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
4510 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4511 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
4512 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4513 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
4514 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4515 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
4516 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4517 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
4518 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4519 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
4520 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4521 0xe9400000, 0xff500000,
4522 "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
4523 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4524 0xe9500000, 0xff500000,
4525 "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
4526 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4527 0xe8600000, 0xff700000,
4528 "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
4529 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4530 0xe8700000, 0xff700000,
4531 "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
4532 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4533 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
4534 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4535 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
4537 /* Filter out Bcc with cond=E or F, which are used for other instructions. */
4538 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4539 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
4540 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4541 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
4542 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4543 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
4544 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4545 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
4547 /* These have been 32-bit since the invention of Thumb. */
4548 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4549 0xf000c000, 0xf800d001, "blx%c\t%B%x"},
4550 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4551 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
4554 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4555 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION
},
4556 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
4559 static const char *const arm_conditional
[] =
4560 {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
4561 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
4563 static const char *const arm_fp_const
[] =
4564 {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
4566 static const char *const arm_shift
[] =
4567 {"lsl", "lsr", "asr", "ror"};
4572 const char *description
;
4573 const char *reg_names
[16];
4577 static const arm_regname regnames
[] =
4579 { "reg-names-raw", N_("Select raw register names"),
4580 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
4581 { "reg-names-gcc", N_("Select register names used by GCC"),
4582 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
4583 { "reg-names-std", N_("Select register names used in ARM's ISA documentation"),
4584 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
4585 { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL
} },
4586 { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL
} },
4587 { "reg-names-apcs", N_("Select register names used in the APCS"),
4588 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
4589 { "reg-names-atpcs", N_("Select register names used in the ATPCS"),
4590 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
4591 { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
4592 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }}
4595 static const char *const iwmmxt_wwnames
[] =
4596 {"b", "h", "w", "d"};
4598 static const char *const iwmmxt_wwssnames
[] =
4599 {"b", "bus", "bc", "bss",
4600 "h", "hus", "hc", "hss",
4601 "w", "wus", "wc", "wss",
4602 "d", "dus", "dc", "dss"
4605 static const char *const iwmmxt_regnames
[] =
4606 { "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
4607 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
4610 static const char *const iwmmxt_cregnames
[] =
4611 { "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
4612 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
4615 static const char *const vec_condnames
[] =
4616 { "eq", "ne", "cs", "hi", "ge", "lt", "gt", "le"
4619 static const char *const mve_predicatenames
[] =
4620 { "", "ttt", "tt", "tte", "t", "tee", "te", "tet", "",
4621 "eee", "ee", "eet", "e", "ett", "et", "ete"
4624 /* Names for 2-bit size field for mve vector isntructions. */
4625 static const char *const mve_vec_sizename
[] =
4626 { "8", "16", "32", "64"};
4628 /* Indicates whether we are processing a then predicate,
4629 else predicate or none at all. */
4637 /* Information used to process a vpt block and subsequent instructions. */
4640 /* Are we in a vpt block. */
4641 bfd_boolean in_vpt_block
;
4643 /* Next predicate state if in vpt block. */
4644 enum vpt_pred_state next_pred_state
;
4646 /* Mask from vpt/vpst instruction. */
4647 long predicate_mask
;
4649 /* Instruction number in vpt block. */
4650 long current_insn_num
;
4652 /* Number of instructions in vpt block.. */
4656 static struct vpt_block vpt_block_state
=
4665 /* Default to GCC register name set. */
4666 static unsigned int regname_selected
= 1;
4668 #define NUM_ARM_OPTIONS ARRAY_SIZE (regnames)
4669 #define arm_regnames regnames[regname_selected].reg_names
4671 static bfd_boolean force_thumb
= FALSE
;
4673 /* Current IT instruction state. This contains the same state as the IT
4674 bits in the CPSR. */
4675 static unsigned int ifthen_state
;
4676 /* IT state for the next instruction. */
4677 static unsigned int ifthen_next_state
;
4678 /* The address of the insn for which the IT state is valid. */
4679 static bfd_vma ifthen_address
;
4680 #define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
4681 /* Indicates that the current Conditional state is unconditional or outside
4683 #define COND_UNCOND 16
4687 /* Extract the predicate mask for a VPT or VPST instruction.
4688 The mask is composed of bits 13-15 (Mkl) and bit 22 (Mkh). */
4691 mve_extract_pred_mask (long given
)
4693 return ((given
& 0x00400000) >> 19) | ((given
& 0xe000) >> 13);
4696 /* Return the number of instructions in a MVE predicate block. */
4698 num_instructions_vpt_block (long given
)
4700 long mask
= mve_extract_pred_mask (given
);
4707 if ((mask
& 7) == 4)
4710 if ((mask
& 3) == 2)
4713 if ((mask
& 1) == 1)
4720 mark_outside_vpt_block (void)
4722 vpt_block_state
.in_vpt_block
= FALSE
;
4723 vpt_block_state
.next_pred_state
= PRED_NONE
;
4724 vpt_block_state
.predicate_mask
= 0;
4725 vpt_block_state
.current_insn_num
= 0;
4726 vpt_block_state
.num_pred_insn
= 0;
4730 mark_inside_vpt_block (long given
)
4732 vpt_block_state
.in_vpt_block
= TRUE
;
4733 vpt_block_state
.next_pred_state
= PRED_THEN
;
4734 vpt_block_state
.predicate_mask
= mve_extract_pred_mask (given
);
4735 vpt_block_state
.current_insn_num
= 0;
4736 vpt_block_state
.num_pred_insn
= num_instructions_vpt_block (given
);
4737 assert (vpt_block_state
.num_pred_insn
>= 1);
4740 static enum vpt_pred_state
4741 invert_next_predicate_state (enum vpt_pred_state astate
)
4743 if (astate
== PRED_THEN
)
4745 else if (astate
== PRED_ELSE
)
4751 static enum vpt_pred_state
4752 update_next_predicate_state (void)
4754 long pred_mask
= vpt_block_state
.predicate_mask
;
4755 long mask_for_insn
= 0;
4757 switch (vpt_block_state
.current_insn_num
)
4775 if (pred_mask
& mask_for_insn
)
4776 return invert_next_predicate_state (vpt_block_state
.next_pred_state
);
4778 return vpt_block_state
.next_pred_state
;
4782 update_vpt_block_state (void)
4784 vpt_block_state
.current_insn_num
++;
4785 if (vpt_block_state
.current_insn_num
== vpt_block_state
.num_pred_insn
)
4787 /* No more instructions to process in vpt block. */
4788 mark_outside_vpt_block ();
4792 vpt_block_state
.next_pred_state
= update_next_predicate_state ();
4795 /* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
4796 Returns pointer to following character of the format string and
4797 fills in *VALUEP and *WIDTHP with the extracted value and number of
4798 bits extracted. WIDTHP can be NULL. */
4801 arm_decode_bitfield (const char *ptr
,
4803 unsigned long *valuep
,
4806 unsigned long value
= 0;
4814 for (start
= 0; *ptr
>= '0' && *ptr
<= '9'; ptr
++)
4815 start
= start
* 10 + *ptr
- '0';
4817 for (end
= 0, ptr
++; *ptr
>= '0' && *ptr
<= '9'; ptr
++)
4818 end
= end
* 10 + *ptr
- '0';
4824 value
|= ((insn
>> start
) & ((2ul << bits
) - 1)) << width
;
4827 while (*ptr
++ == ',');
4835 arm_decode_shift (long given
, fprintf_ftype func
, void *stream
,
4836 bfd_boolean print_shift
)
4838 func (stream
, "%s", arm_regnames
[given
& 0xf]);
4840 if ((given
& 0xff0) != 0)
4842 if ((given
& 0x10) == 0)
4844 int amount
= (given
& 0xf80) >> 7;
4845 int shift
= (given
& 0x60) >> 5;
4851 func (stream
, ", rrx");
4859 func (stream
, ", %s #%d", arm_shift
[shift
], amount
);
4861 func (stream
, ", #%d", amount
);
4863 else if ((given
& 0x80) == 0x80)
4864 func (stream
, "\t; <illegal shifter operand>");
4865 else if (print_shift
)
4866 func (stream
, ", %s %s", arm_shift
[(given
& 0x60) >> 5],
4867 arm_regnames
[(given
& 0xf00) >> 8]);
4869 func (stream
, ", %s", arm_regnames
[(given
& 0xf00) >> 8]);
4873 /* Return TRUE if the MATCHED_INSN can be inside an IT block. */
4876 is_mve_okay_in_it (enum mve_instructions matched_insn
)
4878 switch (matched_insn
)
4880 case MVE_VMOV_GP_TO_VEC_LANE
:
4881 case MVE_VMOV2_VEC_LANE_TO_GP
:
4882 case MVE_VMOV2_GP_TO_VEC_LANE
:
4883 case MVE_VMOV_VEC_LANE_TO_GP
:
4891 is_mve_architecture (struct disassemble_info
*info
)
4893 struct arm_private_data
*private_data
= info
->private_data
;
4894 arm_feature_set allowed_arches
= private_data
->features
;
4896 arm_feature_set arm_ext_v8_1m_main
4897 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
);
4899 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main
, allowed_arches
)
4900 && !ARM_CPU_IS_ANY (allowed_arches
))
4907 is_vpt_instruction (long given
)
4910 /* If mkh:mkl is '0000' then its not a vpt/vpst instruction. */
4911 if ((given
& 0x0040e000) == 0)
4914 /* VPT floating point T1 variant. */
4915 if (((given
& 0xefb10f50) == 0xee310f00 && ((given
& 0x1001) != 0x1))
4916 /* VPT floating point T2 variant. */
4917 || ((given
& 0xefb10f50) == 0xee310f40)
4918 /* VPT vector T1 variant. */
4919 || ((given
& 0xff811f51) == 0xfe010f00)
4920 /* VPT vector T2 variant. */
4921 || ((given
& 0xff811f51) == 0xfe010f01
4922 && ((given
& 0x300000) != 0x300000))
4923 /* VPT vector T3 variant. */
4924 || ((given
& 0xff811f50) == 0xfe011f00)
4925 /* VPT vector T4 variant. */
4926 || ((given
& 0xff811f70) == 0xfe010f40)
4927 /* VPT vector T5 variant. */
4928 || ((given
& 0xff811f70) == 0xfe010f60)
4929 /* VPT vector T6 variant. */
4930 || ((given
& 0xff811f50) == 0xfe011f40)
4931 /* VPST vector T variant. */
4932 || ((given
& 0xffbf1fff) == 0xfe310f4d))
4938 /* Decode a bitfield from opcode GIVEN, with starting bitfield = START
4939 and ending bitfield = END. END must be greater than START. */
4941 static unsigned long
4942 arm_decode_field (unsigned long given
, unsigned int start
, unsigned int end
)
4944 int bits
= end
- start
;
4949 return ((given
>> start
) & ((2ul << bits
) - 1));
4952 /* Decode a bitfield from opcode GIVEN, with multiple bitfields:
4953 START:END and START2:END2. END/END2 must be greater than
4956 static unsigned long
4957 arm_decode_field_multiple (unsigned long given
, unsigned int start
,
4958 unsigned int end
, unsigned int start2
,
4961 int bits
= end
- start
;
4962 int bits2
= end2
- start2
;
4963 unsigned long value
= 0;
4969 value
= arm_decode_field (given
, start
, end
);
4972 value
|= ((given
>> start2
) & ((2ul << bits2
) - 1)) << width
;
4976 /* Return TRUE if the GIVEN encoding should not be decoded as MATCHED_INSN.
4977 This helps us decode instructions that change mnemonic depending on specific
4978 operand values/encodings. */
4981 is_mve_encoding_conflict (unsigned long given
,
4982 enum mve_instructions matched_insn
)
4984 switch (matched_insn
)
4987 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) == 0)
4993 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) == 0)
4995 if ((arm_decode_field (given
, 12, 12) == 0)
4996 && (arm_decode_field (given
, 0, 0) == 1))
5001 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) == 0)
5003 if (arm_decode_field (given
, 0, 3) == 0xd)
5007 case MVE_VPT_VEC_T1
:
5008 case MVE_VPT_VEC_T2
:
5009 case MVE_VPT_VEC_T3
:
5010 case MVE_VPT_VEC_T4
:
5011 case MVE_VPT_VEC_T5
:
5012 case MVE_VPT_VEC_T6
:
5013 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) == 0)
5015 if (arm_decode_field (given
, 20, 21) == 3)
5019 case MVE_VCMP_FP_T1
:
5020 if ((arm_decode_field (given
, 12, 12) == 0)
5021 && (arm_decode_field (given
, 0, 0) == 1))
5026 case MVE_VCMP_FP_T2
:
5027 if (arm_decode_field (given
, 0, 3) == 0xd)
5032 case MVE_VADD_VEC_T2
:
5033 case MVE_VSUB_VEC_T2
:
5050 case MVE_VQDMULH_T3
:
5051 case MVE_VQRDMULH_T4
:
5057 case MVE_VCMP_VEC_T1
:
5058 case MVE_VCMP_VEC_T2
:
5059 case MVE_VCMP_VEC_T3
:
5060 case MVE_VCMP_VEC_T4
:
5061 case MVE_VCMP_VEC_T5
:
5062 case MVE_VCMP_VEC_T6
:
5063 if (arm_decode_field (given
, 20, 21) == 3)
5072 if (arm_decode_field (given
, 7, 8) == 3)
5079 if ((arm_decode_field (given
, 24, 24) == 0)
5080 && (arm_decode_field (given
, 21, 21) == 0))
5084 else if ((arm_decode_field (given
, 7, 8) == 3))
5092 if ((arm_decode_field (given
, 24, 24) == 0)
5093 && (arm_decode_field (given
, 21, 21) == 0))
5100 case MVE_VCVT_FP_FIX_VEC
:
5101 return (arm_decode_field (given
, 16, 21) & 0x38) == 0;
5106 unsigned long cmode
= arm_decode_field (given
, 8, 11);
5108 if ((cmode
& 1) == 0)
5110 else if ((cmode
& 0xc) == 0xc)
5118 unsigned long cmode
= arm_decode_field (given
, 8, 11);
5120 if ((cmode
& 9) == 1)
5122 else if ((cmode
& 5) == 1)
5124 else if ((cmode
& 0xe) == 0xe)
5130 case MVE_VMOV_IMM_TO_VEC
:
5131 if ((arm_decode_field (given
, 5, 5) == 1)
5132 && (arm_decode_field (given
, 8, 11) != 0xe))
5139 unsigned long size
= arm_decode_field (given
, 19, 20);
5140 if ((size
== 0) || (size
== 3))
5155 if (arm_decode_field (given
, 18, 19) == 3)
5161 case MVE_VRMLSLDAVH
:
5164 if (arm_decode_field (given
, 20, 22) == 7)
5169 case MVE_VRMLALDAVH
:
5170 if ((arm_decode_field (given
, 20, 22) & 6) == 6)
5177 if ((arm_decode_field (given
, 20, 21) == 3)
5178 || (arm_decode_field (given
, 1, 3) == 7))
5185 if (arm_decode_field (given
, 16, 18) == 0)
5187 unsigned long sz
= arm_decode_field (given
, 19, 20);
5189 if ((sz
== 1) || (sz
== 2))
5204 if (arm_decode_field (given
, 19, 21) == 0)
5210 case MVE_VADD_FP_T1
:
5211 case MVE_VADD_FP_T2
:
5212 case MVE_VADD_VEC_T1
:
5219 print_mve_vld_str_addr (struct disassemble_info
*info
,
5220 unsigned long given
,
5221 enum mve_instructions matched_insn
)
5223 void *stream
= info
->stream
;
5224 fprintf_ftype func
= info
->fprintf_func
;
5226 unsigned long p
, w
, gpr
, imm
, add
, mod_imm
;
5228 imm
= arm_decode_field (given
, 0, 6);
5231 switch (matched_insn
)
5235 gpr
= arm_decode_field (given
, 16, 18);
5240 gpr
= arm_decode_field (given
, 16, 18);
5246 gpr
= arm_decode_field (given
, 16, 19);
5252 gpr
= arm_decode_field (given
, 16, 19);
5258 gpr
= arm_decode_field (given
, 16, 19);
5265 p
= arm_decode_field (given
, 24, 24);
5266 w
= arm_decode_field (given
, 21, 21);
5268 add
= arm_decode_field (given
, 23, 23);
5272 /* Don't print anything for '+' as it is implied. */
5282 func (stream
, "[%s, #%s%lu]", arm_regnames
[gpr
], add_sub
, mod_imm
);
5283 /* Pre-indexed mode. */
5285 func (stream
, "[%s, #%s%lu]!", arm_regnames
[gpr
], add_sub
, mod_imm
);
5287 else if ((p
== 0) && (w
== 1))
5288 /* Post-index mode. */
5289 func (stream
, "[%s], #%s%lu", arm_regnames
[gpr
], add_sub
, mod_imm
);
5292 /* Return FALSE if GIVEN is not an undefined encoding for MATCHED_INSN.
5293 Otherwise, return TRUE and set UNDEFINED_CODE to give a reason as to why
5294 this encoding is undefined. */
5297 is_mve_undefined (unsigned long given
, enum mve_instructions matched_insn
,
5298 enum mve_undefined
*undefined_code
)
5300 *undefined_code
= UNDEF_NONE
;
5302 switch (matched_insn
)
5305 if (arm_decode_field_multiple (given
, 5, 5, 22, 22) == 3)
5307 *undefined_code
= UNDEF_SIZE_3
;
5314 case MVE_VADD_VEC_T1
:
5315 case MVE_VSUB_VEC_T1
:
5316 case MVE_VQDMULH_T1
:
5317 case MVE_VQRDMULH_T2
:
5321 if (arm_decode_field (given
, 20, 21) == 3)
5323 *undefined_code
= UNDEF_SIZE_3
;
5330 if (arm_decode_field (given
, 7, 8) == 3)
5332 *undefined_code
= UNDEF_SIZE_3
;
5339 if (arm_decode_field (given
, 7, 8) <= 1)
5341 *undefined_code
= UNDEF_SIZE_LE_1
;
5348 if ((arm_decode_field (given
, 7, 8) == 0))
5350 *undefined_code
= UNDEF_SIZE_0
;
5357 if ((arm_decode_field (given
, 7, 8) <= 1))
5359 *undefined_code
= UNDEF_SIZE_LE_1
;
5365 case MVE_VLDRB_GATHER_T1
:
5366 if (arm_decode_field (given
, 7, 8) == 3)
5368 *undefined_code
= UNDEF_SIZE_3
;
5371 else if ((arm_decode_field (given
, 28, 28) == 0)
5372 && (arm_decode_field (given
, 7, 8) == 0))
5374 *undefined_code
= UNDEF_NOT_UNS_SIZE_0
;
5380 case MVE_VLDRH_GATHER_T2
:
5381 if (arm_decode_field (given
, 7, 8) == 3)
5383 *undefined_code
= UNDEF_SIZE_3
;
5386 else if ((arm_decode_field (given
, 28, 28) == 0)
5387 && (arm_decode_field (given
, 7, 8) == 1))
5389 *undefined_code
= UNDEF_NOT_UNS_SIZE_1
;
5392 else if (arm_decode_field (given
, 7, 8) == 0)
5394 *undefined_code
= UNDEF_SIZE_0
;
5400 case MVE_VLDRW_GATHER_T3
:
5401 if (arm_decode_field (given
, 7, 8) != 2)
5403 *undefined_code
= UNDEF_SIZE_NOT_2
;
5406 else if (arm_decode_field (given
, 28, 28) == 0)
5408 *undefined_code
= UNDEF_NOT_UNSIGNED
;
5414 case MVE_VLDRD_GATHER_T4
:
5415 if (arm_decode_field (given
, 7, 8) != 3)
5417 *undefined_code
= UNDEF_SIZE_NOT_3
;
5420 else if (arm_decode_field (given
, 28, 28) == 0)
5422 *undefined_code
= UNDEF_NOT_UNSIGNED
;
5428 case MVE_VSTRB_SCATTER_T1
:
5429 if (arm_decode_field (given
, 7, 8) == 3)
5431 *undefined_code
= UNDEF_SIZE_3
;
5437 case MVE_VSTRH_SCATTER_T2
:
5439 unsigned long size
= arm_decode_field (given
, 7, 8);
5442 *undefined_code
= UNDEF_SIZE_3
;
5447 *undefined_code
= UNDEF_SIZE_0
;
5454 case MVE_VSTRW_SCATTER_T3
:
5455 if (arm_decode_field (given
, 7, 8) != 2)
5457 *undefined_code
= UNDEF_SIZE_NOT_2
;
5463 case MVE_VSTRD_SCATTER_T4
:
5464 if (arm_decode_field (given
, 7, 8) != 3)
5466 *undefined_code
= UNDEF_SIZE_NOT_3
;
5472 case MVE_VCVT_FP_FIX_VEC
:
5474 unsigned long imm6
= arm_decode_field (given
, 16, 21);
5475 if ((imm6
& 0x20) == 0)
5477 *undefined_code
= UNDEF_VCVT_IMM6
;
5481 if ((arm_decode_field (given
, 9, 9) == 0)
5482 && ((imm6
& 0x30) == 0x20))
5484 *undefined_code
= UNDEF_VCVT_FSI_IMM6
;
5492 case MVE_VCVT_BETWEEN_FP_INT
:
5493 case MVE_VCVT_FROM_FP_TO_INT
:
5495 unsigned long size
= arm_decode_field (given
, 18, 19);
5498 *undefined_code
= UNDEF_SIZE_0
;
5503 *undefined_code
= UNDEF_SIZE_3
;
5510 case MVE_VMOV_VEC_LANE_TO_GP
:
5512 unsigned long op1
= arm_decode_field (given
, 21, 22);
5513 unsigned long op2
= arm_decode_field (given
, 5, 6);
5514 unsigned long u
= arm_decode_field (given
, 23, 23);
5516 if ((op2
== 0) && (u
== 1))
5518 if ((op1
== 0) || (op1
== 1))
5520 *undefined_code
= UNDEF_BAD_U_OP1_OP2
;
5528 if ((op1
== 0) || (op1
== 1))
5530 *undefined_code
= UNDEF_BAD_OP1_OP2
;
5540 case MVE_VMOV_GP_TO_VEC_LANE
:
5541 if (arm_decode_field (given
, 5, 6) == 2)
5543 unsigned long op1
= arm_decode_field (given
, 21, 22);
5544 if ((op1
== 0) || (op1
== 1))
5546 *undefined_code
= UNDEF_BAD_OP1_OP2
;
5555 case MVE_VMOV_IMM_TO_VEC
:
5556 if (arm_decode_field (given
, 5, 5) == 0)
5558 unsigned long cmode
= arm_decode_field (given
, 8, 11);
5560 if (((cmode
& 9) == 1) || ((cmode
& 5) == 1))
5562 *undefined_code
= UNDEF_OP_0_BAD_CMODE
;
5573 if (arm_decode_field (given
, 18, 19) == 2)
5575 *undefined_code
= UNDEF_SIZE_2
;
5581 case MVE_VRMLALDAVH
:
5582 case MVE_VMLADAV_T1
:
5583 case MVE_VMLADAV_T2
:
5585 if ((arm_decode_field (given
, 28, 28) == 1)
5586 && (arm_decode_field (given
, 12, 12) == 1))
5588 *undefined_code
= UNDEF_XCHG_UNS
;
5599 unsigned long sz
= arm_decode_field (given
, 19, 20);
5602 else if ((sz
& 2) == 2)
5606 *undefined_code
= UNDEF_SIZE
;
5620 unsigned long sz
= arm_decode_field (given
, 19, 21);
5623 else if ((sz
& 6) == 2)
5625 else if ((sz
& 4) == 4)
5629 *undefined_code
= UNDEF_SIZE
;
5636 if (arm_decode_field (given
, 19, 20) == 0)
5638 *undefined_code
= UNDEF_SIZE_0
;
5645 if (arm_decode_field (given
, 18, 19) == 3)
5647 *undefined_code
= UNDEF_SIZE_3
;
5658 /* Return FALSE if GIVEN is not an unpredictable encoding for MATCHED_INSN.
5659 Otherwise, return TRUE and set UNPREDICTABLE_CODE to give a reason as to
5660 why this encoding is unpredictable. */
5663 is_mve_unpredictable (unsigned long given
, enum mve_instructions matched_insn
,
5664 enum mve_unpredictable
*unpredictable_code
)
5666 *unpredictable_code
= UNPRED_NONE
;
5668 switch (matched_insn
)
5670 case MVE_VCMP_FP_T2
:
5672 if ((arm_decode_field (given
, 12, 12) == 0)
5673 && (arm_decode_field (given
, 5, 5) == 1))
5675 *unpredictable_code
= UNPRED_FCA_0_FCB_1
;
5681 case MVE_VPT_VEC_T4
:
5682 case MVE_VPT_VEC_T5
:
5683 case MVE_VPT_VEC_T6
:
5684 case MVE_VCMP_VEC_T4
:
5685 case MVE_VCMP_VEC_T5
:
5686 case MVE_VCMP_VEC_T6
:
5687 if (arm_decode_field (given
, 0, 3) == 0xd)
5689 *unpredictable_code
= UNPRED_R13
;
5697 unsigned long gpr
= arm_decode_field (given
, 12, 15);
5700 *unpredictable_code
= UNPRED_R13
;
5703 else if (gpr
== 0xf)
5705 *unpredictable_code
= UNPRED_R15
;
5712 case MVE_VADD_FP_T2
:
5713 case MVE_VSUB_FP_T2
:
5714 case MVE_VADD_VEC_T2
:
5715 case MVE_VSUB_VEC_T2
:
5725 case MVE_VQDMULH_T3
:
5726 case MVE_VQRDMULH_T4
:
5728 case MVE_VFMA_FP_SCALAR
:
5729 case MVE_VFMAS_FP_SCALAR
:
5733 unsigned long gpr
= arm_decode_field (given
, 0, 3);
5736 *unpredictable_code
= UNPRED_R13
;
5739 else if (gpr
== 0xf)
5741 *unpredictable_code
= UNPRED_R15
;
5751 unsigned long rn
= arm_decode_field (given
, 16, 19);
5753 if ((rn
== 0xd) && (arm_decode_field (given
, 21, 21) == 1))
5755 *unpredictable_code
= UNPRED_R13_AND_WB
;
5761 *unpredictable_code
= UNPRED_R15
;
5765 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) > 6)
5767 *unpredictable_code
= UNPRED_Q_GT_6
;
5777 unsigned long rn
= arm_decode_field (given
, 16, 19);
5779 if ((rn
== 0xd) && (arm_decode_field (given
, 21, 21) == 1))
5781 *unpredictable_code
= UNPRED_R13_AND_WB
;
5787 *unpredictable_code
= UNPRED_R15
;
5791 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) > 4)
5793 *unpredictable_code
= UNPRED_Q_GT_4
;
5807 unsigned long rn
= arm_decode_field (given
, 16, 19);
5809 if ((rn
== 0xd) && (arm_decode_field (given
, 21, 21) == 1))
5811 *unpredictable_code
= UNPRED_R13_AND_WB
;
5816 *unpredictable_code
= UNPRED_R15
;
5823 case MVE_VLDRB_GATHER_T1
:
5824 if (arm_decode_field (given
, 0, 0) == 1)
5826 *unpredictable_code
= UNPRED_OS
;
5831 /* To handle common code with T2-T4 variants. */
5832 case MVE_VLDRH_GATHER_T2
:
5833 case MVE_VLDRW_GATHER_T3
:
5834 case MVE_VLDRD_GATHER_T4
:
5836 unsigned long qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
5837 unsigned long qm
= arm_decode_field_multiple (given
, 1, 3, 5, 5);
5841 *unpredictable_code
= UNPRED_Q_REGS_EQUAL
;
5845 if (arm_decode_field (given
, 16, 19) == 0xf)
5847 *unpredictable_code
= UNPRED_R15
;
5854 case MVE_VLDRW_GATHER_T5
:
5855 case MVE_VLDRD_GATHER_T6
:
5857 unsigned long qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
5858 unsigned long qm
= arm_decode_field_multiple (given
, 17, 19, 7, 7);
5862 *unpredictable_code
= UNPRED_Q_REGS_EQUAL
;
5869 case MVE_VSTRB_SCATTER_T1
:
5870 if (arm_decode_field (given
, 16, 19) == 0xf)
5872 *unpredictable_code
= UNPRED_R15
;
5875 else if (arm_decode_field (given
, 0, 0) == 1)
5877 *unpredictable_code
= UNPRED_OS
;
5883 case MVE_VSTRH_SCATTER_T2
:
5884 case MVE_VSTRW_SCATTER_T3
:
5885 case MVE_VSTRD_SCATTER_T4
:
5886 if (arm_decode_field (given
, 16, 19) == 0xf)
5888 *unpredictable_code
= UNPRED_R15
;
5894 case MVE_VMOV2_VEC_LANE_TO_GP
:
5895 case MVE_VMOV2_GP_TO_VEC_LANE
:
5896 case MVE_VCVT_BETWEEN_FP_INT
:
5897 case MVE_VCVT_FROM_FP_TO_INT
:
5899 unsigned long rt
= arm_decode_field (given
, 0, 3);
5900 unsigned long rt2
= arm_decode_field (given
, 16, 19);
5902 if ((rt
== 0xd) || (rt2
== 0xd))
5904 *unpredictable_code
= UNPRED_R13
;
5907 else if ((rt
== 0xf) || (rt2
== 0xf))
5909 *unpredictable_code
= UNPRED_R15
;
5914 *unpredictable_code
= UNPRED_GP_REGS_EQUAL
;
5922 case MVE_VMOV_HFP_TO_GP
:
5923 case MVE_VMOV_GP_TO_VEC_LANE
:
5924 case MVE_VMOV_VEC_LANE_TO_GP
:
5926 unsigned long rda
= arm_decode_field (given
, 12, 15);
5929 *unpredictable_code
= UNPRED_R13
;
5932 else if (rda
== 0xf)
5934 *unpredictable_code
= UNPRED_R15
;
5951 if (arm_decode_field (given
, 20, 21) == 2)
5953 Qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
5954 Qm
= arm_decode_field_multiple (given
, 1, 3, 5, 5);
5955 Qn
= arm_decode_field_multiple (given
, 17, 19, 7, 7);
5957 if ((Qd
== Qn
) || (Qd
== Qm
))
5959 *unpredictable_code
= UNPRED_Q_REGS_EQ_AND_SIZE_2
;
5970 case MVE_VQDMULL_T1
:
5976 if (arm_decode_field (given
, 28, 28) == 1)
5978 Qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
5979 Qm
= arm_decode_field_multiple (given
, 1, 3, 5, 5);
5980 Qn
= arm_decode_field_multiple (given
, 17, 19, 7, 7);
5982 if ((Qd
== Qn
) || (Qd
== Qm
))
5984 *unpredictable_code
= UNPRED_Q_REGS_EQ_AND_SIZE_1
;
5994 case MVE_VQDMULL_T2
:
5996 unsigned long gpr
= arm_decode_field (given
, 0, 3);
5999 *unpredictable_code
= UNPRED_R13
;
6002 else if (gpr
== 0xf)
6004 *unpredictable_code
= UNPRED_R15
;
6008 if (arm_decode_field (given
, 28, 28) == 1)
6011 = arm_decode_field_multiple (given
, 13, 15, 22, 22);
6012 unsigned long Qn
= arm_decode_field_multiple (given
, 17, 19, 7, 7);
6016 *unpredictable_code
= UNPRED_Q_REGS_EQ_AND_SIZE_1
;
6027 case MVE_VRMLSLDAVH
:
6030 if (arm_decode_field (given
, 20, 22) == 6)
6032 *unpredictable_code
= UNPRED_R13
;
6040 if (arm_decode_field (given
, 1, 3) == 6)
6042 *unpredictable_code
= UNPRED_R13
;
6051 unsigned long Qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
6052 unsigned long Qm
= arm_decode_field_multiple (given
, 1, 3, 5, 5);
6053 if ((Qd
== Qm
) && arm_decode_field (given
, 20, 21) == 2)
6055 *unpredictable_code
= UNPRED_Q_REGS_EQ_AND_SIZE_2
;
6064 unsigned long Qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
6065 unsigned long Qm
= arm_decode_field_multiple (given
, 1, 3, 5, 5);
6066 if ((Qd
== Qm
) && arm_decode_field (given
, 20, 20) == 1)
6068 *unpredictable_code
= UNPRED_Q_REGS_EQ_AND_SIZE_1
;
6081 if (arm_decode_field (given
, 20, 20) == 1)
6083 Qda
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
6084 Qm
= arm_decode_field_multiple (given
, 1, 3, 5, 5);
6085 Qn
= arm_decode_field_multiple (given
, 17, 19, 7, 7);
6087 if ((Qda
== Qn
) || (Qda
== Qm
))
6089 *unpredictable_code
= UNPRED_Q_REGS_EQ_AND_SIZE_1
;
6106 print_mve_vmov_index (struct disassemble_info
*info
, unsigned long given
)
6108 unsigned long op1
= arm_decode_field (given
, 21, 22);
6109 unsigned long op2
= arm_decode_field (given
, 5, 6);
6110 unsigned long h
= arm_decode_field (given
, 16, 16);
6111 unsigned long index
, esize
, targetBeat
, idx
;
6112 void *stream
= info
->stream
;
6113 fprintf_ftype func
= info
->fprintf_func
;
6115 if ((op1
& 0x2) == 0x2)
6120 else if (((op1
& 0x2) == 0x0) && ((op2
& 0x1) == 0x1))
6125 else if (((op1
& 0x2) == 0) && ((op2
& 0x3) == 0))
6132 func (stream
, "<undefined index>");
6136 targetBeat
= (op1
& 0x1) | (h
<< 1);
6137 idx
= index
+ targetBeat
* (32/esize
);
6139 func (stream
, "%lu", idx
);
6142 /* Print neon and mve 8-bit immediate that can be a 8, 16, 32, or 64-bits
6143 in length and integer of floating-point type. */
6145 print_simd_imm8 (struct disassemble_info
*info
, unsigned long given
,
6146 unsigned int ibit_loc
, const struct mopcode32
*insn
)
6149 int cmode
= (given
>> 8) & 0xf;
6150 int op
= (given
>> 5) & 0x1;
6151 unsigned long value
= 0, hival
= 0;
6155 void *stream
= info
->stream
;
6156 fprintf_ftype func
= info
->fprintf_func
;
6158 /* On Neon the 'i' bit is at bit 24, on mve it is
6160 bits
|= ((given
>> ibit_loc
) & 1) << 7;
6161 bits
|= ((given
>> 16) & 7) << 4;
6162 bits
|= ((given
>> 0) & 15) << 0;
6166 shift
= (cmode
>> 1) & 3;
6167 value
= (unsigned long) bits
<< (8 * shift
);
6170 else if (cmode
< 12)
6172 shift
= (cmode
>> 1) & 1;
6173 value
= (unsigned long) bits
<< (8 * shift
);
6176 else if (cmode
< 14)
6178 shift
= (cmode
& 1) + 1;
6179 value
= (unsigned long) bits
<< (8 * shift
);
6180 value
|= (1ul << (8 * shift
)) - 1;
6183 else if (cmode
== 14)
6187 /* Bit replication into bytes. */
6193 for (ix
= 7; ix
>= 0; ix
--)
6195 mask
= ((bits
>> ix
) & 1) ? 0xff : 0;
6197 value
= (value
<< 8) | mask
;
6199 hival
= (hival
<< 8) | mask
;
6205 /* Byte replication. */
6206 value
= (unsigned long) bits
;
6212 /* Floating point encoding. */
6215 value
= (unsigned long) (bits
& 0x7f) << 19;
6216 value
|= (unsigned long) (bits
& 0x80) << 24;
6217 tmp
= bits
& 0x40 ? 0x3c : 0x40;
6218 value
|= (unsigned long) tmp
<< 24;
6224 func (stream
, "<illegal constant %.8x:%x:%x>",
6230 // printU determines whether the immediate value should be printed as
6232 unsigned printU
= 0;
6233 switch (insn
->mve_op
)
6237 // We want this for instructions that don't have a 'signed' type
6241 case MVE_VMOV_IMM_TO_VEC
:
6248 func (stream
, "#%ld\t; 0x%.2lx", value
, value
);
6255 : "#%ld\t; 0x%.4lx", value
, value
);
6261 unsigned char valbytes
[4];
6264 /* Do this a byte at a time so we don't have to
6265 worry about the host's endianness. */
6266 valbytes
[0] = value
& 0xff;
6267 valbytes
[1] = (value
>> 8) & 0xff;
6268 valbytes
[2] = (value
>> 16) & 0xff;
6269 valbytes
[3] = (value
>> 24) & 0xff;
6271 floatformat_to_double
6272 (& floatformat_ieee_single_little
, valbytes
,
6275 func (stream
, "#%.7g\t; 0x%.8lx", fvalue
,
6282 : "#%ld\t; 0x%.8lx",
6283 (long) (((value
& 0x80000000L
) != 0)
6285 ? value
| ~0xffffffffL
: value
),
6290 func (stream
, "#0x%.8lx%.8lx", hival
, value
);
6300 print_mve_undefined (struct disassemble_info
*info
,
6301 enum mve_undefined undefined_code
)
6303 void *stream
= info
->stream
;
6304 fprintf_ftype func
= info
->fprintf_func
;
6306 func (stream
, "\t\tundefined instruction: ");
6308 switch (undefined_code
)
6311 func (stream
, "illegal size");
6315 func (stream
, "size equals zero");
6319 func (stream
, "size equals two");
6323 func (stream
, "size equals three");
6326 case UNDEF_SIZE_LE_1
:
6327 func (stream
, "size <= 1");
6330 case UNDEF_SIZE_NOT_2
:
6331 func (stream
, "size not equal to 2");
6334 case UNDEF_SIZE_NOT_3
:
6335 func (stream
, "size not equal to 3");
6338 case UNDEF_NOT_UNS_SIZE_0
:
6339 func (stream
, "not unsigned and size = zero");
6342 case UNDEF_NOT_UNS_SIZE_1
:
6343 func (stream
, "not unsigned and size = one");
6346 case UNDEF_NOT_UNSIGNED
:
6347 func (stream
, "not unsigned");
6350 case UNDEF_VCVT_IMM6
:
6351 func (stream
, "invalid imm6");
6354 case UNDEF_VCVT_FSI_IMM6
:
6355 func (stream
, "fsi = 0 and invalid imm6");
6358 case UNDEF_BAD_OP1_OP2
:
6359 func (stream
, "bad size with op2 = 2 and op1 = 0 or 1");
6362 case UNDEF_BAD_U_OP1_OP2
:
6363 func (stream
, "unsigned with op2 = 0 and op1 = 0 or 1");
6366 case UNDEF_OP_0_BAD_CMODE
:
6367 func (stream
, "op field equal 0 and bad cmode");
6370 case UNDEF_XCHG_UNS
:
6371 func (stream
, "exchange and unsigned together");
6381 print_mve_unpredictable (struct disassemble_info
*info
,
6382 enum mve_unpredictable unpredict_code
)
6384 void *stream
= info
->stream
;
6385 fprintf_ftype func
= info
->fprintf_func
;
6387 func (stream
, "%s: ", UNPREDICTABLE_INSTRUCTION
);
6389 switch (unpredict_code
)
6391 case UNPRED_IT_BLOCK
:
6392 func (stream
, "mve instruction in it block");
6395 case UNPRED_FCA_0_FCB_1
:
6396 func (stream
, "condition bits, fca = 0 and fcb = 1");
6400 func (stream
, "use of r13 (sp)");
6404 func (stream
, "use of r15 (pc)");
6408 func (stream
, "start register block > r4");
6412 func (stream
, "start register block > r6");
6415 case UNPRED_R13_AND_WB
:
6416 func (stream
, "use of r13 and write back");
6419 case UNPRED_Q_REGS_EQUAL
:
6421 "same vector register used for destination and other operand");
6425 func (stream
, "use of offset scaled");
6428 case UNPRED_GP_REGS_EQUAL
:
6429 func (stream
, "same general-purpose register used for both operands");
6432 case UNPRED_Q_REGS_EQ_AND_SIZE_1
:
6433 func (stream
, "use of identical q registers and size = 1");
6436 case UNPRED_Q_REGS_EQ_AND_SIZE_2
:
6437 func (stream
, "use of identical q registers and size = 1");
6445 /* Print register block operand for mve vld2/vld4/vst2/vld4. */
6448 print_mve_register_blocks (struct disassemble_info
*info
,
6449 unsigned long given
,
6450 enum mve_instructions matched_insn
)
6452 void *stream
= info
->stream
;
6453 fprintf_ftype func
= info
->fprintf_func
;
6455 unsigned long q_reg_start
= arm_decode_field_multiple (given
,
6458 switch (matched_insn
)
6462 if (q_reg_start
<= 6)
6463 func (stream
, "{q%ld, q%ld}", q_reg_start
, q_reg_start
+ 1);
6465 func (stream
, "<illegal reg q%ld>", q_reg_start
);
6470 if (q_reg_start
<= 4)
6471 func (stream
, "{q%ld, q%ld, q%ld, q%ld}", q_reg_start
,
6472 q_reg_start
+ 1, q_reg_start
+ 2,
6475 func (stream
, "<illegal reg q%ld>", q_reg_start
);
6484 print_mve_rounding_mode (struct disassemble_info
*info
,
6485 unsigned long given
,
6486 enum mve_instructions matched_insn
)
6488 void *stream
= info
->stream
;
6489 fprintf_ftype func
= info
->fprintf_func
;
6491 switch (matched_insn
)
6493 case MVE_VCVT_FROM_FP_TO_INT
:
6495 switch (arm_decode_field (given
, 8, 9))
6521 switch (arm_decode_field (given
, 7, 9))
6560 print_mve_vcvt_size (struct disassemble_info
*info
,
6561 unsigned long given
,
6562 enum mve_instructions matched_insn
)
6564 unsigned long mode
= 0;
6565 void *stream
= info
->stream
;
6566 fprintf_ftype func
= info
->fprintf_func
;
6568 switch (matched_insn
)
6570 case MVE_VCVT_FP_FIX_VEC
:
6572 mode
= (((given
& 0x200) >> 7)
6573 | ((given
& 0x10000000) >> 27)
6574 | ((given
& 0x100) >> 8));
6579 func (stream
, "f16.s16");
6583 func (stream
, "s16.f16");
6587 func (stream
, "f16.u16");
6591 func (stream
, "u16.f16");
6595 func (stream
, "f32.s32");
6599 func (stream
, "s32.f32");
6603 func (stream
, "f32.u32");
6607 func (stream
, "u32.f32");
6615 case MVE_VCVT_BETWEEN_FP_INT
:
6617 unsigned long size
= arm_decode_field (given
, 18, 19);
6618 unsigned long op
= arm_decode_field (given
, 7, 8);
6625 func (stream
, "f16.s16");
6629 func (stream
, "f16.u16");
6633 func (stream
, "s16.f16");
6637 func (stream
, "u16.f16");
6649 func (stream
, "f32.s32");
6653 func (stream
, "f32.u32");
6657 func (stream
, "s32.f32");
6661 func (stream
, "u32.f32");
6668 case MVE_VCVT_FP_HALF_FP
:
6670 unsigned long op
= arm_decode_field (given
, 28, 28);
6672 func (stream
, "f16.f32");
6674 func (stream
, "f32.f16");
6678 case MVE_VCVT_FROM_FP_TO_INT
:
6680 unsigned long size
= arm_decode_field_multiple (given
, 7, 7, 18, 19);
6685 func (stream
, "s16.f16");
6689 func (stream
, "u16.f16");
6693 func (stream
, "s32.f32");
6697 func (stream
, "u32.f32");
6712 print_mve_rotate (struct disassemble_info
*info
, unsigned long rot
,
6713 unsigned long rot_width
)
6715 void *stream
= info
->stream
;
6716 fprintf_ftype func
= info
->fprintf_func
;
6723 func (stream
, "90");
6726 func (stream
, "270");
6732 else if (rot_width
== 2)
6740 func (stream
, "90");
6743 func (stream
, "180");
6746 func (stream
, "270");
6755 print_instruction_predicate (struct disassemble_info
*info
)
6757 void *stream
= info
->stream
;
6758 fprintf_ftype func
= info
->fprintf_func
;
6760 if (vpt_block_state
.next_pred_state
== PRED_THEN
)
6762 else if (vpt_block_state
.next_pred_state
== PRED_ELSE
)
6767 print_mve_size (struct disassemble_info
*info
,
6769 enum mve_instructions matched_insn
)
6771 void *stream
= info
->stream
;
6772 fprintf_ftype func
= info
->fprintf_func
;
6774 switch (matched_insn
)
6780 case MVE_VADD_VEC_T1
:
6781 case MVE_VADD_VEC_T2
:
6784 case MVE_VCMP_VEC_T1
:
6785 case MVE_VCMP_VEC_T2
:
6786 case MVE_VCMP_VEC_T3
:
6787 case MVE_VCMP_VEC_T4
:
6788 case MVE_VCMP_VEC_T5
:
6789 case MVE_VCMP_VEC_T6
:
6801 case MVE_VLDRB_GATHER_T1
:
6802 case MVE_VLDRH_GATHER_T2
:
6803 case MVE_VLDRW_GATHER_T3
:
6804 case MVE_VLDRD_GATHER_T4
:
6808 case MVE_VPT_VEC_T1
:
6809 case MVE_VPT_VEC_T2
:
6810 case MVE_VPT_VEC_T3
:
6811 case MVE_VPT_VEC_T4
:
6812 case MVE_VPT_VEC_T5
:
6813 case MVE_VPT_VEC_T6
:
6822 case MVE_VQDMULH_T1
:
6823 case MVE_VQRDMULH_T2
:
6824 case MVE_VQDMULH_T3
:
6825 case MVE_VQRDMULH_T4
:
6839 case MVE_VSTRB_SCATTER_T1
:
6840 case MVE_VSTRH_SCATTER_T2
:
6841 case MVE_VSTRW_SCATTER_T3
:
6844 case MVE_VSUB_VEC_T1
:
6845 case MVE_VSUB_VEC_T2
:
6847 func (stream
, "%s", mve_vec_sizename
[size
]);
6849 func (stream
, "<undef size>");
6853 case MVE_VADD_FP_T1
:
6854 case MVE_VADD_FP_T2
:
6855 case MVE_VSUB_FP_T1
:
6856 case MVE_VSUB_FP_T2
:
6857 case MVE_VCMP_FP_T1
:
6858 case MVE_VCMP_FP_T2
:
6859 case MVE_VFMA_FP_SCALAR
:
6862 case MVE_VFMAS_FP_SCALAR
:
6866 func (stream
, "32");
6868 func (stream
, "16");
6874 case MVE_VMLADAV_T1
:
6876 case MVE_VMLSDAV_T1
:
6879 case MVE_VQDMULL_T1
:
6880 case MVE_VQDMULL_T2
:
6884 func (stream
, "16");
6886 func (stream
, "32");
6893 func (stream
, "16");
6900 func (stream
, "32");
6903 func (stream
, "16");
6913 case MVE_VMOV_GP_TO_VEC_LANE
:
6914 case MVE_VMOV_VEC_LANE_TO_GP
:
6918 func (stream
, "32");
6923 func (stream
, "16");
6926 case 8: case 9: case 10: case 11:
6927 case 12: case 13: case 14: case 15:
6936 case MVE_VMOV_IMM_TO_VEC
:
6939 case 0: case 4: case 8:
6940 case 12: case 24: case 26:
6941 func (stream
, "i32");
6944 func (stream
, "i16");
6947 func (stream
, "i8");
6950 func (stream
, "i64");
6953 func (stream
, "f32");
6960 case MVE_VMULL_POLY
:
6962 func (stream
, "p8");
6964 func (stream
, "p16");
6970 case 0: case 2: case 4:
6971 case 6: case 12: case 13:
6972 func (stream
, "32");
6976 func (stream
, "16");
6990 func (stream
, "32");
6994 func (stream
, "16");
7012 func (stream
, "16");
7016 func (stream
, "32");
7041 func (stream
, "16");
7044 case 4: case 5: case 6: case 7:
7045 func (stream
, "32");
7060 print_mve_shift_n (struct disassemble_info
*info
, long given
,
7061 enum mve_instructions matched_insn
)
7063 void *stream
= info
->stream
;
7064 fprintf_ftype func
= info
->fprintf_func
;
7067 = matched_insn
== MVE_VQSHL_T2
7068 || matched_insn
== MVE_VQSHLU_T3
7069 || matched_insn
== MVE_VSHL_T1
7070 || matched_insn
== MVE_VSHLL_T1
7071 || matched_insn
== MVE_VSLI
;
7073 unsigned imm6
= (given
& 0x3f0000) >> 16;
7075 if (matched_insn
== MVE_VSHLL_T1
)
7078 unsigned shiftAmount
= 0;
7079 if ((imm6
& 0x20) != 0)
7080 shiftAmount
= startAt0
? imm6
- 32 : 64 - imm6
;
7081 else if ((imm6
& 0x10) != 0)
7082 shiftAmount
= startAt0
? imm6
- 16 : 32 - imm6
;
7083 else if ((imm6
& 0x08) != 0)
7084 shiftAmount
= startAt0
? imm6
- 8 : 16 - imm6
;
7086 print_mve_undefined (info
, UNDEF_SIZE_0
);
7088 func (stream
, "%u", shiftAmount
);
7092 print_vec_condition (struct disassemble_info
*info
, long given
,
7093 enum mve_instructions matched_insn
)
7095 void *stream
= info
->stream
;
7096 fprintf_ftype func
= info
->fprintf_func
;
7099 switch (matched_insn
)
7102 case MVE_VCMP_FP_T1
:
7103 vec_cond
= (((given
& 0x1000) >> 10)
7104 | ((given
& 1) << 1)
7105 | ((given
& 0x0080) >> 7));
7106 func (stream
, "%s",vec_condnames
[vec_cond
]);
7110 case MVE_VCMP_FP_T2
:
7111 vec_cond
= (((given
& 0x1000) >> 10)
7112 | ((given
& 0x0020) >> 4)
7113 | ((given
& 0x0080) >> 7));
7114 func (stream
, "%s",vec_condnames
[vec_cond
]);
7117 case MVE_VPT_VEC_T1
:
7118 case MVE_VCMP_VEC_T1
:
7119 vec_cond
= (given
& 0x0080) >> 7;
7120 func (stream
, "%s",vec_condnames
[vec_cond
]);
7123 case MVE_VPT_VEC_T2
:
7124 case MVE_VCMP_VEC_T2
:
7125 vec_cond
= 2 | ((given
& 0x0080) >> 7);
7126 func (stream
, "%s",vec_condnames
[vec_cond
]);
7129 case MVE_VPT_VEC_T3
:
7130 case MVE_VCMP_VEC_T3
:
7131 vec_cond
= 4 | ((given
& 1) << 1) | ((given
& 0x0080) >> 7);
7132 func (stream
, "%s",vec_condnames
[vec_cond
]);
7135 case MVE_VPT_VEC_T4
:
7136 case MVE_VCMP_VEC_T4
:
7137 vec_cond
= (given
& 0x0080) >> 7;
7138 func (stream
, "%s",vec_condnames
[vec_cond
]);
7141 case MVE_VPT_VEC_T5
:
7142 case MVE_VCMP_VEC_T5
:
7143 vec_cond
= 2 | ((given
& 0x0080) >> 7);
7144 func (stream
, "%s",vec_condnames
[vec_cond
]);
7147 case MVE_VPT_VEC_T6
:
7148 case MVE_VCMP_VEC_T6
:
7149 vec_cond
= 4 | ((given
& 0x0020) >> 4) | ((given
& 0x0080) >> 7);
7150 func (stream
, "%s",vec_condnames
[vec_cond
]);
7165 #define WRITEBACK_BIT_SET (given & (1 << W_BIT))
7166 #define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
7167 #define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
7168 #define PRE_BIT_SET (given & (1 << P_BIT))
7171 /* Print one coprocessor instruction on INFO->STREAM.
7172 Return TRUE if the instuction matched, FALSE if this is not a
7173 recognised coprocessor instruction. */
7176 print_insn_coprocessor (bfd_vma pc
,
7177 struct disassemble_info
*info
,
7181 const struct sopcode32
*insn
;
7182 void *stream
= info
->stream
;
7183 fprintf_ftype func
= info
->fprintf_func
;
7185 unsigned long value
= 0;
7188 struct arm_private_data
*private_data
= info
->private_data
;
7189 arm_feature_set allowed_arches
= ARM_ARCH_NONE
;
7190 arm_feature_set arm_ext_v8_1m_main
=
7191 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
);
7193 allowed_arches
= private_data
->features
;
7195 for (insn
= coprocessor_opcodes
; insn
->assembler
; insn
++)
7197 unsigned long u_reg
= 16;
7198 bfd_boolean is_unpredictable
= FALSE
;
7199 signed long value_in_comment
= 0;
7202 if (ARM_FEATURE_ZERO (insn
->arch
))
7203 switch (insn
->value
)
7205 case SENTINEL_IWMMXT_START
:
7206 if (info
->mach
!= bfd_mach_arm_XScale
7207 && info
->mach
!= bfd_mach_arm_iWMMXt
7208 && info
->mach
!= bfd_mach_arm_iWMMXt2
)
7211 while ((! ARM_FEATURE_ZERO (insn
->arch
))
7212 && insn
->value
!= SENTINEL_IWMMXT_END
);
7215 case SENTINEL_IWMMXT_END
:
7218 case SENTINEL_GENERIC_START
:
7219 allowed_arches
= private_data
->features
;
7227 value
= insn
->value
;
7228 cp_num
= (given
>> 8) & 0xf;
7232 /* The high 4 bits are 0xe for Arm conditional instructions, and
7233 0xe for arm unconditional instructions. The rest of the
7234 encoding is the same. */
7236 value
|= 0xe0000000;
7244 /* Only match unconditional instuctions against unconditional
7246 if ((given
& 0xf0000000) == 0xf0000000)
7253 cond
= (given
>> 28) & 0xf;
7259 if ((insn
->isa
== T32
&& !thumb
)
7260 || (insn
->isa
== ARM
&& thumb
))
7263 if ((given
& mask
) != value
)
7266 if (! ARM_CPU_HAS_FEATURE (insn
->arch
, allowed_arches
))
7269 if (insn
->value
== 0xfe000010 /* mcr2 */
7270 || insn
->value
== 0xfe100010 /* mrc2 */
7271 || insn
->value
== 0xfc100000 /* ldc2 */
7272 || insn
->value
== 0xfc000000) /* stc2 */
7274 if (cp_num
== 9 || cp_num
== 10 || cp_num
== 11)
7275 is_unpredictable
= TRUE
;
7277 /* Armv8.1-M Mainline FP & MVE instructions. */
7278 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main
, allowed_arches
)
7279 && !ARM_CPU_IS_ANY (allowed_arches
)
7280 && (cp_num
== 8 || cp_num
== 14 || cp_num
== 15))
7284 else if (insn
->value
== 0x0e000000 /* cdp */
7285 || insn
->value
== 0xfe000000 /* cdp2 */
7286 || insn
->value
== 0x0e000010 /* mcr */
7287 || insn
->value
== 0x0e100010 /* mrc */
7288 || insn
->value
== 0x0c100000 /* ldc */
7289 || insn
->value
== 0x0c000000) /* stc */
7291 /* Floating-point instructions. */
7292 if (cp_num
== 9 || cp_num
== 10 || cp_num
== 11)
7295 /* Armv8.1-M Mainline FP & MVE instructions. */
7296 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main
, allowed_arches
)
7297 && !ARM_CPU_IS_ANY (allowed_arches
)
7298 && (cp_num
== 8 || cp_num
== 14 || cp_num
== 15))
7301 else if ((insn
->value
== 0xec100f80 /* vldr (system register) */
7302 || insn
->value
== 0xec000f80) /* vstr (system register) */
7303 && arm_decode_field (given
, 24, 24) == 0
7304 && arm_decode_field (given
, 21, 21) == 0)
7305 /* If the P and W bits are both 0 then these encodings match the MVE
7306 VLDR and VSTR instructions, these are in a different table, so we
7307 don't let it match here. */
7310 for (c
= insn
->assembler
; *c
; c
++)
7314 const char mod
= *++c
;
7318 func (stream
, "%%");
7324 int rn
= (given
>> 16) & 0xf;
7325 bfd_vma offset
= given
& 0xff;
7328 offset
= given
& 0x7f;
7330 func (stream
, "[%s", arm_regnames
[(given
>> 16) & 0xf]);
7332 if (PRE_BIT_SET
|| WRITEBACK_BIT_SET
)
7334 /* Not unindexed. The offset is scaled. */
7336 /* vldr.16/vstr.16 will shift the address
7337 left by 1 bit only. */
7338 offset
= offset
* 2;
7340 offset
= offset
* 4;
7342 if (NEGATIVE_BIT_SET
)
7345 value_in_comment
= offset
;
7351 func (stream
, ", #%d]%s",
7353 WRITEBACK_BIT_SET
? "!" : "");
7354 else if (NEGATIVE_BIT_SET
)
7355 func (stream
, ", #-0]");
7363 if (WRITEBACK_BIT_SET
)
7366 func (stream
, ", #%d", (int) offset
);
7367 else if (NEGATIVE_BIT_SET
)
7368 func (stream
, ", #-0");
7372 func (stream
, ", {%s%d}",
7373 (NEGATIVE_BIT_SET
&& !offset
) ? "-" : "",
7375 value_in_comment
= offset
;
7378 if (rn
== 15 && (PRE_BIT_SET
|| WRITEBACK_BIT_SET
))
7380 func (stream
, "\t; ");
7381 /* For unaligned PCs, apply off-by-alignment
7383 info
->print_address_func (offset
+ pc
7384 + info
->bytes_per_chunk
* 2
7393 int regno
= ((given
>> 12) & 0xf) | ((given
>> (22 - 4)) & 0x10);
7394 int offset
= (given
>> 1) & 0x3f;
7397 func (stream
, "{d%d}", regno
);
7398 else if (regno
+ offset
> 32)
7399 func (stream
, "{d%d-<overflow reg d%d>}", regno
, regno
+ offset
- 1);
7401 func (stream
, "{d%d-d%d}", regno
, regno
+ offset
- 1);
7407 bfd_boolean single
= ((given
>> 8) & 1) == 0;
7408 char reg_prefix
= single
? 's' : 'd';
7409 int Dreg
= (given
>> 22) & 0x1;
7410 int Vdreg
= (given
>> 12) & 0xf;
7411 int reg
= single
? ((Vdreg
<< 1) | Dreg
)
7412 : ((Dreg
<< 4) | Vdreg
);
7413 int num
= (given
>> (single
? 0 : 1)) & 0x7f;
7414 int maxreg
= single
? 31 : 15;
7415 int topreg
= reg
+ num
- 1;
7418 func (stream
, "{VPR}");
7420 func (stream
, "{%c%d, VPR}", reg_prefix
, reg
);
7421 else if (topreg
> maxreg
)
7422 func (stream
, "{%c%d-<overflow reg d%d, VPR}",
7423 reg_prefix
, reg
, single
? topreg
>> 1 : topreg
);
7425 func (stream
, "{%c%d-%c%d, VPR}", reg_prefix
, reg
,
7426 reg_prefix
, topreg
);
7431 if (cond
!= COND_UNCOND
)
7432 is_unpredictable
= TRUE
;
7436 if (cond
!= COND_UNCOND
&& cp_num
== 9)
7437 is_unpredictable
= TRUE
;
7439 func (stream
, "%s", arm_conditional
[cond
]);
7443 /* Print a Cirrus/DSP shift immediate. */
7444 /* Immediates are 7bit signed ints with bits 0..3 in
7445 bits 0..3 of opcode and bits 4..6 in bits 5..7
7450 imm
= (given
& 0xf) | ((given
& 0xe0) >> 1);
7452 /* Is ``imm'' a negative number? */
7456 func (stream
, "%d", imm
);
7464 = arm_decode_field_multiple (given
, 13, 15, 22, 22);
7469 func (stream
, "FPSCR");
7472 func (stream
, "FPSCR_nzcvqc");
7475 func (stream
, "VPR");
7478 func (stream
, "P0");
7481 func (stream
, "FPCXTNS");
7484 func (stream
, "FPCXTS");
7487 func (stream
, "<invalid reg %lu>", regno
);
7494 switch (given
& 0x00408000)
7511 switch (given
& 0x00080080)
7523 func (stream
, _("<illegal precision>"));
7529 switch (given
& 0x00408000)
7547 switch (given
& 0x60)
7563 case '0': case '1': case '2': case '3': case '4':
7564 case '5': case '6': case '7': case '8': case '9':
7568 c
= arm_decode_bitfield (c
, given
, &value
, &width
);
7574 is_unpredictable
= TRUE
;
7579 /* Eat the 'u' character. */
7583 is_unpredictable
= TRUE
;
7586 func (stream
, "%s", arm_regnames
[value
]);
7589 if (given
& (1 << 6))
7593 func (stream
, "d%ld", value
);
7598 func (stream
, "<illegal reg q%ld.5>", value
>> 1);
7600 func (stream
, "q%ld", value
>> 1);
7603 func (stream
, "%ld", value
);
7604 value_in_comment
= value
;
7608 /* Converts immediate 8 bit back to float value. */
7609 unsigned floatVal
= (value
& 0x80) << 24
7610 | (value
& 0x3F) << 19
7611 | ((value
& 0x40) ? (0xF8 << 22) : (1 << 30));
7613 /* Quarter float have a maximum value of 31.0.
7614 Get floating point value multiplied by 1e7.
7615 The maximum value stays in limit of a 32-bit int. */
7617 (78125 << (((floatVal
>> 23) & 0xFF) - 124)) *
7618 (16 + (value
& 0xF));
7620 if (!(decVal
% 1000000))
7621 func (stream
, "%ld\t; 0x%08x %c%u.%01u", value
,
7622 floatVal
, value
& 0x80 ? '-' : ' ',
7624 decVal
% 10000000 / 1000000);
7625 else if (!(decVal
% 10000))
7626 func (stream
, "%ld\t; 0x%08x %c%u.%03u", value
,
7627 floatVal
, value
& 0x80 ? '-' : ' ',
7629 decVal
% 10000000 / 10000);
7631 func (stream
, "%ld\t; 0x%08x %c%u.%07u", value
,
7632 floatVal
, value
& 0x80 ? '-' : ' ',
7633 decVal
/ 10000000, decVal
% 10000000);
7638 int from
= (given
& (1 << 7)) ? 32 : 16;
7639 func (stream
, "%ld", from
- value
);
7645 func (stream
, "#%s", arm_fp_const
[value
& 7]);
7647 func (stream
, "f%ld", value
);
7652 func (stream
, "%s", iwmmxt_wwnames
[value
]);
7654 func (stream
, "%s", iwmmxt_wwssnames
[value
]);
7658 func (stream
, "%s", iwmmxt_regnames
[value
]);
7661 func (stream
, "%s", iwmmxt_cregnames
[value
]);
7665 func (stream
, "0x%lx", (value
& 0xffffffffUL
));
7672 func (stream
, "eq");
7676 func (stream
, "vs");
7680 func (stream
, "ge");
7684 func (stream
, "gt");
7688 func (stream
, "??");
7696 func (stream
, "%c", *c
);
7700 if (value
== ((1ul << width
) - 1))
7701 func (stream
, "%c", *c
);
7704 func (stream
, "%c", c
[(1 << width
) - (int) value
]);
7716 int single
= *c
++ == 'y';
7721 case '4': /* Sm pair */
7722 case '0': /* Sm, Dm */
7723 regno
= given
& 0x0000000f;
7727 regno
+= (given
>> 5) & 1;
7730 regno
+= ((given
>> 5) & 1) << 4;
7733 case '1': /* Sd, Dd */
7734 regno
= (given
>> 12) & 0x0000000f;
7738 regno
+= (given
>> 22) & 1;
7741 regno
+= ((given
>> 22) & 1) << 4;
7744 case '2': /* Sn, Dn */
7745 regno
= (given
>> 16) & 0x0000000f;
7749 regno
+= (given
>> 7) & 1;
7752 regno
+= ((given
>> 7) & 1) << 4;
7755 case '3': /* List */
7757 regno
= (given
>> 12) & 0x0000000f;
7761 regno
+= (given
>> 22) & 1;
7764 regno
+= ((given
>> 22) & 1) << 4;
7771 func (stream
, "%c%d", single
? 's' : 'd', regno
);
7775 int count
= given
& 0xff;
7782 func (stream
, "-%c%d",
7790 func (stream
, ", %c%d", single
? 's' : 'd',
7796 switch (given
& 0x00400100)
7798 case 0x00000000: func (stream
, "b"); break;
7799 case 0x00400000: func (stream
, "h"); break;
7800 case 0x00000100: func (stream
, "w"); break;
7801 case 0x00400100: func (stream
, "d"); break;
7809 /* given (20, 23) | given (0, 3) */
7810 value
= ((given
>> 16) & 0xf0) | (given
& 0xf);
7811 func (stream
, "%d", (int) value
);
7816 /* This is like the 'A' operator, except that if
7817 the width field "M" is zero, then the offset is
7818 *not* multiplied by four. */
7820 int offset
= given
& 0xff;
7821 int multiplier
= (given
& 0x00000100) ? 4 : 1;
7823 func (stream
, "[%s", arm_regnames
[(given
>> 16) & 0xf]);
7827 value_in_comment
= offset
* multiplier
;
7828 if (NEGATIVE_BIT_SET
)
7829 value_in_comment
= - value_in_comment
;
7835 func (stream
, ", #%s%d]%s",
7836 NEGATIVE_BIT_SET
? "-" : "",
7837 offset
* multiplier
,
7838 WRITEBACK_BIT_SET
? "!" : "");
7840 func (stream
, "], #%s%d",
7841 NEGATIVE_BIT_SET
? "-" : "",
7842 offset
* multiplier
);
7851 int imm4
= (given
>> 4) & 0xf;
7852 int puw_bits
= ((given
>> 22) & 6) | ((given
>> W_BIT
) & 1);
7853 int ubit
= ! NEGATIVE_BIT_SET
;
7854 const char *rm
= arm_regnames
[given
& 0xf];
7855 const char *rn
= arm_regnames
[(given
>> 16) & 0xf];
7861 func (stream
, "[%s], %c%s", rn
, ubit
? '+' : '-', rm
);
7863 func (stream
, ", lsl #%d", imm4
);
7870 func (stream
, "[%s, %c%s", rn
, ubit
? '+' : '-', rm
);
7872 func (stream
, ", lsl #%d", imm4
);
7874 if (puw_bits
== 5 || puw_bits
== 7)
7879 func (stream
, "INVALID");
7887 imm5
= ((given
& 0x100) >> 4) | (given
& 0xf);
7888 func (stream
, "%ld", (imm5
== 0) ? 32 : imm5
);
7897 func (stream
, "%c", *c
);
7900 if (value_in_comment
> 32 || value_in_comment
< -16)
7901 func (stream
, "\t; 0x%lx", (value_in_comment
& 0xffffffffUL
));
7903 if (is_unpredictable
)
7904 func (stream
, UNPREDICTABLE_INSTRUCTION
);
7911 /* Decodes and prints ARM addressing modes. Returns the offset
7912 used in the address, if any, if it is worthwhile printing the
7913 offset as a hexadecimal value in a comment at the end of the
7914 line of disassembly. */
7917 print_arm_address (bfd_vma pc
, struct disassemble_info
*info
, long given
)
7919 void *stream
= info
->stream
;
7920 fprintf_ftype func
= info
->fprintf_func
;
7923 if (((given
& 0x000f0000) == 0x000f0000)
7924 && ((given
& 0x02000000) == 0))
7926 offset
= given
& 0xfff;
7928 func (stream
, "[pc");
7932 /* Pre-indexed. Elide offset of positive zero when
7934 if (WRITEBACK_BIT_SET
|| NEGATIVE_BIT_SET
|| offset
)
7935 func (stream
, ", #%s%d", NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
7937 if (NEGATIVE_BIT_SET
)
7942 /* Cope with the possibility of write-back
7943 being used. Probably a very dangerous thing
7944 for the programmer to do, but who are we to
7946 func (stream
, "]%s", WRITEBACK_BIT_SET
? "!" : "");
7948 else /* Post indexed. */
7950 func (stream
, "], #%s%d", NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
7952 /* Ie ignore the offset. */
7956 func (stream
, "\t; ");
7957 info
->print_address_func (offset
, info
);
7962 func (stream
, "[%s",
7963 arm_regnames
[(given
>> 16) & 0xf]);
7967 if ((given
& 0x02000000) == 0)
7969 /* Elide offset of positive zero when non-writeback. */
7970 offset
= given
& 0xfff;
7971 if (WRITEBACK_BIT_SET
|| NEGATIVE_BIT_SET
|| offset
)
7972 func (stream
, ", #%s%d", NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
7976 func (stream
, ", %s", NEGATIVE_BIT_SET
? "-" : "");
7977 arm_decode_shift (given
, func
, stream
, TRUE
);
7980 func (stream
, "]%s",
7981 WRITEBACK_BIT_SET
? "!" : "");
7985 if ((given
& 0x02000000) == 0)
7987 /* Always show offset. */
7988 offset
= given
& 0xfff;
7989 func (stream
, "], #%s%d",
7990 NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
7994 func (stream
, "], %s",
7995 NEGATIVE_BIT_SET
? "-" : "");
7996 arm_decode_shift (given
, func
, stream
, TRUE
);
7999 if (NEGATIVE_BIT_SET
)
8003 return (signed long) offset
;
8006 /* Print one neon instruction on INFO->STREAM.
8007 Return TRUE if the instuction matched, FALSE if this is not a
8008 recognised neon instruction. */
8011 print_insn_neon (struct disassemble_info
*info
, long given
, bfd_boolean thumb
)
8013 const struct opcode32
*insn
;
8014 void *stream
= info
->stream
;
8015 fprintf_ftype func
= info
->fprintf_func
;
8019 if ((given
& 0xef000000) == 0xef000000)
8021 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
8022 unsigned long bit28
= given
& (1 << 28);
8024 given
&= 0x00ffffff;
8026 given
|= 0xf3000000;
8028 given
|= 0xf2000000;
8030 else if ((given
& 0xff000000) == 0xf9000000)
8031 given
^= 0xf9000000 ^ 0xf4000000;
8032 /* vdup is also a valid neon instruction. */
8033 else if ((given
& 0xff910f5f) != 0xee800b10)
8037 for (insn
= neon_opcodes
; insn
->assembler
; insn
++)
8039 if ((given
& insn
->mask
) == insn
->value
)
8041 signed long value_in_comment
= 0;
8042 bfd_boolean is_unpredictable
= FALSE
;
8045 for (c
= insn
->assembler
; *c
; c
++)
8052 func (stream
, "%%");
8056 if (thumb
&& ifthen_state
)
8057 is_unpredictable
= TRUE
;
8061 if (thumb
&& ifthen_state
)
8062 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
8067 static const unsigned char enc
[16] =
8069 0x4, 0x14, /* st4 0,1 */
8081 int rd
= ((given
>> 12) & 0xf) | (((given
>> 22) & 1) << 4);
8082 int rn
= ((given
>> 16) & 0xf);
8083 int rm
= ((given
>> 0) & 0xf);
8084 int align
= ((given
>> 4) & 0x3);
8085 int type
= ((given
>> 8) & 0xf);
8086 int n
= enc
[type
] & 0xf;
8087 int stride
= (enc
[type
] >> 4) + 1;
8092 for (ix
= 0; ix
!= n
; ix
++)
8093 func (stream
, "%sd%d", ix
? "," : "", rd
+ ix
* stride
);
8095 func (stream
, "d%d", rd
);
8097 func (stream
, "d%d-d%d", rd
, rd
+ n
- 1);
8098 func (stream
, "}, [%s", arm_regnames
[rn
]);
8100 func (stream
, " :%d", 32 << align
);
8105 func (stream
, ", %s", arm_regnames
[rm
]);
8111 int rd
= ((given
>> 12) & 0xf) | (((given
>> 22) & 1) << 4);
8112 int rn
= ((given
>> 16) & 0xf);
8113 int rm
= ((given
>> 0) & 0xf);
8114 int idx_align
= ((given
>> 4) & 0xf);
8116 int size
= ((given
>> 10) & 0x3);
8117 int idx
= idx_align
>> (size
+ 1);
8118 int length
= ((given
>> 8) & 3) + 1;
8122 if (length
> 1 && size
> 0)
8123 stride
= (idx_align
& (1 << size
)) ? 2 : 1;
8129 int amask
= (1 << size
) - 1;
8130 if ((idx_align
& (1 << size
)) != 0)
8134 if ((idx_align
& amask
) == amask
)
8136 else if ((idx_align
& amask
) != 0)
8143 if (size
== 2 && (idx_align
& 2) != 0)
8145 align
= (idx_align
& 1) ? 16 << size
: 0;
8149 if ((size
== 2 && (idx_align
& 3) != 0)
8150 || (idx_align
& 1) != 0)
8157 if ((idx_align
& 3) == 3)
8159 align
= (idx_align
& 3) * 64;
8162 align
= (idx_align
& 1) ? 32 << size
: 0;
8170 for (i
= 0; i
< length
; i
++)
8171 func (stream
, "%sd%d[%d]", (i
== 0) ? "" : ",",
8172 rd
+ i
* stride
, idx
);
8173 func (stream
, "}, [%s", arm_regnames
[rn
]);
8175 func (stream
, " :%d", align
);
8180 func (stream
, ", %s", arm_regnames
[rm
]);
8186 int rd
= ((given
>> 12) & 0xf) | (((given
>> 22) & 1) << 4);
8187 int rn
= ((given
>> 16) & 0xf);
8188 int rm
= ((given
>> 0) & 0xf);
8189 int align
= ((given
>> 4) & 0x1);
8190 int size
= ((given
>> 6) & 0x3);
8191 int type
= ((given
>> 8) & 0x3);
8193 int stride
= ((given
>> 5) & 0x1);
8196 if (stride
&& (n
== 1))
8203 for (ix
= 0; ix
!= n
; ix
++)
8204 func (stream
, "%sd%d[]", ix
? "," : "", rd
+ ix
* stride
);
8206 func (stream
, "d%d[]", rd
);
8208 func (stream
, "d%d[]-d%d[]", rd
, rd
+ n
- 1);
8209 func (stream
, "}, [%s", arm_regnames
[rn
]);
8212 align
= (8 * (type
+ 1)) << size
;
8214 align
= (size
> 1) ? align
>> 1 : align
;
8215 if (type
== 2 || (type
== 0 && !size
))
8216 func (stream
, " :<bad align %d>", align
);
8218 func (stream
, " :%d", align
);
8224 func (stream
, ", %s", arm_regnames
[rm
]);
8230 int raw_reg
= (given
& 0xf) | ((given
>> 1) & 0x10);
8231 int size
= (given
>> 20) & 3;
8232 int reg
= raw_reg
& ((4 << size
) - 1);
8233 int ix
= raw_reg
>> size
>> 2;
8235 func (stream
, "d%d[%d]", reg
, ix
);
8240 /* Neon encoded constant for mov, mvn, vorr, vbic. */
8243 int cmode
= (given
>> 8) & 0xf;
8244 int op
= (given
>> 5) & 0x1;
8245 unsigned long value
= 0, hival
= 0;
8250 bits
|= ((given
>> 24) & 1) << 7;
8251 bits
|= ((given
>> 16) & 7) << 4;
8252 bits
|= ((given
>> 0) & 15) << 0;
8256 shift
= (cmode
>> 1) & 3;
8257 value
= (unsigned long) bits
<< (8 * shift
);
8260 else if (cmode
< 12)
8262 shift
= (cmode
>> 1) & 1;
8263 value
= (unsigned long) bits
<< (8 * shift
);
8266 else if (cmode
< 14)
8268 shift
= (cmode
& 1) + 1;
8269 value
= (unsigned long) bits
<< (8 * shift
);
8270 value
|= (1ul << (8 * shift
)) - 1;
8273 else if (cmode
== 14)
8277 /* Bit replication into bytes. */
8283 for (ix
= 7; ix
>= 0; ix
--)
8285 mask
= ((bits
>> ix
) & 1) ? 0xff : 0;
8287 value
= (value
<< 8) | mask
;
8289 hival
= (hival
<< 8) | mask
;
8295 /* Byte replication. */
8296 value
= (unsigned long) bits
;
8302 /* Floating point encoding. */
8305 value
= (unsigned long) (bits
& 0x7f) << 19;
8306 value
|= (unsigned long) (bits
& 0x80) << 24;
8307 tmp
= bits
& 0x40 ? 0x3c : 0x40;
8308 value
|= (unsigned long) tmp
<< 24;
8314 func (stream
, "<illegal constant %.8x:%x:%x>",
8322 func (stream
, "#%ld\t; 0x%.2lx", value
, value
);
8326 func (stream
, "#%ld\t; 0x%.4lx", value
, value
);
8332 unsigned char valbytes
[4];
8335 /* Do this a byte at a time so we don't have to
8336 worry about the host's endianness. */
8337 valbytes
[0] = value
& 0xff;
8338 valbytes
[1] = (value
>> 8) & 0xff;
8339 valbytes
[2] = (value
>> 16) & 0xff;
8340 valbytes
[3] = (value
>> 24) & 0xff;
8342 floatformat_to_double
8343 (& floatformat_ieee_single_little
, valbytes
,
8346 func (stream
, "#%.7g\t; 0x%.8lx", fvalue
,
8350 func (stream
, "#%ld\t; 0x%.8lx",
8351 (long) (((value
& 0x80000000L
) != 0)
8352 ? value
| ~0xffffffffL
: value
),
8357 func (stream
, "#0x%.8lx%.8lx", hival
, value
);
8368 int regno
= ((given
>> 16) & 0xf) | ((given
>> (7 - 4)) & 0x10);
8369 int num
= (given
>> 8) & 0x3;
8372 func (stream
, "{d%d}", regno
);
8373 else if (num
+ regno
>= 32)
8374 func (stream
, "{d%d-<overflow reg d%d}", regno
, regno
+ num
);
8376 func (stream
, "{d%d-d%d}", regno
, regno
+ num
);
8381 case '0': case '1': case '2': case '3': case '4':
8382 case '5': case '6': case '7': case '8': case '9':
8385 unsigned long value
;
8387 c
= arm_decode_bitfield (c
, given
, &value
, &width
);
8392 func (stream
, "%s", arm_regnames
[value
]);
8395 func (stream
, "%ld", value
);
8396 value_in_comment
= value
;
8399 func (stream
, "%ld", (1ul << width
) - value
);
8405 /* Various width encodings. */
8407 int base
= 8 << (*c
- 'S'); /* 8,16 or 32 */
8412 if (*c
>= '0' && *c
<= '9')
8414 else if (*c
>= 'a' && *c
<= 'f')
8415 limit
= *c
- 'a' + 10;
8421 if (value
< low
|| value
> high
)
8422 func (stream
, "<illegal width %d>", base
<< value
);
8424 func (stream
, "%d", base
<< value
);
8428 if (given
& (1 << 6))
8432 func (stream
, "d%ld", value
);
8437 func (stream
, "<illegal reg q%ld.5>", value
>> 1);
8439 func (stream
, "q%ld", value
>> 1);
8445 func (stream
, "%c", *c
);
8449 if (value
== ((1ul << width
) - 1))
8450 func (stream
, "%c", *c
);
8453 func (stream
, "%c", c
[(1 << width
) - (int) value
]);
8467 func (stream
, "%c", *c
);
8470 if (value_in_comment
> 32 || value_in_comment
< -16)
8471 func (stream
, "\t; 0x%lx", value_in_comment
);
8473 if (is_unpredictable
)
8474 func (stream
, UNPREDICTABLE_INSTRUCTION
);
8482 /* Print one mve instruction on INFO->STREAM.
8483 Return TRUE if the instuction matched, FALSE if this is not a
8484 recognised mve instruction. */
8487 print_insn_mve (struct disassemble_info
*info
, long given
)
8489 const struct mopcode32
*insn
;
8490 void *stream
= info
->stream
;
8491 fprintf_ftype func
= info
->fprintf_func
;
8493 for (insn
= mve_opcodes
; insn
->assembler
; insn
++)
8495 if (((given
& insn
->mask
) == insn
->value
)
8496 && !is_mve_encoding_conflict (given
, insn
->mve_op
))
8498 signed long value_in_comment
= 0;
8499 bfd_boolean is_unpredictable
= FALSE
;
8500 bfd_boolean is_undefined
= FALSE
;
8502 enum mve_unpredictable unpredictable_cond
= UNPRED_NONE
;
8503 enum mve_undefined undefined_cond
= UNDEF_NONE
;
8505 /* Most vector mve instruction are illegal in a it block.
8506 There are a few exceptions; check for them. */
8507 if (ifthen_state
&& !is_mve_okay_in_it (insn
->mve_op
))
8509 is_unpredictable
= TRUE
;
8510 unpredictable_cond
= UNPRED_IT_BLOCK
;
8512 else if (is_mve_unpredictable (given
, insn
->mve_op
,
8513 &unpredictable_cond
))
8514 is_unpredictable
= TRUE
;
8516 if (is_mve_undefined (given
, insn
->mve_op
, &undefined_cond
))
8517 is_undefined
= TRUE
;
8519 for (c
= insn
->assembler
; *c
; c
++)
8526 func (stream
, "%%");
8530 /* Don't print anything for '+' as it is implied. */
8531 if (arm_decode_field (given
, 23, 23) == 0)
8537 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
8541 print_mve_vld_str_addr (info
, given
, insn
->mve_op
);
8546 long mve_mask
= mve_extract_pred_mask (given
);
8547 func (stream
, "%s", mve_predicatenames
[mve_mask
]);
8552 print_vec_condition (info
, given
, insn
->mve_op
);
8556 if (arm_decode_field (given
, 0, 0) == 1)
8559 = arm_decode_field (given
, 4, 4)
8560 | (arm_decode_field (given
, 6, 6) << 1);
8562 func (stream
, ", uxtw #%lu", size
);
8567 print_mve_rounding_mode (info
, given
, insn
->mve_op
);
8571 print_mve_vcvt_size (info
, given
, insn
->mve_op
);
8576 unsigned long op1
= arm_decode_field (given
, 21, 22);
8578 if ((insn
->mve_op
== MVE_VMOV_VEC_LANE_TO_GP
))
8580 /* Check for signed. */
8581 if (arm_decode_field (given
, 23, 23) == 0)
8583 /* We don't print 's' for S32. */
8584 if ((arm_decode_field (given
, 5, 6) == 0)
8585 && ((op1
== 0) || (op1
== 1)))
8595 if (arm_decode_field (given
, 28, 28) == 0)
8604 print_instruction_predicate (info
);
8608 if (arm_decode_field (given
, 21, 21) == 1)
8613 print_mve_register_blocks (info
, given
, insn
->mve_op
);
8617 /* SIMD encoded constant for mov, mvn, vorr, vbic. */
8619 print_simd_imm8 (info
, given
, 28, insn
);
8623 print_mve_vmov_index (info
, given
);
8627 if (arm_decode_field (given
, 12, 12) == 0)
8634 if (arm_decode_field (given
, 12, 12) == 1)
8638 case '0': case '1': case '2': case '3': case '4':
8639 case '5': case '6': case '7': case '8': case '9':
8642 unsigned long value
;
8644 c
= arm_decode_bitfield (c
, given
, &value
, &width
);
8650 is_unpredictable
= TRUE
;
8651 else if (value
== 15)
8652 func (stream
, "zr");
8654 func (stream
, "%s", arm_regnames
[value
]);
8657 print_mve_size (info
,
8671 unsigned int odd_reg
= (value
<< 1) | 1;
8672 func (stream
, "%s", arm_regnames
[odd_reg
]);
8678 = arm_decode_field (given
, 0, 6);
8679 unsigned long mod_imm
= imm
;
8681 switch (insn
->mve_op
)
8683 case MVE_VLDRW_GATHER_T5
:
8684 case MVE_VSTRW_SCATTER_T5
:
8685 mod_imm
= mod_imm
<< 2;
8687 case MVE_VSTRD_SCATTER_T6
:
8688 case MVE_VLDRD_GATHER_T6
:
8689 mod_imm
= mod_imm
<< 3;
8696 func (stream
, "%lu", mod_imm
);
8700 func (stream
, "%lu", 64 - value
);
8704 unsigned int even_reg
= value
<< 1;
8705 func (stream
, "%s", arm_regnames
[even_reg
]);
8728 print_mve_rotate (info
, value
, width
);
8731 func (stream
, "%s", arm_regnames
[value
]);
8734 if (insn
->mve_op
== MVE_VQSHL_T2
8735 || insn
->mve_op
== MVE_VQSHLU_T3
8736 || insn
->mve_op
== MVE_VRSHR
8737 || insn
->mve_op
== MVE_VRSHRN
8738 || insn
->mve_op
== MVE_VSHL_T1
8739 || insn
->mve_op
== MVE_VSHLL_T1
8740 || insn
->mve_op
== MVE_VSHR
8741 || insn
->mve_op
== MVE_VSHRN
8742 || insn
->mve_op
== MVE_VSLI
8743 || insn
->mve_op
== MVE_VSRI
)
8744 print_mve_shift_n (info
, given
, insn
->mve_op
);
8745 else if (insn
->mve_op
== MVE_VSHLL_T2
)
8753 func (stream
, "16");
8756 print_mve_undefined (info
, UNDEF_SIZE_0
);
8765 if (insn
->mve_op
== MVE_VSHLC
&& value
== 0)
8767 func (stream
, "%ld", value
);
8768 value_in_comment
= value
;
8772 func (stream
, "s%ld", value
);
8776 func (stream
, "<illegal reg q%ld.5>", value
);
8778 func (stream
, "q%ld", value
);
8781 func (stream
, "0x%08lx", value
);
8793 func (stream
, "%c", *c
);
8796 if (value_in_comment
> 32 || value_in_comment
< -16)
8797 func (stream
, "\t; 0x%lx", value_in_comment
);
8799 if (is_unpredictable
)
8800 print_mve_unpredictable (info
, unpredictable_cond
);
8803 print_mve_undefined (info
, undefined_cond
);
8805 if ((vpt_block_state
.in_vpt_block
== FALSE
)
8807 && (is_vpt_instruction (given
) == TRUE
))
8808 mark_inside_vpt_block (given
);
8809 else if (vpt_block_state
.in_vpt_block
== TRUE
)
8810 update_vpt_block_state ();
8819 /* Return the name of a v7A special register. */
8822 banked_regname (unsigned reg
)
8826 case 15: return "CPSR";
8827 case 32: return "R8_usr";
8828 case 33: return "R9_usr";
8829 case 34: return "R10_usr";
8830 case 35: return "R11_usr";
8831 case 36: return "R12_usr";
8832 case 37: return "SP_usr";
8833 case 38: return "LR_usr";
8834 case 40: return "R8_fiq";
8835 case 41: return "R9_fiq";
8836 case 42: return "R10_fiq";
8837 case 43: return "R11_fiq";
8838 case 44: return "R12_fiq";
8839 case 45: return "SP_fiq";
8840 case 46: return "LR_fiq";
8841 case 48: return "LR_irq";
8842 case 49: return "SP_irq";
8843 case 50: return "LR_svc";
8844 case 51: return "SP_svc";
8845 case 52: return "LR_abt";
8846 case 53: return "SP_abt";
8847 case 54: return "LR_und";
8848 case 55: return "SP_und";
8849 case 60: return "LR_mon";
8850 case 61: return "SP_mon";
8851 case 62: return "ELR_hyp";
8852 case 63: return "SP_hyp";
8853 case 79: return "SPSR";
8854 case 110: return "SPSR_fiq";
8855 case 112: return "SPSR_irq";
8856 case 114: return "SPSR_svc";
8857 case 116: return "SPSR_abt";
8858 case 118: return "SPSR_und";
8859 case 124: return "SPSR_mon";
8860 case 126: return "SPSR_hyp";
8861 default: return NULL
;
8865 /* Return the name of the DMB/DSB option. */
8867 data_barrier_option (unsigned option
)
8869 switch (option
& 0xf)
8871 case 0xf: return "sy";
8872 case 0xe: return "st";
8873 case 0xd: return "ld";
8874 case 0xb: return "ish";
8875 case 0xa: return "ishst";
8876 case 0x9: return "ishld";
8877 case 0x7: return "un";
8878 case 0x6: return "unst";
8879 case 0x5: return "nshld";
8880 case 0x3: return "osh";
8881 case 0x2: return "oshst";
8882 case 0x1: return "oshld";
8883 default: return NULL
;
8887 /* Print one ARM instruction from PC on INFO->STREAM. */
8890 print_insn_arm (bfd_vma pc
, struct disassemble_info
*info
, long given
)
8892 const struct opcode32
*insn
;
8893 void *stream
= info
->stream
;
8894 fprintf_ftype func
= info
->fprintf_func
;
8895 struct arm_private_data
*private_data
= info
->private_data
;
8897 if (print_insn_coprocessor (pc
, info
, given
, FALSE
))
8900 if (print_insn_neon (info
, given
, FALSE
))
8903 for (insn
= arm_opcodes
; insn
->assembler
; insn
++)
8905 if ((given
& insn
->mask
) != insn
->value
)
8908 if (! ARM_CPU_HAS_FEATURE (insn
->arch
, private_data
->features
))
8911 /* Special case: an instruction with all bits set in the condition field
8912 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
8913 or by the catchall at the end of the table. */
8914 if ((given
& 0xF0000000) != 0xF0000000
8915 || (insn
->mask
& 0xF0000000) == 0xF0000000
8916 || (insn
->mask
== 0 && insn
->value
== 0))
8918 unsigned long u_reg
= 16;
8919 unsigned long U_reg
= 16;
8920 bfd_boolean is_unpredictable
= FALSE
;
8921 signed long value_in_comment
= 0;
8924 for (c
= insn
->assembler
; *c
; c
++)
8928 bfd_boolean allow_unpredictable
= FALSE
;
8933 func (stream
, "%%");
8937 value_in_comment
= print_arm_address (pc
, info
, given
);
8941 /* Set P address bit and use normal address
8942 printing routine. */
8943 value_in_comment
= print_arm_address (pc
, info
, given
| (1 << P_BIT
));
8947 allow_unpredictable
= TRUE
;
8950 if ((given
& 0x004f0000) == 0x004f0000)
8952 /* PC relative with immediate offset. */
8953 bfd_vma offset
= ((given
& 0xf00) >> 4) | (given
& 0xf);
8957 /* Elide positive zero offset. */
8958 if (offset
|| NEGATIVE_BIT_SET
)
8959 func (stream
, "[pc, #%s%d]\t; ",
8960 NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
8962 func (stream
, "[pc]\t; ");
8963 if (NEGATIVE_BIT_SET
)
8965 info
->print_address_func (offset
+ pc
+ 8, info
);
8969 /* Always show the offset. */
8970 func (stream
, "[pc], #%s%d",
8971 NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
8972 if (! allow_unpredictable
)
8973 is_unpredictable
= TRUE
;
8978 int offset
= ((given
& 0xf00) >> 4) | (given
& 0xf);
8980 func (stream
, "[%s",
8981 arm_regnames
[(given
>> 16) & 0xf]);
8985 if (IMMEDIATE_BIT_SET
)
8987 /* Elide offset for non-writeback
8989 if (WRITEBACK_BIT_SET
|| NEGATIVE_BIT_SET
8991 func (stream
, ", #%s%d",
8992 NEGATIVE_BIT_SET
? "-" : "", offset
);
8994 if (NEGATIVE_BIT_SET
)
8997 value_in_comment
= offset
;
9001 /* Register Offset or Register Pre-Indexed. */
9002 func (stream
, ", %s%s",
9003 NEGATIVE_BIT_SET
? "-" : "",
9004 arm_regnames
[given
& 0xf]);
9006 /* Writing back to the register that is the source/
9007 destination of the load/store is unpredictable. */
9008 if (! allow_unpredictable
9009 && WRITEBACK_BIT_SET
9010 && ((given
& 0xf) == ((given
>> 12) & 0xf)))
9011 is_unpredictable
= TRUE
;
9014 func (stream
, "]%s",
9015 WRITEBACK_BIT_SET
? "!" : "");
9019 if (IMMEDIATE_BIT_SET
)
9021 /* Immediate Post-indexed. */
9022 /* PR 10924: Offset must be printed, even if it is zero. */
9023 func (stream
, "], #%s%d",
9024 NEGATIVE_BIT_SET
? "-" : "", offset
);
9025 if (NEGATIVE_BIT_SET
)
9027 value_in_comment
= offset
;
9031 /* Register Post-indexed. */
9032 func (stream
, "], %s%s",
9033 NEGATIVE_BIT_SET
? "-" : "",
9034 arm_regnames
[given
& 0xf]);
9036 /* Writing back to the register that is the source/
9037 destination of the load/store is unpredictable. */
9038 if (! allow_unpredictable
9039 && (given
& 0xf) == ((given
>> 12) & 0xf))
9040 is_unpredictable
= TRUE
;
9043 if (! allow_unpredictable
)
9045 /* Writeback is automatically implied by post- addressing.
9046 Setting the W bit is unnecessary and ARM specify it as
9047 being unpredictable. */
9048 if (WRITEBACK_BIT_SET
9049 /* Specifying the PC register as the post-indexed
9050 registers is also unpredictable. */
9051 || (! IMMEDIATE_BIT_SET
&& ((given
& 0xf) == 0xf)))
9052 is_unpredictable
= TRUE
;
9060 bfd_vma disp
= (((given
& 0xffffff) ^ 0x800000) - 0x800000);
9061 info
->print_address_func (disp
* 4 + pc
+ 8, info
);
9066 if (((given
>> 28) & 0xf) != 0xe)
9068 arm_conditional
[(given
>> 28) & 0xf]);
9077 for (reg
= 0; reg
< 16; reg
++)
9078 if ((given
& (1 << reg
)) != 0)
9081 func (stream
, ", ");
9083 func (stream
, "%s", arm_regnames
[reg
]);
9087 is_unpredictable
= TRUE
;
9092 arm_decode_shift (given
, func
, stream
, FALSE
);
9096 if ((given
& 0x02000000) != 0)
9098 unsigned int rotate
= (given
& 0xf00) >> 7;
9099 unsigned int immed
= (given
& 0xff);
9102 a
= (((immed
<< (32 - rotate
))
9103 | (immed
>> rotate
)) & 0xffffffff);
9104 /* If there is another encoding with smaller rotate,
9105 the rotate should be specified directly. */
9106 for (i
= 0; i
< 32; i
+= 2)
9107 if ((a
<< i
| a
>> (32 - i
)) <= 0xff)
9111 func (stream
, "#%d, %d", immed
, rotate
);
9113 func (stream
, "#%d", a
);
9114 value_in_comment
= a
;
9117 arm_decode_shift (given
, func
, stream
, TRUE
);
9121 if ((given
& 0x0000f000) == 0x0000f000)
9123 arm_feature_set arm_ext_v6
=
9124 ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
9126 /* The p-variants of tst/cmp/cmn/teq are the pre-V6
9127 mechanism for setting PSR flag bits. They are
9128 obsolete in V6 onwards. */
9129 if (! ARM_CPU_HAS_FEATURE (private_data
->features
, \
9133 is_unpredictable
= TRUE
;
9138 if ((given
& 0x01200000) == 0x00200000)
9144 int offset
= given
& 0xff;
9146 value_in_comment
= offset
* 4;
9147 if (NEGATIVE_BIT_SET
)
9148 value_in_comment
= - value_in_comment
;
9150 func (stream
, "[%s", arm_regnames
[(given
>> 16) & 0xf]);
9155 func (stream
, ", #%d]%s",
9156 (int) value_in_comment
,
9157 WRITEBACK_BIT_SET
? "!" : "");
9165 if (WRITEBACK_BIT_SET
)
9168 func (stream
, ", #%d", (int) value_in_comment
);
9172 func (stream
, ", {%d}", (int) offset
);
9173 value_in_comment
= offset
;
9180 /* Print ARM V5 BLX(1) address: pc+25 bits. */
9185 if (! NEGATIVE_BIT_SET
)
9186 /* Is signed, hi bits should be ones. */
9187 offset
= (-1) ^ 0x00ffffff;
9189 /* Offset is (SignExtend(offset field)<<2). */
9190 offset
+= given
& 0x00ffffff;
9192 address
= offset
+ pc
+ 8;
9194 if (given
& 0x01000000)
9195 /* H bit allows addressing to 2-byte boundaries. */
9198 info
->print_address_func (address
, info
);
9203 if ((given
& 0x02000200) == 0x200)
9206 unsigned sysm
= (given
& 0x004f0000) >> 16;
9208 sysm
|= (given
& 0x300) >> 4;
9209 name
= banked_regname (sysm
);
9212 func (stream
, "%s", name
);
9214 func (stream
, "(UNDEF: %lu)", (unsigned long) sysm
);
9218 func (stream
, "%cPSR_",
9219 (given
& 0x00400000) ? 'S' : 'C');
9220 if (given
& 0x80000)
9222 if (given
& 0x40000)
9224 if (given
& 0x20000)
9226 if (given
& 0x10000)
9232 if ((given
& 0xf0) == 0x60)
9234 switch (given
& 0xf)
9236 case 0xf: func (stream
, "sy"); break;
9238 func (stream
, "#%d", (int) given
& 0xf);
9244 const char * opt
= data_barrier_option (given
& 0xf);
9246 func (stream
, "%s", opt
);
9248 func (stream
, "#%d", (int) given
& 0xf);
9252 case '0': case '1': case '2': case '3': case '4':
9253 case '5': case '6': case '7': case '8': case '9':
9256 unsigned long value
;
9258 c
= arm_decode_bitfield (c
, given
, &value
, &width
);
9264 is_unpredictable
= TRUE
;
9268 /* We want register + 1 when decoding T. */
9274 /* Eat the 'u' character. */
9278 is_unpredictable
= TRUE
;
9283 /* Eat the 'U' character. */
9287 is_unpredictable
= TRUE
;
9290 func (stream
, "%s", arm_regnames
[value
]);
9293 func (stream
, "%ld", value
);
9294 value_in_comment
= value
;
9297 func (stream
, "%ld", value
* 8);
9298 value_in_comment
= value
* 8;
9301 func (stream
, "%ld", value
+ 1);
9302 value_in_comment
= value
+ 1;
9305 func (stream
, "0x%08lx", value
);
9307 /* Some SWI instructions have special
9309 if ((given
& 0x0fffffff) == 0x0FF00000)
9310 func (stream
, "\t; IMB");
9311 else if ((given
& 0x0fffffff) == 0x0FF00001)
9312 func (stream
, "\t; IMBRange");
9315 func (stream
, "%01lx", value
& 0xf);
9316 value_in_comment
= value
;
9321 func (stream
, "%c", *c
);
9325 if (value
== ((1ul << width
) - 1))
9326 func (stream
, "%c", *c
);
9329 func (stream
, "%c", c
[(1 << width
) - (int) value
]);
9342 imm
= (given
& 0xf) | ((given
& 0xfff00) >> 4);
9343 func (stream
, "%d", imm
);
9344 value_in_comment
= imm
;
9349 /* LSB and WIDTH fields of BFI or BFC. The machine-
9350 language instruction encodes LSB and MSB. */
9352 long msb
= (given
& 0x001f0000) >> 16;
9353 long lsb
= (given
& 0x00000f80) >> 7;
9354 long w
= msb
- lsb
+ 1;
9357 func (stream
, "#%lu, #%lu", lsb
, w
);
9359 func (stream
, "(invalid: %lu:%lu)", lsb
, msb
);
9364 /* Get the PSR/banked register name. */
9367 unsigned sysm
= (given
& 0x004f0000) >> 16;
9369 sysm
|= (given
& 0x300) >> 4;
9370 name
= banked_regname (sysm
);
9373 func (stream
, "%s", name
);
9375 func (stream
, "(UNDEF: %lu)", (unsigned long) sysm
);
9380 /* 16-bit unsigned immediate from a MOVT or MOVW
9381 instruction, encoded in bits 0:11 and 15:19. */
9383 long hi
= (given
& 0x000f0000) >> 4;
9384 long lo
= (given
& 0x00000fff);
9385 long imm16
= hi
| lo
;
9387 func (stream
, "#%lu", imm16
);
9388 value_in_comment
= imm16
;
9397 func (stream
, "%c", *c
);
9400 if (value_in_comment
> 32 || value_in_comment
< -16)
9401 func (stream
, "\t; 0x%lx", (value_in_comment
& 0xffffffffUL
));
9403 if (is_unpredictable
)
9404 func (stream
, UNPREDICTABLE_INSTRUCTION
);
9409 func (stream
, UNKNOWN_INSTRUCTION_32BIT
, (unsigned)given
);
9413 /* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
9416 print_insn_thumb16 (bfd_vma pc
, struct disassemble_info
*info
, long given
)
9418 const struct opcode16
*insn
;
9419 void *stream
= info
->stream
;
9420 fprintf_ftype func
= info
->fprintf_func
;
9422 for (insn
= thumb_opcodes
; insn
->assembler
; insn
++)
9423 if ((given
& insn
->mask
) == insn
->value
)
9425 signed long value_in_comment
= 0;
9426 const char *c
= insn
->assembler
;
9435 func (stream
, "%c", *c
);
9442 func (stream
, "%%");
9447 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
9452 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
9461 ifthen_next_state
= given
& 0xff;
9462 for (tmp
= given
<< 1; tmp
& 0xf; tmp
<<= 1)
9463 func (stream
, ((given
^ tmp
) & 0x10) ? "e" : "t");
9464 func (stream
, "\t%s", arm_conditional
[(given
>> 4) & 0xf]);
9469 if (ifthen_next_state
)
9470 func (stream
, "\t; unpredictable branch in IT block\n");
9475 func (stream
, "\t; unpredictable <IT:%s>",
9476 arm_conditional
[IFTHEN_COND
]);
9483 reg
= (given
>> 3) & 0x7;
9484 if (given
& (1 << 6))
9487 func (stream
, "%s", arm_regnames
[reg
]);
9496 if (given
& (1 << 7))
9499 func (stream
, "%s", arm_regnames
[reg
]);
9504 if (given
& (1 << 8))
9508 if (*c
== 'O' && (given
& (1 << 8)))
9518 /* It would be nice if we could spot
9519 ranges, and generate the rS-rE format: */
9520 for (reg
= 0; (reg
< 8); reg
++)
9521 if ((given
& (1 << reg
)) != 0)
9524 func (stream
, ", ");
9526 func (stream
, "%s", arm_regnames
[reg
]);
9532 func (stream
, ", ");
9534 func (stream
, "%s", arm_regnames
[14] /* "lr" */);
9540 func (stream
, ", ");
9541 func (stream
, "%s", arm_regnames
[15] /* "pc" */);
9549 /* Print writeback indicator for a LDMIA. We are doing a
9550 writeback if the base register is not in the register
9552 if ((given
& (1 << ((given
& 0x0700) >> 8))) == 0)
9557 /* Print ARM V6T2 CZB address: pc+4+6 bits. */
9559 bfd_vma address
= (pc
+ 4
9560 + ((given
& 0x00f8) >> 2)
9561 + ((given
& 0x0200) >> 3));
9562 info
->print_address_func (address
, info
);
9567 /* Right shift immediate -- bits 6..10; 1-31 print
9568 as themselves, 0 prints as 32. */
9570 long imm
= (given
& 0x07c0) >> 6;
9573 func (stream
, "#%ld", imm
);
9577 case '0': case '1': case '2': case '3': case '4':
9578 case '5': case '6': case '7': case '8': case '9':
9580 int bitstart
= *c
++ - '0';
9583 while (*c
>= '0' && *c
<= '9')
9584 bitstart
= (bitstart
* 10) + *c
++ - '0';
9593 while (*c
>= '0' && *c
<= '9')
9594 bitend
= (bitend
* 10) + *c
++ - '0';
9597 reg
= given
>> bitstart
;
9598 reg
&= (2 << (bitend
- bitstart
)) - 1;
9603 func (stream
, "%s", arm_regnames
[reg
]);
9607 func (stream
, "%ld", (long) reg
);
9608 value_in_comment
= reg
;
9612 func (stream
, "%ld", (long) (reg
<< 1));
9613 value_in_comment
= reg
<< 1;
9617 func (stream
, "%ld", (long) (reg
<< 2));
9618 value_in_comment
= reg
<< 2;
9622 /* PC-relative address -- the bottom two
9623 bits of the address are dropped
9624 before the calculation. */
9625 info
->print_address_func
9626 (((pc
+ 4) & ~3) + (reg
<< 2), info
);
9627 value_in_comment
= 0;
9631 func (stream
, "0x%04lx", (long) reg
);
9635 reg
= ((reg
^ (1 << bitend
)) - (1 << bitend
));
9636 info
->print_address_func (reg
* 2 + pc
+ 4, info
);
9637 value_in_comment
= 0;
9641 func (stream
, "%s", arm_conditional
[reg
]);
9652 if ((given
& (1 << bitstart
)) != 0)
9653 func (stream
, "%c", *c
);
9658 if ((given
& (1 << bitstart
)) != 0)
9659 func (stream
, "%c", *c
++);
9661 func (stream
, "%c", *++c
);
9675 if (value_in_comment
> 32 || value_in_comment
< -16)
9676 func (stream
, "\t; 0x%lx", value_in_comment
);
9681 func (stream
, UNKNOWN_INSTRUCTION_16BIT
, (unsigned)given
);
9685 /* Return the name of an V7M special register. */
9688 psr_name (int regno
)
9692 case 0x0: return "APSR";
9693 case 0x1: return "IAPSR";
9694 case 0x2: return "EAPSR";
9695 case 0x3: return "PSR";
9696 case 0x5: return "IPSR";
9697 case 0x6: return "EPSR";
9698 case 0x7: return "IEPSR";
9699 case 0x8: return "MSP";
9700 case 0x9: return "PSP";
9701 case 0xa: return "MSPLIM";
9702 case 0xb: return "PSPLIM";
9703 case 0x10: return "PRIMASK";
9704 case 0x11: return "BASEPRI";
9705 case 0x12: return "BASEPRI_MAX";
9706 case 0x13: return "FAULTMASK";
9707 case 0x14: return "CONTROL";
9708 case 0x88: return "MSP_NS";
9709 case 0x89: return "PSP_NS";
9710 case 0x8a: return "MSPLIM_NS";
9711 case 0x8b: return "PSPLIM_NS";
9712 case 0x90: return "PRIMASK_NS";
9713 case 0x91: return "BASEPRI_NS";
9714 case 0x93: return "FAULTMASK_NS";
9715 case 0x94: return "CONTROL_NS";
9716 case 0x98: return "SP_NS";
9717 default: return "<unknown>";
9721 /* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
9724 print_insn_thumb32 (bfd_vma pc
, struct disassemble_info
*info
, long given
)
9726 const struct opcode32
*insn
;
9727 void *stream
= info
->stream
;
9728 fprintf_ftype func
= info
->fprintf_func
;
9729 bfd_boolean is_mve
= is_mve_architecture (info
);
9731 if (print_insn_coprocessor (pc
, info
, given
, TRUE
))
9734 if ((is_mve
== FALSE
) && print_insn_neon (info
, given
, TRUE
))
9737 if (is_mve
&& print_insn_mve (info
, given
))
9740 for (insn
= thumb32_opcodes
; insn
->assembler
; insn
++)
9741 if ((given
& insn
->mask
) == insn
->value
)
9743 bfd_boolean is_clrm
= FALSE
;
9744 bfd_boolean is_unpredictable
= FALSE
;
9745 signed long value_in_comment
= 0;
9746 const char *c
= insn
->assembler
;
9752 func (stream
, "%c", *c
);
9759 func (stream
, "%%");
9764 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
9768 if (ifthen_next_state
)
9769 func (stream
, "\t; unpredictable branch in IT block\n");
9774 func (stream
, "\t; unpredictable <IT:%s>",
9775 arm_conditional
[IFTHEN_COND
]);
9780 unsigned int imm12
= 0;
9782 imm12
|= (given
& 0x000000ffu
);
9783 imm12
|= (given
& 0x00007000u
) >> 4;
9784 imm12
|= (given
& 0x04000000u
) >> 15;
9785 func (stream
, "#%u", imm12
);
9786 value_in_comment
= imm12
;
9792 unsigned int bits
= 0, imm
, imm8
, mod
;
9794 bits
|= (given
& 0x000000ffu
);
9795 bits
|= (given
& 0x00007000u
) >> 4;
9796 bits
|= (given
& 0x04000000u
) >> 15;
9797 imm8
= (bits
& 0x0ff);
9798 mod
= (bits
& 0xf00) >> 8;
9801 case 0: imm
= imm8
; break;
9802 case 1: imm
= ((imm8
<< 16) | imm8
); break;
9803 case 2: imm
= ((imm8
<< 24) | (imm8
<< 8)); break;
9804 case 3: imm
= ((imm8
<< 24) | (imm8
<< 16) | (imm8
<< 8) | imm8
); break;
9806 mod
= (bits
& 0xf80) >> 7;
9807 imm8
= (bits
& 0x07f) | 0x80;
9808 imm
= (((imm8
<< (32 - mod
)) | (imm8
>> mod
)) & 0xffffffff);
9810 func (stream
, "#%u", imm
);
9811 value_in_comment
= imm
;
9817 unsigned int imm
= 0;
9819 imm
|= (given
& 0x000000ffu
);
9820 imm
|= (given
& 0x00007000u
) >> 4;
9821 imm
|= (given
& 0x04000000u
) >> 15;
9822 imm
|= (given
& 0x000f0000u
) >> 4;
9823 func (stream
, "#%u", imm
);
9824 value_in_comment
= imm
;
9830 unsigned int imm
= 0;
9832 imm
|= (given
& 0x000f0000u
) >> 16;
9833 imm
|= (given
& 0x00000ff0u
) >> 0;
9834 imm
|= (given
& 0x0000000fu
) << 12;
9835 func (stream
, "#%u", imm
);
9836 value_in_comment
= imm
;
9842 unsigned int imm
= 0;
9844 imm
|= (given
& 0x000f0000u
) >> 4;
9845 imm
|= (given
& 0x00000fffu
) >> 0;
9846 func (stream
, "#%u", imm
);
9847 value_in_comment
= imm
;
9853 unsigned int imm
= 0;
9855 imm
|= (given
& 0x00000fffu
);
9856 imm
|= (given
& 0x000f0000u
) >> 4;
9857 func (stream
, "#%u", imm
);
9858 value_in_comment
= imm
;
9864 unsigned int reg
= (given
& 0x0000000fu
);
9865 unsigned int stp
= (given
& 0x00000030u
) >> 4;
9866 unsigned int imm
= 0;
9867 imm
|= (given
& 0x000000c0u
) >> 6;
9868 imm
|= (given
& 0x00007000u
) >> 10;
9870 func (stream
, "%s", arm_regnames
[reg
]);
9875 func (stream
, ", lsl #%u", imm
);
9881 func (stream
, ", lsr #%u", imm
);
9887 func (stream
, ", asr #%u", imm
);
9892 func (stream
, ", rrx");
9894 func (stream
, ", ror #%u", imm
);
9901 unsigned int Rn
= (given
& 0x000f0000) >> 16;
9902 unsigned int U
= ! NEGATIVE_BIT_SET
;
9903 unsigned int op
= (given
& 0x00000f00) >> 8;
9904 unsigned int i12
= (given
& 0x00000fff);
9905 unsigned int i8
= (given
& 0x000000ff);
9906 bfd_boolean writeback
= FALSE
, postind
= FALSE
;
9909 func (stream
, "[%s", arm_regnames
[Rn
]);
9910 if (U
) /* 12-bit positive immediate offset. */
9914 value_in_comment
= offset
;
9916 else if (Rn
== 15) /* 12-bit negative immediate offset. */
9917 offset
= - (int) i12
;
9918 else if (op
== 0x0) /* Shifted register offset. */
9920 unsigned int Rm
= (i8
& 0x0f);
9921 unsigned int sh
= (i8
& 0x30) >> 4;
9923 func (stream
, ", %s", arm_regnames
[Rm
]);
9925 func (stream
, ", lsl #%u", sh
);
9931 case 0xE: /* 8-bit positive immediate offset. */
9935 case 0xC: /* 8-bit negative immediate offset. */
9939 case 0xF: /* 8-bit + preindex with wb. */
9944 case 0xD: /* 8-bit - preindex with wb. */
9949 case 0xB: /* 8-bit + postindex. */
9954 case 0x9: /* 8-bit - postindex. */
9960 func (stream
, ", <undefined>]");
9965 func (stream
, "], #%d", (int) offset
);
9969 func (stream
, ", #%d", (int) offset
);
9970 func (stream
, writeback
? "]!" : "]");
9975 func (stream
, "\t; ");
9976 info
->print_address_func (((pc
+ 4) & ~3) + offset
, info
);
9984 unsigned int U
= ! NEGATIVE_BIT_SET
;
9985 unsigned int W
= WRITEBACK_BIT_SET
;
9986 unsigned int Rn
= (given
& 0x000f0000) >> 16;
9987 unsigned int off
= (given
& 0x000000ff);
9989 func (stream
, "[%s", arm_regnames
[Rn
]);
9995 func (stream
, ", #%c%u", U
? '+' : '-', off
* 4);
9996 value_in_comment
= off
* 4 * (U
? 1 : -1);
10000 func (stream
, "!");
10004 func (stream
, "], ");
10007 func (stream
, "#%c%u", U
? '+' : '-', off
* 4);
10008 value_in_comment
= off
* 4 * (U
? 1 : -1);
10012 func (stream
, "{%u}", off
);
10013 value_in_comment
= off
;
10021 unsigned int Sbit
= (given
& 0x01000000) >> 24;
10022 unsigned int type
= (given
& 0x00600000) >> 21;
10026 case 0: func (stream
, Sbit
? "sb" : "b"); break;
10027 case 1: func (stream
, Sbit
? "sh" : "h"); break;
10030 func (stream
, "??");
10033 func (stream
, "??");
10041 /* Fall through. */
10047 func (stream
, "{");
10048 for (reg
= 0; reg
< 16; reg
++)
10049 if ((given
& (1 << reg
)) != 0)
10052 func (stream
, ", ");
10054 if (is_clrm
&& reg
== 13)
10055 func (stream
, "(invalid: %s)", arm_regnames
[reg
]);
10056 else if (is_clrm
&& reg
== 15)
10057 func (stream
, "%s", "APSR");
10059 func (stream
, "%s", arm_regnames
[reg
]);
10061 func (stream
, "}");
10067 unsigned int msb
= (given
& 0x0000001f);
10068 unsigned int lsb
= 0;
10070 lsb
|= (given
& 0x000000c0u
) >> 6;
10071 lsb
|= (given
& 0x00007000u
) >> 10;
10072 func (stream
, "#%u, #%u", lsb
, msb
- lsb
+ 1);
10078 unsigned int width
= (given
& 0x0000001f) + 1;
10079 unsigned int lsb
= 0;
10081 lsb
|= (given
& 0x000000c0u
) >> 6;
10082 lsb
|= (given
& 0x00007000u
) >> 10;
10083 func (stream
, "#%u, #%u", lsb
, width
);
10089 unsigned int boff
= (((given
& 0x07800000) >> 23) << 1);
10090 func (stream
, "%x", boff
);
10096 unsigned int immA
= (given
& 0x001f0000u
) >> 16;
10097 unsigned int immB
= (given
& 0x000007feu
) >> 1;
10098 unsigned int immC
= (given
& 0x00000800u
) >> 11;
10099 bfd_vma offset
= 0;
10101 offset
|= immA
<< 12;
10102 offset
|= immB
<< 2;
10103 offset
|= immC
<< 1;
10105 offset
= (offset
& 0x10000) ? offset
- (1 << 17) : offset
;
10107 info
->print_address_func (pc
+ 4 + offset
, info
);
10113 unsigned int immA
= (given
& 0x007f0000u
) >> 16;
10114 unsigned int immB
= (given
& 0x000007feu
) >> 1;
10115 unsigned int immC
= (given
& 0x00000800u
) >> 11;
10116 bfd_vma offset
= 0;
10118 offset
|= immA
<< 12;
10119 offset
|= immB
<< 2;
10120 offset
|= immC
<< 1;
10122 offset
= (offset
& 0x40000) ? offset
- (1 << 19) : offset
;
10124 info
->print_address_func (pc
+ 4 + offset
, info
);
10130 unsigned int immA
= (given
& 0x00010000u
) >> 16;
10131 unsigned int immB
= (given
& 0x000007feu
) >> 1;
10132 unsigned int immC
= (given
& 0x00000800u
) >> 11;
10133 bfd_vma offset
= 0;
10135 offset
|= immA
<< 12;
10136 offset
|= immB
<< 2;
10137 offset
|= immC
<< 1;
10139 offset
= (offset
& 0x1000) ? offset
- (1 << 13) : offset
;
10141 info
->print_address_func (pc
+ 4 + offset
, info
);
10143 unsigned int T
= (given
& 0x00020000u
) >> 17;
10144 unsigned int endoffset
= (((given
& 0x07800000) >> 23) << 1);
10145 unsigned int boffset
= (T
== 1) ? 4 : 2;
10146 func (stream
, ", ");
10147 func (stream
, "%x", endoffset
+ boffset
);
10153 unsigned int immh
= (given
& 0x000007feu
) >> 1;
10154 unsigned int imml
= (given
& 0x00000800u
) >> 11;
10157 imm32
|= immh
<< 2;
10158 imm32
|= imml
<< 1;
10160 info
->print_address_func (pc
+ 4 + imm32
, info
);
10166 unsigned int immh
= (given
& 0x000007feu
) >> 1;
10167 unsigned int imml
= (given
& 0x00000800u
) >> 11;
10170 imm32
|= immh
<< 2;
10171 imm32
|= imml
<< 1;
10173 info
->print_address_func (pc
+ 4 - imm32
, info
);
10179 unsigned int S
= (given
& 0x04000000u
) >> 26;
10180 unsigned int J1
= (given
& 0x00002000u
) >> 13;
10181 unsigned int J2
= (given
& 0x00000800u
) >> 11;
10182 bfd_vma offset
= 0;
10184 offset
|= !S
<< 20;
10185 offset
|= J2
<< 19;
10186 offset
|= J1
<< 18;
10187 offset
|= (given
& 0x003f0000) >> 4;
10188 offset
|= (given
& 0x000007ff) << 1;
10189 offset
-= (1 << 20);
10191 info
->print_address_func (pc
+ 4 + offset
, info
);
10197 unsigned int S
= (given
& 0x04000000u
) >> 26;
10198 unsigned int I1
= (given
& 0x00002000u
) >> 13;
10199 unsigned int I2
= (given
& 0x00000800u
) >> 11;
10200 bfd_vma offset
= 0;
10202 offset
|= !S
<< 24;
10203 offset
|= !(I1
^ S
) << 23;
10204 offset
|= !(I2
^ S
) << 22;
10205 offset
|= (given
& 0x03ff0000u
) >> 4;
10206 offset
|= (given
& 0x000007ffu
) << 1;
10207 offset
-= (1 << 24);
10210 /* BLX target addresses are always word aligned. */
10211 if ((given
& 0x00001000u
) == 0)
10214 info
->print_address_func (offset
, info
);
10220 unsigned int shift
= 0;
10222 shift
|= (given
& 0x000000c0u
) >> 6;
10223 shift
|= (given
& 0x00007000u
) >> 10;
10224 if (WRITEBACK_BIT_SET
)
10225 func (stream
, ", asr #%u", shift
);
10227 func (stream
, ", lsl #%u", shift
);
10228 /* else print nothing - lsl #0 */
10234 unsigned int rot
= (given
& 0x00000030) >> 4;
10237 func (stream
, ", ror #%u", rot
* 8);
10242 if ((given
& 0xf0) == 0x60)
10244 switch (given
& 0xf)
10246 case 0xf: func (stream
, "sy"); break;
10248 func (stream
, "#%d", (int) given
& 0xf);
10254 const char * opt
= data_barrier_option (given
& 0xf);
10256 func (stream
, "%s", opt
);
10258 func (stream
, "#%d", (int) given
& 0xf);
10263 if ((given
& 0xff) == 0)
10265 func (stream
, "%cPSR_", (given
& 0x100000) ? 'S' : 'C');
10267 func (stream
, "f");
10269 func (stream
, "s");
10271 func (stream
, "x");
10273 func (stream
, "c");
10275 else if ((given
& 0x20) == 0x20)
10278 unsigned sysm
= (given
& 0xf00) >> 8;
10280 sysm
|= (given
& 0x30);
10281 sysm
|= (given
& 0x00100000) >> 14;
10282 name
= banked_regname (sysm
);
10285 func (stream
, "%s", name
);
10287 func (stream
, "(UNDEF: %lu)", (unsigned long) sysm
);
10291 func (stream
, "%s", psr_name (given
& 0xff));
10296 if (((given
& 0xff) == 0)
10297 || ((given
& 0x20) == 0x20))
10300 unsigned sm
= (given
& 0xf0000) >> 16;
10302 sm
|= (given
& 0x30);
10303 sm
|= (given
& 0x00100000) >> 14;
10304 name
= banked_regname (sm
);
10307 func (stream
, "%s", name
);
10309 func (stream
, "(UNDEF: %lu)", (unsigned long) sm
);
10312 func (stream
, "%s", psr_name (given
& 0xff));
10315 case '0': case '1': case '2': case '3': case '4':
10316 case '5': case '6': case '7': case '8': case '9':
10321 c
= arm_decode_bitfield (c
, given
, &val
, &width
);
10327 func (stream
, "%s", mve_vec_sizename
[val
]);
10329 func (stream
, "<undef size>");
10333 func (stream
, "%lu", val
);
10334 value_in_comment
= val
;
10338 func (stream
, "%lu", val
+ 1);
10339 value_in_comment
= val
+ 1;
10343 func (stream
, "%lu", val
* 4);
10344 value_in_comment
= val
* 4;
10349 is_unpredictable
= TRUE
;
10350 /* Fall through. */
10353 is_unpredictable
= TRUE
;
10354 /* Fall through. */
10356 func (stream
, "%s", arm_regnames
[val
]);
10360 func (stream
, "%s", arm_conditional
[val
]);
10365 if (val
== ((1ul << width
) - 1))
10366 func (stream
, "%c", *c
);
10372 func (stream
, "%c", *c
);
10376 func (stream
, "%c", c
[(1 << width
) - (int) val
]);
10381 func (stream
, "0x%lx", val
& 0xffffffffUL
);
10391 /* PR binutils/12534
10392 If we have a PC relative offset in an LDRD or STRD
10393 instructions then display the decoded address. */
10394 if (((given
>> 16) & 0xf) == 0xf)
10396 bfd_vma offset
= (given
& 0xff) * 4;
10398 if ((given
& (1 << 23)) == 0)
10400 func (stream
, "\t; ");
10401 info
->print_address_func ((pc
& ~3) + 4 + offset
, info
);
10410 if (value_in_comment
> 32 || value_in_comment
< -16)
10411 func (stream
, "\t; 0x%lx", value_in_comment
);
10413 if (is_unpredictable
)
10414 func (stream
, UNPREDICTABLE_INSTRUCTION
);
10420 func (stream
, UNKNOWN_INSTRUCTION_32BIT
, (unsigned)given
);
10424 /* Print data bytes on INFO->STREAM. */
10427 print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED
,
10428 struct disassemble_info
*info
,
10431 switch (info
->bytes_per_chunk
)
10434 info
->fprintf_func (info
->stream
, ".byte\t0x%02lx", given
);
10437 info
->fprintf_func (info
->stream
, ".short\t0x%04lx", given
);
10440 info
->fprintf_func (info
->stream
, ".word\t0x%08lx", given
);
10447 /* Disallow mapping symbols ($a, $b, $d, $t etc) from
10448 being displayed in symbol relative addresses.
10450 Also disallow private symbol, with __tagsym$$ prefix,
10451 from ARM RVCT toolchain being displayed. */
10454 arm_symbol_is_valid (asymbol
* sym
,
10455 struct disassemble_info
* info ATTRIBUTE_UNUSED
)
10462 name
= bfd_asymbol_name (sym
);
10464 return (name
&& *name
!= '$' && strncmp (name
, "__tagsym$$", 10));
10467 /* Parse the string of disassembler options. */
10470 parse_arm_disassembler_options (const char *options
)
10474 FOR_EACH_DISASSEMBLER_OPTION (opt
, options
)
10476 if (CONST_STRNEQ (opt
, "reg-names-"))
10479 for (i
= 0; i
< NUM_ARM_OPTIONS
; i
++)
10480 if (disassembler_options_cmp (opt
, regnames
[i
].name
) == 0)
10482 regname_selected
= i
;
10486 if (i
>= NUM_ARM_OPTIONS
)
10487 /* xgettext: c-format */
10488 opcodes_error_handler (_("unrecognised register name set: %s"),
10491 else if (CONST_STRNEQ (opt
, "force-thumb"))
10493 else if (CONST_STRNEQ (opt
, "no-force-thumb"))
10496 /* xgettext: c-format */
10497 opcodes_error_handler (_("unrecognised disassembler option: %s"), opt
);
10504 mapping_symbol_for_insn (bfd_vma pc
, struct disassemble_info
*info
,
10505 enum map_type
*map_symbol
);
10507 /* Search back through the insn stream to determine if this instruction is
10508 conditionally executed. */
10511 find_ifthen_state (bfd_vma pc
,
10512 struct disassemble_info
*info
,
10513 bfd_boolean little
)
10515 unsigned char b
[2];
10518 /* COUNT is twice the number of instructions seen. It will be odd if we
10519 just crossed an instruction boundary. */
10522 unsigned int seen_it
;
10525 ifthen_address
= pc
;
10532 /* Scan backwards looking for IT instructions, keeping track of where
10533 instruction boundaries are. We don't know if something is actually an
10534 IT instruction until we find a definite instruction boundary. */
10537 if (addr
== 0 || info
->symbol_at_address_func (addr
, info
))
10539 /* A symbol must be on an instruction boundary, and will not
10540 be within an IT block. */
10541 if (seen_it
&& (count
& 1))
10547 status
= info
->read_memory_func (addr
, (bfd_byte
*) b
, 2, info
);
10552 insn
= (b
[0]) | (b
[1] << 8);
10554 insn
= (b
[1]) | (b
[0] << 8);
10557 if ((insn
& 0xf800) < 0xe800)
10559 /* Addr + 2 is an instruction boundary. See if this matches
10560 the expected boundary based on the position of the last
10567 if ((insn
& 0xff00) == 0xbf00 && (insn
& 0xf) != 0)
10569 enum map_type type
= MAP_ARM
;
10570 bfd_boolean found
= mapping_symbol_for_insn (addr
, info
, &type
);
10572 if (!found
|| (found
&& type
== MAP_THUMB
))
10574 /* This could be an IT instruction. */
10576 it_count
= count
>> 1;
10579 if ((insn
& 0xf800) >= 0xe800)
10582 count
= (count
+ 2) | 1;
10583 /* IT blocks contain at most 4 instructions. */
10584 if (count
>= 8 && !seen_it
)
10587 /* We found an IT instruction. */
10588 ifthen_state
= (seen_it
& 0xe0) | ((seen_it
<< it_count
) & 0x1f);
10589 if ((ifthen_state
& 0xf) == 0)
10593 /* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
10597 is_mapping_symbol (struct disassemble_info
*info
, int n
,
10598 enum map_type
*map_type
)
10602 name
= bfd_asymbol_name (info
->symtab
[n
]);
10603 if (name
[0] == '$' && (name
[1] == 'a' || name
[1] == 't' || name
[1] == 'd')
10604 && (name
[2] == 0 || name
[2] == '.'))
10606 *map_type
= ((name
[1] == 'a') ? MAP_ARM
10607 : (name
[1] == 't') ? MAP_THUMB
10615 /* Try to infer the code type (ARM or Thumb) from a mapping symbol.
10616 Returns nonzero if *MAP_TYPE was set. */
10619 get_map_sym_type (struct disassemble_info
*info
,
10621 enum map_type
*map_type
)
10623 /* If the symbol is in a different section, ignore it. */
10624 if (info
->section
!= NULL
&& info
->section
!= info
->symtab
[n
]->section
)
10627 return is_mapping_symbol (info
, n
, map_type
);
10630 /* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
10631 Returns nonzero if *MAP_TYPE was set. */
10634 get_sym_code_type (struct disassemble_info
*info
,
10636 enum map_type
*map_type
)
10638 elf_symbol_type
*es
;
10641 /* If the symbol is in a different section, ignore it. */
10642 if (info
->section
!= NULL
&& info
->section
!= info
->symtab
[n
]->section
)
10645 es
= *(elf_symbol_type
**)(info
->symtab
+ n
);
10646 type
= ELF_ST_TYPE (es
->internal_elf_sym
.st_info
);
10648 /* If the symbol has function type then use that. */
10649 if (type
== STT_FUNC
|| type
== STT_GNU_IFUNC
)
10651 if (ARM_GET_SYM_BRANCH_TYPE (es
->internal_elf_sym
.st_target_internal
)
10652 == ST_BRANCH_TO_THUMB
)
10653 *map_type
= MAP_THUMB
;
10655 *map_type
= MAP_ARM
;
10662 /* Search the mapping symbol state for instruction at pc. This is only
10663 applicable for elf target.
10665 There is an assumption Here, info->private_data contains the correct AND
10666 up-to-date information about current scan process. The information will be
10667 used to speed this search process.
10669 Return TRUE if the mapping state can be determined, and map_symbol
10670 will be updated accordingly. Otherwise, return FALSE. */
10673 mapping_symbol_for_insn (bfd_vma pc
, struct disassemble_info
*info
,
10674 enum map_type
*map_symbol
)
10676 bfd_vma addr
, section_vma
= 0;
10677 int n
, last_sym
= -1;
10678 bfd_boolean found
= FALSE
;
10679 bfd_boolean can_use_search_opt_p
= FALSE
;
10681 /* Default to DATA. A text section is required by the ABI to contain an
10682 INSN mapping symbol at the start. A data section has no such
10683 requirement, hence if no mapping symbol is found the section must
10684 contain only data. This however isn't very useful if the user has
10685 fully stripped the binaries. If this is the case use the section
10686 attributes to determine the default. If we have no section default to
10687 INSN as well, as we may be disassembling some raw bytes on a baremetal
10688 HEX file or similar. */
10689 enum map_type type
= MAP_DATA
;
10690 if ((info
->section
&& info
->section
->flags
& SEC_CODE
) || !info
->section
)
10692 struct arm_private_data
*private_data
;
10694 if (info
->private_data
== NULL
10695 || bfd_asymbol_flavour (*info
->symtab
) != bfd_target_elf_flavour
)
10698 private_data
= info
->private_data
;
10700 /* First, look for mapping symbols. */
10701 if (info
->symtab_size
!= 0)
10703 if (pc
<= private_data
->last_mapping_addr
)
10704 private_data
->last_mapping_sym
= -1;
10706 /* Start scanning at the start of the function, or wherever
10707 we finished last time. */
10708 n
= info
->symtab_pos
+ 1;
10710 /* If the last stop offset is different from the current one it means we
10711 are disassembling a different glob of bytes. As such the optimization
10712 would not be safe and we should start over. */
10713 can_use_search_opt_p
10714 = private_data
->last_mapping_sym
>= 0
10715 && info
->stop_offset
== private_data
->last_stop_offset
;
10717 if (n
>= private_data
->last_mapping_sym
&& can_use_search_opt_p
)
10718 n
= private_data
->last_mapping_sym
;
10720 /* Look down while we haven't passed the location being disassembled.
10721 The reason for this is that there's no defined order between a symbol
10722 and an mapping symbol that may be at the same address. We may have to
10723 look at least one position ahead. */
10724 for (; n
< info
->symtab_size
; n
++)
10726 addr
= bfd_asymbol_value (info
->symtab
[n
]);
10729 if (get_map_sym_type (info
, n
, &type
))
10738 n
= info
->symtab_pos
;
10739 if (n
>= private_data
->last_mapping_sym
&& can_use_search_opt_p
)
10740 n
= private_data
->last_mapping_sym
;
10742 /* No mapping symbol found at this address. Look backwards
10743 for a preceeding one, but don't go pass the section start
10744 otherwise a data section with no mapping symbol can pick up
10745 a text mapping symbol of a preceeding section. The documentation
10746 says section can be NULL, in which case we will seek up all the
10749 section_vma
= info
->section
->vma
;
10751 for (; n
>= 0; n
--)
10753 addr
= bfd_asymbol_value (info
->symtab
[n
]);
10754 if (addr
< section_vma
)
10757 if (get_map_sym_type (info
, n
, &type
))
10767 /* If no mapping symbol was found, try looking up without a mapping
10768 symbol. This is done by walking up from the current PC to the nearest
10769 symbol. We don't actually have to loop here since symtab_pos will
10770 contain the nearest symbol already. */
10773 n
= info
->symtab_pos
;
10774 if (n
>= 0 && get_sym_code_type (info
, n
, &type
))
10781 private_data
->last_mapping_sym
= last_sym
;
10782 private_data
->last_type
= type
;
10783 private_data
->last_stop_offset
= info
->stop_offset
;
10785 *map_symbol
= type
;
10789 /* Given a bfd_mach_arm_XXX value, this function fills in the fields
10790 of the supplied arm_feature_set structure with bitmasks indicating
10791 the supported base architectures and coprocessor extensions.
10793 FIXME: This could more efficiently implemented as a constant array,
10794 although it would also be less robust. */
10797 select_arm_features (unsigned long mach
,
10798 arm_feature_set
* features
)
10800 arm_feature_set arch_fset
;
10801 const arm_feature_set fpu_any
= FPU_ANY
;
10803 #undef ARM_SET_FEATURES
10804 #define ARM_SET_FEATURES(FSET) \
10806 const arm_feature_set fset = FSET; \
10807 arch_fset = fset; \
10810 /* When several architecture versions share the same bfd_mach_arm_XXX value
10811 the most featureful is chosen. */
10814 case bfd_mach_arm_2
: ARM_SET_FEATURES (ARM_ARCH_V2
); break;
10815 case bfd_mach_arm_2a
: ARM_SET_FEATURES (ARM_ARCH_V2S
); break;
10816 case bfd_mach_arm_3
: ARM_SET_FEATURES (ARM_ARCH_V3
); break;
10817 case bfd_mach_arm_3M
: ARM_SET_FEATURES (ARM_ARCH_V3M
); break;
10818 case bfd_mach_arm_4
: ARM_SET_FEATURES (ARM_ARCH_V4
); break;
10819 case bfd_mach_arm_4T
: ARM_SET_FEATURES (ARM_ARCH_V4T
); break;
10820 case bfd_mach_arm_5
: ARM_SET_FEATURES (ARM_ARCH_V5
); break;
10821 case bfd_mach_arm_5T
: ARM_SET_FEATURES (ARM_ARCH_V5T
); break;
10822 case bfd_mach_arm_5TE
: ARM_SET_FEATURES (ARM_ARCH_V5TE
); break;
10823 case bfd_mach_arm_XScale
: ARM_SET_FEATURES (ARM_ARCH_XSCALE
); break;
10824 case bfd_mach_arm_ep9312
:
10825 ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T
,
10826 ARM_CEXT_MAVERICK
| FPU_MAVERICK
));
10828 case bfd_mach_arm_iWMMXt
: ARM_SET_FEATURES (ARM_ARCH_IWMMXT
); break;
10829 case bfd_mach_arm_iWMMXt2
: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2
); break;
10830 case bfd_mach_arm_5TEJ
: ARM_SET_FEATURES (ARM_ARCH_V5TEJ
); break;
10831 case bfd_mach_arm_6
: ARM_SET_FEATURES (ARM_ARCH_V6
); break;
10832 case bfd_mach_arm_6KZ
: ARM_SET_FEATURES (ARM_ARCH_V6KZ
); break;
10833 case bfd_mach_arm_6T2
: ARM_SET_FEATURES (ARM_ARCH_V6KZT2
); break;
10834 case bfd_mach_arm_6K
: ARM_SET_FEATURES (ARM_ARCH_V6K
); break;
10835 case bfd_mach_arm_7
: ARM_SET_FEATURES (ARM_ARCH_V7VE
); break;
10836 case bfd_mach_arm_6M
: ARM_SET_FEATURES (ARM_ARCH_V6M
); break;
10837 case bfd_mach_arm_6SM
: ARM_SET_FEATURES (ARM_ARCH_V6SM
); break;
10838 case bfd_mach_arm_7EM
: ARM_SET_FEATURES (ARM_ARCH_V7EM
); break;
10839 case bfd_mach_arm_8
:
10841 /* Add bits for extensions that Armv8.5-A recognizes. */
10842 arm_feature_set armv8_5_ext_fset
10843 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
10844 ARM_SET_FEATURES (ARM_ARCH_V8_5A
);
10845 ARM_MERGE_FEATURE_SETS (arch_fset
, arch_fset
, armv8_5_ext_fset
);
10848 case bfd_mach_arm_8R
: ARM_SET_FEATURES (ARM_ARCH_V8R
); break;
10849 case bfd_mach_arm_8M_BASE
: ARM_SET_FEATURES (ARM_ARCH_V8M_BASE
); break;
10850 case bfd_mach_arm_8M_MAIN
: ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN
); break;
10851 case bfd_mach_arm_8_1M_MAIN
:
10852 ARM_SET_FEATURES (ARM_ARCH_V8_1M_MAIN
);
10855 /* If the machine type is unknown allow all architecture types and all
10857 case bfd_mach_arm_unknown
: ARM_SET_FEATURES (ARM_FEATURE_ALL
); break;
10861 #undef ARM_SET_FEATURES
10863 /* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch
10864 and thus on bfd_mach_arm_XXX value. Therefore for a given
10865 bfd_mach_arm_XXX value all coprocessor feature bits should be allowed. */
10866 ARM_MERGE_FEATURE_SETS (*features
, arch_fset
, fpu_any
);
10870 /* NOTE: There are no checks in these routines that
10871 the relevant number of data bytes exist. */
10874 print_insn (bfd_vma pc
, struct disassemble_info
*info
, bfd_boolean little
)
10876 unsigned char b
[4];
10879 int is_thumb
= FALSE
;
10880 int is_data
= FALSE
;
10882 unsigned int size
= 4;
10883 void (*printer
) (bfd_vma
, struct disassemble_info
*, long);
10884 bfd_boolean found
= FALSE
;
10885 struct arm_private_data
*private_data
;
10887 if (info
->disassembler_options
)
10889 parse_arm_disassembler_options (info
->disassembler_options
);
10891 /* To avoid repeated parsing of these options, we remove them here. */
10892 info
->disassembler_options
= NULL
;
10895 /* PR 10288: Control which instructions will be disassembled. */
10896 if (info
->private_data
== NULL
)
10898 static struct arm_private_data
private;
10900 if ((info
->flags
& USER_SPECIFIED_MACHINE_TYPE
) == 0)
10901 /* If the user did not use the -m command line switch then default to
10902 disassembling all types of ARM instruction.
10904 The info->mach value has to be ignored as this will be based on
10905 the default archictecture for the target and/or hints in the notes
10906 section, but it will never be greater than the current largest arm
10907 machine value (iWMMXt2), which is only equivalent to the V5TE
10908 architecture. ARM architectures have advanced beyond the machine
10909 value encoding, and these newer architectures would be ignored if
10910 the machine value was used.
10912 Ie the -m switch is used to restrict which instructions will be
10913 disassembled. If it is necessary to use the -m switch to tell
10914 objdump that an ARM binary is being disassembled, eg because the
10915 input is a raw binary file, but it is also desired to disassemble
10916 all ARM instructions then use "-marm". This will select the
10917 "unknown" arm architecture which is compatible with any ARM
10919 info
->mach
= bfd_mach_arm_unknown
;
10921 /* Compute the architecture bitmask from the machine number.
10922 Note: This assumes that the machine number will not change
10923 during disassembly.... */
10924 select_arm_features (info
->mach
, & private.features
);
10926 private.last_mapping_sym
= -1;
10927 private.last_mapping_addr
= 0;
10928 private.last_stop_offset
= 0;
10930 info
->private_data
= & private;
10933 private_data
= info
->private_data
;
10935 /* Decide if our code is going to be little-endian, despite what the
10936 function argument might say. */
10937 little_code
= ((info
->endian_code
== BFD_ENDIAN_LITTLE
) || little
);
10939 /* For ELF, consult the symbol table to determine what kind of code
10940 or data we have. */
10941 if (info
->symtab_size
!= 0
10942 && bfd_asymbol_flavour (*info
->symtab
) == bfd_target_elf_flavour
)
10947 enum map_type type
= MAP_ARM
;
10949 found
= mapping_symbol_for_insn (pc
, info
, &type
);
10950 last_sym
= private_data
->last_mapping_sym
;
10952 is_thumb
= (private_data
->last_type
== MAP_THUMB
);
10953 is_data
= (private_data
->last_type
== MAP_DATA
);
10955 /* Look a little bit ahead to see if we should print out
10956 two or four bytes of data. If there's a symbol,
10957 mapping or otherwise, after two bytes then don't
10961 size
= 4 - (pc
& 3);
10962 for (n
= last_sym
+ 1; n
< info
->symtab_size
; n
++)
10964 addr
= bfd_asymbol_value (info
->symtab
[n
]);
10966 && (info
->section
== NULL
10967 || info
->section
== info
->symtab
[n
]->section
))
10969 if (addr
- pc
< size
)
10974 /* If the next symbol is after three bytes, we need to
10975 print only part of the data, so that we can use either
10976 .byte or .short. */
10978 size
= (pc
& 1) ? 1 : 2;
10982 if (info
->symbols
!= NULL
)
10984 if (bfd_asymbol_flavour (*info
->symbols
) == bfd_target_coff_flavour
)
10986 coff_symbol_type
* cs
;
10988 cs
= coffsymbol (*info
->symbols
);
10989 is_thumb
= ( cs
->native
->u
.syment
.n_sclass
== C_THUMBEXT
10990 || cs
->native
->u
.syment
.n_sclass
== C_THUMBSTAT
10991 || cs
->native
->u
.syment
.n_sclass
== C_THUMBLABEL
10992 || cs
->native
->u
.syment
.n_sclass
== C_THUMBEXTFUNC
10993 || cs
->native
->u
.syment
.n_sclass
== C_THUMBSTATFUNC
);
10995 else if (bfd_asymbol_flavour (*info
->symbols
) == bfd_target_elf_flavour
10998 /* If no mapping symbol has been found then fall back to the type
10999 of the function symbol. */
11000 elf_symbol_type
* es
;
11003 es
= *(elf_symbol_type
**)(info
->symbols
);
11004 type
= ELF_ST_TYPE (es
->internal_elf_sym
.st_info
);
11007 ((ARM_GET_SYM_BRANCH_TYPE (es
->internal_elf_sym
.st_target_internal
)
11008 == ST_BRANCH_TO_THUMB
) || type
== STT_ARM_16BIT
);
11010 else if (bfd_asymbol_flavour (*info
->symbols
)
11011 == bfd_target_mach_o_flavour
)
11013 bfd_mach_o_asymbol
*asym
= (bfd_mach_o_asymbol
*)*info
->symbols
;
11015 is_thumb
= (asym
->n_desc
& BFD_MACH_O_N_ARM_THUMB_DEF
);
11023 info
->display_endian
= little
? BFD_ENDIAN_LITTLE
: BFD_ENDIAN_BIG
;
11025 info
->display_endian
= little_code
? BFD_ENDIAN_LITTLE
: BFD_ENDIAN_BIG
;
11027 info
->bytes_per_line
= 4;
11029 /* PR 10263: Disassemble data if requested to do so by the user. */
11030 if (is_data
&& ((info
->flags
& DISASSEMBLE_DATA
) == 0))
11034 /* Size was already set above. */
11035 info
->bytes_per_chunk
= size
;
11036 printer
= print_insn_data
;
11038 status
= info
->read_memory_func (pc
, (bfd_byte
*) b
, size
, info
);
11041 for (i
= size
- 1; i
>= 0; i
--)
11042 given
= b
[i
] | (given
<< 8);
11044 for (i
= 0; i
< (int) size
; i
++)
11045 given
= b
[i
] | (given
<< 8);
11047 else if (!is_thumb
)
11049 /* In ARM mode endianness is a straightforward issue: the instruction
11050 is four bytes long and is either ordered 0123 or 3210. */
11051 printer
= print_insn_arm
;
11052 info
->bytes_per_chunk
= 4;
11055 status
= info
->read_memory_func (pc
, (bfd_byte
*) b
, 4, info
);
11057 given
= (b
[0]) | (b
[1] << 8) | (b
[2] << 16) | (b
[3] << 24);
11059 given
= (b
[3]) | (b
[2] << 8) | (b
[1] << 16) | (b
[0] << 24);
11063 /* In Thumb mode we have the additional wrinkle of two
11064 instruction lengths. Fortunately, the bits that determine
11065 the length of the current instruction are always to be found
11066 in the first two bytes. */
11067 printer
= print_insn_thumb16
;
11068 info
->bytes_per_chunk
= 2;
11071 status
= info
->read_memory_func (pc
, (bfd_byte
*) b
, 2, info
);
11073 given
= (b
[0]) | (b
[1] << 8);
11075 given
= (b
[1]) | (b
[0] << 8);
11079 /* These bit patterns signal a four-byte Thumb
11081 if ((given
& 0xF800) == 0xF800
11082 || (given
& 0xF800) == 0xF000
11083 || (given
& 0xF800) == 0xE800)
11085 status
= info
->read_memory_func (pc
+ 2, (bfd_byte
*) b
, 2, info
);
11087 given
= (b
[0]) | (b
[1] << 8) | (given
<< 16);
11089 given
= (b
[1]) | (b
[0] << 8) | (given
<< 16);
11091 printer
= print_insn_thumb32
;
11096 if (ifthen_address
!= pc
)
11097 find_ifthen_state (pc
, info
, little_code
);
11101 if ((ifthen_state
& 0xf) == 0x8)
11102 ifthen_next_state
= 0;
11104 ifthen_next_state
= (ifthen_state
& 0xe0)
11105 | ((ifthen_state
& 0xf) << 1);
11111 info
->memory_error_func (status
, pc
, info
);
11114 if (info
->flags
& INSN_HAS_RELOC
)
11115 /* If the instruction has a reloc associated with it, then
11116 the offset field in the instruction will actually be the
11117 addend for the reloc. (We are using REL type relocs).
11118 In such cases, we can ignore the pc when computing
11119 addresses, since the addend is not currently pc-relative. */
11122 printer (pc
, info
, given
);
11126 ifthen_state
= ifthen_next_state
;
11127 ifthen_address
+= size
;
11133 print_insn_big_arm (bfd_vma pc
, struct disassemble_info
*info
)
11135 /* Detect BE8-ness and record it in the disassembler info. */
11136 if (info
->flavour
== bfd_target_elf_flavour
11137 && info
->section
!= NULL
11138 && (elf_elfheader (info
->section
->owner
)->e_flags
& EF_ARM_BE8
))
11139 info
->endian_code
= BFD_ENDIAN_LITTLE
;
11141 return print_insn (pc
, info
, FALSE
);
11145 print_insn_little_arm (bfd_vma pc
, struct disassemble_info
*info
)
11147 return print_insn (pc
, info
, TRUE
);
11150 const disasm_options_and_args_t
*
11151 disassembler_options_arm (void)
11153 static disasm_options_and_args_t
*opts_and_args
;
11155 if (opts_and_args
== NULL
)
11157 disasm_options_t
*opts
;
11160 opts_and_args
= XNEW (disasm_options_and_args_t
);
11161 opts_and_args
->args
= NULL
;
11163 opts
= &opts_and_args
->options
;
11164 opts
->name
= XNEWVEC (const char *, NUM_ARM_OPTIONS
+ 1);
11165 opts
->description
= XNEWVEC (const char *, NUM_ARM_OPTIONS
+ 1);
11167 for (i
= 0; i
< NUM_ARM_OPTIONS
; i
++)
11169 opts
->name
[i
] = regnames
[i
].name
;
11170 if (regnames
[i
].description
!= NULL
)
11171 opts
->description
[i
] = _(regnames
[i
].description
);
11173 opts
->description
[i
] = NULL
;
11175 /* The array we return must be NULL terminated. */
11176 opts
->name
[i
] = NULL
;
11177 opts
->description
[i
] = NULL
;
11180 return opts_and_args
;
11184 print_arm_disassembler_options (FILE *stream
)
11186 unsigned int i
, max_len
= 0;
11187 fprintf (stream
, _("\n\
11188 The following ARM specific disassembler options are supported for use with\n\
11189 the -M switch:\n"));
11191 for (i
= 0; i
< NUM_ARM_OPTIONS
; i
++)
11193 unsigned int len
= strlen (regnames
[i
].name
);
11198 for (i
= 0, max_len
++; i
< NUM_ARM_OPTIONS
; i
++)
11199 fprintf (stream
, " %s%*c %s\n",
11201 (int)(max_len
- strlen (regnames
[i
].name
)), ' ',
11202 _(regnames
[i
].description
));