opcodes/arm-dis.c

   1 /* Instruction printing code for the ARM
   2    Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
   3    2004, 2005, 2006, 2007, 2008, 2009, 2010, 2012
   4    Free Software Foundation, Inc.
   5    Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
   6    Modification by James G. Smith (jsmith@cygnus.co.uk)
   7
   8    This file is part of libopcodes.
   9
  10    This library is free software; you can redistribute it and/or modify
  11    it under the terms of the GNU General Public License as published by
  12    the Free Software Foundation; either version 3 of the License, or
  13    (at your option) any later version.
  14
  15    It is distributed in the hope that it will be useful, but WITHOUT
  16    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  17    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  18    License for more details.
  19
  20    You should have received a copy of the GNU General Public License
  21    along with this program; if not, write to the Free Software
  22    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  23    MA 02110-1301, USA.  */
  24
  25 #include "sysdep.h"
  26
  27 #include "dis-asm.h"
  28 #include "opcode/arm.h"
  29 #include "opintl.h"
  30 #include "safe-ctype.h"
  31 #include "floatformat.h"
  32
  33 /* FIXME: This shouldn't be done here.  */
  34 #include "coff/internal.h"
  35 #include "libcoff.h"
  36 #include "elf-bfd.h"
  37 #include "elf/internal.h"
  38 #include "elf/arm.h"
  39
  40 /* FIXME: Belongs in global header.  */
  41 #ifndef strneq
  42 #define strneq(a,b,n)   (strncmp ((a), (b), (n)) == 0)
  43 #endif
  44
  45 #ifndef NUM_ELEM
  46 #define NUM_ELEM(a)     (sizeof (a) / sizeof (a)[0])
  47 #endif
  48
  49 /* Cached mapping symbol state.  */
  50 enum map_type
  51 {
  52   MAP_ARM,
  53   MAP_THUMB,
  54   MAP_DATA
  55 };
  56
  57 struct arm_private_data
  58 {
  59   /* The features to use when disassembling optional instructions.  */
  60   arm_feature_set features;
  61
  62   /* Whether any mapping symbols are present in the provided symbol
  63      table.  -1 if we do not know yet, otherwise 0 or 1.  */
  64   int has_mapping_symbols;
  65
  66   /* Track the last type (although this doesn't seem to be useful) */
  67   enum map_type last_type;
  68
  69   /* Tracking symbol table information */
  70   int last_mapping_sym;
  71   bfd_vma last_mapping_addr;
  72 };
  73
  74 struct opcode32
  75 {
  76   unsigned long arch;           /* Architecture defining this insn.  */
  77   unsigned long value;          /* If arch == 0 then value is a sentinel.  */
  78   unsigned long mask;           /* Recognise insn if (op & mask) == value.  */
  79   const char *  assembler;      /* How to disassemble this insn.  */
  80 };
  81
  82 struct opcode16
  83 {
  84   unsigned long arch;           /* Architecture defining this insn.  */
  85   unsigned short value, mask;   /* Recognise insn if (op & mask) == value.  */
  86   const char *assembler;        /* How to disassemble this insn.  */
  87 };
  88
  89 /* print_insn_coprocessor recognizes the following format control codes:
  90
  91    %%                   %
  92
  93    %c                   print condition code (always bits 28-31 in ARM mode)
  94    %q                   print shifter argument
  95    %u                   print condition code (unconditional in ARM mode,
  96                           UNPREDICTABLE if not AL in Thumb)
  97    %A                   print address for ldc/stc/ldf/stf instruction
  98    %B                   print vstm/vldm register list
  99    %I                   print cirrus signed shift immediate: bits 0..3|4..6
 100    %F                   print the COUNT field of a LFM/SFM instruction.
 101    %P                   print floating point precision in arithmetic insn
 102    %Q                   print floating point precision in ldf/stf insn
 103    %R                   print floating point rounding mode
 104
 105    %<bitfield>c         print as a condition code (for vsel)
 106    %<bitfield>r         print as an ARM register
 107    %<bitfield>R         as %<>r but r15 is UNPREDICTABLE
 108    %<bitfield>ru        as %<>r but each u register must be unique.
 109    %<bitfield>d         print the bitfield in decimal
 110    %<bitfield>k         print immediate for VFPv3 conversion instruction
 111    %<bitfield>x         print the bitfield in hex
 112    %<bitfield>X         print the bitfield as 1 hex digit without leading "0x"
 113    %<bitfield>f         print a floating point constant if >7 else a
 114                         floating point register
 115    %<bitfield>w         print as an iWMMXt width field - [bhwd]ss/us
 116    %<bitfield>g         print as an iWMMXt 64-bit register
 117    %<bitfield>G         print as an iWMMXt general purpose or control register
 118    %<bitfield>D         print as a NEON D register
 119    %<bitfield>Q         print as a NEON Q register
 120
 121    %y<code>             print a single precision VFP reg.
 122                           Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
 123    %z<code>             print a double precision VFP reg
 124                           Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
 125
 126    %<bitfield>'c        print specified char iff bitfield is all ones
 127    %<bitfield>`c        print specified char iff bitfield is all zeroes
 128    %<bitfield>?ab...    select from array of values in big endian order
 129
 130    %L                   print as an iWMMXt N/M width field.
 131    %Z                   print the Immediate of a WSHUFH instruction.
 132    %l                   like 'A' except use byte offsets for 'B' & 'H'
 133                         versions.
 134    %i                   print 5-bit immediate in bits 8,3..0
 135                         (print "32" when 0)
 136    %r                   print register offset address for wldt/wstr instruction.  */
 137
 138 enum opcode_sentinel_enum
 139 {
 140   SENTINEL_IWMMXT_START = 1,
 141   SENTINEL_IWMMXT_END,
 142   SENTINEL_GENERIC_START
 143 } opcode_sentinels;
 144
 145 #define UNDEFINED_INSTRUCTION      "\t\t; <UNDEFINED> instruction: %0-31x"
 146 #define UNPREDICTABLE_INSTRUCTION  "\t; <UNPREDICTABLE>"
 147
 148 /* Common coprocessor opcodes shared between Arm and Thumb-2.  */
 149
 150 static const struct opcode32 coprocessor_opcodes[] =
 151 {
 152   /* XScale instructions.  */
 153   {ARM_CEXT_XSCALE, 0x0e200010, 0x0fff0ff0, "mia%c\tacc0, %0-3r, %12-15r"},
 154   {ARM_CEXT_XSCALE, 0x0e280010, 0x0fff0ff0, "miaph%c\tacc0, %0-3r, %12-15r"},
 155   {ARM_CEXT_XSCALE, 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
 156   {ARM_CEXT_XSCALE, 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
 157   {ARM_CEXT_XSCALE, 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
 158
 159   /* Intel Wireless MMX technology instructions.  */
 160   { 0, SENTINEL_IWMMXT_START, 0, "" },
 161   {ARM_CEXT_IWMMXT, 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
 162   {ARM_CEXT_XSCALE, 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
 163   {ARM_CEXT_XSCALE, 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
 164   {ARM_CEXT_XSCALE, 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
 165   {ARM_CEXT_XSCALE, 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
 166   {ARM_CEXT_XSCALE, 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
 167   {ARM_CEXT_XSCALE, 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
 168   {ARM_CEXT_XSCALE, 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
 169   {ARM_CEXT_XSCALE, 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
 170   {ARM_CEXT_XSCALE, 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
 171   {ARM_CEXT_XSCALE, 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
 172   {ARM_CEXT_XSCALE, 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
 173   {ARM_CEXT_XSCALE, 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
 174   {ARM_CEXT_XSCALE, 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
 175   {ARM_CEXT_XSCALE, 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
 176   {ARM_CEXT_XSCALE, 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
 177   {ARM_CEXT_XSCALE, 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
 178   {ARM_CEXT_XSCALE, 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
 179   {ARM_CEXT_XSCALE, 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
 180   {ARM_CEXT_XSCALE, 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
 181   {ARM_CEXT_XSCALE, 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
 182   {ARM_CEXT_XSCALE, 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
 183   {ARM_CEXT_XSCALE, 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
 184   {ARM_CEXT_XSCALE, 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
 185   {ARM_CEXT_XSCALE, 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
 186   {ARM_CEXT_XSCALE, 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 187   {ARM_CEXT_XSCALE, 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 188   {ARM_CEXT_XSCALE, 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
 189   {ARM_CEXT_XSCALE, 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
 190   {ARM_CEXT_XSCALE, 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
 191   {ARM_CEXT_XSCALE, 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
 192   {ARM_CEXT_XSCALE, 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
 193   {ARM_CEXT_XSCALE, 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
 194   {ARM_CEXT_XSCALE, 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 195   {ARM_CEXT_XSCALE, 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
 196   {ARM_CEXT_XSCALE, 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
 197   {ARM_CEXT_XSCALE, 0x0e800120, 0x0f800ff0, "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
 198   {ARM_CEXT_XSCALE, 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 199   {ARM_CEXT_XSCALE, 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
 200   {ARM_CEXT_XSCALE, 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
 201   {ARM_CEXT_XSCALE, 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
 202   {ARM_CEXT_XSCALE, 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
 203   {ARM_CEXT_XSCALE, 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
 204   {ARM_CEXT_XSCALE, 0x0e8000a0, 0x0f800ff0, "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
 205   {ARM_CEXT_XSCALE, 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
 206   {ARM_CEXT_XSCALE, 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
 207   {ARM_CEXT_XSCALE, 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
 208   {ARM_CEXT_XSCALE, 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
 209   {ARM_CEXT_XSCALE, 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
 210   {ARM_CEXT_XSCALE, 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 211   {ARM_CEXT_XSCALE, 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
 212   {ARM_CEXT_XSCALE, 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
 213   {ARM_CEXT_XSCALE, 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
 214   {ARM_CEXT_XSCALE, 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
 215   {ARM_CEXT_XSCALE, 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
 216   {ARM_CEXT_XSCALE, 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
 217   {ARM_CEXT_XSCALE, 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
 218   {ARM_CEXT_XSCALE, 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
 219   {ARM_CEXT_XSCALE, 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
 220   {ARM_CEXT_XSCALE, 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
 221   {ARM_CEXT_XSCALE, 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
 222   {ARM_CEXT_XSCALE, 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
 223   {ARM_CEXT_XSCALE, 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
 224   {ARM_CEXT_XSCALE, 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
 225   {ARM_CEXT_XSCALE, 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
 226   {ARM_CEXT_XSCALE, 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
 227   {ARM_CEXT_XSCALE, 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
 228   {ARM_CEXT_XSCALE, 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 229   {ARM_CEXT_XSCALE, 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
 230   {ARM_CEXT_XSCALE, 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
 231   {ARM_CEXT_XSCALE, 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
 232   {ARM_CEXT_XSCALE, 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
 233   {ARM_CEXT_XSCALE, 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 234   {ARM_CEXT_XSCALE, 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 235   {ARM_CEXT_XSCALE, 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
 236   { 0, SENTINEL_IWMMXT_END, 0, "" },
 237
 238   /* Floating point coprocessor (FPA) instructions.  */
 239   {FPU_FPA_EXT_V1, 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 240   {FPU_FPA_EXT_V1, 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 241   {FPU_FPA_EXT_V1, 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 242   {FPU_FPA_EXT_V1, 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 243   {FPU_FPA_EXT_V1, 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 244   {FPU_FPA_EXT_V1, 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 245   {FPU_FPA_EXT_V1, 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
 246   {FPU_FPA_EXT_V1, 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
 247   {FPU_FPA_EXT_V1, 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 248   {FPU_FPA_EXT_V1, 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
 249   {FPU_FPA_EXT_V1, 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
 250   {FPU_FPA_EXT_V1, 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
 251   {FPU_FPA_EXT_V1, 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
 252   {FPU_FPA_EXT_V1, 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
 253   {FPU_FPA_EXT_V1, 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
 254   {FPU_FPA_EXT_V1, 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
 255   {FPU_FPA_EXT_V1, 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
 256   {FPU_FPA_EXT_V1, 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
 257   {FPU_FPA_EXT_V1, 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
 258   {FPU_FPA_EXT_V1, 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
 259   {FPU_FPA_EXT_V1, 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
 260   {FPU_FPA_EXT_V1, 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
 261   {FPU_FPA_EXT_V1, 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
 262   {FPU_FPA_EXT_V1, 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
 263   {FPU_FPA_EXT_V1, 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
 264   {FPU_FPA_EXT_V1, 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
 265   {FPU_FPA_EXT_V1, 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
 266   {FPU_FPA_EXT_V1, 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
 267   {FPU_FPA_EXT_V1, 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
 268   {FPU_FPA_EXT_V1, 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
 269   {FPU_FPA_EXT_V1, 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
 270   {FPU_FPA_EXT_V1, 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
 271   {FPU_FPA_EXT_V1, 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
 272   {FPU_FPA_EXT_V1, 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
 273   {FPU_FPA_EXT_V1, 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
 274   {FPU_FPA_EXT_V1, 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
 275   {FPU_FPA_EXT_V1, 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
 276   {FPU_FPA_EXT_V1, 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
 277   {FPU_FPA_EXT_V1, 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
 278   {FPU_FPA_EXT_V1, 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
 279   {FPU_FPA_EXT_V1, 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
 280   {FPU_FPA_EXT_V2, 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
 281   {FPU_FPA_EXT_V2, 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
 282
 283   /* Register load/store.  */
 284   {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
 285   {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
 286   {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
 287   {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
 288   {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
 289   {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
 290   {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
 291   {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
 292   {FPU_VFP_EXT_V1xD, 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
 293   {FPU_VFP_EXT_V1xD, 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
 294   {FPU_VFP_EXT_V1xD, 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
 295   {FPU_VFP_EXT_V1xD, 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
 296   {FPU_VFP_EXT_V1xD, 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
 297   {FPU_VFP_EXT_V1xD, 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
 298   {FPU_VFP_EXT_V1xD, 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
 299   {FPU_VFP_EXT_V1xD, 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
 300
 301   {FPU_VFP_EXT_V1xD, 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
 302   {FPU_VFP_EXT_V1xD, 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
 303   {FPU_VFP_EXT_V1xD, 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
 304   {FPU_VFP_EXT_V1xD, 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
 305
 306   /* Data transfer between ARM and NEON registers.  */
 307   {FPU_NEON_EXT_V1, 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
 308   {FPU_NEON_EXT_V1, 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
 309   {FPU_NEON_EXT_V1, 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
 310   {FPU_NEON_EXT_V1, 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
 311   {FPU_NEON_EXT_V1, 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
 312   {FPU_NEON_EXT_V1, 0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
 313   {FPU_NEON_EXT_V1, 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
 314   {FPU_NEON_EXT_V1, 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
 315   {FPU_NEON_EXT_V1, 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
 316   {FPU_NEON_EXT_V1, 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
 317   {FPU_NEON_EXT_V1, 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
 318   {FPU_NEON_EXT_V1, 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
 319   {FPU_NEON_EXT_V1, 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
 320   {FPU_NEON_EXT_V1, 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
 321   /* Half-precision conversion instructions.  */
 322   {FPU_VFP_EXT_FP16, 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
 323   {FPU_VFP_EXT_FP16, 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
 324
 325   /* Floating point coprocessor (VFP) instructions.  */
 326   {FPU_VFP_EXT_V1xD, 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
 327   {FPU_VFP_EXT_V1xD, 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
 328   {FPU_VFP_EXT_V1xD, 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
 329   {FPU_VFP_EXT_V1xD, 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
 330   {FPU_VFP_EXT_V1xD, 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
 331   {FPU_VFP_EXT_V1xD, 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
 332   {FPU_VFP_EXT_V1xD, 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
 333   {FPU_VFP_EXT_V1xD, 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
 334   {FPU_VFP_EXT_V1xD, 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
 335   {FPU_VFP_EXT_V1xD, 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
 336   {FPU_VFP_EXT_V1xD, 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
 337   {FPU_VFP_EXT_V1xD, 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
 338   {FPU_VFP_EXT_V1xD, 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
 339   {FPU_VFP_EXT_V1xD, 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
 340   {FPU_VFP_EXT_V1xD, 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
 341   {FPU_VFP_EXT_V1, 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
 342   {FPU_VFP_EXT_V1, 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
 343   {FPU_VFP_EXT_V1xD, 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
 344   {FPU_VFP_EXT_V1xD, 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
 345   {FPU_VFP_EXT_V1xD, 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
 346   {FPU_VFP_EXT_V1xD, 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
 347   {FPU_VFP_EXT_V1xD, 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
 348   {FPU_VFP_EXT_V1, 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
 349   {FPU_VFP_EXT_V1xD, 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
 350   {FPU_VFP_EXT_V1xD, 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
 351   {FPU_VFP_EXT_V1, 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
 352   {FPU_VFP_EXT_V1, 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
 353   {FPU_VFP_EXT_V1xD, 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
 354   {FPU_VFP_EXT_V1xD, 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
 355   {FPU_VFP_EXT_V1, 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
 356   {FPU_VFP_EXT_V1, 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
 357   {FPU_VFP_EXT_V1, 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
 358   {FPU_VFP_EXT_V1, 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
 359   {FPU_VFP_EXT_V1xD, 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
 360   {FPU_VFP_EXT_V1, 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
 361   {FPU_VFP_EXT_V1xD, 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
 362   {FPU_VFP_EXT_V1, 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
 363   {FPU_VFP_EXT_V3xD, 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
 364   {FPU_VFP_EXT_V3, 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
 365   {FPU_VFP_EXT_V1xD, 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
 366   {FPU_VFP_EXT_V1, 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
 367   {FPU_VFP_EXT_V3xD, 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
 368   {FPU_VFP_EXT_V3, 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
 369   {FPU_VFP_EXT_V1, 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
 370   {FPU_VFP_EXT_V3xD, 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19d"},
 371   {FPU_VFP_EXT_V3, 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19d"},
 372   {FPU_VFP_EXT_V2, 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
 373   {FPU_VFP_EXT_V2, 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
 374   {FPU_VFP_EXT_V2, 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
 375   {FPU_VFP_EXT_V1xD, 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
 376   {FPU_VFP_EXT_V1xD, 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
 377   {FPU_VFP_EXT_V1, 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
 378   {FPU_VFP_EXT_V1, 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
 379   {FPU_VFP_EXT_V1xD, 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
 380   {FPU_VFP_EXT_V1xD, 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
 381   {FPU_VFP_EXT_V1, 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
 382   {FPU_VFP_EXT_V1, 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
 383   {FPU_VFP_EXT_V1xD, 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
 384   {FPU_VFP_EXT_V1xD, 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
 385   {FPU_VFP_EXT_V1, 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
 386   {FPU_VFP_EXT_V1, 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
 387   {FPU_VFP_EXT_V1xD, 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
 388   {FPU_VFP_EXT_V1xD, 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
 389   {FPU_VFP_EXT_V1, 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
 390   {FPU_VFP_EXT_V1, 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
 391   {FPU_VFP_EXT_V1xD, 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
 392   {FPU_VFP_EXT_V1, 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
 393
 394   /* Cirrus coprocessor instructions.  */
 395   {ARM_CEXT_MAVERICK, 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
 396   {ARM_CEXT_MAVERICK, 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
 397   {ARM_CEXT_MAVERICK, 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
 398   {ARM_CEXT_MAVERICK, 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
 399   {ARM_CEXT_MAVERICK, 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
 400   {ARM_CEXT_MAVERICK, 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
 401   {ARM_CEXT_MAVERICK, 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
 402   {ARM_CEXT_MAVERICK, 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
 403   {ARM_CEXT_MAVERICK, 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
 404   {ARM_CEXT_MAVERICK, 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
 405   {ARM_CEXT_MAVERICK, 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
 406   {ARM_CEXT_MAVERICK, 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
 407   {ARM_CEXT_MAVERICK, 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
 408   {ARM_CEXT_MAVERICK, 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
 409   {ARM_CEXT_MAVERICK, 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
 410   {ARM_CEXT_MAVERICK, 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
 411   {ARM_CEXT_MAVERICK, 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
 412   {ARM_CEXT_MAVERICK, 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
 413   {ARM_CEXT_MAVERICK, 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
 414   {ARM_CEXT_MAVERICK, 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
 415   {ARM_CEXT_MAVERICK, 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
 416   {ARM_CEXT_MAVERICK, 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
 417   {ARM_CEXT_MAVERICK, 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
 418   {ARM_CEXT_MAVERICK, 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
 419   {ARM_CEXT_MAVERICK, 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
 420   {ARM_CEXT_MAVERICK, 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
 421   {ARM_CEXT_MAVERICK, 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
 422   {ARM_CEXT_MAVERICK, 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
 423   {ARM_CEXT_MAVERICK, 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
 424   {ARM_CEXT_MAVERICK, 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
 425   {ARM_CEXT_MAVERICK, 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
 426   {ARM_CEXT_MAVERICK, 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
 427   {ARM_CEXT_MAVERICK, 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
 428   {ARM_CEXT_MAVERICK, 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
 429   {ARM_CEXT_MAVERICK, 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
 430   {ARM_CEXT_MAVERICK, 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
 431   {ARM_CEXT_MAVERICK, 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
 432   {ARM_CEXT_MAVERICK, 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
 433   {ARM_CEXT_MAVERICK, 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
 434   {ARM_CEXT_MAVERICK, 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
 435   {ARM_CEXT_MAVERICK, 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
 436   {ARM_CEXT_MAVERICK, 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
 437   {ARM_CEXT_MAVERICK, 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
 438   {ARM_CEXT_MAVERICK, 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
 439   {ARM_CEXT_MAVERICK, 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
 440   {ARM_CEXT_MAVERICK, 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
 441   {ARM_CEXT_MAVERICK, 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
 442   {ARM_CEXT_MAVERICK, 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
 443   {ARM_CEXT_MAVERICK, 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
 444   {ARM_CEXT_MAVERICK, 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
 445   {ARM_CEXT_MAVERICK, 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
 446   {ARM_CEXT_MAVERICK, 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
 447   {ARM_CEXT_MAVERICK, 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
 448   {ARM_CEXT_MAVERICK, 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
 449   {ARM_CEXT_MAVERICK, 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
 450   {ARM_CEXT_MAVERICK, 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
 451   {ARM_CEXT_MAVERICK, 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
 452   {ARM_CEXT_MAVERICK, 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
 453   {ARM_CEXT_MAVERICK, 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
 454   {ARM_CEXT_MAVERICK, 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
 455   {ARM_CEXT_MAVERICK, 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
 456   {ARM_CEXT_MAVERICK, 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
 457   {ARM_CEXT_MAVERICK, 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
 458   {ARM_CEXT_MAVERICK, 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
 459   {ARM_CEXT_MAVERICK, 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
 460   {ARM_CEXT_MAVERICK, 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
 461   {ARM_CEXT_MAVERICK, 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
 462   {ARM_CEXT_MAVERICK, 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
 463   {ARM_CEXT_MAVERICK, 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
 464   {ARM_CEXT_MAVERICK, 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
 465   {ARM_CEXT_MAVERICK, 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
 466   {ARM_CEXT_MAVERICK, 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
 467   {ARM_CEXT_MAVERICK, 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 468   {ARM_CEXT_MAVERICK, 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
 469   {ARM_CEXT_MAVERICK, 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 470   {ARM_CEXT_MAVERICK, 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
 471   {ARM_CEXT_MAVERICK, 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 472   {ARM_CEXT_MAVERICK, 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
 473   {ARM_CEXT_MAVERICK, 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 474   {ARM_CEXT_MAVERICK, 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 475   {ARM_CEXT_MAVERICK, 0x0e000600, 0x0ff00f10, "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 476   {ARM_CEXT_MAVERICK, 0x0e100600, 0x0ff00f10, "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 477   {ARM_CEXT_MAVERICK, 0x0e200600, 0x0ff00f10, "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
 478   {ARM_CEXT_MAVERICK, 0x0e300600, 0x0ff00f10, "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
 479
 480   /* VFP Fused multiply add instructions.  */
 481   {FPU_VFP_EXT_FMA, 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
 482   {FPU_VFP_EXT_FMA, 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
 483   {FPU_VFP_EXT_FMA, 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
 484   {FPU_VFP_EXT_FMA, 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
 485   {FPU_VFP_EXT_FMA, 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
 486   {FPU_VFP_EXT_FMA, 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
 487   {FPU_VFP_EXT_FMA, 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
 488   {FPU_VFP_EXT_FMA, 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
 489
 490   /* FP v5.  */
 491   {FPU_VFP_EXT_ARMV8, 0xfe000a00, 0xff800f00, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
 492   {FPU_VFP_EXT_ARMV8, 0xfe000b00, 0xff800f00, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
 493
 494   /* Generic coprocessor instructions.  */
 495   { 0, SENTINEL_GENERIC_START, 0, "" },
 496   {ARM_EXT_V5E, 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
 497   {ARM_EXT_V5E, 0x0c500000, 0x0ff00000, "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
 498   {ARM_EXT_V2, 0x0e000000, 0x0f000010, "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
 499   {ARM_EXT_V2, 0x0e10f010, 0x0f10f010, "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
 500   {ARM_EXT_V2, 0x0e100010, 0x0f100010, "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
 501   {ARM_EXT_V2, 0x0e000010, 0x0f100010, "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
 502   {ARM_EXT_V2, 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
 503   {ARM_EXT_V2, 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
 504
 505   /* V6 coprocessor instructions.  */
 506   {ARM_EXT_V6, 0xfc500000, 0xfff00000, "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
 507   {ARM_EXT_V6, 0xfc400000, 0xfff00000, "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
 508
 509   /* V5 coprocessor instructions.  */
 510   {ARM_EXT_V5, 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
 511   {ARM_EXT_V5, 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
 512   {ARM_EXT_V5, 0xfe000000, 0xff000010, "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
 513   {ARM_EXT_V5, 0xfe000010, 0xff100010, "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
 514   {ARM_EXT_V5, 0xfe100010, 0xff100010, "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
 515
 516   {0, 0, 0, 0}
 517 };
 518
 519 /* Neon opcode table:  This does not encode the top byte -- that is
 520    checked by the print_insn_neon routine, as it depends on whether we are
 521    doing thumb32 or arm32 disassembly.  */
 522
 523 /* print_insn_neon recognizes the following format control codes:
 524
 525    %%                   %
 526
 527    %c                   print condition code
 528    %u                   print condition code (unconditional in ARM mode,
 529                           UNPREDICTABLE if not AL in Thumb)
 530    %A                   print v{st,ld}[1234] operands
 531    %B                   print v{st,ld}[1234] any one operands
 532    %C                   print v{st,ld}[1234] single->all operands
 533    %D                   print scalar
 534    %E                   print vmov, vmvn, vorr, vbic encoded constant
 535    %F                   print vtbl,vtbx register list
 536
 537    %<bitfield>r         print as an ARM register
 538    %<bitfield>d         print the bitfield in decimal
 539    %<bitfield>e         print the 2^N - bitfield in decimal
 540    %<bitfield>D         print as a NEON D register
 541    %<bitfield>Q         print as a NEON Q register
 542    %<bitfield>R         print as a NEON D or Q register
 543    %<bitfield>Sn        print byte scaled width limited by n
 544    %<bitfield>Tn        print short scaled width limited by n
 545    %<bitfield>Un        print long scaled width limited by n
 546
 547    %<bitfield>'c        print specified char iff bitfield is all ones
 548    %<bitfield>`c        print specified char iff bitfield is all zeroes
 549    %<bitfield>?ab...    select from array of values in big endian order.  */
 550
 551 static const struct opcode32 neon_opcodes[] =
 552 {
 553   /* Extract.  */
 554   {FPU_NEON_EXT_V1, 0xf2b00840, 0xffb00850, "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
 555   {FPU_NEON_EXT_V1, 0xf2b00000, 0xffb00810, "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
 556
 557   /* Move data element to all lanes.  */
 558   {FPU_NEON_EXT_V1, 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
 559   {FPU_NEON_EXT_V1, 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
 560   {FPU_NEON_EXT_V1, 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
 561
 562   /* Table lookup.  */
 563   {FPU_NEON_EXT_V1, 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
 564   {FPU_NEON_EXT_V1, 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
 565
 566   /* Half-precision conversions.  */
 567   {FPU_VFP_EXT_FP16, 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
 568   {FPU_VFP_EXT_FP16, 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
 569
 570   /* NEON fused multiply add instructions.  */
 571   {FPU_NEON_EXT_FMA, 0xf2000c10, 0xffa00f10, "vfma%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
 572   {FPU_NEON_EXT_FMA, 0xf2200c10, 0xffa00f10, "vfms%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
 573
 574   /* Two registers, miscellaneous.  */
 575   {FPU_NEON_EXT_V1, 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
 576   {FPU_NEON_EXT_V1, 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
 577   {FPU_NEON_EXT_V1, 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
 578   {FPU_NEON_EXT_V1, 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
 579   {FPU_NEON_EXT_V1, 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
 580   {FPU_NEON_EXT_V1, 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
 581   {FPU_NEON_EXT_V1, 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
 582   {FPU_NEON_EXT_V1, 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
 583   {FPU_NEON_EXT_V1, 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
 584   {FPU_NEON_EXT_V1, 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
 585   {FPU_NEON_EXT_V1, 0xf3b20300, 0xffb30fd0, "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
 586   {FPU_NEON_EXT_V1, 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
 587   {FPU_NEON_EXT_V1, 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
 588   {FPU_NEON_EXT_V1, 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
 589   {FPU_NEON_EXT_V1, 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
 590   {FPU_NEON_EXT_V1, 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
 591   {FPU_NEON_EXT_V1, 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
 592   {FPU_NEON_EXT_V1, 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
 593   {FPU_NEON_EXT_V1, 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
 594   {FPU_NEON_EXT_V1, 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
 595   {FPU_NEON_EXT_V1, 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
 596   {FPU_NEON_EXT_V1, 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
 597   {FPU_NEON_EXT_V1, 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
 598   {FPU_NEON_EXT_V1, 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
 599   {FPU_NEON_EXT_V1, 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
 600   {FPU_NEON_EXT_V1, 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
 601   {FPU_NEON_EXT_V1, 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
 602   {FPU_NEON_EXT_V1, 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
 603   {FPU_NEON_EXT_V1, 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
 604   {FPU_NEON_EXT_V1, 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
 605   {FPU_NEON_EXT_V1, 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
 606   {FPU_NEON_EXT_V1, 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
 607   {FPU_NEON_EXT_V1, 0xf3b30600, 0xffb30e10, "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
 608
 609   /* Three registers of the same length.  */
 610   {FPU_NEON_EXT_V1, 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
 611   {FPU_NEON_EXT_V1, 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
 612   {FPU_NEON_EXT_V1, 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
 613   {FPU_NEON_EXT_V1, 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
 614   {FPU_NEON_EXT_V1, 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
 615   {FPU_NEON_EXT_V1, 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
 616   {FPU_NEON_EXT_V1, 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
 617   {FPU_NEON_EXT_V1, 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
 618   {FPU_NEON_EXT_V1, 0xf2000d00, 0xffa00f10, "vadd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
 619   {FPU_NEON_EXT_V1, 0xf2000d10, 0xffa00f10, "vmla%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
 620   {FPU_NEON_EXT_V1, 0xf2000e00, 0xffa00f10, "vceq%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
 621   {FPU_NEON_EXT_V1, 0xf2000f00, 0xffa00f10, "vmax%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
 622   {FPU_NEON_EXT_V1, 0xf2000f10, 0xffa00f10, "vrecps%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
 623   {FPU_NEON_EXT_V1, 0xf2200d00, 0xffa00f10, "vsub%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
 624   {FPU_NEON_EXT_V1, 0xf2200d10, 0xffa00f10, "vmls%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
 625   {FPU_NEON_EXT_V1, 0xf2200f00, 0xffa00f10, "vmin%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
 626   {FPU_NEON_EXT_V1, 0xf2200f10, 0xffa00f10, "vrsqrts%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
 627   {FPU_NEON_EXT_V1, 0xf3000d00, 0xffa00f10, "vpadd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
 628   {FPU_NEON_EXT_V1, 0xf3000d10, 0xffa00f10, "vmul%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
 629   {FPU_NEON_EXT_V1, 0xf3000e00, 0xffa00f10, "vcge%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
 630   {FPU_NEON_EXT_V1, 0xf3000e10, 0xffa00f10, "vacge%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
 631   {FPU_NEON_EXT_V1, 0xf3000f00, 0xffa00f10, "vpmax%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
 632   {FPU_NEON_EXT_V1, 0xf3200d00, 0xffa00f10, "vabd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
 633   {FPU_NEON_EXT_V1, 0xf3200e00, 0xffa00f10, "vcgt%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
 634   {FPU_NEON_EXT_V1, 0xf3200e10, 0xffa00f10, "vacgt%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
 635   {FPU_NEON_EXT_V1, 0xf3200f00, 0xffa00f10, "vpmin%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
 636   {FPU_NEON_EXT_V1, 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
 637   {FPU_NEON_EXT_V1, 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
 638   {FPU_NEON_EXT_V1, 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
 639   {FPU_NEON_EXT_V1, 0xf2000b00, 0xff800f10, "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
 640   {FPU_NEON_EXT_V1, 0xf2000b10, 0xff800f10, "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
 641   {FPU_NEON_EXT_V1, 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
 642   {FPU_NEON_EXT_V1, 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
 643   {FPU_NEON_EXT_V1, 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
 644   {FPU_NEON_EXT_V1, 0xf3000b00, 0xff800f10, "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
 645   {FPU_NEON_EXT_V1, 0xf2000000, 0xfe800f10, "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
 646   {FPU_NEON_EXT_V1, 0xf2000010, 0xfe800f10, "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
 647   {FPU_NEON_EXT_V1, 0xf2000100, 0xfe800f10, "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
 648   {FPU_NEON_EXT_V1, 0xf2000200, 0xfe800f10, "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
 649   {FPU_NEON_EXT_V1, 0xf2000210, 0xfe800f10, "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
 650   {FPU_NEON_EXT_V1, 0xf2000300, 0xfe800f10, "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
 651   {FPU_NEON_EXT_V1, 0xf2000310, 0xfe800f10, "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
 652   {FPU_NEON_EXT_V1, 0xf2000400, 0xfe800f10, "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
 653   {FPU_NEON_EXT_V1, 0xf2000410, 0xfe800f10, "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
 654   {FPU_NEON_EXT_V1, 0xf2000500, 0xfe800f10, "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
 655   {FPU_NEON_EXT_V1, 0xf2000510, 0xfe800f10, "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
 656   {FPU_NEON_EXT_V1, 0xf2000600, 0xfe800f10, "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
 657   {FPU_NEON_EXT_V1, 0xf2000610, 0xfe800f10, "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
 658   {FPU_NEON_EXT_V1, 0xf2000700, 0xfe800f10, "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
 659   {FPU_NEON_EXT_V1, 0xf2000710, 0xfe800f10, "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
 660   {FPU_NEON_EXT_V1, 0xf2000910, 0xfe800f10, "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
 661   {FPU_NEON_EXT_V1, 0xf2000a00, 0xfe800f10, "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
 662   {FPU_NEON_EXT_V1, 0xf2000a10, 0xfe800f10, "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
 663
 664   /* One register and an immediate value.  */
 665   {FPU_NEON_EXT_V1, 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
 666   {FPU_NEON_EXT_V1, 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
 667   {FPU_NEON_EXT_V1, 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
 668   {FPU_NEON_EXT_V1, 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
 669   {FPU_NEON_EXT_V1, 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
 670   {FPU_NEON_EXT_V1, 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
 671   {FPU_NEON_EXT_V1, 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
 672   {FPU_NEON_EXT_V1, 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
 673   {FPU_NEON_EXT_V1, 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
 674   {FPU_NEON_EXT_V1, 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
 675   {FPU_NEON_EXT_V1, 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
 676   {FPU_NEON_EXT_V1, 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
 677   {FPU_NEON_EXT_V1, 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
 678
 679   /* Two registers and a shift amount.  */
 680   {FPU_NEON_EXT_V1, 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
 681   {FPU_NEON_EXT_V1, 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
 682   {FPU_NEON_EXT_V1, 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
 683   {FPU_NEON_EXT_V1, 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
 684   {FPU_NEON_EXT_V1, 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
 685   {FPU_NEON_EXT_V1, 0xf2880950, 0xfeb80fd0, "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
 686   {FPU_NEON_EXT_V1, 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22D, %0-3,5Q, #%16-18d"},
 687   {FPU_NEON_EXT_V1, 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
 688   {FPU_NEON_EXT_V1, 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
 689   {FPU_NEON_EXT_V1, 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
 690   {FPU_NEON_EXT_V1, 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
 691   {FPU_NEON_EXT_V1, 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
 692   {FPU_NEON_EXT_V1, 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
 693   {FPU_NEON_EXT_V1, 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
 694   {FPU_NEON_EXT_V1, 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
 695   {FPU_NEON_EXT_V1, 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
 696   {FPU_NEON_EXT_V1, 0xf2900950, 0xfeb00fd0, "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
 697   {FPU_NEON_EXT_V1, 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-19d"},
 698   {FPU_NEON_EXT_V1, 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
 699   {FPU_NEON_EXT_V1, 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
 700   {FPU_NEON_EXT_V1, 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
 701   {FPU_NEON_EXT_V1, 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
 702   {FPU_NEON_EXT_V1, 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
 703   {FPU_NEON_EXT_V1, 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
 704   {FPU_NEON_EXT_V1, 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
 705   {FPU_NEON_EXT_V1, 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
 706   {FPU_NEON_EXT_V1, 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
 707   {FPU_NEON_EXT_V1, 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
 708   {FPU_NEON_EXT_V1, 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
 709   {FPU_NEON_EXT_V1, 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-20d"},
 710   {FPU_NEON_EXT_V1, 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
 711   {FPU_NEON_EXT_V1, 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
 712   {FPU_NEON_EXT_V1, 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
 713   {FPU_NEON_EXT_V1, 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
 714   {FPU_NEON_EXT_V1, 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
 715   {FPU_NEON_EXT_V1, 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
 716   {FPU_NEON_EXT_V1, 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
 717   {FPU_NEON_EXT_V1, 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
 718   {FPU_NEON_EXT_V1, 0xf2a00950, 0xfea00fd0, "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
 719   {FPU_NEON_EXT_V1, 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
 720   {FPU_NEON_EXT_V1, 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
 721   {FPU_NEON_EXT_V1, 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
 722   {FPU_NEON_EXT_V1, 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
 723   {FPU_NEON_EXT_V1, 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
 724   {FPU_NEON_EXT_V1, 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
 725   {FPU_NEON_EXT_V1, 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
 726   {FPU_NEON_EXT_V1, 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
 727   {FPU_NEON_EXT_V1, 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
 728   {FPU_NEON_EXT_V1, 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
 729   {FPU_NEON_EXT_V1, 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
 730   {FPU_NEON_EXT_V1, 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
 731   {FPU_NEON_EXT_V1, 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
 732   {FPU_NEON_EXT_V1, 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
 733   {FPU_NEON_EXT_V1, 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
 734   {FPU_NEON_EXT_V1, 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
 735   {FPU_NEON_EXT_V1, 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
 736   {FPU_NEON_EXT_V1, 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
 737   {FPU_NEON_EXT_V1, 0xf2a00e10, 0xfea00e90, "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
 738
 739   /* Three registers of different lengths.  */
 740   {FPU_NEON_EXT_V1, 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
 741   {FPU_NEON_EXT_V1, 0xf2800400, 0xff800f50, "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
 742   {FPU_NEON_EXT_V1, 0xf2800600, 0xff800f50, "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
 743   {FPU_NEON_EXT_V1, 0xf2800900, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
 744   {FPU_NEON_EXT_V1, 0xf2800b00, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
 745   {FPU_NEON_EXT_V1, 0xf2800d00, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
 746   {FPU_NEON_EXT_V1, 0xf3800400, 0xff800f50, "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
 747   {FPU_NEON_EXT_V1, 0xf3800600, 0xff800f50, "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
 748   {FPU_NEON_EXT_V1, 0xf2800000, 0xfe800f50, "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
 749   {FPU_NEON_EXT_V1, 0xf2800100, 0xfe800f50, "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
 750   {FPU_NEON_EXT_V1, 0xf2800200, 0xfe800f50, "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
 751   {FPU_NEON_EXT_V1, 0xf2800300, 0xfe800f50, "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
 752   {FPU_NEON_EXT_V1, 0xf2800500, 0xfe800f50, "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
 753   {FPU_NEON_EXT_V1, 0xf2800700, 0xfe800f50, "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
 754   {FPU_NEON_EXT_V1, 0xf2800800, 0xfe800f50, "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
 755   {FPU_NEON_EXT_V1, 0xf2800a00, 0xfe800f50, "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
 756   {FPU_NEON_EXT_V1, 0xf2800c00, 0xfe800f50, "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
 757
 758   /* Two registers and a scalar.  */
 759   {FPU_NEON_EXT_V1, 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
 760   {FPU_NEON_EXT_V1, 0xf2800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
 761   {FPU_NEON_EXT_V1, 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
 762   {FPU_NEON_EXT_V1, 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
 763   {FPU_NEON_EXT_V1, 0xf2800540, 0xff800f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
 764   {FPU_NEON_EXT_V1, 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
 765   {FPU_NEON_EXT_V1, 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
 766   {FPU_NEON_EXT_V1, 0xf2800940, 0xff800f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
 767   {FPU_NEON_EXT_V1, 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
 768   {FPU_NEON_EXT_V1, 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
 769   {FPU_NEON_EXT_V1, 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
 770   {FPU_NEON_EXT_V1, 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
 771   {FPU_NEON_EXT_V1, 0xf3800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
 772   {FPU_NEON_EXT_V1, 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
 773   {FPU_NEON_EXT_V1, 0xf3800540, 0xff800f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
 774   {FPU_NEON_EXT_V1, 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
 775   {FPU_NEON_EXT_V1, 0xf3800940, 0xff800f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
 776   {FPU_NEON_EXT_V1, 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
 777   {FPU_NEON_EXT_V1, 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
 778   {FPU_NEON_EXT_V1, 0xf2800240, 0xfe800f50, "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
 779   {FPU_NEON_EXT_V1, 0xf2800640, 0xfe800f50, "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
 780   {FPU_NEON_EXT_V1, 0xf2800a40, 0xfe800f50, "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
 781
 782   /* Element and structure load/store.  */
 783   {FPU_NEON_EXT_V1, 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
 784   {FPU_NEON_EXT_V1, 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
 785   {FPU_NEON_EXT_V1, 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
 786   {FPU_NEON_EXT_V1, 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
 787   {FPU_NEON_EXT_V1, 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
 788   {FPU_NEON_EXT_V1, 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
 789   {FPU_NEON_EXT_V1, 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
 790   {FPU_NEON_EXT_V1, 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
 791   {FPU_NEON_EXT_V1, 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
 792   {FPU_NEON_EXT_V1, 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
 793   {FPU_NEON_EXT_V1, 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
 794   {FPU_NEON_EXT_V1, 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
 795   {FPU_NEON_EXT_V1, 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
 796   {FPU_NEON_EXT_V1, 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
 797   {FPU_NEON_EXT_V1, 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
 798   {FPU_NEON_EXT_V1, 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
 799   {FPU_NEON_EXT_V1, 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
 800   {FPU_NEON_EXT_V1, 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
 801   {FPU_NEON_EXT_V1, 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
 802
 803   {0,0 ,0, 0}
 804 };
 805
 806 /* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb.  All three are partially
 807    ordered: they must be searched linearly from the top to obtain a correct
 808    match.  */
 809
 810 /* print_insn_arm recognizes the following format control codes:
 811
 812    %%                   %
 813
 814    %a                   print address for ldr/str instruction
 815    %s                   print address for ldr/str halfword/signextend instruction
 816    %S                   like %s but allow UNPREDICTABLE addressing
 817    %b                   print branch destination
 818    %c                   print condition code (always bits 28-31)
 819    %m                   print register mask for ldm/stm instruction
 820    %o                   print operand2 (immediate or register + shift)
 821    %p                   print 'p' iff bits 12-15 are 15
 822    %t                   print 't' iff bit 21 set and bit 24 clear
 823    %B                   print arm BLX(1) destination
 824    %C                   print the PSR sub type.
 825    %U                   print barrier type.
 826    %P                   print address for pli instruction.
 827
 828    %<bitfield>r         print as an ARM register
 829    %<bitfield>T         print as an ARM register + 1
 830    %<bitfield>R         as %r but r15 is UNPREDICTABLE
 831    %<bitfield>{r|R}u    as %{r|R} but if matches the other %u field then is UNPREDICTABLE
 832    %<bitfield>{r|R}U    as %{r|R} but if matches the other %U field then is UNPREDICTABLE
 833    %<bitfield>d         print the bitfield in decimal
 834    %<bitfield>W         print the bitfield plus one in decimal
 835    %<bitfield>x         print the bitfield in hex
 836    %<bitfield>X         print the bitfield as 1 hex digit without leading "0x"
 837
 838    %<bitfield>'c        print specified char iff bitfield is all ones
 839    %<bitfield>`c        print specified char iff bitfield is all zeroes
 840    %<bitfield>?ab...    select from array of values in big endian order
 841
 842    %e                   print arm SMI operand (bits 0..7,8..19).
 843    %E                   print the LSB and WIDTH fields of a BFI or BFC instruction.
 844    %V                   print the 16-bit immediate field of a MOVT or MOVW instruction.
 845    %R                   print the SPSR/CPSR or banked register of an MRS.  */
 846
 847 static const struct opcode32 arm_opcodes[] =
 848 {
 849   /* ARM instructions.  */
 850   {ARM_EXT_V1, 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
 851   {ARM_EXT_V4T | ARM_EXT_V5, 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
 852   {ARM_EXT_V2, 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
 853   {ARM_EXT_V2, 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
 854   {ARM_EXT_V2S, 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
 855   {ARM_EXT_V3M, 0x00800090, 0x0fa000f0, "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
 856   {ARM_EXT_V3M, 0x00a00090, 0x0fa000f0, "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
 857
 858   /* V8 instructions.  */
 859   {ARM_EXT_V8,   0x0320f005, 0x0fffffff, "sevl"},
 860   {ARM_EXT_V8,   0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
 861   {ARM_EXT_V8,   0x01800e90, 0x0ff00ff0, "strlex%c\t%12-15r, %0-3r, [%16-19R]"},
 862   {ARM_EXT_V8,   0x01900e9f, 0x0ff00fff, "ldraex%c\t%12-15r, [%16-19R]"},
 863   {ARM_EXT_V8,   0x01a00e90, 0x0ff00ff0, "strlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
 864   {ARM_EXT_V8,   0x01b00e9f, 0x0ff00fff, "ldraexd%c\t%12-15r, %12-15T, [%16-19R]"},
 865   {ARM_EXT_V8,   0x01c00e90, 0x0ff00ff0, "strlexb%c\t%12-15r, %0-3r, [%16-19R]"},
 866   {ARM_EXT_V8,   0x01d00e9f, 0x0ff00fff, "ldraexb%c\t%12-15r, [%16-19R]"},
 867   {ARM_EXT_V8,   0x01e00e90, 0x0ff00ff0, "strlexh%c\t%12-15r, %0-3r, [%16-19R]"},
 868   {ARM_EXT_V8,   0x01f00e9f, 0x0ff00fff, "ldraexh%c\t%12-15r, [%16-19R]"},
 869   {ARM_EXT_V8,   0x0180fc90, 0x0ff0fff0, "strl%c\t%0-3r, [%16-19R]"},
 870   {ARM_EXT_V8,   0x01900c9f, 0x0ff00fff, "ldra%c\t%12-15r, [%16-19R]"},
 871   {ARM_EXT_V8,   0x01c0fc90, 0x0ff0fff0, "strlb%c\t%0-3r, [%16-19R]"},
 872   {ARM_EXT_V8,   0x01d00c9f, 0x0ff00fff, "ldrab%c\t%12-15r, [%16-19R]"},
 873   {ARM_EXT_V8,   0x01e0fc90, 0x0ff0fff0, "strlh%c\t%0-3r, [%16-19R]"},
 874   {ARM_EXT_V8,   0x01f00c9f, 0x0ff00fff, "ldraexh%c\t%12-15r, [%16-19R]"},
 875
 876   /* Virtualization Extension instructions.  */
 877   {ARM_EXT_VIRT, 0x0160006e, 0x0fffffff, "eret%c"},
 878   {ARM_EXT_VIRT, 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
 879
 880   /* Integer Divide Extension instructions.  */
 881   {ARM_EXT_ADIV, 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
 882   {ARM_EXT_ADIV, 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
 883
 884   /* MP Extension instructions.  */
 885   {ARM_EXT_MP, 0xf410f000, 0xfc70f000, "pldw\t%a"},
 886
 887   /* V7 instructions.  */
 888   {ARM_EXT_V7, 0xf450f000, 0xfd70f000, "pli\t%P"},
 889   {ARM_EXT_V7, 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
 890   {ARM_EXT_V8, 0xf57ff051, 0xfffffff3, "dmb\t%U"},
 891   {ARM_EXT_V8, 0xf57ff041, 0xfffffff3, "dsb\t%U"},
 892   {ARM_EXT_V7, 0xf57ff050, 0xfffffff0, "dmb\t%U"},
 893   {ARM_EXT_V7, 0xf57ff040, 0xfffffff0, "dsb\t%U"},
 894   {ARM_EXT_V7, 0xf57ff060, 0xfffffff0, "isb\t%U"},
 895
 896   /* ARM V6T2 instructions.  */
 897   {ARM_EXT_V6T2, 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
 898   {ARM_EXT_V6T2, 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
 899   {ARM_EXT_V6T2, 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
 900   {ARM_EXT_V6T2, 0x006000b0, 0x0f7000f0, "strht%c\t%12-15R, %S"},
 901
 902   {ARM_EXT_V6T2, 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
 903   {ARM_EXT_V6T2, 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
 904
 905   {ARM_EXT_V6T2, 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
 906   {ARM_EXT_V6T2, 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
 907   {ARM_EXT_V6T2, 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
 908   {ARM_EXT_V6T2, 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
 909
 910   /* ARM Security extension instructions.  */
 911   {ARM_EXT_SEC, 0x01600070, 0x0ff000f0, "smc%c\t%e"},
 912
 913   /* ARM V6K instructions.  */
 914   {ARM_EXT_V6K, 0xf57ff01f, 0xffffffff, "clrex"},
 915   {ARM_EXT_V6K, 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
 916   {ARM_EXT_V6K, 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
 917   {ARM_EXT_V6K, 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
 918   {ARM_EXT_V6K, 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
 919   {ARM_EXT_V6K, 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
 920   {ARM_EXT_V6K, 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
 921
 922   /* ARM V6K NOP hints.  */
 923   {ARM_EXT_V6K, 0x0320f001, 0x0fffffff, "yield%c"},
 924   {ARM_EXT_V6K, 0x0320f002, 0x0fffffff, "wfe%c"},
 925   {ARM_EXT_V6K, 0x0320f003, 0x0fffffff, "wfi%c"},
 926   {ARM_EXT_V6K, 0x0320f004, 0x0fffffff, "sev%c"},
 927   {ARM_EXT_V6K, 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
 928
 929   /* ARM V6 instructions.  */
 930   {ARM_EXT_V6, 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
 931   {ARM_EXT_V6, 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
 932   {ARM_EXT_V6, 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
 933   {ARM_EXT_V6, 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
 934   {ARM_EXT_V6, 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
 935   {ARM_EXT_V6, 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
 936   {ARM_EXT_V6, 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
 937   {ARM_EXT_V6, 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
 938   {ARM_EXT_V6, 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
 939   {ARM_EXT_V6, 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
 940   {ARM_EXT_V6, 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
 941   {ARM_EXT_V6, 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
 942   {ARM_EXT_V6, 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
 943   {ARM_EXT_V6, 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
 944   {ARM_EXT_V6, 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
 945   {ARM_EXT_V6, 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
 946   {ARM_EXT_V6, 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
 947   {ARM_EXT_V6, 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
 948   {ARM_EXT_V6, 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
 949   {ARM_EXT_V6, 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
 950   {ARM_EXT_V6, 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
 951   {ARM_EXT_V6, 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
 952   {ARM_EXT_V6, 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
 953   {ARM_EXT_V6, 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
 954   {ARM_EXT_V6, 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
 955   {ARM_EXT_V6, 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
 956   {ARM_EXT_V6, 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
 957   {ARM_EXT_V6, 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
 958   {ARM_EXT_V6, 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
 959   {ARM_EXT_V6, 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
 960   {ARM_EXT_V6, 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
 961   {ARM_EXT_V6, 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
 962   {ARM_EXT_V6, 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
 963   {ARM_EXT_V6, 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
 964   {ARM_EXT_V6, 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
 965   {ARM_EXT_V6, 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
 966   {ARM_EXT_V6, 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
 967   {ARM_EXT_V6, 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
 968   {ARM_EXT_V6, 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
 969   {ARM_EXT_V6, 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
 970   {ARM_EXT_V6, 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
 971   {ARM_EXT_V6, 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
 972   {ARM_EXT_V6, 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
 973   {ARM_EXT_V6, 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
 974   {ARM_EXT_V6, 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
 975   {ARM_EXT_V6, 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
 976   {ARM_EXT_V6, 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
 977   {ARM_EXT_V6, 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
 978   {ARM_EXT_V6, 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
 979   {ARM_EXT_V6, 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
 980   {ARM_EXT_V6, 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
 981   {ARM_EXT_V6, 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
 982   {ARM_EXT_V6, 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
 983   {ARM_EXT_V6, 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
 984   {ARM_EXT_V6, 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
 985   {ARM_EXT_V6, 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
 986   {ARM_EXT_V6, 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
 987   {ARM_EXT_V6, 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
 988   {ARM_EXT_V6, 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
 989   {ARM_EXT_V6, 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
 990   {ARM_EXT_V6, 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
 991   {ARM_EXT_V6, 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
 992   {ARM_EXT_V6, 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
 993   {ARM_EXT_V6, 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
 994   {ARM_EXT_V6, 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
 995   {ARM_EXT_V6, 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
 996   {ARM_EXT_V6, 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
 997   {ARM_EXT_V6, 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
 998   {ARM_EXT_V6, 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
 999   {ARM_EXT_V6, 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
1000   {ARM_EXT_V6, 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
1001   {ARM_EXT_V6, 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
1002   {ARM_EXT_V6, 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
1003   {ARM_EXT_V6, 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
1004   {ARM_EXT_V6, 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
1005   {ARM_EXT_V6, 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1006   {ARM_EXT_V6, 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1007   {ARM_EXT_V6, 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1008   {ARM_EXT_V6, 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
1009   {ARM_EXT_V6, 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1010   {ARM_EXT_V6, 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1011   {ARM_EXT_V6, 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1012   {ARM_EXT_V6, 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
1013   {ARM_EXT_V6, 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1014   {ARM_EXT_V6, 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1015   {ARM_EXT_V6, 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1016   {ARM_EXT_V6, 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
1017   {ARM_EXT_V6, 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1018   {ARM_EXT_V6, 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1019   {ARM_EXT_V6, 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1020   {ARM_EXT_V6, 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
1021   {ARM_EXT_V6, 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1022   {ARM_EXT_V6, 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1023   {ARM_EXT_V6, 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
1024   {ARM_EXT_V6, 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
1025   {ARM_EXT_V6, 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1026   {ARM_EXT_V6, 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1027   {ARM_EXT_V6, 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1028   {ARM_EXT_V6, 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
1029   {ARM_EXT_V6, 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
1030   {ARM_EXT_V6, 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
1031   {ARM_EXT_V6, 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
1032   {ARM_EXT_V6, 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1033   {ARM_EXT_V6, 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1034   {ARM_EXT_V6, 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1035   {ARM_EXT_V6, 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1036   {ARM_EXT_V6, 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
1037   {ARM_EXT_V6, 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1038   {ARM_EXT_V6, 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1039   {ARM_EXT_V6, 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
1040   {ARM_EXT_V6, 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
1041   {ARM_EXT_V6, 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
1042   {ARM_EXT_V6, 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
1043   {ARM_EXT_V6, 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
1044   {ARM_EXT_V6, 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
1045   {ARM_EXT_V6, 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
1046   {ARM_EXT_V6, 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
1047   {ARM_EXT_V6, 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1048   {ARM_EXT_V6, 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
1049   {ARM_EXT_V6, 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
1050   {ARM_EXT_V6, 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
1051   {ARM_EXT_V6, 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
1052
1053   /* V5J instruction.  */
1054   {ARM_EXT_V5J, 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
1055
1056   /* V5 Instructions.  */
1057   {ARM_EXT_V5, 0xe1200070, 0xfff000f0, "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
1058   {ARM_EXT_V5, 0xfa000000, 0xfe000000, "blx\t%B"},
1059   {ARM_EXT_V5, 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
1060   {ARM_EXT_V5, 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
1061
1062   /* V5E "El Segundo" Instructions.  */
1063   {ARM_EXT_V5E, 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
1064   {ARM_EXT_V5E, 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
1065   {ARM_EXT_V5E, 0xf450f000, 0xfc70f000, "pld\t%a"},
1066   {ARM_EXT_V5ExP, 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1067   {ARM_EXT_V5ExP, 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1068   {ARM_EXT_V5ExP, 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1069   {ARM_EXT_V5ExP, 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
1070
1071   {ARM_EXT_V5ExP, 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1072   {ARM_EXT_V5ExP, 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
1073
1074   {ARM_EXT_V5ExP, 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1075   {ARM_EXT_V5ExP, 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1076   {ARM_EXT_V5ExP, 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1077   {ARM_EXT_V5ExP, 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1078
1079   {ARM_EXT_V5ExP, 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
1080   {ARM_EXT_V5ExP, 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
1081   {ARM_EXT_V5ExP, 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
1082   {ARM_EXT_V5ExP, 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
1083
1084   {ARM_EXT_V5ExP, 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
1085   {ARM_EXT_V5ExP, 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
1086
1087   {ARM_EXT_V5ExP, 0x01000050, 0x0ff00ff0,  "qadd%c\t%12-15R, %0-3R, %16-19R"},
1088   {ARM_EXT_V5ExP, 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
1089   {ARM_EXT_V5ExP, 0x01200050, 0x0ff00ff0,  "qsub%c\t%12-15R, %0-3R, %16-19R"},
1090   {ARM_EXT_V5ExP, 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
1091
1092   /* ARM Instructions.  */
1093   {ARM_EXT_V1, 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
1094
1095   {ARM_EXT_V1, 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
1096   {ARM_EXT_V1, 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
1097   {ARM_EXT_V1, 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
1098   {ARM_EXT_V1, 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
1099   {ARM_EXT_V1, 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
1100   {ARM_EXT_V1, 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
1101
1102   {ARM_EXT_V1, 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
1103   {ARM_EXT_V1, 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
1104   {ARM_EXT_V1, 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
1105   {ARM_EXT_V1, 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
1106
1107   {ARM_EXT_V1, 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
1108   {ARM_EXT_V1, 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
1109   {ARM_EXT_V1, 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
1110   {ARM_EXT_V1, 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
1111
1112   {ARM_EXT_V1, 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
1113   {ARM_EXT_V1, 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
1114   {ARM_EXT_V1, 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
1115
1116   {ARM_EXT_V1, 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
1117   {ARM_EXT_V1, 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
1118   {ARM_EXT_V1, 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
1119
1120   {ARM_EXT_V1, 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
1121   {ARM_EXT_V1, 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
1122   {ARM_EXT_V1, 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
1123
1124   {ARM_EXT_V1, 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
1125   {ARM_EXT_V1, 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
1126   {ARM_EXT_V1, 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
1127
1128   {ARM_EXT_V1, 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
1129   {ARM_EXT_V1, 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
1130   {ARM_EXT_V1, 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
1131
1132   {ARM_EXT_V1, 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
1133   {ARM_EXT_V1, 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
1134   {ARM_EXT_V1, 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
1135
1136   {ARM_EXT_V1, 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
1137   {ARM_EXT_V1, 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
1138   {ARM_EXT_V1, 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
1139
1140   {ARM_EXT_V1, 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
1141   {ARM_EXT_V1, 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
1142   {ARM_EXT_V1, 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
1143
1144   {ARM_EXT_VIRT, 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
1145   {ARM_EXT_V3, 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
1146   {ARM_EXT_V3, 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
1147
1148   {ARM_EXT_V1, 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
1149   {ARM_EXT_V1, 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
1150   {ARM_EXT_V1, 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
1151
1152   {ARM_EXT_V1, 0x03200000, 0x0fe00000, "teq%p%c\t%16-19r, %o"},
1153   {ARM_EXT_V1, 0x01200000, 0x0fe00010, "teq%p%c\t%16-19r, %o"},
1154   {ARM_EXT_V1, 0x01200010, 0x0fe00090, "teq%p%c\t%16-19R, %o"},
1155
1156   {ARM_EXT_V1, 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
1157   {ARM_EXT_V1, 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
1158   {ARM_EXT_V1, 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
1159
1160   {ARM_EXT_V1, 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
1161   {ARM_EXT_V1, 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
1162   {ARM_EXT_V1, 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
1163
1164   {ARM_EXT_V1, 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
1165   {ARM_EXT_V1, 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
1166   {ARM_EXT_V1, 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
1167
1168   {ARM_EXT_V1, 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
1169   {ARM_EXT_V1, 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
1170   {ARM_EXT_V1, 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
1171   {ARM_EXT_V1, 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
1172   {ARM_EXT_V1, 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
1173   {ARM_EXT_V1, 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
1174   {ARM_EXT_V1, 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
1175
1176   {ARM_EXT_V1, 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
1177   {ARM_EXT_V1, 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
1178   {ARM_EXT_V1, 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
1179
1180   {ARM_EXT_V1, 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
1181   {ARM_EXT_V1, 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
1182   {ARM_EXT_V1, 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
1183
1184   {ARM_EXT_V1, 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
1185   {ARM_EXT_V1, 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
1186
1187   {ARM_EXT_V1, 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
1188
1189   {ARM_EXT_V1, 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
1190   {ARM_EXT_V1, 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
1191
1192   {ARM_EXT_V1, 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1193   {ARM_EXT_V1, 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1194   {ARM_EXT_V1, 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1195   {ARM_EXT_V1, 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1196   {ARM_EXT_V1, 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1197   {ARM_EXT_V1, 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1198   {ARM_EXT_V1, 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1199   {ARM_EXT_V1, 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1200   {ARM_EXT_V1, 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1201   {ARM_EXT_V1, 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1202   {ARM_EXT_V1, 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1203   {ARM_EXT_V1, 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1204   {ARM_EXT_V1, 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1205   {ARM_EXT_V1, 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1206   {ARM_EXT_V1, 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1207   {ARM_EXT_V1, 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1208   {ARM_EXT_V1, 0x092d0000, 0x0fff0000, "push%c\t%m"},
1209   {ARM_EXT_V1, 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
1210   {ARM_EXT_V1, 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
1211
1212   {ARM_EXT_V1, 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1213   {ARM_EXT_V1, 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1214   {ARM_EXT_V1, 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1215   {ARM_EXT_V1, 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1216   {ARM_EXT_V1, 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1217   {ARM_EXT_V1, 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1218   {ARM_EXT_V1, 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1219   {ARM_EXT_V1, 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1220   {ARM_EXT_V1, 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1221   {ARM_EXT_V1, 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1222   {ARM_EXT_V1, 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1223   {ARM_EXT_V1, 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1224   {ARM_EXT_V1, 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1225   {ARM_EXT_V1, 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1226   {ARM_EXT_V1, 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1227   {ARM_EXT_V1, 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1228   {ARM_EXT_V1, 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
1229   {ARM_EXT_V1, 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
1230   {ARM_EXT_V1, 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
1231
1232   {ARM_EXT_V1, 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
1233   {ARM_EXT_V1, 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
1234
1235   /* The rest.  */
1236   {ARM_EXT_V1, 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
1237   {0, 0x00000000, 0x00000000, 0}
1238 };
1239
1240 /* print_insn_thumb16 recognizes the following format control codes:
1241
1242    %S                   print Thumb register (bits 3..5 as high number if bit 6 set)
1243    %D                   print Thumb register (bits 0..2 as high number if bit 7 set)
1244    %<bitfield>I         print bitfield as a signed decimal
1245                                 (top bit of range being the sign bit)
1246    %N                   print Thumb register mask (with LR)
1247    %O                   print Thumb register mask (with PC)
1248    %M                   print Thumb register mask
1249    %b                   print CZB's 6-bit unsigned branch destination
1250    %s                   print Thumb right-shift immediate (6..10; 0 == 32).
1251    %c                   print the condition code
1252    %C                   print the condition code, or "s" if not conditional
1253    %x                   print warning if conditional an not at end of IT block"
1254    %X                   print "\t; unpredictable <IT:code>" if conditional
1255    %I                   print IT instruction suffix and operands
1256    %W                   print Thumb Writeback indicator for LDMIA
1257    %<bitfield>r         print bitfield as an ARM register
1258    %<bitfield>d         print bitfield as a decimal
1259    %<bitfield>H         print (bitfield * 2) as a decimal
1260    %<bitfield>W         print (bitfield * 4) as a decimal
1261    %<bitfield>a         print (bitfield * 4) as a pc-rel offset + decoded symbol
1262    %<bitfield>B         print Thumb branch destination (signed displacement)
1263    %<bitfield>c         print bitfield as a condition code
1264    %<bitnum>'c          print specified char iff bit is one
1265    %<bitnum>?ab         print a if bit is one else print b.  */
1266
1267 static const struct opcode16 thumb_opcodes[] =
1268 {
1269   /* Thumb instructions.  */
1270
1271   /* ARM V8 instructions.  */
1272   {ARM_EXT_V8,  0xbf50, 0xffff, "sevl%c"},
1273   {ARM_EXT_V8,  0xba80, 0xffc0, "hlt\t%0-5x"},
1274
1275   /* ARM V6K no-argument instructions.  */
1276   {ARM_EXT_V6K, 0xbf00, 0xffff, "nop%c"},
1277   {ARM_EXT_V6K, 0xbf10, 0xffff, "yield%c"},
1278   {ARM_EXT_V6K, 0xbf20, 0xffff, "wfe%c"},
1279   {ARM_EXT_V6K, 0xbf30, 0xffff, "wfi%c"},
1280   {ARM_EXT_V6K, 0xbf40, 0xffff, "sev%c"},
1281   {ARM_EXT_V6K, 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
1282
1283   /* ARM V6T2 instructions.  */
1284   {ARM_EXT_V6T2, 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
1285   {ARM_EXT_V6T2, 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
1286   {ARM_EXT_V6T2, 0xbf00, 0xff00, "it%I%X"},
1287
1288   /* ARM V6.  */
1289   {ARM_EXT_V6, 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
1290   {ARM_EXT_V6, 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
1291   {ARM_EXT_V6, 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
1292   {ARM_EXT_V6, 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
1293   {ARM_EXT_V6, 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
1294   {ARM_EXT_V6, 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
1295   {ARM_EXT_V6, 0xb650, 0xfff7, "setend\t%3?ble%X"},
1296   {ARM_EXT_V6, 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
1297   {ARM_EXT_V6, 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
1298   {ARM_EXT_V6, 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
1299   {ARM_EXT_V6, 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
1300
1301   /* ARM V5 ISA extends Thumb.  */
1302   {ARM_EXT_V5T, 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional.  */
1303   /* This is BLX(2).  BLX(1) is a 32-bit instruction.  */
1304   {ARM_EXT_V5T, 0x4780, 0xff87, "blx%c\t%3-6r%x"},      /* note: 4 bit register number.  */
1305   /* ARM V4T ISA (Thumb v1).  */
1306   {ARM_EXT_V4T, 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
1307   /* Format 4.  */
1308   {ARM_EXT_V4T, 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
1309   {ARM_EXT_V4T, 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
1310   {ARM_EXT_V4T, 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
1311   {ARM_EXT_V4T, 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
1312   {ARM_EXT_V4T, 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
1313   {ARM_EXT_V4T, 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
1314   {ARM_EXT_V4T, 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
1315   {ARM_EXT_V4T, 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
1316   {ARM_EXT_V4T, 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
1317   {ARM_EXT_V4T, 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
1318   {ARM_EXT_V4T, 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
1319   {ARM_EXT_V4T, 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
1320   {ARM_EXT_V4T, 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
1321   {ARM_EXT_V4T, 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
1322   {ARM_EXT_V4T, 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
1323   {ARM_EXT_V4T, 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
1324   /* format 13 */
1325   {ARM_EXT_V4T, 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
1326   {ARM_EXT_V4T, 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
1327   /* format 5 */
1328   {ARM_EXT_V4T, 0x4700, 0xFF80, "bx%c\t%S%x"},
1329   {ARM_EXT_V4T, 0x4400, 0xFF00, "add%c\t%D, %S"},
1330   {ARM_EXT_V4T, 0x4500, 0xFF00, "cmp%c\t%D, %S"},
1331   {ARM_EXT_V4T, 0x4600, 0xFF00, "mov%c\t%D, %S"},
1332   /* format 14 */
1333   {ARM_EXT_V4T, 0xB400, 0xFE00, "push%c\t%N"},
1334   {ARM_EXT_V4T, 0xBC00, 0xFE00, "pop%c\t%O"},
1335   /* format 2 */
1336   {ARM_EXT_V4T, 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
1337   {ARM_EXT_V4T, 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
1338   {ARM_EXT_V4T, 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
1339   {ARM_EXT_V4T, 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
1340   /* format 8 */
1341   {ARM_EXT_V4T, 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
1342   {ARM_EXT_V4T, 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
1343   {ARM_EXT_V4T, 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
1344   /* format 7 */
1345   {ARM_EXT_V4T, 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
1346   {ARM_EXT_V4T, 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
1347   /* format 1 */
1348   {ARM_EXT_V4T, 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
1349   {ARM_EXT_V4T, 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
1350   {ARM_EXT_V4T, 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
1351   {ARM_EXT_V4T, 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
1352   /* format 3 */
1353   {ARM_EXT_V4T, 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
1354   {ARM_EXT_V4T, 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
1355   {ARM_EXT_V4T, 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
1356   {ARM_EXT_V4T, 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
1357   /* format 6 */
1358   {ARM_EXT_V4T, 0x4800, 0xF800, "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},  /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
1359   /* format 9 */
1360   {ARM_EXT_V4T, 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
1361   {ARM_EXT_V4T, 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
1362   {ARM_EXT_V4T, 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
1363   {ARM_EXT_V4T, 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
1364   /* format 10 */
1365   {ARM_EXT_V4T, 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
1366   {ARM_EXT_V4T, 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
1367   /* format 11 */
1368   {ARM_EXT_V4T, 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
1369   {ARM_EXT_V4T, 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
1370   /* format 12 */
1371   {ARM_EXT_V4T, 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
1372   {ARM_EXT_V4T, 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
1373   /* format 15 */
1374   {ARM_EXT_V4T, 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
1375   {ARM_EXT_V4T, 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
1376   /* format 17 */
1377   {ARM_EXT_V4T, 0xDF00, 0xFF00, "svc%c\t%0-7d"},
1378   /* format 16 */
1379   {ARM_EXT_V4T, 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
1380   {ARM_EXT_V4T, 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
1381   /* format 18 */
1382   {ARM_EXT_V4T, 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
1383
1384   /* The E800 .. FFFF range is unconditionally redirected to the
1385      32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
1386      are processed via that table.  Thus, we can never encounter a
1387      bare "second half of BL/BLX(1)" instruction here.  */
1388   {ARM_EXT_V1,  0x0000, 0x0000, UNDEFINED_INSTRUCTION},
1389   {0, 0, 0, 0}
1390 };
1391
1392 /* Thumb32 opcodes use the same table structure as the ARM opcodes.
1393    We adopt the convention that hw1 is the high 16 bits of .value and
1394    .mask, hw2 the low 16 bits.
1395
1396    print_insn_thumb32 recognizes the following format control codes:
1397
1398        %%               %
1399
1400        %I               print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
1401        %M               print a modified 12-bit immediate (same location)
1402        %J               print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
1403        %K               print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
1404        %H               print a 16-bit immediate from hw2[3:0],hw1[11:0]
1405        %S               print a possibly-shifted Rm
1406
1407        %L               print address for a ldrd/strd instruction
1408        %a               print the address of a plain load/store
1409        %w               print the width and signedness of a core load/store
1410        %m               print register mask for ldm/stm
1411
1412        %E               print the lsb and width fields of a bfc/bfi instruction
1413        %F               print the lsb and width fields of a sbfx/ubfx instruction
1414        %b               print a conditional branch offset
1415        %B               print an unconditional branch offset
1416        %s               print the shift field of an SSAT instruction
1417        %R               print the rotation field of an SXT instruction
1418        %U               print barrier type.
1419        %P               print address for pli instruction.
1420        %c               print the condition code
1421        %x               print warning if conditional an not at end of IT block"
1422        %X               print "\t; unpredictable <IT:code>" if conditional
1423
1424        %<bitfield>d     print bitfield in decimal
1425        %<bitfield>W     print bitfield*4 in decimal
1426        %<bitfield>r     print bitfield as an ARM register
1427        %<bitfield>R     as %<>r bit r15 is UNPREDICTABLE
1428        %<bitfield>c     print bitfield as a condition code
1429
1430        %<bitfield>'c    print specified char iff bitfield is all ones
1431        %<bitfield>`c    print specified char iff bitfield is all zeroes
1432        %<bitfield>?ab... select from array of values in big endian order
1433
1434    With one exception at the bottom (done because BL and BLX(1) need
1435    to come dead last), this table was machine-sorted first in
1436    decreasing order of number of bits set in the mask, then in
1437    increasing numeric order of mask, then in increasing numeric order
1438    of opcode.  This order is not the clearest for a human reader, but
1439    is guaranteed never to catch a special-case bit pattern with a more
1440    general mask, which is important, because this instruction encoding
1441    makes heavy use of special-case bit patterns.  */
1442 static const struct opcode32 thumb32_opcodes[] =
1443 {
1444   /* V8 instructions.  */
1445   {ARM_EXT_V8, 0xf3af8005, 0xffffffff, "sevl%c.w"},
1446   {ARM_EXT_V8, 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
1447   {ARM_EXT_V8, 0xe8c00f8f, 0xfff00fff, "strlb%c\t%12-15r, [%16-19R]"},
1448   {ARM_EXT_V8, 0xe8c00f9f, 0xfff00fff, "strlh%c\t%12-15r, [%16-19R]"},
1449   {ARM_EXT_V8, 0xe8c00faf, 0xfff00fff, "strl%c\t%12-15r, [%16-19R]"},
1450   {ARM_EXT_V8, 0xe8c00fc0, 0xfff00ff0, "strlexb%c\t%0-3r, %12-15r, [%16-19R]"},
1451   {ARM_EXT_V8, 0xe8c00fd0, 0xfff00ff0, "strlexh%c\t%0-3r, %12-15r, [%16-19R]"},
1452   {ARM_EXT_V8, 0xe8c00fe0, 0xfff00ff0, "strlex%c\t%0-3r, %12-15r, [%16-19R]"},
1453   {ARM_EXT_V8, 0xe8c000f0, 0xfff000f0, "strlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
1454   {ARM_EXT_V8, 0xe8d00f8f, 0xfff00fff, "ldrab%c\t%12-15r, [%16-19R]"},
1455   {ARM_EXT_V8, 0xe8d00f9f, 0xfff00fff, "ldrah%c\t%12-15r, [%16-19R]"},
1456   {ARM_EXT_V8, 0xe8d00faf, 0xfff00fff, "ldra%c\t%12-15r, [%16-19R]"},
1457   {ARM_EXT_V8, 0xe8d00fcf, 0xfff00fff, "ldraexb%c\t%12-15r, [%16-19R]"},
1458   {ARM_EXT_V8, 0xe8d00fdf, 0xfff00fff, "ldraexh%c\t%12-15r, [%16-19R]"},
1459   {ARM_EXT_V8, 0xe8d00fef, 0xfff00fff, "ldraex%c\t%12-15r, [%16-19R]"},
1460   {ARM_EXT_V8, 0xe8d000ff, 0xfff000ff, "ldraexd%c\t%12-15r, %8-11r, [%16-19R]"},
1461
1462   /* V7 instructions.  */
1463   {ARM_EXT_V7, 0xf910f000, 0xff70f000, "pli%c\t%a"},
1464   {ARM_EXT_V7, 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
1465   {ARM_EXT_V8, 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
1466   {ARM_EXT_V8, 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
1467   {ARM_EXT_V7, 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
1468   {ARM_EXT_V7, 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
1469   {ARM_EXT_V7, 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
1470   {ARM_EXT_DIV, 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
1471   {ARM_EXT_DIV, 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
1472
1473   /* Virtualization Extension instructions.  */
1474   {ARM_EXT_VIRT, 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
1475   /* We skip ERET as that is SUBS pc, lr, #0.  */
1476
1477   /* MP Extension instructions.  */
1478   {ARM_EXT_MP,   0xf830f000, 0xff70f000, "pldw%c\t%a"},
1479
1480   /* Security extension instructions.  */
1481   {ARM_EXT_SEC,  0xf7f08000, 0xfff0f000, "smc%c\t%K"},
1482
1483   /* Instructions defined in the basic V6T2 set.  */
1484   {ARM_EXT_V6T2, 0xf3af8000, 0xffffffff, "nop%c.w"},
1485   {ARM_EXT_V6T2, 0xf3af8001, 0xffffffff, "yield%c.w"},
1486   {ARM_EXT_V6T2, 0xf3af8002, 0xffffffff, "wfe%c.w"},
1487   {ARM_EXT_V6T2, 0xf3af8003, 0xffffffff, "wfi%c.w"},
1488   {ARM_EXT_V6T2, 0xf3af8004, 0xffffffff, "sev%c.w"},
1489   {ARM_EXT_V6T2, 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
1490
1491   {ARM_EXT_V6T2, 0xf3bf8f2f, 0xffffffff, "clrex%c"},
1492   {ARM_EXT_V6T2, 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
1493   {ARM_EXT_V6T2, 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
1494   {ARM_EXT_V6T2, 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
1495   {ARM_EXT_V6T2, 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
1496   {ARM_EXT_V6T2, 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
1497   {ARM_EXT_V6T2, 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
1498   {ARM_EXT_V6T2, 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
1499   {ARM_EXT_V6T2, 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
1500   {ARM_EXT_V6T2, 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
1501   {ARM_EXT_V6T2, 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
1502   {ARM_EXT_V6T2, 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
1503   {ARM_EXT_V6T2, 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
1504   {ARM_EXT_V6T2, 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
1505   {ARM_EXT_V6T2, 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
1506   {ARM_EXT_V6T2, 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
1507   {ARM_EXT_V6T2, 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
1508   {ARM_EXT_V6T2, 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
1509   {ARM_EXT_V6T2, 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
1510   {ARM_EXT_V6T2, 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
1511   {ARM_EXT_V6T2, 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
1512   {ARM_EXT_V6T2, 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
1513   {ARM_EXT_V6T2, 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
1514   {ARM_EXT_V6T2, 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
1515   {ARM_EXT_V6T2, 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
1516   {ARM_EXT_V6T2, 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
1517   {ARM_EXT_V6T2, 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
1518   {ARM_EXT_V6T2, 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
1519   {ARM_EXT_V6T2, 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
1520   {ARM_EXT_V6T2, 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
1521   {ARM_EXT_V6T2, 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
1522   {ARM_EXT_V6T2, 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
1523   {ARM_EXT_V6T2, 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
1524   {ARM_EXT_V6T2, 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
1525   {ARM_EXT_V6T2, 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
1526   {ARM_EXT_V6T2, 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
1527   {ARM_EXT_V6T2, 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
1528   {ARM_EXT_V6T2, 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
1529   {ARM_EXT_V6T2, 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
1530   {ARM_EXT_V6T2, 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
1531   {ARM_EXT_V6T2, 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
1532   {ARM_EXT_V6T2, 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
1533   {ARM_EXT_V6T2, 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
1534   {ARM_EXT_V6T2, 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
1535   {ARM_EXT_V6T2, 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
1536   {ARM_EXT_V6T2, 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
1537   {ARM_EXT_V6T2, 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
1538   {ARM_EXT_V6T2, 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
1539   {ARM_EXT_V6T2, 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
1540   {ARM_EXT_V6T2, 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
1541   {ARM_EXT_V6T2, 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
1542   {ARM_EXT_V6T2, 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
1543   {ARM_EXT_V6T2, 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
1544   {ARM_EXT_V6T2, 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
1545   {ARM_EXT_V6T2, 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
1546   {ARM_EXT_V6T2, 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
1547   {ARM_EXT_V6T2, 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
1548   {ARM_EXT_V6T2, 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
1549   {ARM_EXT_V6T2, 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
1550   {ARM_EXT_V6T2, 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
1551   {ARM_EXT_V6T2, 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
1552   {ARM_EXT_V6T2, 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
1553   {ARM_EXT_V6T2, 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
1554   {ARM_EXT_V6T2, 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
1555   {ARM_EXT_V6T2, 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
1556   {ARM_EXT_V6T2, 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
1557   {ARM_EXT_V6T2, 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
1558   {ARM_EXT_V6T2, 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
1559   {ARM_EXT_V6T2, 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
1560   {ARM_EXT_V6T2, 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
1561   {ARM_EXT_V6T2, 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
1562   {ARM_EXT_V6T2, 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
1563   {ARM_EXT_V6T2, 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
1564   {ARM_EXT_V6T2, 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
1565   {ARM_EXT_V6T2, 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
1566   {ARM_EXT_V6T2, 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
1567   {ARM_EXT_V6T2, 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
1568   {ARM_EXT_V6T2, 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
1569   {ARM_EXT_V6T2, 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
1570   {ARM_EXT_V6T2, 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4d, %16-19r"},
1571   {ARM_EXT_V6T2, 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
1572   {ARM_EXT_V6T2, 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
1573   {ARM_EXT_V6T2, 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
1574   {ARM_EXT_V6T2, 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
1575   {ARM_EXT_V6T2, 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
1576   {ARM_EXT_V6T2, 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
1577   {ARM_EXT_V6T2, 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
1578   {ARM_EXT_V6T2, 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
1579   {ARM_EXT_V6T2, 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
1580   {ARM_EXT_V6T2, 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
1581   {ARM_EXT_V6T2, 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
1582   {ARM_EXT_V6T2, 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
1583   {ARM_EXT_V6T2, 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
1584   {ARM_EXT_V6T2, 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
1585   {ARM_EXT_V6T2, 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
1586   {ARM_EXT_V6T2, 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
1587   {ARM_EXT_V6T2, 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
1588   {ARM_EXT_V6T2, 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
1589   {ARM_EXT_V6T2, 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
1590   {ARM_EXT_V6T2, 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
1591   {ARM_EXT_V6T2, 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
1592   {ARM_EXT_V6T2, 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
1593   {ARM_EXT_V6T2, 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
1594   {ARM_EXT_V6T2, 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
1595   {ARM_EXT_V6T2, 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
1596   {ARM_EXT_V6T2, 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
1597   {ARM_EXT_V6T2, 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
1598   {ARM_EXT_V6T2, 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
1599   {ARM_EXT_V6T2, 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
1600   {ARM_EXT_V6T2, 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
1601   {ARM_EXT_V6T2, 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
1602   {ARM_EXT_V6T2, 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
1603   {ARM_EXT_V6T2, 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
1604   {ARM_EXT_V6T2, 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
1605   {ARM_EXT_V6T2, 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
1606   {ARM_EXT_V6T2, 0xf810f000, 0xff70f000, "pld%c\t%a"},
1607   {ARM_EXT_V6T2, 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
1608   {ARM_EXT_V6T2, 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
1609   {ARM_EXT_V6T2, 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
1610   {ARM_EXT_V6T2, 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
1611   {ARM_EXT_V6T2, 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
1612   {ARM_EXT_V6T2, 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
1613   {ARM_EXT_V6T2, 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
1614   {ARM_EXT_V6T2, 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
1615   {ARM_EXT_V6T2, 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
1616   {ARM_EXT_V6T2, 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
1617   {ARM_EXT_V6T2, 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
1618   {ARM_EXT_V6T2, 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
1619   {ARM_EXT_V6T2, 0xfb100000, 0xfff000c0, "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
1620   {ARM_EXT_V6T2, 0xfbc00080, 0xfff000c0, "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
1621   {ARM_EXT_V6T2, 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
1622   {ARM_EXT_V6T2, 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
1623   {ARM_EXT_V6T2, 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4d, %16-19r%s"},
1624   {ARM_EXT_V6T2, 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
1625   {ARM_EXT_V6T2, 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
1626   {ARM_EXT_V6T2, 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
1627   {ARM_EXT_V6T2, 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
1628   {ARM_EXT_V6T2, 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
1629   {ARM_EXT_V6T2, 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
1630   {ARM_EXT_V6T2, 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
1631   {ARM_EXT_V6T2, 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
1632   {ARM_EXT_V6T2, 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
1633   {ARM_EXT_V6T2, 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
1634   {ARM_EXT_V6T2, 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
1635   {ARM_EXT_V6T2, 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
1636   {ARM_EXT_V6T2, 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
1637   {ARM_EXT_V6T2, 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
1638   {ARM_EXT_V6T2, 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
1639   {ARM_EXT_V6T2, 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
1640   {ARM_EXT_V6T2, 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
1641   {ARM_EXT_V6T2, 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
1642   {ARM_EXT_V6T2, 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
1643   {ARM_EXT_V6T2, 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
1644   {ARM_EXT_V6T2, 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
1645   {ARM_EXT_V6T2, 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
1646   {ARM_EXT_V6T2, 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
1647   {ARM_EXT_V6T2, 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
1648   {ARM_EXT_V6T2, 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
1649   {ARM_EXT_V6T2, 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
1650   {ARM_EXT_V6T2, 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
1651   {ARM_EXT_V6T2, 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
1652   {ARM_EXT_V6T2, 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
1653   {ARM_EXT_V6T2, 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
1654   {ARM_EXT_V6T2, 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
1655   {ARM_EXT_V6T2, 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
1656   {ARM_EXT_V6T2, 0xe9400000, 0xff500000, "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
1657   {ARM_EXT_V6T2, 0xe9500000, 0xff500000, "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
1658   {ARM_EXT_V6T2, 0xe8600000, 0xff700000, "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
1659   {ARM_EXT_V6T2, 0xe8700000, 0xff700000, "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
1660   {ARM_EXT_V6T2, 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
1661   {ARM_EXT_V6T2, 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
1662
1663   /* Filter out Bcc with cond=E or F, which are used for other instructions.  */
1664   {ARM_EXT_V6T2, 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
1665   {ARM_EXT_V6T2, 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
1666   {ARM_EXT_V6T2, 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
1667   {ARM_EXT_V6T2, 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
1668
1669   /* These have been 32-bit since the invention of Thumb.  */
1670   {ARM_EXT_V4T,  0xf000c000, 0xf800d001, "blx%c\t%B%x"},
1671   {ARM_EXT_V4T,  0xf000d000, 0xf800d000, "bl%c\t%B%x"},
1672
1673   /* Fallback.  */
1674   {ARM_EXT_V1,   0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
1675   {0, 0, 0, 0}
1676 };
1677
1678 static const char *const arm_conditional[] =
1679 {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
1680  "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
1681
1682 static const char *const arm_fp_const[] =
1683 {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
1684
1685 static const char *const arm_shift[] =
1686 {"lsl", "lsr", "asr", "ror"};
1687
1688 typedef struct
1689 {
1690   const char *name;
1691   const char *description;
1692   const char *reg_names[16];
1693 }
1694 arm_regname;
1695
1696 static const arm_regname regnames[] =
1697 {
1698   { "raw" , "Select raw register names",
1699     { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
1700   { "gcc",  "Select register names used by GCC",
1701     { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl",  "fp",  "ip",  "sp",  "lr",  "pc" }},
1702   { "std",  "Select register names used in ARM's ISA documentation",
1703     { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp",  "lr",  "pc" }},
1704   { "apcs", "Select register names used in the APCS",
1705     { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl",  "fp",  "ip",  "sp",  "lr",  "pc" }},
1706   { "atpcs", "Select register names used in the ATPCS",
1707     { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7",  "v8",  "IP",  "SP",  "LR",  "PC" }},
1708   { "special-atpcs", "Select special register names used in the ATPCS",
1709     { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL",  "FP",  "IP",  "SP",  "LR",  "PC" }},
1710 };
1711
1712 static const char *const iwmmxt_wwnames[] =
1713 {"b", "h", "w", "d"};
1714
1715 static const char *const iwmmxt_wwssnames[] =
1716 {"b", "bus", "bc", "bss",
1717  "h", "hus", "hc", "hss",
1718  "w", "wus", "wc", "wss",
1719  "d", "dus", "dc", "dss"
1720 };
1721
1722 static const char *const iwmmxt_regnames[] =
1723 { "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
1724   "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
1725 };
1726
1727 static const char *const iwmmxt_cregnames[] =
1728 { "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
1729   "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
1730 };
1731
1732 /* Default to GCC register name set.  */
1733 static unsigned int regname_selected = 1;
1734
1735 #define NUM_ARM_REGNAMES  NUM_ELEM (regnames)
1736 #define arm_regnames      regnames[regname_selected].reg_names
1737
1738 static bfd_boolean force_thumb = FALSE;
1739
1740 /* Current IT instruction state.  This contains the same state as the IT
1741    bits in the CPSR.  */
1742 static unsigned int ifthen_state;
1743 /* IT state for the next instruction.  */
1744 static unsigned int ifthen_next_state;
1745 /* The address of the insn for which the IT state is valid.  */
1746 static bfd_vma ifthen_address;
1747 #define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
1748 /* Indicates that the current Conditional state is unconditional or outside
1749    an IT block.  */
1750 #define COND_UNCOND 16
1751
1752 \f
1753 /* Functions.  */
1754 int
1755 get_arm_regname_num_options (void)
1756 {
1757   return NUM_ARM_REGNAMES;
1758 }
1759
1760 int
1761 set_arm_regname_option (int option)
1762 {
1763   int old = regname_selected;
1764   regname_selected = option;
1765   return old;
1766 }
1767
1768 int
1769 get_arm_regnames (int option,
1770                   const char **setname,
1771                   const char **setdescription,
1772                   const char *const **register_names)
1773 {
1774   *setname = regnames[option].name;
1775   *setdescription = regnames[option].description;
1776   *register_names = regnames[option].reg_names;
1777   return 16;
1778 }
1779
1780 /* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
1781    Returns pointer to following character of the format string and
1782    fills in *VALUEP and *WIDTHP with the extracted value and number of
1783    bits extracted.  WIDTHP can be NULL.  */
1784
1785 static const char *
1786 arm_decode_bitfield (const char *ptr,
1787                      unsigned long insn,
1788                      unsigned long *valuep,
1789                      int *widthp)
1790 {
1791   unsigned long value = 0;
1792   int width = 0;
1793
1794   do
1795     {
1796       int start, end;
1797       int bits;
1798
1799       for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
1800         start = start * 10 + *ptr - '0';
1801       if (*ptr == '-')
1802         for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
1803           end = end * 10 + *ptr - '0';
1804       else
1805         end = start;
1806       bits = end - start;
1807       if (bits < 0)
1808         abort ();
1809       value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
1810       width += bits + 1;
1811     }
1812   while (*ptr++ == ',');
1813   *valuep = value;
1814   if (widthp)
1815     *widthp = width;
1816   return ptr - 1;
1817 }
1818
1819 static void
1820 arm_decode_shift (long given, fprintf_ftype func, void *stream,
1821                   bfd_boolean print_shift)
1822 {
1823   func (stream, "%s", arm_regnames[given & 0xf]);
1824
1825   if ((given & 0xff0) != 0)
1826     {
1827       if ((given & 0x10) == 0)
1828         {
1829           int amount = (given & 0xf80) >> 7;
1830           int shift = (given & 0x60) >> 5;
1831
1832           if (amount == 0)
1833             {
1834               if (shift == 3)
1835                 {
1836                   func (stream, ", rrx");
1837                   return;
1838                 }
1839
1840               amount = 32;
1841             }
1842
1843           if (print_shift)
1844             func (stream, ", %s #%d", arm_shift[shift], amount);
1845           else
1846             func (stream, ", #%d", amount);
1847         }
1848       else if ((given & 0x80) == 0x80)
1849         func (stream, "\t; <illegal shifter operand>");
1850       else if (print_shift)
1851         func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
1852               arm_regnames[(given & 0xf00) >> 8]);
1853       else
1854         func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
1855     }
1856 }
1857
1858 #define W_BIT 21
1859 #define I_BIT 22
1860 #define U_BIT 23
1861 #define P_BIT 24
1862
1863 #define WRITEBACK_BIT_SET   (given & (1 << W_BIT))
1864 #define IMMEDIATE_BIT_SET   (given & (1 << I_BIT))
1865 #define NEGATIVE_BIT_SET   ((given & (1 << U_BIT)) == 0)
1866 #define PRE_BIT_SET         (given & (1 << P_BIT))
1867
1868 /* Print one coprocessor instruction on INFO->STREAM.
1869    Return TRUE if the instuction matched, FALSE if this is not a
1870    recognised coprocessor instruction.  */
1871
1872 static bfd_boolean
1873 print_insn_coprocessor (bfd_vma pc,
1874                         struct disassemble_info *info,
1875                         long given,
1876                         bfd_boolean thumb)
1877 {
1878   const struct opcode32 *insn;
1879   void *stream = info->stream;
1880   fprintf_ftype func = info->fprintf_func;
1881   unsigned long mask;
1882   unsigned long value = 0;
1883   struct arm_private_data *private_data = info->private_data;
1884   unsigned long allowed_arches = private_data->features.coproc;
1885   int cond;
1886
1887   for (insn = coprocessor_opcodes; insn->assembler; insn++)
1888     {
1889       unsigned long u_reg = 16;
1890       bfd_boolean is_unpredictable = FALSE;
1891       signed long value_in_comment = 0;
1892       const char *c;
1893
1894       if (insn->arch == 0)
1895         switch (insn->value)
1896           {
1897           case SENTINEL_IWMMXT_START:
1898             if (info->mach != bfd_mach_arm_XScale
1899                 && info->mach != bfd_mach_arm_iWMMXt
1900                 && info->mach != bfd_mach_arm_iWMMXt2)
1901               do
1902                 insn++;
1903               while (insn->arch != 0 && insn->value != SENTINEL_IWMMXT_END);
1904             continue;
1905
1906           case SENTINEL_IWMMXT_END:
1907             continue;
1908
1909           case SENTINEL_GENERIC_START:
1910             allowed_arches = private_data->features.core;
1911             continue;
1912
1913           default:
1914             abort ();
1915           }
1916
1917       mask = insn->mask;
1918       value = insn->value;
1919       if (thumb)
1920         {
1921           /* The high 4 bits are 0xe for Arm conditional instructions, and
1922              0xe for arm unconditional instructions.  The rest of the
1923              encoding is the same.  */
1924           mask |= 0xf0000000;
1925           value |= 0xe0000000;
1926           if (ifthen_state)
1927             cond = IFTHEN_COND;
1928           else
1929             cond = COND_UNCOND;
1930         }
1931       else
1932         {
1933           /* Only match unconditional instuctions against unconditional
1934              patterns.  */
1935           if ((given & 0xf0000000) == 0xf0000000)
1936             {
1937               mask |= 0xf0000000;
1938               cond = COND_UNCOND;
1939             }
1940           else
1941             {
1942               cond = (given >> 28) & 0xf;
1943               if (cond == 0xe)
1944                 cond = COND_UNCOND;
1945             }
1946         }
1947
1948       if ((given & mask) != value)
1949         continue;
1950
1951       if ((insn->arch & allowed_arches) == 0)
1952         continue;
1953
1954       for (c = insn->assembler; *c; c++)
1955         {
1956           if (*c == '%')
1957             {
1958               switch (*++c)
1959                 {
1960                 case '%':
1961                   func (stream, "%%");
1962                   break;
1963
1964                 case 'A':
1965                   {
1966                     int rn = (given >> 16) & 0xf;
1967                     bfd_vma offset = given & 0xff;
1968
1969                     func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
1970
1971                     if (PRE_BIT_SET || WRITEBACK_BIT_SET)
1972                       {
1973                         /* Not unindexed.  The offset is scaled.  */
1974                         offset = offset * 4;
1975                         if (NEGATIVE_BIT_SET)
1976                           offset = - offset;
1977                         if (rn != 15)
1978                           value_in_comment = offset;
1979                       }
1980
1981                     if (PRE_BIT_SET)
1982                       {
1983                         if (offset)
1984                           func (stream, ", #%d]%s",
1985                                 (int) offset,
1986                                 WRITEBACK_BIT_SET ? "!" : "");
1987                         else if (NEGATIVE_BIT_SET)
1988                           func (stream, ", #-0]");
1989                         else
1990                           func (stream, "]");
1991                       }
1992                     else
1993                       {
1994                         func (stream, "]");
1995
1996                         if (WRITEBACK_BIT_SET)
1997                           {
1998                             if (offset)
1999                               func (stream, ", #%d", (int) offset);
2000                             else if (NEGATIVE_BIT_SET)
2001                               func (stream, ", #-0");
2002                           }
2003                         else
2004                           {
2005                             func (stream, ", {%s%d}",
2006                                   (NEGATIVE_BIT_SET && !offset) ? "-" : "",
2007                                   (int) offset);
2008                             value_in_comment = offset;
2009                           }
2010                       }
2011                     if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
2012                       {
2013                         func (stream, "\t; ");
2014                         /* For unaligned PCs, apply off-by-alignment
2015                            correction.  */
2016                         info->print_address_func (offset + pc
2017                                                   + info->bytes_per_chunk * 2
2018                                                   - (pc & 3),
2019                                                   info);
2020                       }
2021                   }
2022                   break;
2023
2024                 case 'B':
2025                   {
2026                     int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
2027                     int offset = (given >> 1) & 0x3f;
2028
2029                     if (offset == 1)
2030                       func (stream, "{d%d}", regno);
2031                     else if (regno + offset > 32)
2032                       func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
2033                     else
2034                       func (stream, "{d%d-d%d}", regno, regno + offset - 1);
2035                   }
2036                   break;
2037
2038                 case 'u':
2039                   if (cond != COND_UNCOND)
2040                     is_unpredictable = TRUE;
2041
2042                   /* Fall through.  */
2043                 case 'c':
2044                   func (stream, "%s", arm_conditional[cond]);
2045                   break;
2046
2047                 case 'I':
2048                   /* Print a Cirrus/DSP shift immediate.  */
2049                   /* Immediates are 7bit signed ints with bits 0..3 in
2050                      bits 0..3 of opcode and bits 4..6 in bits 5..7
2051                      of opcode.  */
2052                   {
2053                     int imm;
2054
2055                     imm = (given & 0xf) | ((given & 0xe0) >> 1);
2056
2057                     /* Is ``imm'' a negative number?  */
2058                     if (imm & 0x40)
2059                       imm |= (-1 << 7);
2060
2061                     func (stream, "%d", imm);
2062                   }
2063
2064                   break;
2065
2066                 case 'F':
2067                   switch (given & 0x00408000)
2068                     {
2069                     case 0:
2070                       func (stream, "4");
2071                       break;
2072                     case 0x8000:
2073                       func (stream, "1");
2074                       break;
2075                     case 0x00400000:
2076                       func (stream, "2");
2077                       break;
2078                     default:
2079                       func (stream, "3");
2080                     }
2081                   break;
2082
2083                 case 'P':
2084                   switch (given & 0x00080080)
2085                     {
2086                     case 0:
2087                       func (stream, "s");
2088                       break;
2089                     case 0x80:
2090                       func (stream, "d");
2091                       break;
2092                     case 0x00080000:
2093                       func (stream, "e");
2094                       break;
2095                     default:
2096                       func (stream, _("<illegal precision>"));
2097                       break;
2098                     }
2099                   break;
2100
2101                 case 'Q':
2102                   switch (given & 0x00408000)
2103                     {
2104                     case 0:
2105                       func (stream, "s");
2106                       break;
2107                     case 0x8000:
2108                       func (stream, "d");
2109                       break;
2110                     case 0x00400000:
2111                       func (stream, "e");
2112                       break;
2113                     default:
2114                       func (stream, "p");
2115                       break;
2116                     }
2117                   break;
2118
2119                 case 'R':
2120                   switch (given & 0x60)
2121                     {
2122                     case 0:
2123                       break;
2124                     case 0x20:
2125                       func (stream, "p");
2126                       break;
2127                     case 0x40:
2128                       func (stream, "m");
2129                       break;
2130                     default:
2131                       func (stream, "z");
2132                       break;
2133                     }
2134                   break;
2135
2136                 case '0': case '1': case '2': case '3': case '4':
2137                 case '5': case '6': case '7': case '8': case '9':
2138                   {
2139                     int width;
2140
2141                     c = arm_decode_bitfield (c, given, &value, &width);
2142
2143                     switch (*c)
2144                       {
2145                       case 'R':
2146                         if (value == 15)
2147                           is_unpredictable = TRUE;
2148                         /* Fall through.  */
2149                       case 'r':
2150                         if (c[1] == 'u')
2151                           {
2152                             /* Eat the 'u' character.  */
2153                             ++ c;
2154
2155                             if (u_reg == value)
2156                               is_unpredictable = TRUE;
2157                             u_reg = value;
2158                           }
2159                         func (stream, "%s", arm_regnames[value]);
2160                         break;
2161                       case 'D':
2162                         func (stream, "d%ld", value);
2163                         break;
2164                       case 'Q':
2165                         if (value & 1)
2166                           func (stream, "<illegal reg q%ld.5>", value >> 1);
2167                         else
2168                           func (stream, "q%ld", value >> 1);
2169                         break;
2170                       case 'd':
2171                         func (stream, "%ld", value);
2172                         value_in_comment = value;
2173                         break;
2174                       case 'k':
2175                         {
2176                           int from = (given & (1 << 7)) ? 32 : 16;
2177                           func (stream, "%ld", from - value);
2178                         }
2179                         break;
2180
2181                       case 'f':
2182                         if (value > 7)
2183                           func (stream, "#%s", arm_fp_const[value & 7]);
2184                         else
2185                           func (stream, "f%ld", value);
2186                         break;
2187
2188                       case 'w':
2189                         if (width == 2)
2190                           func (stream, "%s", iwmmxt_wwnames[value]);
2191                         else
2192                           func (stream, "%s", iwmmxt_wwssnames[value]);
2193                         break;
2194
2195                       case 'g':
2196                         func (stream, "%s", iwmmxt_regnames[value]);
2197                         break;
2198                       case 'G':
2199                         func (stream, "%s", iwmmxt_cregnames[value]);
2200                         break;
2201
2202                       case 'x':
2203                         func (stream, "0x%lx", (value & 0xffffffffUL));
2204                         break;
2205
2206                       case 'c':
2207                         switch (value)
2208                           {
2209                           case 0:
2210                             func (stream, "eq");
2211                             break;
2212
2213                           case 1:
2214                             func (stream, "vs");
2215                             break;
2216
2217                           case 2:
2218                             func (stream, "ge");
2219                             break;
2220
2221                           case 3:
2222                             func (stream, "gt");
2223                             break;
2224
2225                           default:
2226                             func (stream, "??");
2227                             break;
2228                           }
2229                         break;
2230
2231                       case '`':
2232                         c++;
2233                         if (value == 0)
2234                           func (stream, "%c", *c);
2235                         break;
2236                       case '\'':
2237                         c++;
2238                         if (value == ((1ul << width) - 1))
2239                           func (stream, "%c", *c);
2240                         break;
2241                       case '?':
2242                         func (stream, "%c", c[(1 << width) - (int) value]);
2243                         c += 1 << width;
2244                         break;
2245                       default:
2246                         abort ();
2247                       }
2248                     break;
2249
2250                   case 'y':
2251                   case 'z':
2252                     {
2253                       int single = *c++ == 'y';
2254                       int regno;
2255
2256                       switch (*c)
2257                         {
2258                         case '4': /* Sm pair */
2259                         case '0': /* Sm, Dm */
2260                           regno = given & 0x0000000f;
2261                           if (single)
2262                             {
2263                               regno <<= 1;
2264                               regno += (given >> 5) & 1;
2265                             }
2266                           else
2267                             regno += ((given >> 5) & 1) << 4;
2268                           break;
2269
2270                         case '1': /* Sd, Dd */
2271                           regno = (given >> 12) & 0x0000000f;
2272                           if (single)
2273                             {
2274                               regno <<= 1;
2275                               regno += (given >> 22) & 1;
2276                             }
2277                           else
2278                             regno += ((given >> 22) & 1) << 4;
2279                           break;
2280
2281                         case '2': /* Sn, Dn */
2282                           regno = (given >> 16) & 0x0000000f;
2283                           if (single)
2284                             {
2285                               regno <<= 1;
2286                               regno += (given >> 7) & 1;
2287                             }
2288                           else
2289                             regno += ((given >> 7) & 1) << 4;
2290                           break;
2291
2292                         case '3': /* List */
2293                           func (stream, "{");
2294                           regno = (given >> 12) & 0x0000000f;
2295                           if (single)
2296                             {
2297                               regno <<= 1;
2298                               regno += (given >> 22) & 1;
2299                             }
2300                           else
2301                             regno += ((given >> 22) & 1) << 4;
2302                           break;
2303
2304                         default:
2305                           abort ();
2306                         }
2307
2308                       func (stream, "%c%d", single ? 's' : 'd', regno);
2309
2310                       if (*c == '3')
2311                         {
2312                           int count = given & 0xff;
2313
2314                           if (single == 0)
2315                             count >>= 1;
2316
2317                           if (--count)
2318                             {
2319                               func (stream, "-%c%d",
2320                                     single ? 's' : 'd',
2321                                     regno + count);
2322                             }
2323
2324                           func (stream, "}");
2325                         }
2326                       else if (*c == '4')
2327                         func (stream, ", %c%d", single ? 's' : 'd',
2328                               regno + 1);
2329                     }
2330                     break;
2331
2332                   case 'L':
2333                     switch (given & 0x00400100)
2334                       {
2335                       case 0x00000000: func (stream, "b"); break;
2336                       case 0x00400000: func (stream, "h"); break;
2337                       case 0x00000100: func (stream, "w"); break;
2338                       case 0x00400100: func (stream, "d"); break;
2339                       default:
2340                         break;
2341                       }
2342                     break;
2343
2344                   case 'Z':
2345                     {
2346                       /* given (20, 23) | given (0, 3) */
2347                       value = ((given >> 16) & 0xf0) | (given & 0xf);
2348                       func (stream, "%d", (int) value);
2349                     }
2350                     break;
2351
2352                   case 'l':
2353                     /* This is like the 'A' operator, except that if
2354                        the width field "M" is zero, then the offset is
2355                        *not* multiplied by four.  */
2356                     {
2357                       int offset = given & 0xff;
2358                       int multiplier = (given & 0x00000100) ? 4 : 1;
2359
2360                       func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
2361
2362                       if (multiplier > 1)
2363                         {
2364                           value_in_comment = offset * multiplier;
2365                           if (NEGATIVE_BIT_SET)
2366                             value_in_comment = - value_in_comment;
2367                         }
2368
2369                       if (offset)
2370                         {
2371                           if (PRE_BIT_SET)
2372                             func (stream, ", #%s%d]%s",
2373                                   NEGATIVE_BIT_SET ? "-" : "",
2374                                   offset * multiplier,
2375                                   WRITEBACK_BIT_SET ? "!" : "");
2376                           else
2377                             func (stream, "], #%s%d",
2378                                   NEGATIVE_BIT_SET ? "-" : "",
2379                                   offset * multiplier);
2380                         }
2381                       else
2382                         func (stream, "]");
2383                     }
2384                     break;
2385
2386                   case 'r':
2387                     {
2388                       int imm4 = (given >> 4) & 0xf;
2389                       int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
2390                       int ubit = ! NEGATIVE_BIT_SET;
2391                       const char *rm = arm_regnames [given & 0xf];
2392                       const char *rn = arm_regnames [(given >> 16) & 0xf];
2393
2394                       switch (puw_bits)
2395                         {
2396                         case 1:
2397                         case 3:
2398                           func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
2399                           if (imm4)
2400                             func (stream, ", lsl #%d", imm4);
2401                           break;
2402
2403                         case 4:
2404                         case 5:
2405                         case 6:
2406                         case 7:
2407                           func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
2408                           if (imm4 > 0)
2409                             func (stream, ", lsl #%d", imm4);
2410                           func (stream, "]");
2411                           if (puw_bits == 5 || puw_bits == 7)
2412                             func (stream, "!");
2413                           break;
2414
2415                         default:
2416                           func (stream, "INVALID");
2417                         }
2418                     }
2419                     break;
2420
2421                   case 'i':
2422                     {
2423                       long imm5;
2424                       imm5 = ((given & 0x100) >> 4) | (given & 0xf);
2425                       func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
2426                     }
2427                     break;
2428
2429                   default:
2430                     abort ();
2431                   }
2432                 }
2433             }
2434           else
2435             func (stream, "%c", *c);
2436         }
2437
2438       if (value_in_comment > 32 || value_in_comment < -16)
2439         func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
2440
2441       if (is_unpredictable)
2442         func (stream, UNPREDICTABLE_INSTRUCTION);
2443
2444       return TRUE;
2445     }
2446   return FALSE;
2447 }
2448
2449 /* Decodes and prints ARM addressing modes.  Returns the offset
2450    used in the address, if any, if it is worthwhile printing the
2451    offset as a hexadecimal value in a comment at the end of the
2452    line of disassembly.  */
2453
2454 static signed long
2455 print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
2456 {
2457   void *stream = info->stream;
2458   fprintf_ftype func = info->fprintf_func;
2459   bfd_vma offset = 0;
2460
2461   if (((given & 0x000f0000) == 0x000f0000)
2462       && ((given & 0x02000000) == 0))
2463     {
2464       offset = given & 0xfff;
2465
2466       func (stream, "[pc");
2467
2468       if (PRE_BIT_SET)
2469         {
2470           /* Pre-indexed.  Elide offset of positive zero when
2471              non-writeback.  */
2472           if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
2473             func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
2474
2475           if (NEGATIVE_BIT_SET)
2476             offset = -offset;
2477
2478           offset += pc + 8;
2479
2480           /* Cope with the possibility of write-back
2481              being used.  Probably a very dangerous thing
2482              for the programmer to do, but who are we to
2483              argue ?  */
2484           func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : "");
2485         }
2486       else  /* Post indexed.  */
2487         {
2488           func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
2489
2490           /* Ie ignore the offset.  */
2491           offset = pc + 8;
2492         }
2493
2494       func (stream, "\t; ");
2495       info->print_address_func (offset, info);
2496       offset = 0;
2497     }
2498   else
2499     {
2500       func (stream, "[%s",
2501             arm_regnames[(given >> 16) & 0xf]);
2502
2503       if (PRE_BIT_SET)
2504         {
2505           if ((given & 0x02000000) == 0)
2506             {
2507               /* Elide offset of positive zero when non-writeback.  */
2508               offset = given & 0xfff;
2509               if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
2510                 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
2511             }
2512           else
2513             {
2514               func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : "");
2515               arm_decode_shift (given, func, stream, TRUE);
2516             }
2517
2518           func (stream, "]%s",
2519                 WRITEBACK_BIT_SET ? "!" : "");
2520         }
2521       else
2522         {
2523           if ((given & 0x02000000) == 0)
2524             {
2525               /* Always show offset.  */
2526               offset = given & 0xfff;
2527               func (stream, "], #%s%d",
2528                     NEGATIVE_BIT_SET ? "-" : "", (int) offset);
2529             }
2530           else
2531             {
2532               func (stream, "], %s",
2533                     NEGATIVE_BIT_SET ? "-" : "");
2534               arm_decode_shift (given, func, stream, TRUE);
2535             }
2536         }
2537     }
2538
2539   return (signed long) offset;
2540 }
2541
2542 /* Print one neon instruction on INFO->STREAM.
2543    Return TRUE if the instuction matched, FALSE if this is not a
2544    recognised neon instruction.  */
2545
2546 static bfd_boolean
2547 print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
2548 {
2549   const struct opcode32 *insn;
2550   void *stream = info->stream;
2551   fprintf_ftype func = info->fprintf_func;
2552
2553   if (thumb)
2554     {
2555       if ((given & 0xef000000) == 0xef000000)
2556         {
2557           /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding.  */
2558           unsigned long bit28 = given & (1 << 28);
2559
2560           given &= 0x00ffffff;
2561           if (bit28)
2562             given |= 0xf3000000;
2563           else
2564             given |= 0xf2000000;
2565         }
2566       else if ((given & 0xff000000) == 0xf9000000)
2567         given ^= 0xf9000000 ^ 0xf4000000;
2568       else
2569         return FALSE;
2570     }
2571
2572   for (insn = neon_opcodes; insn->assembler; insn++)
2573     {
2574       if ((given & insn->mask) == insn->value)
2575         {
2576           signed long value_in_comment = 0;
2577           bfd_boolean is_unpredictable = FALSE;
2578           const char *c;
2579
2580           for (c = insn->assembler; *c; c++)
2581             {
2582               if (*c == '%')
2583                 {
2584                   switch (*++c)
2585                     {
2586                     case '%':
2587                       func (stream, "%%");
2588                       break;
2589
2590                     case 'u':
2591                       if (thumb && ifthen_state)
2592                         is_unpredictable = TRUE;
2593
2594                       /* Fall through.  */
2595                     case 'c':
2596                       if (thumb && ifthen_state)
2597                         func (stream, "%s", arm_conditional[IFTHEN_COND]);
2598                       break;
2599
2600                     case 'A':
2601                       {
2602                         static const unsigned char enc[16] =
2603                         {
2604                           0x4, 0x14, /* st4 0,1 */
2605                           0x4, /* st1 2 */
2606                           0x4, /* st2 3 */
2607                           0x3, /* st3 4 */
2608                           0x13, /* st3 5 */
2609                           0x3, /* st1 6 */
2610                           0x1, /* st1 7 */
2611                           0x2, /* st2 8 */
2612                           0x12, /* st2 9 */
2613                           0x2, /* st1 10 */
2614                           0, 0, 0, 0, 0
2615                         };
2616                         int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
2617                         int rn = ((given >> 16) & 0xf);
2618                         int rm = ((given >> 0) & 0xf);
2619                         int align = ((given >> 4) & 0x3);
2620                         int type = ((given >> 8) & 0xf);
2621                         int n = enc[type] & 0xf;
2622                         int stride = (enc[type] >> 4) + 1;
2623                         int ix;
2624
2625                         func (stream, "{");
2626                         if (stride > 1)
2627                           for (ix = 0; ix != n; ix++)
2628                             func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
2629                         else if (n == 1)
2630                           func (stream, "d%d", rd);
2631                         else
2632                           func (stream, "d%d-d%d", rd, rd + n - 1);
2633                         func (stream, "}, [%s", arm_regnames[rn]);
2634                         if (align)
2635                           func (stream, " :%d", 32 << align);
2636                         func (stream, "]");
2637                         if (rm == 0xd)
2638                           func (stream, "!");
2639                         else if (rm != 0xf)
2640                           func (stream, ", %s", arm_regnames[rm]);
2641                       }
2642                       break;
2643
2644                     case 'B':
2645                       {
2646                         int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
2647                         int rn = ((given >> 16) & 0xf);
2648                         int rm = ((given >> 0) & 0xf);
2649                         int idx_align = ((given >> 4) & 0xf);
2650                         int align = 0;
2651                         int size = ((given >> 10) & 0x3);
2652                         int idx = idx_align >> (size + 1);
2653                         int length = ((given >> 8) & 3) + 1;
2654                         int stride = 1;
2655                         int i;
2656
2657                         if (length > 1 && size > 0)
2658                           stride = (idx_align & (1 << size)) ? 2 : 1;
2659
2660                         switch (length)
2661                           {
2662                           case 1:
2663                             {
2664                               int amask = (1 << size) - 1;
2665                               if ((idx_align & (1 << size)) != 0)
2666                                 return FALSE;
2667                               if (size > 0)
2668                                 {
2669                                   if ((idx_align & amask) == amask)
2670                                     align = 8 << size;
2671                                   else if ((idx_align & amask) != 0)
2672                                     return FALSE;
2673                                 }
2674                               }
2675                             break;
2676
2677                           case 2:
2678                             if (size == 2 && (idx_align & 2) != 0)
2679                               return FALSE;
2680                             align = (idx_align & 1) ? 16 << size : 0;
2681                             break;
2682
2683                           case 3:
2684                             if ((size == 2 && (idx_align & 3) != 0)
2685                                 || (idx_align & 1) != 0)
2686                               return FALSE;
2687                             break;
2688
2689                           case 4:
2690                             if (size == 2)
2691                               {
2692                                 if ((idx_align & 3) == 3)
2693                                   return FALSE;
2694                                 align = (idx_align & 3) * 64;
2695                               }
2696                             else
2697                               align = (idx_align & 1) ? 32 << size : 0;
2698                             break;
2699
2700                           default:
2701                             abort ();
2702                           }
2703
2704                         func (stream, "{");
2705                         for (i = 0; i < length; i++)
2706                           func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
2707                             rd + i * stride, idx);
2708                         func (stream, "}, [%s", arm_regnames[rn]);
2709                         if (align)
2710                           func (stream, " :%d", align);
2711                         func (stream, "]");
2712                         if (rm == 0xd)
2713                           func (stream, "!");
2714                         else if (rm != 0xf)
2715                           func (stream, ", %s", arm_regnames[rm]);
2716                       }
2717                       break;
2718
2719                     case 'C':
2720                       {
2721                         int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
2722                         int rn = ((given >> 16) & 0xf);
2723                         int rm = ((given >> 0) & 0xf);
2724                         int align = ((given >> 4) & 0x1);
2725                         int size = ((given >> 6) & 0x3);
2726                         int type = ((given >> 8) & 0x3);
2727                         int n = type + 1;
2728                         int stride = ((given >> 5) & 0x1);
2729                         int ix;
2730
2731                         if (stride && (n == 1))
2732                           n++;
2733                         else
2734                           stride++;
2735
2736                         func (stream, "{");
2737                         if (stride > 1)
2738                           for (ix = 0; ix != n; ix++)
2739                             func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
2740                         else if (n == 1)
2741                           func (stream, "d%d[]", rd);
2742                         else
2743                           func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
2744                         func (stream, "}, [%s", arm_regnames[rn]);
2745                         if (align)
2746                           {
2747                             align = (8 * (type + 1)) << size;
2748                             if (type == 3)
2749                               align = (size > 1) ? align >> 1 : align;
2750                             if (type == 2 || (type == 0 && !size))
2751                               func (stream, " :<bad align %d>", align);
2752                             else
2753                               func (stream, " :%d", align);
2754                           }
2755                         func (stream, "]");
2756                         if (rm == 0xd)
2757                           func (stream, "!");
2758                         else if (rm != 0xf)
2759                           func (stream, ", %s", arm_regnames[rm]);
2760                       }
2761                       break;
2762
2763                     case 'D':
2764                       {
2765                         int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
2766                         int size = (given >> 20) & 3;
2767                         int reg = raw_reg & ((4 << size) - 1);
2768                         int ix = raw_reg >> size >> 2;
2769
2770                         func (stream, "d%d[%d]", reg, ix);
2771                       }
2772                       break;
2773
2774                     case 'E':
2775                       /* Neon encoded constant for mov, mvn, vorr, vbic.  */
2776                       {
2777                         int bits = 0;
2778                         int cmode = (given >> 8) & 0xf;
2779                         int op = (given >> 5) & 0x1;
2780                         unsigned long value = 0, hival = 0;
2781                         unsigned shift;
2782                         int size = 0;
2783                         int isfloat = 0;
2784
2785                         bits |= ((given >> 24) & 1) << 7;
2786                         bits |= ((given >> 16) & 7) << 4;
2787                         bits |= ((given >> 0) & 15) << 0;
2788
2789                         if (cmode < 8)
2790                           {
2791                             shift = (cmode >> 1) & 3;
2792                             value = (unsigned long) bits << (8 * shift);
2793                             size = 32;
2794                           }
2795                         else if (cmode < 12)
2796                           {
2797                             shift = (cmode >> 1) & 1;
2798                             value = (unsigned long) bits << (8 * shift);
2799                             size = 16;
2800                           }
2801                         else if (cmode < 14)
2802                           {
2803                             shift = (cmode & 1) + 1;
2804                             value = (unsigned long) bits << (8 * shift);
2805                             value |= (1ul << (8 * shift)) - 1;
2806                             size = 32;
2807                           }
2808                         else if (cmode == 14)
2809                           {
2810                             if (op)
2811                               {
2812                                 /* Bit replication into bytes.  */
2813                                 int ix;
2814                                 unsigned long mask;
2815
2816                                 value = 0;
2817                                 hival = 0;
2818                                 for (ix = 7; ix >= 0; ix--)
2819                                   {
2820                                     mask = ((bits >> ix) & 1) ? 0xff : 0;
2821                                     if (ix <= 3)
2822                                       value = (value << 8) | mask;
2823                                     else
2824                                       hival = (hival << 8) | mask;
2825                                   }
2826                                 size = 64;
2827                               }
2828                             else
2829                               {
2830                                 /* Byte replication.  */
2831                                 value = (unsigned long) bits;
2832                                 size = 8;
2833                               }
2834                           }
2835                         else if (!op)
2836                           {
2837                             /* Floating point encoding.  */
2838                             int tmp;
2839
2840                             value = (unsigned long)  (bits & 0x7f) << 19;
2841                             value |= (unsigned long) (bits & 0x80) << 24;
2842                             tmp = bits & 0x40 ? 0x3c : 0x40;
2843                             value |= (unsigned long) tmp << 24;
2844                             size = 32;
2845                             isfloat = 1;
2846                           }
2847                         else
2848                           {
2849                             func (stream, "<illegal constant %.8x:%x:%x>",
2850                                   bits, cmode, op);
2851                             size = 32;
2852                             break;
2853                           }
2854                         switch (size)
2855                           {
2856                           case 8:
2857                             func (stream, "#%ld\t; 0x%.2lx", value, value);
2858                             break;
2859
2860                           case 16:
2861                             func (stream, "#%ld\t; 0x%.4lx", value, value);
2862                             break;
2863
2864                           case 32:
2865                             if (isfloat)
2866                               {
2867                                 unsigned char valbytes[4];
2868                                 double fvalue;
2869
2870                                 /* Do this a byte at a time so we don't have to
2871                                    worry about the host's endianness.  */
2872                                 valbytes[0] = value & 0xff;
2873                                 valbytes[1] = (value >> 8) & 0xff;
2874                                 valbytes[2] = (value >> 16) & 0xff;
2875                                 valbytes[3] = (value >> 24) & 0xff;
2876
2877                                 floatformat_to_double
2878                                   (& floatformat_ieee_single_little, valbytes,
2879                                   & fvalue);
2880
2881                                 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
2882                                       value);
2883                               }
2884                             else
2885                               func (stream, "#%ld\t; 0x%.8lx",
2886                                     (long) (((value & 0x80000000L) != 0)
2887                                             ? value | ~0xffffffffL : value),
2888                                     value);
2889                             break;
2890
2891                           case 64:
2892                             func (stream, "#0x%.8lx%.8lx", hival, value);
2893                             break;
2894
2895                           default:
2896                             abort ();
2897                           }
2898                       }
2899                       break;
2900
2901                     case 'F':
2902                       {
2903                         int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
2904                         int num = (given >> 8) & 0x3;
2905
2906                         if (!num)
2907                           func (stream, "{d%d}", regno);
2908                         else if (num + regno >= 32)
2909                           func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
2910                         else
2911                           func (stream, "{d%d-d%d}", regno, regno + num);
2912                       }
2913                       break;
2914
2915
2916                     case '0': case '1': case '2': case '3': case '4':
2917                     case '5': case '6': case '7': case '8': case '9':
2918                       {
2919                         int width;
2920                         unsigned long value;
2921
2922                         c = arm_decode_bitfield (c, given, &value, &width);
2923
2924                         switch (*c)
2925                           {
2926                           case 'r':
2927                             func (stream, "%s", arm_regnames[value]);
2928                             break;
2929                           case 'd':
2930                             func (stream, "%ld", value);
2931                             value_in_comment = value;
2932                             break;
2933                           case 'e':
2934                             func (stream, "%ld", (1ul << width) - value);
2935                             break;
2936
2937                           case 'S':
2938                           case 'T':
2939                           case 'U':
2940                             /* Various width encodings.  */
2941                             {
2942                               int base = 8 << (*c - 'S'); /* 8,16 or 32 */
2943                               int limit;
2944                               unsigned low, high;
2945
2946                               c++;
2947                               if (*c >= '0' && *c <= '9')
2948                                 limit = *c - '0';
2949                               else if (*c >= 'a' && *c <= 'f')
2950                                 limit = *c - 'a' + 10;
2951                               else
2952                                 abort ();
2953                               low = limit >> 2;
2954                               high = limit & 3;
2955
2956                               if (value < low || value > high)
2957                                 func (stream, "<illegal width %d>", base << value);
2958                               else
2959                                 func (stream, "%d", base << value);
2960                             }
2961                             break;
2962                           case 'R':
2963                             if (given & (1 << 6))
2964                               goto Q;
2965                             /* FALLTHROUGH */
2966                           case 'D':
2967                             func (stream, "d%ld", value);
2968                             break;
2969                           case 'Q':
2970                           Q:
2971                             if (value & 1)
2972                               func (stream, "<illegal reg q%ld.5>", value >> 1);
2973                             else
2974                               func (stream, "q%ld", value >> 1);
2975                             break;
2976
2977                           case '`':
2978                             c++;
2979                             if (value == 0)
2980                               func (stream, "%c", *c);
2981                             break;
2982                           case '\'':
2983                             c++;
2984                             if (value == ((1ul << width) - 1))
2985                               func (stream, "%c", *c);
2986                             break;
2987                           case '?':
2988                             func (stream, "%c", c[(1 << width) - (int) value]);
2989                             c += 1 << width;
2990                             break;
2991                           default:
2992                             abort ();
2993                           }
2994                         break;
2995
2996                       default:
2997                         abort ();
2998                       }
2999                     }
3000                 }
3001               else
3002                 func (stream, "%c", *c);
3003             }
3004
3005           if (value_in_comment > 32 || value_in_comment < -16)
3006             func (stream, "\t; 0x%lx", value_in_comment);
3007
3008           if (is_unpredictable)
3009             func (stream, UNPREDICTABLE_INSTRUCTION);
3010
3011           return TRUE;
3012         }
3013     }
3014   return FALSE;
3015 }
3016
3017 /* Return the name of a v7A special register.  */
3018
3019 static const char *
3020 banked_regname (unsigned reg)
3021 {
3022   switch (reg)
3023     {
3024       case 15: return "CPSR";
3025       case 32: return "R8_usr";
3026       case 33: return "R9_usr";
3027       case 34: return "R10_usr";
3028       case 35: return "R11_usr";
3029       case 36: return "R12_usr";
3030       case 37: return "SP_usr";
3031       case 38: return "LR_usr";
3032       case 40: return "R8_fiq";
3033       case 41: return "R9_fiq";
3034       case 42: return "R10_fiq";
3035       case 43: return "R11_fiq";
3036       case 44: return "R12_fiq";
3037       case 45: return "SP_fiq";
3038       case 46: return "LR_fiq";
3039       case 48: return "LR_irq";
3040       case 49: return "SP_irq";
3041       case 50: return "LR_svc";
3042       case 51: return "SP_svc";
3043       case 52: return "LR_abt";
3044       case 53: return "SP_abt";
3045       case 54: return "LR_und";
3046       case 55: return "SP_und";
3047       case 60: return "LR_mon";
3048       case 61: return "SP_mon";
3049       case 62: return "ELR_hyp";
3050       case 63: return "SP_hyp";
3051       case 79: return "SPSR";
3052       case 110: return "SPSR_fiq";
3053       case 112: return "SPSR_irq";
3054       case 114: return "SPSR_svc";
3055       case 116: return "SPSR_abt";
3056       case 118: return "SPSR_und";
3057       case 124: return "SPSR_mon";
3058       case 126: return "SPSR_hyp";
3059       default: return NULL;
3060     }
3061 }
3062
3063 /* Return the name of the DMB/DSB option.  */
3064 static const char *
3065 data_barrier_option (unsigned option)
3066 {
3067   switch (option & 0xf)
3068     {
3069     case 0xf: return "sy";
3070     case 0xe: return "st";
3071     case 0xd: return "ld";
3072     case 0xb: return "ish";
3073     case 0xa: return "ishst";
3074     case 0x9: return "ishld";
3075     case 0x7: return "un";
3076     case 0x6: return "unst";
3077     case 0x5: return "nshld";
3078     case 0x3: return "osh";
3079     case 0x2: return "oshst";
3080     case 0x1: return "oshld";
3081     default:  return NULL;
3082     }
3083 }
3084
3085 /* Print one ARM instruction from PC on INFO->STREAM.  */
3086
3087 static void
3088 print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
3089 {
3090   const struct opcode32 *insn;
3091   void *stream = info->stream;
3092   fprintf_ftype func = info->fprintf_func;
3093   struct arm_private_data *private_data = info->private_data;
3094
3095   if (print_insn_coprocessor (pc, info, given, FALSE))
3096     return;
3097
3098   if (print_insn_neon (info, given, FALSE))
3099     return;
3100
3101   for (insn = arm_opcodes; insn->assembler; insn++)
3102     {
3103       if ((given & insn->mask) != insn->value)
3104         continue;
3105
3106       if ((insn->arch & private_data->features.core) == 0)
3107         continue;
3108
3109       /* Special case: an instruction with all bits set in the condition field
3110          (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
3111          or by the catchall at the end of the table.  */
3112       if ((given & 0xF0000000) != 0xF0000000
3113           || (insn->mask & 0xF0000000) == 0xF0000000
3114           || (insn->mask == 0 && insn->value == 0))
3115         {
3116           unsigned long u_reg = 16;
3117           unsigned long U_reg = 16;
3118           bfd_boolean is_unpredictable = FALSE;
3119           signed long value_in_comment = 0;
3120           const char *c;
3121
3122           for (c = insn->assembler; *c; c++)
3123             {
3124               if (*c == '%')
3125                 {
3126                   bfd_boolean allow_unpredictable = FALSE;
3127
3128                   switch (*++c)
3129                     {
3130                     case '%':
3131                       func (stream, "%%");
3132                       break;
3133
3134                     case 'a':
3135                       value_in_comment = print_arm_address (pc, info, given);
3136                       break;
3137
3138                     case 'P':
3139                       /* Set P address bit and use normal address
3140                          printing routine.  */
3141                       value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
3142                       break;
3143
3144                     case 'S':
3145                       allow_unpredictable = TRUE;
3146                     case 's':
3147                       if ((given & 0x004f0000) == 0x004f0000)
3148                         {
3149                           /* PC relative with immediate offset.  */
3150                           bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
3151
3152                           if (PRE_BIT_SET)
3153                             {
3154                               /* Elide positive zero offset.  */
3155                               if (offset || NEGATIVE_BIT_SET)
3156                                 func (stream, "[pc, #%s%d]\t; ",
3157                                       NEGATIVE_BIT_SET ? "-" : "", (int) offset);
3158                               else
3159                                 func (stream, "[pc]\t; ");
3160                               if (NEGATIVE_BIT_SET)
3161                                 offset = -offset;
3162                               info->print_address_func (offset + pc + 8, info);
3163                             }
3164                           else
3165                             {
3166                               /* Always show the offset.  */
3167                               func (stream, "[pc], #%s%d",
3168                                     NEGATIVE_BIT_SET ? "-" : "", (int) offset);
3169                               if (! allow_unpredictable)
3170                                 is_unpredictable = TRUE;
3171                             }
3172                         }
3173                       else
3174                         {
3175                           int offset = ((given & 0xf00) >> 4) | (given & 0xf);
3176
3177                           func (stream, "[%s",
3178                                 arm_regnames[(given >> 16) & 0xf]);
3179
3180                           if (PRE_BIT_SET)
3181                             {
3182                               if (IMMEDIATE_BIT_SET)
3183                                 {
3184                                   /* Elide offset for non-writeback
3185                                      positive zero.  */
3186                                   if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
3187                                       || offset)
3188                                     func (stream, ", #%s%d",
3189                                           NEGATIVE_BIT_SET ? "-" : "", offset);
3190
3191                                   if (NEGATIVE_BIT_SET)
3192                                     offset = -offset;
3193
3194                                   value_in_comment = offset;
3195                                 }
3196                               else
3197                                 {
3198                                   /* Register Offset or Register Pre-Indexed.  */
3199                                   func (stream, ", %s%s",
3200                                         NEGATIVE_BIT_SET ? "-" : "",
3201                                         arm_regnames[given & 0xf]);
3202
3203                                   /* Writing back to the register that is the source/
3204                                      destination of the load/store is unpredictable.  */
3205                                   if (! allow_unpredictable
3206                                       && WRITEBACK_BIT_SET
3207                                       && ((given & 0xf) == ((given >> 12) & 0xf)))
3208                                     is_unpredictable = TRUE;
3209                                 }
3210
3211                               func (stream, "]%s",
3212                                     WRITEBACK_BIT_SET ? "!" : "");
3213                             }
3214                           else
3215                             {
3216                               if (IMMEDIATE_BIT_SET)
3217                                 {
3218                                   /* Immediate Post-indexed.  */
3219                                   /* PR 10924: Offset must be printed, even if it is zero.  */
3220                                   func (stream, "], #%s%d",
3221                                         NEGATIVE_BIT_SET ? "-" : "", offset);
3222                                   if (NEGATIVE_BIT_SET)
3223                                     offset = -offset;
3224                                   value_in_comment = offset;
3225                                 }
3226                               else
3227                                 {
3228                                   /* Register Post-indexed.  */
3229                                   func (stream, "], %s%s",
3230                                         NEGATIVE_BIT_SET ? "-" : "",
3231                                         arm_regnames[given & 0xf]);
3232
3233                                   /* Writing back to the register that is the source/
3234                                      destination of the load/store is unpredictable.  */
3235                                   if (! allow_unpredictable
3236                                       && (given & 0xf) == ((given >> 12) & 0xf))
3237                                     is_unpredictable = TRUE;
3238                                 }
3239
3240                               if (! allow_unpredictable)
3241                                 {
3242                                   /* Writeback is automatically implied by post- addressing.
3243                                      Setting the W bit is unnecessary and ARM specify it as
3244                                      being unpredictable.  */
3245                                   if (WRITEBACK_BIT_SET
3246                                       /* Specifying the PC register as the post-indexed
3247                                          registers is also unpredictable.  */
3248                                       || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
3249                                     is_unpredictable = TRUE;
3250                                 }
3251                             }
3252                         }
3253                       break;
3254
3255                     case 'b':
3256                       {
3257                         bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
3258                         info->print_address_func (disp * 4 + pc + 8, info);
3259                       }
3260                       break;
3261
3262                     case 'c':
3263                       if (((given >> 28) & 0xf) != 0xe)
3264                         func (stream, "%s",
3265                               arm_conditional [(given >> 28) & 0xf]);
3266                       break;
3267
3268                     case 'm':
3269                       {
3270                         int started = 0;
3271                         int reg;
3272
3273                         func (stream, "{");
3274                         for (reg = 0; reg < 16; reg++)
3275                           if ((given & (1 << reg)) != 0)
3276                             {
3277                               if (started)
3278                                 func (stream, ", ");
3279                               started = 1;
3280                               func (stream, "%s", arm_regnames[reg]);
3281                             }
3282                         func (stream, "}");
3283                         if (! started)
3284                           is_unpredictable = TRUE;
3285                       }
3286                       break;
3287
3288                     case 'q':
3289                       arm_decode_shift (given, func, stream, FALSE);
3290                       break;
3291
3292                     case 'o':
3293                       if ((given & 0x02000000) != 0)
3294                         {
3295                           unsigned int rotate = (given & 0xf00) >> 7;
3296                           unsigned int immed = (given & 0xff);
3297                           unsigned int a, i;
3298
3299                           a = (((immed << (32 - rotate))
3300                                 | (immed >> rotate)) & 0xffffffff);
3301                           /* If there is another encoding with smaller rotate,
3302                              the rotate should be specified directly.  */
3303                           for (i = 0; i < 32; i += 2)
3304                             if ((a << i | a >> (32 - i)) <= 0xff)
3305                               break;
3306
3307                           if (i != rotate)
3308                             func (stream, "#%d, %d", immed, rotate);
3309                           else
3310                             func (stream, "#%d", a);
3311                           value_in_comment = a;
3312                         }
3313                       else
3314                         arm_decode_shift (given, func, stream, TRUE);
3315                       break;
3316
3317                     case 'p':
3318                       if ((given & 0x0000f000) == 0x0000f000)
3319                         {
3320                           /* The p-variants of tst/cmp/cmn/teq are the pre-V6
3321                              mechanism for setting PSR flag bits.  They are
3322                              obsolete in V6 onwards.  */
3323                           if ((private_data->features.core & ARM_EXT_V6) == 0)
3324                             func (stream, "p");
3325                         }
3326                       break;
3327
3328                     case 't':
3329                       if ((given & 0x01200000) == 0x00200000)
3330                         func (stream, "t");
3331                       break;
3332
3333                     case 'A':
3334                       {
3335                         int offset = given & 0xff;
3336
3337                         value_in_comment = offset * 4;
3338                         if (NEGATIVE_BIT_SET)
3339                           value_in_comment = - value_in_comment;
3340
3341                         func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
3342
3343                         if (PRE_BIT_SET)
3344                           {
3345                             if (offset)
3346                               func (stream, ", #%d]%s",
3347                                     (int) value_in_comment,
3348                                     WRITEBACK_BIT_SET ? "!" : "");
3349                             else
3350                               func (stream, "]");
3351                           }
3352                         else
3353                           {
3354                             func (stream, "]");
3355
3356                             if (WRITEBACK_BIT_SET)
3357                               {
3358                                 if (offset)
3359                                   func (stream, ", #%d", (int) value_in_comment);
3360                               }
3361                             else
3362                               {
3363                                 func (stream, ", {%d}", (int) offset);
3364                                 value_in_comment = offset;
3365                               }
3366                           }
3367                       }
3368                       break;
3369
3370                     case 'B':
3371                       /* Print ARM V5 BLX(1) address: pc+25 bits.  */
3372                       {
3373                         bfd_vma address;
3374                         bfd_vma offset = 0;
3375
3376                         if (! NEGATIVE_BIT_SET)
3377                           /* Is signed, hi bits should be ones.  */
3378                           offset = (-1) ^ 0x00ffffff;
3379
3380                         /* Offset is (SignExtend(offset field)<<2).  */
3381                         offset += given & 0x00ffffff;
3382                         offset <<= 2;
3383                         address = offset + pc + 8;
3384
3385                         if (given & 0x01000000)
3386                           /* H bit allows addressing to 2-byte boundaries.  */
3387                           address += 2;
3388
3389                         info->print_address_func (address, info);
3390                       }
3391                       break;
3392
3393                     case 'C':
3394                       if ((given & 0x02000200) == 0x200)
3395                         {
3396                           const char * name;
3397                           unsigned sysm = (given & 0x004f0000) >> 16;
3398
3399                           sysm |= (given & 0x300) >> 4;
3400                           name = banked_regname (sysm);
3401
3402                           if (name != NULL)
3403                             func (stream, "%s", name);
3404                           else
3405                             func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
3406                         }
3407                       else
3408                         {
3409                           func (stream, "%cPSR_",
3410                                 (given & 0x00400000) ? 'S' : 'C');
3411                           if (given & 0x80000)
3412                             func (stream, "f");
3413                           if (given & 0x40000)
3414                             func (stream, "s");
3415                           if (given & 0x20000)
3416                             func (stream, "x");
3417                           if (given & 0x10000)
3418                             func (stream, "c");
3419                         }
3420                       break;
3421
3422                     case 'U':
3423                       if ((given & 0xf0) == 0x60)
3424                         {
3425                           switch (given & 0xf)
3426                             {
3427                             case 0xf: func (stream, "sy"); break;
3428                             default:
3429                               func (stream, "#%d", (int) given & 0xf);
3430                               break;
3431                             }
3432                         }
3433                       else
3434                         {
3435                           const char * opt = data_barrier_option (given & 0xf);
3436                           if (opt != NULL)
3437                             func (stream, "%s", opt);
3438                           else
3439                               func (stream, "#%d", (int) given & 0xf);
3440                         }
3441                       break;
3442
3443                     case '0': case '1': case '2': case '3': case '4':
3444                     case '5': case '6': case '7': case '8': case '9':
3445                       {
3446                         int width;
3447                         unsigned long value;
3448
3449                         c = arm_decode_bitfield (c, given, &value, &width);
3450
3451                         switch (*c)
3452                           {
3453                           case 'R':
3454                             if (value == 15)
3455                               is_unpredictable = TRUE;
3456                             /* Fall through.  */
3457                           case 'r':
3458                           case 'T':
3459                             /* We want register + 1 when decoding T.  */
3460                             if (*c == 'T')
3461                               ++value;
3462
3463                             if (c[1] == 'u')
3464                               {
3465                                 /* Eat the 'u' character.  */
3466                                 ++ c;
3467
3468                                 if (u_reg == value)
3469                                   is_unpredictable = TRUE;
3470                                 u_reg = value;
3471                               }
3472                             if (c[1] == 'U')
3473                               {
3474                                 /* Eat the 'U' character.  */
3475                                 ++ c;
3476
3477                                 if (U_reg == value)
3478                                   is_unpredictable = TRUE;
3479                                 U_reg = value;
3480                               }
3481                             func (stream, "%s", arm_regnames[value]);
3482                             break;
3483                           case 'd':
3484                             func (stream, "%ld", value);
3485                             value_in_comment = value;
3486                             break;
3487                           case 'b':
3488                             func (stream, "%ld", value * 8);
3489                             value_in_comment = value * 8;
3490                             break;
3491                           case 'W':
3492                             func (stream, "%ld", value + 1);
3493                             value_in_comment = value + 1;
3494                             break;
3495                           case 'x':
3496                             func (stream, "0x%08lx", value);
3497
3498                             /* Some SWI instructions have special
3499                                meanings.  */
3500                             if ((given & 0x0fffffff) == 0x0FF00000)
3501                               func (stream, "\t; IMB");
3502                             else if ((given & 0x0fffffff) == 0x0FF00001)
3503                               func (stream, "\t; IMBRange");
3504                             break;
3505                           case 'X':
3506                             func (stream, "%01lx", value & 0xf);
3507                             value_in_comment = value;
3508                             break;
3509                           case '`':
3510                             c++;
3511                             if (value == 0)
3512                               func (stream, "%c", *c);
3513                             break;
3514                           case '\'':
3515                             c++;
3516                             if (value == ((1ul << width) - 1))
3517                               func (stream, "%c", *c);
3518                             break;
3519                           case '?':
3520                             func (stream, "%c", c[(1 << width) - (int) value]);
3521                             c += 1 << width;
3522                             break;
3523                           default:
3524                             abort ();
3525                           }
3526                         break;
3527
3528                       case 'e':
3529                         {
3530                           int imm;
3531
3532                           imm = (given & 0xf) | ((given & 0xfff00) >> 4);
3533                           func (stream, "%d", imm);
3534                           value_in_comment = imm;
3535                         }
3536                         break;
3537
3538                       case 'E':
3539                         /* LSB and WIDTH fields of BFI or BFC.  The machine-
3540                            language instruction encodes LSB and MSB.  */
3541                         {
3542                           long msb = (given & 0x001f0000) >> 16;
3543                           long lsb = (given & 0x00000f80) >> 7;
3544                           long w = msb - lsb + 1;
3545
3546                           if (w > 0)
3547                             func (stream, "#%lu, #%lu", lsb, w);
3548                           else
3549                             func (stream, "(invalid: %lu:%lu)", lsb, msb);
3550                         }
3551                         break;
3552
3553                       case 'R':
3554                         /* Get the PSR/banked register name.  */
3555                         {
3556                           const char * name;
3557                           unsigned sysm = (given & 0x004f0000) >> 16;
3558
3559                           sysm |= (given & 0x300) >> 4;
3560                           name = banked_regname (sysm);
3561
3562                           if (name != NULL)
3563                             func (stream, "%s", name);
3564                           else
3565                             func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
3566                         }
3567                         break;
3568
3569                       case 'V':
3570                         /* 16-bit unsigned immediate from a MOVT or MOVW
3571                            instruction, encoded in bits 0:11 and 15:19.  */
3572                         {
3573                           long hi = (given & 0x000f0000) >> 4;
3574                           long lo = (given & 0x00000fff);
3575                           long imm16 = hi | lo;
3576
3577                           func (stream, "#%lu", imm16);
3578                           value_in_comment = imm16;
3579                         }
3580                         break;
3581
3582                       default:
3583                         abort ();
3584                       }
3585                     }
3586                 }
3587               else
3588                 func (stream, "%c", *c);
3589             }
3590
3591           if (value_in_comment > 32 || value_in_comment < -16)
3592             func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
3593
3594           if (is_unpredictable)
3595             func (stream, UNPREDICTABLE_INSTRUCTION);
3596
3597           return;
3598         }
3599     }
3600   abort ();
3601 }
3602
3603 /* Print one 16-bit Thumb instruction from PC on INFO->STREAM.  */
3604
3605 static void
3606 print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
3607 {
3608   const struct opcode16 *insn;
3609   void *stream = info->stream;
3610   fprintf_ftype func = info->fprintf_func;
3611
3612   for (insn = thumb_opcodes; insn->assembler; insn++)
3613     if ((given & insn->mask) == insn->value)
3614       {
3615         signed long value_in_comment = 0;
3616         const char *c = insn->assembler;
3617
3618         for (; *c; c++)
3619           {
3620             int domaskpc = 0;
3621             int domasklr = 0;
3622
3623             if (*c != '%')
3624               {
3625                 func (stream, "%c", *c);
3626                 continue;
3627               }
3628
3629             switch (*++c)
3630               {
3631               case '%':
3632                 func (stream, "%%");
3633                 break;
3634
3635               case 'c':
3636                 if (ifthen_state)
3637                   func (stream, "%s", arm_conditional[IFTHEN_COND]);
3638                 break;
3639
3640               case 'C':
3641                 if (ifthen_state)
3642                   func (stream, "%s", arm_conditional[IFTHEN_COND]);
3643                 else
3644                   func (stream, "s");
3645                 break;
3646
3647               case 'I':
3648                 {
3649                   unsigned int tmp;
3650
3651                   ifthen_next_state = given & 0xff;
3652                   for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
3653                     func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
3654                   func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
3655                 }
3656                 break;
3657
3658               case 'x':
3659                 if (ifthen_next_state)
3660                   func (stream, "\t; unpredictable branch in IT block\n");
3661                 break;
3662
3663               case 'X':
3664                 if (ifthen_state)
3665                   func (stream, "\t; unpredictable <IT:%s>",
3666                         arm_conditional[IFTHEN_COND]);
3667                 break;
3668
3669               case 'S':
3670                 {
3671                   long reg;
3672
3673                   reg = (given >> 3) & 0x7;
3674                   if (given & (1 << 6))
3675                     reg += 8;
3676
3677                   func (stream, "%s", arm_regnames[reg]);
3678                 }
3679                 break;
3680
3681               case 'D':
3682                 {
3683                   long reg;
3684
3685                   reg = given & 0x7;
3686                   if (given & (1 << 7))
3687                     reg += 8;
3688
3689                   func (stream, "%s", arm_regnames[reg]);
3690                 }
3691                 break;
3692
3693               case 'N':
3694                 if (given & (1 << 8))
3695                   domasklr = 1;
3696                 /* Fall through.  */
3697               case 'O':
3698                 if (*c == 'O' && (given & (1 << 8)))
3699                   domaskpc = 1;
3700                 /* Fall through.  */
3701               case 'M':
3702                 {
3703                   int started = 0;
3704                   int reg;
3705
3706                   func (stream, "{");
3707
3708                   /* It would be nice if we could spot
3709                      ranges, and generate the rS-rE format: */
3710                   for (reg = 0; (reg < 8); reg++)
3711                     if ((given & (1 << reg)) != 0)
3712                       {
3713                         if (started)
3714                           func (stream, ", ");
3715                         started = 1;
3716                         func (stream, "%s", arm_regnames[reg]);
3717                       }
3718
3719                   if (domasklr)
3720                     {
3721                       if (started)
3722                         func (stream, ", ");
3723                       started = 1;
3724                       func (stream, "%s", arm_regnames[14] /* "lr" */);
3725                     }
3726
3727                   if (domaskpc)
3728                     {
3729                       if (started)
3730                         func (stream, ", ");
3731                       func (stream, "%s", arm_regnames[15] /* "pc" */);
3732                     }
3733
3734                   func (stream, "}");
3735                 }
3736                 break;
3737
3738               case 'W':
3739                 /* Print writeback indicator for a LDMIA.  We are doing a
3740                    writeback if the base register is not in the register
3741                    mask.  */
3742                 if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
3743                   func (stream, "!");
3744                 break;
3745
3746               case 'b':
3747                 /* Print ARM V6T2 CZB address: pc+4+6 bits.  */
3748                 {
3749                   bfd_vma address = (pc + 4
3750                                      + ((given & 0x00f8) >> 2)
3751                                      + ((given & 0x0200) >> 3));
3752                   info->print_address_func (address, info);
3753                 }
3754                 break;
3755
3756               case 's':
3757                 /* Right shift immediate -- bits 6..10; 1-31 print
3758                    as themselves, 0 prints as 32.  */
3759                 {
3760                   long imm = (given & 0x07c0) >> 6;
3761                   if (imm == 0)
3762                     imm = 32;
3763                   func (stream, "#%ld", imm);
3764                 }
3765                 break;
3766
3767               case '0': case '1': case '2': case '3': case '4':
3768               case '5': case '6': case '7': case '8': case '9':
3769                 {
3770                   int bitstart = *c++ - '0';
3771                   int bitend = 0;
3772
3773                   while (*c >= '0' && *c <= '9')
3774                     bitstart = (bitstart * 10) + *c++ - '0';
3775
3776                   switch (*c)
3777                     {
3778                     case '-':
3779                       {
3780                         bfd_vma reg;
3781
3782                         c++;
3783                         while (*c >= '0' && *c <= '9')
3784                           bitend = (bitend * 10) + *c++ - '0';
3785                         if (!bitend)
3786                           abort ();
3787                         reg = given >> bitstart;
3788                         reg &= (2 << (bitend - bitstart)) - 1;
3789
3790                         switch (*c)
3791                           {
3792                           case 'r':
3793                             func (stream, "%s", arm_regnames[reg]);
3794                             break;
3795
3796                           case 'd':
3797                             func (stream, "%ld", (long) reg);
3798                             value_in_comment = reg;
3799                             break;
3800
3801                           case 'H':
3802                             func (stream, "%ld", (long) (reg << 1));
3803                             value_in_comment = reg << 1;
3804                             break;
3805
3806                           case 'W':
3807                             func (stream, "%ld", (long) (reg << 2));
3808                             value_in_comment = reg << 2;
3809                             break;
3810
3811                           case 'a':
3812                             /* PC-relative address -- the bottom two
3813                                bits of the address are dropped
3814                                before the calculation.  */
3815                             info->print_address_func
3816                               (((pc + 4) & ~3) + (reg << 2), info);
3817                             value_in_comment = 0;
3818                             break;
3819
3820                           case 'x':
3821                             func (stream, "0x%04lx", (long) reg);
3822                             break;
3823
3824                           case 'B':
3825                             reg = ((reg ^ (1 << bitend)) - (1 << bitend));
3826                             info->print_address_func (reg * 2 + pc + 4, info);
3827                             value_in_comment = 0;
3828                             break;
3829
3830                           case 'c':
3831                             func (stream, "%s", arm_conditional [reg]);
3832                             break;
3833
3834                           default:
3835                             abort ();
3836                           }
3837                       }
3838                       break;
3839
3840                     case '\'':
3841                       c++;
3842                       if ((given & (1 << bitstart)) != 0)
3843                         func (stream, "%c", *c);
3844                       break;
3845
3846                     case '?':
3847                       ++c;
3848                       if ((given & (1 << bitstart)) != 0)
3849                         func (stream, "%c", *c++);
3850                       else
3851                         func (stream, "%c", *++c);
3852                       break;
3853
3854                     default:
3855                       abort ();
3856                     }
3857                 }
3858                 break;
3859
3860               default:
3861                 abort ();
3862               }
3863           }
3864
3865         if (value_in_comment > 32 || value_in_comment < -16)
3866           func (stream, "\t; 0x%lx", value_in_comment);
3867         return;
3868       }
3869
3870   /* No match.  */
3871   abort ();
3872 }
3873
3874 /* Return the name of an V7M special register.  */
3875
3876 static const char *
3877 psr_name (int regno)
3878 {
3879   switch (regno)
3880     {
3881     case 0: return "APSR";
3882     case 1: return "IAPSR";
3883     case 2: return "EAPSR";
3884     case 3: return "PSR";
3885     case 5: return "IPSR";
3886     case 6: return "EPSR";
3887     case 7: return "IEPSR";
3888     case 8: return "MSP";
3889     case 9: return "PSP";
3890     case 16: return "PRIMASK";
3891     case 17: return "BASEPRI";
3892     case 18: return "BASEPRI_MAX";
3893     case 19: return "FAULTMASK";
3894     case 20: return "CONTROL";
3895     default: return "<unknown>";
3896     }
3897 }
3898
3899 /* Print one 32-bit Thumb instruction from PC on INFO->STREAM.  */
3900
3901 static void
3902 print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
3903 {
3904   const struct opcode32 *insn;
3905   void *stream = info->stream;
3906   fprintf_ftype func = info->fprintf_func;
3907
3908   if (print_insn_coprocessor (pc, info, given, TRUE))
3909     return;
3910
3911   if (print_insn_neon (info, given, TRUE))
3912     return;
3913
3914   for (insn = thumb32_opcodes; insn->assembler; insn++)
3915     if ((given & insn->mask) == insn->value)
3916       {
3917         bfd_boolean is_unpredictable = FALSE;
3918         signed long value_in_comment = 0;
3919         const char *c = insn->assembler;
3920
3921         for (; *c; c++)
3922           {
3923             if (*c != '%')
3924               {
3925                 func (stream, "%c", *c);
3926                 continue;
3927               }
3928
3929             switch (*++c)
3930               {
3931               case '%':
3932                 func (stream, "%%");
3933                 break;
3934
3935               case 'c':
3936                 if (ifthen_state)
3937                   func (stream, "%s", arm_conditional[IFTHEN_COND]);
3938                 break;
3939
3940               case 'x':
3941                 if (ifthen_next_state)
3942                   func (stream, "\t; unpredictable branch in IT block\n");
3943                 break;
3944
3945               case 'X':
3946                 if (ifthen_state)
3947                   func (stream, "\t; unpredictable <IT:%s>",
3948                         arm_conditional[IFTHEN_COND]);
3949                 break;
3950
3951               case 'I':
3952                 {
3953                   unsigned int imm12 = 0;
3954
3955                   imm12 |= (given & 0x000000ffu);
3956                   imm12 |= (given & 0x00007000u) >> 4;
3957                   imm12 |= (given & 0x04000000u) >> 15;
3958                   func (stream, "#%u", imm12);
3959                   value_in_comment = imm12;
3960                 }
3961                 break;
3962
3963               case 'M':
3964                 {
3965                   unsigned int bits = 0, imm, imm8, mod;
3966
3967                   bits |= (given & 0x000000ffu);
3968                   bits |= (given & 0x00007000u) >> 4;
3969                   bits |= (given & 0x04000000u) >> 15;
3970                   imm8 = (bits & 0x0ff);
3971                   mod = (bits & 0xf00) >> 8;
3972                   switch (mod)
3973                     {
3974                     case 0: imm = imm8; break;
3975                     case 1: imm = ((imm8 << 16) | imm8); break;
3976                     case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
3977                     case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
3978                     default:
3979                       mod  = (bits & 0xf80) >> 7;
3980                       imm8 = (bits & 0x07f) | 0x80;
3981                       imm  = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
3982                     }
3983                   func (stream, "#%u", imm);
3984                   value_in_comment = imm;
3985                 }
3986                 break;
3987
3988               case 'J':
3989                 {
3990                   unsigned int imm = 0;
3991
3992                   imm |= (given & 0x000000ffu);
3993                   imm |= (given & 0x00007000u) >> 4;
3994                   imm |= (given & 0x04000000u) >> 15;
3995                   imm |= (given & 0x000f0000u) >> 4;
3996                   func (stream, "#%u", imm);
3997                   value_in_comment = imm;
3998                 }
3999                 break;
4000
4001               case 'K':
4002                 {
4003                   unsigned int imm = 0;
4004
4005                   imm |= (given & 0x000f0000u) >> 16;
4006                   imm |= (given & 0x00000ff0u) >> 0;
4007                   imm |= (given & 0x0000000fu) << 12;
4008                   func (stream, "#%u", imm);
4009                   value_in_comment = imm;
4010                 }
4011                 break;
4012
4013               case 'V':
4014                 {
4015                   unsigned int imm = 0;
4016
4017                   imm |= (given & 0x00000fffu);
4018                   imm |= (given & 0x000f0000u) >> 4;
4019                   func (stream, "#%u", imm);
4020                   value_in_comment = imm;
4021                 }
4022                 break;
4023
4024               case 'S':
4025                 {
4026                   unsigned int reg = (given & 0x0000000fu);
4027                   unsigned int stp = (given & 0x00000030u) >> 4;
4028                   unsigned int imm = 0;
4029                   imm |= (given & 0x000000c0u) >> 6;
4030                   imm |= (given & 0x00007000u) >> 10;
4031
4032                   func (stream, "%s", arm_regnames[reg]);
4033                   switch (stp)
4034                     {
4035                     case 0:
4036                       if (imm > 0)
4037                         func (stream, ", lsl #%u", imm);
4038                       break;
4039
4040                     case 1:
4041                       if (imm == 0)
4042                         imm = 32;
4043                       func (stream, ", lsr #%u", imm);
4044                       break;
4045
4046                     case 2:
4047                       if (imm == 0)
4048                         imm = 32;
4049                       func (stream, ", asr #%u", imm);
4050                       break;
4051
4052                     case 3:
4053                       if (imm == 0)
4054                         func (stream, ", rrx");
4055                       else
4056                         func (stream, ", ror #%u", imm);
4057                     }
4058                 }
4059                 break;
4060
4061               case 'a':
4062                 {
4063                   unsigned int Rn  = (given & 0x000f0000) >> 16;
4064                   unsigned int U   = ! NEGATIVE_BIT_SET;
4065                   unsigned int op  = (given & 0x00000f00) >> 8;
4066                   unsigned int i12 = (given & 0x00000fff);
4067                   unsigned int i8  = (given & 0x000000ff);
4068                   bfd_boolean writeback = FALSE, postind = FALSE;
4069                   bfd_vma offset = 0;
4070
4071                   func (stream, "[%s", arm_regnames[Rn]);
4072                   if (U) /* 12-bit positive immediate offset.  */
4073                     {
4074                       offset = i12;
4075                       if (Rn != 15)
4076                         value_in_comment = offset;
4077                     }
4078                   else if (Rn == 15) /* 12-bit negative immediate offset.  */
4079                     offset = - (int) i12;
4080                   else if (op == 0x0) /* Shifted register offset.  */
4081                     {
4082                       unsigned int Rm = (i8 & 0x0f);
4083                       unsigned int sh = (i8 & 0x30) >> 4;
4084
4085                       func (stream, ", %s", arm_regnames[Rm]);
4086                       if (sh)
4087                         func (stream, ", lsl #%u", sh);
4088                       func (stream, "]");
4089                       break;
4090                     }
4091                   else switch (op)
4092                     {
4093                     case 0xE:  /* 8-bit positive immediate offset.  */
4094                       offset = i8;
4095                       break;
4096
4097                     case 0xC:  /* 8-bit negative immediate offset.  */
4098                       offset = -i8;
4099                       break;
4100
4101                     case 0xF:  /* 8-bit + preindex with wb.  */
4102                       offset = i8;
4103                       writeback = TRUE;
4104                       break;
4105
4106                     case 0xD:  /* 8-bit - preindex with wb.  */
4107                       offset = -i8;
4108                       writeback = TRUE;
4109                       break;
4110
4111                     case 0xB:  /* 8-bit + postindex.  */
4112                       offset = i8;
4113                       postind = TRUE;
4114                       break;
4115
4116                     case 0x9:  /* 8-bit - postindex.  */
4117                       offset = -i8;
4118                       postind = TRUE;
4119                       break;
4120
4121                     default:
4122                       func (stream, ", <undefined>]");
4123                       goto skip;
4124                     }
4125
4126                   if (postind)
4127                     func (stream, "], #%d", (int) offset);
4128                   else
4129                     {
4130                       if (offset)
4131                         func (stream, ", #%d", (int) offset);
4132                       func (stream, writeback ? "]!" : "]");
4133                     }
4134
4135                   if (Rn == 15)
4136                     {
4137                       func (stream, "\t; ");
4138                       info->print_address_func (((pc + 4) & ~3) + offset, info);
4139                     }
4140                 }
4141               skip:
4142                 break;
4143
4144               case 'A':
4145                 {
4146                   unsigned int U   = ! NEGATIVE_BIT_SET;
4147                   unsigned int W   = WRITEBACK_BIT_SET;
4148                   unsigned int Rn  = (given & 0x000f0000) >> 16;
4149                   unsigned int off = (given & 0x000000ff);
4150
4151                   func (stream, "[%s", arm_regnames[Rn]);
4152
4153                   if (PRE_BIT_SET)
4154                     {
4155                       if (off || !U)
4156                         {
4157                           func (stream, ", #%c%u", U ? '+' : '-', off * 4);
4158                           value_in_comment = off * 4 * U ? 1 : -1;
4159                         }
4160                       func (stream, "]");
4161                       if (W)
4162                         func (stream, "!");
4163                     }
4164                   else
4165                     {
4166                       func (stream, "], ");
4167                       if (W)
4168                         {
4169                           func (stream, "#%c%u", U ? '+' : '-', off * 4);
4170                           value_in_comment = off * 4 * U ? 1 : -1;
4171                         }
4172                       else
4173                         {
4174                           func (stream, "{%u}", off);
4175                           value_in_comment = off;
4176                         }
4177                     }
4178                 }
4179                 break;
4180
4181               case 'w':
4182                 {
4183                   unsigned int Sbit = (given & 0x01000000) >> 24;
4184                   unsigned int type = (given & 0x00600000) >> 21;
4185
4186                   switch (type)
4187                     {
4188                     case 0: func (stream, Sbit ? "sb" : "b"); break;
4189                     case 1: func (stream, Sbit ? "sh" : "h"); break;
4190                     case 2:
4191                       if (Sbit)
4192                         func (stream, "??");
4193                       break;
4194                     case 3:
4195                       func (stream, "??");
4196                       break;
4197                     }
4198                 }
4199                 break;
4200
4201               case 'm':
4202                 {
4203                   int started = 0;
4204                   int reg;
4205
4206                   func (stream, "{");
4207                   for (reg = 0; reg < 16; reg++)
4208                     if ((given & (1 << reg)) != 0)
4209                       {
4210                         if (started)
4211                           func (stream, ", ");
4212                         started = 1;
4213                         func (stream, "%s", arm_regnames[reg]);
4214                       }
4215                   func (stream, "}");
4216                 }
4217                 break;
4218
4219               case 'E':
4220                 {
4221                   unsigned int msb = (given & 0x0000001f);
4222                   unsigned int lsb = 0;
4223
4224                   lsb |= (given & 0x000000c0u) >> 6;
4225                   lsb |= (given & 0x00007000u) >> 10;
4226                   func (stream, "#%u, #%u", lsb, msb - lsb + 1);
4227                 }
4228                 break;
4229
4230               case 'F':
4231                 {
4232                   unsigned int width = (given & 0x0000001f) + 1;
4233                   unsigned int lsb = 0;
4234
4235                   lsb |= (given & 0x000000c0u) >> 6;
4236                   lsb |= (given & 0x00007000u) >> 10;
4237                   func (stream, "#%u, #%u", lsb, width);
4238                 }
4239                 break;
4240
4241               case 'b':
4242                 {
4243                   unsigned int S = (given & 0x04000000u) >> 26;
4244                   unsigned int J1 = (given & 0x00002000u) >> 13;
4245                   unsigned int J2 = (given & 0x00000800u) >> 11;
4246                   bfd_vma offset = 0;
4247
4248                   offset |= !S << 20;
4249                   offset |= J2 << 19;
4250                   offset |= J1 << 18;
4251                   offset |= (given & 0x003f0000) >> 4;
4252                   offset |= (given & 0x000007ff) << 1;
4253                   offset -= (1 << 20);
4254
4255                   info->print_address_func (pc + 4 + offset, info);
4256                 }
4257                 break;
4258
4259               case 'B':
4260                 {
4261                   unsigned int S = (given & 0x04000000u) >> 26;
4262                   unsigned int I1 = (given & 0x00002000u) >> 13;
4263                   unsigned int I2 = (given & 0x00000800u) >> 11;
4264                   bfd_vma offset = 0;
4265
4266                   offset |= !S << 24;
4267                   offset |= !(I1 ^ S) << 23;
4268                   offset |= !(I2 ^ S) << 22;
4269                   offset |= (given & 0x03ff0000u) >> 4;
4270                   offset |= (given & 0x000007ffu) << 1;
4271                   offset -= (1 << 24);
4272                   offset += pc + 4;
4273
4274                   /* BLX target addresses are always word aligned.  */
4275                   if ((given & 0x00001000u) == 0)
4276                       offset &= ~2u;
4277
4278                   info->print_address_func (offset, info);
4279                 }
4280                 break;
4281
4282               case 's':
4283                 {
4284                   unsigned int shift = 0;
4285
4286                   shift |= (given & 0x000000c0u) >> 6;
4287                   shift |= (given & 0x00007000u) >> 10;
4288                   if (WRITEBACK_BIT_SET)
4289                     func (stream, ", asr #%u", shift);
4290                   else if (shift)
4291                     func (stream, ", lsl #%u", shift);
4292                   /* else print nothing - lsl #0 */
4293                 }
4294                 break;
4295
4296               case 'R':
4297                 {
4298                   unsigned int rot = (given & 0x00000030) >> 4;
4299
4300                   if (rot)
4301                     func (stream, ", ror #%u", rot * 8);
4302                 }
4303                 break;
4304
4305               case 'U':
4306                 if ((given & 0xf0) == 0x60)
4307                   {
4308                     switch (given & 0xf)
4309                       {
4310                         case 0xf: func (stream, "sy"); break;
4311                         default:
4312                           func (stream, "#%d", (int) given & 0xf);
4313                               break;
4314                       }
4315                   }
4316                 else
4317                   {
4318                     const char * opt = data_barrier_option (given & 0xf);
4319                     if (opt != NULL)
4320                       func (stream, "%s", opt);
4321                     else
4322                       func (stream, "#%d", (int) given & 0xf);
4323                    }
4324                 break;
4325
4326               case 'C':
4327                 if ((given & 0xff) == 0)
4328                   {
4329                     func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
4330                     if (given & 0x800)
4331                       func (stream, "f");
4332                     if (given & 0x400)
4333                       func (stream, "s");
4334                     if (given & 0x200)
4335                       func (stream, "x");
4336                     if (given & 0x100)
4337                       func (stream, "c");
4338                   }
4339                 else if ((given & 0x20) == 0x20)
4340                   {
4341                     char const* name;
4342                     unsigned sysm = (given & 0xf00) >> 8;
4343
4344                     sysm |= (given & 0x30);
4345                     sysm |= (given & 0x00100000) >> 14;
4346                     name = banked_regname (sysm);
4347
4348                     if (name != NULL)
4349                       func (stream, "%s", name);
4350                     else
4351                       func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
4352                   }
4353                 else
4354                   {
4355                     func (stream, "%s", psr_name (given & 0xff));
4356                   }
4357                 break;
4358
4359               case 'D':
4360                 if (((given & 0xff) == 0)
4361                     || ((given & 0x20) == 0x20))
4362                   {
4363                     char const* name;
4364                     unsigned sm = (given & 0xf0000) >> 16;
4365
4366                     sm |= (given & 0x30);
4367                     sm |= (given & 0x00100000) >> 14;
4368                     name = banked_regname (sm);
4369
4370                     if (name != NULL)
4371                       func (stream, "%s", name);
4372                     else
4373                       func (stream, "(UNDEF: %lu)", (unsigned long) sm);
4374                   }
4375                 else
4376                   func (stream, "%s", psr_name (given & 0xff));
4377                 break;
4378
4379               case '0': case '1': case '2': case '3': case '4':
4380               case '5': case '6': case '7': case '8': case '9':
4381                 {
4382                   int width;
4383                   unsigned long val;
4384
4385                   c = arm_decode_bitfield (c, given, &val, &width);
4386
4387                   switch (*c)
4388                     {
4389                     case 'd':
4390                       func (stream, "%lu", val);
4391                       value_in_comment = val;
4392                       break;
4393
4394                     case 'W':
4395                       func (stream, "%lu", val * 4);
4396                       value_in_comment = val * 4;
4397                       break;
4398
4399                     case 'R':
4400                       if (val == 15)
4401                         is_unpredictable = TRUE;
4402                       /* Fall through.  */
4403                     case 'r':
4404                       func (stream, "%s", arm_regnames[val]);
4405                       break;
4406
4407                     case 'c':
4408                       func (stream, "%s", arm_conditional[val]);
4409                       break;
4410
4411                     case '\'':
4412                       c++;
4413                       if (val == ((1ul << width) - 1))
4414                         func (stream, "%c", *c);
4415                       break;
4416
4417                     case '`':
4418                       c++;
4419                       if (val == 0)
4420                         func (stream, "%c", *c);
4421                       break;
4422
4423                     case '?':
4424                       func (stream, "%c", c[(1 << width) - (int) val]);
4425                       c += 1 << width;
4426                       break;
4427
4428                     case 'x':
4429                       func (stream, "0x%lx", val & 0xffffffffUL);
4430                       break;
4431
4432                     default:
4433                       abort ();
4434                     }
4435                 }
4436                 break;
4437
4438               case 'L':
4439                 /* PR binutils/12534
4440                    If we have a PC relative offset in an LDRD or STRD
4441                    instructions then display the decoded address.  */
4442                 if (((given >> 16) & 0xf) == 0xf)
4443                   {
4444                     bfd_vma offset = (given & 0xff) * 4;
4445
4446                     if ((given & (1 << 23)) == 0)
4447                       offset = - offset;
4448                     func (stream, "\t; ");
4449                     info->print_address_func ((pc & ~3) + 4 + offset, info);
4450                   }
4451                 break;
4452
4453               default:
4454                 abort ();
4455               }
4456           }
4457
4458         if (value_in_comment > 32 || value_in_comment < -16)
4459           func (stream, "\t; 0x%lx", value_in_comment);
4460
4461         if (is_unpredictable)
4462           func (stream, UNPREDICTABLE_INSTRUCTION);
4463
4464         return;
4465       }
4466
4467   /* No match.  */
4468   abort ();
4469 }
4470
4471 /* Print data bytes on INFO->STREAM.  */
4472
4473 static void
4474 print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
4475                  struct disassemble_info *info,
4476                  long given)
4477 {
4478   switch (info->bytes_per_chunk)
4479     {
4480     case 1:
4481       info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
4482       break;
4483     case 2:
4484       info->fprintf_func (info->stream, ".short\t0x%04lx", given);
4485       break;
4486     case 4:
4487       info->fprintf_func (info->stream, ".word\t0x%08lx", given);
4488       break;
4489     default:
4490       abort ();
4491     }
4492 }
4493
4494 /* Disallow mapping symbols ($a, $b, $d, $t etc) from
4495    being displayed in symbol relative addresses.  */
4496
4497 bfd_boolean
4498 arm_symbol_is_valid (asymbol * sym,
4499                      struct disassemble_info * info ATTRIBUTE_UNUSED)
4500 {
4501   const char * name;
4502
4503   if (sym == NULL)
4504     return FALSE;
4505
4506   name = bfd_asymbol_name (sym);
4507
4508   return (name && *name != '$');
4509 }
4510
4511 /* Parse an individual disassembler option.  */
4512
4513 void
4514 parse_arm_disassembler_option (char *option)
4515 {
4516   if (option == NULL)
4517     return;
4518
4519   if (CONST_STRNEQ (option, "reg-names-"))
4520     {
4521       int i;
4522
4523       option += 10;
4524
4525       for (i = NUM_ARM_REGNAMES; i--;)
4526         if (strneq (option, regnames[i].name, strlen (regnames[i].name)))
4527           {
4528             regname_selected = i;
4529             break;
4530           }
4531
4532       if (i < 0)
4533         /* XXX - should break 'option' at following delimiter.  */
4534         fprintf (stderr, _("Unrecognised register name set: %s\n"), option);
4535     }
4536   else if (CONST_STRNEQ (option, "force-thumb"))
4537     force_thumb = 1;
4538   else if (CONST_STRNEQ (option, "no-force-thumb"))
4539     force_thumb = 0;
4540   else
4541     /* XXX - should break 'option' at following delimiter.  */
4542     fprintf (stderr, _("Unrecognised disassembler option: %s\n"), option);
4543
4544   return;
4545 }
4546
4547 /* Parse the string of disassembler options, spliting it at whitespaces
4548    or commas.  (Whitespace separators supported for backwards compatibility).  */
4549
4550 static void
4551 parse_disassembler_options (char *options)
4552 {
4553   if (options == NULL)
4554     return;
4555
4556   while (*options)
4557     {
4558       parse_arm_disassembler_option (options);
4559
4560       /* Skip forward to next seperator.  */
4561       while ((*options) && (! ISSPACE (*options)) && (*options != ','))
4562         ++ options;
4563       /* Skip forward past seperators.  */
4564       while (ISSPACE (*options) || (*options == ','))
4565         ++ options;
4566     }
4567 }
4568
4569 /* Search back through the insn stream to determine if this instruction is
4570    conditionally executed.  */
4571
4572 static void
4573 find_ifthen_state (bfd_vma pc,
4574                    struct disassemble_info *info,
4575                    bfd_boolean little)
4576 {
4577   unsigned char b[2];
4578   unsigned int insn;
4579   int status;
4580   /* COUNT is twice the number of instructions seen.  It will be odd if we
4581      just crossed an instruction boundary.  */
4582   int count;
4583   int it_count;
4584   unsigned int seen_it;
4585   bfd_vma addr;
4586
4587   ifthen_address = pc;
4588   ifthen_state = 0;
4589
4590   addr = pc;
4591   count = 1;
4592   it_count = 0;
4593   seen_it = 0;
4594   /* Scan backwards looking for IT instructions, keeping track of where
4595      instruction boundaries are.  We don't know if something is actually an
4596      IT instruction until we find a definite instruction boundary.  */
4597   for (;;)
4598     {
4599       if (addr == 0 || info->symbol_at_address_func (addr, info))
4600         {
4601           /* A symbol must be on an instruction boundary, and will not
4602              be within an IT block.  */
4603           if (seen_it && (count & 1))
4604             break;
4605
4606           return;
4607         }
4608       addr -= 2;
4609       status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
4610       if (status)
4611         return;
4612
4613       if (little)
4614         insn = (b[0]) | (b[1] << 8);
4615       else
4616         insn = (b[1]) | (b[0] << 8);
4617       if (seen_it)
4618         {
4619           if ((insn & 0xf800) < 0xe800)
4620             {
4621               /* Addr + 2 is an instruction boundary.  See if this matches
4622                  the expected boundary based on the position of the last
4623                  IT candidate.  */
4624               if (count & 1)
4625                 break;
4626               seen_it = 0;
4627             }
4628         }
4629       if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
4630         {
4631           /* This could be an IT instruction.  */
4632           seen_it = insn;
4633           it_count = count >> 1;
4634         }
4635       if ((insn & 0xf800) >= 0xe800)
4636         count++;
4637       else
4638         count = (count + 2) | 1;
4639       /* IT blocks contain at most 4 instructions.  */
4640       if (count >= 8 && !seen_it)
4641         return;
4642     }
4643   /* We found an IT instruction.  */
4644   ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
4645   if ((ifthen_state & 0xf) == 0)
4646     ifthen_state = 0;
4647 }
4648
4649 /* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
4650    mapping symbol.  */
4651
4652 static int
4653 is_mapping_symbol (struct disassemble_info *info, int n,
4654                    enum map_type *map_type)
4655 {
4656   const char *name;
4657
4658   name = bfd_asymbol_name (info->symtab[n]);
4659   if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
4660       && (name[2] == 0 || name[2] == '.'))
4661     {
4662       *map_type = ((name[1] == 'a') ? MAP_ARM
4663                    : (name[1] == 't') ? MAP_THUMB
4664                    : MAP_DATA);
4665       return TRUE;
4666     }
4667
4668   return FALSE;
4669 }
4670
4671 /* Try to infer the code type (ARM or Thumb) from a mapping symbol.
4672    Returns nonzero if *MAP_TYPE was set.  */
4673
4674 static int
4675 get_map_sym_type (struct disassemble_info *info,
4676                   int n,
4677                   enum map_type *map_type)
4678 {
4679   /* If the symbol is in a different section, ignore it.  */
4680   if (info->section != NULL && info->section != info->symtab[n]->section)
4681     return FALSE;
4682
4683   return is_mapping_symbol (info, n, map_type);
4684 }
4685
4686 /* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
4687    Returns nonzero if *MAP_TYPE was set.  */
4688
4689 static int
4690 get_sym_code_type (struct disassemble_info *info,
4691                    int n,
4692                    enum map_type *map_type)
4693 {
4694   elf_symbol_type *es;
4695   unsigned int type;
4696
4697   /* If the symbol is in a different section, ignore it.  */
4698   if (info->section != NULL && info->section != info->symtab[n]->section)
4699     return FALSE;
4700
4701   es = *(elf_symbol_type **)(info->symtab + n);
4702   type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
4703
4704   /* If the symbol has function type then use that.  */
4705   if (type == STT_FUNC || type == STT_GNU_IFUNC)
4706     {
4707       if (ARM_SYM_BRANCH_TYPE (&es->internal_elf_sym) == ST_BRANCH_TO_THUMB)
4708         *map_type = MAP_THUMB;
4709       else
4710         *map_type = MAP_ARM;
4711       return TRUE;
4712     }
4713
4714   return FALSE;
4715 }
4716
4717 /* Given a bfd_mach_arm_XXX value, this function fills in the fields
4718    of the supplied arm_feature_set structure with bitmasks indicating
4719    the support base architectures and coprocessor extensions.
4720
4721    FIXME: This could more efficiently implemented as a constant array,
4722    although it would also be less robust.  */
4723
4724 static void
4725 select_arm_features (unsigned long mach,
4726                      arm_feature_set * features)
4727 {
4728 #undef  ARM_FEATURE
4729 #define ARM_FEATURE(ARCH,CEXT) \
4730   features->core = (ARCH); \
4731   features->coproc = (CEXT) | FPU_FPA; \
4732   return
4733
4734   switch (mach)
4735     {
4736     case bfd_mach_arm_2:       ARM_ARCH_V2;
4737     case bfd_mach_arm_2a:      ARM_ARCH_V2S;
4738     case bfd_mach_arm_3:       ARM_ARCH_V3;
4739     case bfd_mach_arm_3M:      ARM_ARCH_V3M;
4740     case bfd_mach_arm_4:       ARM_ARCH_V4;
4741     case bfd_mach_arm_4T:      ARM_ARCH_V4T;
4742     case bfd_mach_arm_5:       ARM_ARCH_V5;
4743     case bfd_mach_arm_5T:      ARM_ARCH_V5T;
4744     case bfd_mach_arm_5TE:     ARM_ARCH_V5TE;
4745     case bfd_mach_arm_XScale:  ARM_ARCH_XSCALE;
4746     case bfd_mach_arm_ep9312:  ARM_FEATURE (ARM_AEXT_V4T, ARM_CEXT_MAVERICK | FPU_MAVERICK);
4747     case bfd_mach_arm_iWMMXt:  ARM_ARCH_IWMMXT;
4748     case bfd_mach_arm_iWMMXt2: ARM_ARCH_IWMMXT2;
4749       /* If the machine type is unknown allow all
4750          architecture types and all extensions.  */
4751     case bfd_mach_arm_unknown: ARM_FEATURE (-1UL, -1UL);
4752     default:
4753       abort ();
4754     }
4755 }
4756
4757
4758 /* NOTE: There are no checks in these routines that
4759    the relevant number of data bytes exist.  */
4760
4761 static int
4762 print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
4763 {
4764   unsigned char b[4];
4765   long          given;
4766   int           status;
4767   int           is_thumb = FALSE;
4768   int           is_data = FALSE;
4769   int           little_code;
4770   unsigned int  size = 4;
4771   void          (*printer) (bfd_vma, struct disassemble_info *, long);
4772   bfd_boolean   found = FALSE;
4773   struct arm_private_data *private_data;
4774
4775   if (info->disassembler_options)
4776     {
4777       parse_disassembler_options (info->disassembler_options);
4778
4779       /* To avoid repeated parsing of these options, we remove them here.  */
4780       info->disassembler_options = NULL;
4781     }
4782
4783   /* PR 10288: Control which instructions will be disassembled.  */
4784   if (info->private_data == NULL)
4785     {
4786       static struct arm_private_data private;
4787
4788       if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
4789         /* If the user did not use the -m command line switch then default to
4790            disassembling all types of ARM instruction.
4791
4792            The info->mach value has to be ignored as this will be based on
4793            the default archictecture for the target and/or hints in the notes
4794            section, but it will never be greater than the current largest arm
4795            machine value (iWMMXt2), which is only equivalent to the V5TE
4796            architecture.  ARM architectures have advanced beyond the machine
4797            value encoding, and these newer architectures would be ignored if
4798            the machine value was used.
4799
4800            Ie the -m switch is used to restrict which instructions will be
4801            disassembled.  If it is necessary to use the -m switch to tell
4802            objdump that an ARM binary is being disassembled, eg because the
4803            input is a raw binary file, but it is also desired to disassemble
4804            all ARM instructions then use "-marm".  This will select the
4805            "unknown" arm architecture which is compatible with any ARM
4806            instruction.  */
4807           info->mach = bfd_mach_arm_unknown;
4808
4809       /* Compute the architecture bitmask from the machine number.
4810          Note: This assumes that the machine number will not change
4811          during disassembly....  */
4812       select_arm_features (info->mach, & private.features);
4813
4814       private.has_mapping_symbols = -1;
4815       private.last_mapping_sym = -1;
4816       private.last_mapping_addr = 0;
4817
4818       info->private_data = & private;
4819     }
4820
4821   private_data = info->private_data;
4822
4823   /* Decide if our code is going to be little-endian, despite what the
4824      function argument might say.  */
4825   little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
4826
4827   /* For ELF, consult the symbol table to determine what kind of code
4828      or data we have.  */
4829   if (info->symtab_size != 0
4830       && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
4831     {
4832       bfd_vma addr;
4833       int n, start;
4834       int last_sym = -1;
4835       enum map_type type = MAP_ARM;
4836
4837       /* Start scanning at the start of the function, or wherever
4838          we finished last time.  */
4839       /* PR 14006.  When the address is 0 we are either at the start of the
4840          very first function, or else the first function in a new, unlinked
4841          executable section (eg because uf -ffunction-sections).  Either way
4842          start scanning from the beginning of the symbol table, not where we
4843          left off last time.  */
4844       if (pc == 0)
4845         start = 0;
4846       else
4847         {
4848           start = info->symtab_pos + 1;
4849           if (start < private_data->last_mapping_sym)
4850             start = private_data->last_mapping_sym;
4851         }
4852       found = FALSE;
4853
4854       /* First, look for mapping symbols.  */
4855       if (private_data->has_mapping_symbols != 0)
4856         {
4857           /* Scan up to the location being disassembled.  */
4858           for (n = start; n < info->symtab_size; n++)
4859             {
4860               addr = bfd_asymbol_value (info->symtab[n]);
4861               if (addr > pc)
4862                 break;
4863               if (get_map_sym_type (info, n, &type))
4864                 {
4865                   last_sym = n;
4866                   found = TRUE;
4867                 }
4868             }
4869
4870           if (!found)
4871             {
4872               /* No mapping symbol found at this address.  Look backwards
4873                  for a preceding one.  */
4874               for (n = start - 1; n >= 0; n--)
4875                 {
4876                   if (get_map_sym_type (info, n, &type))
4877                     {
4878                       last_sym = n;
4879                       found = TRUE;
4880                       break;
4881                     }
4882                 }
4883             }
4884
4885           if (found)
4886             private_data->has_mapping_symbols = 1;
4887
4888           /* No mapping symbols were found.  A leading $d may be
4889              omitted for sections which start with data; but for
4890              compatibility with legacy and stripped binaries, only
4891              assume the leading $d if there is at least one mapping
4892              symbol in the file.  */
4893           if (!found && private_data->has_mapping_symbols == -1)
4894             {
4895               /* Look for mapping symbols, in any section.  */
4896               for (n = 0; n < info->symtab_size; n++)
4897                 if (is_mapping_symbol (info, n, &type))
4898                   {
4899                     private_data->has_mapping_symbols = 1;
4900                     break;
4901                   }
4902               if (private_data->has_mapping_symbols == -1)
4903                 private_data->has_mapping_symbols = 0;
4904             }
4905
4906           if (!found && private_data->has_mapping_symbols == 1)
4907             {
4908               type = MAP_DATA;
4909               found = TRUE;
4910             }
4911         }
4912
4913       /* Next search for function symbols to separate ARM from Thumb
4914          in binaries without mapping symbols.  */
4915       if (!found)
4916         {
4917           /* Scan up to the location being disassembled.  */
4918           for (n = start; n < info->symtab_size; n++)
4919             {
4920               addr = bfd_asymbol_value (info->symtab[n]);
4921               if (addr > pc)
4922                 break;
4923               if (get_sym_code_type (info, n, &type))
4924                 {
4925                   last_sym = n;
4926                   found = TRUE;
4927                 }
4928             }
4929
4930           if (!found)
4931             {
4932               /* No mapping symbol found at this address.  Look backwards
4933                  for a preceding one.  */
4934               for (n = start - 1; n >= 0; n--)
4935                 {
4936                   if (get_sym_code_type (info, n, &type))
4937                     {
4938                       last_sym = n;
4939                       found = TRUE;
4940                       break;
4941                     }
4942                 }
4943             }
4944         }
4945
4946       private_data->last_mapping_sym = last_sym;
4947       private_data->last_type = type;
4948       is_thumb = (private_data->last_type == MAP_THUMB);
4949       is_data = (private_data->last_type == MAP_DATA);
4950
4951       /* Look a little bit ahead to see if we should print out
4952          two or four bytes of data.  If there's a symbol,
4953          mapping or otherwise, after two bytes then don't
4954          print more.  */
4955       if (is_data)
4956         {
4957           size = 4 - (pc & 3);
4958           for (n = last_sym + 1; n < info->symtab_size; n++)
4959             {
4960               addr = bfd_asymbol_value (info->symtab[n]);
4961               if (addr > pc
4962                   && (info->section == NULL
4963                       || info->section == info->symtab[n]->section))
4964                 {
4965                   if (addr - pc < size)
4966                     size = addr - pc;
4967                   break;
4968                 }
4969             }
4970           /* If the next symbol is after three bytes, we need to
4971              print only part of the data, so that we can use either
4972              .byte or .short.  */
4973           if (size == 3)
4974             size = (pc & 1) ? 1 : 2;
4975         }
4976     }
4977
4978   if (info->symbols != NULL)
4979     {
4980       if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
4981         {
4982           coff_symbol_type * cs;
4983
4984           cs = coffsymbol (*info->symbols);
4985           is_thumb = (   cs->native->u.syment.n_sclass == C_THUMBEXT
4986                       || cs->native->u.syment.n_sclass == C_THUMBSTAT
4987                       || cs->native->u.syment.n_sclass == C_THUMBLABEL
4988                       || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
4989                       || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
4990         }
4991       else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
4992                && !found)
4993         {
4994           /* If no mapping symbol has been found then fall back to the type
4995              of the function symbol.  */
4996           elf_symbol_type *  es;
4997           unsigned int       type;
4998
4999           es = *(elf_symbol_type **)(info->symbols);
5000           type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
5001
5002           is_thumb = ((ARM_SYM_BRANCH_TYPE (&es->internal_elf_sym)
5003                        == ST_BRANCH_TO_THUMB)
5004                       || type == STT_ARM_16BIT);
5005         }
5006     }
5007
5008   if (force_thumb)
5009     is_thumb = TRUE;
5010
5011   if (is_data)
5012     info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
5013   else
5014     info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
5015
5016   info->bytes_per_line = 4;
5017
5018   /* PR 10263: Disassemble data if requested to do so by the user.  */
5019   if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
5020     {
5021       int i;
5022
5023       /* Size was already set above.  */
5024       info->bytes_per_chunk = size;
5025       printer = print_insn_data;
5026
5027       status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
5028       given = 0;
5029       if (little)
5030         for (i = size - 1; i >= 0; i--)
5031           given = b[i] | (given << 8);
5032       else
5033         for (i = 0; i < (int) size; i++)
5034           given = b[i] | (given << 8);
5035     }
5036   else if (!is_thumb)
5037     {
5038       /* In ARM mode endianness is a straightforward issue: the instruction
5039          is four bytes long and is either ordered 0123 or 3210.  */
5040       printer = print_insn_arm;
5041       info->bytes_per_chunk = 4;
5042       size = 4;
5043
5044       status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
5045       if (little_code)
5046         given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
5047       else
5048         given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24);
5049     }
5050   else
5051     {
5052       /* In Thumb mode we have the additional wrinkle of two
5053          instruction lengths.  Fortunately, the bits that determine
5054          the length of the current instruction are always to be found
5055          in the first two bytes.  */
5056       printer = print_insn_thumb16;
5057       info->bytes_per_chunk = 2;
5058       size = 2;
5059
5060       status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
5061       if (little_code)
5062         given = (b[0]) | (b[1] << 8);
5063       else
5064         given = (b[1]) | (b[0] << 8);
5065
5066       if (!status)
5067         {
5068           /* These bit patterns signal a four-byte Thumb
5069              instruction.  */
5070           if ((given & 0xF800) == 0xF800
5071               || (given & 0xF800) == 0xF000
5072               || (given & 0xF800) == 0xE800)
5073             {
5074               status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
5075               if (little_code)
5076                 given = (b[0]) | (b[1] << 8) | (given << 16);
5077               else
5078                 given = (b[1]) | (b[0] << 8) | (given << 16);
5079
5080               printer = print_insn_thumb32;
5081               size = 4;
5082             }
5083         }
5084
5085       if (ifthen_address != pc)
5086         find_ifthen_state (pc, info, little_code);
5087
5088       if (ifthen_state)
5089         {
5090           if ((ifthen_state & 0xf) == 0x8)
5091             ifthen_next_state = 0;
5092           else
5093             ifthen_next_state = (ifthen_state & 0xe0)
5094                                 | ((ifthen_state & 0xf) << 1);
5095         }
5096     }
5097
5098   if (status)
5099     {
5100       info->memory_error_func (status, pc, info);
5101       return -1;
5102     }
5103   if (info->flags & INSN_HAS_RELOC)
5104     /* If the instruction has a reloc associated with it, then
5105        the offset field in the instruction will actually be the
5106        addend for the reloc.  (We are using REL type relocs).
5107        In such cases, we can ignore the pc when computing
5108        addresses, since the addend is not currently pc-relative.  */
5109     pc = 0;
5110
5111   printer (pc, info, given);
5112
5113   if (is_thumb)
5114     {
5115       ifthen_state = ifthen_next_state;
5116       ifthen_address += size;
5117     }
5118   return size;
5119 }
5120
5121 int
5122 print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
5123 {
5124   /* Detect BE8-ness and record it in the disassembler info.  */
5125   if (info->flavour == bfd_target_elf_flavour
5126       && info->section != NULL
5127       && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
5128     info->endian_code = BFD_ENDIAN_LITTLE;
5129
5130   return print_insn (pc, info, FALSE);
5131 }
5132
5133 int
5134 print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
5135 {
5136   return print_insn (pc, info, TRUE);
5137 }
5138
5139 void
5140 print_arm_disassembler_options (FILE *stream)
5141 {
5142   int i;
5143
5144   fprintf (stream, _("\n\
5145 The following ARM specific disassembler options are supported for use with\n\
5146 the -M switch:\n"));
5147
5148   for (i = NUM_ARM_REGNAMES; i--;)
5149     fprintf (stream, "  reg-names-%s %*c%s\n",
5150              regnames[i].name,
5151              (int)(14 - strlen (regnames[i].name)), ' ',
5152              regnames[i].description);
5153
5154   fprintf (stream, "  force-thumb              Assume all insns are Thumb insns\n");
5155   fprintf (stream, "  no-force-thumb           Examine preceding label to determine an insn's type\n\n");
5156 }