1 /* Instruction printing code for the ARM
2 Copyright (C) 1994-2022 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
6 This file is part of libopcodes.
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
26 #include "disassemble.h"
27 #include "opcode/arm.h"
29 #include "safe-ctype.h"
30 #include "libiberty.h"
31 #include "floatformat.h"
33 /* FIXME: This shouldn't be done here. */
34 #include "coff/internal.h"
38 #include "elf/internal.h"
42 /* Cached mapping symbol state. */
50 struct arm_private_data
52 /* The features to use when disassembling optional instructions. */
53 arm_feature_set features
;
55 /* Track the last type (although this doesn't seem to be useful) */
56 enum map_type last_type
;
58 /* Tracking symbol table information */
61 /* The end range of the current range being disassembled. */
62 bfd_vma last_stop_offset
;
63 bfd_vma last_mapping_addr
;
116 MVE_VSTRB_SCATTER_T1
,
117 MVE_VSTRH_SCATTER_T2
,
118 MVE_VSTRW_SCATTER_T3
,
119 MVE_VSTRD_SCATTER_T4
,
120 MVE_VSTRW_SCATTER_T5
,
121 MVE_VSTRD_SCATTER_T6
,
123 MVE_VCVT_BETWEEN_FP_INT
,
125 MVE_VCVT_FROM_FP_TO_INT
,
128 MVE_VMOV_GP_TO_VEC_LANE
,
131 MVE_VMOV2_VEC_LANE_TO_GP
,
132 MVE_VMOV2_GP_TO_VEC_LANE
,
133 MVE_VMOV_VEC_LANE_TO_GP
,
291 enum mve_unpredictable
293 UNPRED_IT_BLOCK
, /* Unpredictable because mve insn in it block.
295 UNPRED_FCA_0_FCB_1
, /* Unpredictable because fcA = 0 and
297 UNPRED_R13
, /* Unpredictable because r13 (sp) or
299 UNPRED_R15
, /* Unpredictable because r15 (pc) is used. */
300 UNPRED_Q_GT_4
, /* Unpredictable because
301 vec reg start > 4 (vld4/st4). */
302 UNPRED_Q_GT_6
, /* Unpredictable because
303 vec reg start > 6 (vld2/st2). */
304 UNPRED_R13_AND_WB
, /* Unpredictable becase gp reg = r13
306 UNPRED_Q_REGS_EQUAL
, /* Unpredictable because vector registers are
308 UNPRED_OS
, /* Unpredictable because offset scaled == 1. */
309 UNPRED_GP_REGS_EQUAL
, /* Unpredictable because gp registers are the
311 UNPRED_Q_REGS_EQ_AND_SIZE_1
, /* Unpredictable because q regs equal and
313 UNPRED_Q_REGS_EQ_AND_SIZE_2
, /* Unpredictable because q regs equal and
315 UNPRED_NONE
/* No unpredictable behavior. */
320 UNDEF_SIZE
, /* undefined size. */
321 UNDEF_SIZE_0
, /* undefined because size == 0. */
322 UNDEF_SIZE_2
, /* undefined because size == 2. */
323 UNDEF_SIZE_3
, /* undefined because size == 3. */
324 UNDEF_SIZE_LE_1
, /* undefined because size <= 1. */
325 UNDEF_SIZE_NOT_0
, /* undefined because size != 0. */
326 UNDEF_SIZE_NOT_2
, /* undefined because size != 2. */
327 UNDEF_SIZE_NOT_3
, /* undefined because size != 3. */
328 UNDEF_NOT_UNS_SIZE_0
, /* undefined because U == 0 and
330 UNDEF_NOT_UNS_SIZE_1
, /* undefined because U == 0 and
332 UNDEF_NOT_UNSIGNED
, /* undefined because U == 0. */
333 UNDEF_VCVT_IMM6
, /* imm6 < 32. */
334 UNDEF_VCVT_FSI_IMM6
, /* fsi = 0 and 32 >= imm6 <= 47. */
335 UNDEF_BAD_OP1_OP2
, /* undefined with op2 = 2 and
337 UNDEF_BAD_U_OP1_OP2
, /* undefined with U = 1 and
338 op2 == 0 and op1 == (0 or 1). */
339 UNDEF_OP_0_BAD_CMODE
, /* undefined because op == 0 and cmode
341 UNDEF_XCHG_UNS
, /* undefined because X == 1 and U == 1. */
342 UNDEF_NONE
/* no undefined behavior. */
347 arm_feature_set arch
; /* Architecture defining this insn. */
348 unsigned long value
; /* If arch is 0 then value is a sentinel. */
349 unsigned long mask
; /* Recognise insn if (op & mask) == value. */
350 const char * assembler
; /* How to disassemble this insn. */
355 arm_feature_set arch
; /* Architecture defining this insn. */
356 uint8_t coproc_shift
; /* coproc is this far into op. */
357 uint16_t coproc_mask
; /* Length of coproc field in op. */
358 unsigned long value
; /* If arch is 0 then value is a sentinel. */
359 unsigned long mask
; /* Recognise insn if (op & mask) == value. */
360 const char * assembler
; /* How to disassemble this insn. */
367 arm_feature_set arch
; /* Architecture defining this insn. */
368 enum mve_instructions mve_op
; /* Specific mve instruction for faster
370 unsigned long value
; /* If arch is 0 then value is a sentinel. */
371 unsigned long mask
; /* Recognise insn if (op & mask) == value. */
372 const char * assembler
; /* How to disassemble this insn. */
382 /* Shared (between Arm and Thumb mode) opcode. */
385 enum isa isa
; /* Execution mode instruction availability. */
386 arm_feature_set arch
; /* Architecture defining this insn. */
387 unsigned long value
; /* If arch is 0 then value is a sentinel. */
388 unsigned long mask
; /* Recognise insn if (op & mask) == value. */
389 const char * assembler
; /* How to disassemble this insn. */
394 arm_feature_set arch
; /* Architecture defining this insn. */
395 unsigned short value
, mask
; /* Recognise insn if (op & mask) == value. */
396 const char *assembler
; /* How to disassemble this insn. */
399 /* print_insn_coprocessor recognizes the following format control codes:
403 %c print condition code (always bits 28-31 in ARM mode)
404 %b print condition code allowing cp_num == 9
405 %q print shifter argument
406 %u print condition code (unconditional in ARM mode,
407 UNPREDICTABLE if not AL in Thumb)
408 %A print address for ldc/stc/ldf/stf instruction
409 %B print vstm/vldm register list
410 %C print vscclrm register list
411 %I print cirrus signed shift immediate: bits 0..3|4..6
412 %J print register for VLDR instruction
413 %K print address for VLDR instruction
414 %F print the COUNT field of a LFM/SFM instruction.
415 %P print floating point precision in arithmetic insn
416 %Q print floating point precision in ldf/stf insn
417 %R print floating point rounding mode
419 %<bitfield>c print as a condition code (for vsel)
420 %<bitfield>r print as an ARM register
421 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
422 %<bitfield>ru as %<>r but each u register must be unique.
423 %<bitfield>d print the bitfield in decimal
424 %<bitfield>k print immediate for VFPv3 conversion instruction
425 %<bitfield>x print the bitfield in hex
426 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
427 %<bitfield>f print a floating point constant if >7 else a
428 floating point register
429 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
430 %<bitfield>g print as an iWMMXt 64-bit register
431 %<bitfield>G print as an iWMMXt general purpose or control register
432 %<bitfield>D print as a NEON D register
433 %<bitfield>Q print as a NEON Q register
434 %<bitfield>V print as a NEON D or Q register
435 %<bitfield>E print a quarter-float immediate value
437 %y<code> print a single precision VFP reg.
438 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
439 %z<code> print a double precision VFP reg
440 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
442 %<bitfield>'c print specified char iff bitfield is all ones
443 %<bitfield>`c print specified char iff bitfield is all zeroes
444 %<bitfield>?ab... select from array of values in big endian order
446 %L print as an iWMMXt N/M width field.
447 %Z print the Immediate of a WSHUFH instruction.
448 %l like 'A' except use byte offsets for 'B' & 'H'
450 %i print 5-bit immediate in bits 8,3..0
452 %r print register offset address for wldt/wstr instruction. */
454 enum opcode_sentinel_enum
456 SENTINEL_IWMMXT_START
= 1,
458 SENTINEL_GENERIC_START
461 #define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
462 #define UNKNOWN_INSTRUCTION_32BIT "\t\t; <UNDEFINED> instruction: %08x"
463 #define UNKNOWN_INSTRUCTION_16BIT "\t\t; <UNDEFINED> instruction: %04x"
464 #define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
466 /* Common coprocessor opcodes shared between Arm and Thumb-2. */
468 /* print_insn_cde recognizes the following format control codes:
472 %a print 'a' iff bit 28 is 1
473 %p print bits 8-10 as coprocessor
474 %<bitfield>d print as decimal
475 %<bitfield>r print as an ARM register
476 %<bitfield>n print as an ARM register but r15 is APSR_nzcv
477 %<bitfield>T print as an ARM register + 1
478 %<bitfield>R as %r but r13 is UNPREDICTABLE
479 %<bitfield>S as %r but rX where X > 10 is UNPREDICTABLE
480 %j print immediate taken from bits (16..21,7,0..5)
481 %k print immediate taken from bits (20..21,7,0..5).
482 %l print immediate taken from bits (20..22,7,4..5). */
484 /* At the moment there is only one valid position for the coprocessor number,
485 and hence that's encoded in the macro below. */
486 #define CDE_OPCODE(ARCH, VALUE, MASK, ASM) \
487 { ARCH, 8, 7, VALUE, MASK, ASM }
488 static const struct cdeopcode32 cde_opcodes
[] =
490 /* Custom Datapath Extension instructions. */
491 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE
),
492 0xee000000, 0xefc00840,
493 "cx1%a\t%p, %12-15n, #%0-5,7,16-21d"),
494 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE
),
495 0xee000040, 0xefc00840,
496 "cx1d%a\t%p, %12-15S, %12-15T, #%0-5,7,16-21d"),
498 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE
),
499 0xee400000, 0xefc00840,
500 "cx2%a\t%p, %12-15n, %16-19n, #%0-5,7,20-21d"),
501 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE
),
502 0xee400040, 0xefc00840,
503 "cx2d%a\t%p, %12-15S, %12-15T, %16-19n, #%0-5,7,20-21d"),
505 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE
),
506 0xee800000, 0xef800840,
507 "cx3%a\t%p, %0-3n, %16-19n, %12-15n, #%4-5,7,20-22d"),
508 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE
),
509 0xee800040, 0xef800840,
510 "cx3d%a\t%p, %0-3S, %0-3T, %16-19n, %12-15n, #%4-5,7,20-22d"),
512 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE
),
513 0xec200000, 0xeeb00840,
514 "vcx1%a\t%p, %12-15,22V, #%0-5,7,16-19d"),
515 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE
),
516 0xec200040, 0xeeb00840,
517 "vcx1%a\t%p, %12-15,22V, #%0-5,7,16-19,24d"),
519 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE
),
520 0xec300000, 0xeeb00840,
521 "vcx2%a\t%p, %12-15,22V, %0-3,5V, #%4,7,16-19d"),
522 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE
),
523 0xec300040, 0xeeb00840,
524 "vcx2%a\t%p, %12-15,22V, %0-3,5V, #%4,7,16-19,24d"),
526 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE
),
527 0xec800000, 0xee800840,
528 "vcx3%a\t%p, %12-15,22V, %16-19,7V, %0-3,5V, #%4,20-21d"),
529 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE
),
530 0xec800040, 0xee800840,
531 "vcx3%a\t%p, %12-15,22V, %16-19,7V, %0-3,5V, #%4,20-21,24d"),
533 CDE_OPCODE (ARM_FEATURE_CORE_LOW (0), 0, 0, 0)
537 static const struct sopcode32 coprocessor_opcodes
[] =
539 /* XScale instructions. */
540 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
541 0x0e200010, 0x0fff0ff0,
542 "mia%c\tacc0, %0-3r, %12-15r"},
543 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
544 0x0e280010, 0x0fff0ff0,
545 "miaph%c\tacc0, %0-3r, %12-15r"},
546 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
547 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
548 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
549 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
550 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
551 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
553 /* Intel Wireless MMX technology instructions. */
554 {ANY
, ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START
, 0, "" },
555 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
556 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
557 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
558 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
559 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
560 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
561 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
562 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
563 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
564 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
565 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
566 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
567 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
568 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
569 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
570 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
571 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
572 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
573 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
574 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
575 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
576 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
577 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
578 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
579 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
580 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
581 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
582 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
583 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
584 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
585 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
586 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
587 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
588 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
589 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
590 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
591 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
592 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
593 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
594 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
595 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
596 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
597 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
598 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
599 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
600 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
601 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
602 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
603 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
604 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
605 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
606 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
607 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
608 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
609 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
610 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
611 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
612 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
613 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
614 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
615 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
616 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
617 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
618 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
619 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
620 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
621 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
622 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
623 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
624 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
625 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
626 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
627 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
628 0x0e800120, 0x0f800ff0,
629 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
630 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
631 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
632 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
633 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
634 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
635 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
636 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
637 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
638 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
639 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
640 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
641 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
642 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
643 0x0e8000a0, 0x0f800ff0,
644 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
645 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
646 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
647 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
648 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
649 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
650 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
651 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
652 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
653 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
654 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
655 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
656 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
657 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
658 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
659 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
660 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
661 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
662 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
663 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
664 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
665 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
666 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
667 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
668 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
669 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
670 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
671 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
672 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
673 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
674 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
675 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
676 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
677 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
678 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
679 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
680 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
681 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
682 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
683 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
684 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
685 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
686 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
687 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
688 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
689 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
690 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
691 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
692 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
693 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
694 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
695 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
696 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
697 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
698 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
699 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
700 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
701 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
702 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
703 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
704 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
705 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
706 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
707 {ANY
, ARM_FEATURE_CORE_LOW (0),
708 SENTINEL_IWMMXT_END
, 0, "" },
710 /* Floating point coprocessor (FPA) instructions. */
711 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
712 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
713 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
714 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
715 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
716 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
717 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
718 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
719 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
720 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
721 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
722 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
723 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
724 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
725 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
726 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
727 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
728 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
729 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
730 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
731 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
732 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
733 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
734 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
735 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
736 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
737 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
738 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
739 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
740 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
741 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
742 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
743 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
744 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
745 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
746 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
747 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
748 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
749 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
750 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
751 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
752 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
753 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
754 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
755 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
756 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
757 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
758 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
759 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
760 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
761 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
762 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
763 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
764 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
765 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
766 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
767 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
768 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
769 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
770 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
771 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
772 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
773 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
774 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
775 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
776 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
777 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
778 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
779 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
780 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
781 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
782 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
783 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
784 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
785 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
786 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
787 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
788 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
789 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
790 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
791 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
792 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
793 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
),
794 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
795 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
),
796 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
798 /* Armv8.1-M Mainline instructions. */
799 {T32
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
800 0xec9f0b00, 0xffbf0f01, "vscclrm%c\t%C"},
801 {T32
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
802 0xec9f0a00, 0xffbf0f00, "vscclrm%c\t%C"},
804 /* ARMv8-M Mainline Security Extensions instructions. */
805 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
),
806 0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
807 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
),
808 0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
810 /* Register load/store. */
811 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
812 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
813 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
814 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
815 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
816 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
817 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
818 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
819 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
820 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
821 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
822 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
823 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
824 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
825 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
826 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
827 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
828 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
829 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
830 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
831 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
832 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
833 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
834 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
835 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
836 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
837 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
838 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
839 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
840 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
841 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
842 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
843 {ANY
, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN
),
844 0xec100f80, 0xfe101f80, "vldr%c\t%J, %K"},
845 {ANY
, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN
),
846 0xec000f80, 0xfe101f80, "vstr%c\t%J, %K"},
848 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
849 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
850 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
851 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
852 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
853 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
854 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
855 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
857 /* Data transfer between ARM and NEON registers. */
858 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
859 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
860 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
861 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
862 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
863 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
864 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
865 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
866 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
867 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
868 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
869 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
870 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
871 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
872 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
873 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
874 /* Half-precision conversion instructions. */
875 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
876 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
877 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
878 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
879 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
),
880 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
881 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
),
882 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
884 /* Floating point coprocessor (VFP) instructions. */
885 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
886 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
887 {ANY
, ARM_FEATURE (0, ARM_EXT2_V8_1M_MAIN
, FPU_VFP_EXT_V1xD
),
888 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
889 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
890 0x0ee20a10, 0x0fff0fff, "vmsr%c\tfpscr_nzcvqc, %12-15r"},
891 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
892 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
893 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
894 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
895 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
896 0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"},
897 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
898 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
899 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
900 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
901 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
902 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
903 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
904 0x0eec0a10, 0x0fff0fff, "vmsr%c\tvpr, %12-15r"},
905 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
906 0x0eed0a10, 0x0fff0fff, "vmsr%c\tp0, %12-15r"},
907 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
908 0x0eee0a10, 0x0fff0fff, "vmsr%c\tfpcxt_ns, %12-15r"},
909 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
910 0x0eef0a10, 0x0fff0fff, "vmsr%c\tfpcxt_s, %12-15r"},
911 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
912 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
913 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
914 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
915 {ANY
, ARM_FEATURE (0, ARM_EXT2_V8_1M_MAIN
, FPU_VFP_EXT_V1xD
),
916 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
917 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
918 0x0ef20a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr_nzcvqc"},
919 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
920 0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"},
921 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
922 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
923 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
924 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
925 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
926 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
927 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
928 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
929 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
930 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
931 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
932 0x0efc0a10, 0x0fff0fff, "vmrs%c\t%12-15r, vpr"},
933 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
934 0x0efd0a10, 0x0fff0fff, "vmrs%c\t%12-15r, p0"},
935 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
936 0x0efe0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpcxt_ns"},
937 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
938 0x0eff0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpcxt_s"},
939 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
940 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
941 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
942 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
943 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
944 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
945 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
946 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
947 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
948 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
949 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
950 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
951 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
952 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
953 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
954 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
955 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
956 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
957 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
958 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
959 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
960 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
961 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
962 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
963 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
964 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
965 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
966 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
967 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
968 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
969 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
970 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
971 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
972 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
973 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
974 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
975 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
976 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
977 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
978 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
979 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
980 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
981 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
982 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
983 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
),
984 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
985 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
),
986 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
987 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
988 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
989 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
990 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
991 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
),
992 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
993 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
),
994 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
995 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
996 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
997 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
),
998 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
999 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
),
1000 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
1001 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
),
1002 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
1003 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
),
1004 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
1005 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
),
1006 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
1007 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
1008 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
1009 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
1010 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
1011 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
1012 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
1013 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
1014 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
1015 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
1016 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
1017 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
1018 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
1019 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
1020 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
1021 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
1022 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
1023 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
1024 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
1025 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
1026 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
1027 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
1028 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
1029 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
1030 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
1031 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
1032 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
1033 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
1034 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
1035 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
1036 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
1037 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
1038 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
1039 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
1040 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
1041 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
1042 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
1044 /* Cirrus coprocessor instructions. */
1045 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1046 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
1047 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1048 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
1049 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1050 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
1051 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1052 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
1053 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1054 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
1055 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1056 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
1057 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1058 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
1059 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1060 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
1061 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1062 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
1063 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1064 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
1065 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1066 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
1067 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1068 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
1069 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1070 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
1071 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1072 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
1073 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1074 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
1075 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1076 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
1077 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1078 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
1079 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1080 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
1081 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1082 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
1083 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1084 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
1085 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1086 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
1087 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1088 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
1089 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1090 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
1091 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1092 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
1093 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1094 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
1095 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1096 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
1097 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1098 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
1099 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1100 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
1101 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1102 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
1103 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1104 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
1105 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1106 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
1107 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1108 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
1109 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1110 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
1111 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1112 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
1113 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1114 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
1115 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1116 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
1117 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1118 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
1119 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1120 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
1121 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1122 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
1123 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1124 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
1125 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1126 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
1127 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1128 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
1129 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1130 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
1131 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1132 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
1133 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1134 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
1135 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1136 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
1137 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1138 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
1139 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1140 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
1141 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1142 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
1143 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1144 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
1145 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1146 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
1147 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1148 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
1149 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1150 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
1151 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1152 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
1153 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1154 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
1155 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1156 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
1157 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1158 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
1159 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1160 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
1161 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1162 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
1163 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1164 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
1165 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1166 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
1167 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1168 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
1169 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1170 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
1171 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1172 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
1173 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1174 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
1175 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1176 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
1177 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1178 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
1179 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1180 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
1181 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1182 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
1183 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1184 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
1185 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1186 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
1187 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1188 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
1189 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1190 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1191 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1192 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
1193 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1194 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1195 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1196 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
1197 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1198 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1199 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1200 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
1201 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1202 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1203 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1204 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1205 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1206 0x0e000600, 0x0ff00f10,
1207 "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1208 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1209 0x0e100600, 0x0ff00f10,
1210 "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1211 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1212 0x0e200600, 0x0ff00f10,
1213 "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
1214 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1215 0x0e300600, 0x0ff00f10,
1216 "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
1218 /* VFP Fused multiply add instructions. */
1219 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1220 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
1221 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1222 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
1223 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1224 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
1225 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1226 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
1227 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1228 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
1229 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1230 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
1231 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1232 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
1233 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1234 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
1237 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1238 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
1239 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1240 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
1241 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1242 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
1243 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1244 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
1245 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1246 0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
1247 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1248 0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
1249 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1250 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
1251 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1252 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
1253 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1254 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
1255 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1256 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
1257 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1258 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
1259 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1260 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
1262 {ANY
, ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START
, 0, "" },
1263 /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */
1264 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1265 0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
1266 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1267 0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
1268 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1269 0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
1270 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1271 0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
1272 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1273 0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
1274 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1275 0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
1276 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1277 0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
1278 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1279 0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"},
1280 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1281 0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
1282 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1283 0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"},
1285 /* BFloat16 instructions. */
1286 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
),
1287 0x0eb30940, 0x0fbf0f50, "vcvt%7?tb%b.bf16.f32\t%y1, %y0"},
1289 /* Dot Product instructions in the space of coprocessor 13. */
1290 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
1291 0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
1292 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
1293 0xfe200d00, 0xff200f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"},
1295 /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8. */
1296 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1297 0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
1298 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1299 0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
1300 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1301 0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
1302 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1303 0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
1304 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1305 0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
1306 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1307 0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
1308 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1309 0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
1310 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1311 0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
1313 /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
1314 cp_num: bit <11:8> == 0b1001.
1315 cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */
1316 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1317 0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
1318 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1319 0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
1320 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1321 0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
1322 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1323 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
1324 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1325 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
1326 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1327 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
1328 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1329 0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
1330 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1331 0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
1332 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1333 0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
1334 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1335 0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
1336 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1337 0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
1338 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1339 0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
1340 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1341 0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
1342 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1343 0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
1344 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1345 0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
1346 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1347 0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
1348 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1349 0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
1350 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1351 0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
1352 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1353 0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
1354 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1355 0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
1356 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1357 0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
1358 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1359 0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
1360 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1361 0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
1362 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1363 0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
1364 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1365 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
1366 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1367 0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
1368 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1369 0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
1370 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1371 0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
1372 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1373 0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
1374 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1375 0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
1376 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1377 0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
1378 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1379 0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
1380 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1381 0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
1382 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1383 0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
1384 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1385 0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
1387 /* ARMv8.3 javascript conversion instruction. */
1388 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1389 0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
1391 {ANY
, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
1394 /* Generic coprocessor instructions. These are only matched if a more specific
1395 SIMD or co-processor instruction does not match first. */
1397 static const struct sopcode32 generic_coprocessor_opcodes
[] =
1399 /* Generic coprocessor instructions. */
1400 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
1401 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
1402 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
1403 0x0c500000, 0x0ff00000,
1404 "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
1405 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1406 0x0e000000, 0x0f000010,
1407 "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
1408 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1409 0x0e10f010, 0x0f10f010,
1410 "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
1411 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1412 0x0e100010, 0x0f100010,
1413 "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1414 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1415 0x0e000010, 0x0f100010,
1416 "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
1417 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1418 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
1419 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1420 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
1422 /* V6 coprocessor instructions. */
1423 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
1424 0xfc500000, 0xfff00000,
1425 "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
1426 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
1427 0xfc400000, 0xfff00000,
1428 "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
1430 /* V5 coprocessor instructions. */
1431 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1432 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
1433 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1434 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
1435 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1436 0xfe000000, 0xff000010,
1437 "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
1438 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1439 0xfe000010, 0xff100010,
1440 "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
1441 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1442 0xfe100010, 0xff100010,
1443 "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1445 {ANY
, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
1448 /* Neon opcode table: This does not encode the top byte -- that is
1449 checked by the print_insn_neon routine, as it depends on whether we are
1450 doing thumb32 or arm32 disassembly. */
1452 /* print_insn_neon recognizes the following format control codes:
1456 %c print condition code
1457 %u print condition code (unconditional in ARM mode,
1458 UNPREDICTABLE if not AL in Thumb)
1459 %A print v{st,ld}[1234] operands
1460 %B print v{st,ld}[1234] any one operands
1461 %C print v{st,ld}[1234] single->all operands
1463 %E print vmov, vmvn, vorr, vbic encoded constant
1464 %F print vtbl,vtbx register list
1466 %<bitfield>r print as an ARM register
1467 %<bitfield>d print the bitfield in decimal
1468 %<bitfield>e print the 2^N - bitfield in decimal
1469 %<bitfield>D print as a NEON D register
1470 %<bitfield>Q print as a NEON Q register
1471 %<bitfield>R print as a NEON D or Q register
1472 %<bitfield>Sn print byte scaled width limited by n
1473 %<bitfield>Tn print short scaled width limited by n
1474 %<bitfield>Un print long scaled width limited by n
1476 %<bitfield>'c print specified char iff bitfield is all ones
1477 %<bitfield>`c print specified char iff bitfield is all zeroes
1478 %<bitfield>?ab... select from array of values in big endian order. */
1480 static const struct opcode32 neon_opcodes
[] =
1483 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1484 0xf2b00840, 0xffb00850,
1485 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1486 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1487 0xf2b00000, 0xffb00810,
1488 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1490 /* Data transfer between ARM and NEON registers. */
1491 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1492 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
1493 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1494 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
1495 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1496 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
1497 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1498 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
1499 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1500 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
1501 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1502 0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
1504 /* Move data element to all lanes. */
1505 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1506 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
1507 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1508 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
1509 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1510 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
1513 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1514 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1515 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1516 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1518 /* Half-precision conversions. */
1519 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
),
1520 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1521 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
),
1522 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
1524 /* NEON fused multiply add instructions. */
1525 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
),
1526 0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1527 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1528 0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1529 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
),
1530 0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1531 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1532 0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1534 /* BFloat16 instructions. */
1535 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
),
1536 0xfc000d00, 0xffb00f10, "vdot.bf16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1537 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
),
1538 0xfe000d00, 0xffb00f10, "vdot.bf16\t%12-15,22R, %16-19,7R, d%0-3d[%5d]"},
1539 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
),
1540 0xfc000c40, 0xffb00f50, "vmmla.bf16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1541 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
),
1542 0xf3b60640, 0xffbf0fd0, "vcvt%c.bf16.f32\t%12-15,22D, %0-3,5Q"},
1543 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
),
1544 0xfc300810, 0xffb00f10, "vfma%6?tb.bf16\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1545 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
),
1546 0xfe300810, 0xffb00f10, "vfma%6?tb.bf16\t%12-15,22Q, %16-19,7Q, %0-2D[%3,5d]"},
1548 /* Matrix Multiply instructions. */
1549 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
),
1550 0xfc200c40, 0xffb00f50, "vsmmla.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1551 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
),
1552 0xfc200c50, 0xffb00f50, "vummla.u8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1553 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
),
1554 0xfca00c40, 0xffb00f50, "vusmmla.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1555 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
),
1556 0xfca00d00, 0xffb00f10, "vusdot.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1557 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
),
1558 0xfe800d00, 0xffb00f10, "vusdot.s8\t%12-15,22R, %16-19,7R, d%0-3d[%5d]"},
1559 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
),
1560 0xfe800d10, 0xffb00f10, "vsudot.u8\t%12-15,22R, %16-19,7R, d%0-3d[%5d]"},
1562 /* Two registers, miscellaneous. */
1563 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
),
1564 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
1565 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1566 0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
1567 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
),
1568 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
1569 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1570 0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
1571 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1572 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1573 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1574 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1575 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1576 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1577 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1578 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1579 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1580 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1581 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1582 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1583 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1584 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1585 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1586 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1587 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1588 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1589 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1590 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1591 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1592 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1593 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1594 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1595 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1596 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1597 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1598 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1599 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1600 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1601 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1602 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1603 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1604 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1605 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1606 0xf3b20300, 0xffb30fd0,
1607 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1608 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1609 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1610 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1611 0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1612 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1613 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1614 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1615 0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1616 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1617 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1618 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1619 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1620 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1621 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1622 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1623 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1624 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1625 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1626 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1627 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1628 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1629 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1630 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1631 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1632 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1633 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1634 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1635 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1636 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1637 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1638 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1639 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1640 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1641 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1642 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1643 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1644 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1645 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1646 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1647 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1648 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1649 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1650 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1651 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1652 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1653 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1654 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1655 0xf3bb0600, 0xffbf0e10,
1656 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
1657 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1658 0xf3b70600, 0xffbf0e10,
1659 "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
1661 /* Three registers of the same length. */
1662 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1663 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1664 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1665 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1666 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1667 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1668 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1669 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1670 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1671 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1672 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1673 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1674 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1675 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1676 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
),
1677 0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1678 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1679 0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1680 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
),
1681 0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1682 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1683 0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1684 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1685 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1686 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1687 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1688 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1689 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1690 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1691 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1692 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1693 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1694 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1695 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1696 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1697 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1698 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1699 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1700 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1701 0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1702 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1703 0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1704 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1705 0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1706 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1707 0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1708 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1709 0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1710 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1711 0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1712 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1713 0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1714 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1715 0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1716 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1717 0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1718 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1719 0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1720 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1721 0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1722 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1723 0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1724 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1725 0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1726 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1727 0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1728 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1729 0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1730 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1731 0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1732 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1733 0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1734 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1735 0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1736 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1737 0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1738 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1739 0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1740 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1741 0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1742 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1743 0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1744 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1745 0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1746 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1747 0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1748 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1749 0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1750 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1751 0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1752 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1753 0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1754 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1755 0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1756 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1757 0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1758 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1759 0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1760 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1761 0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1762 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1763 0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1764 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1765 0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1766 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1767 0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1768 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1769 0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1770 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1771 0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1772 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1773 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1774 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1775 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1776 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1777 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1778 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1779 0xf2000b00, 0xff800f10,
1780 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1781 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1782 0xf2000b10, 0xff800f10,
1783 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1784 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1785 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1786 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1787 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1788 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1789 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1790 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1791 0xf3000b00, 0xff800f10,
1792 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1793 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1794 0xf2000000, 0xfe800f10,
1795 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1796 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1797 0xf2000010, 0xfe800f10,
1798 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1799 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1800 0xf2000100, 0xfe800f10,
1801 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1802 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1803 0xf2000200, 0xfe800f10,
1804 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1805 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1806 0xf2000210, 0xfe800f10,
1807 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1808 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1809 0xf2000300, 0xfe800f10,
1810 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1811 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1812 0xf2000310, 0xfe800f10,
1813 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1814 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1815 0xf2000400, 0xfe800f10,
1816 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1817 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1818 0xf2000410, 0xfe800f10,
1819 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1820 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1821 0xf2000500, 0xfe800f10,
1822 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1823 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1824 0xf2000510, 0xfe800f10,
1825 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1826 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1827 0xf2000600, 0xfe800f10,
1828 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1829 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1830 0xf2000610, 0xfe800f10,
1831 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1832 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1833 0xf2000700, 0xfe800f10,
1834 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1835 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1836 0xf2000710, 0xfe800f10,
1837 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1838 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1839 0xf2000910, 0xfe800f10,
1840 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1841 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1842 0xf2000a00, 0xfe800f10,
1843 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1844 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1845 0xf2000a10, 0xfe800f10,
1846 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1847 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
1848 0xf3000b10, 0xff800f10,
1849 "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1850 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
1851 0xf3000c10, 0xff800f10,
1852 "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1854 /* One register and an immediate value. */
1855 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1856 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1857 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1858 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1859 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1860 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1861 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1862 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1863 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1864 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1865 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1866 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1867 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1868 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1869 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1870 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1871 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1872 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1873 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1874 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1875 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1876 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1877 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1878 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1879 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1880 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
1882 /* Two registers and a shift amount. */
1883 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1884 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1885 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1886 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1887 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1888 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1889 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1890 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1891 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1892 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1893 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1894 0xf2880950, 0xfeb80fd0,
1895 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1896 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1897 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1898 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1899 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1900 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1901 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1902 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1903 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1904 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1905 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1906 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1907 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1908 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1909 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1910 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1911 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1912 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1913 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1914 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1915 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1916 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1917 0xf2900950, 0xfeb00fd0,
1918 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1919 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1920 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1921 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1922 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1923 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1924 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1925 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1926 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1927 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1928 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1929 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1930 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1931 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1932 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1933 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1934 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1935 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1936 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1937 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1938 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1939 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1940 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1941 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1942 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1943 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1944 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1945 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1946 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1947 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1948 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1949 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1950 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1951 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1952 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1953 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1954 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1955 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1956 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1957 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1958 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1959 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1960 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1961 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1962 0xf2a00950, 0xfea00fd0,
1963 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1964 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1965 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1966 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1967 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1968 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1969 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1970 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1971 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1972 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1973 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1974 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1975 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1976 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1977 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1978 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1979 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1980 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1981 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1982 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1983 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1984 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1985 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1986 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1987 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1988 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1989 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1990 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1991 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1992 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1993 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1994 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1995 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1996 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1997 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1998 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1999 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
2000 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2001 0xf2a00e10, 0xfea00e90,
2002 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
2003 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
2004 0xf2a00c10, 0xfea00e90,
2005 "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"},
2007 /* Three registers of different lengths. */
2008 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
2009 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2010 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2011 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2012 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2013 0xf2800400, 0xff800f50,
2014 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
2015 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2016 0xf2800600, 0xff800f50,
2017 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
2018 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2019 0xf2800900, 0xff800f50,
2020 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2021 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2022 0xf2800b00, 0xff800f50,
2023 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2024 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2025 0xf2800d00, 0xff800f50,
2026 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2027 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2028 0xf3800400, 0xff800f50,
2029 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
2030 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2031 0xf3800600, 0xff800f50,
2032 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
2033 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2034 0xf2800000, 0xfe800f50,
2035 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2036 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2037 0xf2800100, 0xfe800f50,
2038 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
2039 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2040 0xf2800200, 0xfe800f50,
2041 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2042 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2043 0xf2800300, 0xfe800f50,
2044 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
2045 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2046 0xf2800500, 0xfe800f50,
2047 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2048 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2049 0xf2800700, 0xfe800f50,
2050 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2051 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2052 0xf2800800, 0xfe800f50,
2053 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2054 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2055 0xf2800a00, 0xfe800f50,
2056 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2057 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2058 0xf2800c00, 0xfe800f50,
2059 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2061 /* Two registers and a scalar. */
2062 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2063 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2064 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2065 0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
2066 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
2067 0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
2068 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2069 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2070 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2071 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2072 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2073 0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2074 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
2075 0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
2076 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2077 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2078 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2079 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2080 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2081 0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
2082 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
2083 0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
2084 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2085 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2086 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2087 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2088 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2089 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2090 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2091 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2092 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2093 0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
2094 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
2095 0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
2096 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2097 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2098 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2099 0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
2100 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
2101 0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
2102 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2103 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2104 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2105 0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
2106 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
2107 0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
2108 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2109 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2110 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2111 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2112 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2113 0xf2800240, 0xfe800f50,
2114 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2115 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2116 0xf2800640, 0xfe800f50,
2117 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2118 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2119 0xf2800a40, 0xfe800f50,
2120 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2121 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
2122 0xf2800e40, 0xff800f50,
2123 "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2124 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
2125 0xf2800f40, 0xff800f50,
2126 "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2127 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
2128 0xf3800e40, 0xff800f50,
2129 "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2130 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
2131 0xf3800f40, 0xff800f50,
2132 "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
2135 /* Element and structure load/store. */
2136 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2137 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
2138 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2139 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
2140 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2141 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
2142 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2143 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
2144 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2145 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
2146 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2147 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2148 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2149 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2150 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2151 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
2152 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2153 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
2154 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2155 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2156 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2157 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2158 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2159 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2160 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2161 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2162 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2163 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2164 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2165 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
2166 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2167 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
2168 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2169 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
2170 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2171 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
2172 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2173 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
2175 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
2178 /* mve opcode table. */
2180 /* print_insn_mve recognizes the following format control codes:
2184 %a print '+' or '-' or imm offset in vldr[bhwd] and
2186 %c print condition code
2187 %d print addr mode of MVE vldr[bhw] and vstr[bhw]
2188 %u print 'U' (unsigned) or 'S' for various mve instructions
2189 %i print MVE predicate(s) for vpt and vpst
2190 %j print a 5-bit immediate from hw2[14:12,7:6]
2191 %k print 48 if the 7th position bit is set else print 64.
2192 %m print rounding mode for vcvt and vrint
2193 %n print vector comparison code for predicated instruction
2194 %s print size for various vcvt instructions
2195 %v print vector predicate for instruction in predicated
2197 %o print offset scaled for vldr[hwd] and vstr[hwd]
2198 %w print writeback mode for MVE v{st,ld}[24]
2199 %B print v{st,ld}[24] any one operands
2200 %E print vmov, vmvn, vorr, vbic encoded constant
2201 %N print generic index for vmov
2202 %T print bottom ('b') or top ('t') of source register
2203 %X print exchange field in vmla* instructions
2205 %<bitfield>r print as an ARM register
2206 %<bitfield>d print the bitfield in decimal
2207 %<bitfield>A print accumulate or not
2208 %<bitfield>c print bitfield as a condition code
2209 %<bitfield>C print bitfield as an inverted condition code
2210 %<bitfield>Q print as a MVE Q register
2211 %<bitfield>F print as a MVE S register
2212 %<bitfield>Z as %<>r but r15 is ZR instead of PC and r13 is
2215 %<bitfield>S as %<>r but r15 or r13 is UNPREDICTABLE
2216 %<bitfield>s print size for vector predicate & non VMOV instructions
2217 %<bitfield>I print carry flag or not
2218 %<bitfield>i print immediate for vstr/vldr reg +/- imm
2219 %<bitfield>h print high half of 64-bit destination reg
2220 %<bitfield>k print immediate for vector conversion instruction
2221 %<bitfield>l print low half of 64-bit destination reg
2222 %<bitfield>o print rotate value for vcmul
2223 %<bitfield>u print immediate value for vddup/vdwdup
2224 %<bitfield>x print the bitfield in hex.
2227 static const struct mopcode32 mve_opcodes
[] =
2231 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2233 0xfe310f4d, 0xffbf1fff,
2237 /* Floating point VPT T1. */
2238 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2240 0xee310f00, 0xefb10f50,
2241 "vpt%i.f%28s\t%n, %17-19Q, %1-3,5Q"},
2242 /* Floating point VPT T2. */
2243 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2245 0xee310f40, 0xefb10f50,
2246 "vpt%i.f%28s\t%n, %17-19Q, %0-3Z"},
2248 /* Vector VPT T1. */
2249 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2251 0xfe010f00, 0xff811f51,
2252 "vpt%i.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2253 /* Vector VPT T2. */
2254 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2256 0xfe010f01, 0xff811f51,
2257 "vpt%i.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2258 /* Vector VPT T3. */
2259 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2261 0xfe011f00, 0xff811f50,
2262 "vpt%i.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2263 /* Vector VPT T4. */
2264 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2266 0xfe010f40, 0xff811f70,
2267 "vpt%i.i%20-21s\t%n, %17-19Q, %0-3Z"},
2268 /* Vector VPT T5. */
2269 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2271 0xfe010f60, 0xff811f70,
2272 "vpt%i.u%20-21s\t%n, %17-19Q, %0-3Z"},
2273 /* Vector VPT T6. */
2274 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2276 0xfe011f40, 0xff811f50,
2277 "vpt%i.s%20-21s\t%n, %17-19Q, %0-3Z"},
2279 /* Vector VBIC immediate. */
2280 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2282 0xef800070, 0xefb81070,
2283 "vbic%v.i%8-11s\t%13-15,22Q, %E"},
2285 /* Vector VBIC register. */
2286 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2288 0xef100150, 0xffb11f51,
2289 "vbic%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2292 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2294 0xee800f01, 0xefc10f51,
2295 "vabav%v.%u%20-21s\t%12-15r, %17-19,7Q, %1-3,5Q"},
2297 /* Vector VABD floating point. */
2298 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2300 0xff200d40, 0xffa11f51,
2301 "vabd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2304 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2306 0xef000740, 0xef811f51,
2307 "vabd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2309 /* Vector VABS floating point. */
2310 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2312 0xFFB10740, 0xFFB31FD1,
2313 "vabs%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
2315 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2317 0xffb10340, 0xffb31fd1,
2318 "vabs%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2320 /* Vector VADD floating point T1. */
2321 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2323 0xef000d40, 0xffa11f51,
2324 "vadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2325 /* Vector VADD floating point T2. */
2326 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2328 0xee300f40, 0xefb11f70,
2329 "vadd%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2330 /* Vector VADD T1. */
2331 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2333 0xef000840, 0xff811f51,
2334 "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2335 /* Vector VADD T2. */
2336 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2338 0xee010f40, 0xff811f70,
2339 "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2341 /* Vector VADDLV. */
2342 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2344 0xee890f00, 0xef8f1fd1,
2345 "vaddlv%5A%v.%u32\t%13-15l, %20-22h, %1-3Q"},
2348 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2350 0xeef10f00, 0xeff31fd1,
2351 "vaddv%5A%v.%u%18-19s\t%13-15l, %1-3Q"},
2354 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2356 0xee300f00, 0xffb10f51,
2357 "vadc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2360 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2362 0xef000150, 0xffb11f51,
2363 "vand%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2365 /* Vector VBRSR register. */
2366 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2368 0xfe011e60, 0xff811f70,
2369 "vbrsr%v.%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2371 /* Vector VCADD floating point. */
2372 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2374 0xfc800840, 0xfea11f51,
2375 "vcadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%24o"},
2378 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2380 0xfe000f00, 0xff810f51,
2381 "vcadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
2384 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2386 0xffb00440, 0xffb31fd1,
2387 "vcls%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2390 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2392 0xffb004c0, 0xffb31fd1,
2393 "vclz%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2396 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2398 0xfc200840, 0xfe211f51,
2399 "vcmla%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%23-24o"},
2401 /* Vector VCMP floating point T1. */
2402 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2404 0xee310f00, 0xeff1ef50,
2405 "vcmp%v.f%28s\t%n, %17-19Q, %1-3,5Q"},
2407 /* Vector VCMP floating point T2. */
2408 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2410 0xee310f40, 0xeff1ef50,
2411 "vcmp%v.f%28s\t%n, %17-19Q, %0-3Z"},
2413 /* Vector VCMP T1. */
2414 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2416 0xfe010f00, 0xffc1ff51,
2417 "vcmp%v.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2418 /* Vector VCMP T2. */
2419 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2421 0xfe010f01, 0xffc1ff51,
2422 "vcmp%v.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2423 /* Vector VCMP T3. */
2424 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2426 0xfe011f00, 0xffc1ff50,
2427 "vcmp%v.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2428 /* Vector VCMP T4. */
2429 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2431 0xfe010f40, 0xffc1ff70,
2432 "vcmp%v.i%20-21s\t%n, %17-19Q, %0-3Z"},
2433 /* Vector VCMP T5. */
2434 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2436 0xfe010f60, 0xffc1ff70,
2437 "vcmp%v.u%20-21s\t%n, %17-19Q, %0-3Z"},
2438 /* Vector VCMP T6. */
2439 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2441 0xfe011f40, 0xffc1ff50,
2442 "vcmp%v.s%20-21s\t%n, %17-19Q, %0-3Z"},
2445 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2447 0xeea00b10, 0xffb10f5f,
2448 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2451 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2453 0xff000150, 0xffd11f51,
2454 "veor%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2456 /* Vector VFMA, vector * scalar. */
2457 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2459 0xee310e40, 0xefb11f70,
2460 "vfma%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2462 /* Vector VFMA floating point. */
2463 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2465 0xef000c50, 0xffa11f51,
2466 "vfma%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2468 /* Vector VFMS floating point. */
2469 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2471 0xef200c50, 0xffa11f51,
2472 "vfms%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2474 /* Vector VFMAS, vector * scalar. */
2475 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2476 MVE_VFMAS_FP_SCALAR
,
2477 0xee311e40, 0xefb11f70,
2478 "vfmas%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2480 /* Vector VHADD T1. */
2481 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2483 0xef000040, 0xef811f51,
2484 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2486 /* Vector VHADD T2. */
2487 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2489 0xee000f40, 0xef811f70,
2490 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2492 /* Vector VHSUB T1. */
2493 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2495 0xef000240, 0xef811f51,
2496 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2498 /* Vector VHSUB T2. */
2499 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2501 0xee001f40, 0xef811f70,
2502 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2505 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2507 0xee300e00, 0xefb10f50,
2508 "vcmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%0,12o"},
2511 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2513 0xf000e801, 0xffc0ffff,
2514 "vctp%v.%20-21s\t%16-19r"},
2517 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2519 0xeea00b10, 0xffb10f5f,
2520 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2522 /* Vector VRHADD. */
2523 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2525 0xef000140, 0xef811f51,
2526 "vrhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2529 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2530 MVE_VCVT_FP_FIX_VEC
,
2531 0xef800c50, 0xef801cd1,
2532 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q, #%16-21k"},
2535 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2536 MVE_VCVT_BETWEEN_FP_INT
,
2537 0xffb30640, 0xffb31e51,
2538 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q"},
2540 /* Vector VCVT between single and half-precision float, bottom half. */
2541 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2542 MVE_VCVT_FP_HALF_FP
,
2543 0xee3f0e01, 0xefbf1fd1,
2544 "vcvtb%v.%s\t%13-15,22Q, %1-3,5Q"},
2546 /* Vector VCVT between single and half-precision float, top half. */
2547 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2548 MVE_VCVT_FP_HALF_FP
,
2549 0xee3f1e01, 0xefbf1fd1,
2550 "vcvtt%v.%s\t%13-15,22Q, %1-3,5Q"},
2553 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2554 MVE_VCVT_FROM_FP_TO_INT
,
2555 0xffb30040, 0xffb31c51,
2556 "vcvt%m%v.%s\t%13-15,22Q, %1-3,5Q"},
2559 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2561 0xee011f6e, 0xff811f7e,
2562 "vddup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
2564 /* Vector VDWDUP. */
2565 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2567 0xee011f60, 0xff811f70,
2568 "vdwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
2570 /* Vector VHCADD. */
2571 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2573 0xee000f00, 0xff810f51,
2574 "vhcadd%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
2576 /* Vector VIWDUP. */
2577 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2579 0xee010f60, 0xff811f70,
2580 "viwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
2583 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2585 0xee010f6e, 0xff811f7e,
2586 "vidup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
2589 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2591 0xfc901e00, 0xff901e5f,
2592 "vld2%5d.%7-8s\t%B, [%16-19r]%w"},
2595 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2597 0xfc901e01, 0xff901e1f,
2598 "vld4%5-6d.%7-8s\t%B, [%16-19r]%w"},
2600 /* Vector VLDRB gather load. */
2601 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2602 MVE_VLDRB_GATHER_T1
,
2603 0xec900e00, 0xefb01e50,
2604 "vldrb%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
2606 /* Vector VLDRH gather load. */
2607 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2608 MVE_VLDRH_GATHER_T2
,
2609 0xec900e10, 0xefb01e50,
2610 "vldrh%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2612 /* Vector VLDRW gather load. */
2613 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2614 MVE_VLDRW_GATHER_T3
,
2615 0xfc900f40, 0xffb01fd0,
2616 "vldrw%v.u32\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2618 /* Vector VLDRD gather load. */
2619 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2620 MVE_VLDRD_GATHER_T4
,
2621 0xec900fd0, 0xefb01fd0,
2622 "vldrd%v.u64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2624 /* Vector VLDRW gather load. */
2625 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2626 MVE_VLDRW_GATHER_T5
,
2627 0xfd101e00, 0xff111f00,
2628 "vldrw%v.u32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2630 /* Vector VLDRD gather load, variant T6. */
2631 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2632 MVE_VLDRD_GATHER_T6
,
2633 0xfd101f00, 0xff111f00,
2634 "vldrd%v.u64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2637 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2639 0xec100e00, 0xee581e00,
2640 "vldrb%v.%u%7-8s\t%13-15Q, %d"},
2643 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2645 0xec180e00, 0xee581e00,
2646 "vldrh%v.%u%7-8s\t%13-15Q, %d"},
2648 /* Vector VLDRB unsigned, variant T5. */
2649 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2651 0xec101e00, 0xfe101f80,
2652 "vldrb%v.u8\t%13-15,22Q, %d"},
2654 /* Vector VLDRH unsigned, variant T6. */
2655 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2657 0xec101e80, 0xfe101f80,
2658 "vldrh%v.u16\t%13-15,22Q, %d"},
2660 /* Vector VLDRW unsigned, variant T7. */
2661 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2663 0xec101f00, 0xfe101f80,
2664 "vldrw%v.u32\t%13-15,22Q, %d"},
2667 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2669 0xef000640, 0xef811f51,
2670 "vmax%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2673 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2675 0xee330e81, 0xffb31fd1,
2676 "vmaxa%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2678 /* Vector VMAXNM floating point. */
2679 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2681 0xff000f50, 0xffa11f51,
2682 "vmaxnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2684 /* Vector VMAXNMA floating point. */
2685 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2687 0xee3f0e81, 0xefbf1fd1,
2688 "vmaxnma%v.f%28s\t%13-15,22Q, %1-3,5Q"},
2690 /* Vector VMAXNMV floating point. */
2691 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2693 0xeeee0f00, 0xefff0fd1,
2694 "vmaxnmv%v.f%28s\t%12-15r, %1-3,5Q"},
2696 /* Vector VMAXNMAV floating point. */
2697 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2699 0xeeec0f00, 0xefff0fd1,
2700 "vmaxnmav%v.f%28s\t%12-15r, %1-3,5Q"},
2703 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2705 0xeee20f00, 0xeff30fd1,
2706 "vmaxv%v.%u%18-19s\t%12-15r, %1-3,5Q"},
2708 /* Vector VMAXAV. */
2709 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2711 0xeee00f00, 0xfff30fd1,
2712 "vmaxav%v.s%18-19s\t%12-15r, %1-3,5Q"},
2715 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2717 0xef000650, 0xef811f51,
2718 "vmin%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2721 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2723 0xee331e81, 0xffb31fd1,
2724 "vmina%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2726 /* Vector VMINNM floating point. */
2727 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2729 0xff200f50, 0xffa11f51,
2730 "vminnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2732 /* Vector VMINNMA floating point. */
2733 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2735 0xee3f1e81, 0xefbf1fd1,
2736 "vminnma%v.f%28s\t%13-15,22Q, %1-3,5Q"},
2738 /* Vector VMINNMV floating point. */
2739 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2741 0xeeee0f80, 0xefff0fd1,
2742 "vminnmv%v.f%28s\t%12-15r, %1-3,5Q"},
2744 /* Vector VMINNMAV floating point. */
2745 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2747 0xeeec0f80, 0xefff0fd1,
2748 "vminnmav%v.f%28s\t%12-15r, %1-3,5Q"},
2751 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2753 0xeee20f80, 0xeff30fd1,
2754 "vminv%v.%u%18-19s\t%12-15r, %1-3,5Q"},
2756 /* Vector VMINAV. */
2757 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2759 0xeee00f80, 0xfff30fd1,
2760 "vminav%v.s%18-19s\t%12-15r, %1-3,5Q"},
2763 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2765 0xee010e40, 0xef811f70,
2766 "vmla%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2768 /* Vector VMLALDAV. Note must appear before VMLADAV due to instruction
2770 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2772 0xee801e00, 0xef801f51,
2773 "vmlaldav%5Ax%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2775 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2777 0xee800e00, 0xef801f51,
2778 "vmlalv%5A%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2780 /* Vector VMLAV T1 variant, same as VMLADAV but with X == 0. */
2781 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2783 0xeef00e00, 0xeff01f51,
2784 "vmlav%5A%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2786 /* Vector VMLAV T2 variant, same as VMLADAV but with X == 0. */
2787 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2789 0xeef00f00, 0xeff11f51,
2790 "vmlav%5A%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2792 /* Vector VMLADAV T1 variant. */
2793 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2795 0xeef01e00, 0xeff01f51,
2796 "vmladav%5Ax%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2798 /* Vector VMLADAV T2 variant. */
2799 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2801 0xeef01f00, 0xeff11f51,
2802 "vmladav%5Ax%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2805 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2807 0xee011e40, 0xef811f70,
2808 "vmlas%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2810 /* Vector VRMLSLDAVH. Note must appear before VMLSDAV due to instruction
2812 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2814 0xfe800e01, 0xff810f51,
2815 "vrmlsldavh%5A%X%v.s32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2817 /* Vector VMLSLDAV. Note must appear before VMLSDAV due to instruction
2819 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2821 0xee800e01, 0xff800f51,
2822 "vmlsldav%5A%X%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2824 /* Vector VMLSDAV T1 Variant. */
2825 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2827 0xeef00e01, 0xfff00f51,
2828 "vmlsdav%5A%X%v.s%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2830 /* Vector VMLSDAV T2 Variant. */
2831 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2833 0xfef00e01, 0xfff10f51,
2834 "vmlsdav%5A%X%v.s8\t%13-15l, %17-19,7Q, %1-3Q"},
2836 /* Vector VMOV between gpr and half precision register, op == 0. */
2837 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2839 0xee000910, 0xfff00f7f,
2840 "vmov.f16\t%7,16-19F, %12-15r"},
2842 /* Vector VMOV between gpr and half precision register, op == 1. */
2843 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2845 0xee100910, 0xfff00f7f,
2846 "vmov.f16\t%12-15r, %7,16-19F"},
2848 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2849 MVE_VMOV_GP_TO_VEC_LANE
,
2850 0xee000b10, 0xff900f1f,
2851 "vmov%c.%5-6,21-22s\t%17-19,7Q[%N], %12-15r"},
2853 /* Vector VORR immediate to vector.
2854 NOTE: MVE_VORR_IMM must appear in the table
2855 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2856 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2858 0xef800050, 0xefb810f0,
2859 "vorr%v.i%8-11s\t%13-15,22Q, %E"},
2861 /* Vector VQSHL T2 Variant.
2862 NOTE: MVE_VQSHL_T2 must appear in the table before
2863 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2864 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2866 0xef800750, 0xef801fd1,
2867 "vqshl%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2869 /* Vector VQSHLU T3 Variant
2870 NOTE: MVE_VQSHL_T2 must appear in the table before
2871 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2873 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2875 0xff800650, 0xff801fd1,
2876 "vqshlu%v.s%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2879 NOTE: MVE_VRSHR must appear in the table before
2880 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2881 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2883 0xef800250, 0xef801fd1,
2884 "vrshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2887 NOTE: MVE_VSHL must appear in the table before
2888 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2889 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2891 0xef800550, 0xff801fd1,
2892 "vshl%v.i%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2895 NOTE: MVE_VSHR must appear in the table before
2896 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2897 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2899 0xef800050, 0xef801fd1,
2900 "vshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2903 NOTE: MVE_VSLI must appear in the table before
2904 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2905 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2907 0xff800550, 0xff801fd1,
2908 "vsli%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2911 NOTE: MVE_VSRI must appear in the table before
2912 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2913 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2915 0xff800450, 0xff801fd1,
2916 "vsri%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2918 /* Vector VMOV immediate to vector,
2919 undefinded for cmode == 1111 */
2920 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2921 MVE_VMVN_IMM
, 0xef800f70, 0xefb81ff0, UNDEFINED_INSTRUCTION
},
2923 /* Vector VMOV immediate to vector,
2925 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2926 MVE_VMOV_IMM_TO_VEC
, 0xef800d50, 0xefb81fd0,
2927 "vmov%v.%5,8-11s\t%13-15,22Q, %E"},
2929 /* Vector VMOV immediate to vector. */
2930 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2931 MVE_VMOV_IMM_TO_VEC
,
2932 0xef800050, 0xefb810d0,
2933 "vmov%v.%5,8-11s\t%13-15,22Q, %E"},
2935 /* Vector VMOV two 32-bit lanes to two gprs, idx = 0. */
2936 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2937 MVE_VMOV2_VEC_LANE_TO_GP
,
2938 0xec000f00, 0xffb01ff0,
2939 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[2], %13-15,22Q[0]"},
2941 /* Vector VMOV two 32-bit lanes to two gprs, idx = 1. */
2942 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2943 MVE_VMOV2_VEC_LANE_TO_GP
,
2944 0xec000f10, 0xffb01ff0,
2945 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[3], %13-15,22Q[1]"},
2947 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 0. */
2948 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2949 MVE_VMOV2_GP_TO_VEC_LANE
,
2950 0xec100f00, 0xffb01ff0,
2951 "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
2953 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 1. */
2954 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2955 MVE_VMOV2_GP_TO_VEC_LANE
,
2956 0xec100f10, 0xffb01ff0,
2957 "vmov%c\t%13-15,22Q[3], %13-15,22Q[1], %0-3r, %16-19r"},
2959 /* Vector VMOV Vector lane to gpr. */
2960 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2961 MVE_VMOV_VEC_LANE_TO_GP
,
2962 0xee100b10, 0xff100f1f,
2963 "vmov%c.%u%5-6,21-22s\t%12-15r, %17-19,7Q[%N]"},
2965 /* Vector VSHLL T1 Variant. Note: VSHLL T1 must appear before MVE_VMOVL due
2966 to instruction opcode aliasing. */
2967 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2969 0xeea00f40, 0xefa00fd1,
2970 "vshll%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2972 /* Vector VMOVL long. */
2973 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2975 0xeea00f40, 0xefa70fd1,
2976 "vmovl%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q"},
2978 /* Vector VMOV and narrow. */
2979 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2981 0xfe310e81, 0xffb30fd1,
2982 "vmovn%T%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2984 /* Floating point move extract. */
2985 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2987 0xfeb00a40, 0xffbf0fd0,
2988 "vmovx.f16\t%22,12-15F, %5,0-3F"},
2990 /* Vector VMUL floating-point T1 variant. */
2991 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2993 0xff000d50, 0xffa11f51,
2994 "vmul%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2996 /* Vector VMUL floating-point T2 variant. */
2997 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2999 0xee310e60, 0xefb11f70,
3000 "vmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3002 /* Vector VMUL T1 variant. */
3003 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3005 0xef000950, 0xff811f51,
3006 "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3008 /* Vector VMUL T2 variant. */
3009 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3011 0xee011e60, 0xff811f70,
3012 "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3015 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3017 0xee010e01, 0xef811f51,
3018 "vmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3020 /* Vector VRMULH. */
3021 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3023 0xee011e01, 0xef811f51,
3024 "vrmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3026 /* Vector VMULL integer. */
3027 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3029 0xee010e00, 0xef810f51,
3030 "vmull%T%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3032 /* Vector VMULL polynomial. */
3033 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3035 0xee310e00, 0xefb10f51,
3036 "vmull%T%v.%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3038 /* Vector VMVN immediate to vector. */
3039 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3041 0xef800070, 0xefb810f0,
3042 "vmvn%v.i%8-11s\t%13-15,22Q, %E"},
3044 /* Vector VMVN register. */
3045 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3047 0xffb005c0, 0xffbf1fd1,
3048 "vmvn%v\t%13-15,22Q, %1-3,5Q"},
3050 /* Vector VNEG floating point. */
3051 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
3053 0xffb107c0, 0xffb31fd1,
3054 "vneg%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
3057 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3059 0xffb103c0, 0xffb31fd1,
3060 "vneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
3062 /* Vector VORN, vector bitwise or not. */
3063 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3065 0xef300150, 0xffb11f51,
3066 "vorn%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3068 /* Vector VORR register. */
3069 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3071 0xef200150, 0xffb11f51,
3072 "vorr%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3074 /* Vector VMOV, vector to vector move. While decoding MVE_VORR_REG if
3075 "Qm==Qn", VORR should replaced by its alias VMOV. For that to happen
3076 MVE_VMOV_VEC_TO_VEC need to placed after MVE_VORR_REG in this mve_opcodes
3079 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3080 MVE_VMOV_VEC_TO_VEC
,
3081 0xef200150, 0xffb11f51,
3082 "vmov%v\t%13-15,22Q, %17-19,7Q"},
3084 /* Vector VQDMULL T1 variant. */
3085 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3087 0xee300f01, 0xefb10f51,
3088 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3091 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3093 0xfe310f4d, 0xffffffff,
3097 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3099 0xfe310f01, 0xffb11f51,
3100 "vpsel%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3103 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3105 0xffb00740, 0xffb31fd1,
3106 "vqabs%v.s%18-19s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3108 /* Vector VQADD T1 variant. */
3109 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3111 0xef000050, 0xef811f51,
3112 "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3114 /* Vector VQADD T2 variant. */
3115 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3117 0xee000f60, 0xef811f70,
3118 "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3120 /* Vector VQDMULL T2 variant. */
3121 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3123 0xee300f60, 0xefb10f70,
3124 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3126 /* Vector VQMOVN. */
3127 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3129 0xee330e01, 0xefb30fd1,
3130 "vqmovn%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q"},
3132 /* Vector VQMOVUN. */
3133 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3135 0xee310e81, 0xffb30fd1,
3136 "vqmovun%T%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
3138 /* Vector VQDMLADH. */
3139 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3141 0xee000e00, 0xff810f51,
3142 "vqdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3144 /* Vector VQRDMLADH. */
3145 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3147 0xee000e01, 0xff810f51,
3148 "vqrdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3150 /* Vector VQDMLAH. */
3151 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3153 0xee000e60, 0xff811f70,
3154 "vqdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3156 /* Vector VQRDMLAH. */
3157 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3159 0xee000e40, 0xff811f70,
3160 "vqrdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3162 /* Vector VQDMLASH. */
3163 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3165 0xee001e60, 0xff811f70,
3166 "vqdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3168 /* Vector VQRDMLASH. */
3169 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3171 0xee001e40, 0xff811f70,
3172 "vqrdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3174 /* Vector VQDMLSDH. */
3175 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3177 0xfe000e00, 0xff810f51,
3178 "vqdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3180 /* Vector VQRDMLSDH. */
3181 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3183 0xfe000e01, 0xff810f51,
3184 "vqrdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3186 /* Vector VQDMULH T1 variant. */
3187 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3189 0xef000b40, 0xff811f51,
3190 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3192 /* Vector VQRDMULH T2 variant. */
3193 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3195 0xff000b40, 0xff811f51,
3196 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3198 /* Vector VQDMULH T3 variant. */
3199 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3201 0xee010e60, 0xff811f70,
3202 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3204 /* Vector VQRDMULH T4 variant. */
3205 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3207 0xfe010e60, 0xff811f70,
3208 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3211 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3213 0xffb007c0, 0xffb31fd1,
3214 "vqneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
3216 /* Vector VQRSHL T1 variant. */
3217 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3219 0xef000550, 0xef811f51,
3220 "vqrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3222 /* Vector VQRSHL T2 variant. */
3223 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3225 0xee331ee0, 0xefb31ff0,
3226 "vqrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3228 /* Vector VQRSHRN. */
3229 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3231 0xee800f41, 0xefa00fd1,
3232 "vqrshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3234 /* Vector VQRSHRUN. */
3235 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3237 0xfe800fc0, 0xffa00fd1,
3238 "vqrshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3240 /* Vector VQSHL T1 Variant. */
3241 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3243 0xee311ee0, 0xefb31ff0,
3244 "vqshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3246 /* Vector VQSHL T4 Variant. */
3247 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3249 0xef000450, 0xef811f51,
3250 "vqshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3252 /* Vector VQSHRN. */
3253 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3255 0xee800f40, 0xefa00fd1,
3256 "vqshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3258 /* Vector VQSHRUN. */
3259 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3261 0xee800fc0, 0xffa00fd1,
3262 "vqshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3264 /* Vector VQSUB T1 Variant. */
3265 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3267 0xef000250, 0xef811f51,
3268 "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3270 /* Vector VQSUB T2 Variant. */
3271 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3273 0xee001f60, 0xef811f70,
3274 "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3276 /* Vector VREV16. */
3277 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3279 0xffb00140, 0xffb31fd1,
3280 "vrev16%v.8\t%13-15,22Q, %1-3,5Q"},
3282 /* Vector VREV32. */
3283 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3285 0xffb000c0, 0xffb31fd1,
3286 "vrev32%v.%18-19s\t%13-15,22Q, %1-3,5Q"},
3288 /* Vector VREV64. */
3289 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3291 0xffb00040, 0xffb31fd1,
3292 "vrev64%v.%18-19s\t%13-15,22Q, %1-3,5Q"},
3294 /* Vector VRINT floating point. */
3295 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
3297 0xffb20440, 0xffb31c51,
3298 "vrint%m%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
3300 /* Vector VRMLALDAVH. */
3301 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3303 0xee800f00, 0xef811f51,
3304 "vrmlalvh%5A%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
3306 /* Vector VRMLALDAVH. */
3307 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3309 0xee801f00, 0xef811f51,
3310 "vrmlaldavh%5Ax%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
3312 /* Vector VRSHL T1 Variant. */
3313 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3315 0xef000540, 0xef811f51,
3316 "vrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3318 /* Vector VRSHL T2 Variant. */
3319 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3321 0xee331e60, 0xefb31ff0,
3322 "vrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3324 /* Vector VRSHRN. */
3325 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3327 0xfe800fc1, 0xffa00fd1,
3328 "vrshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3331 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3333 0xfe300f00, 0xffb10f51,
3334 "vsbc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3336 /* Vector VSHL T2 Variant. */
3337 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3339 0xee311e60, 0xefb31ff0,
3340 "vshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3342 /* Vector VSHL T3 Variant. */
3343 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3345 0xef000440, 0xef811f51,
3346 "vshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3349 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3351 0xeea00fc0, 0xffa01ff0,
3352 "vshlc%v\t%13-15,22Q, %0-3r, #%16-20d"},
3354 /* Vector VSHLL T2 Variant. */
3355 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3357 0xee310e01, 0xefb30fd1,
3358 "vshll%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q, #%18-19d"},
3361 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3363 0xee800fc1, 0xffa00fd1,
3364 "vshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3366 /* Vector VST2 no writeback. */
3367 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3369 0xfc801e00, 0xffb01e5f,
3370 "vst2%5d.%7-8s\t%B, [%16-19r]"},
3372 /* Vector VST2 writeback. */
3373 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3375 0xfca01e00, 0xffb01e5f,
3376 "vst2%5d.%7-8s\t%B, [%16-19r]!"},
3378 /* Vector VST4 no writeback. */
3379 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3381 0xfc801e01, 0xffb01e1f,
3382 "vst4%5-6d.%7-8s\t%B, [%16-19r]"},
3384 /* Vector VST4 writeback. */
3385 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3387 0xfca01e01, 0xffb01e1f,
3388 "vst4%5-6d.%7-8s\t%B, [%16-19r]!"},
3390 /* Vector VSTRB scatter store, T1 variant. */
3391 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3392 MVE_VSTRB_SCATTER_T1
,
3393 0xec800e00, 0xffb01e50,
3394 "vstrb%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
3396 /* Vector VSTRH scatter store, T2 variant. */
3397 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3398 MVE_VSTRH_SCATTER_T2
,
3399 0xec800e10, 0xffb01e50,
3400 "vstrh%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3402 /* Vector VSTRW scatter store, T3 variant. */
3403 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3404 MVE_VSTRW_SCATTER_T3
,
3405 0xec800e40, 0xffb01e50,
3406 "vstrw%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3408 /* Vector VSTRD scatter store, T4 variant. */
3409 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3410 MVE_VSTRD_SCATTER_T4
,
3411 0xec800fd0, 0xffb01fd0,
3412 "vstrd%v.64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3414 /* Vector VSTRW scatter store, T5 variant. */
3415 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3416 MVE_VSTRW_SCATTER_T5
,
3417 0xfd001e00, 0xff111f00,
3418 "vstrw%v.32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
3420 /* Vector VSTRD scatter store, T6 variant. */
3421 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3422 MVE_VSTRD_SCATTER_T6
,
3423 0xfd001f00, 0xff111f00,
3424 "vstrd%v.64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
3427 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3429 0xec000e00, 0xfe581e00,
3430 "vstrb%v.%7-8s\t%13-15Q, %d"},
3433 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3435 0xec080e00, 0xfe581e00,
3436 "vstrh%v.%7-8s\t%13-15Q, %d"},
3438 /* Vector VSTRB variant T5. */
3439 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3441 0xec001e00, 0xfe101f80,
3442 "vstrb%v.8\t%13-15,22Q, %d"},
3444 /* Vector VSTRH variant T6. */
3445 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3447 0xec001e80, 0xfe101f80,
3448 "vstrh%v.16\t%13-15,22Q, %d"},
3450 /* Vector VSTRW variant T7. */
3451 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3453 0xec001f00, 0xfe101f80,
3454 "vstrw%v.32\t%13-15,22Q, %d"},
3456 /* Vector VSUB floating point T1 variant. */
3457 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
3459 0xef200d40, 0xffa11f51,
3460 "vsub%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3462 /* Vector VSUB floating point T2 variant. */
3463 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
3465 0xee301f40, 0xefb11f70,
3466 "vsub%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3468 /* Vector VSUB T1 variant. */
3469 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3471 0xff000840, 0xff811f51,
3472 "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3474 /* Vector VSUB T2 variant. */
3475 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3477 0xee011f40, 0xff811f70,
3478 "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3480 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3482 0xea50012f, 0xfff1813f,
3483 "asrl%c\t%17-19l, %9-11h, %j"},
3485 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3487 0xea50012d, 0xfff101ff,
3488 "asrl%c\t%17-19l, %9-11h, %12-15S"},
3490 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3492 0xea50010f, 0xfff1813f,
3493 "lsll%c\t%17-19l, %9-11h, %j"},
3495 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3497 0xea50010d, 0xfff101ff,
3498 "lsll%c\t%17-19l, %9-11h, %12-15S"},
3500 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3502 0xea50011f, 0xfff1813f,
3503 "lsrl%c\t%17-19l, %9-11h, %j"},
3505 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3507 0xea51012d, 0xfff1017f,
3508 "sqrshrl%c\t%17-19l, %9-11h, %k, %12-15S"},
3510 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3512 0xea500f2d, 0xfff00fff,
3513 "sqrshr%c\t%16-19S, %12-15S"},
3515 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3517 0xea51013f, 0xfff1813f,
3518 "sqshll%c\t%17-19l, %9-11h, %j"},
3520 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3522 0xea500f3f, 0xfff08f3f,
3523 "sqshl%c\t%16-19S, %j"},
3525 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3527 0xea51012f, 0xfff1813f,
3528 "srshrl%c\t%17-19l, %9-11h, %j"},
3530 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3532 0xea500f2f, 0xfff08f3f,
3533 "srshr%c\t%16-19S, %j"},
3535 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3537 0xea51010d, 0xfff1017f,
3538 "uqrshll%c\t%17-19l, %9-11h, %k, %12-15S"},
3540 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3542 0xea500f0d, 0xfff00fff,
3543 "uqrshl%c\t%16-19S, %12-15S"},
3545 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3547 0xea51010f, 0xfff1813f,
3548 "uqshll%c\t%17-19l, %9-11h, %j"},
3550 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3552 0xea500f0f, 0xfff08f3f,
3553 "uqshl%c\t%16-19S, %j"},
3555 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3557 0xea51011f, 0xfff1813f,
3558 "urshrl%c\t%17-19l, %9-11h, %j"},
3560 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3562 0xea500f1f, 0xfff08f3f,
3563 "urshr%c\t%16-19S, %j"},
3565 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3567 0xea509000, 0xfff0f000,
3568 "csinc\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3570 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3572 0xea50a000, 0xfff0f000,
3573 "csinv\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3575 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3577 0xea5f900f, 0xfffff00f,
3578 "cset\t%8-11S, %4-7C"},
3580 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3582 0xea5fa00f, 0xfffff00f,
3583 "csetm\t%8-11S, %4-7C"},
3585 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3587 0xea508000, 0xfff0f000,
3588 "csel\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3590 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3592 0xea50b000, 0xfff0f000,
3593 "csneg\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3595 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3597 0xea509000, 0xfff0f000,
3598 "cinc\t%8-11S, %16-19Z, %4-7C"},
3600 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3602 0xea50a000, 0xfff0f000,
3603 "cinv\t%8-11S, %16-19Z, %4-7C"},
3605 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3607 0xea50b000, 0xfff0f000,
3608 "cneg\t%8-11S, %16-19Z, %4-7C"},
3610 {ARM_FEATURE_CORE_LOW (0),
3612 0x00000000, 0x00000000, 0}
3615 /* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
3616 ordered: they must be searched linearly from the top to obtain a correct
3619 /* print_insn_arm recognizes the following format control codes:
3623 %a print address for ldr/str instruction
3624 %s print address for ldr/str halfword/signextend instruction
3625 %S like %s but allow UNPREDICTABLE addressing
3626 %b print branch destination
3627 %c print condition code (always bits 28-31)
3628 %m print register mask for ldm/stm instruction
3629 %o print operand2 (immediate or register + shift)
3630 %p print 'p' iff bits 12-15 are 15
3631 %t print 't' iff bit 21 set and bit 24 clear
3632 %B print arm BLX(1) destination
3633 %C print the PSR sub type.
3634 %U print barrier type.
3635 %P print address for pli instruction.
3637 %<bitfield>r print as an ARM register
3638 %<bitfield>T print as an ARM register + 1
3639 %<bitfield>R as %r but r15 is UNPREDICTABLE
3640 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
3641 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
3642 %<bitfield>d print the bitfield in decimal
3643 %<bitfield>W print the bitfield plus one in decimal
3644 %<bitfield>x print the bitfield in hex
3645 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
3647 %<bitfield>'c print specified char iff bitfield is all ones
3648 %<bitfield>`c print specified char iff bitfield is all zeroes
3649 %<bitfield>?ab... select from array of values in big endian order
3651 %e print arm SMI operand (bits 0..7,8..19).
3652 %E print the LSB and WIDTH fields of a BFI or BFC instruction.
3653 %V print the 16-bit immediate field of a MOVT or MOVW instruction.
3654 %R print the SPSR/CPSR or banked register of an MRS. */
3656 static const struct opcode32 arm_opcodes
[] =
3658 /* ARM instructions. */
3659 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3660 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
3661 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3662 0xe7f000f0, 0xfff000f0, "udf\t#%e"},
3664 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
),
3665 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
3666 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
3667 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
3668 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
3669 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3670 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
),
3671 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
3672 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
),
3673 0x00800090, 0x0fa000f0,
3674 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3675 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
),
3676 0x00a00090, 0x0fa000f0,
3677 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3679 /* V8.2 RAS extension instructions. */
3680 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
3681 0xe320f010, 0xffffffff, "esb"},
3683 /* V8-R instructions. */
3684 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8R
),
3685 0xf57ff04c, 0xffffffff, "dfb"},
3687 /* V8 instructions. */
3688 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3689 0x0320f005, 0x0fffffff, "sevl"},
3690 /* Defined in V8 but is in NOP space so available to all arch. */
3691 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3692 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
3693 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
),
3694 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
3695 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3696 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
3697 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3698 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
3699 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3700 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
3701 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3702 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
3703 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3704 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
3705 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3706 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
3707 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3708 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
3709 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3710 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
3711 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3712 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
3713 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3714 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
3715 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3716 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
3717 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3718 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
3719 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3720 0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
3721 /* CRC32 instructions. */
3722 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
3723 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
3724 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
3725 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
3726 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
3727 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
3728 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
3729 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
3730 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
3731 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
3732 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
3733 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
3735 /* Privileged Access Never extension instructions. */
3736 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
3737 0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
3739 /* Virtualization Extension instructions. */
3740 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
), 0x0160006e, 0x0fffffff, "eret%c"},
3741 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
3743 /* Integer Divide Extension instructions. */
3744 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
3745 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
3746 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
3747 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
3749 /* MP Extension instructions. */
3750 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP
), 0xf410f000, 0xfc70f000, "pldw\t%a"},
3752 /* Speculation Barriers. */
3753 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
), 0xe320f014, 0xffffffff, "csdb"},
3754 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
), 0xf57ff040, 0xffffffff, "ssbb"},
3755 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
), 0xf57ff044, 0xffffffff, "pssbb"},
3757 /* V7 instructions. */
3758 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf450f000, 0xfd70f000, "pli\t%P"},
3759 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
3760 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
3761 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
3762 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
3763 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
3764 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf57ff060, 0xfffffff0, "isb\t%U"},
3765 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
),
3766 0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
3768 /* ARM V6T2 instructions. */
3769 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3770 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
3771 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3772 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
3773 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3774 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3775 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3776 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
3778 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3779 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION
},
3780 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3781 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
3783 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3784 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
3785 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3786 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
3787 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3788 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
3789 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3790 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
3792 /* ARM Security extension instructions. */
3793 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
3794 0x01600070, 0x0ff000f0, "smc%c\t%e"},
3796 /* ARM V6K instructions. */
3797 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3798 0xf57ff01f, 0xffffffff, "clrex"},
3799 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3800 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
3801 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3802 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
3803 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3804 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
3805 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3806 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
3807 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3808 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
3809 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3810 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
3812 /* ARMv8.5-A instructions. */
3813 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
), 0xf57ff070, 0xffffffff, "sb"},
3815 /* ARM V6K NOP hints. */
3816 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3817 0x0320f001, 0x0fffffff, "yield%c"},
3818 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3819 0x0320f002, 0x0fffffff, "wfe%c"},
3820 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3821 0x0320f003, 0x0fffffff, "wfi%c"},
3822 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3823 0x0320f004, 0x0fffffff, "sev%c"},
3824 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3825 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
3827 /* ARM V6 instructions. */
3828 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3829 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
3830 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3831 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
3832 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3833 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
3834 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3835 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
3836 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3837 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
3838 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3839 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
3840 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3841 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
3842 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3843 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
3844 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3845 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
3846 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3847 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
3848 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3849 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
3850 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3851 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
3852 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3853 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
3854 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3855 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
3856 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3857 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
3858 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3859 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
3860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3861 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
3862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3863 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
3864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3865 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
3866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3867 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
3868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3869 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
3870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3871 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
3872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3873 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
3874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3875 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
3876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3877 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
3878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3879 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
3880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3881 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
3882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3883 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
3884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3885 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
3886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3887 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
3888 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3889 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
3890 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3891 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
3892 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3893 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
3894 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3895 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
3896 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3897 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
3898 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3899 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
3900 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3901 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
3902 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3903 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
3904 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3905 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
3906 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3907 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
3908 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3909 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
3910 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3911 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
3912 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3913 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
3914 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3915 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
3916 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3917 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
3918 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3919 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
3920 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3921 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
3922 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3923 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
3924 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3925 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
3926 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3927 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
3928 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3929 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
3930 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3931 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
3932 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3933 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
3934 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3935 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
3936 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3937 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
3938 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3939 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
3940 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3941 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
3942 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3943 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
3944 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3945 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
3946 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3947 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
3948 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3949 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
3950 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3951 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
3952 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3953 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
3954 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3955 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
3956 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3957 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
3958 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3959 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
3960 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3961 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
3962 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3963 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
3964 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3965 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
3966 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3967 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
3968 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3969 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
3970 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3971 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
3972 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3973 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
3974 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3975 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
3976 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3977 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
3978 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3979 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3980 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3981 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3982 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3983 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3984 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3985 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
3986 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3987 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3988 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3989 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3990 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3991 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3992 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3993 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
3994 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3995 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3996 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3997 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3998 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3999 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
4000 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4001 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
4002 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4003 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
4004 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4005 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
4006 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4007 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
4008 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4009 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
4010 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4011 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
4012 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4013 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
4014 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4015 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
4016 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4017 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
4018 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4019 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
4020 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4021 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
4022 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4023 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
4024 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4025 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
4026 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4027 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
4028 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4029 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
4030 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4031 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
4032 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4033 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4034 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4035 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4036 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4037 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4038 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4039 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4040 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4041 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
4042 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4043 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4044 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4045 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4046 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4047 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
4048 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4049 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
4050 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4051 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
4052 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4053 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
4054 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4055 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
4056 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4057 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
4058 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4059 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
4060 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4061 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
4062 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4063 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4064 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4065 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
4066 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4067 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
4068 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4069 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
4070 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4071 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
4073 /* V5J instruction. */
4074 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
),
4075 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
4077 /* V5 Instructions. */
4078 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
4079 0xe1200070, 0xfff000f0,
4080 "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
4081 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
4082 0xfa000000, 0xfe000000, "blx\t%B"},
4083 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
4084 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
4085 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
4086 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
4088 /* V5E "El Segundo" Instructions. */
4089 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
4090 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
4091 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
4092 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
4093 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
4094 0xf450f000, 0xfc70f000, "pld\t%a"},
4095 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4096 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4097 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4098 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4099 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4100 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4101 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4102 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
4104 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4105 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4106 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4107 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
4109 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4110 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4111 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4112 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4113 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4114 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4115 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4116 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4118 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4119 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
4120 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4121 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
4122 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4123 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
4124 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4125 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
4127 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4128 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
4129 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4130 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
4132 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4133 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"},
4134 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4135 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
4136 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4137 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"},
4138 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4139 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
4141 /* ARM Instructions. */
4142 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4143 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
4145 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4146 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
4147 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4148 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
4149 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4150 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
4151 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4152 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
4153 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4154 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
4155 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4156 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
4158 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4159 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
4160 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4161 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
4162 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4163 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
4164 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4165 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
4167 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4168 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION
},
4169 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4170 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
4171 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4172 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION
},
4173 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4174 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
4176 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4177 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
4178 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4179 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
4180 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4181 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
4183 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4184 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
4185 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4186 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
4187 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4188 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
4190 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4191 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
4192 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4193 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
4194 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4195 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
4197 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4198 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
4199 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4200 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
4201 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4202 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
4204 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4205 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
4206 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4207 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
4208 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4209 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
4211 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4212 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
4213 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4214 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
4215 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4216 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
4218 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4219 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
4220 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4221 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
4222 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4223 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
4225 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4226 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
4227 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4228 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
4229 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4230 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
4232 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
4233 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
4234 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
),
4235 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
4236 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
),
4237 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
4239 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4240 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
4241 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4242 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
4243 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4244 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
4246 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4247 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
4248 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4249 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
4250 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4251 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
4253 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4254 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
4255 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4256 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
4257 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4258 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
4260 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4261 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
4262 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4263 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
4264 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4265 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
4267 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4268 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
4269 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4270 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
4271 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4272 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
4274 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4275 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
4276 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4277 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
4278 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4279 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
4280 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4281 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
4282 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4283 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
4284 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4285 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
4286 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4287 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
4289 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4290 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
4291 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4292 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
4293 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4294 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
4296 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4297 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
4298 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4299 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
4300 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4301 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
4303 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4304 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION
},
4305 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4306 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
4308 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4309 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
4311 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4312 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
4313 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4314 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
4316 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4317 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4318 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4319 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4320 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4321 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4322 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4323 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4324 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4325 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4326 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4327 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4328 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4329 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4330 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4331 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4332 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4333 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4334 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4335 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4336 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4337 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4338 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4339 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4340 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4341 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4342 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4343 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4344 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4345 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4346 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4347 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4348 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4349 0x092d0000, 0x0fff0000, "push%c\t%m"},
4350 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4351 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
4352 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4353 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
4355 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4356 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4357 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4358 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4359 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4360 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4361 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4362 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4363 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4364 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4365 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4366 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4367 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4368 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4369 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4370 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4371 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4372 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4373 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4374 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4375 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4376 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4377 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4378 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4379 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4380 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4381 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4382 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4383 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4384 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4385 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4386 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4387 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4388 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
4389 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4390 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
4391 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4392 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
4394 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4395 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
4396 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4397 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
4400 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
),
4401 0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION
},
4402 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4403 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION
},
4404 {ARM_FEATURE_CORE_LOW (0),
4405 0x00000000, 0x00000000, 0}
4408 /* print_insn_thumb16 recognizes the following format control codes:
4410 %S print Thumb register (bits 3..5 as high number if bit 6 set)
4411 %D print Thumb register (bits 0..2 as high number if bit 7 set)
4412 %<bitfield>I print bitfield as a signed decimal
4413 (top bit of range being the sign bit)
4414 %N print Thumb register mask (with LR)
4415 %O print Thumb register mask (with PC)
4416 %M print Thumb register mask
4417 %b print CZB's 6-bit unsigned branch destination
4418 %s print Thumb right-shift immediate (6..10; 0 == 32).
4419 %c print the condition code
4420 %C print the condition code, or "s" if not conditional
4421 %x print warning if conditional an not at end of IT block"
4422 %X print "\t; unpredictable <IT:code>" if conditional
4423 %I print IT instruction suffix and operands
4424 %W print Thumb Writeback indicator for LDMIA
4425 %<bitfield>r print bitfield as an ARM register
4426 %<bitfield>d print bitfield as a decimal
4427 %<bitfield>H print (bitfield * 2) as a decimal
4428 %<bitfield>W print (bitfield * 4) as a decimal
4429 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
4430 %<bitfield>B print Thumb branch destination (signed displacement)
4431 %<bitfield>c print bitfield as a condition code
4432 %<bitnum>'c print specified char iff bit is one
4433 %<bitnum>?ab print a if bit is one else print b. */
4435 static const struct opcode16 thumb_opcodes
[] =
4437 /* Thumb instructions. */
4439 /* ARMv8-M Security Extensions instructions. */
4440 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
), 0x4784, 0xff87, "blxns\t%3-6r"},
4441 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
), 0x4704, 0xff87, "bxns\t%3-6r"},
4443 /* ARM V8 instructions. */
4444 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xbf50, 0xffff, "sevl%c"},
4445 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xba80, 0xffc0, "hlt\t%0-5x"},
4446 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
), 0xb610, 0xfff7, "setpan\t#%3-3d"},
4448 /* ARM V6K no-argument instructions. */
4449 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf00, 0xffff, "nop%c"},
4450 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf10, 0xffff, "yield%c"},
4451 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf20, 0xffff, "wfe%c"},
4452 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf30, 0xffff, "wfi%c"},
4453 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf40, 0xffff, "sev%c"},
4454 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
4456 /* ARM V6T2 instructions. */
4457 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4458 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
4459 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4460 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
4461 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xbf00, 0xff00, "it%I%X"},
4464 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
4465 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
4466 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
4467 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
4468 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
4469 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
4470 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb650, 0xfff7, "setend\t%3?ble%X"},
4471 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
4472 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
4473 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
4474 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
4476 /* ARM V5 ISA extends Thumb. */
4477 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
),
4478 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
4479 /* This is BLX(2). BLX(1) is a 32-bit instruction. */
4480 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
),
4481 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
4482 /* ARM V4T ISA (Thumb v1). */
4483 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4484 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
4486 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
4487 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
4488 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
4489 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
4490 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
4491 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
4492 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
4493 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
4494 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
4495 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
4496 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
4497 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
4498 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
4499 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
4500 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
4501 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
4503 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
4504 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
4506 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4700, 0xFF80, "bx%c\t%S%x"},
4507 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4400, 0xFF00, "add%c\t%D, %S"},
4508 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
4509 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4600, 0xFF00, "mov%c\t%D, %S"},
4511 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xB400, 0xFE00, "push%c\t%N"},
4512 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xBC00, 0xFE00, "pop%c\t%O"},
4514 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4515 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
4516 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4517 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
4518 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4519 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
4520 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4521 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
4523 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4524 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
4525 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4526 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
4527 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4528 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
4530 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4531 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
4532 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4533 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
4535 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
4536 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4537 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
4538 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
4539 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
4541 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
4542 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
4543 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
4544 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
4546 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
4547 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4549 "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
4551 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4552 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
4553 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4554 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
4555 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4556 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
4557 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4558 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
4560 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4561 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
4562 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4563 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
4565 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4566 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
4567 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4568 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
4570 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4571 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
4572 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4573 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
4575 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
4576 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
4578 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
4580 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
4581 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION
},
4582 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
4584 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
4586 /* The E800 .. FFFF range is unconditionally redirected to the
4587 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
4588 are processed via that table. Thus, we can never encounter a
4589 bare "second half of BL/BLX(1)" instruction here. */
4590 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
), 0x0000, 0x0000, UNDEFINED_INSTRUCTION
},
4591 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
4594 /* Thumb32 opcodes use the same table structure as the ARM opcodes.
4595 We adopt the convention that hw1 is the high 16 bits of .value and
4596 .mask, hw2 the low 16 bits.
4598 print_insn_thumb32 recognizes the following format control codes:
4602 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
4603 %M print a modified 12-bit immediate (same location)
4604 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
4605 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
4606 %H print a 16-bit immediate from hw2[3:0],hw1[11:0]
4607 %S print a possibly-shifted Rm
4609 %L print address for a ldrd/strd instruction
4610 %a print the address of a plain load/store
4611 %w print the width and signedness of a core load/store
4612 %m print register mask for ldm/stm
4613 %n print register mask for clrm
4615 %E print the lsb and width fields of a bfc/bfi instruction
4616 %F print the lsb and width fields of a sbfx/ubfx instruction
4617 %G print a fallback offset for Branch Future instructions
4618 %W print an offset for BF instruction
4619 %Y print an offset for BFL instruction
4620 %Z print an offset for BFCSEL instruction
4621 %Q print an offset for Low Overhead Loop instructions
4622 %P print an offset for Low Overhead Loop end instructions
4623 %b print a conditional branch offset
4624 %B print an unconditional branch offset
4625 %s print the shift field of an SSAT instruction
4626 %R print the rotation field of an SXT instruction
4627 %U print barrier type.
4628 %P print address for pli instruction.
4629 %c print the condition code
4630 %x print warning if conditional an not at end of IT block"
4631 %X print "\t; unpredictable <IT:code>" if conditional
4633 %<bitfield>d print bitfield in decimal
4634 %<bitfield>D print bitfield plus one in decimal
4635 %<bitfield>W print bitfield*4 in decimal
4636 %<bitfield>r print bitfield as an ARM register
4637 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
4638 %<bitfield>S as %<>r but r13 and r15 is UNPREDICTABLE
4639 %<bitfield>c print bitfield as a condition code
4641 %<bitfield>'c print specified char iff bitfield is all ones
4642 %<bitfield>`c print specified char iff bitfield is all zeroes
4643 %<bitfield>?ab... select from array of values in big endian order
4645 With one exception at the bottom (done because BL and BLX(1) need
4646 to come dead last), this table was machine-sorted first in
4647 decreasing order of number of bits set in the mask, then in
4648 increasing numeric order of mask, then in increasing numeric order
4649 of opcode. This order is not the clearest for a human reader, but
4650 is guaranteed never to catch a special-case bit pattern with a more
4651 general mask, which is important, because this instruction encoding
4652 makes heavy use of special-case bit patterns. */
4653 static const struct opcode32 thumb32_opcodes
[] =
4655 /* Arm v8.1-M Mainline Pointer Authentication and Branch Target
4656 Identification Extension. */
4657 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4658 0xf3af802d, 0xffffffff, "aut\tr12, lr, sp"},
4659 {ARM_FEATURE_CORE_HIGH_HIGH (ARM_EXT3_PACBTI
),
4660 0xfb500f00, 0xfff00ff0, "autg%c\t%12-15r, %16-19r, %0-3r"},
4661 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4662 0xf3af800f, 0xffffffff, "bti"},
4663 {ARM_FEATURE_CORE_HIGH_HIGH (ARM_EXT3_PACBTI
),
4664 0xfb500f10, 0xfff00ff0, "bxaut%c\t%12-15r, %16-19r, %0-3r"},
4665 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4666 0xf3af801d, 0xffffffff, "pac\tr12, lr, sp"},
4667 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4668 0xf3af800d, 0xffffffff, "pacbti\tr12, lr, sp"},
4669 {ARM_FEATURE_CORE_HIGH_HIGH (ARM_EXT3_PACBTI
),
4670 0xfb60f000, 0xfff0f0f0, "pacg%c\t%8-11r, %16-19r, %0-3r"},
4672 /* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions
4674 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4675 0xf00fe001, 0xffffffff, "lctp%c"},
4676 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4677 0xf02fc001, 0xfffff001, "le\t%P"},
4678 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4679 0xf00fc001, 0xfffff001, "le\tlr, %P"},
4680 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4681 0xf01fc001, 0xfffff001, "letp\tlr, %P"},
4682 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4683 0xf040c001, 0xfff0f001, "wls\tlr, %16-19S, %Q"},
4684 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4685 0xf000c001, 0xffc0f001, "wlstp.%20-21s\tlr, %16-19S, %Q"},
4686 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4687 0xf040e001, 0xfff0ffff, "dls\tlr, %16-19S"},
4688 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4689 0xf000e001, 0xffc0ffff, "dlstp.%20-21s\tlr, %16-19S"},
4691 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4692 0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
4693 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4694 0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"},
4695 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4696 0xf000c001, 0xf800f001, "bfl%c\t%G, %Y"},
4697 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4698 0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"},
4699 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4700 0xf000e001, 0xf840f001, "bfcsel\t%G, %Z, %18-21c"},
4702 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4703 0xe89f0000, 0xffff2000, "clrm%c\t%n"},
4705 /* ARMv8-M and ARMv8-M Security Extensions instructions. */
4706 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
), 0xe97fe97f, 0xffffffff, "sg"},
4707 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
),
4708 0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
4709 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
),
4710 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
4711 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
),
4712 0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
4713 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
),
4714 0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
4716 /* ARM V8.2 RAS extension instructions. */
4717 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
4718 0xf3af8010, 0xffffffff, "esb"},
4720 /* V8 instructions. */
4721 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4722 0xf3af8005, 0xffffffff, "sevl%c.w"},
4723 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4724 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
4725 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4726 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
4727 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4728 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
4729 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4730 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
4731 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4732 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
4733 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4734 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
4735 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4736 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
4737 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4738 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
4739 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4740 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
4741 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4742 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
4743 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4744 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
4745 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4746 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
4747 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4748 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
4749 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4750 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
4751 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4752 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
4754 /* V8-R instructions. */
4755 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8R
),
4756 0xf3bf8f4c, 0xffffffff, "dfb%c"},
4758 /* CRC32 instructions. */
4759 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
4760 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},
4761 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
4762 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"},
4763 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
4764 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"},
4765 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
4766 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"},
4767 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
4768 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"},
4769 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
4770 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
4772 /* Speculation Barriers. */
4773 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8014, 0xffffffff, "csdb"},
4774 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3bf8f40, 0xffffffff, "ssbb"},
4775 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3bf8f44, 0xffffffff, "pssbb"},
4777 /* V7 instructions. */
4778 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf910f000, 0xff70f000, "pli%c\t%a"},
4779 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
4780 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
4781 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
4782 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
4783 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
4784 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
4785 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
4786 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
4787 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
4788 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
4790 /* Virtualization Extension instructions. */
4791 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
4792 /* We skip ERET as that is SUBS pc, lr, #0. */
4794 /* MP Extension instructions. */
4795 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP
), 0xf830f000, 0xff70f000, "pldw%c\t%a"},
4797 /* Security extension instructions. */
4798 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
), 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
4800 /* ARMv8.5-A instructions. */
4801 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
), 0xf3bf8f70, 0xffffffff, "sb"},
4803 /* Instructions defined in the basic V6T2 set. */
4804 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8000, 0xffffffff, "nop%c.w"},
4805 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8001, 0xffffffff, "yield%c.w"},
4806 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8002, 0xffffffff, "wfe%c.w"},
4807 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8003, 0xffffffff, "wfi%c.w"},
4808 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8004, 0xffffffff, "sev%c.w"},
4809 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4810 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
4811 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
4813 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4814 0xf3bf8f2f, 0xffffffff, "clrex%c"},
4815 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4816 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
4817 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4818 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
4819 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4820 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
4821 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4822 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
4823 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4824 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
4825 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4826 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
4827 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4828 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
4829 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4830 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
4831 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4832 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
4833 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4834 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
4835 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4836 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
4837 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4838 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
4839 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4840 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
4841 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4842 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
4843 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4844 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
4845 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4846 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
4847 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4848 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
4849 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4850 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
4851 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4852 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
4853 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4854 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
4855 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4856 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
4857 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4858 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
4859 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4860 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
4861 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4862 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
4863 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4864 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
4865 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4866 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
4867 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4868 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
4869 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4870 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
4871 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4872 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
4873 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4874 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
4875 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4876 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
4877 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4878 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
4879 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4880 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
4881 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4882 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
4883 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4884 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
4885 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4886 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
4887 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4888 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
4889 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4890 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
4891 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4892 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
4893 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4894 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
4895 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4896 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
4897 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4898 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
4899 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4900 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
4901 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4902 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
4903 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4904 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
4905 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4906 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
4907 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4908 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
4909 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4910 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
4911 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4912 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
4913 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4914 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
4915 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4916 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
4917 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4918 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
4919 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4920 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
4921 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4922 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
4923 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4924 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
4925 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4926 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
4927 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4928 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
4929 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4930 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
4931 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4932 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
4933 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4934 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
4935 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4936 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
4937 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4938 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
4939 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4940 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
4941 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4942 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
4943 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4944 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
4945 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4946 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
4947 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4948 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
4949 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4950 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
4951 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4952 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
4953 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4954 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
4955 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4956 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
4957 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4958 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
4959 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4960 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
4961 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4962 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4963 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4964 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4965 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4966 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4967 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4968 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
4969 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4970 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
4971 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4972 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
4973 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4974 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
4975 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4976 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
4977 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4978 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4979 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4980 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
4981 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4982 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
4983 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4984 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4985 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4986 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4987 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4988 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4989 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4990 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4991 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4992 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4993 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4994 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4995 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4996 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4997 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4998 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
4999 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5000 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
5001 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5002 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
5003 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5004 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
5005 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5006 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
5007 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5008 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
5009 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5010 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
5011 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5012 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
5013 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5014 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
5015 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5016 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
5017 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5018 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
5019 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5020 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
5021 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5022 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
5023 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5024 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
5025 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5026 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5027 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5028 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5029 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5030 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5031 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5032 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5033 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5034 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5035 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5036 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5037 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
5038 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
5039 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5040 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
5041 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5042 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
5043 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5044 0xf810f000, 0xff70f000, "pld%c\t%a"},
5045 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5046 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5047 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5048 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5049 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5050 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5051 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5052 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5053 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5054 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5055 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5056 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5057 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5058 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5059 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5060 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
5061 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5062 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
5063 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5064 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
5065 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5066 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
5067 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5068 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
5069 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5070 0xfb100000, 0xfff000c0,
5071 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
5072 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5073 0xfbc00080, 0xfff000c0,
5074 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
5075 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5076 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
5077 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5078 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
5079 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5080 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
5081 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5082 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
5083 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5084 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
5085 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
5086 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
5087 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5088 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
5089 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
5090 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
5091 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5092 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
5093 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5094 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
5095 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5096 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
5097 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5098 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
5099 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5100 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
5101 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5102 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
5103 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5104 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
5105 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5106 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
5107 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5108 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
5109 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5110 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
5111 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
5112 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
5113 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5114 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
5115 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5116 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
5117 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5118 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
5119 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5120 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
5121 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5122 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
5123 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5124 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
5125 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5126 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
5127 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5128 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
5129 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5130 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
5131 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5132 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
5133 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5134 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
5135 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5136 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
5137 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5138 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
5139 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5140 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
5141 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5142 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
5143 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5144 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
5145 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5146 0xe9400000, 0xff500000,
5147 "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
5148 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5149 0xe9500000, 0xff500000,
5150 "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
5151 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5152 0xe8600000, 0xff700000,
5153 "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
5154 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5155 0xe8700000, 0xff700000,
5156 "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
5157 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5158 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
5159 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5160 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
5162 /* Filter out Bcc with cond=E or F, which are used for other instructions. */
5163 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5164 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
5165 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5166 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
5167 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5168 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
5169 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5170 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
5172 /* These have been 32-bit since the invention of Thumb. */
5173 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
5174 0xf000c000, 0xf800d001, "blx%c\t%B%x"},
5175 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
5176 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
5179 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
5180 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION
},
5181 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
5184 static const char *const arm_conditional
[] =
5185 {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
5186 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
5188 static const char *const arm_fp_const
[] =
5189 {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
5191 static const char *const arm_shift
[] =
5192 {"lsl", "lsr", "asr", "ror"};
5197 const char *description
;
5198 const char *reg_names
[16];
5202 static const arm_regname regnames
[] =
5204 { "reg-names-raw", N_("Select raw register names"),
5205 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
5206 { "reg-names-gcc", N_("Select register names used by GCC"),
5207 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
5208 { "reg-names-std", N_("Select register names used in ARM's ISA documentation"),
5209 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
5210 { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL
} },
5211 { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL
} },
5212 { "reg-names-apcs", N_("Select register names used in the APCS"),
5213 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
5214 { "reg-names-atpcs", N_("Select register names used in the ATPCS"),
5215 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
5216 { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
5217 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }},
5218 { "coproc<N>=(cde|generic)", N_("Enable CDE extensions for coprocessor N space"), { NULL
} }
5221 static const char *const iwmmxt_wwnames
[] =
5222 {"b", "h", "w", "d"};
5224 static const char *const iwmmxt_wwssnames
[] =
5225 {"b", "bus", "bc", "bss",
5226 "h", "hus", "hc", "hss",
5227 "w", "wus", "wc", "wss",
5228 "d", "dus", "dc", "dss"
5231 static const char *const iwmmxt_regnames
[] =
5232 { "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
5233 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
5236 static const char *const iwmmxt_cregnames
[] =
5237 { "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
5238 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
5241 static const char *const vec_condnames
[] =
5242 { "eq", "ne", "cs", "hi", "ge", "lt", "gt", "le"
5245 static const char *const mve_predicatenames
[] =
5246 { "", "ttt", "tt", "tte", "t", "tee", "te", "tet", "",
5247 "eee", "ee", "eet", "e", "ett", "et", "ete"
5250 /* Names for 2-bit size field for mve vector isntructions. */
5251 static const char *const mve_vec_sizename
[] =
5252 { "8", "16", "32", "64"};
5254 /* Indicates whether we are processing a then predicate,
5255 else predicate or none at all. */
5263 /* Information used to process a vpt block and subsequent instructions. */
5266 /* Are we in a vpt block. */
5269 /* Next predicate state if in vpt block. */
5270 enum vpt_pred_state next_pred_state
;
5272 /* Mask from vpt/vpst instruction. */
5273 long predicate_mask
;
5275 /* Instruction number in vpt block. */
5276 long current_insn_num
;
5278 /* Number of instructions in vpt block.. */
5282 static struct vpt_block vpt_block_state
=
5291 /* Default to GCC register name set. */
5292 static unsigned int regname_selected
= 1;
5294 #define NUM_ARM_OPTIONS ARRAY_SIZE (regnames)
5295 #define arm_regnames regnames[regname_selected].reg_names
5297 static bool force_thumb
= false;
5298 static uint16_t cde_coprocs
= 0;
5300 /* Current IT instruction state. This contains the same state as the IT
5301 bits in the CPSR. */
5302 static unsigned int ifthen_state
;
5303 /* IT state for the next instruction. */
5304 static unsigned int ifthen_next_state
;
5305 /* The address of the insn for which the IT state is valid. */
5306 static bfd_vma ifthen_address
;
5307 #define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
5308 /* Indicates that the current Conditional state is unconditional or outside
5310 #define COND_UNCOND 16
5314 /* Extract the predicate mask for a VPT or VPST instruction.
5315 The mask is composed of bits 13-15 (Mkl) and bit 22 (Mkh). */
5318 mve_extract_pred_mask (long given
)
5320 return ((given
& 0x00400000) >> 19) | ((given
& 0xe000) >> 13);
5323 /* Return the number of instructions in a MVE predicate block. */
5325 num_instructions_vpt_block (long given
)
5327 long mask
= mve_extract_pred_mask (given
);
5334 if ((mask
& 7) == 4)
5337 if ((mask
& 3) == 2)
5340 if ((mask
& 1) == 1)
5347 mark_outside_vpt_block (void)
5349 vpt_block_state
.in_vpt_block
= false;
5350 vpt_block_state
.next_pred_state
= PRED_NONE
;
5351 vpt_block_state
.predicate_mask
= 0;
5352 vpt_block_state
.current_insn_num
= 0;
5353 vpt_block_state
.num_pred_insn
= 0;
5357 mark_inside_vpt_block (long given
)
5359 vpt_block_state
.in_vpt_block
= true;
5360 vpt_block_state
.next_pred_state
= PRED_THEN
;
5361 vpt_block_state
.predicate_mask
= mve_extract_pred_mask (given
);
5362 vpt_block_state
.current_insn_num
= 0;
5363 vpt_block_state
.num_pred_insn
= num_instructions_vpt_block (given
);
5364 assert (vpt_block_state
.num_pred_insn
>= 1);
5367 static enum vpt_pred_state
5368 invert_next_predicate_state (enum vpt_pred_state astate
)
5370 if (astate
== PRED_THEN
)
5372 else if (astate
== PRED_ELSE
)
5378 static enum vpt_pred_state
5379 update_next_predicate_state (void)
5381 long pred_mask
= vpt_block_state
.predicate_mask
;
5382 long mask_for_insn
= 0;
5384 switch (vpt_block_state
.current_insn_num
)
5402 if (pred_mask
& mask_for_insn
)
5403 return invert_next_predicate_state (vpt_block_state
.next_pred_state
);
5405 return vpt_block_state
.next_pred_state
;
5409 update_vpt_block_state (void)
5411 vpt_block_state
.current_insn_num
++;
5412 if (vpt_block_state
.current_insn_num
== vpt_block_state
.num_pred_insn
)
5414 /* No more instructions to process in vpt block. */
5415 mark_outside_vpt_block ();
5419 vpt_block_state
.next_pred_state
= update_next_predicate_state ();
5422 /* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
5423 Returns pointer to following character of the format string and
5424 fills in *VALUEP and *WIDTHP with the extracted value and number of
5425 bits extracted. WIDTHP can be NULL. */
5428 arm_decode_bitfield (const char *ptr
,
5430 unsigned long *valuep
,
5433 unsigned long value
= 0;
5441 for (start
= 0; *ptr
>= '0' && *ptr
<= '9'; ptr
++)
5442 start
= start
* 10 + *ptr
- '0';
5444 for (end
= 0, ptr
++; *ptr
>= '0' && *ptr
<= '9'; ptr
++)
5445 end
= end
* 10 + *ptr
- '0';
5451 value
|= ((insn
>> start
) & ((2ul << bits
) - 1)) << width
;
5454 while (*ptr
++ == ',');
5462 arm_decode_shift (long given
, fprintf_ftype func
, void *stream
,
5465 func (stream
, "%s", arm_regnames
[given
& 0xf]);
5467 if ((given
& 0xff0) != 0)
5469 if ((given
& 0x10) == 0)
5471 int amount
= (given
& 0xf80) >> 7;
5472 int shift
= (given
& 0x60) >> 5;
5478 func (stream
, ", rrx");
5486 func (stream
, ", %s #%d", arm_shift
[shift
], amount
);
5488 func (stream
, ", #%d", amount
);
5490 else if ((given
& 0x80) == 0x80)
5491 func (stream
, "\t; <illegal shifter operand>");
5492 else if (print_shift
)
5493 func (stream
, ", %s %s", arm_shift
[(given
& 0x60) >> 5],
5494 arm_regnames
[(given
& 0xf00) >> 8]);
5496 func (stream
, ", %s", arm_regnames
[(given
& 0xf00) >> 8]);
5500 /* Return TRUE if the MATCHED_INSN can be inside an IT block. */
5503 is_mve_okay_in_it (enum mve_instructions matched_insn
)
5505 switch (matched_insn
)
5507 case MVE_VMOV_GP_TO_VEC_LANE
:
5508 case MVE_VMOV2_VEC_LANE_TO_GP
:
5509 case MVE_VMOV2_GP_TO_VEC_LANE
:
5510 case MVE_VMOV_VEC_LANE_TO_GP
:
5535 is_mve_architecture (struct disassemble_info
*info
)
5537 struct arm_private_data
*private_data
= info
->private_data
;
5538 arm_feature_set allowed_arches
= private_data
->features
;
5540 arm_feature_set arm_ext_v8_1m_main
5541 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
);
5543 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main
, allowed_arches
)
5544 && !ARM_CPU_IS_ANY (allowed_arches
))
5551 is_vpt_instruction (long given
)
5554 /* If mkh:mkl is '0000' then its not a vpt/vpst instruction. */
5555 if ((given
& 0x0040e000) == 0)
5558 /* VPT floating point T1 variant. */
5559 if (((given
& 0xefb10f50) == 0xee310f00 && ((given
& 0x1001) != 0x1))
5560 /* VPT floating point T2 variant. */
5561 || ((given
& 0xefb10f50) == 0xee310f40)
5562 /* VPT vector T1 variant. */
5563 || ((given
& 0xff811f51) == 0xfe010f00)
5564 /* VPT vector T2 variant. */
5565 || ((given
& 0xff811f51) == 0xfe010f01
5566 && ((given
& 0x300000) != 0x300000))
5567 /* VPT vector T3 variant. */
5568 || ((given
& 0xff811f50) == 0xfe011f00)
5569 /* VPT vector T4 variant. */
5570 || ((given
& 0xff811f70) == 0xfe010f40)
5571 /* VPT vector T5 variant. */
5572 || ((given
& 0xff811f70) == 0xfe010f60)
5573 /* VPT vector T6 variant. */
5574 || ((given
& 0xff811f50) == 0xfe011f40)
5575 /* VPST vector T variant. */
5576 || ((given
& 0xffbf1fff) == 0xfe310f4d))
5582 /* Decode a bitfield from opcode GIVEN, with starting bitfield = START
5583 and ending bitfield = END. END must be greater than START. */
5585 static unsigned long
5586 arm_decode_field (unsigned long given
, unsigned int start
, unsigned int end
)
5588 int bits
= end
- start
;
5593 return ((given
>> start
) & ((2ul << bits
) - 1));
5596 /* Decode a bitfield from opcode GIVEN, with multiple bitfields:
5597 START:END and START2:END2. END/END2 must be greater than
5600 static unsigned long
5601 arm_decode_field_multiple (unsigned long given
, unsigned int start
,
5602 unsigned int end
, unsigned int start2
,
5605 int bits
= end
- start
;
5606 int bits2
= end2
- start2
;
5607 unsigned long value
= 0;
5613 value
= arm_decode_field (given
, start
, end
);
5616 value
|= ((given
>> start2
) & ((2ul << bits2
) - 1)) << width
;
5620 /* Return TRUE if the GIVEN encoding should not be decoded as MATCHED_INSN.
5621 This helps us decode instructions that change mnemonic depending on specific
5622 operand values/encodings. */
5625 is_mve_encoding_conflict (unsigned long given
,
5626 enum mve_instructions matched_insn
)
5628 switch (matched_insn
)
5631 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) == 0)
5637 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) == 0)
5639 if ((arm_decode_field (given
, 12, 12) == 0)
5640 && (arm_decode_field (given
, 0, 0) == 1))
5645 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) == 0)
5647 if (arm_decode_field (given
, 0, 3) == 0xd)
5651 case MVE_VPT_VEC_T1
:
5652 case MVE_VPT_VEC_T2
:
5653 case MVE_VPT_VEC_T3
:
5654 case MVE_VPT_VEC_T4
:
5655 case MVE_VPT_VEC_T5
:
5656 case MVE_VPT_VEC_T6
:
5657 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) == 0)
5659 if (arm_decode_field (given
, 20, 21) == 3)
5663 case MVE_VCMP_FP_T1
:
5664 if ((arm_decode_field (given
, 12, 12) == 0)
5665 && (arm_decode_field (given
, 0, 0) == 1))
5670 case MVE_VCMP_FP_T2
:
5671 if (arm_decode_field (given
, 0, 3) == 0xd)
5678 case MVE_VMUL_VEC_T2
:
5685 case MVE_VADD_VEC_T2
:
5686 case MVE_VSUB_VEC_T2
:
5703 case MVE_VQDMULH_T3
:
5704 case MVE_VQRDMULH_T4
:
5710 case MVE_VCMP_VEC_T1
:
5711 case MVE_VCMP_VEC_T2
:
5712 case MVE_VCMP_VEC_T3
:
5713 case MVE_VCMP_VEC_T4
:
5714 case MVE_VCMP_VEC_T5
:
5715 case MVE_VCMP_VEC_T6
:
5716 if (arm_decode_field (given
, 20, 21) == 3)
5725 if (arm_decode_field (given
, 7, 8) == 3)
5732 if ((arm_decode_field (given
, 24, 24) == 0)
5733 && (arm_decode_field (given
, 21, 21) == 0))
5737 else if ((arm_decode_field (given
, 7, 8) == 3))
5748 if ((arm_decode_field (given
, 24, 24) == 0)
5749 && (arm_decode_field (given
, 21, 21) == 0))
5756 case MVE_VCVT_FP_FIX_VEC
:
5757 return (arm_decode_field (given
, 16, 21) & 0x38) == 0;
5762 unsigned long cmode
= arm_decode_field (given
, 8, 11);
5764 if ((cmode
& 1) == 0)
5766 else if ((cmode
& 0xc) == 0xc)
5774 unsigned long cmode
= arm_decode_field (given
, 8, 11);
5778 else if ((cmode
& 0x9) == 1)
5780 else if ((cmode
& 0xd) == 9)
5786 case MVE_VMOV_IMM_TO_VEC
:
5787 if ((arm_decode_field (given
, 5, 5) == 1)
5788 && (arm_decode_field (given
, 8, 11) != 0xe))
5795 unsigned long size
= arm_decode_field (given
, 19, 20);
5796 if ((size
== 0) || (size
== 3))
5817 if (arm_decode_field (given
, 18, 19) == 3)
5823 case MVE_VRMLSLDAVH
:
5826 if (arm_decode_field (given
, 20, 22) == 7)
5831 case MVE_VRMLALDAVH
:
5832 if ((arm_decode_field (given
, 20, 22) & 6) == 6)
5839 if ((arm_decode_field (given
, 20, 21) == 3)
5840 || (arm_decode_field (given
, 1, 3) == 7))
5847 if (arm_decode_field (given
, 16, 18) == 0)
5849 unsigned long sz
= arm_decode_field (given
, 19, 20);
5851 if ((sz
== 1) || (sz
== 2))
5866 if (arm_decode_field (given
, 19, 21) == 0)
5872 if (arm_decode_field (given
, 16, 19) == 0xf)
5888 if (arm_decode_field (given
, 9, 11) == 0x7)
5896 unsigned long rm
, rn
;
5897 rm
= arm_decode_field (given
, 0, 3);
5898 rn
= arm_decode_field (given
, 16, 19);
5900 if (rm
== 0xf && rn
== 0xf)
5903 else if (rn
== rm
&& rn
!= 0xf)
5909 if (arm_decode_field (given
, 0, 3) == 0xd)
5912 else if (matched_insn
== MVE_CSNEG
)
5913 if (arm_decode_field (given
, 0, 3) == arm_decode_field (given
, 16, 19))
5918 case MVE_VADD_FP_T1
:
5919 case MVE_VADD_FP_T2
:
5920 case MVE_VADD_VEC_T1
:
5927 print_mve_vld_str_addr (struct disassemble_info
*info
,
5928 unsigned long given
,
5929 enum mve_instructions matched_insn
)
5931 void *stream
= info
->stream
;
5932 fprintf_ftype func
= info
->fprintf_func
;
5934 unsigned long p
, w
, gpr
, imm
, add
, mod_imm
;
5936 imm
= arm_decode_field (given
, 0, 6);
5939 switch (matched_insn
)
5943 gpr
= arm_decode_field (given
, 16, 18);
5948 gpr
= arm_decode_field (given
, 16, 18);
5954 gpr
= arm_decode_field (given
, 16, 19);
5960 gpr
= arm_decode_field (given
, 16, 19);
5966 gpr
= arm_decode_field (given
, 16, 19);
5973 p
= arm_decode_field (given
, 24, 24);
5974 w
= arm_decode_field (given
, 21, 21);
5976 add
= arm_decode_field (given
, 23, 23);
5980 /* Don't print anything for '+' as it is implied. */
5990 func (stream
, "[%s, #%s%lu]", arm_regnames
[gpr
], add_sub
, mod_imm
);
5991 /* Pre-indexed mode. */
5993 func (stream
, "[%s, #%s%lu]!", arm_regnames
[gpr
], add_sub
, mod_imm
);
5995 else if ((p
== 0) && (w
== 1))
5996 /* Post-index mode. */
5997 func (stream
, "[%s], #%s%lu", arm_regnames
[gpr
], add_sub
, mod_imm
);
6000 /* Return FALSE if GIVEN is not an undefined encoding for MATCHED_INSN.
6001 Otherwise, return TRUE and set UNDEFINED_CODE to give a reason as to why
6002 this encoding is undefined. */
6005 is_mve_undefined (unsigned long given
, enum mve_instructions matched_insn
,
6006 enum mve_undefined
*undefined_code
)
6008 *undefined_code
= UNDEF_NONE
;
6010 switch (matched_insn
)
6013 if (arm_decode_field_multiple (given
, 5, 5, 22, 22) == 3)
6015 *undefined_code
= UNDEF_SIZE_3
;
6023 case MVE_VMUL_VEC_T1
:
6025 case MVE_VADD_VEC_T1
:
6026 case MVE_VSUB_VEC_T1
:
6027 case MVE_VQDMULH_T1
:
6028 case MVE_VQRDMULH_T2
:
6032 if (arm_decode_field (given
, 20, 21) == 3)
6034 *undefined_code
= UNDEF_SIZE_3
;
6041 if (arm_decode_field (given
, 7, 8) == 3)
6043 *undefined_code
= UNDEF_SIZE_3
;
6050 if (arm_decode_field (given
, 7, 8) <= 1)
6052 *undefined_code
= UNDEF_SIZE_LE_1
;
6059 if ((arm_decode_field (given
, 7, 8) == 0))
6061 *undefined_code
= UNDEF_SIZE_0
;
6068 if ((arm_decode_field (given
, 7, 8) <= 1))
6070 *undefined_code
= UNDEF_SIZE_LE_1
;
6076 case MVE_VLDRB_GATHER_T1
:
6077 if (arm_decode_field (given
, 7, 8) == 3)
6079 *undefined_code
= UNDEF_SIZE_3
;
6082 else if ((arm_decode_field (given
, 28, 28) == 0)
6083 && (arm_decode_field (given
, 7, 8) == 0))
6085 *undefined_code
= UNDEF_NOT_UNS_SIZE_0
;
6091 case MVE_VLDRH_GATHER_T2
:
6092 if (arm_decode_field (given
, 7, 8) == 3)
6094 *undefined_code
= UNDEF_SIZE_3
;
6097 else if ((arm_decode_field (given
, 28, 28) == 0)
6098 && (arm_decode_field (given
, 7, 8) == 1))
6100 *undefined_code
= UNDEF_NOT_UNS_SIZE_1
;
6103 else if (arm_decode_field (given
, 7, 8) == 0)
6105 *undefined_code
= UNDEF_SIZE_0
;
6111 case MVE_VLDRW_GATHER_T3
:
6112 if (arm_decode_field (given
, 7, 8) != 2)
6114 *undefined_code
= UNDEF_SIZE_NOT_2
;
6117 else if (arm_decode_field (given
, 28, 28) == 0)
6119 *undefined_code
= UNDEF_NOT_UNSIGNED
;
6125 case MVE_VLDRD_GATHER_T4
:
6126 if (arm_decode_field (given
, 7, 8) != 3)
6128 *undefined_code
= UNDEF_SIZE_NOT_3
;
6131 else if (arm_decode_field (given
, 28, 28) == 0)
6133 *undefined_code
= UNDEF_NOT_UNSIGNED
;
6139 case MVE_VSTRB_SCATTER_T1
:
6140 if (arm_decode_field (given
, 7, 8) == 3)
6142 *undefined_code
= UNDEF_SIZE_3
;
6148 case MVE_VSTRH_SCATTER_T2
:
6150 unsigned long size
= arm_decode_field (given
, 7, 8);
6153 *undefined_code
= UNDEF_SIZE_3
;
6158 *undefined_code
= UNDEF_SIZE_0
;
6165 case MVE_VSTRW_SCATTER_T3
:
6166 if (arm_decode_field (given
, 7, 8) != 2)
6168 *undefined_code
= UNDEF_SIZE_NOT_2
;
6174 case MVE_VSTRD_SCATTER_T4
:
6175 if (arm_decode_field (given
, 7, 8) != 3)
6177 *undefined_code
= UNDEF_SIZE_NOT_3
;
6183 case MVE_VCVT_FP_FIX_VEC
:
6185 unsigned long imm6
= arm_decode_field (given
, 16, 21);
6186 if ((imm6
& 0x20) == 0)
6188 *undefined_code
= UNDEF_VCVT_IMM6
;
6192 if ((arm_decode_field (given
, 9, 9) == 0)
6193 && ((imm6
& 0x30) == 0x20))
6195 *undefined_code
= UNDEF_VCVT_FSI_IMM6
;
6204 case MVE_VCVT_BETWEEN_FP_INT
:
6205 case MVE_VCVT_FROM_FP_TO_INT
:
6207 unsigned long size
= arm_decode_field (given
, 18, 19);
6210 *undefined_code
= UNDEF_SIZE_0
;
6215 *undefined_code
= UNDEF_SIZE_3
;
6222 case MVE_VMOV_VEC_LANE_TO_GP
:
6224 unsigned long op1
= arm_decode_field (given
, 21, 22);
6225 unsigned long op2
= arm_decode_field (given
, 5, 6);
6226 unsigned long u
= arm_decode_field (given
, 23, 23);
6228 if ((op2
== 0) && (u
== 1))
6230 if ((op1
== 0) || (op1
== 1))
6232 *undefined_code
= UNDEF_BAD_U_OP1_OP2
;
6240 if ((op1
== 0) || (op1
== 1))
6242 *undefined_code
= UNDEF_BAD_OP1_OP2
;
6252 case MVE_VMOV_GP_TO_VEC_LANE
:
6253 if (arm_decode_field (given
, 5, 6) == 2)
6255 unsigned long op1
= arm_decode_field (given
, 21, 22);
6256 if ((op1
== 0) || (op1
== 1))
6258 *undefined_code
= UNDEF_BAD_OP1_OP2
;
6267 case MVE_VMOV_VEC_TO_VEC
:
6268 if ((arm_decode_field (given
, 5, 5) == 1)
6269 || (arm_decode_field (given
, 22, 22) == 1))
6273 case MVE_VMOV_IMM_TO_VEC
:
6274 if (arm_decode_field (given
, 5, 5) == 0)
6276 unsigned long cmode
= arm_decode_field (given
, 8, 11);
6278 if (((cmode
& 9) == 1) || ((cmode
& 5) == 1))
6280 *undefined_code
= UNDEF_OP_0_BAD_CMODE
;
6291 if (arm_decode_field (given
, 18, 19) == 2)
6293 *undefined_code
= UNDEF_SIZE_2
;
6299 case MVE_VRMLALDAVH
:
6300 case MVE_VMLADAV_T1
:
6301 case MVE_VMLADAV_T2
:
6303 if ((arm_decode_field (given
, 28, 28) == 1)
6304 && (arm_decode_field (given
, 12, 12) == 1))
6306 *undefined_code
= UNDEF_XCHG_UNS
;
6317 unsigned long sz
= arm_decode_field (given
, 19, 20);
6320 else if ((sz
& 2) == 2)
6324 *undefined_code
= UNDEF_SIZE
;
6338 unsigned long sz
= arm_decode_field (given
, 19, 21);
6341 else if ((sz
& 6) == 2)
6343 else if ((sz
& 4) == 4)
6347 *undefined_code
= UNDEF_SIZE
;
6354 if (arm_decode_field (given
, 19, 20) == 0)
6356 *undefined_code
= UNDEF_SIZE_0
;
6363 if (arm_decode_field (given
, 18, 19) == 3)
6365 *undefined_code
= UNDEF_SIZE_3
;
6376 if (arm_decode_field (given
, 18, 19) == 3)
6378 *undefined_code
= UNDEF_SIZE_3
;
6385 if (arm_decode_field (given
, 18, 19) == 0)
6389 *undefined_code
= UNDEF_SIZE_NOT_0
;
6395 unsigned long size
= arm_decode_field (given
, 18, 19);
6396 if ((size
& 2) == 2)
6398 *undefined_code
= UNDEF_SIZE_2
;
6406 if (arm_decode_field (given
, 18, 19) != 3)
6410 *undefined_code
= UNDEF_SIZE_3
;
6419 /* Return FALSE if GIVEN is not an unpredictable encoding for MATCHED_INSN.
6420 Otherwise, return TRUE and set UNPREDICTABLE_CODE to give a reason as to
6421 why this encoding is unpredictable. */
6424 is_mve_unpredictable (unsigned long given
, enum mve_instructions matched_insn
,
6425 enum mve_unpredictable
*unpredictable_code
)
6427 *unpredictable_code
= UNPRED_NONE
;
6429 switch (matched_insn
)
6431 case MVE_VCMP_FP_T2
:
6433 if ((arm_decode_field (given
, 12, 12) == 0)
6434 && (arm_decode_field (given
, 5, 5) == 1))
6436 *unpredictable_code
= UNPRED_FCA_0_FCB_1
;
6442 case MVE_VPT_VEC_T4
:
6443 case MVE_VPT_VEC_T5
:
6444 case MVE_VPT_VEC_T6
:
6445 case MVE_VCMP_VEC_T4
:
6446 case MVE_VCMP_VEC_T5
:
6447 case MVE_VCMP_VEC_T6
:
6448 if (arm_decode_field (given
, 0, 3) == 0xd)
6450 *unpredictable_code
= UNPRED_R13
;
6458 unsigned long gpr
= arm_decode_field (given
, 12, 15);
6461 *unpredictable_code
= UNPRED_R13
;
6464 else if (gpr
== 0xf)
6466 *unpredictable_code
= UNPRED_R15
;
6475 case MVE_VMUL_FP_T2
:
6476 case MVE_VMUL_VEC_T2
:
6479 case MVE_VADD_FP_T2
:
6480 case MVE_VSUB_FP_T2
:
6481 case MVE_VADD_VEC_T2
:
6482 case MVE_VSUB_VEC_T2
:
6492 case MVE_VQDMULH_T3
:
6493 case MVE_VQRDMULH_T4
:
6495 case MVE_VFMA_FP_SCALAR
:
6496 case MVE_VFMAS_FP_SCALAR
:
6500 unsigned long gpr
= arm_decode_field (given
, 0, 3);
6503 *unpredictable_code
= UNPRED_R13
;
6506 else if (gpr
== 0xf)
6508 *unpredictable_code
= UNPRED_R15
;
6518 unsigned long rn
= arm_decode_field (given
, 16, 19);
6520 if ((rn
== 0xd) && (arm_decode_field (given
, 21, 21) == 1))
6522 *unpredictable_code
= UNPRED_R13_AND_WB
;
6528 *unpredictable_code
= UNPRED_R15
;
6532 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) > 6)
6534 *unpredictable_code
= UNPRED_Q_GT_6
;
6544 unsigned long rn
= arm_decode_field (given
, 16, 19);
6546 if ((rn
== 0xd) && (arm_decode_field (given
, 21, 21) == 1))
6548 *unpredictable_code
= UNPRED_R13_AND_WB
;
6554 *unpredictable_code
= UNPRED_R15
;
6558 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) > 4)
6560 *unpredictable_code
= UNPRED_Q_GT_4
;
6574 unsigned long rn
= arm_decode_field (given
, 16, 19);
6576 if ((rn
== 0xd) && (arm_decode_field (given
, 21, 21) == 1))
6578 *unpredictable_code
= UNPRED_R13_AND_WB
;
6583 *unpredictable_code
= UNPRED_R15
;
6590 case MVE_VLDRB_GATHER_T1
:
6591 if (arm_decode_field (given
, 0, 0) == 1)
6593 *unpredictable_code
= UNPRED_OS
;
6598 /* To handle common code with T2-T4 variants. */
6599 case MVE_VLDRH_GATHER_T2
:
6600 case MVE_VLDRW_GATHER_T3
:
6601 case MVE_VLDRD_GATHER_T4
:
6603 unsigned long qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
6604 unsigned long qm
= arm_decode_field_multiple (given
, 1, 3, 5, 5);
6608 *unpredictable_code
= UNPRED_Q_REGS_EQUAL
;
6612 if (arm_decode_field (given
, 16, 19) == 0xf)
6614 *unpredictable_code
= UNPRED_R15
;
6621 case MVE_VLDRW_GATHER_T5
:
6622 case MVE_VLDRD_GATHER_T6
:
6624 unsigned long qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
6625 unsigned long qm
= arm_decode_field_multiple (given
, 17, 19, 7, 7);
6629 *unpredictable_code
= UNPRED_Q_REGS_EQUAL
;
6636 case MVE_VSTRB_SCATTER_T1
:
6637 if (arm_decode_field (given
, 16, 19) == 0xf)
6639 *unpredictable_code
= UNPRED_R15
;
6642 else if (arm_decode_field (given
, 0, 0) == 1)
6644 *unpredictable_code
= UNPRED_OS
;
6650 case MVE_VSTRH_SCATTER_T2
:
6651 case MVE_VSTRW_SCATTER_T3
:
6652 case MVE_VSTRD_SCATTER_T4
:
6653 if (arm_decode_field (given
, 16, 19) == 0xf)
6655 *unpredictable_code
= UNPRED_R15
;
6661 case MVE_VMOV2_VEC_LANE_TO_GP
:
6662 case MVE_VMOV2_GP_TO_VEC_LANE
:
6663 case MVE_VCVT_BETWEEN_FP_INT
:
6664 case MVE_VCVT_FROM_FP_TO_INT
:
6666 unsigned long rt
= arm_decode_field (given
, 0, 3);
6667 unsigned long rt2
= arm_decode_field (given
, 16, 19);
6669 if ((rt
== 0xd) || (rt2
== 0xd))
6671 *unpredictable_code
= UNPRED_R13
;
6674 else if ((rt
== 0xf) || (rt2
== 0xf))
6676 *unpredictable_code
= UNPRED_R15
;
6679 else if (rt
== rt2
&& matched_insn
!= MVE_VMOV2_GP_TO_VEC_LANE
)
6681 *unpredictable_code
= UNPRED_GP_REGS_EQUAL
;
6690 case MVE_VMAXNMV_FP
:
6691 case MVE_VMAXNMAV_FP
:
6692 case MVE_VMINNMV_FP
:
6693 case MVE_VMINNMAV_FP
:
6697 case MVE_VMOV_HFP_TO_GP
:
6698 case MVE_VMOV_GP_TO_VEC_LANE
:
6699 case MVE_VMOV_VEC_LANE_TO_GP
:
6701 unsigned long rda
= arm_decode_field (given
, 12, 15);
6704 *unpredictable_code
= UNPRED_R13
;
6707 else if (rda
== 0xf)
6709 *unpredictable_code
= UNPRED_R15
;
6722 if (arm_decode_field (given
, 20, 21) == 2)
6724 Qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
6725 Qm
= arm_decode_field_multiple (given
, 1, 3, 5, 5);
6726 Qn
= arm_decode_field_multiple (given
, 17, 19, 7, 7);
6728 if ((Qd
== Qn
) || (Qd
== Qm
))
6730 *unpredictable_code
= UNPRED_Q_REGS_EQ_AND_SIZE_2
;
6741 case MVE_VQDMULL_T1
:
6747 if (arm_decode_field (given
, 28, 28) == 1)
6749 Qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
6750 Qm
= arm_decode_field_multiple (given
, 1, 3, 5, 5);
6751 Qn
= arm_decode_field_multiple (given
, 17, 19, 7, 7);
6753 if ((Qd
== Qn
) || (Qd
== Qm
))
6755 *unpredictable_code
= UNPRED_Q_REGS_EQ_AND_SIZE_1
;
6765 case MVE_VQDMULL_T2
:
6767 unsigned long gpr
= arm_decode_field (given
, 0, 3);
6770 *unpredictable_code
= UNPRED_R13
;
6773 else if (gpr
== 0xf)
6775 *unpredictable_code
= UNPRED_R15
;
6779 if (arm_decode_field (given
, 28, 28) == 1)
6782 = arm_decode_field_multiple (given
, 13, 15, 22, 22);
6783 unsigned long Qn
= arm_decode_field_multiple (given
, 17, 19, 7, 7);
6787 *unpredictable_code
= UNPRED_Q_REGS_EQ_AND_SIZE_1
;
6798 case MVE_VRMLSLDAVH
:
6801 if (arm_decode_field (given
, 20, 22) == 6)
6803 *unpredictable_code
= UNPRED_R13
;
6811 if (arm_decode_field (given
, 1, 3) == 6)
6813 *unpredictable_code
= UNPRED_R13
;
6822 unsigned long Qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
6823 unsigned long Qm
= arm_decode_field_multiple (given
, 1, 3, 5, 5);
6824 if ((Qd
== Qm
) && arm_decode_field (given
, 20, 21) == 2)
6826 *unpredictable_code
= UNPRED_Q_REGS_EQ_AND_SIZE_2
;
6835 unsigned long Qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
6836 unsigned long Qm
= arm_decode_field_multiple (given
, 1, 3, 5, 5);
6837 if ((Qd
== Qm
) && arm_decode_field (given
, 20, 20) == 1)
6839 *unpredictable_code
= UNPRED_Q_REGS_EQ_AND_SIZE_1
;
6852 if (arm_decode_field (given
, 20, 20) == 1)
6854 Qda
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
6855 Qm
= arm_decode_field_multiple (given
, 1, 3, 5, 5);
6856 Qn
= arm_decode_field_multiple (given
, 17, 19, 7, 7);
6858 if ((Qda
== Qn
) || (Qda
== Qm
))
6860 *unpredictable_code
= UNPRED_Q_REGS_EQ_AND_SIZE_1
;
6872 if (arm_decode_field (given
, 16, 19) == 0xd)
6874 *unpredictable_code
= UNPRED_R13
;
6882 unsigned long qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
6883 unsigned long qm
= arm_decode_field_multiple (given
, 1, 3, 6, 6);
6887 *unpredictable_code
= UNPRED_Q_REGS_EQUAL
;
6906 unsigned long gpr
= arm_decode_field (given
, 9, 11);
6907 gpr
= ((gpr
<< 1) | 1);
6910 *unpredictable_code
= UNPRED_R13
;
6913 else if (gpr
== 0xf)
6915 *unpredictable_code
= UNPRED_R15
;
6928 print_mve_vmov_index (struct disassemble_info
*info
, unsigned long given
)
6930 unsigned long op1
= arm_decode_field (given
, 21, 22);
6931 unsigned long op2
= arm_decode_field (given
, 5, 6);
6932 unsigned long h
= arm_decode_field (given
, 16, 16);
6933 unsigned long index_operand
, esize
, targetBeat
, idx
;
6934 void *stream
= info
->stream
;
6935 fprintf_ftype func
= info
->fprintf_func
;
6937 if ((op1
& 0x2) == 0x2)
6939 index_operand
= op2
;
6942 else if (((op1
& 0x2) == 0x0) && ((op2
& 0x1) == 0x1))
6944 index_operand
= op2
>> 1;
6947 else if (((op1
& 0x2) == 0) && ((op2
& 0x3) == 0))
6954 func (stream
, "<undefined index>");
6958 targetBeat
= (op1
& 0x1) | (h
<< 1);
6959 idx
= index_operand
+ targetBeat
* (32/esize
);
6961 func (stream
, "%lu", idx
);
6964 /* Print neon and mve 8-bit immediate that can be a 8, 16, 32, or 64-bits
6965 in length and integer of floating-point type. */
6967 print_simd_imm8 (struct disassemble_info
*info
, unsigned long given
,
6968 unsigned int ibit_loc
, const struct mopcode32
*insn
)
6971 int cmode
= (given
>> 8) & 0xf;
6972 int op
= (given
>> 5) & 0x1;
6973 unsigned long value
= 0, hival
= 0;
6977 void *stream
= info
->stream
;
6978 fprintf_ftype func
= info
->fprintf_func
;
6980 /* On Neon the 'i' bit is at bit 24, on mve it is
6982 bits
|= ((given
>> ibit_loc
) & 1) << 7;
6983 bits
|= ((given
>> 16) & 7) << 4;
6984 bits
|= ((given
>> 0) & 15) << 0;
6988 shift
= (cmode
>> 1) & 3;
6989 value
= (unsigned long) bits
<< (8 * shift
);
6992 else if (cmode
< 12)
6994 shift
= (cmode
>> 1) & 1;
6995 value
= (unsigned long) bits
<< (8 * shift
);
6998 else if (cmode
< 14)
7000 shift
= (cmode
& 1) + 1;
7001 value
= (unsigned long) bits
<< (8 * shift
);
7002 value
|= (1ul << (8 * shift
)) - 1;
7005 else if (cmode
== 14)
7009 /* Bit replication into bytes. */
7015 for (ix
= 7; ix
>= 0; ix
--)
7017 mask
= ((bits
>> ix
) & 1) ? 0xff : 0;
7019 value
= (value
<< 8) | mask
;
7021 hival
= (hival
<< 8) | mask
;
7027 /* Byte replication. */
7028 value
= (unsigned long) bits
;
7034 /* Floating point encoding. */
7037 value
= (unsigned long) (bits
& 0x7f) << 19;
7038 value
|= (unsigned long) (bits
& 0x80) << 24;
7039 tmp
= bits
& 0x40 ? 0x3c : 0x40;
7040 value
|= (unsigned long) tmp
<< 24;
7046 func (stream
, "<illegal constant %.8x:%x:%x>",
7052 /* printU determines whether the immediate value should be printed as
7054 unsigned printU
= 0;
7055 switch (insn
->mve_op
)
7059 /* We want this for instructions that don't have a 'signed' type. */
7063 case MVE_VMOV_IMM_TO_VEC
:
7070 func (stream
, "#%ld\t; 0x%.2lx", value
, value
);
7077 : "#%ld\t; 0x%.4lx", value
, value
);
7083 unsigned char valbytes
[4];
7086 /* Do this a byte at a time so we don't have to
7087 worry about the host's endianness. */
7088 valbytes
[0] = value
& 0xff;
7089 valbytes
[1] = (value
>> 8) & 0xff;
7090 valbytes
[2] = (value
>> 16) & 0xff;
7091 valbytes
[3] = (value
>> 24) & 0xff;
7093 floatformat_to_double
7094 (& floatformat_ieee_single_little
, valbytes
,
7097 func (stream
, "#%.7g\t; 0x%.8lx", fvalue
,
7104 : "#%ld\t; 0x%.8lx",
7105 (long) (((value
& 0x80000000L
) != 0)
7107 ? value
| ~0xffffffffL
: value
),
7112 func (stream
, "#0x%.8lx%.8lx", hival
, value
);
7122 print_mve_undefined (struct disassemble_info
*info
,
7123 enum mve_undefined undefined_code
)
7125 void *stream
= info
->stream
;
7126 fprintf_ftype func
= info
->fprintf_func
;
7128 func (stream
, "\t\tundefined instruction: ");
7130 switch (undefined_code
)
7133 func (stream
, "illegal size");
7137 func (stream
, "size equals zero");
7141 func (stream
, "size equals two");
7145 func (stream
, "size equals three");
7148 case UNDEF_SIZE_LE_1
:
7149 func (stream
, "size <= 1");
7152 case UNDEF_SIZE_NOT_0
:
7153 func (stream
, "size not equal to 0");
7156 case UNDEF_SIZE_NOT_2
:
7157 func (stream
, "size not equal to 2");
7160 case UNDEF_SIZE_NOT_3
:
7161 func (stream
, "size not equal to 3");
7164 case UNDEF_NOT_UNS_SIZE_0
:
7165 func (stream
, "not unsigned and size = zero");
7168 case UNDEF_NOT_UNS_SIZE_1
:
7169 func (stream
, "not unsigned and size = one");
7172 case UNDEF_NOT_UNSIGNED
:
7173 func (stream
, "not unsigned");
7176 case UNDEF_VCVT_IMM6
:
7177 func (stream
, "invalid imm6");
7180 case UNDEF_VCVT_FSI_IMM6
:
7181 func (stream
, "fsi = 0 and invalid imm6");
7184 case UNDEF_BAD_OP1_OP2
:
7185 func (stream
, "bad size with op2 = 2 and op1 = 0 or 1");
7188 case UNDEF_BAD_U_OP1_OP2
:
7189 func (stream
, "unsigned with op2 = 0 and op1 = 0 or 1");
7192 case UNDEF_OP_0_BAD_CMODE
:
7193 func (stream
, "op field equal 0 and bad cmode");
7196 case UNDEF_XCHG_UNS
:
7197 func (stream
, "exchange and unsigned together");
7207 print_mve_unpredictable (struct disassemble_info
*info
,
7208 enum mve_unpredictable unpredict_code
)
7210 void *stream
= info
->stream
;
7211 fprintf_ftype func
= info
->fprintf_func
;
7213 func (stream
, "%s: ", UNPREDICTABLE_INSTRUCTION
);
7215 switch (unpredict_code
)
7217 case UNPRED_IT_BLOCK
:
7218 func (stream
, "mve instruction in it block");
7221 case UNPRED_FCA_0_FCB_1
:
7222 func (stream
, "condition bits, fca = 0 and fcb = 1");
7226 func (stream
, "use of r13 (sp)");
7230 func (stream
, "use of r15 (pc)");
7234 func (stream
, "start register block > r4");
7238 func (stream
, "start register block > r6");
7241 case UNPRED_R13_AND_WB
:
7242 func (stream
, "use of r13 and write back");
7245 case UNPRED_Q_REGS_EQUAL
:
7247 "same vector register used for destination and other operand");
7251 func (stream
, "use of offset scaled");
7254 case UNPRED_GP_REGS_EQUAL
:
7255 func (stream
, "same general-purpose register used for both operands");
7258 case UNPRED_Q_REGS_EQ_AND_SIZE_1
:
7259 func (stream
, "use of identical q registers and size = 1");
7262 case UNPRED_Q_REGS_EQ_AND_SIZE_2
:
7263 func (stream
, "use of identical q registers and size = 1");
7271 /* Print register block operand for mve vld2/vld4/vst2/vld4. */
7274 print_mve_register_blocks (struct disassemble_info
*info
,
7275 unsigned long given
,
7276 enum mve_instructions matched_insn
)
7278 void *stream
= info
->stream
;
7279 fprintf_ftype func
= info
->fprintf_func
;
7281 unsigned long q_reg_start
= arm_decode_field_multiple (given
,
7284 switch (matched_insn
)
7288 if (q_reg_start
<= 6)
7289 func (stream
, "{q%ld, q%ld}", q_reg_start
, q_reg_start
+ 1);
7291 func (stream
, "<illegal reg q%ld>", q_reg_start
);
7296 if (q_reg_start
<= 4)
7297 func (stream
, "{q%ld, q%ld, q%ld, q%ld}", q_reg_start
,
7298 q_reg_start
+ 1, q_reg_start
+ 2,
7301 func (stream
, "<illegal reg q%ld>", q_reg_start
);
7310 print_mve_rounding_mode (struct disassemble_info
*info
,
7311 unsigned long given
,
7312 enum mve_instructions matched_insn
)
7314 void *stream
= info
->stream
;
7315 fprintf_ftype func
= info
->fprintf_func
;
7317 switch (matched_insn
)
7319 case MVE_VCVT_FROM_FP_TO_INT
:
7321 switch (arm_decode_field (given
, 8, 9))
7347 switch (arm_decode_field (given
, 7, 9))
7386 print_mve_vcvt_size (struct disassemble_info
*info
,
7387 unsigned long given
,
7388 enum mve_instructions matched_insn
)
7390 unsigned long mode
= 0;
7391 void *stream
= info
->stream
;
7392 fprintf_ftype func
= info
->fprintf_func
;
7394 switch (matched_insn
)
7396 case MVE_VCVT_FP_FIX_VEC
:
7398 mode
= (((given
& 0x200) >> 7)
7399 | ((given
& 0x10000000) >> 27)
7400 | ((given
& 0x100) >> 8));
7405 func (stream
, "f16.s16");
7409 func (stream
, "s16.f16");
7413 func (stream
, "f16.u16");
7417 func (stream
, "u16.f16");
7421 func (stream
, "f32.s32");
7425 func (stream
, "s32.f32");
7429 func (stream
, "f32.u32");
7433 func (stream
, "u32.f32");
7441 case MVE_VCVT_BETWEEN_FP_INT
:
7443 unsigned long size
= arm_decode_field (given
, 18, 19);
7444 unsigned long op
= arm_decode_field (given
, 7, 8);
7451 func (stream
, "f16.s16");
7455 func (stream
, "f16.u16");
7459 func (stream
, "s16.f16");
7463 func (stream
, "u16.f16");
7475 func (stream
, "f32.s32");
7479 func (stream
, "f32.u32");
7483 func (stream
, "s32.f32");
7487 func (stream
, "u32.f32");
7494 case MVE_VCVT_FP_HALF_FP
:
7496 unsigned long op
= arm_decode_field (given
, 28, 28);
7498 func (stream
, "f16.f32");
7500 func (stream
, "f32.f16");
7504 case MVE_VCVT_FROM_FP_TO_INT
:
7506 unsigned long size
= arm_decode_field_multiple (given
, 7, 7, 18, 19);
7511 func (stream
, "s16.f16");
7515 func (stream
, "u16.f16");
7519 func (stream
, "s32.f32");
7523 func (stream
, "u32.f32");
7538 print_mve_rotate (struct disassemble_info
*info
, unsigned long rot
,
7539 unsigned long rot_width
)
7541 void *stream
= info
->stream
;
7542 fprintf_ftype func
= info
->fprintf_func
;
7549 func (stream
, "90");
7552 func (stream
, "270");
7558 else if (rot_width
== 2)
7566 func (stream
, "90");
7569 func (stream
, "180");
7572 func (stream
, "270");
7581 print_instruction_predicate (struct disassemble_info
*info
)
7583 void *stream
= info
->stream
;
7584 fprintf_ftype func
= info
->fprintf_func
;
7586 if (vpt_block_state
.next_pred_state
== PRED_THEN
)
7588 else if (vpt_block_state
.next_pred_state
== PRED_ELSE
)
7593 print_mve_size (struct disassemble_info
*info
,
7595 enum mve_instructions matched_insn
)
7597 void *stream
= info
->stream
;
7598 fprintf_ftype func
= info
->fprintf_func
;
7600 switch (matched_insn
)
7606 case MVE_VADD_VEC_T1
:
7607 case MVE_VADD_VEC_T2
:
7613 case MVE_VCMP_VEC_T1
:
7614 case MVE_VCMP_VEC_T2
:
7615 case MVE_VCMP_VEC_T3
:
7616 case MVE_VCMP_VEC_T4
:
7617 case MVE_VCMP_VEC_T5
:
7618 case MVE_VCMP_VEC_T6
:
7631 case MVE_VLDRB_GATHER_T1
:
7632 case MVE_VLDRH_GATHER_T2
:
7633 case MVE_VLDRW_GATHER_T3
:
7634 case MVE_VLDRD_GATHER_T4
:
7647 case MVE_VMUL_VEC_T1
:
7648 case MVE_VMUL_VEC_T2
:
7654 case MVE_VPT_VEC_T1
:
7655 case MVE_VPT_VEC_T2
:
7656 case MVE_VPT_VEC_T3
:
7657 case MVE_VPT_VEC_T4
:
7658 case MVE_VPT_VEC_T5
:
7659 case MVE_VPT_VEC_T6
:
7671 case MVE_VQDMULH_T1
:
7672 case MVE_VQRDMULH_T2
:
7673 case MVE_VQDMULH_T3
:
7674 case MVE_VQRDMULH_T4
:
7693 case MVE_VSTRB_SCATTER_T1
:
7694 case MVE_VSTRH_SCATTER_T2
:
7695 case MVE_VSTRW_SCATTER_T3
:
7698 case MVE_VSUB_VEC_T1
:
7699 case MVE_VSUB_VEC_T2
:
7701 func (stream
, "%s", mve_vec_sizename
[size
]);
7703 func (stream
, "<undef size>");
7707 case MVE_VADD_FP_T1
:
7708 case MVE_VADD_FP_T2
:
7709 case MVE_VSUB_FP_T1
:
7710 case MVE_VSUB_FP_T2
:
7711 case MVE_VCMP_FP_T1
:
7712 case MVE_VCMP_FP_T2
:
7713 case MVE_VFMA_FP_SCALAR
:
7716 case MVE_VFMAS_FP_SCALAR
:
7718 case MVE_VMAXNMA_FP
:
7719 case MVE_VMAXNMV_FP
:
7720 case MVE_VMAXNMAV_FP
:
7722 case MVE_VMINNMA_FP
:
7723 case MVE_VMINNMV_FP
:
7724 case MVE_VMINNMAV_FP
:
7725 case MVE_VMUL_FP_T1
:
7726 case MVE_VMUL_FP_T2
:
7730 func (stream
, "32");
7732 func (stream
, "16");
7738 case MVE_VMLADAV_T1
:
7740 case MVE_VMLSDAV_T1
:
7743 case MVE_VQDMULL_T1
:
7744 case MVE_VQDMULL_T2
:
7748 func (stream
, "16");
7750 func (stream
, "32");
7757 func (stream
, "16");
7764 func (stream
, "32");
7767 func (stream
, "16");
7777 case MVE_VMOV_GP_TO_VEC_LANE
:
7778 case MVE_VMOV_VEC_LANE_TO_GP
:
7782 func (stream
, "32");
7787 func (stream
, "16");
7790 case 8: case 9: case 10: case 11:
7791 case 12: case 13: case 14: case 15:
7800 case MVE_VMOV_IMM_TO_VEC
:
7803 case 0: case 4: case 8:
7804 case 12: case 24: case 26:
7805 func (stream
, "i32");
7808 func (stream
, "i16");
7811 func (stream
, "i8");
7814 func (stream
, "i64");
7817 func (stream
, "f32");
7824 case MVE_VMULL_POLY
:
7826 func (stream
, "p8");
7828 func (stream
, "p16");
7834 case 0: case 2: case 4:
7835 case 6: case 12: case 13:
7836 func (stream
, "32");
7840 func (stream
, "16");
7854 func (stream
, "32");
7858 func (stream
, "16");
7876 func (stream
, "16");
7880 func (stream
, "32");
7905 func (stream
, "16");
7908 case 4: case 5: case 6: case 7:
7909 func (stream
, "32");
7924 print_mve_shift_n (struct disassemble_info
*info
, long given
,
7925 enum mve_instructions matched_insn
)
7927 void *stream
= info
->stream
;
7928 fprintf_ftype func
= info
->fprintf_func
;
7931 = matched_insn
== MVE_VQSHL_T2
7932 || matched_insn
== MVE_VQSHLU_T3
7933 || matched_insn
== MVE_VSHL_T1
7934 || matched_insn
== MVE_VSHLL_T1
7935 || matched_insn
== MVE_VSLI
;
7937 unsigned imm6
= (given
& 0x3f0000) >> 16;
7939 if (matched_insn
== MVE_VSHLL_T1
)
7942 unsigned shiftAmount
= 0;
7943 if ((imm6
& 0x20) != 0)
7944 shiftAmount
= startAt0
? imm6
- 32 : 64 - imm6
;
7945 else if ((imm6
& 0x10) != 0)
7946 shiftAmount
= startAt0
? imm6
- 16 : 32 - imm6
;
7947 else if ((imm6
& 0x08) != 0)
7948 shiftAmount
= startAt0
? imm6
- 8 : 16 - imm6
;
7950 print_mve_undefined (info
, UNDEF_SIZE_0
);
7952 func (stream
, "%u", shiftAmount
);
7956 print_vec_condition (struct disassemble_info
*info
, long given
,
7957 enum mve_instructions matched_insn
)
7959 void *stream
= info
->stream
;
7960 fprintf_ftype func
= info
->fprintf_func
;
7963 switch (matched_insn
)
7966 case MVE_VCMP_FP_T1
:
7967 vec_cond
= (((given
& 0x1000) >> 10)
7968 | ((given
& 1) << 1)
7969 | ((given
& 0x0080) >> 7));
7970 func (stream
, "%s",vec_condnames
[vec_cond
]);
7974 case MVE_VCMP_FP_T2
:
7975 vec_cond
= (((given
& 0x1000) >> 10)
7976 | ((given
& 0x0020) >> 4)
7977 | ((given
& 0x0080) >> 7));
7978 func (stream
, "%s",vec_condnames
[vec_cond
]);
7981 case MVE_VPT_VEC_T1
:
7982 case MVE_VCMP_VEC_T1
:
7983 vec_cond
= (given
& 0x0080) >> 7;
7984 func (stream
, "%s",vec_condnames
[vec_cond
]);
7987 case MVE_VPT_VEC_T2
:
7988 case MVE_VCMP_VEC_T2
:
7989 vec_cond
= 2 | ((given
& 0x0080) >> 7);
7990 func (stream
, "%s",vec_condnames
[vec_cond
]);
7993 case MVE_VPT_VEC_T3
:
7994 case MVE_VCMP_VEC_T3
:
7995 vec_cond
= 4 | ((given
& 1) << 1) | ((given
& 0x0080) >> 7);
7996 func (stream
, "%s",vec_condnames
[vec_cond
]);
7999 case MVE_VPT_VEC_T4
:
8000 case MVE_VCMP_VEC_T4
:
8001 vec_cond
= (given
& 0x0080) >> 7;
8002 func (stream
, "%s",vec_condnames
[vec_cond
]);
8005 case MVE_VPT_VEC_T5
:
8006 case MVE_VCMP_VEC_T5
:
8007 vec_cond
= 2 | ((given
& 0x0080) >> 7);
8008 func (stream
, "%s",vec_condnames
[vec_cond
]);
8011 case MVE_VPT_VEC_T6
:
8012 case MVE_VCMP_VEC_T6
:
8013 vec_cond
= 4 | ((given
& 0x0020) >> 4) | ((given
& 0x0080) >> 7);
8014 func (stream
, "%s",vec_condnames
[vec_cond
]);
8029 #define WRITEBACK_BIT_SET (given & (1 << W_BIT))
8030 #define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
8031 #define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
8032 #define PRE_BIT_SET (given & (1 << P_BIT))
8035 /* Print one coprocessor instruction on INFO->STREAM.
8036 Return TRUE if the instuction matched, FALSE if this is not a
8037 recognised coprocessor instruction. */
8040 print_insn_coprocessor_1 (const struct sopcode32
*opcodes
,
8042 struct disassemble_info
*info
,
8046 const struct sopcode32
*insn
;
8047 void *stream
= info
->stream
;
8048 fprintf_ftype func
= info
->fprintf_func
;
8050 unsigned long value
= 0;
8053 struct arm_private_data
*private_data
= info
->private_data
;
8054 arm_feature_set allowed_arches
= ARM_ARCH_NONE
;
8055 arm_feature_set arm_ext_v8_1m_main
=
8056 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
);
8058 allowed_arches
= private_data
->features
;
8060 for (insn
= opcodes
; insn
->assembler
; insn
++)
8062 unsigned long u_reg
= 16;
8063 bool is_unpredictable
= false;
8064 signed long value_in_comment
= 0;
8067 if (ARM_FEATURE_ZERO (insn
->arch
))
8068 switch (insn
->value
)
8070 case SENTINEL_IWMMXT_START
:
8071 if (info
->mach
!= bfd_mach_arm_XScale
8072 && info
->mach
!= bfd_mach_arm_iWMMXt
8073 && info
->mach
!= bfd_mach_arm_iWMMXt2
)
8076 while ((! ARM_FEATURE_ZERO (insn
->arch
))
8077 && insn
->value
!= SENTINEL_IWMMXT_END
);
8080 case SENTINEL_IWMMXT_END
:
8083 case SENTINEL_GENERIC_START
:
8084 allowed_arches
= private_data
->features
;
8092 value
= insn
->value
;
8093 cp_num
= (given
>> 8) & 0xf;
8097 /* The high 4 bits are 0xe for Arm conditional instructions, and
8098 0xe for arm unconditional instructions. The rest of the
8099 encoding is the same. */
8101 value
|= 0xe0000000;
8109 /* Only match unconditional instuctions against unconditional
8111 if ((given
& 0xf0000000) == 0xf0000000)
8118 cond
= (given
>> 28) & 0xf;
8124 if ((insn
->isa
== T32
&& !thumb
)
8125 || (insn
->isa
== ARM
&& thumb
))
8128 if ((given
& mask
) != value
)
8131 if (! ARM_CPU_HAS_FEATURE (insn
->arch
, allowed_arches
))
8134 if (insn
->value
== 0xfe000010 /* mcr2 */
8135 || insn
->value
== 0xfe100010 /* mrc2 */
8136 || insn
->value
== 0xfc100000 /* ldc2 */
8137 || insn
->value
== 0xfc000000) /* stc2 */
8139 if (cp_num
== 9 || cp_num
== 10 || cp_num
== 11)
8140 is_unpredictable
= true;
8142 /* Armv8.1-M Mainline FP & MVE instructions. */
8143 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main
, allowed_arches
)
8144 && !ARM_CPU_IS_ANY (allowed_arches
)
8145 && (cp_num
== 8 || cp_num
== 14 || cp_num
== 15))
8149 else if (insn
->value
== 0x0e000000 /* cdp */
8150 || insn
->value
== 0xfe000000 /* cdp2 */
8151 || insn
->value
== 0x0e000010 /* mcr */
8152 || insn
->value
== 0x0e100010 /* mrc */
8153 || insn
->value
== 0x0c100000 /* ldc */
8154 || insn
->value
== 0x0c000000) /* stc */
8156 /* Floating-point instructions. */
8157 if (cp_num
== 9 || cp_num
== 10 || cp_num
== 11)
8160 /* Armv8.1-M Mainline FP & MVE instructions. */
8161 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main
, allowed_arches
)
8162 && !ARM_CPU_IS_ANY (allowed_arches
)
8163 && (cp_num
== 8 || cp_num
== 14 || cp_num
== 15))
8166 else if ((insn
->value
== 0xec100f80 /* vldr (system register) */
8167 || insn
->value
== 0xec000f80) /* vstr (system register) */
8168 && arm_decode_field (given
, 24, 24) == 0
8169 && arm_decode_field (given
, 21, 21) == 0)
8170 /* If the P and W bits are both 0 then these encodings match the MVE
8171 VLDR and VSTR instructions, these are in a different table, so we
8172 don't let it match here. */
8175 for (c
= insn
->assembler
; *c
; c
++)
8179 const char mod
= *++c
;
8183 func (stream
, "%%");
8189 int rn
= (given
>> 16) & 0xf;
8190 bfd_vma offset
= given
& 0xff;
8193 offset
= given
& 0x7f;
8195 func (stream
, "[%s", arm_regnames
[(given
>> 16) & 0xf]);
8197 if (PRE_BIT_SET
|| WRITEBACK_BIT_SET
)
8199 /* Not unindexed. The offset is scaled. */
8201 /* vldr.16/vstr.16 will shift the address
8202 left by 1 bit only. */
8203 offset
= offset
* 2;
8205 offset
= offset
* 4;
8207 if (NEGATIVE_BIT_SET
)
8210 value_in_comment
= offset
;
8216 func (stream
, ", #%d]%s",
8218 WRITEBACK_BIT_SET
? "!" : "");
8219 else if (NEGATIVE_BIT_SET
)
8220 func (stream
, ", #-0]");
8228 if (WRITEBACK_BIT_SET
)
8231 func (stream
, ", #%d", (int) offset
);
8232 else if (NEGATIVE_BIT_SET
)
8233 func (stream
, ", #-0");
8237 func (stream
, ", {%s%d}",
8238 (NEGATIVE_BIT_SET
&& !offset
) ? "-" : "",
8240 value_in_comment
= offset
;
8243 if (rn
== 15 && (PRE_BIT_SET
|| WRITEBACK_BIT_SET
))
8245 func (stream
, "\t; ");
8246 /* For unaligned PCs, apply off-by-alignment
8248 info
->print_address_func (offset
+ pc
8249 + info
->bytes_per_chunk
* 2
8258 int regno
= ((given
>> 12) & 0xf) | ((given
>> (22 - 4)) & 0x10);
8259 int offset
= (given
>> 1) & 0x3f;
8262 func (stream
, "{d%d}", regno
);
8263 else if (regno
+ offset
> 32)
8264 func (stream
, "{d%d-<overflow reg d%d>}", regno
, regno
+ offset
- 1);
8266 func (stream
, "{d%d-d%d}", regno
, regno
+ offset
- 1);
8272 bool single
= ((given
>> 8) & 1) == 0;
8273 char reg_prefix
= single
? 's' : 'd';
8274 int Dreg
= (given
>> 22) & 0x1;
8275 int Vdreg
= (given
>> 12) & 0xf;
8276 int reg
= single
? ((Vdreg
<< 1) | Dreg
)
8277 : ((Dreg
<< 4) | Vdreg
);
8278 int num
= (given
>> (single
? 0 : 1)) & 0x7f;
8279 int maxreg
= single
? 31 : 15;
8280 int topreg
= reg
+ num
- 1;
8283 func (stream
, "{VPR}");
8285 func (stream
, "{%c%d, VPR}", reg_prefix
, reg
);
8286 else if (topreg
> maxreg
)
8287 func (stream
, "{%c%d-<overflow reg d%d, VPR}",
8288 reg_prefix
, reg
, single
? topreg
>> 1 : topreg
);
8290 func (stream
, "{%c%d-%c%d, VPR}", reg_prefix
, reg
,
8291 reg_prefix
, topreg
);
8296 if (cond
!= COND_UNCOND
)
8297 is_unpredictable
= true;
8301 if (cond
!= COND_UNCOND
&& cp_num
== 9)
8302 is_unpredictable
= true;
8306 func (stream
, "%s", arm_conditional
[cond
]);
8310 /* Print a Cirrus/DSP shift immediate. */
8311 /* Immediates are 7bit signed ints with bits 0..3 in
8312 bits 0..3 of opcode and bits 4..6 in bits 5..7
8317 imm
= (given
& 0xf) | ((given
& 0xe0) >> 1);
8319 /* Is ``imm'' a negative number? */
8323 func (stream
, "%d", imm
);
8331 = arm_decode_field_multiple (given
, 13, 15, 22, 22);
8336 func (stream
, "FPSCR");
8339 func (stream
, "FPSCR_nzcvqc");
8342 func (stream
, "VPR");
8345 func (stream
, "P0");
8348 func (stream
, "FPCXTNS");
8351 func (stream
, "FPCXTS");
8354 func (stream
, "<invalid reg %lu>", regno
);
8361 switch (given
& 0x00408000)
8378 switch (given
& 0x00080080)
8390 func (stream
, _("<illegal precision>"));
8396 switch (given
& 0x00408000)
8414 switch (given
& 0x60)
8430 case '0': case '1': case '2': case '3': case '4':
8431 case '5': case '6': case '7': case '8': case '9':
8435 c
= arm_decode_bitfield (c
, given
, &value
, &width
);
8441 is_unpredictable
= true;
8446 /* Eat the 'u' character. */
8450 is_unpredictable
= true;
8453 func (stream
, "%s", arm_regnames
[value
]);
8456 if (given
& (1 << 6))
8460 func (stream
, "d%ld", value
);
8465 func (stream
, "<illegal reg q%ld.5>", value
>> 1);
8467 func (stream
, "q%ld", value
>> 1);
8470 func (stream
, "%ld", value
);
8471 value_in_comment
= value
;
8475 /* Converts immediate 8 bit back to float value. */
8476 unsigned floatVal
= (value
& 0x80) << 24
8477 | (value
& 0x3F) << 19
8478 | ((value
& 0x40) ? (0xF8 << 22) : (1 << 30));
8480 /* Quarter float have a maximum value of 31.0.
8481 Get floating point value multiplied by 1e7.
8482 The maximum value stays in limit of a 32-bit int. */
8484 (78125 << (((floatVal
>> 23) & 0xFF) - 124)) *
8485 (16 + (value
& 0xF));
8487 if (!(decVal
% 1000000))
8488 func (stream
, "%ld\t; 0x%08x %c%u.%01u", value
,
8489 floatVal
, value
& 0x80 ? '-' : ' ',
8491 decVal
% 10000000 / 1000000);
8492 else if (!(decVal
% 10000))
8493 func (stream
, "%ld\t; 0x%08x %c%u.%03u", value
,
8494 floatVal
, value
& 0x80 ? '-' : ' ',
8496 decVal
% 10000000 / 10000);
8498 func (stream
, "%ld\t; 0x%08x %c%u.%07u", value
,
8499 floatVal
, value
& 0x80 ? '-' : ' ',
8500 decVal
/ 10000000, decVal
% 10000000);
8505 int from
= (given
& (1 << 7)) ? 32 : 16;
8506 func (stream
, "%ld", from
- value
);
8512 func (stream
, "#%s", arm_fp_const
[value
& 7]);
8514 func (stream
, "f%ld", value
);
8519 func (stream
, "%s", iwmmxt_wwnames
[value
]);
8521 func (stream
, "%s", iwmmxt_wwssnames
[value
]);
8525 func (stream
, "%s", iwmmxt_regnames
[value
]);
8528 func (stream
, "%s", iwmmxt_cregnames
[value
]);
8532 func (stream
, "0x%lx", (value
& 0xffffffffUL
));
8539 func (stream
, "eq");
8543 func (stream
, "vs");
8547 func (stream
, "ge");
8551 func (stream
, "gt");
8555 func (stream
, "??");
8563 func (stream
, "%c", *c
);
8567 if (value
== ((1ul << width
) - 1))
8568 func (stream
, "%c", *c
);
8571 func (stream
, "%c", c
[(1 << width
) - (int) value
]);
8583 int single
= *c
++ == 'y';
8588 case '4': /* Sm pair */
8589 case '0': /* Sm, Dm */
8590 regno
= given
& 0x0000000f;
8594 regno
+= (given
>> 5) & 1;
8597 regno
+= ((given
>> 5) & 1) << 4;
8600 case '1': /* Sd, Dd */
8601 regno
= (given
>> 12) & 0x0000000f;
8605 regno
+= (given
>> 22) & 1;
8608 regno
+= ((given
>> 22) & 1) << 4;
8611 case '2': /* Sn, Dn */
8612 regno
= (given
>> 16) & 0x0000000f;
8616 regno
+= (given
>> 7) & 1;
8619 regno
+= ((given
>> 7) & 1) << 4;
8622 case '3': /* List */
8624 regno
= (given
>> 12) & 0x0000000f;
8628 regno
+= (given
>> 22) & 1;
8631 regno
+= ((given
>> 22) & 1) << 4;
8638 func (stream
, "%c%d", single
? 's' : 'd', regno
);
8642 int count
= given
& 0xff;
8649 func (stream
, "-%c%d",
8657 func (stream
, ", %c%d", single
? 's' : 'd',
8663 switch (given
& 0x00400100)
8665 case 0x00000000: func (stream
, "b"); break;
8666 case 0x00400000: func (stream
, "h"); break;
8667 case 0x00000100: func (stream
, "w"); break;
8668 case 0x00400100: func (stream
, "d"); break;
8676 /* given (20, 23) | given (0, 3) */
8677 value
= ((given
>> 16) & 0xf0) | (given
& 0xf);
8678 func (stream
, "%d", (int) value
);
8683 /* This is like the 'A' operator, except that if
8684 the width field "M" is zero, then the offset is
8685 *not* multiplied by four. */
8687 int offset
= given
& 0xff;
8688 int multiplier
= (given
& 0x00000100) ? 4 : 1;
8690 func (stream
, "[%s", arm_regnames
[(given
>> 16) & 0xf]);
8694 value_in_comment
= offset
* multiplier
;
8695 if (NEGATIVE_BIT_SET
)
8696 value_in_comment
= - value_in_comment
;
8702 func (stream
, ", #%s%d]%s",
8703 NEGATIVE_BIT_SET
? "-" : "",
8704 offset
* multiplier
,
8705 WRITEBACK_BIT_SET
? "!" : "");
8707 func (stream
, "], #%s%d",
8708 NEGATIVE_BIT_SET
? "-" : "",
8709 offset
* multiplier
);
8718 int imm4
= (given
>> 4) & 0xf;
8719 int puw_bits
= ((given
>> 22) & 6) | ((given
>> W_BIT
) & 1);
8720 int ubit
= ! NEGATIVE_BIT_SET
;
8721 const char *rm
= arm_regnames
[given
& 0xf];
8722 const char *rn
= arm_regnames
[(given
>> 16) & 0xf];
8728 func (stream
, "[%s], %c%s", rn
, ubit
? '+' : '-', rm
);
8730 func (stream
, ", lsl #%d", imm4
);
8737 func (stream
, "[%s, %c%s", rn
, ubit
? '+' : '-', rm
);
8739 func (stream
, ", lsl #%d", imm4
);
8741 if (puw_bits
== 5 || puw_bits
== 7)
8746 func (stream
, "INVALID");
8754 imm5
= ((given
& 0x100) >> 4) | (given
& 0xf);
8755 func (stream
, "%ld", (imm5
== 0) ? 32 : imm5
);
8764 func (stream
, "%c", *c
);
8767 if (value_in_comment
> 32 || value_in_comment
< -16)
8768 func (stream
, "\t; 0x%lx", (value_in_comment
& 0xffffffffUL
));
8770 if (is_unpredictable
)
8771 func (stream
, UNPREDICTABLE_INSTRUCTION
);
8779 print_insn_coprocessor (bfd_vma pc
,
8780 struct disassemble_info
*info
,
8784 return print_insn_coprocessor_1 (coprocessor_opcodes
,
8785 pc
, info
, given
, thumb
);
8789 print_insn_generic_coprocessor (bfd_vma pc
,
8790 struct disassemble_info
*info
,
8794 return print_insn_coprocessor_1 (generic_coprocessor_opcodes
,
8795 pc
, info
, given
, thumb
);
8798 /* Decodes and prints ARM addressing modes. Returns the offset
8799 used in the address, if any, if it is worthwhile printing the
8800 offset as a hexadecimal value in a comment at the end of the
8801 line of disassembly. */
8804 print_arm_address (bfd_vma pc
, struct disassemble_info
*info
, long given
)
8806 void *stream
= info
->stream
;
8807 fprintf_ftype func
= info
->fprintf_func
;
8810 if (((given
& 0x000f0000) == 0x000f0000)
8811 && ((given
& 0x02000000) == 0))
8813 offset
= given
& 0xfff;
8815 func (stream
, "[pc");
8819 /* Pre-indexed. Elide offset of positive zero when
8821 if (WRITEBACK_BIT_SET
|| NEGATIVE_BIT_SET
|| offset
)
8822 func (stream
, ", #%s%d", NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
8824 if (NEGATIVE_BIT_SET
)
8829 /* Cope with the possibility of write-back
8830 being used. Probably a very dangerous thing
8831 for the programmer to do, but who are we to
8833 func (stream
, "]%s", WRITEBACK_BIT_SET
? "!" : "");
8835 else /* Post indexed. */
8837 func (stream
, "], #%s%d", NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
8839 /* Ie ignore the offset. */
8843 func (stream
, "\t; ");
8844 info
->print_address_func (offset
, info
);
8849 func (stream
, "[%s",
8850 arm_regnames
[(given
>> 16) & 0xf]);
8854 if ((given
& 0x02000000) == 0)
8856 /* Elide offset of positive zero when non-writeback. */
8857 offset
= given
& 0xfff;
8858 if (WRITEBACK_BIT_SET
|| NEGATIVE_BIT_SET
|| offset
)
8859 func (stream
, ", #%s%d", NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
8863 func (stream
, ", %s", NEGATIVE_BIT_SET
? "-" : "");
8864 arm_decode_shift (given
, func
, stream
, true);
8867 func (stream
, "]%s",
8868 WRITEBACK_BIT_SET
? "!" : "");
8872 if ((given
& 0x02000000) == 0)
8874 /* Always show offset. */
8875 offset
= given
& 0xfff;
8876 func (stream
, "], #%s%d",
8877 NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
8881 func (stream
, "], %s",
8882 NEGATIVE_BIT_SET
? "-" : "");
8883 arm_decode_shift (given
, func
, stream
, true);
8886 if (NEGATIVE_BIT_SET
)
8890 return (signed long) offset
;
8894 /* Print one cde instruction on INFO->STREAM.
8895 Return TRUE if the instuction matched, FALSE if this is not a
8896 recognised cde instruction. */
8898 print_insn_cde (struct disassemble_info
*info
, long given
, bool thumb
)
8900 const struct cdeopcode32
*insn
;
8901 void *stream
= info
->stream
;
8902 fprintf_ftype func
= info
->fprintf_func
;
8906 /* Manually extract the coprocessor code from a known point.
8907 This position is the same across all CDE instructions. */
8908 for (insn
= cde_opcodes
; insn
->assembler
; insn
++)
8910 uint16_t coproc
= (given
>> insn
->coproc_shift
) & insn
->coproc_mask
;
8911 uint16_t coproc_mask
= 1 << coproc
;
8912 if (! (coproc_mask
& cde_coprocs
))
8915 if ((given
& insn
->mask
) == insn
->value
)
8917 bool is_unpredictable
= false;
8920 for (c
= insn
->assembler
; *c
; c
++)
8927 func (stream
, "%%");
8930 case '0': case '1': case '2': case '3': case '4':
8931 case '5': case '6': case '7': case '8': case '9':
8934 unsigned long value
;
8936 c
= arm_decode_bitfield (c
, given
, &value
, &width
);
8942 is_unpredictable
= true;
8946 is_unpredictable
= true;
8949 func (stream
, "%s", arm_regnames
[value
]);
8954 func (stream
, "%s", "APSR_nzcv");
8956 func (stream
, "%s", arm_regnames
[value
]);
8960 func (stream
, "%s", arm_regnames
[value
+ 1]);
8964 func (stream
, "%ld", value
);
8968 if (given
& (1 << 6))
8969 func (stream
, "q%ld", value
>> 1);
8970 else if (given
& (1 << 24))
8971 func (stream
, "d%ld", value
);
8974 /* Encoding for S register is different than for D and
8975 Q registers. S registers are encoded using the top
8976 single bit in position 22 as the lowest bit of the
8977 register number, while for Q and D it represents the
8978 highest bit of the register number. */
8979 uint8_t top_bit
= (value
>> 4) & 1;
8980 uint8_t tmp
= (value
<< 1) & 0x1e;
8981 uint8_t res
= tmp
| top_bit
;
8982 func (stream
, "s%u", res
);
8994 uint8_t proc_number
= (given
>> 8) & 0x7;
8995 func (stream
, "p%u", proc_number
);
9001 uint8_t a_offset
= 28;
9002 if (given
& (1 << a_offset
))
9011 func (stream
, "%c", *c
);
9014 if (is_unpredictable
)
9015 func (stream
, UNPREDICTABLE_INSTRUCTION
);
9027 /* Print one neon instruction on INFO->STREAM.
9028 Return TRUE if the instuction matched, FALSE if this is not a
9029 recognised neon instruction. */
9032 print_insn_neon (struct disassemble_info
*info
, long given
, bool thumb
)
9034 const struct opcode32
*insn
;
9035 void *stream
= info
->stream
;
9036 fprintf_ftype func
= info
->fprintf_func
;
9040 if ((given
& 0xef000000) == 0xef000000)
9042 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
9043 unsigned long bit28
= given
& (1 << 28);
9045 given
&= 0x00ffffff;
9047 given
|= 0xf3000000;
9049 given
|= 0xf2000000;
9051 else if ((given
& 0xff000000) == 0xf9000000)
9052 given
^= 0xf9000000 ^ 0xf4000000;
9053 /* BFloat16 neon instructions without special top byte handling. */
9054 else if ((given
& 0xff000000) == 0xfe000000
9055 || (given
& 0xff000000) == 0xfc000000)
9057 /* vdup is also a valid neon instruction. */
9058 else if ((given
& 0xff900f5f) != 0xee800b10)
9062 for (insn
= neon_opcodes
; insn
->assembler
; insn
++)
9064 unsigned long cond_mask
= insn
->mask
;
9065 unsigned long cond_value
= insn
->value
;
9070 if ((cond_mask
& 0xf0000000) == 0) {
9071 /* For the entries in neon_opcodes, an opcode mask/value with
9072 the high 4 bits equal to 0 indicates a conditional
9073 instruction. For thumb however, we need to include those
9074 bits in the instruction matching. */
9075 cond_mask
|= 0xf0000000;
9076 /* Furthermore, the thumb encoding of a conditional instruction
9077 will have the high 4 bits equal to 0xe. */
9078 cond_value
|= 0xe0000000;
9087 if ((given
& 0xf0000000) == 0xf0000000)
9089 /* If the instruction is unconditional, update the mask to only
9090 match against unconditional opcode values. */
9091 cond_mask
|= 0xf0000000;
9096 cond
= (given
>> 28) & 0xf;
9102 if ((given
& cond_mask
) == cond_value
)
9104 signed long value_in_comment
= 0;
9105 bool is_unpredictable
= false;
9108 for (c
= insn
->assembler
; *c
; c
++)
9115 func (stream
, "%%");
9119 if (thumb
&& ifthen_state
)
9120 is_unpredictable
= true;
9124 func (stream
, "%s", arm_conditional
[cond
]);
9129 static const unsigned char enc
[16] =
9131 0x4, 0x14, /* st4 0,1 */
9143 int rd
= ((given
>> 12) & 0xf) | (((given
>> 22) & 1) << 4);
9144 int rn
= ((given
>> 16) & 0xf);
9145 int rm
= ((given
>> 0) & 0xf);
9146 int align
= ((given
>> 4) & 0x3);
9147 int type
= ((given
>> 8) & 0xf);
9148 int n
= enc
[type
] & 0xf;
9149 int stride
= (enc
[type
] >> 4) + 1;
9154 for (ix
= 0; ix
!= n
; ix
++)
9155 func (stream
, "%sd%d", ix
? "," : "", rd
+ ix
* stride
);
9157 func (stream
, "d%d", rd
);
9159 func (stream
, "d%d-d%d", rd
, rd
+ n
- 1);
9160 func (stream
, "}, [%s", arm_regnames
[rn
]);
9162 func (stream
, " :%d", 32 << align
);
9167 func (stream
, ", %s", arm_regnames
[rm
]);
9173 int rd
= ((given
>> 12) & 0xf) | (((given
>> 22) & 1) << 4);
9174 int rn
= ((given
>> 16) & 0xf);
9175 int rm
= ((given
>> 0) & 0xf);
9176 int idx_align
= ((given
>> 4) & 0xf);
9178 int size
= ((given
>> 10) & 0x3);
9179 int idx
= idx_align
>> (size
+ 1);
9180 int length
= ((given
>> 8) & 3) + 1;
9184 if (length
> 1 && size
> 0)
9185 stride
= (idx_align
& (1 << size
)) ? 2 : 1;
9191 int amask
= (1 << size
) - 1;
9192 if ((idx_align
& (1 << size
)) != 0)
9196 if ((idx_align
& amask
) == amask
)
9198 else if ((idx_align
& amask
) != 0)
9205 if (size
== 2 && (idx_align
& 2) != 0)
9207 align
= (idx_align
& 1) ? 16 << size
: 0;
9211 if ((size
== 2 && (idx_align
& 3) != 0)
9212 || (idx_align
& 1) != 0)
9219 if ((idx_align
& 3) == 3)
9221 align
= (idx_align
& 3) * 64;
9224 align
= (idx_align
& 1) ? 32 << size
: 0;
9232 for (i
= 0; i
< length
; i
++)
9233 func (stream
, "%sd%d[%d]", (i
== 0) ? "" : ",",
9234 rd
+ i
* stride
, idx
);
9235 func (stream
, "}, [%s", arm_regnames
[rn
]);
9237 func (stream
, " :%d", align
);
9242 func (stream
, ", %s", arm_regnames
[rm
]);
9248 int rd
= ((given
>> 12) & 0xf) | (((given
>> 22) & 1) << 4);
9249 int rn
= ((given
>> 16) & 0xf);
9250 int rm
= ((given
>> 0) & 0xf);
9251 int align
= ((given
>> 4) & 0x1);
9252 int size
= ((given
>> 6) & 0x3);
9253 int type
= ((given
>> 8) & 0x3);
9255 int stride
= ((given
>> 5) & 0x1);
9258 if (stride
&& (n
== 1))
9265 for (ix
= 0; ix
!= n
; ix
++)
9266 func (stream
, "%sd%d[]", ix
? "," : "", rd
+ ix
* stride
);
9268 func (stream
, "d%d[]", rd
);
9270 func (stream
, "d%d[]-d%d[]", rd
, rd
+ n
- 1);
9271 func (stream
, "}, [%s", arm_regnames
[rn
]);
9274 align
= (8 * (type
+ 1)) << size
;
9276 align
= (size
> 1) ? align
>> 1 : align
;
9277 if (type
== 2 || (type
== 0 && !size
))
9278 func (stream
, " :<bad align %d>", align
);
9280 func (stream
, " :%d", align
);
9286 func (stream
, ", %s", arm_regnames
[rm
]);
9292 int raw_reg
= (given
& 0xf) | ((given
>> 1) & 0x10);
9293 int size
= (given
>> 20) & 3;
9294 int reg
= raw_reg
& ((4 << size
) - 1);
9295 int ix
= raw_reg
>> size
>> 2;
9297 func (stream
, "d%d[%d]", reg
, ix
);
9302 /* Neon encoded constant for mov, mvn, vorr, vbic. */
9305 int cmode
= (given
>> 8) & 0xf;
9306 int op
= (given
>> 5) & 0x1;
9307 unsigned long value
= 0, hival
= 0;
9312 bits
|= ((given
>> 24) & 1) << 7;
9313 bits
|= ((given
>> 16) & 7) << 4;
9314 bits
|= ((given
>> 0) & 15) << 0;
9318 shift
= (cmode
>> 1) & 3;
9319 value
= (unsigned long) bits
<< (8 * shift
);
9322 else if (cmode
< 12)
9324 shift
= (cmode
>> 1) & 1;
9325 value
= (unsigned long) bits
<< (8 * shift
);
9328 else if (cmode
< 14)
9330 shift
= (cmode
& 1) + 1;
9331 value
= (unsigned long) bits
<< (8 * shift
);
9332 value
|= (1ul << (8 * shift
)) - 1;
9335 else if (cmode
== 14)
9339 /* Bit replication into bytes. */
9345 for (ix
= 7; ix
>= 0; ix
--)
9347 mask
= ((bits
>> ix
) & 1) ? 0xff : 0;
9349 value
= (value
<< 8) | mask
;
9351 hival
= (hival
<< 8) | mask
;
9357 /* Byte replication. */
9358 value
= (unsigned long) bits
;
9364 /* Floating point encoding. */
9367 value
= (unsigned long) (bits
& 0x7f) << 19;
9368 value
|= (unsigned long) (bits
& 0x80) << 24;
9369 tmp
= bits
& 0x40 ? 0x3c : 0x40;
9370 value
|= (unsigned long) tmp
<< 24;
9376 func (stream
, "<illegal constant %.8x:%x:%x>",
9384 func (stream
, "#%ld\t; 0x%.2lx", value
, value
);
9388 func (stream
, "#%ld\t; 0x%.4lx", value
, value
);
9394 unsigned char valbytes
[4];
9397 /* Do this a byte at a time so we don't have to
9398 worry about the host's endianness. */
9399 valbytes
[0] = value
& 0xff;
9400 valbytes
[1] = (value
>> 8) & 0xff;
9401 valbytes
[2] = (value
>> 16) & 0xff;
9402 valbytes
[3] = (value
>> 24) & 0xff;
9404 floatformat_to_double
9405 (& floatformat_ieee_single_little
, valbytes
,
9408 func (stream
, "#%.7g\t; 0x%.8lx", fvalue
,
9412 func (stream
, "#%ld\t; 0x%.8lx",
9413 (long) (((value
& 0x80000000L
) != 0)
9414 ? value
| ~0xffffffffL
: value
),
9419 func (stream
, "#0x%.8lx%.8lx", hival
, value
);
9430 int regno
= ((given
>> 16) & 0xf) | ((given
>> (7 - 4)) & 0x10);
9431 int num
= (given
>> 8) & 0x3;
9434 func (stream
, "{d%d}", regno
);
9435 else if (num
+ regno
>= 32)
9436 func (stream
, "{d%d-<overflow reg d%d}", regno
, regno
+ num
);
9438 func (stream
, "{d%d-d%d}", regno
, regno
+ num
);
9443 case '0': case '1': case '2': case '3': case '4':
9444 case '5': case '6': case '7': case '8': case '9':
9447 unsigned long value
;
9449 c
= arm_decode_bitfield (c
, given
, &value
, &width
);
9454 func (stream
, "%s", arm_regnames
[value
]);
9457 func (stream
, "%ld", value
);
9458 value_in_comment
= value
;
9461 func (stream
, "%ld", (1ul << width
) - value
);
9467 /* Various width encodings. */
9469 int base
= 8 << (*c
- 'S'); /* 8,16 or 32 */
9474 if (*c
>= '0' && *c
<= '9')
9476 else if (*c
>= 'a' && *c
<= 'f')
9477 limit
= *c
- 'a' + 10;
9483 if (value
< low
|| value
> high
)
9484 func (stream
, "<illegal width %d>", base
<< value
);
9486 func (stream
, "%d", base
<< value
);
9490 if (given
& (1 << 6))
9494 func (stream
, "d%ld", value
);
9499 func (stream
, "<illegal reg q%ld.5>", value
>> 1);
9501 func (stream
, "q%ld", value
>> 1);
9507 func (stream
, "%c", *c
);
9511 if (value
== ((1ul << width
) - 1))
9512 func (stream
, "%c", *c
);
9515 func (stream
, "%c", c
[(1 << width
) - (int) value
]);
9529 func (stream
, "%c", *c
);
9532 if (value_in_comment
> 32 || value_in_comment
< -16)
9533 func (stream
, "\t; 0x%lx", value_in_comment
);
9535 if (is_unpredictable
)
9536 func (stream
, UNPREDICTABLE_INSTRUCTION
);
9544 /* Print one mve instruction on INFO->STREAM.
9545 Return TRUE if the instuction matched, FALSE if this is not a
9546 recognised mve instruction. */
9549 print_insn_mve (struct disassemble_info
*info
, long given
)
9551 const struct mopcode32
*insn
;
9552 void *stream
= info
->stream
;
9553 fprintf_ftype func
= info
->fprintf_func
;
9555 for (insn
= mve_opcodes
; insn
->assembler
; insn
++)
9557 if (((given
& insn
->mask
) == insn
->value
)
9558 && !is_mve_encoding_conflict (given
, insn
->mve_op
))
9560 signed long value_in_comment
= 0;
9561 bool is_unpredictable
= false;
9562 bool is_undefined
= false;
9564 enum mve_unpredictable unpredictable_cond
= UNPRED_NONE
;
9565 enum mve_undefined undefined_cond
= UNDEF_NONE
;
9567 /* Most vector mve instruction are illegal in a it block.
9568 There are a few exceptions; check for them. */
9569 if (ifthen_state
&& !is_mve_okay_in_it (insn
->mve_op
))
9571 is_unpredictable
= true;
9572 unpredictable_cond
= UNPRED_IT_BLOCK
;
9574 else if (is_mve_unpredictable (given
, insn
->mve_op
,
9575 &unpredictable_cond
))
9576 is_unpredictable
= true;
9578 if (is_mve_undefined (given
, insn
->mve_op
, &undefined_cond
))
9579 is_undefined
= true;
9581 /* In "VORR Qd, Qm, Qn", if Qm==Qn, VORR is nothing but VMOV,
9582 i.e "VMOV Qd, Qm". */
9583 if ((insn
->mve_op
== MVE_VORR_REG
)
9584 && (arm_decode_field (given
, 1, 3)
9585 == arm_decode_field (given
, 17, 19)))
9588 for (c
= insn
->assembler
; *c
; c
++)
9595 func (stream
, "%%");
9599 /* Don't print anything for '+' as it is implied. */
9600 if (arm_decode_field (given
, 23, 23) == 0)
9606 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
9610 print_mve_vld_str_addr (info
, given
, insn
->mve_op
);
9615 long mve_mask
= mve_extract_pred_mask (given
);
9616 func (stream
, "%s", mve_predicatenames
[mve_mask
]);
9622 unsigned int imm5
= 0;
9623 imm5
|= arm_decode_field (given
, 6, 7);
9624 imm5
|= (arm_decode_field (given
, 12, 14) << 2);
9625 func (stream
, "#%u", (imm5
== 0) ? 32 : imm5
);
9630 func (stream
, "#%u",
9631 (arm_decode_field (given
, 7, 7) == 0) ? 64 : 48);
9635 print_vec_condition (info
, given
, insn
->mve_op
);
9639 if (arm_decode_field (given
, 0, 0) == 1)
9642 = arm_decode_field (given
, 4, 4)
9643 | (arm_decode_field (given
, 6, 6) << 1);
9645 func (stream
, ", uxtw #%lu", size
);
9650 print_mve_rounding_mode (info
, given
, insn
->mve_op
);
9654 print_mve_vcvt_size (info
, given
, insn
->mve_op
);
9659 unsigned long op1
= arm_decode_field (given
, 21, 22);
9661 if ((insn
->mve_op
== MVE_VMOV_VEC_LANE_TO_GP
))
9663 /* Check for signed. */
9664 if (arm_decode_field (given
, 23, 23) == 0)
9666 /* We don't print 's' for S32. */
9667 if ((arm_decode_field (given
, 5, 6) == 0)
9668 && ((op1
== 0) || (op1
== 1)))
9678 if (arm_decode_field (given
, 28, 28) == 0)
9687 print_instruction_predicate (info
);
9691 if (arm_decode_field (given
, 21, 21) == 1)
9696 print_mve_register_blocks (info
, given
, insn
->mve_op
);
9700 /* SIMD encoded constant for mov, mvn, vorr, vbic. */
9702 print_simd_imm8 (info
, given
, 28, insn
);
9706 print_mve_vmov_index (info
, given
);
9710 if (arm_decode_field (given
, 12, 12) == 0)
9717 if (arm_decode_field (given
, 12, 12) == 1)
9721 case '0': case '1': case '2': case '3': case '4':
9722 case '5': case '6': case '7': case '8': case '9':
9725 unsigned long value
;
9727 c
= arm_decode_bitfield (c
, given
, &value
, &width
);
9733 is_unpredictable
= true;
9734 else if (value
== 15)
9735 func (stream
, "zr");
9737 func (stream
, "%s", arm_regnames
[value
]);
9741 func (stream
, "%s", arm_conditional
[value
]);
9746 func (stream
, "%s", arm_conditional
[value
]);
9750 if (value
== 13 || value
== 15)
9751 is_unpredictable
= true;
9753 func (stream
, "%s", arm_regnames
[value
]);
9757 print_mve_size (info
,
9771 unsigned int odd_reg
= (value
<< 1) | 1;
9772 func (stream
, "%s", arm_regnames
[odd_reg
]);
9778 = arm_decode_field (given
, 0, 6);
9779 unsigned long mod_imm
= imm
;
9781 switch (insn
->mve_op
)
9783 case MVE_VLDRW_GATHER_T5
:
9784 case MVE_VSTRW_SCATTER_T5
:
9785 mod_imm
= mod_imm
<< 2;
9787 case MVE_VSTRD_SCATTER_T6
:
9788 case MVE_VLDRD_GATHER_T6
:
9789 mod_imm
= mod_imm
<< 3;
9796 func (stream
, "%lu", mod_imm
);
9800 func (stream
, "%lu", 64 - value
);
9804 unsigned int even_reg
= value
<< 1;
9805 func (stream
, "%s", arm_regnames
[even_reg
]);
9828 print_mve_rotate (info
, value
, width
);
9831 func (stream
, "%s", arm_regnames
[value
]);
9834 if (insn
->mve_op
== MVE_VQSHL_T2
9835 || insn
->mve_op
== MVE_VQSHLU_T3
9836 || insn
->mve_op
== MVE_VRSHR
9837 || insn
->mve_op
== MVE_VRSHRN
9838 || insn
->mve_op
== MVE_VSHL_T1
9839 || insn
->mve_op
== MVE_VSHLL_T1
9840 || insn
->mve_op
== MVE_VSHR
9841 || insn
->mve_op
== MVE_VSHRN
9842 || insn
->mve_op
== MVE_VSLI
9843 || insn
->mve_op
== MVE_VSRI
)
9844 print_mve_shift_n (info
, given
, insn
->mve_op
);
9845 else if (insn
->mve_op
== MVE_VSHLL_T2
)
9853 func (stream
, "16");
9856 print_mve_undefined (info
, UNDEF_SIZE_0
);
9865 if (insn
->mve_op
== MVE_VSHLC
&& value
== 0)
9867 func (stream
, "%ld", value
);
9868 value_in_comment
= value
;
9872 func (stream
, "s%ld", value
);
9876 func (stream
, "<illegal reg q%ld.5>", value
);
9878 func (stream
, "q%ld", value
);
9881 func (stream
, "0x%08lx", value
);
9893 func (stream
, "%c", *c
);
9896 if (value_in_comment
> 32 || value_in_comment
< -16)
9897 func (stream
, "\t; 0x%lx", value_in_comment
);
9899 if (is_unpredictable
)
9900 print_mve_unpredictable (info
, unpredictable_cond
);
9903 print_mve_undefined (info
, undefined_cond
);
9905 if (!vpt_block_state
.in_vpt_block
9907 && is_vpt_instruction (given
))
9908 mark_inside_vpt_block (given
);
9909 else if (vpt_block_state
.in_vpt_block
)
9910 update_vpt_block_state ();
9919 /* Return the name of a v7A special register. */
9922 banked_regname (unsigned reg
)
9926 case 15: return "CPSR";
9927 case 32: return "R8_usr";
9928 case 33: return "R9_usr";
9929 case 34: return "R10_usr";
9930 case 35: return "R11_usr";
9931 case 36: return "R12_usr";
9932 case 37: return "SP_usr";
9933 case 38: return "LR_usr";
9934 case 40: return "R8_fiq";
9935 case 41: return "R9_fiq";
9936 case 42: return "R10_fiq";
9937 case 43: return "R11_fiq";
9938 case 44: return "R12_fiq";
9939 case 45: return "SP_fiq";
9940 case 46: return "LR_fiq";
9941 case 48: return "LR_irq";
9942 case 49: return "SP_irq";
9943 case 50: return "LR_svc";
9944 case 51: return "SP_svc";
9945 case 52: return "LR_abt";
9946 case 53: return "SP_abt";
9947 case 54: return "LR_und";
9948 case 55: return "SP_und";
9949 case 60: return "LR_mon";
9950 case 61: return "SP_mon";
9951 case 62: return "ELR_hyp";
9952 case 63: return "SP_hyp";
9953 case 79: return "SPSR";
9954 case 110: return "SPSR_fiq";
9955 case 112: return "SPSR_irq";
9956 case 114: return "SPSR_svc";
9957 case 116: return "SPSR_abt";
9958 case 118: return "SPSR_und";
9959 case 124: return "SPSR_mon";
9960 case 126: return "SPSR_hyp";
9961 default: return NULL
;
9965 /* Return the name of the DMB/DSB option. */
9967 data_barrier_option (unsigned option
)
9969 switch (option
& 0xf)
9971 case 0xf: return "sy";
9972 case 0xe: return "st";
9973 case 0xd: return "ld";
9974 case 0xb: return "ish";
9975 case 0xa: return "ishst";
9976 case 0x9: return "ishld";
9977 case 0x7: return "un";
9978 case 0x6: return "unst";
9979 case 0x5: return "nshld";
9980 case 0x3: return "osh";
9981 case 0x2: return "oshst";
9982 case 0x1: return "oshld";
9983 default: return NULL
;
9987 /* Print one ARM instruction from PC on INFO->STREAM. */
9990 print_insn_arm (bfd_vma pc
, struct disassemble_info
*info
, long given
)
9992 const struct opcode32
*insn
;
9993 void *stream
= info
->stream
;
9994 fprintf_ftype func
= info
->fprintf_func
;
9995 struct arm_private_data
*private_data
= info
->private_data
;
9997 if (print_insn_coprocessor (pc
, info
, given
, false))
10000 if (print_insn_neon (info
, given
, false))
10003 if (print_insn_generic_coprocessor (pc
, info
, given
, false))
10006 for (insn
= arm_opcodes
; insn
->assembler
; insn
++)
10008 if ((given
& insn
->mask
) != insn
->value
)
10011 if (! ARM_CPU_HAS_FEATURE (insn
->arch
, private_data
->features
))
10014 /* Special case: an instruction with all bits set in the condition field
10015 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
10016 or by the catchall at the end of the table. */
10017 if ((given
& 0xF0000000) != 0xF0000000
10018 || (insn
->mask
& 0xF0000000) == 0xF0000000
10019 || (insn
->mask
== 0 && insn
->value
== 0))
10021 unsigned long u_reg
= 16;
10022 unsigned long U_reg
= 16;
10023 bool is_unpredictable
= false;
10024 signed long value_in_comment
= 0;
10027 for (c
= insn
->assembler
; *c
; c
++)
10031 bool allow_unpredictable
= false;
10036 func (stream
, "%%");
10040 value_in_comment
= print_arm_address (pc
, info
, given
);
10044 /* Set P address bit and use normal address
10045 printing routine. */
10046 value_in_comment
= print_arm_address (pc
, info
, given
| (1 << P_BIT
));
10050 allow_unpredictable
= true;
10051 /* Fall through. */
10053 if ((given
& 0x004f0000) == 0x004f0000)
10055 /* PC relative with immediate offset. */
10056 bfd_vma offset
= ((given
& 0xf00) >> 4) | (given
& 0xf);
10060 /* Elide positive zero offset. */
10061 if (offset
|| NEGATIVE_BIT_SET
)
10062 func (stream
, "[pc, #%s%d]\t; ",
10063 NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
10065 func (stream
, "[pc]\t; ");
10066 if (NEGATIVE_BIT_SET
)
10068 info
->print_address_func (offset
+ pc
+ 8, info
);
10072 /* Always show the offset. */
10073 func (stream
, "[pc], #%s%d",
10074 NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
10075 if (! allow_unpredictable
)
10076 is_unpredictable
= true;
10081 int offset
= ((given
& 0xf00) >> 4) | (given
& 0xf);
10083 func (stream
, "[%s",
10084 arm_regnames
[(given
>> 16) & 0xf]);
10088 if (IMMEDIATE_BIT_SET
)
10090 /* Elide offset for non-writeback
10092 if (WRITEBACK_BIT_SET
|| NEGATIVE_BIT_SET
10094 func (stream
, ", #%s%d",
10095 NEGATIVE_BIT_SET
? "-" : "", offset
);
10097 if (NEGATIVE_BIT_SET
)
10100 value_in_comment
= offset
;
10104 /* Register Offset or Register Pre-Indexed. */
10105 func (stream
, ", %s%s",
10106 NEGATIVE_BIT_SET
? "-" : "",
10107 arm_regnames
[given
& 0xf]);
10109 /* Writing back to the register that is the source/
10110 destination of the load/store is unpredictable. */
10111 if (! allow_unpredictable
10112 && WRITEBACK_BIT_SET
10113 && ((given
& 0xf) == ((given
>> 12) & 0xf)))
10114 is_unpredictable
= true;
10117 func (stream
, "]%s",
10118 WRITEBACK_BIT_SET
? "!" : "");
10122 if (IMMEDIATE_BIT_SET
)
10124 /* Immediate Post-indexed. */
10125 /* PR 10924: Offset must be printed, even if it is zero. */
10126 func (stream
, "], #%s%d",
10127 NEGATIVE_BIT_SET
? "-" : "", offset
);
10128 if (NEGATIVE_BIT_SET
)
10130 value_in_comment
= offset
;
10134 /* Register Post-indexed. */
10135 func (stream
, "], %s%s",
10136 NEGATIVE_BIT_SET
? "-" : "",
10137 arm_regnames
[given
& 0xf]);
10139 /* Writing back to the register that is the source/
10140 destination of the load/store is unpredictable. */
10141 if (! allow_unpredictable
10142 && (given
& 0xf) == ((given
>> 12) & 0xf))
10143 is_unpredictable
= true;
10146 if (! allow_unpredictable
)
10148 /* Writeback is automatically implied by post- addressing.
10149 Setting the W bit is unnecessary and ARM specify it as
10150 being unpredictable. */
10151 if (WRITEBACK_BIT_SET
10152 /* Specifying the PC register as the post-indexed
10153 registers is also unpredictable. */
10154 || (! IMMEDIATE_BIT_SET
&& ((given
& 0xf) == 0xf)))
10155 is_unpredictable
= true;
10163 bfd_vma disp
= (((given
& 0xffffff) ^ 0x800000) - 0x800000);
10164 bfd_vma target
= disp
* 4 + pc
+ 8;
10165 info
->print_address_func (target
, info
);
10167 /* Fill in instruction information. */
10168 info
->insn_info_valid
= 1;
10169 info
->insn_type
= dis_branch
;
10170 info
->target
= target
;
10175 if (((given
>> 28) & 0xf) != 0xe)
10176 func (stream
, "%s",
10177 arm_conditional
[(given
>> 28) & 0xf]);
10185 func (stream
, "{");
10186 for (reg
= 0; reg
< 16; reg
++)
10187 if ((given
& (1 << reg
)) != 0)
10190 func (stream
, ", ");
10192 func (stream
, "%s", arm_regnames
[reg
]);
10194 func (stream
, "}");
10196 is_unpredictable
= true;
10201 arm_decode_shift (given
, func
, stream
, false);
10205 if ((given
& 0x02000000) != 0)
10207 unsigned int rotate
= (given
& 0xf00) >> 7;
10208 unsigned int immed
= (given
& 0xff);
10211 a
= (immed
<< ((32 - rotate
) & 31)
10212 | immed
>> rotate
) & 0xffffffff;
10213 /* If there is another encoding with smaller rotate,
10214 the rotate should be specified directly. */
10215 for (i
= 0; i
< 32; i
+= 2)
10216 if ((a
<< i
| a
>> ((32 - i
) & 31)) <= 0xff)
10220 func (stream
, "#%d, %d", immed
, rotate
);
10222 func (stream
, "#%d", a
);
10223 value_in_comment
= a
;
10226 arm_decode_shift (given
, func
, stream
, true);
10230 if ((given
& 0x0000f000) == 0x0000f000)
10232 arm_feature_set arm_ext_v6
=
10233 ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
10235 /* The p-variants of tst/cmp/cmn/teq are the pre-V6
10236 mechanism for setting PSR flag bits. They are
10237 obsolete in V6 onwards. */
10238 if (! ARM_CPU_HAS_FEATURE (private_data
->features
, \
10240 func (stream
, "p");
10242 is_unpredictable
= true;
10247 if ((given
& 0x01200000) == 0x00200000)
10248 func (stream
, "t");
10253 int offset
= given
& 0xff;
10255 value_in_comment
= offset
* 4;
10256 if (NEGATIVE_BIT_SET
)
10257 value_in_comment
= - value_in_comment
;
10259 func (stream
, "[%s", arm_regnames
[(given
>> 16) & 0xf]);
10264 func (stream
, ", #%d]%s",
10265 (int) value_in_comment
,
10266 WRITEBACK_BIT_SET
? "!" : "");
10268 func (stream
, "]");
10272 func (stream
, "]");
10274 if (WRITEBACK_BIT_SET
)
10277 func (stream
, ", #%d", (int) value_in_comment
);
10281 func (stream
, ", {%d}", (int) offset
);
10282 value_in_comment
= offset
;
10289 /* Print ARM V5 BLX(1) address: pc+25 bits. */
10292 bfd_vma offset
= 0;
10294 if (! NEGATIVE_BIT_SET
)
10295 /* Is signed, hi bits should be ones. */
10296 offset
= (-1) ^ 0x00ffffff;
10298 /* Offset is (SignExtend(offset field)<<2). */
10299 offset
+= given
& 0x00ffffff;
10301 address
= offset
+ pc
+ 8;
10303 if (given
& 0x01000000)
10304 /* H bit allows addressing to 2-byte boundaries. */
10307 info
->print_address_func (address
, info
);
10309 /* Fill in instruction information. */
10310 info
->insn_info_valid
= 1;
10311 info
->insn_type
= dis_branch
;
10312 info
->target
= address
;
10317 if ((given
& 0x02000200) == 0x200)
10320 unsigned sysm
= (given
& 0x004f0000) >> 16;
10322 sysm
|= (given
& 0x300) >> 4;
10323 name
= banked_regname (sysm
);
10326 func (stream
, "%s", name
);
10328 func (stream
, "(UNDEF: %lu)", (unsigned long) sysm
);
10332 func (stream
, "%cPSR_",
10333 (given
& 0x00400000) ? 'S' : 'C');
10334 if (given
& 0x80000)
10335 func (stream
, "f");
10336 if (given
& 0x40000)
10337 func (stream
, "s");
10338 if (given
& 0x20000)
10339 func (stream
, "x");
10340 if (given
& 0x10000)
10341 func (stream
, "c");
10346 if ((given
& 0xf0) == 0x60)
10348 switch (given
& 0xf)
10350 case 0xf: func (stream
, "sy"); break;
10352 func (stream
, "#%d", (int) given
& 0xf);
10358 const char * opt
= data_barrier_option (given
& 0xf);
10360 func (stream
, "%s", opt
);
10362 func (stream
, "#%d", (int) given
& 0xf);
10366 case '0': case '1': case '2': case '3': case '4':
10367 case '5': case '6': case '7': case '8': case '9':
10370 unsigned long value
;
10372 c
= arm_decode_bitfield (c
, given
, &value
, &width
);
10378 is_unpredictable
= true;
10379 /* Fall through. */
10382 /* We want register + 1 when decoding T. */
10384 value
= (value
+ 1) & 0xf;
10388 /* Eat the 'u' character. */
10391 if (u_reg
== value
)
10392 is_unpredictable
= true;
10397 /* Eat the 'U' character. */
10400 if (U_reg
== value
)
10401 is_unpredictable
= true;
10404 func (stream
, "%s", arm_regnames
[value
]);
10407 func (stream
, "%ld", value
);
10408 value_in_comment
= value
;
10411 func (stream
, "%ld", value
* 8);
10412 value_in_comment
= value
* 8;
10415 func (stream
, "%ld", value
+ 1);
10416 value_in_comment
= value
+ 1;
10419 func (stream
, "0x%08lx", value
);
10421 /* Some SWI instructions have special
10423 if ((given
& 0x0fffffff) == 0x0FF00000)
10424 func (stream
, "\t; IMB");
10425 else if ((given
& 0x0fffffff) == 0x0FF00001)
10426 func (stream
, "\t; IMBRange");
10429 func (stream
, "%01lx", value
& 0xf);
10430 value_in_comment
= value
;
10435 func (stream
, "%c", *c
);
10439 if (value
== ((1ul << width
) - 1))
10440 func (stream
, "%c", *c
);
10443 func (stream
, "%c", c
[(1 << width
) - (int) value
]);
10456 imm
= (given
& 0xf) | ((given
& 0xfff00) >> 4);
10457 func (stream
, "%d", imm
);
10458 value_in_comment
= imm
;
10463 /* LSB and WIDTH fields of BFI or BFC. The machine-
10464 language instruction encodes LSB and MSB. */
10466 long msb
= (given
& 0x001f0000) >> 16;
10467 long lsb
= (given
& 0x00000f80) >> 7;
10468 long w
= msb
- lsb
+ 1;
10471 func (stream
, "#%lu, #%lu", lsb
, w
);
10473 func (stream
, "(invalid: %lu:%lu)", lsb
, msb
);
10478 /* Get the PSR/banked register name. */
10481 unsigned sysm
= (given
& 0x004f0000) >> 16;
10483 sysm
|= (given
& 0x300) >> 4;
10484 name
= banked_regname (sysm
);
10487 func (stream
, "%s", name
);
10489 func (stream
, "(UNDEF: %lu)", (unsigned long) sysm
);
10494 /* 16-bit unsigned immediate from a MOVT or MOVW
10495 instruction, encoded in bits 0:11 and 15:19. */
10497 long hi
= (given
& 0x000f0000) >> 4;
10498 long lo
= (given
& 0x00000fff);
10499 long imm16
= hi
| lo
;
10501 func (stream
, "#%lu", imm16
);
10502 value_in_comment
= imm16
;
10511 func (stream
, "%c", *c
);
10514 if (value_in_comment
> 32 || value_in_comment
< -16)
10515 func (stream
, "\t; 0x%lx", (value_in_comment
& 0xffffffffUL
));
10517 if (is_unpredictable
)
10518 func (stream
, UNPREDICTABLE_INSTRUCTION
);
10523 func (stream
, UNKNOWN_INSTRUCTION_32BIT
, (unsigned)given
);
10527 /* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
10530 print_insn_thumb16 (bfd_vma pc
, struct disassemble_info
*info
, long given
)
10532 const struct opcode16
*insn
;
10533 void *stream
= info
->stream
;
10534 fprintf_ftype func
= info
->fprintf_func
;
10536 for (insn
= thumb_opcodes
; insn
->assembler
; insn
++)
10537 if ((given
& insn
->mask
) == insn
->value
)
10539 signed long value_in_comment
= 0;
10540 const char *c
= insn
->assembler
;
10549 func (stream
, "%c", *c
);
10556 func (stream
, "%%");
10561 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
10566 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
10568 func (stream
, "s");
10575 ifthen_next_state
= given
& 0xff;
10576 for (tmp
= given
<< 1; tmp
& 0xf; tmp
<<= 1)
10577 func (stream
, ((given
^ tmp
) & 0x10) ? "e" : "t");
10578 func (stream
, "\t%s", arm_conditional
[(given
>> 4) & 0xf]);
10583 if (ifthen_next_state
)
10584 func (stream
, "\t; unpredictable branch in IT block\n");
10589 func (stream
, "\t; unpredictable <IT:%s>",
10590 arm_conditional
[IFTHEN_COND
]);
10597 reg
= (given
>> 3) & 0x7;
10598 if (given
& (1 << 6))
10601 func (stream
, "%s", arm_regnames
[reg
]);
10610 if (given
& (1 << 7))
10613 func (stream
, "%s", arm_regnames
[reg
]);
10618 if (given
& (1 << 8))
10620 /* Fall through. */
10622 if (*c
== 'O' && (given
& (1 << 8)))
10624 /* Fall through. */
10630 func (stream
, "{");
10632 /* It would be nice if we could spot
10633 ranges, and generate the rS-rE format: */
10634 for (reg
= 0; (reg
< 8); reg
++)
10635 if ((given
& (1 << reg
)) != 0)
10638 func (stream
, ", ");
10640 func (stream
, "%s", arm_regnames
[reg
]);
10646 func (stream
, ", ");
10648 func (stream
, "%s", arm_regnames
[14] /* "lr" */);
10654 func (stream
, ", ");
10655 func (stream
, "%s", arm_regnames
[15] /* "pc" */);
10658 func (stream
, "}");
10663 /* Print writeback indicator for a LDMIA. We are doing a
10664 writeback if the base register is not in the register
10666 if ((given
& (1 << ((given
& 0x0700) >> 8))) == 0)
10667 func (stream
, "!");
10671 /* Print ARM V6T2 CZB address: pc+4+6 bits. */
10673 bfd_vma address
= (pc
+ 4
10674 + ((given
& 0x00f8) >> 2)
10675 + ((given
& 0x0200) >> 3));
10676 info
->print_address_func (address
, info
);
10678 /* Fill in instruction information. */
10679 info
->insn_info_valid
= 1;
10680 info
->insn_type
= dis_branch
;
10681 info
->target
= address
;
10686 /* Right shift immediate -- bits 6..10; 1-31 print
10687 as themselves, 0 prints as 32. */
10689 long imm
= (given
& 0x07c0) >> 6;
10692 func (stream
, "#%ld", imm
);
10696 case '0': case '1': case '2': case '3': case '4':
10697 case '5': case '6': case '7': case '8': case '9':
10699 int bitstart
= *c
++ - '0';
10702 while (*c
>= '0' && *c
<= '9')
10703 bitstart
= (bitstart
* 10) + *c
++ - '0';
10712 while (*c
>= '0' && *c
<= '9')
10713 bitend
= (bitend
* 10) + *c
++ - '0';
10716 reg
= given
>> bitstart
;
10717 reg
&= ((bfd_vma
) 2 << (bitend
- bitstart
)) - 1;
10722 func (stream
, "%s", arm_regnames
[reg
]);
10726 func (stream
, "%ld", (long) reg
);
10727 value_in_comment
= reg
;
10731 func (stream
, "%ld", (long) (reg
<< 1));
10732 value_in_comment
= reg
<< 1;
10736 func (stream
, "%ld", (long) (reg
<< 2));
10737 value_in_comment
= reg
<< 2;
10741 /* PC-relative address -- the bottom two
10742 bits of the address are dropped
10743 before the calculation. */
10744 info
->print_address_func
10745 (((pc
+ 4) & ~3) + (reg
<< 2), info
);
10746 value_in_comment
= 0;
10750 func (stream
, "0x%04lx", (long) reg
);
10754 reg
= ((reg
^ (1 << bitend
)) - (1 << bitend
));
10755 bfd_vma target
= reg
* 2 + pc
+ 4;
10756 info
->print_address_func (target
, info
);
10757 value_in_comment
= 0;
10759 /* Fill in instruction information. */
10760 info
->insn_info_valid
= 1;
10761 info
->insn_type
= dis_branch
;
10762 info
->target
= target
;
10766 func (stream
, "%s", arm_conditional
[reg
]);
10777 if ((given
& (1 << bitstart
)) != 0)
10778 func (stream
, "%c", *c
);
10783 if ((given
& (1 << bitstart
)) != 0)
10784 func (stream
, "%c", *c
++);
10786 func (stream
, "%c", *++c
);
10800 if (value_in_comment
> 32 || value_in_comment
< -16)
10801 func (stream
, "\t; 0x%lx", value_in_comment
);
10806 func (stream
, UNKNOWN_INSTRUCTION_16BIT
, (unsigned)given
);
10810 /* Return the name of an V7M special register. */
10812 static const char *
10813 psr_name (int regno
)
10817 case 0x0: return "APSR";
10818 case 0x1: return "IAPSR";
10819 case 0x2: return "EAPSR";
10820 case 0x3: return "PSR";
10821 case 0x5: return "IPSR";
10822 case 0x6: return "EPSR";
10823 case 0x7: return "IEPSR";
10824 case 0x8: return "MSP";
10825 case 0x9: return "PSP";
10826 case 0xa: return "MSPLIM";
10827 case 0xb: return "PSPLIM";
10828 case 0x10: return "PRIMASK";
10829 case 0x11: return "BASEPRI";
10830 case 0x12: return "BASEPRI_MAX";
10831 case 0x13: return "FAULTMASK";
10832 case 0x14: return "CONTROL";
10833 case 0x88: return "MSP_NS";
10834 case 0x89: return "PSP_NS";
10835 case 0x8a: return "MSPLIM_NS";
10836 case 0x8b: return "PSPLIM_NS";
10837 case 0x90: return "PRIMASK_NS";
10838 case 0x91: return "BASEPRI_NS";
10839 case 0x93: return "FAULTMASK_NS";
10840 case 0x94: return "CONTROL_NS";
10841 case 0x98: return "SP_NS";
10842 default: return "<unknown>";
10846 /* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
10849 print_insn_thumb32 (bfd_vma pc
, struct disassemble_info
*info
, long given
)
10851 const struct opcode32
*insn
;
10852 void *stream
= info
->stream
;
10853 fprintf_ftype func
= info
->fprintf_func
;
10854 bool is_mve
= is_mve_architecture (info
);
10856 if (print_insn_coprocessor (pc
, info
, given
, true))
10859 if (!is_mve
&& print_insn_neon (info
, given
, true))
10862 if (is_mve
&& print_insn_mve (info
, given
))
10865 if (print_insn_cde (info
, given
, true))
10868 if (print_insn_generic_coprocessor (pc
, info
, given
, true))
10871 for (insn
= thumb32_opcodes
; insn
->assembler
; insn
++)
10872 if ((given
& insn
->mask
) == insn
->value
)
10874 bool is_clrm
= false;
10875 bool is_unpredictable
= false;
10876 signed long value_in_comment
= 0;
10877 const char *c
= insn
->assembler
;
10883 func (stream
, "%c", *c
);
10890 func (stream
, "%%");
10895 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
10899 if (ifthen_next_state
)
10900 func (stream
, "\t; unpredictable branch in IT block\n");
10905 func (stream
, "\t; unpredictable <IT:%s>",
10906 arm_conditional
[IFTHEN_COND
]);
10911 unsigned int imm12
= 0;
10913 imm12
|= (given
& 0x000000ffu
);
10914 imm12
|= (given
& 0x00007000u
) >> 4;
10915 imm12
|= (given
& 0x04000000u
) >> 15;
10916 func (stream
, "#%u", imm12
);
10917 value_in_comment
= imm12
;
10923 unsigned int bits
= 0, imm
, imm8
, mod
;
10925 bits
|= (given
& 0x000000ffu
);
10926 bits
|= (given
& 0x00007000u
) >> 4;
10927 bits
|= (given
& 0x04000000u
) >> 15;
10928 imm8
= (bits
& 0x0ff);
10929 mod
= (bits
& 0xf00) >> 8;
10932 case 0: imm
= imm8
; break;
10933 case 1: imm
= ((imm8
<< 16) | imm8
); break;
10934 case 2: imm
= ((imm8
<< 24) | (imm8
<< 8)); break;
10935 case 3: imm
= ((imm8
<< 24) | (imm8
<< 16) | (imm8
<< 8) | imm8
); break;
10937 mod
= (bits
& 0xf80) >> 7;
10938 imm8
= (bits
& 0x07f) | 0x80;
10939 imm
= (((imm8
<< (32 - mod
)) | (imm8
>> mod
)) & 0xffffffff);
10941 func (stream
, "#%u", imm
);
10942 value_in_comment
= imm
;
10948 unsigned int imm
= 0;
10950 imm
|= (given
& 0x000000ffu
);
10951 imm
|= (given
& 0x00007000u
) >> 4;
10952 imm
|= (given
& 0x04000000u
) >> 15;
10953 imm
|= (given
& 0x000f0000u
) >> 4;
10954 func (stream
, "#%u", imm
);
10955 value_in_comment
= imm
;
10961 unsigned int imm
= 0;
10963 imm
|= (given
& 0x000f0000u
) >> 16;
10964 imm
|= (given
& 0x00000ff0u
) >> 0;
10965 imm
|= (given
& 0x0000000fu
) << 12;
10966 func (stream
, "#%u", imm
);
10967 value_in_comment
= imm
;
10973 unsigned int imm
= 0;
10975 imm
|= (given
& 0x000f0000u
) >> 4;
10976 imm
|= (given
& 0x00000fffu
) >> 0;
10977 func (stream
, "#%u", imm
);
10978 value_in_comment
= imm
;
10984 unsigned int imm
= 0;
10986 imm
|= (given
& 0x00000fffu
);
10987 imm
|= (given
& 0x000f0000u
) >> 4;
10988 func (stream
, "#%u", imm
);
10989 value_in_comment
= imm
;
10995 unsigned int reg
= (given
& 0x0000000fu
);
10996 unsigned int stp
= (given
& 0x00000030u
) >> 4;
10997 unsigned int imm
= 0;
10998 imm
|= (given
& 0x000000c0u
) >> 6;
10999 imm
|= (given
& 0x00007000u
) >> 10;
11001 func (stream
, "%s", arm_regnames
[reg
]);
11006 func (stream
, ", lsl #%u", imm
);
11012 func (stream
, ", lsr #%u", imm
);
11018 func (stream
, ", asr #%u", imm
);
11023 func (stream
, ", rrx");
11025 func (stream
, ", ror #%u", imm
);
11032 unsigned int Rn
= (given
& 0x000f0000) >> 16;
11033 unsigned int U
= ! NEGATIVE_BIT_SET
;
11034 unsigned int op
= (given
& 0x00000f00) >> 8;
11035 unsigned int i12
= (given
& 0x00000fff);
11036 unsigned int i8
= (given
& 0x000000ff);
11037 bool writeback
= false, postind
= false;
11038 bfd_vma offset
= 0;
11040 func (stream
, "[%s", arm_regnames
[Rn
]);
11041 if (U
) /* 12-bit positive immediate offset. */
11045 value_in_comment
= offset
;
11047 else if (Rn
== 15) /* 12-bit negative immediate offset. */
11048 offset
= - (int) i12
;
11049 else if (op
== 0x0) /* Shifted register offset. */
11051 unsigned int Rm
= (i8
& 0x0f);
11052 unsigned int sh
= (i8
& 0x30) >> 4;
11054 func (stream
, ", %s", arm_regnames
[Rm
]);
11056 func (stream
, ", lsl #%u", sh
);
11057 func (stream
, "]");
11062 case 0xE: /* 8-bit positive immediate offset. */
11066 case 0xC: /* 8-bit negative immediate offset. */
11070 case 0xF: /* 8-bit + preindex with wb. */
11075 case 0xD: /* 8-bit - preindex with wb. */
11080 case 0xB: /* 8-bit + postindex. */
11085 case 0x9: /* 8-bit - postindex. */
11091 func (stream
, ", <undefined>]");
11096 func (stream
, "], #%d", (int) offset
);
11100 func (stream
, ", #%d", (int) offset
);
11101 func (stream
, writeback
? "]!" : "]");
11106 func (stream
, "\t; ");
11107 info
->print_address_func (((pc
+ 4) & ~3) + offset
, info
);
11115 unsigned int U
= ! NEGATIVE_BIT_SET
;
11116 unsigned int W
= WRITEBACK_BIT_SET
;
11117 unsigned int Rn
= (given
& 0x000f0000) >> 16;
11118 unsigned int off
= (given
& 0x000000ff);
11120 func (stream
, "[%s", arm_regnames
[Rn
]);
11126 func (stream
, ", #%c%u", U
? '+' : '-', off
* 4);
11127 value_in_comment
= off
* 4 * (U
? 1 : -1);
11129 func (stream
, "]");
11131 func (stream
, "!");
11135 func (stream
, "], ");
11138 func (stream
, "#%c%u", U
? '+' : '-', off
* 4);
11139 value_in_comment
= off
* 4 * (U
? 1 : -1);
11143 func (stream
, "{%u}", off
);
11144 value_in_comment
= off
;
11152 unsigned int Sbit
= (given
& 0x01000000) >> 24;
11153 unsigned int type
= (given
& 0x00600000) >> 21;
11157 case 0: func (stream
, Sbit
? "sb" : "b"); break;
11158 case 1: func (stream
, Sbit
? "sh" : "h"); break;
11161 func (stream
, "??");
11164 func (stream
, "??");
11172 /* Fall through. */
11178 func (stream
, "{");
11179 for (reg
= 0; reg
< 16; reg
++)
11180 if ((given
& (1 << reg
)) != 0)
11183 func (stream
, ", ");
11185 if (is_clrm
&& reg
== 13)
11186 func (stream
, "(invalid: %s)", arm_regnames
[reg
]);
11187 else if (is_clrm
&& reg
== 15)
11188 func (stream
, "%s", "APSR");
11190 func (stream
, "%s", arm_regnames
[reg
]);
11192 func (stream
, "}");
11198 unsigned int msb
= (given
& 0x0000001f);
11199 unsigned int lsb
= 0;
11201 lsb
|= (given
& 0x000000c0u
) >> 6;
11202 lsb
|= (given
& 0x00007000u
) >> 10;
11203 func (stream
, "#%u, #%u", lsb
, msb
- lsb
+ 1);
11209 unsigned int width
= (given
& 0x0000001f) + 1;
11210 unsigned int lsb
= 0;
11212 lsb
|= (given
& 0x000000c0u
) >> 6;
11213 lsb
|= (given
& 0x00007000u
) >> 10;
11214 func (stream
, "#%u, #%u", lsb
, width
);
11220 unsigned int boff
= (((given
& 0x07800000) >> 23) << 1);
11221 func (stream
, "%x", boff
);
11227 unsigned int immA
= (given
& 0x001f0000u
) >> 16;
11228 unsigned int immB
= (given
& 0x000007feu
) >> 1;
11229 unsigned int immC
= (given
& 0x00000800u
) >> 11;
11230 bfd_vma offset
= 0;
11232 offset
|= immA
<< 12;
11233 offset
|= immB
<< 2;
11234 offset
|= immC
<< 1;
11236 offset
= (offset
& 0x10000) ? offset
- (1 << 17) : offset
;
11238 info
->print_address_func (pc
+ 4 + offset
, info
);
11244 unsigned int immA
= (given
& 0x007f0000u
) >> 16;
11245 unsigned int immB
= (given
& 0x000007feu
) >> 1;
11246 unsigned int immC
= (given
& 0x00000800u
) >> 11;
11247 bfd_vma offset
= 0;
11249 offset
|= immA
<< 12;
11250 offset
|= immB
<< 2;
11251 offset
|= immC
<< 1;
11253 offset
= (offset
& 0x40000) ? offset
- (1 << 19) : offset
;
11255 info
->print_address_func (pc
+ 4 + offset
, info
);
11261 unsigned int immA
= (given
& 0x00010000u
) >> 16;
11262 unsigned int immB
= (given
& 0x000007feu
) >> 1;
11263 unsigned int immC
= (given
& 0x00000800u
) >> 11;
11264 bfd_vma offset
= 0;
11266 offset
|= immA
<< 12;
11267 offset
|= immB
<< 2;
11268 offset
|= immC
<< 1;
11270 offset
= (offset
& 0x1000) ? offset
- (1 << 13) : offset
;
11272 info
->print_address_func (pc
+ 4 + offset
, info
);
11274 unsigned int T
= (given
& 0x00020000u
) >> 17;
11275 unsigned int endoffset
= (((given
& 0x07800000) >> 23) << 1);
11276 unsigned int boffset
= (T
== 1) ? 4 : 2;
11277 func (stream
, ", ");
11278 func (stream
, "%x", endoffset
+ boffset
);
11284 unsigned int immh
= (given
& 0x000007feu
) >> 1;
11285 unsigned int imml
= (given
& 0x00000800u
) >> 11;
11288 imm32
|= immh
<< 2;
11289 imm32
|= imml
<< 1;
11291 info
->print_address_func (pc
+ 4 + imm32
, info
);
11297 unsigned int immh
= (given
& 0x000007feu
) >> 1;
11298 unsigned int imml
= (given
& 0x00000800u
) >> 11;
11301 imm32
|= immh
<< 2;
11302 imm32
|= imml
<< 1;
11304 info
->print_address_func (pc
+ 4 - imm32
, info
);
11310 unsigned int S
= (given
& 0x04000000u
) >> 26;
11311 unsigned int J1
= (given
& 0x00002000u
) >> 13;
11312 unsigned int J2
= (given
& 0x00000800u
) >> 11;
11313 bfd_vma offset
= 0;
11315 offset
|= !S
<< 20;
11316 offset
|= J2
<< 19;
11317 offset
|= J1
<< 18;
11318 offset
|= (given
& 0x003f0000) >> 4;
11319 offset
|= (given
& 0x000007ff) << 1;
11320 offset
-= (1 << 20);
11322 bfd_vma target
= pc
+ 4 + offset
;
11323 info
->print_address_func (target
, info
);
11325 /* Fill in instruction information. */
11326 info
->insn_info_valid
= 1;
11327 info
->insn_type
= dis_branch
;
11328 info
->target
= target
;
11334 unsigned int S
= (given
& 0x04000000u
) >> 26;
11335 unsigned int I1
= (given
& 0x00002000u
) >> 13;
11336 unsigned int I2
= (given
& 0x00000800u
) >> 11;
11337 bfd_vma offset
= 0;
11339 offset
|= !S
<< 24;
11340 offset
|= !(I1
^ S
) << 23;
11341 offset
|= !(I2
^ S
) << 22;
11342 offset
|= (given
& 0x03ff0000u
) >> 4;
11343 offset
|= (given
& 0x000007ffu
) << 1;
11344 offset
-= (1 << 24);
11347 /* BLX target addresses are always word aligned. */
11348 if ((given
& 0x00001000u
) == 0)
11351 info
->print_address_func (offset
, info
);
11353 /* Fill in instruction information. */
11354 info
->insn_info_valid
= 1;
11355 info
->insn_type
= dis_branch
;
11356 info
->target
= offset
;
11362 unsigned int shift
= 0;
11364 shift
|= (given
& 0x000000c0u
) >> 6;
11365 shift
|= (given
& 0x00007000u
) >> 10;
11366 if (WRITEBACK_BIT_SET
)
11367 func (stream
, ", asr #%u", shift
);
11369 func (stream
, ", lsl #%u", shift
);
11370 /* else print nothing - lsl #0 */
11376 unsigned int rot
= (given
& 0x00000030) >> 4;
11379 func (stream
, ", ror #%u", rot
* 8);
11384 if ((given
& 0xf0) == 0x60)
11386 switch (given
& 0xf)
11388 case 0xf: func (stream
, "sy"); break;
11390 func (stream
, "#%d", (int) given
& 0xf);
11396 const char * opt
= data_barrier_option (given
& 0xf);
11398 func (stream
, "%s", opt
);
11400 func (stream
, "#%d", (int) given
& 0xf);
11405 if ((given
& 0xff) == 0)
11407 func (stream
, "%cPSR_", (given
& 0x100000) ? 'S' : 'C');
11409 func (stream
, "f");
11411 func (stream
, "s");
11413 func (stream
, "x");
11415 func (stream
, "c");
11417 else if ((given
& 0x20) == 0x20)
11420 unsigned sysm
= (given
& 0xf00) >> 8;
11422 sysm
|= (given
& 0x30);
11423 sysm
|= (given
& 0x00100000) >> 14;
11424 name
= banked_regname (sysm
);
11427 func (stream
, "%s", name
);
11429 func (stream
, "(UNDEF: %lu)", (unsigned long) sysm
);
11433 func (stream
, "%s", psr_name (given
& 0xff));
11438 if (((given
& 0xff) == 0)
11439 || ((given
& 0x20) == 0x20))
11442 unsigned sm
= (given
& 0xf0000) >> 16;
11444 sm
|= (given
& 0x30);
11445 sm
|= (given
& 0x00100000) >> 14;
11446 name
= banked_regname (sm
);
11449 func (stream
, "%s", name
);
11451 func (stream
, "(UNDEF: %lu)", (unsigned long) sm
);
11454 func (stream
, "%s", psr_name (given
& 0xff));
11457 case '0': case '1': case '2': case '3': case '4':
11458 case '5': case '6': case '7': case '8': case '9':
11463 c
= arm_decode_bitfield (c
, given
, &val
, &width
);
11469 func (stream
, "%s", mve_vec_sizename
[val
]);
11471 func (stream
, "<undef size>");
11475 func (stream
, "%lu", val
);
11476 value_in_comment
= val
;
11480 func (stream
, "%lu", val
+ 1);
11481 value_in_comment
= val
+ 1;
11485 func (stream
, "%lu", val
* 4);
11486 value_in_comment
= val
* 4;
11491 is_unpredictable
= true;
11492 /* Fall through. */
11495 is_unpredictable
= true;
11496 /* Fall through. */
11498 func (stream
, "%s", arm_regnames
[val
]);
11502 func (stream
, "%s", arm_conditional
[val
]);
11507 if (val
== ((1ul << width
) - 1))
11508 func (stream
, "%c", *c
);
11514 func (stream
, "%c", *c
);
11518 func (stream
, "%c", c
[(1 << width
) - (int) val
]);
11523 func (stream
, "0x%lx", val
& 0xffffffffUL
);
11533 /* PR binutils/12534
11534 If we have a PC relative offset in an LDRD or STRD
11535 instructions then display the decoded address. */
11536 if (((given
>> 16) & 0xf) == 0xf)
11538 bfd_vma offset
= (given
& 0xff) * 4;
11540 if ((given
& (1 << 23)) == 0)
11542 func (stream
, "\t; ");
11543 info
->print_address_func ((pc
& ~3) + 4 + offset
, info
);
11552 if (value_in_comment
> 32 || value_in_comment
< -16)
11553 func (stream
, "\t; 0x%lx", value_in_comment
);
11555 if (is_unpredictable
)
11556 func (stream
, UNPREDICTABLE_INSTRUCTION
);
11562 func (stream
, UNKNOWN_INSTRUCTION_32BIT
, (unsigned)given
);
11566 /* Print data bytes on INFO->STREAM. */
11569 print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED
,
11570 struct disassemble_info
*info
,
11573 switch (info
->bytes_per_chunk
)
11576 info
->fprintf_func (info
->stream
, ".byte\t0x%02lx", given
);
11579 info
->fprintf_func (info
->stream
, ".short\t0x%04lx", given
);
11582 info
->fprintf_func (info
->stream
, ".word\t0x%08lx", given
);
11589 /* Disallow mapping symbols ($a, $b, $d, $t etc) from
11590 being displayed in symbol relative addresses.
11592 Also disallow private symbol, with __tagsym$$ prefix,
11593 from ARM RVCT toolchain being displayed. */
11596 arm_symbol_is_valid (asymbol
* sym
,
11597 struct disassemble_info
* info ATTRIBUTE_UNUSED
)
11604 name
= bfd_asymbol_name (sym
);
11606 return (name
&& *name
!= '$' && strncmp (name
, "__tagsym$$", 10));
11609 /* Parse the string of disassembler options. */
11612 parse_arm_disassembler_options (const char *options
)
11616 force_thumb
= false;
11617 FOR_EACH_DISASSEMBLER_OPTION (opt
, options
)
11619 if (startswith (opt
, "reg-names-"))
11622 for (i
= 0; i
< NUM_ARM_OPTIONS
; i
++)
11623 if (disassembler_options_cmp (opt
, regnames
[i
].name
) == 0)
11625 regname_selected
= i
;
11629 if (i
>= NUM_ARM_OPTIONS
)
11630 /* xgettext: c-format */
11631 opcodes_error_handler (_("unrecognised register name set: %s"),
11634 else if (startswith (opt
, "force-thumb"))
11636 else if (startswith (opt
, "no-force-thumb"))
11638 else if (startswith (opt
, "coproc"))
11640 const char *procptr
= opt
+ sizeof ("coproc") - 1;
11642 uint8_t coproc_number
= strtol (procptr
, &endptr
, 10);
11643 if (endptr
!= procptr
+ 1 || coproc_number
> 7)
11645 opcodes_error_handler (_("cde coprocessor not between 0-7: %s"),
11649 if (*endptr
!= '=')
11651 opcodes_error_handler (_("coproc must have an argument: %s"),
11656 if (startswith (endptr
, "generic"))
11657 cde_coprocs
&= ~(1 << coproc_number
);
11658 else if (startswith (endptr
, "cde")
11659 || startswith (endptr
, "CDE"))
11660 cde_coprocs
|= (1 << coproc_number
);
11663 opcodes_error_handler (
11664 _("coprocN argument takes options \"generic\","
11665 " \"cde\", or \"CDE\": %s"), opt
);
11669 /* xgettext: c-format */
11670 opcodes_error_handler (_("unrecognised disassembler option: %s"), opt
);
11677 mapping_symbol_for_insn (bfd_vma pc
, struct disassemble_info
*info
,
11678 enum map_type
*map_symbol
);
11680 /* Search back through the insn stream to determine if this instruction is
11681 conditionally executed. */
11684 find_ifthen_state (bfd_vma pc
,
11685 struct disassemble_info
*info
,
11688 unsigned char b
[2];
11691 /* COUNT is twice the number of instructions seen. It will be odd if we
11692 just crossed an instruction boundary. */
11695 unsigned int seen_it
;
11698 ifthen_address
= pc
;
11705 /* Scan backwards looking for IT instructions, keeping track of where
11706 instruction boundaries are. We don't know if something is actually an
11707 IT instruction until we find a definite instruction boundary. */
11710 if (addr
== 0 || info
->symbol_at_address_func (addr
, info
))
11712 /* A symbol must be on an instruction boundary, and will not
11713 be within an IT block. */
11714 if (seen_it
&& (count
& 1))
11720 status
= info
->read_memory_func (addr
, (bfd_byte
*) b
, 2, info
);
11725 insn
= (b
[0]) | (b
[1] << 8);
11727 insn
= (b
[1]) | (b
[0] << 8);
11730 if ((insn
& 0xf800) < 0xe800)
11732 /* Addr + 2 is an instruction boundary. See if this matches
11733 the expected boundary based on the position of the last
11740 if ((insn
& 0xff00) == 0xbf00 && (insn
& 0xf) != 0)
11742 enum map_type type
= MAP_ARM
;
11743 bool found
= mapping_symbol_for_insn (addr
, info
, &type
);
11745 if (!found
|| (found
&& type
== MAP_THUMB
))
11747 /* This could be an IT instruction. */
11749 it_count
= count
>> 1;
11752 if ((insn
& 0xf800) >= 0xe800)
11755 count
= (count
+ 2) | 1;
11756 /* IT blocks contain at most 4 instructions. */
11757 if (count
>= 8 && !seen_it
)
11760 /* We found an IT instruction. */
11761 ifthen_state
= (seen_it
& 0xe0) | ((seen_it
<< it_count
) & 0x1f);
11762 if ((ifthen_state
& 0xf) == 0)
11766 /* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
11770 is_mapping_symbol (struct disassemble_info
*info
, int n
,
11771 enum map_type
*map_type
)
11775 name
= bfd_asymbol_name (info
->symtab
[n
]);
11776 if (name
[0] == '$' && (name
[1] == 'a' || name
[1] == 't' || name
[1] == 'd')
11777 && (name
[2] == 0 || name
[2] == '.'))
11779 *map_type
= ((name
[1] == 'a') ? MAP_ARM
11780 : (name
[1] == 't') ? MAP_THUMB
11788 /* Try to infer the code type (ARM or Thumb) from a mapping symbol.
11789 Returns nonzero if *MAP_TYPE was set. */
11792 get_map_sym_type (struct disassemble_info
*info
,
11794 enum map_type
*map_type
)
11796 /* If the symbol is in a different section, ignore it. */
11797 if (info
->section
!= NULL
&& info
->section
!= info
->symtab
[n
]->section
)
11800 return is_mapping_symbol (info
, n
, map_type
);
11803 /* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
11804 Returns nonzero if *MAP_TYPE was set. */
11807 get_sym_code_type (struct disassemble_info
*info
,
11809 enum map_type
*map_type
)
11811 elf_symbol_type
*es
;
11814 /* If the symbol is in a different section, ignore it. */
11815 if (info
->section
!= NULL
&& info
->section
!= info
->symtab
[n
]->section
)
11818 es
= *(elf_symbol_type
**)(info
->symtab
+ n
);
11819 type
= ELF_ST_TYPE (es
->internal_elf_sym
.st_info
);
11821 /* If the symbol has function type then use that. */
11822 if (type
== STT_FUNC
|| type
== STT_GNU_IFUNC
)
11824 if (ARM_GET_SYM_BRANCH_TYPE (es
->internal_elf_sym
.st_target_internal
)
11825 == ST_BRANCH_TO_THUMB
)
11826 *map_type
= MAP_THUMB
;
11828 *map_type
= MAP_ARM
;
11835 /* Search the mapping symbol state for instruction at pc. This is only
11836 applicable for elf target.
11838 There is an assumption Here, info->private_data contains the correct AND
11839 up-to-date information about current scan process. The information will be
11840 used to speed this search process.
11842 Return TRUE if the mapping state can be determined, and map_symbol
11843 will be updated accordingly. Otherwise, return FALSE. */
11846 mapping_symbol_for_insn (bfd_vma pc
, struct disassemble_info
*info
,
11847 enum map_type
*map_symbol
)
11849 bfd_vma addr
, section_vma
= 0;
11850 int n
, last_sym
= -1;
11851 bool found
= false;
11852 bool can_use_search_opt_p
= false;
11854 /* Default to DATA. A text section is required by the ABI to contain an
11855 INSN mapping symbol at the start. A data section has no such
11856 requirement, hence if no mapping symbol is found the section must
11857 contain only data. This however isn't very useful if the user has
11858 fully stripped the binaries. If this is the case use the section
11859 attributes to determine the default. If we have no section default to
11860 INSN as well, as we may be disassembling some raw bytes on a baremetal
11861 HEX file or similar. */
11862 enum map_type type
= MAP_DATA
;
11863 if ((info
->section
&& info
->section
->flags
& SEC_CODE
) || !info
->section
)
11865 struct arm_private_data
*private_data
;
11867 if (info
->private_data
== NULL
11868 || bfd_asymbol_flavour (*info
->symtab
) != bfd_target_elf_flavour
)
11871 private_data
= info
->private_data
;
11873 /* First, look for mapping symbols. */
11874 if (info
->symtab_size
!= 0)
11876 if (pc
<= private_data
->last_mapping_addr
)
11877 private_data
->last_mapping_sym
= -1;
11879 /* Start scanning at the start of the function, or wherever
11880 we finished last time. */
11881 n
= info
->symtab_pos
+ 1;
11883 /* If the last stop offset is different from the current one it means we
11884 are disassembling a different glob of bytes. As such the optimization
11885 would not be safe and we should start over. */
11886 can_use_search_opt_p
11887 = private_data
->last_mapping_sym
>= 0
11888 && info
->stop_offset
== private_data
->last_stop_offset
;
11890 if (n
>= private_data
->last_mapping_sym
&& can_use_search_opt_p
)
11891 n
= private_data
->last_mapping_sym
;
11893 /* Look down while we haven't passed the location being disassembled.
11894 The reason for this is that there's no defined order between a symbol
11895 and an mapping symbol that may be at the same address. We may have to
11896 look at least one position ahead. */
11897 for (; n
< info
->symtab_size
; n
++)
11899 addr
= bfd_asymbol_value (info
->symtab
[n
]);
11902 if (get_map_sym_type (info
, n
, &type
))
11911 n
= info
->symtab_pos
;
11912 if (n
>= private_data
->last_mapping_sym
&& can_use_search_opt_p
)
11913 n
= private_data
->last_mapping_sym
;
11915 /* No mapping symbol found at this address. Look backwards
11916 for a preceeding one, but don't go pass the section start
11917 otherwise a data section with no mapping symbol can pick up
11918 a text mapping symbol of a preceeding section. The documentation
11919 says section can be NULL, in which case we will seek up all the
11922 section_vma
= info
->section
->vma
;
11924 for (; n
>= 0; n
--)
11926 addr
= bfd_asymbol_value (info
->symtab
[n
]);
11927 if (addr
< section_vma
)
11930 if (get_map_sym_type (info
, n
, &type
))
11940 /* If no mapping symbol was found, try looking up without a mapping
11941 symbol. This is done by walking up from the current PC to the nearest
11942 symbol. We don't actually have to loop here since symtab_pos will
11943 contain the nearest symbol already. */
11946 n
= info
->symtab_pos
;
11947 if (n
>= 0 && get_sym_code_type (info
, n
, &type
))
11954 private_data
->last_mapping_sym
= last_sym
;
11955 private_data
->last_type
= type
;
11956 private_data
->last_stop_offset
= info
->stop_offset
;
11958 *map_symbol
= type
;
11962 /* Given a bfd_mach_arm_XXX value, this function fills in the fields
11963 of the supplied arm_feature_set structure with bitmasks indicating
11964 the supported base architectures and coprocessor extensions.
11966 FIXME: This could more efficiently implemented as a constant array,
11967 although it would also be less robust. */
11970 select_arm_features (unsigned long mach
,
11971 arm_feature_set
* features
)
11973 arm_feature_set arch_fset
;
11974 const arm_feature_set fpu_any
= FPU_ANY
;
11976 #undef ARM_SET_FEATURES
11977 #define ARM_SET_FEATURES(FSET) \
11979 const arm_feature_set fset = FSET; \
11980 arch_fset = fset; \
11983 /* When several architecture versions share the same bfd_mach_arm_XXX value
11984 the most featureful is chosen. */
11987 case bfd_mach_arm_2
: ARM_SET_FEATURES (ARM_ARCH_V2
); break;
11988 case bfd_mach_arm_2a
: ARM_SET_FEATURES (ARM_ARCH_V2S
); break;
11989 case bfd_mach_arm_3
: ARM_SET_FEATURES (ARM_ARCH_V3
); break;
11990 case bfd_mach_arm_3M
: ARM_SET_FEATURES (ARM_ARCH_V3M
); break;
11991 case bfd_mach_arm_4
: ARM_SET_FEATURES (ARM_ARCH_V4
); break;
11992 case bfd_mach_arm_4T
: ARM_SET_FEATURES (ARM_ARCH_V4T
); break;
11993 case bfd_mach_arm_5
: ARM_SET_FEATURES (ARM_ARCH_V5
); break;
11994 case bfd_mach_arm_5T
: ARM_SET_FEATURES (ARM_ARCH_V5T
); break;
11995 case bfd_mach_arm_5TE
: ARM_SET_FEATURES (ARM_ARCH_V5TE
); break;
11996 case bfd_mach_arm_XScale
: ARM_SET_FEATURES (ARM_ARCH_XSCALE
); break;
11997 case bfd_mach_arm_ep9312
:
11998 ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T
,
11999 ARM_CEXT_MAVERICK
| FPU_MAVERICK
));
12001 case bfd_mach_arm_iWMMXt
: ARM_SET_FEATURES (ARM_ARCH_IWMMXT
); break;
12002 case bfd_mach_arm_iWMMXt2
: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2
); break;
12003 case bfd_mach_arm_5TEJ
: ARM_SET_FEATURES (ARM_ARCH_V5TEJ
); break;
12004 case bfd_mach_arm_6
: ARM_SET_FEATURES (ARM_ARCH_V6
); break;
12005 case bfd_mach_arm_6KZ
: ARM_SET_FEATURES (ARM_ARCH_V6KZ
); break;
12006 case bfd_mach_arm_6T2
: ARM_SET_FEATURES (ARM_ARCH_V6KZT2
); break;
12007 case bfd_mach_arm_6K
: ARM_SET_FEATURES (ARM_ARCH_V6K
); break;
12008 case bfd_mach_arm_7
: ARM_SET_FEATURES (ARM_ARCH_V7VE
); break;
12009 case bfd_mach_arm_6M
: ARM_SET_FEATURES (ARM_ARCH_V6M
); break;
12010 case bfd_mach_arm_6SM
: ARM_SET_FEATURES (ARM_ARCH_V6SM
); break;
12011 case bfd_mach_arm_7EM
: ARM_SET_FEATURES (ARM_ARCH_V7EM
); break;
12012 case bfd_mach_arm_8
:
12014 /* Add bits for extensions that Armv8.6-A recognizes. */
12015 arm_feature_set armv8_6_ext_fset
12016 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
12017 ARM_SET_FEATURES (ARM_ARCH_V8_6A
);
12018 ARM_MERGE_FEATURE_SETS (arch_fset
, arch_fset
, armv8_6_ext_fset
);
12021 case bfd_mach_arm_8R
: ARM_SET_FEATURES (ARM_ARCH_V8R
); break;
12022 case bfd_mach_arm_8M_BASE
: ARM_SET_FEATURES (ARM_ARCH_V8M_BASE
); break;
12023 case bfd_mach_arm_8M_MAIN
: ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN
); break;
12024 case bfd_mach_arm_8_1M_MAIN
:
12025 ARM_SET_FEATURES (ARM_ARCH_V8_1M_MAIN
);
12026 arm_feature_set mve_all
12027 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
| ARM_EXT2_MVE_FP
);
12028 ARM_MERGE_FEATURE_SETS (arch_fset
, arch_fset
, mve_all
);
12031 case bfd_mach_arm_9
: ARM_SET_FEATURES (ARM_ARCH_V9A
); break;
12032 /* If the machine type is unknown allow all architecture types and all
12033 extensions, with the exception of MVE as that clashes with NEON. */
12034 case bfd_mach_arm_unknown
:
12035 ARM_SET_FEATURES (ARM_ARCH_UNKNOWN
);
12040 #undef ARM_SET_FEATURES
12042 /* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch
12043 and thus on bfd_mach_arm_XXX value. Therefore for a given
12044 bfd_mach_arm_XXX value all coprocessor feature bits should be allowed. */
12045 ARM_MERGE_FEATURE_SETS (*features
, arch_fset
, fpu_any
);
12049 /* NOTE: There are no checks in these routines that
12050 the relevant number of data bytes exist. */
12053 print_insn (bfd_vma pc
, struct disassemble_info
*info
, bool little
)
12055 unsigned char b
[4];
12056 unsigned long given
;
12058 int is_thumb
= false;
12059 int is_data
= false;
12061 unsigned int size
= 4;
12062 void (*printer
) (bfd_vma
, struct disassemble_info
*, long);
12063 bool found
= false;
12064 struct arm_private_data
*private_data
;
12066 /* Clear instruction information field. */
12067 info
->insn_info_valid
= 0;
12068 info
->branch_delay_insns
= 0;
12069 info
->data_size
= 0;
12070 info
->insn_type
= dis_noninsn
;
12074 if (info
->disassembler_options
)
12076 parse_arm_disassembler_options (info
->disassembler_options
);
12078 /* To avoid repeated parsing of these options, we remove them here. */
12079 info
->disassembler_options
= NULL
;
12082 /* PR 10288: Control which instructions will be disassembled. */
12083 if (info
->private_data
== NULL
)
12085 static struct arm_private_data
private;
12087 if ((info
->flags
& USER_SPECIFIED_MACHINE_TYPE
) == 0)
12088 /* If the user did not use the -m command line switch then default to
12089 disassembling all types of ARM instruction.
12091 The info->mach value has to be ignored as this will be based on
12092 the default archictecture for the target and/or hints in the notes
12093 section, but it will never be greater than the current largest arm
12094 machine value (iWMMXt2), which is only equivalent to the V5TE
12095 architecture. ARM architectures have advanced beyond the machine
12096 value encoding, and these newer architectures would be ignored if
12097 the machine value was used.
12099 Ie the -m switch is used to restrict which instructions will be
12100 disassembled. If it is necessary to use the -m switch to tell
12101 objdump that an ARM binary is being disassembled, eg because the
12102 input is a raw binary file, but it is also desired to disassemble
12103 all ARM instructions then use "-marm". This will select the
12104 "unknown" arm architecture which is compatible with any ARM
12106 info
->mach
= bfd_mach_arm_unknown
;
12108 /* Compute the architecture bitmask from the machine number.
12109 Note: This assumes that the machine number will not change
12110 during disassembly.... */
12111 select_arm_features (info
->mach
, & private.features
);
12113 private.last_mapping_sym
= -1;
12114 private.last_mapping_addr
= 0;
12115 private.last_stop_offset
= 0;
12117 info
->private_data
= & private;
12120 private_data
= info
->private_data
;
12122 /* Decide if our code is going to be little-endian, despite what the
12123 function argument might say. */
12124 little_code
= ((info
->endian_code
== BFD_ENDIAN_LITTLE
) || little
);
12126 /* For ELF, consult the symbol table to determine what kind of code
12127 or data we have. */
12128 if (info
->symtab_size
!= 0
12129 && bfd_asymbol_flavour (*info
->symtab
) == bfd_target_elf_flavour
)
12134 enum map_type type
= MAP_ARM
;
12136 found
= mapping_symbol_for_insn (pc
, info
, &type
);
12137 last_sym
= private_data
->last_mapping_sym
;
12139 is_thumb
= (private_data
->last_type
== MAP_THUMB
);
12140 is_data
= (private_data
->last_type
== MAP_DATA
);
12142 /* Look a little bit ahead to see if we should print out
12143 two or four bytes of data. If there's a symbol,
12144 mapping or otherwise, after two bytes then don't
12148 size
= 4 - (pc
& 3);
12149 for (n
= last_sym
+ 1; n
< info
->symtab_size
; n
++)
12151 addr
= bfd_asymbol_value (info
->symtab
[n
]);
12153 && (info
->section
== NULL
12154 || info
->section
== info
->symtab
[n
]->section
))
12156 if (addr
- pc
< size
)
12161 /* If the next symbol is after three bytes, we need to
12162 print only part of the data, so that we can use either
12163 .byte or .short. */
12165 size
= (pc
& 1) ? 1 : 2;
12169 if (info
->symbols
!= NULL
)
12171 if (bfd_asymbol_flavour (*info
->symbols
) == bfd_target_coff_flavour
)
12173 coff_symbol_type
* cs
;
12175 cs
= coffsymbol (*info
->symbols
);
12176 is_thumb
= ( cs
->native
->u
.syment
.n_sclass
== C_THUMBEXT
12177 || cs
->native
->u
.syment
.n_sclass
== C_THUMBSTAT
12178 || cs
->native
->u
.syment
.n_sclass
== C_THUMBLABEL
12179 || cs
->native
->u
.syment
.n_sclass
== C_THUMBEXTFUNC
12180 || cs
->native
->u
.syment
.n_sclass
== C_THUMBSTATFUNC
);
12182 else if (bfd_asymbol_flavour (*info
->symbols
) == bfd_target_elf_flavour
12185 /* If no mapping symbol has been found then fall back to the type
12186 of the function symbol. */
12187 elf_symbol_type
* es
;
12190 es
= *(elf_symbol_type
**)(info
->symbols
);
12191 type
= ELF_ST_TYPE (es
->internal_elf_sym
.st_info
);
12194 ((ARM_GET_SYM_BRANCH_TYPE (es
->internal_elf_sym
.st_target_internal
)
12195 == ST_BRANCH_TO_THUMB
) || type
== STT_ARM_16BIT
);
12197 else if (bfd_asymbol_flavour (*info
->symbols
)
12198 == bfd_target_mach_o_flavour
)
12200 bfd_mach_o_asymbol
*asym
= (bfd_mach_o_asymbol
*)*info
->symbols
;
12202 is_thumb
= (asym
->n_desc
& BFD_MACH_O_N_ARM_THUMB_DEF
);
12210 info
->display_endian
= little
? BFD_ENDIAN_LITTLE
: BFD_ENDIAN_BIG
;
12212 info
->display_endian
= little_code
? BFD_ENDIAN_LITTLE
: BFD_ENDIAN_BIG
;
12214 info
->bytes_per_line
= 4;
12216 /* PR 10263: Disassemble data if requested to do so by the user. */
12217 if (is_data
&& ((info
->flags
& DISASSEMBLE_DATA
) == 0))
12221 /* Size was already set above. */
12222 info
->bytes_per_chunk
= size
;
12223 printer
= print_insn_data
;
12225 status
= info
->read_memory_func (pc
, (bfd_byte
*) b
, size
, info
);
12228 for (i
= size
- 1; i
>= 0; i
--)
12229 given
= b
[i
] | (given
<< 8);
12231 for (i
= 0; i
< (int) size
; i
++)
12232 given
= b
[i
] | (given
<< 8);
12234 else if (!is_thumb
)
12236 /* In ARM mode endianness is a straightforward issue: the instruction
12237 is four bytes long and is either ordered 0123 or 3210. */
12238 printer
= print_insn_arm
;
12239 info
->bytes_per_chunk
= 4;
12242 status
= info
->read_memory_func (pc
, (bfd_byte
*) b
, 4, info
);
12244 given
= (b
[0]) | (b
[1] << 8) | (b
[2] << 16) | ((unsigned) b
[3] << 24);
12246 given
= (b
[3]) | (b
[2] << 8) | (b
[1] << 16) | ((unsigned) b
[0] << 24);
12250 /* In Thumb mode we have the additional wrinkle of two
12251 instruction lengths. Fortunately, the bits that determine
12252 the length of the current instruction are always to be found
12253 in the first two bytes. */
12254 printer
= print_insn_thumb16
;
12255 info
->bytes_per_chunk
= 2;
12258 status
= info
->read_memory_func (pc
, (bfd_byte
*) b
, 2, info
);
12260 given
= (b
[0]) | (b
[1] << 8);
12262 given
= (b
[1]) | (b
[0] << 8);
12266 /* These bit patterns signal a four-byte Thumb
12268 if ((given
& 0xF800) == 0xF800
12269 || (given
& 0xF800) == 0xF000
12270 || (given
& 0xF800) == 0xE800)
12272 status
= info
->read_memory_func (pc
+ 2, (bfd_byte
*) b
, 2, info
);
12274 given
= (b
[0]) | (b
[1] << 8) | (given
<< 16);
12276 given
= (b
[1]) | (b
[0] << 8) | (given
<< 16);
12278 printer
= print_insn_thumb32
;
12283 if (ifthen_address
!= pc
)
12284 find_ifthen_state (pc
, info
, little_code
);
12288 if ((ifthen_state
& 0xf) == 0x8)
12289 ifthen_next_state
= 0;
12291 ifthen_next_state
= (ifthen_state
& 0xe0)
12292 | ((ifthen_state
& 0xf) << 1);
12298 info
->memory_error_func (status
, pc
, info
);
12301 if (info
->flags
& INSN_HAS_RELOC
)
12302 /* If the instruction has a reloc associated with it, then
12303 the offset field in the instruction will actually be the
12304 addend for the reloc. (We are using REL type relocs).
12305 In such cases, we can ignore the pc when computing
12306 addresses, since the addend is not currently pc-relative. */
12309 printer (pc
, info
, given
);
12313 ifthen_state
= ifthen_next_state
;
12314 ifthen_address
+= size
;
12320 print_insn_big_arm (bfd_vma pc
, struct disassemble_info
*info
)
12322 /* Detect BE8-ness and record it in the disassembler info. */
12323 if (info
->flavour
== bfd_target_elf_flavour
12324 && info
->section
!= NULL
12325 && (elf_elfheader (info
->section
->owner
)->e_flags
& EF_ARM_BE8
))
12326 info
->endian_code
= BFD_ENDIAN_LITTLE
;
12328 return print_insn (pc
, info
, false);
12332 print_insn_little_arm (bfd_vma pc
, struct disassemble_info
*info
)
12334 return print_insn (pc
, info
, true);
12337 const disasm_options_and_args_t
*
12338 disassembler_options_arm (void)
12340 static disasm_options_and_args_t
*opts_and_args
;
12342 if (opts_and_args
== NULL
)
12344 disasm_options_t
*opts
;
12347 opts_and_args
= XNEW (disasm_options_and_args_t
);
12348 opts_and_args
->args
= NULL
;
12350 opts
= &opts_and_args
->options
;
12351 opts
->name
= XNEWVEC (const char *, NUM_ARM_OPTIONS
+ 1);
12352 opts
->description
= XNEWVEC (const char *, NUM_ARM_OPTIONS
+ 1);
12354 for (i
= 0; i
< NUM_ARM_OPTIONS
; i
++)
12356 opts
->name
[i
] = regnames
[i
].name
;
12357 if (regnames
[i
].description
!= NULL
)
12358 opts
->description
[i
] = _(regnames
[i
].description
);
12360 opts
->description
[i
] = NULL
;
12362 /* The array we return must be NULL terminated. */
12363 opts
->name
[i
] = NULL
;
12364 opts
->description
[i
] = NULL
;
12367 return opts_and_args
;
12371 print_arm_disassembler_options (FILE *stream
)
12373 unsigned int i
, max_len
= 0;
12374 fprintf (stream
, _("\n\
12375 The following ARM specific disassembler options are supported for use with\n\
12376 the -M switch:\n"));
12378 for (i
= 0; i
< NUM_ARM_OPTIONS
; i
++)
12380 unsigned int len
= strlen (regnames
[i
].name
);
12385 for (i
= 0, max_len
++; i
< NUM_ARM_OPTIONS
; i
++)
12386 fprintf (stream
, " %s%*c %s\n",
12388 (int)(max_len
- strlen (regnames
[i
].name
)), ' ',
12389 _(regnames
[i
].description
));