projects / binutils-gdb.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
Rename parse_disassembler_option to parse_arm_disassembler_option and allow it
[binutils-gdb.git] / opcodes / arm-dis.c
1 /* Instruction printing code for the ARM
2 Copyright (C) 1994, 95, 96, 97, 98, 99, 2000 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
5
6 This file is part of libopcodes.
7
8 This program is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 2 of the License, or (at your option)
11 any later version.
12
13 This program is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
21
22 #include "sysdep.h"
23 #include "dis-asm.h"
24 #define DEFINE_TABLE
25 #include "arm-opc.h"
26 #include "coff/internal.h"
27 #include "libcoff.h"
28 #include "opintl.h"
29
30 /* FIXME: This shouldn't be done here */
31 #include "elf-bfd.h"
32 #include "elf/internal.h"
33 #include "elf/arm.h"
34
35 #ifndef streq
36 #define streq(a,b) (strcmp ((a), (b)) == 0)
37 #endif
38
39 #ifndef strneq
40 #define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
41 #endif
42
43 #ifndef NUM_ELEM
44 #define NUM_ELEM(a) (sizeof (a) / sizeof (a)[0])
45 #endif
46
47 static char * arm_conditional[] =
48 {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
49 "hi", "ls", "ge", "lt", "gt", "le", "", "nv"};
50
51 typedef struct
52 {
53 const char * name;
54 const char * description;
55 const char * reg_names[16];
56 }
57 arm_regname;
58
59 static arm_regname regnames[] =
60 {
61 { "raw" , "Select raw register names",
62 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
63 { "std", "Select register names used in ARM's ISA documentation",
64 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
65 { "apcs", "Select register names used in the APCS",
66 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
67 { "atpcs", "Select register names used in the ATPCS",
68 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
69 { "atpcs-special", "Select special register names used in the ATPCS",
70 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }}
71 };
72
73 /* Default to standard register name set. */
74 static unsigned int regname_selected = 1;
75
76 #define NUM_ARM_REGNAMES NUM_ELEM (regnames)
77 #define arm_regnames regnames[regname_selected].reg_names
78
79 static boolean force_thumb = false;
80
81 static char * arm_fp_const[] =
82 {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
83
84 static char * arm_shift[] =
85 {"lsl", "lsr", "asr", "ror"};
86 \f
87 /* Forward declarations. */
88 static void arm_decode_shift PARAMS ((long, fprintf_ftype, void *));
89 static int print_insn_arm PARAMS ((bfd_vma, struct disassemble_info *, long));
90 static int print_insn_thumb PARAMS ((bfd_vma, struct disassemble_info *, long));
91 static void parse_disassembler_options PARAMS ((char *));
92 static int print_insn PARAMS ((bfd_vma, struct disassemble_info *, boolean));
93 \f
94 /* Functions. */
95 static void
96 arm_decode_shift (given, func, stream)
97 long given;
98 fprintf_ftype func;
99 void * stream;
100 {
101 func (stream, "%s", arm_regnames[given & 0xf]);
102
103 if ((given & 0xff0) != 0)
104 {
105 if ((given & 0x10) == 0)
106 {
107 int amount = (given & 0xf80) >> 7;
108 int shift = (given & 0x60) >> 5;
109
110 if (amount == 0)
111 {
112 if (shift == 3)
113 {
114 func (stream, ", rrx");
115 return;
116 }
117
118 amount = 32;
119 }
120
121 func (stream, ", %s #%d", arm_shift[shift], amount);
122 }
123 else
124 func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
125 arm_regnames[(given & 0xf00) >> 8]);
126 }
127 }
128
129 /* Print one instruction from PC on INFO->STREAM.
130 Return the size of the instruction (always 4 on ARM). */
131 static int
132 print_insn_arm (pc, info, given)
133 bfd_vma pc;
134 struct disassemble_info * info;
135 long given;
136 {
137 struct arm_opcode * insn;
138 void * stream = info->stream;
139 fprintf_ftype func = info->fprintf_func;
140
141 for (insn = arm_opcodes; insn->assembler; insn++)
142 {
143 if ((given & insn->mask) == insn->value)
144 {
145 char * c;
146
147 for (c = insn->assembler; *c; c++)
148 {
149 if (*c == '%')
150 {
151 switch (*++c)
152 {
153 case '%':
154 func (stream, "%%");
155 break;
156
157 case 'a':
158 if (((given & 0x000f0000) == 0x000f0000)
159 && ((given & 0x02000000) == 0))
160 {
161 int offset = given & 0xfff;
162
163 func (stream, "[pc");
164
165 if (given & 0x01000000)
166 {
167 if ((given & 0x00800000) == 0)
168 offset = - offset;
169
170 /* pre-indexed */
171 func (stream, ", #%x]", offset);
172
173 offset += pc + 8;
174
175 /* Cope with the possibility of write-back
176 being used. Probably a very dangerous thing
177 for the programmer to do, but who are we to
178 argue ? */
179 if (given & 0x00200000)
180 func (stream, "!");
181 }
182 else
183 {
184 /* Post indexed. */
185 func (stream, "], #%x", offset);
186
187 offset = pc + 8; /* ie ignore the offset. */
188 }
189
190 func (stream, "\t; ");
191 info->print_address_func (offset, info);
192 }
193 else
194 {
195 func (stream, "[%s",
196 arm_regnames[(given >> 16) & 0xf]);
197 if ((given & 0x01000000) != 0)
198 {
199 if ((given & 0x02000000) == 0)
200 {
201 int offset = given & 0xfff;
202 if (offset)
203 func (stream, ", %s#%d",
204 (((given & 0x00800000) == 0)
205 ? "-" : ""), offset);
206 }
207 else
208 {
209 func (stream, ", %s",
210 (((given & 0x00800000) == 0)
211 ? "-" : ""));
212 arm_decode_shift (given, func, stream);
213 }
214
215 func (stream, "]%s",
216 ((given & 0x00200000) != 0) ? "!" : "");
217 }
218 else
219 {
220 if ((given & 0x02000000) == 0)
221 {
222 int offset = given & 0xfff;
223 if (offset)
224 func (stream, "], %s#%d",
225 (((given & 0x00800000) == 0)
226 ? "-" : ""), offset);
227 else
228 func (stream, "]");
229 }
230 else
231 {
232 func (stream, "], %s",
233 (((given & 0x00800000) == 0)
234 ? "-" : ""));
235 arm_decode_shift (given, func, stream);
236 }
237 }
238 }
239 break;
240
241 case 's':
242 if ((given & 0x004f0000) == 0x004f0000)
243 {
244 /* PC relative with immediate offset. */
245 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
246
247 if ((given & 0x00800000) == 0)
248 offset = -offset;
249
250 func (stream, "[pc, #%x]\t; ", offset);
251
252 (*info->print_address_func)
253 (offset + pc + 8, info);
254 }
255 else
256 {
257 func (stream, "[%s",
258 arm_regnames[(given >> 16) & 0xf]);
259 if ((given & 0x01000000) != 0)
260 {
261 /* Pre-indexed. */
262 if ((given & 0x00400000) == 0x00400000)
263 {
264 /* Immediate. */
265 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
266 if (offset)
267 func (stream, ", %s#%d",
268 (((given & 0x00800000) == 0)
269 ? "-" : ""), offset);
270 }
271 else
272 {
273 /* Register. */
274 func (stream, ", %s%s",
275 (((given & 0x00800000) == 0)
276 ? "-" : ""),
277 arm_regnames[given & 0xf]);
278 }
279
280 func (stream, "]%s",
281 ((given & 0x00200000) != 0) ? "!" : "");
282 }
283 else
284 {
285 /* Post-indexed. */
286 if ((given & 0x00400000) == 0x00400000)
287 {
288 /* Immediate. */
289 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
290 if (offset)
291 func (stream, "], %s#%d",
292 (((given & 0x00800000) == 0)
293 ? "-" : ""), offset);
294 else
295 func (stream, "]");
296 }
297 else
298 {
299 /* Register. */
300 func (stream, "], %s%s",
301 (((given & 0x00800000) == 0)
302 ? "-" : ""),
303 arm_regnames[given & 0xf]);
304 }
305 }
306 }
307 break;
308
309 case 'b':
310 (*info->print_address_func)
311 (BDISP (given) * 4 + pc + 8, info);
312 break;
313
314 case 'c':
315 func (stream, "%s",
316 arm_conditional [(given >> 28) & 0xf]);
317 break;
318
319 case 'm':
320 {
321 int started = 0;
322 int reg;
323
324 func (stream, "{");
325 for (reg = 0; reg < 16; reg++)
326 if ((given & (1 << reg)) != 0)
327 {
328 if (started)
329 func (stream, ", ");
330 started = 1;
331 func (stream, "%s", arm_regnames[reg]);
332 }
333 func (stream, "}");
334 }
335 break;
336
337 case 'o':
338 if ((given & 0x02000000) != 0)
339 {
340 int rotate = (given & 0xf00) >> 7;
341 int immed = (given & 0xff);
342 immed = (((immed << (32 - rotate))
343 | (immed >> rotate)) & 0xffffffff);
344 func (stream, "#%d\t; 0x%x", immed, immed);
345 }
346 else
347 arm_decode_shift (given, func, stream);
348 break;
349
350 case 'p':
351 if ((given & 0x0000f000) == 0x0000f000)
352 func (stream, "p");
353 break;
354
355 case 't':
356 if ((given & 0x01200000) == 0x00200000)
357 func (stream, "t");
358 break;
359
360 case 'h':
361 if ((given & 0x00000020) == 0x00000020)
362 func (stream, "h");
363 else
364 func (stream, "b");
365 break;
366
367 case 'A':
368 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
369 if ((given & 0x01000000) != 0)
370 {
371 int offset = given & 0xff;
372 if (offset)
373 func (stream, ", %s#%d]%s",
374 ((given & 0x00800000) == 0 ? "-" : ""),
375 offset * 4,
376 ((given & 0x00200000) != 0 ? "!" : ""));
377 else
378 func (stream, "]");
379 }
380 else
381 {
382 int offset = given & 0xff;
383 if (offset)
384 func (stream, "], %s#%d",
385 ((given & 0x00800000) == 0 ? "-" : ""),
386 offset * 4);
387 else
388 func (stream, "]");
389 }
390 break;
391
392 case 'C':
393 switch (given & 0x00090000)
394 {
395 default:
396 func (stream, "_???");
397 break;
398 case 0x90000:
399 func (stream, "_all");
400 break;
401 case 0x10000:
402 func (stream, "_ctl");
403 break;
404 case 0x80000:
405 func (stream, "_flg");
406 break;
407 }
408 break;
409
410 case 'F':
411 switch (given & 0x00408000)
412 {
413 case 0:
414 func (stream, "4");
415 break;
416 case 0x8000:
417 func (stream, "1");
418 break;
419 case 0x00400000:
420 func (stream, "2");
421 break;
422 default:
423 func (stream, "3");
424 }
425 break;
426
427 case 'P':
428 switch (given & 0x00080080)
429 {
430 case 0:
431 func (stream, "s");
432 break;
433 case 0x80:
434 func (stream, "d");
435 break;
436 case 0x00080000:
437 func (stream, "e");
438 break;
439 default:
440 func (stream, _("<illegal precision>"));
441 break;
442 }
443 break;
444 case 'Q':
445 switch (given & 0x00408000)
446 {
447 case 0:
448 func (stream, "s");
449 break;
450 case 0x8000:
451 func (stream, "d");
452 break;
453 case 0x00400000:
454 func (stream, "e");
455 break;
456 default:
457 func (stream, "p");
458 break;
459 }
460 break;
461 case 'R':
462 switch (given & 0x60)
463 {
464 case 0:
465 break;
466 case 0x20:
467 func (stream, "p");
468 break;
469 case 0x40:
470 func (stream, "m");
471 break;
472 default:
473 func (stream, "z");
474 break;
475 }
476 break;
477
478 case '0': case '1': case '2': case '3': case '4':
479 case '5': case '6': case '7': case '8': case '9':
480 {
481 int bitstart = *c++ - '0';
482 int bitend = 0;
483 while (*c >= '0' && *c <= '9')
484 bitstart = (bitstart * 10) + *c++ - '0';
485
486 switch (*c)
487 {
488 case '-':
489 c++;
490
491 while (*c >= '0' && *c <= '9')
492 bitend = (bitend * 10) + *c++ - '0';
493
494 if (!bitend)
495 abort ();
496
497 switch (*c)
498 {
499 case 'r':
500 {
501 long reg;
502
503 reg = given >> bitstart;
504 reg &= (2 << (bitend - bitstart)) - 1;
505
506 func (stream, "%s", arm_regnames[reg]);
507 }
508 break;
509 case 'd':
510 {
511 long reg;
512
513 reg = given >> bitstart;
514 reg &= (2 << (bitend - bitstart)) - 1;
515
516 func (stream, "%d", reg);
517 }
518 break;
519 case 'x':
520 {
521 long reg;
522
523 reg = given >> bitstart;
524 reg &= (2 << (bitend - bitstart)) - 1;
525
526 func (stream, "0x%08x", reg);
527
528 /* Some SWI instructions have special
529 meanings. */
530 if ((given & 0x0fffffff) == 0x0FF00000)
531 func (stream, "\t; IMB");
532 else if ((given & 0x0fffffff) == 0x0FF00001)
533 func (stream, "\t; IMBRange");
534 }
535 break;
536 case 'X':
537 {
538 long reg;
539
540 reg = given >> bitstart;
541 reg &= (2 << (bitend - bitstart)) - 1;
542
543 func (stream, "%01x", reg & 0xf);
544 }
545 break;
546 case 'f':
547 {
548 long reg;
549
550 reg = given >> bitstart;
551 reg &= (2 << (bitend - bitstart)) - 1;
552
553 if (reg > 7)
554 func (stream, "#%s",
555 arm_fp_const[reg & 7]);
556 else
557 func (stream, "f%d", reg);
558 }
559 break;
560 default:
561 abort ();
562 }
563 break;
564
565 case '`':
566 c++;
567 if ((given & (1 << bitstart)) == 0)
568 func (stream, "%c", *c);
569 break;
570 case '\'':
571 c++;
572 if ((given & (1 << bitstart)) != 0)
573 func (stream, "%c", *c);
574 break;
575 case '?':
576 ++c;
577 if ((given & (1 << bitstart)) != 0)
578 func (stream, "%c", *c++);
579 else
580 func (stream, "%c", *++c);
581 break;
582 default:
583 abort ();
584 }
585 break;
586
587 default:
588 abort ();
589 }
590 }
591 }
592 else
593 func (stream, "%c", *c);
594 }
595 return 4;
596 }
597 }
598 abort ();
599 }
600
601 /* Print one instruction from PC on INFO->STREAM.
602 Return the size of the instruction. */
603 static int
604 print_insn_thumb (pc, info, given)
605 bfd_vma pc;
606 struct disassemble_info * info;
607 long given;
608 {
609 struct thumb_opcode * insn;
610 void * stream = info->stream;
611 fprintf_ftype func = info->fprintf_func;
612
613 for (insn = thumb_opcodes; insn->assembler; insn++)
614 {
615 if ((given & insn->mask) == insn->value)
616 {
617 char * c = insn->assembler;
618
619 /* Special processing for Thumb 2 instruction BL sequence: */
620 if (!*c) /* Check for empty (not NULL) assembler string. */
621 {
622 info->bytes_per_chunk = 4;
623 info->bytes_per_line = 4;
624
625 func (stream, "bl\t");
626 info->print_address_func (BDISP23 (given) * 2 + pc + 4, info);
627 return 4;
628 }
629 else
630 {
631 info->bytes_per_chunk = 2;
632 info->bytes_per_line = 4;
633
634 given &= 0xffff;
635
636 for (; *c; c++)
637 {
638 if (*c == '%')
639 {
640 int domaskpc = 0;
641 int domasklr = 0;
642
643 switch (*++c)
644 {
645 case '%':
646 func (stream, "%%");
647 break;
648
649 case 'S':
650 {
651 long reg;
652
653 reg = (given >> 3) & 0x7;
654 if (given & (1 << 6))
655 reg += 8;
656
657 func (stream, "%s", arm_regnames[reg]);
658 }
659 break;
660
661 case 'D':
662 {
663 long reg;
664
665 reg = given & 0x7;
666 if (given & (1 << 7))
667 reg += 8;
668
669 func (stream, "%s", arm_regnames[reg]);
670 }
671 break;
672
673 case 'T':
674 func (stream, "%s",
675 arm_conditional [(given >> 8) & 0xf]);
676 break;
677
678 case 'N':
679 if (given & (1 << 8))
680 domasklr = 1;
681 /* Fall through. */
682 case 'O':
683 if (*c == 'O' && (given & (1 << 8)))
684 domaskpc = 1;
685 /* Fall through. */
686 case 'M':
687 {
688 int started = 0;
689 int reg;
690
691 func (stream, "{");
692
693 /* It would be nice if we could spot
694 ranges, and generate the rS-rE format: */
695 for (reg = 0; (reg < 8); reg++)
696 if ((given & (1 << reg)) != 0)
697 {
698 if (started)
699 func (stream, ", ");
700 started = 1;
701 func (stream, "%s", arm_regnames[reg]);
702 }
703
704 if (domasklr)
705 {
706 if (started)
707 func (stream, ", ");
708 started = 1;
709 func (stream, "lr");
710 }
711
712 if (domaskpc)
713 {
714 if (started)
715 func (stream, ", ");
716 func (stream, "pc");
717 }
718
719 func (stream, "}");
720 }
721 break;
722
723
724 case '0': case '1': case '2': case '3': case '4':
725 case '5': case '6': case '7': case '8': case '9':
726 {
727 int bitstart = *c++ - '0';
728 int bitend = 0;
729
730 while (*c >= '0' && *c <= '9')
731 bitstart = (bitstart * 10) + *c++ - '0';
732
733 switch (*c)
734 {
735 case '-':
736 {
737 long reg;
738
739 c++;
740 while (*c >= '0' && *c <= '9')
741 bitend = (bitend * 10) + *c++ - '0';
742 if (!bitend)
743 abort ();
744 reg = given >> bitstart;
745 reg &= (2 << (bitend - bitstart)) - 1;
746 switch (*c)
747 {
748 case 'r':
749 func (stream, "%s", arm_regnames[reg]);
750 break;
751
752 case 'd':
753 func (stream, "%d", reg);
754 break;
755
756 case 'H':
757 func (stream, "%d", reg << 1);
758 break;
759
760 case 'W':
761 func (stream, "%d", reg << 2);
762 break;
763
764 case 'a':
765 /* PC-relative address -- the bottom two
766 bits of the address are dropped
767 before the calculation. */
768 info->print_address_func
769 (((pc + 4) & ~3) + (reg << 2), info);
770 break;
771
772 case 'x':
773 func (stream, "0x%04x", reg);
774 break;
775
776 case 'I':
777 reg = ((reg ^ (1 << bitend)) - (1 << bitend));
778 func (stream, "%d", reg);
779 break;
780
781 case 'B':
782 reg = ((reg ^ (1 << bitend)) - (1 << bitend));
783 (*info->print_address_func)
784 (reg * 2 + pc + 4, info);
785 break;
786
787 default:
788 abort ();
789 }
790 }
791 break;
792
793 case '\'':
794 c++;
795 if ((given & (1 << bitstart)) != 0)
796 func (stream, "%c", *c);
797 break;
798
799 case '?':
800 ++c;
801 if ((given & (1 << bitstart)) != 0)
802 func (stream, "%c", *c++);
803 else
804 func (stream, "%c", *++c);
805 break;
806
807 default:
808 abort ();
809 }
810 }
811 break;
812
813 default:
814 abort ();
815 }
816 }
817 else
818 func (stream, "%c", *c);
819 }
820 }
821 return 2;
822 }
823 }
824
825 /* No match. */
826 abort ();
827 }
828
829 /* Parse an individual disassembler option. */
830 static void
831 parse_disassembler_option (option)
832 char * option;
833 {
834 if (option == NULL)
835 return;
836
837 if (strneq (option, "reg-names-", 10))
838 {
839 int i;
840
841 option += 10;
842
843 for (i = NUM_ARM_REGNAMES; i--;)
844 if (streq (option, regnames[i].name))
845 {
846 regname_selected = i;
847 break;
848 }
849
850 if (i < 0)
851 fprintf (stderr, _("Unrecognised register name set: %s\n"), option);
852 }
853 else if (streq (option, "force-thumb"))
854 force_thumb = 1;
855 else if (streq (option, "no-force-thumb"))
856 force_thumb = 0;
857 else
858 fprintf (stderr, _("Unrecognised disassembler option: %s\n"), option);
859
860 return;
861 }
862
863 /* Parse the string of disassembler options, spliting it at whitespaces. */
864 static void
865 parse_disassembler_options (options)
866 char * options;
867 {
868 char * space;
869
870 if (options == NULL)
871 return;
872
873 do
874 {
875 space = strchr (options, ' ');
876
877 if (space)
878 {
879 * space = '\0';
880 parse_disassembler_option (options);
881 * space = ' ';
882 options = space + 1;
883 }
884 else
885 parse_disassembler_option (options);
886 }
887 while (space);
888 }
889
890 /* NOTE: There are no checks in these routines that
891 the relevant number of data bytes exist. */
892 static int
893 print_insn (pc, info, little)
894 bfd_vma pc;
895 struct disassemble_info * info;
896 boolean little;
897 {
898 unsigned char b[4];
899 long given;
900 int status;
901 int is_thumb;
902
903 if (info->disassembler_options)
904 {
905 parse_disassembler_options (info->disassembler_options);
906
907 /* To avoid repeated parsing of these options, we remove them here. */
908 info->disassembler_options = NULL;
909 }
910
911 is_thumb = force_thumb;
912
913 if (!is_thumb && info->symbols != NULL)
914 {
915 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
916 {
917 coff_symbol_type * cs;
918
919 cs = coffsymbol (*info->symbols);
920 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT
921 || cs->native->u.syment.n_sclass == C_THUMBSTAT
922 || cs->native->u.syment.n_sclass == C_THUMBLABEL
923 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
924 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
925 }
926 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour)
927 {
928 elf_symbol_type * es;
929 unsigned int type;
930
931 es = *(elf_symbol_type **)(info->symbols);
932 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
933
934 is_thumb = (type == STT_ARM_TFUNC) || (type == STT_ARM_16BIT);
935 }
936 }
937
938 info->bytes_per_chunk = 4;
939 info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
940
941 if (little)
942 {
943 status = info->read_memory_func (pc, (bfd_byte *) &b[0], 4, info);
944 if (status != 0 && is_thumb)
945 {
946 info->bytes_per_chunk = 2;
947
948 status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
949 b[3] = b[2] = 0;
950 }
951
952 if (status != 0)
953 {
954 info->memory_error_func (status, pc, info);
955 return -1;
956 }
957
958 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
959 }
960 else
961 {
962 status = info->read_memory_func
963 (pc & ~ 0x3, (bfd_byte *) &b[0], 4, info);
964 if (status != 0)
965 {
966 info->memory_error_func (status, pc, info);
967 return -1;
968 }
969
970 if (is_thumb)
971 {
972 if (pc & 0x2)
973 {
974 given = (b[2] << 8) | b[3];
975
976 status = info->read_memory_func
977 ((pc + 4) & ~ 0x3, (bfd_byte *) b, 4, info);
978 if (status != 0)
979 {
980 info->memory_error_func (status, pc + 4, info);
981 return -1;
982 }
983
984 given |= (b[0] << 24) | (b[1] << 16);
985 }
986 else
987 given = (b[0] << 8) | b[1] | (b[2] << 24) | (b[3] << 16);
988 }
989 else
990 given = (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | (b[3]);
991 }
992
993 if (is_thumb)
994 status = print_insn_thumb (pc, info, given);
995 else
996 status = print_insn_arm (pc, info, given);
997
998 return status;
999 }
1000
1001 int
1002 print_insn_big_arm (pc, info)
1003 bfd_vma pc;
1004 struct disassemble_info * info;
1005 {
1006 return print_insn (pc, info, false);
1007 }
1008
1009 int
1010 print_insn_little_arm (pc, info)
1011 bfd_vma pc;
1012 struct disassemble_info * info;
1013 {
1014 return print_insn (pc, info, true);
1015 }
1016
1017 void
1018 print_arm_disassembler_options (FILE * stream)
1019 {
1020 int i;
1021
1022 fprintf (stream, _("\n\
1023 The following ARM specific disassembler options are supported for use with\n\
1024 the -M switch:\n"));
1025
1026 for (i = NUM_ARM_REGNAMES; i--;)
1027 fprintf (stream, " reg-names-%s %*c%s\n",
1028 regnames[i].name,
1029 14 - strlen (regnames[i].name), ' ',
1030 regnames[i].description);
1031
1032 fprintf (stream, " force-thumb Assume all insns are Thumb insns\n");
1033 fprintf (stream, " no-force-thumb Examine preceeding label to determine an insn's type\n\n");
1034 }