opcodes/arm-dis.c

   1 /* Instruction printing code for the ARM
   2    Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
   3    2004, 2005, 2006, 2007, 2008, 2009, 2010, 2012
   4    Free Software Foundation, Inc.
   5    Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
   6    Modification by James G. Smith (jsmith@cygnus.co.uk)
   7
   8    This file is part of libopcodes.
   9
  10    This library is free software; you can redistribute it and/or modify
  11    it under the terms of the GNU General Public License as published by
  12    the Free Software Foundation; either version 3 of the License, or
  13    (at your option) any later version.
  14
  15    It is distributed in the hope that it will be useful, but WITHOUT
  16    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  17    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  18    License for more details.
  19
  20    You should have received a copy of the GNU General Public License
  21    along with this program; if not, write to the Free Software
  22    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  23    MA 02110-1301, USA.  */
  24
  25 #include "sysdep.h"
  26
  27 #include "dis-asm.h"
  28 #include "opcode/arm.h"
  29 #include "opintl.h"
  30 #include "safe-ctype.h"
  31 #include "floatformat.h"
  32
  33 /* FIXME: This shouldn't be done here.  */
  34 #include "coff/internal.h"
  35 #include "libcoff.h"
  36 #include "elf-bfd.h"
  37 #include "elf/internal.h"
  38 #include "elf/arm.h"
  39
  40 /* FIXME: Belongs in global header.  */
  41 #ifndef strneq
  42 #define strneq(a,b,n)   (strncmp ((a), (b), (n)) == 0)
  43 #endif
  44
  45 #ifndef NUM_ELEM
  46 #define NUM_ELEM(a)     (sizeof (a) / sizeof (a)[0])
  47 #endif
  48
  49 /* Cached mapping symbol state.  */
  50 enum map_type
  51 {
  52   MAP_ARM,
  53   MAP_THUMB,
  54   MAP_DATA
  55 };
  56
  57 struct arm_private_data
  58 {
  59   /* The features to use when disassembling optional instructions.  */
  60   arm_feature_set features;
  61
  62   /* Whether any mapping symbols are present in the provided symbol
  63      table.  -1 if we do not know yet, otherwise 0 or 1.  */
  64   int has_mapping_symbols;
  65
  66   /* Track the last type (although this doesn't seem to be useful) */
  67   enum map_type last_type;
  68
  69   /* Tracking symbol table information */
  70   int last_mapping_sym;
  71   bfd_vma last_mapping_addr;
  72 };
  73
  74 struct opcode32
  75 {
  76   unsigned long arch;           /* Architecture defining this insn.  */
  77   unsigned long value;          /* If arch == 0 then value is a sentinel.  */
  78   unsigned long mask;           /* Recognise insn if (op & mask) == value.  */
  79   const char *  assembler;      /* How to disassemble this insn.  */
  80 };
  81
  82 struct opcode16
  83 {
  84   unsigned long arch;           /* Architecture defining this insn.  */
  85   unsigned short value, mask;   /* Recognise insn if (op & mask) == value.  */
  86   const char *assembler;        /* How to disassemble this insn.  */
  87 };
  88
  89 /* print_insn_coprocessor recognizes the following format control codes:
  90
  91    %%                   %
  92
  93    %c                   print condition code (always bits 28-31 in ARM mode)
  94    %q                   print shifter argument
  95    %u                   print condition code (unconditional in ARM mode,
  96                           UNPREDICTABLE if not AL in Thumb)
  97    %A                   print address for ldc/stc/ldf/stf instruction
  98    %B                   print vstm/vldm register list
  99    %I                   print cirrus signed shift immediate: bits 0..3|4..6
 100    %F                   print the COUNT field of a LFM/SFM instruction.
 101    %P                   print floating point precision in arithmetic insn
 102    %Q                   print floating point precision in ldf/stf insn
 103    %R                   print floating point rounding mode
 104
 105    %<bitfield>c         print as a condition code (for vsel)
 106    %<bitfield>r         print as an ARM register
 107    %<bitfield>R         as %<>r but r15 is UNPREDICTABLE
 108    %<bitfield>ru        as %<>r but each u register must be unique.
 109    %<bitfield>d         print the bitfield in decimal
 110    %<bitfield>k         print immediate for VFPv3 conversion instruction
 111    %<bitfield>x         print the bitfield in hex
 112    %<bitfield>X         print the bitfield as 1 hex digit without leading "0x"
 113    %<bitfield>f         print a floating point constant if >7 else a
 114                         floating point register
 115    %<bitfield>w         print as an iWMMXt width field - [bhwd]ss/us
 116    %<bitfield>g         print as an iWMMXt 64-bit register
 117    %<bitfield>G         print as an iWMMXt general purpose or control register
 118    %<bitfield>D         print as a NEON D register
 119    %<bitfield>Q         print as a NEON Q register
 120
 121    %y<code>             print a single precision VFP reg.
 122                           Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
 123    %z<code>             print a double precision VFP reg
 124                           Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
 125
 126    %<bitfield>'c        print specified char iff bitfield is all ones
 127    %<bitfield>`c        print specified char iff bitfield is all zeroes
 128    %<bitfield>?ab...    select from array of values in big endian order
 129
 130    %L                   print as an iWMMXt N/M width field.
 131    %Z                   print the Immediate of a WSHUFH instruction.
 132    %l                   like 'A' except use byte offsets for 'B' & 'H'
 133                         versions.
 134    %i                   print 5-bit immediate in bits 8,3..0
 135                         (print "32" when 0)
 136    %r                   print register offset address for wldt/wstr instruction.  */
 137
 138 enum opcode_sentinel_enum
 139 {
 140   SENTINEL_IWMMXT_START = 1,
 141   SENTINEL_IWMMXT_END,
 142   SENTINEL_GENERIC_START
 143 } opcode_sentinels;
 144
 145 #define UNDEFINED_INSTRUCTION      "\t\t; <UNDEFINED> instruction: %0-31x"
 146 #define UNPREDICTABLE_INSTRUCTION  "\t; <UNPREDICTABLE>"
 147
 148 /* Common coprocessor opcodes shared between Arm and Thumb-2.  */
 149
 150 static const struct opcode32 coprocessor_opcodes[] =
 151 {
 152   /* XScale instructions.  */
 153   {ARM_CEXT_XSCALE, 0x0e200010, 0x0fff0ff0, "mia%c\tacc0, %0-3r, %12-15r"},
 154   {ARM_CEXT_XSCALE, 0x0e280010, 0x0fff0ff0, "miaph%c\tacc0, %0-3r, %12-15r"},
 155   {ARM_CEXT_XSCALE, 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
 156   {ARM_CEXT_XSCALE, 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
 157   {ARM_CEXT_XSCALE, 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
 158
 159   /* Intel Wireless MMX technology instructions.  */
 160   { 0, SENTINEL_IWMMXT_START, 0, "" },
 161   {ARM_CEXT_IWMMXT, 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
 162   {ARM_CEXT_XSCALE, 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
 163   {ARM_CEXT_XSCALE, 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
 164   {ARM_CEXT_XSCALE, 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
 165   {ARM_CEXT_XSCALE, 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
 166   {ARM_CEXT_XSCALE, 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
 167   {ARM_CEXT_XSCALE, 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
 168   {ARM_CEXT_XSCALE, 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
 169   {ARM_CEXT_XSCALE, 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
 170   {ARM_CEXT_XSCALE, 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
 171   {ARM_CEXT_XSCALE, 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
 172   {ARM_CEXT_XSCALE, 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
 173   {ARM_CEXT_XSCALE, 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
 174   {ARM_CEXT_XSCALE, 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
 175   {ARM_CEXT_XSCALE, 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
 176   {ARM_CEXT_XSCALE, 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
 177   {ARM_CEXT_XSCALE, 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
 178   {ARM_CEXT_XSCALE, 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
 179   {ARM_CEXT_XSCALE, 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
 180   {ARM_CEXT_XSCALE, 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
 181   {ARM_CEXT_XSCALE, 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
 182   {ARM_CEXT_XSCALE, 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
 183   {ARM_CEXT_XSCALE, 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
 184   {ARM_CEXT_XSCALE, 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
 185   {ARM_CEXT_XSCALE, 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
 186   {ARM_CEXT_XSCALE, 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 187   {ARM_CEXT_XSCALE, 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 188   {ARM_CEXT_XSCALE, 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
 189   {ARM_CEXT_XSCALE, 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
 190   {ARM_CEXT_XSCALE, 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
 191   {ARM_CEXT_XSCALE, 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
 192   {ARM_CEXT_XSCALE, 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
 193   {ARM_CEXT_XSCALE, 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
 194   {ARM_CEXT_XSCALE, 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 195   {ARM_CEXT_XSCALE, 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
 196   {ARM_CEXT_XSCALE, 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
 197   {ARM_CEXT_XSCALE, 0x0e800120, 0x0f800ff0, "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
 198   {ARM_CEXT_XSCALE, 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 199   {ARM_CEXT_XSCALE, 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
 200   {ARM_CEXT_XSCALE, 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
 201   {ARM_CEXT_XSCALE, 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
 202   {ARM_CEXT_XSCALE, 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
 203   {ARM_CEXT_XSCALE, 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
 204   {ARM_CEXT_XSCALE, 0x0e8000a0, 0x0f800ff0, "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
 205   {ARM_CEXT_XSCALE, 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
 206   {ARM_CEXT_XSCALE, 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
 207   {ARM_CEXT_XSCALE, 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
 208   {ARM_CEXT_XSCALE, 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
 209   {ARM_CEXT_XSCALE, 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
 210   {ARM_CEXT_XSCALE, 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 211   {ARM_CEXT_XSCALE, 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
 212   {ARM_CEXT_XSCALE, 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
 213   {ARM_CEXT_XSCALE, 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
 214   {ARM_CEXT_XSCALE, 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
 215   {ARM_CEXT_XSCALE, 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
 216   {ARM_CEXT_XSCALE, 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
 217   {ARM_CEXT_XSCALE, 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
 218   {ARM_CEXT_XSCALE, 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
 219   {ARM_CEXT_XSCALE, 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
 220   {ARM_CEXT_XSCALE, 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
 221   {ARM_CEXT_XSCALE, 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
 222   {ARM_CEXT_XSCALE, 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
 223   {ARM_CEXT_XSCALE, 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
 224   {ARM_CEXT_XSCALE, 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
 225   {ARM_CEXT_XSCALE, 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
 226   {ARM_CEXT_XSCALE, 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
 227   {ARM_CEXT_XSCALE, 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
 228   {ARM_CEXT_XSCALE, 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 229   {ARM_CEXT_XSCALE, 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
 230   {ARM_CEXT_XSCALE, 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
 231   {ARM_CEXT_XSCALE, 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
 232   {ARM_CEXT_XSCALE, 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
 233   {ARM_CEXT_XSCALE, 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 234   {ARM_CEXT_XSCALE, 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 235   {ARM_CEXT_XSCALE, 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
 236   { 0, SENTINEL_IWMMXT_END, 0, "" },
 237
 238   /* Floating point coprocessor (FPA) instructions.  */
 239   {FPU_FPA_EXT_V1, 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 240   {FPU_FPA_EXT_V1, 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 241   {FPU_FPA_EXT_V1, 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 242   {FPU_FPA_EXT_V1, 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 243   {FPU_FPA_EXT_V1, 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 244   {FPU_FPA_EXT_V1, 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 245   {FPU_FPA_EXT_V1, 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
 246   {FPU_FPA_EXT_V1, 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
 247   {FPU_FPA_EXT_V1, 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 248   {FPU_FPA_EXT_V1, 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
 249   {FPU_FPA_EXT_V1, 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
 250   {FPU_FPA_EXT_V1, 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
 251   {FPU_FPA_EXT_V1, 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
 252   {FPU_FPA_EXT_V1, 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
 253   {FPU_FPA_EXT_V1, 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
 254   {FPU_FPA_EXT_V1, 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
 255   {FPU_FPA_EXT_V1, 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
 256   {FPU_FPA_EXT_V1, 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
 257   {FPU_FPA_EXT_V1, 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
 258   {FPU_FPA_EXT_V1, 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
 259   {FPU_FPA_EXT_V1, 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
 260   {FPU_FPA_EXT_V1, 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
 261   {FPU_FPA_EXT_V1, 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
 262   {FPU_FPA_EXT_V1, 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
 263   {FPU_FPA_EXT_V1, 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
 264   {FPU_FPA_EXT_V1, 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
 265   {FPU_FPA_EXT_V1, 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
 266   {FPU_FPA_EXT_V1, 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
 267   {FPU_FPA_EXT_V1, 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
 268   {FPU_FPA_EXT_V1, 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
 269   {FPU_FPA_EXT_V1, 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
 270   {FPU_FPA_EXT_V1, 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
 271   {FPU_FPA_EXT_V1, 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
 272   {FPU_FPA_EXT_V1, 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
 273   {FPU_FPA_EXT_V1, 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
 274   {FPU_FPA_EXT_V1, 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
 275   {FPU_FPA_EXT_V1, 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
 276   {FPU_FPA_EXT_V1, 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
 277   {FPU_FPA_EXT_V1, 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
 278   {FPU_FPA_EXT_V1, 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
 279   {FPU_FPA_EXT_V1, 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
 280   {FPU_FPA_EXT_V2, 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
 281   {FPU_FPA_EXT_V2, 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
 282
 283   /* Register load/store.  */
 284   {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
 285   {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
 286   {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
 287   {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
 288   {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
 289   {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
 290   {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
 291   {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
 292   {FPU_VFP_EXT_V1xD, 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
 293   {FPU_VFP_EXT_V1xD, 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
 294   {FPU_VFP_EXT_V1xD, 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
 295   {FPU_VFP_EXT_V1xD, 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
 296   {FPU_VFP_EXT_V1xD, 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
 297   {FPU_VFP_EXT_V1xD, 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
 298   {FPU_VFP_EXT_V1xD, 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
 299   {FPU_VFP_EXT_V1xD, 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
 300
 301   {FPU_VFP_EXT_V1xD, 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
 302   {FPU_VFP_EXT_V1xD, 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
 303   {FPU_VFP_EXT_V1xD, 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
 304   {FPU_VFP_EXT_V1xD, 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
 305
 306   /* Data transfer between ARM and NEON registers.  */
 307   {FPU_NEON_EXT_V1, 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
 308   {FPU_NEON_EXT_V1, 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
 309   {FPU_NEON_EXT_V1, 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
 310   {FPU_NEON_EXT_V1, 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
 311   {FPU_NEON_EXT_V1, 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
 312   {FPU_NEON_EXT_V1, 0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
 313   {FPU_NEON_EXT_V1, 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
 314   {FPU_NEON_EXT_V1, 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
 315   {FPU_NEON_EXT_V1, 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
 316   {FPU_NEON_EXT_V1, 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
 317   {FPU_NEON_EXT_V1, 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
 318   {FPU_NEON_EXT_V1, 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
 319   {FPU_NEON_EXT_V1, 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
 320   {FPU_NEON_EXT_V1, 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
 321   /* Half-precision conversion instructions.  */
 322   {FPU_VFP_EXT_FP16, 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
 323   {FPU_VFP_EXT_FP16, 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
 324
 325   /* Floating point coprocessor (VFP) instructions.  */
 326   {FPU_VFP_EXT_V1xD, 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
 327   {FPU_VFP_EXT_V1xD, 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
 328   {FPU_VFP_EXT_V1xD, 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
 329   {FPU_VFP_EXT_V1xD, 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
 330   {FPU_VFP_EXT_V1xD, 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
 331   {FPU_VFP_EXT_V1xD, 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
 332   {FPU_VFP_EXT_V1xD, 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
 333   {FPU_VFP_EXT_V1xD, 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
 334   {FPU_VFP_EXT_V1xD, 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
 335   {FPU_VFP_EXT_V1xD, 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
 336   {FPU_VFP_EXT_V1xD, 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
 337   {FPU_VFP_EXT_V1xD, 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
 338   {FPU_VFP_EXT_V1xD, 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
 339   {FPU_VFP_EXT_V1xD, 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
 340   {FPU_VFP_EXT_V1xD, 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
 341   {FPU_VFP_EXT_V1, 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
 342   {FPU_VFP_EXT_V1, 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
 343   {FPU_VFP_EXT_V1xD, 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
 344   {FPU_VFP_EXT_V1xD, 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
 345   {FPU_VFP_EXT_V1xD, 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
 346   {FPU_VFP_EXT_V1xD, 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
 347   {FPU_VFP_EXT_V1xD, 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
 348   {FPU_VFP_EXT_V1, 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
 349   {FPU_VFP_EXT_V1xD, 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
 350   {FPU_VFP_EXT_V1xD, 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
 351   {FPU_VFP_EXT_V1, 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
 352   {FPU_VFP_EXT_V1, 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
 353   {FPU_VFP_EXT_V1xD, 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
 354   {FPU_VFP_EXT_V1xD, 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
 355   {FPU_VFP_EXT_V1, 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
 356   {FPU_VFP_EXT_V1, 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
 357   {FPU_VFP_EXT_V1, 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
 358   {FPU_VFP_EXT_V1, 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
 359   {FPU_VFP_EXT_V1xD, 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
 360   {FPU_VFP_EXT_V1, 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
 361   {FPU_VFP_EXT_V1xD, 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
 362   {FPU_VFP_EXT_V1, 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
 363   {FPU_VFP_EXT_V3xD, 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
 364   {FPU_VFP_EXT_V3, 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
 365   {FPU_VFP_EXT_V1xD, 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
 366   {FPU_VFP_EXT_V1, 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
 367   {FPU_VFP_EXT_V3xD, 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
 368   {FPU_VFP_EXT_V3, 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
 369   {FPU_VFP_EXT_V1, 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
 370   {FPU_VFP_EXT_V3xD, 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19d"},
 371   {FPU_VFP_EXT_V3, 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19d"},
 372   {FPU_VFP_EXT_V2, 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
 373   {FPU_VFP_EXT_V2, 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
 374   {FPU_VFP_EXT_V2, 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
 375   {FPU_VFP_EXT_V1xD, 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
 376   {FPU_VFP_EXT_V1xD, 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
 377   {FPU_VFP_EXT_V1, 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
 378   {FPU_VFP_EXT_V1, 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
 379   {FPU_VFP_EXT_V1xD, 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
 380   {FPU_VFP_EXT_V1xD, 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
 381   {FPU_VFP_EXT_V1, 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
 382   {FPU_VFP_EXT_V1, 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
 383   {FPU_VFP_EXT_V1xD, 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
 384   {FPU_VFP_EXT_V1xD, 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
 385   {FPU_VFP_EXT_V1, 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
 386   {FPU_VFP_EXT_V1, 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
 387   {FPU_VFP_EXT_V1xD, 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
 388   {FPU_VFP_EXT_V1xD, 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
 389   {FPU_VFP_EXT_V1, 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
 390   {FPU_VFP_EXT_V1, 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
 391   {FPU_VFP_EXT_V1xD, 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
 392   {FPU_VFP_EXT_V1, 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
 393
 394   /* Cirrus coprocessor instructions.  */
 395   {ARM_CEXT_MAVERICK, 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
 396   {ARM_CEXT_MAVERICK, 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
 397   {ARM_CEXT_MAVERICK, 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
 398   {ARM_CEXT_MAVERICK, 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
 399   {ARM_CEXT_MAVERICK, 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
 400   {ARM_CEXT_MAVERICK, 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
 401   {ARM_CEXT_MAVERICK, 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
 402   {ARM_CEXT_MAVERICK, 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
 403   {ARM_CEXT_MAVERICK, 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
 404   {ARM_CEXT_MAVERICK, 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
 405   {ARM_CEXT_MAVERICK, 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
 406   {ARM_CEXT_MAVERICK, 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
 407   {ARM_CEXT_MAVERICK, 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
 408   {ARM_CEXT_MAVERICK, 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
 409   {ARM_CEXT_MAVERICK, 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
 410   {ARM_CEXT_MAVERICK, 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
 411   {ARM_CEXT_MAVERICK, 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
 412   {ARM_CEXT_MAVERICK, 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
 413   {ARM_CEXT_MAVERICK, 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
 414   {ARM_CEXT_MAVERICK, 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
 415   {ARM_CEXT_MAVERICK, 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
 416   {ARM_CEXT_MAVERICK, 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
 417   {ARM_CEXT_MAVERICK, 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
 418   {ARM_CEXT_MAVERICK, 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
 419   {ARM_CEXT_MAVERICK, 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
 420   {ARM_CEXT_MAVERICK, 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
 421   {ARM_CEXT_MAVERICK, 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
 422   {ARM_CEXT_MAVERICK, 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
 423   {ARM_CEXT_MAVERICK, 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
 424   {ARM_CEXT_MAVERICK, 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
 425   {ARM_CEXT_MAVERICK, 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
 426   {ARM_CEXT_MAVERICK, 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
 427   {ARM_CEXT_MAVERICK, 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
 428   {ARM_CEXT_MAVERICK, 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
 429   {ARM_CEXT_MAVERICK, 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
 430   {ARM_CEXT_MAVERICK, 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
 431   {ARM_CEXT_MAVERICK, 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
 432   {ARM_CEXT_MAVERICK, 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
 433   {ARM_CEXT_MAVERICK, 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
 434   {ARM_CEXT_MAVERICK, 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
 435   {ARM_CEXT_MAVERICK, 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
 436   {ARM_CEXT_MAVERICK, 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
 437   {ARM_CEXT_MAVERICK, 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
 438   {ARM_CEXT_MAVERICK, 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
 439   {ARM_CEXT_MAVERICK, 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
 440   {ARM_CEXT_MAVERICK, 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
 441   {ARM_CEXT_MAVERICK, 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
 442   {ARM_CEXT_MAVERICK, 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
 443   {ARM_CEXT_MAVERICK, 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
 444   {ARM_CEXT_MAVERICK, 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
 445   {ARM_CEXT_MAVERICK, 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
 446   {ARM_CEXT_MAVERICK, 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
 447   {ARM_CEXT_MAVERICK, 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
 448   {ARM_CEXT_MAVERICK, 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
 449   {ARM_CEXT_MAVERICK, 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
 450   {ARM_CEXT_MAVERICK, 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
 451   {ARM_CEXT_MAVERICK, 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
 452   {ARM_CEXT_MAVERICK, 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
 453   {ARM_CEXT_MAVERICK, 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
 454   {ARM_CEXT_MAVERICK, 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
 455   {ARM_CEXT_MAVERICK, 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
 456   {ARM_CEXT_MAVERICK, 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
 457   {ARM_CEXT_MAVERICK, 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
 458   {ARM_CEXT_MAVERICK, 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
 459   {ARM_CEXT_MAVERICK, 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
 460   {ARM_CEXT_MAVERICK, 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
 461   {ARM_CEXT_MAVERICK, 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
 462   {ARM_CEXT_MAVERICK, 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
 463   {ARM_CEXT_MAVERICK, 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
 464   {ARM_CEXT_MAVERICK, 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
 465   {ARM_CEXT_MAVERICK, 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
 466   {ARM_CEXT_MAVERICK, 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
 467   {ARM_CEXT_MAVERICK, 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 468   {ARM_CEXT_MAVERICK, 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
 469   {ARM_CEXT_MAVERICK, 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 470   {ARM_CEXT_MAVERICK, 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
 471   {ARM_CEXT_MAVERICK, 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 472   {ARM_CEXT_MAVERICK, 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
 473   {ARM_CEXT_MAVERICK, 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 474   {ARM_CEXT_MAVERICK, 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 475   {ARM_CEXT_MAVERICK, 0x0e000600, 0x0ff00f10, "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 476   {ARM_CEXT_MAVERICK, 0x0e100600, 0x0ff00f10, "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 477   {ARM_CEXT_MAVERICK, 0x0e200600, 0x0ff00f10, "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
 478   {ARM_CEXT_MAVERICK, 0x0e300600, 0x0ff00f10, "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
 479
 480   /* VFP Fused multiply add instructions.  */
 481   {FPU_VFP_EXT_FMA, 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
 482   {FPU_VFP_EXT_FMA, 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
 483   {FPU_VFP_EXT_FMA, 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
 484   {FPU_VFP_EXT_FMA, 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
 485   {FPU_VFP_EXT_FMA, 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
 486   {FPU_VFP_EXT_FMA, 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
 487   {FPU_VFP_EXT_FMA, 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
 488   {FPU_VFP_EXT_FMA, 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
 489
 490   /* FP v5.  */
 491   {FPU_VFP_EXT_ARMV8, 0xfe000a00, 0xff800f00, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
 492   {FPU_VFP_EXT_ARMV8, 0xfe000b00, 0xff800f00, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
 493   {FPU_VFP_EXT_ARMV8, 0xfe800a00, 0xffb00f40, "vmaxnm%u.f32\t%y1, %y2, %y0"},
 494   {FPU_VFP_EXT_ARMV8, 0xfe800b00, 0xffb00f40, "vmaxnm%u.f64\t%z1, %z2, %z0"},
 495   {FPU_VFP_EXT_ARMV8, 0xfe800a40, 0xffb00f40, "vminnm%u.f32\t%y1, %y2, %y0"},
 496   {FPU_VFP_EXT_ARMV8, 0xfe800b40, 0xffb00f40, "vminnm%u.f64\t%z1, %z2, %z0"},
 497   {FPU_VFP_EXT_ARMV8, 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
 498   {FPU_VFP_EXT_ARMV8, 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
 499
 500   /* Generic coprocessor instructions.  */
 501   { 0, SENTINEL_GENERIC_START, 0, "" },
 502   {ARM_EXT_V5E, 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
 503   {ARM_EXT_V5E, 0x0c500000, 0x0ff00000, "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
 504   {ARM_EXT_V2, 0x0e000000, 0x0f000010, "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
 505   {ARM_EXT_V2, 0x0e10f010, 0x0f10f010, "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
 506   {ARM_EXT_V2, 0x0e100010, 0x0f100010, "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
 507   {ARM_EXT_V2, 0x0e000010, 0x0f100010, "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
 508   {ARM_EXT_V2, 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
 509   {ARM_EXT_V2, 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
 510
 511   /* V6 coprocessor instructions.  */
 512   {ARM_EXT_V6, 0xfc500000, 0xfff00000, "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
 513   {ARM_EXT_V6, 0xfc400000, 0xfff00000, "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
 514
 515   /* V5 coprocessor instructions.  */
 516   {ARM_EXT_V5, 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
 517   {ARM_EXT_V5, 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
 518   {ARM_EXT_V5, 0xfe000000, 0xff000010, "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
 519   {ARM_EXT_V5, 0xfe000010, 0xff100010, "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
 520   {ARM_EXT_V5, 0xfe100010, 0xff100010, "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
 521
 522   {0, 0, 0, 0}
 523 };
 524
 525 /* Neon opcode table:  This does not encode the top byte -- that is
 526    checked by the print_insn_neon routine, as it depends on whether we are
 527    doing thumb32 or arm32 disassembly.  */
 528
 529 /* print_insn_neon recognizes the following format control codes:
 530
 531    %%                   %
 532
 533    %c                   print condition code
 534    %u                   print condition code (unconditional in ARM mode,
 535                           UNPREDICTABLE if not AL in Thumb)
 536    %A                   print v{st,ld}[1234] operands
 537    %B                   print v{st,ld}[1234] any one operands
 538    %C                   print v{st,ld}[1234] single->all operands
 539    %D                   print scalar
 540    %E                   print vmov, vmvn, vorr, vbic encoded constant
 541    %F                   print vtbl,vtbx register list
 542
 543    %<bitfield>r         print as an ARM register
 544    %<bitfield>d         print the bitfield in decimal
 545    %<bitfield>e         print the 2^N - bitfield in decimal
 546    %<bitfield>D         print as a NEON D register
 547    %<bitfield>Q         print as a NEON Q register
 548    %<bitfield>R         print as a NEON D or Q register
 549    %<bitfield>Sn        print byte scaled width limited by n
 550    %<bitfield>Tn        print short scaled width limited by n
 551    %<bitfield>Un        print long scaled width limited by n
 552
 553    %<bitfield>'c        print specified char iff bitfield is all ones
 554    %<bitfield>`c        print specified char iff bitfield is all zeroes
 555    %<bitfield>?ab...    select from array of values in big endian order.  */
 556
 557 static const struct opcode32 neon_opcodes[] =
 558 {
 559   /* Extract.  */
 560   {FPU_NEON_EXT_V1, 0xf2b00840, 0xffb00850, "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
 561   {FPU_NEON_EXT_V1, 0xf2b00000, 0xffb00810, "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
 562
 563   /* Move data element to all lanes.  */
 564   {FPU_NEON_EXT_V1, 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
 565   {FPU_NEON_EXT_V1, 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
 566   {FPU_NEON_EXT_V1, 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
 567
 568   /* Table lookup.  */
 569   {FPU_NEON_EXT_V1, 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
 570   {FPU_NEON_EXT_V1, 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
 571
 572   /* Half-precision conversions.  */
 573   {FPU_VFP_EXT_FP16, 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
 574   {FPU_VFP_EXT_FP16, 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
 575
 576   /* NEON fused multiply add instructions.  */
 577   {FPU_NEON_EXT_FMA, 0xf2000c10, 0xffa00f10, "vfma%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
 578   {FPU_NEON_EXT_FMA, 0xf2200c10, 0xffa00f10, "vfms%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
 579
 580   /* Two registers, miscellaneous.  */
 581   {FPU_NEON_EXT_ARMV8, 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
 582   {FPU_NEON_EXT_V1, 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
 583   {FPU_NEON_EXT_V1, 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
 584   {FPU_NEON_EXT_V1, 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
 585   {FPU_NEON_EXT_V1, 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
 586   {FPU_NEON_EXT_V1, 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
 587   {FPU_NEON_EXT_V1, 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
 588   {FPU_NEON_EXT_V1, 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
 589   {FPU_NEON_EXT_V1, 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
 590   {FPU_NEON_EXT_V1, 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
 591   {FPU_NEON_EXT_V1, 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
 592   {FPU_NEON_EXT_V1, 0xf3b20300, 0xffb30fd0, "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
 593   {FPU_NEON_EXT_V1, 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
 594   {FPU_NEON_EXT_V1, 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
 595   {FPU_NEON_EXT_V1, 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
 596   {FPU_NEON_EXT_V1, 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
 597   {FPU_NEON_EXT_V1, 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
 598   {FPU_NEON_EXT_V1, 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
 599   {FPU_NEON_EXT_V1, 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
 600   {FPU_NEON_EXT_V1, 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
 601   {FPU_NEON_EXT_V1, 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
 602   {FPU_NEON_EXT_V1, 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
 603   {FPU_NEON_EXT_V1, 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
 604   {FPU_NEON_EXT_V1, 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
 605   {FPU_NEON_EXT_V1, 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
 606   {FPU_NEON_EXT_V1, 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
 607   {FPU_NEON_EXT_V1, 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
 608   {FPU_NEON_EXT_V1, 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
 609   {FPU_NEON_EXT_V1, 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
 610   {FPU_NEON_EXT_V1, 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
 611   {FPU_NEON_EXT_V1, 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
 612   {FPU_NEON_EXT_V1, 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
 613   {FPU_NEON_EXT_V1, 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
 614   {FPU_NEON_EXT_V1, 0xf3b30600, 0xffb30e10, "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
 615
 616   /* Three registers of the same length.  */
 617   {FPU_NEON_EXT_ARMV8, 0xf3000f10, 0xffa00f10, "vmaxnm%u.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
 618   {FPU_NEON_EXT_ARMV8, 0xf3200f10, 0xffa00f10, "vminnm%u.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
 619   {FPU_NEON_EXT_V1, 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
 620   {FPU_NEON_EXT_V1, 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
 621   {FPU_NEON_EXT_V1, 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
 622   {FPU_NEON_EXT_V1, 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
 623   {FPU_NEON_EXT_V1, 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
 624   {FPU_NEON_EXT_V1, 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
 625   {FPU_NEON_EXT_V1, 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
 626   {FPU_NEON_EXT_V1, 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
 627   {FPU_NEON_EXT_V1, 0xf2000d00, 0xffa00f10, "vadd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
 628   {FPU_NEON_EXT_V1, 0xf2000d10, 0xffa00f10, "vmla%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
 629   {FPU_NEON_EXT_V1, 0xf2000e00, 0xffa00f10, "vceq%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
 630   {FPU_NEON_EXT_V1, 0xf2000f00, 0xffa00f10, "vmax%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
 631   {FPU_NEON_EXT_V1, 0xf2000f10, 0xffa00f10, "vrecps%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
 632   {FPU_NEON_EXT_V1, 0xf2200d00, 0xffa00f10, "vsub%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
 633   {FPU_NEON_EXT_V1, 0xf2200d10, 0xffa00f10, "vmls%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
 634   {FPU_NEON_EXT_V1, 0xf2200f00, 0xffa00f10, "vmin%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
 635   {FPU_NEON_EXT_V1, 0xf2200f10, 0xffa00f10, "vrsqrts%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
 636   {FPU_NEON_EXT_V1, 0xf3000d00, 0xffa00f10, "vpadd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
 637   {FPU_NEON_EXT_V1, 0xf3000d10, 0xffa00f10, "vmul%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
 638   {FPU_NEON_EXT_V1, 0xf3000e00, 0xffa00f10, "vcge%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
 639   {FPU_NEON_EXT_V1, 0xf3000e10, 0xffa00f10, "vacge%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
 640   {FPU_NEON_EXT_V1, 0xf3000f00, 0xffa00f10, "vpmax%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
 641   {FPU_NEON_EXT_V1, 0xf3200d00, 0xffa00f10, "vabd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
 642   {FPU_NEON_EXT_V1, 0xf3200e00, 0xffa00f10, "vcgt%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
 643   {FPU_NEON_EXT_V1, 0xf3200e10, 0xffa00f10, "vacgt%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
 644   {FPU_NEON_EXT_V1, 0xf3200f00, 0xffa00f10, "vpmin%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
 645   {FPU_NEON_EXT_V1, 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
 646   {FPU_NEON_EXT_V1, 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
 647   {FPU_NEON_EXT_V1, 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
 648   {FPU_NEON_EXT_V1, 0xf2000b00, 0xff800f10, "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
 649   {FPU_NEON_EXT_V1, 0xf2000b10, 0xff800f10, "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
 650   {FPU_NEON_EXT_V1, 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
 651   {FPU_NEON_EXT_V1, 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
 652   {FPU_NEON_EXT_V1, 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
 653   {FPU_NEON_EXT_V1, 0xf3000b00, 0xff800f10, "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
 654   {FPU_NEON_EXT_V1, 0xf2000000, 0xfe800f10, "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
 655   {FPU_NEON_EXT_V1, 0xf2000010, 0xfe800f10, "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
 656   {FPU_NEON_EXT_V1, 0xf2000100, 0xfe800f10, "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
 657   {FPU_NEON_EXT_V1, 0xf2000200, 0xfe800f10, "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
 658   {FPU_NEON_EXT_V1, 0xf2000210, 0xfe800f10, "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
 659   {FPU_NEON_EXT_V1, 0xf2000300, 0xfe800f10, "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
 660   {FPU_NEON_EXT_V1, 0xf2000310, 0xfe800f10, "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
 661   {FPU_NEON_EXT_V1, 0xf2000400, 0xfe800f10, "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
 662   {FPU_NEON_EXT_V1, 0xf2000410, 0xfe800f10, "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
 663   {FPU_NEON_EXT_V1, 0xf2000500, 0xfe800f10, "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
 664   {FPU_NEON_EXT_V1, 0xf2000510, 0xfe800f10, "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
 665   {FPU_NEON_EXT_V1, 0xf2000600, 0xfe800f10, "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
 666   {FPU_NEON_EXT_V1, 0xf2000610, 0xfe800f10, "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
 667   {FPU_NEON_EXT_V1, 0xf2000700, 0xfe800f10, "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
 668   {FPU_NEON_EXT_V1, 0xf2000710, 0xfe800f10, "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
 669   {FPU_NEON_EXT_V1, 0xf2000910, 0xfe800f10, "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
 670   {FPU_NEON_EXT_V1, 0xf2000a00, 0xfe800f10, "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
 671   {FPU_NEON_EXT_V1, 0xf2000a10, 0xfe800f10, "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
 672
 673   /* One register and an immediate value.  */
 674   {FPU_NEON_EXT_V1, 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
 675   {FPU_NEON_EXT_V1, 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
 676   {FPU_NEON_EXT_V1, 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
 677   {FPU_NEON_EXT_V1, 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
 678   {FPU_NEON_EXT_V1, 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
 679   {FPU_NEON_EXT_V1, 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
 680   {FPU_NEON_EXT_V1, 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
 681   {FPU_NEON_EXT_V1, 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
 682   {FPU_NEON_EXT_V1, 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
 683   {FPU_NEON_EXT_V1, 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
 684   {FPU_NEON_EXT_V1, 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
 685   {FPU_NEON_EXT_V1, 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
 686   {FPU_NEON_EXT_V1, 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
 687
 688   /* Two registers and a shift amount.  */
 689   {FPU_NEON_EXT_V1, 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
 690   {FPU_NEON_EXT_V1, 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
 691   {FPU_NEON_EXT_V1, 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
 692   {FPU_NEON_EXT_V1, 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
 693   {FPU_NEON_EXT_V1, 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
 694   {FPU_NEON_EXT_V1, 0xf2880950, 0xfeb80fd0, "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
 695   {FPU_NEON_EXT_V1, 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22D, %0-3,5Q, #%16-18d"},
 696   {FPU_NEON_EXT_V1, 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
 697   {FPU_NEON_EXT_V1, 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
 698   {FPU_NEON_EXT_V1, 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
 699   {FPU_NEON_EXT_V1, 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
 700   {FPU_NEON_EXT_V1, 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
 701   {FPU_NEON_EXT_V1, 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
 702   {FPU_NEON_EXT_V1, 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
 703   {FPU_NEON_EXT_V1, 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
 704   {FPU_NEON_EXT_V1, 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
 705   {FPU_NEON_EXT_V1, 0xf2900950, 0xfeb00fd0, "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
 706   {FPU_NEON_EXT_V1, 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-19d"},
 707   {FPU_NEON_EXT_V1, 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
 708   {FPU_NEON_EXT_V1, 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
 709   {FPU_NEON_EXT_V1, 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
 710   {FPU_NEON_EXT_V1, 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
 711   {FPU_NEON_EXT_V1, 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
 712   {FPU_NEON_EXT_V1, 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
 713   {FPU_NEON_EXT_V1, 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
 714   {FPU_NEON_EXT_V1, 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
 715   {FPU_NEON_EXT_V1, 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
 716   {FPU_NEON_EXT_V1, 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
 717   {FPU_NEON_EXT_V1, 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
 718   {FPU_NEON_EXT_V1, 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-20d"},
 719   {FPU_NEON_EXT_V1, 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
 720   {FPU_NEON_EXT_V1, 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
 721   {FPU_NEON_EXT_V1, 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
 722   {FPU_NEON_EXT_V1, 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
 723   {FPU_NEON_EXT_V1, 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
 724   {FPU_NEON_EXT_V1, 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
 725   {FPU_NEON_EXT_V1, 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
 726   {FPU_NEON_EXT_V1, 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
 727   {FPU_NEON_EXT_V1, 0xf2a00950, 0xfea00fd0, "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
 728   {FPU_NEON_EXT_V1, 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
 729   {FPU_NEON_EXT_V1, 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
 730   {FPU_NEON_EXT_V1, 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
 731   {FPU_NEON_EXT_V1, 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
 732   {FPU_NEON_EXT_V1, 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
 733   {FPU_NEON_EXT_V1, 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
 734   {FPU_NEON_EXT_V1, 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
 735   {FPU_NEON_EXT_V1, 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
 736   {FPU_NEON_EXT_V1, 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
 737   {FPU_NEON_EXT_V1, 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
 738   {FPU_NEON_EXT_V1, 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
 739   {FPU_NEON_EXT_V1, 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
 740   {FPU_NEON_EXT_V1, 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
 741   {FPU_NEON_EXT_V1, 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
 742   {FPU_NEON_EXT_V1, 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
 743   {FPU_NEON_EXT_V1, 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
 744   {FPU_NEON_EXT_V1, 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
 745   {FPU_NEON_EXT_V1, 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
 746   {FPU_NEON_EXT_V1, 0xf2a00e10, 0xfea00e90, "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
 747
 748   /* Three registers of different lengths.  */
 749   {FPU_NEON_EXT_V1, 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
 750   {FPU_NEON_EXT_V1, 0xf2800400, 0xff800f50, "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
 751   {FPU_NEON_EXT_V1, 0xf2800600, 0xff800f50, "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
 752   {FPU_NEON_EXT_V1, 0xf2800900, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
 753   {FPU_NEON_EXT_V1, 0xf2800b00, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
 754   {FPU_NEON_EXT_V1, 0xf2800d00, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
 755   {FPU_NEON_EXT_V1, 0xf3800400, 0xff800f50, "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
 756   {FPU_NEON_EXT_V1, 0xf3800600, 0xff800f50, "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
 757   {FPU_NEON_EXT_V1, 0xf2800000, 0xfe800f50, "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
 758   {FPU_NEON_EXT_V1, 0xf2800100, 0xfe800f50, "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
 759   {FPU_NEON_EXT_V1, 0xf2800200, 0xfe800f50, "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
 760   {FPU_NEON_EXT_V1, 0xf2800300, 0xfe800f50, "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
 761   {FPU_NEON_EXT_V1, 0xf2800500, 0xfe800f50, "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
 762   {FPU_NEON_EXT_V1, 0xf2800700, 0xfe800f50, "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
 763   {FPU_NEON_EXT_V1, 0xf2800800, 0xfe800f50, "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
 764   {FPU_NEON_EXT_V1, 0xf2800a00, 0xfe800f50, "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
 765   {FPU_NEON_EXT_V1, 0xf2800c00, 0xfe800f50, "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
 766
 767   /* Two registers and a scalar.  */
 768   {FPU_NEON_EXT_V1, 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
 769   {FPU_NEON_EXT_V1, 0xf2800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
 770   {FPU_NEON_EXT_V1, 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
 771   {FPU_NEON_EXT_V1, 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
 772   {FPU_NEON_EXT_V1, 0xf2800540, 0xff800f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
 773   {FPU_NEON_EXT_V1, 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
 774   {FPU_NEON_EXT_V1, 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
 775   {FPU_NEON_EXT_V1, 0xf2800940, 0xff800f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
 776   {FPU_NEON_EXT_V1, 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
 777   {FPU_NEON_EXT_V1, 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
 778   {FPU_NEON_EXT_V1, 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
 779   {FPU_NEON_EXT_V1, 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
 780   {FPU_NEON_EXT_V1, 0xf3800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
 781   {FPU_NEON_EXT_V1, 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
 782   {FPU_NEON_EXT_V1, 0xf3800540, 0xff800f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
 783   {FPU_NEON_EXT_V1, 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
 784   {FPU_NEON_EXT_V1, 0xf3800940, 0xff800f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
 785   {FPU_NEON_EXT_V1, 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
 786   {FPU_NEON_EXT_V1, 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
 787   {FPU_NEON_EXT_V1, 0xf2800240, 0xfe800f50, "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
 788   {FPU_NEON_EXT_V1, 0xf2800640, 0xfe800f50, "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
 789   {FPU_NEON_EXT_V1, 0xf2800a40, 0xfe800f50, "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
 790
 791   /* Element and structure load/store.  */
 792   {FPU_NEON_EXT_V1, 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
 793   {FPU_NEON_EXT_V1, 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
 794   {FPU_NEON_EXT_V1, 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
 795   {FPU_NEON_EXT_V1, 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
 796   {FPU_NEON_EXT_V1, 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
 797   {FPU_NEON_EXT_V1, 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
 798   {FPU_NEON_EXT_V1, 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
 799   {FPU_NEON_EXT_V1, 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
 800   {FPU_NEON_EXT_V1, 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
 801   {FPU_NEON_EXT_V1, 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
 802   {FPU_NEON_EXT_V1, 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
 803   {FPU_NEON_EXT_V1, 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
 804   {FPU_NEON_EXT_V1, 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
 805   {FPU_NEON_EXT_V1, 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
 806   {FPU_NEON_EXT_V1, 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
 807   {FPU_NEON_EXT_V1, 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
 808   {FPU_NEON_EXT_V1, 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
 809   {FPU_NEON_EXT_V1, 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
 810   {FPU_NEON_EXT_V1, 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
 811
 812   {0,0 ,0, 0}
 813 };
 814
 815 /* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb.  All three are partially
 816    ordered: they must be searched linearly from the top to obtain a correct
 817    match.  */
 818
 819 /* print_insn_arm recognizes the following format control codes:
 820
 821    %%                   %
 822
 823    %a                   print address for ldr/str instruction
 824    %s                   print address for ldr/str halfword/signextend instruction
 825    %S                   like %s but allow UNPREDICTABLE addressing
 826    %b                   print branch destination
 827    %c                   print condition code (always bits 28-31)
 828    %m                   print register mask for ldm/stm instruction
 829    %o                   print operand2 (immediate or register + shift)
 830    %p                   print 'p' iff bits 12-15 are 15
 831    %t                   print 't' iff bit 21 set and bit 24 clear
 832    %B                   print arm BLX(1) destination
 833    %C                   print the PSR sub type.
 834    %U                   print barrier type.
 835    %P                   print address for pli instruction.
 836
 837    %<bitfield>r         print as an ARM register
 838    %<bitfield>T         print as an ARM register + 1
 839    %<bitfield>R         as %r but r15 is UNPREDICTABLE
 840    %<bitfield>{r|R}u    as %{r|R} but if matches the other %u field then is UNPREDICTABLE
 841    %<bitfield>{r|R}U    as %{r|R} but if matches the other %U field then is UNPREDICTABLE
 842    %<bitfield>d         print the bitfield in decimal
 843    %<bitfield>W         print the bitfield plus one in decimal
 844    %<bitfield>x         print the bitfield in hex
 845    %<bitfield>X         print the bitfield as 1 hex digit without leading "0x"
 846
 847    %<bitfield>'c        print specified char iff bitfield is all ones
 848    %<bitfield>`c        print specified char iff bitfield is all zeroes
 849    %<bitfield>?ab...    select from array of values in big endian order
 850
 851    %e                   print arm SMI operand (bits 0..7,8..19).
 852    %E                   print the LSB and WIDTH fields of a BFI or BFC instruction.
 853    %V                   print the 16-bit immediate field of a MOVT or MOVW instruction.
 854    %R                   print the SPSR/CPSR or banked register of an MRS.  */
 855
 856 static const struct opcode32 arm_opcodes[] =
 857 {
 858   /* ARM instructions.  */
 859   {ARM_EXT_V1, 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
 860   {ARM_EXT_V4T | ARM_EXT_V5, 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
 861   {ARM_EXT_V2, 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
 862   {ARM_EXT_V2, 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
 863   {ARM_EXT_V2S, 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
 864   {ARM_EXT_V3M, 0x00800090, 0x0fa000f0, "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
 865   {ARM_EXT_V3M, 0x00a00090, 0x0fa000f0, "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
 866
 867   /* V8 instructions.  */
 868   {ARM_EXT_V8,   0x0320f005, 0x0fffffff, "sevl"},
 869   {ARM_EXT_V8,   0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
 870   {ARM_EXT_V8,   0x01800e90, 0x0ff00ff0, "strlex%c\t%12-15r, %0-3r, [%16-19R]"},
 871   {ARM_EXT_V8,   0x01900e9f, 0x0ff00fff, "ldraex%c\t%12-15r, [%16-19R]"},
 872   {ARM_EXT_V8,   0x01a00e90, 0x0ff00ff0, "strlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
 873   {ARM_EXT_V8,   0x01b00e9f, 0x0ff00fff, "ldraexd%c\t%12-15r, %12-15T, [%16-19R]"},
 874   {ARM_EXT_V8,   0x01c00e90, 0x0ff00ff0, "strlexb%c\t%12-15r, %0-3r, [%16-19R]"},
 875   {ARM_EXT_V8,   0x01d00e9f, 0x0ff00fff, "ldraexb%c\t%12-15r, [%16-19R]"},
 876   {ARM_EXT_V8,   0x01e00e90, 0x0ff00ff0, "strlexh%c\t%12-15r, %0-3r, [%16-19R]"},
 877   {ARM_EXT_V8,   0x01f00e9f, 0x0ff00fff, "ldraexh%c\t%12-15r, [%16-19R]"},
 878   {ARM_EXT_V8,   0x0180fc90, 0x0ff0fff0, "strl%c\t%0-3r, [%16-19R]"},
 879   {ARM_EXT_V8,   0x01900c9f, 0x0ff00fff, "ldra%c\t%12-15r, [%16-19R]"},
 880   {ARM_EXT_V8,   0x01c0fc90, 0x0ff0fff0, "strlb%c\t%0-3r, [%16-19R]"},
 881   {ARM_EXT_V8,   0x01d00c9f, 0x0ff00fff, "ldrab%c\t%12-15r, [%16-19R]"},
 882   {ARM_EXT_V8,   0x01e0fc90, 0x0ff0fff0, "strlh%c\t%0-3r, [%16-19R]"},
 883   {ARM_EXT_V8,   0x01f00c9f, 0x0ff00fff, "ldraexh%c\t%12-15r, [%16-19R]"},
 884
 885   /* Virtualization Extension instructions.  */
 886   {ARM_EXT_VIRT, 0x0160006e, 0x0fffffff, "eret%c"},
 887   {ARM_EXT_VIRT, 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
 888
 889   /* Integer Divide Extension instructions.  */
 890   {ARM_EXT_ADIV, 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
 891   {ARM_EXT_ADIV, 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
 892
 893   /* MP Extension instructions.  */
 894   {ARM_EXT_MP, 0xf410f000, 0xfc70f000, "pldw\t%a"},
 895
 896   /* V7 instructions.  */
 897   {ARM_EXT_V7, 0xf450f000, 0xfd70f000, "pli\t%P"},
 898   {ARM_EXT_V7, 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
 899   {ARM_EXT_V8, 0xf57ff051, 0xfffffff3, "dmb\t%U"},
 900   {ARM_EXT_V8, 0xf57ff041, 0xfffffff3, "dsb\t%U"},
 901   {ARM_EXT_V7, 0xf57ff050, 0xfffffff0, "dmb\t%U"},
 902   {ARM_EXT_V7, 0xf57ff040, 0xfffffff0, "dsb\t%U"},
 903   {ARM_EXT_V7, 0xf57ff060, 0xfffffff0, "isb\t%U"},
 904
 905   /* ARM V6T2 instructions.  */
 906   {ARM_EXT_V6T2, 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
 907   {ARM_EXT_V6T2, 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
 908   {ARM_EXT_V6T2, 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
 909   {ARM_EXT_V6T2, 0x006000b0, 0x0f7000f0, "strht%c\t%12-15R, %S"},
 910
 911   {ARM_EXT_V6T2, 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
 912   {ARM_EXT_V6T2, 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
 913
 914   {ARM_EXT_V6T2, 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
 915   {ARM_EXT_V6T2, 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
 916   {ARM_EXT_V6T2, 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
 917   {ARM_EXT_V6T2, 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
 918
 919   /* ARM Security extension instructions.  */
 920   {ARM_EXT_SEC, 0x01600070, 0x0ff000f0, "smc%c\t%e"},
 921
 922   /* ARM V6K instructions.  */
 923   {ARM_EXT_V6K, 0xf57ff01f, 0xffffffff, "clrex"},
 924   {ARM_EXT_V6K, 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
 925   {ARM_EXT_V6K, 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
 926   {ARM_EXT_V6K, 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
 927   {ARM_EXT_V6K, 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
 928   {ARM_EXT_V6K, 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
 929   {ARM_EXT_V6K, 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
 930
 931   /* ARM V6K NOP hints.  */
 932   {ARM_EXT_V6K, 0x0320f001, 0x0fffffff, "yield%c"},
 933   {ARM_EXT_V6K, 0x0320f002, 0x0fffffff, "wfe%c"},
 934   {ARM_EXT_V6K, 0x0320f003, 0x0fffffff, "wfi%c"},
 935   {ARM_EXT_V6K, 0x0320f004, 0x0fffffff, "sev%c"},
 936   {ARM_EXT_V6K, 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
 937
 938   /* ARM V6 instructions.  */
 939   {ARM_EXT_V6, 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
 940   {ARM_EXT_V6, 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
 941   {ARM_EXT_V6, 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
 942   {ARM_EXT_V6, 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
 943   {ARM_EXT_V6, 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
 944   {ARM_EXT_V6, 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
 945   {ARM_EXT_V6, 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
 946   {ARM_EXT_V6, 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
 947   {ARM_EXT_V6, 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
 948   {ARM_EXT_V6, 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
 949   {ARM_EXT_V6, 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
 950   {ARM_EXT_V6, 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
 951   {ARM_EXT_V6, 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
 952   {ARM_EXT_V6, 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
 953   {ARM_EXT_V6, 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
 954   {ARM_EXT_V6, 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
 955   {ARM_EXT_V6, 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
 956   {ARM_EXT_V6, 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
 957   {ARM_EXT_V6, 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
 958   {ARM_EXT_V6, 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
 959   {ARM_EXT_V6, 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
 960   {ARM_EXT_V6, 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
 961   {ARM_EXT_V6, 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
 962   {ARM_EXT_V6, 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
 963   {ARM_EXT_V6, 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
 964   {ARM_EXT_V6, 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
 965   {ARM_EXT_V6, 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
 966   {ARM_EXT_V6, 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
 967   {ARM_EXT_V6, 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
 968   {ARM_EXT_V6, 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
 969   {ARM_EXT_V6, 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
 970   {ARM_EXT_V6, 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
 971   {ARM_EXT_V6, 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
 972   {ARM_EXT_V6, 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
 973   {ARM_EXT_V6, 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
 974   {ARM_EXT_V6, 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
 975   {ARM_EXT_V6, 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
 976   {ARM_EXT_V6, 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
 977   {ARM_EXT_V6, 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
 978   {ARM_EXT_V6, 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
 979   {ARM_EXT_V6, 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
 980   {ARM_EXT_V6, 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
 981   {ARM_EXT_V6, 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
 982   {ARM_EXT_V6, 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
 983   {ARM_EXT_V6, 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
 984   {ARM_EXT_V6, 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
 985   {ARM_EXT_V6, 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
 986   {ARM_EXT_V6, 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
 987   {ARM_EXT_V6, 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
 988   {ARM_EXT_V6, 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
 989   {ARM_EXT_V6, 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
 990   {ARM_EXT_V6, 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
 991   {ARM_EXT_V6, 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
 992   {ARM_EXT_V6, 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
 993   {ARM_EXT_V6, 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
 994   {ARM_EXT_V6, 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
 995   {ARM_EXT_V6, 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
 996   {ARM_EXT_V6, 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
 997   {ARM_EXT_V6, 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
 998   {ARM_EXT_V6, 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
 999   {ARM_EXT_V6, 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
1000   {ARM_EXT_V6, 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
1001   {ARM_EXT_V6, 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
1002   {ARM_EXT_V6, 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
1003   {ARM_EXT_V6, 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
1004   {ARM_EXT_V6, 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
1005   {ARM_EXT_V6, 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
1006   {ARM_EXT_V6, 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
1007   {ARM_EXT_V6, 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
1008   {ARM_EXT_V6, 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
1009   {ARM_EXT_V6, 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
1010   {ARM_EXT_V6, 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
1011   {ARM_EXT_V6, 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
1012   {ARM_EXT_V6, 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
1013   {ARM_EXT_V6, 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
1014   {ARM_EXT_V6, 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1015   {ARM_EXT_V6, 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1016   {ARM_EXT_V6, 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1017   {ARM_EXT_V6, 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
1018   {ARM_EXT_V6, 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1019   {ARM_EXT_V6, 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1020   {ARM_EXT_V6, 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1021   {ARM_EXT_V6, 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
1022   {ARM_EXT_V6, 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1023   {ARM_EXT_V6, 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1024   {ARM_EXT_V6, 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1025   {ARM_EXT_V6, 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
1026   {ARM_EXT_V6, 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1027   {ARM_EXT_V6, 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1028   {ARM_EXT_V6, 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1029   {ARM_EXT_V6, 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
1030   {ARM_EXT_V6, 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1031   {ARM_EXT_V6, 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1032   {ARM_EXT_V6, 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
1033   {ARM_EXT_V6, 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
1034   {ARM_EXT_V6, 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
1035   {ARM_EXT_V6, 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
1036   {ARM_EXT_V6, 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
1037   {ARM_EXT_V6, 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
1038   {ARM_EXT_V6, 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
1039   {ARM_EXT_V6, 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
1040   {ARM_EXT_V6, 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
1041   {ARM_EXT_V6, 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1042   {ARM_EXT_V6, 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1043   {ARM_EXT_V6, 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1044   {ARM_EXT_V6, 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1045   {ARM_EXT_V6, 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
1046   {ARM_EXT_V6, 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1047   {ARM_EXT_V6, 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1048   {ARM_EXT_V6, 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
1049   {ARM_EXT_V6, 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
1050   {ARM_EXT_V6, 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
1051   {ARM_EXT_V6, 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
1052   {ARM_EXT_V6, 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
1053   {ARM_EXT_V6, 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
1054   {ARM_EXT_V6, 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
1055   {ARM_EXT_V6, 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
1056   {ARM_EXT_V6, 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1057   {ARM_EXT_V6, 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
1058   {ARM_EXT_V6, 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
1059   {ARM_EXT_V6, 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
1060   {ARM_EXT_V6, 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
1061
1062   /* V5J instruction.  */
1063   {ARM_EXT_V5J, 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
1064
1065   /* V5 Instructions.  */
1066   {ARM_EXT_V5, 0xe1200070, 0xfff000f0, "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
1067   {ARM_EXT_V5, 0xfa000000, 0xfe000000, "blx\t%B"},
1068   {ARM_EXT_V5, 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
1069   {ARM_EXT_V5, 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
1070
1071   /* V5E "El Segundo" Instructions.  */
1072   {ARM_EXT_V5E, 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
1073   {ARM_EXT_V5E, 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
1074   {ARM_EXT_V5E, 0xf450f000, 0xfc70f000, "pld\t%a"},
1075   {ARM_EXT_V5ExP, 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1076   {ARM_EXT_V5ExP, 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1077   {ARM_EXT_V5ExP, 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1078   {ARM_EXT_V5ExP, 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
1079
1080   {ARM_EXT_V5ExP, 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1081   {ARM_EXT_V5ExP, 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
1082
1083   {ARM_EXT_V5ExP, 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1084   {ARM_EXT_V5ExP, 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1085   {ARM_EXT_V5ExP, 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1086   {ARM_EXT_V5ExP, 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1087
1088   {ARM_EXT_V5ExP, 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
1089   {ARM_EXT_V5ExP, 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
1090   {ARM_EXT_V5ExP, 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
1091   {ARM_EXT_V5ExP, 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
1092
1093   {ARM_EXT_V5ExP, 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
1094   {ARM_EXT_V5ExP, 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
1095
1096   {ARM_EXT_V5ExP, 0x01000050, 0x0ff00ff0,  "qadd%c\t%12-15R, %0-3R, %16-19R"},
1097   {ARM_EXT_V5ExP, 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
1098   {ARM_EXT_V5ExP, 0x01200050, 0x0ff00ff0,  "qsub%c\t%12-15R, %0-3R, %16-19R"},
1099   {ARM_EXT_V5ExP, 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
1100
1101   /* ARM Instructions.  */
1102   {ARM_EXT_V1, 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
1103
1104   {ARM_EXT_V1, 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
1105   {ARM_EXT_V1, 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
1106   {ARM_EXT_V1, 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
1107   {ARM_EXT_V1, 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
1108   {ARM_EXT_V1, 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
1109   {ARM_EXT_V1, 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
1110
1111   {ARM_EXT_V1, 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
1112   {ARM_EXT_V1, 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
1113   {ARM_EXT_V1, 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
1114   {ARM_EXT_V1, 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
1115
1116   {ARM_EXT_V1, 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
1117   {ARM_EXT_V1, 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
1118   {ARM_EXT_V1, 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
1119   {ARM_EXT_V1, 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
1120
1121   {ARM_EXT_V1, 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
1122   {ARM_EXT_V1, 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
1123   {ARM_EXT_V1, 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
1124
1125   {ARM_EXT_V1, 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
1126   {ARM_EXT_V1, 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
1127   {ARM_EXT_V1, 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
1128
1129   {ARM_EXT_V1, 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
1130   {ARM_EXT_V1, 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
1131   {ARM_EXT_V1, 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
1132
1133   {ARM_EXT_V1, 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
1134   {ARM_EXT_V1, 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
1135   {ARM_EXT_V1, 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
1136
1137   {ARM_EXT_V1, 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
1138   {ARM_EXT_V1, 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
1139   {ARM_EXT_V1, 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
1140
1141   {ARM_EXT_V1, 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
1142   {ARM_EXT_V1, 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
1143   {ARM_EXT_V1, 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
1144
1145   {ARM_EXT_V1, 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
1146   {ARM_EXT_V1, 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
1147   {ARM_EXT_V1, 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
1148
1149   {ARM_EXT_V1, 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
1150   {ARM_EXT_V1, 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
1151   {ARM_EXT_V1, 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
1152
1153   {ARM_EXT_VIRT, 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
1154   {ARM_EXT_V3, 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
1155   {ARM_EXT_V3, 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
1156
1157   {ARM_EXT_V1, 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
1158   {ARM_EXT_V1, 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
1159   {ARM_EXT_V1, 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
1160
1161   {ARM_EXT_V1, 0x03200000, 0x0fe00000, "teq%p%c\t%16-19r, %o"},
1162   {ARM_EXT_V1, 0x01200000, 0x0fe00010, "teq%p%c\t%16-19r, %o"},
1163   {ARM_EXT_V1, 0x01200010, 0x0fe00090, "teq%p%c\t%16-19R, %o"},
1164
1165   {ARM_EXT_V1, 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
1166   {ARM_EXT_V1, 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
1167   {ARM_EXT_V1, 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
1168
1169   {ARM_EXT_V1, 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
1170   {ARM_EXT_V1, 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
1171   {ARM_EXT_V1, 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
1172
1173   {ARM_EXT_V1, 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
1174   {ARM_EXT_V1, 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
1175   {ARM_EXT_V1, 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
1176
1177   {ARM_EXT_V1, 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
1178   {ARM_EXT_V1, 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
1179   {ARM_EXT_V1, 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
1180   {ARM_EXT_V1, 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
1181   {ARM_EXT_V1, 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
1182   {ARM_EXT_V1, 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
1183   {ARM_EXT_V1, 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
1184
1185   {ARM_EXT_V1, 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
1186   {ARM_EXT_V1, 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
1187   {ARM_EXT_V1, 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
1188
1189   {ARM_EXT_V1, 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
1190   {ARM_EXT_V1, 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
1191   {ARM_EXT_V1, 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
1192
1193   {ARM_EXT_V1, 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
1194   {ARM_EXT_V1, 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
1195
1196   {ARM_EXT_V1, 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
1197
1198   {ARM_EXT_V1, 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
1199   {ARM_EXT_V1, 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
1200
1201   {ARM_EXT_V1, 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1202   {ARM_EXT_V1, 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1203   {ARM_EXT_V1, 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1204   {ARM_EXT_V1, 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1205   {ARM_EXT_V1, 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1206   {ARM_EXT_V1, 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1207   {ARM_EXT_V1, 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1208   {ARM_EXT_V1, 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1209   {ARM_EXT_V1, 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1210   {ARM_EXT_V1, 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1211   {ARM_EXT_V1, 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1212   {ARM_EXT_V1, 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1213   {ARM_EXT_V1, 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1214   {ARM_EXT_V1, 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1215   {ARM_EXT_V1, 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1216   {ARM_EXT_V1, 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
1217   {ARM_EXT_V1, 0x092d0000, 0x0fff0000, "push%c\t%m"},
1218   {ARM_EXT_V1, 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
1219   {ARM_EXT_V1, 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
1220
1221   {ARM_EXT_V1, 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1222   {ARM_EXT_V1, 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1223   {ARM_EXT_V1, 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1224   {ARM_EXT_V1, 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1225   {ARM_EXT_V1, 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1226   {ARM_EXT_V1, 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1227   {ARM_EXT_V1, 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1228   {ARM_EXT_V1, 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1229   {ARM_EXT_V1, 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1230   {ARM_EXT_V1, 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1231   {ARM_EXT_V1, 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1232   {ARM_EXT_V1, 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1233   {ARM_EXT_V1, 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1234   {ARM_EXT_V1, 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1235   {ARM_EXT_V1, 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1236   {ARM_EXT_V1, 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
1237   {ARM_EXT_V1, 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
1238   {ARM_EXT_V1, 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
1239   {ARM_EXT_V1, 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
1240
1241   {ARM_EXT_V1, 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
1242   {ARM_EXT_V1, 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
1243
1244   /* The rest.  */
1245   {ARM_EXT_V1, 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
1246   {0, 0x00000000, 0x00000000, 0}
1247 };
1248
1249 /* print_insn_thumb16 recognizes the following format control codes:
1250
1251    %S                   print Thumb register (bits 3..5 as high number if bit 6 set)
1252    %D                   print Thumb register (bits 0..2 as high number if bit 7 set)
1253    %<bitfield>I         print bitfield as a signed decimal
1254                                 (top bit of range being the sign bit)
1255    %N                   print Thumb register mask (with LR)
1256    %O                   print Thumb register mask (with PC)
1257    %M                   print Thumb register mask
1258    %b                   print CZB's 6-bit unsigned branch destination
1259    %s                   print Thumb right-shift immediate (6..10; 0 == 32).
1260    %c                   print the condition code
1261    %C                   print the condition code, or "s" if not conditional
1262    %x                   print warning if conditional an not at end of IT block"
1263    %X                   print "\t; unpredictable <IT:code>" if conditional
1264    %I                   print IT instruction suffix and operands
1265    %W                   print Thumb Writeback indicator for LDMIA
1266    %<bitfield>r         print bitfield as an ARM register
1267    %<bitfield>d         print bitfield as a decimal
1268    %<bitfield>H         print (bitfield * 2) as a decimal
1269    %<bitfield>W         print (bitfield * 4) as a decimal
1270    %<bitfield>a         print (bitfield * 4) as a pc-rel offset + decoded symbol
1271    %<bitfield>B         print Thumb branch destination (signed displacement)
1272    %<bitfield>c         print bitfield as a condition code
1273    %<bitnum>'c          print specified char iff bit is one
1274    %<bitnum>?ab         print a if bit is one else print b.  */
1275
1276 static const struct opcode16 thumb_opcodes[] =
1277 {
1278   /* Thumb instructions.  */
1279
1280   /* ARM V8 instructions.  */
1281   {ARM_EXT_V8,  0xbf50, 0xffff, "sevl%c"},
1282   {ARM_EXT_V8,  0xba80, 0xffc0, "hlt\t%0-5x"},
1283
1284   /* ARM V6K no-argument instructions.  */
1285   {ARM_EXT_V6K, 0xbf00, 0xffff, "nop%c"},
1286   {ARM_EXT_V6K, 0xbf10, 0xffff, "yield%c"},
1287   {ARM_EXT_V6K, 0xbf20, 0xffff, "wfe%c"},
1288   {ARM_EXT_V6K, 0xbf30, 0xffff, "wfi%c"},
1289   {ARM_EXT_V6K, 0xbf40, 0xffff, "sev%c"},
1290   {ARM_EXT_V6K, 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
1291
1292   /* ARM V6T2 instructions.  */
1293   {ARM_EXT_V6T2, 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
1294   {ARM_EXT_V6T2, 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
1295   {ARM_EXT_V6T2, 0xbf00, 0xff00, "it%I%X"},
1296
1297   /* ARM V6.  */
1298   {ARM_EXT_V6, 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
1299   {ARM_EXT_V6, 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
1300   {ARM_EXT_V6, 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
1301   {ARM_EXT_V6, 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
1302   {ARM_EXT_V6, 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
1303   {ARM_EXT_V6, 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
1304   {ARM_EXT_V6, 0xb650, 0xfff7, "setend\t%3?ble%X"},
1305   {ARM_EXT_V6, 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
1306   {ARM_EXT_V6, 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
1307   {ARM_EXT_V6, 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
1308   {ARM_EXT_V6, 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
1309
1310   /* ARM V5 ISA extends Thumb.  */
1311   {ARM_EXT_V5T, 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional.  */
1312   /* This is BLX(2).  BLX(1) is a 32-bit instruction.  */
1313   {ARM_EXT_V5T, 0x4780, 0xff87, "blx%c\t%3-6r%x"},      /* note: 4 bit register number.  */
1314   /* ARM V4T ISA (Thumb v1).  */
1315   {ARM_EXT_V4T, 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
1316   /* Format 4.  */
1317   {ARM_EXT_V4T, 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
1318   {ARM_EXT_V4T, 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
1319   {ARM_EXT_V4T, 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
1320   {ARM_EXT_V4T, 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
1321   {ARM_EXT_V4T, 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
1322   {ARM_EXT_V4T, 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
1323   {ARM_EXT_V4T, 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
1324   {ARM_EXT_V4T, 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
1325   {ARM_EXT_V4T, 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
1326   {ARM_EXT_V4T, 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
1327   {ARM_EXT_V4T, 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
1328   {ARM_EXT_V4T, 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
1329   {ARM_EXT_V4T, 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
1330   {ARM_EXT_V4T, 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
1331   {ARM_EXT_V4T, 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
1332   {ARM_EXT_V4T, 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
1333   /* format 13 */
1334   {ARM_EXT_V4T, 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
1335   {ARM_EXT_V4T, 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
1336   /* format 5 */
1337   {ARM_EXT_V4T, 0x4700, 0xFF80, "bx%c\t%S%x"},
1338   {ARM_EXT_V4T, 0x4400, 0xFF00, "add%c\t%D, %S"},
1339   {ARM_EXT_V4T, 0x4500, 0xFF00, "cmp%c\t%D, %S"},
1340   {ARM_EXT_V4T, 0x4600, 0xFF00, "mov%c\t%D, %S"},
1341   /* format 14 */
1342   {ARM_EXT_V4T, 0xB400, 0xFE00, "push%c\t%N"},
1343   {ARM_EXT_V4T, 0xBC00, 0xFE00, "pop%c\t%O"},
1344   /* format 2 */
1345   {ARM_EXT_V4T, 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
1346   {ARM_EXT_V4T, 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
1347   {ARM_EXT_V4T, 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
1348   {ARM_EXT_V4T, 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
1349   /* format 8 */
1350   {ARM_EXT_V4T, 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
1351   {ARM_EXT_V4T, 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
1352   {ARM_EXT_V4T, 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
1353   /* format 7 */
1354   {ARM_EXT_V4T, 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
1355   {ARM_EXT_V4T, 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
1356   /* format 1 */
1357   {ARM_EXT_V4T, 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
1358   {ARM_EXT_V4T, 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
1359   {ARM_EXT_V4T, 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
1360   {ARM_EXT_V4T, 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
1361   /* format 3 */
1362   {ARM_EXT_V4T, 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
1363   {ARM_EXT_V4T, 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
1364   {ARM_EXT_V4T, 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
1365   {ARM_EXT_V4T, 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
1366   /* format 6 */
1367   {ARM_EXT_V4T, 0x4800, 0xF800, "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},  /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
1368   /* format 9 */
1369   {ARM_EXT_V4T, 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
1370   {ARM_EXT_V4T, 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
1371   {ARM_EXT_V4T, 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
1372   {ARM_EXT_V4T, 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
1373   /* format 10 */
1374   {ARM_EXT_V4T, 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
1375   {ARM_EXT_V4T, 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
1376   /* format 11 */
1377   {ARM_EXT_V4T, 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
1378   {ARM_EXT_V4T, 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
1379   /* format 12 */
1380   {ARM_EXT_V4T, 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
1381   {ARM_EXT_V4T, 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
1382   /* format 15 */
1383   {ARM_EXT_V4T, 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
1384   {ARM_EXT_V4T, 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
1385   /* format 17 */
1386   {ARM_EXT_V4T, 0xDF00, 0xFF00, "svc%c\t%0-7d"},
1387   /* format 16 */
1388   {ARM_EXT_V4T, 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
1389   {ARM_EXT_V4T, 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
1390   /* format 18 */
1391   {ARM_EXT_V4T, 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
1392
1393   /* The E800 .. FFFF range is unconditionally redirected to the
1394      32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
1395      are processed via that table.  Thus, we can never encounter a
1396      bare "second half of BL/BLX(1)" instruction here.  */
1397   {ARM_EXT_V1,  0x0000, 0x0000, UNDEFINED_INSTRUCTION},
1398   {0, 0, 0, 0}
1399 };
1400
1401 /* Thumb32 opcodes use the same table structure as the ARM opcodes.
1402    We adopt the convention that hw1 is the high 16 bits of .value and
1403    .mask, hw2 the low 16 bits.
1404
1405    print_insn_thumb32 recognizes the following format control codes:
1406
1407        %%               %
1408
1409        %I               print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
1410        %M               print a modified 12-bit immediate (same location)
1411        %J               print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
1412        %K               print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
1413        %H               print a 16-bit immediate from hw2[3:0],hw1[11:0]
1414        %S               print a possibly-shifted Rm
1415
1416        %L               print address for a ldrd/strd instruction
1417        %a               print the address of a plain load/store
1418        %w               print the width and signedness of a core load/store
1419        %m               print register mask for ldm/stm
1420
1421        %E               print the lsb and width fields of a bfc/bfi instruction
1422        %F               print the lsb and width fields of a sbfx/ubfx instruction
1423        %b               print a conditional branch offset
1424        %B               print an unconditional branch offset
1425        %s               print the shift field of an SSAT instruction
1426        %R               print the rotation field of an SXT instruction
1427        %U               print barrier type.
1428        %P               print address for pli instruction.
1429        %c               print the condition code
1430        %x               print warning if conditional an not at end of IT block"
1431        %X               print "\t; unpredictable <IT:code>" if conditional
1432
1433        %<bitfield>d     print bitfield in decimal
1434        %<bitfield>W     print bitfield*4 in decimal
1435        %<bitfield>r     print bitfield as an ARM register
1436        %<bitfield>R     as %<>r bit r15 is UNPREDICTABLE
1437        %<bitfield>c     print bitfield as a condition code
1438
1439        %<bitfield>'c    print specified char iff bitfield is all ones
1440        %<bitfield>`c    print specified char iff bitfield is all zeroes
1441        %<bitfield>?ab... select from array of values in big endian order
1442
1443    With one exception at the bottom (done because BL and BLX(1) need
1444    to come dead last), this table was machine-sorted first in
1445    decreasing order of number of bits set in the mask, then in
1446    increasing numeric order of mask, then in increasing numeric order
1447    of opcode.  This order is not the clearest for a human reader, but
1448    is guaranteed never to catch a special-case bit pattern with a more
1449    general mask, which is important, because this instruction encoding
1450    makes heavy use of special-case bit patterns.  */
1451 static const struct opcode32 thumb32_opcodes[] =
1452 {
1453   /* V8 instructions.  */
1454   {ARM_EXT_V8, 0xf3af8005, 0xffffffff, "sevl%c.w"},
1455   {ARM_EXT_V8, 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
1456   {ARM_EXT_V8, 0xe8c00f8f, 0xfff00fff, "strlb%c\t%12-15r, [%16-19R]"},
1457   {ARM_EXT_V8, 0xe8c00f9f, 0xfff00fff, "strlh%c\t%12-15r, [%16-19R]"},
1458   {ARM_EXT_V8, 0xe8c00faf, 0xfff00fff, "strl%c\t%12-15r, [%16-19R]"},
1459   {ARM_EXT_V8, 0xe8c00fc0, 0xfff00ff0, "strlexb%c\t%0-3r, %12-15r, [%16-19R]"},
1460   {ARM_EXT_V8, 0xe8c00fd0, 0xfff00ff0, "strlexh%c\t%0-3r, %12-15r, [%16-19R]"},
1461   {ARM_EXT_V8, 0xe8c00fe0, 0xfff00ff0, "strlex%c\t%0-3r, %12-15r, [%16-19R]"},
1462   {ARM_EXT_V8, 0xe8c000f0, 0xfff000f0, "strlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
1463   {ARM_EXT_V8, 0xe8d00f8f, 0xfff00fff, "ldrab%c\t%12-15r, [%16-19R]"},
1464   {ARM_EXT_V8, 0xe8d00f9f, 0xfff00fff, "ldrah%c\t%12-15r, [%16-19R]"},
1465   {ARM_EXT_V8, 0xe8d00faf, 0xfff00fff, "ldra%c\t%12-15r, [%16-19R]"},
1466   {ARM_EXT_V8, 0xe8d00fcf, 0xfff00fff, "ldraexb%c\t%12-15r, [%16-19R]"},
1467   {ARM_EXT_V8, 0xe8d00fdf, 0xfff00fff, "ldraexh%c\t%12-15r, [%16-19R]"},
1468   {ARM_EXT_V8, 0xe8d00fef, 0xfff00fff, "ldraex%c\t%12-15r, [%16-19R]"},
1469   {ARM_EXT_V8, 0xe8d000ff, 0xfff000ff, "ldraexd%c\t%12-15r, %8-11r, [%16-19R]"},
1470
1471   /* V7 instructions.  */
1472   {ARM_EXT_V7, 0xf910f000, 0xff70f000, "pli%c\t%a"},
1473   {ARM_EXT_V7, 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
1474   {ARM_EXT_V8, 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
1475   {ARM_EXT_V8, 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
1476   {ARM_EXT_V7, 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
1477   {ARM_EXT_V7, 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
1478   {ARM_EXT_V7, 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
1479   {ARM_EXT_DIV, 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
1480   {ARM_EXT_DIV, 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
1481
1482   /* Virtualization Extension instructions.  */
1483   {ARM_EXT_VIRT, 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
1484   /* We skip ERET as that is SUBS pc, lr, #0.  */
1485
1486   /* MP Extension instructions.  */
1487   {ARM_EXT_MP,   0xf830f000, 0xff70f000, "pldw%c\t%a"},
1488
1489   /* Security extension instructions.  */
1490   {ARM_EXT_SEC,  0xf7f08000, 0xfff0f000, "smc%c\t%K"},
1491
1492   /* Instructions defined in the basic V6T2 set.  */
1493   {ARM_EXT_V6T2, 0xf3af8000, 0xffffffff, "nop%c.w"},
1494   {ARM_EXT_V6T2, 0xf3af8001, 0xffffffff, "yield%c.w"},
1495   {ARM_EXT_V6T2, 0xf3af8002, 0xffffffff, "wfe%c.w"},
1496   {ARM_EXT_V6T2, 0xf3af8003, 0xffffffff, "wfi%c.w"},
1497   {ARM_EXT_V6T2, 0xf3af8004, 0xffffffff, "sev%c.w"},
1498   {ARM_EXT_V6T2, 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
1499
1500   {ARM_EXT_V6T2, 0xf3bf8f2f, 0xffffffff, "clrex%c"},
1501   {ARM_EXT_V6T2, 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
1502   {ARM_EXT_V6T2, 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
1503   {ARM_EXT_V6T2, 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
1504   {ARM_EXT_V6T2, 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
1505   {ARM_EXT_V6T2, 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
1506   {ARM_EXT_V6T2, 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
1507   {ARM_EXT_V6T2, 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
1508   {ARM_EXT_V6T2, 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
1509   {ARM_EXT_V6T2, 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
1510   {ARM_EXT_V6T2, 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
1511   {ARM_EXT_V6T2, 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
1512   {ARM_EXT_V6T2, 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
1513   {ARM_EXT_V6T2, 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
1514   {ARM_EXT_V6T2, 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
1515   {ARM_EXT_V6T2, 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
1516   {ARM_EXT_V6T2, 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
1517   {ARM_EXT_V6T2, 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
1518   {ARM_EXT_V6T2, 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
1519   {ARM_EXT_V6T2, 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
1520   {ARM_EXT_V6T2, 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
1521   {ARM_EXT_V6T2, 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
1522   {ARM_EXT_V6T2, 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
1523   {ARM_EXT_V6T2, 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
1524   {ARM_EXT_V6T2, 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
1525   {ARM_EXT_V6T2, 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
1526   {ARM_EXT_V6T2, 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
1527   {ARM_EXT_V6T2, 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
1528   {ARM_EXT_V6T2, 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
1529   {ARM_EXT_V6T2, 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
1530   {ARM_EXT_V6T2, 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
1531   {ARM_EXT_V6T2, 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
1532   {ARM_EXT_V6T2, 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
1533   {ARM_EXT_V6T2, 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
1534   {ARM_EXT_V6T2, 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
1535   {ARM_EXT_V6T2, 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
1536   {ARM_EXT_V6T2, 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
1537   {ARM_EXT_V6T2, 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
1538   {ARM_EXT_V6T2, 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
1539   {ARM_EXT_V6T2, 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
1540   {ARM_EXT_V6T2, 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
1541   {ARM_EXT_V6T2, 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
1542   {ARM_EXT_V6T2, 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
1543   {ARM_EXT_V6T2, 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
1544   {ARM_EXT_V6T2, 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
1545   {ARM_EXT_V6T2, 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
1546   {ARM_EXT_V6T2, 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
1547   {ARM_EXT_V6T2, 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
1548   {ARM_EXT_V6T2, 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
1549   {ARM_EXT_V6T2, 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
1550   {ARM_EXT_V6T2, 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
1551   {ARM_EXT_V6T2, 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
1552   {ARM_EXT_V6T2, 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
1553   {ARM_EXT_V6T2, 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
1554   {ARM_EXT_V6T2, 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
1555   {ARM_EXT_V6T2, 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
1556   {ARM_EXT_V6T2, 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
1557   {ARM_EXT_V6T2, 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
1558   {ARM_EXT_V6T2, 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
1559   {ARM_EXT_V6T2, 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
1560   {ARM_EXT_V6T2, 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
1561   {ARM_EXT_V6T2, 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
1562   {ARM_EXT_V6T2, 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
1563   {ARM_EXT_V6T2, 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
1564   {ARM_EXT_V6T2, 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
1565   {ARM_EXT_V6T2, 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
1566   {ARM_EXT_V6T2, 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
1567   {ARM_EXT_V6T2, 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
1568   {ARM_EXT_V6T2, 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
1569   {ARM_EXT_V6T2, 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
1570   {ARM_EXT_V6T2, 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
1571   {ARM_EXT_V6T2, 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
1572   {ARM_EXT_V6T2, 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
1573   {ARM_EXT_V6T2, 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
1574   {ARM_EXT_V6T2, 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
1575   {ARM_EXT_V6T2, 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
1576   {ARM_EXT_V6T2, 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
1577   {ARM_EXT_V6T2, 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
1578   {ARM_EXT_V6T2, 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
1579   {ARM_EXT_V6T2, 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4d, %16-19r"},
1580   {ARM_EXT_V6T2, 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
1581   {ARM_EXT_V6T2, 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
1582   {ARM_EXT_V6T2, 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
1583   {ARM_EXT_V6T2, 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
1584   {ARM_EXT_V6T2, 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
1585   {ARM_EXT_V6T2, 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
1586   {ARM_EXT_V6T2, 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
1587   {ARM_EXT_V6T2, 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
1588   {ARM_EXT_V6T2, 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
1589   {ARM_EXT_V6T2, 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
1590   {ARM_EXT_V6T2, 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
1591   {ARM_EXT_V6T2, 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
1592   {ARM_EXT_V6T2, 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
1593   {ARM_EXT_V6T2, 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
1594   {ARM_EXT_V6T2, 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
1595   {ARM_EXT_V6T2, 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
1596   {ARM_EXT_V6T2, 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
1597   {ARM_EXT_V6T2, 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
1598   {ARM_EXT_V6T2, 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
1599   {ARM_EXT_V6T2, 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
1600   {ARM_EXT_V6T2, 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
1601   {ARM_EXT_V6T2, 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
1602   {ARM_EXT_V6T2, 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
1603   {ARM_EXT_V6T2, 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
1604   {ARM_EXT_V6T2, 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
1605   {ARM_EXT_V6T2, 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
1606   {ARM_EXT_V6T2, 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
1607   {ARM_EXT_V6T2, 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
1608   {ARM_EXT_V6T2, 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
1609   {ARM_EXT_V6T2, 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
1610   {ARM_EXT_V6T2, 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
1611   {ARM_EXT_V6T2, 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
1612   {ARM_EXT_V6T2, 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
1613   {ARM_EXT_V6T2, 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
1614   {ARM_EXT_V6T2, 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
1615   {ARM_EXT_V6T2, 0xf810f000, 0xff70f000, "pld%c\t%a"},
1616   {ARM_EXT_V6T2, 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
1617   {ARM_EXT_V6T2, 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
1618   {ARM_EXT_V6T2, 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
1619   {ARM_EXT_V6T2, 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
1620   {ARM_EXT_V6T2, 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
1621   {ARM_EXT_V6T2, 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
1622   {ARM_EXT_V6T2, 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
1623   {ARM_EXT_V6T2, 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
1624   {ARM_EXT_V6T2, 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
1625   {ARM_EXT_V6T2, 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
1626   {ARM_EXT_V6T2, 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
1627   {ARM_EXT_V6T2, 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
1628   {ARM_EXT_V6T2, 0xfb100000, 0xfff000c0, "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
1629   {ARM_EXT_V6T2, 0xfbc00080, 0xfff000c0, "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
1630   {ARM_EXT_V6T2, 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
1631   {ARM_EXT_V6T2, 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
1632   {ARM_EXT_V6T2, 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4d, %16-19r%s"},
1633   {ARM_EXT_V6T2, 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
1634   {ARM_EXT_V6T2, 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
1635   {ARM_EXT_V6T2, 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
1636   {ARM_EXT_V6T2, 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
1637   {ARM_EXT_V6T2, 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
1638   {ARM_EXT_V6T2, 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
1639   {ARM_EXT_V6T2, 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
1640   {ARM_EXT_V6T2, 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
1641   {ARM_EXT_V6T2, 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
1642   {ARM_EXT_V6T2, 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
1643   {ARM_EXT_V6T2, 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
1644   {ARM_EXT_V6T2, 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
1645   {ARM_EXT_V6T2, 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
1646   {ARM_EXT_V6T2, 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
1647   {ARM_EXT_V6T2, 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
1648   {ARM_EXT_V6T2, 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
1649   {ARM_EXT_V6T2, 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
1650   {ARM_EXT_V6T2, 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
1651   {ARM_EXT_V6T2, 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
1652   {ARM_EXT_V6T2, 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
1653   {ARM_EXT_V6T2, 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
1654   {ARM_EXT_V6T2, 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
1655   {ARM_EXT_V6T2, 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
1656   {ARM_EXT_V6T2, 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
1657   {ARM_EXT_V6T2, 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
1658   {ARM_EXT_V6T2, 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
1659   {ARM_EXT_V6T2, 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
1660   {ARM_EXT_V6T2, 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
1661   {ARM_EXT_V6T2, 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
1662   {ARM_EXT_V6T2, 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
1663   {ARM_EXT_V6T2, 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
1664   {ARM_EXT_V6T2, 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
1665   {ARM_EXT_V6T2, 0xe9400000, 0xff500000, "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
1666   {ARM_EXT_V6T2, 0xe9500000, 0xff500000, "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
1667   {ARM_EXT_V6T2, 0xe8600000, 0xff700000, "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
1668   {ARM_EXT_V6T2, 0xe8700000, 0xff700000, "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
1669   {ARM_EXT_V6T2, 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
1670   {ARM_EXT_V6T2, 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
1671
1672   /* Filter out Bcc with cond=E or F, which are used for other instructions.  */
1673   {ARM_EXT_V6T2, 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
1674   {ARM_EXT_V6T2, 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
1675   {ARM_EXT_V6T2, 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
1676   {ARM_EXT_V6T2, 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
1677
1678   /* These have been 32-bit since the invention of Thumb.  */
1679   {ARM_EXT_V4T,  0xf000c000, 0xf800d001, "blx%c\t%B%x"},
1680   {ARM_EXT_V4T,  0xf000d000, 0xf800d000, "bl%c\t%B%x"},
1681
1682   /* Fallback.  */
1683   {ARM_EXT_V1,   0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
1684   {0, 0, 0, 0}
1685 };
1686
1687 static const char *const arm_conditional[] =
1688 {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
1689  "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
1690
1691 static const char *const arm_fp_const[] =
1692 {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
1693
1694 static const char *const arm_shift[] =
1695 {"lsl", "lsr", "asr", "ror"};
1696
1697 typedef struct
1698 {
1699   const char *name;
1700   const char *description;
1701   const char *reg_names[16];
1702 }
1703 arm_regname;
1704
1705 static const arm_regname regnames[] =
1706 {
1707   { "raw" , "Select raw register names",
1708     { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
1709   { "gcc",  "Select register names used by GCC",
1710     { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl",  "fp",  "ip",  "sp",  "lr",  "pc" }},
1711   { "std",  "Select register names used in ARM's ISA documentation",
1712     { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp",  "lr",  "pc" }},
1713   { "apcs", "Select register names used in the APCS",
1714     { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl",  "fp",  "ip",  "sp",  "lr",  "pc" }},
1715   { "atpcs", "Select register names used in the ATPCS",
1716     { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7",  "v8",  "IP",  "SP",  "LR",  "PC" }},
1717   { "special-atpcs", "Select special register names used in the ATPCS",
1718     { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL",  "FP",  "IP",  "SP",  "LR",  "PC" }},
1719 };
1720
1721 static const char *const iwmmxt_wwnames[] =
1722 {"b", "h", "w", "d"};
1723
1724 static const char *const iwmmxt_wwssnames[] =
1725 {"b", "bus", "bc", "bss",
1726  "h", "hus", "hc", "hss",
1727  "w", "wus", "wc", "wss",
1728  "d", "dus", "dc", "dss"
1729 };
1730
1731 static const char *const iwmmxt_regnames[] =
1732 { "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
1733   "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
1734 };
1735
1736 static const char *const iwmmxt_cregnames[] =
1737 { "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
1738   "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
1739 };
1740
1741 /* Default to GCC register name set.  */
1742 static unsigned int regname_selected = 1;
1743
1744 #define NUM_ARM_REGNAMES  NUM_ELEM (regnames)
1745 #define arm_regnames      regnames[regname_selected].reg_names
1746
1747 static bfd_boolean force_thumb = FALSE;
1748
1749 /* Current IT instruction state.  This contains the same state as the IT
1750    bits in the CPSR.  */
1751 static unsigned int ifthen_state;
1752 /* IT state for the next instruction.  */
1753 static unsigned int ifthen_next_state;
1754 /* The address of the insn for which the IT state is valid.  */
1755 static bfd_vma ifthen_address;
1756 #define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
1757 /* Indicates that the current Conditional state is unconditional or outside
1758    an IT block.  */
1759 #define COND_UNCOND 16
1760
1761 \f
1762 /* Functions.  */
1763 int
1764 get_arm_regname_num_options (void)
1765 {
1766   return NUM_ARM_REGNAMES;
1767 }
1768
1769 int
1770 set_arm_regname_option (int option)
1771 {
1772   int old = regname_selected;
1773   regname_selected = option;
1774   return old;
1775 }
1776
1777 int
1778 get_arm_regnames (int option,
1779                   const char **setname,
1780                   const char **setdescription,
1781                   const char *const **register_names)
1782 {
1783   *setname = regnames[option].name;
1784   *setdescription = regnames[option].description;
1785   *register_names = regnames[option].reg_names;
1786   return 16;
1787 }
1788
1789 /* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
1790    Returns pointer to following character of the format string and
1791    fills in *VALUEP and *WIDTHP with the extracted value and number of
1792    bits extracted.  WIDTHP can be NULL.  */
1793
1794 static const char *
1795 arm_decode_bitfield (const char *ptr,
1796                      unsigned long insn,
1797                      unsigned long *valuep,
1798                      int *widthp)
1799 {
1800   unsigned long value = 0;
1801   int width = 0;
1802
1803   do
1804     {
1805       int start, end;
1806       int bits;
1807
1808       for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
1809         start = start * 10 + *ptr - '0';
1810       if (*ptr == '-')
1811         for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
1812           end = end * 10 + *ptr - '0';
1813       else
1814         end = start;
1815       bits = end - start;
1816       if (bits < 0)
1817         abort ();
1818       value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
1819       width += bits + 1;
1820     }
1821   while (*ptr++ == ',');
1822   *valuep = value;
1823   if (widthp)
1824     *widthp = width;
1825   return ptr - 1;
1826 }
1827
1828 static void
1829 arm_decode_shift (long given, fprintf_ftype func, void *stream,
1830                   bfd_boolean print_shift)
1831 {
1832   func (stream, "%s", arm_regnames[given & 0xf]);
1833
1834   if ((given & 0xff0) != 0)
1835     {
1836       if ((given & 0x10) == 0)
1837         {
1838           int amount = (given & 0xf80) >> 7;
1839           int shift = (given & 0x60) >> 5;
1840
1841           if (amount == 0)
1842             {
1843               if (shift == 3)
1844                 {
1845                   func (stream, ", rrx");
1846                   return;
1847                 }
1848
1849               amount = 32;
1850             }
1851
1852           if (print_shift)
1853             func (stream, ", %s #%d", arm_shift[shift], amount);
1854           else
1855             func (stream, ", #%d", amount);
1856         }
1857       else if ((given & 0x80) == 0x80)
1858         func (stream, "\t; <illegal shifter operand>");
1859       else if (print_shift)
1860         func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
1861               arm_regnames[(given & 0xf00) >> 8]);
1862       else
1863         func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
1864     }
1865 }
1866
1867 #define W_BIT 21
1868 #define I_BIT 22
1869 #define U_BIT 23
1870 #define P_BIT 24
1871
1872 #define WRITEBACK_BIT_SET   (given & (1 << W_BIT))
1873 #define IMMEDIATE_BIT_SET   (given & (1 << I_BIT))
1874 #define NEGATIVE_BIT_SET   ((given & (1 << U_BIT)) == 0)
1875 #define PRE_BIT_SET         (given & (1 << P_BIT))
1876
1877 /* Print one coprocessor instruction on INFO->STREAM.
1878    Return TRUE if the instuction matched, FALSE if this is not a
1879    recognised coprocessor instruction.  */
1880
1881 static bfd_boolean
1882 print_insn_coprocessor (bfd_vma pc,
1883                         struct disassemble_info *info,
1884                         long given,
1885                         bfd_boolean thumb)
1886 {
1887   const struct opcode32 *insn;
1888   void *stream = info->stream;
1889   fprintf_ftype func = info->fprintf_func;
1890   unsigned long mask;
1891   unsigned long value = 0;
1892   struct arm_private_data *private_data = info->private_data;
1893   unsigned long allowed_arches = private_data->features.coproc;
1894   int cond;
1895
1896   for (insn = coprocessor_opcodes; insn->assembler; insn++)
1897     {
1898       unsigned long u_reg = 16;
1899       bfd_boolean is_unpredictable = FALSE;
1900       signed long value_in_comment = 0;
1901       const char *c;
1902
1903       if (insn->arch == 0)
1904         switch (insn->value)
1905           {
1906           case SENTINEL_IWMMXT_START:
1907             if (info->mach != bfd_mach_arm_XScale
1908                 && info->mach != bfd_mach_arm_iWMMXt
1909                 && info->mach != bfd_mach_arm_iWMMXt2)
1910               do
1911                 insn++;
1912               while (insn->arch != 0 && insn->value != SENTINEL_IWMMXT_END);
1913             continue;
1914
1915           case SENTINEL_IWMMXT_END:
1916             continue;
1917
1918           case SENTINEL_GENERIC_START:
1919             allowed_arches = private_data->features.core;
1920             continue;
1921
1922           default:
1923             abort ();
1924           }
1925
1926       mask = insn->mask;
1927       value = insn->value;
1928       if (thumb)
1929         {
1930           /* The high 4 bits are 0xe for Arm conditional instructions, and
1931              0xe for arm unconditional instructions.  The rest of the
1932              encoding is the same.  */
1933           mask |= 0xf0000000;
1934           value |= 0xe0000000;
1935           if (ifthen_state)
1936             cond = IFTHEN_COND;
1937           else
1938             cond = COND_UNCOND;
1939         }
1940       else
1941         {
1942           /* Only match unconditional instuctions against unconditional
1943              patterns.  */
1944           if ((given & 0xf0000000) == 0xf0000000)
1945             {
1946               mask |= 0xf0000000;
1947               cond = COND_UNCOND;
1948             }
1949           else
1950             {
1951               cond = (given >> 28) & 0xf;
1952               if (cond == 0xe)
1953                 cond = COND_UNCOND;
1954             }
1955         }
1956
1957       if ((given & mask) != value)
1958         continue;
1959
1960       if ((insn->arch & allowed_arches) == 0)
1961         continue;
1962
1963       for (c = insn->assembler; *c; c++)
1964         {
1965           if (*c == '%')
1966             {
1967               switch (*++c)
1968                 {
1969                 case '%':
1970                   func (stream, "%%");
1971                   break;
1972
1973                 case 'A':
1974                   {
1975                     int rn = (given >> 16) & 0xf;
1976                     bfd_vma offset = given & 0xff;
1977
1978                     func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
1979
1980                     if (PRE_BIT_SET || WRITEBACK_BIT_SET)
1981                       {
1982                         /* Not unindexed.  The offset is scaled.  */
1983                         offset = offset * 4;
1984                         if (NEGATIVE_BIT_SET)
1985                           offset = - offset;
1986                         if (rn != 15)
1987                           value_in_comment = offset;
1988                       }
1989
1990                     if (PRE_BIT_SET)
1991                       {
1992                         if (offset)
1993                           func (stream, ", #%d]%s",
1994                                 (int) offset,
1995                                 WRITEBACK_BIT_SET ? "!" : "");
1996                         else if (NEGATIVE_BIT_SET)
1997                           func (stream, ", #-0]");
1998                         else
1999                           func (stream, "]");
2000                       }
2001                     else
2002                       {
2003                         func (stream, "]");
2004
2005                         if (WRITEBACK_BIT_SET)
2006                           {
2007                             if (offset)
2008                               func (stream, ", #%d", (int) offset);
2009                             else if (NEGATIVE_BIT_SET)
2010                               func (stream, ", #-0");
2011                           }
2012                         else
2013                           {
2014                             func (stream, ", {%s%d}",
2015                                   (NEGATIVE_BIT_SET && !offset) ? "-" : "",
2016                                   (int) offset);
2017                             value_in_comment = offset;
2018                           }
2019                       }
2020                     if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
2021                       {
2022                         func (stream, "\t; ");
2023                         /* For unaligned PCs, apply off-by-alignment
2024                            correction.  */
2025                         info->print_address_func (offset + pc
2026                                                   + info->bytes_per_chunk * 2
2027                                                   - (pc & 3),
2028                                                   info);
2029                       }
2030                   }
2031                   break;
2032
2033                 case 'B':
2034                   {
2035                     int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
2036                     int offset = (given >> 1) & 0x3f;
2037
2038                     if (offset == 1)
2039                       func (stream, "{d%d}", regno);
2040                     else if (regno + offset > 32)
2041                       func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
2042                     else
2043                       func (stream, "{d%d-d%d}", regno, regno + offset - 1);
2044                   }
2045                   break;
2046
2047                 case 'u':
2048                   if (cond != COND_UNCOND)
2049                     is_unpredictable = TRUE;
2050
2051                   /* Fall through.  */
2052                 case 'c':
2053                   func (stream, "%s", arm_conditional[cond]);
2054                   break;
2055
2056                 case 'I':
2057                   /* Print a Cirrus/DSP shift immediate.  */
2058                   /* Immediates are 7bit signed ints with bits 0..3 in
2059                      bits 0..3 of opcode and bits 4..6 in bits 5..7
2060                      of opcode.  */
2061                   {
2062                     int imm;
2063
2064                     imm = (given & 0xf) | ((given & 0xe0) >> 1);
2065
2066                     /* Is ``imm'' a negative number?  */
2067                     if (imm & 0x40)
2068                       imm |= (-1 << 7);
2069
2070                     func (stream, "%d", imm);
2071                   }
2072
2073                   break;
2074
2075                 case 'F':
2076                   switch (given & 0x00408000)
2077                     {
2078                     case 0:
2079                       func (stream, "4");
2080                       break;
2081                     case 0x8000:
2082                       func (stream, "1");
2083                       break;
2084                     case 0x00400000:
2085                       func (stream, "2");
2086                       break;
2087                     default:
2088                       func (stream, "3");
2089                     }
2090                   break;
2091
2092                 case 'P':
2093                   switch (given & 0x00080080)
2094                     {
2095                     case 0:
2096                       func (stream, "s");
2097                       break;
2098                     case 0x80:
2099                       func (stream, "d");
2100                       break;
2101                     case 0x00080000:
2102                       func (stream, "e");
2103                       break;
2104                     default:
2105                       func (stream, _("<illegal precision>"));
2106                       break;
2107                     }
2108                   break;
2109
2110                 case 'Q':
2111                   switch (given & 0x00408000)
2112                     {
2113                     case 0:
2114                       func (stream, "s");
2115                       break;
2116                     case 0x8000:
2117                       func (stream, "d");
2118                       break;
2119                     case 0x00400000:
2120                       func (stream, "e");
2121                       break;
2122                     default:
2123                       func (stream, "p");
2124                       break;
2125                     }
2126                   break;
2127
2128                 case 'R':
2129                   switch (given & 0x60)
2130                     {
2131                     case 0:
2132                       break;
2133                     case 0x20:
2134                       func (stream, "p");
2135                       break;
2136                     case 0x40:
2137                       func (stream, "m");
2138                       break;
2139                     default:
2140                       func (stream, "z");
2141                       break;
2142                     }
2143                   break;
2144
2145                 case '0': case '1': case '2': case '3': case '4':
2146                 case '5': case '6': case '7': case '8': case '9':
2147                   {
2148                     int width;
2149
2150                     c = arm_decode_bitfield (c, given, &value, &width);
2151
2152                     switch (*c)
2153                       {
2154                       case 'R':
2155                         if (value == 15)
2156                           is_unpredictable = TRUE;
2157                         /* Fall through.  */
2158                       case 'r':
2159                         if (c[1] == 'u')
2160                           {
2161                             /* Eat the 'u' character.  */
2162                             ++ c;
2163
2164                             if (u_reg == value)
2165                               is_unpredictable = TRUE;
2166                             u_reg = value;
2167                           }
2168                         func (stream, "%s", arm_regnames[value]);
2169                         break;
2170                       case 'D':
2171                         func (stream, "d%ld", value);
2172                         break;
2173                       case 'Q':
2174                         if (value & 1)
2175                           func (stream, "<illegal reg q%ld.5>", value >> 1);
2176                         else
2177                           func (stream, "q%ld", value >> 1);
2178                         break;
2179                       case 'd':
2180                         func (stream, "%ld", value);
2181                         value_in_comment = value;
2182                         break;
2183                       case 'k':
2184                         {
2185                           int from = (given & (1 << 7)) ? 32 : 16;
2186                           func (stream, "%ld", from - value);
2187                         }
2188                         break;
2189
2190                       case 'f':
2191                         if (value > 7)
2192                           func (stream, "#%s", arm_fp_const[value & 7]);
2193                         else
2194                           func (stream, "f%ld", value);
2195                         break;
2196
2197                       case 'w':
2198                         if (width == 2)
2199                           func (stream, "%s", iwmmxt_wwnames[value]);
2200                         else
2201                           func (stream, "%s", iwmmxt_wwssnames[value]);
2202                         break;
2203
2204                       case 'g':
2205                         func (stream, "%s", iwmmxt_regnames[value]);
2206                         break;
2207                       case 'G':
2208                         func (stream, "%s", iwmmxt_cregnames[value]);
2209                         break;
2210
2211                       case 'x':
2212                         func (stream, "0x%lx", (value & 0xffffffffUL));
2213                         break;
2214
2215                       case 'c':
2216                         switch (value)
2217                           {
2218                           case 0:
2219                             func (stream, "eq");
2220                             break;
2221
2222                           case 1:
2223                             func (stream, "vs");
2224                             break;
2225
2226                           case 2:
2227                             func (stream, "ge");
2228                             break;
2229
2230                           case 3:
2231                             func (stream, "gt");
2232                             break;
2233
2234                           default:
2235                             func (stream, "??");
2236                             break;
2237                           }
2238                         break;
2239
2240                       case '`':
2241                         c++;
2242                         if (value == 0)
2243                           func (stream, "%c", *c);
2244                         break;
2245                       case '\'':
2246                         c++;
2247                         if (value == ((1ul << width) - 1))
2248                           func (stream, "%c", *c);
2249                         break;
2250                       case '?':
2251                         func (stream, "%c", c[(1 << width) - (int) value]);
2252                         c += 1 << width;
2253                         break;
2254                       default:
2255                         abort ();
2256                       }
2257                     break;
2258
2259                   case 'y':
2260                   case 'z':
2261                     {
2262                       int single = *c++ == 'y';
2263                       int regno;
2264
2265                       switch (*c)
2266                         {
2267                         case '4': /* Sm pair */
2268                         case '0': /* Sm, Dm */
2269                           regno = given & 0x0000000f;
2270                           if (single)
2271                             {
2272                               regno <<= 1;
2273                               regno += (given >> 5) & 1;
2274                             }
2275                           else
2276                             regno += ((given >> 5) & 1) << 4;
2277                           break;
2278
2279                         case '1': /* Sd, Dd */
2280                           regno = (given >> 12) & 0x0000000f;
2281                           if (single)
2282                             {
2283                               regno <<= 1;
2284                               regno += (given >> 22) & 1;
2285                             }
2286                           else
2287                             regno += ((given >> 22) & 1) << 4;
2288                           break;
2289
2290                         case '2': /* Sn, Dn */
2291                           regno = (given >> 16) & 0x0000000f;
2292                           if (single)
2293                             {
2294                               regno <<= 1;
2295                               regno += (given >> 7) & 1;
2296                             }
2297                           else
2298                             regno += ((given >> 7) & 1) << 4;
2299                           break;
2300
2301                         case '3': /* List */
2302                           func (stream, "{");
2303                           regno = (given >> 12) & 0x0000000f;
2304                           if (single)
2305                             {
2306                               regno <<= 1;
2307                               regno += (given >> 22) & 1;
2308                             }
2309                           else
2310                             regno += ((given >> 22) & 1) << 4;
2311                           break;
2312
2313                         default:
2314                           abort ();
2315                         }
2316
2317                       func (stream, "%c%d", single ? 's' : 'd', regno);
2318
2319                       if (*c == '3')
2320                         {
2321                           int count = given & 0xff;
2322
2323                           if (single == 0)
2324                             count >>= 1;
2325
2326                           if (--count)
2327                             {
2328                               func (stream, "-%c%d",
2329                                     single ? 's' : 'd',
2330                                     regno + count);
2331                             }
2332
2333                           func (stream, "}");
2334                         }
2335                       else if (*c == '4')
2336                         func (stream, ", %c%d", single ? 's' : 'd',
2337                               regno + 1);
2338                     }
2339                     break;
2340
2341                   case 'L':
2342                     switch (given & 0x00400100)
2343                       {
2344                       case 0x00000000: func (stream, "b"); break;
2345                       case 0x00400000: func (stream, "h"); break;
2346                       case 0x00000100: func (stream, "w"); break;
2347                       case 0x00400100: func (stream, "d"); break;
2348                       default:
2349                         break;
2350                       }
2351                     break;
2352
2353                   case 'Z':
2354                     {
2355                       /* given (20, 23) | given (0, 3) */
2356                       value = ((given >> 16) & 0xf0) | (given & 0xf);
2357                       func (stream, "%d", (int) value);
2358                     }
2359                     break;
2360
2361                   case 'l':
2362                     /* This is like the 'A' operator, except that if
2363                        the width field "M" is zero, then the offset is
2364                        *not* multiplied by four.  */
2365                     {
2366                       int offset = given & 0xff;
2367                       int multiplier = (given & 0x00000100) ? 4 : 1;
2368
2369                       func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
2370
2371                       if (multiplier > 1)
2372                         {
2373                           value_in_comment = offset * multiplier;
2374                           if (NEGATIVE_BIT_SET)
2375                             value_in_comment = - value_in_comment;
2376                         }
2377
2378                       if (offset)
2379                         {
2380                           if (PRE_BIT_SET)
2381                             func (stream, ", #%s%d]%s",
2382                                   NEGATIVE_BIT_SET ? "-" : "",
2383                                   offset * multiplier,
2384                                   WRITEBACK_BIT_SET ? "!" : "");
2385                           else
2386                             func (stream, "], #%s%d",
2387                                   NEGATIVE_BIT_SET ? "-" : "",
2388                                   offset * multiplier);
2389                         }
2390                       else
2391                         func (stream, "]");
2392                     }
2393                     break;
2394
2395                   case 'r':
2396                     {
2397                       int imm4 = (given >> 4) & 0xf;
2398                       int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
2399                       int ubit = ! NEGATIVE_BIT_SET;
2400                       const char *rm = arm_regnames [given & 0xf];
2401                       const char *rn = arm_regnames [(given >> 16) & 0xf];
2402
2403                       switch (puw_bits)
2404                         {
2405                         case 1:
2406                         case 3:
2407                           func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
2408                           if (imm4)
2409                             func (stream, ", lsl #%d", imm4);
2410                           break;
2411
2412                         case 4:
2413                         case 5:
2414                         case 6:
2415                         case 7:
2416                           func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
2417                           if (imm4 > 0)
2418                             func (stream, ", lsl #%d", imm4);
2419                           func (stream, "]");
2420                           if (puw_bits == 5 || puw_bits == 7)
2421                             func (stream, "!");
2422                           break;
2423
2424                         default:
2425                           func (stream, "INVALID");
2426                         }
2427                     }
2428                     break;
2429
2430                   case 'i':
2431                     {
2432                       long imm5;
2433                       imm5 = ((given & 0x100) >> 4) | (given & 0xf);
2434                       func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
2435                     }
2436                     break;
2437
2438                   default:
2439                     abort ();
2440                   }
2441                 }
2442             }
2443           else
2444             func (stream, "%c", *c);
2445         }
2446
2447       if (value_in_comment > 32 || value_in_comment < -16)
2448         func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
2449
2450       if (is_unpredictable)
2451         func (stream, UNPREDICTABLE_INSTRUCTION);
2452
2453       return TRUE;
2454     }
2455   return FALSE;
2456 }
2457
2458 /* Decodes and prints ARM addressing modes.  Returns the offset
2459    used in the address, if any, if it is worthwhile printing the
2460    offset as a hexadecimal value in a comment at the end of the
2461    line of disassembly.  */
2462
2463 static signed long
2464 print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
2465 {
2466   void *stream = info->stream;
2467   fprintf_ftype func = info->fprintf_func;
2468   bfd_vma offset = 0;
2469
2470   if (((given & 0x000f0000) == 0x000f0000)
2471       && ((given & 0x02000000) == 0))
2472     {
2473       offset = given & 0xfff;
2474
2475       func (stream, "[pc");
2476
2477       if (PRE_BIT_SET)
2478         {
2479           /* Pre-indexed.  Elide offset of positive zero when
2480              non-writeback.  */
2481           if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
2482             func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
2483
2484           if (NEGATIVE_BIT_SET)
2485             offset = -offset;
2486
2487           offset += pc + 8;
2488
2489           /* Cope with the possibility of write-back
2490              being used.  Probably a very dangerous thing
2491              for the programmer to do, but who are we to
2492              argue ?  */
2493           func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : "");
2494         }
2495       else  /* Post indexed.  */
2496         {
2497           func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
2498
2499           /* Ie ignore the offset.  */
2500           offset = pc + 8;
2501         }
2502
2503       func (stream, "\t; ");
2504       info->print_address_func (offset, info);
2505       offset = 0;
2506     }
2507   else
2508     {
2509       func (stream, "[%s",
2510             arm_regnames[(given >> 16) & 0xf]);
2511
2512       if (PRE_BIT_SET)
2513         {
2514           if ((given & 0x02000000) == 0)
2515             {
2516               /* Elide offset of positive zero when non-writeback.  */
2517               offset = given & 0xfff;
2518               if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
2519                 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
2520             }
2521           else
2522             {
2523               func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : "");
2524               arm_decode_shift (given, func, stream, TRUE);
2525             }
2526
2527           func (stream, "]%s",
2528                 WRITEBACK_BIT_SET ? "!" : "");
2529         }
2530       else
2531         {
2532           if ((given & 0x02000000) == 0)
2533             {
2534               /* Always show offset.  */
2535               offset = given & 0xfff;
2536               func (stream, "], #%s%d",
2537                     NEGATIVE_BIT_SET ? "-" : "", (int) offset);
2538             }
2539           else
2540             {
2541               func (stream, "], %s",
2542                     NEGATIVE_BIT_SET ? "-" : "");
2543               arm_decode_shift (given, func, stream, TRUE);
2544             }
2545         }
2546     }
2547
2548   return (signed long) offset;
2549 }
2550
2551 /* Print one neon instruction on INFO->STREAM.
2552    Return TRUE if the instuction matched, FALSE if this is not a
2553    recognised neon instruction.  */
2554
2555 static bfd_boolean
2556 print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
2557 {
2558   const struct opcode32 *insn;
2559   void *stream = info->stream;
2560   fprintf_ftype func = info->fprintf_func;
2561
2562   if (thumb)
2563     {
2564       if ((given & 0xef000000) == 0xef000000)
2565         {
2566           /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding.  */
2567           unsigned long bit28 = given & (1 << 28);
2568
2569           given &= 0x00ffffff;
2570           if (bit28)
2571             given |= 0xf3000000;
2572           else
2573             given |= 0xf2000000;
2574         }
2575       else if ((given & 0xff000000) == 0xf9000000)
2576         given ^= 0xf9000000 ^ 0xf4000000;
2577       else
2578         return FALSE;
2579     }
2580
2581   for (insn = neon_opcodes; insn->assembler; insn++)
2582     {
2583       if ((given & insn->mask) == insn->value)
2584         {
2585           signed long value_in_comment = 0;
2586           bfd_boolean is_unpredictable = FALSE;
2587           const char *c;
2588
2589           for (c = insn->assembler; *c; c++)
2590             {
2591               if (*c == '%')
2592                 {
2593                   switch (*++c)
2594                     {
2595                     case '%':
2596                       func (stream, "%%");
2597                       break;
2598
2599                     case 'u':
2600                       if (thumb && ifthen_state)
2601                         is_unpredictable = TRUE;
2602
2603                       /* Fall through.  */
2604                     case 'c':
2605                       if (thumb && ifthen_state)
2606                         func (stream, "%s", arm_conditional[IFTHEN_COND]);
2607                       break;
2608
2609                     case 'A':
2610                       {
2611                         static const unsigned char enc[16] =
2612                         {
2613                           0x4, 0x14, /* st4 0,1 */
2614                           0x4, /* st1 2 */
2615                           0x4, /* st2 3 */
2616                           0x3, /* st3 4 */
2617                           0x13, /* st3 5 */
2618                           0x3, /* st1 6 */
2619                           0x1, /* st1 7 */
2620                           0x2, /* st2 8 */
2621                           0x12, /* st2 9 */
2622                           0x2, /* st1 10 */
2623                           0, 0, 0, 0, 0
2624                         };
2625                         int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
2626                         int rn = ((given >> 16) & 0xf);
2627                         int rm = ((given >> 0) & 0xf);
2628                         int align = ((given >> 4) & 0x3);
2629                         int type = ((given >> 8) & 0xf);
2630                         int n = enc[type] & 0xf;
2631                         int stride = (enc[type] >> 4) + 1;
2632                         int ix;
2633
2634                         func (stream, "{");
2635                         if (stride > 1)
2636                           for (ix = 0; ix != n; ix++)
2637                             func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
2638                         else if (n == 1)
2639                           func (stream, "d%d", rd);
2640                         else
2641                           func (stream, "d%d-d%d", rd, rd + n - 1);
2642                         func (stream, "}, [%s", arm_regnames[rn]);
2643                         if (align)
2644                           func (stream, " :%d", 32 << align);
2645                         func (stream, "]");
2646                         if (rm == 0xd)
2647                           func (stream, "!");
2648                         else if (rm != 0xf)
2649                           func (stream, ", %s", arm_regnames[rm]);
2650                       }
2651                       break;
2652
2653                     case 'B':
2654                       {
2655                         int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
2656                         int rn = ((given >> 16) & 0xf);
2657                         int rm = ((given >> 0) & 0xf);
2658                         int idx_align = ((given >> 4) & 0xf);
2659                         int align = 0;
2660                         int size = ((given >> 10) & 0x3);
2661                         int idx = idx_align >> (size + 1);
2662                         int length = ((given >> 8) & 3) + 1;
2663                         int stride = 1;
2664                         int i;
2665
2666                         if (length > 1 && size > 0)
2667                           stride = (idx_align & (1 << size)) ? 2 : 1;
2668
2669                         switch (length)
2670                           {
2671                           case 1:
2672                             {
2673                               int amask = (1 << size) - 1;
2674                               if ((idx_align & (1 << size)) != 0)
2675                                 return FALSE;
2676                               if (size > 0)
2677                                 {
2678                                   if ((idx_align & amask) == amask)
2679                                     align = 8 << size;
2680                                   else if ((idx_align & amask) != 0)
2681                                     return FALSE;
2682                                 }
2683                               }
2684                             break;
2685
2686                           case 2:
2687                             if (size == 2 && (idx_align & 2) != 0)
2688                               return FALSE;
2689                             align = (idx_align & 1) ? 16 << size : 0;
2690                             break;
2691
2692                           case 3:
2693                             if ((size == 2 && (idx_align & 3) != 0)
2694                                 || (idx_align & 1) != 0)
2695                               return FALSE;
2696                             break;
2697
2698                           case 4:
2699                             if (size == 2)
2700                               {
2701                                 if ((idx_align & 3) == 3)
2702                                   return FALSE;
2703                                 align = (idx_align & 3) * 64;
2704                               }
2705                             else
2706                               align = (idx_align & 1) ? 32 << size : 0;
2707                             break;
2708
2709                           default:
2710                             abort ();
2711                           }
2712
2713                         func (stream, "{");
2714                         for (i = 0; i < length; i++)
2715                           func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
2716                             rd + i * stride, idx);
2717                         func (stream, "}, [%s", arm_regnames[rn]);
2718                         if (align)
2719                           func (stream, " :%d", align);
2720                         func (stream, "]");
2721                         if (rm == 0xd)
2722                           func (stream, "!");
2723                         else if (rm != 0xf)
2724                           func (stream, ", %s", arm_regnames[rm]);
2725                       }
2726                       break;
2727
2728                     case 'C':
2729                       {
2730                         int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
2731                         int rn = ((given >> 16) & 0xf);
2732                         int rm = ((given >> 0) & 0xf);
2733                         int align = ((given >> 4) & 0x1);
2734                         int size = ((given >> 6) & 0x3);
2735                         int type = ((given >> 8) & 0x3);
2736                         int n = type + 1;
2737                         int stride = ((given >> 5) & 0x1);
2738                         int ix;
2739
2740                         if (stride && (n == 1))
2741                           n++;
2742                         else
2743                           stride++;
2744
2745                         func (stream, "{");
2746                         if (stride > 1)
2747                           for (ix = 0; ix != n; ix++)
2748                             func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
2749                         else if (n == 1)
2750                           func (stream, "d%d[]", rd);
2751                         else
2752                           func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
2753                         func (stream, "}, [%s", arm_regnames[rn]);
2754                         if (align)
2755                           {
2756                             align = (8 * (type + 1)) << size;
2757                             if (type == 3)
2758                               align = (size > 1) ? align >> 1 : align;
2759                             if (type == 2 || (type == 0 && !size))
2760                               func (stream, " :<bad align %d>", align);
2761                             else
2762                               func (stream, " :%d", align);
2763                           }
2764                         func (stream, "]");
2765                         if (rm == 0xd)
2766                           func (stream, "!");
2767                         else if (rm != 0xf)
2768                           func (stream, ", %s", arm_regnames[rm]);
2769                       }
2770                       break;
2771
2772                     case 'D':
2773                       {
2774                         int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
2775                         int size = (given >> 20) & 3;
2776                         int reg = raw_reg & ((4 << size) - 1);
2777                         int ix = raw_reg >> size >> 2;
2778
2779                         func (stream, "d%d[%d]", reg, ix);
2780                       }
2781                       break;
2782
2783                     case 'E':
2784                       /* Neon encoded constant for mov, mvn, vorr, vbic.  */
2785                       {
2786                         int bits = 0;
2787                         int cmode = (given >> 8) & 0xf;
2788                         int op = (given >> 5) & 0x1;
2789                         unsigned long value = 0, hival = 0;
2790                         unsigned shift;
2791                         int size = 0;
2792                         int isfloat = 0;
2793
2794                         bits |= ((given >> 24) & 1) << 7;
2795                         bits |= ((given >> 16) & 7) << 4;
2796                         bits |= ((given >> 0) & 15) << 0;
2797
2798                         if (cmode < 8)
2799                           {
2800                             shift = (cmode >> 1) & 3;
2801                             value = (unsigned long) bits << (8 * shift);
2802                             size = 32;
2803                           }
2804                         else if (cmode < 12)
2805                           {
2806                             shift = (cmode >> 1) & 1;
2807                             value = (unsigned long) bits << (8 * shift);
2808                             size = 16;
2809                           }
2810                         else if (cmode < 14)
2811                           {
2812                             shift = (cmode & 1) + 1;
2813                             value = (unsigned long) bits << (8 * shift);
2814                             value |= (1ul << (8 * shift)) - 1;
2815                             size = 32;
2816                           }
2817                         else if (cmode == 14)
2818                           {
2819                             if (op)
2820                               {
2821                                 /* Bit replication into bytes.  */
2822                                 int ix;
2823                                 unsigned long mask;
2824
2825                                 value = 0;
2826                                 hival = 0;
2827                                 for (ix = 7; ix >= 0; ix--)
2828                                   {
2829                                     mask = ((bits >> ix) & 1) ? 0xff : 0;
2830                                     if (ix <= 3)
2831                                       value = (value << 8) | mask;
2832                                     else
2833                                       hival = (hival << 8) | mask;
2834                                   }
2835                                 size = 64;
2836                               }
2837                             else
2838                               {
2839                                 /* Byte replication.  */
2840                                 value = (unsigned long) bits;
2841                                 size = 8;
2842                               }
2843                           }
2844                         else if (!op)
2845                           {
2846                             /* Floating point encoding.  */
2847                             int tmp;
2848
2849                             value = (unsigned long)  (bits & 0x7f) << 19;
2850                             value |= (unsigned long) (bits & 0x80) << 24;
2851                             tmp = bits & 0x40 ? 0x3c : 0x40;
2852                             value |= (unsigned long) tmp << 24;
2853                             size = 32;
2854                             isfloat = 1;
2855                           }
2856                         else
2857                           {
2858                             func (stream, "<illegal constant %.8x:%x:%x>",
2859                                   bits, cmode, op);
2860                             size = 32;
2861                             break;
2862                           }
2863                         switch (size)
2864                           {
2865                           case 8:
2866                             func (stream, "#%ld\t; 0x%.2lx", value, value);
2867                             break;
2868
2869                           case 16:
2870                             func (stream, "#%ld\t; 0x%.4lx", value, value);
2871                             break;
2872
2873                           case 32:
2874                             if (isfloat)
2875                               {
2876                                 unsigned char valbytes[4];
2877                                 double fvalue;
2878
2879                                 /* Do this a byte at a time so we don't have to
2880                                    worry about the host's endianness.  */
2881                                 valbytes[0] = value & 0xff;
2882                                 valbytes[1] = (value >> 8) & 0xff;
2883                                 valbytes[2] = (value >> 16) & 0xff;
2884                                 valbytes[3] = (value >> 24) & 0xff;
2885
2886                                 floatformat_to_double
2887                                   (& floatformat_ieee_single_little, valbytes,
2888                                   & fvalue);
2889
2890                                 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
2891                                       value);
2892                               }
2893                             else
2894                               func (stream, "#%ld\t; 0x%.8lx",
2895                                     (long) (((value & 0x80000000L) != 0)
2896                                             ? value | ~0xffffffffL : value),
2897                                     value);
2898                             break;
2899
2900                           case 64:
2901                             func (stream, "#0x%.8lx%.8lx", hival, value);
2902                             break;
2903
2904                           default:
2905                             abort ();
2906                           }
2907                       }
2908                       break;
2909
2910                     case 'F':
2911                       {
2912                         int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
2913                         int num = (given >> 8) & 0x3;
2914
2915                         if (!num)
2916                           func (stream, "{d%d}", regno);
2917                         else if (num + regno >= 32)
2918                           func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
2919                         else
2920                           func (stream, "{d%d-d%d}", regno, regno + num);
2921                       }
2922                       break;
2923
2924
2925                     case '0': case '1': case '2': case '3': case '4':
2926                     case '5': case '6': case '7': case '8': case '9':
2927                       {
2928                         int width;
2929                         unsigned long value;
2930
2931                         c = arm_decode_bitfield (c, given, &value, &width);
2932
2933                         switch (*c)
2934                           {
2935                           case 'r':
2936                             func (stream, "%s", arm_regnames[value]);
2937                             break;
2938                           case 'd':
2939                             func (stream, "%ld", value);
2940                             value_in_comment = value;
2941                             break;
2942                           case 'e':
2943                             func (stream, "%ld", (1ul << width) - value);
2944                             break;
2945
2946                           case 'S':
2947                           case 'T':
2948                           case 'U':
2949                             /* Various width encodings.  */
2950                             {
2951                               int base = 8 << (*c - 'S'); /* 8,16 or 32 */
2952                               int limit;
2953                               unsigned low, high;
2954
2955                               c++;
2956                               if (*c >= '0' && *c <= '9')
2957                                 limit = *c - '0';
2958                               else if (*c >= 'a' && *c <= 'f')
2959                                 limit = *c - 'a' + 10;
2960                               else
2961                                 abort ();
2962                               low = limit >> 2;
2963                               high = limit & 3;
2964
2965                               if (value < low || value > high)
2966                                 func (stream, "<illegal width %d>", base << value);
2967                               else
2968                                 func (stream, "%d", base << value);
2969                             }
2970                             break;
2971                           case 'R':
2972                             if (given & (1 << 6))
2973                               goto Q;
2974                             /* FALLTHROUGH */
2975                           case 'D':
2976                             func (stream, "d%ld", value);
2977                             break;
2978                           case 'Q':
2979                           Q:
2980                             if (value & 1)
2981                               func (stream, "<illegal reg q%ld.5>", value >> 1);
2982                             else
2983                               func (stream, "q%ld", value >> 1);
2984                             break;
2985
2986                           case '`':
2987                             c++;
2988                             if (value == 0)
2989                               func (stream, "%c", *c);
2990                             break;
2991                           case '\'':
2992                             c++;
2993                             if (value == ((1ul << width) - 1))
2994                               func (stream, "%c", *c);
2995                             break;
2996                           case '?':
2997                             func (stream, "%c", c[(1 << width) - (int) value]);
2998                             c += 1 << width;
2999                             break;
3000                           default:
3001                             abort ();
3002                           }
3003                         break;
3004
3005                       default:
3006                         abort ();
3007                       }
3008                     }
3009                 }
3010               else
3011                 func (stream, "%c", *c);
3012             }
3013
3014           if (value_in_comment > 32 || value_in_comment < -16)
3015             func (stream, "\t; 0x%lx", value_in_comment);
3016
3017           if (is_unpredictable)
3018             func (stream, UNPREDICTABLE_INSTRUCTION);
3019
3020           return TRUE;
3021         }
3022     }
3023   return FALSE;
3024 }
3025
3026 /* Return the name of a v7A special register.  */
3027
3028 static const char *
3029 banked_regname (unsigned reg)
3030 {
3031   switch (reg)
3032     {
3033       case 15: return "CPSR";
3034       case 32: return "R8_usr";
3035       case 33: return "R9_usr";
3036       case 34: return "R10_usr";
3037       case 35: return "R11_usr";
3038       case 36: return "R12_usr";
3039       case 37: return "SP_usr";
3040       case 38: return "LR_usr";
3041       case 40: return "R8_fiq";
3042       case 41: return "R9_fiq";
3043       case 42: return "R10_fiq";
3044       case 43: return "R11_fiq";
3045       case 44: return "R12_fiq";
3046       case 45: return "SP_fiq";
3047       case 46: return "LR_fiq";
3048       case 48: return "LR_irq";
3049       case 49: return "SP_irq";
3050       case 50: return "LR_svc";
3051       case 51: return "SP_svc";
3052       case 52: return "LR_abt";
3053       case 53: return "SP_abt";
3054       case 54: return "LR_und";
3055       case 55: return "SP_und";
3056       case 60: return "LR_mon";
3057       case 61: return "SP_mon";
3058       case 62: return "ELR_hyp";
3059       case 63: return "SP_hyp";
3060       case 79: return "SPSR";
3061       case 110: return "SPSR_fiq";
3062       case 112: return "SPSR_irq";
3063       case 114: return "SPSR_svc";
3064       case 116: return "SPSR_abt";
3065       case 118: return "SPSR_und";
3066       case 124: return "SPSR_mon";
3067       case 126: return "SPSR_hyp";
3068       default: return NULL;
3069     }
3070 }
3071
3072 /* Return the name of the DMB/DSB option.  */
3073 static const char *
3074 data_barrier_option (unsigned option)
3075 {
3076   switch (option & 0xf)
3077     {
3078     case 0xf: return "sy";
3079     case 0xe: return "st";
3080     case 0xd: return "ld";
3081     case 0xb: return "ish";
3082     case 0xa: return "ishst";
3083     case 0x9: return "ishld";
3084     case 0x7: return "un";
3085     case 0x6: return "unst";
3086     case 0x5: return "nshld";
3087     case 0x3: return "osh";
3088     case 0x2: return "oshst";
3089     case 0x1: return "oshld";
3090     default:  return NULL;
3091     }
3092 }
3093
3094 /* Print one ARM instruction from PC on INFO->STREAM.  */
3095
3096 static void
3097 print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
3098 {
3099   const struct opcode32 *insn;
3100   void *stream = info->stream;
3101   fprintf_ftype func = info->fprintf_func;
3102   struct arm_private_data *private_data = info->private_data;
3103
3104   if (print_insn_coprocessor (pc, info, given, FALSE))
3105     return;
3106
3107   if (print_insn_neon (info, given, FALSE))
3108     return;
3109
3110   for (insn = arm_opcodes; insn->assembler; insn++)
3111     {
3112       if ((given & insn->mask) != insn->value)
3113         continue;
3114
3115       if ((insn->arch & private_data->features.core) == 0)
3116         continue;
3117
3118       /* Special case: an instruction with all bits set in the condition field
3119          (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
3120          or by the catchall at the end of the table.  */
3121       if ((given & 0xF0000000) != 0xF0000000
3122           || (insn->mask & 0xF0000000) == 0xF0000000
3123           || (insn->mask == 0 && insn->value == 0))
3124         {
3125           unsigned long u_reg = 16;
3126           unsigned long U_reg = 16;
3127           bfd_boolean is_unpredictable = FALSE;
3128           signed long value_in_comment = 0;
3129           const char *c;
3130
3131           for (c = insn->assembler; *c; c++)
3132             {
3133               if (*c == '%')
3134                 {
3135                   bfd_boolean allow_unpredictable = FALSE;
3136
3137                   switch (*++c)
3138                     {
3139                     case '%':
3140                       func (stream, "%%");
3141                       break;
3142
3143                     case 'a':
3144                       value_in_comment = print_arm_address (pc, info, given);
3145                       break;
3146
3147                     case 'P':
3148                       /* Set P address bit and use normal address
3149                          printing routine.  */
3150                       value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
3151                       break;
3152
3153                     case 'S':
3154                       allow_unpredictable = TRUE;
3155                     case 's':
3156                       if ((given & 0x004f0000) == 0x004f0000)
3157                         {
3158                           /* PC relative with immediate offset.  */
3159                           bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
3160
3161                           if (PRE_BIT_SET)
3162                             {
3163                               /* Elide positive zero offset.  */
3164                               if (offset || NEGATIVE_BIT_SET)
3165                                 func (stream, "[pc, #%s%d]\t; ",
3166                                       NEGATIVE_BIT_SET ? "-" : "", (int) offset);
3167                               else
3168                                 func (stream, "[pc]\t; ");
3169                               if (NEGATIVE_BIT_SET)
3170                                 offset = -offset;
3171                               info->print_address_func (offset + pc + 8, info);
3172                             }
3173                           else
3174                             {
3175                               /* Always show the offset.  */
3176                               func (stream, "[pc], #%s%d",
3177                                     NEGATIVE_BIT_SET ? "-" : "", (int) offset);
3178                               if (! allow_unpredictable)
3179                                 is_unpredictable = TRUE;
3180                             }
3181                         }
3182                       else
3183                         {
3184                           int offset = ((given & 0xf00) >> 4) | (given & 0xf);
3185
3186                           func (stream, "[%s",
3187                                 arm_regnames[(given >> 16) & 0xf]);
3188
3189                           if (PRE_BIT_SET)
3190                             {
3191                               if (IMMEDIATE_BIT_SET)
3192                                 {
3193                                   /* Elide offset for non-writeback
3194                                      positive zero.  */
3195                                   if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
3196                                       || offset)
3197                                     func (stream, ", #%s%d",
3198                                           NEGATIVE_BIT_SET ? "-" : "", offset);
3199
3200                                   if (NEGATIVE_BIT_SET)
3201                                     offset = -offset;
3202
3203                                   value_in_comment = offset;
3204                                 }
3205                               else
3206                                 {
3207                                   /* Register Offset or Register Pre-Indexed.  */
3208                                   func (stream, ", %s%s",
3209                                         NEGATIVE_BIT_SET ? "-" : "",
3210                                         arm_regnames[given & 0xf]);
3211
3212                                   /* Writing back to the register that is the source/
3213                                      destination of the load/store is unpredictable.  */
3214                                   if (! allow_unpredictable
3215                                       && WRITEBACK_BIT_SET
3216                                       && ((given & 0xf) == ((given >> 12) & 0xf)))
3217                                     is_unpredictable = TRUE;
3218                                 }
3219
3220                               func (stream, "]%s",
3221                                     WRITEBACK_BIT_SET ? "!" : "");
3222                             }
3223                           else
3224                             {
3225                               if (IMMEDIATE_BIT_SET)
3226                                 {
3227                                   /* Immediate Post-indexed.  */
3228                                   /* PR 10924: Offset must be printed, even if it is zero.  */
3229                                   func (stream, "], #%s%d",
3230                                         NEGATIVE_BIT_SET ? "-" : "", offset);
3231                                   if (NEGATIVE_BIT_SET)
3232                                     offset = -offset;
3233                                   value_in_comment = offset;
3234                                 }
3235                               else
3236                                 {
3237                                   /* Register Post-indexed.  */
3238                                   func (stream, "], %s%s",
3239                                         NEGATIVE_BIT_SET ? "-" : "",
3240                                         arm_regnames[given & 0xf]);
3241
3242                                   /* Writing back to the register that is the source/
3243                                      destination of the load/store is unpredictable.  */
3244                                   if (! allow_unpredictable
3245                                       && (given & 0xf) == ((given >> 12) & 0xf))
3246                                     is_unpredictable = TRUE;
3247                                 }
3248
3249                               if (! allow_unpredictable)
3250                                 {
3251                                   /* Writeback is automatically implied by post- addressing.
3252                                      Setting the W bit is unnecessary and ARM specify it as
3253                                      being unpredictable.  */
3254                                   if (WRITEBACK_BIT_SET
3255                                       /* Specifying the PC register as the post-indexed
3256                                          registers is also unpredictable.  */
3257                                       || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
3258                                     is_unpredictable = TRUE;
3259                                 }
3260                             }
3261                         }
3262                       break;
3263
3264                     case 'b':
3265                       {
3266                         bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
3267                         info->print_address_func (disp * 4 + pc + 8, info);
3268                       }
3269                       break;
3270
3271                     case 'c':
3272                       if (((given >> 28) & 0xf) != 0xe)
3273                         func (stream, "%s",
3274                               arm_conditional [(given >> 28) & 0xf]);
3275                       break;
3276
3277                     case 'm':
3278                       {
3279                         int started = 0;
3280                         int reg;
3281
3282                         func (stream, "{");
3283                         for (reg = 0; reg < 16; reg++)
3284                           if ((given & (1 << reg)) != 0)
3285                             {
3286                               if (started)
3287                                 func (stream, ", ");
3288                               started = 1;
3289                               func (stream, "%s", arm_regnames[reg]);
3290                             }
3291                         func (stream, "}");
3292                         if (! started)
3293                           is_unpredictable = TRUE;
3294                       }
3295                       break;
3296
3297                     case 'q':
3298                       arm_decode_shift (given, func, stream, FALSE);
3299                       break;
3300
3301                     case 'o':
3302                       if ((given & 0x02000000) != 0)
3303                         {
3304                           unsigned int rotate = (given & 0xf00) >> 7;
3305                           unsigned int immed = (given & 0xff);
3306                           unsigned int a, i;
3307
3308                           a = (((immed << (32 - rotate))
3309                                 | (immed >> rotate)) & 0xffffffff);
3310                           /* If there is another encoding with smaller rotate,
3311                              the rotate should be specified directly.  */
3312                           for (i = 0; i < 32; i += 2)
3313                             if ((a << i | a >> (32 - i)) <= 0xff)
3314                               break;
3315
3316                           if (i != rotate)
3317                             func (stream, "#%d, %d", immed, rotate);
3318                           else
3319                             func (stream, "#%d", a);
3320                           value_in_comment = a;
3321                         }
3322                       else
3323                         arm_decode_shift (given, func, stream, TRUE);
3324                       break;
3325
3326                     case 'p':
3327                       if ((given & 0x0000f000) == 0x0000f000)
3328                         {
3329                           /* The p-variants of tst/cmp/cmn/teq are the pre-V6
3330                              mechanism for setting PSR flag bits.  They are
3331                              obsolete in V6 onwards.  */
3332                           if ((private_data->features.core & ARM_EXT_V6) == 0)
3333                             func (stream, "p");
3334                         }
3335                       break;
3336
3337                     case 't':
3338                       if ((given & 0x01200000) == 0x00200000)
3339                         func (stream, "t");
3340                       break;
3341
3342                     case 'A':
3343                       {
3344                         int offset = given & 0xff;
3345
3346                         value_in_comment = offset * 4;
3347                         if (NEGATIVE_BIT_SET)
3348                           value_in_comment = - value_in_comment;
3349
3350                         func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
3351
3352                         if (PRE_BIT_SET)
3353                           {
3354                             if (offset)
3355                               func (stream, ", #%d]%s",
3356                                     (int) value_in_comment,
3357                                     WRITEBACK_BIT_SET ? "!" : "");
3358                             else
3359                               func (stream, "]");
3360                           }
3361                         else
3362                           {
3363                             func (stream, "]");
3364
3365                             if (WRITEBACK_BIT_SET)
3366                               {
3367                                 if (offset)
3368                                   func (stream, ", #%d", (int) value_in_comment);
3369                               }
3370                             else
3371                               {
3372                                 func (stream, ", {%d}", (int) offset);
3373                                 value_in_comment = offset;
3374                               }
3375                           }
3376                       }
3377                       break;
3378
3379                     case 'B':
3380                       /* Print ARM V5 BLX(1) address: pc+25 bits.  */
3381                       {
3382                         bfd_vma address;
3383                         bfd_vma offset = 0;
3384
3385                         if (! NEGATIVE_BIT_SET)
3386                           /* Is signed, hi bits should be ones.  */
3387                           offset = (-1) ^ 0x00ffffff;
3388
3389                         /* Offset is (SignExtend(offset field)<<2).  */
3390                         offset += given & 0x00ffffff;
3391                         offset <<= 2;
3392                         address = offset + pc + 8;
3393
3394                         if (given & 0x01000000)
3395                           /* H bit allows addressing to 2-byte boundaries.  */
3396                           address += 2;
3397
3398                         info->print_address_func (address, info);
3399                       }
3400                       break;
3401
3402                     case 'C':
3403                       if ((given & 0x02000200) == 0x200)
3404                         {
3405                           const char * name;
3406                           unsigned sysm = (given & 0x004f0000) >> 16;
3407
3408                           sysm |= (given & 0x300) >> 4;
3409                           name = banked_regname (sysm);
3410
3411                           if (name != NULL)
3412                             func (stream, "%s", name);
3413                           else
3414                             func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
3415                         }
3416                       else
3417                         {
3418                           func (stream, "%cPSR_",
3419                                 (given & 0x00400000) ? 'S' : 'C');
3420                           if (given & 0x80000)
3421                             func (stream, "f");
3422                           if (given & 0x40000)
3423                             func (stream, "s");
3424                           if (given & 0x20000)
3425                             func (stream, "x");
3426                           if (given & 0x10000)
3427                             func (stream, "c");
3428                         }
3429                       break;
3430
3431                     case 'U':
3432                       if ((given & 0xf0) == 0x60)
3433                         {
3434                           switch (given & 0xf)
3435                             {
3436                             case 0xf: func (stream, "sy"); break;
3437                             default:
3438                               func (stream, "#%d", (int) given & 0xf);
3439                               break;
3440                             }
3441                         }
3442                       else
3443                         {
3444                           const char * opt = data_barrier_option (given & 0xf);
3445                           if (opt != NULL)
3446                             func (stream, "%s", opt);
3447                           else
3448                               func (stream, "#%d", (int) given & 0xf);
3449                         }
3450                       break;
3451
3452                     case '0': case '1': case '2': case '3': case '4':
3453                     case '5': case '6': case '7': case '8': case '9':
3454                       {
3455                         int width;
3456                         unsigned long value;
3457
3458                         c = arm_decode_bitfield (c, given, &value, &width);
3459
3460                         switch (*c)
3461                           {
3462                           case 'R':
3463                             if (value == 15)
3464                               is_unpredictable = TRUE;
3465                             /* Fall through.  */
3466                           case 'r':
3467                           case 'T':
3468                             /* We want register + 1 when decoding T.  */
3469                             if (*c == 'T')
3470                               ++value;
3471
3472                             if (c[1] == 'u')
3473                               {
3474                                 /* Eat the 'u' character.  */
3475                                 ++ c;
3476
3477                                 if (u_reg == value)
3478                                   is_unpredictable = TRUE;
3479                                 u_reg = value;
3480                               }
3481                             if (c[1] == 'U')
3482                               {
3483                                 /* Eat the 'U' character.  */
3484                                 ++ c;
3485
3486                                 if (U_reg == value)
3487                                   is_unpredictable = TRUE;
3488                                 U_reg = value;
3489                               }
3490                             func (stream, "%s", arm_regnames[value]);
3491                             break;
3492                           case 'd':
3493                             func (stream, "%ld", value);
3494                             value_in_comment = value;
3495                             break;
3496                           case 'b':
3497                             func (stream, "%ld", value * 8);
3498                             value_in_comment = value * 8;
3499                             break;
3500                           case 'W':
3501                             func (stream, "%ld", value + 1);
3502                             value_in_comment = value + 1;
3503                             break;
3504                           case 'x':
3505                             func (stream, "0x%08lx", value);
3506
3507                             /* Some SWI instructions have special
3508                                meanings.  */
3509                             if ((given & 0x0fffffff) == 0x0FF00000)
3510                               func (stream, "\t; IMB");
3511                             else if ((given & 0x0fffffff) == 0x0FF00001)
3512                               func (stream, "\t; IMBRange");
3513                             break;
3514                           case 'X':
3515                             func (stream, "%01lx", value & 0xf);
3516                             value_in_comment = value;
3517                             break;
3518                           case '`':
3519                             c++;
3520                             if (value == 0)
3521                               func (stream, "%c", *c);
3522                             break;
3523                           case '\'':
3524                             c++;
3525                             if (value == ((1ul << width) - 1))
3526                               func (stream, "%c", *c);
3527                             break;
3528                           case '?':
3529                             func (stream, "%c", c[(1 << width) - (int) value]);
3530                             c += 1 << width;
3531                             break;
3532                           default:
3533                             abort ();
3534                           }
3535                         break;
3536
3537                       case 'e':
3538                         {
3539                           int imm;
3540
3541                           imm = (given & 0xf) | ((given & 0xfff00) >> 4);
3542                           func (stream, "%d", imm);
3543                           value_in_comment = imm;
3544                         }
3545                         break;
3546
3547                       case 'E':
3548                         /* LSB and WIDTH fields of BFI or BFC.  The machine-
3549                            language instruction encodes LSB and MSB.  */
3550                         {
3551                           long msb = (given & 0x001f0000) >> 16;
3552                           long lsb = (given & 0x00000f80) >> 7;
3553                           long w = msb - lsb + 1;
3554
3555                           if (w > 0)
3556                             func (stream, "#%lu, #%lu", lsb, w);
3557                           else
3558                             func (stream, "(invalid: %lu:%lu)", lsb, msb);
3559                         }
3560                         break;
3561
3562                       case 'R':
3563                         /* Get the PSR/banked register name.  */
3564                         {
3565                           const char * name;
3566                           unsigned sysm = (given & 0x004f0000) >> 16;
3567
3568                           sysm |= (given & 0x300) >> 4;
3569                           name = banked_regname (sysm);
3570
3571                           if (name != NULL)
3572                             func (stream, "%s", name);
3573                           else
3574                             func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
3575                         }
3576                         break;
3577
3578                       case 'V':
3579                         /* 16-bit unsigned immediate from a MOVT or MOVW
3580                            instruction, encoded in bits 0:11 and 15:19.  */
3581                         {
3582                           long hi = (given & 0x000f0000) >> 4;
3583                           long lo = (given & 0x00000fff);
3584                           long imm16 = hi | lo;
3585
3586                           func (stream, "#%lu", imm16);
3587                           value_in_comment = imm16;
3588                         }
3589                         break;
3590
3591                       default:
3592                         abort ();
3593                       }
3594                     }
3595                 }
3596               else
3597                 func (stream, "%c", *c);
3598             }
3599
3600           if (value_in_comment > 32 || value_in_comment < -16)
3601             func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
3602
3603           if (is_unpredictable)
3604             func (stream, UNPREDICTABLE_INSTRUCTION);
3605
3606           return;
3607         }
3608     }
3609   abort ();
3610 }
3611
3612 /* Print one 16-bit Thumb instruction from PC on INFO->STREAM.  */
3613
3614 static void
3615 print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
3616 {
3617   const struct opcode16 *insn;
3618   void *stream = info->stream;
3619   fprintf_ftype func = info->fprintf_func;
3620
3621   for (insn = thumb_opcodes; insn->assembler; insn++)
3622     if ((given & insn->mask) == insn->value)
3623       {
3624         signed long value_in_comment = 0;
3625         const char *c = insn->assembler;
3626
3627         for (; *c; c++)
3628           {
3629             int domaskpc = 0;
3630             int domasklr = 0;
3631
3632             if (*c != '%')
3633               {
3634                 func (stream, "%c", *c);
3635                 continue;
3636               }
3637
3638             switch (*++c)
3639               {
3640               case '%':
3641                 func (stream, "%%");
3642                 break;
3643
3644               case 'c':
3645                 if (ifthen_state)
3646                   func (stream, "%s", arm_conditional[IFTHEN_COND]);
3647                 break;
3648
3649               case 'C':
3650                 if (ifthen_state)
3651                   func (stream, "%s", arm_conditional[IFTHEN_COND]);
3652                 else
3653                   func (stream, "s");
3654                 break;
3655
3656               case 'I':
3657                 {
3658                   unsigned int tmp;
3659
3660                   ifthen_next_state = given & 0xff;
3661                   for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
3662                     func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
3663                   func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
3664                 }
3665                 break;
3666
3667               case 'x':
3668                 if (ifthen_next_state)
3669                   func (stream, "\t; unpredictable branch in IT block\n");
3670                 break;
3671
3672               case 'X':
3673                 if (ifthen_state)
3674                   func (stream, "\t; unpredictable <IT:%s>",
3675                         arm_conditional[IFTHEN_COND]);
3676                 break;
3677
3678               case 'S':
3679                 {
3680                   long reg;
3681
3682                   reg = (given >> 3) & 0x7;
3683                   if (given & (1 << 6))
3684                     reg += 8;
3685
3686                   func (stream, "%s", arm_regnames[reg]);
3687                 }
3688                 break;
3689
3690               case 'D':
3691                 {
3692                   long reg;
3693
3694                   reg = given & 0x7;
3695                   if (given & (1 << 7))
3696                     reg += 8;
3697
3698                   func (stream, "%s", arm_regnames[reg]);
3699                 }
3700                 break;
3701
3702               case 'N':
3703                 if (given & (1 << 8))
3704                   domasklr = 1;
3705                 /* Fall through.  */
3706               case 'O':
3707                 if (*c == 'O' && (given & (1 << 8)))
3708                   domaskpc = 1;
3709                 /* Fall through.  */
3710               case 'M':
3711                 {
3712                   int started = 0;
3713                   int reg;
3714
3715                   func (stream, "{");
3716
3717                   /* It would be nice if we could spot
3718                      ranges, and generate the rS-rE format: */
3719                   for (reg = 0; (reg < 8); reg++)
3720                     if ((given & (1 << reg)) != 0)
3721                       {
3722                         if (started)
3723                           func (stream, ", ");
3724                         started = 1;
3725                         func (stream, "%s", arm_regnames[reg]);
3726                       }
3727
3728                   if (domasklr)
3729                     {
3730                       if (started)
3731                         func (stream, ", ");
3732                       started = 1;
3733                       func (stream, "%s", arm_regnames[14] /* "lr" */);
3734                     }
3735
3736                   if (domaskpc)
3737                     {
3738                       if (started)
3739                         func (stream, ", ");
3740                       func (stream, "%s", arm_regnames[15] /* "pc" */);
3741                     }
3742
3743                   func (stream, "}");
3744                 }
3745                 break;
3746
3747               case 'W':
3748                 /* Print writeback indicator for a LDMIA.  We are doing a
3749                    writeback if the base register is not in the register
3750                    mask.  */
3751                 if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
3752                   func (stream, "!");
3753                 break;
3754
3755               case 'b':
3756                 /* Print ARM V6T2 CZB address: pc+4+6 bits.  */
3757                 {
3758                   bfd_vma address = (pc + 4
3759                                      + ((given & 0x00f8) >> 2)
3760                                      + ((given & 0x0200) >> 3));
3761                   info->print_address_func (address, info);
3762                 }
3763                 break;
3764
3765               case 's':
3766                 /* Right shift immediate -- bits 6..10; 1-31 print
3767                    as themselves, 0 prints as 32.  */
3768                 {
3769                   long imm = (given & 0x07c0) >> 6;
3770                   if (imm == 0)
3771                     imm = 32;
3772                   func (stream, "#%ld", imm);
3773                 }
3774                 break;
3775
3776               case '0': case '1': case '2': case '3': case '4':
3777               case '5': case '6': case '7': case '8': case '9':
3778                 {
3779                   int bitstart = *c++ - '0';
3780                   int bitend = 0;
3781
3782                   while (*c >= '0' && *c <= '9')
3783                     bitstart = (bitstart * 10) + *c++ - '0';
3784
3785                   switch (*c)
3786                     {
3787                     case '-':
3788                       {
3789                         bfd_vma reg;
3790
3791                         c++;
3792                         while (*c >= '0' && *c <= '9')
3793                           bitend = (bitend * 10) + *c++ - '0';
3794                         if (!bitend)
3795                           abort ();
3796                         reg = given >> bitstart;
3797                         reg &= (2 << (bitend - bitstart)) - 1;
3798
3799                         switch (*c)
3800                           {
3801                           case 'r':
3802                             func (stream, "%s", arm_regnames[reg]);
3803                             break;
3804
3805                           case 'd':
3806                             func (stream, "%ld", (long) reg);
3807                             value_in_comment = reg;
3808                             break;
3809
3810                           case 'H':
3811                             func (stream, "%ld", (long) (reg << 1));
3812                             value_in_comment = reg << 1;
3813                             break;
3814
3815                           case 'W':
3816                             func (stream, "%ld", (long) (reg << 2));
3817                             value_in_comment = reg << 2;
3818                             break;
3819
3820                           case 'a':
3821                             /* PC-relative address -- the bottom two
3822                                bits of the address are dropped
3823                                before the calculation.  */
3824                             info->print_address_func
3825                               (((pc + 4) & ~3) + (reg << 2), info);
3826                             value_in_comment = 0;
3827                             break;
3828
3829                           case 'x':
3830                             func (stream, "0x%04lx", (long) reg);
3831                             break;
3832
3833                           case 'B':
3834                             reg = ((reg ^ (1 << bitend)) - (1 << bitend));
3835                             info->print_address_func (reg * 2 + pc + 4, info);
3836                             value_in_comment = 0;
3837                             break;
3838
3839                           case 'c':
3840                             func (stream, "%s", arm_conditional [reg]);
3841                             break;
3842
3843                           default:
3844                             abort ();
3845                           }
3846                       }
3847                       break;
3848
3849                     case '\'':
3850                       c++;
3851                       if ((given & (1 << bitstart)) != 0)
3852                         func (stream, "%c", *c);
3853                       break;
3854
3855                     case '?':
3856                       ++c;
3857                       if ((given & (1 << bitstart)) != 0)
3858                         func (stream, "%c", *c++);
3859                       else
3860                         func (stream, "%c", *++c);
3861                       break;
3862
3863                     default:
3864                       abort ();
3865                     }
3866                 }
3867                 break;
3868
3869               default:
3870                 abort ();
3871               }
3872           }
3873
3874         if (value_in_comment > 32 || value_in_comment < -16)
3875           func (stream, "\t; 0x%lx", value_in_comment);
3876         return;
3877       }
3878
3879   /* No match.  */
3880   abort ();
3881 }
3882
3883 /* Return the name of an V7M special register.  */
3884
3885 static const char *
3886 psr_name (int regno)
3887 {
3888   switch (regno)
3889     {
3890     case 0: return "APSR";
3891     case 1: return "IAPSR";
3892     case 2: return "EAPSR";
3893     case 3: return "PSR";
3894     case 5: return "IPSR";
3895     case 6: return "EPSR";
3896     case 7: return "IEPSR";
3897     case 8: return "MSP";
3898     case 9: return "PSP";
3899     case 16: return "PRIMASK";
3900     case 17: return "BASEPRI";
3901     case 18: return "BASEPRI_MAX";
3902     case 19: return "FAULTMASK";
3903     case 20: return "CONTROL";
3904     default: return "<unknown>";
3905     }
3906 }
3907
3908 /* Print one 32-bit Thumb instruction from PC on INFO->STREAM.  */
3909
3910 static void
3911 print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
3912 {
3913   const struct opcode32 *insn;
3914   void *stream = info->stream;
3915   fprintf_ftype func = info->fprintf_func;
3916
3917   if (print_insn_coprocessor (pc, info, given, TRUE))
3918     return;
3919
3920   if (print_insn_neon (info, given, TRUE))
3921     return;
3922
3923   for (insn = thumb32_opcodes; insn->assembler; insn++)
3924     if ((given & insn->mask) == insn->value)
3925       {
3926         bfd_boolean is_unpredictable = FALSE;
3927         signed long value_in_comment = 0;
3928         const char *c = insn->assembler;
3929
3930         for (; *c; c++)
3931           {
3932             if (*c != '%')
3933               {
3934                 func (stream, "%c", *c);
3935                 continue;
3936               }
3937
3938             switch (*++c)
3939               {
3940               case '%':
3941                 func (stream, "%%");
3942                 break;
3943
3944               case 'c':
3945                 if (ifthen_state)
3946                   func (stream, "%s", arm_conditional[IFTHEN_COND]);
3947                 break;
3948
3949               case 'x':
3950                 if (ifthen_next_state)
3951                   func (stream, "\t; unpredictable branch in IT block\n");
3952                 break;
3953
3954               case 'X':
3955                 if (ifthen_state)
3956                   func (stream, "\t; unpredictable <IT:%s>",
3957                         arm_conditional[IFTHEN_COND]);
3958                 break;
3959
3960               case 'I':
3961                 {
3962                   unsigned int imm12 = 0;
3963
3964                   imm12 |= (given & 0x000000ffu);
3965                   imm12 |= (given & 0x00007000u) >> 4;
3966                   imm12 |= (given & 0x04000000u) >> 15;
3967                   func (stream, "#%u", imm12);
3968                   value_in_comment = imm12;
3969                 }
3970                 break;
3971
3972               case 'M':
3973                 {
3974                   unsigned int bits = 0, imm, imm8, mod;
3975
3976                   bits |= (given & 0x000000ffu);
3977                   bits |= (given & 0x00007000u) >> 4;
3978                   bits |= (given & 0x04000000u) >> 15;
3979                   imm8 = (bits & 0x0ff);
3980                   mod = (bits & 0xf00) >> 8;
3981                   switch (mod)
3982                     {
3983                     case 0: imm = imm8; break;
3984                     case 1: imm = ((imm8 << 16) | imm8); break;
3985                     case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
3986                     case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
3987                     default:
3988                       mod  = (bits & 0xf80) >> 7;
3989                       imm8 = (bits & 0x07f) | 0x80;
3990                       imm  = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
3991                     }
3992                   func (stream, "#%u", imm);
3993                   value_in_comment = imm;
3994                 }
3995                 break;
3996
3997               case 'J':
3998                 {
3999                   unsigned int imm = 0;
4000
4001                   imm |= (given & 0x000000ffu);
4002                   imm |= (given & 0x00007000u) >> 4;
4003                   imm |= (given & 0x04000000u) >> 15;
4004                   imm |= (given & 0x000f0000u) >> 4;
4005                   func (stream, "#%u", imm);
4006                   value_in_comment = imm;
4007                 }
4008                 break;
4009
4010               case 'K':
4011                 {
4012                   unsigned int imm = 0;
4013
4014                   imm |= (given & 0x000f0000u) >> 16;
4015                   imm |= (given & 0x00000ff0u) >> 0;
4016                   imm |= (given & 0x0000000fu) << 12;
4017                   func (stream, "#%u", imm);
4018                   value_in_comment = imm;
4019                 }
4020                 break;
4021
4022               case 'V':
4023                 {
4024                   unsigned int imm = 0;
4025
4026                   imm |= (given & 0x00000fffu);
4027                   imm |= (given & 0x000f0000u) >> 4;
4028                   func (stream, "#%u", imm);
4029                   value_in_comment = imm;
4030                 }
4031                 break;
4032
4033               case 'S':
4034                 {
4035                   unsigned int reg = (given & 0x0000000fu);
4036                   unsigned int stp = (given & 0x00000030u) >> 4;
4037                   unsigned int imm = 0;
4038                   imm |= (given & 0x000000c0u) >> 6;
4039                   imm |= (given & 0x00007000u) >> 10;
4040
4041                   func (stream, "%s", arm_regnames[reg]);
4042                   switch (stp)
4043                     {
4044                     case 0:
4045                       if (imm > 0)
4046                         func (stream, ", lsl #%u", imm);
4047                       break;
4048
4049                     case 1:
4050                       if (imm == 0)
4051                         imm = 32;
4052                       func (stream, ", lsr #%u", imm);
4053                       break;
4054
4055                     case 2:
4056                       if (imm == 0)
4057                         imm = 32;
4058                       func (stream, ", asr #%u", imm);
4059                       break;
4060
4061                     case 3:
4062                       if (imm == 0)
4063                         func (stream, ", rrx");
4064                       else
4065                         func (stream, ", ror #%u", imm);
4066                     }
4067                 }
4068                 break;
4069
4070               case 'a':
4071                 {
4072                   unsigned int Rn  = (given & 0x000f0000) >> 16;
4073                   unsigned int U   = ! NEGATIVE_BIT_SET;
4074                   unsigned int op  = (given & 0x00000f00) >> 8;
4075                   unsigned int i12 = (given & 0x00000fff);
4076                   unsigned int i8  = (given & 0x000000ff);
4077                   bfd_boolean writeback = FALSE, postind = FALSE;
4078                   bfd_vma offset = 0;
4079
4080                   func (stream, "[%s", arm_regnames[Rn]);
4081                   if (U) /* 12-bit positive immediate offset.  */
4082                     {
4083                       offset = i12;
4084                       if (Rn != 15)
4085                         value_in_comment = offset;
4086                     }
4087                   else if (Rn == 15) /* 12-bit negative immediate offset.  */
4088                     offset = - (int) i12;
4089                   else if (op == 0x0) /* Shifted register offset.  */
4090                     {
4091                       unsigned int Rm = (i8 & 0x0f);
4092                       unsigned int sh = (i8 & 0x30) >> 4;
4093
4094                       func (stream, ", %s", arm_regnames[Rm]);
4095                       if (sh)
4096                         func (stream, ", lsl #%u", sh);
4097                       func (stream, "]");
4098                       break;
4099                     }
4100                   else switch (op)
4101                     {
4102                     case 0xE:  /* 8-bit positive immediate offset.  */
4103                       offset = i8;
4104                       break;
4105
4106                     case 0xC:  /* 8-bit negative immediate offset.  */
4107                       offset = -i8;
4108                       break;
4109
4110                     case 0xF:  /* 8-bit + preindex with wb.  */
4111                       offset = i8;
4112                       writeback = TRUE;
4113                       break;
4114
4115                     case 0xD:  /* 8-bit - preindex with wb.  */
4116                       offset = -i8;
4117                       writeback = TRUE;
4118                       break;
4119
4120                     case 0xB:  /* 8-bit + postindex.  */
4121                       offset = i8;
4122                       postind = TRUE;
4123                       break;
4124
4125                     case 0x9:  /* 8-bit - postindex.  */
4126                       offset = -i8;
4127                       postind = TRUE;
4128                       break;
4129
4130                     default:
4131                       func (stream, ", <undefined>]");
4132                       goto skip;
4133                     }
4134
4135                   if (postind)
4136                     func (stream, "], #%d", (int) offset);
4137                   else
4138                     {
4139                       if (offset)
4140                         func (stream, ", #%d", (int) offset);
4141                       func (stream, writeback ? "]!" : "]");
4142                     }
4143
4144                   if (Rn == 15)
4145                     {
4146                       func (stream, "\t; ");
4147                       info->print_address_func (((pc + 4) & ~3) + offset, info);
4148                     }
4149                 }
4150               skip:
4151                 break;
4152
4153               case 'A':
4154                 {
4155                   unsigned int U   = ! NEGATIVE_BIT_SET;
4156                   unsigned int W   = WRITEBACK_BIT_SET;
4157                   unsigned int Rn  = (given & 0x000f0000) >> 16;
4158                   unsigned int off = (given & 0x000000ff);
4159
4160                   func (stream, "[%s", arm_regnames[Rn]);
4161
4162                   if (PRE_BIT_SET)
4163                     {
4164                       if (off || !U)
4165                         {
4166                           func (stream, ", #%c%u", U ? '+' : '-', off * 4);
4167                           value_in_comment = off * 4 * U ? 1 : -1;
4168                         }
4169                       func (stream, "]");
4170                       if (W)
4171                         func (stream, "!");
4172                     }
4173                   else
4174                     {
4175                       func (stream, "], ");
4176                       if (W)
4177                         {
4178                           func (stream, "#%c%u", U ? '+' : '-', off * 4);
4179                           value_in_comment = off * 4 * U ? 1 : -1;
4180                         }
4181                       else
4182                         {
4183                           func (stream, "{%u}", off);
4184                           value_in_comment = off;
4185                         }
4186                     }
4187                 }
4188                 break;
4189
4190               case 'w':
4191                 {
4192                   unsigned int Sbit = (given & 0x01000000) >> 24;
4193                   unsigned int type = (given & 0x00600000) >> 21;
4194
4195                   switch (type)
4196                     {
4197                     case 0: func (stream, Sbit ? "sb" : "b"); break;
4198                     case 1: func (stream, Sbit ? "sh" : "h"); break;
4199                     case 2:
4200                       if (Sbit)
4201                         func (stream, "??");
4202                       break;
4203                     case 3:
4204                       func (stream, "??");
4205                       break;
4206                     }
4207                 }
4208                 break;
4209
4210               case 'm':
4211                 {
4212                   int started = 0;
4213                   int reg;
4214
4215                   func (stream, "{");
4216                   for (reg = 0; reg < 16; reg++)
4217                     if ((given & (1 << reg)) != 0)
4218                       {
4219                         if (started)
4220                           func (stream, ", ");
4221                         started = 1;
4222                         func (stream, "%s", arm_regnames[reg]);
4223                       }
4224                   func (stream, "}");
4225                 }
4226                 break;
4227
4228               case 'E':
4229                 {
4230                   unsigned int msb = (given & 0x0000001f);
4231                   unsigned int lsb = 0;
4232
4233                   lsb |= (given & 0x000000c0u) >> 6;
4234                   lsb |= (given & 0x00007000u) >> 10;
4235                   func (stream, "#%u, #%u", lsb, msb - lsb + 1);
4236                 }
4237                 break;
4238
4239               case 'F':
4240                 {
4241                   unsigned int width = (given & 0x0000001f) + 1;
4242                   unsigned int lsb = 0;
4243
4244                   lsb |= (given & 0x000000c0u) >> 6;
4245                   lsb |= (given & 0x00007000u) >> 10;
4246                   func (stream, "#%u, #%u", lsb, width);
4247                 }
4248                 break;
4249
4250               case 'b':
4251                 {
4252                   unsigned int S = (given & 0x04000000u) >> 26;
4253                   unsigned int J1 = (given & 0x00002000u) >> 13;
4254                   unsigned int J2 = (given & 0x00000800u) >> 11;
4255                   bfd_vma offset = 0;
4256
4257                   offset |= !S << 20;
4258                   offset |= J2 << 19;
4259                   offset |= J1 << 18;
4260                   offset |= (given & 0x003f0000) >> 4;
4261                   offset |= (given & 0x000007ff) << 1;
4262                   offset -= (1 << 20);
4263
4264                   info->print_address_func (pc + 4 + offset, info);
4265                 }
4266                 break;
4267
4268               case 'B':
4269                 {
4270                   unsigned int S = (given & 0x04000000u) >> 26;
4271                   unsigned int I1 = (given & 0x00002000u) >> 13;
4272                   unsigned int I2 = (given & 0x00000800u) >> 11;
4273                   bfd_vma offset = 0;
4274
4275                   offset |= !S << 24;
4276                   offset |= !(I1 ^ S) << 23;
4277                   offset |= !(I2 ^ S) << 22;
4278                   offset |= (given & 0x03ff0000u) >> 4;
4279                   offset |= (given & 0x000007ffu) << 1;
4280                   offset -= (1 << 24);
4281                   offset += pc + 4;
4282
4283                   /* BLX target addresses are always word aligned.  */
4284                   if ((given & 0x00001000u) == 0)
4285                       offset &= ~2u;
4286
4287                   info->print_address_func (offset, info);
4288                 }
4289                 break;
4290
4291               case 's':
4292                 {
4293                   unsigned int shift = 0;
4294
4295                   shift |= (given & 0x000000c0u) >> 6;
4296                   shift |= (given & 0x00007000u) >> 10;
4297                   if (WRITEBACK_BIT_SET)
4298                     func (stream, ", asr #%u", shift);
4299                   else if (shift)
4300                     func (stream, ", lsl #%u", shift);
4301                   /* else print nothing - lsl #0 */
4302                 }
4303                 break;
4304
4305               case 'R':
4306                 {
4307                   unsigned int rot = (given & 0x00000030) >> 4;
4308
4309                   if (rot)
4310                     func (stream, ", ror #%u", rot * 8);
4311                 }
4312                 break;
4313
4314               case 'U':
4315                 if ((given & 0xf0) == 0x60)
4316                   {
4317                     switch (given & 0xf)
4318                       {
4319                         case 0xf: func (stream, "sy"); break;
4320                         default:
4321                           func (stream, "#%d", (int) given & 0xf);
4322                               break;
4323                       }
4324                   }
4325                 else
4326                   {
4327                     const char * opt = data_barrier_option (given & 0xf);
4328                     if (opt != NULL)
4329                       func (stream, "%s", opt);
4330                     else
4331                       func (stream, "#%d", (int) given & 0xf);
4332                    }
4333                 break;
4334
4335               case 'C':
4336                 if ((given & 0xff) == 0)
4337                   {
4338                     func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
4339                     if (given & 0x800)
4340                       func (stream, "f");
4341                     if (given & 0x400)
4342                       func (stream, "s");
4343                     if (given & 0x200)
4344                       func (stream, "x");
4345                     if (given & 0x100)
4346                       func (stream, "c");
4347                   }
4348                 else if ((given & 0x20) == 0x20)
4349                   {
4350                     char const* name;
4351                     unsigned sysm = (given & 0xf00) >> 8;
4352
4353                     sysm |= (given & 0x30);
4354                     sysm |= (given & 0x00100000) >> 14;
4355                     name = banked_regname (sysm);
4356
4357                     if (name != NULL)
4358                       func (stream, "%s", name);
4359                     else
4360                       func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
4361                   }
4362                 else
4363                   {
4364                     func (stream, "%s", psr_name (given & 0xff));
4365                   }
4366                 break;
4367
4368               case 'D':
4369                 if (((given & 0xff) == 0)
4370                     || ((given & 0x20) == 0x20))
4371                   {
4372                     char const* name;
4373                     unsigned sm = (given & 0xf0000) >> 16;
4374
4375                     sm |= (given & 0x30);
4376                     sm |= (given & 0x00100000) >> 14;
4377                     name = banked_regname (sm);
4378
4379                     if (name != NULL)
4380                       func (stream, "%s", name);
4381                     else
4382                       func (stream, "(UNDEF: %lu)", (unsigned long) sm);
4383                   }
4384                 else
4385                   func (stream, "%s", psr_name (given & 0xff));
4386                 break;
4387
4388               case '0': case '1': case '2': case '3': case '4':
4389               case '5': case '6': case '7': case '8': case '9':
4390                 {
4391                   int width;
4392                   unsigned long val;
4393
4394                   c = arm_decode_bitfield (c, given, &val, &width);
4395
4396                   switch (*c)
4397                     {
4398                     case 'd':
4399                       func (stream, "%lu", val);
4400                       value_in_comment = val;
4401                       break;
4402
4403                     case 'W':
4404                       func (stream, "%lu", val * 4);
4405                       value_in_comment = val * 4;
4406                       break;
4407
4408                     case 'R':
4409                       if (val == 15)
4410                         is_unpredictable = TRUE;
4411                       /* Fall through.  */
4412                     case 'r':
4413                       func (stream, "%s", arm_regnames[val]);
4414                       break;
4415
4416                     case 'c':
4417                       func (stream, "%s", arm_conditional[val]);
4418                       break;
4419
4420                     case '\'':
4421                       c++;
4422                       if (val == ((1ul << width) - 1))
4423                         func (stream, "%c", *c);
4424                       break;
4425
4426                     case '`':
4427                       c++;
4428                       if (val == 0)
4429                         func (stream, "%c", *c);
4430                       break;
4431
4432                     case '?':
4433                       func (stream, "%c", c[(1 << width) - (int) val]);
4434                       c += 1 << width;
4435                       break;
4436
4437                     case 'x':
4438                       func (stream, "0x%lx", val & 0xffffffffUL);
4439                       break;
4440
4441                     default:
4442                       abort ();
4443                     }
4444                 }
4445                 break;
4446
4447               case 'L':
4448                 /* PR binutils/12534
4449                    If we have a PC relative offset in an LDRD or STRD
4450                    instructions then display the decoded address.  */
4451                 if (((given >> 16) & 0xf) == 0xf)
4452                   {
4453                     bfd_vma offset = (given & 0xff) * 4;
4454
4455                     if ((given & (1 << 23)) == 0)
4456                       offset = - offset;
4457                     func (stream, "\t; ");
4458                     info->print_address_func ((pc & ~3) + 4 + offset, info);
4459                   }
4460                 break;
4461
4462               default:
4463                 abort ();
4464               }
4465           }
4466
4467         if (value_in_comment > 32 || value_in_comment < -16)
4468           func (stream, "\t; 0x%lx", value_in_comment);
4469
4470         if (is_unpredictable)
4471           func (stream, UNPREDICTABLE_INSTRUCTION);
4472
4473         return;
4474       }
4475
4476   /* No match.  */
4477   abort ();
4478 }
4479
4480 /* Print data bytes on INFO->STREAM.  */
4481
4482 static void
4483 print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
4484                  struct disassemble_info *info,
4485                  long given)
4486 {
4487   switch (info->bytes_per_chunk)
4488     {
4489     case 1:
4490       info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
4491       break;
4492     case 2:
4493       info->fprintf_func (info->stream, ".short\t0x%04lx", given);
4494       break;
4495     case 4:
4496       info->fprintf_func (info->stream, ".word\t0x%08lx", given);
4497       break;
4498     default:
4499       abort ();
4500     }
4501 }
4502
4503 /* Disallow mapping symbols ($a, $b, $d, $t etc) from
4504    being displayed in symbol relative addresses.  */
4505
4506 bfd_boolean
4507 arm_symbol_is_valid (asymbol * sym,
4508                      struct disassemble_info * info ATTRIBUTE_UNUSED)
4509 {
4510   const char * name;
4511
4512   if (sym == NULL)
4513     return FALSE;
4514
4515   name = bfd_asymbol_name (sym);
4516
4517   return (name && *name != '$');
4518 }
4519
4520 /* Parse an individual disassembler option.  */
4521
4522 void
4523 parse_arm_disassembler_option (char *option)
4524 {
4525   if (option == NULL)
4526     return;
4527
4528   if (CONST_STRNEQ (option, "reg-names-"))
4529     {
4530       int i;
4531
4532       option += 10;
4533
4534       for (i = NUM_ARM_REGNAMES; i--;)
4535         if (strneq (option, regnames[i].name, strlen (regnames[i].name)))
4536           {
4537             regname_selected = i;
4538             break;
4539           }
4540
4541       if (i < 0)
4542         /* XXX - should break 'option' at following delimiter.  */
4543         fprintf (stderr, _("Unrecognised register name set: %s\n"), option);
4544     }
4545   else if (CONST_STRNEQ (option, "force-thumb"))
4546     force_thumb = 1;
4547   else if (CONST_STRNEQ (option, "no-force-thumb"))
4548     force_thumb = 0;
4549   else
4550     /* XXX - should break 'option' at following delimiter.  */
4551     fprintf (stderr, _("Unrecognised disassembler option: %s\n"), option);
4552
4553   return;
4554 }
4555
4556 /* Parse the string of disassembler options, spliting it at whitespaces
4557    or commas.  (Whitespace separators supported for backwards compatibility).  */
4558
4559 static void
4560 parse_disassembler_options (char *options)
4561 {
4562   if (options == NULL)
4563     return;
4564
4565   while (*options)
4566     {
4567       parse_arm_disassembler_option (options);
4568
4569       /* Skip forward to next seperator.  */
4570       while ((*options) && (! ISSPACE (*options)) && (*options != ','))
4571         ++ options;
4572       /* Skip forward past seperators.  */
4573       while (ISSPACE (*options) || (*options == ','))
4574         ++ options;
4575     }
4576 }
4577
4578 /* Search back through the insn stream to determine if this instruction is
4579    conditionally executed.  */
4580
4581 static void
4582 find_ifthen_state (bfd_vma pc,
4583                    struct disassemble_info *info,
4584                    bfd_boolean little)
4585 {
4586   unsigned char b[2];
4587   unsigned int insn;
4588   int status;
4589   /* COUNT is twice the number of instructions seen.  It will be odd if we
4590      just crossed an instruction boundary.  */
4591   int count;
4592   int it_count;
4593   unsigned int seen_it;
4594   bfd_vma addr;
4595
4596   ifthen_address = pc;
4597   ifthen_state = 0;
4598
4599   addr = pc;
4600   count = 1;
4601   it_count = 0;
4602   seen_it = 0;
4603   /* Scan backwards looking for IT instructions, keeping track of where
4604      instruction boundaries are.  We don't know if something is actually an
4605      IT instruction until we find a definite instruction boundary.  */
4606   for (;;)
4607     {
4608       if (addr == 0 || info->symbol_at_address_func (addr, info))
4609         {
4610           /* A symbol must be on an instruction boundary, and will not
4611              be within an IT block.  */
4612           if (seen_it && (count & 1))
4613             break;
4614
4615           return;
4616         }
4617       addr -= 2;
4618       status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
4619       if (status)
4620         return;
4621
4622       if (little)
4623         insn = (b[0]) | (b[1] << 8);
4624       else
4625         insn = (b[1]) | (b[0] << 8);
4626       if (seen_it)
4627         {
4628           if ((insn & 0xf800) < 0xe800)
4629             {
4630               /* Addr + 2 is an instruction boundary.  See if this matches
4631                  the expected boundary based on the position of the last
4632                  IT candidate.  */
4633               if (count & 1)
4634                 break;
4635               seen_it = 0;
4636             }
4637         }
4638       if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
4639         {
4640           /* This could be an IT instruction.  */
4641           seen_it = insn;
4642           it_count = count >> 1;
4643         }
4644       if ((insn & 0xf800) >= 0xe800)
4645         count++;
4646       else
4647         count = (count + 2) | 1;
4648       /* IT blocks contain at most 4 instructions.  */
4649       if (count >= 8 && !seen_it)
4650         return;
4651     }
4652   /* We found an IT instruction.  */
4653   ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
4654   if ((ifthen_state & 0xf) == 0)
4655     ifthen_state = 0;
4656 }
4657
4658 /* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
4659    mapping symbol.  */
4660
4661 static int
4662 is_mapping_symbol (struct disassemble_info *info, int n,
4663                    enum map_type *map_type)
4664 {
4665   const char *name;
4666
4667   name = bfd_asymbol_name (info->symtab[n]);
4668   if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
4669       && (name[2] == 0 || name[2] == '.'))
4670     {
4671       *map_type = ((name[1] == 'a') ? MAP_ARM
4672                    : (name[1] == 't') ? MAP_THUMB
4673                    : MAP_DATA);
4674       return TRUE;
4675     }
4676
4677   return FALSE;
4678 }
4679
4680 /* Try to infer the code type (ARM or Thumb) from a mapping symbol.
4681    Returns nonzero if *MAP_TYPE was set.  */
4682
4683 static int
4684 get_map_sym_type (struct disassemble_info *info,
4685                   int n,
4686                   enum map_type *map_type)
4687 {
4688   /* If the symbol is in a different section, ignore it.  */
4689   if (info->section != NULL && info->section != info->symtab[n]->section)
4690     return FALSE;
4691
4692   return is_mapping_symbol (info, n, map_type);
4693 }
4694
4695 /* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
4696    Returns nonzero if *MAP_TYPE was set.  */
4697
4698 static int
4699 get_sym_code_type (struct disassemble_info *info,
4700                    int n,
4701                    enum map_type *map_type)
4702 {
4703   elf_symbol_type *es;
4704   unsigned int type;
4705
4706   /* If the symbol is in a different section, ignore it.  */
4707   if (info->section != NULL && info->section != info->symtab[n]->section)
4708     return FALSE;
4709
4710   es = *(elf_symbol_type **)(info->symtab + n);
4711   type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
4712
4713   /* If the symbol has function type then use that.  */
4714   if (type == STT_FUNC || type == STT_GNU_IFUNC)
4715     {
4716       if (ARM_SYM_BRANCH_TYPE (&es->internal_elf_sym) == ST_BRANCH_TO_THUMB)
4717         *map_type = MAP_THUMB;
4718       else
4719         *map_type = MAP_ARM;
4720       return TRUE;
4721     }
4722
4723   return FALSE;
4724 }
4725
4726 /* Given a bfd_mach_arm_XXX value, this function fills in the fields
4727    of the supplied arm_feature_set structure with bitmasks indicating
4728    the support base architectures and coprocessor extensions.
4729
4730    FIXME: This could more efficiently implemented as a constant array,
4731    although it would also be less robust.  */
4732
4733 static void
4734 select_arm_features (unsigned long mach,
4735                      arm_feature_set * features)
4736 {
4737 #undef  ARM_FEATURE
4738 #define ARM_FEATURE(ARCH,CEXT) \
4739   features->core = (ARCH); \
4740   features->coproc = (CEXT) | FPU_FPA; \
4741   return
4742
4743   switch (mach)
4744     {
4745     case bfd_mach_arm_2:       ARM_ARCH_V2;
4746     case bfd_mach_arm_2a:      ARM_ARCH_V2S;
4747     case bfd_mach_arm_3:       ARM_ARCH_V3;
4748     case bfd_mach_arm_3M:      ARM_ARCH_V3M;
4749     case bfd_mach_arm_4:       ARM_ARCH_V4;
4750     case bfd_mach_arm_4T:      ARM_ARCH_V4T;
4751     case bfd_mach_arm_5:       ARM_ARCH_V5;
4752     case bfd_mach_arm_5T:      ARM_ARCH_V5T;
4753     case bfd_mach_arm_5TE:     ARM_ARCH_V5TE;
4754     case bfd_mach_arm_XScale:  ARM_ARCH_XSCALE;
4755     case bfd_mach_arm_ep9312:  ARM_FEATURE (ARM_AEXT_V4T, ARM_CEXT_MAVERICK | FPU_MAVERICK);
4756     case bfd_mach_arm_iWMMXt:  ARM_ARCH_IWMMXT;
4757     case bfd_mach_arm_iWMMXt2: ARM_ARCH_IWMMXT2;
4758       /* If the machine type is unknown allow all
4759          architecture types and all extensions.  */
4760     case bfd_mach_arm_unknown: ARM_FEATURE (-1UL, -1UL);
4761     default:
4762       abort ();
4763     }
4764 }
4765
4766
4767 /* NOTE: There are no checks in these routines that
4768    the relevant number of data bytes exist.  */
4769
4770 static int
4771 print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
4772 {
4773   unsigned char b[4];
4774   long          given;
4775   int           status;
4776   int           is_thumb = FALSE;
4777   int           is_data = FALSE;
4778   int           little_code;
4779   unsigned int  size = 4;
4780   void          (*printer) (bfd_vma, struct disassemble_info *, long);
4781   bfd_boolean   found = FALSE;
4782   struct arm_private_data *private_data;
4783
4784   if (info->disassembler_options)
4785     {
4786       parse_disassembler_options (info->disassembler_options);
4787
4788       /* To avoid repeated parsing of these options, we remove them here.  */
4789       info->disassembler_options = NULL;
4790     }
4791
4792   /* PR 10288: Control which instructions will be disassembled.  */
4793   if (info->private_data == NULL)
4794     {
4795       static struct arm_private_data private;
4796
4797       if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
4798         /* If the user did not use the -m command line switch then default to
4799            disassembling all types of ARM instruction.
4800
4801            The info->mach value has to be ignored as this will be based on
4802            the default archictecture for the target and/or hints in the notes
4803            section, but it will never be greater than the current largest arm
4804            machine value (iWMMXt2), which is only equivalent to the V5TE
4805            architecture.  ARM architectures have advanced beyond the machine
4806            value encoding, and these newer architectures would be ignored if
4807            the machine value was used.
4808
4809            Ie the -m switch is used to restrict which instructions will be
4810            disassembled.  If it is necessary to use the -m switch to tell
4811            objdump that an ARM binary is being disassembled, eg because the
4812            input is a raw binary file, but it is also desired to disassemble
4813            all ARM instructions then use "-marm".  This will select the
4814            "unknown" arm architecture which is compatible with any ARM
4815            instruction.  */
4816           info->mach = bfd_mach_arm_unknown;
4817
4818       /* Compute the architecture bitmask from the machine number.
4819          Note: This assumes that the machine number will not change
4820          during disassembly....  */
4821       select_arm_features (info->mach, & private.features);
4822
4823       private.has_mapping_symbols = -1;
4824       private.last_mapping_sym = -1;
4825       private.last_mapping_addr = 0;
4826
4827       info->private_data = & private;
4828     }
4829
4830   private_data = info->private_data;
4831
4832   /* Decide if our code is going to be little-endian, despite what the
4833      function argument might say.  */
4834   little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
4835
4836   /* For ELF, consult the symbol table to determine what kind of code
4837      or data we have.  */
4838   if (info->symtab_size != 0
4839       && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
4840     {
4841       bfd_vma addr;
4842       int n, start;
4843       int last_sym = -1;
4844       enum map_type type = MAP_ARM;
4845
4846       /* Start scanning at the start of the function, or wherever
4847          we finished last time.  */
4848       /* PR 14006.  When the address is 0 we are either at the start of the
4849          very first function, or else the first function in a new, unlinked
4850          executable section (eg because uf -ffunction-sections).  Either way
4851          start scanning from the beginning of the symbol table, not where we
4852          left off last time.  */
4853       if (pc == 0)
4854         start = 0;
4855       else
4856         {
4857           start = info->symtab_pos + 1;
4858           if (start < private_data->last_mapping_sym)
4859             start = private_data->last_mapping_sym;
4860         }
4861       found = FALSE;
4862
4863       /* First, look for mapping symbols.  */
4864       if (private_data->has_mapping_symbols != 0)
4865         {
4866           /* Scan up to the location being disassembled.  */
4867           for (n = start; n < info->symtab_size; n++)
4868             {
4869               addr = bfd_asymbol_value (info->symtab[n]);
4870               if (addr > pc)
4871                 break;
4872               if (get_map_sym_type (info, n, &type))
4873                 {
4874                   last_sym = n;
4875                   found = TRUE;
4876                 }
4877             }
4878
4879           if (!found)
4880             {
4881               /* No mapping symbol found at this address.  Look backwards
4882                  for a preceding one.  */
4883               for (n = start - 1; n >= 0; n--)
4884                 {
4885                   if (get_map_sym_type (info, n, &type))
4886                     {
4887                       last_sym = n;
4888                       found = TRUE;
4889                       break;
4890                     }
4891                 }
4892             }
4893
4894           if (found)
4895             private_data->has_mapping_symbols = 1;
4896
4897           /* No mapping symbols were found.  A leading $d may be
4898              omitted for sections which start with data; but for
4899              compatibility with legacy and stripped binaries, only
4900              assume the leading $d if there is at least one mapping
4901              symbol in the file.  */
4902           if (!found && private_data->has_mapping_symbols == -1)
4903             {
4904               /* Look for mapping symbols, in any section.  */
4905               for (n = 0; n < info->symtab_size; n++)
4906                 if (is_mapping_symbol (info, n, &type))
4907                   {
4908                     private_data->has_mapping_symbols = 1;
4909                     break;
4910                   }
4911               if (private_data->has_mapping_symbols == -1)
4912                 private_data->has_mapping_symbols = 0;
4913             }
4914
4915           if (!found && private_data->has_mapping_symbols == 1)
4916             {
4917               type = MAP_DATA;
4918               found = TRUE;
4919             }
4920         }
4921
4922       /* Next search for function symbols to separate ARM from Thumb
4923          in binaries without mapping symbols.  */
4924       if (!found)
4925         {
4926           /* Scan up to the location being disassembled.  */
4927           for (n = start; n < info->symtab_size; n++)
4928             {
4929               addr = bfd_asymbol_value (info->symtab[n]);
4930               if (addr > pc)
4931                 break;
4932               if (get_sym_code_type (info, n, &type))
4933                 {
4934                   last_sym = n;
4935                   found = TRUE;
4936                 }
4937             }
4938
4939           if (!found)
4940             {
4941               /* No mapping symbol found at this address.  Look backwards
4942                  for a preceding one.  */
4943               for (n = start - 1; n >= 0; n--)
4944                 {
4945                   if (get_sym_code_type (info, n, &type))
4946                     {
4947                       last_sym = n;
4948                       found = TRUE;
4949                       break;
4950                     }
4951                 }
4952             }
4953         }
4954
4955       private_data->last_mapping_sym = last_sym;
4956       private_data->last_type = type;
4957       is_thumb = (private_data->last_type == MAP_THUMB);
4958       is_data = (private_data->last_type == MAP_DATA);
4959
4960       /* Look a little bit ahead to see if we should print out
4961          two or four bytes of data.  If there's a symbol,
4962          mapping or otherwise, after two bytes then don't
4963          print more.  */
4964       if (is_data)
4965         {
4966           size = 4 - (pc & 3);
4967           for (n = last_sym + 1; n < info->symtab_size; n++)
4968             {
4969               addr = bfd_asymbol_value (info->symtab[n]);
4970               if (addr > pc
4971                   && (info->section == NULL
4972                       || info->section == info->symtab[n]->section))
4973                 {
4974                   if (addr - pc < size)
4975                     size = addr - pc;
4976                   break;
4977                 }
4978             }
4979           /* If the next symbol is after three bytes, we need to
4980              print only part of the data, so that we can use either
4981              .byte or .short.  */
4982           if (size == 3)
4983             size = (pc & 1) ? 1 : 2;
4984         }
4985     }
4986
4987   if (info->symbols != NULL)
4988     {
4989       if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
4990         {
4991           coff_symbol_type * cs;
4992
4993           cs = coffsymbol (*info->symbols);
4994           is_thumb = (   cs->native->u.syment.n_sclass == C_THUMBEXT
4995                       || cs->native->u.syment.n_sclass == C_THUMBSTAT
4996                       || cs->native->u.syment.n_sclass == C_THUMBLABEL
4997                       || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
4998                       || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
4999         }
5000       else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
5001                && !found)
5002         {
5003           /* If no mapping symbol has been found then fall back to the type
5004              of the function symbol.  */
5005           elf_symbol_type *  es;
5006           unsigned int       type;
5007
5008           es = *(elf_symbol_type **)(info->symbols);
5009           type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
5010
5011           is_thumb = ((ARM_SYM_BRANCH_TYPE (&es->internal_elf_sym)
5012                        == ST_BRANCH_TO_THUMB)
5013                       || type == STT_ARM_16BIT);
5014         }
5015     }
5016
5017   if (force_thumb)
5018     is_thumb = TRUE;
5019
5020   if (is_data)
5021     info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
5022   else
5023     info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
5024
5025   info->bytes_per_line = 4;
5026
5027   /* PR 10263: Disassemble data if requested to do so by the user.  */
5028   if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
5029     {
5030       int i;
5031
5032       /* Size was already set above.  */
5033       info->bytes_per_chunk = size;
5034       printer = print_insn_data;
5035
5036       status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
5037       given = 0;
5038       if (little)
5039         for (i = size - 1; i >= 0; i--)
5040           given = b[i] | (given << 8);
5041       else
5042         for (i = 0; i < (int) size; i++)
5043           given = b[i] | (given << 8);
5044     }
5045   else if (!is_thumb)
5046     {
5047       /* In ARM mode endianness is a straightforward issue: the instruction
5048          is four bytes long and is either ordered 0123 or 3210.  */
5049       printer = print_insn_arm;
5050       info->bytes_per_chunk = 4;
5051       size = 4;
5052
5053       status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
5054       if (little_code)
5055         given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
5056       else
5057         given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24);
5058     }
5059   else
5060     {
5061       /* In Thumb mode we have the additional wrinkle of two
5062          instruction lengths.  Fortunately, the bits that determine
5063          the length of the current instruction are always to be found
5064          in the first two bytes.  */
5065       printer = print_insn_thumb16;
5066       info->bytes_per_chunk = 2;
5067       size = 2;
5068
5069       status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
5070       if (little_code)
5071         given = (b[0]) | (b[1] << 8);
5072       else
5073         given = (b[1]) | (b[0] << 8);
5074
5075       if (!status)
5076         {
5077           /* These bit patterns signal a four-byte Thumb
5078              instruction.  */
5079           if ((given & 0xF800) == 0xF800
5080               || (given & 0xF800) == 0xF000
5081               || (given & 0xF800) == 0xE800)
5082             {
5083               status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
5084               if (little_code)
5085                 given = (b[0]) | (b[1] << 8) | (given << 16);
5086               else
5087                 given = (b[1]) | (b[0] << 8) | (given << 16);
5088
5089               printer = print_insn_thumb32;
5090               size = 4;
5091             }
5092         }
5093
5094       if (ifthen_address != pc)
5095         find_ifthen_state (pc, info, little_code);
5096
5097       if (ifthen_state)
5098         {
5099           if ((ifthen_state & 0xf) == 0x8)
5100             ifthen_next_state = 0;
5101           else
5102             ifthen_next_state = (ifthen_state & 0xe0)
5103                                 | ((ifthen_state & 0xf) << 1);
5104         }
5105     }
5106
5107   if (status)
5108     {
5109       info->memory_error_func (status, pc, info);
5110       return -1;
5111     }
5112   if (info->flags & INSN_HAS_RELOC)
5113     /* If the instruction has a reloc associated with it, then
5114        the offset field in the instruction will actually be the
5115        addend for the reloc.  (We are using REL type relocs).
5116        In such cases, we can ignore the pc when computing
5117        addresses, since the addend is not currently pc-relative.  */
5118     pc = 0;
5119
5120   printer (pc, info, given);
5121
5122   if (is_thumb)
5123     {
5124       ifthen_state = ifthen_next_state;
5125       ifthen_address += size;
5126     }
5127   return size;
5128 }
5129
5130 int
5131 print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
5132 {
5133   /* Detect BE8-ness and record it in the disassembler info.  */
5134   if (info->flavour == bfd_target_elf_flavour
5135       && info->section != NULL
5136       && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
5137     info->endian_code = BFD_ENDIAN_LITTLE;
5138
5139   return print_insn (pc, info, FALSE);
5140 }
5141
5142 int
5143 print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
5144 {
5145   return print_insn (pc, info, TRUE);
5146 }
5147
5148 void
5149 print_arm_disassembler_options (FILE *stream)
5150 {
5151   int i;
5152
5153   fprintf (stream, _("\n\
5154 The following ARM specific disassembler options are supported for use with\n\
5155 the -M switch:\n"));
5156
5157   for (i = NUM_ARM_REGNAMES; i--;)
5158     fprintf (stream, "  reg-names-%s %*c%s\n",
5159              regnames[i].name,
5160              (int)(14 - strlen (regnames[i].name)), ' ',
5161              regnames[i].description);
5162
5163   fprintf (stream, "  force-thumb              Assume all insns are Thumb insns\n");
5164   fprintf (stream, "  no-force-thumb           Examine preceding label to determine an insn's type\n\n");
5165 }