opcodes/arm-dis.c

   1 /* Instruction printing code for the ARM
   2    Copyright (C) 1994-2021 Free Software Foundation, Inc.
   3    Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
   4    Modification by James G. Smith (jsmith@cygnus.co.uk)
   5
   6    This file is part of libopcodes.
   7
   8    This library is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the License, or
  11    (at your option) any later version.
  12
  13    It is distributed in the hope that it will be useful, but WITHOUT
  14    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16    License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; if not, write to the Free Software
  20    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  21    MA 02110-1301, USA.  */
  22
  23 #include "sysdep.h"
  24 #include <assert.h>
  25
  26 #include "disassemble.h"
  27 #include "opcode/arm.h"
  28 #include "opintl.h"
  29 #include "safe-ctype.h"
  30 #include "libiberty.h"
  31 #include "floatformat.h"
  32
  33 /* FIXME: This shouldn't be done here.  */
  34 #include "coff/internal.h"
  35 #include "libcoff.h"
  36 #include "bfd.h"
  37 #include "elf-bfd.h"
  38 #include "elf/internal.h"
  39 #include "elf/arm.h"
  40 #include "mach-o.h"
  41
  42 /* Cached mapping symbol state.  */
  43 enum map_type
  44 {
  45   MAP_ARM,
  46   MAP_THUMB,
  47   MAP_DATA
  48 };
  49
  50 struct arm_private_data
  51 {
  52   /* The features to use when disassembling optional instructions.  */
  53   arm_feature_set features;
  54
  55   /* Track the last type (although this doesn't seem to be useful) */
  56   enum map_type last_type;
  57
  58   /* Tracking symbol table information */
  59   int last_mapping_sym;
  60
  61   /* The end range of the current range being disassembled.  */
  62   bfd_vma last_stop_offset;
  63   bfd_vma last_mapping_addr;
  64 };
  65
  66 enum mve_instructions
  67 {
  68   MVE_VPST,
  69   MVE_VPT_FP_T1,
  70   MVE_VPT_FP_T2,
  71   MVE_VPT_VEC_T1,
  72   MVE_VPT_VEC_T2,
  73   MVE_VPT_VEC_T3,
  74   MVE_VPT_VEC_T4,
  75   MVE_VPT_VEC_T5,
  76   MVE_VPT_VEC_T6,
  77   MVE_VCMP_FP_T1,
  78   MVE_VCMP_FP_T2,
  79   MVE_VCMP_VEC_T1,
  80   MVE_VCMP_VEC_T2,
  81   MVE_VCMP_VEC_T3,
  82   MVE_VCMP_VEC_T4,
  83   MVE_VCMP_VEC_T5,
  84   MVE_VCMP_VEC_T6,
  85   MVE_VDUP,
  86   MVE_VEOR,
  87   MVE_VFMAS_FP_SCALAR,
  88   MVE_VFMA_FP_SCALAR,
  89   MVE_VFMA_FP,
  90   MVE_VFMS_FP,
  91   MVE_VHADD_T1,
  92   MVE_VHADD_T2,
  93   MVE_VHSUB_T1,
  94   MVE_VHSUB_T2,
  95   MVE_VRHADD,
  96   MVE_VLD2,
  97   MVE_VLD4,
  98   MVE_VST2,
  99   MVE_VST4,
 100   MVE_VLDRB_T1,
 101   MVE_VLDRH_T2,
 102   MVE_VLDRB_T5,
 103   MVE_VLDRH_T6,
 104   MVE_VLDRW_T7,
 105   MVE_VSTRB_T1,
 106   MVE_VSTRH_T2,
 107   MVE_VSTRB_T5,
 108   MVE_VSTRH_T6,
 109   MVE_VSTRW_T7,
 110   MVE_VLDRB_GATHER_T1,
 111   MVE_VLDRH_GATHER_T2,
 112   MVE_VLDRW_GATHER_T3,
 113   MVE_VLDRD_GATHER_T4,
 114   MVE_VLDRW_GATHER_T5,
 115   MVE_VLDRD_GATHER_T6,
 116   MVE_VSTRB_SCATTER_T1,
 117   MVE_VSTRH_SCATTER_T2,
 118   MVE_VSTRW_SCATTER_T3,
 119   MVE_VSTRD_SCATTER_T4,
 120   MVE_VSTRW_SCATTER_T5,
 121   MVE_VSTRD_SCATTER_T6,
 122   MVE_VCVT_FP_FIX_VEC,
 123   MVE_VCVT_BETWEEN_FP_INT,
 124   MVE_VCVT_FP_HALF_FP,
 125   MVE_VCVT_FROM_FP_TO_INT,
 126   MVE_VRINT_FP,
 127   MVE_VMOV_HFP_TO_GP,
 128   MVE_VMOV_GP_TO_VEC_LANE,
 129   MVE_VMOV_IMM_TO_VEC,
 130   MVE_VMOV_VEC_TO_VEC,
 131   MVE_VMOV2_VEC_LANE_TO_GP,
 132   MVE_VMOV2_GP_TO_VEC_LANE,
 133   MVE_VMOV_VEC_LANE_TO_GP,
 134   MVE_VMVN_IMM,
 135   MVE_VMVN_REG,
 136   MVE_VORR_IMM,
 137   MVE_VORR_REG,
 138   MVE_VORN,
 139   MVE_VBIC_IMM,
 140   MVE_VBIC_REG,
 141   MVE_VMOVX,
 142   MVE_VMOVL,
 143   MVE_VMOVN,
 144   MVE_VMULL_INT,
 145   MVE_VMULL_POLY,
 146   MVE_VQDMULL_T1,
 147   MVE_VQDMULL_T2,
 148   MVE_VQMOVN,
 149   MVE_VQMOVUN,
 150   MVE_VADDV,
 151   MVE_VMLADAV_T1,
 152   MVE_VMLADAV_T2,
 153   MVE_VMLALDAV,
 154   MVE_VMLAS,
 155   MVE_VADDLV,
 156   MVE_VMLSDAV_T1,
 157   MVE_VMLSDAV_T2,
 158   MVE_VMLSLDAV,
 159   MVE_VRMLALDAVH,
 160   MVE_VRMLSLDAVH,
 161   MVE_VQDMLADH,
 162   MVE_VQRDMLADH,
 163   MVE_VQDMLAH,
 164   MVE_VQRDMLAH,
 165   MVE_VQDMLASH,
 166   MVE_VQRDMLASH,
 167   MVE_VQDMLSDH,
 168   MVE_VQRDMLSDH,
 169   MVE_VQDMULH_T1,
 170   MVE_VQRDMULH_T2,
 171   MVE_VQDMULH_T3,
 172   MVE_VQRDMULH_T4,
 173   MVE_VDDUP,
 174   MVE_VDWDUP,
 175   MVE_VIWDUP,
 176   MVE_VIDUP,
 177   MVE_VCADD_FP,
 178   MVE_VCADD_VEC,
 179   MVE_VHCADD,
 180   MVE_VCMLA_FP,
 181   MVE_VCMUL_FP,
 182   MVE_VQRSHL_T1,
 183   MVE_VQRSHL_T2,
 184   MVE_VQRSHRN,
 185   MVE_VQRSHRUN,
 186   MVE_VQSHL_T1,
 187   MVE_VQSHL_T2,
 188   MVE_VQSHLU_T3,
 189   MVE_VQSHL_T4,
 190   MVE_VQSHRN,
 191   MVE_VQSHRUN,
 192   MVE_VRSHL_T1,
 193   MVE_VRSHL_T2,
 194   MVE_VRSHR,
 195   MVE_VRSHRN,
 196   MVE_VSHL_T1,
 197   MVE_VSHL_T2,
 198   MVE_VSHL_T3,
 199   MVE_VSHLC,
 200   MVE_VSHLL_T1,
 201   MVE_VSHLL_T2,
 202   MVE_VSHR,
 203   MVE_VSHRN,
 204   MVE_VSLI,
 205   MVE_VSRI,
 206   MVE_VADC,
 207   MVE_VABAV,
 208   MVE_VABD_FP,
 209   MVE_VABD_VEC,
 210   MVE_VABS_FP,
 211   MVE_VABS_VEC,
 212   MVE_VADD_FP_T1,
 213   MVE_VADD_FP_T2,
 214   MVE_VADD_VEC_T1,
 215   MVE_VADD_VEC_T2,
 216   MVE_VSBC,
 217   MVE_VSUB_FP_T1,
 218   MVE_VSUB_FP_T2,
 219   MVE_VSUB_VEC_T1,
 220   MVE_VSUB_VEC_T2,
 221   MVE_VAND,
 222   MVE_VBRSR,
 223   MVE_VCLS,
 224   MVE_VCLZ,
 225   MVE_VCTP,
 226   MVE_VMAX,
 227   MVE_VMAXA,
 228   MVE_VMAXNM_FP,
 229   MVE_VMAXNMA_FP,
 230   MVE_VMAXNMV_FP,
 231   MVE_VMAXNMAV_FP,
 232   MVE_VMAXV,
 233   MVE_VMAXAV,
 234   MVE_VMIN,
 235   MVE_VMINA,
 236   MVE_VMINNM_FP,
 237   MVE_VMINNMA_FP,
 238   MVE_VMINNMV_FP,
 239   MVE_VMINNMAV_FP,
 240   MVE_VMINV,
 241   MVE_VMINAV,
 242   MVE_VMLA,
 243   MVE_VMUL_FP_T1,
 244   MVE_VMUL_FP_T2,
 245   MVE_VMUL_VEC_T1,
 246   MVE_VMUL_VEC_T2,
 247   MVE_VMULH,
 248   MVE_VRMULH,
 249   MVE_VNEG_FP,
 250   MVE_VNEG_VEC,
 251   MVE_VPNOT,
 252   MVE_VPSEL,
 253   MVE_VQABS,
 254   MVE_VQADD_T1,
 255   MVE_VQADD_T2,
 256   MVE_VQSUB_T1,
 257   MVE_VQSUB_T2,
 258   MVE_VQNEG,
 259   MVE_VREV16,
 260   MVE_VREV32,
 261   MVE_VREV64,
 262   MVE_LSLL,
 263   MVE_LSLLI,
 264   MVE_LSRL,
 265   MVE_ASRL,
 266   MVE_ASRLI,
 267   MVE_SQRSHRL,
 268   MVE_SQRSHR,
 269   MVE_UQRSHL,
 270   MVE_UQRSHLL,
 271   MVE_UQSHL,
 272   MVE_UQSHLL,
 273   MVE_URSHRL,
 274   MVE_URSHR,
 275   MVE_SRSHRL,
 276   MVE_SRSHR,
 277   MVE_SQSHLL,
 278   MVE_SQSHL,
 279   MVE_CINC,
 280   MVE_CINV,
 281   MVE_CNEG,
 282   MVE_CSINC,
 283   MVE_CSINV,
 284   MVE_CSET,
 285   MVE_CSETM,
 286   MVE_CSNEG,
 287   MVE_CSEL,
 288   MVE_NONE
 289 };
 290
 291 enum mve_unpredictable
 292 {
 293   UNPRED_IT_BLOCK,              /* Unpredictable because mve insn in it block.
 294                                  */
 295   UNPRED_FCA_0_FCB_1,           /* Unpredictable because fcA = 0 and
 296                                    fcB = 1 (vpt).  */
 297   UNPRED_R13,                   /* Unpredictable because r13 (sp) or
 298                                    r15 (sp) used.  */
 299   UNPRED_R15,                   /* Unpredictable because r15 (pc) is used.  */
 300   UNPRED_Q_GT_4,                /* Unpredictable because
 301                                    vec reg start > 4 (vld4/st4).  */
 302   UNPRED_Q_GT_6,                /* Unpredictable because
 303                                    vec reg start > 6 (vld2/st2).  */
 304   UNPRED_R13_AND_WB,            /* Unpredictable becase gp reg = r13
 305                                    and WB bit = 1.  */
 306   UNPRED_Q_REGS_EQUAL,          /* Unpredictable because vector registers are
 307                                    equal.  */
 308   UNPRED_OS,                    /* Unpredictable because offset scaled == 1.  */
 309   UNPRED_GP_REGS_EQUAL,         /* Unpredictable because gp registers are the
 310                                    same.  */
 311   UNPRED_Q_REGS_EQ_AND_SIZE_1,  /* Unpredictable because q regs equal and
 312                                    size = 1.  */
 313   UNPRED_Q_REGS_EQ_AND_SIZE_2,  /* Unpredictable because q regs equal and
 314                                    size = 2.  */
 315   UNPRED_NONE                   /* No unpredictable behavior.  */
 316 };
 317
 318 enum mve_undefined
 319 {
 320   UNDEF_SIZE,                   /* undefined size.  */
 321   UNDEF_SIZE_0,                 /* undefined because size == 0.  */
 322   UNDEF_SIZE_2,                 /* undefined because size == 2.  */
 323   UNDEF_SIZE_3,                 /* undefined because size == 3.  */
 324   UNDEF_SIZE_LE_1,              /* undefined because size <= 1.  */
 325   UNDEF_SIZE_NOT_0,             /* undefined because size != 0.  */
 326   UNDEF_SIZE_NOT_2,             /* undefined because size != 2.  */
 327   UNDEF_SIZE_NOT_3,             /* undefined because size != 3.  */
 328   UNDEF_NOT_UNS_SIZE_0,         /* undefined because U == 0 and
 329                                    size == 0.  */
 330   UNDEF_NOT_UNS_SIZE_1,         /* undefined because U == 0 and
 331                                    size == 1.  */
 332   UNDEF_NOT_UNSIGNED,           /* undefined because U == 0.  */
 333   UNDEF_VCVT_IMM6,              /* imm6 < 32.  */
 334   UNDEF_VCVT_FSI_IMM6,          /* fsi = 0 and 32 >= imm6 <= 47.  */
 335   UNDEF_BAD_OP1_OP2,            /* undefined with op2 = 2 and
 336                                    op1 == (0 or 1).  */
 337   UNDEF_BAD_U_OP1_OP2,          /* undefined with U = 1 and
 338                                    op2 == 0 and op1 == (0 or 1).  */
 339   UNDEF_OP_0_BAD_CMODE,         /* undefined because op == 0 and cmode
 340                                    in {0xx1, x0x1}.  */
 341   UNDEF_XCHG_UNS,               /* undefined because X == 1 and U == 1.  */
 342   UNDEF_NONE                    /* no undefined behavior.  */
 343 };
 344
 345 struct opcode32
 346 {
 347   arm_feature_set arch;         /* Architecture defining this insn.  */
 348   unsigned long value;          /* If arch is 0 then value is a sentinel.  */
 349   unsigned long mask;           /* Recognise insn if (op & mask) == value.  */
 350   const char *  assembler;      /* How to disassemble this insn.  */
 351 };
 352
 353 struct cdeopcode32
 354 {
 355   arm_feature_set arch;         /* Architecture defining this insn.  */
 356   uint8_t coproc_shift;         /* coproc is this far into op.  */
 357   uint16_t coproc_mask;         /* Length of coproc field in op.  */
 358   unsigned long value;          /* If arch is 0 then value is a sentinel.  */
 359   unsigned long mask;           /* Recognise insn if (op & mask) == value.  */
 360   const char *  assembler;      /* How to disassemble this insn.  */
 361 };
 362
 363 /* MVE opcodes.  */
 364
 365 struct mopcode32
 366 {
 367   arm_feature_set arch;         /* Architecture defining this insn.  */
 368   enum mve_instructions mve_op;  /* Specific mve instruction for faster
 369                                     decoding.  */
 370   unsigned long value;          /* If arch is 0 then value is a sentinel.  */
 371   unsigned long mask;           /* Recognise insn if (op & mask) == value.  */
 372   const char *  assembler;      /* How to disassemble this insn.  */
 373 };
 374
 375 enum isa {
 376   ANY,
 377   T32,
 378   ARM
 379 };
 380
 381
 382 /* Shared (between Arm and Thumb mode) opcode.  */
 383 struct sopcode32
 384 {
 385   enum isa isa;                 /* Execution mode instruction availability.  */
 386   arm_feature_set arch;         /* Architecture defining this insn.  */
 387   unsigned long value;          /* If arch is 0 then value is a sentinel.  */
 388   unsigned long mask;           /* Recognise insn if (op & mask) == value.  */
 389   const char *  assembler;      /* How to disassemble this insn.  */
 390 };
 391
 392 struct opcode16
 393 {
 394   arm_feature_set arch;         /* Architecture defining this insn.  */
 395   unsigned short value, mask;   /* Recognise insn if (op & mask) == value.  */
 396   const char *assembler;        /* How to disassemble this insn.  */
 397 };
 398
 399 /* print_insn_coprocessor recognizes the following format control codes:
 400
 401    %%                   %
 402
 403    %c                   print condition code (always bits 28-31 in ARM mode)
 404    %b                   print condition code allowing cp_num == 9
 405    %q                   print shifter argument
 406    %u                   print condition code (unconditional in ARM mode,
 407                           UNPREDICTABLE if not AL in Thumb)
 408    %A                   print address for ldc/stc/ldf/stf instruction
 409    %B                   print vstm/vldm register list
 410    %C                   print vscclrm register list
 411    %I                   print cirrus signed shift immediate: bits 0..3|4..6
 412    %J                   print register for VLDR instruction
 413    %K                   print address for VLDR instruction
 414    %F                   print the COUNT field of a LFM/SFM instruction.
 415    %P                   print floating point precision in arithmetic insn
 416    %Q                   print floating point precision in ldf/stf insn
 417    %R                   print floating point rounding mode
 418
 419    %<bitfield>c         print as a condition code (for vsel)
 420    %<bitfield>r         print as an ARM register
 421    %<bitfield>R         as %<>r but r15 is UNPREDICTABLE
 422    %<bitfield>ru        as %<>r but each u register must be unique.
 423    %<bitfield>d         print the bitfield in decimal
 424    %<bitfield>k         print immediate for VFPv3 conversion instruction
 425    %<bitfield>x         print the bitfield in hex
 426    %<bitfield>X         print the bitfield as 1 hex digit without leading "0x"
 427    %<bitfield>f         print a floating point constant if >7 else a
 428                         floating point register
 429    %<bitfield>w         print as an iWMMXt width field - [bhwd]ss/us
 430    %<bitfield>g         print as an iWMMXt 64-bit register
 431    %<bitfield>G         print as an iWMMXt general purpose or control register
 432    %<bitfield>D         print as a NEON D register
 433    %<bitfield>Q         print as a NEON Q register
 434    %<bitfield>V         print as a NEON D or Q register
 435    %<bitfield>E         print a quarter-float immediate value
 436
 437    %y<code>             print a single precision VFP reg.
 438                           Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
 439    %z<code>             print a double precision VFP reg
 440                           Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
 441
 442    %<bitfield>'c        print specified char iff bitfield is all ones
 443    %<bitfield>`c        print specified char iff bitfield is all zeroes
 444    %<bitfield>?ab...    select from array of values in big endian order
 445
 446    %L                   print as an iWMMXt N/M width field.
 447    %Z                   print the Immediate of a WSHUFH instruction.
 448    %l                   like 'A' except use byte offsets for 'B' & 'H'
 449                         versions.
 450    %i                   print 5-bit immediate in bits 8,3..0
 451                         (print "32" when 0)
 452    %r                   print register offset address for wldt/wstr instruction.  */
 453
 454 enum opcode_sentinel_enum
 455 {
 456   SENTINEL_IWMMXT_START = 1,
 457   SENTINEL_IWMMXT_END,
 458   SENTINEL_GENERIC_START
 459 } opcode_sentinels;
 460
 461 #define UNDEFINED_INSTRUCTION      "\t\t; <UNDEFINED> instruction: %0-31x"
 462 #define UNKNOWN_INSTRUCTION_32BIT  "\t\t; <UNDEFINED> instruction: %08x"
 463 #define UNKNOWN_INSTRUCTION_16BIT  "\t\t; <UNDEFINED> instruction: %04x"
 464 #define UNPREDICTABLE_INSTRUCTION  "\t; <UNPREDICTABLE>"
 465
 466 /* Common coprocessor opcodes shared between Arm and Thumb-2.  */
 467
 468 /* print_insn_cde recognizes the following format control codes:
 469
 470    %%                   %
 471
 472    %a                   print 'a' iff bit 28 is 1
 473    %p                   print bits 8-10 as coprocessor
 474    %<bitfield>d         print as decimal
 475    %<bitfield>r         print as an ARM register
 476    %<bitfield>n         print as an ARM register but r15 is APSR_nzcv
 477    %<bitfield>T         print as an ARM register + 1
 478    %<bitfield>R         as %r but r13 is UNPREDICTABLE
 479    %<bitfield>S         as %r but rX where X > 10 is UNPREDICTABLE
 480    %j                   print immediate taken from bits (16..21,7,0..5)
 481    %k                   print immediate taken from bits (20..21,7,0..5).
 482    %l                   print immediate taken from bits (20..22,7,4..5).  */
 483
 484 /* At the moment there is only one valid position for the coprocessor number,
 485    and hence that's encoded in the macro below.  */
 486 #define CDE_OPCODE(ARCH, VALUE, MASK, ASM) \
 487   { ARCH, 8, 7, VALUE, MASK, ASM }
 488 static const struct cdeopcode32 cde_opcodes[] =
 489 {
 490   /* Custom Datapath Extension instructions.  */
 491   CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
 492               0xee000000, 0xefc00840,
 493               "cx1%a\t%p, %12-15n, #%0-5,7,16-21d"),
 494   CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
 495               0xee000040, 0xefc00840,
 496               "cx1d%a\t%p, %12-15S, %12-15T, #%0-5,7,16-21d"),
 497
 498   CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
 499               0xee400000, 0xefc00840,
 500               "cx2%a\t%p, %12-15n, %16-19n, #%0-5,7,20-21d"),
 501   CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
 502               0xee400040, 0xefc00840,
 503               "cx2d%a\t%p, %12-15S, %12-15T, %16-19n, #%0-5,7,20-21d"),
 504
 505   CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
 506               0xee800000, 0xef800840,
 507               "cx3%a\t%p, %0-3n, %16-19n, %12-15n, #%4-5,7,20-22d"),
 508   CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
 509               0xee800040, 0xef800840,
 510              "cx3d%a\t%p, %0-3S, %0-3T, %16-19n, %12-15n, #%4-5,7,20-22d"),
 511
 512   CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
 513               0xec200000, 0xeeb00840,
 514               "vcx1%a\t%p, %12-15,22V, #%0-5,7,16-19d"),
 515   CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
 516               0xec200040, 0xeeb00840,
 517               "vcx1%a\t%p, %12-15,22V, #%0-5,7,16-19,24d"),
 518
 519   CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
 520               0xec300000, 0xeeb00840,
 521               "vcx2%a\t%p, %12-15,22V, %0-3,5V, #%4,7,16-19d"),
 522   CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
 523               0xec300040, 0xeeb00840,
 524               "vcx2%a\t%p, %12-15,22V, %0-3,5V, #%4,7,16-19,24d"),
 525
 526   CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
 527               0xec800000, 0xee800840,
 528               "vcx3%a\t%p, %12-15,22V, %16-19,7V, %0-3,5V, #%4,20-21d"),
 529   CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
 530               0xec800040, 0xee800840,
 531               "vcx3%a\t%p, %12-15,22V, %16-19,7V, %0-3,5V, #%4,20-21,24d"),
 532
 533   CDE_OPCODE (ARM_FEATURE_CORE_LOW (0), 0, 0, 0)
 534
 535 };
 536
 537 static const struct sopcode32 coprocessor_opcodes[] =
 538 {
 539   /* XScale instructions.  */
 540   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 541     0x0e200010, 0x0fff0ff0,
 542     "mia%c\tacc0, %0-3r, %12-15r"},
 543   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 544     0x0e280010, 0x0fff0ff0,
 545     "miaph%c\tacc0, %0-3r, %12-15r"},
 546   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 547     0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
 548   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 549     0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
 550   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 551     0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
 552
 553   /* Intel Wireless MMX technology instructions.  */
 554   {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
 555   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
 556     0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
 557   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 558     0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
 559   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 560     0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
 561   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 562     0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
 563   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 564     0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
 565   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 566     0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
 567   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 568     0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
 569   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 570     0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
 571   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 572     0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
 573   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 574     0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
 575   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 576     0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
 577   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 578     0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
 579   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 580     0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
 581   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 582     0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
 583   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 584     0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
 585   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 586     0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
 587   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 588     0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
 589   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 590     0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
 591   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 592     0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
 593   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 594     0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
 595   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 596     0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
 597   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 598     0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
 599   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 600     0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
 601   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 602     0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
 603   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 604     0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
 605   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 606     0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 607   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 608     0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 609   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 610     0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
 611   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 612     0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
 613   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 614     0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
 615   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 616     0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
 617   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 618     0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
 619   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 620     0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
 621   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 622     0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 623   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 624     0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
 625   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 626     0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
 627   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 628     0x0e800120, 0x0f800ff0,
 629     "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
 630   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 631     0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 632   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 633     0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
 634   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 635     0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
 636   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 637     0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
 638   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 639     0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
 640   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 641     0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
 642   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 643     0x0e8000a0, 0x0f800ff0,
 644     "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
 645   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 646     0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
 647   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 648     0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
 649   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 650     0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
 651   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 652     0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
 653   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 654     0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
 655   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 656     0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 657   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 658     0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
 659   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 660     0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
 661   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 662     0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
 663   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 664     0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
 665   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 666     0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
 667   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 668     0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
 669   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 670     0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
 671   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 672     0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
 673   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 674     0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
 675   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 676     0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
 677   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 678     0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
 679   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 680     0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
 681   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 682     0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
 683   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 684     0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
 685   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 686     0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
 687   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 688     0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
 689   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 690     0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
 691   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 692     0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 693   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 694     0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
 695   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 696     0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
 697   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 698     0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
 699   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 700     0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
 701   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 702     0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 703   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 704     0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 705   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 706     0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
 707   {ANY, ARM_FEATURE_CORE_LOW (0),
 708     SENTINEL_IWMMXT_END, 0, "" },
 709
 710   /* Floating point coprocessor (FPA) instructions.  */
 711   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 712     0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 713   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 714     0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 715   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 716     0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 717   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 718     0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 719   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 720     0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 721   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 722     0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 723   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 724     0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
 725   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 726     0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
 727   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 728     0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 729   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 730     0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
 731   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 732     0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
 733   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 734     0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
 735   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 736     0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
 737   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 738     0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
 739   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 740     0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
 741   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 742     0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
 743   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 744     0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
 745   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 746     0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
 747   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 748     0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
 749   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 750     0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
 751   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 752     0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
 753   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 754     0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
 755   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 756     0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
 757   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 758     0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
 759   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 760     0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
 761   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 762     0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
 763   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 764     0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
 765   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 766     0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
 767   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 768     0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
 769   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 770     0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
 771   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 772     0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
 773   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 774     0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
 775   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 776     0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
 777   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 778     0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
 779   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 780     0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
 781   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 782     0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
 783   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 784     0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
 785   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 786     0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
 787   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 788     0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
 789   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 790     0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
 791   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 792     0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
 793   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
 794     0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
 795   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
 796     0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
 797
 798   /* Armv8.1-M Mainline instructions.  */
 799   {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
 800     0xec9f0b00, 0xffbf0f01, "vscclrm%c\t%C"},
 801   {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
 802     0xec9f0a00, 0xffbf0f00, "vscclrm%c\t%C"},
 803
 804   /* ARMv8-M Mainline Security Extensions instructions.  */
 805   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
 806     0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
 807   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
 808     0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
 809
 810   /* Register load/store.  */
 811   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 812     0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
 813   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 814     0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
 815   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 816     0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
 817   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 818     0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
 819   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 820     0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
 821   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 822     0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
 823   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 824     0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
 825   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 826     0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
 827   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 828     0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
 829   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 830     0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
 831   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 832     0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
 833   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 834     0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
 835   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 836     0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
 837   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 838     0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
 839   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 840     0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
 841   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 842     0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
 843   {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
 844     0xec100f80, 0xfe101f80, "vldr%c\t%J, %K"},
 845   {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
 846     0xec000f80, 0xfe101f80, "vstr%c\t%J, %K"},
 847
 848   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 849     0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
 850   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 851     0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
 852   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 853     0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
 854   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 855     0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
 856
 857   /* Data transfer between ARM and NEON registers.  */
 858   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 859     0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
 860   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 861     0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
 862   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 863     0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
 864   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 865     0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
 866   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 867     0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
 868   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 869     0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
 870   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 871     0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
 872   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 873     0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
 874   /* Half-precision conversion instructions.  */
 875   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 876     0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
 877   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 878     0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
 879   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
 880     0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
 881   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
 882     0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
 883
 884   /* Floating point coprocessor (VFP) instructions.  */
 885   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 886     0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
 887   {ANY, ARM_FEATURE (0, ARM_EXT2_V8_1M_MAIN, FPU_VFP_EXT_V1xD),
 888     0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
 889   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
 890     0x0ee20a10, 0x0fff0fff, "vmsr%c\tfpscr_nzcvqc, %12-15r"},
 891   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 892     0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
 893   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 894     0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
 895   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 896     0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"},
 897   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 898     0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
 899   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 900     0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
 901   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 902     0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
 903   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
 904     0x0eec0a10, 0x0fff0fff, "vmsr%c\tvpr, %12-15r"},
 905   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
 906     0x0eed0a10, 0x0fff0fff, "vmsr%c\tp0, %12-15r"},
 907   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
 908     0x0eee0a10, 0x0fff0fff, "vmsr%c\tfpcxt_ns, %12-15r"},
 909   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
 910     0x0eef0a10, 0x0fff0fff, "vmsr%c\tfpcxt_s, %12-15r"},
 911   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 912     0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
 913   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 914     0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
 915   {ANY, ARM_FEATURE (0, ARM_EXT2_V8_1M_MAIN, FPU_VFP_EXT_V1xD),
 916     0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
 917   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
 918     0x0ef20a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr_nzcvqc"},
 919   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 920     0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"},
 921   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 922     0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
 923   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 924     0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
 925   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 926     0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
 927   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 928     0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
 929   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 930     0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
 931   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
 932     0x0efc0a10, 0x0fff0fff, "vmrs%c\t%12-15r, vpr"},
 933   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
 934     0x0efd0a10, 0x0fff0fff, "vmrs%c\t%12-15r, p0"},
 935   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
 936     0x0efe0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpcxt_ns"},
 937   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
 938     0x0eff0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpcxt_s"},
 939   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 940     0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
 941   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 942     0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
 943   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 944     0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
 945   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 946     0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
 947   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 948     0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
 949   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 950     0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
 951   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 952     0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
 953   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 954     0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
 955   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 956     0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
 957   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 958     0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
 959   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 960     0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
 961   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 962     0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
 963   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 964     0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
 965   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 966     0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
 967   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 968     0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
 969   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 970     0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
 971   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 972     0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
 973   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 974     0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
 975   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 976     0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
 977   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 978     0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
 979   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 980     0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
 981   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 982     0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
 983   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
 984     0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
 985   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
 986     0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
 987   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 988     0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
 989   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 990     0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
 991   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
 992     0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
 993   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
 994     0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
 995   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 996     0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
 997   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
 998     0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
 999   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
1000     0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
1001   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
1002     0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
1003   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
1004     0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
1005   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
1006     0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
1007   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
1008     0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
1009   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
1010     0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
1011   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
1012     0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
1013   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
1014     0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
1015   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
1016     0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
1017   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
1018     0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
1019   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
1020     0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
1021   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
1022     0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
1023   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
1024     0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
1025   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
1026     0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
1027   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
1028     0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
1029   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
1030     0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
1031   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
1032     0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
1033   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
1034     0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
1035   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
1036     0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
1037   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
1038     0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
1039   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
1040     0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
1041   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
1042     0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
1043
1044   /* Cirrus coprocessor instructions.  */
1045   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1046     0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
1047   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1048     0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
1049   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1050     0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
1051   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1052     0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
1053   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1054     0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
1055   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1056     0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
1057   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1058     0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
1059   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1060     0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
1061   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1062     0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
1063   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1064     0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
1065   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1066     0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
1067   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1068     0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
1069   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1070     0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
1071   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1072     0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
1073   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1074     0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
1075   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1076     0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
1077   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1078     0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
1079   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1080     0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
1081   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1082     0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
1083   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1084     0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
1085   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1086     0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
1087   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1088     0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
1089   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1090     0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
1091   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1092     0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
1093   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1094     0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
1095   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1096     0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
1097   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1098     0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
1099   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1100     0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
1101   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1102     0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
1103   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1104     0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
1105   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1106     0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
1107   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1108     0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
1109   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1110     0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
1111   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1112     0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
1113   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1114     0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
1115   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1116     0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
1117   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1118     0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
1119   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1120     0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
1121   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1122     0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
1123   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1124     0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
1125   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1126     0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
1127   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1128     0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
1129   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1130     0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
1131   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1132     0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
1133   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1134     0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
1135   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1136     0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
1137   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1138     0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
1139   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1140     0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
1141   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1142     0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
1143   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1144     0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
1145   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1146     0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
1147   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1148     0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
1149   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1150     0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
1151   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1152     0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
1153   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1154     0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
1155   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1156     0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
1157   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1158     0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
1159   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1160     0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
1161   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1162     0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
1163   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1164     0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
1165   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1166     0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
1167   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1168     0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
1169   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1170     0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
1171   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1172     0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
1173   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1174     0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
1175   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1176     0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
1177   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1178     0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
1179   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1180     0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
1181   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1182     0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
1183   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1184     0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
1185   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1186     0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
1187   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1188     0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
1189   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1190     0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1191   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1192     0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
1193   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1194     0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1195   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1196     0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
1197   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1198     0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1199   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1200     0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
1201   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1202     0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1203   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1204     0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1205   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1206     0x0e000600, 0x0ff00f10,
1207     "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1208   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1209     0x0e100600, 0x0ff00f10,
1210     "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1211   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1212     0x0e200600, 0x0ff00f10,
1213     "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
1214   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1215     0x0e300600, 0x0ff00f10,
1216     "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
1217
1218   /* VFP Fused multiply add instructions.  */
1219   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1220     0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
1221   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1222     0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
1223   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1224     0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
1225   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1226     0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
1227   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1228     0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
1229   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1230     0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
1231   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1232     0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
1233   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1234     0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
1235
1236   /* FP v5.  */
1237   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1238     0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
1239   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1240     0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
1241   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1242     0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
1243   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1244     0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
1245   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1246     0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
1247   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1248     0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
1249   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1250     0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
1251   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1252     0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
1253   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1254     0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
1255   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1256     0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
1257   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1258     0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
1259   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1260     0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
1261
1262   {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
1263   /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8.  */
1264   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1265     0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
1266   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1267     0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
1268   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1269     0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
1270   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1271     0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
1272   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1273     0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
1274   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1275     0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
1276   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1277     0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
1278   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1279     0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"},
1280   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1281     0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
1282   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1283     0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"},
1284
1285   /* BFloat16 instructions.  */
1286   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1287     0x0eb30940, 0x0fbf0f50, "vcvt%7?tb%b.bf16.f32\t%y1, %y0"},
1288
1289   /* Dot Product instructions in the space of coprocessor 13.  */
1290   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
1291     0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
1292   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
1293     0xfe200d00, 0xff200f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"},
1294
1295   /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8.  */
1296   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1297     0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
1298   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1299     0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
1300   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1301     0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
1302   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1303     0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
1304   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1305     0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
1306   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1307     0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
1308   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1309     0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
1310   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1311     0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
1312
1313   /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
1314      cp_num: bit <11:8> == 0b1001.
1315      cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE.  */
1316   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1317     0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
1318   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1319     0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
1320   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1321     0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
1322   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1323     0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
1324   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1325     0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
1326   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1327     0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
1328   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1329     0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
1330   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1331     0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
1332   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1333     0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
1334   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1335     0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
1336   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1337     0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
1338   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1339     0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
1340   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1341     0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
1342   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1343     0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
1344   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1345     0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
1346   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1347     0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
1348   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1349     0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
1350   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1351     0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
1352   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1353     0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
1354   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1355     0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
1356   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1357     0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
1358   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1359     0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
1360   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1361     0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
1362   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1363     0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
1364   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1365     0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
1366   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1367     0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
1368   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1369     0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
1370   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1371     0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
1372   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1373     0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
1374   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1375     0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
1376   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1377     0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
1378   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1379     0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
1380   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1381     0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
1382   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1383     0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
1384   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1385     0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
1386
1387   /* ARMv8.3 javascript conversion instruction.  */
1388   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1389     0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
1390
1391   {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
1392 };
1393
1394 /* Generic coprocessor instructions.  These are only matched if a more specific
1395    SIMD or co-processor instruction does not match first.  */
1396
1397 static const struct sopcode32 generic_coprocessor_opcodes[] =
1398 {
1399   /* Generic coprocessor instructions.  */
1400   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1401     0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
1402   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1403     0x0c500000, 0x0ff00000,
1404     "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
1405   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1406     0x0e000000, 0x0f000010,
1407     "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
1408   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1409     0x0e10f010, 0x0f10f010,
1410     "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
1411   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1412     0x0e100010, 0x0f100010,
1413     "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1414   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1415     0x0e000010, 0x0f100010,
1416     "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
1417   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1418     0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
1419   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1420     0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
1421
1422   /* V6 coprocessor instructions.  */
1423   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1424     0xfc500000, 0xfff00000,
1425     "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
1426   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1427     0xfc400000, 0xfff00000,
1428     "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
1429
1430   /* V5 coprocessor instructions.  */
1431   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1432     0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
1433   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1434     0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
1435   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1436     0xfe000000, 0xff000010,
1437     "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
1438   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1439     0xfe000010, 0xff100010,
1440     "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
1441   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1442     0xfe100010, 0xff100010,
1443     "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1444
1445   {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
1446 };
1447
1448 /* Neon opcode table:  This does not encode the top byte -- that is
1449    checked by the print_insn_neon routine, as it depends on whether we are
1450    doing thumb32 or arm32 disassembly.  */
1451
1452 /* print_insn_neon recognizes the following format control codes:
1453
1454    %%                   %
1455
1456    %c                   print condition code
1457    %u                   print condition code (unconditional in ARM mode,
1458                           UNPREDICTABLE if not AL in Thumb)
1459    %A                   print v{st,ld}[1234] operands
1460    %B                   print v{st,ld}[1234] any one operands
1461    %C                   print v{st,ld}[1234] single->all operands
1462    %D                   print scalar
1463    %E                   print vmov, vmvn, vorr, vbic encoded constant
1464    %F                   print vtbl,vtbx register list
1465
1466    %<bitfield>r         print as an ARM register
1467    %<bitfield>d         print the bitfield in decimal
1468    %<bitfield>e         print the 2^N - bitfield in decimal
1469    %<bitfield>D         print as a NEON D register
1470    %<bitfield>Q         print as a NEON Q register
1471    %<bitfield>R         print as a NEON D or Q register
1472    %<bitfield>Sn        print byte scaled width limited by n
1473    %<bitfield>Tn        print short scaled width limited by n
1474    %<bitfield>Un        print long scaled width limited by n
1475
1476    %<bitfield>'c        print specified char iff bitfield is all ones
1477    %<bitfield>`c        print specified char iff bitfield is all zeroes
1478    %<bitfield>?ab...    select from array of values in big endian order.  */
1479
1480 static const struct opcode32 neon_opcodes[] =
1481 {
1482   /* Extract.  */
1483   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1484     0xf2b00840, 0xffb00850,
1485     "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1486   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1487     0xf2b00000, 0xffb00810,
1488     "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1489
1490   /* Data transfer between ARM and NEON registers.  */
1491   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1492     0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
1493   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1494     0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
1495   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1496     0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
1497   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1498     0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
1499   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1500     0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
1501   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1502     0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
1503
1504   /* Move data element to all lanes.  */
1505   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1506     0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
1507   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1508     0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
1509   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1510     0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
1511
1512   /* Table lookup.  */
1513   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1514     0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1515   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1516     0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1517
1518   /* Half-precision conversions.  */
1519   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1520     0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1521   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1522     0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
1523
1524   /* NEON fused multiply add instructions.  */
1525   {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
1526     0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1527   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1528     0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1529   {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
1530     0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1531   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1532     0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1533
1534   /* BFloat16 instructions.  */
1535   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1536     0xfc000d00, 0xffb00f10, "vdot.bf16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1537   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1538     0xfe000d00, 0xffb00f10, "vdot.bf16\t%12-15,22R, %16-19,7R, d%0-3d[%5d]"},
1539   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1540     0xfc000c40, 0xffb00f50, "vmmla.bf16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1541   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1542     0xf3b60640, 0xffbf0fd0, "vcvt%c.bf16.f32\t%12-15,22D, %0-3,5Q"},
1543   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1544     0xfc300810, 0xffb00f10, "vfma%6?tb.bf16\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1545   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1546     0xfe300810, 0xffb00f10, "vfma%6?tb.bf16\t%12-15,22Q, %16-19,7Q, %0-2D[%3,5d]"},
1547
1548   /* Matrix Multiply instructions.  */
1549   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1550     0xfc200c40, 0xffb00f50, "vsmmla.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1551   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1552     0xfc200c50, 0xffb00f50, "vummla.u8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1553   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1554     0xfca00c40, 0xffb00f50, "vusmmla.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1555   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1556     0xfca00d00, 0xffb00f10, "vusdot.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1557   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1558     0xfe800d00, 0xffb00f10, "vusdot.s8\t%12-15,22R, %16-19,7R, d%0-3d[%5d]"},
1559   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1560     0xfe800d10, 0xffb00f10, "vsudot.u8\t%12-15,22R, %16-19,7R, d%0-3d[%5d]"},
1561
1562   /* Two registers, miscellaneous.  */
1563   {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1564     0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
1565   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1566     0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
1567   {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1568     0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
1569   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1570     0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
1571   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1572     0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1573   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1574     0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1575   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1576     0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1577   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1578     0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1579   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1580     0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1581   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1582     0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1583   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1584     0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1585   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1586     0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1587   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1588     0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1589   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1590     0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1591   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1592     0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1593   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1594     0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1595   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1596     0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1597   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1598     0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1599   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1600     0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1601   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1602     0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1603   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1604     0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1605   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1606     0xf3b20300, 0xffb30fd0,
1607     "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1608   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1609     0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1610   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1611     0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1612   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1613     0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1614   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1615     0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1616   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1617     0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1618   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1619     0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1620   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1621     0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1622   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1623     0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1624   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1625     0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1626   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1627     0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1628   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1629     0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1630   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1631     0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1632   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1633     0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1634   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1635     0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1636   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1637     0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1638   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1639     0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1640   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1641     0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1642   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1643     0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1644   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1645     0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1646   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1647     0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1648   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1649     0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1650   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1651     0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1652   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1653     0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1654   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1655     0xf3bb0600, 0xffbf0e10,
1656     "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
1657   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1658     0xf3b70600, 0xffbf0e10,
1659     "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
1660
1661   /* Three registers of the same length.  */
1662   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1663     0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1664   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1665     0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1666   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1667     0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1668   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1669     0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1670   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1671     0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1672   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1673     0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1674   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1675     0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1676   {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1677     0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1678   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1679     0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1680   {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1681     0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1682   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1683     0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1684   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1685     0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1686   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1687     0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1688   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1689     0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1690   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1691     0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1692   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1693     0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1694   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1695     0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1696   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1697     0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1698   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1699     0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1700   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1701     0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1702   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1703     0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1704   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1705     0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1706   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1707     0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1708   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1709     0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1710   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1711     0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1712   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1713     0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1714   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1715     0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1716   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1717     0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1718   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1719     0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1720   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1721     0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1722   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1723     0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1724   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1725     0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1726   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1727     0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1728   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1729     0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1730   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1731     0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1732   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1733     0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1734   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1735     0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1736   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1737     0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1738   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1739     0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1740   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1741     0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1742   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1743     0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1744   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1745     0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1746   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1747     0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1748   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1749     0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1750   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1751     0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1752   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1753     0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1754   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1755     0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1756   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1757     0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1758   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1759     0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1760   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1761     0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1762   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1763     0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1764   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1765     0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1766   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1767     0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1768   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1769     0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1770   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1771     0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1772   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1773     0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1774   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1775     0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1776   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1777     0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1778   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1779     0xf2000b00, 0xff800f10,
1780     "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1781   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1782     0xf2000b10, 0xff800f10,
1783     "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1784   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1785     0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1786   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1787     0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1788   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1789     0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1790   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1791     0xf3000b00, 0xff800f10,
1792     "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1793   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1794     0xf2000000, 0xfe800f10,
1795     "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1796   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1797     0xf2000010, 0xfe800f10,
1798     "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1799   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1800     0xf2000100, 0xfe800f10,
1801     "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1802   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1803     0xf2000200, 0xfe800f10,
1804     "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1805   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1806     0xf2000210, 0xfe800f10,
1807     "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1808   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1809     0xf2000300, 0xfe800f10,
1810     "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1811   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1812     0xf2000310, 0xfe800f10,
1813     "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1814   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1815     0xf2000400, 0xfe800f10,
1816     "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1817   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1818     0xf2000410, 0xfe800f10,
1819     "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1820   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1821     0xf2000500, 0xfe800f10,
1822     "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1823   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1824     0xf2000510, 0xfe800f10,
1825     "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1826   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1827     0xf2000600, 0xfe800f10,
1828     "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1829   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1830     0xf2000610, 0xfe800f10,
1831     "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1832   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1833     0xf2000700, 0xfe800f10,
1834     "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1835   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1836     0xf2000710, 0xfe800f10,
1837     "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1838   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1839     0xf2000910, 0xfe800f10,
1840     "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1841   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1842     0xf2000a00, 0xfe800f10,
1843     "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1844   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1845     0xf2000a10, 0xfe800f10,
1846     "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1847   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1848     0xf3000b10, 0xff800f10,
1849     "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1850   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1851     0xf3000c10, 0xff800f10,
1852     "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1853
1854   /* One register and an immediate value.  */
1855   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1856     0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1857   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1858     0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1859   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1860     0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1861   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1862     0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1863   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1864     0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1865   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1866     0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1867   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1868     0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1869   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1870     0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1871   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1872     0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1873   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1874     0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1875   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1876     0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1877   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1878     0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1879   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1880     0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
1881
1882   /* Two registers and a shift amount.  */
1883   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1884     0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1885   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1886     0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1887   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1888     0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1889   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1890     0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1891   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1892     0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1893   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1894     0xf2880950, 0xfeb80fd0,
1895     "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1896   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1897     0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1898   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1899     0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1900   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1901     0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1902   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1903     0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1904   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1905     0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1906   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1907     0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1908   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1909     0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1910   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1911     0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1912   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1913     0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1914   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1915     0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1916   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1917     0xf2900950, 0xfeb00fd0,
1918     "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1919   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1920     0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1921   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1922     0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1923   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1924     0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1925   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1926     0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1927   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1928     0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1929   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1930     0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1931   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1932     0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1933   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1934     0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1935   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1936     0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1937   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1938     0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1939   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1940     0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1941   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1942     0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1943   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1944     0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1945   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1946     0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1947   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1948     0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1949   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1950     0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1951   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1952     0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1953   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1954     0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1955   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1956     0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1957   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1958     0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1959   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1960     0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1961   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1962     0xf2a00950, 0xfea00fd0,
1963     "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1964   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1965     0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1966   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1967     0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1968   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1969     0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1970   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1971     0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1972   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1973     0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1974   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1975     0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1976   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1977     0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1978   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1979     0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1980   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1981     0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1982   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1983     0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1984   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1985     0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1986   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1987     0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1988   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1989     0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1990   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1991     0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1992   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1993     0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1994   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1995     0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1996   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1997     0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1998   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1999     0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
2000   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2001     0xf2a00e10, 0xfea00e90,
2002     "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
2003   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
2004     0xf2a00c10, 0xfea00e90,
2005     "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"},
2006
2007   /* Three registers of different lengths.  */
2008   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
2009     0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2010   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2011     0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2012   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2013     0xf2800400, 0xff800f50,
2014     "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
2015   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2016     0xf2800600, 0xff800f50,
2017     "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
2018   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2019     0xf2800900, 0xff800f50,
2020     "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2021   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2022     0xf2800b00, 0xff800f50,
2023     "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2024   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2025     0xf2800d00, 0xff800f50,
2026     "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2027   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2028     0xf3800400, 0xff800f50,
2029     "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
2030   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2031     0xf3800600, 0xff800f50,
2032     "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
2033   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2034     0xf2800000, 0xfe800f50,
2035     "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2036   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2037     0xf2800100, 0xfe800f50,
2038     "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
2039   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2040     0xf2800200, 0xfe800f50,
2041     "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2042   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2043     0xf2800300, 0xfe800f50,
2044     "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
2045   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2046     0xf2800500, 0xfe800f50,
2047     "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2048   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2049     0xf2800700, 0xfe800f50,
2050     "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2051   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2052     0xf2800800, 0xfe800f50,
2053     "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2054   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2055     0xf2800a00, 0xfe800f50,
2056     "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2057   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2058     0xf2800c00, 0xfe800f50,
2059     "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2060
2061   /* Two registers and a scalar.  */
2062   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2063     0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2064   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2065     0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
2066   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2067     0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
2068   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2069     0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2070   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2071     0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2072   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2073     0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2074   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2075     0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
2076   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2077     0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2078   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2079     0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2080   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2081     0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
2082   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2083     0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
2084   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2085     0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2086   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2087     0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2088   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2089     0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2090   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2091     0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2092   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2093     0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
2094   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2095     0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
2096   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2097     0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2098   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2099     0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
2100   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2101     0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
2102   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2103     0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2104   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2105     0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
2106   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2107     0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
2108   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2109     0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2110   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2111     0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2112   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2113     0xf2800240, 0xfe800f50,
2114     "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2115   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2116     0xf2800640, 0xfe800f50,
2117     "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2118   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2119     0xf2800a40, 0xfe800f50,
2120     "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2121   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
2122     0xf2800e40, 0xff800f50,
2123    "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2124   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
2125     0xf2800f40, 0xff800f50,
2126    "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2127   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
2128     0xf3800e40, 0xff800f50,
2129    "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2130   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
2131     0xf3800f40, 0xff800f50,
2132    "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
2133   },
2134
2135   /* Element and structure load/store.  */
2136   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2137     0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
2138   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2139     0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
2140   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2141     0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
2142   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2143     0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
2144   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2145     0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
2146   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2147     0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2148   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2149     0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2150   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2151     0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
2152   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2153     0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
2154   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2155     0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2156   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2157     0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2158   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2159     0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2160   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2161     0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2162   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2163     0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2164   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2165     0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
2166   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2167     0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
2168   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2169     0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
2170   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2171     0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
2172   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2173     0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
2174
2175   {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
2176 };
2177
2178 /* mve opcode table.  */
2179
2180 /* print_insn_mve recognizes the following format control codes:
2181
2182    %%                   %
2183
2184    %a                   print '+' or '-' or imm offset in vldr[bhwd] and
2185                         vstr[bhwd]
2186    %c                   print condition code
2187    %d                   print addr mode of MVE vldr[bhw] and vstr[bhw]
2188    %u                   print 'U' (unsigned) or 'S' for various mve instructions
2189    %i                   print MVE predicate(s) for vpt and vpst
2190    %j                   print a 5-bit immediate from hw2[14:12,7:6]
2191    %k                   print 48 if the 7th position bit is set else print 64.
2192    %m                   print rounding mode for vcvt and vrint
2193    %n                   print vector comparison code for predicated instruction
2194    %s                   print size for various vcvt instructions
2195    %v                   print vector predicate for instruction in predicated
2196                         block
2197    %o                   print offset scaled for vldr[hwd] and vstr[hwd]
2198    %w                   print writeback mode for MVE v{st,ld}[24]
2199    %B                   print v{st,ld}[24] any one operands
2200    %E                   print vmov, vmvn, vorr, vbic encoded constant
2201    %N                   print generic index for vmov
2202    %T                   print bottom ('b') or top ('t') of source register
2203    %X                   print exchange field in vmla* instructions
2204
2205    %<bitfield>r         print as an ARM register
2206    %<bitfield>d         print the bitfield in decimal
2207    %<bitfield>A         print accumulate or not
2208    %<bitfield>c         print bitfield as a condition code
2209    %<bitfield>C         print bitfield as an inverted condition code
2210    %<bitfield>Q         print as a MVE Q register
2211    %<bitfield>F         print as a MVE S register
2212    %<bitfield>Z         as %<>r but r15 is ZR instead of PC and r13 is
2213                         UNPREDICTABLE
2214
2215    %<bitfield>S         as %<>r but r15 or r13 is UNPREDICTABLE
2216    %<bitfield>s         print size for vector predicate & non VMOV instructions
2217    %<bitfield>I         print carry flag or not
2218    %<bitfield>i         print immediate for vstr/vldr reg +/- imm
2219    %<bitfield>h         print high half of 64-bit destination reg
2220    %<bitfield>k         print immediate for vector conversion instruction
2221    %<bitfield>l         print low half of 64-bit destination reg
2222    %<bitfield>o         print rotate value for vcmul
2223    %<bitfield>u         print immediate value for vddup/vdwdup
2224    %<bitfield>x         print the bitfield in hex.
2225   */
2226
2227 static const struct mopcode32 mve_opcodes[] =
2228 {
2229   /* MVE.  */
2230
2231   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2232    MVE_VPST,
2233    0xfe310f4d, 0xffbf1fff,
2234    "vpst%i"
2235   },
2236
2237   /* Floating point VPT T1.  */
2238   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2239    MVE_VPT_FP_T1,
2240    0xee310f00, 0xefb10f50,
2241    "vpt%i.f%28s\t%n, %17-19Q, %1-3,5Q"},
2242   /* Floating point VPT T2.  */
2243   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2244    MVE_VPT_FP_T2,
2245    0xee310f40, 0xefb10f50,
2246    "vpt%i.f%28s\t%n, %17-19Q, %0-3Z"},
2247
2248   /* Vector VPT T1.  */
2249   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2250    MVE_VPT_VEC_T1,
2251    0xfe010f00, 0xff811f51,
2252    "vpt%i.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2253   /* Vector VPT T2.  */
2254   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2255    MVE_VPT_VEC_T2,
2256    0xfe010f01, 0xff811f51,
2257    "vpt%i.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2258   /* Vector VPT T3.  */
2259   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2260    MVE_VPT_VEC_T3,
2261    0xfe011f00, 0xff811f50,
2262    "vpt%i.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2263   /* Vector VPT T4.  */
2264   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2265    MVE_VPT_VEC_T4,
2266    0xfe010f40, 0xff811f70,
2267    "vpt%i.i%20-21s\t%n, %17-19Q, %0-3Z"},
2268   /* Vector VPT T5.  */
2269   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2270    MVE_VPT_VEC_T5,
2271    0xfe010f60, 0xff811f70,
2272    "vpt%i.u%20-21s\t%n, %17-19Q, %0-3Z"},
2273   /* Vector VPT T6.  */
2274   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2275    MVE_VPT_VEC_T6,
2276    0xfe011f40, 0xff811f50,
2277    "vpt%i.s%20-21s\t%n, %17-19Q, %0-3Z"},
2278
2279   /* Vector VBIC immediate.  */
2280   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2281    MVE_VBIC_IMM,
2282    0xef800070, 0xefb81070,
2283    "vbic%v.i%8-11s\t%13-15,22Q, %E"},
2284
2285   /* Vector VBIC register.  */
2286   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2287    MVE_VBIC_REG,
2288    0xef100150, 0xffb11f51,
2289    "vbic%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2290
2291   /* Vector VABAV.  */
2292   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2293    MVE_VABAV,
2294    0xee800f01, 0xefc10f51,
2295    "vabav%v.%u%20-21s\t%12-15r, %17-19,7Q, %1-3,5Q"},
2296
2297   /* Vector VABD floating point.  */
2298   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2299    MVE_VABD_FP,
2300    0xff200d40, 0xffa11f51,
2301    "vabd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2302
2303   /* Vector VABD.  */
2304   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2305    MVE_VABD_VEC,
2306    0xef000740, 0xef811f51,
2307    "vabd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2308
2309   /* Vector VABS floating point.  */
2310   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2311    MVE_VABS_FP,
2312    0xFFB10740, 0xFFB31FD1,
2313    "vabs%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
2314   /* Vector VABS.  */
2315   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2316    MVE_VABS_VEC,
2317    0xffb10340, 0xffb31fd1,
2318    "vabs%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2319
2320   /* Vector VADD floating point T1.  */
2321   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2322    MVE_VADD_FP_T1,
2323    0xef000d40, 0xffa11f51,
2324    "vadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2325   /* Vector VADD floating point T2.  */
2326   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2327    MVE_VADD_FP_T2,
2328    0xee300f40, 0xefb11f70,
2329    "vadd%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2330   /* Vector VADD T1.  */
2331   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2332    MVE_VADD_VEC_T1,
2333    0xef000840, 0xff811f51,
2334    "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2335   /* Vector VADD T2.  */
2336   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2337    MVE_VADD_VEC_T2,
2338    0xee010f40, 0xff811f70,
2339    "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2340
2341   /* Vector VADDLV.  */
2342   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2343    MVE_VADDLV,
2344    0xee890f00, 0xef8f1fd1,
2345    "vaddlv%5A%v.%u32\t%13-15l, %20-22h, %1-3Q"},
2346
2347   /* Vector VADDV.  */
2348   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2349    MVE_VADDV,
2350    0xeef10f00, 0xeff31fd1,
2351    "vaddv%5A%v.%u%18-19s\t%13-15l, %1-3Q"},
2352
2353   /* Vector VADC.  */
2354   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2355    MVE_VADC,
2356    0xee300f00, 0xffb10f51,
2357    "vadc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2358
2359   /* Vector VAND.  */
2360   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2361    MVE_VAND,
2362    0xef000150, 0xffb11f51,
2363    "vand%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2364
2365   /* Vector VBRSR register.  */
2366   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2367    MVE_VBRSR,
2368    0xfe011e60, 0xff811f70,
2369    "vbrsr%v.%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2370
2371   /* Vector VCADD floating point.  */
2372   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2373    MVE_VCADD_FP,
2374    0xfc800840, 0xfea11f51,
2375    "vcadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%24o"},
2376
2377   /* Vector VCADD.  */
2378   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2379    MVE_VCADD_VEC,
2380    0xfe000f00, 0xff810f51,
2381    "vcadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
2382
2383   /* Vector VCLS.  */
2384   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2385    MVE_VCLS,
2386    0xffb00440, 0xffb31fd1,
2387    "vcls%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2388
2389   /* Vector VCLZ.  */
2390   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2391    MVE_VCLZ,
2392    0xffb004c0, 0xffb31fd1,
2393    "vclz%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2394
2395   /* Vector VCMLA.  */
2396   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2397    MVE_VCMLA_FP,
2398    0xfc200840, 0xfe211f51,
2399    "vcmla%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%23-24o"},
2400
2401   /* Vector VCMP floating point T1.  */
2402   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2403    MVE_VCMP_FP_T1,
2404    0xee310f00, 0xeff1ef50,
2405    "vcmp%v.f%28s\t%n, %17-19Q, %1-3,5Q"},
2406
2407   /* Vector VCMP floating point T2.  */
2408   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2409    MVE_VCMP_FP_T2,
2410    0xee310f40, 0xeff1ef50,
2411    "vcmp%v.f%28s\t%n, %17-19Q, %0-3Z"},
2412
2413   /* Vector VCMP T1.  */
2414   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2415    MVE_VCMP_VEC_T1,
2416    0xfe010f00, 0xffc1ff51,
2417    "vcmp%v.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2418   /* Vector VCMP T2.  */
2419   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2420    MVE_VCMP_VEC_T2,
2421    0xfe010f01, 0xffc1ff51,
2422    "vcmp%v.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2423   /* Vector VCMP T3.  */
2424   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2425    MVE_VCMP_VEC_T3,
2426    0xfe011f00, 0xffc1ff50,
2427    "vcmp%v.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2428   /* Vector VCMP T4.  */
2429   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2430    MVE_VCMP_VEC_T4,
2431    0xfe010f40, 0xffc1ff70,
2432    "vcmp%v.i%20-21s\t%n, %17-19Q, %0-3Z"},
2433   /* Vector VCMP T5.  */
2434   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2435    MVE_VCMP_VEC_T5,
2436    0xfe010f60, 0xffc1ff70,
2437    "vcmp%v.u%20-21s\t%n, %17-19Q, %0-3Z"},
2438   /* Vector VCMP T6.  */
2439   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2440    MVE_VCMP_VEC_T6,
2441    0xfe011f40, 0xffc1ff50,
2442    "vcmp%v.s%20-21s\t%n, %17-19Q, %0-3Z"},
2443
2444   /* Vector VDUP.  */
2445   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2446    MVE_VDUP,
2447    0xeea00b10, 0xffb10f5f,
2448    "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2449
2450   /* Vector VEOR.  */
2451   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2452    MVE_VEOR,
2453    0xff000150, 0xffd11f51,
2454    "veor%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2455
2456   /* Vector VFMA, vector * scalar.  */
2457   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2458    MVE_VFMA_FP_SCALAR,
2459    0xee310e40, 0xefb11f70,
2460    "vfma%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2461
2462   /* Vector VFMA floating point.  */
2463   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2464    MVE_VFMA_FP,
2465    0xef000c50, 0xffa11f51,
2466    "vfma%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2467
2468   /* Vector VFMS floating point.  */
2469   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2470    MVE_VFMS_FP,
2471    0xef200c50, 0xffa11f51,
2472    "vfms%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2473
2474   /* Vector VFMAS, vector * scalar.  */
2475   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2476    MVE_VFMAS_FP_SCALAR,
2477    0xee311e40, 0xefb11f70,
2478    "vfmas%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2479
2480   /* Vector VHADD T1.  */
2481   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2482    MVE_VHADD_T1,
2483    0xef000040, 0xef811f51,
2484    "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2485
2486   /* Vector VHADD T2.  */
2487   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2488    MVE_VHADD_T2,
2489    0xee000f40, 0xef811f70,
2490    "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2491
2492   /* Vector VHSUB T1.  */
2493   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2494    MVE_VHSUB_T1,
2495    0xef000240, 0xef811f51,
2496    "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2497
2498   /* Vector VHSUB T2.  */
2499   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2500    MVE_VHSUB_T2,
2501    0xee001f40, 0xef811f70,
2502    "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2503
2504   /* Vector VCMUL.  */
2505   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2506    MVE_VCMUL_FP,
2507    0xee300e00, 0xefb10f50,
2508    "vcmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%0,12o"},
2509
2510    /* Vector VCTP.  */
2511   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2512    MVE_VCTP,
2513    0xf000e801, 0xffc0ffff,
2514    "vctp%v.%20-21s\t%16-19r"},
2515
2516   /* Vector VDUP.  */
2517   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2518    MVE_VDUP,
2519    0xeea00b10, 0xffb10f5f,
2520    "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2521
2522   /* Vector VRHADD.  */
2523   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2524    MVE_VRHADD,
2525    0xef000140, 0xef811f51,
2526    "vrhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2527
2528   /* Vector VCVT.  */
2529   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2530    MVE_VCVT_FP_FIX_VEC,
2531    0xef800c50, 0xef801cd1,
2532    "vcvt%v.%s\t%13-15,22Q, %1-3,5Q, #%16-21k"},
2533
2534   /* Vector VCVT.  */
2535   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2536    MVE_VCVT_BETWEEN_FP_INT,
2537    0xffb30640, 0xffb31e51,
2538    "vcvt%v.%s\t%13-15,22Q, %1-3,5Q"},
2539
2540   /* Vector VCVT between single and half-precision float, bottom half.  */
2541   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2542    MVE_VCVT_FP_HALF_FP,
2543    0xee3f0e01, 0xefbf1fd1,
2544    "vcvtb%v.%s\t%13-15,22Q, %1-3,5Q"},
2545
2546   /* Vector VCVT between single and half-precision float, top half.  */
2547   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2548    MVE_VCVT_FP_HALF_FP,
2549    0xee3f1e01, 0xefbf1fd1,
2550    "vcvtt%v.%s\t%13-15,22Q, %1-3,5Q"},
2551
2552   /* Vector VCVT.  */
2553   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2554    MVE_VCVT_FROM_FP_TO_INT,
2555    0xffb30040, 0xffb31c51,
2556    "vcvt%m%v.%s\t%13-15,22Q, %1-3,5Q"},
2557
2558   /* Vector VDDUP.  */
2559   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2560    MVE_VDDUP,
2561    0xee011f6e, 0xff811f7e,
2562    "vddup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
2563
2564   /* Vector VDWDUP.  */
2565   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2566    MVE_VDWDUP,
2567    0xee011f60, 0xff811f70,
2568    "vdwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
2569
2570   /* Vector VHCADD.  */
2571   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2572    MVE_VHCADD,
2573    0xee000f00, 0xff810f51,
2574    "vhcadd%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
2575
2576   /* Vector VIWDUP.  */
2577   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2578    MVE_VIWDUP,
2579    0xee010f60, 0xff811f70,
2580    "viwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
2581
2582   /* Vector VIDUP.  */
2583   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2584    MVE_VIDUP,
2585    0xee010f6e, 0xff811f7e,
2586    "vidup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
2587
2588   /* Vector VLD2.  */
2589   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2590    MVE_VLD2,
2591    0xfc901e00, 0xff901e5f,
2592    "vld2%5d.%7-8s\t%B, [%16-19r]%w"},
2593
2594   /* Vector VLD4.  */
2595   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2596    MVE_VLD4,
2597    0xfc901e01, 0xff901e1f,
2598    "vld4%5-6d.%7-8s\t%B, [%16-19r]%w"},
2599
2600   /* Vector VLDRB gather load.  */
2601   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2602    MVE_VLDRB_GATHER_T1,
2603    0xec900e00, 0xefb01e50,
2604    "vldrb%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
2605
2606   /* Vector VLDRH gather load.  */
2607   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2608    MVE_VLDRH_GATHER_T2,
2609    0xec900e10, 0xefb01e50,
2610    "vldrh%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2611
2612   /* Vector VLDRW gather load.  */
2613   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2614    MVE_VLDRW_GATHER_T3,
2615    0xfc900f40, 0xffb01fd0,
2616    "vldrw%v.u32\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2617
2618   /* Vector VLDRD gather load.  */
2619   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2620    MVE_VLDRD_GATHER_T4,
2621    0xec900fd0, 0xefb01fd0,
2622    "vldrd%v.u64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2623
2624   /* Vector VLDRW gather load.  */
2625   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2626    MVE_VLDRW_GATHER_T5,
2627    0xfd101e00, 0xff111f00,
2628    "vldrw%v.u32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2629
2630   /* Vector VLDRD gather load, variant T6.  */
2631   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2632    MVE_VLDRD_GATHER_T6,
2633    0xfd101f00, 0xff111f00,
2634    "vldrd%v.u64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2635
2636   /* Vector VLDRB.  */
2637   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2638    MVE_VLDRB_T1,
2639    0xec100e00, 0xee581e00,
2640    "vldrb%v.%u%7-8s\t%13-15Q, %d"},
2641
2642   /* Vector VLDRH.  */
2643   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2644    MVE_VLDRH_T2,
2645    0xec180e00, 0xee581e00,
2646    "vldrh%v.%u%7-8s\t%13-15Q, %d"},
2647
2648   /* Vector VLDRB unsigned, variant T5.  */
2649   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2650    MVE_VLDRB_T5,
2651    0xec101e00, 0xfe101f80,
2652    "vldrb%v.u8\t%13-15,22Q, %d"},
2653
2654   /* Vector VLDRH unsigned, variant T6.  */
2655   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2656    MVE_VLDRH_T6,
2657    0xec101e80, 0xfe101f80,
2658    "vldrh%v.u16\t%13-15,22Q, %d"},
2659
2660   /* Vector VLDRW unsigned, variant T7.  */
2661   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2662    MVE_VLDRW_T7,
2663    0xec101f00, 0xfe101f80,
2664    "vldrw%v.u32\t%13-15,22Q, %d"},
2665
2666   /* Vector VMAX.  */
2667   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2668    MVE_VMAX,
2669    0xef000640, 0xef811f51,
2670    "vmax%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2671
2672   /* Vector VMAXA.  */
2673   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2674    MVE_VMAXA,
2675    0xee330e81, 0xffb31fd1,
2676    "vmaxa%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2677
2678   /* Vector VMAXNM floating point.  */
2679   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2680    MVE_VMAXNM_FP,
2681    0xff000f50, 0xffa11f51,
2682    "vmaxnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2683
2684   /* Vector VMAXNMA floating point.  */
2685   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2686    MVE_VMAXNMA_FP,
2687    0xee3f0e81, 0xefbf1fd1,
2688    "vmaxnma%v.f%28s\t%13-15,22Q, %1-3,5Q"},
2689
2690   /* Vector VMAXNMV floating point.  */
2691   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2692    MVE_VMAXNMV_FP,
2693    0xeeee0f00, 0xefff0fd1,
2694    "vmaxnmv%v.f%28s\t%12-15r, %1-3,5Q"},
2695
2696   /* Vector VMAXNMAV floating point.  */
2697   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2698    MVE_VMAXNMAV_FP,
2699    0xeeec0f00, 0xefff0fd1,
2700    "vmaxnmav%v.f%28s\t%12-15r, %1-3,5Q"},
2701
2702   /* Vector VMAXV.  */
2703   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2704    MVE_VMAXV,
2705    0xeee20f00, 0xeff30fd1,
2706    "vmaxv%v.%u%18-19s\t%12-15r, %1-3,5Q"},
2707
2708   /* Vector VMAXAV.  */
2709   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2710    MVE_VMAXAV,
2711    0xeee00f00, 0xfff30fd1,
2712    "vmaxav%v.s%18-19s\t%12-15r, %1-3,5Q"},
2713
2714   /* Vector VMIN.  */
2715   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2716    MVE_VMIN,
2717    0xef000650, 0xef811f51,
2718    "vmin%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2719
2720   /* Vector VMINA.  */
2721   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2722    MVE_VMINA,
2723    0xee331e81, 0xffb31fd1,
2724    "vmina%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2725
2726   /* Vector VMINNM floating point.  */
2727   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2728    MVE_VMINNM_FP,
2729    0xff200f50, 0xffa11f51,
2730    "vminnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2731
2732   /* Vector VMINNMA floating point.  */
2733   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2734    MVE_VMINNMA_FP,
2735    0xee3f1e81, 0xefbf1fd1,
2736    "vminnma%v.f%28s\t%13-15,22Q, %1-3,5Q"},
2737
2738   /* Vector VMINNMV floating point.  */
2739   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2740    MVE_VMINNMV_FP,
2741    0xeeee0f80, 0xefff0fd1,
2742    "vminnmv%v.f%28s\t%12-15r, %1-3,5Q"},
2743
2744   /* Vector VMINNMAV floating point.  */
2745   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2746    MVE_VMINNMAV_FP,
2747    0xeeec0f80, 0xefff0fd1,
2748    "vminnmav%v.f%28s\t%12-15r, %1-3,5Q"},
2749
2750   /* Vector VMINV.  */
2751   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2752    MVE_VMINV,
2753    0xeee20f80, 0xeff30fd1,
2754    "vminv%v.%u%18-19s\t%12-15r, %1-3,5Q"},
2755
2756   /* Vector VMINAV.  */
2757   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2758    MVE_VMINAV,
2759    0xeee00f80, 0xfff30fd1,
2760    "vminav%v.s%18-19s\t%12-15r, %1-3,5Q"},
2761
2762   /* Vector VMLA.  */
2763   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2764    MVE_VMLA,
2765    0xee010e40, 0xef811f70,
2766    "vmla%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2767
2768   /* Vector VMLALDAV.  Note must appear before VMLADAV due to instruction
2769      opcode aliasing.  */
2770   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2771    MVE_VMLALDAV,
2772    0xee801e00, 0xef801f51,
2773    "vmlaldav%5Ax%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2774
2775   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2776    MVE_VMLALDAV,
2777    0xee800e00, 0xef801f51,
2778    "vmlalv%5A%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2779
2780   /* Vector VMLAV T1 variant, same as VMLADAV but with X == 0.  */
2781   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2782    MVE_VMLADAV_T1,
2783    0xeef00e00, 0xeff01f51,
2784    "vmlav%5A%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2785
2786   /* Vector VMLAV T2 variant, same as VMLADAV but with X == 0.  */
2787   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2788    MVE_VMLADAV_T2,
2789    0xeef00f00, 0xeff11f51,
2790    "vmlav%5A%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2791
2792   /* Vector VMLADAV T1 variant.  */
2793   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2794    MVE_VMLADAV_T1,
2795    0xeef01e00, 0xeff01f51,
2796    "vmladav%5Ax%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2797
2798   /* Vector VMLADAV T2 variant.  */
2799   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2800    MVE_VMLADAV_T2,
2801    0xeef01f00, 0xeff11f51,
2802    "vmladav%5Ax%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2803
2804   /* Vector VMLAS.  */
2805   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2806    MVE_VMLAS,
2807    0xee011e40, 0xef811f70,
2808    "vmlas%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2809
2810   /* Vector VRMLSLDAVH.  Note must appear before VMLSDAV due to instruction
2811      opcode aliasing.  */
2812   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2813    MVE_VRMLSLDAVH,
2814    0xfe800e01, 0xff810f51,
2815    "vrmlsldavh%5A%X%v.s32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2816
2817   /* Vector VMLSLDAV.  Note must appear before VMLSDAV due to instruction
2818      opcdoe aliasing.  */
2819   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2820    MVE_VMLSLDAV,
2821    0xee800e01, 0xff800f51,
2822    "vmlsldav%5A%X%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2823
2824   /* Vector VMLSDAV T1 Variant.  */
2825   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2826    MVE_VMLSDAV_T1,
2827    0xeef00e01, 0xfff00f51,
2828    "vmlsdav%5A%X%v.s%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2829
2830   /* Vector VMLSDAV T2 Variant.  */
2831   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2832    MVE_VMLSDAV_T2,
2833    0xfef00e01, 0xfff10f51,
2834    "vmlsdav%5A%X%v.s8\t%13-15l, %17-19,7Q, %1-3Q"},
2835
2836   /* Vector VMOV between gpr and half precision register, op == 0.  */
2837   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2838    MVE_VMOV_HFP_TO_GP,
2839    0xee000910, 0xfff00f7f,
2840    "vmov.f16\t%7,16-19F, %12-15r"},
2841
2842   /* Vector VMOV between gpr and half precision register, op == 1.  */
2843   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2844    MVE_VMOV_HFP_TO_GP,
2845    0xee100910, 0xfff00f7f,
2846    "vmov.f16\t%12-15r, %7,16-19F"},
2847
2848   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2849    MVE_VMOV_GP_TO_VEC_LANE,
2850    0xee000b10, 0xff900f1f,
2851    "vmov%c.%5-6,21-22s\t%17-19,7Q[%N], %12-15r"},
2852
2853   /* Vector VORR immediate to vector.
2854      NOTE: MVE_VORR_IMM must appear in the table
2855      before MVE_VMOV_IMM_TO_VEC due to opcode aliasing.  */
2856   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2857    MVE_VORR_IMM,
2858    0xef800050, 0xefb810f0,
2859    "vorr%v.i%8-11s\t%13-15,22Q, %E"},
2860
2861   /* Vector VQSHL T2 Variant.
2862      NOTE: MVE_VQSHL_T2 must appear in the table before
2863      before MVE_VMOV_IMM_TO_VEC due to opcode aliasing.  */
2864   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2865    MVE_VQSHL_T2,
2866    0xef800750, 0xef801fd1,
2867    "vqshl%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2868
2869   /* Vector VQSHLU T3 Variant
2870      NOTE: MVE_VQSHL_T2 must appear in the table before
2871      before MVE_VMOV_IMM_TO_VEC due to opcode aliasing.  */
2872
2873   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2874    MVE_VQSHLU_T3,
2875    0xff800650, 0xff801fd1,
2876    "vqshlu%v.s%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2877
2878   /* Vector VRSHR
2879      NOTE: MVE_VRSHR must appear in the table before
2880      before MVE_VMOV_IMM_TO_VEC due to opcode aliasing.  */
2881   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2882    MVE_VRSHR,
2883    0xef800250, 0xef801fd1,
2884    "vrshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2885
2886   /* Vector VSHL.
2887      NOTE: MVE_VSHL must appear in the table before
2888      before MVE_VMOV_IMM_TO_VEC due to opcode aliasing.  */
2889   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2890    MVE_VSHL_T1,
2891    0xef800550, 0xff801fd1,
2892    "vshl%v.i%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2893
2894   /* Vector VSHR
2895      NOTE: MVE_VSHR must appear in the table before
2896      before MVE_VMOV_IMM_TO_VEC due to opcode aliasing.  */
2897   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2898    MVE_VSHR,
2899    0xef800050, 0xef801fd1,
2900    "vshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2901
2902   /* Vector VSLI
2903      NOTE: MVE_VSLI must appear in the table before
2904      before MVE_VMOV_IMM_TO_VEC due to opcode aliasing.  */
2905   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2906    MVE_VSLI,
2907    0xff800550, 0xff801fd1,
2908    "vsli%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2909
2910   /* Vector VSRI
2911      NOTE: MVE_VSRI must appear in the table before
2912      before MVE_VMOV_IMM_TO_VEC due to opcode aliasing.  */
2913   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2914    MVE_VSRI,
2915    0xff800450, 0xff801fd1,
2916    "vsri%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2917
2918   /* Vector VMOV immediate to vector,
2919      undefinded for cmode == 1111 */
2920   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2921    MVE_VMVN_IMM, 0xef800f70, 0xefb81ff0, UNDEFINED_INSTRUCTION},
2922
2923   /* Vector VMOV immediate to vector,
2924      cmode == 1101 */
2925   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2926    MVE_VMOV_IMM_TO_VEC, 0xef800d50, 0xefb81fd0,
2927    "vmov%v.%5,8-11s\t%13-15,22Q, %E"},
2928
2929   /* Vector VMOV immediate to vector.  */
2930   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2931    MVE_VMOV_IMM_TO_VEC,
2932    0xef800050, 0xefb810d0,
2933    "vmov%v.%5,8-11s\t%13-15,22Q, %E"},
2934
2935   /* Vector VMOV two 32-bit lanes to two gprs, idx = 0.  */
2936   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2937    MVE_VMOV2_VEC_LANE_TO_GP,
2938    0xec000f00, 0xffb01ff0,
2939    "vmov%c\t%0-3r, %16-19r, %13-15,22Q[2], %13-15,22Q[0]"},
2940
2941   /* Vector VMOV two 32-bit lanes to two gprs, idx = 1.  */
2942   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2943    MVE_VMOV2_VEC_LANE_TO_GP,
2944    0xec000f10, 0xffb01ff0,
2945    "vmov%c\t%0-3r, %16-19r, %13-15,22Q[3], %13-15,22Q[1]"},
2946
2947   /* Vector VMOV Two gprs to two 32-bit lanes, idx = 0.  */
2948   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2949    MVE_VMOV2_GP_TO_VEC_LANE,
2950    0xec100f00, 0xffb01ff0,
2951    "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
2952
2953   /* Vector VMOV Two gprs to two 32-bit lanes, idx = 1.  */
2954   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2955    MVE_VMOV2_GP_TO_VEC_LANE,
2956    0xec100f10, 0xffb01ff0,
2957    "vmov%c\t%13-15,22Q[3], %13-15,22Q[1], %0-3r, %16-19r"},
2958
2959   /* Vector VMOV Vector lane to gpr.  */
2960   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2961    MVE_VMOV_VEC_LANE_TO_GP,
2962    0xee100b10, 0xff100f1f,
2963    "vmov%c.%u%5-6,21-22s\t%12-15r, %17-19,7Q[%N]"},
2964
2965   /* Vector VSHLL T1 Variant.  Note: VSHLL T1 must appear before MVE_VMOVL due
2966      to instruction opcode aliasing.  */
2967   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2968    MVE_VSHLL_T1,
2969    0xeea00f40, 0xefa00fd1,
2970    "vshll%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2971
2972   /* Vector VMOVL long.  */
2973   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2974    MVE_VMOVL,
2975    0xeea00f40, 0xefa70fd1,
2976    "vmovl%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q"},
2977
2978   /* Vector VMOV and narrow.  */
2979   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2980    MVE_VMOVN,
2981    0xfe310e81, 0xffb30fd1,
2982    "vmovn%T%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2983
2984   /* Floating point move extract.  */
2985   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2986    MVE_VMOVX,
2987    0xfeb00a40, 0xffbf0fd0,
2988    "vmovx.f16\t%22,12-15F, %5,0-3F"},
2989
2990   /* Vector VMUL floating-point T1 variant.  */
2991   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2992    MVE_VMUL_FP_T1,
2993    0xff000d50, 0xffa11f51,
2994    "vmul%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2995
2996   /* Vector VMUL floating-point T2 variant.  */
2997   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2998    MVE_VMUL_FP_T2,
2999    0xee310e60, 0xefb11f70,
3000    "vmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3001
3002   /* Vector VMUL T1 variant.  */
3003   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3004    MVE_VMUL_VEC_T1,
3005    0xef000950, 0xff811f51,
3006    "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3007
3008   /* Vector VMUL T2 variant.  */
3009   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3010    MVE_VMUL_VEC_T2,
3011    0xee011e60, 0xff811f70,
3012    "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3013
3014   /* Vector VMULH.  */
3015   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3016    MVE_VMULH,
3017    0xee010e01, 0xef811f51,
3018    "vmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3019
3020   /* Vector VRMULH.  */
3021   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3022    MVE_VRMULH,
3023    0xee011e01, 0xef811f51,
3024    "vrmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3025
3026   /* Vector VMULL integer.  */
3027   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3028    MVE_VMULL_INT,
3029    0xee010e00, 0xef810f51,
3030    "vmull%T%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3031
3032   /* Vector VMULL polynomial.  */
3033   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3034    MVE_VMULL_POLY,
3035    0xee310e00, 0xefb10f51,
3036    "vmull%T%v.%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3037
3038   /* Vector VMVN immediate to vector.  */
3039   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3040    MVE_VMVN_IMM,
3041    0xef800070, 0xefb810f0,
3042    "vmvn%v.i%8-11s\t%13-15,22Q, %E"},
3043
3044   /* Vector VMVN register.  */
3045   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3046    MVE_VMVN_REG,
3047    0xffb005c0, 0xffbf1fd1,
3048    "vmvn%v\t%13-15,22Q, %1-3,5Q"},
3049
3050   /* Vector VNEG floating point.  */
3051   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
3052    MVE_VNEG_FP,
3053    0xffb107c0, 0xffb31fd1,
3054    "vneg%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
3055
3056   /* Vector VNEG.  */
3057   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3058    MVE_VNEG_VEC,
3059    0xffb103c0, 0xffb31fd1,
3060    "vneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
3061
3062   /* Vector VORN, vector bitwise or not.  */
3063   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3064    MVE_VORN,
3065    0xef300150, 0xffb11f51,
3066    "vorn%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3067
3068   /* Vector VORR register.  */
3069   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3070    MVE_VORR_REG,
3071    0xef200150, 0xffb11f51,
3072    "vorr%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3073
3074   /* Vector VMOV, vector to vector move. While decoding MVE_VORR_REG if
3075      "Qm==Qn", VORR should replaced by its alias VMOV. For that to happen
3076      MVE_VMOV_VEC_TO_VEC need to placed after MVE_VORR_REG in this mve_opcodes
3077      array.  */
3078
3079   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3080    MVE_VMOV_VEC_TO_VEC,
3081    0xef200150, 0xffb11f51,
3082    "vmov%v\t%13-15,22Q, %17-19,7Q"},
3083
3084   /* Vector VQDMULL T1 variant.  */
3085   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3086    MVE_VQDMULL_T1,
3087    0xee300f01, 0xefb10f51,
3088    "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3089
3090   /* Vector VPNOT.  */
3091   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3092    MVE_VPNOT,
3093    0xfe310f4d, 0xffffffff,
3094    "vpnot%v"},
3095
3096   /* Vector VPSEL.  */
3097   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3098    MVE_VPSEL,
3099    0xfe310f01, 0xffb11f51,
3100    "vpsel%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3101
3102   /* Vector VQABS.  */
3103   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3104    MVE_VQABS,
3105    0xffb00740, 0xffb31fd1,
3106    "vqabs%v.s%18-19s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3107
3108   /* Vector VQADD T1 variant.  */
3109   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3110    MVE_VQADD_T1,
3111    0xef000050, 0xef811f51,
3112    "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3113
3114   /* Vector VQADD T2 variant.  */
3115   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3116    MVE_VQADD_T2,
3117    0xee000f60, 0xef811f70,
3118    "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3119
3120   /* Vector VQDMULL T2 variant.  */
3121   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3122    MVE_VQDMULL_T2,
3123    0xee300f60, 0xefb10f70,
3124    "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3125
3126   /* Vector VQMOVN.  */
3127   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3128    MVE_VQMOVN,
3129    0xee330e01, 0xefb30fd1,
3130    "vqmovn%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q"},
3131
3132   /* Vector VQMOVUN.  */
3133   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3134    MVE_VQMOVUN,
3135    0xee310e81, 0xffb30fd1,
3136    "vqmovun%T%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
3137
3138   /* Vector VQDMLADH.  */
3139   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3140    MVE_VQDMLADH,
3141    0xee000e00, 0xff810f51,
3142    "vqdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3143
3144   /* Vector VQRDMLADH.  */
3145   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3146    MVE_VQRDMLADH,
3147    0xee000e01, 0xff810f51,
3148    "vqrdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3149
3150   /* Vector VQDMLAH.  */
3151   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3152    MVE_VQDMLAH,
3153    0xee000e60, 0xff811f70,
3154    "vqdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3155
3156   /* Vector VQRDMLAH.  */
3157   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3158    MVE_VQRDMLAH,
3159    0xee000e40, 0xff811f70,
3160    "vqrdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3161
3162   /* Vector VQDMLASH.  */
3163   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3164    MVE_VQDMLASH,
3165    0xee001e60, 0xff811f70,
3166    "vqdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3167
3168   /* Vector VQRDMLASH.  */
3169   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3170    MVE_VQRDMLASH,
3171    0xee001e40, 0xff811f70,
3172    "vqrdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3173
3174   /* Vector VQDMLSDH.  */
3175   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3176    MVE_VQDMLSDH,
3177    0xfe000e00, 0xff810f51,
3178    "vqdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3179
3180   /* Vector VQRDMLSDH.  */
3181   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3182    MVE_VQRDMLSDH,
3183    0xfe000e01, 0xff810f51,
3184    "vqrdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3185
3186   /* Vector VQDMULH T1 variant.  */
3187   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3188    MVE_VQDMULH_T1,
3189    0xef000b40, 0xff811f51,
3190    "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3191
3192   /* Vector VQRDMULH T2 variant.  */
3193   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3194    MVE_VQRDMULH_T2,
3195    0xff000b40, 0xff811f51,
3196    "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3197
3198   /* Vector VQDMULH T3 variant.  */
3199   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3200    MVE_VQDMULH_T3,
3201    0xee010e60, 0xff811f70,
3202    "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3203
3204   /* Vector VQRDMULH T4 variant.  */
3205   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3206    MVE_VQRDMULH_T4,
3207    0xfe010e60, 0xff811f70,
3208    "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3209
3210   /* Vector VQNEG.  */
3211   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3212    MVE_VQNEG,
3213    0xffb007c0, 0xffb31fd1,
3214    "vqneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
3215
3216   /* Vector VQRSHL T1 variant.  */
3217   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3218    MVE_VQRSHL_T1,
3219    0xef000550, 0xef811f51,
3220    "vqrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3221
3222   /* Vector VQRSHL T2 variant.  */
3223   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3224    MVE_VQRSHL_T2,
3225    0xee331ee0, 0xefb31ff0,
3226    "vqrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3227
3228   /* Vector VQRSHRN.  */
3229   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3230    MVE_VQRSHRN,
3231    0xee800f41, 0xefa00fd1,
3232    "vqrshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3233
3234   /* Vector VQRSHRUN.  */
3235   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3236    MVE_VQRSHRUN,
3237    0xfe800fc0, 0xffa00fd1,
3238    "vqrshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3239
3240   /* Vector VQSHL T1 Variant.  */
3241   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3242    MVE_VQSHL_T1,
3243    0xee311ee0, 0xefb31ff0,
3244    "vqshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3245
3246   /* Vector VQSHL T4 Variant.  */
3247   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3248    MVE_VQSHL_T4,
3249    0xef000450, 0xef811f51,
3250    "vqshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3251
3252   /* Vector VQSHRN.  */
3253   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3254    MVE_VQSHRN,
3255    0xee800f40, 0xefa00fd1,
3256    "vqshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3257
3258   /* Vector VQSHRUN.  */
3259   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3260    MVE_VQSHRUN,
3261    0xee800fc0, 0xffa00fd1,
3262    "vqshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3263
3264   /* Vector VQSUB T1 Variant.  */
3265   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3266    MVE_VQSUB_T1,
3267    0xef000250, 0xef811f51,
3268    "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3269
3270   /* Vector VQSUB T2 Variant.  */
3271   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3272    MVE_VQSUB_T2,
3273    0xee001f60, 0xef811f70,
3274    "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3275
3276   /* Vector VREV16.  */
3277   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3278    MVE_VREV16,
3279    0xffb00140, 0xffb31fd1,
3280    "vrev16%v.8\t%13-15,22Q, %1-3,5Q"},
3281
3282   /* Vector VREV32.  */
3283   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3284    MVE_VREV32,
3285    0xffb000c0, 0xffb31fd1,
3286    "vrev32%v.%18-19s\t%13-15,22Q, %1-3,5Q"},
3287
3288   /* Vector VREV64.  */
3289   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3290    MVE_VREV64,
3291    0xffb00040, 0xffb31fd1,
3292    "vrev64%v.%18-19s\t%13-15,22Q, %1-3,5Q"},
3293
3294   /* Vector VRINT floating point.  */
3295   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
3296    MVE_VRINT_FP,
3297    0xffb20440, 0xffb31c51,
3298    "vrint%m%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
3299
3300   /* Vector VRMLALDAVH.  */
3301   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3302    MVE_VRMLALDAVH,
3303    0xee800f00, 0xef811f51,
3304    "vrmlalvh%5A%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
3305
3306   /* Vector VRMLALDAVH.  */
3307   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3308    MVE_VRMLALDAVH,
3309    0xee801f00, 0xef811f51,
3310    "vrmlaldavh%5Ax%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
3311
3312   /* Vector VRSHL T1 Variant.  */
3313   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3314    MVE_VRSHL_T1,
3315    0xef000540, 0xef811f51,
3316    "vrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3317
3318   /* Vector VRSHL T2 Variant.  */
3319   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3320    MVE_VRSHL_T2,
3321    0xee331e60, 0xefb31ff0,
3322    "vrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3323
3324   /* Vector VRSHRN.  */
3325   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3326    MVE_VRSHRN,
3327    0xfe800fc1, 0xffa00fd1,
3328    "vrshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3329
3330   /* Vector VSBC.  */
3331   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3332    MVE_VSBC,
3333    0xfe300f00, 0xffb10f51,
3334    "vsbc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3335
3336   /* Vector VSHL T2 Variant.  */
3337   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3338    MVE_VSHL_T2,
3339    0xee311e60, 0xefb31ff0,
3340    "vshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3341
3342   /* Vector VSHL T3 Variant.  */
3343   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3344    MVE_VSHL_T3,
3345    0xef000440, 0xef811f51,
3346    "vshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3347
3348   /* Vector VSHLC.  */
3349   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3350    MVE_VSHLC,
3351    0xeea00fc0, 0xffa01ff0,
3352    "vshlc%v\t%13-15,22Q, %0-3r, #%16-20d"},
3353
3354   /* Vector VSHLL T2 Variant.  */
3355   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3356    MVE_VSHLL_T2,
3357    0xee310e01, 0xefb30fd1,
3358    "vshll%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q, #%18-19d"},
3359
3360   /* Vector VSHRN.  */
3361   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3362    MVE_VSHRN,
3363    0xee800fc1, 0xffa00fd1,
3364    "vshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3365
3366   /* Vector VST2 no writeback.  */
3367   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3368    MVE_VST2,
3369    0xfc801e00, 0xffb01e5f,
3370    "vst2%5d.%7-8s\t%B, [%16-19r]"},
3371
3372   /* Vector VST2 writeback.  */
3373   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3374    MVE_VST2,
3375    0xfca01e00, 0xffb01e5f,
3376    "vst2%5d.%7-8s\t%B, [%16-19r]!"},
3377
3378   /* Vector VST4 no writeback.  */
3379   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3380    MVE_VST4,
3381    0xfc801e01, 0xffb01e1f,
3382    "vst4%5-6d.%7-8s\t%B, [%16-19r]"},
3383
3384   /* Vector VST4 writeback.  */
3385   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3386    MVE_VST4,
3387    0xfca01e01, 0xffb01e1f,
3388    "vst4%5-6d.%7-8s\t%B, [%16-19r]!"},
3389
3390   /* Vector VSTRB scatter store, T1 variant.  */
3391   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3392    MVE_VSTRB_SCATTER_T1,
3393    0xec800e00, 0xffb01e50,
3394    "vstrb%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
3395
3396   /* Vector VSTRH scatter store, T2 variant.  */
3397   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3398    MVE_VSTRH_SCATTER_T2,
3399    0xec800e10, 0xffb01e50,
3400    "vstrh%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3401
3402   /* Vector VSTRW scatter store, T3 variant.  */
3403   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3404    MVE_VSTRW_SCATTER_T3,
3405    0xec800e40, 0xffb01e50,
3406    "vstrw%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3407
3408   /* Vector VSTRD scatter store, T4 variant.  */
3409   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3410    MVE_VSTRD_SCATTER_T4,
3411    0xec800fd0, 0xffb01fd0,
3412    "vstrd%v.64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3413
3414   /* Vector VSTRW scatter store, T5 variant.  */
3415   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3416    MVE_VSTRW_SCATTER_T5,
3417    0xfd001e00, 0xff111f00,
3418    "vstrw%v.32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
3419
3420   /* Vector VSTRD scatter store, T6 variant.  */
3421   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3422    MVE_VSTRD_SCATTER_T6,
3423    0xfd001f00, 0xff111f00,
3424    "vstrd%v.64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
3425
3426   /* Vector VSTRB.  */
3427   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3428    MVE_VSTRB_T1,
3429    0xec000e00, 0xfe581e00,
3430    "vstrb%v.%7-8s\t%13-15Q, %d"},
3431
3432   /* Vector VSTRH.  */
3433   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3434    MVE_VSTRH_T2,
3435    0xec080e00, 0xfe581e00,
3436    "vstrh%v.%7-8s\t%13-15Q, %d"},
3437
3438   /* Vector VSTRB variant T5.  */
3439   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3440    MVE_VSTRB_T5,
3441    0xec001e00, 0xfe101f80,
3442    "vstrb%v.8\t%13-15,22Q, %d"},
3443
3444   /* Vector VSTRH variant T6.  */
3445   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3446    MVE_VSTRH_T6,
3447    0xec001e80, 0xfe101f80,
3448    "vstrh%v.16\t%13-15,22Q, %d"},
3449
3450   /* Vector VSTRW variant T7.  */
3451   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3452    MVE_VSTRW_T7,
3453    0xec001f00, 0xfe101f80,
3454    "vstrw%v.32\t%13-15,22Q, %d"},
3455
3456   /* Vector VSUB floating point T1 variant.  */
3457   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
3458    MVE_VSUB_FP_T1,
3459    0xef200d40, 0xffa11f51,
3460    "vsub%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3461
3462   /* Vector VSUB floating point T2 variant.  */
3463   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
3464    MVE_VSUB_FP_T2,
3465    0xee301f40, 0xefb11f70,
3466    "vsub%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3467
3468   /* Vector VSUB T1 variant.  */
3469   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3470    MVE_VSUB_VEC_T1,
3471    0xff000840, 0xff811f51,
3472    "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3473
3474   /* Vector VSUB T2 variant.  */
3475   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3476    MVE_VSUB_VEC_T2,
3477    0xee011f40, 0xff811f70,
3478    "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3479
3480   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3481    MVE_ASRLI,
3482    0xea50012f, 0xfff1813f,
3483    "asrl%c\t%17-19l, %9-11h, %j"},
3484
3485   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3486    MVE_ASRL,
3487    0xea50012d, 0xfff101ff,
3488    "asrl%c\t%17-19l, %9-11h, %12-15S"},
3489
3490   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3491    MVE_LSLLI,
3492    0xea50010f, 0xfff1813f,
3493    "lsll%c\t%17-19l, %9-11h, %j"},
3494
3495   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3496    MVE_LSLL,
3497    0xea50010d, 0xfff101ff,
3498    "lsll%c\t%17-19l, %9-11h, %12-15S"},
3499
3500   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3501    MVE_LSRL,
3502    0xea50011f, 0xfff1813f,
3503    "lsrl%c\t%17-19l, %9-11h, %j"},
3504
3505   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3506    MVE_SQRSHRL,
3507    0xea51012d, 0xfff1017f,
3508    "sqrshrl%c\t%17-19l, %9-11h, %k, %12-15S"},
3509
3510   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3511    MVE_SQRSHR,
3512    0xea500f2d, 0xfff00fff,
3513    "sqrshr%c\t%16-19S, %12-15S"},
3514
3515   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3516    MVE_SQSHLL,
3517    0xea51013f, 0xfff1813f,
3518    "sqshll%c\t%17-19l, %9-11h, %j"},
3519
3520   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3521    MVE_SQSHL,
3522    0xea500f3f, 0xfff08f3f,
3523    "sqshl%c\t%16-19S, %j"},
3524
3525   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3526    MVE_SRSHRL,
3527    0xea51012f, 0xfff1813f,
3528    "srshrl%c\t%17-19l, %9-11h, %j"},
3529
3530   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3531    MVE_SRSHR,
3532    0xea500f2f, 0xfff08f3f,
3533    "srshr%c\t%16-19S, %j"},
3534
3535   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3536    MVE_UQRSHLL,
3537    0xea51010d, 0xfff1017f,
3538    "uqrshll%c\t%17-19l, %9-11h, %k, %12-15S"},
3539
3540   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3541    MVE_UQRSHL,
3542    0xea500f0d, 0xfff00fff,
3543    "uqrshl%c\t%16-19S, %12-15S"},
3544
3545   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3546    MVE_UQSHLL,
3547     0xea51010f, 0xfff1813f,
3548    "uqshll%c\t%17-19l, %9-11h, %j"},
3549
3550   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3551    MVE_UQSHL,
3552    0xea500f0f, 0xfff08f3f,
3553    "uqshl%c\t%16-19S, %j"},
3554
3555   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3556    MVE_URSHRL,
3557     0xea51011f, 0xfff1813f,
3558    "urshrl%c\t%17-19l, %9-11h, %j"},
3559
3560   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3561    MVE_URSHR,
3562    0xea500f1f, 0xfff08f3f,
3563    "urshr%c\t%16-19S, %j"},
3564
3565   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3566    MVE_CSINC,
3567    0xea509000, 0xfff0f000,
3568    "csinc\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3569
3570   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3571    MVE_CSINV,
3572    0xea50a000, 0xfff0f000,
3573    "csinv\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3574
3575   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3576    MVE_CSET,
3577    0xea5f900f, 0xfffff00f,
3578    "cset\t%8-11S, %4-7C"},
3579
3580   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3581    MVE_CSETM,
3582    0xea5fa00f, 0xfffff00f,
3583    "csetm\t%8-11S, %4-7C"},
3584
3585   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3586    MVE_CSEL,
3587    0xea508000, 0xfff0f000,
3588    "csel\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3589
3590   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3591    MVE_CSNEG,
3592    0xea50b000, 0xfff0f000,
3593    "csneg\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3594
3595   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3596    MVE_CINC,
3597    0xea509000, 0xfff0f000,
3598    "cinc\t%8-11S, %16-19Z, %4-7C"},
3599
3600   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3601    MVE_CINV,
3602    0xea50a000, 0xfff0f000,
3603    "cinv\t%8-11S, %16-19Z, %4-7C"},
3604
3605   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3606    MVE_CNEG,
3607    0xea50b000, 0xfff0f000,
3608    "cneg\t%8-11S, %16-19Z, %4-7C"},
3609
3610   {ARM_FEATURE_CORE_LOW (0),
3611    MVE_NONE,
3612    0x00000000, 0x00000000, 0}
3613 };
3614
3615 /* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb.  All three are partially
3616    ordered: they must be searched linearly from the top to obtain a correct
3617    match.  */
3618
3619 /* print_insn_arm recognizes the following format control codes:
3620
3621    %%                   %
3622
3623    %a                   print address for ldr/str instruction
3624    %s                   print address for ldr/str halfword/signextend instruction
3625    %S                   like %s but allow UNPREDICTABLE addressing
3626    %b                   print branch destination
3627    %c                   print condition code (always bits 28-31)
3628    %m                   print register mask for ldm/stm instruction
3629    %o                   print operand2 (immediate or register + shift)
3630    %p                   print 'p' iff bits 12-15 are 15
3631    %t                   print 't' iff bit 21 set and bit 24 clear
3632    %B                   print arm BLX(1) destination
3633    %C                   print the PSR sub type.
3634    %U                   print barrier type.
3635    %P                   print address for pli instruction.
3636
3637    %<bitfield>r         print as an ARM register
3638    %<bitfield>T         print as an ARM register + 1
3639    %<bitfield>R         as %r but r15 is UNPREDICTABLE
3640    %<bitfield>{r|R}u    as %{r|R} but if matches the other %u field then is UNPREDICTABLE
3641    %<bitfield>{r|R}U    as %{r|R} but if matches the other %U field then is UNPREDICTABLE
3642    %<bitfield>d         print the bitfield in decimal
3643    %<bitfield>W         print the bitfield plus one in decimal
3644    %<bitfield>x         print the bitfield in hex
3645    %<bitfield>X         print the bitfield as 1 hex digit without leading "0x"
3646
3647    %<bitfield>'c        print specified char iff bitfield is all ones
3648    %<bitfield>`c        print specified char iff bitfield is all zeroes
3649    %<bitfield>?ab...    select from array of values in big endian order
3650
3651    %e                   print arm SMI operand (bits 0..7,8..19).
3652    %E                   print the LSB and WIDTH fields of a BFI or BFC instruction.
3653    %V                   print the 16-bit immediate field of a MOVT or MOVW instruction.
3654    %R                   print the SPSR/CPSR or banked register of an MRS.  */
3655
3656 static const struct opcode32 arm_opcodes[] =
3657 {
3658   /* ARM instructions.  */
3659   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3660     0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
3661   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3662     0xe7f000f0, 0xfff000f0, "udf\t#%e"},
3663
3664   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5),
3665     0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
3666   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
3667     0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
3668   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
3669     0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3670   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S),
3671     0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
3672   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
3673     0x00800090, 0x0fa000f0,
3674     "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3675   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
3676     0x00a00090, 0x0fa000f0,
3677     "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3678
3679   /* V8.2 RAS extension instructions.  */
3680   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
3681     0xe320f010, 0xffffffff, "esb"},
3682
3683   /* V8-R instructions.  */
3684   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8R),
3685     0xf57ff04c, 0xffffffff, "dfb"},
3686
3687   /* V8 instructions.  */
3688   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3689     0x0320f005, 0x0fffffff, "sevl"},
3690   /* Defined in V8 but is in NOP space so available to all arch.  */
3691   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3692     0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
3693   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
3694     0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
3695   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3696     0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
3697   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3698     0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
3699   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3700     0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
3701   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3702     0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
3703   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3704     0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
3705   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3706     0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
3707   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3708     0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
3709   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3710     0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
3711   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3712     0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
3713   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3714     0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
3715   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3716     0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
3717   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3718     0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
3719   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3720     0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
3721   /* CRC32 instructions.  */
3722   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
3723     0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
3724   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
3725     0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
3726   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
3727     0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
3728   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
3729     0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
3730   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
3731     0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
3732   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
3733     0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
3734
3735   /* Privileged Access Never extension instructions.  */
3736   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
3737     0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
3738
3739   /* Virtualization Extension instructions.  */
3740   {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
3741   {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
3742
3743   /* Integer Divide Extension instructions.  */
3744   {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
3745     0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
3746   {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
3747     0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
3748
3749   /* MP Extension instructions.  */
3750   {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"},
3751
3752   /* Speculation Barriers.  */
3753   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xe320f014, 0xffffffff, "csdb"},
3754   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff040, 0xffffffff, "ssbb"},
3755   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff044, 0xffffffff, "pssbb"},
3756
3757   /* V7 instructions.  */
3758   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
3759   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
3760   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
3761   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
3762   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
3763   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
3764   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"},
3765    {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
3766     0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
3767
3768   /* ARM V6T2 instructions.  */
3769   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3770     0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
3771   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3772     0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
3773   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3774     0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3775   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3776     0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
3777
3778   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3779     0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
3780   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3781     0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
3782
3783   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3784     0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
3785   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3786     0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
3787   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3788     0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
3789   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3790     0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
3791
3792   /* ARM Security extension instructions.  */
3793   {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
3794     0x01600070, 0x0ff000f0, "smc%c\t%e"},
3795
3796   /* ARM V6K instructions.  */
3797   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3798     0xf57ff01f, 0xffffffff, "clrex"},
3799   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3800     0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
3801   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3802     0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
3803   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3804     0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
3805   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3806     0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
3807   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3808     0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
3809   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3810     0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
3811
3812   /* ARMv8.5-A instructions.  */
3813   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf57ff070, 0xffffffff, "sb"},
3814
3815   /* ARM V6K NOP hints.  */
3816   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3817     0x0320f001, 0x0fffffff, "yield%c"},
3818   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3819     0x0320f002, 0x0fffffff, "wfe%c"},
3820   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3821     0x0320f003, 0x0fffffff, "wfi%c"},
3822   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3823     0x0320f004, 0x0fffffff, "sev%c"},
3824   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3825     0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
3826
3827   /* ARM V6 instructions.  */
3828   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3829     0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
3830   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3831     0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
3832   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3833     0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
3834   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3835     0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
3836   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3837     0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
3838   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3839     0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
3840   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3841     0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
3842   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3843     0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
3844   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3845     0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
3846   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3847     0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
3848   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3849     0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
3850   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3851     0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
3852   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3853     0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
3854   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3855     0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
3856   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3857     0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
3858   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3859     0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
3860   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3861     0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
3862   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3863     0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
3864   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3865     0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
3866   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3867     0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
3868   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3869     0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
3870   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3871     0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
3872   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3873     0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
3874   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3875     0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
3876   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3877     0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
3878   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3879     0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
3880   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3881     0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
3882   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3883     0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
3884   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3885     0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
3886   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3887     0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
3888   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3889     0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
3890   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3891     0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
3892   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3893     0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
3894   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3895     0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
3896   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3897     0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
3898   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3899     0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
3900   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3901     0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
3902   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3903     0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
3904   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3905     0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
3906   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3907     0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
3908   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3909     0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
3910   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3911     0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
3912   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3913     0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
3914   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3915     0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
3916   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3917     0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
3918   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3919     0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
3920   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3921     0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
3922   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3923     0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
3924   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3925     0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
3926   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3927     0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
3928   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3929     0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
3930   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3931     0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
3932   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3933     0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
3934   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3935     0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
3936   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3937     0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
3938   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3939     0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
3940   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3941     0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
3942   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3943     0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
3944   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3945     0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
3946   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3947     0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
3948   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3949     0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
3950   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3951     0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
3952   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3953     0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
3954   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3955     0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
3956   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3957     0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
3958   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3959     0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
3960   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3961     0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
3962   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3963     0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
3964   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3965     0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
3966   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3967     0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
3968   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3969     0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
3970   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3971     0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
3972   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3973     0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
3974   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3975     0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
3976   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3977     0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
3978   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3979     0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3980   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3981     0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3982   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3983     0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3984   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3985     0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
3986   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3987     0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3988   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3989     0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3990   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3991     0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3992   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3993     0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
3994   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3995     0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3996   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3997     0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3998   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3999     0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
4000   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4001     0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
4002   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4003     0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
4004   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4005     0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
4006   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4007     0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
4008   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4009     0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
4010   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4011     0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
4012   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4013     0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
4014   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4015     0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
4016   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4017     0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
4018   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4019     0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
4020   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4021     0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
4022   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4023     0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
4024   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4025     0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
4026   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4027     0xf1010000, 0xfffffc00, "setend\t%9?ble"},
4028   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4029     0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
4030   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4031     0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
4032   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4033     0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4034   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4035     0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4036   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4037     0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4038   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4039     0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4040   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4041     0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
4042   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4043     0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4044   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4045     0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4046   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4047     0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
4048   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4049     0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
4050   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4051     0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
4052   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4053     0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
4054   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4055     0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
4056   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4057     0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
4058   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4059     0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
4060   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4061     0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
4062   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4063     0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4064   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4065     0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
4066   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4067     0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
4068   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4069     0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
4070   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4071     0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
4072
4073   /* V5J instruction.  */
4074   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J),
4075     0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
4076
4077   /* V5 Instructions.  */
4078   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
4079     0xe1200070, 0xfff000f0,
4080     "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
4081   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
4082     0xfa000000, 0xfe000000, "blx\t%B"},
4083   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
4084     0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
4085   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
4086     0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
4087
4088   /* V5E "El Segundo" Instructions.  */
4089   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
4090     0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
4091   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
4092     0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
4093   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
4094     0xf450f000, 0xfc70f000, "pld\t%a"},
4095   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4096     0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4097   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4098     0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4099   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4100     0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4101   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4102     0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
4103
4104   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4105     0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4106   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4107     0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
4108
4109   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4110     0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4111   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4112     0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4113   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4114     0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4115   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4116     0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4117
4118   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4119     0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
4120   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4121     0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
4122   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4123     0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
4124   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4125     0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
4126
4127   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4128     0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
4129   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4130     0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
4131
4132   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4133     0x01000050, 0x0ff00ff0,  "qadd%c\t%12-15R, %0-3R, %16-19R"},
4134   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4135     0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
4136   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4137     0x01200050, 0x0ff00ff0,  "qsub%c\t%12-15R, %0-3R, %16-19R"},
4138   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4139     0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
4140
4141   /* ARM Instructions.  */
4142   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4143     0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
4144
4145   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4146     0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
4147   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4148     0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
4149   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4150     0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
4151   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4152     0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
4153   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4154     0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
4155   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4156     0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
4157
4158   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4159     0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
4160   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4161     0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
4162   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4163     0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
4164   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4165     0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
4166
4167   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4168     0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
4169   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4170     0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
4171   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4172     0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
4173   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4174     0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
4175
4176   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4177     0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
4178   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4179     0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
4180   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4181     0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
4182
4183   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4184     0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
4185   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4186     0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
4187   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4188     0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
4189
4190   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4191     0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
4192   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4193     0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
4194   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4195     0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
4196
4197   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4198     0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
4199   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4200     0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
4201   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4202     0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
4203
4204   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4205     0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
4206   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4207     0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
4208   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4209     0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
4210
4211   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4212     0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
4213   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4214     0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
4215   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4216     0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
4217
4218   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4219     0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
4220   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4221     0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
4222   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4223     0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
4224
4225   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4226     0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
4227   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4228     0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
4229   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4230     0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
4231
4232   {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
4233     0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
4234   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
4235     0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
4236   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
4237     0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
4238
4239   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4240     0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
4241   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4242     0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
4243   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4244     0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
4245
4246   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4247     0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
4248   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4249     0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
4250   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4251     0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
4252
4253   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4254     0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
4255   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4256     0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
4257   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4258     0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
4259
4260   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4261     0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
4262   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4263     0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
4264   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4265     0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
4266
4267   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4268     0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
4269   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4270     0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
4271   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4272     0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
4273
4274   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4275     0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
4276   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4277     0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
4278   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4279     0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
4280   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4281     0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
4282   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4283     0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
4284   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4285     0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
4286   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4287     0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
4288
4289   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4290     0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
4291   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4292     0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
4293   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4294     0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
4295
4296   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4297     0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
4298   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4299     0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
4300   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4301     0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
4302
4303   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4304     0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
4305   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4306     0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
4307
4308   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4309     0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
4310
4311   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4312     0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
4313   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4314     0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
4315
4316   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4317     0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4318   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4319     0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4320   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4321     0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4322   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4323     0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4324   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4325     0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4326   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4327     0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4328   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4329     0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4330   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4331     0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4332   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4333     0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4334   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4335     0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4336   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4337     0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4338   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4339     0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4340   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4341     0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4342   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4343     0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4344   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4345     0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4346   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4347     0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4348   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4349     0x092d0000, 0x0fff0000, "push%c\t%m"},
4350   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4351     0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
4352   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4353     0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
4354
4355   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4356     0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4357   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4358     0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4359   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4360     0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4361   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4362     0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4363   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4364     0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4365   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4366     0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4367   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4368     0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4369   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4370     0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4371   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4372     0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4373   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4374     0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4375   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4376     0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4377   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4378     0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4379   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4380     0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4381   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4382     0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4383   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4384     0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4385   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4386     0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4387   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4388     0x08bd0000, 0x0fff0000, "pop%c\t%m"},
4389   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4390     0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
4391   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4392     0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
4393
4394   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4395     0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
4396   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4397     0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
4398
4399   /* The rest.  */
4400   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
4401     0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION},
4402   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4403     0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
4404   {ARM_FEATURE_CORE_LOW (0),
4405     0x00000000, 0x00000000, 0}
4406 };
4407
4408 /* print_insn_thumb16 recognizes the following format control codes:
4409
4410    %S                   print Thumb register (bits 3..5 as high number if bit 6 set)
4411    %D                   print Thumb register (bits 0..2 as high number if bit 7 set)
4412    %<bitfield>I         print bitfield as a signed decimal
4413                                 (top bit of range being the sign bit)
4414    %N                   print Thumb register mask (with LR)
4415    %O                   print Thumb register mask (with PC)
4416    %M                   print Thumb register mask
4417    %b                   print CZB's 6-bit unsigned branch destination
4418    %s                   print Thumb right-shift immediate (6..10; 0 == 32).
4419    %c                   print the condition code
4420    %C                   print the condition code, or "s" if not conditional
4421    %x                   print warning if conditional an not at end of IT block"
4422    %X                   print "\t; unpredictable <IT:code>" if conditional
4423    %I                   print IT instruction suffix and operands
4424    %W                   print Thumb Writeback indicator for LDMIA
4425    %<bitfield>r         print bitfield as an ARM register
4426    %<bitfield>d         print bitfield as a decimal
4427    %<bitfield>H         print (bitfield * 2) as a decimal
4428    %<bitfield>W         print (bitfield * 4) as a decimal
4429    %<bitfield>a         print (bitfield * 4) as a pc-rel offset + decoded symbol
4430    %<bitfield>B         print Thumb branch destination (signed displacement)
4431    %<bitfield>c         print bitfield as a condition code
4432    %<bitnum>'c          print specified char iff bit is one
4433    %<bitnum>?ab         print a if bit is one else print b.  */
4434
4435 static const struct opcode16 thumb_opcodes[] =
4436 {
4437   /* Thumb instructions.  */
4438
4439   /* ARMv8-M Security Extensions instructions.  */
4440   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"},
4441   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff87, "bxns\t%3-6r"},
4442
4443   /* ARM V8 instructions.  */
4444   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),  0xbf50, 0xffff, "sevl%c"},
4445   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),  0xba80, 0xffc0, "hlt\t%0-5x"},
4446   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),  0xb610, 0xfff7, "setpan\t#%3-3d"},
4447
4448   /* ARM V6K no-argument instructions.  */
4449   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
4450   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"},
4451   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"},
4452   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"},
4453   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"},
4454   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
4455
4456   /* ARM V6T2 instructions.  */
4457   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4458     0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
4459   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4460     0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
4461   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
4462
4463   /* ARM V6.  */
4464   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
4465   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
4466   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
4467   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
4468   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
4469   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
4470   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%3?ble%X"},
4471   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
4472   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
4473   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
4474   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
4475
4476   /* ARM V5 ISA extends Thumb.  */
4477   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
4478     0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional.  */
4479   /* This is BLX(2).  BLX(1) is a 32-bit instruction.  */
4480   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
4481     0x4780, 0xff87, "blx%c\t%3-6r%x"},  /* note: 4 bit register number.  */
4482   /* ARM V4T ISA (Thumb v1).  */
4483   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4484     0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
4485   /* Format 4.  */
4486   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
4487   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
4488   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
4489   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
4490   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
4491   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
4492   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
4493   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
4494   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
4495   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
4496   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
4497   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
4498   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
4499   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
4500   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
4501   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
4502   /* format 13 */
4503   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
4504   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
4505   /* format 5 */
4506   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"},
4507   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"},
4508   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
4509   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"},
4510   /* format 14 */
4511   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"},
4512   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"},
4513   /* format 2 */
4514   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4515     0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
4516   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4517     0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
4518   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4519     0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
4520   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4521     0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
4522   /* format 8 */
4523   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4524     0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
4525   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4526     0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
4527   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4528     0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
4529   /* format 7 */
4530   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4531     0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
4532   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4533     0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
4534   /* format 1 */
4535   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
4536   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4537     0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
4538   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
4539   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
4540   /* format 3 */
4541   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
4542   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
4543   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
4544   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
4545   /* format 6 */
4546   /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
4547   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4548     0x4800, 0xF800,
4549     "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
4550   /* format 9 */
4551   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4552     0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
4553   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4554     0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
4555   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4556     0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
4557   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4558     0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
4559   /* format 10 */
4560   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4561     0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
4562   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4563     0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
4564   /* format 11 */
4565   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4566     0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
4567   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4568     0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
4569   /* format 12 */
4570   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4571     0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
4572   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4573     0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
4574   /* format 15 */
4575   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
4576   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
4577   /* format 17 */
4578   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
4579   /* format 16 */
4580   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
4581   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
4582   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
4583   /* format 18 */
4584   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
4585
4586   /* The E800 .. FFFF range is unconditionally redirected to the
4587      32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
4588      are processed via that table.  Thus, we can never encounter a
4589      bare "second half of BL/BLX(1)" instruction here.  */
4590   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),  0x0000, 0x0000, UNDEFINED_INSTRUCTION},
4591   {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
4592 };
4593
4594 /* Thumb32 opcodes use the same table structure as the ARM opcodes.
4595    We adopt the convention that hw1 is the high 16 bits of .value and
4596    .mask, hw2 the low 16 bits.
4597
4598    print_insn_thumb32 recognizes the following format control codes:
4599
4600        %%               %
4601
4602        %I               print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
4603        %M               print a modified 12-bit immediate (same location)
4604        %J               print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
4605        %K               print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
4606        %H               print a 16-bit immediate from hw2[3:0],hw1[11:0]
4607        %S               print a possibly-shifted Rm
4608
4609        %L               print address for a ldrd/strd instruction
4610        %a               print the address of a plain load/store
4611        %w               print the width and signedness of a core load/store
4612        %m               print register mask for ldm/stm
4613        %n               print register mask for clrm
4614
4615        %E               print the lsb and width fields of a bfc/bfi instruction
4616        %F               print the lsb and width fields of a sbfx/ubfx instruction
4617        %G               print a fallback offset for Branch Future instructions
4618        %W               print an offset for BF instruction
4619        %Y               print an offset for BFL instruction
4620        %Z               print an offset for BFCSEL instruction
4621        %Q               print an offset for Low Overhead Loop instructions
4622        %P               print an offset for Low Overhead Loop end instructions
4623        %b               print a conditional branch offset
4624        %B               print an unconditional branch offset
4625        %s               print the shift field of an SSAT instruction
4626        %R               print the rotation field of an SXT instruction
4627        %U               print barrier type.
4628        %P               print address for pli instruction.
4629        %c               print the condition code
4630        %x               print warning if conditional an not at end of IT block"
4631        %X               print "\t; unpredictable <IT:code>" if conditional
4632
4633        %<bitfield>d     print bitfield in decimal
4634        %<bitfield>D     print bitfield plus one in decimal
4635        %<bitfield>W     print bitfield*4 in decimal
4636        %<bitfield>r     print bitfield as an ARM register
4637        %<bitfield>R     as %<>r but r15 is UNPREDICTABLE
4638        %<bitfield>S     as %<>r but r13 and r15 is UNPREDICTABLE
4639        %<bitfield>c     print bitfield as a condition code
4640
4641        %<bitfield>'c    print specified char iff bitfield is all ones
4642        %<bitfield>`c    print specified char iff bitfield is all zeroes
4643        %<bitfield>?ab... select from array of values in big endian order
4644
4645    With one exception at the bottom (done because BL and BLX(1) need
4646    to come dead last), this table was machine-sorted first in
4647    decreasing order of number of bits set in the mask, then in
4648    increasing numeric order of mask, then in increasing numeric order
4649    of opcode.  This order is not the clearest for a human reader, but
4650    is guaranteed never to catch a special-case bit pattern with a more
4651    general mask, which is important, because this instruction encoding
4652    makes heavy use of special-case bit patterns.  */
4653 static const struct opcode32 thumb32_opcodes[] =
4654 {
4655   /* Arm v8.1-M Mainline Pointer Authentication and Branch Target
4656      Identification Extension.  */
4657   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4658    0xf3af802d, 0xffffffff, "aut\tr12, lr, sp"},
4659   {ARM_FEATURE_CORE_HIGH_HIGH (ARM_EXT3_PACBTI),
4660    0xfb500f00, 0xfff00ff0, "autg%c\t%12-15r, %16-19r, %0-3r"},
4661   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4662    0xf3af800f, 0xffffffff, "bti"},
4663   {ARM_FEATURE_CORE_HIGH_HIGH (ARM_EXT3_PACBTI),
4664    0xfb500f10, 0xfff00ff0, "bxaut%c\t%12-15r, %16-19r, %0-3r"},
4665   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4666    0xf3af801d, 0xffffffff, "pac\tr12, lr, sp"},
4667   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4668    0xf3af800d, 0xffffffff, "pacbti\tr12, lr, sp"},
4669
4670   /* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions
4671      instructions.  */
4672   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4673     0xf00fe001, 0xffffffff, "lctp%c"},
4674   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4675     0xf02fc001, 0xfffff001, "le\t%P"},
4676   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4677     0xf00fc001, 0xfffff001, "le\tlr, %P"},
4678   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4679     0xf01fc001, 0xfffff001, "letp\tlr, %P"},
4680   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4681     0xf040c001, 0xfff0f001, "wls\tlr, %16-19S, %Q"},
4682   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4683     0xf000c001, 0xffc0f001, "wlstp.%20-21s\tlr, %16-19S, %Q"},
4684   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4685     0xf040e001, 0xfff0ffff, "dls\tlr, %16-19S"},
4686   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4687     0xf000e001, 0xffc0ffff, "dlstp.%20-21s\tlr, %16-19S"},
4688
4689   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4690     0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
4691   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4692     0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"},
4693   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4694     0xf000c001, 0xf800f001, "bfl%c\t%G, %Y"},
4695   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4696     0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"},
4697   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4698     0xf000e001, 0xf840f001, "bfcsel\t%G, %Z, %18-21c"},
4699
4700   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4701     0xe89f0000, 0xffff2000, "clrm%c\t%n"},
4702
4703   /* ARMv8-M and ARMv8-M Security Extensions instructions.  */
4704   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"},
4705   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4706     0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
4707   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4708     0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
4709   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4710     0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
4711   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4712     0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
4713
4714   /* ARM V8.2 RAS extension instructions.  */
4715   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
4716     0xf3af8010, 0xffffffff, "esb"},
4717
4718   /* V8 instructions.  */
4719   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4720     0xf3af8005, 0xffffffff, "sevl%c.w"},
4721   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4722     0xf78f8000, 0xfffffffc, "dcps%0-1d"},
4723   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4724     0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
4725   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4726     0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
4727   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4728     0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
4729   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4730     0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
4731   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4732     0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
4733   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4734     0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
4735   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4736     0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
4737   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4738     0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
4739   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4740     0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
4741   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4742     0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
4743   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4744     0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
4745   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4746     0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
4747   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4748     0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
4749   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4750     0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
4751
4752   /* V8-R instructions.  */
4753   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8R),
4754     0xf3bf8f4c, 0xffffffff, "dfb%c"},
4755
4756   /* CRC32 instructions.  */
4757   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
4758     0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},
4759   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
4760     0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"},
4761   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
4762     0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"},
4763   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
4764     0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"},
4765   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
4766     0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"},
4767   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
4768     0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
4769
4770   /* Speculation Barriers.  */
4771   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8014, 0xffffffff, "csdb"},
4772   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f40, 0xffffffff, "ssbb"},
4773   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f44, 0xffffffff, "pssbb"},
4774
4775   /* V7 instructions.  */
4776   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
4777   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
4778   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
4779   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
4780   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
4781   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
4782   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
4783   {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
4784     0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
4785   {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
4786     0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
4787
4788   /* Virtualization Extension instructions.  */
4789   {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
4790   /* We skip ERET as that is SUBS pc, lr, #0.  */
4791
4792   /* MP Extension instructions.  */
4793   {ARM_FEATURE_CORE_LOW (ARM_EXT_MP),   0xf830f000, 0xff70f000, "pldw%c\t%a"},
4794
4795   /* Security extension instructions.  */
4796   {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),  0xf7f08000, 0xfff0f000, "smc%c\t%K"},
4797
4798   /* ARMv8.5-A instructions.  */
4799   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf3bf8f70, 0xffffffff, "sb"},
4800
4801   /* Instructions defined in the basic V6T2 set.  */
4802   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
4803   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},
4804   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"},
4805   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"},
4806   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"},
4807   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4808     0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
4809   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
4810
4811   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4812     0xf3bf8f2f, 0xffffffff, "clrex%c"},
4813   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4814     0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
4815   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4816     0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
4817   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4818     0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
4819   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4820     0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
4821   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4822     0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
4823   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4824     0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
4825   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4826     0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
4827   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4828     0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
4829   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4830     0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
4831   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4832     0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
4833   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4834     0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
4835   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4836     0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
4837   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4838     0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
4839   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4840     0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
4841   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4842     0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
4843   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4844     0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
4845   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4846     0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
4847   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4848     0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
4849   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4850     0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
4851   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4852     0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
4853   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4854     0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
4855   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4856     0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
4857   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4858     0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
4859   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4860     0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
4861   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4862     0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
4863   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4864     0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
4865   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4866     0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
4867   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4868     0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
4869   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4870     0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
4871   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4872     0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
4873   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4874     0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
4875   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4876     0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
4877   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4878     0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
4879   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4880     0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
4881   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4882     0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
4883   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4884     0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
4885   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4886     0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
4887   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4888     0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
4889   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4890     0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
4891   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4892     0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
4893   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4894     0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
4895   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4896     0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
4897   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4898     0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
4899   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4900     0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
4901   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4902     0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
4903   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4904     0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
4905   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4906     0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
4907   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4908     0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
4909   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4910     0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
4911   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4912     0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
4913   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4914     0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
4915   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4916     0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
4917   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4918     0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
4919   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4920     0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
4921   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4922     0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
4923   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4924     0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
4925   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4926     0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
4927   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4928     0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
4929   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4930     0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
4931   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4932     0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
4933   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4934     0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
4935   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4936     0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
4937   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4938     0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
4939   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4940     0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
4941   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4942     0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
4943   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4944     0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
4945   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4946     0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
4947   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4948     0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
4949   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4950     0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
4951   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4952     0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
4953   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4954     0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
4955   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4956     0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
4957   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4958     0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
4959   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4960     0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4961   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4962     0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4963   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4964     0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4965   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4966     0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
4967   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4968     0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
4969   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4970     0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
4971   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4972     0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
4973   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4974     0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
4975   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4976     0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4977   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4978     0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
4979   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4980     0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
4981   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4982     0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4983   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4984     0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4985   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4986     0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4987   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4988     0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4989   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4990     0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4991   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4992     0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4993   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4994     0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4995   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4996     0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
4997   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4998     0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
4999   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5000     0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
5001   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5002     0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
5003   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5004     0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
5005   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5006     0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
5007   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5008     0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
5009   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5010     0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
5011   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5012     0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
5013   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5014     0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
5015   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5016     0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
5017   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5018     0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
5019   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5020     0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
5021   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5022     0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
5023   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5024     0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5025   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5026     0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5027   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5028     0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5029   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5030     0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5031   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5032     0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5033   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5034     0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5035   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
5036     0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
5037   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5038     0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
5039   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5040     0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
5041   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5042     0xf810f000, 0xff70f000, "pld%c\t%a"},
5043   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5044     0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5045   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5046     0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5047   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5048     0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5049   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5050     0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5051   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5052     0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5053   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5054     0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5055   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5056     0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5057   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5058     0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
5059   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5060     0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
5061   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5062     0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
5063   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5064     0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
5065   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5066     0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
5067   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5068     0xfb100000, 0xfff000c0,
5069     "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
5070   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5071     0xfbc00080, 0xfff000c0,
5072     "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
5073   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5074     0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
5075   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5076     0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
5077   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5078     0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
5079   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5080     0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
5081   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5082     0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
5083   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
5084     0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
5085   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5086     0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
5087   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
5088     0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
5089   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5090     0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
5091   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5092     0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
5093   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5094     0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
5095   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5096     0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
5097   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5098     0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
5099   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5100     0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
5101   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5102     0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
5103   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5104     0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
5105   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5106     0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
5107   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5108     0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
5109   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
5110     0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
5111   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5112     0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
5113   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5114     0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
5115   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5116     0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
5117   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5118     0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
5119   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5120     0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
5121   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5122     0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
5123   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5124     0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
5125   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5126     0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
5127   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5128     0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
5129   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5130     0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
5131   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5132     0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
5133   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5134     0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
5135   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5136     0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
5137   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5138     0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
5139   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5140     0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
5141   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5142     0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
5143   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5144     0xe9400000, 0xff500000,
5145     "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
5146   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5147     0xe9500000, 0xff500000,
5148     "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
5149   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5150     0xe8600000, 0xff700000,
5151     "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
5152   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5153     0xe8700000, 0xff700000,
5154     "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
5155   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5156     0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
5157   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5158     0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
5159
5160   /* Filter out Bcc with cond=E or F, which are used for other instructions.  */
5161   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5162     0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
5163   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5164     0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
5165   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5166     0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
5167   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5168     0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
5169
5170   /* These have been 32-bit since the invention of Thumb.  */
5171   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
5172      0xf000c000, 0xf800d001, "blx%c\t%B%x"},
5173   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
5174      0xf000d000, 0xf800d000, "bl%c\t%B%x"},
5175
5176   /* Fallback.  */
5177   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
5178       0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
5179   {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
5180 };
5181
5182 static const char *const arm_conditional[] =
5183 {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
5184  "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
5185
5186 static const char *const arm_fp_const[] =
5187 {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
5188
5189 static const char *const arm_shift[] =
5190 {"lsl", "lsr", "asr", "ror"};
5191
5192 typedef struct
5193 {
5194   const char *name;
5195   const char *description;
5196   const char *reg_names[16];
5197 }
5198 arm_regname;
5199
5200 static const arm_regname regnames[] =
5201 {
5202   { "reg-names-raw", N_("Select raw register names"),
5203     { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
5204   { "reg-names-gcc", N_("Select register names used by GCC"),
5205     { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl",  "fp",  "ip",  "sp",  "lr",  "pc" }},
5206   { "reg-names-std", N_("Select register names used in ARM's ISA documentation"),
5207     { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp",  "lr",  "pc" }},
5208   { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL} },
5209   { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL} },
5210   { "reg-names-apcs", N_("Select register names used in the APCS"),
5211     { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl",  "fp",  "ip",  "sp",  "lr",  "pc" }},
5212   { "reg-names-atpcs", N_("Select register names used in the ATPCS"),
5213     { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7",  "v8",  "IP",  "SP",  "LR",  "PC" }},
5214   { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
5215     { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL",  "FP",  "IP",  "SP",  "LR",  "PC" }},
5216   { "coproc<N>=(cde|generic)", N_("Enable CDE extensions for coprocessor N space"), { NULL } }
5217 };
5218
5219 static const char *const iwmmxt_wwnames[] =
5220 {"b", "h", "w", "d"};
5221
5222 static const char *const iwmmxt_wwssnames[] =
5223 {"b", "bus", "bc", "bss",
5224  "h", "hus", "hc", "hss",
5225  "w", "wus", "wc", "wss",
5226  "d", "dus", "dc", "dss"
5227 };
5228
5229 static const char *const iwmmxt_regnames[] =
5230 { "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
5231   "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
5232 };
5233
5234 static const char *const iwmmxt_cregnames[] =
5235 { "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
5236   "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
5237 };
5238
5239 static const char *const vec_condnames[] =
5240 { "eq", "ne", "cs", "hi", "ge", "lt", "gt", "le"
5241 };
5242
5243 static const char *const mve_predicatenames[] =
5244 { "", "ttt", "tt", "tte", "t", "tee", "te", "tet", "",
5245   "eee", "ee", "eet", "e", "ett", "et", "ete"
5246 };
5247
5248 /* Names for 2-bit size field for mve vector isntructions.  */
5249 static const char *const mve_vec_sizename[] =
5250   { "8", "16", "32", "64"};
5251
5252 /* Indicates whether we are processing a then predicate,
5253    else predicate or none at all.  */
5254 enum vpt_pred_state
5255 {
5256   PRED_NONE,
5257   PRED_THEN,
5258   PRED_ELSE
5259 };
5260
5261 /* Information used to process a vpt block and subsequent instructions.  */
5262 struct vpt_block
5263 {
5264   /* Are we in a vpt block.  */
5265   bool in_vpt_block;
5266
5267   /* Next predicate state if in vpt block.  */
5268   enum vpt_pred_state next_pred_state;
5269
5270   /* Mask from vpt/vpst instruction.  */
5271   long predicate_mask;
5272
5273   /* Instruction number in vpt block.  */
5274   long current_insn_num;
5275
5276   /* Number of instructions in vpt block..   */
5277   long num_pred_insn;
5278 };
5279
5280 static struct vpt_block vpt_block_state =
5281 {
5282   false,
5283   PRED_NONE,
5284   0,
5285   0,
5286   0
5287 };
5288
5289 /* Default to GCC register name set.  */
5290 static unsigned int regname_selected = 1;
5291
5292 #define NUM_ARM_OPTIONS   ARRAY_SIZE (regnames)
5293 #define arm_regnames      regnames[regname_selected].reg_names
5294
5295 static bool force_thumb = false;
5296 static uint16_t cde_coprocs = 0;
5297
5298 /* Current IT instruction state.  This contains the same state as the IT
5299    bits in the CPSR.  */
5300 static unsigned int ifthen_state;
5301 /* IT state for the next instruction.  */
5302 static unsigned int ifthen_next_state;
5303 /* The address of the insn for which the IT state is valid.  */
5304 static bfd_vma ifthen_address;
5305 #define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
5306 /* Indicates that the current Conditional state is unconditional or outside
5307    an IT block.  */
5308 #define COND_UNCOND 16
5309
5310 \f
5311 /* Functions.  */
5312 /* Extract the predicate mask for a VPT or VPST instruction.
5313    The mask is composed of bits 13-15 (Mkl) and bit 22 (Mkh).  */
5314
5315 static long
5316 mve_extract_pred_mask (long given)
5317 {
5318   return ((given & 0x00400000) >> 19) | ((given & 0xe000) >> 13);
5319 }
5320
5321 /* Return the number of instructions in a MVE predicate block.  */
5322 static long
5323 num_instructions_vpt_block (long given)
5324 {
5325   long mask = mve_extract_pred_mask (given);
5326   if (mask == 0)
5327     return 0;
5328
5329   if (mask == 8)
5330     return 1;
5331
5332   if ((mask & 7) == 4)
5333     return 2;
5334
5335   if ((mask & 3) == 2)
5336     return 3;
5337
5338   if ((mask & 1) == 1)
5339     return 4;
5340
5341   return 0;
5342 }
5343
5344 static void
5345 mark_outside_vpt_block (void)
5346 {
5347   vpt_block_state.in_vpt_block = false;
5348   vpt_block_state.next_pred_state = PRED_NONE;
5349   vpt_block_state.predicate_mask = 0;
5350   vpt_block_state.current_insn_num = 0;
5351   vpt_block_state.num_pred_insn = 0;
5352 }
5353
5354 static void
5355 mark_inside_vpt_block (long given)
5356 {
5357   vpt_block_state.in_vpt_block = true;
5358   vpt_block_state.next_pred_state = PRED_THEN;
5359   vpt_block_state.predicate_mask = mve_extract_pred_mask (given);
5360   vpt_block_state.current_insn_num = 0;
5361   vpt_block_state.num_pred_insn = num_instructions_vpt_block (given);
5362   assert (vpt_block_state.num_pred_insn >= 1);
5363 }
5364
5365 static enum vpt_pred_state
5366 invert_next_predicate_state (enum vpt_pred_state astate)
5367 {
5368   if (astate == PRED_THEN)
5369     return PRED_ELSE;
5370   else if (astate == PRED_ELSE)
5371     return PRED_THEN;
5372   else
5373     return PRED_NONE;
5374 }
5375
5376 static enum vpt_pred_state
5377 update_next_predicate_state (void)
5378 {
5379   long pred_mask = vpt_block_state.predicate_mask;
5380   long mask_for_insn = 0;
5381
5382   switch (vpt_block_state.current_insn_num)
5383     {
5384     case 1:
5385       mask_for_insn = 8;
5386       break;
5387
5388     case 2:
5389       mask_for_insn = 4;
5390       break;
5391
5392     case 3:
5393       mask_for_insn = 2;
5394       break;
5395
5396     case 4:
5397       return PRED_NONE;
5398     }
5399
5400   if (pred_mask & mask_for_insn)
5401     return invert_next_predicate_state (vpt_block_state.next_pred_state);
5402   else
5403     return vpt_block_state.next_pred_state;
5404 }
5405
5406 static void
5407 update_vpt_block_state (void)
5408 {
5409   vpt_block_state.current_insn_num++;
5410   if (vpt_block_state.current_insn_num == vpt_block_state.num_pred_insn)
5411     {
5412       /* No more instructions to process in vpt block.  */
5413       mark_outside_vpt_block ();
5414       return;
5415     }
5416
5417   vpt_block_state.next_pred_state = update_next_predicate_state ();
5418 }
5419
5420 /* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
5421    Returns pointer to following character of the format string and
5422    fills in *VALUEP and *WIDTHP with the extracted value and number of
5423    bits extracted.  WIDTHP can be NULL.  */
5424
5425 static const char *
5426 arm_decode_bitfield (const char *ptr,
5427                      unsigned long insn,
5428                      unsigned long *valuep,
5429                      int *widthp)
5430 {
5431   unsigned long value = 0;
5432   int width = 0;
5433
5434   do
5435     {
5436       int start, end;
5437       int bits;
5438
5439       for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
5440         start = start * 10 + *ptr - '0';
5441       if (*ptr == '-')
5442         for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
5443           end = end * 10 + *ptr - '0';
5444       else
5445         end = start;
5446       bits = end - start;
5447       if (bits < 0)
5448         abort ();
5449       value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
5450       width += bits + 1;
5451     }
5452   while (*ptr++ == ',');
5453   *valuep = value;
5454   if (widthp)
5455     *widthp = width;
5456   return ptr - 1;
5457 }
5458
5459 static void
5460 arm_decode_shift (long given, fprintf_ftype func, void *stream,
5461                   bool print_shift)
5462 {
5463   func (stream, "%s", arm_regnames[given & 0xf]);
5464
5465   if ((given & 0xff0) != 0)
5466     {
5467       if ((given & 0x10) == 0)
5468         {
5469           int amount = (given & 0xf80) >> 7;
5470           int shift = (given & 0x60) >> 5;
5471
5472           if (amount == 0)
5473             {
5474               if (shift == 3)
5475                 {
5476                   func (stream, ", rrx");
5477                   return;
5478                 }
5479
5480               amount = 32;
5481             }
5482
5483           if (print_shift)
5484             func (stream, ", %s #%d", arm_shift[shift], amount);
5485           else
5486             func (stream, ", #%d", amount);
5487         }
5488       else if ((given & 0x80) == 0x80)
5489         func (stream, "\t; <illegal shifter operand>");
5490       else if (print_shift)
5491         func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
5492               arm_regnames[(given & 0xf00) >> 8]);
5493       else
5494         func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
5495     }
5496 }
5497
5498 /* Return TRUE if the MATCHED_INSN can be inside an IT block.  */
5499
5500 static bool
5501 is_mve_okay_in_it (enum mve_instructions matched_insn)
5502 {
5503   switch (matched_insn)
5504     {
5505     case MVE_VMOV_GP_TO_VEC_LANE:
5506     case MVE_VMOV2_VEC_LANE_TO_GP:
5507     case MVE_VMOV2_GP_TO_VEC_LANE:
5508     case MVE_VMOV_VEC_LANE_TO_GP:
5509     case MVE_LSLL:
5510     case MVE_LSLLI:
5511     case MVE_LSRL:
5512     case MVE_ASRL:
5513     case MVE_ASRLI:
5514     case MVE_SQRSHRL:
5515     case MVE_SQRSHR:
5516     case MVE_UQRSHL:
5517     case MVE_UQRSHLL:
5518     case MVE_UQSHL:
5519     case MVE_UQSHLL:
5520     case MVE_URSHRL:
5521     case MVE_URSHR:
5522     case MVE_SRSHRL:
5523     case MVE_SRSHR:
5524     case MVE_SQSHLL:
5525     case MVE_SQSHL:
5526       return true;
5527     default:
5528       return false;
5529     }
5530 }
5531
5532 static bool
5533 is_mve_architecture (struct disassemble_info *info)
5534 {
5535   struct arm_private_data *private_data = info->private_data;
5536   arm_feature_set allowed_arches = private_data->features;
5537
5538   arm_feature_set arm_ext_v8_1m_main
5539     = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
5540
5541   if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
5542       && !ARM_CPU_IS_ANY (allowed_arches))
5543     return true;
5544   else
5545     return false;
5546 }
5547
5548 static bool
5549 is_vpt_instruction (long given)
5550 {
5551
5552   /* If mkh:mkl is '0000' then its not a vpt/vpst instruction.  */
5553   if ((given & 0x0040e000) == 0)
5554     return false;
5555
5556   /* VPT floating point T1 variant.  */
5557   if (((given & 0xefb10f50) == 0xee310f00 && ((given & 0x1001) != 0x1))
5558   /* VPT floating point T2 variant.  */
5559       || ((given & 0xefb10f50) == 0xee310f40)
5560   /* VPT vector T1 variant.  */
5561       || ((given & 0xff811f51) == 0xfe010f00)
5562   /* VPT vector T2 variant.  */
5563       || ((given & 0xff811f51) == 0xfe010f01
5564           && ((given & 0x300000) != 0x300000))
5565   /* VPT vector T3 variant.  */
5566       || ((given & 0xff811f50) == 0xfe011f00)
5567   /* VPT vector T4 variant.  */
5568       || ((given & 0xff811f70) == 0xfe010f40)
5569   /* VPT vector T5 variant.  */
5570       || ((given & 0xff811f70) == 0xfe010f60)
5571   /* VPT vector T6 variant.  */
5572       || ((given & 0xff811f50) == 0xfe011f40)
5573   /* VPST vector T variant.  */
5574       || ((given & 0xffbf1fff) == 0xfe310f4d))
5575     return true;
5576   else
5577     return false;
5578 }
5579
5580 /* Decode a bitfield from opcode GIVEN, with starting bitfield = START
5581    and ending bitfield = END.  END must be greater than START.  */
5582
5583 static unsigned long
5584 arm_decode_field (unsigned long given, unsigned int start, unsigned int end)
5585 {
5586   int bits = end - start;
5587
5588   if (bits < 0)
5589     abort ();
5590
5591   return ((given >> start) & ((2ul << bits) - 1));
5592 }
5593
5594 /* Decode a bitfield from opcode GIVEN, with multiple bitfields:
5595    START:END and START2:END2.  END/END2 must be greater than
5596    START/START2.  */
5597
5598 static unsigned long
5599 arm_decode_field_multiple (unsigned long given, unsigned int start,
5600                            unsigned int end, unsigned int start2,
5601                            unsigned int end2)
5602 {
5603   int bits = end - start;
5604   int bits2 = end2 - start2;
5605   unsigned long value = 0;
5606   int width = 0;
5607
5608   if (bits2 < 0)
5609     abort ();
5610
5611   value = arm_decode_field (given, start, end);
5612   width += bits + 1;
5613
5614   value |= ((given >> start2) & ((2ul << bits2) - 1)) << width;
5615   return value;
5616 }
5617
5618 /* Return TRUE if the GIVEN encoding should not be decoded as MATCHED_INSN.
5619    This helps us decode instructions that change mnemonic depending on specific
5620    operand values/encodings.  */
5621
5622 static bool
5623 is_mve_encoding_conflict (unsigned long given,
5624                           enum mve_instructions matched_insn)
5625 {
5626   switch (matched_insn)
5627     {
5628     case MVE_VPST:
5629       if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5630         return true;
5631       else
5632         return false;
5633
5634     case MVE_VPT_FP_T1:
5635       if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5636         return true;
5637       if ((arm_decode_field (given, 12, 12) == 0)
5638           && (arm_decode_field (given, 0, 0) == 1))
5639         return true;
5640       return false;
5641
5642     case MVE_VPT_FP_T2:
5643       if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5644         return true;
5645       if (arm_decode_field (given, 0, 3) == 0xd)
5646         return true;
5647       return false;
5648
5649     case MVE_VPT_VEC_T1:
5650     case MVE_VPT_VEC_T2:
5651     case MVE_VPT_VEC_T3:
5652     case MVE_VPT_VEC_T4:
5653     case MVE_VPT_VEC_T5:
5654     case MVE_VPT_VEC_T6:
5655       if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5656         return true;
5657       if (arm_decode_field (given, 20, 21) == 3)
5658         return true;
5659       return false;
5660
5661     case MVE_VCMP_FP_T1:
5662       if ((arm_decode_field (given, 12, 12) == 0)
5663           && (arm_decode_field (given, 0, 0) == 1))
5664         return true;
5665       else
5666         return false;
5667
5668     case MVE_VCMP_FP_T2:
5669       if (arm_decode_field (given, 0, 3) == 0xd)
5670         return true;
5671       else
5672         return false;
5673
5674     case MVE_VQADD_T2:
5675     case MVE_VQSUB_T2:
5676     case MVE_VMUL_VEC_T2:
5677     case MVE_VMULH:
5678     case MVE_VRMULH:
5679     case MVE_VMLA:
5680     case MVE_VMAX:
5681     case MVE_VMIN:
5682     case MVE_VBRSR:
5683     case MVE_VADD_VEC_T2:
5684     case MVE_VSUB_VEC_T2:
5685     case MVE_VABAV:
5686     case MVE_VQRSHL_T1:
5687     case MVE_VQSHL_T4:
5688     case MVE_VRSHL_T1:
5689     case MVE_VSHL_T3:
5690     case MVE_VCADD_VEC:
5691     case MVE_VHCADD:
5692     case MVE_VDDUP:
5693     case MVE_VIDUP:
5694     case MVE_VQRDMLADH:
5695     case MVE_VQDMLAH:
5696     case MVE_VQRDMLAH:
5697     case MVE_VQDMLASH:
5698     case MVE_VQRDMLASH:
5699     case MVE_VQDMLSDH:
5700     case MVE_VQRDMLSDH:
5701     case MVE_VQDMULH_T3:
5702     case MVE_VQRDMULH_T4:
5703     case MVE_VQDMLADH:
5704     case MVE_VMLAS:
5705     case MVE_VMULL_INT:
5706     case MVE_VHADD_T2:
5707     case MVE_VHSUB_T2:
5708     case MVE_VCMP_VEC_T1:
5709     case MVE_VCMP_VEC_T2:
5710     case MVE_VCMP_VEC_T3:
5711     case MVE_VCMP_VEC_T4:
5712     case MVE_VCMP_VEC_T5:
5713     case MVE_VCMP_VEC_T6:
5714       if (arm_decode_field (given, 20, 21) == 3)
5715         return true;
5716       else
5717         return false;
5718
5719     case MVE_VLD2:
5720     case MVE_VLD4:
5721     case MVE_VST2:
5722     case MVE_VST4:
5723       if (arm_decode_field (given, 7, 8) == 3)
5724         return true;
5725       else
5726         return false;
5727
5728     case MVE_VSTRB_T1:
5729     case MVE_VSTRH_T2:
5730       if ((arm_decode_field (given, 24, 24) == 0)
5731           && (arm_decode_field (given, 21, 21) == 0))
5732         {
5733             return true;
5734         }
5735       else if ((arm_decode_field (given, 7, 8) == 3))
5736         return true;
5737       else
5738         return false;
5739
5740     case MVE_VLDRB_T1:
5741     case MVE_VLDRH_T2:
5742     case MVE_VLDRW_T7:
5743     case MVE_VSTRB_T5:
5744     case MVE_VSTRH_T6:
5745     case MVE_VSTRW_T7:
5746       if ((arm_decode_field (given, 24, 24) == 0)
5747           && (arm_decode_field (given, 21, 21) == 0))
5748         {
5749             return true;
5750         }
5751       else
5752         return false;
5753
5754     case MVE_VCVT_FP_FIX_VEC:
5755       return (arm_decode_field (given, 16, 21) & 0x38) == 0;
5756
5757     case MVE_VBIC_IMM:
5758     case MVE_VORR_IMM:
5759       {
5760         unsigned long cmode = arm_decode_field (given, 8, 11);
5761
5762         if ((cmode & 1) == 0)
5763           return true;
5764         else if ((cmode & 0xc) == 0xc)
5765           return true;
5766         else
5767           return false;
5768       }
5769
5770     case MVE_VMVN_IMM:
5771       {
5772         unsigned long cmode = arm_decode_field (given, 8, 11);
5773
5774         if (cmode == 0xe)
5775           return true;
5776         else if ((cmode & 0x9) == 1)
5777           return true;
5778         else if ((cmode & 0xd) == 9)
5779           return true;
5780         else
5781           return false;
5782       }
5783
5784     case MVE_VMOV_IMM_TO_VEC:
5785       if ((arm_decode_field (given, 5, 5) == 1)
5786           && (arm_decode_field (given, 8, 11) != 0xe))
5787         return true;
5788       else
5789         return false;
5790
5791     case MVE_VMOVL:
5792       {
5793         unsigned long size = arm_decode_field (given, 19, 20);
5794         if ((size == 0) || (size == 3))
5795           return true;
5796         else
5797           return false;
5798       }
5799
5800     case MVE_VMAXA:
5801     case MVE_VMINA:
5802     case MVE_VMAXV:
5803     case MVE_VMAXAV:
5804     case MVE_VMINV:
5805     case MVE_VMINAV:
5806     case MVE_VQRSHL_T2:
5807     case MVE_VQSHL_T1:
5808     case MVE_VRSHL_T2:
5809     case MVE_VSHL_T2:
5810     case MVE_VSHLL_T2:
5811     case MVE_VADDV:
5812     case MVE_VMOVN:
5813     case MVE_VQMOVUN:
5814     case MVE_VQMOVN:
5815       if (arm_decode_field (given, 18, 19) == 3)
5816         return true;
5817       else
5818         return false;
5819
5820     case MVE_VMLSLDAV:
5821     case MVE_VRMLSLDAVH:
5822     case MVE_VMLALDAV:
5823     case MVE_VADDLV:
5824       if (arm_decode_field (given, 20, 22) == 7)
5825         return true;
5826       else
5827         return false;
5828
5829     case MVE_VRMLALDAVH:
5830       if ((arm_decode_field (given, 20, 22) & 6) == 6)
5831         return true;
5832       else
5833         return false;
5834
5835     case MVE_VDWDUP:
5836     case MVE_VIWDUP:
5837       if ((arm_decode_field (given, 20, 21) == 3)
5838           || (arm_decode_field (given, 1, 3) == 7))
5839         return true;
5840       else
5841         return false;
5842
5843
5844     case MVE_VSHLL_T1:
5845       if (arm_decode_field (given, 16, 18) == 0)
5846         {
5847           unsigned long sz = arm_decode_field (given, 19, 20);
5848
5849           if ((sz == 1) || (sz == 2))
5850             return true;
5851           else
5852             return false;
5853         }
5854       else
5855         return false;
5856
5857     case MVE_VQSHL_T2:
5858     case MVE_VQSHLU_T3:
5859     case MVE_VRSHR:
5860     case MVE_VSHL_T1:
5861     case MVE_VSHR:
5862     case MVE_VSLI:
5863     case MVE_VSRI:
5864       if (arm_decode_field (given, 19, 21) == 0)
5865         return true;
5866       else
5867         return false;
5868
5869     case MVE_VCTP:
5870     if (arm_decode_field (given, 16, 19) == 0xf)
5871       return true;
5872     else
5873       return false;
5874
5875     case MVE_ASRLI:
5876     case MVE_ASRL:
5877     case MVE_LSLLI:
5878     case MVE_LSLL:
5879     case MVE_LSRL:
5880     case MVE_SQRSHRL:
5881     case MVE_SQSHLL:
5882     case MVE_SRSHRL:
5883     case MVE_UQRSHLL:
5884     case MVE_UQSHLL:
5885     case MVE_URSHRL:
5886       if (arm_decode_field (given, 9, 11) == 0x7)
5887         return true;
5888       else
5889         return false;
5890
5891     case MVE_CSINC:
5892     case MVE_CSINV:
5893       {
5894         unsigned long rm, rn;
5895         rm = arm_decode_field (given, 0, 3);
5896         rn = arm_decode_field (given, 16, 19);
5897         /* CSET/CSETM.  */
5898         if (rm == 0xf && rn == 0xf)
5899           return true;
5900         /* CINC/CINV.  */
5901         else if (rn == rm && rn != 0xf)
5902           return true;
5903       }
5904     /* Fall through.  */
5905     case MVE_CSEL:
5906     case MVE_CSNEG:
5907       if (arm_decode_field (given, 0, 3) == 0xd)
5908         return true;
5909       /* CNEG.  */
5910       else if (matched_insn == MVE_CSNEG)
5911         if (arm_decode_field (given, 0, 3) == arm_decode_field (given, 16, 19))
5912           return true;
5913       return false;
5914
5915     default:
5916     case MVE_VADD_FP_T1:
5917     case MVE_VADD_FP_T2:
5918     case MVE_VADD_VEC_T1:
5919       return false;
5920
5921     }
5922 }
5923
5924 static void
5925 print_mve_vld_str_addr (struct disassemble_info *info,
5926                         unsigned long given,
5927                         enum mve_instructions matched_insn)
5928 {
5929   void *stream = info->stream;
5930   fprintf_ftype func = info->fprintf_func;
5931
5932   unsigned long p, w, gpr, imm, add, mod_imm;
5933
5934   imm = arm_decode_field (given, 0, 6);
5935   mod_imm = imm;
5936
5937   switch (matched_insn)
5938     {
5939     case MVE_VLDRB_T1:
5940     case MVE_VSTRB_T1:
5941       gpr = arm_decode_field (given, 16, 18);
5942       break;
5943
5944     case MVE_VLDRH_T2:
5945     case MVE_VSTRH_T2:
5946       gpr = arm_decode_field (given, 16, 18);
5947       mod_imm = imm << 1;
5948       break;
5949
5950     case MVE_VLDRH_T6:
5951     case MVE_VSTRH_T6:
5952       gpr = arm_decode_field (given, 16, 19);
5953       mod_imm = imm << 1;
5954       break;
5955
5956     case MVE_VLDRW_T7:
5957     case MVE_VSTRW_T7:
5958       gpr = arm_decode_field (given, 16, 19);
5959       mod_imm = imm << 2;
5960       break;
5961
5962     case MVE_VLDRB_T5:
5963     case MVE_VSTRB_T5:
5964       gpr = arm_decode_field (given, 16, 19);
5965       break;
5966
5967     default:
5968       return;
5969     }
5970
5971   p = arm_decode_field (given, 24, 24);
5972   w = arm_decode_field (given, 21, 21);
5973
5974   add = arm_decode_field (given, 23, 23);
5975
5976   char * add_sub;
5977
5978   /* Don't print anything for '+' as it is implied.  */
5979   if (add == 1)
5980     add_sub = "";
5981   else
5982     add_sub = "-";
5983
5984   if (p == 1)
5985     {
5986       /* Offset mode.  */
5987       if (w == 0)
5988         func (stream, "[%s, #%s%lu]", arm_regnames[gpr], add_sub, mod_imm);
5989       /* Pre-indexed mode.  */
5990       else
5991         func (stream, "[%s, #%s%lu]!", arm_regnames[gpr], add_sub, mod_imm);
5992     }
5993   else if ((p == 0) && (w == 1))
5994     /* Post-index mode.  */
5995     func (stream, "[%s], #%s%lu", arm_regnames[gpr], add_sub, mod_imm);
5996 }
5997
5998 /* Return FALSE if GIVEN is not an undefined encoding for MATCHED_INSN.
5999    Otherwise, return TRUE and set UNDEFINED_CODE to give a reason as to why
6000    this encoding is undefined.  */
6001
6002 static bool
6003 is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
6004                   enum mve_undefined *undefined_code)
6005 {
6006   *undefined_code = UNDEF_NONE;
6007
6008   switch (matched_insn)
6009     {
6010     case MVE_VDUP:
6011       if (arm_decode_field_multiple (given, 5, 5, 22, 22) == 3)
6012         {
6013           *undefined_code = UNDEF_SIZE_3;
6014           return true;
6015         }
6016       else
6017         return false;
6018
6019     case MVE_VQADD_T1:
6020     case MVE_VQSUB_T1:
6021     case MVE_VMUL_VEC_T1:
6022     case MVE_VABD_VEC:
6023     case MVE_VADD_VEC_T1:
6024     case MVE_VSUB_VEC_T1:
6025     case MVE_VQDMULH_T1:
6026     case MVE_VQRDMULH_T2:
6027     case MVE_VRHADD:
6028     case MVE_VHADD_T1:
6029     case MVE_VHSUB_T1:
6030       if (arm_decode_field (given, 20, 21) == 3)
6031         {
6032           *undefined_code = UNDEF_SIZE_3;
6033           return true;
6034         }
6035       else
6036         return false;
6037
6038     case MVE_VLDRB_T1:
6039       if (arm_decode_field (given, 7, 8) == 3)
6040         {
6041           *undefined_code = UNDEF_SIZE_3;
6042           return true;
6043         }
6044       else
6045         return false;
6046
6047     case MVE_VLDRH_T2:
6048       if (arm_decode_field (given, 7, 8) <= 1)
6049         {
6050           *undefined_code = UNDEF_SIZE_LE_1;
6051           return true;
6052         }
6053       else
6054         return false;
6055
6056     case MVE_VSTRB_T1:
6057       if ((arm_decode_field (given, 7, 8) == 0))
6058         {
6059           *undefined_code = UNDEF_SIZE_0;
6060           return true;
6061         }
6062       else
6063         return false;
6064
6065     case MVE_VSTRH_T2:
6066       if ((arm_decode_field (given, 7, 8) <= 1))
6067         {
6068           *undefined_code = UNDEF_SIZE_LE_1;
6069           return true;
6070         }
6071       else
6072         return false;
6073
6074     case MVE_VLDRB_GATHER_T1:
6075       if (arm_decode_field (given, 7, 8) == 3)
6076         {
6077           *undefined_code = UNDEF_SIZE_3;
6078           return true;
6079         }
6080       else if ((arm_decode_field (given, 28, 28) == 0)
6081                && (arm_decode_field (given, 7, 8) == 0))
6082         {
6083           *undefined_code = UNDEF_NOT_UNS_SIZE_0;
6084           return true;
6085         }
6086       else
6087         return false;
6088
6089     case MVE_VLDRH_GATHER_T2:
6090       if (arm_decode_field (given, 7, 8) == 3)
6091         {
6092           *undefined_code = UNDEF_SIZE_3;
6093           return true;
6094         }
6095       else if ((arm_decode_field (given, 28, 28) == 0)
6096                && (arm_decode_field (given, 7, 8) == 1))
6097         {
6098           *undefined_code = UNDEF_NOT_UNS_SIZE_1;
6099           return true;
6100         }
6101       else if (arm_decode_field (given, 7, 8) == 0)
6102         {
6103           *undefined_code = UNDEF_SIZE_0;
6104           return true;
6105         }
6106       else
6107         return false;
6108
6109     case MVE_VLDRW_GATHER_T3:
6110       if (arm_decode_field (given, 7, 8) != 2)
6111         {
6112           *undefined_code = UNDEF_SIZE_NOT_2;
6113           return true;
6114         }
6115       else if (arm_decode_field (given, 28, 28) == 0)
6116         {
6117           *undefined_code = UNDEF_NOT_UNSIGNED;
6118           return true;
6119         }
6120       else
6121         return false;
6122
6123     case MVE_VLDRD_GATHER_T4:
6124       if (arm_decode_field (given, 7, 8) != 3)
6125         {
6126           *undefined_code = UNDEF_SIZE_NOT_3;
6127           return true;
6128         }
6129       else if (arm_decode_field (given, 28, 28) == 0)
6130         {
6131           *undefined_code = UNDEF_NOT_UNSIGNED;
6132           return true;
6133         }
6134       else
6135         return false;
6136
6137     case MVE_VSTRB_SCATTER_T1:
6138       if (arm_decode_field (given, 7, 8) == 3)
6139         {
6140           *undefined_code = UNDEF_SIZE_3;
6141           return true;
6142         }
6143       else
6144         return false;
6145
6146     case MVE_VSTRH_SCATTER_T2:
6147       {
6148         unsigned long size = arm_decode_field (given, 7, 8);
6149         if (size == 3)
6150           {
6151             *undefined_code = UNDEF_SIZE_3;
6152             return true;
6153           }
6154         else if (size == 0)
6155           {
6156             *undefined_code = UNDEF_SIZE_0;
6157             return true;
6158           }
6159         else
6160           return false;
6161       }
6162
6163     case MVE_VSTRW_SCATTER_T3:
6164       if (arm_decode_field (given, 7, 8) != 2)
6165         {
6166           *undefined_code = UNDEF_SIZE_NOT_2;
6167           return true;
6168         }
6169       else
6170         return false;
6171
6172     case MVE_VSTRD_SCATTER_T4:
6173       if (arm_decode_field (given, 7, 8) != 3)
6174         {
6175           *undefined_code = UNDEF_SIZE_NOT_3;
6176           return true;
6177         }
6178       else
6179         return false;
6180
6181     case MVE_VCVT_FP_FIX_VEC:
6182       {
6183         unsigned long imm6 = arm_decode_field (given, 16, 21);
6184         if ((imm6 & 0x20) == 0)
6185           {
6186             *undefined_code = UNDEF_VCVT_IMM6;
6187             return true;
6188           }
6189
6190         if ((arm_decode_field (given, 9, 9) == 0)
6191             && ((imm6 & 0x30) == 0x20))
6192           {
6193             *undefined_code = UNDEF_VCVT_FSI_IMM6;
6194             return true;
6195           }
6196
6197         return false;
6198       }
6199
6200     case MVE_VNEG_FP:
6201     case MVE_VABS_FP:
6202     case MVE_VCVT_BETWEEN_FP_INT:
6203     case MVE_VCVT_FROM_FP_TO_INT:
6204       {
6205         unsigned long size = arm_decode_field (given, 18, 19);
6206         if (size == 0)
6207           {
6208             *undefined_code = UNDEF_SIZE_0;
6209             return true;
6210           }
6211         else if (size == 3)
6212           {
6213             *undefined_code = UNDEF_SIZE_3;
6214             return true;
6215           }
6216         else
6217           return false;
6218       }
6219
6220     case MVE_VMOV_VEC_LANE_TO_GP:
6221       {
6222         unsigned long op1 = arm_decode_field (given, 21, 22);
6223         unsigned long op2 = arm_decode_field (given, 5, 6);
6224         unsigned long u = arm_decode_field (given, 23, 23);
6225
6226         if ((op2 == 0) && (u == 1))
6227           {
6228             if ((op1 == 0) || (op1 == 1))
6229               {
6230                 *undefined_code = UNDEF_BAD_U_OP1_OP2;
6231                 return true;
6232               }
6233             else
6234               return false;
6235           }
6236         else if (op2 == 2)
6237           {
6238             if ((op1 == 0) || (op1 == 1))
6239               {
6240                 *undefined_code = UNDEF_BAD_OP1_OP2;
6241                 return true;
6242               }
6243             else
6244               return false;
6245           }
6246
6247         return false;
6248       }
6249
6250     case MVE_VMOV_GP_TO_VEC_LANE:
6251       if (arm_decode_field (given, 5, 6) == 2)
6252         {
6253           unsigned long op1 = arm_decode_field (given, 21, 22);
6254           if ((op1 == 0) || (op1 == 1))
6255             {
6256               *undefined_code = UNDEF_BAD_OP1_OP2;
6257               return true;
6258             }
6259           else
6260             return false;
6261         }
6262       else
6263         return false;
6264
6265     case MVE_VMOV_VEC_TO_VEC:
6266       if ((arm_decode_field (given, 5, 5) == 1)
6267           || (arm_decode_field (given, 22, 22) == 1))
6268           return true;
6269       return false;
6270
6271     case MVE_VMOV_IMM_TO_VEC:
6272       if (arm_decode_field (given, 5, 5) == 0)
6273       {
6274         unsigned long cmode = arm_decode_field (given, 8, 11);
6275
6276         if (((cmode & 9) == 1) || ((cmode & 5) == 1))
6277           {
6278             *undefined_code = UNDEF_OP_0_BAD_CMODE;
6279             return true;
6280           }
6281         else
6282           return false;
6283       }
6284       else
6285         return false;
6286
6287     case MVE_VSHLL_T2:
6288     case MVE_VMOVN:
6289       if (arm_decode_field (given, 18, 19) == 2)
6290         {
6291           *undefined_code = UNDEF_SIZE_2;
6292           return true;
6293         }
6294       else
6295         return false;
6296
6297     case MVE_VRMLALDAVH:
6298     case MVE_VMLADAV_T1:
6299     case MVE_VMLADAV_T2:
6300     case MVE_VMLALDAV:
6301       if ((arm_decode_field (given, 28, 28) == 1)
6302           && (arm_decode_field (given, 12, 12) == 1))
6303         {
6304           *undefined_code = UNDEF_XCHG_UNS;
6305           return true;
6306         }
6307       else
6308         return false;
6309
6310     case MVE_VQSHRN:
6311     case MVE_VQSHRUN:
6312     case MVE_VSHLL_T1:
6313     case MVE_VSHRN:
6314       {
6315         unsigned long sz = arm_decode_field (given, 19, 20);
6316         if (sz == 1)
6317           return false;
6318         else if ((sz & 2) == 2)
6319           return false;
6320         else
6321           {
6322             *undefined_code = UNDEF_SIZE;
6323             return true;
6324           }
6325       }
6326       break;
6327
6328     case MVE_VQSHL_T2:
6329     case MVE_VQSHLU_T3:
6330     case MVE_VRSHR:
6331     case MVE_VSHL_T1:
6332     case MVE_VSHR:
6333     case MVE_VSLI:
6334     case MVE_VSRI:
6335       {
6336         unsigned long sz = arm_decode_field (given, 19, 21);
6337         if ((sz & 7) == 1)
6338           return false;
6339         else if ((sz & 6) == 2)
6340           return false;
6341         else if ((sz & 4) == 4)
6342           return false;
6343         else
6344           {
6345             *undefined_code = UNDEF_SIZE;
6346             return true;
6347           }
6348       }
6349
6350     case MVE_VQRSHRN:
6351     case MVE_VQRSHRUN:
6352       if (arm_decode_field (given, 19, 20) == 0)
6353         {
6354           *undefined_code = UNDEF_SIZE_0;
6355           return true;
6356         }
6357       else
6358         return false;
6359
6360     case MVE_VABS_VEC:
6361         if (arm_decode_field (given, 18, 19) == 3)
6362         {
6363           *undefined_code = UNDEF_SIZE_3;
6364           return true;
6365         }
6366         else
6367           return false;
6368
6369     case MVE_VQNEG:
6370     case MVE_VQABS:
6371     case MVE_VNEG_VEC:
6372     case MVE_VCLS:
6373     case MVE_VCLZ:
6374       if (arm_decode_field (given, 18, 19) == 3)
6375         {
6376           *undefined_code = UNDEF_SIZE_3;
6377           return true;
6378         }
6379       else
6380         return false;
6381
6382     case MVE_VREV16:
6383       if (arm_decode_field (given, 18, 19) == 0)
6384         return false;
6385       else
6386         {
6387           *undefined_code = UNDEF_SIZE_NOT_0;
6388           return true;
6389         }
6390
6391     case MVE_VREV32:
6392       {
6393         unsigned long size = arm_decode_field (given, 18, 19);
6394         if ((size & 2) == 2)
6395           {
6396             *undefined_code = UNDEF_SIZE_2;
6397             return true;
6398           }
6399         else
6400           return false;
6401       }
6402
6403     case MVE_VREV64:
6404       if (arm_decode_field (given, 18, 19) != 3)
6405         return false;
6406       else
6407         {
6408           *undefined_code = UNDEF_SIZE_3;
6409           return true;
6410         }
6411
6412     default:
6413       return false;
6414     }
6415 }
6416
6417 /* Return FALSE if GIVEN is not an unpredictable encoding for MATCHED_INSN.
6418    Otherwise, return TRUE and set UNPREDICTABLE_CODE to give a reason as to
6419    why this encoding is unpredictable.  */
6420
6421 static bool
6422 is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
6423                       enum mve_unpredictable *unpredictable_code)
6424 {
6425   *unpredictable_code = UNPRED_NONE;
6426
6427   switch (matched_insn)
6428     {
6429     case MVE_VCMP_FP_T2:
6430     case MVE_VPT_FP_T2:
6431       if ((arm_decode_field (given, 12, 12) == 0)
6432           && (arm_decode_field (given, 5, 5) == 1))
6433         {
6434           *unpredictable_code = UNPRED_FCA_0_FCB_1;
6435           return true;
6436         }
6437       else
6438         return false;
6439
6440     case MVE_VPT_VEC_T4:
6441     case MVE_VPT_VEC_T5:
6442     case MVE_VPT_VEC_T6:
6443     case MVE_VCMP_VEC_T4:
6444     case MVE_VCMP_VEC_T5:
6445     case MVE_VCMP_VEC_T6:
6446       if (arm_decode_field (given, 0, 3) == 0xd)
6447         {
6448           *unpredictable_code = UNPRED_R13;
6449           return true;
6450         }
6451       else
6452         return false;
6453
6454     case MVE_VDUP:
6455       {
6456         unsigned long gpr = arm_decode_field (given, 12, 15);
6457         if (gpr == 0xd)
6458           {
6459             *unpredictable_code = UNPRED_R13;
6460             return true;
6461           }
6462         else if (gpr == 0xf)
6463           {
6464             *unpredictable_code = UNPRED_R15;
6465             return true;
6466           }
6467
6468         return false;
6469       }
6470
6471     case MVE_VQADD_T2:
6472     case MVE_VQSUB_T2:
6473     case MVE_VMUL_FP_T2:
6474     case MVE_VMUL_VEC_T2:
6475     case MVE_VMLA:
6476     case MVE_VBRSR:
6477     case MVE_VADD_FP_T2:
6478     case MVE_VSUB_FP_T2:
6479     case MVE_VADD_VEC_T2:
6480     case MVE_VSUB_VEC_T2:
6481     case MVE_VQRSHL_T2:
6482     case MVE_VQSHL_T1:
6483     case MVE_VRSHL_T2:
6484     case MVE_VSHL_T2:
6485     case MVE_VSHLC:
6486     case MVE_VQDMLAH:
6487     case MVE_VQRDMLAH:
6488     case MVE_VQDMLASH:
6489     case MVE_VQRDMLASH:
6490     case MVE_VQDMULH_T3:
6491     case MVE_VQRDMULH_T4:
6492     case MVE_VMLAS:
6493     case MVE_VFMA_FP_SCALAR:
6494     case MVE_VFMAS_FP_SCALAR:
6495     case MVE_VHADD_T2:
6496     case MVE_VHSUB_T2:
6497       {
6498         unsigned long gpr = arm_decode_field (given, 0, 3);
6499         if (gpr == 0xd)
6500           {
6501             *unpredictable_code = UNPRED_R13;
6502             return true;
6503           }
6504         else if (gpr == 0xf)
6505           {
6506             *unpredictable_code = UNPRED_R15;
6507             return true;
6508           }
6509
6510         return false;
6511       }
6512
6513     case MVE_VLD2:
6514     case MVE_VST2:
6515       {
6516         unsigned long rn = arm_decode_field (given, 16, 19);
6517
6518         if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6519           {
6520             *unpredictable_code = UNPRED_R13_AND_WB;
6521             return true;
6522           }
6523
6524         if (rn == 0xf)
6525           {
6526             *unpredictable_code = UNPRED_R15;
6527             return true;
6528           }
6529
6530         if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 6)
6531           {
6532             *unpredictable_code = UNPRED_Q_GT_6;
6533             return true;
6534           }
6535         else
6536           return false;
6537       }
6538
6539     case MVE_VLD4:
6540     case MVE_VST4:
6541       {
6542         unsigned long rn = arm_decode_field (given, 16, 19);
6543
6544         if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6545           {
6546             *unpredictable_code = UNPRED_R13_AND_WB;
6547             return true;
6548           }
6549
6550         if (rn == 0xf)
6551           {
6552             *unpredictable_code = UNPRED_R15;
6553             return true;
6554           }
6555
6556         if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 4)
6557           {
6558             *unpredictable_code = UNPRED_Q_GT_4;
6559             return true;
6560           }
6561         else
6562           return false;
6563       }
6564
6565     case MVE_VLDRB_T5:
6566     case MVE_VLDRH_T6:
6567     case MVE_VLDRW_T7:
6568     case MVE_VSTRB_T5:
6569     case MVE_VSTRH_T6:
6570     case MVE_VSTRW_T7:
6571       {
6572         unsigned long rn = arm_decode_field (given, 16, 19);
6573
6574         if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6575           {
6576             *unpredictable_code = UNPRED_R13_AND_WB;
6577             return true;
6578           }
6579         else if (rn == 0xf)
6580           {
6581             *unpredictable_code = UNPRED_R15;
6582             return true;
6583           }
6584         else
6585           return false;
6586       }
6587
6588     case MVE_VLDRB_GATHER_T1:
6589       if (arm_decode_field (given, 0, 0) == 1)
6590         {
6591           *unpredictable_code = UNPRED_OS;
6592           return true;
6593         }
6594
6595       /*  fall through.  */
6596       /* To handle common code with T2-T4 variants.  */
6597     case MVE_VLDRH_GATHER_T2:
6598     case MVE_VLDRW_GATHER_T3:
6599     case MVE_VLDRD_GATHER_T4:
6600       {
6601         unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6602         unsigned long qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6603
6604         if (qd == qm)
6605           {
6606             *unpredictable_code = UNPRED_Q_REGS_EQUAL;
6607             return true;
6608           }
6609
6610         if (arm_decode_field (given, 16, 19) == 0xf)
6611           {
6612             *unpredictable_code = UNPRED_R15;
6613             return true;
6614           }
6615
6616         return false;
6617       }
6618
6619     case MVE_VLDRW_GATHER_T5:
6620     case MVE_VLDRD_GATHER_T6:
6621       {
6622         unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6623         unsigned long qm = arm_decode_field_multiple (given, 17, 19, 7, 7);
6624
6625         if (qd == qm)
6626           {
6627             *unpredictable_code = UNPRED_Q_REGS_EQUAL;
6628             return true;
6629           }
6630         else
6631           return false;
6632       }
6633
6634     case MVE_VSTRB_SCATTER_T1:
6635       if (arm_decode_field (given, 16, 19) == 0xf)
6636         {
6637           *unpredictable_code = UNPRED_R15;
6638           return true;
6639         }
6640       else if (arm_decode_field (given, 0, 0) == 1)
6641         {
6642           *unpredictable_code = UNPRED_OS;
6643           return true;
6644         }
6645       else
6646         return false;
6647
6648     case MVE_VSTRH_SCATTER_T2:
6649     case MVE_VSTRW_SCATTER_T3:
6650     case MVE_VSTRD_SCATTER_T4:
6651       if (arm_decode_field (given, 16, 19) == 0xf)
6652         {
6653           *unpredictable_code = UNPRED_R15;
6654           return true;
6655         }
6656       else
6657         return false;
6658
6659     case MVE_VMOV2_VEC_LANE_TO_GP:
6660     case MVE_VMOV2_GP_TO_VEC_LANE:
6661     case MVE_VCVT_BETWEEN_FP_INT:
6662     case MVE_VCVT_FROM_FP_TO_INT:
6663       {
6664         unsigned long rt = arm_decode_field (given, 0, 3);
6665         unsigned long rt2 = arm_decode_field (given, 16, 19);
6666
6667         if ((rt == 0xd) || (rt2 == 0xd))
6668           {
6669             *unpredictable_code = UNPRED_R13;
6670             return true;
6671           }
6672         else if ((rt == 0xf) || (rt2 == 0xf))
6673           {
6674             *unpredictable_code = UNPRED_R15;
6675             return true;
6676           }
6677         else if (rt == rt2 && matched_insn != MVE_VMOV2_GP_TO_VEC_LANE)
6678           {
6679             *unpredictable_code = UNPRED_GP_REGS_EQUAL;
6680             return true;
6681           }
6682
6683         return false;
6684       }
6685
6686     case MVE_VMAXV:
6687     case MVE_VMAXAV:
6688     case MVE_VMAXNMV_FP:
6689     case MVE_VMAXNMAV_FP:
6690     case MVE_VMINNMV_FP:
6691     case MVE_VMINNMAV_FP:
6692     case MVE_VMINV:
6693     case MVE_VMINAV:
6694     case MVE_VABAV:
6695     case MVE_VMOV_HFP_TO_GP:
6696     case MVE_VMOV_GP_TO_VEC_LANE:
6697     case MVE_VMOV_VEC_LANE_TO_GP:
6698       {
6699         unsigned long rda = arm_decode_field (given, 12, 15);
6700         if (rda == 0xd)
6701           {
6702             *unpredictable_code = UNPRED_R13;
6703             return true;
6704           }
6705         else if (rda == 0xf)
6706           {
6707             *unpredictable_code = UNPRED_R15;
6708             return true;
6709           }
6710
6711         return false;
6712       }
6713
6714     case MVE_VMULL_INT:
6715       {
6716         unsigned long Qd;
6717         unsigned long Qm;
6718         unsigned long Qn;
6719
6720         if (arm_decode_field (given, 20, 21) == 2)
6721           {
6722             Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6723             Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6724             Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6725
6726             if ((Qd == Qn) || (Qd == Qm))
6727               {
6728                 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2;
6729                 return true;
6730               }
6731             else
6732               return false;
6733           }
6734         else
6735           return false;
6736       }
6737
6738     case MVE_VCMUL_FP:
6739     case MVE_VQDMULL_T1:
6740       {
6741         unsigned long Qd;
6742         unsigned long Qm;
6743         unsigned long Qn;
6744
6745         if (arm_decode_field (given, 28, 28) == 1)
6746           {
6747             Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6748             Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6749             Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6750
6751             if ((Qd == Qn) || (Qd == Qm))
6752               {
6753                 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6754                 return true;
6755               }
6756             else
6757               return false;
6758           }
6759         else
6760           return false;
6761       }
6762
6763     case MVE_VQDMULL_T2:
6764       {
6765         unsigned long gpr = arm_decode_field (given, 0, 3);
6766         if (gpr == 0xd)
6767           {
6768             *unpredictable_code = UNPRED_R13;
6769             return true;
6770           }
6771         else if (gpr == 0xf)
6772           {
6773             *unpredictable_code = UNPRED_R15;
6774             return true;
6775           }
6776
6777         if (arm_decode_field (given, 28, 28) == 1)
6778           {
6779             unsigned long Qd
6780               = arm_decode_field_multiple (given, 13, 15, 22, 22);
6781             unsigned long Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6782
6783             if (Qd == Qn)
6784               {
6785                 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6786                 return true;
6787               }
6788             else
6789               return false;
6790           }
6791
6792         return false;
6793       }
6794
6795     case MVE_VMLSLDAV:
6796     case MVE_VRMLSLDAVH:
6797     case MVE_VMLALDAV:
6798     case MVE_VADDLV:
6799       if (arm_decode_field (given, 20, 22) == 6)
6800         {
6801           *unpredictable_code = UNPRED_R13;
6802           return true;
6803         }
6804       else
6805         return false;
6806
6807     case MVE_VDWDUP:
6808     case MVE_VIWDUP:
6809       if (arm_decode_field (given, 1, 3) == 6)
6810         {
6811           *unpredictable_code = UNPRED_R13;
6812           return true;
6813         }
6814       else
6815         return false;
6816
6817     case MVE_VCADD_VEC:
6818     case MVE_VHCADD:
6819       {
6820         unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6821         unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6822         if ((Qd == Qm) && arm_decode_field (given, 20, 21) == 2)
6823           {
6824             *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2;
6825             return true;
6826           }
6827         else
6828           return false;
6829       }
6830
6831     case MVE_VCADD_FP:
6832       {
6833         unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6834         unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6835         if ((Qd == Qm) && arm_decode_field (given, 20, 20) == 1)
6836           {
6837             *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6838             return true;
6839           }
6840         else
6841           return false;
6842       }
6843
6844     case MVE_VCMLA_FP:
6845       {
6846         unsigned long Qda;
6847         unsigned long Qm;
6848         unsigned long Qn;
6849
6850         if (arm_decode_field (given, 20, 20) == 1)
6851           {
6852             Qda = arm_decode_field_multiple (given, 13, 15, 22, 22);
6853             Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6854             Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6855
6856             if ((Qda == Qn) || (Qda == Qm))
6857               {
6858                 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6859                 return true;
6860               }
6861             else
6862               return false;
6863           }
6864         else
6865           return false;
6866
6867       }
6868
6869     case MVE_VCTP:
6870       if (arm_decode_field (given, 16, 19) == 0xd)
6871         {
6872           *unpredictable_code = UNPRED_R13;
6873           return true;
6874         }
6875       else
6876         return false;
6877
6878     case MVE_VREV64:
6879       {
6880         unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6881         unsigned long qm = arm_decode_field_multiple (given, 1, 3, 6, 6);
6882
6883         if (qd == qm)
6884           {
6885             *unpredictable_code = UNPRED_Q_REGS_EQUAL;
6886             return true;
6887           }
6888         else
6889           return false;
6890       }
6891
6892     case MVE_LSLL:
6893     case MVE_LSLLI:
6894     case MVE_LSRL:
6895     case MVE_ASRL:
6896     case MVE_ASRLI:
6897     case MVE_UQSHLL:
6898     case MVE_UQRSHLL:
6899     case MVE_URSHRL:
6900     case MVE_SRSHRL:
6901     case MVE_SQSHLL:
6902     case MVE_SQRSHRL:
6903       {
6904         unsigned long gpr = arm_decode_field (given, 9, 11);
6905         gpr = ((gpr << 1) | 1);
6906         if (gpr == 0xd)
6907           {
6908             *unpredictable_code = UNPRED_R13;
6909             return true;
6910           }
6911         else if (gpr == 0xf)
6912           {
6913             *unpredictable_code = UNPRED_R15;
6914             return true;
6915           }
6916
6917         return false;
6918       }
6919
6920     default:
6921       return false;
6922     }
6923 }
6924
6925 static void
6926 print_mve_vmov_index (struct disassemble_info *info, unsigned long given)
6927 {
6928   unsigned long op1 = arm_decode_field (given, 21, 22);
6929   unsigned long op2 = arm_decode_field (given, 5, 6);
6930   unsigned long h = arm_decode_field (given, 16, 16);
6931   unsigned long index_operand, esize, targetBeat, idx;
6932   void *stream = info->stream;
6933   fprintf_ftype func = info->fprintf_func;
6934
6935   if ((op1 & 0x2) == 0x2)
6936     {
6937       index_operand = op2;
6938       esize = 8;
6939     }
6940   else if (((op1 & 0x2) == 0x0) && ((op2 & 0x1) == 0x1))
6941     {
6942       index_operand = op2  >> 1;
6943       esize = 16;
6944     }
6945   else if (((op1 & 0x2) == 0) && ((op2 & 0x3) == 0))
6946     {
6947       index_operand = 0;
6948       esize = 32;
6949     }
6950   else
6951     {
6952       func (stream, "<undefined index>");
6953       return;
6954     }
6955
6956   targetBeat =  (op1 & 0x1) | (h << 1);
6957   idx = index_operand + targetBeat * (32/esize);
6958
6959   func (stream, "%lu", idx);
6960 }
6961
6962 /* Print neon and mve 8-bit immediate that can be a 8, 16, 32, or 64-bits
6963    in length and integer of floating-point type.  */
6964 static void
6965 print_simd_imm8 (struct disassemble_info *info, unsigned long given,
6966                  unsigned int ibit_loc, const struct mopcode32 *insn)
6967 {
6968   int bits = 0;
6969   int cmode = (given >> 8) & 0xf;
6970   int op = (given >> 5) & 0x1;
6971   unsigned long value = 0, hival = 0;
6972   unsigned shift;
6973   int size = 0;
6974   int isfloat = 0;
6975   void *stream = info->stream;
6976   fprintf_ftype func = info->fprintf_func;
6977
6978   /* On Neon the 'i' bit is at bit 24, on mve it is
6979      at bit 28.  */
6980   bits |= ((given >> ibit_loc) & 1) << 7;
6981   bits |= ((given >> 16) & 7) << 4;
6982   bits |= ((given >> 0) & 15) << 0;
6983
6984   if (cmode < 8)
6985     {
6986       shift = (cmode >> 1) & 3;
6987       value = (unsigned long) bits << (8 * shift);
6988       size = 32;
6989     }
6990   else if (cmode < 12)
6991     {
6992       shift = (cmode >> 1) & 1;
6993       value = (unsigned long) bits << (8 * shift);
6994       size = 16;
6995     }
6996   else if (cmode < 14)
6997     {
6998       shift = (cmode & 1) + 1;
6999       value = (unsigned long) bits << (8 * shift);
7000       value |= (1ul << (8 * shift)) - 1;
7001       size = 32;
7002     }
7003   else if (cmode == 14)
7004     {
7005       if (op)
7006         {
7007           /* Bit replication into bytes.  */
7008           int ix;
7009           unsigned long mask;
7010
7011           value = 0;
7012           hival = 0;
7013           for (ix = 7; ix >= 0; ix--)
7014             {
7015               mask = ((bits >> ix) & 1) ? 0xff : 0;
7016               if (ix <= 3)
7017                 value = (value << 8) | mask;
7018               else
7019                 hival = (hival << 8) | mask;
7020             }
7021           size = 64;
7022         }
7023       else
7024         {
7025           /* Byte replication.  */
7026           value = (unsigned long) bits;
7027           size = 8;
7028         }
7029     }
7030   else if (!op)
7031     {
7032       /* Floating point encoding.  */
7033       int tmp;
7034
7035       value = (unsigned long)  (bits & 0x7f) << 19;
7036       value |= (unsigned long) (bits & 0x80) << 24;
7037       tmp = bits & 0x40 ? 0x3c : 0x40;
7038       value |= (unsigned long) tmp << 24;
7039       size = 32;
7040       isfloat = 1;
7041     }
7042   else
7043     {
7044       func (stream, "<illegal constant %.8x:%x:%x>",
7045             bits, cmode, op);
7046       size = 32;
7047       return;
7048     }
7049
7050   /* printU determines whether the immediate value should be printed as
7051      unsigned.  */
7052   unsigned printU = 0;
7053   switch (insn->mve_op)
7054     {
7055     default:
7056       break;
7057     /* We want this for instructions that don't have a 'signed' type.  */
7058     case MVE_VBIC_IMM:
7059     case MVE_VORR_IMM:
7060     case MVE_VMVN_IMM:
7061     case MVE_VMOV_IMM_TO_VEC:
7062       printU = 1;
7063       break;
7064     }
7065   switch (size)
7066     {
7067     case 8:
7068       func (stream, "#%ld\t; 0x%.2lx", value, value);
7069       break;
7070
7071     case 16:
7072       func (stream,
7073             printU
7074             ? "#%lu\t; 0x%.4lx"
7075             : "#%ld\t; 0x%.4lx", value, value);
7076       break;
7077
7078     case 32:
7079       if (isfloat)
7080         {
7081           unsigned char valbytes[4];
7082           double fvalue;
7083
7084           /* Do this a byte at a time so we don't have to
7085              worry about the host's endianness.  */
7086           valbytes[0] = value & 0xff;
7087           valbytes[1] = (value >> 8) & 0xff;
7088           valbytes[2] = (value >> 16) & 0xff;
7089           valbytes[3] = (value >> 24) & 0xff;
7090
7091           floatformat_to_double
7092             (& floatformat_ieee_single_little, valbytes,
7093              & fvalue);
7094
7095           func (stream, "#%.7g\t; 0x%.8lx", fvalue,
7096                 value);
7097         }
7098       else
7099         func (stream,
7100               printU
7101               ? "#%lu\t; 0x%.8lx"
7102               : "#%ld\t; 0x%.8lx",
7103               (long) (((value & 0x80000000L) != 0)
7104                       && !printU
7105                       ? value | ~0xffffffffL : value),
7106               value);
7107       break;
7108
7109     case 64:
7110       func (stream, "#0x%.8lx%.8lx", hival, value);
7111       break;
7112
7113     default:
7114       abort ();
7115     }
7116
7117 }
7118
7119 static void
7120 print_mve_undefined (struct disassemble_info *info,
7121                      enum mve_undefined undefined_code)
7122 {
7123   void *stream = info->stream;
7124   fprintf_ftype func = info->fprintf_func;
7125
7126   func (stream, "\t\tundefined instruction: ");
7127
7128   switch (undefined_code)
7129     {
7130     case UNDEF_SIZE:
7131       func (stream, "illegal size");
7132       break;
7133
7134     case UNDEF_SIZE_0:
7135       func (stream, "size equals zero");
7136       break;
7137
7138     case UNDEF_SIZE_2:
7139       func (stream, "size equals two");
7140       break;
7141
7142     case UNDEF_SIZE_3:
7143       func (stream, "size equals three");
7144       break;
7145
7146     case UNDEF_SIZE_LE_1:
7147       func (stream, "size <= 1");
7148       break;
7149
7150     case UNDEF_SIZE_NOT_0:
7151       func (stream, "size not equal to 0");
7152       break;
7153
7154     case UNDEF_SIZE_NOT_2:
7155       func (stream, "size not equal to 2");
7156       break;
7157
7158     case UNDEF_SIZE_NOT_3:
7159       func (stream, "size not equal to 3");
7160       break;
7161
7162     case UNDEF_NOT_UNS_SIZE_0:
7163       func (stream, "not unsigned and size = zero");
7164       break;
7165
7166     case UNDEF_NOT_UNS_SIZE_1:
7167       func (stream, "not unsigned and size = one");
7168       break;
7169
7170     case UNDEF_NOT_UNSIGNED:
7171       func (stream, "not unsigned");
7172       break;
7173
7174     case UNDEF_VCVT_IMM6:
7175       func (stream, "invalid imm6");
7176       break;
7177
7178     case UNDEF_VCVT_FSI_IMM6:
7179       func (stream, "fsi = 0 and invalid imm6");
7180       break;
7181
7182     case UNDEF_BAD_OP1_OP2:
7183       func (stream, "bad size with op2 = 2 and op1 = 0 or 1");
7184       break;
7185
7186     case UNDEF_BAD_U_OP1_OP2:
7187       func (stream, "unsigned with op2 = 0 and op1 = 0 or 1");
7188       break;
7189
7190     case UNDEF_OP_0_BAD_CMODE:
7191       func (stream, "op field equal 0 and bad cmode");
7192       break;
7193
7194     case UNDEF_XCHG_UNS:
7195       func (stream, "exchange and unsigned together");
7196       break;
7197
7198     case UNDEF_NONE:
7199       break;
7200     }
7201
7202 }
7203
7204 static void
7205 print_mve_unpredictable (struct disassemble_info *info,
7206                          enum mve_unpredictable unpredict_code)
7207 {
7208   void *stream = info->stream;
7209   fprintf_ftype func = info->fprintf_func;
7210
7211   func (stream, "%s: ", UNPREDICTABLE_INSTRUCTION);
7212
7213   switch (unpredict_code)
7214     {
7215     case UNPRED_IT_BLOCK:
7216       func (stream, "mve instruction in it block");
7217       break;
7218
7219     case UNPRED_FCA_0_FCB_1:
7220       func (stream, "condition bits, fca = 0 and fcb = 1");
7221       break;
7222
7223     case UNPRED_R13:
7224       func (stream, "use of r13 (sp)");
7225       break;
7226
7227     case UNPRED_R15:
7228       func (stream, "use of r15 (pc)");
7229       break;
7230
7231     case UNPRED_Q_GT_4:
7232       func (stream, "start register block > r4");
7233       break;
7234
7235     case UNPRED_Q_GT_6:
7236       func (stream, "start register block > r6");
7237       break;
7238
7239     case UNPRED_R13_AND_WB:
7240       func (stream, "use of r13 and write back");
7241       break;
7242
7243     case UNPRED_Q_REGS_EQUAL:
7244       func (stream,
7245             "same vector register used for destination and other operand");
7246       break;
7247
7248     case UNPRED_OS:
7249       func (stream, "use of offset scaled");
7250       break;
7251
7252     case UNPRED_GP_REGS_EQUAL:
7253       func (stream, "same general-purpose register used for both operands");
7254       break;
7255
7256     case UNPRED_Q_REGS_EQ_AND_SIZE_1:
7257       func (stream, "use of identical q registers and size = 1");
7258       break;
7259
7260     case UNPRED_Q_REGS_EQ_AND_SIZE_2:
7261       func (stream, "use of identical q registers and size = 1");
7262       break;
7263
7264     case UNPRED_NONE:
7265       break;
7266     }
7267 }
7268
7269 /* Print register block operand for mve vld2/vld4/vst2/vld4.  */
7270
7271 static void
7272 print_mve_register_blocks (struct disassemble_info *info,
7273                            unsigned long given,
7274                            enum mve_instructions matched_insn)
7275 {
7276   void *stream = info->stream;
7277   fprintf_ftype func = info->fprintf_func;
7278
7279   unsigned long q_reg_start = arm_decode_field_multiple (given,
7280                                                          13, 15,
7281                                                          22, 22);
7282   switch (matched_insn)
7283     {
7284     case MVE_VLD2:
7285     case MVE_VST2:
7286       if (q_reg_start <= 6)
7287         func (stream, "{q%ld, q%ld}", q_reg_start, q_reg_start + 1);
7288       else
7289         func (stream, "<illegal reg q%ld>", q_reg_start);
7290       break;
7291
7292     case MVE_VLD4:
7293     case MVE_VST4:
7294       if (q_reg_start <= 4)
7295         func (stream, "{q%ld, q%ld, q%ld, q%ld}", q_reg_start,
7296               q_reg_start + 1, q_reg_start + 2,
7297               q_reg_start + 3);
7298       else
7299         func (stream, "<illegal reg q%ld>", q_reg_start);
7300       break;
7301
7302     default:
7303       break;
7304     }
7305 }
7306
7307 static void
7308 print_mve_rounding_mode (struct disassemble_info *info,
7309                          unsigned long given,
7310                          enum mve_instructions matched_insn)
7311 {
7312   void *stream = info->stream;
7313   fprintf_ftype func = info->fprintf_func;
7314
7315   switch (matched_insn)
7316     {
7317     case MVE_VCVT_FROM_FP_TO_INT:
7318       {
7319         switch (arm_decode_field (given, 8, 9))
7320           {
7321           case 0:
7322             func (stream, "a");
7323             break;
7324
7325           case 1:
7326             func (stream, "n");
7327             break;
7328
7329           case 2:
7330             func (stream, "p");
7331             break;
7332
7333           case 3:
7334             func (stream, "m");
7335             break;
7336
7337           default:
7338             break;
7339           }
7340       }
7341       break;
7342
7343     case MVE_VRINT_FP:
7344       {
7345         switch (arm_decode_field (given, 7, 9))
7346           {
7347           case 0:
7348             func (stream, "n");
7349             break;
7350
7351           case 1:
7352             func (stream, "x");
7353             break;
7354
7355           case 2:
7356             func (stream, "a");
7357             break;
7358
7359           case 3:
7360             func (stream, "z");
7361             break;
7362
7363           case 5:
7364             func (stream, "m");
7365             break;
7366
7367           case 7:
7368             func (stream, "p");
7369
7370           case 4:
7371           case 6:
7372           default:
7373             break;
7374           }
7375       }
7376       break;
7377
7378     default:
7379       break;
7380     }
7381 }
7382
7383 static void
7384 print_mve_vcvt_size (struct disassemble_info *info,
7385                      unsigned long given,
7386                      enum mve_instructions matched_insn)
7387 {
7388   unsigned long mode = 0;
7389   void *stream = info->stream;
7390   fprintf_ftype func = info->fprintf_func;
7391
7392   switch (matched_insn)
7393     {
7394     case MVE_VCVT_FP_FIX_VEC:
7395       {
7396         mode = (((given & 0x200) >> 7)
7397                 | ((given & 0x10000000) >> 27)
7398                 | ((given & 0x100) >> 8));
7399
7400         switch (mode)
7401           {
7402           case 0:
7403             func (stream, "f16.s16");
7404             break;
7405
7406           case 1:
7407             func (stream, "s16.f16");
7408             break;
7409
7410           case 2:
7411             func (stream, "f16.u16");
7412             break;
7413
7414           case 3:
7415             func (stream, "u16.f16");
7416             break;
7417
7418           case 4:
7419             func (stream, "f32.s32");
7420             break;
7421
7422           case 5:
7423             func (stream, "s32.f32");
7424             break;
7425
7426           case 6:
7427             func (stream, "f32.u32");
7428             break;
7429
7430           case 7:
7431             func (stream, "u32.f32");
7432             break;
7433
7434           default:
7435             break;
7436           }
7437         break;
7438       }
7439     case MVE_VCVT_BETWEEN_FP_INT:
7440       {
7441         unsigned long size = arm_decode_field (given, 18, 19);
7442         unsigned long op = arm_decode_field (given, 7, 8);
7443
7444         if (size == 1)
7445           {
7446             switch (op)
7447               {
7448               case 0:
7449                 func (stream, "f16.s16");
7450                 break;
7451
7452               case 1:
7453                 func (stream, "f16.u16");
7454                 break;
7455
7456               case 2:
7457                 func (stream, "s16.f16");
7458                 break;
7459
7460               case 3:
7461                 func (stream, "u16.f16");
7462                 break;
7463
7464               default:
7465                 break;
7466               }
7467           }
7468         else if (size == 2)
7469           {
7470             switch (op)
7471               {
7472               case 0:
7473                 func (stream, "f32.s32");
7474                 break;
7475
7476               case 1:
7477                 func (stream, "f32.u32");
7478                 break;
7479
7480               case 2:
7481                 func (stream, "s32.f32");
7482                 break;
7483
7484               case 3:
7485                 func (stream, "u32.f32");
7486                 break;
7487               }
7488           }
7489       }
7490       break;
7491
7492     case MVE_VCVT_FP_HALF_FP:
7493       {
7494         unsigned long op = arm_decode_field (given, 28, 28);
7495         if (op == 0)
7496           func (stream, "f16.f32");
7497         else if (op == 1)
7498           func (stream, "f32.f16");
7499       }
7500       break;
7501
7502     case MVE_VCVT_FROM_FP_TO_INT:
7503       {
7504         unsigned long size = arm_decode_field_multiple (given, 7, 7, 18, 19);
7505
7506         switch (size)
7507           {
7508           case 2:
7509             func (stream, "s16.f16");
7510             break;
7511
7512           case 3:
7513             func (stream, "u16.f16");
7514             break;
7515
7516           case 4:
7517             func (stream, "s32.f32");
7518             break;
7519
7520           case 5:
7521             func (stream, "u32.f32");
7522             break;
7523
7524           default:
7525             break;
7526           }
7527       }
7528       break;
7529
7530     default:
7531       break;
7532     }
7533 }
7534
7535 static void
7536 print_mve_rotate (struct disassemble_info *info, unsigned long rot,
7537                   unsigned long rot_width)
7538 {
7539   void *stream = info->stream;
7540   fprintf_ftype func = info->fprintf_func;
7541
7542   if (rot_width == 1)
7543     {
7544       switch (rot)
7545         {
7546         case 0:
7547           func (stream, "90");
7548           break;
7549         case 1:
7550           func (stream, "270");
7551           break;
7552         default:
7553           break;
7554         }
7555     }
7556   else if (rot_width == 2)
7557     {
7558       switch (rot)
7559         {
7560         case 0:
7561           func (stream, "0");
7562           break;
7563         case 1:
7564           func (stream, "90");
7565           break;
7566         case 2:
7567           func (stream, "180");
7568           break;
7569         case 3:
7570           func (stream, "270");
7571           break;
7572         default:
7573           break;
7574         }
7575     }
7576 }
7577
7578 static void
7579 print_instruction_predicate (struct disassemble_info *info)
7580 {
7581   void *stream = info->stream;
7582   fprintf_ftype func = info->fprintf_func;
7583
7584   if (vpt_block_state.next_pred_state == PRED_THEN)
7585     func (stream, "t");
7586   else if (vpt_block_state.next_pred_state == PRED_ELSE)
7587     func (stream, "e");
7588 }
7589
7590 static void
7591 print_mve_size (struct disassemble_info *info,
7592                 unsigned long size,
7593                 enum mve_instructions matched_insn)
7594 {
7595   void *stream = info->stream;
7596   fprintf_ftype func = info->fprintf_func;
7597
7598   switch (matched_insn)
7599     {
7600     case MVE_VABAV:
7601     case MVE_VABD_VEC:
7602     case MVE_VABS_FP:
7603     case MVE_VABS_VEC:
7604     case MVE_VADD_VEC_T1:
7605     case MVE_VADD_VEC_T2:
7606     case MVE_VADDV:
7607     case MVE_VBRSR:
7608     case MVE_VCADD_VEC:
7609     case MVE_VCLS:
7610     case MVE_VCLZ:
7611     case MVE_VCMP_VEC_T1:
7612     case MVE_VCMP_VEC_T2:
7613     case MVE_VCMP_VEC_T3:
7614     case MVE_VCMP_VEC_T4:
7615     case MVE_VCMP_VEC_T5:
7616     case MVE_VCMP_VEC_T6:
7617     case MVE_VCTP:
7618     case MVE_VDDUP:
7619     case MVE_VDWDUP:
7620     case MVE_VHADD_T1:
7621     case MVE_VHADD_T2:
7622     case MVE_VHCADD:
7623     case MVE_VHSUB_T1:
7624     case MVE_VHSUB_T2:
7625     case MVE_VIDUP:
7626     case MVE_VIWDUP:
7627     case MVE_VLD2:
7628     case MVE_VLD4:
7629     case MVE_VLDRB_GATHER_T1:
7630     case MVE_VLDRH_GATHER_T2:
7631     case MVE_VLDRW_GATHER_T3:
7632     case MVE_VLDRD_GATHER_T4:
7633     case MVE_VLDRB_T1:
7634     case MVE_VLDRH_T2:
7635     case MVE_VMAX:
7636     case MVE_VMAXA:
7637     case MVE_VMAXV:
7638     case MVE_VMAXAV:
7639     case MVE_VMIN:
7640     case MVE_VMINA:
7641     case MVE_VMINV:
7642     case MVE_VMINAV:
7643     case MVE_VMLA:
7644     case MVE_VMLAS:
7645     case MVE_VMUL_VEC_T1:
7646     case MVE_VMUL_VEC_T2:
7647     case MVE_VMULH:
7648     case MVE_VRMULH:
7649     case MVE_VMULL_INT:
7650     case MVE_VNEG_FP:
7651     case MVE_VNEG_VEC:
7652     case MVE_VPT_VEC_T1:
7653     case MVE_VPT_VEC_T2:
7654     case MVE_VPT_VEC_T3:
7655     case MVE_VPT_VEC_T4:
7656     case MVE_VPT_VEC_T5:
7657     case MVE_VPT_VEC_T6:
7658     case MVE_VQABS:
7659     case MVE_VQADD_T1:
7660     case MVE_VQADD_T2:
7661     case MVE_VQDMLADH:
7662     case MVE_VQRDMLADH:
7663     case MVE_VQDMLAH:
7664     case MVE_VQRDMLAH:
7665     case MVE_VQDMLASH:
7666     case MVE_VQRDMLASH:
7667     case MVE_VQDMLSDH:
7668     case MVE_VQRDMLSDH:
7669     case MVE_VQDMULH_T1:
7670     case MVE_VQRDMULH_T2:
7671     case MVE_VQDMULH_T3:
7672     case MVE_VQRDMULH_T4:
7673     case MVE_VQNEG:
7674     case MVE_VQRSHL_T1:
7675     case MVE_VQRSHL_T2:
7676     case MVE_VQSHL_T1:
7677     case MVE_VQSHL_T4:
7678     case MVE_VQSUB_T1:
7679     case MVE_VQSUB_T2:
7680     case MVE_VREV32:
7681     case MVE_VREV64:
7682     case MVE_VRHADD:
7683     case MVE_VRINT_FP:
7684     case MVE_VRSHL_T1:
7685     case MVE_VRSHL_T2:
7686     case MVE_VSHL_T2:
7687     case MVE_VSHL_T3:
7688     case MVE_VSHLL_T2:
7689     case MVE_VST2:
7690     case MVE_VST4:
7691     case MVE_VSTRB_SCATTER_T1:
7692     case MVE_VSTRH_SCATTER_T2:
7693     case MVE_VSTRW_SCATTER_T3:
7694     case MVE_VSTRB_T1:
7695     case MVE_VSTRH_T2:
7696     case MVE_VSUB_VEC_T1:
7697     case MVE_VSUB_VEC_T2:
7698       if (size <= 3)
7699         func (stream, "%s", mve_vec_sizename[size]);
7700       else
7701         func (stream, "<undef size>");
7702       break;
7703
7704     case MVE_VABD_FP:
7705     case MVE_VADD_FP_T1:
7706     case MVE_VADD_FP_T2:
7707     case MVE_VSUB_FP_T1:
7708     case MVE_VSUB_FP_T2:
7709     case MVE_VCMP_FP_T1:
7710     case MVE_VCMP_FP_T2:
7711     case MVE_VFMA_FP_SCALAR:
7712     case MVE_VFMA_FP:
7713     case MVE_VFMS_FP:
7714     case MVE_VFMAS_FP_SCALAR:
7715     case MVE_VMAXNM_FP:
7716     case MVE_VMAXNMA_FP:
7717     case MVE_VMAXNMV_FP:
7718     case MVE_VMAXNMAV_FP:
7719     case MVE_VMINNM_FP:
7720     case MVE_VMINNMA_FP:
7721     case MVE_VMINNMV_FP:
7722     case MVE_VMINNMAV_FP:
7723     case MVE_VMUL_FP_T1:
7724     case MVE_VMUL_FP_T2:
7725     case MVE_VPT_FP_T1:
7726     case MVE_VPT_FP_T2:
7727       if (size == 0)
7728         func (stream, "32");
7729       else if (size == 1)
7730         func (stream, "16");
7731       break;
7732
7733     case MVE_VCADD_FP:
7734     case MVE_VCMLA_FP:
7735     case MVE_VCMUL_FP:
7736     case MVE_VMLADAV_T1:
7737     case MVE_VMLALDAV:
7738     case MVE_VMLSDAV_T1:
7739     case MVE_VMLSLDAV:
7740     case MVE_VMOVN:
7741     case MVE_VQDMULL_T1:
7742     case MVE_VQDMULL_T2:
7743     case MVE_VQMOVN:
7744     case MVE_VQMOVUN:
7745       if (size == 0)
7746         func (stream, "16");
7747       else if (size == 1)
7748         func (stream, "32");
7749       break;
7750
7751     case MVE_VMOVL:
7752       if (size == 1)
7753         func (stream, "8");
7754       else if (size == 2)
7755         func (stream, "16");
7756       break;
7757
7758     case MVE_VDUP:
7759       switch (size)
7760         {
7761         case 0:
7762           func (stream, "32");
7763           break;
7764         case 1:
7765           func (stream, "16");
7766           break;
7767         case 2:
7768           func (stream, "8");
7769           break;
7770         default:
7771           break;
7772         }
7773       break;
7774
7775     case MVE_VMOV_GP_TO_VEC_LANE:
7776     case MVE_VMOV_VEC_LANE_TO_GP:
7777       switch (size)
7778         {
7779         case 0: case 4:
7780           func (stream, "32");
7781           break;
7782
7783         case 1: case 3:
7784         case 5: case 7:
7785           func (stream, "16");
7786           break;
7787
7788         case 8: case 9: case 10: case 11:
7789         case 12: case 13: case 14: case 15:
7790           func (stream, "8");
7791           break;
7792
7793         default:
7794           break;
7795         }
7796       break;
7797
7798     case MVE_VMOV_IMM_TO_VEC:
7799       switch (size)
7800         {
7801         case 0: case 4: case 8:
7802         case 12: case 24: case 26:
7803           func (stream, "i32");
7804           break;
7805         case 16: case 20:
7806           func (stream, "i16");
7807           break;
7808         case 28:
7809           func (stream, "i8");
7810           break;
7811         case 29:
7812           func (stream, "i64");
7813           break;
7814         case 30:
7815           func (stream, "f32");
7816           break;
7817         default:
7818           break;
7819         }
7820       break;
7821
7822     case MVE_VMULL_POLY:
7823       if (size == 0)
7824         func (stream, "p8");
7825       else if (size == 1)
7826         func (stream, "p16");
7827       break;
7828
7829     case MVE_VMVN_IMM:
7830       switch (size)
7831         {
7832         case 0: case 2: case 4:
7833         case 6: case 12: case 13:
7834           func (stream, "32");
7835           break;
7836
7837         case 8: case 10:
7838           func (stream, "16");
7839           break;
7840
7841         default:
7842           break;
7843         }
7844       break;
7845
7846     case MVE_VBIC_IMM:
7847     case MVE_VORR_IMM:
7848       switch (size)
7849         {
7850         case 1: case 3:
7851         case 5: case 7:
7852           func (stream, "32");
7853           break;
7854
7855         case 9: case 11:
7856           func (stream, "16");
7857           break;
7858
7859         default:
7860           break;
7861         }
7862       break;
7863
7864     case MVE_VQSHRN:
7865     case MVE_VQSHRUN:
7866     case MVE_VQRSHRN:
7867     case MVE_VQRSHRUN:
7868     case MVE_VRSHRN:
7869     case MVE_VSHRN:
7870       {
7871         switch (size)
7872         {
7873         case 1:
7874           func (stream, "16");
7875           break;
7876
7877         case 2: case 3:
7878           func (stream, "32");
7879           break;
7880
7881         default:
7882           break;
7883         }
7884       }
7885       break;
7886
7887     case MVE_VQSHL_T2:
7888     case MVE_VQSHLU_T3:
7889     case MVE_VRSHR:
7890     case MVE_VSHL_T1:
7891     case MVE_VSHLL_T1:
7892     case MVE_VSHR:
7893     case MVE_VSLI:
7894     case MVE_VSRI:
7895       {
7896         switch (size)
7897         {
7898         case 1:
7899           func (stream, "8");
7900           break;
7901
7902         case 2: case 3:
7903           func (stream, "16");
7904           break;
7905
7906         case 4: case 5: case 6: case 7:
7907           func (stream, "32");
7908           break;
7909
7910         default:
7911           break;
7912         }
7913       }
7914       break;
7915
7916     default:
7917       break;
7918     }
7919 }
7920
7921 static void
7922 print_mve_shift_n (struct disassemble_info *info, long given,
7923                    enum mve_instructions matched_insn)
7924 {
7925   void *stream = info->stream;
7926   fprintf_ftype func = info->fprintf_func;
7927
7928   int startAt0
7929     = matched_insn == MVE_VQSHL_T2
7930       || matched_insn == MVE_VQSHLU_T3
7931       || matched_insn == MVE_VSHL_T1
7932       || matched_insn == MVE_VSHLL_T1
7933       || matched_insn == MVE_VSLI;
7934
7935   unsigned imm6 = (given & 0x3f0000) >> 16;
7936
7937   if (matched_insn == MVE_VSHLL_T1)
7938     imm6 &= 0x1f;
7939
7940   unsigned shiftAmount = 0;
7941   if ((imm6 & 0x20) != 0)
7942     shiftAmount = startAt0 ? imm6 - 32 : 64 - imm6;
7943   else if ((imm6 & 0x10) != 0)
7944     shiftAmount = startAt0 ? imm6 - 16 : 32 - imm6;
7945   else if ((imm6 & 0x08) != 0)
7946     shiftAmount = startAt0 ? imm6 - 8 : 16 - imm6;
7947   else
7948     print_mve_undefined (info, UNDEF_SIZE_0);
7949
7950   func (stream, "%u", shiftAmount);
7951 }
7952
7953 static void
7954 print_vec_condition (struct disassemble_info *info, long given,
7955                      enum mve_instructions matched_insn)
7956 {
7957   void *stream = info->stream;
7958   fprintf_ftype func = info->fprintf_func;
7959   long vec_cond = 0;
7960
7961   switch (matched_insn)
7962     {
7963     case MVE_VPT_FP_T1:
7964     case MVE_VCMP_FP_T1:
7965       vec_cond = (((given & 0x1000) >> 10)
7966                   | ((given & 1) << 1)
7967                   | ((given & 0x0080) >> 7));
7968       func (stream, "%s",vec_condnames[vec_cond]);
7969       break;
7970
7971     case MVE_VPT_FP_T2:
7972     case MVE_VCMP_FP_T2:
7973       vec_cond = (((given & 0x1000) >> 10)
7974                   | ((given & 0x0020) >> 4)
7975                   | ((given & 0x0080) >> 7));
7976       func (stream, "%s",vec_condnames[vec_cond]);
7977       break;
7978
7979     case MVE_VPT_VEC_T1:
7980     case MVE_VCMP_VEC_T1:
7981       vec_cond = (given & 0x0080) >> 7;
7982       func (stream, "%s",vec_condnames[vec_cond]);
7983       break;
7984
7985     case MVE_VPT_VEC_T2:
7986     case MVE_VCMP_VEC_T2:
7987       vec_cond = 2 | ((given & 0x0080) >> 7);
7988       func (stream, "%s",vec_condnames[vec_cond]);
7989       break;
7990
7991     case MVE_VPT_VEC_T3:
7992     case MVE_VCMP_VEC_T3:
7993       vec_cond = 4 | ((given & 1) << 1) | ((given & 0x0080) >> 7);
7994       func (stream, "%s",vec_condnames[vec_cond]);
7995       break;
7996
7997     case MVE_VPT_VEC_T4:
7998     case MVE_VCMP_VEC_T4:
7999       vec_cond = (given & 0x0080) >> 7;
8000       func (stream, "%s",vec_condnames[vec_cond]);
8001       break;
8002
8003     case MVE_VPT_VEC_T5:
8004     case MVE_VCMP_VEC_T5:
8005       vec_cond = 2 | ((given & 0x0080) >> 7);
8006       func (stream, "%s",vec_condnames[vec_cond]);
8007       break;
8008
8009     case MVE_VPT_VEC_T6:
8010     case MVE_VCMP_VEC_T6:
8011       vec_cond = 4 | ((given & 0x0020) >> 4) | ((given & 0x0080) >> 7);
8012       func (stream, "%s",vec_condnames[vec_cond]);
8013       break;
8014
8015     case MVE_NONE:
8016     case MVE_VPST:
8017     default:
8018       break;
8019     }
8020 }
8021
8022 #define W_BIT 21
8023 #define I_BIT 22
8024 #define U_BIT 23
8025 #define P_BIT 24
8026
8027 #define WRITEBACK_BIT_SET (given & (1 << W_BIT))
8028 #define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
8029 #define NEGATIVE_BIT_SET  ((given & (1 << U_BIT)) == 0)
8030 #define PRE_BIT_SET       (given & (1 << P_BIT))
8031
8032
8033 /* Print one coprocessor instruction on INFO->STREAM.
8034    Return TRUE if the instuction matched, FALSE if this is not a
8035    recognised coprocessor instruction.  */
8036
8037 static bool
8038 print_insn_coprocessor_1 (const struct sopcode32 *opcodes,
8039                           bfd_vma pc,
8040                           struct disassemble_info *info,
8041                           long given,
8042                           bool thumb)
8043 {
8044   const struct sopcode32 *insn;
8045   void *stream = info->stream;
8046   fprintf_ftype func = info->fprintf_func;
8047   unsigned long mask;
8048   unsigned long value = 0;
8049   int cond;
8050   int cp_num;
8051   struct arm_private_data *private_data = info->private_data;
8052   arm_feature_set allowed_arches = ARM_ARCH_NONE;
8053   arm_feature_set arm_ext_v8_1m_main =
8054     ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
8055
8056   allowed_arches = private_data->features;
8057
8058   for (insn = opcodes; insn->assembler; insn++)
8059     {
8060       unsigned long u_reg = 16;
8061       bool is_unpredictable = false;
8062       signed long value_in_comment = 0;
8063       const char *c;
8064
8065       if (ARM_FEATURE_ZERO (insn->arch))
8066         switch (insn->value)
8067           {
8068           case SENTINEL_IWMMXT_START:
8069             if (info->mach != bfd_mach_arm_XScale
8070                 && info->mach != bfd_mach_arm_iWMMXt
8071                 && info->mach != bfd_mach_arm_iWMMXt2)
8072               do
8073                 insn++;
8074               while ((! ARM_FEATURE_ZERO (insn->arch))
8075                      && insn->value != SENTINEL_IWMMXT_END);
8076             continue;
8077
8078           case SENTINEL_IWMMXT_END:
8079             continue;
8080
8081           case SENTINEL_GENERIC_START:
8082             allowed_arches = private_data->features;
8083             continue;
8084
8085           default:
8086             abort ();
8087           }
8088
8089       mask = insn->mask;
8090       value = insn->value;
8091       cp_num = (given >> 8) & 0xf;
8092
8093       if (thumb)
8094         {
8095           /* The high 4 bits are 0xe for Arm conditional instructions, and
8096              0xe for arm unconditional instructions.  The rest of the
8097              encoding is the same.  */
8098           mask |= 0xf0000000;
8099           value |= 0xe0000000;
8100           if (ifthen_state)
8101             cond = IFTHEN_COND;
8102           else
8103             cond = COND_UNCOND;
8104         }
8105       else
8106         {
8107           /* Only match unconditional instuctions against unconditional
8108              patterns.  */
8109           if ((given & 0xf0000000) == 0xf0000000)
8110             {
8111               mask |= 0xf0000000;
8112               cond = COND_UNCOND;
8113             }
8114           else
8115             {
8116               cond = (given >> 28) & 0xf;
8117               if (cond == 0xe)
8118                 cond = COND_UNCOND;
8119             }
8120         }
8121
8122       if ((insn->isa == T32 && !thumb)
8123           || (insn->isa == ARM && thumb))
8124         continue;
8125
8126       if ((given & mask) != value)
8127         continue;
8128
8129       if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches))
8130         continue;
8131
8132       if (insn->value == 0xfe000010     /* mcr2  */
8133           || insn->value == 0xfe100010  /* mrc2  */
8134           || insn->value == 0xfc100000  /* ldc2  */
8135           || insn->value == 0xfc000000) /* stc2  */
8136         {
8137           if (cp_num == 9 || cp_num == 10 || cp_num == 11)
8138             is_unpredictable = true;
8139
8140           /* Armv8.1-M Mainline FP & MVE instructions.  */
8141           if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
8142               && !ARM_CPU_IS_ANY (allowed_arches)
8143               && (cp_num == 8 || cp_num == 14 || cp_num == 15))
8144             continue;
8145
8146         }
8147       else if (insn->value == 0x0e000000     /* cdp  */
8148                || insn->value == 0xfe000000  /* cdp2  */
8149                || insn->value == 0x0e000010  /* mcr  */
8150                || insn->value == 0x0e100010  /* mrc  */
8151                || insn->value == 0x0c100000  /* ldc  */
8152                || insn->value == 0x0c000000) /* stc  */
8153         {
8154           /* Floating-point instructions.  */
8155           if (cp_num == 9 || cp_num == 10 || cp_num == 11)
8156             continue;
8157
8158           /* Armv8.1-M Mainline FP & MVE instructions.  */
8159           if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
8160               && !ARM_CPU_IS_ANY (allowed_arches)
8161               && (cp_num == 8 || cp_num == 14 || cp_num == 15))
8162             continue;
8163         }
8164       else if ((insn->value == 0xec100f80      /* vldr (system register) */
8165                 || insn->value == 0xec000f80)  /* vstr (system register) */
8166                && arm_decode_field (given, 24, 24) == 0
8167                && arm_decode_field (given, 21, 21) == 0)
8168         /* If the P and W bits are both 0 then these encodings match the MVE
8169            VLDR and VSTR instructions, these are in a different table, so we
8170            don't let it match here.  */
8171         continue;
8172
8173       for (c = insn->assembler; *c; c++)
8174         {
8175           if (*c == '%')
8176             {
8177               const char mod = *++c;
8178               switch (mod)
8179                 {
8180                 case '%':
8181                   func (stream, "%%");
8182                   break;
8183
8184                 case 'A':
8185                 case 'K':
8186                   {
8187                     int rn = (given >> 16) & 0xf;
8188                     bfd_vma offset = given & 0xff;
8189
8190                     if (mod == 'K')
8191                       offset = given & 0x7f;
8192
8193                     func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
8194
8195                     if (PRE_BIT_SET || WRITEBACK_BIT_SET)
8196                       {
8197                         /* Not unindexed.  The offset is scaled.  */
8198                         if (cp_num == 9)
8199                           /* vldr.16/vstr.16 will shift the address
8200                              left by 1 bit only.  */
8201                           offset = offset * 2;
8202                         else
8203                           offset = offset * 4;
8204
8205                         if (NEGATIVE_BIT_SET)
8206                           offset = - offset;
8207                         if (rn != 15)
8208                           value_in_comment = offset;
8209                       }
8210
8211                     if (PRE_BIT_SET)
8212                       {
8213                         if (offset)
8214                           func (stream, ", #%d]%s",
8215                                 (int) offset,
8216                                 WRITEBACK_BIT_SET ? "!" : "");
8217                         else if (NEGATIVE_BIT_SET)
8218                           func (stream, ", #-0]");
8219                         else
8220                           func (stream, "]");
8221                       }
8222                     else
8223                       {
8224                         func (stream, "]");
8225
8226                         if (WRITEBACK_BIT_SET)
8227                           {
8228                             if (offset)
8229                               func (stream, ", #%d", (int) offset);
8230                             else if (NEGATIVE_BIT_SET)
8231                               func (stream, ", #-0");
8232                           }
8233                         else
8234                           {
8235                             func (stream, ", {%s%d}",
8236                                   (NEGATIVE_BIT_SET && !offset) ? "-" : "",
8237                                   (int) offset);
8238                             value_in_comment = offset;
8239                           }
8240                       }
8241                     if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
8242                       {
8243                         func (stream, "\t; ");
8244                         /* For unaligned PCs, apply off-by-alignment
8245                            correction.  */
8246                         info->print_address_func (offset + pc
8247                                                   + info->bytes_per_chunk * 2
8248                                                   - (pc & 3),
8249                                                   info);
8250                       }
8251                   }
8252                   break;
8253
8254                 case 'B':
8255                   {
8256                     int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
8257                     int offset = (given >> 1) & 0x3f;
8258
8259                     if (offset == 1)
8260                       func (stream, "{d%d}", regno);
8261                     else if (regno + offset > 32)
8262                       func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
8263                     else
8264                       func (stream, "{d%d-d%d}", regno, regno + offset - 1);
8265                   }
8266                   break;
8267
8268                 case 'C':
8269                   {
8270                     bool single = ((given >> 8) & 1) == 0;
8271                     char reg_prefix = single ? 's' : 'd';
8272                     int Dreg = (given >> 22) & 0x1;
8273                     int Vdreg = (given >> 12) & 0xf;
8274                     int reg = single ? ((Vdreg << 1) | Dreg)
8275                                      : ((Dreg << 4) | Vdreg);
8276                     int num = (given >> (single ? 0 : 1)) & 0x7f;
8277                     int maxreg = single ? 31 : 15;
8278                     int topreg = reg + num - 1;
8279
8280                     if (!num)
8281                       func (stream, "{VPR}");
8282                     else if (num == 1)
8283                       func (stream, "{%c%d, VPR}", reg_prefix, reg);
8284                     else if (topreg > maxreg)
8285                       func (stream, "{%c%d-<overflow reg d%d, VPR}",
8286                             reg_prefix, reg, single ? topreg >> 1 : topreg);
8287                     else
8288                       func (stream, "{%c%d-%c%d, VPR}", reg_prefix, reg,
8289                             reg_prefix, topreg);
8290                   }
8291                   break;
8292
8293                 case 'u':
8294                   if (cond != COND_UNCOND)
8295                     is_unpredictable = true;
8296
8297                   /* Fall through.  */
8298                 case 'c':
8299                   if (cond != COND_UNCOND && cp_num == 9)
8300                     is_unpredictable = true;
8301
8302                   /* Fall through.  */
8303                 case 'b':
8304                   func (stream, "%s", arm_conditional[cond]);
8305                   break;
8306
8307                 case 'I':
8308                   /* Print a Cirrus/DSP shift immediate.  */
8309                   /* Immediates are 7bit signed ints with bits 0..3 in
8310                      bits 0..3 of opcode and bits 4..6 in bits 5..7
8311                      of opcode.  */
8312                   {
8313                     int imm;
8314
8315                     imm = (given & 0xf) | ((given & 0xe0) >> 1);
8316
8317                     /* Is ``imm'' a negative number?  */
8318                     if (imm & 0x40)
8319                       imm -= 0x80;
8320
8321                     func (stream, "%d", imm);
8322                   }
8323
8324                   break;
8325
8326                 case 'J':
8327                   {
8328                     unsigned long regno
8329                       = arm_decode_field_multiple (given, 13, 15, 22, 22);
8330
8331                     switch (regno)
8332                       {
8333                       case 0x1:
8334                         func (stream, "FPSCR");
8335                         break;
8336                       case 0x2:
8337                         func (stream, "FPSCR_nzcvqc");
8338                         break;
8339                       case 0xc:
8340                         func (stream, "VPR");
8341                         break;
8342                       case 0xd:
8343                         func (stream, "P0");
8344                         break;
8345                       case 0xe:
8346                         func (stream, "FPCXTNS");
8347                         break;
8348                       case 0xf:
8349                         func (stream, "FPCXTS");
8350                         break;
8351                       default:
8352                         func (stream, "<invalid reg %lu>", regno);
8353                         break;
8354                       }
8355                   }
8356                   break;
8357
8358                 case 'F':
8359                   switch (given & 0x00408000)
8360                     {
8361                     case 0:
8362                       func (stream, "4");
8363                       break;
8364                     case 0x8000:
8365                       func (stream, "1");
8366                       break;
8367                     case 0x00400000:
8368                       func (stream, "2");
8369                       break;
8370                     default:
8371                       func (stream, "3");
8372                     }
8373                   break;
8374
8375                 case 'P':
8376                   switch (given & 0x00080080)
8377                     {
8378                     case 0:
8379                       func (stream, "s");
8380                       break;
8381                     case 0x80:
8382                       func (stream, "d");
8383                       break;
8384                     case 0x00080000:
8385                       func (stream, "e");
8386                       break;
8387                     default:
8388                       func (stream, _("<illegal precision>"));
8389                       break;
8390                     }
8391                   break;
8392
8393                 case 'Q':
8394                   switch (given & 0x00408000)
8395                     {
8396                     case 0:
8397                       func (stream, "s");
8398                       break;
8399                     case 0x8000:
8400                       func (stream, "d");
8401                       break;
8402                     case 0x00400000:
8403                       func (stream, "e");
8404                       break;
8405                     default:
8406                       func (stream, "p");
8407                       break;
8408                     }
8409                   break;
8410
8411                 case 'R':
8412                   switch (given & 0x60)
8413                     {
8414                     case 0:
8415                       break;
8416                     case 0x20:
8417                       func (stream, "p");
8418                       break;
8419                     case 0x40:
8420                       func (stream, "m");
8421                       break;
8422                     default:
8423                       func (stream, "z");
8424                       break;
8425                     }
8426                   break;
8427
8428                 case '0': case '1': case '2': case '3': case '4':
8429                 case '5': case '6': case '7': case '8': case '9':
8430                   {
8431                     int width;
8432
8433                     c = arm_decode_bitfield (c, given, &value, &width);
8434
8435                     switch (*c)
8436                       {
8437                       case 'R':
8438                         if (value == 15)
8439                           is_unpredictable = true;
8440                         /* Fall through.  */
8441                       case 'r':
8442                         if (c[1] == 'u')
8443                           {
8444                             /* Eat the 'u' character.  */
8445                             ++ c;
8446
8447                             if (u_reg == value)
8448                               is_unpredictable = true;
8449                             u_reg = value;
8450                           }
8451                         func (stream, "%s", arm_regnames[value]);
8452                         break;
8453                       case 'V':
8454                         if (given & (1 << 6))
8455                           goto Q;
8456                         /* FALLTHROUGH */
8457                       case 'D':
8458                         func (stream, "d%ld", value);
8459                         break;
8460                       case 'Q':
8461                       Q:
8462                         if (value & 1)
8463                           func (stream, "<illegal reg q%ld.5>", value >> 1);
8464                         else
8465                           func (stream, "q%ld", value >> 1);
8466                         break;
8467                       case 'd':
8468                         func (stream, "%ld", value);
8469                         value_in_comment = value;
8470                         break;
8471                       case 'E':
8472                         {
8473                           /* Converts immediate 8 bit back to float value.  */
8474                           unsigned floatVal = (value & 0x80) << 24
8475                             | (value & 0x3F) << 19
8476                             | ((value & 0x40) ? (0xF8 << 22) : (1 << 30));
8477
8478                           /* Quarter float have a maximum value of 31.0.
8479                              Get floating point value multiplied by 1e7.
8480                              The maximum value stays in limit of a 32-bit int.  */
8481                           unsigned decVal =
8482                             (78125 << (((floatVal >> 23) & 0xFF) - 124)) *
8483                             (16 + (value & 0xF));
8484
8485                           if (!(decVal % 1000000))
8486                             func (stream, "%ld\t; 0x%08x %c%u.%01u", value,
8487                                   floatVal, value & 0x80 ? '-' : ' ',
8488                                   decVal / 10000000,
8489                                   decVal % 10000000 / 1000000);
8490                           else if (!(decVal % 10000))
8491                             func (stream, "%ld\t; 0x%08x %c%u.%03u", value,
8492                                   floatVal, value & 0x80 ? '-' : ' ',
8493                                   decVal / 10000000,
8494                                   decVal % 10000000 / 10000);
8495                           else
8496                             func (stream, "%ld\t; 0x%08x %c%u.%07u", value,
8497                                   floatVal, value & 0x80 ? '-' : ' ',
8498                                   decVal / 10000000, decVal % 10000000);
8499                           break;
8500                         }
8501                       case 'k':
8502                         {
8503                           int from = (given & (1 << 7)) ? 32 : 16;
8504                           func (stream, "%ld", from - value);
8505                         }
8506                         break;
8507
8508                       case 'f':
8509                         if (value > 7)
8510                           func (stream, "#%s", arm_fp_const[value & 7]);
8511                         else
8512                           func (stream, "f%ld", value);
8513                         break;
8514
8515                       case 'w':
8516                         if (width == 2)
8517                           func (stream, "%s", iwmmxt_wwnames[value]);
8518                         else
8519                           func (stream, "%s", iwmmxt_wwssnames[value]);
8520                         break;
8521
8522                       case 'g':
8523                         func (stream, "%s", iwmmxt_regnames[value]);
8524                         break;
8525                       case 'G':
8526                         func (stream, "%s", iwmmxt_cregnames[value]);
8527                         break;
8528
8529                       case 'x':
8530                         func (stream, "0x%lx", (value & 0xffffffffUL));
8531                         break;
8532
8533                       case 'c':
8534                         switch (value)
8535                           {
8536                           case 0:
8537                             func (stream, "eq");
8538                             break;
8539
8540                           case 1:
8541                             func (stream, "vs");
8542                             break;
8543
8544                           case 2:
8545                             func (stream, "ge");
8546                             break;
8547
8548                           case 3:
8549                             func (stream, "gt");
8550                             break;
8551
8552                           default:
8553                             func (stream, "??");
8554                             break;
8555                           }
8556                         break;
8557
8558                       case '`':
8559                         c++;
8560                         if (value == 0)
8561                           func (stream, "%c", *c);
8562                         break;
8563                       case '\'':
8564                         c++;
8565                         if (value == ((1ul << width) - 1))
8566                           func (stream, "%c", *c);
8567                         break;
8568                       case '?':
8569                         func (stream, "%c", c[(1 << width) - (int) value]);
8570                         c += 1 << width;
8571                         break;
8572                       default:
8573                         abort ();
8574                       }
8575                   }
8576                   break;
8577
8578                 case 'y':
8579                 case 'z':
8580                   {
8581                     int single = *c++ == 'y';
8582                     int regno;
8583
8584                     switch (*c)
8585                       {
8586                       case '4': /* Sm pair */
8587                       case '0': /* Sm, Dm */
8588                         regno = given & 0x0000000f;
8589                         if (single)
8590                           {
8591                             regno <<= 1;
8592                             regno += (given >> 5) & 1;
8593                           }
8594                         else
8595                           regno += ((given >> 5) & 1) << 4;
8596                         break;
8597
8598                       case '1': /* Sd, Dd */
8599                         regno = (given >> 12) & 0x0000000f;
8600                         if (single)
8601                           {
8602                             regno <<= 1;
8603                             regno += (given >> 22) & 1;
8604                           }
8605                         else
8606                           regno += ((given >> 22) & 1) << 4;
8607                         break;
8608
8609                       case '2': /* Sn, Dn */
8610                         regno = (given >> 16) & 0x0000000f;
8611                         if (single)
8612                           {
8613                             regno <<= 1;
8614                             regno += (given >> 7) & 1;
8615                           }
8616                         else
8617                           regno += ((given >> 7) & 1) << 4;
8618                         break;
8619
8620                       case '3': /* List */
8621                         func (stream, "{");
8622                         regno = (given >> 12) & 0x0000000f;
8623                         if (single)
8624                           {
8625                             regno <<= 1;
8626                             regno += (given >> 22) & 1;
8627                           }
8628                         else
8629                           regno += ((given >> 22) & 1) << 4;
8630                         break;
8631
8632                       default:
8633                         abort ();
8634                       }
8635
8636                     func (stream, "%c%d", single ? 's' : 'd', regno);
8637
8638                     if (*c == '3')
8639                       {
8640                         int count = given & 0xff;
8641
8642                         if (single == 0)
8643                           count >>= 1;
8644
8645                         if (--count)
8646                           {
8647                             func (stream, "-%c%d",
8648                                   single ? 's' : 'd',
8649                                   regno + count);
8650                           }
8651
8652                         func (stream, "}");
8653                       }
8654                     else if (*c == '4')
8655                       func (stream, ", %c%d", single ? 's' : 'd',
8656                             regno + 1);
8657                   }
8658                   break;
8659
8660                 case 'L':
8661                   switch (given & 0x00400100)
8662                     {
8663                     case 0x00000000: func (stream, "b"); break;
8664                     case 0x00400000: func (stream, "h"); break;
8665                     case 0x00000100: func (stream, "w"); break;
8666                     case 0x00400100: func (stream, "d"); break;
8667                     default:
8668                       break;
8669                     }
8670                   break;
8671
8672                 case 'Z':
8673                   {
8674                     /* given (20, 23) | given (0, 3) */
8675                     value = ((given >> 16) & 0xf0) | (given & 0xf);
8676                     func (stream, "%d", (int) value);
8677                   }
8678                   break;
8679
8680                 case 'l':
8681                   /* This is like the 'A' operator, except that if
8682                      the width field "M" is zero, then the offset is
8683                      *not* multiplied by four.  */
8684                   {
8685                     int offset = given & 0xff;
8686                     int multiplier = (given & 0x00000100) ? 4 : 1;
8687
8688                     func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
8689
8690                     if (multiplier > 1)
8691                       {
8692                         value_in_comment = offset * multiplier;
8693                         if (NEGATIVE_BIT_SET)
8694                           value_in_comment = - value_in_comment;
8695                       }
8696
8697                     if (offset)
8698                       {
8699                         if (PRE_BIT_SET)
8700                           func (stream, ", #%s%d]%s",
8701                                 NEGATIVE_BIT_SET ? "-" : "",
8702                                 offset * multiplier,
8703                                 WRITEBACK_BIT_SET ? "!" : "");
8704                         else
8705                           func (stream, "], #%s%d",
8706                                 NEGATIVE_BIT_SET ? "-" : "",
8707                                 offset * multiplier);
8708                       }
8709                     else
8710                       func (stream, "]");
8711                   }
8712                   break;
8713
8714                 case 'r':
8715                   {
8716                     int imm4 = (given >> 4) & 0xf;
8717                     int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
8718                     int ubit = ! NEGATIVE_BIT_SET;
8719                     const char *rm = arm_regnames [given & 0xf];
8720                     const char *rn = arm_regnames [(given >> 16) & 0xf];
8721
8722                     switch (puw_bits)
8723                       {
8724                       case 1:
8725                       case 3:
8726                         func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
8727                         if (imm4)
8728                           func (stream, ", lsl #%d", imm4);
8729                         break;
8730
8731                       case 4:
8732                       case 5:
8733                       case 6:
8734                       case 7:
8735                         func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
8736                         if (imm4 > 0)
8737                           func (stream, ", lsl #%d", imm4);
8738                         func (stream, "]");
8739                         if (puw_bits == 5 || puw_bits == 7)
8740                           func (stream, "!");
8741                         break;
8742
8743                       default:
8744                         func (stream, "INVALID");
8745                       }
8746                   }
8747                   break;
8748
8749                 case 'i':
8750                   {
8751                     long imm5;
8752                     imm5 = ((given & 0x100) >> 4) | (given & 0xf);
8753                     func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
8754                   }
8755                   break;
8756
8757                 default:
8758                   abort ();
8759                 }
8760             }
8761           else
8762             func (stream, "%c", *c);
8763         }
8764
8765       if (value_in_comment > 32 || value_in_comment < -16)
8766         func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
8767
8768       if (is_unpredictable)
8769         func (stream, UNPREDICTABLE_INSTRUCTION);
8770
8771       return true;
8772     }
8773   return false;
8774 }
8775
8776 static bool
8777 print_insn_coprocessor (bfd_vma pc,
8778                         struct disassemble_info *info,
8779                         long given,
8780                         bool thumb)
8781 {
8782   return print_insn_coprocessor_1 (coprocessor_opcodes,
8783                                    pc, info, given, thumb);
8784 }
8785
8786 static bool
8787 print_insn_generic_coprocessor (bfd_vma pc,
8788                                 struct disassemble_info *info,
8789                                 long given,
8790                                 bool thumb)
8791 {
8792   return print_insn_coprocessor_1 (generic_coprocessor_opcodes,
8793                                    pc, info, given, thumb);
8794 }
8795
8796 /* Decodes and prints ARM addressing modes.  Returns the offset
8797    used in the address, if any, if it is worthwhile printing the
8798    offset as a hexadecimal value in a comment at the end of the
8799    line of disassembly.  */
8800
8801 static signed long
8802 print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
8803 {
8804   void *stream = info->stream;
8805   fprintf_ftype func = info->fprintf_func;
8806   bfd_vma offset = 0;
8807
8808   if (((given & 0x000f0000) == 0x000f0000)
8809       && ((given & 0x02000000) == 0))
8810     {
8811       offset = given & 0xfff;
8812
8813       func (stream, "[pc");
8814
8815       if (PRE_BIT_SET)
8816         {
8817           /* Pre-indexed.  Elide offset of positive zero when
8818              non-writeback.  */
8819           if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
8820             func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
8821
8822           if (NEGATIVE_BIT_SET)
8823             offset = -offset;
8824
8825           offset += pc + 8;
8826
8827           /* Cope with the possibility of write-back
8828              being used.  Probably a very dangerous thing
8829              for the programmer to do, but who are we to
8830              argue ?  */
8831           func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : "");
8832         }
8833       else  /* Post indexed.  */
8834         {
8835           func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
8836
8837           /* Ie ignore the offset.  */
8838           offset = pc + 8;
8839         }
8840
8841       func (stream, "\t; ");
8842       info->print_address_func (offset, info);
8843       offset = 0;
8844     }
8845   else
8846     {
8847       func (stream, "[%s",
8848             arm_regnames[(given >> 16) & 0xf]);
8849
8850       if (PRE_BIT_SET)
8851         {
8852           if ((given & 0x02000000) == 0)
8853             {
8854               /* Elide offset of positive zero when non-writeback.  */
8855               offset = given & 0xfff;
8856               if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
8857                 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
8858             }
8859           else
8860             {
8861               func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : "");
8862               arm_decode_shift (given, func, stream, true);
8863             }
8864
8865           func (stream, "]%s",
8866                 WRITEBACK_BIT_SET ? "!" : "");
8867         }
8868       else
8869         {
8870           if ((given & 0x02000000) == 0)
8871             {
8872               /* Always show offset.  */
8873               offset = given & 0xfff;
8874               func (stream, "], #%s%d",
8875                     NEGATIVE_BIT_SET ? "-" : "", (int) offset);
8876             }
8877           else
8878             {
8879               func (stream, "], %s",
8880                     NEGATIVE_BIT_SET ? "-" : "");
8881               arm_decode_shift (given, func, stream, true);
8882             }
8883         }
8884       if (NEGATIVE_BIT_SET)
8885         offset = -offset;
8886     }
8887
8888   return (signed long) offset;
8889 }
8890
8891
8892 /* Print one cde instruction on INFO->STREAM.
8893    Return TRUE if the instuction matched, FALSE if this is not a
8894    recognised cde instruction.  */
8895 static bool
8896 print_insn_cde (struct disassemble_info *info, long given, bool thumb)
8897 {
8898   const struct cdeopcode32 *insn;
8899   void *stream = info->stream;
8900   fprintf_ftype func = info->fprintf_func;
8901
8902   if (thumb)
8903   {
8904     /* Manually extract the coprocessor code from a known point.
8905        This position is the same across all CDE instructions.  */
8906     for (insn = cde_opcodes; insn->assembler; insn++)
8907     {
8908       uint16_t coproc = (given >> insn->coproc_shift) & insn->coproc_mask;
8909       uint16_t coproc_mask = 1 << coproc;
8910       if (! (coproc_mask & cde_coprocs))
8911         continue;
8912
8913       if ((given & insn->mask) == insn->value)
8914       {
8915         bool is_unpredictable = false;
8916         const char *c;
8917
8918         for (c = insn->assembler; *c; c++)
8919         {
8920           if (*c == '%')
8921           {
8922             switch (*++c)
8923             {
8924               case '%':
8925                 func (stream, "%%");
8926                 break;
8927
8928               case '0': case '1': case '2': case '3': case '4':
8929               case '5': case '6': case '7': case '8': case '9':
8930               {
8931                 int width;
8932                 unsigned long value;
8933
8934                 c = arm_decode_bitfield (c, given, &value, &width);
8935
8936                 switch (*c)
8937                 {
8938                   case 'S':
8939                     if (value > 10)
8940                       is_unpredictable = true;
8941                     /* Fall through.  */
8942                   case 'R':
8943                     if (value == 13)
8944                       is_unpredictable = true;
8945                     /* Fall through.  */
8946                   case 'r':
8947                     func (stream, "%s", arm_regnames[value]);
8948                     break;
8949
8950                   case 'n':
8951                     if (value == 15)
8952                       func (stream, "%s", "APSR_nzcv");
8953                     else
8954                       func (stream, "%s", arm_regnames[value]);
8955                     break;
8956
8957                   case 'T':
8958                     func (stream, "%s", arm_regnames[value + 1]);
8959                     break;
8960
8961                   case 'd':
8962                     func (stream, "%ld", value);
8963                     break;
8964
8965                   case 'V':
8966                     if (given & (1 << 6))
8967                       func (stream, "q%ld", value >> 1);
8968                     else if (given & (1 << 24))
8969                       func (stream, "d%ld", value);
8970                     else
8971                       {
8972                         /* Encoding for S register is different than for D and
8973                            Q registers.  S registers are encoded using the top
8974                            single bit in position 22 as the lowest bit of the
8975                            register number, while for Q and D it represents the
8976                            highest bit of the register number.  */
8977                         uint8_t top_bit = (value >> 4) & 1;
8978                         uint8_t tmp = (value << 1) & 0x1e;
8979                         uint8_t res = tmp | top_bit;
8980                         func (stream, "s%u", res);
8981                       }
8982                     break;
8983
8984                 default:
8985                   abort ();
8986                 }
8987               }
8988             break;
8989
8990             case 'p':
8991               {
8992                 uint8_t proc_number = (given >> 8) & 0x7;
8993                 func (stream, "p%u", proc_number);
8994                 break;
8995               }
8996
8997             case 'a':
8998               {
8999                 uint8_t a_offset = 28;
9000                 if (given & (1 << a_offset))
9001                   func (stream, "a");
9002                 break;
9003               }
9004           default:
9005             abort ();
9006           }
9007         }
9008         else
9009           func (stream, "%c", *c);
9010       }
9011
9012       if (is_unpredictable)
9013         func (stream, UNPREDICTABLE_INSTRUCTION);
9014
9015       return true;
9016       }
9017     }
9018     return false;
9019   }
9020   else
9021     return false;
9022 }
9023
9024
9025 /* Print one neon instruction on INFO->STREAM.
9026    Return TRUE if the instuction matched, FALSE if this is not a
9027    recognised neon instruction.  */
9028
9029 static bool
9030 print_insn_neon (struct disassemble_info *info, long given, bool thumb)
9031 {
9032   const struct opcode32 *insn;
9033   void *stream = info->stream;
9034   fprintf_ftype func = info->fprintf_func;
9035
9036   if (thumb)
9037     {
9038       if ((given & 0xef000000) == 0xef000000)
9039         {
9040           /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding.  */
9041           unsigned long bit28 = given & (1 << 28);
9042
9043           given &= 0x00ffffff;
9044           if (bit28)
9045             given |= 0xf3000000;
9046           else
9047             given |= 0xf2000000;
9048         }
9049       else if ((given & 0xff000000) == 0xf9000000)
9050         given ^= 0xf9000000 ^ 0xf4000000;
9051       /* BFloat16 neon instructions without special top byte handling.  */
9052       else if ((given & 0xff000000) == 0xfe000000
9053                || (given & 0xff000000) == 0xfc000000)
9054         ;
9055       /* vdup is also a valid neon instruction.  */
9056       else if ((given & 0xff900f5f) != 0xee800b10)
9057         return false;
9058     }
9059
9060   for (insn = neon_opcodes; insn->assembler; insn++)
9061     {
9062       unsigned long cond_mask = insn->mask;
9063       unsigned long cond_value = insn->value;
9064       int cond;
9065
9066       if (thumb)
9067         {
9068           if ((cond_mask & 0xf0000000) == 0) {
9069               /* For the entries in neon_opcodes, an opcode mask/value with
9070                  the high 4 bits equal to 0 indicates a conditional
9071                  instruction. For thumb however, we need to include those
9072                  bits in the instruction matching.  */
9073               cond_mask |= 0xf0000000;
9074               /* Furthermore, the thumb encoding of a conditional instruction
9075                  will have the high 4 bits equal to 0xe.  */
9076               cond_value |= 0xe0000000;
9077           }
9078           if (ifthen_state)
9079             cond = IFTHEN_COND;
9080           else
9081             cond = COND_UNCOND;
9082         }
9083       else
9084         {
9085           if ((given & 0xf0000000) == 0xf0000000)
9086             {
9087               /* If the instruction is unconditional, update the mask to only
9088                  match against unconditional opcode values.  */
9089               cond_mask |= 0xf0000000;
9090               cond = COND_UNCOND;
9091             }
9092           else
9093             {
9094               cond = (given >> 28) & 0xf;
9095               if (cond == 0xe)
9096                 cond = COND_UNCOND;
9097             }
9098         }
9099
9100       if ((given & cond_mask) == cond_value)
9101         {
9102           signed long value_in_comment = 0;
9103           bool is_unpredictable = false;
9104           const char *c;
9105
9106           for (c = insn->assembler; *c; c++)
9107             {
9108               if (*c == '%')
9109                 {
9110                   switch (*++c)
9111                     {
9112                     case '%':
9113                       func (stream, "%%");
9114                       break;
9115
9116                     case 'u':
9117                       if (thumb && ifthen_state)
9118                         is_unpredictable = true;
9119
9120                       /* Fall through.  */
9121                     case 'c':
9122                       func (stream, "%s", arm_conditional[cond]);
9123                       break;
9124
9125                     case 'A':
9126                       {
9127                         static const unsigned char enc[16] =
9128                         {
9129                           0x4, 0x14, /* st4 0,1 */
9130                           0x4, /* st1 2 */
9131                           0x4, /* st2 3 */
9132                           0x3, /* st3 4 */
9133                           0x13, /* st3 5 */
9134                           0x3, /* st1 6 */
9135                           0x1, /* st1 7 */
9136                           0x2, /* st2 8 */
9137                           0x12, /* st2 9 */
9138                           0x2, /* st1 10 */
9139                           0, 0, 0, 0, 0
9140                         };
9141                         int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
9142                         int rn = ((given >> 16) & 0xf);
9143                         int rm = ((given >> 0) & 0xf);
9144                         int align = ((given >> 4) & 0x3);
9145                         int type = ((given >> 8) & 0xf);
9146                         int n = enc[type] & 0xf;
9147                         int stride = (enc[type] >> 4) + 1;
9148                         int ix;
9149
9150                         func (stream, "{");
9151                         if (stride > 1)
9152                           for (ix = 0; ix != n; ix++)
9153                             func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
9154                         else if (n == 1)
9155                           func (stream, "d%d", rd);
9156                         else
9157                           func (stream, "d%d-d%d", rd, rd + n - 1);
9158                         func (stream, "}, [%s", arm_regnames[rn]);
9159                         if (align)
9160                           func (stream, " :%d", 32 << align);
9161                         func (stream, "]");
9162                         if (rm == 0xd)
9163                           func (stream, "!");
9164                         else if (rm != 0xf)
9165                           func (stream, ", %s", arm_regnames[rm]);
9166                       }
9167                       break;
9168
9169                     case 'B':
9170                       {
9171                         int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
9172                         int rn = ((given >> 16) & 0xf);
9173                         int rm = ((given >> 0) & 0xf);
9174                         int idx_align = ((given >> 4) & 0xf);
9175                         int align = 0;
9176                         int size = ((given >> 10) & 0x3);
9177                         int idx = idx_align >> (size + 1);
9178                         int length = ((given >> 8) & 3) + 1;
9179                         int stride = 1;
9180                         int i;
9181
9182                         if (length > 1 && size > 0)
9183                           stride = (idx_align & (1 << size)) ? 2 : 1;
9184
9185                         switch (length)
9186                           {
9187                           case 1:
9188                             {
9189                               int amask = (1 << size) - 1;
9190                               if ((idx_align & (1 << size)) != 0)
9191                                 return false;
9192                               if (size > 0)
9193                                 {
9194                                   if ((idx_align & amask) == amask)
9195                                     align = 8 << size;
9196                                   else if ((idx_align & amask) != 0)
9197                                     return false;
9198                                 }
9199                               }
9200                             break;
9201
9202                           case 2:
9203                             if (size == 2 && (idx_align & 2) != 0)
9204                               return false;
9205                             align = (idx_align & 1) ? 16 << size : 0;
9206                             break;
9207
9208                           case 3:
9209                             if ((size == 2 && (idx_align & 3) != 0)
9210                                 || (idx_align & 1) != 0)
9211                               return false;
9212                             break;
9213
9214                           case 4:
9215                             if (size == 2)
9216                               {
9217                                 if ((idx_align & 3) == 3)
9218                                   return false;
9219                                 align = (idx_align & 3) * 64;
9220                               }
9221                             else
9222                               align = (idx_align & 1) ? 32 << size : 0;
9223                             break;
9224
9225                           default:
9226                             abort ();
9227                           }
9228
9229                         func (stream, "{");
9230                         for (i = 0; i < length; i++)
9231                           func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
9232                             rd + i * stride, idx);
9233                         func (stream, "}, [%s", arm_regnames[rn]);
9234                         if (align)
9235                           func (stream, " :%d", align);
9236                         func (stream, "]");
9237                         if (rm == 0xd)
9238                           func (stream, "!");
9239                         else if (rm != 0xf)
9240                           func (stream, ", %s", arm_regnames[rm]);
9241                       }
9242                       break;
9243
9244                     case 'C':
9245                       {
9246                         int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
9247                         int rn = ((given >> 16) & 0xf);
9248                         int rm = ((given >> 0) & 0xf);
9249                         int align = ((given >> 4) & 0x1);
9250                         int size = ((given >> 6) & 0x3);
9251                         int type = ((given >> 8) & 0x3);
9252                         int n = type + 1;
9253                         int stride = ((given >> 5) & 0x1);
9254                         int ix;
9255
9256                         if (stride && (n == 1))
9257                           n++;
9258                         else
9259                           stride++;
9260
9261                         func (stream, "{");
9262                         if (stride > 1)
9263                           for (ix = 0; ix != n; ix++)
9264                             func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
9265                         else if (n == 1)
9266                           func (stream, "d%d[]", rd);
9267                         else
9268                           func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
9269                         func (stream, "}, [%s", arm_regnames[rn]);
9270                         if (align)
9271                           {
9272                             align = (8 * (type + 1)) << size;
9273                             if (type == 3)
9274                               align = (size > 1) ? align >> 1 : align;
9275                             if (type == 2 || (type == 0 && !size))
9276                               func (stream, " :<bad align %d>", align);
9277                             else
9278                               func (stream, " :%d", align);
9279                           }
9280                         func (stream, "]");
9281                         if (rm == 0xd)
9282                           func (stream, "!");
9283                         else if (rm != 0xf)
9284                           func (stream, ", %s", arm_regnames[rm]);
9285                       }
9286                       break;
9287
9288                     case 'D':
9289                       {
9290                         int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
9291                         int size = (given >> 20) & 3;
9292                         int reg = raw_reg & ((4 << size) - 1);
9293                         int ix = raw_reg >> size >> 2;
9294
9295                         func (stream, "d%d[%d]", reg, ix);
9296                       }
9297                       break;
9298
9299                     case 'E':
9300                       /* Neon encoded constant for mov, mvn, vorr, vbic.  */
9301                       {
9302                         int bits = 0;
9303                         int cmode = (given >> 8) & 0xf;
9304                         int op = (given >> 5) & 0x1;
9305                         unsigned long value = 0, hival = 0;
9306                         unsigned shift;
9307                         int size = 0;
9308                         int isfloat = 0;
9309
9310                         bits |= ((given >> 24) & 1) << 7;
9311                         bits |= ((given >> 16) & 7) << 4;
9312                         bits |= ((given >> 0) & 15) << 0;
9313
9314                         if (cmode < 8)
9315                           {
9316                             shift = (cmode >> 1) & 3;
9317                             value = (unsigned long) bits << (8 * shift);
9318                             size = 32;
9319                           }
9320                         else if (cmode < 12)
9321                           {
9322                             shift = (cmode >> 1) & 1;
9323                             value = (unsigned long) bits << (8 * shift);
9324                             size = 16;
9325                           }
9326                         else if (cmode < 14)
9327                           {
9328                             shift = (cmode & 1) + 1;
9329                             value = (unsigned long) bits << (8 * shift);
9330                             value |= (1ul << (8 * shift)) - 1;
9331                             size = 32;
9332                           }
9333                         else if (cmode == 14)
9334                           {
9335                             if (op)
9336                               {
9337                                 /* Bit replication into bytes.  */
9338                                 int ix;
9339                                 unsigned long mask;
9340
9341                                 value = 0;
9342                                 hival = 0;
9343                                 for (ix = 7; ix >= 0; ix--)
9344                                   {
9345                                     mask = ((bits >> ix) & 1) ? 0xff : 0;
9346                                     if (ix <= 3)
9347                                       value = (value << 8) | mask;
9348                                     else
9349                                       hival = (hival << 8) | mask;
9350                                   }
9351                                 size = 64;
9352                               }
9353                             else
9354                               {
9355                                 /* Byte replication.  */
9356                                 value = (unsigned long) bits;
9357                                 size = 8;
9358                               }
9359                           }
9360                         else if (!op)
9361                           {
9362                             /* Floating point encoding.  */
9363                             int tmp;
9364
9365                             value = (unsigned long)  (bits & 0x7f) << 19;
9366                             value |= (unsigned long) (bits & 0x80) << 24;
9367                             tmp = bits & 0x40 ? 0x3c : 0x40;
9368                             value |= (unsigned long) tmp << 24;
9369                             size = 32;
9370                             isfloat = 1;
9371                           }
9372                         else
9373                           {
9374                             func (stream, "<illegal constant %.8x:%x:%x>",
9375                                   bits, cmode, op);
9376                             size = 32;
9377                             break;
9378                           }
9379                         switch (size)
9380                           {
9381                           case 8:
9382                             func (stream, "#%ld\t; 0x%.2lx", value, value);
9383                             break;
9384
9385                           case 16:
9386                             func (stream, "#%ld\t; 0x%.4lx", value, value);
9387                             break;
9388
9389                           case 32:
9390                             if (isfloat)
9391                               {
9392                                 unsigned char valbytes[4];
9393                                 double fvalue;
9394
9395                                 /* Do this a byte at a time so we don't have to
9396                                    worry about the host's endianness.  */
9397                                 valbytes[0] = value & 0xff;
9398                                 valbytes[1] = (value >> 8) & 0xff;
9399                                 valbytes[2] = (value >> 16) & 0xff;
9400                                 valbytes[3] = (value >> 24) & 0xff;
9401
9402                                 floatformat_to_double
9403                                   (& floatformat_ieee_single_little, valbytes,
9404                                   & fvalue);
9405
9406                                 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
9407                                       value);
9408                               }
9409                             else
9410                               func (stream, "#%ld\t; 0x%.8lx",
9411                                     (long) (((value & 0x80000000L) != 0)
9412                                             ? value | ~0xffffffffL : value),
9413                                     value);
9414                             break;
9415
9416                           case 64:
9417                             func (stream, "#0x%.8lx%.8lx", hival, value);
9418                             break;
9419
9420                           default:
9421                             abort ();
9422                           }
9423                       }
9424                       break;
9425
9426                     case 'F':
9427                       {
9428                         int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
9429                         int num = (given >> 8) & 0x3;
9430
9431                         if (!num)
9432                           func (stream, "{d%d}", regno);
9433                         else if (num + regno >= 32)
9434                           func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
9435                         else
9436                           func (stream, "{d%d-d%d}", regno, regno + num);
9437                       }
9438                       break;
9439
9440
9441                     case '0': case '1': case '2': case '3': case '4':
9442                     case '5': case '6': case '7': case '8': case '9':
9443                       {
9444                         int width;
9445                         unsigned long value;
9446
9447                         c = arm_decode_bitfield (c, given, &value, &width);
9448
9449                         switch (*c)
9450                           {
9451                           case 'r':
9452                             func (stream, "%s", arm_regnames[value]);
9453                             break;
9454                           case 'd':
9455                             func (stream, "%ld", value);
9456                             value_in_comment = value;
9457                             break;
9458                           case 'e':
9459                             func (stream, "%ld", (1ul << width) - value);
9460                             break;
9461
9462                           case 'S':
9463                           case 'T':
9464                           case 'U':
9465                             /* Various width encodings.  */
9466                             {
9467                               int base = 8 << (*c - 'S'); /* 8,16 or 32 */
9468                               int limit;
9469                               unsigned low, high;
9470
9471                               c++;
9472                               if (*c >= '0' && *c <= '9')
9473                                 limit = *c - '0';
9474                               else if (*c >= 'a' && *c <= 'f')
9475                                 limit = *c - 'a' + 10;
9476                               else
9477                                 abort ();
9478                               low = limit >> 2;
9479                               high = limit & 3;
9480
9481                               if (value < low || value > high)
9482                                 func (stream, "<illegal width %d>", base << value);
9483                               else
9484                                 func (stream, "%d", base << value);
9485                             }
9486                             break;
9487                           case 'R':
9488                             if (given & (1 << 6))
9489                               goto Q;
9490                             /* FALLTHROUGH */
9491                           case 'D':
9492                             func (stream, "d%ld", value);
9493                             break;
9494                           case 'Q':
9495                           Q:
9496                             if (value & 1)
9497                               func (stream, "<illegal reg q%ld.5>", value >> 1);
9498                             else
9499                               func (stream, "q%ld", value >> 1);
9500                             break;
9501
9502                           case '`':
9503                             c++;
9504                             if (value == 0)
9505                               func (stream, "%c", *c);
9506                             break;
9507                           case '\'':
9508                             c++;
9509                             if (value == ((1ul << width) - 1))
9510                               func (stream, "%c", *c);
9511                             break;
9512                           case '?':
9513                             func (stream, "%c", c[(1 << width) - (int) value]);
9514                             c += 1 << width;
9515                             break;
9516                           default:
9517                             abort ();
9518                           }
9519                       }
9520                       break;
9521
9522                     default:
9523                       abort ();
9524                     }
9525                 }
9526               else
9527                 func (stream, "%c", *c);
9528             }
9529
9530           if (value_in_comment > 32 || value_in_comment < -16)
9531             func (stream, "\t; 0x%lx", value_in_comment);
9532
9533           if (is_unpredictable)
9534             func (stream, UNPREDICTABLE_INSTRUCTION);
9535
9536           return true;
9537         }
9538     }
9539   return false;
9540 }
9541
9542 /* Print one mve instruction on INFO->STREAM.
9543    Return TRUE if the instuction matched, FALSE if this is not a
9544    recognised mve instruction.  */
9545
9546 static bool
9547 print_insn_mve (struct disassemble_info *info, long given)
9548 {
9549   const struct mopcode32 *insn;
9550   void *stream = info->stream;
9551   fprintf_ftype func = info->fprintf_func;
9552
9553   for (insn = mve_opcodes; insn->assembler; insn++)
9554     {
9555       if (((given & insn->mask) == insn->value)
9556           && !is_mve_encoding_conflict (given, insn->mve_op))
9557         {
9558           signed long value_in_comment = 0;
9559           bool is_unpredictable = false;
9560           bool is_undefined = false;
9561           const char *c;
9562           enum mve_unpredictable unpredictable_cond = UNPRED_NONE;
9563           enum mve_undefined undefined_cond = UNDEF_NONE;
9564
9565           /* Most vector mve instruction are illegal in a it block.
9566              There are a few exceptions; check for them.  */
9567           if (ifthen_state && !is_mve_okay_in_it (insn->mve_op))
9568             {
9569               is_unpredictable = true;
9570               unpredictable_cond = UNPRED_IT_BLOCK;
9571             }
9572           else if (is_mve_unpredictable (given, insn->mve_op,
9573                                          &unpredictable_cond))
9574             is_unpredictable = true;
9575
9576           if (is_mve_undefined (given, insn->mve_op, &undefined_cond))
9577             is_undefined = true;
9578
9579           /* In "VORR Qd, Qm, Qn", if Qm==Qn, VORR is nothing but VMOV,
9580              i.e "VMOV Qd, Qm".  */
9581           if ((insn->mve_op == MVE_VORR_REG)
9582               && (arm_decode_field (given, 1, 3)
9583                   == arm_decode_field (given, 17, 19)))
9584             continue;
9585
9586           for (c = insn->assembler; *c; c++)
9587             {
9588               if (*c == '%')
9589                 {
9590                   switch (*++c)
9591                     {
9592                     case '%':
9593                       func (stream, "%%");
9594                       break;
9595
9596                     case 'a':
9597                       /* Don't print anything for '+' as it is implied.  */
9598                       if (arm_decode_field (given, 23, 23) == 0)
9599                         func (stream, "-");
9600                       break;
9601
9602                     case 'c':
9603                       if (ifthen_state)
9604                         func (stream, "%s", arm_conditional[IFTHEN_COND]);
9605                       break;
9606
9607                     case 'd':
9608                       print_mve_vld_str_addr (info, given, insn->mve_op);
9609                       break;
9610
9611                     case 'i':
9612                       {
9613                         long mve_mask = mve_extract_pred_mask (given);
9614                         func (stream, "%s", mve_predicatenames[mve_mask]);
9615                       }
9616                       break;
9617
9618                     case 'j':
9619                       {
9620                         unsigned int imm5 = 0;
9621                         imm5 |= arm_decode_field (given, 6, 7);
9622                         imm5 |= (arm_decode_field (given, 12, 14) << 2);
9623                         func (stream, "#%u", (imm5 == 0) ? 32 : imm5);
9624                       }
9625                       break;
9626
9627                     case 'k':
9628                       func (stream, "#%u",
9629                             (arm_decode_field (given, 7, 7) == 0) ? 64 : 48);
9630                       break;
9631
9632                     case 'n':
9633                       print_vec_condition (info, given, insn->mve_op);
9634                       break;
9635
9636                     case 'o':
9637                       if (arm_decode_field (given, 0, 0) == 1)
9638                         {
9639                           unsigned long size
9640                             = arm_decode_field (given, 4, 4)
9641                               | (arm_decode_field (given, 6, 6) << 1);
9642
9643                           func (stream, ", uxtw #%lu", size);
9644                         }
9645                       break;
9646
9647                     case 'm':
9648                       print_mve_rounding_mode (info, given, insn->mve_op);
9649                       break;
9650
9651                     case 's':
9652                       print_mve_vcvt_size (info, given, insn->mve_op);
9653                       break;
9654
9655                     case 'u':
9656                       {
9657                         unsigned long op1 = arm_decode_field (given, 21, 22);
9658
9659                         if ((insn->mve_op == MVE_VMOV_VEC_LANE_TO_GP))
9660                           {
9661                             /* Check for signed.  */
9662                             if (arm_decode_field (given, 23, 23) == 0)
9663                               {
9664                                 /* We don't print 's' for S32.  */
9665                                 if ((arm_decode_field (given, 5, 6) == 0)
9666                                     && ((op1 == 0) || (op1 == 1)))
9667                                   ;
9668                                 else
9669                                   func (stream, "s");
9670                               }
9671                             else
9672                               func (stream, "u");
9673                           }
9674                         else
9675                           {
9676                             if (arm_decode_field (given, 28, 28) == 0)
9677                               func (stream, "s");
9678                             else
9679                               func (stream, "u");
9680                           }
9681                       }
9682                       break;
9683
9684                     case 'v':
9685                       print_instruction_predicate (info);
9686                       break;
9687
9688                     case 'w':
9689                       if (arm_decode_field (given, 21, 21) == 1)
9690                         func (stream, "!");
9691                       break;
9692
9693                     case 'B':
9694                       print_mve_register_blocks (info, given, insn->mve_op);
9695                       break;
9696
9697                     case 'E':
9698                       /* SIMD encoded constant for mov, mvn, vorr, vbic.  */
9699
9700                       print_simd_imm8 (info, given, 28, insn);
9701                       break;
9702
9703                     case 'N':
9704                       print_mve_vmov_index (info, given);
9705                       break;
9706
9707                     case 'T':
9708                       if (arm_decode_field (given, 12, 12) == 0)
9709                         func (stream, "b");
9710                       else
9711                         func (stream, "t");
9712                       break;
9713
9714                     case 'X':
9715                       if (arm_decode_field (given, 12, 12) == 1)
9716                         func (stream, "x");
9717                       break;
9718
9719                     case '0': case '1': case '2': case '3': case '4':
9720                     case '5': case '6': case '7': case '8': case '9':
9721                       {
9722                         int width;
9723                         unsigned long value;
9724
9725                         c = arm_decode_bitfield (c, given, &value, &width);
9726
9727                         switch (*c)
9728                           {
9729                           case 'Z':
9730                             if (value == 13)
9731                               is_unpredictable = true;
9732                             else if (value == 15)
9733                               func (stream, "zr");
9734                             else
9735                               func (stream, "%s", arm_regnames[value]);
9736                             break;
9737
9738                           case 'c':
9739                             func (stream, "%s", arm_conditional[value]);
9740                             break;
9741
9742                           case 'C':
9743                             value ^= 1;
9744                             func (stream, "%s", arm_conditional[value]);
9745                             break;
9746
9747                           case 'S':
9748                             if (value == 13 || value == 15)
9749                               is_unpredictable = true;
9750                             else
9751                               func (stream, "%s", arm_regnames[value]);
9752                             break;
9753
9754                           case 's':
9755                             print_mve_size (info,
9756                                             value,
9757                                             insn->mve_op);
9758                             break;
9759                           case 'I':
9760                             if (value == 1)
9761                               func (stream, "i");
9762                             break;
9763                           case 'A':
9764                             if (value == 1)
9765                               func (stream, "a");
9766                             break;
9767                           case 'h':
9768                             {
9769                               unsigned int odd_reg = (value << 1) | 1;
9770                               func (stream, "%s", arm_regnames[odd_reg]);
9771                             }
9772                             break;
9773                           case 'i':
9774                             {
9775                               unsigned long imm
9776                                 = arm_decode_field (given, 0, 6);
9777                               unsigned long mod_imm = imm;
9778
9779                               switch (insn->mve_op)
9780                                 {
9781                                 case MVE_VLDRW_GATHER_T5:
9782                                 case MVE_VSTRW_SCATTER_T5:
9783                                   mod_imm = mod_imm << 2;
9784                                   break;
9785                                 case MVE_VSTRD_SCATTER_T6:
9786                                 case MVE_VLDRD_GATHER_T6:
9787                                   mod_imm = mod_imm << 3;
9788                                   break;
9789
9790                                 default:
9791                                   break;
9792                                 }
9793
9794                               func (stream, "%lu", mod_imm);
9795                             }
9796                             break;
9797                           case 'k':
9798                             func (stream, "%lu", 64 - value);
9799                             break;
9800                           case 'l':
9801                             {
9802                               unsigned int even_reg = value << 1;
9803                               func (stream, "%s", arm_regnames[even_reg]);
9804                             }
9805                             break;
9806                           case 'u':
9807                             switch (value)
9808                               {
9809                               case 0:
9810                                 func (stream, "1");
9811                                 break;
9812                               case 1:
9813                                 func (stream, "2");
9814                                 break;
9815                               case 2:
9816                                 func (stream, "4");
9817                                 break;
9818                               case 3:
9819                                 func (stream, "8");
9820                                 break;
9821                               default:
9822                                 break;
9823                               }
9824                             break;
9825                           case 'o':
9826                             print_mve_rotate (info, value, width);
9827                             break;
9828                           case 'r':
9829                             func (stream, "%s", arm_regnames[value]);
9830                             break;
9831                           case 'd':
9832                             if (insn->mve_op == MVE_VQSHL_T2
9833                                 || insn->mve_op == MVE_VQSHLU_T3
9834                                 || insn->mve_op == MVE_VRSHR
9835                                 || insn->mve_op == MVE_VRSHRN
9836                                 || insn->mve_op == MVE_VSHL_T1
9837                                 || insn->mve_op == MVE_VSHLL_T1
9838                                 || insn->mve_op == MVE_VSHR
9839                                 || insn->mve_op == MVE_VSHRN
9840                                 || insn->mve_op == MVE_VSLI
9841                                 || insn->mve_op == MVE_VSRI)
9842                               print_mve_shift_n (info, given, insn->mve_op);
9843                             else if (insn->mve_op == MVE_VSHLL_T2)
9844                               {
9845                                 switch (value)
9846                                   {
9847                                   case 0x00:
9848                                     func (stream, "8");
9849                                     break;
9850                                   case 0x01:
9851                                     func (stream, "16");
9852                                     break;
9853                                   case 0x10:
9854                                     print_mve_undefined (info, UNDEF_SIZE_0);
9855                                     break;
9856                                   default:
9857                                     assert (0);
9858                                     break;
9859                                   }
9860                               }
9861                             else
9862                               {
9863                                 if (insn->mve_op == MVE_VSHLC && value == 0)
9864                                   value = 32;
9865                                 func (stream, "%ld", value);
9866                                 value_in_comment = value;
9867                               }
9868                             break;
9869                           case 'F':
9870                             func (stream, "s%ld", value);
9871                             break;
9872                           case 'Q':
9873                             if (value & 0x8)
9874                               func (stream, "<illegal reg q%ld.5>", value);
9875                             else
9876                               func (stream, "q%ld", value);
9877                             break;
9878                           case 'x':
9879                             func (stream, "0x%08lx", value);
9880                             break;
9881                           default:
9882                             abort ();
9883                           }
9884                         break;
9885                       default:
9886                         abort ();
9887                       }
9888                     }
9889                 }
9890               else
9891                 func (stream, "%c", *c);
9892             }
9893
9894           if (value_in_comment > 32 || value_in_comment < -16)
9895             func (stream, "\t; 0x%lx", value_in_comment);
9896
9897           if (is_unpredictable)
9898             print_mve_unpredictable (info, unpredictable_cond);
9899
9900           if (is_undefined)
9901             print_mve_undefined (info, undefined_cond);
9902
9903           if (!vpt_block_state.in_vpt_block
9904               && !ifthen_state
9905               && is_vpt_instruction (given))
9906             mark_inside_vpt_block (given);
9907           else if (vpt_block_state.in_vpt_block)
9908             update_vpt_block_state ();
9909
9910           return true;
9911         }
9912     }
9913   return false;
9914 }
9915
9916
9917 /* Return the name of a v7A special register.  */
9918
9919 static const char *
9920 banked_regname (unsigned reg)
9921 {
9922   switch (reg)
9923     {
9924       case 15: return "CPSR";
9925       case 32: return "R8_usr";
9926       case 33: return "R9_usr";
9927       case 34: return "R10_usr";
9928       case 35: return "R11_usr";
9929       case 36: return "R12_usr";
9930       case 37: return "SP_usr";
9931       case 38: return "LR_usr";
9932       case 40: return "R8_fiq";
9933       case 41: return "R9_fiq";
9934       case 42: return "R10_fiq";
9935       case 43: return "R11_fiq";
9936       case 44: return "R12_fiq";
9937       case 45: return "SP_fiq";
9938       case 46: return "LR_fiq";
9939       case 48: return "LR_irq";
9940       case 49: return "SP_irq";
9941       case 50: return "LR_svc";
9942       case 51: return "SP_svc";
9943       case 52: return "LR_abt";
9944       case 53: return "SP_abt";
9945       case 54: return "LR_und";
9946       case 55: return "SP_und";
9947       case 60: return "LR_mon";
9948       case 61: return "SP_mon";
9949       case 62: return "ELR_hyp";
9950       case 63: return "SP_hyp";
9951       case 79: return "SPSR";
9952       case 110: return "SPSR_fiq";
9953       case 112: return "SPSR_irq";
9954       case 114: return "SPSR_svc";
9955       case 116: return "SPSR_abt";
9956       case 118: return "SPSR_und";
9957       case 124: return "SPSR_mon";
9958       case 126: return "SPSR_hyp";
9959       default: return NULL;
9960     }
9961 }
9962
9963 /* Return the name of the DMB/DSB option.  */
9964 static const char *
9965 data_barrier_option (unsigned option)
9966 {
9967   switch (option & 0xf)
9968     {
9969     case 0xf: return "sy";
9970     case 0xe: return "st";
9971     case 0xd: return "ld";
9972     case 0xb: return "ish";
9973     case 0xa: return "ishst";
9974     case 0x9: return "ishld";
9975     case 0x7: return "un";
9976     case 0x6: return "unst";
9977     case 0x5: return "nshld";
9978     case 0x3: return "osh";
9979     case 0x2: return "oshst";
9980     case 0x1: return "oshld";
9981     default:  return NULL;
9982     }
9983 }
9984
9985 /* Print one ARM instruction from PC on INFO->STREAM.  */
9986
9987 static void
9988 print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
9989 {
9990   const struct opcode32 *insn;
9991   void *stream = info->stream;
9992   fprintf_ftype func = info->fprintf_func;
9993   struct arm_private_data *private_data = info->private_data;
9994
9995   if (print_insn_coprocessor (pc, info, given, false))
9996     return;
9997
9998   if (print_insn_neon (info, given, false))
9999     return;
10000
10001   if (print_insn_generic_coprocessor (pc, info, given, false))
10002     return;
10003
10004   for (insn = arm_opcodes; insn->assembler; insn++)
10005     {
10006       if ((given & insn->mask) != insn->value)
10007         continue;
10008
10009       if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features))
10010         continue;
10011
10012       /* Special case: an instruction with all bits set in the condition field
10013          (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
10014          or by the catchall at the end of the table.  */
10015       if ((given & 0xF0000000) != 0xF0000000
10016           || (insn->mask & 0xF0000000) == 0xF0000000
10017           || (insn->mask == 0 && insn->value == 0))
10018         {
10019           unsigned long u_reg = 16;
10020           unsigned long U_reg = 16;
10021           bool is_unpredictable = false;
10022           signed long value_in_comment = 0;
10023           const char *c;
10024
10025           for (c = insn->assembler; *c; c++)
10026             {
10027               if (*c == '%')
10028                 {
10029                   bool allow_unpredictable = false;
10030
10031                   switch (*++c)
10032                     {
10033                     case '%':
10034                       func (stream, "%%");
10035                       break;
10036
10037                     case 'a':
10038                       value_in_comment = print_arm_address (pc, info, given);
10039                       break;
10040
10041                     case 'P':
10042                       /* Set P address bit and use normal address
10043                          printing routine.  */
10044                       value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
10045                       break;
10046
10047                     case 'S':
10048                       allow_unpredictable = true;
10049                       /* Fall through.  */
10050                     case 's':
10051                       if ((given & 0x004f0000) == 0x004f0000)
10052                         {
10053                           /* PC relative with immediate offset.  */
10054                           bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
10055
10056                           if (PRE_BIT_SET)
10057                             {
10058                               /* Elide positive zero offset.  */
10059                               if (offset || NEGATIVE_BIT_SET)
10060                                 func (stream, "[pc, #%s%d]\t; ",
10061                                       NEGATIVE_BIT_SET ? "-" : "", (int) offset);
10062                               else
10063                                 func (stream, "[pc]\t; ");
10064                               if (NEGATIVE_BIT_SET)
10065                                 offset = -offset;
10066                               info->print_address_func (offset + pc + 8, info);
10067                             }
10068                           else
10069                             {
10070                               /* Always show the offset.  */
10071                               func (stream, "[pc], #%s%d",
10072                                     NEGATIVE_BIT_SET ? "-" : "", (int) offset);
10073                               if (! allow_unpredictable)
10074                                 is_unpredictable = true;
10075                             }
10076                         }
10077                       else
10078                         {
10079                           int offset = ((given & 0xf00) >> 4) | (given & 0xf);
10080
10081                           func (stream, "[%s",
10082                                 arm_regnames[(given >> 16) & 0xf]);
10083
10084                           if (PRE_BIT_SET)
10085                             {
10086                               if (IMMEDIATE_BIT_SET)
10087                                 {
10088                                   /* Elide offset for non-writeback
10089                                      positive zero.  */
10090                                   if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
10091                                       || offset)
10092                                     func (stream, ", #%s%d",
10093                                           NEGATIVE_BIT_SET ? "-" : "", offset);
10094
10095                                   if (NEGATIVE_BIT_SET)
10096                                     offset = -offset;
10097
10098                                   value_in_comment = offset;
10099                                 }
10100                               else
10101                                 {
10102                                   /* Register Offset or Register Pre-Indexed.  */
10103                                   func (stream, ", %s%s",
10104                                         NEGATIVE_BIT_SET ? "-" : "",
10105                                         arm_regnames[given & 0xf]);
10106
10107                                   /* Writing back to the register that is the source/
10108                                      destination of the load/store is unpredictable.  */
10109                                   if (! allow_unpredictable
10110                                       && WRITEBACK_BIT_SET
10111                                       && ((given & 0xf) == ((given >> 12) & 0xf)))
10112                                     is_unpredictable = true;
10113                                 }
10114
10115                               func (stream, "]%s",
10116                                     WRITEBACK_BIT_SET ? "!" : "");
10117                             }
10118                           else
10119                             {
10120                               if (IMMEDIATE_BIT_SET)
10121                                 {
10122                                   /* Immediate Post-indexed.  */
10123                                   /* PR 10924: Offset must be printed, even if it is zero.  */
10124                                   func (stream, "], #%s%d",
10125                                         NEGATIVE_BIT_SET ? "-" : "", offset);
10126                                   if (NEGATIVE_BIT_SET)
10127                                     offset = -offset;
10128                                   value_in_comment = offset;
10129                                 }
10130                               else
10131                                 {
10132                                   /* Register Post-indexed.  */
10133                                   func (stream, "], %s%s",
10134                                         NEGATIVE_BIT_SET ? "-" : "",
10135                                         arm_regnames[given & 0xf]);
10136
10137                                   /* Writing back to the register that is the source/
10138                                      destination of the load/store is unpredictable.  */
10139                                   if (! allow_unpredictable
10140                                       && (given & 0xf) == ((given >> 12) & 0xf))
10141                                     is_unpredictable = true;
10142                                 }
10143
10144                               if (! allow_unpredictable)
10145                                 {
10146                                   /* Writeback is automatically implied by post- addressing.
10147                                      Setting the W bit is unnecessary and ARM specify it as
10148                                      being unpredictable.  */
10149                                   if (WRITEBACK_BIT_SET
10150                                       /* Specifying the PC register as the post-indexed
10151                                          registers is also unpredictable.  */
10152                                       || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
10153                                     is_unpredictable = true;
10154                                 }
10155                             }
10156                         }
10157                       break;
10158
10159                     case 'b':
10160                       {
10161                         bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
10162                         bfd_vma target = disp * 4 + pc + 8;
10163                         info->print_address_func (target, info);
10164
10165                         /* Fill in instruction information.  */
10166                         info->insn_info_valid = 1;
10167                         info->insn_type = dis_branch;
10168                         info->target = target;
10169                       }
10170                       break;
10171
10172                     case 'c':
10173                       if (((given >> 28) & 0xf) != 0xe)
10174                         func (stream, "%s",
10175                               arm_conditional [(given >> 28) & 0xf]);
10176                       break;
10177
10178                     case 'm':
10179                       {
10180                         int started = 0;
10181                         int reg;
10182
10183                         func (stream, "{");
10184                         for (reg = 0; reg < 16; reg++)
10185                           if ((given & (1 << reg)) != 0)
10186                             {
10187                               if (started)
10188                                 func (stream, ", ");
10189                               started = 1;
10190                               func (stream, "%s", arm_regnames[reg]);
10191                             }
10192                         func (stream, "}");
10193                         if (! started)
10194                           is_unpredictable = true;
10195                       }
10196                       break;
10197
10198                     case 'q':
10199                       arm_decode_shift (given, func, stream, false);
10200                       break;
10201
10202                     case 'o':
10203                       if ((given & 0x02000000) != 0)
10204                         {
10205                           unsigned int rotate = (given & 0xf00) >> 7;
10206                           unsigned int immed = (given & 0xff);
10207                           unsigned int a, i;
10208
10209                           a = (immed << ((32 - rotate) & 31)
10210                                | immed >> rotate) & 0xffffffff;
10211                           /* If there is another encoding with smaller rotate,
10212                              the rotate should be specified directly.  */
10213                           for (i = 0; i < 32; i += 2)
10214                             if ((a << i | a >> ((32 - i) & 31)) <= 0xff)
10215                               break;
10216
10217                           if (i != rotate)
10218                             func (stream, "#%d, %d", immed, rotate);
10219                           else
10220                             func (stream, "#%d", a);
10221                           value_in_comment = a;
10222                         }
10223                       else
10224                         arm_decode_shift (given, func, stream, true);
10225                       break;
10226
10227                     case 'p':
10228                       if ((given & 0x0000f000) == 0x0000f000)
10229                         {
10230                           arm_feature_set arm_ext_v6 =
10231                             ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
10232
10233                           /* The p-variants of tst/cmp/cmn/teq are the pre-V6
10234                              mechanism for setting PSR flag bits.  They are
10235                              obsolete in V6 onwards.  */
10236                           if (! ARM_CPU_HAS_FEATURE (private_data->features, \
10237                                                      arm_ext_v6))
10238                             func (stream, "p");
10239                           else
10240                             is_unpredictable = true;
10241                         }
10242                       break;
10243
10244                     case 't':
10245                       if ((given & 0x01200000) == 0x00200000)
10246                         func (stream, "t");
10247                       break;
10248
10249                     case 'A':
10250                       {
10251                         int offset = given & 0xff;
10252
10253                         value_in_comment = offset * 4;
10254                         if (NEGATIVE_BIT_SET)
10255                           value_in_comment = - value_in_comment;
10256
10257                         func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
10258
10259                         if (PRE_BIT_SET)
10260                           {
10261                             if (offset)
10262                               func (stream, ", #%d]%s",
10263                                     (int) value_in_comment,
10264                                     WRITEBACK_BIT_SET ? "!" : "");
10265                             else
10266                               func (stream, "]");
10267                           }
10268                         else
10269                           {
10270                             func (stream, "]");
10271
10272                             if (WRITEBACK_BIT_SET)
10273                               {
10274                                 if (offset)
10275                                   func (stream, ", #%d", (int) value_in_comment);
10276                               }
10277                             else
10278                               {
10279                                 func (stream, ", {%d}", (int) offset);
10280                                 value_in_comment = offset;
10281                               }
10282                           }
10283                       }
10284                       break;
10285
10286                     case 'B':
10287                       /* Print ARM V5 BLX(1) address: pc+25 bits.  */
10288                       {
10289                         bfd_vma address;
10290                         bfd_vma offset = 0;
10291
10292                         if (! NEGATIVE_BIT_SET)
10293                           /* Is signed, hi bits should be ones.  */
10294                           offset = (-1) ^ 0x00ffffff;
10295
10296                         /* Offset is (SignExtend(offset field)<<2).  */
10297                         offset += given & 0x00ffffff;
10298                         offset <<= 2;
10299                         address = offset + pc + 8;
10300
10301                         if (given & 0x01000000)
10302                           /* H bit allows addressing to 2-byte boundaries.  */
10303                           address += 2;
10304
10305                         info->print_address_func (address, info);
10306
10307                         /* Fill in instruction information.  */
10308                         info->insn_info_valid = 1;
10309                         info->insn_type = dis_branch;
10310                         info->target = address;
10311                       }
10312                       break;
10313
10314                     case 'C':
10315                       if ((given & 0x02000200) == 0x200)
10316                         {
10317                           const char * name;
10318                           unsigned sysm = (given & 0x004f0000) >> 16;
10319
10320                           sysm |= (given & 0x300) >> 4;
10321                           name = banked_regname (sysm);
10322
10323                           if (name != NULL)
10324                             func (stream, "%s", name);
10325                           else
10326                             func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
10327                         }
10328                       else
10329                         {
10330                           func (stream, "%cPSR_",
10331                                 (given & 0x00400000) ? 'S' : 'C');
10332                           if (given & 0x80000)
10333                             func (stream, "f");
10334                           if (given & 0x40000)
10335                             func (stream, "s");
10336                           if (given & 0x20000)
10337                             func (stream, "x");
10338                           if (given & 0x10000)
10339                             func (stream, "c");
10340                         }
10341                       break;
10342
10343                     case 'U':
10344                       if ((given & 0xf0) == 0x60)
10345                         {
10346                           switch (given & 0xf)
10347                             {
10348                             case 0xf: func (stream, "sy"); break;
10349                             default:
10350                               func (stream, "#%d", (int) given & 0xf);
10351                               break;
10352                             }
10353                         }
10354                       else
10355                         {
10356                           const char * opt = data_barrier_option (given & 0xf);
10357                           if (opt != NULL)
10358                             func (stream, "%s", opt);
10359                           else
10360                               func (stream, "#%d", (int) given & 0xf);
10361                         }
10362                       break;
10363
10364                     case '0': case '1': case '2': case '3': case '4':
10365                     case '5': case '6': case '7': case '8': case '9':
10366                       {
10367                         int width;
10368                         unsigned long value;
10369
10370                         c = arm_decode_bitfield (c, given, &value, &width);
10371
10372                         switch (*c)
10373                           {
10374                           case 'R':
10375                             if (value == 15)
10376                               is_unpredictable = true;
10377                             /* Fall through.  */
10378                           case 'r':
10379                           case 'T':
10380                             /* We want register + 1 when decoding T.  */
10381                             if (*c == 'T')
10382                               value = (value + 1) & 0xf;
10383
10384                             if (c[1] == 'u')
10385                               {
10386                                 /* Eat the 'u' character.  */
10387                                 ++ c;
10388
10389                                 if (u_reg == value)
10390                                   is_unpredictable = true;
10391                                 u_reg = value;
10392                               }
10393                             if (c[1] == 'U')
10394                               {
10395                                 /* Eat the 'U' character.  */
10396                                 ++ c;
10397
10398                                 if (U_reg == value)
10399                                   is_unpredictable = true;
10400                                 U_reg = value;
10401                               }
10402                             func (stream, "%s", arm_regnames[value]);
10403                             break;
10404                           case 'd':
10405                             func (stream, "%ld", value);
10406                             value_in_comment = value;
10407                             break;
10408                           case 'b':
10409                             func (stream, "%ld", value * 8);
10410                             value_in_comment = value * 8;
10411                             break;
10412                           case 'W':
10413                             func (stream, "%ld", value + 1);
10414                             value_in_comment = value + 1;
10415                             break;
10416                           case 'x':
10417                             func (stream, "0x%08lx", value);
10418
10419                             /* Some SWI instructions have special
10420                                meanings.  */
10421                             if ((given & 0x0fffffff) == 0x0FF00000)
10422                               func (stream, "\t; IMB");
10423                             else if ((given & 0x0fffffff) == 0x0FF00001)
10424                               func (stream, "\t; IMBRange");
10425                             break;
10426                           case 'X':
10427                             func (stream, "%01lx", value & 0xf);
10428                             value_in_comment = value;
10429                             break;
10430                           case '`':
10431                             c++;
10432                             if (value == 0)
10433                               func (stream, "%c", *c);
10434                             break;
10435                           case '\'':
10436                             c++;
10437                             if (value == ((1ul << width) - 1))
10438                               func (stream, "%c", *c);
10439                             break;
10440                           case '?':
10441                             func (stream, "%c", c[(1 << width) - (int) value]);
10442                             c += 1 << width;
10443                             break;
10444                           default:
10445                             abort ();
10446                           }
10447                       }
10448                       break;
10449
10450                     case 'e':
10451                       {
10452                         int imm;
10453
10454                         imm = (given & 0xf) | ((given & 0xfff00) >> 4);
10455                         func (stream, "%d", imm);
10456                         value_in_comment = imm;
10457                       }
10458                       break;
10459
10460                     case 'E':
10461                       /* LSB and WIDTH fields of BFI or BFC.  The machine-
10462                          language instruction encodes LSB and MSB.  */
10463                       {
10464                         long msb = (given & 0x001f0000) >> 16;
10465                         long lsb = (given & 0x00000f80) >> 7;
10466                         long w = msb - lsb + 1;
10467
10468                         if (w > 0)
10469                           func (stream, "#%lu, #%lu", lsb, w);
10470                         else
10471                           func (stream, "(invalid: %lu:%lu)", lsb, msb);
10472                       }
10473                       break;
10474
10475                     case 'R':
10476                       /* Get the PSR/banked register name.  */
10477                       {
10478                         const char * name;
10479                         unsigned sysm = (given & 0x004f0000) >> 16;
10480
10481                         sysm |= (given & 0x300) >> 4;
10482                         name = banked_regname (sysm);
10483
10484                         if (name != NULL)
10485                           func (stream, "%s", name);
10486                         else
10487                           func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
10488                       }
10489                       break;
10490
10491                     case 'V':
10492                       /* 16-bit unsigned immediate from a MOVT or MOVW
10493                          instruction, encoded in bits 0:11 and 15:19.  */
10494                       {
10495                         long hi = (given & 0x000f0000) >> 4;
10496                         long lo = (given & 0x00000fff);
10497                         long imm16 = hi | lo;
10498
10499                         func (stream, "#%lu", imm16);
10500                         value_in_comment = imm16;
10501                       }
10502                       break;
10503
10504                     default:
10505                       abort ();
10506                     }
10507                 }
10508               else
10509                 func (stream, "%c", *c);
10510             }
10511
10512           if (value_in_comment > 32 || value_in_comment < -16)
10513             func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
10514
10515           if (is_unpredictable)
10516             func (stream, UNPREDICTABLE_INSTRUCTION);
10517
10518           return;
10519         }
10520     }
10521   func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
10522   return;
10523 }
10524
10525 /* Print one 16-bit Thumb instruction from PC on INFO->STREAM.  */
10526
10527 static void
10528 print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
10529 {
10530   const struct opcode16 *insn;
10531   void *stream = info->stream;
10532   fprintf_ftype func = info->fprintf_func;
10533
10534   for (insn = thumb_opcodes; insn->assembler; insn++)
10535     if ((given & insn->mask) == insn->value)
10536       {
10537         signed long value_in_comment = 0;
10538         const char *c = insn->assembler;
10539
10540         for (; *c; c++)
10541           {
10542             int domaskpc = 0;
10543             int domasklr = 0;
10544
10545             if (*c != '%')
10546               {
10547                 func (stream, "%c", *c);
10548                 continue;
10549               }
10550
10551             switch (*++c)
10552               {
10553               case '%':
10554                 func (stream, "%%");
10555                 break;
10556
10557               case 'c':
10558                 if (ifthen_state)
10559                   func (stream, "%s", arm_conditional[IFTHEN_COND]);
10560                 break;
10561
10562               case 'C':
10563                 if (ifthen_state)
10564                   func (stream, "%s", arm_conditional[IFTHEN_COND]);
10565                 else
10566                   func (stream, "s");
10567                 break;
10568
10569               case 'I':
10570                 {
10571                   unsigned int tmp;
10572
10573                   ifthen_next_state = given & 0xff;
10574                   for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
10575                     func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
10576                   func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
10577                 }
10578                 break;
10579
10580               case 'x':
10581                 if (ifthen_next_state)
10582                   func (stream, "\t; unpredictable branch in IT block\n");
10583                 break;
10584
10585               case 'X':
10586                 if (ifthen_state)
10587                   func (stream, "\t; unpredictable <IT:%s>",
10588                         arm_conditional[IFTHEN_COND]);
10589                 break;
10590
10591               case 'S':
10592                 {
10593                   long reg;
10594
10595                   reg = (given >> 3) & 0x7;
10596                   if (given & (1 << 6))
10597                     reg += 8;
10598
10599                   func (stream, "%s", arm_regnames[reg]);
10600                 }
10601                 break;
10602
10603               case 'D':
10604                 {
10605                   long reg;
10606
10607                   reg = given & 0x7;
10608                   if (given & (1 << 7))
10609                     reg += 8;
10610
10611                   func (stream, "%s", arm_regnames[reg]);
10612                 }
10613                 break;
10614
10615               case 'N':
10616                 if (given & (1 << 8))
10617                   domasklr = 1;
10618                 /* Fall through.  */
10619               case 'O':
10620                 if (*c == 'O' && (given & (1 << 8)))
10621                   domaskpc = 1;
10622                 /* Fall through.  */
10623               case 'M':
10624                 {
10625                   int started = 0;
10626                   int reg;
10627
10628                   func (stream, "{");
10629
10630                   /* It would be nice if we could spot
10631                      ranges, and generate the rS-rE format: */
10632                   for (reg = 0; (reg < 8); reg++)
10633                     if ((given & (1 << reg)) != 0)
10634                       {
10635                         if (started)
10636                           func (stream, ", ");
10637                         started = 1;
10638                         func (stream, "%s", arm_regnames[reg]);
10639                       }
10640
10641                   if (domasklr)
10642                     {
10643                       if (started)
10644                         func (stream, ", ");
10645                       started = 1;
10646                       func (stream, "%s", arm_regnames[14] /* "lr" */);
10647                     }
10648
10649                   if (domaskpc)
10650                     {
10651                       if (started)
10652                         func (stream, ", ");
10653                       func (stream, "%s", arm_regnames[15] /* "pc" */);
10654                     }
10655
10656                   func (stream, "}");
10657                 }
10658                 break;
10659
10660               case 'W':
10661                 /* Print writeback indicator for a LDMIA.  We are doing a
10662                    writeback if the base register is not in the register
10663                    mask.  */
10664                 if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
10665                   func (stream, "!");
10666                 break;
10667
10668               case 'b':
10669                 /* Print ARM V6T2 CZB address: pc+4+6 bits.  */
10670                 {
10671                   bfd_vma address = (pc + 4
10672                                      + ((given & 0x00f8) >> 2)
10673                                      + ((given & 0x0200) >> 3));
10674                   info->print_address_func (address, info);
10675
10676                   /* Fill in instruction information.  */
10677                   info->insn_info_valid = 1;
10678                   info->insn_type = dis_branch;
10679                   info->target = address;
10680                 }
10681                 break;
10682
10683               case 's':
10684                 /* Right shift immediate -- bits 6..10; 1-31 print
10685                    as themselves, 0 prints as 32.  */
10686                 {
10687                   long imm = (given & 0x07c0) >> 6;
10688                   if (imm == 0)
10689                     imm = 32;
10690                   func (stream, "#%ld", imm);
10691                 }
10692                 break;
10693
10694               case '0': case '1': case '2': case '3': case '4':
10695               case '5': case '6': case '7': case '8': case '9':
10696                 {
10697                   int bitstart = *c++ - '0';
10698                   int bitend = 0;
10699
10700                   while (*c >= '0' && *c <= '9')
10701                     bitstart = (bitstart * 10) + *c++ - '0';
10702
10703                   switch (*c)
10704                     {
10705                     case '-':
10706                       {
10707                         bfd_vma reg;
10708
10709                         c++;
10710                         while (*c >= '0' && *c <= '9')
10711                           bitend = (bitend * 10) + *c++ - '0';
10712                         if (!bitend)
10713                           abort ();
10714                         reg = given >> bitstart;
10715                         reg &= (2 << (bitend - bitstart)) - 1;
10716
10717                         switch (*c)
10718                           {
10719                           case 'r':
10720                             func (stream, "%s", arm_regnames[reg]);
10721                             break;
10722
10723                           case 'd':
10724                             func (stream, "%ld", (long) reg);
10725                             value_in_comment = reg;
10726                             break;
10727
10728                           case 'H':
10729                             func (stream, "%ld", (long) (reg << 1));
10730                             value_in_comment = reg << 1;
10731                             break;
10732
10733                           case 'W':
10734                             func (stream, "%ld", (long) (reg << 2));
10735                             value_in_comment = reg << 2;
10736                             break;
10737
10738                           case 'a':
10739                             /* PC-relative address -- the bottom two
10740                                bits of the address are dropped
10741                                before the calculation.  */
10742                             info->print_address_func
10743                               (((pc + 4) & ~3) + (reg << 2), info);
10744                             value_in_comment = 0;
10745                             break;
10746
10747                           case 'x':
10748                             func (stream, "0x%04lx", (long) reg);
10749                             break;
10750
10751                           case 'B':
10752                             reg = ((reg ^ (1 << bitend)) - (1 << bitend));
10753                             bfd_vma target = reg * 2 + pc + 4;
10754                             info->print_address_func (target, info);
10755                             value_in_comment = 0;
10756
10757                             /* Fill in instruction information.  */
10758                             info->insn_info_valid = 1;
10759                             info->insn_type = dis_branch;
10760                             info->target = target;
10761                             break;
10762
10763                           case 'c':
10764                             func (stream, "%s", arm_conditional [reg]);
10765                             break;
10766
10767                           default:
10768                             abort ();
10769                           }
10770                       }
10771                       break;
10772
10773                     case '\'':
10774                       c++;
10775                       if ((given & (1 << bitstart)) != 0)
10776                         func (stream, "%c", *c);
10777                       break;
10778
10779                     case '?':
10780                       ++c;
10781                       if ((given & (1 << bitstart)) != 0)
10782                         func (stream, "%c", *c++);
10783                       else
10784                         func (stream, "%c", *++c);
10785                       break;
10786
10787                     default:
10788                       abort ();
10789                     }
10790                 }
10791                 break;
10792
10793               default:
10794                 abort ();
10795               }
10796           }
10797
10798         if (value_in_comment > 32 || value_in_comment < -16)
10799           func (stream, "\t; 0x%lx", value_in_comment);
10800         return;
10801       }
10802
10803   /* No match.  */
10804   func (stream, UNKNOWN_INSTRUCTION_16BIT, (unsigned)given);
10805   return;
10806 }
10807
10808 /* Return the name of an V7M special register.  */
10809
10810 static const char *
10811 psr_name (int regno)
10812 {
10813   switch (regno)
10814     {
10815     case 0x0: return "APSR";
10816     case 0x1: return "IAPSR";
10817     case 0x2: return "EAPSR";
10818     case 0x3: return "PSR";
10819     case 0x5: return "IPSR";
10820     case 0x6: return "EPSR";
10821     case 0x7: return "IEPSR";
10822     case 0x8: return "MSP";
10823     case 0x9: return "PSP";
10824     case 0xa: return "MSPLIM";
10825     case 0xb: return "PSPLIM";
10826     case 0x10: return "PRIMASK";
10827     case 0x11: return "BASEPRI";
10828     case 0x12: return "BASEPRI_MAX";
10829     case 0x13: return "FAULTMASK";
10830     case 0x14: return "CONTROL";
10831     case 0x88: return "MSP_NS";
10832     case 0x89: return "PSP_NS";
10833     case 0x8a: return "MSPLIM_NS";
10834     case 0x8b: return "PSPLIM_NS";
10835     case 0x90: return "PRIMASK_NS";
10836     case 0x91: return "BASEPRI_NS";
10837     case 0x93: return "FAULTMASK_NS";
10838     case 0x94: return "CONTROL_NS";
10839     case 0x98: return "SP_NS";
10840     default: return "<unknown>";
10841     }
10842 }
10843
10844 /* Print one 32-bit Thumb instruction from PC on INFO->STREAM.  */
10845
10846 static void
10847 print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
10848 {
10849   const struct opcode32 *insn;
10850   void *stream = info->stream;
10851   fprintf_ftype func = info->fprintf_func;
10852   bool is_mve = is_mve_architecture (info);
10853
10854   if (print_insn_coprocessor (pc, info, given, true))
10855     return;
10856
10857   if (!is_mve && print_insn_neon (info, given, true))
10858     return;
10859
10860   if (is_mve && print_insn_mve (info, given))
10861     return;
10862
10863   if (print_insn_cde (info, given, true))
10864     return;
10865
10866   if (print_insn_generic_coprocessor (pc, info, given, true))
10867     return;
10868
10869   for (insn = thumb32_opcodes; insn->assembler; insn++)
10870     if ((given & insn->mask) == insn->value)
10871       {
10872         bool is_clrm = false;
10873         bool is_unpredictable = false;
10874         signed long value_in_comment = 0;
10875         const char *c = insn->assembler;
10876
10877         for (; *c; c++)
10878           {
10879             if (*c != '%')
10880               {
10881                 func (stream, "%c", *c);
10882                 continue;
10883               }
10884
10885             switch (*++c)
10886               {
10887               case '%':
10888                 func (stream, "%%");
10889                 break;
10890
10891               case 'c':
10892                 if (ifthen_state)
10893                   func (stream, "%s", arm_conditional[IFTHEN_COND]);
10894                 break;
10895
10896               case 'x':
10897                 if (ifthen_next_state)
10898                   func (stream, "\t; unpredictable branch in IT block\n");
10899                 break;
10900
10901               case 'X':
10902                 if (ifthen_state)
10903                   func (stream, "\t; unpredictable <IT:%s>",
10904                         arm_conditional[IFTHEN_COND]);
10905                 break;
10906
10907               case 'I':
10908                 {
10909                   unsigned int imm12 = 0;
10910
10911                   imm12 |= (given & 0x000000ffu);
10912                   imm12 |= (given & 0x00007000u) >> 4;
10913                   imm12 |= (given & 0x04000000u) >> 15;
10914                   func (stream, "#%u", imm12);
10915                   value_in_comment = imm12;
10916                 }
10917                 break;
10918
10919               case 'M':
10920                 {
10921                   unsigned int bits = 0, imm, imm8, mod;
10922
10923                   bits |= (given & 0x000000ffu);
10924                   bits |= (given & 0x00007000u) >> 4;
10925                   bits |= (given & 0x04000000u) >> 15;
10926                   imm8 = (bits & 0x0ff);
10927                   mod = (bits & 0xf00) >> 8;
10928                   switch (mod)
10929                     {
10930                     case 0: imm = imm8; break;
10931                     case 1: imm = ((imm8 << 16) | imm8); break;
10932                     case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
10933                     case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
10934                     default:
10935                       mod  = (bits & 0xf80) >> 7;
10936                       imm8 = (bits & 0x07f) | 0x80;
10937                       imm  = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
10938                     }
10939                   func (stream, "#%u", imm);
10940                   value_in_comment = imm;
10941                 }
10942                 break;
10943
10944               case 'J':
10945                 {
10946                   unsigned int imm = 0;
10947
10948                   imm |= (given & 0x000000ffu);
10949                   imm |= (given & 0x00007000u) >> 4;
10950                   imm |= (given & 0x04000000u) >> 15;
10951                   imm |= (given & 0x000f0000u) >> 4;
10952                   func (stream, "#%u", imm);
10953                   value_in_comment = imm;
10954                 }
10955                 break;
10956
10957               case 'K':
10958                 {
10959                   unsigned int imm = 0;
10960
10961                   imm |= (given & 0x000f0000u) >> 16;
10962                   imm |= (given & 0x00000ff0u) >> 0;
10963                   imm |= (given & 0x0000000fu) << 12;
10964                   func (stream, "#%u", imm);
10965                   value_in_comment = imm;
10966                 }
10967                 break;
10968
10969               case 'H':
10970                 {
10971                   unsigned int imm = 0;
10972
10973                   imm |= (given & 0x000f0000u) >> 4;
10974                   imm |= (given & 0x00000fffu) >> 0;
10975                   func (stream, "#%u", imm);
10976                   value_in_comment = imm;
10977                 }
10978                 break;
10979
10980               case 'V':
10981                 {
10982                   unsigned int imm = 0;
10983
10984                   imm |= (given & 0x00000fffu);
10985                   imm |= (given & 0x000f0000u) >> 4;
10986                   func (stream, "#%u", imm);
10987                   value_in_comment = imm;
10988                 }
10989                 break;
10990
10991               case 'S':
10992                 {
10993                   unsigned int reg = (given & 0x0000000fu);
10994                   unsigned int stp = (given & 0x00000030u) >> 4;
10995                   unsigned int imm = 0;
10996                   imm |= (given & 0x000000c0u) >> 6;
10997                   imm |= (given & 0x00007000u) >> 10;
10998
10999                   func (stream, "%s", arm_regnames[reg]);
11000                   switch (stp)
11001                     {
11002                     case 0:
11003                       if (imm > 0)
11004                         func (stream, ", lsl #%u", imm);
11005                       break;
11006
11007                     case 1:
11008                       if (imm == 0)
11009                         imm = 32;
11010                       func (stream, ", lsr #%u", imm);
11011                       break;
11012
11013                     case 2:
11014                       if (imm == 0)
11015                         imm = 32;
11016                       func (stream, ", asr #%u", imm);
11017                       break;
11018
11019                     case 3:
11020                       if (imm == 0)
11021                         func (stream, ", rrx");
11022                       else
11023                         func (stream, ", ror #%u", imm);
11024                     }
11025                 }
11026                 break;
11027
11028               case 'a':
11029                 {
11030                   unsigned int Rn  = (given & 0x000f0000) >> 16;
11031                   unsigned int U   = ! NEGATIVE_BIT_SET;
11032                   unsigned int op  = (given & 0x00000f00) >> 8;
11033                   unsigned int i12 = (given & 0x00000fff);
11034                   unsigned int i8  = (given & 0x000000ff);
11035                   bool writeback = false, postind = false;
11036                   bfd_vma offset = 0;
11037
11038                   func (stream, "[%s", arm_regnames[Rn]);
11039                   if (U) /* 12-bit positive immediate offset.  */
11040                     {
11041                       offset = i12;
11042                       if (Rn != 15)
11043                         value_in_comment = offset;
11044                     }
11045                   else if (Rn == 15) /* 12-bit negative immediate offset.  */
11046                     offset = - (int) i12;
11047                   else if (op == 0x0) /* Shifted register offset.  */
11048                     {
11049                       unsigned int Rm = (i8 & 0x0f);
11050                       unsigned int sh = (i8 & 0x30) >> 4;
11051
11052                       func (stream, ", %s", arm_regnames[Rm]);
11053                       if (sh)
11054                         func (stream, ", lsl #%u", sh);
11055                       func (stream, "]");
11056                       break;
11057                     }
11058                   else switch (op)
11059                     {
11060                     case 0xE:  /* 8-bit positive immediate offset.  */
11061                       offset = i8;
11062                       break;
11063
11064                     case 0xC:  /* 8-bit negative immediate offset.  */
11065                       offset = -i8;
11066                       break;
11067
11068                     case 0xF:  /* 8-bit + preindex with wb.  */
11069                       offset = i8;
11070                       writeback = true;
11071                       break;
11072
11073                     case 0xD:  /* 8-bit - preindex with wb.  */
11074                       offset = -i8;
11075                       writeback = true;
11076                       break;
11077
11078                     case 0xB:  /* 8-bit + postindex.  */
11079                       offset = i8;
11080                       postind = true;
11081                       break;
11082
11083                     case 0x9:  /* 8-bit - postindex.  */
11084                       offset = -i8;
11085                       postind = true;
11086                       break;
11087
11088                     default:
11089                       func (stream, ", <undefined>]");
11090                       goto skip;
11091                     }
11092
11093                   if (postind)
11094                     func (stream, "], #%d", (int) offset);
11095                   else
11096                     {
11097                       if (offset)
11098                         func (stream, ", #%d", (int) offset);
11099                       func (stream, writeback ? "]!" : "]");
11100                     }
11101
11102                   if (Rn == 15)
11103                     {
11104                       func (stream, "\t; ");
11105                       info->print_address_func (((pc + 4) & ~3) + offset, info);
11106                     }
11107                 }
11108               skip:
11109                 break;
11110
11111               case 'A':
11112                 {
11113                   unsigned int U   = ! NEGATIVE_BIT_SET;
11114                   unsigned int W   = WRITEBACK_BIT_SET;
11115                   unsigned int Rn  = (given & 0x000f0000) >> 16;
11116                   unsigned int off = (given & 0x000000ff);
11117
11118                   func (stream, "[%s", arm_regnames[Rn]);
11119
11120                   if (PRE_BIT_SET)
11121                     {
11122                       if (off || !U)
11123                         {
11124                           func (stream, ", #%c%u", U ? '+' : '-', off * 4);
11125                           value_in_comment = off * 4 * (U ? 1 : -1);
11126                         }
11127                       func (stream, "]");
11128                       if (W)
11129                         func (stream, "!");
11130                     }
11131                   else
11132                     {
11133                       func (stream, "], ");
11134                       if (W)
11135                         {
11136                           func (stream, "#%c%u", U ? '+' : '-', off * 4);
11137                           value_in_comment = off * 4 * (U ? 1 : -1);
11138                         }
11139                       else
11140                         {
11141                           func (stream, "{%u}", off);
11142                           value_in_comment = off;
11143                         }
11144                     }
11145                 }
11146                 break;
11147
11148               case 'w':
11149                 {
11150                   unsigned int Sbit = (given & 0x01000000) >> 24;
11151                   unsigned int type = (given & 0x00600000) >> 21;
11152
11153                   switch (type)
11154                     {
11155                     case 0: func (stream, Sbit ? "sb" : "b"); break;
11156                     case 1: func (stream, Sbit ? "sh" : "h"); break;
11157                     case 2:
11158                       if (Sbit)
11159                         func (stream, "??");
11160                       break;
11161                     case 3:
11162                       func (stream, "??");
11163                       break;
11164                     }
11165                 }
11166                 break;
11167
11168               case 'n':
11169                 is_clrm = true;
11170                 /* Fall through.  */
11171               case 'm':
11172                 {
11173                   int started = 0;
11174                   int reg;
11175
11176                   func (stream, "{");
11177                   for (reg = 0; reg < 16; reg++)
11178                     if ((given & (1 << reg)) != 0)
11179                       {
11180                         if (started)
11181                           func (stream, ", ");
11182                         started = 1;
11183                         if (is_clrm && reg == 13)
11184                           func (stream, "(invalid: %s)", arm_regnames[reg]);
11185                         else if (is_clrm && reg == 15)
11186                           func (stream, "%s", "APSR");
11187                         else
11188                           func (stream, "%s", arm_regnames[reg]);
11189                       }
11190                   func (stream, "}");
11191                 }
11192                 break;
11193
11194               case 'E':
11195                 {
11196                   unsigned int msb = (given & 0x0000001f);
11197                   unsigned int lsb = 0;
11198
11199                   lsb |= (given & 0x000000c0u) >> 6;
11200                   lsb |= (given & 0x00007000u) >> 10;
11201                   func (stream, "#%u, #%u", lsb, msb - lsb + 1);
11202                 }
11203                 break;
11204
11205               case 'F':
11206                 {
11207                   unsigned int width = (given & 0x0000001f) + 1;
11208                   unsigned int lsb = 0;
11209
11210                   lsb |= (given & 0x000000c0u) >> 6;
11211                   lsb |= (given & 0x00007000u) >> 10;
11212                   func (stream, "#%u, #%u", lsb, width);
11213                 }
11214                 break;
11215
11216               case 'G':
11217                 {
11218                   unsigned int boff = (((given & 0x07800000) >> 23) << 1);
11219                   func (stream, "%x", boff);
11220                 }
11221                 break;
11222
11223               case 'W':
11224                 {
11225                   unsigned int immA = (given & 0x001f0000u) >> 16;
11226                   unsigned int immB = (given & 0x000007feu) >> 1;
11227                   unsigned int immC = (given & 0x00000800u) >> 11;
11228                   bfd_vma offset = 0;
11229
11230                   offset |= immA << 12;
11231                   offset |= immB << 2;
11232                   offset |= immC << 1;
11233                   /* Sign extend.  */
11234                   offset = (offset & 0x10000) ? offset - (1 << 17) : offset;
11235
11236                   info->print_address_func (pc + 4 + offset, info);
11237                 }
11238                 break;
11239
11240               case 'Y':
11241                 {
11242                   unsigned int immA = (given & 0x007f0000u) >> 16;
11243                   unsigned int immB = (given & 0x000007feu) >> 1;
11244                   unsigned int immC = (given & 0x00000800u) >> 11;
11245                   bfd_vma offset = 0;
11246
11247                   offset |= immA << 12;
11248                   offset |= immB << 2;
11249                   offset |= immC << 1;
11250                   /* Sign extend.  */
11251                   offset = (offset & 0x40000) ? offset - (1 << 19) : offset;
11252
11253                   info->print_address_func (pc + 4 + offset, info);
11254                 }
11255                 break;
11256
11257               case 'Z':
11258                 {
11259                   unsigned int immA = (given & 0x00010000u) >> 16;
11260                   unsigned int immB = (given & 0x000007feu) >> 1;
11261                   unsigned int immC = (given & 0x00000800u) >> 11;
11262                   bfd_vma offset = 0;
11263
11264                   offset |= immA << 12;
11265                   offset |= immB << 2;
11266                   offset |= immC << 1;
11267                   /* Sign extend.  */
11268                   offset = (offset & 0x1000) ? offset - (1 << 13) : offset;
11269
11270                   info->print_address_func (pc + 4 + offset, info);
11271
11272                   unsigned int T    = (given & 0x00020000u) >> 17;
11273                   unsigned int endoffset = (((given & 0x07800000) >> 23) << 1);
11274                   unsigned int boffset   = (T == 1) ? 4 : 2;
11275                   func (stream, ", ");
11276                   func (stream, "%x", endoffset + boffset);
11277                 }
11278                 break;
11279
11280               case 'Q':
11281                 {
11282                   unsigned int immh = (given & 0x000007feu) >> 1;
11283                   unsigned int imml = (given & 0x00000800u) >> 11;
11284                   bfd_vma imm32 = 0;
11285
11286                   imm32 |= immh << 2;
11287                   imm32 |= imml << 1;
11288
11289                   info->print_address_func (pc + 4 + imm32, info);
11290                 }
11291                 break;
11292
11293               case 'P':
11294                 {
11295                   unsigned int immh = (given & 0x000007feu) >> 1;
11296                   unsigned int imml = (given & 0x00000800u) >> 11;
11297                   bfd_vma imm32 = 0;
11298
11299                   imm32 |= immh << 2;
11300                   imm32 |= imml << 1;
11301
11302                   info->print_address_func (pc + 4 - imm32, info);
11303                 }
11304                 break;
11305
11306               case 'b':
11307                 {
11308                   unsigned int S = (given & 0x04000000u) >> 26;
11309                   unsigned int J1 = (given & 0x00002000u) >> 13;
11310                   unsigned int J2 = (given & 0x00000800u) >> 11;
11311                   bfd_vma offset = 0;
11312
11313                   offset |= !S << 20;
11314                   offset |= J2 << 19;
11315                   offset |= J1 << 18;
11316                   offset |= (given & 0x003f0000) >> 4;
11317                   offset |= (given & 0x000007ff) << 1;
11318                   offset -= (1 << 20);
11319
11320                   bfd_vma target = pc + 4 + offset;
11321                   info->print_address_func (target, info);
11322
11323                   /* Fill in instruction information.  */
11324                   info->insn_info_valid = 1;
11325                   info->insn_type = dis_branch;
11326                   info->target = target;
11327                 }
11328                 break;
11329
11330               case 'B':
11331                 {
11332                   unsigned int S = (given & 0x04000000u) >> 26;
11333                   unsigned int I1 = (given & 0x00002000u) >> 13;
11334                   unsigned int I2 = (given & 0x00000800u) >> 11;
11335                   bfd_vma offset = 0;
11336
11337                   offset |= !S << 24;
11338                   offset |= !(I1 ^ S) << 23;
11339                   offset |= !(I2 ^ S) << 22;
11340                   offset |= (given & 0x03ff0000u) >> 4;
11341                   offset |= (given & 0x000007ffu) << 1;
11342                   offset -= (1 << 24);
11343                   offset += pc + 4;
11344
11345                   /* BLX target addresses are always word aligned.  */
11346                   if ((given & 0x00001000u) == 0)
11347                       offset &= ~2u;
11348
11349                   info->print_address_func (offset, info);
11350
11351                   /* Fill in instruction information.  */
11352                   info->insn_info_valid = 1;
11353                   info->insn_type = dis_branch;
11354                   info->target = offset;
11355                 }
11356                 break;
11357
11358               case 's':
11359                 {
11360                   unsigned int shift = 0;
11361
11362                   shift |= (given & 0x000000c0u) >> 6;
11363                   shift |= (given & 0x00007000u) >> 10;
11364                   if (WRITEBACK_BIT_SET)
11365                     func (stream, ", asr #%u", shift);
11366                   else if (shift)
11367                     func (stream, ", lsl #%u", shift);
11368                   /* else print nothing - lsl #0 */
11369                 }
11370                 break;
11371
11372               case 'R':
11373                 {
11374                   unsigned int rot = (given & 0x00000030) >> 4;
11375
11376                   if (rot)
11377                     func (stream, ", ror #%u", rot * 8);
11378                 }
11379                 break;
11380
11381               case 'U':
11382                 if ((given & 0xf0) == 0x60)
11383                   {
11384                     switch (given & 0xf)
11385                       {
11386                         case 0xf: func (stream, "sy"); break;
11387                         default:
11388                           func (stream, "#%d", (int) given & 0xf);
11389                               break;
11390                       }
11391                   }
11392                 else
11393                   {
11394                     const char * opt = data_barrier_option (given & 0xf);
11395                     if (opt != NULL)
11396                       func (stream, "%s", opt);
11397                     else
11398                       func (stream, "#%d", (int) given & 0xf);
11399                    }
11400                 break;
11401
11402               case 'C':
11403                 if ((given & 0xff) == 0)
11404                   {
11405                     func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
11406                     if (given & 0x800)
11407                       func (stream, "f");
11408                     if (given & 0x400)
11409                       func (stream, "s");
11410                     if (given & 0x200)
11411                       func (stream, "x");
11412                     if (given & 0x100)
11413                       func (stream, "c");
11414                   }
11415                 else if ((given & 0x20) == 0x20)
11416                   {
11417                     char const* name;
11418                     unsigned sysm = (given & 0xf00) >> 8;
11419
11420                     sysm |= (given & 0x30);
11421                     sysm |= (given & 0x00100000) >> 14;
11422                     name = banked_regname (sysm);
11423
11424                     if (name != NULL)
11425                       func (stream, "%s", name);
11426                     else
11427                       func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
11428                   }
11429                 else
11430                   {
11431                     func (stream, "%s", psr_name (given & 0xff));
11432                   }
11433                 break;
11434
11435               case 'D':
11436                 if (((given & 0xff) == 0)
11437                     || ((given & 0x20) == 0x20))
11438                   {
11439                     char const* name;
11440                     unsigned sm = (given & 0xf0000) >> 16;
11441
11442                     sm |= (given & 0x30);
11443                     sm |= (given & 0x00100000) >> 14;
11444                     name = banked_regname (sm);
11445
11446                     if (name != NULL)
11447                       func (stream, "%s", name);
11448                     else
11449                       func (stream, "(UNDEF: %lu)", (unsigned long) sm);
11450                   }
11451                 else
11452                   func (stream, "%s", psr_name (given & 0xff));
11453                 break;
11454
11455               case '0': case '1': case '2': case '3': case '4':
11456               case '5': case '6': case '7': case '8': case '9':
11457                 {
11458                   int width;
11459                   unsigned long val;
11460
11461                   c = arm_decode_bitfield (c, given, &val, &width);
11462
11463                   switch (*c)
11464                     {
11465                     case 's':
11466                       if (val <= 3)
11467                         func (stream, "%s", mve_vec_sizename[val]);
11468                       else
11469                         func (stream, "<undef size>");
11470                       break;
11471
11472                     case 'd':
11473                       func (stream, "%lu", val);
11474                       value_in_comment = val;
11475                       break;
11476
11477                     case 'D':
11478                       func (stream, "%lu", val + 1);
11479                       value_in_comment = val + 1;
11480                       break;
11481
11482                     case 'W':
11483                       func (stream, "%lu", val * 4);
11484                       value_in_comment = val * 4;
11485                       break;
11486
11487                     case 'S':
11488                       if (val == 13)
11489                         is_unpredictable = true;
11490                       /* Fall through.  */
11491                     case 'R':
11492                       if (val == 15)
11493                         is_unpredictable = true;
11494                       /* Fall through.  */
11495                     case 'r':
11496                       func (stream, "%s", arm_regnames[val]);
11497                       break;
11498
11499                     case 'c':
11500                       func (stream, "%s", arm_conditional[val]);
11501                       break;
11502
11503                     case '\'':
11504                       c++;
11505                       if (val == ((1ul << width) - 1))
11506                         func (stream, "%c", *c);
11507                       break;
11508
11509                     case '`':
11510                       c++;
11511                       if (val == 0)
11512                         func (stream, "%c", *c);
11513                       break;
11514
11515                     case '?':
11516                       func (stream, "%c", c[(1 << width) - (int) val]);
11517                       c += 1 << width;
11518                       break;
11519
11520                     case 'x':
11521                       func (stream, "0x%lx", val & 0xffffffffUL);
11522                       break;
11523
11524                     default:
11525                       abort ();
11526                     }
11527                 }
11528                 break;
11529
11530               case 'L':
11531                 /* PR binutils/12534
11532                    If we have a PC relative offset in an LDRD or STRD
11533                    instructions then display the decoded address.  */
11534                 if (((given >> 16) & 0xf) == 0xf)
11535                   {
11536                     bfd_vma offset = (given & 0xff) * 4;
11537
11538                     if ((given & (1 << 23)) == 0)
11539                       offset = - offset;
11540                     func (stream, "\t; ");
11541                     info->print_address_func ((pc & ~3) + 4 + offset, info);
11542                   }
11543                 break;
11544
11545               default:
11546                 abort ();
11547               }
11548           }
11549
11550         if (value_in_comment > 32 || value_in_comment < -16)
11551           func (stream, "\t; 0x%lx", value_in_comment);
11552
11553         if (is_unpredictable)
11554           func (stream, UNPREDICTABLE_INSTRUCTION);
11555
11556         return;
11557       }
11558
11559   /* No match.  */
11560   func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
11561   return;
11562 }
11563
11564 /* Print data bytes on INFO->STREAM.  */
11565
11566 static void
11567 print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
11568                  struct disassemble_info *info,
11569                  long given)
11570 {
11571   switch (info->bytes_per_chunk)
11572     {
11573     case 1:
11574       info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
11575       break;
11576     case 2:
11577       info->fprintf_func (info->stream, ".short\t0x%04lx", given);
11578       break;
11579     case 4:
11580       info->fprintf_func (info->stream, ".word\t0x%08lx", given);
11581       break;
11582     default:
11583       abort ();
11584     }
11585 }
11586
11587 /* Disallow mapping symbols ($a, $b, $d, $t etc) from
11588    being displayed in symbol relative addresses.
11589
11590    Also disallow private symbol, with __tagsym$$ prefix,
11591    from ARM RVCT toolchain being displayed.  */
11592
11593 bool
11594 arm_symbol_is_valid (asymbol * sym,
11595                      struct disassemble_info * info ATTRIBUTE_UNUSED)
11596 {
11597   const char * name;
11598
11599   if (sym == NULL)
11600     return false;
11601
11602   name = bfd_asymbol_name (sym);
11603
11604   return (name && *name != '$' && strncmp (name, "__tagsym$$", 10));
11605 }
11606
11607 /* Parse the string of disassembler options.  */
11608
11609 static void
11610 parse_arm_disassembler_options (const char *options)
11611 {
11612   const char *opt;
11613
11614   FOR_EACH_DISASSEMBLER_OPTION (opt, options)
11615     {
11616       if (startswith (opt, "reg-names-"))
11617         {
11618           unsigned int i;
11619           for (i = 0; i < NUM_ARM_OPTIONS; i++)
11620             if (disassembler_options_cmp (opt, regnames[i].name) == 0)
11621               {
11622                 regname_selected = i;
11623                 break;
11624               }
11625
11626           if (i >= NUM_ARM_OPTIONS)
11627             /* xgettext: c-format */
11628             opcodes_error_handler (_("unrecognised register name set: %s"),
11629                                    opt);
11630         }
11631       else if (startswith (opt, "force-thumb"))
11632         force_thumb = 1;
11633       else if (startswith (opt, "no-force-thumb"))
11634         force_thumb = 0;
11635       else if (startswith (opt, "coproc"))
11636         {
11637           const char *procptr = opt + sizeof ("coproc") - 1;
11638           char *endptr;
11639           uint8_t coproc_number = strtol (procptr, &endptr, 10);
11640           if (endptr != procptr + 1 || coproc_number > 7)
11641             {
11642               opcodes_error_handler (_("cde coprocessor not between 0-7: %s"),
11643                                      opt);
11644               continue;
11645             }
11646           if (*endptr != '=')
11647             {
11648               opcodes_error_handler (_("coproc must have an argument: %s"),
11649                                      opt);
11650               continue;
11651             }
11652           endptr += 1;
11653           if (startswith (endptr, "generic"))
11654             cde_coprocs &= ~(1 << coproc_number);
11655           else if (startswith (endptr, "cde")
11656                    || startswith (endptr, "CDE"))
11657             cde_coprocs |= (1 << coproc_number);
11658           else
11659             {
11660               opcodes_error_handler (
11661                   _("coprocN argument takes options \"generic\","
11662                     " \"cde\", or \"CDE\": %s"), opt);
11663             }
11664         }
11665       else
11666         /* xgettext: c-format */
11667         opcodes_error_handler (_("unrecognised disassembler option: %s"), opt);
11668     }
11669
11670   return;
11671 }
11672
11673 static bool
11674 mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
11675                          enum map_type *map_symbol);
11676
11677 /* Search back through the insn stream to determine if this instruction is
11678    conditionally executed.  */
11679
11680 static void
11681 find_ifthen_state (bfd_vma pc,
11682                    struct disassemble_info *info,
11683                    bool little)
11684 {
11685   unsigned char b[2];
11686   unsigned int insn;
11687   int status;
11688   /* COUNT is twice the number of instructions seen.  It will be odd if we
11689      just crossed an instruction boundary.  */
11690   int count;
11691   int it_count;
11692   unsigned int seen_it;
11693   bfd_vma addr;
11694
11695   ifthen_address = pc;
11696   ifthen_state = 0;
11697
11698   addr = pc;
11699   count = 1;
11700   it_count = 0;
11701   seen_it = 0;
11702   /* Scan backwards looking for IT instructions, keeping track of where
11703      instruction boundaries are.  We don't know if something is actually an
11704      IT instruction until we find a definite instruction boundary.  */
11705   for (;;)
11706     {
11707       if (addr == 0 || info->symbol_at_address_func (addr, info))
11708         {
11709           /* A symbol must be on an instruction boundary, and will not
11710              be within an IT block.  */
11711           if (seen_it && (count & 1))
11712             break;
11713
11714           return;
11715         }
11716       addr -= 2;
11717       status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
11718       if (status)
11719         return;
11720
11721       if (little)
11722         insn = (b[0]) | (b[1] << 8);
11723       else
11724         insn = (b[1]) | (b[0] << 8);
11725       if (seen_it)
11726         {
11727           if ((insn & 0xf800) < 0xe800)
11728             {
11729               /* Addr + 2 is an instruction boundary.  See if this matches
11730                  the expected boundary based on the position of the last
11731                  IT candidate.  */
11732               if (count & 1)
11733                 break;
11734               seen_it = 0;
11735             }
11736         }
11737       if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
11738         {
11739           enum map_type type = MAP_ARM;
11740           bool found = mapping_symbol_for_insn (addr, info, &type);
11741
11742           if (!found || (found && type == MAP_THUMB))
11743             {
11744               /* This could be an IT instruction.  */
11745               seen_it = insn;
11746               it_count = count >> 1;
11747             }
11748         }
11749       if ((insn & 0xf800) >= 0xe800)
11750         count++;
11751       else
11752         count = (count + 2) | 1;
11753       /* IT blocks contain at most 4 instructions.  */
11754       if (count >= 8 && !seen_it)
11755         return;
11756     }
11757   /* We found an IT instruction.  */
11758   ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
11759   if ((ifthen_state & 0xf) == 0)
11760     ifthen_state = 0;
11761 }
11762
11763 /* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
11764    mapping symbol.  */
11765
11766 static int
11767 is_mapping_symbol (struct disassemble_info *info, int n,
11768                    enum map_type *map_type)
11769 {
11770   const char *name;
11771
11772   name = bfd_asymbol_name (info->symtab[n]);
11773   if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
11774       && (name[2] == 0 || name[2] == '.'))
11775     {
11776       *map_type = ((name[1] == 'a') ? MAP_ARM
11777                    : (name[1] == 't') ? MAP_THUMB
11778                    : MAP_DATA);
11779       return true;
11780     }
11781
11782   return false;
11783 }
11784
11785 /* Try to infer the code type (ARM or Thumb) from a mapping symbol.
11786    Returns nonzero if *MAP_TYPE was set.  */
11787
11788 static int
11789 get_map_sym_type (struct disassemble_info *info,
11790                   int n,
11791                   enum map_type *map_type)
11792 {
11793   /* If the symbol is in a different section, ignore it.  */
11794   if (info->section != NULL && info->section != info->symtab[n]->section)
11795     return false;
11796
11797   return is_mapping_symbol (info, n, map_type);
11798 }
11799
11800 /* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
11801    Returns nonzero if *MAP_TYPE was set.  */
11802
11803 static int
11804 get_sym_code_type (struct disassemble_info *info,
11805                    int n,
11806                    enum map_type *map_type)
11807 {
11808   elf_symbol_type *es;
11809   unsigned int type;
11810
11811   /* If the symbol is in a different section, ignore it.  */
11812   if (info->section != NULL && info->section != info->symtab[n]->section)
11813     return false;
11814
11815   es = *(elf_symbol_type **)(info->symtab + n);
11816   type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
11817
11818   /* If the symbol has function type then use that.  */
11819   if (type == STT_FUNC || type == STT_GNU_IFUNC)
11820     {
11821       if (ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
11822           == ST_BRANCH_TO_THUMB)
11823         *map_type = MAP_THUMB;
11824       else
11825         *map_type = MAP_ARM;
11826       return true;
11827     }
11828
11829   return false;
11830 }
11831
11832 /* Search the mapping symbol state for instruction at pc.  This is only
11833    applicable for elf target.
11834
11835    There is an assumption Here, info->private_data contains the correct AND
11836    up-to-date information about current scan process.  The information will be
11837    used to speed this search process.
11838
11839    Return TRUE if the mapping state can be determined, and map_symbol
11840    will be updated accordingly.  Otherwise, return FALSE.  */
11841
11842 static bool
11843 mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
11844                          enum map_type *map_symbol)
11845 {
11846   bfd_vma addr, section_vma = 0;
11847   int n, last_sym = -1;
11848   bool found = false;
11849   bool can_use_search_opt_p = false;
11850
11851   /* Default to DATA.  A text section is required by the ABI to contain an
11852      INSN mapping symbol at the start.  A data section has no such
11853      requirement, hence if no mapping symbol is found the section must
11854      contain only data.  This however isn't very useful if the user has
11855      fully stripped the binaries.  If this is the case use the section
11856      attributes to determine the default.  If we have no section default to
11857      INSN as well, as we may be disassembling some raw bytes on a baremetal
11858      HEX file or similar.  */
11859   enum map_type type = MAP_DATA;
11860   if ((info->section && info->section->flags & SEC_CODE) || !info->section)
11861     type = MAP_ARM;
11862   struct arm_private_data *private_data;
11863
11864   if (info->private_data == NULL
11865       || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour)
11866     return false;
11867
11868   private_data = info->private_data;
11869
11870   /* First, look for mapping symbols.  */
11871   if (info->symtab_size != 0)
11872   {
11873     if (pc <= private_data->last_mapping_addr)
11874       private_data->last_mapping_sym = -1;
11875
11876     /* Start scanning at the start of the function, or wherever
11877        we finished last time.  */
11878     n = info->symtab_pos + 1;
11879
11880     /* If the last stop offset is different from the current one it means we
11881        are disassembling a different glob of bytes.  As such the optimization
11882        would not be safe and we should start over.  */
11883     can_use_search_opt_p
11884       = private_data->last_mapping_sym >= 0
11885         && info->stop_offset == private_data->last_stop_offset;
11886
11887     if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
11888       n = private_data->last_mapping_sym;
11889
11890     /* Look down while we haven't passed the location being disassembled.
11891        The reason for this is that there's no defined order between a symbol
11892        and an mapping symbol that may be at the same address.  We may have to
11893        look at least one position ahead.  */
11894     for (; n < info->symtab_size; n++)
11895       {
11896         addr = bfd_asymbol_value (info->symtab[n]);
11897         if (addr > pc)
11898           break;
11899         if (get_map_sym_type (info, n, &type))
11900           {
11901             last_sym = n;
11902             found = true;
11903           }
11904       }
11905
11906     if (!found)
11907       {
11908         n = info->symtab_pos;
11909         if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
11910           n = private_data->last_mapping_sym;
11911
11912         /* No mapping symbol found at this address.  Look backwards
11913            for a preceeding one, but don't go pass the section start
11914            otherwise a data section with no mapping symbol can pick up
11915            a text mapping symbol of a preceeding section.  The documentation
11916            says section can be NULL, in which case we will seek up all the
11917            way to the top.  */
11918         if (info->section)
11919           section_vma = info->section->vma;
11920
11921         for (; n >= 0; n--)
11922           {
11923             addr = bfd_asymbol_value (info->symtab[n]);
11924             if (addr < section_vma)
11925               break;
11926
11927             if (get_map_sym_type (info, n, &type))
11928               {
11929                 last_sym = n;
11930                 found = true;
11931                 break;
11932               }
11933           }
11934       }
11935   }
11936
11937   /* If no mapping symbol was found, try looking up without a mapping
11938      symbol.  This is done by walking up from the current PC to the nearest
11939      symbol.  We don't actually have to loop here since symtab_pos will
11940      contain the nearest symbol already.  */
11941   if (!found)
11942     {
11943       n = info->symtab_pos;
11944       if (n >= 0 && get_sym_code_type (info, n, &type))
11945         {
11946           last_sym = n;
11947           found = true;
11948         }
11949     }
11950
11951   private_data->last_mapping_sym = last_sym;
11952   private_data->last_type = type;
11953   private_data->last_stop_offset = info->stop_offset;
11954
11955   *map_symbol = type;
11956   return found;
11957 }
11958
11959 /* Given a bfd_mach_arm_XXX value, this function fills in the fields
11960    of the supplied arm_feature_set structure with bitmasks indicating
11961    the supported base architectures and coprocessor extensions.
11962
11963    FIXME: This could more efficiently implemented as a constant array,
11964    although it would also be less robust.  */
11965
11966 static void
11967 select_arm_features (unsigned long mach,
11968                      arm_feature_set * features)
11969 {
11970   arm_feature_set arch_fset;
11971   const arm_feature_set fpu_any = FPU_ANY;
11972
11973 #undef ARM_SET_FEATURES
11974 #define ARM_SET_FEATURES(FSET) \
11975   {                                                     \
11976     const arm_feature_set fset = FSET;                  \
11977     arch_fset = fset;                                   \
11978   }
11979
11980   /* When several architecture versions share the same bfd_mach_arm_XXX value
11981      the most featureful is chosen.  */
11982   switch (mach)
11983     {
11984     case bfd_mach_arm_2:         ARM_SET_FEATURES (ARM_ARCH_V2); break;
11985     case bfd_mach_arm_2a:        ARM_SET_FEATURES (ARM_ARCH_V2S); break;
11986     case bfd_mach_arm_3:         ARM_SET_FEATURES (ARM_ARCH_V3); break;
11987     case bfd_mach_arm_3M:        ARM_SET_FEATURES (ARM_ARCH_V3M); break;
11988     case bfd_mach_arm_4:         ARM_SET_FEATURES (ARM_ARCH_V4); break;
11989     case bfd_mach_arm_4T:        ARM_SET_FEATURES (ARM_ARCH_V4T); break;
11990     case bfd_mach_arm_5:         ARM_SET_FEATURES (ARM_ARCH_V5); break;
11991     case bfd_mach_arm_5T:        ARM_SET_FEATURES (ARM_ARCH_V5T); break;
11992     case bfd_mach_arm_5TE:       ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
11993     case bfd_mach_arm_XScale:    ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
11994     case bfd_mach_arm_ep9312:
11995         ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T,
11996                                            ARM_CEXT_MAVERICK | FPU_MAVERICK));
11997        break;
11998     case bfd_mach_arm_iWMMXt:    ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
11999     case bfd_mach_arm_iWMMXt2:   ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
12000     case bfd_mach_arm_5TEJ:      ARM_SET_FEATURES (ARM_ARCH_V5TEJ); break;
12001     case bfd_mach_arm_6:         ARM_SET_FEATURES (ARM_ARCH_V6); break;
12002     case bfd_mach_arm_6KZ:       ARM_SET_FEATURES (ARM_ARCH_V6KZ); break;
12003     case bfd_mach_arm_6T2:       ARM_SET_FEATURES (ARM_ARCH_V6KZT2); break;
12004     case bfd_mach_arm_6K:        ARM_SET_FEATURES (ARM_ARCH_V6K); break;
12005     case bfd_mach_arm_7:         ARM_SET_FEATURES (ARM_ARCH_V7VE); break;
12006     case bfd_mach_arm_6M:        ARM_SET_FEATURES (ARM_ARCH_V6M); break;
12007     case bfd_mach_arm_6SM:       ARM_SET_FEATURES (ARM_ARCH_V6SM); break;
12008     case bfd_mach_arm_7EM:       ARM_SET_FEATURES (ARM_ARCH_V7EM); break;
12009     case bfd_mach_arm_8:
12010         {
12011           /* Add bits for extensions that Armv8.6-A recognizes.  */
12012           arm_feature_set armv8_6_ext_fset
12013             = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST);
12014           ARM_SET_FEATURES (ARM_ARCH_V8_6A);
12015           ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, armv8_6_ext_fset);
12016           break;
12017         }
12018     case bfd_mach_arm_8R:        ARM_SET_FEATURES (ARM_ARCH_V8R); break;
12019     case bfd_mach_arm_8M_BASE:   ARM_SET_FEATURES (ARM_ARCH_V8M_BASE); break;
12020     case bfd_mach_arm_8M_MAIN:   ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN); break;
12021     case bfd_mach_arm_8_1M_MAIN:
12022       ARM_SET_FEATURES (ARM_ARCH_V8_1M_MAIN);
12023       arm_feature_set mve_all
12024         = ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE | ARM_EXT2_MVE_FP);
12025       ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, mve_all);
12026       force_thumb = 1;
12027       break;
12028       /* If the machine type is unknown allow all architecture types and all
12029          extensions, with the exception of MVE as that clashes with NEON.  */
12030     case bfd_mach_arm_unknown:
12031       ARM_SET_FEATURES (ARM_FEATURE (-1,
12032                                      -1 & ~(ARM_EXT2_MVE | ARM_EXT2_MVE_FP),
12033                                      -1));
12034       break;
12035     default:
12036       abort ();
12037     }
12038 #undef ARM_SET_FEATURES
12039
12040   /* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch
12041      and thus on bfd_mach_arm_XXX value.  Therefore for a given
12042      bfd_mach_arm_XXX value all coprocessor feature bits should be allowed.  */
12043   ARM_MERGE_FEATURE_SETS (*features, arch_fset, fpu_any);
12044 }
12045
12046
12047 /* NOTE: There are no checks in these routines that
12048    the relevant number of data bytes exist.  */
12049
12050 static int
12051 print_insn (bfd_vma pc, struct disassemble_info *info, bool little)
12052 {
12053   unsigned char b[4];
12054   unsigned long given;
12055   int status;
12056   int is_thumb = false;
12057   int is_data = false;
12058   int little_code;
12059   unsigned int  size = 4;
12060   void (*printer) (bfd_vma, struct disassemble_info *, long);
12061   bool found = false;
12062   struct arm_private_data *private_data;
12063
12064   /* Clear instruction information field.  */
12065   info->insn_info_valid = 0;
12066   info->branch_delay_insns = 0;
12067   info->data_size = 0;
12068   info->insn_type = dis_noninsn;
12069   info->target = 0;
12070   info->target2 = 0;
12071
12072   if (info->disassembler_options)
12073     {
12074       parse_arm_disassembler_options (info->disassembler_options);
12075
12076       /* To avoid repeated parsing of these options, we remove them here.  */
12077       info->disassembler_options = NULL;
12078     }
12079
12080   /* PR 10288: Control which instructions will be disassembled.  */
12081   if (info->private_data == NULL)
12082     {
12083       static struct arm_private_data private;
12084
12085       if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
12086         /* If the user did not use the -m command line switch then default to
12087            disassembling all types of ARM instruction.
12088
12089            The info->mach value has to be ignored as this will be based on
12090            the default archictecture for the target and/or hints in the notes
12091            section, but it will never be greater than the current largest arm
12092            machine value (iWMMXt2), which is only equivalent to the V5TE
12093            architecture.  ARM architectures have advanced beyond the machine
12094            value encoding, and these newer architectures would be ignored if
12095            the machine value was used.
12096
12097            Ie the -m switch is used to restrict which instructions will be
12098            disassembled.  If it is necessary to use the -m switch to tell
12099            objdump that an ARM binary is being disassembled, eg because the
12100            input is a raw binary file, but it is also desired to disassemble
12101            all ARM instructions then use "-marm".  This will select the
12102            "unknown" arm architecture which is compatible with any ARM
12103            instruction.  */
12104           info->mach = bfd_mach_arm_unknown;
12105
12106       /* Compute the architecture bitmask from the machine number.
12107          Note: This assumes that the machine number will not change
12108          during disassembly....  */
12109       select_arm_features (info->mach, & private.features);
12110
12111       private.last_mapping_sym = -1;
12112       private.last_mapping_addr = 0;
12113       private.last_stop_offset = 0;
12114
12115       info->private_data = & private;
12116     }
12117
12118   private_data = info->private_data;
12119
12120   /* Decide if our code is going to be little-endian, despite what the
12121      function argument might say.  */
12122   little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
12123
12124   /* For ELF, consult the symbol table to determine what kind of code
12125      or data we have.  */
12126   if (info->symtab_size != 0
12127       && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
12128     {
12129       bfd_vma addr;
12130       int n;
12131       int last_sym = -1;
12132       enum map_type type = MAP_ARM;
12133
12134       found = mapping_symbol_for_insn (pc, info, &type);
12135       last_sym = private_data->last_mapping_sym;
12136
12137       is_thumb = (private_data->last_type == MAP_THUMB);
12138       is_data = (private_data->last_type == MAP_DATA);
12139
12140       /* Look a little bit ahead to see if we should print out
12141          two or four bytes of data.  If there's a symbol,
12142          mapping or otherwise, after two bytes then don't
12143          print more.  */
12144       if (is_data)
12145         {
12146           size = 4 - (pc & 3);
12147           for (n = last_sym + 1; n < info->symtab_size; n++)
12148             {
12149               addr = bfd_asymbol_value (info->symtab[n]);
12150               if (addr > pc
12151                   && (info->section == NULL
12152                       || info->section == info->symtab[n]->section))
12153                 {
12154                   if (addr - pc < size)
12155                     size = addr - pc;
12156                   break;
12157                 }
12158             }
12159           /* If the next symbol is after three bytes, we need to
12160              print only part of the data, so that we can use either
12161              .byte or .short.  */
12162           if (size == 3)
12163             size = (pc & 1) ? 1 : 2;
12164         }
12165     }
12166
12167   if (info->symbols != NULL)
12168     {
12169       if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
12170         {
12171           coff_symbol_type * cs;
12172
12173           cs = coffsymbol (*info->symbols);
12174           is_thumb = (   cs->native->u.syment.n_sclass == C_THUMBEXT
12175                       || cs->native->u.syment.n_sclass == C_THUMBSTAT
12176                       || cs->native->u.syment.n_sclass == C_THUMBLABEL
12177                       || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
12178                       || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
12179         }
12180       else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
12181                && !found)
12182         {
12183           /* If no mapping symbol has been found then fall back to the type
12184              of the function symbol.  */
12185           elf_symbol_type *  es;
12186           unsigned int       type;
12187
12188           es = *(elf_symbol_type **)(info->symbols);
12189           type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
12190
12191           is_thumb =
12192             ((ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
12193               == ST_BRANCH_TO_THUMB) || type == STT_ARM_16BIT);
12194         }
12195       else if (bfd_asymbol_flavour (*info->symbols)
12196                == bfd_target_mach_o_flavour)
12197         {
12198           bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols;
12199
12200           is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF);
12201         }
12202     }
12203
12204   if (force_thumb)
12205     is_thumb = true;
12206
12207   if (is_data)
12208     info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
12209   else
12210     info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
12211
12212   info->bytes_per_line = 4;
12213
12214   /* PR 10263: Disassemble data if requested to do so by the user.  */
12215   if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
12216     {
12217       int i;
12218
12219       /* Size was already set above.  */
12220       info->bytes_per_chunk = size;
12221       printer = print_insn_data;
12222
12223       status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
12224       given = 0;
12225       if (little)
12226         for (i = size - 1; i >= 0; i--)
12227           given = b[i] | (given << 8);
12228       else
12229         for (i = 0; i < (int) size; i++)
12230           given = b[i] | (given << 8);
12231     }
12232   else if (!is_thumb)
12233     {
12234       /* In ARM mode endianness is a straightforward issue: the instruction
12235          is four bytes long and is either ordered 0123 or 3210.  */
12236       printer = print_insn_arm;
12237       info->bytes_per_chunk = 4;
12238       size = 4;
12239
12240       status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
12241       if (little_code)
12242         given = (b[0]) | (b[1] << 8) | (b[2] << 16) | ((unsigned) b[3] << 24);
12243       else
12244         given = (b[3]) | (b[2] << 8) | (b[1] << 16) | ((unsigned) b[0] << 24);
12245     }
12246   else
12247     {
12248       /* In Thumb mode we have the additional wrinkle of two
12249          instruction lengths.  Fortunately, the bits that determine
12250          the length of the current instruction are always to be found
12251          in the first two bytes.  */
12252       printer = print_insn_thumb16;
12253       info->bytes_per_chunk = 2;
12254       size = 2;
12255
12256       status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
12257       if (little_code)
12258         given = (b[0]) | (b[1] << 8);
12259       else
12260         given = (b[1]) | (b[0] << 8);
12261
12262       if (!status)
12263         {
12264           /* These bit patterns signal a four-byte Thumb
12265              instruction.  */
12266           if ((given & 0xF800) == 0xF800
12267               || (given & 0xF800) == 0xF000
12268               || (given & 0xF800) == 0xE800)
12269             {
12270               status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
12271               if (little_code)
12272                 given = (b[0]) | (b[1] << 8) | (given << 16);
12273               else
12274                 given = (b[1]) | (b[0] << 8) | (given << 16);
12275
12276               printer = print_insn_thumb32;
12277               size = 4;
12278             }
12279         }
12280
12281       if (ifthen_address != pc)
12282         find_ifthen_state (pc, info, little_code);
12283
12284       if (ifthen_state)
12285         {
12286           if ((ifthen_state & 0xf) == 0x8)
12287             ifthen_next_state = 0;
12288           else
12289             ifthen_next_state = (ifthen_state & 0xe0)
12290                                 | ((ifthen_state & 0xf) << 1);
12291         }
12292     }
12293
12294   if (status)
12295     {
12296       info->memory_error_func (status, pc, info);
12297       return -1;
12298     }
12299   if (info->flags & INSN_HAS_RELOC)
12300     /* If the instruction has a reloc associated with it, then
12301        the offset field in the instruction will actually be the
12302        addend for the reloc.  (We are using REL type relocs).
12303        In such cases, we can ignore the pc when computing
12304        addresses, since the addend is not currently pc-relative.  */
12305     pc = 0;
12306
12307   printer (pc, info, given);
12308
12309   if (is_thumb)
12310     {
12311       ifthen_state = ifthen_next_state;
12312       ifthen_address += size;
12313     }
12314   return size;
12315 }
12316
12317 int
12318 print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
12319 {
12320   /* Detect BE8-ness and record it in the disassembler info.  */
12321   if (info->flavour == bfd_target_elf_flavour
12322       && info->section != NULL
12323       && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
12324     info->endian_code = BFD_ENDIAN_LITTLE;
12325
12326   return print_insn (pc, info, false);
12327 }
12328
12329 int
12330 print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
12331 {
12332   return print_insn (pc, info, true);
12333 }
12334
12335 const disasm_options_and_args_t *
12336 disassembler_options_arm (void)
12337 {
12338   static disasm_options_and_args_t *opts_and_args;
12339
12340   if (opts_and_args == NULL)
12341     {
12342       disasm_options_t *opts;
12343       unsigned int i;
12344
12345       opts_and_args = XNEW (disasm_options_and_args_t);
12346       opts_and_args->args = NULL;
12347
12348       opts = &opts_and_args->options;
12349       opts->name = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
12350       opts->description = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
12351       opts->arg = NULL;
12352       for (i = 0; i < NUM_ARM_OPTIONS; i++)
12353         {
12354           opts->name[i] = regnames[i].name;
12355           if (regnames[i].description != NULL)
12356             opts->description[i] = _(regnames[i].description);
12357           else
12358             opts->description[i] = NULL;
12359         }
12360       /* The array we return must be NULL terminated.  */
12361       opts->name[i] = NULL;
12362       opts->description[i] = NULL;
12363     }
12364
12365   return opts_and_args;
12366 }
12367
12368 void
12369 print_arm_disassembler_options (FILE *stream)
12370 {
12371   unsigned int i, max_len = 0;
12372   fprintf (stream, _("\n\
12373 The following ARM specific disassembler options are supported for use with\n\
12374 the -M switch:\n"));
12375
12376   for (i = 0; i < NUM_ARM_OPTIONS; i++)
12377     {
12378       unsigned int len = strlen (regnames[i].name);
12379       if (max_len < len)
12380         max_len = len;
12381     }
12382
12383   for (i = 0, max_len++; i < NUM_ARM_OPTIONS; i++)
12384     fprintf (stream, "  %s%*c %s\n",
12385              regnames[i].name,
12386              (int)(max_len - strlen (regnames[i].name)), ' ',
12387              _(regnames[i].description));
12388 }