opcodes/arm-dis.c

   1 /* Instruction printing code for the ARM
   2    Copyright (C) 1994-2021 Free Software Foundation, Inc.
   3    Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
   4    Modification by James G. Smith (jsmith@cygnus.co.uk)
   5
   6    This file is part of libopcodes.
   7
   8    This library is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the License, or
  11    (at your option) any later version.
  12
  13    It is distributed in the hope that it will be useful, but WITHOUT
  14    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16    License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; if not, write to the Free Software
  20    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  21    MA 02110-1301, USA.  */
  22
  23 #include "sysdep.h"
  24 #include <assert.h>
  25
  26 #include "disassemble.h"
  27 #include "opcode/arm.h"
  28 #include "opintl.h"
  29 #include "safe-ctype.h"
  30 #include "libiberty.h"
  31 #include "floatformat.h"
  32
  33 /* FIXME: This shouldn't be done here.  */
  34 #include "coff/internal.h"
  35 #include "libcoff.h"
  36 #include "bfd.h"
  37 #include "elf-bfd.h"
  38 #include "elf/internal.h"
  39 #include "elf/arm.h"
  40 #include "mach-o.h"
  41
  42 /* Cached mapping symbol state.  */
  43 enum map_type
  44 {
  45   MAP_ARM,
  46   MAP_THUMB,
  47   MAP_DATA
  48 };
  49
  50 struct arm_private_data
  51 {
  52   /* The features to use when disassembling optional instructions.  */
  53   arm_feature_set features;
  54
  55   /* Track the last type (although this doesn't seem to be useful) */
  56   enum map_type last_type;
  57
  58   /* Tracking symbol table information */
  59   int last_mapping_sym;
  60
  61   /* The end range of the current range being disassembled.  */
  62   bfd_vma last_stop_offset;
  63   bfd_vma last_mapping_addr;
  64 };
  65
  66 enum mve_instructions
  67 {
  68   MVE_VPST,
  69   MVE_VPT_FP_T1,
  70   MVE_VPT_FP_T2,
  71   MVE_VPT_VEC_T1,
  72   MVE_VPT_VEC_T2,
  73   MVE_VPT_VEC_T3,
  74   MVE_VPT_VEC_T4,
  75   MVE_VPT_VEC_T5,
  76   MVE_VPT_VEC_T6,
  77   MVE_VCMP_FP_T1,
  78   MVE_VCMP_FP_T2,
  79   MVE_VCMP_VEC_T1,
  80   MVE_VCMP_VEC_T2,
  81   MVE_VCMP_VEC_T3,
  82   MVE_VCMP_VEC_T4,
  83   MVE_VCMP_VEC_T5,
  84   MVE_VCMP_VEC_T6,
  85   MVE_VDUP,
  86   MVE_VEOR,
  87   MVE_VFMAS_FP_SCALAR,
  88   MVE_VFMA_FP_SCALAR,
  89   MVE_VFMA_FP,
  90   MVE_VFMS_FP,
  91   MVE_VHADD_T1,
  92   MVE_VHADD_T2,
  93   MVE_VHSUB_T1,
  94   MVE_VHSUB_T2,
  95   MVE_VRHADD,
  96   MVE_VLD2,
  97   MVE_VLD4,
  98   MVE_VST2,
  99   MVE_VST4,
 100   MVE_VLDRB_T1,
 101   MVE_VLDRH_T2,
 102   MVE_VLDRB_T5,
 103   MVE_VLDRH_T6,
 104   MVE_VLDRW_T7,
 105   MVE_VSTRB_T1,
 106   MVE_VSTRH_T2,
 107   MVE_VSTRB_T5,
 108   MVE_VSTRH_T6,
 109   MVE_VSTRW_T7,
 110   MVE_VLDRB_GATHER_T1,
 111   MVE_VLDRH_GATHER_T2,
 112   MVE_VLDRW_GATHER_T3,
 113   MVE_VLDRD_GATHER_T4,
 114   MVE_VLDRW_GATHER_T5,
 115   MVE_VLDRD_GATHER_T6,
 116   MVE_VSTRB_SCATTER_T1,
 117   MVE_VSTRH_SCATTER_T2,
 118   MVE_VSTRW_SCATTER_T3,
 119   MVE_VSTRD_SCATTER_T4,
 120   MVE_VSTRW_SCATTER_T5,
 121   MVE_VSTRD_SCATTER_T6,
 122   MVE_VCVT_FP_FIX_VEC,
 123   MVE_VCVT_BETWEEN_FP_INT,
 124   MVE_VCVT_FP_HALF_FP,
 125   MVE_VCVT_FROM_FP_TO_INT,
 126   MVE_VRINT_FP,
 127   MVE_VMOV_HFP_TO_GP,
 128   MVE_VMOV_GP_TO_VEC_LANE,
 129   MVE_VMOV_IMM_TO_VEC,
 130   MVE_VMOV_VEC_TO_VEC,
 131   MVE_VMOV2_VEC_LANE_TO_GP,
 132   MVE_VMOV2_GP_TO_VEC_LANE,
 133   MVE_VMOV_VEC_LANE_TO_GP,
 134   MVE_VMVN_IMM,
 135   MVE_VMVN_REG,
 136   MVE_VORR_IMM,
 137   MVE_VORR_REG,
 138   MVE_VORN,
 139   MVE_VBIC_IMM,
 140   MVE_VBIC_REG,
 141   MVE_VMOVX,
 142   MVE_VMOVL,
 143   MVE_VMOVN,
 144   MVE_VMULL_INT,
 145   MVE_VMULL_POLY,
 146   MVE_VQDMULL_T1,
 147   MVE_VQDMULL_T2,
 148   MVE_VQMOVN,
 149   MVE_VQMOVUN,
 150   MVE_VADDV,
 151   MVE_VMLADAV_T1,
 152   MVE_VMLADAV_T2,
 153   MVE_VMLALDAV,
 154   MVE_VMLAS,
 155   MVE_VADDLV,
 156   MVE_VMLSDAV_T1,
 157   MVE_VMLSDAV_T2,
 158   MVE_VMLSLDAV,
 159   MVE_VRMLALDAVH,
 160   MVE_VRMLSLDAVH,
 161   MVE_VQDMLADH,
 162   MVE_VQRDMLADH,
 163   MVE_VQDMLAH,
 164   MVE_VQRDMLAH,
 165   MVE_VQDMLASH,
 166   MVE_VQRDMLASH,
 167   MVE_VQDMLSDH,
 168   MVE_VQRDMLSDH,
 169   MVE_VQDMULH_T1,
 170   MVE_VQRDMULH_T2,
 171   MVE_VQDMULH_T3,
 172   MVE_VQRDMULH_T4,
 173   MVE_VDDUP,
 174   MVE_VDWDUP,
 175   MVE_VIWDUP,
 176   MVE_VIDUP,
 177   MVE_VCADD_FP,
 178   MVE_VCADD_VEC,
 179   MVE_VHCADD,
 180   MVE_VCMLA_FP,
 181   MVE_VCMUL_FP,
 182   MVE_VQRSHL_T1,
 183   MVE_VQRSHL_T2,
 184   MVE_VQRSHRN,
 185   MVE_VQRSHRUN,
 186   MVE_VQSHL_T1,
 187   MVE_VQSHL_T2,
 188   MVE_VQSHLU_T3,
 189   MVE_VQSHL_T4,
 190   MVE_VQSHRN,
 191   MVE_VQSHRUN,
 192   MVE_VRSHL_T1,
 193   MVE_VRSHL_T2,
 194   MVE_VRSHR,
 195   MVE_VRSHRN,
 196   MVE_VSHL_T1,
 197   MVE_VSHL_T2,
 198   MVE_VSHL_T3,
 199   MVE_VSHLC,
 200   MVE_VSHLL_T1,
 201   MVE_VSHLL_T2,
 202   MVE_VSHR,
 203   MVE_VSHRN,
 204   MVE_VSLI,
 205   MVE_VSRI,
 206   MVE_VADC,
 207   MVE_VABAV,
 208   MVE_VABD_FP,
 209   MVE_VABD_VEC,
 210   MVE_VABS_FP,
 211   MVE_VABS_VEC,
 212   MVE_VADD_FP_T1,
 213   MVE_VADD_FP_T2,
 214   MVE_VADD_VEC_T1,
 215   MVE_VADD_VEC_T2,
 216   MVE_VSBC,
 217   MVE_VSUB_FP_T1,
 218   MVE_VSUB_FP_T2,
 219   MVE_VSUB_VEC_T1,
 220   MVE_VSUB_VEC_T2,
 221   MVE_VAND,
 222   MVE_VBRSR,
 223   MVE_VCLS,
 224   MVE_VCLZ,
 225   MVE_VCTP,
 226   MVE_VMAX,
 227   MVE_VMAXA,
 228   MVE_VMAXNM_FP,
 229   MVE_VMAXNMA_FP,
 230   MVE_VMAXNMV_FP,
 231   MVE_VMAXNMAV_FP,
 232   MVE_VMAXV,
 233   MVE_VMAXAV,
 234   MVE_VMIN,
 235   MVE_VMINA,
 236   MVE_VMINNM_FP,
 237   MVE_VMINNMA_FP,
 238   MVE_VMINNMV_FP,
 239   MVE_VMINNMAV_FP,
 240   MVE_VMINV,
 241   MVE_VMINAV,
 242   MVE_VMLA,
 243   MVE_VMUL_FP_T1,
 244   MVE_VMUL_FP_T2,
 245   MVE_VMUL_VEC_T1,
 246   MVE_VMUL_VEC_T2,
 247   MVE_VMULH,
 248   MVE_VRMULH,
 249   MVE_VNEG_FP,
 250   MVE_VNEG_VEC,
 251   MVE_VPNOT,
 252   MVE_VPSEL,
 253   MVE_VQABS,
 254   MVE_VQADD_T1,
 255   MVE_VQADD_T2,
 256   MVE_VQSUB_T1,
 257   MVE_VQSUB_T2,
 258   MVE_VQNEG,
 259   MVE_VREV16,
 260   MVE_VREV32,
 261   MVE_VREV64,
 262   MVE_LSLL,
 263   MVE_LSLLI,
 264   MVE_LSRL,
 265   MVE_ASRL,
 266   MVE_ASRLI,
 267   MVE_SQRSHRL,
 268   MVE_SQRSHR,
 269   MVE_UQRSHL,
 270   MVE_UQRSHLL,
 271   MVE_UQSHL,
 272   MVE_UQSHLL,
 273   MVE_URSHRL,
 274   MVE_URSHR,
 275   MVE_SRSHRL,
 276   MVE_SRSHR,
 277   MVE_SQSHLL,
 278   MVE_SQSHL,
 279   MVE_CINC,
 280   MVE_CINV,
 281   MVE_CNEG,
 282   MVE_CSINC,
 283   MVE_CSINV,
 284   MVE_CSET,
 285   MVE_CSETM,
 286   MVE_CSNEG,
 287   MVE_CSEL,
 288   MVE_NONE
 289 };
 290
 291 enum mve_unpredictable
 292 {
 293   UNPRED_IT_BLOCK,              /* Unpredictable because mve insn in it block.
 294                                  */
 295   UNPRED_FCA_0_FCB_1,           /* Unpredictable because fcA = 0 and
 296                                    fcB = 1 (vpt).  */
 297   UNPRED_R13,                   /* Unpredictable because r13 (sp) or
 298                                    r15 (sp) used.  */
 299   UNPRED_R15,                   /* Unpredictable because r15 (pc) is used.  */
 300   UNPRED_Q_GT_4,                /* Unpredictable because
 301                                    vec reg start > 4 (vld4/st4).  */
 302   UNPRED_Q_GT_6,                /* Unpredictable because
 303                                    vec reg start > 6 (vld2/st2).  */
 304   UNPRED_R13_AND_WB,            /* Unpredictable becase gp reg = r13
 305                                    and WB bit = 1.  */
 306   UNPRED_Q_REGS_EQUAL,          /* Unpredictable because vector registers are
 307                                    equal.  */
 308   UNPRED_OS,                    /* Unpredictable because offset scaled == 1.  */
 309   UNPRED_GP_REGS_EQUAL,         /* Unpredictable because gp registers are the
 310                                    same.  */
 311   UNPRED_Q_REGS_EQ_AND_SIZE_1,  /* Unpredictable because q regs equal and
 312                                    size = 1.  */
 313   UNPRED_Q_REGS_EQ_AND_SIZE_2,  /* Unpredictable because q regs equal and
 314                                    size = 2.  */
 315   UNPRED_NONE                   /* No unpredictable behavior.  */
 316 };
 317
 318 enum mve_undefined
 319 {
 320   UNDEF_SIZE,                   /* undefined size.  */
 321   UNDEF_SIZE_0,                 /* undefined because size == 0.  */
 322   UNDEF_SIZE_2,                 /* undefined because size == 2.  */
 323   UNDEF_SIZE_3,                 /* undefined because size == 3.  */
 324   UNDEF_SIZE_LE_1,              /* undefined because size <= 1.  */
 325   UNDEF_SIZE_NOT_0,             /* undefined because size != 0.  */
 326   UNDEF_SIZE_NOT_2,             /* undefined because size != 2.  */
 327   UNDEF_SIZE_NOT_3,             /* undefined because size != 3.  */
 328   UNDEF_NOT_UNS_SIZE_0,         /* undefined because U == 0 and
 329                                    size == 0.  */
 330   UNDEF_NOT_UNS_SIZE_1,         /* undefined because U == 0 and
 331                                    size == 1.  */
 332   UNDEF_NOT_UNSIGNED,           /* undefined because U == 0.  */
 333   UNDEF_VCVT_IMM6,              /* imm6 < 32.  */
 334   UNDEF_VCVT_FSI_IMM6,          /* fsi = 0 and 32 >= imm6 <= 47.  */
 335   UNDEF_BAD_OP1_OP2,            /* undefined with op2 = 2 and
 336                                    op1 == (0 or 1).  */
 337   UNDEF_BAD_U_OP1_OP2,          /* undefined with U = 1 and
 338                                    op2 == 0 and op1 == (0 or 1).  */
 339   UNDEF_OP_0_BAD_CMODE,         /* undefined because op == 0 and cmode
 340                                    in {0xx1, x0x1}.  */
 341   UNDEF_XCHG_UNS,               /* undefined because X == 1 and U == 1.  */
 342   UNDEF_NONE                    /* no undefined behavior.  */
 343 };
 344
 345 struct opcode32
 346 {
 347   arm_feature_set arch;         /* Architecture defining this insn.  */
 348   unsigned long value;          /* If arch is 0 then value is a sentinel.  */
 349   unsigned long mask;           /* Recognise insn if (op & mask) == value.  */
 350   const char *  assembler;      /* How to disassemble this insn.  */
 351 };
 352
 353 struct cdeopcode32
 354 {
 355   arm_feature_set arch;         /* Architecture defining this insn.  */
 356   uint8_t coproc_shift;         /* coproc is this far into op.  */
 357   uint16_t coproc_mask;         /* Length of coproc field in op.  */
 358   unsigned long value;          /* If arch is 0 then value is a sentinel.  */
 359   unsigned long mask;           /* Recognise insn if (op & mask) == value.  */
 360   const char *  assembler;      /* How to disassemble this insn.  */
 361 };
 362
 363 /* MVE opcodes.  */
 364
 365 struct mopcode32
 366 {
 367   arm_feature_set arch;         /* Architecture defining this insn.  */
 368   enum mve_instructions mve_op;  /* Specific mve instruction for faster
 369                                     decoding.  */
 370   unsigned long value;          /* If arch is 0 then value is a sentinel.  */
 371   unsigned long mask;           /* Recognise insn if (op & mask) == value.  */
 372   const char *  assembler;      /* How to disassemble this insn.  */
 373 };
 374
 375 enum isa {
 376   ANY,
 377   T32,
 378   ARM
 379 };
 380
 381
 382 /* Shared (between Arm and Thumb mode) opcode.  */
 383 struct sopcode32
 384 {
 385   enum isa isa;                 /* Execution mode instruction availability.  */
 386   arm_feature_set arch;         /* Architecture defining this insn.  */
 387   unsigned long value;          /* If arch is 0 then value is a sentinel.  */
 388   unsigned long mask;           /* Recognise insn if (op & mask) == value.  */
 389   const char *  assembler;      /* How to disassemble this insn.  */
 390 };
 391
 392 struct opcode16
 393 {
 394   arm_feature_set arch;         /* Architecture defining this insn.  */
 395   unsigned short value, mask;   /* Recognise insn if (op & mask) == value.  */
 396   const char *assembler;        /* How to disassemble this insn.  */
 397 };
 398
 399 /* print_insn_coprocessor recognizes the following format control codes:
 400
 401    %%                   %
 402
 403    %c                   print condition code (always bits 28-31 in ARM mode)
 404    %b                   print condition code allowing cp_num == 9
 405    %q                   print shifter argument
 406    %u                   print condition code (unconditional in ARM mode,
 407                           UNPREDICTABLE if not AL in Thumb)
 408    %A                   print address for ldc/stc/ldf/stf instruction
 409    %B                   print vstm/vldm register list
 410    %C                   print vscclrm register list
 411    %I                   print cirrus signed shift immediate: bits 0..3|4..6
 412    %J                   print register for VLDR instruction
 413    %K                   print address for VLDR instruction
 414    %F                   print the COUNT field of a LFM/SFM instruction.
 415    %P                   print floating point precision in arithmetic insn
 416    %Q                   print floating point precision in ldf/stf insn
 417    %R                   print floating point rounding mode
 418
 419    %<bitfield>c         print as a condition code (for vsel)
 420    %<bitfield>r         print as an ARM register
 421    %<bitfield>R         as %<>r but r15 is UNPREDICTABLE
 422    %<bitfield>ru        as %<>r but each u register must be unique.
 423    %<bitfield>d         print the bitfield in decimal
 424    %<bitfield>k         print immediate for VFPv3 conversion instruction
 425    %<bitfield>x         print the bitfield in hex
 426    %<bitfield>X         print the bitfield as 1 hex digit without leading "0x"
 427    %<bitfield>f         print a floating point constant if >7 else a
 428                         floating point register
 429    %<bitfield>w         print as an iWMMXt width field - [bhwd]ss/us
 430    %<bitfield>g         print as an iWMMXt 64-bit register
 431    %<bitfield>G         print as an iWMMXt general purpose or control register
 432    %<bitfield>D         print as a NEON D register
 433    %<bitfield>Q         print as a NEON Q register
 434    %<bitfield>V         print as a NEON D or Q register
 435    %<bitfield>E         print a quarter-float immediate value
 436
 437    %y<code>             print a single precision VFP reg.
 438                           Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
 439    %z<code>             print a double precision VFP reg
 440                           Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
 441
 442    %<bitfield>'c        print specified char iff bitfield is all ones
 443    %<bitfield>`c        print specified char iff bitfield is all zeroes
 444    %<bitfield>?ab...    select from array of values in big endian order
 445
 446    %L                   print as an iWMMXt N/M width field.
 447    %Z                   print the Immediate of a WSHUFH instruction.
 448    %l                   like 'A' except use byte offsets for 'B' & 'H'
 449                         versions.
 450    %i                   print 5-bit immediate in bits 8,3..0
 451                         (print "32" when 0)
 452    %r                   print register offset address for wldt/wstr instruction.  */
 453
 454 enum opcode_sentinel_enum
 455 {
 456   SENTINEL_IWMMXT_START = 1,
 457   SENTINEL_IWMMXT_END,
 458   SENTINEL_GENERIC_START
 459 } opcode_sentinels;
 460
 461 #define UNDEFINED_INSTRUCTION      "\t\t; <UNDEFINED> instruction: %0-31x"
 462 #define UNKNOWN_INSTRUCTION_32BIT  "\t\t; <UNDEFINED> instruction: %08x"
 463 #define UNKNOWN_INSTRUCTION_16BIT  "\t\t; <UNDEFINED> instruction: %04x"
 464 #define UNPREDICTABLE_INSTRUCTION  "\t; <UNPREDICTABLE>"
 465
 466 /* Common coprocessor opcodes shared between Arm and Thumb-2.  */
 467
 468 /* print_insn_cde recognizes the following format control codes:
 469
 470    %%                   %
 471
 472    %a                   print 'a' iff bit 28 is 1
 473    %p                   print bits 8-10 as coprocessor
 474    %<bitfield>d         print as decimal
 475    %<bitfield>r         print as an ARM register
 476    %<bitfield>n         print as an ARM register but r15 is APSR_nzcv
 477    %<bitfield>T         print as an ARM register + 1
 478    %<bitfield>R         as %r but r13 is UNPREDICTABLE
 479    %<bitfield>S         as %r but rX where X > 10 is UNPREDICTABLE
 480    %j                   print immediate taken from bits (16..21,7,0..5)
 481    %k                   print immediate taken from bits (20..21,7,0..5).
 482    %l                   print immediate taken from bits (20..22,7,4..5).  */
 483
 484 /* At the moment there is only one valid position for the coprocessor number,
 485    and hence that's encoded in the macro below.  */
 486 #define CDE_OPCODE(ARCH, VALUE, MASK, ASM) \
 487   { ARCH, 8, 7, VALUE, MASK, ASM }
 488 static const struct cdeopcode32 cde_opcodes[] =
 489 {
 490   /* Custom Datapath Extension instructions.  */
 491   CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
 492               0xee000000, 0xefc00840,
 493               "cx1%a\t%p, %12-15n, #%0-5,7,16-21d"),
 494   CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
 495               0xee000040, 0xefc00840,
 496               "cx1d%a\t%p, %12-15S, %12-15T, #%0-5,7,16-21d"),
 497
 498   CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
 499               0xee400000, 0xefc00840,
 500               "cx2%a\t%p, %12-15n, %16-19n, #%0-5,7,20-21d"),
 501   CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
 502               0xee400040, 0xefc00840,
 503               "cx2d%a\t%p, %12-15S, %12-15T, %16-19n, #%0-5,7,20-21d"),
 504
 505   CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
 506               0xee800000, 0xef800840,
 507               "cx3%a\t%p, %0-3n, %16-19n, %12-15n, #%4-5,7,20-22d"),
 508   CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
 509               0xee800040, 0xef800840,
 510              "cx3d%a\t%p, %0-3S, %0-3T, %16-19n, %12-15n, #%4-5,7,20-22d"),
 511
 512   CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
 513               0xec200000, 0xeeb00840,
 514               "vcx1%a\t%p, %12-15,22V, #%0-5,7,16-19d"),
 515   CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
 516               0xec200040, 0xeeb00840,
 517               "vcx1%a\t%p, %12-15,22V, #%0-5,7,16-19,24d"),
 518
 519   CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
 520               0xec300000, 0xeeb00840,
 521               "vcx2%a\t%p, %12-15,22V, %0-3,5V, #%4,7,16-19d"),
 522   CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
 523               0xec300040, 0xeeb00840,
 524               "vcx2%a\t%p, %12-15,22V, %0-3,5V, #%4,7,16-19,24d"),
 525
 526   CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
 527               0xec800000, 0xee800840,
 528               "vcx3%a\t%p, %12-15,22V, %16-19,7V, %0-3,5V, #%4,20-21d"),
 529   CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
 530               0xec800040, 0xee800840,
 531               "vcx3%a\t%p, %12-15,22V, %16-19,7V, %0-3,5V, #%4,20-21,24d"),
 532
 533   CDE_OPCODE (ARM_FEATURE_CORE_LOW (0), 0, 0, 0)
 534
 535 };
 536
 537 static const struct sopcode32 coprocessor_opcodes[] =
 538 {
 539   /* XScale instructions.  */
 540   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 541     0x0e200010, 0x0fff0ff0,
 542     "mia%c\tacc0, %0-3r, %12-15r"},
 543   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 544     0x0e280010, 0x0fff0ff0,
 545     "miaph%c\tacc0, %0-3r, %12-15r"},
 546   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 547     0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
 548   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 549     0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
 550   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 551     0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
 552
 553   /* Intel Wireless MMX technology instructions.  */
 554   {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
 555   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
 556     0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
 557   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 558     0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
 559   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 560     0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
 561   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 562     0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
 563   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 564     0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
 565   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 566     0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
 567   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 568     0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
 569   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 570     0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
 571   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 572     0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
 573   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 574     0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
 575   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 576     0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
 577   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 578     0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
 579   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 580     0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
 581   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 582     0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
 583   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 584     0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
 585   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 586     0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
 587   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 588     0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
 589   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 590     0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
 591   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 592     0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
 593   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 594     0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
 595   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 596     0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
 597   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 598     0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
 599   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 600     0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
 601   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 602     0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
 603   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 604     0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
 605   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 606     0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 607   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 608     0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 609   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 610     0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
 611   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 612     0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
 613   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 614     0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
 615   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 616     0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
 617   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 618     0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
 619   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 620     0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
 621   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 622     0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 623   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 624     0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
 625   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 626     0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
 627   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 628     0x0e800120, 0x0f800ff0,
 629     "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
 630   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 631     0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 632   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 633     0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
 634   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 635     0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
 636   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 637     0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
 638   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 639     0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
 640   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 641     0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
 642   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 643     0x0e8000a0, 0x0f800ff0,
 644     "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
 645   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 646     0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
 647   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 648     0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
 649   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 650     0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
 651   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 652     0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
 653   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 654     0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
 655   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 656     0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 657   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 658     0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
 659   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 660     0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
 661   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 662     0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
 663   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 664     0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
 665   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 666     0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
 667   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 668     0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
 669   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 670     0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
 671   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 672     0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
 673   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 674     0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
 675   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 676     0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
 677   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 678     0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
 679   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 680     0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
 681   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 682     0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
 683   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 684     0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
 685   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 686     0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
 687   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 688     0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
 689   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 690     0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
 691   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 692     0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 693   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 694     0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
 695   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 696     0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
 697   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 698     0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
 699   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 700     0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
 701   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 702     0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 703   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 704     0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 705   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 706     0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
 707   {ANY, ARM_FEATURE_CORE_LOW (0),
 708     SENTINEL_IWMMXT_END, 0, "" },
 709
 710   /* Floating point coprocessor (FPA) instructions.  */
 711   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 712     0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 713   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 714     0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 715   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 716     0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 717   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 718     0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 719   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 720     0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 721   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 722     0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 723   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 724     0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
 725   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 726     0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
 727   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 728     0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 729   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 730     0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
 731   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 732     0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
 733   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 734     0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
 735   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 736     0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
 737   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 738     0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
 739   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 740     0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
 741   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 742     0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
 743   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 744     0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
 745   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 746     0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
 747   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 748     0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
 749   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 750     0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
 751   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 752     0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
 753   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 754     0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
 755   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 756     0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
 757   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 758     0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
 759   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 760     0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
 761   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 762     0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
 763   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 764     0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
 765   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 766     0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
 767   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 768     0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
 769   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 770     0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
 771   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 772     0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
 773   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 774     0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
 775   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 776     0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
 777   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 778     0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
 779   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 780     0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
 781   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 782     0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
 783   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 784     0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
 785   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 786     0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
 787   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 788     0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
 789   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 790     0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
 791   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 792     0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
 793   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
 794     0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
 795   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
 796     0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
 797
 798   /* Armv8.1-M Mainline instructions.  */
 799   {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
 800     0xec9f0b00, 0xffbf0f01, "vscclrm%c\t%C"},
 801   {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
 802     0xec9f0a00, 0xffbf0f00, "vscclrm%c\t%C"},
 803
 804   /* ARMv8-M Mainline Security Extensions instructions.  */
 805   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
 806     0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
 807   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
 808     0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
 809
 810   /* Register load/store.  */
 811   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 812     0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
 813   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 814     0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
 815   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 816     0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
 817   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 818     0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
 819   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 820     0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
 821   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 822     0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
 823   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 824     0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
 825   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 826     0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
 827   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 828     0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
 829   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 830     0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
 831   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 832     0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
 833   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 834     0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
 835   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 836     0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
 837   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 838     0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
 839   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 840     0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
 841   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 842     0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
 843   {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
 844     0xec100f80, 0xfe101f80, "vldr%c\t%J, %K"},
 845   {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
 846     0xec000f80, 0xfe101f80, "vstr%c\t%J, %K"},
 847
 848   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 849     0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
 850   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 851     0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
 852   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 853     0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
 854   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 855     0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
 856
 857   /* Data transfer between ARM and NEON registers.  */
 858   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 859     0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
 860   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 861     0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
 862   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 863     0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
 864   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 865     0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
 866   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 867     0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
 868   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 869     0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
 870   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 871     0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
 872   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 873     0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
 874   /* Half-precision conversion instructions.  */
 875   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 876     0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
 877   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 878     0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
 879   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
 880     0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
 881   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
 882     0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
 883
 884   /* Floating point coprocessor (VFP) instructions.  */
 885   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 886     0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
 887   {ANY, ARM_FEATURE (0, ARM_EXT2_V8_1M_MAIN, FPU_VFP_EXT_V1xD),
 888     0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
 889   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
 890     0x0ee20a10, 0x0fff0fff, "vmsr%c\tfpscr_nzcvqc, %12-15r"},
 891   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 892     0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
 893   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 894     0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
 895   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 896     0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"},
 897   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 898     0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
 899   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 900     0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
 901   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 902     0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
 903   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
 904     0x0eec0a10, 0x0fff0fff, "vmsr%c\tvpr, %12-15r"},
 905   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
 906     0x0eed0a10, 0x0fff0fff, "vmsr%c\tp0, %12-15r"},
 907   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
 908     0x0eee0a10, 0x0fff0fff, "vmsr%c\tfpcxt_ns, %12-15r"},
 909   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
 910     0x0eef0a10, 0x0fff0fff, "vmsr%c\tfpcxt_s, %12-15r"},
 911   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 912     0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
 913   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 914     0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
 915   {ANY, ARM_FEATURE (0, ARM_EXT2_V8_1M_MAIN, FPU_VFP_EXT_V1xD),
 916     0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
 917   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
 918     0x0ef20a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr_nzcvqc"},
 919   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 920     0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"},
 921   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 922     0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
 923   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 924     0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
 925   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 926     0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
 927   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 928     0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
 929   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 930     0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
 931   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
 932     0x0efc0a10, 0x0fff0fff, "vmrs%c\t%12-15r, vpr"},
 933   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
 934     0x0efd0a10, 0x0fff0fff, "vmrs%c\t%12-15r, p0"},
 935   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
 936     0x0efe0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpcxt_ns"},
 937   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
 938     0x0eff0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpcxt_s"},
 939   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 940     0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
 941   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 942     0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
 943   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 944     0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
 945   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 946     0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
 947   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 948     0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
 949   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 950     0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
 951   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 952     0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
 953   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 954     0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
 955   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 956     0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
 957   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 958     0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
 959   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 960     0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
 961   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 962     0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
 963   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 964     0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
 965   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 966     0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
 967   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 968     0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
 969   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 970     0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
 971   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 972     0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
 973   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 974     0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
 975   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 976     0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
 977   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 978     0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
 979   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 980     0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
 981   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 982     0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
 983   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
 984     0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
 985   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
 986     0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
 987   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 988     0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
 989   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 990     0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
 991   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
 992     0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
 993   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
 994     0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
 995   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 996     0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
 997   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
 998     0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
 999   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
1000     0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
1001   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
1002     0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
1003   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
1004     0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
1005   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
1006     0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
1007   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
1008     0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
1009   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
1010     0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
1011   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
1012     0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
1013   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
1014     0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
1015   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
1016     0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
1017   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
1018     0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
1019   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
1020     0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
1021   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
1022     0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
1023   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
1024     0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
1025   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
1026     0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
1027   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
1028     0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
1029   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
1030     0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
1031   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
1032     0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
1033   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
1034     0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
1035   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
1036     0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
1037   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
1038     0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
1039   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
1040     0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
1041   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
1042     0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
1043
1044   /* Cirrus coprocessor instructions.  */
1045   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1046     0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
1047   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1048     0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
1049   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1050     0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
1051   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1052     0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
1053   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1054     0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
1055   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1056     0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
1057   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1058     0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
1059   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1060     0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
1061   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1062     0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
1063   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1064     0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
1065   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1066     0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
1067   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1068     0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
1069   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1070     0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
1071   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1072     0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
1073   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1074     0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
1075   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1076     0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
1077   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1078     0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
1079   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1080     0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
1081   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1082     0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
1083   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1084     0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
1085   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1086     0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
1087   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1088     0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
1089   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1090     0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
1091   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1092     0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
1093   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1094     0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
1095   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1096     0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
1097   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1098     0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
1099   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1100     0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
1101   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1102     0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
1103   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1104     0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
1105   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1106     0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
1107   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1108     0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
1109   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1110     0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
1111   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1112     0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
1113   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1114     0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
1115   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1116     0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
1117   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1118     0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
1119   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1120     0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
1121   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1122     0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
1123   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1124     0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
1125   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1126     0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
1127   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1128     0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
1129   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1130     0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
1131   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1132     0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
1133   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1134     0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
1135   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1136     0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
1137   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1138     0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
1139   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1140     0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
1141   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1142     0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
1143   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1144     0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
1145   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1146     0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
1147   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1148     0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
1149   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1150     0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
1151   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1152     0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
1153   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1154     0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
1155   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1156     0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
1157   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1158     0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
1159   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1160     0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
1161   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1162     0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
1163   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1164     0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
1165   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1166     0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
1167   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1168     0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
1169   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1170     0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
1171   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1172     0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
1173   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1174     0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
1175   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1176     0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
1177   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1178     0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
1179   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1180     0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
1181   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1182     0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
1183   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1184     0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
1185   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1186     0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
1187   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1188     0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
1189   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1190     0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1191   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1192     0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
1193   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1194     0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1195   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1196     0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
1197   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1198     0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1199   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1200     0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
1201   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1202     0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1203   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1204     0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1205   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1206     0x0e000600, 0x0ff00f10,
1207     "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1208   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1209     0x0e100600, 0x0ff00f10,
1210     "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1211   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1212     0x0e200600, 0x0ff00f10,
1213     "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
1214   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1215     0x0e300600, 0x0ff00f10,
1216     "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
1217
1218   /* VFP Fused multiply add instructions.  */
1219   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1220     0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
1221   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1222     0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
1223   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1224     0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
1225   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1226     0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
1227   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1228     0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
1229   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1230     0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
1231   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1232     0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
1233   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1234     0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
1235
1236   /* FP v5.  */
1237   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1238     0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
1239   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1240     0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
1241   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1242     0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
1243   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1244     0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
1245   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1246     0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
1247   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1248     0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
1249   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1250     0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
1251   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1252     0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
1253   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1254     0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
1255   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1256     0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
1257   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1258     0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
1259   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1260     0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
1261
1262   {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
1263   /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8.  */
1264   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1265     0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
1266   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1267     0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
1268   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1269     0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
1270   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1271     0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
1272   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1273     0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
1274   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1275     0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
1276   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1277     0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
1278   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1279     0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"},
1280   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1281     0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
1282   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1283     0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"},
1284
1285   /* BFloat16 instructions.  */
1286   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1287     0x0eb30940, 0x0fbf0f50, "vcvt%7?tb%b.bf16.f32\t%y1, %y0"},
1288
1289   /* Dot Product instructions in the space of coprocessor 13.  */
1290   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
1291     0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
1292   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
1293     0xfe200d00, 0xff200f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"},
1294
1295   /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8.  */
1296   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1297     0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
1298   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1299     0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
1300   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1301     0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
1302   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1303     0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
1304   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1305     0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
1306   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1307     0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
1308   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1309     0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
1310   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1311     0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
1312
1313   /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
1314      cp_num: bit <11:8> == 0b1001.
1315      cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE.  */
1316   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1317     0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
1318   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1319     0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
1320   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1321     0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
1322   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1323     0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
1324   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1325     0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
1326   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1327     0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
1328   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1329     0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
1330   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1331     0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
1332   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1333     0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
1334   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1335     0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
1336   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1337     0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
1338   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1339     0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
1340   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1341     0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
1342   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1343     0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
1344   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1345     0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
1346   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1347     0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
1348   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1349     0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
1350   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1351     0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
1352   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1353     0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
1354   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1355     0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
1356   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1357     0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
1358   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1359     0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
1360   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1361     0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
1362   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1363     0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
1364   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1365     0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
1366   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1367     0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
1368   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1369     0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
1370   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1371     0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
1372   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1373     0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
1374   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1375     0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
1376   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1377     0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
1378   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1379     0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
1380   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1381     0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
1382   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1383     0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
1384   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1385     0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
1386
1387   /* ARMv8.3 javascript conversion instruction.  */
1388   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1389     0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
1390
1391   {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
1392 };
1393
1394 /* Generic coprocessor instructions.  These are only matched if a more specific
1395    SIMD or co-processor instruction does not match first.  */
1396
1397 static const struct sopcode32 generic_coprocessor_opcodes[] =
1398 {
1399   /* Generic coprocessor instructions.  */
1400   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1401     0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
1402   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1403     0x0c500000, 0x0ff00000,
1404     "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
1405   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1406     0x0e000000, 0x0f000010,
1407     "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
1408   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1409     0x0e10f010, 0x0f10f010,
1410     "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
1411   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1412     0x0e100010, 0x0f100010,
1413     "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1414   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1415     0x0e000010, 0x0f100010,
1416     "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
1417   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1418     0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
1419   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1420     0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
1421
1422   /* V6 coprocessor instructions.  */
1423   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1424     0xfc500000, 0xfff00000,
1425     "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
1426   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1427     0xfc400000, 0xfff00000,
1428     "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
1429
1430   /* V5 coprocessor instructions.  */
1431   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1432     0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
1433   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1434     0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
1435   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1436     0xfe000000, 0xff000010,
1437     "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
1438   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1439     0xfe000010, 0xff100010,
1440     "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
1441   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1442     0xfe100010, 0xff100010,
1443     "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1444
1445   {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
1446 };
1447
1448 /* Neon opcode table:  This does not encode the top byte -- that is
1449    checked by the print_insn_neon routine, as it depends on whether we are
1450    doing thumb32 or arm32 disassembly.  */
1451
1452 /* print_insn_neon recognizes the following format control codes:
1453
1454    %%                   %
1455
1456    %c                   print condition code
1457    %u                   print condition code (unconditional in ARM mode,
1458                           UNPREDICTABLE if not AL in Thumb)
1459    %A                   print v{st,ld}[1234] operands
1460    %B                   print v{st,ld}[1234] any one operands
1461    %C                   print v{st,ld}[1234] single->all operands
1462    %D                   print scalar
1463    %E                   print vmov, vmvn, vorr, vbic encoded constant
1464    %F                   print vtbl,vtbx register list
1465
1466    %<bitfield>r         print as an ARM register
1467    %<bitfield>d         print the bitfield in decimal
1468    %<bitfield>e         print the 2^N - bitfield in decimal
1469    %<bitfield>D         print as a NEON D register
1470    %<bitfield>Q         print as a NEON Q register
1471    %<bitfield>R         print as a NEON D or Q register
1472    %<bitfield>Sn        print byte scaled width limited by n
1473    %<bitfield>Tn        print short scaled width limited by n
1474    %<bitfield>Un        print long scaled width limited by n
1475
1476    %<bitfield>'c        print specified char iff bitfield is all ones
1477    %<bitfield>`c        print specified char iff bitfield is all zeroes
1478    %<bitfield>?ab...    select from array of values in big endian order.  */
1479
1480 static const struct opcode32 neon_opcodes[] =
1481 {
1482   /* Extract.  */
1483   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1484     0xf2b00840, 0xffb00850,
1485     "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1486   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1487     0xf2b00000, 0xffb00810,
1488     "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1489
1490   /* Data transfer between ARM and NEON registers.  */
1491   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1492     0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
1493   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1494     0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
1495   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1496     0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
1497   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1498     0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
1499   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1500     0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
1501   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1502     0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
1503
1504   /* Move data element to all lanes.  */
1505   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1506     0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
1507   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1508     0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
1509   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1510     0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
1511
1512   /* Table lookup.  */
1513   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1514     0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1515   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1516     0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1517
1518   /* Half-precision conversions.  */
1519   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1520     0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1521   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1522     0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
1523
1524   /* NEON fused multiply add instructions.  */
1525   {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
1526     0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1527   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1528     0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1529   {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
1530     0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1531   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1532     0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1533
1534   /* BFloat16 instructions.  */
1535   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1536     0xfc000d00, 0xffb00f10, "vdot.bf16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1537   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1538     0xfe000d00, 0xffb00f10, "vdot.bf16\t%12-15,22R, %16-19,7R, d%0-3d[%5d]"},
1539   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1540     0xfc000c40, 0xffb00f50, "vmmla.bf16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1541   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1542     0xf3b60640, 0xffbf0fd0, "vcvt%c.bf16.f32\t%12-15,22D, %0-3,5Q"},
1543   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1544     0xfc300810, 0xffb00f10, "vfma%6?tb.bf16\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1545   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1546     0xfe300810, 0xffb00f10, "vfma%6?tb.bf16\t%12-15,22Q, %16-19,7Q, %0-2D[%3,5d]"},
1547
1548   /* Matrix Multiply instructions.  */
1549   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1550     0xfc200c40, 0xffb00f50, "vsmmla.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1551   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1552     0xfc200c50, 0xffb00f50, "vummla.u8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1553   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1554     0xfca00c40, 0xffb00f50, "vusmmla.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1555   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1556     0xfca00d00, 0xffb00f10, "vusdot.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1557   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1558     0xfe800d00, 0xffb00f10, "vusdot.s8\t%12-15,22R, %16-19,7R, d%0-3d[%5d]"},
1559   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1560     0xfe800d10, 0xffb00f10, "vsudot.u8\t%12-15,22R, %16-19,7R, d%0-3d[%5d]"},
1561
1562   /* Two registers, miscellaneous.  */
1563   {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1564     0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
1565   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1566     0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
1567   {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1568     0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
1569   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1570     0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
1571   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1572     0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1573   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1574     0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1575   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1576     0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1577   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1578     0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1579   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1580     0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1581   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1582     0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1583   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1584     0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1585   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1586     0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1587   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1588     0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1589   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1590     0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1591   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1592     0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1593   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1594     0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1595   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1596     0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1597   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1598     0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1599   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1600     0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1601   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1602     0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1603   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1604     0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1605   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1606     0xf3b20300, 0xffb30fd0,
1607     "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1608   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1609     0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1610   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1611     0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1612   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1613     0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1614   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1615     0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1616   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1617     0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1618   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1619     0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1620   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1621     0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1622   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1623     0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1624   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1625     0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1626   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1627     0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1628   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1629     0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1630   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1631     0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1632   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1633     0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1634   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1635     0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1636   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1637     0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1638   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1639     0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1640   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1641     0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1642   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1643     0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1644   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1645     0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1646   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1647     0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1648   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1649     0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1650   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1651     0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1652   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1653     0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1654   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1655     0xf3bb0600, 0xffbf0e10,
1656     "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
1657   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1658     0xf3b70600, 0xffbf0e10,
1659     "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
1660
1661   /* Three registers of the same length.  */
1662   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1663     0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1664   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1665     0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1666   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1667     0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1668   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1669     0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1670   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1671     0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1672   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1673     0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1674   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1675     0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1676   {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1677     0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1678   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1679     0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1680   {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1681     0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1682   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1683     0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1684   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1685     0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1686   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1687     0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1688   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1689     0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1690   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1691     0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1692   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1693     0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1694   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1695     0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1696   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1697     0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1698   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1699     0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1700   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1701     0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1702   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1703     0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1704   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1705     0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1706   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1707     0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1708   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1709     0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1710   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1711     0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1712   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1713     0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1714   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1715     0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1716   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1717     0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1718   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1719     0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1720   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1721     0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1722   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1723     0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1724   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1725     0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1726   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1727     0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1728   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1729     0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1730   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1731     0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1732   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1733     0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1734   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1735     0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1736   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1737     0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1738   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1739     0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1740   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1741     0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1742   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1743     0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1744   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1745     0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1746   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1747     0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1748   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1749     0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1750   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1751     0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1752   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1753     0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1754   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1755     0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1756   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1757     0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1758   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1759     0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1760   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1761     0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1762   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1763     0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1764   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1765     0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1766   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1767     0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1768   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1769     0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1770   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1771     0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1772   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1773     0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1774   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1775     0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1776   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1777     0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1778   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1779     0xf2000b00, 0xff800f10,
1780     "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1781   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1782     0xf2000b10, 0xff800f10,
1783     "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1784   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1785     0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1786   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1787     0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1788   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1789     0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1790   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1791     0xf3000b00, 0xff800f10,
1792     "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1793   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1794     0xf2000000, 0xfe800f10,
1795     "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1796   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1797     0xf2000010, 0xfe800f10,
1798     "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1799   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1800     0xf2000100, 0xfe800f10,
1801     "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1802   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1803     0xf2000200, 0xfe800f10,
1804     "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1805   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1806     0xf2000210, 0xfe800f10,
1807     "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1808   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1809     0xf2000300, 0xfe800f10,
1810     "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1811   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1812     0xf2000310, 0xfe800f10,
1813     "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1814   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1815     0xf2000400, 0xfe800f10,
1816     "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1817   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1818     0xf2000410, 0xfe800f10,
1819     "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1820   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1821     0xf2000500, 0xfe800f10,
1822     "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1823   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1824     0xf2000510, 0xfe800f10,
1825     "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1826   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1827     0xf2000600, 0xfe800f10,
1828     "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1829   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1830     0xf2000610, 0xfe800f10,
1831     "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1832   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1833     0xf2000700, 0xfe800f10,
1834     "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1835   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1836     0xf2000710, 0xfe800f10,
1837     "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1838   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1839     0xf2000910, 0xfe800f10,
1840     "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1841   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1842     0xf2000a00, 0xfe800f10,
1843     "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1844   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1845     0xf2000a10, 0xfe800f10,
1846     "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1847   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1848     0xf3000b10, 0xff800f10,
1849     "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1850   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1851     0xf3000c10, 0xff800f10,
1852     "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1853
1854   /* One register and an immediate value.  */
1855   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1856     0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1857   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1858     0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1859   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1860     0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1861   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1862     0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1863   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1864     0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1865   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1866     0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1867   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1868     0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1869   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1870     0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1871   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1872     0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1873   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1874     0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1875   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1876     0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1877   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1878     0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1879   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1880     0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
1881
1882   /* Two registers and a shift amount.  */
1883   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1884     0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1885   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1886     0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1887   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1888     0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1889   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1890     0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1891   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1892     0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1893   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1894     0xf2880950, 0xfeb80fd0,
1895     "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1896   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1897     0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1898   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1899     0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1900   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1901     0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1902   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1903     0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1904   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1905     0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1906   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1907     0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1908   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1909     0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1910   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1911     0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1912   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1913     0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1914   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1915     0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1916   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1917     0xf2900950, 0xfeb00fd0,
1918     "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1919   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1920     0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1921   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1922     0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1923   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1924     0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1925   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1926     0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1927   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1928     0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1929   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1930     0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1931   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1932     0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1933   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1934     0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1935   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1936     0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1937   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1938     0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1939   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1940     0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1941   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1942     0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1943   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1944     0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1945   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1946     0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1947   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1948     0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1949   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1950     0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1951   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1952     0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1953   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1954     0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1955   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1956     0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1957   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1958     0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1959   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1960     0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1961   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1962     0xf2a00950, 0xfea00fd0,
1963     "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1964   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1965     0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1966   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1967     0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1968   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1969     0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1970   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1971     0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1972   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1973     0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1974   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1975     0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1976   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1977     0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1978   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1979     0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1980   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1981     0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1982   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1983     0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1984   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1985     0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1986   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1987     0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1988   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1989     0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1990   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1991     0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1992   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1993     0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1994   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1995     0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1996   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1997     0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1998   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1999     0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
2000   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2001     0xf2a00e10, 0xfea00e90,
2002     "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
2003   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
2004     0xf2a00c10, 0xfea00e90,
2005     "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"},
2006
2007   /* Three registers of different lengths.  */
2008   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
2009     0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2010   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2011     0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2012   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2013     0xf2800400, 0xff800f50,
2014     "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
2015   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2016     0xf2800600, 0xff800f50,
2017     "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
2018   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2019     0xf2800900, 0xff800f50,
2020     "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2021   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2022     0xf2800b00, 0xff800f50,
2023     "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2024   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2025     0xf2800d00, 0xff800f50,
2026     "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2027   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2028     0xf3800400, 0xff800f50,
2029     "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
2030   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2031     0xf3800600, 0xff800f50,
2032     "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
2033   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2034     0xf2800000, 0xfe800f50,
2035     "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2036   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2037     0xf2800100, 0xfe800f50,
2038     "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
2039   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2040     0xf2800200, 0xfe800f50,
2041     "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2042   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2043     0xf2800300, 0xfe800f50,
2044     "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
2045   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2046     0xf2800500, 0xfe800f50,
2047     "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2048   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2049     0xf2800700, 0xfe800f50,
2050     "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2051   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2052     0xf2800800, 0xfe800f50,
2053     "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2054   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2055     0xf2800a00, 0xfe800f50,
2056     "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2057   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2058     0xf2800c00, 0xfe800f50,
2059     "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2060
2061   /* Two registers and a scalar.  */
2062   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2063     0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2064   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2065     0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
2066   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2067     0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
2068   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2069     0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2070   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2071     0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2072   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2073     0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2074   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2075     0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
2076   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2077     0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2078   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2079     0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2080   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2081     0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
2082   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2083     0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
2084   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2085     0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2086   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2087     0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2088   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2089     0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2090   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2091     0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2092   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2093     0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
2094   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2095     0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
2096   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2097     0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2098   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2099     0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
2100   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2101     0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
2102   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2103     0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2104   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2105     0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
2106   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2107     0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
2108   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2109     0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2110   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2111     0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2112   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2113     0xf2800240, 0xfe800f50,
2114     "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2115   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2116     0xf2800640, 0xfe800f50,
2117     "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2118   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2119     0xf2800a40, 0xfe800f50,
2120     "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2121   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
2122     0xf2800e40, 0xff800f50,
2123    "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2124   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
2125     0xf2800f40, 0xff800f50,
2126    "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2127   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
2128     0xf3800e40, 0xff800f50,
2129    "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2130   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
2131     0xf3800f40, 0xff800f50,
2132    "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
2133   },
2134
2135   /* Element and structure load/store.  */
2136   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2137     0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
2138   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2139     0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
2140   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2141     0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
2142   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2143     0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
2144   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2145     0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
2146   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2147     0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2148   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2149     0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2150   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2151     0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
2152   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2153     0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
2154   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2155     0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2156   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2157     0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2158   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2159     0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2160   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2161     0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2162   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2163     0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2164   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2165     0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
2166   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2167     0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
2168   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2169     0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
2170   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2171     0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
2172   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2173     0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
2174
2175   {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
2176 };
2177
2178 /* mve opcode table.  */
2179
2180 /* print_insn_mve recognizes the following format control codes:
2181
2182    %%                   %
2183
2184    %a                   print '+' or '-' or imm offset in vldr[bhwd] and
2185                         vstr[bhwd]
2186    %c                   print condition code
2187    %d                   print addr mode of MVE vldr[bhw] and vstr[bhw]
2188    %u                   print 'U' (unsigned) or 'S' for various mve instructions
2189    %i                   print MVE predicate(s) for vpt and vpst
2190    %j                   print a 5-bit immediate from hw2[14:12,7:6]
2191    %k                   print 48 if the 7th position bit is set else print 64.
2192    %m                   print rounding mode for vcvt and vrint
2193    %n                   print vector comparison code for predicated instruction
2194    %s                   print size for various vcvt instructions
2195    %v                   print vector predicate for instruction in predicated
2196                         block
2197    %o                   print offset scaled for vldr[hwd] and vstr[hwd]
2198    %w                   print writeback mode for MVE v{st,ld}[24]
2199    %B                   print v{st,ld}[24] any one operands
2200    %E                   print vmov, vmvn, vorr, vbic encoded constant
2201    %N                   print generic index for vmov
2202    %T                   print bottom ('b') or top ('t') of source register
2203    %X                   print exchange field in vmla* instructions
2204
2205    %<bitfield>r         print as an ARM register
2206    %<bitfield>d         print the bitfield in decimal
2207    %<bitfield>A         print accumulate or not
2208    %<bitfield>c         print bitfield as a condition code
2209    %<bitfield>C         print bitfield as an inverted condition code
2210    %<bitfield>Q         print as a MVE Q register
2211    %<bitfield>F         print as a MVE S register
2212    %<bitfield>Z         as %<>r but r15 is ZR instead of PC and r13 is
2213                         UNPREDICTABLE
2214
2215    %<bitfield>S         as %<>r but r15 or r13 is UNPREDICTABLE
2216    %<bitfield>s         print size for vector predicate & non VMOV instructions
2217    %<bitfield>I         print carry flag or not
2218    %<bitfield>i         print immediate for vstr/vldr reg +/- imm
2219    %<bitfield>h         print high half of 64-bit destination reg
2220    %<bitfield>k         print immediate for vector conversion instruction
2221    %<bitfield>l         print low half of 64-bit destination reg
2222    %<bitfield>o         print rotate value for vcmul
2223    %<bitfield>u         print immediate value for vddup/vdwdup
2224    %<bitfield>x         print the bitfield in hex.
2225   */
2226
2227 static const struct mopcode32 mve_opcodes[] =
2228 {
2229   /* MVE.  */
2230
2231   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2232    MVE_VPST,
2233    0xfe310f4d, 0xffbf1fff,
2234    "vpst%i"
2235   },
2236
2237   /* Floating point VPT T1.  */
2238   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2239    MVE_VPT_FP_T1,
2240    0xee310f00, 0xefb10f50,
2241    "vpt%i.f%28s\t%n, %17-19Q, %1-3,5Q"},
2242   /* Floating point VPT T2.  */
2243   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2244    MVE_VPT_FP_T2,
2245    0xee310f40, 0xefb10f50,
2246    "vpt%i.f%28s\t%n, %17-19Q, %0-3Z"},
2247
2248   /* Vector VPT T1.  */
2249   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2250    MVE_VPT_VEC_T1,
2251    0xfe010f00, 0xff811f51,
2252    "vpt%i.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2253   /* Vector VPT T2.  */
2254   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2255    MVE_VPT_VEC_T2,
2256    0xfe010f01, 0xff811f51,
2257    "vpt%i.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2258   /* Vector VPT T3.  */
2259   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2260    MVE_VPT_VEC_T3,
2261    0xfe011f00, 0xff811f50,
2262    "vpt%i.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2263   /* Vector VPT T4.  */
2264   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2265    MVE_VPT_VEC_T4,
2266    0xfe010f40, 0xff811f70,
2267    "vpt%i.i%20-21s\t%n, %17-19Q, %0-3Z"},
2268   /* Vector VPT T5.  */
2269   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2270    MVE_VPT_VEC_T5,
2271    0xfe010f60, 0xff811f70,
2272    "vpt%i.u%20-21s\t%n, %17-19Q, %0-3Z"},
2273   /* Vector VPT T6.  */
2274   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2275    MVE_VPT_VEC_T6,
2276    0xfe011f40, 0xff811f50,
2277    "vpt%i.s%20-21s\t%n, %17-19Q, %0-3Z"},
2278
2279   /* Vector VBIC immediate.  */
2280   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2281    MVE_VBIC_IMM,
2282    0xef800070, 0xefb81070,
2283    "vbic%v.i%8-11s\t%13-15,22Q, %E"},
2284
2285   /* Vector VBIC register.  */
2286   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2287    MVE_VBIC_REG,
2288    0xef100150, 0xffb11f51,
2289    "vbic%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2290
2291   /* Vector VABAV.  */
2292   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2293    MVE_VABAV,
2294    0xee800f01, 0xefc10f51,
2295    "vabav%v.%u%20-21s\t%12-15r, %17-19,7Q, %1-3,5Q"},
2296
2297   /* Vector VABD floating point.  */
2298   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2299    MVE_VABD_FP,
2300    0xff200d40, 0xffa11f51,
2301    "vabd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2302
2303   /* Vector VABD.  */
2304   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2305    MVE_VABD_VEC,
2306    0xef000740, 0xef811f51,
2307    "vabd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2308
2309   /* Vector VABS floating point.  */
2310   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2311    MVE_VABS_FP,
2312    0xFFB10740, 0xFFB31FD1,
2313    "vabs%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
2314   /* Vector VABS.  */
2315   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2316    MVE_VABS_VEC,
2317    0xffb10340, 0xffb31fd1,
2318    "vabs%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2319
2320   /* Vector VADD floating point T1.  */
2321   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2322    MVE_VADD_FP_T1,
2323    0xef000d40, 0xffa11f51,
2324    "vadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2325   /* Vector VADD floating point T2.  */
2326   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2327    MVE_VADD_FP_T2,
2328    0xee300f40, 0xefb11f70,
2329    "vadd%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2330   /* Vector VADD T1.  */
2331   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2332    MVE_VADD_VEC_T1,
2333    0xef000840, 0xff811f51,
2334    "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2335   /* Vector VADD T2.  */
2336   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2337    MVE_VADD_VEC_T2,
2338    0xee010f40, 0xff811f70,
2339    "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2340
2341   /* Vector VADDLV.  */
2342   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2343    MVE_VADDLV,
2344    0xee890f00, 0xef8f1fd1,
2345    "vaddlv%5A%v.%u32\t%13-15l, %20-22h, %1-3Q"},
2346
2347   /* Vector VADDV.  */
2348   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2349    MVE_VADDV,
2350    0xeef10f00, 0xeff31fd1,
2351    "vaddv%5A%v.%u%18-19s\t%13-15l, %1-3Q"},
2352
2353   /* Vector VADC.  */
2354   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2355    MVE_VADC,
2356    0xee300f00, 0xffb10f51,
2357    "vadc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2358
2359   /* Vector VAND.  */
2360   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2361    MVE_VAND,
2362    0xef000150, 0xffb11f51,
2363    "vand%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2364
2365   /* Vector VBRSR register.  */
2366   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2367    MVE_VBRSR,
2368    0xfe011e60, 0xff811f70,
2369    "vbrsr%v.%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2370
2371   /* Vector VCADD floating point.  */
2372   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2373    MVE_VCADD_FP,
2374    0xfc800840, 0xfea11f51,
2375    "vcadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%24o"},
2376
2377   /* Vector VCADD.  */
2378   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2379    MVE_VCADD_VEC,
2380    0xfe000f00, 0xff810f51,
2381    "vcadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
2382
2383   /* Vector VCLS.  */
2384   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2385    MVE_VCLS,
2386    0xffb00440, 0xffb31fd1,
2387    "vcls%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2388
2389   /* Vector VCLZ.  */
2390   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2391    MVE_VCLZ,
2392    0xffb004c0, 0xffb31fd1,
2393    "vclz%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2394
2395   /* Vector VCMLA.  */
2396   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2397    MVE_VCMLA_FP,
2398    0xfc200840, 0xfe211f51,
2399    "vcmla%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%23-24o"},
2400
2401   /* Vector VCMP floating point T1.  */
2402   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2403    MVE_VCMP_FP_T1,
2404    0xee310f00, 0xeff1ef50,
2405    "vcmp%v.f%28s\t%n, %17-19Q, %1-3,5Q"},
2406
2407   /* Vector VCMP floating point T2.  */
2408   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2409    MVE_VCMP_FP_T2,
2410    0xee310f40, 0xeff1ef50,
2411    "vcmp%v.f%28s\t%n, %17-19Q, %0-3Z"},
2412
2413   /* Vector VCMP T1.  */
2414   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2415    MVE_VCMP_VEC_T1,
2416    0xfe010f00, 0xffc1ff51,
2417    "vcmp%v.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2418   /* Vector VCMP T2.  */
2419   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2420    MVE_VCMP_VEC_T2,
2421    0xfe010f01, 0xffc1ff51,
2422    "vcmp%v.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2423   /* Vector VCMP T3.  */
2424   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2425    MVE_VCMP_VEC_T3,
2426    0xfe011f00, 0xffc1ff50,
2427    "vcmp%v.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2428   /* Vector VCMP T4.  */
2429   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2430    MVE_VCMP_VEC_T4,
2431    0xfe010f40, 0xffc1ff70,
2432    "vcmp%v.i%20-21s\t%n, %17-19Q, %0-3Z"},
2433   /* Vector VCMP T5.  */
2434   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2435    MVE_VCMP_VEC_T5,
2436    0xfe010f60, 0xffc1ff70,
2437    "vcmp%v.u%20-21s\t%n, %17-19Q, %0-3Z"},
2438   /* Vector VCMP T6.  */
2439   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2440    MVE_VCMP_VEC_T6,
2441    0xfe011f40, 0xffc1ff50,
2442    "vcmp%v.s%20-21s\t%n, %17-19Q, %0-3Z"},
2443
2444   /* Vector VDUP.  */
2445   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2446    MVE_VDUP,
2447    0xeea00b10, 0xffb10f5f,
2448    "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2449
2450   /* Vector VEOR.  */
2451   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2452    MVE_VEOR,
2453    0xff000150, 0xffd11f51,
2454    "veor%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2455
2456   /* Vector VFMA, vector * scalar.  */
2457   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2458    MVE_VFMA_FP_SCALAR,
2459    0xee310e40, 0xefb11f70,
2460    "vfma%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2461
2462   /* Vector VFMA floating point.  */
2463   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2464    MVE_VFMA_FP,
2465    0xef000c50, 0xffa11f51,
2466    "vfma%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2467
2468   /* Vector VFMS floating point.  */
2469   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2470    MVE_VFMS_FP,
2471    0xef200c50, 0xffa11f51,
2472    "vfms%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2473
2474   /* Vector VFMAS, vector * scalar.  */
2475   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2476    MVE_VFMAS_FP_SCALAR,
2477    0xee311e40, 0xefb11f70,
2478    "vfmas%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2479
2480   /* Vector VHADD T1.  */
2481   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2482    MVE_VHADD_T1,
2483    0xef000040, 0xef811f51,
2484    "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2485
2486   /* Vector VHADD T2.  */
2487   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2488    MVE_VHADD_T2,
2489    0xee000f40, 0xef811f70,
2490    "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2491
2492   /* Vector VHSUB T1.  */
2493   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2494    MVE_VHSUB_T1,
2495    0xef000240, 0xef811f51,
2496    "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2497
2498   /* Vector VHSUB T2.  */
2499   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2500    MVE_VHSUB_T2,
2501    0xee001f40, 0xef811f70,
2502    "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2503
2504   /* Vector VCMUL.  */
2505   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2506    MVE_VCMUL_FP,
2507    0xee300e00, 0xefb10f50,
2508    "vcmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%0,12o"},
2509
2510    /* Vector VCTP.  */
2511   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2512    MVE_VCTP,
2513    0xf000e801, 0xffc0ffff,
2514    "vctp%v.%20-21s\t%16-19r"},
2515
2516   /* Vector VDUP.  */
2517   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2518    MVE_VDUP,
2519    0xeea00b10, 0xffb10f5f,
2520    "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2521
2522   /* Vector VRHADD.  */
2523   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2524    MVE_VRHADD,
2525    0xef000140, 0xef811f51,
2526    "vrhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2527
2528   /* Vector VCVT.  */
2529   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2530    MVE_VCVT_FP_FIX_VEC,
2531    0xef800c50, 0xef801cd1,
2532    "vcvt%v.%s\t%13-15,22Q, %1-3,5Q, #%16-21k"},
2533
2534   /* Vector VCVT.  */
2535   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2536    MVE_VCVT_BETWEEN_FP_INT,
2537    0xffb30640, 0xffb31e51,
2538    "vcvt%v.%s\t%13-15,22Q, %1-3,5Q"},
2539
2540   /* Vector VCVT between single and half-precision float, bottom half.  */
2541   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2542    MVE_VCVT_FP_HALF_FP,
2543    0xee3f0e01, 0xefbf1fd1,
2544    "vcvtb%v.%s\t%13-15,22Q, %1-3,5Q"},
2545
2546   /* Vector VCVT between single and half-precision float, top half.  */
2547   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2548    MVE_VCVT_FP_HALF_FP,
2549    0xee3f1e01, 0xefbf1fd1,
2550    "vcvtt%v.%s\t%13-15,22Q, %1-3,5Q"},
2551
2552   /* Vector VCVT.  */
2553   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2554    MVE_VCVT_FROM_FP_TO_INT,
2555    0xffb30040, 0xffb31c51,
2556    "vcvt%m%v.%s\t%13-15,22Q, %1-3,5Q"},
2557
2558   /* Vector VDDUP.  */
2559   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2560    MVE_VDDUP,
2561    0xee011f6e, 0xff811f7e,
2562    "vddup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
2563
2564   /* Vector VDWDUP.  */
2565   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2566    MVE_VDWDUP,
2567    0xee011f60, 0xff811f70,
2568    "vdwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
2569
2570   /* Vector VHCADD.  */
2571   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2572    MVE_VHCADD,
2573    0xee000f00, 0xff810f51,
2574    "vhcadd%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
2575
2576   /* Vector VIWDUP.  */
2577   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2578    MVE_VIWDUP,
2579    0xee010f60, 0xff811f70,
2580    "viwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
2581
2582   /* Vector VIDUP.  */
2583   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2584    MVE_VIDUP,
2585    0xee010f6e, 0xff811f7e,
2586    "vidup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
2587
2588   /* Vector VLD2.  */
2589   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2590    MVE_VLD2,
2591    0xfc901e00, 0xff901e5f,
2592    "vld2%5d.%7-8s\t%B, [%16-19r]%w"},
2593
2594   /* Vector VLD4.  */
2595   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2596    MVE_VLD4,
2597    0xfc901e01, 0xff901e1f,
2598    "vld4%5-6d.%7-8s\t%B, [%16-19r]%w"},
2599
2600   /* Vector VLDRB gather load.  */
2601   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2602    MVE_VLDRB_GATHER_T1,
2603    0xec900e00, 0xefb01e50,
2604    "vldrb%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
2605
2606   /* Vector VLDRH gather load.  */
2607   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2608    MVE_VLDRH_GATHER_T2,
2609    0xec900e10, 0xefb01e50,
2610    "vldrh%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2611
2612   /* Vector VLDRW gather load.  */
2613   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2614    MVE_VLDRW_GATHER_T3,
2615    0xfc900f40, 0xffb01fd0,
2616    "vldrw%v.u32\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2617
2618   /* Vector VLDRD gather load.  */
2619   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2620    MVE_VLDRD_GATHER_T4,
2621    0xec900fd0, 0xefb01fd0,
2622    "vldrd%v.u64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2623
2624   /* Vector VLDRW gather load.  */
2625   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2626    MVE_VLDRW_GATHER_T5,
2627    0xfd101e00, 0xff111f00,
2628    "vldrw%v.u32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2629
2630   /* Vector VLDRD gather load, variant T6.  */
2631   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2632    MVE_VLDRD_GATHER_T6,
2633    0xfd101f00, 0xff111f00,
2634    "vldrd%v.u64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2635
2636   /* Vector VLDRB.  */
2637   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2638    MVE_VLDRB_T1,
2639    0xec100e00, 0xee581e00,
2640    "vldrb%v.%u%7-8s\t%13-15Q, %d"},
2641
2642   /* Vector VLDRH.  */
2643   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2644    MVE_VLDRH_T2,
2645    0xec180e00, 0xee581e00,
2646    "vldrh%v.%u%7-8s\t%13-15Q, %d"},
2647
2648   /* Vector VLDRB unsigned, variant T5.  */
2649   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2650    MVE_VLDRB_T5,
2651    0xec101e00, 0xfe101f80,
2652    "vldrb%v.u8\t%13-15,22Q, %d"},
2653
2654   /* Vector VLDRH unsigned, variant T6.  */
2655   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2656    MVE_VLDRH_T6,
2657    0xec101e80, 0xfe101f80,
2658    "vldrh%v.u16\t%13-15,22Q, %d"},
2659
2660   /* Vector VLDRW unsigned, variant T7.  */
2661   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2662    MVE_VLDRW_T7,
2663    0xec101f00, 0xfe101f80,
2664    "vldrw%v.u32\t%13-15,22Q, %d"},
2665
2666   /* Vector VMAX.  */
2667   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2668    MVE_VMAX,
2669    0xef000640, 0xef811f51,
2670    "vmax%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2671
2672   /* Vector VMAXA.  */
2673   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2674    MVE_VMAXA,
2675    0xee330e81, 0xffb31fd1,
2676    "vmaxa%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2677
2678   /* Vector VMAXNM floating point.  */
2679   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2680    MVE_VMAXNM_FP,
2681    0xff000f50, 0xffa11f51,
2682    "vmaxnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2683
2684   /* Vector VMAXNMA floating point.  */
2685   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2686    MVE_VMAXNMA_FP,
2687    0xee3f0e81, 0xefbf1fd1,
2688    "vmaxnma%v.f%28s\t%13-15,22Q, %1-3,5Q"},
2689
2690   /* Vector VMAXNMV floating point.  */
2691   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2692    MVE_VMAXNMV_FP,
2693    0xeeee0f00, 0xefff0fd1,
2694    "vmaxnmv%v.f%28s\t%12-15r, %1-3,5Q"},
2695
2696   /* Vector VMAXNMAV floating point.  */
2697   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2698    MVE_VMAXNMAV_FP,
2699    0xeeec0f00, 0xefff0fd1,
2700    "vmaxnmav%v.f%28s\t%12-15r, %1-3,5Q"},
2701
2702   /* Vector VMAXV.  */
2703   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2704    MVE_VMAXV,
2705    0xeee20f00, 0xeff30fd1,
2706    "vmaxv%v.%u%18-19s\t%12-15r, %1-3,5Q"},
2707
2708   /* Vector VMAXAV.  */
2709   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2710    MVE_VMAXAV,
2711    0xeee00f00, 0xfff30fd1,
2712    "vmaxav%v.s%18-19s\t%12-15r, %1-3,5Q"},
2713
2714   /* Vector VMIN.  */
2715   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2716    MVE_VMIN,
2717    0xef000650, 0xef811f51,
2718    "vmin%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2719
2720   /* Vector VMINA.  */
2721   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2722    MVE_VMINA,
2723    0xee331e81, 0xffb31fd1,
2724    "vmina%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2725
2726   /* Vector VMINNM floating point.  */
2727   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2728    MVE_VMINNM_FP,
2729    0xff200f50, 0xffa11f51,
2730    "vminnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2731
2732   /* Vector VMINNMA floating point.  */
2733   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2734    MVE_VMINNMA_FP,
2735    0xee3f1e81, 0xefbf1fd1,
2736    "vminnma%v.f%28s\t%13-15,22Q, %1-3,5Q"},
2737
2738   /* Vector VMINNMV floating point.  */
2739   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2740    MVE_VMINNMV_FP,
2741    0xeeee0f80, 0xefff0fd1,
2742    "vminnmv%v.f%28s\t%12-15r, %1-3,5Q"},
2743
2744   /* Vector VMINNMAV floating point.  */
2745   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2746    MVE_VMINNMAV_FP,
2747    0xeeec0f80, 0xefff0fd1,
2748    "vminnmav%v.f%28s\t%12-15r, %1-3,5Q"},
2749
2750   /* Vector VMINV.  */
2751   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2752    MVE_VMINV,
2753    0xeee20f80, 0xeff30fd1,
2754    "vminv%v.%u%18-19s\t%12-15r, %1-3,5Q"},
2755
2756   /* Vector VMINAV.  */
2757   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2758    MVE_VMINAV,
2759    0xeee00f80, 0xfff30fd1,
2760    "vminav%v.s%18-19s\t%12-15r, %1-3,5Q"},
2761
2762   /* Vector VMLA.  */
2763   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2764    MVE_VMLA,
2765    0xee010e40, 0xef811f70,
2766    "vmla%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2767
2768   /* Vector VMLALDAV.  Note must appear before VMLADAV due to instruction
2769      opcode aliasing.  */
2770   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2771    MVE_VMLALDAV,
2772    0xee801e00, 0xef801f51,
2773    "vmlaldav%5Ax%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2774
2775   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2776    MVE_VMLALDAV,
2777    0xee800e00, 0xef801f51,
2778    "vmlalv%5A%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2779
2780   /* Vector VMLAV T1 variant, same as VMLADAV but with X == 0.  */
2781   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2782    MVE_VMLADAV_T1,
2783    0xeef00e00, 0xeff01f51,
2784    "vmlav%5A%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2785
2786   /* Vector VMLAV T2 variant, same as VMLADAV but with X == 0.  */
2787   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2788    MVE_VMLADAV_T2,
2789    0xeef00f00, 0xeff11f51,
2790    "vmlav%5A%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2791
2792   /* Vector VMLADAV T1 variant.  */
2793   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2794    MVE_VMLADAV_T1,
2795    0xeef01e00, 0xeff01f51,
2796    "vmladav%5Ax%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2797
2798   /* Vector VMLADAV T2 variant.  */
2799   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2800    MVE_VMLADAV_T2,
2801    0xeef01f00, 0xeff11f51,
2802    "vmladav%5Ax%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2803
2804   /* Vector VMLAS.  */
2805   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2806    MVE_VMLAS,
2807    0xee011e40, 0xef811f70,
2808    "vmlas%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2809
2810   /* Vector VRMLSLDAVH.  Note must appear before VMLSDAV due to instruction
2811      opcode aliasing.  */
2812   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2813    MVE_VRMLSLDAVH,
2814    0xfe800e01, 0xff810f51,
2815    "vrmlsldavh%5A%X%v.s32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2816
2817   /* Vector VMLSLDAV.  Note must appear before VMLSDAV due to instruction
2818      opcdoe aliasing.  */
2819   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2820    MVE_VMLSLDAV,
2821    0xee800e01, 0xff800f51,
2822    "vmlsldav%5A%X%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2823
2824   /* Vector VMLSDAV T1 Variant.  */
2825   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2826    MVE_VMLSDAV_T1,
2827    0xeef00e01, 0xfff00f51,
2828    "vmlsdav%5A%X%v.s%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2829
2830   /* Vector VMLSDAV T2 Variant.  */
2831   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2832    MVE_VMLSDAV_T2,
2833    0xfef00e01, 0xfff10f51,
2834    "vmlsdav%5A%X%v.s8\t%13-15l, %17-19,7Q, %1-3Q"},
2835
2836   /* Vector VMOV between gpr and half precision register, op == 0.  */
2837   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2838    MVE_VMOV_HFP_TO_GP,
2839    0xee000910, 0xfff00f7f,
2840    "vmov.f16\t%7,16-19F, %12-15r"},
2841
2842   /* Vector VMOV between gpr and half precision register, op == 1.  */
2843   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2844    MVE_VMOV_HFP_TO_GP,
2845    0xee100910, 0xfff00f7f,
2846    "vmov.f16\t%12-15r, %7,16-19F"},
2847
2848   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2849    MVE_VMOV_GP_TO_VEC_LANE,
2850    0xee000b10, 0xff900f1f,
2851    "vmov%c.%5-6,21-22s\t%17-19,7Q[%N], %12-15r"},
2852
2853   /* Vector VORR immediate to vector.
2854      NOTE: MVE_VORR_IMM must appear in the table
2855      before MVE_VMOV_IMM_TO_VEC due to opcode aliasing.  */
2856   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2857    MVE_VORR_IMM,
2858    0xef800050, 0xefb810f0,
2859    "vorr%v.i%8-11s\t%13-15,22Q, %E"},
2860
2861   /* Vector VQSHL T2 Variant.
2862      NOTE: MVE_VQSHL_T2 must appear in the table before
2863      before MVE_VMOV_IMM_TO_VEC due to opcode aliasing.  */
2864   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2865    MVE_VQSHL_T2,
2866    0xef800750, 0xef801fd1,
2867    "vqshl%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2868
2869   /* Vector VQSHLU T3 Variant
2870      NOTE: MVE_VQSHL_T2 must appear in the table before
2871      before MVE_VMOV_IMM_TO_VEC due to opcode aliasing.  */
2872
2873   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2874    MVE_VQSHLU_T3,
2875    0xff800650, 0xff801fd1,
2876    "vqshlu%v.s%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2877
2878   /* Vector VRSHR
2879      NOTE: MVE_VRSHR must appear in the table before
2880      before MVE_VMOV_IMM_TO_VEC due to opcode aliasing.  */
2881   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2882    MVE_VRSHR,
2883    0xef800250, 0xef801fd1,
2884    "vrshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2885
2886   /* Vector VSHL.
2887      NOTE: MVE_VSHL must appear in the table before
2888      before MVE_VMOV_IMM_TO_VEC due to opcode aliasing.  */
2889   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2890    MVE_VSHL_T1,
2891    0xef800550, 0xff801fd1,
2892    "vshl%v.i%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2893
2894   /* Vector VSHR
2895      NOTE: MVE_VSHR must appear in the table before
2896      before MVE_VMOV_IMM_TO_VEC due to opcode aliasing.  */
2897   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2898    MVE_VSHR,
2899    0xef800050, 0xef801fd1,
2900    "vshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2901
2902   /* Vector VSLI
2903      NOTE: MVE_VSLI must appear in the table before
2904      before MVE_VMOV_IMM_TO_VEC due to opcode aliasing.  */
2905   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2906    MVE_VSLI,
2907    0xff800550, 0xff801fd1,
2908    "vsli%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2909
2910   /* Vector VSRI
2911      NOTE: MVE_VSRI must appear in the table before
2912      before MVE_VMOV_IMM_TO_VEC due to opcode aliasing.  */
2913   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2914    MVE_VSRI,
2915    0xff800450, 0xff801fd1,
2916    "vsri%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2917
2918   /* Vector VMOV immediate to vector,
2919      undefinded for cmode == 1111 */
2920   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2921    MVE_VMVN_IMM, 0xef800f70, 0xefb81ff0, UNDEFINED_INSTRUCTION},
2922
2923   /* Vector VMOV immediate to vector,
2924      cmode == 1101 */
2925   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2926    MVE_VMOV_IMM_TO_VEC, 0xef800d50, 0xefb81fd0,
2927    "vmov%v.%5,8-11s\t%13-15,22Q, %E"},
2928
2929   /* Vector VMOV immediate to vector.  */
2930   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2931    MVE_VMOV_IMM_TO_VEC,
2932    0xef800050, 0xefb810d0,
2933    "vmov%v.%5,8-11s\t%13-15,22Q, %E"},
2934
2935   /* Vector VMOV two 32-bit lanes to two gprs, idx = 0.  */
2936   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2937    MVE_VMOV2_VEC_LANE_TO_GP,
2938    0xec000f00, 0xffb01ff0,
2939    "vmov%c\t%0-3r, %16-19r, %13-15,22Q[2], %13-15,22Q[0]"},
2940
2941   /* Vector VMOV two 32-bit lanes to two gprs, idx = 1.  */
2942   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2943    MVE_VMOV2_VEC_LANE_TO_GP,
2944    0xec000f10, 0xffb01ff0,
2945    "vmov%c\t%0-3r, %16-19r, %13-15,22Q[3], %13-15,22Q[1]"},
2946
2947   /* Vector VMOV Two gprs to two 32-bit lanes, idx = 0.  */
2948   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2949    MVE_VMOV2_GP_TO_VEC_LANE,
2950    0xec100f00, 0xffb01ff0,
2951    "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
2952
2953   /* Vector VMOV Two gprs to two 32-bit lanes, idx = 1.  */
2954   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2955    MVE_VMOV2_GP_TO_VEC_LANE,
2956    0xec100f10, 0xffb01ff0,
2957    "vmov%c\t%13-15,22Q[3], %13-15,22Q[1], %0-3r, %16-19r"},
2958
2959   /* Vector VMOV Vector lane to gpr.  */
2960   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2961    MVE_VMOV_VEC_LANE_TO_GP,
2962    0xee100b10, 0xff100f1f,
2963    "vmov%c.%u%5-6,21-22s\t%12-15r, %17-19,7Q[%N]"},
2964
2965   /* Vector VSHLL T1 Variant.  Note: VSHLL T1 must appear before MVE_VMOVL due
2966      to instruction opcode aliasing.  */
2967   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2968    MVE_VSHLL_T1,
2969    0xeea00f40, 0xefa00fd1,
2970    "vshll%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2971
2972   /* Vector VMOVL long.  */
2973   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2974    MVE_VMOVL,
2975    0xeea00f40, 0xefa70fd1,
2976    "vmovl%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q"},
2977
2978   /* Vector VMOV and narrow.  */
2979   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
2980    MVE_VMOVN,
2981    0xfe310e81, 0xffb30fd1,
2982    "vmovn%T%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2983
2984   /* Floating point move extract.  */
2985   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2986    MVE_VMOVX,
2987    0xfeb00a40, 0xffbf0fd0,
2988    "vmovx.f16\t%22,12-15F, %5,0-3F"},
2989
2990   /* Vector VMUL floating-point T1 variant.  */
2991   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2992    MVE_VMUL_FP_T1,
2993    0xff000d50, 0xffa11f51,
2994    "vmul%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2995
2996   /* Vector VMUL floating-point T2 variant.  */
2997   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
2998    MVE_VMUL_FP_T2,
2999    0xee310e60, 0xefb11f70,
3000    "vmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3001
3002   /* Vector VMUL T1 variant.  */
3003   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3004    MVE_VMUL_VEC_T1,
3005    0xef000950, 0xff811f51,
3006    "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3007
3008   /* Vector VMUL T2 variant.  */
3009   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3010    MVE_VMUL_VEC_T2,
3011    0xee011e60, 0xff811f70,
3012    "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3013
3014   /* Vector VMULH.  */
3015   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3016    MVE_VMULH,
3017    0xee010e01, 0xef811f51,
3018    "vmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3019
3020   /* Vector VRMULH.  */
3021   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3022    MVE_VRMULH,
3023    0xee011e01, 0xef811f51,
3024    "vrmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3025
3026   /* Vector VMULL integer.  */
3027   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3028    MVE_VMULL_INT,
3029    0xee010e00, 0xef810f51,
3030    "vmull%T%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3031
3032   /* Vector VMULL polynomial.  */
3033   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3034    MVE_VMULL_POLY,
3035    0xee310e00, 0xefb10f51,
3036    "vmull%T%v.%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3037
3038   /* Vector VMVN immediate to vector.  */
3039   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3040    MVE_VMVN_IMM,
3041    0xef800070, 0xefb810f0,
3042    "vmvn%v.i%8-11s\t%13-15,22Q, %E"},
3043
3044   /* Vector VMVN register.  */
3045   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3046    MVE_VMVN_REG,
3047    0xffb005c0, 0xffbf1fd1,
3048    "vmvn%v\t%13-15,22Q, %1-3,5Q"},
3049
3050   /* Vector VNEG floating point.  */
3051   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
3052    MVE_VNEG_FP,
3053    0xffb107c0, 0xffb31fd1,
3054    "vneg%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
3055
3056   /* Vector VNEG.  */
3057   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3058    MVE_VNEG_VEC,
3059    0xffb103c0, 0xffb31fd1,
3060    "vneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
3061
3062   /* Vector VORN, vector bitwise or not.  */
3063   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3064    MVE_VORN,
3065    0xef300150, 0xffb11f51,
3066    "vorn%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3067
3068   /* Vector VORR register.  */
3069   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3070    MVE_VORR_REG,
3071    0xef200150, 0xffb11f51,
3072    "vorr%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3073
3074   /* Vector VMOV, vector to vector move. While decoding MVE_VORR_REG if
3075      "Qm==Qn", VORR should replaced by its alias VMOV. For that to happen
3076      MVE_VMOV_VEC_TO_VEC need to placed after MVE_VORR_REG in this mve_opcodes
3077      array.  */
3078
3079   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3080    MVE_VMOV_VEC_TO_VEC,
3081    0xef200150, 0xffb11f51,
3082    "vmov%v\t%13-15,22Q, %17-19,7Q"},
3083
3084   /* Vector VQDMULL T1 variant.  */
3085   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3086    MVE_VQDMULL_T1,
3087    0xee300f01, 0xefb10f51,
3088    "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3089
3090   /* Vector VPNOT.  */
3091   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3092    MVE_VPNOT,
3093    0xfe310f4d, 0xffffffff,
3094    "vpnot%v"},
3095
3096   /* Vector VPSEL.  */
3097   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3098    MVE_VPSEL,
3099    0xfe310f01, 0xffb11f51,
3100    "vpsel%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3101
3102   /* Vector VQABS.  */
3103   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3104    MVE_VQABS,
3105    0xffb00740, 0xffb31fd1,
3106    "vqabs%v.s%18-19s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3107
3108   /* Vector VQADD T1 variant.  */
3109   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3110    MVE_VQADD_T1,
3111    0xef000050, 0xef811f51,
3112    "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3113
3114   /* Vector VQADD T2 variant.  */
3115   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3116    MVE_VQADD_T2,
3117    0xee000f60, 0xef811f70,
3118    "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3119
3120   /* Vector VQDMULL T2 variant.  */
3121   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3122    MVE_VQDMULL_T2,
3123    0xee300f60, 0xefb10f70,
3124    "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3125
3126   /* Vector VQMOVN.  */
3127   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3128    MVE_VQMOVN,
3129    0xee330e01, 0xefb30fd1,
3130    "vqmovn%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q"},
3131
3132   /* Vector VQMOVUN.  */
3133   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3134    MVE_VQMOVUN,
3135    0xee310e81, 0xffb30fd1,
3136    "vqmovun%T%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
3137
3138   /* Vector VQDMLADH.  */
3139   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3140    MVE_VQDMLADH,
3141    0xee000e00, 0xff810f51,
3142    "vqdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3143
3144   /* Vector VQRDMLADH.  */
3145   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3146    MVE_VQRDMLADH,
3147    0xee000e01, 0xff810f51,
3148    "vqrdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3149
3150   /* Vector VQDMLAH.  */
3151   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3152    MVE_VQDMLAH,
3153    0xee000e60, 0xff811f70,
3154    "vqdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3155
3156   /* Vector VQRDMLAH.  */
3157   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3158    MVE_VQRDMLAH,
3159    0xee000e40, 0xff811f70,
3160    "vqrdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3161
3162   /* Vector VQDMLASH.  */
3163   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3164    MVE_VQDMLASH,
3165    0xee001e60, 0xff811f70,
3166    "vqdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3167
3168   /* Vector VQRDMLASH.  */
3169   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3170    MVE_VQRDMLASH,
3171    0xee001e40, 0xff811f70,
3172    "vqrdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3173
3174   /* Vector VQDMLSDH.  */
3175   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3176    MVE_VQDMLSDH,
3177    0xfe000e00, 0xff810f51,
3178    "vqdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3179
3180   /* Vector VQRDMLSDH.  */
3181   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3182    MVE_VQRDMLSDH,
3183    0xfe000e01, 0xff810f51,
3184    "vqrdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3185
3186   /* Vector VQDMULH T1 variant.  */
3187   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3188    MVE_VQDMULH_T1,
3189    0xef000b40, 0xff811f51,
3190    "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3191
3192   /* Vector VQRDMULH T2 variant.  */
3193   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3194    MVE_VQRDMULH_T2,
3195    0xff000b40, 0xff811f51,
3196    "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3197
3198   /* Vector VQDMULH T3 variant.  */
3199   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3200    MVE_VQDMULH_T3,
3201    0xee010e60, 0xff811f70,
3202    "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3203
3204   /* Vector VQRDMULH T4 variant.  */
3205   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3206    MVE_VQRDMULH_T4,
3207    0xfe010e60, 0xff811f70,
3208    "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3209
3210   /* Vector VQNEG.  */
3211   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3212    MVE_VQNEG,
3213    0xffb007c0, 0xffb31fd1,
3214    "vqneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
3215
3216   /* Vector VQRSHL T1 variant.  */
3217   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3218    MVE_VQRSHL_T1,
3219    0xef000550, 0xef811f51,
3220    "vqrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3221
3222   /* Vector VQRSHL T2 variant.  */
3223   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3224    MVE_VQRSHL_T2,
3225    0xee331ee0, 0xefb31ff0,
3226    "vqrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3227
3228   /* Vector VQRSHRN.  */
3229   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3230    MVE_VQRSHRN,
3231    0xee800f41, 0xefa00fd1,
3232    "vqrshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3233
3234   /* Vector VQRSHRUN.  */
3235   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3236    MVE_VQRSHRUN,
3237    0xfe800fc0, 0xffa00fd1,
3238    "vqrshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3239
3240   /* Vector VQSHL T1 Variant.  */
3241   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3242    MVE_VQSHL_T1,
3243    0xee311ee0, 0xefb31ff0,
3244    "vqshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3245
3246   /* Vector VQSHL T4 Variant.  */
3247   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3248    MVE_VQSHL_T4,
3249    0xef000450, 0xef811f51,
3250    "vqshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3251
3252   /* Vector VQSHRN.  */
3253   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3254    MVE_VQSHRN,
3255    0xee800f40, 0xefa00fd1,
3256    "vqshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3257
3258   /* Vector VQSHRUN.  */
3259   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3260    MVE_VQSHRUN,
3261    0xee800fc0, 0xffa00fd1,
3262    "vqshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3263
3264   /* Vector VQSUB T1 Variant.  */
3265   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3266    MVE_VQSUB_T1,
3267    0xef000250, 0xef811f51,
3268    "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3269
3270   /* Vector VQSUB T2 Variant.  */
3271   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3272    MVE_VQSUB_T2,
3273    0xee001f60, 0xef811f70,
3274    "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3275
3276   /* Vector VREV16.  */
3277   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3278    MVE_VREV16,
3279    0xffb00140, 0xffb31fd1,
3280    "vrev16%v.8\t%13-15,22Q, %1-3,5Q"},
3281
3282   /* Vector VREV32.  */
3283   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3284    MVE_VREV32,
3285    0xffb000c0, 0xffb31fd1,
3286    "vrev32%v.%18-19s\t%13-15,22Q, %1-3,5Q"},
3287
3288   /* Vector VREV64.  */
3289   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3290    MVE_VREV64,
3291    0xffb00040, 0xffb31fd1,
3292    "vrev64%v.%18-19s\t%13-15,22Q, %1-3,5Q"},
3293
3294   /* Vector VRINT floating point.  */
3295   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
3296    MVE_VRINT_FP,
3297    0xffb20440, 0xffb31c51,
3298    "vrint%m%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
3299
3300   /* Vector VRMLALDAVH.  */
3301   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3302    MVE_VRMLALDAVH,
3303    0xee800f00, 0xef811f51,
3304    "vrmlalvh%5A%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
3305
3306   /* Vector VRMLALDAVH.  */
3307   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3308    MVE_VRMLALDAVH,
3309    0xee801f00, 0xef811f51,
3310    "vrmlaldavh%5Ax%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
3311
3312   /* Vector VRSHL T1 Variant.  */
3313   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3314    MVE_VRSHL_T1,
3315    0xef000540, 0xef811f51,
3316    "vrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3317
3318   /* Vector VRSHL T2 Variant.  */
3319   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3320    MVE_VRSHL_T2,
3321    0xee331e60, 0xefb31ff0,
3322    "vrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3323
3324   /* Vector VRSHRN.  */
3325   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3326    MVE_VRSHRN,
3327    0xfe800fc1, 0xffa00fd1,
3328    "vrshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3329
3330   /* Vector VSBC.  */
3331   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3332    MVE_VSBC,
3333    0xfe300f00, 0xffb10f51,
3334    "vsbc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3335
3336   /* Vector VSHL T2 Variant.  */
3337   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3338    MVE_VSHL_T2,
3339    0xee311e60, 0xefb31ff0,
3340    "vshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3341
3342   /* Vector VSHL T3 Variant.  */
3343   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3344    MVE_VSHL_T3,
3345    0xef000440, 0xef811f51,
3346    "vshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3347
3348   /* Vector VSHLC.  */
3349   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3350    MVE_VSHLC,
3351    0xeea00fc0, 0xffa01ff0,
3352    "vshlc%v\t%13-15,22Q, %0-3r, #%16-20d"},
3353
3354   /* Vector VSHLL T2 Variant.  */
3355   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3356    MVE_VSHLL_T2,
3357    0xee310e01, 0xefb30fd1,
3358    "vshll%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q, #%18-19d"},
3359
3360   /* Vector VSHRN.  */
3361   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3362    MVE_VSHRN,
3363    0xee800fc1, 0xffa00fd1,
3364    "vshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3365
3366   /* Vector VST2 no writeback.  */
3367   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3368    MVE_VST2,
3369    0xfc801e00, 0xffb01e5f,
3370    "vst2%5d.%7-8s\t%B, [%16-19r]"},
3371
3372   /* Vector VST2 writeback.  */
3373   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3374    MVE_VST2,
3375    0xfca01e00, 0xffb01e5f,
3376    "vst2%5d.%7-8s\t%B, [%16-19r]!"},
3377
3378   /* Vector VST4 no writeback.  */
3379   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3380    MVE_VST4,
3381    0xfc801e01, 0xffb01e1f,
3382    "vst4%5-6d.%7-8s\t%B, [%16-19r]"},
3383
3384   /* Vector VST4 writeback.  */
3385   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3386    MVE_VST4,
3387    0xfca01e01, 0xffb01e1f,
3388    "vst4%5-6d.%7-8s\t%B, [%16-19r]!"},
3389
3390   /* Vector VSTRB scatter store, T1 variant.  */
3391   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3392    MVE_VSTRB_SCATTER_T1,
3393    0xec800e00, 0xffb01e50,
3394    "vstrb%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
3395
3396   /* Vector VSTRH scatter store, T2 variant.  */
3397   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3398    MVE_VSTRH_SCATTER_T2,
3399    0xec800e10, 0xffb01e50,
3400    "vstrh%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3401
3402   /* Vector VSTRW scatter store, T3 variant.  */
3403   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3404    MVE_VSTRW_SCATTER_T3,
3405    0xec800e40, 0xffb01e50,
3406    "vstrw%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3407
3408   /* Vector VSTRD scatter store, T4 variant.  */
3409   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3410    MVE_VSTRD_SCATTER_T4,
3411    0xec800fd0, 0xffb01fd0,
3412    "vstrd%v.64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3413
3414   /* Vector VSTRW scatter store, T5 variant.  */
3415   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3416    MVE_VSTRW_SCATTER_T5,
3417    0xfd001e00, 0xff111f00,
3418    "vstrw%v.32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
3419
3420   /* Vector VSTRD scatter store, T6 variant.  */
3421   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3422    MVE_VSTRD_SCATTER_T6,
3423    0xfd001f00, 0xff111f00,
3424    "vstrd%v.64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
3425
3426   /* Vector VSTRB.  */
3427   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3428    MVE_VSTRB_T1,
3429    0xec000e00, 0xfe581e00,
3430    "vstrb%v.%7-8s\t%13-15Q, %d"},
3431
3432   /* Vector VSTRH.  */
3433   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3434    MVE_VSTRH_T2,
3435    0xec080e00, 0xfe581e00,
3436    "vstrh%v.%7-8s\t%13-15Q, %d"},
3437
3438   /* Vector VSTRB variant T5.  */
3439   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3440    MVE_VSTRB_T5,
3441    0xec001e00, 0xfe101f80,
3442    "vstrb%v.8\t%13-15,22Q, %d"},
3443
3444   /* Vector VSTRH variant T6.  */
3445   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3446    MVE_VSTRH_T6,
3447    0xec001e80, 0xfe101f80,
3448    "vstrh%v.16\t%13-15,22Q, %d"},
3449
3450   /* Vector VSTRW variant T7.  */
3451   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3452    MVE_VSTRW_T7,
3453    0xec001f00, 0xfe101f80,
3454    "vstrw%v.32\t%13-15,22Q, %d"},
3455
3456   /* Vector VSUB floating point T1 variant.  */
3457   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
3458    MVE_VSUB_FP_T1,
3459    0xef200d40, 0xffa11f51,
3460    "vsub%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3461
3462   /* Vector VSUB floating point T2 variant.  */
3463   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
3464    MVE_VSUB_FP_T2,
3465    0xee301f40, 0xefb11f70,
3466    "vsub%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3467
3468   /* Vector VSUB T1 variant.  */
3469   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3470    MVE_VSUB_VEC_T1,
3471    0xff000840, 0xff811f51,
3472    "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3473
3474   /* Vector VSUB T2 variant.  */
3475   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3476    MVE_VSUB_VEC_T2,
3477    0xee011f40, 0xff811f70,
3478    "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3479
3480   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3481    MVE_ASRLI,
3482    0xea50012f, 0xfff1813f,
3483    "asrl%c\t%17-19l, %9-11h, %j"},
3484
3485   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3486    MVE_ASRL,
3487    0xea50012d, 0xfff101ff,
3488    "asrl%c\t%17-19l, %9-11h, %12-15S"},
3489
3490   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3491    MVE_LSLLI,
3492    0xea50010f, 0xfff1813f,
3493    "lsll%c\t%17-19l, %9-11h, %j"},
3494
3495   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3496    MVE_LSLL,
3497    0xea50010d, 0xfff101ff,
3498    "lsll%c\t%17-19l, %9-11h, %12-15S"},
3499
3500   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3501    MVE_LSRL,
3502    0xea50011f, 0xfff1813f,
3503    "lsrl%c\t%17-19l, %9-11h, %j"},
3504
3505   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3506    MVE_SQRSHRL,
3507    0xea51012d, 0xfff1017f,
3508    "sqrshrl%c\t%17-19l, %9-11h, %k, %12-15S"},
3509
3510   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3511    MVE_SQRSHR,
3512    0xea500f2d, 0xfff00fff,
3513    "sqrshr%c\t%16-19S, %12-15S"},
3514
3515   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3516    MVE_SQSHLL,
3517    0xea51013f, 0xfff1813f,
3518    "sqshll%c\t%17-19l, %9-11h, %j"},
3519
3520   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3521    MVE_SQSHL,
3522    0xea500f3f, 0xfff08f3f,
3523    "sqshl%c\t%16-19S, %j"},
3524
3525   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3526    MVE_SRSHRL,
3527    0xea51012f, 0xfff1813f,
3528    "srshrl%c\t%17-19l, %9-11h, %j"},
3529
3530   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3531    MVE_SRSHR,
3532    0xea500f2f, 0xfff08f3f,
3533    "srshr%c\t%16-19S, %j"},
3534
3535   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3536    MVE_UQRSHLL,
3537    0xea51010d, 0xfff1017f,
3538    "uqrshll%c\t%17-19l, %9-11h, %k, %12-15S"},
3539
3540   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3541    MVE_UQRSHL,
3542    0xea500f0d, 0xfff00fff,
3543    "uqrshl%c\t%16-19S, %12-15S"},
3544
3545   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3546    MVE_UQSHLL,
3547     0xea51010f, 0xfff1813f,
3548    "uqshll%c\t%17-19l, %9-11h, %j"},
3549
3550   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3551    MVE_UQSHL,
3552    0xea500f0f, 0xfff08f3f,
3553    "uqshl%c\t%16-19S, %j"},
3554
3555   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3556    MVE_URSHRL,
3557     0xea51011f, 0xfff1813f,
3558    "urshrl%c\t%17-19l, %9-11h, %j"},
3559
3560   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
3561    MVE_URSHR,
3562    0xea500f1f, 0xfff08f3f,
3563    "urshr%c\t%16-19S, %j"},
3564
3565   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3566    MVE_CSINC,
3567    0xea509000, 0xfff0f000,
3568    "csinc\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3569
3570   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3571    MVE_CSINV,
3572    0xea50a000, 0xfff0f000,
3573    "csinv\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3574
3575   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3576    MVE_CSET,
3577    0xea5f900f, 0xfffff00f,
3578    "cset\t%8-11S, %4-7C"},
3579
3580   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3581    MVE_CSETM,
3582    0xea5fa00f, 0xfffff00f,
3583    "csetm\t%8-11S, %4-7C"},
3584
3585   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3586    MVE_CSEL,
3587    0xea508000, 0xfff0f000,
3588    "csel\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3589
3590   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3591    MVE_CSNEG,
3592    0xea50b000, 0xfff0f000,
3593    "csneg\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3594
3595   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3596    MVE_CINC,
3597    0xea509000, 0xfff0f000,
3598    "cinc\t%8-11S, %16-19Z, %4-7C"},
3599
3600   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3601    MVE_CINV,
3602    0xea50a000, 0xfff0f000,
3603    "cinv\t%8-11S, %16-19Z, %4-7C"},
3604
3605   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3606    MVE_CNEG,
3607    0xea50b000, 0xfff0f000,
3608    "cneg\t%8-11S, %16-19Z, %4-7C"},
3609
3610   {ARM_FEATURE_CORE_LOW (0),
3611    MVE_NONE,
3612    0x00000000, 0x00000000, 0}
3613 };
3614
3615 /* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb.  All three are partially
3616    ordered: they must be searched linearly from the top to obtain a correct
3617    match.  */
3618
3619 /* print_insn_arm recognizes the following format control codes:
3620
3621    %%                   %
3622
3623    %a                   print address for ldr/str instruction
3624    %s                   print address for ldr/str halfword/signextend instruction
3625    %S                   like %s but allow UNPREDICTABLE addressing
3626    %b                   print branch destination
3627    %c                   print condition code (always bits 28-31)
3628    %m                   print register mask for ldm/stm instruction
3629    %o                   print operand2 (immediate or register + shift)
3630    %p                   print 'p' iff bits 12-15 are 15
3631    %t                   print 't' iff bit 21 set and bit 24 clear
3632    %B                   print arm BLX(1) destination
3633    %C                   print the PSR sub type.
3634    %U                   print barrier type.
3635    %P                   print address for pli instruction.
3636
3637    %<bitfield>r         print as an ARM register
3638    %<bitfield>T         print as an ARM register + 1
3639    %<bitfield>R         as %r but r15 is UNPREDICTABLE
3640    %<bitfield>{r|R}u    as %{r|R} but if matches the other %u field then is UNPREDICTABLE
3641    %<bitfield>{r|R}U    as %{r|R} but if matches the other %U field then is UNPREDICTABLE
3642    %<bitfield>d         print the bitfield in decimal
3643    %<bitfield>W         print the bitfield plus one in decimal
3644    %<bitfield>x         print the bitfield in hex
3645    %<bitfield>X         print the bitfield as 1 hex digit without leading "0x"
3646
3647    %<bitfield>'c        print specified char iff bitfield is all ones
3648    %<bitfield>`c        print specified char iff bitfield is all zeroes
3649    %<bitfield>?ab...    select from array of values in big endian order
3650
3651    %e                   print arm SMI operand (bits 0..7,8..19).
3652    %E                   print the LSB and WIDTH fields of a BFI or BFC instruction.
3653    %V                   print the 16-bit immediate field of a MOVT or MOVW instruction.
3654    %R                   print the SPSR/CPSR or banked register of an MRS.  */
3655
3656 static const struct opcode32 arm_opcodes[] =
3657 {
3658   /* ARM instructions.  */
3659   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3660     0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
3661   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3662     0xe7f000f0, 0xfff000f0, "udf\t#%e"},
3663
3664   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5),
3665     0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
3666   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
3667     0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
3668   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
3669     0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3670   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S),
3671     0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
3672   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
3673     0x00800090, 0x0fa000f0,
3674     "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3675   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
3676     0x00a00090, 0x0fa000f0,
3677     "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3678
3679   /* V8.2 RAS extension instructions.  */
3680   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
3681     0xe320f010, 0xffffffff, "esb"},
3682
3683   /* V8-R instructions.  */
3684   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8R),
3685     0xf57ff04c, 0xffffffff, "dfb"},
3686
3687   /* V8 instructions.  */
3688   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3689     0x0320f005, 0x0fffffff, "sevl"},
3690   /* Defined in V8 but is in NOP space so available to all arch.  */
3691   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3692     0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
3693   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
3694     0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
3695   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3696     0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
3697   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3698     0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
3699   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3700     0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
3701   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3702     0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
3703   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3704     0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
3705   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3706     0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
3707   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3708     0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
3709   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3710     0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
3711   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3712     0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
3713   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3714     0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
3715   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3716     0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
3717   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3718     0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
3719   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3720     0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
3721   /* CRC32 instructions.  */
3722   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
3723     0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
3724   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
3725     0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
3726   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
3727     0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
3728   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
3729     0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
3730   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
3731     0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
3732   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
3733     0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
3734
3735   /* Privileged Access Never extension instructions.  */
3736   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
3737     0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
3738
3739   /* Virtualization Extension instructions.  */
3740   {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
3741   {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
3742
3743   /* Integer Divide Extension instructions.  */
3744   {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
3745     0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
3746   {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
3747     0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
3748
3749   /* MP Extension instructions.  */
3750   {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"},
3751
3752   /* Speculation Barriers.  */
3753   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xe320f014, 0xffffffff, "csdb"},
3754   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff040, 0xffffffff, "ssbb"},
3755   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff044, 0xffffffff, "pssbb"},
3756
3757   /* V7 instructions.  */
3758   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
3759   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
3760   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
3761   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
3762   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
3763   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
3764   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"},
3765    {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
3766     0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
3767
3768   /* ARM V6T2 instructions.  */
3769   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3770     0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
3771   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3772     0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
3773   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3774     0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3775   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3776     0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
3777
3778   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3779     0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
3780   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3781     0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
3782
3783   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3784     0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
3785   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3786     0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
3787   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3788     0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
3789   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3790     0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
3791
3792   /* ARM Security extension instructions.  */
3793   {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
3794     0x01600070, 0x0ff000f0, "smc%c\t%e"},
3795
3796   /* ARM V6K instructions.  */
3797   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3798     0xf57ff01f, 0xffffffff, "clrex"},
3799   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3800     0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
3801   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3802     0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
3803   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3804     0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
3805   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3806     0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
3807   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3808     0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
3809   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3810     0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
3811
3812   /* ARMv8.5-A instructions.  */
3813   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf57ff070, 0xffffffff, "sb"},
3814
3815   /* ARM V6K NOP hints.  */
3816   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3817     0x0320f001, 0x0fffffff, "yield%c"},
3818   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3819     0x0320f002, 0x0fffffff, "wfe%c"},
3820   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3821     0x0320f003, 0x0fffffff, "wfi%c"},
3822   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3823     0x0320f004, 0x0fffffff, "sev%c"},
3824   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3825     0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
3826
3827   /* ARM V6 instructions.  */
3828   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3829     0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
3830   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3831     0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
3832   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3833     0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
3834   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3835     0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
3836   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3837     0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
3838   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3839     0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
3840   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3841     0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
3842   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3843     0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
3844   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3845     0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
3846   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3847     0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
3848   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3849     0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
3850   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3851     0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
3852   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3853     0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
3854   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3855     0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
3856   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3857     0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
3858   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3859     0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
3860   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3861     0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
3862   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3863     0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
3864   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3865     0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
3866   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3867     0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
3868   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3869     0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
3870   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3871     0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
3872   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3873     0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
3874   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3875     0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
3876   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3877     0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
3878   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3879     0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
3880   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3881     0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
3882   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3883     0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
3884   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3885     0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
3886   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3887     0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
3888   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3889     0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
3890   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3891     0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
3892   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3893     0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
3894   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3895     0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
3896   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3897     0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
3898   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3899     0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
3900   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3901     0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
3902   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3903     0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
3904   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3905     0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
3906   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3907     0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
3908   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3909     0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
3910   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3911     0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
3912   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3913     0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
3914   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3915     0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
3916   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3917     0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
3918   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3919     0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
3920   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3921     0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
3922   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3923     0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
3924   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3925     0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
3926   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3927     0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
3928   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3929     0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
3930   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3931     0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
3932   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3933     0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
3934   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3935     0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
3936   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3937     0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
3938   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3939     0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
3940   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3941     0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
3942   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3943     0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
3944   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3945     0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
3946   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3947     0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
3948   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3949     0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
3950   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3951     0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
3952   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3953     0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
3954   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3955     0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
3956   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3957     0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
3958   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3959     0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
3960   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3961     0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
3962   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3963     0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
3964   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3965     0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
3966   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3967     0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
3968   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3969     0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
3970   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3971     0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
3972   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3973     0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
3974   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3975     0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
3976   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3977     0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
3978   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3979     0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3980   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3981     0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3982   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3983     0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3984   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3985     0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
3986   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3987     0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3988   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3989     0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3990   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3991     0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3992   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3993     0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
3994   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3995     0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3996   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3997     0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3998   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3999     0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
4000   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4001     0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
4002   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4003     0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
4004   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4005     0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
4006   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4007     0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
4008   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4009     0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
4010   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4011     0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
4012   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4013     0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
4014   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4015     0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
4016   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4017     0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
4018   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4019     0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
4020   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4021     0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
4022   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4023     0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
4024   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4025     0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
4026   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4027     0xf1010000, 0xfffffc00, "setend\t%9?ble"},
4028   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4029     0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
4030   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4031     0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
4032   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4033     0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4034   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4035     0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4036   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4037     0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4038   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4039     0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4040   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4041     0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
4042   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4043     0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4044   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4045     0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4046   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4047     0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
4048   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4049     0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
4050   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4051     0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
4052   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4053     0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
4054   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4055     0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
4056   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4057     0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
4058   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4059     0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
4060   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4061     0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
4062   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4063     0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4064   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4065     0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
4066   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4067     0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
4068   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4069     0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
4070   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4071     0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
4072
4073   /* V5J instruction.  */
4074   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J),
4075     0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
4076
4077   /* V5 Instructions.  */
4078   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
4079     0xe1200070, 0xfff000f0,
4080     "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
4081   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
4082     0xfa000000, 0xfe000000, "blx\t%B"},
4083   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
4084     0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
4085   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
4086     0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
4087
4088   /* V5E "El Segundo" Instructions.  */
4089   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
4090     0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
4091   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
4092     0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
4093   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
4094     0xf450f000, 0xfc70f000, "pld\t%a"},
4095   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4096     0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4097   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4098     0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4099   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4100     0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4101   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4102     0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
4103
4104   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4105     0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4106   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4107     0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
4108
4109   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4110     0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4111   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4112     0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4113   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4114     0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4115   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4116     0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4117
4118   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4119     0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
4120   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4121     0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
4122   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4123     0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
4124   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4125     0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
4126
4127   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4128     0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
4129   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4130     0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
4131
4132   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4133     0x01000050, 0x0ff00ff0,  "qadd%c\t%12-15R, %0-3R, %16-19R"},
4134   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4135     0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
4136   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4137     0x01200050, 0x0ff00ff0,  "qsub%c\t%12-15R, %0-3R, %16-19R"},
4138   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4139     0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
4140
4141   /* ARM Instructions.  */
4142   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4143     0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
4144
4145   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4146     0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
4147   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4148     0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
4149   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4150     0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
4151   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4152     0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
4153   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4154     0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
4155   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4156     0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
4157
4158   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4159     0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
4160   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4161     0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
4162   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4163     0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
4164   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4165     0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
4166
4167   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4168     0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
4169   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4170     0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
4171   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4172     0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
4173   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4174     0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
4175
4176   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4177     0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
4178   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4179     0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
4180   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4181     0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
4182
4183   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4184     0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
4185   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4186     0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
4187   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4188     0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
4189
4190   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4191     0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
4192   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4193     0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
4194   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4195     0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
4196
4197   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4198     0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
4199   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4200     0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
4201   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4202     0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
4203
4204   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4205     0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
4206   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4207     0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
4208   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4209     0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
4210
4211   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4212     0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
4213   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4214     0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
4215   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4216     0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
4217
4218   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4219     0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
4220   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4221     0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
4222   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4223     0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
4224
4225   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4226     0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
4227   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4228     0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
4229   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4230     0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
4231
4232   {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
4233     0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
4234   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
4235     0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
4236   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
4237     0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
4238
4239   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4240     0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
4241   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4242     0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
4243   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4244     0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
4245
4246   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4247     0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
4248   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4249     0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
4250   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4251     0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
4252
4253   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4254     0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
4255   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4256     0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
4257   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4258     0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
4259
4260   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4261     0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
4262   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4263     0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
4264   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4265     0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
4266
4267   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4268     0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
4269   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4270     0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
4271   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4272     0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
4273
4274   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4275     0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
4276   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4277     0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
4278   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4279     0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
4280   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4281     0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
4282   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4283     0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
4284   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4285     0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
4286   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4287     0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
4288
4289   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4290     0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
4291   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4292     0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
4293   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4294     0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
4295
4296   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4297     0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
4298   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4299     0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
4300   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4301     0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
4302
4303   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4304     0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
4305   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4306     0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
4307
4308   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4309     0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
4310
4311   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4312     0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
4313   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4314     0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
4315
4316   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4317     0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4318   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4319     0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4320   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4321     0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4322   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4323     0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4324   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4325     0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4326   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4327     0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4328   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4329     0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4330   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4331     0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4332   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4333     0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4334   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4335     0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4336   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4337     0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4338   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4339     0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4340   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4341     0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4342   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4343     0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4344   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4345     0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4346   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4347     0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4348   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4349     0x092d0000, 0x0fff0000, "push%c\t%m"},
4350   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4351     0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
4352   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4353     0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
4354
4355   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4356     0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4357   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4358     0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4359   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4360     0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4361   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4362     0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4363   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4364     0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4365   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4366     0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4367   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4368     0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4369   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4370     0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4371   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4372     0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4373   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4374     0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4375   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4376     0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4377   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4378     0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4379   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4380     0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4381   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4382     0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4383   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4384     0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4385   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4386     0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4387   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4388     0x08bd0000, 0x0fff0000, "pop%c\t%m"},
4389   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4390     0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
4391   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4392     0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
4393
4394   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4395     0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
4396   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4397     0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
4398
4399   /* The rest.  */
4400   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
4401     0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION},
4402   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4403     0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
4404   {ARM_FEATURE_CORE_LOW (0),
4405     0x00000000, 0x00000000, 0}
4406 };
4407
4408 /* print_insn_thumb16 recognizes the following format control codes:
4409
4410    %S                   print Thumb register (bits 3..5 as high number if bit 6 set)
4411    %D                   print Thumb register (bits 0..2 as high number if bit 7 set)
4412    %<bitfield>I         print bitfield as a signed decimal
4413                                 (top bit of range being the sign bit)
4414    %N                   print Thumb register mask (with LR)
4415    %O                   print Thumb register mask (with PC)
4416    %M                   print Thumb register mask
4417    %b                   print CZB's 6-bit unsigned branch destination
4418    %s                   print Thumb right-shift immediate (6..10; 0 == 32).
4419    %c                   print the condition code
4420    %C                   print the condition code, or "s" if not conditional
4421    %x                   print warning if conditional an not at end of IT block"
4422    %X                   print "\t; unpredictable <IT:code>" if conditional
4423    %I                   print IT instruction suffix and operands
4424    %W                   print Thumb Writeback indicator for LDMIA
4425    %<bitfield>r         print bitfield as an ARM register
4426    %<bitfield>d         print bitfield as a decimal
4427    %<bitfield>H         print (bitfield * 2) as a decimal
4428    %<bitfield>W         print (bitfield * 4) as a decimal
4429    %<bitfield>a         print (bitfield * 4) as a pc-rel offset + decoded symbol
4430    %<bitfield>B         print Thumb branch destination (signed displacement)
4431    %<bitfield>c         print bitfield as a condition code
4432    %<bitnum>'c          print specified char iff bit is one
4433    %<bitnum>?ab         print a if bit is one else print b.  */
4434
4435 static const struct opcode16 thumb_opcodes[] =
4436 {
4437   /* Thumb instructions.  */
4438
4439   /* ARMv8-M Security Extensions instructions.  */
4440   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"},
4441   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff87, "bxns\t%3-6r"},
4442
4443   /* ARM V8 instructions.  */
4444   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),  0xbf50, 0xffff, "sevl%c"},
4445   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),  0xba80, 0xffc0, "hlt\t%0-5x"},
4446   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),  0xb610, 0xfff7, "setpan\t#%3-3d"},
4447
4448   /* ARM V6K no-argument instructions.  */
4449   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
4450   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"},
4451   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"},
4452   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"},
4453   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"},
4454   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
4455
4456   /* ARM V6T2 instructions.  */
4457   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4458     0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
4459   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4460     0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
4461   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
4462
4463   /* ARM V6.  */
4464   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
4465   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
4466   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
4467   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
4468   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
4469   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
4470   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%3?ble%X"},
4471   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
4472   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
4473   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
4474   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
4475
4476   /* ARM V5 ISA extends Thumb.  */
4477   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
4478     0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional.  */
4479   /* This is BLX(2).  BLX(1) is a 32-bit instruction.  */
4480   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
4481     0x4780, 0xff87, "blx%c\t%3-6r%x"},  /* note: 4 bit register number.  */
4482   /* ARM V4T ISA (Thumb v1).  */
4483   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4484     0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
4485   /* Format 4.  */
4486   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
4487   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
4488   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
4489   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
4490   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
4491   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
4492   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
4493   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
4494   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
4495   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
4496   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
4497   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
4498   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
4499   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
4500   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
4501   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
4502   /* format 13 */
4503   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
4504   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
4505   /* format 5 */
4506   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"},
4507   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"},
4508   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
4509   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"},
4510   /* format 14 */
4511   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"},
4512   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"},
4513   /* format 2 */
4514   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4515     0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
4516   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4517     0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
4518   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4519     0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
4520   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4521     0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
4522   /* format 8 */
4523   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4524     0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
4525   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4526     0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
4527   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4528     0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
4529   /* format 7 */
4530   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4531     0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
4532   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4533     0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
4534   /* format 1 */
4535   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
4536   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4537     0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
4538   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
4539   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
4540   /* format 3 */
4541   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
4542   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
4543   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
4544   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
4545   /* format 6 */
4546   /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
4547   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4548     0x4800, 0xF800,
4549     "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
4550   /* format 9 */
4551   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4552     0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
4553   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4554     0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
4555   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4556     0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
4557   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4558     0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
4559   /* format 10 */
4560   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4561     0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
4562   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4563     0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
4564   /* format 11 */
4565   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4566     0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
4567   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4568     0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
4569   /* format 12 */
4570   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4571     0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
4572   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4573     0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
4574   /* format 15 */
4575   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
4576   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
4577   /* format 17 */
4578   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
4579   /* format 16 */
4580   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
4581   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
4582   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
4583   /* format 18 */
4584   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
4585
4586   /* The E800 .. FFFF range is unconditionally redirected to the
4587      32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
4588      are processed via that table.  Thus, we can never encounter a
4589      bare "second half of BL/BLX(1)" instruction here.  */
4590   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),  0x0000, 0x0000, UNDEFINED_INSTRUCTION},
4591   {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
4592 };
4593
4594 /* Thumb32 opcodes use the same table structure as the ARM opcodes.
4595    We adopt the convention that hw1 is the high 16 bits of .value and
4596    .mask, hw2 the low 16 bits.
4597
4598    print_insn_thumb32 recognizes the following format control codes:
4599
4600        %%               %
4601
4602        %I               print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
4603        %M               print a modified 12-bit immediate (same location)
4604        %J               print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
4605        %K               print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
4606        %H               print a 16-bit immediate from hw2[3:0],hw1[11:0]
4607        %S               print a possibly-shifted Rm
4608
4609        %L               print address for a ldrd/strd instruction
4610        %a               print the address of a plain load/store
4611        %w               print the width and signedness of a core load/store
4612        %m               print register mask for ldm/stm
4613        %n               print register mask for clrm
4614
4615        %E               print the lsb and width fields of a bfc/bfi instruction
4616        %F               print the lsb and width fields of a sbfx/ubfx instruction
4617        %G               print a fallback offset for Branch Future instructions
4618        %W               print an offset for BF instruction
4619        %Y               print an offset for BFL instruction
4620        %Z               print an offset for BFCSEL instruction
4621        %Q               print an offset for Low Overhead Loop instructions
4622        %P               print an offset for Low Overhead Loop end instructions
4623        %b               print a conditional branch offset
4624        %B               print an unconditional branch offset
4625        %s               print the shift field of an SSAT instruction
4626        %R               print the rotation field of an SXT instruction
4627        %U               print barrier type.
4628        %P               print address for pli instruction.
4629        %c               print the condition code
4630        %x               print warning if conditional an not at end of IT block"
4631        %X               print "\t; unpredictable <IT:code>" if conditional
4632
4633        %<bitfield>d     print bitfield in decimal
4634        %<bitfield>D     print bitfield plus one in decimal
4635        %<bitfield>W     print bitfield*4 in decimal
4636        %<bitfield>r     print bitfield as an ARM register
4637        %<bitfield>R     as %<>r but r15 is UNPREDICTABLE
4638        %<bitfield>S     as %<>r but r13 and r15 is UNPREDICTABLE
4639        %<bitfield>c     print bitfield as a condition code
4640
4641        %<bitfield>'c    print specified char iff bitfield is all ones
4642        %<bitfield>`c    print specified char iff bitfield is all zeroes
4643        %<bitfield>?ab... select from array of values in big endian order
4644
4645    With one exception at the bottom (done because BL and BLX(1) need
4646    to come dead last), this table was machine-sorted first in
4647    decreasing order of number of bits set in the mask, then in
4648    increasing numeric order of mask, then in increasing numeric order
4649    of opcode.  This order is not the clearest for a human reader, but
4650    is guaranteed never to catch a special-case bit pattern with a more
4651    general mask, which is important, because this instruction encoding
4652    makes heavy use of special-case bit patterns.  */
4653 static const struct opcode32 thumb32_opcodes[] =
4654 {
4655   /* Arm v8.1-M Mainline Pointer Authentication and Branch Target
4656      Identification Extension.  */
4657   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4658    0xf3af800f, 0xffffffff, "bti"},
4659   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4660    0xf3af800d, 0xffffffff, "pacbti\tr12, lr, sp"},
4661
4662   /* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions
4663      instructions.  */
4664   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4665     0xf00fe001, 0xffffffff, "lctp%c"},
4666   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4667     0xf02fc001, 0xfffff001, "le\t%P"},
4668   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4669     0xf00fc001, 0xfffff001, "le\tlr, %P"},
4670   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4671     0xf01fc001, 0xfffff001, "letp\tlr, %P"},
4672   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4673     0xf040c001, 0xfff0f001, "wls\tlr, %16-19S, %Q"},
4674   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4675     0xf000c001, 0xffc0f001, "wlstp.%20-21s\tlr, %16-19S, %Q"},
4676   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4677     0xf040e001, 0xfff0ffff, "dls\tlr, %16-19S"},
4678   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4679     0xf000e001, 0xffc0ffff, "dlstp.%20-21s\tlr, %16-19S"},
4680
4681   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4682     0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
4683   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4684     0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"},
4685   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4686     0xf000c001, 0xf800f001, "bfl%c\t%G, %Y"},
4687   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4688     0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"},
4689   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4690     0xf000e001, 0xf840f001, "bfcsel\t%G, %Z, %18-21c"},
4691
4692   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4693     0xe89f0000, 0xffff2000, "clrm%c\t%n"},
4694
4695   /* ARMv8-M and ARMv8-M Security Extensions instructions.  */
4696   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"},
4697   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4698     0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
4699   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4700     0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
4701   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4702     0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
4703   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4704     0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
4705
4706   /* ARM V8.2 RAS extension instructions.  */
4707   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
4708     0xf3af8010, 0xffffffff, "esb"},
4709
4710   /* V8 instructions.  */
4711   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4712     0xf3af8005, 0xffffffff, "sevl%c.w"},
4713   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4714     0xf78f8000, 0xfffffffc, "dcps%0-1d"},
4715   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4716     0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
4717   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4718     0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
4719   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4720     0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
4721   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4722     0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
4723   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4724     0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
4725   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4726     0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
4727   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4728     0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
4729   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4730     0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
4731   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4732     0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
4733   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4734     0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
4735   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4736     0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
4737   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4738     0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
4739   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4740     0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
4741   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4742     0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
4743
4744   /* V8-R instructions.  */
4745   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8R),
4746     0xf3bf8f4c, 0xffffffff, "dfb%c"},
4747
4748   /* CRC32 instructions.  */
4749   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
4750     0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},
4751   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
4752     0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"},
4753   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
4754     0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"},
4755   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
4756     0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"},
4757   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
4758     0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"},
4759   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
4760     0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
4761
4762   /* Speculation Barriers.  */
4763   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8014, 0xffffffff, "csdb"},
4764   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f40, 0xffffffff, "ssbb"},
4765   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f44, 0xffffffff, "pssbb"},
4766
4767   /* V7 instructions.  */
4768   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
4769   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
4770   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
4771   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
4772   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
4773   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
4774   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
4775   {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
4776     0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
4777   {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
4778     0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
4779
4780   /* Virtualization Extension instructions.  */
4781   {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
4782   /* We skip ERET as that is SUBS pc, lr, #0.  */
4783
4784   /* MP Extension instructions.  */
4785   {ARM_FEATURE_CORE_LOW (ARM_EXT_MP),   0xf830f000, 0xff70f000, "pldw%c\t%a"},
4786
4787   /* Security extension instructions.  */
4788   {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),  0xf7f08000, 0xfff0f000, "smc%c\t%K"},
4789
4790   /* ARMv8.5-A instructions.  */
4791   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf3bf8f70, 0xffffffff, "sb"},
4792
4793   /* Instructions defined in the basic V6T2 set.  */
4794   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
4795   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},
4796   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"},
4797   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"},
4798   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"},
4799   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4800     0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
4801   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
4802
4803   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4804     0xf3bf8f2f, 0xffffffff, "clrex%c"},
4805   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4806     0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
4807   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4808     0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
4809   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4810     0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
4811   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4812     0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
4813   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4814     0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
4815   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4816     0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
4817   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4818     0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
4819   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4820     0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
4821   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4822     0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
4823   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4824     0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
4825   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4826     0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
4827   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4828     0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
4829   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4830     0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
4831   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4832     0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
4833   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4834     0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
4835   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4836     0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
4837   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4838     0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
4839   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4840     0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
4841   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4842     0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
4843   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4844     0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
4845   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4846     0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
4847   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4848     0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
4849   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4850     0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
4851   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4852     0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
4853   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4854     0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
4855   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4856     0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
4857   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4858     0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
4859   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4860     0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
4861   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4862     0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
4863   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4864     0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
4865   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4866     0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
4867   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4868     0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
4869   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4870     0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
4871   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4872     0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
4873   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4874     0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
4875   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4876     0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
4877   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4878     0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
4879   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4880     0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
4881   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4882     0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
4883   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4884     0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
4885   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4886     0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
4887   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4888     0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
4889   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4890     0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
4891   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4892     0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
4893   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4894     0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
4895   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4896     0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
4897   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4898     0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
4899   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4900     0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
4901   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4902     0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
4903   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4904     0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
4905   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4906     0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
4907   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4908     0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
4909   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4910     0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
4911   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4912     0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
4913   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4914     0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
4915   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4916     0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
4917   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4918     0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
4919   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4920     0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
4921   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4922     0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
4923   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4924     0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
4925   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4926     0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
4927   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4928     0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
4929   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4930     0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
4931   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4932     0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
4933   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4934     0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
4935   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4936     0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
4937   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4938     0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
4939   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4940     0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
4941   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4942     0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
4943   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4944     0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
4945   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4946     0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
4947   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4948     0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
4949   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4950     0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
4951   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4952     0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4953   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4954     0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4955   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4956     0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4957   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4958     0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
4959   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4960     0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
4961   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4962     0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
4963   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4964     0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
4965   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4966     0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
4967   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4968     0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4969   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4970     0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
4971   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4972     0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
4973   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4974     0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4975   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4976     0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4977   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4978     0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4979   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4980     0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4981   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4982     0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4983   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4984     0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4985   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4986     0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4987   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4988     0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
4989   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4990     0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
4991   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4992     0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
4993   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4994     0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
4995   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4996     0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
4997   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4998     0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
4999   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5000     0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
5001   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5002     0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
5003   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5004     0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
5005   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5006     0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
5007   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5008     0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
5009   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5010     0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
5011   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5012     0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
5013   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5014     0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
5015   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5016     0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5017   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5018     0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5019   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5020     0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5021   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5022     0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5023   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5024     0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5025   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5026     0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5027   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
5028     0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
5029   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5030     0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
5031   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5032     0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
5033   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5034     0xf810f000, 0xff70f000, "pld%c\t%a"},
5035   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5036     0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5037   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5038     0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5039   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5040     0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5041   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5042     0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5043   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5044     0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5045   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5046     0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5047   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5048     0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5049   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5050     0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
5051   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5052     0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
5053   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5054     0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
5055   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5056     0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
5057   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5058     0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
5059   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5060     0xfb100000, 0xfff000c0,
5061     "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
5062   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5063     0xfbc00080, 0xfff000c0,
5064     "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
5065   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5066     0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
5067   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5068     0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
5069   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5070     0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
5071   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5072     0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
5073   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5074     0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
5075   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
5076     0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
5077   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5078     0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
5079   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
5080     0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
5081   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5082     0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
5083   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5084     0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
5085   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5086     0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
5087   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5088     0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
5089   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5090     0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
5091   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5092     0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
5093   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5094     0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
5095   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5096     0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
5097   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5098     0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
5099   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5100     0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
5101   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
5102     0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
5103   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5104     0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
5105   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5106     0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
5107   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5108     0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
5109   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5110     0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
5111   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5112     0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
5113   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5114     0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
5115   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5116     0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
5117   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5118     0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
5119   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5120     0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
5121   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5122     0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
5123   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5124     0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
5125   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5126     0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
5127   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5128     0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
5129   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5130     0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
5131   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5132     0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
5133   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5134     0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
5135   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5136     0xe9400000, 0xff500000,
5137     "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
5138   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5139     0xe9500000, 0xff500000,
5140     "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
5141   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5142     0xe8600000, 0xff700000,
5143     "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
5144   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5145     0xe8700000, 0xff700000,
5146     "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
5147   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5148     0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
5149   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5150     0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
5151
5152   /* Filter out Bcc with cond=E or F, which are used for other instructions.  */
5153   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5154     0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
5155   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5156     0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
5157   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5158     0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
5159   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5160     0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
5161
5162   /* These have been 32-bit since the invention of Thumb.  */
5163   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
5164      0xf000c000, 0xf800d001, "blx%c\t%B%x"},
5165   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
5166      0xf000d000, 0xf800d000, "bl%c\t%B%x"},
5167
5168   /* Fallback.  */
5169   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
5170       0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
5171   {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
5172 };
5173
5174 static const char *const arm_conditional[] =
5175 {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
5176  "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
5177
5178 static const char *const arm_fp_const[] =
5179 {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
5180
5181 static const char *const arm_shift[] =
5182 {"lsl", "lsr", "asr", "ror"};
5183
5184 typedef struct
5185 {
5186   const char *name;
5187   const char *description;
5188   const char *reg_names[16];
5189 }
5190 arm_regname;
5191
5192 static const arm_regname regnames[] =
5193 {
5194   { "reg-names-raw", N_("Select raw register names"),
5195     { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
5196   { "reg-names-gcc", N_("Select register names used by GCC"),
5197     { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl",  "fp",  "ip",  "sp",  "lr",  "pc" }},
5198   { "reg-names-std", N_("Select register names used in ARM's ISA documentation"),
5199     { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp",  "lr",  "pc" }},
5200   { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL} },
5201   { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL} },
5202   { "reg-names-apcs", N_("Select register names used in the APCS"),
5203     { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl",  "fp",  "ip",  "sp",  "lr",  "pc" }},
5204   { "reg-names-atpcs", N_("Select register names used in the ATPCS"),
5205     { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7",  "v8",  "IP",  "SP",  "LR",  "PC" }},
5206   { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
5207     { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL",  "FP",  "IP",  "SP",  "LR",  "PC" }},
5208   { "coproc<N>=(cde|generic)", N_("Enable CDE extensions for coprocessor N space"), { NULL } }
5209 };
5210
5211 static const char *const iwmmxt_wwnames[] =
5212 {"b", "h", "w", "d"};
5213
5214 static const char *const iwmmxt_wwssnames[] =
5215 {"b", "bus", "bc", "bss",
5216  "h", "hus", "hc", "hss",
5217  "w", "wus", "wc", "wss",
5218  "d", "dus", "dc", "dss"
5219 };
5220
5221 static const char *const iwmmxt_regnames[] =
5222 { "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
5223   "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
5224 };
5225
5226 static const char *const iwmmxt_cregnames[] =
5227 { "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
5228   "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
5229 };
5230
5231 static const char *const vec_condnames[] =
5232 { "eq", "ne", "cs", "hi", "ge", "lt", "gt", "le"
5233 };
5234
5235 static const char *const mve_predicatenames[] =
5236 { "", "ttt", "tt", "tte", "t", "tee", "te", "tet", "",
5237   "eee", "ee", "eet", "e", "ett", "et", "ete"
5238 };
5239
5240 /* Names for 2-bit size field for mve vector isntructions.  */
5241 static const char *const mve_vec_sizename[] =
5242   { "8", "16", "32", "64"};
5243
5244 /* Indicates whether we are processing a then predicate,
5245    else predicate or none at all.  */
5246 enum vpt_pred_state
5247 {
5248   PRED_NONE,
5249   PRED_THEN,
5250   PRED_ELSE
5251 };
5252
5253 /* Information used to process a vpt block and subsequent instructions.  */
5254 struct vpt_block
5255 {
5256   /* Are we in a vpt block.  */
5257   bool in_vpt_block;
5258
5259   /* Next predicate state if in vpt block.  */
5260   enum vpt_pred_state next_pred_state;
5261
5262   /* Mask from vpt/vpst instruction.  */
5263   long predicate_mask;
5264
5265   /* Instruction number in vpt block.  */
5266   long current_insn_num;
5267
5268   /* Number of instructions in vpt block..   */
5269   long num_pred_insn;
5270 };
5271
5272 static struct vpt_block vpt_block_state =
5273 {
5274   false,
5275   PRED_NONE,
5276   0,
5277   0,
5278   0
5279 };
5280
5281 /* Default to GCC register name set.  */
5282 static unsigned int regname_selected = 1;
5283
5284 #define NUM_ARM_OPTIONS   ARRAY_SIZE (regnames)
5285 #define arm_regnames      regnames[regname_selected].reg_names
5286
5287 static bool force_thumb = false;
5288 static uint16_t cde_coprocs = 0;
5289
5290 /* Current IT instruction state.  This contains the same state as the IT
5291    bits in the CPSR.  */
5292 static unsigned int ifthen_state;
5293 /* IT state for the next instruction.  */
5294 static unsigned int ifthen_next_state;
5295 /* The address of the insn for which the IT state is valid.  */
5296 static bfd_vma ifthen_address;
5297 #define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
5298 /* Indicates that the current Conditional state is unconditional or outside
5299    an IT block.  */
5300 #define COND_UNCOND 16
5301
5302 \f
5303 /* Functions.  */
5304 /* Extract the predicate mask for a VPT or VPST instruction.
5305    The mask is composed of bits 13-15 (Mkl) and bit 22 (Mkh).  */
5306
5307 static long
5308 mve_extract_pred_mask (long given)
5309 {
5310   return ((given & 0x00400000) >> 19) | ((given & 0xe000) >> 13);
5311 }
5312
5313 /* Return the number of instructions in a MVE predicate block.  */
5314 static long
5315 num_instructions_vpt_block (long given)
5316 {
5317   long mask = mve_extract_pred_mask (given);
5318   if (mask == 0)
5319     return 0;
5320
5321   if (mask == 8)
5322     return 1;
5323
5324   if ((mask & 7) == 4)
5325     return 2;
5326
5327   if ((mask & 3) == 2)
5328     return 3;
5329
5330   if ((mask & 1) == 1)
5331     return 4;
5332
5333   return 0;
5334 }
5335
5336 static void
5337 mark_outside_vpt_block (void)
5338 {
5339   vpt_block_state.in_vpt_block = false;
5340   vpt_block_state.next_pred_state = PRED_NONE;
5341   vpt_block_state.predicate_mask = 0;
5342   vpt_block_state.current_insn_num = 0;
5343   vpt_block_state.num_pred_insn = 0;
5344 }
5345
5346 static void
5347 mark_inside_vpt_block (long given)
5348 {
5349   vpt_block_state.in_vpt_block = true;
5350   vpt_block_state.next_pred_state = PRED_THEN;
5351   vpt_block_state.predicate_mask = mve_extract_pred_mask (given);
5352   vpt_block_state.current_insn_num = 0;
5353   vpt_block_state.num_pred_insn = num_instructions_vpt_block (given);
5354   assert (vpt_block_state.num_pred_insn >= 1);
5355 }
5356
5357 static enum vpt_pred_state
5358 invert_next_predicate_state (enum vpt_pred_state astate)
5359 {
5360   if (astate == PRED_THEN)
5361     return PRED_ELSE;
5362   else if (astate == PRED_ELSE)
5363     return PRED_THEN;
5364   else
5365     return PRED_NONE;
5366 }
5367
5368 static enum vpt_pred_state
5369 update_next_predicate_state (void)
5370 {
5371   long pred_mask = vpt_block_state.predicate_mask;
5372   long mask_for_insn = 0;
5373
5374   switch (vpt_block_state.current_insn_num)
5375     {
5376     case 1:
5377       mask_for_insn = 8;
5378       break;
5379
5380     case 2:
5381       mask_for_insn = 4;
5382       break;
5383
5384     case 3:
5385       mask_for_insn = 2;
5386       break;
5387
5388     case 4:
5389       return PRED_NONE;
5390     }
5391
5392   if (pred_mask & mask_for_insn)
5393     return invert_next_predicate_state (vpt_block_state.next_pred_state);
5394   else
5395     return vpt_block_state.next_pred_state;
5396 }
5397
5398 static void
5399 update_vpt_block_state (void)
5400 {
5401   vpt_block_state.current_insn_num++;
5402   if (vpt_block_state.current_insn_num == vpt_block_state.num_pred_insn)
5403     {
5404       /* No more instructions to process in vpt block.  */
5405       mark_outside_vpt_block ();
5406       return;
5407     }
5408
5409   vpt_block_state.next_pred_state = update_next_predicate_state ();
5410 }
5411
5412 /* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
5413    Returns pointer to following character of the format string and
5414    fills in *VALUEP and *WIDTHP with the extracted value and number of
5415    bits extracted.  WIDTHP can be NULL.  */
5416
5417 static const char *
5418 arm_decode_bitfield (const char *ptr,
5419                      unsigned long insn,
5420                      unsigned long *valuep,
5421                      int *widthp)
5422 {
5423   unsigned long value = 0;
5424   int width = 0;
5425
5426   do
5427     {
5428       int start, end;
5429       int bits;
5430
5431       for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
5432         start = start * 10 + *ptr - '0';
5433       if (*ptr == '-')
5434         for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
5435           end = end * 10 + *ptr - '0';
5436       else
5437         end = start;
5438       bits = end - start;
5439       if (bits < 0)
5440         abort ();
5441       value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
5442       width += bits + 1;
5443     }
5444   while (*ptr++ == ',');
5445   *valuep = value;
5446   if (widthp)
5447     *widthp = width;
5448   return ptr - 1;
5449 }
5450
5451 static void
5452 arm_decode_shift (long given, fprintf_ftype func, void *stream,
5453                   bool print_shift)
5454 {
5455   func (stream, "%s", arm_regnames[given & 0xf]);
5456
5457   if ((given & 0xff0) != 0)
5458     {
5459       if ((given & 0x10) == 0)
5460         {
5461           int amount = (given & 0xf80) >> 7;
5462           int shift = (given & 0x60) >> 5;
5463
5464           if (amount == 0)
5465             {
5466               if (shift == 3)
5467                 {
5468                   func (stream, ", rrx");
5469                   return;
5470                 }
5471
5472               amount = 32;
5473             }
5474
5475           if (print_shift)
5476             func (stream, ", %s #%d", arm_shift[shift], amount);
5477           else
5478             func (stream, ", #%d", amount);
5479         }
5480       else if ((given & 0x80) == 0x80)
5481         func (stream, "\t; <illegal shifter operand>");
5482       else if (print_shift)
5483         func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
5484               arm_regnames[(given & 0xf00) >> 8]);
5485       else
5486         func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
5487     }
5488 }
5489
5490 /* Return TRUE if the MATCHED_INSN can be inside an IT block.  */
5491
5492 static bool
5493 is_mve_okay_in_it (enum mve_instructions matched_insn)
5494 {
5495   switch (matched_insn)
5496     {
5497     case MVE_VMOV_GP_TO_VEC_LANE:
5498     case MVE_VMOV2_VEC_LANE_TO_GP:
5499     case MVE_VMOV2_GP_TO_VEC_LANE:
5500     case MVE_VMOV_VEC_LANE_TO_GP:
5501     case MVE_LSLL:
5502     case MVE_LSLLI:
5503     case MVE_LSRL:
5504     case MVE_ASRL:
5505     case MVE_ASRLI:
5506     case MVE_SQRSHRL:
5507     case MVE_SQRSHR:
5508     case MVE_UQRSHL:
5509     case MVE_UQRSHLL:
5510     case MVE_UQSHL:
5511     case MVE_UQSHLL:
5512     case MVE_URSHRL:
5513     case MVE_URSHR:
5514     case MVE_SRSHRL:
5515     case MVE_SRSHR:
5516     case MVE_SQSHLL:
5517     case MVE_SQSHL:
5518       return true;
5519     default:
5520       return false;
5521     }
5522 }
5523
5524 static bool
5525 is_mve_architecture (struct disassemble_info *info)
5526 {
5527   struct arm_private_data *private_data = info->private_data;
5528   arm_feature_set allowed_arches = private_data->features;
5529
5530   arm_feature_set arm_ext_v8_1m_main
5531     = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
5532
5533   if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
5534       && !ARM_CPU_IS_ANY (allowed_arches))
5535     return true;
5536   else
5537     return false;
5538 }
5539
5540 static bool
5541 is_vpt_instruction (long given)
5542 {
5543
5544   /* If mkh:mkl is '0000' then its not a vpt/vpst instruction.  */
5545   if ((given & 0x0040e000) == 0)
5546     return false;
5547
5548   /* VPT floating point T1 variant.  */
5549   if (((given & 0xefb10f50) == 0xee310f00 && ((given & 0x1001) != 0x1))
5550   /* VPT floating point T2 variant.  */
5551       || ((given & 0xefb10f50) == 0xee310f40)
5552   /* VPT vector T1 variant.  */
5553       || ((given & 0xff811f51) == 0xfe010f00)
5554   /* VPT vector T2 variant.  */
5555       || ((given & 0xff811f51) == 0xfe010f01
5556           && ((given & 0x300000) != 0x300000))
5557   /* VPT vector T3 variant.  */
5558       || ((given & 0xff811f50) == 0xfe011f00)
5559   /* VPT vector T4 variant.  */
5560       || ((given & 0xff811f70) == 0xfe010f40)
5561   /* VPT vector T5 variant.  */
5562       || ((given & 0xff811f70) == 0xfe010f60)
5563   /* VPT vector T6 variant.  */
5564       || ((given & 0xff811f50) == 0xfe011f40)
5565   /* VPST vector T variant.  */
5566       || ((given & 0xffbf1fff) == 0xfe310f4d))
5567     return true;
5568   else
5569     return false;
5570 }
5571
5572 /* Decode a bitfield from opcode GIVEN, with starting bitfield = START
5573    and ending bitfield = END.  END must be greater than START.  */
5574
5575 static unsigned long
5576 arm_decode_field (unsigned long given, unsigned int start, unsigned int end)
5577 {
5578   int bits = end - start;
5579
5580   if (bits < 0)
5581     abort ();
5582
5583   return ((given >> start) & ((2ul << bits) - 1));
5584 }
5585
5586 /* Decode a bitfield from opcode GIVEN, with multiple bitfields:
5587    START:END and START2:END2.  END/END2 must be greater than
5588    START/START2.  */
5589
5590 static unsigned long
5591 arm_decode_field_multiple (unsigned long given, unsigned int start,
5592                            unsigned int end, unsigned int start2,
5593                            unsigned int end2)
5594 {
5595   int bits = end - start;
5596   int bits2 = end2 - start2;
5597   unsigned long value = 0;
5598   int width = 0;
5599
5600   if (bits2 < 0)
5601     abort ();
5602
5603   value = arm_decode_field (given, start, end);
5604   width += bits + 1;
5605
5606   value |= ((given >> start2) & ((2ul << bits2) - 1)) << width;
5607   return value;
5608 }
5609
5610 /* Return TRUE if the GIVEN encoding should not be decoded as MATCHED_INSN.
5611    This helps us decode instructions that change mnemonic depending on specific
5612    operand values/encodings.  */
5613
5614 static bool
5615 is_mve_encoding_conflict (unsigned long given,
5616                           enum mve_instructions matched_insn)
5617 {
5618   switch (matched_insn)
5619     {
5620     case MVE_VPST:
5621       if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5622         return true;
5623       else
5624         return false;
5625
5626     case MVE_VPT_FP_T1:
5627       if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5628         return true;
5629       if ((arm_decode_field (given, 12, 12) == 0)
5630           && (arm_decode_field (given, 0, 0) == 1))
5631         return true;
5632       return false;
5633
5634     case MVE_VPT_FP_T2:
5635       if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5636         return true;
5637       if (arm_decode_field (given, 0, 3) == 0xd)
5638         return true;
5639       return false;
5640
5641     case MVE_VPT_VEC_T1:
5642     case MVE_VPT_VEC_T2:
5643     case MVE_VPT_VEC_T3:
5644     case MVE_VPT_VEC_T4:
5645     case MVE_VPT_VEC_T5:
5646     case MVE_VPT_VEC_T6:
5647       if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5648         return true;
5649       if (arm_decode_field (given, 20, 21) == 3)
5650         return true;
5651       return false;
5652
5653     case MVE_VCMP_FP_T1:
5654       if ((arm_decode_field (given, 12, 12) == 0)
5655           && (arm_decode_field (given, 0, 0) == 1))
5656         return true;
5657       else
5658         return false;
5659
5660     case MVE_VCMP_FP_T2:
5661       if (arm_decode_field (given, 0, 3) == 0xd)
5662         return true;
5663       else
5664         return false;
5665
5666     case MVE_VQADD_T2:
5667     case MVE_VQSUB_T2:
5668     case MVE_VMUL_VEC_T2:
5669     case MVE_VMULH:
5670     case MVE_VRMULH:
5671     case MVE_VMLA:
5672     case MVE_VMAX:
5673     case MVE_VMIN:
5674     case MVE_VBRSR:
5675     case MVE_VADD_VEC_T2:
5676     case MVE_VSUB_VEC_T2:
5677     case MVE_VABAV:
5678     case MVE_VQRSHL_T1:
5679     case MVE_VQSHL_T4:
5680     case MVE_VRSHL_T1:
5681     case MVE_VSHL_T3:
5682     case MVE_VCADD_VEC:
5683     case MVE_VHCADD:
5684     case MVE_VDDUP:
5685     case MVE_VIDUP:
5686     case MVE_VQRDMLADH:
5687     case MVE_VQDMLAH:
5688     case MVE_VQRDMLAH:
5689     case MVE_VQDMLASH:
5690     case MVE_VQRDMLASH:
5691     case MVE_VQDMLSDH:
5692     case MVE_VQRDMLSDH:
5693     case MVE_VQDMULH_T3:
5694     case MVE_VQRDMULH_T4:
5695     case MVE_VQDMLADH:
5696     case MVE_VMLAS:
5697     case MVE_VMULL_INT:
5698     case MVE_VHADD_T2:
5699     case MVE_VHSUB_T2:
5700     case MVE_VCMP_VEC_T1:
5701     case MVE_VCMP_VEC_T2:
5702     case MVE_VCMP_VEC_T3:
5703     case MVE_VCMP_VEC_T4:
5704     case MVE_VCMP_VEC_T5:
5705     case MVE_VCMP_VEC_T6:
5706       if (arm_decode_field (given, 20, 21) == 3)
5707         return true;
5708       else
5709         return false;
5710
5711     case MVE_VLD2:
5712     case MVE_VLD4:
5713     case MVE_VST2:
5714     case MVE_VST4:
5715       if (arm_decode_field (given, 7, 8) == 3)
5716         return true;
5717       else
5718         return false;
5719
5720     case MVE_VSTRB_T1:
5721     case MVE_VSTRH_T2:
5722       if ((arm_decode_field (given, 24, 24) == 0)
5723           && (arm_decode_field (given, 21, 21) == 0))
5724         {
5725             return true;
5726         }
5727       else if ((arm_decode_field (given, 7, 8) == 3))
5728         return true;
5729       else
5730         return false;
5731
5732     case MVE_VLDRB_T1:
5733     case MVE_VLDRH_T2:
5734     case MVE_VLDRW_T7:
5735     case MVE_VSTRB_T5:
5736     case MVE_VSTRH_T6:
5737     case MVE_VSTRW_T7:
5738       if ((arm_decode_field (given, 24, 24) == 0)
5739           && (arm_decode_field (given, 21, 21) == 0))
5740         {
5741             return true;
5742         }
5743       else
5744         return false;
5745
5746     case MVE_VCVT_FP_FIX_VEC:
5747       return (arm_decode_field (given, 16, 21) & 0x38) == 0;
5748
5749     case MVE_VBIC_IMM:
5750     case MVE_VORR_IMM:
5751       {
5752         unsigned long cmode = arm_decode_field (given, 8, 11);
5753
5754         if ((cmode & 1) == 0)
5755           return true;
5756         else if ((cmode & 0xc) == 0xc)
5757           return true;
5758         else
5759           return false;
5760       }
5761
5762     case MVE_VMVN_IMM:
5763       {
5764         unsigned long cmode = arm_decode_field (given, 8, 11);
5765
5766         if (cmode == 0xe)
5767           return true;
5768         else if ((cmode & 0x9) == 1)
5769           return true;
5770         else if ((cmode & 0xd) == 9)
5771           return true;
5772         else
5773           return false;
5774       }
5775
5776     case MVE_VMOV_IMM_TO_VEC:
5777       if ((arm_decode_field (given, 5, 5) == 1)
5778           && (arm_decode_field (given, 8, 11) != 0xe))
5779         return true;
5780       else
5781         return false;
5782
5783     case MVE_VMOVL:
5784       {
5785         unsigned long size = arm_decode_field (given, 19, 20);
5786         if ((size == 0) || (size == 3))
5787           return true;
5788         else
5789           return false;
5790       }
5791
5792     case MVE_VMAXA:
5793     case MVE_VMINA:
5794     case MVE_VMAXV:
5795     case MVE_VMAXAV:
5796     case MVE_VMINV:
5797     case MVE_VMINAV:
5798     case MVE_VQRSHL_T2:
5799     case MVE_VQSHL_T1:
5800     case MVE_VRSHL_T2:
5801     case MVE_VSHL_T2:
5802     case MVE_VSHLL_T2:
5803     case MVE_VADDV:
5804     case MVE_VMOVN:
5805     case MVE_VQMOVUN:
5806     case MVE_VQMOVN:
5807       if (arm_decode_field (given, 18, 19) == 3)
5808         return true;
5809       else
5810         return false;
5811
5812     case MVE_VMLSLDAV:
5813     case MVE_VRMLSLDAVH:
5814     case MVE_VMLALDAV:
5815     case MVE_VADDLV:
5816       if (arm_decode_field (given, 20, 22) == 7)
5817         return true;
5818       else
5819         return false;
5820
5821     case MVE_VRMLALDAVH:
5822       if ((arm_decode_field (given, 20, 22) & 6) == 6)
5823         return true;
5824       else
5825         return false;
5826
5827     case MVE_VDWDUP:
5828     case MVE_VIWDUP:
5829       if ((arm_decode_field (given, 20, 21) == 3)
5830           || (arm_decode_field (given, 1, 3) == 7))
5831         return true;
5832       else
5833         return false;
5834
5835
5836     case MVE_VSHLL_T1:
5837       if (arm_decode_field (given, 16, 18) == 0)
5838         {
5839           unsigned long sz = arm_decode_field (given, 19, 20);
5840
5841           if ((sz == 1) || (sz == 2))
5842             return true;
5843           else
5844             return false;
5845         }
5846       else
5847         return false;
5848
5849     case MVE_VQSHL_T2:
5850     case MVE_VQSHLU_T3:
5851     case MVE_VRSHR:
5852     case MVE_VSHL_T1:
5853     case MVE_VSHR:
5854     case MVE_VSLI:
5855     case MVE_VSRI:
5856       if (arm_decode_field (given, 19, 21) == 0)
5857         return true;
5858       else
5859         return false;
5860
5861     case MVE_VCTP:
5862     if (arm_decode_field (given, 16, 19) == 0xf)
5863       return true;
5864     else
5865       return false;
5866
5867     case MVE_ASRLI:
5868     case MVE_ASRL:
5869     case MVE_LSLLI:
5870     case MVE_LSLL:
5871     case MVE_LSRL:
5872     case MVE_SQRSHRL:
5873     case MVE_SQSHLL:
5874     case MVE_SRSHRL:
5875     case MVE_UQRSHLL:
5876     case MVE_UQSHLL:
5877     case MVE_URSHRL:
5878       if (arm_decode_field (given, 9, 11) == 0x7)
5879         return true;
5880       else
5881         return false;
5882
5883     case MVE_CSINC:
5884     case MVE_CSINV:
5885       {
5886         unsigned long rm, rn;
5887         rm = arm_decode_field (given, 0, 3);
5888         rn = arm_decode_field (given, 16, 19);
5889         /* CSET/CSETM.  */
5890         if (rm == 0xf && rn == 0xf)
5891           return true;
5892         /* CINC/CINV.  */
5893         else if (rn == rm && rn != 0xf)
5894           return true;
5895       }
5896     /* Fall through.  */
5897     case MVE_CSEL:
5898     case MVE_CSNEG:
5899       if (arm_decode_field (given, 0, 3) == 0xd)
5900         return true;
5901       /* CNEG.  */
5902       else if (matched_insn == MVE_CSNEG)
5903         if (arm_decode_field (given, 0, 3) == arm_decode_field (given, 16, 19))
5904           return true;
5905       return false;
5906
5907     default:
5908     case MVE_VADD_FP_T1:
5909     case MVE_VADD_FP_T2:
5910     case MVE_VADD_VEC_T1:
5911       return false;
5912
5913     }
5914 }
5915
5916 static void
5917 print_mve_vld_str_addr (struct disassemble_info *info,
5918                         unsigned long given,
5919                         enum mve_instructions matched_insn)
5920 {
5921   void *stream = info->stream;
5922   fprintf_ftype func = info->fprintf_func;
5923
5924   unsigned long p, w, gpr, imm, add, mod_imm;
5925
5926   imm = arm_decode_field (given, 0, 6);
5927   mod_imm = imm;
5928
5929   switch (matched_insn)
5930     {
5931     case MVE_VLDRB_T1:
5932     case MVE_VSTRB_T1:
5933       gpr = arm_decode_field (given, 16, 18);
5934       break;
5935
5936     case MVE_VLDRH_T2:
5937     case MVE_VSTRH_T2:
5938       gpr = arm_decode_field (given, 16, 18);
5939       mod_imm = imm << 1;
5940       break;
5941
5942     case MVE_VLDRH_T6:
5943     case MVE_VSTRH_T6:
5944       gpr = arm_decode_field (given, 16, 19);
5945       mod_imm = imm << 1;
5946       break;
5947
5948     case MVE_VLDRW_T7:
5949     case MVE_VSTRW_T7:
5950       gpr = arm_decode_field (given, 16, 19);
5951       mod_imm = imm << 2;
5952       break;
5953
5954     case MVE_VLDRB_T5:
5955     case MVE_VSTRB_T5:
5956       gpr = arm_decode_field (given, 16, 19);
5957       break;
5958
5959     default:
5960       return;
5961     }
5962
5963   p = arm_decode_field (given, 24, 24);
5964   w = arm_decode_field (given, 21, 21);
5965
5966   add = arm_decode_field (given, 23, 23);
5967
5968   char * add_sub;
5969
5970   /* Don't print anything for '+' as it is implied.  */
5971   if (add == 1)
5972     add_sub = "";
5973   else
5974     add_sub = "-";
5975
5976   if (p == 1)
5977     {
5978       /* Offset mode.  */
5979       if (w == 0)
5980         func (stream, "[%s, #%s%lu]", arm_regnames[gpr], add_sub, mod_imm);
5981       /* Pre-indexed mode.  */
5982       else
5983         func (stream, "[%s, #%s%lu]!", arm_regnames[gpr], add_sub, mod_imm);
5984     }
5985   else if ((p == 0) && (w == 1))
5986     /* Post-index mode.  */
5987     func (stream, "[%s], #%s%lu", arm_regnames[gpr], add_sub, mod_imm);
5988 }
5989
5990 /* Return FALSE if GIVEN is not an undefined encoding for MATCHED_INSN.
5991    Otherwise, return TRUE and set UNDEFINED_CODE to give a reason as to why
5992    this encoding is undefined.  */
5993
5994 static bool
5995 is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
5996                   enum mve_undefined *undefined_code)
5997 {
5998   *undefined_code = UNDEF_NONE;
5999
6000   switch (matched_insn)
6001     {
6002     case MVE_VDUP:
6003       if (arm_decode_field_multiple (given, 5, 5, 22, 22) == 3)
6004         {
6005           *undefined_code = UNDEF_SIZE_3;
6006           return true;
6007         }
6008       else
6009         return false;
6010
6011     case MVE_VQADD_T1:
6012     case MVE_VQSUB_T1:
6013     case MVE_VMUL_VEC_T1:
6014     case MVE_VABD_VEC:
6015     case MVE_VADD_VEC_T1:
6016     case MVE_VSUB_VEC_T1:
6017     case MVE_VQDMULH_T1:
6018     case MVE_VQRDMULH_T2:
6019     case MVE_VRHADD:
6020     case MVE_VHADD_T1:
6021     case MVE_VHSUB_T1:
6022       if (arm_decode_field (given, 20, 21) == 3)
6023         {
6024           *undefined_code = UNDEF_SIZE_3;
6025           return true;
6026         }
6027       else
6028         return false;
6029
6030     case MVE_VLDRB_T1:
6031       if (arm_decode_field (given, 7, 8) == 3)
6032         {
6033           *undefined_code = UNDEF_SIZE_3;
6034           return true;
6035         }
6036       else
6037         return false;
6038
6039     case MVE_VLDRH_T2:
6040       if (arm_decode_field (given, 7, 8) <= 1)
6041         {
6042           *undefined_code = UNDEF_SIZE_LE_1;
6043           return true;
6044         }
6045       else
6046         return false;
6047
6048     case MVE_VSTRB_T1:
6049       if ((arm_decode_field (given, 7, 8) == 0))
6050         {
6051           *undefined_code = UNDEF_SIZE_0;
6052           return true;
6053         }
6054       else
6055         return false;
6056
6057     case MVE_VSTRH_T2:
6058       if ((arm_decode_field (given, 7, 8) <= 1))
6059         {
6060           *undefined_code = UNDEF_SIZE_LE_1;
6061           return true;
6062         }
6063       else
6064         return false;
6065
6066     case MVE_VLDRB_GATHER_T1:
6067       if (arm_decode_field (given, 7, 8) == 3)
6068         {
6069           *undefined_code = UNDEF_SIZE_3;
6070           return true;
6071         }
6072       else if ((arm_decode_field (given, 28, 28) == 0)
6073                && (arm_decode_field (given, 7, 8) == 0))
6074         {
6075           *undefined_code = UNDEF_NOT_UNS_SIZE_0;
6076           return true;
6077         }
6078       else
6079         return false;
6080
6081     case MVE_VLDRH_GATHER_T2:
6082       if (arm_decode_field (given, 7, 8) == 3)
6083         {
6084           *undefined_code = UNDEF_SIZE_3;
6085           return true;
6086         }
6087       else if ((arm_decode_field (given, 28, 28) == 0)
6088                && (arm_decode_field (given, 7, 8) == 1))
6089         {
6090           *undefined_code = UNDEF_NOT_UNS_SIZE_1;
6091           return true;
6092         }
6093       else if (arm_decode_field (given, 7, 8) == 0)
6094         {
6095           *undefined_code = UNDEF_SIZE_0;
6096           return true;
6097         }
6098       else
6099         return false;
6100
6101     case MVE_VLDRW_GATHER_T3:
6102       if (arm_decode_field (given, 7, 8) != 2)
6103         {
6104           *undefined_code = UNDEF_SIZE_NOT_2;
6105           return true;
6106         }
6107       else if (arm_decode_field (given, 28, 28) == 0)
6108         {
6109           *undefined_code = UNDEF_NOT_UNSIGNED;
6110           return true;
6111         }
6112       else
6113         return false;
6114
6115     case MVE_VLDRD_GATHER_T4:
6116       if (arm_decode_field (given, 7, 8) != 3)
6117         {
6118           *undefined_code = UNDEF_SIZE_NOT_3;
6119           return true;
6120         }
6121       else if (arm_decode_field (given, 28, 28) == 0)
6122         {
6123           *undefined_code = UNDEF_NOT_UNSIGNED;
6124           return true;
6125         }
6126       else
6127         return false;
6128
6129     case MVE_VSTRB_SCATTER_T1:
6130       if (arm_decode_field (given, 7, 8) == 3)
6131         {
6132           *undefined_code = UNDEF_SIZE_3;
6133           return true;
6134         }
6135       else
6136         return false;
6137
6138     case MVE_VSTRH_SCATTER_T2:
6139       {
6140         unsigned long size = arm_decode_field (given, 7, 8);
6141         if (size == 3)
6142           {
6143             *undefined_code = UNDEF_SIZE_3;
6144             return true;
6145           }
6146         else if (size == 0)
6147           {
6148             *undefined_code = UNDEF_SIZE_0;
6149             return true;
6150           }
6151         else
6152           return false;
6153       }
6154
6155     case MVE_VSTRW_SCATTER_T3:
6156       if (arm_decode_field (given, 7, 8) != 2)
6157         {
6158           *undefined_code = UNDEF_SIZE_NOT_2;
6159           return true;
6160         }
6161       else
6162         return false;
6163
6164     case MVE_VSTRD_SCATTER_T4:
6165       if (arm_decode_field (given, 7, 8) != 3)
6166         {
6167           *undefined_code = UNDEF_SIZE_NOT_3;
6168           return true;
6169         }
6170       else
6171         return false;
6172
6173     case MVE_VCVT_FP_FIX_VEC:
6174       {
6175         unsigned long imm6 = arm_decode_field (given, 16, 21);
6176         if ((imm6 & 0x20) == 0)
6177           {
6178             *undefined_code = UNDEF_VCVT_IMM6;
6179             return true;
6180           }
6181
6182         if ((arm_decode_field (given, 9, 9) == 0)
6183             && ((imm6 & 0x30) == 0x20))
6184           {
6185             *undefined_code = UNDEF_VCVT_FSI_IMM6;
6186             return true;
6187           }
6188
6189         return false;
6190       }
6191
6192     case MVE_VNEG_FP:
6193     case MVE_VABS_FP:
6194     case MVE_VCVT_BETWEEN_FP_INT:
6195     case MVE_VCVT_FROM_FP_TO_INT:
6196       {
6197         unsigned long size = arm_decode_field (given, 18, 19);
6198         if (size == 0)
6199           {
6200             *undefined_code = UNDEF_SIZE_0;
6201             return true;
6202           }
6203         else if (size == 3)
6204           {
6205             *undefined_code = UNDEF_SIZE_3;
6206             return true;
6207           }
6208         else
6209           return false;
6210       }
6211
6212     case MVE_VMOV_VEC_LANE_TO_GP:
6213       {
6214         unsigned long op1 = arm_decode_field (given, 21, 22);
6215         unsigned long op2 = arm_decode_field (given, 5, 6);
6216         unsigned long u = arm_decode_field (given, 23, 23);
6217
6218         if ((op2 == 0) && (u == 1))
6219           {
6220             if ((op1 == 0) || (op1 == 1))
6221               {
6222                 *undefined_code = UNDEF_BAD_U_OP1_OP2;
6223                 return true;
6224               }
6225             else
6226               return false;
6227           }
6228         else if (op2 == 2)
6229           {
6230             if ((op1 == 0) || (op1 == 1))
6231               {
6232                 *undefined_code = UNDEF_BAD_OP1_OP2;
6233                 return true;
6234               }
6235             else
6236               return false;
6237           }
6238
6239         return false;
6240       }
6241
6242     case MVE_VMOV_GP_TO_VEC_LANE:
6243       if (arm_decode_field (given, 5, 6) == 2)
6244         {
6245           unsigned long op1 = arm_decode_field (given, 21, 22);
6246           if ((op1 == 0) || (op1 == 1))
6247             {
6248               *undefined_code = UNDEF_BAD_OP1_OP2;
6249               return true;
6250             }
6251           else
6252             return false;
6253         }
6254       else
6255         return false;
6256
6257     case MVE_VMOV_VEC_TO_VEC:
6258       if ((arm_decode_field (given, 5, 5) == 1)
6259           || (arm_decode_field (given, 22, 22) == 1))
6260           return true;
6261       return false;
6262
6263     case MVE_VMOV_IMM_TO_VEC:
6264       if (arm_decode_field (given, 5, 5) == 0)
6265       {
6266         unsigned long cmode = arm_decode_field (given, 8, 11);
6267
6268         if (((cmode & 9) == 1) || ((cmode & 5) == 1))
6269           {
6270             *undefined_code = UNDEF_OP_0_BAD_CMODE;
6271             return true;
6272           }
6273         else
6274           return false;
6275       }
6276       else
6277         return false;
6278
6279     case MVE_VSHLL_T2:
6280     case MVE_VMOVN:
6281       if (arm_decode_field (given, 18, 19) == 2)
6282         {
6283           *undefined_code = UNDEF_SIZE_2;
6284           return true;
6285         }
6286       else
6287         return false;
6288
6289     case MVE_VRMLALDAVH:
6290     case MVE_VMLADAV_T1:
6291     case MVE_VMLADAV_T2:
6292     case MVE_VMLALDAV:
6293       if ((arm_decode_field (given, 28, 28) == 1)
6294           && (arm_decode_field (given, 12, 12) == 1))
6295         {
6296           *undefined_code = UNDEF_XCHG_UNS;
6297           return true;
6298         }
6299       else
6300         return false;
6301
6302     case MVE_VQSHRN:
6303     case MVE_VQSHRUN:
6304     case MVE_VSHLL_T1:
6305     case MVE_VSHRN:
6306       {
6307         unsigned long sz = arm_decode_field (given, 19, 20);
6308         if (sz == 1)
6309           return false;
6310         else if ((sz & 2) == 2)
6311           return false;
6312         else
6313           {
6314             *undefined_code = UNDEF_SIZE;
6315             return true;
6316           }
6317       }
6318       break;
6319
6320     case MVE_VQSHL_T2:
6321     case MVE_VQSHLU_T3:
6322     case MVE_VRSHR:
6323     case MVE_VSHL_T1:
6324     case MVE_VSHR:
6325     case MVE_VSLI:
6326     case MVE_VSRI:
6327       {
6328         unsigned long sz = arm_decode_field (given, 19, 21);
6329         if ((sz & 7) == 1)
6330           return false;
6331         else if ((sz & 6) == 2)
6332           return false;
6333         else if ((sz & 4) == 4)
6334           return false;
6335         else
6336           {
6337             *undefined_code = UNDEF_SIZE;
6338             return true;
6339           }
6340       }
6341
6342     case MVE_VQRSHRN:
6343     case MVE_VQRSHRUN:
6344       if (arm_decode_field (given, 19, 20) == 0)
6345         {
6346           *undefined_code = UNDEF_SIZE_0;
6347           return true;
6348         }
6349       else
6350         return false;
6351
6352     case MVE_VABS_VEC:
6353         if (arm_decode_field (given, 18, 19) == 3)
6354         {
6355           *undefined_code = UNDEF_SIZE_3;
6356           return true;
6357         }
6358         else
6359           return false;
6360
6361     case MVE_VQNEG:
6362     case MVE_VQABS:
6363     case MVE_VNEG_VEC:
6364     case MVE_VCLS:
6365     case MVE_VCLZ:
6366       if (arm_decode_field (given, 18, 19) == 3)
6367         {
6368           *undefined_code = UNDEF_SIZE_3;
6369           return true;
6370         }
6371       else
6372         return false;
6373
6374     case MVE_VREV16:
6375       if (arm_decode_field (given, 18, 19) == 0)
6376         return false;
6377       else
6378         {
6379           *undefined_code = UNDEF_SIZE_NOT_0;
6380           return true;
6381         }
6382
6383     case MVE_VREV32:
6384       {
6385         unsigned long size = arm_decode_field (given, 18, 19);
6386         if ((size & 2) == 2)
6387           {
6388             *undefined_code = UNDEF_SIZE_2;
6389             return true;
6390           }
6391         else
6392           return false;
6393       }
6394
6395     case MVE_VREV64:
6396       if (arm_decode_field (given, 18, 19) != 3)
6397         return false;
6398       else
6399         {
6400           *undefined_code = UNDEF_SIZE_3;
6401           return true;
6402         }
6403
6404     default:
6405       return false;
6406     }
6407 }
6408
6409 /* Return FALSE if GIVEN is not an unpredictable encoding for MATCHED_INSN.
6410    Otherwise, return TRUE and set UNPREDICTABLE_CODE to give a reason as to
6411    why this encoding is unpredictable.  */
6412
6413 static bool
6414 is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
6415                       enum mve_unpredictable *unpredictable_code)
6416 {
6417   *unpredictable_code = UNPRED_NONE;
6418
6419   switch (matched_insn)
6420     {
6421     case MVE_VCMP_FP_T2:
6422     case MVE_VPT_FP_T2:
6423       if ((arm_decode_field (given, 12, 12) == 0)
6424           && (arm_decode_field (given, 5, 5) == 1))
6425         {
6426           *unpredictable_code = UNPRED_FCA_0_FCB_1;
6427           return true;
6428         }
6429       else
6430         return false;
6431
6432     case MVE_VPT_VEC_T4:
6433     case MVE_VPT_VEC_T5:
6434     case MVE_VPT_VEC_T6:
6435     case MVE_VCMP_VEC_T4:
6436     case MVE_VCMP_VEC_T5:
6437     case MVE_VCMP_VEC_T6:
6438       if (arm_decode_field (given, 0, 3) == 0xd)
6439         {
6440           *unpredictable_code = UNPRED_R13;
6441           return true;
6442         }
6443       else
6444         return false;
6445
6446     case MVE_VDUP:
6447       {
6448         unsigned long gpr = arm_decode_field (given, 12, 15);
6449         if (gpr == 0xd)
6450           {
6451             *unpredictable_code = UNPRED_R13;
6452             return true;
6453           }
6454         else if (gpr == 0xf)
6455           {
6456             *unpredictable_code = UNPRED_R15;
6457             return true;
6458           }
6459
6460         return false;
6461       }
6462
6463     case MVE_VQADD_T2:
6464     case MVE_VQSUB_T2:
6465     case MVE_VMUL_FP_T2:
6466     case MVE_VMUL_VEC_T2:
6467     case MVE_VMLA:
6468     case MVE_VBRSR:
6469     case MVE_VADD_FP_T2:
6470     case MVE_VSUB_FP_T2:
6471     case MVE_VADD_VEC_T2:
6472     case MVE_VSUB_VEC_T2:
6473     case MVE_VQRSHL_T2:
6474     case MVE_VQSHL_T1:
6475     case MVE_VRSHL_T2:
6476     case MVE_VSHL_T2:
6477     case MVE_VSHLC:
6478     case MVE_VQDMLAH:
6479     case MVE_VQRDMLAH:
6480     case MVE_VQDMLASH:
6481     case MVE_VQRDMLASH:
6482     case MVE_VQDMULH_T3:
6483     case MVE_VQRDMULH_T4:
6484     case MVE_VMLAS:
6485     case MVE_VFMA_FP_SCALAR:
6486     case MVE_VFMAS_FP_SCALAR:
6487     case MVE_VHADD_T2:
6488     case MVE_VHSUB_T2:
6489       {
6490         unsigned long gpr = arm_decode_field (given, 0, 3);
6491         if (gpr == 0xd)
6492           {
6493             *unpredictable_code = UNPRED_R13;
6494             return true;
6495           }
6496         else if (gpr == 0xf)
6497           {
6498             *unpredictable_code = UNPRED_R15;
6499             return true;
6500           }
6501
6502         return false;
6503       }
6504
6505     case MVE_VLD2:
6506     case MVE_VST2:
6507       {
6508         unsigned long rn = arm_decode_field (given, 16, 19);
6509
6510         if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6511           {
6512             *unpredictable_code = UNPRED_R13_AND_WB;
6513             return true;
6514           }
6515
6516         if (rn == 0xf)
6517           {
6518             *unpredictable_code = UNPRED_R15;
6519             return true;
6520           }
6521
6522         if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 6)
6523           {
6524             *unpredictable_code = UNPRED_Q_GT_6;
6525             return true;
6526           }
6527         else
6528           return false;
6529       }
6530
6531     case MVE_VLD4:
6532     case MVE_VST4:
6533       {
6534         unsigned long rn = arm_decode_field (given, 16, 19);
6535
6536         if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6537           {
6538             *unpredictable_code = UNPRED_R13_AND_WB;
6539             return true;
6540           }
6541
6542         if (rn == 0xf)
6543           {
6544             *unpredictable_code = UNPRED_R15;
6545             return true;
6546           }
6547
6548         if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 4)
6549           {
6550             *unpredictable_code = UNPRED_Q_GT_4;
6551             return true;
6552           }
6553         else
6554           return false;
6555       }
6556
6557     case MVE_VLDRB_T5:
6558     case MVE_VLDRH_T6:
6559     case MVE_VLDRW_T7:
6560     case MVE_VSTRB_T5:
6561     case MVE_VSTRH_T6:
6562     case MVE_VSTRW_T7:
6563       {
6564         unsigned long rn = arm_decode_field (given, 16, 19);
6565
6566         if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6567           {
6568             *unpredictable_code = UNPRED_R13_AND_WB;
6569             return true;
6570           }
6571         else if (rn == 0xf)
6572           {
6573             *unpredictable_code = UNPRED_R15;
6574             return true;
6575           }
6576         else
6577           return false;
6578       }
6579
6580     case MVE_VLDRB_GATHER_T1:
6581       if (arm_decode_field (given, 0, 0) == 1)
6582         {
6583           *unpredictable_code = UNPRED_OS;
6584           return true;
6585         }
6586
6587       /*  fall through.  */
6588       /* To handle common code with T2-T4 variants.  */
6589     case MVE_VLDRH_GATHER_T2:
6590     case MVE_VLDRW_GATHER_T3:
6591     case MVE_VLDRD_GATHER_T4:
6592       {
6593         unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6594         unsigned long qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6595
6596         if (qd == qm)
6597           {
6598             *unpredictable_code = UNPRED_Q_REGS_EQUAL;
6599             return true;
6600           }
6601
6602         if (arm_decode_field (given, 16, 19) == 0xf)
6603           {
6604             *unpredictable_code = UNPRED_R15;
6605             return true;
6606           }
6607
6608         return false;
6609       }
6610
6611     case MVE_VLDRW_GATHER_T5:
6612     case MVE_VLDRD_GATHER_T6:
6613       {
6614         unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6615         unsigned long qm = arm_decode_field_multiple (given, 17, 19, 7, 7);
6616
6617         if (qd == qm)
6618           {
6619             *unpredictable_code = UNPRED_Q_REGS_EQUAL;
6620             return true;
6621           }
6622         else
6623           return false;
6624       }
6625
6626     case MVE_VSTRB_SCATTER_T1:
6627       if (arm_decode_field (given, 16, 19) == 0xf)
6628         {
6629           *unpredictable_code = UNPRED_R15;
6630           return true;
6631         }
6632       else if (arm_decode_field (given, 0, 0) == 1)
6633         {
6634           *unpredictable_code = UNPRED_OS;
6635           return true;
6636         }
6637       else
6638         return false;
6639
6640     case MVE_VSTRH_SCATTER_T2:
6641     case MVE_VSTRW_SCATTER_T3:
6642     case MVE_VSTRD_SCATTER_T4:
6643       if (arm_decode_field (given, 16, 19) == 0xf)
6644         {
6645           *unpredictable_code = UNPRED_R15;
6646           return true;
6647         }
6648       else
6649         return false;
6650
6651     case MVE_VMOV2_VEC_LANE_TO_GP:
6652     case MVE_VMOV2_GP_TO_VEC_LANE:
6653     case MVE_VCVT_BETWEEN_FP_INT:
6654     case MVE_VCVT_FROM_FP_TO_INT:
6655       {
6656         unsigned long rt = arm_decode_field (given, 0, 3);
6657         unsigned long rt2 = arm_decode_field (given, 16, 19);
6658
6659         if ((rt == 0xd) || (rt2 == 0xd))
6660           {
6661             *unpredictable_code = UNPRED_R13;
6662             return true;
6663           }
6664         else if ((rt == 0xf) || (rt2 == 0xf))
6665           {
6666             *unpredictable_code = UNPRED_R15;
6667             return true;
6668           }
6669         else if (rt == rt2 && matched_insn != MVE_VMOV2_GP_TO_VEC_LANE)
6670           {
6671             *unpredictable_code = UNPRED_GP_REGS_EQUAL;
6672             return true;
6673           }
6674
6675         return false;
6676       }
6677
6678     case MVE_VMAXV:
6679     case MVE_VMAXAV:
6680     case MVE_VMAXNMV_FP:
6681     case MVE_VMAXNMAV_FP:
6682     case MVE_VMINNMV_FP:
6683     case MVE_VMINNMAV_FP:
6684     case MVE_VMINV:
6685     case MVE_VMINAV:
6686     case MVE_VABAV:
6687     case MVE_VMOV_HFP_TO_GP:
6688     case MVE_VMOV_GP_TO_VEC_LANE:
6689     case MVE_VMOV_VEC_LANE_TO_GP:
6690       {
6691         unsigned long rda = arm_decode_field (given, 12, 15);
6692         if (rda == 0xd)
6693           {
6694             *unpredictable_code = UNPRED_R13;
6695             return true;
6696           }
6697         else if (rda == 0xf)
6698           {
6699             *unpredictable_code = UNPRED_R15;
6700             return true;
6701           }
6702
6703         return false;
6704       }
6705
6706     case MVE_VMULL_INT:
6707       {
6708         unsigned long Qd;
6709         unsigned long Qm;
6710         unsigned long Qn;
6711
6712         if (arm_decode_field (given, 20, 21) == 2)
6713           {
6714             Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6715             Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6716             Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6717
6718             if ((Qd == Qn) || (Qd == Qm))
6719               {
6720                 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2;
6721                 return true;
6722               }
6723             else
6724               return false;
6725           }
6726         else
6727           return false;
6728       }
6729
6730     case MVE_VCMUL_FP:
6731     case MVE_VQDMULL_T1:
6732       {
6733         unsigned long Qd;
6734         unsigned long Qm;
6735         unsigned long Qn;
6736
6737         if (arm_decode_field (given, 28, 28) == 1)
6738           {
6739             Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6740             Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6741             Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6742
6743             if ((Qd == Qn) || (Qd == Qm))
6744               {
6745                 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6746                 return true;
6747               }
6748             else
6749               return false;
6750           }
6751         else
6752           return false;
6753       }
6754
6755     case MVE_VQDMULL_T2:
6756       {
6757         unsigned long gpr = arm_decode_field (given, 0, 3);
6758         if (gpr == 0xd)
6759           {
6760             *unpredictable_code = UNPRED_R13;
6761             return true;
6762           }
6763         else if (gpr == 0xf)
6764           {
6765             *unpredictable_code = UNPRED_R15;
6766             return true;
6767           }
6768
6769         if (arm_decode_field (given, 28, 28) == 1)
6770           {
6771             unsigned long Qd
6772               = arm_decode_field_multiple (given, 13, 15, 22, 22);
6773             unsigned long Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6774
6775             if (Qd == Qn)
6776               {
6777                 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6778                 return true;
6779               }
6780             else
6781               return false;
6782           }
6783
6784         return false;
6785       }
6786
6787     case MVE_VMLSLDAV:
6788     case MVE_VRMLSLDAVH:
6789     case MVE_VMLALDAV:
6790     case MVE_VADDLV:
6791       if (arm_decode_field (given, 20, 22) == 6)
6792         {
6793           *unpredictable_code = UNPRED_R13;
6794           return true;
6795         }
6796       else
6797         return false;
6798
6799     case MVE_VDWDUP:
6800     case MVE_VIWDUP:
6801       if (arm_decode_field (given, 1, 3) == 6)
6802         {
6803           *unpredictable_code = UNPRED_R13;
6804           return true;
6805         }
6806       else
6807         return false;
6808
6809     case MVE_VCADD_VEC:
6810     case MVE_VHCADD:
6811       {
6812         unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6813         unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6814         if ((Qd == Qm) && arm_decode_field (given, 20, 21) == 2)
6815           {
6816             *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2;
6817             return true;
6818           }
6819         else
6820           return false;
6821       }
6822
6823     case MVE_VCADD_FP:
6824       {
6825         unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6826         unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6827         if ((Qd == Qm) && arm_decode_field (given, 20, 20) == 1)
6828           {
6829             *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6830             return true;
6831           }
6832         else
6833           return false;
6834       }
6835
6836     case MVE_VCMLA_FP:
6837       {
6838         unsigned long Qda;
6839         unsigned long Qm;
6840         unsigned long Qn;
6841
6842         if (arm_decode_field (given, 20, 20) == 1)
6843           {
6844             Qda = arm_decode_field_multiple (given, 13, 15, 22, 22);
6845             Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6846             Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6847
6848             if ((Qda == Qn) || (Qda == Qm))
6849               {
6850                 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6851                 return true;
6852               }
6853             else
6854               return false;
6855           }
6856         else
6857           return false;
6858
6859       }
6860
6861     case MVE_VCTP:
6862       if (arm_decode_field (given, 16, 19) == 0xd)
6863         {
6864           *unpredictable_code = UNPRED_R13;
6865           return true;
6866         }
6867       else
6868         return false;
6869
6870     case MVE_VREV64:
6871       {
6872         unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6873         unsigned long qm = arm_decode_field_multiple (given, 1, 3, 6, 6);
6874
6875         if (qd == qm)
6876           {
6877             *unpredictable_code = UNPRED_Q_REGS_EQUAL;
6878             return true;
6879           }
6880         else
6881           return false;
6882       }
6883
6884     case MVE_LSLL:
6885     case MVE_LSLLI:
6886     case MVE_LSRL:
6887     case MVE_ASRL:
6888     case MVE_ASRLI:
6889     case MVE_UQSHLL:
6890     case MVE_UQRSHLL:
6891     case MVE_URSHRL:
6892     case MVE_SRSHRL:
6893     case MVE_SQSHLL:
6894     case MVE_SQRSHRL:
6895       {
6896         unsigned long gpr = arm_decode_field (given, 9, 11);
6897         gpr = ((gpr << 1) | 1);
6898         if (gpr == 0xd)
6899           {
6900             *unpredictable_code = UNPRED_R13;
6901             return true;
6902           }
6903         else if (gpr == 0xf)
6904           {
6905             *unpredictable_code = UNPRED_R15;
6906             return true;
6907           }
6908
6909         return false;
6910       }
6911
6912     default:
6913       return false;
6914     }
6915 }
6916
6917 static void
6918 print_mve_vmov_index (struct disassemble_info *info, unsigned long given)
6919 {
6920   unsigned long op1 = arm_decode_field (given, 21, 22);
6921   unsigned long op2 = arm_decode_field (given, 5, 6);
6922   unsigned long h = arm_decode_field (given, 16, 16);
6923   unsigned long index_operand, esize, targetBeat, idx;
6924   void *stream = info->stream;
6925   fprintf_ftype func = info->fprintf_func;
6926
6927   if ((op1 & 0x2) == 0x2)
6928     {
6929       index_operand = op2;
6930       esize = 8;
6931     }
6932   else if (((op1 & 0x2) == 0x0) && ((op2 & 0x1) == 0x1))
6933     {
6934       index_operand = op2  >> 1;
6935       esize = 16;
6936     }
6937   else if (((op1 & 0x2) == 0) && ((op2 & 0x3) == 0))
6938     {
6939       index_operand = 0;
6940       esize = 32;
6941     }
6942   else
6943     {
6944       func (stream, "<undefined index>");
6945       return;
6946     }
6947
6948   targetBeat =  (op1 & 0x1) | (h << 1);
6949   idx = index_operand + targetBeat * (32/esize);
6950
6951   func (stream, "%lu", idx);
6952 }
6953
6954 /* Print neon and mve 8-bit immediate that can be a 8, 16, 32, or 64-bits
6955    in length and integer of floating-point type.  */
6956 static void
6957 print_simd_imm8 (struct disassemble_info *info, unsigned long given,
6958                  unsigned int ibit_loc, const struct mopcode32 *insn)
6959 {
6960   int bits = 0;
6961   int cmode = (given >> 8) & 0xf;
6962   int op = (given >> 5) & 0x1;
6963   unsigned long value = 0, hival = 0;
6964   unsigned shift;
6965   int size = 0;
6966   int isfloat = 0;
6967   void *stream = info->stream;
6968   fprintf_ftype func = info->fprintf_func;
6969
6970   /* On Neon the 'i' bit is at bit 24, on mve it is
6971      at bit 28.  */
6972   bits |= ((given >> ibit_loc) & 1) << 7;
6973   bits |= ((given >> 16) & 7) << 4;
6974   bits |= ((given >> 0) & 15) << 0;
6975
6976   if (cmode < 8)
6977     {
6978       shift = (cmode >> 1) & 3;
6979       value = (unsigned long) bits << (8 * shift);
6980       size = 32;
6981     }
6982   else if (cmode < 12)
6983     {
6984       shift = (cmode >> 1) & 1;
6985       value = (unsigned long) bits << (8 * shift);
6986       size = 16;
6987     }
6988   else if (cmode < 14)
6989     {
6990       shift = (cmode & 1) + 1;
6991       value = (unsigned long) bits << (8 * shift);
6992       value |= (1ul << (8 * shift)) - 1;
6993       size = 32;
6994     }
6995   else if (cmode == 14)
6996     {
6997       if (op)
6998         {
6999           /* Bit replication into bytes.  */
7000           int ix;
7001           unsigned long mask;
7002
7003           value = 0;
7004           hival = 0;
7005           for (ix = 7; ix >= 0; ix--)
7006             {
7007               mask = ((bits >> ix) & 1) ? 0xff : 0;
7008               if (ix <= 3)
7009                 value = (value << 8) | mask;
7010               else
7011                 hival = (hival << 8) | mask;
7012             }
7013           size = 64;
7014         }
7015       else
7016         {
7017           /* Byte replication.  */
7018           value = (unsigned long) bits;
7019           size = 8;
7020         }
7021     }
7022   else if (!op)
7023     {
7024       /* Floating point encoding.  */
7025       int tmp;
7026
7027       value = (unsigned long)  (bits & 0x7f) << 19;
7028       value |= (unsigned long) (bits & 0x80) << 24;
7029       tmp = bits & 0x40 ? 0x3c : 0x40;
7030       value |= (unsigned long) tmp << 24;
7031       size = 32;
7032       isfloat = 1;
7033     }
7034   else
7035     {
7036       func (stream, "<illegal constant %.8x:%x:%x>",
7037             bits, cmode, op);
7038       size = 32;
7039       return;
7040     }
7041
7042   /* printU determines whether the immediate value should be printed as
7043      unsigned.  */
7044   unsigned printU = 0;
7045   switch (insn->mve_op)
7046     {
7047     default:
7048       break;
7049     /* We want this for instructions that don't have a 'signed' type.  */
7050     case MVE_VBIC_IMM:
7051     case MVE_VORR_IMM:
7052     case MVE_VMVN_IMM:
7053     case MVE_VMOV_IMM_TO_VEC:
7054       printU = 1;
7055       break;
7056     }
7057   switch (size)
7058     {
7059     case 8:
7060       func (stream, "#%ld\t; 0x%.2lx", value, value);
7061       break;
7062
7063     case 16:
7064       func (stream,
7065             printU
7066             ? "#%lu\t; 0x%.4lx"
7067             : "#%ld\t; 0x%.4lx", value, value);
7068       break;
7069
7070     case 32:
7071       if (isfloat)
7072         {
7073           unsigned char valbytes[4];
7074           double fvalue;
7075
7076           /* Do this a byte at a time so we don't have to
7077              worry about the host's endianness.  */
7078           valbytes[0] = value & 0xff;
7079           valbytes[1] = (value >> 8) & 0xff;
7080           valbytes[2] = (value >> 16) & 0xff;
7081           valbytes[3] = (value >> 24) & 0xff;
7082
7083           floatformat_to_double
7084             (& floatformat_ieee_single_little, valbytes,
7085              & fvalue);
7086
7087           func (stream, "#%.7g\t; 0x%.8lx", fvalue,
7088                 value);
7089         }
7090       else
7091         func (stream,
7092               printU
7093               ? "#%lu\t; 0x%.8lx"
7094               : "#%ld\t; 0x%.8lx",
7095               (long) (((value & 0x80000000L) != 0)
7096                       && !printU
7097                       ? value | ~0xffffffffL : value),
7098               value);
7099       break;
7100
7101     case 64:
7102       func (stream, "#0x%.8lx%.8lx", hival, value);
7103       break;
7104
7105     default:
7106       abort ();
7107     }
7108
7109 }
7110
7111 static void
7112 print_mve_undefined (struct disassemble_info *info,
7113                      enum mve_undefined undefined_code)
7114 {
7115   void *stream = info->stream;
7116   fprintf_ftype func = info->fprintf_func;
7117
7118   func (stream, "\t\tundefined instruction: ");
7119
7120   switch (undefined_code)
7121     {
7122     case UNDEF_SIZE:
7123       func (stream, "illegal size");
7124       break;
7125
7126     case UNDEF_SIZE_0:
7127       func (stream, "size equals zero");
7128       break;
7129
7130     case UNDEF_SIZE_2:
7131       func (stream, "size equals two");
7132       break;
7133
7134     case UNDEF_SIZE_3:
7135       func (stream, "size equals three");
7136       break;
7137
7138     case UNDEF_SIZE_LE_1:
7139       func (stream, "size <= 1");
7140       break;
7141
7142     case UNDEF_SIZE_NOT_0:
7143       func (stream, "size not equal to 0");
7144       break;
7145
7146     case UNDEF_SIZE_NOT_2:
7147       func (stream, "size not equal to 2");
7148       break;
7149
7150     case UNDEF_SIZE_NOT_3:
7151       func (stream, "size not equal to 3");
7152       break;
7153
7154     case UNDEF_NOT_UNS_SIZE_0:
7155       func (stream, "not unsigned and size = zero");
7156       break;
7157
7158     case UNDEF_NOT_UNS_SIZE_1:
7159       func (stream, "not unsigned and size = one");
7160       break;
7161
7162     case UNDEF_NOT_UNSIGNED:
7163       func (stream, "not unsigned");
7164       break;
7165
7166     case UNDEF_VCVT_IMM6:
7167       func (stream, "invalid imm6");
7168       break;
7169
7170     case UNDEF_VCVT_FSI_IMM6:
7171       func (stream, "fsi = 0 and invalid imm6");
7172       break;
7173
7174     case UNDEF_BAD_OP1_OP2:
7175       func (stream, "bad size with op2 = 2 and op1 = 0 or 1");
7176       break;
7177
7178     case UNDEF_BAD_U_OP1_OP2:
7179       func (stream, "unsigned with op2 = 0 and op1 = 0 or 1");
7180       break;
7181
7182     case UNDEF_OP_0_BAD_CMODE:
7183       func (stream, "op field equal 0 and bad cmode");
7184       break;
7185
7186     case UNDEF_XCHG_UNS:
7187       func (stream, "exchange and unsigned together");
7188       break;
7189
7190     case UNDEF_NONE:
7191       break;
7192     }
7193
7194 }
7195
7196 static void
7197 print_mve_unpredictable (struct disassemble_info *info,
7198                          enum mve_unpredictable unpredict_code)
7199 {
7200   void *stream = info->stream;
7201   fprintf_ftype func = info->fprintf_func;
7202
7203   func (stream, "%s: ", UNPREDICTABLE_INSTRUCTION);
7204
7205   switch (unpredict_code)
7206     {
7207     case UNPRED_IT_BLOCK:
7208       func (stream, "mve instruction in it block");
7209       break;
7210
7211     case UNPRED_FCA_0_FCB_1:
7212       func (stream, "condition bits, fca = 0 and fcb = 1");
7213       break;
7214
7215     case UNPRED_R13:
7216       func (stream, "use of r13 (sp)");
7217       break;
7218
7219     case UNPRED_R15:
7220       func (stream, "use of r15 (pc)");
7221       break;
7222
7223     case UNPRED_Q_GT_4:
7224       func (stream, "start register block > r4");
7225       break;
7226
7227     case UNPRED_Q_GT_6:
7228       func (stream, "start register block > r6");
7229       break;
7230
7231     case UNPRED_R13_AND_WB:
7232       func (stream, "use of r13 and write back");
7233       break;
7234
7235     case UNPRED_Q_REGS_EQUAL:
7236       func (stream,
7237             "same vector register used for destination and other operand");
7238       break;
7239
7240     case UNPRED_OS:
7241       func (stream, "use of offset scaled");
7242       break;
7243
7244     case UNPRED_GP_REGS_EQUAL:
7245       func (stream, "same general-purpose register used for both operands");
7246       break;
7247
7248     case UNPRED_Q_REGS_EQ_AND_SIZE_1:
7249       func (stream, "use of identical q registers and size = 1");
7250       break;
7251
7252     case UNPRED_Q_REGS_EQ_AND_SIZE_2:
7253       func (stream, "use of identical q registers and size = 1");
7254       break;
7255
7256     case UNPRED_NONE:
7257       break;
7258     }
7259 }
7260
7261 /* Print register block operand for mve vld2/vld4/vst2/vld4.  */
7262
7263 static void
7264 print_mve_register_blocks (struct disassemble_info *info,
7265                            unsigned long given,
7266                            enum mve_instructions matched_insn)
7267 {
7268   void *stream = info->stream;
7269   fprintf_ftype func = info->fprintf_func;
7270
7271   unsigned long q_reg_start = arm_decode_field_multiple (given,
7272                                                          13, 15,
7273                                                          22, 22);
7274   switch (matched_insn)
7275     {
7276     case MVE_VLD2:
7277     case MVE_VST2:
7278       if (q_reg_start <= 6)
7279         func (stream, "{q%ld, q%ld}", q_reg_start, q_reg_start + 1);
7280       else
7281         func (stream, "<illegal reg q%ld>", q_reg_start);
7282       break;
7283
7284     case MVE_VLD4:
7285     case MVE_VST4:
7286       if (q_reg_start <= 4)
7287         func (stream, "{q%ld, q%ld, q%ld, q%ld}", q_reg_start,
7288               q_reg_start + 1, q_reg_start + 2,
7289               q_reg_start + 3);
7290       else
7291         func (stream, "<illegal reg q%ld>", q_reg_start);
7292       break;
7293
7294     default:
7295       break;
7296     }
7297 }
7298
7299 static void
7300 print_mve_rounding_mode (struct disassemble_info *info,
7301                          unsigned long given,
7302                          enum mve_instructions matched_insn)
7303 {
7304   void *stream = info->stream;
7305   fprintf_ftype func = info->fprintf_func;
7306
7307   switch (matched_insn)
7308     {
7309     case MVE_VCVT_FROM_FP_TO_INT:
7310       {
7311         switch (arm_decode_field (given, 8, 9))
7312           {
7313           case 0:
7314             func (stream, "a");
7315             break;
7316
7317           case 1:
7318             func (stream, "n");
7319             break;
7320
7321           case 2:
7322             func (stream, "p");
7323             break;
7324
7325           case 3:
7326             func (stream, "m");
7327             break;
7328
7329           default:
7330             break;
7331           }
7332       }
7333       break;
7334
7335     case MVE_VRINT_FP:
7336       {
7337         switch (arm_decode_field (given, 7, 9))
7338           {
7339           case 0:
7340             func (stream, "n");
7341             break;
7342
7343           case 1:
7344             func (stream, "x");
7345             break;
7346
7347           case 2:
7348             func (stream, "a");
7349             break;
7350
7351           case 3:
7352             func (stream, "z");
7353             break;
7354
7355           case 5:
7356             func (stream, "m");
7357             break;
7358
7359           case 7:
7360             func (stream, "p");
7361
7362           case 4:
7363           case 6:
7364           default:
7365             break;
7366           }
7367       }
7368       break;
7369
7370     default:
7371       break;
7372     }
7373 }
7374
7375 static void
7376 print_mve_vcvt_size (struct disassemble_info *info,
7377                      unsigned long given,
7378                      enum mve_instructions matched_insn)
7379 {
7380   unsigned long mode = 0;
7381   void *stream = info->stream;
7382   fprintf_ftype func = info->fprintf_func;
7383
7384   switch (matched_insn)
7385     {
7386     case MVE_VCVT_FP_FIX_VEC:
7387       {
7388         mode = (((given & 0x200) >> 7)
7389                 | ((given & 0x10000000) >> 27)
7390                 | ((given & 0x100) >> 8));
7391
7392         switch (mode)
7393           {
7394           case 0:
7395             func (stream, "f16.s16");
7396             break;
7397
7398           case 1:
7399             func (stream, "s16.f16");
7400             break;
7401
7402           case 2:
7403             func (stream, "f16.u16");
7404             break;
7405
7406           case 3:
7407             func (stream, "u16.f16");
7408             break;
7409
7410           case 4:
7411             func (stream, "f32.s32");
7412             break;
7413
7414           case 5:
7415             func (stream, "s32.f32");
7416             break;
7417
7418           case 6:
7419             func (stream, "f32.u32");
7420             break;
7421
7422           case 7:
7423             func (stream, "u32.f32");
7424             break;
7425
7426           default:
7427             break;
7428           }
7429         break;
7430       }
7431     case MVE_VCVT_BETWEEN_FP_INT:
7432       {
7433         unsigned long size = arm_decode_field (given, 18, 19);
7434         unsigned long op = arm_decode_field (given, 7, 8);
7435
7436         if (size == 1)
7437           {
7438             switch (op)
7439               {
7440               case 0:
7441                 func (stream, "f16.s16");
7442                 break;
7443
7444               case 1:
7445                 func (stream, "f16.u16");
7446                 break;
7447
7448               case 2:
7449                 func (stream, "s16.f16");
7450                 break;
7451
7452               case 3:
7453                 func (stream, "u16.f16");
7454                 break;
7455
7456               default:
7457                 break;
7458               }
7459           }
7460         else if (size == 2)
7461           {
7462             switch (op)
7463               {
7464               case 0:
7465                 func (stream, "f32.s32");
7466                 break;
7467
7468               case 1:
7469                 func (stream, "f32.u32");
7470                 break;
7471
7472               case 2:
7473                 func (stream, "s32.f32");
7474                 break;
7475
7476               case 3:
7477                 func (stream, "u32.f32");
7478                 break;
7479               }
7480           }
7481       }
7482       break;
7483
7484     case MVE_VCVT_FP_HALF_FP:
7485       {
7486         unsigned long op = arm_decode_field (given, 28, 28);
7487         if (op == 0)
7488           func (stream, "f16.f32");
7489         else if (op == 1)
7490           func (stream, "f32.f16");
7491       }
7492       break;
7493
7494     case MVE_VCVT_FROM_FP_TO_INT:
7495       {
7496         unsigned long size = arm_decode_field_multiple (given, 7, 7, 18, 19);
7497
7498         switch (size)
7499           {
7500           case 2:
7501             func (stream, "s16.f16");
7502             break;
7503
7504           case 3:
7505             func (stream, "u16.f16");
7506             break;
7507
7508           case 4:
7509             func (stream, "s32.f32");
7510             break;
7511
7512           case 5:
7513             func (stream, "u32.f32");
7514             break;
7515
7516           default:
7517             break;
7518           }
7519       }
7520       break;
7521
7522     default:
7523       break;
7524     }
7525 }
7526
7527 static void
7528 print_mve_rotate (struct disassemble_info *info, unsigned long rot,
7529                   unsigned long rot_width)
7530 {
7531   void *stream = info->stream;
7532   fprintf_ftype func = info->fprintf_func;
7533
7534   if (rot_width == 1)
7535     {
7536       switch (rot)
7537         {
7538         case 0:
7539           func (stream, "90");
7540           break;
7541         case 1:
7542           func (stream, "270");
7543           break;
7544         default:
7545           break;
7546         }
7547     }
7548   else if (rot_width == 2)
7549     {
7550       switch (rot)
7551         {
7552         case 0:
7553           func (stream, "0");
7554           break;
7555         case 1:
7556           func (stream, "90");
7557           break;
7558         case 2:
7559           func (stream, "180");
7560           break;
7561         case 3:
7562           func (stream, "270");
7563           break;
7564         default:
7565           break;
7566         }
7567     }
7568 }
7569
7570 static void
7571 print_instruction_predicate (struct disassemble_info *info)
7572 {
7573   void *stream = info->stream;
7574   fprintf_ftype func = info->fprintf_func;
7575
7576   if (vpt_block_state.next_pred_state == PRED_THEN)
7577     func (stream, "t");
7578   else if (vpt_block_state.next_pred_state == PRED_ELSE)
7579     func (stream, "e");
7580 }
7581
7582 static void
7583 print_mve_size (struct disassemble_info *info,
7584                 unsigned long size,
7585                 enum mve_instructions matched_insn)
7586 {
7587   void *stream = info->stream;
7588   fprintf_ftype func = info->fprintf_func;
7589
7590   switch (matched_insn)
7591     {
7592     case MVE_VABAV:
7593     case MVE_VABD_VEC:
7594     case MVE_VABS_FP:
7595     case MVE_VABS_VEC:
7596     case MVE_VADD_VEC_T1:
7597     case MVE_VADD_VEC_T2:
7598     case MVE_VADDV:
7599     case MVE_VBRSR:
7600     case MVE_VCADD_VEC:
7601     case MVE_VCLS:
7602     case MVE_VCLZ:
7603     case MVE_VCMP_VEC_T1:
7604     case MVE_VCMP_VEC_T2:
7605     case MVE_VCMP_VEC_T3:
7606     case MVE_VCMP_VEC_T4:
7607     case MVE_VCMP_VEC_T5:
7608     case MVE_VCMP_VEC_T6:
7609     case MVE_VCTP:
7610     case MVE_VDDUP:
7611     case MVE_VDWDUP:
7612     case MVE_VHADD_T1:
7613     case MVE_VHADD_T2:
7614     case MVE_VHCADD:
7615     case MVE_VHSUB_T1:
7616     case MVE_VHSUB_T2:
7617     case MVE_VIDUP:
7618     case MVE_VIWDUP:
7619     case MVE_VLD2:
7620     case MVE_VLD4:
7621     case MVE_VLDRB_GATHER_T1:
7622     case MVE_VLDRH_GATHER_T2:
7623     case MVE_VLDRW_GATHER_T3:
7624     case MVE_VLDRD_GATHER_T4:
7625     case MVE_VLDRB_T1:
7626     case MVE_VLDRH_T2:
7627     case MVE_VMAX:
7628     case MVE_VMAXA:
7629     case MVE_VMAXV:
7630     case MVE_VMAXAV:
7631     case MVE_VMIN:
7632     case MVE_VMINA:
7633     case MVE_VMINV:
7634     case MVE_VMINAV:
7635     case MVE_VMLA:
7636     case MVE_VMLAS:
7637     case MVE_VMUL_VEC_T1:
7638     case MVE_VMUL_VEC_T2:
7639     case MVE_VMULH:
7640     case MVE_VRMULH:
7641     case MVE_VMULL_INT:
7642     case MVE_VNEG_FP:
7643     case MVE_VNEG_VEC:
7644     case MVE_VPT_VEC_T1:
7645     case MVE_VPT_VEC_T2:
7646     case MVE_VPT_VEC_T3:
7647     case MVE_VPT_VEC_T4:
7648     case MVE_VPT_VEC_T5:
7649     case MVE_VPT_VEC_T6:
7650     case MVE_VQABS:
7651     case MVE_VQADD_T1:
7652     case MVE_VQADD_T2:
7653     case MVE_VQDMLADH:
7654     case MVE_VQRDMLADH:
7655     case MVE_VQDMLAH:
7656     case MVE_VQRDMLAH:
7657     case MVE_VQDMLASH:
7658     case MVE_VQRDMLASH:
7659     case MVE_VQDMLSDH:
7660     case MVE_VQRDMLSDH:
7661     case MVE_VQDMULH_T1:
7662     case MVE_VQRDMULH_T2:
7663     case MVE_VQDMULH_T3:
7664     case MVE_VQRDMULH_T4:
7665     case MVE_VQNEG:
7666     case MVE_VQRSHL_T1:
7667     case MVE_VQRSHL_T2:
7668     case MVE_VQSHL_T1:
7669     case MVE_VQSHL_T4:
7670     case MVE_VQSUB_T1:
7671     case MVE_VQSUB_T2:
7672     case MVE_VREV32:
7673     case MVE_VREV64:
7674     case MVE_VRHADD:
7675     case MVE_VRINT_FP:
7676     case MVE_VRSHL_T1:
7677     case MVE_VRSHL_T2:
7678     case MVE_VSHL_T2:
7679     case MVE_VSHL_T3:
7680     case MVE_VSHLL_T2:
7681     case MVE_VST2:
7682     case MVE_VST4:
7683     case MVE_VSTRB_SCATTER_T1:
7684     case MVE_VSTRH_SCATTER_T2:
7685     case MVE_VSTRW_SCATTER_T3:
7686     case MVE_VSTRB_T1:
7687     case MVE_VSTRH_T2:
7688     case MVE_VSUB_VEC_T1:
7689     case MVE_VSUB_VEC_T2:
7690       if (size <= 3)
7691         func (stream, "%s", mve_vec_sizename[size]);
7692       else
7693         func (stream, "<undef size>");
7694       break;
7695
7696     case MVE_VABD_FP:
7697     case MVE_VADD_FP_T1:
7698     case MVE_VADD_FP_T2:
7699     case MVE_VSUB_FP_T1:
7700     case MVE_VSUB_FP_T2:
7701     case MVE_VCMP_FP_T1:
7702     case MVE_VCMP_FP_T2:
7703     case MVE_VFMA_FP_SCALAR:
7704     case MVE_VFMA_FP:
7705     case MVE_VFMS_FP:
7706     case MVE_VFMAS_FP_SCALAR:
7707     case MVE_VMAXNM_FP:
7708     case MVE_VMAXNMA_FP:
7709     case MVE_VMAXNMV_FP:
7710     case MVE_VMAXNMAV_FP:
7711     case MVE_VMINNM_FP:
7712     case MVE_VMINNMA_FP:
7713     case MVE_VMINNMV_FP:
7714     case MVE_VMINNMAV_FP:
7715     case MVE_VMUL_FP_T1:
7716     case MVE_VMUL_FP_T2:
7717     case MVE_VPT_FP_T1:
7718     case MVE_VPT_FP_T2:
7719       if (size == 0)
7720         func (stream, "32");
7721       else if (size == 1)
7722         func (stream, "16");
7723       break;
7724
7725     case MVE_VCADD_FP:
7726     case MVE_VCMLA_FP:
7727     case MVE_VCMUL_FP:
7728     case MVE_VMLADAV_T1:
7729     case MVE_VMLALDAV:
7730     case MVE_VMLSDAV_T1:
7731     case MVE_VMLSLDAV:
7732     case MVE_VMOVN:
7733     case MVE_VQDMULL_T1:
7734     case MVE_VQDMULL_T2:
7735     case MVE_VQMOVN:
7736     case MVE_VQMOVUN:
7737       if (size == 0)
7738         func (stream, "16");
7739       else if (size == 1)
7740         func (stream, "32");
7741       break;
7742
7743     case MVE_VMOVL:
7744       if (size == 1)
7745         func (stream, "8");
7746       else if (size == 2)
7747         func (stream, "16");
7748       break;
7749
7750     case MVE_VDUP:
7751       switch (size)
7752         {
7753         case 0:
7754           func (stream, "32");
7755           break;
7756         case 1:
7757           func (stream, "16");
7758           break;
7759         case 2:
7760           func (stream, "8");
7761           break;
7762         default:
7763           break;
7764         }
7765       break;
7766
7767     case MVE_VMOV_GP_TO_VEC_LANE:
7768     case MVE_VMOV_VEC_LANE_TO_GP:
7769       switch (size)
7770         {
7771         case 0: case 4:
7772           func (stream, "32");
7773           break;
7774
7775         case 1: case 3:
7776         case 5: case 7:
7777           func (stream, "16");
7778           break;
7779
7780         case 8: case 9: case 10: case 11:
7781         case 12: case 13: case 14: case 15:
7782           func (stream, "8");
7783           break;
7784
7785         default:
7786           break;
7787         }
7788       break;
7789
7790     case MVE_VMOV_IMM_TO_VEC:
7791       switch (size)
7792         {
7793         case 0: case 4: case 8:
7794         case 12: case 24: case 26:
7795           func (stream, "i32");
7796           break;
7797         case 16: case 20:
7798           func (stream, "i16");
7799           break;
7800         case 28:
7801           func (stream, "i8");
7802           break;
7803         case 29:
7804           func (stream, "i64");
7805           break;
7806         case 30:
7807           func (stream, "f32");
7808           break;
7809         default:
7810           break;
7811         }
7812       break;
7813
7814     case MVE_VMULL_POLY:
7815       if (size == 0)
7816         func (stream, "p8");
7817       else if (size == 1)
7818         func (stream, "p16");
7819       break;
7820
7821     case MVE_VMVN_IMM:
7822       switch (size)
7823         {
7824         case 0: case 2: case 4:
7825         case 6: case 12: case 13:
7826           func (stream, "32");
7827           break;
7828
7829         case 8: case 10:
7830           func (stream, "16");
7831           break;
7832
7833         default:
7834           break;
7835         }
7836       break;
7837
7838     case MVE_VBIC_IMM:
7839     case MVE_VORR_IMM:
7840       switch (size)
7841         {
7842         case 1: case 3:
7843         case 5: case 7:
7844           func (stream, "32");
7845           break;
7846
7847         case 9: case 11:
7848           func (stream, "16");
7849           break;
7850
7851         default:
7852           break;
7853         }
7854       break;
7855
7856     case MVE_VQSHRN:
7857     case MVE_VQSHRUN:
7858     case MVE_VQRSHRN:
7859     case MVE_VQRSHRUN:
7860     case MVE_VRSHRN:
7861     case MVE_VSHRN:
7862       {
7863         switch (size)
7864         {
7865         case 1:
7866           func (stream, "16");
7867           break;
7868
7869         case 2: case 3:
7870           func (stream, "32");
7871           break;
7872
7873         default:
7874           break;
7875         }
7876       }
7877       break;
7878
7879     case MVE_VQSHL_T2:
7880     case MVE_VQSHLU_T3:
7881     case MVE_VRSHR:
7882     case MVE_VSHL_T1:
7883     case MVE_VSHLL_T1:
7884     case MVE_VSHR:
7885     case MVE_VSLI:
7886     case MVE_VSRI:
7887       {
7888         switch (size)
7889         {
7890         case 1:
7891           func (stream, "8");
7892           break;
7893
7894         case 2: case 3:
7895           func (stream, "16");
7896           break;
7897
7898         case 4: case 5: case 6: case 7:
7899           func (stream, "32");
7900           break;
7901
7902         default:
7903           break;
7904         }
7905       }
7906       break;
7907
7908     default:
7909       break;
7910     }
7911 }
7912
7913 static void
7914 print_mve_shift_n (struct disassemble_info *info, long given,
7915                    enum mve_instructions matched_insn)
7916 {
7917   void *stream = info->stream;
7918   fprintf_ftype func = info->fprintf_func;
7919
7920   int startAt0
7921     = matched_insn == MVE_VQSHL_T2
7922       || matched_insn == MVE_VQSHLU_T3
7923       || matched_insn == MVE_VSHL_T1
7924       || matched_insn == MVE_VSHLL_T1
7925       || matched_insn == MVE_VSLI;
7926
7927   unsigned imm6 = (given & 0x3f0000) >> 16;
7928
7929   if (matched_insn == MVE_VSHLL_T1)
7930     imm6 &= 0x1f;
7931
7932   unsigned shiftAmount = 0;
7933   if ((imm6 & 0x20) != 0)
7934     shiftAmount = startAt0 ? imm6 - 32 : 64 - imm6;
7935   else if ((imm6 & 0x10) != 0)
7936     shiftAmount = startAt0 ? imm6 - 16 : 32 - imm6;
7937   else if ((imm6 & 0x08) != 0)
7938     shiftAmount = startAt0 ? imm6 - 8 : 16 - imm6;
7939   else
7940     print_mve_undefined (info, UNDEF_SIZE_0);
7941
7942   func (stream, "%u", shiftAmount);
7943 }
7944
7945 static void
7946 print_vec_condition (struct disassemble_info *info, long given,
7947                      enum mve_instructions matched_insn)
7948 {
7949   void *stream = info->stream;
7950   fprintf_ftype func = info->fprintf_func;
7951   long vec_cond = 0;
7952
7953   switch (matched_insn)
7954     {
7955     case MVE_VPT_FP_T1:
7956     case MVE_VCMP_FP_T1:
7957       vec_cond = (((given & 0x1000) >> 10)
7958                   | ((given & 1) << 1)
7959                   | ((given & 0x0080) >> 7));
7960       func (stream, "%s",vec_condnames[vec_cond]);
7961       break;
7962
7963     case MVE_VPT_FP_T2:
7964     case MVE_VCMP_FP_T2:
7965       vec_cond = (((given & 0x1000) >> 10)
7966                   | ((given & 0x0020) >> 4)
7967                   | ((given & 0x0080) >> 7));
7968       func (stream, "%s",vec_condnames[vec_cond]);
7969       break;
7970
7971     case MVE_VPT_VEC_T1:
7972     case MVE_VCMP_VEC_T1:
7973       vec_cond = (given & 0x0080) >> 7;
7974       func (stream, "%s",vec_condnames[vec_cond]);
7975       break;
7976
7977     case MVE_VPT_VEC_T2:
7978     case MVE_VCMP_VEC_T2:
7979       vec_cond = 2 | ((given & 0x0080) >> 7);
7980       func (stream, "%s",vec_condnames[vec_cond]);
7981       break;
7982
7983     case MVE_VPT_VEC_T3:
7984     case MVE_VCMP_VEC_T3:
7985       vec_cond = 4 | ((given & 1) << 1) | ((given & 0x0080) >> 7);
7986       func (stream, "%s",vec_condnames[vec_cond]);
7987       break;
7988
7989     case MVE_VPT_VEC_T4:
7990     case MVE_VCMP_VEC_T4:
7991       vec_cond = (given & 0x0080) >> 7;
7992       func (stream, "%s",vec_condnames[vec_cond]);
7993       break;
7994
7995     case MVE_VPT_VEC_T5:
7996     case MVE_VCMP_VEC_T5:
7997       vec_cond = 2 | ((given & 0x0080) >> 7);
7998       func (stream, "%s",vec_condnames[vec_cond]);
7999       break;
8000
8001     case MVE_VPT_VEC_T6:
8002     case MVE_VCMP_VEC_T6:
8003       vec_cond = 4 | ((given & 0x0020) >> 4) | ((given & 0x0080) >> 7);
8004       func (stream, "%s",vec_condnames[vec_cond]);
8005       break;
8006
8007     case MVE_NONE:
8008     case MVE_VPST:
8009     default:
8010       break;
8011     }
8012 }
8013
8014 #define W_BIT 21
8015 #define I_BIT 22
8016 #define U_BIT 23
8017 #define P_BIT 24
8018
8019 #define WRITEBACK_BIT_SET (given & (1 << W_BIT))
8020 #define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
8021 #define NEGATIVE_BIT_SET  ((given & (1 << U_BIT)) == 0)
8022 #define PRE_BIT_SET       (given & (1 << P_BIT))
8023
8024
8025 /* Print one coprocessor instruction on INFO->STREAM.
8026    Return TRUE if the instuction matched, FALSE if this is not a
8027    recognised coprocessor instruction.  */
8028
8029 static bool
8030 print_insn_coprocessor_1 (const struct sopcode32 *opcodes,
8031                           bfd_vma pc,
8032                           struct disassemble_info *info,
8033                           long given,
8034                           bool thumb)
8035 {
8036   const struct sopcode32 *insn;
8037   void *stream = info->stream;
8038   fprintf_ftype func = info->fprintf_func;
8039   unsigned long mask;
8040   unsigned long value = 0;
8041   int cond;
8042   int cp_num;
8043   struct arm_private_data *private_data = info->private_data;
8044   arm_feature_set allowed_arches = ARM_ARCH_NONE;
8045   arm_feature_set arm_ext_v8_1m_main =
8046     ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
8047
8048   allowed_arches = private_data->features;
8049
8050   for (insn = opcodes; insn->assembler; insn++)
8051     {
8052       unsigned long u_reg = 16;
8053       bool is_unpredictable = false;
8054       signed long value_in_comment = 0;
8055       const char *c;
8056
8057       if (ARM_FEATURE_ZERO (insn->arch))
8058         switch (insn->value)
8059           {
8060           case SENTINEL_IWMMXT_START:
8061             if (info->mach != bfd_mach_arm_XScale
8062                 && info->mach != bfd_mach_arm_iWMMXt
8063                 && info->mach != bfd_mach_arm_iWMMXt2)
8064               do
8065                 insn++;
8066               while ((! ARM_FEATURE_ZERO (insn->arch))
8067                      && insn->value != SENTINEL_IWMMXT_END);
8068             continue;
8069
8070           case SENTINEL_IWMMXT_END:
8071             continue;
8072
8073           case SENTINEL_GENERIC_START:
8074             allowed_arches = private_data->features;
8075             continue;
8076
8077           default:
8078             abort ();
8079           }
8080
8081       mask = insn->mask;
8082       value = insn->value;
8083       cp_num = (given >> 8) & 0xf;
8084
8085       if (thumb)
8086         {
8087           /* The high 4 bits are 0xe for Arm conditional instructions, and
8088              0xe for arm unconditional instructions.  The rest of the
8089              encoding is the same.  */
8090           mask |= 0xf0000000;
8091           value |= 0xe0000000;
8092           if (ifthen_state)
8093             cond = IFTHEN_COND;
8094           else
8095             cond = COND_UNCOND;
8096         }
8097       else
8098         {
8099           /* Only match unconditional instuctions against unconditional
8100              patterns.  */
8101           if ((given & 0xf0000000) == 0xf0000000)
8102             {
8103               mask |= 0xf0000000;
8104               cond = COND_UNCOND;
8105             }
8106           else
8107             {
8108               cond = (given >> 28) & 0xf;
8109               if (cond == 0xe)
8110                 cond = COND_UNCOND;
8111             }
8112         }
8113
8114       if ((insn->isa == T32 && !thumb)
8115           || (insn->isa == ARM && thumb))
8116         continue;
8117
8118       if ((given & mask) != value)
8119         continue;
8120
8121       if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches))
8122         continue;
8123
8124       if (insn->value == 0xfe000010     /* mcr2  */
8125           || insn->value == 0xfe100010  /* mrc2  */
8126           || insn->value == 0xfc100000  /* ldc2  */
8127           || insn->value == 0xfc000000) /* stc2  */
8128         {
8129           if (cp_num == 9 || cp_num == 10 || cp_num == 11)
8130             is_unpredictable = true;
8131
8132           /* Armv8.1-M Mainline FP & MVE instructions.  */
8133           if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
8134               && !ARM_CPU_IS_ANY (allowed_arches)
8135               && (cp_num == 8 || cp_num == 14 || cp_num == 15))
8136             continue;
8137
8138         }
8139       else if (insn->value == 0x0e000000     /* cdp  */
8140                || insn->value == 0xfe000000  /* cdp2  */
8141                || insn->value == 0x0e000010  /* mcr  */
8142                || insn->value == 0x0e100010  /* mrc  */
8143                || insn->value == 0x0c100000  /* ldc  */
8144                || insn->value == 0x0c000000) /* stc  */
8145         {
8146           /* Floating-point instructions.  */
8147           if (cp_num == 9 || cp_num == 10 || cp_num == 11)
8148             continue;
8149
8150           /* Armv8.1-M Mainline FP & MVE instructions.  */
8151           if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
8152               && !ARM_CPU_IS_ANY (allowed_arches)
8153               && (cp_num == 8 || cp_num == 14 || cp_num == 15))
8154             continue;
8155         }
8156       else if ((insn->value == 0xec100f80      /* vldr (system register) */
8157                 || insn->value == 0xec000f80)  /* vstr (system register) */
8158                && arm_decode_field (given, 24, 24) == 0
8159                && arm_decode_field (given, 21, 21) == 0)
8160         /* If the P and W bits are both 0 then these encodings match the MVE
8161            VLDR and VSTR instructions, these are in a different table, so we
8162            don't let it match here.  */
8163         continue;
8164
8165       for (c = insn->assembler; *c; c++)
8166         {
8167           if (*c == '%')
8168             {
8169               const char mod = *++c;
8170               switch (mod)
8171                 {
8172                 case '%':
8173                   func (stream, "%%");
8174                   break;
8175
8176                 case 'A':
8177                 case 'K':
8178                   {
8179                     int rn = (given >> 16) & 0xf;
8180                     bfd_vma offset = given & 0xff;
8181
8182                     if (mod == 'K')
8183                       offset = given & 0x7f;
8184
8185                     func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
8186
8187                     if (PRE_BIT_SET || WRITEBACK_BIT_SET)
8188                       {
8189                         /* Not unindexed.  The offset is scaled.  */
8190                         if (cp_num == 9)
8191                           /* vldr.16/vstr.16 will shift the address
8192                              left by 1 bit only.  */
8193                           offset = offset * 2;
8194                         else
8195                           offset = offset * 4;
8196
8197                         if (NEGATIVE_BIT_SET)
8198                           offset = - offset;
8199                         if (rn != 15)
8200                           value_in_comment = offset;
8201                       }
8202
8203                     if (PRE_BIT_SET)
8204                       {
8205                         if (offset)
8206                           func (stream, ", #%d]%s",
8207                                 (int) offset,
8208                                 WRITEBACK_BIT_SET ? "!" : "");
8209                         else if (NEGATIVE_BIT_SET)
8210                           func (stream, ", #-0]");
8211                         else
8212                           func (stream, "]");
8213                       }
8214                     else
8215                       {
8216                         func (stream, "]");
8217
8218                         if (WRITEBACK_BIT_SET)
8219                           {
8220                             if (offset)
8221                               func (stream, ", #%d", (int) offset);
8222                             else if (NEGATIVE_BIT_SET)
8223                               func (stream, ", #-0");
8224                           }
8225                         else
8226                           {
8227                             func (stream, ", {%s%d}",
8228                                   (NEGATIVE_BIT_SET && !offset) ? "-" : "",
8229                                   (int) offset);
8230                             value_in_comment = offset;
8231                           }
8232                       }
8233                     if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
8234                       {
8235                         func (stream, "\t; ");
8236                         /* For unaligned PCs, apply off-by-alignment
8237                            correction.  */
8238                         info->print_address_func (offset + pc
8239                                                   + info->bytes_per_chunk * 2
8240                                                   - (pc & 3),
8241                                                   info);
8242                       }
8243                   }
8244                   break;
8245
8246                 case 'B':
8247                   {
8248                     int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
8249                     int offset = (given >> 1) & 0x3f;
8250
8251                     if (offset == 1)
8252                       func (stream, "{d%d}", regno);
8253                     else if (regno + offset > 32)
8254                       func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
8255                     else
8256                       func (stream, "{d%d-d%d}", regno, regno + offset - 1);
8257                   }
8258                   break;
8259
8260                 case 'C':
8261                   {
8262                     bool single = ((given >> 8) & 1) == 0;
8263                     char reg_prefix = single ? 's' : 'd';
8264                     int Dreg = (given >> 22) & 0x1;
8265                     int Vdreg = (given >> 12) & 0xf;
8266                     int reg = single ? ((Vdreg << 1) | Dreg)
8267                                      : ((Dreg << 4) | Vdreg);
8268                     int num = (given >> (single ? 0 : 1)) & 0x7f;
8269                     int maxreg = single ? 31 : 15;
8270                     int topreg = reg + num - 1;
8271
8272                     if (!num)
8273                       func (stream, "{VPR}");
8274                     else if (num == 1)
8275                       func (stream, "{%c%d, VPR}", reg_prefix, reg);
8276                     else if (topreg > maxreg)
8277                       func (stream, "{%c%d-<overflow reg d%d, VPR}",
8278                             reg_prefix, reg, single ? topreg >> 1 : topreg);
8279                     else
8280                       func (stream, "{%c%d-%c%d, VPR}", reg_prefix, reg,
8281                             reg_prefix, topreg);
8282                   }
8283                   break;
8284
8285                 case 'u':
8286                   if (cond != COND_UNCOND)
8287                     is_unpredictable = true;
8288
8289                   /* Fall through.  */
8290                 case 'c':
8291                   if (cond != COND_UNCOND && cp_num == 9)
8292                     is_unpredictable = true;
8293
8294                   /* Fall through.  */
8295                 case 'b':
8296                   func (stream, "%s", arm_conditional[cond]);
8297                   break;
8298
8299                 case 'I':
8300                   /* Print a Cirrus/DSP shift immediate.  */
8301                   /* Immediates are 7bit signed ints with bits 0..3 in
8302                      bits 0..3 of opcode and bits 4..6 in bits 5..7
8303                      of opcode.  */
8304                   {
8305                     int imm;
8306
8307                     imm = (given & 0xf) | ((given & 0xe0) >> 1);
8308
8309                     /* Is ``imm'' a negative number?  */
8310                     if (imm & 0x40)
8311                       imm -= 0x80;
8312
8313                     func (stream, "%d", imm);
8314                   }
8315
8316                   break;
8317
8318                 case 'J':
8319                   {
8320                     unsigned long regno
8321                       = arm_decode_field_multiple (given, 13, 15, 22, 22);
8322
8323                     switch (regno)
8324                       {
8325                       case 0x1:
8326                         func (stream, "FPSCR");
8327                         break;
8328                       case 0x2:
8329                         func (stream, "FPSCR_nzcvqc");
8330                         break;
8331                       case 0xc:
8332                         func (stream, "VPR");
8333                         break;
8334                       case 0xd:
8335                         func (stream, "P0");
8336                         break;
8337                       case 0xe:
8338                         func (stream, "FPCXTNS");
8339                         break;
8340                       case 0xf:
8341                         func (stream, "FPCXTS");
8342                         break;
8343                       default:
8344                         func (stream, "<invalid reg %lu>", regno);
8345                         break;
8346                       }
8347                   }
8348                   break;
8349
8350                 case 'F':
8351                   switch (given & 0x00408000)
8352                     {
8353                     case 0:
8354                       func (stream, "4");
8355                       break;
8356                     case 0x8000:
8357                       func (stream, "1");
8358                       break;
8359                     case 0x00400000:
8360                       func (stream, "2");
8361                       break;
8362                     default:
8363                       func (stream, "3");
8364                     }
8365                   break;
8366
8367                 case 'P':
8368                   switch (given & 0x00080080)
8369                     {
8370                     case 0:
8371                       func (stream, "s");
8372                       break;
8373                     case 0x80:
8374                       func (stream, "d");
8375                       break;
8376                     case 0x00080000:
8377                       func (stream, "e");
8378                       break;
8379                     default:
8380                       func (stream, _("<illegal precision>"));
8381                       break;
8382                     }
8383                   break;
8384
8385                 case 'Q':
8386                   switch (given & 0x00408000)
8387                     {
8388                     case 0:
8389                       func (stream, "s");
8390                       break;
8391                     case 0x8000:
8392                       func (stream, "d");
8393                       break;
8394                     case 0x00400000:
8395                       func (stream, "e");
8396                       break;
8397                     default:
8398                       func (stream, "p");
8399                       break;
8400                     }
8401                   break;
8402
8403                 case 'R':
8404                   switch (given & 0x60)
8405                     {
8406                     case 0:
8407                       break;
8408                     case 0x20:
8409                       func (stream, "p");
8410                       break;
8411                     case 0x40:
8412                       func (stream, "m");
8413                       break;
8414                     default:
8415                       func (stream, "z");
8416                       break;
8417                     }
8418                   break;
8419
8420                 case '0': case '1': case '2': case '3': case '4':
8421                 case '5': case '6': case '7': case '8': case '9':
8422                   {
8423                     int width;
8424
8425                     c = arm_decode_bitfield (c, given, &value, &width);
8426
8427                     switch (*c)
8428                       {
8429                       case 'R':
8430                         if (value == 15)
8431                           is_unpredictable = true;
8432                         /* Fall through.  */
8433                       case 'r':
8434                         if (c[1] == 'u')
8435                           {
8436                             /* Eat the 'u' character.  */
8437                             ++ c;
8438
8439                             if (u_reg == value)
8440                               is_unpredictable = true;
8441                             u_reg = value;
8442                           }
8443                         func (stream, "%s", arm_regnames[value]);
8444                         break;
8445                       case 'V':
8446                         if (given & (1 << 6))
8447                           goto Q;
8448                         /* FALLTHROUGH */
8449                       case 'D':
8450                         func (stream, "d%ld", value);
8451                         break;
8452                       case 'Q':
8453                       Q:
8454                         if (value & 1)
8455                           func (stream, "<illegal reg q%ld.5>", value >> 1);
8456                         else
8457                           func (stream, "q%ld", value >> 1);
8458                         break;
8459                       case 'd':
8460                         func (stream, "%ld", value);
8461                         value_in_comment = value;
8462                         break;
8463                       case 'E':
8464                         {
8465                           /* Converts immediate 8 bit back to float value.  */
8466                           unsigned floatVal = (value & 0x80) << 24
8467                             | (value & 0x3F) << 19
8468                             | ((value & 0x40) ? (0xF8 << 22) : (1 << 30));
8469
8470                           /* Quarter float have a maximum value of 31.0.
8471                              Get floating point value multiplied by 1e7.
8472                              The maximum value stays in limit of a 32-bit int.  */
8473                           unsigned decVal =
8474                             (78125 << (((floatVal >> 23) & 0xFF) - 124)) *
8475                             (16 + (value & 0xF));
8476
8477                           if (!(decVal % 1000000))
8478                             func (stream, "%ld\t; 0x%08x %c%u.%01u", value,
8479                                   floatVal, value & 0x80 ? '-' : ' ',
8480                                   decVal / 10000000,
8481                                   decVal % 10000000 / 1000000);
8482                           else if (!(decVal % 10000))
8483                             func (stream, "%ld\t; 0x%08x %c%u.%03u", value,
8484                                   floatVal, value & 0x80 ? '-' : ' ',
8485                                   decVal / 10000000,
8486                                   decVal % 10000000 / 10000);
8487                           else
8488                             func (stream, "%ld\t; 0x%08x %c%u.%07u", value,
8489                                   floatVal, value & 0x80 ? '-' : ' ',
8490                                   decVal / 10000000, decVal % 10000000);
8491                           break;
8492                         }
8493                       case 'k':
8494                         {
8495                           int from = (given & (1 << 7)) ? 32 : 16;
8496                           func (stream, "%ld", from - value);
8497                         }
8498                         break;
8499
8500                       case 'f':
8501                         if (value > 7)
8502                           func (stream, "#%s", arm_fp_const[value & 7]);
8503                         else
8504                           func (stream, "f%ld", value);
8505                         break;
8506
8507                       case 'w':
8508                         if (width == 2)
8509                           func (stream, "%s", iwmmxt_wwnames[value]);
8510                         else
8511                           func (stream, "%s", iwmmxt_wwssnames[value]);
8512                         break;
8513
8514                       case 'g':
8515                         func (stream, "%s", iwmmxt_regnames[value]);
8516                         break;
8517                       case 'G':
8518                         func (stream, "%s", iwmmxt_cregnames[value]);
8519                         break;
8520
8521                       case 'x':
8522                         func (stream, "0x%lx", (value & 0xffffffffUL));
8523                         break;
8524
8525                       case 'c':
8526                         switch (value)
8527                           {
8528                           case 0:
8529                             func (stream, "eq");
8530                             break;
8531
8532                           case 1:
8533                             func (stream, "vs");
8534                             break;
8535
8536                           case 2:
8537                             func (stream, "ge");
8538                             break;
8539
8540                           case 3:
8541                             func (stream, "gt");
8542                             break;
8543
8544                           default:
8545                             func (stream, "??");
8546                             break;
8547                           }
8548                         break;
8549
8550                       case '`':
8551                         c++;
8552                         if (value == 0)
8553                           func (stream, "%c", *c);
8554                         break;
8555                       case '\'':
8556                         c++;
8557                         if (value == ((1ul << width) - 1))
8558                           func (stream, "%c", *c);
8559                         break;
8560                       case '?':
8561                         func (stream, "%c", c[(1 << width) - (int) value]);
8562                         c += 1 << width;
8563                         break;
8564                       default:
8565                         abort ();
8566                       }
8567                   }
8568                   break;
8569
8570                 case 'y':
8571                 case 'z':
8572                   {
8573                     int single = *c++ == 'y';
8574                     int regno;
8575
8576                     switch (*c)
8577                       {
8578                       case '4': /* Sm pair */
8579                       case '0': /* Sm, Dm */
8580                         regno = given & 0x0000000f;
8581                         if (single)
8582                           {
8583                             regno <<= 1;
8584                             regno += (given >> 5) & 1;
8585                           }
8586                         else
8587                           regno += ((given >> 5) & 1) << 4;
8588                         break;
8589
8590                       case '1': /* Sd, Dd */
8591                         regno = (given >> 12) & 0x0000000f;
8592                         if (single)
8593                           {
8594                             regno <<= 1;
8595                             regno += (given >> 22) & 1;
8596                           }
8597                         else
8598                           regno += ((given >> 22) & 1) << 4;
8599                         break;
8600
8601                       case '2': /* Sn, Dn */
8602                         regno = (given >> 16) & 0x0000000f;
8603                         if (single)
8604                           {
8605                             regno <<= 1;
8606                             regno += (given >> 7) & 1;
8607                           }
8608                         else
8609                           regno += ((given >> 7) & 1) << 4;
8610                         break;
8611
8612                       case '3': /* List */
8613                         func (stream, "{");
8614                         regno = (given >> 12) & 0x0000000f;
8615                         if (single)
8616                           {
8617                             regno <<= 1;
8618                             regno += (given >> 22) & 1;
8619                           }
8620                         else
8621                           regno += ((given >> 22) & 1) << 4;
8622                         break;
8623
8624                       default:
8625                         abort ();
8626                       }
8627
8628                     func (stream, "%c%d", single ? 's' : 'd', regno);
8629
8630                     if (*c == '3')
8631                       {
8632                         int count = given & 0xff;
8633
8634                         if (single == 0)
8635                           count >>= 1;
8636
8637                         if (--count)
8638                           {
8639                             func (stream, "-%c%d",
8640                                   single ? 's' : 'd',
8641                                   regno + count);
8642                           }
8643
8644                         func (stream, "}");
8645                       }
8646                     else if (*c == '4')
8647                       func (stream, ", %c%d", single ? 's' : 'd',
8648                             regno + 1);
8649                   }
8650                   break;
8651
8652                 case 'L':
8653                   switch (given & 0x00400100)
8654                     {
8655                     case 0x00000000: func (stream, "b"); break;
8656                     case 0x00400000: func (stream, "h"); break;
8657                     case 0x00000100: func (stream, "w"); break;
8658                     case 0x00400100: func (stream, "d"); break;
8659                     default:
8660                       break;
8661                     }
8662                   break;
8663
8664                 case 'Z':
8665                   {
8666                     /* given (20, 23) | given (0, 3) */
8667                     value = ((given >> 16) & 0xf0) | (given & 0xf);
8668                     func (stream, "%d", (int) value);
8669                   }
8670                   break;
8671
8672                 case 'l':
8673                   /* This is like the 'A' operator, except that if
8674                      the width field "M" is zero, then the offset is
8675                      *not* multiplied by four.  */
8676                   {
8677                     int offset = given & 0xff;
8678                     int multiplier = (given & 0x00000100) ? 4 : 1;
8679
8680                     func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
8681
8682                     if (multiplier > 1)
8683                       {
8684                         value_in_comment = offset * multiplier;
8685                         if (NEGATIVE_BIT_SET)
8686                           value_in_comment = - value_in_comment;
8687                       }
8688
8689                     if (offset)
8690                       {
8691                         if (PRE_BIT_SET)
8692                           func (stream, ", #%s%d]%s",
8693                                 NEGATIVE_BIT_SET ? "-" : "",
8694                                 offset * multiplier,
8695                                 WRITEBACK_BIT_SET ? "!" : "");
8696                         else
8697                           func (stream, "], #%s%d",
8698                                 NEGATIVE_BIT_SET ? "-" : "",
8699                                 offset * multiplier);
8700                       }
8701                     else
8702                       func (stream, "]");
8703                   }
8704                   break;
8705
8706                 case 'r':
8707                   {
8708                     int imm4 = (given >> 4) & 0xf;
8709                     int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
8710                     int ubit = ! NEGATIVE_BIT_SET;
8711                     const char *rm = arm_regnames [given & 0xf];
8712                     const char *rn = arm_regnames [(given >> 16) & 0xf];
8713
8714                     switch (puw_bits)
8715                       {
8716                       case 1:
8717                       case 3:
8718                         func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
8719                         if (imm4)
8720                           func (stream, ", lsl #%d", imm4);
8721                         break;
8722
8723                       case 4:
8724                       case 5:
8725                       case 6:
8726                       case 7:
8727                         func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
8728                         if (imm4 > 0)
8729                           func (stream, ", lsl #%d", imm4);
8730                         func (stream, "]");
8731                         if (puw_bits == 5 || puw_bits == 7)
8732                           func (stream, "!");
8733                         break;
8734
8735                       default:
8736                         func (stream, "INVALID");
8737                       }
8738                   }
8739                   break;
8740
8741                 case 'i':
8742                   {
8743                     long imm5;
8744                     imm5 = ((given & 0x100) >> 4) | (given & 0xf);
8745                     func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
8746                   }
8747                   break;
8748
8749                 default:
8750                   abort ();
8751                 }
8752             }
8753           else
8754             func (stream, "%c", *c);
8755         }
8756
8757       if (value_in_comment > 32 || value_in_comment < -16)
8758         func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
8759
8760       if (is_unpredictable)
8761         func (stream, UNPREDICTABLE_INSTRUCTION);
8762
8763       return true;
8764     }
8765   return false;
8766 }
8767
8768 static bool
8769 print_insn_coprocessor (bfd_vma pc,
8770                         struct disassemble_info *info,
8771                         long given,
8772                         bool thumb)
8773 {
8774   return print_insn_coprocessor_1 (coprocessor_opcodes,
8775                                    pc, info, given, thumb);
8776 }
8777
8778 static bool
8779 print_insn_generic_coprocessor (bfd_vma pc,
8780                                 struct disassemble_info *info,
8781                                 long given,
8782                                 bool thumb)
8783 {
8784   return print_insn_coprocessor_1 (generic_coprocessor_opcodes,
8785                                    pc, info, given, thumb);
8786 }
8787
8788 /* Decodes and prints ARM addressing modes.  Returns the offset
8789    used in the address, if any, if it is worthwhile printing the
8790    offset as a hexadecimal value in a comment at the end of the
8791    line of disassembly.  */
8792
8793 static signed long
8794 print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
8795 {
8796   void *stream = info->stream;
8797   fprintf_ftype func = info->fprintf_func;
8798   bfd_vma offset = 0;
8799
8800   if (((given & 0x000f0000) == 0x000f0000)
8801       && ((given & 0x02000000) == 0))
8802     {
8803       offset = given & 0xfff;
8804
8805       func (stream, "[pc");
8806
8807       if (PRE_BIT_SET)
8808         {
8809           /* Pre-indexed.  Elide offset of positive zero when
8810              non-writeback.  */
8811           if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
8812             func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
8813
8814           if (NEGATIVE_BIT_SET)
8815             offset = -offset;
8816
8817           offset += pc + 8;
8818
8819           /* Cope with the possibility of write-back
8820              being used.  Probably a very dangerous thing
8821              for the programmer to do, but who are we to
8822              argue ?  */
8823           func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : "");
8824         }
8825       else  /* Post indexed.  */
8826         {
8827           func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
8828
8829           /* Ie ignore the offset.  */
8830           offset = pc + 8;
8831         }
8832
8833       func (stream, "\t; ");
8834       info->print_address_func (offset, info);
8835       offset = 0;
8836     }
8837   else
8838     {
8839       func (stream, "[%s",
8840             arm_regnames[(given >> 16) & 0xf]);
8841
8842       if (PRE_BIT_SET)
8843         {
8844           if ((given & 0x02000000) == 0)
8845             {
8846               /* Elide offset of positive zero when non-writeback.  */
8847               offset = given & 0xfff;
8848               if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
8849                 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
8850             }
8851           else
8852             {
8853               func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : "");
8854               arm_decode_shift (given, func, stream, true);
8855             }
8856
8857           func (stream, "]%s",
8858                 WRITEBACK_BIT_SET ? "!" : "");
8859         }
8860       else
8861         {
8862           if ((given & 0x02000000) == 0)
8863             {
8864               /* Always show offset.  */
8865               offset = given & 0xfff;
8866               func (stream, "], #%s%d",
8867                     NEGATIVE_BIT_SET ? "-" : "", (int) offset);
8868             }
8869           else
8870             {
8871               func (stream, "], %s",
8872                     NEGATIVE_BIT_SET ? "-" : "");
8873               arm_decode_shift (given, func, stream, true);
8874             }
8875         }
8876       if (NEGATIVE_BIT_SET)
8877         offset = -offset;
8878     }
8879
8880   return (signed long) offset;
8881 }
8882
8883
8884 /* Print one cde instruction on INFO->STREAM.
8885    Return TRUE if the instuction matched, FALSE if this is not a
8886    recognised cde instruction.  */
8887 static bool
8888 print_insn_cde (struct disassemble_info *info, long given, bool thumb)
8889 {
8890   const struct cdeopcode32 *insn;
8891   void *stream = info->stream;
8892   fprintf_ftype func = info->fprintf_func;
8893
8894   if (thumb)
8895   {
8896     /* Manually extract the coprocessor code from a known point.
8897        This position is the same across all CDE instructions.  */
8898     for (insn = cde_opcodes; insn->assembler; insn++)
8899     {
8900       uint16_t coproc = (given >> insn->coproc_shift) & insn->coproc_mask;
8901       uint16_t coproc_mask = 1 << coproc;
8902       if (! (coproc_mask & cde_coprocs))
8903         continue;
8904
8905       if ((given & insn->mask) == insn->value)
8906       {
8907         bool is_unpredictable = false;
8908         const char *c;
8909
8910         for (c = insn->assembler; *c; c++)
8911         {
8912           if (*c == '%')
8913           {
8914             switch (*++c)
8915             {
8916               case '%':
8917                 func (stream, "%%");
8918                 break;
8919
8920               case '0': case '1': case '2': case '3': case '4':
8921               case '5': case '6': case '7': case '8': case '9':
8922               {
8923                 int width;
8924                 unsigned long value;
8925
8926                 c = arm_decode_bitfield (c, given, &value, &width);
8927
8928                 switch (*c)
8929                 {
8930                   case 'S':
8931                     if (value > 10)
8932                       is_unpredictable = true;
8933                     /* Fall through.  */
8934                   case 'R':
8935                     if (value == 13)
8936                       is_unpredictable = true;
8937                     /* Fall through.  */
8938                   case 'r':
8939                     func (stream, "%s", arm_regnames[value]);
8940                     break;
8941
8942                   case 'n':
8943                     if (value == 15)
8944                       func (stream, "%s", "APSR_nzcv");
8945                     else
8946                       func (stream, "%s", arm_regnames[value]);
8947                     break;
8948
8949                   case 'T':
8950                     func (stream, "%s", arm_regnames[value + 1]);
8951                     break;
8952
8953                   case 'd':
8954                     func (stream, "%ld", value);
8955                     break;
8956
8957                   case 'V':
8958                     if (given & (1 << 6))
8959                       func (stream, "q%ld", value >> 1);
8960                     else if (given & (1 << 24))
8961                       func (stream, "d%ld", value);
8962                     else
8963                       {
8964                         /* Encoding for S register is different than for D and
8965                            Q registers.  S registers are encoded using the top
8966                            single bit in position 22 as the lowest bit of the
8967                            register number, while for Q and D it represents the
8968                            highest bit of the register number.  */
8969                         uint8_t top_bit = (value >> 4) & 1;
8970                         uint8_t tmp = (value << 1) & 0x1e;
8971                         uint8_t res = tmp | top_bit;
8972                         func (stream, "s%u", res);
8973                       }
8974                     break;
8975
8976                 default:
8977                   abort ();
8978                 }
8979               }
8980             break;
8981
8982             case 'p':
8983               {
8984                 uint8_t proc_number = (given >> 8) & 0x7;
8985                 func (stream, "p%u", proc_number);
8986                 break;
8987               }
8988
8989             case 'a':
8990               {
8991                 uint8_t a_offset = 28;
8992                 if (given & (1 << a_offset))
8993                   func (stream, "a");
8994                 break;
8995               }
8996           default:
8997             abort ();
8998           }
8999         }
9000         else
9001           func (stream, "%c", *c);
9002       }
9003
9004       if (is_unpredictable)
9005         func (stream, UNPREDICTABLE_INSTRUCTION);
9006
9007       return true;
9008       }
9009     }
9010     return false;
9011   }
9012   else
9013     return false;
9014 }
9015
9016
9017 /* Print one neon instruction on INFO->STREAM.
9018    Return TRUE if the instuction matched, FALSE if this is not a
9019    recognised neon instruction.  */
9020
9021 static bool
9022 print_insn_neon (struct disassemble_info *info, long given, bool thumb)
9023 {
9024   const struct opcode32 *insn;
9025   void *stream = info->stream;
9026   fprintf_ftype func = info->fprintf_func;
9027
9028   if (thumb)
9029     {
9030       if ((given & 0xef000000) == 0xef000000)
9031         {
9032           /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding.  */
9033           unsigned long bit28 = given & (1 << 28);
9034
9035           given &= 0x00ffffff;
9036           if (bit28)
9037             given |= 0xf3000000;
9038           else
9039             given |= 0xf2000000;
9040         }
9041       else if ((given & 0xff000000) == 0xf9000000)
9042         given ^= 0xf9000000 ^ 0xf4000000;
9043       /* BFloat16 neon instructions without special top byte handling.  */
9044       else if ((given & 0xff000000) == 0xfe000000
9045                || (given & 0xff000000) == 0xfc000000)
9046         ;
9047       /* vdup is also a valid neon instruction.  */
9048       else if ((given & 0xff900f5f) != 0xee800b10)
9049         return false;
9050     }
9051
9052   for (insn = neon_opcodes; insn->assembler; insn++)
9053     {
9054       unsigned long cond_mask = insn->mask;
9055       unsigned long cond_value = insn->value;
9056       int cond;
9057
9058       if (thumb)
9059         {
9060           if ((cond_mask & 0xf0000000) == 0) {
9061               /* For the entries in neon_opcodes, an opcode mask/value with
9062                  the high 4 bits equal to 0 indicates a conditional
9063                  instruction. For thumb however, we need to include those
9064                  bits in the instruction matching.  */
9065               cond_mask |= 0xf0000000;
9066               /* Furthermore, the thumb encoding of a conditional instruction
9067                  will have the high 4 bits equal to 0xe.  */
9068               cond_value |= 0xe0000000;
9069           }
9070           if (ifthen_state)
9071             cond = IFTHEN_COND;
9072           else
9073             cond = COND_UNCOND;
9074         }
9075       else
9076         {
9077           if ((given & 0xf0000000) == 0xf0000000)
9078             {
9079               /* If the instruction is unconditional, update the mask to only
9080                  match against unconditional opcode values.  */
9081               cond_mask |= 0xf0000000;
9082               cond = COND_UNCOND;
9083             }
9084           else
9085             {
9086               cond = (given >> 28) & 0xf;
9087               if (cond == 0xe)
9088                 cond = COND_UNCOND;
9089             }
9090         }
9091
9092       if ((given & cond_mask) == cond_value)
9093         {
9094           signed long value_in_comment = 0;
9095           bool is_unpredictable = false;
9096           const char *c;
9097
9098           for (c = insn->assembler; *c; c++)
9099             {
9100               if (*c == '%')
9101                 {
9102                   switch (*++c)
9103                     {
9104                     case '%':
9105                       func (stream, "%%");
9106                       break;
9107
9108                     case 'u':
9109                       if (thumb && ifthen_state)
9110                         is_unpredictable = true;
9111
9112                       /* Fall through.  */
9113                     case 'c':
9114                       func (stream, "%s", arm_conditional[cond]);
9115                       break;
9116
9117                     case 'A':
9118                       {
9119                         static const unsigned char enc[16] =
9120                         {
9121                           0x4, 0x14, /* st4 0,1 */
9122                           0x4, /* st1 2 */
9123                           0x4, /* st2 3 */
9124                           0x3, /* st3 4 */
9125                           0x13, /* st3 5 */
9126                           0x3, /* st1 6 */
9127                           0x1, /* st1 7 */
9128                           0x2, /* st2 8 */
9129                           0x12, /* st2 9 */
9130                           0x2, /* st1 10 */
9131                           0, 0, 0, 0, 0
9132                         };
9133                         int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
9134                         int rn = ((given >> 16) & 0xf);
9135                         int rm = ((given >> 0) & 0xf);
9136                         int align = ((given >> 4) & 0x3);
9137                         int type = ((given >> 8) & 0xf);
9138                         int n = enc[type] & 0xf;
9139                         int stride = (enc[type] >> 4) + 1;
9140                         int ix;
9141
9142                         func (stream, "{");
9143                         if (stride > 1)
9144                           for (ix = 0; ix != n; ix++)
9145                             func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
9146                         else if (n == 1)
9147                           func (stream, "d%d", rd);
9148                         else
9149                           func (stream, "d%d-d%d", rd, rd + n - 1);
9150                         func (stream, "}, [%s", arm_regnames[rn]);
9151                         if (align)
9152                           func (stream, " :%d", 32 << align);
9153                         func (stream, "]");
9154                         if (rm == 0xd)
9155                           func (stream, "!");
9156                         else if (rm != 0xf)
9157                           func (stream, ", %s", arm_regnames[rm]);
9158                       }
9159                       break;
9160
9161                     case 'B':
9162                       {
9163                         int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
9164                         int rn = ((given >> 16) & 0xf);
9165                         int rm = ((given >> 0) & 0xf);
9166                         int idx_align = ((given >> 4) & 0xf);
9167                         int align = 0;
9168                         int size = ((given >> 10) & 0x3);
9169                         int idx = idx_align >> (size + 1);
9170                         int length = ((given >> 8) & 3) + 1;
9171                         int stride = 1;
9172                         int i;
9173
9174                         if (length > 1 && size > 0)
9175                           stride = (idx_align & (1 << size)) ? 2 : 1;
9176
9177                         switch (length)
9178                           {
9179                           case 1:
9180                             {
9181                               int amask = (1 << size) - 1;
9182                               if ((idx_align & (1 << size)) != 0)
9183                                 return false;
9184                               if (size > 0)
9185                                 {
9186                                   if ((idx_align & amask) == amask)
9187                                     align = 8 << size;
9188                                   else if ((idx_align & amask) != 0)
9189                                     return false;
9190                                 }
9191                               }
9192                             break;
9193
9194                           case 2:
9195                             if (size == 2 && (idx_align & 2) != 0)
9196                               return false;
9197                             align = (idx_align & 1) ? 16 << size : 0;
9198                             break;
9199
9200                           case 3:
9201                             if ((size == 2 && (idx_align & 3) != 0)
9202                                 || (idx_align & 1) != 0)
9203                               return false;
9204                             break;
9205
9206                           case 4:
9207                             if (size == 2)
9208                               {
9209                                 if ((idx_align & 3) == 3)
9210                                   return false;
9211                                 align = (idx_align & 3) * 64;
9212                               }
9213                             else
9214                               align = (idx_align & 1) ? 32 << size : 0;
9215                             break;
9216
9217                           default:
9218                             abort ();
9219                           }
9220
9221                         func (stream, "{");
9222                         for (i = 0; i < length; i++)
9223                           func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
9224                             rd + i * stride, idx);
9225                         func (stream, "}, [%s", arm_regnames[rn]);
9226                         if (align)
9227                           func (stream, " :%d", align);
9228                         func (stream, "]");
9229                         if (rm == 0xd)
9230                           func (stream, "!");
9231                         else if (rm != 0xf)
9232                           func (stream, ", %s", arm_regnames[rm]);
9233                       }
9234                       break;
9235
9236                     case 'C':
9237                       {
9238                         int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
9239                         int rn = ((given >> 16) & 0xf);
9240                         int rm = ((given >> 0) & 0xf);
9241                         int align = ((given >> 4) & 0x1);
9242                         int size = ((given >> 6) & 0x3);
9243                         int type = ((given >> 8) & 0x3);
9244                         int n = type + 1;
9245                         int stride = ((given >> 5) & 0x1);
9246                         int ix;
9247
9248                         if (stride && (n == 1))
9249                           n++;
9250                         else
9251                           stride++;
9252
9253                         func (stream, "{");
9254                         if (stride > 1)
9255                           for (ix = 0; ix != n; ix++)
9256                             func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
9257                         else if (n == 1)
9258                           func (stream, "d%d[]", rd);
9259                         else
9260                           func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
9261                         func (stream, "}, [%s", arm_regnames[rn]);
9262                         if (align)
9263                           {
9264                             align = (8 * (type + 1)) << size;
9265                             if (type == 3)
9266                               align = (size > 1) ? align >> 1 : align;
9267                             if (type == 2 || (type == 0 && !size))
9268                               func (stream, " :<bad align %d>", align);
9269                             else
9270                               func (stream, " :%d", align);
9271                           }
9272                         func (stream, "]");
9273                         if (rm == 0xd)
9274                           func (stream, "!");
9275                         else if (rm != 0xf)
9276                           func (stream, ", %s", arm_regnames[rm]);
9277                       }
9278                       break;
9279
9280                     case 'D':
9281                       {
9282                         int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
9283                         int size = (given >> 20) & 3;
9284                         int reg = raw_reg & ((4 << size) - 1);
9285                         int ix = raw_reg >> size >> 2;
9286
9287                         func (stream, "d%d[%d]", reg, ix);
9288                       }
9289                       break;
9290
9291                     case 'E':
9292                       /* Neon encoded constant for mov, mvn, vorr, vbic.  */
9293                       {
9294                         int bits = 0;
9295                         int cmode = (given >> 8) & 0xf;
9296                         int op = (given >> 5) & 0x1;
9297                         unsigned long value = 0, hival = 0;
9298                         unsigned shift;
9299                         int size = 0;
9300                         int isfloat = 0;
9301
9302                         bits |= ((given >> 24) & 1) << 7;
9303                         bits |= ((given >> 16) & 7) << 4;
9304                         bits |= ((given >> 0) & 15) << 0;
9305
9306                         if (cmode < 8)
9307                           {
9308                             shift = (cmode >> 1) & 3;
9309                             value = (unsigned long) bits << (8 * shift);
9310                             size = 32;
9311                           }
9312                         else if (cmode < 12)
9313                           {
9314                             shift = (cmode >> 1) & 1;
9315                             value = (unsigned long) bits << (8 * shift);
9316                             size = 16;
9317                           }
9318                         else if (cmode < 14)
9319                           {
9320                             shift = (cmode & 1) + 1;
9321                             value = (unsigned long) bits << (8 * shift);
9322                             value |= (1ul << (8 * shift)) - 1;
9323                             size = 32;
9324                           }
9325                         else if (cmode == 14)
9326                           {
9327                             if (op)
9328                               {
9329                                 /* Bit replication into bytes.  */
9330                                 int ix;
9331                                 unsigned long mask;
9332
9333                                 value = 0;
9334                                 hival = 0;
9335                                 for (ix = 7; ix >= 0; ix--)
9336                                   {
9337                                     mask = ((bits >> ix) & 1) ? 0xff : 0;
9338                                     if (ix <= 3)
9339                                       value = (value << 8) | mask;
9340                                     else
9341                                       hival = (hival << 8) | mask;
9342                                   }
9343                                 size = 64;
9344                               }
9345                             else
9346                               {
9347                                 /* Byte replication.  */
9348                                 value = (unsigned long) bits;
9349                                 size = 8;
9350                               }
9351                           }
9352                         else if (!op)
9353                           {
9354                             /* Floating point encoding.  */
9355                             int tmp;
9356
9357                             value = (unsigned long)  (bits & 0x7f) << 19;
9358                             value |= (unsigned long) (bits & 0x80) << 24;
9359                             tmp = bits & 0x40 ? 0x3c : 0x40;
9360                             value |= (unsigned long) tmp << 24;
9361                             size = 32;
9362                             isfloat = 1;
9363                           }
9364                         else
9365                           {
9366                             func (stream, "<illegal constant %.8x:%x:%x>",
9367                                   bits, cmode, op);
9368                             size = 32;
9369                             break;
9370                           }
9371                         switch (size)
9372                           {
9373                           case 8:
9374                             func (stream, "#%ld\t; 0x%.2lx", value, value);
9375                             break;
9376
9377                           case 16:
9378                             func (stream, "#%ld\t; 0x%.4lx", value, value);
9379                             break;
9380
9381                           case 32:
9382                             if (isfloat)
9383                               {
9384                                 unsigned char valbytes[4];
9385                                 double fvalue;
9386
9387                                 /* Do this a byte at a time so we don't have to
9388                                    worry about the host's endianness.  */
9389                                 valbytes[0] = value & 0xff;
9390                                 valbytes[1] = (value >> 8) & 0xff;
9391                                 valbytes[2] = (value >> 16) & 0xff;
9392                                 valbytes[3] = (value >> 24) & 0xff;
9393
9394                                 floatformat_to_double
9395                                   (& floatformat_ieee_single_little, valbytes,
9396                                   & fvalue);
9397
9398                                 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
9399                                       value);
9400                               }
9401                             else
9402                               func (stream, "#%ld\t; 0x%.8lx",
9403                                     (long) (((value & 0x80000000L) != 0)
9404                                             ? value | ~0xffffffffL : value),
9405                                     value);
9406                             break;
9407
9408                           case 64:
9409                             func (stream, "#0x%.8lx%.8lx", hival, value);
9410                             break;
9411
9412                           default:
9413                             abort ();
9414                           }
9415                       }
9416                       break;
9417
9418                     case 'F':
9419                       {
9420                         int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
9421                         int num = (given >> 8) & 0x3;
9422
9423                         if (!num)
9424                           func (stream, "{d%d}", regno);
9425                         else if (num + regno >= 32)
9426                           func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
9427                         else
9428                           func (stream, "{d%d-d%d}", regno, regno + num);
9429                       }
9430                       break;
9431
9432
9433                     case '0': case '1': case '2': case '3': case '4':
9434                     case '5': case '6': case '7': case '8': case '9':
9435                       {
9436                         int width;
9437                         unsigned long value;
9438
9439                         c = arm_decode_bitfield (c, given, &value, &width);
9440
9441                         switch (*c)
9442                           {
9443                           case 'r':
9444                             func (stream, "%s", arm_regnames[value]);
9445                             break;
9446                           case 'd':
9447                             func (stream, "%ld", value);
9448                             value_in_comment = value;
9449                             break;
9450                           case 'e':
9451                             func (stream, "%ld", (1ul << width) - value);
9452                             break;
9453
9454                           case 'S':
9455                           case 'T':
9456                           case 'U':
9457                             /* Various width encodings.  */
9458                             {
9459                               int base = 8 << (*c - 'S'); /* 8,16 or 32 */
9460                               int limit;
9461                               unsigned low, high;
9462
9463                               c++;
9464                               if (*c >= '0' && *c <= '9')
9465                                 limit = *c - '0';
9466                               else if (*c >= 'a' && *c <= 'f')
9467                                 limit = *c - 'a' + 10;
9468                               else
9469                                 abort ();
9470                               low = limit >> 2;
9471                               high = limit & 3;
9472
9473                               if (value < low || value > high)
9474                                 func (stream, "<illegal width %d>", base << value);
9475                               else
9476                                 func (stream, "%d", base << value);
9477                             }
9478                             break;
9479                           case 'R':
9480                             if (given & (1 << 6))
9481                               goto Q;
9482                             /* FALLTHROUGH */
9483                           case 'D':
9484                             func (stream, "d%ld", value);
9485                             break;
9486                           case 'Q':
9487                           Q:
9488                             if (value & 1)
9489                               func (stream, "<illegal reg q%ld.5>", value >> 1);
9490                             else
9491                               func (stream, "q%ld", value >> 1);
9492                             break;
9493
9494                           case '`':
9495                             c++;
9496                             if (value == 0)
9497                               func (stream, "%c", *c);
9498                             break;
9499                           case '\'':
9500                             c++;
9501                             if (value == ((1ul << width) - 1))
9502                               func (stream, "%c", *c);
9503                             break;
9504                           case '?':
9505                             func (stream, "%c", c[(1 << width) - (int) value]);
9506                             c += 1 << width;
9507                             break;
9508                           default:
9509                             abort ();
9510                           }
9511                       }
9512                       break;
9513
9514                     default:
9515                       abort ();
9516                     }
9517                 }
9518               else
9519                 func (stream, "%c", *c);
9520             }
9521
9522           if (value_in_comment > 32 || value_in_comment < -16)
9523             func (stream, "\t; 0x%lx", value_in_comment);
9524
9525           if (is_unpredictable)
9526             func (stream, UNPREDICTABLE_INSTRUCTION);
9527
9528           return true;
9529         }
9530     }
9531   return false;
9532 }
9533
9534 /* Print one mve instruction on INFO->STREAM.
9535    Return TRUE if the instuction matched, FALSE if this is not a
9536    recognised mve instruction.  */
9537
9538 static bool
9539 print_insn_mve (struct disassemble_info *info, long given)
9540 {
9541   const struct mopcode32 *insn;
9542   void *stream = info->stream;
9543   fprintf_ftype func = info->fprintf_func;
9544
9545   for (insn = mve_opcodes; insn->assembler; insn++)
9546     {
9547       if (((given & insn->mask) == insn->value)
9548           && !is_mve_encoding_conflict (given, insn->mve_op))
9549         {
9550           signed long value_in_comment = 0;
9551           bool is_unpredictable = false;
9552           bool is_undefined = false;
9553           const char *c;
9554           enum mve_unpredictable unpredictable_cond = UNPRED_NONE;
9555           enum mve_undefined undefined_cond = UNDEF_NONE;
9556
9557           /* Most vector mve instruction are illegal in a it block.
9558              There are a few exceptions; check for them.  */
9559           if (ifthen_state && !is_mve_okay_in_it (insn->mve_op))
9560             {
9561               is_unpredictable = true;
9562               unpredictable_cond = UNPRED_IT_BLOCK;
9563             }
9564           else if (is_mve_unpredictable (given, insn->mve_op,
9565                                          &unpredictable_cond))
9566             is_unpredictable = true;
9567
9568           if (is_mve_undefined (given, insn->mve_op, &undefined_cond))
9569             is_undefined = true;
9570
9571           /* In "VORR Qd, Qm, Qn", if Qm==Qn, VORR is nothing but VMOV,
9572              i.e "VMOV Qd, Qm".  */
9573           if ((insn->mve_op == MVE_VORR_REG)
9574               && (arm_decode_field (given, 1, 3)
9575                   == arm_decode_field (given, 17, 19)))
9576             continue;
9577
9578           for (c = insn->assembler; *c; c++)
9579             {
9580               if (*c == '%')
9581                 {
9582                   switch (*++c)
9583                     {
9584                     case '%':
9585                       func (stream, "%%");
9586                       break;
9587
9588                     case 'a':
9589                       /* Don't print anything for '+' as it is implied.  */
9590                       if (arm_decode_field (given, 23, 23) == 0)
9591                         func (stream, "-");
9592                       break;
9593
9594                     case 'c':
9595                       if (ifthen_state)
9596                         func (stream, "%s", arm_conditional[IFTHEN_COND]);
9597                       break;
9598
9599                     case 'd':
9600                       print_mve_vld_str_addr (info, given, insn->mve_op);
9601                       break;
9602
9603                     case 'i':
9604                       {
9605                         long mve_mask = mve_extract_pred_mask (given);
9606                         func (stream, "%s", mve_predicatenames[mve_mask]);
9607                       }
9608                       break;
9609
9610                     case 'j':
9611                       {
9612                         unsigned int imm5 = 0;
9613                         imm5 |= arm_decode_field (given, 6, 7);
9614                         imm5 |= (arm_decode_field (given, 12, 14) << 2);
9615                         func (stream, "#%u", (imm5 == 0) ? 32 : imm5);
9616                       }
9617                       break;
9618
9619                     case 'k':
9620                       func (stream, "#%u",
9621                             (arm_decode_field (given, 7, 7) == 0) ? 64 : 48);
9622                       break;
9623
9624                     case 'n':
9625                       print_vec_condition (info, given, insn->mve_op);
9626                       break;
9627
9628                     case 'o':
9629                       if (arm_decode_field (given, 0, 0) == 1)
9630                         {
9631                           unsigned long size
9632                             = arm_decode_field (given, 4, 4)
9633                               | (arm_decode_field (given, 6, 6) << 1);
9634
9635                           func (stream, ", uxtw #%lu", size);
9636                         }
9637                       break;
9638
9639                     case 'm':
9640                       print_mve_rounding_mode (info, given, insn->mve_op);
9641                       break;
9642
9643                     case 's':
9644                       print_mve_vcvt_size (info, given, insn->mve_op);
9645                       break;
9646
9647                     case 'u':
9648                       {
9649                         unsigned long op1 = arm_decode_field (given, 21, 22);
9650
9651                         if ((insn->mve_op == MVE_VMOV_VEC_LANE_TO_GP))
9652                           {
9653                             /* Check for signed.  */
9654                             if (arm_decode_field (given, 23, 23) == 0)
9655                               {
9656                                 /* We don't print 's' for S32.  */
9657                                 if ((arm_decode_field (given, 5, 6) == 0)
9658                                     && ((op1 == 0) || (op1 == 1)))
9659                                   ;
9660                                 else
9661                                   func (stream, "s");
9662                               }
9663                             else
9664                               func (stream, "u");
9665                           }
9666                         else
9667                           {
9668                             if (arm_decode_field (given, 28, 28) == 0)
9669                               func (stream, "s");
9670                             else
9671                               func (stream, "u");
9672                           }
9673                       }
9674                       break;
9675
9676                     case 'v':
9677                       print_instruction_predicate (info);
9678                       break;
9679
9680                     case 'w':
9681                       if (arm_decode_field (given, 21, 21) == 1)
9682                         func (stream, "!");
9683                       break;
9684
9685                     case 'B':
9686                       print_mve_register_blocks (info, given, insn->mve_op);
9687                       break;
9688
9689                     case 'E':
9690                       /* SIMD encoded constant for mov, mvn, vorr, vbic.  */
9691
9692                       print_simd_imm8 (info, given, 28, insn);
9693                       break;
9694
9695                     case 'N':
9696                       print_mve_vmov_index (info, given);
9697                       break;
9698
9699                     case 'T':
9700                       if (arm_decode_field (given, 12, 12) == 0)
9701                         func (stream, "b");
9702                       else
9703                         func (stream, "t");
9704                       break;
9705
9706                     case 'X':
9707                       if (arm_decode_field (given, 12, 12) == 1)
9708                         func (stream, "x");
9709                       break;
9710
9711                     case '0': case '1': case '2': case '3': case '4':
9712                     case '5': case '6': case '7': case '8': case '9':
9713                       {
9714                         int width;
9715                         unsigned long value;
9716
9717                         c = arm_decode_bitfield (c, given, &value, &width);
9718
9719                         switch (*c)
9720                           {
9721                           case 'Z':
9722                             if (value == 13)
9723                               is_unpredictable = true;
9724                             else if (value == 15)
9725                               func (stream, "zr");
9726                             else
9727                               func (stream, "%s", arm_regnames[value]);
9728                             break;
9729
9730                           case 'c':
9731                             func (stream, "%s", arm_conditional[value]);
9732                             break;
9733
9734                           case 'C':
9735                             value ^= 1;
9736                             func (stream, "%s", arm_conditional[value]);
9737                             break;
9738
9739                           case 'S':
9740                             if (value == 13 || value == 15)
9741                               is_unpredictable = true;
9742                             else
9743                               func (stream, "%s", arm_regnames[value]);
9744                             break;
9745
9746                           case 's':
9747                             print_mve_size (info,
9748                                             value,
9749                                             insn->mve_op);
9750                             break;
9751                           case 'I':
9752                             if (value == 1)
9753                               func (stream, "i");
9754                             break;
9755                           case 'A':
9756                             if (value == 1)
9757                               func (stream, "a");
9758                             break;
9759                           case 'h':
9760                             {
9761                               unsigned int odd_reg = (value << 1) | 1;
9762                               func (stream, "%s", arm_regnames[odd_reg]);
9763                             }
9764                             break;
9765                           case 'i':
9766                             {
9767                               unsigned long imm
9768                                 = arm_decode_field (given, 0, 6);
9769                               unsigned long mod_imm = imm;
9770
9771                               switch (insn->mve_op)
9772                                 {
9773                                 case MVE_VLDRW_GATHER_T5:
9774                                 case MVE_VSTRW_SCATTER_T5:
9775                                   mod_imm = mod_imm << 2;
9776                                   break;
9777                                 case MVE_VSTRD_SCATTER_T6:
9778                                 case MVE_VLDRD_GATHER_T6:
9779                                   mod_imm = mod_imm << 3;
9780                                   break;
9781
9782                                 default:
9783                                   break;
9784                                 }
9785
9786                               func (stream, "%lu", mod_imm);
9787                             }
9788                             break;
9789                           case 'k':
9790                             func (stream, "%lu", 64 - value);
9791                             break;
9792                           case 'l':
9793                             {
9794                               unsigned int even_reg = value << 1;
9795                               func (stream, "%s", arm_regnames[even_reg]);
9796                             }
9797                             break;
9798                           case 'u':
9799                             switch (value)
9800                               {
9801                               case 0:
9802                                 func (stream, "1");
9803                                 break;
9804                               case 1:
9805                                 func (stream, "2");
9806                                 break;
9807                               case 2:
9808                                 func (stream, "4");
9809                                 break;
9810                               case 3:
9811                                 func (stream, "8");
9812                                 break;
9813                               default:
9814                                 break;
9815                               }
9816                             break;
9817                           case 'o':
9818                             print_mve_rotate (info, value, width);
9819                             break;
9820                           case 'r':
9821                             func (stream, "%s", arm_regnames[value]);
9822                             break;
9823                           case 'd':
9824                             if (insn->mve_op == MVE_VQSHL_T2
9825                                 || insn->mve_op == MVE_VQSHLU_T3
9826                                 || insn->mve_op == MVE_VRSHR
9827                                 || insn->mve_op == MVE_VRSHRN
9828                                 || insn->mve_op == MVE_VSHL_T1
9829                                 || insn->mve_op == MVE_VSHLL_T1
9830                                 || insn->mve_op == MVE_VSHR
9831                                 || insn->mve_op == MVE_VSHRN
9832                                 || insn->mve_op == MVE_VSLI
9833                                 || insn->mve_op == MVE_VSRI)
9834                               print_mve_shift_n (info, given, insn->mve_op);
9835                             else if (insn->mve_op == MVE_VSHLL_T2)
9836                               {
9837                                 switch (value)
9838                                   {
9839                                   case 0x00:
9840                                     func (stream, "8");
9841                                     break;
9842                                   case 0x01:
9843                                     func (stream, "16");
9844                                     break;
9845                                   case 0x10:
9846                                     print_mve_undefined (info, UNDEF_SIZE_0);
9847                                     break;
9848                                   default:
9849                                     assert (0);
9850                                     break;
9851                                   }
9852                               }
9853                             else
9854                               {
9855                                 if (insn->mve_op == MVE_VSHLC && value == 0)
9856                                   value = 32;
9857                                 func (stream, "%ld", value);
9858                                 value_in_comment = value;
9859                               }
9860                             break;
9861                           case 'F':
9862                             func (stream, "s%ld", value);
9863                             break;
9864                           case 'Q':
9865                             if (value & 0x8)
9866                               func (stream, "<illegal reg q%ld.5>", value);
9867                             else
9868                               func (stream, "q%ld", value);
9869                             break;
9870                           case 'x':
9871                             func (stream, "0x%08lx", value);
9872                             break;
9873                           default:
9874                             abort ();
9875                           }
9876                         break;
9877                       default:
9878                         abort ();
9879                       }
9880                     }
9881                 }
9882               else
9883                 func (stream, "%c", *c);
9884             }
9885
9886           if (value_in_comment > 32 || value_in_comment < -16)
9887             func (stream, "\t; 0x%lx", value_in_comment);
9888
9889           if (is_unpredictable)
9890             print_mve_unpredictable (info, unpredictable_cond);
9891
9892           if (is_undefined)
9893             print_mve_undefined (info, undefined_cond);
9894
9895           if (!vpt_block_state.in_vpt_block
9896               && !ifthen_state
9897               && is_vpt_instruction (given))
9898             mark_inside_vpt_block (given);
9899           else if (vpt_block_state.in_vpt_block)
9900             update_vpt_block_state ();
9901
9902           return true;
9903         }
9904     }
9905   return false;
9906 }
9907
9908
9909 /* Return the name of a v7A special register.  */
9910
9911 static const char *
9912 banked_regname (unsigned reg)
9913 {
9914   switch (reg)
9915     {
9916       case 15: return "CPSR";
9917       case 32: return "R8_usr";
9918       case 33: return "R9_usr";
9919       case 34: return "R10_usr";
9920       case 35: return "R11_usr";
9921       case 36: return "R12_usr";
9922       case 37: return "SP_usr";
9923       case 38: return "LR_usr";
9924       case 40: return "R8_fiq";
9925       case 41: return "R9_fiq";
9926       case 42: return "R10_fiq";
9927       case 43: return "R11_fiq";
9928       case 44: return "R12_fiq";
9929       case 45: return "SP_fiq";
9930       case 46: return "LR_fiq";
9931       case 48: return "LR_irq";
9932       case 49: return "SP_irq";
9933       case 50: return "LR_svc";
9934       case 51: return "SP_svc";
9935       case 52: return "LR_abt";
9936       case 53: return "SP_abt";
9937       case 54: return "LR_und";
9938       case 55: return "SP_und";
9939       case 60: return "LR_mon";
9940       case 61: return "SP_mon";
9941       case 62: return "ELR_hyp";
9942       case 63: return "SP_hyp";
9943       case 79: return "SPSR";
9944       case 110: return "SPSR_fiq";
9945       case 112: return "SPSR_irq";
9946       case 114: return "SPSR_svc";
9947       case 116: return "SPSR_abt";
9948       case 118: return "SPSR_und";
9949       case 124: return "SPSR_mon";
9950       case 126: return "SPSR_hyp";
9951       default: return NULL;
9952     }
9953 }
9954
9955 /* Return the name of the DMB/DSB option.  */
9956 static const char *
9957 data_barrier_option (unsigned option)
9958 {
9959   switch (option & 0xf)
9960     {
9961     case 0xf: return "sy";
9962     case 0xe: return "st";
9963     case 0xd: return "ld";
9964     case 0xb: return "ish";
9965     case 0xa: return "ishst";
9966     case 0x9: return "ishld";
9967     case 0x7: return "un";
9968     case 0x6: return "unst";
9969     case 0x5: return "nshld";
9970     case 0x3: return "osh";
9971     case 0x2: return "oshst";
9972     case 0x1: return "oshld";
9973     default:  return NULL;
9974     }
9975 }
9976
9977 /* Print one ARM instruction from PC on INFO->STREAM.  */
9978
9979 static void
9980 print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
9981 {
9982   const struct opcode32 *insn;
9983   void *stream = info->stream;
9984   fprintf_ftype func = info->fprintf_func;
9985   struct arm_private_data *private_data = info->private_data;
9986
9987   if (print_insn_coprocessor (pc, info, given, false))
9988     return;
9989
9990   if (print_insn_neon (info, given, false))
9991     return;
9992
9993   if (print_insn_generic_coprocessor (pc, info, given, false))
9994     return;
9995
9996   for (insn = arm_opcodes; insn->assembler; insn++)
9997     {
9998       if ((given & insn->mask) != insn->value)
9999         continue;
10000
10001       if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features))
10002         continue;
10003
10004       /* Special case: an instruction with all bits set in the condition field
10005          (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
10006          or by the catchall at the end of the table.  */
10007       if ((given & 0xF0000000) != 0xF0000000
10008           || (insn->mask & 0xF0000000) == 0xF0000000
10009           || (insn->mask == 0 && insn->value == 0))
10010         {
10011           unsigned long u_reg = 16;
10012           unsigned long U_reg = 16;
10013           bool is_unpredictable = false;
10014           signed long value_in_comment = 0;
10015           const char *c;
10016
10017           for (c = insn->assembler; *c; c++)
10018             {
10019               if (*c == '%')
10020                 {
10021                   bool allow_unpredictable = false;
10022
10023                   switch (*++c)
10024                     {
10025                     case '%':
10026                       func (stream, "%%");
10027                       break;
10028
10029                     case 'a':
10030                       value_in_comment = print_arm_address (pc, info, given);
10031                       break;
10032
10033                     case 'P':
10034                       /* Set P address bit and use normal address
10035                          printing routine.  */
10036                       value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
10037                       break;
10038
10039                     case 'S':
10040                       allow_unpredictable = true;
10041                       /* Fall through.  */
10042                     case 's':
10043                       if ((given & 0x004f0000) == 0x004f0000)
10044                         {
10045                           /* PC relative with immediate offset.  */
10046                           bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
10047
10048                           if (PRE_BIT_SET)
10049                             {
10050                               /* Elide positive zero offset.  */
10051                               if (offset || NEGATIVE_BIT_SET)
10052                                 func (stream, "[pc, #%s%d]\t; ",
10053                                       NEGATIVE_BIT_SET ? "-" : "", (int) offset);
10054                               else
10055                                 func (stream, "[pc]\t; ");
10056                               if (NEGATIVE_BIT_SET)
10057                                 offset = -offset;
10058                               info->print_address_func (offset + pc + 8, info);
10059                             }
10060                           else
10061                             {
10062                               /* Always show the offset.  */
10063                               func (stream, "[pc], #%s%d",
10064                                     NEGATIVE_BIT_SET ? "-" : "", (int) offset);
10065                               if (! allow_unpredictable)
10066                                 is_unpredictable = true;
10067                             }
10068                         }
10069                       else
10070                         {
10071                           int offset = ((given & 0xf00) >> 4) | (given & 0xf);
10072
10073                           func (stream, "[%s",
10074                                 arm_regnames[(given >> 16) & 0xf]);
10075
10076                           if (PRE_BIT_SET)
10077                             {
10078                               if (IMMEDIATE_BIT_SET)
10079                                 {
10080                                   /* Elide offset for non-writeback
10081                                      positive zero.  */
10082                                   if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
10083                                       || offset)
10084                                     func (stream, ", #%s%d",
10085                                           NEGATIVE_BIT_SET ? "-" : "", offset);
10086
10087                                   if (NEGATIVE_BIT_SET)
10088                                     offset = -offset;
10089
10090                                   value_in_comment = offset;
10091                                 }
10092                               else
10093                                 {
10094                                   /* Register Offset or Register Pre-Indexed.  */
10095                                   func (stream, ", %s%s",
10096                                         NEGATIVE_BIT_SET ? "-" : "",
10097                                         arm_regnames[given & 0xf]);
10098
10099                                   /* Writing back to the register that is the source/
10100                                      destination of the load/store is unpredictable.  */
10101                                   if (! allow_unpredictable
10102                                       && WRITEBACK_BIT_SET
10103                                       && ((given & 0xf) == ((given >> 12) & 0xf)))
10104                                     is_unpredictable = true;
10105                                 }
10106
10107                               func (stream, "]%s",
10108                                     WRITEBACK_BIT_SET ? "!" : "");
10109                             }
10110                           else
10111                             {
10112                               if (IMMEDIATE_BIT_SET)
10113                                 {
10114                                   /* Immediate Post-indexed.  */
10115                                   /* PR 10924: Offset must be printed, even if it is zero.  */
10116                                   func (stream, "], #%s%d",
10117                                         NEGATIVE_BIT_SET ? "-" : "", offset);
10118                                   if (NEGATIVE_BIT_SET)
10119                                     offset = -offset;
10120                                   value_in_comment = offset;
10121                                 }
10122                               else
10123                                 {
10124                                   /* Register Post-indexed.  */
10125                                   func (stream, "], %s%s",
10126                                         NEGATIVE_BIT_SET ? "-" : "",
10127                                         arm_regnames[given & 0xf]);
10128
10129                                   /* Writing back to the register that is the source/
10130                                      destination of the load/store is unpredictable.  */
10131                                   if (! allow_unpredictable
10132                                       && (given & 0xf) == ((given >> 12) & 0xf))
10133                                     is_unpredictable = true;
10134                                 }
10135
10136                               if (! allow_unpredictable)
10137                                 {
10138                                   /* Writeback is automatically implied by post- addressing.
10139                                      Setting the W bit is unnecessary and ARM specify it as
10140                                      being unpredictable.  */
10141                                   if (WRITEBACK_BIT_SET
10142                                       /* Specifying the PC register as the post-indexed
10143                                          registers is also unpredictable.  */
10144                                       || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
10145                                     is_unpredictable = true;
10146                                 }
10147                             }
10148                         }
10149                       break;
10150
10151                     case 'b':
10152                       {
10153                         bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
10154                         bfd_vma target = disp * 4 + pc + 8;
10155                         info->print_address_func (target, info);
10156
10157                         /* Fill in instruction information.  */
10158                         info->insn_info_valid = 1;
10159                         info->insn_type = dis_branch;
10160                         info->target = target;
10161                       }
10162                       break;
10163
10164                     case 'c':
10165                       if (((given >> 28) & 0xf) != 0xe)
10166                         func (stream, "%s",
10167                               arm_conditional [(given >> 28) & 0xf]);
10168                       break;
10169
10170                     case 'm':
10171                       {
10172                         int started = 0;
10173                         int reg;
10174
10175                         func (stream, "{");
10176                         for (reg = 0; reg < 16; reg++)
10177                           if ((given & (1 << reg)) != 0)
10178                             {
10179                               if (started)
10180                                 func (stream, ", ");
10181                               started = 1;
10182                               func (stream, "%s", arm_regnames[reg]);
10183                             }
10184                         func (stream, "}");
10185                         if (! started)
10186                           is_unpredictable = true;
10187                       }
10188                       break;
10189
10190                     case 'q':
10191                       arm_decode_shift (given, func, stream, false);
10192                       break;
10193
10194                     case 'o':
10195                       if ((given & 0x02000000) != 0)
10196                         {
10197                           unsigned int rotate = (given & 0xf00) >> 7;
10198                           unsigned int immed = (given & 0xff);
10199                           unsigned int a, i;
10200
10201                           a = (immed << ((32 - rotate) & 31)
10202                                | immed >> rotate) & 0xffffffff;
10203                           /* If there is another encoding with smaller rotate,
10204                              the rotate should be specified directly.  */
10205                           for (i = 0; i < 32; i += 2)
10206                             if ((a << i | a >> ((32 - i) & 31)) <= 0xff)
10207                               break;
10208
10209                           if (i != rotate)
10210                             func (stream, "#%d, %d", immed, rotate);
10211                           else
10212                             func (stream, "#%d", a);
10213                           value_in_comment = a;
10214                         }
10215                       else
10216                         arm_decode_shift (given, func, stream, true);
10217                       break;
10218
10219                     case 'p':
10220                       if ((given & 0x0000f000) == 0x0000f000)
10221                         {
10222                           arm_feature_set arm_ext_v6 =
10223                             ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
10224
10225                           /* The p-variants of tst/cmp/cmn/teq are the pre-V6
10226                              mechanism for setting PSR flag bits.  They are
10227                              obsolete in V6 onwards.  */
10228                           if (! ARM_CPU_HAS_FEATURE (private_data->features, \
10229                                                      arm_ext_v6))
10230                             func (stream, "p");
10231                           else
10232                             is_unpredictable = true;
10233                         }
10234                       break;
10235
10236                     case 't':
10237                       if ((given & 0x01200000) == 0x00200000)
10238                         func (stream, "t");
10239                       break;
10240
10241                     case 'A':
10242                       {
10243                         int offset = given & 0xff;
10244
10245                         value_in_comment = offset * 4;
10246                         if (NEGATIVE_BIT_SET)
10247                           value_in_comment = - value_in_comment;
10248
10249                         func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
10250
10251                         if (PRE_BIT_SET)
10252                           {
10253                             if (offset)
10254                               func (stream, ", #%d]%s",
10255                                     (int) value_in_comment,
10256                                     WRITEBACK_BIT_SET ? "!" : "");
10257                             else
10258                               func (stream, "]");
10259                           }
10260                         else
10261                           {
10262                             func (stream, "]");
10263
10264                             if (WRITEBACK_BIT_SET)
10265                               {
10266                                 if (offset)
10267                                   func (stream, ", #%d", (int) value_in_comment);
10268                               }
10269                             else
10270                               {
10271                                 func (stream, ", {%d}", (int) offset);
10272                                 value_in_comment = offset;
10273                               }
10274                           }
10275                       }
10276                       break;
10277
10278                     case 'B':
10279                       /* Print ARM V5 BLX(1) address: pc+25 bits.  */
10280                       {
10281                         bfd_vma address;
10282                         bfd_vma offset = 0;
10283
10284                         if (! NEGATIVE_BIT_SET)
10285                           /* Is signed, hi bits should be ones.  */
10286                           offset = (-1) ^ 0x00ffffff;
10287
10288                         /* Offset is (SignExtend(offset field)<<2).  */
10289                         offset += given & 0x00ffffff;
10290                         offset <<= 2;
10291                         address = offset + pc + 8;
10292
10293                         if (given & 0x01000000)
10294                           /* H bit allows addressing to 2-byte boundaries.  */
10295                           address += 2;
10296
10297                         info->print_address_func (address, info);
10298
10299                         /* Fill in instruction information.  */
10300                         info->insn_info_valid = 1;
10301                         info->insn_type = dis_branch;
10302                         info->target = address;
10303                       }
10304                       break;
10305
10306                     case 'C':
10307                       if ((given & 0x02000200) == 0x200)
10308                         {
10309                           const char * name;
10310                           unsigned sysm = (given & 0x004f0000) >> 16;
10311
10312                           sysm |= (given & 0x300) >> 4;
10313                           name = banked_regname (sysm);
10314
10315                           if (name != NULL)
10316                             func (stream, "%s", name);
10317                           else
10318                             func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
10319                         }
10320                       else
10321                         {
10322                           func (stream, "%cPSR_",
10323                                 (given & 0x00400000) ? 'S' : 'C');
10324                           if (given & 0x80000)
10325                             func (stream, "f");
10326                           if (given & 0x40000)
10327                             func (stream, "s");
10328                           if (given & 0x20000)
10329                             func (stream, "x");
10330                           if (given & 0x10000)
10331                             func (stream, "c");
10332                         }
10333                       break;
10334
10335                     case 'U':
10336                       if ((given & 0xf0) == 0x60)
10337                         {
10338                           switch (given & 0xf)
10339                             {
10340                             case 0xf: func (stream, "sy"); break;
10341                             default:
10342                               func (stream, "#%d", (int) given & 0xf);
10343                               break;
10344                             }
10345                         }
10346                       else
10347                         {
10348                           const char * opt = data_barrier_option (given & 0xf);
10349                           if (opt != NULL)
10350                             func (stream, "%s", opt);
10351                           else
10352                               func (stream, "#%d", (int) given & 0xf);
10353                         }
10354                       break;
10355
10356                     case '0': case '1': case '2': case '3': case '4':
10357                     case '5': case '6': case '7': case '8': case '9':
10358                       {
10359                         int width;
10360                         unsigned long value;
10361
10362                         c = arm_decode_bitfield (c, given, &value, &width);
10363
10364                         switch (*c)
10365                           {
10366                           case 'R':
10367                             if (value == 15)
10368                               is_unpredictable = true;
10369                             /* Fall through.  */
10370                           case 'r':
10371                           case 'T':
10372                             /* We want register + 1 when decoding T.  */
10373                             if (*c == 'T')
10374                               value = (value + 1) & 0xf;
10375
10376                             if (c[1] == 'u')
10377                               {
10378                                 /* Eat the 'u' character.  */
10379                                 ++ c;
10380
10381                                 if (u_reg == value)
10382                                   is_unpredictable = true;
10383                                 u_reg = value;
10384                               }
10385                             if (c[1] == 'U')
10386                               {
10387                                 /* Eat the 'U' character.  */
10388                                 ++ c;
10389
10390                                 if (U_reg == value)
10391                                   is_unpredictable = true;
10392                                 U_reg = value;
10393                               }
10394                             func (stream, "%s", arm_regnames[value]);
10395                             break;
10396                           case 'd':
10397                             func (stream, "%ld", value);
10398                             value_in_comment = value;
10399                             break;
10400                           case 'b':
10401                             func (stream, "%ld", value * 8);
10402                             value_in_comment = value * 8;
10403                             break;
10404                           case 'W':
10405                             func (stream, "%ld", value + 1);
10406                             value_in_comment = value + 1;
10407                             break;
10408                           case 'x':
10409                             func (stream, "0x%08lx", value);
10410
10411                             /* Some SWI instructions have special
10412                                meanings.  */
10413                             if ((given & 0x0fffffff) == 0x0FF00000)
10414                               func (stream, "\t; IMB");
10415                             else if ((given & 0x0fffffff) == 0x0FF00001)
10416                               func (stream, "\t; IMBRange");
10417                             break;
10418                           case 'X':
10419                             func (stream, "%01lx", value & 0xf);
10420                             value_in_comment = value;
10421                             break;
10422                           case '`':
10423                             c++;
10424                             if (value == 0)
10425                               func (stream, "%c", *c);
10426                             break;
10427                           case '\'':
10428                             c++;
10429                             if (value == ((1ul << width) - 1))
10430                               func (stream, "%c", *c);
10431                             break;
10432                           case '?':
10433                             func (stream, "%c", c[(1 << width) - (int) value]);
10434                             c += 1 << width;
10435                             break;
10436                           default:
10437                             abort ();
10438                           }
10439                       }
10440                       break;
10441
10442                     case 'e':
10443                       {
10444                         int imm;
10445
10446                         imm = (given & 0xf) | ((given & 0xfff00) >> 4);
10447                         func (stream, "%d", imm);
10448                         value_in_comment = imm;
10449                       }
10450                       break;
10451
10452                     case 'E':
10453                       /* LSB and WIDTH fields of BFI or BFC.  The machine-
10454                          language instruction encodes LSB and MSB.  */
10455                       {
10456                         long msb = (given & 0x001f0000) >> 16;
10457                         long lsb = (given & 0x00000f80) >> 7;
10458                         long w = msb - lsb + 1;
10459
10460                         if (w > 0)
10461                           func (stream, "#%lu, #%lu", lsb, w);
10462                         else
10463                           func (stream, "(invalid: %lu:%lu)", lsb, msb);
10464                       }
10465                       break;
10466
10467                     case 'R':
10468                       /* Get the PSR/banked register name.  */
10469                       {
10470                         const char * name;
10471                         unsigned sysm = (given & 0x004f0000) >> 16;
10472
10473                         sysm |= (given & 0x300) >> 4;
10474                         name = banked_regname (sysm);
10475
10476                         if (name != NULL)
10477                           func (stream, "%s", name);
10478                         else
10479                           func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
10480                       }
10481                       break;
10482
10483                     case 'V':
10484                       /* 16-bit unsigned immediate from a MOVT or MOVW
10485                          instruction, encoded in bits 0:11 and 15:19.  */
10486                       {
10487                         long hi = (given & 0x000f0000) >> 4;
10488                         long lo = (given & 0x00000fff);
10489                         long imm16 = hi | lo;
10490
10491                         func (stream, "#%lu", imm16);
10492                         value_in_comment = imm16;
10493                       }
10494                       break;
10495
10496                     default:
10497                       abort ();
10498                     }
10499                 }
10500               else
10501                 func (stream, "%c", *c);
10502             }
10503
10504           if (value_in_comment > 32 || value_in_comment < -16)
10505             func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
10506
10507           if (is_unpredictable)
10508             func (stream, UNPREDICTABLE_INSTRUCTION);
10509
10510           return;
10511         }
10512     }
10513   func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
10514   return;
10515 }
10516
10517 /* Print one 16-bit Thumb instruction from PC on INFO->STREAM.  */
10518
10519 static void
10520 print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
10521 {
10522   const struct opcode16 *insn;
10523   void *stream = info->stream;
10524   fprintf_ftype func = info->fprintf_func;
10525
10526   for (insn = thumb_opcodes; insn->assembler; insn++)
10527     if ((given & insn->mask) == insn->value)
10528       {
10529         signed long value_in_comment = 0;
10530         const char *c = insn->assembler;
10531
10532         for (; *c; c++)
10533           {
10534             int domaskpc = 0;
10535             int domasklr = 0;
10536
10537             if (*c != '%')
10538               {
10539                 func (stream, "%c", *c);
10540                 continue;
10541               }
10542
10543             switch (*++c)
10544               {
10545               case '%':
10546                 func (stream, "%%");
10547                 break;
10548
10549               case 'c':
10550                 if (ifthen_state)
10551                   func (stream, "%s", arm_conditional[IFTHEN_COND]);
10552                 break;
10553
10554               case 'C':
10555                 if (ifthen_state)
10556                   func (stream, "%s", arm_conditional[IFTHEN_COND]);
10557                 else
10558                   func (stream, "s");
10559                 break;
10560
10561               case 'I':
10562                 {
10563                   unsigned int tmp;
10564
10565                   ifthen_next_state = given & 0xff;
10566                   for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
10567                     func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
10568                   func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
10569                 }
10570                 break;
10571
10572               case 'x':
10573                 if (ifthen_next_state)
10574                   func (stream, "\t; unpredictable branch in IT block\n");
10575                 break;
10576
10577               case 'X':
10578                 if (ifthen_state)
10579                   func (stream, "\t; unpredictable <IT:%s>",
10580                         arm_conditional[IFTHEN_COND]);
10581                 break;
10582
10583               case 'S':
10584                 {
10585                   long reg;
10586
10587                   reg = (given >> 3) & 0x7;
10588                   if (given & (1 << 6))
10589                     reg += 8;
10590
10591                   func (stream, "%s", arm_regnames[reg]);
10592                 }
10593                 break;
10594
10595               case 'D':
10596                 {
10597                   long reg;
10598
10599                   reg = given & 0x7;
10600                   if (given & (1 << 7))
10601                     reg += 8;
10602
10603                   func (stream, "%s", arm_regnames[reg]);
10604                 }
10605                 break;
10606
10607               case 'N':
10608                 if (given & (1 << 8))
10609                   domasklr = 1;
10610                 /* Fall through.  */
10611               case 'O':
10612                 if (*c == 'O' && (given & (1 << 8)))
10613                   domaskpc = 1;
10614                 /* Fall through.  */
10615               case 'M':
10616                 {
10617                   int started = 0;
10618                   int reg;
10619
10620                   func (stream, "{");
10621
10622                   /* It would be nice if we could spot
10623                      ranges, and generate the rS-rE format: */
10624                   for (reg = 0; (reg < 8); reg++)
10625                     if ((given & (1 << reg)) != 0)
10626                       {
10627                         if (started)
10628                           func (stream, ", ");
10629                         started = 1;
10630                         func (stream, "%s", arm_regnames[reg]);
10631                       }
10632
10633                   if (domasklr)
10634                     {
10635                       if (started)
10636                         func (stream, ", ");
10637                       started = 1;
10638                       func (stream, "%s", arm_regnames[14] /* "lr" */);
10639                     }
10640
10641                   if (domaskpc)
10642                     {
10643                       if (started)
10644                         func (stream, ", ");
10645                       func (stream, "%s", arm_regnames[15] /* "pc" */);
10646                     }
10647
10648                   func (stream, "}");
10649                 }
10650                 break;
10651
10652               case 'W':
10653                 /* Print writeback indicator for a LDMIA.  We are doing a
10654                    writeback if the base register is not in the register
10655                    mask.  */
10656                 if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
10657                   func (stream, "!");
10658                 break;
10659
10660               case 'b':
10661                 /* Print ARM V6T2 CZB address: pc+4+6 bits.  */
10662                 {
10663                   bfd_vma address = (pc + 4
10664                                      + ((given & 0x00f8) >> 2)
10665                                      + ((given & 0x0200) >> 3));
10666                   info->print_address_func (address, info);
10667
10668                   /* Fill in instruction information.  */
10669                   info->insn_info_valid = 1;
10670                   info->insn_type = dis_branch;
10671                   info->target = address;
10672                 }
10673                 break;
10674
10675               case 's':
10676                 /* Right shift immediate -- bits 6..10; 1-31 print
10677                    as themselves, 0 prints as 32.  */
10678                 {
10679                   long imm = (given & 0x07c0) >> 6;
10680                   if (imm == 0)
10681                     imm = 32;
10682                   func (stream, "#%ld", imm);
10683                 }
10684                 break;
10685
10686               case '0': case '1': case '2': case '3': case '4':
10687               case '5': case '6': case '7': case '8': case '9':
10688                 {
10689                   int bitstart = *c++ - '0';
10690                   int bitend = 0;
10691
10692                   while (*c >= '0' && *c <= '9')
10693                     bitstart = (bitstart * 10) + *c++ - '0';
10694
10695                   switch (*c)
10696                     {
10697                     case '-':
10698                       {
10699                         bfd_vma reg;
10700
10701                         c++;
10702                         while (*c >= '0' && *c <= '9')
10703                           bitend = (bitend * 10) + *c++ - '0';
10704                         if (!bitend)
10705                           abort ();
10706                         reg = given >> bitstart;
10707                         reg &= (2 << (bitend - bitstart)) - 1;
10708
10709                         switch (*c)
10710                           {
10711                           case 'r':
10712                             func (stream, "%s", arm_regnames[reg]);
10713                             break;
10714
10715                           case 'd':
10716                             func (stream, "%ld", (long) reg);
10717                             value_in_comment = reg;
10718                             break;
10719
10720                           case 'H':
10721                             func (stream, "%ld", (long) (reg << 1));
10722                             value_in_comment = reg << 1;
10723                             break;
10724
10725                           case 'W':
10726                             func (stream, "%ld", (long) (reg << 2));
10727                             value_in_comment = reg << 2;
10728                             break;
10729
10730                           case 'a':
10731                             /* PC-relative address -- the bottom two
10732                                bits of the address are dropped
10733                                before the calculation.  */
10734                             info->print_address_func
10735                               (((pc + 4) & ~3) + (reg << 2), info);
10736                             value_in_comment = 0;
10737                             break;
10738
10739                           case 'x':
10740                             func (stream, "0x%04lx", (long) reg);
10741                             break;
10742
10743                           case 'B':
10744                             reg = ((reg ^ (1 << bitend)) - (1 << bitend));
10745                             bfd_vma target = reg * 2 + pc + 4;
10746                             info->print_address_func (target, info);
10747                             value_in_comment = 0;
10748
10749                             /* Fill in instruction information.  */
10750                             info->insn_info_valid = 1;
10751                             info->insn_type = dis_branch;
10752                             info->target = target;
10753                             break;
10754
10755                           case 'c':
10756                             func (stream, "%s", arm_conditional [reg]);
10757                             break;
10758
10759                           default:
10760                             abort ();
10761                           }
10762                       }
10763                       break;
10764
10765                     case '\'':
10766                       c++;
10767                       if ((given & (1 << bitstart)) != 0)
10768                         func (stream, "%c", *c);
10769                       break;
10770
10771                     case '?':
10772                       ++c;
10773                       if ((given & (1 << bitstart)) != 0)
10774                         func (stream, "%c", *c++);
10775                       else
10776                         func (stream, "%c", *++c);
10777                       break;
10778
10779                     default:
10780                       abort ();
10781                     }
10782                 }
10783                 break;
10784
10785               default:
10786                 abort ();
10787               }
10788           }
10789
10790         if (value_in_comment > 32 || value_in_comment < -16)
10791           func (stream, "\t; 0x%lx", value_in_comment);
10792         return;
10793       }
10794
10795   /* No match.  */
10796   func (stream, UNKNOWN_INSTRUCTION_16BIT, (unsigned)given);
10797   return;
10798 }
10799
10800 /* Return the name of an V7M special register.  */
10801
10802 static const char *
10803 psr_name (int regno)
10804 {
10805   switch (regno)
10806     {
10807     case 0x0: return "APSR";
10808     case 0x1: return "IAPSR";
10809     case 0x2: return "EAPSR";
10810     case 0x3: return "PSR";
10811     case 0x5: return "IPSR";
10812     case 0x6: return "EPSR";
10813     case 0x7: return "IEPSR";
10814     case 0x8: return "MSP";
10815     case 0x9: return "PSP";
10816     case 0xa: return "MSPLIM";
10817     case 0xb: return "PSPLIM";
10818     case 0x10: return "PRIMASK";
10819     case 0x11: return "BASEPRI";
10820     case 0x12: return "BASEPRI_MAX";
10821     case 0x13: return "FAULTMASK";
10822     case 0x14: return "CONTROL";
10823     case 0x88: return "MSP_NS";
10824     case 0x89: return "PSP_NS";
10825     case 0x8a: return "MSPLIM_NS";
10826     case 0x8b: return "PSPLIM_NS";
10827     case 0x90: return "PRIMASK_NS";
10828     case 0x91: return "BASEPRI_NS";
10829     case 0x93: return "FAULTMASK_NS";
10830     case 0x94: return "CONTROL_NS";
10831     case 0x98: return "SP_NS";
10832     default: return "<unknown>";
10833     }
10834 }
10835
10836 /* Print one 32-bit Thumb instruction from PC on INFO->STREAM.  */
10837
10838 static void
10839 print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
10840 {
10841   const struct opcode32 *insn;
10842   void *stream = info->stream;
10843   fprintf_ftype func = info->fprintf_func;
10844   bool is_mve = is_mve_architecture (info);
10845
10846   if (print_insn_coprocessor (pc, info, given, true))
10847     return;
10848
10849   if (!is_mve && print_insn_neon (info, given, true))
10850     return;
10851
10852   if (is_mve && print_insn_mve (info, given))
10853     return;
10854
10855   if (print_insn_cde (info, given, true))
10856     return;
10857
10858   if (print_insn_generic_coprocessor (pc, info, given, true))
10859     return;
10860
10861   for (insn = thumb32_opcodes; insn->assembler; insn++)
10862     if ((given & insn->mask) == insn->value)
10863       {
10864         bool is_clrm = false;
10865         bool is_unpredictable = false;
10866         signed long value_in_comment = 0;
10867         const char *c = insn->assembler;
10868
10869         for (; *c; c++)
10870           {
10871             if (*c != '%')
10872               {
10873                 func (stream, "%c", *c);
10874                 continue;
10875               }
10876
10877             switch (*++c)
10878               {
10879               case '%':
10880                 func (stream, "%%");
10881                 break;
10882
10883               case 'c':
10884                 if (ifthen_state)
10885                   func (stream, "%s", arm_conditional[IFTHEN_COND]);
10886                 break;
10887
10888               case 'x':
10889                 if (ifthen_next_state)
10890                   func (stream, "\t; unpredictable branch in IT block\n");
10891                 break;
10892
10893               case 'X':
10894                 if (ifthen_state)
10895                   func (stream, "\t; unpredictable <IT:%s>",
10896                         arm_conditional[IFTHEN_COND]);
10897                 break;
10898
10899               case 'I':
10900                 {
10901                   unsigned int imm12 = 0;
10902
10903                   imm12 |= (given & 0x000000ffu);
10904                   imm12 |= (given & 0x00007000u) >> 4;
10905                   imm12 |= (given & 0x04000000u) >> 15;
10906                   func (stream, "#%u", imm12);
10907                   value_in_comment = imm12;
10908                 }
10909                 break;
10910
10911               case 'M':
10912                 {
10913                   unsigned int bits = 0, imm, imm8, mod;
10914
10915                   bits |= (given & 0x000000ffu);
10916                   bits |= (given & 0x00007000u) >> 4;
10917                   bits |= (given & 0x04000000u) >> 15;
10918                   imm8 = (bits & 0x0ff);
10919                   mod = (bits & 0xf00) >> 8;
10920                   switch (mod)
10921                     {
10922                     case 0: imm = imm8; break;
10923                     case 1: imm = ((imm8 << 16) | imm8); break;
10924                     case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
10925                     case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
10926                     default:
10927                       mod  = (bits & 0xf80) >> 7;
10928                       imm8 = (bits & 0x07f) | 0x80;
10929                       imm  = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
10930                     }
10931                   func (stream, "#%u", imm);
10932                   value_in_comment = imm;
10933                 }
10934                 break;
10935
10936               case 'J':
10937                 {
10938                   unsigned int imm = 0;
10939
10940                   imm |= (given & 0x000000ffu);
10941                   imm |= (given & 0x00007000u) >> 4;
10942                   imm |= (given & 0x04000000u) >> 15;
10943                   imm |= (given & 0x000f0000u) >> 4;
10944                   func (stream, "#%u", imm);
10945                   value_in_comment = imm;
10946                 }
10947                 break;
10948
10949               case 'K':
10950                 {
10951                   unsigned int imm = 0;
10952
10953                   imm |= (given & 0x000f0000u) >> 16;
10954                   imm |= (given & 0x00000ff0u) >> 0;
10955                   imm |= (given & 0x0000000fu) << 12;
10956                   func (stream, "#%u", imm);
10957                   value_in_comment = imm;
10958                 }
10959                 break;
10960
10961               case 'H':
10962                 {
10963                   unsigned int imm = 0;
10964
10965                   imm |= (given & 0x000f0000u) >> 4;
10966                   imm |= (given & 0x00000fffu) >> 0;
10967                   func (stream, "#%u", imm);
10968                   value_in_comment = imm;
10969                 }
10970                 break;
10971
10972               case 'V':
10973                 {
10974                   unsigned int imm = 0;
10975
10976                   imm |= (given & 0x00000fffu);
10977                   imm |= (given & 0x000f0000u) >> 4;
10978                   func (stream, "#%u", imm);
10979                   value_in_comment = imm;
10980                 }
10981                 break;
10982
10983               case 'S':
10984                 {
10985                   unsigned int reg = (given & 0x0000000fu);
10986                   unsigned int stp = (given & 0x00000030u) >> 4;
10987                   unsigned int imm = 0;
10988                   imm |= (given & 0x000000c0u) >> 6;
10989                   imm |= (given & 0x00007000u) >> 10;
10990
10991                   func (stream, "%s", arm_regnames[reg]);
10992                   switch (stp)
10993                     {
10994                     case 0:
10995                       if (imm > 0)
10996                         func (stream, ", lsl #%u", imm);
10997                       break;
10998
10999                     case 1:
11000                       if (imm == 0)
11001                         imm = 32;
11002                       func (stream, ", lsr #%u", imm);
11003                       break;
11004
11005                     case 2:
11006                       if (imm == 0)
11007                         imm = 32;
11008                       func (stream, ", asr #%u", imm);
11009                       break;
11010
11011                     case 3:
11012                       if (imm == 0)
11013                         func (stream, ", rrx");
11014                       else
11015                         func (stream, ", ror #%u", imm);
11016                     }
11017                 }
11018                 break;
11019
11020               case 'a':
11021                 {
11022                   unsigned int Rn  = (given & 0x000f0000) >> 16;
11023                   unsigned int U   = ! NEGATIVE_BIT_SET;
11024                   unsigned int op  = (given & 0x00000f00) >> 8;
11025                   unsigned int i12 = (given & 0x00000fff);
11026                   unsigned int i8  = (given & 0x000000ff);
11027                   bool writeback = false, postind = false;
11028                   bfd_vma offset = 0;
11029
11030                   func (stream, "[%s", arm_regnames[Rn]);
11031                   if (U) /* 12-bit positive immediate offset.  */
11032                     {
11033                       offset = i12;
11034                       if (Rn != 15)
11035                         value_in_comment = offset;
11036                     }
11037                   else if (Rn == 15) /* 12-bit negative immediate offset.  */
11038                     offset = - (int) i12;
11039                   else if (op == 0x0) /* Shifted register offset.  */
11040                     {
11041                       unsigned int Rm = (i8 & 0x0f);
11042                       unsigned int sh = (i8 & 0x30) >> 4;
11043
11044                       func (stream, ", %s", arm_regnames[Rm]);
11045                       if (sh)
11046                         func (stream, ", lsl #%u", sh);
11047                       func (stream, "]");
11048                       break;
11049                     }
11050                   else switch (op)
11051                     {
11052                     case 0xE:  /* 8-bit positive immediate offset.  */
11053                       offset = i8;
11054                       break;
11055
11056                     case 0xC:  /* 8-bit negative immediate offset.  */
11057                       offset = -i8;
11058                       break;
11059
11060                     case 0xF:  /* 8-bit + preindex with wb.  */
11061                       offset = i8;
11062                       writeback = true;
11063                       break;
11064
11065                     case 0xD:  /* 8-bit - preindex with wb.  */
11066                       offset = -i8;
11067                       writeback = true;
11068                       break;
11069
11070                     case 0xB:  /* 8-bit + postindex.  */
11071                       offset = i8;
11072                       postind = true;
11073                       break;
11074
11075                     case 0x9:  /* 8-bit - postindex.  */
11076                       offset = -i8;
11077                       postind = true;
11078                       break;
11079
11080                     default:
11081                       func (stream, ", <undefined>]");
11082                       goto skip;
11083                     }
11084
11085                   if (postind)
11086                     func (stream, "], #%d", (int) offset);
11087                   else
11088                     {
11089                       if (offset)
11090                         func (stream, ", #%d", (int) offset);
11091                       func (stream, writeback ? "]!" : "]");
11092                     }
11093
11094                   if (Rn == 15)
11095                     {
11096                       func (stream, "\t; ");
11097                       info->print_address_func (((pc + 4) & ~3) + offset, info);
11098                     }
11099                 }
11100               skip:
11101                 break;
11102
11103               case 'A':
11104                 {
11105                   unsigned int U   = ! NEGATIVE_BIT_SET;
11106                   unsigned int W   = WRITEBACK_BIT_SET;
11107                   unsigned int Rn  = (given & 0x000f0000) >> 16;
11108                   unsigned int off = (given & 0x000000ff);
11109
11110                   func (stream, "[%s", arm_regnames[Rn]);
11111
11112                   if (PRE_BIT_SET)
11113                     {
11114                       if (off || !U)
11115                         {
11116                           func (stream, ", #%c%u", U ? '+' : '-', off * 4);
11117                           value_in_comment = off * 4 * (U ? 1 : -1);
11118                         }
11119                       func (stream, "]");
11120                       if (W)
11121                         func (stream, "!");
11122                     }
11123                   else
11124                     {
11125                       func (stream, "], ");
11126                       if (W)
11127                         {
11128                           func (stream, "#%c%u", U ? '+' : '-', off * 4);
11129                           value_in_comment = off * 4 * (U ? 1 : -1);
11130                         }
11131                       else
11132                         {
11133                           func (stream, "{%u}", off);
11134                           value_in_comment = off;
11135                         }
11136                     }
11137                 }
11138                 break;
11139
11140               case 'w':
11141                 {
11142                   unsigned int Sbit = (given & 0x01000000) >> 24;
11143                   unsigned int type = (given & 0x00600000) >> 21;
11144
11145                   switch (type)
11146                     {
11147                     case 0: func (stream, Sbit ? "sb" : "b"); break;
11148                     case 1: func (stream, Sbit ? "sh" : "h"); break;
11149                     case 2:
11150                       if (Sbit)
11151                         func (stream, "??");
11152                       break;
11153                     case 3:
11154                       func (stream, "??");
11155                       break;
11156                     }
11157                 }
11158                 break;
11159
11160               case 'n':
11161                 is_clrm = true;
11162                 /* Fall through.  */
11163               case 'm':
11164                 {
11165                   int started = 0;
11166                   int reg;
11167
11168                   func (stream, "{");
11169                   for (reg = 0; reg < 16; reg++)
11170                     if ((given & (1 << reg)) != 0)
11171                       {
11172                         if (started)
11173                           func (stream, ", ");
11174                         started = 1;
11175                         if (is_clrm && reg == 13)
11176                           func (stream, "(invalid: %s)", arm_regnames[reg]);
11177                         else if (is_clrm && reg == 15)
11178                           func (stream, "%s", "APSR");
11179                         else
11180                           func (stream, "%s", arm_regnames[reg]);
11181                       }
11182                   func (stream, "}");
11183                 }
11184                 break;
11185
11186               case 'E':
11187                 {
11188                   unsigned int msb = (given & 0x0000001f);
11189                   unsigned int lsb = 0;
11190
11191                   lsb |= (given & 0x000000c0u) >> 6;
11192                   lsb |= (given & 0x00007000u) >> 10;
11193                   func (stream, "#%u, #%u", lsb, msb - lsb + 1);
11194                 }
11195                 break;
11196
11197               case 'F':
11198                 {
11199                   unsigned int width = (given & 0x0000001f) + 1;
11200                   unsigned int lsb = 0;
11201
11202                   lsb |= (given & 0x000000c0u) >> 6;
11203                   lsb |= (given & 0x00007000u) >> 10;
11204                   func (stream, "#%u, #%u", lsb, width);
11205                 }
11206                 break;
11207
11208               case 'G':
11209                 {
11210                   unsigned int boff = (((given & 0x07800000) >> 23) << 1);
11211                   func (stream, "%x", boff);
11212                 }
11213                 break;
11214
11215               case 'W':
11216                 {
11217                   unsigned int immA = (given & 0x001f0000u) >> 16;
11218                   unsigned int immB = (given & 0x000007feu) >> 1;
11219                   unsigned int immC = (given & 0x00000800u) >> 11;
11220                   bfd_vma offset = 0;
11221
11222                   offset |= immA << 12;
11223                   offset |= immB << 2;
11224                   offset |= immC << 1;
11225                   /* Sign extend.  */
11226                   offset = (offset & 0x10000) ? offset - (1 << 17) : offset;
11227
11228                   info->print_address_func (pc + 4 + offset, info);
11229                 }
11230                 break;
11231
11232               case 'Y':
11233                 {
11234                   unsigned int immA = (given & 0x007f0000u) >> 16;
11235                   unsigned int immB = (given & 0x000007feu) >> 1;
11236                   unsigned int immC = (given & 0x00000800u) >> 11;
11237                   bfd_vma offset = 0;
11238
11239                   offset |= immA << 12;
11240                   offset |= immB << 2;
11241                   offset |= immC << 1;
11242                   /* Sign extend.  */
11243                   offset = (offset & 0x40000) ? offset - (1 << 19) : offset;
11244
11245                   info->print_address_func (pc + 4 + offset, info);
11246                 }
11247                 break;
11248
11249               case 'Z':
11250                 {
11251                   unsigned int immA = (given & 0x00010000u) >> 16;
11252                   unsigned int immB = (given & 0x000007feu) >> 1;
11253                   unsigned int immC = (given & 0x00000800u) >> 11;
11254                   bfd_vma offset = 0;
11255
11256                   offset |= immA << 12;
11257                   offset |= immB << 2;
11258                   offset |= immC << 1;
11259                   /* Sign extend.  */
11260                   offset = (offset & 0x1000) ? offset - (1 << 13) : offset;
11261
11262                   info->print_address_func (pc + 4 + offset, info);
11263
11264                   unsigned int T    = (given & 0x00020000u) >> 17;
11265                   unsigned int endoffset = (((given & 0x07800000) >> 23) << 1);
11266                   unsigned int boffset   = (T == 1) ? 4 : 2;
11267                   func (stream, ", ");
11268                   func (stream, "%x", endoffset + boffset);
11269                 }
11270                 break;
11271
11272               case 'Q':
11273                 {
11274                   unsigned int immh = (given & 0x000007feu) >> 1;
11275                   unsigned int imml = (given & 0x00000800u) >> 11;
11276                   bfd_vma imm32 = 0;
11277
11278                   imm32 |= immh << 2;
11279                   imm32 |= imml << 1;
11280
11281                   info->print_address_func (pc + 4 + imm32, info);
11282                 }
11283                 break;
11284
11285               case 'P':
11286                 {
11287                   unsigned int immh = (given & 0x000007feu) >> 1;
11288                   unsigned int imml = (given & 0x00000800u) >> 11;
11289                   bfd_vma imm32 = 0;
11290
11291                   imm32 |= immh << 2;
11292                   imm32 |= imml << 1;
11293
11294                   info->print_address_func (pc + 4 - imm32, info);
11295                 }
11296                 break;
11297
11298               case 'b':
11299                 {
11300                   unsigned int S = (given & 0x04000000u) >> 26;
11301                   unsigned int J1 = (given & 0x00002000u) >> 13;
11302                   unsigned int J2 = (given & 0x00000800u) >> 11;
11303                   bfd_vma offset = 0;
11304
11305                   offset |= !S << 20;
11306                   offset |= J2 << 19;
11307                   offset |= J1 << 18;
11308                   offset |= (given & 0x003f0000) >> 4;
11309                   offset |= (given & 0x000007ff) << 1;
11310                   offset -= (1 << 20);
11311
11312                   bfd_vma target = pc + 4 + offset;
11313                   info->print_address_func (target, info);
11314
11315                   /* Fill in instruction information.  */
11316                   info->insn_info_valid = 1;
11317                   info->insn_type = dis_branch;
11318                   info->target = target;
11319                 }
11320                 break;
11321
11322               case 'B':
11323                 {
11324                   unsigned int S = (given & 0x04000000u) >> 26;
11325                   unsigned int I1 = (given & 0x00002000u) >> 13;
11326                   unsigned int I2 = (given & 0x00000800u) >> 11;
11327                   bfd_vma offset = 0;
11328
11329                   offset |= !S << 24;
11330                   offset |= !(I1 ^ S) << 23;
11331                   offset |= !(I2 ^ S) << 22;
11332                   offset |= (given & 0x03ff0000u) >> 4;
11333                   offset |= (given & 0x000007ffu) << 1;
11334                   offset -= (1 << 24);
11335                   offset += pc + 4;
11336
11337                   /* BLX target addresses are always word aligned.  */
11338                   if ((given & 0x00001000u) == 0)
11339                       offset &= ~2u;
11340
11341                   info->print_address_func (offset, info);
11342
11343                   /* Fill in instruction information.  */
11344                   info->insn_info_valid = 1;
11345                   info->insn_type = dis_branch;
11346                   info->target = offset;
11347                 }
11348                 break;
11349
11350               case 's':
11351                 {
11352                   unsigned int shift = 0;
11353
11354                   shift |= (given & 0x000000c0u) >> 6;
11355                   shift |= (given & 0x00007000u) >> 10;
11356                   if (WRITEBACK_BIT_SET)
11357                     func (stream, ", asr #%u", shift);
11358                   else if (shift)
11359                     func (stream, ", lsl #%u", shift);
11360                   /* else print nothing - lsl #0 */
11361                 }
11362                 break;
11363
11364               case 'R':
11365                 {
11366                   unsigned int rot = (given & 0x00000030) >> 4;
11367
11368                   if (rot)
11369                     func (stream, ", ror #%u", rot * 8);
11370                 }
11371                 break;
11372
11373               case 'U':
11374                 if ((given & 0xf0) == 0x60)
11375                   {
11376                     switch (given & 0xf)
11377                       {
11378                         case 0xf: func (stream, "sy"); break;
11379                         default:
11380                           func (stream, "#%d", (int) given & 0xf);
11381                               break;
11382                       }
11383                   }
11384                 else
11385                   {
11386                     const char * opt = data_barrier_option (given & 0xf);
11387                     if (opt != NULL)
11388                       func (stream, "%s", opt);
11389                     else
11390                       func (stream, "#%d", (int) given & 0xf);
11391                    }
11392                 break;
11393
11394               case 'C':
11395                 if ((given & 0xff) == 0)
11396                   {
11397                     func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
11398                     if (given & 0x800)
11399                       func (stream, "f");
11400                     if (given & 0x400)
11401                       func (stream, "s");
11402                     if (given & 0x200)
11403                       func (stream, "x");
11404                     if (given & 0x100)
11405                       func (stream, "c");
11406                   }
11407                 else if ((given & 0x20) == 0x20)
11408                   {
11409                     char const* name;
11410                     unsigned sysm = (given & 0xf00) >> 8;
11411
11412                     sysm |= (given & 0x30);
11413                     sysm |= (given & 0x00100000) >> 14;
11414                     name = banked_regname (sysm);
11415
11416                     if (name != NULL)
11417                       func (stream, "%s", name);
11418                     else
11419                       func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
11420                   }
11421                 else
11422                   {
11423                     func (stream, "%s", psr_name (given & 0xff));
11424                   }
11425                 break;
11426
11427               case 'D':
11428                 if (((given & 0xff) == 0)
11429                     || ((given & 0x20) == 0x20))
11430                   {
11431                     char const* name;
11432                     unsigned sm = (given & 0xf0000) >> 16;
11433
11434                     sm |= (given & 0x30);
11435                     sm |= (given & 0x00100000) >> 14;
11436                     name = banked_regname (sm);
11437
11438                     if (name != NULL)
11439                       func (stream, "%s", name);
11440                     else
11441                       func (stream, "(UNDEF: %lu)", (unsigned long) sm);
11442                   }
11443                 else
11444                   func (stream, "%s", psr_name (given & 0xff));
11445                 break;
11446
11447               case '0': case '1': case '2': case '3': case '4':
11448               case '5': case '6': case '7': case '8': case '9':
11449                 {
11450                   int width;
11451                   unsigned long val;
11452
11453                   c = arm_decode_bitfield (c, given, &val, &width);
11454
11455                   switch (*c)
11456                     {
11457                     case 's':
11458                       if (val <= 3)
11459                         func (stream, "%s", mve_vec_sizename[val]);
11460                       else
11461                         func (stream, "<undef size>");
11462                       break;
11463
11464                     case 'd':
11465                       func (stream, "%lu", val);
11466                       value_in_comment = val;
11467                       break;
11468
11469                     case 'D':
11470                       func (stream, "%lu", val + 1);
11471                       value_in_comment = val + 1;
11472                       break;
11473
11474                     case 'W':
11475                       func (stream, "%lu", val * 4);
11476                       value_in_comment = val * 4;
11477                       break;
11478
11479                     case 'S':
11480                       if (val == 13)
11481                         is_unpredictable = true;
11482                       /* Fall through.  */
11483                     case 'R':
11484                       if (val == 15)
11485                         is_unpredictable = true;
11486                       /* Fall through.  */
11487                     case 'r':
11488                       func (stream, "%s", arm_regnames[val]);
11489                       break;
11490
11491                     case 'c':
11492                       func (stream, "%s", arm_conditional[val]);
11493                       break;
11494
11495                     case '\'':
11496                       c++;
11497                       if (val == ((1ul << width) - 1))
11498                         func (stream, "%c", *c);
11499                       break;
11500
11501                     case '`':
11502                       c++;
11503                       if (val == 0)
11504                         func (stream, "%c", *c);
11505                       break;
11506
11507                     case '?':
11508                       func (stream, "%c", c[(1 << width) - (int) val]);
11509                       c += 1 << width;
11510                       break;
11511
11512                     case 'x':
11513                       func (stream, "0x%lx", val & 0xffffffffUL);
11514                       break;
11515
11516                     default:
11517                       abort ();
11518                     }
11519                 }
11520                 break;
11521
11522               case 'L':
11523                 /* PR binutils/12534
11524                    If we have a PC relative offset in an LDRD or STRD
11525                    instructions then display the decoded address.  */
11526                 if (((given >> 16) & 0xf) == 0xf)
11527                   {
11528                     bfd_vma offset = (given & 0xff) * 4;
11529
11530                     if ((given & (1 << 23)) == 0)
11531                       offset = - offset;
11532                     func (stream, "\t; ");
11533                     info->print_address_func ((pc & ~3) + 4 + offset, info);
11534                   }
11535                 break;
11536
11537               default:
11538                 abort ();
11539               }
11540           }
11541
11542         if (value_in_comment > 32 || value_in_comment < -16)
11543           func (stream, "\t; 0x%lx", value_in_comment);
11544
11545         if (is_unpredictable)
11546           func (stream, UNPREDICTABLE_INSTRUCTION);
11547
11548         return;
11549       }
11550
11551   /* No match.  */
11552   func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
11553   return;
11554 }
11555
11556 /* Print data bytes on INFO->STREAM.  */
11557
11558 static void
11559 print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
11560                  struct disassemble_info *info,
11561                  long given)
11562 {
11563   switch (info->bytes_per_chunk)
11564     {
11565     case 1:
11566       info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
11567       break;
11568     case 2:
11569       info->fprintf_func (info->stream, ".short\t0x%04lx", given);
11570       break;
11571     case 4:
11572       info->fprintf_func (info->stream, ".word\t0x%08lx", given);
11573       break;
11574     default:
11575       abort ();
11576     }
11577 }
11578
11579 /* Disallow mapping symbols ($a, $b, $d, $t etc) from
11580    being displayed in symbol relative addresses.
11581
11582    Also disallow private symbol, with __tagsym$$ prefix,
11583    from ARM RVCT toolchain being displayed.  */
11584
11585 bool
11586 arm_symbol_is_valid (asymbol * sym,
11587                      struct disassemble_info * info ATTRIBUTE_UNUSED)
11588 {
11589   const char * name;
11590
11591   if (sym == NULL)
11592     return false;
11593
11594   name = bfd_asymbol_name (sym);
11595
11596   return (name && *name != '$' && strncmp (name, "__tagsym$$", 10));
11597 }
11598
11599 /* Parse the string of disassembler options.  */
11600
11601 static void
11602 parse_arm_disassembler_options (const char *options)
11603 {
11604   const char *opt;
11605
11606   FOR_EACH_DISASSEMBLER_OPTION (opt, options)
11607     {
11608       if (startswith (opt, "reg-names-"))
11609         {
11610           unsigned int i;
11611           for (i = 0; i < NUM_ARM_OPTIONS; i++)
11612             if (disassembler_options_cmp (opt, regnames[i].name) == 0)
11613               {
11614                 regname_selected = i;
11615                 break;
11616               }
11617
11618           if (i >= NUM_ARM_OPTIONS)
11619             /* xgettext: c-format */
11620             opcodes_error_handler (_("unrecognised register name set: %s"),
11621                                    opt);
11622         }
11623       else if (startswith (opt, "force-thumb"))
11624         force_thumb = 1;
11625       else if (startswith (opt, "no-force-thumb"))
11626         force_thumb = 0;
11627       else if (startswith (opt, "coproc"))
11628         {
11629           const char *procptr = opt + sizeof ("coproc") - 1;
11630           char *endptr;
11631           uint8_t coproc_number = strtol (procptr, &endptr, 10);
11632           if (endptr != procptr + 1 || coproc_number > 7)
11633             {
11634               opcodes_error_handler (_("cde coprocessor not between 0-7: %s"),
11635                                      opt);
11636               continue;
11637             }
11638           if (*endptr != '=')
11639             {
11640               opcodes_error_handler (_("coproc must have an argument: %s"),
11641                                      opt);
11642               continue;
11643             }
11644           endptr += 1;
11645           if (startswith (endptr, "generic"))
11646             cde_coprocs &= ~(1 << coproc_number);
11647           else if (startswith (endptr, "cde")
11648                    || startswith (endptr, "CDE"))
11649             cde_coprocs |= (1 << coproc_number);
11650           else
11651             {
11652               opcodes_error_handler (
11653                   _("coprocN argument takes options \"generic\","
11654                     " \"cde\", or \"CDE\": %s"), opt);
11655             }
11656         }
11657       else
11658         /* xgettext: c-format */
11659         opcodes_error_handler (_("unrecognised disassembler option: %s"), opt);
11660     }
11661
11662   return;
11663 }
11664
11665 static bool
11666 mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
11667                          enum map_type *map_symbol);
11668
11669 /* Search back through the insn stream to determine if this instruction is
11670    conditionally executed.  */
11671
11672 static void
11673 find_ifthen_state (bfd_vma pc,
11674                    struct disassemble_info *info,
11675                    bool little)
11676 {
11677   unsigned char b[2];
11678   unsigned int insn;
11679   int status;
11680   /* COUNT is twice the number of instructions seen.  It will be odd if we
11681      just crossed an instruction boundary.  */
11682   int count;
11683   int it_count;
11684   unsigned int seen_it;
11685   bfd_vma addr;
11686
11687   ifthen_address = pc;
11688   ifthen_state = 0;
11689
11690   addr = pc;
11691   count = 1;
11692   it_count = 0;
11693   seen_it = 0;
11694   /* Scan backwards looking for IT instructions, keeping track of where
11695      instruction boundaries are.  We don't know if something is actually an
11696      IT instruction until we find a definite instruction boundary.  */
11697   for (;;)
11698     {
11699       if (addr == 0 || info->symbol_at_address_func (addr, info))
11700         {
11701           /* A symbol must be on an instruction boundary, and will not
11702              be within an IT block.  */
11703           if (seen_it && (count & 1))
11704             break;
11705
11706           return;
11707         }
11708       addr -= 2;
11709       status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
11710       if (status)
11711         return;
11712
11713       if (little)
11714         insn = (b[0]) | (b[1] << 8);
11715       else
11716         insn = (b[1]) | (b[0] << 8);
11717       if (seen_it)
11718         {
11719           if ((insn & 0xf800) < 0xe800)
11720             {
11721               /* Addr + 2 is an instruction boundary.  See if this matches
11722                  the expected boundary based on the position of the last
11723                  IT candidate.  */
11724               if (count & 1)
11725                 break;
11726               seen_it = 0;
11727             }
11728         }
11729       if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
11730         {
11731           enum map_type type = MAP_ARM;
11732           bool found = mapping_symbol_for_insn (addr, info, &type);
11733
11734           if (!found || (found && type == MAP_THUMB))
11735             {
11736               /* This could be an IT instruction.  */
11737               seen_it = insn;
11738               it_count = count >> 1;
11739             }
11740         }
11741       if ((insn & 0xf800) >= 0xe800)
11742         count++;
11743       else
11744         count = (count + 2) | 1;
11745       /* IT blocks contain at most 4 instructions.  */
11746       if (count >= 8 && !seen_it)
11747         return;
11748     }
11749   /* We found an IT instruction.  */
11750   ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
11751   if ((ifthen_state & 0xf) == 0)
11752     ifthen_state = 0;
11753 }
11754
11755 /* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
11756    mapping symbol.  */
11757
11758 static int
11759 is_mapping_symbol (struct disassemble_info *info, int n,
11760                    enum map_type *map_type)
11761 {
11762   const char *name;
11763
11764   name = bfd_asymbol_name (info->symtab[n]);
11765   if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
11766       && (name[2] == 0 || name[2] == '.'))
11767     {
11768       *map_type = ((name[1] == 'a') ? MAP_ARM
11769                    : (name[1] == 't') ? MAP_THUMB
11770                    : MAP_DATA);
11771       return true;
11772     }
11773
11774   return false;
11775 }
11776
11777 /* Try to infer the code type (ARM or Thumb) from a mapping symbol.
11778    Returns nonzero if *MAP_TYPE was set.  */
11779
11780 static int
11781 get_map_sym_type (struct disassemble_info *info,
11782                   int n,
11783                   enum map_type *map_type)
11784 {
11785   /* If the symbol is in a different section, ignore it.  */
11786   if (info->section != NULL && info->section != info->symtab[n]->section)
11787     return false;
11788
11789   return is_mapping_symbol (info, n, map_type);
11790 }
11791
11792 /* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
11793    Returns nonzero if *MAP_TYPE was set.  */
11794
11795 static int
11796 get_sym_code_type (struct disassemble_info *info,
11797                    int n,
11798                    enum map_type *map_type)
11799 {
11800   elf_symbol_type *es;
11801   unsigned int type;
11802
11803   /* If the symbol is in a different section, ignore it.  */
11804   if (info->section != NULL && info->section != info->symtab[n]->section)
11805     return false;
11806
11807   es = *(elf_symbol_type **)(info->symtab + n);
11808   type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
11809
11810   /* If the symbol has function type then use that.  */
11811   if (type == STT_FUNC || type == STT_GNU_IFUNC)
11812     {
11813       if (ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
11814           == ST_BRANCH_TO_THUMB)
11815         *map_type = MAP_THUMB;
11816       else
11817         *map_type = MAP_ARM;
11818       return true;
11819     }
11820
11821   return false;
11822 }
11823
11824 /* Search the mapping symbol state for instruction at pc.  This is only
11825    applicable for elf target.
11826
11827    There is an assumption Here, info->private_data contains the correct AND
11828    up-to-date information about current scan process.  The information will be
11829    used to speed this search process.
11830
11831    Return TRUE if the mapping state can be determined, and map_symbol
11832    will be updated accordingly.  Otherwise, return FALSE.  */
11833
11834 static bool
11835 mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
11836                          enum map_type *map_symbol)
11837 {
11838   bfd_vma addr, section_vma = 0;
11839   int n, last_sym = -1;
11840   bool found = false;
11841   bool can_use_search_opt_p = false;
11842
11843   /* Default to DATA.  A text section is required by the ABI to contain an
11844      INSN mapping symbol at the start.  A data section has no such
11845      requirement, hence if no mapping symbol is found the section must
11846      contain only data.  This however isn't very useful if the user has
11847      fully stripped the binaries.  If this is the case use the section
11848      attributes to determine the default.  If we have no section default to
11849      INSN as well, as we may be disassembling some raw bytes on a baremetal
11850      HEX file or similar.  */
11851   enum map_type type = MAP_DATA;
11852   if ((info->section && info->section->flags & SEC_CODE) || !info->section)
11853     type = MAP_ARM;
11854   struct arm_private_data *private_data;
11855
11856   if (info->private_data == NULL
11857       || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour)
11858     return false;
11859
11860   private_data = info->private_data;
11861
11862   /* First, look for mapping symbols.  */
11863   if (info->symtab_size != 0)
11864   {
11865     if (pc <= private_data->last_mapping_addr)
11866       private_data->last_mapping_sym = -1;
11867
11868     /* Start scanning at the start of the function, or wherever
11869        we finished last time.  */
11870     n = info->symtab_pos + 1;
11871
11872     /* If the last stop offset is different from the current one it means we
11873        are disassembling a different glob of bytes.  As such the optimization
11874        would not be safe and we should start over.  */
11875     can_use_search_opt_p
11876       = private_data->last_mapping_sym >= 0
11877         && info->stop_offset == private_data->last_stop_offset;
11878
11879     if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
11880       n = private_data->last_mapping_sym;
11881
11882     /* Look down while we haven't passed the location being disassembled.
11883        The reason for this is that there's no defined order between a symbol
11884        and an mapping symbol that may be at the same address.  We may have to
11885        look at least one position ahead.  */
11886     for (; n < info->symtab_size; n++)
11887       {
11888         addr = bfd_asymbol_value (info->symtab[n]);
11889         if (addr > pc)
11890           break;
11891         if (get_map_sym_type (info, n, &type))
11892           {
11893             last_sym = n;
11894             found = true;
11895           }
11896       }
11897
11898     if (!found)
11899       {
11900         n = info->symtab_pos;
11901         if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
11902           n = private_data->last_mapping_sym;
11903
11904         /* No mapping symbol found at this address.  Look backwards
11905            for a preceeding one, but don't go pass the section start
11906            otherwise a data section with no mapping symbol can pick up
11907            a text mapping symbol of a preceeding section.  The documentation
11908            says section can be NULL, in which case we will seek up all the
11909            way to the top.  */
11910         if (info->section)
11911           section_vma = info->section->vma;
11912
11913         for (; n >= 0; n--)
11914           {
11915             addr = bfd_asymbol_value (info->symtab[n]);
11916             if (addr < section_vma)
11917               break;
11918
11919             if (get_map_sym_type (info, n, &type))
11920               {
11921                 last_sym = n;
11922                 found = true;
11923                 break;
11924               }
11925           }
11926       }
11927   }
11928
11929   /* If no mapping symbol was found, try looking up without a mapping
11930      symbol.  This is done by walking up from the current PC to the nearest
11931      symbol.  We don't actually have to loop here since symtab_pos will
11932      contain the nearest symbol already.  */
11933   if (!found)
11934     {
11935       n = info->symtab_pos;
11936       if (n >= 0 && get_sym_code_type (info, n, &type))
11937         {
11938           last_sym = n;
11939           found = true;
11940         }
11941     }
11942
11943   private_data->last_mapping_sym = last_sym;
11944   private_data->last_type = type;
11945   private_data->last_stop_offset = info->stop_offset;
11946
11947   *map_symbol = type;
11948   return found;
11949 }
11950
11951 /* Given a bfd_mach_arm_XXX value, this function fills in the fields
11952    of the supplied arm_feature_set structure with bitmasks indicating
11953    the supported base architectures and coprocessor extensions.
11954
11955    FIXME: This could more efficiently implemented as a constant array,
11956    although it would also be less robust.  */
11957
11958 static void
11959 select_arm_features (unsigned long mach,
11960                      arm_feature_set * features)
11961 {
11962   arm_feature_set arch_fset;
11963   const arm_feature_set fpu_any = FPU_ANY;
11964
11965 #undef ARM_SET_FEATURES
11966 #define ARM_SET_FEATURES(FSET) \
11967   {                                                     \
11968     const arm_feature_set fset = FSET;                  \
11969     arch_fset = fset;                                   \
11970   }
11971
11972   /* When several architecture versions share the same bfd_mach_arm_XXX value
11973      the most featureful is chosen.  */
11974   switch (mach)
11975     {
11976     case bfd_mach_arm_2:         ARM_SET_FEATURES (ARM_ARCH_V2); break;
11977     case bfd_mach_arm_2a:        ARM_SET_FEATURES (ARM_ARCH_V2S); break;
11978     case bfd_mach_arm_3:         ARM_SET_FEATURES (ARM_ARCH_V3); break;
11979     case bfd_mach_arm_3M:        ARM_SET_FEATURES (ARM_ARCH_V3M); break;
11980     case bfd_mach_arm_4:         ARM_SET_FEATURES (ARM_ARCH_V4); break;
11981     case bfd_mach_arm_4T:        ARM_SET_FEATURES (ARM_ARCH_V4T); break;
11982     case bfd_mach_arm_5:         ARM_SET_FEATURES (ARM_ARCH_V5); break;
11983     case bfd_mach_arm_5T:        ARM_SET_FEATURES (ARM_ARCH_V5T); break;
11984     case bfd_mach_arm_5TE:       ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
11985     case bfd_mach_arm_XScale:    ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
11986     case bfd_mach_arm_ep9312:
11987         ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T,
11988                                            ARM_CEXT_MAVERICK | FPU_MAVERICK));
11989        break;
11990     case bfd_mach_arm_iWMMXt:    ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
11991     case bfd_mach_arm_iWMMXt2:   ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
11992     case bfd_mach_arm_5TEJ:      ARM_SET_FEATURES (ARM_ARCH_V5TEJ); break;
11993     case bfd_mach_arm_6:         ARM_SET_FEATURES (ARM_ARCH_V6); break;
11994     case bfd_mach_arm_6KZ:       ARM_SET_FEATURES (ARM_ARCH_V6KZ); break;
11995     case bfd_mach_arm_6T2:       ARM_SET_FEATURES (ARM_ARCH_V6KZT2); break;
11996     case bfd_mach_arm_6K:        ARM_SET_FEATURES (ARM_ARCH_V6K); break;
11997     case bfd_mach_arm_7:         ARM_SET_FEATURES (ARM_ARCH_V7VE); break;
11998     case bfd_mach_arm_6M:        ARM_SET_FEATURES (ARM_ARCH_V6M); break;
11999     case bfd_mach_arm_6SM:       ARM_SET_FEATURES (ARM_ARCH_V6SM); break;
12000     case bfd_mach_arm_7EM:       ARM_SET_FEATURES (ARM_ARCH_V7EM); break;
12001     case bfd_mach_arm_8:
12002         {
12003           /* Add bits for extensions that Armv8.6-A recognizes.  */
12004           arm_feature_set armv8_6_ext_fset
12005             = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST);
12006           ARM_SET_FEATURES (ARM_ARCH_V8_6A);
12007           ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, armv8_6_ext_fset);
12008           break;
12009         }
12010     case bfd_mach_arm_8R:        ARM_SET_FEATURES (ARM_ARCH_V8R); break;
12011     case bfd_mach_arm_8M_BASE:   ARM_SET_FEATURES (ARM_ARCH_V8M_BASE); break;
12012     case bfd_mach_arm_8M_MAIN:   ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN); break;
12013     case bfd_mach_arm_8_1M_MAIN:
12014       ARM_SET_FEATURES (ARM_ARCH_V8_1M_MAIN);
12015       arm_feature_set mve_all
12016         = ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE | ARM_EXT2_MVE_FP);
12017       ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, mve_all);
12018       force_thumb = 1;
12019       break;
12020       /* If the machine type is unknown allow all architecture types and all
12021          extensions, with the exception of MVE as that clashes with NEON.  */
12022     case bfd_mach_arm_unknown:
12023       ARM_SET_FEATURES (ARM_FEATURE (-1,
12024                                      -1 & ~(ARM_EXT2_MVE | ARM_EXT2_MVE_FP),
12025                                      -1));
12026       break;
12027     default:
12028       abort ();
12029     }
12030 #undef ARM_SET_FEATURES
12031
12032   /* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch
12033      and thus on bfd_mach_arm_XXX value.  Therefore for a given
12034      bfd_mach_arm_XXX value all coprocessor feature bits should be allowed.  */
12035   ARM_MERGE_FEATURE_SETS (*features, arch_fset, fpu_any);
12036 }
12037
12038
12039 /* NOTE: There are no checks in these routines that
12040    the relevant number of data bytes exist.  */
12041
12042 static int
12043 print_insn (bfd_vma pc, struct disassemble_info *info, bool little)
12044 {
12045   unsigned char b[4];
12046   unsigned long given;
12047   int status;
12048   int is_thumb = false;
12049   int is_data = false;
12050   int little_code;
12051   unsigned int  size = 4;
12052   void (*printer) (bfd_vma, struct disassemble_info *, long);
12053   bool found = false;
12054   struct arm_private_data *private_data;
12055
12056   /* Clear instruction information field.  */
12057   info->insn_info_valid = 0;
12058   info->branch_delay_insns = 0;
12059   info->data_size = 0;
12060   info->insn_type = dis_noninsn;
12061   info->target = 0;
12062   info->target2 = 0;
12063
12064   if (info->disassembler_options)
12065     {
12066       parse_arm_disassembler_options (info->disassembler_options);
12067
12068       /* To avoid repeated parsing of these options, we remove them here.  */
12069       info->disassembler_options = NULL;
12070     }
12071
12072   /* PR 10288: Control which instructions will be disassembled.  */
12073   if (info->private_data == NULL)
12074     {
12075       static struct arm_private_data private;
12076
12077       if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
12078         /* If the user did not use the -m command line switch then default to
12079            disassembling all types of ARM instruction.
12080
12081            The info->mach value has to be ignored as this will be based on
12082            the default archictecture for the target and/or hints in the notes
12083            section, but it will never be greater than the current largest arm
12084            machine value (iWMMXt2), which is only equivalent to the V5TE
12085            architecture.  ARM architectures have advanced beyond the machine
12086            value encoding, and these newer architectures would be ignored if
12087            the machine value was used.
12088
12089            Ie the -m switch is used to restrict which instructions will be
12090            disassembled.  If it is necessary to use the -m switch to tell
12091            objdump that an ARM binary is being disassembled, eg because the
12092            input is a raw binary file, but it is also desired to disassemble
12093            all ARM instructions then use "-marm".  This will select the
12094            "unknown" arm architecture which is compatible with any ARM
12095            instruction.  */
12096           info->mach = bfd_mach_arm_unknown;
12097
12098       /* Compute the architecture bitmask from the machine number.
12099          Note: This assumes that the machine number will not change
12100          during disassembly....  */
12101       select_arm_features (info->mach, & private.features);
12102
12103       private.last_mapping_sym = -1;
12104       private.last_mapping_addr = 0;
12105       private.last_stop_offset = 0;
12106
12107       info->private_data = & private;
12108     }
12109
12110   private_data = info->private_data;
12111
12112   /* Decide if our code is going to be little-endian, despite what the
12113      function argument might say.  */
12114   little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
12115
12116   /* For ELF, consult the symbol table to determine what kind of code
12117      or data we have.  */
12118   if (info->symtab_size != 0
12119       && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
12120     {
12121       bfd_vma addr;
12122       int n;
12123       int last_sym = -1;
12124       enum map_type type = MAP_ARM;
12125
12126       found = mapping_symbol_for_insn (pc, info, &type);
12127       last_sym = private_data->last_mapping_sym;
12128
12129       is_thumb = (private_data->last_type == MAP_THUMB);
12130       is_data = (private_data->last_type == MAP_DATA);
12131
12132       /* Look a little bit ahead to see if we should print out
12133          two or four bytes of data.  If there's a symbol,
12134          mapping or otherwise, after two bytes then don't
12135          print more.  */
12136       if (is_data)
12137         {
12138           size = 4 - (pc & 3);
12139           for (n = last_sym + 1; n < info->symtab_size; n++)
12140             {
12141               addr = bfd_asymbol_value (info->symtab[n]);
12142               if (addr > pc
12143                   && (info->section == NULL
12144                       || info->section == info->symtab[n]->section))
12145                 {
12146                   if (addr - pc < size)
12147                     size = addr - pc;
12148                   break;
12149                 }
12150             }
12151           /* If the next symbol is after three bytes, we need to
12152              print only part of the data, so that we can use either
12153              .byte or .short.  */
12154           if (size == 3)
12155             size = (pc & 1) ? 1 : 2;
12156         }
12157     }
12158
12159   if (info->symbols != NULL)
12160     {
12161       if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
12162         {
12163           coff_symbol_type * cs;
12164
12165           cs = coffsymbol (*info->symbols);
12166           is_thumb = (   cs->native->u.syment.n_sclass == C_THUMBEXT
12167                       || cs->native->u.syment.n_sclass == C_THUMBSTAT
12168                       || cs->native->u.syment.n_sclass == C_THUMBLABEL
12169                       || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
12170                       || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
12171         }
12172       else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
12173                && !found)
12174         {
12175           /* If no mapping symbol has been found then fall back to the type
12176              of the function symbol.  */
12177           elf_symbol_type *  es;
12178           unsigned int       type;
12179
12180           es = *(elf_symbol_type **)(info->symbols);
12181           type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
12182
12183           is_thumb =
12184             ((ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
12185               == ST_BRANCH_TO_THUMB) || type == STT_ARM_16BIT);
12186         }
12187       else if (bfd_asymbol_flavour (*info->symbols)
12188                == bfd_target_mach_o_flavour)
12189         {
12190           bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols;
12191
12192           is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF);
12193         }
12194     }
12195
12196   if (force_thumb)
12197     is_thumb = true;
12198
12199   if (is_data)
12200     info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
12201   else
12202     info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
12203
12204   info->bytes_per_line = 4;
12205
12206   /* PR 10263: Disassemble data if requested to do so by the user.  */
12207   if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
12208     {
12209       int i;
12210
12211       /* Size was already set above.  */
12212       info->bytes_per_chunk = size;
12213       printer = print_insn_data;
12214
12215       status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
12216       given = 0;
12217       if (little)
12218         for (i = size - 1; i >= 0; i--)
12219           given = b[i] | (given << 8);
12220       else
12221         for (i = 0; i < (int) size; i++)
12222           given = b[i] | (given << 8);
12223     }
12224   else if (!is_thumb)
12225     {
12226       /* In ARM mode endianness is a straightforward issue: the instruction
12227          is four bytes long and is either ordered 0123 or 3210.  */
12228       printer = print_insn_arm;
12229       info->bytes_per_chunk = 4;
12230       size = 4;
12231
12232       status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
12233       if (little_code)
12234         given = (b[0]) | (b[1] << 8) | (b[2] << 16) | ((unsigned) b[3] << 24);
12235       else
12236         given = (b[3]) | (b[2] << 8) | (b[1] << 16) | ((unsigned) b[0] << 24);
12237     }
12238   else
12239     {
12240       /* In Thumb mode we have the additional wrinkle of two
12241          instruction lengths.  Fortunately, the bits that determine
12242          the length of the current instruction are always to be found
12243          in the first two bytes.  */
12244       printer = print_insn_thumb16;
12245       info->bytes_per_chunk = 2;
12246       size = 2;
12247
12248       status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
12249       if (little_code)
12250         given = (b[0]) | (b[1] << 8);
12251       else
12252         given = (b[1]) | (b[0] << 8);
12253
12254       if (!status)
12255         {
12256           /* These bit patterns signal a four-byte Thumb
12257              instruction.  */
12258           if ((given & 0xF800) == 0xF800
12259               || (given & 0xF800) == 0xF000
12260               || (given & 0xF800) == 0xE800)
12261             {
12262               status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
12263               if (little_code)
12264                 given = (b[0]) | (b[1] << 8) | (given << 16);
12265               else
12266                 given = (b[1]) | (b[0] << 8) | (given << 16);
12267
12268               printer = print_insn_thumb32;
12269               size = 4;
12270             }
12271         }
12272
12273       if (ifthen_address != pc)
12274         find_ifthen_state (pc, info, little_code);
12275
12276       if (ifthen_state)
12277         {
12278           if ((ifthen_state & 0xf) == 0x8)
12279             ifthen_next_state = 0;
12280           else
12281             ifthen_next_state = (ifthen_state & 0xe0)
12282                                 | ((ifthen_state & 0xf) << 1);
12283         }
12284     }
12285
12286   if (status)
12287     {
12288       info->memory_error_func (status, pc, info);
12289       return -1;
12290     }
12291   if (info->flags & INSN_HAS_RELOC)
12292     /* If the instruction has a reloc associated with it, then
12293        the offset field in the instruction will actually be the
12294        addend for the reloc.  (We are using REL type relocs).
12295        In such cases, we can ignore the pc when computing
12296        addresses, since the addend is not currently pc-relative.  */
12297     pc = 0;
12298
12299   printer (pc, info, given);
12300
12301   if (is_thumb)
12302     {
12303       ifthen_state = ifthen_next_state;
12304       ifthen_address += size;
12305     }
12306   return size;
12307 }
12308
12309 int
12310 print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
12311 {
12312   /* Detect BE8-ness and record it in the disassembler info.  */
12313   if (info->flavour == bfd_target_elf_flavour
12314       && info->section != NULL
12315       && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
12316     info->endian_code = BFD_ENDIAN_LITTLE;
12317
12318   return print_insn (pc, info, false);
12319 }
12320
12321 int
12322 print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
12323 {
12324   return print_insn (pc, info, true);
12325 }
12326
12327 const disasm_options_and_args_t *
12328 disassembler_options_arm (void)
12329 {
12330   static disasm_options_and_args_t *opts_and_args;
12331
12332   if (opts_and_args == NULL)
12333     {
12334       disasm_options_t *opts;
12335       unsigned int i;
12336
12337       opts_and_args = XNEW (disasm_options_and_args_t);
12338       opts_and_args->args = NULL;
12339
12340       opts = &opts_and_args->options;
12341       opts->name = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
12342       opts->description = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
12343       opts->arg = NULL;
12344       for (i = 0; i < NUM_ARM_OPTIONS; i++)
12345         {
12346           opts->name[i] = regnames[i].name;
12347           if (regnames[i].description != NULL)
12348             opts->description[i] = _(regnames[i].description);
12349           else
12350             opts->description[i] = NULL;
12351         }
12352       /* The array we return must be NULL terminated.  */
12353       opts->name[i] = NULL;
12354       opts->description[i] = NULL;
12355     }
12356
12357   return opts_and_args;
12358 }
12359
12360 void
12361 print_arm_disassembler_options (FILE *stream)
12362 {
12363   unsigned int i, max_len = 0;
12364   fprintf (stream, _("\n\
12365 The following ARM specific disassembler options are supported for use with\n\
12366 the -M switch:\n"));
12367
12368   for (i = 0; i < NUM_ARM_OPTIONS; i++)
12369     {
12370       unsigned int len = strlen (regnames[i].name);
12371       if (max_len < len)
12372         max_len = len;
12373     }
12374
12375   for (i = 0, max_len++; i < NUM_ARM_OPTIONS; i++)
12376     fprintf (stream, "  %s%*c %s\n",
12377              regnames[i].name,
12378              (int)(max_len - strlen (regnames[i].name)), ' ',
12379              _(regnames[i].description));
12380 }