opcodes/arm-dis.c

   1 /* Instruction printing code for the ARM
   2    Copyright (C) 1994-2019 Free Software Foundation, Inc.
   3    Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
   4    Modification by James G. Smith (jsmith@cygnus.co.uk)
   5
   6    This file is part of libopcodes.
   7
   8    This library is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the License, or
  11    (at your option) any later version.
  12
  13    It is distributed in the hope that it will be useful, but WITHOUT
  14    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16    License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; if not, write to the Free Software
  20    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  21    MA 02110-1301, USA.  */
  22
  23 #include "sysdep.h"
  24 #include <assert.h>
  25
  26 #include "disassemble.h"
  27 #include "opcode/arm.h"
  28 #include "opintl.h"
  29 #include "safe-ctype.h"
  30 #include "libiberty.h"
  31 #include "floatformat.h"
  32
  33 /* FIXME: This shouldn't be done here.  */
  34 #include "coff/internal.h"
  35 #include "libcoff.h"
  36 #include "bfd.h"
  37 #include "elf-bfd.h"
  38 #include "elf/internal.h"
  39 #include "elf/arm.h"
  40 #include "mach-o.h"
  41
  42 /* FIXME: Belongs in global header.  */
  43 #ifndef strneq
  44 #define strneq(a,b,n)   (strncmp ((a), (b), (n)) == 0)
  45 #endif
  46
  47 /* Cached mapping symbol state.  */
  48 enum map_type
  49 {
  50   MAP_ARM,
  51   MAP_THUMB,
  52   MAP_DATA
  53 };
  54
  55 struct arm_private_data
  56 {
  57   /* The features to use when disassembling optional instructions.  */
  58   arm_feature_set features;
  59
  60   /* Track the last type (although this doesn't seem to be useful) */
  61   enum map_type last_type;
  62
  63   /* Tracking symbol table information */
  64   int last_mapping_sym;
  65
  66   /* The end range of the current range being disassembled.  */
  67   bfd_vma last_stop_offset;
  68   bfd_vma last_mapping_addr;
  69 };
  70
  71 enum mve_instructions
  72 {
  73   MVE_VPST,
  74   MVE_VPT_FP_T1,
  75   MVE_VPT_FP_T2,
  76   MVE_VPT_VEC_T1,
  77   MVE_VPT_VEC_T2,
  78   MVE_VPT_VEC_T3,
  79   MVE_VPT_VEC_T4,
  80   MVE_VPT_VEC_T5,
  81   MVE_VPT_VEC_T6,
  82   MVE_VCMP_FP_T1,
  83   MVE_VCMP_FP_T2,
  84   MVE_VCMP_VEC_T1,
  85   MVE_VCMP_VEC_T2,
  86   MVE_VCMP_VEC_T3,
  87   MVE_VCMP_VEC_T4,
  88   MVE_VCMP_VEC_T5,
  89   MVE_VCMP_VEC_T6,
  90   MVE_VDUP,
  91   MVE_VEOR,
  92   MVE_VFMAS_FP_SCALAR,
  93   MVE_VFMA_FP_SCALAR,
  94   MVE_VFMA_FP,
  95   MVE_VFMS_FP,
  96   MVE_VHADD_T1,
  97   MVE_VHADD_T2,
  98   MVE_VHSUB_T1,
  99   MVE_VHSUB_T2,
 100   MVE_VRHADD,
 101   MVE_VLD2,
 102   MVE_VLD4,
 103   MVE_VST2,
 104   MVE_VST4,
 105   MVE_VLDRB_T1,
 106   MVE_VLDRH_T2,
 107   MVE_VLDRB_T5,
 108   MVE_VLDRH_T6,
 109   MVE_VLDRW_T7,
 110   MVE_VSTRB_T1,
 111   MVE_VSTRH_T2,
 112   MVE_VSTRB_T5,
 113   MVE_VSTRH_T6,
 114   MVE_VSTRW_T7,
 115   MVE_VLDRB_GATHER_T1,
 116   MVE_VLDRH_GATHER_T2,
 117   MVE_VLDRW_GATHER_T3,
 118   MVE_VLDRD_GATHER_T4,
 119   MVE_VLDRW_GATHER_T5,
 120   MVE_VLDRD_GATHER_T6,
 121   MVE_VSTRB_SCATTER_T1,
 122   MVE_VSTRH_SCATTER_T2,
 123   MVE_VSTRW_SCATTER_T3,
 124   MVE_VSTRD_SCATTER_T4,
 125   MVE_VSTRW_SCATTER_T5,
 126   MVE_VSTRD_SCATTER_T6,
 127   MVE_VCVT_FP_FIX_VEC,
 128   MVE_VCVT_BETWEEN_FP_INT,
 129   MVE_VCVT_FP_HALF_FP,
 130   MVE_VCVT_FROM_FP_TO_INT,
 131   MVE_VRINT_FP,
 132   MVE_VMOV_HFP_TO_GP,
 133   MVE_VMOV_GP_TO_VEC_LANE,
 134   MVE_VMOV_IMM_TO_VEC,
 135   MVE_VMOV_VEC_TO_VEC,
 136   MVE_VMOV2_VEC_LANE_TO_GP,
 137   MVE_VMOV2_GP_TO_VEC_LANE,
 138   MVE_VMOV_VEC_LANE_TO_GP,
 139   MVE_VMVN_IMM,
 140   MVE_VMVN_REG,
 141   MVE_VORR_IMM,
 142   MVE_VORR_REG,
 143   MVE_VORN,
 144   MVE_VBIC_IMM,
 145   MVE_VBIC_REG,
 146   MVE_VMOVX,
 147   MVE_VMOVL,
 148   MVE_VMOVN,
 149   MVE_VMULL_INT,
 150   MVE_VMULL_POLY,
 151   MVE_VQDMULL_T1,
 152   MVE_VQDMULL_T2,
 153   MVE_VQMOVN,
 154   MVE_VQMOVUN,
 155   MVE_VADDV,
 156   MVE_VMLADAV_T1,
 157   MVE_VMLADAV_T2,
 158   MVE_VMLALDAV,
 159   MVE_VMLAS,
 160   MVE_VADDLV,
 161   MVE_VMLSDAV_T1,
 162   MVE_VMLSDAV_T2,
 163   MVE_VMLSLDAV,
 164   MVE_VRMLALDAVH,
 165   MVE_VRMLSLDAVH,
 166   MVE_VQDMLADH,
 167   MVE_VQRDMLADH,
 168   MVE_VQDMLAH,
 169   MVE_VQRDMLAH,
 170   MVE_VQDMLASH,
 171   MVE_VQRDMLASH,
 172   MVE_VQDMLSDH,
 173   MVE_VQRDMLSDH,
 174   MVE_VQDMULH_T1,
 175   MVE_VQRDMULH_T2,
 176   MVE_VQDMULH_T3,
 177   MVE_VQRDMULH_T4,
 178   MVE_VDDUP,
 179   MVE_VDWDUP,
 180   MVE_VIWDUP,
 181   MVE_VIDUP,
 182   MVE_VCADD_FP,
 183   MVE_VCADD_VEC,
 184   MVE_VHCADD,
 185   MVE_VCMLA_FP,
 186   MVE_VCMUL_FP,
 187   MVE_VQRSHL_T1,
 188   MVE_VQRSHL_T2,
 189   MVE_VQRSHRN,
 190   MVE_VQRSHRUN,
 191   MVE_VQSHL_T1,
 192   MVE_VQSHL_T2,
 193   MVE_VQSHLU_T3,
 194   MVE_VQSHL_T4,
 195   MVE_VQSHRN,
 196   MVE_VQSHRUN,
 197   MVE_VRSHL_T1,
 198   MVE_VRSHL_T2,
 199   MVE_VRSHR,
 200   MVE_VRSHRN,
 201   MVE_VSHL_T1,
 202   MVE_VSHL_T2,
 203   MVE_VSHL_T3,
 204   MVE_VSHLC,
 205   MVE_VSHLL_T1,
 206   MVE_VSHLL_T2,
 207   MVE_VSHR,
 208   MVE_VSHRN,
 209   MVE_VSLI,
 210   MVE_VSRI,
 211   MVE_VADC,
 212   MVE_VABAV,
 213   MVE_VABD_FP,
 214   MVE_VABD_VEC,
 215   MVE_VABS_FP,
 216   MVE_VABS_VEC,
 217   MVE_VADD_FP_T1,
 218   MVE_VADD_FP_T2,
 219   MVE_VADD_VEC_T1,
 220   MVE_VADD_VEC_T2,
 221   MVE_VSBC,
 222   MVE_VSUB_FP_T1,
 223   MVE_VSUB_FP_T2,
 224   MVE_VSUB_VEC_T1,
 225   MVE_VSUB_VEC_T2,
 226   MVE_VAND,
 227   MVE_VBRSR,
 228   MVE_VCLS,
 229   MVE_VCLZ,
 230   MVE_VCTP,
 231   MVE_VMAX,
 232   MVE_VMAXA,
 233   MVE_VMAXNM_FP,
 234   MVE_VMAXNMA_FP,
 235   MVE_VMAXNMV_FP,
 236   MVE_VMAXNMAV_FP,
 237   MVE_VMAXV,
 238   MVE_VMAXAV,
 239   MVE_VMIN,
 240   MVE_VMINA,
 241   MVE_VMINNM_FP,
 242   MVE_VMINNMA_FP,
 243   MVE_VMINNMV_FP,
 244   MVE_VMINNMAV_FP,
 245   MVE_VMINV,
 246   MVE_VMINAV,
 247   MVE_VMLA,
 248   MVE_VMUL_FP_T1,
 249   MVE_VMUL_FP_T2,
 250   MVE_VMUL_VEC_T1,
 251   MVE_VMUL_VEC_T2,
 252   MVE_VMULH,
 253   MVE_VRMULH,
 254   MVE_VNEG_FP,
 255   MVE_VNEG_VEC,
 256   MVE_NONE
 257 };
 258
 259 enum mve_unpredictable
 260 {
 261   UNPRED_IT_BLOCK,              /* Unpredictable because mve insn in it block.
 262                                  */
 263   UNPRED_FCA_0_FCB_1,           /* Unpredictable because fcA = 0 and
 264                                    fcB = 1 (vpt).  */
 265   UNPRED_R13,                   /* Unpredictable because r13 (sp) or
 266                                    r15 (sp) used.  */
 267   UNPRED_R15,                   /* Unpredictable because r15 (pc) is used.  */
 268   UNPRED_Q_GT_4,                /* Unpredictable because
 269                                    vec reg start > 4 (vld4/st4).  */
 270   UNPRED_Q_GT_6,                /* Unpredictable because
 271                                    vec reg start > 6 (vld2/st2).  */
 272   UNPRED_R13_AND_WB,            /* Unpredictable becase gp reg = r13
 273                                    and WB bit = 1.  */
 274   UNPRED_Q_REGS_EQUAL,          /* Unpredictable because vector registers are
 275                                    equal.  */
 276   UNPRED_OS,                    /* Unpredictable because offset scaled == 1.  */
 277   UNPRED_GP_REGS_EQUAL,         /* Unpredictable because gp registers are the
 278                                    same.  */
 279   UNPRED_Q_REGS_EQ_AND_SIZE_1,  /* Unpredictable because q regs equal and
 280                                    size = 1.  */
 281   UNPRED_Q_REGS_EQ_AND_SIZE_2,  /* Unpredictable because q regs equal and
 282                                    size = 2.  */
 283   UNPRED_NONE                   /* No unpredictable behavior.  */
 284 };
 285
 286 enum mve_undefined
 287 {
 288   UNDEF_SIZE,                   /* undefined size.  */
 289   UNDEF_SIZE_0,                 /* undefined because size == 0.  */
 290   UNDEF_SIZE_2,                 /* undefined because size == 2.  */
 291   UNDEF_SIZE_3,                 /* undefined because size == 3.  */
 292   UNDEF_SIZE_LE_1,              /* undefined because size <= 1.  */
 293   UNDEF_SIZE_NOT_2,             /* undefined because size != 2.  */
 294   UNDEF_SIZE_NOT_3,             /* undefined because size != 3.  */
 295   UNDEF_NOT_UNS_SIZE_0,         /* undefined because U == 0 and
 296                                    size == 0.  */
 297   UNDEF_NOT_UNS_SIZE_1,         /* undefined because U == 0 and
 298                                    size == 1.  */
 299   UNDEF_NOT_UNSIGNED,           /* undefined because U == 0.  */
 300   UNDEF_VCVT_IMM6,              /* imm6 < 32.  */
 301   UNDEF_VCVT_FSI_IMM6,          /* fsi = 0 and 32 >= imm6 <= 47.  */
 302   UNDEF_BAD_OP1_OP2,            /* undefined with op2 = 2 and
 303                                    op1 == (0 or 1).  */
 304   UNDEF_BAD_U_OP1_OP2,          /* undefined with U = 1 and
 305                                    op2 == 0 and op1 == (0 or 1).  */
 306   UNDEF_OP_0_BAD_CMODE,         /* undefined because op == 0 and cmode
 307                                    in {0xx1, x0x1}.  */
 308   UNDEF_XCHG_UNS,               /* undefined because X == 1 and U == 1.  */
 309   UNDEF_NONE                    /* no undefined behavior.  */
 310 };
 311
 312 struct opcode32
 313 {
 314   arm_feature_set arch;         /* Architecture defining this insn.  */
 315   unsigned long value;          /* If arch is 0 then value is a sentinel.  */
 316   unsigned long mask;           /* Recognise insn if (op & mask) == value.  */
 317   const char *  assembler;      /* How to disassemble this insn.  */
 318 };
 319
 320 /* MVE opcodes.  */
 321
 322 struct mopcode32
 323 {
 324   arm_feature_set arch;         /* Architecture defining this insn.  */
 325   enum mve_instructions mve_op;  /* Specific mve instruction for faster
 326                                     decoding.  */
 327   unsigned long value;          /* If arch is 0 then value is a sentinel.  */
 328   unsigned long mask;           /* Recognise insn if (op & mask) == value.  */
 329   const char *  assembler;      /* How to disassemble this insn.  */
 330 };
 331
 332 enum isa {
 333   ANY,
 334   T32,
 335   ARM
 336 };
 337
 338
 339 /* Shared (between Arm and Thumb mode) opcode.  */
 340 struct sopcode32
 341 {
 342   enum isa isa;                 /* Execution mode instruction availability.  */
 343   arm_feature_set arch;         /* Architecture defining this insn.  */
 344   unsigned long value;          /* If arch is 0 then value is a sentinel.  */
 345   unsigned long mask;           /* Recognise insn if (op & mask) == value.  */
 346   const char *  assembler;      /* How to disassemble this insn.  */
 347 };
 348
 349 struct opcode16
 350 {
 351   arm_feature_set arch;         /* Architecture defining this insn.  */
 352   unsigned short value, mask;   /* Recognise insn if (op & mask) == value.  */
 353   const char *assembler;        /* How to disassemble this insn.  */
 354 };
 355
 356 /* print_insn_coprocessor recognizes the following format control codes:
 357
 358    %%                   %
 359
 360    %c                   print condition code (always bits 28-31 in ARM mode)
 361    %q                   print shifter argument
 362    %u                   print condition code (unconditional in ARM mode,
 363                           UNPREDICTABLE if not AL in Thumb)
 364    %A                   print address for ldc/stc/ldf/stf instruction
 365    %B                   print vstm/vldm register list
 366    %C                   print vscclrm register list
 367    %I                   print cirrus signed shift immediate: bits 0..3|4..6
 368    %J                   print register for VLDR instruction
 369    %K                   print address for VLDR instruction
 370    %F                   print the COUNT field of a LFM/SFM instruction.
 371    %P                   print floating point precision in arithmetic insn
 372    %Q                   print floating point precision in ldf/stf insn
 373    %R                   print floating point rounding mode
 374
 375    %<bitfield>c         print as a condition code (for vsel)
 376    %<bitfield>r         print as an ARM register
 377    %<bitfield>R         as %<>r but r15 is UNPREDICTABLE
 378    %<bitfield>ru        as %<>r but each u register must be unique.
 379    %<bitfield>d         print the bitfield in decimal
 380    %<bitfield>k         print immediate for VFPv3 conversion instruction
 381    %<bitfield>x         print the bitfield in hex
 382    %<bitfield>X         print the bitfield as 1 hex digit without leading "0x"
 383    %<bitfield>f         print a floating point constant if >7 else a
 384                         floating point register
 385    %<bitfield>w         print as an iWMMXt width field - [bhwd]ss/us
 386    %<bitfield>g         print as an iWMMXt 64-bit register
 387    %<bitfield>G         print as an iWMMXt general purpose or control register
 388    %<bitfield>D         print as a NEON D register
 389    %<bitfield>Q         print as a NEON Q register
 390    %<bitfield>V         print as a NEON D or Q register
 391    %<bitfield>E         print a quarter-float immediate value
 392
 393    %y<code>             print a single precision VFP reg.
 394                           Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
 395    %z<code>             print a double precision VFP reg
 396                           Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
 397
 398    %<bitfield>'c        print specified char iff bitfield is all ones
 399    %<bitfield>`c        print specified char iff bitfield is all zeroes
 400    %<bitfield>?ab...    select from array of values in big endian order
 401
 402    %L                   print as an iWMMXt N/M width field.
 403    %Z                   print the Immediate of a WSHUFH instruction.
 404    %l                   like 'A' except use byte offsets for 'B' & 'H'
 405                         versions.
 406    %i                   print 5-bit immediate in bits 8,3..0
 407                         (print "32" when 0)
 408    %r                   print register offset address for wldt/wstr instruction.  */
 409
 410 enum opcode_sentinel_enum
 411 {
 412   SENTINEL_IWMMXT_START = 1,
 413   SENTINEL_IWMMXT_END,
 414   SENTINEL_GENERIC_START
 415 } opcode_sentinels;
 416
 417 #define UNDEFINED_INSTRUCTION      "\t\t; <UNDEFINED> instruction: %0-31x"
 418 #define UNKNOWN_INSTRUCTION_32BIT  "\t\t; <UNDEFINED> instruction: %08x"
 419 #define UNKNOWN_INSTRUCTION_16BIT  "\t\t; <UNDEFINED> instruction: %04x"
 420 #define UNPREDICTABLE_INSTRUCTION  "\t; <UNPREDICTABLE>"
 421
 422 /* Common coprocessor opcodes shared between Arm and Thumb-2.  */
 423
 424 static const struct sopcode32 coprocessor_opcodes[] =
 425 {
 426   /* XScale instructions.  */
 427   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 428     0x0e200010, 0x0fff0ff0,
 429     "mia%c\tacc0, %0-3r, %12-15r"},
 430   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 431     0x0e280010, 0x0fff0ff0,
 432     "miaph%c\tacc0, %0-3r, %12-15r"},
 433   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 434     0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
 435   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 436     0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
 437   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 438     0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
 439
 440   /* Intel Wireless MMX technology instructions.  */
 441   {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
 442   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
 443     0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
 444   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 445     0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
 446   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 447     0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
 448   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 449     0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
 450   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 451     0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
 452   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 453     0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
 454   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 455     0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
 456   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 457     0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
 458   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 459     0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
 460   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 461     0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
 462   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 463     0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
 464   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 465     0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
 466   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 467     0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
 468   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 469     0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
 470   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 471     0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
 472   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 473     0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
 474   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 475     0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
 476   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 477     0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
 478   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 479     0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
 480   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 481     0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
 482   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 483     0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
 484   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 485     0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
 486   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 487     0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
 488   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 489     0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
 490   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 491     0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
 492   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 493     0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 494   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 495     0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 496   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 497     0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
 498   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 499     0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
 500   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 501     0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
 502   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 503     0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
 504   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 505     0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
 506   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 507     0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
 508   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 509     0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 510   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 511     0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
 512   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 513     0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
 514   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 515     0x0e800120, 0x0f800ff0,
 516     "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
 517   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 518     0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 519   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 520     0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
 521   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 522     0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
 523   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 524     0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
 525   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 526     0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
 527   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 528     0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
 529   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 530     0x0e8000a0, 0x0f800ff0,
 531     "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
 532   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 533     0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
 534   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 535     0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
 536   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 537     0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
 538   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 539     0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
 540   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 541     0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
 542   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 543     0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 544   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 545     0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
 546   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 547     0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
 548   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 549     0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
 550   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 551     0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
 552   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 553     0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
 554   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 555     0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
 556   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 557     0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
 558   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 559     0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
 560   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 561     0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
 562   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 563     0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
 564   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 565     0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
 566   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 567     0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
 568   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 569     0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
 570   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 571     0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
 572   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 573     0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
 574   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 575     0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
 576   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 577     0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
 578   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 579     0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 580   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 581     0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
 582   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 583     0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
 584   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 585     0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
 586   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 587     0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
 588   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 589     0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 590   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 591     0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 592   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 593     0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
 594   {ANY, ARM_FEATURE_CORE_LOW (0),
 595     SENTINEL_IWMMXT_END, 0, "" },
 596
 597   /* Floating point coprocessor (FPA) instructions.  */
 598   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 599     0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 600   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 601     0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 602   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 603     0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 604   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 605     0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 606   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 607     0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 608   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 609     0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 610   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 611     0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
 612   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 613     0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
 614   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 615     0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 616   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 617     0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
 618   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 619     0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
 620   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 621     0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
 622   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 623     0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
 624   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 625     0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
 626   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 627     0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
 628   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 629     0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
 630   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 631     0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
 632   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 633     0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
 634   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 635     0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
 636   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 637     0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
 638   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 639     0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
 640   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 641     0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
 642   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 643     0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
 644   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 645     0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
 646   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 647     0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
 648   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 649     0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
 650   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 651     0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
 652   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 653     0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
 654   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 655     0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
 656   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 657     0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
 658   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 659     0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
 660   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 661     0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
 662   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 663     0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
 664   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 665     0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
 666   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 667     0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
 668   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 669     0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
 670   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 671     0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
 672   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 673     0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
 674   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 675     0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
 676   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 677     0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
 678   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 679     0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
 680   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
 681     0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
 682   {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
 683     0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
 684
 685   /* Armv8.1-M Mainline instructions.  */
 686   {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
 687     0xec9f0b00, 0xffbf0f01, "vscclrm%c\t%C"},
 688   {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
 689     0xec9f0a00, 0xffbf0f00, "vscclrm%c\t%C"},
 690
 691   /* ARMv8-M Mainline Security Extensions instructions.  */
 692   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
 693     0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
 694   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
 695     0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
 696
 697   /* Register load/store.  */
 698   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 699     0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
 700   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 701     0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
 702   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 703     0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
 704   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 705     0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
 706   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 707     0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
 708   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 709     0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
 710   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 711     0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
 712   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 713     0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
 714   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 715     0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
 716   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 717     0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
 718   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 719     0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
 720   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 721     0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
 722   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 723     0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
 724   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 725     0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
 726   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 727     0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
 728   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 729     0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
 730   {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
 731     0xec100f80, 0xfe101f80, "vldr%c\t%J, %K"},
 732   {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
 733     0xec000f80, 0xfe101f80, "vstr%c\t%J, %K"},
 734
 735   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 736     0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
 737   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 738     0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
 739   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 740     0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
 741   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 742     0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
 743
 744   /* Data transfer between ARM and NEON registers.  */
 745   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 746     0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
 747   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 748     0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
 749   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 750     0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
 751   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 752     0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
 753   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 754     0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
 755   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 756     0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
 757   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 758     0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
 759   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 760     0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
 761   /* Half-precision conversion instructions.  */
 762   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 763     0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
 764   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 765     0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
 766   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
 767     0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
 768   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
 769     0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
 770
 771   /* Floating point coprocessor (VFP) instructions.  */
 772   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 773     0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
 774   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 775     0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
 776   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 777     0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
 778   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 779     0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
 780   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 781     0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"},
 782   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 783     0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
 784   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 785     0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
 786   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 787     0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
 788   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 789     0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
 790   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 791     0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
 792   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 793     0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
 794   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 795     0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"},
 796   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 797     0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
 798   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 799     0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
 800   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 801     0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
 802   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 803     0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
 804   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 805     0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
 806   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 807     0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
 808   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 809     0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
 810   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 811     0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
 812   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 813     0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
 814   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 815     0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
 816   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 817     0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
 818   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 819     0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
 820   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 821     0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
 822   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 823     0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
 824   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 825     0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
 826   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 827     0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
 828   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 829     0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
 830   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 831     0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
 832   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 833     0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
 834   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 835     0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
 836   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 837     0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
 838   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 839     0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
 840   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 841     0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
 842   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 843     0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
 844   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 845     0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
 846   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 847     0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
 848   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 849     0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
 850   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
 851     0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
 852   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
 853     0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
 854   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 855     0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
 856   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 857     0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
 858   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
 859     0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
 860   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
 861     0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
 862   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 863     0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
 864   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
 865     0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
 866   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
 867     0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
 868   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
 869     0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
 870   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
 871     0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
 872   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
 873     0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
 874   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 875     0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
 876   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 877     0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
 878   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 879     0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
 880   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 881     0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
 882   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 883     0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
 884   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 885     0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
 886   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 887     0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
 888   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 889     0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
 890   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 891     0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
 892   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 893     0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
 894   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 895     0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
 896   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 897     0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
 898   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 899     0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
 900   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 901     0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
 902   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 903     0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
 904   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 905     0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
 906   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 907     0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
 908   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 909     0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
 910
 911   /* Cirrus coprocessor instructions.  */
 912   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 913     0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
 914   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 915     0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
 916   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 917     0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
 918   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 919     0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
 920   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 921     0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
 922   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 923     0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
 924   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 925     0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
 926   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 927     0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
 928   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 929     0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
 930   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 931     0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
 932   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 933     0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
 934   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 935     0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
 936   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 937     0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
 938   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 939     0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
 940   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 941     0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
 942   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 943     0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
 944   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 945     0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
 946   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 947     0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
 948   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 949     0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
 950   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 951     0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
 952   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 953     0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
 954   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 955     0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
 956   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 957     0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
 958   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 959     0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
 960   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 961     0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
 962   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 963     0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
 964   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 965     0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
 966   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 967     0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
 968   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 969     0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
 970   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 971     0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
 972   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 973     0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
 974   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 975     0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
 976   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 977     0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
 978   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 979     0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
 980   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 981     0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
 982   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 983     0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
 984   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 985     0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
 986   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 987     0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
 988   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 989     0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
 990   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 991     0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
 992   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 993     0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
 994   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 995     0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
 996   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 997     0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
 998   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 999     0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
1000   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1001     0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
1002   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1003     0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
1004   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1005     0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
1006   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1007     0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
1008   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1009     0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
1010   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1011     0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
1012   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1013     0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
1014   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1015     0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
1016   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1017     0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
1018   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1019     0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
1020   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1021     0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
1022   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1023     0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
1024   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1025     0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
1026   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1027     0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
1028   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1029     0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
1030   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1031     0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
1032   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1033     0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
1034   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1035     0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
1036   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1037     0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
1038   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1039     0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
1040   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1041     0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
1042   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1043     0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
1044   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1045     0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
1046   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1047     0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
1048   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1049     0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
1050   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1051     0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
1052   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1053     0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
1054   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1055     0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
1056   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1057     0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1058   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1059     0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
1060   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1061     0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1062   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1063     0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
1064   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1065     0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1066   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1067     0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
1068   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1069     0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1070   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1071     0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1072   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1073     0x0e000600, 0x0ff00f10,
1074     "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1075   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1076     0x0e100600, 0x0ff00f10,
1077     "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1078   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1079     0x0e200600, 0x0ff00f10,
1080     "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
1081   {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
1082     0x0e300600, 0x0ff00f10,
1083     "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
1084
1085   /* VFP Fused multiply add instructions.  */
1086   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1087     0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
1088   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1089     0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
1090   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1091     0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
1092   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1093     0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
1094   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1095     0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
1096   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1097     0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
1098   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1099     0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
1100   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
1101     0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
1102
1103   /* FP v5.  */
1104   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1105     0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
1106   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1107     0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
1108   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1109     0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
1110   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1111     0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
1112   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1113     0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
1114   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1115     0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
1116   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1117     0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
1118   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1119     0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
1120   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1121     0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
1122   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1123     0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
1124   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1125     0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
1126   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
1127     0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
1128
1129   /* Generic coprocessor instructions.  */
1130   {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
1131   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1132     0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
1133   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1134     0x0c500000, 0x0ff00000,
1135     "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
1136   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1137     0x0e000000, 0x0f000010,
1138     "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
1139   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1140     0x0e10f010, 0x0f10f010,
1141     "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
1142   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1143     0x0e100010, 0x0f100010,
1144     "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1145   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1146     0x0e000010, 0x0f100010,
1147     "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
1148   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1149     0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
1150   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1151     0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
1152
1153   /* V6 coprocessor instructions.  */
1154   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1155     0xfc500000, 0xfff00000,
1156     "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
1157   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1158     0xfc400000, 0xfff00000,
1159     "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
1160
1161   /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8.  */
1162   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1163     0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
1164   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1165     0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
1166   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1167     0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
1168   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1169     0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
1170   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1171     0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
1172   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1173     0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
1174   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1175     0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
1176   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1177     0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"},
1178   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1179     0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
1180   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1181     0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"},
1182
1183   /* Dot Product instructions in the space of coprocessor 13.  */
1184   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
1185     0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
1186   {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
1187     0xfe000d00, 0xff000f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"},
1188
1189   /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8.  */
1190   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1191     0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
1192   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1193     0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
1194   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1195     0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
1196   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1197     0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
1198   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1199     0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
1200   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1201     0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
1202   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1203     0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
1204   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
1205     0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
1206
1207   /* V5 coprocessor instructions.  */
1208   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1209     0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
1210   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1211     0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
1212   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1213     0xfe000000, 0xff000010,
1214     "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
1215   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1216     0xfe000010, 0xff100010,
1217     "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
1218   {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1219     0xfe100010, 0xff100010,
1220     "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1221
1222   /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
1223      cp_num: bit <11:8> == 0b1001.
1224      cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE.  */
1225   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1226     0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
1227   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1228     0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
1229   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1230     0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
1231   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1232     0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
1233   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1234     0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
1235   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1236     0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
1237   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1238     0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
1239   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1240     0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
1241   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1242     0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
1243   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1244     0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
1245   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1246     0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
1247   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1248     0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
1249   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1250     0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
1251   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1252     0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
1253   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1254     0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
1255   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1256     0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
1257   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1258     0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
1259   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1260     0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
1261   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1262     0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
1263   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1264     0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
1265   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1266     0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
1267   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1268     0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
1269   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1270     0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
1271   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1272     0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
1273   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1274     0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
1275   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1276     0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
1277   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1278     0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
1279   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1280     0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
1281   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1282     0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
1283   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1284     0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
1285   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1286     0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
1287   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1288     0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
1289   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1290     0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
1291   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1292     0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
1293   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1294     0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
1295
1296   /* ARMv8.3 javascript conversion instruction.  */
1297   {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1298     0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
1299
1300   {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
1301 };
1302
1303 /* Neon opcode table:  This does not encode the top byte -- that is
1304    checked by the print_insn_neon routine, as it depends on whether we are
1305    doing thumb32 or arm32 disassembly.  */
1306
1307 /* print_insn_neon recognizes the following format control codes:
1308
1309    %%                   %
1310
1311    %c                   print condition code
1312    %u                   print condition code (unconditional in ARM mode,
1313                           UNPREDICTABLE if not AL in Thumb)
1314    %A                   print v{st,ld}[1234] operands
1315    %B                   print v{st,ld}[1234] any one operands
1316    %C                   print v{st,ld}[1234] single->all operands
1317    %D                   print scalar
1318    %E                   print vmov, vmvn, vorr, vbic encoded constant
1319    %F                   print vtbl,vtbx register list
1320
1321    %<bitfield>r         print as an ARM register
1322    %<bitfield>d         print the bitfield in decimal
1323    %<bitfield>e         print the 2^N - bitfield in decimal
1324    %<bitfield>D         print as a NEON D register
1325    %<bitfield>Q         print as a NEON Q register
1326    %<bitfield>R         print as a NEON D or Q register
1327    %<bitfield>Sn        print byte scaled width limited by n
1328    %<bitfield>Tn        print short scaled width limited by n
1329    %<bitfield>Un        print long scaled width limited by n
1330
1331    %<bitfield>'c        print specified char iff bitfield is all ones
1332    %<bitfield>`c        print specified char iff bitfield is all zeroes
1333    %<bitfield>?ab...    select from array of values in big endian order.  */
1334
1335 static const struct opcode32 neon_opcodes[] =
1336 {
1337   /* Extract.  */
1338   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1339     0xf2b00840, 0xffb00850,
1340     "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1341   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1342     0xf2b00000, 0xffb00810,
1343     "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1344
1345   /* Data transfer between ARM and NEON registers.  */
1346   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1347     0x0e800b10, 0x1ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
1348   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1349     0x0e800b30, 0x1ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
1350   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1351     0x0ea00b10, 0x1ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
1352   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1353     0x0ea00b30, 0x1ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
1354   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1355     0x0ec00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
1356   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1357     0x0ee00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
1358
1359   /* Move data element to all lanes.  */
1360   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1361     0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
1362   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1363     0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
1364   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1365     0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
1366
1367   /* Table lookup.  */
1368   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1369     0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1370   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1371     0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1372
1373   /* Half-precision conversions.  */
1374   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1375     0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1376   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1377     0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
1378
1379   /* NEON fused multiply add instructions.  */
1380   {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
1381     0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1382   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1383     0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1384   {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
1385     0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1386   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1387     0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1388
1389   /* Two registers, miscellaneous.  */
1390   {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1391     0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
1392   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1393     0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
1394   {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1395     0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
1396   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1397     0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
1398   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1399     0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1400   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1401     0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1402   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1403     0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1404   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1405     0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1406   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1407     0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1408   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1409     0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1410   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1411     0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1412   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1413     0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1414   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1415     0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1416   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1417     0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1418   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1419     0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1420   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1421     0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1422   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1423     0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1424   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1425     0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1426   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1427     0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1428   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1429     0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1430   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1431     0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1432   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1433     0xf3b20300, 0xffb30fd0,
1434     "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1435   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1436     0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1437   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1438     0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1439   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1440     0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1441   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1442     0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1443   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1444     0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1445   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1446     0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1447   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1448     0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1449   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1450     0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1451   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1452     0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1453   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1454     0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1455   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1456     0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1457   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1458     0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1459   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1460     0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1461   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1462     0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1463   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1464     0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1465   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1466     0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1467   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1468     0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1469   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1470     0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1471   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1472     0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1473   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1474     0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1475   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1476     0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1477   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1478     0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1479   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1480     0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1481   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1482     0xf3bb0600, 0xffbf0e10,
1483     "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
1484   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1485     0xf3b70600, 0xffbf0e10,
1486     "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
1487
1488   /* Three registers of the same length.  */
1489   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1490     0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1491   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1492     0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1493   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1494     0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1495   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1496     0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1497   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1498     0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1499   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1500     0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1501   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1502     0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1503   {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1504     0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1505   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1506     0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1507   {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1508     0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1509   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1510     0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1511   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1512     0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1513   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1514     0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1515   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1516     0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1517   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1518     0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1519   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1520     0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1521   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1522     0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1523   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1524     0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1525   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1526     0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1527   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1528     0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1529   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1530     0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1531   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1532     0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1533   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1534     0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1535   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1536     0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1537   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1538     0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1539   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1540     0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1541   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1542     0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1543   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1544     0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1545   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1546     0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1547   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1548     0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1549   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1550     0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1551   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1552     0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1553   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1554     0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1555   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1556     0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1557   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1558     0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1559   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1560     0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1561   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1562     0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1563   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1564     0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1565   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1566     0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1567   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1568     0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1569   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1570     0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1571   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1572     0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1573   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1574     0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1575   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1576     0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1577   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1578     0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1579   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1580     0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1581   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1582     0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1583   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1584     0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1585   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1586     0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1587   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1588     0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1589   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1590     0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1591   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1592     0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1593   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1594     0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1595   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1596     0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1597   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1598     0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1599   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1600     0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1601   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1602     0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1603   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1604     0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1605   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1606     0xf2000b00, 0xff800f10,
1607     "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1608   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1609     0xf2000b10, 0xff800f10,
1610     "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1611   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1612     0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1613   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1614     0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1615   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1616     0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1617   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1618     0xf3000b00, 0xff800f10,
1619     "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1620   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1621     0xf2000000, 0xfe800f10,
1622     "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1623   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1624     0xf2000010, 0xfe800f10,
1625     "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1626   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1627     0xf2000100, 0xfe800f10,
1628     "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1629   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1630     0xf2000200, 0xfe800f10,
1631     "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1632   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1633     0xf2000210, 0xfe800f10,
1634     "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1635   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1636     0xf2000300, 0xfe800f10,
1637     "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1638   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1639     0xf2000310, 0xfe800f10,
1640     "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1641   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1642     0xf2000400, 0xfe800f10,
1643     "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1644   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1645     0xf2000410, 0xfe800f10,
1646     "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1647   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1648     0xf2000500, 0xfe800f10,
1649     "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1650   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1651     0xf2000510, 0xfe800f10,
1652     "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1653   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1654     0xf2000600, 0xfe800f10,
1655     "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1656   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1657     0xf2000610, 0xfe800f10,
1658     "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1659   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1660     0xf2000700, 0xfe800f10,
1661     "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1662   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1663     0xf2000710, 0xfe800f10,
1664     "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1665   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1666     0xf2000910, 0xfe800f10,
1667     "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1668   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1669     0xf2000a00, 0xfe800f10,
1670     "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1671   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1672     0xf2000a10, 0xfe800f10,
1673     "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1674   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1675     0xf3000b10, 0xff800f10,
1676     "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1677   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1678     0xf3000c10, 0xff800f10,
1679     "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1680
1681   /* One register and an immediate value.  */
1682   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1683     0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1684   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1685     0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1686   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1687     0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1688   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1689     0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1690   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1691     0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1692   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1693     0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1694   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1695     0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1696   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1697     0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1698   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1699     0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1700   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1701     0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1702   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1703     0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1704   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1705     0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1706   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1707     0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
1708
1709   /* Two registers and a shift amount.  */
1710   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1711     0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1712   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1713     0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1714   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1715     0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1716   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1717     0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1718   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1719     0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1720   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1721     0xf2880950, 0xfeb80fd0,
1722     "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1723   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1724     0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1725   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1726     0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1727   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1728     0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1729   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1730     0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1731   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1732     0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1733   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1734     0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1735   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1736     0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1737   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1738     0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1739   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1740     0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1741   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1742     0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1743   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1744     0xf2900950, 0xfeb00fd0,
1745     "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1746   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1747     0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1748   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1749     0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1750   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1751     0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1752   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1753     0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1754   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1755     0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1756   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1757     0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1758   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1759     0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1760   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1761     0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1762   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1763     0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1764   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1765     0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1766   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1767     0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1768   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1769     0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1770   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1771     0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1772   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1773     0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1774   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1775     0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1776   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1777     0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1778   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1779     0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1780   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1781     0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1782   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1783     0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1784   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1785     0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1786   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1787     0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1788   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1789     0xf2a00950, 0xfea00fd0,
1790     "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1791   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1792     0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1793   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1794     0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1795   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1796     0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1797   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1798     0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1799   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1800     0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1801   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1802     0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1803   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1804     0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1805   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1806     0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1807   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1808     0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1809   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1810     0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1811   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1812     0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1813   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1814     0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1815   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1816     0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1817   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1818     0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1819   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1820     0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1821   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1822     0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1823   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1824     0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1825   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1826     0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1827   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1828     0xf2a00e10, 0xfea00e90,
1829     "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
1830   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1831     0xf2a00c10, 0xfea00e90,
1832     "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"},
1833
1834   /* Three registers of different lengths.  */
1835   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1836     0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1837   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1838     0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1839   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1840     0xf2800400, 0xff800f50,
1841     "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1842   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1843     0xf2800600, 0xff800f50,
1844     "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1845   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1846     0xf2800900, 0xff800f50,
1847     "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1848   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1849     0xf2800b00, 0xff800f50,
1850     "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1851   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1852     0xf2800d00, 0xff800f50,
1853     "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1854   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1855     0xf3800400, 0xff800f50,
1856     "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1857   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1858     0xf3800600, 0xff800f50,
1859     "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1860   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1861     0xf2800000, 0xfe800f50,
1862     "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1863   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1864     0xf2800100, 0xfe800f50,
1865     "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1866   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1867     0xf2800200, 0xfe800f50,
1868     "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1869   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1870     0xf2800300, 0xfe800f50,
1871     "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1872   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1873     0xf2800500, 0xfe800f50,
1874     "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1875   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1876     0xf2800700, 0xfe800f50,
1877     "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1878   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1879     0xf2800800, 0xfe800f50,
1880     "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1881   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1882     0xf2800a00, 0xfe800f50,
1883     "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1884   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1885     0xf2800c00, 0xfe800f50,
1886     "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1887
1888   /* Two registers and a scalar.  */
1889   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1890     0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1891   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1892     0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1893   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1894     0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
1895   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1896     0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1897   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1898     0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1899   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1900     0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1901   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1902     0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
1903   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1904     0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1905   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1906     0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1907   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1908     0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1909   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1910     0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
1911   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1912     0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1913   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1914     0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1915   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1916     0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1917   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1918     0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1919   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1920     0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1921   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1922     0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1923   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1924     0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1925   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1926     0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1927   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1928     0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1929   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1930     0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1931   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1932     0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1933   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1934     0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1935   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1936     0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1937   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1938     0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1939   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1940     0xf2800240, 0xfe800f50,
1941     "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1942   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1943     0xf2800640, 0xfe800f50,
1944     "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1945   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1946     0xf2800a40, 0xfe800f50,
1947     "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1948   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1949     0xf2800e40, 0xff800f50,
1950    "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1951   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1952     0xf2800f40, 0xff800f50,
1953    "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1954   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1955     0xf3800e40, 0xff800f50,
1956    "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1957   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1958     0xf3800f40, 0xff800f50,
1959    "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
1960   },
1961
1962   /* Element and structure load/store.  */
1963   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1964     0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
1965   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1966     0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
1967   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1968     0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
1969   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1970     0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
1971   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1972     0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
1973   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1974     0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1975   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1976     0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1977   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1978     0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1979   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1980     0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1981   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1982     0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1983   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1984     0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1985   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1986     0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1987   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1988     0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1989   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1990     0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1991   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1992     0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
1993   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1994     0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
1995   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1996     0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
1997   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1998     0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
1999   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2000     0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
2001
2002   {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
2003 };
2004
2005 /* mve opcode table.  */
2006
2007 /* print_insn_mve recognizes the following format control codes:
2008
2009    %%                   %
2010
2011    %a                   print '+' or '-' or imm offset in vldr[bhwd] and
2012                         vstr[bhwd]
2013    %c                   print condition code
2014    %d                   print addr mode of MVE vldr[bhw] and vstr[bhw]
2015    %u                   print 'U' (unsigned) or 'S' for various mve instructions
2016    %i                   print MVE predicate(s) for vpt and vpst
2017    %m                   print rounding mode for vcvt and vrint
2018    %n                   print vector comparison code for predicated instruction
2019    %s                   print size for various vcvt instructions
2020    %v                   print vector predicate for instruction in predicated
2021                         block
2022    %o                   print offset scaled for vldr[hwd] and vstr[hwd]
2023    %w                   print writeback mode for MVE v{st,ld}[24]
2024    %B                   print v{st,ld}[24] any one operands
2025    %E                   print vmov, vmvn, vorr, vbic encoded constant
2026    %N                   print generic index for vmov
2027    %T                   print bottom ('b') or top ('t') of source register
2028    %X                   print exchange field in vmla* instructions
2029
2030    %<bitfield>r         print as an ARM register
2031    %<bitfield>d         print the bitfield in decimal
2032    %<bitfield>A         print accumulate or not
2033    %<bitfield>Q         print as a MVE Q register
2034    %<bitfield>F         print as a MVE S register
2035    %<bitfield>Z         as %<>r but r15 is ZR instead of PC and r13 is
2036                         UNPREDICTABLE
2037    %<bitfield>s         print size for vector predicate & non VMOV instructions
2038    %<bitfield>I         print carry flag or not
2039    %<bitfield>i         print immediate for vstr/vldr reg +/- imm
2040    %<bitfield>h         print high half of 64-bit destination reg
2041    %<bitfield>k         print immediate for vector conversion instruction
2042    %<bitfield>l         print low half of 64-bit destination reg
2043    %<bitfield>o         print rotate value for vcmul
2044    %<bitfield>u         print immediate value for vddup/vdwdup
2045    %<bitfield>x         print the bitfield in hex.
2046   */
2047
2048 static const struct mopcode32 mve_opcodes[] =
2049 {
2050   /* MVE.  */
2051
2052   {ARM_FEATURE_COPROC (FPU_MVE),
2053    MVE_VPST,
2054    0xfe310f4d, 0xffbf1fff,
2055    "vpst%i"
2056   },
2057
2058   /* Floating point VPT T1.  */
2059   {ARM_FEATURE_COPROC (FPU_MVE_FP),
2060    MVE_VPT_FP_T1,
2061    0xee310f00, 0xefb10f50,
2062    "vpt%i.f%28s\t%n, %17-19Q, %1-3,5Q"},
2063   /* Floating point VPT T2.  */
2064   {ARM_FEATURE_COPROC (FPU_MVE_FP),
2065    MVE_VPT_FP_T2,
2066    0xee310f40, 0xefb10f50,
2067    "vpt%i.f%28s\t%n, %17-19Q, %0-3Z"},
2068
2069   /* Vector VPT T1.  */
2070   {ARM_FEATURE_COPROC (FPU_MVE),
2071    MVE_VPT_VEC_T1,
2072    0xfe010f00, 0xff811f51,
2073    "vpt%i.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2074   /* Vector VPT T2.  */
2075   {ARM_FEATURE_COPROC (FPU_MVE),
2076    MVE_VPT_VEC_T2,
2077    0xfe010f01, 0xff811f51,
2078    "vpt%i.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2079   /* Vector VPT T3.  */
2080   {ARM_FEATURE_COPROC (FPU_MVE),
2081    MVE_VPT_VEC_T3,
2082    0xfe011f00, 0xff811f50,
2083    "vpt%i.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2084   /* Vector VPT T4.  */
2085   {ARM_FEATURE_COPROC (FPU_MVE),
2086    MVE_VPT_VEC_T4,
2087    0xfe010f40, 0xff811f70,
2088    "vpt%i.i%20-21s\t%n, %17-19Q, %0-3Z"},
2089   /* Vector VPT T5.  */
2090   {ARM_FEATURE_COPROC (FPU_MVE),
2091    MVE_VPT_VEC_T5,
2092    0xfe010f60, 0xff811f70,
2093    "vpt%i.u%20-21s\t%n, %17-19Q, %0-3Z"},
2094   /* Vector VPT T6.  */
2095   {ARM_FEATURE_COPROC (FPU_MVE),
2096    MVE_VPT_VEC_T6,
2097    0xfe011f40, 0xff811f50,
2098    "vpt%i.s%20-21s\t%n, %17-19Q, %0-3Z"},
2099
2100   /* Vector VBIC immediate.  */
2101   {ARM_FEATURE_COPROC (FPU_MVE),
2102    MVE_VBIC_IMM,
2103    0xef800070, 0xefb81070,
2104    "vbic%v.i%8-11s\t%13-15,22Q, %E"},
2105
2106   /* Vector VBIC register.  */
2107   {ARM_FEATURE_COPROC (FPU_MVE),
2108    MVE_VBIC_REG,
2109    0xef100150, 0xffb11f51,
2110    "vbic%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2111
2112   /* Vector VABAV.  */
2113   {ARM_FEATURE_COPROC (FPU_MVE),
2114    MVE_VABAV,
2115    0xee800f01, 0xefc10f51,
2116    "vabav%v.%u%20-21s\t%12-15r, %17-19,7Q, %1-3,5Q"},
2117
2118   /* Vector VABD floating point.  */
2119   {ARM_FEATURE_COPROC (FPU_MVE_FP),
2120    MVE_VABD_FP,
2121    0xff200d40, 0xffa11f51,
2122    "vabd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2123
2124   /* Vector VABD.  */
2125   {ARM_FEATURE_COPROC (FPU_MVE),
2126    MVE_VABD_VEC,
2127    0xef000740, 0xef811f51,
2128    "vabd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2129
2130   /* Vector VABS floating point.  */
2131   {ARM_FEATURE_COPROC (FPU_MVE_FP),
2132    MVE_VABS_FP,
2133    0xFFB10740, 0xFFB31FD1,
2134    "vabs%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
2135   /* Vector VABS.  */
2136   {ARM_FEATURE_COPROC (FPU_MVE),
2137    MVE_VABS_VEC,
2138    0xffb10340, 0xffb31fd1,
2139    "vabs%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2140
2141   /* Vector VADD floating point T1.  */
2142   {ARM_FEATURE_COPROC (FPU_MVE_FP),
2143    MVE_VADD_FP_T1,
2144    0xef000d40, 0xffa11f51,
2145    "vadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2146   /* Vector VADD floating point T2.  */
2147   {ARM_FEATURE_COPROC (FPU_MVE_FP),
2148    MVE_VADD_FP_T2,
2149    0xee300f40, 0xefb11f70,
2150    "vadd%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2151   /* Vector VADD T1.  */
2152   {ARM_FEATURE_COPROC (FPU_MVE),
2153    MVE_VADD_VEC_T1,
2154    0xef000840, 0xff811f51,
2155    "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2156   /* Vector VADD T2.  */
2157   {ARM_FEATURE_COPROC (FPU_MVE),
2158    MVE_VADD_VEC_T2,
2159    0xee010f40, 0xff811f70,
2160    "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2161
2162   /* Vector VADDLV.  */
2163   {ARM_FEATURE_COPROC (FPU_MVE),
2164    MVE_VADDLV,
2165    0xee890f00, 0xef8f1fd1,
2166    "vaddlv%5A%v.%u32\t%13-15l, %20-22h, %1-3Q"},
2167
2168   /* Vector VADDV.  */
2169   {ARM_FEATURE_COPROC (FPU_MVE),
2170    MVE_VADDV,
2171    0xeef10f00, 0xeff31fd1,
2172    "vaddv%5A%v.%u%18-19s\t%13-15l, %1-3Q"},
2173
2174   /* Vector VADC.  */
2175   {ARM_FEATURE_COPROC (FPU_MVE),
2176    MVE_VADC,
2177    0xee300f00, 0xffb10f51,
2178    "vadc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2179
2180   /* Vector VAND.  */
2181   {ARM_FEATURE_COPROC (FPU_MVE),
2182    MVE_VAND,
2183    0xef000150, 0xffb11f51,
2184    "vand%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2185
2186   /* Vector VBRSR register.  */
2187   {ARM_FEATURE_COPROC (FPU_MVE),
2188    MVE_VBRSR,
2189    0xfe011e60, 0xff811f70,
2190    "vbrsr%v.%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2191
2192   /* Vector VCADD floating point.  */
2193   {ARM_FEATURE_COPROC (FPU_MVE_FP),
2194    MVE_VCADD_FP,
2195    0xfc800840, 0xfea11f51,
2196    "vcadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%24o"},
2197
2198   /* Vector VCADD.  */
2199   {ARM_FEATURE_COPROC (FPU_MVE),
2200    MVE_VCADD_VEC,
2201    0xfe000f00, 0xff810f51,
2202    "vcadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
2203
2204   /* Vector VCLS.  */
2205   {ARM_FEATURE_COPROC (FPU_MVE),
2206    MVE_VCLS,
2207    0xffb00440, 0xffb31fd1,
2208    "vcls%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2209
2210   /* Vector VCLZ.  */
2211   {ARM_FEATURE_COPROC (FPU_MVE),
2212    MVE_VCLZ,
2213    0xffb004c0, 0xffb31fd1,
2214    "vclz%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2215
2216   /* Vector VCMLA.  */
2217   {ARM_FEATURE_COPROC (FPU_MVE_FP),
2218    MVE_VCMLA_FP,
2219    0xfc200840, 0xfe211f51,
2220    "vcmla%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%23-24o"},
2221
2222   /* Vector VCMP floating point T1.  */
2223   {ARM_FEATURE_COPROC (FPU_MVE_FP),
2224    MVE_VCMP_FP_T1,
2225    0xee310f00, 0xeff1ef50,
2226    "vcmp%v.f%28s\t%n, %17-19Q, %1-3,5Q"},
2227
2228   /* Vector VCMP floating point T2.  */
2229   {ARM_FEATURE_COPROC (FPU_MVE_FP),
2230    MVE_VCMP_FP_T2,
2231    0xee310f40, 0xeff1ef50,
2232    "vcmp%v.f%28s\t%n, %17-19Q, %0-3Z"},
2233
2234   /* Vector VCMP T1.  */
2235   {ARM_FEATURE_COPROC (FPU_MVE),
2236    MVE_VCMP_VEC_T1,
2237    0xfe010f00, 0xffc1ff51,
2238    "vcmp%v.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2239   /* Vector VCMP T2.  */
2240   {ARM_FEATURE_COPROC (FPU_MVE),
2241    MVE_VCMP_VEC_T2,
2242    0xfe010f01, 0xffc1ff51,
2243    "vcmp%v.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2244   /* Vector VCMP T3.  */
2245   {ARM_FEATURE_COPROC (FPU_MVE),
2246    MVE_VCMP_VEC_T3,
2247    0xfe011f00, 0xffc1ff50,
2248    "vcmp%v.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2249   /* Vector VCMP T4.  */
2250   {ARM_FEATURE_COPROC (FPU_MVE),
2251    MVE_VCMP_VEC_T4,
2252    0xfe010f40, 0xffc1ff70,
2253    "vcmp%v.i%20-21s\t%n, %17-19Q, %0-3Z"},
2254   /* Vector VCMP T5.  */
2255   {ARM_FEATURE_COPROC (FPU_MVE),
2256    MVE_VCMP_VEC_T5,
2257    0xfe010f60, 0xffc1ff70,
2258    "vcmp%v.u%20-21s\t%n, %17-19Q, %0-3Z"},
2259   /* Vector VCMP T6.  */
2260   {ARM_FEATURE_COPROC (FPU_MVE),
2261    MVE_VCMP_VEC_T6,
2262    0xfe011f40, 0xffc1ff50,
2263    "vcmp%v.s%20-21s\t%n, %17-19Q, %0-3Z"},
2264
2265   /* Vector VDUP.  */
2266   {ARM_FEATURE_COPROC (FPU_MVE),
2267    MVE_VDUP,
2268    0xeea00b10, 0xffb10f5f,
2269    "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2270
2271   /* Vector VEOR.  */
2272   {ARM_FEATURE_COPROC (FPU_MVE),
2273    MVE_VEOR,
2274    0xff000150, 0xffd11f51,
2275    "veor%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2276
2277   /* Vector VFMA, vector * scalar.  */
2278   {ARM_FEATURE_COPROC (FPU_MVE_FP),
2279    MVE_VFMA_FP_SCALAR,
2280    0xee310e40, 0xefb11f70,
2281    "vfma%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2282
2283   /* Vector VFMA floating point.  */
2284   {ARM_FEATURE_COPROC (FPU_MVE_FP),
2285    MVE_VFMA_FP,
2286    0xef000c50, 0xffa11f51,
2287    "vfma%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2288
2289   /* Vector VFMS floating point.  */
2290   {ARM_FEATURE_COPROC (FPU_MVE_FP),
2291    MVE_VFMS_FP,
2292    0xef200c50, 0xffa11f51,
2293    "vfms%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2294
2295   /* Vector VFMAS, vector * scalar.  */
2296   {ARM_FEATURE_COPROC (FPU_MVE_FP),
2297    MVE_VFMAS_FP_SCALAR,
2298    0xee311e40, 0xefb11f70,
2299    "vfmas%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2300
2301   /* Vector VHADD T1.  */
2302   {ARM_FEATURE_COPROC (FPU_MVE),
2303    MVE_VHADD_T1,
2304    0xef000040, 0xef811f51,
2305    "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2306
2307   /* Vector VHADD T2.  */
2308   {ARM_FEATURE_COPROC (FPU_MVE),
2309    MVE_VHADD_T2,
2310    0xee000f40, 0xef811f70,
2311    "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2312
2313   /* Vector VHSUB T1.  */
2314   {ARM_FEATURE_COPROC (FPU_MVE),
2315    MVE_VHSUB_T1,
2316    0xef000240, 0xef811f51,
2317    "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2318
2319   /* Vector VHSUB T2.  */
2320   {ARM_FEATURE_COPROC (FPU_MVE),
2321    MVE_VHSUB_T2,
2322    0xee001f40, 0xef811f70,
2323    "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2324
2325   /* Vector VCMUL.  */
2326   {ARM_FEATURE_COPROC (FPU_MVE_FP),
2327    MVE_VCMUL_FP,
2328    0xee300e00, 0xefb10f50,
2329    "vcmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%0,12o"},
2330
2331    /* Vector VCTP.  */
2332   {ARM_FEATURE_COPROC (FPU_MVE),
2333    MVE_VCTP,
2334    0xf000e801, 0xffc0ffff,
2335    "vctp%v.%20-21s\t%16-19r"},
2336
2337   /* Vector VDUP.  */
2338   {ARM_FEATURE_COPROC (FPU_MVE),
2339    MVE_VDUP,
2340    0xeea00b10, 0xffb10f5f,
2341    "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2342
2343   /* Vector VRHADD.  */
2344   {ARM_FEATURE_COPROC (FPU_MVE),
2345    MVE_VRHADD,
2346    0xef000140, 0xef811f51,
2347    "vrhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2348
2349   /* Vector VCVT.  */
2350   {ARM_FEATURE_COPROC (FPU_MVE_FP),
2351    MVE_VCVT_FP_FIX_VEC,
2352    0xef800c50, 0xef801cd1,
2353    "vcvt%v.%s\t%13-15,22Q, %1-3,5Q, #%16-21k"},
2354
2355   /* Vector VCVT.  */
2356   {ARM_FEATURE_COPROC (FPU_MVE_FP),
2357    MVE_VCVT_BETWEEN_FP_INT,
2358    0xffb30640, 0xffb31e51,
2359    "vcvt%v.%s\t%13-15,22Q, %1-3,5Q"},
2360
2361   /* Vector VCVT between single and half-precision float, bottom half.  */
2362   {ARM_FEATURE_COPROC (FPU_MVE_FP),
2363    MVE_VCVT_FP_HALF_FP,
2364    0xee3f0e01, 0xefbf1fd1,
2365    "vcvtb%v.%s\t%13-15,22Q, %1-3,5Q"},
2366
2367   /* Vector VCVT between single and half-precision float, top half.  */
2368   {ARM_FEATURE_COPROC (FPU_MVE_FP),
2369    MVE_VCVT_FP_HALF_FP,
2370    0xee3f1e01, 0xefbf1fd1,
2371    "vcvtt%v.%s\t%13-15,22Q, %1-3,5Q"},
2372
2373   /* Vector VCVT.  */
2374   {ARM_FEATURE_COPROC (FPU_MVE_FP),
2375    MVE_VCVT_FROM_FP_TO_INT,
2376    0xffb30040, 0xffb31c51,
2377    "vcvt%m%v.%s\t%13-15,22Q, %1-3,5Q"},
2378
2379   /* Vector VDDUP.  */
2380   {ARM_FEATURE_COPROC (FPU_MVE),
2381    MVE_VDDUP,
2382    0xee011f6e, 0xff811f7e,
2383    "vddup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
2384
2385   /* Vector VDWDUP.  */
2386   {ARM_FEATURE_COPROC (FPU_MVE),
2387    MVE_VDWDUP,
2388    0xee011f60, 0xff811f70,
2389    "vdwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
2390
2391   /* Vector VHCADD.  */
2392   {ARM_FEATURE_COPROC (FPU_MVE),
2393    MVE_VHCADD,
2394    0xee000f00, 0xff810f51,
2395    "vhcadd%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
2396
2397   /* Vector VIWDUP.  */
2398   {ARM_FEATURE_COPROC (FPU_MVE),
2399    MVE_VIWDUP,
2400    0xee010f60, 0xff811f70,
2401    "viwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
2402
2403   /* Vector VIDUP.  */
2404   {ARM_FEATURE_COPROC (FPU_MVE),
2405    MVE_VIDUP,
2406    0xee010f6e, 0xff811f7e,
2407    "vidup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
2408
2409   /* Vector VLD2.  */
2410   {ARM_FEATURE_COPROC (FPU_MVE),
2411    MVE_VLD2,
2412    0xfc901e00, 0xff901e5f,
2413    "vld2%5d.%7-8s\t%B, [%16-19r]%w"},
2414
2415   /* Vector VLD4.  */
2416   {ARM_FEATURE_COPROC (FPU_MVE),
2417    MVE_VLD4,
2418    0xfc901e01, 0xff901e1f,
2419    "vld4%5-6d.%7-8s\t%B, [%16-19r]%w"},
2420
2421   /* Vector VLDRB gather load.  */
2422   {ARM_FEATURE_COPROC (FPU_MVE),
2423    MVE_VLDRB_GATHER_T1,
2424    0xec900e00, 0xefb01e50,
2425    "vldrb%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
2426
2427   /* Vector VLDRH gather load.  */
2428   {ARM_FEATURE_COPROC (FPU_MVE),
2429    MVE_VLDRH_GATHER_T2,
2430    0xec900e10, 0xefb01e50,
2431    "vldrh%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2432
2433   /* Vector VLDRW gather load.  */
2434   {ARM_FEATURE_COPROC (FPU_MVE),
2435    MVE_VLDRW_GATHER_T3,
2436    0xfc900f40, 0xffb01fd0,
2437    "vldrw%v.u32\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2438
2439   /* Vector VLDRD gather load.  */
2440   {ARM_FEATURE_COPROC (FPU_MVE),
2441    MVE_VLDRD_GATHER_T4,
2442    0xec900fd0, 0xefb01fd0,
2443    "vldrd%v.u64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2444
2445   /* Vector VLDRW gather load.  */
2446   {ARM_FEATURE_COPROC (FPU_MVE),
2447    MVE_VLDRW_GATHER_T5,
2448    0xfd101e00, 0xff111f00,
2449    "vldrw%v.u32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2450
2451   /* Vector VLDRD gather load, variant T6.  */
2452   {ARM_FEATURE_COPROC (FPU_MVE),
2453    MVE_VLDRD_GATHER_T6,
2454    0xfd101f00, 0xff111f00,
2455    "vldrd%v.u64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2456
2457   /* Vector VLDRB.  */
2458   {ARM_FEATURE_COPROC (FPU_MVE),
2459    MVE_VLDRB_T1,
2460    0xec100e00, 0xee581e00,
2461    "vldrb%v.%u%7-8s\t%13-15Q, %d"},
2462
2463   /* Vector VLDRH.  */
2464   {ARM_FEATURE_COPROC (FPU_MVE),
2465    MVE_VLDRH_T2,
2466    0xec180e00, 0xee581e00,
2467    "vldrh%v.%u%7-8s\t%13-15Q, %d"},
2468
2469   /* Vector VLDRB unsigned, variant T5.  */
2470   {ARM_FEATURE_COPROC (FPU_MVE),
2471    MVE_VLDRB_T5,
2472    0xec101e00, 0xfe101f80,
2473    "vldrb%v.u8\t%13-15,22Q, %d"},
2474
2475   /* Vector VLDRH unsigned, variant T6.  */
2476   {ARM_FEATURE_COPROC (FPU_MVE),
2477    MVE_VLDRH_T6,
2478    0xec101e80, 0xfe101f80,
2479    "vldrh%v.u16\t%13-15,22Q, %d"},
2480
2481   /* Vector VLDRW unsigned, variant T7.  */
2482   {ARM_FEATURE_COPROC (FPU_MVE),
2483    MVE_VLDRW_T7,
2484    0xec101f00, 0xfe101f80,
2485    "vldrw%v.u32\t%13-15,22Q, %d"},
2486
2487   /* Vector VMAX.  */
2488   {ARM_FEATURE_COPROC (FPU_MVE),
2489    MVE_VMAX,
2490    0xef000640, 0xef811f51,
2491    "vmax%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2492
2493   /* Vector VMAXA.  */
2494   {ARM_FEATURE_COPROC (FPU_MVE),
2495    MVE_VMAXA,
2496    0xee330e81, 0xffb31fd1,
2497    "vmaxa%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2498
2499   /* Vector VMAXNM floating point.  */
2500   {ARM_FEATURE_COPROC (FPU_MVE_FP),
2501    MVE_VMAXNM_FP,
2502    0xff000f50, 0xffa11f51,
2503    "vmaxnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2504
2505   /* Vector VMAXNMA floating point.  */
2506   {ARM_FEATURE_COPROC (FPU_MVE_FP),
2507    MVE_VMAXNMA_FP,
2508    0xee3f0e81, 0xefbf1fd1,
2509    "vmaxnma%v.f%28s\t%13-15,22Q, %1-3,5Q"},
2510
2511   /* Vector VMAXNMV floating point.  */
2512   {ARM_FEATURE_COPROC (FPU_MVE_FP),
2513    MVE_VMAXNMV_FP,
2514    0xeeee0f00, 0xefff0fd1,
2515    "vmaxnmv%v.f%28s\t%12-15r, %1-3,5Q"},
2516
2517   /* Vector VMAXNMAV floating point.  */
2518   {ARM_FEATURE_COPROC (FPU_MVE_FP),
2519    MVE_VMAXNMAV_FP,
2520    0xeeec0f00, 0xefff0fd1,
2521    "vmaxnmav%v.f%28s\t%12-15r, %1-3,5Q"},
2522
2523   /* Vector VMAXV.  */
2524   {ARM_FEATURE_COPROC (FPU_MVE),
2525    MVE_VMAXV,
2526    0xeee20f00, 0xeff30fd1,
2527    "vmaxv%v.%u%18-19s\t%12-15r, %1-3,5Q"},
2528
2529   /* Vector VMAXAV.  */
2530   {ARM_FEATURE_COPROC (FPU_MVE),
2531    MVE_VMAXAV,
2532    0xeee00f00, 0xfff30fd1,
2533    "vmaxav%v.s%18-19s\t%12-15r, %1-3,5Q"},
2534
2535   /* Vector VMIN.  */
2536   {ARM_FEATURE_COPROC (FPU_MVE),
2537    MVE_VMIN,
2538    0xef000650, 0xef811f51,
2539    "vmin%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2540
2541   /* Vector VMINA.  */
2542   {ARM_FEATURE_COPROC (FPU_MVE),
2543    MVE_VMINA,
2544    0xee331e81, 0xffb31fd1,
2545    "vmina%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2546
2547   /* Vector VMINNM floating point.  */
2548   {ARM_FEATURE_COPROC (FPU_MVE_FP),
2549    MVE_VMINNM_FP,
2550    0xff200f50, 0xffa11f51,
2551    "vminnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2552
2553   /* Vector VMINNMA floating point.  */
2554   {ARM_FEATURE_COPROC (FPU_MVE_FP),
2555    MVE_VMINNMA_FP,
2556    0xee3f1e81, 0xefbf1fd1,
2557    "vminnma%v.f%28s\t%13-15,22Q, %1-3,5Q"},
2558
2559   /* Vector VMINNMV floating point.  */
2560   {ARM_FEATURE_COPROC (FPU_MVE_FP),
2561    MVE_VMINNMV_FP,
2562    0xeeee0f80, 0xefff0fd1,
2563    "vminnmv%v.f%28s\t%12-15r, %1-3,5Q"},
2564
2565   /* Vector VMINNMAV floating point.  */
2566   {ARM_FEATURE_COPROC (FPU_MVE_FP),
2567    MVE_VMINNMAV_FP,
2568    0xeeec0f80, 0xefff0fd1,
2569    "vminnmav%v.f%28s\t%12-15r, %1-3,5Q"},
2570
2571   /* Vector VMINV.  */
2572   {ARM_FEATURE_COPROC (FPU_MVE),
2573    MVE_VMINV,
2574    0xeee20f80, 0xeff30fd1,
2575    "vminv%v.%u%18-19s\t%12-15r, %1-3,5Q"},
2576
2577   /* Vector VMINAV.  */
2578   {ARM_FEATURE_COPROC (FPU_MVE),
2579    MVE_VMINAV,
2580    0xeee00f80, 0xfff30fd1,
2581    "vminav%v.s%18-19s\t%12-15r, %1-3,5Q"},
2582
2583   /* Vector VMLA.  */
2584   {ARM_FEATURE_COPROC (FPU_MVE),
2585    MVE_VMLA,
2586    0xee010e40, 0xef811f70,
2587    "vmla%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2588
2589   /* Vector VMLALDAV.  Note must appear before VMLADAV due to instruction
2590      opcode aliasing.  */
2591   {ARM_FEATURE_COPROC (FPU_MVE),
2592    MVE_VMLALDAV,
2593    0xee801e00, 0xef801f51,
2594    "vmlaldav%5Ax%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2595
2596   {ARM_FEATURE_COPROC (FPU_MVE),
2597    MVE_VMLALDAV,
2598    0xee800e00, 0xef801f51,
2599    "vmlalv%5A%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2600
2601   /* Vector VMLAV T1 variant, same as VMLADAV but with X == 0.  */
2602   {ARM_FEATURE_COPROC (FPU_MVE),
2603    MVE_VMLADAV_T1,
2604    0xeef00e00, 0xeff01f51,
2605    "vmlav%5A%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2606
2607   /* Vector VMLAV T2 variant, same as VMLADAV but with X == 0.  */
2608   {ARM_FEATURE_COPROC (FPU_MVE),
2609    MVE_VMLADAV_T2,
2610    0xeef00f00, 0xeff11f51,
2611    "vmlav%5A%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2612
2613   /* Vector VMLADAV T1 variant.  */
2614   {ARM_FEATURE_COPROC (FPU_MVE),
2615    MVE_VMLADAV_T1,
2616    0xeef01e00, 0xeff01f51,
2617    "vmladav%5Ax%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2618
2619   /* Vector VMLADAV T2 variant.  */
2620   {ARM_FEATURE_COPROC (FPU_MVE),
2621    MVE_VMLADAV_T2,
2622    0xeef01f00, 0xeff11f51,
2623    "vmladav%5Ax%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2624
2625   /* Vector VMLAS.  */
2626   {ARM_FEATURE_COPROC (FPU_MVE),
2627    MVE_VMLAS,
2628    0xee011e40, 0xef811f70,
2629    "vmlas%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2630
2631   /* Vector VRMLSLDAVH.  Note must appear before VMLSDAV due to instruction
2632      opcode aliasing.  */
2633   {ARM_FEATURE_COPROC (FPU_MVE),
2634    MVE_VRMLSLDAVH,
2635    0xfe800e01, 0xff810f51,
2636    "vrmlsldavh%5A%X%v.s32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2637
2638   /* Vector VMLSLDAV.  Note must appear before VMLSDAV due to instruction
2639      opcdoe aliasing.  */
2640   {ARM_FEATURE_COPROC (FPU_MVE),
2641    MVE_VMLSLDAV,
2642    0xee800e01, 0xff800f51,
2643    "vmlsldav%5A%X%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2644
2645   /* Vector VMLSDAV T1 Variant.  */
2646   {ARM_FEATURE_COPROC (FPU_MVE),
2647    MVE_VMLSDAV_T1,
2648    0xeef00e01, 0xfff00f51,
2649    "vmlsdav%5A%X%v.s%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2650
2651   /* Vector VMLSDAV T2 Variant.  */
2652   {ARM_FEATURE_COPROC (FPU_MVE),
2653    MVE_VMLSDAV_T2,
2654    0xfef00e01, 0xfff10f51,
2655    "vmlsdav%5A%X%v.s8\t%13-15l, %17-19,7Q, %1-3Q"},
2656
2657   /* Vector VMOV between gpr and half precision register, op == 0.  */
2658   {ARM_FEATURE_COPROC (FPU_MVE_FP),
2659    MVE_VMOV_HFP_TO_GP,
2660    0xee000910, 0xfff00f7f,
2661    "vmov.f16\t%7,16-19F, %12-15r"},
2662
2663   /* Vector VMOV between gpr and half precision register, op == 1.  */
2664   {ARM_FEATURE_COPROC (FPU_MVE_FP),
2665    MVE_VMOV_HFP_TO_GP,
2666    0xee100910, 0xfff00f7f,
2667    "vmov.f16\t%12-15r, %7,16-19F"},
2668
2669   {ARM_FEATURE_COPROC (FPU_MVE_FP),
2670    MVE_VMOV_GP_TO_VEC_LANE,
2671    0xee000b10, 0xff900f1f,
2672    "vmov%c.%5-6,21-22s\t%17-19,7Q[%N], %12-15r"},
2673
2674   /* Vector VORR immediate to vector.
2675      NOTE: MVE_VORR_IMM must appear in the table
2676      before MVE_VMOV_IMM_TO_VEC due to opcode aliasing.  */
2677   {ARM_FEATURE_COPROC (FPU_MVE),
2678    MVE_VORR_IMM,
2679    0xef800050, 0xefb810f0,
2680    "vorr%v.i%8-11s\t%13-15,22Q, %E"},
2681
2682   /* Vector VQSHL T2 Variant.
2683      NOTE: MVE_VQSHL_T2 must appear in the table before
2684      before MVE_VMOV_IMM_TO_VEC due to opcode aliasing.  */
2685   {ARM_FEATURE_COPROC (FPU_MVE),
2686    MVE_VQSHL_T2,
2687    0xef800750, 0xef801fd1,
2688    "vqshl%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2689
2690   /* Vector VQSHLU T3 Variant
2691      NOTE: MVE_VQSHL_T2 must appear in the table before
2692      before MVE_VMOV_IMM_TO_VEC due to opcode aliasing.  */
2693
2694   {ARM_FEATURE_COPROC (FPU_MVE),
2695    MVE_VQSHLU_T3,
2696    0xff800650, 0xff801fd1,
2697    "vqshlu%v.s%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2698
2699   /* Vector VRSHR
2700      NOTE: MVE_VRSHR must appear in the table before
2701      before MVE_VMOV_IMM_TO_VEC due to opcode aliasing.  */
2702   {ARM_FEATURE_COPROC (FPU_MVE),
2703    MVE_VRSHR,
2704    0xef800250, 0xef801fd1,
2705    "vrshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2706
2707   /* Vector VSHL.
2708      NOTE: MVE_VSHL must appear in the table before
2709      before MVE_VMOV_IMM_TO_VEC due to opcode aliasing.  */
2710   {ARM_FEATURE_COPROC (FPU_MVE),
2711    MVE_VSHL_T1,
2712    0xef800550, 0xff801fd1,
2713    "vshl%v.i%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2714
2715   /* Vector VSHR
2716      NOTE: MVE_VSHR must appear in the table before
2717      before MVE_VMOV_IMM_TO_VEC due to opcode aliasing.  */
2718   {ARM_FEATURE_COPROC (FPU_MVE),
2719    MVE_VSHR,
2720    0xef800050, 0xef801fd1,
2721    "vshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2722
2723   /* Vector VSLI
2724      NOTE: MVE_VSLI must appear in the table before
2725      before MVE_VMOV_IMM_TO_VEC due to opcode aliasing.  */
2726   {ARM_FEATURE_COPROC (FPU_MVE),
2727    MVE_VSLI,
2728    0xff800550, 0xff801fd1,
2729    "vsli%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2730
2731   /* Vector VSRI
2732      NOTE: MVE_VSRI must appear in the table before
2733      before MVE_VMOV_IMM_TO_VEC due to opcode aliasing.  */
2734   {ARM_FEATURE_COPROC (FPU_MVE),
2735    MVE_VSRI,
2736    0xff800450, 0xff801fd1,
2737    "vsri%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2738
2739   /* Vector VMOV immediate to vector,
2740      cmode == 11x1 -> VMVN which is UNDEFINED
2741      for such a cmode.  */
2742   {ARM_FEATURE_COPROC (FPU_MVE),
2743    MVE_VMVN_IMM, 0xef800d50, 0xefb81dd0, UNDEFINED_INSTRUCTION},
2744
2745   /* Vector VMOV immediate to vector.  */
2746   {ARM_FEATURE_COPROC (FPU_MVE),
2747    MVE_VMOV_IMM_TO_VEC,
2748    0xef800050, 0xefb810d0,
2749    "vmov%v.%5,8-11s\t%13-15,22Q, %E"},
2750
2751   /* Vector VMOV two 32-bit lanes to two gprs, idx = 0.  */
2752   {ARM_FEATURE_COPROC (FPU_MVE),
2753    MVE_VMOV2_VEC_LANE_TO_GP,
2754    0xec000f00, 0xffb01ff0,
2755    "vmov%c\t%0-3r, %16-19r, %13-15,22Q[2], %13-15,22Q[0]"},
2756
2757   /* Vector VMOV two 32-bit lanes to two gprs, idx = 1.  */
2758   {ARM_FEATURE_COPROC (FPU_MVE),
2759    MVE_VMOV2_VEC_LANE_TO_GP,
2760    0xec000f10, 0xffb01ff0,
2761    "vmov%c\t%0-3r, %16-19r, %13-15,22Q[3], %13-15,22Q[1]"},
2762
2763   /* Vector VMOV Two gprs to two 32-bit lanes, idx = 0.  */
2764   {ARM_FEATURE_COPROC (FPU_MVE),
2765    MVE_VMOV2_GP_TO_VEC_LANE,
2766    0xec100f00, 0xffb01ff0,
2767    "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
2768
2769   /* Vector VMOV Two gprs to two 32-bit lanes, idx = 1.  */
2770   {ARM_FEATURE_COPROC (FPU_MVE),
2771    MVE_VMOV2_GP_TO_VEC_LANE,
2772    0xec100f10, 0xffb01ff0,
2773    "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
2774
2775   /* Vector VMOV Vector lane to gpr.  */
2776   {ARM_FEATURE_COPROC (FPU_MVE_FP),
2777    MVE_VMOV_VEC_LANE_TO_GP,
2778    0xee100b10, 0xff100f1f,
2779    "vmov%c.%u%5-6,21-22s\t%12-15r, %17-19,7Q[%N]"},
2780
2781   /* Vector VSHLL T1 Variant.  Note: VSHLL T1 must appear before MVE_VMOVL due
2782      to instruction opcode aliasing.  */
2783   {ARM_FEATURE_COPROC (FPU_MVE),
2784    MVE_VSHLL_T1,
2785    0xeea00f40, 0xefa00fd1,
2786    "vshll%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2787
2788   /* Vector VMOVL long.  */
2789   {ARM_FEATURE_COPROC (FPU_MVE),
2790    MVE_VMOVL,
2791    0xeea00f40, 0xefa70fd1,
2792    "vmovl%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q"},
2793
2794   /* Vector VMOV and narrow.  */
2795   {ARM_FEATURE_COPROC (FPU_MVE),
2796    MVE_VMOVN,
2797    0xfe310e81, 0xffb30fd1,
2798    "vmovn%T%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2799
2800   /* Floating point move extract.  */
2801   {ARM_FEATURE_COPROC (FPU_MVE_FP),
2802    MVE_VMOVX,
2803    0xfeb00a40, 0xffbf0fd0,
2804    "vmovx.f16\t%22,12-15F, %5,0-3F"},
2805
2806   /* Vector VMUL floating-point T1 variant.  */
2807   {ARM_FEATURE_COPROC (FPU_MVE_FP),
2808    MVE_VMUL_FP_T1,
2809    0xff000d50, 0xffa11f51,
2810    "vmul%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2811
2812   /* Vector VMUL floating-point T2 variant.  */
2813   {ARM_FEATURE_COPROC (FPU_MVE_FP),
2814    MVE_VMUL_FP_T2,
2815    0xee310e60, 0xefb11f70,
2816    "vmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2817
2818   /* Vector VMUL T1 variant.  */
2819   {ARM_FEATURE_COPROC (FPU_MVE),
2820    MVE_VMUL_VEC_T1,
2821    0xef000950, 0xff811f51,
2822    "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2823
2824   /* Vector VMUL T2 variant.  */
2825   {ARM_FEATURE_COPROC (FPU_MVE),
2826    MVE_VMUL_VEC_T2,
2827    0xee011e60, 0xff811f70,
2828    "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2829
2830   /* Vector VMULH.  */
2831   {ARM_FEATURE_COPROC (FPU_MVE),
2832    MVE_VMULH,
2833    0xee010e01, 0xef811f51,
2834    "vmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2835
2836   /* Vector VRMULH.  */
2837   {ARM_FEATURE_COPROC (FPU_MVE),
2838    MVE_VRMULH,
2839    0xee011e01, 0xef811f51,
2840    "vrmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2841
2842   /* Vector VMULL integer.  */
2843   {ARM_FEATURE_COPROC (FPU_MVE),
2844    MVE_VMULL_INT,
2845    0xee010e00, 0xef810f51,
2846    "vmull%T%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2847
2848   /* Vector VMULL polynomial.  */
2849   {ARM_FEATURE_COPROC (FPU_MVE),
2850    MVE_VMULL_POLY,
2851    0xee310e00, 0xefb10f51,
2852    "vmull%T%v.%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2853
2854   /* Vector VMVN immediate to vector.  */
2855   {ARM_FEATURE_COPROC (FPU_MVE),
2856    MVE_VMVN_IMM,
2857    0xef800070, 0xefb810f0,
2858    "vmvn%v.i%8-11s\t%13-15,22Q, %E"},
2859
2860   /* Vector VMVN register.  */
2861   {ARM_FEATURE_COPROC (FPU_MVE),
2862    MVE_VMVN_REG,
2863    0xffb005c0, 0xffbf1fd1,
2864    "vmvn%v\t%13-15,22Q, %1-3,5Q"},
2865
2866   /* Vector VNEG floating point.  */
2867   {ARM_FEATURE_COPROC (FPU_MVE_FP),
2868    MVE_VNEG_FP,
2869    0xffb107c0, 0xffb31fd1,
2870    "vneg%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
2871
2872   /* Vector VNEG.  */
2873   {ARM_FEATURE_COPROC (FPU_MVE),
2874    MVE_VNEG_VEC,
2875    0xffb103c0, 0xffb31fd1,
2876    "vneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2877
2878   /* Vector VORN, vector bitwise or not.  */
2879   {ARM_FEATURE_COPROC (FPU_MVE),
2880    MVE_VORN,
2881    0xef300150, 0xffb11f51,
2882    "vorn%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2883
2884   /* Vector VORR register.  */
2885   {ARM_FEATURE_COPROC (FPU_MVE),
2886    MVE_VORR_REG,
2887    0xef200150, 0xffb11f51,
2888    "vorr%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2889
2890   /* Vector VQDMULL T1 variant.  */
2891   {ARM_FEATURE_COPROC (FPU_MVE),
2892    MVE_VQDMULL_T1,
2893    0xee300f01, 0xefb10f51,
2894    "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2895
2896   /* Vector VQDMULL T2 variant.  */
2897   {ARM_FEATURE_COPROC (FPU_MVE),
2898    MVE_VQDMULL_T2,
2899    0xee300f60, 0xefb10f70,
2900    "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2901
2902   /* Vector VQMOVN.  */
2903   {ARM_FEATURE_COPROC (FPU_MVE),
2904    MVE_VQMOVN,
2905    0xee330e01, 0xefb30fd1,
2906    "vqmovn%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q"},
2907
2908   /* Vector VQMOVUN.  */
2909   {ARM_FEATURE_COPROC (FPU_MVE),
2910    MVE_VQMOVUN,
2911    0xee310e81, 0xffb30fd1,
2912    "vqmovun%T%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2913
2914   /* Vector VQDMLADH.  */
2915   {ARM_FEATURE_COPROC (FPU_MVE),
2916    MVE_VQDMLADH,
2917    0xee000e00, 0xff810f51,
2918    "vqdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2919
2920   /* Vector VQRDMLADH.  */
2921   {ARM_FEATURE_COPROC (FPU_MVE),
2922    MVE_VQRDMLADH,
2923    0xee000e01, 0xff810f51,
2924    "vqrdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2925
2926   /* Vector VQDMLAH.  */
2927   {ARM_FEATURE_COPROC (FPU_MVE),
2928    MVE_VQDMLAH,
2929    0xee000e60, 0xef811f70,
2930    "vqdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2931
2932   /* Vector VQRDMLAH.  */
2933   {ARM_FEATURE_COPROC (FPU_MVE),
2934    MVE_VQRDMLAH,
2935    0xee000e40, 0xef811f70,
2936    "vqrdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2937
2938   /* Vector VQDMLASH.  */
2939   {ARM_FEATURE_COPROC (FPU_MVE),
2940    MVE_VQDMLASH,
2941    0xee001e60, 0xef811f70,
2942    "vqdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2943
2944   /* Vector VQRDMLASH.  */
2945   {ARM_FEATURE_COPROC (FPU_MVE),
2946    MVE_VQRDMLASH,
2947    0xee001e40, 0xef811f70,
2948    "vqrdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2949
2950   /* Vector VQDMLSDH.  */
2951   {ARM_FEATURE_COPROC (FPU_MVE),
2952    MVE_VQDMLSDH,
2953    0xfe000e00, 0xff810f51,
2954    "vqdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2955
2956   /* Vector VQRDMLSDH.  */
2957   {ARM_FEATURE_COPROC (FPU_MVE),
2958    MVE_VQRDMLSDH,
2959    0xfe000e01, 0xff810f51,
2960    "vqrdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2961
2962   /* Vector VQDMULH T1 variant.  */
2963   {ARM_FEATURE_COPROC (FPU_MVE),
2964    MVE_VQDMULH_T1,
2965    0xef000b40, 0xff811f51,
2966    "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2967
2968   /* Vector VQRDMULH T2 variant.  */
2969   {ARM_FEATURE_COPROC (FPU_MVE),
2970    MVE_VQRDMULH_T2,
2971    0xff000b40, 0xff811f51,
2972    "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2973
2974   /* Vector VQDMULH T3 variant.  */
2975   {ARM_FEATURE_COPROC (FPU_MVE),
2976    MVE_VQDMULH_T3,
2977    0xee010e60, 0xff811f70,
2978    "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2979
2980   /* Vector VQRDMULH T4 variant.  */
2981   {ARM_FEATURE_COPROC (FPU_MVE),
2982    MVE_VQRDMULH_T4,
2983    0xfe010e60, 0xff811f70,
2984    "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2985
2986   /* Vector VQRSHL T1 variant.  */
2987   {ARM_FEATURE_COPROC (FPU_MVE),
2988    MVE_VQRSHL_T1,
2989    0xef000550, 0xef811f51,
2990    "vqrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
2991
2992   /* Vector VQRSHL T2 variant.  */
2993   {ARM_FEATURE_COPROC (FPU_MVE),
2994    MVE_VQRSHL_T2,
2995    0xee331ee0, 0xefb31ff0,
2996    "vqrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
2997
2998   /* Vector VQRSHRN.  */
2999   {ARM_FEATURE_COPROC (FPU_MVE),
3000    MVE_VQRSHRN,
3001    0xee800f41, 0xefa00fd1,
3002    "vqrshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3003
3004   /* Vector VQRSHRUN.  */
3005   {ARM_FEATURE_COPROC (FPU_MVE),
3006    MVE_VQRSHRUN,
3007    0xfe800fc0, 0xffa00fd1,
3008    "vqrshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3009
3010   /* Vector VQSHL T1 Variant.  */
3011   {ARM_FEATURE_COPROC (FPU_MVE),
3012    MVE_VQSHL_T1,
3013    0xee311ee0, 0xefb31ff0,
3014    "vqshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3015
3016   /* Vector VQSHL T4 Variant.  */
3017   {ARM_FEATURE_COPROC (FPU_MVE),
3018    MVE_VQSHL_T4,
3019    0xef000450, 0xef811f51,
3020    "vqshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3021
3022   /* Vector VQSHRN.  */
3023   {ARM_FEATURE_COPROC (FPU_MVE),
3024    MVE_VQSHRN,
3025    0xee800f40, 0xefa00fd1,
3026    "vqshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3027
3028   /* Vector VQSHRUN.  */
3029   {ARM_FEATURE_COPROC (FPU_MVE),
3030    MVE_VQSHRUN,
3031    0xee800fc0, 0xffa00fd1,
3032    "vqshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3033
3034   /* Vector VRINT floating point.  */
3035   {ARM_FEATURE_COPROC (FPU_MVE_FP),
3036    MVE_VRINT_FP,
3037    0xffb20440, 0xffb31c51,
3038    "vrint%m%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
3039
3040   /* Vector VRMLALDAVH.  */
3041   {ARM_FEATURE_COPROC (FPU_MVE),
3042    MVE_VRMLALDAVH,
3043    0xee800f00, 0xef811f51,
3044    "vrmlalvh%5A%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
3045
3046   /* Vector VRMLALDAVH.  */
3047   {ARM_FEATURE_COPROC (FPU_MVE),
3048    MVE_VRMLALDAVH,
3049    0xee801f00, 0xef811f51,
3050    "vrmlaldavh%5Ax%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
3051
3052   /* Vector VRSHL T1 Variant.  */
3053   {ARM_FEATURE_COPROC (FPU_MVE),
3054    MVE_VRSHL_T1,
3055    0xef000540, 0xef811f51,
3056    "vrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3057
3058   /* Vector VRSHL T2 Variant.  */
3059   {ARM_FEATURE_COPROC (FPU_MVE),
3060    MVE_VRSHL_T2,
3061    0xee331e60, 0xefb31ff0,
3062    "vrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3063
3064   /* Vector VRSHRN.  */
3065   {ARM_FEATURE_COPROC (FPU_MVE),
3066    MVE_VRSHRN,
3067    0xfe800fc1, 0xffa00fd1,
3068    "vrshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3069
3070   /* Vector VSBC.  */
3071   {ARM_FEATURE_COPROC (FPU_MVE),
3072    MVE_VSBC,
3073    0xfe300f00, 0xffb10f51,
3074    "vsbc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3075
3076   /* Vector VSHL T2 Variant.  */
3077   {ARM_FEATURE_COPROC (FPU_MVE),
3078    MVE_VSHL_T2,
3079    0xee311e60, 0xefb31ff0,
3080    "vshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3081
3082   /* Vector VSHL T3 Variant.  */
3083   {ARM_FEATURE_COPROC (FPU_MVE),
3084    MVE_VSHL_T3,
3085    0xef000440, 0xef811f51,
3086    "vshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3087
3088   /* Vector VSHLC.  */
3089   {ARM_FEATURE_COPROC (FPU_MVE),
3090    MVE_VSHLC,
3091    0xeea00fc0, 0xffa01ff0,
3092    "vshlc%v\t%13-15,22Q, %0-3r, #%16-20d"},
3093
3094   /* Vector VSHLL T2 Variant.  */
3095   {ARM_FEATURE_COPROC (FPU_MVE),
3096    MVE_VSHLL_T2,
3097    0xee310e01, 0xefb30fd1,
3098    "vshll%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q, #%18-19d"},
3099
3100   /* Vector VSHRN.  */
3101   {ARM_FEATURE_COPROC (FPU_MVE),
3102    MVE_VSHRN,
3103    0xee800fc1, 0xffa00fd1,
3104    "vshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3105
3106   /* Vector VST2 no writeback.  */
3107   {ARM_FEATURE_COPROC (FPU_MVE),
3108    MVE_VST2,
3109    0xfc801e00, 0xffb01e5f,
3110    "vst2%5d.%7-8s\t%B, [%16-19r]"},
3111
3112   /* Vector VST2 writeback.  */
3113   {ARM_FEATURE_COPROC (FPU_MVE),
3114    MVE_VST2,
3115    0xfca01e00, 0xffb01e5f,
3116    "vst2%5d.%7-8s\t%B, [%16-19r]!"},
3117
3118   /* Vector VST4 no writeback.  */
3119   {ARM_FEATURE_COPROC (FPU_MVE),
3120    MVE_VST4,
3121    0xfc801e01, 0xffb01e1f,
3122    "vst4%5-6d.%7-8s\t%B, [%16-19r]"},
3123
3124   /* Vector VST4 writeback.  */
3125   {ARM_FEATURE_COPROC (FPU_MVE),
3126    MVE_VST4,
3127    0xfca01e01, 0xffb01e1f,
3128    "vst4%5-6d.%7-8s\t%B, [%16-19r]!"},
3129
3130   /* Vector VSTRB scatter store, T1 variant.  */
3131   {ARM_FEATURE_COPROC (FPU_MVE),
3132    MVE_VSTRB_SCATTER_T1,
3133    0xec800e00, 0xffb01e50,
3134    "vstrb%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
3135
3136   /* Vector VSTRH scatter store, T2 variant.  */
3137   {ARM_FEATURE_COPROC (FPU_MVE),
3138    MVE_VSTRH_SCATTER_T2,
3139    0xec800e10, 0xffb01e50,
3140    "vstrh%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3141
3142   /* Vector VSTRW scatter store, T3 variant.  */
3143   {ARM_FEATURE_COPROC (FPU_MVE),
3144    MVE_VSTRW_SCATTER_T3,
3145    0xec800e40, 0xffb01e50,
3146    "vstrw%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3147
3148   /* Vector VSTRD scatter store, T4 variant.  */
3149   {ARM_FEATURE_COPROC (FPU_MVE),
3150    MVE_VSTRD_SCATTER_T4,
3151    0xec800fd0, 0xffb01fd0,
3152    "vstrd%v.64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3153
3154   /* Vector VSTRW scatter store, T5 variant.  */
3155   {ARM_FEATURE_COPROC (FPU_MVE),
3156    MVE_VSTRW_SCATTER_T5,
3157    0xfd001e00, 0xff111f00,
3158    "vstrw%v.32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
3159
3160   /* Vector VSTRD scatter store, T6 variant.  */
3161   {ARM_FEATURE_COPROC (FPU_MVE),
3162    MVE_VSTRD_SCATTER_T6,
3163    0xfd001f00, 0xff111f00,
3164    "vstrd%v.64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
3165
3166   /* Vector VSTRB.  */
3167   {ARM_FEATURE_COPROC (FPU_MVE),
3168    MVE_VSTRB_T1,
3169    0xec000e00, 0xfe581e00,
3170    "vstrb%v.%7-8s\t%13-15Q, %d"},
3171
3172   /* Vector VSTRH.  */
3173   {ARM_FEATURE_COPROC (FPU_MVE),
3174    MVE_VSTRH_T2,
3175    0xec080e00, 0xfe581e00,
3176    "vstrh%v.%7-8s\t%13-15Q, %d"},
3177
3178   /* Vector VSTRB variant T5.  */
3179   {ARM_FEATURE_COPROC (FPU_MVE),
3180    MVE_VSTRB_T5,
3181    0xec001e00, 0xfe101f80,
3182    "vstrb%v.8\t%13-15,22Q, %d"},
3183
3184   /* Vector VSTRH variant T6.  */
3185   {ARM_FEATURE_COPROC (FPU_MVE),
3186    MVE_VSTRH_T6,
3187    0xec001e80, 0xfe101f80,
3188    "vstrh%v.16\t%13-15,22Q, %d"},
3189
3190   /* Vector VSTRW variant T7.  */
3191   {ARM_FEATURE_COPROC (FPU_MVE),
3192    MVE_VSTRW_T7,
3193    0xec001f00, 0xfe101f80,
3194    "vstrw%v.32\t%13-15,22Q, %d"},
3195
3196   /* Vector VSUB floating point T1 variant.  */
3197   {ARM_FEATURE_COPROC (FPU_MVE_FP),
3198    MVE_VSUB_FP_T1,
3199    0xef200d40, 0xffa11f51,
3200    "vsub%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3201
3202   /* Vector VSUB floating point T2 variant.  */
3203   {ARM_FEATURE_COPROC (FPU_MVE_FP),
3204    MVE_VSUB_FP_T2,
3205    0xee301f40, 0xefb11f70,
3206    "vsub%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3207
3208   /* Vector VSUB T1 variant.  */
3209   {ARM_FEATURE_COPROC (FPU_MVE),
3210    MVE_VSUB_VEC_T1,
3211    0xff000840, 0xff811f51,
3212    "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3213
3214   /* Vector VSUB T2 variant.  */
3215   {ARM_FEATURE_COPROC (FPU_MVE),
3216    MVE_VSUB_VEC_T2,
3217    0xee011f40, 0xff811f70,
3218    "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3219
3220   {ARM_FEATURE_CORE_LOW (0),
3221    MVE_NONE,
3222    0x00000000, 0x00000000, 0}
3223 };
3224
3225 /* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb.  All three are partially
3226    ordered: they must be searched linearly from the top to obtain a correct
3227    match.  */
3228
3229 /* print_insn_arm recognizes the following format control codes:
3230
3231    %%                   %
3232
3233    %a                   print address for ldr/str instruction
3234    %s                   print address for ldr/str halfword/signextend instruction
3235    %S                   like %s but allow UNPREDICTABLE addressing
3236    %b                   print branch destination
3237    %c                   print condition code (always bits 28-31)
3238    %m                   print register mask for ldm/stm instruction
3239    %o                   print operand2 (immediate or register + shift)
3240    %p                   print 'p' iff bits 12-15 are 15
3241    %t                   print 't' iff bit 21 set and bit 24 clear
3242    %B                   print arm BLX(1) destination
3243    %C                   print the PSR sub type.
3244    %U                   print barrier type.
3245    %P                   print address for pli instruction.
3246
3247    %<bitfield>r         print as an ARM register
3248    %<bitfield>T         print as an ARM register + 1
3249    %<bitfield>R         as %r but r15 is UNPREDICTABLE
3250    %<bitfield>{r|R}u    as %{r|R} but if matches the other %u field then is UNPREDICTABLE
3251    %<bitfield>{r|R}U    as %{r|R} but if matches the other %U field then is UNPREDICTABLE
3252    %<bitfield>d         print the bitfield in decimal
3253    %<bitfield>W         print the bitfield plus one in decimal
3254    %<bitfield>x         print the bitfield in hex
3255    %<bitfield>X         print the bitfield as 1 hex digit without leading "0x"
3256
3257    %<bitfield>'c        print specified char iff bitfield is all ones
3258    %<bitfield>`c        print specified char iff bitfield is all zeroes
3259    %<bitfield>?ab...    select from array of values in big endian order
3260
3261    %e                   print arm SMI operand (bits 0..7,8..19).
3262    %E                   print the LSB and WIDTH fields of a BFI or BFC instruction.
3263    %V                   print the 16-bit immediate field of a MOVT or MOVW instruction.
3264    %R                   print the SPSR/CPSR or banked register of an MRS.  */
3265
3266 static const struct opcode32 arm_opcodes[] =
3267 {
3268   /* ARM instructions.  */
3269   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3270     0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
3271   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3272     0xe7f000f0, 0xfff000f0, "udf\t#%e"},
3273
3274   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5),
3275     0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
3276   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
3277     0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
3278   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
3279     0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3280   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S),
3281     0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
3282   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
3283     0x00800090, 0x0fa000f0,
3284     "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3285   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
3286     0x00a00090, 0x0fa000f0,
3287     "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3288
3289   /* V8.2 RAS extension instructions.  */
3290   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
3291     0xe320f010, 0xffffffff, "esb"},
3292
3293   /* V8 instructions.  */
3294   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3295     0x0320f005, 0x0fffffff, "sevl"},
3296   /* Defined in V8 but is in NOP space so available to all arch.  */
3297   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3298     0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
3299   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
3300     0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
3301   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3302     0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
3303   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3304     0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
3305   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3306     0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
3307   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3308     0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
3309   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3310     0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
3311   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3312     0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
3313   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3314     0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
3315   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3316     0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
3317   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3318     0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
3319   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3320     0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
3321   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3322     0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
3323   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3324     0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
3325   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3326     0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
3327   /* CRC32 instructions.  */
3328   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3329     0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
3330   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3331     0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
3332   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3333     0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
3334   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3335     0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
3336   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3337     0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
3338   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3339     0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
3340
3341   /* Privileged Access Never extension instructions.  */
3342   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
3343     0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
3344
3345   /* Virtualization Extension instructions.  */
3346   {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
3347   {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
3348
3349   /* Integer Divide Extension instructions.  */
3350   {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
3351     0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
3352   {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
3353     0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
3354
3355   /* MP Extension instructions.  */
3356   {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"},
3357
3358   /* Speculation Barriers.  */
3359   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xe320f014, 0xffffffff, "csdb"},
3360   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff040, 0xffffffff, "ssbb"},
3361   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff044, 0xffffffff, "pssbb"},
3362
3363   /* V7 instructions.  */
3364   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
3365   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
3366   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
3367   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
3368   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
3369   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
3370   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"},
3371    {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
3372     0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
3373
3374   /* ARM V6T2 instructions.  */
3375   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3376     0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
3377   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3378     0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
3379   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3380     0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3381   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3382     0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
3383
3384   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3385     0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
3386   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3387     0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
3388
3389   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3390     0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
3391   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3392     0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
3393   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3394     0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
3395   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3396     0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
3397
3398   /* ARM Security extension instructions.  */
3399   {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
3400     0x01600070, 0x0ff000f0, "smc%c\t%e"},
3401
3402   /* ARM V6K instructions.  */
3403   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3404     0xf57ff01f, 0xffffffff, "clrex"},
3405   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3406     0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
3407   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3408     0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
3409   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3410     0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
3411   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3412     0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
3413   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3414     0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
3415   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3416     0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
3417
3418   /* ARMv8.5-A instructions.  */
3419   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf57ff070, 0xffffffff, "sb"},
3420
3421   /* ARM V6K NOP hints.  */
3422   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3423     0x0320f001, 0x0fffffff, "yield%c"},
3424   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3425     0x0320f002, 0x0fffffff, "wfe%c"},
3426   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3427     0x0320f003, 0x0fffffff, "wfi%c"},
3428   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3429     0x0320f004, 0x0fffffff, "sev%c"},
3430   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3431     0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
3432
3433   /* ARM V6 instructions.  */
3434   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3435     0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
3436   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3437     0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
3438   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3439     0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
3440   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3441     0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
3442   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3443     0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
3444   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3445     0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
3446   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3447     0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
3448   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3449     0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
3450   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3451     0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
3452   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3453     0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
3454   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3455     0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
3456   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3457     0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
3458   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3459     0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
3460   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3461     0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
3462   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3463     0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
3464   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3465     0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
3466   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3467     0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
3468   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3469     0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
3470   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3471     0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
3472   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3473     0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
3474   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3475     0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
3476   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3477     0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
3478   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3479     0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
3480   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3481     0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
3482   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3483     0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
3484   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3485     0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
3486   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3487     0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
3488   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3489     0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
3490   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3491     0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
3492   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3493     0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
3494   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3495     0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
3496   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3497     0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
3498   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3499     0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
3500   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3501     0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
3502   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3503     0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
3504   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3505     0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
3506   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3507     0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
3508   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3509     0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
3510   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3511     0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
3512   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3513     0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
3514   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3515     0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
3516   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3517     0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
3518   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3519     0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
3520   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3521     0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
3522   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3523     0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
3524   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3525     0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
3526   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3527     0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
3528   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3529     0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
3530   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3531     0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
3532   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3533     0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
3534   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3535     0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
3536   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3537     0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
3538   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3539     0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
3540   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3541     0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
3542   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3543     0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
3544   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3545     0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
3546   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3547     0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
3548   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3549     0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
3550   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3551     0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
3552   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3553     0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
3554   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3555     0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
3556   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3557     0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
3558   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3559     0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
3560   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3561     0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
3562   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3563     0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
3564   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3565     0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
3566   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3567     0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
3568   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3569     0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
3570   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3571     0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
3572   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3573     0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
3574   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3575     0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
3576   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3577     0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
3578   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3579     0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
3580   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3581     0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
3582   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3583     0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
3584   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3585     0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3586   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3587     0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3588   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3589     0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3590   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3591     0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
3592   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3593     0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3594   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3595     0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3596   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3597     0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3598   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3599     0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
3600   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3601     0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3602   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3603     0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3604   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3605     0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3606   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3607     0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
3608   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3609     0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3610   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3611     0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3612   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3613     0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3614   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3615     0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
3616   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3617     0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3618   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3619     0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3620   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3621     0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
3622   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3623     0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
3624   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3625     0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3626   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3627     0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3628   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3629     0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3630   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3631     0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
3632   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3633     0xf1010000, 0xfffffc00, "setend\t%9?ble"},
3634   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3635     0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
3636   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3637     0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
3638   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3639     0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3640   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3641     0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3642   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3643     0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3644   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3645     0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3646   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3647     0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
3648   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3649     0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3650   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3651     0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3652   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3653     0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
3654   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3655     0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
3656   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3657     0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
3658   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3659     0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
3660   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3661     0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
3662   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3663     0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
3664   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3665     0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
3666   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3667     0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
3668   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3669     0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3670   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3671     0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
3672   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3673     0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
3674   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3675     0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
3676   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3677     0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
3678
3679   /* V5J instruction.  */
3680   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J),
3681     0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
3682
3683   /* V5 Instructions.  */
3684   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3685     0xe1200070, 0xfff000f0,
3686     "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
3687   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3688     0xfa000000, 0xfe000000, "blx\t%B"},
3689   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3690     0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
3691   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3692     0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
3693
3694   /* V5E "El Segundo" Instructions.  */
3695   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
3696     0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
3697   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
3698     0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
3699   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
3700     0xf450f000, 0xfc70f000, "pld\t%a"},
3701   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3702     0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3703   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3704     0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3705   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3706     0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3707   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3708     0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
3709
3710   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3711     0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3712   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3713     0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
3714
3715   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3716     0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3717   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3718     0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3719   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3720     0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3721   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3722     0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3723
3724   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3725     0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
3726   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3727     0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
3728   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3729     0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
3730   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3731     0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
3732
3733   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3734     0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
3735   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3736     0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
3737
3738   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3739     0x01000050, 0x0ff00ff0,  "qadd%c\t%12-15R, %0-3R, %16-19R"},
3740   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3741     0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
3742   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3743     0x01200050, 0x0ff00ff0,  "qsub%c\t%12-15R, %0-3R, %16-19R"},
3744   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3745     0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
3746
3747   /* ARM Instructions.  */
3748   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3749     0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
3750
3751   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3752     0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
3753   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3754     0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
3755   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3756     0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
3757   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3758     0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
3759   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3760     0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
3761   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3762     0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
3763
3764   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3765     0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
3766   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3767     0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
3768   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3769     0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
3770   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3771     0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
3772
3773   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3774     0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
3775   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3776     0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
3777   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3778     0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
3779   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3780     0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
3781
3782   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3783     0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
3784   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3785     0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
3786   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3787     0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
3788
3789   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3790     0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
3791   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3792     0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
3793   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3794     0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
3795
3796   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3797     0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
3798   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3799     0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
3800   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3801     0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
3802
3803   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3804     0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
3805   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3806     0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
3807   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3808     0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
3809
3810   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3811     0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
3812   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3813     0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
3814   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3815     0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
3816
3817   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3818     0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
3819   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3820     0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
3821   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3822     0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
3823
3824   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3825     0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
3826   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3827     0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
3828   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3829     0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
3830
3831   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3832     0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
3833   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3834     0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
3835   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3836     0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
3837
3838   {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
3839     0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
3840   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
3841     0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
3842   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
3843     0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
3844
3845   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3846     0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
3847   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3848     0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
3849   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3850     0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
3851
3852   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3853     0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
3854   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3855     0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
3856   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3857     0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
3858
3859   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3860     0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
3861   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3862     0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
3863   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3864     0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
3865
3866   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3867     0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
3868   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3869     0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
3870   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3871     0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
3872
3873   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3874     0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
3875   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3876     0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
3877   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3878     0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
3879
3880   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3881     0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
3882   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3883     0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
3884   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3885     0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
3886   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3887     0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
3888   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3889     0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
3890   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3891     0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
3892   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3893     0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
3894
3895   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3896     0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
3897   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3898     0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
3899   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3900     0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
3901
3902   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3903     0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
3904   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3905     0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
3906   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3907     0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
3908
3909   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3910     0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
3911   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3912     0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
3913
3914   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3915     0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
3916
3917   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3918     0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
3919   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3920     0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
3921
3922   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3923     0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3924   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3925     0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3926   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3927     0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3928   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3929     0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3930   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3931     0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3932   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3933     0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3934   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3935     0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3936   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3937     0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3938   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3939     0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3940   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3941     0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3942   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3943     0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3944   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3945     0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3946   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3947     0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3948   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3949     0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3950   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3951     0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3952   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3953     0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3954   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3955     0x092d0000, 0x0fff0000, "push%c\t%m"},
3956   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3957     0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
3958   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3959     0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
3960
3961   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3962     0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3963   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3964     0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3965   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3966     0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3967   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3968     0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3969   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3970     0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3971   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3972     0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3973   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3974     0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3975   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3976     0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3977   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3978     0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3979   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3980     0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3981   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3982     0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3983   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3984     0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3985   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3986     0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3987   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3988     0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3989   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3990     0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3991   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3992     0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3993   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3994     0x08bd0000, 0x0fff0000, "pop%c\t%m"},
3995   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3996     0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
3997   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3998     0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
3999
4000   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4001     0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
4002   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4003     0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
4004
4005   /* The rest.  */
4006   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
4007     0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION},
4008   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4009     0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
4010   {ARM_FEATURE_CORE_LOW (0),
4011     0x00000000, 0x00000000, 0}
4012 };
4013
4014 /* print_insn_thumb16 recognizes the following format control codes:
4015
4016    %S                   print Thumb register (bits 3..5 as high number if bit 6 set)
4017    %D                   print Thumb register (bits 0..2 as high number if bit 7 set)
4018    %<bitfield>I         print bitfield as a signed decimal
4019                                 (top bit of range being the sign bit)
4020    %N                   print Thumb register mask (with LR)
4021    %O                   print Thumb register mask (with PC)
4022    %M                   print Thumb register mask
4023    %b                   print CZB's 6-bit unsigned branch destination
4024    %s                   print Thumb right-shift immediate (6..10; 0 == 32).
4025    %c                   print the condition code
4026    %C                   print the condition code, or "s" if not conditional
4027    %x                   print warning if conditional an not at end of IT block"
4028    %X                   print "\t; unpredictable <IT:code>" if conditional
4029    %I                   print IT instruction suffix and operands
4030    %W                   print Thumb Writeback indicator for LDMIA
4031    %<bitfield>r         print bitfield as an ARM register
4032    %<bitfield>d         print bitfield as a decimal
4033    %<bitfield>H         print (bitfield * 2) as a decimal
4034    %<bitfield>W         print (bitfield * 4) as a decimal
4035    %<bitfield>a         print (bitfield * 4) as a pc-rel offset + decoded symbol
4036    %<bitfield>B         print Thumb branch destination (signed displacement)
4037    %<bitfield>c         print bitfield as a condition code
4038    %<bitnum>'c          print specified char iff bit is one
4039    %<bitnum>?ab         print a if bit is one else print b.  */
4040
4041 static const struct opcode16 thumb_opcodes[] =
4042 {
4043   /* Thumb instructions.  */
4044
4045   /* ARMv8-M Security Extensions instructions.  */
4046   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"},
4047   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff87, "bxns\t%3-6r"},
4048
4049   /* ARM V8 instructions.  */
4050   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),  0xbf50, 0xffff, "sevl%c"},
4051   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),  0xba80, 0xffc0, "hlt\t%0-5x"},
4052   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),  0xb610, 0xfff7, "setpan\t#%3-3d"},
4053
4054   /* ARM V6K no-argument instructions.  */
4055   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
4056   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"},
4057   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"},
4058   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"},
4059   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"},
4060   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
4061
4062   /* ARM V6T2 instructions.  */
4063   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4064     0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
4065   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4066     0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
4067   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
4068
4069   /* ARM V6.  */
4070   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
4071   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
4072   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
4073   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
4074   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
4075   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
4076   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%3?ble%X"},
4077   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
4078   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
4079   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
4080   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
4081
4082   /* ARM V5 ISA extends Thumb.  */
4083   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
4084     0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional.  */
4085   /* This is BLX(2).  BLX(1) is a 32-bit instruction.  */
4086   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
4087     0x4780, 0xff87, "blx%c\t%3-6r%x"},  /* note: 4 bit register number.  */
4088   /* ARM V4T ISA (Thumb v1).  */
4089   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4090     0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
4091   /* Format 4.  */
4092   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
4093   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
4094   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
4095   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
4096   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
4097   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
4098   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
4099   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
4100   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
4101   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
4102   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
4103   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
4104   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
4105   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
4106   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
4107   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
4108   /* format 13 */
4109   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
4110   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
4111   /* format 5 */
4112   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"},
4113   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"},
4114   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
4115   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"},
4116   /* format 14 */
4117   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"},
4118   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"},
4119   /* format 2 */
4120   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4121     0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
4122   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4123     0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
4124   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4125     0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
4126   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4127     0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
4128   /* format 8 */
4129   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4130     0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
4131   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4132     0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
4133   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4134     0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
4135   /* format 7 */
4136   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4137     0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
4138   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4139     0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
4140   /* format 1 */
4141   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
4142   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4143     0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
4144   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
4145   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
4146   /* format 3 */
4147   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
4148   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
4149   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
4150   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
4151   /* format 6 */
4152   /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
4153   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4154     0x4800, 0xF800,
4155     "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
4156   /* format 9 */
4157   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4158     0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
4159   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4160     0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
4161   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4162     0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
4163   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4164     0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
4165   /* format 10 */
4166   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4167     0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
4168   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4169     0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
4170   /* format 11 */
4171   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4172     0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
4173   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4174     0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
4175   /* format 12 */
4176   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4177     0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
4178   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4179     0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
4180   /* format 15 */
4181   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
4182   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
4183   /* format 17 */
4184   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
4185   /* format 16 */
4186   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
4187   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
4188   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
4189   /* format 18 */
4190   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
4191
4192   /* The E800 .. FFFF range is unconditionally redirected to the
4193      32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
4194      are processed via that table.  Thus, we can never encounter a
4195      bare "second half of BL/BLX(1)" instruction here.  */
4196   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),  0x0000, 0x0000, UNDEFINED_INSTRUCTION},
4197   {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
4198 };
4199
4200 /* Thumb32 opcodes use the same table structure as the ARM opcodes.
4201    We adopt the convention that hw1 is the high 16 bits of .value and
4202    .mask, hw2 the low 16 bits.
4203
4204    print_insn_thumb32 recognizes the following format control codes:
4205
4206        %%               %
4207
4208        %I               print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
4209        %M               print a modified 12-bit immediate (same location)
4210        %J               print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
4211        %K               print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
4212        %H               print a 16-bit immediate from hw2[3:0],hw1[11:0]
4213        %S               print a possibly-shifted Rm
4214
4215        %L               print address for a ldrd/strd instruction
4216        %a               print the address of a plain load/store
4217        %w               print the width and signedness of a core load/store
4218        %m               print register mask for ldm/stm
4219        %n               print register mask for clrm
4220
4221        %E               print the lsb and width fields of a bfc/bfi instruction
4222        %F               print the lsb and width fields of a sbfx/ubfx instruction
4223        %G               print a fallback offset for Branch Future instructions
4224        %W               print an offset for BF instruction
4225        %Y               print an offset for BFL instruction
4226        %Z               print an offset for BFCSEL instruction
4227        %Q               print an offset for Low Overhead Loop instructions
4228        %P               print an offset for Low Overhead Loop end instructions
4229        %b               print a conditional branch offset
4230        %B               print an unconditional branch offset
4231        %s               print the shift field of an SSAT instruction
4232        %R               print the rotation field of an SXT instruction
4233        %U               print barrier type.
4234        %P               print address for pli instruction.
4235        %c               print the condition code
4236        %x               print warning if conditional an not at end of IT block"
4237        %X               print "\t; unpredictable <IT:code>" if conditional
4238
4239        %<bitfield>d     print bitfield in decimal
4240        %<bitfield>D     print bitfield plus one in decimal
4241        %<bitfield>W     print bitfield*4 in decimal
4242        %<bitfield>r     print bitfield as an ARM register
4243        %<bitfield>R     as %<>r but r15 is UNPREDICTABLE
4244        %<bitfield>S     as %<>r but r13 and r15 is UNPREDICTABLE
4245        %<bitfield>c     print bitfield as a condition code
4246
4247        %<bitfield>'c    print specified char iff bitfield is all ones
4248        %<bitfield>`c    print specified char iff bitfield is all zeroes
4249        %<bitfield>?ab... select from array of values in big endian order
4250
4251    With one exception at the bottom (done because BL and BLX(1) need
4252    to come dead last), this table was machine-sorted first in
4253    decreasing order of number of bits set in the mask, then in
4254    increasing numeric order of mask, then in increasing numeric order
4255    of opcode.  This order is not the clearest for a human reader, but
4256    is guaranteed never to catch a special-case bit pattern with a more
4257    general mask, which is important, because this instruction encoding
4258    makes heavy use of special-case bit patterns.  */
4259 static const struct opcode32 thumb32_opcodes[] =
4260 {
4261   /* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions
4262      instructions.  */
4263   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4264     0xf00fe001, 0xffffffff, "lctp%c"},
4265   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4266     0xf02fc001, 0xfffff001, "le\t%P"},
4267   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4268     0xf00fc001, 0xfffff001, "le\tlr, %P"},
4269   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4270     0xf01fc001, 0xfffff001, "letp\tlr, %P"},
4271   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4272     0xf040c001, 0xfff0f001, "wls\tlr, %16-19S, %Q"},
4273   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4274     0xf000c001, 0xffc0f001, "wlstp.%20-21s\tlr, %16-19S, %Q"},
4275   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4276     0xf040e001, 0xfff0ffff, "dls\tlr, %16-19S"},
4277   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4278     0xf000e001, 0xffc0ffff, "dlstp.%20-21s\tlr, %16-19S"},
4279
4280   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4281     0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
4282   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4283     0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"},
4284   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4285     0xf000c001, 0xf800f001, "bfl%c\t%G, %Y"},
4286   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4287     0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"},
4288   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4289     0xf000e001, 0xf840f001, "bfcsel\t%G, %Z, %18-21c"},
4290
4291   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4292     0xe89f0000, 0xffff2000, "clrm%c\t%n"},
4293
4294   /* ARMv8-M and ARMv8-M Security Extensions instructions.  */
4295   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"},
4296   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4297     0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
4298   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4299     0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
4300   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4301     0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
4302   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4303     0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
4304
4305   /* ARM V8.2 RAS extension instructions.  */
4306   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
4307     0xf3af8010, 0xffffffff, "esb"},
4308
4309   /* V8 instructions.  */
4310   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4311     0xf3af8005, 0xffffffff, "sevl%c.w"},
4312   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4313     0xf78f8000, 0xfffffffc, "dcps%0-1d"},
4314   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4315     0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
4316   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4317     0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
4318   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4319     0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
4320   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4321     0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
4322   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4323     0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
4324   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4325     0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
4326   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4327     0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
4328   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4329     0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
4330   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4331     0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
4332   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4333     0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
4334   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4335     0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
4336   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4337     0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
4338   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4339     0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
4340   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4341     0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
4342
4343   /* CRC32 instructions.  */
4344   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
4345     0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},
4346   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
4347     0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"},
4348   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
4349     0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"},
4350   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
4351     0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"},
4352   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
4353     0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"},
4354   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
4355     0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
4356
4357   /* Speculation Barriers.  */
4358   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8014, 0xffffffff, "csdb"},
4359   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f40, 0xffffffff, "ssbb"},
4360   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f44, 0xffffffff, "pssbb"},
4361
4362   /* V7 instructions.  */
4363   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
4364   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
4365   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
4366   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
4367   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
4368   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
4369   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
4370   {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
4371     0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
4372   {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
4373     0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
4374
4375   /* Virtualization Extension instructions.  */
4376   {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
4377   /* We skip ERET as that is SUBS pc, lr, #0.  */
4378
4379   /* MP Extension instructions.  */
4380   {ARM_FEATURE_CORE_LOW (ARM_EXT_MP),   0xf830f000, 0xff70f000, "pldw%c\t%a"},
4381
4382   /* Security extension instructions.  */
4383   {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),  0xf7f08000, 0xfff0f000, "smc%c\t%K"},
4384
4385   /* ARMv8.5-A instructions.  */
4386   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf3bf8f70, 0xffffffff, "sb"},
4387
4388   /* Instructions defined in the basic V6T2 set.  */
4389   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
4390   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},
4391   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"},
4392   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"},
4393   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"},
4394   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4395     0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
4396   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
4397
4398   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4399     0xf3bf8f2f, 0xffffffff, "clrex%c"},
4400   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4401     0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
4402   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4403     0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
4404   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4405     0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
4406   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4407     0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
4408   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4409     0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
4410   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4411     0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
4412   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4413     0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
4414   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4415     0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
4416   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4417     0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
4418   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4419     0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
4420   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4421     0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
4422   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4423     0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
4424   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4425     0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
4426   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4427     0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
4428   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4429     0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
4430   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4431     0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
4432   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4433     0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
4434   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4435     0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
4436   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4437     0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
4438   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4439     0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
4440   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4441     0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
4442   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4443     0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
4444   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4445     0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
4446   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4447     0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
4448   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4449     0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
4450   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4451     0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
4452   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4453     0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
4454   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4455     0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
4456   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4457     0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
4458   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4459     0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
4460   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4461     0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
4462   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4463     0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
4464   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4465     0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
4466   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4467     0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
4468   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4469     0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
4470   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4471     0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
4472   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4473     0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
4474   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4475     0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
4476   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4477     0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
4478   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4479     0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
4480   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4481     0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
4482   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4483     0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
4484   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4485     0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
4486   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4487     0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
4488   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4489     0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
4490   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4491     0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
4492   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4493     0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
4494   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4495     0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
4496   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4497     0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
4498   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4499     0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
4500   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4501     0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
4502   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4503     0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
4504   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4505     0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
4506   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4507     0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
4508   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4509     0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
4510   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4511     0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
4512   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4513     0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
4514   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4515     0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
4516   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4517     0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
4518   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4519     0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
4520   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4521     0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
4522   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4523     0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
4524   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4525     0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
4526   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4527     0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
4528   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4529     0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
4530   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4531     0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
4532   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4533     0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
4534   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4535     0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
4536   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4537     0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
4538   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4539     0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
4540   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4541     0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
4542   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4543     0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
4544   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4545     0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
4546   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4547     0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4548   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4549     0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4550   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4551     0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4552   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4553     0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
4554   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4555     0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
4556   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4557     0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
4558   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4559     0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
4560   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4561     0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
4562   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4563     0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4564   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4565     0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
4566   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4567     0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
4568   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4569     0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4570   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4571     0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4572   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4573     0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4574   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4575     0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4576   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4577     0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4578   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4579     0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4580   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4581     0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4582   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4583     0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
4584   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4585     0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
4586   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4587     0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
4588   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4589     0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
4590   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4591     0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
4592   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4593     0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
4594   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4595     0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
4596   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4597     0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
4598   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4599     0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
4600   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4601     0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
4602   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4603     0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
4604   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4605     0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
4606   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4607     0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4608   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4609     0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4610   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4611     0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4612   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4613     0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4614   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4615     0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4616   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4617     0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4618   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4619     0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4620   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4621     0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4622   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4623     0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
4624   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4625     0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
4626   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4627     0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
4628   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4629     0xf810f000, 0xff70f000, "pld%c\t%a"},
4630   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4631     0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4632   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4633     0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4634   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4635     0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4636   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4637     0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4638   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4639     0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4640   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4641     0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4642   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4643     0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4644   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4645     0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
4646   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4647     0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
4648   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4649     0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
4650   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4651     0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
4652   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4653     0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
4654   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4655     0xfb100000, 0xfff000c0,
4656     "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4657   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4658     0xfbc00080, 0xfff000c0,
4659     "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
4660   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4661     0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
4662   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4663     0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
4664   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4665     0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
4666   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4667     0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
4668   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4669     0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
4670   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4671     0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
4672   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4673     0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
4674   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4675     0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
4676   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4677     0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
4678   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4679     0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
4680   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4681     0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
4682   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4683     0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
4684   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4685     0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
4686   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4687     0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
4688   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4689     0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
4690   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4691     0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
4692   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4693     0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
4694   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4695     0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
4696   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4697     0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
4698   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4699     0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
4700   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4701     0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
4702   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4703     0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
4704   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4705     0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
4706   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4707     0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
4708   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4709     0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
4710   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4711     0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
4712   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4713     0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
4714   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4715     0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
4716   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4717     0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
4718   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4719     0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
4720   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4721     0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
4722   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4723     0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
4724   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4725     0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
4726   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4727     0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
4728   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4729     0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
4730   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4731     0xe9400000, 0xff500000,
4732     "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
4733   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4734     0xe9500000, 0xff500000,
4735     "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
4736   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4737     0xe8600000, 0xff700000,
4738     "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
4739   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4740     0xe8700000, 0xff700000,
4741     "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
4742   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4743     0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
4744   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4745     0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
4746
4747   /* Filter out Bcc with cond=E or F, which are used for other instructions.  */
4748   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4749     0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
4750   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4751     0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
4752   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4753     0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
4754   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4755     0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
4756
4757   /* These have been 32-bit since the invention of Thumb.  */
4758   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4759      0xf000c000, 0xf800d001, "blx%c\t%B%x"},
4760   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4761      0xf000d000, 0xf800d000, "bl%c\t%B%x"},
4762
4763   /* Fallback.  */
4764   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4765       0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
4766   {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
4767 };
4768
4769 static const char *const arm_conditional[] =
4770 {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
4771  "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
4772
4773 static const char *const arm_fp_const[] =
4774 {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
4775
4776 static const char *const arm_shift[] =
4777 {"lsl", "lsr", "asr", "ror"};
4778
4779 typedef struct
4780 {
4781   const char *name;
4782   const char *description;
4783   const char *reg_names[16];
4784 }
4785 arm_regname;
4786
4787 static const arm_regname regnames[] =
4788 {
4789   { "reg-names-raw", N_("Select raw register names"),
4790     { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
4791   { "reg-names-gcc", N_("Select register names used by GCC"),
4792     { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl",  "fp",  "ip",  "sp",  "lr",  "pc" }},
4793   { "reg-names-std", N_("Select register names used in ARM's ISA documentation"),
4794     { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp",  "lr",  "pc" }},
4795   { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL} },
4796   { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL} },
4797   { "reg-names-apcs", N_("Select register names used in the APCS"),
4798     { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl",  "fp",  "ip",  "sp",  "lr",  "pc" }},
4799   { "reg-names-atpcs", N_("Select register names used in the ATPCS"),
4800     { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7",  "v8",  "IP",  "SP",  "LR",  "PC" }},
4801   { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
4802     { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL",  "FP",  "IP",  "SP",  "LR",  "PC" }}
4803 };
4804
4805 static const char *const iwmmxt_wwnames[] =
4806 {"b", "h", "w", "d"};
4807
4808 static const char *const iwmmxt_wwssnames[] =
4809 {"b", "bus", "bc", "bss",
4810  "h", "hus", "hc", "hss",
4811  "w", "wus", "wc", "wss",
4812  "d", "dus", "dc", "dss"
4813 };
4814
4815 static const char *const iwmmxt_regnames[] =
4816 { "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
4817   "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
4818 };
4819
4820 static const char *const iwmmxt_cregnames[] =
4821 { "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
4822   "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
4823 };
4824
4825 static const char *const vec_condnames[] =
4826 { "eq", "ne", "cs", "hi", "ge", "lt", "gt", "le"
4827 };
4828
4829 static const char *const mve_predicatenames[] =
4830 { "", "ttt", "tt", "tte", "t", "tee", "te", "tet", "",
4831   "eee", "ee", "eet", "e", "ett", "et", "ete"
4832 };
4833
4834 /* Names for 2-bit size field for mve vector isntructions.  */
4835 static const char *const mve_vec_sizename[] =
4836   { "8", "16", "32", "64"};
4837
4838 /* Indicates whether we are processing a then predicate,
4839    else predicate or none at all.  */
4840 enum vpt_pred_state
4841 {
4842   PRED_NONE,
4843   PRED_THEN,
4844   PRED_ELSE
4845 };
4846
4847 /* Information used to process a vpt block and subsequent instructions.  */
4848 struct vpt_block
4849 {
4850   /* Are we in a vpt block.  */
4851   bfd_boolean in_vpt_block;
4852
4853   /* Next predicate state if in vpt block.  */
4854   enum vpt_pred_state next_pred_state;
4855
4856   /* Mask from vpt/vpst instruction.  */
4857   long predicate_mask;
4858
4859   /* Instruction number in vpt block.  */
4860   long current_insn_num;
4861
4862   /* Number of instructions in vpt block..   */
4863   long num_pred_insn;
4864 };
4865
4866 static struct vpt_block vpt_block_state =
4867 {
4868   FALSE,
4869   PRED_NONE,
4870   0,
4871   0,
4872   0
4873 };
4874
4875 /* Default to GCC register name set.  */
4876 static unsigned int regname_selected = 1;
4877
4878 #define NUM_ARM_OPTIONS   ARRAY_SIZE (regnames)
4879 #define arm_regnames      regnames[regname_selected].reg_names
4880
4881 static bfd_boolean force_thumb = FALSE;
4882
4883 /* Current IT instruction state.  This contains the same state as the IT
4884    bits in the CPSR.  */
4885 static unsigned int ifthen_state;
4886 /* IT state for the next instruction.  */
4887 static unsigned int ifthen_next_state;
4888 /* The address of the insn for which the IT state is valid.  */
4889 static bfd_vma ifthen_address;
4890 #define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
4891 /* Indicates that the current Conditional state is unconditional or outside
4892    an IT block.  */
4893 #define COND_UNCOND 16
4894
4895 \f
4896 /* Functions.  */
4897 /* Extract the predicate mask for a VPT or VPST instruction.
4898    The mask is composed of bits 13-15 (Mkl) and bit 22 (Mkh).  */
4899
4900 static long
4901 mve_extract_pred_mask (long given)
4902 {
4903   return ((given & 0x00400000) >> 19) | ((given & 0xe000) >> 13);
4904 }
4905
4906 /* Return the number of instructions in a MVE predicate block.  */
4907 static long
4908 num_instructions_vpt_block (long given)
4909 {
4910   long mask = mve_extract_pred_mask (given);
4911   if (mask == 0)
4912     return 0;
4913
4914   if (mask == 8)
4915     return 1;
4916
4917   if ((mask & 7) == 4)
4918     return 2;
4919
4920   if ((mask & 3) == 2)
4921     return 3;
4922
4923   if ((mask & 1) == 1)
4924     return 4;
4925
4926   return 0;
4927 }
4928
4929 static void
4930 mark_outside_vpt_block (void)
4931 {
4932   vpt_block_state.in_vpt_block = FALSE;
4933   vpt_block_state.next_pred_state = PRED_NONE;
4934   vpt_block_state.predicate_mask = 0;
4935   vpt_block_state.current_insn_num = 0;
4936   vpt_block_state.num_pred_insn = 0;
4937 }
4938
4939 static void
4940 mark_inside_vpt_block (long given)
4941 {
4942   vpt_block_state.in_vpt_block = TRUE;
4943   vpt_block_state.next_pred_state = PRED_THEN;
4944   vpt_block_state.predicate_mask = mve_extract_pred_mask (given);
4945   vpt_block_state.current_insn_num = 0;
4946   vpt_block_state.num_pred_insn = num_instructions_vpt_block (given);
4947   assert (vpt_block_state.num_pred_insn >= 1);
4948 }
4949
4950 static enum vpt_pred_state
4951 invert_next_predicate_state (enum vpt_pred_state astate)
4952 {
4953   if (astate == PRED_THEN)
4954     return PRED_ELSE;
4955   else if (astate == PRED_ELSE)
4956     return PRED_THEN;
4957   else
4958     return PRED_NONE;
4959 }
4960
4961 static enum vpt_pred_state
4962 update_next_predicate_state (void)
4963 {
4964   long pred_mask = vpt_block_state.predicate_mask;
4965   long mask_for_insn = 0;
4966
4967   switch (vpt_block_state.current_insn_num)
4968     {
4969     case 1:
4970       mask_for_insn = 8;
4971       break;
4972
4973     case 2:
4974       mask_for_insn = 4;
4975       break;
4976
4977     case 3:
4978       mask_for_insn = 2;
4979       break;
4980
4981     case 4:
4982       return PRED_NONE;
4983     }
4984
4985   if (pred_mask & mask_for_insn)
4986     return invert_next_predicate_state (vpt_block_state.next_pred_state);
4987   else
4988     return vpt_block_state.next_pred_state;
4989 }
4990
4991 static void
4992 update_vpt_block_state (void)
4993 {
4994   vpt_block_state.current_insn_num++;
4995   if (vpt_block_state.current_insn_num == vpt_block_state.num_pred_insn)
4996     {
4997       /* No more instructions to process in vpt block.  */
4998       mark_outside_vpt_block ();
4999       return;
5000     }
5001
5002   vpt_block_state.next_pred_state = update_next_predicate_state ();
5003 }
5004
5005 /* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
5006    Returns pointer to following character of the format string and
5007    fills in *VALUEP and *WIDTHP with the extracted value and number of
5008    bits extracted.  WIDTHP can be NULL.  */
5009
5010 static const char *
5011 arm_decode_bitfield (const char *ptr,
5012                      unsigned long insn,
5013                      unsigned long *valuep,
5014                      int *widthp)
5015 {
5016   unsigned long value = 0;
5017   int width = 0;
5018
5019   do
5020     {
5021       int start, end;
5022       int bits;
5023
5024       for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
5025         start = start * 10 + *ptr - '0';
5026       if (*ptr == '-')
5027         for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
5028           end = end * 10 + *ptr - '0';
5029       else
5030         end = start;
5031       bits = end - start;
5032       if (bits < 0)
5033         abort ();
5034       value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
5035       width += bits + 1;
5036     }
5037   while (*ptr++ == ',');
5038   *valuep = value;
5039   if (widthp)
5040     *widthp = width;
5041   return ptr - 1;
5042 }
5043
5044 static void
5045 arm_decode_shift (long given, fprintf_ftype func, void *stream,
5046                   bfd_boolean print_shift)
5047 {
5048   func (stream, "%s", arm_regnames[given & 0xf]);
5049
5050   if ((given & 0xff0) != 0)
5051     {
5052       if ((given & 0x10) == 0)
5053         {
5054           int amount = (given & 0xf80) >> 7;
5055           int shift = (given & 0x60) >> 5;
5056
5057           if (amount == 0)
5058             {
5059               if (shift == 3)
5060                 {
5061                   func (stream, ", rrx");
5062                   return;
5063                 }
5064
5065               amount = 32;
5066             }
5067
5068           if (print_shift)
5069             func (stream, ", %s #%d", arm_shift[shift], amount);
5070           else
5071             func (stream, ", #%d", amount);
5072         }
5073       else if ((given & 0x80) == 0x80)
5074         func (stream, "\t; <illegal shifter operand>");
5075       else if (print_shift)
5076         func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
5077               arm_regnames[(given & 0xf00) >> 8]);
5078       else
5079         func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
5080     }
5081 }
5082
5083 /* Return TRUE if the MATCHED_INSN can be inside an IT block.  */
5084
5085 static bfd_boolean
5086 is_mve_okay_in_it (enum mve_instructions matched_insn)
5087 {
5088   switch (matched_insn)
5089     {
5090     case MVE_VMOV_GP_TO_VEC_LANE:
5091     case MVE_VMOV2_VEC_LANE_TO_GP:
5092     case MVE_VMOV2_GP_TO_VEC_LANE:
5093     case MVE_VMOV_VEC_LANE_TO_GP:
5094       return TRUE;
5095     default:
5096       return FALSE;
5097     }
5098 }
5099
5100 static bfd_boolean
5101 is_mve_architecture (struct disassemble_info *info)
5102 {
5103   struct arm_private_data *private_data = info->private_data;
5104   arm_feature_set allowed_arches = private_data->features;
5105
5106   arm_feature_set arm_ext_v8_1m_main
5107     = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
5108
5109   if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
5110       && !ARM_CPU_IS_ANY (allowed_arches))
5111     return TRUE;
5112   else
5113     return FALSE;
5114 }
5115
5116 static bfd_boolean
5117 is_vpt_instruction (long given)
5118 {
5119
5120   /* If mkh:mkl is '0000' then its not a vpt/vpst instruction.  */
5121   if ((given & 0x0040e000) == 0)
5122     return FALSE;
5123
5124   /* VPT floating point T1 variant.  */
5125   if (((given & 0xefb10f50) == 0xee310f00 && ((given & 0x1001) != 0x1))
5126   /* VPT floating point T2 variant.  */
5127       || ((given & 0xefb10f50) == 0xee310f40)
5128   /* VPT vector T1 variant.  */
5129       || ((given & 0xff811f51) == 0xfe010f00)
5130   /* VPT vector T2 variant.  */
5131       || ((given & 0xff811f51) == 0xfe010f01
5132           && ((given & 0x300000) != 0x300000))
5133   /* VPT vector T3 variant.  */
5134       || ((given & 0xff811f50) == 0xfe011f00)
5135   /* VPT vector T4 variant.  */
5136       || ((given & 0xff811f70) == 0xfe010f40)
5137   /* VPT vector T5 variant.  */
5138       || ((given & 0xff811f70) == 0xfe010f60)
5139   /* VPT vector T6 variant.  */
5140       || ((given & 0xff811f50) == 0xfe011f40)
5141   /* VPST vector T variant.  */
5142       || ((given & 0xffbf1fff) == 0xfe310f4d))
5143     return TRUE;
5144   else
5145     return FALSE;
5146 }
5147
5148 /* Decode a bitfield from opcode GIVEN, with starting bitfield = START
5149    and ending bitfield = END.  END must be greater than START.  */
5150
5151 static unsigned long
5152 arm_decode_field (unsigned long given, unsigned int start, unsigned int end)
5153 {
5154   int bits = end - start;
5155
5156   if (bits < 0)
5157     abort ();
5158
5159   return ((given >> start) & ((2ul << bits) - 1));
5160 }
5161
5162 /* Decode a bitfield from opcode GIVEN, with multiple bitfields:
5163    START:END and START2:END2.  END/END2 must be greater than
5164    START/START2.  */
5165
5166 static unsigned long
5167 arm_decode_field_multiple (unsigned long given, unsigned int start,
5168                            unsigned int end, unsigned int start2,
5169                            unsigned int end2)
5170 {
5171   int bits = end - start;
5172   int bits2 = end2 - start2;
5173   unsigned long value = 0;
5174   int width = 0;
5175
5176   if (bits2 < 0)
5177     abort ();
5178
5179   value = arm_decode_field (given, start, end);
5180   width += bits + 1;
5181
5182   value |= ((given >> start2) & ((2ul << bits2) - 1)) << width;
5183   return value;
5184 }
5185
5186 /* Return TRUE if the GIVEN encoding should not be decoded as MATCHED_INSN.
5187    This helps us decode instructions that change mnemonic depending on specific
5188    operand values/encodings.  */
5189
5190 static bfd_boolean
5191 is_mve_encoding_conflict (unsigned long given,
5192                           enum mve_instructions matched_insn)
5193 {
5194   switch (matched_insn)
5195     {
5196     case MVE_VPST:
5197       if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5198         return TRUE;
5199       else
5200         return FALSE;
5201
5202     case MVE_VPT_FP_T1:
5203       if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5204         return TRUE;
5205       if ((arm_decode_field (given, 12, 12) == 0)
5206           && (arm_decode_field (given, 0, 0) == 1))
5207         return TRUE;
5208       return FALSE;
5209
5210     case MVE_VPT_FP_T2:
5211       if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5212         return TRUE;
5213       if (arm_decode_field (given, 0, 3) == 0xd)
5214         return TRUE;
5215       return FALSE;
5216
5217     case MVE_VPT_VEC_T1:
5218     case MVE_VPT_VEC_T2:
5219     case MVE_VPT_VEC_T3:
5220     case MVE_VPT_VEC_T4:
5221     case MVE_VPT_VEC_T5:
5222     case MVE_VPT_VEC_T6:
5223       if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5224         return TRUE;
5225       if (arm_decode_field (given, 20, 21) == 3)
5226         return TRUE;
5227       return FALSE;
5228
5229     case MVE_VCMP_FP_T1:
5230       if ((arm_decode_field (given, 12, 12) == 0)
5231           && (arm_decode_field (given, 0, 0) == 1))
5232         return TRUE;
5233       else
5234         return FALSE;
5235
5236     case MVE_VCMP_FP_T2:
5237       if (arm_decode_field (given, 0, 3) == 0xd)
5238         return TRUE;
5239       else
5240         return FALSE;
5241
5242     case MVE_VMUL_VEC_T2:
5243     case MVE_VMULH:
5244     case MVE_VRMULH:
5245     case MVE_VMLA:
5246     case MVE_VMAX:
5247     case MVE_VMIN:
5248     case MVE_VBRSR:
5249     case MVE_VADD_VEC_T2:
5250     case MVE_VSUB_VEC_T2:
5251     case MVE_VABAV:
5252     case MVE_VQRSHL_T1:
5253     case MVE_VQSHL_T4:
5254     case MVE_VRSHL_T1:
5255     case MVE_VSHL_T3:
5256     case MVE_VCADD_VEC:
5257     case MVE_VHCADD:
5258     case MVE_VDDUP:
5259     case MVE_VIDUP:
5260     case MVE_VQRDMLADH:
5261     case MVE_VQDMLAH:
5262     case MVE_VQRDMLAH:
5263     case MVE_VQDMLASH:
5264     case MVE_VQRDMLASH:
5265     case MVE_VQDMLSDH:
5266     case MVE_VQRDMLSDH:
5267     case MVE_VQDMULH_T3:
5268     case MVE_VQRDMULH_T4:
5269     case MVE_VQDMLADH:
5270     case MVE_VMLAS:
5271     case MVE_VMULL_INT:
5272     case MVE_VHADD_T2:
5273     case MVE_VHSUB_T2:
5274     case MVE_VCMP_VEC_T1:
5275     case MVE_VCMP_VEC_T2:
5276     case MVE_VCMP_VEC_T3:
5277     case MVE_VCMP_VEC_T4:
5278     case MVE_VCMP_VEC_T5:
5279     case MVE_VCMP_VEC_T6:
5280       if (arm_decode_field (given, 20, 21) == 3)
5281         return TRUE;
5282       else
5283         return FALSE;
5284
5285     case MVE_VLD2:
5286     case MVE_VLD4:
5287     case MVE_VST2:
5288     case MVE_VST4:
5289       if (arm_decode_field (given, 7, 8) == 3)
5290         return TRUE;
5291       else
5292         return FALSE;
5293
5294     case MVE_VSTRB_T1:
5295     case MVE_VSTRH_T2:
5296       if ((arm_decode_field (given, 24, 24) == 0)
5297           && (arm_decode_field (given, 21, 21) == 0))
5298         {
5299             return TRUE;
5300         }
5301       else if ((arm_decode_field (given, 7, 8) == 3))
5302         return TRUE;
5303       else
5304         return FALSE;
5305
5306     case MVE_VSTRB_T5:
5307     case MVE_VSTRH_T6:
5308     case MVE_VSTRW_T7:
5309       if ((arm_decode_field (given, 24, 24) == 0)
5310           && (arm_decode_field (given, 21, 21) == 0))
5311         {
5312             return TRUE;
5313         }
5314       else
5315         return FALSE;
5316
5317     case MVE_VCVT_FP_FIX_VEC:
5318       return (arm_decode_field (given, 16, 21) & 0x38) == 0;
5319
5320     case MVE_VBIC_IMM:
5321     case MVE_VORR_IMM:
5322       {
5323         unsigned long cmode = arm_decode_field (given, 8, 11);
5324
5325         if ((cmode & 1) == 0)
5326           return TRUE;
5327         else if ((cmode & 0xc) == 0xc)
5328           return TRUE;
5329         else
5330           return FALSE;
5331       }
5332
5333     case MVE_VMVN_IMM:
5334       {
5335         unsigned long cmode = arm_decode_field (given, 8, 11);
5336
5337         if ((cmode & 9) == 1)
5338           return TRUE;
5339         else if ((cmode & 5) == 1)
5340           return TRUE;
5341         else if ((cmode & 0xe) == 0xe)
5342           return TRUE;
5343         else
5344           return FALSE;
5345       }
5346
5347     case MVE_VMOV_IMM_TO_VEC:
5348       if ((arm_decode_field (given, 5, 5) == 1)
5349           && (arm_decode_field (given, 8, 11) != 0xe))
5350         return TRUE;
5351       else
5352         return FALSE;
5353
5354     case MVE_VMOVL:
5355       {
5356         unsigned long size = arm_decode_field (given, 19, 20);
5357         if ((size == 0) || (size == 3))
5358           return TRUE;
5359         else
5360           return FALSE;
5361       }
5362
5363     case MVE_VMAXA:
5364     case MVE_VMINA:
5365     case MVE_VMAXV:
5366     case MVE_VMAXAV:
5367     case MVE_VMINV:
5368     case MVE_VMINAV:
5369     case MVE_VQRSHL_T2:
5370     case MVE_VQSHL_T1:
5371     case MVE_VRSHL_T2:
5372     case MVE_VSHL_T2:
5373     case MVE_VSHLL_T2:
5374     case MVE_VADDV:
5375     case MVE_VMOVN:
5376     case MVE_VQMOVUN:
5377     case MVE_VQMOVN:
5378       if (arm_decode_field (given, 18, 19) == 3)
5379         return TRUE;
5380       else
5381         return FALSE;
5382
5383     case MVE_VMLSLDAV:
5384     case MVE_VRMLSLDAVH:
5385     case MVE_VMLALDAV:
5386     case MVE_VADDLV:
5387       if (arm_decode_field (given, 20, 22) == 7)
5388         return TRUE;
5389       else
5390         return FALSE;
5391
5392     case MVE_VRMLALDAVH:
5393       if ((arm_decode_field (given, 20, 22) & 6) == 6)
5394         return TRUE;
5395       else
5396         return FALSE;
5397
5398     case MVE_VDWDUP:
5399     case MVE_VIWDUP:
5400       if ((arm_decode_field (given, 20, 21) == 3)
5401           || (arm_decode_field (given, 1, 3) == 7))
5402         return TRUE;
5403       else
5404         return FALSE;
5405
5406
5407     case MVE_VSHLL_T1:
5408       if (arm_decode_field (given, 16, 18) == 0)
5409         {
5410           unsigned long sz = arm_decode_field (given, 19, 20);
5411
5412           if ((sz == 1) || (sz == 2))
5413             return TRUE;
5414           else
5415             return FALSE;
5416         }
5417       else
5418         return FALSE;
5419
5420     case MVE_VQSHL_T2:
5421     case MVE_VQSHLU_T3:
5422     case MVE_VRSHR:
5423     case MVE_VSHL_T1:
5424     case MVE_VSHR:
5425     case MVE_VSLI:
5426     case MVE_VSRI:
5427       if (arm_decode_field (given, 19, 21) == 0)
5428         return TRUE;
5429       else
5430         return FALSE;
5431
5432     case MVE_VCTP:
5433     if (arm_decode_field (given, 16, 19) == 0xf)
5434       return TRUE;
5435     else
5436       return FALSE;
5437
5438     default:
5439     case MVE_VADD_FP_T1:
5440     case MVE_VADD_FP_T2:
5441     case MVE_VADD_VEC_T1:
5442       return FALSE;
5443
5444     }
5445 }
5446
5447 static void
5448 print_mve_vld_str_addr (struct disassemble_info *info,
5449                         unsigned long given,
5450                         enum mve_instructions matched_insn)
5451 {
5452   void *stream = info->stream;
5453   fprintf_ftype func = info->fprintf_func;
5454
5455   unsigned long p, w, gpr, imm, add, mod_imm;
5456
5457   imm = arm_decode_field (given, 0, 6);
5458   mod_imm = imm;
5459
5460   switch (matched_insn)
5461     {
5462     case MVE_VLDRB_T1:
5463     case MVE_VSTRB_T1:
5464       gpr = arm_decode_field (given, 16, 18);
5465       break;
5466
5467     case MVE_VLDRH_T2:
5468     case MVE_VSTRH_T2:
5469       gpr = arm_decode_field (given, 16, 18);
5470       mod_imm = imm << 1;
5471       break;
5472
5473     case MVE_VLDRH_T6:
5474     case MVE_VSTRH_T6:
5475       gpr = arm_decode_field (given, 16, 19);
5476       mod_imm = imm << 1;
5477       break;
5478
5479     case MVE_VLDRW_T7:
5480     case MVE_VSTRW_T7:
5481       gpr = arm_decode_field (given, 16, 19);
5482       mod_imm = imm << 2;
5483       break;
5484
5485     case MVE_VLDRB_T5:
5486     case MVE_VSTRB_T5:
5487       gpr = arm_decode_field (given, 16, 19);
5488       break;
5489
5490     default:
5491       return;
5492     }
5493
5494   p = arm_decode_field (given, 24, 24);
5495   w = arm_decode_field (given, 21, 21);
5496
5497   add = arm_decode_field (given, 23, 23);
5498
5499   char * add_sub;
5500
5501   /* Don't print anything for '+' as it is implied.  */
5502   if (add == 1)
5503     add_sub = "";
5504   else
5505     add_sub = "-";
5506
5507   if (p == 1)
5508     {
5509       /* Offset mode.  */
5510       if (w == 0)
5511         func (stream, "[%s, #%s%lu]", arm_regnames[gpr], add_sub, mod_imm);
5512       /* Pre-indexed mode.  */
5513       else
5514         func (stream, "[%s, #%s%lu]!", arm_regnames[gpr], add_sub, mod_imm);
5515     }
5516   else if ((p == 0) && (w == 1))
5517     /* Post-index mode.  */
5518     func (stream, "[%s], #%s%lu", arm_regnames[gpr], add_sub, mod_imm);
5519 }
5520
5521 /* Return FALSE if GIVEN is not an undefined encoding for MATCHED_INSN.
5522    Otherwise, return TRUE and set UNDEFINED_CODE to give a reason as to why
5523    this encoding is undefined.  */
5524
5525 static bfd_boolean
5526 is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
5527                   enum mve_undefined *undefined_code)
5528 {
5529   *undefined_code = UNDEF_NONE;
5530
5531   switch (matched_insn)
5532     {
5533     case MVE_VDUP:
5534       if (arm_decode_field_multiple (given, 5, 5, 22, 22) == 3)
5535         {
5536           *undefined_code = UNDEF_SIZE_3;
5537           return TRUE;
5538         }
5539       else
5540         return FALSE;
5541
5542     case MVE_VMUL_VEC_T1:
5543     case MVE_VABD_VEC:
5544     case MVE_VADD_VEC_T1:
5545     case MVE_VSUB_VEC_T1:
5546     case MVE_VQDMULH_T1:
5547     case MVE_VQRDMULH_T2:
5548     case MVE_VRHADD:
5549     case MVE_VHADD_T1:
5550     case MVE_VHSUB_T1:
5551       if (arm_decode_field (given, 20, 21) == 3)
5552         {
5553           *undefined_code = UNDEF_SIZE_3;
5554           return TRUE;
5555         }
5556       else
5557         return FALSE;
5558
5559     case MVE_VLDRB_T1:
5560       if (arm_decode_field (given, 7, 8) == 3)
5561         {
5562           *undefined_code = UNDEF_SIZE_3;
5563           return TRUE;
5564         }
5565       else
5566         return FALSE;
5567
5568     case MVE_VLDRH_T2:
5569       if (arm_decode_field (given, 7, 8) <= 1)
5570         {
5571           *undefined_code = UNDEF_SIZE_LE_1;
5572           return TRUE;
5573         }
5574       else
5575         return FALSE;
5576
5577     case MVE_VSTRB_T1:
5578       if ((arm_decode_field (given, 7, 8) == 0))
5579         {
5580           *undefined_code = UNDEF_SIZE_0;
5581           return TRUE;
5582         }
5583       else
5584         return FALSE;
5585
5586     case MVE_VSTRH_T2:
5587       if ((arm_decode_field (given, 7, 8) <= 1))
5588         {
5589           *undefined_code = UNDEF_SIZE_LE_1;
5590           return TRUE;
5591         }
5592       else
5593         return FALSE;
5594
5595     case MVE_VLDRB_GATHER_T1:
5596       if (arm_decode_field (given, 7, 8) == 3)
5597         {
5598           *undefined_code = UNDEF_SIZE_3;
5599           return TRUE;
5600         }
5601       else if ((arm_decode_field (given, 28, 28) == 0)
5602                && (arm_decode_field (given, 7, 8) == 0))
5603         {
5604           *undefined_code = UNDEF_NOT_UNS_SIZE_0;
5605           return TRUE;
5606         }
5607       else
5608         return FALSE;
5609
5610     case MVE_VLDRH_GATHER_T2:
5611       if (arm_decode_field (given, 7, 8) == 3)
5612         {
5613           *undefined_code = UNDEF_SIZE_3;
5614           return TRUE;
5615         }
5616       else if ((arm_decode_field (given, 28, 28) == 0)
5617                && (arm_decode_field (given, 7, 8) == 1))
5618         {
5619           *undefined_code = UNDEF_NOT_UNS_SIZE_1;
5620           return TRUE;
5621         }
5622       else if (arm_decode_field (given, 7, 8) == 0)
5623         {
5624           *undefined_code = UNDEF_SIZE_0;
5625           return TRUE;
5626         }
5627       else
5628         return FALSE;
5629
5630     case MVE_VLDRW_GATHER_T3:
5631       if (arm_decode_field (given, 7, 8) != 2)
5632         {
5633           *undefined_code = UNDEF_SIZE_NOT_2;
5634           return TRUE;
5635         }
5636       else if (arm_decode_field (given, 28, 28) == 0)
5637         {
5638           *undefined_code = UNDEF_NOT_UNSIGNED;
5639           return TRUE;
5640         }
5641       else
5642         return FALSE;
5643
5644     case MVE_VLDRD_GATHER_T4:
5645       if (arm_decode_field (given, 7, 8) != 3)
5646         {
5647           *undefined_code = UNDEF_SIZE_NOT_3;
5648           return TRUE;
5649         }
5650       else if (arm_decode_field (given, 28, 28) == 0)
5651         {
5652           *undefined_code = UNDEF_NOT_UNSIGNED;
5653           return TRUE;
5654         }
5655       else
5656         return FALSE;
5657
5658     case MVE_VSTRB_SCATTER_T1:
5659       if (arm_decode_field (given, 7, 8) == 3)
5660         {
5661           *undefined_code = UNDEF_SIZE_3;
5662           return TRUE;
5663         }
5664       else
5665         return FALSE;
5666
5667     case MVE_VSTRH_SCATTER_T2:
5668       {
5669         unsigned long size = arm_decode_field (given, 7, 8);
5670         if (size == 3)
5671           {
5672             *undefined_code = UNDEF_SIZE_3;
5673             return TRUE;
5674           }
5675         else if (size == 0)
5676           {
5677             *undefined_code = UNDEF_SIZE_0;
5678             return TRUE;
5679           }
5680         else
5681           return FALSE;
5682       }
5683
5684     case MVE_VSTRW_SCATTER_T3:
5685       if (arm_decode_field (given, 7, 8) != 2)
5686         {
5687           *undefined_code = UNDEF_SIZE_NOT_2;
5688           return TRUE;
5689         }
5690       else
5691         return FALSE;
5692
5693     case MVE_VSTRD_SCATTER_T4:
5694       if (arm_decode_field (given, 7, 8) != 3)
5695         {
5696           *undefined_code = UNDEF_SIZE_NOT_3;
5697           return TRUE;
5698         }
5699       else
5700         return FALSE;
5701
5702     case MVE_VCVT_FP_FIX_VEC:
5703       {
5704         unsigned long imm6 = arm_decode_field (given, 16, 21);
5705         if ((imm6 & 0x20) == 0)
5706           {
5707             *undefined_code = UNDEF_VCVT_IMM6;
5708             return TRUE;
5709           }
5710
5711         if ((arm_decode_field (given, 9, 9) == 0)
5712             && ((imm6 & 0x30) == 0x20))
5713           {
5714             *undefined_code = UNDEF_VCVT_FSI_IMM6;
5715             return TRUE;
5716           }
5717
5718         return FALSE;
5719       }
5720
5721     case MVE_VNEG_FP:
5722     case MVE_VABS_FP:
5723     case MVE_VCVT_BETWEEN_FP_INT:
5724     case MVE_VCVT_FROM_FP_TO_INT:
5725       {
5726         unsigned long size = arm_decode_field (given, 18, 19);
5727         if (size == 0)
5728           {
5729             *undefined_code = UNDEF_SIZE_0;
5730             return TRUE;
5731           }
5732         else if (size == 3)
5733           {
5734             *undefined_code = UNDEF_SIZE_3;
5735             return TRUE;
5736           }
5737         else
5738           return FALSE;
5739       }
5740
5741     case MVE_VMOV_VEC_LANE_TO_GP:
5742       {
5743         unsigned long op1 = arm_decode_field (given, 21, 22);
5744         unsigned long op2 = arm_decode_field (given, 5, 6);
5745         unsigned long u = arm_decode_field (given, 23, 23);
5746
5747         if ((op2 == 0) && (u == 1))
5748           {
5749             if ((op1 == 0) || (op1 == 1))
5750               {
5751                 *undefined_code = UNDEF_BAD_U_OP1_OP2;
5752                 return TRUE;
5753               }
5754             else
5755               return FALSE;
5756           }
5757         else if (op2 == 2)
5758           {
5759             if ((op1 == 0) || (op1 == 1))
5760               {
5761                 *undefined_code = UNDEF_BAD_OP1_OP2;
5762                 return TRUE;
5763               }
5764             else
5765               return FALSE;
5766           }
5767
5768         return FALSE;
5769       }
5770
5771     case MVE_VMOV_GP_TO_VEC_LANE:
5772       if (arm_decode_field (given, 5, 6) == 2)
5773         {
5774           unsigned long op1 = arm_decode_field (given, 21, 22);
5775           if ((op1 == 0) || (op1 == 1))
5776             {
5777               *undefined_code = UNDEF_BAD_OP1_OP2;
5778               return TRUE;
5779             }
5780           else
5781             return FALSE;
5782         }
5783       else
5784         return FALSE;
5785
5786     case MVE_VMOV_IMM_TO_VEC:
5787       if (arm_decode_field (given, 5, 5) == 0)
5788       {
5789         unsigned long cmode = arm_decode_field (given, 8, 11);
5790
5791         if (((cmode & 9) == 1) || ((cmode & 5) == 1))
5792           {
5793             *undefined_code = UNDEF_OP_0_BAD_CMODE;
5794             return TRUE;
5795           }
5796         else
5797           return FALSE;
5798       }
5799       else
5800         return FALSE;
5801
5802     case MVE_VSHLL_T2:
5803     case MVE_VMOVN:
5804       if (arm_decode_field (given, 18, 19) == 2)
5805         {
5806           *undefined_code = UNDEF_SIZE_2;
5807           return TRUE;
5808         }
5809       else
5810         return FALSE;
5811
5812     case MVE_VRMLALDAVH:
5813     case MVE_VMLADAV_T1:
5814     case MVE_VMLADAV_T2:
5815     case MVE_VMLALDAV:
5816       if ((arm_decode_field (given, 28, 28) == 1)
5817           && (arm_decode_field (given, 12, 12) == 1))
5818         {
5819           *undefined_code = UNDEF_XCHG_UNS;
5820           return TRUE;
5821         }
5822       else
5823         return FALSE;
5824
5825     case MVE_VQSHRN:
5826     case MVE_VQSHRUN:
5827     case MVE_VSHLL_T1:
5828     case MVE_VSHRN:
5829       {
5830         unsigned long sz = arm_decode_field (given, 19, 20);
5831         if (sz == 1)
5832           return FALSE;
5833         else if ((sz & 2) == 2)
5834           return FALSE;
5835         else
5836           {
5837             *undefined_code = UNDEF_SIZE;
5838             return TRUE;
5839           }
5840       }
5841       break;
5842
5843     case MVE_VQSHL_T2:
5844     case MVE_VQSHLU_T3:
5845     case MVE_VRSHR:
5846     case MVE_VSHL_T1:
5847     case MVE_VSHR:
5848     case MVE_VSLI:
5849     case MVE_VSRI:
5850       {
5851         unsigned long sz = arm_decode_field (given, 19, 21);
5852         if ((sz & 7) == 1)
5853           return FALSE;
5854         else if ((sz & 6) == 2)
5855           return FALSE;
5856         else if ((sz & 4) == 4)
5857           return FALSE;
5858         else
5859           {
5860             *undefined_code = UNDEF_SIZE;
5861             return TRUE;
5862           }
5863       }
5864
5865     case MVE_VQRSHRN:
5866     case MVE_VQRSHRUN:
5867       if (arm_decode_field (given, 19, 20) == 0)
5868         {
5869           *undefined_code = UNDEF_SIZE_0;
5870           return TRUE;
5871         }
5872       else
5873         return FALSE;
5874
5875     case MVE_VABS_VEC:
5876         if (arm_decode_field (given, 18, 19) == 3)
5877         {
5878           *undefined_code = UNDEF_SIZE_3;
5879           return TRUE;
5880         }
5881         else
5882           return FALSE;
5883
5884     case MVE_VNEG_VEC:
5885     case MVE_VCLS:
5886     case MVE_VCLZ:
5887       if (arm_decode_field (given, 18, 19) == 3)
5888         {
5889           *undefined_code = UNDEF_SIZE_3;
5890           return TRUE;
5891         }
5892       else
5893         return FALSE;
5894
5895     default:
5896       return FALSE;
5897     }
5898 }
5899
5900 /* Return FALSE if GIVEN is not an unpredictable encoding for MATCHED_INSN.
5901    Otherwise, return TRUE and set UNPREDICTABLE_CODE to give a reason as to
5902    why this encoding is unpredictable.  */
5903
5904 static bfd_boolean
5905 is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
5906                       enum mve_unpredictable *unpredictable_code)
5907 {
5908   *unpredictable_code = UNPRED_NONE;
5909
5910   switch (matched_insn)
5911     {
5912     case MVE_VCMP_FP_T2:
5913     case MVE_VPT_FP_T2:
5914       if ((arm_decode_field (given, 12, 12) == 0)
5915           && (arm_decode_field (given, 5, 5) == 1))
5916         {
5917           *unpredictable_code = UNPRED_FCA_0_FCB_1;
5918           return TRUE;
5919         }
5920       else
5921         return FALSE;
5922
5923     case MVE_VPT_VEC_T4:
5924     case MVE_VPT_VEC_T5:
5925     case MVE_VPT_VEC_T6:
5926     case MVE_VCMP_VEC_T4:
5927     case MVE_VCMP_VEC_T5:
5928     case MVE_VCMP_VEC_T6:
5929       if (arm_decode_field (given, 0, 3) == 0xd)
5930         {
5931           *unpredictable_code = UNPRED_R13;
5932           return TRUE;
5933         }
5934       else
5935         return FALSE;
5936
5937     case MVE_VDUP:
5938       {
5939         unsigned long gpr = arm_decode_field (given, 12, 15);
5940         if (gpr == 0xd)
5941           {
5942             *unpredictable_code = UNPRED_R13;
5943             return TRUE;
5944           }
5945         else if (gpr == 0xf)
5946           {
5947             *unpredictable_code = UNPRED_R15;
5948             return TRUE;
5949           }
5950
5951         return FALSE;
5952       }
5953
5954     case MVE_VMUL_FP_T2:
5955     case MVE_VMUL_VEC_T2:
5956     case MVE_VMLA:
5957     case MVE_VBRSR:
5958     case MVE_VADD_FP_T2:
5959     case MVE_VSUB_FP_T2:
5960     case MVE_VADD_VEC_T2:
5961     case MVE_VSUB_VEC_T2:
5962     case MVE_VQRSHL_T2:
5963     case MVE_VQSHL_T1:
5964     case MVE_VRSHL_T2:
5965     case MVE_VSHL_T2:
5966     case MVE_VSHLC:
5967     case MVE_VQDMLAH:
5968     case MVE_VQRDMLAH:
5969     case MVE_VQDMLASH:
5970     case MVE_VQRDMLASH:
5971     case MVE_VQDMULH_T3:
5972     case MVE_VQRDMULH_T4:
5973     case MVE_VMLAS:
5974     case MVE_VFMA_FP_SCALAR:
5975     case MVE_VFMAS_FP_SCALAR:
5976     case MVE_VHADD_T2:
5977     case MVE_VHSUB_T2:
5978       {
5979         unsigned long gpr = arm_decode_field (given, 0, 3);
5980         if (gpr == 0xd)
5981           {
5982             *unpredictable_code = UNPRED_R13;
5983             return TRUE;
5984           }
5985         else if (gpr == 0xf)
5986           {
5987             *unpredictable_code = UNPRED_R15;
5988             return TRUE;
5989           }
5990
5991         return FALSE;
5992       }
5993
5994     case MVE_VLD2:
5995     case MVE_VST2:
5996       {
5997         unsigned long rn = arm_decode_field (given, 16, 19);
5998
5999         if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6000           {
6001             *unpredictable_code = UNPRED_R13_AND_WB;
6002             return TRUE;
6003           }
6004
6005         if (rn == 0xf)
6006           {
6007             *unpredictable_code = UNPRED_R15;
6008             return TRUE;
6009           }
6010
6011         if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 6)
6012           {
6013             *unpredictable_code = UNPRED_Q_GT_6;
6014             return TRUE;
6015           }
6016         else
6017           return FALSE;
6018       }
6019
6020     case MVE_VLD4:
6021     case MVE_VST4:
6022       {
6023         unsigned long rn = arm_decode_field (given, 16, 19);
6024
6025         if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6026           {
6027             *unpredictable_code = UNPRED_R13_AND_WB;
6028             return TRUE;
6029           }
6030
6031         if (rn == 0xf)
6032           {
6033             *unpredictable_code = UNPRED_R15;
6034             return TRUE;
6035           }
6036
6037         if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 4)
6038           {
6039             *unpredictable_code = UNPRED_Q_GT_4;
6040             return TRUE;
6041           }
6042         else
6043           return FALSE;
6044       }
6045
6046     case MVE_VLDRB_T5:
6047     case MVE_VLDRH_T6:
6048     case MVE_VLDRW_T7:
6049     case MVE_VSTRB_T5:
6050     case MVE_VSTRH_T6:
6051     case MVE_VSTRW_T7:
6052       {
6053         unsigned long rn = arm_decode_field (given, 16, 19);
6054
6055         if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6056           {
6057             *unpredictable_code = UNPRED_R13_AND_WB;
6058             return TRUE;
6059           }
6060         else if (rn == 0xf)
6061           {
6062             *unpredictable_code = UNPRED_R15;
6063             return TRUE;
6064           }
6065         else
6066           return FALSE;
6067       }
6068
6069     case MVE_VLDRB_GATHER_T1:
6070       if (arm_decode_field (given, 0, 0) == 1)
6071         {
6072           *unpredictable_code = UNPRED_OS;
6073           return TRUE;
6074         }
6075
6076       /*  fall through.  */
6077       /* To handle common code with T2-T4 variants.  */
6078     case MVE_VLDRH_GATHER_T2:
6079     case MVE_VLDRW_GATHER_T3:
6080     case MVE_VLDRD_GATHER_T4:
6081       {
6082         unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6083         unsigned long qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6084
6085         if (qd == qm)
6086           {
6087             *unpredictable_code = UNPRED_Q_REGS_EQUAL;
6088             return TRUE;
6089           }
6090
6091         if (arm_decode_field (given, 16, 19) == 0xf)
6092           {
6093             *unpredictable_code = UNPRED_R15;
6094             return TRUE;
6095           }
6096
6097         return FALSE;
6098       }
6099
6100     case MVE_VLDRW_GATHER_T5:
6101     case MVE_VLDRD_GATHER_T6:
6102       {
6103         unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6104         unsigned long qm = arm_decode_field_multiple (given, 17, 19, 7, 7);
6105
6106         if (qd == qm)
6107           {
6108             *unpredictable_code = UNPRED_Q_REGS_EQUAL;
6109             return TRUE;
6110           }
6111         else
6112           return FALSE;
6113       }
6114
6115     case MVE_VSTRB_SCATTER_T1:
6116       if (arm_decode_field (given, 16, 19) == 0xf)
6117         {
6118           *unpredictable_code = UNPRED_R15;
6119           return TRUE;
6120         }
6121       else if (arm_decode_field (given, 0, 0) == 1)
6122         {
6123           *unpredictable_code = UNPRED_OS;
6124           return TRUE;
6125         }
6126       else
6127         return FALSE;
6128
6129     case MVE_VSTRH_SCATTER_T2:
6130     case MVE_VSTRW_SCATTER_T3:
6131     case MVE_VSTRD_SCATTER_T4:
6132       if (arm_decode_field (given, 16, 19) == 0xf)
6133         {
6134           *unpredictable_code = UNPRED_R15;
6135           return TRUE;
6136         }
6137       else
6138         return FALSE;
6139
6140     case MVE_VMOV2_VEC_LANE_TO_GP:
6141     case MVE_VMOV2_GP_TO_VEC_LANE:
6142     case MVE_VCVT_BETWEEN_FP_INT:
6143     case MVE_VCVT_FROM_FP_TO_INT:
6144       {
6145         unsigned long rt = arm_decode_field (given, 0, 3);
6146         unsigned long rt2 = arm_decode_field (given, 16, 19);
6147
6148         if ((rt == 0xd) || (rt2 == 0xd))
6149           {
6150             *unpredictable_code = UNPRED_R13;
6151             return TRUE;
6152           }
6153         else if ((rt == 0xf) || (rt2 == 0xf))
6154           {
6155             *unpredictable_code = UNPRED_R15;
6156             return TRUE;
6157           }
6158         else if (rt == rt2)
6159           {
6160             *unpredictable_code = UNPRED_GP_REGS_EQUAL;
6161             return TRUE;
6162           }
6163
6164         return FALSE;
6165       }
6166
6167     case MVE_VMAXV:
6168     case MVE_VMAXAV:
6169     case MVE_VMAXNMV_FP:
6170     case MVE_VMAXNMAV_FP:
6171     case MVE_VMINNMV_FP:
6172     case MVE_VMINNMAV_FP:
6173     case MVE_VMINV:
6174     case MVE_VMINAV:
6175     case MVE_VABAV:
6176     case MVE_VMOV_HFP_TO_GP:
6177     case MVE_VMOV_GP_TO_VEC_LANE:
6178     case MVE_VMOV_VEC_LANE_TO_GP:
6179       {
6180         unsigned long rda = arm_decode_field (given, 12, 15);
6181         if (rda == 0xd)
6182           {
6183             *unpredictable_code = UNPRED_R13;
6184             return TRUE;
6185           }
6186         else if (rda == 0xf)
6187           {
6188             *unpredictable_code = UNPRED_R15;
6189             return TRUE;
6190           }
6191
6192         return FALSE;
6193       }
6194
6195     case MVE_VQRDMLADH:
6196     case MVE_VQDMLSDH:
6197     case MVE_VQRDMLSDH:
6198     case MVE_VQDMLADH:
6199     case MVE_VMULL_INT:
6200       {
6201         unsigned long Qd;
6202         unsigned long Qm;
6203         unsigned long Qn;
6204
6205         if (arm_decode_field (given, 20, 21) == 2)
6206           {
6207             Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6208             Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6209             Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6210
6211             if ((Qd == Qn) || (Qd == Qm))
6212               {
6213                 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2;
6214                 return TRUE;
6215               }
6216             else
6217               return FALSE;
6218           }
6219         else
6220           return FALSE;
6221       }
6222
6223     case MVE_VCMUL_FP:
6224     case MVE_VQDMULL_T1:
6225       {
6226         unsigned long Qd;
6227         unsigned long Qm;
6228         unsigned long Qn;
6229
6230         if (arm_decode_field (given, 28, 28) == 1)
6231           {
6232             Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6233             Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6234             Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6235
6236             if ((Qd == Qn) || (Qd == Qm))
6237               {
6238                 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6239                 return TRUE;
6240               }
6241             else
6242               return FALSE;
6243           }
6244         else
6245           return FALSE;
6246       }
6247
6248     case MVE_VQDMULL_T2:
6249       {
6250         unsigned long gpr = arm_decode_field (given, 0, 3);
6251         if (gpr == 0xd)
6252           {
6253             *unpredictable_code = UNPRED_R13;
6254             return TRUE;
6255           }
6256         else if (gpr == 0xf)
6257           {
6258             *unpredictable_code = UNPRED_R15;
6259             return TRUE;
6260           }
6261
6262         if (arm_decode_field (given, 28, 28) == 1)
6263           {
6264             unsigned long Qd
6265               = arm_decode_field_multiple (given, 13, 15, 22, 22);
6266             unsigned long Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6267
6268             if ((Qd == Qn))
6269               {
6270                 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6271                 return TRUE;
6272               }
6273             else
6274               return FALSE;
6275           }
6276
6277         return FALSE;
6278       }
6279
6280     case MVE_VMLSLDAV:
6281     case MVE_VRMLSLDAVH:
6282     case MVE_VMLALDAV:
6283     case MVE_VADDLV:
6284       if (arm_decode_field (given, 20, 22) == 6)
6285         {
6286           *unpredictable_code = UNPRED_R13;
6287           return TRUE;
6288         }
6289       else
6290         return FALSE;
6291
6292     case MVE_VDWDUP:
6293     case MVE_VIWDUP:
6294       if (arm_decode_field (given, 1, 3) == 6)
6295         {
6296           *unpredictable_code = UNPRED_R13;
6297           return TRUE;
6298         }
6299       else
6300         return FALSE;
6301
6302     case MVE_VCADD_VEC:
6303     case MVE_VHCADD:
6304       {
6305         unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6306         unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6307         if ((Qd == Qm) && arm_decode_field (given, 20, 21) == 2)
6308           {
6309             *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2;
6310             return TRUE;
6311           }
6312         else
6313           return FALSE;
6314       }
6315
6316     case MVE_VCADD_FP:
6317       {
6318         unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6319         unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6320         if ((Qd == Qm) && arm_decode_field (given, 20, 20) == 1)
6321           {
6322             *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6323             return TRUE;
6324           }
6325         else
6326           return FALSE;
6327       }
6328
6329     case MVE_VCMLA_FP:
6330       {
6331         unsigned long Qda;
6332         unsigned long Qm;
6333         unsigned long Qn;
6334
6335         if (arm_decode_field (given, 20, 20) == 1)
6336           {
6337             Qda = arm_decode_field_multiple (given, 13, 15, 22, 22);
6338             Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6339             Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6340
6341             if ((Qda == Qn) || (Qda == Qm))
6342               {
6343                 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6344                 return TRUE;
6345               }
6346             else
6347               return FALSE;
6348           }
6349         else
6350           return FALSE;
6351
6352       }
6353
6354     case MVE_VCTP:
6355       if (arm_decode_field (given, 16, 19) == 0xd)
6356         {
6357           *unpredictable_code = UNPRED_R13;
6358           return TRUE;
6359         }
6360       else
6361         return FALSE;
6362
6363     default:
6364       return FALSE;
6365     }
6366 }
6367
6368 static void
6369 print_mve_vmov_index (struct disassemble_info *info, unsigned long given)
6370 {
6371   unsigned long op1 = arm_decode_field (given, 21, 22);
6372   unsigned long op2 = arm_decode_field (given, 5, 6);
6373   unsigned long h = arm_decode_field (given, 16, 16);
6374   unsigned long index, esize, targetBeat, idx;
6375   void *stream = info->stream;
6376   fprintf_ftype func = info->fprintf_func;
6377
6378   if ((op1 & 0x2) == 0x2)
6379     {
6380       index = op2;
6381       esize = 8;
6382     }
6383   else if (((op1 & 0x2) == 0x0) && ((op2 & 0x1) == 0x1))
6384     {
6385       index = op2  >> 1;
6386       esize = 16;
6387     }
6388   else if (((op1 & 0x2) == 0) && ((op2 & 0x3) == 0))
6389     {
6390       index = 0;
6391       esize = 32;
6392     }
6393   else
6394     {
6395       func (stream, "<undefined index>");
6396       return;
6397     }
6398
6399   targetBeat =  (op1 & 0x1) | (h << 1);
6400   idx = index + targetBeat * (32/esize);
6401
6402   func (stream, "%lu", idx);
6403 }
6404
6405 /* Print neon and mve 8-bit immediate that can be a 8, 16, 32, or 64-bits
6406    in length and integer of floating-point type.  */
6407 static void
6408 print_simd_imm8 (struct disassemble_info *info, unsigned long given,
6409                  unsigned int ibit_loc, const struct mopcode32 *insn)
6410 {
6411   int bits = 0;
6412   int cmode = (given >> 8) & 0xf;
6413   int op = (given >> 5) & 0x1;
6414   unsigned long value = 0, hival = 0;
6415   unsigned shift;
6416   int size = 0;
6417   int isfloat = 0;
6418   void *stream = info->stream;
6419   fprintf_ftype func = info->fprintf_func;
6420
6421   /* On Neon the 'i' bit is at bit 24, on mve it is
6422      at bit 28.  */
6423   bits |= ((given >> ibit_loc) & 1) << 7;
6424   bits |= ((given >> 16) & 7) << 4;
6425   bits |= ((given >> 0) & 15) << 0;
6426
6427   if (cmode < 8)
6428     {
6429       shift = (cmode >> 1) & 3;
6430       value = (unsigned long) bits << (8 * shift);
6431       size = 32;
6432     }
6433   else if (cmode < 12)
6434     {
6435       shift = (cmode >> 1) & 1;
6436       value = (unsigned long) bits << (8 * shift);
6437       size = 16;
6438     }
6439   else if (cmode < 14)
6440     {
6441       shift = (cmode & 1) + 1;
6442       value = (unsigned long) bits << (8 * shift);
6443       value |= (1ul << (8 * shift)) - 1;
6444       size = 32;
6445     }
6446   else if (cmode == 14)
6447     {
6448       if (op)
6449         {
6450           /* Bit replication into bytes.  */
6451           int ix;
6452           unsigned long mask;
6453
6454           value = 0;
6455           hival = 0;
6456           for (ix = 7; ix >= 0; ix--)
6457             {
6458               mask = ((bits >> ix) & 1) ? 0xff : 0;
6459               if (ix <= 3)
6460                 value = (value << 8) | mask;
6461               else
6462                 hival = (hival << 8) | mask;
6463             }
6464           size = 64;
6465         }
6466       else
6467         {
6468           /* Byte replication.  */
6469           value = (unsigned long) bits;
6470           size = 8;
6471         }
6472     }
6473   else if (!op)
6474     {
6475       /* Floating point encoding.  */
6476       int tmp;
6477
6478       value = (unsigned long)  (bits & 0x7f) << 19;
6479       value |= (unsigned long) (bits & 0x80) << 24;
6480       tmp = bits & 0x40 ? 0x3c : 0x40;
6481       value |= (unsigned long) tmp << 24;
6482       size = 32;
6483       isfloat = 1;
6484     }
6485   else
6486     {
6487       func (stream, "<illegal constant %.8x:%x:%x>",
6488             bits, cmode, op);
6489       size = 32;
6490       return;
6491     }
6492
6493   // printU determines whether the immediate value should be printed as
6494   // unsigned.
6495   unsigned printU = 0;
6496   switch (insn->mve_op)
6497     {
6498     default:
6499       break;
6500     // We want this for instructions that don't have a 'signed' type
6501     case MVE_VBIC_IMM:
6502     case MVE_VORR_IMM:
6503     case MVE_VMVN_IMM:
6504     case MVE_VMOV_IMM_TO_VEC:
6505       printU = 1;
6506       break;
6507     }
6508   switch (size)
6509     {
6510     case 8:
6511       func (stream, "#%ld\t; 0x%.2lx", value, value);
6512       break;
6513
6514     case 16:
6515       func (stream,
6516             printU
6517             ? "#%lu\t; 0x%.4lx"
6518             : "#%ld\t; 0x%.4lx", value, value);
6519       break;
6520
6521     case 32:
6522       if (isfloat)
6523         {
6524           unsigned char valbytes[4];
6525           double fvalue;
6526
6527           /* Do this a byte at a time so we don't have to
6528              worry about the host's endianness.  */
6529           valbytes[0] = value & 0xff;
6530           valbytes[1] = (value >> 8) & 0xff;
6531           valbytes[2] = (value >> 16) & 0xff;
6532           valbytes[3] = (value >> 24) & 0xff;
6533
6534           floatformat_to_double
6535             (& floatformat_ieee_single_little, valbytes,
6536              & fvalue);
6537
6538           func (stream, "#%.7g\t; 0x%.8lx", fvalue,
6539                 value);
6540         }
6541       else
6542         func (stream,
6543               printU
6544               ? "#%lu\t; 0x%.8lx"
6545               : "#%ld\t; 0x%.8lx",
6546               (long) (((value & 0x80000000L) != 0)
6547                       && !printU
6548                       ? value | ~0xffffffffL : value),
6549               value);
6550       break;
6551
6552     case 64:
6553       func (stream, "#0x%.8lx%.8lx", hival, value);
6554       break;
6555
6556     default:
6557       abort ();
6558     }
6559
6560 }
6561
6562 static void
6563 print_mve_undefined (struct disassemble_info *info,
6564                      enum mve_undefined undefined_code)
6565 {
6566   void *stream = info->stream;
6567   fprintf_ftype func = info->fprintf_func;
6568
6569   func (stream, "\t\tundefined instruction: ");
6570
6571   switch (undefined_code)
6572     {
6573     case UNDEF_SIZE:
6574       func (stream, "illegal size");
6575       break;
6576
6577     case UNDEF_SIZE_0:
6578       func (stream, "size equals zero");
6579       break;
6580
6581     case UNDEF_SIZE_2:
6582       func (stream, "size equals two");
6583       break;
6584
6585     case UNDEF_SIZE_3:
6586       func (stream, "size equals three");
6587       break;
6588
6589     case UNDEF_SIZE_LE_1:
6590       func (stream, "size <= 1");
6591       break;
6592
6593     case UNDEF_SIZE_NOT_2:
6594       func (stream, "size not equal to 2");
6595       break;
6596
6597     case UNDEF_SIZE_NOT_3:
6598       func (stream, "size not equal to 3");
6599       break;
6600
6601     case UNDEF_NOT_UNS_SIZE_0:
6602       func (stream, "not unsigned and size = zero");
6603       break;
6604
6605     case UNDEF_NOT_UNS_SIZE_1:
6606       func (stream, "not unsigned and size = one");
6607       break;
6608
6609     case UNDEF_NOT_UNSIGNED:
6610       func (stream, "not unsigned");
6611       break;
6612
6613     case UNDEF_VCVT_IMM6:
6614       func (stream, "invalid imm6");
6615       break;
6616
6617     case UNDEF_VCVT_FSI_IMM6:
6618       func (stream, "fsi = 0 and invalid imm6");
6619       break;
6620
6621     case UNDEF_BAD_OP1_OP2:
6622       func (stream, "bad size with op2 = 2 and op1 = 0 or 1");
6623       break;
6624
6625     case UNDEF_BAD_U_OP1_OP2:
6626       func (stream, "unsigned with op2 = 0 and op1 = 0 or 1");
6627       break;
6628
6629     case UNDEF_OP_0_BAD_CMODE:
6630       func (stream, "op field equal 0 and bad cmode");
6631       break;
6632
6633     case UNDEF_XCHG_UNS:
6634       func (stream, "exchange and unsigned together");
6635       break;
6636
6637     case UNDEF_NONE:
6638       break;
6639     }
6640
6641 }
6642
6643 static void
6644 print_mve_unpredictable (struct disassemble_info *info,
6645                          enum mve_unpredictable unpredict_code)
6646 {
6647   void *stream = info->stream;
6648   fprintf_ftype func = info->fprintf_func;
6649
6650   func (stream, "%s: ", UNPREDICTABLE_INSTRUCTION);
6651
6652   switch (unpredict_code)
6653     {
6654     case UNPRED_IT_BLOCK:
6655       func (stream, "mve instruction in it block");
6656       break;
6657
6658     case UNPRED_FCA_0_FCB_1:
6659       func (stream, "condition bits, fca = 0 and fcb = 1");
6660       break;
6661
6662     case UNPRED_R13:
6663       func (stream, "use of r13 (sp)");
6664       break;
6665
6666     case UNPRED_R15:
6667       func (stream, "use of r15 (pc)");
6668       break;
6669
6670     case UNPRED_Q_GT_4:
6671       func (stream, "start register block > r4");
6672       break;
6673
6674     case UNPRED_Q_GT_6:
6675       func (stream, "start register block > r6");
6676       break;
6677
6678     case UNPRED_R13_AND_WB:
6679       func (stream, "use of r13 and write back");
6680       break;
6681
6682     case UNPRED_Q_REGS_EQUAL:
6683       func (stream,
6684             "same vector register used for destination and other operand");
6685       break;
6686
6687     case UNPRED_OS:
6688       func (stream, "use of offset scaled");
6689       break;
6690
6691     case UNPRED_GP_REGS_EQUAL:
6692       func (stream, "same general-purpose register used for both operands");
6693       break;
6694
6695     case UNPRED_Q_REGS_EQ_AND_SIZE_1:
6696       func (stream, "use of identical q registers and size = 1");
6697       break;
6698
6699     case UNPRED_Q_REGS_EQ_AND_SIZE_2:
6700       func (stream, "use of identical q registers and size = 1");
6701       break;
6702
6703     case UNPRED_NONE:
6704       break;
6705     }
6706 }
6707
6708 /* Print register block operand for mve vld2/vld4/vst2/vld4.  */
6709
6710 static void
6711 print_mve_register_blocks (struct disassemble_info *info,
6712                            unsigned long given,
6713                            enum mve_instructions matched_insn)
6714 {
6715   void *stream = info->stream;
6716   fprintf_ftype func = info->fprintf_func;
6717
6718   unsigned long q_reg_start = arm_decode_field_multiple (given,
6719                                                          13, 15,
6720                                                          22, 22);
6721   switch (matched_insn)
6722     {
6723     case MVE_VLD2:
6724     case MVE_VST2:
6725       if (q_reg_start <= 6)
6726         func (stream, "{q%ld, q%ld}", q_reg_start, q_reg_start + 1);
6727       else
6728         func (stream, "<illegal reg q%ld>", q_reg_start);
6729       break;
6730
6731     case MVE_VLD4:
6732     case MVE_VST4:
6733       if (q_reg_start <= 4)
6734         func (stream, "{q%ld, q%ld, q%ld, q%ld}", q_reg_start,
6735               q_reg_start + 1, q_reg_start + 2,
6736               q_reg_start + 3);
6737       else
6738         func (stream, "<illegal reg q%ld>", q_reg_start);
6739       break;
6740
6741     default:
6742       break;
6743     }
6744 }
6745
6746 static void
6747 print_mve_rounding_mode (struct disassemble_info *info,
6748                          unsigned long given,
6749                          enum mve_instructions matched_insn)
6750 {
6751   void *stream = info->stream;
6752   fprintf_ftype func = info->fprintf_func;
6753
6754   switch (matched_insn)
6755     {
6756     case MVE_VCVT_FROM_FP_TO_INT:
6757       {
6758         switch (arm_decode_field (given, 8, 9))
6759           {
6760           case 0:
6761             func (stream, "a");
6762             break;
6763
6764           case 1:
6765             func (stream, "n");
6766             break;
6767
6768           case 2:
6769             func (stream, "p");
6770             break;
6771
6772           case 3:
6773             func (stream, "m");
6774             break;
6775
6776           default:
6777             break;
6778           }
6779       }
6780       break;
6781
6782     case MVE_VRINT_FP:
6783       {
6784         switch (arm_decode_field (given, 7, 9))
6785           {
6786           case 0:
6787             func (stream, "n");
6788             break;
6789
6790           case 1:
6791             func (stream, "x");
6792             break;
6793
6794           case 2:
6795             func (stream, "a");
6796             break;
6797
6798           case 3:
6799             func (stream, "z");
6800             break;
6801
6802           case 5:
6803             func (stream, "m");
6804             break;
6805
6806           case 7:
6807             func (stream, "p");
6808
6809           case 4:
6810           case 6:
6811           default:
6812             break;
6813           }
6814       }
6815       break;
6816
6817     default:
6818       break;
6819     }
6820 }
6821
6822 static void
6823 print_mve_vcvt_size (struct disassemble_info *info,
6824                      unsigned long given,
6825                      enum mve_instructions matched_insn)
6826 {
6827   unsigned long mode = 0;
6828   void *stream = info->stream;
6829   fprintf_ftype func = info->fprintf_func;
6830
6831   switch (matched_insn)
6832     {
6833     case MVE_VCVT_FP_FIX_VEC:
6834       {
6835         mode = (((given & 0x200) >> 7)
6836                 | ((given & 0x10000000) >> 27)
6837                 | ((given & 0x100) >> 8));
6838
6839         switch (mode)
6840           {
6841           case 0:
6842             func (stream, "f16.s16");
6843             break;
6844
6845           case 1:
6846             func (stream, "s16.f16");
6847             break;
6848
6849           case 2:
6850             func (stream, "f16.u16");
6851             break;
6852
6853           case 3:
6854             func (stream, "u16.f16");
6855             break;
6856
6857           case 4:
6858             func (stream, "f32.s32");
6859             break;
6860
6861           case 5:
6862             func (stream, "s32.f32");
6863             break;
6864
6865           case 6:
6866             func (stream, "f32.u32");
6867             break;
6868
6869           case 7:
6870             func (stream, "u32.f32");
6871             break;
6872
6873           default:
6874             break;
6875           }
6876         break;
6877       }
6878     case MVE_VCVT_BETWEEN_FP_INT:
6879       {
6880         unsigned long size = arm_decode_field (given, 18, 19);
6881         unsigned long op = arm_decode_field (given, 7, 8);
6882
6883         if (size == 1)
6884           {
6885             switch (op)
6886               {
6887               case 0:
6888                 func (stream, "f16.s16");
6889                 break;
6890
6891               case 1:
6892                 func (stream, "f16.u16");
6893                 break;
6894
6895               case 2:
6896                 func (stream, "s16.f16");
6897                 break;
6898
6899               case 3:
6900                 func (stream, "u16.f16");
6901                 break;
6902
6903               default:
6904                 break;
6905               }
6906           }
6907         else if (size == 2)
6908           {
6909             switch (op)
6910               {
6911               case 0:
6912                 func (stream, "f32.s32");
6913                 break;
6914
6915               case 1:
6916                 func (stream, "f32.u32");
6917                 break;
6918
6919               case 2:
6920                 func (stream, "s32.f32");
6921                 break;
6922
6923               case 3:
6924                 func (stream, "u32.f32");
6925                 break;
6926               }
6927           }
6928       }
6929       break;
6930
6931     case MVE_VCVT_FP_HALF_FP:
6932       {
6933         unsigned long op = arm_decode_field (given, 28, 28);
6934         if (op == 0)
6935           func (stream, "f16.f32");
6936         else if (op == 1)
6937           func (stream, "f32.f16");
6938       }
6939       break;
6940
6941     case MVE_VCVT_FROM_FP_TO_INT:
6942       {
6943         unsigned long size = arm_decode_field_multiple (given, 7, 7, 18, 19);
6944
6945         switch (size)
6946           {
6947           case 2:
6948             func (stream, "s16.f16");
6949             break;
6950
6951           case 3:
6952             func (stream, "u16.f16");
6953             break;
6954
6955           case 4:
6956             func (stream, "s32.f32");
6957             break;
6958
6959           case 5:
6960             func (stream, "u32.f32");
6961             break;
6962
6963           default:
6964             break;
6965           }
6966       }
6967       break;
6968
6969     default:
6970       break;
6971     }
6972 }
6973
6974 static void
6975 print_mve_rotate (struct disassemble_info *info, unsigned long rot,
6976                   unsigned long rot_width)
6977 {
6978   void *stream = info->stream;
6979   fprintf_ftype func = info->fprintf_func;
6980
6981   if (rot_width == 1)
6982     {
6983       switch (rot)
6984         {
6985         case 0:
6986           func (stream, "90");
6987           break;
6988         case 1:
6989           func (stream, "270");
6990           break;
6991         default:
6992           break;
6993         }
6994     }
6995   else if (rot_width == 2)
6996     {
6997       switch (rot)
6998         {
6999         case 0:
7000           func (stream, "0");
7001           break;
7002         case 1:
7003           func (stream, "90");
7004           break;
7005         case 2:
7006           func (stream, "180");
7007           break;
7008         case 3:
7009           func (stream, "270");
7010           break;
7011         default:
7012           break;
7013         }
7014     }
7015 }
7016
7017 static void
7018 print_instruction_predicate (struct disassemble_info *info)
7019 {
7020   void *stream = info->stream;
7021   fprintf_ftype func = info->fprintf_func;
7022
7023   if (vpt_block_state.next_pred_state == PRED_THEN)
7024     func (stream, "t");
7025   else if (vpt_block_state.next_pred_state == PRED_ELSE)
7026     func (stream, "e");
7027 }
7028
7029 static void
7030 print_mve_size (struct disassemble_info *info,
7031                 unsigned long size,
7032                 enum mve_instructions matched_insn)
7033 {
7034   void *stream = info->stream;
7035   fprintf_ftype func = info->fprintf_func;
7036
7037   switch (matched_insn)
7038     {
7039     case MVE_VABAV:
7040     case MVE_VABD_VEC:
7041     case MVE_VABS_FP:
7042     case MVE_VABS_VEC:
7043     case MVE_VADD_VEC_T1:
7044     case MVE_VADD_VEC_T2:
7045     case MVE_VADDV:
7046     case MVE_VBRSR:
7047     case MVE_VCADD_VEC:
7048     case MVE_VCLS:
7049     case MVE_VCLZ:
7050     case MVE_VCMP_VEC_T1:
7051     case MVE_VCMP_VEC_T2:
7052     case MVE_VCMP_VEC_T3:
7053     case MVE_VCMP_VEC_T4:
7054     case MVE_VCMP_VEC_T5:
7055     case MVE_VCMP_VEC_T6:
7056     case MVE_VCTP:
7057     case MVE_VDDUP:
7058     case MVE_VDWDUP:
7059     case MVE_VHADD_T1:
7060     case MVE_VHADD_T2:
7061     case MVE_VHCADD:
7062     case MVE_VHSUB_T1:
7063     case MVE_VHSUB_T2:
7064     case MVE_VIDUP:
7065     case MVE_VIWDUP:
7066     case MVE_VLD2:
7067     case MVE_VLD4:
7068     case MVE_VLDRB_GATHER_T1:
7069     case MVE_VLDRH_GATHER_T2:
7070     case MVE_VLDRW_GATHER_T3:
7071     case MVE_VLDRD_GATHER_T4:
7072     case MVE_VLDRB_T1:
7073     case MVE_VLDRH_T2:
7074     case MVE_VMAX:
7075     case MVE_VMAXA:
7076     case MVE_VMAXV:
7077     case MVE_VMAXAV:
7078     case MVE_VMIN:
7079     case MVE_VMINA:
7080     case MVE_VMINV:
7081     case MVE_VMINAV:
7082     case MVE_VMLA:
7083     case MVE_VMLAS:
7084     case MVE_VMUL_VEC_T1:
7085     case MVE_VMUL_VEC_T2:
7086     case MVE_VMULH:
7087     case MVE_VRMULH:
7088     case MVE_VMULL_INT:
7089     case MVE_VNEG_FP:
7090     case MVE_VNEG_VEC:
7091     case MVE_VPT_VEC_T1:
7092     case MVE_VPT_VEC_T2:
7093     case MVE_VPT_VEC_T3:
7094     case MVE_VPT_VEC_T4:
7095     case MVE_VPT_VEC_T5:
7096     case MVE_VPT_VEC_T6:
7097     case MVE_VQDMLADH:
7098     case MVE_VQRDMLADH:
7099     case MVE_VQDMLAH:
7100     case MVE_VQRDMLAH:
7101     case MVE_VQDMLASH:
7102     case MVE_VQRDMLASH:
7103     case MVE_VQDMLSDH:
7104     case MVE_VQRDMLSDH:
7105     case MVE_VQDMULH_T1:
7106     case MVE_VQRDMULH_T2:
7107     case MVE_VQDMULH_T3:
7108     case MVE_VQRDMULH_T4:
7109     case MVE_VQRSHL_T1:
7110     case MVE_VQRSHL_T2:
7111     case MVE_VQSHL_T1:
7112     case MVE_VQSHL_T4:
7113     case MVE_VRHADD:
7114     case MVE_VRINT_FP:
7115     case MVE_VRSHL_T1:
7116     case MVE_VRSHL_T2:
7117     case MVE_VSHL_T2:
7118     case MVE_VSHL_T3:
7119     case MVE_VSHLL_T2:
7120     case MVE_VST2:
7121     case MVE_VST4:
7122     case MVE_VSTRB_SCATTER_T1:
7123     case MVE_VSTRH_SCATTER_T2:
7124     case MVE_VSTRW_SCATTER_T3:
7125     case MVE_VSTRB_T1:
7126     case MVE_VSTRH_T2:
7127     case MVE_VSUB_VEC_T1:
7128     case MVE_VSUB_VEC_T2:
7129       if (size <= 3)
7130         func (stream, "%s", mve_vec_sizename[size]);
7131       else
7132         func (stream, "<undef size>");
7133       break;
7134
7135     case MVE_VABD_FP:
7136     case MVE_VADD_FP_T1:
7137     case MVE_VADD_FP_T2:
7138     case MVE_VSUB_FP_T1:
7139     case MVE_VSUB_FP_T2:
7140     case MVE_VCMP_FP_T1:
7141     case MVE_VCMP_FP_T2:
7142     case MVE_VFMA_FP_SCALAR:
7143     case MVE_VFMA_FP:
7144     case MVE_VFMS_FP:
7145     case MVE_VFMAS_FP_SCALAR:
7146     case MVE_VMAXNM_FP:
7147     case MVE_VMAXNMA_FP:
7148     case MVE_VMAXNMV_FP:
7149     case MVE_VMAXNMAV_FP:
7150     case MVE_VMINNM_FP:
7151     case MVE_VMINNMA_FP:
7152     case MVE_VMINNMV_FP:
7153     case MVE_VMINNMAV_FP:
7154     case MVE_VMUL_FP_T1:
7155     case MVE_VMUL_FP_T2:
7156     case MVE_VPT_FP_T1:
7157     case MVE_VPT_FP_T2:
7158       if (size == 0)
7159         func (stream, "32");
7160       else if (size == 1)
7161         func (stream, "16");
7162       break;
7163
7164     case MVE_VCADD_FP:
7165     case MVE_VCMLA_FP:
7166     case MVE_VCMUL_FP:
7167     case MVE_VMLADAV_T1:
7168     case MVE_VMLALDAV:
7169     case MVE_VMLSDAV_T1:
7170     case MVE_VMLSLDAV:
7171     case MVE_VMOVN:
7172     case MVE_VQDMULL_T1:
7173     case MVE_VQDMULL_T2:
7174     case MVE_VQMOVN:
7175     case MVE_VQMOVUN:
7176       if (size == 0)
7177         func (stream, "16");
7178       else if (size == 1)
7179         func (stream, "32");
7180       break;
7181
7182     case MVE_VMOVL:
7183       if (size == 1)
7184         func (stream, "8");
7185       else if (size == 2)
7186         func (stream, "16");
7187       break;
7188
7189     case MVE_VDUP:
7190       switch (size)
7191         {
7192         case 0:
7193           func (stream, "32");
7194           break;
7195         case 1:
7196           func (stream, "16");
7197           break;
7198         case 2:
7199           func (stream, "8");
7200           break;
7201         default:
7202           break;
7203         }
7204       break;
7205
7206     case MVE_VMOV_GP_TO_VEC_LANE:
7207     case MVE_VMOV_VEC_LANE_TO_GP:
7208       switch (size)
7209         {
7210         case 0: case 4:
7211           func (stream, "32");
7212           break;
7213
7214         case 1: case 3:
7215         case 5: case 7:
7216           func (stream, "16");
7217           break;
7218
7219         case 8: case 9: case 10: case 11:
7220         case 12: case 13: case 14: case 15:
7221           func (stream, "8");
7222           break;
7223
7224         default:
7225           break;
7226         }
7227       break;
7228
7229     case MVE_VMOV_IMM_TO_VEC:
7230       switch (size)
7231         {
7232         case 0: case 4: case 8:
7233         case 12: case 24: case 26:
7234           func (stream, "i32");
7235           break;
7236         case 16: case 20:
7237           func (stream, "i16");
7238           break;
7239         case 28:
7240           func (stream, "i8");
7241           break;
7242         case 29:
7243           func (stream, "i64");
7244           break;
7245         case 30:
7246           func (stream, "f32");
7247           break;
7248         default:
7249           break;
7250         }
7251       break;
7252
7253     case MVE_VMULL_POLY:
7254       if (size == 0)
7255         func (stream, "p8");
7256       else if (size == 1)
7257         func (stream, "p16");
7258       break;
7259
7260     case MVE_VMVN_IMM:
7261       switch (size)
7262         {
7263         case 0: case 2: case 4:
7264         case 6: case 12: case 13:
7265           func (stream, "32");
7266           break;
7267
7268         case 8: case 10:
7269           func (stream, "16");
7270           break;
7271
7272         default:
7273           break;
7274         }
7275       break;
7276
7277     case MVE_VBIC_IMM:
7278     case MVE_VORR_IMM:
7279       switch (size)
7280         {
7281         case 1: case 3:
7282         case 5: case 7:
7283           func (stream, "32");
7284           break;
7285
7286         case 9: case 11:
7287           func (stream, "16");
7288           break;
7289
7290         default:
7291           break;
7292         }
7293       break;
7294
7295     case MVE_VQSHRN:
7296     case MVE_VQSHRUN:
7297     case MVE_VQRSHRN:
7298     case MVE_VQRSHRUN:
7299     case MVE_VRSHRN:
7300     case MVE_VSHRN:
7301       {
7302         switch (size)
7303         {
7304         case 1:
7305           func (stream, "16");
7306           break;
7307
7308         case 2: case 3:
7309           func (stream, "32");
7310           break;
7311
7312         default:
7313           break;
7314         }
7315       }
7316       break;
7317
7318     case MVE_VQSHL_T2:
7319     case MVE_VQSHLU_T3:
7320     case MVE_VRSHR:
7321     case MVE_VSHL_T1:
7322     case MVE_VSHLL_T1:
7323     case MVE_VSHR:
7324     case MVE_VSLI:
7325     case MVE_VSRI:
7326       {
7327         switch (size)
7328         {
7329         case 1:
7330           func (stream, "8");
7331           break;
7332
7333         case 2: case 3:
7334           func (stream, "16");
7335           break;
7336
7337         case 4: case 5: case 6: case 7:
7338           func (stream, "32");
7339           break;
7340
7341         default:
7342           break;
7343         }
7344       }
7345       break;
7346
7347     default:
7348       break;
7349     }
7350 }
7351
7352 static void
7353 print_mve_shift_n (struct disassemble_info *info, long given,
7354                    enum mve_instructions matched_insn)
7355 {
7356   void *stream = info->stream;
7357   fprintf_ftype func = info->fprintf_func;
7358
7359   int startAt0
7360     = matched_insn == MVE_VQSHL_T2
7361       || matched_insn == MVE_VQSHLU_T3
7362       || matched_insn == MVE_VSHL_T1
7363       || matched_insn == MVE_VSHLL_T1
7364       || matched_insn == MVE_VSLI;
7365
7366   unsigned imm6 = (given & 0x3f0000) >> 16;
7367
7368   if (matched_insn == MVE_VSHLL_T1)
7369     imm6 &= 0x1f;
7370
7371   unsigned shiftAmount = 0;
7372   if ((imm6 & 0x20) != 0)
7373     shiftAmount = startAt0 ? imm6 - 32 : 64 - imm6;
7374   else if ((imm6 & 0x10) != 0)
7375     shiftAmount = startAt0 ? imm6 - 16 : 32 - imm6;
7376   else if ((imm6 & 0x08) != 0)
7377     shiftAmount = startAt0 ? imm6 - 8 : 16 - imm6;
7378   else
7379     print_mve_undefined (info, UNDEF_SIZE_0);
7380
7381   func (stream, "%u", shiftAmount);
7382 }
7383
7384 static void
7385 print_vec_condition (struct disassemble_info *info, long given,
7386                      enum mve_instructions matched_insn)
7387 {
7388   void *stream = info->stream;
7389   fprintf_ftype func = info->fprintf_func;
7390   long vec_cond = 0;
7391
7392   switch (matched_insn)
7393     {
7394     case MVE_VPT_FP_T1:
7395     case MVE_VCMP_FP_T1:
7396       vec_cond = (((given & 0x1000) >> 10)
7397                   | ((given & 1) << 1)
7398                   | ((given & 0x0080) >> 7));
7399       func (stream, "%s",vec_condnames[vec_cond]);
7400       break;
7401
7402     case MVE_VPT_FP_T2:
7403     case MVE_VCMP_FP_T2:
7404       vec_cond = (((given & 0x1000) >> 10)
7405                   | ((given & 0x0020) >> 4)
7406                   | ((given & 0x0080) >> 7));
7407       func (stream, "%s",vec_condnames[vec_cond]);
7408       break;
7409
7410     case MVE_VPT_VEC_T1:
7411     case MVE_VCMP_VEC_T1:
7412       vec_cond = (given & 0x0080) >> 7;
7413       func (stream, "%s",vec_condnames[vec_cond]);
7414       break;
7415
7416     case MVE_VPT_VEC_T2:
7417     case MVE_VCMP_VEC_T2:
7418       vec_cond = 2 | ((given & 0x0080) >> 7);
7419       func (stream, "%s",vec_condnames[vec_cond]);
7420       break;
7421
7422     case MVE_VPT_VEC_T3:
7423     case MVE_VCMP_VEC_T3:
7424       vec_cond = 4 | ((given & 1) << 1) | ((given & 0x0080) >> 7);
7425       func (stream, "%s",vec_condnames[vec_cond]);
7426       break;
7427
7428     case MVE_VPT_VEC_T4:
7429     case MVE_VCMP_VEC_T4:
7430       vec_cond = (given & 0x0080) >> 7;
7431       func (stream, "%s",vec_condnames[vec_cond]);
7432       break;
7433
7434     case MVE_VPT_VEC_T5:
7435     case MVE_VCMP_VEC_T5:
7436       vec_cond = 2 | ((given & 0x0080) >> 7);
7437       func (stream, "%s",vec_condnames[vec_cond]);
7438       break;
7439
7440     case MVE_VPT_VEC_T6:
7441     case MVE_VCMP_VEC_T6:
7442       vec_cond = 4 | ((given & 0x0020) >> 4) | ((given & 0x0080) >> 7);
7443       func (stream, "%s",vec_condnames[vec_cond]);
7444       break;
7445
7446     case MVE_NONE:
7447     case MVE_VPST:
7448     default:
7449       break;
7450     }
7451 }
7452
7453 #define W_BIT 21
7454 #define I_BIT 22
7455 #define U_BIT 23
7456 #define P_BIT 24
7457
7458 #define WRITEBACK_BIT_SET (given & (1 << W_BIT))
7459 #define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
7460 #define NEGATIVE_BIT_SET  ((given & (1 << U_BIT)) == 0)
7461 #define PRE_BIT_SET       (given & (1 << P_BIT))
7462
7463
7464 /* Print one coprocessor instruction on INFO->STREAM.
7465    Return TRUE if the instuction matched, FALSE if this is not a
7466    recognised coprocessor instruction.  */
7467
7468 static bfd_boolean
7469 print_insn_coprocessor (bfd_vma pc,
7470                         struct disassemble_info *info,
7471                         long given,
7472                         bfd_boolean thumb)
7473 {
7474   const struct sopcode32 *insn;
7475   void *stream = info->stream;
7476   fprintf_ftype func = info->fprintf_func;
7477   unsigned long mask;
7478   unsigned long value = 0;
7479   int cond;
7480   int cp_num;
7481   struct arm_private_data *private_data = info->private_data;
7482   arm_feature_set allowed_arches = ARM_ARCH_NONE;
7483   arm_feature_set arm_ext_v8_1m_main =
7484     ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
7485
7486   allowed_arches = private_data->features;
7487
7488   for (insn = coprocessor_opcodes; insn->assembler; insn++)
7489     {
7490       unsigned long u_reg = 16;
7491       bfd_boolean is_unpredictable = FALSE;
7492       signed long value_in_comment = 0;
7493       const char *c;
7494
7495       if (ARM_FEATURE_ZERO (insn->arch))
7496         switch (insn->value)
7497           {
7498           case SENTINEL_IWMMXT_START:
7499             if (info->mach != bfd_mach_arm_XScale
7500                 && info->mach != bfd_mach_arm_iWMMXt
7501                 && info->mach != bfd_mach_arm_iWMMXt2)
7502               do
7503                 insn++;
7504               while ((! ARM_FEATURE_ZERO (insn->arch))
7505                      && insn->value != SENTINEL_IWMMXT_END);
7506             continue;
7507
7508           case SENTINEL_IWMMXT_END:
7509             continue;
7510
7511           case SENTINEL_GENERIC_START:
7512             allowed_arches = private_data->features;
7513             continue;
7514
7515           default:
7516             abort ();
7517           }
7518
7519       mask = insn->mask;
7520       value = insn->value;
7521       cp_num = (given >> 8) & 0xf;
7522
7523       if (thumb)
7524         {
7525           /* The high 4 bits are 0xe for Arm conditional instructions, and
7526              0xe for arm unconditional instructions.  The rest of the
7527              encoding is the same.  */
7528           mask |= 0xf0000000;
7529           value |= 0xe0000000;
7530           if (ifthen_state)
7531             cond = IFTHEN_COND;
7532           else
7533             cond = COND_UNCOND;
7534         }
7535       else
7536         {
7537           /* Only match unconditional instuctions against unconditional
7538              patterns.  */
7539           if ((given & 0xf0000000) == 0xf0000000)
7540             {
7541               mask |= 0xf0000000;
7542               cond = COND_UNCOND;
7543             }
7544           else
7545             {
7546               cond = (given >> 28) & 0xf;
7547               if (cond == 0xe)
7548                 cond = COND_UNCOND;
7549             }
7550         }
7551
7552       if ((insn->isa == T32 && !thumb)
7553           || (insn->isa == ARM && thumb))
7554         continue;
7555
7556       if ((given & mask) != value)
7557         continue;
7558
7559       if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches))
7560         continue;
7561
7562       if (insn->value == 0xfe000010     /* mcr2  */
7563           || insn->value == 0xfe100010  /* mrc2  */
7564           || insn->value == 0xfc100000  /* ldc2  */
7565           || insn->value == 0xfc000000) /* stc2  */
7566         {
7567           if (cp_num == 9 || cp_num == 10 || cp_num == 11)
7568             is_unpredictable = TRUE;
7569
7570           /* Armv8.1-M Mainline FP & MVE instructions.  */
7571           if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
7572               && !ARM_CPU_IS_ANY (allowed_arches)
7573               && (cp_num == 8 || cp_num == 14 || cp_num == 15))
7574             continue;
7575
7576         }
7577       else if (insn->value == 0x0e000000     /* cdp  */
7578                || insn->value == 0xfe000000  /* cdp2  */
7579                || insn->value == 0x0e000010  /* mcr  */
7580                || insn->value == 0x0e100010  /* mrc  */
7581                || insn->value == 0x0c100000  /* ldc  */
7582                || insn->value == 0x0c000000) /* stc  */
7583         {
7584           /* Floating-point instructions.  */
7585           if (cp_num == 9 || cp_num == 10 || cp_num == 11)
7586             continue;
7587
7588           /* Armv8.1-M Mainline FP & MVE instructions.  */
7589           if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
7590               && !ARM_CPU_IS_ANY (allowed_arches)
7591               && (cp_num == 8 || cp_num == 14 || cp_num == 15))
7592             continue;
7593         }
7594       else if ((insn->value == 0xec100f80      /* vldr (system register) */
7595                 || insn->value == 0xec000f80)  /* vstr (system register) */
7596                && arm_decode_field (given, 24, 24) == 0
7597                && arm_decode_field (given, 21, 21) == 0)
7598         /* If the P and W bits are both 0 then these encodings match the MVE
7599            VLDR and VSTR instructions, these are in a different table, so we
7600            don't let it match here.  */
7601         continue;
7602
7603       for (c = insn->assembler; *c; c++)
7604         {
7605           if (*c == '%')
7606             {
7607               const char mod = *++c;
7608               switch (mod)
7609                 {
7610                 case '%':
7611                   func (stream, "%%");
7612                   break;
7613
7614                 case 'A':
7615                 case 'K':
7616                   {
7617                     int rn = (given >> 16) & 0xf;
7618                     bfd_vma offset = given & 0xff;
7619
7620                     if (mod == 'K')
7621                       offset = given & 0x7f;
7622
7623                     func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
7624
7625                     if (PRE_BIT_SET || WRITEBACK_BIT_SET)
7626                       {
7627                         /* Not unindexed.  The offset is scaled.  */
7628                         if (cp_num == 9)
7629                           /* vldr.16/vstr.16 will shift the address
7630                              left by 1 bit only.  */
7631                           offset = offset * 2;
7632                         else
7633                           offset = offset * 4;
7634
7635                         if (NEGATIVE_BIT_SET)
7636                           offset = - offset;
7637                         if (rn != 15)
7638                           value_in_comment = offset;
7639                       }
7640
7641                     if (PRE_BIT_SET)
7642                       {
7643                         if (offset)
7644                           func (stream, ", #%d]%s",
7645                                 (int) offset,
7646                                 WRITEBACK_BIT_SET ? "!" : "");
7647                         else if (NEGATIVE_BIT_SET)
7648                           func (stream, ", #-0]");
7649                         else
7650                           func (stream, "]");
7651                       }
7652                     else
7653                       {
7654                         func (stream, "]");
7655
7656                         if (WRITEBACK_BIT_SET)
7657                           {
7658                             if (offset)
7659                               func (stream, ", #%d", (int) offset);
7660                             else if (NEGATIVE_BIT_SET)
7661                               func (stream, ", #-0");
7662                           }
7663                         else
7664                           {
7665                             func (stream, ", {%s%d}",
7666                                   (NEGATIVE_BIT_SET && !offset) ? "-" : "",
7667                                   (int) offset);
7668                             value_in_comment = offset;
7669                           }
7670                       }
7671                     if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
7672                       {
7673                         func (stream, "\t; ");
7674                         /* For unaligned PCs, apply off-by-alignment
7675                            correction.  */
7676                         info->print_address_func (offset + pc
7677                                                   + info->bytes_per_chunk * 2
7678                                                   - (pc & 3),
7679                                                   info);
7680                       }
7681                   }
7682                   break;
7683
7684                 case 'B':
7685                   {
7686                     int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
7687                     int offset = (given >> 1) & 0x3f;
7688
7689                     if (offset == 1)
7690                       func (stream, "{d%d}", regno);
7691                     else if (regno + offset > 32)
7692                       func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
7693                     else
7694                       func (stream, "{d%d-d%d}", regno, regno + offset - 1);
7695                   }
7696                   break;
7697
7698                 case 'C':
7699                   {
7700                     bfd_boolean single = ((given >> 8) & 1) == 0;
7701                     char reg_prefix = single ? 's' : 'd';
7702                     int Dreg = (given >> 22) & 0x1;
7703                     int Vdreg = (given >> 12) & 0xf;
7704                     int reg = single ? ((Vdreg << 1) | Dreg)
7705                                      : ((Dreg << 4) | Vdreg);
7706                     int num = (given >> (single ? 0 : 1)) & 0x7f;
7707                     int maxreg = single ? 31 : 15;
7708                     int topreg = reg + num - 1;
7709
7710                     if (!num)
7711                       func (stream, "{VPR}");
7712                     else if (num == 1)
7713                       func (stream, "{%c%d, VPR}", reg_prefix, reg);
7714                     else if (topreg > maxreg)
7715                       func (stream, "{%c%d-<overflow reg d%d, VPR}",
7716                             reg_prefix, reg, single ? topreg >> 1 : topreg);
7717                     else
7718                       func (stream, "{%c%d-%c%d, VPR}", reg_prefix, reg,
7719                             reg_prefix, topreg);
7720                   }
7721                   break;
7722
7723                 case 'u':
7724                   if (cond != COND_UNCOND)
7725                     is_unpredictable = TRUE;
7726
7727                   /* Fall through.  */
7728                 case 'c':
7729                   if (cond != COND_UNCOND && cp_num == 9)
7730                     is_unpredictable = TRUE;
7731
7732                   func (stream, "%s", arm_conditional[cond]);
7733                   break;
7734
7735                 case 'I':
7736                   /* Print a Cirrus/DSP shift immediate.  */
7737                   /* Immediates are 7bit signed ints with bits 0..3 in
7738                      bits 0..3 of opcode and bits 4..6 in bits 5..7
7739                      of opcode.  */
7740                   {
7741                     int imm;
7742
7743                     imm = (given & 0xf) | ((given & 0xe0) >> 1);
7744
7745                     /* Is ``imm'' a negative number?  */
7746                     if (imm & 0x40)
7747                       imm -= 0x80;
7748
7749                     func (stream, "%d", imm);
7750                   }
7751
7752                   break;
7753
7754                 case 'J':
7755                   {
7756                     unsigned long regno
7757                       = arm_decode_field_multiple (given, 13, 15, 22, 22);
7758
7759                     switch (regno)
7760                       {
7761                       case 0x1:
7762                         func (stream, "FPSCR");
7763                         break;
7764                       case 0x2:
7765                         func (stream, "FPSCR_nzcvqc");
7766                         break;
7767                       case 0xc:
7768                         func (stream, "VPR");
7769                         break;
7770                       case 0xd:
7771                         func (stream, "P0");
7772                         break;
7773                       case 0xe:
7774                         func (stream, "FPCXTNS");
7775                         break;
7776                       case 0xf:
7777                         func (stream, "FPCXTS");
7778                         break;
7779                       default:
7780                         func (stream, "<invalid reg %lu>", regno);
7781                         break;
7782                       }
7783                   }
7784                   break;
7785
7786                 case 'F':
7787                   switch (given & 0x00408000)
7788                     {
7789                     case 0:
7790                       func (stream, "4");
7791                       break;
7792                     case 0x8000:
7793                       func (stream, "1");
7794                       break;
7795                     case 0x00400000:
7796                       func (stream, "2");
7797                       break;
7798                     default:
7799                       func (stream, "3");
7800                     }
7801                   break;
7802
7803                 case 'P':
7804                   switch (given & 0x00080080)
7805                     {
7806                     case 0:
7807                       func (stream, "s");
7808                       break;
7809                     case 0x80:
7810                       func (stream, "d");
7811                       break;
7812                     case 0x00080000:
7813                       func (stream, "e");
7814                       break;
7815                     default:
7816                       func (stream, _("<illegal precision>"));
7817                       break;
7818                     }
7819                   break;
7820
7821                 case 'Q':
7822                   switch (given & 0x00408000)
7823                     {
7824                     case 0:
7825                       func (stream, "s");
7826                       break;
7827                     case 0x8000:
7828                       func (stream, "d");
7829                       break;
7830                     case 0x00400000:
7831                       func (stream, "e");
7832                       break;
7833                     default:
7834                       func (stream, "p");
7835                       break;
7836                     }
7837                   break;
7838
7839                 case 'R':
7840                   switch (given & 0x60)
7841                     {
7842                     case 0:
7843                       break;
7844                     case 0x20:
7845                       func (stream, "p");
7846                       break;
7847                     case 0x40:
7848                       func (stream, "m");
7849                       break;
7850                     default:
7851                       func (stream, "z");
7852                       break;
7853                     }
7854                   break;
7855
7856                 case '0': case '1': case '2': case '3': case '4':
7857                 case '5': case '6': case '7': case '8': case '9':
7858                   {
7859                     int width;
7860
7861                     c = arm_decode_bitfield (c, given, &value, &width);
7862
7863                     switch (*c)
7864                       {
7865                       case 'R':
7866                         if (value == 15)
7867                           is_unpredictable = TRUE;
7868                         /* Fall through.  */
7869                       case 'r':
7870                         if (c[1] == 'u')
7871                           {
7872                             /* Eat the 'u' character.  */
7873                             ++ c;
7874
7875                             if (u_reg == value)
7876                               is_unpredictable = TRUE;
7877                             u_reg = value;
7878                           }
7879                         func (stream, "%s", arm_regnames[value]);
7880                         break;
7881                       case 'V':
7882                         if (given & (1 << 6))
7883                           goto Q;
7884                         /* FALLTHROUGH */
7885                       case 'D':
7886                         func (stream, "d%ld", value);
7887                         break;
7888                       case 'Q':
7889                       Q:
7890                         if (value & 1)
7891                           func (stream, "<illegal reg q%ld.5>", value >> 1);
7892                         else
7893                           func (stream, "q%ld", value >> 1);
7894                         break;
7895                       case 'd':
7896                         func (stream, "%ld", value);
7897                         value_in_comment = value;
7898                         break;
7899                       case 'E':
7900                         {
7901                           /* Converts immediate 8 bit back to float value.  */
7902                           unsigned floatVal = (value & 0x80) << 24
7903                             | (value & 0x3F) << 19
7904                             | ((value & 0x40) ? (0xF8 << 22) : (1 << 30));
7905
7906                           /* Quarter float have a maximum value of 31.0.
7907                              Get floating point value multiplied by 1e7.
7908                              The maximum value stays in limit of a 32-bit int.  */
7909                           unsigned decVal =
7910                             (78125 << (((floatVal >> 23) & 0xFF) - 124)) *
7911                             (16 + (value & 0xF));
7912
7913                           if (!(decVal % 1000000))
7914                             func (stream, "%ld\t; 0x%08x %c%u.%01u", value,
7915                                   floatVal, value & 0x80 ? '-' : ' ',
7916                                   decVal / 10000000,
7917                                   decVal % 10000000 / 1000000);
7918                           else if (!(decVal % 10000))
7919                             func (stream, "%ld\t; 0x%08x %c%u.%03u", value,
7920                                   floatVal, value & 0x80 ? '-' : ' ',
7921                                   decVal / 10000000,
7922                                   decVal % 10000000 / 10000);
7923                           else
7924                             func (stream, "%ld\t; 0x%08x %c%u.%07u", value,
7925                                   floatVal, value & 0x80 ? '-' : ' ',
7926                                   decVal / 10000000, decVal % 10000000);
7927                           break;
7928                         }
7929                       case 'k':
7930                         {
7931                           int from = (given & (1 << 7)) ? 32 : 16;
7932                           func (stream, "%ld", from - value);
7933                         }
7934                         break;
7935
7936                       case 'f':
7937                         if (value > 7)
7938                           func (stream, "#%s", arm_fp_const[value & 7]);
7939                         else
7940                           func (stream, "f%ld", value);
7941                         break;
7942
7943                       case 'w':
7944                         if (width == 2)
7945                           func (stream, "%s", iwmmxt_wwnames[value]);
7946                         else
7947                           func (stream, "%s", iwmmxt_wwssnames[value]);
7948                         break;
7949
7950                       case 'g':
7951                         func (stream, "%s", iwmmxt_regnames[value]);
7952                         break;
7953                       case 'G':
7954                         func (stream, "%s", iwmmxt_cregnames[value]);
7955                         break;
7956
7957                       case 'x':
7958                         func (stream, "0x%lx", (value & 0xffffffffUL));
7959                         break;
7960
7961                       case 'c':
7962                         switch (value)
7963                           {
7964                           case 0:
7965                             func (stream, "eq");
7966                             break;
7967
7968                           case 1:
7969                             func (stream, "vs");
7970                             break;
7971
7972                           case 2:
7973                             func (stream, "ge");
7974                             break;
7975
7976                           case 3:
7977                             func (stream, "gt");
7978                             break;
7979
7980                           default:
7981                             func (stream, "??");
7982                             break;
7983                           }
7984                         break;
7985
7986                       case '`':
7987                         c++;
7988                         if (value == 0)
7989                           func (stream, "%c", *c);
7990                         break;
7991                       case '\'':
7992                         c++;
7993                         if (value == ((1ul << width) - 1))
7994                           func (stream, "%c", *c);
7995                         break;
7996                       case '?':
7997                         func (stream, "%c", c[(1 << width) - (int) value]);
7998                         c += 1 << width;
7999                         break;
8000                       default:
8001                         abort ();
8002                       }
8003                   }
8004                   break;
8005
8006                 case 'y':
8007                 case 'z':
8008                   {
8009                     int single = *c++ == 'y';
8010                     int regno;
8011
8012                     switch (*c)
8013                       {
8014                       case '4': /* Sm pair */
8015                       case '0': /* Sm, Dm */
8016                         regno = given & 0x0000000f;
8017                         if (single)
8018                           {
8019                             regno <<= 1;
8020                             regno += (given >> 5) & 1;
8021                           }
8022                         else
8023                           regno += ((given >> 5) & 1) << 4;
8024                         break;
8025
8026                       case '1': /* Sd, Dd */
8027                         regno = (given >> 12) & 0x0000000f;
8028                         if (single)
8029                           {
8030                             regno <<= 1;
8031                             regno += (given >> 22) & 1;
8032                           }
8033                         else
8034                           regno += ((given >> 22) & 1) << 4;
8035                         break;
8036
8037                       case '2': /* Sn, Dn */
8038                         regno = (given >> 16) & 0x0000000f;
8039                         if (single)
8040                           {
8041                             regno <<= 1;
8042                             regno += (given >> 7) & 1;
8043                           }
8044                         else
8045                           regno += ((given >> 7) & 1) << 4;
8046                         break;
8047
8048                       case '3': /* List */
8049                         func (stream, "{");
8050                         regno = (given >> 12) & 0x0000000f;
8051                         if (single)
8052                           {
8053                             regno <<= 1;
8054                             regno += (given >> 22) & 1;
8055                           }
8056                         else
8057                           regno += ((given >> 22) & 1) << 4;
8058                         break;
8059
8060                       default:
8061                         abort ();
8062                       }
8063
8064                     func (stream, "%c%d", single ? 's' : 'd', regno);
8065
8066                     if (*c == '3')
8067                       {
8068                         int count = given & 0xff;
8069
8070                         if (single == 0)
8071                           count >>= 1;
8072
8073                         if (--count)
8074                           {
8075                             func (stream, "-%c%d",
8076                                   single ? 's' : 'd',
8077                                   regno + count);
8078                           }
8079
8080                         func (stream, "}");
8081                       }
8082                     else if (*c == '4')
8083                       func (stream, ", %c%d", single ? 's' : 'd',
8084                             regno + 1);
8085                   }
8086                   break;
8087
8088                 case 'L':
8089                   switch (given & 0x00400100)
8090                     {
8091                     case 0x00000000: func (stream, "b"); break;
8092                     case 0x00400000: func (stream, "h"); break;
8093                     case 0x00000100: func (stream, "w"); break;
8094                     case 0x00400100: func (stream, "d"); break;
8095                     default:
8096                       break;
8097                     }
8098                   break;
8099
8100                 case 'Z':
8101                   {
8102                     /* given (20, 23) | given (0, 3) */
8103                     value = ((given >> 16) & 0xf0) | (given & 0xf);
8104                     func (stream, "%d", (int) value);
8105                   }
8106                   break;
8107
8108                 case 'l':
8109                   /* This is like the 'A' operator, except that if
8110                      the width field "M" is zero, then the offset is
8111                      *not* multiplied by four.  */
8112                   {
8113                     int offset = given & 0xff;
8114                     int multiplier = (given & 0x00000100) ? 4 : 1;
8115
8116                     func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
8117
8118                     if (multiplier > 1)
8119                       {
8120                         value_in_comment = offset * multiplier;
8121                         if (NEGATIVE_BIT_SET)
8122                           value_in_comment = - value_in_comment;
8123                       }
8124
8125                     if (offset)
8126                       {
8127                         if (PRE_BIT_SET)
8128                           func (stream, ", #%s%d]%s",
8129                                 NEGATIVE_BIT_SET ? "-" : "",
8130                                 offset * multiplier,
8131                                 WRITEBACK_BIT_SET ? "!" : "");
8132                         else
8133                           func (stream, "], #%s%d",
8134                                 NEGATIVE_BIT_SET ? "-" : "",
8135                                 offset * multiplier);
8136                       }
8137                     else
8138                       func (stream, "]");
8139                   }
8140                   break;
8141
8142                 case 'r':
8143                   {
8144                     int imm4 = (given >> 4) & 0xf;
8145                     int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
8146                     int ubit = ! NEGATIVE_BIT_SET;
8147                     const char *rm = arm_regnames [given & 0xf];
8148                     const char *rn = arm_regnames [(given >> 16) & 0xf];
8149
8150                     switch (puw_bits)
8151                       {
8152                       case 1:
8153                       case 3:
8154                         func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
8155                         if (imm4)
8156                           func (stream, ", lsl #%d", imm4);
8157                         break;
8158
8159                       case 4:
8160                       case 5:
8161                       case 6:
8162                       case 7:
8163                         func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
8164                         if (imm4 > 0)
8165                           func (stream, ", lsl #%d", imm4);
8166                         func (stream, "]");
8167                         if (puw_bits == 5 || puw_bits == 7)
8168                           func (stream, "!");
8169                         break;
8170
8171                       default:
8172                         func (stream, "INVALID");
8173                       }
8174                   }
8175                   break;
8176
8177                 case 'i':
8178                   {
8179                     long imm5;
8180                     imm5 = ((given & 0x100) >> 4) | (given & 0xf);
8181                     func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
8182                   }
8183                   break;
8184
8185                 default:
8186                   abort ();
8187                 }
8188             }
8189           else
8190             func (stream, "%c", *c);
8191         }
8192
8193       if (value_in_comment > 32 || value_in_comment < -16)
8194         func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
8195
8196       if (is_unpredictable)
8197         func (stream, UNPREDICTABLE_INSTRUCTION);
8198
8199       return TRUE;
8200     }
8201   return FALSE;
8202 }
8203
8204 /* Decodes and prints ARM addressing modes.  Returns the offset
8205    used in the address, if any, if it is worthwhile printing the
8206    offset as a hexadecimal value in a comment at the end of the
8207    line of disassembly.  */
8208
8209 static signed long
8210 print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
8211 {
8212   void *stream = info->stream;
8213   fprintf_ftype func = info->fprintf_func;
8214   bfd_vma offset = 0;
8215
8216   if (((given & 0x000f0000) == 0x000f0000)
8217       && ((given & 0x02000000) == 0))
8218     {
8219       offset = given & 0xfff;
8220
8221       func (stream, "[pc");
8222
8223       if (PRE_BIT_SET)
8224         {
8225           /* Pre-indexed.  Elide offset of positive zero when
8226              non-writeback.  */
8227           if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
8228             func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
8229
8230           if (NEGATIVE_BIT_SET)
8231             offset = -offset;
8232
8233           offset += pc + 8;
8234
8235           /* Cope with the possibility of write-back
8236              being used.  Probably a very dangerous thing
8237              for the programmer to do, but who are we to
8238              argue ?  */
8239           func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : "");
8240         }
8241       else  /* Post indexed.  */
8242         {
8243           func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
8244
8245           /* Ie ignore the offset.  */
8246           offset = pc + 8;
8247         }
8248
8249       func (stream, "\t; ");
8250       info->print_address_func (offset, info);
8251       offset = 0;
8252     }
8253   else
8254     {
8255       func (stream, "[%s",
8256             arm_regnames[(given >> 16) & 0xf]);
8257
8258       if (PRE_BIT_SET)
8259         {
8260           if ((given & 0x02000000) == 0)
8261             {
8262               /* Elide offset of positive zero when non-writeback.  */
8263               offset = given & 0xfff;
8264               if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
8265                 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
8266             }
8267           else
8268             {
8269               func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : "");
8270               arm_decode_shift (given, func, stream, TRUE);
8271             }
8272
8273           func (stream, "]%s",
8274                 WRITEBACK_BIT_SET ? "!" : "");
8275         }
8276       else
8277         {
8278           if ((given & 0x02000000) == 0)
8279             {
8280               /* Always show offset.  */
8281               offset = given & 0xfff;
8282               func (stream, "], #%s%d",
8283                     NEGATIVE_BIT_SET ? "-" : "", (int) offset);
8284             }
8285           else
8286             {
8287               func (stream, "], %s",
8288                     NEGATIVE_BIT_SET ? "-" : "");
8289               arm_decode_shift (given, func, stream, TRUE);
8290             }
8291         }
8292       if (NEGATIVE_BIT_SET)
8293         offset = -offset;
8294     }
8295
8296   return (signed long) offset;
8297 }
8298
8299 /* Print one neon instruction on INFO->STREAM.
8300    Return TRUE if the instuction matched, FALSE if this is not a
8301    recognised neon instruction.  */
8302
8303 static bfd_boolean
8304 print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
8305 {
8306   const struct opcode32 *insn;
8307   void *stream = info->stream;
8308   fprintf_ftype func = info->fprintf_func;
8309
8310   if (thumb)
8311     {
8312       if ((given & 0xef000000) == 0xef000000)
8313         {
8314           /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding.  */
8315           unsigned long bit28 = given & (1 << 28);
8316
8317           given &= 0x00ffffff;
8318           if (bit28)
8319             given |= 0xf3000000;
8320           else
8321             given |= 0xf2000000;
8322         }
8323       else if ((given & 0xff000000) == 0xf9000000)
8324         given ^= 0xf9000000 ^ 0xf4000000;
8325       /* vdup is also a valid neon instruction.  */
8326       else if ((given & 0xff910f5f) != 0xee800b10)
8327         return FALSE;
8328     }
8329
8330   for (insn = neon_opcodes; insn->assembler; insn++)
8331     {
8332       if ((given & insn->mask) == insn->value)
8333         {
8334           signed long value_in_comment = 0;
8335           bfd_boolean is_unpredictable = FALSE;
8336           const char *c;
8337
8338           for (c = insn->assembler; *c; c++)
8339             {
8340               if (*c == '%')
8341                 {
8342                   switch (*++c)
8343                     {
8344                     case '%':
8345                       func (stream, "%%");
8346                       break;
8347
8348                     case 'u':
8349                       if (thumb && ifthen_state)
8350                         is_unpredictable = TRUE;
8351
8352                       /* Fall through.  */
8353                     case 'c':
8354                       if (thumb && ifthen_state)
8355                         func (stream, "%s", arm_conditional[IFTHEN_COND]);
8356                       break;
8357
8358                     case 'A':
8359                       {
8360                         static const unsigned char enc[16] =
8361                         {
8362                           0x4, 0x14, /* st4 0,1 */
8363                           0x4, /* st1 2 */
8364                           0x4, /* st2 3 */
8365                           0x3, /* st3 4 */
8366                           0x13, /* st3 5 */
8367                           0x3, /* st1 6 */
8368                           0x1, /* st1 7 */
8369                           0x2, /* st2 8 */
8370                           0x12, /* st2 9 */
8371                           0x2, /* st1 10 */
8372                           0, 0, 0, 0, 0
8373                         };
8374                         int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
8375                         int rn = ((given >> 16) & 0xf);
8376                         int rm = ((given >> 0) & 0xf);
8377                         int align = ((given >> 4) & 0x3);
8378                         int type = ((given >> 8) & 0xf);
8379                         int n = enc[type] & 0xf;
8380                         int stride = (enc[type] >> 4) + 1;
8381                         int ix;
8382
8383                         func (stream, "{");
8384                         if (stride > 1)
8385                           for (ix = 0; ix != n; ix++)
8386                             func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
8387                         else if (n == 1)
8388                           func (stream, "d%d", rd);
8389                         else
8390                           func (stream, "d%d-d%d", rd, rd + n - 1);
8391                         func (stream, "}, [%s", arm_regnames[rn]);
8392                         if (align)
8393                           func (stream, " :%d", 32 << align);
8394                         func (stream, "]");
8395                         if (rm == 0xd)
8396                           func (stream, "!");
8397                         else if (rm != 0xf)
8398                           func (stream, ", %s", arm_regnames[rm]);
8399                       }
8400                       break;
8401
8402                     case 'B':
8403                       {
8404                         int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
8405                         int rn = ((given >> 16) & 0xf);
8406                         int rm = ((given >> 0) & 0xf);
8407                         int idx_align = ((given >> 4) & 0xf);
8408                         int align = 0;
8409                         int size = ((given >> 10) & 0x3);
8410                         int idx = idx_align >> (size + 1);
8411                         int length = ((given >> 8) & 3) + 1;
8412                         int stride = 1;
8413                         int i;
8414
8415                         if (length > 1 && size > 0)
8416                           stride = (idx_align & (1 << size)) ? 2 : 1;
8417
8418                         switch (length)
8419                           {
8420                           case 1:
8421                             {
8422                               int amask = (1 << size) - 1;
8423                               if ((idx_align & (1 << size)) != 0)
8424                                 return FALSE;
8425                               if (size > 0)
8426                                 {
8427                                   if ((idx_align & amask) == amask)
8428                                     align = 8 << size;
8429                                   else if ((idx_align & amask) != 0)
8430                                     return FALSE;
8431                                 }
8432                               }
8433                             break;
8434
8435                           case 2:
8436                             if (size == 2 && (idx_align & 2) != 0)
8437                               return FALSE;
8438                             align = (idx_align & 1) ? 16 << size : 0;
8439                             break;
8440
8441                           case 3:
8442                             if ((size == 2 && (idx_align & 3) != 0)
8443                                 || (idx_align & 1) != 0)
8444                               return FALSE;
8445                             break;
8446
8447                           case 4:
8448                             if (size == 2)
8449                               {
8450                                 if ((idx_align & 3) == 3)
8451                                   return FALSE;
8452                                 align = (idx_align & 3) * 64;
8453                               }
8454                             else
8455                               align = (idx_align & 1) ? 32 << size : 0;
8456                             break;
8457
8458                           default:
8459                             abort ();
8460                           }
8461
8462                         func (stream, "{");
8463                         for (i = 0; i < length; i++)
8464                           func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
8465                             rd + i * stride, idx);
8466                         func (stream, "}, [%s", arm_regnames[rn]);
8467                         if (align)
8468                           func (stream, " :%d", align);
8469                         func (stream, "]");
8470                         if (rm == 0xd)
8471                           func (stream, "!");
8472                         else if (rm != 0xf)
8473                           func (stream, ", %s", arm_regnames[rm]);
8474                       }
8475                       break;
8476
8477                     case 'C':
8478                       {
8479                         int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
8480                         int rn = ((given >> 16) & 0xf);
8481                         int rm = ((given >> 0) & 0xf);
8482                         int align = ((given >> 4) & 0x1);
8483                         int size = ((given >> 6) & 0x3);
8484                         int type = ((given >> 8) & 0x3);
8485                         int n = type + 1;
8486                         int stride = ((given >> 5) & 0x1);
8487                         int ix;
8488
8489                         if (stride && (n == 1))
8490                           n++;
8491                         else
8492                           stride++;
8493
8494                         func (stream, "{");
8495                         if (stride > 1)
8496                           for (ix = 0; ix != n; ix++)
8497                             func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
8498                         else if (n == 1)
8499                           func (stream, "d%d[]", rd);
8500                         else
8501                           func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
8502                         func (stream, "}, [%s", arm_regnames[rn]);
8503                         if (align)
8504                           {
8505                             align = (8 * (type + 1)) << size;
8506                             if (type == 3)
8507                               align = (size > 1) ? align >> 1 : align;
8508                             if (type == 2 || (type == 0 && !size))
8509                               func (stream, " :<bad align %d>", align);
8510                             else
8511                               func (stream, " :%d", align);
8512                           }
8513                         func (stream, "]");
8514                         if (rm == 0xd)
8515                           func (stream, "!");
8516                         else if (rm != 0xf)
8517                           func (stream, ", %s", arm_regnames[rm]);
8518                       }
8519                       break;
8520
8521                     case 'D':
8522                       {
8523                         int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
8524                         int size = (given >> 20) & 3;
8525                         int reg = raw_reg & ((4 << size) - 1);
8526                         int ix = raw_reg >> size >> 2;
8527
8528                         func (stream, "d%d[%d]", reg, ix);
8529                       }
8530                       break;
8531
8532                     case 'E':
8533                       /* Neon encoded constant for mov, mvn, vorr, vbic.  */
8534                       {
8535                         int bits = 0;
8536                         int cmode = (given >> 8) & 0xf;
8537                         int op = (given >> 5) & 0x1;
8538                         unsigned long value = 0, hival = 0;
8539                         unsigned shift;
8540                         int size = 0;
8541                         int isfloat = 0;
8542
8543                         bits |= ((given >> 24) & 1) << 7;
8544                         bits |= ((given >> 16) & 7) << 4;
8545                         bits |= ((given >> 0) & 15) << 0;
8546
8547                         if (cmode < 8)
8548                           {
8549                             shift = (cmode >> 1) & 3;
8550                             value = (unsigned long) bits << (8 * shift);
8551                             size = 32;
8552                           }
8553                         else if (cmode < 12)
8554                           {
8555                             shift = (cmode >> 1) & 1;
8556                             value = (unsigned long) bits << (8 * shift);
8557                             size = 16;
8558                           }
8559                         else if (cmode < 14)
8560                           {
8561                             shift = (cmode & 1) + 1;
8562                             value = (unsigned long) bits << (8 * shift);
8563                             value |= (1ul << (8 * shift)) - 1;
8564                             size = 32;
8565                           }
8566                         else if (cmode == 14)
8567                           {
8568                             if (op)
8569                               {
8570                                 /* Bit replication into bytes.  */
8571                                 int ix;
8572                                 unsigned long mask;
8573
8574                                 value = 0;
8575                                 hival = 0;
8576                                 for (ix = 7; ix >= 0; ix--)
8577                                   {
8578                                     mask = ((bits >> ix) & 1) ? 0xff : 0;
8579                                     if (ix <= 3)
8580                                       value = (value << 8) | mask;
8581                                     else
8582                                       hival = (hival << 8) | mask;
8583                                   }
8584                                 size = 64;
8585                               }
8586                             else
8587                               {
8588                                 /* Byte replication.  */
8589                                 value = (unsigned long) bits;
8590                                 size = 8;
8591                               }
8592                           }
8593                         else if (!op)
8594                           {
8595                             /* Floating point encoding.  */
8596                             int tmp;
8597
8598                             value = (unsigned long)  (bits & 0x7f) << 19;
8599                             value |= (unsigned long) (bits & 0x80) << 24;
8600                             tmp = bits & 0x40 ? 0x3c : 0x40;
8601                             value |= (unsigned long) tmp << 24;
8602                             size = 32;
8603                             isfloat = 1;
8604                           }
8605                         else
8606                           {
8607                             func (stream, "<illegal constant %.8x:%x:%x>",
8608                                   bits, cmode, op);
8609                             size = 32;
8610                             break;
8611                           }
8612                         switch (size)
8613                           {
8614                           case 8:
8615                             func (stream, "#%ld\t; 0x%.2lx", value, value);
8616                             break;
8617
8618                           case 16:
8619                             func (stream, "#%ld\t; 0x%.4lx", value, value);
8620                             break;
8621
8622                           case 32:
8623                             if (isfloat)
8624                               {
8625                                 unsigned char valbytes[4];
8626                                 double fvalue;
8627
8628                                 /* Do this a byte at a time so we don't have to
8629                                    worry about the host's endianness.  */
8630                                 valbytes[0] = value & 0xff;
8631                                 valbytes[1] = (value >> 8) & 0xff;
8632                                 valbytes[2] = (value >> 16) & 0xff;
8633                                 valbytes[3] = (value >> 24) & 0xff;
8634
8635                                 floatformat_to_double
8636                                   (& floatformat_ieee_single_little, valbytes,
8637                                   & fvalue);
8638
8639                                 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
8640                                       value);
8641                               }
8642                             else
8643                               func (stream, "#%ld\t; 0x%.8lx",
8644                                     (long) (((value & 0x80000000L) != 0)
8645                                             ? value | ~0xffffffffL : value),
8646                                     value);
8647                             break;
8648
8649                           case 64:
8650                             func (stream, "#0x%.8lx%.8lx", hival, value);
8651                             break;
8652
8653                           default:
8654                             abort ();
8655                           }
8656                       }
8657                       break;
8658
8659                     case 'F':
8660                       {
8661                         int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
8662                         int num = (given >> 8) & 0x3;
8663
8664                         if (!num)
8665                           func (stream, "{d%d}", regno);
8666                         else if (num + regno >= 32)
8667                           func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
8668                         else
8669                           func (stream, "{d%d-d%d}", regno, regno + num);
8670                       }
8671                       break;
8672
8673
8674                     case '0': case '1': case '2': case '3': case '4':
8675                     case '5': case '6': case '7': case '8': case '9':
8676                       {
8677                         int width;
8678                         unsigned long value;
8679
8680                         c = arm_decode_bitfield (c, given, &value, &width);
8681
8682                         switch (*c)
8683                           {
8684                           case 'r':
8685                             func (stream, "%s", arm_regnames[value]);
8686                             break;
8687                           case 'd':
8688                             func (stream, "%ld", value);
8689                             value_in_comment = value;
8690                             break;
8691                           case 'e':
8692                             func (stream, "%ld", (1ul << width) - value);
8693                             break;
8694
8695                           case 'S':
8696                           case 'T':
8697                           case 'U':
8698                             /* Various width encodings.  */
8699                             {
8700                               int base = 8 << (*c - 'S'); /* 8,16 or 32 */
8701                               int limit;
8702                               unsigned low, high;
8703
8704                               c++;
8705                               if (*c >= '0' && *c <= '9')
8706                                 limit = *c - '0';
8707                               else if (*c >= 'a' && *c <= 'f')
8708                                 limit = *c - 'a' + 10;
8709                               else
8710                                 abort ();
8711                               low = limit >> 2;
8712                               high = limit & 3;
8713
8714                               if (value < low || value > high)
8715                                 func (stream, "<illegal width %d>", base << value);
8716                               else
8717                                 func (stream, "%d", base << value);
8718                             }
8719                             break;
8720                           case 'R':
8721                             if (given & (1 << 6))
8722                               goto Q;
8723                             /* FALLTHROUGH */
8724                           case 'D':
8725                             func (stream, "d%ld", value);
8726                             break;
8727                           case 'Q':
8728                           Q:
8729                             if (value & 1)
8730                               func (stream, "<illegal reg q%ld.5>", value >> 1);
8731                             else
8732                               func (stream, "q%ld", value >> 1);
8733                             break;
8734
8735                           case '`':
8736                             c++;
8737                             if (value == 0)
8738                               func (stream, "%c", *c);
8739                             break;
8740                           case '\'':
8741                             c++;
8742                             if (value == ((1ul << width) - 1))
8743                               func (stream, "%c", *c);
8744                             break;
8745                           case '?':
8746                             func (stream, "%c", c[(1 << width) - (int) value]);
8747                             c += 1 << width;
8748                             break;
8749                           default:
8750                             abort ();
8751                           }
8752                       }
8753                       break;
8754
8755                     default:
8756                       abort ();
8757                     }
8758                 }
8759               else
8760                 func (stream, "%c", *c);
8761             }
8762
8763           if (value_in_comment > 32 || value_in_comment < -16)
8764             func (stream, "\t; 0x%lx", value_in_comment);
8765
8766           if (is_unpredictable)
8767             func (stream, UNPREDICTABLE_INSTRUCTION);
8768
8769           return TRUE;
8770         }
8771     }
8772   return FALSE;
8773 }
8774
8775 /* Print one mve instruction on INFO->STREAM.
8776    Return TRUE if the instuction matched, FALSE if this is not a
8777    recognised mve instruction.  */
8778
8779 static bfd_boolean
8780 print_insn_mve (struct disassemble_info *info, long given)
8781 {
8782   const struct mopcode32 *insn;
8783   void *stream = info->stream;
8784   fprintf_ftype func = info->fprintf_func;
8785
8786   for (insn = mve_opcodes; insn->assembler; insn++)
8787     {
8788       if (((given & insn->mask) == insn->value)
8789           && !is_mve_encoding_conflict (given, insn->mve_op))
8790         {
8791           signed long value_in_comment = 0;
8792           bfd_boolean is_unpredictable = FALSE;
8793           bfd_boolean is_undefined = FALSE;
8794           const char *c;
8795           enum mve_unpredictable unpredictable_cond = UNPRED_NONE;
8796           enum mve_undefined undefined_cond = UNDEF_NONE;
8797
8798           /* Most vector mve instruction are illegal in a it block.
8799              There are a few exceptions; check for them.  */
8800           if (ifthen_state && !is_mve_okay_in_it (insn->mve_op))
8801             {
8802               is_unpredictable = TRUE;
8803               unpredictable_cond = UNPRED_IT_BLOCK;
8804             }
8805           else if (is_mve_unpredictable (given, insn->mve_op,
8806                                          &unpredictable_cond))
8807             is_unpredictable = TRUE;
8808
8809           if (is_mve_undefined (given, insn->mve_op, &undefined_cond))
8810             is_undefined = TRUE;
8811
8812           for (c = insn->assembler; *c; c++)
8813             {
8814               if (*c == '%')
8815                 {
8816                   switch (*++c)
8817                     {
8818                     case '%':
8819                       func (stream, "%%");
8820                       break;
8821
8822                     case 'a':
8823                       /* Don't print anything for '+' as it is implied.  */
8824                       if (arm_decode_field (given, 23, 23) == 0)
8825                         func (stream, "-");
8826                       break;
8827
8828                     case 'c':
8829                       if (ifthen_state)
8830                         func (stream, "%s", arm_conditional[IFTHEN_COND]);
8831                       break;
8832
8833                     case 'd':
8834                       print_mve_vld_str_addr (info, given, insn->mve_op);
8835                       break;
8836
8837                     case 'i':
8838                       {
8839                         long mve_mask = mve_extract_pred_mask (given);
8840                         func (stream, "%s", mve_predicatenames[mve_mask]);
8841                       }
8842                       break;
8843
8844                     case 'n':
8845                       print_vec_condition (info, given, insn->mve_op);
8846                       break;
8847
8848                     case 'o':
8849                       if (arm_decode_field (given, 0, 0) == 1)
8850                         {
8851                           unsigned long size
8852                             = arm_decode_field (given, 4, 4)
8853                               | (arm_decode_field (given, 6, 6) << 1);
8854
8855                           func (stream, ", uxtw #%lu", size);
8856                         }
8857                       break;
8858
8859                     case 'm':
8860                       print_mve_rounding_mode (info, given, insn->mve_op);
8861                       break;
8862
8863                     case 's':
8864                       print_mve_vcvt_size (info, given, insn->mve_op);
8865                       break;
8866
8867                     case 'u':
8868                       {
8869                         unsigned long op1 = arm_decode_field (given, 21, 22);
8870
8871                         if ((insn->mve_op == MVE_VMOV_VEC_LANE_TO_GP))
8872                           {
8873                             /* Check for signed.  */
8874                             if (arm_decode_field (given, 23, 23) == 0)
8875                               {
8876                                 /* We don't print 's' for S32.  */
8877                                 if ((arm_decode_field (given, 5, 6) == 0)
8878                                     && ((op1 == 0) || (op1 == 1)))
8879                                   ;
8880                                 else
8881                                   func (stream, "s");
8882                               }
8883                             else
8884                               func (stream, "u");
8885                           }
8886                         else
8887                           {
8888                             if (arm_decode_field (given, 28, 28) == 0)
8889                               func (stream, "s");
8890                             else
8891                               func (stream, "u");
8892                           }
8893                       }
8894                       break;
8895
8896                     case 'v':
8897                       print_instruction_predicate (info);
8898                       break;
8899
8900                     case 'w':
8901                       if (arm_decode_field (given, 21, 21) == 1)
8902                         func (stream, "!");
8903                       break;
8904
8905                     case 'B':
8906                       print_mve_register_blocks (info, given, insn->mve_op);
8907                       break;
8908
8909                     case 'E':
8910                       /* SIMD encoded constant for mov, mvn, vorr, vbic.  */
8911
8912                       print_simd_imm8 (info, given, 28, insn);
8913                       break;
8914
8915                     case 'N':
8916                       print_mve_vmov_index (info, given);
8917                       break;
8918
8919                     case 'T':
8920                       if (arm_decode_field (given, 12, 12) == 0)
8921                         func (stream, "b");
8922                       else
8923                         func (stream, "t");
8924                       break;
8925
8926                     case 'X':
8927                       if (arm_decode_field (given, 12, 12) == 1)
8928                         func (stream, "x");
8929                       break;
8930
8931                     case '0': case '1': case '2': case '3': case '4':
8932                     case '5': case '6': case '7': case '8': case '9':
8933                       {
8934                         int width;
8935                         unsigned long value;
8936
8937                         c = arm_decode_bitfield (c, given, &value, &width);
8938
8939                         switch (*c)
8940                           {
8941                           case 'Z':
8942                             if (value == 13)
8943                               is_unpredictable = TRUE;
8944                             else if (value == 15)
8945                               func (stream, "zr");
8946                             else
8947                               func (stream, "%s", arm_regnames[value]);
8948                             break;
8949                           case 's':
8950                             print_mve_size (info,
8951                                             value,
8952                                             insn->mve_op);
8953                             break;
8954                           case 'I':
8955                             if (value == 1)
8956                               func (stream, "i");
8957                             break;
8958                           case 'A':
8959                             if (value == 1)
8960                               func (stream, "a");
8961                             break;
8962                           case 'h':
8963                             {
8964                               unsigned int odd_reg = (value << 1) | 1;
8965                               func (stream, "%s", arm_regnames[odd_reg]);
8966                             }
8967                             break;
8968                           case 'i':
8969                             {
8970                               unsigned long imm
8971                                 = arm_decode_field (given, 0, 6);
8972                               unsigned long mod_imm = imm;
8973
8974                               switch (insn->mve_op)
8975                                 {
8976                                 case MVE_VLDRW_GATHER_T5:
8977                                 case MVE_VSTRW_SCATTER_T5:
8978                                   mod_imm = mod_imm << 2;
8979                                   break;
8980                                 case MVE_VSTRD_SCATTER_T6:
8981                                 case MVE_VLDRD_GATHER_T6:
8982                                   mod_imm = mod_imm << 3;
8983                                   break;
8984
8985                                 default:
8986                                   break;
8987                                 }
8988
8989                               func (stream, "%lu", mod_imm);
8990                             }
8991                             break;
8992                           case 'k':
8993                             func (stream, "%lu", 64 - value);
8994                             break;
8995                           case 'l':
8996                             {
8997                               unsigned int even_reg = value << 1;
8998                               func (stream, "%s", arm_regnames[even_reg]);
8999                             }
9000                             break;
9001                           case 'u':
9002                             switch (value)
9003                               {
9004                               case 0:
9005                                 func (stream, "1");
9006                                 break;
9007                               case 1:
9008                                 func (stream, "2");
9009                                 break;
9010                               case 2:
9011                                 func (stream, "4");
9012                                 break;
9013                               case 3:
9014                                 func (stream, "8");
9015                                 break;
9016                               default:
9017                                 break;
9018                               }
9019                             break;
9020                           case 'o':
9021                             print_mve_rotate (info, value, width);
9022                             break;
9023                           case 'r':
9024                             func (stream, "%s", arm_regnames[value]);
9025                             break;
9026                           case 'd':
9027                             if (insn->mve_op == MVE_VQSHL_T2
9028                                 || insn->mve_op == MVE_VQSHLU_T3
9029                                 || insn->mve_op == MVE_VRSHR
9030                                 || insn->mve_op == MVE_VRSHRN
9031                                 || insn->mve_op == MVE_VSHL_T1
9032                                 || insn->mve_op == MVE_VSHLL_T1
9033                                 || insn->mve_op == MVE_VSHR
9034                                 || insn->mve_op == MVE_VSHRN
9035                                 || insn->mve_op == MVE_VSLI
9036                                 || insn->mve_op == MVE_VSRI)
9037                               print_mve_shift_n (info, given, insn->mve_op);
9038                             else if (insn->mve_op == MVE_VSHLL_T2)
9039                               {
9040                                 switch (value)
9041                                   {
9042                                   case 0x00:
9043                                     func (stream, "8");
9044                                     break;
9045                                   case 0x01:
9046                                     func (stream, "16");
9047                                     break;
9048                                   case 0x10:
9049                                     print_mve_undefined (info, UNDEF_SIZE_0);
9050                                     break;
9051                                   default:
9052                                     assert (0);
9053                                     break;
9054                                   }
9055                               }
9056                             else
9057                               {
9058                                 if (insn->mve_op == MVE_VSHLC && value == 0)
9059                                   value = 32;
9060                                 func (stream, "%ld", value);
9061                                 value_in_comment = value;
9062                               }
9063                             break;
9064                           case 'F':
9065                             func (stream, "s%ld", value);
9066                             break;
9067                           case 'Q':
9068                             if (value & 0x8)
9069                               func (stream, "<illegal reg q%ld.5>", value);
9070                             else
9071                               func (stream, "q%ld", value);
9072                             break;
9073                           case 'x':
9074                             func (stream, "0x%08lx", value);
9075                             break;
9076                           default:
9077                             abort ();
9078                           }
9079                         break;
9080                       default:
9081                         abort ();
9082                       }
9083                     }
9084                 }
9085               else
9086                 func (stream, "%c", *c);
9087             }
9088
9089           if (value_in_comment > 32 || value_in_comment < -16)
9090             func (stream, "\t; 0x%lx", value_in_comment);
9091
9092           if (is_unpredictable)
9093             print_mve_unpredictable (info, unpredictable_cond);
9094
9095           if (is_undefined)
9096             print_mve_undefined (info, undefined_cond);
9097
9098           if ((vpt_block_state.in_vpt_block == FALSE)
9099               && !ifthen_state
9100               && (is_vpt_instruction (given) == TRUE))
9101             mark_inside_vpt_block (given);
9102           else if (vpt_block_state.in_vpt_block == TRUE)
9103             update_vpt_block_state ();
9104
9105           return TRUE;
9106         }
9107     }
9108   return FALSE;
9109 }
9110
9111
9112 /* Return the name of a v7A special register.  */
9113
9114 static const char *
9115 banked_regname (unsigned reg)
9116 {
9117   switch (reg)
9118     {
9119       case 15: return "CPSR";
9120       case 32: return "R8_usr";
9121       case 33: return "R9_usr";
9122       case 34: return "R10_usr";
9123       case 35: return "R11_usr";
9124       case 36: return "R12_usr";
9125       case 37: return "SP_usr";
9126       case 38: return "LR_usr";
9127       case 40: return "R8_fiq";
9128       case 41: return "R9_fiq";
9129       case 42: return "R10_fiq";
9130       case 43: return "R11_fiq";
9131       case 44: return "R12_fiq";
9132       case 45: return "SP_fiq";
9133       case 46: return "LR_fiq";
9134       case 48: return "LR_irq";
9135       case 49: return "SP_irq";
9136       case 50: return "LR_svc";
9137       case 51: return "SP_svc";
9138       case 52: return "LR_abt";
9139       case 53: return "SP_abt";
9140       case 54: return "LR_und";
9141       case 55: return "SP_und";
9142       case 60: return "LR_mon";
9143       case 61: return "SP_mon";
9144       case 62: return "ELR_hyp";
9145       case 63: return "SP_hyp";
9146       case 79: return "SPSR";
9147       case 110: return "SPSR_fiq";
9148       case 112: return "SPSR_irq";
9149       case 114: return "SPSR_svc";
9150       case 116: return "SPSR_abt";
9151       case 118: return "SPSR_und";
9152       case 124: return "SPSR_mon";
9153       case 126: return "SPSR_hyp";
9154       default: return NULL;
9155     }
9156 }
9157
9158 /* Return the name of the DMB/DSB option.  */
9159 static const char *
9160 data_barrier_option (unsigned option)
9161 {
9162   switch (option & 0xf)
9163     {
9164     case 0xf: return "sy";
9165     case 0xe: return "st";
9166     case 0xd: return "ld";
9167     case 0xb: return "ish";
9168     case 0xa: return "ishst";
9169     case 0x9: return "ishld";
9170     case 0x7: return "un";
9171     case 0x6: return "unst";
9172     case 0x5: return "nshld";
9173     case 0x3: return "osh";
9174     case 0x2: return "oshst";
9175     case 0x1: return "oshld";
9176     default:  return NULL;
9177     }
9178 }
9179
9180 /* Print one ARM instruction from PC on INFO->STREAM.  */
9181
9182 static void
9183 print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
9184 {
9185   const struct opcode32 *insn;
9186   void *stream = info->stream;
9187   fprintf_ftype func = info->fprintf_func;
9188   struct arm_private_data *private_data = info->private_data;
9189
9190   if (print_insn_coprocessor (pc, info, given, FALSE))
9191     return;
9192
9193   if (print_insn_neon (info, given, FALSE))
9194     return;
9195
9196   for (insn = arm_opcodes; insn->assembler; insn++)
9197     {
9198       if ((given & insn->mask) != insn->value)
9199         continue;
9200
9201       if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features))
9202         continue;
9203
9204       /* Special case: an instruction with all bits set in the condition field
9205          (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
9206          or by the catchall at the end of the table.  */
9207       if ((given & 0xF0000000) != 0xF0000000
9208           || (insn->mask & 0xF0000000) == 0xF0000000
9209           || (insn->mask == 0 && insn->value == 0))
9210         {
9211           unsigned long u_reg = 16;
9212           unsigned long U_reg = 16;
9213           bfd_boolean is_unpredictable = FALSE;
9214           signed long value_in_comment = 0;
9215           const char *c;
9216
9217           for (c = insn->assembler; *c; c++)
9218             {
9219               if (*c == '%')
9220                 {
9221                   bfd_boolean allow_unpredictable = FALSE;
9222
9223                   switch (*++c)
9224                     {
9225                     case '%':
9226                       func (stream, "%%");
9227                       break;
9228
9229                     case 'a':
9230                       value_in_comment = print_arm_address (pc, info, given);
9231                       break;
9232
9233                     case 'P':
9234                       /* Set P address bit and use normal address
9235                          printing routine.  */
9236                       value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
9237                       break;
9238
9239                     case 'S':
9240                       allow_unpredictable = TRUE;
9241                       /* Fall through.  */
9242                     case 's':
9243                       if ((given & 0x004f0000) == 0x004f0000)
9244                         {
9245                           /* PC relative with immediate offset.  */
9246                           bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
9247
9248                           if (PRE_BIT_SET)
9249                             {
9250                               /* Elide positive zero offset.  */
9251                               if (offset || NEGATIVE_BIT_SET)
9252                                 func (stream, "[pc, #%s%d]\t; ",
9253                                       NEGATIVE_BIT_SET ? "-" : "", (int) offset);
9254                               else
9255                                 func (stream, "[pc]\t; ");
9256                               if (NEGATIVE_BIT_SET)
9257                                 offset = -offset;
9258                               info->print_address_func (offset + pc + 8, info);
9259                             }
9260                           else
9261                             {
9262                               /* Always show the offset.  */
9263                               func (stream, "[pc], #%s%d",
9264                                     NEGATIVE_BIT_SET ? "-" : "", (int) offset);
9265                               if (! allow_unpredictable)
9266                                 is_unpredictable = TRUE;
9267                             }
9268                         }
9269                       else
9270                         {
9271                           int offset = ((given & 0xf00) >> 4) | (given & 0xf);
9272
9273                           func (stream, "[%s",
9274                                 arm_regnames[(given >> 16) & 0xf]);
9275
9276                           if (PRE_BIT_SET)
9277                             {
9278                               if (IMMEDIATE_BIT_SET)
9279                                 {
9280                                   /* Elide offset for non-writeback
9281                                      positive zero.  */
9282                                   if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
9283                                       || offset)
9284                                     func (stream, ", #%s%d",
9285                                           NEGATIVE_BIT_SET ? "-" : "", offset);
9286
9287                                   if (NEGATIVE_BIT_SET)
9288                                     offset = -offset;
9289
9290                                   value_in_comment = offset;
9291                                 }
9292                               else
9293                                 {
9294                                   /* Register Offset or Register Pre-Indexed.  */
9295                                   func (stream, ", %s%s",
9296                                         NEGATIVE_BIT_SET ? "-" : "",
9297                                         arm_regnames[given & 0xf]);
9298
9299                                   /* Writing back to the register that is the source/
9300                                      destination of the load/store is unpredictable.  */
9301                                   if (! allow_unpredictable
9302                                       && WRITEBACK_BIT_SET
9303                                       && ((given & 0xf) == ((given >> 12) & 0xf)))
9304                                     is_unpredictable = TRUE;
9305                                 }
9306
9307                               func (stream, "]%s",
9308                                     WRITEBACK_BIT_SET ? "!" : "");
9309                             }
9310                           else
9311                             {
9312                               if (IMMEDIATE_BIT_SET)
9313                                 {
9314                                   /* Immediate Post-indexed.  */
9315                                   /* PR 10924: Offset must be printed, even if it is zero.  */
9316                                   func (stream, "], #%s%d",
9317                                         NEGATIVE_BIT_SET ? "-" : "", offset);
9318                                   if (NEGATIVE_BIT_SET)
9319                                     offset = -offset;
9320                                   value_in_comment = offset;
9321                                 }
9322                               else
9323                                 {
9324                                   /* Register Post-indexed.  */
9325                                   func (stream, "], %s%s",
9326                                         NEGATIVE_BIT_SET ? "-" : "",
9327                                         arm_regnames[given & 0xf]);
9328
9329                                   /* Writing back to the register that is the source/
9330                                      destination of the load/store is unpredictable.  */
9331                                   if (! allow_unpredictable
9332                                       && (given & 0xf) == ((given >> 12) & 0xf))
9333                                     is_unpredictable = TRUE;
9334                                 }
9335
9336                               if (! allow_unpredictable)
9337                                 {
9338                                   /* Writeback is automatically implied by post- addressing.
9339                                      Setting the W bit is unnecessary and ARM specify it as
9340                                      being unpredictable.  */
9341                                   if (WRITEBACK_BIT_SET
9342                                       /* Specifying the PC register as the post-indexed
9343                                          registers is also unpredictable.  */
9344                                       || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
9345                                     is_unpredictable = TRUE;
9346                                 }
9347                             }
9348                         }
9349                       break;
9350
9351                     case 'b':
9352                       {
9353                         bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
9354                         info->print_address_func (disp * 4 + pc + 8, info);
9355                       }
9356                       break;
9357
9358                     case 'c':
9359                       if (((given >> 28) & 0xf) != 0xe)
9360                         func (stream, "%s",
9361                               arm_conditional [(given >> 28) & 0xf]);
9362                       break;
9363
9364                     case 'm':
9365                       {
9366                         int started = 0;
9367                         int reg;
9368
9369                         func (stream, "{");
9370                         for (reg = 0; reg < 16; reg++)
9371                           if ((given & (1 << reg)) != 0)
9372                             {
9373                               if (started)
9374                                 func (stream, ", ");
9375                               started = 1;
9376                               func (stream, "%s", arm_regnames[reg]);
9377                             }
9378                         func (stream, "}");
9379                         if (! started)
9380                           is_unpredictable = TRUE;
9381                       }
9382                       break;
9383
9384                     case 'q':
9385                       arm_decode_shift (given, func, stream, FALSE);
9386                       break;
9387
9388                     case 'o':
9389                       if ((given & 0x02000000) != 0)
9390                         {
9391                           unsigned int rotate = (given & 0xf00) >> 7;
9392                           unsigned int immed = (given & 0xff);
9393                           unsigned int a, i;
9394
9395                           a = (((immed << (32 - rotate))
9396                                 | (immed >> rotate)) & 0xffffffff);
9397                           /* If there is another encoding with smaller rotate,
9398                              the rotate should be specified directly.  */
9399                           for (i = 0; i < 32; i += 2)
9400                             if ((a << i | a >> (32 - i)) <= 0xff)
9401                               break;
9402
9403                           if (i != rotate)
9404                             func (stream, "#%d, %d", immed, rotate);
9405                           else
9406                             func (stream, "#%d", a);
9407                           value_in_comment = a;
9408                         }
9409                       else
9410                         arm_decode_shift (given, func, stream, TRUE);
9411                       break;
9412
9413                     case 'p':
9414                       if ((given & 0x0000f000) == 0x0000f000)
9415                         {
9416                           arm_feature_set arm_ext_v6 =
9417                             ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
9418
9419                           /* The p-variants of tst/cmp/cmn/teq are the pre-V6
9420                              mechanism for setting PSR flag bits.  They are
9421                              obsolete in V6 onwards.  */
9422                           if (! ARM_CPU_HAS_FEATURE (private_data->features, \
9423                                                      arm_ext_v6))
9424                             func (stream, "p");
9425                           else
9426                             is_unpredictable = TRUE;
9427                         }
9428                       break;
9429
9430                     case 't':
9431                       if ((given & 0x01200000) == 0x00200000)
9432                         func (stream, "t");
9433                       break;
9434
9435                     case 'A':
9436                       {
9437                         int offset = given & 0xff;
9438
9439                         value_in_comment = offset * 4;
9440                         if (NEGATIVE_BIT_SET)
9441                           value_in_comment = - value_in_comment;
9442
9443                         func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
9444
9445                         if (PRE_BIT_SET)
9446                           {
9447                             if (offset)
9448                               func (stream, ", #%d]%s",
9449                                     (int) value_in_comment,
9450                                     WRITEBACK_BIT_SET ? "!" : "");
9451                             else
9452                               func (stream, "]");
9453                           }
9454                         else
9455                           {
9456                             func (stream, "]");
9457
9458                             if (WRITEBACK_BIT_SET)
9459                               {
9460                                 if (offset)
9461                                   func (stream, ", #%d", (int) value_in_comment);
9462                               }
9463                             else
9464                               {
9465                                 func (stream, ", {%d}", (int) offset);
9466                                 value_in_comment = offset;
9467                               }
9468                           }
9469                       }
9470                       break;
9471
9472                     case 'B':
9473                       /* Print ARM V5 BLX(1) address: pc+25 bits.  */
9474                       {
9475                         bfd_vma address;
9476                         bfd_vma offset = 0;
9477
9478                         if (! NEGATIVE_BIT_SET)
9479                           /* Is signed, hi bits should be ones.  */
9480                           offset = (-1) ^ 0x00ffffff;
9481
9482                         /* Offset is (SignExtend(offset field)<<2).  */
9483                         offset += given & 0x00ffffff;
9484                         offset <<= 2;
9485                         address = offset + pc + 8;
9486
9487                         if (given & 0x01000000)
9488                           /* H bit allows addressing to 2-byte boundaries.  */
9489                           address += 2;
9490
9491                         info->print_address_func (address, info);
9492                       }
9493                       break;
9494
9495                     case 'C':
9496                       if ((given & 0x02000200) == 0x200)
9497                         {
9498                           const char * name;
9499                           unsigned sysm = (given & 0x004f0000) >> 16;
9500
9501                           sysm |= (given & 0x300) >> 4;
9502                           name = banked_regname (sysm);
9503
9504                           if (name != NULL)
9505                             func (stream, "%s", name);
9506                           else
9507                             func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
9508                         }
9509                       else
9510                         {
9511                           func (stream, "%cPSR_",
9512                                 (given & 0x00400000) ? 'S' : 'C');
9513                           if (given & 0x80000)
9514                             func (stream, "f");
9515                           if (given & 0x40000)
9516                             func (stream, "s");
9517                           if (given & 0x20000)
9518                             func (stream, "x");
9519                           if (given & 0x10000)
9520                             func (stream, "c");
9521                         }
9522                       break;
9523
9524                     case 'U':
9525                       if ((given & 0xf0) == 0x60)
9526                         {
9527                           switch (given & 0xf)
9528                             {
9529                             case 0xf: func (stream, "sy"); break;
9530                             default:
9531                               func (stream, "#%d", (int) given & 0xf);
9532                               break;
9533                             }
9534                         }
9535                       else
9536                         {
9537                           const char * opt = data_barrier_option (given & 0xf);
9538                           if (opt != NULL)
9539                             func (stream, "%s", opt);
9540                           else
9541                               func (stream, "#%d", (int) given & 0xf);
9542                         }
9543                       break;
9544
9545                     case '0': case '1': case '2': case '3': case '4':
9546                     case '5': case '6': case '7': case '8': case '9':
9547                       {
9548                         int width;
9549                         unsigned long value;
9550
9551                         c = arm_decode_bitfield (c, given, &value, &width);
9552
9553                         switch (*c)
9554                           {
9555                           case 'R':
9556                             if (value == 15)
9557                               is_unpredictable = TRUE;
9558                             /* Fall through.  */
9559                           case 'r':
9560                           case 'T':
9561                             /* We want register + 1 when decoding T.  */
9562                             if (*c == 'T')
9563                               ++value;
9564
9565                             if (c[1] == 'u')
9566                               {
9567                                 /* Eat the 'u' character.  */
9568                                 ++ c;
9569
9570                                 if (u_reg == value)
9571                                   is_unpredictable = TRUE;
9572                                 u_reg = value;
9573                               }
9574                             if (c[1] == 'U')
9575                               {
9576                                 /* Eat the 'U' character.  */
9577                                 ++ c;
9578
9579                                 if (U_reg == value)
9580                                   is_unpredictable = TRUE;
9581                                 U_reg = value;
9582                               }
9583                             func (stream, "%s", arm_regnames[value]);
9584                             break;
9585                           case 'd':
9586                             func (stream, "%ld", value);
9587                             value_in_comment = value;
9588                             break;
9589                           case 'b':
9590                             func (stream, "%ld", value * 8);
9591                             value_in_comment = value * 8;
9592                             break;
9593                           case 'W':
9594                             func (stream, "%ld", value + 1);
9595                             value_in_comment = value + 1;
9596                             break;
9597                           case 'x':
9598                             func (stream, "0x%08lx", value);
9599
9600                             /* Some SWI instructions have special
9601                                meanings.  */
9602                             if ((given & 0x0fffffff) == 0x0FF00000)
9603                               func (stream, "\t; IMB");
9604                             else if ((given & 0x0fffffff) == 0x0FF00001)
9605                               func (stream, "\t; IMBRange");
9606                             break;
9607                           case 'X':
9608                             func (stream, "%01lx", value & 0xf);
9609                             value_in_comment = value;
9610                             break;
9611                           case '`':
9612                             c++;
9613                             if (value == 0)
9614                               func (stream, "%c", *c);
9615                             break;
9616                           case '\'':
9617                             c++;
9618                             if (value == ((1ul << width) - 1))
9619                               func (stream, "%c", *c);
9620                             break;
9621                           case '?':
9622                             func (stream, "%c", c[(1 << width) - (int) value]);
9623                             c += 1 << width;
9624                             break;
9625                           default:
9626                             abort ();
9627                           }
9628                       }
9629                       break;
9630
9631                     case 'e':
9632                       {
9633                         int imm;
9634
9635                         imm = (given & 0xf) | ((given & 0xfff00) >> 4);
9636                         func (stream, "%d", imm);
9637                         value_in_comment = imm;
9638                       }
9639                       break;
9640
9641                     case 'E':
9642                       /* LSB and WIDTH fields of BFI or BFC.  The machine-
9643                          language instruction encodes LSB and MSB.  */
9644                       {
9645                         long msb = (given & 0x001f0000) >> 16;
9646                         long lsb = (given & 0x00000f80) >> 7;
9647                         long w = msb - lsb + 1;
9648
9649                         if (w > 0)
9650                           func (stream, "#%lu, #%lu", lsb, w);
9651                         else
9652                           func (stream, "(invalid: %lu:%lu)", lsb, msb);
9653                       }
9654                       break;
9655
9656                     case 'R':
9657                       /* Get the PSR/banked register name.  */
9658                       {
9659                         const char * name;
9660                         unsigned sysm = (given & 0x004f0000) >> 16;
9661
9662                         sysm |= (given & 0x300) >> 4;
9663                         name = banked_regname (sysm);
9664
9665                         if (name != NULL)
9666                           func (stream, "%s", name);
9667                         else
9668                           func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
9669                       }
9670                       break;
9671
9672                     case 'V':
9673                       /* 16-bit unsigned immediate from a MOVT or MOVW
9674                          instruction, encoded in bits 0:11 and 15:19.  */
9675                       {
9676                         long hi = (given & 0x000f0000) >> 4;
9677                         long lo = (given & 0x00000fff);
9678                         long imm16 = hi | lo;
9679
9680                         func (stream, "#%lu", imm16);
9681                         value_in_comment = imm16;
9682                       }
9683                       break;
9684
9685                     default:
9686                       abort ();
9687                     }
9688                 }
9689               else
9690                 func (stream, "%c", *c);
9691             }
9692
9693           if (value_in_comment > 32 || value_in_comment < -16)
9694             func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
9695
9696           if (is_unpredictable)
9697             func (stream, UNPREDICTABLE_INSTRUCTION);
9698
9699           return;
9700         }
9701     }
9702   func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
9703   return;
9704 }
9705
9706 /* Print one 16-bit Thumb instruction from PC on INFO->STREAM.  */
9707
9708 static void
9709 print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
9710 {
9711   const struct opcode16 *insn;
9712   void *stream = info->stream;
9713   fprintf_ftype func = info->fprintf_func;
9714
9715   for (insn = thumb_opcodes; insn->assembler; insn++)
9716     if ((given & insn->mask) == insn->value)
9717       {
9718         signed long value_in_comment = 0;
9719         const char *c = insn->assembler;
9720
9721         for (; *c; c++)
9722           {
9723             int domaskpc = 0;
9724             int domasklr = 0;
9725
9726             if (*c != '%')
9727               {
9728                 func (stream, "%c", *c);
9729                 continue;
9730               }
9731
9732             switch (*++c)
9733               {
9734               case '%':
9735                 func (stream, "%%");
9736                 break;
9737
9738               case 'c':
9739                 if (ifthen_state)
9740                   func (stream, "%s", arm_conditional[IFTHEN_COND]);
9741                 break;
9742
9743               case 'C':
9744                 if (ifthen_state)
9745                   func (stream, "%s", arm_conditional[IFTHEN_COND]);
9746                 else
9747                   func (stream, "s");
9748                 break;
9749
9750               case 'I':
9751                 {
9752                   unsigned int tmp;
9753
9754                   ifthen_next_state = given & 0xff;
9755                   for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
9756                     func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
9757                   func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
9758                 }
9759                 break;
9760
9761               case 'x':
9762                 if (ifthen_next_state)
9763                   func (stream, "\t; unpredictable branch in IT block\n");
9764                 break;
9765
9766               case 'X':
9767                 if (ifthen_state)
9768                   func (stream, "\t; unpredictable <IT:%s>",
9769                         arm_conditional[IFTHEN_COND]);
9770                 break;
9771
9772               case 'S':
9773                 {
9774                   long reg;
9775
9776                   reg = (given >> 3) & 0x7;
9777                   if (given & (1 << 6))
9778                     reg += 8;
9779
9780                   func (stream, "%s", arm_regnames[reg]);
9781                 }
9782                 break;
9783
9784               case 'D':
9785                 {
9786                   long reg;
9787
9788                   reg = given & 0x7;
9789                   if (given & (1 << 7))
9790                     reg += 8;
9791
9792                   func (stream, "%s", arm_regnames[reg]);
9793                 }
9794                 break;
9795
9796               case 'N':
9797                 if (given & (1 << 8))
9798                   domasklr = 1;
9799                 /* Fall through.  */
9800               case 'O':
9801                 if (*c == 'O' && (given & (1 << 8)))
9802                   domaskpc = 1;
9803                 /* Fall through.  */
9804               case 'M':
9805                 {
9806                   int started = 0;
9807                   int reg;
9808
9809                   func (stream, "{");
9810
9811                   /* It would be nice if we could spot
9812                      ranges, and generate the rS-rE format: */
9813                   for (reg = 0; (reg < 8); reg++)
9814                     if ((given & (1 << reg)) != 0)
9815                       {
9816                         if (started)
9817                           func (stream, ", ");
9818                         started = 1;
9819                         func (stream, "%s", arm_regnames[reg]);
9820                       }
9821
9822                   if (domasklr)
9823                     {
9824                       if (started)
9825                         func (stream, ", ");
9826                       started = 1;
9827                       func (stream, "%s", arm_regnames[14] /* "lr" */);
9828                     }
9829
9830                   if (domaskpc)
9831                     {
9832                       if (started)
9833                         func (stream, ", ");
9834                       func (stream, "%s", arm_regnames[15] /* "pc" */);
9835                     }
9836
9837                   func (stream, "}");
9838                 }
9839                 break;
9840
9841               case 'W':
9842                 /* Print writeback indicator for a LDMIA.  We are doing a
9843                    writeback if the base register is not in the register
9844                    mask.  */
9845                 if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
9846                   func (stream, "!");
9847                 break;
9848
9849               case 'b':
9850                 /* Print ARM V6T2 CZB address: pc+4+6 bits.  */
9851                 {
9852                   bfd_vma address = (pc + 4
9853                                      + ((given & 0x00f8) >> 2)
9854                                      + ((given & 0x0200) >> 3));
9855                   info->print_address_func (address, info);
9856                 }
9857                 break;
9858
9859               case 's':
9860                 /* Right shift immediate -- bits 6..10; 1-31 print
9861                    as themselves, 0 prints as 32.  */
9862                 {
9863                   long imm = (given & 0x07c0) >> 6;
9864                   if (imm == 0)
9865                     imm = 32;
9866                   func (stream, "#%ld", imm);
9867                 }
9868                 break;
9869
9870               case '0': case '1': case '2': case '3': case '4':
9871               case '5': case '6': case '7': case '8': case '9':
9872                 {
9873                   int bitstart = *c++ - '0';
9874                   int bitend = 0;
9875
9876                   while (*c >= '0' && *c <= '9')
9877                     bitstart = (bitstart * 10) + *c++ - '0';
9878
9879                   switch (*c)
9880                     {
9881                     case '-':
9882                       {
9883                         bfd_vma reg;
9884
9885                         c++;
9886                         while (*c >= '0' && *c <= '9')
9887                           bitend = (bitend * 10) + *c++ - '0';
9888                         if (!bitend)
9889                           abort ();
9890                         reg = given >> bitstart;
9891                         reg &= (2 << (bitend - bitstart)) - 1;
9892
9893                         switch (*c)
9894                           {
9895                           case 'r':
9896                             func (stream, "%s", arm_regnames[reg]);
9897                             break;
9898
9899                           case 'd':
9900                             func (stream, "%ld", (long) reg);
9901                             value_in_comment = reg;
9902                             break;
9903
9904                           case 'H':
9905                             func (stream, "%ld", (long) (reg << 1));
9906                             value_in_comment = reg << 1;
9907                             break;
9908
9909                           case 'W':
9910                             func (stream, "%ld", (long) (reg << 2));
9911                             value_in_comment = reg << 2;
9912                             break;
9913
9914                           case 'a':
9915                             /* PC-relative address -- the bottom two
9916                                bits of the address are dropped
9917                                before the calculation.  */
9918                             info->print_address_func
9919                               (((pc + 4) & ~3) + (reg << 2), info);
9920                             value_in_comment = 0;
9921                             break;
9922
9923                           case 'x':
9924                             func (stream, "0x%04lx", (long) reg);
9925                             break;
9926
9927                           case 'B':
9928                             reg = ((reg ^ (1 << bitend)) - (1 << bitend));
9929                             info->print_address_func (reg * 2 + pc + 4, info);
9930                             value_in_comment = 0;
9931                             break;
9932
9933                           case 'c':
9934                             func (stream, "%s", arm_conditional [reg]);
9935                             break;
9936
9937                           default:
9938                             abort ();
9939                           }
9940                       }
9941                       break;
9942
9943                     case '\'':
9944                       c++;
9945                       if ((given & (1 << bitstart)) != 0)
9946                         func (stream, "%c", *c);
9947                       break;
9948
9949                     case '?':
9950                       ++c;
9951                       if ((given & (1 << bitstart)) != 0)
9952                         func (stream, "%c", *c++);
9953                       else
9954                         func (stream, "%c", *++c);
9955                       break;
9956
9957                     default:
9958                       abort ();
9959                     }
9960                 }
9961                 break;
9962
9963               default:
9964                 abort ();
9965               }
9966           }
9967
9968         if (value_in_comment > 32 || value_in_comment < -16)
9969           func (stream, "\t; 0x%lx", value_in_comment);
9970         return;
9971       }
9972
9973   /* No match.  */
9974   func (stream, UNKNOWN_INSTRUCTION_16BIT, (unsigned)given);
9975   return;
9976 }
9977
9978 /* Return the name of an V7M special register.  */
9979
9980 static const char *
9981 psr_name (int regno)
9982 {
9983   switch (regno)
9984     {
9985     case 0x0: return "APSR";
9986     case 0x1: return "IAPSR";
9987     case 0x2: return "EAPSR";
9988     case 0x3: return "PSR";
9989     case 0x5: return "IPSR";
9990     case 0x6: return "EPSR";
9991     case 0x7: return "IEPSR";
9992     case 0x8: return "MSP";
9993     case 0x9: return "PSP";
9994     case 0xa: return "MSPLIM";
9995     case 0xb: return "PSPLIM";
9996     case 0x10: return "PRIMASK";
9997     case 0x11: return "BASEPRI";
9998     case 0x12: return "BASEPRI_MAX";
9999     case 0x13: return "FAULTMASK";
10000     case 0x14: return "CONTROL";
10001     case 0x88: return "MSP_NS";
10002     case 0x89: return "PSP_NS";
10003     case 0x8a: return "MSPLIM_NS";
10004     case 0x8b: return "PSPLIM_NS";
10005     case 0x90: return "PRIMASK_NS";
10006     case 0x91: return "BASEPRI_NS";
10007     case 0x93: return "FAULTMASK_NS";
10008     case 0x94: return "CONTROL_NS";
10009     case 0x98: return "SP_NS";
10010     default: return "<unknown>";
10011     }
10012 }
10013
10014 /* Print one 32-bit Thumb instruction from PC on INFO->STREAM.  */
10015
10016 static void
10017 print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
10018 {
10019   const struct opcode32 *insn;
10020   void *stream = info->stream;
10021   fprintf_ftype func = info->fprintf_func;
10022   bfd_boolean is_mve = is_mve_architecture (info);
10023
10024   if (print_insn_coprocessor (pc, info, given, TRUE))
10025     return;
10026
10027   if ((is_mve == FALSE) && print_insn_neon (info, given, TRUE))
10028     return;
10029
10030   if (is_mve && print_insn_mve (info, given))
10031     return;
10032
10033   for (insn = thumb32_opcodes; insn->assembler; insn++)
10034     if ((given & insn->mask) == insn->value)
10035       {
10036         bfd_boolean is_clrm = FALSE;
10037         bfd_boolean is_unpredictable = FALSE;
10038         signed long value_in_comment = 0;
10039         const char *c = insn->assembler;
10040
10041         for (; *c; c++)
10042           {
10043             if (*c != '%')
10044               {
10045                 func (stream, "%c", *c);
10046                 continue;
10047               }
10048
10049             switch (*++c)
10050               {
10051               case '%':
10052                 func (stream, "%%");
10053                 break;
10054
10055               case 'c':
10056                 if (ifthen_state)
10057                   func (stream, "%s", arm_conditional[IFTHEN_COND]);
10058                 break;
10059
10060               case 'x':
10061                 if (ifthen_next_state)
10062                   func (stream, "\t; unpredictable branch in IT block\n");
10063                 break;
10064
10065               case 'X':
10066                 if (ifthen_state)
10067                   func (stream, "\t; unpredictable <IT:%s>",
10068                         arm_conditional[IFTHEN_COND]);
10069                 break;
10070
10071               case 'I':
10072                 {
10073                   unsigned int imm12 = 0;
10074
10075                   imm12 |= (given & 0x000000ffu);
10076                   imm12 |= (given & 0x00007000u) >> 4;
10077                   imm12 |= (given & 0x04000000u) >> 15;
10078                   func (stream, "#%u", imm12);
10079                   value_in_comment = imm12;
10080                 }
10081                 break;
10082
10083               case 'M':
10084                 {
10085                   unsigned int bits = 0, imm, imm8, mod;
10086
10087                   bits |= (given & 0x000000ffu);
10088                   bits |= (given & 0x00007000u) >> 4;
10089                   bits |= (given & 0x04000000u) >> 15;
10090                   imm8 = (bits & 0x0ff);
10091                   mod = (bits & 0xf00) >> 8;
10092                   switch (mod)
10093                     {
10094                     case 0: imm = imm8; break;
10095                     case 1: imm = ((imm8 << 16) | imm8); break;
10096                     case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
10097                     case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
10098                     default:
10099                       mod  = (bits & 0xf80) >> 7;
10100                       imm8 = (bits & 0x07f) | 0x80;
10101                       imm  = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
10102                     }
10103                   func (stream, "#%u", imm);
10104                   value_in_comment = imm;
10105                 }
10106                 break;
10107
10108               case 'J':
10109                 {
10110                   unsigned int imm = 0;
10111
10112                   imm |= (given & 0x000000ffu);
10113                   imm |= (given & 0x00007000u) >> 4;
10114                   imm |= (given & 0x04000000u) >> 15;
10115                   imm |= (given & 0x000f0000u) >> 4;
10116                   func (stream, "#%u", imm);
10117                   value_in_comment = imm;
10118                 }
10119                 break;
10120
10121               case 'K':
10122                 {
10123                   unsigned int imm = 0;
10124
10125                   imm |= (given & 0x000f0000u) >> 16;
10126                   imm |= (given & 0x00000ff0u) >> 0;
10127                   imm |= (given & 0x0000000fu) << 12;
10128                   func (stream, "#%u", imm);
10129                   value_in_comment = imm;
10130                 }
10131                 break;
10132
10133               case 'H':
10134                 {
10135                   unsigned int imm = 0;
10136
10137                   imm |= (given & 0x000f0000u) >> 4;
10138                   imm |= (given & 0x00000fffu) >> 0;
10139                   func (stream, "#%u", imm);
10140                   value_in_comment = imm;
10141                 }
10142                 break;
10143
10144               case 'V':
10145                 {
10146                   unsigned int imm = 0;
10147
10148                   imm |= (given & 0x00000fffu);
10149                   imm |= (given & 0x000f0000u) >> 4;
10150                   func (stream, "#%u", imm);
10151                   value_in_comment = imm;
10152                 }
10153                 break;
10154
10155               case 'S':
10156                 {
10157                   unsigned int reg = (given & 0x0000000fu);
10158                   unsigned int stp = (given & 0x00000030u) >> 4;
10159                   unsigned int imm = 0;
10160                   imm |= (given & 0x000000c0u) >> 6;
10161                   imm |= (given & 0x00007000u) >> 10;
10162
10163                   func (stream, "%s", arm_regnames[reg]);
10164                   switch (stp)
10165                     {
10166                     case 0:
10167                       if (imm > 0)
10168                         func (stream, ", lsl #%u", imm);
10169                       break;
10170
10171                     case 1:
10172                       if (imm == 0)
10173                         imm = 32;
10174                       func (stream, ", lsr #%u", imm);
10175                       break;
10176
10177                     case 2:
10178                       if (imm == 0)
10179                         imm = 32;
10180                       func (stream, ", asr #%u", imm);
10181                       break;
10182
10183                     case 3:
10184                       if (imm == 0)
10185                         func (stream, ", rrx");
10186                       else
10187                         func (stream, ", ror #%u", imm);
10188                     }
10189                 }
10190                 break;
10191
10192               case 'a':
10193                 {
10194                   unsigned int Rn  = (given & 0x000f0000) >> 16;
10195                   unsigned int U   = ! NEGATIVE_BIT_SET;
10196                   unsigned int op  = (given & 0x00000f00) >> 8;
10197                   unsigned int i12 = (given & 0x00000fff);
10198                   unsigned int i8  = (given & 0x000000ff);
10199                   bfd_boolean writeback = FALSE, postind = FALSE;
10200                   bfd_vma offset = 0;
10201
10202                   func (stream, "[%s", arm_regnames[Rn]);
10203                   if (U) /* 12-bit positive immediate offset.  */
10204                     {
10205                       offset = i12;
10206                       if (Rn != 15)
10207                         value_in_comment = offset;
10208                     }
10209                   else if (Rn == 15) /* 12-bit negative immediate offset.  */
10210                     offset = - (int) i12;
10211                   else if (op == 0x0) /* Shifted register offset.  */
10212                     {
10213                       unsigned int Rm = (i8 & 0x0f);
10214                       unsigned int sh = (i8 & 0x30) >> 4;
10215
10216                       func (stream, ", %s", arm_regnames[Rm]);
10217                       if (sh)
10218                         func (stream, ", lsl #%u", sh);
10219                       func (stream, "]");
10220                       break;
10221                     }
10222                   else switch (op)
10223                     {
10224                     case 0xE:  /* 8-bit positive immediate offset.  */
10225                       offset = i8;
10226                       break;
10227
10228                     case 0xC:  /* 8-bit negative immediate offset.  */
10229                       offset = -i8;
10230                       break;
10231
10232                     case 0xF:  /* 8-bit + preindex with wb.  */
10233                       offset = i8;
10234                       writeback = TRUE;
10235                       break;
10236
10237                     case 0xD:  /* 8-bit - preindex with wb.  */
10238                       offset = -i8;
10239                       writeback = TRUE;
10240                       break;
10241
10242                     case 0xB:  /* 8-bit + postindex.  */
10243                       offset = i8;
10244                       postind = TRUE;
10245                       break;
10246
10247                     case 0x9:  /* 8-bit - postindex.  */
10248                       offset = -i8;
10249                       postind = TRUE;
10250                       break;
10251
10252                     default:
10253                       func (stream, ", <undefined>]");
10254                       goto skip;
10255                     }
10256
10257                   if (postind)
10258                     func (stream, "], #%d", (int) offset);
10259                   else
10260                     {
10261                       if (offset)
10262                         func (stream, ", #%d", (int) offset);
10263                       func (stream, writeback ? "]!" : "]");
10264                     }
10265
10266                   if (Rn == 15)
10267                     {
10268                       func (stream, "\t; ");
10269                       info->print_address_func (((pc + 4) & ~3) + offset, info);
10270                     }
10271                 }
10272               skip:
10273                 break;
10274
10275               case 'A':
10276                 {
10277                   unsigned int U   = ! NEGATIVE_BIT_SET;
10278                   unsigned int W   = WRITEBACK_BIT_SET;
10279                   unsigned int Rn  = (given & 0x000f0000) >> 16;
10280                   unsigned int off = (given & 0x000000ff);
10281
10282                   func (stream, "[%s", arm_regnames[Rn]);
10283
10284                   if (PRE_BIT_SET)
10285                     {
10286                       if (off || !U)
10287                         {
10288                           func (stream, ", #%c%u", U ? '+' : '-', off * 4);
10289                           value_in_comment = off * 4 * (U ? 1 : -1);
10290                         }
10291                       func (stream, "]");
10292                       if (W)
10293                         func (stream, "!");
10294                     }
10295                   else
10296                     {
10297                       func (stream, "], ");
10298                       if (W)
10299                         {
10300                           func (stream, "#%c%u", U ? '+' : '-', off * 4);
10301                           value_in_comment = off * 4 * (U ? 1 : -1);
10302                         }
10303                       else
10304                         {
10305                           func (stream, "{%u}", off);
10306                           value_in_comment = off;
10307                         }
10308                     }
10309                 }
10310                 break;
10311
10312               case 'w':
10313                 {
10314                   unsigned int Sbit = (given & 0x01000000) >> 24;
10315                   unsigned int type = (given & 0x00600000) >> 21;
10316
10317                   switch (type)
10318                     {
10319                     case 0: func (stream, Sbit ? "sb" : "b"); break;
10320                     case 1: func (stream, Sbit ? "sh" : "h"); break;
10321                     case 2:
10322                       if (Sbit)
10323                         func (stream, "??");
10324                       break;
10325                     case 3:
10326                       func (stream, "??");
10327                       break;
10328                     }
10329                 }
10330                 break;
10331
10332               case 'n':
10333                 is_clrm = TRUE;
10334                 /* Fall through.  */
10335               case 'm':
10336                 {
10337                   int started = 0;
10338                   int reg;
10339
10340                   func (stream, "{");
10341                   for (reg = 0; reg < 16; reg++)
10342                     if ((given & (1 << reg)) != 0)
10343                       {
10344                         if (started)
10345                           func (stream, ", ");
10346                         started = 1;
10347                         if (is_clrm && reg == 13)
10348                           func (stream, "(invalid: %s)", arm_regnames[reg]);
10349                         else if (is_clrm && reg == 15)
10350                           func (stream, "%s", "APSR");
10351                         else
10352                           func (stream, "%s", arm_regnames[reg]);
10353                       }
10354                   func (stream, "}");
10355                 }
10356                 break;
10357
10358               case 'E':
10359                 {
10360                   unsigned int msb = (given & 0x0000001f);
10361                   unsigned int lsb = 0;
10362
10363                   lsb |= (given & 0x000000c0u) >> 6;
10364                   lsb |= (given & 0x00007000u) >> 10;
10365                   func (stream, "#%u, #%u", lsb, msb - lsb + 1);
10366                 }
10367                 break;
10368
10369               case 'F':
10370                 {
10371                   unsigned int width = (given & 0x0000001f) + 1;
10372                   unsigned int lsb = 0;
10373
10374                   lsb |= (given & 0x000000c0u) >> 6;
10375                   lsb |= (given & 0x00007000u) >> 10;
10376                   func (stream, "#%u, #%u", lsb, width);
10377                 }
10378                 break;
10379
10380               case 'G':
10381                 {
10382                   unsigned int boff = (((given & 0x07800000) >> 23) << 1);
10383                   func (stream, "%x", boff);
10384                 }
10385                 break;
10386
10387               case 'W':
10388                 {
10389                   unsigned int immA = (given & 0x001f0000u) >> 16;
10390                   unsigned int immB = (given & 0x000007feu) >> 1;
10391                   unsigned int immC = (given & 0x00000800u) >> 11;
10392                   bfd_vma offset = 0;
10393
10394                   offset |= immA << 12;
10395                   offset |= immB << 2;
10396                   offset |= immC << 1;
10397                   /* Sign extend.  */
10398                   offset = (offset & 0x10000) ? offset - (1 << 17) : offset;
10399
10400                   info->print_address_func (pc + 4 + offset, info);
10401                 }
10402                 break;
10403
10404               case 'Y':
10405                 {
10406                   unsigned int immA = (given & 0x007f0000u) >> 16;
10407                   unsigned int immB = (given & 0x000007feu) >> 1;
10408                   unsigned int immC = (given & 0x00000800u) >> 11;
10409                   bfd_vma offset = 0;
10410
10411                   offset |= immA << 12;
10412                   offset |= immB << 2;
10413                   offset |= immC << 1;
10414                   /* Sign extend.  */
10415                   offset = (offset & 0x40000) ? offset - (1 << 19) : offset;
10416
10417                   info->print_address_func (pc + 4 + offset, info);
10418                 }
10419                 break;
10420
10421               case 'Z':
10422                 {
10423                   unsigned int immA = (given & 0x00010000u) >> 16;
10424                   unsigned int immB = (given & 0x000007feu) >> 1;
10425                   unsigned int immC = (given & 0x00000800u) >> 11;
10426                   bfd_vma offset = 0;
10427
10428                   offset |= immA << 12;
10429                   offset |= immB << 2;
10430                   offset |= immC << 1;
10431                   /* Sign extend.  */
10432                   offset = (offset & 0x1000) ? offset - (1 << 13) : offset;
10433
10434                   info->print_address_func (pc + 4 + offset, info);
10435
10436                   unsigned int T    = (given & 0x00020000u) >> 17;
10437                   unsigned int endoffset = (((given & 0x07800000) >> 23) << 1);
10438                   unsigned int boffset   = (T == 1) ? 4 : 2;
10439                   func (stream, ", ");
10440                   func (stream, "%x", endoffset + boffset);
10441                 }
10442                 break;
10443
10444               case 'Q':
10445                 {
10446                   unsigned int immh = (given & 0x000007feu) >> 1;
10447                   unsigned int imml = (given & 0x00000800u) >> 11;
10448                   bfd_vma imm32 = 0;
10449
10450                   imm32 |= immh << 2;
10451                   imm32 |= imml << 1;
10452
10453                   info->print_address_func (pc + 4 + imm32, info);
10454                 }
10455                 break;
10456
10457               case 'P':
10458                 {
10459                   unsigned int immh = (given & 0x000007feu) >> 1;
10460                   unsigned int imml = (given & 0x00000800u) >> 11;
10461                   bfd_vma imm32 = 0;
10462
10463                   imm32 |= immh << 2;
10464                   imm32 |= imml << 1;
10465
10466                   info->print_address_func (pc + 4 - imm32, info);
10467                 }
10468                 break;
10469
10470               case 'b':
10471                 {
10472                   unsigned int S = (given & 0x04000000u) >> 26;
10473                   unsigned int J1 = (given & 0x00002000u) >> 13;
10474                   unsigned int J2 = (given & 0x00000800u) >> 11;
10475                   bfd_vma offset = 0;
10476
10477                   offset |= !S << 20;
10478                   offset |= J2 << 19;
10479                   offset |= J1 << 18;
10480                   offset |= (given & 0x003f0000) >> 4;
10481                   offset |= (given & 0x000007ff) << 1;
10482                   offset -= (1 << 20);
10483
10484                   info->print_address_func (pc + 4 + offset, info);
10485                 }
10486                 break;
10487
10488               case 'B':
10489                 {
10490                   unsigned int S = (given & 0x04000000u) >> 26;
10491                   unsigned int I1 = (given & 0x00002000u) >> 13;
10492                   unsigned int I2 = (given & 0x00000800u) >> 11;
10493                   bfd_vma offset = 0;
10494
10495                   offset |= !S << 24;
10496                   offset |= !(I1 ^ S) << 23;
10497                   offset |= !(I2 ^ S) << 22;
10498                   offset |= (given & 0x03ff0000u) >> 4;
10499                   offset |= (given & 0x000007ffu) << 1;
10500                   offset -= (1 << 24);
10501                   offset += pc + 4;
10502
10503                   /* BLX target addresses are always word aligned.  */
10504                   if ((given & 0x00001000u) == 0)
10505                       offset &= ~2u;
10506
10507                   info->print_address_func (offset, info);
10508                 }
10509                 break;
10510
10511               case 's':
10512                 {
10513                   unsigned int shift = 0;
10514
10515                   shift |= (given & 0x000000c0u) >> 6;
10516                   shift |= (given & 0x00007000u) >> 10;
10517                   if (WRITEBACK_BIT_SET)
10518                     func (stream, ", asr #%u", shift);
10519                   else if (shift)
10520                     func (stream, ", lsl #%u", shift);
10521                   /* else print nothing - lsl #0 */
10522                 }
10523                 break;
10524
10525               case 'R':
10526                 {
10527                   unsigned int rot = (given & 0x00000030) >> 4;
10528
10529                   if (rot)
10530                     func (stream, ", ror #%u", rot * 8);
10531                 }
10532                 break;
10533
10534               case 'U':
10535                 if ((given & 0xf0) == 0x60)
10536                   {
10537                     switch (given & 0xf)
10538                       {
10539                         case 0xf: func (stream, "sy"); break;
10540                         default:
10541                           func (stream, "#%d", (int) given & 0xf);
10542                               break;
10543                       }
10544                   }
10545                 else
10546                   {
10547                     const char * opt = data_barrier_option (given & 0xf);
10548                     if (opt != NULL)
10549                       func (stream, "%s", opt);
10550                     else
10551                       func (stream, "#%d", (int) given & 0xf);
10552                    }
10553                 break;
10554
10555               case 'C':
10556                 if ((given & 0xff) == 0)
10557                   {
10558                     func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
10559                     if (given & 0x800)
10560                       func (stream, "f");
10561                     if (given & 0x400)
10562                       func (stream, "s");
10563                     if (given & 0x200)
10564                       func (stream, "x");
10565                     if (given & 0x100)
10566                       func (stream, "c");
10567                   }
10568                 else if ((given & 0x20) == 0x20)
10569                   {
10570                     char const* name;
10571                     unsigned sysm = (given & 0xf00) >> 8;
10572
10573                     sysm |= (given & 0x30);
10574                     sysm |= (given & 0x00100000) >> 14;
10575                     name = banked_regname (sysm);
10576
10577                     if (name != NULL)
10578                       func (stream, "%s", name);
10579                     else
10580                       func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
10581                   }
10582                 else
10583                   {
10584                     func (stream, "%s", psr_name (given & 0xff));
10585                   }
10586                 break;
10587
10588               case 'D':
10589                 if (((given & 0xff) == 0)
10590                     || ((given & 0x20) == 0x20))
10591                   {
10592                     char const* name;
10593                     unsigned sm = (given & 0xf0000) >> 16;
10594
10595                     sm |= (given & 0x30);
10596                     sm |= (given & 0x00100000) >> 14;
10597                     name = banked_regname (sm);
10598
10599                     if (name != NULL)
10600                       func (stream, "%s", name);
10601                     else
10602                       func (stream, "(UNDEF: %lu)", (unsigned long) sm);
10603                   }
10604                 else
10605                   func (stream, "%s", psr_name (given & 0xff));
10606                 break;
10607
10608               case '0': case '1': case '2': case '3': case '4':
10609               case '5': case '6': case '7': case '8': case '9':
10610                 {
10611                   int width;
10612                   unsigned long val;
10613
10614                   c = arm_decode_bitfield (c, given, &val, &width);
10615
10616                   switch (*c)
10617                     {
10618                     case 's':
10619                       if (val <= 3)
10620                         func (stream, "%s", mve_vec_sizename[val]);
10621                       else
10622                         func (stream, "<undef size>");
10623                       break;
10624
10625                     case 'd':
10626                       func (stream, "%lu", val);
10627                       value_in_comment = val;
10628                       break;
10629
10630                     case 'D':
10631                       func (stream, "%lu", val + 1);
10632                       value_in_comment = val + 1;
10633                       break;
10634
10635                     case 'W':
10636                       func (stream, "%lu", val * 4);
10637                       value_in_comment = val * 4;
10638                       break;
10639
10640                     case 'S':
10641                       if (val == 13)
10642                         is_unpredictable = TRUE;
10643                       /* Fall through.  */
10644                     case 'R':
10645                       if (val == 15)
10646                         is_unpredictable = TRUE;
10647                       /* Fall through.  */
10648                     case 'r':
10649                       func (stream, "%s", arm_regnames[val]);
10650                       break;
10651
10652                     case 'c':
10653                       func (stream, "%s", arm_conditional[val]);
10654                       break;
10655
10656                     case '\'':
10657                       c++;
10658                       if (val == ((1ul << width) - 1))
10659                         func (stream, "%c", *c);
10660                       break;
10661
10662                     case '`':
10663                       c++;
10664                       if (val == 0)
10665                         func (stream, "%c", *c);
10666                       break;
10667
10668                     case '?':
10669                       func (stream, "%c", c[(1 << width) - (int) val]);
10670                       c += 1 << width;
10671                       break;
10672
10673                     case 'x':
10674                       func (stream, "0x%lx", val & 0xffffffffUL);
10675                       break;
10676
10677                     default:
10678                       abort ();
10679                     }
10680                 }
10681                 break;
10682
10683               case 'L':
10684                 /* PR binutils/12534
10685                    If we have a PC relative offset in an LDRD or STRD
10686                    instructions then display the decoded address.  */
10687                 if (((given >> 16) & 0xf) == 0xf)
10688                   {
10689                     bfd_vma offset = (given & 0xff) * 4;
10690
10691                     if ((given & (1 << 23)) == 0)
10692                       offset = - offset;
10693                     func (stream, "\t; ");
10694                     info->print_address_func ((pc & ~3) + 4 + offset, info);
10695                   }
10696                 break;
10697
10698               default:
10699                 abort ();
10700               }
10701           }
10702
10703         if (value_in_comment > 32 || value_in_comment < -16)
10704           func (stream, "\t; 0x%lx", value_in_comment);
10705
10706         if (is_unpredictable)
10707           func (stream, UNPREDICTABLE_INSTRUCTION);
10708
10709         return;
10710       }
10711
10712   /* No match.  */
10713   func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
10714   return;
10715 }
10716
10717 /* Print data bytes on INFO->STREAM.  */
10718
10719 static void
10720 print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
10721                  struct disassemble_info *info,
10722                  long given)
10723 {
10724   switch (info->bytes_per_chunk)
10725     {
10726     case 1:
10727       info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
10728       break;
10729     case 2:
10730       info->fprintf_func (info->stream, ".short\t0x%04lx", given);
10731       break;
10732     case 4:
10733       info->fprintf_func (info->stream, ".word\t0x%08lx", given);
10734       break;
10735     default:
10736       abort ();
10737     }
10738 }
10739
10740 /* Disallow mapping symbols ($a, $b, $d, $t etc) from
10741    being displayed in symbol relative addresses.
10742
10743    Also disallow private symbol, with __tagsym$$ prefix,
10744    from ARM RVCT toolchain being displayed.  */
10745
10746 bfd_boolean
10747 arm_symbol_is_valid (asymbol * sym,
10748                      struct disassemble_info * info ATTRIBUTE_UNUSED)
10749 {
10750   const char * name;
10751
10752   if (sym == NULL)
10753     return FALSE;
10754
10755   name = bfd_asymbol_name (sym);
10756
10757   return (name && *name != '$' && strncmp (name, "__tagsym$$", 10));
10758 }
10759
10760 /* Parse the string of disassembler options.  */
10761
10762 static void
10763 parse_arm_disassembler_options (const char *options)
10764 {
10765   const char *opt;
10766
10767   FOR_EACH_DISASSEMBLER_OPTION (opt, options)
10768     {
10769       if (CONST_STRNEQ (opt, "reg-names-"))
10770         {
10771           unsigned int i;
10772           for (i = 0; i < NUM_ARM_OPTIONS; i++)
10773             if (disassembler_options_cmp (opt, regnames[i].name) == 0)
10774               {
10775                 regname_selected = i;
10776                 break;
10777               }
10778
10779           if (i >= NUM_ARM_OPTIONS)
10780             /* xgettext: c-format */
10781             opcodes_error_handler (_("unrecognised register name set: %s"),
10782                                    opt);
10783         }
10784       else if (CONST_STRNEQ (opt, "force-thumb"))
10785         force_thumb = 1;
10786       else if (CONST_STRNEQ (opt, "no-force-thumb"))
10787         force_thumb = 0;
10788       else
10789         /* xgettext: c-format */
10790         opcodes_error_handler (_("unrecognised disassembler option: %s"), opt);
10791     }
10792
10793   return;
10794 }
10795
10796 static bfd_boolean
10797 mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
10798                          enum map_type *map_symbol);
10799
10800 /* Search back through the insn stream to determine if this instruction is
10801    conditionally executed.  */
10802
10803 static void
10804 find_ifthen_state (bfd_vma pc,
10805                    struct disassemble_info *info,
10806                    bfd_boolean little)
10807 {
10808   unsigned char b[2];
10809   unsigned int insn;
10810   int status;
10811   /* COUNT is twice the number of instructions seen.  It will be odd if we
10812      just crossed an instruction boundary.  */
10813   int count;
10814   int it_count;
10815   unsigned int seen_it;
10816   bfd_vma addr;
10817
10818   ifthen_address = pc;
10819   ifthen_state = 0;
10820
10821   addr = pc;
10822   count = 1;
10823   it_count = 0;
10824   seen_it = 0;
10825   /* Scan backwards looking for IT instructions, keeping track of where
10826      instruction boundaries are.  We don't know if something is actually an
10827      IT instruction until we find a definite instruction boundary.  */
10828   for (;;)
10829     {
10830       if (addr == 0 || info->symbol_at_address_func (addr, info))
10831         {
10832           /* A symbol must be on an instruction boundary, and will not
10833              be within an IT block.  */
10834           if (seen_it && (count & 1))
10835             break;
10836
10837           return;
10838         }
10839       addr -= 2;
10840       status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
10841       if (status)
10842         return;
10843
10844       if (little)
10845         insn = (b[0]) | (b[1] << 8);
10846       else
10847         insn = (b[1]) | (b[0] << 8);
10848       if (seen_it)
10849         {
10850           if ((insn & 0xf800) < 0xe800)
10851             {
10852               /* Addr + 2 is an instruction boundary.  See if this matches
10853                  the expected boundary based on the position of the last
10854                  IT candidate.  */
10855               if (count & 1)
10856                 break;
10857               seen_it = 0;
10858             }
10859         }
10860       if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
10861         {
10862           enum map_type type = MAP_ARM;
10863           bfd_boolean found = mapping_symbol_for_insn (addr, info, &type);
10864
10865           if (!found || (found && type == MAP_THUMB))
10866             {
10867               /* This could be an IT instruction.  */
10868               seen_it = insn;
10869               it_count = count >> 1;
10870             }
10871         }
10872       if ((insn & 0xf800) >= 0xe800)
10873         count++;
10874       else
10875         count = (count + 2) | 1;
10876       /* IT blocks contain at most 4 instructions.  */
10877       if (count >= 8 && !seen_it)
10878         return;
10879     }
10880   /* We found an IT instruction.  */
10881   ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
10882   if ((ifthen_state & 0xf) == 0)
10883     ifthen_state = 0;
10884 }
10885
10886 /* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
10887    mapping symbol.  */
10888
10889 static int
10890 is_mapping_symbol (struct disassemble_info *info, int n,
10891                    enum map_type *map_type)
10892 {
10893   const char *name;
10894
10895   name = bfd_asymbol_name (info->symtab[n]);
10896   if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
10897       && (name[2] == 0 || name[2] == '.'))
10898     {
10899       *map_type = ((name[1] == 'a') ? MAP_ARM
10900                    : (name[1] == 't') ? MAP_THUMB
10901                    : MAP_DATA);
10902       return TRUE;
10903     }
10904
10905   return FALSE;
10906 }
10907
10908 /* Try to infer the code type (ARM or Thumb) from a mapping symbol.
10909    Returns nonzero if *MAP_TYPE was set.  */
10910
10911 static int
10912 get_map_sym_type (struct disassemble_info *info,
10913                   int n,
10914                   enum map_type *map_type)
10915 {
10916   /* If the symbol is in a different section, ignore it.  */
10917   if (info->section != NULL && info->section != info->symtab[n]->section)
10918     return FALSE;
10919
10920   return is_mapping_symbol (info, n, map_type);
10921 }
10922
10923 /* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
10924    Returns nonzero if *MAP_TYPE was set.  */
10925
10926 static int
10927 get_sym_code_type (struct disassemble_info *info,
10928                    int n,
10929                    enum map_type *map_type)
10930 {
10931   elf_symbol_type *es;
10932   unsigned int type;
10933
10934   /* If the symbol is in a different section, ignore it.  */
10935   if (info->section != NULL && info->section != info->symtab[n]->section)
10936     return FALSE;
10937
10938   es = *(elf_symbol_type **)(info->symtab + n);
10939   type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
10940
10941   /* If the symbol has function type then use that.  */
10942   if (type == STT_FUNC || type == STT_GNU_IFUNC)
10943     {
10944       if (ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
10945           == ST_BRANCH_TO_THUMB)
10946         *map_type = MAP_THUMB;
10947       else
10948         *map_type = MAP_ARM;
10949       return TRUE;
10950     }
10951
10952   return FALSE;
10953 }
10954
10955 /* Search the mapping symbol state for instruction at pc.  This is only
10956    applicable for elf target.
10957
10958    There is an assumption Here, info->private_data contains the correct AND
10959    up-to-date information about current scan process.  The information will be
10960    used to speed this search process.
10961
10962    Return TRUE if the mapping state can be determined, and map_symbol
10963    will be updated accordingly.  Otherwise, return FALSE.  */
10964
10965 static bfd_boolean
10966 mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
10967                          enum map_type *map_symbol)
10968 {
10969   bfd_vma addr, section_vma = 0;
10970   int n, last_sym = -1;
10971   bfd_boolean found = FALSE;
10972   bfd_boolean can_use_search_opt_p = FALSE;
10973
10974   /* Default to DATA.  A text section is required by the ABI to contain an
10975      INSN mapping symbol at the start.  A data section has no such
10976      requirement, hence if no mapping symbol is found the section must
10977      contain only data.  This however isn't very useful if the user has
10978      fully stripped the binaries.  If this is the case use the section
10979      attributes to determine the default.  If we have no section default to
10980      INSN as well, as we may be disassembling some raw bytes on a baremetal
10981      HEX file or similar.  */
10982   enum map_type type = MAP_DATA;
10983   if ((info->section && info->section->flags & SEC_CODE) || !info->section)
10984     type = MAP_ARM;
10985   struct arm_private_data *private_data;
10986
10987   if (info->private_data == NULL
10988       || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour)
10989     return FALSE;
10990
10991   private_data = info->private_data;
10992
10993   /* First, look for mapping symbols.  */
10994   if (info->symtab_size != 0)
10995   {
10996     if (pc <= private_data->last_mapping_addr)
10997       private_data->last_mapping_sym = -1;
10998
10999     /* Start scanning at the start of the function, or wherever
11000        we finished last time.  */
11001     n = info->symtab_pos + 1;
11002
11003     /* If the last stop offset is different from the current one it means we
11004        are disassembling a different glob of bytes.  As such the optimization
11005        would not be safe and we should start over.  */
11006     can_use_search_opt_p
11007       = private_data->last_mapping_sym >= 0
11008         && info->stop_offset == private_data->last_stop_offset;
11009
11010     if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
11011       n = private_data->last_mapping_sym;
11012
11013     /* Look down while we haven't passed the location being disassembled.
11014        The reason for this is that there's no defined order between a symbol
11015        and an mapping symbol that may be at the same address.  We may have to
11016        look at least one position ahead.  */
11017     for (; n < info->symtab_size; n++)
11018       {
11019         addr = bfd_asymbol_value (info->symtab[n]);
11020         if (addr > pc)
11021           break;
11022         if (get_map_sym_type (info, n, &type))
11023           {
11024             last_sym = n;
11025             found = TRUE;
11026           }
11027       }
11028
11029     if (!found)
11030       {
11031         n = info->symtab_pos;
11032         if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
11033           n = private_data->last_mapping_sym;
11034
11035         /* No mapping symbol found at this address.  Look backwards
11036            for a preceeding one, but don't go pass the section start
11037            otherwise a data section with no mapping symbol can pick up
11038            a text mapping symbol of a preceeding section.  The documentation
11039            says section can be NULL, in which case we will seek up all the
11040            way to the top.  */
11041         if (info->section)
11042           section_vma = info->section->vma;
11043
11044         for (; n >= 0; n--)
11045           {
11046             addr = bfd_asymbol_value (info->symtab[n]);
11047             if (addr < section_vma)
11048               break;
11049
11050             if (get_map_sym_type (info, n, &type))
11051               {
11052                 last_sym = n;
11053                 found = TRUE;
11054                 break;
11055               }
11056           }
11057       }
11058   }
11059
11060   /* If no mapping symbol was found, try looking up without a mapping
11061      symbol.  This is done by walking up from the current PC to the nearest
11062      symbol.  We don't actually have to loop here since symtab_pos will
11063      contain the nearest symbol already.  */
11064   if (!found)
11065     {
11066       n = info->symtab_pos;
11067       if (n >= 0 && get_sym_code_type (info, n, &type))
11068         {
11069           last_sym = n;
11070           found = TRUE;
11071         }
11072     }
11073
11074   private_data->last_mapping_sym = last_sym;
11075   private_data->last_type = type;
11076   private_data->last_stop_offset = info->stop_offset;
11077
11078   *map_symbol = type;
11079   return found;
11080 }
11081
11082 /* Given a bfd_mach_arm_XXX value, this function fills in the fields
11083    of the supplied arm_feature_set structure with bitmasks indicating
11084    the supported base architectures and coprocessor extensions.
11085
11086    FIXME: This could more efficiently implemented as a constant array,
11087    although it would also be less robust.  */
11088
11089 static void
11090 select_arm_features (unsigned long mach,
11091                      arm_feature_set * features)
11092 {
11093   arm_feature_set arch_fset;
11094   const arm_feature_set fpu_any = FPU_ANY;
11095
11096 #undef ARM_SET_FEATURES
11097 #define ARM_SET_FEATURES(FSET) \
11098   {                                                     \
11099     const arm_feature_set fset = FSET;                  \
11100     arch_fset = fset;                                   \
11101   }
11102
11103   /* When several architecture versions share the same bfd_mach_arm_XXX value
11104      the most featureful is chosen.  */
11105   switch (mach)
11106     {
11107     case bfd_mach_arm_2:         ARM_SET_FEATURES (ARM_ARCH_V2); break;
11108     case bfd_mach_arm_2a:        ARM_SET_FEATURES (ARM_ARCH_V2S); break;
11109     case bfd_mach_arm_3:         ARM_SET_FEATURES (ARM_ARCH_V3); break;
11110     case bfd_mach_arm_3M:        ARM_SET_FEATURES (ARM_ARCH_V3M); break;
11111     case bfd_mach_arm_4:         ARM_SET_FEATURES (ARM_ARCH_V4); break;
11112     case bfd_mach_arm_4T:        ARM_SET_FEATURES (ARM_ARCH_V4T); break;
11113     case bfd_mach_arm_5:         ARM_SET_FEATURES (ARM_ARCH_V5); break;
11114     case bfd_mach_arm_5T:        ARM_SET_FEATURES (ARM_ARCH_V5T); break;
11115     case bfd_mach_arm_5TE:       ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
11116     case bfd_mach_arm_XScale:    ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
11117     case bfd_mach_arm_ep9312:
11118         ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T,
11119                                            ARM_CEXT_MAVERICK | FPU_MAVERICK));
11120        break;
11121     case bfd_mach_arm_iWMMXt:    ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
11122     case bfd_mach_arm_iWMMXt2:   ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
11123     case bfd_mach_arm_5TEJ:      ARM_SET_FEATURES (ARM_ARCH_V5TEJ); break;
11124     case bfd_mach_arm_6:         ARM_SET_FEATURES (ARM_ARCH_V6); break;
11125     case bfd_mach_arm_6KZ:       ARM_SET_FEATURES (ARM_ARCH_V6KZ); break;
11126     case bfd_mach_arm_6T2:       ARM_SET_FEATURES (ARM_ARCH_V6KZT2); break;
11127     case bfd_mach_arm_6K:        ARM_SET_FEATURES (ARM_ARCH_V6K); break;
11128     case bfd_mach_arm_7:         ARM_SET_FEATURES (ARM_ARCH_V7VE); break;
11129     case bfd_mach_arm_6M:        ARM_SET_FEATURES (ARM_ARCH_V6M); break;
11130     case bfd_mach_arm_6SM:       ARM_SET_FEATURES (ARM_ARCH_V6SM); break;
11131     case bfd_mach_arm_7EM:       ARM_SET_FEATURES (ARM_ARCH_V7EM); break;
11132     case bfd_mach_arm_8:
11133         {
11134           /* Add bits for extensions that Armv8.5-A recognizes.  */
11135           arm_feature_set armv8_5_ext_fset
11136             = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST);
11137           ARM_SET_FEATURES (ARM_ARCH_V8_5A);
11138           ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, armv8_5_ext_fset);
11139           break;
11140         }
11141     case bfd_mach_arm_8R:        ARM_SET_FEATURES (ARM_ARCH_V8R); break;
11142     case bfd_mach_arm_8M_BASE:   ARM_SET_FEATURES (ARM_ARCH_V8M_BASE); break;
11143     case bfd_mach_arm_8M_MAIN:   ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN); break;
11144     case bfd_mach_arm_8_1M_MAIN:
11145       ARM_SET_FEATURES (ARM_ARCH_V8_1M_MAIN);
11146       force_thumb = 1;
11147       break;
11148       /* If the machine type is unknown allow all architecture types and all
11149          extensions.  */
11150     case bfd_mach_arm_unknown:   ARM_SET_FEATURES (ARM_FEATURE_ALL); break;
11151     default:
11152       abort ();
11153     }
11154 #undef ARM_SET_FEATURES
11155
11156   /* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch
11157      and thus on bfd_mach_arm_XXX value.  Therefore for a given
11158      bfd_mach_arm_XXX value all coprocessor feature bits should be allowed.  */
11159   ARM_MERGE_FEATURE_SETS (*features, arch_fset, fpu_any);
11160 }
11161
11162
11163 /* NOTE: There are no checks in these routines that
11164    the relevant number of data bytes exist.  */
11165
11166 static int
11167 print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
11168 {
11169   unsigned char b[4];
11170   long          given;
11171   int           status;
11172   int           is_thumb = FALSE;
11173   int           is_data = FALSE;
11174   int           little_code;
11175   unsigned int  size = 4;
11176   void          (*printer) (bfd_vma, struct disassemble_info *, long);
11177   bfd_boolean   found = FALSE;
11178   struct arm_private_data *private_data;
11179
11180   if (info->disassembler_options)
11181     {
11182       parse_arm_disassembler_options (info->disassembler_options);
11183
11184       /* To avoid repeated parsing of these options, we remove them here.  */
11185       info->disassembler_options = NULL;
11186     }
11187
11188   /* PR 10288: Control which instructions will be disassembled.  */
11189   if (info->private_data == NULL)
11190     {
11191       static struct arm_private_data private;
11192
11193       if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
11194         /* If the user did not use the -m command line switch then default to
11195            disassembling all types of ARM instruction.
11196
11197            The info->mach value has to be ignored as this will be based on
11198            the default archictecture for the target and/or hints in the notes
11199            section, but it will never be greater than the current largest arm
11200            machine value (iWMMXt2), which is only equivalent to the V5TE
11201            architecture.  ARM architectures have advanced beyond the machine
11202            value encoding, and these newer architectures would be ignored if
11203            the machine value was used.
11204
11205            Ie the -m switch is used to restrict which instructions will be
11206            disassembled.  If it is necessary to use the -m switch to tell
11207            objdump that an ARM binary is being disassembled, eg because the
11208            input is a raw binary file, but it is also desired to disassemble
11209            all ARM instructions then use "-marm".  This will select the
11210            "unknown" arm architecture which is compatible with any ARM
11211            instruction.  */
11212           info->mach = bfd_mach_arm_unknown;
11213
11214       /* Compute the architecture bitmask from the machine number.
11215          Note: This assumes that the machine number will not change
11216          during disassembly....  */
11217       select_arm_features (info->mach, & private.features);
11218
11219       private.last_mapping_sym = -1;
11220       private.last_mapping_addr = 0;
11221       private.last_stop_offset = 0;
11222
11223       info->private_data = & private;
11224     }
11225
11226   private_data = info->private_data;
11227
11228   /* Decide if our code is going to be little-endian, despite what the
11229      function argument might say.  */
11230   little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
11231
11232   /* For ELF, consult the symbol table to determine what kind of code
11233      or data we have.  */
11234   if (info->symtab_size != 0
11235       && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
11236     {
11237       bfd_vma addr;
11238       int n;
11239       int last_sym = -1;
11240       enum map_type type = MAP_ARM;
11241
11242       found = mapping_symbol_for_insn (pc, info, &type);
11243       last_sym = private_data->last_mapping_sym;
11244
11245       is_thumb = (private_data->last_type == MAP_THUMB);
11246       is_data = (private_data->last_type == MAP_DATA);
11247
11248       /* Look a little bit ahead to see if we should print out
11249          two or four bytes of data.  If there's a symbol,
11250          mapping or otherwise, after two bytes then don't
11251          print more.  */
11252       if (is_data)
11253         {
11254           size = 4 - (pc & 3);
11255           for (n = last_sym + 1; n < info->symtab_size; n++)
11256             {
11257               addr = bfd_asymbol_value (info->symtab[n]);
11258               if (addr > pc
11259                   && (info->section == NULL
11260                       || info->section == info->symtab[n]->section))
11261                 {
11262                   if (addr - pc < size)
11263                     size = addr - pc;
11264                   break;
11265                 }
11266             }
11267           /* If the next symbol is after three bytes, we need to
11268              print only part of the data, so that we can use either
11269              .byte or .short.  */
11270           if (size == 3)
11271             size = (pc & 1) ? 1 : 2;
11272         }
11273     }
11274
11275   if (info->symbols != NULL)
11276     {
11277       if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
11278         {
11279           coff_symbol_type * cs;
11280
11281           cs = coffsymbol (*info->symbols);
11282           is_thumb = (   cs->native->u.syment.n_sclass == C_THUMBEXT
11283                       || cs->native->u.syment.n_sclass == C_THUMBSTAT
11284                       || cs->native->u.syment.n_sclass == C_THUMBLABEL
11285                       || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
11286                       || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
11287         }
11288       else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
11289                && !found)
11290         {
11291           /* If no mapping symbol has been found then fall back to the type
11292              of the function symbol.  */
11293           elf_symbol_type *  es;
11294           unsigned int       type;
11295
11296           es = *(elf_symbol_type **)(info->symbols);
11297           type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
11298
11299           is_thumb =
11300             ((ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
11301               == ST_BRANCH_TO_THUMB) || type == STT_ARM_16BIT);
11302         }
11303       else if (bfd_asymbol_flavour (*info->symbols)
11304                == bfd_target_mach_o_flavour)
11305         {
11306           bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols;
11307
11308           is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF);
11309         }
11310     }
11311
11312   if (force_thumb)
11313     is_thumb = TRUE;
11314
11315   if (is_data)
11316     info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
11317   else
11318     info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
11319
11320   info->bytes_per_line = 4;
11321
11322   /* PR 10263: Disassemble data if requested to do so by the user.  */
11323   if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
11324     {
11325       int i;
11326
11327       /* Size was already set above.  */
11328       info->bytes_per_chunk = size;
11329       printer = print_insn_data;
11330
11331       status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
11332       given = 0;
11333       if (little)
11334         for (i = size - 1; i >= 0; i--)
11335           given = b[i] | (given << 8);
11336       else
11337         for (i = 0; i < (int) size; i++)
11338           given = b[i] | (given << 8);
11339     }
11340   else if (!is_thumb)
11341     {
11342       /* In ARM mode endianness is a straightforward issue: the instruction
11343          is four bytes long and is either ordered 0123 or 3210.  */
11344       printer = print_insn_arm;
11345       info->bytes_per_chunk = 4;
11346       size = 4;
11347
11348       status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
11349       if (little_code)
11350         given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
11351       else
11352         given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24);
11353     }
11354   else
11355     {
11356       /* In Thumb mode we have the additional wrinkle of two
11357          instruction lengths.  Fortunately, the bits that determine
11358          the length of the current instruction are always to be found
11359          in the first two bytes.  */
11360       printer = print_insn_thumb16;
11361       info->bytes_per_chunk = 2;
11362       size = 2;
11363
11364       status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
11365       if (little_code)
11366         given = (b[0]) | (b[1] << 8);
11367       else
11368         given = (b[1]) | (b[0] << 8);
11369
11370       if (!status)
11371         {
11372           /* These bit patterns signal a four-byte Thumb
11373              instruction.  */
11374           if ((given & 0xF800) == 0xF800
11375               || (given & 0xF800) == 0xF000
11376               || (given & 0xF800) == 0xE800)
11377             {
11378               status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
11379               if (little_code)
11380                 given = (b[0]) | (b[1] << 8) | (given << 16);
11381               else
11382                 given = (b[1]) | (b[0] << 8) | (given << 16);
11383
11384               printer = print_insn_thumb32;
11385               size = 4;
11386             }
11387         }
11388
11389       if (ifthen_address != pc)
11390         find_ifthen_state (pc, info, little_code);
11391
11392       if (ifthen_state)
11393         {
11394           if ((ifthen_state & 0xf) == 0x8)
11395             ifthen_next_state = 0;
11396           else
11397             ifthen_next_state = (ifthen_state & 0xe0)
11398                                 | ((ifthen_state & 0xf) << 1);
11399         }
11400     }
11401
11402   if (status)
11403     {
11404       info->memory_error_func (status, pc, info);
11405       return -1;
11406     }
11407   if (info->flags & INSN_HAS_RELOC)
11408     /* If the instruction has a reloc associated with it, then
11409        the offset field in the instruction will actually be the
11410        addend for the reloc.  (We are using REL type relocs).
11411        In such cases, we can ignore the pc when computing
11412        addresses, since the addend is not currently pc-relative.  */
11413     pc = 0;
11414
11415   printer (pc, info, given);
11416
11417   if (is_thumb)
11418     {
11419       ifthen_state = ifthen_next_state;
11420       ifthen_address += size;
11421     }
11422   return size;
11423 }
11424
11425 int
11426 print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
11427 {
11428   /* Detect BE8-ness and record it in the disassembler info.  */
11429   if (info->flavour == bfd_target_elf_flavour
11430       && info->section != NULL
11431       && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
11432     info->endian_code = BFD_ENDIAN_LITTLE;
11433
11434   return print_insn (pc, info, FALSE);
11435 }
11436
11437 int
11438 print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
11439 {
11440   return print_insn (pc, info, TRUE);
11441 }
11442
11443 const disasm_options_and_args_t *
11444 disassembler_options_arm (void)
11445 {
11446   static disasm_options_and_args_t *opts_and_args;
11447
11448   if (opts_and_args == NULL)
11449     {
11450       disasm_options_t *opts;
11451       unsigned int i;
11452
11453       opts_and_args = XNEW (disasm_options_and_args_t);
11454       opts_and_args->args = NULL;
11455
11456       opts = &opts_and_args->options;
11457       opts->name = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
11458       opts->description = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
11459       opts->arg = NULL;
11460       for (i = 0; i < NUM_ARM_OPTIONS; i++)
11461         {
11462           opts->name[i] = regnames[i].name;
11463           if (regnames[i].description != NULL)
11464             opts->description[i] = _(regnames[i].description);
11465           else
11466             opts->description[i] = NULL;
11467         }
11468       /* The array we return must be NULL terminated.  */
11469       opts->name[i] = NULL;
11470       opts->description[i] = NULL;
11471     }
11472
11473   return opts_and_args;
11474 }
11475
11476 void
11477 print_arm_disassembler_options (FILE *stream)
11478 {
11479   unsigned int i, max_len = 0;
11480   fprintf (stream, _("\n\
11481 The following ARM specific disassembler options are supported for use with\n\
11482 the -M switch:\n"));
11483
11484   for (i = 0; i < NUM_ARM_OPTIONS; i++)
11485     {
11486       unsigned int len = strlen (regnames[i].name);
11487       if (max_len < len)
11488         max_len = len;
11489     }
11490
11491   for (i = 0, max_len++; i < NUM_ARM_OPTIONS; i++)
11492     fprintf (stream, "  %s%*c %s\n",
11493              regnames[i].name,
11494              (int)(max_len - strlen (regnames[i].name)), ' ',
11495              _(regnames[i].description));
11496 }