3 { "vmovupX", { XM
, EXEvexXNoBcst
}, PREFIX_OPCODE
},
4 { VEX_W_TABLE (EVEX_W_0F10_P_1
) },
5 { "vmovupX", { XM
, EXEvexXNoBcst
}, PREFIX_OPCODE
},
6 { VEX_W_TABLE (EVEX_W_0F10_P_3
) },
10 { "vmovupX", { EXxS
, XM
}, PREFIX_OPCODE
},
11 { VEX_W_TABLE (EVEX_W_0F11_P_1
) },
12 { "vmovupX", { EXxS
, XM
}, PREFIX_OPCODE
},
13 { VEX_W_TABLE (EVEX_W_0F11_P_3
) },
15 /* PREFIX_EVEX_0F12 */
17 { MOD_TABLE (MOD_EVEX_0F12_PREFIX_0
) },
18 { VEX_W_TABLE (EVEX_W_0F12_P_1
) },
19 { MOD_TABLE (MOD_EVEX_0F12_PREFIX_2
) },
20 { VEX_W_TABLE (EVEX_W_0F12_P_3
) },
22 /* PREFIX_EVEX_0F16 */
24 { MOD_TABLE (MOD_EVEX_0F16_PREFIX_0
) },
25 { VEX_W_TABLE (EVEX_W_0F16_P_1
) },
26 { MOD_TABLE (MOD_EVEX_0F16_PREFIX_2
) },
28 /* PREFIX_EVEX_0F2A */
31 { "vcvtsi2ss{%LQ|}", { XMScalar
, VexScalar
, EXxEVexR
, Edq
}, 0 },
33 { "vcvtsi2sd{%LQ|}", { XMScalar
, VexScalar
, EXxEVexR64
, Edq
}, 0 },
35 /* PREFIX_EVEX_0F51 */
37 { "vsqrtpX", { XM
, EXx
, EXxEVexR
}, PREFIX_OPCODE
},
38 { VEX_W_TABLE (EVEX_W_0F51_P_1
) },
39 { "vsqrtpX", { XM
, EXx
, EXxEVexR
}, PREFIX_OPCODE
},
40 { VEX_W_TABLE (EVEX_W_0F51_P_3
) },
42 /* PREFIX_EVEX_0F58 */
44 { "vaddpX", { XM
, Vex
, EXx
, EXxEVexR
}, PREFIX_OPCODE
},
45 { VEX_W_TABLE (EVEX_W_0F58_P_1
) },
46 { "vaddpX", { XM
, Vex
, EXx
, EXxEVexR
}, PREFIX_OPCODE
},
47 { VEX_W_TABLE (EVEX_W_0F58_P_3
) },
49 /* PREFIX_EVEX_0F59 */
51 { "vmulpX", { XM
, Vex
, EXx
, EXxEVexR
}, PREFIX_OPCODE
},
52 { VEX_W_TABLE (EVEX_W_0F59_P_1
) },
53 { "vmulpX", { XM
, Vex
, EXx
, EXxEVexR
}, PREFIX_OPCODE
},
54 { VEX_W_TABLE (EVEX_W_0F59_P_3
) },
56 /* PREFIX_EVEX_0F5A */
58 { VEX_W_TABLE (EVEX_W_0F5A_P_0
) },
59 { VEX_W_TABLE (EVEX_W_0F5A_P_1
) },
60 { VEX_W_TABLE (EVEX_W_0F5A_P_2
) },
61 { VEX_W_TABLE (EVEX_W_0F5A_P_3
) },
63 /* PREFIX_EVEX_0F5B */
65 { VEX_W_TABLE (EVEX_W_0F5B_P_0
) },
66 { VEX_W_TABLE (EVEX_W_0F5B_P_1
) },
67 { VEX_W_TABLE (EVEX_W_0F5B_P_2
) },
69 /* PREFIX_EVEX_0F5C */
71 { "vsubpX", { XM
, Vex
, EXx
, EXxEVexR
}, PREFIX_OPCODE
},
72 { VEX_W_TABLE (EVEX_W_0F5C_P_1
) },
73 { "vsubpX", { XM
, Vex
, EXx
, EXxEVexR
}, PREFIX_OPCODE
},
74 { VEX_W_TABLE (EVEX_W_0F5C_P_3
) },
76 /* PREFIX_EVEX_0F5D */
78 { "vminpX", { XM
, Vex
, EXx
, EXxEVexS
}, PREFIX_OPCODE
},
79 { VEX_W_TABLE (EVEX_W_0F5D_P_1
) },
80 { "vminpX", { XM
, Vex
, EXx
, EXxEVexS
}, PREFIX_OPCODE
},
81 { VEX_W_TABLE (EVEX_W_0F5D_P_3
) },
83 /* PREFIX_EVEX_0F5E */
85 { "vdivpX", { XM
, Vex
, EXx
, EXxEVexR
}, PREFIX_OPCODE
},
86 { VEX_W_TABLE (EVEX_W_0F5E_P_1
) },
87 { "vdivpX", { XM
, Vex
, EXx
, EXxEVexR
}, PREFIX_OPCODE
},
88 { VEX_W_TABLE (EVEX_W_0F5E_P_3
) },
90 /* PREFIX_EVEX_0F5F */
92 { "vmaxpX", { XM
, Vex
, EXx
, EXxEVexS
}, PREFIX_OPCODE
},
93 { VEX_W_TABLE (EVEX_W_0F5F_P_1
) },
94 { "vmaxpX", { XM
, Vex
, EXx
, EXxEVexS
}, PREFIX_OPCODE
},
95 { VEX_W_TABLE (EVEX_W_0F5F_P_3
) },
97 /* PREFIX_EVEX_0F6F */
100 { VEX_W_TABLE (EVEX_W_0F6F_P_1
) },
101 { VEX_W_TABLE (EVEX_W_0F6F_P_2
) },
102 { VEX_W_TABLE (EVEX_W_0F6F_P_3
) },
104 /* PREFIX_EVEX_0F70 */
107 { "vpshufhw", { XM
, EXx
, Ib
}, 0 },
108 { VEX_W_TABLE (EVEX_W_0F70_P_2
) },
109 { "vpshuflw", { XM
, EXx
, Ib
}, 0 },
111 /* PREFIX_EVEX_0F78 */
113 { VEX_W_TABLE (EVEX_W_0F78_P_0
) },
114 { "vcvttss2usi", { Gdq
, EXd
, EXxEVexS
}, 0 },
115 { VEX_W_TABLE (EVEX_W_0F78_P_2
) },
116 { "vcvttsd2usi", { Gdq
, EXq
, EXxEVexS
}, 0 },
118 /* PREFIX_EVEX_0F79 */
120 { VEX_W_TABLE (EVEX_W_0F79_P_0
) },
121 { "vcvtss2usi", { Gdq
, EXd
, EXxEVexR
}, 0 },
122 { VEX_W_TABLE (EVEX_W_0F79_P_2
) },
123 { "vcvtsd2usi", { Gdq
, EXq
, EXxEVexR
}, 0 },
125 /* PREFIX_EVEX_0F7A */
128 { VEX_W_TABLE (EVEX_W_0F7A_P_1
) },
129 { VEX_W_TABLE (EVEX_W_0F7A_P_2
) },
130 { VEX_W_TABLE (EVEX_W_0F7A_P_3
) },
132 /* PREFIX_EVEX_0F7B */
135 { "vcvtusi2ss{%LQ|}", { XMScalar
, VexScalar
, EXxEVexR
, Edq
}, 0 },
136 { VEX_W_TABLE (EVEX_W_0F7B_P_2
) },
137 { "vcvtusi2sd{%LQ|}", { XMScalar
, VexScalar
, EXxEVexR64
, Edq
}, 0 },
139 /* PREFIX_EVEX_0F7E */
142 { VEX_W_TABLE (EVEX_W_0F7E_P_1
) },
143 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2
) },
145 /* PREFIX_EVEX_0F7F */
148 { VEX_W_TABLE (EVEX_W_0F7F_P_1
) },
149 { VEX_W_TABLE (EVEX_W_0F7F_P_2
) },
150 { VEX_W_TABLE (EVEX_W_0F7F_P_3
) },
152 /* PREFIX_EVEX_0FC2 */
154 { "vcmppX", { MaskG
, Vex
, EXx
, EXxEVexS
, CMP
}, PREFIX_OPCODE
},
155 { VEX_W_TABLE (EVEX_W_0FC2_P_1
) },
156 { "vcmppX", { MaskG
, Vex
, EXx
, EXxEVexS
, CMP
}, PREFIX_OPCODE
},
157 { VEX_W_TABLE (EVEX_W_0FC2_P_3
) },
159 /* PREFIX_EVEX_0FE6 */
162 { VEX_W_TABLE (EVEX_W_0FE6_P_1
) },
163 { VEX_W_TABLE (EVEX_W_0FE6_P_2
) },
164 { VEX_W_TABLE (EVEX_W_0FE6_P_3
) },
166 /* PREFIX_EVEX_0F3810 */
169 { VEX_W_TABLE (EVEX_W_0F3810_P_1
) },
170 { VEX_W_TABLE (EVEX_W_0F3810_P_2
) },
172 /* PREFIX_EVEX_0F3811 */
175 { VEX_W_TABLE (EVEX_W_0F3811_P_1
) },
176 { VEX_W_TABLE (EVEX_W_0F3811_P_2
) },
178 /* PREFIX_EVEX_0F3812 */
181 { VEX_W_TABLE (EVEX_W_0F3812_P_1
) },
182 { VEX_W_TABLE (EVEX_W_0F3812_P_2
) },
184 /* PREFIX_EVEX_0F3813 */
187 { VEX_W_TABLE (EVEX_W_0F3813_P_1
) },
188 { VEX_W_TABLE (EVEX_W_0F3813_P_2
) },
190 /* PREFIX_EVEX_0F3814 */
193 { VEX_W_TABLE (EVEX_W_0F3814_P_1
) },
194 { "vprorv%DQ", { XM
, Vex
, EXx
}, 0 },
196 /* PREFIX_EVEX_0F3815 */
199 { VEX_W_TABLE (EVEX_W_0F3815_P_1
) },
200 { "vprolv%DQ", { XM
, Vex
, EXx
}, 0 },
202 /* PREFIX_EVEX_0F3820 */
205 { VEX_W_TABLE (EVEX_W_0F3820_P_1
) },
206 { "vpmovsxbw", { XM
, EXxmmq
}, 0 },
208 /* PREFIX_EVEX_0F3821 */
211 { VEX_W_TABLE (EVEX_W_0F3821_P_1
) },
212 { "vpmovsxbd", { XM
, EXxmmqd
}, 0 },
214 /* PREFIX_EVEX_0F3822 */
217 { VEX_W_TABLE (EVEX_W_0F3822_P_1
) },
218 { "vpmovsxbq", { XM
, EXxmmdw
}, 0 },
220 /* PREFIX_EVEX_0F3823 */
223 { VEX_W_TABLE (EVEX_W_0F3823_P_1
) },
224 { "vpmovsxwd", { XM
, EXxmmq
}, 0 },
226 /* PREFIX_EVEX_0F3824 */
229 { VEX_W_TABLE (EVEX_W_0F3824_P_1
) },
230 { "vpmovsxwq", { XM
, EXxmmqd
}, 0 },
232 /* PREFIX_EVEX_0F3825 */
235 { VEX_W_TABLE (EVEX_W_0F3825_P_1
) },
236 { VEX_W_TABLE (EVEX_W_0F3825_P_2
) },
238 /* PREFIX_EVEX_0F3826 */
241 { "vptestnm%BW", { MaskG
, Vex
, EXx
}, 0 },
242 { "vptestm%BW", { MaskG
, Vex
, EXx
}, 0 },
244 /* PREFIX_EVEX_0F3827 */
247 { "vptestnm%DQ", { MaskG
, Vex
, EXx
}, 0 },
248 { "vptestm%DQ", { MaskG
, Vex
, EXx
}, 0 },
250 /* PREFIX_EVEX_0F3828 */
253 { MOD_TABLE (MOD_EVEX_0F3828_P_1
) },
254 { VEX_W_TABLE (EVEX_W_0F3828_P_2
) },
256 /* PREFIX_EVEX_0F3829 */
259 { "vpmov%BW2m", { MaskG
, EXx
}, 0 },
260 { VEX_W_TABLE (EVEX_W_0F3829_P_2
) },
262 /* PREFIX_EVEX_0F382A */
265 { VEX_W_TABLE (EVEX_W_0F382A_P_1
) },
266 { VEX_W_TABLE (EVEX_W_0F382A_P_2
) },
268 /* PREFIX_EVEX_0F3830 */
271 { VEX_W_TABLE (EVEX_W_0F3830_P_1
) },
272 { "vpmovzxbw", { XM
, EXxmmq
}, 0 },
274 /* PREFIX_EVEX_0F3831 */
277 { VEX_W_TABLE (EVEX_W_0F3831_P_1
) },
278 { "vpmovzxbd", { XM
, EXxmmqd
}, 0 },
280 /* PREFIX_EVEX_0F3832 */
283 { VEX_W_TABLE (EVEX_W_0F3832_P_1
) },
284 { "vpmovzxbq", { XM
, EXxmmdw
}, 0 },
286 /* PREFIX_EVEX_0F3833 */
289 { VEX_W_TABLE (EVEX_W_0F3833_P_1
) },
290 { "vpmovzxwd", { XM
, EXxmmq
}, 0 },
292 /* PREFIX_EVEX_0F3834 */
295 { VEX_W_TABLE (EVEX_W_0F3834_P_1
) },
296 { "vpmovzxwq", { XM
, EXxmmqd
}, 0 },
298 /* PREFIX_EVEX_0F3835 */
301 { VEX_W_TABLE (EVEX_W_0F3835_P_1
) },
302 { VEX_W_TABLE (EVEX_W_0F3835_P_2
) },
304 /* PREFIX_EVEX_0F3838 */
307 { MOD_TABLE (MOD_EVEX_0F3838_P_1
) },
308 { "vpminsb", { XM
, Vex
, EXx
}, 0 },
310 /* PREFIX_EVEX_0F3839 */
313 { "vpmov%DQ2m", { MaskG
, EXx
}, 0 },
314 { "vpmins%DQ", { XM
, Vex
, EXx
}, 0 },
316 /* PREFIX_EVEX_0F383A */
319 { VEX_W_TABLE (EVEX_W_0F383A_P_1
) },
320 { "vpminuw", { XM
, Vex
, EXx
}, 0 },
322 /* PREFIX_EVEX_0F3852 */
325 { VEX_W_TABLE (EVEX_W_0F3852_P_1
) },
326 { "vpdpwssd", { XM
, Vex
, EXx
}, 0 },
327 { "vp4dpwssd", { XM
, Vex
, EXxmm
}, 0 },
329 /* PREFIX_EVEX_0F3853 */
333 { "vpdpwssds", { XM
, Vex
, EXx
}, 0 },
334 { "vp4dpwssds", { XM
, Vex
, EXxmm
}, 0 },
336 /* PREFIX_EVEX_0F3868 */
341 { "vp2intersect%DQ", { MaskG
, Vex
, EXx
, EXxEVexS
}, 0 },
343 /* PREFIX_EVEX_0F3872 */
346 { VEX_W_TABLE (EVEX_W_0F3872_P_1
) },
347 { VEX_W_TABLE (EVEX_W_0F3872_P_2
) },
348 { VEX_W_TABLE (EVEX_W_0F3872_P_3
) },
350 /* PREFIX_EVEX_0F389A */
354 { "vfmsub132p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
355 { "v4fmaddps", { XM
, Vex
, Mxmm
}, 0 },
357 /* PREFIX_EVEX_0F389B */
361 { "vfmsub132s%XW", { XMScalar
, VexScalar
, EXdq
, EXxEVexR
}, 0 },
362 { "v4fmaddss", { XMScalar
, VexScalar
, Mxmm
}, 0 },
364 /* PREFIX_EVEX_0F38AA */
368 { "vfmsub213p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
369 { "v4fnmaddps", { XM
, Vex
, Mxmm
}, 0 },
371 /* PREFIX_EVEX_0F38AB */
375 { "vfmsub213s%XW", { XMScalar
, VexScalar
, EXdq
, EXxEVexR
}, 0 },
376 { "v4fnmaddss", { XMScalar
, VexScalar
, Mxmm
}, 0 },
378 /* PREFIX_EVEX_0F3A08_W_0 */
380 { "vrndscaleph", { XM
, EXxh
, EXxEVexS
, Ib
}, 0 },
382 { "vrndscaleps", { XM
, EXx
, EXxEVexS
, Ib
}, 0 },
384 /* PREFIX_EVEX_0F3A0A_W_0 */
386 { "vrndscalesh", { XMScalar
, VexScalar
, EXw
, EXxEVexS
, Ib
}, 0 },
388 { "vrndscaless", { XMScalar
, VexScalar
, EXd
, EXxEVexS
, Ib
}, 0 },
390 /* PREFIX_EVEX_0F3A26 */
392 { "vgetmantp%XH", { XM
, EXxh
, EXxEVexS
, Ib
}, 0 },
394 { "vgetmantp%XW", { XM
, EXx
, EXxEVexS
, Ib
}, 0 },
396 /* PREFIX_EVEX_0F3A27 */
398 { "vgetmants%XH", { XMScalar
, VexScalar
, EXw
, EXxEVexS
, Ib
}, 0 },
400 { "vgetmants%XW", { XMScalar
, VexScalar
, EXdq
, EXxEVexS
, Ib
}, 0 },
402 /* PREFIX_EVEX_0F3A56 */
404 { "vreducep%XH", { XM
, EXxh
, EXxEVexS
, Ib
}, 0 },
406 { "vreducep%XW", { XM
, EXx
, EXxEVexS
, Ib
}, 0 },
408 /* PREFIX_EVEX_0F3A57 */
410 { "vreduces%XH", { XMScalar
, VexScalar
, EXw
, EXxEVexS
, Ib
}, 0 },
412 { "vreduces%XW", { XMScalar
, VexScalar
, EXdq
, EXxEVexS
, Ib
}, 0 },
414 /* PREFIX_EVEX_0F3A66 */
416 { "vfpclassp%XH%XZ", { MaskG
, EXxh
, Ib
}, 0 },
418 { "vfpclassp%XW%XZ", { MaskG
, EXx
, Ib
}, 0 },
420 /* PREFIX_EVEX_0F3A67 */
422 { "vfpclasss%XH", { MaskG
, EXw
, Ib
}, 0 },
424 { "vfpclasss%XW", { MaskG
, EXdq
, Ib
}, 0 },
426 /* PREFIX_EVEX_0F3AC2 */
428 { "vcmpp%XH", { MaskG
, Vex
, EXxh
, EXxEVexS
, CMP
}, 0 },
429 { "vcmps%XH", { MaskG
, VexScalar
, EXw
, EXxEVexS
, CMP
}, 0 },
431 /* PREFIX_EVEX_MAP5_10 */
434 { "vmovs%XH", { XMScalar
, VexScalarR
, EXw
}, 0 },
436 /* PREFIX_EVEX_MAP5_11 */
439 { "vmovs%XH", { EXwS
, VexScalarR
, XMScalar
}, 0 },
441 /* PREFIX_EVEX_MAP5_1D */
443 { "vcvtss2s%XH", { XMM
, VexScalar
, EXd
, EXxEVexR
}, 0 },
445 { "vcvtps2p%XHx%XY", { XMxmmq
, EXx
, EXxEVexR
}, 0 },
447 /* PREFIX_EVEX_MAP5_2A */
450 { "vcvtsi2sh{%LQ|}", { XMScalar
, VexScalar
, EXxEVexR
, Edq
}, 0 },
452 /* PREFIX_EVEX_MAP5_2C */
455 { "vcvttsh2si", { Gdq
, EXw
, EXxEVexS
}, 0 },
457 /* PREFIX_EVEX_MAP5_2D */
460 { "vcvtsh2si", { Gdq
, EXw
, EXxEVexR
}, 0 },
462 /* PREFIX_EVEX_MAP5_2E */
464 { "vucomis%XH", { XMScalar
, EXw
, EXxEVexS
}, 0 },
466 /* PREFIX_EVEX_MAP5_2F */
468 { "vcomis%XH", { XMScalar
, EXw
, EXxEVexS
}, 0 },
470 /* PREFIX_EVEX_MAP5_51 */
472 { "vsqrtp%XH", { XM
, EXxh
, EXxEVexR
}, 0 },
473 { "vsqrts%XH", { XMM
, VexScalar
, EXw
, EXxEVexR
}, 0 },
475 /* PREFIX_EVEX_MAP5_58 */
477 { "vaddp%XH", { XM
, Vex
, EXxh
, EXxEVexR
}, 0 },
478 { "vadds%XH", { XMM
, VexScalar
, EXw
, EXxEVexR
}, 0 },
480 /* PREFIX_EVEX_MAP5_59 */
482 { "vmulp%XH", { XM
, Vex
, EXxh
, EXxEVexR
}, 0 },
483 { "vmuls%XH", { XMM
, VexScalar
, EXw
, EXxEVexR
}, 0 },
485 /* PREFIX_EVEX_MAP5_5A_W_0 */
487 { "vcvtph2pd", { XM
, EXxmmqdh
, EXxEVexS
}, 0 },
488 { "vcvtsh2sd", { XMM
, VexScalar
, EXw
, EXxEVexS
}, 0 },
490 /* PREFIX_EVEX_MAP5_5A_W_1 */
494 { "vcvtpd2ph%XZ", { XMM
, EXx
, EXxEVexR
}, 0 },
495 { "vcvtsd2sh", { XMM
, VexScalar
, EXq
, EXxEVexR
}, 0 },
497 /* PREFIX_EVEX_MAP5_5B_W_0 */
499 { "vcvtdq2ph%XY", { XMxmmq
, EXx
, EXxEVexR
}, 0 },
500 { "vcvttph2dq", { XM
, EXxmmqh
, EXxEVexS
}, 0 },
501 { "vcvtph2dq", { XM
, EXxmmqh
, EXxEVexR
}, 0 },
503 /* PREFIX_EVEX_MAP5_5B_W_1 */
505 { "vcvtqq2ph%XZ", { XMM
, EXx
, EXxEVexR
}, 0 },
507 /* PREFIX_EVEX_MAP5_5C */
509 { "vsubp%XH", { XM
, Vex
, EXxh
, EXxEVexR
}, 0 },
510 { "vsubs%XH", { XMM
, VexScalar
, EXw
, EXxEVexR
}, 0 },
512 /* PREFIX_EVEX_MAP5_5D */
514 { "vminp%XH", { XM
, Vex
, EXxh
, EXxEVexS
}, 0 },
515 { "vmins%XH", { XMM
, VexScalar
, EXw
, EXxEVexS
}, 0 },
517 /* PREFIX_EVEX_MAP5_5E */
519 { "vdivp%XH", { XM
, Vex
, EXxh
, EXxEVexR
}, 0 },
520 { "vdivs%XH", { XMM
, VexScalar
, EXw
, EXxEVexR
}, 0 },
522 /* PREFIX_EVEX_MAP5_5F */
524 { "vmaxp%XH", { XM
, Vex
, EXxh
, EXxEVexS
}, 0 },
525 { "vmaxs%XH", { XMM
, VexScalar
, EXw
, EXxEVexS
}, 0 },
527 /* PREFIX_EVEX_MAP5_78 */
529 { VEX_W_TABLE (EVEX_W_MAP5_78_P_0
) },
530 { "vcvttsh2usi", { Gdq
, EXw
, EXxEVexS
}, 0 },
531 { VEX_W_TABLE (EVEX_W_MAP5_78_P_2
) },
533 /* PREFIX_EVEX_MAP5_79 */
535 { VEX_W_TABLE (EVEX_W_MAP5_79_P_0
) },
536 { "vcvtsh2usi", { Gdq
, EXw
, EXxEVexR
}, 0 },
537 { VEX_W_TABLE (EVEX_W_MAP5_79_P_2
) },
539 /* PREFIX_EVEX_MAP5_7A */
543 { VEX_W_TABLE (EVEX_W_MAP5_7A_P_2
) },
544 { VEX_W_TABLE (EVEX_W_MAP5_7A_P_3
) },
546 /* PREFIX_EVEX_MAP5_7B */
549 { "vcvtusi2sh{%LQ|}", { XMScalar
, VexScalar
, EXxEVexR
, Edq
}, 0 },
550 { VEX_W_TABLE (EVEX_W_MAP5_7B_P_2
) },
552 /* PREFIX_EVEX_MAP5_7C */
554 { VEX_W_TABLE (EVEX_W_MAP5_7C_P_0
) },
556 { VEX_W_TABLE (EVEX_W_MAP5_7C_P_2
) },
558 /* PREFIX_EVEX_MAP5_7D_W_0 */
560 { "vcvtph2uw", { XM
, EXxh
, EXxEVexR
}, 0 },
561 { "vcvtw2ph", { XM
, EXxh
, EXxEVexR
}, 0 },
562 { "vcvtph2w", { XM
, EXxh
, EXxEVexR
}, 0 },
563 { "vcvtuw2ph", { XM
, EXxh
, EXxEVexR
}, 0 },
565 /* PREFIX_EVEX_MAP6_13 */
567 { VEX_W_TABLE (EVEX_W_MAP6_13_P_0
) },
569 { VEX_W_TABLE (EVEX_W_MAP6_13_P_2
) },
571 /* PREFIX_EVEX_MAP6_56 */
574 { "vfmaddcp%XH", { { DistinctDest_Fixup
, 0 }, Vex
, EXx
, EXxEVexR
}, 0 },
576 { "vfcmaddcp%XH", { { DistinctDest_Fixup
, 0 }, Vex
, EXx
, EXxEVexR
}, 0 },
578 /* PREFIX_EVEX_MAP6_57 */
581 { "vfmaddcs%XH", { { DistinctDest_Fixup
, xmm_mode
}, VexScalar
, EXd
, EXxEVexR
}, 0 },
583 { "vfcmaddcs%XH", { { DistinctDest_Fixup
, xmm_mode
}, VexScalar
, EXd
, EXxEVexR
}, 0 },
585 /* PREFIX_EVEX_MAP6_D6 */
588 { "vfmulcp%XH", { { DistinctDest_Fixup
, 0 }, Vex
, EXx
, EXxEVexR
}, 0 },
590 { "vfcmulcp%XH", { { DistinctDest_Fixup
, 0 }, Vex
, EXx
, EXxEVexR
}, 0 },
592 /* PREFIX_EVEX_MAP6_D7 */
595 { "vfmulcs%XH", { { DistinctDest_Fixup
, xmm_mode
}, VexScalar
, EXd
, EXxEVexR
}, 0 },
597 { "vfcmulcs%XH", { { DistinctDest_Fixup
, xmm_mode
}, VexScalar
, EXd
, EXxEVexR
}, 0 },