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* mips-opc.c (mips_builtin_opcodes): Set field `match' to 0 for
[binutils-gdb.git] / opcodes / i386-dis.c
1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
4
5 This file is part of the GNU opcodes library.
6
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
11
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
21
22
23 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 July 1988
25 modified by John Hassey (hassey@dg-rtp.dg.com)
26 x86-64 support added by Jan Hubicka (jh@suse.cz)
27 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28
29 /* The main tables describing the instructions is essentially a copy
30 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
31 Programmers Manual. Usually, there is a capital letter, followed
32 by a small letter. The capital letter tell the addressing mode,
33 and the small letter tells about the operand size. Refer to
34 the Intel manual for details. */
35
36 #include "sysdep.h"
37 #include "dis-asm.h"
38 #include "opintl.h"
39 #include "opcode/i386.h"
40 #include "libiberty.h"
41
42 #include <setjmp.h>
43
44 static int fetch_data (struct disassemble_info *, bfd_byte *);
45 static void ckprefix (void);
46 static const char *prefix_name (int, int);
47 static int print_insn (bfd_vma, disassemble_info *);
48 static void dofloat (int);
49 static void OP_ST (int, int);
50 static void OP_STi (int, int);
51 static int putop (const char *, int);
52 static void oappend (const char *);
53 static void append_seg (void);
54 static void OP_indirE (int, int);
55 static void print_operand_value (char *, int, bfd_vma);
56 static void OP_E_register (int, int);
57 static void OP_E_memory (int, int, int);
58 static void OP_E_extended (int, int, int);
59 static void print_displacement (char *, bfd_vma);
60 static void OP_E (int, int);
61 static void OP_G (int, int);
62 static bfd_vma get64 (void);
63 static bfd_signed_vma get32 (void);
64 static bfd_signed_vma get32s (void);
65 static int get16 (void);
66 static void set_op (bfd_vma, int);
67 static void OP_Skip_MODRM (int, int);
68 static void OP_REG (int, int);
69 static void OP_IMREG (int, int);
70 static void OP_I (int, int);
71 static void OP_I64 (int, int);
72 static void OP_sI (int, int);
73 static void OP_J (int, int);
74 static void OP_SEG (int, int);
75 static void OP_DIR (int, int);
76 static void OP_OFF (int, int);
77 static void OP_OFF64 (int, int);
78 static void ptr_reg (int, int);
79 static void OP_ESreg (int, int);
80 static void OP_DSreg (int, int);
81 static void OP_C (int, int);
82 static void OP_D (int, int);
83 static void OP_T (int, int);
84 static void OP_R (int, int);
85 static void OP_MMX (int, int);
86 static void OP_XMM (int, int);
87 static void OP_EM (int, int);
88 static void OP_EX (int, int);
89 static void OP_EMC (int,int);
90 static void OP_MXC (int,int);
91 static void OP_MS (int, int);
92 static void OP_XS (int, int);
93 static void OP_M (int, int);
94 static void OP_VEX (int, int);
95 static void OP_VEX_FMA (int, int);
96 static void OP_EX_Vex (int, int);
97 static void OP_EX_VexW (int, int);
98 static void OP_EX_VexImmW (int, int);
99 static void OP_XMM_Vex (int, int);
100 static void OP_XMM_VexW (int, int);
101 static void OP_REG_VexI4 (int, int);
102 static void PCLMUL_Fixup (int, int);
103 static void VEXI4_Fixup (int, int);
104 static void VZERO_Fixup (int, int);
105 static void VCMP_Fixup (int, int);
106 static void VPERMIL2_Fixup (int, int);
107 static void OP_0f07 (int, int);
108 static void OP_Monitor (int, int);
109 static void OP_Mwait (int, int);
110 static void NOP_Fixup1 (int, int);
111 static void NOP_Fixup2 (int, int);
112 static void OP_3DNowSuffix (int, int);
113 static void CMP_Fixup (int, int);
114 static void BadOp (void);
115 static void REP_Fixup (int, int);
116 static void CMPXCHG8B_Fixup (int, int);
117 static void XMM_Fixup (int, int);
118 static void CRC32_Fixup (int, int);
119 static void print_drex_arg (unsigned int, int, int);
120 static void OP_DREX4 (int, int);
121 static void OP_DREX3 (int, int);
122 static void OP_DREX_ICMP (int, int);
123 static void OP_DREX_FCMP (int, int);
124
125 struct dis_private {
126 /* Points to first byte not fetched. */
127 bfd_byte *max_fetched;
128 bfd_byte the_buffer[MAX_MNEM_SIZE];
129 bfd_vma insn_start;
130 int orig_sizeflag;
131 jmp_buf bailout;
132 };
133
134 enum address_mode
135 {
136 mode_16bit,
137 mode_32bit,
138 mode_64bit
139 };
140
141 enum address_mode address_mode;
142
143 /* Flags for the prefixes for the current instruction. See below. */
144 static int prefixes;
145
146 /* REX prefix the current instruction. See below. */
147 static int rex;
148 /* Bits of REX we've already used. */
149 static int rex_used;
150 /* Original REX prefix. */
151 static int rex_original;
152 /* REX bits in original REX prefix ignored. It may not be the same
153 as rex_original since some bits may not be ignored. */
154 static int rex_ignored;
155 /* Mark parts used in the REX prefix. When we are testing for
156 empty prefix (for 8bit register REX extension), just mask it
157 out. Otherwise test for REX bit is excuse for existence of REX
158 only in case value is nonzero. */
159 #define USED_REX(value) \
160 { \
161 if (value) \
162 { \
163 if ((rex & value)) \
164 rex_used |= (value) | REX_OPCODE; \
165 } \
166 else \
167 rex_used |= REX_OPCODE; \
168 }
169
170 /* Special 'registers' for DREX handling */
171 #define DREX_REG_UNKNOWN 1000 /* not initialized */
172 #define DREX_REG_MEMORY 1001 /* use MODRM/SIB/OFFSET memory */
173
174 /* The DREX byte has the following fields:
175 Bits 7-4 -- DREX.Dest, xmm destination register
176 Bit 3 -- DREX.OC0, operand config bit defines operand order
177 Bit 2 -- DREX.R, equivalent to REX_R bit, to extend ModRM register
178 Bit 1 -- DREX.X, equivalent to REX_X bit, to extend SIB index field
179 Bit 0 -- DREX.W, equivalent to REX_B bit, to extend ModRM r/m field,
180 SIB base field, or opcode reg field. */
181 #define DREX_XMM(drex) ((drex >> 4) & 0xf)
182 #define DREX_OC0(drex) ((drex >> 3) & 0x1)
183
184 /* Flags for prefixes which we somehow handled when printing the
185 current instruction. */
186 static int used_prefixes;
187
188 /* Flags stored in PREFIXES. */
189 #define PREFIX_REPZ 1
190 #define PREFIX_REPNZ 2
191 #define PREFIX_LOCK 4
192 #define PREFIX_CS 8
193 #define PREFIX_SS 0x10
194 #define PREFIX_DS 0x20
195 #define PREFIX_ES 0x40
196 #define PREFIX_FS 0x80
197 #define PREFIX_GS 0x100
198 #define PREFIX_DATA 0x200
199 #define PREFIX_ADDR 0x400
200 #define PREFIX_FWAIT 0x800
201
202 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
203 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
204 on error. */
205 #define FETCH_DATA(info, addr) \
206 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
207 ? 1 : fetch_data ((info), (addr)))
208
209 static int
210 fetch_data (struct disassemble_info *info, bfd_byte *addr)
211 {
212 int status;
213 struct dis_private *priv = (struct dis_private *) info->private_data;
214 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
215
216 if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
217 status = (*info->read_memory_func) (start,
218 priv->max_fetched,
219 addr - priv->max_fetched,
220 info);
221 else
222 status = -1;
223 if (status != 0)
224 {
225 /* If we did manage to read at least one byte, then
226 print_insn_i386 will do something sensible. Otherwise, print
227 an error. We do that here because this is where we know
228 STATUS. */
229 if (priv->max_fetched == priv->the_buffer)
230 (*info->memory_error_func) (status, start, info);
231 longjmp (priv->bailout, 1);
232 }
233 else
234 priv->max_fetched = addr;
235 return 1;
236 }
237
238 #define XX { NULL, 0 }
239
240 #define Eb { OP_E, b_mode }
241 #define Ev { OP_E, v_mode }
242 #define Ed { OP_E, d_mode }
243 #define Edq { OP_E, dq_mode }
244 #define Edqw { OP_E, dqw_mode }
245 #define Edqb { OP_E, dqb_mode }
246 #define Edqd { OP_E, dqd_mode }
247 #define Eq { OP_E, q_mode }
248 #define indirEv { OP_indirE, stack_v_mode }
249 #define indirEp { OP_indirE, f_mode }
250 #define stackEv { OP_E, stack_v_mode }
251 #define Em { OP_E, m_mode }
252 #define Ew { OP_E, w_mode }
253 #define M { OP_M, 0 } /* lea, lgdt, etc. */
254 #define Ma { OP_M, a_mode }
255 #define Mb { OP_M, b_mode }
256 #define Md { OP_M, d_mode }
257 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
258 #define Mq { OP_M, q_mode }
259 #define Mx { OP_M, x_mode }
260 #define Mxmm { OP_M, xmm_mode }
261 #define Gb { OP_G, b_mode }
262 #define Gv { OP_G, v_mode }
263 #define Gd { OP_G, d_mode }
264 #define Gdq { OP_G, dq_mode }
265 #define Gm { OP_G, m_mode }
266 #define Gw { OP_G, w_mode }
267 #define Rd { OP_R, d_mode }
268 #define Rm { OP_R, m_mode }
269 #define Ib { OP_I, b_mode }
270 #define sIb { OP_sI, b_mode } /* sign extened byte */
271 #define Iv { OP_I, v_mode }
272 #define Iq { OP_I, q_mode }
273 #define Iv64 { OP_I64, v_mode }
274 #define Iw { OP_I, w_mode }
275 #define I1 { OP_I, const_1_mode }
276 #define Jb { OP_J, b_mode }
277 #define Jv { OP_J, v_mode }
278 #define Cm { OP_C, m_mode }
279 #define Dm { OP_D, m_mode }
280 #define Td { OP_T, d_mode }
281 #define Skip_MODRM { OP_Skip_MODRM, 0 }
282
283 #define RMeAX { OP_REG, eAX_reg }
284 #define RMeBX { OP_REG, eBX_reg }
285 #define RMeCX { OP_REG, eCX_reg }
286 #define RMeDX { OP_REG, eDX_reg }
287 #define RMeSP { OP_REG, eSP_reg }
288 #define RMeBP { OP_REG, eBP_reg }
289 #define RMeSI { OP_REG, eSI_reg }
290 #define RMeDI { OP_REG, eDI_reg }
291 #define RMrAX { OP_REG, rAX_reg }
292 #define RMrBX { OP_REG, rBX_reg }
293 #define RMrCX { OP_REG, rCX_reg }
294 #define RMrDX { OP_REG, rDX_reg }
295 #define RMrSP { OP_REG, rSP_reg }
296 #define RMrBP { OP_REG, rBP_reg }
297 #define RMrSI { OP_REG, rSI_reg }
298 #define RMrDI { OP_REG, rDI_reg }
299 #define RMAL { OP_REG, al_reg }
300 #define RMAL { OP_REG, al_reg }
301 #define RMCL { OP_REG, cl_reg }
302 #define RMDL { OP_REG, dl_reg }
303 #define RMBL { OP_REG, bl_reg }
304 #define RMAH { OP_REG, ah_reg }
305 #define RMCH { OP_REG, ch_reg }
306 #define RMDH { OP_REG, dh_reg }
307 #define RMBH { OP_REG, bh_reg }
308 #define RMAX { OP_REG, ax_reg }
309 #define RMDX { OP_REG, dx_reg }
310
311 #define eAX { OP_IMREG, eAX_reg }
312 #define eBX { OP_IMREG, eBX_reg }
313 #define eCX { OP_IMREG, eCX_reg }
314 #define eDX { OP_IMREG, eDX_reg }
315 #define eSP { OP_IMREG, eSP_reg }
316 #define eBP { OP_IMREG, eBP_reg }
317 #define eSI { OP_IMREG, eSI_reg }
318 #define eDI { OP_IMREG, eDI_reg }
319 #define AL { OP_IMREG, al_reg }
320 #define CL { OP_IMREG, cl_reg }
321 #define DL { OP_IMREG, dl_reg }
322 #define BL { OP_IMREG, bl_reg }
323 #define AH { OP_IMREG, ah_reg }
324 #define CH { OP_IMREG, ch_reg }
325 #define DH { OP_IMREG, dh_reg }
326 #define BH { OP_IMREG, bh_reg }
327 #define AX { OP_IMREG, ax_reg }
328 #define DX { OP_IMREG, dx_reg }
329 #define zAX { OP_IMREG, z_mode_ax_reg }
330 #define indirDX { OP_IMREG, indir_dx_reg }
331
332 #define Sw { OP_SEG, w_mode }
333 #define Sv { OP_SEG, v_mode }
334 #define Ap { OP_DIR, 0 }
335 #define Ob { OP_OFF64, b_mode }
336 #define Ov { OP_OFF64, v_mode }
337 #define Xb { OP_DSreg, eSI_reg }
338 #define Xv { OP_DSreg, eSI_reg }
339 #define Xz { OP_DSreg, eSI_reg }
340 #define Yb { OP_ESreg, eDI_reg }
341 #define Yv { OP_ESreg, eDI_reg }
342 #define DSBX { OP_DSreg, eBX_reg }
343
344 #define es { OP_REG, es_reg }
345 #define ss { OP_REG, ss_reg }
346 #define cs { OP_REG, cs_reg }
347 #define ds { OP_REG, ds_reg }
348 #define fs { OP_REG, fs_reg }
349 #define gs { OP_REG, gs_reg }
350
351 #define MX { OP_MMX, 0 }
352 #define XM { OP_XMM, 0 }
353 #define XMM { OP_XMM, xmm_mode }
354 #define EM { OP_EM, v_mode }
355 #define EMd { OP_EM, d_mode }
356 #define EMx { OP_EM, x_mode }
357 #define EXw { OP_EX, w_mode }
358 #define EXd { OP_EX, d_mode }
359 #define EXq { OP_EX, q_mode }
360 #define EXx { OP_EX, x_mode }
361 #define EXxmm { OP_EX, xmm_mode }
362 #define EXxmmq { OP_EX, xmmq_mode }
363 #define EXymmq { OP_EX, ymmq_mode }
364 #define MS { OP_MS, v_mode }
365 #define XS { OP_XS, v_mode }
366 #define EMCq { OP_EMC, q_mode }
367 #define MXC { OP_MXC, 0 }
368 #define OPSUF { OP_3DNowSuffix, 0 }
369 #define CMP { CMP_Fixup, 0 }
370 #define XMM0 { XMM_Fixup, 0 }
371
372 #define Vex { OP_VEX, vex_mode }
373 #define Vex128 { OP_VEX, vex128_mode }
374 #define Vex256 { OP_VEX, vex256_mode }
375 #define VexI4 { VEXI4_Fixup, 0}
376 #define VexFMA { OP_VEX_FMA, vex_mode }
377 #define Vex128FMA { OP_VEX_FMA, vex128_mode }
378 #define EXdVex { OP_EX_Vex, d_mode }
379 #define EXqVex { OP_EX_Vex, q_mode }
380 #define EXVexW { OP_EX_VexW, x_mode }
381 #define EXdVexW { OP_EX_VexW, d_mode }
382 #define EXqVexW { OP_EX_VexW, q_mode }
383 #define EXVexImmW { OP_EX_VexImmW, x_mode }
384 #define XMVex { OP_XMM_Vex, 0 }
385 #define XMVexW { OP_XMM_VexW, 0 }
386 #define XMVexI4 { OP_REG_VexI4, x_mode }
387 #define PCLMUL { PCLMUL_Fixup, 0 }
388 #define VZERO { VZERO_Fixup, 0 }
389 #define VCMP { VCMP_Fixup, 0 }
390 #define VPERMIL2 { VPERMIL2_Fixup, 0 }
391
392 /* Used handle "rep" prefix for string instructions. */
393 #define Xbr { REP_Fixup, eSI_reg }
394 #define Xvr { REP_Fixup, eSI_reg }
395 #define Ybr { REP_Fixup, eDI_reg }
396 #define Yvr { REP_Fixup, eDI_reg }
397 #define Yzr { REP_Fixup, eDI_reg }
398 #define indirDXr { REP_Fixup, indir_dx_reg }
399 #define ALr { REP_Fixup, al_reg }
400 #define eAXr { REP_Fixup, eAX_reg }
401
402 #define cond_jump_flag { NULL, cond_jump_mode }
403 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
404
405 /* bits in sizeflag */
406 #define SUFFIX_ALWAYS 4
407 #define AFLAG 2
408 #define DFLAG 1
409
410 /* byte operand */
411 #define b_mode 1
412 /* operand size depends on prefixes */
413 #define v_mode (b_mode + 1)
414 /* word operand */
415 #define w_mode (v_mode + 1)
416 /* double word operand */
417 #define d_mode (w_mode + 1)
418 /* quad word operand */
419 #define q_mode (d_mode + 1)
420 /* ten-byte operand */
421 #define t_mode (q_mode + 1)
422 /* 16-byte XMM or 32-byte YMM operand */
423 #define x_mode (t_mode + 1)
424 /* 16-byte XMM operand */
425 #define xmm_mode (x_mode + 1)
426 /* 16-byte XMM or quad word operand */
427 #define xmmq_mode (xmm_mode + 1)
428 /* 32-byte YMM or quad word operand */
429 #define ymmq_mode (xmmq_mode + 1)
430 /* d_mode in 32bit, q_mode in 64bit mode. */
431 #define m_mode (ymmq_mode + 1)
432 /* pair of v_mode operands */
433 #define a_mode (m_mode + 1)
434 #define cond_jump_mode (a_mode + 1)
435 #define loop_jcxz_mode (cond_jump_mode + 1)
436 /* operand size depends on REX prefixes. */
437 #define dq_mode (loop_jcxz_mode + 1)
438 /* registers like dq_mode, memory like w_mode. */
439 #define dqw_mode (dq_mode + 1)
440 /* 4- or 6-byte pointer operand */
441 #define f_mode (dqw_mode + 1)
442 #define const_1_mode (f_mode + 1)
443 /* v_mode for stack-related opcodes. */
444 #define stack_v_mode (const_1_mode + 1)
445 /* non-quad operand size depends on prefixes */
446 #define z_mode (stack_v_mode + 1)
447 /* 16-byte operand */
448 #define o_mode (z_mode + 1)
449 /* registers like dq_mode, memory like b_mode. */
450 #define dqb_mode (o_mode + 1)
451 /* registers like dq_mode, memory like d_mode. */
452 #define dqd_mode (dqb_mode + 1)
453 /* normal vex mode */
454 #define vex_mode (dqd_mode + 1)
455 /* 128bit vex mode */
456 #define vex128_mode (vex_mode + 1)
457 /* 256bit vex mode */
458 #define vex256_mode (vex128_mode + 1)
459
460 #define es_reg (vex256_mode + 1)
461 #define cs_reg (es_reg + 1)
462 #define ss_reg (cs_reg + 1)
463 #define ds_reg (ss_reg + 1)
464 #define fs_reg (ds_reg + 1)
465 #define gs_reg (fs_reg + 1)
466
467 #define eAX_reg (gs_reg + 1)
468 #define eCX_reg (eAX_reg + 1)
469 #define eDX_reg (eCX_reg + 1)
470 #define eBX_reg (eDX_reg + 1)
471 #define eSP_reg (eBX_reg + 1)
472 #define eBP_reg (eSP_reg + 1)
473 #define eSI_reg (eBP_reg + 1)
474 #define eDI_reg (eSI_reg + 1)
475
476 #define al_reg (eDI_reg + 1)
477 #define cl_reg (al_reg + 1)
478 #define dl_reg (cl_reg + 1)
479 #define bl_reg (dl_reg + 1)
480 #define ah_reg (bl_reg + 1)
481 #define ch_reg (ah_reg + 1)
482 #define dh_reg (ch_reg + 1)
483 #define bh_reg (dh_reg + 1)
484
485 #define ax_reg (bh_reg + 1)
486 #define cx_reg (ax_reg + 1)
487 #define dx_reg (cx_reg + 1)
488 #define bx_reg (dx_reg + 1)
489 #define sp_reg (bx_reg + 1)
490 #define bp_reg (sp_reg + 1)
491 #define si_reg (bp_reg + 1)
492 #define di_reg (si_reg + 1)
493
494 #define rAX_reg (di_reg + 1)
495 #define rCX_reg (rAX_reg + 1)
496 #define rDX_reg (rCX_reg + 1)
497 #define rBX_reg (rDX_reg + 1)
498 #define rSP_reg (rBX_reg + 1)
499 #define rBP_reg (rSP_reg + 1)
500 #define rSI_reg (rBP_reg + 1)
501 #define rDI_reg (rSI_reg + 1)
502
503 #define z_mode_ax_reg (rDI_reg + 1)
504 #define indir_dx_reg (z_mode_ax_reg + 1)
505
506 #define MAX_BYTEMODE indir_dx_reg
507
508 /* Flags that are OR'ed into the bytemode field to pass extra
509 information. */
510 #define DREX_OC1 0x10000 /* OC1 bit set */
511 #define DREX_NO_OC0 0x20000 /* OC0 bit not used */
512 #define DREX_MASK 0x40000 /* mask to delete */
513
514 #if MAX_BYTEMODE >= DREX_OC1
515 #error MAX_BYTEMODE must be less than DREX_OC1
516 #endif
517
518 #define FLOATCODE 1
519 #define USE_REG_TABLE (FLOATCODE + 1)
520 #define USE_MOD_TABLE (USE_REG_TABLE + 1)
521 #define USE_RM_TABLE (USE_MOD_TABLE + 1)
522 #define USE_PREFIX_TABLE (USE_RM_TABLE + 1)
523 #define USE_X86_64_TABLE (USE_PREFIX_TABLE + 1)
524 #define USE_3BYTE_TABLE (USE_X86_64_TABLE + 1)
525 #define USE_VEX_C4_TABLE (USE_3BYTE_TABLE + 1)
526 #define USE_VEX_C5_TABLE (USE_VEX_C4_TABLE + 1)
527 #define USE_VEX_LEN_TABLE (USE_VEX_C5_TABLE + 1)
528
529 #define FLOAT NULL, { { NULL, FLOATCODE } }
530
531 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }
532 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
533 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
534 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
535 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
536 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
537 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
538 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
539 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
540 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
541
542 #define REG_80 0
543 #define REG_81 (REG_80 + 1)
544 #define REG_82 (REG_81 + 1)
545 #define REG_8F (REG_82 + 1)
546 #define REG_C0 (REG_8F + 1)
547 #define REG_C1 (REG_C0 + 1)
548 #define REG_C6 (REG_C1 + 1)
549 #define REG_C7 (REG_C6 + 1)
550 #define REG_D0 (REG_C7 + 1)
551 #define REG_D1 (REG_D0 + 1)
552 #define REG_D2 (REG_D1 + 1)
553 #define REG_D3 (REG_D2 + 1)
554 #define REG_F6 (REG_D3 + 1)
555 #define REG_F7 (REG_F6 + 1)
556 #define REG_FE (REG_F7 + 1)
557 #define REG_FF (REG_FE + 1)
558 #define REG_0F00 (REG_FF + 1)
559 #define REG_0F01 (REG_0F00 + 1)
560 #define REG_0F0D (REG_0F01 + 1)
561 #define REG_0F18 (REG_0F0D + 1)
562 #define REG_0F71 (REG_0F18 + 1)
563 #define REG_0F72 (REG_0F71 + 1)
564 #define REG_0F73 (REG_0F72 + 1)
565 #define REG_0FA6 (REG_0F73 + 1)
566 #define REG_0FA7 (REG_0FA6 + 1)
567 #define REG_0FAE (REG_0FA7 + 1)
568 #define REG_0FBA (REG_0FAE + 1)
569 #define REG_0FC7 (REG_0FBA + 1)
570 #define REG_VEX_71 (REG_0FC7 + 1)
571 #define REG_VEX_72 (REG_VEX_71 + 1)
572 #define REG_VEX_73 (REG_VEX_72 + 1)
573 #define REG_VEX_AE (REG_VEX_73 + 1)
574
575 #define MOD_8D 0
576 #define MOD_0F01_REG_0 (MOD_8D + 1)
577 #define MOD_0F01_REG_1 (MOD_0F01_REG_0 + 1)
578 #define MOD_0F01_REG_2 (MOD_0F01_REG_1 + 1)
579 #define MOD_0F01_REG_3 (MOD_0F01_REG_2 + 1)
580 #define MOD_0F01_REG_7 (MOD_0F01_REG_3 + 1)
581 #define MOD_0F12_PREFIX_0 (MOD_0F01_REG_7 + 1)
582 #define MOD_0F13 (MOD_0F12_PREFIX_0 + 1)
583 #define MOD_0F16_PREFIX_0 (MOD_0F13 + 1)
584 #define MOD_0F17 (MOD_0F16_PREFIX_0 + 1)
585 #define MOD_0F18_REG_0 (MOD_0F17 + 1)
586 #define MOD_0F18_REG_1 (MOD_0F18_REG_0 + 1)
587 #define MOD_0F18_REG_2 (MOD_0F18_REG_1 + 1)
588 #define MOD_0F18_REG_3 (MOD_0F18_REG_2 + 1)
589 #define MOD_0F20 (MOD_0F18_REG_3 + 1)
590 #define MOD_0F21 (MOD_0F20 + 1)
591 #define MOD_0F22 (MOD_0F21 + 1)
592 #define MOD_0F23 (MOD_0F22 + 1)
593 #define MOD_0F24 (MOD_0F23 + 1)
594 #define MOD_0F26 (MOD_0F24 + 1)
595 #define MOD_0F2B_PREFIX_0 (MOD_0F26 + 1)
596 #define MOD_0F2B_PREFIX_1 (MOD_0F2B_PREFIX_0 + 1)
597 #define MOD_0F2B_PREFIX_2 (MOD_0F2B_PREFIX_1 + 1)
598 #define MOD_0F2B_PREFIX_3 (MOD_0F2B_PREFIX_2 + 1)
599 #define MOD_0F51 (MOD_0F2B_PREFIX_3 + 1)
600 #define MOD_0F71_REG_2 (MOD_0F51 + 1)
601 #define MOD_0F71_REG_4 (MOD_0F71_REG_2 + 1)
602 #define MOD_0F71_REG_6 (MOD_0F71_REG_4 + 1)
603 #define MOD_0F72_REG_2 (MOD_0F71_REG_6 + 1)
604 #define MOD_0F72_REG_4 (MOD_0F72_REG_2 + 1)
605 #define MOD_0F72_REG_6 (MOD_0F72_REG_4 + 1)
606 #define MOD_0F73_REG_2 (MOD_0F72_REG_6 + 1)
607 #define MOD_0F73_REG_3 (MOD_0F73_REG_2 + 1)
608 #define MOD_0F73_REG_6 (MOD_0F73_REG_3 + 1)
609 #define MOD_0F73_REG_7 (MOD_0F73_REG_6 + 1)
610 #define MOD_0FAE_REG_0 (MOD_0F73_REG_7 + 1)
611 #define MOD_0FAE_REG_1 (MOD_0FAE_REG_0 + 1)
612 #define MOD_0FAE_REG_2 (MOD_0FAE_REG_1 + 1)
613 #define MOD_0FAE_REG_3 (MOD_0FAE_REG_2 + 1)
614 #define MOD_0FAE_REG_4 (MOD_0FAE_REG_3 + 1)
615 #define MOD_0FAE_REG_5 (MOD_0FAE_REG_4 + 1)
616 #define MOD_0FAE_REG_6 (MOD_0FAE_REG_5 + 1)
617 #define MOD_0FAE_REG_7 (MOD_0FAE_REG_6 + 1)
618 #define MOD_0FB2 (MOD_0FAE_REG_7 + 1)
619 #define MOD_0FB4 (MOD_0FB2 + 1)
620 #define MOD_0FB5 (MOD_0FB4 + 1)
621 #define MOD_0FC7_REG_6 (MOD_0FB5 + 1)
622 #define MOD_0FC7_REG_7 (MOD_0FC7_REG_6 + 1)
623 #define MOD_0FD7 (MOD_0FC7_REG_7 + 1)
624 #define MOD_0FE7_PREFIX_2 (MOD_0FD7 + 1)
625 #define MOD_0FF0_PREFIX_3 (MOD_0FE7_PREFIX_2 + 1)
626 #define MOD_0F382A_PREFIX_2 (MOD_0FF0_PREFIX_3 + 1)
627 #define MOD_62_32BIT (MOD_0F382A_PREFIX_2 + 1)
628 #define MOD_C4_32BIT (MOD_62_32BIT + 1)
629 #define MOD_C5_32BIT (MOD_C4_32BIT + 1)
630 #define MOD_VEX_12_PREFIX_0 (MOD_C5_32BIT + 1)
631 #define MOD_VEX_13 (MOD_VEX_12_PREFIX_0 + 1)
632 #define MOD_VEX_16_PREFIX_0 (MOD_VEX_13 + 1)
633 #define MOD_VEX_17 (MOD_VEX_16_PREFIX_0 + 1)
634 #define MOD_VEX_2B (MOD_VEX_17 + 1)
635 #define MOD_VEX_51 (MOD_VEX_2B + 1)
636 #define MOD_VEX_71_REG_2 (MOD_VEX_51 + 1)
637 #define MOD_VEX_71_REG_4 (MOD_VEX_71_REG_2 + 1)
638 #define MOD_VEX_71_REG_6 (MOD_VEX_71_REG_4 + 1)
639 #define MOD_VEX_72_REG_2 (MOD_VEX_71_REG_6 + 1)
640 #define MOD_VEX_72_REG_4 (MOD_VEX_72_REG_2 + 1)
641 #define MOD_VEX_72_REG_6 (MOD_VEX_72_REG_4 + 1)
642 #define MOD_VEX_73_REG_2 (MOD_VEX_72_REG_6 + 1)
643 #define MOD_VEX_73_REG_3 (MOD_VEX_73_REG_2 + 1)
644 #define MOD_VEX_73_REG_6 (MOD_VEX_73_REG_3 + 1)
645 #define MOD_VEX_73_REG_7 (MOD_VEX_73_REG_6 + 1)
646 #define MOD_VEX_AE_REG_2 (MOD_VEX_73_REG_7 + 1)
647 #define MOD_VEX_AE_REG_3 (MOD_VEX_AE_REG_2 + 1)
648 #define MOD_VEX_D7_PREFIX_2 (MOD_VEX_AE_REG_3 + 1)
649 #define MOD_VEX_E7_PREFIX_2 (MOD_VEX_D7_PREFIX_2 + 1)
650 #define MOD_VEX_F0_PREFIX_3 (MOD_VEX_E7_PREFIX_2 + 1)
651 #define MOD_VEX_3818_PREFIX_2 (MOD_VEX_F0_PREFIX_3 + 1)
652 #define MOD_VEX_3819_PREFIX_2 (MOD_VEX_3818_PREFIX_2 + 1)
653 #define MOD_VEX_381A_PREFIX_2 (MOD_VEX_3819_PREFIX_2 + 1)
654 #define MOD_VEX_382A_PREFIX_2 (MOD_VEX_381A_PREFIX_2 + 1)
655 #define MOD_VEX_382C_PREFIX_2 (MOD_VEX_382A_PREFIX_2 + 1)
656 #define MOD_VEX_382D_PREFIX_2 (MOD_VEX_382C_PREFIX_2 + 1)
657 #define MOD_VEX_382E_PREFIX_2 (MOD_VEX_382D_PREFIX_2 + 1)
658 #define MOD_VEX_382F_PREFIX_2 (MOD_VEX_382E_PREFIX_2 + 1)
659
660 #define RM_0F01_REG_0 0
661 #define RM_0F01_REG_1 (RM_0F01_REG_0 + 1)
662 #define RM_0F01_REG_2 (RM_0F01_REG_1 + 1)
663 #define RM_0F01_REG_3 (RM_0F01_REG_2 + 1)
664 #define RM_0F01_REG_7 (RM_0F01_REG_3 + 1)
665 #define RM_0FAE_REG_5 (RM_0F01_REG_7 + 1)
666 #define RM_0FAE_REG_6 (RM_0FAE_REG_5 + 1)
667 #define RM_0FAE_REG_7 (RM_0FAE_REG_6 + 1)
668
669 #define PREFIX_90 0
670 #define PREFIX_0F10 (PREFIX_90 + 1)
671 #define PREFIX_0F11 (PREFIX_0F10 + 1)
672 #define PREFIX_0F12 (PREFIX_0F11 + 1)
673 #define PREFIX_0F16 (PREFIX_0F12 + 1)
674 #define PREFIX_0F2A (PREFIX_0F16 + 1)
675 #define PREFIX_0F2B (PREFIX_0F2A + 1)
676 #define PREFIX_0F2C (PREFIX_0F2B + 1)
677 #define PREFIX_0F2D (PREFIX_0F2C + 1)
678 #define PREFIX_0F2E (PREFIX_0F2D + 1)
679 #define PREFIX_0F2F (PREFIX_0F2E + 1)
680 #define PREFIX_0F51 (PREFIX_0F2F + 1)
681 #define PREFIX_0F52 (PREFIX_0F51 + 1)
682 #define PREFIX_0F53 (PREFIX_0F52 + 1)
683 #define PREFIX_0F58 (PREFIX_0F53 + 1)
684 #define PREFIX_0F59 (PREFIX_0F58 + 1)
685 #define PREFIX_0F5A (PREFIX_0F59 + 1)
686 #define PREFIX_0F5B (PREFIX_0F5A + 1)
687 #define PREFIX_0F5C (PREFIX_0F5B + 1)
688 #define PREFIX_0F5D (PREFIX_0F5C + 1)
689 #define PREFIX_0F5E (PREFIX_0F5D + 1)
690 #define PREFIX_0F5F (PREFIX_0F5E + 1)
691 #define PREFIX_0F60 (PREFIX_0F5F + 1)
692 #define PREFIX_0F61 (PREFIX_0F60 + 1)
693 #define PREFIX_0F62 (PREFIX_0F61 + 1)
694 #define PREFIX_0F6C (PREFIX_0F62 + 1)
695 #define PREFIX_0F6D (PREFIX_0F6C + 1)
696 #define PREFIX_0F6F (PREFIX_0F6D + 1)
697 #define PREFIX_0F70 (PREFIX_0F6F + 1)
698 #define PREFIX_0F73_REG_3 (PREFIX_0F70 + 1)
699 #define PREFIX_0F73_REG_7 (PREFIX_0F73_REG_3 + 1)
700 #define PREFIX_0F78 (PREFIX_0F73_REG_7 + 1)
701 #define PREFIX_0F79 (PREFIX_0F78 + 1)
702 #define PREFIX_0F7C (PREFIX_0F79 + 1)
703 #define PREFIX_0F7D (PREFIX_0F7C + 1)
704 #define PREFIX_0F7E (PREFIX_0F7D + 1)
705 #define PREFIX_0F7F (PREFIX_0F7E + 1)
706 #define PREFIX_0FB8 (PREFIX_0F7F + 1)
707 #define PREFIX_0FBD (PREFIX_0FB8 + 1)
708 #define PREFIX_0FC2 (PREFIX_0FBD + 1)
709 #define PREFIX_0FC3 (PREFIX_0FC2 + 1)
710 #define PREFIX_0FC7_REG_6 (PREFIX_0FC3 + 1)
711 #define PREFIX_0FD0 (PREFIX_0FC7_REG_6 + 1)
712 #define PREFIX_0FD6 (PREFIX_0FD0 + 1)
713 #define PREFIX_0FE6 (PREFIX_0FD6 + 1)
714 #define PREFIX_0FE7 (PREFIX_0FE6 + 1)
715 #define PREFIX_0FF0 (PREFIX_0FE7 + 1)
716 #define PREFIX_0FF7 (PREFIX_0FF0 + 1)
717 #define PREFIX_0F3810 (PREFIX_0FF7 + 1)
718 #define PREFIX_0F3814 (PREFIX_0F3810 + 1)
719 #define PREFIX_0F3815 (PREFIX_0F3814 + 1)
720 #define PREFIX_0F3817 (PREFIX_0F3815 + 1)
721 #define PREFIX_0F3820 (PREFIX_0F3817 + 1)
722 #define PREFIX_0F3821 (PREFIX_0F3820 + 1)
723 #define PREFIX_0F3822 (PREFIX_0F3821 + 1)
724 #define PREFIX_0F3823 (PREFIX_0F3822 + 1)
725 #define PREFIX_0F3824 (PREFIX_0F3823 + 1)
726 #define PREFIX_0F3825 (PREFIX_0F3824 + 1)
727 #define PREFIX_0F3828 (PREFIX_0F3825 + 1)
728 #define PREFIX_0F3829 (PREFIX_0F3828 + 1)
729 #define PREFIX_0F382A (PREFIX_0F3829 + 1)
730 #define PREFIX_0F382B (PREFIX_0F382A + 1)
731 #define PREFIX_0F3830 (PREFIX_0F382B + 1)
732 #define PREFIX_0F3831 (PREFIX_0F3830 + 1)
733 #define PREFIX_0F3832 (PREFIX_0F3831 + 1)
734 #define PREFIX_0F3833 (PREFIX_0F3832 + 1)
735 #define PREFIX_0F3834 (PREFIX_0F3833 + 1)
736 #define PREFIX_0F3835 (PREFIX_0F3834 + 1)
737 #define PREFIX_0F3837 (PREFIX_0F3835 + 1)
738 #define PREFIX_0F3838 (PREFIX_0F3837 + 1)
739 #define PREFIX_0F3839 (PREFIX_0F3838 + 1)
740 #define PREFIX_0F383A (PREFIX_0F3839 + 1)
741 #define PREFIX_0F383B (PREFIX_0F383A + 1)
742 #define PREFIX_0F383C (PREFIX_0F383B + 1)
743 #define PREFIX_0F383D (PREFIX_0F383C + 1)
744 #define PREFIX_0F383E (PREFIX_0F383D + 1)
745 #define PREFIX_0F383F (PREFIX_0F383E + 1)
746 #define PREFIX_0F3840 (PREFIX_0F383F + 1)
747 #define PREFIX_0F3841 (PREFIX_0F3840 + 1)
748 #define PREFIX_0F38DB (PREFIX_0F3841 + 1)
749 #define PREFIX_0F38DC (PREFIX_0F38DB + 1)
750 #define PREFIX_0F38DD (PREFIX_0F38DC + 1)
751 #define PREFIX_0F38DE (PREFIX_0F38DD + 1)
752 #define PREFIX_0F38DF (PREFIX_0F38DE + 1)
753 #define PREFIX_0F38F0 (PREFIX_0F38DF + 1)
754 #define PREFIX_0F38F1 (PREFIX_0F38F0 + 1)
755 #define PREFIX_0F3A08 (PREFIX_0F38F1 + 1)
756 #define PREFIX_0F3A09 (PREFIX_0F3A08 + 1)
757 #define PREFIX_0F3A0A (PREFIX_0F3A09 + 1)
758 #define PREFIX_0F3A0B (PREFIX_0F3A0A + 1)
759 #define PREFIX_0F3A0C (PREFIX_0F3A0B + 1)
760 #define PREFIX_0F3A0D (PREFIX_0F3A0C + 1)
761 #define PREFIX_0F3A0E (PREFIX_0F3A0D + 1)
762 #define PREFIX_0F3A14 (PREFIX_0F3A0E + 1)
763 #define PREFIX_0F3A15 (PREFIX_0F3A14 + 1)
764 #define PREFIX_0F3A16 (PREFIX_0F3A15 + 1)
765 #define PREFIX_0F3A17 (PREFIX_0F3A16 + 1)
766 #define PREFIX_0F3A20 (PREFIX_0F3A17 + 1)
767 #define PREFIX_0F3A21 (PREFIX_0F3A20 + 1)
768 #define PREFIX_0F3A22 (PREFIX_0F3A21 + 1)
769 #define PREFIX_0F3A40 (PREFIX_0F3A22 + 1)
770 #define PREFIX_0F3A41 (PREFIX_0F3A40 + 1)
771 #define PREFIX_0F3A42 (PREFIX_0F3A41 + 1)
772 #define PREFIX_0F3A44 (PREFIX_0F3A42 + 1)
773 #define PREFIX_0F3A60 (PREFIX_0F3A44 + 1)
774 #define PREFIX_0F3A61 (PREFIX_0F3A60 + 1)
775 #define PREFIX_0F3A62 (PREFIX_0F3A61 + 1)
776 #define PREFIX_0F3A63 (PREFIX_0F3A62 + 1)
777 #define PREFIX_0F3ADF (PREFIX_0F3A63 + 1)
778 #define PREFIX_VEX_10 (PREFIX_0F3ADF + 1)
779 #define PREFIX_VEX_11 (PREFIX_VEX_10 + 1)
780 #define PREFIX_VEX_12 (PREFIX_VEX_11 + 1)
781 #define PREFIX_VEX_16 (PREFIX_VEX_12 + 1)
782 #define PREFIX_VEX_2A (PREFIX_VEX_16 + 1)
783 #define PREFIX_VEX_2C (PREFIX_VEX_2A + 1)
784 #define PREFIX_VEX_2D (PREFIX_VEX_2C + 1)
785 #define PREFIX_VEX_2E (PREFIX_VEX_2D + 1)
786 #define PREFIX_VEX_2F (PREFIX_VEX_2E + 1)
787 #define PREFIX_VEX_51 (PREFIX_VEX_2F + 1)
788 #define PREFIX_VEX_52 (PREFIX_VEX_51 + 1)
789 #define PREFIX_VEX_53 (PREFIX_VEX_52 + 1)
790 #define PREFIX_VEX_58 (PREFIX_VEX_53 + 1)
791 #define PREFIX_VEX_59 (PREFIX_VEX_58 + 1)
792 #define PREFIX_VEX_5A (PREFIX_VEX_59 + 1)
793 #define PREFIX_VEX_5B (PREFIX_VEX_5A + 1)
794 #define PREFIX_VEX_5C (PREFIX_VEX_5B + 1)
795 #define PREFIX_VEX_5D (PREFIX_VEX_5C + 1)
796 #define PREFIX_VEX_5E (PREFIX_VEX_5D + 1)
797 #define PREFIX_VEX_5F (PREFIX_VEX_5E + 1)
798 #define PREFIX_VEX_60 (PREFIX_VEX_5F + 1)
799 #define PREFIX_VEX_61 (PREFIX_VEX_60 + 1)
800 #define PREFIX_VEX_62 (PREFIX_VEX_61 + 1)
801 #define PREFIX_VEX_63 (PREFIX_VEX_62 + 1)
802 #define PREFIX_VEX_64 (PREFIX_VEX_63 + 1)
803 #define PREFIX_VEX_65 (PREFIX_VEX_64 + 1)
804 #define PREFIX_VEX_66 (PREFIX_VEX_65 + 1)
805 #define PREFIX_VEX_67 (PREFIX_VEX_66 + 1)
806 #define PREFIX_VEX_68 (PREFIX_VEX_67 + 1)
807 #define PREFIX_VEX_69 (PREFIX_VEX_68 + 1)
808 #define PREFIX_VEX_6A (PREFIX_VEX_69 + 1)
809 #define PREFIX_VEX_6B (PREFIX_VEX_6A + 1)
810 #define PREFIX_VEX_6C (PREFIX_VEX_6B + 1)
811 #define PREFIX_VEX_6D (PREFIX_VEX_6C + 1)
812 #define PREFIX_VEX_6E (PREFIX_VEX_6D + 1)
813 #define PREFIX_VEX_6F (PREFIX_VEX_6E + 1)
814 #define PREFIX_VEX_70 (PREFIX_VEX_6F + 1)
815 #define PREFIX_VEX_71_REG_2 (PREFIX_VEX_70 + 1)
816 #define PREFIX_VEX_71_REG_4 (PREFIX_VEX_71_REG_2 + 1)
817 #define PREFIX_VEX_71_REG_6 (PREFIX_VEX_71_REG_4 + 1)
818 #define PREFIX_VEX_72_REG_2 (PREFIX_VEX_71_REG_6 + 1)
819 #define PREFIX_VEX_72_REG_4 (PREFIX_VEX_72_REG_2 + 1)
820 #define PREFIX_VEX_72_REG_6 (PREFIX_VEX_72_REG_4 + 1)
821 #define PREFIX_VEX_73_REG_2 (PREFIX_VEX_72_REG_6 + 1)
822 #define PREFIX_VEX_73_REG_3 (PREFIX_VEX_73_REG_2 + 1)
823 #define PREFIX_VEX_73_REG_6 (PREFIX_VEX_73_REG_3 + 1)
824 #define PREFIX_VEX_73_REG_7 (PREFIX_VEX_73_REG_6 + 1)
825 #define PREFIX_VEX_74 (PREFIX_VEX_73_REG_7 + 1)
826 #define PREFIX_VEX_75 (PREFIX_VEX_74 + 1)
827 #define PREFIX_VEX_76 (PREFIX_VEX_75 + 1)
828 #define PREFIX_VEX_77 (PREFIX_VEX_76 + 1)
829 #define PREFIX_VEX_7C (PREFIX_VEX_77 + 1)
830 #define PREFIX_VEX_7D (PREFIX_VEX_7C + 1)
831 #define PREFIX_VEX_7E (PREFIX_VEX_7D + 1)
832 #define PREFIX_VEX_7F (PREFIX_VEX_7E + 1)
833 #define PREFIX_VEX_C2 (PREFIX_VEX_7F + 1)
834 #define PREFIX_VEX_C4 (PREFIX_VEX_C2 + 1)
835 #define PREFIX_VEX_C5 (PREFIX_VEX_C4 + 1)
836 #define PREFIX_VEX_D0 (PREFIX_VEX_C5 + 1)
837 #define PREFIX_VEX_D1 (PREFIX_VEX_D0 + 1)
838 #define PREFIX_VEX_D2 (PREFIX_VEX_D1 + 1)
839 #define PREFIX_VEX_D3 (PREFIX_VEX_D2 + 1)
840 #define PREFIX_VEX_D4 (PREFIX_VEX_D3 + 1)
841 #define PREFIX_VEX_D5 (PREFIX_VEX_D4 + 1)
842 #define PREFIX_VEX_D6 (PREFIX_VEX_D5 + 1)
843 #define PREFIX_VEX_D7 (PREFIX_VEX_D6 + 1)
844 #define PREFIX_VEX_D8 (PREFIX_VEX_D7 + 1)
845 #define PREFIX_VEX_D9 (PREFIX_VEX_D8 + 1)
846 #define PREFIX_VEX_DA (PREFIX_VEX_D9 + 1)
847 #define PREFIX_VEX_DB (PREFIX_VEX_DA + 1)
848 #define PREFIX_VEX_DC (PREFIX_VEX_DB + 1)
849 #define PREFIX_VEX_DD (PREFIX_VEX_DC + 1)
850 #define PREFIX_VEX_DE (PREFIX_VEX_DD + 1)
851 #define PREFIX_VEX_DF (PREFIX_VEX_DE + 1)
852 #define PREFIX_VEX_E0 (PREFIX_VEX_DF + 1)
853 #define PREFIX_VEX_E1 (PREFIX_VEX_E0 + 1)
854 #define PREFIX_VEX_E2 (PREFIX_VEX_E1 + 1)
855 #define PREFIX_VEX_E3 (PREFIX_VEX_E2 + 1)
856 #define PREFIX_VEX_E4 (PREFIX_VEX_E3 + 1)
857 #define PREFIX_VEX_E5 (PREFIX_VEX_E4 + 1)
858 #define PREFIX_VEX_E6 (PREFIX_VEX_E5 + 1)
859 #define PREFIX_VEX_E7 (PREFIX_VEX_E6 + 1)
860 #define PREFIX_VEX_E8 (PREFIX_VEX_E7 + 1)
861 #define PREFIX_VEX_E9 (PREFIX_VEX_E8 + 1)
862 #define PREFIX_VEX_EA (PREFIX_VEX_E9 + 1)
863 #define PREFIX_VEX_EB (PREFIX_VEX_EA + 1)
864 #define PREFIX_VEX_EC (PREFIX_VEX_EB + 1)
865 #define PREFIX_VEX_ED (PREFIX_VEX_EC + 1)
866 #define PREFIX_VEX_EE (PREFIX_VEX_ED + 1)
867 #define PREFIX_VEX_EF (PREFIX_VEX_EE + 1)
868 #define PREFIX_VEX_F0 (PREFIX_VEX_EF + 1)
869 #define PREFIX_VEX_F1 (PREFIX_VEX_F0 + 1)
870 #define PREFIX_VEX_F2 (PREFIX_VEX_F1 + 1)
871 #define PREFIX_VEX_F3 (PREFIX_VEX_F2 + 1)
872 #define PREFIX_VEX_F4 (PREFIX_VEX_F3 + 1)
873 #define PREFIX_VEX_F5 (PREFIX_VEX_F4 + 1)
874 #define PREFIX_VEX_F6 (PREFIX_VEX_F5 + 1)
875 #define PREFIX_VEX_F7 (PREFIX_VEX_F6 + 1)
876 #define PREFIX_VEX_F8 (PREFIX_VEX_F7 + 1)
877 #define PREFIX_VEX_F9 (PREFIX_VEX_F8 + 1)
878 #define PREFIX_VEX_FA (PREFIX_VEX_F9 + 1)
879 #define PREFIX_VEX_FB (PREFIX_VEX_FA + 1)
880 #define PREFIX_VEX_FC (PREFIX_VEX_FB + 1)
881 #define PREFIX_VEX_FD (PREFIX_VEX_FC + 1)
882 #define PREFIX_VEX_FE (PREFIX_VEX_FD + 1)
883 #define PREFIX_VEX_3800 (PREFIX_VEX_FE + 1)
884 #define PREFIX_VEX_3801 (PREFIX_VEX_3800 + 1)
885 #define PREFIX_VEX_3802 (PREFIX_VEX_3801 + 1)
886 #define PREFIX_VEX_3803 (PREFIX_VEX_3802 + 1)
887 #define PREFIX_VEX_3804 (PREFIX_VEX_3803 + 1)
888 #define PREFIX_VEX_3805 (PREFIX_VEX_3804 + 1)
889 #define PREFIX_VEX_3806 (PREFIX_VEX_3805 + 1)
890 #define PREFIX_VEX_3807 (PREFIX_VEX_3806 + 1)
891 #define PREFIX_VEX_3808 (PREFIX_VEX_3807 + 1)
892 #define PREFIX_VEX_3809 (PREFIX_VEX_3808 + 1)
893 #define PREFIX_VEX_380A (PREFIX_VEX_3809 + 1)
894 #define PREFIX_VEX_380B (PREFIX_VEX_380A + 1)
895 #define PREFIX_VEX_380C (PREFIX_VEX_380B + 1)
896 #define PREFIX_VEX_380D (PREFIX_VEX_380C + 1)
897 #define PREFIX_VEX_380E (PREFIX_VEX_380D + 1)
898 #define PREFIX_VEX_380F (PREFIX_VEX_380E + 1)
899 #define PREFIX_VEX_3817 (PREFIX_VEX_380F + 1)
900 #define PREFIX_VEX_3818 (PREFIX_VEX_3817 + 1)
901 #define PREFIX_VEX_3819 (PREFIX_VEX_3818 + 1)
902 #define PREFIX_VEX_381A (PREFIX_VEX_3819 + 1)
903 #define PREFIX_VEX_381C (PREFIX_VEX_381A + 1)
904 #define PREFIX_VEX_381D (PREFIX_VEX_381C + 1)
905 #define PREFIX_VEX_381E (PREFIX_VEX_381D + 1)
906 #define PREFIX_VEX_3820 (PREFIX_VEX_381E + 1)
907 #define PREFIX_VEX_3821 (PREFIX_VEX_3820 + 1)
908 #define PREFIX_VEX_3822 (PREFIX_VEX_3821 + 1)
909 #define PREFIX_VEX_3823 (PREFIX_VEX_3822 + 1)
910 #define PREFIX_VEX_3824 (PREFIX_VEX_3823 + 1)
911 #define PREFIX_VEX_3825 (PREFIX_VEX_3824 + 1)
912 #define PREFIX_VEX_3828 (PREFIX_VEX_3825 + 1)
913 #define PREFIX_VEX_3829 (PREFIX_VEX_3828 + 1)
914 #define PREFIX_VEX_382A (PREFIX_VEX_3829 + 1)
915 #define PREFIX_VEX_382B (PREFIX_VEX_382A + 1)
916 #define PREFIX_VEX_382C (PREFIX_VEX_382B + 1)
917 #define PREFIX_VEX_382D (PREFIX_VEX_382C + 1)
918 #define PREFIX_VEX_382E (PREFIX_VEX_382D + 1)
919 #define PREFIX_VEX_382F (PREFIX_VEX_382E + 1)
920 #define PREFIX_VEX_3830 (PREFIX_VEX_382F + 1)
921 #define PREFIX_VEX_3831 (PREFIX_VEX_3830 + 1)
922 #define PREFIX_VEX_3832 (PREFIX_VEX_3831 + 1)
923 #define PREFIX_VEX_3833 (PREFIX_VEX_3832 + 1)
924 #define PREFIX_VEX_3834 (PREFIX_VEX_3833 + 1)
925 #define PREFIX_VEX_3835 (PREFIX_VEX_3834 + 1)
926 #define PREFIX_VEX_3837 (PREFIX_VEX_3835 + 1)
927 #define PREFIX_VEX_3838 (PREFIX_VEX_3837 + 1)
928 #define PREFIX_VEX_3839 (PREFIX_VEX_3838 + 1)
929 #define PREFIX_VEX_383A (PREFIX_VEX_3839 + 1)
930 #define PREFIX_VEX_383B (PREFIX_VEX_383A + 1)
931 #define PREFIX_VEX_383C (PREFIX_VEX_383B + 1)
932 #define PREFIX_VEX_383D (PREFIX_VEX_383C + 1)
933 #define PREFIX_VEX_383E (PREFIX_VEX_383D + 1)
934 #define PREFIX_VEX_383F (PREFIX_VEX_383E + 1)
935 #define PREFIX_VEX_3840 (PREFIX_VEX_383F + 1)
936 #define PREFIX_VEX_3841 (PREFIX_VEX_3840 + 1)
937 #define PREFIX_VEX_3A04 (PREFIX_VEX_3841 + 1)
938 #define PREFIX_VEX_3A05 (PREFIX_VEX_3A04 + 1)
939 #define PREFIX_VEX_3A06 (PREFIX_VEX_3A05 + 1)
940 #define PREFIX_VEX_3A08 (PREFIX_VEX_3A06 + 1)
941 #define PREFIX_VEX_3A09 (PREFIX_VEX_3A08 + 1)
942 #define PREFIX_VEX_3A0A (PREFIX_VEX_3A09 + 1)
943 #define PREFIX_VEX_3A0B (PREFIX_VEX_3A0A + 1)
944 #define PREFIX_VEX_3A0C (PREFIX_VEX_3A0B + 1)
945 #define PREFIX_VEX_3A0D (PREFIX_VEX_3A0C + 1)
946 #define PREFIX_VEX_3A0E (PREFIX_VEX_3A0D + 1)
947 #define PREFIX_VEX_3A0F (PREFIX_VEX_3A0E + 1)
948 #define PREFIX_VEX_3A14 (PREFIX_VEX_3A0F + 1)
949 #define PREFIX_VEX_3A15 (PREFIX_VEX_3A14 + 1)
950 #define PREFIX_VEX_3A16 (PREFIX_VEX_3A15 + 1)
951 #define PREFIX_VEX_3A17 (PREFIX_VEX_3A16 + 1)
952 #define PREFIX_VEX_3A18 (PREFIX_VEX_3A17 + 1)
953 #define PREFIX_VEX_3A19 (PREFIX_VEX_3A18 + 1)
954 #define PREFIX_VEX_3A20 (PREFIX_VEX_3A19 + 1)
955 #define PREFIX_VEX_3A21 (PREFIX_VEX_3A20 + 1)
956 #define PREFIX_VEX_3A22 (PREFIX_VEX_3A21 + 1)
957 #define PREFIX_VEX_3A40 (PREFIX_VEX_3A22 + 1)
958 #define PREFIX_VEX_3A41 (PREFIX_VEX_3A40 + 1)
959 #define PREFIX_VEX_3A42 (PREFIX_VEX_3A41 + 1)
960 #define PREFIX_VEX_3A48 (PREFIX_VEX_3A42 + 1)
961 #define PREFIX_VEX_3A49 (PREFIX_VEX_3A48 + 1)
962 #define PREFIX_VEX_3A4A (PREFIX_VEX_3A49 + 1)
963 #define PREFIX_VEX_3A4B (PREFIX_VEX_3A4A + 1)
964 #define PREFIX_VEX_3A4C (PREFIX_VEX_3A4B + 1)
965 #define PREFIX_VEX_3A5C (PREFIX_VEX_3A4C + 1)
966 #define PREFIX_VEX_3A5D (PREFIX_VEX_3A5C + 1)
967 #define PREFIX_VEX_3A5E (PREFIX_VEX_3A5D + 1)
968 #define PREFIX_VEX_3A5F (PREFIX_VEX_3A5E + 1)
969 #define PREFIX_VEX_3A60 (PREFIX_VEX_3A5F + 1)
970 #define PREFIX_VEX_3A61 (PREFIX_VEX_3A60 + 1)
971 #define PREFIX_VEX_3A62 (PREFIX_VEX_3A61 + 1)
972 #define PREFIX_VEX_3A63 (PREFIX_VEX_3A62 + 1)
973 #define PREFIX_VEX_3A68 (PREFIX_VEX_3A63 + 1)
974 #define PREFIX_VEX_3A69 (PREFIX_VEX_3A68 + 1)
975 #define PREFIX_VEX_3A6A (PREFIX_VEX_3A69 + 1)
976 #define PREFIX_VEX_3A6B (PREFIX_VEX_3A6A + 1)
977 #define PREFIX_VEX_3A6C (PREFIX_VEX_3A6B + 1)
978 #define PREFIX_VEX_3A6D (PREFIX_VEX_3A6C + 1)
979 #define PREFIX_VEX_3A6E (PREFIX_VEX_3A6D + 1)
980 #define PREFIX_VEX_3A6F (PREFIX_VEX_3A6E + 1)
981 #define PREFIX_VEX_3A78 (PREFIX_VEX_3A6F + 1)
982 #define PREFIX_VEX_3A79 (PREFIX_VEX_3A78 + 1)
983 #define PREFIX_VEX_3A7A (PREFIX_VEX_3A79 + 1)
984 #define PREFIX_VEX_3A7B (PREFIX_VEX_3A7A + 1)
985 #define PREFIX_VEX_3A7C (PREFIX_VEX_3A7B + 1)
986 #define PREFIX_VEX_3A7D (PREFIX_VEX_3A7C + 1)
987 #define PREFIX_VEX_3A7E (PREFIX_VEX_3A7D + 1)
988 #define PREFIX_VEX_3A7F (PREFIX_VEX_3A7E + 1)
989
990 #define X86_64_06 0
991 #define X86_64_07 (X86_64_06 + 1)
992 #define X86_64_0D (X86_64_07 + 1)
993 #define X86_64_16 (X86_64_0D + 1)
994 #define X86_64_17 (X86_64_16 + 1)
995 #define X86_64_1E (X86_64_17 + 1)
996 #define X86_64_1F (X86_64_1E + 1)
997 #define X86_64_27 (X86_64_1F + 1)
998 #define X86_64_2F (X86_64_27 + 1)
999 #define X86_64_37 (X86_64_2F + 1)
1000 #define X86_64_3F (X86_64_37 + 1)
1001 #define X86_64_60 (X86_64_3F + 1)
1002 #define X86_64_61 (X86_64_60 + 1)
1003 #define X86_64_62 (X86_64_61 + 1)
1004 #define X86_64_63 (X86_64_62 + 1)
1005 #define X86_64_6D (X86_64_63 + 1)
1006 #define X86_64_6F (X86_64_6D + 1)
1007 #define X86_64_9A (X86_64_6F + 1)
1008 #define X86_64_C4 (X86_64_9A + 1)
1009 #define X86_64_C5 (X86_64_C4 + 1)
1010 #define X86_64_CE (X86_64_C5 + 1)
1011 #define X86_64_D4 (X86_64_CE + 1)
1012 #define X86_64_D5 (X86_64_D4 + 1)
1013 #define X86_64_EA (X86_64_D5 + 1)
1014 #define X86_64_0F01_REG_0 (X86_64_EA + 1)
1015 #define X86_64_0F01_REG_1 (X86_64_0F01_REG_0 + 1)
1016 #define X86_64_0F01_REG_2 (X86_64_0F01_REG_1 + 1)
1017 #define X86_64_0F01_REG_3 (X86_64_0F01_REG_2 + 1)
1018
1019 #define THREE_BYTE_0F24 0
1020 #define THREE_BYTE_0F25 (THREE_BYTE_0F24 + 1)
1021 #define THREE_BYTE_0F38 (THREE_BYTE_0F25 + 1)
1022 #define THREE_BYTE_0F3A (THREE_BYTE_0F38 + 1)
1023 #define THREE_BYTE_0F7A (THREE_BYTE_0F3A + 1)
1024 #define THREE_BYTE_0F7B (THREE_BYTE_0F7A + 1)
1025
1026 #define VEX_0F 0
1027 #define VEX_0F38 (VEX_0F + 1)
1028 #define VEX_0F3A (VEX_0F38 + 1)
1029
1030 #define VEX_LEN_10_P_1 0
1031 #define VEX_LEN_10_P_3 (VEX_LEN_10_P_1 + 1)
1032 #define VEX_LEN_11_P_1 (VEX_LEN_10_P_3 + 1)
1033 #define VEX_LEN_11_P_3 (VEX_LEN_11_P_1 + 1)
1034 #define VEX_LEN_12_P_0_M_0 (VEX_LEN_11_P_3 + 1)
1035 #define VEX_LEN_12_P_0_M_1 (VEX_LEN_12_P_0_M_0 + 1)
1036 #define VEX_LEN_12_P_2 (VEX_LEN_12_P_0_M_1 + 1)
1037 #define VEX_LEN_13_M_0 (VEX_LEN_12_P_2 + 1)
1038 #define VEX_LEN_16_P_0_M_0 (VEX_LEN_13_M_0 + 1)
1039 #define VEX_LEN_16_P_0_M_1 (VEX_LEN_16_P_0_M_0 + 1)
1040 #define VEX_LEN_16_P_2 (VEX_LEN_16_P_0_M_1 + 1)
1041 #define VEX_LEN_17_M_0 (VEX_LEN_16_P_2 + 1)
1042 #define VEX_LEN_2A_P_1 (VEX_LEN_17_M_0 + 1)
1043 #define VEX_LEN_2A_P_3 (VEX_LEN_2A_P_1 + 1)
1044 #define VEX_LEN_2B_M_0 (VEX_LEN_2A_P_3 + 1)
1045 #define VEX_LEN_2C_P_1 (VEX_LEN_2B_M_0 + 1)
1046 #define VEX_LEN_2C_P_3 (VEX_LEN_2C_P_1 + 1)
1047 #define VEX_LEN_2D_P_1 (VEX_LEN_2C_P_3 + 1)
1048 #define VEX_LEN_2D_P_3 (VEX_LEN_2D_P_1 + 1)
1049 #define VEX_LEN_2E_P_0 (VEX_LEN_2D_P_3 + 1)
1050 #define VEX_LEN_2E_P_2 (VEX_LEN_2E_P_0 + 1)
1051 #define VEX_LEN_2F_P_0 (VEX_LEN_2E_P_2 + 1)
1052 #define VEX_LEN_2F_P_2 (VEX_LEN_2F_P_0 + 1)
1053 #define VEX_LEN_51_P_1 (VEX_LEN_2F_P_2 + 1)
1054 #define VEX_LEN_51_P_3 (VEX_LEN_51_P_1 + 1)
1055 #define VEX_LEN_52_P_1 (VEX_LEN_51_P_3 + 1)
1056 #define VEX_LEN_53_P_1 (VEX_LEN_52_P_1 + 1)
1057 #define VEX_LEN_58_P_1 (VEX_LEN_53_P_1 + 1)
1058 #define VEX_LEN_58_P_3 (VEX_LEN_58_P_1 + 1)
1059 #define VEX_LEN_59_P_1 (VEX_LEN_58_P_3 + 1)
1060 #define VEX_LEN_59_P_3 (VEX_LEN_59_P_1 + 1)
1061 #define VEX_LEN_5A_P_1 (VEX_LEN_59_P_3 + 1)
1062 #define VEX_LEN_5A_P_3 (VEX_LEN_5A_P_1 + 1)
1063 #define VEX_LEN_5C_P_1 (VEX_LEN_5A_P_3 + 1)
1064 #define VEX_LEN_5C_P_3 (VEX_LEN_5C_P_1 + 1)
1065 #define VEX_LEN_5D_P_1 (VEX_LEN_5C_P_3 + 1)
1066 #define VEX_LEN_5D_P_3 (VEX_LEN_5D_P_1 + 1)
1067 #define VEX_LEN_5E_P_1 (VEX_LEN_5D_P_3 + 1)
1068 #define VEX_LEN_5E_P_3 (VEX_LEN_5E_P_1 + 1)
1069 #define VEX_LEN_5F_P_1 (VEX_LEN_5E_P_3 + 1)
1070 #define VEX_LEN_5F_P_3 (VEX_LEN_5F_P_1 + 1)
1071 #define VEX_LEN_60_P_2 (VEX_LEN_5F_P_3 + 1)
1072 #define VEX_LEN_61_P_2 (VEX_LEN_60_P_2 + 1)
1073 #define VEX_LEN_62_P_2 (VEX_LEN_61_P_2 + 1)
1074 #define VEX_LEN_63_P_2 (VEX_LEN_62_P_2 + 1)
1075 #define VEX_LEN_64_P_2 (VEX_LEN_63_P_2 + 1)
1076 #define VEX_LEN_65_P_2 (VEX_LEN_64_P_2 + 1)
1077 #define VEX_LEN_66_P_2 (VEX_LEN_65_P_2 + 1)
1078 #define VEX_LEN_67_P_2 (VEX_LEN_66_P_2 + 1)
1079 #define VEX_LEN_68_P_2 (VEX_LEN_67_P_2 + 1)
1080 #define VEX_LEN_69_P_2 (VEX_LEN_68_P_2 + 1)
1081 #define VEX_LEN_6A_P_2 (VEX_LEN_69_P_2 + 1)
1082 #define VEX_LEN_6B_P_2 (VEX_LEN_6A_P_2 + 1)
1083 #define VEX_LEN_6C_P_2 (VEX_LEN_6B_P_2 + 1)
1084 #define VEX_LEN_6D_P_2 (VEX_LEN_6C_P_2 + 1)
1085 #define VEX_LEN_6E_P_2 (VEX_LEN_6D_P_2 + 1)
1086 #define VEX_LEN_70_P_1 (VEX_LEN_6E_P_2 + 1)
1087 #define VEX_LEN_70_P_2 (VEX_LEN_70_P_1 + 1)
1088 #define VEX_LEN_70_P_3 (VEX_LEN_70_P_2 + 1)
1089 #define VEX_LEN_71_R_2_P_2 (VEX_LEN_70_P_3 + 1)
1090 #define VEX_LEN_71_R_4_P_2 (VEX_LEN_71_R_2_P_2 + 1)
1091 #define VEX_LEN_71_R_6_P_2 (VEX_LEN_71_R_4_P_2 + 1)
1092 #define VEX_LEN_72_R_2_P_2 (VEX_LEN_71_R_6_P_2 + 1)
1093 #define VEX_LEN_72_R_4_P_2 (VEX_LEN_72_R_2_P_2 + 1)
1094 #define VEX_LEN_72_R_6_P_2 (VEX_LEN_72_R_4_P_2 + 1)
1095 #define VEX_LEN_73_R_2_P_2 (VEX_LEN_72_R_6_P_2 + 1)
1096 #define VEX_LEN_73_R_3_P_2 (VEX_LEN_73_R_2_P_2 + 1)
1097 #define VEX_LEN_73_R_6_P_2 (VEX_LEN_73_R_3_P_2 + 1)
1098 #define VEX_LEN_73_R_7_P_2 (VEX_LEN_73_R_6_P_2 + 1)
1099 #define VEX_LEN_74_P_2 (VEX_LEN_73_R_7_P_2 + 1)
1100 #define VEX_LEN_75_P_2 (VEX_LEN_74_P_2 + 1)
1101 #define VEX_LEN_76_P_2 (VEX_LEN_75_P_2 + 1)
1102 #define VEX_LEN_7E_P_1 (VEX_LEN_76_P_2 + 1)
1103 #define VEX_LEN_7E_P_2 (VEX_LEN_7E_P_1 + 1)
1104 #define VEX_LEN_AE_R_2_M_0 (VEX_LEN_7E_P_2 + 1)
1105 #define VEX_LEN_AE_R_3_M_0 (VEX_LEN_AE_R_2_M_0 + 1)
1106 #define VEX_LEN_C2_P_1 (VEX_LEN_AE_R_3_M_0 + 1)
1107 #define VEX_LEN_C2_P_3 (VEX_LEN_C2_P_1 + 1)
1108 #define VEX_LEN_C4_P_2 (VEX_LEN_C2_P_3 + 1)
1109 #define VEX_LEN_C5_P_2 (VEX_LEN_C4_P_2 + 1)
1110 #define VEX_LEN_D1_P_2 (VEX_LEN_C5_P_2 + 1)
1111 #define VEX_LEN_D2_P_2 (VEX_LEN_D1_P_2 + 1)
1112 #define VEX_LEN_D3_P_2 (VEX_LEN_D2_P_2 + 1)
1113 #define VEX_LEN_D4_P_2 (VEX_LEN_D3_P_2 + 1)
1114 #define VEX_LEN_D5_P_2 (VEX_LEN_D4_P_2 + 1)
1115 #define VEX_LEN_D6_P_2 (VEX_LEN_D5_P_2 + 1)
1116 #define VEX_LEN_D7_P_2_M_1 (VEX_LEN_D6_P_2 + 1)
1117 #define VEX_LEN_D8_P_2 (VEX_LEN_D7_P_2_M_1 + 1)
1118 #define VEX_LEN_D9_P_2 (VEX_LEN_D8_P_2 + 1)
1119 #define VEX_LEN_DA_P_2 (VEX_LEN_D9_P_2 + 1)
1120 #define VEX_LEN_DB_P_2 (VEX_LEN_DA_P_2 + 1)
1121 #define VEX_LEN_DC_P_2 (VEX_LEN_DB_P_2 + 1)
1122 #define VEX_LEN_DD_P_2 (VEX_LEN_DC_P_2 + 1)
1123 #define VEX_LEN_DE_P_2 (VEX_LEN_DD_P_2 + 1)
1124 #define VEX_LEN_DF_P_2 (VEX_LEN_DE_P_2 + 1)
1125 #define VEX_LEN_E0_P_2 (VEX_LEN_DF_P_2 + 1)
1126 #define VEX_LEN_E1_P_2 (VEX_LEN_E0_P_2 + 1)
1127 #define VEX_LEN_E2_P_2 (VEX_LEN_E1_P_2 + 1)
1128 #define VEX_LEN_E3_P_2 (VEX_LEN_E2_P_2 + 1)
1129 #define VEX_LEN_E4_P_2 (VEX_LEN_E3_P_2 + 1)
1130 #define VEX_LEN_E5_P_2 (VEX_LEN_E4_P_2 + 1)
1131 #define VEX_LEN_E7_P_2_M_0 (VEX_LEN_E5_P_2 + 1)
1132 #define VEX_LEN_E8_P_2 (VEX_LEN_E7_P_2_M_0 + 1)
1133 #define VEX_LEN_E9_P_2 (VEX_LEN_E8_P_2 + 1)
1134 #define VEX_LEN_EA_P_2 (VEX_LEN_E9_P_2 + 1)
1135 #define VEX_LEN_EB_P_2 (VEX_LEN_EA_P_2 + 1)
1136 #define VEX_LEN_EC_P_2 (VEX_LEN_EB_P_2 + 1)
1137 #define VEX_LEN_ED_P_2 (VEX_LEN_EC_P_2 + 1)
1138 #define VEX_LEN_EE_P_2 (VEX_LEN_ED_P_2 + 1)
1139 #define VEX_LEN_EF_P_2 (VEX_LEN_EE_P_2 + 1)
1140 #define VEX_LEN_F1_P_2 (VEX_LEN_EF_P_2 + 1)
1141 #define VEX_LEN_F2_P_2 (VEX_LEN_F1_P_2 + 1)
1142 #define VEX_LEN_F3_P_2 (VEX_LEN_F2_P_2 + 1)
1143 #define VEX_LEN_F4_P_2 (VEX_LEN_F3_P_2 + 1)
1144 #define VEX_LEN_F5_P_2 (VEX_LEN_F4_P_2 + 1)
1145 #define VEX_LEN_F6_P_2 (VEX_LEN_F5_P_2 + 1)
1146 #define VEX_LEN_F7_P_2 (VEX_LEN_F6_P_2 + 1)
1147 #define VEX_LEN_F8_P_2 (VEX_LEN_F7_P_2 + 1)
1148 #define VEX_LEN_F9_P_2 (VEX_LEN_F8_P_2 + 1)
1149 #define VEX_LEN_FA_P_2 (VEX_LEN_F9_P_2 + 1)
1150 #define VEX_LEN_FB_P_2 (VEX_LEN_FA_P_2 + 1)
1151 #define VEX_LEN_FC_P_2 (VEX_LEN_FB_P_2 + 1)
1152 #define VEX_LEN_FD_P_2 (VEX_LEN_FC_P_2 + 1)
1153 #define VEX_LEN_FE_P_2 (VEX_LEN_FD_P_2 + 1)
1154 #define VEX_LEN_3800_P_2 (VEX_LEN_FE_P_2 + 1)
1155 #define VEX_LEN_3801_P_2 (VEX_LEN_3800_P_2 + 1)
1156 #define VEX_LEN_3802_P_2 (VEX_LEN_3801_P_2 + 1)
1157 #define VEX_LEN_3803_P_2 (VEX_LEN_3802_P_2 + 1)
1158 #define VEX_LEN_3804_P_2 (VEX_LEN_3803_P_2 + 1)
1159 #define VEX_LEN_3805_P_2 (VEX_LEN_3804_P_2 + 1)
1160 #define VEX_LEN_3806_P_2 (VEX_LEN_3805_P_2 + 1)
1161 #define VEX_LEN_3807_P_2 (VEX_LEN_3806_P_2 + 1)
1162 #define VEX_LEN_3808_P_2 (VEX_LEN_3807_P_2 + 1)
1163 #define VEX_LEN_3809_P_2 (VEX_LEN_3808_P_2 + 1)
1164 #define VEX_LEN_380A_P_2 (VEX_LEN_3809_P_2 + 1)
1165 #define VEX_LEN_380B_P_2 (VEX_LEN_380A_P_2 + 1)
1166 #define VEX_LEN_3819_P_2_M_0 (VEX_LEN_380B_P_2 + 1)
1167 #define VEX_LEN_381A_P_2_M_0 (VEX_LEN_3819_P_2_M_0 + 1)
1168 #define VEX_LEN_381C_P_2 (VEX_LEN_381A_P_2_M_0 + 1)
1169 #define VEX_LEN_381D_P_2 (VEX_LEN_381C_P_2 + 1)
1170 #define VEX_LEN_381E_P_2 (VEX_LEN_381D_P_2 + 1)
1171 #define VEX_LEN_3820_P_2 (VEX_LEN_381E_P_2 + 1)
1172 #define VEX_LEN_3821_P_2 (VEX_LEN_3820_P_2 + 1)
1173 #define VEX_LEN_3822_P_2 (VEX_LEN_3821_P_2 + 1)
1174 #define VEX_LEN_3823_P_2 (VEX_LEN_3822_P_2 + 1)
1175 #define VEX_LEN_3824_P_2 (VEX_LEN_3823_P_2 + 1)
1176 #define VEX_LEN_3825_P_2 (VEX_LEN_3824_P_2 + 1)
1177 #define VEX_LEN_3828_P_2 (VEX_LEN_3825_P_2 + 1)
1178 #define VEX_LEN_3829_P_2 (VEX_LEN_3828_P_2 + 1)
1179 #define VEX_LEN_382A_P_2_M_0 (VEX_LEN_3829_P_2 + 1)
1180 #define VEX_LEN_382B_P_2 (VEX_LEN_382A_P_2_M_0 + 1)
1181 #define VEX_LEN_3830_P_2 (VEX_LEN_382B_P_2 + 1)
1182 #define VEX_LEN_3831_P_2 (VEX_LEN_3830_P_2 + 1)
1183 #define VEX_LEN_3832_P_2 (VEX_LEN_3831_P_2 + 1)
1184 #define VEX_LEN_3833_P_2 (VEX_LEN_3832_P_2 + 1)
1185 #define VEX_LEN_3834_P_2 (VEX_LEN_3833_P_2 + 1)
1186 #define VEX_LEN_3835_P_2 (VEX_LEN_3834_P_2 + 1)
1187 #define VEX_LEN_3837_P_2 (VEX_LEN_3835_P_2 + 1)
1188 #define VEX_LEN_3838_P_2 (VEX_LEN_3837_P_2 + 1)
1189 #define VEX_LEN_3839_P_2 (VEX_LEN_3838_P_2 + 1)
1190 #define VEX_LEN_383A_P_2 (VEX_LEN_3839_P_2 + 1)
1191 #define VEX_LEN_383B_P_2 (VEX_LEN_383A_P_2 + 1)
1192 #define VEX_LEN_383C_P_2 (VEX_LEN_383B_P_2 + 1)
1193 #define VEX_LEN_383D_P_2 (VEX_LEN_383C_P_2 + 1)
1194 #define VEX_LEN_383E_P_2 (VEX_LEN_383D_P_2 + 1)
1195 #define VEX_LEN_383F_P_2 (VEX_LEN_383E_P_2 + 1)
1196 #define VEX_LEN_3840_P_2 (VEX_LEN_383F_P_2 + 1)
1197 #define VEX_LEN_3841_P_2 (VEX_LEN_3840_P_2 + 1)
1198 #define VEX_LEN_3A06_P_2 (VEX_LEN_3841_P_2 + 1)
1199 #define VEX_LEN_3A0A_P_2 (VEX_LEN_3A06_P_2 + 1)
1200 #define VEX_LEN_3A0B_P_2 (VEX_LEN_3A0A_P_2 + 1)
1201 #define VEX_LEN_3A0E_P_2 (VEX_LEN_3A0B_P_2 + 1)
1202 #define VEX_LEN_3A0F_P_2 (VEX_LEN_3A0E_P_2 + 1)
1203 #define VEX_LEN_3A14_P_2 (VEX_LEN_3A0F_P_2 + 1)
1204 #define VEX_LEN_3A15_P_2 (VEX_LEN_3A14_P_2 + 1)
1205 #define VEX_LEN_3A16_P_2 (VEX_LEN_3A15_P_2 + 1)
1206 #define VEX_LEN_3A17_P_2 (VEX_LEN_3A16_P_2 + 1)
1207 #define VEX_LEN_3A18_P_2 (VEX_LEN_3A17_P_2 + 1)
1208 #define VEX_LEN_3A19_P_2 (VEX_LEN_3A18_P_2 + 1)
1209 #define VEX_LEN_3A20_P_2 (VEX_LEN_3A19_P_2 + 1)
1210 #define VEX_LEN_3A21_P_2 (VEX_LEN_3A20_P_2 + 1)
1211 #define VEX_LEN_3A22_P_2 (VEX_LEN_3A21_P_2 + 1)
1212 #define VEX_LEN_3A41_P_2 (VEX_LEN_3A22_P_2 + 1)
1213 #define VEX_LEN_3A42_P_2 (VEX_LEN_3A41_P_2 + 1)
1214 #define VEX_LEN_3A4C_P_2 (VEX_LEN_3A42_P_2 + 1)
1215 #define VEX_LEN_3A60_P_2 (VEX_LEN_3A4C_P_2 + 1)
1216 #define VEX_LEN_3A61_P_2 (VEX_LEN_3A60_P_2 + 1)
1217 #define VEX_LEN_3A62_P_2 (VEX_LEN_3A61_P_2 + 1)
1218 #define VEX_LEN_3A63_P_2 (VEX_LEN_3A62_P_2 + 1)
1219 #define VEX_LEN_3A6A_P_2 (VEX_LEN_3A63_P_2 + 1)
1220 #define VEX_LEN_3A6B_P_2 (VEX_LEN_3A6A_P_2 + 1)
1221 #define VEX_LEN_3A6E_P_2 (VEX_LEN_3A6B_P_2 + 1)
1222 #define VEX_LEN_3A6F_P_2 (VEX_LEN_3A6E_P_2 + 1)
1223 #define VEX_LEN_3A7A_P_2 (VEX_LEN_3A6F_P_2 + 1)
1224 #define VEX_LEN_3A7B_P_2 (VEX_LEN_3A7A_P_2 + 1)
1225 #define VEX_LEN_3A7E_P_2 (VEX_LEN_3A7B_P_2 + 1)
1226 #define VEX_LEN_3A7F_P_2 (VEX_LEN_3A7E_P_2 + 1)
1227
1228 typedef void (*op_rtn) (int bytemode, int sizeflag);
1229
1230 struct dis386 {
1231 const char *name;
1232 struct
1233 {
1234 op_rtn rtn;
1235 int bytemode;
1236 } op[MAX_OPERANDS];
1237 };
1238
1239 /* Upper case letters in the instruction names here are macros.
1240 'A' => print 'b' if no register operands or suffix_always is true
1241 'B' => print 'b' if suffix_always is true
1242 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1243 size prefix
1244 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1245 suffix_always is true
1246 'E' => print 'e' if 32-bit form of jcxz
1247 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1248 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1249 'H' => print ",pt" or ",pn" branch hint
1250 'I' => honor following macro letter even in Intel mode (implemented only
1251 for some of the macro letters)
1252 'J' => print 'l'
1253 'K' => print 'd' or 'q' if rex prefix is present.
1254 'L' => print 'l' if suffix_always is true
1255 'M' => print 'r' if intel_mnemonic is false.
1256 'N' => print 'n' if instruction has no wait "prefix"
1257 'O' => print 'd' or 'o' (or 'q' in Intel mode)
1258 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
1259 or suffix_always is true. print 'q' if rex prefix is present.
1260 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1261 is true
1262 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1263 'S' => print 'w', 'l' or 'q' if suffix_always is true
1264 'T' => print 'q' in 64bit mode and behave as 'P' otherwise
1265 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
1266 'V' => print 'q' in 64bit mode and behave as 'S' otherwise
1267 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1268 'X' => print 's', 'd' depending on data16 prefix (for XMM)
1269 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
1270 suffix_always is true.
1271 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
1272 '!' => change condition from true to false or from false to true.
1273 '%' => add 1 upper case letter to the macro.
1274
1275 2 upper case letter macros:
1276 "XY" => print 'x' or 'y' if no register operands or suffix_always
1277 is true.
1278 'LQ' => print 'l' ('d' in Intel mode) or 'q' for memory operand
1279 or suffix_always is true
1280
1281 Many of the above letters print nothing in Intel mode. See "putop"
1282 for the details.
1283
1284 Braces '{' and '}', and vertical bars '|', indicate alternative
1285 mnemonic strings for AT&T and Intel. */
1286
1287 static const struct dis386 dis386[] = {
1288 /* 00 */
1289 { "addB", { Eb, Gb } },
1290 { "addS", { Ev, Gv } },
1291 { "addB", { Gb, Eb } },
1292 { "addS", { Gv, Ev } },
1293 { "addB", { AL, Ib } },
1294 { "addS", { eAX, Iv } },
1295 { X86_64_TABLE (X86_64_06) },
1296 { X86_64_TABLE (X86_64_07) },
1297 /* 08 */
1298 { "orB", { Eb, Gb } },
1299 { "orS", { Ev, Gv } },
1300 { "orB", { Gb, Eb } },
1301 { "orS", { Gv, Ev } },
1302 { "orB", { AL, Ib } },
1303 { "orS", { eAX, Iv } },
1304 { X86_64_TABLE (X86_64_0D) },
1305 { "(bad)", { XX } }, /* 0x0f extended opcode escape */
1306 /* 10 */
1307 { "adcB", { Eb, Gb } },
1308 { "adcS", { Ev, Gv } },
1309 { "adcB", { Gb, Eb } },
1310 { "adcS", { Gv, Ev } },
1311 { "adcB", { AL, Ib } },
1312 { "adcS", { eAX, Iv } },
1313 { X86_64_TABLE (X86_64_16) },
1314 { X86_64_TABLE (X86_64_17) },
1315 /* 18 */
1316 { "sbbB", { Eb, Gb } },
1317 { "sbbS", { Ev, Gv } },
1318 { "sbbB", { Gb, Eb } },
1319 { "sbbS", { Gv, Ev } },
1320 { "sbbB", { AL, Ib } },
1321 { "sbbS", { eAX, Iv } },
1322 { X86_64_TABLE (X86_64_1E) },
1323 { X86_64_TABLE (X86_64_1F) },
1324 /* 20 */
1325 { "andB", { Eb, Gb } },
1326 { "andS", { Ev, Gv } },
1327 { "andB", { Gb, Eb } },
1328 { "andS", { Gv, Ev } },
1329 { "andB", { AL, Ib } },
1330 { "andS", { eAX, Iv } },
1331 { "(bad)", { XX } }, /* SEG ES prefix */
1332 { X86_64_TABLE (X86_64_27) },
1333 /* 28 */
1334 { "subB", { Eb, Gb } },
1335 { "subS", { Ev, Gv } },
1336 { "subB", { Gb, Eb } },
1337 { "subS", { Gv, Ev } },
1338 { "subB", { AL, Ib } },
1339 { "subS", { eAX, Iv } },
1340 { "(bad)", { XX } }, /* SEG CS prefix */
1341 { X86_64_TABLE (X86_64_2F) },
1342 /* 30 */
1343 { "xorB", { Eb, Gb } },
1344 { "xorS", { Ev, Gv } },
1345 { "xorB", { Gb, Eb } },
1346 { "xorS", { Gv, Ev } },
1347 { "xorB", { AL, Ib } },
1348 { "xorS", { eAX, Iv } },
1349 { "(bad)", { XX } }, /* SEG SS prefix */
1350 { X86_64_TABLE (X86_64_37) },
1351 /* 38 */
1352 { "cmpB", { Eb, Gb } },
1353 { "cmpS", { Ev, Gv } },
1354 { "cmpB", { Gb, Eb } },
1355 { "cmpS", { Gv, Ev } },
1356 { "cmpB", { AL, Ib } },
1357 { "cmpS", { eAX, Iv } },
1358 { "(bad)", { XX } }, /* SEG DS prefix */
1359 { X86_64_TABLE (X86_64_3F) },
1360 /* 40 */
1361 { "inc{S|}", { RMeAX } },
1362 { "inc{S|}", { RMeCX } },
1363 { "inc{S|}", { RMeDX } },
1364 { "inc{S|}", { RMeBX } },
1365 { "inc{S|}", { RMeSP } },
1366 { "inc{S|}", { RMeBP } },
1367 { "inc{S|}", { RMeSI } },
1368 { "inc{S|}", { RMeDI } },
1369 /* 48 */
1370 { "dec{S|}", { RMeAX } },
1371 { "dec{S|}", { RMeCX } },
1372 { "dec{S|}", { RMeDX } },
1373 { "dec{S|}", { RMeBX } },
1374 { "dec{S|}", { RMeSP } },
1375 { "dec{S|}", { RMeBP } },
1376 { "dec{S|}", { RMeSI } },
1377 { "dec{S|}", { RMeDI } },
1378 /* 50 */
1379 { "pushV", { RMrAX } },
1380 { "pushV", { RMrCX } },
1381 { "pushV", { RMrDX } },
1382 { "pushV", { RMrBX } },
1383 { "pushV", { RMrSP } },
1384 { "pushV", { RMrBP } },
1385 { "pushV", { RMrSI } },
1386 { "pushV", { RMrDI } },
1387 /* 58 */
1388 { "popV", { RMrAX } },
1389 { "popV", { RMrCX } },
1390 { "popV", { RMrDX } },
1391 { "popV", { RMrBX } },
1392 { "popV", { RMrSP } },
1393 { "popV", { RMrBP } },
1394 { "popV", { RMrSI } },
1395 { "popV", { RMrDI } },
1396 /* 60 */
1397 { X86_64_TABLE (X86_64_60) },
1398 { X86_64_TABLE (X86_64_61) },
1399 { X86_64_TABLE (X86_64_62) },
1400 { X86_64_TABLE (X86_64_63) },
1401 { "(bad)", { XX } }, /* seg fs */
1402 { "(bad)", { XX } }, /* seg gs */
1403 { "(bad)", { XX } }, /* op size prefix */
1404 { "(bad)", { XX } }, /* adr size prefix */
1405 /* 68 */
1406 { "pushT", { Iq } },
1407 { "imulS", { Gv, Ev, Iv } },
1408 { "pushT", { sIb } },
1409 { "imulS", { Gv, Ev, sIb } },
1410 { "ins{b|}", { Ybr, indirDX } },
1411 { X86_64_TABLE (X86_64_6D) },
1412 { "outs{b|}", { indirDXr, Xb } },
1413 { X86_64_TABLE (X86_64_6F) },
1414 /* 70 */
1415 { "joH", { Jb, XX, cond_jump_flag } },
1416 { "jnoH", { Jb, XX, cond_jump_flag } },
1417 { "jbH", { Jb, XX, cond_jump_flag } },
1418 { "jaeH", { Jb, XX, cond_jump_flag } },
1419 { "jeH", { Jb, XX, cond_jump_flag } },
1420 { "jneH", { Jb, XX, cond_jump_flag } },
1421 { "jbeH", { Jb, XX, cond_jump_flag } },
1422 { "jaH", { Jb, XX, cond_jump_flag } },
1423 /* 78 */
1424 { "jsH", { Jb, XX, cond_jump_flag } },
1425 { "jnsH", { Jb, XX, cond_jump_flag } },
1426 { "jpH", { Jb, XX, cond_jump_flag } },
1427 { "jnpH", { Jb, XX, cond_jump_flag } },
1428 { "jlH", { Jb, XX, cond_jump_flag } },
1429 { "jgeH", { Jb, XX, cond_jump_flag } },
1430 { "jleH", { Jb, XX, cond_jump_flag } },
1431 { "jgH", { Jb, XX, cond_jump_flag } },
1432 /* 80 */
1433 { REG_TABLE (REG_80) },
1434 { REG_TABLE (REG_81) },
1435 { "(bad)", { XX } },
1436 { REG_TABLE (REG_82) },
1437 { "testB", { Eb, Gb } },
1438 { "testS", { Ev, Gv } },
1439 { "xchgB", { Eb, Gb } },
1440 { "xchgS", { Ev, Gv } },
1441 /* 88 */
1442 { "movB", { Eb, Gb } },
1443 { "movS", { Ev, Gv } },
1444 { "movB", { Gb, Eb } },
1445 { "movS", { Gv, Ev } },
1446 { "movD", { Sv, Sw } },
1447 { MOD_TABLE (MOD_8D) },
1448 { "movD", { Sw, Sv } },
1449 { REG_TABLE (REG_8F) },
1450 /* 90 */
1451 { PREFIX_TABLE (PREFIX_90) },
1452 { "xchgS", { RMeCX, eAX } },
1453 { "xchgS", { RMeDX, eAX } },
1454 { "xchgS", { RMeBX, eAX } },
1455 { "xchgS", { RMeSP, eAX } },
1456 { "xchgS", { RMeBP, eAX } },
1457 { "xchgS", { RMeSI, eAX } },
1458 { "xchgS", { RMeDI, eAX } },
1459 /* 98 */
1460 { "cW{t|}R", { XX } },
1461 { "cR{t|}O", { XX } },
1462 { X86_64_TABLE (X86_64_9A) },
1463 { "(bad)", { XX } }, /* fwait */
1464 { "pushfT", { XX } },
1465 { "popfT", { XX } },
1466 { "sahf", { XX } },
1467 { "lahf", { XX } },
1468 /* a0 */
1469 { "movB", { AL, Ob } },
1470 { "movS", { eAX, Ov } },
1471 { "movB", { Ob, AL } },
1472 { "movS", { Ov, eAX } },
1473 { "movs{b|}", { Ybr, Xb } },
1474 { "movs{R|}", { Yvr, Xv } },
1475 { "cmps{b|}", { Xb, Yb } },
1476 { "cmps{R|}", { Xv, Yv } },
1477 /* a8 */
1478 { "testB", { AL, Ib } },
1479 { "testS", { eAX, Iv } },
1480 { "stosB", { Ybr, AL } },
1481 { "stosS", { Yvr, eAX } },
1482 { "lodsB", { ALr, Xb } },
1483 { "lodsS", { eAXr, Xv } },
1484 { "scasB", { AL, Yb } },
1485 { "scasS", { eAX, Yv } },
1486 /* b0 */
1487 { "movB", { RMAL, Ib } },
1488 { "movB", { RMCL, Ib } },
1489 { "movB", { RMDL, Ib } },
1490 { "movB", { RMBL, Ib } },
1491 { "movB", { RMAH, Ib } },
1492 { "movB", { RMCH, Ib } },
1493 { "movB", { RMDH, Ib } },
1494 { "movB", { RMBH, Ib } },
1495 /* b8 */
1496 { "movS", { RMeAX, Iv64 } },
1497 { "movS", { RMeCX, Iv64 } },
1498 { "movS", { RMeDX, Iv64 } },
1499 { "movS", { RMeBX, Iv64 } },
1500 { "movS", { RMeSP, Iv64 } },
1501 { "movS", { RMeBP, Iv64 } },
1502 { "movS", { RMeSI, Iv64 } },
1503 { "movS", { RMeDI, Iv64 } },
1504 /* c0 */
1505 { REG_TABLE (REG_C0) },
1506 { REG_TABLE (REG_C1) },
1507 { "retT", { Iw } },
1508 { "retT", { XX } },
1509 { X86_64_TABLE (X86_64_C4) },
1510 { X86_64_TABLE (X86_64_C5) },
1511 { REG_TABLE (REG_C6) },
1512 { REG_TABLE (REG_C7) },
1513 /* c8 */
1514 { "enterT", { Iw, Ib } },
1515 { "leaveT", { XX } },
1516 { "lretP", { Iw } },
1517 { "lretP", { XX } },
1518 { "int3", { XX } },
1519 { "int", { Ib } },
1520 { X86_64_TABLE (X86_64_CE) },
1521 { "iretP", { XX } },
1522 /* d0 */
1523 { REG_TABLE (REG_D0) },
1524 { REG_TABLE (REG_D1) },
1525 { REG_TABLE (REG_D2) },
1526 { REG_TABLE (REG_D3) },
1527 { X86_64_TABLE (X86_64_D4) },
1528 { X86_64_TABLE (X86_64_D5) },
1529 { "(bad)", { XX } },
1530 { "xlat", { DSBX } },
1531 /* d8 */
1532 { FLOAT },
1533 { FLOAT },
1534 { FLOAT },
1535 { FLOAT },
1536 { FLOAT },
1537 { FLOAT },
1538 { FLOAT },
1539 { FLOAT },
1540 /* e0 */
1541 { "loopneFH", { Jb, XX, loop_jcxz_flag } },
1542 { "loopeFH", { Jb, XX, loop_jcxz_flag } },
1543 { "loopFH", { Jb, XX, loop_jcxz_flag } },
1544 { "jEcxzH", { Jb, XX, loop_jcxz_flag } },
1545 { "inB", { AL, Ib } },
1546 { "inG", { zAX, Ib } },
1547 { "outB", { Ib, AL } },
1548 { "outG", { Ib, zAX } },
1549 /* e8 */
1550 { "callT", { Jv } },
1551 { "jmpT", { Jv } },
1552 { X86_64_TABLE (X86_64_EA) },
1553 { "jmp", { Jb } },
1554 { "inB", { AL, indirDX } },
1555 { "inG", { zAX, indirDX } },
1556 { "outB", { indirDX, AL } },
1557 { "outG", { indirDX, zAX } },
1558 /* f0 */
1559 { "(bad)", { XX } }, /* lock prefix */
1560 { "icebp", { XX } },
1561 { "(bad)", { XX } }, /* repne */
1562 { "(bad)", { XX } }, /* repz */
1563 { "hlt", { XX } },
1564 { "cmc", { XX } },
1565 { REG_TABLE (REG_F6) },
1566 { REG_TABLE (REG_F7) },
1567 /* f8 */
1568 { "clc", { XX } },
1569 { "stc", { XX } },
1570 { "cli", { XX } },
1571 { "sti", { XX } },
1572 { "cld", { XX } },
1573 { "std", { XX } },
1574 { REG_TABLE (REG_FE) },
1575 { REG_TABLE (REG_FF) },
1576 };
1577
1578 static const struct dis386 dis386_twobyte[] = {
1579 /* 00 */
1580 { REG_TABLE (REG_0F00 ) },
1581 { REG_TABLE (REG_0F01 ) },
1582 { "larS", { Gv, Ew } },
1583 { "lslS", { Gv, Ew } },
1584 { "(bad)", { XX } },
1585 { "syscall", { XX } },
1586 { "clts", { XX } },
1587 { "sysretP", { XX } },
1588 /* 08 */
1589 { "invd", { XX } },
1590 { "wbinvd", { XX } },
1591 { "(bad)", { XX } },
1592 { "ud2a", { XX } },
1593 { "(bad)", { XX } },
1594 { REG_TABLE (REG_0F0D) },
1595 { "femms", { XX } },
1596 { "", { MX, EM, OPSUF } }, /* See OP_3DNowSuffix. */
1597 /* 10 */
1598 { PREFIX_TABLE (PREFIX_0F10) },
1599 { PREFIX_TABLE (PREFIX_0F11) },
1600 { PREFIX_TABLE (PREFIX_0F12) },
1601 { MOD_TABLE (MOD_0F13) },
1602 { "unpcklpX", { XM, EXx } },
1603 { "unpckhpX", { XM, EXx } },
1604 { PREFIX_TABLE (PREFIX_0F16) },
1605 { MOD_TABLE (MOD_0F17) },
1606 /* 18 */
1607 { REG_TABLE (REG_0F18) },
1608 { "nopQ", { Ev } },
1609 { "nopQ", { Ev } },
1610 { "nopQ", { Ev } },
1611 { "nopQ", { Ev } },
1612 { "nopQ", { Ev } },
1613 { "nopQ", { Ev } },
1614 { "nopQ", { Ev } },
1615 /* 20 */
1616 { MOD_TABLE (MOD_0F20) },
1617 { MOD_TABLE (MOD_0F21) },
1618 { MOD_TABLE (MOD_0F22) },
1619 { MOD_TABLE (MOD_0F23) },
1620 { MOD_TABLE (MOD_0F24) },
1621 { THREE_BYTE_TABLE (THREE_BYTE_0F25) },
1622 { MOD_TABLE (MOD_0F26) },
1623 { "(bad)", { XX } },
1624 /* 28 */
1625 { "movapX", { XM, EXx } },
1626 { "movapX", { EXx, XM } },
1627 { PREFIX_TABLE (PREFIX_0F2A) },
1628 { PREFIX_TABLE (PREFIX_0F2B) },
1629 { PREFIX_TABLE (PREFIX_0F2C) },
1630 { PREFIX_TABLE (PREFIX_0F2D) },
1631 { PREFIX_TABLE (PREFIX_0F2E) },
1632 { PREFIX_TABLE (PREFIX_0F2F) },
1633 /* 30 */
1634 { "wrmsr", { XX } },
1635 { "rdtsc", { XX } },
1636 { "rdmsr", { XX } },
1637 { "rdpmc", { XX } },
1638 { "sysenter", { XX } },
1639 { "sysexit", { XX } },
1640 { "(bad)", { XX } },
1641 { "getsec", { XX } },
1642 /* 38 */
1643 { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
1644 { "(bad)", { XX } },
1645 { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
1646 { "(bad)", { XX } },
1647 { "(bad)", { XX } },
1648 { "(bad)", { XX } },
1649 { "(bad)", { XX } },
1650 { "(bad)", { XX } },
1651 /* 40 */
1652 { "cmovo", { Gv, Ev } },
1653 { "cmovno", { Gv, Ev } },
1654 { "cmovb", { Gv, Ev } },
1655 { "cmovae", { Gv, Ev } },
1656 { "cmove", { Gv, Ev } },
1657 { "cmovne", { Gv, Ev } },
1658 { "cmovbe", { Gv, Ev } },
1659 { "cmova", { Gv, Ev } },
1660 /* 48 */
1661 { "cmovs", { Gv, Ev } },
1662 { "cmovns", { Gv, Ev } },
1663 { "cmovp", { Gv, Ev } },
1664 { "cmovnp", { Gv, Ev } },
1665 { "cmovl", { Gv, Ev } },
1666 { "cmovge", { Gv, Ev } },
1667 { "cmovle", { Gv, Ev } },
1668 { "cmovg", { Gv, Ev } },
1669 /* 50 */
1670 { MOD_TABLE (MOD_0F51) },
1671 { PREFIX_TABLE (PREFIX_0F51) },
1672 { PREFIX_TABLE (PREFIX_0F52) },
1673 { PREFIX_TABLE (PREFIX_0F53) },
1674 { "andpX", { XM, EXx } },
1675 { "andnpX", { XM, EXx } },
1676 { "orpX", { XM, EXx } },
1677 { "xorpX", { XM, EXx } },
1678 /* 58 */
1679 { PREFIX_TABLE (PREFIX_0F58) },
1680 { PREFIX_TABLE (PREFIX_0F59) },
1681 { PREFIX_TABLE (PREFIX_0F5A) },
1682 { PREFIX_TABLE (PREFIX_0F5B) },
1683 { PREFIX_TABLE (PREFIX_0F5C) },
1684 { PREFIX_TABLE (PREFIX_0F5D) },
1685 { PREFIX_TABLE (PREFIX_0F5E) },
1686 { PREFIX_TABLE (PREFIX_0F5F) },
1687 /* 60 */
1688 { PREFIX_TABLE (PREFIX_0F60) },
1689 { PREFIX_TABLE (PREFIX_0F61) },
1690 { PREFIX_TABLE (PREFIX_0F62) },
1691 { "packsswb", { MX, EM } },
1692 { "pcmpgtb", { MX, EM } },
1693 { "pcmpgtw", { MX, EM } },
1694 { "pcmpgtd", { MX, EM } },
1695 { "packuswb", { MX, EM } },
1696 /* 68 */
1697 { "punpckhbw", { MX, EM } },
1698 { "punpckhwd", { MX, EM } },
1699 { "punpckhdq", { MX, EM } },
1700 { "packssdw", { MX, EM } },
1701 { PREFIX_TABLE (PREFIX_0F6C) },
1702 { PREFIX_TABLE (PREFIX_0F6D) },
1703 { "movK", { MX, Edq } },
1704 { PREFIX_TABLE (PREFIX_0F6F) },
1705 /* 70 */
1706 { PREFIX_TABLE (PREFIX_0F70) },
1707 { REG_TABLE (REG_0F71) },
1708 { REG_TABLE (REG_0F72) },
1709 { REG_TABLE (REG_0F73) },
1710 { "pcmpeqb", { MX, EM } },
1711 { "pcmpeqw", { MX, EM } },
1712 { "pcmpeqd", { MX, EM } },
1713 { "emms", { XX } },
1714 /* 78 */
1715 { PREFIX_TABLE (PREFIX_0F78) },
1716 { PREFIX_TABLE (PREFIX_0F79) },
1717 { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
1718 { THREE_BYTE_TABLE (THREE_BYTE_0F7B) },
1719 { PREFIX_TABLE (PREFIX_0F7C) },
1720 { PREFIX_TABLE (PREFIX_0F7D) },
1721 { PREFIX_TABLE (PREFIX_0F7E) },
1722 { PREFIX_TABLE (PREFIX_0F7F) },
1723 /* 80 */
1724 { "joH", { Jv, XX, cond_jump_flag } },
1725 { "jnoH", { Jv, XX, cond_jump_flag } },
1726 { "jbH", { Jv, XX, cond_jump_flag } },
1727 { "jaeH", { Jv, XX, cond_jump_flag } },
1728 { "jeH", { Jv, XX, cond_jump_flag } },
1729 { "jneH", { Jv, XX, cond_jump_flag } },
1730 { "jbeH", { Jv, XX, cond_jump_flag } },
1731 { "jaH", { Jv, XX, cond_jump_flag } },
1732 /* 88 */
1733 { "jsH", { Jv, XX, cond_jump_flag } },
1734 { "jnsH", { Jv, XX, cond_jump_flag } },
1735 { "jpH", { Jv, XX, cond_jump_flag } },
1736 { "jnpH", { Jv, XX, cond_jump_flag } },
1737 { "jlH", { Jv, XX, cond_jump_flag } },
1738 { "jgeH", { Jv, XX, cond_jump_flag } },
1739 { "jleH", { Jv, XX, cond_jump_flag } },
1740 { "jgH", { Jv, XX, cond_jump_flag } },
1741 /* 90 */
1742 { "seto", { Eb } },
1743 { "setno", { Eb } },
1744 { "setb", { Eb } },
1745 { "setae", { Eb } },
1746 { "sete", { Eb } },
1747 { "setne", { Eb } },
1748 { "setbe", { Eb } },
1749 { "seta", { Eb } },
1750 /* 98 */
1751 { "sets", { Eb } },
1752 { "setns", { Eb } },
1753 { "setp", { Eb } },
1754 { "setnp", { Eb } },
1755 { "setl", { Eb } },
1756 { "setge", { Eb } },
1757 { "setle", { Eb } },
1758 { "setg", { Eb } },
1759 /* a0 */
1760 { "pushT", { fs } },
1761 { "popT", { fs } },
1762 { "cpuid", { XX } },
1763 { "btS", { Ev, Gv } },
1764 { "shldS", { Ev, Gv, Ib } },
1765 { "shldS", { Ev, Gv, CL } },
1766 { REG_TABLE (REG_0FA6) },
1767 { REG_TABLE (REG_0FA7) },
1768 /* a8 */
1769 { "pushT", { gs } },
1770 { "popT", { gs } },
1771 { "rsm", { XX } },
1772 { "btsS", { Ev, Gv } },
1773 { "shrdS", { Ev, Gv, Ib } },
1774 { "shrdS", { Ev, Gv, CL } },
1775 { REG_TABLE (REG_0FAE) },
1776 { "imulS", { Gv, Ev } },
1777 /* b0 */
1778 { "cmpxchgB", { Eb, Gb } },
1779 { "cmpxchgS", { Ev, Gv } },
1780 { MOD_TABLE (MOD_0FB2) },
1781 { "btrS", { Ev, Gv } },
1782 { MOD_TABLE (MOD_0FB4) },
1783 { MOD_TABLE (MOD_0FB5) },
1784 { "movz{bR|x}", { Gv, Eb } },
1785 { "movz{wR|x}", { Gv, Ew } }, /* yes, there really is movzww ! */
1786 /* b8 */
1787 { PREFIX_TABLE (PREFIX_0FB8) },
1788 { "ud2b", { XX } },
1789 { REG_TABLE (REG_0FBA) },
1790 { "btcS", { Ev, Gv } },
1791 { "bsfS", { Gv, Ev } },
1792 { PREFIX_TABLE (PREFIX_0FBD) },
1793 { "movs{bR|x}", { Gv, Eb } },
1794 { "movs{wR|x}", { Gv, Ew } }, /* yes, there really is movsww ! */
1795 /* c0 */
1796 { "xaddB", { Eb, Gb } },
1797 { "xaddS", { Ev, Gv } },
1798 { PREFIX_TABLE (PREFIX_0FC2) },
1799 { PREFIX_TABLE (PREFIX_0FC3) },
1800 { "pinsrw", { MX, Edqw, Ib } },
1801 { "pextrw", { Gdq, MS, Ib } },
1802 { "shufpX", { XM, EXx, Ib } },
1803 { REG_TABLE (REG_0FC7) },
1804 /* c8 */
1805 { "bswap", { RMeAX } },
1806 { "bswap", { RMeCX } },
1807 { "bswap", { RMeDX } },
1808 { "bswap", { RMeBX } },
1809 { "bswap", { RMeSP } },
1810 { "bswap", { RMeBP } },
1811 { "bswap", { RMeSI } },
1812 { "bswap", { RMeDI } },
1813 /* d0 */
1814 { PREFIX_TABLE (PREFIX_0FD0) },
1815 { "psrlw", { MX, EM } },
1816 { "psrld", { MX, EM } },
1817 { "psrlq", { MX, EM } },
1818 { "paddq", { MX, EM } },
1819 { "pmullw", { MX, EM } },
1820 { PREFIX_TABLE (PREFIX_0FD6) },
1821 { MOD_TABLE (MOD_0FD7) },
1822 /* d8 */
1823 { "psubusb", { MX, EM } },
1824 { "psubusw", { MX, EM } },
1825 { "pminub", { MX, EM } },
1826 { "pand", { MX, EM } },
1827 { "paddusb", { MX, EM } },
1828 { "paddusw", { MX, EM } },
1829 { "pmaxub", { MX, EM } },
1830 { "pandn", { MX, EM } },
1831 /* e0 */
1832 { "pavgb", { MX, EM } },
1833 { "psraw", { MX, EM } },
1834 { "psrad", { MX, EM } },
1835 { "pavgw", { MX, EM } },
1836 { "pmulhuw", { MX, EM } },
1837 { "pmulhw", { MX, EM } },
1838 { PREFIX_TABLE (PREFIX_0FE6) },
1839 { PREFIX_TABLE (PREFIX_0FE7) },
1840 /* e8 */
1841 { "psubsb", { MX, EM } },
1842 { "psubsw", { MX, EM } },
1843 { "pminsw", { MX, EM } },
1844 { "por", { MX, EM } },
1845 { "paddsb", { MX, EM } },
1846 { "paddsw", { MX, EM } },
1847 { "pmaxsw", { MX, EM } },
1848 { "pxor", { MX, EM } },
1849 /* f0 */
1850 { PREFIX_TABLE (PREFIX_0FF0) },
1851 { "psllw", { MX, EM } },
1852 { "pslld", { MX, EM } },
1853 { "psllq", { MX, EM } },
1854 { "pmuludq", { MX, EM } },
1855 { "pmaddwd", { MX, EM } },
1856 { "psadbw", { MX, EM } },
1857 { PREFIX_TABLE (PREFIX_0FF7) },
1858 /* f8 */
1859 { "psubb", { MX, EM } },
1860 { "psubw", { MX, EM } },
1861 { "psubd", { MX, EM } },
1862 { "psubq", { MX, EM } },
1863 { "paddb", { MX, EM } },
1864 { "paddw", { MX, EM } },
1865 { "paddd", { MX, EM } },
1866 { "(bad)", { XX } },
1867 };
1868
1869 static const unsigned char onebyte_has_modrm[256] = {
1870 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1871 /* ------------------------------- */
1872 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
1873 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
1874 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
1875 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
1876 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
1877 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
1878 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
1879 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
1880 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
1881 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
1882 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
1883 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
1884 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
1885 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
1886 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
1887 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
1888 /* ------------------------------- */
1889 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1890 };
1891
1892 static const unsigned char twobyte_has_modrm[256] = {
1893 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1894 /* ------------------------------- */
1895 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
1896 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
1897 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
1898 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
1899 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
1900 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
1901 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
1902 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
1903 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
1904 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
1905 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
1906 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
1907 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
1908 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
1909 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
1910 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
1911 /* ------------------------------- */
1912 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1913 };
1914
1915 static char obuf[100];
1916 static char *obufp;
1917 static char scratchbuf[100];
1918 static unsigned char *start_codep;
1919 static unsigned char *insn_codep;
1920 static unsigned char *codep;
1921 static const char *lock_prefix;
1922 static const char *data_prefix;
1923 static const char *addr_prefix;
1924 static const char *repz_prefix;
1925 static const char *repnz_prefix;
1926 static disassemble_info *the_info;
1927 static struct
1928 {
1929 int mod;
1930 int reg;
1931 int rm;
1932 }
1933 modrm;
1934 static unsigned char need_modrm;
1935 static struct
1936 {
1937 int register_specifier;
1938 int length;
1939 int prefix;
1940 int w;
1941 }
1942 vex;
1943 static unsigned char need_vex;
1944 static unsigned char need_vex_reg;
1945 static unsigned char vex_w_done;
1946
1947 /* If we are accessing mod/rm/reg without need_modrm set, then the
1948 values are stale. Hitting this abort likely indicates that you
1949 need to update onebyte_has_modrm or twobyte_has_modrm. */
1950 #define MODRM_CHECK if (!need_modrm) abort ()
1951
1952 static const char **names64;
1953 static const char **names32;
1954 static const char **names16;
1955 static const char **names8;
1956 static const char **names8rex;
1957 static const char **names_seg;
1958 static const char *index64;
1959 static const char *index32;
1960 static const char **index16;
1961
1962 static const char *intel_names64[] = {
1963 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
1964 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
1965 };
1966 static const char *intel_names32[] = {
1967 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
1968 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
1969 };
1970 static const char *intel_names16[] = {
1971 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
1972 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
1973 };
1974 static const char *intel_names8[] = {
1975 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
1976 };
1977 static const char *intel_names8rex[] = {
1978 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
1979 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
1980 };
1981 static const char *intel_names_seg[] = {
1982 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
1983 };
1984 static const char *intel_index64 = "riz";
1985 static const char *intel_index32 = "eiz";
1986 static const char *intel_index16[] = {
1987 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
1988 };
1989
1990 static const char *att_names64[] = {
1991 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
1992 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
1993 };
1994 static const char *att_names32[] = {
1995 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
1996 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
1997 };
1998 static const char *att_names16[] = {
1999 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2000 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2001 };
2002 static const char *att_names8[] = {
2003 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2004 };
2005 static const char *att_names8rex[] = {
2006 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2007 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2008 };
2009 static const char *att_names_seg[] = {
2010 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2011 };
2012 static const char *att_index64 = "%riz";
2013 static const char *att_index32 = "%eiz";
2014 static const char *att_index16[] = {
2015 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2016 };
2017
2018 static const struct dis386 reg_table[][8] = {
2019 /* REG_80 */
2020 {
2021 { "addA", { Eb, Ib } },
2022 { "orA", { Eb, Ib } },
2023 { "adcA", { Eb, Ib } },
2024 { "sbbA", { Eb, Ib } },
2025 { "andA", { Eb, Ib } },
2026 { "subA", { Eb, Ib } },
2027 { "xorA", { Eb, Ib } },
2028 { "cmpA", { Eb, Ib } },
2029 },
2030 /* REG_81 */
2031 {
2032 { "addQ", { Ev, Iv } },
2033 { "orQ", { Ev, Iv } },
2034 { "adcQ", { Ev, Iv } },
2035 { "sbbQ", { Ev, Iv } },
2036 { "andQ", { Ev, Iv } },
2037 { "subQ", { Ev, Iv } },
2038 { "xorQ", { Ev, Iv } },
2039 { "cmpQ", { Ev, Iv } },
2040 },
2041 /* REG_82 */
2042 {
2043 { "addQ", { Ev, sIb } },
2044 { "orQ", { Ev, sIb } },
2045 { "adcQ", { Ev, sIb } },
2046 { "sbbQ", { Ev, sIb } },
2047 { "andQ", { Ev, sIb } },
2048 { "subQ", { Ev, sIb } },
2049 { "xorQ", { Ev, sIb } },
2050 { "cmpQ", { Ev, sIb } },
2051 },
2052 /* REG_8F */
2053 {
2054 { "popU", { stackEv } },
2055 { "(bad)", { XX } },
2056 { "(bad)", { XX } },
2057 { "(bad)", { XX } },
2058 { "(bad)", { XX } },
2059 { "(bad)", { XX } },
2060 { "(bad)", { XX } },
2061 { "(bad)", { XX } },
2062 },
2063 /* REG_C0 */
2064 {
2065 { "rolA", { Eb, Ib } },
2066 { "rorA", { Eb, Ib } },
2067 { "rclA", { Eb, Ib } },
2068 { "rcrA", { Eb, Ib } },
2069 { "shlA", { Eb, Ib } },
2070 { "shrA", { Eb, Ib } },
2071 { "(bad)", { XX } },
2072 { "sarA", { Eb, Ib } },
2073 },
2074 /* REG_C1 */
2075 {
2076 { "rolQ", { Ev, Ib } },
2077 { "rorQ", { Ev, Ib } },
2078 { "rclQ", { Ev, Ib } },
2079 { "rcrQ", { Ev, Ib } },
2080 { "shlQ", { Ev, Ib } },
2081 { "shrQ", { Ev, Ib } },
2082 { "(bad)", { XX } },
2083 { "sarQ", { Ev, Ib } },
2084 },
2085 /* REG_C6 */
2086 {
2087 { "movA", { Eb, Ib } },
2088 { "(bad)", { XX } },
2089 { "(bad)", { XX } },
2090 { "(bad)", { XX } },
2091 { "(bad)", { XX } },
2092 { "(bad)", { XX } },
2093 { "(bad)", { XX } },
2094 { "(bad)", { XX } },
2095 },
2096 /* REG_C7 */
2097 {
2098 { "movQ", { Ev, Iv } },
2099 { "(bad)", { XX } },
2100 { "(bad)", { XX } },
2101 { "(bad)", { XX } },
2102 { "(bad)", { XX } },
2103 { "(bad)", { XX } },
2104 { "(bad)", { XX } },
2105 { "(bad)", { XX } },
2106 },
2107 /* REG_D0 */
2108 {
2109 { "rolA", { Eb, I1 } },
2110 { "rorA", { Eb, I1 } },
2111 { "rclA", { Eb, I1 } },
2112 { "rcrA", { Eb, I1 } },
2113 { "shlA", { Eb, I1 } },
2114 { "shrA", { Eb, I1 } },
2115 { "(bad)", { XX } },
2116 { "sarA", { Eb, I1 } },
2117 },
2118 /* REG_D1 */
2119 {
2120 { "rolQ", { Ev, I1 } },
2121 { "rorQ", { Ev, I1 } },
2122 { "rclQ", { Ev, I1 } },
2123 { "rcrQ", { Ev, I1 } },
2124 { "shlQ", { Ev, I1 } },
2125 { "shrQ", { Ev, I1 } },
2126 { "(bad)", { XX } },
2127 { "sarQ", { Ev, I1 } },
2128 },
2129 /* REG_D2 */
2130 {
2131 { "rolA", { Eb, CL } },
2132 { "rorA", { Eb, CL } },
2133 { "rclA", { Eb, CL } },
2134 { "rcrA", { Eb, CL } },
2135 { "shlA", { Eb, CL } },
2136 { "shrA", { Eb, CL } },
2137 { "(bad)", { XX } },
2138 { "sarA", { Eb, CL } },
2139 },
2140 /* REG_D3 */
2141 {
2142 { "rolQ", { Ev, CL } },
2143 { "rorQ", { Ev, CL } },
2144 { "rclQ", { Ev, CL } },
2145 { "rcrQ", { Ev, CL } },
2146 { "shlQ", { Ev, CL } },
2147 { "shrQ", { Ev, CL } },
2148 { "(bad)", { XX } },
2149 { "sarQ", { Ev, CL } },
2150 },
2151 /* REG_F6 */
2152 {
2153 { "testA", { Eb, Ib } },
2154 { "(bad)", { XX } },
2155 { "notA", { Eb } },
2156 { "negA", { Eb } },
2157 { "mulA", { Eb } }, /* Don't print the implicit %al register, */
2158 { "imulA", { Eb } }, /* to distinguish these opcodes from other */
2159 { "divA", { Eb } }, /* mul/imul opcodes. Do the same for div */
2160 { "idivA", { Eb } }, /* and idiv for consistency. */
2161 },
2162 /* REG_F7 */
2163 {
2164 { "testQ", { Ev, Iv } },
2165 { "(bad)", { XX } },
2166 { "notQ", { Ev } },
2167 { "negQ", { Ev } },
2168 { "mulQ", { Ev } }, /* Don't print the implicit register. */
2169 { "imulQ", { Ev } },
2170 { "divQ", { Ev } },
2171 { "idivQ", { Ev } },
2172 },
2173 /* REG_FE */
2174 {
2175 { "incA", { Eb } },
2176 { "decA", { Eb } },
2177 { "(bad)", { XX } },
2178 { "(bad)", { XX } },
2179 { "(bad)", { XX } },
2180 { "(bad)", { XX } },
2181 { "(bad)", { XX } },
2182 { "(bad)", { XX } },
2183 },
2184 /* REG_FF */
2185 {
2186 { "incQ", { Ev } },
2187 { "decQ", { Ev } },
2188 { "callT", { indirEv } },
2189 { "JcallT", { indirEp } },
2190 { "jmpT", { indirEv } },
2191 { "JjmpT", { indirEp } },
2192 { "pushU", { stackEv } },
2193 { "(bad)", { XX } },
2194 },
2195 /* REG_0F00 */
2196 {
2197 { "sldtD", { Sv } },
2198 { "strD", { Sv } },
2199 { "lldt", { Ew } },
2200 { "ltr", { Ew } },
2201 { "verr", { Ew } },
2202 { "verw", { Ew } },
2203 { "(bad)", { XX } },
2204 { "(bad)", { XX } },
2205 },
2206 /* REG_0F01 */
2207 {
2208 { MOD_TABLE (MOD_0F01_REG_0) },
2209 { MOD_TABLE (MOD_0F01_REG_1) },
2210 { MOD_TABLE (MOD_0F01_REG_2) },
2211 { MOD_TABLE (MOD_0F01_REG_3) },
2212 { "smswD", { Sv } },
2213 { "(bad)", { XX } },
2214 { "lmsw", { Ew } },
2215 { MOD_TABLE (MOD_0F01_REG_7) },
2216 },
2217 /* REG_0F0D */
2218 {
2219 { "prefetch", { Eb } },
2220 { "prefetchw", { Eb } },
2221 { "(bad)", { XX } },
2222 { "(bad)", { XX } },
2223 { "(bad)", { XX } },
2224 { "(bad)", { XX } },
2225 { "(bad)", { XX } },
2226 { "(bad)", { XX } },
2227 },
2228 /* REG_0F18 */
2229 {
2230 { MOD_TABLE (MOD_0F18_REG_0) },
2231 { MOD_TABLE (MOD_0F18_REG_1) },
2232 { MOD_TABLE (MOD_0F18_REG_2) },
2233 { MOD_TABLE (MOD_0F18_REG_3) },
2234 { "(bad)", { XX } },
2235 { "(bad)", { XX } },
2236 { "(bad)", { XX } },
2237 { "(bad)", { XX } },
2238 },
2239 /* REG_0F71 */
2240 {
2241 { "(bad)", { XX } },
2242 { "(bad)", { XX } },
2243 { MOD_TABLE (MOD_0F71_REG_2) },
2244 { "(bad)", { XX } },
2245 { MOD_TABLE (MOD_0F71_REG_4) },
2246 { "(bad)", { XX } },
2247 { MOD_TABLE (MOD_0F71_REG_6) },
2248 { "(bad)", { XX } },
2249 },
2250 /* REG_0F72 */
2251 {
2252 { "(bad)", { XX } },
2253 { "(bad)", { XX } },
2254 { MOD_TABLE (MOD_0F72_REG_2) },
2255 { "(bad)", { XX } },
2256 { MOD_TABLE (MOD_0F72_REG_4) },
2257 { "(bad)", { XX } },
2258 { MOD_TABLE (MOD_0F72_REG_6) },
2259 { "(bad)", { XX } },
2260 },
2261 /* REG_0F73 */
2262 {
2263 { "(bad)", { XX } },
2264 { "(bad)", { XX } },
2265 { MOD_TABLE (MOD_0F73_REG_2) },
2266 { MOD_TABLE (MOD_0F73_REG_3) },
2267 { "(bad)", { XX } },
2268 { "(bad)", { XX } },
2269 { MOD_TABLE (MOD_0F73_REG_6) },
2270 { MOD_TABLE (MOD_0F73_REG_7) },
2271 },
2272 /* REG_0FA6 */
2273 {
2274 { "montmul", { { OP_0f07, 0 } } },
2275 { "xsha1", { { OP_0f07, 0 } } },
2276 { "xsha256", { { OP_0f07, 0 } } },
2277 { "(bad)", { { OP_0f07, 0 } } },
2278 { "(bad)", { { OP_0f07, 0 } } },
2279 { "(bad)", { { OP_0f07, 0 } } },
2280 { "(bad)", { { OP_0f07, 0 } } },
2281 { "(bad)", { { OP_0f07, 0 } } },
2282 },
2283 /* REG_0FA7 */
2284 {
2285 { "xstore-rng", { { OP_0f07, 0 } } },
2286 { "xcrypt-ecb", { { OP_0f07, 0 } } },
2287 { "xcrypt-cbc", { { OP_0f07, 0 } } },
2288 { "xcrypt-ctr", { { OP_0f07, 0 } } },
2289 { "xcrypt-cfb", { { OP_0f07, 0 } } },
2290 { "xcrypt-ofb", { { OP_0f07, 0 } } },
2291 { "(bad)", { { OP_0f07, 0 } } },
2292 { "(bad)", { { OP_0f07, 0 } } },
2293 },
2294 /* REG_0FAE */
2295 {
2296 { MOD_TABLE (MOD_0FAE_REG_0) },
2297 { MOD_TABLE (MOD_0FAE_REG_1) },
2298 { MOD_TABLE (MOD_0FAE_REG_2) },
2299 { MOD_TABLE (MOD_0FAE_REG_3) },
2300 { MOD_TABLE (MOD_0FAE_REG_4) },
2301 { MOD_TABLE (MOD_0FAE_REG_5) },
2302 { MOD_TABLE (MOD_0FAE_REG_6) },
2303 { MOD_TABLE (MOD_0FAE_REG_7) },
2304 },
2305 /* REG_0FBA */
2306 {
2307 { "(bad)", { XX } },
2308 { "(bad)", { XX } },
2309 { "(bad)", { XX } },
2310 { "(bad)", { XX } },
2311 { "btQ", { Ev, Ib } },
2312 { "btsQ", { Ev, Ib } },
2313 { "btrQ", { Ev, Ib } },
2314 { "btcQ", { Ev, Ib } },
2315 },
2316 /* REG_0FC7 */
2317 {
2318 { "(bad)", { XX } },
2319 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
2320 { "(bad)", { XX } },
2321 { "(bad)", { XX } },
2322 { "(bad)", { XX } },
2323 { "(bad)", { XX } },
2324 { MOD_TABLE (MOD_0FC7_REG_6) },
2325 { MOD_TABLE (MOD_0FC7_REG_7) },
2326 },
2327 /* REG_VEX_71 */
2328 {
2329 { "(bad)", { XX } },
2330 { "(bad)", { XX } },
2331 { MOD_TABLE (MOD_VEX_71_REG_2) },
2332 { "(bad)", { XX } },
2333 { MOD_TABLE (MOD_VEX_71_REG_4) },
2334 { "(bad)", { XX } },
2335 { MOD_TABLE (MOD_VEX_71_REG_6) },
2336 { "(bad)", { XX } },
2337 },
2338 /* REG_VEX_72 */
2339 {
2340 { "(bad)", { XX } },
2341 { "(bad)", { XX } },
2342 { MOD_TABLE (MOD_VEX_72_REG_2) },
2343 { "(bad)", { XX } },
2344 { MOD_TABLE (MOD_VEX_72_REG_4) },
2345 { "(bad)", { XX } },
2346 { MOD_TABLE (MOD_VEX_72_REG_6) },
2347 { "(bad)", { XX } },
2348 },
2349 /* REG_VEX_73 */
2350 {
2351 { "(bad)", { XX } },
2352 { "(bad)", { XX } },
2353 { MOD_TABLE (MOD_VEX_73_REG_2) },
2354 { MOD_TABLE (MOD_VEX_73_REG_3) },
2355 { "(bad)", { XX } },
2356 { "(bad)", { XX } },
2357 { MOD_TABLE (MOD_VEX_73_REG_6) },
2358 { MOD_TABLE (MOD_VEX_73_REG_7) },
2359 },
2360 /* REG_VEX_AE */
2361 {
2362 { "(bad)", { XX } },
2363 { "(bad)", { XX } },
2364 { MOD_TABLE (MOD_VEX_AE_REG_2) },
2365 { MOD_TABLE (MOD_VEX_AE_REG_3) },
2366 { "(bad)", { XX } },
2367 { "(bad)", { XX } },
2368 { "(bad)", { XX } },
2369 { "(bad)", { XX } },
2370 },
2371 };
2372
2373 static const struct dis386 prefix_table[][4] = {
2374 /* PREFIX_90 */
2375 {
2376 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2377 { "pause", { XX } },
2378 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2379 { "(bad)", { XX } },
2380 },
2381
2382 /* PREFIX_0F10 */
2383 {
2384 { "movups", { XM, EXx } },
2385 { "movss", { XM, EXd } },
2386 { "movupd", { XM, EXx } },
2387 { "movsd", { XM, EXq } },
2388 },
2389
2390 /* PREFIX_0F11 */
2391 {
2392 { "movups", { EXx, XM } },
2393 { "movss", { EXd, XM } },
2394 { "movupd", { EXx, XM } },
2395 { "movsd", { EXq, XM } },
2396 },
2397
2398 /* PREFIX_0F12 */
2399 {
2400 { MOD_TABLE (MOD_0F12_PREFIX_0) },
2401 { "movsldup", { XM, EXx } },
2402 { "movlpd", { XM, EXq } },
2403 { "movddup", { XM, EXq } },
2404 },
2405
2406 /* PREFIX_0F16 */
2407 {
2408 { MOD_TABLE (MOD_0F16_PREFIX_0) },
2409 { "movshdup", { XM, EXx } },
2410 { "movhpd", { XM, EXq } },
2411 { "(bad)", { XX } },
2412 },
2413
2414 /* PREFIX_0F2A */
2415 {
2416 { "cvtpi2ps", { XM, EMCq } },
2417 { "cvtsi2ss%LQ", { XM, Ev } },
2418 { "cvtpi2pd", { XM, EMCq } },
2419 { "cvtsi2sd%LQ", { XM, Ev } },
2420 },
2421
2422 /* PREFIX_0F2B */
2423 {
2424 { MOD_TABLE (MOD_0F2B_PREFIX_0) },
2425 { MOD_TABLE (MOD_0F2B_PREFIX_1) },
2426 { MOD_TABLE (MOD_0F2B_PREFIX_2) },
2427 { MOD_TABLE (MOD_0F2B_PREFIX_3) },
2428 },
2429
2430 /* PREFIX_0F2C */
2431 {
2432 { "cvttps2pi", { MXC, EXq } },
2433 { "cvttss2siY", { Gv, EXd } },
2434 { "cvttpd2pi", { MXC, EXx } },
2435 { "cvttsd2siY", { Gv, EXq } },
2436 },
2437
2438 /* PREFIX_0F2D */
2439 {
2440 { "cvtps2pi", { MXC, EXq } },
2441 { "cvtss2siY", { Gv, EXd } },
2442 { "cvtpd2pi", { MXC, EXx } },
2443 { "cvtsd2siY", { Gv, EXq } },
2444 },
2445
2446 /* PREFIX_0F2E */
2447 {
2448 { "ucomiss",{ XM, EXd } },
2449 { "(bad)", { XX } },
2450 { "ucomisd",{ XM, EXq } },
2451 { "(bad)", { XX } },
2452 },
2453
2454 /* PREFIX_0F2F */
2455 {
2456 { "comiss", { XM, EXd } },
2457 { "(bad)", { XX } },
2458 { "comisd", { XM, EXq } },
2459 { "(bad)", { XX } },
2460 },
2461
2462 /* PREFIX_0F51 */
2463 {
2464 { "sqrtps", { XM, EXx } },
2465 { "sqrtss", { XM, EXd } },
2466 { "sqrtpd", { XM, EXx } },
2467 { "sqrtsd", { XM, EXq } },
2468 },
2469
2470 /* PREFIX_0F52 */
2471 {
2472 { "rsqrtps",{ XM, EXx } },
2473 { "rsqrtss",{ XM, EXd } },
2474 { "(bad)", { XX } },
2475 { "(bad)", { XX } },
2476 },
2477
2478 /* PREFIX_0F53 */
2479 {
2480 { "rcpps", { XM, EXx } },
2481 { "rcpss", { XM, EXd } },
2482 { "(bad)", { XX } },
2483 { "(bad)", { XX } },
2484 },
2485
2486 /* PREFIX_0F58 */
2487 {
2488 { "addps", { XM, EXx } },
2489 { "addss", { XM, EXd } },
2490 { "addpd", { XM, EXx } },
2491 { "addsd", { XM, EXq } },
2492 },
2493
2494 /* PREFIX_0F59 */
2495 {
2496 { "mulps", { XM, EXx } },
2497 { "mulss", { XM, EXd } },
2498 { "mulpd", { XM, EXx } },
2499 { "mulsd", { XM, EXq } },
2500 },
2501
2502 /* PREFIX_0F5A */
2503 {
2504 { "cvtps2pd", { XM, EXq } },
2505 { "cvtss2sd", { XM, EXd } },
2506 { "cvtpd2ps", { XM, EXx } },
2507 { "cvtsd2ss", { XM, EXq } },
2508 },
2509
2510 /* PREFIX_0F5B */
2511 {
2512 { "cvtdq2ps", { XM, EXx } },
2513 { "cvttps2dq", { XM, EXx } },
2514 { "cvtps2dq", { XM, EXx } },
2515 { "(bad)", { XX } },
2516 },
2517
2518 /* PREFIX_0F5C */
2519 {
2520 { "subps", { XM, EXx } },
2521 { "subss", { XM, EXd } },
2522 { "subpd", { XM, EXx } },
2523 { "subsd", { XM, EXq } },
2524 },
2525
2526 /* PREFIX_0F5D */
2527 {
2528 { "minps", { XM, EXx } },
2529 { "minss", { XM, EXd } },
2530 { "minpd", { XM, EXx } },
2531 { "minsd", { XM, EXq } },
2532 },
2533
2534 /* PREFIX_0F5E */
2535 {
2536 { "divps", { XM, EXx } },
2537 { "divss", { XM, EXd } },
2538 { "divpd", { XM, EXx } },
2539 { "divsd", { XM, EXq } },
2540 },
2541
2542 /* PREFIX_0F5F */
2543 {
2544 { "maxps", { XM, EXx } },
2545 { "maxss", { XM, EXd } },
2546 { "maxpd", { XM, EXx } },
2547 { "maxsd", { XM, EXq } },
2548 },
2549
2550 /* PREFIX_0F60 */
2551 {
2552 { "punpcklbw",{ MX, EMd } },
2553 { "(bad)", { XX } },
2554 { "punpcklbw",{ MX, EMx } },
2555 { "(bad)", { XX } },
2556 },
2557
2558 /* PREFIX_0F61 */
2559 {
2560 { "punpcklwd",{ MX, EMd } },
2561 { "(bad)", { XX } },
2562 { "punpcklwd",{ MX, EMx } },
2563 { "(bad)", { XX } },
2564 },
2565
2566 /* PREFIX_0F62 */
2567 {
2568 { "punpckldq",{ MX, EMd } },
2569 { "(bad)", { XX } },
2570 { "punpckldq",{ MX, EMx } },
2571 { "(bad)", { XX } },
2572 },
2573
2574 /* PREFIX_0F6C */
2575 {
2576 { "(bad)", { XX } },
2577 { "(bad)", { XX } },
2578 { "punpcklqdq", { XM, EXx } },
2579 { "(bad)", { XX } },
2580 },
2581
2582 /* PREFIX_0F6D */
2583 {
2584 { "(bad)", { XX } },
2585 { "(bad)", { XX } },
2586 { "punpckhqdq", { XM, EXx } },
2587 { "(bad)", { XX } },
2588 },
2589
2590 /* PREFIX_0F6F */
2591 {
2592 { "movq", { MX, EM } },
2593 { "movdqu", { XM, EXx } },
2594 { "movdqa", { XM, EXx } },
2595 { "(bad)", { XX } },
2596 },
2597
2598 /* PREFIX_0F70 */
2599 {
2600 { "pshufw", { MX, EM, Ib } },
2601 { "pshufhw",{ XM, EXx, Ib } },
2602 { "pshufd", { XM, EXx, Ib } },
2603 { "pshuflw",{ XM, EXx, Ib } },
2604 },
2605
2606 /* PREFIX_0F73_REG_3 */
2607 {
2608 { "(bad)", { XX } },
2609 { "(bad)", { XX } },
2610 { "psrldq", { XS, Ib } },
2611 { "(bad)", { XX } },
2612 },
2613
2614 /* PREFIX_0F73_REG_7 */
2615 {
2616 { "(bad)", { XX } },
2617 { "(bad)", { XX } },
2618 { "pslldq", { XS, Ib } },
2619 { "(bad)", { XX } },
2620 },
2621
2622 /* PREFIX_0F78 */
2623 {
2624 {"vmread", { Em, Gm } },
2625 {"(bad)", { XX } },
2626 {"extrq", { XS, Ib, Ib } },
2627 {"insertq", { XM, XS, Ib, Ib } },
2628 },
2629
2630 /* PREFIX_0F79 */
2631 {
2632 {"vmwrite", { Gm, Em } },
2633 {"(bad)", { XX } },
2634 {"extrq", { XM, XS } },
2635 {"insertq", { XM, XS } },
2636 },
2637
2638 /* PREFIX_0F7C */
2639 {
2640 { "(bad)", { XX } },
2641 { "(bad)", { XX } },
2642 { "haddpd", { XM, EXx } },
2643 { "haddps", { XM, EXx } },
2644 },
2645
2646 /* PREFIX_0F7D */
2647 {
2648 { "(bad)", { XX } },
2649 { "(bad)", { XX } },
2650 { "hsubpd", { XM, EXx } },
2651 { "hsubps", { XM, EXx } },
2652 },
2653
2654 /* PREFIX_0F7E */
2655 {
2656 { "movK", { Edq, MX } },
2657 { "movq", { XM, EXq } },
2658 { "movK", { Edq, XM } },
2659 { "(bad)", { XX } },
2660 },
2661
2662 /* PREFIX_0F7F */
2663 {
2664 { "movq", { EM, MX } },
2665 { "movdqu", { EXx, XM } },
2666 { "movdqa", { EXx, XM } },
2667 { "(bad)", { XX } },
2668 },
2669
2670 /* PREFIX_0FB8 */
2671 {
2672 { "(bad)", { XX } },
2673 { "popcntS", { Gv, Ev } },
2674 { "(bad)", { XX } },
2675 { "(bad)", { XX } },
2676 },
2677
2678 /* PREFIX_0FBD */
2679 {
2680 { "bsrS", { Gv, Ev } },
2681 { "lzcntS", { Gv, Ev } },
2682 { "bsrS", { Gv, Ev } },
2683 { "(bad)", { XX } },
2684 },
2685
2686 /* PREFIX_0FC2 */
2687 {
2688 { "cmpps", { XM, EXx, CMP } },
2689 { "cmpss", { XM, EXd, CMP } },
2690 { "cmppd", { XM, EXx, CMP } },
2691 { "cmpsd", { XM, EXq, CMP } },
2692 },
2693
2694 /* PREFIX_0FC3 */
2695 {
2696 { "movntiS", { Ma, Gv } },
2697 { "(bad)", { XX } },
2698 { "(bad)", { XX } },
2699 { "(bad)", { XX } },
2700 },
2701
2702 /* PREFIX_0FC7_REG_6 */
2703 {
2704 { "vmptrld",{ Mq } },
2705 { "vmxon", { Mq } },
2706 { "vmclear",{ Mq } },
2707 { "(bad)", { XX } },
2708 },
2709
2710 /* PREFIX_0FD0 */
2711 {
2712 { "(bad)", { XX } },
2713 { "(bad)", { XX } },
2714 { "addsubpd", { XM, EXx } },
2715 { "addsubps", { XM, EXx } },
2716 },
2717
2718 /* PREFIX_0FD6 */
2719 {
2720 { "(bad)", { XX } },
2721 { "movq2dq",{ XM, MS } },
2722 { "movq", { EXq, XM } },
2723 { "movdq2q",{ MX, XS } },
2724 },
2725
2726 /* PREFIX_0FE6 */
2727 {
2728 { "(bad)", { XX } },
2729 { "cvtdq2pd", { XM, EXq } },
2730 { "cvttpd2dq", { XM, EXx } },
2731 { "cvtpd2dq", { XM, EXx } },
2732 },
2733
2734 /* PREFIX_0FE7 */
2735 {
2736 { "movntq", { Mq, MX } },
2737 { "(bad)", { XX } },
2738 { MOD_TABLE (MOD_0FE7_PREFIX_2) },
2739 { "(bad)", { XX } },
2740 },
2741
2742 /* PREFIX_0FF0 */
2743 {
2744 { "(bad)", { XX } },
2745 { "(bad)", { XX } },
2746 { "(bad)", { XX } },
2747 { MOD_TABLE (MOD_0FF0_PREFIX_3) },
2748 },
2749
2750 /* PREFIX_0FF7 */
2751 {
2752 { "maskmovq", { MX, MS } },
2753 { "(bad)", { XX } },
2754 { "maskmovdqu", { XM, XS } },
2755 { "(bad)", { XX } },
2756 },
2757
2758 /* PREFIX_0F3810 */
2759 {
2760 { "(bad)", { XX } },
2761 { "(bad)", { XX } },
2762 { "pblendvb", { XM, EXx, XMM0 } },
2763 { "(bad)", { XX } },
2764 },
2765
2766 /* PREFIX_0F3814 */
2767 {
2768 { "(bad)", { XX } },
2769 { "(bad)", { XX } },
2770 { "blendvps", { XM, EXx, XMM0 } },
2771 { "(bad)", { XX } },
2772 },
2773
2774 /* PREFIX_0F3815 */
2775 {
2776 { "(bad)", { XX } },
2777 { "(bad)", { XX } },
2778 { "blendvpd", { XM, EXx, XMM0 } },
2779 { "(bad)", { XX } },
2780 },
2781
2782 /* PREFIX_0F3817 */
2783 {
2784 { "(bad)", { XX } },
2785 { "(bad)", { XX } },
2786 { "ptest", { XM, EXx } },
2787 { "(bad)", { XX } },
2788 },
2789
2790 /* PREFIX_0F3820 */
2791 {
2792 { "(bad)", { XX } },
2793 { "(bad)", { XX } },
2794 { "pmovsxbw", { XM, EXq } },
2795 { "(bad)", { XX } },
2796 },
2797
2798 /* PREFIX_0F3821 */
2799 {
2800 { "(bad)", { XX } },
2801 { "(bad)", { XX } },
2802 { "pmovsxbd", { XM, EXd } },
2803 { "(bad)", { XX } },
2804 },
2805
2806 /* PREFIX_0F3822 */
2807 {
2808 { "(bad)", { XX } },
2809 { "(bad)", { XX } },
2810 { "pmovsxbq", { XM, EXw } },
2811 { "(bad)", { XX } },
2812 },
2813
2814 /* PREFIX_0F3823 */
2815 {
2816 { "(bad)", { XX } },
2817 { "(bad)", { XX } },
2818 { "pmovsxwd", { XM, EXq } },
2819 { "(bad)", { XX } },
2820 },
2821
2822 /* PREFIX_0F3824 */
2823 {
2824 { "(bad)", { XX } },
2825 { "(bad)", { XX } },
2826 { "pmovsxwq", { XM, EXd } },
2827 { "(bad)", { XX } },
2828 },
2829
2830 /* PREFIX_0F3825 */
2831 {
2832 { "(bad)", { XX } },
2833 { "(bad)", { XX } },
2834 { "pmovsxdq", { XM, EXq } },
2835 { "(bad)", { XX } },
2836 },
2837
2838 /* PREFIX_0F3828 */
2839 {
2840 { "(bad)", { XX } },
2841 { "(bad)", { XX } },
2842 { "pmuldq", { XM, EXx } },
2843 { "(bad)", { XX } },
2844 },
2845
2846 /* PREFIX_0F3829 */
2847 {
2848 { "(bad)", { XX } },
2849 { "(bad)", { XX } },
2850 { "pcmpeqq", { XM, EXx } },
2851 { "(bad)", { XX } },
2852 },
2853
2854 /* PREFIX_0F382A */
2855 {
2856 { "(bad)", { XX } },
2857 { "(bad)", { XX } },
2858 { MOD_TABLE (MOD_0F382A_PREFIX_2) },
2859 { "(bad)", { XX } },
2860 },
2861
2862 /* PREFIX_0F382B */
2863 {
2864 { "(bad)", { XX } },
2865 { "(bad)", { XX } },
2866 { "packusdw", { XM, EXx } },
2867 { "(bad)", { XX } },
2868 },
2869
2870 /* PREFIX_0F3830 */
2871 {
2872 { "(bad)", { XX } },
2873 { "(bad)", { XX } },
2874 { "pmovzxbw", { XM, EXq } },
2875 { "(bad)", { XX } },
2876 },
2877
2878 /* PREFIX_0F3831 */
2879 {
2880 { "(bad)", { XX } },
2881 { "(bad)", { XX } },
2882 { "pmovzxbd", { XM, EXd } },
2883 { "(bad)", { XX } },
2884 },
2885
2886 /* PREFIX_0F3832 */
2887 {
2888 { "(bad)", { XX } },
2889 { "(bad)", { XX } },
2890 { "pmovzxbq", { XM, EXw } },
2891 { "(bad)", { XX } },
2892 },
2893
2894 /* PREFIX_0F3833 */
2895 {
2896 { "(bad)", { XX } },
2897 { "(bad)", { XX } },
2898 { "pmovzxwd", { XM, EXq } },
2899 { "(bad)", { XX } },
2900 },
2901
2902 /* PREFIX_0F3834 */
2903 {
2904 { "(bad)", { XX } },
2905 { "(bad)", { XX } },
2906 { "pmovzxwq", { XM, EXd } },
2907 { "(bad)", { XX } },
2908 },
2909
2910 /* PREFIX_0F3835 */
2911 {
2912 { "(bad)", { XX } },
2913 { "(bad)", { XX } },
2914 { "pmovzxdq", { XM, EXq } },
2915 { "(bad)", { XX } },
2916 },
2917
2918 /* PREFIX_0F3837 */
2919 {
2920 { "(bad)", { XX } },
2921 { "(bad)", { XX } },
2922 { "pcmpgtq", { XM, EXx } },
2923 { "(bad)", { XX } },
2924 },
2925
2926 /* PREFIX_0F3838 */
2927 {
2928 { "(bad)", { XX } },
2929 { "(bad)", { XX } },
2930 { "pminsb", { XM, EXx } },
2931 { "(bad)", { XX } },
2932 },
2933
2934 /* PREFIX_0F3839 */
2935 {
2936 { "(bad)", { XX } },
2937 { "(bad)", { XX } },
2938 { "pminsd", { XM, EXx } },
2939 { "(bad)", { XX } },
2940 },
2941
2942 /* PREFIX_0F383A */
2943 {
2944 { "(bad)", { XX } },
2945 { "(bad)", { XX } },
2946 { "pminuw", { XM, EXx } },
2947 { "(bad)", { XX } },
2948 },
2949
2950 /* PREFIX_0F383B */
2951 {
2952 { "(bad)", { XX } },
2953 { "(bad)", { XX } },
2954 { "pminud", { XM, EXx } },
2955 { "(bad)", { XX } },
2956 },
2957
2958 /* PREFIX_0F383C */
2959 {
2960 { "(bad)", { XX } },
2961 { "(bad)", { XX } },
2962 { "pmaxsb", { XM, EXx } },
2963 { "(bad)", { XX } },
2964 },
2965
2966 /* PREFIX_0F383D */
2967 {
2968 { "(bad)", { XX } },
2969 { "(bad)", { XX } },
2970 { "pmaxsd", { XM, EXx } },
2971 { "(bad)", { XX } },
2972 },
2973
2974 /* PREFIX_0F383E */
2975 {
2976 { "(bad)", { XX } },
2977 { "(bad)", { XX } },
2978 { "pmaxuw", { XM, EXx } },
2979 { "(bad)", { XX } },
2980 },
2981
2982 /* PREFIX_0F383F */
2983 {
2984 { "(bad)", { XX } },
2985 { "(bad)", { XX } },
2986 { "pmaxud", { XM, EXx } },
2987 { "(bad)", { XX } },
2988 },
2989
2990 /* PREFIX_0F3840 */
2991 {
2992 { "(bad)", { XX } },
2993 { "(bad)", { XX } },
2994 { "pmulld", { XM, EXx } },
2995 { "(bad)", { XX } },
2996 },
2997
2998 /* PREFIX_0F3841 */
2999 {
3000 { "(bad)", { XX } },
3001 { "(bad)", { XX } },
3002 { "phminposuw", { XM, EXx } },
3003 { "(bad)", { XX } },
3004 },
3005
3006 /* PREFIX_0F38DB */
3007 {
3008 { "(bad)", { XX } },
3009 { "(bad)", { XX } },
3010 { "aesimc", { XM, EXx } },
3011 { "(bad)", { XX } },
3012 },
3013
3014 /* PREFIX_0F38DC */
3015 {
3016 { "(bad)", { XX } },
3017 { "(bad)", { XX } },
3018 { "aesenc", { XM, EXx } },
3019 { "(bad)", { XX } },
3020 },
3021
3022 /* PREFIX_0F38DD */
3023 {
3024 { "(bad)", { XX } },
3025 { "(bad)", { XX } },
3026 { "aesenclast", { XM, EXx } },
3027 { "(bad)", { XX } },
3028 },
3029
3030 /* PREFIX_0F38DE */
3031 {
3032 { "(bad)", { XX } },
3033 { "(bad)", { XX } },
3034 { "aesdec", { XM, EXx } },
3035 { "(bad)", { XX } },
3036 },
3037
3038 /* PREFIX_0F38DF */
3039 {
3040 { "(bad)", { XX } },
3041 { "(bad)", { XX } },
3042 { "aesdeclast", { XM, EXx } },
3043 { "(bad)", { XX } },
3044 },
3045
3046 /* PREFIX_0F38F0 */
3047 {
3048 { "(bad)", { XX } },
3049 { "(bad)", { XX } },
3050 { "(bad)", { XX } },
3051 { "crc32", { Gdq, { CRC32_Fixup, b_mode } } },
3052 },
3053
3054 /* PREFIX_0F38F1 */
3055 {
3056 { "(bad)", { XX } },
3057 { "(bad)", { XX } },
3058 { "(bad)", { XX } },
3059 { "crc32", { Gdq, { CRC32_Fixup, v_mode } } },
3060 },
3061
3062 /* PREFIX_0F3A08 */
3063 {
3064 { "(bad)", { XX } },
3065 { "(bad)", { XX } },
3066 { "roundps", { XM, EXx, Ib } },
3067 { "(bad)", { XX } },
3068 },
3069
3070 /* PREFIX_0F3A09 */
3071 {
3072 { "(bad)", { XX } },
3073 { "(bad)", { XX } },
3074 { "roundpd", { XM, EXx, Ib } },
3075 { "(bad)", { XX } },
3076 },
3077
3078 /* PREFIX_0F3A0A */
3079 {
3080 { "(bad)", { XX } },
3081 { "(bad)", { XX } },
3082 { "roundss", { XM, EXd, Ib } },
3083 { "(bad)", { XX } },
3084 },
3085
3086 /* PREFIX_0F3A0B */
3087 {
3088 { "(bad)", { XX } },
3089 { "(bad)", { XX } },
3090 { "roundsd", { XM, EXq, Ib } },
3091 { "(bad)", { XX } },
3092 },
3093
3094 /* PREFIX_0F3A0C */
3095 {
3096 { "(bad)", { XX } },
3097 { "(bad)", { XX } },
3098 { "blendps", { XM, EXx, Ib } },
3099 { "(bad)", { XX } },
3100 },
3101
3102 /* PREFIX_0F3A0D */
3103 {
3104 { "(bad)", { XX } },
3105 { "(bad)", { XX } },
3106 { "blendpd", { XM, EXx, Ib } },
3107 { "(bad)", { XX } },
3108 },
3109
3110 /* PREFIX_0F3A0E */
3111 {
3112 { "(bad)", { XX } },
3113 { "(bad)", { XX } },
3114 { "pblendw", { XM, EXx, Ib } },
3115 { "(bad)", { XX } },
3116 },
3117
3118 /* PREFIX_0F3A14 */
3119 {
3120 { "(bad)", { XX } },
3121 { "(bad)", { XX } },
3122 { "pextrb", { Edqb, XM, Ib } },
3123 { "(bad)", { XX } },
3124 },
3125
3126 /* PREFIX_0F3A15 */
3127 {
3128 { "(bad)", { XX } },
3129 { "(bad)", { XX } },
3130 { "pextrw", { Edqw, XM, Ib } },
3131 { "(bad)", { XX } },
3132 },
3133
3134 /* PREFIX_0F3A16 */
3135 {
3136 { "(bad)", { XX } },
3137 { "(bad)", { XX } },
3138 { "pextrK", { Edq, XM, Ib } },
3139 { "(bad)", { XX } },
3140 },
3141
3142 /* PREFIX_0F3A17 */
3143 {
3144 { "(bad)", { XX } },
3145 { "(bad)", { XX } },
3146 { "extractps", { Edqd, XM, Ib } },
3147 { "(bad)", { XX } },
3148 },
3149
3150 /* PREFIX_0F3A20 */
3151 {
3152 { "(bad)", { XX } },
3153 { "(bad)", { XX } },
3154 { "pinsrb", { XM, Edqb, Ib } },
3155 { "(bad)", { XX } },
3156 },
3157
3158 /* PREFIX_0F3A21 */
3159 {
3160 { "(bad)", { XX } },
3161 { "(bad)", { XX } },
3162 { "insertps", { XM, EXd, Ib } },
3163 { "(bad)", { XX } },
3164 },
3165
3166 /* PREFIX_0F3A22 */
3167 {
3168 { "(bad)", { XX } },
3169 { "(bad)", { XX } },
3170 { "pinsrK", { XM, Edq, Ib } },
3171 { "(bad)", { XX } },
3172 },
3173
3174 /* PREFIX_0F3A40 */
3175 {
3176 { "(bad)", { XX } },
3177 { "(bad)", { XX } },
3178 { "dpps", { XM, EXx, Ib } },
3179 { "(bad)", { XX } },
3180 },
3181
3182 /* PREFIX_0F3A41 */
3183 {
3184 { "(bad)", { XX } },
3185 { "(bad)", { XX } },
3186 { "dppd", { XM, EXx, Ib } },
3187 { "(bad)", { XX } },
3188 },
3189
3190 /* PREFIX_0F3A42 */
3191 {
3192 { "(bad)", { XX } },
3193 { "(bad)", { XX } },
3194 { "mpsadbw", { XM, EXx, Ib } },
3195 { "(bad)", { XX } },
3196 },
3197
3198 /* PREFIX_0F3A44 */
3199 {
3200 { "(bad)", { XX } },
3201 { "(bad)", { XX } },
3202 { "pclmulqdq", { XM, EXx, PCLMUL } },
3203 { "(bad)", { XX } },
3204 },
3205
3206 /* PREFIX_0F3A60 */
3207 {
3208 { "(bad)", { XX } },
3209 { "(bad)", { XX } },
3210 { "pcmpestrm", { XM, EXx, Ib } },
3211 { "(bad)", { XX } },
3212 },
3213
3214 /* PREFIX_0F3A61 */
3215 {
3216 { "(bad)", { XX } },
3217 { "(bad)", { XX } },
3218 { "pcmpestri", { XM, EXx, Ib } },
3219 { "(bad)", { XX } },
3220 },
3221
3222 /* PREFIX_0F3A62 */
3223 {
3224 { "(bad)", { XX } },
3225 { "(bad)", { XX } },
3226 { "pcmpistrm", { XM, EXx, Ib } },
3227 { "(bad)", { XX } },
3228 },
3229
3230 /* PREFIX_0F3A63 */
3231 {
3232 { "(bad)", { XX } },
3233 { "(bad)", { XX } },
3234 { "pcmpistri", { XM, EXx, Ib } },
3235 { "(bad)", { XX } },
3236 },
3237
3238 /* PREFIX_0F3ADF */
3239 {
3240 { "(bad)", { XX } },
3241 { "(bad)", { XX } },
3242 { "aeskeygenassist", { XM, EXx, Ib } },
3243 { "(bad)", { XX } },
3244 },
3245
3246 /* PREFIX_VEX_10 */
3247 {
3248 { "vmovups", { XM, EXx } },
3249 { VEX_LEN_TABLE (VEX_LEN_10_P_1) },
3250 { "vmovupd", { XM, EXx } },
3251 { VEX_LEN_TABLE (VEX_LEN_10_P_3) },
3252 },
3253
3254 /* PREFIX_VEX_11 */
3255 {
3256 { "vmovups", { EXx, XM } },
3257 { VEX_LEN_TABLE (VEX_LEN_11_P_1) },
3258 { "vmovupd", { EXx, XM } },
3259 { VEX_LEN_TABLE (VEX_LEN_11_P_3) },
3260 },
3261
3262 /* PREFIX_VEX_12 */
3263 {
3264 { MOD_TABLE (MOD_VEX_12_PREFIX_0) },
3265 { "vmovsldup", { XM, EXx } },
3266 { VEX_LEN_TABLE (VEX_LEN_12_P_2) },
3267 { "vmovddup", { XM, EXymmq } },
3268 },
3269
3270 /* PREFIX_VEX_16 */
3271 {
3272 { MOD_TABLE (MOD_VEX_16_PREFIX_0) },
3273 { "vmovshdup", { XM, EXx } },
3274 { VEX_LEN_TABLE (VEX_LEN_16_P_2) },
3275 { "(bad)", { XX } },
3276 },
3277
3278 /* PREFIX_VEX_2A */
3279 {
3280 { "(bad)", { XX } },
3281 { VEX_LEN_TABLE (VEX_LEN_2A_P_1) },
3282 { "(bad)", { XX } },
3283 { VEX_LEN_TABLE (VEX_LEN_2A_P_3) },
3284 },
3285
3286 /* PREFIX_VEX_2C */
3287 {
3288 { "(bad)", { XX } },
3289 { VEX_LEN_TABLE (VEX_LEN_2C_P_1) },
3290 { "(bad)", { XX } },
3291 { VEX_LEN_TABLE (VEX_LEN_2C_P_3) },
3292 },
3293
3294 /* PREFIX_VEX_2D */
3295 {
3296 { "(bad)", { XX } },
3297 { VEX_LEN_TABLE (VEX_LEN_2D_P_1) },
3298 { "(bad)", { XX } },
3299 { VEX_LEN_TABLE (VEX_LEN_2D_P_3) },
3300 },
3301
3302 /* PREFIX_VEX_2E */
3303 {
3304 { VEX_LEN_TABLE (VEX_LEN_2E_P_0) },
3305 { "(bad)", { XX } },
3306 { VEX_LEN_TABLE (VEX_LEN_2E_P_2) },
3307 { "(bad)", { XX } },
3308 },
3309
3310 /* PREFIX_VEX_2F */
3311 {
3312 { VEX_LEN_TABLE (VEX_LEN_2F_P_0) },
3313 { "(bad)", { XX } },
3314 { VEX_LEN_TABLE (VEX_LEN_2F_P_2) },
3315 { "(bad)", { XX } },
3316 },
3317
3318 /* PREFIX_VEX_51 */
3319 {
3320 { "vsqrtps", { XM, EXx } },
3321 { VEX_LEN_TABLE (VEX_LEN_51_P_1) },
3322 { "vsqrtpd", { XM, EXx } },
3323 { VEX_LEN_TABLE (VEX_LEN_51_P_3) },
3324 },
3325
3326 /* PREFIX_VEX_52 */
3327 {
3328 { "vrsqrtps", { XM, EXx } },
3329 { VEX_LEN_TABLE (VEX_LEN_52_P_1) },
3330 { "(bad)", { XX } },
3331 { "(bad)", { XX } },
3332 },
3333
3334 /* PREFIX_VEX_53 */
3335 {
3336 { "vrcpps", { XM, EXx } },
3337 { VEX_LEN_TABLE (VEX_LEN_53_P_1) },
3338 { "(bad)", { XX } },
3339 { "(bad)", { XX } },
3340 },
3341
3342 /* PREFIX_VEX_58 */
3343 {
3344 { "vaddps", { XM, Vex, EXx } },
3345 { VEX_LEN_TABLE (VEX_LEN_58_P_1) },
3346 { "vaddpd", { XM, Vex, EXx } },
3347 { VEX_LEN_TABLE (VEX_LEN_58_P_3) },
3348 },
3349
3350 /* PREFIX_VEX_59 */
3351 {
3352 { "vmulps", { XM, Vex, EXx } },
3353 { VEX_LEN_TABLE (VEX_LEN_59_P_1) },
3354 { "vmulpd", { XM, Vex, EXx } },
3355 { VEX_LEN_TABLE (VEX_LEN_59_P_3) },
3356 },
3357
3358 /* PREFIX_VEX_5A */
3359 {
3360 { "vcvtps2pd", { XM, EXxmmq } },
3361 { VEX_LEN_TABLE (VEX_LEN_5A_P_1) },
3362 { "vcvtpd2ps%XY", { XMM, EXx } },
3363 { VEX_LEN_TABLE (VEX_LEN_5A_P_3) },
3364 },
3365
3366 /* PREFIX_VEX_5B */
3367 {
3368 { "vcvtdq2ps", { XM, EXx } },
3369 { "vcvttps2dq", { XM, EXx } },
3370 { "vcvtps2dq", { XM, EXx } },
3371 { "(bad)", { XX } },
3372 },
3373
3374 /* PREFIX_VEX_5C */
3375 {
3376 { "vsubps", { XM, Vex, EXx } },
3377 { VEX_LEN_TABLE (VEX_LEN_5C_P_1) },
3378 { "vsubpd", { XM, Vex, EXx } },
3379 { VEX_LEN_TABLE (VEX_LEN_5C_P_3) },
3380 },
3381
3382 /* PREFIX_VEX_5D */
3383 {
3384 { "vminps", { XM, Vex, EXx } },
3385 { VEX_LEN_TABLE (VEX_LEN_5D_P_1) },
3386 { "vminpd", { XM, Vex, EXx } },
3387 { VEX_LEN_TABLE (VEX_LEN_5D_P_3) },
3388 },
3389
3390 /* PREFIX_VEX_5E */
3391 {
3392 { "vdivps", { XM, Vex, EXx } },
3393 { VEX_LEN_TABLE (VEX_LEN_5E_P_1) },
3394 { "vdivpd", { XM, Vex, EXx } },
3395 { VEX_LEN_TABLE (VEX_LEN_5E_P_3) },
3396 },
3397
3398 /* PREFIX_VEX_5F */
3399 {
3400 { "vmaxps", { XM, Vex, EXx } },
3401 { VEX_LEN_TABLE (VEX_LEN_5F_P_1) },
3402 { "vmaxpd", { XM, Vex, EXx } },
3403 { VEX_LEN_TABLE (VEX_LEN_5F_P_3) },
3404 },
3405
3406 /* PREFIX_VEX_60 */
3407 {
3408 { "(bad)", { XX } },
3409 { "(bad)", { XX } },
3410 { VEX_LEN_TABLE (VEX_LEN_60_P_2) },
3411 { "(bad)", { XX } },
3412 },
3413
3414 /* PREFIX_VEX_61 */
3415 {
3416 { "(bad)", { XX } },
3417 { "(bad)", { XX } },
3418 { VEX_LEN_TABLE (VEX_LEN_61_P_2) },
3419 { "(bad)", { XX } },
3420 },
3421
3422 /* PREFIX_VEX_62 */
3423 {
3424 { "(bad)", { XX } },
3425 { "(bad)", { XX } },
3426 { VEX_LEN_TABLE (VEX_LEN_62_P_2) },
3427 { "(bad)", { XX } },
3428 },
3429
3430 /* PREFIX_VEX_63 */
3431 {
3432 { "(bad)", { XX } },
3433 { "(bad)", { XX } },
3434 { VEX_LEN_TABLE (VEX_LEN_63_P_2) },
3435 { "(bad)", { XX } },
3436 },
3437
3438 /* PREFIX_VEX_64 */
3439 {
3440 { "(bad)", { XX } },
3441 { "(bad)", { XX } },
3442 { VEX_LEN_TABLE (VEX_LEN_64_P_2) },
3443 { "(bad)", { XX } },
3444 },
3445
3446 /* PREFIX_VEX_65 */
3447 {
3448 { "(bad)", { XX } },
3449 { "(bad)", { XX } },
3450 { VEX_LEN_TABLE (VEX_LEN_65_P_2) },
3451 { "(bad)", { XX } },
3452 },
3453
3454 /* PREFIX_VEX_66 */
3455 {
3456 { "(bad)", { XX } },
3457 { "(bad)", { XX } },
3458 { VEX_LEN_TABLE (VEX_LEN_66_P_2) },
3459 { "(bad)", { XX } },
3460 },
3461
3462 /* PREFIX_VEX_67 */
3463 {
3464 { "(bad)", { XX } },
3465 { "(bad)", { XX } },
3466 { VEX_LEN_TABLE (VEX_LEN_67_P_2) },
3467 { "(bad)", { XX } },
3468 },
3469
3470 /* PREFIX_VEX_68 */
3471 {
3472 { "(bad)", { XX } },
3473 { "(bad)", { XX } },
3474 { VEX_LEN_TABLE (VEX_LEN_68_P_2) },
3475 { "(bad)", { XX } },
3476 },
3477
3478 /* PREFIX_VEX_69 */
3479 {
3480 { "(bad)", { XX } },
3481 { "(bad)", { XX } },
3482 { VEX_LEN_TABLE (VEX_LEN_69_P_2) },
3483 { "(bad)", { XX } },
3484 },
3485
3486 /* PREFIX_VEX_6A */
3487 {
3488 { "(bad)", { XX } },
3489 { "(bad)", { XX } },
3490 { VEX_LEN_TABLE (VEX_LEN_6A_P_2) },
3491 { "(bad)", { XX } },
3492 },
3493
3494 /* PREFIX_VEX_6B */
3495 {
3496 { "(bad)", { XX } },
3497 { "(bad)", { XX } },
3498 { VEX_LEN_TABLE (VEX_LEN_6B_P_2) },
3499 { "(bad)", { XX } },
3500 },
3501
3502 /* PREFIX_VEX_6C */
3503 {
3504 { "(bad)", { XX } },
3505 { "(bad)", { XX } },
3506 { VEX_LEN_TABLE (VEX_LEN_6C_P_2) },
3507 { "(bad)", { XX } },
3508 },
3509
3510 /* PREFIX_VEX_6D */
3511 {
3512 { "(bad)", { XX } },
3513 { "(bad)", { XX } },
3514 { VEX_LEN_TABLE (VEX_LEN_6D_P_2) },
3515 { "(bad)", { XX } },
3516 },
3517
3518 /* PREFIX_VEX_6E */
3519 {
3520 { "(bad)", { XX } },
3521 { "(bad)", { XX } },
3522 { VEX_LEN_TABLE (VEX_LEN_6E_P_2) },
3523 { "(bad)", { XX } },
3524 },
3525
3526 /* PREFIX_VEX_6F */
3527 {
3528 { "(bad)", { XX } },
3529 { "vmovdqu", { XM, EXx } },
3530 { "vmovdqa", { XM, EXx } },
3531 { "(bad)", { XX } },
3532 },
3533
3534 /* PREFIX_VEX_70 */
3535 {
3536 { "(bad)", { XX } },
3537 { VEX_LEN_TABLE (VEX_LEN_70_P_1) },
3538 { VEX_LEN_TABLE (VEX_LEN_70_P_2) },
3539 { VEX_LEN_TABLE (VEX_LEN_70_P_3) },
3540 },
3541
3542 /* PREFIX_VEX_71_REG_2 */
3543 {
3544 { "(bad)", { XX } },
3545 { "(bad)", { XX } },
3546 { VEX_LEN_TABLE (VEX_LEN_71_R_2_P_2) },
3547 { "(bad)", { XX } },
3548 },
3549
3550 /* PREFIX_VEX_71_REG_4 */
3551 {
3552 { "(bad)", { XX } },
3553 { "(bad)", { XX } },
3554 { VEX_LEN_TABLE (VEX_LEN_71_R_4_P_2) },
3555 { "(bad)", { XX } },
3556 },
3557
3558 /* PREFIX_VEX_71_REG_6 */
3559 {
3560 { "(bad)", { XX } },
3561 { "(bad)", { XX } },
3562 { VEX_LEN_TABLE (VEX_LEN_71_R_6_P_2) },
3563 { "(bad)", { XX } },
3564 },
3565
3566 /* PREFIX_VEX_72_REG_2 */
3567 {
3568 { "(bad)", { XX } },
3569 { "(bad)", { XX } },
3570 { VEX_LEN_TABLE (VEX_LEN_72_R_2_P_2) },
3571 { "(bad)", { XX } },
3572 },
3573
3574 /* PREFIX_VEX_72_REG_4 */
3575 {
3576 { "(bad)", { XX } },
3577 { "(bad)", { XX } },
3578 { VEX_LEN_TABLE (VEX_LEN_72_R_4_P_2) },
3579 { "(bad)", { XX } },
3580 },
3581
3582 /* PREFIX_VEX_72_REG_6 */
3583 {
3584 { "(bad)", { XX } },
3585 { "(bad)", { XX } },
3586 { VEX_LEN_TABLE (VEX_LEN_72_R_6_P_2) },
3587 { "(bad)", { XX } },
3588 },
3589
3590 /* PREFIX_VEX_73_REG_2 */
3591 {
3592 { "(bad)", { XX } },
3593 { "(bad)", { XX } },
3594 { VEX_LEN_TABLE (VEX_LEN_73_R_2_P_2) },
3595 { "(bad)", { XX } },
3596 },
3597
3598 /* PREFIX_VEX_73_REG_3 */
3599 {
3600 { "(bad)", { XX } },
3601 { "(bad)", { XX } },
3602 { VEX_LEN_TABLE (VEX_LEN_73_R_3_P_2) },
3603 { "(bad)", { XX } },
3604 },
3605
3606 /* PREFIX_VEX_73_REG_6 */
3607 {
3608 { "(bad)", { XX } },
3609 { "(bad)", { XX } },
3610 { VEX_LEN_TABLE (VEX_LEN_73_R_6_P_2) },
3611 { "(bad)", { XX } },
3612 },
3613
3614 /* PREFIX_VEX_73_REG_7 */
3615 {
3616 { "(bad)", { XX } },
3617 { "(bad)", { XX } },
3618 { VEX_LEN_TABLE (VEX_LEN_73_R_7_P_2) },
3619 { "(bad)", { XX } },
3620 },
3621
3622 /* PREFIX_VEX_74 */
3623 {
3624 { "(bad)", { XX } },
3625 { "(bad)", { XX } },
3626 { VEX_LEN_TABLE (VEX_LEN_74_P_2) },
3627 { "(bad)", { XX } },
3628 },
3629
3630 /* PREFIX_VEX_75 */
3631 {
3632 { "(bad)", { XX } },
3633 { "(bad)", { XX } },
3634 { VEX_LEN_TABLE (VEX_LEN_75_P_2) },
3635 { "(bad)", { XX } },
3636 },
3637
3638 /* PREFIX_VEX_76 */
3639 {
3640 { "(bad)", { XX } },
3641 { "(bad)", { XX } },
3642 { VEX_LEN_TABLE (VEX_LEN_76_P_2) },
3643 { "(bad)", { XX } },
3644 },
3645
3646 /* PREFIX_VEX_77 */
3647 {
3648 { "", { VZERO } },
3649 { "(bad)", { XX } },
3650 { "(bad)", { XX } },
3651 { "(bad)", { XX } },
3652 },
3653
3654 /* PREFIX_VEX_7C */
3655 {
3656 { "(bad)", { XX } },
3657 { "(bad)", { XX } },
3658 { "vhaddpd", { XM, Vex, EXx } },
3659 { "vhaddps", { XM, Vex, EXx } },
3660 },
3661
3662 /* PREFIX_VEX_7D */
3663 {
3664 { "(bad)", { XX } },
3665 { "(bad)", { XX } },
3666 { "vhsubpd", { XM, Vex, EXx } },
3667 { "vhsubps", { XM, Vex, EXx } },
3668 },
3669
3670 /* PREFIX_VEX_7E */
3671 {
3672 { "(bad)", { XX } },
3673 { VEX_LEN_TABLE (VEX_LEN_7E_P_1) },
3674 { VEX_LEN_TABLE (VEX_LEN_7E_P_2) },
3675 { "(bad)", { XX } },
3676 },
3677
3678 /* PREFIX_VEX_7F */
3679 {
3680 { "(bad)", { XX } },
3681 { "vmovdqu", { EXx, XM } },
3682 { "vmovdqa", { EXx, XM } },
3683 { "(bad)", { XX } },
3684 },
3685
3686 /* PREFIX_VEX_C2 */
3687 {
3688 { "vcmpps", { XM, Vex, EXx, VCMP } },
3689 { VEX_LEN_TABLE (VEX_LEN_C2_P_1) },
3690 { "vcmppd", { XM, Vex, EXx, VCMP } },
3691 { VEX_LEN_TABLE (VEX_LEN_C2_P_3) },
3692 },
3693
3694 /* PREFIX_VEX_C4 */
3695 {
3696 { "(bad)", { XX } },
3697 { "(bad)", { XX } },
3698 { VEX_LEN_TABLE (VEX_LEN_C4_P_2) },
3699 { "(bad)", { XX } },
3700 },
3701
3702 /* PREFIX_VEX_C5 */
3703 {
3704 { "(bad)", { XX } },
3705 { "(bad)", { XX } },
3706 { VEX_LEN_TABLE (VEX_LEN_C5_P_2) },
3707 { "(bad)", { XX } },
3708 },
3709
3710 /* PREFIX_VEX_D0 */
3711 {
3712 { "(bad)", { XX } },
3713 { "(bad)", { XX } },
3714 { "vaddsubpd", { XM, Vex, EXx } },
3715 { "vaddsubps", { XM, Vex, EXx } },
3716 },
3717
3718 /* PREFIX_VEX_D1 */
3719 {
3720 { "(bad)", { XX } },
3721 { "(bad)", { XX } },
3722 { VEX_LEN_TABLE (VEX_LEN_D1_P_2) },
3723 { "(bad)", { XX } },
3724 },
3725
3726 /* PREFIX_VEX_D2 */
3727 {
3728 { "(bad)", { XX } },
3729 { "(bad)", { XX } },
3730 { VEX_LEN_TABLE (VEX_LEN_D2_P_2) },
3731 { "(bad)", { XX } },
3732 },
3733
3734 /* PREFIX_VEX_D3 */
3735 {
3736 { "(bad)", { XX } },
3737 { "(bad)", { XX } },
3738 { VEX_LEN_TABLE (VEX_LEN_D3_P_2) },
3739 { "(bad)", { XX } },
3740 },
3741
3742 /* PREFIX_VEX_D4 */
3743 {
3744 { "(bad)", { XX } },
3745 { "(bad)", { XX } },
3746 { VEX_LEN_TABLE (VEX_LEN_D4_P_2) },
3747 { "(bad)", { XX } },
3748 },
3749
3750 /* PREFIX_VEX_D5 */
3751 {
3752 { "(bad)", { XX } },
3753 { "(bad)", { XX } },
3754 { VEX_LEN_TABLE (VEX_LEN_D5_P_2) },
3755 { "(bad)", { XX } },
3756 },
3757
3758 /* PREFIX_VEX_D6 */
3759 {
3760 { "(bad)", { XX } },
3761 { "(bad)", { XX } },
3762 { VEX_LEN_TABLE (VEX_LEN_D6_P_2) },
3763 { "(bad)", { XX } },
3764 },
3765
3766 /* PREFIX_VEX_D7 */
3767 {
3768 { "(bad)", { XX } },
3769 { "(bad)", { XX } },
3770 { MOD_TABLE (MOD_VEX_D7_PREFIX_2) },
3771 { "(bad)", { XX } },
3772 },
3773
3774 /* PREFIX_VEX_D8 */
3775 {
3776 { "(bad)", { XX } },
3777 { "(bad)", { XX } },
3778 { VEX_LEN_TABLE (VEX_LEN_D8_P_2) },
3779 { "(bad)", { XX } },
3780 },
3781
3782 /* PREFIX_VEX_D9 */
3783 {
3784 { "(bad)", { XX } },
3785 { "(bad)", { XX } },
3786 { VEX_LEN_TABLE (VEX_LEN_D9_P_2) },
3787 { "(bad)", { XX } },
3788 },
3789
3790 /* PREFIX_VEX_DA */
3791 {
3792 { "(bad)", { XX } },
3793 { "(bad)", { XX } },
3794 { VEX_LEN_TABLE (VEX_LEN_DA_P_2) },
3795 { "(bad)", { XX } },
3796 },
3797
3798 /* PREFIX_VEX_DB */
3799 {
3800 { "(bad)", { XX } },
3801 { "(bad)", { XX } },
3802 { VEX_LEN_TABLE (VEX_LEN_DB_P_2) },
3803 { "(bad)", { XX } },
3804 },
3805
3806 /* PREFIX_VEX_DC */
3807 {
3808 { "(bad)", { XX } },
3809 { "(bad)", { XX } },
3810 { VEX_LEN_TABLE (VEX_LEN_DC_P_2) },
3811 { "(bad)", { XX } },
3812 },
3813
3814 /* PREFIX_VEX_DD */
3815 {
3816 { "(bad)", { XX } },
3817 { "(bad)", { XX } },
3818 { VEX_LEN_TABLE (VEX_LEN_DD_P_2) },
3819 { "(bad)", { XX } },
3820 },
3821
3822 /* PREFIX_VEX_DE */
3823 {
3824 { "(bad)", { XX } },
3825 { "(bad)", { XX } },
3826 { VEX_LEN_TABLE (VEX_LEN_DE_P_2) },
3827 { "(bad)", { XX } },
3828 },
3829
3830 /* PREFIX_VEX_DF */
3831 {
3832 { "(bad)", { XX } },
3833 { "(bad)", { XX } },
3834 { VEX_LEN_TABLE (VEX_LEN_DF_P_2) },
3835 { "(bad)", { XX } },
3836 },
3837
3838 /* PREFIX_VEX_E0 */
3839 {
3840 { "(bad)", { XX } },
3841 { "(bad)", { XX } },
3842 { VEX_LEN_TABLE (VEX_LEN_E0_P_2) },
3843 { "(bad)", { XX } },
3844 },
3845
3846 /* PREFIX_VEX_E1 */
3847 {
3848 { "(bad)", { XX } },
3849 { "(bad)", { XX } },
3850 { VEX_LEN_TABLE (VEX_LEN_E1_P_2) },
3851 { "(bad)", { XX } },
3852 },
3853
3854 /* PREFIX_VEX_E2 */
3855 {
3856 { "(bad)", { XX } },
3857 { "(bad)", { XX } },
3858 { VEX_LEN_TABLE (VEX_LEN_E2_P_2) },
3859 { "(bad)", { XX } },
3860 },
3861
3862 /* PREFIX_VEX_E3 */
3863 {
3864 { "(bad)", { XX } },
3865 { "(bad)", { XX } },
3866 { VEX_LEN_TABLE (VEX_LEN_E3_P_2) },
3867 { "(bad)", { XX } },
3868 },
3869
3870 /* PREFIX_VEX_E4 */
3871 {
3872 { "(bad)", { XX } },
3873 { "(bad)", { XX } },
3874 { VEX_LEN_TABLE (VEX_LEN_E4_P_2) },
3875 { "(bad)", { XX } },
3876 },
3877
3878 /* PREFIX_VEX_E5 */
3879 {
3880 { "(bad)", { XX } },
3881 { "(bad)", { XX } },
3882 { VEX_LEN_TABLE (VEX_LEN_E5_P_2) },
3883 { "(bad)", { XX } },
3884 },
3885
3886 /* PREFIX_VEX_E6 */
3887 {
3888 { "(bad)", { XX } },
3889 { "vcvtdq2pd", { XM, EXxmmq } },
3890 { "vcvttpd2dq%XY", { XMM, EXx } },
3891 { "vcvtpd2dq%XY", { XMM, EXx } },
3892 },
3893
3894 /* PREFIX_VEX_E7 */
3895 {
3896 { "(bad)", { XX } },
3897 { "(bad)", { XX } },
3898 { MOD_TABLE (MOD_VEX_E7_PREFIX_2) },
3899 { "(bad)", { XX } },
3900 },
3901
3902 /* PREFIX_VEX_E8 */
3903 {
3904 { "(bad)", { XX } },
3905 { "(bad)", { XX } },
3906 { VEX_LEN_TABLE (VEX_LEN_E8_P_2) },
3907 { "(bad)", { XX } },
3908 },
3909
3910 /* PREFIX_VEX_E9 */
3911 {
3912 { "(bad)", { XX } },
3913 { "(bad)", { XX } },
3914 { VEX_LEN_TABLE (VEX_LEN_E9_P_2) },
3915 { "(bad)", { XX } },
3916 },
3917
3918 /* PREFIX_VEX_EA */
3919 {
3920 { "(bad)", { XX } },
3921 { "(bad)", { XX } },
3922 { VEX_LEN_TABLE (VEX_LEN_EA_P_2) },
3923 { "(bad)", { XX } },
3924 },
3925
3926 /* PREFIX_VEX_EB */
3927 {
3928 { "(bad)", { XX } },
3929 { "(bad)", { XX } },
3930 { VEX_LEN_TABLE (VEX_LEN_EB_P_2) },
3931 { "(bad)", { XX } },
3932 },
3933
3934 /* PREFIX_VEX_EC */
3935 {
3936 { "(bad)", { XX } },
3937 { "(bad)", { XX } },
3938 { VEX_LEN_TABLE (VEX_LEN_EC_P_2) },
3939 { "(bad)", { XX } },
3940 },
3941
3942 /* PREFIX_VEX_ED */
3943 {
3944 { "(bad)", { XX } },
3945 { "(bad)", { XX } },
3946 { VEX_LEN_TABLE (VEX_LEN_ED_P_2) },
3947 { "(bad)", { XX } },
3948 },
3949
3950 /* PREFIX_VEX_EE */
3951 {
3952 { "(bad)", { XX } },
3953 { "(bad)", { XX } },
3954 { VEX_LEN_TABLE (VEX_LEN_EE_P_2) },
3955 { "(bad)", { XX } },
3956 },
3957
3958 /* PREFIX_VEX_EF */
3959 {
3960 { "(bad)", { XX } },
3961 { "(bad)", { XX } },
3962 { VEX_LEN_TABLE (VEX_LEN_EF_P_2) },
3963 { "(bad)", { XX } },
3964 },
3965
3966 /* PREFIX_VEX_F0 */
3967 {
3968 { "(bad)", { XX } },
3969 { "(bad)", { XX } },
3970 { "(bad)", { XX } },
3971 { MOD_TABLE (MOD_VEX_F0_PREFIX_3) },
3972 },
3973
3974 /* PREFIX_VEX_F1 */
3975 {
3976 { "(bad)", { XX } },
3977 { "(bad)", { XX } },
3978 { VEX_LEN_TABLE (VEX_LEN_F1_P_2) },
3979 { "(bad)", { XX } },
3980 },
3981
3982 /* PREFIX_VEX_F2 */
3983 {
3984 { "(bad)", { XX } },
3985 { "(bad)", { XX } },
3986 { VEX_LEN_TABLE (VEX_LEN_F2_P_2) },
3987 { "(bad)", { XX } },
3988 },
3989
3990 /* PREFIX_VEX_F3 */
3991 {
3992 { "(bad)", { XX } },
3993 { "(bad)", { XX } },
3994 { VEX_LEN_TABLE (VEX_LEN_F3_P_2) },
3995 { "(bad)", { XX } },
3996 },
3997
3998 /* PREFIX_VEX_F4 */
3999 {
4000 { "(bad)", { XX } },
4001 { "(bad)", { XX } },
4002 { VEX_LEN_TABLE (VEX_LEN_F4_P_2) },
4003 { "(bad)", { XX } },
4004 },
4005
4006 /* PREFIX_VEX_F5 */
4007 {
4008 { "(bad)", { XX } },
4009 { "(bad)", { XX } },
4010 { VEX_LEN_TABLE (VEX_LEN_F5_P_2) },
4011 { "(bad)", { XX } },
4012 },
4013
4014 /* PREFIX_VEX_F6 */
4015 {
4016 { "(bad)", { XX } },
4017 { "(bad)", { XX } },
4018 { VEX_LEN_TABLE (VEX_LEN_F6_P_2) },
4019 { "(bad)", { XX } },
4020 },
4021
4022 /* PREFIX_VEX_F7 */
4023 {
4024 { "(bad)", { XX } },
4025 { "(bad)", { XX } },
4026 { VEX_LEN_TABLE (VEX_LEN_F7_P_2) },
4027 { "(bad)", { XX } },
4028 },
4029
4030 /* PREFIX_VEX_F8 */
4031 {
4032 { "(bad)", { XX } },
4033 { "(bad)", { XX } },
4034 { VEX_LEN_TABLE (VEX_LEN_F8_P_2) },
4035 { "(bad)", { XX } },
4036 },
4037
4038 /* PREFIX_VEX_F9 */
4039 {
4040 { "(bad)", { XX } },
4041 { "(bad)", { XX } },
4042 { VEX_LEN_TABLE (VEX_LEN_F9_P_2) },
4043 { "(bad)", { XX } },
4044 },
4045
4046 /* PREFIX_VEX_FA */
4047 {
4048 { "(bad)", { XX } },
4049 { "(bad)", { XX } },
4050 { VEX_LEN_TABLE (VEX_LEN_FA_P_2) },
4051 { "(bad)", { XX } },
4052 },
4053
4054 /* PREFIX_VEX_FB */
4055 {
4056 { "(bad)", { XX } },
4057 { "(bad)", { XX } },
4058 { VEX_LEN_TABLE (VEX_LEN_FB_P_2) },
4059 { "(bad)", { XX } },
4060 },
4061
4062 /* PREFIX_VEX_FC */
4063 {
4064 { "(bad)", { XX } },
4065 { "(bad)", { XX } },
4066 { VEX_LEN_TABLE (VEX_LEN_FC_P_2) },
4067 { "(bad)", { XX } },
4068 },
4069
4070 /* PREFIX_VEX_FD */
4071 {
4072 { "(bad)", { XX } },
4073 { "(bad)", { XX } },
4074 { VEX_LEN_TABLE (VEX_LEN_FD_P_2) },
4075 { "(bad)", { XX } },
4076 },
4077
4078 /* PREFIX_VEX_FE */
4079 {
4080 { "(bad)", { XX } },
4081 { "(bad)", { XX } },
4082 { VEX_LEN_TABLE (VEX_LEN_FE_P_2) },
4083 { "(bad)", { XX } },
4084 },
4085
4086 /* PREFIX_VEX_3800 */
4087 {
4088 { "(bad)", { XX } },
4089 { "(bad)", { XX } },
4090 { VEX_LEN_TABLE (VEX_LEN_3800_P_2) },
4091 { "(bad)", { XX } },
4092 },
4093
4094 /* PREFIX_VEX_3801 */
4095 {
4096 { "(bad)", { XX } },
4097 { "(bad)", { XX } },
4098 { VEX_LEN_TABLE (VEX_LEN_3801_P_2) },
4099 { "(bad)", { XX } },
4100 },
4101
4102 /* PREFIX_VEX_3802 */
4103 {
4104 { "(bad)", { XX } },
4105 { "(bad)", { XX } },
4106 { VEX_LEN_TABLE (VEX_LEN_3802_P_2) },
4107 { "(bad)", { XX } },
4108 },
4109
4110 /* PREFIX_VEX_3803 */
4111 {
4112 { "(bad)", { XX } },
4113 { "(bad)", { XX } },
4114 { VEX_LEN_TABLE (VEX_LEN_3803_P_2) },
4115 { "(bad)", { XX } },
4116 },
4117
4118 /* PREFIX_VEX_3804 */
4119 {
4120 { "(bad)", { XX } },
4121 { "(bad)", { XX } },
4122 { VEX_LEN_TABLE (VEX_LEN_3804_P_2) },
4123 { "(bad)", { XX } },
4124 },
4125
4126 /* PREFIX_VEX_3805 */
4127 {
4128 { "(bad)", { XX } },
4129 { "(bad)", { XX } },
4130 { VEX_LEN_TABLE (VEX_LEN_3805_P_2) },
4131 { "(bad)", { XX } },
4132 },
4133
4134 /* PREFIX_VEX_3806 */
4135 {
4136 { "(bad)", { XX } },
4137 { "(bad)", { XX } },
4138 { VEX_LEN_TABLE (VEX_LEN_3806_P_2) },
4139 { "(bad)", { XX } },
4140 },
4141
4142 /* PREFIX_VEX_3807 */
4143 {
4144 { "(bad)", { XX } },
4145 { "(bad)", { XX } },
4146 { VEX_LEN_TABLE (VEX_LEN_3807_P_2) },
4147 { "(bad)", { XX } },
4148 },
4149
4150 /* PREFIX_VEX_3808 */
4151 {
4152 { "(bad)", { XX } },
4153 { "(bad)", { XX } },
4154 { VEX_LEN_TABLE (VEX_LEN_3808_P_2) },
4155 { "(bad)", { XX } },
4156 },
4157
4158 /* PREFIX_VEX_3809 */
4159 {
4160 { "(bad)", { XX } },
4161 { "(bad)", { XX } },
4162 { VEX_LEN_TABLE (VEX_LEN_3809_P_2) },
4163 { "(bad)", { XX } },
4164 },
4165
4166 /* PREFIX_VEX_380A */
4167 {
4168 { "(bad)", { XX } },
4169 { "(bad)", { XX } },
4170 { VEX_LEN_TABLE (VEX_LEN_380A_P_2) },
4171 { "(bad)", { XX } },
4172 },
4173
4174 /* PREFIX_VEX_380B */
4175 {
4176 { "(bad)", { XX } },
4177 { "(bad)", { XX } },
4178 { VEX_LEN_TABLE (VEX_LEN_380B_P_2) },
4179 { "(bad)", { XX } },
4180 },
4181
4182 /* PREFIX_VEX_380C */
4183 {
4184 { "(bad)", { XX } },
4185 { "(bad)", { XX } },
4186 { "vpermilps", { XM, Vex, EXx } },
4187 { "(bad)", { XX } },
4188 },
4189
4190 /* PREFIX_VEX_380D */
4191 {
4192 { "(bad)", { XX } },
4193 { "(bad)", { XX } },
4194 { "vpermilpd", { XM, Vex, EXx } },
4195 { "(bad)", { XX } },
4196 },
4197
4198 /* PREFIX_VEX_380E */
4199 {
4200 { "(bad)", { XX } },
4201 { "(bad)", { XX } },
4202 { "vtestps", { XM, EXx } },
4203 { "(bad)", { XX } },
4204 },
4205
4206 /* PREFIX_VEX_380F */
4207 {
4208 { "(bad)", { XX } },
4209 { "(bad)", { XX } },
4210 { "vtestpd", { XM, EXx } },
4211 { "(bad)", { XX } },
4212 },
4213
4214 /* PREFIX_VEX_3817 */
4215 {
4216 { "(bad)", { XX } },
4217 { "(bad)", { XX } },
4218 { "vptest", { XM, EXx } },
4219 { "(bad)", { XX } },
4220 },
4221
4222 /* PREFIX_VEX_3818 */
4223 {
4224 { "(bad)", { XX } },
4225 { "(bad)", { XX } },
4226 { MOD_TABLE (MOD_VEX_3818_PREFIX_2) },
4227 { "(bad)", { XX } },
4228 },
4229
4230 /* PREFIX_VEX_3819 */
4231 {
4232 { "(bad)", { XX } },
4233 { "(bad)", { XX } },
4234 { MOD_TABLE (MOD_VEX_3819_PREFIX_2) },
4235 { "(bad)", { XX } },
4236 },
4237
4238 /* PREFIX_VEX_381A */
4239 {
4240 { "(bad)", { XX } },
4241 { "(bad)", { XX } },
4242 { MOD_TABLE (MOD_VEX_381A_PREFIX_2) },
4243 { "(bad)", { XX } },
4244 },
4245
4246 /* PREFIX_VEX_381C */
4247 {
4248 { "(bad)", { XX } },
4249 { "(bad)", { XX } },
4250 { VEX_LEN_TABLE (VEX_LEN_381C_P_2) },
4251 { "(bad)", { XX } },
4252 },
4253
4254 /* PREFIX_VEX_381D */
4255 {
4256 { "(bad)", { XX } },
4257 { "(bad)", { XX } },
4258 { VEX_LEN_TABLE (VEX_LEN_381D_P_2) },
4259 { "(bad)", { XX } },
4260 },
4261
4262 /* PREFIX_VEX_381E */
4263 {
4264 { "(bad)", { XX } },
4265 { "(bad)", { XX } },
4266 { VEX_LEN_TABLE (VEX_LEN_381E_P_2) },
4267 { "(bad)", { XX } },
4268 },
4269
4270 /* PREFIX_VEX_3820 */
4271 {
4272 { "(bad)", { XX } },
4273 { "(bad)", { XX } },
4274 { VEX_LEN_TABLE (VEX_LEN_3820_P_2) },
4275 { "(bad)", { XX } },
4276 },
4277
4278 /* PREFIX_VEX_3821 */
4279 {
4280 { "(bad)", { XX } },
4281 { "(bad)", { XX } },
4282 { VEX_LEN_TABLE (VEX_LEN_3821_P_2) },
4283 { "(bad)", { XX } },
4284 },
4285
4286 /* PREFIX_VEX_3822 */
4287 {
4288 { "(bad)", { XX } },
4289 { "(bad)", { XX } },
4290 { VEX_LEN_TABLE (VEX_LEN_3822_P_2) },
4291 { "(bad)", { XX } },
4292 },
4293
4294 /* PREFIX_VEX_3823 */
4295 {
4296 { "(bad)", { XX } },
4297 { "(bad)", { XX } },
4298 { VEX_LEN_TABLE (VEX_LEN_3823_P_2) },
4299 { "(bad)", { XX } },
4300 },
4301
4302 /* PREFIX_VEX_3824 */
4303 {
4304 { "(bad)", { XX } },
4305 { "(bad)", { XX } },
4306 { VEX_LEN_TABLE (VEX_LEN_3824_P_2) },
4307 { "(bad)", { XX } },
4308 },
4309
4310 /* PREFIX_VEX_3825 */
4311 {
4312 { "(bad)", { XX } },
4313 { "(bad)", { XX } },
4314 { VEX_LEN_TABLE (VEX_LEN_3825_P_2) },
4315 { "(bad)", { XX } },
4316 },
4317
4318 /* PREFIX_VEX_3828 */
4319 {
4320 { "(bad)", { XX } },
4321 { "(bad)", { XX } },
4322 { VEX_LEN_TABLE (VEX_LEN_3828_P_2) },
4323 { "(bad)", { XX } },
4324 },
4325
4326 /* PREFIX_VEX_3829 */
4327 {
4328 { "(bad)", { XX } },
4329 { "(bad)", { XX } },
4330 { VEX_LEN_TABLE (VEX_LEN_3829_P_2) },
4331 { "(bad)", { XX } },
4332 },
4333
4334 /* PREFIX_VEX_382A */
4335 {
4336 { "(bad)", { XX } },
4337 { "(bad)", { XX } },
4338 { MOD_TABLE (MOD_VEX_382A_PREFIX_2) },
4339 { "(bad)", { XX } },
4340 },
4341
4342 /* PREFIX_VEX_382B */
4343 {
4344 { "(bad)", { XX } },
4345 { "(bad)", { XX } },
4346 { VEX_LEN_TABLE (VEX_LEN_382B_P_2) },
4347 { "(bad)", { XX } },
4348 },
4349
4350 /* PREFIX_VEX_382C */
4351 {
4352 { "(bad)", { XX } },
4353 { "(bad)", { XX } },
4354 { MOD_TABLE (MOD_VEX_382C_PREFIX_2) },
4355 { "(bad)", { XX } },
4356 },
4357
4358 /* PREFIX_VEX_382D */
4359 {
4360 { "(bad)", { XX } },
4361 { "(bad)", { XX } },
4362 { MOD_TABLE (MOD_VEX_382D_PREFIX_2) },
4363 { "(bad)", { XX } },
4364 },
4365
4366 /* PREFIX_VEX_382E */
4367 {
4368 { "(bad)", { XX } },
4369 { "(bad)", { XX } },
4370 { MOD_TABLE (MOD_VEX_382E_PREFIX_2) },
4371 { "(bad)", { XX } },
4372 },
4373
4374 /* PREFIX_VEX_382F */
4375 {
4376 { "(bad)", { XX } },
4377 { "(bad)", { XX } },
4378 { MOD_TABLE (MOD_VEX_382F_PREFIX_2) },
4379 { "(bad)", { XX } },
4380 },
4381
4382 /* PREFIX_VEX_3830 */
4383 {
4384 { "(bad)", { XX } },
4385 { "(bad)", { XX } },
4386 { VEX_LEN_TABLE (VEX_LEN_3830_P_2) },
4387 { "(bad)", { XX } },
4388 },
4389
4390 /* PREFIX_VEX_3831 */
4391 {
4392 { "(bad)", { XX } },
4393 { "(bad)", { XX } },
4394 { VEX_LEN_TABLE (VEX_LEN_3831_P_2) },
4395 { "(bad)", { XX } },
4396 },
4397
4398 /* PREFIX_VEX_3832 */
4399 {
4400 { "(bad)", { XX } },
4401 { "(bad)", { XX } },
4402 { VEX_LEN_TABLE (VEX_LEN_3832_P_2) },
4403 { "(bad)", { XX } },
4404 },
4405
4406 /* PREFIX_VEX_3833 */
4407 {
4408 { "(bad)", { XX } },
4409 { "(bad)", { XX } },
4410 { VEX_LEN_TABLE (VEX_LEN_3833_P_2) },
4411 { "(bad)", { XX } },
4412 },
4413
4414 /* PREFIX_VEX_3834 */
4415 {
4416 { "(bad)", { XX } },
4417 { "(bad)", { XX } },
4418 { VEX_LEN_TABLE (VEX_LEN_3834_P_2) },
4419 { "(bad)", { XX } },
4420 },
4421
4422 /* PREFIX_VEX_3835 */
4423 {
4424 { "(bad)", { XX } },
4425 { "(bad)", { XX } },
4426 { VEX_LEN_TABLE (VEX_LEN_3835_P_2) },
4427 { "(bad)", { XX } },
4428 },
4429
4430 /* PREFIX_VEX_3837 */
4431 {
4432 { "(bad)", { XX } },
4433 { "(bad)", { XX } },
4434 { VEX_LEN_TABLE (VEX_LEN_3837_P_2) },
4435 { "(bad)", { XX } },
4436 },
4437
4438 /* PREFIX_VEX_3838 */
4439 {
4440 { "(bad)", { XX } },
4441 { "(bad)", { XX } },
4442 { VEX_LEN_TABLE (VEX_LEN_3838_P_2) },
4443 { "(bad)", { XX } },
4444 },
4445
4446 /* PREFIX_VEX_3839 */
4447 {
4448 { "(bad)", { XX } },
4449 { "(bad)", { XX } },
4450 { VEX_LEN_TABLE (VEX_LEN_3839_P_2) },
4451 { "(bad)", { XX } },
4452 },
4453
4454 /* PREFIX_VEX_383A */
4455 {
4456 { "(bad)", { XX } },
4457 { "(bad)", { XX } },
4458 { VEX_LEN_TABLE (VEX_LEN_383A_P_2) },
4459 { "(bad)", { XX } },
4460 },
4461
4462 /* PREFIX_VEX_383B */
4463 {
4464 { "(bad)", { XX } },
4465 { "(bad)", { XX } },
4466 { VEX_LEN_TABLE (VEX_LEN_383B_P_2) },
4467 { "(bad)", { XX } },
4468 },
4469
4470 /* PREFIX_VEX_383C */
4471 {
4472 { "(bad)", { XX } },
4473 { "(bad)", { XX } },
4474 { VEX_LEN_TABLE (VEX_LEN_383C_P_2) },
4475 { "(bad)", { XX } },
4476 },
4477
4478 /* PREFIX_VEX_383D */
4479 {
4480 { "(bad)", { XX } },
4481 { "(bad)", { XX } },
4482 { VEX_LEN_TABLE (VEX_LEN_383D_P_2) },
4483 { "(bad)", { XX } },
4484 },
4485
4486 /* PREFIX_VEX_383E */
4487 {
4488 { "(bad)", { XX } },
4489 { "(bad)", { XX } },
4490 { VEX_LEN_TABLE (VEX_LEN_383E_P_2) },
4491 { "(bad)", { XX } },
4492 },
4493
4494 /* PREFIX_VEX_383F */
4495 {
4496 { "(bad)", { XX } },
4497 { "(bad)", { XX } },
4498 { VEX_LEN_TABLE (VEX_LEN_383F_P_2) },
4499 { "(bad)", { XX } },
4500 },
4501
4502 /* PREFIX_VEX_3840 */
4503 {
4504 { "(bad)", { XX } },
4505 { "(bad)", { XX } },
4506 { VEX_LEN_TABLE (VEX_LEN_3840_P_2) },
4507 { "(bad)", { XX } },
4508 },
4509
4510 /* PREFIX_VEX_3841 */
4511 {
4512 { "(bad)", { XX } },
4513 { "(bad)", { XX } },
4514 { VEX_LEN_TABLE (VEX_LEN_3841_P_2) },
4515 { "(bad)", { XX } },
4516 },
4517
4518 /* PREFIX_VEX_3A04 */
4519 {
4520 { "(bad)", { XX } },
4521 { "(bad)", { XX } },
4522 { "vpermilps", { XM, EXx, Ib } },
4523 { "(bad)", { XX } },
4524 },
4525
4526 /* PREFIX_VEX_3A05 */
4527 {
4528 { "(bad)", { XX } },
4529 { "(bad)", { XX } },
4530 { "vpermilpd", { XM, EXx, Ib } },
4531 { "(bad)", { XX } },
4532 },
4533
4534 /* PREFIX_VEX_3A06 */
4535 {
4536 { "(bad)", { XX } },
4537 { "(bad)", { XX } },
4538 { VEX_LEN_TABLE (VEX_LEN_3A06_P_2) },
4539 { "(bad)", { XX } },
4540 },
4541
4542 /* PREFIX_VEX_3A08 */
4543 {
4544 { "(bad)", { XX } },
4545 { "(bad)", { XX } },
4546 { "vroundps", { XM, EXx, Ib } },
4547 { "(bad)", { XX } },
4548 },
4549
4550 /* PREFIX_VEX_3A09 */
4551 {
4552 { "(bad)", { XX } },
4553 { "(bad)", { XX } },
4554 { "vroundpd", { XM, EXx, Ib } },
4555 { "(bad)", { XX } },
4556 },
4557
4558 /* PREFIX_VEX_3A0A */
4559 {
4560 { "(bad)", { XX } },
4561 { "(bad)", { XX } },
4562 { VEX_LEN_TABLE (VEX_LEN_3A0A_P_2) },
4563 { "(bad)", { XX } },
4564 },
4565
4566 /* PREFIX_VEX_3A0B */
4567 {
4568 { "(bad)", { XX } },
4569 { "(bad)", { XX } },
4570 { VEX_LEN_TABLE (VEX_LEN_3A0B_P_2) },
4571 { "(bad)", { XX } },
4572 },
4573
4574 /* PREFIX_VEX_3A0C */
4575 {
4576 { "(bad)", { XX } },
4577 { "(bad)", { XX } },
4578 { "vblendps", { XM, Vex, EXx, Ib } },
4579 { "(bad)", { XX } },
4580 },
4581
4582 /* PREFIX_VEX_3A0D */
4583 {
4584 { "(bad)", { XX } },
4585 { "(bad)", { XX } },
4586 { "vblendpd", { XM, Vex, EXx, Ib } },
4587 { "(bad)", { XX } },
4588 },
4589
4590 /* PREFIX_VEX_3A0E */
4591 {
4592 { "(bad)", { XX } },
4593 { "(bad)", { XX } },
4594 { VEX_LEN_TABLE (VEX_LEN_3A0E_P_2) },
4595 { "(bad)", { XX } },
4596 },
4597
4598 /* PREFIX_VEX_3A0F */
4599 {
4600 { "(bad)", { XX } },
4601 { "(bad)", { XX } },
4602 { VEX_LEN_TABLE (VEX_LEN_3A0F_P_2) },
4603 { "(bad)", { XX } },
4604 },
4605
4606 /* PREFIX_VEX_3A14 */
4607 {
4608 { "(bad)", { XX } },
4609 { "(bad)", { XX } },
4610 { VEX_LEN_TABLE (VEX_LEN_3A14_P_2) },
4611 { "(bad)", { XX } },
4612 },
4613
4614 /* PREFIX_VEX_3A15 */
4615 {
4616 { "(bad)", { XX } },
4617 { "(bad)", { XX } },
4618 { VEX_LEN_TABLE (VEX_LEN_3A15_P_2) },
4619 { "(bad)", { XX } },
4620 },
4621
4622 /* PREFIX_VEX_3A16 */
4623 {
4624 { "(bad)", { XX } },
4625 { "(bad)", { XX } },
4626 { VEX_LEN_TABLE (VEX_LEN_3A16_P_2) },
4627 { "(bad)", { XX } },
4628 },
4629
4630 /* PREFIX_VEX_3A17 */
4631 {
4632 { "(bad)", { XX } },
4633 { "(bad)", { XX } },
4634 { VEX_LEN_TABLE (VEX_LEN_3A17_P_2) },
4635 { "(bad)", { XX } },
4636 },
4637
4638 /* PREFIX_VEX_3A18 */
4639 {
4640 { "(bad)", { XX } },
4641 { "(bad)", { XX } },
4642 { VEX_LEN_TABLE (VEX_LEN_3A18_P_2) },
4643 { "(bad)", { XX } },
4644 },
4645
4646 /* PREFIX_VEX_3A19 */
4647 {
4648 { "(bad)", { XX } },
4649 { "(bad)", { XX } },
4650 { VEX_LEN_TABLE (VEX_LEN_3A19_P_2) },
4651 { "(bad)", { XX } },
4652 },
4653
4654 /* PREFIX_VEX_3A20 */
4655 {
4656 { "(bad)", { XX } },
4657 { "(bad)", { XX } },
4658 { VEX_LEN_TABLE (VEX_LEN_3A20_P_2) },
4659 { "(bad)", { XX } },
4660 },
4661
4662 /* PREFIX_VEX_3A21 */
4663 {
4664 { "(bad)", { XX } },
4665 { "(bad)", { XX } },
4666 { VEX_LEN_TABLE (VEX_LEN_3A21_P_2) },
4667 { "(bad)", { XX } },
4668 },
4669
4670 /* PREFIX_VEX_3A22 */
4671 {
4672 { "(bad)", { XX } },
4673 { "(bad)", { XX } },
4674 { VEX_LEN_TABLE (VEX_LEN_3A22_P_2) },
4675 { "(bad)", { XX } },
4676 },
4677
4678 /* PREFIX_VEX_3A40 */
4679 {
4680 { "(bad)", { XX } },
4681 { "(bad)", { XX } },
4682 { "vdpps", { XM, Vex, EXx, Ib } },
4683 { "(bad)", { XX } },
4684 },
4685
4686 /* PREFIX_VEX_3A41 */
4687 {
4688 { "(bad)", { XX } },
4689 { "(bad)", { XX } },
4690 { VEX_LEN_TABLE (VEX_LEN_3A41_P_2) },
4691 { "(bad)", { XX } },
4692 },
4693
4694 /* PREFIX_VEX_3A42 */
4695 {
4696 { "(bad)", { XX } },
4697 { "(bad)", { XX } },
4698 { VEX_LEN_TABLE (VEX_LEN_3A42_P_2) },
4699 { "(bad)", { XX } },
4700 },
4701
4702 /* PREFIX_VEX_3A48 */
4703 {
4704 { "(bad)", { XX } },
4705 { "(bad)", { XX } },
4706 { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, VPERMIL2 } },
4707 { "(bad)", { XX } },
4708 },
4709
4710 /* PREFIX_VEX_3A49 */
4711 {
4712 { "(bad)", { XX } },
4713 { "(bad)", { XX } },
4714 { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, VPERMIL2 } },
4715 { "(bad)", { XX } },
4716 },
4717
4718 /* PREFIX_VEX_3A4A */
4719 {
4720 { "(bad)", { XX } },
4721 { "(bad)", { XX } },
4722 { "vblendvps", { XM, Vex, EXx, XMVexI4 } },
4723 { "(bad)", { XX } },
4724 },
4725
4726 /* PREFIX_VEX_3A4B */
4727 {
4728 { "(bad)", { XX } },
4729 { "(bad)", { XX } },
4730 { "vblendvpd", { XM, Vex, EXx, XMVexI4 } },
4731 { "(bad)", { XX } },
4732 },
4733
4734 /* PREFIX_VEX_3A4C */
4735 {
4736 { "(bad)", { XX } },
4737 { "(bad)", { XX } },
4738 { VEX_LEN_TABLE (VEX_LEN_3A4C_P_2) },
4739 { "(bad)", { XX } },
4740 },
4741
4742 /* PREFIX_VEX_3A5C */
4743 {
4744 { "(bad)", { XX } },
4745 { "(bad)", { XX } },
4746 { "vfmaddsubps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
4747 { "(bad)", { XX } },
4748 },
4749
4750 /* PREFIX_VEX_3A5D */
4751 {
4752 { "(bad)", { XX } },
4753 { "(bad)", { XX } },
4754 { "vfmaddsubpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
4755 { "(bad)", { XX } },
4756 },
4757
4758 /* PREFIX_VEX_3A5E */
4759 {
4760 { "(bad)", { XX } },
4761 { "(bad)", { XX } },
4762 { "vfmsubaddps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
4763 { "(bad)", { XX } },
4764 },
4765
4766 /* PREFIX_VEX_3A5F */
4767 {
4768 { "(bad)", { XX } },
4769 { "(bad)", { XX } },
4770 { "vfmsubaddpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
4771 { "(bad)", { XX } },
4772 },
4773
4774 /* PREFIX_VEX_3A60 */
4775 {
4776 { "(bad)", { XX } },
4777 { "(bad)", { XX } },
4778 { VEX_LEN_TABLE (VEX_LEN_3A60_P_2) },
4779 { "(bad)", { XX } },
4780 },
4781
4782 /* PREFIX_VEX_3A61 */
4783 {
4784 { "(bad)", { XX } },
4785 { "(bad)", { XX } },
4786 { VEX_LEN_TABLE (VEX_LEN_3A61_P_2) },
4787 { "(bad)", { XX } },
4788 },
4789
4790 /* PREFIX_VEX_3A62 */
4791 {
4792 { "(bad)", { XX } },
4793 { "(bad)", { XX } },
4794 { VEX_LEN_TABLE (VEX_LEN_3A62_P_2) },
4795 { "(bad)", { XX } },
4796 },
4797
4798 /* PREFIX_VEX_3A63 */
4799 {
4800 { "(bad)", { XX } },
4801 { "(bad)", { XX } },
4802 { VEX_LEN_TABLE (VEX_LEN_3A63_P_2) },
4803 { "(bad)", { XX } },
4804 },
4805
4806 /* PREFIX_VEX_3A68 */
4807 {
4808 { "(bad)", { XX } },
4809 { "(bad)", { XX } },
4810 { "vfmaddps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
4811 { "(bad)", { XX } },
4812 },
4813
4814 /* PREFIX_VEX_3A69 */
4815 {
4816 { "(bad)", { XX } },
4817 { "(bad)", { XX } },
4818 { "vfmaddpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
4819 { "(bad)", { XX } },
4820 },
4821
4822 /* PREFIX_VEX_3A6A */
4823 {
4824 { "(bad)", { XX } },
4825 { "(bad)", { XX } },
4826 { VEX_LEN_TABLE (VEX_LEN_3A6A_P_2) },
4827 { "(bad)", { XX } },
4828 },
4829
4830 /* PREFIX_VEX_3A6B */
4831 {
4832 { "(bad)", { XX } },
4833 { "(bad)", { XX } },
4834 { VEX_LEN_TABLE (VEX_LEN_3A6B_P_2) },
4835 { "(bad)", { XX } },
4836 },
4837
4838 /* PREFIX_VEX_3A6C */
4839 {
4840 { "(bad)", { XX } },
4841 { "(bad)", { XX } },
4842 { "vfmsubps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
4843 { "(bad)", { XX } },
4844 },
4845
4846 /* PREFIX_VEX_3A6D */
4847 {
4848 { "(bad)", { XX } },
4849 { "(bad)", { XX } },
4850 { "vfmsubpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
4851 { "(bad)", { XX } },
4852 },
4853
4854 /* PREFIX_VEX_3A6E */
4855 {
4856 { "(bad)", { XX } },
4857 { "(bad)", { XX } },
4858 { VEX_LEN_TABLE (VEX_LEN_3A6E_P_2) },
4859 { "(bad)", { XX } },
4860 },
4861
4862 /* PREFIX_VEX_3A6F */
4863 {
4864 { "(bad)", { XX } },
4865 { "(bad)", { XX } },
4866 { VEX_LEN_TABLE (VEX_LEN_3A6F_P_2) },
4867 { "(bad)", { XX } },
4868 },
4869
4870 /* PREFIX_VEX_3A78 */
4871 {
4872 { "(bad)", { XX } },
4873 { "(bad)", { XX } },
4874 { "vfnmaddps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
4875 { "(bad)", { XX } },
4876 },
4877
4878 /* PREFIX_VEX_3A79 */
4879 {
4880 { "(bad)", { XX } },
4881 { "(bad)", { XX } },
4882 { "vfnmaddpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
4883 { "(bad)", { XX } },
4884 },
4885
4886 /* PREFIX_VEX_3A7A */
4887 {
4888 { "(bad)", { XX } },
4889 { "(bad)", { XX } },
4890 { VEX_LEN_TABLE (VEX_LEN_3A7A_P_2) },
4891 { "(bad)", { XX } },
4892 },
4893
4894 /* PREFIX_VEX_3A7B */
4895 {
4896 { "(bad)", { XX } },
4897 { "(bad)", { XX } },
4898 { VEX_LEN_TABLE (VEX_LEN_3A7B_P_2) },
4899 { "(bad)", { XX } },
4900 },
4901
4902 /* PREFIX_VEX_3A7C */
4903 {
4904 { "(bad)", { XX } },
4905 { "(bad)", { XX } },
4906 { "vfnmsubps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
4907 { "(bad)", { XX } },
4908 },
4909
4910 /* PREFIX_VEX_3A7D */
4911 {
4912 { "(bad)", { XX } },
4913 { "(bad)", { XX } },
4914 { "vfnmsubpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
4915 { "(bad)", { XX } },
4916 },
4917
4918 /* PREFIX_VEX_3A7E */
4919 {
4920 { "(bad)", { XX } },
4921 { "(bad)", { XX } },
4922 { VEX_LEN_TABLE (VEX_LEN_3A7E_P_2) },
4923 { "(bad)", { XX } },
4924 },
4925
4926 /* PREFIX_VEX_3A7F */
4927 {
4928 { "(bad)", { XX } },
4929 { "(bad)", { XX } },
4930 { VEX_LEN_TABLE (VEX_LEN_3A7F_P_2) },
4931 { "(bad)", { XX } },
4932 },
4933 };
4934
4935 static const struct dis386 x86_64_table[][2] = {
4936 /* X86_64_06 */
4937 {
4938 { "push{T|}", { es } },
4939 { "(bad)", { XX } },
4940 },
4941
4942 /* X86_64_07 */
4943 {
4944 { "pop{T|}", { es } },
4945 { "(bad)", { XX } },
4946 },
4947
4948 /* X86_64_0D */
4949 {
4950 { "push{T|}", { cs } },
4951 { "(bad)", { XX } },
4952 },
4953
4954 /* X86_64_16 */
4955 {
4956 { "push{T|}", { ss } },
4957 { "(bad)", { XX } },
4958 },
4959
4960 /* X86_64_17 */
4961 {
4962 { "pop{T|}", { ss } },
4963 { "(bad)", { XX } },
4964 },
4965
4966 /* X86_64_1E */
4967 {
4968 { "push{T|}", { ds } },
4969 { "(bad)", { XX } },
4970 },
4971
4972 /* X86_64_1F */
4973 {
4974 { "pop{T|}", { ds } },
4975 { "(bad)", { XX } },
4976 },
4977
4978 /* X86_64_27 */
4979 {
4980 { "daa", { XX } },
4981 { "(bad)", { XX } },
4982 },
4983
4984 /* X86_64_2F */
4985 {
4986 { "das", { XX } },
4987 { "(bad)", { XX } },
4988 },
4989
4990 /* X86_64_37 */
4991 {
4992 { "aaa", { XX } },
4993 { "(bad)", { XX } },
4994 },
4995
4996 /* X86_64_3F */
4997 {
4998 { "aas", { XX } },
4999 { "(bad)", { XX } },
5000 },
5001
5002 /* X86_64_60 */
5003 {
5004 { "pusha{P|}", { XX } },
5005 { "(bad)", { XX } },
5006 },
5007
5008 /* X86_64_61 */
5009 {
5010 { "popa{P|}", { XX } },
5011 { "(bad)", { XX } },
5012 },
5013
5014 /* X86_64_62 */
5015 {
5016 { MOD_TABLE (MOD_62_32BIT) },
5017 { "(bad)", { XX } },
5018 },
5019
5020 /* X86_64_63 */
5021 {
5022 { "arpl", { Ew, Gw } },
5023 { "movs{lq|xd}", { Gv, Ed } },
5024 },
5025
5026 /* X86_64_6D */
5027 {
5028 { "ins{R|}", { Yzr, indirDX } },
5029 { "ins{G|}", { Yzr, indirDX } },
5030 },
5031
5032 /* X86_64_6F */
5033 {
5034 { "outs{R|}", { indirDXr, Xz } },
5035 { "outs{G|}", { indirDXr, Xz } },
5036 },
5037
5038 /* X86_64_9A */
5039 {
5040 { "Jcall{T|}", { Ap } },
5041 { "(bad)", { XX } },
5042 },
5043
5044 /* X86_64_C4 */
5045 {
5046 { MOD_TABLE (MOD_C4_32BIT) },
5047 { VEX_C4_TABLE (VEX_0F) },
5048 },
5049
5050 /* X86_64_C5 */
5051 {
5052 { MOD_TABLE (MOD_C5_32BIT) },
5053 { VEX_C5_TABLE (VEX_0F) },
5054 },
5055
5056 /* X86_64_CE */
5057 {
5058 { "into", { XX } },
5059 { "(bad)", { XX } },
5060 },
5061
5062 /* X86_64_D4 */
5063 {
5064 { "aam", { sIb } },
5065 { "(bad)", { XX } },
5066 },
5067
5068 /* X86_64_D5 */
5069 {
5070 { "aad", { sIb } },
5071 { "(bad)", { XX } },
5072 },
5073
5074 /* X86_64_EA */
5075 {
5076 { "Jjmp{T|}", { Ap } },
5077 { "(bad)", { XX } },
5078 },
5079
5080 /* X86_64_0F01_REG_0 */
5081 {
5082 { "sgdt{Q|IQ}", { M } },
5083 { "sgdt", { M } },
5084 },
5085
5086 /* X86_64_0F01_REG_1 */
5087 {
5088 { "sidt{Q|IQ}", { M } },
5089 { "sidt", { M } },
5090 },
5091
5092 /* X86_64_0F01_REG_2 */
5093 {
5094 { "lgdt{Q|Q}", { M } },
5095 { "lgdt", { M } },
5096 },
5097
5098 /* X86_64_0F01_REG_3 */
5099 {
5100 { "lidt{Q|Q}", { M } },
5101 { "lidt", { M } },
5102 },
5103 };
5104
5105 static const struct dis386 three_byte_table[][256] = {
5106 /* THREE_BYTE_0F24 */
5107 {
5108 /* 00 */
5109 { "fmaddps", { { OP_DREX4, q_mode } } },
5110 { "fmaddpd", { { OP_DREX4, q_mode } } },
5111 { "fmaddss", { { OP_DREX4, w_mode } } },
5112 { "fmaddsd", { { OP_DREX4, d_mode } } },
5113 { "fmaddps", { { OP_DREX4, DREX_OC1 + q_mode } } },
5114 { "fmaddpd", { { OP_DREX4, DREX_OC1 + q_mode } } },
5115 { "fmaddss", { { OP_DREX4, DREX_OC1 + w_mode } } },
5116 { "fmaddsd", { { OP_DREX4, DREX_OC1 + d_mode } } },
5117 /* 08 */
5118 { "fmsubps", { { OP_DREX4, q_mode } } },
5119 { "fmsubpd", { { OP_DREX4, q_mode } } },
5120 { "fmsubss", { { OP_DREX4, w_mode } } },
5121 { "fmsubsd", { { OP_DREX4, d_mode } } },
5122 { "fmsubps", { { OP_DREX4, DREX_OC1 + q_mode } } },
5123 { "fmsubpd", { { OP_DREX4, DREX_OC1 + q_mode } } },
5124 { "fmsubss", { { OP_DREX4, DREX_OC1 + w_mode } } },
5125 { "fmsubsd", { { OP_DREX4, DREX_OC1 + d_mode } } },
5126 /* 10 */
5127 { "fnmaddps", { { OP_DREX4, q_mode } } },
5128 { "fnmaddpd", { { OP_DREX4, q_mode } } },
5129 { "fnmaddss", { { OP_DREX4, w_mode } } },
5130 { "fnmaddsd", { { OP_DREX4, d_mode } } },
5131 { "fnmaddps", { { OP_DREX4, DREX_OC1 + q_mode } } },
5132 { "fnmaddpd", { { OP_DREX4, DREX_OC1 + q_mode } } },
5133 { "fnmaddss", { { OP_DREX4, DREX_OC1 + w_mode } } },
5134 { "fnmaddsd", { { OP_DREX4, DREX_OC1 + d_mode } } },
5135 /* 18 */
5136 { "fnmsubps", { { OP_DREX4, q_mode } } },
5137 { "fnmsubpd", { { OP_DREX4, q_mode } } },
5138 { "fnmsubss", { { OP_DREX4, w_mode } } },
5139 { "fnmsubsd", { { OP_DREX4, d_mode } } },
5140 { "fnmsubps", { { OP_DREX4, DREX_OC1 + q_mode } } },
5141 { "fnmsubpd", { { OP_DREX4, DREX_OC1 + q_mode } } },
5142 { "fnmsubss", { { OP_DREX4, DREX_OC1 + w_mode } } },
5143 { "fnmsubsd", { { OP_DREX4, DREX_OC1 + d_mode } } },
5144 /* 20 */
5145 { "permps", { { OP_DREX4, q_mode } } },
5146 { "permpd", { { OP_DREX4, q_mode } } },
5147 { "pcmov", { { OP_DREX4, q_mode } } },
5148 { "pperm", { { OP_DREX4, q_mode } } },
5149 { "permps", { { OP_DREX4, DREX_OC1 + q_mode } } },
5150 { "permpd", { { OP_DREX4, DREX_OC1 + q_mode } } },
5151 { "pcmov", { { OP_DREX4, DREX_OC1 + w_mode } } },
5152 { "pperm", { { OP_DREX4, DREX_OC1 + d_mode } } },
5153 /* 28 */
5154 { "(bad)", { XX } },
5155 { "(bad)", { XX } },
5156 { "(bad)", { XX } },
5157 { "(bad)", { XX } },
5158 { "(bad)", { XX } },
5159 { "(bad)", { XX } },
5160 { "(bad)", { XX } },
5161 { "(bad)", { XX } },
5162 /* 30 */
5163 { "(bad)", { XX } },
5164 { "(bad)", { XX } },
5165 { "(bad)", { XX } },
5166 { "(bad)", { XX } },
5167 { "(bad)", { XX } },
5168 { "(bad)", { XX } },
5169 { "(bad)", { XX } },
5170 { "(bad)", { XX } },
5171 /* 38 */
5172 { "(bad)", { XX } },
5173 { "(bad)", { XX } },
5174 { "(bad)", { XX } },
5175 { "(bad)", { XX } },
5176 { "(bad)", { XX } },
5177 { "(bad)", { XX } },
5178 { "(bad)", { XX } },
5179 { "(bad)", { XX } },
5180 /* 40 */
5181 { "protb", { { OP_DREX3, q_mode } } },
5182 { "protw", { { OP_DREX3, q_mode } } },
5183 { "protd", { { OP_DREX3, q_mode } } },
5184 { "protq", { { OP_DREX3, q_mode } } },
5185 { "pshlb", { { OP_DREX3, q_mode } } },
5186 { "pshlw", { { OP_DREX3, q_mode } } },
5187 { "pshld", { { OP_DREX3, q_mode } } },
5188 { "pshlq", { { OP_DREX3, q_mode } } },
5189 /* 48 */
5190 { "pshab", { { OP_DREX3, q_mode } } },
5191 { "pshaw", { { OP_DREX3, q_mode } } },
5192 { "pshad", { { OP_DREX3, q_mode } } },
5193 { "pshaq", { { OP_DREX3, q_mode } } },
5194 { "(bad)", { XX } },
5195 { "(bad)", { XX } },
5196 { "(bad)", { XX } },
5197 { "(bad)", { XX } },
5198 /* 50 */
5199 { "(bad)", { XX } },
5200 { "(bad)", { XX } },
5201 { "(bad)", { XX } },
5202 { "(bad)", { XX } },
5203 { "(bad)", { XX } },
5204 { "(bad)", { XX } },
5205 { "(bad)", { XX } },
5206 { "(bad)", { XX } },
5207 /* 58 */
5208 { "(bad)", { XX } },
5209 { "(bad)", { XX } },
5210 { "(bad)", { XX } },
5211 { "(bad)", { XX } },
5212 { "(bad)", { XX } },
5213 { "(bad)", { XX } },
5214 { "(bad)", { XX } },
5215 { "(bad)", { XX } },
5216 /* 60 */
5217 { "(bad)", { XX } },
5218 { "(bad)", { XX } },
5219 { "(bad)", { XX } },
5220 { "(bad)", { XX } },
5221 { "(bad)", { XX } },
5222 { "(bad)", { XX } },
5223 { "(bad)", { XX } },
5224 { "(bad)", { XX } },
5225 /* 68 */
5226 { "(bad)", { XX } },
5227 { "(bad)", { XX } },
5228 { "(bad)", { XX } },
5229 { "(bad)", { XX } },
5230 { "(bad)", { XX } },
5231 { "(bad)", { XX } },
5232 { "(bad)", { XX } },
5233 { "(bad)", { XX } },
5234 /* 70 */
5235 { "(bad)", { XX } },
5236 { "(bad)", { XX } },
5237 { "(bad)", { XX } },
5238 { "(bad)", { XX } },
5239 { "(bad)", { XX } },
5240 { "(bad)", { XX } },
5241 { "(bad)", { XX } },
5242 { "(bad)", { XX } },
5243 /* 78 */
5244 { "(bad)", { XX } },
5245 { "(bad)", { XX } },
5246 { "(bad)", { XX } },
5247 { "(bad)", { XX } },
5248 { "(bad)", { XX } },
5249 { "(bad)", { XX } },
5250 { "(bad)", { XX } },
5251 { "(bad)", { XX } },
5252 /* 80 */
5253 { "(bad)", { XX } },
5254 { "(bad)", { XX } },
5255 { "(bad)", { XX } },
5256 { "(bad)", { XX } },
5257 { "(bad)", { XX } },
5258 { "pmacssww", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5259 { "pmacsswd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5260 { "pmacssdql", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5261 /* 88 */
5262 { "(bad)", { XX } },
5263 { "(bad)", { XX } },
5264 { "(bad)", { XX } },
5265 { "(bad)", { XX } },
5266 { "(bad)", { XX } },
5267 { "(bad)", { XX } },
5268 { "pmacssdd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5269 { "pmacssdqh", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5270 /* 90 */
5271 { "(bad)", { XX } },
5272 { "(bad)", { XX } },
5273 { "(bad)", { XX } },
5274 { "(bad)", { XX } },
5275 { "(bad)", { XX } },
5276 { "pmacsww", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5277 { "pmacswd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5278 { "pmacsdql", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5279 /* 98 */
5280 { "(bad)", { XX } },
5281 { "(bad)", { XX } },
5282 { "(bad)", { XX } },
5283 { "(bad)", { XX } },
5284 { "(bad)", { XX } },
5285 { "(bad)", { XX } },
5286 { "pmacsdd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5287 { "pmacsdqh", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5288 /* a0 */
5289 { "(bad)", { XX } },
5290 { "(bad)", { XX } },
5291 { "(bad)", { XX } },
5292 { "(bad)", { XX } },
5293 { "(bad)", { XX } },
5294 { "(bad)", { XX } },
5295 { "pmadcsswd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5296 { "(bad)", { XX } },
5297 /* a8 */
5298 { "(bad)", { XX } },
5299 { "(bad)", { XX } },
5300 { "(bad)", { XX } },
5301 { "(bad)", { XX } },
5302 { "(bad)", { XX } },
5303 { "(bad)", { XX } },
5304 { "(bad)", { XX } },
5305 { "(bad)", { XX } },
5306 /* b0 */
5307 { "(bad)", { XX } },
5308 { "(bad)", { XX } },
5309 { "(bad)", { XX } },
5310 { "(bad)", { XX } },
5311 { "(bad)", { XX } },
5312 { "(bad)", { XX } },
5313 { "pmadcswd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5314 { "(bad)", { XX } },
5315 /* b8 */
5316 { "(bad)", { XX } },
5317 { "(bad)", { XX } },
5318 { "(bad)", { XX } },
5319 { "(bad)", { XX } },
5320 { "(bad)", { XX } },
5321 { "(bad)", { XX } },
5322 { "(bad)", { XX } },
5323 { "(bad)", { XX } },
5324 /* c0 */
5325 { "(bad)", { XX } },
5326 { "(bad)", { XX } },
5327 { "(bad)", { XX } },
5328 { "(bad)", { XX } },
5329 { "(bad)", { XX } },
5330 { "(bad)", { XX } },
5331 { "(bad)", { XX } },
5332 { "(bad)", { XX } },
5333 /* c8 */
5334 { "(bad)", { XX } },
5335 { "(bad)", { XX } },
5336 { "(bad)", { XX } },
5337 { "(bad)", { XX } },
5338 { "(bad)", { XX } },
5339 { "(bad)", { XX } },
5340 { "(bad)", { XX } },
5341 { "(bad)", { XX } },
5342 /* d0 */
5343 { "(bad)", { XX } },
5344 { "(bad)", { XX } },
5345 { "(bad)", { XX } },
5346 { "(bad)", { XX } },
5347 { "(bad)", { XX } },
5348 { "(bad)", { XX } },
5349 { "(bad)", { XX } },
5350 { "(bad)", { XX } },
5351 /* d8 */
5352 { "(bad)", { XX } },
5353 { "(bad)", { XX } },
5354 { "(bad)", { XX } },
5355 { "(bad)", { XX } },
5356 { "(bad)", { XX } },
5357 { "(bad)", { XX } },
5358 { "(bad)", { XX } },
5359 { "(bad)", { XX } },
5360 /* e0 */
5361 { "(bad)", { XX } },
5362 { "(bad)", { XX } },
5363 { "(bad)", { XX } },
5364 { "(bad)", { XX } },
5365 { "(bad)", { XX } },
5366 { "(bad)", { XX } },
5367 { "(bad)", { XX } },
5368 { "(bad)", { XX } },
5369 /* e8 */
5370 { "(bad)", { XX } },
5371 { "(bad)", { XX } },
5372 { "(bad)", { XX } },
5373 { "(bad)", { XX } },
5374 { "(bad)", { XX } },
5375 { "(bad)", { XX } },
5376 { "(bad)", { XX } },
5377 { "(bad)", { XX } },
5378 /* f0 */
5379 { "(bad)", { XX } },
5380 { "(bad)", { XX } },
5381 { "(bad)", { XX } },
5382 { "(bad)", { XX } },
5383 { "(bad)", { XX } },
5384 { "(bad)", { XX } },
5385 { "(bad)", { XX } },
5386 { "(bad)", { XX } },
5387 /* f8 */
5388 { "(bad)", { XX } },
5389 { "(bad)", { XX } },
5390 { "(bad)", { XX } },
5391 { "(bad)", { XX } },
5392 { "(bad)", { XX } },
5393 { "(bad)", { XX } },
5394 { "(bad)", { XX } },
5395 { "(bad)", { XX } },
5396 },
5397 /* THREE_BYTE_0F25 */
5398 {
5399 /* 00 */
5400 { "(bad)", { XX } },
5401 { "(bad)", { XX } },
5402 { "(bad)", { XX } },
5403 { "(bad)", { XX } },
5404 { "(bad)", { XX } },
5405 { "(bad)", { XX } },
5406 { "(bad)", { XX } },
5407 { "(bad)", { XX } },
5408 /* 08 */
5409 { "(bad)", { XX } },
5410 { "(bad)", { XX } },
5411 { "(bad)", { XX } },
5412 { "(bad)", { XX } },
5413 { "(bad)", { XX } },
5414 { "(bad)", { XX } },
5415 { "(bad)", { XX } },
5416 { "(bad)", { XX } },
5417 /* 10 */
5418 { "(bad)", { XX } },
5419 { "(bad)", { XX } },
5420 { "(bad)", { XX } },
5421 { "(bad)", { XX } },
5422 { "(bad)", { XX } },
5423 { "(bad)", { XX } },
5424 { "(bad)", { XX } },
5425 { "(bad)", { XX } },
5426 /* 18 */
5427 { "(bad)", { XX } },
5428 { "(bad)", { XX } },
5429 { "(bad)", { XX } },
5430 { "(bad)", { XX } },
5431 { "(bad)", { XX } },
5432 { "(bad)", { XX } },
5433 { "(bad)", { XX } },
5434 { "(bad)", { XX } },
5435 /* 20 */
5436 { "(bad)", { XX } },
5437 { "(bad)", { XX } },
5438 { "(bad)", { XX } },
5439 { "(bad)", { XX } },
5440 { "(bad)", { XX } },
5441 { "(bad)", { XX } },
5442 { "(bad)", { XX } },
5443 { "(bad)", { XX } },
5444 /* 28 */
5445 { "(bad)", { XX } },
5446 { "(bad)", { XX } },
5447 { "(bad)", { XX } },
5448 { "(bad)", { XX } },
5449 { "comps", { { OP_DREX3, q_mode }, { OP_DREX_FCMP, b_mode } } },
5450 { "compd", { { OP_DREX3, q_mode }, { OP_DREX_FCMP, b_mode } } },
5451 { "comss", { { OP_DREX3, w_mode }, { OP_DREX_FCMP, b_mode } } },
5452 { "comsd", { { OP_DREX3, d_mode }, { OP_DREX_FCMP, b_mode } } },
5453 /* 30 */
5454 { "(bad)", { XX } },
5455 { "(bad)", { XX } },
5456 { "(bad)", { XX } },
5457 { "(bad)", { XX } },
5458 { "(bad)", { XX } },
5459 { "(bad)", { XX } },
5460 { "(bad)", { XX } },
5461 { "(bad)", { XX } },
5462 /* 38 */
5463 { "(bad)", { XX } },
5464 { "(bad)", { XX } },
5465 { "(bad)", { XX } },
5466 { "(bad)", { XX } },
5467 { "(bad)", { XX } },
5468 { "(bad)", { XX } },
5469 { "(bad)", { XX } },
5470 { "(bad)", { XX } },
5471 /* 40 */
5472 { "(bad)", { XX } },
5473 { "(bad)", { XX } },
5474 { "(bad)", { XX } },
5475 { "(bad)", { XX } },
5476 { "(bad)", { XX } },
5477 { "(bad)", { XX } },
5478 { "(bad)", { XX } },
5479 { "(bad)", { XX } },
5480 /* 48 */
5481 { "(bad)", { XX } },
5482 { "(bad)", { XX } },
5483 { "(bad)", { XX } },
5484 { "(bad)", { XX } },
5485 { "pcomb", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5486 { "pcomw", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5487 { "pcomd", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5488 { "pcomq", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5489 /* 50 */
5490 { "(bad)", { XX } },
5491 { "(bad)", { XX } },
5492 { "(bad)", { XX } },
5493 { "(bad)", { XX } },
5494 { "(bad)", { XX } },
5495 { "(bad)", { XX } },
5496 { "(bad)", { XX } },
5497 { "(bad)", { XX } },
5498 /* 58 */
5499 { "(bad)", { XX } },
5500 { "(bad)", { XX } },
5501 { "(bad)", { XX } },
5502 { "(bad)", { XX } },
5503 { "(bad)", { XX } },
5504 { "(bad)", { XX } },
5505 { "(bad)", { XX } },
5506 { "(bad)", { XX } },
5507 /* 60 */
5508 { "(bad)", { XX } },
5509 { "(bad)", { XX } },
5510 { "(bad)", { XX } },
5511 { "(bad)", { XX } },
5512 { "(bad)", { XX } },
5513 { "(bad)", { XX } },
5514 { "(bad)", { XX } },
5515 { "(bad)", { XX } },
5516 /* 68 */
5517 { "(bad)", { XX } },
5518 { "(bad)", { XX } },
5519 { "(bad)", { XX } },
5520 { "(bad)", { XX } },
5521 { "pcomub", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5522 { "pcomuw", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5523 { "pcomud", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5524 { "pcomuq", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5525 /* 70 */
5526 { "(bad)", { XX } },
5527 { "(bad)", { XX } },
5528 { "(bad)", { XX } },
5529 { "(bad)", { XX } },
5530 { "(bad)", { XX } },
5531 { "(bad)", { XX } },
5532 { "(bad)", { XX } },
5533 { "(bad)", { XX } },
5534 /* 78 */
5535 { "(bad)", { XX } },
5536 { "(bad)", { XX } },
5537 { "(bad)", { XX } },
5538 { "(bad)", { XX } },
5539 { "(bad)", { XX } },
5540 { "(bad)", { XX } },
5541 { "(bad)", { XX } },
5542 { "(bad)", { XX } },
5543 /* 80 */
5544 { "(bad)", { XX } },
5545 { "(bad)", { XX } },
5546 { "(bad)", { XX } },
5547 { "(bad)", { XX } },
5548 { "(bad)", { XX } },
5549 { "(bad)", { XX } },
5550 { "(bad)", { XX } },
5551 { "(bad)", { XX } },
5552 /* 88 */
5553 { "(bad)", { XX } },
5554 { "(bad)", { XX } },
5555 { "(bad)", { XX } },
5556 { "(bad)", { XX } },
5557 { "(bad)", { XX } },
5558 { "(bad)", { XX } },
5559 { "(bad)", { XX } },
5560 { "(bad)", { XX } },
5561 /* 90 */
5562 { "(bad)", { XX } },
5563 { "(bad)", { XX } },
5564 { "(bad)", { XX } },
5565 { "(bad)", { XX } },
5566 { "(bad)", { XX } },
5567 { "(bad)", { XX } },
5568 { "(bad)", { XX } },
5569 { "(bad)", { XX } },
5570 /* 98 */
5571 { "(bad)", { XX } },
5572 { "(bad)", { XX } },
5573 { "(bad)", { XX } },
5574 { "(bad)", { XX } },
5575 { "(bad)", { XX } },
5576 { "(bad)", { XX } },
5577 { "(bad)", { XX } },
5578 { "(bad)", { XX } },
5579 /* a0 */
5580 { "(bad)", { XX } },
5581 { "(bad)", { XX } },
5582 { "(bad)", { XX } },
5583 { "(bad)", { XX } },
5584 { "(bad)", { XX } },
5585 { "(bad)", { XX } },
5586 { "(bad)", { XX } },
5587 { "(bad)", { XX } },
5588 /* a8 */
5589 { "(bad)", { XX } },
5590 { "(bad)", { XX } },
5591 { "(bad)", { XX } },
5592 { "(bad)", { XX } },
5593 { "(bad)", { XX } },
5594 { "(bad)", { XX } },
5595 { "(bad)", { XX } },
5596 { "(bad)", { XX } },
5597 /* b0 */
5598 { "(bad)", { XX } },
5599 { "(bad)", { XX } },
5600 { "(bad)", { XX } },
5601 { "(bad)", { XX } },
5602 { "(bad)", { XX } },
5603 { "(bad)", { XX } },
5604 { "(bad)", { XX } },
5605 { "(bad)", { XX } },
5606 /* b8 */
5607 { "(bad)", { XX } },
5608 { "(bad)", { XX } },
5609 { "(bad)", { XX } },
5610 { "(bad)", { XX } },
5611 { "(bad)", { XX } },
5612 { "(bad)", { XX } },
5613 { "(bad)", { XX } },
5614 { "(bad)", { XX } },
5615 /* c0 */
5616 { "(bad)", { XX } },
5617 { "(bad)", { XX } },
5618 { "(bad)", { XX } },
5619 { "(bad)", { XX } },
5620 { "(bad)", { XX } },
5621 { "(bad)", { XX } },
5622 { "(bad)", { XX } },
5623 { "(bad)", { XX } },
5624 /* c8 */
5625 { "(bad)", { XX } },
5626 { "(bad)", { XX } },
5627 { "(bad)", { XX } },
5628 { "(bad)", { XX } },
5629 { "(bad)", { XX } },
5630 { "(bad)", { XX } },
5631 { "(bad)", { XX } },
5632 { "(bad)", { XX } },
5633 /* d0 */
5634 { "(bad)", { XX } },
5635 { "(bad)", { XX } },
5636 { "(bad)", { XX } },
5637 { "(bad)", { XX } },
5638 { "(bad)", { XX } },
5639 { "(bad)", { XX } },
5640 { "(bad)", { XX } },
5641 { "(bad)", { XX } },
5642 /* d8 */
5643 { "(bad)", { XX } },
5644 { "(bad)", { XX } },
5645 { "(bad)", { XX } },
5646 { "(bad)", { XX } },
5647 { "(bad)", { XX } },
5648 { "(bad)", { XX } },
5649 { "(bad)", { XX } },
5650 { "(bad)", { XX } },
5651 /* e0 */
5652 { "(bad)", { XX } },
5653 { "(bad)", { XX } },
5654 { "(bad)", { XX } },
5655 { "(bad)", { XX } },
5656 { "(bad)", { XX } },
5657 { "(bad)", { XX } },
5658 { "(bad)", { XX } },
5659 { "(bad)", { XX } },
5660 /* e8 */
5661 { "(bad)", { XX } },
5662 { "(bad)", { XX } },
5663 { "(bad)", { XX } },
5664 { "(bad)", { XX } },
5665 { "(bad)", { XX } },
5666 { "(bad)", { XX } },
5667 { "(bad)", { XX } },
5668 { "(bad)", { XX } },
5669 /* f0 */
5670 { "(bad)", { XX } },
5671 { "(bad)", { XX } },
5672 { "(bad)", { XX } },
5673 { "(bad)", { XX } },
5674 { "(bad)", { XX } },
5675 { "(bad)", { XX } },
5676 { "(bad)", { XX } },
5677 { "(bad)", { XX } },
5678 /* f8 */
5679 { "(bad)", { XX } },
5680 { "(bad)", { XX } },
5681 { "(bad)", { XX } },
5682 { "(bad)", { XX } },
5683 { "(bad)", { XX } },
5684 { "(bad)", { XX } },
5685 { "(bad)", { XX } },
5686 { "(bad)", { XX } },
5687 },
5688 /* THREE_BYTE_0F38 */
5689 {
5690 /* 00 */
5691 { "pshufb", { MX, EM } },
5692 { "phaddw", { MX, EM } },
5693 { "phaddd", { MX, EM } },
5694 { "phaddsw", { MX, EM } },
5695 { "pmaddubsw", { MX, EM } },
5696 { "phsubw", { MX, EM } },
5697 { "phsubd", { MX, EM } },
5698 { "phsubsw", { MX, EM } },
5699 /* 08 */
5700 { "psignb", { MX, EM } },
5701 { "psignw", { MX, EM } },
5702 { "psignd", { MX, EM } },
5703 { "pmulhrsw", { MX, EM } },
5704 { "(bad)", { XX } },
5705 { "(bad)", { XX } },
5706 { "(bad)", { XX } },
5707 { "(bad)", { XX } },
5708 /* 10 */
5709 { PREFIX_TABLE (PREFIX_0F3810) },
5710 { "(bad)", { XX } },
5711 { "(bad)", { XX } },
5712 { "(bad)", { XX } },
5713 { PREFIX_TABLE (PREFIX_0F3814) },
5714 { PREFIX_TABLE (PREFIX_0F3815) },
5715 { "(bad)", { XX } },
5716 { PREFIX_TABLE (PREFIX_0F3817) },
5717 /* 18 */
5718 { "(bad)", { XX } },
5719 { "(bad)", { XX } },
5720 { "(bad)", { XX } },
5721 { "(bad)", { XX } },
5722 { "pabsb", { MX, EM } },
5723 { "pabsw", { MX, EM } },
5724 { "pabsd", { MX, EM } },
5725 { "(bad)", { XX } },
5726 /* 20 */
5727 { PREFIX_TABLE (PREFIX_0F3820) },
5728 { PREFIX_TABLE (PREFIX_0F3821) },
5729 { PREFIX_TABLE (PREFIX_0F3822) },
5730 { PREFIX_TABLE (PREFIX_0F3823) },
5731 { PREFIX_TABLE (PREFIX_0F3824) },
5732 { PREFIX_TABLE (PREFIX_0F3825) },
5733 { "(bad)", { XX } },
5734 { "(bad)", { XX } },
5735 /* 28 */
5736 { PREFIX_TABLE (PREFIX_0F3828) },
5737 { PREFIX_TABLE (PREFIX_0F3829) },
5738 { PREFIX_TABLE (PREFIX_0F382A) },
5739 { PREFIX_TABLE (PREFIX_0F382B) },
5740 { "(bad)", { XX } },
5741 { "(bad)", { XX } },
5742 { "(bad)", { XX } },
5743 { "(bad)", { XX } },
5744 /* 30 */
5745 { PREFIX_TABLE (PREFIX_0F3830) },
5746 { PREFIX_TABLE (PREFIX_0F3831) },
5747 { PREFIX_TABLE (PREFIX_0F3832) },
5748 { PREFIX_TABLE (PREFIX_0F3833) },
5749 { PREFIX_TABLE (PREFIX_0F3834) },
5750 { PREFIX_TABLE (PREFIX_0F3835) },
5751 { "(bad)", { XX } },
5752 { PREFIX_TABLE (PREFIX_0F3837) },
5753 /* 38 */
5754 { PREFIX_TABLE (PREFIX_0F3838) },
5755 { PREFIX_TABLE (PREFIX_0F3839) },
5756 { PREFIX_TABLE (PREFIX_0F383A) },
5757 { PREFIX_TABLE (PREFIX_0F383B) },
5758 { PREFIX_TABLE (PREFIX_0F383C) },
5759 { PREFIX_TABLE (PREFIX_0F383D) },
5760 { PREFIX_TABLE (PREFIX_0F383E) },
5761 { PREFIX_TABLE (PREFIX_0F383F) },
5762 /* 40 */
5763 { PREFIX_TABLE (PREFIX_0F3840) },
5764 { PREFIX_TABLE (PREFIX_0F3841) },
5765 { "(bad)", { XX } },
5766 { "(bad)", { XX } },
5767 { "(bad)", { XX } },
5768 { "(bad)", { XX } },
5769 { "(bad)", { XX } },
5770 { "(bad)", { XX } },
5771 /* 48 */
5772 { "(bad)", { XX } },
5773 { "(bad)", { XX } },
5774 { "(bad)", { XX } },
5775 { "(bad)", { XX } },
5776 { "(bad)", { XX } },
5777 { "(bad)", { XX } },
5778 { "(bad)", { XX } },
5779 { "(bad)", { XX } },
5780 /* 50 */
5781 { "(bad)", { XX } },
5782 { "(bad)", { XX } },
5783 { "(bad)", { XX } },
5784 { "(bad)", { XX } },
5785 { "(bad)", { XX } },
5786 { "(bad)", { XX } },
5787 { "(bad)", { XX } },
5788 { "(bad)", { XX } },
5789 /* 58 */
5790 { "(bad)", { XX } },
5791 { "(bad)", { XX } },
5792 { "(bad)", { XX } },
5793 { "(bad)", { XX } },
5794 { "(bad)", { XX } },
5795 { "(bad)", { XX } },
5796 { "(bad)", { XX } },
5797 { "(bad)", { XX } },
5798 /* 60 */
5799 { "(bad)", { XX } },
5800 { "(bad)", { XX } },
5801 { "(bad)", { XX } },
5802 { "(bad)", { XX } },
5803 { "(bad)", { XX } },
5804 { "(bad)", { XX } },
5805 { "(bad)", { XX } },
5806 { "(bad)", { XX } },
5807 /* 68 */
5808 { "(bad)", { XX } },
5809 { "(bad)", { XX } },
5810 { "(bad)", { XX } },
5811 { "(bad)", { XX } },
5812 { "(bad)", { XX } },
5813 { "(bad)", { XX } },
5814 { "(bad)", { XX } },
5815 { "(bad)", { XX } },
5816 /* 70 */
5817 { "(bad)", { XX } },
5818 { "(bad)", { XX } },
5819 { "(bad)", { XX } },
5820 { "(bad)", { XX } },
5821 { "(bad)", { XX } },
5822 { "(bad)", { XX } },
5823 { "(bad)", { XX } },
5824 { "(bad)", { XX } },
5825 /* 78 */
5826 { "(bad)", { XX } },
5827 { "(bad)", { XX } },
5828 { "(bad)", { XX } },
5829 { "(bad)", { XX } },
5830 { "(bad)", { XX } },
5831 { "(bad)", { XX } },
5832 { "(bad)", { XX } },
5833 { "(bad)", { XX } },
5834 /* 80 */
5835 { "(bad)", { XX } },
5836 { "(bad)", { XX } },
5837 { "(bad)", { XX } },
5838 { "(bad)", { XX } },
5839 { "(bad)", { XX } },
5840 { "(bad)", { XX } },
5841 { "(bad)", { XX } },
5842 { "(bad)", { XX } },
5843 /* 88 */
5844 { "(bad)", { XX } },
5845 { "(bad)", { XX } },
5846 { "(bad)", { XX } },
5847 { "(bad)", { XX } },
5848 { "(bad)", { XX } },
5849 { "(bad)", { XX } },
5850 { "(bad)", { XX } },
5851 { "(bad)", { XX } },
5852 /* 90 */
5853 { "(bad)", { XX } },
5854 { "(bad)", { XX } },
5855 { "(bad)", { XX } },
5856 { "(bad)", { XX } },
5857 { "(bad)", { XX } },
5858 { "(bad)", { XX } },
5859 { "(bad)", { XX } },
5860 { "(bad)", { XX } },
5861 /* 98 */
5862 { "(bad)", { XX } },
5863 { "(bad)", { XX } },
5864 { "(bad)", { XX } },
5865 { "(bad)", { XX } },
5866 { "(bad)", { XX } },
5867 { "(bad)", { XX } },
5868 { "(bad)", { XX } },
5869 { "(bad)", { XX } },
5870 /* a0 */
5871 { "(bad)", { XX } },
5872 { "(bad)", { XX } },
5873 { "(bad)", { XX } },
5874 { "(bad)", { XX } },
5875 { "(bad)", { XX } },
5876 { "(bad)", { XX } },
5877 { "(bad)", { XX } },
5878 { "(bad)", { XX } },
5879 /* a8 */
5880 { "(bad)", { XX } },
5881 { "(bad)", { XX } },
5882 { "(bad)", { XX } },
5883 { "(bad)", { XX } },
5884 { "(bad)", { XX } },
5885 { "(bad)", { XX } },
5886 { "(bad)", { XX } },
5887 { "(bad)", { XX } },
5888 /* b0 */
5889 { "(bad)", { XX } },
5890 { "(bad)", { XX } },
5891 { "(bad)", { XX } },
5892 { "(bad)", { XX } },
5893 { "(bad)", { XX } },
5894 { "(bad)", { XX } },
5895 { "(bad)", { XX } },
5896 { "(bad)", { XX } },
5897 /* b8 */
5898 { "(bad)", { XX } },
5899 { "(bad)", { XX } },
5900 { "(bad)", { XX } },
5901 { "(bad)", { XX } },
5902 { "(bad)", { XX } },
5903 { "(bad)", { XX } },
5904 { "(bad)", { XX } },
5905 { "(bad)", { XX } },
5906 /* c0 */
5907 { "(bad)", { XX } },
5908 { "(bad)", { XX } },
5909 { "(bad)", { XX } },
5910 { "(bad)", { XX } },
5911 { "(bad)", { XX } },
5912 { "(bad)", { XX } },
5913 { "(bad)", { XX } },
5914 { "(bad)", { XX } },
5915 /* c8 */
5916 { "(bad)", { XX } },
5917 { "(bad)", { XX } },
5918 { "(bad)", { XX } },
5919 { "(bad)", { XX } },
5920 { "(bad)", { XX } },
5921 { "(bad)", { XX } },
5922 { "(bad)", { XX } },
5923 { "(bad)", { XX } },
5924 /* d0 */
5925 { "(bad)", { XX } },
5926 { "(bad)", { XX } },
5927 { "(bad)", { XX } },
5928 { "(bad)", { XX } },
5929 { "(bad)", { XX } },
5930 { "(bad)", { XX } },
5931 { "(bad)", { XX } },
5932 { "(bad)", { XX } },
5933 /* d8 */
5934 { "(bad)", { XX } },
5935 { "(bad)", { XX } },
5936 { "(bad)", { XX } },
5937 { PREFIX_TABLE (PREFIX_0F38DB) },
5938 { PREFIX_TABLE (PREFIX_0F38DC) },
5939 { PREFIX_TABLE (PREFIX_0F38DD) },
5940 { PREFIX_TABLE (PREFIX_0F38DE) },
5941 { PREFIX_TABLE (PREFIX_0F38DF) },
5942 /* e0 */
5943 { "(bad)", { XX } },
5944 { "(bad)", { XX } },
5945 { "(bad)", { XX } },
5946 { "(bad)", { XX } },
5947 { "(bad)", { XX } },
5948 { "(bad)", { XX } },
5949 { "(bad)", { XX } },
5950 { "(bad)", { XX } },
5951 /* e8 */
5952 { "(bad)", { XX } },
5953 { "(bad)", { XX } },
5954 { "(bad)", { XX } },
5955 { "(bad)", { XX } },
5956 { "(bad)", { XX } },
5957 { "(bad)", { XX } },
5958 { "(bad)", { XX } },
5959 { "(bad)", { XX } },
5960 /* f0 */
5961 { PREFIX_TABLE (PREFIX_0F38F0) },
5962 { PREFIX_TABLE (PREFIX_0F38F1) },
5963 { "(bad)", { XX } },
5964 { "(bad)", { XX } },
5965 { "(bad)", { XX } },
5966 { "(bad)", { XX } },
5967 { "(bad)", { XX } },
5968 { "(bad)", { XX } },
5969 /* f8 */
5970 { "(bad)", { XX } },
5971 { "(bad)", { XX } },
5972 { "(bad)", { XX } },
5973 { "(bad)", { XX } },
5974 { "(bad)", { XX } },
5975 { "(bad)", { XX } },
5976 { "(bad)", { XX } },
5977 { "(bad)", { XX } },
5978 },
5979 /* THREE_BYTE_0F3A */
5980 {
5981 /* 00 */
5982 { "(bad)", { XX } },
5983 { "(bad)", { XX } },
5984 { "(bad)", { XX } },
5985 { "(bad)", { XX } },
5986 { "(bad)", { XX } },
5987 { "(bad)", { XX } },
5988 { "(bad)", { XX } },
5989 { "(bad)", { XX } },
5990 /* 08 */
5991 { PREFIX_TABLE (PREFIX_0F3A08) },
5992 { PREFIX_TABLE (PREFIX_0F3A09) },
5993 { PREFIX_TABLE (PREFIX_0F3A0A) },
5994 { PREFIX_TABLE (PREFIX_0F3A0B) },
5995 { PREFIX_TABLE (PREFIX_0F3A0C) },
5996 { PREFIX_TABLE (PREFIX_0F3A0D) },
5997 { PREFIX_TABLE (PREFIX_0F3A0E) },
5998 { "palignr", { MX, EM, Ib } },
5999 /* 10 */
6000 { "(bad)", { XX } },
6001 { "(bad)", { XX } },
6002 { "(bad)", { XX } },
6003 { "(bad)", { XX } },
6004 { PREFIX_TABLE (PREFIX_0F3A14) },
6005 { PREFIX_TABLE (PREFIX_0F3A15) },
6006 { PREFIX_TABLE (PREFIX_0F3A16) },
6007 { PREFIX_TABLE (PREFIX_0F3A17) },
6008 /* 18 */
6009 { "(bad)", { XX } },
6010 { "(bad)", { XX } },
6011 { "(bad)", { XX } },
6012 { "(bad)", { XX } },
6013 { "(bad)", { XX } },
6014 { "(bad)", { XX } },
6015 { "(bad)", { XX } },
6016 { "(bad)", { XX } },
6017 /* 20 */
6018 { PREFIX_TABLE (PREFIX_0F3A20) },
6019 { PREFIX_TABLE (PREFIX_0F3A21) },
6020 { PREFIX_TABLE (PREFIX_0F3A22) },
6021 { "(bad)", { XX } },
6022 { "(bad)", { XX } },
6023 { "(bad)", { XX } },
6024 { "(bad)", { XX } },
6025 { "(bad)", { XX } },
6026 /* 28 */
6027 { "(bad)", { XX } },
6028 { "(bad)", { XX } },
6029 { "(bad)", { XX } },
6030 { "(bad)", { XX } },
6031 { "(bad)", { XX } },
6032 { "(bad)", { XX } },
6033 { "(bad)", { XX } },
6034 { "(bad)", { XX } },
6035 /* 30 */
6036 { "(bad)", { XX } },
6037 { "(bad)", { XX } },
6038 { "(bad)", { XX } },
6039 { "(bad)", { XX } },
6040 { "(bad)", { XX } },
6041 { "(bad)", { XX } },
6042 { "(bad)", { XX } },
6043 { "(bad)", { XX } },
6044 /* 38 */
6045 { "(bad)", { XX } },
6046 { "(bad)", { XX } },
6047 { "(bad)", { XX } },
6048 { "(bad)", { XX } },
6049 { "(bad)", { XX } },
6050 { "(bad)", { XX } },
6051 { "(bad)", { XX } },
6052 { "(bad)", { XX } },
6053 /* 40 */
6054 { PREFIX_TABLE (PREFIX_0F3A40) },
6055 { PREFIX_TABLE (PREFIX_0F3A41) },
6056 { PREFIX_TABLE (PREFIX_0F3A42) },
6057 { "(bad)", { XX } },
6058 { PREFIX_TABLE (PREFIX_0F3A44) },
6059 { "(bad)", { XX } },
6060 { "(bad)", { XX } },
6061 { "(bad)", { XX } },
6062 /* 48 */
6063 { "(bad)", { XX } },
6064 { "(bad)", { XX } },
6065 { "(bad)", { XX } },
6066 { "(bad)", { XX } },
6067 { "(bad)", { XX } },
6068 { "(bad)", { XX } },
6069 { "(bad)", { XX } },
6070 { "(bad)", { XX } },
6071 /* 50 */
6072 { "(bad)", { XX } },
6073 { "(bad)", { XX } },
6074 { "(bad)", { XX } },
6075 { "(bad)", { XX } },
6076 { "(bad)", { XX } },
6077 { "(bad)", { XX } },
6078 { "(bad)", { XX } },
6079 { "(bad)", { XX } },
6080 /* 58 */
6081 { "(bad)", { XX } },
6082 { "(bad)", { XX } },
6083 { "(bad)", { XX } },
6084 { "(bad)", { XX } },
6085 { "(bad)", { XX } },
6086 { "(bad)", { XX } },
6087 { "(bad)", { XX } },
6088 { "(bad)", { XX } },
6089 /* 60 */
6090 { PREFIX_TABLE (PREFIX_0F3A60) },
6091 { PREFIX_TABLE (PREFIX_0F3A61) },
6092 { PREFIX_TABLE (PREFIX_0F3A62) },
6093 { PREFIX_TABLE (PREFIX_0F3A63) },
6094 { "(bad)", { XX } },
6095 { "(bad)", { XX } },
6096 { "(bad)", { XX } },
6097 { "(bad)", { XX } },
6098 /* 68 */
6099 { "(bad)", { XX } },
6100 { "(bad)", { XX } },
6101 { "(bad)", { XX } },
6102 { "(bad)", { XX } },
6103 { "(bad)", { XX } },
6104 { "(bad)", { XX } },
6105 { "(bad)", { XX } },
6106 { "(bad)", { XX } },
6107 /* 70 */
6108 { "(bad)", { XX } },
6109 { "(bad)", { XX } },
6110 { "(bad)", { XX } },
6111 { "(bad)", { XX } },
6112 { "(bad)", { XX } },
6113 { "(bad)", { XX } },
6114 { "(bad)", { XX } },
6115 { "(bad)", { XX } },
6116 /* 78 */
6117 { "(bad)", { XX } },
6118 { "(bad)", { XX } },
6119 { "(bad)", { XX } },
6120 { "(bad)", { XX } },
6121 { "(bad)", { XX } },
6122 { "(bad)", { XX } },
6123 { "(bad)", { XX } },
6124 { "(bad)", { XX } },
6125 /* 80 */
6126 { "(bad)", { XX } },
6127 { "(bad)", { XX } },
6128 { "(bad)", { XX } },
6129 { "(bad)", { XX } },
6130 { "(bad)", { XX } },
6131 { "(bad)", { XX } },
6132 { "(bad)", { XX } },
6133 { "(bad)", { XX } },
6134 /* 88 */
6135 { "(bad)", { XX } },
6136 { "(bad)", { XX } },
6137 { "(bad)", { XX } },
6138 { "(bad)", { XX } },
6139 { "(bad)", { XX } },
6140 { "(bad)", { XX } },
6141 { "(bad)", { XX } },
6142 { "(bad)", { XX } },
6143 /* 90 */
6144 { "(bad)", { XX } },
6145 { "(bad)", { XX } },
6146 { "(bad)", { XX } },
6147 { "(bad)", { XX } },
6148 { "(bad)", { XX } },
6149 { "(bad)", { XX } },
6150 { "(bad)", { XX } },
6151 { "(bad)", { XX } },
6152 /* 98 */
6153 { "(bad)", { XX } },
6154 { "(bad)", { XX } },
6155 { "(bad)", { XX } },
6156 { "(bad)", { XX } },
6157 { "(bad)", { XX } },
6158 { "(bad)", { XX } },
6159 { "(bad)", { XX } },
6160 { "(bad)", { XX } },
6161 /* a0 */
6162 { "(bad)", { XX } },
6163 { "(bad)", { XX } },
6164 { "(bad)", { XX } },
6165 { "(bad)", { XX } },
6166 { "(bad)", { XX } },
6167 { "(bad)", { XX } },
6168 { "(bad)", { XX } },
6169 { "(bad)", { XX } },
6170 /* a8 */
6171 { "(bad)", { XX } },
6172 { "(bad)", { XX } },
6173 { "(bad)", { XX } },
6174 { "(bad)", { XX } },
6175 { "(bad)", { XX } },
6176 { "(bad)", { XX } },
6177 { "(bad)", { XX } },
6178 { "(bad)", { XX } },
6179 /* b0 */
6180 { "(bad)", { XX } },
6181 { "(bad)", { XX } },
6182 { "(bad)", { XX } },
6183 { "(bad)", { XX } },
6184 { "(bad)", { XX } },
6185 { "(bad)", { XX } },
6186 { "(bad)", { XX } },
6187 { "(bad)", { XX } },
6188 /* b8 */
6189 { "(bad)", { XX } },
6190 { "(bad)", { XX } },
6191 { "(bad)", { XX } },
6192 { "(bad)", { XX } },
6193 { "(bad)", { XX } },
6194 { "(bad)", { XX } },
6195 { "(bad)", { XX } },
6196 { "(bad)", { XX } },
6197 /* c0 */
6198 { "(bad)", { XX } },
6199 { "(bad)", { XX } },
6200 { "(bad)", { XX } },
6201 { "(bad)", { XX } },
6202 { "(bad)", { XX } },
6203 { "(bad)", { XX } },
6204 { "(bad)", { XX } },
6205 { "(bad)", { XX } },
6206 /* c8 */
6207 { "(bad)", { XX } },
6208 { "(bad)", { XX } },
6209 { "(bad)", { XX } },
6210 { "(bad)", { XX } },
6211 { "(bad)", { XX } },
6212 { "(bad)", { XX } },
6213 { "(bad)", { XX } },
6214 { "(bad)", { XX } },
6215 /* d0 */
6216 { "(bad)", { XX } },
6217 { "(bad)", { XX } },
6218 { "(bad)", { XX } },
6219 { "(bad)", { XX } },
6220 { "(bad)", { XX } },
6221 { "(bad)", { XX } },
6222 { "(bad)", { XX } },
6223 { "(bad)", { XX } },
6224 /* d8 */
6225 { "(bad)", { XX } },
6226 { "(bad)", { XX } },
6227 { "(bad)", { XX } },
6228 { "(bad)", { XX } },
6229 { "(bad)", { XX } },
6230 { "(bad)", { XX } },
6231 { "(bad)", { XX } },
6232 { PREFIX_TABLE (PREFIX_0F3ADF) },
6233 /* e0 */
6234 { "(bad)", { XX } },
6235 { "(bad)", { XX } },
6236 { "(bad)", { XX } },
6237 { "(bad)", { XX } },
6238 { "(bad)", { XX } },
6239 { "(bad)", { XX } },
6240 { "(bad)", { XX } },
6241 { "(bad)", { XX } },
6242 /* e8 */
6243 { "(bad)", { XX } },
6244 { "(bad)", { XX } },
6245 { "(bad)", { XX } },
6246 { "(bad)", { XX } },
6247 { "(bad)", { XX } },
6248 { "(bad)", { XX } },
6249 { "(bad)", { XX } },
6250 { "(bad)", { XX } },
6251 /* f0 */
6252 { "(bad)", { XX } },
6253 { "(bad)", { XX } },
6254 { "(bad)", { XX } },
6255 { "(bad)", { XX } },
6256 { "(bad)", { XX } },
6257 { "(bad)", { XX } },
6258 { "(bad)", { XX } },
6259 { "(bad)", { XX } },
6260 /* f8 */
6261 { "(bad)", { XX } },
6262 { "(bad)", { XX } },
6263 { "(bad)", { XX } },
6264 { "(bad)", { XX } },
6265 { "(bad)", { XX } },
6266 { "(bad)", { XX } },
6267 { "(bad)", { XX } },
6268 { "(bad)", { XX } },
6269 },
6270 /* THREE_BYTE_0F7A */
6271 {
6272 /* 00 */
6273 { "(bad)", { XX } },
6274 { "(bad)", { XX } },
6275 { "(bad)", { XX } },
6276 { "(bad)", { XX } },
6277 { "(bad)", { XX } },
6278 { "(bad)", { XX } },
6279 { "(bad)", { XX } },
6280 { "(bad)", { XX } },
6281 /* 08 */
6282 { "(bad)", { XX } },
6283 { "(bad)", { XX } },
6284 { "(bad)", { XX } },
6285 { "(bad)", { XX } },
6286 { "(bad)", { XX } },
6287 { "(bad)", { XX } },
6288 { "(bad)", { XX } },
6289 { "(bad)", { XX } },
6290 /* 10 */
6291 { "frczps", { XM, EXq } },
6292 { "frczpd", { XM, EXq } },
6293 { "frczss", { XM, EXq } },
6294 { "frczsd", { XM, EXq } },
6295 { "(bad)", { XX } },
6296 { "(bad)", { XX } },
6297 { "(bad)", { XX } },
6298 { "(bad)", { XX } },
6299 /* 18 */
6300 { "(bad)", { XX } },
6301 { "(bad)", { XX } },
6302 { "(bad)", { XX } },
6303 { "(bad)", { XX } },
6304 { "(bad)", { XX } },
6305 { "(bad)", { XX } },
6306 { "(bad)", { XX } },
6307 { "(bad)", { XX } },
6308 /* 20 */
6309 { "ptest", { XX } },
6310 { "(bad)", { XX } },
6311 { "(bad)", { XX } },
6312 { "(bad)", { XX } },
6313 { "(bad)", { XX } },
6314 { "(bad)", { XX } },
6315 { "(bad)", { XX } },
6316 { "(bad)", { XX } },
6317 /* 28 */
6318 { "(bad)", { XX } },
6319 { "(bad)", { XX } },
6320 { "(bad)", { XX } },
6321 { "(bad)", { XX } },
6322 { "(bad)", { XX } },
6323 { "(bad)", { XX } },
6324 { "(bad)", { XX } },
6325 { "(bad)", { XX } },
6326 /* 30 */
6327 { "cvtph2ps", { XM, EXd } },
6328 { "cvtps2ph", { EXd, XM } },
6329 { "(bad)", { XX } },
6330 { "(bad)", { XX } },
6331 { "(bad)", { XX } },
6332 { "(bad)", { XX } },
6333 { "(bad)", { XX } },
6334 { "(bad)", { XX } },
6335 /* 38 */
6336 { "(bad)", { XX } },
6337 { "(bad)", { XX } },
6338 { "(bad)", { XX } },
6339 { "(bad)", { XX } },
6340 { "(bad)", { XX } },
6341 { "(bad)", { XX } },
6342 { "(bad)", { XX } },
6343 { "(bad)", { XX } },
6344 /* 40 */
6345 { "(bad)", { XX } },
6346 { "phaddbw", { XM, EXq } },
6347 { "phaddbd", { XM, EXq } },
6348 { "phaddbq", { XM, EXq } },
6349 { "(bad)", { XX } },
6350 { "(bad)", { XX } },
6351 { "phaddwd", { XM, EXq } },
6352 { "phaddwq", { XM, EXq } },
6353 /* 48 */
6354 { "(bad)", { XX } },
6355 { "(bad)", { XX } },
6356 { "(bad)", { XX } },
6357 { "phadddq", { XM, EXq } },
6358 { "(bad)", { XX } },
6359 { "(bad)", { XX } },
6360 { "(bad)", { XX } },
6361 { "(bad)", { XX } },
6362 /* 50 */
6363 { "(bad)", { XX } },
6364 { "phaddubw", { XM, EXq } },
6365 { "phaddubd", { XM, EXq } },
6366 { "phaddubq", { XM, EXq } },
6367 { "(bad)", { XX } },
6368 { "(bad)", { XX } },
6369 { "phadduwd", { XM, EXq } },
6370 { "phadduwq", { XM, EXq } },
6371 /* 58 */
6372 { "(bad)", { XX } },
6373 { "(bad)", { XX } },
6374 { "(bad)", { XX } },
6375 { "phaddudq", { XM, EXq } },
6376 { "(bad)", { XX } },
6377 { "(bad)", { XX } },
6378 { "(bad)", { XX } },
6379 { "(bad)", { XX } },
6380 /* 60 */
6381 { "(bad)", { XX } },
6382 { "phsubbw", { XM, EXq } },
6383 { "phsubbd", { XM, EXq } },
6384 { "phsubbq", { XM, EXq } },
6385 { "(bad)", { XX } },
6386 { "(bad)", { XX } },
6387 { "(bad)", { XX } },
6388 { "(bad)", { XX } },
6389 /* 68 */
6390 { "(bad)", { XX } },
6391 { "(bad)", { XX } },
6392 { "(bad)", { XX } },
6393 { "(bad)", { XX } },
6394 { "(bad)", { XX } },
6395 { "(bad)", { XX } },
6396 { "(bad)", { XX } },
6397 { "(bad)", { XX } },
6398 /* 70 */
6399 { "(bad)", { XX } },
6400 { "(bad)", { XX } },
6401 { "(bad)", { XX } },
6402 { "(bad)", { XX } },
6403 { "(bad)", { XX } },
6404 { "(bad)", { XX } },
6405 { "(bad)", { XX } },
6406 { "(bad)", { XX } },
6407 /* 78 */
6408 { "(bad)", { XX } },
6409 { "(bad)", { XX } },
6410 { "(bad)", { XX } },
6411 { "(bad)", { XX } },
6412 { "(bad)", { XX } },
6413 { "(bad)", { XX } },
6414 { "(bad)", { XX } },
6415 { "(bad)", { XX } },
6416 /* 80 */
6417 { "(bad)", { XX } },
6418 { "(bad)", { XX } },
6419 { "(bad)", { XX } },
6420 { "(bad)", { XX } },
6421 { "(bad)", { XX } },
6422 { "(bad)", { XX } },
6423 { "(bad)", { XX } },
6424 { "(bad)", { XX } },
6425 /* 88 */
6426 { "(bad)", { XX } },
6427 { "(bad)", { XX } },
6428 { "(bad)", { XX } },
6429 { "(bad)", { XX } },
6430 { "(bad)", { XX } },
6431 { "(bad)", { XX } },
6432 { "(bad)", { XX } },
6433 { "(bad)", { XX } },
6434 /* 90 */
6435 { "(bad)", { XX } },
6436 { "(bad)", { XX } },
6437 { "(bad)", { XX } },
6438 { "(bad)", { XX } },
6439 { "(bad)", { XX } },
6440 { "(bad)", { XX } },
6441 { "(bad)", { XX } },
6442 { "(bad)", { XX } },
6443 /* 98 */
6444 { "(bad)", { XX } },
6445 { "(bad)", { XX } },
6446 { "(bad)", { XX } },
6447 { "(bad)", { XX } },
6448 { "(bad)", { XX } },
6449 { "(bad)", { XX } },
6450 { "(bad)", { XX } },
6451 { "(bad)", { XX } },
6452 /* a0 */
6453 { "(bad)", { XX } },
6454 { "(bad)", { XX } },
6455 { "(bad)", { XX } },
6456 { "(bad)", { XX } },
6457 { "(bad)", { XX } },
6458 { "(bad)", { XX } },
6459 { "(bad)", { XX } },
6460 { "(bad)", { XX } },
6461 /* a8 */
6462 { "(bad)", { XX } },
6463 { "(bad)", { XX } },
6464 { "(bad)", { XX } },
6465 { "(bad)", { XX } },
6466 { "(bad)", { XX } },
6467 { "(bad)", { XX } },
6468 { "(bad)", { XX } },
6469 { "(bad)", { XX } },
6470 /* b0 */
6471 { "(bad)", { XX } },
6472 { "(bad)", { XX } },
6473 { "(bad)", { XX } },
6474 { "(bad)", { XX } },
6475 { "(bad)", { XX } },
6476 { "(bad)", { XX } },
6477 { "(bad)", { XX } },
6478 { "(bad)", { XX } },
6479 /* b8 */
6480 { "(bad)", { XX } },
6481 { "(bad)", { XX } },
6482 { "(bad)", { XX } },
6483 { "(bad)", { XX } },
6484 { "(bad)", { XX } },
6485 { "(bad)", { XX } },
6486 { "(bad)", { XX } },
6487 { "(bad)", { XX } },
6488 /* c0 */
6489 { "(bad)", { XX } },
6490 { "(bad)", { XX } },
6491 { "(bad)", { XX } },
6492 { "(bad)", { XX } },
6493 { "(bad)", { XX } },
6494 { "(bad)", { XX } },
6495 { "(bad)", { XX } },
6496 { "(bad)", { XX } },
6497 /* c8 */
6498 { "(bad)", { XX } },
6499 { "(bad)", { XX } },
6500 { "(bad)", { XX } },
6501 { "(bad)", { XX } },
6502 { "(bad)", { XX } },
6503 { "(bad)", { XX } },
6504 { "(bad)", { XX } },
6505 { "(bad)", { XX } },
6506 /* d0 */
6507 { "(bad)", { XX } },
6508 { "(bad)", { XX } },
6509 { "(bad)", { XX } },
6510 { "(bad)", { XX } },
6511 { "(bad)", { XX } },
6512 { "(bad)", { XX } },
6513 { "(bad)", { XX } },
6514 { "(bad)", { XX } },
6515 /* d8 */
6516 { "(bad)", { XX } },
6517 { "(bad)", { XX } },
6518 { "(bad)", { XX } },
6519 { "(bad)", { XX } },
6520 { "(bad)", { XX } },
6521 { "(bad)", { XX } },
6522 { "(bad)", { XX } },
6523 { "(bad)", { XX } },
6524 /* e0 */
6525 { "(bad)", { XX } },
6526 { "(bad)", { XX } },
6527 { "(bad)", { XX } },
6528 { "(bad)", { XX } },
6529 { "(bad)", { XX } },
6530 { "(bad)", { XX } },
6531 { "(bad)", { XX } },
6532 { "(bad)", { XX } },
6533 /* e8 */
6534 { "(bad)", { XX } },
6535 { "(bad)", { XX } },
6536 { "(bad)", { XX } },
6537 { "(bad)", { XX } },
6538 { "(bad)", { XX } },
6539 { "(bad)", { XX } },
6540 { "(bad)", { XX } },
6541 { "(bad)", { XX } },
6542 /* f0 */
6543 { "(bad)", { XX } },
6544 { "(bad)", { XX } },
6545 { "(bad)", { XX } },
6546 { "(bad)", { XX } },
6547 { "(bad)", { XX } },
6548 { "(bad)", { XX } },
6549 { "(bad)", { XX } },
6550 { "(bad)", { XX } },
6551 /* f8 */
6552 { "(bad)", { XX } },
6553 { "(bad)", { XX } },
6554 { "(bad)", { XX } },
6555 { "(bad)", { XX } },
6556 { "(bad)", { XX } },
6557 { "(bad)", { XX } },
6558 { "(bad)", { XX } },
6559 { "(bad)", { XX } },
6560 },
6561 /* THREE_BYTE_0F7B */
6562 {
6563 /* 00 */
6564 { "(bad)", { XX } },
6565 { "(bad)", { XX } },
6566 { "(bad)", { XX } },
6567 { "(bad)", { XX } },
6568 { "(bad)", { XX } },
6569 { "(bad)", { XX } },
6570 { "(bad)", { XX } },
6571 { "(bad)", { XX } },
6572 /* 08 */
6573 { "(bad)", { XX } },
6574 { "(bad)", { XX } },
6575 { "(bad)", { XX } },
6576 { "(bad)", { XX } },
6577 { "(bad)", { XX } },
6578 { "(bad)", { XX } },
6579 { "(bad)", { XX } },
6580 { "(bad)", { XX } },
6581 /* 10 */
6582 { "(bad)", { XX } },
6583 { "(bad)", { XX } },
6584 { "(bad)", { XX } },
6585 { "(bad)", { XX } },
6586 { "(bad)", { XX } },
6587 { "(bad)", { XX } },
6588 { "(bad)", { XX } },
6589 { "(bad)", { XX } },
6590 /* 18 */
6591 { "(bad)", { XX } },
6592 { "(bad)", { XX } },
6593 { "(bad)", { XX } },
6594 { "(bad)", { XX } },
6595 { "(bad)", { XX } },
6596 { "(bad)", { XX } },
6597 { "(bad)", { XX } },
6598 { "(bad)", { XX } },
6599 /* 20 */
6600 { "(bad)", { XX } },
6601 { "(bad)", { XX } },
6602 { "(bad)", { XX } },
6603 { "(bad)", { XX } },
6604 { "(bad)", { XX } },
6605 { "(bad)", { XX } },
6606 { "(bad)", { XX } },
6607 { "(bad)", { XX } },
6608 /* 28 */
6609 { "(bad)", { XX } },
6610 { "(bad)", { XX } },
6611 { "(bad)", { XX } },
6612 { "(bad)", { XX } },
6613 { "(bad)", { XX } },
6614 { "(bad)", { XX } },
6615 { "(bad)", { XX } },
6616 { "(bad)", { XX } },
6617 /* 30 */
6618 { "(bad)", { XX } },
6619 { "(bad)", { XX } },
6620 { "(bad)", { XX } },
6621 { "(bad)", { XX } },
6622 { "(bad)", { XX } },
6623 { "(bad)", { XX } },
6624 { "(bad)", { XX } },
6625 { "(bad)", { XX } },
6626 /* 38 */
6627 { "(bad)", { XX } },
6628 { "(bad)", { XX } },
6629 { "(bad)", { XX } },
6630 { "(bad)", { XX } },
6631 { "(bad)", { XX } },
6632 { "(bad)", { XX } },
6633 { "(bad)", { XX } },
6634 { "(bad)", { XX } },
6635 /* 40 */
6636 { "protb", { XM, EXq, Ib } },
6637 { "protw", { XM, EXq, Ib } },
6638 { "protd", { XM, EXq, Ib } },
6639 { "protq", { XM, EXq, Ib } },
6640 { "pshlb", { XM, EXq, Ib } },
6641 { "pshlw", { XM, EXq, Ib } },
6642 { "pshld", { XM, EXq, Ib } },
6643 { "pshlq", { XM, EXq, Ib } },
6644 /* 48 */
6645 { "pshab", { XM, EXq, Ib } },
6646 { "pshaw", { XM, EXq, Ib } },
6647 { "pshad", { XM, EXq, Ib } },
6648 { "pshaq", { XM, EXq, Ib } },
6649 { "(bad)", { XX } },
6650 { "(bad)", { XX } },
6651 { "(bad)", { XX } },
6652 { "(bad)", { XX } },
6653 /* 50 */
6654 { "(bad)", { XX } },
6655 { "(bad)", { XX } },
6656 { "(bad)", { XX } },
6657 { "(bad)", { XX } },
6658 { "(bad)", { XX } },
6659 { "(bad)", { XX } },
6660 { "(bad)", { XX } },
6661 { "(bad)", { XX } },
6662 /* 58 */
6663 { "(bad)", { XX } },
6664 { "(bad)", { XX } },
6665 { "(bad)", { XX } },
6666 { "(bad)", { XX } },
6667 { "(bad)", { XX } },
6668 { "(bad)", { XX } },
6669 { "(bad)", { XX } },
6670 { "(bad)", { XX } },
6671 /* 60 */
6672 { "(bad)", { XX } },
6673 { "(bad)", { XX } },
6674 { "(bad)", { XX } },
6675 { "(bad)", { XX } },
6676 { "(bad)", { XX } },
6677 { "(bad)", { XX } },
6678 { "(bad)", { XX } },
6679 { "(bad)", { XX } },
6680 /* 68 */
6681 { "(bad)", { XX } },
6682 { "(bad)", { XX } },
6683 { "(bad)", { XX } },
6684 { "(bad)", { XX } },
6685 { "(bad)", { XX } },
6686 { "(bad)", { XX } },
6687 { "(bad)", { XX } },
6688 { "(bad)", { XX } },
6689 /* 70 */
6690 { "(bad)", { XX } },
6691 { "(bad)", { XX } },
6692 { "(bad)", { XX } },
6693 { "(bad)", { XX } },
6694 { "(bad)", { XX } },
6695 { "(bad)", { XX } },
6696 { "(bad)", { XX } },
6697 { "(bad)", { XX } },
6698 /* 78 */
6699 { "(bad)", { XX } },
6700 { "(bad)", { XX } },
6701 { "(bad)", { XX } },
6702 { "(bad)", { XX } },
6703 { "(bad)", { XX } },
6704 { "(bad)", { XX } },
6705 { "(bad)", { XX } },
6706 { "(bad)", { XX } },
6707 /* 80 */
6708 { "(bad)", { XX } },
6709 { "(bad)", { XX } },
6710 { "(bad)", { XX } },
6711 { "(bad)", { XX } },
6712 { "(bad)", { XX } },
6713 { "(bad)", { XX } },
6714 { "(bad)", { XX } },
6715 { "(bad)", { XX } },
6716 /* 88 */
6717 { "(bad)", { XX } },
6718 { "(bad)", { XX } },
6719 { "(bad)", { XX } },
6720 { "(bad)", { XX } },
6721 { "(bad)", { XX } },
6722 { "(bad)", { XX } },
6723 { "(bad)", { XX } },
6724 { "(bad)", { XX } },
6725 /* 90 */
6726 { "(bad)", { XX } },
6727 { "(bad)", { XX } },
6728 { "(bad)", { XX } },
6729 { "(bad)", { XX } },
6730 { "(bad)", { XX } },
6731 { "(bad)", { XX } },
6732 { "(bad)", { XX } },
6733 { "(bad)", { XX } },
6734 /* 98 */
6735 { "(bad)", { XX } },
6736 { "(bad)", { XX } },
6737 { "(bad)", { XX } },
6738 { "(bad)", { XX } },
6739 { "(bad)", { XX } },
6740 { "(bad)", { XX } },
6741 { "(bad)", { XX } },
6742 { "(bad)", { XX } },
6743 /* a0 */
6744 { "(bad)", { XX } },
6745 { "(bad)", { XX } },
6746 { "(bad)", { XX } },
6747 { "(bad)", { XX } },
6748 { "(bad)", { XX } },
6749 { "(bad)", { XX } },
6750 { "(bad)", { XX } },
6751 { "(bad)", { XX } },
6752 /* a8 */
6753 { "(bad)", { XX } },
6754 { "(bad)", { XX } },
6755 { "(bad)", { XX } },
6756 { "(bad)", { XX } },
6757 { "(bad)", { XX } },
6758 { "(bad)", { XX } },
6759 { "(bad)", { XX } },
6760 { "(bad)", { XX } },
6761 /* b0 */
6762 { "(bad)", { XX } },
6763 { "(bad)", { XX } },
6764 { "(bad)", { XX } },
6765 { "(bad)", { XX } },
6766 { "(bad)", { XX } },
6767 { "(bad)", { XX } },
6768 { "(bad)", { XX } },
6769 { "(bad)", { XX } },
6770 /* b8 */
6771 { "(bad)", { XX } },
6772 { "(bad)", { XX } },
6773 { "(bad)", { XX } },
6774 { "(bad)", { XX } },
6775 { "(bad)", { XX } },
6776 { "(bad)", { XX } },
6777 { "(bad)", { XX } },
6778 { "(bad)", { XX } },
6779 /* c0 */
6780 { "(bad)", { XX } },
6781 { "(bad)", { XX } },
6782 { "(bad)", { XX } },
6783 { "(bad)", { XX } },
6784 { "(bad)", { XX } },
6785 { "(bad)", { XX } },
6786 { "(bad)", { XX } },
6787 { "(bad)", { XX } },
6788 /* c8 */
6789 { "(bad)", { XX } },
6790 { "(bad)", { XX } },
6791 { "(bad)", { XX } },
6792 { "(bad)", { XX } },
6793 { "(bad)", { XX } },
6794 { "(bad)", { XX } },
6795 { "(bad)", { XX } },
6796 { "(bad)", { XX } },
6797 /* d0 */
6798 { "(bad)", { XX } },
6799 { "(bad)", { XX } },
6800 { "(bad)", { XX } },
6801 { "(bad)", { XX } },
6802 { "(bad)", { XX } },
6803 { "(bad)", { XX } },
6804 { "(bad)", { XX } },
6805 { "(bad)", { XX } },
6806 /* d8 */
6807 { "(bad)", { XX } },
6808 { "(bad)", { XX } },
6809 { "(bad)", { XX } },
6810 { "(bad)", { XX } },
6811 { "(bad)", { XX } },
6812 { "(bad)", { XX } },
6813 { "(bad)", { XX } },
6814 { "(bad)", { XX } },
6815 /* e0 */
6816 { "(bad)", { XX } },
6817 { "(bad)", { XX } },
6818 { "(bad)", { XX } },
6819 { "(bad)", { XX } },
6820 { "(bad)", { XX } },
6821 { "(bad)", { XX } },
6822 { "(bad)", { XX } },
6823 { "(bad)", { XX } },
6824 /* e8 */
6825 { "(bad)", { XX } },
6826 { "(bad)", { XX } },
6827 { "(bad)", { XX } },
6828 { "(bad)", { XX } },
6829 { "(bad)", { XX } },
6830 { "(bad)", { XX } },
6831 { "(bad)", { XX } },
6832 { "(bad)", { XX } },
6833 /* f0 */
6834 { "(bad)", { XX } },
6835 { "(bad)", { XX } },
6836 { "(bad)", { XX } },
6837 { "(bad)", { XX } },
6838 { "(bad)", { XX } },
6839 { "(bad)", { XX } },
6840 { "(bad)", { XX } },
6841 { "(bad)", { XX } },
6842 /* f8 */
6843 { "(bad)", { XX } },
6844 { "(bad)", { XX } },
6845 { "(bad)", { XX } },
6846 { "(bad)", { XX } },
6847 { "(bad)", { XX } },
6848 { "(bad)", { XX } },
6849 { "(bad)", { XX } },
6850 { "(bad)", { XX } },
6851 },
6852 };
6853
6854 static const struct dis386 vex_table[][256] = {
6855 /* VEX_0F */
6856 {
6857 /* 00 */
6858 { "(bad)", { XX } },
6859 { "(bad)", { XX } },
6860 { "(bad)", { XX } },
6861 { "(bad)", { XX } },
6862 { "(bad)", { XX } },
6863 { "(bad)", { XX } },
6864 { "(bad)", { XX } },
6865 { "(bad)", { XX } },
6866 /* 08 */
6867 { "(bad)", { XX } },
6868 { "(bad)", { XX } },
6869 { "(bad)", { XX } },
6870 { "(bad)", { XX } },
6871 { "(bad)", { XX } },
6872 { "(bad)", { XX } },
6873 { "(bad)", { XX } },
6874 { "(bad)", { XX } },
6875 /* 10 */
6876 { PREFIX_TABLE (PREFIX_VEX_10) },
6877 { PREFIX_TABLE (PREFIX_VEX_11) },
6878 { PREFIX_TABLE (PREFIX_VEX_12) },
6879 { MOD_TABLE (MOD_VEX_13) },
6880 { "vunpcklpX", { XM, Vex, EXx } },
6881 { "vunpckhpX", { XM, Vex, EXx } },
6882 { PREFIX_TABLE (PREFIX_VEX_16) },
6883 { MOD_TABLE (MOD_VEX_17) },
6884 /* 18 */
6885 { "(bad)", { XX } },
6886 { "(bad)", { XX } },
6887 { "(bad)", { XX } },
6888 { "(bad)", { XX } },
6889 { "(bad)", { XX } },
6890 { "(bad)", { XX } },
6891 { "(bad)", { XX } },
6892 { "(bad)", { XX } },
6893 /* 20 */
6894 { "(bad)", { XX } },
6895 { "(bad)", { XX } },
6896 { "(bad)", { XX } },
6897 { "(bad)", { XX } },
6898 { "(bad)", { XX } },
6899 { "(bad)", { XX } },
6900 { "(bad)", { XX } },
6901 { "(bad)", { XX } },
6902 /* 28 */
6903 { "vmovapX", { XM, EXx } },
6904 { "vmovapX", { EXx, XM } },
6905 { PREFIX_TABLE (PREFIX_VEX_2A) },
6906 { MOD_TABLE (MOD_VEX_2B) },
6907 { PREFIX_TABLE (PREFIX_VEX_2C) },
6908 { PREFIX_TABLE (PREFIX_VEX_2D) },
6909 { PREFIX_TABLE (PREFIX_VEX_2E) },
6910 { PREFIX_TABLE (PREFIX_VEX_2F) },
6911 /* 30 */
6912 { "(bad)", { XX } },
6913 { "(bad)", { XX } },
6914 { "(bad)", { XX } },
6915 { "(bad)", { XX } },
6916 { "(bad)", { XX } },
6917 { "(bad)", { XX } },
6918 { "(bad)", { XX } },
6919 { "(bad)", { XX } },
6920 /* 38 */
6921 { "(bad)", { XX } },
6922 { "(bad)", { XX } },
6923 { "(bad)", { XX } },
6924 { "(bad)", { XX } },
6925 { "(bad)", { XX } },
6926 { "(bad)", { XX } },
6927 { "(bad)", { XX } },
6928 { "(bad)", { XX } },
6929 /* 40 */
6930 { "(bad)", { XX } },
6931 { "(bad)", { XX } },
6932 { "(bad)", { XX } },
6933 { "(bad)", { XX } },
6934 { "(bad)", { XX } },
6935 { "(bad)", { XX } },
6936 { "(bad)", { XX } },
6937 { "(bad)", { XX } },
6938 /* 48 */
6939 { "(bad)", { XX } },
6940 { "(bad)", { XX } },
6941 { "(bad)", { XX } },
6942 { "(bad)", { XX } },
6943 { "(bad)", { XX } },
6944 { "(bad)", { XX } },
6945 { "(bad)", { XX } },
6946 { "(bad)", { XX } },
6947 /* 50 */
6948 { MOD_TABLE (MOD_VEX_51) },
6949 { PREFIX_TABLE (PREFIX_VEX_51) },
6950 { PREFIX_TABLE (PREFIX_VEX_52) },
6951 { PREFIX_TABLE (PREFIX_VEX_53) },
6952 { "vandpX", { XM, Vex, EXx } },
6953 { "vandnpX", { XM, Vex, EXx } },
6954 { "vorpX", { XM, Vex, EXx } },
6955 { "vxorpX", { XM, Vex, EXx } },
6956 /* 58 */
6957 { PREFIX_TABLE (PREFIX_VEX_58) },
6958 { PREFIX_TABLE (PREFIX_VEX_59) },
6959 { PREFIX_TABLE (PREFIX_VEX_5A) },
6960 { PREFIX_TABLE (PREFIX_VEX_5B) },
6961 { PREFIX_TABLE (PREFIX_VEX_5C) },
6962 { PREFIX_TABLE (PREFIX_VEX_5D) },
6963 { PREFIX_TABLE (PREFIX_VEX_5E) },
6964 { PREFIX_TABLE (PREFIX_VEX_5F) },
6965 /* 60 */
6966 { PREFIX_TABLE (PREFIX_VEX_60) },
6967 { PREFIX_TABLE (PREFIX_VEX_61) },
6968 { PREFIX_TABLE (PREFIX_VEX_62) },
6969 { PREFIX_TABLE (PREFIX_VEX_63) },
6970 { PREFIX_TABLE (PREFIX_VEX_64) },
6971 { PREFIX_TABLE (PREFIX_VEX_65) },
6972 { PREFIX_TABLE (PREFIX_VEX_66) },
6973 { PREFIX_TABLE (PREFIX_VEX_67) },
6974 /* 68 */
6975 { PREFIX_TABLE (PREFIX_VEX_68) },
6976 { PREFIX_TABLE (PREFIX_VEX_69) },
6977 { PREFIX_TABLE (PREFIX_VEX_6A) },
6978 { PREFIX_TABLE (PREFIX_VEX_6B) },
6979 { PREFIX_TABLE (PREFIX_VEX_6C) },
6980 { PREFIX_TABLE (PREFIX_VEX_6D) },
6981 { PREFIX_TABLE (PREFIX_VEX_6E) },
6982 { PREFIX_TABLE (PREFIX_VEX_6F) },
6983 /* 70 */
6984 { PREFIX_TABLE (PREFIX_VEX_70) },
6985 { REG_TABLE (REG_VEX_71) },
6986 { REG_TABLE (REG_VEX_72) },
6987 { REG_TABLE (REG_VEX_73) },
6988 { PREFIX_TABLE (PREFIX_VEX_74) },
6989 { PREFIX_TABLE (PREFIX_VEX_75) },
6990 { PREFIX_TABLE (PREFIX_VEX_76) },
6991 { PREFIX_TABLE (PREFIX_VEX_77) },
6992 /* 78 */
6993 { "(bad)", { XX } },
6994 { "(bad)", { XX } },
6995 { "(bad)", { XX } },
6996 { "(bad)", { XX } },
6997 { PREFIX_TABLE (PREFIX_VEX_7C) },
6998 { PREFIX_TABLE (PREFIX_VEX_7D) },
6999 { PREFIX_TABLE (PREFIX_VEX_7E) },
7000 { PREFIX_TABLE (PREFIX_VEX_7F) },
7001 /* 80 */
7002 { "(bad)", { XX } },
7003 { "(bad)", { XX } },
7004 { "(bad)", { XX } },
7005 { "(bad)", { XX } },
7006 { "(bad)", { XX } },
7007 { "(bad)", { XX } },
7008 { "(bad)", { XX } },
7009 { "(bad)", { XX } },
7010 /* 88 */
7011 { "(bad)", { XX } },
7012 { "(bad)", { XX } },
7013 { "(bad)", { XX } },
7014 { "(bad)", { XX } },
7015 { "(bad)", { XX } },
7016 { "(bad)", { XX } },
7017 { "(bad)", { XX } },
7018 { "(bad)", { XX } },
7019 /* 90 */
7020 { "(bad)", { XX } },
7021 { "(bad)", { XX } },
7022 { "(bad)", { XX } },
7023 { "(bad)", { XX } },
7024 { "(bad)", { XX } },
7025 { "(bad)", { XX } },
7026 { "(bad)", { XX } },
7027 { "(bad)", { XX } },
7028 /* 98 */
7029 { "(bad)", { XX } },
7030 { "(bad)", { XX } },
7031 { "(bad)", { XX } },
7032 { "(bad)", { XX } },
7033 { "(bad)", { XX } },
7034 { "(bad)", { XX } },
7035 { "(bad)", { XX } },
7036 { "(bad)", { XX } },
7037 /* a0 */
7038 { "(bad)", { XX } },
7039 { "(bad)", { XX } },
7040 { "(bad)", { XX } },
7041 { "(bad)", { XX } },
7042 { "(bad)", { XX } },
7043 { "(bad)", { XX } },
7044 { "(bad)", { XX } },
7045 { "(bad)", { XX } },
7046 /* a8 */
7047 { "(bad)", { XX } },
7048 { "(bad)", { XX } },
7049 { "(bad)", { XX } },
7050 { "(bad)", { XX } },
7051 { "(bad)", { XX } },
7052 { "(bad)", { XX } },
7053 { REG_TABLE (REG_VEX_AE) },
7054 { "(bad)", { XX } },
7055 /* b0 */
7056 { "(bad)", { XX } },
7057 { "(bad)", { XX } },
7058 { "(bad)", { XX } },
7059 { "(bad)", { XX } },
7060 { "(bad)", { XX } },
7061 { "(bad)", { XX } },
7062 { "(bad)", { XX } },
7063 { "(bad)", { XX } },
7064 /* b8 */
7065 { "(bad)", { XX } },
7066 { "(bad)", { XX } },
7067 { "(bad)", { XX } },
7068 { "(bad)", { XX } },
7069 { "(bad)", { XX } },
7070 { "(bad)", { XX } },
7071 { "(bad)", { XX } },
7072 { "(bad)", { XX } },
7073 /* c0 */
7074 { "(bad)", { XX } },
7075 { "(bad)", { XX } },
7076 { PREFIX_TABLE (PREFIX_VEX_C2) },
7077 { "(bad)", { XX } },
7078 { PREFIX_TABLE (PREFIX_VEX_C4) },
7079 { PREFIX_TABLE (PREFIX_VEX_C5) },
7080 { "vshufpX", { XM, Vex, EXx, Ib } },
7081 { "(bad)", { XX } },
7082 /* c8 */
7083 { "(bad)", { XX } },
7084 { "(bad)", { XX } },
7085 { "(bad)", { XX } },
7086 { "(bad)", { XX } },
7087 { "(bad)", { XX } },
7088 { "(bad)", { XX } },
7089 { "(bad)", { XX } },
7090 { "(bad)", { XX } },
7091 /* d0 */
7092 { PREFIX_TABLE (PREFIX_VEX_D0) },
7093 { PREFIX_TABLE (PREFIX_VEX_D1) },
7094 { PREFIX_TABLE (PREFIX_VEX_D2) },
7095 { PREFIX_TABLE (PREFIX_VEX_D3) },
7096 { PREFIX_TABLE (PREFIX_VEX_D4) },
7097 { PREFIX_TABLE (PREFIX_VEX_D5) },
7098 { PREFIX_TABLE (PREFIX_VEX_D6) },
7099 { PREFIX_TABLE (PREFIX_VEX_D7) },
7100 /* d8 */
7101 { PREFIX_TABLE (PREFIX_VEX_D8) },
7102 { PREFIX_TABLE (PREFIX_VEX_D9) },
7103 { PREFIX_TABLE (PREFIX_VEX_DA) },
7104 { PREFIX_TABLE (PREFIX_VEX_DB) },
7105 { PREFIX_TABLE (PREFIX_VEX_DC) },
7106 { PREFIX_TABLE (PREFIX_VEX_DD) },
7107 { PREFIX_TABLE (PREFIX_VEX_DE) },
7108 { PREFIX_TABLE (PREFIX_VEX_DF) },
7109 /* e0 */
7110 { PREFIX_TABLE (PREFIX_VEX_E0) },
7111 { PREFIX_TABLE (PREFIX_VEX_E1) },
7112 { PREFIX_TABLE (PREFIX_VEX_E2) },
7113 { PREFIX_TABLE (PREFIX_VEX_E3) },
7114 { PREFIX_TABLE (PREFIX_VEX_E4) },
7115 { PREFIX_TABLE (PREFIX_VEX_E5) },
7116 { PREFIX_TABLE (PREFIX_VEX_E6) },
7117 { PREFIX_TABLE (PREFIX_VEX_E7) },
7118 /* e8 */
7119 { PREFIX_TABLE (PREFIX_VEX_E8) },
7120 { PREFIX_TABLE (PREFIX_VEX_E9) },
7121 { PREFIX_TABLE (PREFIX_VEX_EA) },
7122 { PREFIX_TABLE (PREFIX_VEX_EB) },
7123 { PREFIX_TABLE (PREFIX_VEX_EC) },
7124 { PREFIX_TABLE (PREFIX_VEX_ED) },
7125 { PREFIX_TABLE (PREFIX_VEX_EE) },
7126 { PREFIX_TABLE (PREFIX_VEX_EF) },
7127 /* f0 */
7128 { PREFIX_TABLE (PREFIX_VEX_F0) },
7129 { PREFIX_TABLE (PREFIX_VEX_F1) },
7130 { PREFIX_TABLE (PREFIX_VEX_F2) },
7131 { PREFIX_TABLE (PREFIX_VEX_F3) },
7132 { PREFIX_TABLE (PREFIX_VEX_F4) },
7133 { PREFIX_TABLE (PREFIX_VEX_F5) },
7134 { PREFIX_TABLE (PREFIX_VEX_F6) },
7135 { PREFIX_TABLE (PREFIX_VEX_F7) },
7136 /* f8 */
7137 { PREFIX_TABLE (PREFIX_VEX_F8) },
7138 { PREFIX_TABLE (PREFIX_VEX_F9) },
7139 { PREFIX_TABLE (PREFIX_VEX_FA) },
7140 { PREFIX_TABLE (PREFIX_VEX_FB) },
7141 { PREFIX_TABLE (PREFIX_VEX_FC) },
7142 { PREFIX_TABLE (PREFIX_VEX_FD) },
7143 { PREFIX_TABLE (PREFIX_VEX_FE) },
7144 { "(bad)", { XX } },
7145 },
7146 /* VEX_0F38 */
7147 {
7148 /* 00 */
7149 { PREFIX_TABLE (PREFIX_VEX_3800) },
7150 { PREFIX_TABLE (PREFIX_VEX_3801) },
7151 { PREFIX_TABLE (PREFIX_VEX_3802) },
7152 { PREFIX_TABLE (PREFIX_VEX_3803) },
7153 { PREFIX_TABLE (PREFIX_VEX_3804) },
7154 { PREFIX_TABLE (PREFIX_VEX_3805) },
7155 { PREFIX_TABLE (PREFIX_VEX_3806) },
7156 { PREFIX_TABLE (PREFIX_VEX_3807) },
7157 /* 08 */
7158 { PREFIX_TABLE (PREFIX_VEX_3808) },
7159 { PREFIX_TABLE (PREFIX_VEX_3809) },
7160 { PREFIX_TABLE (PREFIX_VEX_380A) },
7161 { PREFIX_TABLE (PREFIX_VEX_380B) },
7162 { PREFIX_TABLE (PREFIX_VEX_380C) },
7163 { PREFIX_TABLE (PREFIX_VEX_380D) },
7164 { PREFIX_TABLE (PREFIX_VEX_380E) },
7165 { PREFIX_TABLE (PREFIX_VEX_380F) },
7166 /* 10 */
7167 { "(bad)", { XX } },
7168 { "(bad)", { XX } },
7169 { "(bad)", { XX } },
7170 { "(bad)", { XX } },
7171 { "(bad)", { XX } },
7172 { "(bad)", { XX } },
7173 { "(bad)", { XX } },
7174 { PREFIX_TABLE (PREFIX_VEX_3817) },
7175 /* 18 */
7176 { PREFIX_TABLE (PREFIX_VEX_3818) },
7177 { PREFIX_TABLE (PREFIX_VEX_3819) },
7178 { PREFIX_TABLE (PREFIX_VEX_381A) },
7179 { "(bad)", { XX } },
7180 { PREFIX_TABLE (PREFIX_VEX_381C) },
7181 { PREFIX_TABLE (PREFIX_VEX_381D) },
7182 { PREFIX_TABLE (PREFIX_VEX_381E) },
7183 { "(bad)", { XX } },
7184 /* 20 */
7185 { PREFIX_TABLE (PREFIX_VEX_3820) },
7186 { PREFIX_TABLE (PREFIX_VEX_3821) },
7187 { PREFIX_TABLE (PREFIX_VEX_3822) },
7188 { PREFIX_TABLE (PREFIX_VEX_3823) },
7189 { PREFIX_TABLE (PREFIX_VEX_3824) },
7190 { PREFIX_TABLE (PREFIX_VEX_3825) },
7191 { "(bad)", { XX } },
7192 { "(bad)", { XX } },
7193 /* 28 */
7194 { PREFIX_TABLE (PREFIX_VEX_3828) },
7195 { PREFIX_TABLE (PREFIX_VEX_3829) },
7196 { PREFIX_TABLE (PREFIX_VEX_382A) },
7197 { PREFIX_TABLE (PREFIX_VEX_382B) },
7198 { PREFIX_TABLE (PREFIX_VEX_382C) },
7199 { PREFIX_TABLE (PREFIX_VEX_382D) },
7200 { PREFIX_TABLE (PREFIX_VEX_382E) },
7201 { PREFIX_TABLE (PREFIX_VEX_382F) },
7202 /* 30 */
7203 { PREFIX_TABLE (PREFIX_VEX_3830) },
7204 { PREFIX_TABLE (PREFIX_VEX_3831) },
7205 { PREFIX_TABLE (PREFIX_VEX_3832) },
7206 { PREFIX_TABLE (PREFIX_VEX_3833) },
7207 { PREFIX_TABLE (PREFIX_VEX_3834) },
7208 { PREFIX_TABLE (PREFIX_VEX_3835) },
7209 { "(bad)", { XX } },
7210 { PREFIX_TABLE (PREFIX_VEX_3837) },
7211 /* 38 */
7212 { PREFIX_TABLE (PREFIX_VEX_3838) },
7213 { PREFIX_TABLE (PREFIX_VEX_3839) },
7214 { PREFIX_TABLE (PREFIX_VEX_383A) },
7215 { PREFIX_TABLE (PREFIX_VEX_383B) },
7216 { PREFIX_TABLE (PREFIX_VEX_383C) },
7217 { PREFIX_TABLE (PREFIX_VEX_383D) },
7218 { PREFIX_TABLE (PREFIX_VEX_383E) },
7219 { PREFIX_TABLE (PREFIX_VEX_383F) },
7220 /* 40 */
7221 { PREFIX_TABLE (PREFIX_VEX_3840) },
7222 { PREFIX_TABLE (PREFIX_VEX_3841) },
7223 { "(bad)", { XX } },
7224 { "(bad)", { XX } },
7225 { "(bad)", { XX } },
7226 { "(bad)", { XX } },
7227 { "(bad)", { XX } },
7228 { "(bad)", { XX } },
7229 /* 48 */
7230 { "(bad)", { XX } },
7231 { "(bad)", { XX } },
7232 { "(bad)", { XX } },
7233 { "(bad)", { XX } },
7234 { "(bad)", { XX } },
7235 { "(bad)", { XX } },
7236 { "(bad)", { XX } },
7237 { "(bad)", { XX } },
7238 /* 50 */
7239 { "(bad)", { XX } },
7240 { "(bad)", { XX } },
7241 { "(bad)", { XX } },
7242 { "(bad)", { XX } },
7243 { "(bad)", { XX } },
7244 { "(bad)", { XX } },
7245 { "(bad)", { XX } },
7246 { "(bad)", { XX } },
7247 /* 58 */
7248 { "(bad)", { XX } },
7249 { "(bad)", { XX } },
7250 { "(bad)", { XX } },
7251 { "(bad)", { XX } },
7252 { "(bad)", { XX } },
7253 { "(bad)", { XX } },
7254 { "(bad)", { XX } },
7255 { "(bad)", { XX } },
7256 /* 60 */
7257 { "(bad)", { XX } },
7258 { "(bad)", { XX } },
7259 { "(bad)", { XX } },
7260 { "(bad)", { XX } },
7261 { "(bad)", { XX } },
7262 { "(bad)", { XX } },
7263 { "(bad)", { XX } },
7264 { "(bad)", { XX } },
7265 /* 68 */
7266 { "(bad)", { XX } },
7267 { "(bad)", { XX } },
7268 { "(bad)", { XX } },
7269 { "(bad)", { XX } },
7270 { "(bad)", { XX } },
7271 { "(bad)", { XX } },
7272 { "(bad)", { XX } },
7273 { "(bad)", { XX } },
7274 /* 70 */
7275 { "(bad)", { XX } },
7276 { "(bad)", { XX } },
7277 { "(bad)", { XX } },
7278 { "(bad)", { XX } },
7279 { "(bad)", { XX } },
7280 { "(bad)", { XX } },
7281 { "(bad)", { XX } },
7282 { "(bad)", { XX } },
7283 /* 78 */
7284 { "(bad)", { XX } },
7285 { "(bad)", { XX } },
7286 { "(bad)", { XX } },
7287 { "(bad)", { XX } },
7288 { "(bad)", { XX } },
7289 { "(bad)", { XX } },
7290 { "(bad)", { XX } },
7291 { "(bad)", { XX } },
7292 /* 80 */
7293 { "(bad)", { XX } },
7294 { "(bad)", { XX } },
7295 { "(bad)", { XX } },
7296 { "(bad)", { XX } },
7297 { "(bad)", { XX } },
7298 { "(bad)", { XX } },
7299 { "(bad)", { XX } },
7300 { "(bad)", { XX } },
7301 /* 88 */
7302 { "(bad)", { XX } },
7303 { "(bad)", { XX } },
7304 { "(bad)", { XX } },
7305 { "(bad)", { XX } },
7306 { "(bad)", { XX } },
7307 { "(bad)", { XX } },
7308 { "(bad)", { XX } },
7309 { "(bad)", { XX } },
7310 /* 90 */
7311 { "(bad)", { XX } },
7312 { "(bad)", { XX } },
7313 { "(bad)", { XX } },
7314 { "(bad)", { XX } },
7315 { "(bad)", { XX } },
7316 { "(bad)", { XX } },
7317 { "(bad)", { XX } },
7318 { "(bad)", { XX } },
7319 /* 98 */
7320 { "(bad)", { XX } },
7321 { "(bad)", { XX } },
7322 { "(bad)", { XX } },
7323 { "(bad)", { XX } },
7324 { "(bad)", { XX } },
7325 { "(bad)", { XX } },
7326 { "(bad)", { XX } },
7327 { "(bad)", { XX } },
7328 /* a0 */
7329 { "(bad)", { XX } },
7330 { "(bad)", { XX } },
7331 { "(bad)", { XX } },
7332 { "(bad)", { XX } },
7333 { "(bad)", { XX } },
7334 { "(bad)", { XX } },
7335 { "(bad)", { XX } },
7336 { "(bad)", { XX } },
7337 /* a8 */
7338 { "(bad)", { XX } },
7339 { "(bad)", { XX } },
7340 { "(bad)", { XX } },
7341 { "(bad)", { XX } },
7342 { "(bad)", { XX } },
7343 { "(bad)", { XX } },
7344 { "(bad)", { XX } },
7345 { "(bad)", { XX } },
7346 /* b0 */
7347 { "(bad)", { XX } },
7348 { "(bad)", { XX } },
7349 { "(bad)", { XX } },
7350 { "(bad)", { XX } },
7351 { "(bad)", { XX } },
7352 { "(bad)", { XX } },
7353 { "(bad)", { XX } },
7354 { "(bad)", { XX } },
7355 /* b8 */
7356 { "(bad)", { XX } },
7357 { "(bad)", { XX } },
7358 { "(bad)", { XX } },
7359 { "(bad)", { XX } },
7360 { "(bad)", { XX } },
7361 { "(bad)", { XX } },
7362 { "(bad)", { XX } },
7363 { "(bad)", { XX } },
7364 /* c0 */
7365 { "(bad)", { XX } },
7366 { "(bad)", { XX } },
7367 { "(bad)", { XX } },
7368 { "(bad)", { XX } },
7369 { "(bad)", { XX } },
7370 { "(bad)", { XX } },
7371 { "(bad)", { XX } },
7372 { "(bad)", { XX } },
7373 /* c8 */
7374 { "(bad)", { XX } },
7375 { "(bad)", { XX } },
7376 { "(bad)", { XX } },
7377 { "(bad)", { XX } },
7378 { "(bad)", { XX } },
7379 { "(bad)", { XX } },
7380 { "(bad)", { XX } },
7381 { "(bad)", { XX } },
7382 /* d0 */
7383 { "(bad)", { XX } },
7384 { "(bad)", { XX } },
7385 { "(bad)", { XX } },
7386 { "(bad)", { XX } },
7387 { "(bad)", { XX } },
7388 { "(bad)", { XX } },
7389 { "(bad)", { XX } },
7390 { "(bad)", { XX } },
7391 /* d8 */
7392 { "(bad)", { XX } },
7393 { "(bad)", { XX } },
7394 { "(bad)", { XX } },
7395 { "(bad)", { XX } },
7396 { "(bad)", { XX } },
7397 { "(bad)", { XX } },
7398 { "(bad)", { XX } },
7399 { "(bad)", { XX } },
7400 /* e0 */
7401 { "(bad)", { XX } },
7402 { "(bad)", { XX } },
7403 { "(bad)", { XX } },
7404 { "(bad)", { XX } },
7405 { "(bad)", { XX } },
7406 { "(bad)", { XX } },
7407 { "(bad)", { XX } },
7408 { "(bad)", { XX } },
7409 /* e8 */
7410 { "(bad)", { XX } },
7411 { "(bad)", { XX } },
7412 { "(bad)", { XX } },
7413 { "(bad)", { XX } },
7414 { "(bad)", { XX } },
7415 { "(bad)", { XX } },
7416 { "(bad)", { XX } },
7417 { "(bad)", { XX } },
7418 /* f0 */
7419 { "(bad)", { XX } },
7420 { "(bad)", { XX } },
7421 { "(bad)", { XX } },
7422 { "(bad)", { XX } },
7423 { "(bad)", { XX } },
7424 { "(bad)", { XX } },
7425 { "(bad)", { XX } },
7426 { "(bad)", { XX } },
7427 /* f8 */
7428 { "(bad)", { XX } },
7429 { "(bad)", { XX } },
7430 { "(bad)", { XX } },
7431 { "(bad)", { XX } },
7432 { "(bad)", { XX } },
7433 { "(bad)", { XX } },
7434 { "(bad)", { XX } },
7435 { "(bad)", { XX } },
7436 },
7437 /* VEX_0F3A */
7438 {
7439 /* 00 */
7440 { "(bad)", { XX } },
7441 { "(bad)", { XX } },
7442 { "(bad)", { XX } },
7443 { "(bad)", { XX } },
7444 { PREFIX_TABLE (PREFIX_VEX_3A04) },
7445 { PREFIX_TABLE (PREFIX_VEX_3A05) },
7446 { PREFIX_TABLE (PREFIX_VEX_3A06) },
7447 { "(bad)", { XX } },
7448 /* 08 */
7449 { PREFIX_TABLE (PREFIX_VEX_3A08) },
7450 { PREFIX_TABLE (PREFIX_VEX_3A09) },
7451 { PREFIX_TABLE (PREFIX_VEX_3A0A) },
7452 { PREFIX_TABLE (PREFIX_VEX_3A0B) },
7453 { PREFIX_TABLE (PREFIX_VEX_3A0C) },
7454 { PREFIX_TABLE (PREFIX_VEX_3A0D) },
7455 { PREFIX_TABLE (PREFIX_VEX_3A0E) },
7456 { PREFIX_TABLE (PREFIX_VEX_3A0F) },
7457 /* 10 */
7458 { "(bad)", { XX } },
7459 { "(bad)", { XX } },
7460 { "(bad)", { XX } },
7461 { "(bad)", { XX } },
7462 { PREFIX_TABLE (PREFIX_VEX_3A14) },
7463 { PREFIX_TABLE (PREFIX_VEX_3A15) },
7464 { PREFIX_TABLE (PREFIX_VEX_3A16) },
7465 { PREFIX_TABLE (PREFIX_VEX_3A17) },
7466 /* 18 */
7467 { PREFIX_TABLE (PREFIX_VEX_3A18) },
7468 { PREFIX_TABLE (PREFIX_VEX_3A19) },
7469 { "(bad)", { XX } },
7470 { "(bad)", { XX } },
7471 { "(bad)", { XX } },
7472 { "(bad)", { XX } },
7473 { "(bad)", { XX } },
7474 { "(bad)", { XX } },
7475 /* 20 */
7476 { PREFIX_TABLE (PREFIX_VEX_3A20) },
7477 { PREFIX_TABLE (PREFIX_VEX_3A21) },
7478 { PREFIX_TABLE (PREFIX_VEX_3A22) },
7479 { "(bad)", { XX } },
7480 { "(bad)", { XX } },
7481 { "(bad)", { XX } },
7482 { "(bad)", { XX } },
7483 { "(bad)", { XX } },
7484 /* 28 */
7485 { "(bad)", { XX } },
7486 { "(bad)", { XX } },
7487 { "(bad)", { XX } },
7488 { "(bad)", { XX } },
7489 { "(bad)", { XX } },
7490 { "(bad)", { XX } },
7491 { "(bad)", { XX } },
7492 { "(bad)", { XX } },
7493 /* 30 */
7494 { "(bad)", { XX } },
7495 { "(bad)", { XX } },
7496 { "(bad)", { XX } },
7497 { "(bad)", { XX } },
7498 { "(bad)", { XX } },
7499 { "(bad)", { XX } },
7500 { "(bad)", { XX } },
7501 { "(bad)", { XX } },
7502 /* 38 */
7503 { "(bad)", { XX } },
7504 { "(bad)", { XX } },
7505 { "(bad)", { XX } },
7506 { "(bad)", { XX } },
7507 { "(bad)", { XX } },
7508 { "(bad)", { XX } },
7509 { "(bad)", { XX } },
7510 { "(bad)", { XX } },
7511 /* 40 */
7512 { PREFIX_TABLE (PREFIX_VEX_3A40) },
7513 { PREFIX_TABLE (PREFIX_VEX_3A41) },
7514 { PREFIX_TABLE (PREFIX_VEX_3A42) },
7515 { "(bad)", { XX } },
7516 { "(bad)", { XX } },
7517 { "(bad)", { XX } },
7518 { "(bad)", { XX } },
7519 { "(bad)", { XX } },
7520 /* 48 */
7521 { PREFIX_TABLE (PREFIX_VEX_3A48) },
7522 { PREFIX_TABLE (PREFIX_VEX_3A49) },
7523 { PREFIX_TABLE (PREFIX_VEX_3A4A) },
7524 { PREFIX_TABLE (PREFIX_VEX_3A4B) },
7525 { PREFIX_TABLE (PREFIX_VEX_3A4C) },
7526 { "(bad)", { XX } },
7527 { "(bad)", { XX } },
7528 { "(bad)", { XX } },
7529 /* 50 */
7530 { "(bad)", { XX } },
7531 { "(bad)", { XX } },
7532 { "(bad)", { XX } },
7533 { "(bad)", { XX } },
7534 { "(bad)", { XX } },
7535 { "(bad)", { XX } },
7536 { "(bad)", { XX } },
7537 { "(bad)", { XX } },
7538 /* 58 */
7539 { "(bad)", { XX } },
7540 { "(bad)", { XX } },
7541 { "(bad)", { XX } },
7542 { "(bad)", { XX } },
7543 { PREFIX_TABLE (PREFIX_VEX_3A5C) },
7544 { PREFIX_TABLE (PREFIX_VEX_3A5D) },
7545 { PREFIX_TABLE (PREFIX_VEX_3A5E) },
7546 { PREFIX_TABLE (PREFIX_VEX_3A5F) },
7547 /* 60 */
7548 { PREFIX_TABLE (PREFIX_VEX_3A60) },
7549 { PREFIX_TABLE (PREFIX_VEX_3A61) },
7550 { PREFIX_TABLE (PREFIX_VEX_3A62) },
7551 { PREFIX_TABLE (PREFIX_VEX_3A63) },
7552 { "(bad)", { XX } },
7553 { "(bad)", { XX } },
7554 { "(bad)", { XX } },
7555 { "(bad)", { XX } },
7556 /* 68 */
7557 { PREFIX_TABLE (PREFIX_VEX_3A68) },
7558 { PREFIX_TABLE (PREFIX_VEX_3A69) },
7559 { PREFIX_TABLE (PREFIX_VEX_3A6A) },
7560 { PREFIX_TABLE (PREFIX_VEX_3A6B) },
7561 { PREFIX_TABLE (PREFIX_VEX_3A6C) },
7562 { PREFIX_TABLE (PREFIX_VEX_3A6D) },
7563 { PREFIX_TABLE (PREFIX_VEX_3A6E) },
7564 { PREFIX_TABLE (PREFIX_VEX_3A6F) },
7565 /* 70 */
7566 { "(bad)", { XX } },
7567 { "(bad)", { XX } },
7568 { "(bad)", { XX } },
7569 { "(bad)", { XX } },
7570 { "(bad)", { XX } },
7571 { "(bad)", { XX } },
7572 { "(bad)", { XX } },
7573 { "(bad)", { XX } },
7574 /* 78 */
7575 { PREFIX_TABLE (PREFIX_VEX_3A78) },
7576 { PREFIX_TABLE (PREFIX_VEX_3A79) },
7577 { PREFIX_TABLE (PREFIX_VEX_3A7A) },
7578 { PREFIX_TABLE (PREFIX_VEX_3A7B) },
7579 { PREFIX_TABLE (PREFIX_VEX_3A7C) },
7580 { PREFIX_TABLE (PREFIX_VEX_3A7D) },
7581 { PREFIX_TABLE (PREFIX_VEX_3A7E) },
7582 { PREFIX_TABLE (PREFIX_VEX_3A7F) },
7583 /* 80 */
7584 { "(bad)", { XX } },
7585 { "(bad)", { XX } },
7586 { "(bad)", { XX } },
7587 { "(bad)", { XX } },
7588 { "(bad)", { XX } },
7589 { "(bad)", { XX } },
7590 { "(bad)", { XX } },
7591 { "(bad)", { XX } },
7592 /* 88 */
7593 { "(bad)", { XX } },
7594 { "(bad)", { XX } },
7595 { "(bad)", { XX } },
7596 { "(bad)", { XX } },
7597 { "(bad)", { XX } },
7598 { "(bad)", { XX } },
7599 { "(bad)", { XX } },
7600 { "(bad)", { XX } },
7601 /* 90 */
7602 { "(bad)", { XX } },
7603 { "(bad)", { XX } },
7604 { "(bad)", { XX } },
7605 { "(bad)", { XX } },
7606 { "(bad)", { XX } },
7607 { "(bad)", { XX } },
7608 { "(bad)", { XX } },
7609 { "(bad)", { XX } },
7610 /* 98 */
7611 { "(bad)", { XX } },
7612 { "(bad)", { XX } },
7613 { "(bad)", { XX } },
7614 { "(bad)", { XX } },
7615 { "(bad)", { XX } },
7616 { "(bad)", { XX } },
7617 { "(bad)", { XX } },
7618 { "(bad)", { XX } },
7619 /* a0 */
7620 { "(bad)", { XX } },
7621 { "(bad)", { XX } },
7622 { "(bad)", { XX } },
7623 { "(bad)", { XX } },
7624 { "(bad)", { XX } },
7625 { "(bad)", { XX } },
7626 { "(bad)", { XX } },
7627 { "(bad)", { XX } },
7628 /* a8 */
7629 { "(bad)", { XX } },
7630 { "(bad)", { XX } },
7631 { "(bad)", { XX } },
7632 { "(bad)", { XX } },
7633 { "(bad)", { XX } },
7634 { "(bad)", { XX } },
7635 { "(bad)", { XX } },
7636 { "(bad)", { XX } },
7637 /* b0 */
7638 { "(bad)", { XX } },
7639 { "(bad)", { XX } },
7640 { "(bad)", { XX } },
7641 { "(bad)", { XX } },
7642 { "(bad)", { XX } },
7643 { "(bad)", { XX } },
7644 { "(bad)", { XX } },
7645 { "(bad)", { XX } },
7646 /* b8 */
7647 { "(bad)", { XX } },
7648 { "(bad)", { XX } },
7649 { "(bad)", { XX } },
7650 { "(bad)", { XX } },
7651 { "(bad)", { XX } },
7652 { "(bad)", { XX } },
7653 { "(bad)", { XX } },
7654 { "(bad)", { XX } },
7655 /* c0 */
7656 { "(bad)", { XX } },
7657 { "(bad)", { XX } },
7658 { "(bad)", { XX } },
7659 { "(bad)", { XX } },
7660 { "(bad)", { XX } },
7661 { "(bad)", { XX } },
7662 { "(bad)", { XX } },
7663 { "(bad)", { XX } },
7664 /* c8 */
7665 { "(bad)", { XX } },
7666 { "(bad)", { XX } },
7667 { "(bad)", { XX } },
7668 { "(bad)", { XX } },
7669 { "(bad)", { XX } },
7670 { "(bad)", { XX } },
7671 { "(bad)", { XX } },
7672 { "(bad)", { XX } },
7673 /* d0 */
7674 { "(bad)", { XX } },
7675 { "(bad)", { XX } },
7676 { "(bad)", { XX } },
7677 { "(bad)", { XX } },
7678 { "(bad)", { XX } },
7679 { "(bad)", { XX } },
7680 { "(bad)", { XX } },
7681 { "(bad)", { XX } },
7682 /* d8 */
7683 { "(bad)", { XX } },
7684 { "(bad)", { XX } },
7685 { "(bad)", { XX } },
7686 { "(bad)", { XX } },
7687 { "(bad)", { XX } },
7688 { "(bad)", { XX } },
7689 { "(bad)", { XX } },
7690 { "(bad)", { XX } },
7691 /* e0 */
7692 { "(bad)", { XX } },
7693 { "(bad)", { XX } },
7694 { "(bad)", { XX } },
7695 { "(bad)", { XX } },
7696 { "(bad)", { XX } },
7697 { "(bad)", { XX } },
7698 { "(bad)", { XX } },
7699 { "(bad)", { XX } },
7700 /* e8 */
7701 { "(bad)", { XX } },
7702 { "(bad)", { XX } },
7703 { "(bad)", { XX } },
7704 { "(bad)", { XX } },
7705 { "(bad)", { XX } },
7706 { "(bad)", { XX } },
7707 { "(bad)", { XX } },
7708 { "(bad)", { XX } },
7709 /* f0 */
7710 { "(bad)", { XX } },
7711 { "(bad)", { XX } },
7712 { "(bad)", { XX } },
7713 { "(bad)", { XX } },
7714 { "(bad)", { XX } },
7715 { "(bad)", { XX } },
7716 { "(bad)", { XX } },
7717 { "(bad)", { XX } },
7718 /* f8 */
7719 { "(bad)", { XX } },
7720 { "(bad)", { XX } },
7721 { "(bad)", { XX } },
7722 { "(bad)", { XX } },
7723 { "(bad)", { XX } },
7724 { "(bad)", { XX } },
7725 { "(bad)", { XX } },
7726 { "(bad)", { XX } },
7727 },
7728 };
7729
7730 static const struct dis386 vex_len_table[][2] = {
7731 /* VEX_LEN_10_P_1 */
7732 {
7733 { "vmovss", { XMVex, Vex128, EXd } },
7734 { "(bad)", { XX } },
7735 },
7736
7737 /* VEX_LEN_10_P_3 */
7738 {
7739 { "vmovsd", { XMVex, Vex128, EXq } },
7740 { "(bad)", { XX } },
7741 },
7742
7743 /* VEX_LEN_11_P_1 */
7744 {
7745 { "vmovss", { EXdVex, Vex128, XM } },
7746 { "(bad)", { XX } },
7747 },
7748
7749 /* VEX_LEN_11_P_3 */
7750 {
7751 { "vmovsd", { EXqVex, Vex128, XM } },
7752 { "(bad)", { XX } },
7753 },
7754
7755 /* VEX_LEN_12_P_0_M_0 */
7756 {
7757 { "vmovlps", { XM, Vex128, EXq } },
7758 { "(bad)", { XX } },
7759 },
7760
7761 /* VEX_LEN_12_P_0_M_1 */
7762 {
7763 { "vmovhlps", { XM, Vex128, EXq } },
7764 { "(bad)", { XX } },
7765 },
7766
7767 /* VEX_LEN_12_P_2 */
7768 {
7769 { "vmovlpd", { XM, Vex128, EXq } },
7770 { "(bad)", { XX } },
7771 },
7772
7773 /* VEX_LEN_13_M_0 */
7774 {
7775 { "vmovlpX", { EXq, XM } },
7776 { "(bad)", { XX } },
7777 },
7778
7779 /* VEX_LEN_16_P_0_M_0 */
7780 {
7781 { "vmovhps", { XM, Vex128, EXq } },
7782 { "(bad)", { XX } },
7783 },
7784
7785 /* VEX_LEN_16_P_0_M_1 */
7786 {
7787 { "vmovlhps", { XM, Vex128, EXq } },
7788 { "(bad)", { XX } },
7789 },
7790
7791 /* VEX_LEN_16_P_2 */
7792 {
7793 { "vmovhpd", { XM, Vex128, EXq } },
7794 { "(bad)", { XX } },
7795 },
7796
7797 /* VEX_LEN_17_M_0 */
7798 {
7799 { "vmovhpX", { EXq, XM } },
7800 { "(bad)", { XX } },
7801 },
7802
7803 /* VEX_LEN_2A_P_1 */
7804 {
7805 { "vcvtsi2ss%LQ", { XM, Vex128, Ev } },
7806 { "(bad)", { XX } },
7807 },
7808
7809 /* VEX_LEN_2A_P_3 */
7810 {
7811 { "vcvtsi2sd%LQ", { XM, Vex128, Ev } },
7812 { "(bad)", { XX } },
7813 },
7814
7815 /* VEX_LEN_2B_M_0 */
7816 {
7817 { "vmovntpX", { Mx, XM } },
7818 { "(bad)", { XX } },
7819 },
7820
7821 /* VEX_LEN_2C_P_1 */
7822 {
7823 { "vcvttss2siY", { Gv, EXd } },
7824 { "(bad)", { XX } },
7825 },
7826
7827 /* VEX_LEN_2C_P_3 */
7828 {
7829 { "vcvttsd2siY", { Gv, EXq } },
7830 { "(bad)", { XX } },
7831 },
7832
7833 /* VEX_LEN_2D_P_1 */
7834 {
7835 { "vcvtss2siY", { Gv, EXd } },
7836 { "(bad)", { XX } },
7837 },
7838
7839 /* VEX_LEN_2D_P_3 */
7840 {
7841 { "vcvtsd2siY", { Gv, EXq } },
7842 { "(bad)", { XX } },
7843 },
7844
7845 /* VEX_LEN_2E_P_0 */
7846 {
7847 { "vucomiss", { XM, EXd } },
7848 { "(bad)", { XX } },
7849 },
7850
7851 /* VEX_LEN_2E_P_2 */
7852 {
7853 { "vucomisd", { XM, EXq } },
7854 { "(bad)", { XX } },
7855 },
7856
7857 /* VEX_LEN_2F_P_0 */
7858 {
7859 { "vcomiss", { XM, EXd } },
7860 { "(bad)", { XX } },
7861 },
7862
7863 /* VEX_LEN_2F_P_2 */
7864 {
7865 { "vcomisd", { XM, EXq } },
7866 { "(bad)", { XX } },
7867 },
7868
7869 /* VEX_LEN_51_P_1 */
7870 {
7871 { "vsqrtss", { XM, Vex128, EXd } },
7872 { "(bad)", { XX } },
7873 },
7874
7875 /* VEX_LEN_51_P_3 */
7876 {
7877 { "vsqrtsd", { XM, Vex128, EXq } },
7878 { "(bad)", { XX } },
7879 },
7880
7881 /* VEX_LEN_52_P_1 */
7882 {
7883 { "vrsqrtss", { XM, Vex128, EXd } },
7884 { "(bad)", { XX } },
7885 },
7886
7887 /* VEX_LEN_53_P_1 */
7888 {
7889 { "vrcpss", { XM, Vex128, EXd } },
7890 { "(bad)", { XX } },
7891 },
7892
7893 /* VEX_LEN_58_P_1 */
7894 {
7895 { "vaddss", { XM, Vex128, EXd } },
7896 { "(bad)", { XX } },
7897 },
7898
7899 /* VEX_LEN_58_P_3 */
7900 {
7901 { "vaddsd", { XM, Vex128, EXq } },
7902 { "(bad)", { XX } },
7903 },
7904
7905 /* VEX_LEN_59_P_1 */
7906 {
7907 { "vmulss", { XM, Vex128, EXd } },
7908 { "(bad)", { XX } },
7909 },
7910
7911 /* VEX_LEN_59_P_3 */
7912 {
7913 { "vmulsd", { XM, Vex128, EXq } },
7914 { "(bad)", { XX } },
7915 },
7916
7917 /* VEX_LEN_5A_P_1 */
7918 {
7919 { "vcvtss2sd", { XM, Vex128, EXd } },
7920 { "(bad)", { XX } },
7921 },
7922
7923 /* VEX_LEN_5A_P_3 */
7924 {
7925 { "vcvtsd2ss", { XM, Vex128, EXq } },
7926 { "(bad)", { XX } },
7927 },
7928
7929 /* VEX_LEN_5C_P_1 */
7930 {
7931 { "vsubss", { XM, Vex128, EXd } },
7932 { "(bad)", { XX } },
7933 },
7934
7935 /* VEX_LEN_5C_P_3 */
7936 {
7937 { "vsubsd", { XM, Vex128, EXq } },
7938 { "(bad)", { XX } },
7939 },
7940
7941 /* VEX_LEN_5D_P_1 */
7942 {
7943 { "vminss", { XM, Vex128, EXd } },
7944 { "(bad)", { XX } },
7945 },
7946
7947 /* VEX_LEN_5D_P_3 */
7948 {
7949 { "vminsd", { XM, Vex128, EXq } },
7950 { "(bad)", { XX } },
7951 },
7952
7953 /* VEX_LEN_5E_P_1 */
7954 {
7955 { "vdivss", { XM, Vex128, EXd } },
7956 { "(bad)", { XX } },
7957 },
7958
7959 /* VEX_LEN_5E_P_3 */
7960 {
7961 { "vdivsd", { XM, Vex128, EXq } },
7962 { "(bad)", { XX } },
7963 },
7964
7965 /* VEX_LEN_5F_P_1 */
7966 {
7967 { "vmaxss", { XM, Vex128, EXd } },
7968 { "(bad)", { XX } },
7969 },
7970
7971 /* VEX_LEN_5F_P_3 */
7972 {
7973 { "vmaxsd", { XM, Vex128, EXq } },
7974 { "(bad)", { XX } },
7975 },
7976
7977 /* VEX_LEN_60_P_2 */
7978 {
7979 { "vpunpcklbw", { XM, Vex128, EXx } },
7980 { "(bad)", { XX } },
7981 },
7982
7983 /* VEX_LEN_61_P_2 */
7984 {
7985 { "vpunpcklwd", { XM, Vex128, EXx } },
7986 { "(bad)", { XX } },
7987 },
7988
7989 /* VEX_LEN_62_P_2 */
7990 {
7991 { "vpunpckldq", { XM, Vex128, EXx } },
7992 { "(bad)", { XX } },
7993 },
7994
7995 /* VEX_LEN_63_P_2 */
7996 {
7997 { "vpacksswb", { XM, Vex128, EXx } },
7998 { "(bad)", { XX } },
7999 },
8000
8001 /* VEX_LEN_64_P_2 */
8002 {
8003 { "vpcmpgtb", { XM, Vex128, EXx } },
8004 { "(bad)", { XX } },
8005 },
8006
8007 /* VEX_LEN_65_P_2 */
8008 {
8009 { "vpcmpgtw", { XM, Vex128, EXx } },
8010 { "(bad)", { XX } },
8011 },
8012
8013 /* VEX_LEN_66_P_2 */
8014 {
8015 { "vpcmpgtd", { XM, Vex128, EXx } },
8016 { "(bad)", { XX } },
8017 },
8018
8019 /* VEX_LEN_67_P_2 */
8020 {
8021 { "vpackuswb", { XM, Vex128, EXx } },
8022 { "(bad)", { XX } },
8023 },
8024
8025 /* VEX_LEN_68_P_2 */
8026 {
8027 { "vpunpckhbw", { XM, Vex128, EXx } },
8028 { "(bad)", { XX } },
8029 },
8030
8031 /* VEX_LEN_69_P_2 */
8032 {
8033 { "vpunpckhwd", { XM, Vex128, EXx } },
8034 { "(bad)", { XX } },
8035 },
8036
8037 /* VEX_LEN_6A_P_2 */
8038 {
8039 { "vpunpckhdq", { XM, Vex128, EXx } },
8040 { "(bad)", { XX } },
8041 },
8042
8043 /* VEX_LEN_6B_P_2 */
8044 {
8045 { "vpackssdw", { XM, Vex128, EXx } },
8046 { "(bad)", { XX } },
8047 },
8048
8049 /* VEX_LEN_6C_P_2 */
8050 {
8051 { "vpunpcklqdq", { XM, Vex128, EXx } },
8052 { "(bad)", { XX } },
8053 },
8054
8055 /* VEX_LEN_6D_P_2 */
8056 {
8057 { "vpunpckhqdq", { XM, Vex128, EXx } },
8058 { "(bad)", { XX } },
8059 },
8060
8061 /* VEX_LEN_6E_P_2 */
8062 {
8063 { "vmovK", { XM, Edq } },
8064 { "(bad)", { XX } },
8065 },
8066
8067 /* VEX_LEN_70_P_1 */
8068 {
8069 { "vpshufhw", { XM, EXx, Ib } },
8070 { "(bad)", { XX } },
8071 },
8072
8073 /* VEX_LEN_70_P_2 */
8074 {
8075 { "vpshufd", { XM, EXx, Ib } },
8076 { "(bad)", { XX } },
8077 },
8078
8079 /* VEX_LEN_70_P_3 */
8080 {
8081 { "vpshuflw", { XM, EXx, Ib } },
8082 { "(bad)", { XX } },
8083 },
8084
8085 /* VEX_LEN_71_R_2_P_2 */
8086 {
8087 { "vpsrlw", { Vex128, XS, Ib } },
8088 { "(bad)", { XX } },
8089 },
8090
8091 /* VEX_LEN_71_R_4_P_2 */
8092 {
8093 { "vpsraw", { Vex128, XS, Ib } },
8094 { "(bad)", { XX } },
8095 },
8096
8097 /* VEX_LEN_71_R_6_P_2 */
8098 {
8099 { "vpsllw", { Vex128, XS, Ib } },
8100 { "(bad)", { XX } },
8101 },
8102
8103 /* VEX_LEN_72_R_2_P_2 */
8104 {
8105 { "vpsrld", { Vex128, XS, Ib } },
8106 { "(bad)", { XX } },
8107 },
8108
8109 /* VEX_LEN_72_R_4_P_2 */
8110 {
8111 { "vpsrad", { Vex128, XS, Ib } },
8112 { "(bad)", { XX } },
8113 },
8114
8115 /* VEX_LEN_72_R_6_P_2 */
8116 {
8117 { "vpslld", { Vex128, XS, Ib } },
8118 { "(bad)", { XX } },
8119 },
8120
8121 /* VEX_LEN_73_R_2_P_2 */
8122 {
8123 { "vpsrlq", { Vex128, XS, Ib } },
8124 { "(bad)", { XX } },
8125 },
8126
8127 /* VEX_LEN_73_R_3_P_2 */
8128 {
8129 { "vpsrldq", { Vex128, XS, Ib } },
8130 { "(bad)", { XX } },
8131 },
8132
8133 /* VEX_LEN_73_R_6_P_2 */
8134 {
8135 { "vpsllq", { Vex128, XS, Ib } },
8136 { "(bad)", { XX } },
8137 },
8138
8139 /* VEX_LEN_73_R_7_P_2 */
8140 {
8141 { "vpslldq", { Vex128, XS, Ib } },
8142 { "(bad)", { XX } },
8143 },
8144
8145 /* VEX_LEN_74_P_2 */
8146 {
8147 { "vpcmpeqb", { XM, Vex128, EXx } },
8148 { "(bad)", { XX } },
8149 },
8150
8151 /* VEX_LEN_75_P_2 */
8152 {
8153 { "vpcmpeqw", { XM, Vex128, EXx } },
8154 { "(bad)", { XX } },
8155 },
8156
8157 /* VEX_LEN_76_P_2 */
8158 {
8159 { "vpcmpeqd", { XM, Vex128, EXx } },
8160 { "(bad)", { XX } },
8161 },
8162
8163 /* VEX_LEN_7E_P_1 */
8164 {
8165 { "vmovq", { XM, EXq } },
8166 { "(bad)", { XX } },
8167 },
8168
8169 /* VEX_LEN_7E_P_2 */
8170 {
8171 { "vmovK", { Edq, XM } },
8172 { "(bad)", { XX } },
8173 },
8174
8175 /* VEX_LEN_AE_R_2_M0 */
8176 {
8177 { "vldmxcsr", { Md } },
8178 { "(bad)", { XX } },
8179 },
8180
8181 /* VEX_LEN_AE_R_3_M0 */
8182 {
8183 { "vstmxcsr", { Md } },
8184 { "(bad)", { XX } },
8185 },
8186
8187 /* VEX_LEN_C2_P_1 */
8188 {
8189 { "vcmpss", { XM, Vex128, EXd, VCMP } },
8190 { "(bad)", { XX } },
8191 },
8192
8193 /* VEX_LEN_C2_P_3 */
8194 {
8195 { "vcmpsd", { XM, Vex128, EXq, VCMP } },
8196 { "(bad)", { XX } },
8197 },
8198
8199 /* VEX_LEN_C4_P_2 */
8200 {
8201 { "vpinsrw", { XM, Vex128, Edqw, Ib } },
8202 { "(bad)", { XX } },
8203 },
8204
8205 /* VEX_LEN_C5_P_2 */
8206 {
8207 { "vpextrw", { Gdq, XS, Ib } },
8208 { "(bad)", { XX } },
8209 },
8210
8211 /* VEX_LEN_D1_P_2 */
8212 {
8213 { "vpsrlw", { XM, Vex128, EXx } },
8214 { "(bad)", { XX } },
8215 },
8216
8217 /* VEX_LEN_D2_P_2 */
8218 {
8219 { "vpsrld", { XM, Vex128, EXx } },
8220 { "(bad)", { XX } },
8221 },
8222
8223 /* VEX_LEN_D3_P_2 */
8224 {
8225 { "vpsrlq", { XM, Vex128, EXx } },
8226 { "(bad)", { XX } },
8227 },
8228
8229 /* VEX_LEN_D4_P_2 */
8230 {
8231 { "vpaddq", { XM, Vex128, EXx } },
8232 { "(bad)", { XX } },
8233 },
8234
8235 /* VEX_LEN_D5_P_2 */
8236 {
8237 { "vpmullw", { XM, Vex128, EXx } },
8238 { "(bad)", { XX } },
8239 },
8240
8241 /* VEX_LEN_D6_P_2 */
8242 {
8243 { "vmovq", { EXq, XM } },
8244 { "(bad)", { XX } },
8245 },
8246
8247 /* VEX_LEN_D7_P_2_M_1 */
8248 {
8249 { "vpmovmskb", { Gdq, XS } },
8250 { "(bad)", { XX } },
8251 },
8252
8253 /* VEX_LEN_D8_P_2 */
8254 {
8255 { "vpsubusb", { XM, Vex128, EXx } },
8256 { "(bad)", { XX } },
8257 },
8258
8259 /* VEX_LEN_D9_P_2 */
8260 {
8261 { "vpsubusw", { XM, Vex128, EXx } },
8262 { "(bad)", { XX } },
8263 },
8264
8265 /* VEX_LEN_DA_P_2 */
8266 {
8267 { "vpminub", { XM, Vex128, EXx } },
8268 { "(bad)", { XX } },
8269 },
8270
8271 /* VEX_LEN_DB_P_2 */
8272 {
8273 { "vpand", { XM, Vex128, EXx } },
8274 { "(bad)", { XX } },
8275 },
8276
8277 /* VEX_LEN_DC_P_2 */
8278 {
8279 { "vpaddusb", { XM, Vex128, EXx } },
8280 { "(bad)", { XX } },
8281 },
8282
8283 /* VEX_LEN_DD_P_2 */
8284 {
8285 { "vpaddusw", { XM, Vex128, EXx } },
8286 { "(bad)", { XX } },
8287 },
8288
8289 /* VEX_LEN_DE_P_2 */
8290 {
8291 { "vpmaxub", { XM, Vex128, EXx } },
8292 { "(bad)", { XX } },
8293 },
8294
8295 /* VEX_LEN_DF_P_2 */
8296 {
8297 { "vpandn", { XM, Vex128, EXx } },
8298 { "(bad)", { XX } },
8299 },
8300
8301 /* VEX_LEN_E0_P_2 */
8302 {
8303 { "vpavgb", { XM, Vex128, EXx } },
8304 { "(bad)", { XX } },
8305 },
8306
8307 /* VEX_LEN_E1_P_2 */
8308 {
8309 { "vpsraw", { XM, Vex128, EXx } },
8310 { "(bad)", { XX } },
8311 },
8312
8313 /* VEX_LEN_E2_P_2 */
8314 {
8315 { "vpsrad", { XM, Vex128, EXx } },
8316 { "(bad)", { XX } },
8317 },
8318
8319 /* VEX_LEN_E3_P_2 */
8320 {
8321 { "vpavgw", { XM, Vex128, EXx } },
8322 { "(bad)", { XX } },
8323 },
8324
8325 /* VEX_LEN_E4_P_2 */
8326 {
8327 { "vpmulhuw", { XM, Vex128, EXx } },
8328 { "(bad)", { XX } },
8329 },
8330
8331 /* VEX_LEN_E5_P_2 */
8332 {
8333 { "vpmulhw", { XM, Vex128, EXx } },
8334 { "(bad)", { XX } },
8335 },
8336
8337 /* VEX_LEN_E7_P_2_M_0 */
8338 {
8339 { "vmovntdq", { Mx, XM } },
8340 { "(bad)", { XX } },
8341 },
8342
8343 /* VEX_LEN_E8_P_2 */
8344 {
8345 { "vpsubsb", { XM, Vex128, EXx } },
8346 { "(bad)", { XX } },
8347 },
8348
8349 /* VEX_LEN_E9_P_2 */
8350 {
8351 { "vpsubsw", { XM, Vex128, EXx } },
8352 { "(bad)", { XX } },
8353 },
8354
8355 /* VEX_LEN_EA_P_2 */
8356 {
8357 { "vpminsw", { XM, Vex128, EXx } },
8358 { "(bad)", { XX } },
8359 },
8360
8361 /* VEX_LEN_EB_P_2 */
8362 {
8363 { "vpor", { XM, Vex128, EXx } },
8364 { "(bad)", { XX } },
8365 },
8366
8367 /* VEX_LEN_EC_P_2 */
8368 {
8369 { "vpaddsb", { XM, Vex128, EXx } },
8370 { "(bad)", { XX } },
8371 },
8372
8373 /* VEX_LEN_ED_P_2 */
8374 {
8375 { "vpaddsw", { XM, Vex128, EXx } },
8376 { "(bad)", { XX } },
8377 },
8378
8379 /* VEX_LEN_EE_P_2 */
8380 {
8381 { "vpmaxsw", { XM, Vex128, EXx } },
8382 { "(bad)", { XX } },
8383 },
8384
8385 /* VEX_LEN_EF_P_2 */
8386 {
8387 { "vpxor", { XM, Vex128, EXx } },
8388 { "(bad)", { XX } },
8389 },
8390
8391 /* VEX_LEN_F1_P_2 */
8392 {
8393 { "vpsllw", { XM, Vex128, EXx } },
8394 { "(bad)", { XX } },
8395 },
8396
8397 /* VEX_LEN_F2_P_2 */
8398 {
8399 { "vpslld", { XM, Vex128, EXx } },
8400 { "(bad)", { XX } },
8401 },
8402
8403 /* VEX_LEN_F3_P_2 */
8404 {
8405 { "vpsllq", { XM, Vex128, EXx } },
8406 { "(bad)", { XX } },
8407 },
8408
8409 /* VEX_LEN_F4_P_2 */
8410 {
8411 { "vpmuludq", { XM, Vex128, EXx } },
8412 { "(bad)", { XX } },
8413 },
8414
8415 /* VEX_LEN_F5_P_2 */
8416 {
8417 { "vpmaddwd", { XM, Vex128, EXx } },
8418 { "(bad)", { XX } },
8419 },
8420
8421 /* VEX_LEN_F6_P_2 */
8422 {
8423 { "vpsadbw", { XM, Vex128, EXx } },
8424 { "(bad)", { XX } },
8425 },
8426
8427 /* VEX_LEN_F7_P_2 */
8428 {
8429 { "vmaskmovdqu", { XM, XS } },
8430 { "(bad)", { XX } },
8431 },
8432
8433 /* VEX_LEN_F8_P_2 */
8434 {
8435 { "vpsubb", { XM, Vex128, EXx } },
8436 { "(bad)", { XX } },
8437 },
8438
8439 /* VEX_LEN_F9_P_2 */
8440 {
8441 { "vpsubw", { XM, Vex128, EXx } },
8442 { "(bad)", { XX } },
8443 },
8444
8445 /* VEX_LEN_FA_P_2 */
8446 {
8447 { "vpsubd", { XM, Vex128, EXx } },
8448 { "(bad)", { XX } },
8449 },
8450
8451 /* VEX_LEN_FB_P_2 */
8452 {
8453 { "vpsubq", { XM, Vex128, EXx } },
8454 { "(bad)", { XX } },
8455 },
8456
8457 /* VEX_LEN_FC_P_2 */
8458 {
8459 { "vpaddb", { XM, Vex128, EXx } },
8460 { "(bad)", { XX } },
8461 },
8462
8463 /* VEX_LEN_FD_P_2 */
8464 {
8465 { "vpaddw", { XM, Vex128, EXx } },
8466 { "(bad)", { XX } },
8467 },
8468
8469 /* VEX_LEN_FE_P_2 */
8470 {
8471 { "vpaddd", { XM, Vex128, EXx } },
8472 { "(bad)", { XX } },
8473 },
8474
8475 /* VEX_LEN_3800_P_2 */
8476 {
8477 { "vpshufb", { XM, Vex128, EXx } },
8478 { "(bad)", { XX } },
8479 },
8480
8481 /* VEX_LEN_3801_P_2 */
8482 {
8483 { "vphaddw", { XM, Vex128, EXx } },
8484 { "(bad)", { XX } },
8485 },
8486
8487 /* VEX_LEN_3802_P_2 */
8488 {
8489 { "vphaddd", { XM, Vex128, EXx } },
8490 { "(bad)", { XX } },
8491 },
8492
8493 /* VEX_LEN_3803_P_2 */
8494 {
8495 { "vphaddsw", { XM, Vex128, EXx } },
8496 { "(bad)", { XX } },
8497 },
8498
8499 /* VEX_LEN_3804_P_2 */
8500 {
8501 { "vpmaddubsw", { XM, Vex128, EXx } },
8502 { "(bad)", { XX } },
8503 },
8504
8505 /* VEX_LEN_3805_P_2 */
8506 {
8507 { "vphsubw", { XM, Vex128, EXx } },
8508 { "(bad)", { XX } },
8509 },
8510
8511 /* VEX_LEN_3806_P_2 */
8512 {
8513 { "vphsubd", { XM, Vex128, EXx } },
8514 { "(bad)", { XX } },
8515 },
8516
8517 /* VEX_LEN_3807_P_2 */
8518 {
8519 { "vphsubsw", { XM, Vex128, EXx } },
8520 { "(bad)", { XX } },
8521 },
8522
8523 /* VEX_LEN_3808_P_2 */
8524 {
8525 { "vpsignb", { XM, Vex128, EXx } },
8526 { "(bad)", { XX } },
8527 },
8528
8529 /* VEX_LEN_3809_P_2 */
8530 {
8531 { "vpsignw", { XM, Vex128, EXx } },
8532 { "(bad)", { XX } },
8533 },
8534
8535 /* VEX_LEN_380A_P_2 */
8536 {
8537 { "vpsignd", { XM, Vex128, EXx } },
8538 { "(bad)", { XX } },
8539 },
8540
8541 /* VEX_LEN_380B_P_2 */
8542 {
8543 { "vpmulhrsw", { XM, Vex128, EXx } },
8544 { "(bad)", { XX } },
8545 },
8546
8547 /* VEX_LEN_3819_P_2_M_0 */
8548 {
8549 { "(bad)", { XX } },
8550 { "vbroadcastsd", { XM, Mq } },
8551 },
8552
8553 /* VEX_LEN_381A_P_2_M_0 */
8554 {
8555 { "(bad)", { XX } },
8556 { "vbroadcastf128", { XM, Mxmm } },
8557 },
8558
8559 /* VEX_LEN_381C_P_2 */
8560 {
8561 { "vpabsb", { XM, EXx } },
8562 { "(bad)", { XX } },
8563 },
8564
8565 /* VEX_LEN_381D_P_2 */
8566 {
8567 { "vpabsw", { XM, EXx } },
8568 { "(bad)", { XX } },
8569 },
8570
8571 /* VEX_LEN_381E_P_2 */
8572 {
8573 { "vpabsd", { XM, EXx } },
8574 { "(bad)", { XX } },
8575 },
8576
8577 /* VEX_LEN_3820_P_2 */
8578 {
8579 { "vpmovsxbw", { XM, EXq } },
8580 { "(bad)", { XX } },
8581 },
8582
8583 /* VEX_LEN_3821_P_2 */
8584 {
8585 { "vpmovsxbd", { XM, EXd } },
8586 { "(bad)", { XX } },
8587 },
8588
8589 /* VEX_LEN_3822_P_2 */
8590 {
8591 { "vpmovsxbq", { XM, EXw } },
8592 { "(bad)", { XX } },
8593 },
8594
8595 /* VEX_LEN_3823_P_2 */
8596 {
8597 { "vpmovsxwd", { XM, EXq } },
8598 { "(bad)", { XX } },
8599 },
8600
8601 /* VEX_LEN_3824_P_2 */
8602 {
8603 { "vpmovsxwq", { XM, EXd } },
8604 { "(bad)", { XX } },
8605 },
8606
8607 /* VEX_LEN_3825_P_2 */
8608 {
8609 { "vpmovsxdq", { XM, EXq } },
8610 { "(bad)", { XX } },
8611 },
8612
8613 /* VEX_LEN_3828_P_2 */
8614 {
8615 { "vpmuldq", { XM, Vex128, EXx } },
8616 { "(bad)", { XX } },
8617 },
8618
8619 /* VEX_LEN_3829_P_2 */
8620 {
8621 { "vpcmpeqq", { XM, Vex128, EXx } },
8622 { "(bad)", { XX } },
8623 },
8624
8625 /* VEX_LEN_382A_P_2_M_0 */
8626 {
8627 { "vmovntdqa", { XM, Mx } },
8628 { "(bad)", { XX } },
8629 },
8630
8631 /* VEX_LEN_382B_P_2 */
8632 {
8633 { "vpackusdw", { XM, Vex128, EXx } },
8634 { "(bad)", { XX } },
8635 },
8636
8637 /* VEX_LEN_3830_P_2 */
8638 {
8639 { "vpmovzxbw", { XM, EXq } },
8640 { "(bad)", { XX } },
8641 },
8642
8643 /* VEX_LEN_3831_P_2 */
8644 {
8645 { "vpmovzxbd", { XM, EXd } },
8646 { "(bad)", { XX } },
8647 },
8648
8649 /* VEX_LEN_3832_P_2 */
8650 {
8651 { "vpmovzxbq", { XM, EXw } },
8652 { "(bad)", { XX } },
8653 },
8654
8655 /* VEX_LEN_3833_P_2 */
8656 {
8657 { "vpmovzxwd", { XM, EXq } },
8658 { "(bad)", { XX } },
8659 },
8660
8661 /* VEX_LEN_3834_P_2 */
8662 {
8663 { "vpmovzxwq", { XM, EXd } },
8664 { "(bad)", { XX } },
8665 },
8666
8667 /* VEX_LEN_3835_P_2 */
8668 {
8669 { "vpmovzxdq", { XM, EXq } },
8670 { "(bad)", { XX } },
8671 },
8672
8673 /* VEX_LEN_3837_P_2 */
8674 {
8675 { "vpcmpgtq", { XM, Vex128, EXx } },
8676 { "(bad)", { XX } },
8677 },
8678
8679 /* VEX_LEN_3838_P_2 */
8680 {
8681 { "vpminsb", { XM, Vex128, EXx } },
8682 { "(bad)", { XX } },
8683 },
8684
8685 /* VEX_LEN_3839_P_2 */
8686 {
8687 { "vpminsd", { XM, Vex128, EXx } },
8688 { "(bad)", { XX } },
8689 },
8690
8691 /* VEX_LEN_383A_P_2 */
8692 {
8693 { "vpminuw", { XM, Vex128, EXx } },
8694 { "(bad)", { XX } },
8695 },
8696
8697 /* VEX_LEN_383B_P_2 */
8698 {
8699 { "vpminud", { XM, Vex128, EXx } },
8700 { "(bad)", { XX } },
8701 },
8702
8703 /* VEX_LEN_383C_P_2 */
8704 {
8705 { "vpmaxsb", { XM, Vex128, EXx } },
8706 { "(bad)", { XX } },
8707 },
8708
8709 /* VEX_LEN_383D_P_2 */
8710 {
8711 { "vpmaxsd", { XM, Vex128, EXx } },
8712 { "(bad)", { XX } },
8713 },
8714
8715 /* VEX_LEN_383E_P_2 */
8716 {
8717 { "vpmaxuw", { XM, Vex128, EXx } },
8718 { "(bad)", { XX } },
8719 },
8720
8721 /* VEX_LEN_383F_P_2 */
8722 {
8723 { "vpmaxud", { XM, Vex128, EXx } },
8724 { "(bad)", { XX } },
8725 },
8726
8727 /* VEX_LEN_3840_P_2 */
8728 {
8729 { "vpmulld", { XM, Vex128, EXx } },
8730 { "(bad)", { XX } },
8731 },
8732
8733 /* VEX_LEN_3841_P_2 */
8734 {
8735 { "vphminposuw", { XM, EXx } },
8736 { "(bad)", { XX } },
8737 },
8738
8739 /* VEX_LEN_3A06_P_2 */
8740 {
8741 { "(bad)", { XX } },
8742 { "vperm2f128", { XM, Vex256, EXx, Ib } },
8743 },
8744
8745 /* VEX_LEN_3A0A_P_2 */
8746 {
8747 { "vroundss", { XM, Vex128, EXd, Ib } },
8748 { "(bad)", { XX } },
8749 },
8750
8751 /* VEX_LEN_3A0B_P_2 */
8752 {
8753 { "vroundsd", { XM, Vex128, EXq, Ib } },
8754 { "(bad)", { XX } },
8755 },
8756
8757 /* VEX_LEN_3A0E_P_2 */
8758 {
8759 { "vpblendw", { XM, Vex128, EXx, Ib } },
8760 { "(bad)", { XX } },
8761 },
8762
8763 /* VEX_LEN_3A0F_P_2 */
8764 {
8765 { "vpalignr", { XM, Vex128, EXx, Ib } },
8766 { "(bad)", { XX } },
8767 },
8768
8769 /* VEX_LEN_3A14_P_2 */
8770 {
8771 { "vpextrb", { Edqb, XM, Ib } },
8772 { "(bad)", { XX } },
8773 },
8774
8775 /* VEX_LEN_3A15_P_2 */
8776 {
8777 { "vpextrw", { Edqw, XM, Ib } },
8778 { "(bad)", { XX } },
8779 },
8780
8781 /* VEX_LEN_3A16_P_2 */
8782 {
8783 { "vpextrK", { Edq, XM, Ib } },
8784 { "(bad)", { XX } },
8785 },
8786
8787 /* VEX_LEN_3A17_P_2 */
8788 {
8789 { "vextractps", { Edqd, XM, Ib } },
8790 { "(bad)", { XX } },
8791 },
8792
8793 /* VEX_LEN_3A18_P_2 */
8794 {
8795 { "(bad)", { XX } },
8796 { "vinsertf128", { XM, Vex256, EXxmm, Ib } },
8797 },
8798
8799 /* VEX_LEN_3A19_P_2 */
8800 {
8801 { "(bad)", { XX } },
8802 { "vextractf128", { EXxmm, XM, Ib } },
8803 },
8804
8805 /* VEX_LEN_3A20_P_2 */
8806 {
8807 { "vpinsrb", { XM, Vex128, Edqb, Ib } },
8808 { "(bad)", { XX } },
8809 },
8810
8811 /* VEX_LEN_3A21_P_2 */
8812 {
8813 { "vinsertps", { XM, Vex128, EXd, Ib } },
8814 { "(bad)", { XX } },
8815 },
8816
8817 /* VEX_LEN_3A22_P_2 */
8818 {
8819 { "vpinsrK", { XM, Vex128, Edq, Ib } },
8820 { "(bad)", { XX } },
8821 },
8822
8823 /* VEX_LEN_3A41_P_2 */
8824 {
8825 { "vdppd", { XM, Vex128, EXx, Ib } },
8826 { "(bad)", { XX } },
8827 },
8828
8829 /* VEX_LEN_3A42_P_2 */
8830 {
8831 { "vmpsadbw", { XM, Vex128, EXx, Ib } },
8832 { "(bad)", { XX } },
8833 },
8834
8835 /* VEX_LEN_3A4C_P_2 */
8836 {
8837 { "vpblendvb", { XM, Vex128, EXx, XMVexI4 } },
8838 { "(bad)", { XX } },
8839 },
8840
8841 /* VEX_LEN_3A60_P_2 */
8842 {
8843 { "vpcmpestrm", { XM, EXx, Ib } },
8844 { "(bad)", { XX } },
8845 },
8846
8847 /* VEX_LEN_3A61_P_2 */
8848 {
8849 { "vpcmpestri", { XM, EXx, Ib } },
8850 { "(bad)", { XX } },
8851 },
8852
8853 /* VEX_LEN_3A62_P_2 */
8854 {
8855 { "vpcmpistrm", { XM, EXx, Ib } },
8856 { "(bad)", { XX } },
8857 },
8858
8859 /* VEX_LEN_3A63_P_2 */
8860 {
8861 { "vpcmpistri", { XM, EXx, Ib } },
8862 { "(bad)", { XX } },
8863 },
8864
8865 /* VEX_LEN_3A6A_P_2 */
8866 {
8867 { "vfmaddss", { XMVexW, Vex128FMA, EXdVexW, EXdVexW, VexI4 } },
8868 { "(bad)", { XX } },
8869 },
8870
8871 /* VEX_LEN_3A6B_P_2 */
8872 {
8873 { "vfmaddsd", { XMVexW, Vex128FMA, EXqVexW, EXqVexW, VexI4 } },
8874 { "(bad)", { XX } },
8875 },
8876
8877 /* VEX_LEN_3A6E_P_2 */
8878 {
8879 { "vfmsubss", { XMVexW, Vex128FMA, EXdVexW, EXdVexW, VexI4 } },
8880 { "(bad)", { XX } },
8881 },
8882
8883 /* VEX_LEN_3A6F_P_2 */
8884 {
8885 { "vfmsubsd", { XMVexW, Vex128FMA, EXqVexW, EXqVexW, VexI4 } },
8886 { "(bad)", { XX } },
8887 },
8888
8889 /* VEX_LEN_3A7A_P_2 */
8890 {
8891 { "vfnmaddss", { XMVexW, Vex128FMA, EXdVexW, EXdVexW, VexI4 } },
8892 { "(bad)", { XX } },
8893 },
8894
8895 /* VEX_LEN_3A7B_P_2 */
8896 {
8897 { "vfnmaddsd", { XMVexW, Vex128FMA, EXqVexW, EXqVexW, VexI4 } },
8898 { "(bad)", { XX } },
8899 },
8900
8901 /* VEX_LEN_3A7E_P_2 */
8902 {
8903 { "vfnmsubss", { XMVexW, Vex128FMA, EXdVexW, EXdVexW, VexI4 } },
8904 { "(bad)", { XX } },
8905 },
8906
8907 /* VEX_LEN_3A7F_P_2 */
8908 {
8909 { "vfnmsubsd", { XMVexW, Vex128FMA, EXqVexW, EXqVexW, VexI4 } },
8910 { "(bad)", { XX } },
8911 },
8912 };
8913
8914 static const struct dis386 mod_table[][2] = {
8915 {
8916 /* MOD_8D */
8917 { "leaS", { Gv, M } },
8918 { "(bad)", { XX } },
8919 },
8920 {
8921 /* MOD_0F01_REG_0 */
8922 { X86_64_TABLE (X86_64_0F01_REG_0) },
8923 { RM_TABLE (RM_0F01_REG_0) },
8924 },
8925 {
8926 /* MOD_0F01_REG_1 */
8927 { X86_64_TABLE (X86_64_0F01_REG_1) },
8928 { RM_TABLE (RM_0F01_REG_1) },
8929 },
8930 {
8931 /* MOD_0F01_REG_2 */
8932 { X86_64_TABLE (X86_64_0F01_REG_2) },
8933 { RM_TABLE (RM_0F01_REG_2) },
8934 },
8935 {
8936 /* MOD_0F01_REG_3 */
8937 { X86_64_TABLE (X86_64_0F01_REG_3) },
8938 { RM_TABLE (RM_0F01_REG_3) },
8939 },
8940 {
8941 /* MOD_0F01_REG_7 */
8942 { "invlpg", { Mb } },
8943 { RM_TABLE (RM_0F01_REG_7) },
8944 },
8945 {
8946 /* MOD_0F12_PREFIX_0 */
8947 { "movlps", { XM, EXq } },
8948 { "movhlps", { XM, EXq } },
8949 },
8950 {
8951 /* MOD_0F13 */
8952 { "movlpX", { EXq, XM } },
8953 { "(bad)", { XX } },
8954 },
8955 {
8956 /* MOD_0F16_PREFIX_0 */
8957 { "movhps", { XM, EXq } },
8958 { "movlhps", { XM, EXq } },
8959 },
8960 {
8961 /* MOD_0F17 */
8962 { "movhpX", { EXq, XM } },
8963 { "(bad)", { XX } },
8964 },
8965 {
8966 /* MOD_0F18_REG_0 */
8967 { "prefetchnta", { Mb } },
8968 { "(bad)", { XX } },
8969 },
8970 {
8971 /* MOD_0F18_REG_1 */
8972 { "prefetcht0", { Mb } },
8973 { "(bad)", { XX } },
8974 },
8975 {
8976 /* MOD_0F18_REG_2 */
8977 { "prefetcht1", { Mb } },
8978 { "(bad)", { XX } },
8979 },
8980 {
8981 /* MOD_0F18_REG_3 */
8982 { "prefetcht2", { Mb } },
8983 { "(bad)", { XX } },
8984 },
8985 {
8986 /* MOD_0F20 */
8987 { "(bad)", { XX } },
8988 { "movZ", { Rm, Cm } },
8989 },
8990 {
8991 /* MOD_0F21 */
8992 { "(bad)", { XX } },
8993 { "movZ", { Rm, Dm } },
8994 },
8995 {
8996 /* MOD_0F22 */
8997 { "(bad)", { XX } },
8998 { "movZ", { Cm, Rm } },
8999 },
9000 {
9001 /* MOD_0F23 */
9002 { "(bad)", { XX } },
9003 { "movZ", { Dm, Rm } },
9004 },
9005 {
9006 /* MOD_0F24 */
9007 { THREE_BYTE_TABLE (THREE_BYTE_0F24) },
9008 { "movL", { Rd, Td } },
9009 },
9010 {
9011 /* MOD_0F26 */
9012 { "(bad)", { XX } },
9013 { "movL", { Td, Rd } },
9014 },
9015 {
9016 /* MOD_0F2B_PREFIX_0 */
9017 {"movntps", { Mx, XM } },
9018 { "(bad)", { XX } },
9019 },
9020 {
9021 /* MOD_0F2B_PREFIX_1 */
9022 {"movntss", { Md, XM } },
9023 { "(bad)", { XX } },
9024 },
9025 {
9026 /* MOD_0F2B_PREFIX_2 */
9027 {"movntpd", { Mx, XM } },
9028 { "(bad)", { XX } },
9029 },
9030 {
9031 /* MOD_0F2B_PREFIX_3 */
9032 {"movntsd", { Mq, XM } },
9033 { "(bad)", { XX } },
9034 },
9035 {
9036 /* MOD_0F51 */
9037 { "(bad)", { XX } },
9038 { "movmskpX", { Gdq, XS } },
9039 },
9040 {
9041 /* MOD_0F71_REG_2 */
9042 { "(bad)", { XX } },
9043 { "psrlw", { MS, Ib } },
9044 },
9045 {
9046 /* MOD_0F71_REG_4 */
9047 { "(bad)", { XX } },
9048 { "psraw", { MS, Ib } },
9049 },
9050 {
9051 /* MOD_0F71_REG_6 */
9052 { "(bad)", { XX } },
9053 { "psllw", { MS, Ib } },
9054 },
9055 {
9056 /* MOD_0F72_REG_2 */
9057 { "(bad)", { XX } },
9058 { "psrld", { MS, Ib } },
9059 },
9060 {
9061 /* MOD_0F72_REG_4 */
9062 { "(bad)", { XX } },
9063 { "psrad", { MS, Ib } },
9064 },
9065 {
9066 /* MOD_0F72_REG_6 */
9067 { "(bad)", { XX } },
9068 { "pslld", { MS, Ib } },
9069 },
9070 {
9071 /* MOD_0F73_REG_2 */
9072 { "(bad)", { XX } },
9073 { "psrlq", { MS, Ib } },
9074 },
9075 {
9076 /* MOD_0F73_REG_3 */
9077 { "(bad)", { XX } },
9078 { PREFIX_TABLE (PREFIX_0F73_REG_3) },
9079 },
9080 {
9081 /* MOD_0F73_REG_6 */
9082 { "(bad)", { XX } },
9083 { "psllq", { MS, Ib } },
9084 },
9085 {
9086 /* MOD_0F73_REG_7 */
9087 { "(bad)", { XX } },
9088 { PREFIX_TABLE (PREFIX_0F73_REG_7) },
9089 },
9090 {
9091 /* MOD_0FAE_REG_0 */
9092 { "fxsave", { M } },
9093 { "(bad)", { XX } },
9094 },
9095 {
9096 /* MOD_0FAE_REG_1 */
9097 { "fxrstor", { M } },
9098 { "(bad)", { XX } },
9099 },
9100 {
9101 /* MOD_0FAE_REG_2 */
9102 { "ldmxcsr", { Md } },
9103 { "(bad)", { XX } },
9104 },
9105 {
9106 /* MOD_0FAE_REG_3 */
9107 { "stmxcsr", { Md } },
9108 { "(bad)", { XX } },
9109 },
9110 {
9111 /* MOD_0FAE_REG_4 */
9112 { "xsave", { M } },
9113 { "(bad)", { XX } },
9114 },
9115 {
9116 /* MOD_0FAE_REG_5 */
9117 { "xrstor", { M } },
9118 { RM_TABLE (RM_0FAE_REG_5) },
9119 },
9120 {
9121 /* MOD_0FAE_REG_6 */
9122 { "xsaveopt", { M } },
9123 { RM_TABLE (RM_0FAE_REG_6) },
9124 },
9125 {
9126 /* MOD_0FAE_REG_7 */
9127 { "clflush", { Mb } },
9128 { RM_TABLE (RM_0FAE_REG_7) },
9129 },
9130 {
9131 /* MOD_0FB2 */
9132 { "lssS", { Gv, Mp } },
9133 { "(bad)", { XX } },
9134 },
9135 {
9136 /* MOD_0FB4 */
9137 { "lfsS", { Gv, Mp } },
9138 { "(bad)", { XX } },
9139 },
9140 {
9141 /* MOD_0FB5 */
9142 { "lgsS", { Gv, Mp } },
9143 { "(bad)", { XX } },
9144 },
9145 {
9146 /* MOD_0FC7_REG_6 */
9147 { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
9148 { "(bad)", { XX } },
9149 },
9150 {
9151 /* MOD_0FC7_REG_7 */
9152 { "vmptrst", { Mq } },
9153 { "(bad)", { XX } },
9154 },
9155 {
9156 /* MOD_0FD7 */
9157 { "(bad)", { XX } },
9158 { "pmovmskb", { Gdq, MS } },
9159 },
9160 {
9161 /* MOD_0FE7_PREFIX_2 */
9162 { "movntdq", { Mx, XM } },
9163 { "(bad)", { XX } },
9164 },
9165 {
9166 /* MOD_0FF0_PREFIX_3 */
9167 { "lddqu", { XM, M } },
9168 { "(bad)", { XX } },
9169 },
9170 {
9171 /* MOD_0F382A_PREFIX_2 */
9172 { "movntdqa", { XM, Mx } },
9173 { "(bad)", { XX } },
9174 },
9175 {
9176 /* MOD_62_32BIT */
9177 { "bound{S|}", { Gv, Ma } },
9178 { "(bad)", { XX } },
9179 },
9180 {
9181 /* MOD_C4_32BIT */
9182 { "lesS", { Gv, Mp } },
9183 { VEX_C4_TABLE (VEX_0F) },
9184 },
9185 {
9186 /* MOD_C5_32BIT */
9187 { "ldsS", { Gv, Mp } },
9188 { VEX_C5_TABLE (VEX_0F) },
9189 },
9190 {
9191 /* MOD_VEX_12_PREFIX_0 */
9192 { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_0) },
9193 { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_1) },
9194 },
9195 {
9196 /* MOD_VEX_13 */
9197 { VEX_LEN_TABLE (VEX_LEN_13_M_0) },
9198 { "(bad)", { XX } },
9199 },
9200 {
9201 /* MOD_VEX_16_PREFIX_0 */
9202 { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_0) },
9203 { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_1) },
9204 },
9205 {
9206 /* MOD_VEX_17 */
9207 { VEX_LEN_TABLE (VEX_LEN_17_M_0) },
9208 { "(bad)", { XX } },
9209 },
9210 {
9211 /* MOD_VEX_2B */
9212 { VEX_LEN_TABLE (VEX_LEN_2B_M_0) },
9213 { "(bad)", { XX } },
9214 },
9215 {
9216 /* MOD_VEX_51 */
9217 { "(bad)", { XX } },
9218 { "vmovmskpX", { Gdq, XS } },
9219 },
9220 {
9221 /* MOD_VEX_71_REG_2 */
9222 { "(bad)", { XX } },
9223 { PREFIX_TABLE (PREFIX_VEX_71_REG_2) },
9224 },
9225 {
9226 /* MOD_VEX_71_REG_4 */
9227 { "(bad)", { XX } },
9228 { PREFIX_TABLE (PREFIX_VEX_71_REG_4) },
9229 },
9230 {
9231 /* MOD_VEX_71_REG_6 */
9232 { "(bad)", { XX } },
9233 { PREFIX_TABLE (PREFIX_VEX_71_REG_6) },
9234 },
9235 {
9236 /* MOD_VEX_72_REG_2 */
9237 { "(bad)", { XX } },
9238 { PREFIX_TABLE (PREFIX_VEX_72_REG_2) },
9239 },
9240 {
9241 /* MOD_VEX_72_REG_4 */
9242 { "(bad)", { XX } },
9243 { PREFIX_TABLE (PREFIX_VEX_72_REG_4) },
9244 },
9245 {
9246 /* MOD_VEX_72_REG_6 */
9247 { "(bad)", { XX } },
9248 { PREFIX_TABLE (PREFIX_VEX_72_REG_6) },
9249 },
9250 {
9251 /* MOD_VEX_73_REG_2 */
9252 { "(bad)", { XX } },
9253 { PREFIX_TABLE (PREFIX_VEX_73_REG_2) },
9254 },
9255 {
9256 /* MOD_VEX_73_REG_3 */
9257 { "(bad)", { XX } },
9258 { PREFIX_TABLE (PREFIX_VEX_73_REG_3) },
9259 },
9260 {
9261 /* MOD_VEX_73_REG_6 */
9262 { "(bad)", { XX } },
9263 { PREFIX_TABLE (PREFIX_VEX_73_REG_6) },
9264 },
9265 {
9266 /* MOD_VEX_73_REG_7 */
9267 { "(bad)", { XX } },
9268 { PREFIX_TABLE (PREFIX_VEX_73_REG_7) },
9269 },
9270 {
9271 /* MOD_VEX_AE_REG_2 */
9272 { VEX_LEN_TABLE (VEX_LEN_AE_R_2_M_0) },
9273 { "(bad)", { XX } },
9274 },
9275 {
9276 /* MOD_VEX_AE_REG_3 */
9277 { VEX_LEN_TABLE (VEX_LEN_AE_R_3_M_0) },
9278 { "(bad)", { XX } },
9279 },
9280 {
9281 /* MOD_VEX_D7_PREFIX_2 */
9282 { "(bad)", { XX } },
9283 { VEX_LEN_TABLE (VEX_LEN_D7_P_2_M_1) },
9284 },
9285 {
9286 /* MOD_VEX_E7_PREFIX_2 */
9287 { VEX_LEN_TABLE (VEX_LEN_E7_P_2_M_0) },
9288 { "(bad)", { XX } },
9289 },
9290 {
9291 /* MOD_VEX_F0_PREFIX_3 */
9292 { "vlddqu", { XM, M } },
9293 { "(bad)", { XX } },
9294 },
9295 {
9296 /* MOD_VEX_3818_PREFIX_2 */
9297 { "vbroadcastss", { XM, Md } },
9298 { "(bad)", { XX } },
9299 },
9300 {
9301 /* MOD_VEX_3819_PREFIX_2 */
9302 { VEX_LEN_TABLE (VEX_LEN_3819_P_2_M_0) },
9303 { "(bad)", { XX } },
9304 },
9305 {
9306 /* MOD_VEX_381A_PREFIX_2 */
9307 { VEX_LEN_TABLE (VEX_LEN_381A_P_2_M_0) },
9308 { "(bad)", { XX } },
9309 },
9310 {
9311 /* MOD_VEX_382A_PREFIX_2 */
9312 { VEX_LEN_TABLE (VEX_LEN_382A_P_2_M_0) },
9313 { "(bad)", { XX } },
9314 },
9315 {
9316 /* MOD_VEX_382C_PREFIX_2 */
9317 { "vmaskmovps", { XM, Vex, Mx } },
9318 { "(bad)", { XX } },
9319 },
9320 {
9321 /* MOD_VEX_382D_PREFIX_2 */
9322 { "vmaskmovpd", { XM, Vex, Mx } },
9323 { "(bad)", { XX } },
9324 },
9325 {
9326 /* MOD_VEX_382E_PREFIX_2 */
9327 { "vmaskmovps", { Mx, Vex, XM } },
9328 { "(bad)", { XX } },
9329 },
9330 {
9331 /* MOD_VEX_382F_PREFIX_2 */
9332 { "vmaskmovpd", { Mx, Vex, XM } },
9333 { "(bad)", { XX } },
9334 },
9335 };
9336
9337 static const struct dis386 rm_table[][8] = {
9338 {
9339 /* RM_0F01_REG_0 */
9340 { "(bad)", { XX } },
9341 { "vmcall", { Skip_MODRM } },
9342 { "vmlaunch", { Skip_MODRM } },
9343 { "vmresume", { Skip_MODRM } },
9344 { "vmxoff", { Skip_MODRM } },
9345 { "(bad)", { XX } },
9346 { "(bad)", { XX } },
9347 { "(bad)", { XX } },
9348 },
9349 {
9350 /* RM_0F01_REG_1 */
9351 { "monitor", { { OP_Monitor, 0 } } },
9352 { "mwait", { { OP_Mwait, 0 } } },
9353 { "(bad)", { XX } },
9354 { "(bad)", { XX } },
9355 { "(bad)", { XX } },
9356 { "(bad)", { XX } },
9357 { "(bad)", { XX } },
9358 { "(bad)", { XX } },
9359 },
9360 {
9361 /* RM_0F01_REG_2 */
9362 { "xgetbv", { Skip_MODRM } },
9363 { "xsetbv", { Skip_MODRM } },
9364 { "(bad)", { XX } },
9365 { "(bad)", { XX } },
9366 { "(bad)", { XX } },
9367 { "(bad)", { XX } },
9368 { "(bad)", { XX } },
9369 { "(bad)", { XX } },
9370 },
9371 {
9372 /* RM_0F01_REG_3 */
9373 { "vmrun", { Skip_MODRM } },
9374 { "vmmcall", { Skip_MODRM } },
9375 { "vmload", { Skip_MODRM } },
9376 { "vmsave", { Skip_MODRM } },
9377 { "stgi", { Skip_MODRM } },
9378 { "clgi", { Skip_MODRM } },
9379 { "skinit", { Skip_MODRM } },
9380 { "invlpga", { Skip_MODRM } },
9381 },
9382 {
9383 /* RM_0F01_REG_7 */
9384 { "swapgs", { Skip_MODRM } },
9385 { "rdtscp", { Skip_MODRM } },
9386 { "(bad)", { XX } },
9387 { "(bad)", { XX } },
9388 { "(bad)", { XX } },
9389 { "(bad)", { XX } },
9390 { "(bad)", { XX } },
9391 { "(bad)", { XX } },
9392 },
9393 {
9394 /* RM_0FAE_REG_5 */
9395 { "lfence", { Skip_MODRM } },
9396 { "(bad)", { XX } },
9397 { "(bad)", { XX } },
9398 { "(bad)", { XX } },
9399 { "(bad)", { XX } },
9400 { "(bad)", { XX } },
9401 { "(bad)", { XX } },
9402 { "(bad)", { XX } },
9403 },
9404 {
9405 /* RM_0FAE_REG_6 */
9406 { "mfence", { Skip_MODRM } },
9407 { "(bad)", { XX } },
9408 { "(bad)", { XX } },
9409 { "(bad)", { XX } },
9410 { "(bad)", { XX } },
9411 { "(bad)", { XX } },
9412 { "(bad)", { XX } },
9413 { "(bad)", { XX } },
9414 },
9415 {
9416 /* RM_0FAE_REG_7 */
9417 { "sfence", { Skip_MODRM } },
9418 { "(bad)", { XX } },
9419 { "(bad)", { XX } },
9420 { "(bad)", { XX } },
9421 { "(bad)", { XX } },
9422 { "(bad)", { XX } },
9423 { "(bad)", { XX } },
9424 { "(bad)", { XX } },
9425 },
9426 };
9427
9428 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
9429
9430 static void
9431 ckprefix (void)
9432 {
9433 int newrex;
9434 rex = 0;
9435 rex_original = 0;
9436 rex_ignored = 0;
9437 prefixes = 0;
9438 used_prefixes = 0;
9439 rex_used = 0;
9440 while (1)
9441 {
9442 FETCH_DATA (the_info, codep + 1);
9443 newrex = 0;
9444 switch (*codep)
9445 {
9446 /* REX prefixes family. */
9447 case 0x40:
9448 case 0x41:
9449 case 0x42:
9450 case 0x43:
9451 case 0x44:
9452 case 0x45:
9453 case 0x46:
9454 case 0x47:
9455 case 0x48:
9456 case 0x49:
9457 case 0x4a:
9458 case 0x4b:
9459 case 0x4c:
9460 case 0x4d:
9461 case 0x4e:
9462 case 0x4f:
9463 if (address_mode == mode_64bit)
9464 newrex = *codep;
9465 else
9466 return;
9467 break;
9468 case 0xf3:
9469 prefixes |= PREFIX_REPZ;
9470 break;
9471 case 0xf2:
9472 prefixes |= PREFIX_REPNZ;
9473 break;
9474 case 0xf0:
9475 prefixes |= PREFIX_LOCK;
9476 break;
9477 case 0x2e:
9478 prefixes |= PREFIX_CS;
9479 break;
9480 case 0x36:
9481 prefixes |= PREFIX_SS;
9482 break;
9483 case 0x3e:
9484 prefixes |= PREFIX_DS;
9485 break;
9486 case 0x26:
9487 prefixes |= PREFIX_ES;
9488 break;
9489 case 0x64:
9490 prefixes |= PREFIX_FS;
9491 break;
9492 case 0x65:
9493 prefixes |= PREFIX_GS;
9494 break;
9495 case 0x66:
9496 prefixes |= PREFIX_DATA;
9497 break;
9498 case 0x67:
9499 prefixes |= PREFIX_ADDR;
9500 break;
9501 case FWAIT_OPCODE:
9502 /* fwait is really an instruction. If there are prefixes
9503 before the fwait, they belong to the fwait, *not* to the
9504 following instruction. */
9505 if (prefixes || rex)
9506 {
9507 prefixes |= PREFIX_FWAIT;
9508 codep++;
9509 return;
9510 }
9511 prefixes = PREFIX_FWAIT;
9512 break;
9513 default:
9514 return;
9515 }
9516 /* Rex is ignored when followed by another prefix. */
9517 if (rex)
9518 {
9519 rex_used = rex;
9520 return;
9521 }
9522 rex = newrex;
9523 rex_original = rex;
9524 codep++;
9525 }
9526 }
9527
9528 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
9529 prefix byte. */
9530
9531 static const char *
9532 prefix_name (int pref, int sizeflag)
9533 {
9534 static const char *rexes [16] =
9535 {
9536 "rex", /* 0x40 */
9537 "rex.B", /* 0x41 */
9538 "rex.X", /* 0x42 */
9539 "rex.XB", /* 0x43 */
9540 "rex.R", /* 0x44 */
9541 "rex.RB", /* 0x45 */
9542 "rex.RX", /* 0x46 */
9543 "rex.RXB", /* 0x47 */
9544 "rex.W", /* 0x48 */
9545 "rex.WB", /* 0x49 */
9546 "rex.WX", /* 0x4a */
9547 "rex.WXB", /* 0x4b */
9548 "rex.WR", /* 0x4c */
9549 "rex.WRB", /* 0x4d */
9550 "rex.WRX", /* 0x4e */
9551 "rex.WRXB", /* 0x4f */
9552 };
9553
9554 switch (pref)
9555 {
9556 /* REX prefixes family. */
9557 case 0x40:
9558 case 0x41:
9559 case 0x42:
9560 case 0x43:
9561 case 0x44:
9562 case 0x45:
9563 case 0x46:
9564 case 0x47:
9565 case 0x48:
9566 case 0x49:
9567 case 0x4a:
9568 case 0x4b:
9569 case 0x4c:
9570 case 0x4d:
9571 case 0x4e:
9572 case 0x4f:
9573 return rexes [pref - 0x40];
9574 case 0xf3:
9575 return "repz";
9576 case 0xf2:
9577 return "repnz";
9578 case 0xf0:
9579 return "lock";
9580 case 0x2e:
9581 return "cs";
9582 case 0x36:
9583 return "ss";
9584 case 0x3e:
9585 return "ds";
9586 case 0x26:
9587 return "es";
9588 case 0x64:
9589 return "fs";
9590 case 0x65:
9591 return "gs";
9592 case 0x66:
9593 return (sizeflag & DFLAG) ? "data16" : "data32";
9594 case 0x67:
9595 if (address_mode == mode_64bit)
9596 return (sizeflag & AFLAG) ? "addr32" : "addr64";
9597 else
9598 return (sizeflag & AFLAG) ? "addr16" : "addr32";
9599 case FWAIT_OPCODE:
9600 return "fwait";
9601 default:
9602 return NULL;
9603 }
9604 }
9605
9606 static char op_out[MAX_OPERANDS][100];
9607 static int op_ad, op_index[MAX_OPERANDS];
9608 static int two_source_ops;
9609 static bfd_vma op_address[MAX_OPERANDS];
9610 static bfd_vma op_riprel[MAX_OPERANDS];
9611 static bfd_vma start_pc;
9612
9613 /*
9614 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
9615 * (see topic "Redundant prefixes" in the "Differences from 8086"
9616 * section of the "Virtual 8086 Mode" chapter.)
9617 * 'pc' should be the address of this instruction, it will
9618 * be used to print the target address if this is a relative jump or call
9619 * The function returns the length of this instruction in bytes.
9620 */
9621
9622 static char intel_syntax;
9623 static char intel_mnemonic = !SYSV386_COMPAT;
9624 static char open_char;
9625 static char close_char;
9626 static char separator_char;
9627 static char scale_char;
9628
9629 /* Here for backwards compatibility. When gdb stops using
9630 print_insn_i386_att and print_insn_i386_intel these functions can
9631 disappear, and print_insn_i386 be merged into print_insn. */
9632 int
9633 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
9634 {
9635 intel_syntax = 0;
9636
9637 return print_insn (pc, info);
9638 }
9639
9640 int
9641 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
9642 {
9643 intel_syntax = 1;
9644
9645 return print_insn (pc, info);
9646 }
9647
9648 int
9649 print_insn_i386 (bfd_vma pc, disassemble_info *info)
9650 {
9651 intel_syntax = -1;
9652
9653 return print_insn (pc, info);
9654 }
9655
9656 void
9657 print_i386_disassembler_options (FILE *stream)
9658 {
9659 fprintf (stream, _("\n\
9660 The following i386/x86-64 specific disassembler options are supported for use\n\
9661 with the -M switch (multiple options should be separated by commas):\n"));
9662
9663 fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n"));
9664 fprintf (stream, _(" i386 Disassemble in 32bit mode\n"));
9665 fprintf (stream, _(" i8086 Disassemble in 16bit mode\n"));
9666 fprintf (stream, _(" att Display instruction in AT&T syntax\n"));
9667 fprintf (stream, _(" intel Display instruction in Intel syntax\n"));
9668 fprintf (stream, _(" att-mnemonic\n"
9669 " Display instruction in AT&T mnemonic\n"));
9670 fprintf (stream, _(" intel-mnemonic\n"
9671 " Display instruction in Intel mnemonic\n"));
9672 fprintf (stream, _(" addr64 Assume 64bit address size\n"));
9673 fprintf (stream, _(" addr32 Assume 32bit address size\n"));
9674 fprintf (stream, _(" addr16 Assume 16bit address size\n"));
9675 fprintf (stream, _(" data32 Assume 32bit data size\n"));
9676 fprintf (stream, _(" data16 Assume 16bit data size\n"));
9677 fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n"));
9678 }
9679
9680 /* Get a pointer to struct dis386 with a valid name. */
9681
9682 static const struct dis386 *
9683 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
9684 {
9685 int index, vex_table_index;
9686
9687 if (dp->name != NULL)
9688 return dp;
9689
9690 switch (dp->op[0].bytemode)
9691 {
9692 case USE_REG_TABLE:
9693 dp = &reg_table[dp->op[1].bytemode][modrm.reg];
9694 break;
9695
9696 case USE_MOD_TABLE:
9697 index = modrm.mod == 0x3 ? 1 : 0;
9698 dp = &mod_table[dp->op[1].bytemode][index];
9699 break;
9700
9701 case USE_RM_TABLE:
9702 dp = &rm_table[dp->op[1].bytemode][modrm.rm];
9703 break;
9704
9705 case USE_PREFIX_TABLE:
9706 if (need_vex)
9707 {
9708 /* The prefix in VEX is implicit. */
9709 switch (vex.prefix)
9710 {
9711 case 0:
9712 index = 0;
9713 break;
9714 case REPE_PREFIX_OPCODE:
9715 index = 1;
9716 break;
9717 case DATA_PREFIX_OPCODE:
9718 index = 2;
9719 break;
9720 case REPNE_PREFIX_OPCODE:
9721 index = 3;
9722 break;
9723 default:
9724 abort ();
9725 break;
9726 }
9727 }
9728 else
9729 {
9730 index = 0;
9731 used_prefixes |= (prefixes & PREFIX_REPZ);
9732 if (prefixes & PREFIX_REPZ)
9733 {
9734 index = 1;
9735 repz_prefix = NULL;
9736 }
9737 else
9738 {
9739 /* We should check PREFIX_REPNZ and PREFIX_REPZ before
9740 PREFIX_DATA. */
9741 used_prefixes |= (prefixes & PREFIX_REPNZ);
9742 if (prefixes & PREFIX_REPNZ)
9743 {
9744 index = 3;
9745 repnz_prefix = NULL;
9746 }
9747 else
9748 {
9749 used_prefixes |= (prefixes & PREFIX_DATA);
9750 if (prefixes & PREFIX_DATA)
9751 {
9752 index = 2;
9753 data_prefix = NULL;
9754 }
9755 }
9756 }
9757 }
9758 dp = &prefix_table[dp->op[1].bytemode][index];
9759 break;
9760
9761 case USE_X86_64_TABLE:
9762 index = address_mode == mode_64bit ? 1 : 0;
9763 dp = &x86_64_table[dp->op[1].bytemode][index];
9764 break;
9765
9766 case USE_3BYTE_TABLE:
9767 FETCH_DATA (info, codep + 2);
9768 index = *codep++;
9769 dp = &three_byte_table[dp->op[1].bytemode][index];
9770 modrm.mod = (*codep >> 6) & 3;
9771 modrm.reg = (*codep >> 3) & 7;
9772 modrm.rm = *codep & 7;
9773 break;
9774
9775 case USE_VEX_LEN_TABLE:
9776 if (!need_vex)
9777 abort ();
9778
9779 switch (vex.length)
9780 {
9781 case 128:
9782 index = 0;
9783 break;
9784 case 256:
9785 index = 1;
9786 break;
9787 default:
9788 abort ();
9789 break;
9790 }
9791
9792 dp = &vex_len_table[dp->op[1].bytemode][index];
9793 break;
9794
9795 case USE_VEX_C4_TABLE:
9796 FETCH_DATA (info, codep + 3);
9797 /* All bits in the REX prefix are ignored. */
9798 rex_ignored = rex;
9799 rex = ~(*codep >> 5) & 0x7;
9800 switch ((*codep & 0x1f))
9801 {
9802 default:
9803 BadOp ();
9804 case 0x1:
9805 vex_table_index = 0;
9806 break;
9807 case 0x2:
9808 vex_table_index = 1;
9809 break;
9810 case 0x3:
9811 vex_table_index = 2;
9812 break;
9813 }
9814 codep++;
9815 vex.w = *codep & 0x80;
9816 if (vex.w && address_mode == mode_64bit)
9817 rex |= REX_W;
9818
9819 vex.register_specifier = (~(*codep >> 3)) & 0xf;
9820 if (address_mode != mode_64bit
9821 && vex.register_specifier > 0x7)
9822 BadOp ();
9823
9824 vex.length = (*codep & 0x4) ? 256 : 128;
9825 switch ((*codep & 0x3))
9826 {
9827 case 0:
9828 vex.prefix = 0;
9829 break;
9830 case 1:
9831 vex.prefix = DATA_PREFIX_OPCODE;
9832 break;
9833 case 2:
9834 vex.prefix = REPE_PREFIX_OPCODE;
9835 break;
9836 case 3:
9837 vex.prefix = REPNE_PREFIX_OPCODE;
9838 break;
9839 }
9840 need_vex = 1;
9841 need_vex_reg = 1;
9842 codep++;
9843 index = *codep++;
9844 dp = &vex_table[vex_table_index][index];
9845 /* There is no MODRM byte for VEX [82|77]. */
9846 if (index != 0x77 && index != 0x82)
9847 {
9848 FETCH_DATA (info, codep + 1);
9849 modrm.mod = (*codep >> 6) & 3;
9850 modrm.reg = (*codep >> 3) & 7;
9851 modrm.rm = *codep & 7;
9852 }
9853 break;
9854
9855 case USE_VEX_C5_TABLE:
9856 FETCH_DATA (info, codep + 2);
9857 /* All bits in the REX prefix are ignored. */
9858 rex_ignored = rex;
9859 rex = (*codep & 0x80) ? 0 : REX_R;
9860
9861 vex.register_specifier = (~(*codep >> 3)) & 0xf;
9862 if (address_mode != mode_64bit
9863 && vex.register_specifier > 0x7)
9864 BadOp ();
9865
9866 vex.length = (*codep & 0x4) ? 256 : 128;
9867 switch ((*codep & 0x3))
9868 {
9869 case 0:
9870 vex.prefix = 0;
9871 break;
9872 case 1:
9873 vex.prefix = DATA_PREFIX_OPCODE;
9874 break;
9875 case 2:
9876 vex.prefix = REPE_PREFIX_OPCODE;
9877 break;
9878 case 3:
9879 vex.prefix = REPNE_PREFIX_OPCODE;
9880 break;
9881 }
9882 need_vex = 1;
9883 need_vex_reg = 1;
9884 codep++;
9885 index = *codep++;
9886 dp = &vex_table[dp->op[1].bytemode][index];
9887 /* There is no MODRM byte for VEX [82|77]. */
9888 if (index != 0x77 && index != 0x82)
9889 {
9890 FETCH_DATA (info, codep + 1);
9891 modrm.mod = (*codep >> 6) & 3;
9892 modrm.reg = (*codep >> 3) & 7;
9893 modrm.rm = *codep & 7;
9894 }
9895 break;
9896
9897 default:
9898 oappend (INTERNAL_DISASSEMBLER_ERROR);
9899 return NULL;
9900 }
9901
9902 if (dp->name != NULL)
9903 return dp;
9904 else
9905 return get_valid_dis386 (dp, info);
9906 }
9907
9908 static int
9909 print_insn (bfd_vma pc, disassemble_info *info)
9910 {
9911 const struct dis386 *dp;
9912 int i;
9913 char *op_txt[MAX_OPERANDS];
9914 int needcomma;
9915 int sizeflag;
9916 const char *p;
9917 struct dis_private priv;
9918 unsigned char op;
9919 char prefix_obuf[32];
9920 char *prefix_obufp;
9921
9922 if (info->mach == bfd_mach_x86_64_intel_syntax
9923 || info->mach == bfd_mach_x86_64)
9924 address_mode = mode_64bit;
9925 else
9926 address_mode = mode_32bit;
9927
9928 if (intel_syntax == (char) -1)
9929 intel_syntax = (info->mach == bfd_mach_i386_i386_intel_syntax
9930 || info->mach == bfd_mach_x86_64_intel_syntax);
9931
9932 if (info->mach == bfd_mach_i386_i386
9933 || info->mach == bfd_mach_x86_64
9934 || info->mach == bfd_mach_i386_i386_intel_syntax
9935 || info->mach == bfd_mach_x86_64_intel_syntax)
9936 priv.orig_sizeflag = AFLAG | DFLAG;
9937 else if (info->mach == bfd_mach_i386_i8086)
9938 priv.orig_sizeflag = 0;
9939 else
9940 abort ();
9941
9942 for (p = info->disassembler_options; p != NULL; )
9943 {
9944 if (CONST_STRNEQ (p, "x86-64"))
9945 {
9946 address_mode = mode_64bit;
9947 priv.orig_sizeflag = AFLAG | DFLAG;
9948 }
9949 else if (CONST_STRNEQ (p, "i386"))
9950 {
9951 address_mode = mode_32bit;
9952 priv.orig_sizeflag = AFLAG | DFLAG;
9953 }
9954 else if (CONST_STRNEQ (p, "i8086"))
9955 {
9956 address_mode = mode_16bit;
9957 priv.orig_sizeflag = 0;
9958 }
9959 else if (CONST_STRNEQ (p, "intel"))
9960 {
9961 intel_syntax = 1;
9962 if (CONST_STRNEQ (p + 5, "-mnemonic"))
9963 intel_mnemonic = 1;
9964 }
9965 else if (CONST_STRNEQ (p, "att"))
9966 {
9967 intel_syntax = 0;
9968 if (CONST_STRNEQ (p + 3, "-mnemonic"))
9969 intel_mnemonic = 0;
9970 }
9971 else if (CONST_STRNEQ (p, "addr"))
9972 {
9973 if (address_mode == mode_64bit)
9974 {
9975 if (p[4] == '3' && p[5] == '2')
9976 priv.orig_sizeflag &= ~AFLAG;
9977 else if (p[4] == '6' && p[5] == '4')
9978 priv.orig_sizeflag |= AFLAG;
9979 }
9980 else
9981 {
9982 if (p[4] == '1' && p[5] == '6')
9983 priv.orig_sizeflag &= ~AFLAG;
9984 else if (p[4] == '3' && p[5] == '2')
9985 priv.orig_sizeflag |= AFLAG;
9986 }
9987 }
9988 else if (CONST_STRNEQ (p, "data"))
9989 {
9990 if (p[4] == '1' && p[5] == '6')
9991 priv.orig_sizeflag &= ~DFLAG;
9992 else if (p[4] == '3' && p[5] == '2')
9993 priv.orig_sizeflag |= DFLAG;
9994 }
9995 else if (CONST_STRNEQ (p, "suffix"))
9996 priv.orig_sizeflag |= SUFFIX_ALWAYS;
9997
9998 p = strchr (p, ',');
9999 if (p != NULL)
10000 p++;
10001 }
10002
10003 if (intel_syntax)
10004 {
10005 names64 = intel_names64;
10006 names32 = intel_names32;
10007 names16 = intel_names16;
10008 names8 = intel_names8;
10009 names8rex = intel_names8rex;
10010 names_seg = intel_names_seg;
10011 index64 = intel_index64;
10012 index32 = intel_index32;
10013 index16 = intel_index16;
10014 open_char = '[';
10015 close_char = ']';
10016 separator_char = '+';
10017 scale_char = '*';
10018 }
10019 else
10020 {
10021 names64 = att_names64;
10022 names32 = att_names32;
10023 names16 = att_names16;
10024 names8 = att_names8;
10025 names8rex = att_names8rex;
10026 names_seg = att_names_seg;
10027 index64 = att_index64;
10028 index32 = att_index32;
10029 index16 = att_index16;
10030 open_char = '(';
10031 close_char = ')';
10032 separator_char = ',';
10033 scale_char = ',';
10034 }
10035
10036 /* The output looks better if we put 7 bytes on a line, since that
10037 puts most long word instructions on a single line. */
10038 info->bytes_per_line = 7;
10039
10040 info->private_data = &priv;
10041 priv.max_fetched = priv.the_buffer;
10042 priv.insn_start = pc;
10043
10044 obuf[0] = 0;
10045 for (i = 0; i < MAX_OPERANDS; ++i)
10046 {
10047 op_out[i][0] = 0;
10048 op_index[i] = -1;
10049 }
10050
10051 the_info = info;
10052 start_pc = pc;
10053 start_codep = priv.the_buffer;
10054 codep = priv.the_buffer;
10055
10056 if (setjmp (priv.bailout) != 0)
10057 {
10058 const char *name;
10059
10060 /* Getting here means we tried for data but didn't get it. That
10061 means we have an incomplete instruction of some sort. Just
10062 print the first byte as a prefix or a .byte pseudo-op. */
10063 if (codep > priv.the_buffer)
10064 {
10065 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
10066 if (name != NULL)
10067 (*info->fprintf_func) (info->stream, "%s", name);
10068 else
10069 {
10070 /* Just print the first byte as a .byte instruction. */
10071 (*info->fprintf_func) (info->stream, ".byte 0x%x",
10072 (unsigned int) priv.the_buffer[0]);
10073 }
10074
10075 return 1;
10076 }
10077
10078 return -1;
10079 }
10080
10081 obufp = obuf;
10082 ckprefix ();
10083
10084 insn_codep = codep;
10085 sizeflag = priv.orig_sizeflag;
10086
10087 FETCH_DATA (info, codep + 1);
10088 two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
10089
10090 if (((prefixes & PREFIX_FWAIT)
10091 && ((*codep < 0xd8) || (*codep > 0xdf)))
10092 || (rex && rex_used))
10093 {
10094 const char *name;
10095
10096 /* fwait not followed by floating point instruction, or rex followed
10097 by other prefixes. Print the first prefix. */
10098 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
10099 if (name == NULL)
10100 name = INTERNAL_DISASSEMBLER_ERROR;
10101 (*info->fprintf_func) (info->stream, "%s", name);
10102 return 1;
10103 }
10104
10105 op = 0;
10106 if (*codep == 0x0f)
10107 {
10108 unsigned char threebyte;
10109 FETCH_DATA (info, codep + 2);
10110 threebyte = *++codep;
10111 dp = &dis386_twobyte[threebyte];
10112 need_modrm = twobyte_has_modrm[*codep];
10113 codep++;
10114 }
10115 else
10116 {
10117 dp = &dis386[*codep];
10118 need_modrm = onebyte_has_modrm[*codep];
10119 codep++;
10120 }
10121
10122 if ((prefixes & PREFIX_REPZ))
10123 {
10124 repz_prefix = "repz ";
10125 used_prefixes |= PREFIX_REPZ;
10126 }
10127 else
10128 repz_prefix = NULL;
10129
10130 if ((prefixes & PREFIX_REPNZ))
10131 {
10132 repnz_prefix = "repnz ";
10133 used_prefixes |= PREFIX_REPNZ;
10134 }
10135 else
10136 repnz_prefix = NULL;
10137
10138 if ((prefixes & PREFIX_LOCK))
10139 {
10140 lock_prefix = "lock ";
10141 used_prefixes |= PREFIX_LOCK;
10142 }
10143 else
10144 lock_prefix = NULL;
10145
10146 addr_prefix = NULL;
10147 if (prefixes & PREFIX_ADDR)
10148 {
10149 sizeflag ^= AFLAG;
10150 if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax)
10151 {
10152 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
10153 addr_prefix = "addr32 ";
10154 else
10155 addr_prefix = "addr16 ";
10156 used_prefixes |= PREFIX_ADDR;
10157 }
10158 }
10159
10160 data_prefix = NULL;
10161 if ((prefixes & PREFIX_DATA))
10162 {
10163 sizeflag ^= DFLAG;
10164 if (dp->op[2].bytemode == cond_jump_mode
10165 && dp->op[0].bytemode == v_mode
10166 && !intel_syntax)
10167 {
10168 if (sizeflag & DFLAG)
10169 data_prefix = "data32 ";
10170 else
10171 data_prefix = "data16 ";
10172 used_prefixes |= PREFIX_DATA;
10173 }
10174 }
10175
10176 if (need_modrm)
10177 {
10178 FETCH_DATA (info, codep + 1);
10179 modrm.mod = (*codep >> 6) & 3;
10180 modrm.reg = (*codep >> 3) & 7;
10181 modrm.rm = *codep & 7;
10182 }
10183
10184 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
10185 {
10186 dofloat (sizeflag);
10187 }
10188 else
10189 {
10190 need_vex = 0;
10191 need_vex_reg = 0;
10192 vex_w_done = 0;
10193 dp = get_valid_dis386 (dp, info);
10194 if (dp != NULL && putop (dp->name, sizeflag) == 0)
10195 {
10196 for (i = 0; i < MAX_OPERANDS; ++i)
10197 {
10198 obufp = op_out[i];
10199 op_ad = MAX_OPERANDS - 1 - i;
10200 if (dp->op[i].rtn)
10201 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
10202 }
10203 }
10204 }
10205
10206 /* See if any prefixes were not used. If so, print the first one
10207 separately. If we don't do this, we'll wind up printing an
10208 instruction stream which does not precisely correspond to the
10209 bytes we are disassembling. */
10210 if ((prefixes & ~used_prefixes) != 0)
10211 {
10212 const char *name;
10213
10214 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
10215 if (name == NULL)
10216 name = INTERNAL_DISASSEMBLER_ERROR;
10217 (*info->fprintf_func) (info->stream, "%s", name);
10218 return 1;
10219 }
10220 if ((rex_original & ~rex_used) || rex_ignored)
10221 {
10222 const char *name;
10223 name = prefix_name (rex_original, priv.orig_sizeflag);
10224 if (name == NULL)
10225 name = INTERNAL_DISASSEMBLER_ERROR;
10226 (*info->fprintf_func) (info->stream, "%s ", name);
10227 }
10228
10229 prefix_obuf[0] = 0;
10230 prefix_obufp = prefix_obuf;
10231 if (lock_prefix)
10232 prefix_obufp = stpcpy (prefix_obufp, lock_prefix);
10233 if (repz_prefix)
10234 prefix_obufp = stpcpy (prefix_obufp, repz_prefix);
10235 if (repnz_prefix)
10236 prefix_obufp = stpcpy (prefix_obufp, repnz_prefix);
10237 if (addr_prefix)
10238 prefix_obufp = stpcpy (prefix_obufp, addr_prefix);
10239 if (data_prefix)
10240 prefix_obufp = stpcpy (prefix_obufp, data_prefix);
10241
10242 if (prefix_obuf[0] != 0)
10243 (*info->fprintf_func) (info->stream, "%s", prefix_obuf);
10244
10245 obufp = obuf + strlen (obuf);
10246 for (i = strlen (obuf) + strlen (prefix_obuf); i < 6; i++)
10247 oappend (" ");
10248 oappend (" ");
10249 (*info->fprintf_func) (info->stream, "%s", obuf);
10250
10251 /* The enter and bound instructions are printed with operands in the same
10252 order as the intel book; everything else is printed in reverse order. */
10253 if (intel_syntax || two_source_ops)
10254 {
10255 bfd_vma riprel;
10256
10257 for (i = 0; i < MAX_OPERANDS; ++i)
10258 op_txt[i] = op_out[i];
10259
10260 for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
10261 {
10262 op_ad = op_index[i];
10263 op_index[i] = op_index[MAX_OPERANDS - 1 - i];
10264 op_index[MAX_OPERANDS - 1 - i] = op_ad;
10265 riprel = op_riprel[i];
10266 op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
10267 op_riprel[MAX_OPERANDS - 1 - i] = riprel;
10268 }
10269 }
10270 else
10271 {
10272 for (i = 0; i < MAX_OPERANDS; ++i)
10273 op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
10274 }
10275
10276 needcomma = 0;
10277 for (i = 0; i < MAX_OPERANDS; ++i)
10278 if (*op_txt[i])
10279 {
10280 if (needcomma)
10281 (*info->fprintf_func) (info->stream, ",");
10282 if (op_index[i] != -1 && !op_riprel[i])
10283 (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
10284 else
10285 (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
10286 needcomma = 1;
10287 }
10288
10289 for (i = 0; i < MAX_OPERANDS; i++)
10290 if (op_index[i] != -1 && op_riprel[i])
10291 {
10292 (*info->fprintf_func) (info->stream, " # ");
10293 (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
10294 + op_address[op_index[i]]), info);
10295 break;
10296 }
10297 return codep - priv.the_buffer;
10298 }
10299
10300 static const char *float_mem[] = {
10301 /* d8 */
10302 "fadd{s|}",
10303 "fmul{s|}",
10304 "fcom{s|}",
10305 "fcomp{s|}",
10306 "fsub{s|}",
10307 "fsubr{s|}",
10308 "fdiv{s|}",
10309 "fdivr{s|}",
10310 /* d9 */
10311 "fld{s|}",
10312 "(bad)",
10313 "fst{s|}",
10314 "fstp{s|}",
10315 "fldenvIC",
10316 "fldcw",
10317 "fNstenvIC",
10318 "fNstcw",
10319 /* da */
10320 "fiadd{l|}",
10321 "fimul{l|}",
10322 "ficom{l|}",
10323 "ficomp{l|}",
10324 "fisub{l|}",
10325 "fisubr{l|}",
10326 "fidiv{l|}",
10327 "fidivr{l|}",
10328 /* db */
10329 "fild{l|}",
10330 "fisttp{l|}",
10331 "fist{l|}",
10332 "fistp{l|}",
10333 "(bad)",
10334 "fld{t||t|}",
10335 "(bad)",
10336 "fstp{t||t|}",
10337 /* dc */
10338 "fadd{l|}",
10339 "fmul{l|}",
10340 "fcom{l|}",
10341 "fcomp{l|}",
10342 "fsub{l|}",
10343 "fsubr{l|}",
10344 "fdiv{l|}",
10345 "fdivr{l|}",
10346 /* dd */
10347 "fld{l|}",
10348 "fisttp{ll|}",
10349 "fst{l||}",
10350 "fstp{l|}",
10351 "frstorIC",
10352 "(bad)",
10353 "fNsaveIC",
10354 "fNstsw",
10355 /* de */
10356 "fiadd",
10357 "fimul",
10358 "ficom",
10359 "ficomp",
10360 "fisub",
10361 "fisubr",
10362 "fidiv",
10363 "fidivr",
10364 /* df */
10365 "fild",
10366 "fisttp",
10367 "fist",
10368 "fistp",
10369 "fbld",
10370 "fild{ll|}",
10371 "fbstp",
10372 "fistp{ll|}",
10373 };
10374
10375 static const unsigned char float_mem_mode[] = {
10376 /* d8 */
10377 d_mode,
10378 d_mode,
10379 d_mode,
10380 d_mode,
10381 d_mode,
10382 d_mode,
10383 d_mode,
10384 d_mode,
10385 /* d9 */
10386 d_mode,
10387 0,
10388 d_mode,
10389 d_mode,
10390 0,
10391 w_mode,
10392 0,
10393 w_mode,
10394 /* da */
10395 d_mode,
10396 d_mode,
10397 d_mode,
10398 d_mode,
10399 d_mode,
10400 d_mode,
10401 d_mode,
10402 d_mode,
10403 /* db */
10404 d_mode,
10405 d_mode,
10406 d_mode,
10407 d_mode,
10408 0,
10409 t_mode,
10410 0,
10411 t_mode,
10412 /* dc */
10413 q_mode,
10414 q_mode,
10415 q_mode,
10416 q_mode,
10417 q_mode,
10418 q_mode,
10419 q_mode,
10420 q_mode,
10421 /* dd */
10422 q_mode,
10423 q_mode,
10424 q_mode,
10425 q_mode,
10426 0,
10427 0,
10428 0,
10429 w_mode,
10430 /* de */
10431 w_mode,
10432 w_mode,
10433 w_mode,
10434 w_mode,
10435 w_mode,
10436 w_mode,
10437 w_mode,
10438 w_mode,
10439 /* df */
10440 w_mode,
10441 w_mode,
10442 w_mode,
10443 w_mode,
10444 t_mode,
10445 q_mode,
10446 t_mode,
10447 q_mode
10448 };
10449
10450 #define ST { OP_ST, 0 }
10451 #define STi { OP_STi, 0 }
10452
10453 #define FGRPd9_2 NULL, { { NULL, 0 } }
10454 #define FGRPd9_4 NULL, { { NULL, 1 } }
10455 #define FGRPd9_5 NULL, { { NULL, 2 } }
10456 #define FGRPd9_6 NULL, { { NULL, 3 } }
10457 #define FGRPd9_7 NULL, { { NULL, 4 } }
10458 #define FGRPda_5 NULL, { { NULL, 5 } }
10459 #define FGRPdb_4 NULL, { { NULL, 6 } }
10460 #define FGRPde_3 NULL, { { NULL, 7 } }
10461 #define FGRPdf_4 NULL, { { NULL, 8 } }
10462
10463 static const struct dis386 float_reg[][8] = {
10464 /* d8 */
10465 {
10466 { "fadd", { ST, STi } },
10467 { "fmul", { ST, STi } },
10468 { "fcom", { STi } },
10469 { "fcomp", { STi } },
10470 { "fsub", { ST, STi } },
10471 { "fsubr", { ST, STi } },
10472 { "fdiv", { ST, STi } },
10473 { "fdivr", { ST, STi } },
10474 },
10475 /* d9 */
10476 {
10477 { "fld", { STi } },
10478 { "fxch", { STi } },
10479 { FGRPd9_2 },
10480 { "(bad)", { XX } },
10481 { FGRPd9_4 },
10482 { FGRPd9_5 },
10483 { FGRPd9_6 },
10484 { FGRPd9_7 },
10485 },
10486 /* da */
10487 {
10488 { "fcmovb", { ST, STi } },
10489 { "fcmove", { ST, STi } },
10490 { "fcmovbe",{ ST, STi } },
10491 { "fcmovu", { ST, STi } },
10492 { "(bad)", { XX } },
10493 { FGRPda_5 },
10494 { "(bad)", { XX } },
10495 { "(bad)", { XX } },
10496 },
10497 /* db */
10498 {
10499 { "fcmovnb",{ ST, STi } },
10500 { "fcmovne",{ ST, STi } },
10501 { "fcmovnbe",{ ST, STi } },
10502 { "fcmovnu",{ ST, STi } },
10503 { FGRPdb_4 },
10504 { "fucomi", { ST, STi } },
10505 { "fcomi", { ST, STi } },
10506 { "(bad)", { XX } },
10507 },
10508 /* dc */
10509 {
10510 { "fadd", { STi, ST } },
10511 { "fmul", { STi, ST } },
10512 { "(bad)", { XX } },
10513 { "(bad)", { XX } },
10514 { "fsub!M", { STi, ST } },
10515 { "fsubM", { STi, ST } },
10516 { "fdiv!M", { STi, ST } },
10517 { "fdivM", { STi, ST } },
10518 },
10519 /* dd */
10520 {
10521 { "ffree", { STi } },
10522 { "(bad)", { XX } },
10523 { "fst", { STi } },
10524 { "fstp", { STi } },
10525 { "fucom", { STi } },
10526 { "fucomp", { STi } },
10527 { "(bad)", { XX } },
10528 { "(bad)", { XX } },
10529 },
10530 /* de */
10531 {
10532 { "faddp", { STi, ST } },
10533 { "fmulp", { STi, ST } },
10534 { "(bad)", { XX } },
10535 { FGRPde_3 },
10536 { "fsub!Mp", { STi, ST } },
10537 { "fsubMp", { STi, ST } },
10538 { "fdiv!Mp", { STi, ST } },
10539 { "fdivMp", { STi, ST } },
10540 },
10541 /* df */
10542 {
10543 { "ffreep", { STi } },
10544 { "(bad)", { XX } },
10545 { "(bad)", { XX } },
10546 { "(bad)", { XX } },
10547 { FGRPdf_4 },
10548 { "fucomip", { ST, STi } },
10549 { "fcomip", { ST, STi } },
10550 { "(bad)", { XX } },
10551 },
10552 };
10553
10554 static char *fgrps[][8] = {
10555 /* d9_2 0 */
10556 {
10557 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10558 },
10559
10560 /* d9_4 1 */
10561 {
10562 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
10563 },
10564
10565 /* d9_5 2 */
10566 {
10567 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
10568 },
10569
10570 /* d9_6 3 */
10571 {
10572 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
10573 },
10574
10575 /* d9_7 4 */
10576 {
10577 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
10578 },
10579
10580 /* da_5 5 */
10581 {
10582 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10583 },
10584
10585 /* db_4 6 */
10586 {
10587 "feni(287 only)","fdisi(287 only)","fNclex","fNinit",
10588 "fNsetpm(287 only)","(bad)","(bad)","(bad)",
10589 },
10590
10591 /* de_3 7 */
10592 {
10593 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10594 },
10595
10596 /* df_4 8 */
10597 {
10598 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10599 },
10600 };
10601
10602 static void
10603 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
10604 int sizeflag ATTRIBUTE_UNUSED)
10605 {
10606 /* Skip mod/rm byte. */
10607 MODRM_CHECK;
10608 codep++;
10609 }
10610
10611 static void
10612 dofloat (int sizeflag)
10613 {
10614 const struct dis386 *dp;
10615 unsigned char floatop;
10616
10617 floatop = codep[-1];
10618
10619 if (modrm.mod != 3)
10620 {
10621 int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
10622
10623 putop (float_mem[fp_indx], sizeflag);
10624 obufp = op_out[0];
10625 op_ad = 2;
10626 OP_E (float_mem_mode[fp_indx], sizeflag);
10627 return;
10628 }
10629 /* Skip mod/rm byte. */
10630 MODRM_CHECK;
10631 codep++;
10632
10633 dp = &float_reg[floatop - 0xd8][modrm.reg];
10634 if (dp->name == NULL)
10635 {
10636 putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
10637
10638 /* Instruction fnstsw is only one with strange arg. */
10639 if (floatop == 0xdf && codep[-1] == 0xe0)
10640 strcpy (op_out[0], names16[0]);
10641 }
10642 else
10643 {
10644 putop (dp->name, sizeflag);
10645
10646 obufp = op_out[0];
10647 op_ad = 2;
10648 if (dp->op[0].rtn)
10649 (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
10650
10651 obufp = op_out[1];
10652 op_ad = 1;
10653 if (dp->op[1].rtn)
10654 (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
10655 }
10656 }
10657
10658 static void
10659 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
10660 {
10661 oappend ("%st" + intel_syntax);
10662 }
10663
10664 static void
10665 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
10666 {
10667 sprintf (scratchbuf, "%%st(%d)", modrm.rm);
10668 oappend (scratchbuf + intel_syntax);
10669 }
10670
10671 /* Capital letters in template are macros. */
10672 static int
10673 putop (const char *template, int sizeflag)
10674 {
10675 const char *p;
10676 int alt = 0;
10677 int cond = 1;
10678 unsigned int l = 0, len = 1;
10679 char last[4];
10680
10681 #define SAVE_LAST(c) \
10682 if (l < len && l < sizeof (last)) \
10683 last[l++] = c; \
10684 else \
10685 abort ();
10686
10687 for (p = template; *p; p++)
10688 {
10689 switch (*p)
10690 {
10691 default:
10692 *obufp++ = *p;
10693 break;
10694 case '%':
10695 len++;
10696 break;
10697 case '!':
10698 cond = 0;
10699 break;
10700 case '{':
10701 alt = 0;
10702 if (intel_syntax)
10703 {
10704 while (*++p != '|')
10705 if (*p == '}' || *p == '\0')
10706 abort ();
10707 }
10708 /* Fall through. */
10709 case 'I':
10710 alt = 1;
10711 continue;
10712 case '|':
10713 while (*++p != '}')
10714 {
10715 if (*p == '\0')
10716 abort ();
10717 }
10718 break;
10719 case '}':
10720 break;
10721 case 'A':
10722 if (intel_syntax)
10723 break;
10724 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
10725 *obufp++ = 'b';
10726 break;
10727 case 'B':
10728 if (intel_syntax)
10729 break;
10730 if (sizeflag & SUFFIX_ALWAYS)
10731 *obufp++ = 'b';
10732 break;
10733 case 'C':
10734 if (intel_syntax && !alt)
10735 break;
10736 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10737 {
10738 if (sizeflag & DFLAG)
10739 *obufp++ = intel_syntax ? 'd' : 'l';
10740 else
10741 *obufp++ = intel_syntax ? 'w' : 's';
10742 used_prefixes |= (prefixes & PREFIX_DATA);
10743 }
10744 break;
10745 case 'D':
10746 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
10747 break;
10748 USED_REX (REX_W);
10749 if (modrm.mod == 3)
10750 {
10751 if (rex & REX_W)
10752 *obufp++ = 'q';
10753 else if (sizeflag & DFLAG)
10754 *obufp++ = intel_syntax ? 'd' : 'l';
10755 else
10756 *obufp++ = 'w';
10757 used_prefixes |= (prefixes & PREFIX_DATA);
10758 }
10759 else
10760 *obufp++ = 'w';
10761 break;
10762 case 'E': /* For jcxz/jecxz */
10763 if (address_mode == mode_64bit)
10764 {
10765 if (sizeflag & AFLAG)
10766 *obufp++ = 'r';
10767 else
10768 *obufp++ = 'e';
10769 }
10770 else
10771 if (sizeflag & AFLAG)
10772 *obufp++ = 'e';
10773 used_prefixes |= (prefixes & PREFIX_ADDR);
10774 break;
10775 case 'F':
10776 if (intel_syntax)
10777 break;
10778 if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
10779 {
10780 if (sizeflag & AFLAG)
10781 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
10782 else
10783 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
10784 used_prefixes |= (prefixes & PREFIX_ADDR);
10785 }
10786 break;
10787 case 'G':
10788 if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
10789 break;
10790 if ((rex & REX_W) || (sizeflag & DFLAG))
10791 *obufp++ = 'l';
10792 else
10793 *obufp++ = 'w';
10794 if (!(rex & REX_W))
10795 used_prefixes |= (prefixes & PREFIX_DATA);
10796 break;
10797 case 'H':
10798 if (intel_syntax)
10799 break;
10800 if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
10801 || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
10802 {
10803 used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
10804 *obufp++ = ',';
10805 *obufp++ = 'p';
10806 if (prefixes & PREFIX_DS)
10807 *obufp++ = 't';
10808 else
10809 *obufp++ = 'n';
10810 }
10811 break;
10812 case 'J':
10813 if (intel_syntax)
10814 break;
10815 *obufp++ = 'l';
10816 break;
10817 case 'K':
10818 USED_REX (REX_W);
10819 if (rex & REX_W)
10820 *obufp++ = 'q';
10821 else
10822 *obufp++ = 'd';
10823 break;
10824 case 'Z':
10825 if (intel_syntax)
10826 break;
10827 if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
10828 {
10829 *obufp++ = 'q';
10830 break;
10831 }
10832 /* Fall through. */
10833 goto case_L;
10834 case 'L':
10835 if (l != 0 || len != 1)
10836 {
10837 SAVE_LAST (*p);
10838 break;
10839 }
10840 case_L:
10841 if (intel_syntax)
10842 break;
10843 if (sizeflag & SUFFIX_ALWAYS)
10844 *obufp++ = 'l';
10845 break;
10846 case 'M':
10847 if (intel_mnemonic != cond)
10848 *obufp++ = 'r';
10849 break;
10850 case 'N':
10851 if ((prefixes & PREFIX_FWAIT) == 0)
10852 *obufp++ = 'n';
10853 else
10854 used_prefixes |= PREFIX_FWAIT;
10855 break;
10856 case 'O':
10857 USED_REX (REX_W);
10858 if (rex & REX_W)
10859 *obufp++ = 'o';
10860 else if (intel_syntax && (sizeflag & DFLAG))
10861 *obufp++ = 'q';
10862 else
10863 *obufp++ = 'd';
10864 if (!(rex & REX_W))
10865 used_prefixes |= (prefixes & PREFIX_DATA);
10866 break;
10867 case 'T':
10868 if (intel_syntax)
10869 break;
10870 if (address_mode == mode_64bit && (sizeflag & DFLAG))
10871 {
10872 *obufp++ = 'q';
10873 break;
10874 }
10875 /* Fall through. */
10876 case 'P':
10877 if (intel_syntax)
10878 break;
10879 if ((prefixes & PREFIX_DATA)
10880 || (rex & REX_W)
10881 || (sizeflag & SUFFIX_ALWAYS))
10882 {
10883 USED_REX (REX_W);
10884 if (rex & REX_W)
10885 *obufp++ = 'q';
10886 else
10887 {
10888 if (sizeflag & DFLAG)
10889 *obufp++ = 'l';
10890 else
10891 *obufp++ = 'w';
10892 }
10893 used_prefixes |= (prefixes & PREFIX_DATA);
10894 }
10895 break;
10896 case 'U':
10897 if (intel_syntax)
10898 break;
10899 if (address_mode == mode_64bit && (sizeflag & DFLAG))
10900 {
10901 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
10902 *obufp++ = 'q';
10903 break;
10904 }
10905 /* Fall through. */
10906 goto case_Q;
10907 case 'Q':
10908 if (l == 0 && len == 1)
10909 {
10910 case_Q:
10911 if (intel_syntax && !alt)
10912 break;
10913 USED_REX (REX_W);
10914 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
10915 {
10916 if (rex & REX_W)
10917 *obufp++ = 'q';
10918 else
10919 {
10920 if (sizeflag & DFLAG)
10921 *obufp++ = intel_syntax ? 'd' : 'l';
10922 else
10923 *obufp++ = 'w';
10924 }
10925 used_prefixes |= (prefixes & PREFIX_DATA);
10926 }
10927 }
10928 else
10929 {
10930 if (l != 1 || len != 2 || last[0] != 'L')
10931 {
10932 SAVE_LAST (*p);
10933 break;
10934 }
10935 if (intel_syntax
10936 || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
10937 break;
10938 if ((rex & REX_W))
10939 {
10940 USED_REX (REX_W);
10941 *obufp++ = 'q';
10942 }
10943 else
10944 *obufp++ = 'l';
10945 }
10946 break;
10947 case 'R':
10948 USED_REX (REX_W);
10949 if (rex & REX_W)
10950 *obufp++ = 'q';
10951 else if (sizeflag & DFLAG)
10952 {
10953 if (intel_syntax)
10954 *obufp++ = 'd';
10955 else
10956 *obufp++ = 'l';
10957 }
10958 else
10959 *obufp++ = 'w';
10960 if (intel_syntax && !p[1]
10961 && ((rex & REX_W) || (sizeflag & DFLAG)))
10962 *obufp++ = 'e';
10963 if (!(rex & REX_W))
10964 used_prefixes |= (prefixes & PREFIX_DATA);
10965 break;
10966 case 'V':
10967 if (intel_syntax)
10968 break;
10969 if (address_mode == mode_64bit && (sizeflag & DFLAG))
10970 {
10971 if (sizeflag & SUFFIX_ALWAYS)
10972 *obufp++ = 'q';
10973 break;
10974 }
10975 /* Fall through. */
10976 case 'S':
10977 if (intel_syntax)
10978 break;
10979 if (sizeflag & SUFFIX_ALWAYS)
10980 {
10981 if (rex & REX_W)
10982 *obufp++ = 'q';
10983 else
10984 {
10985 if (sizeflag & DFLAG)
10986 *obufp++ = 'l';
10987 else
10988 *obufp++ = 'w';
10989 used_prefixes |= (prefixes & PREFIX_DATA);
10990 }
10991 }
10992 break;
10993 case 'X':
10994 if (l != 0 || len != 1)
10995 {
10996 SAVE_LAST (*p);
10997 break;
10998 }
10999 if (need_vex && vex.prefix)
11000 {
11001 if (vex.prefix == DATA_PREFIX_OPCODE)
11002 *obufp++ = 'd';
11003 else
11004 *obufp++ = 's';
11005 }
11006 else if (prefixes & PREFIX_DATA)
11007 *obufp++ = 'd';
11008 else
11009 *obufp++ = 's';
11010 used_prefixes |= (prefixes & PREFIX_DATA);
11011 break;
11012 case 'Y':
11013 if (l == 0 && len == 1)
11014 {
11015 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
11016 break;
11017 if (rex & REX_W)
11018 {
11019 USED_REX (REX_W);
11020 *obufp++ = 'q';
11021 }
11022 break;
11023 }
11024 else
11025 {
11026 if (l != 1 || len != 2 || last[0] != 'X')
11027 {
11028 SAVE_LAST (*p);
11029 break;
11030 }
11031 if (!need_vex)
11032 abort ();
11033 if (intel_syntax
11034 || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
11035 break;
11036 switch (vex.length)
11037 {
11038 case 128:
11039 *obufp++ = 'x';
11040 break;
11041 case 256:
11042 *obufp++ = 'y';
11043 break;
11044 default:
11045 abort ();
11046 }
11047 }
11048 break;
11049 /* implicit operand size 'l' for i386 or 'q' for x86-64 */
11050 case 'W':
11051 /* operand size flag for cwtl, cbtw */
11052 USED_REX (REX_W);
11053 if (rex & REX_W)
11054 {
11055 if (intel_syntax)
11056 *obufp++ = 'd';
11057 else
11058 *obufp++ = 'l';
11059 }
11060 else if (sizeflag & DFLAG)
11061 *obufp++ = 'w';
11062 else
11063 *obufp++ = 'b';
11064 if (!(rex & REX_W))
11065 used_prefixes |= (prefixes & PREFIX_DATA);
11066 break;
11067 }
11068 alt = 0;
11069 }
11070 *obufp = 0;
11071 return 0;
11072 }
11073
11074 static void
11075 oappend (const char *s)
11076 {
11077 strcpy (obufp, s);
11078 obufp += strlen (s);
11079 }
11080
11081 static void
11082 append_seg (void)
11083 {
11084 if (prefixes & PREFIX_CS)
11085 {
11086 used_prefixes |= PREFIX_CS;
11087 oappend ("%cs:" + intel_syntax);
11088 }
11089 if (prefixes & PREFIX_DS)
11090 {
11091 used_prefixes |= PREFIX_DS;
11092 oappend ("%ds:" + intel_syntax);
11093 }
11094 if (prefixes & PREFIX_SS)
11095 {
11096 used_prefixes |= PREFIX_SS;
11097 oappend ("%ss:" + intel_syntax);
11098 }
11099 if (prefixes & PREFIX_ES)
11100 {
11101 used_prefixes |= PREFIX_ES;
11102 oappend ("%es:" + intel_syntax);
11103 }
11104 if (prefixes & PREFIX_FS)
11105 {
11106 used_prefixes |= PREFIX_FS;
11107 oappend ("%fs:" + intel_syntax);
11108 }
11109 if (prefixes & PREFIX_GS)
11110 {
11111 used_prefixes |= PREFIX_GS;
11112 oappend ("%gs:" + intel_syntax);
11113 }
11114 }
11115
11116 static void
11117 OP_indirE (int bytemode, int sizeflag)
11118 {
11119 if (!intel_syntax)
11120 oappend ("*");
11121 OP_E (bytemode, sizeflag);
11122 }
11123
11124 static void
11125 print_operand_value (char *buf, int hex, bfd_vma disp)
11126 {
11127 if (address_mode == mode_64bit)
11128 {
11129 if (hex)
11130 {
11131 char tmp[30];
11132 int i;
11133 buf[0] = '0';
11134 buf[1] = 'x';
11135 sprintf_vma (tmp, disp);
11136 for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
11137 strcpy (buf + 2, tmp + i);
11138 }
11139 else
11140 {
11141 bfd_signed_vma v = disp;
11142 char tmp[30];
11143 int i;
11144 if (v < 0)
11145 {
11146 *(buf++) = '-';
11147 v = -disp;
11148 /* Check for possible overflow on 0x8000000000000000. */
11149 if (v < 0)
11150 {
11151 strcpy (buf, "9223372036854775808");
11152 return;
11153 }
11154 }
11155 if (!v)
11156 {
11157 strcpy (buf, "0");
11158 return;
11159 }
11160
11161 i = 0;
11162 tmp[29] = 0;
11163 while (v)
11164 {
11165 tmp[28 - i] = (v % 10) + '0';
11166 v /= 10;
11167 i++;
11168 }
11169 strcpy (buf, tmp + 29 - i);
11170 }
11171 }
11172 else
11173 {
11174 if (hex)
11175 sprintf (buf, "0x%x", (unsigned int) disp);
11176 else
11177 sprintf (buf, "%d", (int) disp);
11178 }
11179 }
11180
11181 /* Put DISP in BUF as signed hex number. */
11182
11183 static void
11184 print_displacement (char *buf, bfd_vma disp)
11185 {
11186 bfd_signed_vma val = disp;
11187 char tmp[30];
11188 int i, j = 0;
11189
11190 if (val < 0)
11191 {
11192 buf[j++] = '-';
11193 val = -disp;
11194
11195 /* Check for possible overflow. */
11196 if (val < 0)
11197 {
11198 switch (address_mode)
11199 {
11200 case mode_64bit:
11201 strcpy (buf + j, "0x8000000000000000");
11202 break;
11203 case mode_32bit:
11204 strcpy (buf + j, "0x80000000");
11205 break;
11206 case mode_16bit:
11207 strcpy (buf + j, "0x8000");
11208 break;
11209 }
11210 return;
11211 }
11212 }
11213
11214 buf[j++] = '0';
11215 buf[j++] = 'x';
11216
11217 sprintf_vma (tmp, val);
11218 for (i = 0; tmp[i] == '0'; i++)
11219 continue;
11220 if (tmp[i] == '\0')
11221 i--;
11222 strcpy (buf + j, tmp + i);
11223 }
11224
11225 static void
11226 intel_operand_size (int bytemode, int sizeflag)
11227 {
11228 switch (bytemode)
11229 {
11230 case b_mode:
11231 case dqb_mode:
11232 oappend ("BYTE PTR ");
11233 break;
11234 case w_mode:
11235 case dqw_mode:
11236 oappend ("WORD PTR ");
11237 break;
11238 case stack_v_mode:
11239 if (address_mode == mode_64bit && (sizeflag & DFLAG))
11240 {
11241 oappend ("QWORD PTR ");
11242 used_prefixes |= (prefixes & PREFIX_DATA);
11243 break;
11244 }
11245 /* FALLTHRU */
11246 case v_mode:
11247 case dq_mode:
11248 USED_REX (REX_W);
11249 if (rex & REX_W)
11250 oappend ("QWORD PTR ");
11251 else if ((sizeflag & DFLAG) || bytemode == dq_mode)
11252 oappend ("DWORD PTR ");
11253 else
11254 oappend ("WORD PTR ");
11255 used_prefixes |= (prefixes & PREFIX_DATA);
11256 break;
11257 case z_mode:
11258 if ((rex & REX_W) || (sizeflag & DFLAG))
11259 *obufp++ = 'D';
11260 oappend ("WORD PTR ");
11261 if (!(rex & REX_W))
11262 used_prefixes |= (prefixes & PREFIX_DATA);
11263 break;
11264 case a_mode:
11265 if (sizeflag & DFLAG)
11266 oappend ("QWORD PTR ");
11267 else
11268 oappend ("DWORD PTR ");
11269 used_prefixes |= (prefixes & PREFIX_DATA);
11270 break;
11271 case d_mode:
11272 case dqd_mode:
11273 oappend ("DWORD PTR ");
11274 break;
11275 case q_mode:
11276 oappend ("QWORD PTR ");
11277 break;
11278 case m_mode:
11279 if (address_mode == mode_64bit)
11280 oappend ("QWORD PTR ");
11281 else
11282 oappend ("DWORD PTR ");
11283 break;
11284 case f_mode:
11285 if (sizeflag & DFLAG)
11286 oappend ("FWORD PTR ");
11287 else
11288 oappend ("DWORD PTR ");
11289 used_prefixes |= (prefixes & PREFIX_DATA);
11290 break;
11291 case t_mode:
11292 oappend ("TBYTE PTR ");
11293 break;
11294 case x_mode:
11295 if (need_vex)
11296 {
11297 switch (vex.length)
11298 {
11299 case 128:
11300 oappend ("XMMWORD PTR ");
11301 break;
11302 case 256:
11303 oappend ("YMMWORD PTR ");
11304 break;
11305 default:
11306 abort ();
11307 }
11308 }
11309 else
11310 oappend ("XMMWORD PTR ");
11311 break;
11312 case xmm_mode:
11313 oappend ("XMMWORD PTR ");
11314 break;
11315 case xmmq_mode:
11316 if (!need_vex)
11317 abort ();
11318
11319 switch (vex.length)
11320 {
11321 case 128:
11322 oappend ("QWORD PTR ");
11323 break;
11324 case 256:
11325 oappend ("XMMWORD PTR ");
11326 break;
11327 default:
11328 abort ();
11329 }
11330 break;
11331 case ymmq_mode:
11332 if (!need_vex)
11333 abort ();
11334
11335 switch (vex.length)
11336 {
11337 case 128:
11338 oappend ("QWORD PTR ");
11339 break;
11340 case 256:
11341 oappend ("YMMWORD PTR ");
11342 break;
11343 default:
11344 abort ();
11345 }
11346 break;
11347 case o_mode:
11348 oappend ("OWORD PTR ");
11349 break;
11350 default:
11351 break;
11352 }
11353 }
11354
11355 static void
11356 OP_E_register (int bytemode, int sizeflag)
11357 {
11358 int reg = modrm.rm;
11359 const char **names;
11360
11361 USED_REX (REX_B);
11362 if ((rex & REX_B))
11363 reg += 8;
11364
11365 switch (bytemode)
11366 {
11367 case b_mode:
11368 USED_REX (0);
11369 if (rex)
11370 names = names8rex;
11371 else
11372 names = names8;
11373 break;
11374 case w_mode:
11375 names = names16;
11376 break;
11377 case d_mode:
11378 names = names32;
11379 break;
11380 case q_mode:
11381 names = names64;
11382 break;
11383 case m_mode:
11384 names = address_mode == mode_64bit ? names64 : names32;
11385 break;
11386 case stack_v_mode:
11387 if (address_mode == mode_64bit && (sizeflag & DFLAG))
11388 {
11389 names = names64;
11390 used_prefixes |= (prefixes & PREFIX_DATA);
11391 break;
11392 }
11393 bytemode = v_mode;
11394 /* FALLTHRU */
11395 case v_mode:
11396 case dq_mode:
11397 case dqb_mode:
11398 case dqd_mode:
11399 case dqw_mode:
11400 USED_REX (REX_W);
11401 if (rex & REX_W)
11402 names = names64;
11403 else if ((sizeflag & DFLAG) || bytemode != v_mode)
11404 names = names32;
11405 else
11406 names = names16;
11407 used_prefixes |= (prefixes & PREFIX_DATA);
11408 break;
11409 case 0:
11410 return;
11411 default:
11412 oappend (INTERNAL_DISASSEMBLER_ERROR);
11413 return;
11414 }
11415 oappend (names[reg]);
11416 }
11417
11418 static void
11419 OP_E_memory (int bytemode, int sizeflag, int has_drex)
11420 {
11421 bfd_vma disp = 0;
11422 int add = (rex & REX_B) ? 8 : 0;
11423 int riprel = 0;
11424
11425 USED_REX (REX_B);
11426 if (intel_syntax)
11427 intel_operand_size (bytemode, sizeflag);
11428 append_seg ();
11429
11430 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
11431 {
11432 /* 32/64 bit address mode */
11433 int havedisp;
11434 int havesib;
11435 int havebase;
11436 int haveindex;
11437 int needindex;
11438 int base, rbase;
11439 int index = 0;
11440 int scale = 0;
11441
11442 havesib = 0;
11443 havebase = 1;
11444 haveindex = 0;
11445 base = modrm.rm;
11446
11447 if (base == 4)
11448 {
11449 havesib = 1;
11450 FETCH_DATA (the_info, codep + 1);
11451 index = (*codep >> 3) & 7;
11452 scale = (*codep >> 6) & 3;
11453 base = *codep & 7;
11454 USED_REX (REX_X);
11455 if (rex & REX_X)
11456 index += 8;
11457 haveindex = index != 4;
11458 codep++;
11459 }
11460 rbase = base + add;
11461
11462 /* If we have a DREX byte, skip it now
11463 (it has already been handled) */
11464 if (has_drex)
11465 {
11466 FETCH_DATA (the_info, codep + 1);
11467 codep++;
11468 }
11469
11470 switch (modrm.mod)
11471 {
11472 case 0:
11473 if (base == 5)
11474 {
11475 havebase = 0;
11476 if (address_mode == mode_64bit && !havesib)
11477 riprel = 1;
11478 disp = get32s ();
11479 }
11480 break;
11481 case 1:
11482 FETCH_DATA (the_info, codep + 1);
11483 disp = *codep++;
11484 if ((disp & 0x80) != 0)
11485 disp -= 0x100;
11486 break;
11487 case 2:
11488 disp = get32s ();
11489 break;
11490 }
11491
11492 /* In 32bit mode, we need index register to tell [offset] from
11493 [eiz*1 + offset]. */
11494 needindex = (havesib
11495 && !havebase
11496 && !haveindex
11497 && address_mode == mode_32bit);
11498 havedisp = (havebase
11499 || needindex
11500 || (havesib && (haveindex || scale != 0)));
11501
11502 if (!intel_syntax)
11503 if (modrm.mod != 0 || base == 5)
11504 {
11505 if (havedisp || riprel)
11506 print_displacement (scratchbuf, disp);
11507 else
11508 print_operand_value (scratchbuf, 1, disp);
11509 oappend (scratchbuf);
11510 if (riprel)
11511 {
11512 set_op (disp, 1);
11513 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
11514 }
11515 }
11516
11517 if (havebase || haveindex || riprel)
11518 used_prefixes |= PREFIX_ADDR;
11519
11520 if (havedisp || (intel_syntax && riprel))
11521 {
11522 *obufp++ = open_char;
11523 if (intel_syntax && riprel)
11524 {
11525 set_op (disp, 1);
11526 oappend (sizeflag & AFLAG ? "rip" : "eip");
11527 }
11528 *obufp = '\0';
11529 if (havebase)
11530 oappend (address_mode == mode_64bit && (sizeflag & AFLAG)
11531 ? names64[rbase] : names32[rbase]);
11532 if (havesib)
11533 {
11534 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
11535 print index to tell base + index from base. */
11536 if (scale != 0
11537 || needindex
11538 || haveindex
11539 || (havebase && base != ESP_REG_NUM))
11540 {
11541 if (!intel_syntax || havebase)
11542 {
11543 *obufp++ = separator_char;
11544 *obufp = '\0';
11545 }
11546 if (haveindex)
11547 oappend (address_mode == mode_64bit
11548 && (sizeflag & AFLAG)
11549 ? names64[index] : names32[index]);
11550 else
11551 oappend (address_mode == mode_64bit
11552 && (sizeflag & AFLAG)
11553 ? index64 : index32);
11554
11555 *obufp++ = scale_char;
11556 *obufp = '\0';
11557 sprintf (scratchbuf, "%d", 1 << scale);
11558 oappend (scratchbuf);
11559 }
11560 }
11561 if (intel_syntax
11562 && (disp || modrm.mod != 0 || base == 5))
11563 {
11564 if (!havedisp || (bfd_signed_vma) disp >= 0)
11565 {
11566 *obufp++ = '+';
11567 *obufp = '\0';
11568 }
11569 else if (modrm.mod != 1)
11570 {
11571 *obufp++ = '-';
11572 *obufp = '\0';
11573 disp = - (bfd_signed_vma) disp;
11574 }
11575
11576 if (havedisp)
11577 print_displacement (scratchbuf, disp);
11578 else
11579 print_operand_value (scratchbuf, 1, disp);
11580 oappend (scratchbuf);
11581 }
11582
11583 *obufp++ = close_char;
11584 *obufp = '\0';
11585 }
11586 else if (intel_syntax)
11587 {
11588 if (modrm.mod != 0 || base == 5)
11589 {
11590 if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
11591 | PREFIX_ES | PREFIX_FS | PREFIX_GS))
11592 ;
11593 else
11594 {
11595 oappend (names_seg[ds_reg - es_reg]);
11596 oappend (":");
11597 }
11598 print_operand_value (scratchbuf, 1, disp);
11599 oappend (scratchbuf);
11600 }
11601 }
11602 }
11603 else
11604 { /* 16 bit address mode */
11605 switch (modrm.mod)
11606 {
11607 case 0:
11608 if (modrm.rm == 6)
11609 {
11610 disp = get16 ();
11611 if ((disp & 0x8000) != 0)
11612 disp -= 0x10000;
11613 }
11614 break;
11615 case 1:
11616 FETCH_DATA (the_info, codep + 1);
11617 disp = *codep++;
11618 if ((disp & 0x80) != 0)
11619 disp -= 0x100;
11620 break;
11621 case 2:
11622 disp = get16 ();
11623 if ((disp & 0x8000) != 0)
11624 disp -= 0x10000;
11625 break;
11626 }
11627
11628 if (!intel_syntax)
11629 if (modrm.mod != 0 || modrm.rm == 6)
11630 {
11631 print_displacement (scratchbuf, disp);
11632 oappend (scratchbuf);
11633 }
11634
11635 if (modrm.mod != 0 || modrm.rm != 6)
11636 {
11637 *obufp++ = open_char;
11638 *obufp = '\0';
11639 oappend (index16[modrm.rm]);
11640 if (intel_syntax
11641 && (disp || modrm.mod != 0 || modrm.rm == 6))
11642 {
11643 if ((bfd_signed_vma) disp >= 0)
11644 {
11645 *obufp++ = '+';
11646 *obufp = '\0';
11647 }
11648 else if (modrm.mod != 1)
11649 {
11650 *obufp++ = '-';
11651 *obufp = '\0';
11652 disp = - (bfd_signed_vma) disp;
11653 }
11654
11655 print_displacement (scratchbuf, disp);
11656 oappend (scratchbuf);
11657 }
11658
11659 *obufp++ = close_char;
11660 *obufp = '\0';
11661 }
11662 else if (intel_syntax)
11663 {
11664 if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
11665 | PREFIX_ES | PREFIX_FS | PREFIX_GS))
11666 ;
11667 else
11668 {
11669 oappend (names_seg[ds_reg - es_reg]);
11670 oappend (":");
11671 }
11672 print_operand_value (scratchbuf, 1, disp & 0xffff);
11673 oappend (scratchbuf);
11674 }
11675 }
11676 }
11677
11678 static void
11679 OP_E_extended (int bytemode, int sizeflag, int has_drex)
11680 {
11681 /* Skip mod/rm byte. */
11682 MODRM_CHECK;
11683 codep++;
11684
11685 if (modrm.mod == 3)
11686 OP_E_register (bytemode, sizeflag);
11687 else
11688 OP_E_memory (bytemode, sizeflag, has_drex);
11689 }
11690
11691 static void
11692 OP_E (int bytemode, int sizeflag)
11693 {
11694 OP_E_extended (bytemode, sizeflag, 0);
11695 }
11696
11697
11698 static void
11699 OP_G (int bytemode, int sizeflag)
11700 {
11701 int add = 0;
11702 USED_REX (REX_R);
11703 if (rex & REX_R)
11704 add += 8;
11705 switch (bytemode)
11706 {
11707 case b_mode:
11708 USED_REX (0);
11709 if (rex)
11710 oappend (names8rex[modrm.reg + add]);
11711 else
11712 oappend (names8[modrm.reg + add]);
11713 break;
11714 case w_mode:
11715 oappend (names16[modrm.reg + add]);
11716 break;
11717 case d_mode:
11718 oappend (names32[modrm.reg + add]);
11719 break;
11720 case q_mode:
11721 oappend (names64[modrm.reg + add]);
11722 break;
11723 case v_mode:
11724 case dq_mode:
11725 case dqb_mode:
11726 case dqd_mode:
11727 case dqw_mode:
11728 USED_REX (REX_W);
11729 if (rex & REX_W)
11730 oappend (names64[modrm.reg + add]);
11731 else if ((sizeflag & DFLAG) || bytemode != v_mode)
11732 oappend (names32[modrm.reg + add]);
11733 else
11734 oappend (names16[modrm.reg + add]);
11735 used_prefixes |= (prefixes & PREFIX_DATA);
11736 break;
11737 case m_mode:
11738 if (address_mode == mode_64bit)
11739 oappend (names64[modrm.reg + add]);
11740 else
11741 oappend (names32[modrm.reg + add]);
11742 break;
11743 default:
11744 oappend (INTERNAL_DISASSEMBLER_ERROR);
11745 break;
11746 }
11747 }
11748
11749 static bfd_vma
11750 get64 (void)
11751 {
11752 bfd_vma x;
11753 #ifdef BFD64
11754 unsigned int a;
11755 unsigned int b;
11756
11757 FETCH_DATA (the_info, codep + 8);
11758 a = *codep++ & 0xff;
11759 a |= (*codep++ & 0xff) << 8;
11760 a |= (*codep++ & 0xff) << 16;
11761 a |= (*codep++ & 0xff) << 24;
11762 b = *codep++ & 0xff;
11763 b |= (*codep++ & 0xff) << 8;
11764 b |= (*codep++ & 0xff) << 16;
11765 b |= (*codep++ & 0xff) << 24;
11766 x = a + ((bfd_vma) b << 32);
11767 #else
11768 abort ();
11769 x = 0;
11770 #endif
11771 return x;
11772 }
11773
11774 static bfd_signed_vma
11775 get32 (void)
11776 {
11777 bfd_signed_vma x = 0;
11778
11779 FETCH_DATA (the_info, codep + 4);
11780 x = *codep++ & (bfd_signed_vma) 0xff;
11781 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
11782 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
11783 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
11784 return x;
11785 }
11786
11787 static bfd_signed_vma
11788 get32s (void)
11789 {
11790 bfd_signed_vma x = 0;
11791
11792 FETCH_DATA (the_info, codep + 4);
11793 x = *codep++ & (bfd_signed_vma) 0xff;
11794 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
11795 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
11796 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
11797
11798 x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
11799
11800 return x;
11801 }
11802
11803 static int
11804 get16 (void)
11805 {
11806 int x = 0;
11807
11808 FETCH_DATA (the_info, codep + 2);
11809 x = *codep++ & 0xff;
11810 x |= (*codep++ & 0xff) << 8;
11811 return x;
11812 }
11813
11814 static void
11815 set_op (bfd_vma op, int riprel)
11816 {
11817 op_index[op_ad] = op_ad;
11818 if (address_mode == mode_64bit)
11819 {
11820 op_address[op_ad] = op;
11821 op_riprel[op_ad] = riprel;
11822 }
11823 else
11824 {
11825 /* Mask to get a 32-bit address. */
11826 op_address[op_ad] = op & 0xffffffff;
11827 op_riprel[op_ad] = riprel & 0xffffffff;
11828 }
11829 }
11830
11831 static void
11832 OP_REG (int code, int sizeflag)
11833 {
11834 const char *s;
11835 int add;
11836 USED_REX (REX_B);
11837 if (rex & REX_B)
11838 add = 8;
11839 else
11840 add = 0;
11841
11842 switch (code)
11843 {
11844 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
11845 case sp_reg: case bp_reg: case si_reg: case di_reg:
11846 s = names16[code - ax_reg + add];
11847 break;
11848 case es_reg: case ss_reg: case cs_reg:
11849 case ds_reg: case fs_reg: case gs_reg:
11850 s = names_seg[code - es_reg + add];
11851 break;
11852 case al_reg: case ah_reg: case cl_reg: case ch_reg:
11853 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
11854 USED_REX (0);
11855 if (rex)
11856 s = names8rex[code - al_reg + add];
11857 else
11858 s = names8[code - al_reg];
11859 break;
11860 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
11861 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
11862 if (address_mode == mode_64bit && (sizeflag & DFLAG))
11863 {
11864 s = names64[code - rAX_reg + add];
11865 break;
11866 }
11867 code += eAX_reg - rAX_reg;
11868 /* Fall through. */
11869 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
11870 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
11871 USED_REX (REX_W);
11872 if (rex & REX_W)
11873 s = names64[code - eAX_reg + add];
11874 else if (sizeflag & DFLAG)
11875 s = names32[code - eAX_reg + add];
11876 else
11877 s = names16[code - eAX_reg + add];
11878 used_prefixes |= (prefixes & PREFIX_DATA);
11879 break;
11880 default:
11881 s = INTERNAL_DISASSEMBLER_ERROR;
11882 break;
11883 }
11884 oappend (s);
11885 }
11886
11887 static void
11888 OP_IMREG (int code, int sizeflag)
11889 {
11890 const char *s;
11891
11892 switch (code)
11893 {
11894 case indir_dx_reg:
11895 if (intel_syntax)
11896 s = "dx";
11897 else
11898 s = "(%dx)";
11899 break;
11900 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
11901 case sp_reg: case bp_reg: case si_reg: case di_reg:
11902 s = names16[code - ax_reg];
11903 break;
11904 case es_reg: case ss_reg: case cs_reg:
11905 case ds_reg: case fs_reg: case gs_reg:
11906 s = names_seg[code - es_reg];
11907 break;
11908 case al_reg: case ah_reg: case cl_reg: case ch_reg:
11909 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
11910 USED_REX (0);
11911 if (rex)
11912 s = names8rex[code - al_reg];
11913 else
11914 s = names8[code - al_reg];
11915 break;
11916 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
11917 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
11918 USED_REX (REX_W);
11919 if (rex & REX_W)
11920 s = names64[code - eAX_reg];
11921 else if (sizeflag & DFLAG)
11922 s = names32[code - eAX_reg];
11923 else
11924 s = names16[code - eAX_reg];
11925 used_prefixes |= (prefixes & PREFIX_DATA);
11926 break;
11927 case z_mode_ax_reg:
11928 if ((rex & REX_W) || (sizeflag & DFLAG))
11929 s = *names32;
11930 else
11931 s = *names16;
11932 if (!(rex & REX_W))
11933 used_prefixes |= (prefixes & PREFIX_DATA);
11934 break;
11935 default:
11936 s = INTERNAL_DISASSEMBLER_ERROR;
11937 break;
11938 }
11939 oappend (s);
11940 }
11941
11942 static void
11943 OP_I (int bytemode, int sizeflag)
11944 {
11945 bfd_signed_vma op;
11946 bfd_signed_vma mask = -1;
11947
11948 switch (bytemode)
11949 {
11950 case b_mode:
11951 FETCH_DATA (the_info, codep + 1);
11952 op = *codep++;
11953 mask = 0xff;
11954 break;
11955 case q_mode:
11956 if (address_mode == mode_64bit)
11957 {
11958 op = get32s ();
11959 break;
11960 }
11961 /* Fall through. */
11962 case v_mode:
11963 USED_REX (REX_W);
11964 if (rex & REX_W)
11965 op = get32s ();
11966 else if (sizeflag & DFLAG)
11967 {
11968 op = get32 ();
11969 mask = 0xffffffff;
11970 }
11971 else
11972 {
11973 op = get16 ();
11974 mask = 0xfffff;
11975 }
11976 used_prefixes |= (prefixes & PREFIX_DATA);
11977 break;
11978 case w_mode:
11979 mask = 0xfffff;
11980 op = get16 ();
11981 break;
11982 case const_1_mode:
11983 if (intel_syntax)
11984 oappend ("1");
11985 return;
11986 default:
11987 oappend (INTERNAL_DISASSEMBLER_ERROR);
11988 return;
11989 }
11990
11991 op &= mask;
11992 scratchbuf[0] = '$';
11993 print_operand_value (scratchbuf + 1, 1, op);
11994 oappend (scratchbuf + intel_syntax);
11995 scratchbuf[0] = '\0';
11996 }
11997
11998 static void
11999 OP_I64 (int bytemode, int sizeflag)
12000 {
12001 bfd_signed_vma op;
12002 bfd_signed_vma mask = -1;
12003
12004 if (address_mode != mode_64bit)
12005 {
12006 OP_I (bytemode, sizeflag);
12007 return;
12008 }
12009
12010 switch (bytemode)
12011 {
12012 case b_mode:
12013 FETCH_DATA (the_info, codep + 1);
12014 op = *codep++;
12015 mask = 0xff;
12016 break;
12017 case v_mode:
12018 USED_REX (REX_W);
12019 if (rex & REX_W)
12020 op = get64 ();
12021 else if (sizeflag & DFLAG)
12022 {
12023 op = get32 ();
12024 mask = 0xffffffff;
12025 }
12026 else
12027 {
12028 op = get16 ();
12029 mask = 0xfffff;
12030 }
12031 used_prefixes |= (prefixes & PREFIX_DATA);
12032 break;
12033 case w_mode:
12034 mask = 0xfffff;
12035 op = get16 ();
12036 break;
12037 default:
12038 oappend (INTERNAL_DISASSEMBLER_ERROR);
12039 return;
12040 }
12041
12042 op &= mask;
12043 scratchbuf[0] = '$';
12044 print_operand_value (scratchbuf + 1, 1, op);
12045 oappend (scratchbuf + intel_syntax);
12046 scratchbuf[0] = '\0';
12047 }
12048
12049 static void
12050 OP_sI (int bytemode, int sizeflag)
12051 {
12052 bfd_signed_vma op;
12053 bfd_signed_vma mask = -1;
12054
12055 switch (bytemode)
12056 {
12057 case b_mode:
12058 FETCH_DATA (the_info, codep + 1);
12059 op = *codep++;
12060 if ((op & 0x80) != 0)
12061 op -= 0x100;
12062 mask = 0xffffffff;
12063 break;
12064 case v_mode:
12065 USED_REX (REX_W);
12066 if (rex & REX_W)
12067 op = get32s ();
12068 else if (sizeflag & DFLAG)
12069 {
12070 op = get32s ();
12071 mask = 0xffffffff;
12072 }
12073 else
12074 {
12075 mask = 0xffffffff;
12076 op = get16 ();
12077 if ((op & 0x8000) != 0)
12078 op -= 0x10000;
12079 }
12080 used_prefixes |= (prefixes & PREFIX_DATA);
12081 break;
12082 case w_mode:
12083 op = get16 ();
12084 mask = 0xffffffff;
12085 if ((op & 0x8000) != 0)
12086 op -= 0x10000;
12087 break;
12088 default:
12089 oappend (INTERNAL_DISASSEMBLER_ERROR);
12090 return;
12091 }
12092
12093 scratchbuf[0] = '$';
12094 print_operand_value (scratchbuf + 1, 1, op);
12095 oappend (scratchbuf + intel_syntax);
12096 }
12097
12098 static void
12099 OP_J (int bytemode, int sizeflag)
12100 {
12101 bfd_vma disp;
12102 bfd_vma mask = -1;
12103 bfd_vma segment = 0;
12104
12105 switch (bytemode)
12106 {
12107 case b_mode:
12108 FETCH_DATA (the_info, codep + 1);
12109 disp = *codep++;
12110 if ((disp & 0x80) != 0)
12111 disp -= 0x100;
12112 break;
12113 case v_mode:
12114 if ((sizeflag & DFLAG) || (rex & REX_W))
12115 disp = get32s ();
12116 else
12117 {
12118 disp = get16 ();
12119 if ((disp & 0x8000) != 0)
12120 disp -= 0x10000;
12121 /* In 16bit mode, address is wrapped around at 64k within
12122 the same segment. Otherwise, a data16 prefix on a jump
12123 instruction means that the pc is masked to 16 bits after
12124 the displacement is added! */
12125 mask = 0xffff;
12126 if ((prefixes & PREFIX_DATA) == 0)
12127 segment = ((start_pc + codep - start_codep)
12128 & ~((bfd_vma) 0xffff));
12129 }
12130 used_prefixes |= (prefixes & PREFIX_DATA);
12131 break;
12132 default:
12133 oappend (INTERNAL_DISASSEMBLER_ERROR);
12134 return;
12135 }
12136 disp = ((start_pc + codep - start_codep + disp) & mask) | segment;
12137 set_op (disp, 0);
12138 print_operand_value (scratchbuf, 1, disp);
12139 oappend (scratchbuf);
12140 }
12141
12142 static void
12143 OP_SEG (int bytemode, int sizeflag)
12144 {
12145 if (bytemode == w_mode)
12146 oappend (names_seg[modrm.reg]);
12147 else
12148 OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
12149 }
12150
12151 static void
12152 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
12153 {
12154 int seg, offset;
12155
12156 if (sizeflag & DFLAG)
12157 {
12158 offset = get32 ();
12159 seg = get16 ();
12160 }
12161 else
12162 {
12163 offset = get16 ();
12164 seg = get16 ();
12165 }
12166 used_prefixes |= (prefixes & PREFIX_DATA);
12167 if (intel_syntax)
12168 sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
12169 else
12170 sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
12171 oappend (scratchbuf);
12172 }
12173
12174 static void
12175 OP_OFF (int bytemode, int sizeflag)
12176 {
12177 bfd_vma off;
12178
12179 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12180 intel_operand_size (bytemode, sizeflag);
12181 append_seg ();
12182
12183 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
12184 off = get32 ();
12185 else
12186 off = get16 ();
12187
12188 if (intel_syntax)
12189 {
12190 if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
12191 | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
12192 {
12193 oappend (names_seg[ds_reg - es_reg]);
12194 oappend (":");
12195 }
12196 }
12197 print_operand_value (scratchbuf, 1, off);
12198 oappend (scratchbuf);
12199 }
12200
12201 static void
12202 OP_OFF64 (int bytemode, int sizeflag)
12203 {
12204 bfd_vma off;
12205
12206 if (address_mode != mode_64bit
12207 || (prefixes & PREFIX_ADDR))
12208 {
12209 OP_OFF (bytemode, sizeflag);
12210 return;
12211 }
12212
12213 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12214 intel_operand_size (bytemode, sizeflag);
12215 append_seg ();
12216
12217 off = get64 ();
12218
12219 if (intel_syntax)
12220 {
12221 if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
12222 | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
12223 {
12224 oappend (names_seg[ds_reg - es_reg]);
12225 oappend (":");
12226 }
12227 }
12228 print_operand_value (scratchbuf, 1, off);
12229 oappend (scratchbuf);
12230 }
12231
12232 static void
12233 ptr_reg (int code, int sizeflag)
12234 {
12235 const char *s;
12236
12237 *obufp++ = open_char;
12238 used_prefixes |= (prefixes & PREFIX_ADDR);
12239 if (address_mode == mode_64bit)
12240 {
12241 if (!(sizeflag & AFLAG))
12242 s = names32[code - eAX_reg];
12243 else
12244 s = names64[code - eAX_reg];
12245 }
12246 else if (sizeflag & AFLAG)
12247 s = names32[code - eAX_reg];
12248 else
12249 s = names16[code - eAX_reg];
12250 oappend (s);
12251 *obufp++ = close_char;
12252 *obufp = 0;
12253 }
12254
12255 static void
12256 OP_ESreg (int code, int sizeflag)
12257 {
12258 if (intel_syntax)
12259 {
12260 switch (codep[-1])
12261 {
12262 case 0x6d: /* insw/insl */
12263 intel_operand_size (z_mode, sizeflag);
12264 break;
12265 case 0xa5: /* movsw/movsl/movsq */
12266 case 0xa7: /* cmpsw/cmpsl/cmpsq */
12267 case 0xab: /* stosw/stosl */
12268 case 0xaf: /* scasw/scasl */
12269 intel_operand_size (v_mode, sizeflag);
12270 break;
12271 default:
12272 intel_operand_size (b_mode, sizeflag);
12273 }
12274 }
12275 oappend ("%es:" + intel_syntax);
12276 ptr_reg (code, sizeflag);
12277 }
12278
12279 static void
12280 OP_DSreg (int code, int sizeflag)
12281 {
12282 if (intel_syntax)
12283 {
12284 switch (codep[-1])
12285 {
12286 case 0x6f: /* outsw/outsl */
12287 intel_operand_size (z_mode, sizeflag);
12288 break;
12289 case 0xa5: /* movsw/movsl/movsq */
12290 case 0xa7: /* cmpsw/cmpsl/cmpsq */
12291 case 0xad: /* lodsw/lodsl/lodsq */
12292 intel_operand_size (v_mode, sizeflag);
12293 break;
12294 default:
12295 intel_operand_size (b_mode, sizeflag);
12296 }
12297 }
12298 if ((prefixes
12299 & (PREFIX_CS
12300 | PREFIX_DS
12301 | PREFIX_SS
12302 | PREFIX_ES
12303 | PREFIX_FS
12304 | PREFIX_GS)) == 0)
12305 prefixes |= PREFIX_DS;
12306 append_seg ();
12307 ptr_reg (code, sizeflag);
12308 }
12309
12310 static void
12311 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12312 {
12313 int add;
12314 if (rex & REX_R)
12315 {
12316 USED_REX (REX_R);
12317 add = 8;
12318 }
12319 else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
12320 {
12321 lock_prefix = NULL;
12322 used_prefixes |= PREFIX_LOCK;
12323 add = 8;
12324 }
12325 else
12326 add = 0;
12327 sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
12328 oappend (scratchbuf + intel_syntax);
12329 }
12330
12331 static void
12332 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12333 {
12334 int add;
12335 USED_REX (REX_R);
12336 if (rex & REX_R)
12337 add = 8;
12338 else
12339 add = 0;
12340 if (intel_syntax)
12341 sprintf (scratchbuf, "db%d", modrm.reg + add);
12342 else
12343 sprintf (scratchbuf, "%%db%d", modrm.reg + add);
12344 oappend (scratchbuf);
12345 }
12346
12347 static void
12348 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12349 {
12350 sprintf (scratchbuf, "%%tr%d", modrm.reg);
12351 oappend (scratchbuf + intel_syntax);
12352 }
12353
12354 static void
12355 OP_R (int bytemode, int sizeflag)
12356 {
12357 if (modrm.mod == 3)
12358 OP_E (bytemode, sizeflag);
12359 else
12360 BadOp ();
12361 }
12362
12363 static void
12364 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12365 {
12366 used_prefixes |= (prefixes & PREFIX_DATA);
12367 if (prefixes & PREFIX_DATA)
12368 {
12369 int add;
12370 USED_REX (REX_R);
12371 if (rex & REX_R)
12372 add = 8;
12373 else
12374 add = 0;
12375 sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
12376 }
12377 else
12378 sprintf (scratchbuf, "%%mm%d", modrm.reg);
12379 oappend (scratchbuf + intel_syntax);
12380 }
12381
12382 static void
12383 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
12384 {
12385 int add;
12386 USED_REX (REX_R);
12387 if (rex & REX_R)
12388 add = 8;
12389 else
12390 add = 0;
12391 if (need_vex && bytemode != xmm_mode)
12392 {
12393 switch (vex.length)
12394 {
12395 case 128:
12396 sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
12397 break;
12398 case 256:
12399 sprintf (scratchbuf, "%%ymm%d", modrm.reg + add);
12400 break;
12401 default:
12402 abort ();
12403 }
12404 }
12405 else
12406 sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
12407 oappend (scratchbuf + intel_syntax);
12408 }
12409
12410 static void
12411 OP_EM (int bytemode, int sizeflag)
12412 {
12413 if (modrm.mod != 3)
12414 {
12415 if (intel_syntax && bytemode == v_mode)
12416 {
12417 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
12418 used_prefixes |= (prefixes & PREFIX_DATA);
12419 }
12420 OP_E (bytemode, sizeflag);
12421 return;
12422 }
12423
12424 /* Skip mod/rm byte. */
12425 MODRM_CHECK;
12426 codep++;
12427 used_prefixes |= (prefixes & PREFIX_DATA);
12428 if (prefixes & PREFIX_DATA)
12429 {
12430 int add;
12431
12432 USED_REX (REX_B);
12433 if (rex & REX_B)
12434 add = 8;
12435 else
12436 add = 0;
12437 sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
12438 }
12439 else
12440 sprintf (scratchbuf, "%%mm%d", modrm.rm);
12441 oappend (scratchbuf + intel_syntax);
12442 }
12443
12444 /* cvt* are the only instructions in sse2 which have
12445 both SSE and MMX operands and also have 0x66 prefix
12446 in their opcode. 0x66 was originally used to differentiate
12447 between SSE and MMX instruction(operands). So we have to handle the
12448 cvt* separately using OP_EMC and OP_MXC */
12449 static void
12450 OP_EMC (int bytemode, int sizeflag)
12451 {
12452 if (modrm.mod != 3)
12453 {
12454 if (intel_syntax && bytemode == v_mode)
12455 {
12456 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
12457 used_prefixes |= (prefixes & PREFIX_DATA);
12458 }
12459 OP_E (bytemode, sizeflag);
12460 return;
12461 }
12462
12463 /* Skip mod/rm byte. */
12464 MODRM_CHECK;
12465 codep++;
12466 used_prefixes |= (prefixes & PREFIX_DATA);
12467 sprintf (scratchbuf, "%%mm%d", modrm.rm);
12468 oappend (scratchbuf + intel_syntax);
12469 }
12470
12471 static void
12472 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12473 {
12474 used_prefixes |= (prefixes & PREFIX_DATA);
12475 sprintf (scratchbuf, "%%mm%d", modrm.reg);
12476 oappend (scratchbuf + intel_syntax);
12477 }
12478
12479 static void
12480 OP_EX (int bytemode, int sizeflag)
12481 {
12482 int add;
12483 if (modrm.mod != 3)
12484 {
12485 OP_E (bytemode, sizeflag);
12486 return;
12487 }
12488 USED_REX (REX_B);
12489 if (rex & REX_B)
12490 add = 8;
12491 else
12492 add = 0;
12493
12494 /* Skip mod/rm byte. */
12495 MODRM_CHECK;
12496 codep++;
12497 if (need_vex
12498 && bytemode != xmm_mode
12499 && bytemode != xmmq_mode)
12500 {
12501 switch (vex.length)
12502 {
12503 case 128:
12504 sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
12505 break;
12506 case 256:
12507 sprintf (scratchbuf, "%%ymm%d", modrm.rm + add);
12508 break;
12509 default:
12510 abort ();
12511 }
12512 }
12513 else
12514 sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
12515 oappend (scratchbuf + intel_syntax);
12516 }
12517
12518 static void
12519 OP_MS (int bytemode, int sizeflag)
12520 {
12521 if (modrm.mod == 3)
12522 OP_EM (bytemode, sizeflag);
12523 else
12524 BadOp ();
12525 }
12526
12527 static void
12528 OP_XS (int bytemode, int sizeflag)
12529 {
12530 if (modrm.mod == 3)
12531 OP_EX (bytemode, sizeflag);
12532 else
12533 BadOp ();
12534 }
12535
12536 static void
12537 OP_M (int bytemode, int sizeflag)
12538 {
12539 if (modrm.mod == 3)
12540 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
12541 BadOp ();
12542 else
12543 OP_E (bytemode, sizeflag);
12544 }
12545
12546 static void
12547 OP_0f07 (int bytemode, int sizeflag)
12548 {
12549 if (modrm.mod != 3 || modrm.rm != 0)
12550 BadOp ();
12551 else
12552 OP_E (bytemode, sizeflag);
12553 }
12554
12555 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
12556 32bit mode and "xchg %rax,%rax" in 64bit mode. */
12557
12558 static void
12559 NOP_Fixup1 (int bytemode, int sizeflag)
12560 {
12561 if ((prefixes & PREFIX_DATA) != 0
12562 || (rex != 0
12563 && rex != 0x48
12564 && address_mode == mode_64bit))
12565 OP_REG (bytemode, sizeflag);
12566 else
12567 strcpy (obuf, "nop");
12568 }
12569
12570 static void
12571 NOP_Fixup2 (int bytemode, int sizeflag)
12572 {
12573 if ((prefixes & PREFIX_DATA) != 0
12574 || (rex != 0
12575 && rex != 0x48
12576 && address_mode == mode_64bit))
12577 OP_IMREG (bytemode, sizeflag);
12578 }
12579
12580 static const char *const Suffix3DNow[] = {
12581 /* 00 */ NULL, NULL, NULL, NULL,
12582 /* 04 */ NULL, NULL, NULL, NULL,
12583 /* 08 */ NULL, NULL, NULL, NULL,
12584 /* 0C */ "pi2fw", "pi2fd", NULL, NULL,
12585 /* 10 */ NULL, NULL, NULL, NULL,
12586 /* 14 */ NULL, NULL, NULL, NULL,
12587 /* 18 */ NULL, NULL, NULL, NULL,
12588 /* 1C */ "pf2iw", "pf2id", NULL, NULL,
12589 /* 20 */ NULL, NULL, NULL, NULL,
12590 /* 24 */ NULL, NULL, NULL, NULL,
12591 /* 28 */ NULL, NULL, NULL, NULL,
12592 /* 2C */ NULL, NULL, NULL, NULL,
12593 /* 30 */ NULL, NULL, NULL, NULL,
12594 /* 34 */ NULL, NULL, NULL, NULL,
12595 /* 38 */ NULL, NULL, NULL, NULL,
12596 /* 3C */ NULL, NULL, NULL, NULL,
12597 /* 40 */ NULL, NULL, NULL, NULL,
12598 /* 44 */ NULL, NULL, NULL, NULL,
12599 /* 48 */ NULL, NULL, NULL, NULL,
12600 /* 4C */ NULL, NULL, NULL, NULL,
12601 /* 50 */ NULL, NULL, NULL, NULL,
12602 /* 54 */ NULL, NULL, NULL, NULL,
12603 /* 58 */ NULL, NULL, NULL, NULL,
12604 /* 5C */ NULL, NULL, NULL, NULL,
12605 /* 60 */ NULL, NULL, NULL, NULL,
12606 /* 64 */ NULL, NULL, NULL, NULL,
12607 /* 68 */ NULL, NULL, NULL, NULL,
12608 /* 6C */ NULL, NULL, NULL, NULL,
12609 /* 70 */ NULL, NULL, NULL, NULL,
12610 /* 74 */ NULL, NULL, NULL, NULL,
12611 /* 78 */ NULL, NULL, NULL, NULL,
12612 /* 7C */ NULL, NULL, NULL, NULL,
12613 /* 80 */ NULL, NULL, NULL, NULL,
12614 /* 84 */ NULL, NULL, NULL, NULL,
12615 /* 88 */ NULL, NULL, "pfnacc", NULL,
12616 /* 8C */ NULL, NULL, "pfpnacc", NULL,
12617 /* 90 */ "pfcmpge", NULL, NULL, NULL,
12618 /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt",
12619 /* 98 */ NULL, NULL, "pfsub", NULL,
12620 /* 9C */ NULL, NULL, "pfadd", NULL,
12621 /* A0 */ "pfcmpgt", NULL, NULL, NULL,
12622 /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1",
12623 /* A8 */ NULL, NULL, "pfsubr", NULL,
12624 /* AC */ NULL, NULL, "pfacc", NULL,
12625 /* B0 */ "pfcmpeq", NULL, NULL, NULL,
12626 /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw",
12627 /* B8 */ NULL, NULL, NULL, "pswapd",
12628 /* BC */ NULL, NULL, NULL, "pavgusb",
12629 /* C0 */ NULL, NULL, NULL, NULL,
12630 /* C4 */ NULL, NULL, NULL, NULL,
12631 /* C8 */ NULL, NULL, NULL, NULL,
12632 /* CC */ NULL, NULL, NULL, NULL,
12633 /* D0 */ NULL, NULL, NULL, NULL,
12634 /* D4 */ NULL, NULL, NULL, NULL,
12635 /* D8 */ NULL, NULL, NULL, NULL,
12636 /* DC */ NULL, NULL, NULL, NULL,
12637 /* E0 */ NULL, NULL, NULL, NULL,
12638 /* E4 */ NULL, NULL, NULL, NULL,
12639 /* E8 */ NULL, NULL, NULL, NULL,
12640 /* EC */ NULL, NULL, NULL, NULL,
12641 /* F0 */ NULL, NULL, NULL, NULL,
12642 /* F4 */ NULL, NULL, NULL, NULL,
12643 /* F8 */ NULL, NULL, NULL, NULL,
12644 /* FC */ NULL, NULL, NULL, NULL,
12645 };
12646
12647 static void
12648 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12649 {
12650 const char *mnemonic;
12651
12652 FETCH_DATA (the_info, codep + 1);
12653 /* AMD 3DNow! instructions are specified by an opcode suffix in the
12654 place where an 8-bit immediate would normally go. ie. the last
12655 byte of the instruction. */
12656 obufp = obuf + strlen (obuf);
12657 mnemonic = Suffix3DNow[*codep++ & 0xff];
12658 if (mnemonic)
12659 oappend (mnemonic);
12660 else
12661 {
12662 /* Since a variable sized modrm/sib chunk is between the start
12663 of the opcode (0x0f0f) and the opcode suffix, we need to do
12664 all the modrm processing first, and don't know until now that
12665 we have a bad opcode. This necessitates some cleaning up. */
12666 op_out[0][0] = '\0';
12667 op_out[1][0] = '\0';
12668 BadOp ();
12669 }
12670 }
12671
12672 static const char *simd_cmp_op[] = {
12673 "eq",
12674 "lt",
12675 "le",
12676 "unord",
12677 "neq",
12678 "nlt",
12679 "nle",
12680 "ord"
12681 };
12682
12683 static void
12684 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12685 {
12686 unsigned int cmp_type;
12687
12688 FETCH_DATA (the_info, codep + 1);
12689 cmp_type = *codep++ & 0xff;
12690 if (cmp_type < ARRAY_SIZE (simd_cmp_op))
12691 {
12692 char suffix [3];
12693 char *p = obuf + strlen (obuf) - 2;
12694 suffix[0] = p[0];
12695 suffix[1] = p[1];
12696 suffix[2] = '\0';
12697 sprintf (p, "%s%s", simd_cmp_op[cmp_type], suffix);
12698 }
12699 else
12700 {
12701 /* We have a reserved extension byte. Output it directly. */
12702 scratchbuf[0] = '$';
12703 print_operand_value (scratchbuf + 1, 1, cmp_type);
12704 oappend (scratchbuf + intel_syntax);
12705 scratchbuf[0] = '\0';
12706 }
12707 }
12708
12709 static void
12710 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
12711 int sizeflag ATTRIBUTE_UNUSED)
12712 {
12713 /* mwait %eax,%ecx */
12714 if (!intel_syntax)
12715 {
12716 const char **names = (address_mode == mode_64bit
12717 ? names64 : names32);
12718 strcpy (op_out[0], names[0]);
12719 strcpy (op_out[1], names[1]);
12720 two_source_ops = 1;
12721 }
12722 /* Skip mod/rm byte. */
12723 MODRM_CHECK;
12724 codep++;
12725 }
12726
12727 static void
12728 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
12729 int sizeflag ATTRIBUTE_UNUSED)
12730 {
12731 /* monitor %eax,%ecx,%edx" */
12732 if (!intel_syntax)
12733 {
12734 const char **op1_names;
12735 const char **names = (address_mode == mode_64bit
12736 ? names64 : names32);
12737
12738 if (!(prefixes & PREFIX_ADDR))
12739 op1_names = (address_mode == mode_16bit
12740 ? names16 : names);
12741 else
12742 {
12743 /* Remove "addr16/addr32". */
12744 addr_prefix = NULL;
12745 op1_names = (address_mode != mode_32bit
12746 ? names32 : names16);
12747 used_prefixes |= PREFIX_ADDR;
12748 }
12749 strcpy (op_out[0], op1_names[0]);
12750 strcpy (op_out[1], names[1]);
12751 strcpy (op_out[2], names[2]);
12752 two_source_ops = 1;
12753 }
12754 /* Skip mod/rm byte. */
12755 MODRM_CHECK;
12756 codep++;
12757 }
12758
12759 static void
12760 BadOp (void)
12761 {
12762 /* Throw away prefixes and 1st. opcode byte. */
12763 codep = insn_codep + 1;
12764 oappend ("(bad)");
12765 }
12766
12767 static void
12768 REP_Fixup (int bytemode, int sizeflag)
12769 {
12770 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
12771 lods and stos. */
12772 if (prefixes & PREFIX_REPZ)
12773 repz_prefix = "rep ";
12774
12775 switch (bytemode)
12776 {
12777 case al_reg:
12778 case eAX_reg:
12779 case indir_dx_reg:
12780 OP_IMREG (bytemode, sizeflag);
12781 break;
12782 case eDI_reg:
12783 OP_ESreg (bytemode, sizeflag);
12784 break;
12785 case eSI_reg:
12786 OP_DSreg (bytemode, sizeflag);
12787 break;
12788 default:
12789 abort ();
12790 break;
12791 }
12792 }
12793
12794 static void
12795 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
12796 {
12797 USED_REX (REX_W);
12798 if (rex & REX_W)
12799 {
12800 /* Change cmpxchg8b to cmpxchg16b. */
12801 char *p = obuf + strlen (obuf) - 2;
12802 strcpy (p, "16b");
12803 bytemode = o_mode;
12804 }
12805 OP_M (bytemode, sizeflag);
12806 }
12807
12808 static void
12809 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
12810 {
12811 if (need_vex)
12812 {
12813 switch (vex.length)
12814 {
12815 case 128:
12816 sprintf (scratchbuf, "%%xmm%d", reg);
12817 break;
12818 case 256:
12819 sprintf (scratchbuf, "%%ymm%d", reg);
12820 break;
12821 default:
12822 abort ();
12823 }
12824 }
12825 else
12826 sprintf (scratchbuf, "%%xmm%d", reg);
12827 oappend (scratchbuf + intel_syntax);
12828 }
12829
12830 static void
12831 CRC32_Fixup (int bytemode, int sizeflag)
12832 {
12833 /* Add proper suffix to "crc32". */
12834 char *p = obuf + strlen (obuf);
12835
12836 switch (bytemode)
12837 {
12838 case b_mode:
12839 if (intel_syntax)
12840 break;
12841
12842 *p++ = 'b';
12843 break;
12844 case v_mode:
12845 if (intel_syntax)
12846 break;
12847
12848 USED_REX (REX_W);
12849 if (rex & REX_W)
12850 *p++ = 'q';
12851 else if (sizeflag & DFLAG)
12852 *p++ = 'l';
12853 else
12854 *p++ = 'w';
12855 used_prefixes |= (prefixes & PREFIX_DATA);
12856 break;
12857 default:
12858 oappend (INTERNAL_DISASSEMBLER_ERROR);
12859 break;
12860 }
12861 *p = '\0';
12862
12863 if (modrm.mod == 3)
12864 {
12865 int add;
12866
12867 /* Skip mod/rm byte. */
12868 MODRM_CHECK;
12869 codep++;
12870
12871 USED_REX (REX_B);
12872 add = (rex & REX_B) ? 8 : 0;
12873 if (bytemode == b_mode)
12874 {
12875 USED_REX (0);
12876 if (rex)
12877 oappend (names8rex[modrm.rm + add]);
12878 else
12879 oappend (names8[modrm.rm + add]);
12880 }
12881 else
12882 {
12883 USED_REX (REX_W);
12884 if (rex & REX_W)
12885 oappend (names64[modrm.rm + add]);
12886 else if ((prefixes & PREFIX_DATA))
12887 oappend (names16[modrm.rm + add]);
12888 else
12889 oappend (names32[modrm.rm + add]);
12890 }
12891 }
12892 else
12893 OP_E (bytemode, sizeflag);
12894 }
12895
12896 /* Print a DREX argument as either a register or memory operation. */
12897 static void
12898 print_drex_arg (unsigned int reg, int bytemode, int sizeflag)
12899 {
12900 if (reg == DREX_REG_UNKNOWN)
12901 BadOp ();
12902
12903 else if (reg != DREX_REG_MEMORY)
12904 {
12905 sprintf (scratchbuf, "%%xmm%d", reg);
12906 oappend (scratchbuf + intel_syntax);
12907 }
12908
12909 else
12910 OP_E_extended (bytemode, sizeflag, 1);
12911 }
12912
12913 /* SSE5 instructions that have 4 arguments are encoded as:
12914 0f 24 <sub-opcode> <modrm> <optional-sib> <drex> <offset>.
12915
12916 The <sub-opcode> byte has 1 bit (0x4) that is combined with 1 bit in
12917 the DREX field (0x8) to determine how the arguments are laid out.
12918 The destination register must be the same register as one of the
12919 inputs, and it is encoded in the DREX byte. No REX prefix is used
12920 for these instructions, since the DREX field contains the 3 extension
12921 bits provided by the REX prefix.
12922
12923 The bytemode argument adds 2 extra bits for passing extra information:
12924 DREX_OC1 -- Set the OC1 bit to indicate dest == 1st arg
12925 DREX_NO_OC0 -- OC0 in DREX is invalid
12926 (but pretend it is set). */
12927
12928 static void
12929 OP_DREX4 (int flag_bytemode, int sizeflag)
12930 {
12931 unsigned int drex_byte;
12932 unsigned int regs[4];
12933 unsigned int modrm_regmem;
12934 unsigned int modrm_reg;
12935 unsigned int drex_reg;
12936 int bytemode;
12937 int rex_save = rex;
12938 int rex_used_save = rex_used;
12939 int has_sib = 0;
12940 int oc1 = (flag_bytemode & DREX_OC1) ? 2 : 0;
12941 int oc0;
12942 int i;
12943
12944 bytemode = flag_bytemode & ~ DREX_MASK;
12945
12946 for (i = 0; i < 4; i++)
12947 regs[i] = DREX_REG_UNKNOWN;
12948
12949 /* Determine if we have a SIB byte in addition to MODRM before the
12950 DREX byte. */
12951 if (((sizeflag & AFLAG) || address_mode == mode_64bit)
12952 && (modrm.mod != 3)
12953 && (modrm.rm == 4))
12954 has_sib = 1;
12955
12956 /* Get the DREX byte. */
12957 FETCH_DATA (the_info, codep + 2 + has_sib);
12958 drex_byte = codep[has_sib+1];
12959 drex_reg = DREX_XMM (drex_byte);
12960 modrm_reg = modrm.reg + ((drex_byte & REX_R) ? 8 : 0);
12961
12962 /* Is OC0 legal? If not, hardwire oc0 == 1. */
12963 if (flag_bytemode & DREX_NO_OC0)
12964 {
12965 oc0 = 1;
12966 if (DREX_OC0 (drex_byte))
12967 BadOp ();
12968 }
12969 else
12970 oc0 = DREX_OC0 (drex_byte);
12971
12972 if (modrm.mod == 3)
12973 {
12974 /* regmem == register */
12975 modrm_regmem = modrm.rm + ((drex_byte & REX_B) ? 8 : 0);
12976 rex = rex_used = 0;
12977 /* skip modrm/drex since we don't call OP_E_extended */
12978 codep += 2;
12979 }
12980 else
12981 {
12982 /* regmem == memory, fill in appropriate REX bits */
12983 modrm_regmem = DREX_REG_MEMORY;
12984 rex = drex_byte & (REX_B | REX_X | REX_R);
12985 if (rex)
12986 rex |= REX_OPCODE;
12987 rex_used = rex;
12988 }
12989
12990 /* Based on the OC1/OC0 bits, lay out the arguments in the correct
12991 order. */
12992 switch (oc0 + oc1)
12993 {
12994 default:
12995 BadOp ();
12996 return;
12997
12998 case 0:
12999 regs[0] = modrm_regmem;
13000 regs[1] = modrm_reg;
13001 regs[2] = drex_reg;
13002 regs[3] = drex_reg;
13003 break;
13004
13005 case 1:
13006 regs[0] = modrm_reg;
13007 regs[1] = modrm_regmem;
13008 regs[2] = drex_reg;
13009 regs[3] = drex_reg;
13010 break;
13011
13012 case 2:
13013 regs[0] = drex_reg;
13014 regs[1] = modrm_regmem;
13015 regs[2] = modrm_reg;
13016 regs[3] = drex_reg;
13017 break;
13018
13019 case 3:
13020 regs[0] = drex_reg;
13021 regs[1] = modrm_reg;
13022 regs[2] = modrm_regmem;
13023 regs[3] = drex_reg;
13024 break;
13025 }
13026
13027 /* Print out the arguments. */
13028 for (i = 0; i < 4; i++)
13029 {
13030 int j = (intel_syntax) ? 3 - i : i;
13031 if (i > 0)
13032 {
13033 *obufp++ = ',';
13034 *obufp = '\0';
13035 }
13036
13037 print_drex_arg (regs[j], bytemode, sizeflag);
13038 }
13039
13040 rex = rex_save;
13041 rex_used = rex_used_save;
13042 }
13043
13044 /* SSE5 instructions that have 3 arguments, and are encoded as:
13045 0f 24 <sub-opcode> <modrm> <optional-sib> <drex> <offset> (or)
13046 0f 25 <sub-opcode> <modrm> <optional-sib> <drex> <offset> <cmp-byte>
13047
13048 The DREX field has 1 bit (0x8) to determine how the arguments are
13049 laid out. The destination register is encoded in the DREX byte.
13050 No REX prefix is used for these instructions, since the DREX field
13051 contains the 3 extension bits provided by the REX prefix. */
13052
13053 static void
13054 OP_DREX3 (int flag_bytemode, int sizeflag)
13055 {
13056 unsigned int drex_byte;
13057 unsigned int regs[3];
13058 unsigned int modrm_regmem;
13059 unsigned int modrm_reg;
13060 unsigned int drex_reg;
13061 int bytemode;
13062 int rex_save = rex;
13063 int rex_used_save = rex_used;
13064 int has_sib = 0;
13065 int oc0;
13066 int i;
13067
13068 bytemode = flag_bytemode & ~ DREX_MASK;
13069
13070 for (i = 0; i < 3; i++)
13071 regs[i] = DREX_REG_UNKNOWN;
13072
13073 /* Determine if we have a SIB byte in addition to MODRM before the
13074 DREX byte. */
13075 if (((sizeflag & AFLAG) || address_mode == mode_64bit)
13076 && (modrm.mod != 3)
13077 && (modrm.rm == 4))
13078 has_sib = 1;
13079
13080 /* Get the DREX byte. */
13081 FETCH_DATA (the_info, codep + 2 + has_sib);
13082 drex_byte = codep[has_sib+1];
13083 drex_reg = DREX_XMM (drex_byte);
13084 modrm_reg = modrm.reg + ((drex_byte & REX_R) ? 8 : 0);
13085
13086 /* Is OC0 legal? If not, hardwire oc0 == 0 */
13087 oc0 = DREX_OC0 (drex_byte);
13088 if ((flag_bytemode & DREX_NO_OC0) && oc0)
13089 BadOp ();
13090
13091 if (modrm.mod == 3)
13092 {
13093 /* regmem == register */
13094 modrm_regmem = modrm.rm + ((drex_byte & REX_B) ? 8 : 0);
13095 rex = rex_used = 0;
13096 /* skip modrm/drex since we don't call OP_E_extended. */
13097 codep += 2;
13098 }
13099 else
13100 {
13101 /* regmem == memory, fill in appropriate REX bits. */
13102 modrm_regmem = DREX_REG_MEMORY;
13103 rex = drex_byte & (REX_B | REX_X | REX_R);
13104 if (rex)
13105 rex |= REX_OPCODE;
13106 rex_used = rex;
13107 }
13108
13109 /* Based on the OC1/OC0 bits, lay out the arguments in the correct
13110 order. */
13111 switch (oc0)
13112 {
13113 default:
13114 BadOp ();
13115 return;
13116
13117 case 0:
13118 regs[0] = modrm_regmem;
13119 regs[1] = modrm_reg;
13120 regs[2] = drex_reg;
13121 break;
13122
13123 case 1:
13124 regs[0] = modrm_reg;
13125 regs[1] = modrm_regmem;
13126 regs[2] = drex_reg;
13127 break;
13128 }
13129
13130 /* Print out the arguments. */
13131 for (i = 0; i < 3; i++)
13132 {
13133 int j = (intel_syntax) ? 2 - i : i;
13134 if (i > 0)
13135 {
13136 *obufp++ = ',';
13137 *obufp = '\0';
13138 }
13139
13140 print_drex_arg (regs[j], bytemode, sizeflag);
13141 }
13142
13143 rex = rex_save;
13144 rex_used = rex_used_save;
13145 }
13146
13147 /* Emit a floating point comparison for comp<xx> instructions. */
13148
13149 static void
13150 OP_DREX_FCMP (int bytemode ATTRIBUTE_UNUSED,
13151 int sizeflag ATTRIBUTE_UNUSED)
13152 {
13153 unsigned char byte;
13154
13155 static const char *const cmp_test[] = {
13156 "eq",
13157 "lt",
13158 "le",
13159 "unord",
13160 "ne",
13161 "nlt",
13162 "nle",
13163 "ord",
13164 "ueq",
13165 "ult",
13166 "ule",
13167 "false",
13168 "une",
13169 "unlt",
13170 "unle",
13171 "true"
13172 };
13173
13174 FETCH_DATA (the_info, codep + 1);
13175 byte = *codep & 0xff;
13176
13177 if (byte >= ARRAY_SIZE (cmp_test)
13178 || obuf[0] != 'c'
13179 || obuf[1] != 'o'
13180 || obuf[2] != 'm')
13181 {
13182 /* The instruction isn't one we know about, so just append the
13183 extension byte as a numeric value. */
13184 OP_I (b_mode, 0);
13185 }
13186
13187 else
13188 {
13189 sprintf (scratchbuf, "com%s%s", cmp_test[byte], obuf+3);
13190 strcpy (obuf, scratchbuf);
13191 codep++;
13192 }
13193 }
13194
13195 /* Emit an integer point comparison for pcom<xx> instructions,
13196 rewriting the instruction to have the test inside of it. */
13197
13198 static void
13199 OP_DREX_ICMP (int bytemode ATTRIBUTE_UNUSED,
13200 int sizeflag ATTRIBUTE_UNUSED)
13201 {
13202 unsigned char byte;
13203
13204 static const char *const cmp_test[] = {
13205 "lt",
13206 "le",
13207 "gt",
13208 "ge",
13209 "eq",
13210 "ne",
13211 "false",
13212 "true"
13213 };
13214
13215 FETCH_DATA (the_info, codep + 1);
13216 byte = *codep & 0xff;
13217
13218 if (byte >= ARRAY_SIZE (cmp_test)
13219 || obuf[0] != 'p'
13220 || obuf[1] != 'c'
13221 || obuf[2] != 'o'
13222 || obuf[3] != 'm')
13223 {
13224 /* The instruction isn't one we know about, so just print the
13225 comparison test byte as a numeric value. */
13226 OP_I (b_mode, 0);
13227 }
13228
13229 else
13230 {
13231 sprintf (scratchbuf, "pcom%s%s", cmp_test[byte], obuf+4);
13232 strcpy (obuf, scratchbuf);
13233 codep++;
13234 }
13235 }
13236
13237 /* Display the destination register operand for instructions with
13238 VEX. */
13239
13240 static void
13241 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13242 {
13243 if (!need_vex)
13244 abort ();
13245
13246 if (!need_vex_reg)
13247 return;
13248
13249 switch (vex.length)
13250 {
13251 case 128:
13252 switch (bytemode)
13253 {
13254 case vex_mode:
13255 case vex128_mode:
13256 break;
13257 default:
13258 abort ();
13259 return;
13260 }
13261
13262 sprintf (scratchbuf, "%%xmm%d", vex.register_specifier);
13263 break;
13264 case 256:
13265 switch (bytemode)
13266 {
13267 case vex_mode:
13268 case vex256_mode:
13269 break;
13270 default:
13271 abort ();
13272 return;
13273 }
13274
13275 sprintf (scratchbuf, "%%ymm%d", vex.register_specifier);
13276 break;
13277 default:
13278 abort ();
13279 break;
13280 }
13281 oappend (scratchbuf + intel_syntax);
13282 }
13283
13284 /* Get the VEX immediate byte without moving codep. */
13285
13286 static unsigned char
13287 get_vex_imm8 (int sizeflag)
13288 {
13289 int bytes_before_imm = 0;
13290
13291 /* Skip mod/rm byte. */
13292 MODRM_CHECK;
13293 codep++;
13294
13295 if (modrm.mod != 3)
13296 {
13297 /* There are SIB/displacement bytes. */
13298 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
13299 {
13300 /* 32/64 bit address mode */
13301 int base = modrm.rm;
13302
13303 /* Check SIB byte. */
13304 if (base == 4)
13305 {
13306 FETCH_DATA (the_info, codep + 1);
13307 base = *codep & 7;
13308 bytes_before_imm++;
13309 }
13310
13311 switch (modrm.mod)
13312 {
13313 case 0:
13314 /* When modrm.rm == 5 or modrm.rm == 4 and base in
13315 SIB == 5, there is a 4 byte displacement. */
13316 if (base != 5)
13317 /* No displacement. */
13318 break;
13319 case 2:
13320 /* 4 byte displacement. */
13321 bytes_before_imm += 4;
13322 break;
13323 case 1:
13324 /* 1 byte displacement. */
13325 bytes_before_imm++;
13326 break;
13327 }
13328 }
13329 else
13330 { /* 16 bit address mode */
13331 switch (modrm.mod)
13332 {
13333 case 0:
13334 /* When modrm.rm == 6, there is a 2 byte displacement. */
13335 if (modrm.rm != 6)
13336 /* No displacement. */
13337 break;
13338 case 2:
13339 /* 2 byte displacement. */
13340 bytes_before_imm += 2;
13341 break;
13342 case 1:
13343 /* 1 byte displacement. */
13344 bytes_before_imm++;
13345 break;
13346 }
13347 }
13348 }
13349
13350 FETCH_DATA (the_info, codep + bytes_before_imm + 1);
13351 return codep [bytes_before_imm];
13352 }
13353
13354 static void
13355 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
13356 {
13357 if (reg == -1 && modrm.mod != 3)
13358 {
13359 OP_E_memory (bytemode, sizeflag, 0);
13360 return;
13361 }
13362 else
13363 {
13364 if (reg == -1)
13365 {
13366 reg = modrm.rm;
13367 USED_REX (REX_B);
13368 if (rex & REX_B)
13369 reg += 8;
13370 }
13371 else if (reg > 7 && address_mode != mode_64bit)
13372 BadOp ();
13373 }
13374
13375 switch (vex.length)
13376 {
13377 case 128:
13378 sprintf (scratchbuf, "%%xmm%d", reg);
13379 break;
13380 case 256:
13381 sprintf (scratchbuf, "%%ymm%d", reg);
13382 break;
13383 default:
13384 abort ();
13385 }
13386 oappend (scratchbuf + intel_syntax);
13387 }
13388
13389 static void
13390 OP_EX_VexImmW (int bytemode, int sizeflag)
13391 {
13392 int reg = -1;
13393 static unsigned char vex_imm8;
13394
13395 if (!vex_w_done)
13396 {
13397 vex_imm8 = get_vex_imm8 (sizeflag);
13398 if (vex.w)
13399 reg = vex_imm8 >> 4;
13400 vex_w_done = 1;
13401 }
13402 else
13403 {
13404 if (!vex.w)
13405 reg = vex_imm8 >> 4;
13406 }
13407
13408 OP_EX_VexReg (bytemode, sizeflag, reg);
13409 }
13410
13411 static void
13412 OP_EX_VexW (int bytemode, int sizeflag)
13413 {
13414 int reg = -1;
13415
13416 if (!vex_w_done)
13417 {
13418 vex_w_done = 1;
13419 if (vex.w)
13420 reg = vex.register_specifier;
13421 }
13422 else
13423 {
13424 if (!vex.w)
13425 reg = vex.register_specifier;
13426 }
13427
13428 OP_EX_VexReg (bytemode, sizeflag, reg);
13429 }
13430
13431 static void
13432 OP_VEX_FMA (int bytemode, int sizeflag)
13433 {
13434 int reg = get_vex_imm8 (sizeflag) >> 4;
13435
13436 if (reg > 7 && address_mode != mode_64bit)
13437 BadOp ();
13438
13439 switch (vex.length)
13440 {
13441 case 128:
13442 switch (bytemode)
13443 {
13444 case vex_mode:
13445 case vex128_mode:
13446 break;
13447 default:
13448 abort ();
13449 return;
13450 }
13451
13452 sprintf (scratchbuf, "%%xmm%d", reg);
13453 break;
13454 case 256:
13455 switch (bytemode)
13456 {
13457 case vex_mode:
13458 break;
13459 default:
13460 abort ();
13461 return;
13462 }
13463
13464 sprintf (scratchbuf, "%%ymm%d", reg);
13465 break;
13466 default:
13467 abort ();
13468 }
13469 oappend (scratchbuf + intel_syntax);
13470 }
13471
13472 static void
13473 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
13474 int sizeflag ATTRIBUTE_UNUSED)
13475 {
13476 /* Skip the immediate byte and check for invalid bits. */
13477 FETCH_DATA (the_info, codep + 1);
13478 if (*codep++ & 0xf)
13479 BadOp ();
13480 }
13481
13482 static void
13483 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13484 {
13485 int reg;
13486 FETCH_DATA (the_info, codep + 1);
13487 reg = *codep++;
13488
13489 if (bytemode != x_mode)
13490 abort ();
13491
13492 if (reg & 0xf)
13493 BadOp ();
13494
13495 reg >>= 4;
13496 if (reg > 7 && address_mode != mode_64bit)
13497 BadOp ();
13498
13499 switch (vex.length)
13500 {
13501 case 128:
13502 sprintf (scratchbuf, "%%xmm%d", reg);
13503 break;
13504 case 256:
13505 sprintf (scratchbuf, "%%ymm%d", reg);
13506 break;
13507 default:
13508 abort ();
13509 }
13510 oappend (scratchbuf + intel_syntax);
13511 }
13512
13513 static void
13514 OP_XMM_VexW (int bytemode, int sizeflag)
13515 {
13516 /* Turn off the REX.W bit since it is used for swapping operands
13517 now. */
13518 rex &= ~REX_W;
13519 OP_XMM (bytemode, sizeflag);
13520 }
13521
13522 static void
13523 OP_EX_Vex (int bytemode, int sizeflag)
13524 {
13525 if (modrm.mod != 3)
13526 {
13527 if (vex.register_specifier != 0)
13528 BadOp ();
13529 need_vex_reg = 0;
13530 }
13531 OP_EX (bytemode, sizeflag);
13532 }
13533
13534 static void
13535 OP_XMM_Vex (int bytemode, int sizeflag)
13536 {
13537 if (modrm.mod != 3)
13538 {
13539 if (vex.register_specifier != 0)
13540 BadOp ();
13541 need_vex_reg = 0;
13542 }
13543 OP_XMM (bytemode, sizeflag);
13544 }
13545
13546 static void
13547 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13548 {
13549 switch (vex.length)
13550 {
13551 case 128:
13552 strcpy (obuf, "vzeroupper");
13553 break;
13554 case 256:
13555 strcpy (obuf, "vzeroall");
13556 break;
13557 default:
13558 abort ();
13559 }
13560 }
13561
13562 static const char *vex_cmp_op[] = {
13563 "eq",
13564 "lt",
13565 "le",
13566 "unord",
13567 "neq",
13568 "nlt",
13569 "nle",
13570 "ord",
13571 "eq_uq",
13572 "nge",
13573 "ngt",
13574 "false",
13575 "neq_oq",
13576 "ge",
13577 "gt",
13578 "true",
13579 "eq_os",
13580 "lt_oq",
13581 "le_oq",
13582 "unord_s",
13583 "neq_us",
13584 "nlt_uq",
13585 "nle_uq",
13586 "ord_s",
13587 "eq_us",
13588 "nge_uq",
13589 "ngt_uq",
13590 "false_os",
13591 "neq_os",
13592 "ge_oq",
13593 "gt_oq",
13594 "true_us"
13595 };
13596
13597 static void
13598 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13599 {
13600 unsigned int cmp_type;
13601
13602 FETCH_DATA (the_info, codep + 1);
13603 cmp_type = *codep++ & 0xff;
13604 if (cmp_type < ARRAY_SIZE (vex_cmp_op))
13605 {
13606 char suffix [3];
13607 char *p = obuf + strlen (obuf) - 2;
13608 suffix[0] = p[0];
13609 suffix[1] = p[1];
13610 suffix[2] = '\0';
13611 sprintf (p, "%s%s", vex_cmp_op[cmp_type], suffix);
13612 }
13613 else
13614 {
13615 /* We have a reserved extension byte. Output it directly. */
13616 scratchbuf[0] = '$';
13617 print_operand_value (scratchbuf + 1, 1, cmp_type);
13618 oappend (scratchbuf + intel_syntax);
13619 scratchbuf[0] = '\0';
13620 }
13621 }
13622
13623 static const char *pclmul_op[] = {
13624 "lql",
13625 "hql",
13626 "lqh",
13627 "hqh"
13628 };
13629
13630 static void
13631 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
13632 int sizeflag ATTRIBUTE_UNUSED)
13633 {
13634 unsigned int pclmul_type;
13635
13636 FETCH_DATA (the_info, codep + 1);
13637 pclmul_type = *codep++ & 0xff;
13638 switch (pclmul_type)
13639 {
13640 case 0x10:
13641 pclmul_type = 2;
13642 break;
13643 case 0x11:
13644 pclmul_type = 3;
13645 break;
13646 default:
13647 break;
13648 }
13649 if (pclmul_type < ARRAY_SIZE (pclmul_op))
13650 {
13651 char suffix [4];
13652 char *p = obuf + strlen (obuf) - 3;
13653 suffix[0] = p[0];
13654 suffix[1] = p[1];
13655 suffix[2] = p[2];
13656 suffix[3] = '\0';
13657 sprintf (p, "%s%s", pclmul_op[pclmul_type], suffix);
13658 }
13659 else
13660 {
13661 /* We have a reserved extension byte. Output it directly. */
13662 scratchbuf[0] = '$';
13663 print_operand_value (scratchbuf + 1, 1, pclmul_type);
13664 oappend (scratchbuf + intel_syntax);
13665 scratchbuf[0] = '\0';
13666 }
13667 }
13668
13669 static const char *vpermil2_op[] = {
13670 "td",
13671 "td",
13672 "mo",
13673 "mz"
13674 };
13675
13676 static void
13677 VPERMIL2_Fixup (int bytemode ATTRIBUTE_UNUSED,
13678 int sizeflag ATTRIBUTE_UNUSED)
13679 {
13680 unsigned int vpermil2_type;
13681
13682 FETCH_DATA (the_info, codep + 1);
13683 vpermil2_type = *codep++ & 0xf;
13684 if (vpermil2_type < ARRAY_SIZE (vpermil2_op))
13685 {
13686 char suffix [4];
13687 char *p = obuf + strlen (obuf) - 3;
13688 suffix[0] = p[0];
13689 suffix[1] = p[1];
13690 suffix[2] = p[2];
13691 suffix[3] = '\0';
13692 sprintf (p, "%s%s", vpermil2_op[vpermil2_type], suffix);
13693 }
13694 else
13695 {
13696 /* We have a reserved extension byte. Output it directly. */
13697 scratchbuf[0] = '$';
13698 print_operand_value (scratchbuf + 1, 1, vpermil2_type);
13699 oappend (scratchbuf + intel_syntax);
13700 scratchbuf[0] = '\0';
13701 }
13702 }