1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2020 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
36 #include "disassemble.h"
38 #include "opcode/i386.h"
39 #include "libiberty.h"
40 #include "safe-ctype.h"
44 static int print_insn (bfd_vma
, disassemble_info
*);
45 static void dofloat (int);
46 static void OP_ST (int, int);
47 static void OP_STi (int, int);
48 static int putop (const char *, int);
49 static void oappend (const char *);
50 static void append_seg (void);
51 static void OP_indirE (int, int);
52 static void print_operand_value (char *, int, bfd_vma
);
53 static void OP_E_register (int, int);
54 static void OP_E_memory (int, int);
55 static void print_displacement (char *, bfd_vma
);
56 static void OP_E (int, int);
57 static void OP_G (int, int);
58 static bfd_vma
get64 (void);
59 static bfd_signed_vma
get32 (void);
60 static bfd_signed_vma
get32s (void);
61 static int get16 (void);
62 static void set_op (bfd_vma
, int);
63 static void OP_Skip_MODRM (int, int);
64 static void OP_REG (int, int);
65 static void OP_IMREG (int, int);
66 static void OP_I (int, int);
67 static void OP_I64 (int, int);
68 static void OP_sI (int, int);
69 static void OP_J (int, int);
70 static void OP_SEG (int, int);
71 static void OP_DIR (int, int);
72 static void OP_OFF (int, int);
73 static void OP_OFF64 (int, int);
74 static void ptr_reg (int, int);
75 static void OP_ESreg (int, int);
76 static void OP_DSreg (int, int);
77 static void OP_C (int, int);
78 static void OP_D (int, int);
79 static void OP_T (int, int);
80 static void OP_R (int, int);
81 static void OP_MMX (int, int);
82 static void OP_XMM (int, int);
83 static void OP_EM (int, int);
84 static void OP_EX (int, int);
85 static void OP_EMC (int,int);
86 static void OP_MXC (int,int);
87 static void OP_MS (int, int);
88 static void OP_XS (int, int);
89 static void OP_M (int, int);
90 static void OP_VEX (int, int);
91 static void OP_EX_Vex (int, int);
92 static void OP_EX_VexW (int, int);
93 static void OP_EX_VexImmW (int, int);
94 static void OP_XMM_Vex (int, int);
95 static void OP_XMM_VexW (int, int);
96 static void OP_Rounding (int, int);
97 static void OP_REG_VexI4 (int, int);
98 static void PCLMUL_Fixup (int, int);
99 static void VCMP_Fixup (int, int);
100 static void VPCMP_Fixup (int, int);
101 static void VPCOM_Fixup (int, int);
102 static void OP_0f07 (int, int);
103 static void OP_Monitor (int, int);
104 static void OP_Mwait (int, int);
105 static void NOP_Fixup1 (int, int);
106 static void NOP_Fixup2 (int, int);
107 static void OP_3DNowSuffix (int, int);
108 static void CMP_Fixup (int, int);
109 static void BadOp (void);
110 static void REP_Fixup (int, int);
111 static void SEP_Fixup (int, int);
112 static void BND_Fixup (int, int);
113 static void NOTRACK_Fixup (int, int);
114 static void HLE_Fixup1 (int, int);
115 static void HLE_Fixup2 (int, int);
116 static void HLE_Fixup3 (int, int);
117 static void CMPXCHG8B_Fixup (int, int);
118 static void XMM_Fixup (int, int);
119 static void CRC32_Fixup (int, int);
120 static void FXSAVE_Fixup (int, int);
121 static void PCMPESTR_Fixup (int, int);
122 static void OP_LWPCB_E (int, int);
123 static void OP_LWP_E (int, int);
124 static void OP_Vex_2src_1 (int, int);
125 static void OP_Vex_2src_2 (int, int);
127 static void MOVBE_Fixup (int, int);
128 static void MOVSXD_Fixup (int, int);
130 static void OP_Mask (int, int);
133 /* Points to first byte not fetched. */
134 bfd_byte
*max_fetched
;
135 bfd_byte the_buffer
[MAX_MNEM_SIZE
];
138 OPCODES_SIGJMP_BUF bailout
;
148 enum address_mode address_mode
;
150 /* Flags for the prefixes for the current instruction. See below. */
153 /* REX prefix the current instruction. See below. */
155 /* Bits of REX we've already used. */
157 /* Mark parts used in the REX prefix. When we are testing for
158 empty prefix (for 8bit register REX extension), just mask it
159 out. Otherwise test for REX bit is excuse for existence of REX
160 only in case value is nonzero. */
161 #define USED_REX(value) \
166 rex_used |= (value) | REX_OPCODE; \
169 rex_used |= REX_OPCODE; \
172 /* Flags for prefixes which we somehow handled when printing the
173 current instruction. */
174 static int used_prefixes
;
176 /* Flags stored in PREFIXES. */
177 #define PREFIX_REPZ 1
178 #define PREFIX_REPNZ 2
179 #define PREFIX_LOCK 4
181 #define PREFIX_SS 0x10
182 #define PREFIX_DS 0x20
183 #define PREFIX_ES 0x40
184 #define PREFIX_FS 0x80
185 #define PREFIX_GS 0x100
186 #define PREFIX_DATA 0x200
187 #define PREFIX_ADDR 0x400
188 #define PREFIX_FWAIT 0x800
190 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
191 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
193 #define FETCH_DATA(info, addr) \
194 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
195 ? 1 : fetch_data ((info), (addr)))
198 fetch_data (struct disassemble_info
*info
, bfd_byte
*addr
)
201 struct dis_private
*priv
= (struct dis_private
*) info
->private_data
;
202 bfd_vma start
= priv
->insn_start
+ (priv
->max_fetched
- priv
->the_buffer
);
204 if (addr
<= priv
->the_buffer
+ MAX_MNEM_SIZE
)
205 status
= (*info
->read_memory_func
) (start
,
207 addr
- priv
->max_fetched
,
213 /* If we did manage to read at least one byte, then
214 print_insn_i386 will do something sensible. Otherwise, print
215 an error. We do that here because this is where we know
217 if (priv
->max_fetched
== priv
->the_buffer
)
218 (*info
->memory_error_func
) (status
, start
, info
);
219 OPCODES_SIGLONGJMP (priv
->bailout
, 1);
222 priv
->max_fetched
= addr
;
226 /* Possible values for prefix requirement. */
227 #define PREFIX_IGNORED_SHIFT 16
228 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
229 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
230 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
231 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
232 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
234 /* Opcode prefixes. */
235 #define PREFIX_OPCODE (PREFIX_REPZ \
239 /* Prefixes ignored. */
240 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
241 | PREFIX_IGNORED_REPNZ \
242 | PREFIX_IGNORED_DATA)
244 #define XX { NULL, 0 }
245 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
247 #define Eb { OP_E, b_mode }
248 #define Ebnd { OP_E, bnd_mode }
249 #define EbS { OP_E, b_swap_mode }
250 #define EbndS { OP_E, bnd_swap_mode }
251 #define Ev { OP_E, v_mode }
252 #define Eva { OP_E, va_mode }
253 #define Ev_bnd { OP_E, v_bnd_mode }
254 #define EvS { OP_E, v_swap_mode }
255 #define Ed { OP_E, d_mode }
256 #define Edq { OP_E, dq_mode }
257 #define Edqw { OP_E, dqw_mode }
258 #define Edqb { OP_E, dqb_mode }
259 #define Edb { OP_E, db_mode }
260 #define Edw { OP_E, dw_mode }
261 #define Edqd { OP_E, dqd_mode }
262 #define Eq { OP_E, q_mode }
263 #define indirEv { OP_indirE, indir_v_mode }
264 #define indirEp { OP_indirE, f_mode }
265 #define stackEv { OP_E, stack_v_mode }
266 #define Em { OP_E, m_mode }
267 #define Ew { OP_E, w_mode }
268 #define M { OP_M, 0 } /* lea, lgdt, etc. */
269 #define Ma { OP_M, a_mode }
270 #define Mb { OP_M, b_mode }
271 #define Md { OP_M, d_mode }
272 #define Mo { OP_M, o_mode }
273 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
274 #define Mq { OP_M, q_mode }
275 #define Mv_bnd { OP_M, v_bndmk_mode }
276 #define Mx { OP_M, x_mode }
277 #define Mxmm { OP_M, xmm_mode }
278 #define Gb { OP_G, b_mode }
279 #define Gbnd { OP_G, bnd_mode }
280 #define Gv { OP_G, v_mode }
281 #define Gd { OP_G, d_mode }
282 #define Gdq { OP_G, dq_mode }
283 #define Gm { OP_G, m_mode }
284 #define Gva { OP_G, va_mode }
285 #define Gw { OP_G, w_mode }
286 #define Rd { OP_R, d_mode }
287 #define Rdq { OP_R, dq_mode }
288 #define Rm { OP_R, m_mode }
289 #define Ib { OP_I, b_mode }
290 #define sIb { OP_sI, b_mode } /* sign extened byte */
291 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
292 #define Iv { OP_I, v_mode }
293 #define sIv { OP_sI, v_mode }
294 #define Iv64 { OP_I64, v_mode }
295 #define Id { OP_I, d_mode }
296 #define Iw { OP_I, w_mode }
297 #define I1 { OP_I, const_1_mode }
298 #define Jb { OP_J, b_mode }
299 #define Jv { OP_J, v_mode }
300 #define Jdqw { OP_J, dqw_mode }
301 #define Cm { OP_C, m_mode }
302 #define Dm { OP_D, m_mode }
303 #define Td { OP_T, d_mode }
304 #define Skip_MODRM { OP_Skip_MODRM, 0 }
306 #define RMeAX { OP_REG, eAX_reg }
307 #define RMeBX { OP_REG, eBX_reg }
308 #define RMeCX { OP_REG, eCX_reg }
309 #define RMeDX { OP_REG, eDX_reg }
310 #define RMeSP { OP_REG, eSP_reg }
311 #define RMeBP { OP_REG, eBP_reg }
312 #define RMeSI { OP_REG, eSI_reg }
313 #define RMeDI { OP_REG, eDI_reg }
314 #define RMrAX { OP_REG, rAX_reg }
315 #define RMrBX { OP_REG, rBX_reg }
316 #define RMrCX { OP_REG, rCX_reg }
317 #define RMrDX { OP_REG, rDX_reg }
318 #define RMrSP { OP_REG, rSP_reg }
319 #define RMrBP { OP_REG, rBP_reg }
320 #define RMrSI { OP_REG, rSI_reg }
321 #define RMrDI { OP_REG, rDI_reg }
322 #define RMAL { OP_REG, al_reg }
323 #define RMCL { OP_REG, cl_reg }
324 #define RMDL { OP_REG, dl_reg }
325 #define RMBL { OP_REG, bl_reg }
326 #define RMAH { OP_REG, ah_reg }
327 #define RMCH { OP_REG, ch_reg }
328 #define RMDH { OP_REG, dh_reg }
329 #define RMBH { OP_REG, bh_reg }
330 #define RMAX { OP_REG, ax_reg }
331 #define RMDX { OP_REG, dx_reg }
333 #define eAX { OP_IMREG, eAX_reg }
334 #define eBX { OP_IMREG, eBX_reg }
335 #define eCX { OP_IMREG, eCX_reg }
336 #define eDX { OP_IMREG, eDX_reg }
337 #define eSP { OP_IMREG, eSP_reg }
338 #define eBP { OP_IMREG, eBP_reg }
339 #define eSI { OP_IMREG, eSI_reg }
340 #define eDI { OP_IMREG, eDI_reg }
341 #define AL { OP_IMREG, al_reg }
342 #define CL { OP_IMREG, cl_reg }
343 #define DL { OP_IMREG, dl_reg }
344 #define BL { OP_IMREG, bl_reg }
345 #define AH { OP_IMREG, ah_reg }
346 #define CH { OP_IMREG, ch_reg }
347 #define DH { OP_IMREG, dh_reg }
348 #define BH { OP_IMREG, bh_reg }
349 #define AX { OP_IMREG, ax_reg }
350 #define DX { OP_IMREG, dx_reg }
351 #define zAX { OP_IMREG, z_mode_ax_reg }
352 #define indirDX { OP_IMREG, indir_dx_reg }
354 #define Sw { OP_SEG, w_mode }
355 #define Sv { OP_SEG, v_mode }
356 #define Ap { OP_DIR, 0 }
357 #define Ob { OP_OFF64, b_mode }
358 #define Ov { OP_OFF64, v_mode }
359 #define Xb { OP_DSreg, eSI_reg }
360 #define Xv { OP_DSreg, eSI_reg }
361 #define Xz { OP_DSreg, eSI_reg }
362 #define Yb { OP_ESreg, eDI_reg }
363 #define Yv { OP_ESreg, eDI_reg }
364 #define DSBX { OP_DSreg, eBX_reg }
366 #define es { OP_REG, es_reg }
367 #define ss { OP_REG, ss_reg }
368 #define cs { OP_REG, cs_reg }
369 #define ds { OP_REG, ds_reg }
370 #define fs { OP_REG, fs_reg }
371 #define gs { OP_REG, gs_reg }
373 #define MX { OP_MMX, 0 }
374 #define XM { OP_XMM, 0 }
375 #define XMScalar { OP_XMM, scalar_mode }
376 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
377 #define XMM { OP_XMM, xmm_mode }
378 #define XMxmmq { OP_XMM, xmmq_mode }
379 #define EM { OP_EM, v_mode }
380 #define EMS { OP_EM, v_swap_mode }
381 #define EMd { OP_EM, d_mode }
382 #define EMx { OP_EM, x_mode }
383 #define EXbScalar { OP_EX, b_scalar_mode }
384 #define EXw { OP_EX, w_mode }
385 #define EXwScalar { OP_EX, w_scalar_mode }
386 #define EXd { OP_EX, d_mode }
387 #define EXdS { OP_EX, d_swap_mode }
388 #define EXq { OP_EX, q_mode }
389 #define EXqS { OP_EX, q_swap_mode }
390 #define EXx { OP_EX, x_mode }
391 #define EXxS { OP_EX, x_swap_mode }
392 #define EXxmm { OP_EX, xmm_mode }
393 #define EXymm { OP_EX, ymm_mode }
394 #define EXxmmq { OP_EX, xmmq_mode }
395 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
396 #define EXxmm_mb { OP_EX, xmm_mb_mode }
397 #define EXxmm_mw { OP_EX, xmm_mw_mode }
398 #define EXxmm_md { OP_EX, xmm_md_mode }
399 #define EXxmm_mq { OP_EX, xmm_mq_mode }
400 #define EXxmmdw { OP_EX, xmmdw_mode }
401 #define EXxmmqd { OP_EX, xmmqd_mode }
402 #define EXymmq { OP_EX, ymmq_mode }
403 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
404 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
405 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
406 #define MS { OP_MS, v_mode }
407 #define XS { OP_XS, v_mode }
408 #define EMCq { OP_EMC, q_mode }
409 #define MXC { OP_MXC, 0 }
410 #define OPSUF { OP_3DNowSuffix, 0 }
411 #define SEP { SEP_Fixup, 0 }
412 #define CMP { CMP_Fixup, 0 }
413 #define XMM0 { XMM_Fixup, 0 }
414 #define FXSAVE { FXSAVE_Fixup, 0 }
415 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
416 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
418 #define Vex { OP_VEX, vex_mode }
419 #define VexScalar { OP_VEX, vex_scalar_mode }
420 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
421 #define Vex128 { OP_VEX, vex128_mode }
422 #define Vex256 { OP_VEX, vex256_mode }
423 #define VexGdq { OP_VEX, dq_mode }
424 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
425 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
426 #define EXVexW { OP_EX_VexW, x_mode }
427 #define EXdVexW { OP_EX_VexW, d_mode }
428 #define EXqVexW { OP_EX_VexW, q_mode }
429 #define EXVexImmW { OP_EX_VexImmW, x_mode }
430 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
431 #define XMVexW { OP_XMM_VexW, 0 }
432 #define XMVexI4 { OP_REG_VexI4, x_mode }
433 #define PCLMUL { PCLMUL_Fixup, 0 }
434 #define VCMP { VCMP_Fixup, 0 }
435 #define VPCMP { VPCMP_Fixup, 0 }
436 #define VPCOM { VPCOM_Fixup, 0 }
438 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
439 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
440 #define EXxEVexS { OP_Rounding, evex_sae_mode }
442 #define XMask { OP_Mask, mask_mode }
443 #define MaskG { OP_G, mask_mode }
444 #define MaskE { OP_E, mask_mode }
445 #define MaskBDE { OP_E, mask_bd_mode }
446 #define MaskR { OP_R, mask_mode }
447 #define MaskVex { OP_VEX, mask_mode }
449 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
450 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
451 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
452 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
454 /* Used handle "rep" prefix for string instructions. */
455 #define Xbr { REP_Fixup, eSI_reg }
456 #define Xvr { REP_Fixup, eSI_reg }
457 #define Ybr { REP_Fixup, eDI_reg }
458 #define Yvr { REP_Fixup, eDI_reg }
459 #define Yzr { REP_Fixup, eDI_reg }
460 #define indirDXr { REP_Fixup, indir_dx_reg }
461 #define ALr { REP_Fixup, al_reg }
462 #define eAXr { REP_Fixup, eAX_reg }
464 /* Used handle HLE prefix for lockable instructions. */
465 #define Ebh1 { HLE_Fixup1, b_mode }
466 #define Evh1 { HLE_Fixup1, v_mode }
467 #define Ebh2 { HLE_Fixup2, b_mode }
468 #define Evh2 { HLE_Fixup2, v_mode }
469 #define Ebh3 { HLE_Fixup3, b_mode }
470 #define Evh3 { HLE_Fixup3, v_mode }
472 #define BND { BND_Fixup, 0 }
473 #define NOTRACK { NOTRACK_Fixup, 0 }
475 #define cond_jump_flag { NULL, cond_jump_mode }
476 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
478 /* bits in sizeflag */
479 #define SUFFIX_ALWAYS 4
487 /* byte operand with operand swapped */
489 /* byte operand, sign extend like 'T' suffix */
491 /* operand size depends on prefixes */
493 /* operand size depends on prefixes with operand swapped */
495 /* operand size depends on address prefix */
499 /* double word operand */
501 /* double word operand with operand swapped */
503 /* quad word operand */
505 /* quad word operand with operand swapped */
507 /* ten-byte operand */
509 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
510 broadcast enabled. */
512 /* Similar to x_mode, but with different EVEX mem shifts. */
514 /* Similar to x_mode, but with disabled broadcast. */
516 /* Similar to x_mode, but with operands swapped and disabled broadcast
519 /* 16-byte XMM operand */
521 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
522 memory operand (depending on vector length). Broadcast isn't
525 /* Same as xmmq_mode, but broadcast is allowed. */
526 evex_half_bcst_xmmq_mode
,
527 /* XMM register or byte memory operand */
529 /* XMM register or word memory operand */
531 /* XMM register or double word memory operand */
533 /* XMM register or quad word memory operand */
535 /* 16-byte XMM, word, double word or quad word operand. */
537 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
539 /* 32-byte YMM operand */
541 /* quad word, ymmword or zmmword memory operand. */
543 /* 32-byte YMM or 16-byte word operand */
545 /* d_mode in 32bit, q_mode in 64bit mode. */
547 /* pair of v_mode operands */
553 /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */
555 /* operand size depends on REX prefixes. */
557 /* registers like dq_mode, memory like w_mode, displacements like
558 v_mode without considering Intel64 ISA. */
562 /* bounds operand with operand swapped */
564 /* 4- or 6-byte pointer operand */
567 /* v_mode for indirect branch opcodes. */
569 /* v_mode for stack-related opcodes. */
571 /* non-quad operand size depends on prefixes */
573 /* 16-byte operand */
575 /* registers like dq_mode, memory like b_mode. */
577 /* registers like d_mode, memory like b_mode. */
579 /* registers like d_mode, memory like w_mode. */
581 /* registers like dq_mode, memory like d_mode. */
583 /* normal vex mode */
585 /* 128bit vex mode */
587 /* 256bit vex mode */
590 /* Operand size depends on the VEX.W bit, with VSIB dword indices. */
591 vex_vsib_d_w_dq_mode
,
592 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
594 /* Operand size depends on the VEX.W bit, with VSIB qword indices. */
595 vex_vsib_q_w_dq_mode
,
596 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
599 /* scalar, ignore vector length. */
601 /* like b_mode, ignore vector length. */
603 /* like w_mode, ignore vector length. */
605 /* like d_swap_mode, ignore vector length. */
607 /* like q_swap_mode, ignore vector length. */
609 /* like vex_mode, ignore vector length. */
611 /* Operand size depends on the VEX.W bit, ignore vector length. */
612 vex_scalar_w_dq_mode
,
614 /* Static rounding. */
616 /* Static rounding, 64-bit mode only. */
617 evex_rounding_64_mode
,
618 /* Supress all exceptions. */
621 /* Mask register operand. */
623 /* Mask register operand. */
691 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
693 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
694 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
695 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
696 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
697 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
698 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
699 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
700 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
701 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
702 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
703 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
704 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
705 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
706 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
707 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
708 #define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I))
838 MOD_VEX_0F12_PREFIX_0
,
839 MOD_VEX_0F12_PREFIX_2
,
841 MOD_VEX_0F16_PREFIX_0
,
842 MOD_VEX_0F16_PREFIX_2
,
845 MOD_VEX_W_0_0F41_P_0_LEN_1
,
846 MOD_VEX_W_1_0F41_P_0_LEN_1
,
847 MOD_VEX_W_0_0F41_P_2_LEN_1
,
848 MOD_VEX_W_1_0F41_P_2_LEN_1
,
849 MOD_VEX_W_0_0F42_P_0_LEN_1
,
850 MOD_VEX_W_1_0F42_P_0_LEN_1
,
851 MOD_VEX_W_0_0F42_P_2_LEN_1
,
852 MOD_VEX_W_1_0F42_P_2_LEN_1
,
853 MOD_VEX_W_0_0F44_P_0_LEN_1
,
854 MOD_VEX_W_1_0F44_P_0_LEN_1
,
855 MOD_VEX_W_0_0F44_P_2_LEN_1
,
856 MOD_VEX_W_1_0F44_P_2_LEN_1
,
857 MOD_VEX_W_0_0F45_P_0_LEN_1
,
858 MOD_VEX_W_1_0F45_P_0_LEN_1
,
859 MOD_VEX_W_0_0F45_P_2_LEN_1
,
860 MOD_VEX_W_1_0F45_P_2_LEN_1
,
861 MOD_VEX_W_0_0F46_P_0_LEN_1
,
862 MOD_VEX_W_1_0F46_P_0_LEN_1
,
863 MOD_VEX_W_0_0F46_P_2_LEN_1
,
864 MOD_VEX_W_1_0F46_P_2_LEN_1
,
865 MOD_VEX_W_0_0F47_P_0_LEN_1
,
866 MOD_VEX_W_1_0F47_P_0_LEN_1
,
867 MOD_VEX_W_0_0F47_P_2_LEN_1
,
868 MOD_VEX_W_1_0F47_P_2_LEN_1
,
869 MOD_VEX_W_0_0F4A_P_0_LEN_1
,
870 MOD_VEX_W_1_0F4A_P_0_LEN_1
,
871 MOD_VEX_W_0_0F4A_P_2_LEN_1
,
872 MOD_VEX_W_1_0F4A_P_2_LEN_1
,
873 MOD_VEX_W_0_0F4B_P_0_LEN_1
,
874 MOD_VEX_W_1_0F4B_P_0_LEN_1
,
875 MOD_VEX_W_0_0F4B_P_2_LEN_1
,
887 MOD_VEX_W_0_0F91_P_0_LEN_0
,
888 MOD_VEX_W_1_0F91_P_0_LEN_0
,
889 MOD_VEX_W_0_0F91_P_2_LEN_0
,
890 MOD_VEX_W_1_0F91_P_2_LEN_0
,
891 MOD_VEX_W_0_0F92_P_0_LEN_0
,
892 MOD_VEX_W_0_0F92_P_2_LEN_0
,
893 MOD_VEX_0F92_P_3_LEN_0
,
894 MOD_VEX_W_0_0F93_P_0_LEN_0
,
895 MOD_VEX_W_0_0F93_P_2_LEN_0
,
896 MOD_VEX_0F93_P_3_LEN_0
,
897 MOD_VEX_W_0_0F98_P_0_LEN_0
,
898 MOD_VEX_W_1_0F98_P_0_LEN_0
,
899 MOD_VEX_W_0_0F98_P_2_LEN_0
,
900 MOD_VEX_W_1_0F98_P_2_LEN_0
,
901 MOD_VEX_W_0_0F99_P_0_LEN_0
,
902 MOD_VEX_W_1_0F99_P_0_LEN_0
,
903 MOD_VEX_W_0_0F99_P_2_LEN_0
,
904 MOD_VEX_W_1_0F99_P_2_LEN_0
,
907 MOD_VEX_0FD7_PREFIX_2
,
908 MOD_VEX_0FE7_PREFIX_2
,
909 MOD_VEX_0FF0_PREFIX_3
,
910 MOD_VEX_0F381A_PREFIX_2
,
911 MOD_VEX_0F382A_PREFIX_2
,
912 MOD_VEX_0F382C_PREFIX_2
,
913 MOD_VEX_0F382D_PREFIX_2
,
914 MOD_VEX_0F382E_PREFIX_2
,
915 MOD_VEX_0F382F_PREFIX_2
,
916 MOD_VEX_0F385A_PREFIX_2
,
917 MOD_VEX_0F388C_PREFIX_2
,
918 MOD_VEX_0F388E_PREFIX_2
,
919 MOD_VEX_W_0_0F3A30_P_2_LEN_0
,
920 MOD_VEX_W_1_0F3A30_P_2_LEN_0
,
921 MOD_VEX_W_0_0F3A31_P_2_LEN_0
,
922 MOD_VEX_W_1_0F3A31_P_2_LEN_0
,
923 MOD_VEX_W_0_0F3A32_P_2_LEN_0
,
924 MOD_VEX_W_1_0F3A32_P_2_LEN_0
,
925 MOD_VEX_W_0_0F3A33_P_2_LEN_0
,
926 MOD_VEX_W_1_0F3A33_P_2_LEN_0
,
928 MOD_EVEX_0F12_PREFIX_0
,
929 MOD_EVEX_0F12_PREFIX_2
,
931 MOD_EVEX_0F16_PREFIX_0
,
932 MOD_EVEX_0F16_PREFIX_2
,
935 MOD_EVEX_0F38C6_REG_1
,
936 MOD_EVEX_0F38C6_REG_2
,
937 MOD_EVEX_0F38C6_REG_5
,
938 MOD_EVEX_0F38C6_REG_6
,
939 MOD_EVEX_0F38C7_REG_1
,
940 MOD_EVEX_0F38C7_REG_2
,
941 MOD_EVEX_0F38C7_REG_5
,
942 MOD_EVEX_0F38C7_REG_6
955 RM_0F1E_P_1_MOD_3_REG_7
,
956 RM_0FAE_REG_6_MOD_3_P_0
,
963 PREFIX_0F01_REG_3_RM_1
,
964 PREFIX_0F01_REG_5_MOD_0
,
965 PREFIX_0F01_REG_5_MOD_3_RM_0
,
966 PREFIX_0F01_REG_5_MOD_3_RM_1
,
967 PREFIX_0F01_REG_5_MOD_3_RM_2
,
968 PREFIX_0F01_REG_7_MOD_3_RM_2
,
969 PREFIX_0F01_REG_7_MOD_3_RM_3
,
1011 PREFIX_0FAE_REG_0_MOD_3
,
1012 PREFIX_0FAE_REG_1_MOD_3
,
1013 PREFIX_0FAE_REG_2_MOD_3
,
1014 PREFIX_0FAE_REG_3_MOD_3
,
1015 PREFIX_0FAE_REG_4_MOD_0
,
1016 PREFIX_0FAE_REG_4_MOD_3
,
1017 PREFIX_0FAE_REG_5_MOD_0
,
1018 PREFIX_0FAE_REG_5_MOD_3
,
1019 PREFIX_0FAE_REG_6_MOD_0
,
1020 PREFIX_0FAE_REG_6_MOD_3
,
1021 PREFIX_0FAE_REG_7_MOD_0
,
1027 PREFIX_0FC7_REG_6_MOD_0
,
1028 PREFIX_0FC7_REG_6_MOD_3
,
1029 PREFIX_0FC7_REG_7_MOD_3
,
1159 PREFIX_VEX_0F71_REG_2
,
1160 PREFIX_VEX_0F71_REG_4
,
1161 PREFIX_VEX_0F71_REG_6
,
1162 PREFIX_VEX_0F72_REG_2
,
1163 PREFIX_VEX_0F72_REG_4
,
1164 PREFIX_VEX_0F72_REG_6
,
1165 PREFIX_VEX_0F73_REG_2
,
1166 PREFIX_VEX_0F73_REG_3
,
1167 PREFIX_VEX_0F73_REG_6
,
1168 PREFIX_VEX_0F73_REG_7
,
1341 PREFIX_VEX_0F38F3_REG_1
,
1342 PREFIX_VEX_0F38F3_REG_2
,
1343 PREFIX_VEX_0F38F3_REG_3
,
1445 PREFIX_EVEX_0F71_REG_2
,
1446 PREFIX_EVEX_0F71_REG_4
,
1447 PREFIX_EVEX_0F71_REG_6
,
1448 PREFIX_EVEX_0F72_REG_0
,
1449 PREFIX_EVEX_0F72_REG_1
,
1450 PREFIX_EVEX_0F72_REG_2
,
1451 PREFIX_EVEX_0F72_REG_4
,
1452 PREFIX_EVEX_0F72_REG_6
,
1453 PREFIX_EVEX_0F73_REG_2
,
1454 PREFIX_EVEX_0F73_REG_3
,
1455 PREFIX_EVEX_0F73_REG_6
,
1456 PREFIX_EVEX_0F73_REG_7
,
1588 PREFIX_EVEX_0F38C6_REG_1
,
1589 PREFIX_EVEX_0F38C6_REG_2
,
1590 PREFIX_EVEX_0F38C6_REG_5
,
1591 PREFIX_EVEX_0F38C6_REG_6
,
1592 PREFIX_EVEX_0F38C7_REG_1
,
1593 PREFIX_EVEX_0F38C7_REG_2
,
1594 PREFIX_EVEX_0F38C7_REG_5
,
1595 PREFIX_EVEX_0F38C7_REG_6
,
1688 THREE_BYTE_0F38
= 0,
1715 VEX_LEN_0F12_P_0_M_0
= 0,
1716 VEX_LEN_0F12_P_0_M_1
,
1717 #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0
1719 VEX_LEN_0F16_P_0_M_0
,
1720 VEX_LEN_0F16_P_0_M_1
,
1721 #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0
1757 VEX_LEN_0FAE_R_2_M_0
,
1758 VEX_LEN_0FAE_R_3_M_0
,
1765 VEX_LEN_0F381A_P_2_M_0
,
1768 VEX_LEN_0F385A_P_2_M_0
,
1771 VEX_LEN_0F38F3_R_1_P_0
,
1772 VEX_LEN_0F38F3_R_2_P_0
,
1773 VEX_LEN_0F38F3_R_3_P_0
,
1816 VEX_LEN_0FXOP_08_CC
,
1817 VEX_LEN_0FXOP_08_CD
,
1818 VEX_LEN_0FXOP_08_CE
,
1819 VEX_LEN_0FXOP_08_CF
,
1820 VEX_LEN_0FXOP_08_EC
,
1821 VEX_LEN_0FXOP_08_ED
,
1822 VEX_LEN_0FXOP_08_EE
,
1823 VEX_LEN_0FXOP_08_EF
,
1824 VEX_LEN_0FXOP_09_80
,
1830 EVEX_LEN_0F6E_P_2
= 0,
1836 EVEX_LEN_0F3819_P_2_W_0
,
1837 EVEX_LEN_0F3819_P_2_W_1
,
1838 EVEX_LEN_0F381A_P_2_W_0
,
1839 EVEX_LEN_0F381A_P_2_W_1
,
1840 EVEX_LEN_0F381B_P_2_W_0
,
1841 EVEX_LEN_0F381B_P_2_W_1
,
1842 EVEX_LEN_0F385A_P_2_W_0
,
1843 EVEX_LEN_0F385A_P_2_W_1
,
1844 EVEX_LEN_0F385B_P_2_W_0
,
1845 EVEX_LEN_0F385B_P_2_W_1
,
1846 EVEX_LEN_0F38C6_REG_1_PREFIX_2
,
1847 EVEX_LEN_0F38C6_REG_2_PREFIX_2
,
1848 EVEX_LEN_0F38C6_REG_5_PREFIX_2
,
1849 EVEX_LEN_0F38C6_REG_6_PREFIX_2
,
1850 EVEX_LEN_0F38C7_R_1_P_2_W_0
,
1851 EVEX_LEN_0F38C7_R_1_P_2_W_1
,
1852 EVEX_LEN_0F38C7_R_2_P_2_W_0
,
1853 EVEX_LEN_0F38C7_R_2_P_2_W_1
,
1854 EVEX_LEN_0F38C7_R_5_P_2_W_0
,
1855 EVEX_LEN_0F38C7_R_5_P_2_W_1
,
1856 EVEX_LEN_0F38C7_R_6_P_2_W_0
,
1857 EVEX_LEN_0F38C7_R_6_P_2_W_1
,
1858 EVEX_LEN_0F3A14_P_2
,
1859 EVEX_LEN_0F3A15_P_2
,
1860 EVEX_LEN_0F3A16_P_2
,
1861 EVEX_LEN_0F3A17_P_2
,
1862 EVEX_LEN_0F3A18_P_2_W_0
,
1863 EVEX_LEN_0F3A18_P_2_W_1
,
1864 EVEX_LEN_0F3A19_P_2_W_0
,
1865 EVEX_LEN_0F3A19_P_2_W_1
,
1866 EVEX_LEN_0F3A1A_P_2_W_0
,
1867 EVEX_LEN_0F3A1A_P_2_W_1
,
1868 EVEX_LEN_0F3A1B_P_2_W_0
,
1869 EVEX_LEN_0F3A1B_P_2_W_1
,
1870 EVEX_LEN_0F3A20_P_2
,
1871 EVEX_LEN_0F3A21_P_2_W_0
,
1872 EVEX_LEN_0F3A22_P_2
,
1873 EVEX_LEN_0F3A23_P_2_W_0
,
1874 EVEX_LEN_0F3A23_P_2_W_1
,
1875 EVEX_LEN_0F3A38_P_2_W_0
,
1876 EVEX_LEN_0F3A38_P_2_W_1
,
1877 EVEX_LEN_0F3A39_P_2_W_0
,
1878 EVEX_LEN_0F3A39_P_2_W_1
,
1879 EVEX_LEN_0F3A3A_P_2_W_0
,
1880 EVEX_LEN_0F3A3A_P_2_W_1
,
1881 EVEX_LEN_0F3A3B_P_2_W_0
,
1882 EVEX_LEN_0F3A3B_P_2_W_1
,
1883 EVEX_LEN_0F3A43_P_2_W_0
,
1884 EVEX_LEN_0F3A43_P_2_W_1
1889 VEX_W_0F41_P_0_LEN_1
= 0,
1890 VEX_W_0F41_P_2_LEN_1
,
1891 VEX_W_0F42_P_0_LEN_1
,
1892 VEX_W_0F42_P_2_LEN_1
,
1893 VEX_W_0F44_P_0_LEN_0
,
1894 VEX_W_0F44_P_2_LEN_0
,
1895 VEX_W_0F45_P_0_LEN_1
,
1896 VEX_W_0F45_P_2_LEN_1
,
1897 VEX_W_0F46_P_0_LEN_1
,
1898 VEX_W_0F46_P_2_LEN_1
,
1899 VEX_W_0F47_P_0_LEN_1
,
1900 VEX_W_0F47_P_2_LEN_1
,
1901 VEX_W_0F4A_P_0_LEN_1
,
1902 VEX_W_0F4A_P_2_LEN_1
,
1903 VEX_W_0F4B_P_0_LEN_1
,
1904 VEX_W_0F4B_P_2_LEN_1
,
1905 VEX_W_0F90_P_0_LEN_0
,
1906 VEX_W_0F90_P_2_LEN_0
,
1907 VEX_W_0F91_P_0_LEN_0
,
1908 VEX_W_0F91_P_2_LEN_0
,
1909 VEX_W_0F92_P_0_LEN_0
,
1910 VEX_W_0F92_P_2_LEN_0
,
1911 VEX_W_0F93_P_0_LEN_0
,
1912 VEX_W_0F93_P_2_LEN_0
,
1913 VEX_W_0F98_P_0_LEN_0
,
1914 VEX_W_0F98_P_2_LEN_0
,
1915 VEX_W_0F99_P_0_LEN_0
,
1916 VEX_W_0F99_P_2_LEN_0
,
1925 VEX_W_0F381A_P_2_M_0
,
1926 VEX_W_0F382C_P_2_M_0
,
1927 VEX_W_0F382D_P_2_M_0
,
1928 VEX_W_0F382E_P_2_M_0
,
1929 VEX_W_0F382F_P_2_M_0
,
1934 VEX_W_0F385A_P_2_M_0
,
1947 VEX_W_0F3A30_P_2_LEN_0
,
1948 VEX_W_0F3A31_P_2_LEN_0
,
1949 VEX_W_0F3A32_P_2_LEN_0
,
1950 VEX_W_0F3A33_P_2_LEN_0
,
1966 EVEX_W_0F12_P_0_M_1
,
1969 EVEX_W_0F16_P_0_M_1
,
2003 EVEX_W_0F72_R_2_P_2
,
2004 EVEX_W_0F72_R_6_P_2
,
2005 EVEX_W_0F73_R_2_P_2
,
2006 EVEX_W_0F73_R_6_P_2
,
2107 EVEX_W_0F38C7_R_1_P_2
,
2108 EVEX_W_0F38C7_R_2_P_2
,
2109 EVEX_W_0F38C7_R_5_P_2
,
2110 EVEX_W_0F38C7_R_6_P_2
,
2145 typedef void (*op_rtn
) (int bytemode
, int sizeflag
);
2154 unsigned int prefix_requirement
;
2157 /* Upper case letters in the instruction names here are macros.
2158 'A' => print 'b' if no register operands or suffix_always is true
2159 'B' => print 'b' if suffix_always is true
2160 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2162 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2163 suffix_always is true
2164 'E' => print 'e' if 32-bit form of jcxz
2165 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2166 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2167 'H' => print ",pt" or ",pn" branch hint
2170 'K' => print 'd' or 'q' if rex prefix is present.
2171 'L' => print 'l' if suffix_always is true
2172 'M' => print 'r' if intel_mnemonic is false.
2173 'N' => print 'n' if instruction has no wait "prefix"
2174 'O' => print 'd' or 'o' (or 'q' in Intel mode)
2175 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2176 or suffix_always is true. print 'q' if rex prefix is present.
2177 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2179 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2180 'S' => print 'w', 'l' or 'q' if suffix_always is true
2181 'T' => print 'q' in 64bit mode if instruction has no operand size
2182 prefix and behave as 'P' otherwise
2183 'U' => print 'q' in 64bit mode if instruction has no operand size
2184 prefix and behave as 'Q' otherwise
2185 'V' => print 'q' in 64bit mode if instruction has no operand size
2186 prefix and behave as 'S' otherwise
2187 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2188 'X' => print 's', 'd' depending on data16 prefix (for XMM)
2190 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2191 '!' => change condition from true to false or from false to true.
2192 '%' => add 1 upper case letter to the macro.
2193 '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
2194 prefix or suffix_always is true (lcall/ljmp).
2195 '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2196 on operand size prefix.
2197 '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2198 has no operand size prefix for AMD64 ISA, behave as 'P'
2201 2 upper case letter macros:
2202 "XY" => print 'x' or 'y' if suffix_always is true or no register
2203 operands and no broadcast.
2204 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2205 register operands and no broadcast.
2206 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2207 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory
2208 operand or no operand at all in 64bit mode, or if suffix_always
2210 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2211 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2212 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2213 "LW" => print 'd', 'q' depending on the VEX.W bit
2214 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2215 an operand size prefix, or suffix_always is true. print
2216 'q' if rex prefix is present.
2218 Many of the above letters print nothing in Intel mode. See "putop"
2221 Braces '{' and '}', and vertical bars '|', indicate alternative
2222 mnemonic strings for AT&T and Intel. */
2224 static const struct dis386 dis386
[] = {
2226 { "addB", { Ebh1
, Gb
}, 0 },
2227 { "addS", { Evh1
, Gv
}, 0 },
2228 { "addB", { Gb
, EbS
}, 0 },
2229 { "addS", { Gv
, EvS
}, 0 },
2230 { "addB", { AL
, Ib
}, 0 },
2231 { "addS", { eAX
, Iv
}, 0 },
2232 { X86_64_TABLE (X86_64_06
) },
2233 { X86_64_TABLE (X86_64_07
) },
2235 { "orB", { Ebh1
, Gb
}, 0 },
2236 { "orS", { Evh1
, Gv
}, 0 },
2237 { "orB", { Gb
, EbS
}, 0 },
2238 { "orS", { Gv
, EvS
}, 0 },
2239 { "orB", { AL
, Ib
}, 0 },
2240 { "orS", { eAX
, Iv
}, 0 },
2241 { X86_64_TABLE (X86_64_0E
) },
2242 { Bad_Opcode
}, /* 0x0f extended opcode escape */
2244 { "adcB", { Ebh1
, Gb
}, 0 },
2245 { "adcS", { Evh1
, Gv
}, 0 },
2246 { "adcB", { Gb
, EbS
}, 0 },
2247 { "adcS", { Gv
, EvS
}, 0 },
2248 { "adcB", { AL
, Ib
}, 0 },
2249 { "adcS", { eAX
, Iv
}, 0 },
2250 { X86_64_TABLE (X86_64_16
) },
2251 { X86_64_TABLE (X86_64_17
) },
2253 { "sbbB", { Ebh1
, Gb
}, 0 },
2254 { "sbbS", { Evh1
, Gv
}, 0 },
2255 { "sbbB", { Gb
, EbS
}, 0 },
2256 { "sbbS", { Gv
, EvS
}, 0 },
2257 { "sbbB", { AL
, Ib
}, 0 },
2258 { "sbbS", { eAX
, Iv
}, 0 },
2259 { X86_64_TABLE (X86_64_1E
) },
2260 { X86_64_TABLE (X86_64_1F
) },
2262 { "andB", { Ebh1
, Gb
}, 0 },
2263 { "andS", { Evh1
, Gv
}, 0 },
2264 { "andB", { Gb
, EbS
}, 0 },
2265 { "andS", { Gv
, EvS
}, 0 },
2266 { "andB", { AL
, Ib
}, 0 },
2267 { "andS", { eAX
, Iv
}, 0 },
2268 { Bad_Opcode
}, /* SEG ES prefix */
2269 { X86_64_TABLE (X86_64_27
) },
2271 { "subB", { Ebh1
, Gb
}, 0 },
2272 { "subS", { Evh1
, Gv
}, 0 },
2273 { "subB", { Gb
, EbS
}, 0 },
2274 { "subS", { Gv
, EvS
}, 0 },
2275 { "subB", { AL
, Ib
}, 0 },
2276 { "subS", { eAX
, Iv
}, 0 },
2277 { Bad_Opcode
}, /* SEG CS prefix */
2278 { X86_64_TABLE (X86_64_2F
) },
2280 { "xorB", { Ebh1
, Gb
}, 0 },
2281 { "xorS", { Evh1
, Gv
}, 0 },
2282 { "xorB", { Gb
, EbS
}, 0 },
2283 { "xorS", { Gv
, EvS
}, 0 },
2284 { "xorB", { AL
, Ib
}, 0 },
2285 { "xorS", { eAX
, Iv
}, 0 },
2286 { Bad_Opcode
}, /* SEG SS prefix */
2287 { X86_64_TABLE (X86_64_37
) },
2289 { "cmpB", { Eb
, Gb
}, 0 },
2290 { "cmpS", { Ev
, Gv
}, 0 },
2291 { "cmpB", { Gb
, EbS
}, 0 },
2292 { "cmpS", { Gv
, EvS
}, 0 },
2293 { "cmpB", { AL
, Ib
}, 0 },
2294 { "cmpS", { eAX
, Iv
}, 0 },
2295 { Bad_Opcode
}, /* SEG DS prefix */
2296 { X86_64_TABLE (X86_64_3F
) },
2298 { "inc{S|}", { RMeAX
}, 0 },
2299 { "inc{S|}", { RMeCX
}, 0 },
2300 { "inc{S|}", { RMeDX
}, 0 },
2301 { "inc{S|}", { RMeBX
}, 0 },
2302 { "inc{S|}", { RMeSP
}, 0 },
2303 { "inc{S|}", { RMeBP
}, 0 },
2304 { "inc{S|}", { RMeSI
}, 0 },
2305 { "inc{S|}", { RMeDI
}, 0 },
2307 { "dec{S|}", { RMeAX
}, 0 },
2308 { "dec{S|}", { RMeCX
}, 0 },
2309 { "dec{S|}", { RMeDX
}, 0 },
2310 { "dec{S|}", { RMeBX
}, 0 },
2311 { "dec{S|}", { RMeSP
}, 0 },
2312 { "dec{S|}", { RMeBP
}, 0 },
2313 { "dec{S|}", { RMeSI
}, 0 },
2314 { "dec{S|}", { RMeDI
}, 0 },
2316 { "pushV", { RMrAX
}, 0 },
2317 { "pushV", { RMrCX
}, 0 },
2318 { "pushV", { RMrDX
}, 0 },
2319 { "pushV", { RMrBX
}, 0 },
2320 { "pushV", { RMrSP
}, 0 },
2321 { "pushV", { RMrBP
}, 0 },
2322 { "pushV", { RMrSI
}, 0 },
2323 { "pushV", { RMrDI
}, 0 },
2325 { "popV", { RMrAX
}, 0 },
2326 { "popV", { RMrCX
}, 0 },
2327 { "popV", { RMrDX
}, 0 },
2328 { "popV", { RMrBX
}, 0 },
2329 { "popV", { RMrSP
}, 0 },
2330 { "popV", { RMrBP
}, 0 },
2331 { "popV", { RMrSI
}, 0 },
2332 { "popV", { RMrDI
}, 0 },
2334 { X86_64_TABLE (X86_64_60
) },
2335 { X86_64_TABLE (X86_64_61
) },
2336 { X86_64_TABLE (X86_64_62
) },
2337 { X86_64_TABLE (X86_64_63
) },
2338 { Bad_Opcode
}, /* seg fs */
2339 { Bad_Opcode
}, /* seg gs */
2340 { Bad_Opcode
}, /* op size prefix */
2341 { Bad_Opcode
}, /* adr size prefix */
2343 { "pushT", { sIv
}, 0 },
2344 { "imulS", { Gv
, Ev
, Iv
}, 0 },
2345 { "pushT", { sIbT
}, 0 },
2346 { "imulS", { Gv
, Ev
, sIb
}, 0 },
2347 { "ins{b|}", { Ybr
, indirDX
}, 0 },
2348 { X86_64_TABLE (X86_64_6D
) },
2349 { "outs{b|}", { indirDXr
, Xb
}, 0 },
2350 { X86_64_TABLE (X86_64_6F
) },
2352 { "joH", { Jb
, BND
, cond_jump_flag
}, 0 },
2353 { "jnoH", { Jb
, BND
, cond_jump_flag
}, 0 },
2354 { "jbH", { Jb
, BND
, cond_jump_flag
}, 0 },
2355 { "jaeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2356 { "jeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2357 { "jneH", { Jb
, BND
, cond_jump_flag
}, 0 },
2358 { "jbeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2359 { "jaH", { Jb
, BND
, cond_jump_flag
}, 0 },
2361 { "jsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2362 { "jnsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2363 { "jpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2364 { "jnpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2365 { "jlH", { Jb
, BND
, cond_jump_flag
}, 0 },
2366 { "jgeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2367 { "jleH", { Jb
, BND
, cond_jump_flag
}, 0 },
2368 { "jgH", { Jb
, BND
, cond_jump_flag
}, 0 },
2370 { REG_TABLE (REG_80
) },
2371 { REG_TABLE (REG_81
) },
2372 { X86_64_TABLE (X86_64_82
) },
2373 { REG_TABLE (REG_83
) },
2374 { "testB", { Eb
, Gb
}, 0 },
2375 { "testS", { Ev
, Gv
}, 0 },
2376 { "xchgB", { Ebh2
, Gb
}, 0 },
2377 { "xchgS", { Evh2
, Gv
}, 0 },
2379 { "movB", { Ebh3
, Gb
}, 0 },
2380 { "movS", { Evh3
, Gv
}, 0 },
2381 { "movB", { Gb
, EbS
}, 0 },
2382 { "movS", { Gv
, EvS
}, 0 },
2383 { "movD", { Sv
, Sw
}, 0 },
2384 { MOD_TABLE (MOD_8D
) },
2385 { "movD", { Sw
, Sv
}, 0 },
2386 { REG_TABLE (REG_8F
) },
2388 { PREFIX_TABLE (PREFIX_90
) },
2389 { "xchgS", { RMeCX
, eAX
}, 0 },
2390 { "xchgS", { RMeDX
, eAX
}, 0 },
2391 { "xchgS", { RMeBX
, eAX
}, 0 },
2392 { "xchgS", { RMeSP
, eAX
}, 0 },
2393 { "xchgS", { RMeBP
, eAX
}, 0 },
2394 { "xchgS", { RMeSI
, eAX
}, 0 },
2395 { "xchgS", { RMeDI
, eAX
}, 0 },
2397 { "cW{t|}R", { XX
}, 0 },
2398 { "cR{t|}O", { XX
}, 0 },
2399 { X86_64_TABLE (X86_64_9A
) },
2400 { Bad_Opcode
}, /* fwait */
2401 { "pushfT", { XX
}, 0 },
2402 { "popfT", { XX
}, 0 },
2403 { "sahf", { XX
}, 0 },
2404 { "lahf", { XX
}, 0 },
2406 { "mov%LB", { AL
, Ob
}, 0 },
2407 { "mov%LS", { eAX
, Ov
}, 0 },
2408 { "mov%LB", { Ob
, AL
}, 0 },
2409 { "mov%LS", { Ov
, eAX
}, 0 },
2410 { "movs{b|}", { Ybr
, Xb
}, 0 },
2411 { "movs{R|}", { Yvr
, Xv
}, 0 },
2412 { "cmps{b|}", { Xb
, Yb
}, 0 },
2413 { "cmps{R|}", { Xv
, Yv
}, 0 },
2415 { "testB", { AL
, Ib
}, 0 },
2416 { "testS", { eAX
, Iv
}, 0 },
2417 { "stosB", { Ybr
, AL
}, 0 },
2418 { "stosS", { Yvr
, eAX
}, 0 },
2419 { "lodsB", { ALr
, Xb
}, 0 },
2420 { "lodsS", { eAXr
, Xv
}, 0 },
2421 { "scasB", { AL
, Yb
}, 0 },
2422 { "scasS", { eAX
, Yv
}, 0 },
2424 { "movB", { RMAL
, Ib
}, 0 },
2425 { "movB", { RMCL
, Ib
}, 0 },
2426 { "movB", { RMDL
, Ib
}, 0 },
2427 { "movB", { RMBL
, Ib
}, 0 },
2428 { "movB", { RMAH
, Ib
}, 0 },
2429 { "movB", { RMCH
, Ib
}, 0 },
2430 { "movB", { RMDH
, Ib
}, 0 },
2431 { "movB", { RMBH
, Ib
}, 0 },
2433 { "mov%LV", { RMeAX
, Iv64
}, 0 },
2434 { "mov%LV", { RMeCX
, Iv64
}, 0 },
2435 { "mov%LV", { RMeDX
, Iv64
}, 0 },
2436 { "mov%LV", { RMeBX
, Iv64
}, 0 },
2437 { "mov%LV", { RMeSP
, Iv64
}, 0 },
2438 { "mov%LV", { RMeBP
, Iv64
}, 0 },
2439 { "mov%LV", { RMeSI
, Iv64
}, 0 },
2440 { "mov%LV", { RMeDI
, Iv64
}, 0 },
2442 { REG_TABLE (REG_C0
) },
2443 { REG_TABLE (REG_C1
) },
2444 { X86_64_TABLE (X86_64_C2
) },
2445 { X86_64_TABLE (X86_64_C3
) },
2446 { X86_64_TABLE (X86_64_C4
) },
2447 { X86_64_TABLE (X86_64_C5
) },
2448 { REG_TABLE (REG_C6
) },
2449 { REG_TABLE (REG_C7
) },
2451 { "enterT", { Iw
, Ib
}, 0 },
2452 { "leaveT", { XX
}, 0 },
2453 { "{l|}ret{|f}P", { Iw
}, 0 },
2454 { "{l|}ret{|f}P", { XX
}, 0 },
2455 { "int3", { XX
}, 0 },
2456 { "int", { Ib
}, 0 },
2457 { X86_64_TABLE (X86_64_CE
) },
2458 { "iret%LP", { XX
}, 0 },
2460 { REG_TABLE (REG_D0
) },
2461 { REG_TABLE (REG_D1
) },
2462 { REG_TABLE (REG_D2
) },
2463 { REG_TABLE (REG_D3
) },
2464 { X86_64_TABLE (X86_64_D4
) },
2465 { X86_64_TABLE (X86_64_D5
) },
2467 { "xlat", { DSBX
}, 0 },
2478 { "loopneFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2479 { "loopeFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2480 { "loopFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2481 { "jEcxzH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2482 { "inB", { AL
, Ib
}, 0 },
2483 { "inG", { zAX
, Ib
}, 0 },
2484 { "outB", { Ib
, AL
}, 0 },
2485 { "outG", { Ib
, zAX
}, 0 },
2487 { X86_64_TABLE (X86_64_E8
) },
2488 { X86_64_TABLE (X86_64_E9
) },
2489 { X86_64_TABLE (X86_64_EA
) },
2490 { "jmp", { Jb
, BND
}, 0 },
2491 { "inB", { AL
, indirDX
}, 0 },
2492 { "inG", { zAX
, indirDX
}, 0 },
2493 { "outB", { indirDX
, AL
}, 0 },
2494 { "outG", { indirDX
, zAX
}, 0 },
2496 { Bad_Opcode
}, /* lock prefix */
2497 { "icebp", { XX
}, 0 },
2498 { Bad_Opcode
}, /* repne */
2499 { Bad_Opcode
}, /* repz */
2500 { "hlt", { XX
}, 0 },
2501 { "cmc", { XX
}, 0 },
2502 { REG_TABLE (REG_F6
) },
2503 { REG_TABLE (REG_F7
) },
2505 { "clc", { XX
}, 0 },
2506 { "stc", { XX
}, 0 },
2507 { "cli", { XX
}, 0 },
2508 { "sti", { XX
}, 0 },
2509 { "cld", { XX
}, 0 },
2510 { "std", { XX
}, 0 },
2511 { REG_TABLE (REG_FE
) },
2512 { REG_TABLE (REG_FF
) },
2515 static const struct dis386 dis386_twobyte
[] = {
2517 { REG_TABLE (REG_0F00
) },
2518 { REG_TABLE (REG_0F01
) },
2519 { "larS", { Gv
, Ew
}, 0 },
2520 { "lslS", { Gv
, Ew
}, 0 },
2522 { "syscall", { XX
}, 0 },
2523 { "clts", { XX
}, 0 },
2524 { "sysret%LQ", { XX
}, 0 },
2526 { "invd", { XX
}, 0 },
2527 { PREFIX_TABLE (PREFIX_0F09
) },
2529 { "ud2", { XX
}, 0 },
2531 { REG_TABLE (REG_0F0D
) },
2532 { "femms", { XX
}, 0 },
2533 { "", { MX
, EM
, OPSUF
}, 0 }, /* See OP_3DNowSuffix. */
2535 { PREFIX_TABLE (PREFIX_0F10
) },
2536 { PREFIX_TABLE (PREFIX_0F11
) },
2537 { PREFIX_TABLE (PREFIX_0F12
) },
2538 { MOD_TABLE (MOD_0F13
) },
2539 { "unpcklpX", { XM
, EXx
}, PREFIX_OPCODE
},
2540 { "unpckhpX", { XM
, EXx
}, PREFIX_OPCODE
},
2541 { PREFIX_TABLE (PREFIX_0F16
) },
2542 { MOD_TABLE (MOD_0F17
) },
2544 { REG_TABLE (REG_0F18
) },
2545 { "nopQ", { Ev
}, 0 },
2546 { PREFIX_TABLE (PREFIX_0F1A
) },
2547 { PREFIX_TABLE (PREFIX_0F1B
) },
2548 { PREFIX_TABLE (PREFIX_0F1C
) },
2549 { "nopQ", { Ev
}, 0 },
2550 { PREFIX_TABLE (PREFIX_0F1E
) },
2551 { "nopQ", { Ev
}, 0 },
2553 { "movZ", { Rm
, Cm
}, 0 },
2554 { "movZ", { Rm
, Dm
}, 0 },
2555 { "movZ", { Cm
, Rm
}, 0 },
2556 { "movZ", { Dm
, Rm
}, 0 },
2557 { MOD_TABLE (MOD_0F24
) },
2559 { MOD_TABLE (MOD_0F26
) },
2562 { "movapX", { XM
, EXx
}, PREFIX_OPCODE
},
2563 { "movapX", { EXxS
, XM
}, PREFIX_OPCODE
},
2564 { PREFIX_TABLE (PREFIX_0F2A
) },
2565 { PREFIX_TABLE (PREFIX_0F2B
) },
2566 { PREFIX_TABLE (PREFIX_0F2C
) },
2567 { PREFIX_TABLE (PREFIX_0F2D
) },
2568 { PREFIX_TABLE (PREFIX_0F2E
) },
2569 { PREFIX_TABLE (PREFIX_0F2F
) },
2571 { "wrmsr", { XX
}, 0 },
2572 { "rdtsc", { XX
}, 0 },
2573 { "rdmsr", { XX
}, 0 },
2574 { "rdpmc", { XX
}, 0 },
2575 { "sysenter", { SEP
}, 0 },
2576 { "sysexit", { SEP
}, 0 },
2578 { "getsec", { XX
}, 0 },
2580 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38
, PREFIX_OPCODE
) },
2582 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A
, PREFIX_OPCODE
) },
2589 { "cmovoS", { Gv
, Ev
}, 0 },
2590 { "cmovnoS", { Gv
, Ev
}, 0 },
2591 { "cmovbS", { Gv
, Ev
}, 0 },
2592 { "cmovaeS", { Gv
, Ev
}, 0 },
2593 { "cmoveS", { Gv
, Ev
}, 0 },
2594 { "cmovneS", { Gv
, Ev
}, 0 },
2595 { "cmovbeS", { Gv
, Ev
}, 0 },
2596 { "cmovaS", { Gv
, Ev
}, 0 },
2598 { "cmovsS", { Gv
, Ev
}, 0 },
2599 { "cmovnsS", { Gv
, Ev
}, 0 },
2600 { "cmovpS", { Gv
, Ev
}, 0 },
2601 { "cmovnpS", { Gv
, Ev
}, 0 },
2602 { "cmovlS", { Gv
, Ev
}, 0 },
2603 { "cmovgeS", { Gv
, Ev
}, 0 },
2604 { "cmovleS", { Gv
, Ev
}, 0 },
2605 { "cmovgS", { Gv
, Ev
}, 0 },
2607 { MOD_TABLE (MOD_0F50
) },
2608 { PREFIX_TABLE (PREFIX_0F51
) },
2609 { PREFIX_TABLE (PREFIX_0F52
) },
2610 { PREFIX_TABLE (PREFIX_0F53
) },
2611 { "andpX", { XM
, EXx
}, PREFIX_OPCODE
},
2612 { "andnpX", { XM
, EXx
}, PREFIX_OPCODE
},
2613 { "orpX", { XM
, EXx
}, PREFIX_OPCODE
},
2614 { "xorpX", { XM
, EXx
}, PREFIX_OPCODE
},
2616 { PREFIX_TABLE (PREFIX_0F58
) },
2617 { PREFIX_TABLE (PREFIX_0F59
) },
2618 { PREFIX_TABLE (PREFIX_0F5A
) },
2619 { PREFIX_TABLE (PREFIX_0F5B
) },
2620 { PREFIX_TABLE (PREFIX_0F5C
) },
2621 { PREFIX_TABLE (PREFIX_0F5D
) },
2622 { PREFIX_TABLE (PREFIX_0F5E
) },
2623 { PREFIX_TABLE (PREFIX_0F5F
) },
2625 { PREFIX_TABLE (PREFIX_0F60
) },
2626 { PREFIX_TABLE (PREFIX_0F61
) },
2627 { PREFIX_TABLE (PREFIX_0F62
) },
2628 { "packsswb", { MX
, EM
}, PREFIX_OPCODE
},
2629 { "pcmpgtb", { MX
, EM
}, PREFIX_OPCODE
},
2630 { "pcmpgtw", { MX
, EM
}, PREFIX_OPCODE
},
2631 { "pcmpgtd", { MX
, EM
}, PREFIX_OPCODE
},
2632 { "packuswb", { MX
, EM
}, PREFIX_OPCODE
},
2634 { "punpckhbw", { MX
, EM
}, PREFIX_OPCODE
},
2635 { "punpckhwd", { MX
, EM
}, PREFIX_OPCODE
},
2636 { "punpckhdq", { MX
, EM
}, PREFIX_OPCODE
},
2637 { "packssdw", { MX
, EM
}, PREFIX_OPCODE
},
2638 { PREFIX_TABLE (PREFIX_0F6C
) },
2639 { PREFIX_TABLE (PREFIX_0F6D
) },
2640 { "movK", { MX
, Edq
}, PREFIX_OPCODE
},
2641 { PREFIX_TABLE (PREFIX_0F6F
) },
2643 { PREFIX_TABLE (PREFIX_0F70
) },
2644 { REG_TABLE (REG_0F71
) },
2645 { REG_TABLE (REG_0F72
) },
2646 { REG_TABLE (REG_0F73
) },
2647 { "pcmpeqb", { MX
, EM
}, PREFIX_OPCODE
},
2648 { "pcmpeqw", { MX
, EM
}, PREFIX_OPCODE
},
2649 { "pcmpeqd", { MX
, EM
}, PREFIX_OPCODE
},
2650 { "emms", { XX
}, PREFIX_OPCODE
},
2652 { PREFIX_TABLE (PREFIX_0F78
) },
2653 { PREFIX_TABLE (PREFIX_0F79
) },
2656 { PREFIX_TABLE (PREFIX_0F7C
) },
2657 { PREFIX_TABLE (PREFIX_0F7D
) },
2658 { PREFIX_TABLE (PREFIX_0F7E
) },
2659 { PREFIX_TABLE (PREFIX_0F7F
) },
2661 { "joH", { Jv
, BND
, cond_jump_flag
}, 0 },
2662 { "jnoH", { Jv
, BND
, cond_jump_flag
}, 0 },
2663 { "jbH", { Jv
, BND
, cond_jump_flag
}, 0 },
2664 { "jaeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2665 { "jeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2666 { "jneH", { Jv
, BND
, cond_jump_flag
}, 0 },
2667 { "jbeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2668 { "jaH", { Jv
, BND
, cond_jump_flag
}, 0 },
2670 { "jsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2671 { "jnsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2672 { "jpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2673 { "jnpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2674 { "jlH", { Jv
, BND
, cond_jump_flag
}, 0 },
2675 { "jgeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2676 { "jleH", { Jv
, BND
, cond_jump_flag
}, 0 },
2677 { "jgH", { Jv
, BND
, cond_jump_flag
}, 0 },
2679 { "seto", { Eb
}, 0 },
2680 { "setno", { Eb
}, 0 },
2681 { "setb", { Eb
}, 0 },
2682 { "setae", { Eb
}, 0 },
2683 { "sete", { Eb
}, 0 },
2684 { "setne", { Eb
}, 0 },
2685 { "setbe", { Eb
}, 0 },
2686 { "seta", { Eb
}, 0 },
2688 { "sets", { Eb
}, 0 },
2689 { "setns", { Eb
}, 0 },
2690 { "setp", { Eb
}, 0 },
2691 { "setnp", { Eb
}, 0 },
2692 { "setl", { Eb
}, 0 },
2693 { "setge", { Eb
}, 0 },
2694 { "setle", { Eb
}, 0 },
2695 { "setg", { Eb
}, 0 },
2697 { "pushT", { fs
}, 0 },
2698 { "popT", { fs
}, 0 },
2699 { "cpuid", { XX
}, 0 },
2700 { "btS", { Ev
, Gv
}, 0 },
2701 { "shldS", { Ev
, Gv
, Ib
}, 0 },
2702 { "shldS", { Ev
, Gv
, CL
}, 0 },
2703 { REG_TABLE (REG_0FA6
) },
2704 { REG_TABLE (REG_0FA7
) },
2706 { "pushT", { gs
}, 0 },
2707 { "popT", { gs
}, 0 },
2708 { "rsm", { XX
}, 0 },
2709 { "btsS", { Evh1
, Gv
}, 0 },
2710 { "shrdS", { Ev
, Gv
, Ib
}, 0 },
2711 { "shrdS", { Ev
, Gv
, CL
}, 0 },
2712 { REG_TABLE (REG_0FAE
) },
2713 { "imulS", { Gv
, Ev
}, 0 },
2715 { "cmpxchgB", { Ebh1
, Gb
}, 0 },
2716 { "cmpxchgS", { Evh1
, Gv
}, 0 },
2717 { MOD_TABLE (MOD_0FB2
) },
2718 { "btrS", { Evh1
, Gv
}, 0 },
2719 { MOD_TABLE (MOD_0FB4
) },
2720 { MOD_TABLE (MOD_0FB5
) },
2721 { "movz{bR|x}", { Gv
, Eb
}, 0 },
2722 { "movz{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movzww ! */
2724 { PREFIX_TABLE (PREFIX_0FB8
) },
2725 { "ud1S", { Gv
, Ev
}, 0 },
2726 { REG_TABLE (REG_0FBA
) },
2727 { "btcS", { Evh1
, Gv
}, 0 },
2728 { PREFIX_TABLE (PREFIX_0FBC
) },
2729 { PREFIX_TABLE (PREFIX_0FBD
) },
2730 { "movs{bR|x}", { Gv
, Eb
}, 0 },
2731 { "movs{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movsww ! */
2733 { "xaddB", { Ebh1
, Gb
}, 0 },
2734 { "xaddS", { Evh1
, Gv
}, 0 },
2735 { PREFIX_TABLE (PREFIX_0FC2
) },
2736 { MOD_TABLE (MOD_0FC3
) },
2737 { "pinsrw", { MX
, Edqw
, Ib
}, PREFIX_OPCODE
},
2738 { "pextrw", { Gdq
, MS
, Ib
}, PREFIX_OPCODE
},
2739 { "shufpX", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
2740 { REG_TABLE (REG_0FC7
) },
2742 { "bswap", { RMeAX
}, 0 },
2743 { "bswap", { RMeCX
}, 0 },
2744 { "bswap", { RMeDX
}, 0 },
2745 { "bswap", { RMeBX
}, 0 },
2746 { "bswap", { RMeSP
}, 0 },
2747 { "bswap", { RMeBP
}, 0 },
2748 { "bswap", { RMeSI
}, 0 },
2749 { "bswap", { RMeDI
}, 0 },
2751 { PREFIX_TABLE (PREFIX_0FD0
) },
2752 { "psrlw", { MX
, EM
}, PREFIX_OPCODE
},
2753 { "psrld", { MX
, EM
}, PREFIX_OPCODE
},
2754 { "psrlq", { MX
, EM
}, PREFIX_OPCODE
},
2755 { "paddq", { MX
, EM
}, PREFIX_OPCODE
},
2756 { "pmullw", { MX
, EM
}, PREFIX_OPCODE
},
2757 { PREFIX_TABLE (PREFIX_0FD6
) },
2758 { MOD_TABLE (MOD_0FD7
) },
2760 { "psubusb", { MX
, EM
}, PREFIX_OPCODE
},
2761 { "psubusw", { MX
, EM
}, PREFIX_OPCODE
},
2762 { "pminub", { MX
, EM
}, PREFIX_OPCODE
},
2763 { "pand", { MX
, EM
}, PREFIX_OPCODE
},
2764 { "paddusb", { MX
, EM
}, PREFIX_OPCODE
},
2765 { "paddusw", { MX
, EM
}, PREFIX_OPCODE
},
2766 { "pmaxub", { MX
, EM
}, PREFIX_OPCODE
},
2767 { "pandn", { MX
, EM
}, PREFIX_OPCODE
},
2769 { "pavgb", { MX
, EM
}, PREFIX_OPCODE
},
2770 { "psraw", { MX
, EM
}, PREFIX_OPCODE
},
2771 { "psrad", { MX
, EM
}, PREFIX_OPCODE
},
2772 { "pavgw", { MX
, EM
}, PREFIX_OPCODE
},
2773 { "pmulhuw", { MX
, EM
}, PREFIX_OPCODE
},
2774 { "pmulhw", { MX
, EM
}, PREFIX_OPCODE
},
2775 { PREFIX_TABLE (PREFIX_0FE6
) },
2776 { PREFIX_TABLE (PREFIX_0FE7
) },
2778 { "psubsb", { MX
, EM
}, PREFIX_OPCODE
},
2779 { "psubsw", { MX
, EM
}, PREFIX_OPCODE
},
2780 { "pminsw", { MX
, EM
}, PREFIX_OPCODE
},
2781 { "por", { MX
, EM
}, PREFIX_OPCODE
},
2782 { "paddsb", { MX
, EM
}, PREFIX_OPCODE
},
2783 { "paddsw", { MX
, EM
}, PREFIX_OPCODE
},
2784 { "pmaxsw", { MX
, EM
}, PREFIX_OPCODE
},
2785 { "pxor", { MX
, EM
}, PREFIX_OPCODE
},
2787 { PREFIX_TABLE (PREFIX_0FF0
) },
2788 { "psllw", { MX
, EM
}, PREFIX_OPCODE
},
2789 { "pslld", { MX
, EM
}, PREFIX_OPCODE
},
2790 { "psllq", { MX
, EM
}, PREFIX_OPCODE
},
2791 { "pmuludq", { MX
, EM
}, PREFIX_OPCODE
},
2792 { "pmaddwd", { MX
, EM
}, PREFIX_OPCODE
},
2793 { "psadbw", { MX
, EM
}, PREFIX_OPCODE
},
2794 { PREFIX_TABLE (PREFIX_0FF7
) },
2796 { "psubb", { MX
, EM
}, PREFIX_OPCODE
},
2797 { "psubw", { MX
, EM
}, PREFIX_OPCODE
},
2798 { "psubd", { MX
, EM
}, PREFIX_OPCODE
},
2799 { "psubq", { MX
, EM
}, PREFIX_OPCODE
},
2800 { "paddb", { MX
, EM
}, PREFIX_OPCODE
},
2801 { "paddw", { MX
, EM
}, PREFIX_OPCODE
},
2802 { "paddd", { MX
, EM
}, PREFIX_OPCODE
},
2803 { "ud0S", { Gv
, Ev
}, 0 },
2806 static const unsigned char onebyte_has_modrm
[256] = {
2807 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2808 /* ------------------------------- */
2809 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2810 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2811 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2812 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2813 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2814 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2815 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2816 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2817 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2818 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2819 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2820 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2821 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2822 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2823 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2824 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2825 /* ------------------------------- */
2826 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2829 static const unsigned char twobyte_has_modrm
[256] = {
2830 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2831 /* ------------------------------- */
2832 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2833 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2834 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2835 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2836 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2837 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2838 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2839 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2840 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2841 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2842 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2843 /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2844 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2845 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2846 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2847 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */
2848 /* ------------------------------- */
2849 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2852 static char obuf
[100];
2854 static char *mnemonicendp
;
2855 static char scratchbuf
[100];
2856 static unsigned char *start_codep
;
2857 static unsigned char *insn_codep
;
2858 static unsigned char *codep
;
2859 static unsigned char *end_codep
;
2860 static int last_lock_prefix
;
2861 static int last_repz_prefix
;
2862 static int last_repnz_prefix
;
2863 static int last_data_prefix
;
2864 static int last_addr_prefix
;
2865 static int last_rex_prefix
;
2866 static int last_seg_prefix
;
2867 static int fwait_prefix
;
2868 /* The active segment register prefix. */
2869 static int active_seg_prefix
;
2870 #define MAX_CODE_LENGTH 15
2871 /* We can up to 14 prefixes since the maximum instruction length is
2873 static int all_prefixes
[MAX_CODE_LENGTH
- 1];
2874 static disassemble_info
*the_info
;
2882 static unsigned char need_modrm
;
2892 int register_specifier
;
2899 int mask_register_specifier
;
2905 static unsigned char need_vex
;
2906 static unsigned char need_vex_reg
;
2907 static unsigned char vex_w_done
;
2915 /* If we are accessing mod/rm/reg without need_modrm set, then the
2916 values are stale. Hitting this abort likely indicates that you
2917 need to update onebyte_has_modrm or twobyte_has_modrm. */
2918 #define MODRM_CHECK if (!need_modrm) abort ()
2920 static const char **names64
;
2921 static const char **names32
;
2922 static const char **names16
;
2923 static const char **names8
;
2924 static const char **names8rex
;
2925 static const char **names_seg
;
2926 static const char *index64
;
2927 static const char *index32
;
2928 static const char **index16
;
2929 static const char **names_bnd
;
2931 static const char *intel_names64
[] = {
2932 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2933 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2935 static const char *intel_names32
[] = {
2936 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2937 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2939 static const char *intel_names16
[] = {
2940 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2941 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2943 static const char *intel_names8
[] = {
2944 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2946 static const char *intel_names8rex
[] = {
2947 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2948 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2950 static const char *intel_names_seg
[] = {
2951 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2953 static const char *intel_index64
= "riz";
2954 static const char *intel_index32
= "eiz";
2955 static const char *intel_index16
[] = {
2956 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2959 static const char *att_names64
[] = {
2960 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2961 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2963 static const char *att_names32
[] = {
2964 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2965 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2967 static const char *att_names16
[] = {
2968 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2969 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2971 static const char *att_names8
[] = {
2972 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2974 static const char *att_names8rex
[] = {
2975 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2976 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2978 static const char *att_names_seg
[] = {
2979 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2981 static const char *att_index64
= "%riz";
2982 static const char *att_index32
= "%eiz";
2983 static const char *att_index16
[] = {
2984 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2987 static const char **names_mm
;
2988 static const char *intel_names_mm
[] = {
2989 "mm0", "mm1", "mm2", "mm3",
2990 "mm4", "mm5", "mm6", "mm7"
2992 static const char *att_names_mm
[] = {
2993 "%mm0", "%mm1", "%mm2", "%mm3",
2994 "%mm4", "%mm5", "%mm6", "%mm7"
2997 static const char *intel_names_bnd
[] = {
2998 "bnd0", "bnd1", "bnd2", "bnd3"
3001 static const char *att_names_bnd
[] = {
3002 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3005 static const char **names_xmm
;
3006 static const char *intel_names_xmm
[] = {
3007 "xmm0", "xmm1", "xmm2", "xmm3",
3008 "xmm4", "xmm5", "xmm6", "xmm7",
3009 "xmm8", "xmm9", "xmm10", "xmm11",
3010 "xmm12", "xmm13", "xmm14", "xmm15",
3011 "xmm16", "xmm17", "xmm18", "xmm19",
3012 "xmm20", "xmm21", "xmm22", "xmm23",
3013 "xmm24", "xmm25", "xmm26", "xmm27",
3014 "xmm28", "xmm29", "xmm30", "xmm31"
3016 static const char *att_names_xmm
[] = {
3017 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3018 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3019 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3020 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3021 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3022 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3023 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3024 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3027 static const char **names_ymm
;
3028 static const char *intel_names_ymm
[] = {
3029 "ymm0", "ymm1", "ymm2", "ymm3",
3030 "ymm4", "ymm5", "ymm6", "ymm7",
3031 "ymm8", "ymm9", "ymm10", "ymm11",
3032 "ymm12", "ymm13", "ymm14", "ymm15",
3033 "ymm16", "ymm17", "ymm18", "ymm19",
3034 "ymm20", "ymm21", "ymm22", "ymm23",
3035 "ymm24", "ymm25", "ymm26", "ymm27",
3036 "ymm28", "ymm29", "ymm30", "ymm31"
3038 static const char *att_names_ymm
[] = {
3039 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3040 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3041 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3042 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3043 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3044 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3045 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3046 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3049 static const char **names_zmm
;
3050 static const char *intel_names_zmm
[] = {
3051 "zmm0", "zmm1", "zmm2", "zmm3",
3052 "zmm4", "zmm5", "zmm6", "zmm7",
3053 "zmm8", "zmm9", "zmm10", "zmm11",
3054 "zmm12", "zmm13", "zmm14", "zmm15",
3055 "zmm16", "zmm17", "zmm18", "zmm19",
3056 "zmm20", "zmm21", "zmm22", "zmm23",
3057 "zmm24", "zmm25", "zmm26", "zmm27",
3058 "zmm28", "zmm29", "zmm30", "zmm31"
3060 static const char *att_names_zmm
[] = {
3061 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3062 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3063 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3064 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3065 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3066 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3067 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3068 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3071 static const char **names_mask
;
3072 static const char *intel_names_mask
[] = {
3073 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3075 static const char *att_names_mask
[] = {
3076 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3079 static const char *names_rounding
[] =
3087 static const struct dis386 reg_table
[][8] = {
3090 { "addA", { Ebh1
, Ib
}, 0 },
3091 { "orA", { Ebh1
, Ib
}, 0 },
3092 { "adcA", { Ebh1
, Ib
}, 0 },
3093 { "sbbA", { Ebh1
, Ib
}, 0 },
3094 { "andA", { Ebh1
, Ib
}, 0 },
3095 { "subA", { Ebh1
, Ib
}, 0 },
3096 { "xorA", { Ebh1
, Ib
}, 0 },
3097 { "cmpA", { Eb
, Ib
}, 0 },
3101 { "addQ", { Evh1
, Iv
}, 0 },
3102 { "orQ", { Evh1
, Iv
}, 0 },
3103 { "adcQ", { Evh1
, Iv
}, 0 },
3104 { "sbbQ", { Evh1
, Iv
}, 0 },
3105 { "andQ", { Evh1
, Iv
}, 0 },
3106 { "subQ", { Evh1
, Iv
}, 0 },
3107 { "xorQ", { Evh1
, Iv
}, 0 },
3108 { "cmpQ", { Ev
, Iv
}, 0 },
3112 { "addQ", { Evh1
, sIb
}, 0 },
3113 { "orQ", { Evh1
, sIb
}, 0 },
3114 { "adcQ", { Evh1
, sIb
}, 0 },
3115 { "sbbQ", { Evh1
, sIb
}, 0 },
3116 { "andQ", { Evh1
, sIb
}, 0 },
3117 { "subQ", { Evh1
, sIb
}, 0 },
3118 { "xorQ", { Evh1
, sIb
}, 0 },
3119 { "cmpQ", { Ev
, sIb
}, 0 },
3123 { "popU", { stackEv
}, 0 },
3124 { XOP_8F_TABLE (XOP_09
) },
3128 { XOP_8F_TABLE (XOP_09
) },
3132 { "rolA", { Eb
, Ib
}, 0 },
3133 { "rorA", { Eb
, Ib
}, 0 },
3134 { "rclA", { Eb
, Ib
}, 0 },
3135 { "rcrA", { Eb
, Ib
}, 0 },
3136 { "shlA", { Eb
, Ib
}, 0 },
3137 { "shrA", { Eb
, Ib
}, 0 },
3138 { "shlA", { Eb
, Ib
}, 0 },
3139 { "sarA", { Eb
, Ib
}, 0 },
3143 { "rolQ", { Ev
, Ib
}, 0 },
3144 { "rorQ", { Ev
, Ib
}, 0 },
3145 { "rclQ", { Ev
, Ib
}, 0 },
3146 { "rcrQ", { Ev
, Ib
}, 0 },
3147 { "shlQ", { Ev
, Ib
}, 0 },
3148 { "shrQ", { Ev
, Ib
}, 0 },
3149 { "shlQ", { Ev
, Ib
}, 0 },
3150 { "sarQ", { Ev
, Ib
}, 0 },
3154 { "movA", { Ebh3
, Ib
}, 0 },
3161 { MOD_TABLE (MOD_C6_REG_7
) },
3165 { "movQ", { Evh3
, Iv
}, 0 },
3172 { MOD_TABLE (MOD_C7_REG_7
) },
3176 { "rolA", { Eb
, I1
}, 0 },
3177 { "rorA", { Eb
, I1
}, 0 },
3178 { "rclA", { Eb
, I1
}, 0 },
3179 { "rcrA", { Eb
, I1
}, 0 },
3180 { "shlA", { Eb
, I1
}, 0 },
3181 { "shrA", { Eb
, I1
}, 0 },
3182 { "shlA", { Eb
, I1
}, 0 },
3183 { "sarA", { Eb
, I1
}, 0 },
3187 { "rolQ", { Ev
, I1
}, 0 },
3188 { "rorQ", { Ev
, I1
}, 0 },
3189 { "rclQ", { Ev
, I1
}, 0 },
3190 { "rcrQ", { Ev
, I1
}, 0 },
3191 { "shlQ", { Ev
, I1
}, 0 },
3192 { "shrQ", { Ev
, I1
}, 0 },
3193 { "shlQ", { Ev
, I1
}, 0 },
3194 { "sarQ", { Ev
, I1
}, 0 },
3198 { "rolA", { Eb
, CL
}, 0 },
3199 { "rorA", { Eb
, CL
}, 0 },
3200 { "rclA", { Eb
, CL
}, 0 },
3201 { "rcrA", { Eb
, CL
}, 0 },
3202 { "shlA", { Eb
, CL
}, 0 },
3203 { "shrA", { Eb
, CL
}, 0 },
3204 { "shlA", { Eb
, CL
}, 0 },
3205 { "sarA", { Eb
, CL
}, 0 },
3209 { "rolQ", { Ev
, CL
}, 0 },
3210 { "rorQ", { Ev
, CL
}, 0 },
3211 { "rclQ", { Ev
, CL
}, 0 },
3212 { "rcrQ", { Ev
, CL
}, 0 },
3213 { "shlQ", { Ev
, CL
}, 0 },
3214 { "shrQ", { Ev
, CL
}, 0 },
3215 { "shlQ", { Ev
, CL
}, 0 },
3216 { "sarQ", { Ev
, CL
}, 0 },
3220 { "testA", { Eb
, Ib
}, 0 },
3221 { "testA", { Eb
, Ib
}, 0 },
3222 { "notA", { Ebh1
}, 0 },
3223 { "negA", { Ebh1
}, 0 },
3224 { "mulA", { Eb
}, 0 }, /* Don't print the implicit %al register, */
3225 { "imulA", { Eb
}, 0 }, /* to distinguish these opcodes from other */
3226 { "divA", { Eb
}, 0 }, /* mul/imul opcodes. Do the same for div */
3227 { "idivA", { Eb
}, 0 }, /* and idiv for consistency. */
3231 { "testQ", { Ev
, Iv
}, 0 },
3232 { "testQ", { Ev
, Iv
}, 0 },
3233 { "notQ", { Evh1
}, 0 },
3234 { "negQ", { Evh1
}, 0 },
3235 { "mulQ", { Ev
}, 0 }, /* Don't print the implicit register. */
3236 { "imulQ", { Ev
}, 0 },
3237 { "divQ", { Ev
}, 0 },
3238 { "idivQ", { Ev
}, 0 },
3242 { "incA", { Ebh1
}, 0 },
3243 { "decA", { Ebh1
}, 0 },
3247 { "incQ", { Evh1
}, 0 },
3248 { "decQ", { Evh1
}, 0 },
3249 { "call{&|}", { NOTRACK
, indirEv
, BND
}, 0 },
3250 { MOD_TABLE (MOD_FF_REG_3
) },
3251 { "jmp{&|}", { NOTRACK
, indirEv
, BND
}, 0 },
3252 { MOD_TABLE (MOD_FF_REG_5
) },
3253 { "pushU", { stackEv
}, 0 },
3258 { "sldtD", { Sv
}, 0 },
3259 { "strD", { Sv
}, 0 },
3260 { "lldt", { Ew
}, 0 },
3261 { "ltr", { Ew
}, 0 },
3262 { "verr", { Ew
}, 0 },
3263 { "verw", { Ew
}, 0 },
3269 { MOD_TABLE (MOD_0F01_REG_0
) },
3270 { MOD_TABLE (MOD_0F01_REG_1
) },
3271 { MOD_TABLE (MOD_0F01_REG_2
) },
3272 { MOD_TABLE (MOD_0F01_REG_3
) },
3273 { "smswD", { Sv
}, 0 },
3274 { MOD_TABLE (MOD_0F01_REG_5
) },
3275 { "lmsw", { Ew
}, 0 },
3276 { MOD_TABLE (MOD_0F01_REG_7
) },
3280 { "prefetch", { Mb
}, 0 },
3281 { "prefetchw", { Mb
}, 0 },
3282 { "prefetchwt1", { Mb
}, 0 },
3283 { "prefetch", { Mb
}, 0 },
3284 { "prefetch", { Mb
}, 0 },
3285 { "prefetch", { Mb
}, 0 },
3286 { "prefetch", { Mb
}, 0 },
3287 { "prefetch", { Mb
}, 0 },
3291 { MOD_TABLE (MOD_0F18_REG_0
) },
3292 { MOD_TABLE (MOD_0F18_REG_1
) },
3293 { MOD_TABLE (MOD_0F18_REG_2
) },
3294 { MOD_TABLE (MOD_0F18_REG_3
) },
3295 { MOD_TABLE (MOD_0F18_REG_4
) },
3296 { MOD_TABLE (MOD_0F18_REG_5
) },
3297 { MOD_TABLE (MOD_0F18_REG_6
) },
3298 { MOD_TABLE (MOD_0F18_REG_7
) },
3300 /* REG_0F1C_P_0_MOD_0 */
3302 { "cldemote", { Mb
}, 0 },
3303 { "nopQ", { Ev
}, 0 },
3304 { "nopQ", { Ev
}, 0 },
3305 { "nopQ", { Ev
}, 0 },
3306 { "nopQ", { Ev
}, 0 },
3307 { "nopQ", { Ev
}, 0 },
3308 { "nopQ", { Ev
}, 0 },
3309 { "nopQ", { Ev
}, 0 },
3311 /* REG_0F1E_P_1_MOD_3 */
3313 { "nopQ", { Ev
}, 0 },
3314 { "rdsspK", { Rdq
}, PREFIX_OPCODE
},
3315 { "nopQ", { Ev
}, 0 },
3316 { "nopQ", { Ev
}, 0 },
3317 { "nopQ", { Ev
}, 0 },
3318 { "nopQ", { Ev
}, 0 },
3319 { "nopQ", { Ev
}, 0 },
3320 { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7
) },
3326 { MOD_TABLE (MOD_0F71_REG_2
) },
3328 { MOD_TABLE (MOD_0F71_REG_4
) },
3330 { MOD_TABLE (MOD_0F71_REG_6
) },
3336 { MOD_TABLE (MOD_0F72_REG_2
) },
3338 { MOD_TABLE (MOD_0F72_REG_4
) },
3340 { MOD_TABLE (MOD_0F72_REG_6
) },
3346 { MOD_TABLE (MOD_0F73_REG_2
) },
3347 { MOD_TABLE (MOD_0F73_REG_3
) },
3350 { MOD_TABLE (MOD_0F73_REG_6
) },
3351 { MOD_TABLE (MOD_0F73_REG_7
) },
3355 { "montmul", { { OP_0f07
, 0 } }, 0 },
3356 { "xsha1", { { OP_0f07
, 0 } }, 0 },
3357 { "xsha256", { { OP_0f07
, 0 } }, 0 },
3361 { "xstore-rng", { { OP_0f07
, 0 } }, 0 },
3362 { "xcrypt-ecb", { { OP_0f07
, 0 } }, 0 },
3363 { "xcrypt-cbc", { { OP_0f07
, 0 } }, 0 },
3364 { "xcrypt-ctr", { { OP_0f07
, 0 } }, 0 },
3365 { "xcrypt-cfb", { { OP_0f07
, 0 } }, 0 },
3366 { "xcrypt-ofb", { { OP_0f07
, 0 } }, 0 },
3370 { MOD_TABLE (MOD_0FAE_REG_0
) },
3371 { MOD_TABLE (MOD_0FAE_REG_1
) },
3372 { MOD_TABLE (MOD_0FAE_REG_2
) },
3373 { MOD_TABLE (MOD_0FAE_REG_3
) },
3374 { MOD_TABLE (MOD_0FAE_REG_4
) },
3375 { MOD_TABLE (MOD_0FAE_REG_5
) },
3376 { MOD_TABLE (MOD_0FAE_REG_6
) },
3377 { MOD_TABLE (MOD_0FAE_REG_7
) },
3385 { "btQ", { Ev
, Ib
}, 0 },
3386 { "btsQ", { Evh1
, Ib
}, 0 },
3387 { "btrQ", { Evh1
, Ib
}, 0 },
3388 { "btcQ", { Evh1
, Ib
}, 0 },
3393 { "cmpxchg8b", { { CMPXCHG8B_Fixup
, q_mode
} }, 0 },
3395 { MOD_TABLE (MOD_0FC7_REG_3
) },
3396 { MOD_TABLE (MOD_0FC7_REG_4
) },
3397 { MOD_TABLE (MOD_0FC7_REG_5
) },
3398 { MOD_TABLE (MOD_0FC7_REG_6
) },
3399 { MOD_TABLE (MOD_0FC7_REG_7
) },
3405 { MOD_TABLE (MOD_VEX_0F71_REG_2
) },
3407 { MOD_TABLE (MOD_VEX_0F71_REG_4
) },
3409 { MOD_TABLE (MOD_VEX_0F71_REG_6
) },
3415 { MOD_TABLE (MOD_VEX_0F72_REG_2
) },
3417 { MOD_TABLE (MOD_VEX_0F72_REG_4
) },
3419 { MOD_TABLE (MOD_VEX_0F72_REG_6
) },
3425 { MOD_TABLE (MOD_VEX_0F73_REG_2
) },
3426 { MOD_TABLE (MOD_VEX_0F73_REG_3
) },
3429 { MOD_TABLE (MOD_VEX_0F73_REG_6
) },
3430 { MOD_TABLE (MOD_VEX_0F73_REG_7
) },
3436 { MOD_TABLE (MOD_VEX_0FAE_REG_2
) },
3437 { MOD_TABLE (MOD_VEX_0FAE_REG_3
) },
3439 /* REG_VEX_0F38F3 */
3442 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1
) },
3443 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2
) },
3444 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3
) },
3448 { "llwpcb", { { OP_LWPCB_E
, 0 } }, 0 },
3449 { "slwpcb", { { OP_LWPCB_E
, 0 } }, 0 },
3453 { "lwpins", { { OP_LWP_E
, 0 }, Ed
, Id
}, 0 },
3454 { "lwpval", { { OP_LWP_E
, 0 }, Ed
, Id
}, 0 },
3456 /* REG_XOP_TBM_01 */
3459 { "blcfill", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3460 { "blsfill", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3461 { "blcs", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3462 { "tzmsk", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3463 { "blcic", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3464 { "blsic", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3465 { "t1mskc", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3467 /* REG_XOP_TBM_02 */
3470 { "blcmsk", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3475 { "blci", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3478 #include "i386-dis-evex-reg.h"
3481 static const struct dis386 prefix_table
[][4] = {
3484 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3485 { "pause", { XX
}, 0 },
3486 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3487 { NULL
, { { NULL
, 0 } }, PREFIX_IGNORED
}
3490 /* PREFIX_0F01_REG_3_RM_1 */
3492 { "vmmcall", { Skip_MODRM
}, 0 },
3493 { "vmgexit", { Skip_MODRM
}, 0 },
3495 { "vmgexit", { Skip_MODRM
}, 0 },
3498 /* PREFIX_0F01_REG_5_MOD_0 */
3501 { "rstorssp", { Mq
}, PREFIX_OPCODE
},
3504 /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3506 { "serialize", { Skip_MODRM
}, PREFIX_OPCODE
},
3507 { "setssbsy", { Skip_MODRM
}, PREFIX_OPCODE
},
3509 { "xsusldtrk", { Skip_MODRM
}, PREFIX_OPCODE
},
3512 /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
3517 { "xresldtrk", { Skip_MODRM
}, PREFIX_OPCODE
},
3520 /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3523 { "saveprevssp", { Skip_MODRM
}, PREFIX_OPCODE
},
3526 /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3528 { "monitorx", { { OP_Monitor
, 0 } }, 0 },
3529 { "mcommit", { Skip_MODRM
}, 0 },
3532 /* PREFIX_0F01_REG_7_MOD_3_RM_3 */
3534 { "mwaitx", { { OP_Mwait
, eBX_reg
} }, 0 },
3539 { "wbinvd", { XX
}, 0 },
3540 { "wbnoinvd", { XX
}, 0 },
3545 { "movups", { XM
, EXx
}, PREFIX_OPCODE
},
3546 { "movss", { XM
, EXd
}, PREFIX_OPCODE
},
3547 { "movupd", { XM
, EXx
}, PREFIX_OPCODE
},
3548 { "movsd", { XM
, EXq
}, PREFIX_OPCODE
},
3553 { "movups", { EXxS
, XM
}, PREFIX_OPCODE
},
3554 { "movss", { EXdS
, XM
}, PREFIX_OPCODE
},
3555 { "movupd", { EXxS
, XM
}, PREFIX_OPCODE
},
3556 { "movsd", { EXqS
, XM
}, PREFIX_OPCODE
},
3561 { MOD_TABLE (MOD_0F12_PREFIX_0
) },
3562 { "movsldup", { XM
, EXx
}, PREFIX_OPCODE
},
3563 { MOD_TABLE (MOD_0F12_PREFIX_2
) },
3564 { "movddup", { XM
, EXq
}, PREFIX_OPCODE
},
3569 { MOD_TABLE (MOD_0F16_PREFIX_0
) },
3570 { "movshdup", { XM
, EXx
}, PREFIX_OPCODE
},
3571 { MOD_TABLE (MOD_0F16_PREFIX_2
) },
3576 { MOD_TABLE (MOD_0F1A_PREFIX_0
) },
3577 { "bndcl", { Gbnd
, Ev_bnd
}, 0 },
3578 { "bndmov", { Gbnd
, Ebnd
}, 0 },
3579 { "bndcu", { Gbnd
, Ev_bnd
}, 0 },
3584 { MOD_TABLE (MOD_0F1B_PREFIX_0
) },
3585 { MOD_TABLE (MOD_0F1B_PREFIX_1
) },
3586 { "bndmov", { EbndS
, Gbnd
}, 0 },
3587 { "bndcn", { Gbnd
, Ev_bnd
}, 0 },
3592 { MOD_TABLE (MOD_0F1C_PREFIX_0
) },
3593 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3594 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3595 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3600 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3601 { MOD_TABLE (MOD_0F1E_PREFIX_1
) },
3602 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3603 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3608 { "cvtpi2ps", { XM
, EMCq
}, PREFIX_OPCODE
},
3609 { "cvtsi2ss%LQ", { XM
, Edq
}, PREFIX_OPCODE
},
3610 { "cvtpi2pd", { XM
, EMCq
}, PREFIX_OPCODE
},
3611 { "cvtsi2sd%LQ", { XM
, Edq
}, 0 },
3616 { MOD_TABLE (MOD_0F2B_PREFIX_0
) },
3617 { MOD_TABLE (MOD_0F2B_PREFIX_1
) },
3618 { MOD_TABLE (MOD_0F2B_PREFIX_2
) },
3619 { MOD_TABLE (MOD_0F2B_PREFIX_3
) },
3624 { "cvttps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3625 { "cvttss2si", { Gdq
, EXd
}, PREFIX_OPCODE
},
3626 { "cvttpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3627 { "cvttsd2si", { Gdq
, EXq
}, PREFIX_OPCODE
},
3632 { "cvtps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3633 { "cvtss2si", { Gdq
, EXd
}, PREFIX_OPCODE
},
3634 { "cvtpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3635 { "cvtsd2si", { Gdq
, EXq
}, PREFIX_OPCODE
},
3640 { "ucomiss",{ XM
, EXd
}, 0 },
3642 { "ucomisd",{ XM
, EXq
}, 0 },
3647 { "comiss", { XM
, EXd
}, 0 },
3649 { "comisd", { XM
, EXq
}, 0 },
3654 { "sqrtps", { XM
, EXx
}, PREFIX_OPCODE
},
3655 { "sqrtss", { XM
, EXd
}, PREFIX_OPCODE
},
3656 { "sqrtpd", { XM
, EXx
}, PREFIX_OPCODE
},
3657 { "sqrtsd", { XM
, EXq
}, PREFIX_OPCODE
},
3662 { "rsqrtps",{ XM
, EXx
}, PREFIX_OPCODE
},
3663 { "rsqrtss",{ XM
, EXd
}, PREFIX_OPCODE
},
3668 { "rcpps", { XM
, EXx
}, PREFIX_OPCODE
},
3669 { "rcpss", { XM
, EXd
}, PREFIX_OPCODE
},
3674 { "addps", { XM
, EXx
}, PREFIX_OPCODE
},
3675 { "addss", { XM
, EXd
}, PREFIX_OPCODE
},
3676 { "addpd", { XM
, EXx
}, PREFIX_OPCODE
},
3677 { "addsd", { XM
, EXq
}, PREFIX_OPCODE
},
3682 { "mulps", { XM
, EXx
}, PREFIX_OPCODE
},
3683 { "mulss", { XM
, EXd
}, PREFIX_OPCODE
},
3684 { "mulpd", { XM
, EXx
}, PREFIX_OPCODE
},
3685 { "mulsd", { XM
, EXq
}, PREFIX_OPCODE
},
3690 { "cvtps2pd", { XM
, EXq
}, PREFIX_OPCODE
},
3691 { "cvtss2sd", { XM
, EXd
}, PREFIX_OPCODE
},
3692 { "cvtpd2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3693 { "cvtsd2ss", { XM
, EXq
}, PREFIX_OPCODE
},
3698 { "cvtdq2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3699 { "cvttps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3700 { "cvtps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3705 { "subps", { XM
, EXx
}, PREFIX_OPCODE
},
3706 { "subss", { XM
, EXd
}, PREFIX_OPCODE
},
3707 { "subpd", { XM
, EXx
}, PREFIX_OPCODE
},
3708 { "subsd", { XM
, EXq
}, PREFIX_OPCODE
},
3713 { "minps", { XM
, EXx
}, PREFIX_OPCODE
},
3714 { "minss", { XM
, EXd
}, PREFIX_OPCODE
},
3715 { "minpd", { XM
, EXx
}, PREFIX_OPCODE
},
3716 { "minsd", { XM
, EXq
}, PREFIX_OPCODE
},
3721 { "divps", { XM
, EXx
}, PREFIX_OPCODE
},
3722 { "divss", { XM
, EXd
}, PREFIX_OPCODE
},
3723 { "divpd", { XM
, EXx
}, PREFIX_OPCODE
},
3724 { "divsd", { XM
, EXq
}, PREFIX_OPCODE
},
3729 { "maxps", { XM
, EXx
}, PREFIX_OPCODE
},
3730 { "maxss", { XM
, EXd
}, PREFIX_OPCODE
},
3731 { "maxpd", { XM
, EXx
}, PREFIX_OPCODE
},
3732 { "maxsd", { XM
, EXq
}, PREFIX_OPCODE
},
3737 { "punpcklbw",{ MX
, EMd
}, PREFIX_OPCODE
},
3739 { "punpcklbw",{ MX
, EMx
}, PREFIX_OPCODE
},
3744 { "punpcklwd",{ MX
, EMd
}, PREFIX_OPCODE
},
3746 { "punpcklwd",{ MX
, EMx
}, PREFIX_OPCODE
},
3751 { "punpckldq",{ MX
, EMd
}, PREFIX_OPCODE
},
3753 { "punpckldq",{ MX
, EMx
}, PREFIX_OPCODE
},
3760 { "punpcklqdq", { XM
, EXx
}, PREFIX_OPCODE
},
3767 { "punpckhqdq", { XM
, EXx
}, PREFIX_OPCODE
},
3772 { "movq", { MX
, EM
}, PREFIX_OPCODE
},
3773 { "movdqu", { XM
, EXx
}, PREFIX_OPCODE
},
3774 { "movdqa", { XM
, EXx
}, PREFIX_OPCODE
},
3779 { "pshufw", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
3780 { "pshufhw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3781 { "pshufd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3782 { "pshuflw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3785 /* PREFIX_0F73_REG_3 */
3789 { "psrldq", { XS
, Ib
}, 0 },
3792 /* PREFIX_0F73_REG_7 */
3796 { "pslldq", { XS
, Ib
}, 0 },
3801 {"vmread", { Em
, Gm
}, 0 },
3803 {"extrq", { XS
, Ib
, Ib
}, 0 },
3804 {"insertq", { XM
, XS
, Ib
, Ib
}, 0 },
3809 {"vmwrite", { Gm
, Em
}, 0 },
3811 {"extrq", { XM
, XS
}, 0 },
3812 {"insertq", { XM
, XS
}, 0 },
3819 { "haddpd", { XM
, EXx
}, PREFIX_OPCODE
},
3820 { "haddps", { XM
, EXx
}, PREFIX_OPCODE
},
3827 { "hsubpd", { XM
, EXx
}, PREFIX_OPCODE
},
3828 { "hsubps", { XM
, EXx
}, PREFIX_OPCODE
},
3833 { "movK", { Edq
, MX
}, PREFIX_OPCODE
},
3834 { "movq", { XM
, EXq
}, PREFIX_OPCODE
},
3835 { "movK", { Edq
, XM
}, PREFIX_OPCODE
},
3840 { "movq", { EMS
, MX
}, PREFIX_OPCODE
},
3841 { "movdqu", { EXxS
, XM
}, PREFIX_OPCODE
},
3842 { "movdqa", { EXxS
, XM
}, PREFIX_OPCODE
},
3845 /* PREFIX_0FAE_REG_0_MOD_3 */
3848 { "rdfsbase", { Ev
}, 0 },
3851 /* PREFIX_0FAE_REG_1_MOD_3 */
3854 { "rdgsbase", { Ev
}, 0 },
3857 /* PREFIX_0FAE_REG_2_MOD_3 */
3860 { "wrfsbase", { Ev
}, 0 },
3863 /* PREFIX_0FAE_REG_3_MOD_3 */
3866 { "wrgsbase", { Ev
}, 0 },
3869 /* PREFIX_0FAE_REG_4_MOD_0 */
3871 { "xsave", { FXSAVE
}, 0 },
3872 { "ptwrite%LQ", { Edq
}, 0 },
3875 /* PREFIX_0FAE_REG_4_MOD_3 */
3878 { "ptwrite%LQ", { Edq
}, 0 },
3881 /* PREFIX_0FAE_REG_5_MOD_0 */
3883 { "xrstor", { FXSAVE
}, PREFIX_OPCODE
},
3886 /* PREFIX_0FAE_REG_5_MOD_3 */
3888 { "lfence", { Skip_MODRM
}, 0 },
3889 { "incsspK", { Rdq
}, PREFIX_OPCODE
},
3892 /* PREFIX_0FAE_REG_6_MOD_0 */
3894 { "xsaveopt", { FXSAVE
}, PREFIX_OPCODE
},
3895 { "clrssbsy", { Mq
}, PREFIX_OPCODE
},
3896 { "clwb", { Mb
}, PREFIX_OPCODE
},
3899 /* PREFIX_0FAE_REG_6_MOD_3 */
3901 { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0
) },
3902 { "umonitor", { Eva
}, PREFIX_OPCODE
},
3903 { "tpause", { Edq
}, PREFIX_OPCODE
},
3904 { "umwait", { Edq
}, PREFIX_OPCODE
},
3907 /* PREFIX_0FAE_REG_7_MOD_0 */
3909 { "clflush", { Mb
}, 0 },
3911 { "clflushopt", { Mb
}, 0 },
3917 { "popcntS", { Gv
, Ev
}, 0 },
3922 { "bsfS", { Gv
, Ev
}, 0 },
3923 { "tzcntS", { Gv
, Ev
}, 0 },
3924 { "bsfS", { Gv
, Ev
}, 0 },
3929 { "bsrS", { Gv
, Ev
}, 0 },
3930 { "lzcntS", { Gv
, Ev
}, 0 },
3931 { "bsrS", { Gv
, Ev
}, 0 },
3936 { "cmpps", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
3937 { "cmpss", { XM
, EXd
, CMP
}, PREFIX_OPCODE
},
3938 { "cmppd", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
3939 { "cmpsd", { XM
, EXq
, CMP
}, PREFIX_OPCODE
},
3942 /* PREFIX_0FC3_MOD_0 */
3944 { "movntiS", { Edq
, Gdq
}, PREFIX_OPCODE
},
3947 /* PREFIX_0FC7_REG_6_MOD_0 */
3949 { "vmptrld",{ Mq
}, 0 },
3950 { "vmxon", { Mq
}, 0 },
3951 { "vmclear",{ Mq
}, 0 },
3954 /* PREFIX_0FC7_REG_6_MOD_3 */
3956 { "rdrand", { Ev
}, 0 },
3958 { "rdrand", { Ev
}, 0 }
3961 /* PREFIX_0FC7_REG_7_MOD_3 */
3963 { "rdseed", { Ev
}, 0 },
3964 { "rdpid", { Em
}, 0 },
3965 { "rdseed", { Ev
}, 0 },
3972 { "addsubpd", { XM
, EXx
}, 0 },
3973 { "addsubps", { XM
, EXx
}, 0 },
3979 { "movq2dq",{ XM
, MS
}, 0 },
3980 { "movq", { EXqS
, XM
}, 0 },
3981 { "movdq2q",{ MX
, XS
}, 0 },
3987 { "cvtdq2pd", { XM
, EXq
}, PREFIX_OPCODE
},
3988 { "cvttpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3989 { "cvtpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3994 { "movntq", { Mq
, MX
}, PREFIX_OPCODE
},
3996 { MOD_TABLE (MOD_0FE7_PREFIX_2
) },
4004 { MOD_TABLE (MOD_0FF0_PREFIX_3
) },
4009 { "maskmovq", { MX
, MS
}, PREFIX_OPCODE
},
4011 { "maskmovdqu", { XM
, XS
}, PREFIX_OPCODE
},
4018 { "pblendvb", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4025 { "blendvps", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4032 { "blendvpd", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4039 { "ptest", { XM
, EXx
}, PREFIX_OPCODE
},
4046 { "pmovsxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4053 { "pmovsxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4060 { "pmovsxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4067 { "pmovsxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4074 { "pmovsxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4081 { "pmovsxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4088 { "pmuldq", { XM
, EXx
}, PREFIX_OPCODE
},
4095 { "pcmpeqq", { XM
, EXx
}, PREFIX_OPCODE
},
4102 { MOD_TABLE (MOD_0F382A_PREFIX_2
) },
4109 { "packusdw", { XM
, EXx
}, PREFIX_OPCODE
},
4116 { "pmovzxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4123 { "pmovzxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4130 { "pmovzxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4137 { "pmovzxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4144 { "pmovzxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4151 { "pmovzxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4158 { "pcmpgtq", { XM
, EXx
}, PREFIX_OPCODE
},
4165 { "pminsb", { XM
, EXx
}, PREFIX_OPCODE
},
4172 { "pminsd", { XM
, EXx
}, PREFIX_OPCODE
},
4179 { "pminuw", { XM
, EXx
}, PREFIX_OPCODE
},
4186 { "pminud", { XM
, EXx
}, PREFIX_OPCODE
},
4193 { "pmaxsb", { XM
, EXx
}, PREFIX_OPCODE
},
4200 { "pmaxsd", { XM
, EXx
}, PREFIX_OPCODE
},
4207 { "pmaxuw", { XM
, EXx
}, PREFIX_OPCODE
},
4214 { "pmaxud", { XM
, EXx
}, PREFIX_OPCODE
},
4221 { "pmulld", { XM
, EXx
}, PREFIX_OPCODE
},
4228 { "phminposuw", { XM
, EXx
}, PREFIX_OPCODE
},
4235 { "invept", { Gm
, Mo
}, PREFIX_OPCODE
},
4242 { "invvpid", { Gm
, Mo
}, PREFIX_OPCODE
},
4249 { "invpcid", { Gm
, M
}, PREFIX_OPCODE
},
4254 { "sha1nexte", { XM
, EXxmm
}, PREFIX_OPCODE
},
4259 { "sha1msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4264 { "sha1msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4269 { "sha256rnds2", { XM
, EXxmm
, XMM0
}, PREFIX_OPCODE
},
4274 { "sha256msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4279 { "sha256msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4286 { "gf2p8mulb", { XM
, EXxmm
}, PREFIX_OPCODE
},
4293 { "aesimc", { XM
, EXx
}, PREFIX_OPCODE
},
4300 { "aesenc", { XM
, EXx
}, PREFIX_OPCODE
},
4307 { "aesenclast", { XM
, EXx
}, PREFIX_OPCODE
},
4314 { "aesdec", { XM
, EXx
}, PREFIX_OPCODE
},
4321 { "aesdeclast", { XM
, EXx
}, PREFIX_OPCODE
},
4326 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4328 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4329 { "crc32", { Gdq
, { CRC32_Fixup
, b_mode
} }, PREFIX_OPCODE
},
4334 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
}, PREFIX_OPCODE
},
4336 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
}, PREFIX_OPCODE
},
4337 { "crc32", { Gdq
, { CRC32_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4344 { MOD_TABLE (MOD_0F38F5_PREFIX_2
) },
4349 { MOD_TABLE (MOD_0F38F6_PREFIX_0
) },
4350 { "adoxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4351 { "adcxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4358 { MOD_TABLE (MOD_0F38F8_PREFIX_1
) },
4359 { MOD_TABLE (MOD_0F38F8_PREFIX_2
) },
4360 { MOD_TABLE (MOD_0F38F8_PREFIX_3
) },
4365 { MOD_TABLE (MOD_0F38F9_PREFIX_0
) },
4372 { "roundps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4379 { "roundpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4386 { "roundss", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4393 { "roundsd", { XM
, EXq
, Ib
}, PREFIX_OPCODE
},
4400 { "blendps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4407 { "blendpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4414 { "pblendw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4421 { "pextrb", { Edqb
, XM
, Ib
}, PREFIX_OPCODE
},
4428 { "pextrw", { Edqw
, XM
, Ib
}, PREFIX_OPCODE
},
4435 { "pextrK", { Edq
, XM
, Ib
}, PREFIX_OPCODE
},
4442 { "extractps", { Edqd
, XM
, Ib
}, PREFIX_OPCODE
},
4449 { "pinsrb", { XM
, Edqb
, Ib
}, PREFIX_OPCODE
},
4456 { "insertps", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4463 { "pinsrK", { XM
, Edq
, Ib
}, PREFIX_OPCODE
},
4470 { "dpps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4477 { "dppd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4484 { "mpsadbw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4491 { "pclmulqdq", { XM
, EXx
, PCLMUL
}, PREFIX_OPCODE
},
4498 { "pcmpestrm", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, PREFIX_OPCODE
},
4505 { "pcmpestri", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, PREFIX_OPCODE
},
4512 { "pcmpistrm", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4519 { "pcmpistri", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4524 { "sha1rnds4", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4531 { "gf2p8affineqb", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4538 { "gf2p8affineinvqb", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4545 { "aeskeygenassist", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4548 /* PREFIX_VEX_0F10 */
4550 { "vmovups", { XM
, EXx
}, 0 },
4551 { "vmovss", { XMVexScalar
, VexScalar
, EXxmm_md
}, 0 },
4552 { "vmovupd", { XM
, EXx
}, 0 },
4553 { "vmovsd", { XMVexScalar
, VexScalar
, EXxmm_mq
}, 0 },
4556 /* PREFIX_VEX_0F11 */
4558 { "vmovups", { EXxS
, XM
}, 0 },
4559 { "vmovss", { EXdVexScalarS
, VexScalar
, XMScalar
}, 0 },
4560 { "vmovupd", { EXxS
, XM
}, 0 },
4561 { "vmovsd", { EXqVexScalarS
, VexScalar
, XMScalar
}, 0 },
4564 /* PREFIX_VEX_0F12 */
4566 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0
) },
4567 { "vmovsldup", { XM
, EXx
}, 0 },
4568 { MOD_TABLE (MOD_VEX_0F12_PREFIX_2
) },
4569 { "vmovddup", { XM
, EXymmq
}, 0 },
4572 /* PREFIX_VEX_0F16 */
4574 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0
) },
4575 { "vmovshdup", { XM
, EXx
}, 0 },
4576 { MOD_TABLE (MOD_VEX_0F16_PREFIX_2
) },
4579 /* PREFIX_VEX_0F2A */
4582 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Edq
}, 0 },
4584 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Edq
}, 0 },
4587 /* PREFIX_VEX_0F2C */
4590 { "vcvttss2si", { Gdq
, EXxmm_md
}, 0 },
4592 { "vcvttsd2si", { Gdq
, EXxmm_mq
}, 0 },
4595 /* PREFIX_VEX_0F2D */
4598 { "vcvtss2si", { Gdq
, EXxmm_md
}, 0 },
4600 { "vcvtsd2si", { Gdq
, EXxmm_mq
}, 0 },
4603 /* PREFIX_VEX_0F2E */
4605 { "vucomiss", { XMScalar
, EXxmm_md
}, 0 },
4607 { "vucomisd", { XMScalar
, EXxmm_mq
}, 0 },
4610 /* PREFIX_VEX_0F2F */
4612 { "vcomiss", { XMScalar
, EXxmm_md
}, 0 },
4614 { "vcomisd", { XMScalar
, EXxmm_mq
}, 0 },
4617 /* PREFIX_VEX_0F41 */
4619 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0
) },
4621 { VEX_LEN_TABLE (VEX_LEN_0F41_P_2
) },
4624 /* PREFIX_VEX_0F42 */
4626 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0
) },
4628 { VEX_LEN_TABLE (VEX_LEN_0F42_P_2
) },
4631 /* PREFIX_VEX_0F44 */
4633 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0
) },
4635 { VEX_LEN_TABLE (VEX_LEN_0F44_P_2
) },
4638 /* PREFIX_VEX_0F45 */
4640 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0
) },
4642 { VEX_LEN_TABLE (VEX_LEN_0F45_P_2
) },
4645 /* PREFIX_VEX_0F46 */
4647 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0
) },
4649 { VEX_LEN_TABLE (VEX_LEN_0F46_P_2
) },
4652 /* PREFIX_VEX_0F47 */
4654 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0
) },
4656 { VEX_LEN_TABLE (VEX_LEN_0F47_P_2
) },
4659 /* PREFIX_VEX_0F4A */
4661 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0
) },
4663 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2
) },
4666 /* PREFIX_VEX_0F4B */
4668 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0
) },
4670 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2
) },
4673 /* PREFIX_VEX_0F51 */
4675 { "vsqrtps", { XM
, EXx
}, 0 },
4676 { "vsqrtss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4677 { "vsqrtpd", { XM
, EXx
}, 0 },
4678 { "vsqrtsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
4681 /* PREFIX_VEX_0F52 */
4683 { "vrsqrtps", { XM
, EXx
}, 0 },
4684 { "vrsqrtss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4687 /* PREFIX_VEX_0F53 */
4689 { "vrcpps", { XM
, EXx
}, 0 },
4690 { "vrcpss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4693 /* PREFIX_VEX_0F58 */
4695 { "vaddps", { XM
, Vex
, EXx
}, 0 },
4696 { "vaddss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4697 { "vaddpd", { XM
, Vex
, EXx
}, 0 },
4698 { "vaddsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
4701 /* PREFIX_VEX_0F59 */
4703 { "vmulps", { XM
, Vex
, EXx
}, 0 },
4704 { "vmulss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4705 { "vmulpd", { XM
, Vex
, EXx
}, 0 },
4706 { "vmulsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
4709 /* PREFIX_VEX_0F5A */
4711 { "vcvtps2pd", { XM
, EXxmmq
}, 0 },
4712 { "vcvtss2sd", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4713 { "vcvtpd2ps%XY",{ XMM
, EXx
}, 0 },
4714 { "vcvtsd2ss", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
4717 /* PREFIX_VEX_0F5B */
4719 { "vcvtdq2ps", { XM
, EXx
}, 0 },
4720 { "vcvttps2dq", { XM
, EXx
}, 0 },
4721 { "vcvtps2dq", { XM
, EXx
}, 0 },
4724 /* PREFIX_VEX_0F5C */
4726 { "vsubps", { XM
, Vex
, EXx
}, 0 },
4727 { "vsubss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4728 { "vsubpd", { XM
, Vex
, EXx
}, 0 },
4729 { "vsubsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
4732 /* PREFIX_VEX_0F5D */
4734 { "vminps", { XM
, Vex
, EXx
}, 0 },
4735 { "vminss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4736 { "vminpd", { XM
, Vex
, EXx
}, 0 },
4737 { "vminsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
4740 /* PREFIX_VEX_0F5E */
4742 { "vdivps", { XM
, Vex
, EXx
}, 0 },
4743 { "vdivss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4744 { "vdivpd", { XM
, Vex
, EXx
}, 0 },
4745 { "vdivsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
4748 /* PREFIX_VEX_0F5F */
4750 { "vmaxps", { XM
, Vex
, EXx
}, 0 },
4751 { "vmaxss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4752 { "vmaxpd", { XM
, Vex
, EXx
}, 0 },
4753 { "vmaxsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
4756 /* PREFIX_VEX_0F60 */
4760 { "vpunpcklbw", { XM
, Vex
, EXx
}, 0 },
4763 /* PREFIX_VEX_0F61 */
4767 { "vpunpcklwd", { XM
, Vex
, EXx
}, 0 },
4770 /* PREFIX_VEX_0F62 */
4774 { "vpunpckldq", { XM
, Vex
, EXx
}, 0 },
4777 /* PREFIX_VEX_0F63 */
4781 { "vpacksswb", { XM
, Vex
, EXx
}, 0 },
4784 /* PREFIX_VEX_0F64 */
4788 { "vpcmpgtb", { XM
, Vex
, EXx
}, 0 },
4791 /* PREFIX_VEX_0F65 */
4795 { "vpcmpgtw", { XM
, Vex
, EXx
}, 0 },
4798 /* PREFIX_VEX_0F66 */
4802 { "vpcmpgtd", { XM
, Vex
, EXx
}, 0 },
4805 /* PREFIX_VEX_0F67 */
4809 { "vpackuswb", { XM
, Vex
, EXx
}, 0 },
4812 /* PREFIX_VEX_0F68 */
4816 { "vpunpckhbw", { XM
, Vex
, EXx
}, 0 },
4819 /* PREFIX_VEX_0F69 */
4823 { "vpunpckhwd", { XM
, Vex
, EXx
}, 0 },
4826 /* PREFIX_VEX_0F6A */
4830 { "vpunpckhdq", { XM
, Vex
, EXx
}, 0 },
4833 /* PREFIX_VEX_0F6B */
4837 { "vpackssdw", { XM
, Vex
, EXx
}, 0 },
4840 /* PREFIX_VEX_0F6C */
4844 { "vpunpcklqdq", { XM
, Vex
, EXx
}, 0 },
4847 /* PREFIX_VEX_0F6D */
4851 { "vpunpckhqdq", { XM
, Vex
, EXx
}, 0 },
4854 /* PREFIX_VEX_0F6E */
4858 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2
) },
4861 /* PREFIX_VEX_0F6F */
4864 { "vmovdqu", { XM
, EXx
}, 0 },
4865 { "vmovdqa", { XM
, EXx
}, 0 },
4868 /* PREFIX_VEX_0F70 */
4871 { "vpshufhw", { XM
, EXx
, Ib
}, 0 },
4872 { "vpshufd", { XM
, EXx
, Ib
}, 0 },
4873 { "vpshuflw", { XM
, EXx
, Ib
}, 0 },
4876 /* PREFIX_VEX_0F71_REG_2 */
4880 { "vpsrlw", { Vex
, XS
, Ib
}, 0 },
4883 /* PREFIX_VEX_0F71_REG_4 */
4887 { "vpsraw", { Vex
, XS
, Ib
}, 0 },
4890 /* PREFIX_VEX_0F71_REG_6 */
4894 { "vpsllw", { Vex
, XS
, Ib
}, 0 },
4897 /* PREFIX_VEX_0F72_REG_2 */
4901 { "vpsrld", { Vex
, XS
, Ib
}, 0 },
4904 /* PREFIX_VEX_0F72_REG_4 */
4908 { "vpsrad", { Vex
, XS
, Ib
}, 0 },
4911 /* PREFIX_VEX_0F72_REG_6 */
4915 { "vpslld", { Vex
, XS
, Ib
}, 0 },
4918 /* PREFIX_VEX_0F73_REG_2 */
4922 { "vpsrlq", { Vex
, XS
, Ib
}, 0 },
4925 /* PREFIX_VEX_0F73_REG_3 */
4929 { "vpsrldq", { Vex
, XS
, Ib
}, 0 },
4932 /* PREFIX_VEX_0F73_REG_6 */
4936 { "vpsllq", { Vex
, XS
, Ib
}, 0 },
4939 /* PREFIX_VEX_0F73_REG_7 */
4943 { "vpslldq", { Vex
, XS
, Ib
}, 0 },
4946 /* PREFIX_VEX_0F74 */
4950 { "vpcmpeqb", { XM
, Vex
, EXx
}, 0 },
4953 /* PREFIX_VEX_0F75 */
4957 { "vpcmpeqw", { XM
, Vex
, EXx
}, 0 },
4960 /* PREFIX_VEX_0F76 */
4964 { "vpcmpeqd", { XM
, Vex
, EXx
}, 0 },
4967 /* PREFIX_VEX_0F77 */
4969 { VEX_LEN_TABLE (VEX_LEN_0F77_P_0
) },
4972 /* PREFIX_VEX_0F7C */
4976 { "vhaddpd", { XM
, Vex
, EXx
}, 0 },
4977 { "vhaddps", { XM
, Vex
, EXx
}, 0 },
4980 /* PREFIX_VEX_0F7D */
4984 { "vhsubpd", { XM
, Vex
, EXx
}, 0 },
4985 { "vhsubps", { XM
, Vex
, EXx
}, 0 },
4988 /* PREFIX_VEX_0F7E */
4991 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1
) },
4992 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2
) },
4995 /* PREFIX_VEX_0F7F */
4998 { "vmovdqu", { EXxS
, XM
}, 0 },
4999 { "vmovdqa", { EXxS
, XM
}, 0 },
5002 /* PREFIX_VEX_0F90 */
5004 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0
) },
5006 { VEX_LEN_TABLE (VEX_LEN_0F90_P_2
) },
5009 /* PREFIX_VEX_0F91 */
5011 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0
) },
5013 { VEX_LEN_TABLE (VEX_LEN_0F91_P_2
) },
5016 /* PREFIX_VEX_0F92 */
5018 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0
) },
5020 { VEX_LEN_TABLE (VEX_LEN_0F92_P_2
) },
5021 { VEX_LEN_TABLE (VEX_LEN_0F92_P_3
) },
5024 /* PREFIX_VEX_0F93 */
5026 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0
) },
5028 { VEX_LEN_TABLE (VEX_LEN_0F93_P_2
) },
5029 { VEX_LEN_TABLE (VEX_LEN_0F93_P_3
) },
5032 /* PREFIX_VEX_0F98 */
5034 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0
) },
5036 { VEX_LEN_TABLE (VEX_LEN_0F98_P_2
) },
5039 /* PREFIX_VEX_0F99 */
5041 { VEX_LEN_TABLE (VEX_LEN_0F99_P_0
) },
5043 { VEX_LEN_TABLE (VEX_LEN_0F99_P_2
) },
5046 /* PREFIX_VEX_0FC2 */
5048 { "vcmpps", { XM
, Vex
, EXx
, VCMP
}, 0 },
5049 { "vcmpss", { XMScalar
, VexScalar
, EXxmm_md
, VCMP
}, 0 },
5050 { "vcmppd", { XM
, Vex
, EXx
, VCMP
}, 0 },
5051 { "vcmpsd", { XMScalar
, VexScalar
, EXxmm_mq
, VCMP
}, 0 },
5054 /* PREFIX_VEX_0FC4 */
5058 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2
) },
5061 /* PREFIX_VEX_0FC5 */
5065 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2
) },
5068 /* PREFIX_VEX_0FD0 */
5072 { "vaddsubpd", { XM
, Vex
, EXx
}, 0 },
5073 { "vaddsubps", { XM
, Vex
, EXx
}, 0 },
5076 /* PREFIX_VEX_0FD1 */
5080 { "vpsrlw", { XM
, Vex
, EXxmm
}, 0 },
5083 /* PREFIX_VEX_0FD2 */
5087 { "vpsrld", { XM
, Vex
, EXxmm
}, 0 },
5090 /* PREFIX_VEX_0FD3 */
5094 { "vpsrlq", { XM
, Vex
, EXxmm
}, 0 },
5097 /* PREFIX_VEX_0FD4 */
5101 { "vpaddq", { XM
, Vex
, EXx
}, 0 },
5104 /* PREFIX_VEX_0FD5 */
5108 { "vpmullw", { XM
, Vex
, EXx
}, 0 },
5111 /* PREFIX_VEX_0FD6 */
5115 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2
) },
5118 /* PREFIX_VEX_0FD7 */
5122 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2
) },
5125 /* PREFIX_VEX_0FD8 */
5129 { "vpsubusb", { XM
, Vex
, EXx
}, 0 },
5132 /* PREFIX_VEX_0FD9 */
5136 { "vpsubusw", { XM
, Vex
, EXx
}, 0 },
5139 /* PREFIX_VEX_0FDA */
5143 { "vpminub", { XM
, Vex
, EXx
}, 0 },
5146 /* PREFIX_VEX_0FDB */
5150 { "vpand", { XM
, Vex
, EXx
}, 0 },
5153 /* PREFIX_VEX_0FDC */
5157 { "vpaddusb", { XM
, Vex
, EXx
}, 0 },
5160 /* PREFIX_VEX_0FDD */
5164 { "vpaddusw", { XM
, Vex
, EXx
}, 0 },
5167 /* PREFIX_VEX_0FDE */
5171 { "vpmaxub", { XM
, Vex
, EXx
}, 0 },
5174 /* PREFIX_VEX_0FDF */
5178 { "vpandn", { XM
, Vex
, EXx
}, 0 },
5181 /* PREFIX_VEX_0FE0 */
5185 { "vpavgb", { XM
, Vex
, EXx
}, 0 },
5188 /* PREFIX_VEX_0FE1 */
5192 { "vpsraw", { XM
, Vex
, EXxmm
}, 0 },
5195 /* PREFIX_VEX_0FE2 */
5199 { "vpsrad", { XM
, Vex
, EXxmm
}, 0 },
5202 /* PREFIX_VEX_0FE3 */
5206 { "vpavgw", { XM
, Vex
, EXx
}, 0 },
5209 /* PREFIX_VEX_0FE4 */
5213 { "vpmulhuw", { XM
, Vex
, EXx
}, 0 },
5216 /* PREFIX_VEX_0FE5 */
5220 { "vpmulhw", { XM
, Vex
, EXx
}, 0 },
5223 /* PREFIX_VEX_0FE6 */
5226 { "vcvtdq2pd", { XM
, EXxmmq
}, 0 },
5227 { "vcvttpd2dq%XY", { XMM
, EXx
}, 0 },
5228 { "vcvtpd2dq%XY", { XMM
, EXx
}, 0 },
5231 /* PREFIX_VEX_0FE7 */
5235 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2
) },
5238 /* PREFIX_VEX_0FE8 */
5242 { "vpsubsb", { XM
, Vex
, EXx
}, 0 },
5245 /* PREFIX_VEX_0FE9 */
5249 { "vpsubsw", { XM
, Vex
, EXx
}, 0 },
5252 /* PREFIX_VEX_0FEA */
5256 { "vpminsw", { XM
, Vex
, EXx
}, 0 },
5259 /* PREFIX_VEX_0FEB */
5263 { "vpor", { XM
, Vex
, EXx
}, 0 },
5266 /* PREFIX_VEX_0FEC */
5270 { "vpaddsb", { XM
, Vex
, EXx
}, 0 },
5273 /* PREFIX_VEX_0FED */
5277 { "vpaddsw", { XM
, Vex
, EXx
}, 0 },
5280 /* PREFIX_VEX_0FEE */
5284 { "vpmaxsw", { XM
, Vex
, EXx
}, 0 },
5287 /* PREFIX_VEX_0FEF */
5291 { "vpxor", { XM
, Vex
, EXx
}, 0 },
5294 /* PREFIX_VEX_0FF0 */
5299 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3
) },
5302 /* PREFIX_VEX_0FF1 */
5306 { "vpsllw", { XM
, Vex
, EXxmm
}, 0 },
5309 /* PREFIX_VEX_0FF2 */
5313 { "vpslld", { XM
, Vex
, EXxmm
}, 0 },
5316 /* PREFIX_VEX_0FF3 */
5320 { "vpsllq", { XM
, Vex
, EXxmm
}, 0 },
5323 /* PREFIX_VEX_0FF4 */
5327 { "vpmuludq", { XM
, Vex
, EXx
}, 0 },
5330 /* PREFIX_VEX_0FF5 */
5334 { "vpmaddwd", { XM
, Vex
, EXx
}, 0 },
5337 /* PREFIX_VEX_0FF6 */
5341 { "vpsadbw", { XM
, Vex
, EXx
}, 0 },
5344 /* PREFIX_VEX_0FF7 */
5348 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2
) },
5351 /* PREFIX_VEX_0FF8 */
5355 { "vpsubb", { XM
, Vex
, EXx
}, 0 },
5358 /* PREFIX_VEX_0FF9 */
5362 { "vpsubw", { XM
, Vex
, EXx
}, 0 },
5365 /* PREFIX_VEX_0FFA */
5369 { "vpsubd", { XM
, Vex
, EXx
}, 0 },
5372 /* PREFIX_VEX_0FFB */
5376 { "vpsubq", { XM
, Vex
, EXx
}, 0 },
5379 /* PREFIX_VEX_0FFC */
5383 { "vpaddb", { XM
, Vex
, EXx
}, 0 },
5386 /* PREFIX_VEX_0FFD */
5390 { "vpaddw", { XM
, Vex
, EXx
}, 0 },
5393 /* PREFIX_VEX_0FFE */
5397 { "vpaddd", { XM
, Vex
, EXx
}, 0 },
5400 /* PREFIX_VEX_0F3800 */
5404 { "vpshufb", { XM
, Vex
, EXx
}, 0 },
5407 /* PREFIX_VEX_0F3801 */
5411 { "vphaddw", { XM
, Vex
, EXx
}, 0 },
5414 /* PREFIX_VEX_0F3802 */
5418 { "vphaddd", { XM
, Vex
, EXx
}, 0 },
5421 /* PREFIX_VEX_0F3803 */
5425 { "vphaddsw", { XM
, Vex
, EXx
}, 0 },
5428 /* PREFIX_VEX_0F3804 */
5432 { "vpmaddubsw", { XM
, Vex
, EXx
}, 0 },
5435 /* PREFIX_VEX_0F3805 */
5439 { "vphsubw", { XM
, Vex
, EXx
}, 0 },
5442 /* PREFIX_VEX_0F3806 */
5446 { "vphsubd", { XM
, Vex
, EXx
}, 0 },
5449 /* PREFIX_VEX_0F3807 */
5453 { "vphsubsw", { XM
, Vex
, EXx
}, 0 },
5456 /* PREFIX_VEX_0F3808 */
5460 { "vpsignb", { XM
, Vex
, EXx
}, 0 },
5463 /* PREFIX_VEX_0F3809 */
5467 { "vpsignw", { XM
, Vex
, EXx
}, 0 },
5470 /* PREFIX_VEX_0F380A */
5474 { "vpsignd", { XM
, Vex
, EXx
}, 0 },
5477 /* PREFIX_VEX_0F380B */
5481 { "vpmulhrsw", { XM
, Vex
, EXx
}, 0 },
5484 /* PREFIX_VEX_0F380C */
5488 { VEX_W_TABLE (VEX_W_0F380C_P_2
) },
5491 /* PREFIX_VEX_0F380D */
5495 { VEX_W_TABLE (VEX_W_0F380D_P_2
) },
5498 /* PREFIX_VEX_0F380E */
5502 { VEX_W_TABLE (VEX_W_0F380E_P_2
) },
5505 /* PREFIX_VEX_0F380F */
5509 { VEX_W_TABLE (VEX_W_0F380F_P_2
) },
5512 /* PREFIX_VEX_0F3813 */
5516 { VEX_W_TABLE (VEX_W_0F3813_P_2
) },
5519 /* PREFIX_VEX_0F3816 */
5523 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2
) },
5526 /* PREFIX_VEX_0F3817 */
5530 { "vptest", { XM
, EXx
}, 0 },
5533 /* PREFIX_VEX_0F3818 */
5537 { VEX_W_TABLE (VEX_W_0F3818_P_2
) },
5540 /* PREFIX_VEX_0F3819 */
5544 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2
) },
5547 /* PREFIX_VEX_0F381A */
5551 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2
) },
5554 /* PREFIX_VEX_0F381C */
5558 { "vpabsb", { XM
, EXx
}, 0 },
5561 /* PREFIX_VEX_0F381D */
5565 { "vpabsw", { XM
, EXx
}, 0 },
5568 /* PREFIX_VEX_0F381E */
5572 { "vpabsd", { XM
, EXx
}, 0 },
5575 /* PREFIX_VEX_0F3820 */
5579 { "vpmovsxbw", { XM
, EXxmmq
}, 0 },
5582 /* PREFIX_VEX_0F3821 */
5586 { "vpmovsxbd", { XM
, EXxmmqd
}, 0 },
5589 /* PREFIX_VEX_0F3822 */
5593 { "vpmovsxbq", { XM
, EXxmmdw
}, 0 },
5596 /* PREFIX_VEX_0F3823 */
5600 { "vpmovsxwd", { XM
, EXxmmq
}, 0 },
5603 /* PREFIX_VEX_0F3824 */
5607 { "vpmovsxwq", { XM
, EXxmmqd
}, 0 },
5610 /* PREFIX_VEX_0F3825 */
5614 { "vpmovsxdq", { XM
, EXxmmq
}, 0 },
5617 /* PREFIX_VEX_0F3828 */
5621 { "vpmuldq", { XM
, Vex
, EXx
}, 0 },
5624 /* PREFIX_VEX_0F3829 */
5628 { "vpcmpeqq", { XM
, Vex
, EXx
}, 0 },
5631 /* PREFIX_VEX_0F382A */
5635 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2
) },
5638 /* PREFIX_VEX_0F382B */
5642 { "vpackusdw", { XM
, Vex
, EXx
}, 0 },
5645 /* PREFIX_VEX_0F382C */
5649 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2
) },
5652 /* PREFIX_VEX_0F382D */
5656 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2
) },
5659 /* PREFIX_VEX_0F382E */
5663 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2
) },
5666 /* PREFIX_VEX_0F382F */
5670 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2
) },
5673 /* PREFIX_VEX_0F3830 */
5677 { "vpmovzxbw", { XM
, EXxmmq
}, 0 },
5680 /* PREFIX_VEX_0F3831 */
5684 { "vpmovzxbd", { XM
, EXxmmqd
}, 0 },
5687 /* PREFIX_VEX_0F3832 */
5691 { "vpmovzxbq", { XM
, EXxmmdw
}, 0 },
5694 /* PREFIX_VEX_0F3833 */
5698 { "vpmovzxwd", { XM
, EXxmmq
}, 0 },
5701 /* PREFIX_VEX_0F3834 */
5705 { "vpmovzxwq", { XM
, EXxmmqd
}, 0 },
5708 /* PREFIX_VEX_0F3835 */
5712 { "vpmovzxdq", { XM
, EXxmmq
}, 0 },
5715 /* PREFIX_VEX_0F3836 */
5719 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2
) },
5722 /* PREFIX_VEX_0F3837 */
5726 { "vpcmpgtq", { XM
, Vex
, EXx
}, 0 },
5729 /* PREFIX_VEX_0F3838 */
5733 { "vpminsb", { XM
, Vex
, EXx
}, 0 },
5736 /* PREFIX_VEX_0F3839 */
5740 { "vpminsd", { XM
, Vex
, EXx
}, 0 },
5743 /* PREFIX_VEX_0F383A */
5747 { "vpminuw", { XM
, Vex
, EXx
}, 0 },
5750 /* PREFIX_VEX_0F383B */
5754 { "vpminud", { XM
, Vex
, EXx
}, 0 },
5757 /* PREFIX_VEX_0F383C */
5761 { "vpmaxsb", { XM
, Vex
, EXx
}, 0 },
5764 /* PREFIX_VEX_0F383D */
5768 { "vpmaxsd", { XM
, Vex
, EXx
}, 0 },
5771 /* PREFIX_VEX_0F383E */
5775 { "vpmaxuw", { XM
, Vex
, EXx
}, 0 },
5778 /* PREFIX_VEX_0F383F */
5782 { "vpmaxud", { XM
, Vex
, EXx
}, 0 },
5785 /* PREFIX_VEX_0F3840 */
5789 { "vpmulld", { XM
, Vex
, EXx
}, 0 },
5792 /* PREFIX_VEX_0F3841 */
5796 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2
) },
5799 /* PREFIX_VEX_0F3845 */
5803 { "vpsrlv%LW", { XM
, Vex
, EXx
}, 0 },
5806 /* PREFIX_VEX_0F3846 */
5810 { VEX_W_TABLE (VEX_W_0F3846_P_2
) },
5813 /* PREFIX_VEX_0F3847 */
5817 { "vpsllv%LW", { XM
, Vex
, EXx
}, 0 },
5820 /* PREFIX_VEX_0F3858 */
5824 { VEX_W_TABLE (VEX_W_0F3858_P_2
) },
5827 /* PREFIX_VEX_0F3859 */
5831 { VEX_W_TABLE (VEX_W_0F3859_P_2
) },
5834 /* PREFIX_VEX_0F385A */
5838 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2
) },
5841 /* PREFIX_VEX_0F3878 */
5845 { VEX_W_TABLE (VEX_W_0F3878_P_2
) },
5848 /* PREFIX_VEX_0F3879 */
5852 { VEX_W_TABLE (VEX_W_0F3879_P_2
) },
5855 /* PREFIX_VEX_0F388C */
5859 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2
) },
5862 /* PREFIX_VEX_0F388E */
5866 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2
) },
5869 /* PREFIX_VEX_0F3890 */
5873 { "vpgatherd%LW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
5876 /* PREFIX_VEX_0F3891 */
5880 { "vpgatherq%LW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
5883 /* PREFIX_VEX_0F3892 */
5887 { "vgatherdp%XW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
5890 /* PREFIX_VEX_0F3893 */
5894 { "vgatherqp%XW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
5897 /* PREFIX_VEX_0F3896 */
5901 { "vfmaddsub132p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
5904 /* PREFIX_VEX_0F3897 */
5908 { "vfmsubadd132p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
5911 /* PREFIX_VEX_0F3898 */
5915 { "vfmadd132p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
5918 /* PREFIX_VEX_0F3899 */
5922 { "vfmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
5925 /* PREFIX_VEX_0F389A */
5929 { "vfmsub132p%XW", { XM
, Vex
, EXx
}, 0 },
5932 /* PREFIX_VEX_0F389B */
5936 { "vfmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
5939 /* PREFIX_VEX_0F389C */
5943 { "vfnmadd132p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
5946 /* PREFIX_VEX_0F389D */
5950 { "vfnmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
5953 /* PREFIX_VEX_0F389E */
5957 { "vfnmsub132p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
5960 /* PREFIX_VEX_0F389F */
5964 { "vfnmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
5967 /* PREFIX_VEX_0F38A6 */
5971 { "vfmaddsub213p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
5975 /* PREFIX_VEX_0F38A7 */
5979 { "vfmsubadd213p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
5982 /* PREFIX_VEX_0F38A8 */
5986 { "vfmadd213p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
5989 /* PREFIX_VEX_0F38A9 */
5993 { "vfmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
5996 /* PREFIX_VEX_0F38AA */
6000 { "vfmsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6003 /* PREFIX_VEX_0F38AB */
6007 { "vfmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6010 /* PREFIX_VEX_0F38AC */
6014 { "vfnmadd213p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6017 /* PREFIX_VEX_0F38AD */
6021 { "vfnmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
6024 /* PREFIX_VEX_0F38AE */
6028 { "vfnmsub213p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6031 /* PREFIX_VEX_0F38AF */
6035 { "vfnmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
6038 /* PREFIX_VEX_0F38B6 */
6042 { "vfmaddsub231p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6045 /* PREFIX_VEX_0F38B7 */
6049 { "vfmsubadd231p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6052 /* PREFIX_VEX_0F38B8 */
6056 { "vfmadd231p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6059 /* PREFIX_VEX_0F38B9 */
6063 { "vfmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
6066 /* PREFIX_VEX_0F38BA */
6070 { "vfmsub231p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6073 /* PREFIX_VEX_0F38BB */
6077 { "vfmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
6080 /* PREFIX_VEX_0F38BC */
6084 { "vfnmadd231p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6087 /* PREFIX_VEX_0F38BD */
6091 { "vfnmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
6094 /* PREFIX_VEX_0F38BE */
6098 { "vfnmsub231p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6101 /* PREFIX_VEX_0F38BF */
6105 { "vfnmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
6108 /* PREFIX_VEX_0F38CF */
6112 { VEX_W_TABLE (VEX_W_0F38CF_P_2
) },
6115 /* PREFIX_VEX_0F38DB */
6119 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2
) },
6122 /* PREFIX_VEX_0F38DC */
6126 { "vaesenc", { XM
, Vex
, EXx
}, 0 },
6129 /* PREFIX_VEX_0F38DD */
6133 { "vaesenclast", { XM
, Vex
, EXx
}, 0 },
6136 /* PREFIX_VEX_0F38DE */
6140 { "vaesdec", { XM
, Vex
, EXx
}, 0 },
6143 /* PREFIX_VEX_0F38DF */
6147 { "vaesdeclast", { XM
, Vex
, EXx
}, 0 },
6150 /* PREFIX_VEX_0F38F2 */
6152 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0
) },
6155 /* PREFIX_VEX_0F38F3_REG_1 */
6157 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0
) },
6160 /* PREFIX_VEX_0F38F3_REG_2 */
6162 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0
) },
6165 /* PREFIX_VEX_0F38F3_REG_3 */
6167 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0
) },
6170 /* PREFIX_VEX_0F38F5 */
6172 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0
) },
6173 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1
) },
6175 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3
) },
6178 /* PREFIX_VEX_0F38F6 */
6183 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3
) },
6186 /* PREFIX_VEX_0F38F7 */
6188 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0
) },
6189 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1
) },
6190 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2
) },
6191 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3
) },
6194 /* PREFIX_VEX_0F3A00 */
6198 { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2
) },
6201 /* PREFIX_VEX_0F3A01 */
6205 { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2
) },
6208 /* PREFIX_VEX_0F3A02 */
6212 { VEX_W_TABLE (VEX_W_0F3A02_P_2
) },
6215 /* PREFIX_VEX_0F3A04 */
6219 { VEX_W_TABLE (VEX_W_0F3A04_P_2
) },
6222 /* PREFIX_VEX_0F3A05 */
6226 { VEX_W_TABLE (VEX_W_0F3A05_P_2
) },
6229 /* PREFIX_VEX_0F3A06 */
6233 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2
) },
6236 /* PREFIX_VEX_0F3A08 */
6240 { "vroundps", { XM
, EXx
, Ib
}, 0 },
6243 /* PREFIX_VEX_0F3A09 */
6247 { "vroundpd", { XM
, EXx
, Ib
}, 0 },
6250 /* PREFIX_VEX_0F3A0A */
6254 { "vroundss", { XMScalar
, VexScalar
, EXxmm_md
, Ib
}, 0 },
6257 /* PREFIX_VEX_0F3A0B */
6261 { "vroundsd", { XMScalar
, VexScalar
, EXxmm_mq
, Ib
}, 0 },
6264 /* PREFIX_VEX_0F3A0C */
6268 { "vblendps", { XM
, Vex
, EXx
, Ib
}, 0 },
6271 /* PREFIX_VEX_0F3A0D */
6275 { "vblendpd", { XM
, Vex
, EXx
, Ib
}, 0 },
6278 /* PREFIX_VEX_0F3A0E */
6282 { "vpblendw", { XM
, Vex
, EXx
, Ib
}, 0 },
6285 /* PREFIX_VEX_0F3A0F */
6289 { "vpalignr", { XM
, Vex
, EXx
, Ib
}, 0 },
6292 /* PREFIX_VEX_0F3A14 */
6296 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2
) },
6299 /* PREFIX_VEX_0F3A15 */
6303 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2
) },
6306 /* PREFIX_VEX_0F3A16 */
6310 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2
) },
6313 /* PREFIX_VEX_0F3A17 */
6317 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2
) },
6320 /* PREFIX_VEX_0F3A18 */
6324 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2
) },
6327 /* PREFIX_VEX_0F3A19 */
6331 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2
) },
6334 /* PREFIX_VEX_0F3A1D */
6338 { VEX_W_TABLE (VEX_W_0F3A1D_P_2
) },
6341 /* PREFIX_VEX_0F3A20 */
6345 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2
) },
6348 /* PREFIX_VEX_0F3A21 */
6352 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2
) },
6355 /* PREFIX_VEX_0F3A22 */
6359 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2
) },
6362 /* PREFIX_VEX_0F3A30 */
6366 { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2
) },
6369 /* PREFIX_VEX_0F3A31 */
6373 { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2
) },
6376 /* PREFIX_VEX_0F3A32 */
6380 { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2
) },
6383 /* PREFIX_VEX_0F3A33 */
6387 { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2
) },
6390 /* PREFIX_VEX_0F3A38 */
6394 { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2
) },
6397 /* PREFIX_VEX_0F3A39 */
6401 { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2
) },
6404 /* PREFIX_VEX_0F3A40 */
6408 { "vdpps", { XM
, Vex
, EXx
, Ib
}, 0 },
6411 /* PREFIX_VEX_0F3A41 */
6415 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2
) },
6418 /* PREFIX_VEX_0F3A42 */
6422 { "vmpsadbw", { XM
, Vex
, EXx
, Ib
}, 0 },
6425 /* PREFIX_VEX_0F3A44 */
6429 { "vpclmulqdq", { XM
, Vex
, EXx
, PCLMUL
}, 0 },
6432 /* PREFIX_VEX_0F3A46 */
6436 { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2
) },
6439 /* PREFIX_VEX_0F3A48 */
6443 { VEX_W_TABLE (VEX_W_0F3A48_P_2
) },
6446 /* PREFIX_VEX_0F3A49 */
6450 { VEX_W_TABLE (VEX_W_0F3A49_P_2
) },
6453 /* PREFIX_VEX_0F3A4A */
6457 { VEX_W_TABLE (VEX_W_0F3A4A_P_2
) },
6460 /* PREFIX_VEX_0F3A4B */
6464 { VEX_W_TABLE (VEX_W_0F3A4B_P_2
) },
6467 /* PREFIX_VEX_0F3A4C */
6471 { VEX_W_TABLE (VEX_W_0F3A4C_P_2
) },
6474 /* PREFIX_VEX_0F3A5C */
6478 { "vfmaddsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6481 /* PREFIX_VEX_0F3A5D */
6485 { "vfmaddsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6488 /* PREFIX_VEX_0F3A5E */
6492 { "vfmsubaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6495 /* PREFIX_VEX_0F3A5F */
6499 { "vfmsubaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6502 /* PREFIX_VEX_0F3A60 */
6506 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2
) },
6510 /* PREFIX_VEX_0F3A61 */
6514 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2
) },
6517 /* PREFIX_VEX_0F3A62 */
6521 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2
) },
6524 /* PREFIX_VEX_0F3A63 */
6528 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2
) },
6531 /* PREFIX_VEX_0F3A68 */
6535 { "vfmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6538 /* PREFIX_VEX_0F3A69 */
6542 { "vfmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6545 /* PREFIX_VEX_0F3A6A */
6549 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2
) },
6552 /* PREFIX_VEX_0F3A6B */
6556 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2
) },
6559 /* PREFIX_VEX_0F3A6C */
6563 { "vfmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6566 /* PREFIX_VEX_0F3A6D */
6570 { "vfmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6573 /* PREFIX_VEX_0F3A6E */
6577 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2
) },
6580 /* PREFIX_VEX_0F3A6F */
6584 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2
) },
6587 /* PREFIX_VEX_0F3A78 */
6591 { "vfnmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6594 /* PREFIX_VEX_0F3A79 */
6598 { "vfnmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6601 /* PREFIX_VEX_0F3A7A */
6605 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2
) },
6608 /* PREFIX_VEX_0F3A7B */
6612 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2
) },
6615 /* PREFIX_VEX_0F3A7C */
6619 { "vfnmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6623 /* PREFIX_VEX_0F3A7D */
6627 { "vfnmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6630 /* PREFIX_VEX_0F3A7E */
6634 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2
) },
6637 /* PREFIX_VEX_0F3A7F */
6641 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2
) },
6644 /* PREFIX_VEX_0F3ACE */
6648 { VEX_W_TABLE (VEX_W_0F3ACE_P_2
) },
6651 /* PREFIX_VEX_0F3ACF */
6655 { VEX_W_TABLE (VEX_W_0F3ACF_P_2
) },
6658 /* PREFIX_VEX_0F3ADF */
6662 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2
) },
6665 /* PREFIX_VEX_0F3AF0 */
6670 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3
) },
6673 #include "i386-dis-evex-prefix.h"
6676 static const struct dis386 x86_64_table
[][2] = {
6679 { "pushP", { es
}, 0 },
6684 { "popP", { es
}, 0 },
6689 { "pushP", { cs
}, 0 },
6694 { "pushP", { ss
}, 0 },
6699 { "popP", { ss
}, 0 },
6704 { "pushP", { ds
}, 0 },
6709 { "popP", { ds
}, 0 },
6714 { "daa", { XX
}, 0 },
6719 { "das", { XX
}, 0 },
6724 { "aaa", { XX
}, 0 },
6729 { "aas", { XX
}, 0 },
6734 { "pushaP", { XX
}, 0 },
6739 { "popaP", { XX
}, 0 },
6744 { MOD_TABLE (MOD_62_32BIT
) },
6745 { EVEX_TABLE (EVEX_0F
) },
6750 { "arpl", { Ew
, Gw
}, 0 },
6751 { "movs", { { OP_G
, movsxd_mode
}, { MOVSXD_Fixup
, movsxd_mode
} }, 0 },
6756 { "ins{R|}", { Yzr
, indirDX
}, 0 },
6757 { "ins{G|}", { Yzr
, indirDX
}, 0 },
6762 { "outs{R|}", { indirDXr
, Xz
}, 0 },
6763 { "outs{G|}", { indirDXr
, Xz
}, 0 },
6768 /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */
6769 { REG_TABLE (REG_80
) },
6774 { "{l|}call{T|}", { Ap
}, 0 },
6779 { "retP", { Iw
, BND
}, 0 },
6780 { "ret@", { Iw
, BND
}, 0 },
6785 { "retP", { BND
}, 0 },
6786 { "ret@", { BND
}, 0 },
6791 { MOD_TABLE (MOD_C4_32BIT
) },
6792 { VEX_C4_TABLE (VEX_0F
) },
6797 { MOD_TABLE (MOD_C5_32BIT
) },
6798 { VEX_C5_TABLE (VEX_0F
) },
6803 { "into", { XX
}, 0 },
6808 { "aam", { Ib
}, 0 },
6813 { "aad", { Ib
}, 0 },
6818 { "callP", { Jv
, BND
}, 0 },
6819 { "call@", { Jv
, BND
}, 0 }
6824 { "jmpP", { Jv
, BND
}, 0 },
6825 { "jmp@", { Jv
, BND
}, 0 }
6830 { "{l|}jmp{T|}", { Ap
}, 0 },
6833 /* X86_64_0F01_REG_0 */
6835 { "sgdt{Q|Q}", { M
}, 0 },
6836 { "sgdt", { M
}, 0 },
6839 /* X86_64_0F01_REG_1 */
6841 { "sidt{Q|Q}", { M
}, 0 },
6842 { "sidt", { M
}, 0 },
6845 /* X86_64_0F01_REG_2 */
6847 { "lgdt{Q|Q}", { M
}, 0 },
6848 { "lgdt", { M
}, 0 },
6851 /* X86_64_0F01_REG_3 */
6853 { "lidt{Q|Q}", { M
}, 0 },
6854 { "lidt", { M
}, 0 },
6858 static const struct dis386 three_byte_table
[][256] = {
6860 /* THREE_BYTE_0F38 */
6863 { "pshufb", { MX
, EM
}, PREFIX_OPCODE
},
6864 { "phaddw", { MX
, EM
}, PREFIX_OPCODE
},
6865 { "phaddd", { MX
, EM
}, PREFIX_OPCODE
},
6866 { "phaddsw", { MX
, EM
}, PREFIX_OPCODE
},
6867 { "pmaddubsw", { MX
, EM
}, PREFIX_OPCODE
},
6868 { "phsubw", { MX
, EM
}, PREFIX_OPCODE
},
6869 { "phsubd", { MX
, EM
}, PREFIX_OPCODE
},
6870 { "phsubsw", { MX
, EM
}, PREFIX_OPCODE
},
6872 { "psignb", { MX
, EM
}, PREFIX_OPCODE
},
6873 { "psignw", { MX
, EM
}, PREFIX_OPCODE
},
6874 { "psignd", { MX
, EM
}, PREFIX_OPCODE
},
6875 { "pmulhrsw", { MX
, EM
}, PREFIX_OPCODE
},
6881 { PREFIX_TABLE (PREFIX_0F3810
) },
6885 { PREFIX_TABLE (PREFIX_0F3814
) },
6886 { PREFIX_TABLE (PREFIX_0F3815
) },
6888 { PREFIX_TABLE (PREFIX_0F3817
) },
6894 { "pabsb", { MX
, EM
}, PREFIX_OPCODE
},
6895 { "pabsw", { MX
, EM
}, PREFIX_OPCODE
},
6896 { "pabsd", { MX
, EM
}, PREFIX_OPCODE
},
6899 { PREFIX_TABLE (PREFIX_0F3820
) },
6900 { PREFIX_TABLE (PREFIX_0F3821
) },
6901 { PREFIX_TABLE (PREFIX_0F3822
) },
6902 { PREFIX_TABLE (PREFIX_0F3823
) },
6903 { PREFIX_TABLE (PREFIX_0F3824
) },
6904 { PREFIX_TABLE (PREFIX_0F3825
) },
6908 { PREFIX_TABLE (PREFIX_0F3828
) },
6909 { PREFIX_TABLE (PREFIX_0F3829
) },
6910 { PREFIX_TABLE (PREFIX_0F382A
) },
6911 { PREFIX_TABLE (PREFIX_0F382B
) },
6917 { PREFIX_TABLE (PREFIX_0F3830
) },
6918 { PREFIX_TABLE (PREFIX_0F3831
) },
6919 { PREFIX_TABLE (PREFIX_0F3832
) },
6920 { PREFIX_TABLE (PREFIX_0F3833
) },
6921 { PREFIX_TABLE (PREFIX_0F3834
) },
6922 { PREFIX_TABLE (PREFIX_0F3835
) },
6924 { PREFIX_TABLE (PREFIX_0F3837
) },
6926 { PREFIX_TABLE (PREFIX_0F3838
) },
6927 { PREFIX_TABLE (PREFIX_0F3839
) },
6928 { PREFIX_TABLE (PREFIX_0F383A
) },
6929 { PREFIX_TABLE (PREFIX_0F383B
) },
6930 { PREFIX_TABLE (PREFIX_0F383C
) },
6931 { PREFIX_TABLE (PREFIX_0F383D
) },
6932 { PREFIX_TABLE (PREFIX_0F383E
) },
6933 { PREFIX_TABLE (PREFIX_0F383F
) },
6935 { PREFIX_TABLE (PREFIX_0F3840
) },
6936 { PREFIX_TABLE (PREFIX_0F3841
) },
7007 { PREFIX_TABLE (PREFIX_0F3880
) },
7008 { PREFIX_TABLE (PREFIX_0F3881
) },
7009 { PREFIX_TABLE (PREFIX_0F3882
) },
7088 { PREFIX_TABLE (PREFIX_0F38C8
) },
7089 { PREFIX_TABLE (PREFIX_0F38C9
) },
7090 { PREFIX_TABLE (PREFIX_0F38CA
) },
7091 { PREFIX_TABLE (PREFIX_0F38CB
) },
7092 { PREFIX_TABLE (PREFIX_0F38CC
) },
7093 { PREFIX_TABLE (PREFIX_0F38CD
) },
7095 { PREFIX_TABLE (PREFIX_0F38CF
) },
7109 { PREFIX_TABLE (PREFIX_0F38DB
) },
7110 { PREFIX_TABLE (PREFIX_0F38DC
) },
7111 { PREFIX_TABLE (PREFIX_0F38DD
) },
7112 { PREFIX_TABLE (PREFIX_0F38DE
) },
7113 { PREFIX_TABLE (PREFIX_0F38DF
) },
7133 { PREFIX_TABLE (PREFIX_0F38F0
) },
7134 { PREFIX_TABLE (PREFIX_0F38F1
) },
7138 { PREFIX_TABLE (PREFIX_0F38F5
) },
7139 { PREFIX_TABLE (PREFIX_0F38F6
) },
7142 { PREFIX_TABLE (PREFIX_0F38F8
) },
7143 { PREFIX_TABLE (PREFIX_0F38F9
) },
7151 /* THREE_BYTE_0F3A */
7163 { PREFIX_TABLE (PREFIX_0F3A08
) },
7164 { PREFIX_TABLE (PREFIX_0F3A09
) },
7165 { PREFIX_TABLE (PREFIX_0F3A0A
) },
7166 { PREFIX_TABLE (PREFIX_0F3A0B
) },
7167 { PREFIX_TABLE (PREFIX_0F3A0C
) },
7168 { PREFIX_TABLE (PREFIX_0F3A0D
) },
7169 { PREFIX_TABLE (PREFIX_0F3A0E
) },
7170 { "palignr", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
7176 { PREFIX_TABLE (PREFIX_0F3A14
) },
7177 { PREFIX_TABLE (PREFIX_0F3A15
) },
7178 { PREFIX_TABLE (PREFIX_0F3A16
) },
7179 { PREFIX_TABLE (PREFIX_0F3A17
) },
7190 { PREFIX_TABLE (PREFIX_0F3A20
) },
7191 { PREFIX_TABLE (PREFIX_0F3A21
) },
7192 { PREFIX_TABLE (PREFIX_0F3A22
) },
7226 { PREFIX_TABLE (PREFIX_0F3A40
) },
7227 { PREFIX_TABLE (PREFIX_0F3A41
) },
7228 { PREFIX_TABLE (PREFIX_0F3A42
) },
7230 { PREFIX_TABLE (PREFIX_0F3A44
) },
7262 { PREFIX_TABLE (PREFIX_0F3A60
) },
7263 { PREFIX_TABLE (PREFIX_0F3A61
) },
7264 { PREFIX_TABLE (PREFIX_0F3A62
) },
7265 { PREFIX_TABLE (PREFIX_0F3A63
) },
7383 { PREFIX_TABLE (PREFIX_0F3ACC
) },
7385 { PREFIX_TABLE (PREFIX_0F3ACE
) },
7386 { PREFIX_TABLE (PREFIX_0F3ACF
) },
7404 { PREFIX_TABLE (PREFIX_0F3ADF
) },
7444 static const struct dis386 xop_table
[][256] = {
7597 { "vpmacssww", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7598 { "vpmacsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7599 { "vpmacssdql", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7607 { "vpmacssdd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7608 { "vpmacssdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7615 { "vpmacsww", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7616 { "vpmacswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7617 { "vpmacsdql", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7625 { "vpmacsdd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7626 { "vpmacsdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7630 { "vpcmov", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7631 { "vpperm", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7634 { "vpmadcsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7652 { "vpmadcswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7664 { "vprotb", { XM
, Vex_2src_1
, Ib
}, 0 },
7665 { "vprotw", { XM
, Vex_2src_1
, Ib
}, 0 },
7666 { "vprotd", { XM
, Vex_2src_1
, Ib
}, 0 },
7667 { "vprotq", { XM
, Vex_2src_1
, Ib
}, 0 },
7677 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC
) },
7678 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD
) },
7679 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE
) },
7680 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF
) },
7713 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC
) },
7714 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED
) },
7715 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE
) },
7716 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF
) },
7740 { REG_TABLE (REG_XOP_TBM_01
) },
7741 { REG_TABLE (REG_XOP_TBM_02
) },
7759 { REG_TABLE (REG_XOP_LWPCB
) },
7883 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80
) },
7884 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81
) },
7885 { "vfrczss", { XM
, EXd
}, 0 },
7886 { "vfrczsd", { XM
, EXq
}, 0 },
7901 { "vprotb", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7902 { "vprotw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7903 { "vprotd", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7904 { "vprotq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7905 { "vpshlb", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7906 { "vpshlw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7907 { "vpshld", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7908 { "vpshlq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7910 { "vpshab", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7911 { "vpshaw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7912 { "vpshad", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7913 { "vpshaq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7956 { "vphaddbw", { XM
, EXxmm
}, 0 },
7957 { "vphaddbd", { XM
, EXxmm
}, 0 },
7958 { "vphaddbq", { XM
, EXxmm
}, 0 },
7961 { "vphaddwd", { XM
, EXxmm
}, 0 },
7962 { "vphaddwq", { XM
, EXxmm
}, 0 },
7967 { "vphadddq", { XM
, EXxmm
}, 0 },
7974 { "vphaddubw", { XM
, EXxmm
}, 0 },
7975 { "vphaddubd", { XM
, EXxmm
}, 0 },
7976 { "vphaddubq", { XM
, EXxmm
}, 0 },
7979 { "vphadduwd", { XM
, EXxmm
}, 0 },
7980 { "vphadduwq", { XM
, EXxmm
}, 0 },
7985 { "vphaddudq", { XM
, EXxmm
}, 0 },
7992 { "vphsubbw", { XM
, EXxmm
}, 0 },
7993 { "vphsubwd", { XM
, EXxmm
}, 0 },
7994 { "vphsubdq", { XM
, EXxmm
}, 0 },
8048 { "bextrS", { Gdq
, Edq
, Id
}, 0 },
8050 { REG_TABLE (REG_XOP_LWP
) },
8320 static const struct dis386 vex_table
[][256] = {
8342 { PREFIX_TABLE (PREFIX_VEX_0F10
) },
8343 { PREFIX_TABLE (PREFIX_VEX_0F11
) },
8344 { PREFIX_TABLE (PREFIX_VEX_0F12
) },
8345 { MOD_TABLE (MOD_VEX_0F13
) },
8346 { "vunpcklpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
8347 { "vunpckhpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
8348 { PREFIX_TABLE (PREFIX_VEX_0F16
) },
8349 { MOD_TABLE (MOD_VEX_0F17
) },
8369 { "vmovapX", { XM
, EXx
}, PREFIX_OPCODE
},
8370 { "vmovapX", { EXxS
, XM
}, PREFIX_OPCODE
},
8371 { PREFIX_TABLE (PREFIX_VEX_0F2A
) },
8372 { MOD_TABLE (MOD_VEX_0F2B
) },
8373 { PREFIX_TABLE (PREFIX_VEX_0F2C
) },
8374 { PREFIX_TABLE (PREFIX_VEX_0F2D
) },
8375 { PREFIX_TABLE (PREFIX_VEX_0F2E
) },
8376 { PREFIX_TABLE (PREFIX_VEX_0F2F
) },
8397 { PREFIX_TABLE (PREFIX_VEX_0F41
) },
8398 { PREFIX_TABLE (PREFIX_VEX_0F42
) },
8400 { PREFIX_TABLE (PREFIX_VEX_0F44
) },
8401 { PREFIX_TABLE (PREFIX_VEX_0F45
) },
8402 { PREFIX_TABLE (PREFIX_VEX_0F46
) },
8403 { PREFIX_TABLE (PREFIX_VEX_0F47
) },
8407 { PREFIX_TABLE (PREFIX_VEX_0F4A
) },
8408 { PREFIX_TABLE (PREFIX_VEX_0F4B
) },
8414 { MOD_TABLE (MOD_VEX_0F50
) },
8415 { PREFIX_TABLE (PREFIX_VEX_0F51
) },
8416 { PREFIX_TABLE (PREFIX_VEX_0F52
) },
8417 { PREFIX_TABLE (PREFIX_VEX_0F53
) },
8418 { "vandpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
8419 { "vandnpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
8420 { "vorpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
8421 { "vxorpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
8423 { PREFIX_TABLE (PREFIX_VEX_0F58
) },
8424 { PREFIX_TABLE (PREFIX_VEX_0F59
) },
8425 { PREFIX_TABLE (PREFIX_VEX_0F5A
) },
8426 { PREFIX_TABLE (PREFIX_VEX_0F5B
) },
8427 { PREFIX_TABLE (PREFIX_VEX_0F5C
) },
8428 { PREFIX_TABLE (PREFIX_VEX_0F5D
) },
8429 { PREFIX_TABLE (PREFIX_VEX_0F5E
) },
8430 { PREFIX_TABLE (PREFIX_VEX_0F5F
) },
8432 { PREFIX_TABLE (PREFIX_VEX_0F60
) },
8433 { PREFIX_TABLE (PREFIX_VEX_0F61
) },
8434 { PREFIX_TABLE (PREFIX_VEX_0F62
) },
8435 { PREFIX_TABLE (PREFIX_VEX_0F63
) },
8436 { PREFIX_TABLE (PREFIX_VEX_0F64
) },
8437 { PREFIX_TABLE (PREFIX_VEX_0F65
) },
8438 { PREFIX_TABLE (PREFIX_VEX_0F66
) },
8439 { PREFIX_TABLE (PREFIX_VEX_0F67
) },
8441 { PREFIX_TABLE (PREFIX_VEX_0F68
) },
8442 { PREFIX_TABLE (PREFIX_VEX_0F69
) },
8443 { PREFIX_TABLE (PREFIX_VEX_0F6A
) },
8444 { PREFIX_TABLE (PREFIX_VEX_0F6B
) },
8445 { PREFIX_TABLE (PREFIX_VEX_0F6C
) },
8446 { PREFIX_TABLE (PREFIX_VEX_0F6D
) },
8447 { PREFIX_TABLE (PREFIX_VEX_0F6E
) },
8448 { PREFIX_TABLE (PREFIX_VEX_0F6F
) },
8450 { PREFIX_TABLE (PREFIX_VEX_0F70
) },
8451 { REG_TABLE (REG_VEX_0F71
) },
8452 { REG_TABLE (REG_VEX_0F72
) },
8453 { REG_TABLE (REG_VEX_0F73
) },
8454 { PREFIX_TABLE (PREFIX_VEX_0F74
) },
8455 { PREFIX_TABLE (PREFIX_VEX_0F75
) },
8456 { PREFIX_TABLE (PREFIX_VEX_0F76
) },
8457 { PREFIX_TABLE (PREFIX_VEX_0F77
) },
8463 { PREFIX_TABLE (PREFIX_VEX_0F7C
) },
8464 { PREFIX_TABLE (PREFIX_VEX_0F7D
) },
8465 { PREFIX_TABLE (PREFIX_VEX_0F7E
) },
8466 { PREFIX_TABLE (PREFIX_VEX_0F7F
) },
8486 { PREFIX_TABLE (PREFIX_VEX_0F90
) },
8487 { PREFIX_TABLE (PREFIX_VEX_0F91
) },
8488 { PREFIX_TABLE (PREFIX_VEX_0F92
) },
8489 { PREFIX_TABLE (PREFIX_VEX_0F93
) },
8495 { PREFIX_TABLE (PREFIX_VEX_0F98
) },
8496 { PREFIX_TABLE (PREFIX_VEX_0F99
) },
8519 { REG_TABLE (REG_VEX_0FAE
) },
8542 { PREFIX_TABLE (PREFIX_VEX_0FC2
) },
8544 { PREFIX_TABLE (PREFIX_VEX_0FC4
) },
8545 { PREFIX_TABLE (PREFIX_VEX_0FC5
) },
8546 { "vshufpX", { XM
, Vex
, EXx
, Ib
}, PREFIX_OPCODE
},
8558 { PREFIX_TABLE (PREFIX_VEX_0FD0
) },
8559 { PREFIX_TABLE (PREFIX_VEX_0FD1
) },
8560 { PREFIX_TABLE (PREFIX_VEX_0FD2
) },
8561 { PREFIX_TABLE (PREFIX_VEX_0FD3
) },
8562 { PREFIX_TABLE (PREFIX_VEX_0FD4
) },
8563 { PREFIX_TABLE (PREFIX_VEX_0FD5
) },
8564 { PREFIX_TABLE (PREFIX_VEX_0FD6
) },
8565 { PREFIX_TABLE (PREFIX_VEX_0FD7
) },
8567 { PREFIX_TABLE (PREFIX_VEX_0FD8
) },
8568 { PREFIX_TABLE (PREFIX_VEX_0FD9
) },
8569 { PREFIX_TABLE (PREFIX_VEX_0FDA
) },
8570 { PREFIX_TABLE (PREFIX_VEX_0FDB
) },
8571 { PREFIX_TABLE (PREFIX_VEX_0FDC
) },
8572 { PREFIX_TABLE (PREFIX_VEX_0FDD
) },
8573 { PREFIX_TABLE (PREFIX_VEX_0FDE
) },
8574 { PREFIX_TABLE (PREFIX_VEX_0FDF
) },
8576 { PREFIX_TABLE (PREFIX_VEX_0FE0
) },
8577 { PREFIX_TABLE (PREFIX_VEX_0FE1
) },
8578 { PREFIX_TABLE (PREFIX_VEX_0FE2
) },
8579 { PREFIX_TABLE (PREFIX_VEX_0FE3
) },
8580 { PREFIX_TABLE (PREFIX_VEX_0FE4
) },
8581 { PREFIX_TABLE (PREFIX_VEX_0FE5
) },
8582 { PREFIX_TABLE (PREFIX_VEX_0FE6
) },
8583 { PREFIX_TABLE (PREFIX_VEX_0FE7
) },
8585 { PREFIX_TABLE (PREFIX_VEX_0FE8
) },
8586 { PREFIX_TABLE (PREFIX_VEX_0FE9
) },
8587 { PREFIX_TABLE (PREFIX_VEX_0FEA
) },
8588 { PREFIX_TABLE (PREFIX_VEX_0FEB
) },
8589 { PREFIX_TABLE (PREFIX_VEX_0FEC
) },
8590 { PREFIX_TABLE (PREFIX_VEX_0FED
) },
8591 { PREFIX_TABLE (PREFIX_VEX_0FEE
) },
8592 { PREFIX_TABLE (PREFIX_VEX_0FEF
) },
8594 { PREFIX_TABLE (PREFIX_VEX_0FF0
) },
8595 { PREFIX_TABLE (PREFIX_VEX_0FF1
) },
8596 { PREFIX_TABLE (PREFIX_VEX_0FF2
) },
8597 { PREFIX_TABLE (PREFIX_VEX_0FF3
) },
8598 { PREFIX_TABLE (PREFIX_VEX_0FF4
) },
8599 { PREFIX_TABLE (PREFIX_VEX_0FF5
) },
8600 { PREFIX_TABLE (PREFIX_VEX_0FF6
) },
8601 { PREFIX_TABLE (PREFIX_VEX_0FF7
) },
8603 { PREFIX_TABLE (PREFIX_VEX_0FF8
) },
8604 { PREFIX_TABLE (PREFIX_VEX_0FF9
) },
8605 { PREFIX_TABLE (PREFIX_VEX_0FFA
) },
8606 { PREFIX_TABLE (PREFIX_VEX_0FFB
) },
8607 { PREFIX_TABLE (PREFIX_VEX_0FFC
) },
8608 { PREFIX_TABLE (PREFIX_VEX_0FFD
) },
8609 { PREFIX_TABLE (PREFIX_VEX_0FFE
) },
8615 { PREFIX_TABLE (PREFIX_VEX_0F3800
) },
8616 { PREFIX_TABLE (PREFIX_VEX_0F3801
) },
8617 { PREFIX_TABLE (PREFIX_VEX_0F3802
) },
8618 { PREFIX_TABLE (PREFIX_VEX_0F3803
) },
8619 { PREFIX_TABLE (PREFIX_VEX_0F3804
) },
8620 { PREFIX_TABLE (PREFIX_VEX_0F3805
) },
8621 { PREFIX_TABLE (PREFIX_VEX_0F3806
) },
8622 { PREFIX_TABLE (PREFIX_VEX_0F3807
) },
8624 { PREFIX_TABLE (PREFIX_VEX_0F3808
) },
8625 { PREFIX_TABLE (PREFIX_VEX_0F3809
) },
8626 { PREFIX_TABLE (PREFIX_VEX_0F380A
) },
8627 { PREFIX_TABLE (PREFIX_VEX_0F380B
) },
8628 { PREFIX_TABLE (PREFIX_VEX_0F380C
) },
8629 { PREFIX_TABLE (PREFIX_VEX_0F380D
) },
8630 { PREFIX_TABLE (PREFIX_VEX_0F380E
) },
8631 { PREFIX_TABLE (PREFIX_VEX_0F380F
) },
8636 { PREFIX_TABLE (PREFIX_VEX_0F3813
) },
8639 { PREFIX_TABLE (PREFIX_VEX_0F3816
) },
8640 { PREFIX_TABLE (PREFIX_VEX_0F3817
) },
8642 { PREFIX_TABLE (PREFIX_VEX_0F3818
) },
8643 { PREFIX_TABLE (PREFIX_VEX_0F3819
) },
8644 { PREFIX_TABLE (PREFIX_VEX_0F381A
) },
8646 { PREFIX_TABLE (PREFIX_VEX_0F381C
) },
8647 { PREFIX_TABLE (PREFIX_VEX_0F381D
) },
8648 { PREFIX_TABLE (PREFIX_VEX_0F381E
) },
8651 { PREFIX_TABLE (PREFIX_VEX_0F3820
) },
8652 { PREFIX_TABLE (PREFIX_VEX_0F3821
) },
8653 { PREFIX_TABLE (PREFIX_VEX_0F3822
) },
8654 { PREFIX_TABLE (PREFIX_VEX_0F3823
) },
8655 { PREFIX_TABLE (PREFIX_VEX_0F3824
) },
8656 { PREFIX_TABLE (PREFIX_VEX_0F3825
) },
8660 { PREFIX_TABLE (PREFIX_VEX_0F3828
) },
8661 { PREFIX_TABLE (PREFIX_VEX_0F3829
) },
8662 { PREFIX_TABLE (PREFIX_VEX_0F382A
) },
8663 { PREFIX_TABLE (PREFIX_VEX_0F382B
) },
8664 { PREFIX_TABLE (PREFIX_VEX_0F382C
) },
8665 { PREFIX_TABLE (PREFIX_VEX_0F382D
) },
8666 { PREFIX_TABLE (PREFIX_VEX_0F382E
) },
8667 { PREFIX_TABLE (PREFIX_VEX_0F382F
) },
8669 { PREFIX_TABLE (PREFIX_VEX_0F3830
) },
8670 { PREFIX_TABLE (PREFIX_VEX_0F3831
) },
8671 { PREFIX_TABLE (PREFIX_VEX_0F3832
) },
8672 { PREFIX_TABLE (PREFIX_VEX_0F3833
) },
8673 { PREFIX_TABLE (PREFIX_VEX_0F3834
) },
8674 { PREFIX_TABLE (PREFIX_VEX_0F3835
) },
8675 { PREFIX_TABLE (PREFIX_VEX_0F3836
) },
8676 { PREFIX_TABLE (PREFIX_VEX_0F3837
) },
8678 { PREFIX_TABLE (PREFIX_VEX_0F3838
) },
8679 { PREFIX_TABLE (PREFIX_VEX_0F3839
) },
8680 { PREFIX_TABLE (PREFIX_VEX_0F383A
) },
8681 { PREFIX_TABLE (PREFIX_VEX_0F383B
) },
8682 { PREFIX_TABLE (PREFIX_VEX_0F383C
) },
8683 { PREFIX_TABLE (PREFIX_VEX_0F383D
) },
8684 { PREFIX_TABLE (PREFIX_VEX_0F383E
) },
8685 { PREFIX_TABLE (PREFIX_VEX_0F383F
) },
8687 { PREFIX_TABLE (PREFIX_VEX_0F3840
) },
8688 { PREFIX_TABLE (PREFIX_VEX_0F3841
) },
8692 { PREFIX_TABLE (PREFIX_VEX_0F3845
) },
8693 { PREFIX_TABLE (PREFIX_VEX_0F3846
) },
8694 { PREFIX_TABLE (PREFIX_VEX_0F3847
) },
8714 { PREFIX_TABLE (PREFIX_VEX_0F3858
) },
8715 { PREFIX_TABLE (PREFIX_VEX_0F3859
) },
8716 { PREFIX_TABLE (PREFIX_VEX_0F385A
) },
8750 { PREFIX_TABLE (PREFIX_VEX_0F3878
) },
8751 { PREFIX_TABLE (PREFIX_VEX_0F3879
) },
8772 { PREFIX_TABLE (PREFIX_VEX_0F388C
) },
8774 { PREFIX_TABLE (PREFIX_VEX_0F388E
) },
8777 { PREFIX_TABLE (PREFIX_VEX_0F3890
) },
8778 { PREFIX_TABLE (PREFIX_VEX_0F3891
) },
8779 { PREFIX_TABLE (PREFIX_VEX_0F3892
) },
8780 { PREFIX_TABLE (PREFIX_VEX_0F3893
) },
8783 { PREFIX_TABLE (PREFIX_VEX_0F3896
) },
8784 { PREFIX_TABLE (PREFIX_VEX_0F3897
) },
8786 { PREFIX_TABLE (PREFIX_VEX_0F3898
) },
8787 { PREFIX_TABLE (PREFIX_VEX_0F3899
) },
8788 { PREFIX_TABLE (PREFIX_VEX_0F389A
) },
8789 { PREFIX_TABLE (PREFIX_VEX_0F389B
) },
8790 { PREFIX_TABLE (PREFIX_VEX_0F389C
) },
8791 { PREFIX_TABLE (PREFIX_VEX_0F389D
) },
8792 { PREFIX_TABLE (PREFIX_VEX_0F389E
) },
8793 { PREFIX_TABLE (PREFIX_VEX_0F389F
) },
8801 { PREFIX_TABLE (PREFIX_VEX_0F38A6
) },
8802 { PREFIX_TABLE (PREFIX_VEX_0F38A7
) },
8804 { PREFIX_TABLE (PREFIX_VEX_0F38A8
) },
8805 { PREFIX_TABLE (PREFIX_VEX_0F38A9
) },
8806 { PREFIX_TABLE (PREFIX_VEX_0F38AA
) },
8807 { PREFIX_TABLE (PREFIX_VEX_0F38AB
) },
8808 { PREFIX_TABLE (PREFIX_VEX_0F38AC
) },
8809 { PREFIX_TABLE (PREFIX_VEX_0F38AD
) },
8810 { PREFIX_TABLE (PREFIX_VEX_0F38AE
) },
8811 { PREFIX_TABLE (PREFIX_VEX_0F38AF
) },
8819 { PREFIX_TABLE (PREFIX_VEX_0F38B6
) },
8820 { PREFIX_TABLE (PREFIX_VEX_0F38B7
) },
8822 { PREFIX_TABLE (PREFIX_VEX_0F38B8
) },
8823 { PREFIX_TABLE (PREFIX_VEX_0F38B9
) },
8824 { PREFIX_TABLE (PREFIX_VEX_0F38BA
) },
8825 { PREFIX_TABLE (PREFIX_VEX_0F38BB
) },
8826 { PREFIX_TABLE (PREFIX_VEX_0F38BC
) },
8827 { PREFIX_TABLE (PREFIX_VEX_0F38BD
) },
8828 { PREFIX_TABLE (PREFIX_VEX_0F38BE
) },
8829 { PREFIX_TABLE (PREFIX_VEX_0F38BF
) },
8847 { PREFIX_TABLE (PREFIX_VEX_0F38CF
) },
8861 { PREFIX_TABLE (PREFIX_VEX_0F38DB
) },
8862 { PREFIX_TABLE (PREFIX_VEX_0F38DC
) },
8863 { PREFIX_TABLE (PREFIX_VEX_0F38DD
) },
8864 { PREFIX_TABLE (PREFIX_VEX_0F38DE
) },
8865 { PREFIX_TABLE (PREFIX_VEX_0F38DF
) },
8887 { PREFIX_TABLE (PREFIX_VEX_0F38F2
) },
8888 { REG_TABLE (REG_VEX_0F38F3
) },
8890 { PREFIX_TABLE (PREFIX_VEX_0F38F5
) },
8891 { PREFIX_TABLE (PREFIX_VEX_0F38F6
) },
8892 { PREFIX_TABLE (PREFIX_VEX_0F38F7
) },
8906 { PREFIX_TABLE (PREFIX_VEX_0F3A00
) },
8907 { PREFIX_TABLE (PREFIX_VEX_0F3A01
) },
8908 { PREFIX_TABLE (PREFIX_VEX_0F3A02
) },
8910 { PREFIX_TABLE (PREFIX_VEX_0F3A04
) },
8911 { PREFIX_TABLE (PREFIX_VEX_0F3A05
) },
8912 { PREFIX_TABLE (PREFIX_VEX_0F3A06
) },
8915 { PREFIX_TABLE (PREFIX_VEX_0F3A08
) },
8916 { PREFIX_TABLE (PREFIX_VEX_0F3A09
) },
8917 { PREFIX_TABLE (PREFIX_VEX_0F3A0A
) },
8918 { PREFIX_TABLE (PREFIX_VEX_0F3A0B
) },
8919 { PREFIX_TABLE (PREFIX_VEX_0F3A0C
) },
8920 { PREFIX_TABLE (PREFIX_VEX_0F3A0D
) },
8921 { PREFIX_TABLE (PREFIX_VEX_0F3A0E
) },
8922 { PREFIX_TABLE (PREFIX_VEX_0F3A0F
) },
8928 { PREFIX_TABLE (PREFIX_VEX_0F3A14
) },
8929 { PREFIX_TABLE (PREFIX_VEX_0F3A15
) },
8930 { PREFIX_TABLE (PREFIX_VEX_0F3A16
) },
8931 { PREFIX_TABLE (PREFIX_VEX_0F3A17
) },
8933 { PREFIX_TABLE (PREFIX_VEX_0F3A18
) },
8934 { PREFIX_TABLE (PREFIX_VEX_0F3A19
) },
8938 { PREFIX_TABLE (PREFIX_VEX_0F3A1D
) },
8942 { PREFIX_TABLE (PREFIX_VEX_0F3A20
) },
8943 { PREFIX_TABLE (PREFIX_VEX_0F3A21
) },
8944 { PREFIX_TABLE (PREFIX_VEX_0F3A22
) },
8960 { PREFIX_TABLE (PREFIX_VEX_0F3A30
) },
8961 { PREFIX_TABLE (PREFIX_VEX_0F3A31
) },
8962 { PREFIX_TABLE (PREFIX_VEX_0F3A32
) },
8963 { PREFIX_TABLE (PREFIX_VEX_0F3A33
) },
8969 { PREFIX_TABLE (PREFIX_VEX_0F3A38
) },
8970 { PREFIX_TABLE (PREFIX_VEX_0F3A39
) },
8978 { PREFIX_TABLE (PREFIX_VEX_0F3A40
) },
8979 { PREFIX_TABLE (PREFIX_VEX_0F3A41
) },
8980 { PREFIX_TABLE (PREFIX_VEX_0F3A42
) },
8982 { PREFIX_TABLE (PREFIX_VEX_0F3A44
) },
8984 { PREFIX_TABLE (PREFIX_VEX_0F3A46
) },
8987 { PREFIX_TABLE (PREFIX_VEX_0F3A48
) },
8988 { PREFIX_TABLE (PREFIX_VEX_0F3A49
) },
8989 { PREFIX_TABLE (PREFIX_VEX_0F3A4A
) },
8990 { PREFIX_TABLE (PREFIX_VEX_0F3A4B
) },
8991 { PREFIX_TABLE (PREFIX_VEX_0F3A4C
) },
9009 { PREFIX_TABLE (PREFIX_VEX_0F3A5C
) },
9010 { PREFIX_TABLE (PREFIX_VEX_0F3A5D
) },
9011 { PREFIX_TABLE (PREFIX_VEX_0F3A5E
) },
9012 { PREFIX_TABLE (PREFIX_VEX_0F3A5F
) },
9014 { PREFIX_TABLE (PREFIX_VEX_0F3A60
) },
9015 { PREFIX_TABLE (PREFIX_VEX_0F3A61
) },
9016 { PREFIX_TABLE (PREFIX_VEX_0F3A62
) },
9017 { PREFIX_TABLE (PREFIX_VEX_0F3A63
) },
9023 { PREFIX_TABLE (PREFIX_VEX_0F3A68
) },
9024 { PREFIX_TABLE (PREFIX_VEX_0F3A69
) },
9025 { PREFIX_TABLE (PREFIX_VEX_0F3A6A
) },
9026 { PREFIX_TABLE (PREFIX_VEX_0F3A6B
) },
9027 { PREFIX_TABLE (PREFIX_VEX_0F3A6C
) },
9028 { PREFIX_TABLE (PREFIX_VEX_0F3A6D
) },
9029 { PREFIX_TABLE (PREFIX_VEX_0F3A6E
) },
9030 { PREFIX_TABLE (PREFIX_VEX_0F3A6F
) },
9041 { PREFIX_TABLE (PREFIX_VEX_0F3A78
) },
9042 { PREFIX_TABLE (PREFIX_VEX_0F3A79
) },
9043 { PREFIX_TABLE (PREFIX_VEX_0F3A7A
) },
9044 { PREFIX_TABLE (PREFIX_VEX_0F3A7B
) },
9045 { PREFIX_TABLE (PREFIX_VEX_0F3A7C
) },
9046 { PREFIX_TABLE (PREFIX_VEX_0F3A7D
) },
9047 { PREFIX_TABLE (PREFIX_VEX_0F3A7E
) },
9048 { PREFIX_TABLE (PREFIX_VEX_0F3A7F
) },
9137 { PREFIX_TABLE(PREFIX_VEX_0F3ACE
) },
9138 { PREFIX_TABLE(PREFIX_VEX_0F3ACF
) },
9156 { PREFIX_TABLE (PREFIX_VEX_0F3ADF
) },
9176 { PREFIX_TABLE (PREFIX_VEX_0F3AF0
) },
9196 #include "i386-dis-evex.h"
9198 static const struct dis386 vex_len_table
[][2] = {
9199 /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */
9201 { "vmovlpX", { XM
, Vex128
, EXq
}, 0 },
9204 /* VEX_LEN_0F12_P_0_M_1 */
9206 { "vmovhlps", { XM
, Vex128
, EXq
}, 0 },
9209 /* VEX_LEN_0F13_M_0 */
9211 { "vmovlpX", { EXq
, XM
}, PREFIX_OPCODE
},
9214 /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */
9216 { "vmovhpX", { XM
, Vex128
, EXq
}, 0 },
9219 /* VEX_LEN_0F16_P_0_M_1 */
9221 { "vmovlhps", { XM
, Vex128
, EXq
}, 0 },
9224 /* VEX_LEN_0F17_M_0 */
9226 { "vmovhpX", { EXq
, XM
}, PREFIX_OPCODE
},
9229 /* VEX_LEN_0F41_P_0 */
9232 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1
) },
9234 /* VEX_LEN_0F41_P_2 */
9237 { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1
) },
9239 /* VEX_LEN_0F42_P_0 */
9242 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1
) },
9244 /* VEX_LEN_0F42_P_2 */
9247 { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1
) },
9249 /* VEX_LEN_0F44_P_0 */
9251 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0
) },
9253 /* VEX_LEN_0F44_P_2 */
9255 { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0
) },
9257 /* VEX_LEN_0F45_P_0 */
9260 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1
) },
9262 /* VEX_LEN_0F45_P_2 */
9265 { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1
) },
9267 /* VEX_LEN_0F46_P_0 */
9270 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1
) },
9272 /* VEX_LEN_0F46_P_2 */
9275 { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1
) },
9277 /* VEX_LEN_0F47_P_0 */
9280 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1
) },
9282 /* VEX_LEN_0F47_P_2 */
9285 { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1
) },
9287 /* VEX_LEN_0F4A_P_0 */
9290 { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1
) },
9292 /* VEX_LEN_0F4A_P_2 */
9295 { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1
) },
9297 /* VEX_LEN_0F4B_P_0 */
9300 { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1
) },
9302 /* VEX_LEN_0F4B_P_2 */
9305 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1
) },
9308 /* VEX_LEN_0F6E_P_2 */
9310 { "vmovK", { XMScalar
, Edq
}, 0 },
9313 /* VEX_LEN_0F77_P_1 */
9315 { "vzeroupper", { XX
}, 0 },
9316 { "vzeroall", { XX
}, 0 },
9319 /* VEX_LEN_0F7E_P_1 */
9321 { "vmovq", { XMScalar
, EXxmm_mq
}, 0 },
9324 /* VEX_LEN_0F7E_P_2 */
9326 { "vmovK", { Edq
, XMScalar
}, 0 },
9329 /* VEX_LEN_0F90_P_0 */
9331 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0
) },
9334 /* VEX_LEN_0F90_P_2 */
9336 { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0
) },
9339 /* VEX_LEN_0F91_P_0 */
9341 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0
) },
9344 /* VEX_LEN_0F91_P_2 */
9346 { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0
) },
9349 /* VEX_LEN_0F92_P_0 */
9351 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0
) },
9354 /* VEX_LEN_0F92_P_2 */
9356 { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0
) },
9359 /* VEX_LEN_0F92_P_3 */
9361 { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0
) },
9364 /* VEX_LEN_0F93_P_0 */
9366 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0
) },
9369 /* VEX_LEN_0F93_P_2 */
9371 { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0
) },
9374 /* VEX_LEN_0F93_P_3 */
9376 { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0
) },
9379 /* VEX_LEN_0F98_P_0 */
9381 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0
) },
9384 /* VEX_LEN_0F98_P_2 */
9386 { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0
) },
9389 /* VEX_LEN_0F99_P_0 */
9391 { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0
) },
9394 /* VEX_LEN_0F99_P_2 */
9396 { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0
) },
9399 /* VEX_LEN_0FAE_R_2_M_0 */
9401 { "vldmxcsr", { Md
}, 0 },
9404 /* VEX_LEN_0FAE_R_3_M_0 */
9406 { "vstmxcsr", { Md
}, 0 },
9409 /* VEX_LEN_0FC4_P_2 */
9411 { "vpinsrw", { XM
, Vex128
, Edqw
, Ib
}, 0 },
9414 /* VEX_LEN_0FC5_P_2 */
9416 { "vpextrw", { Gdq
, XS
, Ib
}, 0 },
9419 /* VEX_LEN_0FD6_P_2 */
9421 { "vmovq", { EXqVexScalarS
, XMScalar
}, 0 },
9424 /* VEX_LEN_0FF7_P_2 */
9426 { "vmaskmovdqu", { XM
, XS
}, 0 },
9429 /* VEX_LEN_0F3816_P_2 */
9432 { VEX_W_TABLE (VEX_W_0F3816_P_2
) },
9435 /* VEX_LEN_0F3819_P_2 */
9438 { VEX_W_TABLE (VEX_W_0F3819_P_2
) },
9441 /* VEX_LEN_0F381A_P_2_M_0 */
9444 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0
) },
9447 /* VEX_LEN_0F3836_P_2 */
9450 { VEX_W_TABLE (VEX_W_0F3836_P_2
) },
9453 /* VEX_LEN_0F3841_P_2 */
9455 { "vphminposuw", { XM
, EXx
}, 0 },
9458 /* VEX_LEN_0F385A_P_2_M_0 */
9461 { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0
) },
9464 /* VEX_LEN_0F38DB_P_2 */
9466 { "vaesimc", { XM
, EXx
}, 0 },
9469 /* VEX_LEN_0F38F2_P_0 */
9471 { "andnS", { Gdq
, VexGdq
, Edq
}, 0 },
9474 /* VEX_LEN_0F38F3_R_1_P_0 */
9476 { "blsrS", { VexGdq
, Edq
}, 0 },
9479 /* VEX_LEN_0F38F3_R_2_P_0 */
9481 { "blsmskS", { VexGdq
, Edq
}, 0 },
9484 /* VEX_LEN_0F38F3_R_3_P_0 */
9486 { "blsiS", { VexGdq
, Edq
}, 0 },
9489 /* VEX_LEN_0F38F5_P_0 */
9491 { "bzhiS", { Gdq
, Edq
, VexGdq
}, 0 },
9494 /* VEX_LEN_0F38F5_P_1 */
9496 { "pextS", { Gdq
, VexGdq
, Edq
}, 0 },
9499 /* VEX_LEN_0F38F5_P_3 */
9501 { "pdepS", { Gdq
, VexGdq
, Edq
}, 0 },
9504 /* VEX_LEN_0F38F6_P_3 */
9506 { "mulxS", { Gdq
, VexGdq
, Edq
}, 0 },
9509 /* VEX_LEN_0F38F7_P_0 */
9511 { "bextrS", { Gdq
, Edq
, VexGdq
}, 0 },
9514 /* VEX_LEN_0F38F7_P_1 */
9516 { "sarxS", { Gdq
, Edq
, VexGdq
}, 0 },
9519 /* VEX_LEN_0F38F7_P_2 */
9521 { "shlxS", { Gdq
, Edq
, VexGdq
}, 0 },
9524 /* VEX_LEN_0F38F7_P_3 */
9526 { "shrxS", { Gdq
, Edq
, VexGdq
}, 0 },
9529 /* VEX_LEN_0F3A00_P_2 */
9532 { VEX_W_TABLE (VEX_W_0F3A00_P_2
) },
9535 /* VEX_LEN_0F3A01_P_2 */
9538 { VEX_W_TABLE (VEX_W_0F3A01_P_2
) },
9541 /* VEX_LEN_0F3A06_P_2 */
9544 { VEX_W_TABLE (VEX_W_0F3A06_P_2
) },
9547 /* VEX_LEN_0F3A14_P_2 */
9549 { "vpextrb", { Edqb
, XM
, Ib
}, 0 },
9552 /* VEX_LEN_0F3A15_P_2 */
9554 { "vpextrw", { Edqw
, XM
, Ib
}, 0 },
9557 /* VEX_LEN_0F3A16_P_2 */
9559 { "vpextrK", { Edq
, XM
, Ib
}, 0 },
9562 /* VEX_LEN_0F3A17_P_2 */
9564 { "vextractps", { Edqd
, XM
, Ib
}, 0 },
9567 /* VEX_LEN_0F3A18_P_2 */
9570 { VEX_W_TABLE (VEX_W_0F3A18_P_2
) },
9573 /* VEX_LEN_0F3A19_P_2 */
9576 { VEX_W_TABLE (VEX_W_0F3A19_P_2
) },
9579 /* VEX_LEN_0F3A20_P_2 */
9581 { "vpinsrb", { XM
, Vex128
, Edqb
, Ib
}, 0 },
9584 /* VEX_LEN_0F3A21_P_2 */
9586 { "vinsertps", { XM
, Vex128
, EXd
, Ib
}, 0 },
9589 /* VEX_LEN_0F3A22_P_2 */
9591 { "vpinsrK", { XM
, Vex128
, Edq
, Ib
}, 0 },
9594 /* VEX_LEN_0F3A30_P_2 */
9596 { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0
) },
9599 /* VEX_LEN_0F3A31_P_2 */
9601 { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0
) },
9604 /* VEX_LEN_0F3A32_P_2 */
9606 { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0
) },
9609 /* VEX_LEN_0F3A33_P_2 */
9611 { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0
) },
9614 /* VEX_LEN_0F3A38_P_2 */
9617 { VEX_W_TABLE (VEX_W_0F3A38_P_2
) },
9620 /* VEX_LEN_0F3A39_P_2 */
9623 { VEX_W_TABLE (VEX_W_0F3A39_P_2
) },
9626 /* VEX_LEN_0F3A41_P_2 */
9628 { "vdppd", { XM
, Vex128
, EXx
, Ib
}, 0 },
9631 /* VEX_LEN_0F3A46_P_2 */
9634 { VEX_W_TABLE (VEX_W_0F3A46_P_2
) },
9637 /* VEX_LEN_0F3A60_P_2 */
9639 { "vpcmpestrm", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, 0 },
9642 /* VEX_LEN_0F3A61_P_2 */
9644 { "vpcmpestri", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, 0 },
9647 /* VEX_LEN_0F3A62_P_2 */
9649 { "vpcmpistrm", { XM
, EXx
, Ib
}, 0 },
9652 /* VEX_LEN_0F3A63_P_2 */
9654 { "vpcmpistri", { XM
, EXx
, Ib
}, 0 },
9657 /* VEX_LEN_0F3A6A_P_2 */
9659 { "vfmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9662 /* VEX_LEN_0F3A6B_P_2 */
9664 { "vfmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9667 /* VEX_LEN_0F3A6E_P_2 */
9669 { "vfmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9672 /* VEX_LEN_0F3A6F_P_2 */
9674 { "vfmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9677 /* VEX_LEN_0F3A7A_P_2 */
9679 { "vfnmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9682 /* VEX_LEN_0F3A7B_P_2 */
9684 { "vfnmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9687 /* VEX_LEN_0F3A7E_P_2 */
9689 { "vfnmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9692 /* VEX_LEN_0F3A7F_P_2 */
9694 { "vfnmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9697 /* VEX_LEN_0F3ADF_P_2 */
9699 { "vaeskeygenassist", { XM
, EXx
, Ib
}, 0 },
9702 /* VEX_LEN_0F3AF0_P_3 */
9704 { "rorxS", { Gdq
, Edq
, Ib
}, 0 },
9707 /* VEX_LEN_0FXOP_08_CC */
9709 { "vpcomb", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9712 /* VEX_LEN_0FXOP_08_CD */
9714 { "vpcomw", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9717 /* VEX_LEN_0FXOP_08_CE */
9719 { "vpcomd", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9722 /* VEX_LEN_0FXOP_08_CF */
9724 { "vpcomq", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9727 /* VEX_LEN_0FXOP_08_EC */
9729 { "vpcomub", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9732 /* VEX_LEN_0FXOP_08_ED */
9734 { "vpcomuw", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9737 /* VEX_LEN_0FXOP_08_EE */
9739 { "vpcomud", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9742 /* VEX_LEN_0FXOP_08_EF */
9744 { "vpcomuq", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9747 /* VEX_LEN_0FXOP_09_80 */
9749 { "vfrczps", { XM
, EXxmm
}, 0 },
9750 { "vfrczps", { XM
, EXymmq
}, 0 },
9753 /* VEX_LEN_0FXOP_09_81 */
9755 { "vfrczpd", { XM
, EXxmm
}, 0 },
9756 { "vfrczpd", { XM
, EXymmq
}, 0 },
9760 #include "i386-dis-evex-len.h"
9762 static const struct dis386 vex_w_table
[][2] = {
9764 /* VEX_W_0F41_P_0_LEN_1 */
9765 { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1
) },
9766 { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1
) },
9769 /* VEX_W_0F41_P_2_LEN_1 */
9770 { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1
) },
9771 { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1
) }
9774 /* VEX_W_0F42_P_0_LEN_1 */
9775 { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1
) },
9776 { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1
) },
9779 /* VEX_W_0F42_P_2_LEN_1 */
9780 { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1
) },
9781 { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1
) },
9784 /* VEX_W_0F44_P_0_LEN_0 */
9785 { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1
) },
9786 { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1
) },
9789 /* VEX_W_0F44_P_2_LEN_0 */
9790 { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1
) },
9791 { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1
) },
9794 /* VEX_W_0F45_P_0_LEN_1 */
9795 { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1
) },
9796 { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1
) },
9799 /* VEX_W_0F45_P_2_LEN_1 */
9800 { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1
) },
9801 { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1
) },
9804 /* VEX_W_0F46_P_0_LEN_1 */
9805 { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1
) },
9806 { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1
) },
9809 /* VEX_W_0F46_P_2_LEN_1 */
9810 { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1
) },
9811 { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1
) },
9814 /* VEX_W_0F47_P_0_LEN_1 */
9815 { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1
) },
9816 { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1
) },
9819 /* VEX_W_0F47_P_2_LEN_1 */
9820 { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1
) },
9821 { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1
) },
9824 /* VEX_W_0F4A_P_0_LEN_1 */
9825 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1
) },
9826 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1
) },
9829 /* VEX_W_0F4A_P_2_LEN_1 */
9830 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1
) },
9831 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1
) },
9834 /* VEX_W_0F4B_P_0_LEN_1 */
9835 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1
) },
9836 { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1
) },
9839 /* VEX_W_0F4B_P_2_LEN_1 */
9840 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1
) },
9843 /* VEX_W_0F90_P_0_LEN_0 */
9844 { "kmovw", { MaskG
, MaskE
}, 0 },
9845 { "kmovq", { MaskG
, MaskE
}, 0 },
9848 /* VEX_W_0F90_P_2_LEN_0 */
9849 { "kmovb", { MaskG
, MaskBDE
}, 0 },
9850 { "kmovd", { MaskG
, MaskBDE
}, 0 },
9853 /* VEX_W_0F91_P_0_LEN_0 */
9854 { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0
) },
9855 { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0
) },
9858 /* VEX_W_0F91_P_2_LEN_0 */
9859 { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0
) },
9860 { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0
) },
9863 /* VEX_W_0F92_P_0_LEN_0 */
9864 { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0
) },
9867 /* VEX_W_0F92_P_2_LEN_0 */
9868 { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0
) },
9871 /* VEX_W_0F93_P_0_LEN_0 */
9872 { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0
) },
9875 /* VEX_W_0F93_P_2_LEN_0 */
9876 { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0
) },
9879 /* VEX_W_0F98_P_0_LEN_0 */
9880 { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0
) },
9881 { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0
) },
9884 /* VEX_W_0F98_P_2_LEN_0 */
9885 { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0
) },
9886 { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0
) },
9889 /* VEX_W_0F99_P_0_LEN_0 */
9890 { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0
) },
9891 { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0
) },
9894 /* VEX_W_0F99_P_2_LEN_0 */
9895 { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0
) },
9896 { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0
) },
9899 /* VEX_W_0F380C_P_2 */
9900 { "vpermilps", { XM
, Vex
, EXx
}, 0 },
9903 /* VEX_W_0F380D_P_2 */
9904 { "vpermilpd", { XM
, Vex
, EXx
}, 0 },
9907 /* VEX_W_0F380E_P_2 */
9908 { "vtestps", { XM
, EXx
}, 0 },
9911 /* VEX_W_0F380F_P_2 */
9912 { "vtestpd", { XM
, EXx
}, 0 },
9915 /* VEX_W_0F3813_P_2 */
9916 { "vcvtph2ps", { XM
, EXxmmq
}, 0 },
9919 /* VEX_W_0F3816_P_2 */
9920 { "vpermps", { XM
, Vex
, EXx
}, 0 },
9923 /* VEX_W_0F3818_P_2 */
9924 { "vbroadcastss", { XM
, EXxmm_md
}, 0 },
9927 /* VEX_W_0F3819_P_2 */
9928 { "vbroadcastsd", { XM
, EXxmm_mq
}, 0 },
9931 /* VEX_W_0F381A_P_2_M_0 */
9932 { "vbroadcastf128", { XM
, Mxmm
}, 0 },
9935 /* VEX_W_0F382C_P_2_M_0 */
9936 { "vmaskmovps", { XM
, Vex
, Mx
}, 0 },
9939 /* VEX_W_0F382D_P_2_M_0 */
9940 { "vmaskmovpd", { XM
, Vex
, Mx
}, 0 },
9943 /* VEX_W_0F382E_P_2_M_0 */
9944 { "vmaskmovps", { Mx
, Vex
, XM
}, 0 },
9947 /* VEX_W_0F382F_P_2_M_0 */
9948 { "vmaskmovpd", { Mx
, Vex
, XM
}, 0 },
9951 /* VEX_W_0F3836_P_2 */
9952 { "vpermd", { XM
, Vex
, EXx
}, 0 },
9955 /* VEX_W_0F3846_P_2 */
9956 { "vpsravd", { XM
, Vex
, EXx
}, 0 },
9959 /* VEX_W_0F3858_P_2 */
9960 { "vpbroadcastd", { XM
, EXxmm_md
}, 0 },
9963 /* VEX_W_0F3859_P_2 */
9964 { "vpbroadcastq", { XM
, EXxmm_mq
}, 0 },
9967 /* VEX_W_0F385A_P_2_M_0 */
9968 { "vbroadcasti128", { XM
, Mxmm
}, 0 },
9971 /* VEX_W_0F3878_P_2 */
9972 { "vpbroadcastb", { XM
, EXxmm_mb
}, 0 },
9975 /* VEX_W_0F3879_P_2 */
9976 { "vpbroadcastw", { XM
, EXxmm_mw
}, 0 },
9979 /* VEX_W_0F38CF_P_2 */
9980 { "vgf2p8mulb", { XM
, Vex
, EXx
}, 0 },
9983 /* VEX_W_0F3A00_P_2 */
9985 { "vpermq", { XM
, EXx
, Ib
}, 0 },
9988 /* VEX_W_0F3A01_P_2 */
9990 { "vpermpd", { XM
, EXx
, Ib
}, 0 },
9993 /* VEX_W_0F3A02_P_2 */
9994 { "vpblendd", { XM
, Vex
, EXx
, Ib
}, 0 },
9997 /* VEX_W_0F3A04_P_2 */
9998 { "vpermilps", { XM
, EXx
, Ib
}, 0 },
10001 /* VEX_W_0F3A05_P_2 */
10002 { "vpermilpd", { XM
, EXx
, Ib
}, 0 },
10005 /* VEX_W_0F3A06_P_2 */
10006 { "vperm2f128", { XM
, Vex256
, EXx
, Ib
}, 0 },
10009 /* VEX_W_0F3A18_P_2 */
10010 { "vinsertf128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
10013 /* VEX_W_0F3A19_P_2 */
10014 { "vextractf128", { EXxmm
, XM
, Ib
}, 0 },
10017 /* VEX_W_0F3A1D_P_2 */
10018 { "vcvtps2ph", { EXxmmq
, XM
, EXxEVexS
, Ib
}, 0 },
10021 /* VEX_W_0F3A30_P_2_LEN_0 */
10022 { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0
) },
10023 { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0
) },
10026 /* VEX_W_0F3A31_P_2_LEN_0 */
10027 { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0
) },
10028 { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0
) },
10031 /* VEX_W_0F3A32_P_2_LEN_0 */
10032 { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0
) },
10033 { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0
) },
10036 /* VEX_W_0F3A33_P_2_LEN_0 */
10037 { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0
) },
10038 { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0
) },
10041 /* VEX_W_0F3A38_P_2 */
10042 { "vinserti128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
10045 /* VEX_W_0F3A39_P_2 */
10046 { "vextracti128", { EXxmm
, XM
, Ib
}, 0 },
10049 /* VEX_W_0F3A46_P_2 */
10050 { "vperm2i128", { XM
, Vex256
, EXx
, Ib
}, 0 },
10053 /* VEX_W_0F3A48_P_2 */
10054 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10055 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10058 /* VEX_W_0F3A49_P_2 */
10059 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10060 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10063 /* VEX_W_0F3A4A_P_2 */
10064 { "vblendvps", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10067 /* VEX_W_0F3A4B_P_2 */
10068 { "vblendvpd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10071 /* VEX_W_0F3A4C_P_2 */
10072 { "vpblendvb", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10075 /* VEX_W_0F3ACE_P_2 */
10077 { "vgf2p8affineqb", { XM
, Vex
, EXx
, Ib
}, 0 },
10080 /* VEX_W_0F3ACF_P_2 */
10082 { "vgf2p8affineinvqb", { XM
, Vex
, EXx
, Ib
}, 0 },
10085 #include "i386-dis-evex-w.h"
10088 static const struct dis386 mod_table
[][2] = {
10091 { "leaS", { Gv
, M
}, 0 },
10096 { RM_TABLE (RM_C6_REG_7
) },
10101 { RM_TABLE (RM_C7_REG_7
) },
10105 { "{l|}call^", { indirEp
}, 0 },
10109 { "{l|}jmp^", { indirEp
}, 0 },
10112 /* MOD_0F01_REG_0 */
10113 { X86_64_TABLE (X86_64_0F01_REG_0
) },
10114 { RM_TABLE (RM_0F01_REG_0
) },
10117 /* MOD_0F01_REG_1 */
10118 { X86_64_TABLE (X86_64_0F01_REG_1
) },
10119 { RM_TABLE (RM_0F01_REG_1
) },
10122 /* MOD_0F01_REG_2 */
10123 { X86_64_TABLE (X86_64_0F01_REG_2
) },
10124 { RM_TABLE (RM_0F01_REG_2
) },
10127 /* MOD_0F01_REG_3 */
10128 { X86_64_TABLE (X86_64_0F01_REG_3
) },
10129 { RM_TABLE (RM_0F01_REG_3
) },
10132 /* MOD_0F01_REG_5 */
10133 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0
) },
10134 { RM_TABLE (RM_0F01_REG_5_MOD_3
) },
10137 /* MOD_0F01_REG_7 */
10138 { "invlpg", { Mb
}, 0 },
10139 { RM_TABLE (RM_0F01_REG_7_MOD_3
) },
10142 /* MOD_0F12_PREFIX_0 */
10143 { "movlpX", { XM
, EXq
}, 0 },
10144 { "movhlps", { XM
, EXq
}, 0 },
10147 /* MOD_0F12_PREFIX_2 */
10148 { "movlpX", { XM
, EXq
}, 0 },
10152 { "movlpX", { EXq
, XM
}, PREFIX_OPCODE
},
10155 /* MOD_0F16_PREFIX_0 */
10156 { "movhpX", { XM
, EXq
}, 0 },
10157 { "movlhps", { XM
, EXq
}, 0 },
10160 /* MOD_0F16_PREFIX_2 */
10161 { "movhpX", { XM
, EXq
}, 0 },
10165 { "movhpX", { EXq
, XM
}, PREFIX_OPCODE
},
10168 /* MOD_0F18_REG_0 */
10169 { "prefetchnta", { Mb
}, 0 },
10172 /* MOD_0F18_REG_1 */
10173 { "prefetcht0", { Mb
}, 0 },
10176 /* MOD_0F18_REG_2 */
10177 { "prefetcht1", { Mb
}, 0 },
10180 /* MOD_0F18_REG_3 */
10181 { "prefetcht2", { Mb
}, 0 },
10184 /* MOD_0F18_REG_4 */
10185 { "nop/reserved", { Mb
}, 0 },
10188 /* MOD_0F18_REG_5 */
10189 { "nop/reserved", { Mb
}, 0 },
10192 /* MOD_0F18_REG_6 */
10193 { "nop/reserved", { Mb
}, 0 },
10196 /* MOD_0F18_REG_7 */
10197 { "nop/reserved", { Mb
}, 0 },
10200 /* MOD_0F1A_PREFIX_0 */
10201 { "bndldx", { Gbnd
, Mv_bnd
}, 0 },
10202 { "nopQ", { Ev
}, 0 },
10205 /* MOD_0F1B_PREFIX_0 */
10206 { "bndstx", { Mv_bnd
, Gbnd
}, 0 },
10207 { "nopQ", { Ev
}, 0 },
10210 /* MOD_0F1B_PREFIX_1 */
10211 { "bndmk", { Gbnd
, Mv_bnd
}, 0 },
10212 { "nopQ", { Ev
}, 0 },
10215 /* MOD_0F1C_PREFIX_0 */
10216 { REG_TABLE (REG_0F1C_P_0_MOD_0
) },
10217 { "nopQ", { Ev
}, 0 },
10220 /* MOD_0F1E_PREFIX_1 */
10221 { "nopQ", { Ev
}, 0 },
10222 { REG_TABLE (REG_0F1E_P_1_MOD_3
) },
10227 { "movL", { Rd
, Td
}, 0 },
10232 { "movL", { Td
, Rd
}, 0 },
10235 /* MOD_0F2B_PREFIX_0 */
10236 {"movntps", { Mx
, XM
}, PREFIX_OPCODE
},
10239 /* MOD_0F2B_PREFIX_1 */
10240 {"movntss", { Md
, XM
}, PREFIX_OPCODE
},
10243 /* MOD_0F2B_PREFIX_2 */
10244 {"movntpd", { Mx
, XM
}, PREFIX_OPCODE
},
10247 /* MOD_0F2B_PREFIX_3 */
10248 {"movntsd", { Mq
, XM
}, PREFIX_OPCODE
},
10253 { "movmskpX", { Gdq
, XS
}, PREFIX_OPCODE
},
10256 /* MOD_0F71_REG_2 */
10258 { "psrlw", { MS
, Ib
}, 0 },
10261 /* MOD_0F71_REG_4 */
10263 { "psraw", { MS
, Ib
}, 0 },
10266 /* MOD_0F71_REG_6 */
10268 { "psllw", { MS
, Ib
}, 0 },
10271 /* MOD_0F72_REG_2 */
10273 { "psrld", { MS
, Ib
}, 0 },
10276 /* MOD_0F72_REG_4 */
10278 { "psrad", { MS
, Ib
}, 0 },
10281 /* MOD_0F72_REG_6 */
10283 { "pslld", { MS
, Ib
}, 0 },
10286 /* MOD_0F73_REG_2 */
10288 { "psrlq", { MS
, Ib
}, 0 },
10291 /* MOD_0F73_REG_3 */
10293 { PREFIX_TABLE (PREFIX_0F73_REG_3
) },
10296 /* MOD_0F73_REG_6 */
10298 { "psllq", { MS
, Ib
}, 0 },
10301 /* MOD_0F73_REG_7 */
10303 { PREFIX_TABLE (PREFIX_0F73_REG_7
) },
10306 /* MOD_0FAE_REG_0 */
10307 { "fxsave", { FXSAVE
}, 0 },
10308 { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3
) },
10311 /* MOD_0FAE_REG_1 */
10312 { "fxrstor", { FXSAVE
}, 0 },
10313 { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3
) },
10316 /* MOD_0FAE_REG_2 */
10317 { "ldmxcsr", { Md
}, 0 },
10318 { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3
) },
10321 /* MOD_0FAE_REG_3 */
10322 { "stmxcsr", { Md
}, 0 },
10323 { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3
) },
10326 /* MOD_0FAE_REG_4 */
10327 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0
) },
10328 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3
) },
10331 /* MOD_0FAE_REG_5 */
10332 { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_0
) },
10333 { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3
) },
10336 /* MOD_0FAE_REG_6 */
10337 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0
) },
10338 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3
) },
10341 /* MOD_0FAE_REG_7 */
10342 { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0
) },
10343 { RM_TABLE (RM_0FAE_REG_7_MOD_3
) },
10347 { "lssS", { Gv
, Mp
}, 0 },
10351 { "lfsS", { Gv
, Mp
}, 0 },
10355 { "lgsS", { Gv
, Mp
}, 0 },
10359 { PREFIX_TABLE (PREFIX_0FC3_MOD_0
) },
10362 /* MOD_0FC7_REG_3 */
10363 { "xrstors", { FXSAVE
}, 0 },
10366 /* MOD_0FC7_REG_4 */
10367 { "xsavec", { FXSAVE
}, 0 },
10370 /* MOD_0FC7_REG_5 */
10371 { "xsaves", { FXSAVE
}, 0 },
10374 /* MOD_0FC7_REG_6 */
10375 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0
) },
10376 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3
) }
10379 /* MOD_0FC7_REG_7 */
10380 { "vmptrst", { Mq
}, 0 },
10381 { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3
) }
10386 { "pmovmskb", { Gdq
, MS
}, 0 },
10389 /* MOD_0FE7_PREFIX_2 */
10390 { "movntdq", { Mx
, XM
}, 0 },
10393 /* MOD_0FF0_PREFIX_3 */
10394 { "lddqu", { XM
, M
}, 0 },
10397 /* MOD_0F382A_PREFIX_2 */
10398 { "movntdqa", { XM
, Mx
}, 0 },
10401 /* MOD_0F38F5_PREFIX_2 */
10402 { "wrussK", { M
, Gdq
}, PREFIX_OPCODE
},
10405 /* MOD_0F38F6_PREFIX_0 */
10406 { "wrssK", { M
, Gdq
}, PREFIX_OPCODE
},
10409 /* MOD_0F38F8_PREFIX_1 */
10410 { "enqcmds", { Gva
, M
}, PREFIX_OPCODE
},
10413 /* MOD_0F38F8_PREFIX_2 */
10414 { "movdir64b", { Gva
, M
}, PREFIX_OPCODE
},
10417 /* MOD_0F38F8_PREFIX_3 */
10418 { "enqcmd", { Gva
, M
}, PREFIX_OPCODE
},
10421 /* MOD_0F38F9_PREFIX_0 */
10422 { "movdiri", { Ev
, Gv
}, PREFIX_OPCODE
},
10426 { "bound{S|}", { Gv
, Ma
}, 0 },
10427 { EVEX_TABLE (EVEX_0F
) },
10431 { "lesS", { Gv
, Mp
}, 0 },
10432 { VEX_C4_TABLE (VEX_0F
) },
10436 { "ldsS", { Gv
, Mp
}, 0 },
10437 { VEX_C5_TABLE (VEX_0F
) },
10440 /* MOD_VEX_0F12_PREFIX_0 */
10441 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0
) },
10442 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1
) },
10445 /* MOD_VEX_0F12_PREFIX_2 */
10446 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0
) },
10450 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0
) },
10453 /* MOD_VEX_0F16_PREFIX_0 */
10454 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0
) },
10455 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1
) },
10458 /* MOD_VEX_0F16_PREFIX_2 */
10459 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0
) },
10463 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0
) },
10467 { "vmovntpX", { Mx
, XM
}, PREFIX_OPCODE
},
10470 /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
10472 { "kandw", { MaskG
, MaskVex
, MaskR
}, 0 },
10475 /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
10477 { "kandq", { MaskG
, MaskVex
, MaskR
}, 0 },
10480 /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
10482 { "kandb", { MaskG
, MaskVex
, MaskR
}, 0 },
10485 /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
10487 { "kandd", { MaskG
, MaskVex
, MaskR
}, 0 },
10490 /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
10492 { "kandnw", { MaskG
, MaskVex
, MaskR
}, 0 },
10495 /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
10497 { "kandnq", { MaskG
, MaskVex
, MaskR
}, 0 },
10500 /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
10502 { "kandnb", { MaskG
, MaskVex
, MaskR
}, 0 },
10505 /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
10507 { "kandnd", { MaskG
, MaskVex
, MaskR
}, 0 },
10510 /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
10512 { "knotw", { MaskG
, MaskR
}, 0 },
10515 /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
10517 { "knotq", { MaskG
, MaskR
}, 0 },
10520 /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
10522 { "knotb", { MaskG
, MaskR
}, 0 },
10525 /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
10527 { "knotd", { MaskG
, MaskR
}, 0 },
10530 /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
10532 { "korw", { MaskG
, MaskVex
, MaskR
}, 0 },
10535 /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
10537 { "korq", { MaskG
, MaskVex
, MaskR
}, 0 },
10540 /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
10542 { "korb", { MaskG
, MaskVex
, MaskR
}, 0 },
10545 /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
10547 { "kord", { MaskG
, MaskVex
, MaskR
}, 0 },
10550 /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
10552 { "kxnorw", { MaskG
, MaskVex
, MaskR
}, 0 },
10555 /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
10557 { "kxnorq", { MaskG
, MaskVex
, MaskR
}, 0 },
10560 /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
10562 { "kxnorb", { MaskG
, MaskVex
, MaskR
}, 0 },
10565 /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
10567 { "kxnord", { MaskG
, MaskVex
, MaskR
}, 0 },
10570 /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
10572 { "kxorw", { MaskG
, MaskVex
, MaskR
}, 0 },
10575 /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
10577 { "kxorq", { MaskG
, MaskVex
, MaskR
}, 0 },
10580 /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
10582 { "kxorb", { MaskG
, MaskVex
, MaskR
}, 0 },
10585 /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
10587 { "kxord", { MaskG
, MaskVex
, MaskR
}, 0 },
10590 /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
10592 { "kaddw", { MaskG
, MaskVex
, MaskR
}, 0 },
10595 /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
10597 { "kaddq", { MaskG
, MaskVex
, MaskR
}, 0 },
10600 /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
10602 { "kaddb", { MaskG
, MaskVex
, MaskR
}, 0 },
10605 /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
10607 { "kaddd", { MaskG
, MaskVex
, MaskR
}, 0 },
10610 /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
10612 { "kunpckwd", { MaskG
, MaskVex
, MaskR
}, 0 },
10615 /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
10617 { "kunpckdq", { MaskG
, MaskVex
, MaskR
}, 0 },
10620 /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
10622 { "kunpckbw", { MaskG
, MaskVex
, MaskR
}, 0 },
10627 { "vmovmskpX", { Gdq
, XS
}, PREFIX_OPCODE
},
10630 /* MOD_VEX_0F71_REG_2 */
10632 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2
) },
10635 /* MOD_VEX_0F71_REG_4 */
10637 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4
) },
10640 /* MOD_VEX_0F71_REG_6 */
10642 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6
) },
10645 /* MOD_VEX_0F72_REG_2 */
10647 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2
) },
10650 /* MOD_VEX_0F72_REG_4 */
10652 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4
) },
10655 /* MOD_VEX_0F72_REG_6 */
10657 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6
) },
10660 /* MOD_VEX_0F73_REG_2 */
10662 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2
) },
10665 /* MOD_VEX_0F73_REG_3 */
10667 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3
) },
10670 /* MOD_VEX_0F73_REG_6 */
10672 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6
) },
10675 /* MOD_VEX_0F73_REG_7 */
10677 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7
) },
10680 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10681 { "kmovw", { Ew
, MaskG
}, 0 },
10685 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10686 { "kmovq", { Eq
, MaskG
}, 0 },
10690 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10691 { "kmovb", { Eb
, MaskG
}, 0 },
10695 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10696 { "kmovd", { Ed
, MaskG
}, 0 },
10700 /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
10702 { "kmovw", { MaskG
, Rdq
}, 0 },
10705 /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
10707 { "kmovb", { MaskG
, Rdq
}, 0 },
10710 /* MOD_VEX_0F92_P_3_LEN_0 */
10712 { "kmovK", { MaskG
, Rdq
}, 0 },
10715 /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
10717 { "kmovw", { Gdq
, MaskR
}, 0 },
10720 /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
10722 { "kmovb", { Gdq
, MaskR
}, 0 },
10725 /* MOD_VEX_0F93_P_3_LEN_0 */
10727 { "kmovK", { Gdq
, MaskR
}, 0 },
10730 /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
10732 { "kortestw", { MaskG
, MaskR
}, 0 },
10735 /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
10737 { "kortestq", { MaskG
, MaskR
}, 0 },
10740 /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
10742 { "kortestb", { MaskG
, MaskR
}, 0 },
10745 /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
10747 { "kortestd", { MaskG
, MaskR
}, 0 },
10750 /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
10752 { "ktestw", { MaskG
, MaskR
}, 0 },
10755 /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
10757 { "ktestq", { MaskG
, MaskR
}, 0 },
10760 /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
10762 { "ktestb", { MaskG
, MaskR
}, 0 },
10765 /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
10767 { "ktestd", { MaskG
, MaskR
}, 0 },
10770 /* MOD_VEX_0FAE_REG_2 */
10771 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0
) },
10774 /* MOD_VEX_0FAE_REG_3 */
10775 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0
) },
10778 /* MOD_VEX_0FD7_PREFIX_2 */
10780 { "vpmovmskb", { Gdq
, XS
}, 0 },
10783 /* MOD_VEX_0FE7_PREFIX_2 */
10784 { "vmovntdq", { Mx
, XM
}, 0 },
10787 /* MOD_VEX_0FF0_PREFIX_3 */
10788 { "vlddqu", { XM
, M
}, 0 },
10791 /* MOD_VEX_0F381A_PREFIX_2 */
10792 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0
) },
10795 /* MOD_VEX_0F382A_PREFIX_2 */
10796 { "vmovntdqa", { XM
, Mx
}, 0 },
10799 /* MOD_VEX_0F382C_PREFIX_2 */
10800 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0
) },
10803 /* MOD_VEX_0F382D_PREFIX_2 */
10804 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0
) },
10807 /* MOD_VEX_0F382E_PREFIX_2 */
10808 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0
) },
10811 /* MOD_VEX_0F382F_PREFIX_2 */
10812 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0
) },
10815 /* MOD_VEX_0F385A_PREFIX_2 */
10816 { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0
) },
10819 /* MOD_VEX_0F388C_PREFIX_2 */
10820 { "vpmaskmov%LW", { XM
, Vex
, Mx
}, 0 },
10823 /* MOD_VEX_0F388E_PREFIX_2 */
10824 { "vpmaskmov%LW", { Mx
, Vex
, XM
}, 0 },
10827 /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
10829 { "kshiftrb", { MaskG
, MaskR
, Ib
}, 0 },
10832 /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
10834 { "kshiftrw", { MaskG
, MaskR
, Ib
}, 0 },
10837 /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
10839 { "kshiftrd", { MaskG
, MaskR
, Ib
}, 0 },
10842 /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
10844 { "kshiftrq", { MaskG
, MaskR
, Ib
}, 0 },
10847 /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
10849 { "kshiftlb", { MaskG
, MaskR
, Ib
}, 0 },
10852 /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
10854 { "kshiftlw", { MaskG
, MaskR
, Ib
}, 0 },
10857 /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
10859 { "kshiftld", { MaskG
, MaskR
, Ib
}, 0 },
10862 /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
10864 { "kshiftlq", { MaskG
, MaskR
, Ib
}, 0 },
10867 #include "i386-dis-evex-mod.h"
10870 static const struct dis386 rm_table
[][8] = {
10873 { "xabort", { Skip_MODRM
, Ib
}, 0 },
10877 { "xbeginT", { Skip_MODRM
, Jdqw
}, 0 },
10880 /* RM_0F01_REG_0 */
10881 { "enclv", { Skip_MODRM
}, 0 },
10882 { "vmcall", { Skip_MODRM
}, 0 },
10883 { "vmlaunch", { Skip_MODRM
}, 0 },
10884 { "vmresume", { Skip_MODRM
}, 0 },
10885 { "vmxoff", { Skip_MODRM
}, 0 },
10886 { "pconfig", { Skip_MODRM
}, 0 },
10889 /* RM_0F01_REG_1 */
10890 { "monitor", { { OP_Monitor
, 0 } }, 0 },
10891 { "mwait", { { OP_Mwait
, 0 } }, 0 },
10892 { "clac", { Skip_MODRM
}, 0 },
10893 { "stac", { Skip_MODRM
}, 0 },
10897 { "encls", { Skip_MODRM
}, 0 },
10900 /* RM_0F01_REG_2 */
10901 { "xgetbv", { Skip_MODRM
}, 0 },
10902 { "xsetbv", { Skip_MODRM
}, 0 },
10905 { "vmfunc", { Skip_MODRM
}, 0 },
10906 { "xend", { Skip_MODRM
}, 0 },
10907 { "xtest", { Skip_MODRM
}, 0 },
10908 { "enclu", { Skip_MODRM
}, 0 },
10911 /* RM_0F01_REG_3 */
10912 { "vmrun", { Skip_MODRM
}, 0 },
10913 { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1
) },
10914 { "vmload", { Skip_MODRM
}, 0 },
10915 { "vmsave", { Skip_MODRM
}, 0 },
10916 { "stgi", { Skip_MODRM
}, 0 },
10917 { "clgi", { Skip_MODRM
}, 0 },
10918 { "skinit", { Skip_MODRM
}, 0 },
10919 { "invlpga", { Skip_MODRM
}, 0 },
10922 /* RM_0F01_REG_5_MOD_3 */
10923 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0
) },
10924 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1
) },
10925 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2
) },
10929 { "rdpkru", { Skip_MODRM
}, 0 },
10930 { "wrpkru", { Skip_MODRM
}, 0 },
10933 /* RM_0F01_REG_7_MOD_3 */
10934 { "swapgs", { Skip_MODRM
}, 0 },
10935 { "rdtscp", { Skip_MODRM
}, 0 },
10936 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2
) },
10937 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_3
) },
10938 { "clzero", { Skip_MODRM
}, 0 },
10939 { "rdpru", { Skip_MODRM
}, 0 },
10942 /* RM_0F1E_P_1_MOD_3_REG_7 */
10943 { "nopQ", { Ev
}, 0 },
10944 { "nopQ", { Ev
}, 0 },
10945 { "endbr64", { Skip_MODRM
}, PREFIX_OPCODE
},
10946 { "endbr32", { Skip_MODRM
}, PREFIX_OPCODE
},
10947 { "nopQ", { Ev
}, 0 },
10948 { "nopQ", { Ev
}, 0 },
10949 { "nopQ", { Ev
}, 0 },
10950 { "nopQ", { Ev
}, 0 },
10953 /* RM_0FAE_REG_6_MOD_3 */
10954 { "mfence", { Skip_MODRM
}, 0 },
10957 /* RM_0FAE_REG_7_MOD_3 */
10958 { "sfence", { Skip_MODRM
}, 0 },
10963 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
10965 /* We use the high bit to indicate different name for the same
10967 #define REP_PREFIX (0xf3 | 0x100)
10968 #define XACQUIRE_PREFIX (0xf2 | 0x200)
10969 #define XRELEASE_PREFIX (0xf3 | 0x400)
10970 #define BND_PREFIX (0xf2 | 0x400)
10971 #define NOTRACK_PREFIX (0x3e | 0x100)
10973 /* Remember if the current op is a jump instruction. */
10974 static bfd_boolean op_is_jump
= FALSE
;
10979 int newrex
, i
, length
;
10984 last_lock_prefix
= -1;
10985 last_repz_prefix
= -1;
10986 last_repnz_prefix
= -1;
10987 last_data_prefix
= -1;
10988 last_addr_prefix
= -1;
10989 last_rex_prefix
= -1;
10990 last_seg_prefix
= -1;
10992 active_seg_prefix
= 0;
10993 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
10994 all_prefixes
[i
] = 0;
10997 /* The maximum instruction length is 15bytes. */
10998 while (length
< MAX_CODE_LENGTH
- 1)
11000 FETCH_DATA (the_info
, codep
+ 1);
11004 /* REX prefixes family. */
11021 if (address_mode
== mode_64bit
)
11025 last_rex_prefix
= i
;
11028 prefixes
|= PREFIX_REPZ
;
11029 last_repz_prefix
= i
;
11032 prefixes
|= PREFIX_REPNZ
;
11033 last_repnz_prefix
= i
;
11036 prefixes
|= PREFIX_LOCK
;
11037 last_lock_prefix
= i
;
11040 prefixes
|= PREFIX_CS
;
11041 last_seg_prefix
= i
;
11042 active_seg_prefix
= PREFIX_CS
;
11045 prefixes
|= PREFIX_SS
;
11046 last_seg_prefix
= i
;
11047 active_seg_prefix
= PREFIX_SS
;
11050 prefixes
|= PREFIX_DS
;
11051 last_seg_prefix
= i
;
11052 active_seg_prefix
= PREFIX_DS
;
11055 prefixes
|= PREFIX_ES
;
11056 last_seg_prefix
= i
;
11057 active_seg_prefix
= PREFIX_ES
;
11060 prefixes
|= PREFIX_FS
;
11061 last_seg_prefix
= i
;
11062 active_seg_prefix
= PREFIX_FS
;
11065 prefixes
|= PREFIX_GS
;
11066 last_seg_prefix
= i
;
11067 active_seg_prefix
= PREFIX_GS
;
11070 prefixes
|= PREFIX_DATA
;
11071 last_data_prefix
= i
;
11074 prefixes
|= PREFIX_ADDR
;
11075 last_addr_prefix
= i
;
11078 /* fwait is really an instruction. If there are prefixes
11079 before the fwait, they belong to the fwait, *not* to the
11080 following instruction. */
11082 if (prefixes
|| rex
)
11084 prefixes
|= PREFIX_FWAIT
;
11086 /* This ensures that the previous REX prefixes are noticed
11087 as unused prefixes, as in the return case below. */
11091 prefixes
= PREFIX_FWAIT
;
11096 /* Rex is ignored when followed by another prefix. */
11102 if (*codep
!= FWAIT_OPCODE
)
11103 all_prefixes
[i
++] = *codep
;
11111 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11114 static const char *
11115 prefix_name (int pref
, int sizeflag
)
11117 static const char *rexes
[16] =
11120 "rex.B", /* 0x41 */
11121 "rex.X", /* 0x42 */
11122 "rex.XB", /* 0x43 */
11123 "rex.R", /* 0x44 */
11124 "rex.RB", /* 0x45 */
11125 "rex.RX", /* 0x46 */
11126 "rex.RXB", /* 0x47 */
11127 "rex.W", /* 0x48 */
11128 "rex.WB", /* 0x49 */
11129 "rex.WX", /* 0x4a */
11130 "rex.WXB", /* 0x4b */
11131 "rex.WR", /* 0x4c */
11132 "rex.WRB", /* 0x4d */
11133 "rex.WRX", /* 0x4e */
11134 "rex.WRXB", /* 0x4f */
11139 /* REX prefixes family. */
11156 return rexes
[pref
- 0x40];
11176 return (sizeflag
& DFLAG
) ? "data16" : "data32";
11178 if (address_mode
== mode_64bit
)
11179 return (sizeflag
& AFLAG
) ? "addr32" : "addr64";
11181 return (sizeflag
& AFLAG
) ? "addr16" : "addr32";
11186 case XACQUIRE_PREFIX
:
11188 case XRELEASE_PREFIX
:
11192 case NOTRACK_PREFIX
:
11199 static char op_out
[MAX_OPERANDS
][100];
11200 static int op_ad
, op_index
[MAX_OPERANDS
];
11201 static int two_source_ops
;
11202 static bfd_vma op_address
[MAX_OPERANDS
];
11203 static bfd_vma op_riprel
[MAX_OPERANDS
];
11204 static bfd_vma start_pc
;
11207 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11208 * (see topic "Redundant prefixes" in the "Differences from 8086"
11209 * section of the "Virtual 8086 Mode" chapter.)
11210 * 'pc' should be the address of this instruction, it will
11211 * be used to print the target address if this is a relative jump or call
11212 * The function returns the length of this instruction in bytes.
11215 static char intel_syntax
;
11216 static char intel_mnemonic
= !SYSV386_COMPAT
;
11217 static char open_char
;
11218 static char close_char
;
11219 static char separator_char
;
11220 static char scale_char
;
11228 static enum x86_64_isa isa64
;
11230 /* Here for backwards compatibility. When gdb stops using
11231 print_insn_i386_att and print_insn_i386_intel these functions can
11232 disappear, and print_insn_i386 be merged into print_insn. */
11234 print_insn_i386_att (bfd_vma pc
, disassemble_info
*info
)
11238 return print_insn (pc
, info
);
11242 print_insn_i386_intel (bfd_vma pc
, disassemble_info
*info
)
11246 return print_insn (pc
, info
);
11250 print_insn_i386 (bfd_vma pc
, disassemble_info
*info
)
11254 return print_insn (pc
, info
);
11258 print_i386_disassembler_options (FILE *stream
)
11260 fprintf (stream
, _("\n\
11261 The following i386/x86-64 specific disassembler options are supported for use\n\
11262 with the -M switch (multiple options should be separated by commas):\n"));
11264 fprintf (stream
, _(" x86-64 Disassemble in 64bit mode\n"));
11265 fprintf (stream
, _(" i386 Disassemble in 32bit mode\n"));
11266 fprintf (stream
, _(" i8086 Disassemble in 16bit mode\n"));
11267 fprintf (stream
, _(" att Display instruction in AT&T syntax\n"));
11268 fprintf (stream
, _(" intel Display instruction in Intel syntax\n"));
11269 fprintf (stream
, _(" att-mnemonic\n"
11270 " Display instruction in AT&T mnemonic\n"));
11271 fprintf (stream
, _(" intel-mnemonic\n"
11272 " Display instruction in Intel mnemonic\n"));
11273 fprintf (stream
, _(" addr64 Assume 64bit address size\n"));
11274 fprintf (stream
, _(" addr32 Assume 32bit address size\n"));
11275 fprintf (stream
, _(" addr16 Assume 16bit address size\n"));
11276 fprintf (stream
, _(" data32 Assume 32bit data size\n"));
11277 fprintf (stream
, _(" data16 Assume 16bit data size\n"));
11278 fprintf (stream
, _(" suffix Always display instruction suffix in AT&T syntax\n"));
11279 fprintf (stream
, _(" amd64 Display instruction in AMD64 ISA\n"));
11280 fprintf (stream
, _(" intel64 Display instruction in Intel64 ISA\n"));
11284 static const struct dis386 bad_opcode
= { "(bad)", { XX
}, 0 };
11286 /* Get a pointer to struct dis386 with a valid name. */
11288 static const struct dis386
*
11289 get_valid_dis386 (const struct dis386
*dp
, disassemble_info
*info
)
11291 int vindex
, vex_table_index
;
11293 if (dp
->name
!= NULL
)
11296 switch (dp
->op
[0].bytemode
)
11298 case USE_REG_TABLE
:
11299 dp
= ®_table
[dp
->op
[1].bytemode
][modrm
.reg
];
11302 case USE_MOD_TABLE
:
11303 vindex
= modrm
.mod
== 0x3 ? 1 : 0;
11304 dp
= &mod_table
[dp
->op
[1].bytemode
][vindex
];
11308 dp
= &rm_table
[dp
->op
[1].bytemode
][modrm
.rm
];
11311 case USE_PREFIX_TABLE
:
11314 /* The prefix in VEX is implicit. */
11315 switch (vex
.prefix
)
11320 case REPE_PREFIX_OPCODE
:
11323 case DATA_PREFIX_OPCODE
:
11326 case REPNE_PREFIX_OPCODE
:
11336 int last_prefix
= -1;
11339 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
11340 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
11342 if ((prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0)
11344 if (last_repz_prefix
> last_repnz_prefix
)
11347 prefix
= PREFIX_REPZ
;
11348 last_prefix
= last_repz_prefix
;
11353 prefix
= PREFIX_REPNZ
;
11354 last_prefix
= last_repnz_prefix
;
11357 /* Check if prefix should be ignored. */
11358 if ((((prefix_table
[dp
->op
[1].bytemode
][vindex
].prefix_requirement
11359 & PREFIX_IGNORED
) >> PREFIX_IGNORED_SHIFT
)
11364 if (vindex
== 0 && (prefixes
& PREFIX_DATA
) != 0)
11367 prefix
= PREFIX_DATA
;
11368 last_prefix
= last_data_prefix
;
11373 used_prefixes
|= prefix
;
11374 all_prefixes
[last_prefix
] = 0;
11377 dp
= &prefix_table
[dp
->op
[1].bytemode
][vindex
];
11380 case USE_X86_64_TABLE
:
11381 vindex
= address_mode
== mode_64bit
? 1 : 0;
11382 dp
= &x86_64_table
[dp
->op
[1].bytemode
][vindex
];
11385 case USE_3BYTE_TABLE
:
11386 FETCH_DATA (info
, codep
+ 2);
11388 dp
= &three_byte_table
[dp
->op
[1].bytemode
][vindex
];
11390 modrm
.mod
= (*codep
>> 6) & 3;
11391 modrm
.reg
= (*codep
>> 3) & 7;
11392 modrm
.rm
= *codep
& 7;
11395 case USE_VEX_LEN_TABLE
:
11399 switch (vex
.length
)
11412 dp
= &vex_len_table
[dp
->op
[1].bytemode
][vindex
];
11415 case USE_EVEX_LEN_TABLE
:
11419 switch (vex
.length
)
11435 dp
= &evex_len_table
[dp
->op
[1].bytemode
][vindex
];
11438 case USE_XOP_8F_TABLE
:
11439 FETCH_DATA (info
, codep
+ 3);
11440 rex
= ~(*codep
>> 5) & 0x7;
11442 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
11443 switch ((*codep
& 0x1f))
11449 vex_table_index
= XOP_08
;
11452 vex_table_index
= XOP_09
;
11455 vex_table_index
= XOP_0A
;
11459 vex
.w
= *codep
& 0x80;
11460 if (vex
.w
&& address_mode
== mode_64bit
)
11463 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11464 if (address_mode
!= mode_64bit
)
11466 /* In 16/32-bit mode REX_B is silently ignored. */
11470 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11471 switch ((*codep
& 0x3))
11476 vex
.prefix
= DATA_PREFIX_OPCODE
;
11479 vex
.prefix
= REPE_PREFIX_OPCODE
;
11482 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11489 dp
= &xop_table
[vex_table_index
][vindex
];
11492 FETCH_DATA (info
, codep
+ 1);
11493 modrm
.mod
= (*codep
>> 6) & 3;
11494 modrm
.reg
= (*codep
>> 3) & 7;
11495 modrm
.rm
= *codep
& 7;
11498 case USE_VEX_C4_TABLE
:
11500 FETCH_DATA (info
, codep
+ 3);
11501 rex
= ~(*codep
>> 5) & 0x7;
11502 switch ((*codep
& 0x1f))
11508 vex_table_index
= VEX_0F
;
11511 vex_table_index
= VEX_0F38
;
11514 vex_table_index
= VEX_0F3A
;
11518 vex
.w
= *codep
& 0x80;
11519 if (address_mode
== mode_64bit
)
11526 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
11527 is ignored, other REX bits are 0 and the highest bit in
11528 VEX.vvvv is also ignored (but we mustn't clear it here). */
11531 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11532 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11533 switch ((*codep
& 0x3))
11538 vex
.prefix
= DATA_PREFIX_OPCODE
;
11541 vex
.prefix
= REPE_PREFIX_OPCODE
;
11544 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11551 dp
= &vex_table
[vex_table_index
][vindex
];
11553 /* There is no MODRM byte for VEX0F 77. */
11554 if (vex_table_index
!= VEX_0F
|| vindex
!= 0x77)
11556 FETCH_DATA (info
, codep
+ 1);
11557 modrm
.mod
= (*codep
>> 6) & 3;
11558 modrm
.reg
= (*codep
>> 3) & 7;
11559 modrm
.rm
= *codep
& 7;
11563 case USE_VEX_C5_TABLE
:
11565 FETCH_DATA (info
, codep
+ 2);
11566 rex
= (*codep
& 0x80) ? 0 : REX_R
;
11568 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
11570 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11571 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11572 switch ((*codep
& 0x3))
11577 vex
.prefix
= DATA_PREFIX_OPCODE
;
11580 vex
.prefix
= REPE_PREFIX_OPCODE
;
11583 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11590 dp
= &vex_table
[dp
->op
[1].bytemode
][vindex
];
11592 /* There is no MODRM byte for VEX 77. */
11593 if (vindex
!= 0x77)
11595 FETCH_DATA (info
, codep
+ 1);
11596 modrm
.mod
= (*codep
>> 6) & 3;
11597 modrm
.reg
= (*codep
>> 3) & 7;
11598 modrm
.rm
= *codep
& 7;
11602 case USE_VEX_W_TABLE
:
11606 dp
= &vex_w_table
[dp
->op
[1].bytemode
][vex
.w
? 1 : 0];
11609 case USE_EVEX_TABLE
:
11610 two_source_ops
= 0;
11613 FETCH_DATA (info
, codep
+ 4);
11614 /* The first byte after 0x62. */
11615 rex
= ~(*codep
>> 5) & 0x7;
11616 vex
.r
= *codep
& 0x10;
11617 switch ((*codep
& 0xf))
11620 return &bad_opcode
;
11622 vex_table_index
= EVEX_0F
;
11625 vex_table_index
= EVEX_0F38
;
11628 vex_table_index
= EVEX_0F3A
;
11632 /* The second byte after 0x62. */
11634 vex
.w
= *codep
& 0x80;
11635 if (vex
.w
&& address_mode
== mode_64bit
)
11638 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11641 if (!(*codep
& 0x4))
11642 return &bad_opcode
;
11644 switch ((*codep
& 0x3))
11649 vex
.prefix
= DATA_PREFIX_OPCODE
;
11652 vex
.prefix
= REPE_PREFIX_OPCODE
;
11655 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11659 /* The third byte after 0x62. */
11662 /* Remember the static rounding bits. */
11663 vex
.ll
= (*codep
>> 5) & 3;
11664 vex
.b
= (*codep
& 0x10) != 0;
11666 vex
.v
= *codep
& 0x8;
11667 vex
.mask_register_specifier
= *codep
& 0x7;
11668 vex
.zeroing
= *codep
& 0x80;
11670 if (address_mode
!= mode_64bit
)
11672 /* In 16/32-bit mode silently ignore following bits. */
11682 dp
= &evex_table
[vex_table_index
][vindex
];
11684 FETCH_DATA (info
, codep
+ 1);
11685 modrm
.mod
= (*codep
>> 6) & 3;
11686 modrm
.reg
= (*codep
>> 3) & 7;
11687 modrm
.rm
= *codep
& 7;
11689 /* Set vector length. */
11690 if (modrm
.mod
== 3 && vex
.b
)
11706 return &bad_opcode
;
11719 if (dp
->name
!= NULL
)
11722 return get_valid_dis386 (dp
, info
);
11726 get_sib (disassemble_info
*info
, int sizeflag
)
11728 /* If modrm.mod == 3, operand must be register. */
11730 && ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
11734 FETCH_DATA (info
, codep
+ 2);
11735 sib
.index
= (codep
[1] >> 3) & 7;
11736 sib
.scale
= (codep
[1] >> 6) & 3;
11737 sib
.base
= codep
[1] & 7;
11742 print_insn (bfd_vma pc
, disassemble_info
*info
)
11744 const struct dis386
*dp
;
11746 char *op_txt
[MAX_OPERANDS
];
11748 int sizeflag
, orig_sizeflag
;
11750 struct dis_private priv
;
11753 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
11754 if ((info
->mach
& bfd_mach_i386_i386
) != 0)
11755 address_mode
= mode_32bit
;
11756 else if (info
->mach
== bfd_mach_i386_i8086
)
11758 address_mode
= mode_16bit
;
11759 priv
.orig_sizeflag
= 0;
11762 address_mode
= mode_64bit
;
11764 if (intel_syntax
== (char) -1)
11765 intel_syntax
= (info
->mach
& bfd_mach_i386_intel_syntax
) != 0;
11767 for (p
= info
->disassembler_options
; p
!= NULL
; )
11769 if (CONST_STRNEQ (p
, "amd64"))
11771 else if (CONST_STRNEQ (p
, "intel64"))
11773 else if (CONST_STRNEQ (p
, "x86-64"))
11775 address_mode
= mode_64bit
;
11776 priv
.orig_sizeflag
|= AFLAG
| DFLAG
;
11778 else if (CONST_STRNEQ (p
, "i386"))
11780 address_mode
= mode_32bit
;
11781 priv
.orig_sizeflag
|= AFLAG
| DFLAG
;
11783 else if (CONST_STRNEQ (p
, "i8086"))
11785 address_mode
= mode_16bit
;
11786 priv
.orig_sizeflag
&= ~(AFLAG
| DFLAG
);
11788 else if (CONST_STRNEQ (p
, "intel"))
11791 if (CONST_STRNEQ (p
+ 5, "-mnemonic"))
11792 intel_mnemonic
= 1;
11794 else if (CONST_STRNEQ (p
, "att"))
11797 if (CONST_STRNEQ (p
+ 3, "-mnemonic"))
11798 intel_mnemonic
= 0;
11800 else if (CONST_STRNEQ (p
, "addr"))
11802 if (address_mode
== mode_64bit
)
11804 if (p
[4] == '3' && p
[5] == '2')
11805 priv
.orig_sizeflag
&= ~AFLAG
;
11806 else if (p
[4] == '6' && p
[5] == '4')
11807 priv
.orig_sizeflag
|= AFLAG
;
11811 if (p
[4] == '1' && p
[5] == '6')
11812 priv
.orig_sizeflag
&= ~AFLAG
;
11813 else if (p
[4] == '3' && p
[5] == '2')
11814 priv
.orig_sizeflag
|= AFLAG
;
11817 else if (CONST_STRNEQ (p
, "data"))
11819 if (p
[4] == '1' && p
[5] == '6')
11820 priv
.orig_sizeflag
&= ~DFLAG
;
11821 else if (p
[4] == '3' && p
[5] == '2')
11822 priv
.orig_sizeflag
|= DFLAG
;
11824 else if (CONST_STRNEQ (p
, "suffix"))
11825 priv
.orig_sizeflag
|= SUFFIX_ALWAYS
;
11827 p
= strchr (p
, ',');
11832 if (address_mode
== mode_64bit
&& sizeof (bfd_vma
) < 8)
11834 (*info
->fprintf_func
) (info
->stream
,
11835 _("64-bit address is disabled"));
11841 names64
= intel_names64
;
11842 names32
= intel_names32
;
11843 names16
= intel_names16
;
11844 names8
= intel_names8
;
11845 names8rex
= intel_names8rex
;
11846 names_seg
= intel_names_seg
;
11847 names_mm
= intel_names_mm
;
11848 names_bnd
= intel_names_bnd
;
11849 names_xmm
= intel_names_xmm
;
11850 names_ymm
= intel_names_ymm
;
11851 names_zmm
= intel_names_zmm
;
11852 index64
= intel_index64
;
11853 index32
= intel_index32
;
11854 names_mask
= intel_names_mask
;
11855 index16
= intel_index16
;
11858 separator_char
= '+';
11863 names64
= att_names64
;
11864 names32
= att_names32
;
11865 names16
= att_names16
;
11866 names8
= att_names8
;
11867 names8rex
= att_names8rex
;
11868 names_seg
= att_names_seg
;
11869 names_mm
= att_names_mm
;
11870 names_bnd
= att_names_bnd
;
11871 names_xmm
= att_names_xmm
;
11872 names_ymm
= att_names_ymm
;
11873 names_zmm
= att_names_zmm
;
11874 index64
= att_index64
;
11875 index32
= att_index32
;
11876 names_mask
= att_names_mask
;
11877 index16
= att_index16
;
11880 separator_char
= ',';
11884 /* The output looks better if we put 7 bytes on a line, since that
11885 puts most long word instructions on a single line. Use 8 bytes
11887 if ((info
->mach
& bfd_mach_l1om
) != 0)
11888 info
->bytes_per_line
= 8;
11890 info
->bytes_per_line
= 7;
11892 info
->private_data
= &priv
;
11893 priv
.max_fetched
= priv
.the_buffer
;
11894 priv
.insn_start
= pc
;
11897 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
11905 start_codep
= priv
.the_buffer
;
11906 codep
= priv
.the_buffer
;
11908 if (OPCODES_SIGSETJMP (priv
.bailout
) != 0)
11912 /* Getting here means we tried for data but didn't get it. That
11913 means we have an incomplete instruction of some sort. Just
11914 print the first byte as a prefix or a .byte pseudo-op. */
11915 if (codep
> priv
.the_buffer
)
11917 name
= prefix_name (priv
.the_buffer
[0], priv
.orig_sizeflag
);
11919 (*info
->fprintf_func
) (info
->stream
, "%s", name
);
11922 /* Just print the first byte as a .byte instruction. */
11923 (*info
->fprintf_func
) (info
->stream
, ".byte 0x%x",
11924 (unsigned int) priv
.the_buffer
[0]);
11934 sizeflag
= priv
.orig_sizeflag
;
11936 if (!ckprefix () || rex_used
)
11938 /* Too many prefixes or unused REX prefixes. */
11940 i
< (int) ARRAY_SIZE (all_prefixes
) && all_prefixes
[i
];
11942 (*info
->fprintf_func
) (info
->stream
, "%s%s",
11944 prefix_name (all_prefixes
[i
], sizeflag
));
11948 insn_codep
= codep
;
11950 FETCH_DATA (info
, codep
+ 1);
11951 two_source_ops
= (*codep
== 0x62) || (*codep
== 0xc8);
11953 if (((prefixes
& PREFIX_FWAIT
)
11954 && ((*codep
< 0xd8) || (*codep
> 0xdf))))
11956 /* Handle prefixes before fwait. */
11957 for (i
= 0; i
< fwait_prefix
&& all_prefixes
[i
];
11959 (*info
->fprintf_func
) (info
->stream
, "%s ",
11960 prefix_name (all_prefixes
[i
], sizeflag
));
11961 (*info
->fprintf_func
) (info
->stream
, "fwait");
11965 if (*codep
== 0x0f)
11967 unsigned char threebyte
;
11970 FETCH_DATA (info
, codep
+ 1);
11971 threebyte
= *codep
;
11972 dp
= &dis386_twobyte
[threebyte
];
11973 need_modrm
= twobyte_has_modrm
[*codep
];
11978 dp
= &dis386
[*codep
];
11979 need_modrm
= onebyte_has_modrm
[*codep
];
11983 /* Save sizeflag for printing the extra prefixes later before updating
11984 it for mnemonic and operand processing. The prefix names depend
11985 only on the address mode. */
11986 orig_sizeflag
= sizeflag
;
11987 if (prefixes
& PREFIX_ADDR
)
11989 if ((prefixes
& PREFIX_DATA
))
11995 FETCH_DATA (info
, codep
+ 1);
11996 modrm
.mod
= (*codep
>> 6) & 3;
11997 modrm
.reg
= (*codep
>> 3) & 7;
11998 modrm
.rm
= *codep
& 7;
12004 memset (&vex
, 0, sizeof (vex
));
12006 if (dp
->name
== NULL
&& dp
->op
[0].bytemode
== FLOATCODE
)
12008 get_sib (info
, sizeflag
);
12009 dofloat (sizeflag
);
12013 dp
= get_valid_dis386 (dp
, info
);
12014 if (dp
!= NULL
&& putop (dp
->name
, sizeflag
) == 0)
12016 get_sib (info
, sizeflag
);
12017 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12020 op_ad
= MAX_OPERANDS
- 1 - i
;
12022 (*dp
->op
[i
].rtn
) (dp
->op
[i
].bytemode
, sizeflag
);
12023 /* For EVEX instruction after the last operand masking
12024 should be printed. */
12025 if (i
== 0 && vex
.evex
)
12027 /* Don't print {%k0}. */
12028 if (vex
.mask_register_specifier
)
12031 oappend (names_mask
[vex
.mask_register_specifier
]);
12041 /* Clear instruction information. */
12044 the_info
->insn_info_valid
= 0;
12045 the_info
->branch_delay_insns
= 0;
12046 the_info
->data_size
= 0;
12047 the_info
->insn_type
= dis_noninsn
;
12048 the_info
->target
= 0;
12049 the_info
->target2
= 0;
12052 /* Reset jump operation indicator. */
12053 op_is_jump
= FALSE
;
12056 int jump_detection
= 0;
12058 /* Extract flags. */
12059 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12061 if ((dp
->op
[i
].rtn
== OP_J
)
12062 || (dp
->op
[i
].rtn
== OP_indirE
))
12063 jump_detection
|= 1;
12064 else if ((dp
->op
[i
].rtn
== BND_Fixup
)
12065 || (!dp
->op
[i
].rtn
&& !dp
->op
[i
].bytemode
))
12066 jump_detection
|= 2;
12067 else if ((dp
->op
[i
].bytemode
== cond_jump_mode
)
12068 || (dp
->op
[i
].bytemode
== loop_jcxz_mode
))
12069 jump_detection
|= 4;
12072 /* Determine if this is a jump or branch. */
12073 if ((jump_detection
& 0x3) == 0x3)
12076 if (jump_detection
& 0x4)
12077 the_info
->insn_type
= dis_condbranch
;
12079 the_info
->insn_type
=
12080 (dp
->name
&& !strncmp(dp
->name
, "call", 4))
12081 ? dis_jsr
: dis_branch
;
12085 /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
12086 are all 0s in inverted form. */
12087 if (need_vex
&& vex
.register_specifier
!= 0)
12089 (*info
->fprintf_func
) (info
->stream
, "(bad)");
12090 return end_codep
- priv
.the_buffer
;
12093 /* Check if the REX prefix is used. */
12094 if ((rex
^ rex_used
) == 0 && !need_vex
&& last_rex_prefix
>= 0)
12095 all_prefixes
[last_rex_prefix
] = 0;
12097 /* Check if the SEG prefix is used. */
12098 if ((prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
| PREFIX_ES
12099 | PREFIX_FS
| PREFIX_GS
)) != 0
12100 && (used_prefixes
& active_seg_prefix
) != 0)
12101 all_prefixes
[last_seg_prefix
] = 0;
12103 /* Check if the ADDR prefix is used. */
12104 if ((prefixes
& PREFIX_ADDR
) != 0
12105 && (used_prefixes
& PREFIX_ADDR
) != 0)
12106 all_prefixes
[last_addr_prefix
] = 0;
12108 /* Check if the DATA prefix is used. */
12109 if ((prefixes
& PREFIX_DATA
) != 0
12110 && (used_prefixes
& PREFIX_DATA
) != 0
12112 all_prefixes
[last_data_prefix
] = 0;
12114 /* Print the extra prefixes. */
12116 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
12117 if (all_prefixes
[i
])
12120 name
= prefix_name (all_prefixes
[i
], orig_sizeflag
);
12123 prefix_length
+= strlen (name
) + 1;
12124 (*info
->fprintf_func
) (info
->stream
, "%s ", name
);
12127 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
12128 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
12129 used by putop and MMX/SSE operand and may be overriden by the
12130 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
12132 if (dp
->prefix_requirement
== PREFIX_OPCODE
12134 ? vex
.prefix
== REPE_PREFIX_OPCODE
12135 || vex
.prefix
== REPNE_PREFIX_OPCODE
12137 & (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0)
12139 & (PREFIX_REPZ
| PREFIX_REPNZ
)) == 0)
12141 ? vex
.prefix
== DATA_PREFIX_OPCODE
12143 & (PREFIX_REPZ
| PREFIX_REPNZ
| PREFIX_DATA
))
12145 && (used_prefixes
& PREFIX_DATA
) == 0))
12146 || (vex
.evex
&& !vex
.w
!= !(used_prefixes
& PREFIX_DATA
))))
12148 (*info
->fprintf_func
) (info
->stream
, "(bad)");
12149 return end_codep
- priv
.the_buffer
;
12152 /* Check maximum code length. */
12153 if ((codep
- start_codep
) > MAX_CODE_LENGTH
)
12155 (*info
->fprintf_func
) (info
->stream
, "(bad)");
12156 return MAX_CODE_LENGTH
;
12159 obufp
= mnemonicendp
;
12160 for (i
= strlen (obuf
) + prefix_length
; i
< 6; i
++)
12163 (*info
->fprintf_func
) (info
->stream
, "%s", obuf
);
12165 /* The enter and bound instructions are printed with operands in the same
12166 order as the intel book; everything else is printed in reverse order. */
12167 if (intel_syntax
|| two_source_ops
)
12171 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12172 op_txt
[i
] = op_out
[i
];
12174 if (intel_syntax
&& dp
&& dp
->op
[2].rtn
== OP_Rounding
12175 && dp
->op
[3].rtn
== OP_E
&& dp
->op
[4].rtn
== NULL
)
12177 op_txt
[2] = op_out
[3];
12178 op_txt
[3] = op_out
[2];
12181 for (i
= 0; i
< (MAX_OPERANDS
>> 1); ++i
)
12183 op_ad
= op_index
[i
];
12184 op_index
[i
] = op_index
[MAX_OPERANDS
- 1 - i
];
12185 op_index
[MAX_OPERANDS
- 1 - i
] = op_ad
;
12186 riprel
= op_riprel
[i
];
12187 op_riprel
[i
] = op_riprel
[MAX_OPERANDS
- 1 - i
];
12188 op_riprel
[MAX_OPERANDS
- 1 - i
] = riprel
;
12193 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12194 op_txt
[MAX_OPERANDS
- 1 - i
] = op_out
[i
];
12198 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12202 (*info
->fprintf_func
) (info
->stream
, ",");
12203 if (op_index
[i
] != -1 && !op_riprel
[i
])
12205 bfd_vma target
= (bfd_vma
) op_address
[op_index
[i
]];
12207 if (the_info
&& op_is_jump
)
12209 the_info
->insn_info_valid
= 1;
12210 the_info
->branch_delay_insns
= 0;
12211 the_info
->data_size
= 0;
12212 the_info
->target
= target
;
12213 the_info
->target2
= 0;
12215 (*info
->print_address_func
) (target
, info
);
12218 (*info
->fprintf_func
) (info
->stream
, "%s", op_txt
[i
]);
12222 for (i
= 0; i
< MAX_OPERANDS
; i
++)
12223 if (op_index
[i
] != -1 && op_riprel
[i
])
12225 (*info
->fprintf_func
) (info
->stream
, " # ");
12226 (*info
->print_address_func
) ((bfd_vma
) (start_pc
+ (codep
- start_codep
)
12227 + op_address
[op_index
[i
]]), info
);
12230 return codep
- priv
.the_buffer
;
12233 static const char *float_mem
[] = {
12308 static const unsigned char float_mem_mode
[] = {
12383 #define ST { OP_ST, 0 }
12384 #define STi { OP_STi, 0 }
12386 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
12387 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
12388 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
12389 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
12390 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
12391 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
12392 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
12393 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
12394 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
12396 static const struct dis386 float_reg
[][8] = {
12399 { "fadd", { ST
, STi
}, 0 },
12400 { "fmul", { ST
, STi
}, 0 },
12401 { "fcom", { STi
}, 0 },
12402 { "fcomp", { STi
}, 0 },
12403 { "fsub", { ST
, STi
}, 0 },
12404 { "fsubr", { ST
, STi
}, 0 },
12405 { "fdiv", { ST
, STi
}, 0 },
12406 { "fdivr", { ST
, STi
}, 0 },
12410 { "fld", { STi
}, 0 },
12411 { "fxch", { STi
}, 0 },
12421 { "fcmovb", { ST
, STi
}, 0 },
12422 { "fcmove", { ST
, STi
}, 0 },
12423 { "fcmovbe",{ ST
, STi
}, 0 },
12424 { "fcmovu", { ST
, STi
}, 0 },
12432 { "fcmovnb",{ ST
, STi
}, 0 },
12433 { "fcmovne",{ ST
, STi
}, 0 },
12434 { "fcmovnbe",{ ST
, STi
}, 0 },
12435 { "fcmovnu",{ ST
, STi
}, 0 },
12437 { "fucomi", { ST
, STi
}, 0 },
12438 { "fcomi", { ST
, STi
}, 0 },
12443 { "fadd", { STi
, ST
}, 0 },
12444 { "fmul", { STi
, ST
}, 0 },
12447 { "fsub{!M|r}", { STi
, ST
}, 0 },
12448 { "fsub{M|}", { STi
, ST
}, 0 },
12449 { "fdiv{!M|r}", { STi
, ST
}, 0 },
12450 { "fdiv{M|}", { STi
, ST
}, 0 },
12454 { "ffree", { STi
}, 0 },
12456 { "fst", { STi
}, 0 },
12457 { "fstp", { STi
}, 0 },
12458 { "fucom", { STi
}, 0 },
12459 { "fucomp", { STi
}, 0 },
12465 { "faddp", { STi
, ST
}, 0 },
12466 { "fmulp", { STi
, ST
}, 0 },
12469 { "fsub{!M|r}p", { STi
, ST
}, 0 },
12470 { "fsub{M|}p", { STi
, ST
}, 0 },
12471 { "fdiv{!M|r}p", { STi
, ST
}, 0 },
12472 { "fdiv{M|}p", { STi
, ST
}, 0 },
12476 { "ffreep", { STi
}, 0 },
12481 { "fucomip", { ST
, STi
}, 0 },
12482 { "fcomip", { ST
, STi
}, 0 },
12487 static char *fgrps
[][8] = {
12490 "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12495 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12500 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
12505 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
12510 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
12515 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
12520 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12525 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
12526 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
12531 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12536 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12541 swap_operand (void)
12543 mnemonicendp
[0] = '.';
12544 mnemonicendp
[1] = 's';
12549 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED
,
12550 int sizeflag ATTRIBUTE_UNUSED
)
12552 /* Skip mod/rm byte. */
12558 dofloat (int sizeflag
)
12560 const struct dis386
*dp
;
12561 unsigned char floatop
;
12563 floatop
= codep
[-1];
12565 if (modrm
.mod
!= 3)
12567 int fp_indx
= (floatop
- 0xd8) * 8 + modrm
.reg
;
12569 putop (float_mem
[fp_indx
], sizeflag
);
12572 OP_E (float_mem_mode
[fp_indx
], sizeflag
);
12575 /* Skip mod/rm byte. */
12579 dp
= &float_reg
[floatop
- 0xd8][modrm
.reg
];
12580 if (dp
->name
== NULL
)
12582 putop (fgrps
[dp
->op
[0].bytemode
][modrm
.rm
], sizeflag
);
12584 /* Instruction fnstsw is only one with strange arg. */
12585 if (floatop
== 0xdf && codep
[-1] == 0xe0)
12586 strcpy (op_out
[0], names16
[0]);
12590 putop (dp
->name
, sizeflag
);
12595 (*dp
->op
[0].rtn
) (dp
->op
[0].bytemode
, sizeflag
);
12600 (*dp
->op
[1].rtn
) (dp
->op
[1].bytemode
, sizeflag
);
12604 /* Like oappend (below), but S is a string starting with '%'.
12605 In Intel syntax, the '%' is elided. */
12607 oappend_maybe_intel (const char *s
)
12609 oappend (s
+ intel_syntax
);
12613 OP_ST (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12615 oappend_maybe_intel ("%st");
12619 OP_STi (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12621 sprintf (scratchbuf
, "%%st(%d)", modrm
.rm
);
12622 oappend_maybe_intel (scratchbuf
);
12625 /* Capital letters in template are macros. */
12627 putop (const char *in_template
, int sizeflag
)
12632 unsigned int l
= 0, len
= 1;
12635 #define SAVE_LAST(c) \
12636 if (l < len && l < sizeof (last)) \
12641 for (p
= in_template
; *p
; p
++)
12657 while (*++p
!= '|')
12658 if (*p
== '}' || *p
== '\0')
12664 while (*++p
!= '}')
12676 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
12680 if (l
== 0 && len
== 1)
12685 if (sizeflag
& SUFFIX_ALWAYS
)
12698 if (address_mode
== mode_64bit
12699 && !(prefixes
& PREFIX_ADDR
))
12710 if (intel_syntax
&& !alt
)
12712 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
12714 if (sizeflag
& DFLAG
)
12715 *obufp
++ = intel_syntax
? 'd' : 'l';
12717 *obufp
++ = intel_syntax
? 'w' : 's';
12718 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12722 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
12725 if (modrm
.mod
== 3)
12731 if (sizeflag
& DFLAG
)
12732 *obufp
++ = intel_syntax
? 'd' : 'l';
12735 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12741 case 'E': /* For jcxz/jecxz */
12742 if (address_mode
== mode_64bit
)
12744 if (sizeflag
& AFLAG
)
12750 if (sizeflag
& AFLAG
)
12752 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
12757 if ((prefixes
& PREFIX_ADDR
) || (sizeflag
& SUFFIX_ALWAYS
))
12759 if (sizeflag
& AFLAG
)
12760 *obufp
++ = address_mode
== mode_64bit
? 'q' : 'l';
12762 *obufp
++ = address_mode
== mode_64bit
? 'l' : 'w';
12763 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
12767 if (intel_syntax
|| (obufp
[-1] != 's' && !(sizeflag
& SUFFIX_ALWAYS
)))
12769 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
12773 if (!(rex
& REX_W
))
12774 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12779 if ((prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_CS
12780 || (prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_DS
)
12782 used_prefixes
|= prefixes
& (PREFIX_CS
| PREFIX_DS
);
12785 if (prefixes
& PREFIX_DS
)
12799 if (l
!= 0 || len
!= 1)
12801 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
12806 if (!need_vex
|| !vex
.evex
)
12809 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
12811 switch (vex
.length
)
12829 if (address_mode
== mode_64bit
&& (sizeflag
& SUFFIX_ALWAYS
))
12834 /* Fall through. */
12837 if (l
!= 0 || len
!= 1)
12845 if (sizeflag
& SUFFIX_ALWAYS
)
12849 if (intel_mnemonic
!= cond
)
12853 if ((prefixes
& PREFIX_FWAIT
) == 0)
12856 used_prefixes
|= PREFIX_FWAIT
;
12862 else if (intel_syntax
&& (sizeflag
& DFLAG
))
12866 if (!(rex
& REX_W
))
12867 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12871 && address_mode
== mode_64bit
12872 && isa64
== intel64
)
12877 /* Fall through. */
12880 && address_mode
== mode_64bit
12881 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
12886 /* Fall through. */
12889 if (l
== 0 && len
== 1)
12894 if ((rex
& REX_W
) == 0
12895 && (prefixes
& PREFIX_DATA
))
12897 if ((sizeflag
& DFLAG
) == 0)
12899 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12903 if ((prefixes
& PREFIX_DATA
)
12905 || (sizeflag
& SUFFIX_ALWAYS
))
12912 if (sizeflag
& DFLAG
)
12916 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12922 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
12928 if ((prefixes
& PREFIX_DATA
)
12930 || (sizeflag
& SUFFIX_ALWAYS
))
12937 if (sizeflag
& DFLAG
)
12938 *obufp
++ = intel_syntax
? 'd' : 'l';
12941 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12949 if (address_mode
== mode_64bit
12950 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
12952 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
12956 /* Fall through. */
12959 if (l
== 0 && len
== 1)
12962 if (intel_syntax
&& !alt
)
12965 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
12971 if (sizeflag
& DFLAG
)
12972 *obufp
++ = intel_syntax
? 'd' : 'l';
12975 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12981 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
12986 if ((intel_syntax
&& need_modrm
)
12987 || (modrm
.mod
== 3 && !(sizeflag
& SUFFIX_ALWAYS
)))
12994 else if((address_mode
== mode_64bit
&& need_modrm
)
12995 || (sizeflag
& SUFFIX_ALWAYS
))
12996 *obufp
++ = intel_syntax
? 'd' : 'l';
13003 else if (sizeflag
& DFLAG
)
13012 if (intel_syntax
&& !p
[1]
13013 && ((rex
& REX_W
) || (sizeflag
& DFLAG
)))
13015 if (!(rex
& REX_W
))
13016 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13019 if (l
== 0 && len
== 1)
13023 if (address_mode
== mode_64bit
13024 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13026 if (sizeflag
& SUFFIX_ALWAYS
)
13048 /* Fall through. */
13051 if (l
== 0 && len
== 1)
13056 if (sizeflag
& SUFFIX_ALWAYS
)
13062 if (sizeflag
& DFLAG
)
13066 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13080 if (address_mode
== mode_64bit
13081 && !(prefixes
& PREFIX_ADDR
))
13092 if (l
!= 0 || len
!= 1)
13098 ? vex
.prefix
== DATA_PREFIX_OPCODE
13099 : prefixes
& PREFIX_DATA
)
13102 used_prefixes
|= PREFIX_DATA
;
13108 if (l
== 0 && len
== 1)
13112 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
13120 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
13122 switch (vex
.length
)
13138 if (l
== 0 && len
== 1)
13140 /* operand size flag for cwtl, cbtw */
13149 else if (sizeflag
& DFLAG
)
13153 if (!(rex
& REX_W
))
13154 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13161 && last
[0] != 'L'))
13168 if (last
[0] == 'X')
13169 *obufp
++ = vex
.w
? 'd': 's';
13171 *obufp
++ = vex
.w
? 'q': 'd';
13177 if (isa64
== intel64
&& (rex
& REX_W
))
13183 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
13185 if (sizeflag
& DFLAG
)
13189 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13195 if (address_mode
== mode_64bit
13196 && (isa64
== intel64
13197 || ((sizeflag
& DFLAG
) || (rex
& REX_W
))))
13199 else if ((prefixes
& PREFIX_DATA
))
13201 if (!(sizeflag
& DFLAG
))
13203 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13209 mnemonicendp
= obufp
;
13214 oappend (const char *s
)
13216 obufp
= stpcpy (obufp
, s
);
13222 /* Only print the active segment register. */
13223 if (!active_seg_prefix
)
13226 used_prefixes
|= active_seg_prefix
;
13227 switch (active_seg_prefix
)
13230 oappend_maybe_intel ("%cs:");
13233 oappend_maybe_intel ("%ds:");
13236 oappend_maybe_intel ("%ss:");
13239 oappend_maybe_intel ("%es:");
13242 oappend_maybe_intel ("%fs:");
13245 oappend_maybe_intel ("%gs:");
13253 OP_indirE (int bytemode
, int sizeflag
)
13257 OP_E (bytemode
, sizeflag
);
13261 print_operand_value (char *buf
, int hex
, bfd_vma disp
)
13263 if (address_mode
== mode_64bit
)
13271 sprintf_vma (tmp
, disp
);
13272 for (i
= 0; tmp
[i
] == '0' && tmp
[i
+ 1]; i
++);
13273 strcpy (buf
+ 2, tmp
+ i
);
13277 bfd_signed_vma v
= disp
;
13284 /* Check for possible overflow on 0x8000000000000000. */
13287 strcpy (buf
, "9223372036854775808");
13301 tmp
[28 - i
] = (v
% 10) + '0';
13305 strcpy (buf
, tmp
+ 29 - i
);
13311 sprintf (buf
, "0x%x", (unsigned int) disp
);
13313 sprintf (buf
, "%d", (int) disp
);
13317 /* Put DISP in BUF as signed hex number. */
13320 print_displacement (char *buf
, bfd_vma disp
)
13322 bfd_signed_vma val
= disp
;
13331 /* Check for possible overflow. */
13334 switch (address_mode
)
13337 strcpy (buf
+ j
, "0x8000000000000000");
13340 strcpy (buf
+ j
, "0x80000000");
13343 strcpy (buf
+ j
, "0x8000");
13353 sprintf_vma (tmp
, (bfd_vma
) val
);
13354 for (i
= 0; tmp
[i
] == '0'; i
++)
13356 if (tmp
[i
] == '\0')
13358 strcpy (buf
+ j
, tmp
+ i
);
13362 intel_operand_size (int bytemode
, int sizeflag
)
13366 && (bytemode
== x_mode
13367 || bytemode
== evex_half_bcst_xmmq_mode
))
13370 oappend ("QWORD PTR ");
13372 oappend ("DWORD PTR ");
13381 oappend ("BYTE PTR ");
13386 oappend ("WORD PTR ");
13389 if (address_mode
== mode_64bit
&& isa64
== intel64
)
13391 oappend ("QWORD PTR ");
13394 /* Fall through. */
13396 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13398 oappend ("QWORD PTR ");
13401 /* Fall through. */
13407 oappend ("QWORD PTR ");
13410 if ((sizeflag
& DFLAG
) || bytemode
== dq_mode
)
13411 oappend ("DWORD PTR ");
13413 oappend ("WORD PTR ");
13414 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13418 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
13420 oappend ("WORD PTR ");
13421 if (!(rex
& REX_W
))
13422 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13425 if (sizeflag
& DFLAG
)
13426 oappend ("QWORD PTR ");
13428 oappend ("DWORD PTR ");
13429 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13432 if (!(sizeflag
& DFLAG
) && isa64
== intel64
)
13433 oappend ("WORD PTR ");
13435 oappend ("DWORD PTR ");
13436 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13439 case d_scalar_swap_mode
:
13442 oappend ("DWORD PTR ");
13445 case q_scalar_swap_mode
:
13447 oappend ("QWORD PTR ");
13450 if (address_mode
== mode_64bit
)
13451 oappend ("QWORD PTR ");
13453 oappend ("DWORD PTR ");
13456 if (sizeflag
& DFLAG
)
13457 oappend ("FWORD PTR ");
13459 oappend ("DWORD PTR ");
13460 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13463 oappend ("TBYTE PTR ");
13467 case evex_x_gscat_mode
:
13468 case evex_x_nobcst_mode
:
13469 case b_scalar_mode
:
13470 case w_scalar_mode
:
13473 switch (vex
.length
)
13476 oappend ("XMMWORD PTR ");
13479 oappend ("YMMWORD PTR ");
13482 oappend ("ZMMWORD PTR ");
13489 oappend ("XMMWORD PTR ");
13492 oappend ("XMMWORD PTR ");
13495 oappend ("YMMWORD PTR ");
13498 case evex_half_bcst_xmmq_mode
:
13502 switch (vex
.length
)
13505 oappend ("QWORD PTR ");
13508 oappend ("XMMWORD PTR ");
13511 oappend ("YMMWORD PTR ");
13521 switch (vex
.length
)
13526 oappend ("BYTE PTR ");
13536 switch (vex
.length
)
13541 oappend ("WORD PTR ");
13551 switch (vex
.length
)
13556 oappend ("DWORD PTR ");
13566 switch (vex
.length
)
13571 oappend ("QWORD PTR ");
13581 switch (vex
.length
)
13584 oappend ("WORD PTR ");
13587 oappend ("DWORD PTR ");
13590 oappend ("QWORD PTR ");
13600 switch (vex
.length
)
13603 oappend ("DWORD PTR ");
13606 oappend ("QWORD PTR ");
13609 oappend ("XMMWORD PTR ");
13619 switch (vex
.length
)
13622 oappend ("QWORD PTR ");
13625 oappend ("YMMWORD PTR ");
13628 oappend ("ZMMWORD PTR ");
13638 switch (vex
.length
)
13642 oappend ("XMMWORD PTR ");
13649 oappend ("OWORD PTR ");
13651 case vex_scalar_w_dq_mode
:
13656 oappend ("QWORD PTR ");
13658 oappend ("DWORD PTR ");
13660 case vex_vsib_d_w_dq_mode
:
13661 case vex_vsib_q_w_dq_mode
:
13668 oappend ("QWORD PTR ");
13670 oappend ("DWORD PTR ");
13674 switch (vex
.length
)
13677 oappend ("XMMWORD PTR ");
13680 oappend ("YMMWORD PTR ");
13683 oappend ("ZMMWORD PTR ");
13690 case vex_vsib_q_w_d_mode
:
13691 case vex_vsib_d_w_d_mode
:
13692 if (!need_vex
|| !vex
.evex
)
13695 switch (vex
.length
)
13698 oappend ("QWORD PTR ");
13701 oappend ("XMMWORD PTR ");
13704 oappend ("YMMWORD PTR ");
13712 if (!need_vex
|| vex
.length
!= 128)
13715 oappend ("DWORD PTR ");
13717 oappend ("BYTE PTR ");
13723 oappend ("QWORD PTR ");
13725 oappend ("WORD PTR ");
13735 OP_E_register (int bytemode
, int sizeflag
)
13737 int reg
= modrm
.rm
;
13738 const char **names
;
13744 if ((sizeflag
& SUFFIX_ALWAYS
)
13745 && (bytemode
== b_swap_mode
13746 || bytemode
== bnd_swap_mode
13747 || bytemode
== v_swap_mode
))
13773 names
= address_mode
== mode_64bit
? names64
: names32
;
13776 case bnd_swap_mode
:
13785 if (address_mode
== mode_64bit
&& isa64
== intel64
)
13790 /* Fall through. */
13792 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13798 /* Fall through. */
13810 if ((sizeflag
& DFLAG
)
13811 || (bytemode
!= v_mode
13812 && bytemode
!= v_swap_mode
))
13816 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13820 if (!(sizeflag
& DFLAG
) && isa64
== intel64
)
13824 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13827 names
= (address_mode
== mode_64bit
13828 ? names64
: names32
);
13829 if (!(prefixes
& PREFIX_ADDR
))
13830 names
= (address_mode
== mode_16bit
13831 ? names16
: names
);
13834 /* Remove "addr16/addr32". */
13835 all_prefixes
[last_addr_prefix
] = 0;
13836 names
= (address_mode
!= mode_32bit
13837 ? names32
: names16
);
13838 used_prefixes
|= PREFIX_ADDR
;
13848 names
= names_mask
;
13853 oappend (INTERNAL_DISASSEMBLER_ERROR
);
13856 oappend (names
[reg
]);
13860 OP_E_memory (int bytemode
, int sizeflag
)
13863 int add
= (rex
& REX_B
) ? 8 : 0;
13869 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
13871 && bytemode
!= x_mode
13872 && bytemode
!= xmmq_mode
13873 && bytemode
!= evex_half_bcst_xmmq_mode
)
13889 if (address_mode
!= mode_64bit
)
13895 case vex_scalar_w_dq_mode
:
13896 case vex_vsib_d_w_dq_mode
:
13897 case vex_vsib_d_w_d_mode
:
13898 case vex_vsib_q_w_dq_mode
:
13899 case vex_vsib_q_w_d_mode
:
13900 case evex_x_gscat_mode
:
13901 shift
= vex
.w
? 3 : 2;
13904 case evex_half_bcst_xmmq_mode
:
13908 shift
= vex
.w
? 3 : 2;
13911 /* Fall through. */
13915 case evex_x_nobcst_mode
:
13917 switch (vex
.length
)
13941 case q_scalar_swap_mode
:
13948 case d_scalar_swap_mode
:
13951 case w_scalar_mode
:
13955 case b_scalar_mode
:
13962 /* Make necessary corrections to shift for modes that need it.
13963 For these modes we currently have shift 4, 5 or 6 depending on
13964 vex.length (it corresponds to xmmword, ymmword or zmmword
13965 operand). We might want to make it 3, 4 or 5 (e.g. for
13966 xmmq_mode). In case of broadcast enabled the corrections
13967 aren't needed, as element size is always 32 or 64 bits. */
13969 && (bytemode
== xmmq_mode
13970 || bytemode
== evex_half_bcst_xmmq_mode
))
13972 else if (bytemode
== xmmqd_mode
)
13974 else if (bytemode
== xmmdw_mode
)
13976 else if (bytemode
== ymmq_mode
&& vex
.length
== 128)
13984 intel_operand_size (bytemode
, sizeflag
);
13987 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
13989 /* 32/64 bit address mode */
13999 int addr32flag
= !((sizeflag
& AFLAG
)
14000 || bytemode
== v_bnd_mode
14001 || bytemode
== v_bndmk_mode
14002 || bytemode
== bnd_mode
14003 || bytemode
== bnd_swap_mode
);
14004 const char **indexes64
= names64
;
14005 const char **indexes32
= names32
;
14015 vindex
= sib
.index
;
14021 case vex_vsib_d_w_dq_mode
:
14022 case vex_vsib_d_w_d_mode
:
14023 case vex_vsib_q_w_dq_mode
:
14024 case vex_vsib_q_w_d_mode
:
14034 switch (vex
.length
)
14037 indexes64
= indexes32
= names_xmm
;
14041 || bytemode
== vex_vsib_q_w_dq_mode
14042 || bytemode
== vex_vsib_q_w_d_mode
)
14043 indexes64
= indexes32
= names_ymm
;
14045 indexes64
= indexes32
= names_xmm
;
14049 || bytemode
== vex_vsib_q_w_dq_mode
14050 || bytemode
== vex_vsib_q_w_d_mode
)
14051 indexes64
= indexes32
= names_zmm
;
14053 indexes64
= indexes32
= names_ymm
;
14060 haveindex
= vindex
!= 4;
14067 rbase
= base
+ add
;
14075 if (address_mode
== mode_64bit
&& !havesib
)
14078 if (riprel
&& bytemode
== v_bndmk_mode
)
14086 FETCH_DATA (the_info
, codep
+ 1);
14088 if ((disp
& 0x80) != 0)
14090 if (vex
.evex
&& shift
> 0)
14103 && address_mode
!= mode_16bit
)
14105 if (address_mode
== mode_64bit
)
14107 /* Display eiz instead of addr32. */
14108 needindex
= addr32flag
;
14113 /* In 32-bit mode, we need index register to tell [offset]
14114 from [eiz*1 + offset]. */
14119 havedisp
= (havebase
14121 || (havesib
&& (haveindex
|| scale
!= 0)));
14124 if (modrm
.mod
!= 0 || base
== 5)
14126 if (havedisp
|| riprel
)
14127 print_displacement (scratchbuf
, disp
);
14129 print_operand_value (scratchbuf
, 1, disp
);
14130 oappend (scratchbuf
);
14134 oappend (!addr32flag
? "(%rip)" : "(%eip)");
14138 if ((havebase
|| haveindex
|| needindex
|| needaddr32
|| riprel
)
14139 && (address_mode
!= mode_64bit
14140 || ((bytemode
!= v_bnd_mode
)
14141 && (bytemode
!= v_bndmk_mode
)
14142 && (bytemode
!= bnd_mode
)
14143 && (bytemode
!= bnd_swap_mode
))))
14144 used_prefixes
|= PREFIX_ADDR
;
14146 if (havedisp
|| (intel_syntax
&& riprel
))
14148 *obufp
++ = open_char
;
14149 if (intel_syntax
&& riprel
)
14152 oappend (!addr32flag
? "rip" : "eip");
14156 oappend (address_mode
== mode_64bit
&& !addr32flag
14157 ? names64
[rbase
] : names32
[rbase
]);
14160 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
14161 print index to tell base + index from base. */
14165 || (havebase
&& base
!= ESP_REG_NUM
))
14167 if (!intel_syntax
|| havebase
)
14169 *obufp
++ = separator_char
;
14173 oappend (address_mode
== mode_64bit
&& !addr32flag
14174 ? indexes64
[vindex
] : indexes32
[vindex
]);
14176 oappend (address_mode
== mode_64bit
&& !addr32flag
14177 ? index64
: index32
);
14179 *obufp
++ = scale_char
;
14181 sprintf (scratchbuf
, "%d", 1 << scale
);
14182 oappend (scratchbuf
);
14186 && (disp
|| modrm
.mod
!= 0 || base
== 5))
14188 if (!havedisp
|| (bfd_signed_vma
) disp
>= 0)
14193 else if (modrm
.mod
!= 1 && disp
!= -disp
)
14197 disp
= - (bfd_signed_vma
) disp
;
14201 print_displacement (scratchbuf
, disp
);
14203 print_operand_value (scratchbuf
, 1, disp
);
14204 oappend (scratchbuf
);
14207 *obufp
++ = close_char
;
14210 else if (intel_syntax
)
14212 if (modrm
.mod
!= 0 || base
== 5)
14214 if (!active_seg_prefix
)
14216 oappend (names_seg
[ds_reg
- es_reg
]);
14219 print_operand_value (scratchbuf
, 1, disp
);
14220 oappend (scratchbuf
);
14224 else if (bytemode
== v_bnd_mode
14225 || bytemode
== v_bndmk_mode
14226 || bytemode
== bnd_mode
14227 || bytemode
== bnd_swap_mode
)
14234 /* 16 bit address mode */
14235 used_prefixes
|= prefixes
& PREFIX_ADDR
;
14242 if ((disp
& 0x8000) != 0)
14247 FETCH_DATA (the_info
, codep
+ 1);
14249 if ((disp
& 0x80) != 0)
14251 if (vex
.evex
&& shift
> 0)
14256 if ((disp
& 0x8000) != 0)
14262 if (modrm
.mod
!= 0 || modrm
.rm
== 6)
14264 print_displacement (scratchbuf
, disp
);
14265 oappend (scratchbuf
);
14268 if (modrm
.mod
!= 0 || modrm
.rm
!= 6)
14270 *obufp
++ = open_char
;
14272 oappend (index16
[modrm
.rm
]);
14274 && (disp
|| modrm
.mod
!= 0 || modrm
.rm
== 6))
14276 if ((bfd_signed_vma
) disp
>= 0)
14281 else if (modrm
.mod
!= 1)
14285 disp
= - (bfd_signed_vma
) disp
;
14288 print_displacement (scratchbuf
, disp
);
14289 oappend (scratchbuf
);
14292 *obufp
++ = close_char
;
14295 else if (intel_syntax
)
14297 if (!active_seg_prefix
)
14299 oappend (names_seg
[ds_reg
- es_reg
]);
14302 print_operand_value (scratchbuf
, 1, disp
& 0xffff);
14303 oappend (scratchbuf
);
14306 if (vex
.evex
&& vex
.b
14307 && (bytemode
== x_mode
14308 || bytemode
== xmmq_mode
14309 || bytemode
== evex_half_bcst_xmmq_mode
))
14312 || bytemode
== xmmq_mode
14313 || bytemode
== evex_half_bcst_xmmq_mode
)
14315 switch (vex
.length
)
14318 oappend ("{1to2}");
14321 oappend ("{1to4}");
14324 oappend ("{1to8}");
14332 switch (vex
.length
)
14335 oappend ("{1to4}");
14338 oappend ("{1to8}");
14341 oappend ("{1to16}");
14351 OP_E (int bytemode
, int sizeflag
)
14353 /* Skip mod/rm byte. */
14357 if (modrm
.mod
== 3)
14358 OP_E_register (bytemode
, sizeflag
);
14360 OP_E_memory (bytemode
, sizeflag
);
14364 OP_G (int bytemode
, int sizeflag
)
14367 const char **names
;
14376 oappend (names8rex
[modrm
.reg
+ add
]);
14378 oappend (names8
[modrm
.reg
+ add
]);
14381 oappend (names16
[modrm
.reg
+ add
]);
14386 oappend (names32
[modrm
.reg
+ add
]);
14389 oappend (names64
[modrm
.reg
+ add
]);
14392 if (modrm
.reg
> 0x3)
14397 oappend (names_bnd
[modrm
.reg
]);
14407 oappend (names64
[modrm
.reg
+ add
]);
14410 if ((sizeflag
& DFLAG
)
14411 || (bytemode
!= v_mode
&& bytemode
!= movsxd_mode
))
14412 oappend (names32
[modrm
.reg
+ add
]);
14414 oappend (names16
[modrm
.reg
+ add
]);
14415 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14419 names
= (address_mode
== mode_64bit
14420 ? names64
: names32
);
14421 if (!(prefixes
& PREFIX_ADDR
))
14423 if (address_mode
== mode_16bit
)
14428 /* Remove "addr16/addr32". */
14429 all_prefixes
[last_addr_prefix
] = 0;
14430 names
= (address_mode
!= mode_32bit
14431 ? names32
: names16
);
14432 used_prefixes
|= PREFIX_ADDR
;
14434 oappend (names
[modrm
.reg
+ add
]);
14437 if (address_mode
== mode_64bit
)
14438 oappend (names64
[modrm
.reg
+ add
]);
14440 oappend (names32
[modrm
.reg
+ add
]);
14444 if ((modrm
.reg
+ add
) > 0x7)
14449 oappend (names_mask
[modrm
.reg
+ add
]);
14452 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14465 FETCH_DATA (the_info
, codep
+ 8);
14466 a
= *codep
++ & 0xff;
14467 a
|= (*codep
++ & 0xff) << 8;
14468 a
|= (*codep
++ & 0xff) << 16;
14469 a
|= (*codep
++ & 0xffu
) << 24;
14470 b
= *codep
++ & 0xff;
14471 b
|= (*codep
++ & 0xff) << 8;
14472 b
|= (*codep
++ & 0xff) << 16;
14473 b
|= (*codep
++ & 0xffu
) << 24;
14474 x
= a
+ ((bfd_vma
) b
<< 32);
14482 static bfd_signed_vma
14485 bfd_signed_vma x
= 0;
14487 FETCH_DATA (the_info
, codep
+ 4);
14488 x
= *codep
++ & (bfd_signed_vma
) 0xff;
14489 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
14490 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
14491 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
14495 static bfd_signed_vma
14498 bfd_signed_vma x
= 0;
14500 FETCH_DATA (the_info
, codep
+ 4);
14501 x
= *codep
++ & (bfd_signed_vma
) 0xff;
14502 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
14503 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
14504 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
14506 x
= (x
^ ((bfd_signed_vma
) 1 << 31)) - ((bfd_signed_vma
) 1 << 31);
14516 FETCH_DATA (the_info
, codep
+ 2);
14517 x
= *codep
++ & 0xff;
14518 x
|= (*codep
++ & 0xff) << 8;
14523 set_op (bfd_vma op
, int riprel
)
14525 op_index
[op_ad
] = op_ad
;
14526 if (address_mode
== mode_64bit
)
14528 op_address
[op_ad
] = op
;
14529 op_riprel
[op_ad
] = riprel
;
14533 /* Mask to get a 32-bit address. */
14534 op_address
[op_ad
] = op
& 0xffffffff;
14535 op_riprel
[op_ad
] = riprel
& 0xffffffff;
14540 OP_REG (int code
, int sizeflag
)
14547 case es_reg
: case ss_reg
: case cs_reg
:
14548 case ds_reg
: case fs_reg
: case gs_reg
:
14549 oappend (names_seg
[code
- es_reg
]);
14561 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
14562 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
14563 s
= names16
[code
- ax_reg
+ add
];
14565 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
14566 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
14569 s
= names8rex
[code
- al_reg
+ add
];
14571 s
= names8
[code
- al_reg
];
14573 case rAX_reg
: case rCX_reg
: case rDX_reg
: case rBX_reg
:
14574 case rSP_reg
: case rBP_reg
: case rSI_reg
: case rDI_reg
:
14575 if (address_mode
== mode_64bit
14576 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14578 s
= names64
[code
- rAX_reg
+ add
];
14581 code
+= eAX_reg
- rAX_reg
;
14582 /* Fall through. */
14583 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
14584 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
14587 s
= names64
[code
- eAX_reg
+ add
];
14590 if (sizeflag
& DFLAG
)
14591 s
= names32
[code
- eAX_reg
+ add
];
14593 s
= names16
[code
- eAX_reg
+ add
];
14594 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14598 s
= INTERNAL_DISASSEMBLER_ERROR
;
14605 OP_IMREG (int code
, int sizeflag
)
14617 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
14618 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
14619 s
= names16
[code
- ax_reg
];
14621 case es_reg
: case ss_reg
: case cs_reg
:
14622 case ds_reg
: case fs_reg
: case gs_reg
:
14623 s
= names_seg
[code
- es_reg
];
14625 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
14626 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
14629 s
= names8rex
[code
- al_reg
];
14631 s
= names8
[code
- al_reg
];
14633 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
14634 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
14637 s
= names64
[code
- eAX_reg
];
14640 if (sizeflag
& DFLAG
)
14641 s
= names32
[code
- eAX_reg
];
14643 s
= names16
[code
- eAX_reg
];
14644 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14647 case z_mode_ax_reg
:
14648 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
14652 if (!(rex
& REX_W
))
14653 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14656 s
= INTERNAL_DISASSEMBLER_ERROR
;
14663 OP_I (int bytemode
, int sizeflag
)
14666 bfd_signed_vma mask
= -1;
14671 FETCH_DATA (the_info
, codep
+ 1);
14681 if (sizeflag
& DFLAG
)
14691 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14707 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14712 scratchbuf
[0] = '$';
14713 print_operand_value (scratchbuf
+ 1, 1, op
);
14714 oappend_maybe_intel (scratchbuf
);
14715 scratchbuf
[0] = '\0';
14719 OP_I64 (int bytemode
, int sizeflag
)
14721 if (bytemode
!= v_mode
|| address_mode
!= mode_64bit
|| !(rex
& REX_W
))
14723 OP_I (bytemode
, sizeflag
);
14729 scratchbuf
[0] = '$';
14730 print_operand_value (scratchbuf
+ 1, 1, get64 ());
14731 oappend_maybe_intel (scratchbuf
);
14732 scratchbuf
[0] = '\0';
14736 OP_sI (int bytemode
, int sizeflag
)
14744 FETCH_DATA (the_info
, codep
+ 1);
14746 if ((op
& 0x80) != 0)
14748 if (bytemode
== b_T_mode
)
14750 if (address_mode
!= mode_64bit
14751 || !((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14753 /* The operand-size prefix is overridden by a REX prefix. */
14754 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
14762 if (!(rex
& REX_W
))
14764 if (sizeflag
& DFLAG
)
14772 /* The operand-size prefix is overridden by a REX prefix. */
14773 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
14779 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14783 scratchbuf
[0] = '$';
14784 print_operand_value (scratchbuf
+ 1, 1, op
);
14785 oappend_maybe_intel (scratchbuf
);
14789 OP_J (int bytemode
, int sizeflag
)
14793 bfd_vma segment
= 0;
14798 FETCH_DATA (the_info
, codep
+ 1);
14800 if ((disp
& 0x80) != 0)
14804 if (isa64
!= intel64
)
14807 if ((sizeflag
& DFLAG
)
14808 || (address_mode
== mode_64bit
14809 && ((isa64
== intel64
&& bytemode
!= dqw_mode
)
14810 || (rex
& REX_W
))))
14815 if ((disp
& 0x8000) != 0)
14817 /* In 16bit mode, address is wrapped around at 64k within
14818 the same segment. Otherwise, a data16 prefix on a jump
14819 instruction means that the pc is masked to 16 bits after
14820 the displacement is added! */
14822 if ((prefixes
& PREFIX_DATA
) == 0)
14823 segment
= ((start_pc
+ (codep
- start_codep
))
14824 & ~((bfd_vma
) 0xffff));
14826 if (address_mode
!= mode_64bit
14827 || (isa64
!= intel64
&& !(rex
& REX_W
)))
14828 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14831 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14834 disp
= ((start_pc
+ (codep
- start_codep
) + disp
) & mask
) | segment
;
14836 print_operand_value (scratchbuf
, 1, disp
);
14837 oappend (scratchbuf
);
14841 OP_SEG (int bytemode
, int sizeflag
)
14843 if (bytemode
== w_mode
)
14844 oappend (names_seg
[modrm
.reg
]);
14846 OP_E (modrm
.mod
== 3 ? bytemode
: w_mode
, sizeflag
);
14850 OP_DIR (int dummy ATTRIBUTE_UNUSED
, int sizeflag
)
14854 if (sizeflag
& DFLAG
)
14864 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14866 sprintf (scratchbuf
, "0x%x:0x%x", seg
, offset
);
14868 sprintf (scratchbuf
, "$0x%x,$0x%x", seg
, offset
);
14869 oappend (scratchbuf
);
14873 OP_OFF (int bytemode
, int sizeflag
)
14877 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
14878 intel_operand_size (bytemode
, sizeflag
);
14881 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
14888 if (!active_seg_prefix
)
14890 oappend (names_seg
[ds_reg
- es_reg
]);
14894 print_operand_value (scratchbuf
, 1, off
);
14895 oappend (scratchbuf
);
14899 OP_OFF64 (int bytemode
, int sizeflag
)
14903 if (address_mode
!= mode_64bit
14904 || (prefixes
& PREFIX_ADDR
))
14906 OP_OFF (bytemode
, sizeflag
);
14910 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
14911 intel_operand_size (bytemode
, sizeflag
);
14918 if (!active_seg_prefix
)
14920 oappend (names_seg
[ds_reg
- es_reg
]);
14924 print_operand_value (scratchbuf
, 1, off
);
14925 oappend (scratchbuf
);
14929 ptr_reg (int code
, int sizeflag
)
14933 *obufp
++ = open_char
;
14934 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
14935 if (address_mode
== mode_64bit
)
14937 if (!(sizeflag
& AFLAG
))
14938 s
= names32
[code
- eAX_reg
];
14940 s
= names64
[code
- eAX_reg
];
14942 else if (sizeflag
& AFLAG
)
14943 s
= names32
[code
- eAX_reg
];
14945 s
= names16
[code
- eAX_reg
];
14947 *obufp
++ = close_char
;
14952 OP_ESreg (int code
, int sizeflag
)
14958 case 0x6d: /* insw/insl */
14959 intel_operand_size (z_mode
, sizeflag
);
14961 case 0xa5: /* movsw/movsl/movsq */
14962 case 0xa7: /* cmpsw/cmpsl/cmpsq */
14963 case 0xab: /* stosw/stosl */
14964 case 0xaf: /* scasw/scasl */
14965 intel_operand_size (v_mode
, sizeflag
);
14968 intel_operand_size (b_mode
, sizeflag
);
14971 oappend_maybe_intel ("%es:");
14972 ptr_reg (code
, sizeflag
);
14976 OP_DSreg (int code
, int sizeflag
)
14982 case 0x6f: /* outsw/outsl */
14983 intel_operand_size (z_mode
, sizeflag
);
14985 case 0xa5: /* movsw/movsl/movsq */
14986 case 0xa7: /* cmpsw/cmpsl/cmpsq */
14987 case 0xad: /* lodsw/lodsl/lodsq */
14988 intel_operand_size (v_mode
, sizeflag
);
14991 intel_operand_size (b_mode
, sizeflag
);
14994 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
14995 default segment register DS is printed. */
14996 if (!active_seg_prefix
)
14997 active_seg_prefix
= PREFIX_DS
;
14999 ptr_reg (code
, sizeflag
);
15003 OP_C (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15011 else if (address_mode
!= mode_64bit
&& (prefixes
& PREFIX_LOCK
))
15013 all_prefixes
[last_lock_prefix
] = 0;
15014 used_prefixes
|= PREFIX_LOCK
;
15019 sprintf (scratchbuf
, "%%cr%d", modrm
.reg
+ add
);
15020 oappend_maybe_intel (scratchbuf
);
15024 OP_D (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15033 sprintf (scratchbuf
, "db%d", modrm
.reg
+ add
);
15035 sprintf (scratchbuf
, "%%db%d", modrm
.reg
+ add
);
15036 oappend (scratchbuf
);
15040 OP_T (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15042 sprintf (scratchbuf
, "%%tr%d", modrm
.reg
);
15043 oappend_maybe_intel (scratchbuf
);
15047 OP_R (int bytemode
, int sizeflag
)
15049 /* Skip mod/rm byte. */
15052 OP_E_register (bytemode
, sizeflag
);
15056 OP_MMX (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15058 int reg
= modrm
.reg
;
15059 const char **names
;
15061 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15062 if (prefixes
& PREFIX_DATA
)
15071 oappend (names
[reg
]);
15075 OP_XMM (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
15077 int reg
= modrm
.reg
;
15078 const char **names
;
15090 && bytemode
!= xmm_mode
15091 && bytemode
!= xmmq_mode
15092 && bytemode
!= evex_half_bcst_xmmq_mode
15093 && bytemode
!= ymm_mode
15094 && bytemode
!= scalar_mode
)
15096 switch (vex
.length
)
15103 || (bytemode
!= vex_vsib_q_w_dq_mode
15104 && bytemode
!= vex_vsib_q_w_d_mode
))
15116 else if (bytemode
== xmmq_mode
15117 || bytemode
== evex_half_bcst_xmmq_mode
)
15119 switch (vex
.length
)
15132 else if (bytemode
== ymm_mode
)
15136 oappend (names
[reg
]);
15140 OP_EM (int bytemode
, int sizeflag
)
15143 const char **names
;
15145 if (modrm
.mod
!= 3)
15148 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
15150 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
15151 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15153 OP_E (bytemode
, sizeflag
);
15157 if ((sizeflag
& SUFFIX_ALWAYS
) && bytemode
== v_swap_mode
)
15160 /* Skip mod/rm byte. */
15163 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15165 if (prefixes
& PREFIX_DATA
)
15174 oappend (names
[reg
]);
15177 /* cvt* are the only instructions in sse2 which have
15178 both SSE and MMX operands and also have 0x66 prefix
15179 in their opcode. 0x66 was originally used to differentiate
15180 between SSE and MMX instruction(operands). So we have to handle the
15181 cvt* separately using OP_EMC and OP_MXC */
15183 OP_EMC (int bytemode
, int sizeflag
)
15185 if (modrm
.mod
!= 3)
15187 if (intel_syntax
&& bytemode
== v_mode
)
15189 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
15190 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15192 OP_E (bytemode
, sizeflag
);
15196 /* Skip mod/rm byte. */
15199 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15200 oappend (names_mm
[modrm
.rm
]);
15204 OP_MXC (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15206 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15207 oappend (names_mm
[modrm
.reg
]);
15211 OP_EX (int bytemode
, int sizeflag
)
15214 const char **names
;
15216 /* Skip mod/rm byte. */
15220 if (modrm
.mod
!= 3)
15222 OP_E_memory (bytemode
, sizeflag
);
15237 if ((sizeflag
& SUFFIX_ALWAYS
)
15238 && (bytemode
== x_swap_mode
15239 || bytemode
== d_swap_mode
15240 || bytemode
== d_scalar_swap_mode
15241 || bytemode
== q_swap_mode
15242 || bytemode
== q_scalar_swap_mode
))
15246 && bytemode
!= xmm_mode
15247 && bytemode
!= xmmdw_mode
15248 && bytemode
!= xmmqd_mode
15249 && bytemode
!= xmm_mb_mode
15250 && bytemode
!= xmm_mw_mode
15251 && bytemode
!= xmm_md_mode
15252 && bytemode
!= xmm_mq_mode
15253 && bytemode
!= xmmq_mode
15254 && bytemode
!= evex_half_bcst_xmmq_mode
15255 && bytemode
!= ymm_mode
15256 && bytemode
!= d_scalar_swap_mode
15257 && bytemode
!= q_scalar_swap_mode
15258 && bytemode
!= vex_scalar_w_dq_mode
)
15260 switch (vex
.length
)
15275 else if (bytemode
== xmmq_mode
15276 || bytemode
== evex_half_bcst_xmmq_mode
)
15278 switch (vex
.length
)
15291 else if (bytemode
== ymm_mode
)
15295 oappend (names
[reg
]);
15299 OP_MS (int bytemode
, int sizeflag
)
15301 if (modrm
.mod
== 3)
15302 OP_EM (bytemode
, sizeflag
);
15308 OP_XS (int bytemode
, int sizeflag
)
15310 if (modrm
.mod
== 3)
15311 OP_EX (bytemode
, sizeflag
);
15317 OP_M (int bytemode
, int sizeflag
)
15319 if (modrm
.mod
== 3)
15320 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15323 OP_E (bytemode
, sizeflag
);
15327 OP_0f07 (int bytemode
, int sizeflag
)
15329 if (modrm
.mod
!= 3 || modrm
.rm
!= 0)
15332 OP_E (bytemode
, sizeflag
);
15335 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15336 32bit mode and "xchg %rax,%rax" in 64bit mode. */
15339 NOP_Fixup1 (int bytemode
, int sizeflag
)
15341 if ((prefixes
& PREFIX_DATA
) != 0
15344 && address_mode
== mode_64bit
))
15345 OP_REG (bytemode
, sizeflag
);
15347 strcpy (obuf
, "nop");
15351 NOP_Fixup2 (int bytemode
, int sizeflag
)
15353 if ((prefixes
& PREFIX_DATA
) != 0
15356 && address_mode
== mode_64bit
))
15357 OP_IMREG (bytemode
, sizeflag
);
15360 static const char *const Suffix3DNow
[] = {
15361 /* 00 */ NULL
, NULL
, NULL
, NULL
,
15362 /* 04 */ NULL
, NULL
, NULL
, NULL
,
15363 /* 08 */ NULL
, NULL
, NULL
, NULL
,
15364 /* 0C */ "pi2fw", "pi2fd", NULL
, NULL
,
15365 /* 10 */ NULL
, NULL
, NULL
, NULL
,
15366 /* 14 */ NULL
, NULL
, NULL
, NULL
,
15367 /* 18 */ NULL
, NULL
, NULL
, NULL
,
15368 /* 1C */ "pf2iw", "pf2id", NULL
, NULL
,
15369 /* 20 */ NULL
, NULL
, NULL
, NULL
,
15370 /* 24 */ NULL
, NULL
, NULL
, NULL
,
15371 /* 28 */ NULL
, NULL
, NULL
, NULL
,
15372 /* 2C */ NULL
, NULL
, NULL
, NULL
,
15373 /* 30 */ NULL
, NULL
, NULL
, NULL
,
15374 /* 34 */ NULL
, NULL
, NULL
, NULL
,
15375 /* 38 */ NULL
, NULL
, NULL
, NULL
,
15376 /* 3C */ NULL
, NULL
, NULL
, NULL
,
15377 /* 40 */ NULL
, NULL
, NULL
, NULL
,
15378 /* 44 */ NULL
, NULL
, NULL
, NULL
,
15379 /* 48 */ NULL
, NULL
, NULL
, NULL
,
15380 /* 4C */ NULL
, NULL
, NULL
, NULL
,
15381 /* 50 */ NULL
, NULL
, NULL
, NULL
,
15382 /* 54 */ NULL
, NULL
, NULL
, NULL
,
15383 /* 58 */ NULL
, NULL
, NULL
, NULL
,
15384 /* 5C */ NULL
, NULL
, NULL
, NULL
,
15385 /* 60 */ NULL
, NULL
, NULL
, NULL
,
15386 /* 64 */ NULL
, NULL
, NULL
, NULL
,
15387 /* 68 */ NULL
, NULL
, NULL
, NULL
,
15388 /* 6C */ NULL
, NULL
, NULL
, NULL
,
15389 /* 70 */ NULL
, NULL
, NULL
, NULL
,
15390 /* 74 */ NULL
, NULL
, NULL
, NULL
,
15391 /* 78 */ NULL
, NULL
, NULL
, NULL
,
15392 /* 7C */ NULL
, NULL
, NULL
, NULL
,
15393 /* 80 */ NULL
, NULL
, NULL
, NULL
,
15394 /* 84 */ NULL
, NULL
, NULL
, NULL
,
15395 /* 88 */ NULL
, NULL
, "pfnacc", NULL
,
15396 /* 8C */ NULL
, NULL
, "pfpnacc", NULL
,
15397 /* 90 */ "pfcmpge", NULL
, NULL
, NULL
,
15398 /* 94 */ "pfmin", NULL
, "pfrcp", "pfrsqrt",
15399 /* 98 */ NULL
, NULL
, "pfsub", NULL
,
15400 /* 9C */ NULL
, NULL
, "pfadd", NULL
,
15401 /* A0 */ "pfcmpgt", NULL
, NULL
, NULL
,
15402 /* A4 */ "pfmax", NULL
, "pfrcpit1", "pfrsqit1",
15403 /* A8 */ NULL
, NULL
, "pfsubr", NULL
,
15404 /* AC */ NULL
, NULL
, "pfacc", NULL
,
15405 /* B0 */ "pfcmpeq", NULL
, NULL
, NULL
,
15406 /* B4 */ "pfmul", NULL
, "pfrcpit2", "pmulhrw",
15407 /* B8 */ NULL
, NULL
, NULL
, "pswapd",
15408 /* BC */ NULL
, NULL
, NULL
, "pavgusb",
15409 /* C0 */ NULL
, NULL
, NULL
, NULL
,
15410 /* C4 */ NULL
, NULL
, NULL
, NULL
,
15411 /* C8 */ NULL
, NULL
, NULL
, NULL
,
15412 /* CC */ NULL
, NULL
, NULL
, NULL
,
15413 /* D0 */ NULL
, NULL
, NULL
, NULL
,
15414 /* D4 */ NULL
, NULL
, NULL
, NULL
,
15415 /* D8 */ NULL
, NULL
, NULL
, NULL
,
15416 /* DC */ NULL
, NULL
, NULL
, NULL
,
15417 /* E0 */ NULL
, NULL
, NULL
, NULL
,
15418 /* E4 */ NULL
, NULL
, NULL
, NULL
,
15419 /* E8 */ NULL
, NULL
, NULL
, NULL
,
15420 /* EC */ NULL
, NULL
, NULL
, NULL
,
15421 /* F0 */ NULL
, NULL
, NULL
, NULL
,
15422 /* F4 */ NULL
, NULL
, NULL
, NULL
,
15423 /* F8 */ NULL
, NULL
, NULL
, NULL
,
15424 /* FC */ NULL
, NULL
, NULL
, NULL
,
15428 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15430 const char *mnemonic
;
15432 FETCH_DATA (the_info
, codep
+ 1);
15433 /* AMD 3DNow! instructions are specified by an opcode suffix in the
15434 place where an 8-bit immediate would normally go. ie. the last
15435 byte of the instruction. */
15436 obufp
= mnemonicendp
;
15437 mnemonic
= Suffix3DNow
[*codep
++ & 0xff];
15439 oappend (mnemonic
);
15442 /* Since a variable sized modrm/sib chunk is between the start
15443 of the opcode (0x0f0f) and the opcode suffix, we need to do
15444 all the modrm processing first, and don't know until now that
15445 we have a bad opcode. This necessitates some cleaning up. */
15446 op_out
[0][0] = '\0';
15447 op_out
[1][0] = '\0';
15450 mnemonicendp
= obufp
;
15453 static struct op simd_cmp_op
[] =
15455 { STRING_COMMA_LEN ("eq") },
15456 { STRING_COMMA_LEN ("lt") },
15457 { STRING_COMMA_LEN ("le") },
15458 { STRING_COMMA_LEN ("unord") },
15459 { STRING_COMMA_LEN ("neq") },
15460 { STRING_COMMA_LEN ("nlt") },
15461 { STRING_COMMA_LEN ("nle") },
15462 { STRING_COMMA_LEN ("ord") }
15466 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15468 unsigned int cmp_type
;
15470 FETCH_DATA (the_info
, codep
+ 1);
15471 cmp_type
= *codep
++ & 0xff;
15472 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
))
15475 char *p
= mnemonicendp
- 2;
15479 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
15480 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
15484 /* We have a reserved extension byte. Output it directly. */
15485 scratchbuf
[0] = '$';
15486 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
15487 oappend_maybe_intel (scratchbuf
);
15488 scratchbuf
[0] = '\0';
15493 OP_Mwait (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
15495 /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx */
15498 strcpy (op_out
[0], names32
[0]);
15499 strcpy (op_out
[1], names32
[1]);
15500 if (bytemode
== eBX_reg
)
15501 strcpy (op_out
[2], names32
[3]);
15502 two_source_ops
= 1;
15504 /* Skip mod/rm byte. */
15510 OP_Monitor (int bytemode ATTRIBUTE_UNUSED
,
15511 int sizeflag ATTRIBUTE_UNUSED
)
15513 /* monitor %{e,r,}ax,%ecx,%edx" */
15516 const char **names
= (address_mode
== mode_64bit
15517 ? names64
: names32
);
15519 if (prefixes
& PREFIX_ADDR
)
15521 /* Remove "addr16/addr32". */
15522 all_prefixes
[last_addr_prefix
] = 0;
15523 names
= (address_mode
!= mode_32bit
15524 ? names32
: names16
);
15525 used_prefixes
|= PREFIX_ADDR
;
15527 else if (address_mode
== mode_16bit
)
15529 strcpy (op_out
[0], names
[0]);
15530 strcpy (op_out
[1], names32
[1]);
15531 strcpy (op_out
[2], names32
[2]);
15532 two_source_ops
= 1;
15534 /* Skip mod/rm byte. */
15542 /* Throw away prefixes and 1st. opcode byte. */
15543 codep
= insn_codep
+ 1;
15548 REP_Fixup (int bytemode
, int sizeflag
)
15550 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15552 if (prefixes
& PREFIX_REPZ
)
15553 all_prefixes
[last_repz_prefix
] = REP_PREFIX
;
15560 OP_IMREG (bytemode
, sizeflag
);
15563 OP_ESreg (bytemode
, sizeflag
);
15566 OP_DSreg (bytemode
, sizeflag
);
15575 SEP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15577 if ( isa64
!= amd64
)
15582 mnemonicendp
= obufp
;
15586 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15590 BND_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15592 if (prefixes
& PREFIX_REPNZ
)
15593 all_prefixes
[last_repnz_prefix
] = BND_PREFIX
;
15596 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
15600 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED
,
15601 int sizeflag ATTRIBUTE_UNUSED
)
15603 if (active_seg_prefix
== PREFIX_DS
15604 && (address_mode
!= mode_64bit
|| last_data_prefix
< 0))
15606 /* NOTRACK prefix is only valid on indirect branch instructions.
15607 NB: DATA prefix is unsupported for Intel64. */
15608 active_seg_prefix
= 0;
15609 all_prefixes
[last_seg_prefix
] = NOTRACK_PREFIX
;
15613 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
15614 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15618 HLE_Fixup1 (int bytemode
, int sizeflag
)
15621 && (prefixes
& PREFIX_LOCK
) != 0)
15623 if (prefixes
& PREFIX_REPZ
)
15624 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15625 if (prefixes
& PREFIX_REPNZ
)
15626 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
15629 OP_E (bytemode
, sizeflag
);
15632 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
15633 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
15637 HLE_Fixup2 (int bytemode
, int sizeflag
)
15639 if (modrm
.mod
!= 3)
15641 if (prefixes
& PREFIX_REPZ
)
15642 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15643 if (prefixes
& PREFIX_REPNZ
)
15644 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
15647 OP_E (bytemode
, sizeflag
);
15650 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
15651 "xrelease" for memory operand. No check for LOCK prefix. */
15654 HLE_Fixup3 (int bytemode
, int sizeflag
)
15657 && last_repz_prefix
> last_repnz_prefix
15658 && (prefixes
& PREFIX_REPZ
) != 0)
15659 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15661 OP_E (bytemode
, sizeflag
);
15665 CMPXCHG8B_Fixup (int bytemode
, int sizeflag
)
15670 /* Change cmpxchg8b to cmpxchg16b. */
15671 char *p
= mnemonicendp
- 2;
15672 mnemonicendp
= stpcpy (p
, "16b");
15675 else if ((prefixes
& PREFIX_LOCK
) != 0)
15677 if (prefixes
& PREFIX_REPZ
)
15678 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15679 if (prefixes
& PREFIX_REPNZ
)
15680 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
15683 OP_M (bytemode
, sizeflag
);
15687 XMM_Fixup (int reg
, int sizeflag ATTRIBUTE_UNUSED
)
15689 const char **names
;
15693 switch (vex
.length
)
15707 oappend (names
[reg
]);
15711 CRC32_Fixup (int bytemode
, int sizeflag
)
15713 /* Add proper suffix to "crc32". */
15714 char *p
= mnemonicendp
;
15733 if (sizeflag
& DFLAG
)
15737 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15741 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15748 if (modrm
.mod
== 3)
15752 /* Skip mod/rm byte. */
15757 add
= (rex
& REX_B
) ? 8 : 0;
15758 if (bytemode
== b_mode
)
15762 oappend (names8rex
[modrm
.rm
+ add
]);
15764 oappend (names8
[modrm
.rm
+ add
]);
15770 oappend (names64
[modrm
.rm
+ add
]);
15771 else if ((prefixes
& PREFIX_DATA
))
15772 oappend (names16
[modrm
.rm
+ add
]);
15774 oappend (names32
[modrm
.rm
+ add
]);
15778 OP_E (bytemode
, sizeflag
);
15782 FXSAVE_Fixup (int bytemode
, int sizeflag
)
15784 /* Add proper suffix to "fxsave" and "fxrstor". */
15788 char *p
= mnemonicendp
;
15794 OP_M (bytemode
, sizeflag
);
15798 PCMPESTR_Fixup (int bytemode
, int sizeflag
)
15800 /* Add proper suffix to "{,v}pcmpestr{i,m}". */
15803 char *p
= mnemonicendp
;
15808 else if (sizeflag
& SUFFIX_ALWAYS
)
15815 OP_EX (bytemode
, sizeflag
);
15818 /* Display the destination register operand for instructions with
15822 OP_VEX (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
15825 const char **names
;
15833 reg
= vex
.register_specifier
;
15834 vex
.register_specifier
= 0;
15835 if (address_mode
!= mode_64bit
)
15837 else if (vex
.evex
&& !vex
.v
)
15840 if (bytemode
== vex_scalar_mode
)
15842 oappend (names_xmm
[reg
]);
15846 switch (vex
.length
)
15853 case vex_vsib_q_w_dq_mode
:
15854 case vex_vsib_q_w_d_mode
:
15870 names
= names_mask
;
15884 case vex_vsib_q_w_dq_mode
:
15885 case vex_vsib_q_w_d_mode
:
15886 names
= vex
.w
? names_ymm
: names_xmm
;
15895 names
= names_mask
;
15898 /* See PR binutils/20893 for a reproducer. */
15910 oappend (names
[reg
]);
15913 /* Get the VEX immediate byte without moving codep. */
15915 static unsigned char
15916 get_vex_imm8 (int sizeflag
, int opnum
)
15918 int bytes_before_imm
= 0;
15920 if (modrm
.mod
!= 3)
15922 /* There are SIB/displacement bytes. */
15923 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
15925 /* 32/64 bit address mode */
15926 int base
= modrm
.rm
;
15928 /* Check SIB byte. */
15931 FETCH_DATA (the_info
, codep
+ 1);
15933 /* When decoding the third source, don't increase
15934 bytes_before_imm as this has already been incremented
15935 by one in OP_E_memory while decoding the second
15938 bytes_before_imm
++;
15941 /* Don't increase bytes_before_imm when decoding the third source,
15942 it has already been incremented by OP_E_memory while decoding
15943 the second source operand. */
15949 /* When modrm.rm == 5 or modrm.rm == 4 and base in
15950 SIB == 5, there is a 4 byte displacement. */
15952 /* No displacement. */
15954 /* Fall through. */
15956 /* 4 byte displacement. */
15957 bytes_before_imm
+= 4;
15960 /* 1 byte displacement. */
15961 bytes_before_imm
++;
15968 /* 16 bit address mode */
15969 /* Don't increase bytes_before_imm when decoding the third source,
15970 it has already been incremented by OP_E_memory while decoding
15971 the second source operand. */
15977 /* When modrm.rm == 6, there is a 2 byte displacement. */
15979 /* No displacement. */
15981 /* Fall through. */
15983 /* 2 byte displacement. */
15984 bytes_before_imm
+= 2;
15987 /* 1 byte displacement: when decoding the third source,
15988 don't increase bytes_before_imm as this has already
15989 been incremented by one in OP_E_memory while decoding
15990 the second source operand. */
15992 bytes_before_imm
++;
16000 FETCH_DATA (the_info
, codep
+ bytes_before_imm
+ 1);
16001 return codep
[bytes_before_imm
];
16005 OP_EX_VexReg (int bytemode
, int sizeflag
, int reg
)
16007 const char **names
;
16009 if (reg
== -1 && modrm
.mod
!= 3)
16011 OP_E_memory (bytemode
, sizeflag
);
16023 if (address_mode
!= mode_64bit
)
16027 switch (vex
.length
)
16038 oappend (names
[reg
]);
16042 OP_EX_VexImmW (int bytemode
, int sizeflag
)
16045 static unsigned char vex_imm8
;
16047 if (vex_w_done
== 0)
16051 /* Skip mod/rm byte. */
16055 vex_imm8
= get_vex_imm8 (sizeflag
, 0);
16058 reg
= vex_imm8
>> 4;
16060 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16062 else if (vex_w_done
== 1)
16067 reg
= vex_imm8
>> 4;
16069 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16073 /* Output the imm8 directly. */
16074 scratchbuf
[0] = '$';
16075 print_operand_value (scratchbuf
+ 1, 1, vex_imm8
& 0xf);
16076 oappend_maybe_intel (scratchbuf
);
16077 scratchbuf
[0] = '\0';
16083 OP_Vex_2src (int bytemode
, int sizeflag
)
16085 if (modrm
.mod
== 3)
16087 int reg
= modrm
.rm
;
16091 oappend (names_xmm
[reg
]);
16096 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
16098 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
16099 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16101 OP_E (bytemode
, sizeflag
);
16106 OP_Vex_2src_1 (int bytemode
, int sizeflag
)
16108 if (modrm
.mod
== 3)
16110 /* Skip mod/rm byte. */
16117 unsigned int reg
= vex
.register_specifier
;
16118 vex
.register_specifier
= 0;
16120 if (address_mode
!= mode_64bit
)
16122 oappend (names_xmm
[reg
]);
16125 OP_Vex_2src (bytemode
, sizeflag
);
16129 OP_Vex_2src_2 (int bytemode
, int sizeflag
)
16132 OP_Vex_2src (bytemode
, sizeflag
);
16135 unsigned int reg
= vex
.register_specifier
;
16136 vex
.register_specifier
= 0;
16138 if (address_mode
!= mode_64bit
)
16140 oappend (names_xmm
[reg
]);
16145 OP_EX_VexW (int bytemode
, int sizeflag
)
16151 /* Skip mod/rm byte. */
16156 reg
= get_vex_imm8 (sizeflag
, 0) >> 4;
16161 reg
= get_vex_imm8 (sizeflag
, 1) >> 4;
16164 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16172 OP_REG_VexI4 (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16175 const char **names
;
16177 FETCH_DATA (the_info
, codep
+ 1);
16180 if (bytemode
!= x_mode
)
16184 if (address_mode
!= mode_64bit
)
16187 switch (vex
.length
)
16198 oappend (names
[reg
]);
16202 OP_XMM_VexW (int bytemode
, int sizeflag
)
16204 /* Turn off the REX.W bit since it is used for swapping operands
16207 OP_XMM (bytemode
, sizeflag
);
16211 OP_EX_Vex (int bytemode
, int sizeflag
)
16213 if (modrm
.mod
!= 3)
16215 OP_EX (bytemode
, sizeflag
);
16219 OP_XMM_Vex (int bytemode
, int sizeflag
)
16221 if (modrm
.mod
!= 3)
16223 OP_XMM (bytemode
, sizeflag
);
16226 static struct op vex_cmp_op
[] =
16228 { STRING_COMMA_LEN ("eq") },
16229 { STRING_COMMA_LEN ("lt") },
16230 { STRING_COMMA_LEN ("le") },
16231 { STRING_COMMA_LEN ("unord") },
16232 { STRING_COMMA_LEN ("neq") },
16233 { STRING_COMMA_LEN ("nlt") },
16234 { STRING_COMMA_LEN ("nle") },
16235 { STRING_COMMA_LEN ("ord") },
16236 { STRING_COMMA_LEN ("eq_uq") },
16237 { STRING_COMMA_LEN ("nge") },
16238 { STRING_COMMA_LEN ("ngt") },
16239 { STRING_COMMA_LEN ("false") },
16240 { STRING_COMMA_LEN ("neq_oq") },
16241 { STRING_COMMA_LEN ("ge") },
16242 { STRING_COMMA_LEN ("gt") },
16243 { STRING_COMMA_LEN ("true") },
16244 { STRING_COMMA_LEN ("eq_os") },
16245 { STRING_COMMA_LEN ("lt_oq") },
16246 { STRING_COMMA_LEN ("le_oq") },
16247 { STRING_COMMA_LEN ("unord_s") },
16248 { STRING_COMMA_LEN ("neq_us") },
16249 { STRING_COMMA_LEN ("nlt_uq") },
16250 { STRING_COMMA_LEN ("nle_uq") },
16251 { STRING_COMMA_LEN ("ord_s") },
16252 { STRING_COMMA_LEN ("eq_us") },
16253 { STRING_COMMA_LEN ("nge_uq") },
16254 { STRING_COMMA_LEN ("ngt_uq") },
16255 { STRING_COMMA_LEN ("false_os") },
16256 { STRING_COMMA_LEN ("neq_os") },
16257 { STRING_COMMA_LEN ("ge_oq") },
16258 { STRING_COMMA_LEN ("gt_oq") },
16259 { STRING_COMMA_LEN ("true_us") },
16263 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16265 unsigned int cmp_type
;
16267 FETCH_DATA (the_info
, codep
+ 1);
16268 cmp_type
= *codep
++ & 0xff;
16269 if (cmp_type
< ARRAY_SIZE (vex_cmp_op
))
16272 char *p
= mnemonicendp
- 2;
16276 sprintf (p
, "%s%s", vex_cmp_op
[cmp_type
].name
, suffix
);
16277 mnemonicendp
+= vex_cmp_op
[cmp_type
].len
;
16281 /* We have a reserved extension byte. Output it directly. */
16282 scratchbuf
[0] = '$';
16283 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16284 oappend_maybe_intel (scratchbuf
);
16285 scratchbuf
[0] = '\0';
16290 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16291 int sizeflag ATTRIBUTE_UNUSED
)
16293 unsigned int cmp_type
;
16298 FETCH_DATA (the_info
, codep
+ 1);
16299 cmp_type
= *codep
++ & 0xff;
16300 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16301 If it's the case, print suffix, otherwise - print the immediate. */
16302 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
)
16307 char *p
= mnemonicendp
- 2;
16309 /* vpcmp* can have both one- and two-lettered suffix. */
16323 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
16324 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
16328 /* We have a reserved extension byte. Output it directly. */
16329 scratchbuf
[0] = '$';
16330 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16331 oappend_maybe_intel (scratchbuf
);
16332 scratchbuf
[0] = '\0';
16336 static const struct op xop_cmp_op
[] =
16338 { STRING_COMMA_LEN ("lt") },
16339 { STRING_COMMA_LEN ("le") },
16340 { STRING_COMMA_LEN ("gt") },
16341 { STRING_COMMA_LEN ("ge") },
16342 { STRING_COMMA_LEN ("eq") },
16343 { STRING_COMMA_LEN ("neq") },
16344 { STRING_COMMA_LEN ("false") },
16345 { STRING_COMMA_LEN ("true") }
16349 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16350 int sizeflag ATTRIBUTE_UNUSED
)
16352 unsigned int cmp_type
;
16354 FETCH_DATA (the_info
, codep
+ 1);
16355 cmp_type
= *codep
++ & 0xff;
16356 if (cmp_type
< ARRAY_SIZE (xop_cmp_op
))
16359 char *p
= mnemonicendp
- 2;
16361 /* vpcom* can have both one- and two-lettered suffix. */
16375 sprintf (p
, "%s%s", xop_cmp_op
[cmp_type
].name
, suffix
);
16376 mnemonicendp
+= xop_cmp_op
[cmp_type
].len
;
16380 /* We have a reserved extension byte. Output it directly. */
16381 scratchbuf
[0] = '$';
16382 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16383 oappend_maybe_intel (scratchbuf
);
16384 scratchbuf
[0] = '\0';
16388 static const struct op pclmul_op
[] =
16390 { STRING_COMMA_LEN ("lql") },
16391 { STRING_COMMA_LEN ("hql") },
16392 { STRING_COMMA_LEN ("lqh") },
16393 { STRING_COMMA_LEN ("hqh") }
16397 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16398 int sizeflag ATTRIBUTE_UNUSED
)
16400 unsigned int pclmul_type
;
16402 FETCH_DATA (the_info
, codep
+ 1);
16403 pclmul_type
= *codep
++ & 0xff;
16404 switch (pclmul_type
)
16415 if (pclmul_type
< ARRAY_SIZE (pclmul_op
))
16418 char *p
= mnemonicendp
- 3;
16423 sprintf (p
, "%s%s", pclmul_op
[pclmul_type
].name
, suffix
);
16424 mnemonicendp
+= pclmul_op
[pclmul_type
].len
;
16428 /* We have a reserved extension byte. Output it directly. */
16429 scratchbuf
[0] = '$';
16430 print_operand_value (scratchbuf
+ 1, 1, pclmul_type
);
16431 oappend_maybe_intel (scratchbuf
);
16432 scratchbuf
[0] = '\0';
16437 MOVBE_Fixup (int bytemode
, int sizeflag
)
16439 /* Add proper suffix to "movbe". */
16440 char *p
= mnemonicendp
;
16449 if (sizeflag
& SUFFIX_ALWAYS
)
16455 if (sizeflag
& DFLAG
)
16459 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16464 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16471 OP_M (bytemode
, sizeflag
);
16475 MOVSXD_Fixup (int bytemode
, int sizeflag
)
16477 /* Add proper suffix to "movsxd". */
16478 char *p
= mnemonicendp
;
16503 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16510 OP_E (bytemode
, sizeflag
);
16514 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16517 const char **names
;
16519 /* Skip mod/rm byte. */
16533 oappend (names
[reg
]);
16537 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16539 const char **names
;
16540 unsigned int reg
= vex
.register_specifier
;
16541 vex
.register_specifier
= 0;
16548 if (address_mode
!= mode_64bit
)
16550 oappend (names
[reg
]);
16554 OP_Mask (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16557 || (bytemode
!= mask_mode
&& bytemode
!= mask_bd_mode
))
16561 if ((rex
& REX_R
) != 0 || !vex
.r
)
16567 oappend (names_mask
[modrm
.reg
]);
16571 OP_Rounding (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16573 if (modrm
.mod
== 3 && vex
.b
)
16576 case evex_rounding_64_mode
:
16577 if (address_mode
!= mode_64bit
)
16582 /* Fall through. */
16583 case evex_rounding_mode
:
16584 oappend (names_rounding
[vex
.ll
]);
16586 case evex_sae_mode
: