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[binutils-gdb.git] / opcodes / i386-dis.c
1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2020 Free Software Foundation, Inc.
3
4 This file is part of the GNU opcodes library.
5
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
20
21
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
23 July 1988
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
27
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
34
35 #include "sysdep.h"
36 #include "disassemble.h"
37 #include "opintl.h"
38 #include "opcode/i386.h"
39 #include "libiberty.h"
40 #include "safe-ctype.h"
41
42 #include <setjmp.h>
43
44 static int print_insn (bfd_vma, disassemble_info *);
45 static void dofloat (int);
46 static void OP_ST (int, int);
47 static void OP_STi (int, int);
48 static int putop (const char *, int);
49 static void oappend (const char *);
50 static void append_seg (void);
51 static void OP_indirE (int, int);
52 static void print_operand_value (char *, int, bfd_vma);
53 static void OP_E_register (int, int);
54 static void OP_E_memory (int, int);
55 static void print_displacement (char *, bfd_vma);
56 static void OP_E (int, int);
57 static void OP_G (int, int);
58 static bfd_vma get64 (void);
59 static bfd_signed_vma get32 (void);
60 static bfd_signed_vma get32s (void);
61 static int get16 (void);
62 static void set_op (bfd_vma, int);
63 static void OP_Skip_MODRM (int, int);
64 static void OP_REG (int, int);
65 static void OP_IMREG (int, int);
66 static void OP_I (int, int);
67 static void OP_I64 (int, int);
68 static void OP_sI (int, int);
69 static void OP_J (int, int);
70 static void OP_SEG (int, int);
71 static void OP_DIR (int, int);
72 static void OP_OFF (int, int);
73 static void OP_OFF64 (int, int);
74 static void ptr_reg (int, int);
75 static void OP_ESreg (int, int);
76 static void OP_DSreg (int, int);
77 static void OP_C (int, int);
78 static void OP_D (int, int);
79 static void OP_T (int, int);
80 static void OP_R (int, int);
81 static void OP_MMX (int, int);
82 static void OP_XMM (int, int);
83 static void OP_EM (int, int);
84 static void OP_EX (int, int);
85 static void OP_EMC (int,int);
86 static void OP_MXC (int,int);
87 static void OP_MS (int, int);
88 static void OP_XS (int, int);
89 static void OP_M (int, int);
90 static void OP_VEX (int, int);
91 static void OP_VexR (int, int);
92 static void OP_VexW (int, int);
93 static void OP_Rounding (int, int);
94 static void OP_REG_VexI4 (int, int);
95 static void OP_VexI4 (int, int);
96 static void PCLMUL_Fixup (int, int);
97 static void VPCMP_Fixup (int, int);
98 static void VPCOM_Fixup (int, int);
99 static void OP_0f07 (int, int);
100 static void OP_Monitor (int, int);
101 static void OP_Mwait (int, int);
102 static void NOP_Fixup1 (int, int);
103 static void NOP_Fixup2 (int, int);
104 static void OP_3DNowSuffix (int, int);
105 static void CMP_Fixup (int, int);
106 static void BadOp (void);
107 static void REP_Fixup (int, int);
108 static void SEP_Fixup (int, int);
109 static void BND_Fixup (int, int);
110 static void NOTRACK_Fixup (int, int);
111 static void HLE_Fixup1 (int, int);
112 static void HLE_Fixup2 (int, int);
113 static void HLE_Fixup3 (int, int);
114 static void CMPXCHG8B_Fixup (int, int);
115 static void XMM_Fixup (int, int);
116 static void FXSAVE_Fixup (int, int);
117
118 static void MOVSXD_Fixup (int, int);
119
120 static void OP_Mask (int, int);
121
122 struct dis_private {
123 /* Points to first byte not fetched. */
124 bfd_byte *max_fetched;
125 bfd_byte the_buffer[MAX_MNEM_SIZE];
126 bfd_vma insn_start;
127 int orig_sizeflag;
128 OPCODES_SIGJMP_BUF bailout;
129 };
130
131 enum address_mode
132 {
133 mode_16bit,
134 mode_32bit,
135 mode_64bit
136 };
137
138 enum address_mode address_mode;
139
140 /* Flags for the prefixes for the current instruction. See below. */
141 static int prefixes;
142
143 /* REX prefix the current instruction. See below. */
144 static int rex;
145 /* Bits of REX we've already used. */
146 static int rex_used;
147 /* Mark parts used in the REX prefix. When we are testing for
148 empty prefix (for 8bit register REX extension), just mask it
149 out. Otherwise test for REX bit is excuse for existence of REX
150 only in case value is nonzero. */
151 #define USED_REX(value) \
152 { \
153 if (value) \
154 { \
155 if ((rex & value)) \
156 rex_used |= (value) | REX_OPCODE; \
157 } \
158 else \
159 rex_used |= REX_OPCODE; \
160 }
161
162 /* Flags for prefixes which we somehow handled when printing the
163 current instruction. */
164 static int used_prefixes;
165
166 /* Flags stored in PREFIXES. */
167 #define PREFIX_REPZ 1
168 #define PREFIX_REPNZ 2
169 #define PREFIX_LOCK 4
170 #define PREFIX_CS 8
171 #define PREFIX_SS 0x10
172 #define PREFIX_DS 0x20
173 #define PREFIX_ES 0x40
174 #define PREFIX_FS 0x80
175 #define PREFIX_GS 0x100
176 #define PREFIX_DATA 0x200
177 #define PREFIX_ADDR 0x400
178 #define PREFIX_FWAIT 0x800
179
180 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
181 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
182 on error. */
183 #define FETCH_DATA(info, addr) \
184 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
185 ? 1 : fetch_data ((info), (addr)))
186
187 static int
188 fetch_data (struct disassemble_info *info, bfd_byte *addr)
189 {
190 int status;
191 struct dis_private *priv = (struct dis_private *) info->private_data;
192 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
193
194 if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
195 status = (*info->read_memory_func) (start,
196 priv->max_fetched,
197 addr - priv->max_fetched,
198 info);
199 else
200 status = -1;
201 if (status != 0)
202 {
203 /* If we did manage to read at least one byte, then
204 print_insn_i386 will do something sensible. Otherwise, print
205 an error. We do that here because this is where we know
206 STATUS. */
207 if (priv->max_fetched == priv->the_buffer)
208 (*info->memory_error_func) (status, start, info);
209 OPCODES_SIGLONGJMP (priv->bailout, 1);
210 }
211 else
212 priv->max_fetched = addr;
213 return 1;
214 }
215
216 /* Possible values for prefix requirement. */
217 #define PREFIX_IGNORED_SHIFT 16
218 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
219 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
220 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
221 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
222 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
223
224 /* Opcode prefixes. */
225 #define PREFIX_OPCODE (PREFIX_REPZ \
226 | PREFIX_REPNZ \
227 | PREFIX_DATA)
228
229 /* Prefixes ignored. */
230 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
231 | PREFIX_IGNORED_REPNZ \
232 | PREFIX_IGNORED_DATA)
233
234 #define XX { NULL, 0 }
235 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
236
237 #define Eb { OP_E, b_mode }
238 #define Ebnd { OP_E, bnd_mode }
239 #define EbS { OP_E, b_swap_mode }
240 #define EbndS { OP_E, bnd_swap_mode }
241 #define Ev { OP_E, v_mode }
242 #define Eva { OP_E, va_mode }
243 #define Ev_bnd { OP_E, v_bnd_mode }
244 #define EvS { OP_E, v_swap_mode }
245 #define Ed { OP_E, d_mode }
246 #define Edq { OP_E, dq_mode }
247 #define Edqw { OP_E, dqw_mode }
248 #define Edqb { OP_E, dqb_mode }
249 #define Edb { OP_E, db_mode }
250 #define Edw { OP_E, dw_mode }
251 #define Edqd { OP_E, dqd_mode }
252 #define Eq { OP_E, q_mode }
253 #define indirEv { OP_indirE, indir_v_mode }
254 #define indirEp { OP_indirE, f_mode }
255 #define stackEv { OP_E, stack_v_mode }
256 #define Em { OP_E, m_mode }
257 #define Ew { OP_E, w_mode }
258 #define M { OP_M, 0 } /* lea, lgdt, etc. */
259 #define Ma { OP_M, a_mode }
260 #define Mb { OP_M, b_mode }
261 #define Md { OP_M, d_mode }
262 #define Mo { OP_M, o_mode }
263 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
264 #define Mq { OP_M, q_mode }
265 #define Mv { OP_M, v_mode }
266 #define Mv_bnd { OP_M, v_bndmk_mode }
267 #define Mx { OP_M, x_mode }
268 #define Mxmm { OP_M, xmm_mode }
269 #define Gb { OP_G, b_mode }
270 #define Gbnd { OP_G, bnd_mode }
271 #define Gv { OP_G, v_mode }
272 #define Gd { OP_G, d_mode }
273 #define Gdq { OP_G, dq_mode }
274 #define Gm { OP_G, m_mode }
275 #define Gva { OP_G, va_mode }
276 #define Gw { OP_G, w_mode }
277 #define Rd { OP_R, d_mode }
278 #define Rdq { OP_R, dq_mode }
279 #define Rm { OP_R, m_mode }
280 #define Ib { OP_I, b_mode }
281 #define sIb { OP_sI, b_mode } /* sign extened byte */
282 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
283 #define Iv { OP_I, v_mode }
284 #define sIv { OP_sI, v_mode }
285 #define Iv64 { OP_I64, v_mode }
286 #define Id { OP_I, d_mode }
287 #define Iw { OP_I, w_mode }
288 #define I1 { OP_I, const_1_mode }
289 #define Jb { OP_J, b_mode }
290 #define Jv { OP_J, v_mode }
291 #define Jdqw { OP_J, dqw_mode }
292 #define Cm { OP_C, m_mode }
293 #define Dm { OP_D, m_mode }
294 #define Td { OP_T, d_mode }
295 #define Skip_MODRM { OP_Skip_MODRM, 0 }
296
297 #define RMeAX { OP_REG, eAX_reg }
298 #define RMeBX { OP_REG, eBX_reg }
299 #define RMeCX { OP_REG, eCX_reg }
300 #define RMeDX { OP_REG, eDX_reg }
301 #define RMeSP { OP_REG, eSP_reg }
302 #define RMeBP { OP_REG, eBP_reg }
303 #define RMeSI { OP_REG, eSI_reg }
304 #define RMeDI { OP_REG, eDI_reg }
305 #define RMrAX { OP_REG, rAX_reg }
306 #define RMrBX { OP_REG, rBX_reg }
307 #define RMrCX { OP_REG, rCX_reg }
308 #define RMrDX { OP_REG, rDX_reg }
309 #define RMrSP { OP_REG, rSP_reg }
310 #define RMrBP { OP_REG, rBP_reg }
311 #define RMrSI { OP_REG, rSI_reg }
312 #define RMrDI { OP_REG, rDI_reg }
313 #define RMAL { OP_REG, al_reg }
314 #define RMCL { OP_REG, cl_reg }
315 #define RMDL { OP_REG, dl_reg }
316 #define RMBL { OP_REG, bl_reg }
317 #define RMAH { OP_REG, ah_reg }
318 #define RMCH { OP_REG, ch_reg }
319 #define RMDH { OP_REG, dh_reg }
320 #define RMBH { OP_REG, bh_reg }
321 #define RMAX { OP_REG, ax_reg }
322 #define RMDX { OP_REG, dx_reg }
323
324 #define eAX { OP_IMREG, eAX_reg }
325 #define AL { OP_IMREG, al_reg }
326 #define CL { OP_IMREG, cl_reg }
327 #define zAX { OP_IMREG, z_mode_ax_reg }
328 #define indirDX { OP_IMREG, indir_dx_reg }
329
330 #define Sw { OP_SEG, w_mode }
331 #define Sv { OP_SEG, v_mode }
332 #define Ap { OP_DIR, 0 }
333 #define Ob { OP_OFF64, b_mode }
334 #define Ov { OP_OFF64, v_mode }
335 #define Xb { OP_DSreg, eSI_reg }
336 #define Xv { OP_DSreg, eSI_reg }
337 #define Xz { OP_DSreg, eSI_reg }
338 #define Yb { OP_ESreg, eDI_reg }
339 #define Yv { OP_ESreg, eDI_reg }
340 #define DSBX { OP_DSreg, eBX_reg }
341
342 #define es { OP_REG, es_reg }
343 #define ss { OP_REG, ss_reg }
344 #define cs { OP_REG, cs_reg }
345 #define ds { OP_REG, ds_reg }
346 #define fs { OP_REG, fs_reg }
347 #define gs { OP_REG, gs_reg }
348
349 #define MX { OP_MMX, 0 }
350 #define XM { OP_XMM, 0 }
351 #define XMScalar { OP_XMM, scalar_mode }
352 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
353 #define XMM { OP_XMM, xmm_mode }
354 #define TMM { OP_XMM, tmm_mode }
355 #define XMxmmq { OP_XMM, xmmq_mode }
356 #define EM { OP_EM, v_mode }
357 #define EMS { OP_EM, v_swap_mode }
358 #define EMd { OP_EM, d_mode }
359 #define EMx { OP_EM, x_mode }
360 #define EXbwUnit { OP_EX, bw_unit_mode }
361 #define EXw { OP_EX, w_mode }
362 #define EXd { OP_EX, d_mode }
363 #define EXdS { OP_EX, d_swap_mode }
364 #define EXq { OP_EX, q_mode }
365 #define EXqS { OP_EX, q_swap_mode }
366 #define EXx { OP_EX, x_mode }
367 #define EXxS { OP_EX, x_swap_mode }
368 #define EXxmm { OP_EX, xmm_mode }
369 #define EXymm { OP_EX, ymm_mode }
370 #define EXtmm { OP_EX, tmm_mode }
371 #define EXxmmq { OP_EX, xmmq_mode }
372 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
373 #define EXxmm_mb { OP_EX, xmm_mb_mode }
374 #define EXxmm_mw { OP_EX, xmm_mw_mode }
375 #define EXxmm_md { OP_EX, xmm_md_mode }
376 #define EXxmm_mq { OP_EX, xmm_mq_mode }
377 #define EXxmmdw { OP_EX, xmmdw_mode }
378 #define EXxmmqd { OP_EX, xmmqd_mode }
379 #define EXymmq { OP_EX, ymmq_mode }
380 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
381 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
382 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
383 #define MS { OP_MS, v_mode }
384 #define XS { OP_XS, v_mode }
385 #define EMCq { OP_EMC, q_mode }
386 #define MXC { OP_MXC, 0 }
387 #define OPSUF { OP_3DNowSuffix, 0 }
388 #define SEP { SEP_Fixup, 0 }
389 #define CMP { CMP_Fixup, 0 }
390 #define XMM0 { XMM_Fixup, 0 }
391 #define FXSAVE { FXSAVE_Fixup, 0 }
392
393 #define Vex { OP_VEX, vex_mode }
394 #define VexW { OP_VexW, vex_mode }
395 #define VexScalar { OP_VEX, vex_scalar_mode }
396 #define VexScalarR { OP_VexR, vex_scalar_mode }
397 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
398 #define VexGdq { OP_VEX, dq_mode }
399 #define VexTmm { OP_VEX, tmm_mode }
400 #define XMVexI4 { OP_REG_VexI4, x_mode }
401 #define XMVexScalarI4 { OP_REG_VexI4, scalar_mode }
402 #define VexI4 { OP_VexI4, 0 }
403 #define PCLMUL { PCLMUL_Fixup, 0 }
404 #define VPCMP { VPCMP_Fixup, 0 }
405 #define VPCOM { VPCOM_Fixup, 0 }
406
407 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
408 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
409 #define EXxEVexS { OP_Rounding, evex_sae_mode }
410
411 #define XMask { OP_Mask, mask_mode }
412 #define MaskG { OP_G, mask_mode }
413 #define MaskE { OP_E, mask_mode }
414 #define MaskBDE { OP_E, mask_bd_mode }
415 #define MaskR { OP_R, mask_mode }
416 #define MaskVex { OP_VEX, mask_mode }
417
418 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
419 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
420 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
421 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
422
423 #define MVexSIBMEM { OP_M, vex_sibmem_mode }
424
425 /* Used handle "rep" prefix for string instructions. */
426 #define Xbr { REP_Fixup, eSI_reg }
427 #define Xvr { REP_Fixup, eSI_reg }
428 #define Ybr { REP_Fixup, eDI_reg }
429 #define Yvr { REP_Fixup, eDI_reg }
430 #define Yzr { REP_Fixup, eDI_reg }
431 #define indirDXr { REP_Fixup, indir_dx_reg }
432 #define ALr { REP_Fixup, al_reg }
433 #define eAXr { REP_Fixup, eAX_reg }
434
435 /* Used handle HLE prefix for lockable instructions. */
436 #define Ebh1 { HLE_Fixup1, b_mode }
437 #define Evh1 { HLE_Fixup1, v_mode }
438 #define Ebh2 { HLE_Fixup2, b_mode }
439 #define Evh2 { HLE_Fixup2, v_mode }
440 #define Ebh3 { HLE_Fixup3, b_mode }
441 #define Evh3 { HLE_Fixup3, v_mode }
442
443 #define BND { BND_Fixup, 0 }
444 #define NOTRACK { NOTRACK_Fixup, 0 }
445
446 #define cond_jump_flag { NULL, cond_jump_mode }
447 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
448
449 /* bits in sizeflag */
450 #define SUFFIX_ALWAYS 4
451 #define AFLAG 2
452 #define DFLAG 1
453
454 enum
455 {
456 /* byte operand */
457 b_mode = 1,
458 /* byte operand with operand swapped */
459 b_swap_mode,
460 /* byte operand, sign extend like 'T' suffix */
461 b_T_mode,
462 /* operand size depends on prefixes */
463 v_mode,
464 /* operand size depends on prefixes with operand swapped */
465 v_swap_mode,
466 /* operand size depends on address prefix */
467 va_mode,
468 /* word operand */
469 w_mode,
470 /* double word operand */
471 d_mode,
472 /* double word operand with operand swapped */
473 d_swap_mode,
474 /* quad word operand */
475 q_mode,
476 /* quad word operand with operand swapped */
477 q_swap_mode,
478 /* ten-byte operand */
479 t_mode,
480 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
481 broadcast enabled. */
482 x_mode,
483 /* Similar to x_mode, but with different EVEX mem shifts. */
484 evex_x_gscat_mode,
485 /* Similar to x_mode, but with yet different EVEX mem shifts. */
486 bw_unit_mode,
487 /* Similar to x_mode, but with disabled broadcast. */
488 evex_x_nobcst_mode,
489 /* Similar to x_mode, but with operands swapped and disabled broadcast
490 in EVEX. */
491 x_swap_mode,
492 /* 16-byte XMM operand */
493 xmm_mode,
494 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
495 memory operand (depending on vector length). Broadcast isn't
496 allowed. */
497 xmmq_mode,
498 /* Same as xmmq_mode, but broadcast is allowed. */
499 evex_half_bcst_xmmq_mode,
500 /* XMM register or byte memory operand */
501 xmm_mb_mode,
502 /* XMM register or word memory operand */
503 xmm_mw_mode,
504 /* XMM register or double word memory operand */
505 xmm_md_mode,
506 /* XMM register or quad word memory operand */
507 xmm_mq_mode,
508 /* 16-byte XMM, word, double word or quad word operand. */
509 xmmdw_mode,
510 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
511 xmmqd_mode,
512 /* 32-byte YMM operand */
513 ymm_mode,
514 /* quad word, ymmword or zmmword memory operand. */
515 ymmq_mode,
516 /* 32-byte YMM or 16-byte word operand */
517 ymmxmm_mode,
518 /* TMM operand */
519 tmm_mode,
520 /* d_mode in 32bit, q_mode in 64bit mode. */
521 m_mode,
522 /* pair of v_mode operands */
523 a_mode,
524 cond_jump_mode,
525 loop_jcxz_mode,
526 movsxd_mode,
527 v_bnd_mode,
528 /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */
529 v_bndmk_mode,
530 /* operand size depends on REX prefixes. */
531 dq_mode,
532 /* registers like dq_mode, memory like w_mode, displacements like
533 v_mode without considering Intel64 ISA. */
534 dqw_mode,
535 /* bounds operand */
536 bnd_mode,
537 /* bounds operand with operand swapped */
538 bnd_swap_mode,
539 /* 4- or 6-byte pointer operand */
540 f_mode,
541 const_1_mode,
542 /* v_mode for indirect branch opcodes. */
543 indir_v_mode,
544 /* v_mode for stack-related opcodes. */
545 stack_v_mode,
546 /* non-quad operand size depends on prefixes */
547 z_mode,
548 /* 16-byte operand */
549 o_mode,
550 /* registers like dq_mode, memory like b_mode. */
551 dqb_mode,
552 /* registers like d_mode, memory like b_mode. */
553 db_mode,
554 /* registers like d_mode, memory like w_mode. */
555 dw_mode,
556 /* registers like dq_mode, memory like d_mode. */
557 dqd_mode,
558 /* normal vex mode */
559 vex_mode,
560
561 /* Operand size depends on the VEX.W bit, with VSIB dword indices. */
562 vex_vsib_d_w_dq_mode,
563 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
564 vex_vsib_d_w_d_mode,
565 /* Operand size depends on the VEX.W bit, with VSIB qword indices. */
566 vex_vsib_q_w_dq_mode,
567 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
568 vex_vsib_q_w_d_mode,
569 /* mandatory non-vector SIB. */
570 vex_sibmem_mode,
571
572 /* scalar, ignore vector length. */
573 scalar_mode,
574 /* like vex_mode, ignore vector length. */
575 vex_scalar_mode,
576 /* Operand size depends on the VEX.W bit, ignore vector length. */
577 vex_scalar_w_dq_mode,
578
579 /* Static rounding. */
580 evex_rounding_mode,
581 /* Static rounding, 64-bit mode only. */
582 evex_rounding_64_mode,
583 /* Supress all exceptions. */
584 evex_sae_mode,
585
586 /* Mask register operand. */
587 mask_mode,
588 /* Mask register operand. */
589 mask_bd_mode,
590
591 es_reg,
592 cs_reg,
593 ss_reg,
594 ds_reg,
595 fs_reg,
596 gs_reg,
597
598 eAX_reg,
599 eCX_reg,
600 eDX_reg,
601 eBX_reg,
602 eSP_reg,
603 eBP_reg,
604 eSI_reg,
605 eDI_reg,
606
607 al_reg,
608 cl_reg,
609 dl_reg,
610 bl_reg,
611 ah_reg,
612 ch_reg,
613 dh_reg,
614 bh_reg,
615
616 ax_reg,
617 cx_reg,
618 dx_reg,
619 bx_reg,
620 sp_reg,
621 bp_reg,
622 si_reg,
623 di_reg,
624
625 rAX_reg,
626 rCX_reg,
627 rDX_reg,
628 rBX_reg,
629 rSP_reg,
630 rBP_reg,
631 rSI_reg,
632 rDI_reg,
633
634 z_mode_ax_reg,
635 indir_dx_reg
636 };
637
638 enum
639 {
640 FLOATCODE = 1,
641 USE_REG_TABLE,
642 USE_MOD_TABLE,
643 USE_RM_TABLE,
644 USE_PREFIX_TABLE,
645 USE_X86_64_TABLE,
646 USE_3BYTE_TABLE,
647 USE_XOP_8F_TABLE,
648 USE_VEX_C4_TABLE,
649 USE_VEX_C5_TABLE,
650 USE_VEX_LEN_TABLE,
651 USE_VEX_W_TABLE,
652 USE_EVEX_TABLE,
653 USE_EVEX_LEN_TABLE
654 };
655
656 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
657
658 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
659 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
660 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
661 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
662 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
663 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
664 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
665 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
666 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
667 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
668 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
669 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
670 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
671 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
672 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
673 #define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I))
674
675 enum
676 {
677 REG_80 = 0,
678 REG_81,
679 REG_83,
680 REG_8F,
681 REG_C0,
682 REG_C1,
683 REG_C6,
684 REG_C7,
685 REG_D0,
686 REG_D1,
687 REG_D2,
688 REG_D3,
689 REG_F6,
690 REG_F7,
691 REG_FE,
692 REG_FF,
693 REG_0F00,
694 REG_0F01,
695 REG_0F0D,
696 REG_0F18,
697 REG_0F1C_P_0_MOD_0,
698 REG_0F1E_P_1_MOD_3,
699 REG_0F71,
700 REG_0F72,
701 REG_0F73,
702 REG_0FA6,
703 REG_0FA7,
704 REG_0FAE,
705 REG_0FBA,
706 REG_0FC7,
707 REG_VEX_0F71,
708 REG_VEX_0F72,
709 REG_VEX_0F73,
710 REG_VEX_0FAE,
711 REG_VEX_0F3849_X86_64_P_0_W_0_M_1,
712 REG_VEX_0F38F3,
713
714 REG_0FXOP_09_01_L_0,
715 REG_0FXOP_09_02_L_0,
716 REG_0FXOP_09_12_M_1_L_0,
717 REG_0FXOP_0A_12_L_0,
718
719 REG_EVEX_0F71,
720 REG_EVEX_0F72,
721 REG_EVEX_0F73,
722 REG_EVEX_0F38C6,
723 REG_EVEX_0F38C7
724 };
725
726 enum
727 {
728 MOD_8D = 0,
729 MOD_C6_REG_7,
730 MOD_C7_REG_7,
731 MOD_FF_REG_3,
732 MOD_FF_REG_5,
733 MOD_0F01_REG_0,
734 MOD_0F01_REG_1,
735 MOD_0F01_REG_2,
736 MOD_0F01_REG_3,
737 MOD_0F01_REG_5,
738 MOD_0F01_REG_7,
739 MOD_0F12_PREFIX_0,
740 MOD_0F12_PREFIX_2,
741 MOD_0F13,
742 MOD_0F16_PREFIX_0,
743 MOD_0F16_PREFIX_2,
744 MOD_0F17,
745 MOD_0F18_REG_0,
746 MOD_0F18_REG_1,
747 MOD_0F18_REG_2,
748 MOD_0F18_REG_3,
749 MOD_0F18_REG_4,
750 MOD_0F18_REG_5,
751 MOD_0F18_REG_6,
752 MOD_0F18_REG_7,
753 MOD_0F1A_PREFIX_0,
754 MOD_0F1B_PREFIX_0,
755 MOD_0F1B_PREFIX_1,
756 MOD_0F1C_PREFIX_0,
757 MOD_0F1E_PREFIX_1,
758 MOD_0F24,
759 MOD_0F26,
760 MOD_0F2B_PREFIX_0,
761 MOD_0F2B_PREFIX_1,
762 MOD_0F2B_PREFIX_2,
763 MOD_0F2B_PREFIX_3,
764 MOD_0F50,
765 MOD_0F71_REG_2,
766 MOD_0F71_REG_4,
767 MOD_0F71_REG_6,
768 MOD_0F72_REG_2,
769 MOD_0F72_REG_4,
770 MOD_0F72_REG_6,
771 MOD_0F73_REG_2,
772 MOD_0F73_REG_3,
773 MOD_0F73_REG_6,
774 MOD_0F73_REG_7,
775 MOD_0FAE_REG_0,
776 MOD_0FAE_REG_1,
777 MOD_0FAE_REG_2,
778 MOD_0FAE_REG_3,
779 MOD_0FAE_REG_4,
780 MOD_0FAE_REG_5,
781 MOD_0FAE_REG_6,
782 MOD_0FAE_REG_7,
783 MOD_0FB2,
784 MOD_0FB4,
785 MOD_0FB5,
786 MOD_0FC3,
787 MOD_0FC7_REG_3,
788 MOD_0FC7_REG_4,
789 MOD_0FC7_REG_5,
790 MOD_0FC7_REG_6,
791 MOD_0FC7_REG_7,
792 MOD_0FD7,
793 MOD_0FE7_PREFIX_2,
794 MOD_0FF0_PREFIX_3,
795 MOD_0F382A,
796 MOD_VEX_0F3849_X86_64_P_0_W_0,
797 MOD_VEX_0F3849_X86_64_P_2_W_0,
798 MOD_VEX_0F3849_X86_64_P_3_W_0,
799 MOD_VEX_0F384B_X86_64_P_1_W_0,
800 MOD_VEX_0F384B_X86_64_P_2_W_0,
801 MOD_VEX_0F384B_X86_64_P_3_W_0,
802 MOD_VEX_0F385C_X86_64_P_1_W_0,
803 MOD_VEX_0F385E_X86_64_P_0_W_0,
804 MOD_VEX_0F385E_X86_64_P_1_W_0,
805 MOD_VEX_0F385E_X86_64_P_2_W_0,
806 MOD_VEX_0F385E_X86_64_P_3_W_0,
807 MOD_0F38F5,
808 MOD_0F38F6_PREFIX_0,
809 MOD_0F38F8_PREFIX_1,
810 MOD_0F38F8_PREFIX_2,
811 MOD_0F38F8_PREFIX_3,
812 MOD_0F38F9,
813 MOD_62_32BIT,
814 MOD_C4_32BIT,
815 MOD_C5_32BIT,
816 MOD_VEX_0F12_PREFIX_0,
817 MOD_VEX_0F12_PREFIX_2,
818 MOD_VEX_0F13,
819 MOD_VEX_0F16_PREFIX_0,
820 MOD_VEX_0F16_PREFIX_2,
821 MOD_VEX_0F17,
822 MOD_VEX_0F2B,
823 MOD_VEX_W_0_0F41_P_0_LEN_1,
824 MOD_VEX_W_1_0F41_P_0_LEN_1,
825 MOD_VEX_W_0_0F41_P_2_LEN_1,
826 MOD_VEX_W_1_0F41_P_2_LEN_1,
827 MOD_VEX_W_0_0F42_P_0_LEN_1,
828 MOD_VEX_W_1_0F42_P_0_LEN_1,
829 MOD_VEX_W_0_0F42_P_2_LEN_1,
830 MOD_VEX_W_1_0F42_P_2_LEN_1,
831 MOD_VEX_W_0_0F44_P_0_LEN_1,
832 MOD_VEX_W_1_0F44_P_0_LEN_1,
833 MOD_VEX_W_0_0F44_P_2_LEN_1,
834 MOD_VEX_W_1_0F44_P_2_LEN_1,
835 MOD_VEX_W_0_0F45_P_0_LEN_1,
836 MOD_VEX_W_1_0F45_P_0_LEN_1,
837 MOD_VEX_W_0_0F45_P_2_LEN_1,
838 MOD_VEX_W_1_0F45_P_2_LEN_1,
839 MOD_VEX_W_0_0F46_P_0_LEN_1,
840 MOD_VEX_W_1_0F46_P_0_LEN_1,
841 MOD_VEX_W_0_0F46_P_2_LEN_1,
842 MOD_VEX_W_1_0F46_P_2_LEN_1,
843 MOD_VEX_W_0_0F47_P_0_LEN_1,
844 MOD_VEX_W_1_0F47_P_0_LEN_1,
845 MOD_VEX_W_0_0F47_P_2_LEN_1,
846 MOD_VEX_W_1_0F47_P_2_LEN_1,
847 MOD_VEX_W_0_0F4A_P_0_LEN_1,
848 MOD_VEX_W_1_0F4A_P_0_LEN_1,
849 MOD_VEX_W_0_0F4A_P_2_LEN_1,
850 MOD_VEX_W_1_0F4A_P_2_LEN_1,
851 MOD_VEX_W_0_0F4B_P_0_LEN_1,
852 MOD_VEX_W_1_0F4B_P_0_LEN_1,
853 MOD_VEX_W_0_0F4B_P_2_LEN_1,
854 MOD_VEX_0F50,
855 MOD_VEX_0F71_REG_2,
856 MOD_VEX_0F71_REG_4,
857 MOD_VEX_0F71_REG_6,
858 MOD_VEX_0F72_REG_2,
859 MOD_VEX_0F72_REG_4,
860 MOD_VEX_0F72_REG_6,
861 MOD_VEX_0F73_REG_2,
862 MOD_VEX_0F73_REG_3,
863 MOD_VEX_0F73_REG_6,
864 MOD_VEX_0F73_REG_7,
865 MOD_VEX_W_0_0F91_P_0_LEN_0,
866 MOD_VEX_W_1_0F91_P_0_LEN_0,
867 MOD_VEX_W_0_0F91_P_2_LEN_0,
868 MOD_VEX_W_1_0F91_P_2_LEN_0,
869 MOD_VEX_W_0_0F92_P_0_LEN_0,
870 MOD_VEX_W_0_0F92_P_2_LEN_0,
871 MOD_VEX_0F92_P_3_LEN_0,
872 MOD_VEX_W_0_0F93_P_0_LEN_0,
873 MOD_VEX_W_0_0F93_P_2_LEN_0,
874 MOD_VEX_0F93_P_3_LEN_0,
875 MOD_VEX_W_0_0F98_P_0_LEN_0,
876 MOD_VEX_W_1_0F98_P_0_LEN_0,
877 MOD_VEX_W_0_0F98_P_2_LEN_0,
878 MOD_VEX_W_1_0F98_P_2_LEN_0,
879 MOD_VEX_W_0_0F99_P_0_LEN_0,
880 MOD_VEX_W_1_0F99_P_0_LEN_0,
881 MOD_VEX_W_0_0F99_P_2_LEN_0,
882 MOD_VEX_W_1_0F99_P_2_LEN_0,
883 MOD_VEX_0FAE_REG_2,
884 MOD_VEX_0FAE_REG_3,
885 MOD_VEX_0FD7,
886 MOD_VEX_0FE7,
887 MOD_VEX_0FF0_PREFIX_3,
888 MOD_VEX_0F381A,
889 MOD_VEX_0F382A,
890 MOD_VEX_0F382C,
891 MOD_VEX_0F382D,
892 MOD_VEX_0F382E,
893 MOD_VEX_0F382F,
894 MOD_VEX_0F385A,
895 MOD_VEX_0F388C,
896 MOD_VEX_0F388E,
897 MOD_VEX_0F3A30_L_0,
898 MOD_VEX_0F3A31_L_0,
899 MOD_VEX_0F3A32_L_0,
900 MOD_VEX_0F3A33_L_0,
901
902 MOD_VEX_0FXOP_09_12,
903
904 MOD_EVEX_0F12_PREFIX_0,
905 MOD_EVEX_0F12_PREFIX_2,
906 MOD_EVEX_0F13,
907 MOD_EVEX_0F16_PREFIX_0,
908 MOD_EVEX_0F16_PREFIX_2,
909 MOD_EVEX_0F17,
910 MOD_EVEX_0F2B,
911 MOD_EVEX_0F381A_W_0,
912 MOD_EVEX_0F381A_W_1,
913 MOD_EVEX_0F381B_W_0,
914 MOD_EVEX_0F381B_W_1,
915 MOD_EVEX_0F385A_W_0,
916 MOD_EVEX_0F385A_W_1,
917 MOD_EVEX_0F385B_W_0,
918 MOD_EVEX_0F385B_W_1,
919 MOD_EVEX_0F38C6_REG_1,
920 MOD_EVEX_0F38C6_REG_2,
921 MOD_EVEX_0F38C6_REG_5,
922 MOD_EVEX_0F38C6_REG_6,
923 MOD_EVEX_0F38C7_REG_1,
924 MOD_EVEX_0F38C7_REG_2,
925 MOD_EVEX_0F38C7_REG_5,
926 MOD_EVEX_0F38C7_REG_6
927 };
928
929 enum
930 {
931 RM_C6_REG_7 = 0,
932 RM_C7_REG_7,
933 RM_0F01_REG_0,
934 RM_0F01_REG_1,
935 RM_0F01_REG_2,
936 RM_0F01_REG_3,
937 RM_0F01_REG_5_MOD_3,
938 RM_0F01_REG_7_MOD_3,
939 RM_0F1E_P_1_MOD_3_REG_7,
940 RM_0FAE_REG_6_MOD_3_P_0,
941 RM_0FAE_REG_7_MOD_3,
942 RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0
943 };
944
945 enum
946 {
947 PREFIX_90 = 0,
948 PREFIX_0F01_REG_3_RM_1,
949 PREFIX_0F01_REG_5_MOD_0,
950 PREFIX_0F01_REG_5_MOD_3_RM_0,
951 PREFIX_0F01_REG_5_MOD_3_RM_1,
952 PREFIX_0F01_REG_5_MOD_3_RM_2,
953 PREFIX_0F01_REG_7_MOD_3_RM_2,
954 PREFIX_0F09,
955 PREFIX_0F10,
956 PREFIX_0F11,
957 PREFIX_0F12,
958 PREFIX_0F16,
959 PREFIX_0F1A,
960 PREFIX_0F1B,
961 PREFIX_0F1C,
962 PREFIX_0F1E,
963 PREFIX_0F2A,
964 PREFIX_0F2B,
965 PREFIX_0F2C,
966 PREFIX_0F2D,
967 PREFIX_0F2E,
968 PREFIX_0F2F,
969 PREFIX_0F51,
970 PREFIX_0F52,
971 PREFIX_0F53,
972 PREFIX_0F58,
973 PREFIX_0F59,
974 PREFIX_0F5A,
975 PREFIX_0F5B,
976 PREFIX_0F5C,
977 PREFIX_0F5D,
978 PREFIX_0F5E,
979 PREFIX_0F5F,
980 PREFIX_0F60,
981 PREFIX_0F61,
982 PREFIX_0F62,
983 PREFIX_0F6F,
984 PREFIX_0F70,
985 PREFIX_0F78,
986 PREFIX_0F79,
987 PREFIX_0F7C,
988 PREFIX_0F7D,
989 PREFIX_0F7E,
990 PREFIX_0F7F,
991 PREFIX_0FAE_REG_0_MOD_3,
992 PREFIX_0FAE_REG_1_MOD_3,
993 PREFIX_0FAE_REG_2_MOD_3,
994 PREFIX_0FAE_REG_3_MOD_3,
995 PREFIX_0FAE_REG_4_MOD_0,
996 PREFIX_0FAE_REG_4_MOD_3,
997 PREFIX_0FAE_REG_5_MOD_3,
998 PREFIX_0FAE_REG_6_MOD_0,
999 PREFIX_0FAE_REG_6_MOD_3,
1000 PREFIX_0FAE_REG_7_MOD_0,
1001 PREFIX_0FB8,
1002 PREFIX_0FBC,
1003 PREFIX_0FBD,
1004 PREFIX_0FC2,
1005 PREFIX_0FC7_REG_6_MOD_0,
1006 PREFIX_0FC7_REG_6_MOD_3,
1007 PREFIX_0FC7_REG_7_MOD_3,
1008 PREFIX_0FD0,
1009 PREFIX_0FD6,
1010 PREFIX_0FE6,
1011 PREFIX_0FE7,
1012 PREFIX_0FF0,
1013 PREFIX_0FF7,
1014 PREFIX_0F38F0,
1015 PREFIX_0F38F1,
1016 PREFIX_0F38F6,
1017 PREFIX_0F38F8,
1018 PREFIX_VEX_0F10,
1019 PREFIX_VEX_0F11,
1020 PREFIX_VEX_0F12,
1021 PREFIX_VEX_0F16,
1022 PREFIX_VEX_0F2A,
1023 PREFIX_VEX_0F2C,
1024 PREFIX_VEX_0F2D,
1025 PREFIX_VEX_0F2E,
1026 PREFIX_VEX_0F2F,
1027 PREFIX_VEX_0F41,
1028 PREFIX_VEX_0F42,
1029 PREFIX_VEX_0F44,
1030 PREFIX_VEX_0F45,
1031 PREFIX_VEX_0F46,
1032 PREFIX_VEX_0F47,
1033 PREFIX_VEX_0F4A,
1034 PREFIX_VEX_0F4B,
1035 PREFIX_VEX_0F51,
1036 PREFIX_VEX_0F52,
1037 PREFIX_VEX_0F53,
1038 PREFIX_VEX_0F58,
1039 PREFIX_VEX_0F59,
1040 PREFIX_VEX_0F5A,
1041 PREFIX_VEX_0F5B,
1042 PREFIX_VEX_0F5C,
1043 PREFIX_VEX_0F5D,
1044 PREFIX_VEX_0F5E,
1045 PREFIX_VEX_0F5F,
1046 PREFIX_VEX_0F6F,
1047 PREFIX_VEX_0F70,
1048 PREFIX_VEX_0F7C,
1049 PREFIX_VEX_0F7D,
1050 PREFIX_VEX_0F7E,
1051 PREFIX_VEX_0F7F,
1052 PREFIX_VEX_0F90,
1053 PREFIX_VEX_0F91,
1054 PREFIX_VEX_0F92,
1055 PREFIX_VEX_0F93,
1056 PREFIX_VEX_0F98,
1057 PREFIX_VEX_0F99,
1058 PREFIX_VEX_0FC2,
1059 PREFIX_VEX_0FD0,
1060 PREFIX_VEX_0FE6,
1061 PREFIX_VEX_0FF0,
1062 PREFIX_VEX_0F3849_X86_64,
1063 PREFIX_VEX_0F384B_X86_64,
1064 PREFIX_VEX_0F385C_X86_64,
1065 PREFIX_VEX_0F385E_X86_64,
1066 PREFIX_VEX_0F38F5,
1067 PREFIX_VEX_0F38F6,
1068 PREFIX_VEX_0F38F7,
1069 PREFIX_VEX_0F3AF0,
1070
1071 PREFIX_EVEX_0F10,
1072 PREFIX_EVEX_0F11,
1073 PREFIX_EVEX_0F12,
1074 PREFIX_EVEX_0F16,
1075 PREFIX_EVEX_0F2A,
1076 PREFIX_EVEX_0F51,
1077 PREFIX_EVEX_0F58,
1078 PREFIX_EVEX_0F59,
1079 PREFIX_EVEX_0F5A,
1080 PREFIX_EVEX_0F5B,
1081 PREFIX_EVEX_0F5C,
1082 PREFIX_EVEX_0F5D,
1083 PREFIX_EVEX_0F5E,
1084 PREFIX_EVEX_0F5F,
1085 PREFIX_EVEX_0F6F,
1086 PREFIX_EVEX_0F70,
1087 PREFIX_EVEX_0F78,
1088 PREFIX_EVEX_0F79,
1089 PREFIX_EVEX_0F7A,
1090 PREFIX_EVEX_0F7B,
1091 PREFIX_EVEX_0F7E,
1092 PREFIX_EVEX_0F7F,
1093 PREFIX_EVEX_0FC2,
1094 PREFIX_EVEX_0FE6,
1095 PREFIX_EVEX_0F3810,
1096 PREFIX_EVEX_0F3811,
1097 PREFIX_EVEX_0F3812,
1098 PREFIX_EVEX_0F3813,
1099 PREFIX_EVEX_0F3814,
1100 PREFIX_EVEX_0F3815,
1101 PREFIX_EVEX_0F3820,
1102 PREFIX_EVEX_0F3821,
1103 PREFIX_EVEX_0F3822,
1104 PREFIX_EVEX_0F3823,
1105 PREFIX_EVEX_0F3824,
1106 PREFIX_EVEX_0F3825,
1107 PREFIX_EVEX_0F3826,
1108 PREFIX_EVEX_0F3827,
1109 PREFIX_EVEX_0F3828,
1110 PREFIX_EVEX_0F3829,
1111 PREFIX_EVEX_0F382A,
1112 PREFIX_EVEX_0F3830,
1113 PREFIX_EVEX_0F3831,
1114 PREFIX_EVEX_0F3832,
1115 PREFIX_EVEX_0F3833,
1116 PREFIX_EVEX_0F3834,
1117 PREFIX_EVEX_0F3835,
1118 PREFIX_EVEX_0F3838,
1119 PREFIX_EVEX_0F3839,
1120 PREFIX_EVEX_0F383A,
1121 PREFIX_EVEX_0F3852,
1122 PREFIX_EVEX_0F3853,
1123 PREFIX_EVEX_0F3868,
1124 PREFIX_EVEX_0F3872,
1125 PREFIX_EVEX_0F389A,
1126 PREFIX_EVEX_0F389B,
1127 PREFIX_EVEX_0F38AA,
1128 PREFIX_EVEX_0F38AB,
1129 };
1130
1131 enum
1132 {
1133 X86_64_06 = 0,
1134 X86_64_07,
1135 X86_64_0E,
1136 X86_64_16,
1137 X86_64_17,
1138 X86_64_1E,
1139 X86_64_1F,
1140 X86_64_27,
1141 X86_64_2F,
1142 X86_64_37,
1143 X86_64_3F,
1144 X86_64_60,
1145 X86_64_61,
1146 X86_64_62,
1147 X86_64_63,
1148 X86_64_6D,
1149 X86_64_6F,
1150 X86_64_82,
1151 X86_64_9A,
1152 X86_64_C2,
1153 X86_64_C3,
1154 X86_64_C4,
1155 X86_64_C5,
1156 X86_64_CE,
1157 X86_64_D4,
1158 X86_64_D5,
1159 X86_64_E8,
1160 X86_64_E9,
1161 X86_64_EA,
1162 X86_64_0F01_REG_0,
1163 X86_64_0F01_REG_1,
1164 X86_64_0F01_REG_2,
1165 X86_64_0F01_REG_3,
1166 X86_64_VEX_0F3849,
1167 X86_64_VEX_0F384B,
1168 X86_64_VEX_0F385C,
1169 X86_64_VEX_0F385E
1170 };
1171
1172 enum
1173 {
1174 THREE_BYTE_0F38 = 0,
1175 THREE_BYTE_0F3A
1176 };
1177
1178 enum
1179 {
1180 XOP_08 = 0,
1181 XOP_09,
1182 XOP_0A
1183 };
1184
1185 enum
1186 {
1187 VEX_0F = 0,
1188 VEX_0F38,
1189 VEX_0F3A
1190 };
1191
1192 enum
1193 {
1194 EVEX_0F = 0,
1195 EVEX_0F38,
1196 EVEX_0F3A
1197 };
1198
1199 enum
1200 {
1201 VEX_LEN_0F12_P_0_M_0 = 0,
1202 VEX_LEN_0F12_P_0_M_1,
1203 #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0
1204 VEX_LEN_0F13_M_0,
1205 VEX_LEN_0F16_P_0_M_0,
1206 VEX_LEN_0F16_P_0_M_1,
1207 #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0
1208 VEX_LEN_0F17_M_0,
1209 VEX_LEN_0F41_P_0,
1210 VEX_LEN_0F41_P_2,
1211 VEX_LEN_0F42_P_0,
1212 VEX_LEN_0F42_P_2,
1213 VEX_LEN_0F44_P_0,
1214 VEX_LEN_0F44_P_2,
1215 VEX_LEN_0F45_P_0,
1216 VEX_LEN_0F45_P_2,
1217 VEX_LEN_0F46_P_0,
1218 VEX_LEN_0F46_P_2,
1219 VEX_LEN_0F47_P_0,
1220 VEX_LEN_0F47_P_2,
1221 VEX_LEN_0F4A_P_0,
1222 VEX_LEN_0F4A_P_2,
1223 VEX_LEN_0F4B_P_0,
1224 VEX_LEN_0F4B_P_2,
1225 VEX_LEN_0F6E,
1226 VEX_LEN_0F77,
1227 VEX_LEN_0F7E_P_1,
1228 VEX_LEN_0F7E_P_2,
1229 VEX_LEN_0F90_P_0,
1230 VEX_LEN_0F90_P_2,
1231 VEX_LEN_0F91_P_0,
1232 VEX_LEN_0F91_P_2,
1233 VEX_LEN_0F92_P_0,
1234 VEX_LEN_0F92_P_2,
1235 VEX_LEN_0F92_P_3,
1236 VEX_LEN_0F93_P_0,
1237 VEX_LEN_0F93_P_2,
1238 VEX_LEN_0F93_P_3,
1239 VEX_LEN_0F98_P_0,
1240 VEX_LEN_0F98_P_2,
1241 VEX_LEN_0F99_P_0,
1242 VEX_LEN_0F99_P_2,
1243 VEX_LEN_0FAE_R_2_M_0,
1244 VEX_LEN_0FAE_R_3_M_0,
1245 VEX_LEN_0FC4,
1246 VEX_LEN_0FC5,
1247 VEX_LEN_0FD6,
1248 VEX_LEN_0FF7,
1249 VEX_LEN_0F3816,
1250 VEX_LEN_0F3819,
1251 VEX_LEN_0F381A_M_0,
1252 VEX_LEN_0F3836,
1253 VEX_LEN_0F3841,
1254 VEX_LEN_0F3849_X86_64_P_0_W_0_M_0,
1255 VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0,
1256 VEX_LEN_0F3849_X86_64_P_2_W_0_M_0,
1257 VEX_LEN_0F3849_X86_64_P_3_W_0_M_0,
1258 VEX_LEN_0F384B_X86_64_P_1_W_0_M_0,
1259 VEX_LEN_0F384B_X86_64_P_2_W_0_M_0,
1260 VEX_LEN_0F384B_X86_64_P_3_W_0_M_0,
1261 VEX_LEN_0F385A_M_0,
1262 VEX_LEN_0F385C_X86_64_P_1_W_0_M_0,
1263 VEX_LEN_0F385E_X86_64_P_0_W_0_M_0,
1264 VEX_LEN_0F385E_X86_64_P_1_W_0_M_0,
1265 VEX_LEN_0F385E_X86_64_P_2_W_0_M_0,
1266 VEX_LEN_0F385E_X86_64_P_3_W_0_M_0,
1267 VEX_LEN_0F38DB,
1268 VEX_LEN_0F38F2,
1269 VEX_LEN_0F38F3_R_1,
1270 VEX_LEN_0F38F3_R_2,
1271 VEX_LEN_0F38F3_R_3,
1272 VEX_LEN_0F38F5_P_0,
1273 VEX_LEN_0F38F5_P_1,
1274 VEX_LEN_0F38F5_P_3,
1275 VEX_LEN_0F38F6_P_3,
1276 VEX_LEN_0F38F7_P_0,
1277 VEX_LEN_0F38F7_P_1,
1278 VEX_LEN_0F38F7_P_2,
1279 VEX_LEN_0F38F7_P_3,
1280 VEX_LEN_0F3A00,
1281 VEX_LEN_0F3A01,
1282 VEX_LEN_0F3A06,
1283 VEX_LEN_0F3A14,
1284 VEX_LEN_0F3A15,
1285 VEX_LEN_0F3A16,
1286 VEX_LEN_0F3A17,
1287 VEX_LEN_0F3A18,
1288 VEX_LEN_0F3A19,
1289 VEX_LEN_0F3A20,
1290 VEX_LEN_0F3A21,
1291 VEX_LEN_0F3A22,
1292 VEX_LEN_0F3A30,
1293 VEX_LEN_0F3A31,
1294 VEX_LEN_0F3A32,
1295 VEX_LEN_0F3A33,
1296 VEX_LEN_0F3A38,
1297 VEX_LEN_0F3A39,
1298 VEX_LEN_0F3A41,
1299 VEX_LEN_0F3A46,
1300 VEX_LEN_0F3A60,
1301 VEX_LEN_0F3A61,
1302 VEX_LEN_0F3A62,
1303 VEX_LEN_0F3A63,
1304 VEX_LEN_0F3ADF,
1305 VEX_LEN_0F3AF0_P_3,
1306 VEX_LEN_0FXOP_08_85,
1307 VEX_LEN_0FXOP_08_86,
1308 VEX_LEN_0FXOP_08_87,
1309 VEX_LEN_0FXOP_08_8E,
1310 VEX_LEN_0FXOP_08_8F,
1311 VEX_LEN_0FXOP_08_95,
1312 VEX_LEN_0FXOP_08_96,
1313 VEX_LEN_0FXOP_08_97,
1314 VEX_LEN_0FXOP_08_9E,
1315 VEX_LEN_0FXOP_08_9F,
1316 VEX_LEN_0FXOP_08_A3,
1317 VEX_LEN_0FXOP_08_A6,
1318 VEX_LEN_0FXOP_08_B6,
1319 VEX_LEN_0FXOP_08_C0,
1320 VEX_LEN_0FXOP_08_C1,
1321 VEX_LEN_0FXOP_08_C2,
1322 VEX_LEN_0FXOP_08_C3,
1323 VEX_LEN_0FXOP_08_CC,
1324 VEX_LEN_0FXOP_08_CD,
1325 VEX_LEN_0FXOP_08_CE,
1326 VEX_LEN_0FXOP_08_CF,
1327 VEX_LEN_0FXOP_08_EC,
1328 VEX_LEN_0FXOP_08_ED,
1329 VEX_LEN_0FXOP_08_EE,
1330 VEX_LEN_0FXOP_08_EF,
1331 VEX_LEN_0FXOP_09_01,
1332 VEX_LEN_0FXOP_09_02,
1333 VEX_LEN_0FXOP_09_12_M_1,
1334 VEX_LEN_0FXOP_09_82_W_0,
1335 VEX_LEN_0FXOP_09_83_W_0,
1336 VEX_LEN_0FXOP_09_90,
1337 VEX_LEN_0FXOP_09_91,
1338 VEX_LEN_0FXOP_09_92,
1339 VEX_LEN_0FXOP_09_93,
1340 VEX_LEN_0FXOP_09_94,
1341 VEX_LEN_0FXOP_09_95,
1342 VEX_LEN_0FXOP_09_96,
1343 VEX_LEN_0FXOP_09_97,
1344 VEX_LEN_0FXOP_09_98,
1345 VEX_LEN_0FXOP_09_99,
1346 VEX_LEN_0FXOP_09_9A,
1347 VEX_LEN_0FXOP_09_9B,
1348 VEX_LEN_0FXOP_09_C1,
1349 VEX_LEN_0FXOP_09_C2,
1350 VEX_LEN_0FXOP_09_C3,
1351 VEX_LEN_0FXOP_09_C6,
1352 VEX_LEN_0FXOP_09_C7,
1353 VEX_LEN_0FXOP_09_CB,
1354 VEX_LEN_0FXOP_09_D1,
1355 VEX_LEN_0FXOP_09_D2,
1356 VEX_LEN_0FXOP_09_D3,
1357 VEX_LEN_0FXOP_09_D6,
1358 VEX_LEN_0FXOP_09_D7,
1359 VEX_LEN_0FXOP_09_DB,
1360 VEX_LEN_0FXOP_09_E1,
1361 VEX_LEN_0FXOP_09_E2,
1362 VEX_LEN_0FXOP_09_E3,
1363 VEX_LEN_0FXOP_0A_12,
1364 };
1365
1366 enum
1367 {
1368 EVEX_LEN_0F6E = 0,
1369 EVEX_LEN_0F7E_P_1,
1370 EVEX_LEN_0F7E_P_2,
1371 EVEX_LEN_0FC4,
1372 EVEX_LEN_0FC5,
1373 EVEX_LEN_0FD6,
1374 EVEX_LEN_0F3816,
1375 EVEX_LEN_0F3819_W_0,
1376 EVEX_LEN_0F3819_W_1,
1377 EVEX_LEN_0F381A_W_0_M_0,
1378 EVEX_LEN_0F381A_W_1_M_0,
1379 EVEX_LEN_0F381B_W_0_M_0,
1380 EVEX_LEN_0F381B_W_1_M_0,
1381 EVEX_LEN_0F3836,
1382 EVEX_LEN_0F385A_W_0_M_0,
1383 EVEX_LEN_0F385A_W_1_M_0,
1384 EVEX_LEN_0F385B_W_0_M_0,
1385 EVEX_LEN_0F385B_W_1_M_0,
1386 EVEX_LEN_0F38C6_R_1_M_0,
1387 EVEX_LEN_0F38C6_R_2_M_0,
1388 EVEX_LEN_0F38C6_R_5_M_0,
1389 EVEX_LEN_0F38C6_R_6_M_0,
1390 EVEX_LEN_0F38C7_R_1_M_0_W_0,
1391 EVEX_LEN_0F38C7_R_1_M_0_W_1,
1392 EVEX_LEN_0F38C7_R_2_M_0_W_0,
1393 EVEX_LEN_0F38C7_R_2_M_0_W_1,
1394 EVEX_LEN_0F38C7_R_5_M_0_W_0,
1395 EVEX_LEN_0F38C7_R_5_M_0_W_1,
1396 EVEX_LEN_0F38C7_R_6_M_0_W_0,
1397 EVEX_LEN_0F38C7_R_6_M_0_W_1,
1398 EVEX_LEN_0F3A00_W_1,
1399 EVEX_LEN_0F3A01_W_1,
1400 EVEX_LEN_0F3A14,
1401 EVEX_LEN_0F3A15,
1402 EVEX_LEN_0F3A16,
1403 EVEX_LEN_0F3A17,
1404 EVEX_LEN_0F3A18_W_0,
1405 EVEX_LEN_0F3A18_W_1,
1406 EVEX_LEN_0F3A19_W_0,
1407 EVEX_LEN_0F3A19_W_1,
1408 EVEX_LEN_0F3A1A_W_0,
1409 EVEX_LEN_0F3A1A_W_1,
1410 EVEX_LEN_0F3A1B_W_0,
1411 EVEX_LEN_0F3A1B_W_1,
1412 EVEX_LEN_0F3A20,
1413 EVEX_LEN_0F3A21_W_0,
1414 EVEX_LEN_0F3A22,
1415 EVEX_LEN_0F3A23_W_0,
1416 EVEX_LEN_0F3A23_W_1,
1417 EVEX_LEN_0F3A38_W_0,
1418 EVEX_LEN_0F3A38_W_1,
1419 EVEX_LEN_0F3A39_W_0,
1420 EVEX_LEN_0F3A39_W_1,
1421 EVEX_LEN_0F3A3A_W_0,
1422 EVEX_LEN_0F3A3A_W_1,
1423 EVEX_LEN_0F3A3B_W_0,
1424 EVEX_LEN_0F3A3B_W_1,
1425 EVEX_LEN_0F3A43_W_0,
1426 EVEX_LEN_0F3A43_W_1
1427 };
1428
1429 enum
1430 {
1431 VEX_W_0F41_P_0_LEN_1 = 0,
1432 VEX_W_0F41_P_2_LEN_1,
1433 VEX_W_0F42_P_0_LEN_1,
1434 VEX_W_0F42_P_2_LEN_1,
1435 VEX_W_0F44_P_0_LEN_0,
1436 VEX_W_0F44_P_2_LEN_0,
1437 VEX_W_0F45_P_0_LEN_1,
1438 VEX_W_0F45_P_2_LEN_1,
1439 VEX_W_0F46_P_0_LEN_1,
1440 VEX_W_0F46_P_2_LEN_1,
1441 VEX_W_0F47_P_0_LEN_1,
1442 VEX_W_0F47_P_2_LEN_1,
1443 VEX_W_0F4A_P_0_LEN_1,
1444 VEX_W_0F4A_P_2_LEN_1,
1445 VEX_W_0F4B_P_0_LEN_1,
1446 VEX_W_0F4B_P_2_LEN_1,
1447 VEX_W_0F90_P_0_LEN_0,
1448 VEX_W_0F90_P_2_LEN_0,
1449 VEX_W_0F91_P_0_LEN_0,
1450 VEX_W_0F91_P_2_LEN_0,
1451 VEX_W_0F92_P_0_LEN_0,
1452 VEX_W_0F92_P_2_LEN_0,
1453 VEX_W_0F93_P_0_LEN_0,
1454 VEX_W_0F93_P_2_LEN_0,
1455 VEX_W_0F98_P_0_LEN_0,
1456 VEX_W_0F98_P_2_LEN_0,
1457 VEX_W_0F99_P_0_LEN_0,
1458 VEX_W_0F99_P_2_LEN_0,
1459 VEX_W_0F380C,
1460 VEX_W_0F380D,
1461 VEX_W_0F380E,
1462 VEX_W_0F380F,
1463 VEX_W_0F3813,
1464 VEX_W_0F3816_L_1,
1465 VEX_W_0F3818,
1466 VEX_W_0F3819_L_1,
1467 VEX_W_0F381A_M_0_L_1,
1468 VEX_W_0F382C_M_0,
1469 VEX_W_0F382D_M_0,
1470 VEX_W_0F382E_M_0,
1471 VEX_W_0F382F_M_0,
1472 VEX_W_0F3836,
1473 VEX_W_0F3846,
1474 VEX_W_0F3849_X86_64_P_0,
1475 VEX_W_0F3849_X86_64_P_2,
1476 VEX_W_0F3849_X86_64_P_3,
1477 VEX_W_0F384B_X86_64_P_1,
1478 VEX_W_0F384B_X86_64_P_2,
1479 VEX_W_0F384B_X86_64_P_3,
1480 VEX_W_0F3858,
1481 VEX_W_0F3859,
1482 VEX_W_0F385A_M_0_L_0,
1483 VEX_W_0F385C_X86_64_P_1,
1484 VEX_W_0F385E_X86_64_P_0,
1485 VEX_W_0F385E_X86_64_P_1,
1486 VEX_W_0F385E_X86_64_P_2,
1487 VEX_W_0F385E_X86_64_P_3,
1488 VEX_W_0F3878,
1489 VEX_W_0F3879,
1490 VEX_W_0F38CF,
1491 VEX_W_0F3A00_L_1,
1492 VEX_W_0F3A01_L_1,
1493 VEX_W_0F3A02,
1494 VEX_W_0F3A04,
1495 VEX_W_0F3A05,
1496 VEX_W_0F3A06_L_1,
1497 VEX_W_0F3A18_L_1,
1498 VEX_W_0F3A19_L_1,
1499 VEX_W_0F3A1D,
1500 VEX_W_0F3A38_L_1,
1501 VEX_W_0F3A39_L_1,
1502 VEX_W_0F3A46_L_1,
1503 VEX_W_0F3A4A,
1504 VEX_W_0F3A4B,
1505 VEX_W_0F3A4C,
1506 VEX_W_0F3ACE,
1507 VEX_W_0F3ACF,
1508
1509 VEX_W_0FXOP_08_85_L_0,
1510 VEX_W_0FXOP_08_86_L_0,
1511 VEX_W_0FXOP_08_87_L_0,
1512 VEX_W_0FXOP_08_8E_L_0,
1513 VEX_W_0FXOP_08_8F_L_0,
1514 VEX_W_0FXOP_08_95_L_0,
1515 VEX_W_0FXOP_08_96_L_0,
1516 VEX_W_0FXOP_08_97_L_0,
1517 VEX_W_0FXOP_08_9E_L_0,
1518 VEX_W_0FXOP_08_9F_L_0,
1519 VEX_W_0FXOP_08_A6_L_0,
1520 VEX_W_0FXOP_08_B6_L_0,
1521 VEX_W_0FXOP_08_C0_L_0,
1522 VEX_W_0FXOP_08_C1_L_0,
1523 VEX_W_0FXOP_08_C2_L_0,
1524 VEX_W_0FXOP_08_C3_L_0,
1525 VEX_W_0FXOP_08_CC_L_0,
1526 VEX_W_0FXOP_08_CD_L_0,
1527 VEX_W_0FXOP_08_CE_L_0,
1528 VEX_W_0FXOP_08_CF_L_0,
1529 VEX_W_0FXOP_08_EC_L_0,
1530 VEX_W_0FXOP_08_ED_L_0,
1531 VEX_W_0FXOP_08_EE_L_0,
1532 VEX_W_0FXOP_08_EF_L_0,
1533
1534 VEX_W_0FXOP_09_80,
1535 VEX_W_0FXOP_09_81,
1536 VEX_W_0FXOP_09_82,
1537 VEX_W_0FXOP_09_83,
1538 VEX_W_0FXOP_09_C1_L_0,
1539 VEX_W_0FXOP_09_C2_L_0,
1540 VEX_W_0FXOP_09_C3_L_0,
1541 VEX_W_0FXOP_09_C6_L_0,
1542 VEX_W_0FXOP_09_C7_L_0,
1543 VEX_W_0FXOP_09_CB_L_0,
1544 VEX_W_0FXOP_09_D1_L_0,
1545 VEX_W_0FXOP_09_D2_L_0,
1546 VEX_W_0FXOP_09_D3_L_0,
1547 VEX_W_0FXOP_09_D6_L_0,
1548 VEX_W_0FXOP_09_D7_L_0,
1549 VEX_W_0FXOP_09_DB_L_0,
1550 VEX_W_0FXOP_09_E1_L_0,
1551 VEX_W_0FXOP_09_E2_L_0,
1552 VEX_W_0FXOP_09_E3_L_0,
1553
1554 EVEX_W_0F10_P_1,
1555 EVEX_W_0F10_P_3,
1556 EVEX_W_0F11_P_1,
1557 EVEX_W_0F11_P_3,
1558 EVEX_W_0F12_P_0_M_1,
1559 EVEX_W_0F12_P_1,
1560 EVEX_W_0F12_P_3,
1561 EVEX_W_0F16_P_0_M_1,
1562 EVEX_W_0F16_P_1,
1563 EVEX_W_0F2A_P_3,
1564 EVEX_W_0F51_P_1,
1565 EVEX_W_0F51_P_3,
1566 EVEX_W_0F58_P_1,
1567 EVEX_W_0F58_P_3,
1568 EVEX_W_0F59_P_1,
1569 EVEX_W_0F59_P_3,
1570 EVEX_W_0F5A_P_0,
1571 EVEX_W_0F5A_P_1,
1572 EVEX_W_0F5A_P_2,
1573 EVEX_W_0F5A_P_3,
1574 EVEX_W_0F5B_P_0,
1575 EVEX_W_0F5B_P_1,
1576 EVEX_W_0F5B_P_2,
1577 EVEX_W_0F5C_P_1,
1578 EVEX_W_0F5C_P_3,
1579 EVEX_W_0F5D_P_1,
1580 EVEX_W_0F5D_P_3,
1581 EVEX_W_0F5E_P_1,
1582 EVEX_W_0F5E_P_3,
1583 EVEX_W_0F5F_P_1,
1584 EVEX_W_0F5F_P_3,
1585 EVEX_W_0F62,
1586 EVEX_W_0F66,
1587 EVEX_W_0F6A,
1588 EVEX_W_0F6B,
1589 EVEX_W_0F6C,
1590 EVEX_W_0F6D,
1591 EVEX_W_0F6F_P_1,
1592 EVEX_W_0F6F_P_2,
1593 EVEX_W_0F6F_P_3,
1594 EVEX_W_0F70_P_2,
1595 EVEX_W_0F72_R_2,
1596 EVEX_W_0F72_R_6,
1597 EVEX_W_0F73_R_2,
1598 EVEX_W_0F73_R_6,
1599 EVEX_W_0F76,
1600 EVEX_W_0F78_P_0,
1601 EVEX_W_0F78_P_2,
1602 EVEX_W_0F79_P_0,
1603 EVEX_W_0F79_P_2,
1604 EVEX_W_0F7A_P_1,
1605 EVEX_W_0F7A_P_2,
1606 EVEX_W_0F7A_P_3,
1607 EVEX_W_0F7B_P_2,
1608 EVEX_W_0F7B_P_3,
1609 EVEX_W_0F7E_P_1,
1610 EVEX_W_0F7F_P_1,
1611 EVEX_W_0F7F_P_2,
1612 EVEX_W_0F7F_P_3,
1613 EVEX_W_0FC2_P_1,
1614 EVEX_W_0FC2_P_3,
1615 EVEX_W_0FD2,
1616 EVEX_W_0FD3,
1617 EVEX_W_0FD4,
1618 EVEX_W_0FD6_L_0,
1619 EVEX_W_0FE6_P_1,
1620 EVEX_W_0FE6_P_2,
1621 EVEX_W_0FE6_P_3,
1622 EVEX_W_0FE7,
1623 EVEX_W_0FF2,
1624 EVEX_W_0FF3,
1625 EVEX_W_0FF4,
1626 EVEX_W_0FFA,
1627 EVEX_W_0FFB,
1628 EVEX_W_0FFE,
1629 EVEX_W_0F380D,
1630 EVEX_W_0F3810_P_1,
1631 EVEX_W_0F3810_P_2,
1632 EVEX_W_0F3811_P_1,
1633 EVEX_W_0F3811_P_2,
1634 EVEX_W_0F3812_P_1,
1635 EVEX_W_0F3812_P_2,
1636 EVEX_W_0F3813_P_1,
1637 EVEX_W_0F3813_P_2,
1638 EVEX_W_0F3814_P_1,
1639 EVEX_W_0F3815_P_1,
1640 EVEX_W_0F3819,
1641 EVEX_W_0F381A,
1642 EVEX_W_0F381B,
1643 EVEX_W_0F381E,
1644 EVEX_W_0F381F,
1645 EVEX_W_0F3820_P_1,
1646 EVEX_W_0F3821_P_1,
1647 EVEX_W_0F3822_P_1,
1648 EVEX_W_0F3823_P_1,
1649 EVEX_W_0F3824_P_1,
1650 EVEX_W_0F3825_P_1,
1651 EVEX_W_0F3825_P_2,
1652 EVEX_W_0F3828_P_2,
1653 EVEX_W_0F3829_P_2,
1654 EVEX_W_0F382A_P_1,
1655 EVEX_W_0F382A_P_2,
1656 EVEX_W_0F382B,
1657 EVEX_W_0F3830_P_1,
1658 EVEX_W_0F3831_P_1,
1659 EVEX_W_0F3832_P_1,
1660 EVEX_W_0F3833_P_1,
1661 EVEX_W_0F3834_P_1,
1662 EVEX_W_0F3835_P_1,
1663 EVEX_W_0F3835_P_2,
1664 EVEX_W_0F3837,
1665 EVEX_W_0F383A_P_1,
1666 EVEX_W_0F3852_P_1,
1667 EVEX_W_0F3859,
1668 EVEX_W_0F385A,
1669 EVEX_W_0F385B,
1670 EVEX_W_0F3870,
1671 EVEX_W_0F3872_P_1,
1672 EVEX_W_0F3872_P_2,
1673 EVEX_W_0F3872_P_3,
1674 EVEX_W_0F387A,
1675 EVEX_W_0F387B,
1676 EVEX_W_0F3883,
1677 EVEX_W_0F3891,
1678 EVEX_W_0F3893,
1679 EVEX_W_0F38A1,
1680 EVEX_W_0F38A3,
1681 EVEX_W_0F38C7_R_1_M_0,
1682 EVEX_W_0F38C7_R_2_M_0,
1683 EVEX_W_0F38C7_R_5_M_0,
1684 EVEX_W_0F38C7_R_6_M_0,
1685
1686 EVEX_W_0F3A00,
1687 EVEX_W_0F3A01,
1688 EVEX_W_0F3A05,
1689 EVEX_W_0F3A08,
1690 EVEX_W_0F3A09,
1691 EVEX_W_0F3A0A,
1692 EVEX_W_0F3A0B,
1693 EVEX_W_0F3A18,
1694 EVEX_W_0F3A19,
1695 EVEX_W_0F3A1A,
1696 EVEX_W_0F3A1B,
1697 EVEX_W_0F3A21,
1698 EVEX_W_0F3A23,
1699 EVEX_W_0F3A38,
1700 EVEX_W_0F3A39,
1701 EVEX_W_0F3A3A,
1702 EVEX_W_0F3A3B,
1703 EVEX_W_0F3A42,
1704 EVEX_W_0F3A43,
1705 EVEX_W_0F3A70,
1706 EVEX_W_0F3A72,
1707 };
1708
1709 typedef void (*op_rtn) (int bytemode, int sizeflag);
1710
1711 struct dis386 {
1712 const char *name;
1713 struct
1714 {
1715 op_rtn rtn;
1716 int bytemode;
1717 } op[MAX_OPERANDS];
1718 unsigned int prefix_requirement;
1719 };
1720
1721 /* Upper case letters in the instruction names here are macros.
1722 'A' => print 'b' if no register operands or suffix_always is true
1723 'B' => print 'b' if suffix_always is true
1724 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1725 size prefix
1726 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1727 suffix_always is true
1728 'E' => print 'e' if 32-bit form of jcxz
1729 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1730 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1731 'H' => print ",pt" or ",pn" branch hint
1732 'I' unused.
1733 'J' unused.
1734 'K' => print 'd' or 'q' if rex prefix is present.
1735 'L' => print 'l' if suffix_always is true
1736 'M' => print 'r' if intel_mnemonic is false.
1737 'N' => print 'n' if instruction has no wait "prefix"
1738 'O' => print 'd' or 'o' (or 'q' in Intel mode)
1739 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
1740 or suffix_always is true. print 'q' if rex prefix is present.
1741 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1742 is true
1743 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1744 'S' => print 'w', 'l' or 'q' if suffix_always is true
1745 'T' => print 'q' in 64bit mode if instruction has no operand size
1746 prefix and behave as 'P' otherwise
1747 'U' => print 'q' in 64bit mode if instruction has no operand size
1748 prefix and behave as 'Q' otherwise
1749 'V' => print 'q' in 64bit mode if instruction has no operand size
1750 prefix and behave as 'S' otherwise
1751 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1752 'X' => print 's', 'd' depending on data16 prefix (for XMM)
1753 'Y' unused.
1754 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
1755 '!' => change condition from true to false or from false to true.
1756 '%' => add 1 upper case letter to the macro.
1757 '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
1758 prefix or suffix_always is true (lcall/ljmp).
1759 '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
1760 on operand size prefix.
1761 '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
1762 has no operand size prefix for AMD64 ISA, behave as 'P'
1763 otherwise
1764
1765 2 upper case letter macros:
1766 "XY" => print 'x' or 'y' if suffix_always is true or no register
1767 operands and no broadcast.
1768 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
1769 register operands and no broadcast.
1770 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1771 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond
1772 being false, or no operand at all in 64bit mode, or if suffix_always
1773 is true.
1774 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1775 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1776 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1777 "DQ" => print 'd' or 'q' depending on the VEX.W bit
1778 "BW" => print 'b' or 'w' depending on the VEX.W bit
1779 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
1780 an operand size prefix, or suffix_always is true. print
1781 'q' if rex prefix is present.
1782
1783 Many of the above letters print nothing in Intel mode. See "putop"
1784 for the details.
1785
1786 Braces '{' and '}', and vertical bars '|', indicate alternative
1787 mnemonic strings for AT&T and Intel. */
1788
1789 static const struct dis386 dis386[] = {
1790 /* 00 */
1791 { "addB", { Ebh1, Gb }, 0 },
1792 { "addS", { Evh1, Gv }, 0 },
1793 { "addB", { Gb, EbS }, 0 },
1794 { "addS", { Gv, EvS }, 0 },
1795 { "addB", { AL, Ib }, 0 },
1796 { "addS", { eAX, Iv }, 0 },
1797 { X86_64_TABLE (X86_64_06) },
1798 { X86_64_TABLE (X86_64_07) },
1799 /* 08 */
1800 { "orB", { Ebh1, Gb }, 0 },
1801 { "orS", { Evh1, Gv }, 0 },
1802 { "orB", { Gb, EbS }, 0 },
1803 { "orS", { Gv, EvS }, 0 },
1804 { "orB", { AL, Ib }, 0 },
1805 { "orS", { eAX, Iv }, 0 },
1806 { X86_64_TABLE (X86_64_0E) },
1807 { Bad_Opcode }, /* 0x0f extended opcode escape */
1808 /* 10 */
1809 { "adcB", { Ebh1, Gb }, 0 },
1810 { "adcS", { Evh1, Gv }, 0 },
1811 { "adcB", { Gb, EbS }, 0 },
1812 { "adcS", { Gv, EvS }, 0 },
1813 { "adcB", { AL, Ib }, 0 },
1814 { "adcS", { eAX, Iv }, 0 },
1815 { X86_64_TABLE (X86_64_16) },
1816 { X86_64_TABLE (X86_64_17) },
1817 /* 18 */
1818 { "sbbB", { Ebh1, Gb }, 0 },
1819 { "sbbS", { Evh1, Gv }, 0 },
1820 { "sbbB", { Gb, EbS }, 0 },
1821 { "sbbS", { Gv, EvS }, 0 },
1822 { "sbbB", { AL, Ib }, 0 },
1823 { "sbbS", { eAX, Iv }, 0 },
1824 { X86_64_TABLE (X86_64_1E) },
1825 { X86_64_TABLE (X86_64_1F) },
1826 /* 20 */
1827 { "andB", { Ebh1, Gb }, 0 },
1828 { "andS", { Evh1, Gv }, 0 },
1829 { "andB", { Gb, EbS }, 0 },
1830 { "andS", { Gv, EvS }, 0 },
1831 { "andB", { AL, Ib }, 0 },
1832 { "andS", { eAX, Iv }, 0 },
1833 { Bad_Opcode }, /* SEG ES prefix */
1834 { X86_64_TABLE (X86_64_27) },
1835 /* 28 */
1836 { "subB", { Ebh1, Gb }, 0 },
1837 { "subS", { Evh1, Gv }, 0 },
1838 { "subB", { Gb, EbS }, 0 },
1839 { "subS", { Gv, EvS }, 0 },
1840 { "subB", { AL, Ib }, 0 },
1841 { "subS", { eAX, Iv }, 0 },
1842 { Bad_Opcode }, /* SEG CS prefix */
1843 { X86_64_TABLE (X86_64_2F) },
1844 /* 30 */
1845 { "xorB", { Ebh1, Gb }, 0 },
1846 { "xorS", { Evh1, Gv }, 0 },
1847 { "xorB", { Gb, EbS }, 0 },
1848 { "xorS", { Gv, EvS }, 0 },
1849 { "xorB", { AL, Ib }, 0 },
1850 { "xorS", { eAX, Iv }, 0 },
1851 { Bad_Opcode }, /* SEG SS prefix */
1852 { X86_64_TABLE (X86_64_37) },
1853 /* 38 */
1854 { "cmpB", { Eb, Gb }, 0 },
1855 { "cmpS", { Ev, Gv }, 0 },
1856 { "cmpB", { Gb, EbS }, 0 },
1857 { "cmpS", { Gv, EvS }, 0 },
1858 { "cmpB", { AL, Ib }, 0 },
1859 { "cmpS", { eAX, Iv }, 0 },
1860 { Bad_Opcode }, /* SEG DS prefix */
1861 { X86_64_TABLE (X86_64_3F) },
1862 /* 40 */
1863 { "inc{S|}", { RMeAX }, 0 },
1864 { "inc{S|}", { RMeCX }, 0 },
1865 { "inc{S|}", { RMeDX }, 0 },
1866 { "inc{S|}", { RMeBX }, 0 },
1867 { "inc{S|}", { RMeSP }, 0 },
1868 { "inc{S|}", { RMeBP }, 0 },
1869 { "inc{S|}", { RMeSI }, 0 },
1870 { "inc{S|}", { RMeDI }, 0 },
1871 /* 48 */
1872 { "dec{S|}", { RMeAX }, 0 },
1873 { "dec{S|}", { RMeCX }, 0 },
1874 { "dec{S|}", { RMeDX }, 0 },
1875 { "dec{S|}", { RMeBX }, 0 },
1876 { "dec{S|}", { RMeSP }, 0 },
1877 { "dec{S|}", { RMeBP }, 0 },
1878 { "dec{S|}", { RMeSI }, 0 },
1879 { "dec{S|}", { RMeDI }, 0 },
1880 /* 50 */
1881 { "pushV", { RMrAX }, 0 },
1882 { "pushV", { RMrCX }, 0 },
1883 { "pushV", { RMrDX }, 0 },
1884 { "pushV", { RMrBX }, 0 },
1885 { "pushV", { RMrSP }, 0 },
1886 { "pushV", { RMrBP }, 0 },
1887 { "pushV", { RMrSI }, 0 },
1888 { "pushV", { RMrDI }, 0 },
1889 /* 58 */
1890 { "popV", { RMrAX }, 0 },
1891 { "popV", { RMrCX }, 0 },
1892 { "popV", { RMrDX }, 0 },
1893 { "popV", { RMrBX }, 0 },
1894 { "popV", { RMrSP }, 0 },
1895 { "popV", { RMrBP }, 0 },
1896 { "popV", { RMrSI }, 0 },
1897 { "popV", { RMrDI }, 0 },
1898 /* 60 */
1899 { X86_64_TABLE (X86_64_60) },
1900 { X86_64_TABLE (X86_64_61) },
1901 { X86_64_TABLE (X86_64_62) },
1902 { X86_64_TABLE (X86_64_63) },
1903 { Bad_Opcode }, /* seg fs */
1904 { Bad_Opcode }, /* seg gs */
1905 { Bad_Opcode }, /* op size prefix */
1906 { Bad_Opcode }, /* adr size prefix */
1907 /* 68 */
1908 { "pushT", { sIv }, 0 },
1909 { "imulS", { Gv, Ev, Iv }, 0 },
1910 { "pushT", { sIbT }, 0 },
1911 { "imulS", { Gv, Ev, sIb }, 0 },
1912 { "ins{b|}", { Ybr, indirDX }, 0 },
1913 { X86_64_TABLE (X86_64_6D) },
1914 { "outs{b|}", { indirDXr, Xb }, 0 },
1915 { X86_64_TABLE (X86_64_6F) },
1916 /* 70 */
1917 { "joH", { Jb, BND, cond_jump_flag }, 0 },
1918 { "jnoH", { Jb, BND, cond_jump_flag }, 0 },
1919 { "jbH", { Jb, BND, cond_jump_flag }, 0 },
1920 { "jaeH", { Jb, BND, cond_jump_flag }, 0 },
1921 { "jeH", { Jb, BND, cond_jump_flag }, 0 },
1922 { "jneH", { Jb, BND, cond_jump_flag }, 0 },
1923 { "jbeH", { Jb, BND, cond_jump_flag }, 0 },
1924 { "jaH", { Jb, BND, cond_jump_flag }, 0 },
1925 /* 78 */
1926 { "jsH", { Jb, BND, cond_jump_flag }, 0 },
1927 { "jnsH", { Jb, BND, cond_jump_flag }, 0 },
1928 { "jpH", { Jb, BND, cond_jump_flag }, 0 },
1929 { "jnpH", { Jb, BND, cond_jump_flag }, 0 },
1930 { "jlH", { Jb, BND, cond_jump_flag }, 0 },
1931 { "jgeH", { Jb, BND, cond_jump_flag }, 0 },
1932 { "jleH", { Jb, BND, cond_jump_flag }, 0 },
1933 { "jgH", { Jb, BND, cond_jump_flag }, 0 },
1934 /* 80 */
1935 { REG_TABLE (REG_80) },
1936 { REG_TABLE (REG_81) },
1937 { X86_64_TABLE (X86_64_82) },
1938 { REG_TABLE (REG_83) },
1939 { "testB", { Eb, Gb }, 0 },
1940 { "testS", { Ev, Gv }, 0 },
1941 { "xchgB", { Ebh2, Gb }, 0 },
1942 { "xchgS", { Evh2, Gv }, 0 },
1943 /* 88 */
1944 { "movB", { Ebh3, Gb }, 0 },
1945 { "movS", { Evh3, Gv }, 0 },
1946 { "movB", { Gb, EbS }, 0 },
1947 { "movS", { Gv, EvS }, 0 },
1948 { "movD", { Sv, Sw }, 0 },
1949 { MOD_TABLE (MOD_8D) },
1950 { "movD", { Sw, Sv }, 0 },
1951 { REG_TABLE (REG_8F) },
1952 /* 90 */
1953 { PREFIX_TABLE (PREFIX_90) },
1954 { "xchgS", { RMeCX, eAX }, 0 },
1955 { "xchgS", { RMeDX, eAX }, 0 },
1956 { "xchgS", { RMeBX, eAX }, 0 },
1957 { "xchgS", { RMeSP, eAX }, 0 },
1958 { "xchgS", { RMeBP, eAX }, 0 },
1959 { "xchgS", { RMeSI, eAX }, 0 },
1960 { "xchgS", { RMeDI, eAX }, 0 },
1961 /* 98 */
1962 { "cW{t|}R", { XX }, 0 },
1963 { "cR{t|}O", { XX }, 0 },
1964 { X86_64_TABLE (X86_64_9A) },
1965 { Bad_Opcode }, /* fwait */
1966 { "pushfT", { XX }, 0 },
1967 { "popfT", { XX }, 0 },
1968 { "sahf", { XX }, 0 },
1969 { "lahf", { XX }, 0 },
1970 /* a0 */
1971 { "mov%LB", { AL, Ob }, 0 },
1972 { "mov%LS", { eAX, Ov }, 0 },
1973 { "mov%LB", { Ob, AL }, 0 },
1974 { "mov%LS", { Ov, eAX }, 0 },
1975 { "movs{b|}", { Ybr, Xb }, 0 },
1976 { "movs{R|}", { Yvr, Xv }, 0 },
1977 { "cmps{b|}", { Xb, Yb }, 0 },
1978 { "cmps{R|}", { Xv, Yv }, 0 },
1979 /* a8 */
1980 { "testB", { AL, Ib }, 0 },
1981 { "testS", { eAX, Iv }, 0 },
1982 { "stosB", { Ybr, AL }, 0 },
1983 { "stosS", { Yvr, eAX }, 0 },
1984 { "lodsB", { ALr, Xb }, 0 },
1985 { "lodsS", { eAXr, Xv }, 0 },
1986 { "scasB", { AL, Yb }, 0 },
1987 { "scasS", { eAX, Yv }, 0 },
1988 /* b0 */
1989 { "movB", { RMAL, Ib }, 0 },
1990 { "movB", { RMCL, Ib }, 0 },
1991 { "movB", { RMDL, Ib }, 0 },
1992 { "movB", { RMBL, Ib }, 0 },
1993 { "movB", { RMAH, Ib }, 0 },
1994 { "movB", { RMCH, Ib }, 0 },
1995 { "movB", { RMDH, Ib }, 0 },
1996 { "movB", { RMBH, Ib }, 0 },
1997 /* b8 */
1998 { "mov%LV", { RMeAX, Iv64 }, 0 },
1999 { "mov%LV", { RMeCX, Iv64 }, 0 },
2000 { "mov%LV", { RMeDX, Iv64 }, 0 },
2001 { "mov%LV", { RMeBX, Iv64 }, 0 },
2002 { "mov%LV", { RMeSP, Iv64 }, 0 },
2003 { "mov%LV", { RMeBP, Iv64 }, 0 },
2004 { "mov%LV", { RMeSI, Iv64 }, 0 },
2005 { "mov%LV", { RMeDI, Iv64 }, 0 },
2006 /* c0 */
2007 { REG_TABLE (REG_C0) },
2008 { REG_TABLE (REG_C1) },
2009 { X86_64_TABLE (X86_64_C2) },
2010 { X86_64_TABLE (X86_64_C3) },
2011 { X86_64_TABLE (X86_64_C4) },
2012 { X86_64_TABLE (X86_64_C5) },
2013 { REG_TABLE (REG_C6) },
2014 { REG_TABLE (REG_C7) },
2015 /* c8 */
2016 { "enterT", { Iw, Ib }, 0 },
2017 { "leaveT", { XX }, 0 },
2018 { "{l|}ret{|f}P", { Iw }, 0 },
2019 { "{l|}ret{|f}P", { XX }, 0 },
2020 { "int3", { XX }, 0 },
2021 { "int", { Ib }, 0 },
2022 { X86_64_TABLE (X86_64_CE) },
2023 { "iret%LP", { XX }, 0 },
2024 /* d0 */
2025 { REG_TABLE (REG_D0) },
2026 { REG_TABLE (REG_D1) },
2027 { REG_TABLE (REG_D2) },
2028 { REG_TABLE (REG_D3) },
2029 { X86_64_TABLE (X86_64_D4) },
2030 { X86_64_TABLE (X86_64_D5) },
2031 { Bad_Opcode },
2032 { "xlat", { DSBX }, 0 },
2033 /* d8 */
2034 { FLOAT },
2035 { FLOAT },
2036 { FLOAT },
2037 { FLOAT },
2038 { FLOAT },
2039 { FLOAT },
2040 { FLOAT },
2041 { FLOAT },
2042 /* e0 */
2043 { "loopneFH", { Jb, XX, loop_jcxz_flag }, 0 },
2044 { "loopeFH", { Jb, XX, loop_jcxz_flag }, 0 },
2045 { "loopFH", { Jb, XX, loop_jcxz_flag }, 0 },
2046 { "jEcxzH", { Jb, XX, loop_jcxz_flag }, 0 },
2047 { "inB", { AL, Ib }, 0 },
2048 { "inG", { zAX, Ib }, 0 },
2049 { "outB", { Ib, AL }, 0 },
2050 { "outG", { Ib, zAX }, 0 },
2051 /* e8 */
2052 { X86_64_TABLE (X86_64_E8) },
2053 { X86_64_TABLE (X86_64_E9) },
2054 { X86_64_TABLE (X86_64_EA) },
2055 { "jmp", { Jb, BND }, 0 },
2056 { "inB", { AL, indirDX }, 0 },
2057 { "inG", { zAX, indirDX }, 0 },
2058 { "outB", { indirDX, AL }, 0 },
2059 { "outG", { indirDX, zAX }, 0 },
2060 /* f0 */
2061 { Bad_Opcode }, /* lock prefix */
2062 { "icebp", { XX }, 0 },
2063 { Bad_Opcode }, /* repne */
2064 { Bad_Opcode }, /* repz */
2065 { "hlt", { XX }, 0 },
2066 { "cmc", { XX }, 0 },
2067 { REG_TABLE (REG_F6) },
2068 { REG_TABLE (REG_F7) },
2069 /* f8 */
2070 { "clc", { XX }, 0 },
2071 { "stc", { XX }, 0 },
2072 { "cli", { XX }, 0 },
2073 { "sti", { XX }, 0 },
2074 { "cld", { XX }, 0 },
2075 { "std", { XX }, 0 },
2076 { REG_TABLE (REG_FE) },
2077 { REG_TABLE (REG_FF) },
2078 };
2079
2080 static const struct dis386 dis386_twobyte[] = {
2081 /* 00 */
2082 { REG_TABLE (REG_0F00 ) },
2083 { REG_TABLE (REG_0F01 ) },
2084 { "larS", { Gv, Ew }, 0 },
2085 { "lslS", { Gv, Ew }, 0 },
2086 { Bad_Opcode },
2087 { "syscall", { XX }, 0 },
2088 { "clts", { XX }, 0 },
2089 { "sysret%LQ", { XX }, 0 },
2090 /* 08 */
2091 { "invd", { XX }, 0 },
2092 { PREFIX_TABLE (PREFIX_0F09) },
2093 { Bad_Opcode },
2094 { "ud2", { XX }, 0 },
2095 { Bad_Opcode },
2096 { REG_TABLE (REG_0F0D) },
2097 { "femms", { XX }, 0 },
2098 { "", { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix. */
2099 /* 10 */
2100 { PREFIX_TABLE (PREFIX_0F10) },
2101 { PREFIX_TABLE (PREFIX_0F11) },
2102 { PREFIX_TABLE (PREFIX_0F12) },
2103 { MOD_TABLE (MOD_0F13) },
2104 { "unpcklpX", { XM, EXx }, PREFIX_OPCODE },
2105 { "unpckhpX", { XM, EXx }, PREFIX_OPCODE },
2106 { PREFIX_TABLE (PREFIX_0F16) },
2107 { MOD_TABLE (MOD_0F17) },
2108 /* 18 */
2109 { REG_TABLE (REG_0F18) },
2110 { "nopQ", { Ev }, 0 },
2111 { PREFIX_TABLE (PREFIX_0F1A) },
2112 { PREFIX_TABLE (PREFIX_0F1B) },
2113 { PREFIX_TABLE (PREFIX_0F1C) },
2114 { "nopQ", { Ev }, 0 },
2115 { PREFIX_TABLE (PREFIX_0F1E) },
2116 { "nopQ", { Ev }, 0 },
2117 /* 20 */
2118 { "movZ", { Rm, Cm }, 0 },
2119 { "movZ", { Rm, Dm }, 0 },
2120 { "movZ", { Cm, Rm }, 0 },
2121 { "movZ", { Dm, Rm }, 0 },
2122 { MOD_TABLE (MOD_0F24) },
2123 { Bad_Opcode },
2124 { MOD_TABLE (MOD_0F26) },
2125 { Bad_Opcode },
2126 /* 28 */
2127 { "movapX", { XM, EXx }, PREFIX_OPCODE },
2128 { "movapX", { EXxS, XM }, PREFIX_OPCODE },
2129 { PREFIX_TABLE (PREFIX_0F2A) },
2130 { PREFIX_TABLE (PREFIX_0F2B) },
2131 { PREFIX_TABLE (PREFIX_0F2C) },
2132 { PREFIX_TABLE (PREFIX_0F2D) },
2133 { PREFIX_TABLE (PREFIX_0F2E) },
2134 { PREFIX_TABLE (PREFIX_0F2F) },
2135 /* 30 */
2136 { "wrmsr", { XX }, 0 },
2137 { "rdtsc", { XX }, 0 },
2138 { "rdmsr", { XX }, 0 },
2139 { "rdpmc", { XX }, 0 },
2140 { "sysenter", { SEP }, 0 },
2141 { "sysexit", { SEP }, 0 },
2142 { Bad_Opcode },
2143 { "getsec", { XX }, 0 },
2144 /* 38 */
2145 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2146 { Bad_Opcode },
2147 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2148 { Bad_Opcode },
2149 { Bad_Opcode },
2150 { Bad_Opcode },
2151 { Bad_Opcode },
2152 { Bad_Opcode },
2153 /* 40 */
2154 { "cmovoS", { Gv, Ev }, 0 },
2155 { "cmovnoS", { Gv, Ev }, 0 },
2156 { "cmovbS", { Gv, Ev }, 0 },
2157 { "cmovaeS", { Gv, Ev }, 0 },
2158 { "cmoveS", { Gv, Ev }, 0 },
2159 { "cmovneS", { Gv, Ev }, 0 },
2160 { "cmovbeS", { Gv, Ev }, 0 },
2161 { "cmovaS", { Gv, Ev }, 0 },
2162 /* 48 */
2163 { "cmovsS", { Gv, Ev }, 0 },
2164 { "cmovnsS", { Gv, Ev }, 0 },
2165 { "cmovpS", { Gv, Ev }, 0 },
2166 { "cmovnpS", { Gv, Ev }, 0 },
2167 { "cmovlS", { Gv, Ev }, 0 },
2168 { "cmovgeS", { Gv, Ev }, 0 },
2169 { "cmovleS", { Gv, Ev }, 0 },
2170 { "cmovgS", { Gv, Ev }, 0 },
2171 /* 50 */
2172 { MOD_TABLE (MOD_0F50) },
2173 { PREFIX_TABLE (PREFIX_0F51) },
2174 { PREFIX_TABLE (PREFIX_0F52) },
2175 { PREFIX_TABLE (PREFIX_0F53) },
2176 { "andpX", { XM, EXx }, PREFIX_OPCODE },
2177 { "andnpX", { XM, EXx }, PREFIX_OPCODE },
2178 { "orpX", { XM, EXx }, PREFIX_OPCODE },
2179 { "xorpX", { XM, EXx }, PREFIX_OPCODE },
2180 /* 58 */
2181 { PREFIX_TABLE (PREFIX_0F58) },
2182 { PREFIX_TABLE (PREFIX_0F59) },
2183 { PREFIX_TABLE (PREFIX_0F5A) },
2184 { PREFIX_TABLE (PREFIX_0F5B) },
2185 { PREFIX_TABLE (PREFIX_0F5C) },
2186 { PREFIX_TABLE (PREFIX_0F5D) },
2187 { PREFIX_TABLE (PREFIX_0F5E) },
2188 { PREFIX_TABLE (PREFIX_0F5F) },
2189 /* 60 */
2190 { PREFIX_TABLE (PREFIX_0F60) },
2191 { PREFIX_TABLE (PREFIX_0F61) },
2192 { PREFIX_TABLE (PREFIX_0F62) },
2193 { "packsswb", { MX, EM }, PREFIX_OPCODE },
2194 { "pcmpgtb", { MX, EM }, PREFIX_OPCODE },
2195 { "pcmpgtw", { MX, EM }, PREFIX_OPCODE },
2196 { "pcmpgtd", { MX, EM }, PREFIX_OPCODE },
2197 { "packuswb", { MX, EM }, PREFIX_OPCODE },
2198 /* 68 */
2199 { "punpckhbw", { MX, EM }, PREFIX_OPCODE },
2200 { "punpckhwd", { MX, EM }, PREFIX_OPCODE },
2201 { "punpckhdq", { MX, EM }, PREFIX_OPCODE },
2202 { "packssdw", { MX, EM }, PREFIX_OPCODE },
2203 { "punpcklqdq", { XM, EXx }, PREFIX_DATA },
2204 { "punpckhqdq", { XM, EXx }, PREFIX_DATA },
2205 { "movK", { MX, Edq }, PREFIX_OPCODE },
2206 { PREFIX_TABLE (PREFIX_0F6F) },
2207 /* 70 */
2208 { PREFIX_TABLE (PREFIX_0F70) },
2209 { REG_TABLE (REG_0F71) },
2210 { REG_TABLE (REG_0F72) },
2211 { REG_TABLE (REG_0F73) },
2212 { "pcmpeqb", { MX, EM }, PREFIX_OPCODE },
2213 { "pcmpeqw", { MX, EM }, PREFIX_OPCODE },
2214 { "pcmpeqd", { MX, EM }, PREFIX_OPCODE },
2215 { "emms", { XX }, PREFIX_OPCODE },
2216 /* 78 */
2217 { PREFIX_TABLE (PREFIX_0F78) },
2218 { PREFIX_TABLE (PREFIX_0F79) },
2219 { Bad_Opcode },
2220 { Bad_Opcode },
2221 { PREFIX_TABLE (PREFIX_0F7C) },
2222 { PREFIX_TABLE (PREFIX_0F7D) },
2223 { PREFIX_TABLE (PREFIX_0F7E) },
2224 { PREFIX_TABLE (PREFIX_0F7F) },
2225 /* 80 */
2226 { "joH", { Jv, BND, cond_jump_flag }, 0 },
2227 { "jnoH", { Jv, BND, cond_jump_flag }, 0 },
2228 { "jbH", { Jv, BND, cond_jump_flag }, 0 },
2229 { "jaeH", { Jv, BND, cond_jump_flag }, 0 },
2230 { "jeH", { Jv, BND, cond_jump_flag }, 0 },
2231 { "jneH", { Jv, BND, cond_jump_flag }, 0 },
2232 { "jbeH", { Jv, BND, cond_jump_flag }, 0 },
2233 { "jaH", { Jv, BND, cond_jump_flag }, 0 },
2234 /* 88 */
2235 { "jsH", { Jv, BND, cond_jump_flag }, 0 },
2236 { "jnsH", { Jv, BND, cond_jump_flag }, 0 },
2237 { "jpH", { Jv, BND, cond_jump_flag }, 0 },
2238 { "jnpH", { Jv, BND, cond_jump_flag }, 0 },
2239 { "jlH", { Jv, BND, cond_jump_flag }, 0 },
2240 { "jgeH", { Jv, BND, cond_jump_flag }, 0 },
2241 { "jleH", { Jv, BND, cond_jump_flag }, 0 },
2242 { "jgH", { Jv, BND, cond_jump_flag }, 0 },
2243 /* 90 */
2244 { "seto", { Eb }, 0 },
2245 { "setno", { Eb }, 0 },
2246 { "setb", { Eb }, 0 },
2247 { "setae", { Eb }, 0 },
2248 { "sete", { Eb }, 0 },
2249 { "setne", { Eb }, 0 },
2250 { "setbe", { Eb }, 0 },
2251 { "seta", { Eb }, 0 },
2252 /* 98 */
2253 { "sets", { Eb }, 0 },
2254 { "setns", { Eb }, 0 },
2255 { "setp", { Eb }, 0 },
2256 { "setnp", { Eb }, 0 },
2257 { "setl", { Eb }, 0 },
2258 { "setge", { Eb }, 0 },
2259 { "setle", { Eb }, 0 },
2260 { "setg", { Eb }, 0 },
2261 /* a0 */
2262 { "pushT", { fs }, 0 },
2263 { "popT", { fs }, 0 },
2264 { "cpuid", { XX }, 0 },
2265 { "btS", { Ev, Gv }, 0 },
2266 { "shldS", { Ev, Gv, Ib }, 0 },
2267 { "shldS", { Ev, Gv, CL }, 0 },
2268 { REG_TABLE (REG_0FA6) },
2269 { REG_TABLE (REG_0FA7) },
2270 /* a8 */
2271 { "pushT", { gs }, 0 },
2272 { "popT", { gs }, 0 },
2273 { "rsm", { XX }, 0 },
2274 { "btsS", { Evh1, Gv }, 0 },
2275 { "shrdS", { Ev, Gv, Ib }, 0 },
2276 { "shrdS", { Ev, Gv, CL }, 0 },
2277 { REG_TABLE (REG_0FAE) },
2278 { "imulS", { Gv, Ev }, 0 },
2279 /* b0 */
2280 { "cmpxchgB", { Ebh1, Gb }, 0 },
2281 { "cmpxchgS", { Evh1, Gv }, 0 },
2282 { MOD_TABLE (MOD_0FB2) },
2283 { "btrS", { Evh1, Gv }, 0 },
2284 { MOD_TABLE (MOD_0FB4) },
2285 { MOD_TABLE (MOD_0FB5) },
2286 { "movz{bR|x}", { Gv, Eb }, 0 },
2287 { "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2288 /* b8 */
2289 { PREFIX_TABLE (PREFIX_0FB8) },
2290 { "ud1S", { Gv, Ev }, 0 },
2291 { REG_TABLE (REG_0FBA) },
2292 { "btcS", { Evh1, Gv }, 0 },
2293 { PREFIX_TABLE (PREFIX_0FBC) },
2294 { PREFIX_TABLE (PREFIX_0FBD) },
2295 { "movs{bR|x}", { Gv, Eb }, 0 },
2296 { "movs{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2297 /* c0 */
2298 { "xaddB", { Ebh1, Gb }, 0 },
2299 { "xaddS", { Evh1, Gv }, 0 },
2300 { PREFIX_TABLE (PREFIX_0FC2) },
2301 { MOD_TABLE (MOD_0FC3) },
2302 { "pinsrw", { MX, Edqw, Ib }, PREFIX_OPCODE },
2303 { "pextrw", { Gdq, MS, Ib }, PREFIX_OPCODE },
2304 { "shufpX", { XM, EXx, Ib }, PREFIX_OPCODE },
2305 { REG_TABLE (REG_0FC7) },
2306 /* c8 */
2307 { "bswap", { RMeAX }, 0 },
2308 { "bswap", { RMeCX }, 0 },
2309 { "bswap", { RMeDX }, 0 },
2310 { "bswap", { RMeBX }, 0 },
2311 { "bswap", { RMeSP }, 0 },
2312 { "bswap", { RMeBP }, 0 },
2313 { "bswap", { RMeSI }, 0 },
2314 { "bswap", { RMeDI }, 0 },
2315 /* d0 */
2316 { PREFIX_TABLE (PREFIX_0FD0) },
2317 { "psrlw", { MX, EM }, PREFIX_OPCODE },
2318 { "psrld", { MX, EM }, PREFIX_OPCODE },
2319 { "psrlq", { MX, EM }, PREFIX_OPCODE },
2320 { "paddq", { MX, EM }, PREFIX_OPCODE },
2321 { "pmullw", { MX, EM }, PREFIX_OPCODE },
2322 { PREFIX_TABLE (PREFIX_0FD6) },
2323 { MOD_TABLE (MOD_0FD7) },
2324 /* d8 */
2325 { "psubusb", { MX, EM }, PREFIX_OPCODE },
2326 { "psubusw", { MX, EM }, PREFIX_OPCODE },
2327 { "pminub", { MX, EM }, PREFIX_OPCODE },
2328 { "pand", { MX, EM }, PREFIX_OPCODE },
2329 { "paddusb", { MX, EM }, PREFIX_OPCODE },
2330 { "paddusw", { MX, EM }, PREFIX_OPCODE },
2331 { "pmaxub", { MX, EM }, PREFIX_OPCODE },
2332 { "pandn", { MX, EM }, PREFIX_OPCODE },
2333 /* e0 */
2334 { "pavgb", { MX, EM }, PREFIX_OPCODE },
2335 { "psraw", { MX, EM }, PREFIX_OPCODE },
2336 { "psrad", { MX, EM }, PREFIX_OPCODE },
2337 { "pavgw", { MX, EM }, PREFIX_OPCODE },
2338 { "pmulhuw", { MX, EM }, PREFIX_OPCODE },
2339 { "pmulhw", { MX, EM }, PREFIX_OPCODE },
2340 { PREFIX_TABLE (PREFIX_0FE6) },
2341 { PREFIX_TABLE (PREFIX_0FE7) },
2342 /* e8 */
2343 { "psubsb", { MX, EM }, PREFIX_OPCODE },
2344 { "psubsw", { MX, EM }, PREFIX_OPCODE },
2345 { "pminsw", { MX, EM }, PREFIX_OPCODE },
2346 { "por", { MX, EM }, PREFIX_OPCODE },
2347 { "paddsb", { MX, EM }, PREFIX_OPCODE },
2348 { "paddsw", { MX, EM }, PREFIX_OPCODE },
2349 { "pmaxsw", { MX, EM }, PREFIX_OPCODE },
2350 { "pxor", { MX, EM }, PREFIX_OPCODE },
2351 /* f0 */
2352 { PREFIX_TABLE (PREFIX_0FF0) },
2353 { "psllw", { MX, EM }, PREFIX_OPCODE },
2354 { "pslld", { MX, EM }, PREFIX_OPCODE },
2355 { "psllq", { MX, EM }, PREFIX_OPCODE },
2356 { "pmuludq", { MX, EM }, PREFIX_OPCODE },
2357 { "pmaddwd", { MX, EM }, PREFIX_OPCODE },
2358 { "psadbw", { MX, EM }, PREFIX_OPCODE },
2359 { PREFIX_TABLE (PREFIX_0FF7) },
2360 /* f8 */
2361 { "psubb", { MX, EM }, PREFIX_OPCODE },
2362 { "psubw", { MX, EM }, PREFIX_OPCODE },
2363 { "psubd", { MX, EM }, PREFIX_OPCODE },
2364 { "psubq", { MX, EM }, PREFIX_OPCODE },
2365 { "paddb", { MX, EM }, PREFIX_OPCODE },
2366 { "paddw", { MX, EM }, PREFIX_OPCODE },
2367 { "paddd", { MX, EM }, PREFIX_OPCODE },
2368 { "ud0S", { Gv, Ev }, 0 },
2369 };
2370
2371 static const unsigned char onebyte_has_modrm[256] = {
2372 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2373 /* ------------------------------- */
2374 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2375 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2376 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2377 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2378 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2379 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2380 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2381 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2382 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2383 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2384 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2385 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2386 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2387 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2388 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2389 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2390 /* ------------------------------- */
2391 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2392 };
2393
2394 static const unsigned char twobyte_has_modrm[256] = {
2395 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2396 /* ------------------------------- */
2397 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2398 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2399 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2400 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2401 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2402 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2403 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2404 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2405 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2406 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2407 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2408 /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2409 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2410 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2411 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2412 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */
2413 /* ------------------------------- */
2414 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2415 };
2416
2417 static char obuf[100];
2418 static char *obufp;
2419 static char *mnemonicendp;
2420 static char scratchbuf[100];
2421 static unsigned char *start_codep;
2422 static unsigned char *insn_codep;
2423 static unsigned char *codep;
2424 static unsigned char *end_codep;
2425 static int last_lock_prefix;
2426 static int last_repz_prefix;
2427 static int last_repnz_prefix;
2428 static int last_data_prefix;
2429 static int last_addr_prefix;
2430 static int last_rex_prefix;
2431 static int last_seg_prefix;
2432 static int fwait_prefix;
2433 /* The active segment register prefix. */
2434 static int active_seg_prefix;
2435 #define MAX_CODE_LENGTH 15
2436 /* We can up to 14 prefixes since the maximum instruction length is
2437 15bytes. */
2438 static int all_prefixes[MAX_CODE_LENGTH - 1];
2439 static disassemble_info *the_info;
2440 static struct
2441 {
2442 int mod;
2443 int reg;
2444 int rm;
2445 }
2446 modrm;
2447 static unsigned char need_modrm;
2448 static struct
2449 {
2450 int scale;
2451 int index;
2452 int base;
2453 }
2454 sib;
2455 static struct
2456 {
2457 int register_specifier;
2458 int length;
2459 int prefix;
2460 int w;
2461 int evex;
2462 int r;
2463 int v;
2464 int mask_register_specifier;
2465 int zeroing;
2466 int ll;
2467 int b;
2468 }
2469 vex;
2470 static unsigned char need_vex;
2471
2472 struct op
2473 {
2474 const char *name;
2475 unsigned int len;
2476 };
2477
2478 /* If we are accessing mod/rm/reg without need_modrm set, then the
2479 values are stale. Hitting this abort likely indicates that you
2480 need to update onebyte_has_modrm or twobyte_has_modrm. */
2481 #define MODRM_CHECK if (!need_modrm) abort ()
2482
2483 static const char **names64;
2484 static const char **names32;
2485 static const char **names16;
2486 static const char **names8;
2487 static const char **names8rex;
2488 static const char **names_seg;
2489 static const char *index64;
2490 static const char *index32;
2491 static const char **index16;
2492 static const char **names_bnd;
2493
2494 static const char *intel_names64[] = {
2495 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2496 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2497 };
2498 static const char *intel_names32[] = {
2499 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2500 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2501 };
2502 static const char *intel_names16[] = {
2503 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2504 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2505 };
2506 static const char *intel_names8[] = {
2507 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2508 };
2509 static const char *intel_names8rex[] = {
2510 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2511 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2512 };
2513 static const char *intel_names_seg[] = {
2514 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2515 };
2516 static const char *intel_index64 = "riz";
2517 static const char *intel_index32 = "eiz";
2518 static const char *intel_index16[] = {
2519 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2520 };
2521
2522 static const char *att_names64[] = {
2523 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2524 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2525 };
2526 static const char *att_names32[] = {
2527 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2528 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2529 };
2530 static const char *att_names16[] = {
2531 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2532 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2533 };
2534 static const char *att_names8[] = {
2535 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2536 };
2537 static const char *att_names8rex[] = {
2538 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2539 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2540 };
2541 static const char *att_names_seg[] = {
2542 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2543 };
2544 static const char *att_index64 = "%riz";
2545 static const char *att_index32 = "%eiz";
2546 static const char *att_index16[] = {
2547 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2548 };
2549
2550 static const char **names_mm;
2551 static const char *intel_names_mm[] = {
2552 "mm0", "mm1", "mm2", "mm3",
2553 "mm4", "mm5", "mm6", "mm7"
2554 };
2555 static const char *att_names_mm[] = {
2556 "%mm0", "%mm1", "%mm2", "%mm3",
2557 "%mm4", "%mm5", "%mm6", "%mm7"
2558 };
2559
2560 static const char *intel_names_bnd[] = {
2561 "bnd0", "bnd1", "bnd2", "bnd3"
2562 };
2563
2564 static const char *att_names_bnd[] = {
2565 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
2566 };
2567
2568 static const char **names_xmm;
2569 static const char *intel_names_xmm[] = {
2570 "xmm0", "xmm1", "xmm2", "xmm3",
2571 "xmm4", "xmm5", "xmm6", "xmm7",
2572 "xmm8", "xmm9", "xmm10", "xmm11",
2573 "xmm12", "xmm13", "xmm14", "xmm15",
2574 "xmm16", "xmm17", "xmm18", "xmm19",
2575 "xmm20", "xmm21", "xmm22", "xmm23",
2576 "xmm24", "xmm25", "xmm26", "xmm27",
2577 "xmm28", "xmm29", "xmm30", "xmm31"
2578 };
2579 static const char *att_names_xmm[] = {
2580 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2581 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2582 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2583 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
2584 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
2585 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
2586 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
2587 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
2588 };
2589
2590 static const char **names_ymm;
2591 static const char *intel_names_ymm[] = {
2592 "ymm0", "ymm1", "ymm2", "ymm3",
2593 "ymm4", "ymm5", "ymm6", "ymm7",
2594 "ymm8", "ymm9", "ymm10", "ymm11",
2595 "ymm12", "ymm13", "ymm14", "ymm15",
2596 "ymm16", "ymm17", "ymm18", "ymm19",
2597 "ymm20", "ymm21", "ymm22", "ymm23",
2598 "ymm24", "ymm25", "ymm26", "ymm27",
2599 "ymm28", "ymm29", "ymm30", "ymm31"
2600 };
2601 static const char *att_names_ymm[] = {
2602 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2603 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2604 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2605 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
2606 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
2607 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
2608 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
2609 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
2610 };
2611
2612 static const char **names_zmm;
2613 static const char *intel_names_zmm[] = {
2614 "zmm0", "zmm1", "zmm2", "zmm3",
2615 "zmm4", "zmm5", "zmm6", "zmm7",
2616 "zmm8", "zmm9", "zmm10", "zmm11",
2617 "zmm12", "zmm13", "zmm14", "zmm15",
2618 "zmm16", "zmm17", "zmm18", "zmm19",
2619 "zmm20", "zmm21", "zmm22", "zmm23",
2620 "zmm24", "zmm25", "zmm26", "zmm27",
2621 "zmm28", "zmm29", "zmm30", "zmm31"
2622 };
2623 static const char *att_names_zmm[] = {
2624 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
2625 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
2626 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
2627 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
2628 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
2629 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
2630 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
2631 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
2632 };
2633
2634 static const char **names_tmm;
2635 static const char *intel_names_tmm[] = {
2636 "tmm0", "tmm1", "tmm2", "tmm3",
2637 "tmm4", "tmm5", "tmm6", "tmm7"
2638 };
2639 static const char *att_names_tmm[] = {
2640 "%tmm0", "%tmm1", "%tmm2", "%tmm3",
2641 "%tmm4", "%tmm5", "%tmm6", "%tmm7"
2642 };
2643
2644 static const char **names_mask;
2645 static const char *intel_names_mask[] = {
2646 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
2647 };
2648 static const char *att_names_mask[] = {
2649 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
2650 };
2651
2652 static const char *names_rounding[] =
2653 {
2654 "{rn-sae}",
2655 "{rd-sae}",
2656 "{ru-sae}",
2657 "{rz-sae}"
2658 };
2659
2660 static const struct dis386 reg_table[][8] = {
2661 /* REG_80 */
2662 {
2663 { "addA", { Ebh1, Ib }, 0 },
2664 { "orA", { Ebh1, Ib }, 0 },
2665 { "adcA", { Ebh1, Ib }, 0 },
2666 { "sbbA", { Ebh1, Ib }, 0 },
2667 { "andA", { Ebh1, Ib }, 0 },
2668 { "subA", { Ebh1, Ib }, 0 },
2669 { "xorA", { Ebh1, Ib }, 0 },
2670 { "cmpA", { Eb, Ib }, 0 },
2671 },
2672 /* REG_81 */
2673 {
2674 { "addQ", { Evh1, Iv }, 0 },
2675 { "orQ", { Evh1, Iv }, 0 },
2676 { "adcQ", { Evh1, Iv }, 0 },
2677 { "sbbQ", { Evh1, Iv }, 0 },
2678 { "andQ", { Evh1, Iv }, 0 },
2679 { "subQ", { Evh1, Iv }, 0 },
2680 { "xorQ", { Evh1, Iv }, 0 },
2681 { "cmpQ", { Ev, Iv }, 0 },
2682 },
2683 /* REG_83 */
2684 {
2685 { "addQ", { Evh1, sIb }, 0 },
2686 { "orQ", { Evh1, sIb }, 0 },
2687 { "adcQ", { Evh1, sIb }, 0 },
2688 { "sbbQ", { Evh1, sIb }, 0 },
2689 { "andQ", { Evh1, sIb }, 0 },
2690 { "subQ", { Evh1, sIb }, 0 },
2691 { "xorQ", { Evh1, sIb }, 0 },
2692 { "cmpQ", { Ev, sIb }, 0 },
2693 },
2694 /* REG_8F */
2695 {
2696 { "popU", { stackEv }, 0 },
2697 { XOP_8F_TABLE (XOP_09) },
2698 { Bad_Opcode },
2699 { Bad_Opcode },
2700 { Bad_Opcode },
2701 { XOP_8F_TABLE (XOP_09) },
2702 },
2703 /* REG_C0 */
2704 {
2705 { "rolA", { Eb, Ib }, 0 },
2706 { "rorA", { Eb, Ib }, 0 },
2707 { "rclA", { Eb, Ib }, 0 },
2708 { "rcrA", { Eb, Ib }, 0 },
2709 { "shlA", { Eb, Ib }, 0 },
2710 { "shrA", { Eb, Ib }, 0 },
2711 { "shlA", { Eb, Ib }, 0 },
2712 { "sarA", { Eb, Ib }, 0 },
2713 },
2714 /* REG_C1 */
2715 {
2716 { "rolQ", { Ev, Ib }, 0 },
2717 { "rorQ", { Ev, Ib }, 0 },
2718 { "rclQ", { Ev, Ib }, 0 },
2719 { "rcrQ", { Ev, Ib }, 0 },
2720 { "shlQ", { Ev, Ib }, 0 },
2721 { "shrQ", { Ev, Ib }, 0 },
2722 { "shlQ", { Ev, Ib }, 0 },
2723 { "sarQ", { Ev, Ib }, 0 },
2724 },
2725 /* REG_C6 */
2726 {
2727 { "movA", { Ebh3, Ib }, 0 },
2728 { Bad_Opcode },
2729 { Bad_Opcode },
2730 { Bad_Opcode },
2731 { Bad_Opcode },
2732 { Bad_Opcode },
2733 { Bad_Opcode },
2734 { MOD_TABLE (MOD_C6_REG_7) },
2735 },
2736 /* REG_C7 */
2737 {
2738 { "movQ", { Evh3, Iv }, 0 },
2739 { Bad_Opcode },
2740 { Bad_Opcode },
2741 { Bad_Opcode },
2742 { Bad_Opcode },
2743 { Bad_Opcode },
2744 { Bad_Opcode },
2745 { MOD_TABLE (MOD_C7_REG_7) },
2746 },
2747 /* REG_D0 */
2748 {
2749 { "rolA", { Eb, I1 }, 0 },
2750 { "rorA", { Eb, I1 }, 0 },
2751 { "rclA", { Eb, I1 }, 0 },
2752 { "rcrA", { Eb, I1 }, 0 },
2753 { "shlA", { Eb, I1 }, 0 },
2754 { "shrA", { Eb, I1 }, 0 },
2755 { "shlA", { Eb, I1 }, 0 },
2756 { "sarA", { Eb, I1 }, 0 },
2757 },
2758 /* REG_D1 */
2759 {
2760 { "rolQ", { Ev, I1 }, 0 },
2761 { "rorQ", { Ev, I1 }, 0 },
2762 { "rclQ", { Ev, I1 }, 0 },
2763 { "rcrQ", { Ev, I1 }, 0 },
2764 { "shlQ", { Ev, I1 }, 0 },
2765 { "shrQ", { Ev, I1 }, 0 },
2766 { "shlQ", { Ev, I1 }, 0 },
2767 { "sarQ", { Ev, I1 }, 0 },
2768 },
2769 /* REG_D2 */
2770 {
2771 { "rolA", { Eb, CL }, 0 },
2772 { "rorA", { Eb, CL }, 0 },
2773 { "rclA", { Eb, CL }, 0 },
2774 { "rcrA", { Eb, CL }, 0 },
2775 { "shlA", { Eb, CL }, 0 },
2776 { "shrA", { Eb, CL }, 0 },
2777 { "shlA", { Eb, CL }, 0 },
2778 { "sarA", { Eb, CL }, 0 },
2779 },
2780 /* REG_D3 */
2781 {
2782 { "rolQ", { Ev, CL }, 0 },
2783 { "rorQ", { Ev, CL }, 0 },
2784 { "rclQ", { Ev, CL }, 0 },
2785 { "rcrQ", { Ev, CL }, 0 },
2786 { "shlQ", { Ev, CL }, 0 },
2787 { "shrQ", { Ev, CL }, 0 },
2788 { "shlQ", { Ev, CL }, 0 },
2789 { "sarQ", { Ev, CL }, 0 },
2790 },
2791 /* REG_F6 */
2792 {
2793 { "testA", { Eb, Ib }, 0 },
2794 { "testA", { Eb, Ib }, 0 },
2795 { "notA", { Ebh1 }, 0 },
2796 { "negA", { Ebh1 }, 0 },
2797 { "mulA", { Eb }, 0 }, /* Don't print the implicit %al register, */
2798 { "imulA", { Eb }, 0 }, /* to distinguish these opcodes from other */
2799 { "divA", { Eb }, 0 }, /* mul/imul opcodes. Do the same for div */
2800 { "idivA", { Eb }, 0 }, /* and idiv for consistency. */
2801 },
2802 /* REG_F7 */
2803 {
2804 { "testQ", { Ev, Iv }, 0 },
2805 { "testQ", { Ev, Iv }, 0 },
2806 { "notQ", { Evh1 }, 0 },
2807 { "negQ", { Evh1 }, 0 },
2808 { "mulQ", { Ev }, 0 }, /* Don't print the implicit register. */
2809 { "imulQ", { Ev }, 0 },
2810 { "divQ", { Ev }, 0 },
2811 { "idivQ", { Ev }, 0 },
2812 },
2813 /* REG_FE */
2814 {
2815 { "incA", { Ebh1 }, 0 },
2816 { "decA", { Ebh1 }, 0 },
2817 },
2818 /* REG_FF */
2819 {
2820 { "incQ", { Evh1 }, 0 },
2821 { "decQ", { Evh1 }, 0 },
2822 { "call{&|}", { NOTRACK, indirEv, BND }, 0 },
2823 { MOD_TABLE (MOD_FF_REG_3) },
2824 { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 },
2825 { MOD_TABLE (MOD_FF_REG_5) },
2826 { "pushU", { stackEv }, 0 },
2827 { Bad_Opcode },
2828 },
2829 /* REG_0F00 */
2830 {
2831 { "sldtD", { Sv }, 0 },
2832 { "strD", { Sv }, 0 },
2833 { "lldt", { Ew }, 0 },
2834 { "ltr", { Ew }, 0 },
2835 { "verr", { Ew }, 0 },
2836 { "verw", { Ew }, 0 },
2837 { Bad_Opcode },
2838 { Bad_Opcode },
2839 },
2840 /* REG_0F01 */
2841 {
2842 { MOD_TABLE (MOD_0F01_REG_0) },
2843 { MOD_TABLE (MOD_0F01_REG_1) },
2844 { MOD_TABLE (MOD_0F01_REG_2) },
2845 { MOD_TABLE (MOD_0F01_REG_3) },
2846 { "smswD", { Sv }, 0 },
2847 { MOD_TABLE (MOD_0F01_REG_5) },
2848 { "lmsw", { Ew }, 0 },
2849 { MOD_TABLE (MOD_0F01_REG_7) },
2850 },
2851 /* REG_0F0D */
2852 {
2853 { "prefetch", { Mb }, 0 },
2854 { "prefetchw", { Mb }, 0 },
2855 { "prefetchwt1", { Mb }, 0 },
2856 { "prefetch", { Mb }, 0 },
2857 { "prefetch", { Mb }, 0 },
2858 { "prefetch", { Mb }, 0 },
2859 { "prefetch", { Mb }, 0 },
2860 { "prefetch", { Mb }, 0 },
2861 },
2862 /* REG_0F18 */
2863 {
2864 { MOD_TABLE (MOD_0F18_REG_0) },
2865 { MOD_TABLE (MOD_0F18_REG_1) },
2866 { MOD_TABLE (MOD_0F18_REG_2) },
2867 { MOD_TABLE (MOD_0F18_REG_3) },
2868 { MOD_TABLE (MOD_0F18_REG_4) },
2869 { MOD_TABLE (MOD_0F18_REG_5) },
2870 { MOD_TABLE (MOD_0F18_REG_6) },
2871 { MOD_TABLE (MOD_0F18_REG_7) },
2872 },
2873 /* REG_0F1C_P_0_MOD_0 */
2874 {
2875 { "cldemote", { Mb }, 0 },
2876 { "nopQ", { Ev }, 0 },
2877 { "nopQ", { Ev }, 0 },
2878 { "nopQ", { Ev }, 0 },
2879 { "nopQ", { Ev }, 0 },
2880 { "nopQ", { Ev }, 0 },
2881 { "nopQ", { Ev }, 0 },
2882 { "nopQ", { Ev }, 0 },
2883 },
2884 /* REG_0F1E_P_1_MOD_3 */
2885 {
2886 { "nopQ", { Ev }, 0 },
2887 { "rdsspK", { Rdq }, PREFIX_OPCODE },
2888 { "nopQ", { Ev }, 0 },
2889 { "nopQ", { Ev }, 0 },
2890 { "nopQ", { Ev }, 0 },
2891 { "nopQ", { Ev }, 0 },
2892 { "nopQ", { Ev }, 0 },
2893 { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) },
2894 },
2895 /* REG_0F71 */
2896 {
2897 { Bad_Opcode },
2898 { Bad_Opcode },
2899 { MOD_TABLE (MOD_0F71_REG_2) },
2900 { Bad_Opcode },
2901 { MOD_TABLE (MOD_0F71_REG_4) },
2902 { Bad_Opcode },
2903 { MOD_TABLE (MOD_0F71_REG_6) },
2904 },
2905 /* REG_0F72 */
2906 {
2907 { Bad_Opcode },
2908 { Bad_Opcode },
2909 { MOD_TABLE (MOD_0F72_REG_2) },
2910 { Bad_Opcode },
2911 { MOD_TABLE (MOD_0F72_REG_4) },
2912 { Bad_Opcode },
2913 { MOD_TABLE (MOD_0F72_REG_6) },
2914 },
2915 /* REG_0F73 */
2916 {
2917 { Bad_Opcode },
2918 { Bad_Opcode },
2919 { MOD_TABLE (MOD_0F73_REG_2) },
2920 { MOD_TABLE (MOD_0F73_REG_3) },
2921 { Bad_Opcode },
2922 { Bad_Opcode },
2923 { MOD_TABLE (MOD_0F73_REG_6) },
2924 { MOD_TABLE (MOD_0F73_REG_7) },
2925 },
2926 /* REG_0FA6 */
2927 {
2928 { "montmul", { { OP_0f07, 0 } }, 0 },
2929 { "xsha1", { { OP_0f07, 0 } }, 0 },
2930 { "xsha256", { { OP_0f07, 0 } }, 0 },
2931 },
2932 /* REG_0FA7 */
2933 {
2934 { "xstore-rng", { { OP_0f07, 0 } }, 0 },
2935 { "xcrypt-ecb", { { OP_0f07, 0 } }, 0 },
2936 { "xcrypt-cbc", { { OP_0f07, 0 } }, 0 },
2937 { "xcrypt-ctr", { { OP_0f07, 0 } }, 0 },
2938 { "xcrypt-cfb", { { OP_0f07, 0 } }, 0 },
2939 { "xcrypt-ofb", { { OP_0f07, 0 } }, 0 },
2940 },
2941 /* REG_0FAE */
2942 {
2943 { MOD_TABLE (MOD_0FAE_REG_0) },
2944 { MOD_TABLE (MOD_0FAE_REG_1) },
2945 { MOD_TABLE (MOD_0FAE_REG_2) },
2946 { MOD_TABLE (MOD_0FAE_REG_3) },
2947 { MOD_TABLE (MOD_0FAE_REG_4) },
2948 { MOD_TABLE (MOD_0FAE_REG_5) },
2949 { MOD_TABLE (MOD_0FAE_REG_6) },
2950 { MOD_TABLE (MOD_0FAE_REG_7) },
2951 },
2952 /* REG_0FBA */
2953 {
2954 { Bad_Opcode },
2955 { Bad_Opcode },
2956 { Bad_Opcode },
2957 { Bad_Opcode },
2958 { "btQ", { Ev, Ib }, 0 },
2959 { "btsQ", { Evh1, Ib }, 0 },
2960 { "btrQ", { Evh1, Ib }, 0 },
2961 { "btcQ", { Evh1, Ib }, 0 },
2962 },
2963 /* REG_0FC7 */
2964 {
2965 { Bad_Opcode },
2966 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
2967 { Bad_Opcode },
2968 { MOD_TABLE (MOD_0FC7_REG_3) },
2969 { MOD_TABLE (MOD_0FC7_REG_4) },
2970 { MOD_TABLE (MOD_0FC7_REG_5) },
2971 { MOD_TABLE (MOD_0FC7_REG_6) },
2972 { MOD_TABLE (MOD_0FC7_REG_7) },
2973 },
2974 /* REG_VEX_0F71 */
2975 {
2976 { Bad_Opcode },
2977 { Bad_Opcode },
2978 { MOD_TABLE (MOD_VEX_0F71_REG_2) },
2979 { Bad_Opcode },
2980 { MOD_TABLE (MOD_VEX_0F71_REG_4) },
2981 { Bad_Opcode },
2982 { MOD_TABLE (MOD_VEX_0F71_REG_6) },
2983 },
2984 /* REG_VEX_0F72 */
2985 {
2986 { Bad_Opcode },
2987 { Bad_Opcode },
2988 { MOD_TABLE (MOD_VEX_0F72_REG_2) },
2989 { Bad_Opcode },
2990 { MOD_TABLE (MOD_VEX_0F72_REG_4) },
2991 { Bad_Opcode },
2992 { MOD_TABLE (MOD_VEX_0F72_REG_6) },
2993 },
2994 /* REG_VEX_0F73 */
2995 {
2996 { Bad_Opcode },
2997 { Bad_Opcode },
2998 { MOD_TABLE (MOD_VEX_0F73_REG_2) },
2999 { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3000 { Bad_Opcode },
3001 { Bad_Opcode },
3002 { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3003 { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3004 },
3005 /* REG_VEX_0FAE */
3006 {
3007 { Bad_Opcode },
3008 { Bad_Opcode },
3009 { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3010 { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3011 },
3012 /* REG_VEX_0F3849_X86_64_P_0_W_0_M_1 */
3013 {
3014 { RM_TABLE (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0) },
3015 },
3016 /* REG_VEX_0F38F3 */
3017 {
3018 { Bad_Opcode },
3019 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1) },
3020 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2) },
3021 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3) },
3022 },
3023 /* REG_0FXOP_09_01_L_0 */
3024 {
3025 { Bad_Opcode },
3026 { "blcfill", { VexGdq, Edq }, 0 },
3027 { "blsfill", { VexGdq, Edq }, 0 },
3028 { "blcs", { VexGdq, Edq }, 0 },
3029 { "tzmsk", { VexGdq, Edq }, 0 },
3030 { "blcic", { VexGdq, Edq }, 0 },
3031 { "blsic", { VexGdq, Edq }, 0 },
3032 { "t1mskc", { VexGdq, Edq }, 0 },
3033 },
3034 /* REG_0FXOP_09_02_L_0 */
3035 {
3036 { Bad_Opcode },
3037 { "blcmsk", { VexGdq, Edq }, 0 },
3038 { Bad_Opcode },
3039 { Bad_Opcode },
3040 { Bad_Opcode },
3041 { Bad_Opcode },
3042 { "blci", { VexGdq, Edq }, 0 },
3043 },
3044 /* REG_0FXOP_09_12_M_1_L_0 */
3045 {
3046 { "llwpcb", { Edq }, 0 },
3047 { "slwpcb", { Edq }, 0 },
3048 },
3049 /* REG_0FXOP_0A_12_L_0 */
3050 {
3051 { "lwpins", { VexGdq, Ed, Id }, 0 },
3052 { "lwpval", { VexGdq, Ed, Id }, 0 },
3053 },
3054
3055 #include "i386-dis-evex-reg.h"
3056 };
3057
3058 static const struct dis386 prefix_table[][4] = {
3059 /* PREFIX_90 */
3060 {
3061 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3062 { "pause", { XX }, 0 },
3063 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3064 { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3065 },
3066
3067 /* PREFIX_0F01_REG_3_RM_1 */
3068 {
3069 { "vmmcall", { Skip_MODRM }, 0 },
3070 { "vmgexit", { Skip_MODRM }, 0 },
3071 { Bad_Opcode },
3072 { "vmgexit", { Skip_MODRM }, 0 },
3073 },
3074
3075 /* PREFIX_0F01_REG_5_MOD_0 */
3076 {
3077 { Bad_Opcode },
3078 { "rstorssp", { Mq }, PREFIX_OPCODE },
3079 },
3080
3081 /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3082 {
3083 { "serialize", { Skip_MODRM }, PREFIX_OPCODE },
3084 { "setssbsy", { Skip_MODRM }, PREFIX_OPCODE },
3085 { Bad_Opcode },
3086 { "xsusldtrk", { Skip_MODRM }, PREFIX_OPCODE },
3087 },
3088
3089 /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
3090 {
3091 { Bad_Opcode },
3092 { Bad_Opcode },
3093 { Bad_Opcode },
3094 { "xresldtrk", { Skip_MODRM }, PREFIX_OPCODE },
3095 },
3096
3097 /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3098 {
3099 { Bad_Opcode },
3100 { "saveprevssp", { Skip_MODRM }, PREFIX_OPCODE },
3101 },
3102
3103 /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3104 {
3105 { "monitorx", { { OP_Monitor, 0 } }, 0 },
3106 { "mcommit", { Skip_MODRM }, 0 },
3107 },
3108
3109 /* PREFIX_0F09 */
3110 {
3111 { "wbinvd", { XX }, 0 },
3112 { "wbnoinvd", { XX }, 0 },
3113 },
3114
3115 /* PREFIX_0F10 */
3116 {
3117 { "movups", { XM, EXx }, PREFIX_OPCODE },
3118 { "movss", { XM, EXd }, PREFIX_OPCODE },
3119 { "movupd", { XM, EXx }, PREFIX_OPCODE },
3120 { "movsd", { XM, EXq }, PREFIX_OPCODE },
3121 },
3122
3123 /* PREFIX_0F11 */
3124 {
3125 { "movups", { EXxS, XM }, PREFIX_OPCODE },
3126 { "movss", { EXdS, XM }, PREFIX_OPCODE },
3127 { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3128 { "movsd", { EXqS, XM }, PREFIX_OPCODE },
3129 },
3130
3131 /* PREFIX_0F12 */
3132 {
3133 { MOD_TABLE (MOD_0F12_PREFIX_0) },
3134 { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3135 { MOD_TABLE (MOD_0F12_PREFIX_2) },
3136 { "movddup", { XM, EXq }, PREFIX_OPCODE },
3137 },
3138
3139 /* PREFIX_0F16 */
3140 {
3141 { MOD_TABLE (MOD_0F16_PREFIX_0) },
3142 { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3143 { MOD_TABLE (MOD_0F16_PREFIX_2) },
3144 },
3145
3146 /* PREFIX_0F1A */
3147 {
3148 { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3149 { "bndcl", { Gbnd, Ev_bnd }, 0 },
3150 { "bndmov", { Gbnd, Ebnd }, 0 },
3151 { "bndcu", { Gbnd, Ev_bnd }, 0 },
3152 },
3153
3154 /* PREFIX_0F1B */
3155 {
3156 { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3157 { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3158 { "bndmov", { EbndS, Gbnd }, 0 },
3159 { "bndcn", { Gbnd, Ev_bnd }, 0 },
3160 },
3161
3162 /* PREFIX_0F1C */
3163 {
3164 { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3165 { "nopQ", { Ev }, PREFIX_OPCODE },
3166 { "nopQ", { Ev }, PREFIX_OPCODE },
3167 { "nopQ", { Ev }, PREFIX_OPCODE },
3168 },
3169
3170 /* PREFIX_0F1E */
3171 {
3172 { "nopQ", { Ev }, PREFIX_OPCODE },
3173 { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3174 { "nopQ", { Ev }, PREFIX_OPCODE },
3175 { "nopQ", { Ev }, PREFIX_OPCODE },
3176 },
3177
3178 /* PREFIX_0F2A */
3179 {
3180 { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3181 { "cvtsi2ss{%LQ|}", { XM, Edq }, PREFIX_OPCODE },
3182 { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3183 { "cvtsi2sd{%LQ|}", { XM, Edq }, 0 },
3184 },
3185
3186 /* PREFIX_0F2B */
3187 {
3188 { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3189 { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3190 { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3191 { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3192 },
3193
3194 /* PREFIX_0F2C */
3195 {
3196 { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3197 { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
3198 { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3199 { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3200 },
3201
3202 /* PREFIX_0F2D */
3203 {
3204 { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3205 { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
3206 { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3207 { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3208 },
3209
3210 /* PREFIX_0F2E */
3211 {
3212 { "ucomiss",{ XM, EXd }, 0 },
3213 { Bad_Opcode },
3214 { "ucomisd",{ XM, EXq }, 0 },
3215 },
3216
3217 /* PREFIX_0F2F */
3218 {
3219 { "comiss", { XM, EXd }, 0 },
3220 { Bad_Opcode },
3221 { "comisd", { XM, EXq }, 0 },
3222 },
3223
3224 /* PREFIX_0F51 */
3225 {
3226 { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3227 { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3228 { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3229 { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3230 },
3231
3232 /* PREFIX_0F52 */
3233 {
3234 { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3235 { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3236 },
3237
3238 /* PREFIX_0F53 */
3239 {
3240 { "rcpps", { XM, EXx }, PREFIX_OPCODE },
3241 { "rcpss", { XM, EXd }, PREFIX_OPCODE },
3242 },
3243
3244 /* PREFIX_0F58 */
3245 {
3246 { "addps", { XM, EXx }, PREFIX_OPCODE },
3247 { "addss", { XM, EXd }, PREFIX_OPCODE },
3248 { "addpd", { XM, EXx }, PREFIX_OPCODE },
3249 { "addsd", { XM, EXq }, PREFIX_OPCODE },
3250 },
3251
3252 /* PREFIX_0F59 */
3253 {
3254 { "mulps", { XM, EXx }, PREFIX_OPCODE },
3255 { "mulss", { XM, EXd }, PREFIX_OPCODE },
3256 { "mulpd", { XM, EXx }, PREFIX_OPCODE },
3257 { "mulsd", { XM, EXq }, PREFIX_OPCODE },
3258 },
3259
3260 /* PREFIX_0F5A */
3261 {
3262 { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3263 { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3264 { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3265 { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3266 },
3267
3268 /* PREFIX_0F5B */
3269 {
3270 { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3271 { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3272 { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3273 },
3274
3275 /* PREFIX_0F5C */
3276 {
3277 { "subps", { XM, EXx }, PREFIX_OPCODE },
3278 { "subss", { XM, EXd }, PREFIX_OPCODE },
3279 { "subpd", { XM, EXx }, PREFIX_OPCODE },
3280 { "subsd", { XM, EXq }, PREFIX_OPCODE },
3281 },
3282
3283 /* PREFIX_0F5D */
3284 {
3285 { "minps", { XM, EXx }, PREFIX_OPCODE },
3286 { "minss", { XM, EXd }, PREFIX_OPCODE },
3287 { "minpd", { XM, EXx }, PREFIX_OPCODE },
3288 { "minsd", { XM, EXq }, PREFIX_OPCODE },
3289 },
3290
3291 /* PREFIX_0F5E */
3292 {
3293 { "divps", { XM, EXx }, PREFIX_OPCODE },
3294 { "divss", { XM, EXd }, PREFIX_OPCODE },
3295 { "divpd", { XM, EXx }, PREFIX_OPCODE },
3296 { "divsd", { XM, EXq }, PREFIX_OPCODE },
3297 },
3298
3299 /* PREFIX_0F5F */
3300 {
3301 { "maxps", { XM, EXx }, PREFIX_OPCODE },
3302 { "maxss", { XM, EXd }, PREFIX_OPCODE },
3303 { "maxpd", { XM, EXx }, PREFIX_OPCODE },
3304 { "maxsd", { XM, EXq }, PREFIX_OPCODE },
3305 },
3306
3307 /* PREFIX_0F60 */
3308 {
3309 { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3310 { Bad_Opcode },
3311 { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3312 },
3313
3314 /* PREFIX_0F61 */
3315 {
3316 { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3317 { Bad_Opcode },
3318 { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3319 },
3320
3321 /* PREFIX_0F62 */
3322 {
3323 { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3324 { Bad_Opcode },
3325 { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3326 },
3327
3328 /* PREFIX_0F6F */
3329 {
3330 { "movq", { MX, EM }, PREFIX_OPCODE },
3331 { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3332 { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3333 },
3334
3335 /* PREFIX_0F70 */
3336 {
3337 { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3338 { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3339 { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3340 { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3341 },
3342
3343 /* PREFIX_0F78 */
3344 {
3345 {"vmread", { Em, Gm }, 0 },
3346 { Bad_Opcode },
3347 {"extrq", { XS, Ib, Ib }, 0 },
3348 {"insertq", { XM, XS, Ib, Ib }, 0 },
3349 },
3350
3351 /* PREFIX_0F79 */
3352 {
3353 {"vmwrite", { Gm, Em }, 0 },
3354 { Bad_Opcode },
3355 {"extrq", { XM, XS }, 0 },
3356 {"insertq", { XM, XS }, 0 },
3357 },
3358
3359 /* PREFIX_0F7C */
3360 {
3361 { Bad_Opcode },
3362 { Bad_Opcode },
3363 { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3364 { "haddps", { XM, EXx }, PREFIX_OPCODE },
3365 },
3366
3367 /* PREFIX_0F7D */
3368 {
3369 { Bad_Opcode },
3370 { Bad_Opcode },
3371 { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3372 { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3373 },
3374
3375 /* PREFIX_0F7E */
3376 {
3377 { "movK", { Edq, MX }, PREFIX_OPCODE },
3378 { "movq", { XM, EXq }, PREFIX_OPCODE },
3379 { "movK", { Edq, XM }, PREFIX_OPCODE },
3380 },
3381
3382 /* PREFIX_0F7F */
3383 {
3384 { "movq", { EMS, MX }, PREFIX_OPCODE },
3385 { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3386 { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3387 },
3388
3389 /* PREFIX_0FAE_REG_0_MOD_3 */
3390 {
3391 { Bad_Opcode },
3392 { "rdfsbase", { Ev }, 0 },
3393 },
3394
3395 /* PREFIX_0FAE_REG_1_MOD_3 */
3396 {
3397 { Bad_Opcode },
3398 { "rdgsbase", { Ev }, 0 },
3399 },
3400
3401 /* PREFIX_0FAE_REG_2_MOD_3 */
3402 {
3403 { Bad_Opcode },
3404 { "wrfsbase", { Ev }, 0 },
3405 },
3406
3407 /* PREFIX_0FAE_REG_3_MOD_3 */
3408 {
3409 { Bad_Opcode },
3410 { "wrgsbase", { Ev }, 0 },
3411 },
3412
3413 /* PREFIX_0FAE_REG_4_MOD_0 */
3414 {
3415 { "xsave", { FXSAVE }, 0 },
3416 { "ptwrite{%LQ|}", { Edq }, 0 },
3417 },
3418
3419 /* PREFIX_0FAE_REG_4_MOD_3 */
3420 {
3421 { Bad_Opcode },
3422 { "ptwrite{%LQ|}", { Edq }, 0 },
3423 },
3424
3425 /* PREFIX_0FAE_REG_5_MOD_3 */
3426 {
3427 { "lfence", { Skip_MODRM }, 0 },
3428 { "incsspK", { Rdq }, PREFIX_OPCODE },
3429 },
3430
3431 /* PREFIX_0FAE_REG_6_MOD_0 */
3432 {
3433 { "xsaveopt", { FXSAVE }, PREFIX_OPCODE },
3434 { "clrssbsy", { Mq }, PREFIX_OPCODE },
3435 { "clwb", { Mb }, PREFIX_OPCODE },
3436 },
3437
3438 /* PREFIX_0FAE_REG_6_MOD_3 */
3439 {
3440 { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) },
3441 { "umonitor", { Eva }, PREFIX_OPCODE },
3442 { "tpause", { Edq }, PREFIX_OPCODE },
3443 { "umwait", { Edq }, PREFIX_OPCODE },
3444 },
3445
3446 /* PREFIX_0FAE_REG_7_MOD_0 */
3447 {
3448 { "clflush", { Mb }, 0 },
3449 { Bad_Opcode },
3450 { "clflushopt", { Mb }, 0 },
3451 },
3452
3453 /* PREFIX_0FB8 */
3454 {
3455 { Bad_Opcode },
3456 { "popcntS", { Gv, Ev }, 0 },
3457 },
3458
3459 /* PREFIX_0FBC */
3460 {
3461 { "bsfS", { Gv, Ev }, 0 },
3462 { "tzcntS", { Gv, Ev }, 0 },
3463 { "bsfS", { Gv, Ev }, 0 },
3464 },
3465
3466 /* PREFIX_0FBD */
3467 {
3468 { "bsrS", { Gv, Ev }, 0 },
3469 { "lzcntS", { Gv, Ev }, 0 },
3470 { "bsrS", { Gv, Ev }, 0 },
3471 },
3472
3473 /* PREFIX_0FC2 */
3474 {
3475 { "cmpps", { XM, EXx, CMP }, PREFIX_OPCODE },
3476 { "cmpss", { XM, EXd, CMP }, PREFIX_OPCODE },
3477 { "cmppd", { XM, EXx, CMP }, PREFIX_OPCODE },
3478 { "cmpsd", { XM, EXq, CMP }, PREFIX_OPCODE },
3479 },
3480
3481 /* PREFIX_0FC7_REG_6_MOD_0 */
3482 {
3483 { "vmptrld",{ Mq }, 0 },
3484 { "vmxon", { Mq }, 0 },
3485 { "vmclear",{ Mq }, 0 },
3486 },
3487
3488 /* PREFIX_0FC7_REG_6_MOD_3 */
3489 {
3490 { "rdrand", { Ev }, 0 },
3491 { Bad_Opcode },
3492 { "rdrand", { Ev }, 0 }
3493 },
3494
3495 /* PREFIX_0FC7_REG_7_MOD_3 */
3496 {
3497 { "rdseed", { Ev }, 0 },
3498 { "rdpid", { Em }, 0 },
3499 { "rdseed", { Ev }, 0 },
3500 },
3501
3502 /* PREFIX_0FD0 */
3503 {
3504 { Bad_Opcode },
3505 { Bad_Opcode },
3506 { "addsubpd", { XM, EXx }, 0 },
3507 { "addsubps", { XM, EXx }, 0 },
3508 },
3509
3510 /* PREFIX_0FD6 */
3511 {
3512 { Bad_Opcode },
3513 { "movq2dq",{ XM, MS }, 0 },
3514 { "movq", { EXqS, XM }, 0 },
3515 { "movdq2q",{ MX, XS }, 0 },
3516 },
3517
3518 /* PREFIX_0FE6 */
3519 {
3520 { Bad_Opcode },
3521 { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
3522 { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
3523 { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
3524 },
3525
3526 /* PREFIX_0FE7 */
3527 {
3528 { "movntq", { Mq, MX }, PREFIX_OPCODE },
3529 { Bad_Opcode },
3530 { MOD_TABLE (MOD_0FE7_PREFIX_2) },
3531 },
3532
3533 /* PREFIX_0FF0 */
3534 {
3535 { Bad_Opcode },
3536 { Bad_Opcode },
3537 { Bad_Opcode },
3538 { MOD_TABLE (MOD_0FF0_PREFIX_3) },
3539 },
3540
3541 /* PREFIX_0FF7 */
3542 {
3543 { "maskmovq", { MX, MS }, PREFIX_OPCODE },
3544 { Bad_Opcode },
3545 { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
3546 },
3547
3548 /* PREFIX_0F38F0 */
3549 {
3550 { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3551 { Bad_Opcode },
3552 { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3553 { "crc32A", { Gdq, Eb }, PREFIX_OPCODE },
3554 },
3555
3556 /* PREFIX_0F38F1 */
3557 {
3558 { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3559 { Bad_Opcode },
3560 { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3561 { "crc32Q", { Gdq, Ev }, PREFIX_OPCODE },
3562 },
3563
3564 /* PREFIX_0F38F6 */
3565 {
3566 { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
3567 { "adoxS", { Gdq, Edq}, PREFIX_OPCODE },
3568 { "adcxS", { Gdq, Edq}, PREFIX_OPCODE },
3569 { Bad_Opcode },
3570 },
3571
3572 /* PREFIX_0F38F8 */
3573 {
3574 { Bad_Opcode },
3575 { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
3576 { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
3577 { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
3578 },
3579
3580 /* PREFIX_VEX_0F10 */
3581 {
3582 { "vmovups", { XM, EXx }, 0 },
3583 { "vmovss", { XMScalar, VexScalarR, EXxmm_md }, 0 },
3584 { "vmovupd", { XM, EXx }, 0 },
3585 { "vmovsd", { XMScalar, VexScalarR, EXxmm_mq }, 0 },
3586 },
3587
3588 /* PREFIX_VEX_0F11 */
3589 {
3590 { "vmovups", { EXxS, XM }, 0 },
3591 { "vmovss", { EXdS, VexScalarR, XMScalar }, 0 },
3592 { "vmovupd", { EXxS, XM }, 0 },
3593 { "vmovsd", { EXqS, VexScalarR, XMScalar }, 0 },
3594 },
3595
3596 /* PREFIX_VEX_0F12 */
3597 {
3598 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
3599 { "vmovsldup", { XM, EXx }, 0 },
3600 { MOD_TABLE (MOD_VEX_0F12_PREFIX_2) },
3601 { "vmovddup", { XM, EXymmq }, 0 },
3602 },
3603
3604 /* PREFIX_VEX_0F16 */
3605 {
3606 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
3607 { "vmovshdup", { XM, EXx }, 0 },
3608 { MOD_TABLE (MOD_VEX_0F16_PREFIX_2) },
3609 },
3610
3611 /* PREFIX_VEX_0F2A */
3612 {
3613 { Bad_Opcode },
3614 { "vcvtsi2ss{%LQ|}", { XMScalar, VexScalar, Edq }, 0 },
3615 { Bad_Opcode },
3616 { "vcvtsi2sd{%LQ|}", { XMScalar, VexScalar, Edq }, 0 },
3617 },
3618
3619 /* PREFIX_VEX_0F2C */
3620 {
3621 { Bad_Opcode },
3622 { "vcvttss2si", { Gdq, EXxmm_md, EXxEVexS }, 0 },
3623 { Bad_Opcode },
3624 { "vcvttsd2si", { Gdq, EXxmm_mq, EXxEVexS }, 0 },
3625 },
3626
3627 /* PREFIX_VEX_0F2D */
3628 {
3629 { Bad_Opcode },
3630 { "vcvtss2si", { Gdq, EXxmm_md, EXxEVexR }, 0 },
3631 { Bad_Opcode },
3632 { "vcvtsd2si", { Gdq, EXxmm_mq, EXxEVexR }, 0 },
3633 },
3634
3635 /* PREFIX_VEX_0F2E */
3636 {
3637 { "vucomisX", { XMScalar, EXxmm_md, EXxEVexS }, PREFIX_OPCODE },
3638 { Bad_Opcode },
3639 { "vucomisX", { XMScalar, EXxmm_mq, EXxEVexS }, PREFIX_OPCODE },
3640 },
3641
3642 /* PREFIX_VEX_0F2F */
3643 {
3644 { "vcomisX", { XMScalar, EXxmm_md, EXxEVexS }, PREFIX_OPCODE },
3645 { Bad_Opcode },
3646 { "vcomisX", { XMScalar, EXxmm_mq, EXxEVexS }, PREFIX_OPCODE },
3647 },
3648
3649 /* PREFIX_VEX_0F41 */
3650 {
3651 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
3652 { Bad_Opcode },
3653 { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
3654 },
3655
3656 /* PREFIX_VEX_0F42 */
3657 {
3658 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
3659 { Bad_Opcode },
3660 { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
3661 },
3662
3663 /* PREFIX_VEX_0F44 */
3664 {
3665 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
3666 { Bad_Opcode },
3667 { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
3668 },
3669
3670 /* PREFIX_VEX_0F45 */
3671 {
3672 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
3673 { Bad_Opcode },
3674 { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
3675 },
3676
3677 /* PREFIX_VEX_0F46 */
3678 {
3679 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
3680 { Bad_Opcode },
3681 { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
3682 },
3683
3684 /* PREFIX_VEX_0F47 */
3685 {
3686 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
3687 { Bad_Opcode },
3688 { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
3689 },
3690
3691 /* PREFIX_VEX_0F4A */
3692 {
3693 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
3694 { Bad_Opcode },
3695 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
3696 },
3697
3698 /* PREFIX_VEX_0F4B */
3699 {
3700 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
3701 { Bad_Opcode },
3702 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
3703 },
3704
3705 /* PREFIX_VEX_0F51 */
3706 {
3707 { "vsqrtps", { XM, EXx }, 0 },
3708 { "vsqrtss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3709 { "vsqrtpd", { XM, EXx }, 0 },
3710 { "vsqrtsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
3711 },
3712
3713 /* PREFIX_VEX_0F52 */
3714 {
3715 { "vrsqrtps", { XM, EXx }, 0 },
3716 { "vrsqrtss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3717 },
3718
3719 /* PREFIX_VEX_0F53 */
3720 {
3721 { "vrcpps", { XM, EXx }, 0 },
3722 { "vrcpss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3723 },
3724
3725 /* PREFIX_VEX_0F58 */
3726 {
3727 { "vaddps", { XM, Vex, EXx }, 0 },
3728 { "vaddss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3729 { "vaddpd", { XM, Vex, EXx }, 0 },
3730 { "vaddsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
3731 },
3732
3733 /* PREFIX_VEX_0F59 */
3734 {
3735 { "vmulps", { XM, Vex, EXx }, 0 },
3736 { "vmulss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3737 { "vmulpd", { XM, Vex, EXx }, 0 },
3738 { "vmulsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
3739 },
3740
3741 /* PREFIX_VEX_0F5A */
3742 {
3743 { "vcvtps2pd", { XM, EXxmmq }, 0 },
3744 { "vcvtss2sd", { XMScalar, VexScalar, EXxmm_md }, 0 },
3745 { "vcvtpd2ps%XY",{ XMM, EXx }, 0 },
3746 { "vcvtsd2ss", { XMScalar, VexScalar, EXxmm_mq }, 0 },
3747 },
3748
3749 /* PREFIX_VEX_0F5B */
3750 {
3751 { "vcvtdq2ps", { XM, EXx }, 0 },
3752 { "vcvttps2dq", { XM, EXx }, 0 },
3753 { "vcvtps2dq", { XM, EXx }, 0 },
3754 },
3755
3756 /* PREFIX_VEX_0F5C */
3757 {
3758 { "vsubps", { XM, Vex, EXx }, 0 },
3759 { "vsubss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3760 { "vsubpd", { XM, Vex, EXx }, 0 },
3761 { "vsubsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
3762 },
3763
3764 /* PREFIX_VEX_0F5D */
3765 {
3766 { "vminps", { XM, Vex, EXx }, 0 },
3767 { "vminss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3768 { "vminpd", { XM, Vex, EXx }, 0 },
3769 { "vminsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
3770 },
3771
3772 /* PREFIX_VEX_0F5E */
3773 {
3774 { "vdivps", { XM, Vex, EXx }, 0 },
3775 { "vdivss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3776 { "vdivpd", { XM, Vex, EXx }, 0 },
3777 { "vdivsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
3778 },
3779
3780 /* PREFIX_VEX_0F5F */
3781 {
3782 { "vmaxps", { XM, Vex, EXx }, 0 },
3783 { "vmaxss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3784 { "vmaxpd", { XM, Vex, EXx }, 0 },
3785 { "vmaxsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
3786 },
3787
3788 /* PREFIX_VEX_0F6F */
3789 {
3790 { Bad_Opcode },
3791 { "vmovdqu", { XM, EXx }, 0 },
3792 { "vmovdqa", { XM, EXx }, 0 },
3793 },
3794
3795 /* PREFIX_VEX_0F70 */
3796 {
3797 { Bad_Opcode },
3798 { "vpshufhw", { XM, EXx, Ib }, 0 },
3799 { "vpshufd", { XM, EXx, Ib }, 0 },
3800 { "vpshuflw", { XM, EXx, Ib }, 0 },
3801 },
3802
3803 /* PREFIX_VEX_0F7C */
3804 {
3805 { Bad_Opcode },
3806 { Bad_Opcode },
3807 { "vhaddpd", { XM, Vex, EXx }, 0 },
3808 { "vhaddps", { XM, Vex, EXx }, 0 },
3809 },
3810
3811 /* PREFIX_VEX_0F7D */
3812 {
3813 { Bad_Opcode },
3814 { Bad_Opcode },
3815 { "vhsubpd", { XM, Vex, EXx }, 0 },
3816 { "vhsubps", { XM, Vex, EXx }, 0 },
3817 },
3818
3819 /* PREFIX_VEX_0F7E */
3820 {
3821 { Bad_Opcode },
3822 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
3823 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
3824 },
3825
3826 /* PREFIX_VEX_0F7F */
3827 {
3828 { Bad_Opcode },
3829 { "vmovdqu", { EXxS, XM }, 0 },
3830 { "vmovdqa", { EXxS, XM }, 0 },
3831 },
3832
3833 /* PREFIX_VEX_0F90 */
3834 {
3835 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
3836 { Bad_Opcode },
3837 { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
3838 },
3839
3840 /* PREFIX_VEX_0F91 */
3841 {
3842 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
3843 { Bad_Opcode },
3844 { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
3845 },
3846
3847 /* PREFIX_VEX_0F92 */
3848 {
3849 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
3850 { Bad_Opcode },
3851 { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
3852 { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
3853 },
3854
3855 /* PREFIX_VEX_0F93 */
3856 {
3857 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
3858 { Bad_Opcode },
3859 { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
3860 { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
3861 },
3862
3863 /* PREFIX_VEX_0F98 */
3864 {
3865 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
3866 { Bad_Opcode },
3867 { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
3868 },
3869
3870 /* PREFIX_VEX_0F99 */
3871 {
3872 { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
3873 { Bad_Opcode },
3874 { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
3875 },
3876
3877 /* PREFIX_VEX_0FC2 */
3878 {
3879 { "vcmpps", { XM, Vex, EXx, CMP }, 0 },
3880 { "vcmpss", { XMScalar, VexScalar, EXxmm_md, CMP }, 0 },
3881 { "vcmppd", { XM, Vex, EXx, CMP }, 0 },
3882 { "vcmpsd", { XMScalar, VexScalar, EXxmm_mq, CMP }, 0 },
3883 },
3884
3885 /* PREFIX_VEX_0FD0 */
3886 {
3887 { Bad_Opcode },
3888 { Bad_Opcode },
3889 { "vaddsubpd", { XM, Vex, EXx }, 0 },
3890 { "vaddsubps", { XM, Vex, EXx }, 0 },
3891 },
3892
3893 /* PREFIX_VEX_0FE6 */
3894 {
3895 { Bad_Opcode },
3896 { "vcvtdq2pd", { XM, EXxmmq }, 0 },
3897 { "vcvttpd2dq%XY", { XMM, EXx }, 0 },
3898 { "vcvtpd2dq%XY", { XMM, EXx }, 0 },
3899 },
3900
3901 /* PREFIX_VEX_0FF0 */
3902 {
3903 { Bad_Opcode },
3904 { Bad_Opcode },
3905 { Bad_Opcode },
3906 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
3907 },
3908
3909 /* PREFIX_VEX_0F3849_X86_64 */
3910 {
3911 { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_0) },
3912 { Bad_Opcode },
3913 { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_2) },
3914 { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_3) },
3915 },
3916
3917 /* PREFIX_VEX_0F384B_X86_64 */
3918 {
3919 { Bad_Opcode },
3920 { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_1) },
3921 { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_2) },
3922 { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_3) },
3923 },
3924
3925 /* PREFIX_VEX_0F385C_X86_64 */
3926 {
3927 { Bad_Opcode },
3928 { VEX_W_TABLE (VEX_W_0F385C_X86_64_P_1) },
3929 { Bad_Opcode },
3930 },
3931
3932 /* PREFIX_VEX_0F385E_X86_64 */
3933 {
3934 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_0) },
3935 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_1) },
3936 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_2) },
3937 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_3) },
3938 },
3939
3940 /* PREFIX_VEX_0F38F5 */
3941 {
3942 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
3943 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
3944 { Bad_Opcode },
3945 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
3946 },
3947
3948 /* PREFIX_VEX_0F38F6 */
3949 {
3950 { Bad_Opcode },
3951 { Bad_Opcode },
3952 { Bad_Opcode },
3953 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
3954 },
3955
3956 /* PREFIX_VEX_0F38F7 */
3957 {
3958 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
3959 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
3960 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
3961 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
3962 },
3963
3964 /* PREFIX_VEX_0F3AF0 */
3965 {
3966 { Bad_Opcode },
3967 { Bad_Opcode },
3968 { Bad_Opcode },
3969 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
3970 },
3971
3972 #include "i386-dis-evex-prefix.h"
3973 };
3974
3975 static const struct dis386 x86_64_table[][2] = {
3976 /* X86_64_06 */
3977 {
3978 { "pushP", { es }, 0 },
3979 },
3980
3981 /* X86_64_07 */
3982 {
3983 { "popP", { es }, 0 },
3984 },
3985
3986 /* X86_64_0E */
3987 {
3988 { "pushP", { cs }, 0 },
3989 },
3990
3991 /* X86_64_16 */
3992 {
3993 { "pushP", { ss }, 0 },
3994 },
3995
3996 /* X86_64_17 */
3997 {
3998 { "popP", { ss }, 0 },
3999 },
4000
4001 /* X86_64_1E */
4002 {
4003 { "pushP", { ds }, 0 },
4004 },
4005
4006 /* X86_64_1F */
4007 {
4008 { "popP", { ds }, 0 },
4009 },
4010
4011 /* X86_64_27 */
4012 {
4013 { "daa", { XX }, 0 },
4014 },
4015
4016 /* X86_64_2F */
4017 {
4018 { "das", { XX }, 0 },
4019 },
4020
4021 /* X86_64_37 */
4022 {
4023 { "aaa", { XX }, 0 },
4024 },
4025
4026 /* X86_64_3F */
4027 {
4028 { "aas", { XX }, 0 },
4029 },
4030
4031 /* X86_64_60 */
4032 {
4033 { "pushaP", { XX }, 0 },
4034 },
4035
4036 /* X86_64_61 */
4037 {
4038 { "popaP", { XX }, 0 },
4039 },
4040
4041 /* X86_64_62 */
4042 {
4043 { MOD_TABLE (MOD_62_32BIT) },
4044 { EVEX_TABLE (EVEX_0F) },
4045 },
4046
4047 /* X86_64_63 */
4048 {
4049 { "arpl", { Ew, Gw }, 0 },
4050 { "movs", { { OP_G, movsxd_mode }, { MOVSXD_Fixup, movsxd_mode } }, 0 },
4051 },
4052
4053 /* X86_64_6D */
4054 {
4055 { "ins{R|}", { Yzr, indirDX }, 0 },
4056 { "ins{G|}", { Yzr, indirDX }, 0 },
4057 },
4058
4059 /* X86_64_6F */
4060 {
4061 { "outs{R|}", { indirDXr, Xz }, 0 },
4062 { "outs{G|}", { indirDXr, Xz }, 0 },
4063 },
4064
4065 /* X86_64_82 */
4066 {
4067 /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */
4068 { REG_TABLE (REG_80) },
4069 },
4070
4071 /* X86_64_9A */
4072 {
4073 { "{l|}call{T|}", { Ap }, 0 },
4074 },
4075
4076 /* X86_64_C2 */
4077 {
4078 { "retP", { Iw, BND }, 0 },
4079 { "ret@", { Iw, BND }, 0 },
4080 },
4081
4082 /* X86_64_C3 */
4083 {
4084 { "retP", { BND }, 0 },
4085 { "ret@", { BND }, 0 },
4086 },
4087
4088 /* X86_64_C4 */
4089 {
4090 { MOD_TABLE (MOD_C4_32BIT) },
4091 { VEX_C4_TABLE (VEX_0F) },
4092 },
4093
4094 /* X86_64_C5 */
4095 {
4096 { MOD_TABLE (MOD_C5_32BIT) },
4097 { VEX_C5_TABLE (VEX_0F) },
4098 },
4099
4100 /* X86_64_CE */
4101 {
4102 { "into", { XX }, 0 },
4103 },
4104
4105 /* X86_64_D4 */
4106 {
4107 { "aam", { Ib }, 0 },
4108 },
4109
4110 /* X86_64_D5 */
4111 {
4112 { "aad", { Ib }, 0 },
4113 },
4114
4115 /* X86_64_E8 */
4116 {
4117 { "callP", { Jv, BND }, 0 },
4118 { "call@", { Jv, BND }, 0 }
4119 },
4120
4121 /* X86_64_E9 */
4122 {
4123 { "jmpP", { Jv, BND }, 0 },
4124 { "jmp@", { Jv, BND }, 0 }
4125 },
4126
4127 /* X86_64_EA */
4128 {
4129 { "{l|}jmp{T|}", { Ap }, 0 },
4130 },
4131
4132 /* X86_64_0F01_REG_0 */
4133 {
4134 { "sgdt{Q|Q}", { M }, 0 },
4135 { "sgdt", { M }, 0 },
4136 },
4137
4138 /* X86_64_0F01_REG_1 */
4139 {
4140 { "sidt{Q|Q}", { M }, 0 },
4141 { "sidt", { M }, 0 },
4142 },
4143
4144 /* X86_64_0F01_REG_2 */
4145 {
4146 { "lgdt{Q|Q}", { M }, 0 },
4147 { "lgdt", { M }, 0 },
4148 },
4149
4150 /* X86_64_0F01_REG_3 */
4151 {
4152 { "lidt{Q|Q}", { M }, 0 },
4153 { "lidt", { M }, 0 },
4154 },
4155
4156 /* X86_64_VEX_0F3849 */
4157 {
4158 { Bad_Opcode },
4159 { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64) },
4160 },
4161
4162 /* X86_64_VEX_0F384B */
4163 {
4164 { Bad_Opcode },
4165 { PREFIX_TABLE (PREFIX_VEX_0F384B_X86_64) },
4166 },
4167
4168 /* X86_64_VEX_0F385C */
4169 {
4170 { Bad_Opcode },
4171 { PREFIX_TABLE (PREFIX_VEX_0F385C_X86_64) },
4172 },
4173
4174 /* X86_64_VEX_0F385E */
4175 {
4176 { Bad_Opcode },
4177 { PREFIX_TABLE (PREFIX_VEX_0F385E_X86_64) },
4178 },
4179 };
4180
4181 static const struct dis386 three_byte_table[][256] = {
4182
4183 /* THREE_BYTE_0F38 */
4184 {
4185 /* 00 */
4186 { "pshufb", { MX, EM }, PREFIX_OPCODE },
4187 { "phaddw", { MX, EM }, PREFIX_OPCODE },
4188 { "phaddd", { MX, EM }, PREFIX_OPCODE },
4189 { "phaddsw", { MX, EM }, PREFIX_OPCODE },
4190 { "pmaddubsw", { MX, EM }, PREFIX_OPCODE },
4191 { "phsubw", { MX, EM }, PREFIX_OPCODE },
4192 { "phsubd", { MX, EM }, PREFIX_OPCODE },
4193 { "phsubsw", { MX, EM }, PREFIX_OPCODE },
4194 /* 08 */
4195 { "psignb", { MX, EM }, PREFIX_OPCODE },
4196 { "psignw", { MX, EM }, PREFIX_OPCODE },
4197 { "psignd", { MX, EM }, PREFIX_OPCODE },
4198 { "pmulhrsw", { MX, EM }, PREFIX_OPCODE },
4199 { Bad_Opcode },
4200 { Bad_Opcode },
4201 { Bad_Opcode },
4202 { Bad_Opcode },
4203 /* 10 */
4204 { "pblendvb", { XM, EXx, XMM0 }, PREFIX_DATA },
4205 { Bad_Opcode },
4206 { Bad_Opcode },
4207 { Bad_Opcode },
4208 { "blendvps", { XM, EXx, XMM0 }, PREFIX_DATA },
4209 { "blendvpd", { XM, EXx, XMM0 }, PREFIX_DATA },
4210 { Bad_Opcode },
4211 { "ptest", { XM, EXx }, PREFIX_DATA },
4212 /* 18 */
4213 { Bad_Opcode },
4214 { Bad_Opcode },
4215 { Bad_Opcode },
4216 { Bad_Opcode },
4217 { "pabsb", { MX, EM }, PREFIX_OPCODE },
4218 { "pabsw", { MX, EM }, PREFIX_OPCODE },
4219 { "pabsd", { MX, EM }, PREFIX_OPCODE },
4220 { Bad_Opcode },
4221 /* 20 */
4222 { "pmovsxbw", { XM, EXq }, PREFIX_DATA },
4223 { "pmovsxbd", { XM, EXd }, PREFIX_DATA },
4224 { "pmovsxbq", { XM, EXw }, PREFIX_DATA },
4225 { "pmovsxwd", { XM, EXq }, PREFIX_DATA },
4226 { "pmovsxwq", { XM, EXd }, PREFIX_DATA },
4227 { "pmovsxdq", { XM, EXq }, PREFIX_DATA },
4228 { Bad_Opcode },
4229 { Bad_Opcode },
4230 /* 28 */
4231 { "pmuldq", { XM, EXx }, PREFIX_DATA },
4232 { "pcmpeqq", { XM, EXx }, PREFIX_DATA },
4233 { MOD_TABLE (MOD_0F382A) },
4234 { "packusdw", { XM, EXx }, PREFIX_DATA },
4235 { Bad_Opcode },
4236 { Bad_Opcode },
4237 { Bad_Opcode },
4238 { Bad_Opcode },
4239 /* 30 */
4240 { "pmovzxbw", { XM, EXq }, PREFIX_DATA },
4241 { "pmovzxbd", { XM, EXd }, PREFIX_DATA },
4242 { "pmovzxbq", { XM, EXw }, PREFIX_DATA },
4243 { "pmovzxwd", { XM, EXq }, PREFIX_DATA },
4244 { "pmovzxwq", { XM, EXd }, PREFIX_DATA },
4245 { "pmovzxdq", { XM, EXq }, PREFIX_DATA },
4246 { Bad_Opcode },
4247 { "pcmpgtq", { XM, EXx }, PREFIX_DATA },
4248 /* 38 */
4249 { "pminsb", { XM, EXx }, PREFIX_DATA },
4250 { "pminsd", { XM, EXx }, PREFIX_DATA },
4251 { "pminuw", { XM, EXx }, PREFIX_DATA },
4252 { "pminud", { XM, EXx }, PREFIX_DATA },
4253 { "pmaxsb", { XM, EXx }, PREFIX_DATA },
4254 { "pmaxsd", { XM, EXx }, PREFIX_DATA },
4255 { "pmaxuw", { XM, EXx }, PREFIX_DATA },
4256 { "pmaxud", { XM, EXx }, PREFIX_DATA },
4257 /* 40 */
4258 { "pmulld", { XM, EXx }, PREFIX_DATA },
4259 { "phminposuw", { XM, EXx }, PREFIX_DATA },
4260 { Bad_Opcode },
4261 { Bad_Opcode },
4262 { Bad_Opcode },
4263 { Bad_Opcode },
4264 { Bad_Opcode },
4265 { Bad_Opcode },
4266 /* 48 */
4267 { Bad_Opcode },
4268 { Bad_Opcode },
4269 { Bad_Opcode },
4270 { Bad_Opcode },
4271 { Bad_Opcode },
4272 { Bad_Opcode },
4273 { Bad_Opcode },
4274 { Bad_Opcode },
4275 /* 50 */
4276 { Bad_Opcode },
4277 { Bad_Opcode },
4278 { Bad_Opcode },
4279 { Bad_Opcode },
4280 { Bad_Opcode },
4281 { Bad_Opcode },
4282 { Bad_Opcode },
4283 { Bad_Opcode },
4284 /* 58 */
4285 { Bad_Opcode },
4286 { Bad_Opcode },
4287 { Bad_Opcode },
4288 { Bad_Opcode },
4289 { Bad_Opcode },
4290 { Bad_Opcode },
4291 { Bad_Opcode },
4292 { Bad_Opcode },
4293 /* 60 */
4294 { Bad_Opcode },
4295 { Bad_Opcode },
4296 { Bad_Opcode },
4297 { Bad_Opcode },
4298 { Bad_Opcode },
4299 { Bad_Opcode },
4300 { Bad_Opcode },
4301 { Bad_Opcode },
4302 /* 68 */
4303 { Bad_Opcode },
4304 { Bad_Opcode },
4305 { Bad_Opcode },
4306 { Bad_Opcode },
4307 { Bad_Opcode },
4308 { Bad_Opcode },
4309 { Bad_Opcode },
4310 { Bad_Opcode },
4311 /* 70 */
4312 { Bad_Opcode },
4313 { Bad_Opcode },
4314 { Bad_Opcode },
4315 { Bad_Opcode },
4316 { Bad_Opcode },
4317 { Bad_Opcode },
4318 { Bad_Opcode },
4319 { Bad_Opcode },
4320 /* 78 */
4321 { Bad_Opcode },
4322 { Bad_Opcode },
4323 { Bad_Opcode },
4324 { Bad_Opcode },
4325 { Bad_Opcode },
4326 { Bad_Opcode },
4327 { Bad_Opcode },
4328 { Bad_Opcode },
4329 /* 80 */
4330 { "invept", { Gm, Mo }, PREFIX_DATA },
4331 { "invvpid", { Gm, Mo }, PREFIX_DATA },
4332 { "invpcid", { Gm, M }, PREFIX_DATA },
4333 { Bad_Opcode },
4334 { Bad_Opcode },
4335 { Bad_Opcode },
4336 { Bad_Opcode },
4337 { Bad_Opcode },
4338 /* 88 */
4339 { Bad_Opcode },
4340 { Bad_Opcode },
4341 { Bad_Opcode },
4342 { Bad_Opcode },
4343 { Bad_Opcode },
4344 { Bad_Opcode },
4345 { Bad_Opcode },
4346 { Bad_Opcode },
4347 /* 90 */
4348 { Bad_Opcode },
4349 { Bad_Opcode },
4350 { Bad_Opcode },
4351 { Bad_Opcode },
4352 { Bad_Opcode },
4353 { Bad_Opcode },
4354 { Bad_Opcode },
4355 { Bad_Opcode },
4356 /* 98 */
4357 { Bad_Opcode },
4358 { Bad_Opcode },
4359 { Bad_Opcode },
4360 { Bad_Opcode },
4361 { Bad_Opcode },
4362 { Bad_Opcode },
4363 { Bad_Opcode },
4364 { Bad_Opcode },
4365 /* a0 */
4366 { Bad_Opcode },
4367 { Bad_Opcode },
4368 { Bad_Opcode },
4369 { Bad_Opcode },
4370 { Bad_Opcode },
4371 { Bad_Opcode },
4372 { Bad_Opcode },
4373 { Bad_Opcode },
4374 /* a8 */
4375 { Bad_Opcode },
4376 { Bad_Opcode },
4377 { Bad_Opcode },
4378 { Bad_Opcode },
4379 { Bad_Opcode },
4380 { Bad_Opcode },
4381 { Bad_Opcode },
4382 { Bad_Opcode },
4383 /* b0 */
4384 { Bad_Opcode },
4385 { Bad_Opcode },
4386 { Bad_Opcode },
4387 { Bad_Opcode },
4388 { Bad_Opcode },
4389 { Bad_Opcode },
4390 { Bad_Opcode },
4391 { Bad_Opcode },
4392 /* b8 */
4393 { Bad_Opcode },
4394 { Bad_Opcode },
4395 { Bad_Opcode },
4396 { Bad_Opcode },
4397 { Bad_Opcode },
4398 { Bad_Opcode },
4399 { Bad_Opcode },
4400 { Bad_Opcode },
4401 /* c0 */
4402 { Bad_Opcode },
4403 { Bad_Opcode },
4404 { Bad_Opcode },
4405 { Bad_Opcode },
4406 { Bad_Opcode },
4407 { Bad_Opcode },
4408 { Bad_Opcode },
4409 { Bad_Opcode },
4410 /* c8 */
4411 { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4412 { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4413 { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4414 { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4415 { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4416 { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4417 { Bad_Opcode },
4418 { "gf2p8mulb", { XM, EXxmm }, PREFIX_DATA },
4419 /* d0 */
4420 { Bad_Opcode },
4421 { Bad_Opcode },
4422 { Bad_Opcode },
4423 { Bad_Opcode },
4424 { Bad_Opcode },
4425 { Bad_Opcode },
4426 { Bad_Opcode },
4427 { Bad_Opcode },
4428 /* d8 */
4429 { Bad_Opcode },
4430 { Bad_Opcode },
4431 { Bad_Opcode },
4432 { "aesimc", { XM, EXx }, PREFIX_DATA },
4433 { "aesenc", { XM, EXx }, PREFIX_DATA },
4434 { "aesenclast", { XM, EXx }, PREFIX_DATA },
4435 { "aesdec", { XM, EXx }, PREFIX_DATA },
4436 { "aesdeclast", { XM, EXx }, PREFIX_DATA },
4437 /* e0 */
4438 { Bad_Opcode },
4439 { Bad_Opcode },
4440 { Bad_Opcode },
4441 { Bad_Opcode },
4442 { Bad_Opcode },
4443 { Bad_Opcode },
4444 { Bad_Opcode },
4445 { Bad_Opcode },
4446 /* e8 */
4447 { Bad_Opcode },
4448 { Bad_Opcode },
4449 { Bad_Opcode },
4450 { Bad_Opcode },
4451 { Bad_Opcode },
4452 { Bad_Opcode },
4453 { Bad_Opcode },
4454 { Bad_Opcode },
4455 /* f0 */
4456 { PREFIX_TABLE (PREFIX_0F38F0) },
4457 { PREFIX_TABLE (PREFIX_0F38F1) },
4458 { Bad_Opcode },
4459 { Bad_Opcode },
4460 { Bad_Opcode },
4461 { MOD_TABLE (MOD_0F38F5) },
4462 { PREFIX_TABLE (PREFIX_0F38F6) },
4463 { Bad_Opcode },
4464 /* f8 */
4465 { PREFIX_TABLE (PREFIX_0F38F8) },
4466 { MOD_TABLE (MOD_0F38F9) },
4467 { Bad_Opcode },
4468 { Bad_Opcode },
4469 { Bad_Opcode },
4470 { Bad_Opcode },
4471 { Bad_Opcode },
4472 { Bad_Opcode },
4473 },
4474 /* THREE_BYTE_0F3A */
4475 {
4476 /* 00 */
4477 { Bad_Opcode },
4478 { Bad_Opcode },
4479 { Bad_Opcode },
4480 { Bad_Opcode },
4481 { Bad_Opcode },
4482 { Bad_Opcode },
4483 { Bad_Opcode },
4484 { Bad_Opcode },
4485 /* 08 */
4486 { "roundps", { XM, EXx, Ib }, PREFIX_DATA },
4487 { "roundpd", { XM, EXx, Ib }, PREFIX_DATA },
4488 { "roundss", { XM, EXd, Ib }, PREFIX_DATA },
4489 { "roundsd", { XM, EXq, Ib }, PREFIX_DATA },
4490 { "blendps", { XM, EXx, Ib }, PREFIX_DATA },
4491 { "blendpd", { XM, EXx, Ib }, PREFIX_DATA },
4492 { "pblendw", { XM, EXx, Ib }, PREFIX_DATA },
4493 { "palignr", { MX, EM, Ib }, PREFIX_OPCODE },
4494 /* 10 */
4495 { Bad_Opcode },
4496 { Bad_Opcode },
4497 { Bad_Opcode },
4498 { Bad_Opcode },
4499 { "pextrb", { Edqb, XM, Ib }, PREFIX_DATA },
4500 { "pextrw", { Edqw, XM, Ib }, PREFIX_DATA },
4501 { "pextrK", { Edq, XM, Ib }, PREFIX_DATA },
4502 { "extractps", { Edqd, XM, Ib }, PREFIX_DATA },
4503 /* 18 */
4504 { Bad_Opcode },
4505 { Bad_Opcode },
4506 { Bad_Opcode },
4507 { Bad_Opcode },
4508 { Bad_Opcode },
4509 { Bad_Opcode },
4510 { Bad_Opcode },
4511 { Bad_Opcode },
4512 /* 20 */
4513 { "pinsrb", { XM, Edqb, Ib }, PREFIX_DATA },
4514 { "insertps", { XM, EXd, Ib }, PREFIX_DATA },
4515 { "pinsrK", { XM, Edq, Ib }, PREFIX_DATA },
4516 { Bad_Opcode },
4517 { Bad_Opcode },
4518 { Bad_Opcode },
4519 { Bad_Opcode },
4520 { Bad_Opcode },
4521 /* 28 */
4522 { Bad_Opcode },
4523 { Bad_Opcode },
4524 { Bad_Opcode },
4525 { Bad_Opcode },
4526 { Bad_Opcode },
4527 { Bad_Opcode },
4528 { Bad_Opcode },
4529 { Bad_Opcode },
4530 /* 30 */
4531 { Bad_Opcode },
4532 { Bad_Opcode },
4533 { Bad_Opcode },
4534 { Bad_Opcode },
4535 { Bad_Opcode },
4536 { Bad_Opcode },
4537 { Bad_Opcode },
4538 { Bad_Opcode },
4539 /* 38 */
4540 { Bad_Opcode },
4541 { Bad_Opcode },
4542 { Bad_Opcode },
4543 { Bad_Opcode },
4544 { Bad_Opcode },
4545 { Bad_Opcode },
4546 { Bad_Opcode },
4547 { Bad_Opcode },
4548 /* 40 */
4549 { "dpps", { XM, EXx, Ib }, PREFIX_DATA },
4550 { "dppd", { XM, EXx, Ib }, PREFIX_DATA },
4551 { "mpsadbw", { XM, EXx, Ib }, PREFIX_DATA },
4552 { Bad_Opcode },
4553 { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_DATA },
4554 { Bad_Opcode },
4555 { Bad_Opcode },
4556 { Bad_Opcode },
4557 /* 48 */
4558 { Bad_Opcode },
4559 { Bad_Opcode },
4560 { Bad_Opcode },
4561 { Bad_Opcode },
4562 { Bad_Opcode },
4563 { Bad_Opcode },
4564 { Bad_Opcode },
4565 { Bad_Opcode },
4566 /* 50 */
4567 { Bad_Opcode },
4568 { Bad_Opcode },
4569 { Bad_Opcode },
4570 { Bad_Opcode },
4571 { Bad_Opcode },
4572 { Bad_Opcode },
4573 { Bad_Opcode },
4574 { Bad_Opcode },
4575 /* 58 */
4576 { Bad_Opcode },
4577 { Bad_Opcode },
4578 { Bad_Opcode },
4579 { Bad_Opcode },
4580 { Bad_Opcode },
4581 { Bad_Opcode },
4582 { Bad_Opcode },
4583 { Bad_Opcode },
4584 /* 60 */
4585 { "pcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
4586 { "pcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
4587 { "pcmpistrm", { XM, EXx, Ib }, PREFIX_DATA },
4588 { "pcmpistri", { XM, EXx, Ib }, PREFIX_DATA },
4589 { Bad_Opcode },
4590 { Bad_Opcode },
4591 { Bad_Opcode },
4592 { Bad_Opcode },
4593 /* 68 */
4594 { Bad_Opcode },
4595 { Bad_Opcode },
4596 { Bad_Opcode },
4597 { Bad_Opcode },
4598 { Bad_Opcode },
4599 { Bad_Opcode },
4600 { Bad_Opcode },
4601 { Bad_Opcode },
4602 /* 70 */
4603 { Bad_Opcode },
4604 { Bad_Opcode },
4605 { Bad_Opcode },
4606 { Bad_Opcode },
4607 { Bad_Opcode },
4608 { Bad_Opcode },
4609 { Bad_Opcode },
4610 { Bad_Opcode },
4611 /* 78 */
4612 { Bad_Opcode },
4613 { Bad_Opcode },
4614 { Bad_Opcode },
4615 { Bad_Opcode },
4616 { Bad_Opcode },
4617 { Bad_Opcode },
4618 { Bad_Opcode },
4619 { Bad_Opcode },
4620 /* 80 */
4621 { Bad_Opcode },
4622 { Bad_Opcode },
4623 { Bad_Opcode },
4624 { Bad_Opcode },
4625 { Bad_Opcode },
4626 { Bad_Opcode },
4627 { Bad_Opcode },
4628 { Bad_Opcode },
4629 /* 88 */
4630 { Bad_Opcode },
4631 { Bad_Opcode },
4632 { Bad_Opcode },
4633 { Bad_Opcode },
4634 { Bad_Opcode },
4635 { Bad_Opcode },
4636 { Bad_Opcode },
4637 { Bad_Opcode },
4638 /* 90 */
4639 { Bad_Opcode },
4640 { Bad_Opcode },
4641 { Bad_Opcode },
4642 { Bad_Opcode },
4643 { Bad_Opcode },
4644 { Bad_Opcode },
4645 { Bad_Opcode },
4646 { Bad_Opcode },
4647 /* 98 */
4648 { Bad_Opcode },
4649 { Bad_Opcode },
4650 { Bad_Opcode },
4651 { Bad_Opcode },
4652 { Bad_Opcode },
4653 { Bad_Opcode },
4654 { Bad_Opcode },
4655 { Bad_Opcode },
4656 /* a0 */
4657 { Bad_Opcode },
4658 { Bad_Opcode },
4659 { Bad_Opcode },
4660 { Bad_Opcode },
4661 { Bad_Opcode },
4662 { Bad_Opcode },
4663 { Bad_Opcode },
4664 { Bad_Opcode },
4665 /* a8 */
4666 { Bad_Opcode },
4667 { Bad_Opcode },
4668 { Bad_Opcode },
4669 { Bad_Opcode },
4670 { Bad_Opcode },
4671 { Bad_Opcode },
4672 { Bad_Opcode },
4673 { Bad_Opcode },
4674 /* b0 */
4675 { Bad_Opcode },
4676 { Bad_Opcode },
4677 { Bad_Opcode },
4678 { Bad_Opcode },
4679 { Bad_Opcode },
4680 { Bad_Opcode },
4681 { Bad_Opcode },
4682 { Bad_Opcode },
4683 /* b8 */
4684 { Bad_Opcode },
4685 { Bad_Opcode },
4686 { Bad_Opcode },
4687 { Bad_Opcode },
4688 { Bad_Opcode },
4689 { Bad_Opcode },
4690 { Bad_Opcode },
4691 { Bad_Opcode },
4692 /* c0 */
4693 { Bad_Opcode },
4694 { Bad_Opcode },
4695 { Bad_Opcode },
4696 { Bad_Opcode },
4697 { Bad_Opcode },
4698 { Bad_Opcode },
4699 { Bad_Opcode },
4700 { Bad_Opcode },
4701 /* c8 */
4702 { Bad_Opcode },
4703 { Bad_Opcode },
4704 { Bad_Opcode },
4705 { Bad_Opcode },
4706 { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4707 { Bad_Opcode },
4708 { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_DATA },
4709 { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_DATA },
4710 /* d0 */
4711 { Bad_Opcode },
4712 { Bad_Opcode },
4713 { Bad_Opcode },
4714 { Bad_Opcode },
4715 { Bad_Opcode },
4716 { Bad_Opcode },
4717 { Bad_Opcode },
4718 { Bad_Opcode },
4719 /* d8 */
4720 { Bad_Opcode },
4721 { Bad_Opcode },
4722 { Bad_Opcode },
4723 { Bad_Opcode },
4724 { Bad_Opcode },
4725 { Bad_Opcode },
4726 { Bad_Opcode },
4727 { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
4728 /* e0 */
4729 { Bad_Opcode },
4730 { Bad_Opcode },
4731 { Bad_Opcode },
4732 { Bad_Opcode },
4733 { Bad_Opcode },
4734 { Bad_Opcode },
4735 { Bad_Opcode },
4736 { Bad_Opcode },
4737 /* e8 */
4738 { Bad_Opcode },
4739 { Bad_Opcode },
4740 { Bad_Opcode },
4741 { Bad_Opcode },
4742 { Bad_Opcode },
4743 { Bad_Opcode },
4744 { Bad_Opcode },
4745 { Bad_Opcode },
4746 /* f0 */
4747 { Bad_Opcode },
4748 { Bad_Opcode },
4749 { Bad_Opcode },
4750 { Bad_Opcode },
4751 { Bad_Opcode },
4752 { Bad_Opcode },
4753 { Bad_Opcode },
4754 { Bad_Opcode },
4755 /* f8 */
4756 { Bad_Opcode },
4757 { Bad_Opcode },
4758 { Bad_Opcode },
4759 { Bad_Opcode },
4760 { Bad_Opcode },
4761 { Bad_Opcode },
4762 { Bad_Opcode },
4763 { Bad_Opcode },
4764 },
4765 };
4766
4767 static const struct dis386 xop_table[][256] = {
4768 /* XOP_08 */
4769 {
4770 /* 00 */
4771 { Bad_Opcode },
4772 { Bad_Opcode },
4773 { Bad_Opcode },
4774 { Bad_Opcode },
4775 { Bad_Opcode },
4776 { Bad_Opcode },
4777 { Bad_Opcode },
4778 { Bad_Opcode },
4779 /* 08 */
4780 { Bad_Opcode },
4781 { Bad_Opcode },
4782 { Bad_Opcode },
4783 { Bad_Opcode },
4784 { Bad_Opcode },
4785 { Bad_Opcode },
4786 { Bad_Opcode },
4787 { Bad_Opcode },
4788 /* 10 */
4789 { Bad_Opcode },
4790 { Bad_Opcode },
4791 { Bad_Opcode },
4792 { Bad_Opcode },
4793 { Bad_Opcode },
4794 { Bad_Opcode },
4795 { Bad_Opcode },
4796 { Bad_Opcode },
4797 /* 18 */
4798 { Bad_Opcode },
4799 { Bad_Opcode },
4800 { Bad_Opcode },
4801 { Bad_Opcode },
4802 { Bad_Opcode },
4803 { Bad_Opcode },
4804 { Bad_Opcode },
4805 { Bad_Opcode },
4806 /* 20 */
4807 { Bad_Opcode },
4808 { Bad_Opcode },
4809 { Bad_Opcode },
4810 { Bad_Opcode },
4811 { Bad_Opcode },
4812 { Bad_Opcode },
4813 { Bad_Opcode },
4814 { Bad_Opcode },
4815 /* 28 */
4816 { Bad_Opcode },
4817 { Bad_Opcode },
4818 { Bad_Opcode },
4819 { Bad_Opcode },
4820 { Bad_Opcode },
4821 { Bad_Opcode },
4822 { Bad_Opcode },
4823 { Bad_Opcode },
4824 /* 30 */
4825 { Bad_Opcode },
4826 { Bad_Opcode },
4827 { Bad_Opcode },
4828 { Bad_Opcode },
4829 { Bad_Opcode },
4830 { Bad_Opcode },
4831 { Bad_Opcode },
4832 { Bad_Opcode },
4833 /* 38 */
4834 { Bad_Opcode },
4835 { Bad_Opcode },
4836 { Bad_Opcode },
4837 { Bad_Opcode },
4838 { Bad_Opcode },
4839 { Bad_Opcode },
4840 { Bad_Opcode },
4841 { Bad_Opcode },
4842 /* 40 */
4843 { Bad_Opcode },
4844 { Bad_Opcode },
4845 { Bad_Opcode },
4846 { Bad_Opcode },
4847 { Bad_Opcode },
4848 { Bad_Opcode },
4849 { Bad_Opcode },
4850 { Bad_Opcode },
4851 /* 48 */
4852 { Bad_Opcode },
4853 { Bad_Opcode },
4854 { Bad_Opcode },
4855 { Bad_Opcode },
4856 { Bad_Opcode },
4857 { Bad_Opcode },
4858 { Bad_Opcode },
4859 { Bad_Opcode },
4860 /* 50 */
4861 { Bad_Opcode },
4862 { Bad_Opcode },
4863 { Bad_Opcode },
4864 { Bad_Opcode },
4865 { Bad_Opcode },
4866 { Bad_Opcode },
4867 { Bad_Opcode },
4868 { Bad_Opcode },
4869 /* 58 */
4870 { Bad_Opcode },
4871 { Bad_Opcode },
4872 { Bad_Opcode },
4873 { Bad_Opcode },
4874 { Bad_Opcode },
4875 { Bad_Opcode },
4876 { Bad_Opcode },
4877 { Bad_Opcode },
4878 /* 60 */
4879 { Bad_Opcode },
4880 { Bad_Opcode },
4881 { Bad_Opcode },
4882 { Bad_Opcode },
4883 { Bad_Opcode },
4884 { Bad_Opcode },
4885 { Bad_Opcode },
4886 { Bad_Opcode },
4887 /* 68 */
4888 { Bad_Opcode },
4889 { Bad_Opcode },
4890 { Bad_Opcode },
4891 { Bad_Opcode },
4892 { Bad_Opcode },
4893 { Bad_Opcode },
4894 { Bad_Opcode },
4895 { Bad_Opcode },
4896 /* 70 */
4897 { Bad_Opcode },
4898 { Bad_Opcode },
4899 { Bad_Opcode },
4900 { Bad_Opcode },
4901 { Bad_Opcode },
4902 { Bad_Opcode },
4903 { Bad_Opcode },
4904 { Bad_Opcode },
4905 /* 78 */
4906 { Bad_Opcode },
4907 { Bad_Opcode },
4908 { Bad_Opcode },
4909 { Bad_Opcode },
4910 { Bad_Opcode },
4911 { Bad_Opcode },
4912 { Bad_Opcode },
4913 { Bad_Opcode },
4914 /* 80 */
4915 { Bad_Opcode },
4916 { Bad_Opcode },
4917 { Bad_Opcode },
4918 { Bad_Opcode },
4919 { Bad_Opcode },
4920 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_85) },
4921 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_86) },
4922 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_87) },
4923 /* 88 */
4924 { Bad_Opcode },
4925 { Bad_Opcode },
4926 { Bad_Opcode },
4927 { Bad_Opcode },
4928 { Bad_Opcode },
4929 { Bad_Opcode },
4930 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8E) },
4931 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8F) },
4932 /* 90 */
4933 { Bad_Opcode },
4934 { Bad_Opcode },
4935 { Bad_Opcode },
4936 { Bad_Opcode },
4937 { Bad_Opcode },
4938 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_95) },
4939 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_96) },
4940 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_97) },
4941 /* 98 */
4942 { Bad_Opcode },
4943 { Bad_Opcode },
4944 { Bad_Opcode },
4945 { Bad_Opcode },
4946 { Bad_Opcode },
4947 { Bad_Opcode },
4948 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9E) },
4949 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9F) },
4950 /* a0 */
4951 { Bad_Opcode },
4952 { Bad_Opcode },
4953 { "vpcmov", { XM, Vex, EXx, XMVexI4 }, 0 },
4954 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A3) },
4955 { Bad_Opcode },
4956 { Bad_Opcode },
4957 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A6) },
4958 { Bad_Opcode },
4959 /* a8 */
4960 { Bad_Opcode },
4961 { Bad_Opcode },
4962 { Bad_Opcode },
4963 { Bad_Opcode },
4964 { Bad_Opcode },
4965 { Bad_Opcode },
4966 { Bad_Opcode },
4967 { Bad_Opcode },
4968 /* b0 */
4969 { Bad_Opcode },
4970 { Bad_Opcode },
4971 { Bad_Opcode },
4972 { Bad_Opcode },
4973 { Bad_Opcode },
4974 { Bad_Opcode },
4975 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_B6) },
4976 { Bad_Opcode },
4977 /* b8 */
4978 { Bad_Opcode },
4979 { Bad_Opcode },
4980 { Bad_Opcode },
4981 { Bad_Opcode },
4982 { Bad_Opcode },
4983 { Bad_Opcode },
4984 { Bad_Opcode },
4985 { Bad_Opcode },
4986 /* c0 */
4987 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C0) },
4988 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C1) },
4989 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C2) },
4990 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C3) },
4991 { Bad_Opcode },
4992 { Bad_Opcode },
4993 { Bad_Opcode },
4994 { Bad_Opcode },
4995 /* c8 */
4996 { Bad_Opcode },
4997 { Bad_Opcode },
4998 { Bad_Opcode },
4999 { Bad_Opcode },
5000 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
5001 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
5002 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
5003 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
5004 /* d0 */
5005 { Bad_Opcode },
5006 { Bad_Opcode },
5007 { Bad_Opcode },
5008 { Bad_Opcode },
5009 { Bad_Opcode },
5010 { Bad_Opcode },
5011 { Bad_Opcode },
5012 { Bad_Opcode },
5013 /* d8 */
5014 { Bad_Opcode },
5015 { Bad_Opcode },
5016 { Bad_Opcode },
5017 { Bad_Opcode },
5018 { Bad_Opcode },
5019 { Bad_Opcode },
5020 { Bad_Opcode },
5021 { Bad_Opcode },
5022 /* e0 */
5023 { Bad_Opcode },
5024 { Bad_Opcode },
5025 { Bad_Opcode },
5026 { Bad_Opcode },
5027 { Bad_Opcode },
5028 { Bad_Opcode },
5029 { Bad_Opcode },
5030 { Bad_Opcode },
5031 /* e8 */
5032 { Bad_Opcode },
5033 { Bad_Opcode },
5034 { Bad_Opcode },
5035 { Bad_Opcode },
5036 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
5037 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
5038 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
5039 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
5040 /* f0 */
5041 { Bad_Opcode },
5042 { Bad_Opcode },
5043 { Bad_Opcode },
5044 { Bad_Opcode },
5045 { Bad_Opcode },
5046 { Bad_Opcode },
5047 { Bad_Opcode },
5048 { Bad_Opcode },
5049 /* f8 */
5050 { Bad_Opcode },
5051 { Bad_Opcode },
5052 { Bad_Opcode },
5053 { Bad_Opcode },
5054 { Bad_Opcode },
5055 { Bad_Opcode },
5056 { Bad_Opcode },
5057 { Bad_Opcode },
5058 },
5059 /* XOP_09 */
5060 {
5061 /* 00 */
5062 { Bad_Opcode },
5063 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_01) },
5064 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_02) },
5065 { Bad_Opcode },
5066 { Bad_Opcode },
5067 { Bad_Opcode },
5068 { Bad_Opcode },
5069 { Bad_Opcode },
5070 /* 08 */
5071 { Bad_Opcode },
5072 { Bad_Opcode },
5073 { Bad_Opcode },
5074 { Bad_Opcode },
5075 { Bad_Opcode },
5076 { Bad_Opcode },
5077 { Bad_Opcode },
5078 { Bad_Opcode },
5079 /* 10 */
5080 { Bad_Opcode },
5081 { Bad_Opcode },
5082 { MOD_TABLE (MOD_VEX_0FXOP_09_12) },
5083 { Bad_Opcode },
5084 { Bad_Opcode },
5085 { Bad_Opcode },
5086 { Bad_Opcode },
5087 { Bad_Opcode },
5088 /* 18 */
5089 { Bad_Opcode },
5090 { Bad_Opcode },
5091 { Bad_Opcode },
5092 { Bad_Opcode },
5093 { Bad_Opcode },
5094 { Bad_Opcode },
5095 { Bad_Opcode },
5096 { Bad_Opcode },
5097 /* 20 */
5098 { Bad_Opcode },
5099 { Bad_Opcode },
5100 { Bad_Opcode },
5101 { Bad_Opcode },
5102 { Bad_Opcode },
5103 { Bad_Opcode },
5104 { Bad_Opcode },
5105 { Bad_Opcode },
5106 /* 28 */
5107 { Bad_Opcode },
5108 { Bad_Opcode },
5109 { Bad_Opcode },
5110 { Bad_Opcode },
5111 { Bad_Opcode },
5112 { Bad_Opcode },
5113 { Bad_Opcode },
5114 { Bad_Opcode },
5115 /* 30 */
5116 { Bad_Opcode },
5117 { Bad_Opcode },
5118 { Bad_Opcode },
5119 { Bad_Opcode },
5120 { Bad_Opcode },
5121 { Bad_Opcode },
5122 { Bad_Opcode },
5123 { Bad_Opcode },
5124 /* 38 */
5125 { Bad_Opcode },
5126 { Bad_Opcode },
5127 { Bad_Opcode },
5128 { Bad_Opcode },
5129 { Bad_Opcode },
5130 { Bad_Opcode },
5131 { Bad_Opcode },
5132 { Bad_Opcode },
5133 /* 40 */
5134 { Bad_Opcode },
5135 { Bad_Opcode },
5136 { Bad_Opcode },
5137 { Bad_Opcode },
5138 { Bad_Opcode },
5139 { Bad_Opcode },
5140 { Bad_Opcode },
5141 { Bad_Opcode },
5142 /* 48 */
5143 { Bad_Opcode },
5144 { Bad_Opcode },
5145 { Bad_Opcode },
5146 { Bad_Opcode },
5147 { Bad_Opcode },
5148 { Bad_Opcode },
5149 { Bad_Opcode },
5150 { Bad_Opcode },
5151 /* 50 */
5152 { Bad_Opcode },
5153 { Bad_Opcode },
5154 { Bad_Opcode },
5155 { Bad_Opcode },
5156 { Bad_Opcode },
5157 { Bad_Opcode },
5158 { Bad_Opcode },
5159 { Bad_Opcode },
5160 /* 58 */
5161 { Bad_Opcode },
5162 { Bad_Opcode },
5163 { Bad_Opcode },
5164 { Bad_Opcode },
5165 { Bad_Opcode },
5166 { Bad_Opcode },
5167 { Bad_Opcode },
5168 { Bad_Opcode },
5169 /* 60 */
5170 { Bad_Opcode },
5171 { Bad_Opcode },
5172 { Bad_Opcode },
5173 { Bad_Opcode },
5174 { Bad_Opcode },
5175 { Bad_Opcode },
5176 { Bad_Opcode },
5177 { Bad_Opcode },
5178 /* 68 */
5179 { Bad_Opcode },
5180 { Bad_Opcode },
5181 { Bad_Opcode },
5182 { Bad_Opcode },
5183 { Bad_Opcode },
5184 { Bad_Opcode },
5185 { Bad_Opcode },
5186 { Bad_Opcode },
5187 /* 70 */
5188 { Bad_Opcode },
5189 { Bad_Opcode },
5190 { Bad_Opcode },
5191 { Bad_Opcode },
5192 { Bad_Opcode },
5193 { Bad_Opcode },
5194 { Bad_Opcode },
5195 { Bad_Opcode },
5196 /* 78 */
5197 { Bad_Opcode },
5198 { Bad_Opcode },
5199 { Bad_Opcode },
5200 { Bad_Opcode },
5201 { Bad_Opcode },
5202 { Bad_Opcode },
5203 { Bad_Opcode },
5204 { Bad_Opcode },
5205 /* 80 */
5206 { VEX_W_TABLE (VEX_W_0FXOP_09_80) },
5207 { VEX_W_TABLE (VEX_W_0FXOP_09_81) },
5208 { VEX_W_TABLE (VEX_W_0FXOP_09_82) },
5209 { VEX_W_TABLE (VEX_W_0FXOP_09_83) },
5210 { Bad_Opcode },
5211 { Bad_Opcode },
5212 { Bad_Opcode },
5213 { Bad_Opcode },
5214 /* 88 */
5215 { Bad_Opcode },
5216 { Bad_Opcode },
5217 { Bad_Opcode },
5218 { Bad_Opcode },
5219 { Bad_Opcode },
5220 { Bad_Opcode },
5221 { Bad_Opcode },
5222 { Bad_Opcode },
5223 /* 90 */
5224 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_90) },
5225 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_91) },
5226 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_92) },
5227 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_93) },
5228 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_94) },
5229 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_95) },
5230 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_96) },
5231 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_97) },
5232 /* 98 */
5233 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_98) },
5234 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_99) },
5235 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9A) },
5236 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9B) },
5237 { Bad_Opcode },
5238 { Bad_Opcode },
5239 { Bad_Opcode },
5240 { Bad_Opcode },
5241 /* a0 */
5242 { Bad_Opcode },
5243 { Bad_Opcode },
5244 { Bad_Opcode },
5245 { Bad_Opcode },
5246 { Bad_Opcode },
5247 { Bad_Opcode },
5248 { Bad_Opcode },
5249 { Bad_Opcode },
5250 /* a8 */
5251 { Bad_Opcode },
5252 { Bad_Opcode },
5253 { Bad_Opcode },
5254 { Bad_Opcode },
5255 { Bad_Opcode },
5256 { Bad_Opcode },
5257 { Bad_Opcode },
5258 { Bad_Opcode },
5259 /* b0 */
5260 { Bad_Opcode },
5261 { Bad_Opcode },
5262 { Bad_Opcode },
5263 { Bad_Opcode },
5264 { Bad_Opcode },
5265 { Bad_Opcode },
5266 { Bad_Opcode },
5267 { Bad_Opcode },
5268 /* b8 */
5269 { Bad_Opcode },
5270 { Bad_Opcode },
5271 { Bad_Opcode },
5272 { Bad_Opcode },
5273 { Bad_Opcode },
5274 { Bad_Opcode },
5275 { Bad_Opcode },
5276 { Bad_Opcode },
5277 /* c0 */
5278 { Bad_Opcode },
5279 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C1) },
5280 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C2) },
5281 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C3) },
5282 { Bad_Opcode },
5283 { Bad_Opcode },
5284 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C6) },
5285 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C7) },
5286 /* c8 */
5287 { Bad_Opcode },
5288 { Bad_Opcode },
5289 { Bad_Opcode },
5290 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_CB) },
5291 { Bad_Opcode },
5292 { Bad_Opcode },
5293 { Bad_Opcode },
5294 { Bad_Opcode },
5295 /* d0 */
5296 { Bad_Opcode },
5297 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D1) },
5298 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D2) },
5299 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D3) },
5300 { Bad_Opcode },
5301 { Bad_Opcode },
5302 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D6) },
5303 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D7) },
5304 /* d8 */
5305 { Bad_Opcode },
5306 { Bad_Opcode },
5307 { Bad_Opcode },
5308 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_DB) },
5309 { Bad_Opcode },
5310 { Bad_Opcode },
5311 { Bad_Opcode },
5312 { Bad_Opcode },
5313 /* e0 */
5314 { Bad_Opcode },
5315 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E1) },
5316 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E2) },
5317 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E3) },
5318 { Bad_Opcode },
5319 { Bad_Opcode },
5320 { Bad_Opcode },
5321 { Bad_Opcode },
5322 /* e8 */
5323 { Bad_Opcode },
5324 { Bad_Opcode },
5325 { Bad_Opcode },
5326 { Bad_Opcode },
5327 { Bad_Opcode },
5328 { Bad_Opcode },
5329 { Bad_Opcode },
5330 { Bad_Opcode },
5331 /* f0 */
5332 { Bad_Opcode },
5333 { Bad_Opcode },
5334 { Bad_Opcode },
5335 { Bad_Opcode },
5336 { Bad_Opcode },
5337 { Bad_Opcode },
5338 { Bad_Opcode },
5339 { Bad_Opcode },
5340 /* f8 */
5341 { Bad_Opcode },
5342 { Bad_Opcode },
5343 { Bad_Opcode },
5344 { Bad_Opcode },
5345 { Bad_Opcode },
5346 { Bad_Opcode },
5347 { Bad_Opcode },
5348 { Bad_Opcode },
5349 },
5350 /* XOP_0A */
5351 {
5352 /* 00 */
5353 { Bad_Opcode },
5354 { Bad_Opcode },
5355 { Bad_Opcode },
5356 { Bad_Opcode },
5357 { Bad_Opcode },
5358 { Bad_Opcode },
5359 { Bad_Opcode },
5360 { Bad_Opcode },
5361 /* 08 */
5362 { Bad_Opcode },
5363 { Bad_Opcode },
5364 { Bad_Opcode },
5365 { Bad_Opcode },
5366 { Bad_Opcode },
5367 { Bad_Opcode },
5368 { Bad_Opcode },
5369 { Bad_Opcode },
5370 /* 10 */
5371 { "bextrS", { Gdq, Edq, Id }, 0 },
5372 { Bad_Opcode },
5373 { VEX_LEN_TABLE (VEX_LEN_0FXOP_0A_12) },
5374 { Bad_Opcode },
5375 { Bad_Opcode },
5376 { Bad_Opcode },
5377 { Bad_Opcode },
5378 { Bad_Opcode },
5379 /* 18 */
5380 { Bad_Opcode },
5381 { Bad_Opcode },
5382 { Bad_Opcode },
5383 { Bad_Opcode },
5384 { Bad_Opcode },
5385 { Bad_Opcode },
5386 { Bad_Opcode },
5387 { Bad_Opcode },
5388 /* 20 */
5389 { Bad_Opcode },
5390 { Bad_Opcode },
5391 { Bad_Opcode },
5392 { Bad_Opcode },
5393 { Bad_Opcode },
5394 { Bad_Opcode },
5395 { Bad_Opcode },
5396 { Bad_Opcode },
5397 /* 28 */
5398 { Bad_Opcode },
5399 { Bad_Opcode },
5400 { Bad_Opcode },
5401 { Bad_Opcode },
5402 { Bad_Opcode },
5403 { Bad_Opcode },
5404 { Bad_Opcode },
5405 { Bad_Opcode },
5406 /* 30 */
5407 { Bad_Opcode },
5408 { Bad_Opcode },
5409 { Bad_Opcode },
5410 { Bad_Opcode },
5411 { Bad_Opcode },
5412 { Bad_Opcode },
5413 { Bad_Opcode },
5414 { Bad_Opcode },
5415 /* 38 */
5416 { Bad_Opcode },
5417 { Bad_Opcode },
5418 { Bad_Opcode },
5419 { Bad_Opcode },
5420 { Bad_Opcode },
5421 { Bad_Opcode },
5422 { Bad_Opcode },
5423 { Bad_Opcode },
5424 /* 40 */
5425 { Bad_Opcode },
5426 { Bad_Opcode },
5427 { Bad_Opcode },
5428 { Bad_Opcode },
5429 { Bad_Opcode },
5430 { Bad_Opcode },
5431 { Bad_Opcode },
5432 { Bad_Opcode },
5433 /* 48 */
5434 { Bad_Opcode },
5435 { Bad_Opcode },
5436 { Bad_Opcode },
5437 { Bad_Opcode },
5438 { Bad_Opcode },
5439 { Bad_Opcode },
5440 { Bad_Opcode },
5441 { Bad_Opcode },
5442 /* 50 */
5443 { Bad_Opcode },
5444 { Bad_Opcode },
5445 { Bad_Opcode },
5446 { Bad_Opcode },
5447 { Bad_Opcode },
5448 { Bad_Opcode },
5449 { Bad_Opcode },
5450 { Bad_Opcode },
5451 /* 58 */
5452 { Bad_Opcode },
5453 { Bad_Opcode },
5454 { Bad_Opcode },
5455 { Bad_Opcode },
5456 { Bad_Opcode },
5457 { Bad_Opcode },
5458 { Bad_Opcode },
5459 { Bad_Opcode },
5460 /* 60 */
5461 { Bad_Opcode },
5462 { Bad_Opcode },
5463 { Bad_Opcode },
5464 { Bad_Opcode },
5465 { Bad_Opcode },
5466 { Bad_Opcode },
5467 { Bad_Opcode },
5468 { Bad_Opcode },
5469 /* 68 */
5470 { Bad_Opcode },
5471 { Bad_Opcode },
5472 { Bad_Opcode },
5473 { Bad_Opcode },
5474 { Bad_Opcode },
5475 { Bad_Opcode },
5476 { Bad_Opcode },
5477 { Bad_Opcode },
5478 /* 70 */
5479 { Bad_Opcode },
5480 { Bad_Opcode },
5481 { Bad_Opcode },
5482 { Bad_Opcode },
5483 { Bad_Opcode },
5484 { Bad_Opcode },
5485 { Bad_Opcode },
5486 { Bad_Opcode },
5487 /* 78 */
5488 { Bad_Opcode },
5489 { Bad_Opcode },
5490 { Bad_Opcode },
5491 { Bad_Opcode },
5492 { Bad_Opcode },
5493 { Bad_Opcode },
5494 { Bad_Opcode },
5495 { Bad_Opcode },
5496 /* 80 */
5497 { Bad_Opcode },
5498 { Bad_Opcode },
5499 { Bad_Opcode },
5500 { Bad_Opcode },
5501 { Bad_Opcode },
5502 { Bad_Opcode },
5503 { Bad_Opcode },
5504 { Bad_Opcode },
5505 /* 88 */
5506 { Bad_Opcode },
5507 { Bad_Opcode },
5508 { Bad_Opcode },
5509 { Bad_Opcode },
5510 { Bad_Opcode },
5511 { Bad_Opcode },
5512 { Bad_Opcode },
5513 { Bad_Opcode },
5514 /* 90 */
5515 { Bad_Opcode },
5516 { Bad_Opcode },
5517 { Bad_Opcode },
5518 { Bad_Opcode },
5519 { Bad_Opcode },
5520 { Bad_Opcode },
5521 { Bad_Opcode },
5522 { Bad_Opcode },
5523 /* 98 */
5524 { Bad_Opcode },
5525 { Bad_Opcode },
5526 { Bad_Opcode },
5527 { Bad_Opcode },
5528 { Bad_Opcode },
5529 { Bad_Opcode },
5530 { Bad_Opcode },
5531 { Bad_Opcode },
5532 /* a0 */
5533 { Bad_Opcode },
5534 { Bad_Opcode },
5535 { Bad_Opcode },
5536 { Bad_Opcode },
5537 { Bad_Opcode },
5538 { Bad_Opcode },
5539 { Bad_Opcode },
5540 { Bad_Opcode },
5541 /* a8 */
5542 { Bad_Opcode },
5543 { Bad_Opcode },
5544 { Bad_Opcode },
5545 { Bad_Opcode },
5546 { Bad_Opcode },
5547 { Bad_Opcode },
5548 { Bad_Opcode },
5549 { Bad_Opcode },
5550 /* b0 */
5551 { Bad_Opcode },
5552 { Bad_Opcode },
5553 { Bad_Opcode },
5554 { Bad_Opcode },
5555 { Bad_Opcode },
5556 { Bad_Opcode },
5557 { Bad_Opcode },
5558 { Bad_Opcode },
5559 /* b8 */
5560 { Bad_Opcode },
5561 { Bad_Opcode },
5562 { Bad_Opcode },
5563 { Bad_Opcode },
5564 { Bad_Opcode },
5565 { Bad_Opcode },
5566 { Bad_Opcode },
5567 { Bad_Opcode },
5568 /* c0 */
5569 { Bad_Opcode },
5570 { Bad_Opcode },
5571 { Bad_Opcode },
5572 { Bad_Opcode },
5573 { Bad_Opcode },
5574 { Bad_Opcode },
5575 { Bad_Opcode },
5576 { Bad_Opcode },
5577 /* c8 */
5578 { Bad_Opcode },
5579 { Bad_Opcode },
5580 { Bad_Opcode },
5581 { Bad_Opcode },
5582 { Bad_Opcode },
5583 { Bad_Opcode },
5584 { Bad_Opcode },
5585 { Bad_Opcode },
5586 /* d0 */
5587 { Bad_Opcode },
5588 { Bad_Opcode },
5589 { Bad_Opcode },
5590 { Bad_Opcode },
5591 { Bad_Opcode },
5592 { Bad_Opcode },
5593 { Bad_Opcode },
5594 { Bad_Opcode },
5595 /* d8 */
5596 { Bad_Opcode },
5597 { Bad_Opcode },
5598 { Bad_Opcode },
5599 { Bad_Opcode },
5600 { Bad_Opcode },
5601 { Bad_Opcode },
5602 { Bad_Opcode },
5603 { Bad_Opcode },
5604 /* e0 */
5605 { Bad_Opcode },
5606 { Bad_Opcode },
5607 { Bad_Opcode },
5608 { Bad_Opcode },
5609 { Bad_Opcode },
5610 { Bad_Opcode },
5611 { Bad_Opcode },
5612 { Bad_Opcode },
5613 /* e8 */
5614 { Bad_Opcode },
5615 { Bad_Opcode },
5616 { Bad_Opcode },
5617 { Bad_Opcode },
5618 { Bad_Opcode },
5619 { Bad_Opcode },
5620 { Bad_Opcode },
5621 { Bad_Opcode },
5622 /* f0 */
5623 { Bad_Opcode },
5624 { Bad_Opcode },
5625 { Bad_Opcode },
5626 { Bad_Opcode },
5627 { Bad_Opcode },
5628 { Bad_Opcode },
5629 { Bad_Opcode },
5630 { Bad_Opcode },
5631 /* f8 */
5632 { Bad_Opcode },
5633 { Bad_Opcode },
5634 { Bad_Opcode },
5635 { Bad_Opcode },
5636 { Bad_Opcode },
5637 { Bad_Opcode },
5638 { Bad_Opcode },
5639 { Bad_Opcode },
5640 },
5641 };
5642
5643 static const struct dis386 vex_table[][256] = {
5644 /* VEX_0F */
5645 {
5646 /* 00 */
5647 { Bad_Opcode },
5648 { Bad_Opcode },
5649 { Bad_Opcode },
5650 { Bad_Opcode },
5651 { Bad_Opcode },
5652 { Bad_Opcode },
5653 { Bad_Opcode },
5654 { Bad_Opcode },
5655 /* 08 */
5656 { Bad_Opcode },
5657 { Bad_Opcode },
5658 { Bad_Opcode },
5659 { Bad_Opcode },
5660 { Bad_Opcode },
5661 { Bad_Opcode },
5662 { Bad_Opcode },
5663 { Bad_Opcode },
5664 /* 10 */
5665 { PREFIX_TABLE (PREFIX_VEX_0F10) },
5666 { PREFIX_TABLE (PREFIX_VEX_0F11) },
5667 { PREFIX_TABLE (PREFIX_VEX_0F12) },
5668 { MOD_TABLE (MOD_VEX_0F13) },
5669 { "vunpcklpX", { XM, Vex, EXx }, PREFIX_OPCODE },
5670 { "vunpckhpX", { XM, Vex, EXx }, PREFIX_OPCODE },
5671 { PREFIX_TABLE (PREFIX_VEX_0F16) },
5672 { MOD_TABLE (MOD_VEX_0F17) },
5673 /* 18 */
5674 { Bad_Opcode },
5675 { Bad_Opcode },
5676 { Bad_Opcode },
5677 { Bad_Opcode },
5678 { Bad_Opcode },
5679 { Bad_Opcode },
5680 { Bad_Opcode },
5681 { Bad_Opcode },
5682 /* 20 */
5683 { Bad_Opcode },
5684 { Bad_Opcode },
5685 { Bad_Opcode },
5686 { Bad_Opcode },
5687 { Bad_Opcode },
5688 { Bad_Opcode },
5689 { Bad_Opcode },
5690 { Bad_Opcode },
5691 /* 28 */
5692 { "vmovapX", { XM, EXx }, PREFIX_OPCODE },
5693 { "vmovapX", { EXxS, XM }, PREFIX_OPCODE },
5694 { PREFIX_TABLE (PREFIX_VEX_0F2A) },
5695 { MOD_TABLE (MOD_VEX_0F2B) },
5696 { PREFIX_TABLE (PREFIX_VEX_0F2C) },
5697 { PREFIX_TABLE (PREFIX_VEX_0F2D) },
5698 { PREFIX_TABLE (PREFIX_VEX_0F2E) },
5699 { PREFIX_TABLE (PREFIX_VEX_0F2F) },
5700 /* 30 */
5701 { Bad_Opcode },
5702 { Bad_Opcode },
5703 { Bad_Opcode },
5704 { Bad_Opcode },
5705 { Bad_Opcode },
5706 { Bad_Opcode },
5707 { Bad_Opcode },
5708 { Bad_Opcode },
5709 /* 38 */
5710 { Bad_Opcode },
5711 { Bad_Opcode },
5712 { Bad_Opcode },
5713 { Bad_Opcode },
5714 { Bad_Opcode },
5715 { Bad_Opcode },
5716 { Bad_Opcode },
5717 { Bad_Opcode },
5718 /* 40 */
5719 { Bad_Opcode },
5720 { PREFIX_TABLE (PREFIX_VEX_0F41) },
5721 { PREFIX_TABLE (PREFIX_VEX_0F42) },
5722 { Bad_Opcode },
5723 { PREFIX_TABLE (PREFIX_VEX_0F44) },
5724 { PREFIX_TABLE (PREFIX_VEX_0F45) },
5725 { PREFIX_TABLE (PREFIX_VEX_0F46) },
5726 { PREFIX_TABLE (PREFIX_VEX_0F47) },
5727 /* 48 */
5728 { Bad_Opcode },
5729 { Bad_Opcode },
5730 { PREFIX_TABLE (PREFIX_VEX_0F4A) },
5731 { PREFIX_TABLE (PREFIX_VEX_0F4B) },
5732 { Bad_Opcode },
5733 { Bad_Opcode },
5734 { Bad_Opcode },
5735 { Bad_Opcode },
5736 /* 50 */
5737 { MOD_TABLE (MOD_VEX_0F50) },
5738 { PREFIX_TABLE (PREFIX_VEX_0F51) },
5739 { PREFIX_TABLE (PREFIX_VEX_0F52) },
5740 { PREFIX_TABLE (PREFIX_VEX_0F53) },
5741 { "vandpX", { XM, Vex, EXx }, PREFIX_OPCODE },
5742 { "vandnpX", { XM, Vex, EXx }, PREFIX_OPCODE },
5743 { "vorpX", { XM, Vex, EXx }, PREFIX_OPCODE },
5744 { "vxorpX", { XM, Vex, EXx }, PREFIX_OPCODE },
5745 /* 58 */
5746 { PREFIX_TABLE (PREFIX_VEX_0F58) },
5747 { PREFIX_TABLE (PREFIX_VEX_0F59) },
5748 { PREFIX_TABLE (PREFIX_VEX_0F5A) },
5749 { PREFIX_TABLE (PREFIX_VEX_0F5B) },
5750 { PREFIX_TABLE (PREFIX_VEX_0F5C) },
5751 { PREFIX_TABLE (PREFIX_VEX_0F5D) },
5752 { PREFIX_TABLE (PREFIX_VEX_0F5E) },
5753 { PREFIX_TABLE (PREFIX_VEX_0F5F) },
5754 /* 60 */
5755 { "vpunpcklbw", { XM, Vex, EXx }, PREFIX_DATA },
5756 { "vpunpcklwd", { XM, Vex, EXx }, PREFIX_DATA },
5757 { "vpunpckldq", { XM, Vex, EXx }, PREFIX_DATA },
5758 { "vpacksswb", { XM, Vex, EXx }, PREFIX_DATA },
5759 { "vpcmpgtb", { XM, Vex, EXx }, PREFIX_DATA },
5760 { "vpcmpgtw", { XM, Vex, EXx }, PREFIX_DATA },
5761 { "vpcmpgtd", { XM, Vex, EXx }, PREFIX_DATA },
5762 { "vpackuswb", { XM, Vex, EXx }, PREFIX_DATA },
5763 /* 68 */
5764 { "vpunpckhbw", { XM, Vex, EXx }, PREFIX_DATA },
5765 { "vpunpckhwd", { XM, Vex, EXx }, PREFIX_DATA },
5766 { "vpunpckhdq", { XM, Vex, EXx }, PREFIX_DATA },
5767 { "vpackssdw", { XM, Vex, EXx }, PREFIX_DATA },
5768 { "vpunpcklqdq", { XM, Vex, EXx }, PREFIX_DATA },
5769 { "vpunpckhqdq", { XM, Vex, EXx }, PREFIX_DATA },
5770 { VEX_LEN_TABLE (VEX_LEN_0F6E) },
5771 { PREFIX_TABLE (PREFIX_VEX_0F6F) },
5772 /* 70 */
5773 { PREFIX_TABLE (PREFIX_VEX_0F70) },
5774 { REG_TABLE (REG_VEX_0F71) },
5775 { REG_TABLE (REG_VEX_0F72) },
5776 { REG_TABLE (REG_VEX_0F73) },
5777 { "vpcmpeqb", { XM, Vex, EXx }, PREFIX_DATA },
5778 { "vpcmpeqw", { XM, Vex, EXx }, PREFIX_DATA },
5779 { "vpcmpeqd", { XM, Vex, EXx }, PREFIX_DATA },
5780 { VEX_LEN_TABLE (VEX_LEN_0F77) },
5781 /* 78 */
5782 { Bad_Opcode },
5783 { Bad_Opcode },
5784 { Bad_Opcode },
5785 { Bad_Opcode },
5786 { PREFIX_TABLE (PREFIX_VEX_0F7C) },
5787 { PREFIX_TABLE (PREFIX_VEX_0F7D) },
5788 { PREFIX_TABLE (PREFIX_VEX_0F7E) },
5789 { PREFIX_TABLE (PREFIX_VEX_0F7F) },
5790 /* 80 */
5791 { Bad_Opcode },
5792 { Bad_Opcode },
5793 { Bad_Opcode },
5794 { Bad_Opcode },
5795 { Bad_Opcode },
5796 { Bad_Opcode },
5797 { Bad_Opcode },
5798 { Bad_Opcode },
5799 /* 88 */
5800 { Bad_Opcode },
5801 { Bad_Opcode },
5802 { Bad_Opcode },
5803 { Bad_Opcode },
5804 { Bad_Opcode },
5805 { Bad_Opcode },
5806 { Bad_Opcode },
5807 { Bad_Opcode },
5808 /* 90 */
5809 { PREFIX_TABLE (PREFIX_VEX_0F90) },
5810 { PREFIX_TABLE (PREFIX_VEX_0F91) },
5811 { PREFIX_TABLE (PREFIX_VEX_0F92) },
5812 { PREFIX_TABLE (PREFIX_VEX_0F93) },
5813 { Bad_Opcode },
5814 { Bad_Opcode },
5815 { Bad_Opcode },
5816 { Bad_Opcode },
5817 /* 98 */
5818 { PREFIX_TABLE (PREFIX_VEX_0F98) },
5819 { PREFIX_TABLE (PREFIX_VEX_0F99) },
5820 { Bad_Opcode },
5821 { Bad_Opcode },
5822 { Bad_Opcode },
5823 { Bad_Opcode },
5824 { Bad_Opcode },
5825 { Bad_Opcode },
5826 /* a0 */
5827 { Bad_Opcode },
5828 { Bad_Opcode },
5829 { Bad_Opcode },
5830 { Bad_Opcode },
5831 { Bad_Opcode },
5832 { Bad_Opcode },
5833 { Bad_Opcode },
5834 { Bad_Opcode },
5835 /* a8 */
5836 { Bad_Opcode },
5837 { Bad_Opcode },
5838 { Bad_Opcode },
5839 { Bad_Opcode },
5840 { Bad_Opcode },
5841 { Bad_Opcode },
5842 { REG_TABLE (REG_VEX_0FAE) },
5843 { Bad_Opcode },
5844 /* b0 */
5845 { Bad_Opcode },
5846 { Bad_Opcode },
5847 { Bad_Opcode },
5848 { Bad_Opcode },
5849 { Bad_Opcode },
5850 { Bad_Opcode },
5851 { Bad_Opcode },
5852 { Bad_Opcode },
5853 /* b8 */
5854 { Bad_Opcode },
5855 { Bad_Opcode },
5856 { Bad_Opcode },
5857 { Bad_Opcode },
5858 { Bad_Opcode },
5859 { Bad_Opcode },
5860 { Bad_Opcode },
5861 { Bad_Opcode },
5862 /* c0 */
5863 { Bad_Opcode },
5864 { Bad_Opcode },
5865 { PREFIX_TABLE (PREFIX_VEX_0FC2) },
5866 { Bad_Opcode },
5867 { VEX_LEN_TABLE (VEX_LEN_0FC4) },
5868 { VEX_LEN_TABLE (VEX_LEN_0FC5) },
5869 { "vshufpX", { XM, Vex, EXx, Ib }, PREFIX_OPCODE },
5870 { Bad_Opcode },
5871 /* c8 */
5872 { Bad_Opcode },
5873 { Bad_Opcode },
5874 { Bad_Opcode },
5875 { Bad_Opcode },
5876 { Bad_Opcode },
5877 { Bad_Opcode },
5878 { Bad_Opcode },
5879 { Bad_Opcode },
5880 /* d0 */
5881 { PREFIX_TABLE (PREFIX_VEX_0FD0) },
5882 { "vpsrlw", { XM, Vex, EXxmm }, PREFIX_DATA },
5883 { "vpsrld", { XM, Vex, EXxmm }, PREFIX_DATA },
5884 { "vpsrlq", { XM, Vex, EXxmm }, PREFIX_DATA },
5885 { "vpaddq", { XM, Vex, EXx }, PREFIX_DATA },
5886 { "vpmullw", { XM, Vex, EXx }, PREFIX_DATA },
5887 { VEX_LEN_TABLE (VEX_LEN_0FD6) },
5888 { MOD_TABLE (MOD_VEX_0FD7) },
5889 /* d8 */
5890 { "vpsubusb", { XM, Vex, EXx }, PREFIX_DATA },
5891 { "vpsubusw", { XM, Vex, EXx }, PREFIX_DATA },
5892 { "vpminub", { XM, Vex, EXx }, PREFIX_DATA },
5893 { "vpand", { XM, Vex, EXx }, PREFIX_DATA },
5894 { "vpaddusb", { XM, Vex, EXx }, PREFIX_DATA },
5895 { "vpaddusw", { XM, Vex, EXx }, PREFIX_DATA },
5896 { "vpmaxub", { XM, Vex, EXx }, PREFIX_DATA },
5897 { "vpandn", { XM, Vex, EXx }, PREFIX_DATA },
5898 /* e0 */
5899 { "vpavgb", { XM, Vex, EXx }, PREFIX_DATA },
5900 { "vpsraw", { XM, Vex, EXxmm }, PREFIX_DATA },
5901 { "vpsrad", { XM, Vex, EXxmm }, PREFIX_DATA },
5902 { "vpavgw", { XM, Vex, EXx }, PREFIX_DATA },
5903 { "vpmulhuw", { XM, Vex, EXx }, PREFIX_DATA },
5904 { "vpmulhw", { XM, Vex, EXx }, PREFIX_DATA },
5905 { PREFIX_TABLE (PREFIX_VEX_0FE6) },
5906 { MOD_TABLE (MOD_VEX_0FE7) },
5907 /* e8 */
5908 { "vpsubsb", { XM, Vex, EXx }, PREFIX_DATA },
5909 { "vpsubsw", { XM, Vex, EXx }, PREFIX_DATA },
5910 { "vpminsw", { XM, Vex, EXx }, PREFIX_DATA },
5911 { "vpor", { XM, Vex, EXx }, PREFIX_DATA },
5912 { "vpaddsb", { XM, Vex, EXx }, PREFIX_DATA },
5913 { "vpaddsw", { XM, Vex, EXx }, PREFIX_DATA },
5914 { "vpmaxsw", { XM, Vex, EXx }, PREFIX_DATA },
5915 { "vpxor", { XM, Vex, EXx }, PREFIX_DATA },
5916 /* f0 */
5917 { PREFIX_TABLE (PREFIX_VEX_0FF0) },
5918 { "vpsllw", { XM, Vex, EXxmm }, PREFIX_DATA },
5919 { "vpslld", { XM, Vex, EXxmm }, PREFIX_DATA },
5920 { "vpsllq", { XM, Vex, EXxmm }, PREFIX_DATA },
5921 { "vpmuludq", { XM, Vex, EXx }, PREFIX_DATA },
5922 { "vpmaddwd", { XM, Vex, EXx }, PREFIX_DATA },
5923 { "vpsadbw", { XM, Vex, EXx }, PREFIX_DATA },
5924 { VEX_LEN_TABLE (VEX_LEN_0FF7) },
5925 /* f8 */
5926 { "vpsubb", { XM, Vex, EXx }, PREFIX_DATA },
5927 { "vpsubw", { XM, Vex, EXx }, PREFIX_DATA },
5928 { "vpsubd", { XM, Vex, EXx }, PREFIX_DATA },
5929 { "vpsubq", { XM, Vex, EXx }, PREFIX_DATA },
5930 { "vpaddb", { XM, Vex, EXx }, PREFIX_DATA },
5931 { "vpaddw", { XM, Vex, EXx }, PREFIX_DATA },
5932 { "vpaddd", { XM, Vex, EXx }, PREFIX_DATA },
5933 { Bad_Opcode },
5934 },
5935 /* VEX_0F38 */
5936 {
5937 /* 00 */
5938 { "vpshufb", { XM, Vex, EXx }, PREFIX_DATA },
5939 { "vphaddw", { XM, Vex, EXx }, PREFIX_DATA },
5940 { "vphaddd", { XM, Vex, EXx }, PREFIX_DATA },
5941 { "vphaddsw", { XM, Vex, EXx }, PREFIX_DATA },
5942 { "vpmaddubsw", { XM, Vex, EXx }, PREFIX_DATA },
5943 { "vphsubw", { XM, Vex, EXx }, PREFIX_DATA },
5944 { "vphsubd", { XM, Vex, EXx }, PREFIX_DATA },
5945 { "vphsubsw", { XM, Vex, EXx }, PREFIX_DATA },
5946 /* 08 */
5947 { "vpsignb", { XM, Vex, EXx }, PREFIX_DATA },
5948 { "vpsignw", { XM, Vex, EXx }, PREFIX_DATA },
5949 { "vpsignd", { XM, Vex, EXx }, PREFIX_DATA },
5950 { "vpmulhrsw", { XM, Vex, EXx }, PREFIX_DATA },
5951 { VEX_W_TABLE (VEX_W_0F380C) },
5952 { VEX_W_TABLE (VEX_W_0F380D) },
5953 { VEX_W_TABLE (VEX_W_0F380E) },
5954 { VEX_W_TABLE (VEX_W_0F380F) },
5955 /* 10 */
5956 { Bad_Opcode },
5957 { Bad_Opcode },
5958 { Bad_Opcode },
5959 { VEX_W_TABLE (VEX_W_0F3813) },
5960 { Bad_Opcode },
5961 { Bad_Opcode },
5962 { VEX_LEN_TABLE (VEX_LEN_0F3816) },
5963 { "vptest", { XM, EXx }, PREFIX_DATA },
5964 /* 18 */
5965 { VEX_W_TABLE (VEX_W_0F3818) },
5966 { VEX_LEN_TABLE (VEX_LEN_0F3819) },
5967 { MOD_TABLE (MOD_VEX_0F381A) },
5968 { Bad_Opcode },
5969 { "vpabsb", { XM, EXx }, PREFIX_DATA },
5970 { "vpabsw", { XM, EXx }, PREFIX_DATA },
5971 { "vpabsd", { XM, EXx }, PREFIX_DATA },
5972 { Bad_Opcode },
5973 /* 20 */
5974 { "vpmovsxbw", { XM, EXxmmq }, PREFIX_DATA },
5975 { "vpmovsxbd", { XM, EXxmmqd }, PREFIX_DATA },
5976 { "vpmovsxbq", { XM, EXxmmdw }, PREFIX_DATA },
5977 { "vpmovsxwd", { XM, EXxmmq }, PREFIX_DATA },
5978 { "vpmovsxwq", { XM, EXxmmqd }, PREFIX_DATA },
5979 { "vpmovsxdq", { XM, EXxmmq }, PREFIX_DATA },
5980 { Bad_Opcode },
5981 { Bad_Opcode },
5982 /* 28 */
5983 { "vpmuldq", { XM, Vex, EXx }, PREFIX_DATA },
5984 { "vpcmpeqq", { XM, Vex, EXx }, PREFIX_DATA },
5985 { MOD_TABLE (MOD_VEX_0F382A) },
5986 { "vpackusdw", { XM, Vex, EXx }, PREFIX_DATA },
5987 { MOD_TABLE (MOD_VEX_0F382C) },
5988 { MOD_TABLE (MOD_VEX_0F382D) },
5989 { MOD_TABLE (MOD_VEX_0F382E) },
5990 { MOD_TABLE (MOD_VEX_0F382F) },
5991 /* 30 */
5992 { "vpmovzxbw", { XM, EXxmmq }, PREFIX_DATA },
5993 { "vpmovzxbd", { XM, EXxmmqd }, PREFIX_DATA },
5994 { "vpmovzxbq", { XM, EXxmmdw }, PREFIX_DATA },
5995 { "vpmovzxwd", { XM, EXxmmq }, PREFIX_DATA },
5996 { "vpmovzxwq", { XM, EXxmmqd }, PREFIX_DATA },
5997 { "vpmovzxdq", { XM, EXxmmq }, PREFIX_DATA },
5998 { VEX_LEN_TABLE (VEX_LEN_0F3836) },
5999 { "vpcmpgtq", { XM, Vex, EXx }, PREFIX_DATA },
6000 /* 38 */
6001 { "vpminsb", { XM, Vex, EXx }, PREFIX_DATA },
6002 { "vpminsd", { XM, Vex, EXx }, PREFIX_DATA },
6003 { "vpminuw", { XM, Vex, EXx }, PREFIX_DATA },
6004 { "vpminud", { XM, Vex, EXx }, PREFIX_DATA },
6005 { "vpmaxsb", { XM, Vex, EXx }, PREFIX_DATA },
6006 { "vpmaxsd", { XM, Vex, EXx }, PREFIX_DATA },
6007 { "vpmaxuw", { XM, Vex, EXx }, PREFIX_DATA },
6008 { "vpmaxud", { XM, Vex, EXx }, PREFIX_DATA },
6009 /* 40 */
6010 { "vpmulld", { XM, Vex, EXx }, PREFIX_DATA },
6011 { VEX_LEN_TABLE (VEX_LEN_0F3841) },
6012 { Bad_Opcode },
6013 { Bad_Opcode },
6014 { Bad_Opcode },
6015 { "vpsrlv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6016 { VEX_W_TABLE (VEX_W_0F3846) },
6017 { "vpsllv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6018 /* 48 */
6019 { Bad_Opcode },
6020 { X86_64_TABLE (X86_64_VEX_0F3849) },
6021 { Bad_Opcode },
6022 { X86_64_TABLE (X86_64_VEX_0F384B) },
6023 { Bad_Opcode },
6024 { Bad_Opcode },
6025 { Bad_Opcode },
6026 { Bad_Opcode },
6027 /* 50 */
6028 { Bad_Opcode },
6029 { Bad_Opcode },
6030 { Bad_Opcode },
6031 { Bad_Opcode },
6032 { Bad_Opcode },
6033 { Bad_Opcode },
6034 { Bad_Opcode },
6035 { Bad_Opcode },
6036 /* 58 */
6037 { VEX_W_TABLE (VEX_W_0F3858) },
6038 { VEX_W_TABLE (VEX_W_0F3859) },
6039 { MOD_TABLE (MOD_VEX_0F385A) },
6040 { Bad_Opcode },
6041 { X86_64_TABLE (X86_64_VEX_0F385C) },
6042 { Bad_Opcode },
6043 { X86_64_TABLE (X86_64_VEX_0F385E) },
6044 { Bad_Opcode },
6045 /* 60 */
6046 { Bad_Opcode },
6047 { Bad_Opcode },
6048 { Bad_Opcode },
6049 { Bad_Opcode },
6050 { Bad_Opcode },
6051 { Bad_Opcode },
6052 { Bad_Opcode },
6053 { Bad_Opcode },
6054 /* 68 */
6055 { Bad_Opcode },
6056 { Bad_Opcode },
6057 { Bad_Opcode },
6058 { Bad_Opcode },
6059 { Bad_Opcode },
6060 { Bad_Opcode },
6061 { Bad_Opcode },
6062 { Bad_Opcode },
6063 /* 70 */
6064 { Bad_Opcode },
6065 { Bad_Opcode },
6066 { Bad_Opcode },
6067 { Bad_Opcode },
6068 { Bad_Opcode },
6069 { Bad_Opcode },
6070 { Bad_Opcode },
6071 { Bad_Opcode },
6072 /* 78 */
6073 { VEX_W_TABLE (VEX_W_0F3878) },
6074 { VEX_W_TABLE (VEX_W_0F3879) },
6075 { Bad_Opcode },
6076 { Bad_Opcode },
6077 { Bad_Opcode },
6078 { Bad_Opcode },
6079 { Bad_Opcode },
6080 { Bad_Opcode },
6081 /* 80 */
6082 { Bad_Opcode },
6083 { Bad_Opcode },
6084 { Bad_Opcode },
6085 { Bad_Opcode },
6086 { Bad_Opcode },
6087 { Bad_Opcode },
6088 { Bad_Opcode },
6089 { Bad_Opcode },
6090 /* 88 */
6091 { Bad_Opcode },
6092 { Bad_Opcode },
6093 { Bad_Opcode },
6094 { Bad_Opcode },
6095 { MOD_TABLE (MOD_VEX_0F388C) },
6096 { Bad_Opcode },
6097 { MOD_TABLE (MOD_VEX_0F388E) },
6098 { Bad_Opcode },
6099 /* 90 */
6100 { "vpgatherd%DQ", { XM, MVexVSIBDWpX, Vex }, PREFIX_DATA },
6101 { "vpgatherq%DQ", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6102 { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, PREFIX_DATA },
6103 { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6104 { Bad_Opcode },
6105 { Bad_Opcode },
6106 { "vfmaddsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6107 { "vfmsubadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6108 /* 98 */
6109 { "vfmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6110 { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6111 { "vfmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6112 { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6113 { "vfnmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6114 { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6115 { "vfnmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6116 { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6117 /* a0 */
6118 { Bad_Opcode },
6119 { Bad_Opcode },
6120 { Bad_Opcode },
6121 { Bad_Opcode },
6122 { Bad_Opcode },
6123 { Bad_Opcode },
6124 { "vfmaddsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6125 { "vfmsubadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6126 /* a8 */
6127 { "vfmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6128 { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6129 { "vfmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6130 { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6131 { "vfnmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6132 { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6133 { "vfnmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6134 { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6135 /* b0 */
6136 { Bad_Opcode },
6137 { Bad_Opcode },
6138 { Bad_Opcode },
6139 { Bad_Opcode },
6140 { Bad_Opcode },
6141 { Bad_Opcode },
6142 { "vfmaddsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6143 { "vfmsubadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6144 /* b8 */
6145 { "vfmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6146 { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6147 { "vfmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6148 { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6149 { "vfnmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6150 { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6151 { "vfnmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6152 { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6153 /* c0 */
6154 { Bad_Opcode },
6155 { Bad_Opcode },
6156 { Bad_Opcode },
6157 { Bad_Opcode },
6158 { Bad_Opcode },
6159 { Bad_Opcode },
6160 { Bad_Opcode },
6161 { Bad_Opcode },
6162 /* c8 */
6163 { Bad_Opcode },
6164 { Bad_Opcode },
6165 { Bad_Opcode },
6166 { Bad_Opcode },
6167 { Bad_Opcode },
6168 { Bad_Opcode },
6169 { Bad_Opcode },
6170 { VEX_W_TABLE (VEX_W_0F38CF) },
6171 /* d0 */
6172 { Bad_Opcode },
6173 { Bad_Opcode },
6174 { Bad_Opcode },
6175 { Bad_Opcode },
6176 { Bad_Opcode },
6177 { Bad_Opcode },
6178 { Bad_Opcode },
6179 { Bad_Opcode },
6180 /* d8 */
6181 { Bad_Opcode },
6182 { Bad_Opcode },
6183 { Bad_Opcode },
6184 { VEX_LEN_TABLE (VEX_LEN_0F38DB) },
6185 { "vaesenc", { XM, Vex, EXx }, PREFIX_DATA },
6186 { "vaesenclast", { XM, Vex, EXx }, PREFIX_DATA },
6187 { "vaesdec", { XM, Vex, EXx }, PREFIX_DATA },
6188 { "vaesdeclast", { XM, Vex, EXx }, PREFIX_DATA },
6189 /* e0 */
6190 { Bad_Opcode },
6191 { Bad_Opcode },
6192 { Bad_Opcode },
6193 { Bad_Opcode },
6194 { Bad_Opcode },
6195 { Bad_Opcode },
6196 { Bad_Opcode },
6197 { Bad_Opcode },
6198 /* e8 */
6199 { Bad_Opcode },
6200 { Bad_Opcode },
6201 { Bad_Opcode },
6202 { Bad_Opcode },
6203 { Bad_Opcode },
6204 { Bad_Opcode },
6205 { Bad_Opcode },
6206 { Bad_Opcode },
6207 /* f0 */
6208 { Bad_Opcode },
6209 { Bad_Opcode },
6210 { VEX_LEN_TABLE (VEX_LEN_0F38F2) },
6211 { REG_TABLE (REG_VEX_0F38F3) },
6212 { Bad_Opcode },
6213 { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
6214 { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
6215 { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
6216 /* f8 */
6217 { Bad_Opcode },
6218 { Bad_Opcode },
6219 { Bad_Opcode },
6220 { Bad_Opcode },
6221 { Bad_Opcode },
6222 { Bad_Opcode },
6223 { Bad_Opcode },
6224 { Bad_Opcode },
6225 },
6226 /* VEX_0F3A */
6227 {
6228 /* 00 */
6229 { VEX_LEN_TABLE (VEX_LEN_0F3A00) },
6230 { VEX_LEN_TABLE (VEX_LEN_0F3A01) },
6231 { VEX_W_TABLE (VEX_W_0F3A02) },
6232 { Bad_Opcode },
6233 { VEX_W_TABLE (VEX_W_0F3A04) },
6234 { VEX_W_TABLE (VEX_W_0F3A05) },
6235 { VEX_LEN_TABLE (VEX_LEN_0F3A06) },
6236 { Bad_Opcode },
6237 /* 08 */
6238 { "vroundps", { XM, EXx, Ib }, PREFIX_DATA },
6239 { "vroundpd", { XM, EXx, Ib }, PREFIX_DATA },
6240 { "vroundss", { XMScalar, VexScalar, EXxmm_md, Ib }, PREFIX_DATA },
6241 { "vroundsd", { XMScalar, VexScalar, EXxmm_mq, Ib }, PREFIX_DATA },
6242 { "vblendps", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6243 { "vblendpd", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6244 { "vpblendw", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6245 { "vpalignr", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6246 /* 10 */
6247 { Bad_Opcode },
6248 { Bad_Opcode },
6249 { Bad_Opcode },
6250 { Bad_Opcode },
6251 { VEX_LEN_TABLE (VEX_LEN_0F3A14) },
6252 { VEX_LEN_TABLE (VEX_LEN_0F3A15) },
6253 { VEX_LEN_TABLE (VEX_LEN_0F3A16) },
6254 { VEX_LEN_TABLE (VEX_LEN_0F3A17) },
6255 /* 18 */
6256 { VEX_LEN_TABLE (VEX_LEN_0F3A18) },
6257 { VEX_LEN_TABLE (VEX_LEN_0F3A19) },
6258 { Bad_Opcode },
6259 { Bad_Opcode },
6260 { Bad_Opcode },
6261 { VEX_W_TABLE (VEX_W_0F3A1D) },
6262 { Bad_Opcode },
6263 { Bad_Opcode },
6264 /* 20 */
6265 { VEX_LEN_TABLE (VEX_LEN_0F3A20) },
6266 { VEX_LEN_TABLE (VEX_LEN_0F3A21) },
6267 { VEX_LEN_TABLE (VEX_LEN_0F3A22) },
6268 { Bad_Opcode },
6269 { Bad_Opcode },
6270 { Bad_Opcode },
6271 { Bad_Opcode },
6272 { Bad_Opcode },
6273 /* 28 */
6274 { Bad_Opcode },
6275 { Bad_Opcode },
6276 { Bad_Opcode },
6277 { Bad_Opcode },
6278 { Bad_Opcode },
6279 { Bad_Opcode },
6280 { Bad_Opcode },
6281 { Bad_Opcode },
6282 /* 30 */
6283 { VEX_LEN_TABLE (VEX_LEN_0F3A30) },
6284 { VEX_LEN_TABLE (VEX_LEN_0F3A31) },
6285 { VEX_LEN_TABLE (VEX_LEN_0F3A32) },
6286 { VEX_LEN_TABLE (VEX_LEN_0F3A33) },
6287 { Bad_Opcode },
6288 { Bad_Opcode },
6289 { Bad_Opcode },
6290 { Bad_Opcode },
6291 /* 38 */
6292 { VEX_LEN_TABLE (VEX_LEN_0F3A38) },
6293 { VEX_LEN_TABLE (VEX_LEN_0F3A39) },
6294 { Bad_Opcode },
6295 { Bad_Opcode },
6296 { Bad_Opcode },
6297 { Bad_Opcode },
6298 { Bad_Opcode },
6299 { Bad_Opcode },
6300 /* 40 */
6301 { "vdpps", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6302 { VEX_LEN_TABLE (VEX_LEN_0F3A41) },
6303 { "vmpsadbw", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6304 { Bad_Opcode },
6305 { "vpclmulqdq", { XM, Vex, EXx, PCLMUL }, PREFIX_DATA },
6306 { Bad_Opcode },
6307 { VEX_LEN_TABLE (VEX_LEN_0F3A46) },
6308 { Bad_Opcode },
6309 /* 48 */
6310 { "vpermil2ps", { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6311 { "vpermil2pd", { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6312 { VEX_W_TABLE (VEX_W_0F3A4A) },
6313 { VEX_W_TABLE (VEX_W_0F3A4B) },
6314 { VEX_W_TABLE (VEX_W_0F3A4C) },
6315 { Bad_Opcode },
6316 { Bad_Opcode },
6317 { Bad_Opcode },
6318 /* 50 */
6319 { Bad_Opcode },
6320 { Bad_Opcode },
6321 { Bad_Opcode },
6322 { Bad_Opcode },
6323 { Bad_Opcode },
6324 { Bad_Opcode },
6325 { Bad_Opcode },
6326 { Bad_Opcode },
6327 /* 58 */
6328 { Bad_Opcode },
6329 { Bad_Opcode },
6330 { Bad_Opcode },
6331 { Bad_Opcode },
6332 { "vfmaddsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6333 { "vfmaddsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6334 { "vfmsubaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6335 { "vfmsubaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6336 /* 60 */
6337 { VEX_LEN_TABLE (VEX_LEN_0F3A60) },
6338 { VEX_LEN_TABLE (VEX_LEN_0F3A61) },
6339 { VEX_LEN_TABLE (VEX_LEN_0F3A62) },
6340 { VEX_LEN_TABLE (VEX_LEN_0F3A63) },
6341 { Bad_Opcode },
6342 { Bad_Opcode },
6343 { Bad_Opcode },
6344 { Bad_Opcode },
6345 /* 68 */
6346 { "vfmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6347 { "vfmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6348 { "vfmaddss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
6349 { "vfmaddsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
6350 { "vfmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6351 { "vfmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6352 { "vfmsubss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
6353 { "vfmsubsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
6354 /* 70 */
6355 { Bad_Opcode },
6356 { Bad_Opcode },
6357 { Bad_Opcode },
6358 { Bad_Opcode },
6359 { Bad_Opcode },
6360 { Bad_Opcode },
6361 { Bad_Opcode },
6362 { Bad_Opcode },
6363 /* 78 */
6364 { "vfnmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6365 { "vfnmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6366 { "vfnmaddss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
6367 { "vfnmaddsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
6368 { "vfnmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6369 { "vfnmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6370 { "vfnmsubss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
6371 { "vfnmsubsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
6372 /* 80 */
6373 { Bad_Opcode },
6374 { Bad_Opcode },
6375 { Bad_Opcode },
6376 { Bad_Opcode },
6377 { Bad_Opcode },
6378 { Bad_Opcode },
6379 { Bad_Opcode },
6380 { Bad_Opcode },
6381 /* 88 */
6382 { Bad_Opcode },
6383 { Bad_Opcode },
6384 { Bad_Opcode },
6385 { Bad_Opcode },
6386 { Bad_Opcode },
6387 { Bad_Opcode },
6388 { Bad_Opcode },
6389 { Bad_Opcode },
6390 /* 90 */
6391 { Bad_Opcode },
6392 { Bad_Opcode },
6393 { Bad_Opcode },
6394 { Bad_Opcode },
6395 { Bad_Opcode },
6396 { Bad_Opcode },
6397 { Bad_Opcode },
6398 { Bad_Opcode },
6399 /* 98 */
6400 { Bad_Opcode },
6401 { Bad_Opcode },
6402 { Bad_Opcode },
6403 { Bad_Opcode },
6404 { Bad_Opcode },
6405 { Bad_Opcode },
6406 { Bad_Opcode },
6407 { Bad_Opcode },
6408 /* a0 */
6409 { Bad_Opcode },
6410 { Bad_Opcode },
6411 { Bad_Opcode },
6412 { Bad_Opcode },
6413 { Bad_Opcode },
6414 { Bad_Opcode },
6415 { Bad_Opcode },
6416 { Bad_Opcode },
6417 /* a8 */
6418 { Bad_Opcode },
6419 { Bad_Opcode },
6420 { Bad_Opcode },
6421 { Bad_Opcode },
6422 { Bad_Opcode },
6423 { Bad_Opcode },
6424 { Bad_Opcode },
6425 { Bad_Opcode },
6426 /* b0 */
6427 { Bad_Opcode },
6428 { Bad_Opcode },
6429 { Bad_Opcode },
6430 { Bad_Opcode },
6431 { Bad_Opcode },
6432 { Bad_Opcode },
6433 { Bad_Opcode },
6434 { Bad_Opcode },
6435 /* b8 */
6436 { Bad_Opcode },
6437 { Bad_Opcode },
6438 { Bad_Opcode },
6439 { Bad_Opcode },
6440 { Bad_Opcode },
6441 { Bad_Opcode },
6442 { Bad_Opcode },
6443 { Bad_Opcode },
6444 /* c0 */
6445 { Bad_Opcode },
6446 { Bad_Opcode },
6447 { Bad_Opcode },
6448 { Bad_Opcode },
6449 { Bad_Opcode },
6450 { Bad_Opcode },
6451 { Bad_Opcode },
6452 { Bad_Opcode },
6453 /* c8 */
6454 { Bad_Opcode },
6455 { Bad_Opcode },
6456 { Bad_Opcode },
6457 { Bad_Opcode },
6458 { Bad_Opcode },
6459 { Bad_Opcode },
6460 { VEX_W_TABLE (VEX_W_0F3ACE) },
6461 { VEX_W_TABLE (VEX_W_0F3ACF) },
6462 /* d0 */
6463 { Bad_Opcode },
6464 { Bad_Opcode },
6465 { Bad_Opcode },
6466 { Bad_Opcode },
6467 { Bad_Opcode },
6468 { Bad_Opcode },
6469 { Bad_Opcode },
6470 { Bad_Opcode },
6471 /* d8 */
6472 { Bad_Opcode },
6473 { Bad_Opcode },
6474 { Bad_Opcode },
6475 { Bad_Opcode },
6476 { Bad_Opcode },
6477 { Bad_Opcode },
6478 { Bad_Opcode },
6479 { VEX_LEN_TABLE (VEX_LEN_0F3ADF) },
6480 /* e0 */
6481 { Bad_Opcode },
6482 { Bad_Opcode },
6483 { Bad_Opcode },
6484 { Bad_Opcode },
6485 { Bad_Opcode },
6486 { Bad_Opcode },
6487 { Bad_Opcode },
6488 { Bad_Opcode },
6489 /* e8 */
6490 { Bad_Opcode },
6491 { Bad_Opcode },
6492 { Bad_Opcode },
6493 { Bad_Opcode },
6494 { Bad_Opcode },
6495 { Bad_Opcode },
6496 { Bad_Opcode },
6497 { Bad_Opcode },
6498 /* f0 */
6499 { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
6500 { Bad_Opcode },
6501 { Bad_Opcode },
6502 { Bad_Opcode },
6503 { Bad_Opcode },
6504 { Bad_Opcode },
6505 { Bad_Opcode },
6506 { Bad_Opcode },
6507 /* f8 */
6508 { Bad_Opcode },
6509 { Bad_Opcode },
6510 { Bad_Opcode },
6511 { Bad_Opcode },
6512 { Bad_Opcode },
6513 { Bad_Opcode },
6514 { Bad_Opcode },
6515 { Bad_Opcode },
6516 },
6517 };
6518
6519 #include "i386-dis-evex.h"
6520
6521 static const struct dis386 vex_len_table[][2] = {
6522 /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */
6523 {
6524 { "vmovlpX", { XM, Vex, EXq }, 0 },
6525 },
6526
6527 /* VEX_LEN_0F12_P_0_M_1 */
6528 {
6529 { "vmovhlps", { XM, Vex, EXq }, 0 },
6530 },
6531
6532 /* VEX_LEN_0F13_M_0 */
6533 {
6534 { "vmovlpX", { EXq, XM }, PREFIX_OPCODE },
6535 },
6536
6537 /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */
6538 {
6539 { "vmovhpX", { XM, Vex, EXq }, 0 },
6540 },
6541
6542 /* VEX_LEN_0F16_P_0_M_1 */
6543 {
6544 { "vmovlhps", { XM, Vex, EXq }, 0 },
6545 },
6546
6547 /* VEX_LEN_0F17_M_0 */
6548 {
6549 { "vmovhpX", { EXq, XM }, PREFIX_OPCODE },
6550 },
6551
6552 /* VEX_LEN_0F41_P_0 */
6553 {
6554 { Bad_Opcode },
6555 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
6556 },
6557 /* VEX_LEN_0F41_P_2 */
6558 {
6559 { Bad_Opcode },
6560 { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
6561 },
6562 /* VEX_LEN_0F42_P_0 */
6563 {
6564 { Bad_Opcode },
6565 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
6566 },
6567 /* VEX_LEN_0F42_P_2 */
6568 {
6569 { Bad_Opcode },
6570 { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
6571 },
6572 /* VEX_LEN_0F44_P_0 */
6573 {
6574 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
6575 },
6576 /* VEX_LEN_0F44_P_2 */
6577 {
6578 { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
6579 },
6580 /* VEX_LEN_0F45_P_0 */
6581 {
6582 { Bad_Opcode },
6583 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
6584 },
6585 /* VEX_LEN_0F45_P_2 */
6586 {
6587 { Bad_Opcode },
6588 { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
6589 },
6590 /* VEX_LEN_0F46_P_0 */
6591 {
6592 { Bad_Opcode },
6593 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
6594 },
6595 /* VEX_LEN_0F46_P_2 */
6596 {
6597 { Bad_Opcode },
6598 { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
6599 },
6600 /* VEX_LEN_0F47_P_0 */
6601 {
6602 { Bad_Opcode },
6603 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
6604 },
6605 /* VEX_LEN_0F47_P_2 */
6606 {
6607 { Bad_Opcode },
6608 { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
6609 },
6610 /* VEX_LEN_0F4A_P_0 */
6611 {
6612 { Bad_Opcode },
6613 { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
6614 },
6615 /* VEX_LEN_0F4A_P_2 */
6616 {
6617 { Bad_Opcode },
6618 { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
6619 },
6620 /* VEX_LEN_0F4B_P_0 */
6621 {
6622 { Bad_Opcode },
6623 { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
6624 },
6625 /* VEX_LEN_0F4B_P_2 */
6626 {
6627 { Bad_Opcode },
6628 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
6629 },
6630
6631 /* VEX_LEN_0F6E */
6632 {
6633 { "vmovK", { XMScalar, Edq }, PREFIX_DATA },
6634 },
6635
6636 /* VEX_LEN_0F77 */
6637 {
6638 { "vzeroupper", { XX }, 0 },
6639 { "vzeroall", { XX }, 0 },
6640 },
6641
6642 /* VEX_LEN_0F7E_P_1 */
6643 {
6644 { "vmovq", { XMScalar, EXxmm_mq }, 0 },
6645 },
6646
6647 /* VEX_LEN_0F7E_P_2 */
6648 {
6649 { "vmovK", { Edq, XMScalar }, 0 },
6650 },
6651
6652 /* VEX_LEN_0F90_P_0 */
6653 {
6654 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
6655 },
6656
6657 /* VEX_LEN_0F90_P_2 */
6658 {
6659 { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
6660 },
6661
6662 /* VEX_LEN_0F91_P_0 */
6663 {
6664 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
6665 },
6666
6667 /* VEX_LEN_0F91_P_2 */
6668 {
6669 { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
6670 },
6671
6672 /* VEX_LEN_0F92_P_0 */
6673 {
6674 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
6675 },
6676
6677 /* VEX_LEN_0F92_P_2 */
6678 {
6679 { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
6680 },
6681
6682 /* VEX_LEN_0F92_P_3 */
6683 {
6684 { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) },
6685 },
6686
6687 /* VEX_LEN_0F93_P_0 */
6688 {
6689 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
6690 },
6691
6692 /* VEX_LEN_0F93_P_2 */
6693 {
6694 { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
6695 },
6696
6697 /* VEX_LEN_0F93_P_3 */
6698 {
6699 { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) },
6700 },
6701
6702 /* VEX_LEN_0F98_P_0 */
6703 {
6704 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
6705 },
6706
6707 /* VEX_LEN_0F98_P_2 */
6708 {
6709 { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
6710 },
6711
6712 /* VEX_LEN_0F99_P_0 */
6713 {
6714 { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
6715 },
6716
6717 /* VEX_LEN_0F99_P_2 */
6718 {
6719 { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
6720 },
6721
6722 /* VEX_LEN_0FAE_R_2_M_0 */
6723 {
6724 { "vldmxcsr", { Md }, 0 },
6725 },
6726
6727 /* VEX_LEN_0FAE_R_3_M_0 */
6728 {
6729 { "vstmxcsr", { Md }, 0 },
6730 },
6731
6732 /* VEX_LEN_0FC4 */
6733 {
6734 { "vpinsrw", { XM, Vex, Edqw, Ib }, PREFIX_DATA },
6735 },
6736
6737 /* VEX_LEN_0FC5 */
6738 {
6739 { "vpextrw", { Gdq, XS, Ib }, PREFIX_DATA },
6740 },
6741
6742 /* VEX_LEN_0FD6 */
6743 {
6744 { "vmovq", { EXqS, XMScalar }, PREFIX_DATA },
6745 },
6746
6747 /* VEX_LEN_0FF7 */
6748 {
6749 { "vmaskmovdqu", { XM, XS }, PREFIX_DATA },
6750 },
6751
6752 /* VEX_LEN_0F3816 */
6753 {
6754 { Bad_Opcode },
6755 { VEX_W_TABLE (VEX_W_0F3816_L_1) },
6756 },
6757
6758 /* VEX_LEN_0F3819 */
6759 {
6760 { Bad_Opcode },
6761 { VEX_W_TABLE (VEX_W_0F3819_L_1) },
6762 },
6763
6764 /* VEX_LEN_0F381A_M_0 */
6765 {
6766 { Bad_Opcode },
6767 { VEX_W_TABLE (VEX_W_0F381A_M_0_L_1) },
6768 },
6769
6770 /* VEX_LEN_0F3836 */
6771 {
6772 { Bad_Opcode },
6773 { VEX_W_TABLE (VEX_W_0F3836) },
6774 },
6775
6776 /* VEX_LEN_0F3841 */
6777 {
6778 { "vphminposuw", { XM, EXx }, PREFIX_DATA },
6779 },
6780
6781 /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_0 */
6782 {
6783 { "ldtilecfg", { M }, 0 },
6784 },
6785
6786 /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0 */
6787 {
6788 { "tilerelease", { Skip_MODRM }, 0 },
6789 },
6790
6791 /* VEX_LEN_0F3849_X86_64_P_2_W_0_M_0 */
6792 {
6793 { "sttilecfg", { M }, 0 },
6794 },
6795
6796 /* VEX_LEN_0F3849_X86_64_P_3_W_0_M_0 */
6797 {
6798 { "tilezero", { TMM, Skip_MODRM }, 0 },
6799 },
6800
6801 /* VEX_LEN_0F384B_X86_64_P_1_W_0_M_0 */
6802 {
6803 { "tilestored", { MVexSIBMEM, TMM }, 0 },
6804 },
6805 /* VEX_LEN_0F384B_X86_64_P_2_W_0_M_0 */
6806 {
6807 { "tileloaddt1", { TMM, MVexSIBMEM }, 0 },
6808 },
6809
6810 /* VEX_LEN_0F384B_X86_64_P_3_W_0_M_0 */
6811 {
6812 { "tileloadd", { TMM, MVexSIBMEM }, 0 },
6813 },
6814
6815 /* VEX_LEN_0F385A_M_0 */
6816 {
6817 { Bad_Opcode },
6818 { VEX_W_TABLE (VEX_W_0F385A_M_0_L_0) },
6819 },
6820
6821 /* VEX_LEN_0F385C_X86_64_P_1_W_0_M_0 */
6822 {
6823 { "tdpbf16ps", { TMM, EXtmm, VexTmm }, 0 },
6824 },
6825
6826 /* VEX_LEN_0F385E_X86_64_P_0_W_0_M_0 */
6827 {
6828 { "tdpbuud", {TMM, EXtmm, VexTmm }, 0 },
6829 },
6830
6831 /* VEX_LEN_0F385E_X86_64_P_1_W_0_M_0 */
6832 {
6833 { "tdpbsud", {TMM, EXtmm, VexTmm }, 0 },
6834 },
6835
6836 /* VEX_LEN_0F385E_X86_64_P_2_W_0_M_0 */
6837 {
6838 { "tdpbusd", {TMM, EXtmm, VexTmm }, 0 },
6839 },
6840
6841 /* VEX_LEN_0F385E_X86_64_P_3_W_0_M_0 */
6842 {
6843 { "tdpbssd", {TMM, EXtmm, VexTmm }, 0 },
6844 },
6845
6846 /* VEX_LEN_0F38DB */
6847 {
6848 { "vaesimc", { XM, EXx }, PREFIX_DATA },
6849 },
6850
6851 /* VEX_LEN_0F38F2 */
6852 {
6853 { "andnS", { Gdq, VexGdq, Edq }, PREFIX_OPCODE },
6854 },
6855
6856 /* VEX_LEN_0F38F3_R_1 */
6857 {
6858 { "blsrS", { VexGdq, Edq }, PREFIX_OPCODE },
6859 },
6860
6861 /* VEX_LEN_0F38F3_R_2 */
6862 {
6863 { "blsmskS", { VexGdq, Edq }, PREFIX_OPCODE },
6864 },
6865
6866 /* VEX_LEN_0F38F3_R_3 */
6867 {
6868 { "blsiS", { VexGdq, Edq }, PREFIX_OPCODE },
6869 },
6870
6871 /* VEX_LEN_0F38F5_P_0 */
6872 {
6873 { "bzhiS", { Gdq, Edq, VexGdq }, 0 },
6874 },
6875
6876 /* VEX_LEN_0F38F5_P_1 */
6877 {
6878 { "pextS", { Gdq, VexGdq, Edq }, 0 },
6879 },
6880
6881 /* VEX_LEN_0F38F5_P_3 */
6882 {
6883 { "pdepS", { Gdq, VexGdq, Edq }, 0 },
6884 },
6885
6886 /* VEX_LEN_0F38F6_P_3 */
6887 {
6888 { "mulxS", { Gdq, VexGdq, Edq }, 0 },
6889 },
6890
6891 /* VEX_LEN_0F38F7_P_0 */
6892 {
6893 { "bextrS", { Gdq, Edq, VexGdq }, 0 },
6894 },
6895
6896 /* VEX_LEN_0F38F7_P_1 */
6897 {
6898 { "sarxS", { Gdq, Edq, VexGdq }, 0 },
6899 },
6900
6901 /* VEX_LEN_0F38F7_P_2 */
6902 {
6903 { "shlxS", { Gdq, Edq, VexGdq }, 0 },
6904 },
6905
6906 /* VEX_LEN_0F38F7_P_3 */
6907 {
6908 { "shrxS", { Gdq, Edq, VexGdq }, 0 },
6909 },
6910
6911 /* VEX_LEN_0F3A00 */
6912 {
6913 { Bad_Opcode },
6914 { VEX_W_TABLE (VEX_W_0F3A00_L_1) },
6915 },
6916
6917 /* VEX_LEN_0F3A01 */
6918 {
6919 { Bad_Opcode },
6920 { VEX_W_TABLE (VEX_W_0F3A01_L_1) },
6921 },
6922
6923 /* VEX_LEN_0F3A06 */
6924 {
6925 { Bad_Opcode },
6926 { VEX_W_TABLE (VEX_W_0F3A06_L_1) },
6927 },
6928
6929 /* VEX_LEN_0F3A14 */
6930 {
6931 { "vpextrb", { Edqb, XM, Ib }, PREFIX_DATA },
6932 },
6933
6934 /* VEX_LEN_0F3A15 */
6935 {
6936 { "vpextrw", { Edqw, XM, Ib }, PREFIX_DATA },
6937 },
6938
6939 /* VEX_LEN_0F3A16 */
6940 {
6941 { "vpextrK", { Edq, XM, Ib }, PREFIX_DATA },
6942 },
6943
6944 /* VEX_LEN_0F3A17 */
6945 {
6946 { "vextractps", { Edqd, XM, Ib }, PREFIX_DATA },
6947 },
6948
6949 /* VEX_LEN_0F3A18 */
6950 {
6951 { Bad_Opcode },
6952 { VEX_W_TABLE (VEX_W_0F3A18_L_1) },
6953 },
6954
6955 /* VEX_LEN_0F3A19 */
6956 {
6957 { Bad_Opcode },
6958 { VEX_W_TABLE (VEX_W_0F3A19_L_1) },
6959 },
6960
6961 /* VEX_LEN_0F3A20 */
6962 {
6963 { "vpinsrb", { XM, Vex, Edqb, Ib }, PREFIX_DATA },
6964 },
6965
6966 /* VEX_LEN_0F3A21 */
6967 {
6968 { "vinsertps", { XM, Vex, EXd, Ib }, PREFIX_DATA },
6969 },
6970
6971 /* VEX_LEN_0F3A22 */
6972 {
6973 { "vpinsrK", { XM, Vex, Edq, Ib }, PREFIX_DATA },
6974 },
6975
6976 /* VEX_LEN_0F3A30 */
6977 {
6978 { MOD_TABLE (MOD_VEX_0F3A30_L_0) },
6979 },
6980
6981 /* VEX_LEN_0F3A31 */
6982 {
6983 { MOD_TABLE (MOD_VEX_0F3A31_L_0) },
6984 },
6985
6986 /* VEX_LEN_0F3A32 */
6987 {
6988 { MOD_TABLE (MOD_VEX_0F3A32_L_0) },
6989 },
6990
6991 /* VEX_LEN_0F3A33 */
6992 {
6993 { MOD_TABLE (MOD_VEX_0F3A33_L_0) },
6994 },
6995
6996 /* VEX_LEN_0F3A38 */
6997 {
6998 { Bad_Opcode },
6999 { VEX_W_TABLE (VEX_W_0F3A38_L_1) },
7000 },
7001
7002 /* VEX_LEN_0F3A39 */
7003 {
7004 { Bad_Opcode },
7005 { VEX_W_TABLE (VEX_W_0F3A39_L_1) },
7006 },
7007
7008 /* VEX_LEN_0F3A41 */
7009 {
7010 { "vdppd", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7011 },
7012
7013 /* VEX_LEN_0F3A46 */
7014 {
7015 { Bad_Opcode },
7016 { VEX_W_TABLE (VEX_W_0F3A46_L_1) },
7017 },
7018
7019 /* VEX_LEN_0F3A60 */
7020 {
7021 { "vpcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7022 },
7023
7024 /* VEX_LEN_0F3A61 */
7025 {
7026 { "vpcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7027 },
7028
7029 /* VEX_LEN_0F3A62 */
7030 {
7031 { "vpcmpistrm", { XM, EXx, Ib }, PREFIX_DATA },
7032 },
7033
7034 /* VEX_LEN_0F3A63 */
7035 {
7036 { "vpcmpistri", { XM, EXx, Ib }, PREFIX_DATA },
7037 },
7038
7039 /* VEX_LEN_0F3ADF */
7040 {
7041 { "vaeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
7042 },
7043
7044 /* VEX_LEN_0F3AF0_P_3 */
7045 {
7046 { "rorxS", { Gdq, Edq, Ib }, 0 },
7047 },
7048
7049 /* VEX_LEN_0FXOP_08_85 */
7050 {
7051 { VEX_W_TABLE (VEX_W_0FXOP_08_85_L_0) },
7052 },
7053
7054 /* VEX_LEN_0FXOP_08_86 */
7055 {
7056 { VEX_W_TABLE (VEX_W_0FXOP_08_86_L_0) },
7057 },
7058
7059 /* VEX_LEN_0FXOP_08_87 */
7060 {
7061 { VEX_W_TABLE (VEX_W_0FXOP_08_87_L_0) },
7062 },
7063
7064 /* VEX_LEN_0FXOP_08_8E */
7065 {
7066 { VEX_W_TABLE (VEX_W_0FXOP_08_8E_L_0) },
7067 },
7068
7069 /* VEX_LEN_0FXOP_08_8F */
7070 {
7071 { VEX_W_TABLE (VEX_W_0FXOP_08_8F_L_0) },
7072 },
7073
7074 /* VEX_LEN_0FXOP_08_95 */
7075 {
7076 { VEX_W_TABLE (VEX_W_0FXOP_08_95_L_0) },
7077 },
7078
7079 /* VEX_LEN_0FXOP_08_96 */
7080 {
7081 { VEX_W_TABLE (VEX_W_0FXOP_08_96_L_0) },
7082 },
7083
7084 /* VEX_LEN_0FXOP_08_97 */
7085 {
7086 { VEX_W_TABLE (VEX_W_0FXOP_08_97_L_0) },
7087 },
7088
7089 /* VEX_LEN_0FXOP_08_9E */
7090 {
7091 { VEX_W_TABLE (VEX_W_0FXOP_08_9E_L_0) },
7092 },
7093
7094 /* VEX_LEN_0FXOP_08_9F */
7095 {
7096 { VEX_W_TABLE (VEX_W_0FXOP_08_9F_L_0) },
7097 },
7098
7099 /* VEX_LEN_0FXOP_08_A3 */
7100 {
7101 { "vpperm", { XM, Vex, EXx, XMVexI4 }, 0 },
7102 },
7103
7104 /* VEX_LEN_0FXOP_08_A6 */
7105 {
7106 { VEX_W_TABLE (VEX_W_0FXOP_08_A6_L_0) },
7107 },
7108
7109 /* VEX_LEN_0FXOP_08_B6 */
7110 {
7111 { VEX_W_TABLE (VEX_W_0FXOP_08_B6_L_0) },
7112 },
7113
7114 /* VEX_LEN_0FXOP_08_C0 */
7115 {
7116 { VEX_W_TABLE (VEX_W_0FXOP_08_C0_L_0) },
7117 },
7118
7119 /* VEX_LEN_0FXOP_08_C1 */
7120 {
7121 { VEX_W_TABLE (VEX_W_0FXOP_08_C1_L_0) },
7122 },
7123
7124 /* VEX_LEN_0FXOP_08_C2 */
7125 {
7126 { VEX_W_TABLE (VEX_W_0FXOP_08_C2_L_0) },
7127 },
7128
7129 /* VEX_LEN_0FXOP_08_C3 */
7130 {
7131 { VEX_W_TABLE (VEX_W_0FXOP_08_C3_L_0) },
7132 },
7133
7134 /* VEX_LEN_0FXOP_08_CC */
7135 {
7136 { VEX_W_TABLE (VEX_W_0FXOP_08_CC_L_0) },
7137 },
7138
7139 /* VEX_LEN_0FXOP_08_CD */
7140 {
7141 { VEX_W_TABLE (VEX_W_0FXOP_08_CD_L_0) },
7142 },
7143
7144 /* VEX_LEN_0FXOP_08_CE */
7145 {
7146 { VEX_W_TABLE (VEX_W_0FXOP_08_CE_L_0) },
7147 },
7148
7149 /* VEX_LEN_0FXOP_08_CF */
7150 {
7151 { VEX_W_TABLE (VEX_W_0FXOP_08_CF_L_0) },
7152 },
7153
7154 /* VEX_LEN_0FXOP_08_EC */
7155 {
7156 { VEX_W_TABLE (VEX_W_0FXOP_08_EC_L_0) },
7157 },
7158
7159 /* VEX_LEN_0FXOP_08_ED */
7160 {
7161 { VEX_W_TABLE (VEX_W_0FXOP_08_ED_L_0) },
7162 },
7163
7164 /* VEX_LEN_0FXOP_08_EE */
7165 {
7166 { VEX_W_TABLE (VEX_W_0FXOP_08_EE_L_0) },
7167 },
7168
7169 /* VEX_LEN_0FXOP_08_EF */
7170 {
7171 { VEX_W_TABLE (VEX_W_0FXOP_08_EF_L_0) },
7172 },
7173
7174 /* VEX_LEN_0FXOP_09_01 */
7175 {
7176 { REG_TABLE (REG_0FXOP_09_01_L_0) },
7177 },
7178
7179 /* VEX_LEN_0FXOP_09_02 */
7180 {
7181 { REG_TABLE (REG_0FXOP_09_02_L_0) },
7182 },
7183
7184 /* VEX_LEN_0FXOP_09_12_M_1 */
7185 {
7186 { REG_TABLE (REG_0FXOP_09_12_M_1_L_0) },
7187 },
7188
7189 /* VEX_LEN_0FXOP_09_82_W_0 */
7190 {
7191 { "vfrczss", { XM, EXd }, 0 },
7192 },
7193
7194 /* VEX_LEN_0FXOP_09_83_W_0 */
7195 {
7196 { "vfrczsd", { XM, EXq }, 0 },
7197 },
7198
7199 /* VEX_LEN_0FXOP_09_90 */
7200 {
7201 { "vprotb", { XM, EXx, VexW }, 0 },
7202 },
7203
7204 /* VEX_LEN_0FXOP_09_91 */
7205 {
7206 { "vprotw", { XM, EXx, VexW }, 0 },
7207 },
7208
7209 /* VEX_LEN_0FXOP_09_92 */
7210 {
7211 { "vprotd", { XM, EXx, VexW }, 0 },
7212 },
7213
7214 /* VEX_LEN_0FXOP_09_93 */
7215 {
7216 { "vprotq", { XM, EXx, VexW }, 0 },
7217 },
7218
7219 /* VEX_LEN_0FXOP_09_94 */
7220 {
7221 { "vpshlb", { XM, EXx, VexW }, 0 },
7222 },
7223
7224 /* VEX_LEN_0FXOP_09_95 */
7225 {
7226 { "vpshlw", { XM, EXx, VexW }, 0 },
7227 },
7228
7229 /* VEX_LEN_0FXOP_09_96 */
7230 {
7231 { "vpshld", { XM, EXx, VexW }, 0 },
7232 },
7233
7234 /* VEX_LEN_0FXOP_09_97 */
7235 {
7236 { "vpshlq", { XM, EXx, VexW }, 0 },
7237 },
7238
7239 /* VEX_LEN_0FXOP_09_98 */
7240 {
7241 { "vpshab", { XM, EXx, VexW }, 0 },
7242 },
7243
7244 /* VEX_LEN_0FXOP_09_99 */
7245 {
7246 { "vpshaw", { XM, EXx, VexW }, 0 },
7247 },
7248
7249 /* VEX_LEN_0FXOP_09_9A */
7250 {
7251 { "vpshad", { XM, EXx, VexW }, 0 },
7252 },
7253
7254 /* VEX_LEN_0FXOP_09_9B */
7255 {
7256 { "vpshaq", { XM, EXx, VexW }, 0 },
7257 },
7258
7259 /* VEX_LEN_0FXOP_09_C1 */
7260 {
7261 { VEX_W_TABLE (VEX_W_0FXOP_09_C1_L_0) },
7262 },
7263
7264 /* VEX_LEN_0FXOP_09_C2 */
7265 {
7266 { VEX_W_TABLE (VEX_W_0FXOP_09_C2_L_0) },
7267 },
7268
7269 /* VEX_LEN_0FXOP_09_C3 */
7270 {
7271 { VEX_W_TABLE (VEX_W_0FXOP_09_C3_L_0) },
7272 },
7273
7274 /* VEX_LEN_0FXOP_09_C6 */
7275 {
7276 { VEX_W_TABLE (VEX_W_0FXOP_09_C6_L_0) },
7277 },
7278
7279 /* VEX_LEN_0FXOP_09_C7 */
7280 {
7281 { VEX_W_TABLE (VEX_W_0FXOP_09_C7_L_0) },
7282 },
7283
7284 /* VEX_LEN_0FXOP_09_CB */
7285 {
7286 { VEX_W_TABLE (VEX_W_0FXOP_09_CB_L_0) },
7287 },
7288
7289 /* VEX_LEN_0FXOP_09_D1 */
7290 {
7291 { VEX_W_TABLE (VEX_W_0FXOP_09_D1_L_0) },
7292 },
7293
7294 /* VEX_LEN_0FXOP_09_D2 */
7295 {
7296 { VEX_W_TABLE (VEX_W_0FXOP_09_D2_L_0) },
7297 },
7298
7299 /* VEX_LEN_0FXOP_09_D3 */
7300 {
7301 { VEX_W_TABLE (VEX_W_0FXOP_09_D3_L_0) },
7302 },
7303
7304 /* VEX_LEN_0FXOP_09_D6 */
7305 {
7306 { VEX_W_TABLE (VEX_W_0FXOP_09_D6_L_0) },
7307 },
7308
7309 /* VEX_LEN_0FXOP_09_D7 */
7310 {
7311 { VEX_W_TABLE (VEX_W_0FXOP_09_D7_L_0) },
7312 },
7313
7314 /* VEX_LEN_0FXOP_09_DB */
7315 {
7316 { VEX_W_TABLE (VEX_W_0FXOP_09_DB_L_0) },
7317 },
7318
7319 /* VEX_LEN_0FXOP_09_E1 */
7320 {
7321 { VEX_W_TABLE (VEX_W_0FXOP_09_E1_L_0) },
7322 },
7323
7324 /* VEX_LEN_0FXOP_09_E2 */
7325 {
7326 { VEX_W_TABLE (VEX_W_0FXOP_09_E2_L_0) },
7327 },
7328
7329 /* VEX_LEN_0FXOP_09_E3 */
7330 {
7331 { VEX_W_TABLE (VEX_W_0FXOP_09_E3_L_0) },
7332 },
7333
7334 /* VEX_LEN_0FXOP_0A_12 */
7335 {
7336 { REG_TABLE (REG_0FXOP_0A_12_L_0) },
7337 },
7338 };
7339
7340 #include "i386-dis-evex-len.h"
7341
7342 static const struct dis386 vex_w_table[][2] = {
7343 {
7344 /* VEX_W_0F41_P_0_LEN_1 */
7345 { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
7346 { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
7347 },
7348 {
7349 /* VEX_W_0F41_P_2_LEN_1 */
7350 { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
7351 { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
7352 },
7353 {
7354 /* VEX_W_0F42_P_0_LEN_1 */
7355 { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
7356 { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
7357 },
7358 {
7359 /* VEX_W_0F42_P_2_LEN_1 */
7360 { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
7361 { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
7362 },
7363 {
7364 /* VEX_W_0F44_P_0_LEN_0 */
7365 { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
7366 { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
7367 },
7368 {
7369 /* VEX_W_0F44_P_2_LEN_0 */
7370 { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
7371 { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
7372 },
7373 {
7374 /* VEX_W_0F45_P_0_LEN_1 */
7375 { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
7376 { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
7377 },
7378 {
7379 /* VEX_W_0F45_P_2_LEN_1 */
7380 { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
7381 { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
7382 },
7383 {
7384 /* VEX_W_0F46_P_0_LEN_1 */
7385 { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
7386 { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
7387 },
7388 {
7389 /* VEX_W_0F46_P_2_LEN_1 */
7390 { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
7391 { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
7392 },
7393 {
7394 /* VEX_W_0F47_P_0_LEN_1 */
7395 { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
7396 { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
7397 },
7398 {
7399 /* VEX_W_0F47_P_2_LEN_1 */
7400 { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
7401 { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
7402 },
7403 {
7404 /* VEX_W_0F4A_P_0_LEN_1 */
7405 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
7406 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
7407 },
7408 {
7409 /* VEX_W_0F4A_P_2_LEN_1 */
7410 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
7411 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
7412 },
7413 {
7414 /* VEX_W_0F4B_P_0_LEN_1 */
7415 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
7416 { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
7417 },
7418 {
7419 /* VEX_W_0F4B_P_2_LEN_1 */
7420 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
7421 },
7422 {
7423 /* VEX_W_0F90_P_0_LEN_0 */
7424 { "kmovw", { MaskG, MaskE }, 0 },
7425 { "kmovq", { MaskG, MaskE }, 0 },
7426 },
7427 {
7428 /* VEX_W_0F90_P_2_LEN_0 */
7429 { "kmovb", { MaskG, MaskBDE }, 0 },
7430 { "kmovd", { MaskG, MaskBDE }, 0 },
7431 },
7432 {
7433 /* VEX_W_0F91_P_0_LEN_0 */
7434 { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
7435 { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
7436 },
7437 {
7438 /* VEX_W_0F91_P_2_LEN_0 */
7439 { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
7440 { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
7441 },
7442 {
7443 /* VEX_W_0F92_P_0_LEN_0 */
7444 { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
7445 },
7446 {
7447 /* VEX_W_0F92_P_2_LEN_0 */
7448 { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
7449 },
7450 {
7451 /* VEX_W_0F93_P_0_LEN_0 */
7452 { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
7453 },
7454 {
7455 /* VEX_W_0F93_P_2_LEN_0 */
7456 { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
7457 },
7458 {
7459 /* VEX_W_0F98_P_0_LEN_0 */
7460 { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
7461 { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
7462 },
7463 {
7464 /* VEX_W_0F98_P_2_LEN_0 */
7465 { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
7466 { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
7467 },
7468 {
7469 /* VEX_W_0F99_P_0_LEN_0 */
7470 { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
7471 { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
7472 },
7473 {
7474 /* VEX_W_0F99_P_2_LEN_0 */
7475 { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
7476 { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
7477 },
7478 {
7479 /* VEX_W_0F380C */
7480 { "vpermilps", { XM, Vex, EXx }, PREFIX_DATA },
7481 },
7482 {
7483 /* VEX_W_0F380D */
7484 { "vpermilpd", { XM, Vex, EXx }, PREFIX_DATA },
7485 },
7486 {
7487 /* VEX_W_0F380E */
7488 { "vtestps", { XM, EXx }, PREFIX_DATA },
7489 },
7490 {
7491 /* VEX_W_0F380F */
7492 { "vtestpd", { XM, EXx }, PREFIX_DATA },
7493 },
7494 {
7495 /* VEX_W_0F3813 */
7496 { "vcvtph2ps", { XM, EXxmmq }, PREFIX_DATA },
7497 },
7498 {
7499 /* VEX_W_0F3816_L_1 */
7500 { "vpermps", { XM, Vex, EXx }, PREFIX_DATA },
7501 },
7502 {
7503 /* VEX_W_0F3818 */
7504 { "vbroadcastss", { XM, EXxmm_md }, PREFIX_DATA },
7505 },
7506 {
7507 /* VEX_W_0F3819_L_1 */
7508 { "vbroadcastsd", { XM, EXxmm_mq }, PREFIX_DATA },
7509 },
7510 {
7511 /* VEX_W_0F381A_M_0_L_1 */
7512 { "vbroadcastf128", { XM, Mxmm }, PREFIX_DATA },
7513 },
7514 {
7515 /* VEX_W_0F382C_M_0 */
7516 { "vmaskmovps", { XM, Vex, Mx }, PREFIX_DATA },
7517 },
7518 {
7519 /* VEX_W_0F382D_M_0 */
7520 { "vmaskmovpd", { XM, Vex, Mx }, PREFIX_DATA },
7521 },
7522 {
7523 /* VEX_W_0F382E_M_0 */
7524 { "vmaskmovps", { Mx, Vex, XM }, PREFIX_DATA },
7525 },
7526 {
7527 /* VEX_W_0F382F_M_0 */
7528 { "vmaskmovpd", { Mx, Vex, XM }, PREFIX_DATA },
7529 },
7530 {
7531 /* VEX_W_0F3836 */
7532 { "vpermd", { XM, Vex, EXx }, PREFIX_DATA },
7533 },
7534 {
7535 /* VEX_W_0F3846 */
7536 { "vpsravd", { XM, Vex, EXx }, PREFIX_DATA },
7537 },
7538 {
7539 /* VEX_W_0F3849_X86_64_P_0 */
7540 { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_0_W_0) },
7541 },
7542 {
7543 /* VEX_W_0F3849_X86_64_P_2 */
7544 { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_2_W_0) },
7545 },
7546 {
7547 /* VEX_W_0F3849_X86_64_P_3 */
7548 { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_3_W_0) },
7549 },
7550 {
7551 /* VEX_W_0F384B_X86_64_P_1 */
7552 { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_1_W_0) },
7553 },
7554 {
7555 /* VEX_W_0F384B_X86_64_P_2 */
7556 { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_2_W_0) },
7557 },
7558 {
7559 /* VEX_W_0F384B_X86_64_P_3 */
7560 { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_3_W_0) },
7561 },
7562 {
7563 /* VEX_W_0F3858 */
7564 { "vpbroadcastd", { XM, EXxmm_md }, PREFIX_DATA },
7565 },
7566 {
7567 /* VEX_W_0F3859 */
7568 { "vpbroadcastq", { XM, EXxmm_mq }, PREFIX_DATA },
7569 },
7570 {
7571 /* VEX_W_0F385A_M_0_L_0 */
7572 { "vbroadcasti128", { XM, Mxmm }, PREFIX_DATA },
7573 },
7574 {
7575 /* VEX_W_0F385C_X86_64_P_1 */
7576 { MOD_TABLE (MOD_VEX_0F385C_X86_64_P_1_W_0) },
7577 },
7578 {
7579 /* VEX_W_0F385E_X86_64_P_0 */
7580 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_0_W_0) },
7581 },
7582 {
7583 /* VEX_W_0F385E_X86_64_P_1 */
7584 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_1_W_0) },
7585 },
7586 {
7587 /* VEX_W_0F385E_X86_64_P_2 */
7588 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_2_W_0) },
7589 },
7590 {
7591 /* VEX_W_0F385E_X86_64_P_3 */
7592 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_3_W_0) },
7593 },
7594 {
7595 /* VEX_W_0F3878 */
7596 { "vpbroadcastb", { XM, EXxmm_mb }, PREFIX_DATA },
7597 },
7598 {
7599 /* VEX_W_0F3879 */
7600 { "vpbroadcastw", { XM, EXxmm_mw }, PREFIX_DATA },
7601 },
7602 {
7603 /* VEX_W_0F38CF */
7604 { "vgf2p8mulb", { XM, Vex, EXx }, PREFIX_DATA },
7605 },
7606 {
7607 /* VEX_W_0F3A00_L_1 */
7608 { Bad_Opcode },
7609 { "vpermq", { XM, EXx, Ib }, PREFIX_DATA },
7610 },
7611 {
7612 /* VEX_W_0F3A01_L_1 */
7613 { Bad_Opcode },
7614 { "vpermpd", { XM, EXx, Ib }, PREFIX_DATA },
7615 },
7616 {
7617 /* VEX_W_0F3A02 */
7618 { "vpblendd", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7619 },
7620 {
7621 /* VEX_W_0F3A04 */
7622 { "vpermilps", { XM, EXx, Ib }, PREFIX_DATA },
7623 },
7624 {
7625 /* VEX_W_0F3A05 */
7626 { "vpermilpd", { XM, EXx, Ib }, PREFIX_DATA },
7627 },
7628 {
7629 /* VEX_W_0F3A06_L_1 */
7630 { "vperm2f128", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7631 },
7632 {
7633 /* VEX_W_0F3A18_L_1 */
7634 { "vinsertf128", { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7635 },
7636 {
7637 /* VEX_W_0F3A19_L_1 */
7638 { "vextractf128", { EXxmm, XM, Ib }, PREFIX_DATA },
7639 },
7640 {
7641 /* VEX_W_0F3A1D */
7642 { "vcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, PREFIX_DATA },
7643 },
7644 {
7645 /* VEX_W_0F3A38_L_1 */
7646 { "vinserti128", { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7647 },
7648 {
7649 /* VEX_W_0F3A39_L_1 */
7650 { "vextracti128", { EXxmm, XM, Ib }, PREFIX_DATA },
7651 },
7652 {
7653 /* VEX_W_0F3A46_L_1 */
7654 { "vperm2i128", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7655 },
7656 {
7657 /* VEX_W_0F3A4A */
7658 { "vblendvps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7659 },
7660 {
7661 /* VEX_W_0F3A4B */
7662 { "vblendvpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7663 },
7664 {
7665 /* VEX_W_0F3A4C */
7666 { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7667 },
7668 {
7669 /* VEX_W_0F3ACE */
7670 { Bad_Opcode },
7671 { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7672 },
7673 {
7674 /* VEX_W_0F3ACF */
7675 { Bad_Opcode },
7676 { "vgf2p8affineinvqb", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7677 },
7678 /* VEX_W_0FXOP_08_85_L_0 */
7679 {
7680 { "vpmacssww", { XM, Vex, EXx, XMVexI4 }, 0 },
7681 },
7682 /* VEX_W_0FXOP_08_86_L_0 */
7683 {
7684 { "vpmacsswd", { XM, Vex, EXx, XMVexI4 }, 0 },
7685 },
7686 /* VEX_W_0FXOP_08_87_L_0 */
7687 {
7688 { "vpmacssdql", { XM, Vex, EXx, XMVexI4 }, 0 },
7689 },
7690 /* VEX_W_0FXOP_08_8E_L_0 */
7691 {
7692 { "vpmacssdd", { XM, Vex, EXx, XMVexI4 }, 0 },
7693 },
7694 /* VEX_W_0FXOP_08_8F_L_0 */
7695 {
7696 { "vpmacssdqh", { XM, Vex, EXx, XMVexI4 }, 0 },
7697 },
7698 /* VEX_W_0FXOP_08_95_L_0 */
7699 {
7700 { "vpmacsww", { XM, Vex, EXx, XMVexI4 }, 0 },
7701 },
7702 /* VEX_W_0FXOP_08_96_L_0 */
7703 {
7704 { "vpmacswd", { XM, Vex, EXx, XMVexI4 }, 0 },
7705 },
7706 /* VEX_W_0FXOP_08_97_L_0 */
7707 {
7708 { "vpmacsdql", { XM, Vex, EXx, XMVexI4 }, 0 },
7709 },
7710 /* VEX_W_0FXOP_08_9E_L_0 */
7711 {
7712 { "vpmacsdd", { XM, Vex, EXx, XMVexI4 }, 0 },
7713 },
7714 /* VEX_W_0FXOP_08_9F_L_0 */
7715 {
7716 { "vpmacsdqh", { XM, Vex, EXx, XMVexI4 }, 0 },
7717 },
7718 /* VEX_W_0FXOP_08_A6_L_0 */
7719 {
7720 { "vpmadcsswd", { XM, Vex, EXx, XMVexI4 }, 0 },
7721 },
7722 /* VEX_W_0FXOP_08_B6_L_0 */
7723 {
7724 { "vpmadcswd", { XM, Vex, EXx, XMVexI4 }, 0 },
7725 },
7726 /* VEX_W_0FXOP_08_C0_L_0 */
7727 {
7728 { "vprotb", { XM, EXx, Ib }, 0 },
7729 },
7730 /* VEX_W_0FXOP_08_C1_L_0 */
7731 {
7732 { "vprotw", { XM, EXx, Ib }, 0 },
7733 },
7734 /* VEX_W_0FXOP_08_C2_L_0 */
7735 {
7736 { "vprotd", { XM, EXx, Ib }, 0 },
7737 },
7738 /* VEX_W_0FXOP_08_C3_L_0 */
7739 {
7740 { "vprotq", { XM, EXx, Ib }, 0 },
7741 },
7742 /* VEX_W_0FXOP_08_CC_L_0 */
7743 {
7744 { "vpcomb", { XM, Vex, EXx, VPCOM }, 0 },
7745 },
7746 /* VEX_W_0FXOP_08_CD_L_0 */
7747 {
7748 { "vpcomw", { XM, Vex, EXx, VPCOM }, 0 },
7749 },
7750 /* VEX_W_0FXOP_08_CE_L_0 */
7751 {
7752 { "vpcomd", { XM, Vex, EXx, VPCOM }, 0 },
7753 },
7754 /* VEX_W_0FXOP_08_CF_L_0 */
7755 {
7756 { "vpcomq", { XM, Vex, EXx, VPCOM }, 0 },
7757 },
7758 /* VEX_W_0FXOP_08_EC_L_0 */
7759 {
7760 { "vpcomub", { XM, Vex, EXx, VPCOM }, 0 },
7761 },
7762 /* VEX_W_0FXOP_08_ED_L_0 */
7763 {
7764 { "vpcomuw", { XM, Vex, EXx, VPCOM }, 0 },
7765 },
7766 /* VEX_W_0FXOP_08_EE_L_0 */
7767 {
7768 { "vpcomud", { XM, Vex, EXx, VPCOM }, 0 },
7769 },
7770 /* VEX_W_0FXOP_08_EF_L_0 */
7771 {
7772 { "vpcomuq", { XM, Vex, EXx, VPCOM }, 0 },
7773 },
7774 /* VEX_W_0FXOP_09_80 */
7775 {
7776 { "vfrczps", { XM, EXx }, 0 },
7777 },
7778 /* VEX_W_0FXOP_09_81 */
7779 {
7780 { "vfrczpd", { XM, EXx }, 0 },
7781 },
7782 /* VEX_W_0FXOP_09_82 */
7783 {
7784 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_82_W_0) },
7785 },
7786 /* VEX_W_0FXOP_09_83 */
7787 {
7788 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_83_W_0) },
7789 },
7790 /* VEX_W_0FXOP_09_C1_L_0 */
7791 {
7792 { "vphaddbw", { XM, EXxmm }, 0 },
7793 },
7794 /* VEX_W_0FXOP_09_C2_L_0 */
7795 {
7796 { "vphaddbd", { XM, EXxmm }, 0 },
7797 },
7798 /* VEX_W_0FXOP_09_C3_L_0 */
7799 {
7800 { "vphaddbq", { XM, EXxmm }, 0 },
7801 },
7802 /* VEX_W_0FXOP_09_C6_L_0 */
7803 {
7804 { "vphaddwd", { XM, EXxmm }, 0 },
7805 },
7806 /* VEX_W_0FXOP_09_C7_L_0 */
7807 {
7808 { "vphaddwq", { XM, EXxmm }, 0 },
7809 },
7810 /* VEX_W_0FXOP_09_CB_L_0 */
7811 {
7812 { "vphadddq", { XM, EXxmm }, 0 },
7813 },
7814 /* VEX_W_0FXOP_09_D1_L_0 */
7815 {
7816 { "vphaddubw", { XM, EXxmm }, 0 },
7817 },
7818 /* VEX_W_0FXOP_09_D2_L_0 */
7819 {
7820 { "vphaddubd", { XM, EXxmm }, 0 },
7821 },
7822 /* VEX_W_0FXOP_09_D3_L_0 */
7823 {
7824 { "vphaddubq", { XM, EXxmm }, 0 },
7825 },
7826 /* VEX_W_0FXOP_09_D6_L_0 */
7827 {
7828 { "vphadduwd", { XM, EXxmm }, 0 },
7829 },
7830 /* VEX_W_0FXOP_09_D7_L_0 */
7831 {
7832 { "vphadduwq", { XM, EXxmm }, 0 },
7833 },
7834 /* VEX_W_0FXOP_09_DB_L_0 */
7835 {
7836 { "vphaddudq", { XM, EXxmm }, 0 },
7837 },
7838 /* VEX_W_0FXOP_09_E1_L_0 */
7839 {
7840 { "vphsubbw", { XM, EXxmm }, 0 },
7841 },
7842 /* VEX_W_0FXOP_09_E2_L_0 */
7843 {
7844 { "vphsubwd", { XM, EXxmm }, 0 },
7845 },
7846 /* VEX_W_0FXOP_09_E3_L_0 */
7847 {
7848 { "vphsubdq", { XM, EXxmm }, 0 },
7849 },
7850
7851 #include "i386-dis-evex-w.h"
7852 };
7853
7854 static const struct dis386 mod_table[][2] = {
7855 {
7856 /* MOD_8D */
7857 { "leaS", { Gv, M }, 0 },
7858 },
7859 {
7860 /* MOD_C6_REG_7 */
7861 { Bad_Opcode },
7862 { RM_TABLE (RM_C6_REG_7) },
7863 },
7864 {
7865 /* MOD_C7_REG_7 */
7866 { Bad_Opcode },
7867 { RM_TABLE (RM_C7_REG_7) },
7868 },
7869 {
7870 /* MOD_FF_REG_3 */
7871 { "{l|}call^", { indirEp }, 0 },
7872 },
7873 {
7874 /* MOD_FF_REG_5 */
7875 { "{l|}jmp^", { indirEp }, 0 },
7876 },
7877 {
7878 /* MOD_0F01_REG_0 */
7879 { X86_64_TABLE (X86_64_0F01_REG_0) },
7880 { RM_TABLE (RM_0F01_REG_0) },
7881 },
7882 {
7883 /* MOD_0F01_REG_1 */
7884 { X86_64_TABLE (X86_64_0F01_REG_1) },
7885 { RM_TABLE (RM_0F01_REG_1) },
7886 },
7887 {
7888 /* MOD_0F01_REG_2 */
7889 { X86_64_TABLE (X86_64_0F01_REG_2) },
7890 { RM_TABLE (RM_0F01_REG_2) },
7891 },
7892 {
7893 /* MOD_0F01_REG_3 */
7894 { X86_64_TABLE (X86_64_0F01_REG_3) },
7895 { RM_TABLE (RM_0F01_REG_3) },
7896 },
7897 {
7898 /* MOD_0F01_REG_5 */
7899 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) },
7900 { RM_TABLE (RM_0F01_REG_5_MOD_3) },
7901 },
7902 {
7903 /* MOD_0F01_REG_7 */
7904 { "invlpg", { Mb }, 0 },
7905 { RM_TABLE (RM_0F01_REG_7_MOD_3) },
7906 },
7907 {
7908 /* MOD_0F12_PREFIX_0 */
7909 { "movlpX", { XM, EXq }, 0 },
7910 { "movhlps", { XM, EXq }, 0 },
7911 },
7912 {
7913 /* MOD_0F12_PREFIX_2 */
7914 { "movlpX", { XM, EXq }, 0 },
7915 },
7916 {
7917 /* MOD_0F13 */
7918 { "movlpX", { EXq, XM }, PREFIX_OPCODE },
7919 },
7920 {
7921 /* MOD_0F16_PREFIX_0 */
7922 { "movhpX", { XM, EXq }, 0 },
7923 { "movlhps", { XM, EXq }, 0 },
7924 },
7925 {
7926 /* MOD_0F16_PREFIX_2 */
7927 { "movhpX", { XM, EXq }, 0 },
7928 },
7929 {
7930 /* MOD_0F17 */
7931 { "movhpX", { EXq, XM }, PREFIX_OPCODE },
7932 },
7933 {
7934 /* MOD_0F18_REG_0 */
7935 { "prefetchnta", { Mb }, 0 },
7936 },
7937 {
7938 /* MOD_0F18_REG_1 */
7939 { "prefetcht0", { Mb }, 0 },
7940 },
7941 {
7942 /* MOD_0F18_REG_2 */
7943 { "prefetcht1", { Mb }, 0 },
7944 },
7945 {
7946 /* MOD_0F18_REG_3 */
7947 { "prefetcht2", { Mb }, 0 },
7948 },
7949 {
7950 /* MOD_0F18_REG_4 */
7951 { "nop/reserved", { Mb }, 0 },
7952 },
7953 {
7954 /* MOD_0F18_REG_5 */
7955 { "nop/reserved", { Mb }, 0 },
7956 },
7957 {
7958 /* MOD_0F18_REG_6 */
7959 { "nop/reserved", { Mb }, 0 },
7960 },
7961 {
7962 /* MOD_0F18_REG_7 */
7963 { "nop/reserved", { Mb }, 0 },
7964 },
7965 {
7966 /* MOD_0F1A_PREFIX_0 */
7967 { "bndldx", { Gbnd, Mv_bnd }, 0 },
7968 { "nopQ", { Ev }, 0 },
7969 },
7970 {
7971 /* MOD_0F1B_PREFIX_0 */
7972 { "bndstx", { Mv_bnd, Gbnd }, 0 },
7973 { "nopQ", { Ev }, 0 },
7974 },
7975 {
7976 /* MOD_0F1B_PREFIX_1 */
7977 { "bndmk", { Gbnd, Mv_bnd }, 0 },
7978 { "nopQ", { Ev }, 0 },
7979 },
7980 {
7981 /* MOD_0F1C_PREFIX_0 */
7982 { REG_TABLE (REG_0F1C_P_0_MOD_0) },
7983 { "nopQ", { Ev }, 0 },
7984 },
7985 {
7986 /* MOD_0F1E_PREFIX_1 */
7987 { "nopQ", { Ev }, 0 },
7988 { REG_TABLE (REG_0F1E_P_1_MOD_3) },
7989 },
7990 {
7991 /* MOD_0F24 */
7992 { Bad_Opcode },
7993 { "movL", { Rd, Td }, 0 },
7994 },
7995 {
7996 /* MOD_0F26 */
7997 { Bad_Opcode },
7998 { "movL", { Td, Rd }, 0 },
7999 },
8000 {
8001 /* MOD_0F2B_PREFIX_0 */
8002 {"movntps", { Mx, XM }, PREFIX_OPCODE },
8003 },
8004 {
8005 /* MOD_0F2B_PREFIX_1 */
8006 {"movntss", { Md, XM }, PREFIX_OPCODE },
8007 },
8008 {
8009 /* MOD_0F2B_PREFIX_2 */
8010 {"movntpd", { Mx, XM }, PREFIX_OPCODE },
8011 },
8012 {
8013 /* MOD_0F2B_PREFIX_3 */
8014 {"movntsd", { Mq, XM }, PREFIX_OPCODE },
8015 },
8016 {
8017 /* MOD_0F50 */
8018 { Bad_Opcode },
8019 { "movmskpX", { Gdq, XS }, PREFIX_OPCODE },
8020 },
8021 {
8022 /* MOD_0F71_REG_2 */
8023 { Bad_Opcode },
8024 { "psrlw", { MS, Ib }, PREFIX_OPCODE },
8025 },
8026 {
8027 /* MOD_0F71_REG_4 */
8028 { Bad_Opcode },
8029 { "psraw", { MS, Ib }, PREFIX_OPCODE },
8030 },
8031 {
8032 /* MOD_0F71_REG_6 */
8033 { Bad_Opcode },
8034 { "psllw", { MS, Ib }, PREFIX_OPCODE },
8035 },
8036 {
8037 /* MOD_0F72_REG_2 */
8038 { Bad_Opcode },
8039 { "psrld", { MS, Ib }, PREFIX_OPCODE },
8040 },
8041 {
8042 /* MOD_0F72_REG_4 */
8043 { Bad_Opcode },
8044 { "psrad", { MS, Ib }, PREFIX_OPCODE },
8045 },
8046 {
8047 /* MOD_0F72_REG_6 */
8048 { Bad_Opcode },
8049 { "pslld", { MS, Ib }, PREFIX_OPCODE },
8050 },
8051 {
8052 /* MOD_0F73_REG_2 */
8053 { Bad_Opcode },
8054 { "psrlq", { MS, Ib }, PREFIX_OPCODE },
8055 },
8056 {
8057 /* MOD_0F73_REG_3 */
8058 { Bad_Opcode },
8059 { "psrldq", { XS, Ib }, PREFIX_DATA },
8060 },
8061 {
8062 /* MOD_0F73_REG_6 */
8063 { Bad_Opcode },
8064 { "psllq", { MS, Ib }, PREFIX_OPCODE },
8065 },
8066 {
8067 /* MOD_0F73_REG_7 */
8068 { Bad_Opcode },
8069 { "pslldq", { XS, Ib }, PREFIX_DATA },
8070 },
8071 {
8072 /* MOD_0FAE_REG_0 */
8073 { "fxsave", { FXSAVE }, 0 },
8074 { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) },
8075 },
8076 {
8077 /* MOD_0FAE_REG_1 */
8078 { "fxrstor", { FXSAVE }, 0 },
8079 { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) },
8080 },
8081 {
8082 /* MOD_0FAE_REG_2 */
8083 { "ldmxcsr", { Md }, 0 },
8084 { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) },
8085 },
8086 {
8087 /* MOD_0FAE_REG_3 */
8088 { "stmxcsr", { Md }, 0 },
8089 { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) },
8090 },
8091 {
8092 /* MOD_0FAE_REG_4 */
8093 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) },
8094 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) },
8095 },
8096 {
8097 /* MOD_0FAE_REG_5 */
8098 { "xrstor", { FXSAVE }, PREFIX_OPCODE },
8099 { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) },
8100 },
8101 {
8102 /* MOD_0FAE_REG_6 */
8103 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) },
8104 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) },
8105 },
8106 {
8107 /* MOD_0FAE_REG_7 */
8108 { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) },
8109 { RM_TABLE (RM_0FAE_REG_7_MOD_3) },
8110 },
8111 {
8112 /* MOD_0FB2 */
8113 { "lssS", { Gv, Mp }, 0 },
8114 },
8115 {
8116 /* MOD_0FB4 */
8117 { "lfsS", { Gv, Mp }, 0 },
8118 },
8119 {
8120 /* MOD_0FB5 */
8121 { "lgsS", { Gv, Mp }, 0 },
8122 },
8123 {
8124 /* MOD_0FC3 */
8125 { "movntiS", { Edq, Gdq }, PREFIX_OPCODE },
8126 },
8127 {
8128 /* MOD_0FC7_REG_3 */
8129 { "xrstors", { FXSAVE }, 0 },
8130 },
8131 {
8132 /* MOD_0FC7_REG_4 */
8133 { "xsavec", { FXSAVE }, 0 },
8134 },
8135 {
8136 /* MOD_0FC7_REG_5 */
8137 { "xsaves", { FXSAVE }, 0 },
8138 },
8139 {
8140 /* MOD_0FC7_REG_6 */
8141 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) },
8142 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) }
8143 },
8144 {
8145 /* MOD_0FC7_REG_7 */
8146 { "vmptrst", { Mq }, 0 },
8147 { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) }
8148 },
8149 {
8150 /* MOD_0FD7 */
8151 { Bad_Opcode },
8152 { "pmovmskb", { Gdq, MS }, 0 },
8153 },
8154 {
8155 /* MOD_0FE7_PREFIX_2 */
8156 { "movntdq", { Mx, XM }, 0 },
8157 },
8158 {
8159 /* MOD_0FF0_PREFIX_3 */
8160 { "lddqu", { XM, M }, 0 },
8161 },
8162 {
8163 /* MOD_0F382A */
8164 { "movntdqa", { XM, Mx }, PREFIX_DATA },
8165 },
8166 {
8167 /* MOD_VEX_0F3849_X86_64_P_0_W_0 */
8168 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0) },
8169 { REG_TABLE (REG_VEX_0F3849_X86_64_P_0_W_0_M_1) },
8170 },
8171 {
8172 /* MOD_VEX_0F3849_X86_64_P_2_W_0 */
8173 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0) },
8174 },
8175 {
8176 /* MOD_VEX_0F3849_X86_64_P_3_W_0 */
8177 { Bad_Opcode },
8178 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0) },
8179 },
8180 {
8181 /* MOD_VEX_0F384B_X86_64_P_1_W_0 */
8182 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0) },
8183 },
8184 {
8185 /* MOD_VEX_0F384B_X86_64_P_2_W_0 */
8186 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0) },
8187 },
8188 {
8189 /* MOD_VEX_0F384B_X86_64_P_3_W_0 */
8190 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0) },
8191 },
8192 {
8193 /* MOD_VEX_0F385C_X86_64_P_1_W_0 */
8194 { Bad_Opcode },
8195 { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0) },
8196 },
8197 {
8198 /* MOD_VEX_0F385E_X86_64_P_0_W_0 */
8199 { Bad_Opcode },
8200 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0) },
8201 },
8202 {
8203 /* MOD_VEX_0F385E_X86_64_P_1_W_0 */
8204 { Bad_Opcode },
8205 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0) },
8206 },
8207 {
8208 /* MOD_VEX_0F385E_X86_64_P_2_W_0 */
8209 { Bad_Opcode },
8210 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0) },
8211 },
8212 {
8213 /* MOD_VEX_0F385E_X86_64_P_3_W_0 */
8214 { Bad_Opcode },
8215 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0) },
8216 },
8217 {
8218 /* MOD_0F38F5 */
8219 { "wrussK", { M, Gdq }, PREFIX_DATA },
8220 },
8221 {
8222 /* MOD_0F38F6_PREFIX_0 */
8223 { "wrssK", { M, Gdq }, PREFIX_OPCODE },
8224 },
8225 {
8226 /* MOD_0F38F8_PREFIX_1 */
8227 { "enqcmds", { Gva, M }, PREFIX_OPCODE },
8228 },
8229 {
8230 /* MOD_0F38F8_PREFIX_2 */
8231 { "movdir64b", { Gva, M }, PREFIX_OPCODE },
8232 },
8233 {
8234 /* MOD_0F38F8_PREFIX_3 */
8235 { "enqcmd", { Gva, M }, PREFIX_OPCODE },
8236 },
8237 {
8238 /* MOD_0F38F9 */
8239 { "movdiri", { Edq, Gdq }, PREFIX_OPCODE },
8240 },
8241 {
8242 /* MOD_62_32BIT */
8243 { "bound{S|}", { Gv, Ma }, 0 },
8244 { EVEX_TABLE (EVEX_0F) },
8245 },
8246 {
8247 /* MOD_C4_32BIT */
8248 { "lesS", { Gv, Mp }, 0 },
8249 { VEX_C4_TABLE (VEX_0F) },
8250 },
8251 {
8252 /* MOD_C5_32BIT */
8253 { "ldsS", { Gv, Mp }, 0 },
8254 { VEX_C5_TABLE (VEX_0F) },
8255 },
8256 {
8257 /* MOD_VEX_0F12_PREFIX_0 */
8258 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
8259 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
8260 },
8261 {
8262 /* MOD_VEX_0F12_PREFIX_2 */
8263 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0) },
8264 },
8265 {
8266 /* MOD_VEX_0F13 */
8267 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
8268 },
8269 {
8270 /* MOD_VEX_0F16_PREFIX_0 */
8271 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
8272 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
8273 },
8274 {
8275 /* MOD_VEX_0F16_PREFIX_2 */
8276 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0) },
8277 },
8278 {
8279 /* MOD_VEX_0F17 */
8280 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
8281 },
8282 {
8283 /* MOD_VEX_0F2B */
8284 { "vmovntpX", { Mx, XM }, PREFIX_OPCODE },
8285 },
8286 {
8287 /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
8288 { Bad_Opcode },
8289 { "kandw", { MaskG, MaskVex, MaskR }, 0 },
8290 },
8291 {
8292 /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
8293 { Bad_Opcode },
8294 { "kandq", { MaskG, MaskVex, MaskR }, 0 },
8295 },
8296 {
8297 /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
8298 { Bad_Opcode },
8299 { "kandb", { MaskG, MaskVex, MaskR }, 0 },
8300 },
8301 {
8302 /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
8303 { Bad_Opcode },
8304 { "kandd", { MaskG, MaskVex, MaskR }, 0 },
8305 },
8306 {
8307 /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
8308 { Bad_Opcode },
8309 { "kandnw", { MaskG, MaskVex, MaskR }, 0 },
8310 },
8311 {
8312 /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
8313 { Bad_Opcode },
8314 { "kandnq", { MaskG, MaskVex, MaskR }, 0 },
8315 },
8316 {
8317 /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
8318 { Bad_Opcode },
8319 { "kandnb", { MaskG, MaskVex, MaskR }, 0 },
8320 },
8321 {
8322 /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
8323 { Bad_Opcode },
8324 { "kandnd", { MaskG, MaskVex, MaskR }, 0 },
8325 },
8326 {
8327 /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
8328 { Bad_Opcode },
8329 { "knotw", { MaskG, MaskR }, 0 },
8330 },
8331 {
8332 /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
8333 { Bad_Opcode },
8334 { "knotq", { MaskG, MaskR }, 0 },
8335 },
8336 {
8337 /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
8338 { Bad_Opcode },
8339 { "knotb", { MaskG, MaskR }, 0 },
8340 },
8341 {
8342 /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
8343 { Bad_Opcode },
8344 { "knotd", { MaskG, MaskR }, 0 },
8345 },
8346 {
8347 /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
8348 { Bad_Opcode },
8349 { "korw", { MaskG, MaskVex, MaskR }, 0 },
8350 },
8351 {
8352 /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
8353 { Bad_Opcode },
8354 { "korq", { MaskG, MaskVex, MaskR }, 0 },
8355 },
8356 {
8357 /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
8358 { Bad_Opcode },
8359 { "korb", { MaskG, MaskVex, MaskR }, 0 },
8360 },
8361 {
8362 /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
8363 { Bad_Opcode },
8364 { "kord", { MaskG, MaskVex, MaskR }, 0 },
8365 },
8366 {
8367 /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
8368 { Bad_Opcode },
8369 { "kxnorw", { MaskG, MaskVex, MaskR }, 0 },
8370 },
8371 {
8372 /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
8373 { Bad_Opcode },
8374 { "kxnorq", { MaskG, MaskVex, MaskR }, 0 },
8375 },
8376 {
8377 /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
8378 { Bad_Opcode },
8379 { "kxnorb", { MaskG, MaskVex, MaskR }, 0 },
8380 },
8381 {
8382 /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
8383 { Bad_Opcode },
8384 { "kxnord", { MaskG, MaskVex, MaskR }, 0 },
8385 },
8386 {
8387 /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
8388 { Bad_Opcode },
8389 { "kxorw", { MaskG, MaskVex, MaskR }, 0 },
8390 },
8391 {
8392 /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
8393 { Bad_Opcode },
8394 { "kxorq", { MaskG, MaskVex, MaskR }, 0 },
8395 },
8396 {
8397 /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
8398 { Bad_Opcode },
8399 { "kxorb", { MaskG, MaskVex, MaskR }, 0 },
8400 },
8401 {
8402 /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
8403 { Bad_Opcode },
8404 { "kxord", { MaskG, MaskVex, MaskR }, 0 },
8405 },
8406 {
8407 /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
8408 { Bad_Opcode },
8409 { "kaddw", { MaskG, MaskVex, MaskR }, 0 },
8410 },
8411 {
8412 /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
8413 { Bad_Opcode },
8414 { "kaddq", { MaskG, MaskVex, MaskR }, 0 },
8415 },
8416 {
8417 /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
8418 { Bad_Opcode },
8419 { "kaddb", { MaskG, MaskVex, MaskR }, 0 },
8420 },
8421 {
8422 /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
8423 { Bad_Opcode },
8424 { "kaddd", { MaskG, MaskVex, MaskR }, 0 },
8425 },
8426 {
8427 /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
8428 { Bad_Opcode },
8429 { "kunpckwd", { MaskG, MaskVex, MaskR }, 0 },
8430 },
8431 {
8432 /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
8433 { Bad_Opcode },
8434 { "kunpckdq", { MaskG, MaskVex, MaskR }, 0 },
8435 },
8436 {
8437 /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
8438 { Bad_Opcode },
8439 { "kunpckbw", { MaskG, MaskVex, MaskR }, 0 },
8440 },
8441 {
8442 /* MOD_VEX_0F50 */
8443 { Bad_Opcode },
8444 { "vmovmskpX", { Gdq, XS }, PREFIX_OPCODE },
8445 },
8446 {
8447 /* MOD_VEX_0F71_REG_2 */
8448 { Bad_Opcode },
8449 { "vpsrlw", { Vex, XS, Ib }, PREFIX_DATA },
8450 },
8451 {
8452 /* MOD_VEX_0F71_REG_4 */
8453 { Bad_Opcode },
8454 { "vpsraw", { Vex, XS, Ib }, PREFIX_DATA },
8455 },
8456 {
8457 /* MOD_VEX_0F71_REG_6 */
8458 { Bad_Opcode },
8459 { "vpsllw", { Vex, XS, Ib }, PREFIX_DATA },
8460 },
8461 {
8462 /* MOD_VEX_0F72_REG_2 */
8463 { Bad_Opcode },
8464 { "vpsrld", { Vex, XS, Ib }, PREFIX_DATA },
8465 },
8466 {
8467 /* MOD_VEX_0F72_REG_4 */
8468 { Bad_Opcode },
8469 { "vpsrad", { Vex, XS, Ib }, PREFIX_DATA },
8470 },
8471 {
8472 /* MOD_VEX_0F72_REG_6 */
8473 { Bad_Opcode },
8474 { "vpslld", { Vex, XS, Ib }, PREFIX_DATA },
8475 },
8476 {
8477 /* MOD_VEX_0F73_REG_2 */
8478 { Bad_Opcode },
8479 { "vpsrlq", { Vex, XS, Ib }, PREFIX_DATA },
8480 },
8481 {
8482 /* MOD_VEX_0F73_REG_3 */
8483 { Bad_Opcode },
8484 { "vpsrldq", { Vex, XS, Ib }, PREFIX_DATA },
8485 },
8486 {
8487 /* MOD_VEX_0F73_REG_6 */
8488 { Bad_Opcode },
8489 { "vpsllq", { Vex, XS, Ib }, PREFIX_DATA },
8490 },
8491 {
8492 /* MOD_VEX_0F73_REG_7 */
8493 { Bad_Opcode },
8494 { "vpslldq", { Vex, XS, Ib }, PREFIX_DATA },
8495 },
8496 {
8497 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
8498 { "kmovw", { Ew, MaskG }, 0 },
8499 { Bad_Opcode },
8500 },
8501 {
8502 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
8503 { "kmovq", { Eq, MaskG }, 0 },
8504 { Bad_Opcode },
8505 },
8506 {
8507 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
8508 { "kmovb", { Eb, MaskG }, 0 },
8509 { Bad_Opcode },
8510 },
8511 {
8512 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
8513 { "kmovd", { Ed, MaskG }, 0 },
8514 { Bad_Opcode },
8515 },
8516 {
8517 /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
8518 { Bad_Opcode },
8519 { "kmovw", { MaskG, Rdq }, 0 },
8520 },
8521 {
8522 /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
8523 { Bad_Opcode },
8524 { "kmovb", { MaskG, Rdq }, 0 },
8525 },
8526 {
8527 /* MOD_VEX_0F92_P_3_LEN_0 */
8528 { Bad_Opcode },
8529 { "kmovK", { MaskG, Rdq }, 0 },
8530 },
8531 {
8532 /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
8533 { Bad_Opcode },
8534 { "kmovw", { Gdq, MaskR }, 0 },
8535 },
8536 {
8537 /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
8538 { Bad_Opcode },
8539 { "kmovb", { Gdq, MaskR }, 0 },
8540 },
8541 {
8542 /* MOD_VEX_0F93_P_3_LEN_0 */
8543 { Bad_Opcode },
8544 { "kmovK", { Gdq, MaskR }, 0 },
8545 },
8546 {
8547 /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
8548 { Bad_Opcode },
8549 { "kortestw", { MaskG, MaskR }, 0 },
8550 },
8551 {
8552 /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
8553 { Bad_Opcode },
8554 { "kortestq", { MaskG, MaskR }, 0 },
8555 },
8556 {
8557 /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
8558 { Bad_Opcode },
8559 { "kortestb", { MaskG, MaskR }, 0 },
8560 },
8561 {
8562 /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
8563 { Bad_Opcode },
8564 { "kortestd", { MaskG, MaskR }, 0 },
8565 },
8566 {
8567 /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
8568 { Bad_Opcode },
8569 { "ktestw", { MaskG, MaskR }, 0 },
8570 },
8571 {
8572 /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
8573 { Bad_Opcode },
8574 { "ktestq", { MaskG, MaskR }, 0 },
8575 },
8576 {
8577 /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
8578 { Bad_Opcode },
8579 { "ktestb", { MaskG, MaskR }, 0 },
8580 },
8581 {
8582 /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
8583 { Bad_Opcode },
8584 { "ktestd", { MaskG, MaskR }, 0 },
8585 },
8586 {
8587 /* MOD_VEX_0FAE_REG_2 */
8588 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
8589 },
8590 {
8591 /* MOD_VEX_0FAE_REG_3 */
8592 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
8593 },
8594 {
8595 /* MOD_VEX_0FD7 */
8596 { Bad_Opcode },
8597 { "vpmovmskb", { Gdq, XS }, PREFIX_DATA },
8598 },
8599 {
8600 /* MOD_VEX_0FE7 */
8601 { "vmovntdq", { Mx, XM }, PREFIX_DATA },
8602 },
8603 {
8604 /* MOD_VEX_0FF0_PREFIX_3 */
8605 { "vlddqu", { XM, M }, 0 },
8606 },
8607 {
8608 /* MOD_VEX_0F381A */
8609 { VEX_LEN_TABLE (VEX_LEN_0F381A_M_0) },
8610 },
8611 {
8612 /* MOD_VEX_0F382A */
8613 { "vmovntdqa", { XM, Mx }, PREFIX_DATA },
8614 },
8615 {
8616 /* MOD_VEX_0F382C */
8617 { VEX_W_TABLE (VEX_W_0F382C_M_0) },
8618 },
8619 {
8620 /* MOD_VEX_0F382D */
8621 { VEX_W_TABLE (VEX_W_0F382D_M_0) },
8622 },
8623 {
8624 /* MOD_VEX_0F382E */
8625 { VEX_W_TABLE (VEX_W_0F382E_M_0) },
8626 },
8627 {
8628 /* MOD_VEX_0F382F */
8629 { VEX_W_TABLE (VEX_W_0F382F_M_0) },
8630 },
8631 {
8632 /* MOD_VEX_0F385A */
8633 { VEX_LEN_TABLE (VEX_LEN_0F385A_M_0) },
8634 },
8635 {
8636 /* MOD_VEX_0F388C */
8637 { "vpmaskmov%DQ", { XM, Vex, Mx }, PREFIX_DATA },
8638 },
8639 {
8640 /* MOD_VEX_0F388E */
8641 { "vpmaskmov%DQ", { Mx, Vex, XM }, PREFIX_DATA },
8642 },
8643 {
8644 /* MOD_VEX_0F3A30_L_0 */
8645 { Bad_Opcode },
8646 { "kshiftr%BW", { MaskG, MaskR, Ib }, PREFIX_DATA },
8647 },
8648 {
8649 /* MOD_VEX_0F3A31_L_0 */
8650 { Bad_Opcode },
8651 { "kshiftr%DQ", { MaskG, MaskR, Ib }, PREFIX_DATA },
8652 },
8653 {
8654 /* MOD_VEX_0F3A32_L_0 */
8655 { Bad_Opcode },
8656 { "kshiftl%BW", { MaskG, MaskR, Ib }, PREFIX_DATA },
8657 },
8658 {
8659 /* MOD_VEX_0F3A33_L_0 */
8660 { Bad_Opcode },
8661 { "kshiftl%DQ", { MaskG, MaskR, Ib }, PREFIX_DATA },
8662 },
8663 {
8664 /* MOD_VEX_0FXOP_09_12 */
8665 { Bad_Opcode },
8666 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_12_M_1) },
8667 },
8668
8669 #include "i386-dis-evex-mod.h"
8670 };
8671
8672 static const struct dis386 rm_table[][8] = {
8673 {
8674 /* RM_C6_REG_7 */
8675 { "xabort", { Skip_MODRM, Ib }, 0 },
8676 },
8677 {
8678 /* RM_C7_REG_7 */
8679 { "xbeginT", { Skip_MODRM, Jdqw }, 0 },
8680 },
8681 {
8682 /* RM_0F01_REG_0 */
8683 { "enclv", { Skip_MODRM }, 0 },
8684 { "vmcall", { Skip_MODRM }, 0 },
8685 { "vmlaunch", { Skip_MODRM }, 0 },
8686 { "vmresume", { Skip_MODRM }, 0 },
8687 { "vmxoff", { Skip_MODRM }, 0 },
8688 { "pconfig", { Skip_MODRM }, 0 },
8689 },
8690 {
8691 /* RM_0F01_REG_1 */
8692 { "monitor", { { OP_Monitor, 0 } }, 0 },
8693 { "mwait", { { OP_Mwait, 0 } }, 0 },
8694 { "clac", { Skip_MODRM }, 0 },
8695 { "stac", { Skip_MODRM }, 0 },
8696 { Bad_Opcode },
8697 { Bad_Opcode },
8698 { Bad_Opcode },
8699 { "encls", { Skip_MODRM }, 0 },
8700 },
8701 {
8702 /* RM_0F01_REG_2 */
8703 { "xgetbv", { Skip_MODRM }, 0 },
8704 { "xsetbv", { Skip_MODRM }, 0 },
8705 { Bad_Opcode },
8706 { Bad_Opcode },
8707 { "vmfunc", { Skip_MODRM }, 0 },
8708 { "xend", { Skip_MODRM }, 0 },
8709 { "xtest", { Skip_MODRM }, 0 },
8710 { "enclu", { Skip_MODRM }, 0 },
8711 },
8712 {
8713 /* RM_0F01_REG_3 */
8714 { "vmrun", { Skip_MODRM }, 0 },
8715 { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) },
8716 { "vmload", { Skip_MODRM }, 0 },
8717 { "vmsave", { Skip_MODRM }, 0 },
8718 { "stgi", { Skip_MODRM }, 0 },
8719 { "clgi", { Skip_MODRM }, 0 },
8720 { "skinit", { Skip_MODRM }, 0 },
8721 { "invlpga", { Skip_MODRM }, 0 },
8722 },
8723 {
8724 /* RM_0F01_REG_5_MOD_3 */
8725 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) },
8726 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) },
8727 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) },
8728 { Bad_Opcode },
8729 { Bad_Opcode },
8730 { Bad_Opcode },
8731 { "rdpkru", { Skip_MODRM }, 0 },
8732 { "wrpkru", { Skip_MODRM }, 0 },
8733 },
8734 {
8735 /* RM_0F01_REG_7_MOD_3 */
8736 { "swapgs", { Skip_MODRM }, 0 },
8737 { "rdtscp", { Skip_MODRM }, 0 },
8738 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) },
8739 { "mwaitx", { { OP_Mwait, eBX_reg } }, PREFIX_OPCODE },
8740 { "clzero", { Skip_MODRM }, 0 },
8741 { "rdpru", { Skip_MODRM }, 0 },
8742 },
8743 {
8744 /* RM_0F1E_P_1_MOD_3_REG_7 */
8745 { "nopQ", { Ev }, 0 },
8746 { "nopQ", { Ev }, 0 },
8747 { "endbr64", { Skip_MODRM }, PREFIX_OPCODE },
8748 { "endbr32", { Skip_MODRM }, PREFIX_OPCODE },
8749 { "nopQ", { Ev }, 0 },
8750 { "nopQ", { Ev }, 0 },
8751 { "nopQ", { Ev }, 0 },
8752 { "nopQ", { Ev }, 0 },
8753 },
8754 {
8755 /* RM_0FAE_REG_6_MOD_3 */
8756 { "mfence", { Skip_MODRM }, 0 },
8757 },
8758 {
8759 /* RM_0FAE_REG_7_MOD_3 */
8760 { "sfence", { Skip_MODRM }, 0 },
8761
8762 },
8763 {
8764 /* RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0 */
8765 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0) },
8766 },
8767 };
8768
8769 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
8770
8771 /* We use the high bit to indicate different name for the same
8772 prefix. */
8773 #define REP_PREFIX (0xf3 | 0x100)
8774 #define XACQUIRE_PREFIX (0xf2 | 0x200)
8775 #define XRELEASE_PREFIX (0xf3 | 0x400)
8776 #define BND_PREFIX (0xf2 | 0x400)
8777 #define NOTRACK_PREFIX (0x3e | 0x100)
8778
8779 /* Remember if the current op is a jump instruction. */
8780 static bfd_boolean op_is_jump = FALSE;
8781
8782 static int
8783 ckprefix (void)
8784 {
8785 int newrex, i, length;
8786 rex = 0;
8787 prefixes = 0;
8788 used_prefixes = 0;
8789 rex_used = 0;
8790 last_lock_prefix = -1;
8791 last_repz_prefix = -1;
8792 last_repnz_prefix = -1;
8793 last_data_prefix = -1;
8794 last_addr_prefix = -1;
8795 last_rex_prefix = -1;
8796 last_seg_prefix = -1;
8797 fwait_prefix = -1;
8798 active_seg_prefix = 0;
8799 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
8800 all_prefixes[i] = 0;
8801 i = 0;
8802 length = 0;
8803 /* The maximum instruction length is 15bytes. */
8804 while (length < MAX_CODE_LENGTH - 1)
8805 {
8806 FETCH_DATA (the_info, codep + 1);
8807 newrex = 0;
8808 switch (*codep)
8809 {
8810 /* REX prefixes family. */
8811 case 0x40:
8812 case 0x41:
8813 case 0x42:
8814 case 0x43:
8815 case 0x44:
8816 case 0x45:
8817 case 0x46:
8818 case 0x47:
8819 case 0x48:
8820 case 0x49:
8821 case 0x4a:
8822 case 0x4b:
8823 case 0x4c:
8824 case 0x4d:
8825 case 0x4e:
8826 case 0x4f:
8827 if (address_mode == mode_64bit)
8828 newrex = *codep;
8829 else
8830 return 1;
8831 last_rex_prefix = i;
8832 break;
8833 case 0xf3:
8834 prefixes |= PREFIX_REPZ;
8835 last_repz_prefix = i;
8836 break;
8837 case 0xf2:
8838 prefixes |= PREFIX_REPNZ;
8839 last_repnz_prefix = i;
8840 break;
8841 case 0xf0:
8842 prefixes |= PREFIX_LOCK;
8843 last_lock_prefix = i;
8844 break;
8845 case 0x2e:
8846 prefixes |= PREFIX_CS;
8847 last_seg_prefix = i;
8848 active_seg_prefix = PREFIX_CS;
8849 break;
8850 case 0x36:
8851 prefixes |= PREFIX_SS;
8852 last_seg_prefix = i;
8853 active_seg_prefix = PREFIX_SS;
8854 break;
8855 case 0x3e:
8856 prefixes |= PREFIX_DS;
8857 last_seg_prefix = i;
8858 active_seg_prefix = PREFIX_DS;
8859 break;
8860 case 0x26:
8861 prefixes |= PREFIX_ES;
8862 last_seg_prefix = i;
8863 active_seg_prefix = PREFIX_ES;
8864 break;
8865 case 0x64:
8866 prefixes |= PREFIX_FS;
8867 last_seg_prefix = i;
8868 active_seg_prefix = PREFIX_FS;
8869 break;
8870 case 0x65:
8871 prefixes |= PREFIX_GS;
8872 last_seg_prefix = i;
8873 active_seg_prefix = PREFIX_GS;
8874 break;
8875 case 0x66:
8876 prefixes |= PREFIX_DATA;
8877 last_data_prefix = i;
8878 break;
8879 case 0x67:
8880 prefixes |= PREFIX_ADDR;
8881 last_addr_prefix = i;
8882 break;
8883 case FWAIT_OPCODE:
8884 /* fwait is really an instruction. If there are prefixes
8885 before the fwait, they belong to the fwait, *not* to the
8886 following instruction. */
8887 fwait_prefix = i;
8888 if (prefixes || rex)
8889 {
8890 prefixes |= PREFIX_FWAIT;
8891 codep++;
8892 /* This ensures that the previous REX prefixes are noticed
8893 as unused prefixes, as in the return case below. */
8894 rex_used = rex;
8895 return 1;
8896 }
8897 prefixes = PREFIX_FWAIT;
8898 break;
8899 default:
8900 return 1;
8901 }
8902 /* Rex is ignored when followed by another prefix. */
8903 if (rex)
8904 {
8905 rex_used = rex;
8906 return 1;
8907 }
8908 if (*codep != FWAIT_OPCODE)
8909 all_prefixes[i++] = *codep;
8910 rex = newrex;
8911 codep++;
8912 length++;
8913 }
8914 return 0;
8915 }
8916
8917 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
8918 prefix byte. */
8919
8920 static const char *
8921 prefix_name (int pref, int sizeflag)
8922 {
8923 static const char *rexes [16] =
8924 {
8925 "rex", /* 0x40 */
8926 "rex.B", /* 0x41 */
8927 "rex.X", /* 0x42 */
8928 "rex.XB", /* 0x43 */
8929 "rex.R", /* 0x44 */
8930 "rex.RB", /* 0x45 */
8931 "rex.RX", /* 0x46 */
8932 "rex.RXB", /* 0x47 */
8933 "rex.W", /* 0x48 */
8934 "rex.WB", /* 0x49 */
8935 "rex.WX", /* 0x4a */
8936 "rex.WXB", /* 0x4b */
8937 "rex.WR", /* 0x4c */
8938 "rex.WRB", /* 0x4d */
8939 "rex.WRX", /* 0x4e */
8940 "rex.WRXB", /* 0x4f */
8941 };
8942
8943 switch (pref)
8944 {
8945 /* REX prefixes family. */
8946 case 0x40:
8947 case 0x41:
8948 case 0x42:
8949 case 0x43:
8950 case 0x44:
8951 case 0x45:
8952 case 0x46:
8953 case 0x47:
8954 case 0x48:
8955 case 0x49:
8956 case 0x4a:
8957 case 0x4b:
8958 case 0x4c:
8959 case 0x4d:
8960 case 0x4e:
8961 case 0x4f:
8962 return rexes [pref - 0x40];
8963 case 0xf3:
8964 return "repz";
8965 case 0xf2:
8966 return "repnz";
8967 case 0xf0:
8968 return "lock";
8969 case 0x2e:
8970 return "cs";
8971 case 0x36:
8972 return "ss";
8973 case 0x3e:
8974 return "ds";
8975 case 0x26:
8976 return "es";
8977 case 0x64:
8978 return "fs";
8979 case 0x65:
8980 return "gs";
8981 case 0x66:
8982 return (sizeflag & DFLAG) ? "data16" : "data32";
8983 case 0x67:
8984 if (address_mode == mode_64bit)
8985 return (sizeflag & AFLAG) ? "addr32" : "addr64";
8986 else
8987 return (sizeflag & AFLAG) ? "addr16" : "addr32";
8988 case FWAIT_OPCODE:
8989 return "fwait";
8990 case REP_PREFIX:
8991 return "rep";
8992 case XACQUIRE_PREFIX:
8993 return "xacquire";
8994 case XRELEASE_PREFIX:
8995 return "xrelease";
8996 case BND_PREFIX:
8997 return "bnd";
8998 case NOTRACK_PREFIX:
8999 return "notrack";
9000 default:
9001 return NULL;
9002 }
9003 }
9004
9005 static char op_out[MAX_OPERANDS][100];
9006 static int op_ad, op_index[MAX_OPERANDS];
9007 static int two_source_ops;
9008 static bfd_vma op_address[MAX_OPERANDS];
9009 static bfd_vma op_riprel[MAX_OPERANDS];
9010 static bfd_vma start_pc;
9011
9012 /*
9013 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
9014 * (see topic "Redundant prefixes" in the "Differences from 8086"
9015 * section of the "Virtual 8086 Mode" chapter.)
9016 * 'pc' should be the address of this instruction, it will
9017 * be used to print the target address if this is a relative jump or call
9018 * The function returns the length of this instruction in bytes.
9019 */
9020
9021 static char intel_syntax;
9022 static char intel_mnemonic = !SYSV386_COMPAT;
9023 static char open_char;
9024 static char close_char;
9025 static char separator_char;
9026 static char scale_char;
9027
9028 enum x86_64_isa
9029 {
9030 amd64 = 1,
9031 intel64
9032 };
9033
9034 static enum x86_64_isa isa64;
9035
9036 /* Here for backwards compatibility. When gdb stops using
9037 print_insn_i386_att and print_insn_i386_intel these functions can
9038 disappear, and print_insn_i386 be merged into print_insn. */
9039 int
9040 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
9041 {
9042 intel_syntax = 0;
9043
9044 return print_insn (pc, info);
9045 }
9046
9047 int
9048 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
9049 {
9050 intel_syntax = 1;
9051
9052 return print_insn (pc, info);
9053 }
9054
9055 int
9056 print_insn_i386 (bfd_vma pc, disassemble_info *info)
9057 {
9058 intel_syntax = -1;
9059
9060 return print_insn (pc, info);
9061 }
9062
9063 void
9064 print_i386_disassembler_options (FILE *stream)
9065 {
9066 fprintf (stream, _("\n\
9067 The following i386/x86-64 specific disassembler options are supported for use\n\
9068 with the -M switch (multiple options should be separated by commas):\n"));
9069
9070 fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n"));
9071 fprintf (stream, _(" i386 Disassemble in 32bit mode\n"));
9072 fprintf (stream, _(" i8086 Disassemble in 16bit mode\n"));
9073 fprintf (stream, _(" att Display instruction in AT&T syntax\n"));
9074 fprintf (stream, _(" intel Display instruction in Intel syntax\n"));
9075 fprintf (stream, _(" att-mnemonic\n"
9076 " Display instruction in AT&T mnemonic\n"));
9077 fprintf (stream, _(" intel-mnemonic\n"
9078 " Display instruction in Intel mnemonic\n"));
9079 fprintf (stream, _(" addr64 Assume 64bit address size\n"));
9080 fprintf (stream, _(" addr32 Assume 32bit address size\n"));
9081 fprintf (stream, _(" addr16 Assume 16bit address size\n"));
9082 fprintf (stream, _(" data32 Assume 32bit data size\n"));
9083 fprintf (stream, _(" data16 Assume 16bit data size\n"));
9084 fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n"));
9085 fprintf (stream, _(" amd64 Display instruction in AMD64 ISA\n"));
9086 fprintf (stream, _(" intel64 Display instruction in Intel64 ISA\n"));
9087 }
9088
9089 /* Bad opcode. */
9090 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
9091
9092 /* Get a pointer to struct dis386 with a valid name. */
9093
9094 static const struct dis386 *
9095 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
9096 {
9097 int vindex, vex_table_index;
9098
9099 if (dp->name != NULL)
9100 return dp;
9101
9102 switch (dp->op[0].bytemode)
9103 {
9104 case USE_REG_TABLE:
9105 dp = &reg_table[dp->op[1].bytemode][modrm.reg];
9106 break;
9107
9108 case USE_MOD_TABLE:
9109 vindex = modrm.mod == 0x3 ? 1 : 0;
9110 dp = &mod_table[dp->op[1].bytemode][vindex];
9111 break;
9112
9113 case USE_RM_TABLE:
9114 dp = &rm_table[dp->op[1].bytemode][modrm.rm];
9115 break;
9116
9117 case USE_PREFIX_TABLE:
9118 if (need_vex)
9119 {
9120 /* The prefix in VEX is implicit. */
9121 switch (vex.prefix)
9122 {
9123 case 0:
9124 vindex = 0;
9125 break;
9126 case REPE_PREFIX_OPCODE:
9127 vindex = 1;
9128 break;
9129 case DATA_PREFIX_OPCODE:
9130 vindex = 2;
9131 break;
9132 case REPNE_PREFIX_OPCODE:
9133 vindex = 3;
9134 break;
9135 default:
9136 abort ();
9137 break;
9138 }
9139 }
9140 else
9141 {
9142 int last_prefix = -1;
9143 int prefix = 0;
9144 vindex = 0;
9145 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
9146 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
9147 last one wins. */
9148 if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
9149 {
9150 if (last_repz_prefix > last_repnz_prefix)
9151 {
9152 vindex = 1;
9153 prefix = PREFIX_REPZ;
9154 last_prefix = last_repz_prefix;
9155 }
9156 else
9157 {
9158 vindex = 3;
9159 prefix = PREFIX_REPNZ;
9160 last_prefix = last_repnz_prefix;
9161 }
9162
9163 /* Check if prefix should be ignored. */
9164 if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
9165 & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
9166 & prefix) != 0)
9167 vindex = 0;
9168 }
9169
9170 if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
9171 {
9172 vindex = 2;
9173 prefix = PREFIX_DATA;
9174 last_prefix = last_data_prefix;
9175 }
9176
9177 if (vindex != 0)
9178 {
9179 used_prefixes |= prefix;
9180 all_prefixes[last_prefix] = 0;
9181 }
9182 }
9183 dp = &prefix_table[dp->op[1].bytemode][vindex];
9184 break;
9185
9186 case USE_X86_64_TABLE:
9187 vindex = address_mode == mode_64bit ? 1 : 0;
9188 dp = &x86_64_table[dp->op[1].bytemode][vindex];
9189 break;
9190
9191 case USE_3BYTE_TABLE:
9192 FETCH_DATA (info, codep + 2);
9193 vindex = *codep++;
9194 dp = &three_byte_table[dp->op[1].bytemode][vindex];
9195 end_codep = codep;
9196 modrm.mod = (*codep >> 6) & 3;
9197 modrm.reg = (*codep >> 3) & 7;
9198 modrm.rm = *codep & 7;
9199 break;
9200
9201 case USE_VEX_LEN_TABLE:
9202 if (!need_vex)
9203 abort ();
9204
9205 switch (vex.length)
9206 {
9207 case 128:
9208 vindex = 0;
9209 break;
9210 case 256:
9211 vindex = 1;
9212 break;
9213 default:
9214 abort ();
9215 break;
9216 }
9217
9218 dp = &vex_len_table[dp->op[1].bytemode][vindex];
9219 break;
9220
9221 case USE_EVEX_LEN_TABLE:
9222 if (!vex.evex)
9223 abort ();
9224
9225 switch (vex.length)
9226 {
9227 case 128:
9228 vindex = 0;
9229 break;
9230 case 256:
9231 vindex = 1;
9232 break;
9233 case 512:
9234 vindex = 2;
9235 break;
9236 default:
9237 abort ();
9238 break;
9239 }
9240
9241 dp = &evex_len_table[dp->op[1].bytemode][vindex];
9242 break;
9243
9244 case USE_XOP_8F_TABLE:
9245 FETCH_DATA (info, codep + 3);
9246 rex = ~(*codep >> 5) & 0x7;
9247
9248 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
9249 switch ((*codep & 0x1f))
9250 {
9251 default:
9252 dp = &bad_opcode;
9253 return dp;
9254 case 0x8:
9255 vex_table_index = XOP_08;
9256 break;
9257 case 0x9:
9258 vex_table_index = XOP_09;
9259 break;
9260 case 0xa:
9261 vex_table_index = XOP_0A;
9262 break;
9263 }
9264 codep++;
9265 vex.w = *codep & 0x80;
9266 if (vex.w && address_mode == mode_64bit)
9267 rex |= REX_W;
9268
9269 vex.register_specifier = (~(*codep >> 3)) & 0xf;
9270 if (address_mode != mode_64bit)
9271 {
9272 /* In 16/32-bit mode REX_B is silently ignored. */
9273 rex &= ~REX_B;
9274 }
9275
9276 vex.length = (*codep & 0x4) ? 256 : 128;
9277 switch ((*codep & 0x3))
9278 {
9279 case 0:
9280 break;
9281 case 1:
9282 vex.prefix = DATA_PREFIX_OPCODE;
9283 break;
9284 case 2:
9285 vex.prefix = REPE_PREFIX_OPCODE;
9286 break;
9287 case 3:
9288 vex.prefix = REPNE_PREFIX_OPCODE;
9289 break;
9290 }
9291 need_vex = 1;
9292 codep++;
9293 vindex = *codep++;
9294 dp = &xop_table[vex_table_index][vindex];
9295
9296 end_codep = codep;
9297 FETCH_DATA (info, codep + 1);
9298 modrm.mod = (*codep >> 6) & 3;
9299 modrm.reg = (*codep >> 3) & 7;
9300 modrm.rm = *codep & 7;
9301
9302 /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid
9303 having to decode the bits for every otherwise valid encoding. */
9304 if (vex.prefix)
9305 return &bad_opcode;
9306 break;
9307
9308 case USE_VEX_C4_TABLE:
9309 /* VEX prefix. */
9310 FETCH_DATA (info, codep + 3);
9311 rex = ~(*codep >> 5) & 0x7;
9312 switch ((*codep & 0x1f))
9313 {
9314 default:
9315 dp = &bad_opcode;
9316 return dp;
9317 case 0x1:
9318 vex_table_index = VEX_0F;
9319 break;
9320 case 0x2:
9321 vex_table_index = VEX_0F38;
9322 break;
9323 case 0x3:
9324 vex_table_index = VEX_0F3A;
9325 break;
9326 }
9327 codep++;
9328 vex.w = *codep & 0x80;
9329 if (address_mode == mode_64bit)
9330 {
9331 if (vex.w)
9332 rex |= REX_W;
9333 }
9334 else
9335 {
9336 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
9337 is ignored, other REX bits are 0 and the highest bit in
9338 VEX.vvvv is also ignored (but we mustn't clear it here). */
9339 rex = 0;
9340 }
9341 vex.register_specifier = (~(*codep >> 3)) & 0xf;
9342 vex.length = (*codep & 0x4) ? 256 : 128;
9343 switch ((*codep & 0x3))
9344 {
9345 case 0:
9346 break;
9347 case 1:
9348 vex.prefix = DATA_PREFIX_OPCODE;
9349 break;
9350 case 2:
9351 vex.prefix = REPE_PREFIX_OPCODE;
9352 break;
9353 case 3:
9354 vex.prefix = REPNE_PREFIX_OPCODE;
9355 break;
9356 }
9357 need_vex = 1;
9358 codep++;
9359 vindex = *codep++;
9360 dp = &vex_table[vex_table_index][vindex];
9361 end_codep = codep;
9362 /* There is no MODRM byte for VEX0F 77. */
9363 if (vex_table_index != VEX_0F || vindex != 0x77)
9364 {
9365 FETCH_DATA (info, codep + 1);
9366 modrm.mod = (*codep >> 6) & 3;
9367 modrm.reg = (*codep >> 3) & 7;
9368 modrm.rm = *codep & 7;
9369 }
9370 break;
9371
9372 case USE_VEX_C5_TABLE:
9373 /* VEX prefix. */
9374 FETCH_DATA (info, codep + 2);
9375 rex = (*codep & 0x80) ? 0 : REX_R;
9376
9377 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
9378 VEX.vvvv is 1. */
9379 vex.register_specifier = (~(*codep >> 3)) & 0xf;
9380 vex.length = (*codep & 0x4) ? 256 : 128;
9381 switch ((*codep & 0x3))
9382 {
9383 case 0:
9384 break;
9385 case 1:
9386 vex.prefix = DATA_PREFIX_OPCODE;
9387 break;
9388 case 2:
9389 vex.prefix = REPE_PREFIX_OPCODE;
9390 break;
9391 case 3:
9392 vex.prefix = REPNE_PREFIX_OPCODE;
9393 break;
9394 }
9395 need_vex = 1;
9396 codep++;
9397 vindex = *codep++;
9398 dp = &vex_table[dp->op[1].bytemode][vindex];
9399 end_codep = codep;
9400 /* There is no MODRM byte for VEX 77. */
9401 if (vindex != 0x77)
9402 {
9403 FETCH_DATA (info, codep + 1);
9404 modrm.mod = (*codep >> 6) & 3;
9405 modrm.reg = (*codep >> 3) & 7;
9406 modrm.rm = *codep & 7;
9407 }
9408 break;
9409
9410 case USE_VEX_W_TABLE:
9411 if (!need_vex)
9412 abort ();
9413
9414 dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
9415 break;
9416
9417 case USE_EVEX_TABLE:
9418 two_source_ops = 0;
9419 /* EVEX prefix. */
9420 vex.evex = 1;
9421 FETCH_DATA (info, codep + 4);
9422 /* The first byte after 0x62. */
9423 rex = ~(*codep >> 5) & 0x7;
9424 vex.r = *codep & 0x10;
9425 switch ((*codep & 0xf))
9426 {
9427 default:
9428 return &bad_opcode;
9429 case 0x1:
9430 vex_table_index = EVEX_0F;
9431 break;
9432 case 0x2:
9433 vex_table_index = EVEX_0F38;
9434 break;
9435 case 0x3:
9436 vex_table_index = EVEX_0F3A;
9437 break;
9438 }
9439
9440 /* The second byte after 0x62. */
9441 codep++;
9442 vex.w = *codep & 0x80;
9443 if (vex.w && address_mode == mode_64bit)
9444 rex |= REX_W;
9445
9446 vex.register_specifier = (~(*codep >> 3)) & 0xf;
9447
9448 /* The U bit. */
9449 if (!(*codep & 0x4))
9450 return &bad_opcode;
9451
9452 switch ((*codep & 0x3))
9453 {
9454 case 0:
9455 break;
9456 case 1:
9457 vex.prefix = DATA_PREFIX_OPCODE;
9458 break;
9459 case 2:
9460 vex.prefix = REPE_PREFIX_OPCODE;
9461 break;
9462 case 3:
9463 vex.prefix = REPNE_PREFIX_OPCODE;
9464 break;
9465 }
9466
9467 /* The third byte after 0x62. */
9468 codep++;
9469
9470 /* Remember the static rounding bits. */
9471 vex.ll = (*codep >> 5) & 3;
9472 vex.b = (*codep & 0x10) != 0;
9473
9474 vex.v = *codep & 0x8;
9475 vex.mask_register_specifier = *codep & 0x7;
9476 vex.zeroing = *codep & 0x80;
9477
9478 if (address_mode != mode_64bit)
9479 {
9480 /* In 16/32-bit mode silently ignore following bits. */
9481 rex &= ~REX_B;
9482 vex.r = 1;
9483 vex.v = 1;
9484 }
9485
9486 need_vex = 1;
9487 codep++;
9488 vindex = *codep++;
9489 dp = &evex_table[vex_table_index][vindex];
9490 end_codep = codep;
9491 FETCH_DATA (info, codep + 1);
9492 modrm.mod = (*codep >> 6) & 3;
9493 modrm.reg = (*codep >> 3) & 7;
9494 modrm.rm = *codep & 7;
9495
9496 /* Set vector length. */
9497 if (modrm.mod == 3 && vex.b)
9498 vex.length = 512;
9499 else
9500 {
9501 switch (vex.ll)
9502 {
9503 case 0x0:
9504 vex.length = 128;
9505 break;
9506 case 0x1:
9507 vex.length = 256;
9508 break;
9509 case 0x2:
9510 vex.length = 512;
9511 break;
9512 default:
9513 return &bad_opcode;
9514 }
9515 }
9516 break;
9517
9518 case 0:
9519 dp = &bad_opcode;
9520 break;
9521
9522 default:
9523 abort ();
9524 }
9525
9526 if (dp->name != NULL)
9527 return dp;
9528 else
9529 return get_valid_dis386 (dp, info);
9530 }
9531
9532 static void
9533 get_sib (disassemble_info *info, int sizeflag)
9534 {
9535 /* If modrm.mod == 3, operand must be register. */
9536 if (need_modrm
9537 && ((sizeflag & AFLAG) || address_mode == mode_64bit)
9538 && modrm.mod != 3
9539 && modrm.rm == 4)
9540 {
9541 FETCH_DATA (info, codep + 2);
9542 sib.index = (codep [1] >> 3) & 7;
9543 sib.scale = (codep [1] >> 6) & 3;
9544 sib.base = codep [1] & 7;
9545 }
9546 }
9547
9548 static int
9549 print_insn (bfd_vma pc, disassemble_info *info)
9550 {
9551 const struct dis386 *dp;
9552 int i;
9553 char *op_txt[MAX_OPERANDS];
9554 int needcomma;
9555 int sizeflag, orig_sizeflag;
9556 const char *p;
9557 struct dis_private priv;
9558 int prefix_length;
9559
9560 priv.orig_sizeflag = AFLAG | DFLAG;
9561 if ((info->mach & bfd_mach_i386_i386) != 0)
9562 address_mode = mode_32bit;
9563 else if (info->mach == bfd_mach_i386_i8086)
9564 {
9565 address_mode = mode_16bit;
9566 priv.orig_sizeflag = 0;
9567 }
9568 else
9569 address_mode = mode_64bit;
9570
9571 if (intel_syntax == (char) -1)
9572 intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
9573
9574 for (p = info->disassembler_options; p != NULL; )
9575 {
9576 if (CONST_STRNEQ (p, "amd64"))
9577 isa64 = amd64;
9578 else if (CONST_STRNEQ (p, "intel64"))
9579 isa64 = intel64;
9580 else if (CONST_STRNEQ (p, "x86-64"))
9581 {
9582 address_mode = mode_64bit;
9583 priv.orig_sizeflag |= AFLAG | DFLAG;
9584 }
9585 else if (CONST_STRNEQ (p, "i386"))
9586 {
9587 address_mode = mode_32bit;
9588 priv.orig_sizeflag |= AFLAG | DFLAG;
9589 }
9590 else if (CONST_STRNEQ (p, "i8086"))
9591 {
9592 address_mode = mode_16bit;
9593 priv.orig_sizeflag &= ~(AFLAG | DFLAG);
9594 }
9595 else if (CONST_STRNEQ (p, "intel"))
9596 {
9597 intel_syntax = 1;
9598 if (CONST_STRNEQ (p + 5, "-mnemonic"))
9599 intel_mnemonic = 1;
9600 }
9601 else if (CONST_STRNEQ (p, "att"))
9602 {
9603 intel_syntax = 0;
9604 if (CONST_STRNEQ (p + 3, "-mnemonic"))
9605 intel_mnemonic = 0;
9606 }
9607 else if (CONST_STRNEQ (p, "addr"))
9608 {
9609 if (address_mode == mode_64bit)
9610 {
9611 if (p[4] == '3' && p[5] == '2')
9612 priv.orig_sizeflag &= ~AFLAG;
9613 else if (p[4] == '6' && p[5] == '4')
9614 priv.orig_sizeflag |= AFLAG;
9615 }
9616 else
9617 {
9618 if (p[4] == '1' && p[5] == '6')
9619 priv.orig_sizeflag &= ~AFLAG;
9620 else if (p[4] == '3' && p[5] == '2')
9621 priv.orig_sizeflag |= AFLAG;
9622 }
9623 }
9624 else if (CONST_STRNEQ (p, "data"))
9625 {
9626 if (p[4] == '1' && p[5] == '6')
9627 priv.orig_sizeflag &= ~DFLAG;
9628 else if (p[4] == '3' && p[5] == '2')
9629 priv.orig_sizeflag |= DFLAG;
9630 }
9631 else if (CONST_STRNEQ (p, "suffix"))
9632 priv.orig_sizeflag |= SUFFIX_ALWAYS;
9633
9634 p = strchr (p, ',');
9635 if (p != NULL)
9636 p++;
9637 }
9638
9639 if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
9640 {
9641 (*info->fprintf_func) (info->stream,
9642 _("64-bit address is disabled"));
9643 return -1;
9644 }
9645
9646 if (intel_syntax)
9647 {
9648 names64 = intel_names64;
9649 names32 = intel_names32;
9650 names16 = intel_names16;
9651 names8 = intel_names8;
9652 names8rex = intel_names8rex;
9653 names_seg = intel_names_seg;
9654 names_mm = intel_names_mm;
9655 names_bnd = intel_names_bnd;
9656 names_xmm = intel_names_xmm;
9657 names_ymm = intel_names_ymm;
9658 names_zmm = intel_names_zmm;
9659 names_tmm = intel_names_tmm;
9660 index64 = intel_index64;
9661 index32 = intel_index32;
9662 names_mask = intel_names_mask;
9663 index16 = intel_index16;
9664 open_char = '[';
9665 close_char = ']';
9666 separator_char = '+';
9667 scale_char = '*';
9668 }
9669 else
9670 {
9671 names64 = att_names64;
9672 names32 = att_names32;
9673 names16 = att_names16;
9674 names8 = att_names8;
9675 names8rex = att_names8rex;
9676 names_seg = att_names_seg;
9677 names_mm = att_names_mm;
9678 names_bnd = att_names_bnd;
9679 names_xmm = att_names_xmm;
9680 names_ymm = att_names_ymm;
9681 names_zmm = att_names_zmm;
9682 names_tmm = att_names_tmm;
9683 index64 = att_index64;
9684 index32 = att_index32;
9685 names_mask = att_names_mask;
9686 index16 = att_index16;
9687 open_char = '(';
9688 close_char = ')';
9689 separator_char = ',';
9690 scale_char = ',';
9691 }
9692
9693 /* The output looks better if we put 7 bytes on a line, since that
9694 puts most long word instructions on a single line. Use 8 bytes
9695 for Intel L1OM. */
9696 if ((info->mach & bfd_mach_l1om) != 0)
9697 info->bytes_per_line = 8;
9698 else
9699 info->bytes_per_line = 7;
9700
9701 info->private_data = &priv;
9702 priv.max_fetched = priv.the_buffer;
9703 priv.insn_start = pc;
9704
9705 obuf[0] = 0;
9706 for (i = 0; i < MAX_OPERANDS; ++i)
9707 {
9708 op_out[i][0] = 0;
9709 op_index[i] = -1;
9710 }
9711
9712 the_info = info;
9713 start_pc = pc;
9714 start_codep = priv.the_buffer;
9715 codep = priv.the_buffer;
9716
9717 if (OPCODES_SIGSETJMP (priv.bailout) != 0)
9718 {
9719 const char *name;
9720
9721 /* Getting here means we tried for data but didn't get it. That
9722 means we have an incomplete instruction of some sort. Just
9723 print the first byte as a prefix or a .byte pseudo-op. */
9724 if (codep > priv.the_buffer)
9725 {
9726 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
9727 if (name != NULL)
9728 (*info->fprintf_func) (info->stream, "%s", name);
9729 else
9730 {
9731 /* Just print the first byte as a .byte instruction. */
9732 (*info->fprintf_func) (info->stream, ".byte 0x%x",
9733 (unsigned int) priv.the_buffer[0]);
9734 }
9735
9736 return 1;
9737 }
9738
9739 return -1;
9740 }
9741
9742 obufp = obuf;
9743 sizeflag = priv.orig_sizeflag;
9744
9745 if (!ckprefix () || rex_used)
9746 {
9747 /* Too many prefixes or unused REX prefixes. */
9748 for (i = 0;
9749 i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
9750 i++)
9751 (*info->fprintf_func) (info->stream, "%s%s",
9752 i == 0 ? "" : " ",
9753 prefix_name (all_prefixes[i], sizeflag));
9754 return i;
9755 }
9756
9757 insn_codep = codep;
9758
9759 FETCH_DATA (info, codep + 1);
9760 two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
9761
9762 if (((prefixes & PREFIX_FWAIT)
9763 && ((*codep < 0xd8) || (*codep > 0xdf))))
9764 {
9765 /* Handle prefixes before fwait. */
9766 for (i = 0; i < fwait_prefix && all_prefixes[i];
9767 i++)
9768 (*info->fprintf_func) (info->stream, "%s ",
9769 prefix_name (all_prefixes[i], sizeflag));
9770 (*info->fprintf_func) (info->stream, "fwait");
9771 return i + 1;
9772 }
9773
9774 if (*codep == 0x0f)
9775 {
9776 unsigned char threebyte;
9777
9778 codep++;
9779 FETCH_DATA (info, codep + 1);
9780 threebyte = *codep;
9781 dp = &dis386_twobyte[threebyte];
9782 need_modrm = twobyte_has_modrm[*codep];
9783 codep++;
9784 }
9785 else
9786 {
9787 dp = &dis386[*codep];
9788 need_modrm = onebyte_has_modrm[*codep];
9789 codep++;
9790 }
9791
9792 /* Save sizeflag for printing the extra prefixes later before updating
9793 it for mnemonic and operand processing. The prefix names depend
9794 only on the address mode. */
9795 orig_sizeflag = sizeflag;
9796 if (prefixes & PREFIX_ADDR)
9797 sizeflag ^= AFLAG;
9798 if ((prefixes & PREFIX_DATA))
9799 sizeflag ^= DFLAG;
9800
9801 end_codep = codep;
9802 if (need_modrm)
9803 {
9804 FETCH_DATA (info, codep + 1);
9805 modrm.mod = (*codep >> 6) & 3;
9806 modrm.reg = (*codep >> 3) & 7;
9807 modrm.rm = *codep & 7;
9808 }
9809
9810 need_vex = 0;
9811 memset (&vex, 0, sizeof (vex));
9812
9813 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
9814 {
9815 get_sib (info, sizeflag);
9816 dofloat (sizeflag);
9817 }
9818 else
9819 {
9820 dp = get_valid_dis386 (dp, info);
9821 if (dp != NULL && putop (dp->name, sizeflag) == 0)
9822 {
9823 get_sib (info, sizeflag);
9824 for (i = 0; i < MAX_OPERANDS; ++i)
9825 {
9826 obufp = op_out[i];
9827 op_ad = MAX_OPERANDS - 1 - i;
9828 if (dp->op[i].rtn)
9829 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
9830 /* For EVEX instruction after the last operand masking
9831 should be printed. */
9832 if (i == 0 && vex.evex)
9833 {
9834 /* Don't print {%k0}. */
9835 if (vex.mask_register_specifier)
9836 {
9837 oappend ("{");
9838 oappend (names_mask[vex.mask_register_specifier]);
9839 oappend ("}");
9840 }
9841 if (vex.zeroing)
9842 oappend ("{z}");
9843 }
9844 }
9845 }
9846 }
9847
9848 /* Clear instruction information. */
9849 if (the_info)
9850 {
9851 the_info->insn_info_valid = 0;
9852 the_info->branch_delay_insns = 0;
9853 the_info->data_size = 0;
9854 the_info->insn_type = dis_noninsn;
9855 the_info->target = 0;
9856 the_info->target2 = 0;
9857 }
9858
9859 /* Reset jump operation indicator. */
9860 op_is_jump = FALSE;
9861
9862 {
9863 int jump_detection = 0;
9864
9865 /* Extract flags. */
9866 for (i = 0; i < MAX_OPERANDS; ++i)
9867 {
9868 if ((dp->op[i].rtn == OP_J)
9869 || (dp->op[i].rtn == OP_indirE))
9870 jump_detection |= 1;
9871 else if ((dp->op[i].rtn == BND_Fixup)
9872 || (!dp->op[i].rtn && !dp->op[i].bytemode))
9873 jump_detection |= 2;
9874 else if ((dp->op[i].bytemode == cond_jump_mode)
9875 || (dp->op[i].bytemode == loop_jcxz_mode))
9876 jump_detection |= 4;
9877 }
9878
9879 /* Determine if this is a jump or branch. */
9880 if ((jump_detection & 0x3) == 0x3)
9881 {
9882 op_is_jump = TRUE;
9883 if (jump_detection & 0x4)
9884 the_info->insn_type = dis_condbranch;
9885 else
9886 the_info->insn_type =
9887 (dp->name && !strncmp(dp->name, "call", 4))
9888 ? dis_jsr : dis_branch;
9889 }
9890 }
9891
9892 /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
9893 are all 0s in inverted form. */
9894 if (need_vex && vex.register_specifier != 0)
9895 {
9896 (*info->fprintf_func) (info->stream, "(bad)");
9897 return end_codep - priv.the_buffer;
9898 }
9899
9900 switch (dp->prefix_requirement)
9901 {
9902 case PREFIX_DATA:
9903 /* If only the data prefix is marked as mandatory, its absence renders
9904 the encoding invalid. Most other PREFIX_OPCODE rules still apply. */
9905 if (need_vex ? !vex.prefix : !(prefixes & PREFIX_DATA))
9906 {
9907 (*info->fprintf_func) (info->stream, "(bad)");
9908 return end_codep - priv.the_buffer;
9909 }
9910 used_prefixes |= PREFIX_DATA;
9911 /* Fall through. */
9912 case PREFIX_OPCODE:
9913 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
9914 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
9915 used by putop and MMX/SSE operand and may be overridden by the
9916 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
9917 separately. */
9918 if (((need_vex
9919 ? vex.prefix == REPE_PREFIX_OPCODE
9920 || vex.prefix == REPNE_PREFIX_OPCODE
9921 : (prefixes
9922 & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
9923 && (used_prefixes
9924 & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
9925 || (((need_vex
9926 ? vex.prefix == DATA_PREFIX_OPCODE
9927 : ((prefixes
9928 & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
9929 == PREFIX_DATA))
9930 && (used_prefixes & PREFIX_DATA) == 0))
9931 || (vex.evex && dp->prefix_requirement != PREFIX_DATA
9932 && !vex.w != !(used_prefixes & PREFIX_DATA)))
9933 {
9934 (*info->fprintf_func) (info->stream, "(bad)");
9935 return end_codep - priv.the_buffer;
9936 }
9937 break;
9938 }
9939
9940 /* Check if the REX prefix is used. */
9941 if ((rex ^ rex_used) == 0 && !need_vex && last_rex_prefix >= 0)
9942 all_prefixes[last_rex_prefix] = 0;
9943
9944 /* Check if the SEG prefix is used. */
9945 if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
9946 | PREFIX_FS | PREFIX_GS)) != 0
9947 && (used_prefixes & active_seg_prefix) != 0)
9948 all_prefixes[last_seg_prefix] = 0;
9949
9950 /* Check if the ADDR prefix is used. */
9951 if ((prefixes & PREFIX_ADDR) != 0
9952 && (used_prefixes & PREFIX_ADDR) != 0)
9953 all_prefixes[last_addr_prefix] = 0;
9954
9955 /* Check if the DATA prefix is used. */
9956 if ((prefixes & PREFIX_DATA) != 0
9957 && (used_prefixes & PREFIX_DATA) != 0
9958 && !need_vex)
9959 all_prefixes[last_data_prefix] = 0;
9960
9961 /* Print the extra prefixes. */
9962 prefix_length = 0;
9963 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
9964 if (all_prefixes[i])
9965 {
9966 const char *name;
9967 name = prefix_name (all_prefixes[i], orig_sizeflag);
9968 if (name == NULL)
9969 abort ();
9970 prefix_length += strlen (name) + 1;
9971 (*info->fprintf_func) (info->stream, "%s ", name);
9972 }
9973
9974 /* Check maximum code length. */
9975 if ((codep - start_codep) > MAX_CODE_LENGTH)
9976 {
9977 (*info->fprintf_func) (info->stream, "(bad)");
9978 return MAX_CODE_LENGTH;
9979 }
9980
9981 obufp = mnemonicendp;
9982 for (i = strlen (obuf) + prefix_length; i < 6; i++)
9983 oappend (" ");
9984 oappend (" ");
9985 (*info->fprintf_func) (info->stream, "%s", obuf);
9986
9987 /* The enter and bound instructions are printed with operands in the same
9988 order as the intel book; everything else is printed in reverse order. */
9989 if (intel_syntax || two_source_ops)
9990 {
9991 bfd_vma riprel;
9992
9993 for (i = 0; i < MAX_OPERANDS; ++i)
9994 op_txt[i] = op_out[i];
9995
9996 if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
9997 && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
9998 {
9999 op_txt[2] = op_out[3];
10000 op_txt[3] = op_out[2];
10001 }
10002
10003 for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
10004 {
10005 op_ad = op_index[i];
10006 op_index[i] = op_index[MAX_OPERANDS - 1 - i];
10007 op_index[MAX_OPERANDS - 1 - i] = op_ad;
10008 riprel = op_riprel[i];
10009 op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
10010 op_riprel[MAX_OPERANDS - 1 - i] = riprel;
10011 }
10012 }
10013 else
10014 {
10015 for (i = 0; i < MAX_OPERANDS; ++i)
10016 op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
10017 }
10018
10019 needcomma = 0;
10020 for (i = 0; i < MAX_OPERANDS; ++i)
10021 if (*op_txt[i])
10022 {
10023 if (needcomma)
10024 (*info->fprintf_func) (info->stream, ",");
10025 if (op_index[i] != -1 && !op_riprel[i])
10026 {
10027 bfd_vma target = (bfd_vma) op_address[op_index[i]];
10028
10029 if (the_info && op_is_jump)
10030 {
10031 the_info->insn_info_valid = 1;
10032 the_info->branch_delay_insns = 0;
10033 the_info->data_size = 0;
10034 the_info->target = target;
10035 the_info->target2 = 0;
10036 }
10037 (*info->print_address_func) (target, info);
10038 }
10039 else
10040 (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
10041 needcomma = 1;
10042 }
10043
10044 for (i = 0; i < MAX_OPERANDS; i++)
10045 if (op_index[i] != -1 && op_riprel[i])
10046 {
10047 (*info->fprintf_func) (info->stream, " # ");
10048 (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
10049 + op_address[op_index[i]]), info);
10050 break;
10051 }
10052 return codep - priv.the_buffer;
10053 }
10054
10055 static const char *float_mem[] = {
10056 /* d8 */
10057 "fadd{s|}",
10058 "fmul{s|}",
10059 "fcom{s|}",
10060 "fcomp{s|}",
10061 "fsub{s|}",
10062 "fsubr{s|}",
10063 "fdiv{s|}",
10064 "fdivr{s|}",
10065 /* d9 */
10066 "fld{s|}",
10067 "(bad)",
10068 "fst{s|}",
10069 "fstp{s|}",
10070 "fldenv{C|C}",
10071 "fldcw",
10072 "fNstenv{C|C}",
10073 "fNstcw",
10074 /* da */
10075 "fiadd{l|}",
10076 "fimul{l|}",
10077 "ficom{l|}",
10078 "ficomp{l|}",
10079 "fisub{l|}",
10080 "fisubr{l|}",
10081 "fidiv{l|}",
10082 "fidivr{l|}",
10083 /* db */
10084 "fild{l|}",
10085 "fisttp{l|}",
10086 "fist{l|}",
10087 "fistp{l|}",
10088 "(bad)",
10089 "fld{t|}",
10090 "(bad)",
10091 "fstp{t|}",
10092 /* dc */
10093 "fadd{l|}",
10094 "fmul{l|}",
10095 "fcom{l|}",
10096 "fcomp{l|}",
10097 "fsub{l|}",
10098 "fsubr{l|}",
10099 "fdiv{l|}",
10100 "fdivr{l|}",
10101 /* dd */
10102 "fld{l|}",
10103 "fisttp{ll|}",
10104 "fst{l||}",
10105 "fstp{l|}",
10106 "frstor{C|C}",
10107 "(bad)",
10108 "fNsave{C|C}",
10109 "fNstsw",
10110 /* de */
10111 "fiadd{s|}",
10112 "fimul{s|}",
10113 "ficom{s|}",
10114 "ficomp{s|}",
10115 "fisub{s|}",
10116 "fisubr{s|}",
10117 "fidiv{s|}",
10118 "fidivr{s|}",
10119 /* df */
10120 "fild{s|}",
10121 "fisttp{s|}",
10122 "fist{s|}",
10123 "fistp{s|}",
10124 "fbld",
10125 "fild{ll|}",
10126 "fbstp",
10127 "fistp{ll|}",
10128 };
10129
10130 static const unsigned char float_mem_mode[] = {
10131 /* d8 */
10132 d_mode,
10133 d_mode,
10134 d_mode,
10135 d_mode,
10136 d_mode,
10137 d_mode,
10138 d_mode,
10139 d_mode,
10140 /* d9 */
10141 d_mode,
10142 0,
10143 d_mode,
10144 d_mode,
10145 0,
10146 w_mode,
10147 0,
10148 w_mode,
10149 /* da */
10150 d_mode,
10151 d_mode,
10152 d_mode,
10153 d_mode,
10154 d_mode,
10155 d_mode,
10156 d_mode,
10157 d_mode,
10158 /* db */
10159 d_mode,
10160 d_mode,
10161 d_mode,
10162 d_mode,
10163 0,
10164 t_mode,
10165 0,
10166 t_mode,
10167 /* dc */
10168 q_mode,
10169 q_mode,
10170 q_mode,
10171 q_mode,
10172 q_mode,
10173 q_mode,
10174 q_mode,
10175 q_mode,
10176 /* dd */
10177 q_mode,
10178 q_mode,
10179 q_mode,
10180 q_mode,
10181 0,
10182 0,
10183 0,
10184 w_mode,
10185 /* de */
10186 w_mode,
10187 w_mode,
10188 w_mode,
10189 w_mode,
10190 w_mode,
10191 w_mode,
10192 w_mode,
10193 w_mode,
10194 /* df */
10195 w_mode,
10196 w_mode,
10197 w_mode,
10198 w_mode,
10199 t_mode,
10200 q_mode,
10201 t_mode,
10202 q_mode
10203 };
10204
10205 #define ST { OP_ST, 0 }
10206 #define STi { OP_STi, 0 }
10207
10208 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
10209 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
10210 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
10211 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
10212 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
10213 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
10214 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
10215 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
10216 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
10217
10218 static const struct dis386 float_reg[][8] = {
10219 /* d8 */
10220 {
10221 { "fadd", { ST, STi }, 0 },
10222 { "fmul", { ST, STi }, 0 },
10223 { "fcom", { STi }, 0 },
10224 { "fcomp", { STi }, 0 },
10225 { "fsub", { ST, STi }, 0 },
10226 { "fsubr", { ST, STi }, 0 },
10227 { "fdiv", { ST, STi }, 0 },
10228 { "fdivr", { ST, STi }, 0 },
10229 },
10230 /* d9 */
10231 {
10232 { "fld", { STi }, 0 },
10233 { "fxch", { STi }, 0 },
10234 { FGRPd9_2 },
10235 { Bad_Opcode },
10236 { FGRPd9_4 },
10237 { FGRPd9_5 },
10238 { FGRPd9_6 },
10239 { FGRPd9_7 },
10240 },
10241 /* da */
10242 {
10243 { "fcmovb", { ST, STi }, 0 },
10244 { "fcmove", { ST, STi }, 0 },
10245 { "fcmovbe",{ ST, STi }, 0 },
10246 { "fcmovu", { ST, STi }, 0 },
10247 { Bad_Opcode },
10248 { FGRPda_5 },
10249 { Bad_Opcode },
10250 { Bad_Opcode },
10251 },
10252 /* db */
10253 {
10254 { "fcmovnb",{ ST, STi }, 0 },
10255 { "fcmovne",{ ST, STi }, 0 },
10256 { "fcmovnbe",{ ST, STi }, 0 },
10257 { "fcmovnu",{ ST, STi }, 0 },
10258 { FGRPdb_4 },
10259 { "fucomi", { ST, STi }, 0 },
10260 { "fcomi", { ST, STi }, 0 },
10261 { Bad_Opcode },
10262 },
10263 /* dc */
10264 {
10265 { "fadd", { STi, ST }, 0 },
10266 { "fmul", { STi, ST }, 0 },
10267 { Bad_Opcode },
10268 { Bad_Opcode },
10269 { "fsub{!M|r}", { STi, ST }, 0 },
10270 { "fsub{M|}", { STi, ST }, 0 },
10271 { "fdiv{!M|r}", { STi, ST }, 0 },
10272 { "fdiv{M|}", { STi, ST }, 0 },
10273 },
10274 /* dd */
10275 {
10276 { "ffree", { STi }, 0 },
10277 { Bad_Opcode },
10278 { "fst", { STi }, 0 },
10279 { "fstp", { STi }, 0 },
10280 { "fucom", { STi }, 0 },
10281 { "fucomp", { STi }, 0 },
10282 { Bad_Opcode },
10283 { Bad_Opcode },
10284 },
10285 /* de */
10286 {
10287 { "faddp", { STi, ST }, 0 },
10288 { "fmulp", { STi, ST }, 0 },
10289 { Bad_Opcode },
10290 { FGRPde_3 },
10291 { "fsub{!M|r}p", { STi, ST }, 0 },
10292 { "fsub{M|}p", { STi, ST }, 0 },
10293 { "fdiv{!M|r}p", { STi, ST }, 0 },
10294 { "fdiv{M|}p", { STi, ST }, 0 },
10295 },
10296 /* df */
10297 {
10298 { "ffreep", { STi }, 0 },
10299 { Bad_Opcode },
10300 { Bad_Opcode },
10301 { Bad_Opcode },
10302 { FGRPdf_4 },
10303 { "fucomip", { ST, STi }, 0 },
10304 { "fcomip", { ST, STi }, 0 },
10305 { Bad_Opcode },
10306 },
10307 };
10308
10309 static char *fgrps[][8] = {
10310 /* Bad opcode 0 */
10311 {
10312 "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10313 },
10314
10315 /* d9_2 1 */
10316 {
10317 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10318 },
10319
10320 /* d9_4 2 */
10321 {
10322 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
10323 },
10324
10325 /* d9_5 3 */
10326 {
10327 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
10328 },
10329
10330 /* d9_6 4 */
10331 {
10332 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
10333 },
10334
10335 /* d9_7 5 */
10336 {
10337 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
10338 },
10339
10340 /* da_5 6 */
10341 {
10342 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10343 },
10344
10345 /* db_4 7 */
10346 {
10347 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
10348 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
10349 },
10350
10351 /* de_3 8 */
10352 {
10353 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10354 },
10355
10356 /* df_4 9 */
10357 {
10358 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10359 },
10360 };
10361
10362 static void
10363 swap_operand (void)
10364 {
10365 mnemonicendp[0] = '.';
10366 mnemonicendp[1] = 's';
10367 mnemonicendp += 2;
10368 }
10369
10370 static void
10371 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
10372 int sizeflag ATTRIBUTE_UNUSED)
10373 {
10374 /* Skip mod/rm byte. */
10375 MODRM_CHECK;
10376 codep++;
10377 }
10378
10379 static void
10380 dofloat (int sizeflag)
10381 {
10382 const struct dis386 *dp;
10383 unsigned char floatop;
10384
10385 floatop = codep[-1];
10386
10387 if (modrm.mod != 3)
10388 {
10389 int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
10390
10391 putop (float_mem[fp_indx], sizeflag);
10392 obufp = op_out[0];
10393 op_ad = 2;
10394 OP_E (float_mem_mode[fp_indx], sizeflag);
10395 return;
10396 }
10397 /* Skip mod/rm byte. */
10398 MODRM_CHECK;
10399 codep++;
10400
10401 dp = &float_reg[floatop - 0xd8][modrm.reg];
10402 if (dp->name == NULL)
10403 {
10404 putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
10405
10406 /* Instruction fnstsw is only one with strange arg. */
10407 if (floatop == 0xdf && codep[-1] == 0xe0)
10408 strcpy (op_out[0], names16[0]);
10409 }
10410 else
10411 {
10412 putop (dp->name, sizeflag);
10413
10414 obufp = op_out[0];
10415 op_ad = 2;
10416 if (dp->op[0].rtn)
10417 (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
10418
10419 obufp = op_out[1];
10420 op_ad = 1;
10421 if (dp->op[1].rtn)
10422 (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
10423 }
10424 }
10425
10426 /* Like oappend (below), but S is a string starting with '%'.
10427 In Intel syntax, the '%' is elided. */
10428 static void
10429 oappend_maybe_intel (const char *s)
10430 {
10431 oappend (s + intel_syntax);
10432 }
10433
10434 static void
10435 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
10436 {
10437 oappend_maybe_intel ("%st");
10438 }
10439
10440 static void
10441 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
10442 {
10443 sprintf (scratchbuf, "%%st(%d)", modrm.rm);
10444 oappend_maybe_intel (scratchbuf);
10445 }
10446
10447 /* Capital letters in template are macros. */
10448 static int
10449 putop (const char *in_template, int sizeflag)
10450 {
10451 const char *p;
10452 int alt = 0;
10453 int cond = 1;
10454 unsigned int l = 0, len = 0;
10455 char last[4];
10456
10457 for (p = in_template; *p; p++)
10458 {
10459 if (len > l)
10460 {
10461 if (l >= sizeof (last) || !ISUPPER (*p))
10462 abort ();
10463 last[l++] = *p;
10464 continue;
10465 }
10466 switch (*p)
10467 {
10468 default:
10469 *obufp++ = *p;
10470 break;
10471 case '%':
10472 len++;
10473 break;
10474 case '!':
10475 cond = 0;
10476 break;
10477 case '{':
10478 if (intel_syntax)
10479 {
10480 while (*++p != '|')
10481 if (*p == '}' || *p == '\0')
10482 abort ();
10483 alt = 1;
10484 }
10485 break;
10486 case '|':
10487 while (*++p != '}')
10488 {
10489 if (*p == '\0')
10490 abort ();
10491 }
10492 break;
10493 case '}':
10494 alt = 0;
10495 break;
10496 case 'A':
10497 if (intel_syntax)
10498 break;
10499 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
10500 *obufp++ = 'b';
10501 break;
10502 case 'B':
10503 if (l == 0)
10504 {
10505 case_B:
10506 if (intel_syntax)
10507 break;
10508 if (sizeflag & SUFFIX_ALWAYS)
10509 *obufp++ = 'b';
10510 }
10511 else if (l == 1 && last[0] == 'L')
10512 {
10513 if (address_mode == mode_64bit
10514 && !(prefixes & PREFIX_ADDR))
10515 {
10516 *obufp++ = 'a';
10517 *obufp++ = 'b';
10518 *obufp++ = 's';
10519 }
10520
10521 goto case_B;
10522 }
10523 else
10524 abort ();
10525 break;
10526 case 'C':
10527 if (intel_syntax && !alt)
10528 break;
10529 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10530 {
10531 if (sizeflag & DFLAG)
10532 *obufp++ = intel_syntax ? 'd' : 'l';
10533 else
10534 *obufp++ = intel_syntax ? 'w' : 's';
10535 used_prefixes |= (prefixes & PREFIX_DATA);
10536 }
10537 break;
10538 case 'D':
10539 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
10540 break;
10541 USED_REX (REX_W);
10542 if (modrm.mod == 3)
10543 {
10544 if (rex & REX_W)
10545 *obufp++ = 'q';
10546 else
10547 {
10548 if (sizeflag & DFLAG)
10549 *obufp++ = intel_syntax ? 'd' : 'l';
10550 else
10551 *obufp++ = 'w';
10552 used_prefixes |= (prefixes & PREFIX_DATA);
10553 }
10554 }
10555 else
10556 *obufp++ = 'w';
10557 break;
10558 case 'E': /* For jcxz/jecxz */
10559 if (address_mode == mode_64bit)
10560 {
10561 if (sizeflag & AFLAG)
10562 *obufp++ = 'r';
10563 else
10564 *obufp++ = 'e';
10565 }
10566 else
10567 if (sizeflag & AFLAG)
10568 *obufp++ = 'e';
10569 used_prefixes |= (prefixes & PREFIX_ADDR);
10570 break;
10571 case 'F':
10572 if (intel_syntax)
10573 break;
10574 if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
10575 {
10576 if (sizeflag & AFLAG)
10577 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
10578 else
10579 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
10580 used_prefixes |= (prefixes & PREFIX_ADDR);
10581 }
10582 break;
10583 case 'G':
10584 if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
10585 break;
10586 if ((rex & REX_W) || (sizeflag & DFLAG))
10587 *obufp++ = 'l';
10588 else
10589 *obufp++ = 'w';
10590 if (!(rex & REX_W))
10591 used_prefixes |= (prefixes & PREFIX_DATA);
10592 break;
10593 case 'H':
10594 if (intel_syntax)
10595 break;
10596 if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
10597 || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
10598 {
10599 used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
10600 *obufp++ = ',';
10601 *obufp++ = 'p';
10602 if (prefixes & PREFIX_DS)
10603 *obufp++ = 't';
10604 else
10605 *obufp++ = 'n';
10606 }
10607 break;
10608 case 'K':
10609 USED_REX (REX_W);
10610 if (rex & REX_W)
10611 *obufp++ = 'q';
10612 else
10613 *obufp++ = 'd';
10614 break;
10615 case 'Z':
10616 if (l != 0)
10617 {
10618 if (l != 1 || last[0] != 'X')
10619 abort ();
10620 if (!need_vex || !vex.evex)
10621 abort ();
10622 if (intel_syntax
10623 || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
10624 break;
10625 switch (vex.length)
10626 {
10627 case 128:
10628 *obufp++ = 'x';
10629 break;
10630 case 256:
10631 *obufp++ = 'y';
10632 break;
10633 case 512:
10634 *obufp++ = 'z';
10635 break;
10636 default:
10637 abort ();
10638 }
10639 break;
10640 }
10641 if (intel_syntax)
10642 break;
10643 if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
10644 {
10645 *obufp++ = 'q';
10646 break;
10647 }
10648 /* Fall through. */
10649 goto case_L;
10650 case 'L':
10651 if (l != 0)
10652 abort ();
10653 case_L:
10654 if (intel_syntax)
10655 break;
10656 if (sizeflag & SUFFIX_ALWAYS)
10657 *obufp++ = 'l';
10658 break;
10659 case 'M':
10660 if (intel_mnemonic != cond)
10661 *obufp++ = 'r';
10662 break;
10663 case 'N':
10664 if ((prefixes & PREFIX_FWAIT) == 0)
10665 *obufp++ = 'n';
10666 else
10667 used_prefixes |= PREFIX_FWAIT;
10668 break;
10669 case 'O':
10670 USED_REX (REX_W);
10671 if (rex & REX_W)
10672 *obufp++ = 'o';
10673 else if (intel_syntax && (sizeflag & DFLAG))
10674 *obufp++ = 'q';
10675 else
10676 *obufp++ = 'd';
10677 if (!(rex & REX_W))
10678 used_prefixes |= (prefixes & PREFIX_DATA);
10679 break;
10680 case '&':
10681 if (!intel_syntax
10682 && address_mode == mode_64bit
10683 && isa64 == intel64)
10684 {
10685 *obufp++ = 'q';
10686 break;
10687 }
10688 /* Fall through. */
10689 case 'T':
10690 if (!intel_syntax
10691 && address_mode == mode_64bit
10692 && ((sizeflag & DFLAG) || (rex & REX_W)))
10693 {
10694 *obufp++ = 'q';
10695 break;
10696 }
10697 /* Fall through. */
10698 goto case_P;
10699 case 'P':
10700 if (l == 0)
10701 {
10702 case_P:
10703 if (intel_syntax)
10704 {
10705 if ((rex & REX_W) == 0
10706 && (prefixes & PREFIX_DATA))
10707 {
10708 if ((sizeflag & DFLAG) == 0)
10709 *obufp++ = 'w';
10710 used_prefixes |= (prefixes & PREFIX_DATA);
10711 }
10712 break;
10713 }
10714 if ((prefixes & PREFIX_DATA)
10715 || (rex & REX_W)
10716 || (sizeflag & SUFFIX_ALWAYS))
10717 {
10718 USED_REX (REX_W);
10719 if (rex & REX_W)
10720 *obufp++ = 'q';
10721 else
10722 {
10723 if (sizeflag & DFLAG)
10724 *obufp++ = 'l';
10725 else
10726 *obufp++ = 'w';
10727 used_prefixes |= (prefixes & PREFIX_DATA);
10728 }
10729 }
10730 }
10731 else if (l == 1 && last[0] == 'L')
10732 {
10733 if ((prefixes & PREFIX_DATA)
10734 || (rex & REX_W)
10735 || (sizeflag & SUFFIX_ALWAYS))
10736 {
10737 USED_REX (REX_W);
10738 if (rex & REX_W)
10739 *obufp++ = 'q';
10740 else
10741 {
10742 if (sizeflag & DFLAG)
10743 *obufp++ = intel_syntax ? 'd' : 'l';
10744 else
10745 *obufp++ = 'w';
10746 used_prefixes |= (prefixes & PREFIX_DATA);
10747 }
10748 }
10749 }
10750 else
10751 abort ();
10752 break;
10753 case 'U':
10754 if (intel_syntax)
10755 break;
10756 if (address_mode == mode_64bit
10757 && ((sizeflag & DFLAG) || (rex & REX_W)))
10758 {
10759 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
10760 *obufp++ = 'q';
10761 break;
10762 }
10763 /* Fall through. */
10764 goto case_Q;
10765 case 'Q':
10766 if (l == 0)
10767 {
10768 case_Q:
10769 if (intel_syntax && !alt)
10770 break;
10771 USED_REX (REX_W);
10772 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
10773 {
10774 if (rex & REX_W)
10775 *obufp++ = 'q';
10776 else
10777 {
10778 if (sizeflag & DFLAG)
10779 *obufp++ = intel_syntax ? 'd' : 'l';
10780 else
10781 *obufp++ = 'w';
10782 used_prefixes |= (prefixes & PREFIX_DATA);
10783 }
10784 }
10785 }
10786 else if (l == 1 && last[0] == 'D')
10787 *obufp++ = vex.w ? 'q' : 'd';
10788 else if (l == 1 && last[0] == 'L')
10789 {
10790 if (cond ? modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)
10791 : address_mode != mode_64bit)
10792 break;
10793 if ((rex & REX_W))
10794 {
10795 USED_REX (REX_W);
10796 *obufp++ = 'q';
10797 }
10798 else if((address_mode == mode_64bit && need_modrm && cond)
10799 || (sizeflag & SUFFIX_ALWAYS))
10800 *obufp++ = intel_syntax? 'd' : 'l';
10801 }
10802 else
10803 abort ();
10804 break;
10805 case 'R':
10806 USED_REX (REX_W);
10807 if (rex & REX_W)
10808 *obufp++ = 'q';
10809 else if (sizeflag & DFLAG)
10810 {
10811 if (intel_syntax)
10812 *obufp++ = 'd';
10813 else
10814 *obufp++ = 'l';
10815 }
10816 else
10817 *obufp++ = 'w';
10818 if (intel_syntax && !p[1]
10819 && ((rex & REX_W) || (sizeflag & DFLAG)))
10820 *obufp++ = 'e';
10821 if (!(rex & REX_W))
10822 used_prefixes |= (prefixes & PREFIX_DATA);
10823 break;
10824 case 'V':
10825 if (l == 0)
10826 {
10827 if (intel_syntax)
10828 break;
10829 if (address_mode == mode_64bit
10830 && ((sizeflag & DFLAG) || (rex & REX_W)))
10831 {
10832 if (sizeflag & SUFFIX_ALWAYS)
10833 *obufp++ = 'q';
10834 break;
10835 }
10836 }
10837 else if (l == 1 && last[0] == 'L')
10838 {
10839 if (rex & REX_W)
10840 {
10841 *obufp++ = 'a';
10842 *obufp++ = 'b';
10843 *obufp++ = 's';
10844 }
10845 }
10846 else
10847 abort ();
10848 /* Fall through. */
10849 goto case_S;
10850 case 'S':
10851 if (l == 0)
10852 {
10853 case_S:
10854 if (intel_syntax)
10855 break;
10856 if (sizeflag & SUFFIX_ALWAYS)
10857 {
10858 if (rex & REX_W)
10859 *obufp++ = 'q';
10860 else
10861 {
10862 if (sizeflag & DFLAG)
10863 *obufp++ = 'l';
10864 else
10865 *obufp++ = 'w';
10866 used_prefixes |= (prefixes & PREFIX_DATA);
10867 }
10868 }
10869 }
10870 else if (l == 1 && last[0] == 'L')
10871 {
10872 if (address_mode == mode_64bit
10873 && !(prefixes & PREFIX_ADDR))
10874 {
10875 *obufp++ = 'a';
10876 *obufp++ = 'b';
10877 *obufp++ = 's';
10878 }
10879
10880 goto case_S;
10881 }
10882 else
10883 abort ();
10884 break;
10885 case 'X':
10886 if (l != 0)
10887 abort ();
10888 if (need_vex
10889 ? vex.prefix == DATA_PREFIX_OPCODE
10890 : prefixes & PREFIX_DATA)
10891 {
10892 *obufp++ = 'd';
10893 used_prefixes |= PREFIX_DATA;
10894 }
10895 else
10896 *obufp++ = 's';
10897 break;
10898 case 'Y':
10899 if (l == 1 && last[0] == 'X')
10900 {
10901 if (!need_vex)
10902 abort ();
10903 if (intel_syntax
10904 || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
10905 break;
10906 switch (vex.length)
10907 {
10908 case 128:
10909 *obufp++ = 'x';
10910 break;
10911 case 256:
10912 *obufp++ = 'y';
10913 break;
10914 case 512:
10915 if (!vex.evex)
10916 default:
10917 abort ();
10918 }
10919 }
10920 else
10921 abort ();
10922 break;
10923 case 'W':
10924 if (l == 0)
10925 {
10926 /* operand size flag for cwtl, cbtw */
10927 USED_REX (REX_W);
10928 if (rex & REX_W)
10929 {
10930 if (intel_syntax)
10931 *obufp++ = 'd';
10932 else
10933 *obufp++ = 'l';
10934 }
10935 else if (sizeflag & DFLAG)
10936 *obufp++ = 'w';
10937 else
10938 *obufp++ = 'b';
10939 if (!(rex & REX_W))
10940 used_prefixes |= (prefixes & PREFIX_DATA);
10941 }
10942 else if (l == 1)
10943 {
10944 if (!need_vex)
10945 abort ();
10946 if (last[0] == 'X')
10947 *obufp++ = vex.w ? 'd': 's';
10948 else if (last[0] == 'B')
10949 *obufp++ = vex.w ? 'w': 'b';
10950 else
10951 abort ();
10952 }
10953 else
10954 abort ();
10955 break;
10956 case '^':
10957 if (intel_syntax)
10958 break;
10959 if (isa64 == intel64 && (rex & REX_W))
10960 {
10961 USED_REX (REX_W);
10962 *obufp++ = 'q';
10963 break;
10964 }
10965 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10966 {
10967 if (sizeflag & DFLAG)
10968 *obufp++ = 'l';
10969 else
10970 *obufp++ = 'w';
10971 used_prefixes |= (prefixes & PREFIX_DATA);
10972 }
10973 break;
10974 case '@':
10975 if (intel_syntax)
10976 break;
10977 if (address_mode == mode_64bit
10978 && (isa64 == intel64
10979 || ((sizeflag & DFLAG) || (rex & REX_W))))
10980 *obufp++ = 'q';
10981 else if ((prefixes & PREFIX_DATA))
10982 {
10983 if (!(sizeflag & DFLAG))
10984 *obufp++ = 'w';
10985 used_prefixes |= (prefixes & PREFIX_DATA);
10986 }
10987 break;
10988 }
10989
10990 if (len == l)
10991 len = l = 0;
10992 }
10993 *obufp = 0;
10994 mnemonicendp = obufp;
10995 return 0;
10996 }
10997
10998 static void
10999 oappend (const char *s)
11000 {
11001 obufp = stpcpy (obufp, s);
11002 }
11003
11004 static void
11005 append_seg (void)
11006 {
11007 /* Only print the active segment register. */
11008 if (!active_seg_prefix)
11009 return;
11010
11011 used_prefixes |= active_seg_prefix;
11012 switch (active_seg_prefix)
11013 {
11014 case PREFIX_CS:
11015 oappend_maybe_intel ("%cs:");
11016 break;
11017 case PREFIX_DS:
11018 oappend_maybe_intel ("%ds:");
11019 break;
11020 case PREFIX_SS:
11021 oappend_maybe_intel ("%ss:");
11022 break;
11023 case PREFIX_ES:
11024 oappend_maybe_intel ("%es:");
11025 break;
11026 case PREFIX_FS:
11027 oappend_maybe_intel ("%fs:");
11028 break;
11029 case PREFIX_GS:
11030 oappend_maybe_intel ("%gs:");
11031 break;
11032 default:
11033 break;
11034 }
11035 }
11036
11037 static void
11038 OP_indirE (int bytemode, int sizeflag)
11039 {
11040 if (!intel_syntax)
11041 oappend ("*");
11042 OP_E (bytemode, sizeflag);
11043 }
11044
11045 static void
11046 print_operand_value (char *buf, int hex, bfd_vma disp)
11047 {
11048 if (address_mode == mode_64bit)
11049 {
11050 if (hex)
11051 {
11052 char tmp[30];
11053 int i;
11054 buf[0] = '0';
11055 buf[1] = 'x';
11056 sprintf_vma (tmp, disp);
11057 for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
11058 strcpy (buf + 2, tmp + i);
11059 }
11060 else
11061 {
11062 bfd_signed_vma v = disp;
11063 char tmp[30];
11064 int i;
11065 if (v < 0)
11066 {
11067 *(buf++) = '-';
11068 v = -disp;
11069 /* Check for possible overflow on 0x8000000000000000. */
11070 if (v < 0)
11071 {
11072 strcpy (buf, "9223372036854775808");
11073 return;
11074 }
11075 }
11076 if (!v)
11077 {
11078 strcpy (buf, "0");
11079 return;
11080 }
11081
11082 i = 0;
11083 tmp[29] = 0;
11084 while (v)
11085 {
11086 tmp[28 - i] = (v % 10) + '0';
11087 v /= 10;
11088 i++;
11089 }
11090 strcpy (buf, tmp + 29 - i);
11091 }
11092 }
11093 else
11094 {
11095 if (hex)
11096 sprintf (buf, "0x%x", (unsigned int) disp);
11097 else
11098 sprintf (buf, "%d", (int) disp);
11099 }
11100 }
11101
11102 /* Put DISP in BUF as signed hex number. */
11103
11104 static void
11105 print_displacement (char *buf, bfd_vma disp)
11106 {
11107 bfd_signed_vma val = disp;
11108 char tmp[30];
11109 int i, j = 0;
11110
11111 if (val < 0)
11112 {
11113 buf[j++] = '-';
11114 val = -disp;
11115
11116 /* Check for possible overflow. */
11117 if (val < 0)
11118 {
11119 switch (address_mode)
11120 {
11121 case mode_64bit:
11122 strcpy (buf + j, "0x8000000000000000");
11123 break;
11124 case mode_32bit:
11125 strcpy (buf + j, "0x80000000");
11126 break;
11127 case mode_16bit:
11128 strcpy (buf + j, "0x8000");
11129 break;
11130 }
11131 return;
11132 }
11133 }
11134
11135 buf[j++] = '0';
11136 buf[j++] = 'x';
11137
11138 sprintf_vma (tmp, (bfd_vma) val);
11139 for (i = 0; tmp[i] == '0'; i++)
11140 continue;
11141 if (tmp[i] == '\0')
11142 i--;
11143 strcpy (buf + j, tmp + i);
11144 }
11145
11146 static void
11147 intel_operand_size (int bytemode, int sizeflag)
11148 {
11149 if (vex.evex
11150 && vex.b
11151 && (bytemode == x_mode
11152 || bytemode == evex_half_bcst_xmmq_mode))
11153 {
11154 if (vex.w)
11155 oappend ("QWORD PTR ");
11156 else
11157 oappend ("DWORD PTR ");
11158 return;
11159 }
11160 switch (bytemode)
11161 {
11162 case b_mode:
11163 case b_swap_mode:
11164 case dqb_mode:
11165 case db_mode:
11166 oappend ("BYTE PTR ");
11167 break;
11168 case w_mode:
11169 case dw_mode:
11170 case dqw_mode:
11171 oappend ("WORD PTR ");
11172 break;
11173 case indir_v_mode:
11174 if (address_mode == mode_64bit && isa64 == intel64)
11175 {
11176 oappend ("QWORD PTR ");
11177 break;
11178 }
11179 /* Fall through. */
11180 case stack_v_mode:
11181 if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
11182 {
11183 oappend ("QWORD PTR ");
11184 break;
11185 }
11186 /* Fall through. */
11187 case v_mode:
11188 case v_swap_mode:
11189 case dq_mode:
11190 USED_REX (REX_W);
11191 if (rex & REX_W)
11192 oappend ("QWORD PTR ");
11193 else if (bytemode == dq_mode)
11194 oappend ("DWORD PTR ");
11195 else
11196 {
11197 if (sizeflag & DFLAG)
11198 oappend ("DWORD PTR ");
11199 else
11200 oappend ("WORD PTR ");
11201 used_prefixes |= (prefixes & PREFIX_DATA);
11202 }
11203 break;
11204 case z_mode:
11205 if ((rex & REX_W) || (sizeflag & DFLAG))
11206 *obufp++ = 'D';
11207 oappend ("WORD PTR ");
11208 if (!(rex & REX_W))
11209 used_prefixes |= (prefixes & PREFIX_DATA);
11210 break;
11211 case a_mode:
11212 if (sizeflag & DFLAG)
11213 oappend ("QWORD PTR ");
11214 else
11215 oappend ("DWORD PTR ");
11216 used_prefixes |= (prefixes & PREFIX_DATA);
11217 break;
11218 case movsxd_mode:
11219 if (!(sizeflag & DFLAG) && isa64 == intel64)
11220 oappend ("WORD PTR ");
11221 else
11222 oappend ("DWORD PTR ");
11223 used_prefixes |= (prefixes & PREFIX_DATA);
11224 break;
11225 case d_mode:
11226 case d_swap_mode:
11227 case dqd_mode:
11228 oappend ("DWORD PTR ");
11229 break;
11230 case q_mode:
11231 case q_swap_mode:
11232 oappend ("QWORD PTR ");
11233 break;
11234 case m_mode:
11235 if (address_mode == mode_64bit)
11236 oappend ("QWORD PTR ");
11237 else
11238 oappend ("DWORD PTR ");
11239 break;
11240 case f_mode:
11241 if (sizeflag & DFLAG)
11242 oappend ("FWORD PTR ");
11243 else
11244 oappend ("DWORD PTR ");
11245 used_prefixes |= (prefixes & PREFIX_DATA);
11246 break;
11247 case t_mode:
11248 oappend ("TBYTE PTR ");
11249 break;
11250 case x_mode:
11251 case x_swap_mode:
11252 case evex_x_gscat_mode:
11253 case evex_x_nobcst_mode:
11254 case bw_unit_mode:
11255 if (need_vex)
11256 {
11257 switch (vex.length)
11258 {
11259 case 128:
11260 oappend ("XMMWORD PTR ");
11261 break;
11262 case 256:
11263 oappend ("YMMWORD PTR ");
11264 break;
11265 case 512:
11266 oappend ("ZMMWORD PTR ");
11267 break;
11268 default:
11269 abort ();
11270 }
11271 }
11272 else
11273 oappend ("XMMWORD PTR ");
11274 break;
11275 case xmm_mode:
11276 oappend ("XMMWORD PTR ");
11277 break;
11278 case ymm_mode:
11279 oappend ("YMMWORD PTR ");
11280 break;
11281 case xmmq_mode:
11282 case evex_half_bcst_xmmq_mode:
11283 if (!need_vex)
11284 abort ();
11285
11286 switch (vex.length)
11287 {
11288 case 128:
11289 oappend ("QWORD PTR ");
11290 break;
11291 case 256:
11292 oappend ("XMMWORD PTR ");
11293 break;
11294 case 512:
11295 oappend ("YMMWORD PTR ");
11296 break;
11297 default:
11298 abort ();
11299 }
11300 break;
11301 case xmm_mb_mode:
11302 if (!need_vex)
11303 abort ();
11304
11305 switch (vex.length)
11306 {
11307 case 128:
11308 case 256:
11309 case 512:
11310 oappend ("BYTE PTR ");
11311 break;
11312 default:
11313 abort ();
11314 }
11315 break;
11316 case xmm_mw_mode:
11317 if (!need_vex)
11318 abort ();
11319
11320 switch (vex.length)
11321 {
11322 case 128:
11323 case 256:
11324 case 512:
11325 oappend ("WORD PTR ");
11326 break;
11327 default:
11328 abort ();
11329 }
11330 break;
11331 case xmm_md_mode:
11332 if (!need_vex)
11333 abort ();
11334
11335 switch (vex.length)
11336 {
11337 case 128:
11338 case 256:
11339 case 512:
11340 oappend ("DWORD PTR ");
11341 break;
11342 default:
11343 abort ();
11344 }
11345 break;
11346 case xmm_mq_mode:
11347 if (!need_vex)
11348 abort ();
11349
11350 switch (vex.length)
11351 {
11352 case 128:
11353 case 256:
11354 case 512:
11355 oappend ("QWORD PTR ");
11356 break;
11357 default:
11358 abort ();
11359 }
11360 break;
11361 case xmmdw_mode:
11362 if (!need_vex)
11363 abort ();
11364
11365 switch (vex.length)
11366 {
11367 case 128:
11368 oappend ("WORD PTR ");
11369 break;
11370 case 256:
11371 oappend ("DWORD PTR ");
11372 break;
11373 case 512:
11374 oappend ("QWORD PTR ");
11375 break;
11376 default:
11377 abort ();
11378 }
11379 break;
11380 case xmmqd_mode:
11381 if (!need_vex)
11382 abort ();
11383
11384 switch (vex.length)
11385 {
11386 case 128:
11387 oappend ("DWORD PTR ");
11388 break;
11389 case 256:
11390 oappend ("QWORD PTR ");
11391 break;
11392 case 512:
11393 oappend ("XMMWORD PTR ");
11394 break;
11395 default:
11396 abort ();
11397 }
11398 break;
11399 case ymmq_mode:
11400 if (!need_vex)
11401 abort ();
11402
11403 switch (vex.length)
11404 {
11405 case 128:
11406 oappend ("QWORD PTR ");
11407 break;
11408 case 256:
11409 oappend ("YMMWORD PTR ");
11410 break;
11411 case 512:
11412 oappend ("ZMMWORD PTR ");
11413 break;
11414 default:
11415 abort ();
11416 }
11417 break;
11418 case ymmxmm_mode:
11419 if (!need_vex)
11420 abort ();
11421
11422 switch (vex.length)
11423 {
11424 case 128:
11425 case 256:
11426 oappend ("XMMWORD PTR ");
11427 break;
11428 default:
11429 abort ();
11430 }
11431 break;
11432 case o_mode:
11433 oappend ("OWORD PTR ");
11434 break;
11435 case vex_scalar_w_dq_mode:
11436 if (!need_vex)
11437 abort ();
11438
11439 if (vex.w)
11440 oappend ("QWORD PTR ");
11441 else
11442 oappend ("DWORD PTR ");
11443 break;
11444 case vex_vsib_d_w_dq_mode:
11445 case vex_vsib_q_w_dq_mode:
11446 if (!need_vex)
11447 abort ();
11448
11449 if (!vex.evex)
11450 {
11451 if (vex.w)
11452 oappend ("QWORD PTR ");
11453 else
11454 oappend ("DWORD PTR ");
11455 }
11456 else
11457 {
11458 switch (vex.length)
11459 {
11460 case 128:
11461 oappend ("XMMWORD PTR ");
11462 break;
11463 case 256:
11464 oappend ("YMMWORD PTR ");
11465 break;
11466 case 512:
11467 oappend ("ZMMWORD PTR ");
11468 break;
11469 default:
11470 abort ();
11471 }
11472 }
11473 break;
11474 case vex_vsib_q_w_d_mode:
11475 case vex_vsib_d_w_d_mode:
11476 if (!need_vex || !vex.evex)
11477 abort ();
11478
11479 switch (vex.length)
11480 {
11481 case 128:
11482 oappend ("QWORD PTR ");
11483 break;
11484 case 256:
11485 oappend ("XMMWORD PTR ");
11486 break;
11487 case 512:
11488 oappend ("YMMWORD PTR ");
11489 break;
11490 default:
11491 abort ();
11492 }
11493
11494 break;
11495 case mask_bd_mode:
11496 if (!need_vex || vex.length != 128)
11497 abort ();
11498 if (vex.w)
11499 oappend ("DWORD PTR ");
11500 else
11501 oappend ("BYTE PTR ");
11502 break;
11503 case mask_mode:
11504 if (!need_vex)
11505 abort ();
11506 if (vex.w)
11507 oappend ("QWORD PTR ");
11508 else
11509 oappend ("WORD PTR ");
11510 break;
11511 case v_bnd_mode:
11512 case v_bndmk_mode:
11513 default:
11514 break;
11515 }
11516 }
11517
11518 static void
11519 OP_E_register (int bytemode, int sizeflag)
11520 {
11521 int reg = modrm.rm;
11522 const char **names;
11523
11524 USED_REX (REX_B);
11525 if ((rex & REX_B))
11526 reg += 8;
11527
11528 if ((sizeflag & SUFFIX_ALWAYS)
11529 && (bytemode == b_swap_mode
11530 || bytemode == bnd_swap_mode
11531 || bytemode == v_swap_mode))
11532 swap_operand ();
11533
11534 switch (bytemode)
11535 {
11536 case b_mode:
11537 case b_swap_mode:
11538 if (reg & 4)
11539 USED_REX (0);
11540 if (rex)
11541 names = names8rex;
11542 else
11543 names = names8;
11544 break;
11545 case w_mode:
11546 names = names16;
11547 break;
11548 case d_mode:
11549 case dw_mode:
11550 case db_mode:
11551 names = names32;
11552 break;
11553 case q_mode:
11554 names = names64;
11555 break;
11556 case m_mode:
11557 case v_bnd_mode:
11558 names = address_mode == mode_64bit ? names64 : names32;
11559 break;
11560 case bnd_mode:
11561 case bnd_swap_mode:
11562 if (reg > 0x3)
11563 {
11564 oappend ("(bad)");
11565 return;
11566 }
11567 names = names_bnd;
11568 break;
11569 case indir_v_mode:
11570 if (address_mode == mode_64bit && isa64 == intel64)
11571 {
11572 names = names64;
11573 break;
11574 }
11575 /* Fall through. */
11576 case stack_v_mode:
11577 if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
11578 {
11579 names = names64;
11580 break;
11581 }
11582 bytemode = v_mode;
11583 /* Fall through. */
11584 case v_mode:
11585 case v_swap_mode:
11586 case dq_mode:
11587 case dqb_mode:
11588 case dqd_mode:
11589 case dqw_mode:
11590 USED_REX (REX_W);
11591 if (rex & REX_W)
11592 names = names64;
11593 else if (bytemode != v_mode && bytemode != v_swap_mode)
11594 names = names32;
11595 else
11596 {
11597 if (sizeflag & DFLAG)
11598 names = names32;
11599 else
11600 names = names16;
11601 used_prefixes |= (prefixes & PREFIX_DATA);
11602 }
11603 break;
11604 case movsxd_mode:
11605 if (!(sizeflag & DFLAG) && isa64 == intel64)
11606 names = names16;
11607 else
11608 names = names32;
11609 used_prefixes |= (prefixes & PREFIX_DATA);
11610 break;
11611 case va_mode:
11612 names = (address_mode == mode_64bit
11613 ? names64 : names32);
11614 if (!(prefixes & PREFIX_ADDR))
11615 names = (address_mode == mode_16bit
11616 ? names16 : names);
11617 else
11618 {
11619 /* Remove "addr16/addr32". */
11620 all_prefixes[last_addr_prefix] = 0;
11621 names = (address_mode != mode_32bit
11622 ? names32 : names16);
11623 used_prefixes |= PREFIX_ADDR;
11624 }
11625 break;
11626 case mask_bd_mode:
11627 case mask_mode:
11628 if (reg > 0x7)
11629 {
11630 oappend ("(bad)");
11631 return;
11632 }
11633 names = names_mask;
11634 break;
11635 case 0:
11636 return;
11637 default:
11638 oappend (INTERNAL_DISASSEMBLER_ERROR);
11639 return;
11640 }
11641 oappend (names[reg]);
11642 }
11643
11644 static void
11645 OP_E_memory (int bytemode, int sizeflag)
11646 {
11647 bfd_vma disp = 0;
11648 int add = (rex & REX_B) ? 8 : 0;
11649 int riprel = 0;
11650 int shift;
11651
11652 if (vex.evex)
11653 {
11654 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
11655 if (vex.b
11656 && bytemode != x_mode
11657 && bytemode != xmmq_mode
11658 && bytemode != evex_half_bcst_xmmq_mode)
11659 {
11660 BadOp ();
11661 return;
11662 }
11663 switch (bytemode)
11664 {
11665 case dqw_mode:
11666 case dw_mode:
11667 case xmm_mw_mode:
11668 shift = 1;
11669 break;
11670 case dqb_mode:
11671 case db_mode:
11672 case xmm_mb_mode:
11673 shift = 0;
11674 break;
11675 case dq_mode:
11676 if (address_mode != mode_64bit)
11677 {
11678 case dqd_mode:
11679 case xmm_md_mode:
11680 case d_mode:
11681 case d_swap_mode:
11682 shift = 2;
11683 break;
11684 }
11685 /* fall through */
11686 case vex_scalar_w_dq_mode:
11687 case vex_vsib_d_w_dq_mode:
11688 case vex_vsib_d_w_d_mode:
11689 case vex_vsib_q_w_dq_mode:
11690 case vex_vsib_q_w_d_mode:
11691 case evex_x_gscat_mode:
11692 shift = vex.w ? 3 : 2;
11693 break;
11694 case x_mode:
11695 case evex_half_bcst_xmmq_mode:
11696 case xmmq_mode:
11697 if (vex.b)
11698 {
11699 shift = vex.w ? 3 : 2;
11700 break;
11701 }
11702 /* Fall through. */
11703 case xmmqd_mode:
11704 case xmmdw_mode:
11705 case ymmq_mode:
11706 case evex_x_nobcst_mode:
11707 case x_swap_mode:
11708 switch (vex.length)
11709 {
11710 case 128:
11711 shift = 4;
11712 break;
11713 case 256:
11714 shift = 5;
11715 break;
11716 case 512:
11717 shift = 6;
11718 break;
11719 default:
11720 abort ();
11721 }
11722 /* Make necessary corrections to shift for modes that need it. */
11723 if (bytemode == xmmq_mode
11724 || bytemode == evex_half_bcst_xmmq_mode
11725 || (bytemode == ymmq_mode && vex.length == 128))
11726 shift -= 1;
11727 else if (bytemode == xmmqd_mode)
11728 shift -= 2;
11729 else if (bytemode == xmmdw_mode)
11730 shift -= 3;
11731 break;
11732 case ymm_mode:
11733 shift = 5;
11734 break;
11735 case xmm_mode:
11736 shift = 4;
11737 break;
11738 case xmm_mq_mode:
11739 case q_mode:
11740 case q_swap_mode:
11741 shift = 3;
11742 break;
11743 case bw_unit_mode:
11744 shift = vex.w ? 1 : 0;
11745 break;
11746 default:
11747 abort ();
11748 }
11749 }
11750 else
11751 shift = 0;
11752
11753 USED_REX (REX_B);
11754 if (intel_syntax)
11755 intel_operand_size (bytemode, sizeflag);
11756 append_seg ();
11757
11758 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
11759 {
11760 /* 32/64 bit address mode */
11761 int havedisp;
11762 int havesib;
11763 int havebase;
11764 int haveindex;
11765 int needindex;
11766 int needaddr32;
11767 int base, rbase;
11768 int vindex = 0;
11769 int scale = 0;
11770 int addr32flag = !((sizeflag & AFLAG)
11771 || bytemode == v_bnd_mode
11772 || bytemode == v_bndmk_mode
11773 || bytemode == bnd_mode
11774 || bytemode == bnd_swap_mode);
11775 const char **indexes64 = names64;
11776 const char **indexes32 = names32;
11777
11778 havesib = 0;
11779 havebase = 1;
11780 haveindex = 0;
11781 base = modrm.rm;
11782
11783 if (base == 4)
11784 {
11785 havesib = 1;
11786 vindex = sib.index;
11787 USED_REX (REX_X);
11788 if (rex & REX_X)
11789 vindex += 8;
11790 switch (bytemode)
11791 {
11792 case vex_vsib_d_w_dq_mode:
11793 case vex_vsib_d_w_d_mode:
11794 case vex_vsib_q_w_dq_mode:
11795 case vex_vsib_q_w_d_mode:
11796 if (!need_vex)
11797 abort ();
11798 if (vex.evex)
11799 {
11800 if (!vex.v)
11801 vindex += 16;
11802 }
11803
11804 haveindex = 1;
11805 switch (vex.length)
11806 {
11807 case 128:
11808 indexes64 = indexes32 = names_xmm;
11809 break;
11810 case 256:
11811 if (!vex.w
11812 || bytemode == vex_vsib_q_w_dq_mode
11813 || bytemode == vex_vsib_q_w_d_mode)
11814 indexes64 = indexes32 = names_ymm;
11815 else
11816 indexes64 = indexes32 = names_xmm;
11817 break;
11818 case 512:
11819 if (!vex.w
11820 || bytemode == vex_vsib_q_w_dq_mode
11821 || bytemode == vex_vsib_q_w_d_mode)
11822 indexes64 = indexes32 = names_zmm;
11823 else
11824 indexes64 = indexes32 = names_ymm;
11825 break;
11826 default:
11827 abort ();
11828 }
11829 break;
11830 default:
11831 haveindex = vindex != 4;
11832 break;
11833 }
11834 scale = sib.scale;
11835 base = sib.base;
11836 codep++;
11837 }
11838 else
11839 {
11840 /* mandatory non-vector SIB must have sib */
11841 if (bytemode == vex_sibmem_mode)
11842 {
11843 oappend ("(bad)");
11844 return;
11845 }
11846 }
11847 rbase = base + add;
11848
11849 switch (modrm.mod)
11850 {
11851 case 0:
11852 if (base == 5)
11853 {
11854 havebase = 0;
11855 if (address_mode == mode_64bit && !havesib)
11856 riprel = 1;
11857 disp = get32s ();
11858 if (riprel && bytemode == v_bndmk_mode)
11859 {
11860 oappend ("(bad)");
11861 return;
11862 }
11863 }
11864 break;
11865 case 1:
11866 FETCH_DATA (the_info, codep + 1);
11867 disp = *codep++;
11868 if ((disp & 0x80) != 0)
11869 disp -= 0x100;
11870 if (vex.evex && shift > 0)
11871 disp <<= shift;
11872 break;
11873 case 2:
11874 disp = get32s ();
11875 break;
11876 }
11877
11878 needindex = 0;
11879 needaddr32 = 0;
11880 if (havesib
11881 && !havebase
11882 && !haveindex
11883 && address_mode != mode_16bit)
11884 {
11885 if (address_mode == mode_64bit)
11886 {
11887 /* Display eiz instead of addr32. */
11888 needindex = addr32flag;
11889 needaddr32 = 1;
11890 }
11891 else
11892 {
11893 /* In 32-bit mode, we need index register to tell [offset]
11894 from [eiz*1 + offset]. */
11895 needindex = 1;
11896 }
11897 }
11898
11899 havedisp = (havebase
11900 || needindex
11901 || (havesib && (haveindex || scale != 0)));
11902
11903 if (!intel_syntax)
11904 if (modrm.mod != 0 || base == 5)
11905 {
11906 if (havedisp || riprel)
11907 print_displacement (scratchbuf, disp);
11908 else
11909 print_operand_value (scratchbuf, 1, disp);
11910 oappend (scratchbuf);
11911 if (riprel)
11912 {
11913 set_op (disp, 1);
11914 oappend (!addr32flag ? "(%rip)" : "(%eip)");
11915 }
11916 }
11917
11918 if ((havebase || haveindex || needindex || needaddr32 || riprel)
11919 && (address_mode != mode_64bit
11920 || ((bytemode != v_bnd_mode)
11921 && (bytemode != v_bndmk_mode)
11922 && (bytemode != bnd_mode)
11923 && (bytemode != bnd_swap_mode))))
11924 used_prefixes |= PREFIX_ADDR;
11925
11926 if (havedisp || (intel_syntax && riprel))
11927 {
11928 *obufp++ = open_char;
11929 if (intel_syntax && riprel)
11930 {
11931 set_op (disp, 1);
11932 oappend (!addr32flag ? "rip" : "eip");
11933 }
11934 *obufp = '\0';
11935 if (havebase)
11936 oappend (address_mode == mode_64bit && !addr32flag
11937 ? names64[rbase] : names32[rbase]);
11938 if (havesib)
11939 {
11940 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
11941 print index to tell base + index from base. */
11942 if (scale != 0
11943 || needindex
11944 || haveindex
11945 || (havebase && base != ESP_REG_NUM))
11946 {
11947 if (!intel_syntax || havebase)
11948 {
11949 *obufp++ = separator_char;
11950 *obufp = '\0';
11951 }
11952 if (haveindex)
11953 oappend (address_mode == mode_64bit && !addr32flag
11954 ? indexes64[vindex] : indexes32[vindex]);
11955 else
11956 oappend (address_mode == mode_64bit && !addr32flag
11957 ? index64 : index32);
11958
11959 *obufp++ = scale_char;
11960 *obufp = '\0';
11961 sprintf (scratchbuf, "%d", 1 << scale);
11962 oappend (scratchbuf);
11963 }
11964 }
11965 if (intel_syntax
11966 && (disp || modrm.mod != 0 || base == 5))
11967 {
11968 if (!havedisp || (bfd_signed_vma) disp >= 0)
11969 {
11970 *obufp++ = '+';
11971 *obufp = '\0';
11972 }
11973 else if (modrm.mod != 1 && disp != -disp)
11974 {
11975 *obufp++ = '-';
11976 *obufp = '\0';
11977 disp = - (bfd_signed_vma) disp;
11978 }
11979
11980 if (havedisp)
11981 print_displacement (scratchbuf, disp);
11982 else
11983 print_operand_value (scratchbuf, 1, disp);
11984 oappend (scratchbuf);
11985 }
11986
11987 *obufp++ = close_char;
11988 *obufp = '\0';
11989 }
11990 else if (intel_syntax)
11991 {
11992 if (modrm.mod != 0 || base == 5)
11993 {
11994 if (!active_seg_prefix)
11995 {
11996 oappend (names_seg[ds_reg - es_reg]);
11997 oappend (":");
11998 }
11999 print_operand_value (scratchbuf, 1, disp);
12000 oappend (scratchbuf);
12001 }
12002 }
12003 }
12004 else if (bytemode == v_bnd_mode
12005 || bytemode == v_bndmk_mode
12006 || bytemode == bnd_mode
12007 || bytemode == bnd_swap_mode)
12008 {
12009 oappend ("(bad)");
12010 return;
12011 }
12012 else
12013 {
12014 /* 16 bit address mode */
12015 used_prefixes |= prefixes & PREFIX_ADDR;
12016 switch (modrm.mod)
12017 {
12018 case 0:
12019 if (modrm.rm == 6)
12020 {
12021 disp = get16 ();
12022 if ((disp & 0x8000) != 0)
12023 disp -= 0x10000;
12024 }
12025 break;
12026 case 1:
12027 FETCH_DATA (the_info, codep + 1);
12028 disp = *codep++;
12029 if ((disp & 0x80) != 0)
12030 disp -= 0x100;
12031 if (vex.evex && shift > 0)
12032 disp <<= shift;
12033 break;
12034 case 2:
12035 disp = get16 ();
12036 if ((disp & 0x8000) != 0)
12037 disp -= 0x10000;
12038 break;
12039 }
12040
12041 if (!intel_syntax)
12042 if (modrm.mod != 0 || modrm.rm == 6)
12043 {
12044 print_displacement (scratchbuf, disp);
12045 oappend (scratchbuf);
12046 }
12047
12048 if (modrm.mod != 0 || modrm.rm != 6)
12049 {
12050 *obufp++ = open_char;
12051 *obufp = '\0';
12052 oappend (index16[modrm.rm]);
12053 if (intel_syntax
12054 && (disp || modrm.mod != 0 || modrm.rm == 6))
12055 {
12056 if ((bfd_signed_vma) disp >= 0)
12057 {
12058 *obufp++ = '+';
12059 *obufp = '\0';
12060 }
12061 else if (modrm.mod != 1)
12062 {
12063 *obufp++ = '-';
12064 *obufp = '\0';
12065 disp = - (bfd_signed_vma) disp;
12066 }
12067
12068 print_displacement (scratchbuf, disp);
12069 oappend (scratchbuf);
12070 }
12071
12072 *obufp++ = close_char;
12073 *obufp = '\0';
12074 }
12075 else if (intel_syntax)
12076 {
12077 if (!active_seg_prefix)
12078 {
12079 oappend (names_seg[ds_reg - es_reg]);
12080 oappend (":");
12081 }
12082 print_operand_value (scratchbuf, 1, disp & 0xffff);
12083 oappend (scratchbuf);
12084 }
12085 }
12086 if (vex.evex && vex.b
12087 && (bytemode == x_mode
12088 || bytemode == xmmq_mode
12089 || bytemode == evex_half_bcst_xmmq_mode))
12090 {
12091 if (vex.w
12092 || bytemode == xmmq_mode
12093 || bytemode == evex_half_bcst_xmmq_mode)
12094 {
12095 switch (vex.length)
12096 {
12097 case 128:
12098 oappend ("{1to2}");
12099 break;
12100 case 256:
12101 oappend ("{1to4}");
12102 break;
12103 case 512:
12104 oappend ("{1to8}");
12105 break;
12106 default:
12107 abort ();
12108 }
12109 }
12110 else
12111 {
12112 switch (vex.length)
12113 {
12114 case 128:
12115 oappend ("{1to4}");
12116 break;
12117 case 256:
12118 oappend ("{1to8}");
12119 break;
12120 case 512:
12121 oappend ("{1to16}");
12122 break;
12123 default:
12124 abort ();
12125 }
12126 }
12127 }
12128 }
12129
12130 static void
12131 OP_E (int bytemode, int sizeflag)
12132 {
12133 /* Skip mod/rm byte. */
12134 MODRM_CHECK;
12135 codep++;
12136
12137 if (modrm.mod == 3)
12138 OP_E_register (bytemode, sizeflag);
12139 else
12140 OP_E_memory (bytemode, sizeflag);
12141 }
12142
12143 static void
12144 OP_G (int bytemode, int sizeflag)
12145 {
12146 int add = 0;
12147 const char **names;
12148 USED_REX (REX_R);
12149 if (rex & REX_R)
12150 add += 8;
12151 switch (bytemode)
12152 {
12153 case b_mode:
12154 if (modrm.reg & 4)
12155 USED_REX (0);
12156 if (rex)
12157 oappend (names8rex[modrm.reg + add]);
12158 else
12159 oappend (names8[modrm.reg + add]);
12160 break;
12161 case w_mode:
12162 oappend (names16[modrm.reg + add]);
12163 break;
12164 case d_mode:
12165 case db_mode:
12166 case dw_mode:
12167 oappend (names32[modrm.reg + add]);
12168 break;
12169 case q_mode:
12170 oappend (names64[modrm.reg + add]);
12171 break;
12172 case bnd_mode:
12173 if (modrm.reg > 0x3)
12174 {
12175 oappend ("(bad)");
12176 return;
12177 }
12178 oappend (names_bnd[modrm.reg]);
12179 break;
12180 case v_mode:
12181 case dq_mode:
12182 case dqb_mode:
12183 case dqd_mode:
12184 case dqw_mode:
12185 case movsxd_mode:
12186 USED_REX (REX_W);
12187 if (rex & REX_W)
12188 oappend (names64[modrm.reg + add]);
12189 else if (bytemode != v_mode && bytemode != movsxd_mode)
12190 oappend (names32[modrm.reg + add]);
12191 else
12192 {
12193 if (sizeflag & DFLAG)
12194 oappend (names32[modrm.reg + add]);
12195 else
12196 oappend (names16[modrm.reg + add]);
12197 used_prefixes |= (prefixes & PREFIX_DATA);
12198 }
12199 break;
12200 case va_mode:
12201 names = (address_mode == mode_64bit
12202 ? names64 : names32);
12203 if (!(prefixes & PREFIX_ADDR))
12204 {
12205 if (address_mode == mode_16bit)
12206 names = names16;
12207 }
12208 else
12209 {
12210 /* Remove "addr16/addr32". */
12211 all_prefixes[last_addr_prefix] = 0;
12212 names = (address_mode != mode_32bit
12213 ? names32 : names16);
12214 used_prefixes |= PREFIX_ADDR;
12215 }
12216 oappend (names[modrm.reg + add]);
12217 break;
12218 case m_mode:
12219 if (address_mode == mode_64bit)
12220 oappend (names64[modrm.reg + add]);
12221 else
12222 oappend (names32[modrm.reg + add]);
12223 break;
12224 case mask_bd_mode:
12225 case mask_mode:
12226 if ((modrm.reg + add) > 0x7)
12227 {
12228 oappend ("(bad)");
12229 return;
12230 }
12231 oappend (names_mask[modrm.reg + add]);
12232 break;
12233 default:
12234 oappend (INTERNAL_DISASSEMBLER_ERROR);
12235 break;
12236 }
12237 }
12238
12239 static bfd_vma
12240 get64 (void)
12241 {
12242 bfd_vma x;
12243 #ifdef BFD64
12244 unsigned int a;
12245 unsigned int b;
12246
12247 FETCH_DATA (the_info, codep + 8);
12248 a = *codep++ & 0xff;
12249 a |= (*codep++ & 0xff) << 8;
12250 a |= (*codep++ & 0xff) << 16;
12251 a |= (*codep++ & 0xffu) << 24;
12252 b = *codep++ & 0xff;
12253 b |= (*codep++ & 0xff) << 8;
12254 b |= (*codep++ & 0xff) << 16;
12255 b |= (*codep++ & 0xffu) << 24;
12256 x = a + ((bfd_vma) b << 32);
12257 #else
12258 abort ();
12259 x = 0;
12260 #endif
12261 return x;
12262 }
12263
12264 static bfd_signed_vma
12265 get32 (void)
12266 {
12267 bfd_signed_vma x = 0;
12268
12269 FETCH_DATA (the_info, codep + 4);
12270 x = *codep++ & (bfd_signed_vma) 0xff;
12271 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
12272 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
12273 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
12274 return x;
12275 }
12276
12277 static bfd_signed_vma
12278 get32s (void)
12279 {
12280 bfd_signed_vma x = 0;
12281
12282 FETCH_DATA (the_info, codep + 4);
12283 x = *codep++ & (bfd_signed_vma) 0xff;
12284 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
12285 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
12286 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
12287
12288 x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
12289
12290 return x;
12291 }
12292
12293 static int
12294 get16 (void)
12295 {
12296 int x = 0;
12297
12298 FETCH_DATA (the_info, codep + 2);
12299 x = *codep++ & 0xff;
12300 x |= (*codep++ & 0xff) << 8;
12301 return x;
12302 }
12303
12304 static void
12305 set_op (bfd_vma op, int riprel)
12306 {
12307 op_index[op_ad] = op_ad;
12308 if (address_mode == mode_64bit)
12309 {
12310 op_address[op_ad] = op;
12311 op_riprel[op_ad] = riprel;
12312 }
12313 else
12314 {
12315 /* Mask to get a 32-bit address. */
12316 op_address[op_ad] = op & 0xffffffff;
12317 op_riprel[op_ad] = riprel & 0xffffffff;
12318 }
12319 }
12320
12321 static void
12322 OP_REG (int code, int sizeflag)
12323 {
12324 const char *s;
12325 int add;
12326
12327 switch (code)
12328 {
12329 case es_reg: case ss_reg: case cs_reg:
12330 case ds_reg: case fs_reg: case gs_reg:
12331 oappend (names_seg[code - es_reg]);
12332 return;
12333 }
12334
12335 USED_REX (REX_B);
12336 if (rex & REX_B)
12337 add = 8;
12338 else
12339 add = 0;
12340
12341 switch (code)
12342 {
12343 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
12344 case sp_reg: case bp_reg: case si_reg: case di_reg:
12345 s = names16[code - ax_reg + add];
12346 break;
12347 case ah_reg: case ch_reg: case dh_reg: case bh_reg:
12348 USED_REX (0);
12349 /* Fall through. */
12350 case al_reg: case cl_reg: case dl_reg: case bl_reg:
12351 if (rex)
12352 s = names8rex[code - al_reg + add];
12353 else
12354 s = names8[code - al_reg];
12355 break;
12356 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
12357 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
12358 if (address_mode == mode_64bit
12359 && ((sizeflag & DFLAG) || (rex & REX_W)))
12360 {
12361 s = names64[code - rAX_reg + add];
12362 break;
12363 }
12364 code += eAX_reg - rAX_reg;
12365 /* Fall through. */
12366 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
12367 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
12368 USED_REX (REX_W);
12369 if (rex & REX_W)
12370 s = names64[code - eAX_reg + add];
12371 else
12372 {
12373 if (sizeflag & DFLAG)
12374 s = names32[code - eAX_reg + add];
12375 else
12376 s = names16[code - eAX_reg + add];
12377 used_prefixes |= (prefixes & PREFIX_DATA);
12378 }
12379 break;
12380 default:
12381 s = INTERNAL_DISASSEMBLER_ERROR;
12382 break;
12383 }
12384 oappend (s);
12385 }
12386
12387 static void
12388 OP_IMREG (int code, int sizeflag)
12389 {
12390 const char *s;
12391
12392 switch (code)
12393 {
12394 case indir_dx_reg:
12395 if (intel_syntax)
12396 s = "dx";
12397 else
12398 s = "(%dx)";
12399 break;
12400 case al_reg: case cl_reg:
12401 s = names8[code - al_reg];
12402 break;
12403 case eAX_reg:
12404 USED_REX (REX_W);
12405 if (rex & REX_W)
12406 {
12407 s = *names64;
12408 break;
12409 }
12410 /* Fall through. */
12411 case z_mode_ax_reg:
12412 if ((rex & REX_W) || (sizeflag & DFLAG))
12413 s = *names32;
12414 else
12415 s = *names16;
12416 if (!(rex & REX_W))
12417 used_prefixes |= (prefixes & PREFIX_DATA);
12418 break;
12419 default:
12420 s = INTERNAL_DISASSEMBLER_ERROR;
12421 break;
12422 }
12423 oappend (s);
12424 }
12425
12426 static void
12427 OP_I (int bytemode, int sizeflag)
12428 {
12429 bfd_signed_vma op;
12430 bfd_signed_vma mask = -1;
12431
12432 switch (bytemode)
12433 {
12434 case b_mode:
12435 FETCH_DATA (the_info, codep + 1);
12436 op = *codep++;
12437 mask = 0xff;
12438 break;
12439 case v_mode:
12440 USED_REX (REX_W);
12441 if (rex & REX_W)
12442 op = get32s ();
12443 else
12444 {
12445 if (sizeflag & DFLAG)
12446 {
12447 op = get32 ();
12448 mask = 0xffffffff;
12449 }
12450 else
12451 {
12452 op = get16 ();
12453 mask = 0xfffff;
12454 }
12455 used_prefixes |= (prefixes & PREFIX_DATA);
12456 }
12457 break;
12458 case d_mode:
12459 mask = 0xffffffff;
12460 op = get32 ();
12461 break;
12462 case w_mode:
12463 mask = 0xfffff;
12464 op = get16 ();
12465 break;
12466 case const_1_mode:
12467 if (intel_syntax)
12468 oappend ("1");
12469 return;
12470 default:
12471 oappend (INTERNAL_DISASSEMBLER_ERROR);
12472 return;
12473 }
12474
12475 op &= mask;
12476 scratchbuf[0] = '$';
12477 print_operand_value (scratchbuf + 1, 1, op);
12478 oappend_maybe_intel (scratchbuf);
12479 scratchbuf[0] = '\0';
12480 }
12481
12482 static void
12483 OP_I64 (int bytemode, int sizeflag)
12484 {
12485 if (bytemode != v_mode || address_mode != mode_64bit || !(rex & REX_W))
12486 {
12487 OP_I (bytemode, sizeflag);
12488 return;
12489 }
12490
12491 USED_REX (REX_W);
12492
12493 scratchbuf[0] = '$';
12494 print_operand_value (scratchbuf + 1, 1, get64 ());
12495 oappend_maybe_intel (scratchbuf);
12496 scratchbuf[0] = '\0';
12497 }
12498
12499 static void
12500 OP_sI (int bytemode, int sizeflag)
12501 {
12502 bfd_signed_vma op;
12503
12504 switch (bytemode)
12505 {
12506 case b_mode:
12507 case b_T_mode:
12508 FETCH_DATA (the_info, codep + 1);
12509 op = *codep++;
12510 if ((op & 0x80) != 0)
12511 op -= 0x100;
12512 if (bytemode == b_T_mode)
12513 {
12514 if (address_mode != mode_64bit
12515 || !((sizeflag & DFLAG) || (rex & REX_W)))
12516 {
12517 /* The operand-size prefix is overridden by a REX prefix. */
12518 if ((sizeflag & DFLAG) || (rex & REX_W))
12519 op &= 0xffffffff;
12520 else
12521 op &= 0xffff;
12522 }
12523 }
12524 else
12525 {
12526 if (!(rex & REX_W))
12527 {
12528 if (sizeflag & DFLAG)
12529 op &= 0xffffffff;
12530 else
12531 op &= 0xffff;
12532 }
12533 }
12534 break;
12535 case v_mode:
12536 /* The operand-size prefix is overridden by a REX prefix. */
12537 if ((sizeflag & DFLAG) || (rex & REX_W))
12538 op = get32s ();
12539 else
12540 op = get16 ();
12541 break;
12542 default:
12543 oappend (INTERNAL_DISASSEMBLER_ERROR);
12544 return;
12545 }
12546
12547 scratchbuf[0] = '$';
12548 print_operand_value (scratchbuf + 1, 1, op);
12549 oappend_maybe_intel (scratchbuf);
12550 }
12551
12552 static void
12553 OP_J (int bytemode, int sizeflag)
12554 {
12555 bfd_vma disp;
12556 bfd_vma mask = -1;
12557 bfd_vma segment = 0;
12558
12559 switch (bytemode)
12560 {
12561 case b_mode:
12562 FETCH_DATA (the_info, codep + 1);
12563 disp = *codep++;
12564 if ((disp & 0x80) != 0)
12565 disp -= 0x100;
12566 break;
12567 case v_mode:
12568 if (isa64 != intel64)
12569 case dqw_mode:
12570 USED_REX (REX_W);
12571 if ((sizeflag & DFLAG)
12572 || (address_mode == mode_64bit
12573 && ((isa64 == intel64 && bytemode != dqw_mode)
12574 || (rex & REX_W))))
12575 disp = get32s ();
12576 else
12577 {
12578 disp = get16 ();
12579 if ((disp & 0x8000) != 0)
12580 disp -= 0x10000;
12581 /* In 16bit mode, address is wrapped around at 64k within
12582 the same segment. Otherwise, a data16 prefix on a jump
12583 instruction means that the pc is masked to 16 bits after
12584 the displacement is added! */
12585 mask = 0xffff;
12586 if ((prefixes & PREFIX_DATA) == 0)
12587 segment = ((start_pc + (codep - start_codep))
12588 & ~((bfd_vma) 0xffff));
12589 }
12590 if (address_mode != mode_64bit
12591 || (isa64 != intel64 && !(rex & REX_W)))
12592 used_prefixes |= (prefixes & PREFIX_DATA);
12593 break;
12594 default:
12595 oappend (INTERNAL_DISASSEMBLER_ERROR);
12596 return;
12597 }
12598 disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
12599 set_op (disp, 0);
12600 print_operand_value (scratchbuf, 1, disp);
12601 oappend (scratchbuf);
12602 }
12603
12604 static void
12605 OP_SEG (int bytemode, int sizeflag)
12606 {
12607 if (bytemode == w_mode)
12608 oappend (names_seg[modrm.reg]);
12609 else
12610 OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
12611 }
12612
12613 static void
12614 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
12615 {
12616 int seg, offset;
12617
12618 if (sizeflag & DFLAG)
12619 {
12620 offset = get32 ();
12621 seg = get16 ();
12622 }
12623 else
12624 {
12625 offset = get16 ();
12626 seg = get16 ();
12627 }
12628 used_prefixes |= (prefixes & PREFIX_DATA);
12629 if (intel_syntax)
12630 sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
12631 else
12632 sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
12633 oappend (scratchbuf);
12634 }
12635
12636 static void
12637 OP_OFF (int bytemode, int sizeflag)
12638 {
12639 bfd_vma off;
12640
12641 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12642 intel_operand_size (bytemode, sizeflag);
12643 append_seg ();
12644
12645 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
12646 off = get32 ();
12647 else
12648 off = get16 ();
12649
12650 if (intel_syntax)
12651 {
12652 if (!active_seg_prefix)
12653 {
12654 oappend (names_seg[ds_reg - es_reg]);
12655 oappend (":");
12656 }
12657 }
12658 print_operand_value (scratchbuf, 1, off);
12659 oappend (scratchbuf);
12660 }
12661
12662 static void
12663 OP_OFF64 (int bytemode, int sizeflag)
12664 {
12665 bfd_vma off;
12666
12667 if (address_mode != mode_64bit
12668 || (prefixes & PREFIX_ADDR))
12669 {
12670 OP_OFF (bytemode, sizeflag);
12671 return;
12672 }
12673
12674 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12675 intel_operand_size (bytemode, sizeflag);
12676 append_seg ();
12677
12678 off = get64 ();
12679
12680 if (intel_syntax)
12681 {
12682 if (!active_seg_prefix)
12683 {
12684 oappend (names_seg[ds_reg - es_reg]);
12685 oappend (":");
12686 }
12687 }
12688 print_operand_value (scratchbuf, 1, off);
12689 oappend (scratchbuf);
12690 }
12691
12692 static void
12693 ptr_reg (int code, int sizeflag)
12694 {
12695 const char *s;
12696
12697 *obufp++ = open_char;
12698 used_prefixes |= (prefixes & PREFIX_ADDR);
12699 if (address_mode == mode_64bit)
12700 {
12701 if (!(sizeflag & AFLAG))
12702 s = names32[code - eAX_reg];
12703 else
12704 s = names64[code - eAX_reg];
12705 }
12706 else if (sizeflag & AFLAG)
12707 s = names32[code - eAX_reg];
12708 else
12709 s = names16[code - eAX_reg];
12710 oappend (s);
12711 *obufp++ = close_char;
12712 *obufp = 0;
12713 }
12714
12715 static void
12716 OP_ESreg (int code, int sizeflag)
12717 {
12718 if (intel_syntax)
12719 {
12720 switch (codep[-1])
12721 {
12722 case 0x6d: /* insw/insl */
12723 intel_operand_size (z_mode, sizeflag);
12724 break;
12725 case 0xa5: /* movsw/movsl/movsq */
12726 case 0xa7: /* cmpsw/cmpsl/cmpsq */
12727 case 0xab: /* stosw/stosl */
12728 case 0xaf: /* scasw/scasl */
12729 intel_operand_size (v_mode, sizeflag);
12730 break;
12731 default:
12732 intel_operand_size (b_mode, sizeflag);
12733 }
12734 }
12735 oappend_maybe_intel ("%es:");
12736 ptr_reg (code, sizeflag);
12737 }
12738
12739 static void
12740 OP_DSreg (int code, int sizeflag)
12741 {
12742 if (intel_syntax)
12743 {
12744 switch (codep[-1])
12745 {
12746 case 0x6f: /* outsw/outsl */
12747 intel_operand_size (z_mode, sizeflag);
12748 break;
12749 case 0xa5: /* movsw/movsl/movsq */
12750 case 0xa7: /* cmpsw/cmpsl/cmpsq */
12751 case 0xad: /* lodsw/lodsl/lodsq */
12752 intel_operand_size (v_mode, sizeflag);
12753 break;
12754 default:
12755 intel_operand_size (b_mode, sizeflag);
12756 }
12757 }
12758 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
12759 default segment register DS is printed. */
12760 if (!active_seg_prefix)
12761 active_seg_prefix = PREFIX_DS;
12762 append_seg ();
12763 ptr_reg (code, sizeflag);
12764 }
12765
12766 static void
12767 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12768 {
12769 int add;
12770 if (rex & REX_R)
12771 {
12772 USED_REX (REX_R);
12773 add = 8;
12774 }
12775 else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
12776 {
12777 all_prefixes[last_lock_prefix] = 0;
12778 used_prefixes |= PREFIX_LOCK;
12779 add = 8;
12780 }
12781 else
12782 add = 0;
12783 sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
12784 oappend_maybe_intel (scratchbuf);
12785 }
12786
12787 static void
12788 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12789 {
12790 int add;
12791 USED_REX (REX_R);
12792 if (rex & REX_R)
12793 add = 8;
12794 else
12795 add = 0;
12796 if (intel_syntax)
12797 sprintf (scratchbuf, "db%d", modrm.reg + add);
12798 else
12799 sprintf (scratchbuf, "%%db%d", modrm.reg + add);
12800 oappend (scratchbuf);
12801 }
12802
12803 static void
12804 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12805 {
12806 sprintf (scratchbuf, "%%tr%d", modrm.reg);
12807 oappend_maybe_intel (scratchbuf);
12808 }
12809
12810 static void
12811 OP_R (int bytemode, int sizeflag)
12812 {
12813 /* Skip mod/rm byte. */
12814 MODRM_CHECK;
12815 codep++;
12816 OP_E_register (bytemode, sizeflag);
12817 }
12818
12819 static void
12820 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12821 {
12822 int reg = modrm.reg;
12823 const char **names;
12824
12825 used_prefixes |= (prefixes & PREFIX_DATA);
12826 if (prefixes & PREFIX_DATA)
12827 {
12828 names = names_xmm;
12829 USED_REX (REX_R);
12830 if (rex & REX_R)
12831 reg += 8;
12832 }
12833 else
12834 names = names_mm;
12835 oappend (names[reg]);
12836 }
12837
12838 static void
12839 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
12840 {
12841 int reg = modrm.reg;
12842 const char **names;
12843
12844 USED_REX (REX_R);
12845 if (rex & REX_R)
12846 reg += 8;
12847 if (vex.evex)
12848 {
12849 if (!vex.r)
12850 reg += 16;
12851 }
12852
12853 if (need_vex
12854 && bytemode != xmm_mode
12855 && bytemode != xmmq_mode
12856 && bytemode != evex_half_bcst_xmmq_mode
12857 && bytemode != ymm_mode
12858 && bytemode != tmm_mode
12859 && bytemode != scalar_mode)
12860 {
12861 switch (vex.length)
12862 {
12863 case 128:
12864 names = names_xmm;
12865 break;
12866 case 256:
12867 if (vex.w
12868 || (bytemode != vex_vsib_q_w_dq_mode
12869 && bytemode != vex_vsib_q_w_d_mode))
12870 names = names_ymm;
12871 else
12872 names = names_xmm;
12873 break;
12874 case 512:
12875 names = names_zmm;
12876 break;
12877 default:
12878 abort ();
12879 }
12880 }
12881 else if (bytemode == xmmq_mode
12882 || bytemode == evex_half_bcst_xmmq_mode)
12883 {
12884 switch (vex.length)
12885 {
12886 case 128:
12887 case 256:
12888 names = names_xmm;
12889 break;
12890 case 512:
12891 names = names_ymm;
12892 break;
12893 default:
12894 abort ();
12895 }
12896 }
12897 else if (bytemode == tmm_mode)
12898 {
12899 modrm.reg = reg;
12900 if (reg >= 8)
12901 {
12902 oappend ("(bad)");
12903 return;
12904 }
12905 names = names_tmm;
12906 }
12907 else if (bytemode == ymm_mode)
12908 names = names_ymm;
12909 else
12910 names = names_xmm;
12911 oappend (names[reg]);
12912 }
12913
12914 static void
12915 OP_EM (int bytemode, int sizeflag)
12916 {
12917 int reg;
12918 const char **names;
12919
12920 if (modrm.mod != 3)
12921 {
12922 if (intel_syntax
12923 && (bytemode == v_mode || bytemode == v_swap_mode))
12924 {
12925 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
12926 used_prefixes |= (prefixes & PREFIX_DATA);
12927 }
12928 OP_E (bytemode, sizeflag);
12929 return;
12930 }
12931
12932 if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
12933 swap_operand ();
12934
12935 /* Skip mod/rm byte. */
12936 MODRM_CHECK;
12937 codep++;
12938 used_prefixes |= (prefixes & PREFIX_DATA);
12939 reg = modrm.rm;
12940 if (prefixes & PREFIX_DATA)
12941 {
12942 names = names_xmm;
12943 USED_REX (REX_B);
12944 if (rex & REX_B)
12945 reg += 8;
12946 }
12947 else
12948 names = names_mm;
12949 oappend (names[reg]);
12950 }
12951
12952 /* cvt* are the only instructions in sse2 which have
12953 both SSE and MMX operands and also have 0x66 prefix
12954 in their opcode. 0x66 was originally used to differentiate
12955 between SSE and MMX instruction(operands). So we have to handle the
12956 cvt* separately using OP_EMC and OP_MXC */
12957 static void
12958 OP_EMC (int bytemode, int sizeflag)
12959 {
12960 if (modrm.mod != 3)
12961 {
12962 if (intel_syntax && bytemode == v_mode)
12963 {
12964 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
12965 used_prefixes |= (prefixes & PREFIX_DATA);
12966 }
12967 OP_E (bytemode, sizeflag);
12968 return;
12969 }
12970
12971 /* Skip mod/rm byte. */
12972 MODRM_CHECK;
12973 codep++;
12974 used_prefixes |= (prefixes & PREFIX_DATA);
12975 oappend (names_mm[modrm.rm]);
12976 }
12977
12978 static void
12979 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12980 {
12981 used_prefixes |= (prefixes & PREFIX_DATA);
12982 oappend (names_mm[modrm.reg]);
12983 }
12984
12985 static void
12986 OP_EX (int bytemode, int sizeflag)
12987 {
12988 int reg;
12989 const char **names;
12990
12991 /* Skip mod/rm byte. */
12992 MODRM_CHECK;
12993 codep++;
12994
12995 if (modrm.mod != 3)
12996 {
12997 OP_E_memory (bytemode, sizeflag);
12998 return;
12999 }
13000
13001 reg = modrm.rm;
13002 USED_REX (REX_B);
13003 if (rex & REX_B)
13004 reg += 8;
13005 if (vex.evex)
13006 {
13007 USED_REX (REX_X);
13008 if ((rex & REX_X))
13009 reg += 16;
13010 }
13011
13012 if ((sizeflag & SUFFIX_ALWAYS)
13013 && (bytemode == x_swap_mode
13014 || bytemode == d_swap_mode
13015 || bytemode == q_swap_mode))
13016 swap_operand ();
13017
13018 if (need_vex
13019 && bytemode != xmm_mode
13020 && bytemode != xmmdw_mode
13021 && bytemode != xmmqd_mode
13022 && bytemode != xmm_mb_mode
13023 && bytemode != xmm_mw_mode
13024 && bytemode != xmm_md_mode
13025 && bytemode != xmm_mq_mode
13026 && bytemode != xmmq_mode
13027 && bytemode != evex_half_bcst_xmmq_mode
13028 && bytemode != ymm_mode
13029 && bytemode != tmm_mode
13030 && bytemode != vex_scalar_w_dq_mode)
13031 {
13032 switch (vex.length)
13033 {
13034 case 128:
13035 names = names_xmm;
13036 break;
13037 case 256:
13038 names = names_ymm;
13039 break;
13040 case 512:
13041 names = names_zmm;
13042 break;
13043 default:
13044 abort ();
13045 }
13046 }
13047 else if (bytemode == xmmq_mode
13048 || bytemode == evex_half_bcst_xmmq_mode)
13049 {
13050 switch (vex.length)
13051 {
13052 case 128:
13053 case 256:
13054 names = names_xmm;
13055 break;
13056 case 512:
13057 names = names_ymm;
13058 break;
13059 default:
13060 abort ();
13061 }
13062 }
13063 else if (bytemode == tmm_mode)
13064 {
13065 modrm.rm = reg;
13066 if (reg >= 8)
13067 {
13068 oappend ("(bad)");
13069 return;
13070 }
13071 names = names_tmm;
13072 }
13073 else if (bytemode == ymm_mode)
13074 names = names_ymm;
13075 else
13076 names = names_xmm;
13077 oappend (names[reg]);
13078 }
13079
13080 static void
13081 OP_MS (int bytemode, int sizeflag)
13082 {
13083 if (modrm.mod == 3)
13084 OP_EM (bytemode, sizeflag);
13085 else
13086 BadOp ();
13087 }
13088
13089 static void
13090 OP_XS (int bytemode, int sizeflag)
13091 {
13092 if (modrm.mod == 3)
13093 OP_EX (bytemode, sizeflag);
13094 else
13095 BadOp ();
13096 }
13097
13098 static void
13099 OP_M (int bytemode, int sizeflag)
13100 {
13101 if (modrm.mod == 3)
13102 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
13103 BadOp ();
13104 else
13105 OP_E (bytemode, sizeflag);
13106 }
13107
13108 static void
13109 OP_0f07 (int bytemode, int sizeflag)
13110 {
13111 if (modrm.mod != 3 || modrm.rm != 0)
13112 BadOp ();
13113 else
13114 OP_E (bytemode, sizeflag);
13115 }
13116
13117 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
13118 32bit mode and "xchg %rax,%rax" in 64bit mode. */
13119
13120 static void
13121 NOP_Fixup1 (int bytemode, int sizeflag)
13122 {
13123 if ((prefixes & PREFIX_DATA) != 0
13124 || (rex != 0
13125 && rex != 0x48
13126 && address_mode == mode_64bit))
13127 OP_REG (bytemode, sizeflag);
13128 else
13129 strcpy (obuf, "nop");
13130 }
13131
13132 static void
13133 NOP_Fixup2 (int bytemode, int sizeflag)
13134 {
13135 if ((prefixes & PREFIX_DATA) != 0
13136 || (rex != 0
13137 && rex != 0x48
13138 && address_mode == mode_64bit))
13139 OP_IMREG (bytemode, sizeflag);
13140 }
13141
13142 static const char *const Suffix3DNow[] = {
13143 /* 00 */ NULL, NULL, NULL, NULL,
13144 /* 04 */ NULL, NULL, NULL, NULL,
13145 /* 08 */ NULL, NULL, NULL, NULL,
13146 /* 0C */ "pi2fw", "pi2fd", NULL, NULL,
13147 /* 10 */ NULL, NULL, NULL, NULL,
13148 /* 14 */ NULL, NULL, NULL, NULL,
13149 /* 18 */ NULL, NULL, NULL, NULL,
13150 /* 1C */ "pf2iw", "pf2id", NULL, NULL,
13151 /* 20 */ NULL, NULL, NULL, NULL,
13152 /* 24 */ NULL, NULL, NULL, NULL,
13153 /* 28 */ NULL, NULL, NULL, NULL,
13154 /* 2C */ NULL, NULL, NULL, NULL,
13155 /* 30 */ NULL, NULL, NULL, NULL,
13156 /* 34 */ NULL, NULL, NULL, NULL,
13157 /* 38 */ NULL, NULL, NULL, NULL,
13158 /* 3C */ NULL, NULL, NULL, NULL,
13159 /* 40 */ NULL, NULL, NULL, NULL,
13160 /* 44 */ NULL, NULL, NULL, NULL,
13161 /* 48 */ NULL, NULL, NULL, NULL,
13162 /* 4C */ NULL, NULL, NULL, NULL,
13163 /* 50 */ NULL, NULL, NULL, NULL,
13164 /* 54 */ NULL, NULL, NULL, NULL,
13165 /* 58 */ NULL, NULL, NULL, NULL,
13166 /* 5C */ NULL, NULL, NULL, NULL,
13167 /* 60 */ NULL, NULL, NULL, NULL,
13168 /* 64 */ NULL, NULL, NULL, NULL,
13169 /* 68 */ NULL, NULL, NULL, NULL,
13170 /* 6C */ NULL, NULL, NULL, NULL,
13171 /* 70 */ NULL, NULL, NULL, NULL,
13172 /* 74 */ NULL, NULL, NULL, NULL,
13173 /* 78 */ NULL, NULL, NULL, NULL,
13174 /* 7C */ NULL, NULL, NULL, NULL,
13175 /* 80 */ NULL, NULL, NULL, NULL,
13176 /* 84 */ NULL, NULL, NULL, NULL,
13177 /* 88 */ NULL, NULL, "pfnacc", NULL,
13178 /* 8C */ NULL, NULL, "pfpnacc", NULL,
13179 /* 90 */ "pfcmpge", NULL, NULL, NULL,
13180 /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt",
13181 /* 98 */ NULL, NULL, "pfsub", NULL,
13182 /* 9C */ NULL, NULL, "pfadd", NULL,
13183 /* A0 */ "pfcmpgt", NULL, NULL, NULL,
13184 /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1",
13185 /* A8 */ NULL, NULL, "pfsubr", NULL,
13186 /* AC */ NULL, NULL, "pfacc", NULL,
13187 /* B0 */ "pfcmpeq", NULL, NULL, NULL,
13188 /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw",
13189 /* B8 */ NULL, NULL, NULL, "pswapd",
13190 /* BC */ NULL, NULL, NULL, "pavgusb",
13191 /* C0 */ NULL, NULL, NULL, NULL,
13192 /* C4 */ NULL, NULL, NULL, NULL,
13193 /* C8 */ NULL, NULL, NULL, NULL,
13194 /* CC */ NULL, NULL, NULL, NULL,
13195 /* D0 */ NULL, NULL, NULL, NULL,
13196 /* D4 */ NULL, NULL, NULL, NULL,
13197 /* D8 */ NULL, NULL, NULL, NULL,
13198 /* DC */ NULL, NULL, NULL, NULL,
13199 /* E0 */ NULL, NULL, NULL, NULL,
13200 /* E4 */ NULL, NULL, NULL, NULL,
13201 /* E8 */ NULL, NULL, NULL, NULL,
13202 /* EC */ NULL, NULL, NULL, NULL,
13203 /* F0 */ NULL, NULL, NULL, NULL,
13204 /* F4 */ NULL, NULL, NULL, NULL,
13205 /* F8 */ NULL, NULL, NULL, NULL,
13206 /* FC */ NULL, NULL, NULL, NULL,
13207 };
13208
13209 static void
13210 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13211 {
13212 const char *mnemonic;
13213
13214 FETCH_DATA (the_info, codep + 1);
13215 /* AMD 3DNow! instructions are specified by an opcode suffix in the
13216 place where an 8-bit immediate would normally go. ie. the last
13217 byte of the instruction. */
13218 obufp = mnemonicendp;
13219 mnemonic = Suffix3DNow[*codep++ & 0xff];
13220 if (mnemonic)
13221 oappend (mnemonic);
13222 else
13223 {
13224 /* Since a variable sized modrm/sib chunk is between the start
13225 of the opcode (0x0f0f) and the opcode suffix, we need to do
13226 all the modrm processing first, and don't know until now that
13227 we have a bad opcode. This necessitates some cleaning up. */
13228 op_out[0][0] = '\0';
13229 op_out[1][0] = '\0';
13230 BadOp ();
13231 }
13232 mnemonicendp = obufp;
13233 }
13234
13235 static const struct op simd_cmp_op[] =
13236 {
13237 { STRING_COMMA_LEN ("eq") },
13238 { STRING_COMMA_LEN ("lt") },
13239 { STRING_COMMA_LEN ("le") },
13240 { STRING_COMMA_LEN ("unord") },
13241 { STRING_COMMA_LEN ("neq") },
13242 { STRING_COMMA_LEN ("nlt") },
13243 { STRING_COMMA_LEN ("nle") },
13244 { STRING_COMMA_LEN ("ord") }
13245 };
13246
13247 static const struct op vex_cmp_op[] =
13248 {
13249 { STRING_COMMA_LEN ("eq_uq") },
13250 { STRING_COMMA_LEN ("nge") },
13251 { STRING_COMMA_LEN ("ngt") },
13252 { STRING_COMMA_LEN ("false") },
13253 { STRING_COMMA_LEN ("neq_oq") },
13254 { STRING_COMMA_LEN ("ge") },
13255 { STRING_COMMA_LEN ("gt") },
13256 { STRING_COMMA_LEN ("true") },
13257 { STRING_COMMA_LEN ("eq_os") },
13258 { STRING_COMMA_LEN ("lt_oq") },
13259 { STRING_COMMA_LEN ("le_oq") },
13260 { STRING_COMMA_LEN ("unord_s") },
13261 { STRING_COMMA_LEN ("neq_us") },
13262 { STRING_COMMA_LEN ("nlt_uq") },
13263 { STRING_COMMA_LEN ("nle_uq") },
13264 { STRING_COMMA_LEN ("ord_s") },
13265 { STRING_COMMA_LEN ("eq_us") },
13266 { STRING_COMMA_LEN ("nge_uq") },
13267 { STRING_COMMA_LEN ("ngt_uq") },
13268 { STRING_COMMA_LEN ("false_os") },
13269 { STRING_COMMA_LEN ("neq_os") },
13270 { STRING_COMMA_LEN ("ge_oq") },
13271 { STRING_COMMA_LEN ("gt_oq") },
13272 { STRING_COMMA_LEN ("true_us") },
13273 };
13274
13275 static void
13276 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13277 {
13278 unsigned int cmp_type;
13279
13280 FETCH_DATA (the_info, codep + 1);
13281 cmp_type = *codep++ & 0xff;
13282 if (cmp_type < ARRAY_SIZE (simd_cmp_op))
13283 {
13284 char suffix [3];
13285 char *p = mnemonicendp - 2;
13286 suffix[0] = p[0];
13287 suffix[1] = p[1];
13288 suffix[2] = '\0';
13289 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13290 mnemonicendp += simd_cmp_op[cmp_type].len;
13291 }
13292 else if (need_vex
13293 && cmp_type < ARRAY_SIZE (simd_cmp_op) + ARRAY_SIZE (vex_cmp_op))
13294 {
13295 char suffix [3];
13296 char *p = mnemonicendp - 2;
13297 suffix[0] = p[0];
13298 suffix[1] = p[1];
13299 suffix[2] = '\0';
13300 cmp_type -= ARRAY_SIZE (simd_cmp_op);
13301 sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
13302 mnemonicendp += vex_cmp_op[cmp_type].len;
13303 }
13304 else
13305 {
13306 /* We have a reserved extension byte. Output it directly. */
13307 scratchbuf[0] = '$';
13308 print_operand_value (scratchbuf + 1, 1, cmp_type);
13309 oappend_maybe_intel (scratchbuf);
13310 scratchbuf[0] = '\0';
13311 }
13312 }
13313
13314 static void
13315 OP_Mwait (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13316 {
13317 /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx */
13318 if (!intel_syntax)
13319 {
13320 strcpy (op_out[0], names32[0]);
13321 strcpy (op_out[1], names32[1]);
13322 if (bytemode == eBX_reg)
13323 strcpy (op_out[2], names32[3]);
13324 two_source_ops = 1;
13325 }
13326 /* Skip mod/rm byte. */
13327 MODRM_CHECK;
13328 codep++;
13329 }
13330
13331 static void
13332 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
13333 int sizeflag ATTRIBUTE_UNUSED)
13334 {
13335 /* monitor %{e,r,}ax,%ecx,%edx" */
13336 if (!intel_syntax)
13337 {
13338 const char **names = (address_mode == mode_64bit
13339 ? names64 : names32);
13340
13341 if (prefixes & PREFIX_ADDR)
13342 {
13343 /* Remove "addr16/addr32". */
13344 all_prefixes[last_addr_prefix] = 0;
13345 names = (address_mode != mode_32bit
13346 ? names32 : names16);
13347 used_prefixes |= PREFIX_ADDR;
13348 }
13349 else if (address_mode == mode_16bit)
13350 names = names16;
13351 strcpy (op_out[0], names[0]);
13352 strcpy (op_out[1], names32[1]);
13353 strcpy (op_out[2], names32[2]);
13354 two_source_ops = 1;
13355 }
13356 /* Skip mod/rm byte. */
13357 MODRM_CHECK;
13358 codep++;
13359 }
13360
13361 static void
13362 BadOp (void)
13363 {
13364 /* Throw away prefixes and 1st. opcode byte. */
13365 codep = insn_codep + 1;
13366 oappend ("(bad)");
13367 }
13368
13369 static void
13370 REP_Fixup (int bytemode, int sizeflag)
13371 {
13372 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
13373 lods and stos. */
13374 if (prefixes & PREFIX_REPZ)
13375 all_prefixes[last_repz_prefix] = REP_PREFIX;
13376
13377 switch (bytemode)
13378 {
13379 case al_reg:
13380 case eAX_reg:
13381 case indir_dx_reg:
13382 OP_IMREG (bytemode, sizeflag);
13383 break;
13384 case eDI_reg:
13385 OP_ESreg (bytemode, sizeflag);
13386 break;
13387 case eSI_reg:
13388 OP_DSreg (bytemode, sizeflag);
13389 break;
13390 default:
13391 abort ();
13392 break;
13393 }
13394 }
13395
13396 static void
13397 SEP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13398 {
13399 if ( isa64 != amd64 )
13400 return;
13401
13402 obufp = obuf;
13403 BadOp ();
13404 mnemonicendp = obufp;
13405 ++codep;
13406 }
13407
13408 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
13409 "bnd". */
13410
13411 static void
13412 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13413 {
13414 if (prefixes & PREFIX_REPNZ)
13415 all_prefixes[last_repnz_prefix] = BND_PREFIX;
13416 }
13417
13418 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
13419 "notrack". */
13420
13421 static void
13422 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
13423 int sizeflag ATTRIBUTE_UNUSED)
13424 {
13425 if (active_seg_prefix == PREFIX_DS
13426 && (address_mode != mode_64bit || last_data_prefix < 0))
13427 {
13428 /* NOTRACK prefix is only valid on indirect branch instructions.
13429 NB: DATA prefix is unsupported for Intel64. */
13430 active_seg_prefix = 0;
13431 all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
13432 }
13433 }
13434
13435 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
13436 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
13437 */
13438
13439 static void
13440 HLE_Fixup1 (int bytemode, int sizeflag)
13441 {
13442 if (modrm.mod != 3
13443 && (prefixes & PREFIX_LOCK) != 0)
13444 {
13445 if (prefixes & PREFIX_REPZ)
13446 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
13447 if (prefixes & PREFIX_REPNZ)
13448 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
13449 }
13450
13451 OP_E (bytemode, sizeflag);
13452 }
13453
13454 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
13455 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
13456 */
13457
13458 static void
13459 HLE_Fixup2 (int bytemode, int sizeflag)
13460 {
13461 if (modrm.mod != 3)
13462 {
13463 if (prefixes & PREFIX_REPZ)
13464 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
13465 if (prefixes & PREFIX_REPNZ)
13466 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
13467 }
13468
13469 OP_E (bytemode, sizeflag);
13470 }
13471
13472 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
13473 "xrelease" for memory operand. No check for LOCK prefix. */
13474
13475 static void
13476 HLE_Fixup3 (int bytemode, int sizeflag)
13477 {
13478 if (modrm.mod != 3
13479 && last_repz_prefix > last_repnz_prefix
13480 && (prefixes & PREFIX_REPZ) != 0)
13481 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
13482
13483 OP_E (bytemode, sizeflag);
13484 }
13485
13486 static void
13487 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
13488 {
13489 USED_REX (REX_W);
13490 if (rex & REX_W)
13491 {
13492 /* Change cmpxchg8b to cmpxchg16b. */
13493 char *p = mnemonicendp - 2;
13494 mnemonicendp = stpcpy (p, "16b");
13495 bytemode = o_mode;
13496 }
13497 else if ((prefixes & PREFIX_LOCK) != 0)
13498 {
13499 if (prefixes & PREFIX_REPZ)
13500 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
13501 if (prefixes & PREFIX_REPNZ)
13502 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
13503 }
13504
13505 OP_M (bytemode, sizeflag);
13506 }
13507
13508 static void
13509 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
13510 {
13511 const char **names;
13512
13513 if (need_vex)
13514 {
13515 switch (vex.length)
13516 {
13517 case 128:
13518 names = names_xmm;
13519 break;
13520 case 256:
13521 names = names_ymm;
13522 break;
13523 default:
13524 abort ();
13525 }
13526 }
13527 else
13528 names = names_xmm;
13529 oappend (names[reg]);
13530 }
13531
13532 static void
13533 FXSAVE_Fixup (int bytemode, int sizeflag)
13534 {
13535 /* Add proper suffix to "fxsave" and "fxrstor". */
13536 USED_REX (REX_W);
13537 if (rex & REX_W)
13538 {
13539 char *p = mnemonicendp;
13540 *p++ = '6';
13541 *p++ = '4';
13542 *p = '\0';
13543 mnemonicendp = p;
13544 }
13545 OP_M (bytemode, sizeflag);
13546 }
13547
13548 /* Display the destination register operand for instructions with
13549 VEX. */
13550
13551 static void
13552 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13553 {
13554 int reg;
13555 const char **names;
13556
13557 if (!need_vex)
13558 abort ();
13559
13560 reg = vex.register_specifier;
13561 vex.register_specifier = 0;
13562 if (address_mode != mode_64bit)
13563 reg &= 7;
13564 else if (vex.evex && !vex.v)
13565 reg += 16;
13566
13567 if (bytemode == vex_scalar_mode)
13568 {
13569 oappend (names_xmm[reg]);
13570 return;
13571 }
13572
13573 if (bytemode == tmm_mode)
13574 {
13575 /* All 3 TMM registers must be distinct. */
13576 if (reg >= 8)
13577 oappend ("(bad)");
13578 else
13579 {
13580 /* This must be the 3rd operand. */
13581 if (obufp != op_out[2])
13582 abort ();
13583 oappend (names_tmm[reg]);
13584 if (reg == modrm.reg || reg == modrm.rm)
13585 strcpy (obufp, "/(bad)");
13586 }
13587
13588 if (modrm.reg == modrm.rm || modrm.reg == reg || modrm.rm == reg)
13589 {
13590 if (modrm.reg <= 8
13591 && (modrm.reg == modrm.rm || modrm.reg == reg))
13592 strcat (op_out[0], "/(bad)");
13593 if (modrm.rm <= 8
13594 && (modrm.rm == modrm.reg || modrm.rm == reg))
13595 strcat (op_out[1], "/(bad)");
13596 }
13597
13598 return;
13599 }
13600
13601 switch (vex.length)
13602 {
13603 case 128:
13604 switch (bytemode)
13605 {
13606 case vex_mode:
13607 case vex_vsib_q_w_dq_mode:
13608 case vex_vsib_q_w_d_mode:
13609 names = names_xmm;
13610 break;
13611 case dq_mode:
13612 if (rex & REX_W)
13613 names = names64;
13614 else
13615 names = names32;
13616 break;
13617 case mask_bd_mode:
13618 case mask_mode:
13619 if (reg > 0x7)
13620 {
13621 oappend ("(bad)");
13622 return;
13623 }
13624 names = names_mask;
13625 break;
13626 default:
13627 abort ();
13628 return;
13629 }
13630 break;
13631 case 256:
13632 switch (bytemode)
13633 {
13634 case vex_mode:
13635 names = names_ymm;
13636 break;
13637 case vex_vsib_q_w_dq_mode:
13638 case vex_vsib_q_w_d_mode:
13639 names = vex.w ? names_ymm : names_xmm;
13640 break;
13641 case mask_bd_mode:
13642 case mask_mode:
13643 if (reg > 0x7)
13644 {
13645 oappend ("(bad)");
13646 return;
13647 }
13648 names = names_mask;
13649 break;
13650 default:
13651 /* See PR binutils/20893 for a reproducer. */
13652 oappend ("(bad)");
13653 return;
13654 }
13655 break;
13656 case 512:
13657 names = names_zmm;
13658 break;
13659 default:
13660 abort ();
13661 break;
13662 }
13663 oappend (names[reg]);
13664 }
13665
13666 static void
13667 OP_VexR (int bytemode, int sizeflag)
13668 {
13669 if (modrm.mod == 3)
13670 OP_VEX (bytemode, sizeflag);
13671 }
13672
13673 static void
13674 OP_VexW (int bytemode, int sizeflag)
13675 {
13676 OP_VEX (bytemode, sizeflag);
13677
13678 if (vex.w)
13679 {
13680 /* Swap 2nd and 3rd operands. */
13681 strcpy (scratchbuf, op_out[2]);
13682 strcpy (op_out[2], op_out[1]);
13683 strcpy (op_out[1], scratchbuf);
13684 }
13685 }
13686
13687 static void
13688 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13689 {
13690 int reg;
13691 const char **names = names_xmm;
13692
13693 FETCH_DATA (the_info, codep + 1);
13694 reg = *codep++;
13695
13696 if (bytemode != x_mode && bytemode != scalar_mode)
13697 abort ();
13698
13699 reg >>= 4;
13700 if (address_mode != mode_64bit)
13701 reg &= 7;
13702
13703 if (bytemode == x_mode && vex.length == 256)
13704 names = names_ymm;
13705
13706 oappend (names[reg]);
13707
13708 if (vex.w)
13709 {
13710 /* Swap 3rd and 4th operands. */
13711 strcpy (scratchbuf, op_out[3]);
13712 strcpy (op_out[3], op_out[2]);
13713 strcpy (op_out[2], scratchbuf);
13714 }
13715 }
13716
13717 static void
13718 OP_VexI4 (int bytemode ATTRIBUTE_UNUSED,
13719 int sizeflag ATTRIBUTE_UNUSED)
13720 {
13721 scratchbuf[0] = '$';
13722 print_operand_value (scratchbuf + 1, 1, codep[-1] & 0xf);
13723 oappend_maybe_intel (scratchbuf);
13724 }
13725
13726 static void
13727 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
13728 int sizeflag ATTRIBUTE_UNUSED)
13729 {
13730 unsigned int cmp_type;
13731
13732 if (!vex.evex)
13733 abort ();
13734
13735 FETCH_DATA (the_info, codep + 1);
13736 cmp_type = *codep++ & 0xff;
13737 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
13738 If it's the case, print suffix, otherwise - print the immediate. */
13739 if (cmp_type < ARRAY_SIZE (simd_cmp_op)
13740 && cmp_type != 3
13741 && cmp_type != 7)
13742 {
13743 char suffix [3];
13744 char *p = mnemonicendp - 2;
13745
13746 /* vpcmp* can have both one- and two-lettered suffix. */
13747 if (p[0] == 'p')
13748 {
13749 p++;
13750 suffix[0] = p[0];
13751 suffix[1] = '\0';
13752 }
13753 else
13754 {
13755 suffix[0] = p[0];
13756 suffix[1] = p[1];
13757 suffix[2] = '\0';
13758 }
13759
13760 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13761 mnemonicendp += simd_cmp_op[cmp_type].len;
13762 }
13763 else
13764 {
13765 /* We have a reserved extension byte. Output it directly. */
13766 scratchbuf[0] = '$';
13767 print_operand_value (scratchbuf + 1, 1, cmp_type);
13768 oappend_maybe_intel (scratchbuf);
13769 scratchbuf[0] = '\0';
13770 }
13771 }
13772
13773 static const struct op xop_cmp_op[] =
13774 {
13775 { STRING_COMMA_LEN ("lt") },
13776 { STRING_COMMA_LEN ("le") },
13777 { STRING_COMMA_LEN ("gt") },
13778 { STRING_COMMA_LEN ("ge") },
13779 { STRING_COMMA_LEN ("eq") },
13780 { STRING_COMMA_LEN ("neq") },
13781 { STRING_COMMA_LEN ("false") },
13782 { STRING_COMMA_LEN ("true") }
13783 };
13784
13785 static void
13786 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
13787 int sizeflag ATTRIBUTE_UNUSED)
13788 {
13789 unsigned int cmp_type;
13790
13791 FETCH_DATA (the_info, codep + 1);
13792 cmp_type = *codep++ & 0xff;
13793 if (cmp_type < ARRAY_SIZE (xop_cmp_op))
13794 {
13795 char suffix[3];
13796 char *p = mnemonicendp - 2;
13797
13798 /* vpcom* can have both one- and two-lettered suffix. */
13799 if (p[0] == 'm')
13800 {
13801 p++;
13802 suffix[0] = p[0];
13803 suffix[1] = '\0';
13804 }
13805 else
13806 {
13807 suffix[0] = p[0];
13808 suffix[1] = p[1];
13809 suffix[2] = '\0';
13810 }
13811
13812 sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
13813 mnemonicendp += xop_cmp_op[cmp_type].len;
13814 }
13815 else
13816 {
13817 /* We have a reserved extension byte. Output it directly. */
13818 scratchbuf[0] = '$';
13819 print_operand_value (scratchbuf + 1, 1, cmp_type);
13820 oappend_maybe_intel (scratchbuf);
13821 scratchbuf[0] = '\0';
13822 }
13823 }
13824
13825 static const struct op pclmul_op[] =
13826 {
13827 { STRING_COMMA_LEN ("lql") },
13828 { STRING_COMMA_LEN ("hql") },
13829 { STRING_COMMA_LEN ("lqh") },
13830 { STRING_COMMA_LEN ("hqh") }
13831 };
13832
13833 static void
13834 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
13835 int sizeflag ATTRIBUTE_UNUSED)
13836 {
13837 unsigned int pclmul_type;
13838
13839 FETCH_DATA (the_info, codep + 1);
13840 pclmul_type = *codep++ & 0xff;
13841 switch (pclmul_type)
13842 {
13843 case 0x10:
13844 pclmul_type = 2;
13845 break;
13846 case 0x11:
13847 pclmul_type = 3;
13848 break;
13849 default:
13850 break;
13851 }
13852 if (pclmul_type < ARRAY_SIZE (pclmul_op))
13853 {
13854 char suffix [4];
13855 char *p = mnemonicendp - 3;
13856 suffix[0] = p[0];
13857 suffix[1] = p[1];
13858 suffix[2] = p[2];
13859 suffix[3] = '\0';
13860 sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
13861 mnemonicendp += pclmul_op[pclmul_type].len;
13862 }
13863 else
13864 {
13865 /* We have a reserved extension byte. Output it directly. */
13866 scratchbuf[0] = '$';
13867 print_operand_value (scratchbuf + 1, 1, pclmul_type);
13868 oappend_maybe_intel (scratchbuf);
13869 scratchbuf[0] = '\0';
13870 }
13871 }
13872
13873 static void
13874 MOVSXD_Fixup (int bytemode, int sizeflag)
13875 {
13876 /* Add proper suffix to "movsxd". */
13877 char *p = mnemonicendp;
13878
13879 switch (bytemode)
13880 {
13881 case movsxd_mode:
13882 if (intel_syntax)
13883 {
13884 *p++ = 'x';
13885 *p++ = 'd';
13886 goto skip;
13887 }
13888
13889 USED_REX (REX_W);
13890 if (rex & REX_W)
13891 {
13892 *p++ = 'l';
13893 *p++ = 'q';
13894 }
13895 else
13896 {
13897 *p++ = 'x';
13898 *p++ = 'd';
13899 }
13900 break;
13901 default:
13902 oappend (INTERNAL_DISASSEMBLER_ERROR);
13903 break;
13904 }
13905
13906 skip:
13907 mnemonicendp = p;
13908 *p = '\0';
13909 OP_E (bytemode, sizeflag);
13910 }
13911
13912 static void
13913 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13914 {
13915 if (!vex.evex
13916 || (bytemode != mask_mode && bytemode != mask_bd_mode))
13917 abort ();
13918
13919 USED_REX (REX_R);
13920 if ((rex & REX_R) != 0 || !vex.r)
13921 {
13922 BadOp ();
13923 return;
13924 }
13925
13926 oappend (names_mask [modrm.reg]);
13927 }
13928
13929 static void
13930 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13931 {
13932 if (modrm.mod == 3 && vex.b)
13933 switch (bytemode)
13934 {
13935 case evex_rounding_64_mode:
13936 if (address_mode != mode_64bit)
13937 {
13938 oappend ("(bad)");
13939 break;
13940 }
13941 /* Fall through. */
13942 case evex_rounding_mode:
13943 oappend (names_rounding[vex.ll]);
13944 break;
13945 case evex_sae_mode:
13946 oappend ("{sae}");
13947 break;
13948 default:
13949 abort ();
13950 break;
13951 }
13952 }