opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2020 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "disassemble.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40 #include "safe-ctype.h"
  41
  42 #include <setjmp.h>
  43
  44 static int print_insn (bfd_vma, disassemble_info *);
  45 static void dofloat (int);
  46 static void OP_ST (int, int);
  47 static void OP_STi (int, int);
  48 static int putop (const char *, int);
  49 static void oappend (const char *);
  50 static void append_seg (void);
  51 static void OP_indirE (int, int);
  52 static void print_operand_value (char *, int, bfd_vma);
  53 static void OP_E_register (int, int);
  54 static void OP_E_memory (int, int);
  55 static void print_displacement (char *, bfd_vma);
  56 static void OP_E (int, int);
  57 static void OP_G (int, int);
  58 static bfd_vma get64 (void);
  59 static bfd_signed_vma get32 (void);
  60 static bfd_signed_vma get32s (void);
  61 static int get16 (void);
  62 static void set_op (bfd_vma, int);
  63 static void OP_Skip_MODRM (int, int);
  64 static void OP_REG (int, int);
  65 static void OP_IMREG (int, int);
  66 static void OP_I (int, int);
  67 static void OP_I64 (int, int);
  68 static void OP_sI (int, int);
  69 static void OP_J (int, int);
  70 static void OP_SEG (int, int);
  71 static void OP_DIR (int, int);
  72 static void OP_OFF (int, int);
  73 static void OP_OFF64 (int, int);
  74 static void ptr_reg (int, int);
  75 static void OP_ESreg (int, int);
  76 static void OP_DSreg (int, int);
  77 static void OP_C (int, int);
  78 static void OP_D (int, int);
  79 static void OP_T (int, int);
  80 static void OP_MMX (int, int);
  81 static void OP_XMM (int, int);
  82 static void OP_EM (int, int);
  83 static void OP_EX (int, int);
  84 static void OP_EMC (int,int);
  85 static void OP_MXC (int,int);
  86 static void OP_MS (int, int);
  87 static void OP_XS (int, int);
  88 static void OP_M (int, int);
  89 static void OP_VEX (int, int);
  90 static void OP_VexR (int, int);
  91 static void OP_VexW (int, int);
  92 static void OP_Rounding (int, int);
  93 static void OP_REG_VexI4 (int, int);
  94 static void OP_VexI4 (int, int);
  95 static void PCLMUL_Fixup (int, int);
  96 static void VPCMP_Fixup (int, int);
  97 static void VPCOM_Fixup (int, int);
  98 static void OP_0f07 (int, int);
  99 static void OP_Monitor (int, int);
 100 static void OP_Mwait (int, int);
 101 static void NOP_Fixup1 (int, int);
 102 static void NOP_Fixup2 (int, int);
 103 static void OP_3DNowSuffix (int, int);
 104 static void CMP_Fixup (int, int);
 105 static void BadOp (void);
 106 static void REP_Fixup (int, int);
 107 static void SEP_Fixup (int, int);
 108 static void BND_Fixup (int, int);
 109 static void NOTRACK_Fixup (int, int);
 110 static void HLE_Fixup1 (int, int);
 111 static void HLE_Fixup2 (int, int);
 112 static void HLE_Fixup3 (int, int);
 113 static void CMPXCHG8B_Fixup (int, int);
 114 static void XMM_Fixup (int, int);
 115 static void FXSAVE_Fixup (int, int);
 116
 117 static void MOVSXD_Fixup (int, int);
 118
 119 static void OP_Mask (int, int);
 120
 121 struct dis_private {
 122   /* Points to first byte not fetched.  */
 123   bfd_byte *max_fetched;
 124   bfd_byte the_buffer[MAX_MNEM_SIZE];
 125   bfd_vma insn_start;
 126   int orig_sizeflag;
 127   OPCODES_SIGJMP_BUF bailout;
 128 };
 129
 130 enum address_mode
 131 {
 132   mode_16bit,
 133   mode_32bit,
 134   mode_64bit
 135 };
 136
 137 enum address_mode address_mode;
 138
 139 /* Flags for the prefixes for the current instruction.  See below.  */
 140 static int prefixes;
 141
 142 /* REX prefix the current instruction.  See below.  */
 143 static int rex;
 144 /* Bits of REX we've already used.  */
 145 static int rex_used;
 146 /* Mark parts used in the REX prefix.  When we are testing for
 147    empty prefix (for 8bit register REX extension), just mask it
 148    out.  Otherwise test for REX bit is excuse for existence of REX
 149    only in case value is nonzero.  */
 150 #define USED_REX(value)                                 \
 151   {                                                     \
 152     if (value)                                          \
 153       {                                                 \
 154         if ((rex & value))                              \
 155           rex_used |= (value) | REX_OPCODE;             \
 156       }                                                 \
 157     else                                                \
 158       rex_used |= REX_OPCODE;                           \
 159   }
 160
 161 /* Flags for prefixes which we somehow handled when printing the
 162    current instruction.  */
 163 static int used_prefixes;
 164
 165 /* Flags stored in PREFIXES.  */
 166 #define PREFIX_REPZ 1
 167 #define PREFIX_REPNZ 2
 168 #define PREFIX_LOCK 4
 169 #define PREFIX_CS 8
 170 #define PREFIX_SS 0x10
 171 #define PREFIX_DS 0x20
 172 #define PREFIX_ES 0x40
 173 #define PREFIX_FS 0x80
 174 #define PREFIX_GS 0x100
 175 #define PREFIX_DATA 0x200
 176 #define PREFIX_ADDR 0x400
 177 #define PREFIX_FWAIT 0x800
 178
 179 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 180    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 181    on error.  */
 182 #define FETCH_DATA(info, addr) \
 183   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 184    ? 1 : fetch_data ((info), (addr)))
 185
 186 static int
 187 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 188 {
 189   int status;
 190   struct dis_private *priv = (struct dis_private *) info->private_data;
 191   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 192
 193   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 194     status = (*info->read_memory_func) (start,
 195                                         priv->max_fetched,
 196                                         addr - priv->max_fetched,
 197                                         info);
 198   else
 199     status = -1;
 200   if (status != 0)
 201     {
 202       /* If we did manage to read at least one byte, then
 203          print_insn_i386 will do something sensible.  Otherwise, print
 204          an error.  We do that here because this is where we know
 205          STATUS.  */
 206       if (priv->max_fetched == priv->the_buffer)
 207         (*info->memory_error_func) (status, start, info);
 208       OPCODES_SIGLONGJMP (priv->bailout, 1);
 209     }
 210   else
 211     priv->max_fetched = addr;
 212   return 1;
 213 }
 214
 215 /* Possible values for prefix requirement.  */
 216 #define PREFIX_IGNORED_SHIFT    16
 217 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 218 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 219 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 220 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 221 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 222
 223 /* Opcode prefixes.  */
 224 #define PREFIX_OPCODE           (PREFIX_REPZ \
 225                                  | PREFIX_REPNZ \
 226                                  | PREFIX_DATA)
 227
 228 /* Prefixes ignored.  */
 229 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 230                                  | PREFIX_IGNORED_REPNZ \
 231                                  | PREFIX_IGNORED_DATA)
 232
 233 #define XX { NULL, 0 }
 234 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 235
 236 #define Eb { OP_E, b_mode }
 237 #define Ebnd { OP_E, bnd_mode }
 238 #define EbS { OP_E, b_swap_mode }
 239 #define EbndS { OP_E, bnd_swap_mode }
 240 #define Ev { OP_E, v_mode }
 241 #define Eva { OP_E, va_mode }
 242 #define Ev_bnd { OP_E, v_bnd_mode }
 243 #define EvS { OP_E, v_swap_mode }
 244 #define Ed { OP_E, d_mode }
 245 #define Edq { OP_E, dq_mode }
 246 #define Edqw { OP_E, dqw_mode }
 247 #define Edqb { OP_E, dqb_mode }
 248 #define Edb { OP_E, db_mode }
 249 #define Edw { OP_E, dw_mode }
 250 #define Edqd { OP_E, dqd_mode }
 251 #define Eq { OP_E, q_mode }
 252 #define indirEv { OP_indirE, indir_v_mode }
 253 #define indirEp { OP_indirE, f_mode }
 254 #define stackEv { OP_E, stack_v_mode }
 255 #define Em { OP_E, m_mode }
 256 #define Ew { OP_E, w_mode }
 257 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 258 #define Ma { OP_M, a_mode }
 259 #define Mb { OP_M, b_mode }
 260 #define Md { OP_M, d_mode }
 261 #define Mo { OP_M, o_mode }
 262 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 263 #define Mq { OP_M, q_mode }
 264 #define Mv { OP_M, v_mode }
 265 #define Mv_bnd { OP_M, v_bndmk_mode }
 266 #define Mx { OP_M, x_mode }
 267 #define Mxmm { OP_M, xmm_mode }
 268 #define Gb { OP_G, b_mode }
 269 #define Gbnd { OP_G, bnd_mode }
 270 #define Gv { OP_G, v_mode }
 271 #define Gd { OP_G, d_mode }
 272 #define Gdq { OP_G, dq_mode }
 273 #define Gm { OP_G, m_mode }
 274 #define Gva { OP_G, va_mode }
 275 #define Gw { OP_G, w_mode }
 276 #define Ib { OP_I, b_mode }
 277 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 278 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 279 #define Iv { OP_I, v_mode }
 280 #define sIv { OP_sI, v_mode }
 281 #define Iv64 { OP_I64, v_mode }
 282 #define Id { OP_I, d_mode }
 283 #define Iw { OP_I, w_mode }
 284 #define I1 { OP_I, const_1_mode }
 285 #define Jb { OP_J, b_mode }
 286 #define Jv { OP_J, v_mode }
 287 #define Jdqw { OP_J, dqw_mode }
 288 #define Cm { OP_C, m_mode }
 289 #define Dm { OP_D, m_mode }
 290 #define Td { OP_T, d_mode }
 291 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 292
 293 #define RMeAX { OP_REG, eAX_reg }
 294 #define RMeBX { OP_REG, eBX_reg }
 295 #define RMeCX { OP_REG, eCX_reg }
 296 #define RMeDX { OP_REG, eDX_reg }
 297 #define RMeSP { OP_REG, eSP_reg }
 298 #define RMeBP { OP_REG, eBP_reg }
 299 #define RMeSI { OP_REG, eSI_reg }
 300 #define RMeDI { OP_REG, eDI_reg }
 301 #define RMrAX { OP_REG, rAX_reg }
 302 #define RMrBX { OP_REG, rBX_reg }
 303 #define RMrCX { OP_REG, rCX_reg }
 304 #define RMrDX { OP_REG, rDX_reg }
 305 #define RMrSP { OP_REG, rSP_reg }
 306 #define RMrBP { OP_REG, rBP_reg }
 307 #define RMrSI { OP_REG, rSI_reg }
 308 #define RMrDI { OP_REG, rDI_reg }
 309 #define RMAL { OP_REG, al_reg }
 310 #define RMCL { OP_REG, cl_reg }
 311 #define RMDL { OP_REG, dl_reg }
 312 #define RMBL { OP_REG, bl_reg }
 313 #define RMAH { OP_REG, ah_reg }
 314 #define RMCH { OP_REG, ch_reg }
 315 #define RMDH { OP_REG, dh_reg }
 316 #define RMBH { OP_REG, bh_reg }
 317 #define RMAX { OP_REG, ax_reg }
 318 #define RMDX { OP_REG, dx_reg }
 319
 320 #define eAX { OP_IMREG, eAX_reg }
 321 #define AL { OP_IMREG, al_reg }
 322 #define CL { OP_IMREG, cl_reg }
 323 #define zAX { OP_IMREG, z_mode_ax_reg }
 324 #define indirDX { OP_IMREG, indir_dx_reg }
 325
 326 #define Sw { OP_SEG, w_mode }
 327 #define Sv { OP_SEG, v_mode }
 328 #define Ap { OP_DIR, 0 }
 329 #define Ob { OP_OFF64, b_mode }
 330 #define Ov { OP_OFF64, v_mode }
 331 #define Xb { OP_DSreg, eSI_reg }
 332 #define Xv { OP_DSreg, eSI_reg }
 333 #define Xz { OP_DSreg, eSI_reg }
 334 #define Yb { OP_ESreg, eDI_reg }
 335 #define Yv { OP_ESreg, eDI_reg }
 336 #define DSBX { OP_DSreg, eBX_reg }
 337
 338 #define es { OP_REG, es_reg }
 339 #define ss { OP_REG, ss_reg }
 340 #define cs { OP_REG, cs_reg }
 341 #define ds { OP_REG, ds_reg }
 342 #define fs { OP_REG, fs_reg }
 343 #define gs { OP_REG, gs_reg }
 344
 345 #define MX { OP_MMX, 0 }
 346 #define XM { OP_XMM, 0 }
 347 #define XMScalar { OP_XMM, scalar_mode }
 348 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 349 #define XMM { OP_XMM, xmm_mode }
 350 #define TMM { OP_XMM, tmm_mode }
 351 #define XMxmmq { OP_XMM, xmmq_mode }
 352 #define EM { OP_EM, v_mode }
 353 #define EMS { OP_EM, v_swap_mode }
 354 #define EMd { OP_EM, d_mode }
 355 #define EMx { OP_EM, x_mode }
 356 #define EXbwUnit { OP_EX, bw_unit_mode }
 357 #define EXw { OP_EX, w_mode }
 358 #define EXd { OP_EX, d_mode }
 359 #define EXdS { OP_EX, d_swap_mode }
 360 #define EXq { OP_EX, q_mode }
 361 #define EXqS { OP_EX, q_swap_mode }
 362 #define EXx { OP_EX, x_mode }
 363 #define EXxS { OP_EX, x_swap_mode }
 364 #define EXxmm { OP_EX, xmm_mode }
 365 #define EXymm { OP_EX, ymm_mode }
 366 #define EXtmm { OP_EX, tmm_mode }
 367 #define EXxmmq { OP_EX, xmmq_mode }
 368 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 369 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 370 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 371 #define EXxmm_md { OP_EX, xmm_md_mode }
 372 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 373 #define EXxmmdw { OP_EX, xmmdw_mode }
 374 #define EXxmmqd { OP_EX, xmmqd_mode }
 375 #define EXymmq { OP_EX, ymmq_mode }
 376 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 377 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 378 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 379 #define MS { OP_MS, v_mode }
 380 #define XS { OP_XS, v_mode }
 381 #define EMCq { OP_EMC, q_mode }
 382 #define MXC { OP_MXC, 0 }
 383 #define OPSUF { OP_3DNowSuffix, 0 }
 384 #define SEP { SEP_Fixup, 0 }
 385 #define CMP { CMP_Fixup, 0 }
 386 #define XMM0 { XMM_Fixup, 0 }
 387 #define FXSAVE { FXSAVE_Fixup, 0 }
 388
 389 #define Vex { OP_VEX, vex_mode }
 390 #define VexW { OP_VexW, vex_mode }
 391 #define VexScalar { OP_VEX, vex_scalar_mode }
 392 #define VexScalarR { OP_VexR, vex_scalar_mode }
 393 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 394 #define VexGdq { OP_VEX, dq_mode }
 395 #define VexTmm { OP_VEX, tmm_mode }
 396 #define XMVexI4 { OP_REG_VexI4, x_mode }
 397 #define XMVexScalarI4 { OP_REG_VexI4, scalar_mode }
 398 #define VexI4 { OP_VexI4, 0 }
 399 #define PCLMUL { PCLMUL_Fixup, 0 }
 400 #define VPCMP { VPCMP_Fixup, 0 }
 401 #define VPCOM { VPCOM_Fixup, 0 }
 402
 403 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 404 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
 405 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 406
 407 #define XMask { OP_Mask, mask_mode }
 408 #define MaskG { OP_G, mask_mode }
 409 #define MaskE { OP_E, mask_mode }
 410 #define MaskBDE { OP_E, mask_bd_mode }
 411 #define MaskVex { OP_VEX, mask_mode }
 412
 413 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 414 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 415 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 416 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 417
 418 #define MVexSIBMEM { OP_M, vex_sibmem_mode }
 419
 420 /* Used handle "rep" prefix for string instructions.  */
 421 #define Xbr { REP_Fixup, eSI_reg }
 422 #define Xvr { REP_Fixup, eSI_reg }
 423 #define Ybr { REP_Fixup, eDI_reg }
 424 #define Yvr { REP_Fixup, eDI_reg }
 425 #define Yzr { REP_Fixup, eDI_reg }
 426 #define indirDXr { REP_Fixup, indir_dx_reg }
 427 #define ALr { REP_Fixup, al_reg }
 428 #define eAXr { REP_Fixup, eAX_reg }
 429
 430 /* Used handle HLE prefix for lockable instructions.  */
 431 #define Ebh1 { HLE_Fixup1, b_mode }
 432 #define Evh1 { HLE_Fixup1, v_mode }
 433 #define Ebh2 { HLE_Fixup2, b_mode }
 434 #define Evh2 { HLE_Fixup2, v_mode }
 435 #define Ebh3 { HLE_Fixup3, b_mode }
 436 #define Evh3 { HLE_Fixup3, v_mode }
 437
 438 #define BND { BND_Fixup, 0 }
 439 #define NOTRACK { NOTRACK_Fixup, 0 }
 440
 441 #define cond_jump_flag { NULL, cond_jump_mode }
 442 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 443
 444 /* bits in sizeflag */
 445 #define SUFFIX_ALWAYS 4
 446 #define AFLAG 2
 447 #define DFLAG 1
 448
 449 enum
 450 {
 451   /* byte operand */
 452   b_mode = 1,
 453   /* byte operand with operand swapped */
 454   b_swap_mode,
 455   /* byte operand, sign extend like 'T' suffix */
 456   b_T_mode,
 457   /* operand size depends on prefixes */
 458   v_mode,
 459   /* operand size depends on prefixes with operand swapped */
 460   v_swap_mode,
 461   /* operand size depends on address prefix */
 462   va_mode,
 463   /* word operand */
 464   w_mode,
 465   /* double word operand  */
 466   d_mode,
 467   /* double word operand with operand swapped */
 468   d_swap_mode,
 469   /* quad word operand */
 470   q_mode,
 471   /* quad word operand with operand swapped */
 472   q_swap_mode,
 473   /* ten-byte operand */
 474   t_mode,
 475   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 476      broadcast enabled.  */
 477   x_mode,
 478   /* Similar to x_mode, but with different EVEX mem shifts.  */
 479   evex_x_gscat_mode,
 480   /* Similar to x_mode, but with yet different EVEX mem shifts.  */
 481   bw_unit_mode,
 482   /* Similar to x_mode, but with disabled broadcast.  */
 483   evex_x_nobcst_mode,
 484   /* Similar to x_mode, but with operands swapped and disabled broadcast
 485      in EVEX.  */
 486   x_swap_mode,
 487   /* 16-byte XMM operand */
 488   xmm_mode,
 489   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 490      memory operand (depending on vector length).  Broadcast isn't
 491      allowed.  */
 492   xmmq_mode,
 493   /* Same as xmmq_mode, but broadcast is allowed.  */
 494   evex_half_bcst_xmmq_mode,
 495   /* XMM register or byte memory operand */
 496   xmm_mb_mode,
 497   /* XMM register or word memory operand */
 498   xmm_mw_mode,
 499   /* XMM register or double word memory operand */
 500   xmm_md_mode,
 501   /* XMM register or quad word memory operand */
 502   xmm_mq_mode,
 503   /* 16-byte XMM, word, double word or quad word operand.  */
 504   xmmdw_mode,
 505   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 506   xmmqd_mode,
 507   /* 32-byte YMM operand */
 508   ymm_mode,
 509   /* quad word, ymmword or zmmword memory operand.  */
 510   ymmq_mode,
 511   /* 32-byte YMM or 16-byte word operand */
 512   ymmxmm_mode,
 513   /* TMM operand */
 514   tmm_mode,
 515   /* d_mode in 32bit, q_mode in 64bit mode.  */
 516   m_mode,
 517   /* pair of v_mode operands */
 518   a_mode,
 519   cond_jump_mode,
 520   loop_jcxz_mode,
 521   movsxd_mode,
 522   v_bnd_mode,
 523   /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode.  */
 524   v_bndmk_mode,
 525   /* operand size depends on REX prefixes.  */
 526   dq_mode,
 527   /* registers like dq_mode, memory like w_mode, displacements like
 528      v_mode without considering Intel64 ISA.  */
 529   dqw_mode,
 530   /* bounds operand */
 531   bnd_mode,
 532   /* bounds operand with operand swapped */
 533   bnd_swap_mode,
 534   /* 4- or 6-byte pointer operand */
 535   f_mode,
 536   const_1_mode,
 537   /* v_mode for indirect branch opcodes.  */
 538   indir_v_mode,
 539   /* v_mode for stack-related opcodes.  */
 540   stack_v_mode,
 541   /* non-quad operand size depends on prefixes */
 542   z_mode,
 543   /* 16-byte operand */
 544   o_mode,
 545   /* registers like dq_mode, memory like b_mode.  */
 546   dqb_mode,
 547   /* registers like d_mode, memory like b_mode.  */
 548   db_mode,
 549   /* registers like d_mode, memory like w_mode.  */
 550   dw_mode,
 551   /* registers like dq_mode, memory like d_mode.  */
 552   dqd_mode,
 553   /* normal vex mode */
 554   vex_mode,
 555
 556   /* Operand size depends on the VEX.W bit, with VSIB dword indices.  */
 557   vex_vsib_d_w_dq_mode,
 558   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 559   vex_vsib_d_w_d_mode,
 560   /* Operand size depends on the VEX.W bit, with VSIB qword indices.  */
 561   vex_vsib_q_w_dq_mode,
 562   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 563   vex_vsib_q_w_d_mode,
 564   /* mandatory non-vector SIB.  */
 565   vex_sibmem_mode,
 566
 567   /* scalar, ignore vector length.  */
 568   scalar_mode,
 569   /* like vex_mode, ignore vector length.  */
 570   vex_scalar_mode,
 571   /* Operand size depends on the VEX.W bit, ignore vector length.  */
 572   vex_scalar_w_dq_mode,
 573
 574   /* Static rounding.  */
 575   evex_rounding_mode,
 576   /* Static rounding, 64-bit mode only.  */
 577   evex_rounding_64_mode,
 578   /* Supress all exceptions.  */
 579   evex_sae_mode,
 580
 581   /* Mask register operand.  */
 582   mask_mode,
 583   /* Mask register operand.  */
 584   mask_bd_mode,
 585
 586   es_reg,
 587   cs_reg,
 588   ss_reg,
 589   ds_reg,
 590   fs_reg,
 591   gs_reg,
 592
 593   eAX_reg,
 594   eCX_reg,
 595   eDX_reg,
 596   eBX_reg,
 597   eSP_reg,
 598   eBP_reg,
 599   eSI_reg,
 600   eDI_reg,
 601
 602   al_reg,
 603   cl_reg,
 604   dl_reg,
 605   bl_reg,
 606   ah_reg,
 607   ch_reg,
 608   dh_reg,
 609   bh_reg,
 610
 611   ax_reg,
 612   cx_reg,
 613   dx_reg,
 614   bx_reg,
 615   sp_reg,
 616   bp_reg,
 617   si_reg,
 618   di_reg,
 619
 620   rAX_reg,
 621   rCX_reg,
 622   rDX_reg,
 623   rBX_reg,
 624   rSP_reg,
 625   rBP_reg,
 626   rSI_reg,
 627   rDI_reg,
 628
 629   z_mode_ax_reg,
 630   indir_dx_reg
 631 };
 632
 633 enum
 634 {
 635   FLOATCODE = 1,
 636   USE_REG_TABLE,
 637   USE_MOD_TABLE,
 638   USE_RM_TABLE,
 639   USE_PREFIX_TABLE,
 640   USE_X86_64_TABLE,
 641   USE_3BYTE_TABLE,
 642   USE_XOP_8F_TABLE,
 643   USE_VEX_C4_TABLE,
 644   USE_VEX_C5_TABLE,
 645   USE_VEX_LEN_TABLE,
 646   USE_VEX_W_TABLE,
 647   USE_EVEX_TABLE,
 648   USE_EVEX_LEN_TABLE
 649 };
 650
 651 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 652
 653 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 654 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 655 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 656 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 657 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 658 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 659 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 660 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 661 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 662 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 663 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 664 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 665 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 666 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 667 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 668 #define EVEX_LEN_TABLE(I)       DIS386 (USE_EVEX_LEN_TABLE, (I))
 669
 670 enum
 671 {
 672   REG_80 = 0,
 673   REG_81,
 674   REG_83,
 675   REG_8F,
 676   REG_C0,
 677   REG_C1,
 678   REG_C6,
 679   REG_C7,
 680   REG_D0,
 681   REG_D1,
 682   REG_D2,
 683   REG_D3,
 684   REG_F6,
 685   REG_F7,
 686   REG_FE,
 687   REG_FF,
 688   REG_0F00,
 689   REG_0F01,
 690   REG_0F0D,
 691   REG_0F18,
 692   REG_0F1C_P_0_MOD_0,
 693   REG_0F1E_P_1_MOD_3,
 694   REG_0F38D8_PREFIX_1,
 695   REG_0F71,
 696   REG_0F72,
 697   REG_0F73,
 698   REG_0FA6,
 699   REG_0FA7,
 700   REG_0FAE,
 701   REG_0FBA,
 702   REG_0FC7,
 703   REG_VEX_0F71,
 704   REG_VEX_0F72,
 705   REG_VEX_0F73,
 706   REG_VEX_0FAE,
 707   REG_VEX_0F3849_X86_64_P_0_W_0_M_1,
 708   REG_VEX_0F38F3,
 709
 710   REG_0FXOP_09_01_L_0,
 711   REG_0FXOP_09_02_L_0,
 712   REG_0FXOP_09_12_M_1_L_0,
 713   REG_0FXOP_0A_12_L_0,
 714
 715   REG_EVEX_0F71,
 716   REG_EVEX_0F72,
 717   REG_EVEX_0F73,
 718   REG_EVEX_0F38C6,
 719   REG_EVEX_0F38C7
 720 };
 721
 722 enum
 723 {
 724   MOD_8D = 0,
 725   MOD_C6_REG_7,
 726   MOD_C7_REG_7,
 727   MOD_FF_REG_3,
 728   MOD_FF_REG_5,
 729   MOD_0F01_REG_0,
 730   MOD_0F01_REG_1,
 731   MOD_0F01_REG_2,
 732   MOD_0F01_REG_3,
 733   MOD_0F01_REG_5,
 734   MOD_0F01_REG_7,
 735   MOD_0F12_PREFIX_0,
 736   MOD_0F12_PREFIX_2,
 737   MOD_0F13,
 738   MOD_0F16_PREFIX_0,
 739   MOD_0F16_PREFIX_2,
 740   MOD_0F17,
 741   MOD_0F18_REG_0,
 742   MOD_0F18_REG_1,
 743   MOD_0F18_REG_2,
 744   MOD_0F18_REG_3,
 745   MOD_0F18_REG_4,
 746   MOD_0F18_REG_5,
 747   MOD_0F18_REG_6,
 748   MOD_0F18_REG_7,
 749   MOD_0F1A_PREFIX_0,
 750   MOD_0F1B_PREFIX_0,
 751   MOD_0F1B_PREFIX_1,
 752   MOD_0F1C_PREFIX_0,
 753   MOD_0F1E_PREFIX_1,
 754   MOD_0F2B_PREFIX_0,
 755   MOD_0F2B_PREFIX_1,
 756   MOD_0F2B_PREFIX_2,
 757   MOD_0F2B_PREFIX_3,
 758   MOD_0F50,
 759   MOD_0F71_REG_2,
 760   MOD_0F71_REG_4,
 761   MOD_0F71_REG_6,
 762   MOD_0F72_REG_2,
 763   MOD_0F72_REG_4,
 764   MOD_0F72_REG_6,
 765   MOD_0F73_REG_2,
 766   MOD_0F73_REG_3,
 767   MOD_0F73_REG_6,
 768   MOD_0F73_REG_7,
 769   MOD_0FAE_REG_0,
 770   MOD_0FAE_REG_1,
 771   MOD_0FAE_REG_2,
 772   MOD_0FAE_REG_3,
 773   MOD_0FAE_REG_4,
 774   MOD_0FAE_REG_5,
 775   MOD_0FAE_REG_6,
 776   MOD_0FAE_REG_7,
 777   MOD_0FB2,
 778   MOD_0FB4,
 779   MOD_0FB5,
 780   MOD_0FC3,
 781   MOD_0FC7_REG_3,
 782   MOD_0FC7_REG_4,
 783   MOD_0FC7_REG_5,
 784   MOD_0FC7_REG_6,
 785   MOD_0FC7_REG_7,
 786   MOD_0FD7,
 787   MOD_0FE7_PREFIX_2,
 788   MOD_0FF0_PREFIX_3,
 789   MOD_0F382A,
 790   MOD_0F38DC_PREFIX_1,
 791   MOD_0F38DD_PREFIX_1,
 792   MOD_0F38DE_PREFIX_1,
 793   MOD_0F38DF_PREFIX_1,
 794   MOD_0F38F5,
 795   MOD_0F38F6_PREFIX_0,
 796   MOD_0F38F8_PREFIX_1,
 797   MOD_0F38F8_PREFIX_2,
 798   MOD_0F38F8_PREFIX_3,
 799   MOD_0F38F9,
 800   MOD_0F38FA_PREFIX_1,
 801   MOD_0F38FB_PREFIX_1,
 802   MOD_62_32BIT,
 803   MOD_C4_32BIT,
 804   MOD_C5_32BIT,
 805   MOD_VEX_0F12_PREFIX_0,
 806   MOD_VEX_0F12_PREFIX_2,
 807   MOD_VEX_0F13,
 808   MOD_VEX_0F16_PREFIX_0,
 809   MOD_VEX_0F16_PREFIX_2,
 810   MOD_VEX_0F17,
 811   MOD_VEX_0F2B,
 812   MOD_VEX_W_0_0F41_P_0_LEN_1,
 813   MOD_VEX_W_1_0F41_P_0_LEN_1,
 814   MOD_VEX_W_0_0F41_P_2_LEN_1,
 815   MOD_VEX_W_1_0F41_P_2_LEN_1,
 816   MOD_VEX_W_0_0F42_P_0_LEN_1,
 817   MOD_VEX_W_1_0F42_P_0_LEN_1,
 818   MOD_VEX_W_0_0F42_P_2_LEN_1,
 819   MOD_VEX_W_1_0F42_P_2_LEN_1,
 820   MOD_VEX_W_0_0F44_P_0_LEN_1,
 821   MOD_VEX_W_1_0F44_P_0_LEN_1,
 822   MOD_VEX_W_0_0F44_P_2_LEN_1,
 823   MOD_VEX_W_1_0F44_P_2_LEN_1,
 824   MOD_VEX_W_0_0F45_P_0_LEN_1,
 825   MOD_VEX_W_1_0F45_P_0_LEN_1,
 826   MOD_VEX_W_0_0F45_P_2_LEN_1,
 827   MOD_VEX_W_1_0F45_P_2_LEN_1,
 828   MOD_VEX_W_0_0F46_P_0_LEN_1,
 829   MOD_VEX_W_1_0F46_P_0_LEN_1,
 830   MOD_VEX_W_0_0F46_P_2_LEN_1,
 831   MOD_VEX_W_1_0F46_P_2_LEN_1,
 832   MOD_VEX_W_0_0F47_P_0_LEN_1,
 833   MOD_VEX_W_1_0F47_P_0_LEN_1,
 834   MOD_VEX_W_0_0F47_P_2_LEN_1,
 835   MOD_VEX_W_1_0F47_P_2_LEN_1,
 836   MOD_VEX_W_0_0F4A_P_0_LEN_1,
 837   MOD_VEX_W_1_0F4A_P_0_LEN_1,
 838   MOD_VEX_W_0_0F4A_P_2_LEN_1,
 839   MOD_VEX_W_1_0F4A_P_2_LEN_1,
 840   MOD_VEX_W_0_0F4B_P_0_LEN_1,
 841   MOD_VEX_W_1_0F4B_P_0_LEN_1,
 842   MOD_VEX_W_0_0F4B_P_2_LEN_1,
 843   MOD_VEX_0F50,
 844   MOD_VEX_0F71_REG_2,
 845   MOD_VEX_0F71_REG_4,
 846   MOD_VEX_0F71_REG_6,
 847   MOD_VEX_0F72_REG_2,
 848   MOD_VEX_0F72_REG_4,
 849   MOD_VEX_0F72_REG_6,
 850   MOD_VEX_0F73_REG_2,
 851   MOD_VEX_0F73_REG_3,
 852   MOD_VEX_0F73_REG_6,
 853   MOD_VEX_0F73_REG_7,
 854   MOD_VEX_W_0_0F91_P_0_LEN_0,
 855   MOD_VEX_W_1_0F91_P_0_LEN_0,
 856   MOD_VEX_W_0_0F91_P_2_LEN_0,
 857   MOD_VEX_W_1_0F91_P_2_LEN_0,
 858   MOD_VEX_W_0_0F92_P_0_LEN_0,
 859   MOD_VEX_W_0_0F92_P_2_LEN_0,
 860   MOD_VEX_0F92_P_3_LEN_0,
 861   MOD_VEX_W_0_0F93_P_0_LEN_0,
 862   MOD_VEX_W_0_0F93_P_2_LEN_0,
 863   MOD_VEX_0F93_P_3_LEN_0,
 864   MOD_VEX_W_0_0F98_P_0_LEN_0,
 865   MOD_VEX_W_1_0F98_P_0_LEN_0,
 866   MOD_VEX_W_0_0F98_P_2_LEN_0,
 867   MOD_VEX_W_1_0F98_P_2_LEN_0,
 868   MOD_VEX_W_0_0F99_P_0_LEN_0,
 869   MOD_VEX_W_1_0F99_P_0_LEN_0,
 870   MOD_VEX_W_0_0F99_P_2_LEN_0,
 871   MOD_VEX_W_1_0F99_P_2_LEN_0,
 872   MOD_VEX_0FAE_REG_2,
 873   MOD_VEX_0FAE_REG_3,
 874   MOD_VEX_0FD7,
 875   MOD_VEX_0FE7,
 876   MOD_VEX_0FF0_PREFIX_3,
 877   MOD_VEX_0F381A,
 878   MOD_VEX_0F382A,
 879   MOD_VEX_0F382C,
 880   MOD_VEX_0F382D,
 881   MOD_VEX_0F382E,
 882   MOD_VEX_0F382F,
 883   MOD_VEX_0F3849_X86_64_P_0_W_0,
 884   MOD_VEX_0F3849_X86_64_P_2_W_0,
 885   MOD_VEX_0F3849_X86_64_P_3_W_0,
 886   MOD_VEX_0F384B_X86_64_P_1_W_0,
 887   MOD_VEX_0F384B_X86_64_P_2_W_0,
 888   MOD_VEX_0F384B_X86_64_P_3_W_0,
 889   MOD_VEX_0F385A,
 890   MOD_VEX_0F385C_X86_64_P_1_W_0,
 891   MOD_VEX_0F385E_X86_64_P_0_W_0,
 892   MOD_VEX_0F385E_X86_64_P_1_W_0,
 893   MOD_VEX_0F385E_X86_64_P_2_W_0,
 894   MOD_VEX_0F385E_X86_64_P_3_W_0,
 895   MOD_VEX_0F388C,
 896   MOD_VEX_0F388E,
 897   MOD_VEX_0F3A30_L_0,
 898   MOD_VEX_0F3A31_L_0,
 899   MOD_VEX_0F3A32_L_0,
 900   MOD_VEX_0F3A33_L_0,
 901
 902   MOD_VEX_0FXOP_09_12,
 903
 904   MOD_EVEX_0F12_PREFIX_0,
 905   MOD_EVEX_0F12_PREFIX_2,
 906   MOD_EVEX_0F13,
 907   MOD_EVEX_0F16_PREFIX_0,
 908   MOD_EVEX_0F16_PREFIX_2,
 909   MOD_EVEX_0F17,
 910   MOD_EVEX_0F2B,
 911   MOD_EVEX_0F381A_W_0,
 912   MOD_EVEX_0F381A_W_1,
 913   MOD_EVEX_0F381B_W_0,
 914   MOD_EVEX_0F381B_W_1,
 915   MOD_EVEX_0F3828_P_1,
 916   MOD_EVEX_0F382A_P_1_W_1,
 917   MOD_EVEX_0F3838_P_1,
 918   MOD_EVEX_0F383A_P_1_W_0,
 919   MOD_EVEX_0F385A_W_0,
 920   MOD_EVEX_0F385A_W_1,
 921   MOD_EVEX_0F385B_W_0,
 922   MOD_EVEX_0F385B_W_1,
 923   MOD_EVEX_0F387A_W_0,
 924   MOD_EVEX_0F387B_W_0,
 925   MOD_EVEX_0F387C,
 926   MOD_EVEX_0F38C6_REG_1,
 927   MOD_EVEX_0F38C6_REG_2,
 928   MOD_EVEX_0F38C6_REG_5,
 929   MOD_EVEX_0F38C6_REG_6,
 930   MOD_EVEX_0F38C7_REG_1,
 931   MOD_EVEX_0F38C7_REG_2,
 932   MOD_EVEX_0F38C7_REG_5,
 933   MOD_EVEX_0F38C7_REG_6
 934 };
 935
 936 enum
 937 {
 938   RM_C6_REG_7 = 0,
 939   RM_C7_REG_7,
 940   RM_0F01_REG_0,
 941   RM_0F01_REG_1,
 942   RM_0F01_REG_2,
 943   RM_0F01_REG_3,
 944   RM_0F01_REG_5_MOD_3,
 945   RM_0F01_REG_7_MOD_3,
 946   RM_0F1E_P_1_MOD_3_REG_7,
 947   RM_0FAE_REG_6_MOD_3_P_0,
 948   RM_0FAE_REG_7_MOD_3,
 949   RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0
 950 };
 951
 952 enum
 953 {
 954   PREFIX_90 = 0,
 955   PREFIX_0F01_REG_1_RM_4,
 956   PREFIX_0F01_REG_1_RM_5,
 957   PREFIX_0F01_REG_1_RM_6,
 958   PREFIX_0F01_REG_1_RM_7,
 959   PREFIX_0F01_REG_3_RM_1,
 960   PREFIX_0F01_REG_5_MOD_0,
 961   PREFIX_0F01_REG_5_MOD_3_RM_0,
 962   PREFIX_0F01_REG_5_MOD_3_RM_1,
 963   PREFIX_0F01_REG_5_MOD_3_RM_2,
 964   PREFIX_0F01_REG_7_MOD_3_RM_2,
 965   PREFIX_0F09,
 966   PREFIX_0F10,
 967   PREFIX_0F11,
 968   PREFIX_0F12,
 969   PREFIX_0F16,
 970   PREFIX_0F1A,
 971   PREFIX_0F1B,
 972   PREFIX_0F1C,
 973   PREFIX_0F1E,
 974   PREFIX_0F2A,
 975   PREFIX_0F2B,
 976   PREFIX_0F2C,
 977   PREFIX_0F2D,
 978   PREFIX_0F2E,
 979   PREFIX_0F2F,
 980   PREFIX_0F51,
 981   PREFIX_0F52,
 982   PREFIX_0F53,
 983   PREFIX_0F58,
 984   PREFIX_0F59,
 985   PREFIX_0F5A,
 986   PREFIX_0F5B,
 987   PREFIX_0F5C,
 988   PREFIX_0F5D,
 989   PREFIX_0F5E,
 990   PREFIX_0F5F,
 991   PREFIX_0F60,
 992   PREFIX_0F61,
 993   PREFIX_0F62,
 994   PREFIX_0F6F,
 995   PREFIX_0F70,
 996   PREFIX_0F78,
 997   PREFIX_0F79,
 998   PREFIX_0F7C,
 999   PREFIX_0F7D,
1000   PREFIX_0F7E,
1001   PREFIX_0F7F,
1002   PREFIX_0FAE_REG_0_MOD_3,
1003   PREFIX_0FAE_REG_1_MOD_3,
1004   PREFIX_0FAE_REG_2_MOD_3,
1005   PREFIX_0FAE_REG_3_MOD_3,
1006   PREFIX_0FAE_REG_4_MOD_0,
1007   PREFIX_0FAE_REG_4_MOD_3,
1008   PREFIX_0FAE_REG_5_MOD_3,
1009   PREFIX_0FAE_REG_6_MOD_0,
1010   PREFIX_0FAE_REG_6_MOD_3,
1011   PREFIX_0FAE_REG_7_MOD_0,
1012   PREFIX_0FB8,
1013   PREFIX_0FBC,
1014   PREFIX_0FBD,
1015   PREFIX_0FC2,
1016   PREFIX_0FC7_REG_6_MOD_0,
1017   PREFIX_0FC7_REG_6_MOD_3,
1018   PREFIX_0FC7_REG_7_MOD_3,
1019   PREFIX_0FD0,
1020   PREFIX_0FD6,
1021   PREFIX_0FE6,
1022   PREFIX_0FE7,
1023   PREFIX_0FF0,
1024   PREFIX_0FF7,
1025   PREFIX_0F38D8,
1026   PREFIX_0F38DC,
1027   PREFIX_0F38DD,
1028   PREFIX_0F38DE,
1029   PREFIX_0F38DF,
1030   PREFIX_0F38F0,
1031   PREFIX_0F38F1,
1032   PREFIX_0F38F6,
1033   PREFIX_0F38F8,
1034   PREFIX_0F38FA,
1035   PREFIX_0F38FB,
1036   PREFIX_VEX_0F10,
1037   PREFIX_VEX_0F11,
1038   PREFIX_VEX_0F12,
1039   PREFIX_VEX_0F16,
1040   PREFIX_VEX_0F2A,
1041   PREFIX_VEX_0F2C,
1042   PREFIX_VEX_0F2D,
1043   PREFIX_VEX_0F2E,
1044   PREFIX_VEX_0F2F,
1045   PREFIX_VEX_0F41,
1046   PREFIX_VEX_0F42,
1047   PREFIX_VEX_0F44,
1048   PREFIX_VEX_0F45,
1049   PREFIX_VEX_0F46,
1050   PREFIX_VEX_0F47,
1051   PREFIX_VEX_0F4A,
1052   PREFIX_VEX_0F4B,
1053   PREFIX_VEX_0F51,
1054   PREFIX_VEX_0F52,
1055   PREFIX_VEX_0F53,
1056   PREFIX_VEX_0F58,
1057   PREFIX_VEX_0F59,
1058   PREFIX_VEX_0F5A,
1059   PREFIX_VEX_0F5B,
1060   PREFIX_VEX_0F5C,
1061   PREFIX_VEX_0F5D,
1062   PREFIX_VEX_0F5E,
1063   PREFIX_VEX_0F5F,
1064   PREFIX_VEX_0F6F,
1065   PREFIX_VEX_0F70,
1066   PREFIX_VEX_0F7C,
1067   PREFIX_VEX_0F7D,
1068   PREFIX_VEX_0F7E,
1069   PREFIX_VEX_0F7F,
1070   PREFIX_VEX_0F90,
1071   PREFIX_VEX_0F91,
1072   PREFIX_VEX_0F92,
1073   PREFIX_VEX_0F93,
1074   PREFIX_VEX_0F98,
1075   PREFIX_VEX_0F99,
1076   PREFIX_VEX_0FC2,
1077   PREFIX_VEX_0FD0,
1078   PREFIX_VEX_0FE6,
1079   PREFIX_VEX_0FF0,
1080   PREFIX_VEX_0F3849_X86_64,
1081   PREFIX_VEX_0F384B_X86_64,
1082   PREFIX_VEX_0F385C_X86_64,
1083   PREFIX_VEX_0F385E_X86_64,
1084   PREFIX_VEX_0F38F5,
1085   PREFIX_VEX_0F38F6,
1086   PREFIX_VEX_0F38F7,
1087   PREFIX_VEX_0F3AF0,
1088
1089   PREFIX_EVEX_0F10,
1090   PREFIX_EVEX_0F11,
1091   PREFIX_EVEX_0F12,
1092   PREFIX_EVEX_0F16,
1093   PREFIX_EVEX_0F2A,
1094   PREFIX_EVEX_0F51,
1095   PREFIX_EVEX_0F58,
1096   PREFIX_EVEX_0F59,
1097   PREFIX_EVEX_0F5A,
1098   PREFIX_EVEX_0F5B,
1099   PREFIX_EVEX_0F5C,
1100   PREFIX_EVEX_0F5D,
1101   PREFIX_EVEX_0F5E,
1102   PREFIX_EVEX_0F5F,
1103   PREFIX_EVEX_0F6F,
1104   PREFIX_EVEX_0F70,
1105   PREFIX_EVEX_0F78,
1106   PREFIX_EVEX_0F79,
1107   PREFIX_EVEX_0F7A,
1108   PREFIX_EVEX_0F7B,
1109   PREFIX_EVEX_0F7E,
1110   PREFIX_EVEX_0F7F,
1111   PREFIX_EVEX_0FC2,
1112   PREFIX_EVEX_0FE6,
1113   PREFIX_EVEX_0F3810,
1114   PREFIX_EVEX_0F3811,
1115   PREFIX_EVEX_0F3812,
1116   PREFIX_EVEX_0F3813,
1117   PREFIX_EVEX_0F3814,
1118   PREFIX_EVEX_0F3815,
1119   PREFIX_EVEX_0F3820,
1120   PREFIX_EVEX_0F3821,
1121   PREFIX_EVEX_0F3822,
1122   PREFIX_EVEX_0F3823,
1123   PREFIX_EVEX_0F3824,
1124   PREFIX_EVEX_0F3825,
1125   PREFIX_EVEX_0F3826,
1126   PREFIX_EVEX_0F3827,
1127   PREFIX_EVEX_0F3828,
1128   PREFIX_EVEX_0F3829,
1129   PREFIX_EVEX_0F382A,
1130   PREFIX_EVEX_0F3830,
1131   PREFIX_EVEX_0F3831,
1132   PREFIX_EVEX_0F3832,
1133   PREFIX_EVEX_0F3833,
1134   PREFIX_EVEX_0F3834,
1135   PREFIX_EVEX_0F3835,
1136   PREFIX_EVEX_0F3838,
1137   PREFIX_EVEX_0F3839,
1138   PREFIX_EVEX_0F383A,
1139   PREFIX_EVEX_0F3852,
1140   PREFIX_EVEX_0F3853,
1141   PREFIX_EVEX_0F3868,
1142   PREFIX_EVEX_0F3872,
1143   PREFIX_EVEX_0F389A,
1144   PREFIX_EVEX_0F389B,
1145   PREFIX_EVEX_0F38AA,
1146   PREFIX_EVEX_0F38AB,
1147 };
1148
1149 enum
1150 {
1151   X86_64_06 = 0,
1152   X86_64_07,
1153   X86_64_0E,
1154   X86_64_16,
1155   X86_64_17,
1156   X86_64_1E,
1157   X86_64_1F,
1158   X86_64_27,
1159   X86_64_2F,
1160   X86_64_37,
1161   X86_64_3F,
1162   X86_64_60,
1163   X86_64_61,
1164   X86_64_62,
1165   X86_64_63,
1166   X86_64_6D,
1167   X86_64_6F,
1168   X86_64_82,
1169   X86_64_9A,
1170   X86_64_C2,
1171   X86_64_C3,
1172   X86_64_C4,
1173   X86_64_C5,
1174   X86_64_CE,
1175   X86_64_D4,
1176   X86_64_D5,
1177   X86_64_E8,
1178   X86_64_E9,
1179   X86_64_EA,
1180   X86_64_0F01_REG_0,
1181   X86_64_0F01_REG_1,
1182   X86_64_0F01_REG_1_RM_5_PREFIX_2,
1183   X86_64_0F01_REG_1_RM_6_PREFIX_2,
1184   X86_64_0F01_REG_1_RM_7_PREFIX_2,
1185   X86_64_0F01_REG_2,
1186   X86_64_0F01_REG_3,
1187   X86_64_0F24,
1188   X86_64_0F26,
1189   X86_64_VEX_0F3849,
1190   X86_64_VEX_0F384B,
1191   X86_64_VEX_0F385C,
1192   X86_64_VEX_0F385E
1193 };
1194
1195 enum
1196 {
1197   THREE_BYTE_0F38 = 0,
1198   THREE_BYTE_0F3A
1199 };
1200
1201 enum
1202 {
1203   XOP_08 = 0,
1204   XOP_09,
1205   XOP_0A
1206 };
1207
1208 enum
1209 {
1210   VEX_0F = 0,
1211   VEX_0F38,
1212   VEX_0F3A
1213 };
1214
1215 enum
1216 {
1217   EVEX_0F = 0,
1218   EVEX_0F38,
1219   EVEX_0F3A
1220 };
1221
1222 enum
1223 {
1224   VEX_LEN_0F12_P_0_M_0 = 0,
1225   VEX_LEN_0F12_P_0_M_1,
1226 #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0
1227   VEX_LEN_0F13_M_0,
1228   VEX_LEN_0F16_P_0_M_0,
1229   VEX_LEN_0F16_P_0_M_1,
1230 #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0
1231   VEX_LEN_0F17_M_0,
1232   VEX_LEN_0F41_P_0,
1233   VEX_LEN_0F41_P_2,
1234   VEX_LEN_0F42_P_0,
1235   VEX_LEN_0F42_P_2,
1236   VEX_LEN_0F44_P_0,
1237   VEX_LEN_0F44_P_2,
1238   VEX_LEN_0F45_P_0,
1239   VEX_LEN_0F45_P_2,
1240   VEX_LEN_0F46_P_0,
1241   VEX_LEN_0F46_P_2,
1242   VEX_LEN_0F47_P_0,
1243   VEX_LEN_0F47_P_2,
1244   VEX_LEN_0F4A_P_0,
1245   VEX_LEN_0F4A_P_2,
1246   VEX_LEN_0F4B_P_0,
1247   VEX_LEN_0F4B_P_2,
1248   VEX_LEN_0F6E,
1249   VEX_LEN_0F77,
1250   VEX_LEN_0F7E_P_1,
1251   VEX_LEN_0F7E_P_2,
1252   VEX_LEN_0F90_P_0,
1253   VEX_LEN_0F90_P_2,
1254   VEX_LEN_0F91_P_0,
1255   VEX_LEN_0F91_P_2,
1256   VEX_LEN_0F92_P_0,
1257   VEX_LEN_0F92_P_2,
1258   VEX_LEN_0F92_P_3,
1259   VEX_LEN_0F93_P_0,
1260   VEX_LEN_0F93_P_2,
1261   VEX_LEN_0F93_P_3,
1262   VEX_LEN_0F98_P_0,
1263   VEX_LEN_0F98_P_2,
1264   VEX_LEN_0F99_P_0,
1265   VEX_LEN_0F99_P_2,
1266   VEX_LEN_0FAE_R_2_M_0,
1267   VEX_LEN_0FAE_R_3_M_0,
1268   VEX_LEN_0FC4,
1269   VEX_LEN_0FC5,
1270   VEX_LEN_0FD6,
1271   VEX_LEN_0FF7,
1272   VEX_LEN_0F3816,
1273   VEX_LEN_0F3819,
1274   VEX_LEN_0F381A_M_0,
1275   VEX_LEN_0F3836,
1276   VEX_LEN_0F3841,
1277   VEX_LEN_0F3849_X86_64_P_0_W_0_M_0,
1278   VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0,
1279   VEX_LEN_0F3849_X86_64_P_2_W_0_M_0,
1280   VEX_LEN_0F3849_X86_64_P_3_W_0_M_0,
1281   VEX_LEN_0F384B_X86_64_P_1_W_0_M_0,
1282   VEX_LEN_0F384B_X86_64_P_2_W_0_M_0,
1283   VEX_LEN_0F384B_X86_64_P_3_W_0_M_0,
1284   VEX_LEN_0F385A_M_0,
1285   VEX_LEN_0F385C_X86_64_P_1_W_0_M_0,
1286   VEX_LEN_0F385E_X86_64_P_0_W_0_M_0,
1287   VEX_LEN_0F385E_X86_64_P_1_W_0_M_0,
1288   VEX_LEN_0F385E_X86_64_P_2_W_0_M_0,
1289   VEX_LEN_0F385E_X86_64_P_3_W_0_M_0,
1290   VEX_LEN_0F38DB,
1291   VEX_LEN_0F38F2,
1292   VEX_LEN_0F38F3_R_1,
1293   VEX_LEN_0F38F3_R_2,
1294   VEX_LEN_0F38F3_R_3,
1295   VEX_LEN_0F38F5_P_0,
1296   VEX_LEN_0F38F5_P_1,
1297   VEX_LEN_0F38F5_P_3,
1298   VEX_LEN_0F38F6_P_3,
1299   VEX_LEN_0F38F7_P_0,
1300   VEX_LEN_0F38F7_P_1,
1301   VEX_LEN_0F38F7_P_2,
1302   VEX_LEN_0F38F7_P_3,
1303   VEX_LEN_0F3A00,
1304   VEX_LEN_0F3A01,
1305   VEX_LEN_0F3A06,
1306   VEX_LEN_0F3A14,
1307   VEX_LEN_0F3A15,
1308   VEX_LEN_0F3A16,
1309   VEX_LEN_0F3A17,
1310   VEX_LEN_0F3A18,
1311   VEX_LEN_0F3A19,
1312   VEX_LEN_0F3A20,
1313   VEX_LEN_0F3A21,
1314   VEX_LEN_0F3A22,
1315   VEX_LEN_0F3A30,
1316   VEX_LEN_0F3A31,
1317   VEX_LEN_0F3A32,
1318   VEX_LEN_0F3A33,
1319   VEX_LEN_0F3A38,
1320   VEX_LEN_0F3A39,
1321   VEX_LEN_0F3A41,
1322   VEX_LEN_0F3A46,
1323   VEX_LEN_0F3A60,
1324   VEX_LEN_0F3A61,
1325   VEX_LEN_0F3A62,
1326   VEX_LEN_0F3A63,
1327   VEX_LEN_0F3ADF,
1328   VEX_LEN_0F3AF0_P_3,
1329   VEX_LEN_0FXOP_08_85,
1330   VEX_LEN_0FXOP_08_86,
1331   VEX_LEN_0FXOP_08_87,
1332   VEX_LEN_0FXOP_08_8E,
1333   VEX_LEN_0FXOP_08_8F,
1334   VEX_LEN_0FXOP_08_95,
1335   VEX_LEN_0FXOP_08_96,
1336   VEX_LEN_0FXOP_08_97,
1337   VEX_LEN_0FXOP_08_9E,
1338   VEX_LEN_0FXOP_08_9F,
1339   VEX_LEN_0FXOP_08_A3,
1340   VEX_LEN_0FXOP_08_A6,
1341   VEX_LEN_0FXOP_08_B6,
1342   VEX_LEN_0FXOP_08_C0,
1343   VEX_LEN_0FXOP_08_C1,
1344   VEX_LEN_0FXOP_08_C2,
1345   VEX_LEN_0FXOP_08_C3,
1346   VEX_LEN_0FXOP_08_CC,
1347   VEX_LEN_0FXOP_08_CD,
1348   VEX_LEN_0FXOP_08_CE,
1349   VEX_LEN_0FXOP_08_CF,
1350   VEX_LEN_0FXOP_08_EC,
1351   VEX_LEN_0FXOP_08_ED,
1352   VEX_LEN_0FXOP_08_EE,
1353   VEX_LEN_0FXOP_08_EF,
1354   VEX_LEN_0FXOP_09_01,
1355   VEX_LEN_0FXOP_09_02,
1356   VEX_LEN_0FXOP_09_12_M_1,
1357   VEX_LEN_0FXOP_09_82_W_0,
1358   VEX_LEN_0FXOP_09_83_W_0,
1359   VEX_LEN_0FXOP_09_90,
1360   VEX_LEN_0FXOP_09_91,
1361   VEX_LEN_0FXOP_09_92,
1362   VEX_LEN_0FXOP_09_93,
1363   VEX_LEN_0FXOP_09_94,
1364   VEX_LEN_0FXOP_09_95,
1365   VEX_LEN_0FXOP_09_96,
1366   VEX_LEN_0FXOP_09_97,
1367   VEX_LEN_0FXOP_09_98,
1368   VEX_LEN_0FXOP_09_99,
1369   VEX_LEN_0FXOP_09_9A,
1370   VEX_LEN_0FXOP_09_9B,
1371   VEX_LEN_0FXOP_09_C1,
1372   VEX_LEN_0FXOP_09_C2,
1373   VEX_LEN_0FXOP_09_C3,
1374   VEX_LEN_0FXOP_09_C6,
1375   VEX_LEN_0FXOP_09_C7,
1376   VEX_LEN_0FXOP_09_CB,
1377   VEX_LEN_0FXOP_09_D1,
1378   VEX_LEN_0FXOP_09_D2,
1379   VEX_LEN_0FXOP_09_D3,
1380   VEX_LEN_0FXOP_09_D6,
1381   VEX_LEN_0FXOP_09_D7,
1382   VEX_LEN_0FXOP_09_DB,
1383   VEX_LEN_0FXOP_09_E1,
1384   VEX_LEN_0FXOP_09_E2,
1385   VEX_LEN_0FXOP_09_E3,
1386   VEX_LEN_0FXOP_0A_12,
1387 };
1388
1389 enum
1390 {
1391   EVEX_LEN_0F6E = 0,
1392   EVEX_LEN_0F7E_P_1,
1393   EVEX_LEN_0F7E_P_2,
1394   EVEX_LEN_0FC4,
1395   EVEX_LEN_0FC5,
1396   EVEX_LEN_0FD6,
1397   EVEX_LEN_0F3816,
1398   EVEX_LEN_0F3819_W_0,
1399   EVEX_LEN_0F3819_W_1,
1400   EVEX_LEN_0F381A_W_0_M_0,
1401   EVEX_LEN_0F381A_W_1_M_0,
1402   EVEX_LEN_0F381B_W_0_M_0,
1403   EVEX_LEN_0F381B_W_1_M_0,
1404   EVEX_LEN_0F3836,
1405   EVEX_LEN_0F385A_W_0_M_0,
1406   EVEX_LEN_0F385A_W_1_M_0,
1407   EVEX_LEN_0F385B_W_0_M_0,
1408   EVEX_LEN_0F385B_W_1_M_0,
1409   EVEX_LEN_0F38C6_R_1_M_0,
1410   EVEX_LEN_0F38C6_R_2_M_0,
1411   EVEX_LEN_0F38C6_R_5_M_0,
1412   EVEX_LEN_0F38C6_R_6_M_0,
1413   EVEX_LEN_0F38C7_R_1_M_0_W_0,
1414   EVEX_LEN_0F38C7_R_1_M_0_W_1,
1415   EVEX_LEN_0F38C7_R_2_M_0_W_0,
1416   EVEX_LEN_0F38C7_R_2_M_0_W_1,
1417   EVEX_LEN_0F38C7_R_5_M_0_W_0,
1418   EVEX_LEN_0F38C7_R_5_M_0_W_1,
1419   EVEX_LEN_0F38C7_R_6_M_0_W_0,
1420   EVEX_LEN_0F38C7_R_6_M_0_W_1,
1421   EVEX_LEN_0F3A00_W_1,
1422   EVEX_LEN_0F3A01_W_1,
1423   EVEX_LEN_0F3A14,
1424   EVEX_LEN_0F3A15,
1425   EVEX_LEN_0F3A16,
1426   EVEX_LEN_0F3A17,
1427   EVEX_LEN_0F3A18_W_0,
1428   EVEX_LEN_0F3A18_W_1,
1429   EVEX_LEN_0F3A19_W_0,
1430   EVEX_LEN_0F3A19_W_1,
1431   EVEX_LEN_0F3A1A_W_0,
1432   EVEX_LEN_0F3A1A_W_1,
1433   EVEX_LEN_0F3A1B_W_0,
1434   EVEX_LEN_0F3A1B_W_1,
1435   EVEX_LEN_0F3A20,
1436   EVEX_LEN_0F3A21_W_0,
1437   EVEX_LEN_0F3A22,
1438   EVEX_LEN_0F3A23_W_0,
1439   EVEX_LEN_0F3A23_W_1,
1440   EVEX_LEN_0F3A38_W_0,
1441   EVEX_LEN_0F3A38_W_1,
1442   EVEX_LEN_0F3A39_W_0,
1443   EVEX_LEN_0F3A39_W_1,
1444   EVEX_LEN_0F3A3A_W_0,
1445   EVEX_LEN_0F3A3A_W_1,
1446   EVEX_LEN_0F3A3B_W_0,
1447   EVEX_LEN_0F3A3B_W_1,
1448   EVEX_LEN_0F3A43_W_0,
1449   EVEX_LEN_0F3A43_W_1
1450 };
1451
1452 enum
1453 {
1454   VEX_W_0F41_P_0_LEN_1 = 0,
1455   VEX_W_0F41_P_2_LEN_1,
1456   VEX_W_0F42_P_0_LEN_1,
1457   VEX_W_0F42_P_2_LEN_1,
1458   VEX_W_0F44_P_0_LEN_0,
1459   VEX_W_0F44_P_2_LEN_0,
1460   VEX_W_0F45_P_0_LEN_1,
1461   VEX_W_0F45_P_2_LEN_1,
1462   VEX_W_0F46_P_0_LEN_1,
1463   VEX_W_0F46_P_2_LEN_1,
1464   VEX_W_0F47_P_0_LEN_1,
1465   VEX_W_0F47_P_2_LEN_1,
1466   VEX_W_0F4A_P_0_LEN_1,
1467   VEX_W_0F4A_P_2_LEN_1,
1468   VEX_W_0F4B_P_0_LEN_1,
1469   VEX_W_0F4B_P_2_LEN_1,
1470   VEX_W_0F90_P_0_LEN_0,
1471   VEX_W_0F90_P_2_LEN_0,
1472   VEX_W_0F91_P_0_LEN_0,
1473   VEX_W_0F91_P_2_LEN_0,
1474   VEX_W_0F92_P_0_LEN_0,
1475   VEX_W_0F92_P_2_LEN_0,
1476   VEX_W_0F93_P_0_LEN_0,
1477   VEX_W_0F93_P_2_LEN_0,
1478   VEX_W_0F98_P_0_LEN_0,
1479   VEX_W_0F98_P_2_LEN_0,
1480   VEX_W_0F99_P_0_LEN_0,
1481   VEX_W_0F99_P_2_LEN_0,
1482   VEX_W_0F380C,
1483   VEX_W_0F380D,
1484   VEX_W_0F380E,
1485   VEX_W_0F380F,
1486   VEX_W_0F3813,
1487   VEX_W_0F3816_L_1,
1488   VEX_W_0F3818,
1489   VEX_W_0F3819_L_1,
1490   VEX_W_0F381A_M_0_L_1,
1491   VEX_W_0F382C_M_0,
1492   VEX_W_0F382D_M_0,
1493   VEX_W_0F382E_M_0,
1494   VEX_W_0F382F_M_0,
1495   VEX_W_0F3836,
1496   VEX_W_0F3846,
1497   VEX_W_0F3849_X86_64_P_0,
1498   VEX_W_0F3849_X86_64_P_2,
1499   VEX_W_0F3849_X86_64_P_3,
1500   VEX_W_0F384B_X86_64_P_1,
1501   VEX_W_0F384B_X86_64_P_2,
1502   VEX_W_0F384B_X86_64_P_3,
1503   VEX_W_0F3858,
1504   VEX_W_0F3859,
1505   VEX_W_0F385A_M_0_L_0,
1506   VEX_W_0F385C_X86_64_P_1,
1507   VEX_W_0F385E_X86_64_P_0,
1508   VEX_W_0F385E_X86_64_P_1,
1509   VEX_W_0F385E_X86_64_P_2,
1510   VEX_W_0F385E_X86_64_P_3,
1511   VEX_W_0F3878,
1512   VEX_W_0F3879,
1513   VEX_W_0F38CF,
1514   VEX_W_0F3A00_L_1,
1515   VEX_W_0F3A01_L_1,
1516   VEX_W_0F3A02,
1517   VEX_W_0F3A04,
1518   VEX_W_0F3A05,
1519   VEX_W_0F3A06_L_1,
1520   VEX_W_0F3A18_L_1,
1521   VEX_W_0F3A19_L_1,
1522   VEX_W_0F3A1D,
1523   VEX_W_0F3A38_L_1,
1524   VEX_W_0F3A39_L_1,
1525   VEX_W_0F3A46_L_1,
1526   VEX_W_0F3A4A,
1527   VEX_W_0F3A4B,
1528   VEX_W_0F3A4C,
1529   VEX_W_0F3ACE,
1530   VEX_W_0F3ACF,
1531
1532   VEX_W_0FXOP_08_85_L_0,
1533   VEX_W_0FXOP_08_86_L_0,
1534   VEX_W_0FXOP_08_87_L_0,
1535   VEX_W_0FXOP_08_8E_L_0,
1536   VEX_W_0FXOP_08_8F_L_0,
1537   VEX_W_0FXOP_08_95_L_0,
1538   VEX_W_0FXOP_08_96_L_0,
1539   VEX_W_0FXOP_08_97_L_0,
1540   VEX_W_0FXOP_08_9E_L_0,
1541   VEX_W_0FXOP_08_9F_L_0,
1542   VEX_W_0FXOP_08_A6_L_0,
1543   VEX_W_0FXOP_08_B6_L_0,
1544   VEX_W_0FXOP_08_C0_L_0,
1545   VEX_W_0FXOP_08_C1_L_0,
1546   VEX_W_0FXOP_08_C2_L_0,
1547   VEX_W_0FXOP_08_C3_L_0,
1548   VEX_W_0FXOP_08_CC_L_0,
1549   VEX_W_0FXOP_08_CD_L_0,
1550   VEX_W_0FXOP_08_CE_L_0,
1551   VEX_W_0FXOP_08_CF_L_0,
1552   VEX_W_0FXOP_08_EC_L_0,
1553   VEX_W_0FXOP_08_ED_L_0,
1554   VEX_W_0FXOP_08_EE_L_0,
1555   VEX_W_0FXOP_08_EF_L_0,
1556
1557   VEX_W_0FXOP_09_80,
1558   VEX_W_0FXOP_09_81,
1559   VEX_W_0FXOP_09_82,
1560   VEX_W_0FXOP_09_83,
1561   VEX_W_0FXOP_09_C1_L_0,
1562   VEX_W_0FXOP_09_C2_L_0,
1563   VEX_W_0FXOP_09_C3_L_0,
1564   VEX_W_0FXOP_09_C6_L_0,
1565   VEX_W_0FXOP_09_C7_L_0,
1566   VEX_W_0FXOP_09_CB_L_0,
1567   VEX_W_0FXOP_09_D1_L_0,
1568   VEX_W_0FXOP_09_D2_L_0,
1569   VEX_W_0FXOP_09_D3_L_0,
1570   VEX_W_0FXOP_09_D6_L_0,
1571   VEX_W_0FXOP_09_D7_L_0,
1572   VEX_W_0FXOP_09_DB_L_0,
1573   VEX_W_0FXOP_09_E1_L_0,
1574   VEX_W_0FXOP_09_E2_L_0,
1575   VEX_W_0FXOP_09_E3_L_0,
1576
1577   EVEX_W_0F10_P_1,
1578   EVEX_W_0F10_P_3,
1579   EVEX_W_0F11_P_1,
1580   EVEX_W_0F11_P_3,
1581   EVEX_W_0F12_P_0_M_1,
1582   EVEX_W_0F12_P_1,
1583   EVEX_W_0F12_P_3,
1584   EVEX_W_0F16_P_0_M_1,
1585   EVEX_W_0F16_P_1,
1586   EVEX_W_0F2A_P_3,
1587   EVEX_W_0F51_P_1,
1588   EVEX_W_0F51_P_3,
1589   EVEX_W_0F58_P_1,
1590   EVEX_W_0F58_P_3,
1591   EVEX_W_0F59_P_1,
1592   EVEX_W_0F59_P_3,
1593   EVEX_W_0F5A_P_0,
1594   EVEX_W_0F5A_P_1,
1595   EVEX_W_0F5A_P_2,
1596   EVEX_W_0F5A_P_3,
1597   EVEX_W_0F5B_P_0,
1598   EVEX_W_0F5B_P_1,
1599   EVEX_W_0F5B_P_2,
1600   EVEX_W_0F5C_P_1,
1601   EVEX_W_0F5C_P_3,
1602   EVEX_W_0F5D_P_1,
1603   EVEX_W_0F5D_P_3,
1604   EVEX_W_0F5E_P_1,
1605   EVEX_W_0F5E_P_3,
1606   EVEX_W_0F5F_P_1,
1607   EVEX_W_0F5F_P_3,
1608   EVEX_W_0F62,
1609   EVEX_W_0F66,
1610   EVEX_W_0F6A,
1611   EVEX_W_0F6B,
1612   EVEX_W_0F6C,
1613   EVEX_W_0F6D,
1614   EVEX_W_0F6F_P_1,
1615   EVEX_W_0F6F_P_2,
1616   EVEX_W_0F6F_P_3,
1617   EVEX_W_0F70_P_2,
1618   EVEX_W_0F72_R_2,
1619   EVEX_W_0F72_R_6,
1620   EVEX_W_0F73_R_2,
1621   EVEX_W_0F73_R_6,
1622   EVEX_W_0F76,
1623   EVEX_W_0F78_P_0,
1624   EVEX_W_0F78_P_2,
1625   EVEX_W_0F79_P_0,
1626   EVEX_W_0F79_P_2,
1627   EVEX_W_0F7A_P_1,
1628   EVEX_W_0F7A_P_2,
1629   EVEX_W_0F7A_P_3,
1630   EVEX_W_0F7B_P_2,
1631   EVEX_W_0F7B_P_3,
1632   EVEX_W_0F7E_P_1,
1633   EVEX_W_0F7F_P_1,
1634   EVEX_W_0F7F_P_2,
1635   EVEX_W_0F7F_P_3,
1636   EVEX_W_0FC2_P_1,
1637   EVEX_W_0FC2_P_3,
1638   EVEX_W_0FD2,
1639   EVEX_W_0FD3,
1640   EVEX_W_0FD4,
1641   EVEX_W_0FD6_L_0,
1642   EVEX_W_0FE6_P_1,
1643   EVEX_W_0FE6_P_2,
1644   EVEX_W_0FE6_P_3,
1645   EVEX_W_0FE7,
1646   EVEX_W_0FF2,
1647   EVEX_W_0FF3,
1648   EVEX_W_0FF4,
1649   EVEX_W_0FFA,
1650   EVEX_W_0FFB,
1651   EVEX_W_0FFE,
1652   EVEX_W_0F380D,
1653   EVEX_W_0F3810_P_1,
1654   EVEX_W_0F3810_P_2,
1655   EVEX_W_0F3811_P_1,
1656   EVEX_W_0F3811_P_2,
1657   EVEX_W_0F3812_P_1,
1658   EVEX_W_0F3812_P_2,
1659   EVEX_W_0F3813_P_1,
1660   EVEX_W_0F3813_P_2,
1661   EVEX_W_0F3814_P_1,
1662   EVEX_W_0F3815_P_1,
1663   EVEX_W_0F3819,
1664   EVEX_W_0F381A,
1665   EVEX_W_0F381B,
1666   EVEX_W_0F381E,
1667   EVEX_W_0F381F,
1668   EVEX_W_0F3820_P_1,
1669   EVEX_W_0F3821_P_1,
1670   EVEX_W_0F3822_P_1,
1671   EVEX_W_0F3823_P_1,
1672   EVEX_W_0F3824_P_1,
1673   EVEX_W_0F3825_P_1,
1674   EVEX_W_0F3825_P_2,
1675   EVEX_W_0F3828_P_2,
1676   EVEX_W_0F3829_P_2,
1677   EVEX_W_0F382A_P_1,
1678   EVEX_W_0F382A_P_2,
1679   EVEX_W_0F382B,
1680   EVEX_W_0F3830_P_1,
1681   EVEX_W_0F3831_P_1,
1682   EVEX_W_0F3832_P_1,
1683   EVEX_W_0F3833_P_1,
1684   EVEX_W_0F3834_P_1,
1685   EVEX_W_0F3835_P_1,
1686   EVEX_W_0F3835_P_2,
1687   EVEX_W_0F3837,
1688   EVEX_W_0F383A_P_1,
1689   EVEX_W_0F3852_P_1,
1690   EVEX_W_0F3859,
1691   EVEX_W_0F385A,
1692   EVEX_W_0F385B,
1693   EVEX_W_0F3870,
1694   EVEX_W_0F3872_P_1,
1695   EVEX_W_0F3872_P_2,
1696   EVEX_W_0F3872_P_3,
1697   EVEX_W_0F387A,
1698   EVEX_W_0F387B,
1699   EVEX_W_0F3883,
1700   EVEX_W_0F3891,
1701   EVEX_W_0F3893,
1702   EVEX_W_0F38A1,
1703   EVEX_W_0F38A3,
1704   EVEX_W_0F38C7_R_1_M_0,
1705   EVEX_W_0F38C7_R_2_M_0,
1706   EVEX_W_0F38C7_R_5_M_0,
1707   EVEX_W_0F38C7_R_6_M_0,
1708
1709   EVEX_W_0F3A00,
1710   EVEX_W_0F3A01,
1711   EVEX_W_0F3A05,
1712   EVEX_W_0F3A08,
1713   EVEX_W_0F3A09,
1714   EVEX_W_0F3A0A,
1715   EVEX_W_0F3A0B,
1716   EVEX_W_0F3A18,
1717   EVEX_W_0F3A19,
1718   EVEX_W_0F3A1A,
1719   EVEX_W_0F3A1B,
1720   EVEX_W_0F3A21,
1721   EVEX_W_0F3A23,
1722   EVEX_W_0F3A38,
1723   EVEX_W_0F3A39,
1724   EVEX_W_0F3A3A,
1725   EVEX_W_0F3A3B,
1726   EVEX_W_0F3A42,
1727   EVEX_W_0F3A43,
1728   EVEX_W_0F3A70,
1729   EVEX_W_0F3A72,
1730 };
1731
1732 typedef void (*op_rtn) (int bytemode, int sizeflag);
1733
1734 struct dis386 {
1735   const char *name;
1736   struct
1737     {
1738       op_rtn rtn;
1739       int bytemode;
1740     } op[MAX_OPERANDS];
1741   unsigned int prefix_requirement;
1742 };
1743
1744 /* Upper case letters in the instruction names here are macros.
1745    'A' => print 'b' if no register operands or suffix_always is true
1746    'B' => print 'b' if suffix_always is true
1747    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1748           size prefix
1749    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1750           suffix_always is true
1751    'E' => print 'e' if 32-bit form of jcxz
1752    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1753    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1754    'H' => print ",pt" or ",pn" branch hint
1755    'I' unused.
1756    'J' unused.
1757    'K' => print 'd' or 'q' if rex prefix is present.
1758    'L' unused.
1759    'M' => print 'r' if intel_mnemonic is false.
1760    'N' => print 'n' if instruction has no wait "prefix"
1761    'O' => print 'd' or 'o' (or 'q' in Intel mode)
1762    'P' => behave as 'T' except with register operand outside of suffix_always
1763           mode
1764    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1765           is true
1766    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1767    'S' => print 'w', 'l' or 'q' if suffix_always is true
1768    'T' => print 'w', 'l'/'d', or 'q' if instruction has an operand size
1769           prefix or if suffix_always is true.
1770    'U' unused.
1771    'V' unused.
1772    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1773    'X' => print 's', 'd' depending on data16 prefix (for XMM)
1774    'Y' unused.
1775    'Z' => print 'q' in 64bit mode and 'l' otherwise, if suffix_always is true.
1776    '!' => change condition from true to false or from false to true.
1777    '%' => add 1 upper case letter to the macro.
1778    '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
1779           prefix or suffix_always is true (lcall/ljmp).
1780    '@' => in 64bit mode for Intel64 ISA or if instruction
1781           has no operand sizing prefix, print 'q' if suffix_always is true or
1782           nothing otherwise; behave as 'P' in all other cases
1783
1784    2 upper case letter macros:
1785    "XY" => print 'x' or 'y' if suffix_always is true or no register
1786            operands and no broadcast.
1787    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
1788            register operands and no broadcast.
1789    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1790    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond
1791            being false, or no operand at all in 64bit mode, or if suffix_always
1792            is true.
1793    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1794    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1795    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1796    "DQ" => print 'd' or 'q' depending on the VEX.W bit
1797    "BW" => print 'b' or 'w' depending on the VEX.W bit
1798    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
1799            an operand size prefix, or suffix_always is true.  print
1800            'q' if rex prefix is present.
1801
1802    Many of the above letters print nothing in Intel mode.  See "putop"
1803    for the details.
1804
1805    Braces '{' and '}', and vertical bars '|', indicate alternative
1806    mnemonic strings for AT&T and Intel.  */
1807
1808 static const struct dis386 dis386[] = {
1809   /* 00 */
1810   { "addB",             { Ebh1, Gb }, 0 },
1811   { "addS",             { Evh1, Gv }, 0 },
1812   { "addB",             { Gb, EbS }, 0 },
1813   { "addS",             { Gv, EvS }, 0 },
1814   { "addB",             { AL, Ib }, 0 },
1815   { "addS",             { eAX, Iv }, 0 },
1816   { X86_64_TABLE (X86_64_06) },
1817   { X86_64_TABLE (X86_64_07) },
1818   /* 08 */
1819   { "orB",              { Ebh1, Gb }, 0 },
1820   { "orS",              { Evh1, Gv }, 0 },
1821   { "orB",              { Gb, EbS }, 0 },
1822   { "orS",              { Gv, EvS }, 0 },
1823   { "orB",              { AL, Ib }, 0 },
1824   { "orS",              { eAX, Iv }, 0 },
1825   { X86_64_TABLE (X86_64_0E) },
1826   { Bad_Opcode },       /* 0x0f extended opcode escape */
1827   /* 10 */
1828   { "adcB",             { Ebh1, Gb }, 0 },
1829   { "adcS",             { Evh1, Gv }, 0 },
1830   { "adcB",             { Gb, EbS }, 0 },
1831   { "adcS",             { Gv, EvS }, 0 },
1832   { "adcB",             { AL, Ib }, 0 },
1833   { "adcS",             { eAX, Iv }, 0 },
1834   { X86_64_TABLE (X86_64_16) },
1835   { X86_64_TABLE (X86_64_17) },
1836   /* 18 */
1837   { "sbbB",             { Ebh1, Gb }, 0 },
1838   { "sbbS",             { Evh1, Gv }, 0 },
1839   { "sbbB",             { Gb, EbS }, 0 },
1840   { "sbbS",             { Gv, EvS }, 0 },
1841   { "sbbB",             { AL, Ib }, 0 },
1842   { "sbbS",             { eAX, Iv }, 0 },
1843   { X86_64_TABLE (X86_64_1E) },
1844   { X86_64_TABLE (X86_64_1F) },
1845   /* 20 */
1846   { "andB",             { Ebh1, Gb }, 0 },
1847   { "andS",             { Evh1, Gv }, 0 },
1848   { "andB",             { Gb, EbS }, 0 },
1849   { "andS",             { Gv, EvS }, 0 },
1850   { "andB",             { AL, Ib }, 0 },
1851   { "andS",             { eAX, Iv }, 0 },
1852   { Bad_Opcode },       /* SEG ES prefix */
1853   { X86_64_TABLE (X86_64_27) },
1854   /* 28 */
1855   { "subB",             { Ebh1, Gb }, 0 },
1856   { "subS",             { Evh1, Gv }, 0 },
1857   { "subB",             { Gb, EbS }, 0 },
1858   { "subS",             { Gv, EvS }, 0 },
1859   { "subB",             { AL, Ib }, 0 },
1860   { "subS",             { eAX, Iv }, 0 },
1861   { Bad_Opcode },       /* SEG CS prefix */
1862   { X86_64_TABLE (X86_64_2F) },
1863   /* 30 */
1864   { "xorB",             { Ebh1, Gb }, 0 },
1865   { "xorS",             { Evh1, Gv }, 0 },
1866   { "xorB",             { Gb, EbS }, 0 },
1867   { "xorS",             { Gv, EvS }, 0 },
1868   { "xorB",             { AL, Ib }, 0 },
1869   { "xorS",             { eAX, Iv }, 0 },
1870   { Bad_Opcode },       /* SEG SS prefix */
1871   { X86_64_TABLE (X86_64_37) },
1872   /* 38 */
1873   { "cmpB",             { Eb, Gb }, 0 },
1874   { "cmpS",             { Ev, Gv }, 0 },
1875   { "cmpB",             { Gb, EbS }, 0 },
1876   { "cmpS",             { Gv, EvS }, 0 },
1877   { "cmpB",             { AL, Ib }, 0 },
1878   { "cmpS",             { eAX, Iv }, 0 },
1879   { Bad_Opcode },       /* SEG DS prefix */
1880   { X86_64_TABLE (X86_64_3F) },
1881   /* 40 */
1882   { "inc{S|}",          { RMeAX }, 0 },
1883   { "inc{S|}",          { RMeCX }, 0 },
1884   { "inc{S|}",          { RMeDX }, 0 },
1885   { "inc{S|}",          { RMeBX }, 0 },
1886   { "inc{S|}",          { RMeSP }, 0 },
1887   { "inc{S|}",          { RMeBP }, 0 },
1888   { "inc{S|}",          { RMeSI }, 0 },
1889   { "inc{S|}",          { RMeDI }, 0 },
1890   /* 48 */
1891   { "dec{S|}",          { RMeAX }, 0 },
1892   { "dec{S|}",          { RMeCX }, 0 },
1893   { "dec{S|}",          { RMeDX }, 0 },
1894   { "dec{S|}",          { RMeBX }, 0 },
1895   { "dec{S|}",          { RMeSP }, 0 },
1896   { "dec{S|}",          { RMeBP }, 0 },
1897   { "dec{S|}",          { RMeSI }, 0 },
1898   { "dec{S|}",          { RMeDI }, 0 },
1899   /* 50 */
1900   { "push{!P|}",                { RMrAX }, 0 },
1901   { "push{!P|}",                { RMrCX }, 0 },
1902   { "push{!P|}",                { RMrDX }, 0 },
1903   { "push{!P|}",                { RMrBX }, 0 },
1904   { "push{!P|}",                { RMrSP }, 0 },
1905   { "push{!P|}",                { RMrBP }, 0 },
1906   { "push{!P|}",                { RMrSI }, 0 },
1907   { "push{!P|}",                { RMrDI }, 0 },
1908   /* 58 */
1909   { "pop{!P|}",         { RMrAX }, 0 },
1910   { "pop{!P|}",         { RMrCX }, 0 },
1911   { "pop{!P|}",         { RMrDX }, 0 },
1912   { "pop{!P|}",         { RMrBX }, 0 },
1913   { "pop{!P|}",         { RMrSP }, 0 },
1914   { "pop{!P|}",         { RMrBP }, 0 },
1915   { "pop{!P|}",         { RMrSI }, 0 },
1916   { "pop{!P|}",         { RMrDI }, 0 },
1917   /* 60 */
1918   { X86_64_TABLE (X86_64_60) },
1919   { X86_64_TABLE (X86_64_61) },
1920   { X86_64_TABLE (X86_64_62) },
1921   { X86_64_TABLE (X86_64_63) },
1922   { Bad_Opcode },       /* seg fs */
1923   { Bad_Opcode },       /* seg gs */
1924   { Bad_Opcode },       /* op size prefix */
1925   { Bad_Opcode },       /* adr size prefix */
1926   /* 68 */
1927   { "pushP",            { sIv }, 0 },
1928   { "imulS",            { Gv, Ev, Iv }, 0 },
1929   { "pushP",            { sIbT }, 0 },
1930   { "imulS",            { Gv, Ev, sIb }, 0 },
1931   { "ins{b|}",          { Ybr, indirDX }, 0 },
1932   { X86_64_TABLE (X86_64_6D) },
1933   { "outs{b|}",         { indirDXr, Xb }, 0 },
1934   { X86_64_TABLE (X86_64_6F) },
1935   /* 70 */
1936   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
1937   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
1938   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
1939   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
1940   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
1941   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
1942   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
1943   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
1944   /* 78 */
1945   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
1946   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
1947   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
1948   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
1949   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
1950   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
1951   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
1952   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
1953   /* 80 */
1954   { REG_TABLE (REG_80) },
1955   { REG_TABLE (REG_81) },
1956   { X86_64_TABLE (X86_64_82) },
1957   { REG_TABLE (REG_83) },
1958   { "testB",            { Eb, Gb }, 0 },
1959   { "testS",            { Ev, Gv }, 0 },
1960   { "xchgB",            { Ebh2, Gb }, 0 },
1961   { "xchgS",            { Evh2, Gv }, 0 },
1962   /* 88 */
1963   { "movB",             { Ebh3, Gb }, 0 },
1964   { "movS",             { Evh3, Gv }, 0 },
1965   { "movB",             { Gb, EbS }, 0 },
1966   { "movS",             { Gv, EvS }, 0 },
1967   { "movD",             { Sv, Sw }, 0 },
1968   { MOD_TABLE (MOD_8D) },
1969   { "movD",             { Sw, Sv }, 0 },
1970   { REG_TABLE (REG_8F) },
1971   /* 90 */
1972   { PREFIX_TABLE (PREFIX_90) },
1973   { "xchgS",            { RMeCX, eAX }, 0 },
1974   { "xchgS",            { RMeDX, eAX }, 0 },
1975   { "xchgS",            { RMeBX, eAX }, 0 },
1976   { "xchgS",            { RMeSP, eAX }, 0 },
1977   { "xchgS",            { RMeBP, eAX }, 0 },
1978   { "xchgS",            { RMeSI, eAX }, 0 },
1979   { "xchgS",            { RMeDI, eAX }, 0 },
1980   /* 98 */
1981   { "cW{t|}R",          { XX }, 0 },
1982   { "cR{t|}O",          { XX }, 0 },
1983   { X86_64_TABLE (X86_64_9A) },
1984   { Bad_Opcode },       /* fwait */
1985   { "pushfP",           { XX }, 0 },
1986   { "popfP",            { XX }, 0 },
1987   { "sahf",             { XX }, 0 },
1988   { "lahf",             { XX }, 0 },
1989   /* a0 */
1990   { "mov%LB",           { AL, Ob }, 0 },
1991   { "mov%LS",           { eAX, Ov }, 0 },
1992   { "mov%LB",           { Ob, AL }, 0 },
1993   { "mov%LS",           { Ov, eAX }, 0 },
1994   { "movs{b|}",         { Ybr, Xb }, 0 },
1995   { "movs{R|}",         { Yvr, Xv }, 0 },
1996   { "cmps{b|}",         { Xb, Yb }, 0 },
1997   { "cmps{R|}",         { Xv, Yv }, 0 },
1998   /* a8 */
1999   { "testB",            { AL, Ib }, 0 },
2000   { "testS",            { eAX, Iv }, 0 },
2001   { "stosB",            { Ybr, AL }, 0 },
2002   { "stosS",            { Yvr, eAX }, 0 },
2003   { "lodsB",            { ALr, Xb }, 0 },
2004   { "lodsS",            { eAXr, Xv }, 0 },
2005   { "scasB",            { AL, Yb }, 0 },
2006   { "scasS",            { eAX, Yv }, 0 },
2007   /* b0 */
2008   { "movB",             { RMAL, Ib }, 0 },
2009   { "movB",             { RMCL, Ib }, 0 },
2010   { "movB",             { RMDL, Ib }, 0 },
2011   { "movB",             { RMBL, Ib }, 0 },
2012   { "movB",             { RMAH, Ib }, 0 },
2013   { "movB",             { RMCH, Ib }, 0 },
2014   { "movB",             { RMDH, Ib }, 0 },
2015   { "movB",             { RMBH, Ib }, 0 },
2016   /* b8 */
2017   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2018   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2019   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2020   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2021   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2022   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2023   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2024   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2025   /* c0 */
2026   { REG_TABLE (REG_C0) },
2027   { REG_TABLE (REG_C1) },
2028   { X86_64_TABLE (X86_64_C2) },
2029   { X86_64_TABLE (X86_64_C3) },
2030   { X86_64_TABLE (X86_64_C4) },
2031   { X86_64_TABLE (X86_64_C5) },
2032   { REG_TABLE (REG_C6) },
2033   { REG_TABLE (REG_C7) },
2034   /* c8 */
2035   { "enterP",           { Iw, Ib }, 0 },
2036   { "leaveP",           { XX }, 0 },
2037   { "{l|}ret{|f}%LP",   { Iw }, 0 },
2038   { "{l|}ret{|f}%LP",   { XX }, 0 },
2039   { "int3",             { XX }, 0 },
2040   { "int",              { Ib }, 0 },
2041   { X86_64_TABLE (X86_64_CE) },
2042   { "iret%LP",          { XX }, 0 },
2043   /* d0 */
2044   { REG_TABLE (REG_D0) },
2045   { REG_TABLE (REG_D1) },
2046   { REG_TABLE (REG_D2) },
2047   { REG_TABLE (REG_D3) },
2048   { X86_64_TABLE (X86_64_D4) },
2049   { X86_64_TABLE (X86_64_D5) },
2050   { Bad_Opcode },
2051   { "xlat",             { DSBX }, 0 },
2052   /* d8 */
2053   { FLOAT },
2054   { FLOAT },
2055   { FLOAT },
2056   { FLOAT },
2057   { FLOAT },
2058   { FLOAT },
2059   { FLOAT },
2060   { FLOAT },
2061   /* e0 */
2062   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2063   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2064   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2065   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2066   { "inB",              { AL, Ib }, 0 },
2067   { "inG",              { zAX, Ib }, 0 },
2068   { "outB",             { Ib, AL }, 0 },
2069   { "outG",             { Ib, zAX }, 0 },
2070   /* e8 */
2071   { X86_64_TABLE (X86_64_E8) },
2072   { X86_64_TABLE (X86_64_E9) },
2073   { X86_64_TABLE (X86_64_EA) },
2074   { "jmp",              { Jb, BND }, 0 },
2075   { "inB",              { AL, indirDX }, 0 },
2076   { "inG",              { zAX, indirDX }, 0 },
2077   { "outB",             { indirDX, AL }, 0 },
2078   { "outG",             { indirDX, zAX }, 0 },
2079   /* f0 */
2080   { Bad_Opcode },       /* lock prefix */
2081   { "icebp",            { XX }, 0 },
2082   { Bad_Opcode },       /* repne */
2083   { Bad_Opcode },       /* repz */
2084   { "hlt",              { XX }, 0 },
2085   { "cmc",              { XX }, 0 },
2086   { REG_TABLE (REG_F6) },
2087   { REG_TABLE (REG_F7) },
2088   /* f8 */
2089   { "clc",              { XX }, 0 },
2090   { "stc",              { XX }, 0 },
2091   { "cli",              { XX }, 0 },
2092   { "sti",              { XX }, 0 },
2093   { "cld",              { XX }, 0 },
2094   { "std",              { XX }, 0 },
2095   { REG_TABLE (REG_FE) },
2096   { REG_TABLE (REG_FF) },
2097 };
2098
2099 static const struct dis386 dis386_twobyte[] = {
2100   /* 00 */
2101   { REG_TABLE (REG_0F00 ) },
2102   { REG_TABLE (REG_0F01 ) },
2103   { "larS",             { Gv, Ew }, 0 },
2104   { "lslS",             { Gv, Ew }, 0 },
2105   { Bad_Opcode },
2106   { "syscall",          { XX }, 0 },
2107   { "clts",             { XX }, 0 },
2108   { "sysret%LQ",                { XX }, 0 },
2109   /* 08 */
2110   { "invd",             { XX }, 0 },
2111   { PREFIX_TABLE (PREFIX_0F09) },
2112   { Bad_Opcode },
2113   { "ud2",              { XX }, 0 },
2114   { Bad_Opcode },
2115   { REG_TABLE (REG_0F0D) },
2116   { "femms",            { XX }, 0 },
2117   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2118   /* 10 */
2119   { PREFIX_TABLE (PREFIX_0F10) },
2120   { PREFIX_TABLE (PREFIX_0F11) },
2121   { PREFIX_TABLE (PREFIX_0F12) },
2122   { MOD_TABLE (MOD_0F13) },
2123   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2124   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2125   { PREFIX_TABLE (PREFIX_0F16) },
2126   { MOD_TABLE (MOD_0F17) },
2127   /* 18 */
2128   { REG_TABLE (REG_0F18) },
2129   { "nopQ",             { Ev }, 0 },
2130   { PREFIX_TABLE (PREFIX_0F1A) },
2131   { PREFIX_TABLE (PREFIX_0F1B) },
2132   { PREFIX_TABLE (PREFIX_0F1C) },
2133   { "nopQ",             { Ev }, 0 },
2134   { PREFIX_TABLE (PREFIX_0F1E) },
2135   { "nopQ",             { Ev }, 0 },
2136   /* 20 */
2137   { "movZ",             { Em, Cm }, 0 },
2138   { "movZ",             { Em, Dm }, 0 },
2139   { "movZ",             { Cm, Em }, 0 },
2140   { "movZ",             { Dm, Em }, 0 },
2141   { X86_64_TABLE (X86_64_0F24) },
2142   { Bad_Opcode },
2143   { X86_64_TABLE (X86_64_0F26) },
2144   { Bad_Opcode },
2145   /* 28 */
2146   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2147   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2148   { PREFIX_TABLE (PREFIX_0F2A) },
2149   { PREFIX_TABLE (PREFIX_0F2B) },
2150   { PREFIX_TABLE (PREFIX_0F2C) },
2151   { PREFIX_TABLE (PREFIX_0F2D) },
2152   { PREFIX_TABLE (PREFIX_0F2E) },
2153   { PREFIX_TABLE (PREFIX_0F2F) },
2154   /* 30 */
2155   { "wrmsr",            { XX }, 0 },
2156   { "rdtsc",            { XX }, 0 },
2157   { "rdmsr",            { XX }, 0 },
2158   { "rdpmc",            { XX }, 0 },
2159   { "sysenter",         { SEP }, 0 },
2160   { "sysexit",          { SEP }, 0 },
2161   { Bad_Opcode },
2162   { "getsec",           { XX }, 0 },
2163   /* 38 */
2164   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2165   { Bad_Opcode },
2166   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2167   { Bad_Opcode },
2168   { Bad_Opcode },
2169   { Bad_Opcode },
2170   { Bad_Opcode },
2171   { Bad_Opcode },
2172   /* 40 */
2173   { "cmovoS",           { Gv, Ev }, 0 },
2174   { "cmovnoS",          { Gv, Ev }, 0 },
2175   { "cmovbS",           { Gv, Ev }, 0 },
2176   { "cmovaeS",          { Gv, Ev }, 0 },
2177   { "cmoveS",           { Gv, Ev }, 0 },
2178   { "cmovneS",          { Gv, Ev }, 0 },
2179   { "cmovbeS",          { Gv, Ev }, 0 },
2180   { "cmovaS",           { Gv, Ev }, 0 },
2181   /* 48 */
2182   { "cmovsS",           { Gv, Ev }, 0 },
2183   { "cmovnsS",          { Gv, Ev }, 0 },
2184   { "cmovpS",           { Gv, Ev }, 0 },
2185   { "cmovnpS",          { Gv, Ev }, 0 },
2186   { "cmovlS",           { Gv, Ev }, 0 },
2187   { "cmovgeS",          { Gv, Ev }, 0 },
2188   { "cmovleS",          { Gv, Ev }, 0 },
2189   { "cmovgS",           { Gv, Ev }, 0 },
2190   /* 50 */
2191   { MOD_TABLE (MOD_0F50) },
2192   { PREFIX_TABLE (PREFIX_0F51) },
2193   { PREFIX_TABLE (PREFIX_0F52) },
2194   { PREFIX_TABLE (PREFIX_0F53) },
2195   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2196   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2197   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2198   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2199   /* 58 */
2200   { PREFIX_TABLE (PREFIX_0F58) },
2201   { PREFIX_TABLE (PREFIX_0F59) },
2202   { PREFIX_TABLE (PREFIX_0F5A) },
2203   { PREFIX_TABLE (PREFIX_0F5B) },
2204   { PREFIX_TABLE (PREFIX_0F5C) },
2205   { PREFIX_TABLE (PREFIX_0F5D) },
2206   { PREFIX_TABLE (PREFIX_0F5E) },
2207   { PREFIX_TABLE (PREFIX_0F5F) },
2208   /* 60 */
2209   { PREFIX_TABLE (PREFIX_0F60) },
2210   { PREFIX_TABLE (PREFIX_0F61) },
2211   { PREFIX_TABLE (PREFIX_0F62) },
2212   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2213   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2214   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2215   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2216   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2217   /* 68 */
2218   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2219   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2220   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2221   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2222   { "punpcklqdq", { XM, EXx }, PREFIX_DATA },
2223   { "punpckhqdq", { XM, EXx }, PREFIX_DATA },
2224   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2225   { PREFIX_TABLE (PREFIX_0F6F) },
2226   /* 70 */
2227   { PREFIX_TABLE (PREFIX_0F70) },
2228   { REG_TABLE (REG_0F71) },
2229   { REG_TABLE (REG_0F72) },
2230   { REG_TABLE (REG_0F73) },
2231   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2232   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2233   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2234   { "emms",             { XX }, PREFIX_OPCODE },
2235   /* 78 */
2236   { PREFIX_TABLE (PREFIX_0F78) },
2237   { PREFIX_TABLE (PREFIX_0F79) },
2238   { Bad_Opcode },
2239   { Bad_Opcode },
2240   { PREFIX_TABLE (PREFIX_0F7C) },
2241   { PREFIX_TABLE (PREFIX_0F7D) },
2242   { PREFIX_TABLE (PREFIX_0F7E) },
2243   { PREFIX_TABLE (PREFIX_0F7F) },
2244   /* 80 */
2245   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2246   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2247   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2248   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2249   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2250   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2251   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2252   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2253   /* 88 */
2254   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2255   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2256   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2257   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2258   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2259   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2260   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2261   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2262   /* 90 */
2263   { "seto",             { Eb }, 0 },
2264   { "setno",            { Eb }, 0 },
2265   { "setb",             { Eb }, 0 },
2266   { "setae",            { Eb }, 0 },
2267   { "sete",             { Eb }, 0 },
2268   { "setne",            { Eb }, 0 },
2269   { "setbe",            { Eb }, 0 },
2270   { "seta",             { Eb }, 0 },
2271   /* 98 */
2272   { "sets",             { Eb }, 0 },
2273   { "setns",            { Eb }, 0 },
2274   { "setp",             { Eb }, 0 },
2275   { "setnp",            { Eb }, 0 },
2276   { "setl",             { Eb }, 0 },
2277   { "setge",            { Eb }, 0 },
2278   { "setle",            { Eb }, 0 },
2279   { "setg",             { Eb }, 0 },
2280   /* a0 */
2281   { "pushP",            { fs }, 0 },
2282   { "popP",             { fs }, 0 },
2283   { "cpuid",            { XX }, 0 },
2284   { "btS",              { Ev, Gv }, 0 },
2285   { "shldS",            { Ev, Gv, Ib }, 0 },
2286   { "shldS",            { Ev, Gv, CL }, 0 },
2287   { REG_TABLE (REG_0FA6) },
2288   { REG_TABLE (REG_0FA7) },
2289   /* a8 */
2290   { "pushP",            { gs }, 0 },
2291   { "popP",             { gs }, 0 },
2292   { "rsm",              { XX }, 0 },
2293   { "btsS",             { Evh1, Gv }, 0 },
2294   { "shrdS",            { Ev, Gv, Ib }, 0 },
2295   { "shrdS",            { Ev, Gv, CL }, 0 },
2296   { REG_TABLE (REG_0FAE) },
2297   { "imulS",            { Gv, Ev }, 0 },
2298   /* b0 */
2299   { "cmpxchgB",         { Ebh1, Gb }, 0 },
2300   { "cmpxchgS",         { Evh1, Gv }, 0 },
2301   { MOD_TABLE (MOD_0FB2) },
2302   { "btrS",             { Evh1, Gv }, 0 },
2303   { MOD_TABLE (MOD_0FB4) },
2304   { MOD_TABLE (MOD_0FB5) },
2305   { "movz{bR|x}",       { Gv, Eb }, 0 },
2306   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2307   /* b8 */
2308   { PREFIX_TABLE (PREFIX_0FB8) },
2309   { "ud1S",             { Gv, Ev }, 0 },
2310   { REG_TABLE (REG_0FBA) },
2311   { "btcS",             { Evh1, Gv }, 0 },
2312   { PREFIX_TABLE (PREFIX_0FBC) },
2313   { PREFIX_TABLE (PREFIX_0FBD) },
2314   { "movs{bR|x}",       { Gv, Eb }, 0 },
2315   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2316   /* c0 */
2317   { "xaddB",            { Ebh1, Gb }, 0 },
2318   { "xaddS",            { Evh1, Gv }, 0 },
2319   { PREFIX_TABLE (PREFIX_0FC2) },
2320   { MOD_TABLE (MOD_0FC3) },
2321   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
2322   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
2323   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
2324   { REG_TABLE (REG_0FC7) },
2325   /* c8 */
2326   { "bswap",            { RMeAX }, 0 },
2327   { "bswap",            { RMeCX }, 0 },
2328   { "bswap",            { RMeDX }, 0 },
2329   { "bswap",            { RMeBX }, 0 },
2330   { "bswap",            { RMeSP }, 0 },
2331   { "bswap",            { RMeBP }, 0 },
2332   { "bswap",            { RMeSI }, 0 },
2333   { "bswap",            { RMeDI }, 0 },
2334   /* d0 */
2335   { PREFIX_TABLE (PREFIX_0FD0) },
2336   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
2337   { "psrld",            { MX, EM }, PREFIX_OPCODE },
2338   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
2339   { "paddq",            { MX, EM }, PREFIX_OPCODE },
2340   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
2341   { PREFIX_TABLE (PREFIX_0FD6) },
2342   { MOD_TABLE (MOD_0FD7) },
2343   /* d8 */
2344   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
2345   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
2346   { "pminub",           { MX, EM }, PREFIX_OPCODE },
2347   { "pand",             { MX, EM }, PREFIX_OPCODE },
2348   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
2349   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
2350   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
2351   { "pandn",            { MX, EM }, PREFIX_OPCODE },
2352   /* e0 */
2353   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
2354   { "psraw",            { MX, EM }, PREFIX_OPCODE },
2355   { "psrad",            { MX, EM }, PREFIX_OPCODE },
2356   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
2357   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
2358   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
2359   { PREFIX_TABLE (PREFIX_0FE6) },
2360   { PREFIX_TABLE (PREFIX_0FE7) },
2361   /* e8 */
2362   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
2363   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
2364   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
2365   { "por",              { MX, EM }, PREFIX_OPCODE },
2366   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
2367   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
2368   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
2369   { "pxor",             { MX, EM }, PREFIX_OPCODE },
2370   /* f0 */
2371   { PREFIX_TABLE (PREFIX_0FF0) },
2372   { "psllw",            { MX, EM }, PREFIX_OPCODE },
2373   { "pslld",            { MX, EM }, PREFIX_OPCODE },
2374   { "psllq",            { MX, EM }, PREFIX_OPCODE },
2375   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
2376   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
2377   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
2378   { PREFIX_TABLE (PREFIX_0FF7) },
2379   /* f8 */
2380   { "psubb",            { MX, EM }, PREFIX_OPCODE },
2381   { "psubw",            { MX, EM }, PREFIX_OPCODE },
2382   { "psubd",            { MX, EM }, PREFIX_OPCODE },
2383   { "psubq",            { MX, EM }, PREFIX_OPCODE },
2384   { "paddb",            { MX, EM }, PREFIX_OPCODE },
2385   { "paddw",            { MX, EM }, PREFIX_OPCODE },
2386   { "paddd",            { MX, EM }, PREFIX_OPCODE },
2387   { "ud0S",             { Gv, Ev }, 0 },
2388 };
2389
2390 static const unsigned char onebyte_has_modrm[256] = {
2391   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2392   /*       -------------------------------        */
2393   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2394   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2395   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2396   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2397   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2398   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2399   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2400   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2401   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2402   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2403   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2404   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2405   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2406   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2407   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2408   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2409   /*       -------------------------------        */
2410   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2411 };
2412
2413 static const unsigned char twobyte_has_modrm[256] = {
2414   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2415   /*       -------------------------------        */
2416   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2417   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2418   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2419   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2420   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2421   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2422   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2423   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2424   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2425   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2426   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2427   /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2428   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2429   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2430   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2431   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1  /* ff */
2432   /*       -------------------------------        */
2433   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2434 };
2435
2436 static char obuf[100];
2437 static char *obufp;
2438 static char *mnemonicendp;
2439 static char scratchbuf[100];
2440 static unsigned char *start_codep;
2441 static unsigned char *insn_codep;
2442 static unsigned char *codep;
2443 static unsigned char *end_codep;
2444 static int last_lock_prefix;
2445 static int last_repz_prefix;
2446 static int last_repnz_prefix;
2447 static int last_data_prefix;
2448 static int last_addr_prefix;
2449 static int last_rex_prefix;
2450 static int last_seg_prefix;
2451 static int fwait_prefix;
2452 /* The active segment register prefix.  */
2453 static int active_seg_prefix;
2454 #define MAX_CODE_LENGTH 15
2455 /* We can up to 14 prefixes since the maximum instruction length is
2456    15bytes.  */
2457 static int all_prefixes[MAX_CODE_LENGTH - 1];
2458 static disassemble_info *the_info;
2459 static struct
2460   {
2461     int mod;
2462     int reg;
2463     int rm;
2464   }
2465 modrm;
2466 static unsigned char need_modrm;
2467 static struct
2468   {
2469     int scale;
2470     int index;
2471     int base;
2472   }
2473 sib;
2474 static struct
2475   {
2476     int register_specifier;
2477     int length;
2478     int prefix;
2479     int w;
2480     int evex;
2481     int r;
2482     int v;
2483     int mask_register_specifier;
2484     int zeroing;
2485     int ll;
2486     int b;
2487   }
2488 vex;
2489 static unsigned char need_vex;
2490
2491 struct op
2492   {
2493     const char *name;
2494     unsigned int len;
2495   };
2496
2497 /* If we are accessing mod/rm/reg without need_modrm set, then the
2498    values are stale.  Hitting this abort likely indicates that you
2499    need to update onebyte_has_modrm or twobyte_has_modrm.  */
2500 #define MODRM_CHECK  if (!need_modrm) abort ()
2501
2502 static const char **names64;
2503 static const char **names32;
2504 static const char **names16;
2505 static const char **names8;
2506 static const char **names8rex;
2507 static const char **names_seg;
2508 static const char *index64;
2509 static const char *index32;
2510 static const char **index16;
2511 static const char **names_bnd;
2512
2513 static const char *intel_names64[] = {
2514   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2515   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2516 };
2517 static const char *intel_names32[] = {
2518   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2519   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2520 };
2521 static const char *intel_names16[] = {
2522   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2523   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2524 };
2525 static const char *intel_names8[] = {
2526   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2527 };
2528 static const char *intel_names8rex[] = {
2529   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2530   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2531 };
2532 static const char *intel_names_seg[] = {
2533   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2534 };
2535 static const char *intel_index64 = "riz";
2536 static const char *intel_index32 = "eiz";
2537 static const char *intel_index16[] = {
2538   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2539 };
2540
2541 static const char *att_names64[] = {
2542   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2543   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2544 };
2545 static const char *att_names32[] = {
2546   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2547   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2548 };
2549 static const char *att_names16[] = {
2550   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2551   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2552 };
2553 static const char *att_names8[] = {
2554   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2555 };
2556 static const char *att_names8rex[] = {
2557   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2558   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2559 };
2560 static const char *att_names_seg[] = {
2561   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2562 };
2563 static const char *att_index64 = "%riz";
2564 static const char *att_index32 = "%eiz";
2565 static const char *att_index16[] = {
2566   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2567 };
2568
2569 static const char **names_mm;
2570 static const char *intel_names_mm[] = {
2571   "mm0", "mm1", "mm2", "mm3",
2572   "mm4", "mm5", "mm6", "mm7"
2573 };
2574 static const char *att_names_mm[] = {
2575   "%mm0", "%mm1", "%mm2", "%mm3",
2576   "%mm4", "%mm5", "%mm6", "%mm7"
2577 };
2578
2579 static const char *intel_names_bnd[] = {
2580   "bnd0", "bnd1", "bnd2", "bnd3"
2581 };
2582
2583 static const char *att_names_bnd[] = {
2584   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
2585 };
2586
2587 static const char **names_xmm;
2588 static const char *intel_names_xmm[] = {
2589   "xmm0", "xmm1", "xmm2", "xmm3",
2590   "xmm4", "xmm5", "xmm6", "xmm7",
2591   "xmm8", "xmm9", "xmm10", "xmm11",
2592   "xmm12", "xmm13", "xmm14", "xmm15",
2593   "xmm16", "xmm17", "xmm18", "xmm19",
2594   "xmm20", "xmm21", "xmm22", "xmm23",
2595   "xmm24", "xmm25", "xmm26", "xmm27",
2596   "xmm28", "xmm29", "xmm30", "xmm31"
2597 };
2598 static const char *att_names_xmm[] = {
2599   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2600   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2601   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2602   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
2603   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
2604   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
2605   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
2606   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
2607 };
2608
2609 static const char **names_ymm;
2610 static const char *intel_names_ymm[] = {
2611   "ymm0", "ymm1", "ymm2", "ymm3",
2612   "ymm4", "ymm5", "ymm6", "ymm7",
2613   "ymm8", "ymm9", "ymm10", "ymm11",
2614   "ymm12", "ymm13", "ymm14", "ymm15",
2615   "ymm16", "ymm17", "ymm18", "ymm19",
2616   "ymm20", "ymm21", "ymm22", "ymm23",
2617   "ymm24", "ymm25", "ymm26", "ymm27",
2618   "ymm28", "ymm29", "ymm30", "ymm31"
2619 };
2620 static const char *att_names_ymm[] = {
2621   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2622   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2623   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2624   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
2625   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
2626   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
2627   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
2628   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
2629 };
2630
2631 static const char **names_zmm;
2632 static const char *intel_names_zmm[] = {
2633   "zmm0", "zmm1", "zmm2", "zmm3",
2634   "zmm4", "zmm5", "zmm6", "zmm7",
2635   "zmm8", "zmm9", "zmm10", "zmm11",
2636   "zmm12", "zmm13", "zmm14", "zmm15",
2637   "zmm16", "zmm17", "zmm18", "zmm19",
2638   "zmm20", "zmm21", "zmm22", "zmm23",
2639   "zmm24", "zmm25", "zmm26", "zmm27",
2640   "zmm28", "zmm29", "zmm30", "zmm31"
2641 };
2642 static const char *att_names_zmm[] = {
2643   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
2644   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
2645   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
2646   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
2647   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
2648   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
2649   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
2650   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
2651 };
2652
2653 static const char **names_tmm;
2654 static const char *intel_names_tmm[] = {
2655   "tmm0", "tmm1", "tmm2", "tmm3",
2656   "tmm4", "tmm5", "tmm6", "tmm7"
2657 };
2658 static const char *att_names_tmm[] = {
2659   "%tmm0", "%tmm1", "%tmm2", "%tmm3",
2660   "%tmm4", "%tmm5", "%tmm6", "%tmm7"
2661 };
2662
2663 static const char **names_mask;
2664 static const char *intel_names_mask[] = {
2665   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
2666 };
2667 static const char *att_names_mask[] = {
2668   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
2669 };
2670
2671 static const char *names_rounding[] =
2672 {
2673   "{rn-sae}",
2674   "{rd-sae}",
2675   "{ru-sae}",
2676   "{rz-sae}"
2677 };
2678
2679 static const struct dis386 reg_table[][8] = {
2680   /* REG_80 */
2681   {
2682     { "addA",   { Ebh1, Ib }, 0 },
2683     { "orA",    { Ebh1, Ib }, 0 },
2684     { "adcA",   { Ebh1, Ib }, 0 },
2685     { "sbbA",   { Ebh1, Ib }, 0 },
2686     { "andA",   { Ebh1, Ib }, 0 },
2687     { "subA",   { Ebh1, Ib }, 0 },
2688     { "xorA",   { Ebh1, Ib }, 0 },
2689     { "cmpA",   { Eb, Ib }, 0 },
2690   },
2691   /* REG_81 */
2692   {
2693     { "addQ",   { Evh1, Iv }, 0 },
2694     { "orQ",    { Evh1, Iv }, 0 },
2695     { "adcQ",   { Evh1, Iv }, 0 },
2696     { "sbbQ",   { Evh1, Iv }, 0 },
2697     { "andQ",   { Evh1, Iv }, 0 },
2698     { "subQ",   { Evh1, Iv }, 0 },
2699     { "xorQ",   { Evh1, Iv }, 0 },
2700     { "cmpQ",   { Ev, Iv }, 0 },
2701   },
2702   /* REG_83 */
2703   {
2704     { "addQ",   { Evh1, sIb }, 0 },
2705     { "orQ",    { Evh1, sIb }, 0 },
2706     { "adcQ",   { Evh1, sIb }, 0 },
2707     { "sbbQ",   { Evh1, sIb }, 0 },
2708     { "andQ",   { Evh1, sIb }, 0 },
2709     { "subQ",   { Evh1, sIb }, 0 },
2710     { "xorQ",   { Evh1, sIb }, 0 },
2711     { "cmpQ",   { Ev, sIb }, 0 },
2712   },
2713   /* REG_8F */
2714   {
2715     { "pop{P|}", { stackEv }, 0 },
2716     { XOP_8F_TABLE (XOP_09) },
2717     { Bad_Opcode },
2718     { Bad_Opcode },
2719     { Bad_Opcode },
2720     { XOP_8F_TABLE (XOP_09) },
2721   },
2722   /* REG_C0 */
2723   {
2724     { "rolA",   { Eb, Ib }, 0 },
2725     { "rorA",   { Eb, Ib }, 0 },
2726     { "rclA",   { Eb, Ib }, 0 },
2727     { "rcrA",   { Eb, Ib }, 0 },
2728     { "shlA",   { Eb, Ib }, 0 },
2729     { "shrA",   { Eb, Ib }, 0 },
2730     { "shlA",   { Eb, Ib }, 0 },
2731     { "sarA",   { Eb, Ib }, 0 },
2732   },
2733   /* REG_C1 */
2734   {
2735     { "rolQ",   { Ev, Ib }, 0 },
2736     { "rorQ",   { Ev, Ib }, 0 },
2737     { "rclQ",   { Ev, Ib }, 0 },
2738     { "rcrQ",   { Ev, Ib }, 0 },
2739     { "shlQ",   { Ev, Ib }, 0 },
2740     { "shrQ",   { Ev, Ib }, 0 },
2741     { "shlQ",   { Ev, Ib }, 0 },
2742     { "sarQ",   { Ev, Ib }, 0 },
2743   },
2744   /* REG_C6 */
2745   {
2746     { "movA",   { Ebh3, Ib }, 0 },
2747     { Bad_Opcode },
2748     { Bad_Opcode },
2749     { Bad_Opcode },
2750     { Bad_Opcode },
2751     { Bad_Opcode },
2752     { Bad_Opcode },
2753     { MOD_TABLE (MOD_C6_REG_7) },
2754   },
2755   /* REG_C7 */
2756   {
2757     { "movQ",   { Evh3, Iv }, 0 },
2758     { Bad_Opcode },
2759     { Bad_Opcode },
2760     { Bad_Opcode },
2761     { Bad_Opcode },
2762     { Bad_Opcode },
2763     { Bad_Opcode },
2764     { MOD_TABLE (MOD_C7_REG_7) },
2765   },
2766   /* REG_D0 */
2767   {
2768     { "rolA",   { Eb, I1 }, 0 },
2769     { "rorA",   { Eb, I1 }, 0 },
2770     { "rclA",   { Eb, I1 }, 0 },
2771     { "rcrA",   { Eb, I1 }, 0 },
2772     { "shlA",   { Eb, I1 }, 0 },
2773     { "shrA",   { Eb, I1 }, 0 },
2774     { "shlA",   { Eb, I1 }, 0 },
2775     { "sarA",   { Eb, I1 }, 0 },
2776   },
2777   /* REG_D1 */
2778   {
2779     { "rolQ",   { Ev, I1 }, 0 },
2780     { "rorQ",   { Ev, I1 }, 0 },
2781     { "rclQ",   { Ev, I1 }, 0 },
2782     { "rcrQ",   { Ev, I1 }, 0 },
2783     { "shlQ",   { Ev, I1 }, 0 },
2784     { "shrQ",   { Ev, I1 }, 0 },
2785     { "shlQ",   { Ev, I1 }, 0 },
2786     { "sarQ",   { Ev, I1 }, 0 },
2787   },
2788   /* REG_D2 */
2789   {
2790     { "rolA",   { Eb, CL }, 0 },
2791     { "rorA",   { Eb, CL }, 0 },
2792     { "rclA",   { Eb, CL }, 0 },
2793     { "rcrA",   { Eb, CL }, 0 },
2794     { "shlA",   { Eb, CL }, 0 },
2795     { "shrA",   { Eb, CL }, 0 },
2796     { "shlA",   { Eb, CL }, 0 },
2797     { "sarA",   { Eb, CL }, 0 },
2798   },
2799   /* REG_D3 */
2800   {
2801     { "rolQ",   { Ev, CL }, 0 },
2802     { "rorQ",   { Ev, CL }, 0 },
2803     { "rclQ",   { Ev, CL }, 0 },
2804     { "rcrQ",   { Ev, CL }, 0 },
2805     { "shlQ",   { Ev, CL }, 0 },
2806     { "shrQ",   { Ev, CL }, 0 },
2807     { "shlQ",   { Ev, CL }, 0 },
2808     { "sarQ",   { Ev, CL }, 0 },
2809   },
2810   /* REG_F6 */
2811   {
2812     { "testA",  { Eb, Ib }, 0 },
2813     { "testA",  { Eb, Ib }, 0 },
2814     { "notA",   { Ebh1 }, 0 },
2815     { "negA",   { Ebh1 }, 0 },
2816     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
2817     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
2818     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
2819     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
2820   },
2821   /* REG_F7 */
2822   {
2823     { "testQ",  { Ev, Iv }, 0 },
2824     { "testQ",  { Ev, Iv }, 0 },
2825     { "notQ",   { Evh1 }, 0 },
2826     { "negQ",   { Evh1 }, 0 },
2827     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
2828     { "imulQ",  { Ev }, 0 },
2829     { "divQ",   { Ev }, 0 },
2830     { "idivQ",  { Ev }, 0 },
2831   },
2832   /* REG_FE */
2833   {
2834     { "incA",   { Ebh1 }, 0 },
2835     { "decA",   { Ebh1 }, 0 },
2836   },
2837   /* REG_FF */
2838   {
2839     { "incQ",   { Evh1 }, 0 },
2840     { "decQ",   { Evh1 }, 0 },
2841     { "call{@|}", { NOTRACK, indirEv, BND }, 0 },
2842     { MOD_TABLE (MOD_FF_REG_3) },
2843     { "jmp{@|}", { NOTRACK, indirEv, BND }, 0 },
2844     { MOD_TABLE (MOD_FF_REG_5) },
2845     { "push{P|}", { stackEv }, 0 },
2846     { Bad_Opcode },
2847   },
2848   /* REG_0F00 */
2849   {
2850     { "sldtD",  { Sv }, 0 },
2851     { "strD",   { Sv }, 0 },
2852     { "lldt",   { Ew }, 0 },
2853     { "ltr",    { Ew }, 0 },
2854     { "verr",   { Ew }, 0 },
2855     { "verw",   { Ew }, 0 },
2856     { Bad_Opcode },
2857     { Bad_Opcode },
2858   },
2859   /* REG_0F01 */
2860   {
2861     { MOD_TABLE (MOD_0F01_REG_0) },
2862     { MOD_TABLE (MOD_0F01_REG_1) },
2863     { MOD_TABLE (MOD_0F01_REG_2) },
2864     { MOD_TABLE (MOD_0F01_REG_3) },
2865     { "smswD",  { Sv }, 0 },
2866     { MOD_TABLE (MOD_0F01_REG_5) },
2867     { "lmsw",   { Ew }, 0 },
2868     { MOD_TABLE (MOD_0F01_REG_7) },
2869   },
2870   /* REG_0F0D */
2871   {
2872     { "prefetch",       { Mb }, 0 },
2873     { "prefetchw",      { Mb }, 0 },
2874     { "prefetchwt1",    { Mb }, 0 },
2875     { "prefetch",       { Mb }, 0 },
2876     { "prefetch",       { Mb }, 0 },
2877     { "prefetch",       { Mb }, 0 },
2878     { "prefetch",       { Mb }, 0 },
2879     { "prefetch",       { Mb }, 0 },
2880   },
2881   /* REG_0F18 */
2882   {
2883     { MOD_TABLE (MOD_0F18_REG_0) },
2884     { MOD_TABLE (MOD_0F18_REG_1) },
2885     { MOD_TABLE (MOD_0F18_REG_2) },
2886     { MOD_TABLE (MOD_0F18_REG_3) },
2887     { MOD_TABLE (MOD_0F18_REG_4) },
2888     { MOD_TABLE (MOD_0F18_REG_5) },
2889     { MOD_TABLE (MOD_0F18_REG_6) },
2890     { MOD_TABLE (MOD_0F18_REG_7) },
2891   },
2892   /* REG_0F1C_P_0_MOD_0 */
2893   {
2894     { "cldemote",       { Mb }, 0 },
2895     { "nopQ",           { Ev }, 0 },
2896     { "nopQ",           { Ev }, 0 },
2897     { "nopQ",           { Ev }, 0 },
2898     { "nopQ",           { Ev }, 0 },
2899     { "nopQ",           { Ev }, 0 },
2900     { "nopQ",           { Ev }, 0 },
2901     { "nopQ",           { Ev }, 0 },
2902   },
2903   /* REG_0F1E_P_1_MOD_3 */
2904   {
2905     { "nopQ",           { Ev }, 0 },
2906     { "rdsspK",         { Edq }, PREFIX_OPCODE },
2907     { "nopQ",           { Ev }, 0 },
2908     { "nopQ",           { Ev }, 0 },
2909     { "nopQ",           { Ev }, 0 },
2910     { "nopQ",           { Ev }, 0 },
2911     { "nopQ",           { Ev }, 0 },
2912     { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) },
2913   },
2914   /* REG_0F38D8_PREFIX_1 */
2915   {
2916     { "aesencwide128kl",        { M }, 0 },
2917     { "aesdecwide128kl",        { M }, 0 },
2918     { "aesencwide256kl",        { M }, 0 },
2919     { "aesdecwide256kl",        { M }, 0 },
2920   },
2921   /* REG_0F71 */
2922   {
2923     { Bad_Opcode },
2924     { Bad_Opcode },
2925     { MOD_TABLE (MOD_0F71_REG_2) },
2926     { Bad_Opcode },
2927     { MOD_TABLE (MOD_0F71_REG_4) },
2928     { Bad_Opcode },
2929     { MOD_TABLE (MOD_0F71_REG_6) },
2930   },
2931   /* REG_0F72 */
2932   {
2933     { Bad_Opcode },
2934     { Bad_Opcode },
2935     { MOD_TABLE (MOD_0F72_REG_2) },
2936     { Bad_Opcode },
2937     { MOD_TABLE (MOD_0F72_REG_4) },
2938     { Bad_Opcode },
2939     { MOD_TABLE (MOD_0F72_REG_6) },
2940   },
2941   /* REG_0F73 */
2942   {
2943     { Bad_Opcode },
2944     { Bad_Opcode },
2945     { MOD_TABLE (MOD_0F73_REG_2) },
2946     { MOD_TABLE (MOD_0F73_REG_3) },
2947     { Bad_Opcode },
2948     { Bad_Opcode },
2949     { MOD_TABLE (MOD_0F73_REG_6) },
2950     { MOD_TABLE (MOD_0F73_REG_7) },
2951   },
2952   /* REG_0FA6 */
2953   {
2954     { "montmul",        { { OP_0f07, 0 } }, 0 },
2955     { "xsha1",          { { OP_0f07, 0 } }, 0 },
2956     { "xsha256",        { { OP_0f07, 0 } }, 0 },
2957   },
2958   /* REG_0FA7 */
2959   {
2960     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
2961     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
2962     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
2963     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
2964     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
2965     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
2966   },
2967   /* REG_0FAE */
2968   {
2969     { MOD_TABLE (MOD_0FAE_REG_0) },
2970     { MOD_TABLE (MOD_0FAE_REG_1) },
2971     { MOD_TABLE (MOD_0FAE_REG_2) },
2972     { MOD_TABLE (MOD_0FAE_REG_3) },
2973     { MOD_TABLE (MOD_0FAE_REG_4) },
2974     { MOD_TABLE (MOD_0FAE_REG_5) },
2975     { MOD_TABLE (MOD_0FAE_REG_6) },
2976     { MOD_TABLE (MOD_0FAE_REG_7) },
2977   },
2978   /* REG_0FBA */
2979   {
2980     { Bad_Opcode },
2981     { Bad_Opcode },
2982     { Bad_Opcode },
2983     { Bad_Opcode },
2984     { "btQ",    { Ev, Ib }, 0 },
2985     { "btsQ",   { Evh1, Ib }, 0 },
2986     { "btrQ",   { Evh1, Ib }, 0 },
2987     { "btcQ",   { Evh1, Ib }, 0 },
2988   },
2989   /* REG_0FC7 */
2990   {
2991     { Bad_Opcode },
2992     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
2993     { Bad_Opcode },
2994     { MOD_TABLE (MOD_0FC7_REG_3) },
2995     { MOD_TABLE (MOD_0FC7_REG_4) },
2996     { MOD_TABLE (MOD_0FC7_REG_5) },
2997     { MOD_TABLE (MOD_0FC7_REG_6) },
2998     { MOD_TABLE (MOD_0FC7_REG_7) },
2999   },
3000   /* REG_VEX_0F71 */
3001   {
3002     { Bad_Opcode },
3003     { Bad_Opcode },
3004     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3005     { Bad_Opcode },
3006     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3007     { Bad_Opcode },
3008     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3009   },
3010   /* REG_VEX_0F72 */
3011   {
3012     { Bad_Opcode },
3013     { Bad_Opcode },
3014     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3015     { Bad_Opcode },
3016     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3017     { Bad_Opcode },
3018     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3019   },
3020   /* REG_VEX_0F73 */
3021   {
3022     { Bad_Opcode },
3023     { Bad_Opcode },
3024     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3025     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3026     { Bad_Opcode },
3027     { Bad_Opcode },
3028     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3029     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3030   },
3031   /* REG_VEX_0FAE */
3032   {
3033     { Bad_Opcode },
3034     { Bad_Opcode },
3035     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3036     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3037   },
3038   /* REG_VEX_0F3849_X86_64_P_0_W_0_M_1 */
3039   {
3040     { RM_TABLE (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0) },
3041   },
3042   /* REG_VEX_0F38F3 */
3043   {
3044     { Bad_Opcode },
3045     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1) },
3046     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2) },
3047     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3) },
3048   },
3049   /* REG_0FXOP_09_01_L_0 */
3050   {
3051     { Bad_Opcode },
3052     { "blcfill",        { VexGdq, Edq }, 0 },
3053     { "blsfill",        { VexGdq, Edq }, 0 },
3054     { "blcs",   { VexGdq, Edq }, 0 },
3055     { "tzmsk",  { VexGdq, Edq }, 0 },
3056     { "blcic",  { VexGdq, Edq }, 0 },
3057     { "blsic",  { VexGdq, Edq }, 0 },
3058     { "t1mskc", { VexGdq, Edq }, 0 },
3059   },
3060   /* REG_0FXOP_09_02_L_0 */
3061   {
3062     { Bad_Opcode },
3063     { "blcmsk", { VexGdq, Edq }, 0 },
3064     { Bad_Opcode },
3065     { Bad_Opcode },
3066     { Bad_Opcode },
3067     { Bad_Opcode },
3068     { "blci",   { VexGdq, Edq }, 0 },
3069   },
3070   /* REG_0FXOP_09_12_M_1_L_0 */
3071   {
3072     { "llwpcb", { Edq }, 0 },
3073     { "slwpcb", { Edq }, 0 },
3074   },
3075   /* REG_0FXOP_0A_12_L_0 */
3076   {
3077     { "lwpins", { VexGdq, Ed, Id }, 0 },
3078     { "lwpval", { VexGdq, Ed, Id }, 0 },
3079   },
3080
3081 #include "i386-dis-evex-reg.h"
3082 };
3083
3084 static const struct dis386 prefix_table[][4] = {
3085   /* PREFIX_90 */
3086   {
3087     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3088     { "pause", { XX }, 0 },
3089     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3090     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3091   },
3092
3093   /* PREFIX_0F01_REG_1_RM_4 */
3094   {
3095     { Bad_Opcode },
3096     { Bad_Opcode },
3097     { "tdcall",         { Skip_MODRM }, 0 },
3098     { Bad_Opcode },
3099   },
3100
3101   /* PREFIX_0F01_REG_1_RM_5 */
3102   {
3103     { Bad_Opcode },
3104     { Bad_Opcode },
3105     { X86_64_TABLE (X86_64_0F01_REG_1_RM_5_PREFIX_2) },
3106     { Bad_Opcode },
3107   },
3108
3109   /* PREFIX_0F01_REG_1_RM_6 */
3110   {
3111     { Bad_Opcode },
3112     { Bad_Opcode },
3113     { X86_64_TABLE (X86_64_0F01_REG_1_RM_6_PREFIX_2) },
3114     { Bad_Opcode },
3115   },
3116
3117   /* PREFIX_0F01_REG_1_RM_7 */
3118   {
3119     { "encls",          { Skip_MODRM }, 0 },
3120     { Bad_Opcode },
3121     { X86_64_TABLE (X86_64_0F01_REG_1_RM_7_PREFIX_2) },
3122     { Bad_Opcode },
3123   },
3124
3125   /* PREFIX_0F01_REG_3_RM_1 */
3126   {
3127     { "vmmcall",        { Skip_MODRM }, 0 },
3128     { "vmgexit",        { Skip_MODRM }, 0 },
3129     { Bad_Opcode },
3130     { "vmgexit",        { Skip_MODRM }, 0 },
3131   },
3132
3133   /* PREFIX_0F01_REG_5_MOD_0 */
3134   {
3135     { Bad_Opcode },
3136     { "rstorssp",       { Mq }, PREFIX_OPCODE },
3137   },
3138
3139   /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3140   {
3141     { "serialize",      { Skip_MODRM }, PREFIX_OPCODE },
3142     { "setssbsy",       { Skip_MODRM }, PREFIX_OPCODE },
3143     { Bad_Opcode },
3144     { "xsusldtrk",      { Skip_MODRM }, PREFIX_OPCODE },
3145   },
3146
3147   /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
3148   {
3149     { Bad_Opcode },
3150     { Bad_Opcode },
3151     { Bad_Opcode },
3152     { "xresldtrk",     { Skip_MODRM }, PREFIX_OPCODE },
3153   },
3154
3155   /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3156   {
3157     { Bad_Opcode },
3158     { "saveprevssp",    { Skip_MODRM }, PREFIX_OPCODE },
3159   },
3160
3161   /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3162   {
3163     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
3164     { "mcommit",        { Skip_MODRM }, 0 },
3165   },
3166
3167   /* PREFIX_0F09 */
3168   {
3169     { "wbinvd",   { XX }, 0 },
3170     { "wbnoinvd", { XX }, 0 },
3171   },
3172
3173   /* PREFIX_0F10 */
3174   {
3175     { "movups", { XM, EXx }, PREFIX_OPCODE },
3176     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3177     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3178     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3179   },
3180
3181   /* PREFIX_0F11 */
3182   {
3183     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3184     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3185     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3186     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3187   },
3188
3189   /* PREFIX_0F12 */
3190   {
3191     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3192     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3193     { MOD_TABLE (MOD_0F12_PREFIX_2) },
3194     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3195   },
3196
3197   /* PREFIX_0F16 */
3198   {
3199     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3200     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3201     { MOD_TABLE (MOD_0F16_PREFIX_2) },
3202   },
3203
3204   /* PREFIX_0F1A */
3205   {
3206     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3207     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3208     { "bndmov", { Gbnd, Ebnd }, 0 },
3209     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3210   },
3211
3212   /* PREFIX_0F1B */
3213   {
3214     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3215     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3216     { "bndmov", { EbndS, Gbnd }, 0 },
3217     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3218   },
3219
3220   /* PREFIX_0F1C */
3221   {
3222     { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3223     { "nopQ",   { Ev }, PREFIX_OPCODE },
3224     { "nopQ",   { Ev }, PREFIX_OPCODE },
3225     { "nopQ",   { Ev }, PREFIX_OPCODE },
3226   },
3227
3228   /* PREFIX_0F1E */
3229   {
3230     { "nopQ",   { Ev }, PREFIX_OPCODE },
3231     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3232     { "nopQ",   { Ev }, PREFIX_OPCODE },
3233     { "nopQ",   { Ev }, PREFIX_OPCODE },
3234   },
3235
3236   /* PREFIX_0F2A */
3237   {
3238     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3239     { "cvtsi2ss{%LQ|}", { XM, Edq }, PREFIX_OPCODE },
3240     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3241     { "cvtsi2sd{%LQ|}", { XM, Edq }, 0 },
3242   },
3243
3244   /* PREFIX_0F2B */
3245   {
3246     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3247     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3248     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3249     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3250   },
3251
3252   /* PREFIX_0F2C */
3253   {
3254     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3255     { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
3256     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3257     { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3258   },
3259
3260   /* PREFIX_0F2D */
3261   {
3262     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3263     { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
3264     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3265     { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3266   },
3267
3268   /* PREFIX_0F2E */
3269   {
3270     { "ucomiss",{ XM, EXd }, 0 },
3271     { Bad_Opcode },
3272     { "ucomisd",{ XM, EXq }, 0 },
3273   },
3274
3275   /* PREFIX_0F2F */
3276   {
3277     { "comiss", { XM, EXd }, 0 },
3278     { Bad_Opcode },
3279     { "comisd", { XM, EXq }, 0 },
3280   },
3281
3282   /* PREFIX_0F51 */
3283   {
3284     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3285     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3286     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3287     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3288   },
3289
3290   /* PREFIX_0F52 */
3291   {
3292     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3293     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3294   },
3295
3296   /* PREFIX_0F53 */
3297   {
3298     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3299     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3300   },
3301
3302   /* PREFIX_0F58 */
3303   {
3304     { "addps", { XM, EXx }, PREFIX_OPCODE },
3305     { "addss", { XM, EXd }, PREFIX_OPCODE },
3306     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3307     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3308   },
3309
3310   /* PREFIX_0F59 */
3311   {
3312     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3313     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3314     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3315     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3316   },
3317
3318   /* PREFIX_0F5A */
3319   {
3320     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3321     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3322     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3323     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3324   },
3325
3326   /* PREFIX_0F5B */
3327   {
3328     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3329     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3330     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3331   },
3332
3333   /* PREFIX_0F5C */
3334   {
3335     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3336     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3337     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3338     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3339   },
3340
3341   /* PREFIX_0F5D */
3342   {
3343     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3344     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3345     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3346     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3347   },
3348
3349   /* PREFIX_0F5E */
3350   {
3351     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3352     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3353     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3354     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3355   },
3356
3357   /* PREFIX_0F5F */
3358   {
3359     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3360     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3361     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3362     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3363   },
3364
3365   /* PREFIX_0F60 */
3366   {
3367     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3368     { Bad_Opcode },
3369     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3370   },
3371
3372   /* PREFIX_0F61 */
3373   {
3374     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3375     { Bad_Opcode },
3376     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3377   },
3378
3379   /* PREFIX_0F62 */
3380   {
3381     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3382     { Bad_Opcode },
3383     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3384   },
3385
3386   /* PREFIX_0F6F */
3387   {
3388     { "movq",   { MX, EM }, PREFIX_OPCODE },
3389     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3390     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3391   },
3392
3393   /* PREFIX_0F70 */
3394   {
3395     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3396     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3397     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3398     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3399   },
3400
3401   /* PREFIX_0F78 */
3402   {
3403     {"vmread",  { Em, Gm }, 0 },
3404     { Bad_Opcode },
3405     {"extrq",   { XS, Ib, Ib }, 0 },
3406     {"insertq", { XM, XS, Ib, Ib }, 0 },
3407   },
3408
3409   /* PREFIX_0F79 */
3410   {
3411     {"vmwrite", { Gm, Em }, 0 },
3412     { Bad_Opcode },
3413     {"extrq",   { XM, XS }, 0 },
3414     {"insertq", { XM, XS }, 0 },
3415   },
3416
3417   /* PREFIX_0F7C */
3418   {
3419     { Bad_Opcode },
3420     { Bad_Opcode },
3421     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3422     { "haddps", { XM, EXx }, PREFIX_OPCODE },
3423   },
3424
3425   /* PREFIX_0F7D */
3426   {
3427     { Bad_Opcode },
3428     { Bad_Opcode },
3429     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3430     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3431   },
3432
3433   /* PREFIX_0F7E */
3434   {
3435     { "movK",   { Edq, MX }, PREFIX_OPCODE },
3436     { "movq",   { XM, EXq }, PREFIX_OPCODE },
3437     { "movK",   { Edq, XM }, PREFIX_OPCODE },
3438   },
3439
3440   /* PREFIX_0F7F */
3441   {
3442     { "movq",   { EMS, MX }, PREFIX_OPCODE },
3443     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3444     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3445   },
3446
3447   /* PREFIX_0FAE_REG_0_MOD_3 */
3448   {
3449     { Bad_Opcode },
3450     { "rdfsbase", { Ev }, 0 },
3451   },
3452
3453   /* PREFIX_0FAE_REG_1_MOD_3 */
3454   {
3455     { Bad_Opcode },
3456     { "rdgsbase", { Ev }, 0 },
3457   },
3458
3459   /* PREFIX_0FAE_REG_2_MOD_3 */
3460   {
3461     { Bad_Opcode },
3462     { "wrfsbase", { Ev }, 0 },
3463   },
3464
3465   /* PREFIX_0FAE_REG_3_MOD_3 */
3466   {
3467     { Bad_Opcode },
3468     { "wrgsbase", { Ev }, 0 },
3469   },
3470
3471   /* PREFIX_0FAE_REG_4_MOD_0 */
3472   {
3473     { "xsave",  { FXSAVE }, 0 },
3474     { "ptwrite{%LQ|}", { Edq }, 0 },
3475   },
3476
3477   /* PREFIX_0FAE_REG_4_MOD_3 */
3478   {
3479     { Bad_Opcode },
3480     { "ptwrite{%LQ|}", { Edq }, 0 },
3481   },
3482
3483   /* PREFIX_0FAE_REG_5_MOD_3 */
3484   {
3485     { "lfence",         { Skip_MODRM }, 0 },
3486     { "incsspK",        { Edq }, PREFIX_OPCODE },
3487   },
3488
3489   /* PREFIX_0FAE_REG_6_MOD_0 */
3490   {
3491     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE },
3492     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
3493     { "clwb",   { Mb }, PREFIX_OPCODE },
3494   },
3495
3496   /* PREFIX_0FAE_REG_6_MOD_3 */
3497   {
3498     { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) },
3499     { "umonitor",       { Eva }, PREFIX_OPCODE },
3500     { "tpause", { Edq }, PREFIX_OPCODE },
3501     { "umwait", { Edq }, PREFIX_OPCODE },
3502   },
3503
3504   /* PREFIX_0FAE_REG_7_MOD_0 */
3505   {
3506     { "clflush",        { Mb }, 0 },
3507     { Bad_Opcode },
3508     { "clflushopt",     { Mb }, 0 },
3509   },
3510
3511   /* PREFIX_0FB8 */
3512   {
3513     { Bad_Opcode },
3514     { "popcntS", { Gv, Ev }, 0 },
3515   },
3516
3517   /* PREFIX_0FBC */
3518   {
3519     { "bsfS",   { Gv, Ev }, 0 },
3520     { "tzcntS", { Gv, Ev }, 0 },
3521     { "bsfS",   { Gv, Ev }, 0 },
3522   },
3523
3524   /* PREFIX_0FBD */
3525   {
3526     { "bsrS",   { Gv, Ev }, 0 },
3527     { "lzcntS", { Gv, Ev }, 0 },
3528     { "bsrS",   { Gv, Ev }, 0 },
3529   },
3530
3531   /* PREFIX_0FC2 */
3532   {
3533     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
3534     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
3535     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
3536     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
3537   },
3538
3539   /* PREFIX_0FC7_REG_6_MOD_0 */
3540   {
3541     { "vmptrld",{ Mq }, 0 },
3542     { "vmxon",  { Mq }, 0 },
3543     { "vmclear",{ Mq }, 0 },
3544   },
3545
3546   /* PREFIX_0FC7_REG_6_MOD_3 */
3547   {
3548     { "rdrand", { Ev }, 0 },
3549     { Bad_Opcode },
3550     { "rdrand", { Ev }, 0 }
3551   },
3552
3553   /* PREFIX_0FC7_REG_7_MOD_3 */
3554   {
3555     { "rdseed", { Ev }, 0 },
3556     { "rdpid",  { Em }, 0 },
3557     { "rdseed", { Ev }, 0 },
3558   },
3559
3560   /* PREFIX_0FD0 */
3561   {
3562     { Bad_Opcode },
3563     { Bad_Opcode },
3564     { "addsubpd", { XM, EXx }, 0 },
3565     { "addsubps", { XM, EXx }, 0 },
3566   },
3567
3568   /* PREFIX_0FD6 */
3569   {
3570     { Bad_Opcode },
3571     { "movq2dq",{ XM, MS }, 0 },
3572     { "movq",   { EXqS, XM }, 0 },
3573     { "movdq2q",{ MX, XS }, 0 },
3574   },
3575
3576   /* PREFIX_0FE6 */
3577   {
3578     { Bad_Opcode },
3579     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
3580     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
3581     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
3582   },
3583
3584   /* PREFIX_0FE7 */
3585   {
3586     { "movntq", { Mq, MX }, PREFIX_OPCODE },
3587     { Bad_Opcode },
3588     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
3589   },
3590
3591   /* PREFIX_0FF0 */
3592   {
3593     { Bad_Opcode },
3594     { Bad_Opcode },
3595     { Bad_Opcode },
3596     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
3597   },
3598
3599   /* PREFIX_0FF7 */
3600   {
3601     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
3602     { Bad_Opcode },
3603     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
3604   },
3605
3606   /* PREFIX_0F38D8 */
3607   {
3608     { Bad_Opcode },
3609     { REG_TABLE (REG_0F38D8_PREFIX_1) },
3610   },
3611
3612   /* PREFIX_0F38DC */
3613   {
3614     { Bad_Opcode },
3615     { MOD_TABLE (MOD_0F38DC_PREFIX_1) },
3616     { "aesenc", { XM, EXx }, 0 },
3617   },
3618
3619   /* PREFIX_0F38DD */
3620   {
3621     { Bad_Opcode },
3622     { MOD_TABLE (MOD_0F38DD_PREFIX_1) },
3623     { "aesenclast", { XM, EXx }, 0 },
3624   },
3625
3626   /* PREFIX_0F38DE */
3627   {
3628     { Bad_Opcode },
3629     { MOD_TABLE (MOD_0F38DE_PREFIX_1) },
3630     { "aesdec", { XM, EXx }, 0 },
3631   },
3632
3633   /* PREFIX_0F38DF */
3634   {
3635     { Bad_Opcode },
3636     { MOD_TABLE (MOD_0F38DF_PREFIX_1) },
3637     { "aesdeclast", { XM, EXx }, 0 },
3638   },
3639
3640   /* PREFIX_0F38F0 */
3641   {
3642     { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3643     { Bad_Opcode },
3644     { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3645     { "crc32A", { Gdq, Eb }, PREFIX_OPCODE },
3646   },
3647
3648   /* PREFIX_0F38F1 */
3649   {
3650     { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3651     { Bad_Opcode },
3652     { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3653     { "crc32Q", { Gdq, Ev }, PREFIX_OPCODE },
3654   },
3655
3656   /* PREFIX_0F38F6 */
3657   {
3658     { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
3659     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
3660     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
3661     { Bad_Opcode },
3662   },
3663
3664   /* PREFIX_0F38F8 */
3665   {
3666     { Bad_Opcode },
3667     { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
3668     { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
3669     { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
3670   },
3671   /* PREFIX_0F38FA */
3672   {
3673     { Bad_Opcode },
3674     { MOD_TABLE (MOD_0F38FA_PREFIX_1) },
3675   },
3676
3677   /* PREFIX_0F38FB */
3678   {
3679     { Bad_Opcode },
3680     { MOD_TABLE (MOD_0F38FB_PREFIX_1) },
3681   },
3682
3683   /* PREFIX_VEX_0F10 */
3684   {
3685     { "vmovups",        { XM, EXx }, 0 },
3686     { "vmovss",         { XMScalar, VexScalarR, EXxmm_md }, 0 },
3687     { "vmovupd",        { XM, EXx }, 0 },
3688     { "vmovsd",         { XMScalar, VexScalarR, EXxmm_mq }, 0 },
3689   },
3690
3691   /* PREFIX_VEX_0F11 */
3692   {
3693     { "vmovups",        { EXxS, XM }, 0 },
3694     { "vmovss",         { EXdS, VexScalarR, XMScalar }, 0 },
3695     { "vmovupd",        { EXxS, XM }, 0 },
3696     { "vmovsd",         { EXqS, VexScalarR, XMScalar }, 0 },
3697   },
3698
3699   /* PREFIX_VEX_0F12 */
3700   {
3701     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
3702     { "vmovsldup",      { XM, EXx }, 0 },
3703     { MOD_TABLE (MOD_VEX_0F12_PREFIX_2) },
3704     { "vmovddup",       { XM, EXymmq }, 0 },
3705   },
3706
3707   /* PREFIX_VEX_0F16 */
3708   {
3709     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
3710     { "vmovshdup",      { XM, EXx }, 0 },
3711     { MOD_TABLE (MOD_VEX_0F16_PREFIX_2) },
3712   },
3713
3714   /* PREFIX_VEX_0F2A */
3715   {
3716     { Bad_Opcode },
3717     { "vcvtsi2ss{%LQ|}",        { XMScalar, VexScalar, Edq }, 0 },
3718     { Bad_Opcode },
3719     { "vcvtsi2sd{%LQ|}",        { XMScalar, VexScalar, Edq }, 0 },
3720   },
3721
3722   /* PREFIX_VEX_0F2C */
3723   {
3724     { Bad_Opcode },
3725     { "vcvttss2si",     { Gdq, EXxmm_md, EXxEVexS }, 0 },
3726     { Bad_Opcode },
3727     { "vcvttsd2si",     { Gdq, EXxmm_mq, EXxEVexS }, 0 },
3728   },
3729
3730   /* PREFIX_VEX_0F2D */
3731   {
3732     { Bad_Opcode },
3733     { "vcvtss2si",      { Gdq, EXxmm_md, EXxEVexR }, 0 },
3734     { Bad_Opcode },
3735     { "vcvtsd2si",      { Gdq, EXxmm_mq, EXxEVexR }, 0 },
3736   },
3737
3738   /* PREFIX_VEX_0F2E */
3739   {
3740     { "vucomisX",       { XMScalar, EXxmm_md, EXxEVexS }, PREFIX_OPCODE },
3741     { Bad_Opcode },
3742     { "vucomisX",       { XMScalar, EXxmm_mq, EXxEVexS }, PREFIX_OPCODE },
3743   },
3744
3745   /* PREFIX_VEX_0F2F */
3746   {
3747     { "vcomisX",        { XMScalar, EXxmm_md, EXxEVexS }, PREFIX_OPCODE },
3748     { Bad_Opcode },
3749     { "vcomisX",        { XMScalar, EXxmm_mq, EXxEVexS }, PREFIX_OPCODE },
3750   },
3751
3752   /* PREFIX_VEX_0F41 */
3753   {
3754     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
3755     { Bad_Opcode },
3756     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
3757   },
3758
3759   /* PREFIX_VEX_0F42 */
3760   {
3761     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
3762     { Bad_Opcode },
3763     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
3764   },
3765
3766   /* PREFIX_VEX_0F44 */
3767   {
3768     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
3769     { Bad_Opcode },
3770     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
3771   },
3772
3773   /* PREFIX_VEX_0F45 */
3774   {
3775     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
3776     { Bad_Opcode },
3777     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
3778   },
3779
3780   /* PREFIX_VEX_0F46 */
3781   {
3782     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
3783     { Bad_Opcode },
3784     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
3785   },
3786
3787   /* PREFIX_VEX_0F47 */
3788   {
3789     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
3790     { Bad_Opcode },
3791     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
3792   },
3793
3794   /* PREFIX_VEX_0F4A */
3795   {
3796     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
3797     { Bad_Opcode },
3798     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
3799   },
3800
3801   /* PREFIX_VEX_0F4B */
3802   {
3803     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
3804     { Bad_Opcode },
3805     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
3806   },
3807
3808   /* PREFIX_VEX_0F51 */
3809   {
3810     { "vsqrtps",        { XM, EXx }, 0 },
3811     { "vsqrtss",        { XMScalar, VexScalar, EXxmm_md }, 0 },
3812     { "vsqrtpd",        { XM, EXx }, 0 },
3813     { "vsqrtsd",        { XMScalar, VexScalar, EXxmm_mq }, 0 },
3814   },
3815
3816   /* PREFIX_VEX_0F52 */
3817   {
3818     { "vrsqrtps",       { XM, EXx }, 0 },
3819     { "vrsqrtss",       { XMScalar, VexScalar, EXxmm_md }, 0 },
3820   },
3821
3822   /* PREFIX_VEX_0F53 */
3823   {
3824     { "vrcpps",         { XM, EXx }, 0 },
3825     { "vrcpss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
3826   },
3827
3828   /* PREFIX_VEX_0F58 */
3829   {
3830     { "vaddps",         { XM, Vex, EXx }, 0 },
3831     { "vaddss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
3832     { "vaddpd",         { XM, Vex, EXx }, 0 },
3833     { "vaddsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
3834   },
3835
3836   /* PREFIX_VEX_0F59 */
3837   {
3838     { "vmulps",         { XM, Vex, EXx }, 0 },
3839     { "vmulss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
3840     { "vmulpd",         { XM, Vex, EXx }, 0 },
3841     { "vmulsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
3842   },
3843
3844   /* PREFIX_VEX_0F5A */
3845   {
3846     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
3847     { "vcvtss2sd",      { XMScalar, VexScalar, EXxmm_md }, 0 },
3848     { "vcvtpd2ps%XY",{ XMM, EXx }, 0 },
3849     { "vcvtsd2ss",      { XMScalar, VexScalar, EXxmm_mq }, 0 },
3850   },
3851
3852   /* PREFIX_VEX_0F5B */
3853   {
3854     { "vcvtdq2ps",      { XM, EXx }, 0 },
3855     { "vcvttps2dq",     { XM, EXx }, 0 },
3856     { "vcvtps2dq",      { XM, EXx }, 0 },
3857   },
3858
3859   /* PREFIX_VEX_0F5C */
3860   {
3861     { "vsubps",         { XM, Vex, EXx }, 0 },
3862     { "vsubss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
3863     { "vsubpd",         { XM, Vex, EXx }, 0 },
3864     { "vsubsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
3865   },
3866
3867   /* PREFIX_VEX_0F5D */
3868   {
3869     { "vminps",         { XM, Vex, EXx }, 0 },
3870     { "vminss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
3871     { "vminpd",         { XM, Vex, EXx }, 0 },
3872     { "vminsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
3873   },
3874
3875   /* PREFIX_VEX_0F5E */
3876   {
3877     { "vdivps",         { XM, Vex, EXx }, 0 },
3878     { "vdivss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
3879     { "vdivpd",         { XM, Vex, EXx }, 0 },
3880     { "vdivsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
3881   },
3882
3883   /* PREFIX_VEX_0F5F */
3884   {
3885     { "vmaxps",         { XM, Vex, EXx }, 0 },
3886     { "vmaxss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
3887     { "vmaxpd",         { XM, Vex, EXx }, 0 },
3888     { "vmaxsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
3889   },
3890
3891   /* PREFIX_VEX_0F6F */
3892   {
3893     { Bad_Opcode },
3894     { "vmovdqu",        { XM, EXx }, 0 },
3895     { "vmovdqa",        { XM, EXx }, 0 },
3896   },
3897
3898   /* PREFIX_VEX_0F70 */
3899   {
3900     { Bad_Opcode },
3901     { "vpshufhw",       { XM, EXx, Ib }, 0 },
3902     { "vpshufd",        { XM, EXx, Ib }, 0 },
3903     { "vpshuflw",       { XM, EXx, Ib }, 0 },
3904   },
3905
3906   /* PREFIX_VEX_0F7C */
3907   {
3908     { Bad_Opcode },
3909     { Bad_Opcode },
3910     { "vhaddpd",        { XM, Vex, EXx }, 0 },
3911     { "vhaddps",        { XM, Vex, EXx }, 0 },
3912   },
3913
3914   /* PREFIX_VEX_0F7D */
3915   {
3916     { Bad_Opcode },
3917     { Bad_Opcode },
3918     { "vhsubpd",        { XM, Vex, EXx }, 0 },
3919     { "vhsubps",        { XM, Vex, EXx }, 0 },
3920   },
3921
3922   /* PREFIX_VEX_0F7E */
3923   {
3924     { Bad_Opcode },
3925     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
3926     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
3927   },
3928
3929   /* PREFIX_VEX_0F7F */
3930   {
3931     { Bad_Opcode },
3932     { "vmovdqu",        { EXxS, XM }, 0 },
3933     { "vmovdqa",        { EXxS, XM }, 0 },
3934   },
3935
3936   /* PREFIX_VEX_0F90 */
3937   {
3938     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
3939     { Bad_Opcode },
3940     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
3941   },
3942
3943   /* PREFIX_VEX_0F91 */
3944   {
3945     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
3946     { Bad_Opcode },
3947     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
3948   },
3949
3950   /* PREFIX_VEX_0F92 */
3951   {
3952     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
3953     { Bad_Opcode },
3954     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
3955     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
3956   },
3957
3958   /* PREFIX_VEX_0F93 */
3959   {
3960     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
3961     { Bad_Opcode },
3962     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
3963     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
3964   },
3965
3966   /* PREFIX_VEX_0F98 */
3967   {
3968     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
3969     { Bad_Opcode },
3970     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
3971   },
3972
3973   /* PREFIX_VEX_0F99 */
3974   {
3975     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
3976     { Bad_Opcode },
3977     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
3978   },
3979
3980   /* PREFIX_VEX_0FC2 */
3981   {
3982     { "vcmpps",         { XM, Vex, EXx, CMP }, 0 },
3983     { "vcmpss",         { XMScalar, VexScalar, EXxmm_md, CMP }, 0 },
3984     { "vcmppd",         { XM, Vex, EXx, CMP }, 0 },
3985     { "vcmpsd",         { XMScalar, VexScalar, EXxmm_mq, CMP }, 0 },
3986   },
3987
3988   /* PREFIX_VEX_0FD0 */
3989   {
3990     { Bad_Opcode },
3991     { Bad_Opcode },
3992     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
3993     { "vaddsubps",      { XM, Vex, EXx }, 0 },
3994   },
3995
3996   /* PREFIX_VEX_0FE6 */
3997   {
3998     { Bad_Opcode },
3999     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
4000     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
4001     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
4002   },
4003
4004   /* PREFIX_VEX_0FF0 */
4005   {
4006     { Bad_Opcode },
4007     { Bad_Opcode },
4008     { Bad_Opcode },
4009     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
4010   },
4011
4012   /* PREFIX_VEX_0F3849_X86_64 */
4013   {
4014     { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_0) },
4015     { Bad_Opcode },
4016     { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_2) },
4017     { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_3) },
4018   },
4019
4020   /* PREFIX_VEX_0F384B_X86_64 */
4021   {
4022     { Bad_Opcode },
4023     { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_1) },
4024     { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_2) },
4025     { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_3) },
4026   },
4027
4028   /* PREFIX_VEX_0F385C_X86_64 */
4029   {
4030     { Bad_Opcode },
4031     { VEX_W_TABLE (VEX_W_0F385C_X86_64_P_1) },
4032     { Bad_Opcode },
4033   },
4034
4035   /* PREFIX_VEX_0F385E_X86_64 */
4036   {
4037     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_0) },
4038     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_1) },
4039     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_2) },
4040     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_3) },
4041   },
4042
4043   /* PREFIX_VEX_0F38F5 */
4044   {
4045     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
4046     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
4047     { Bad_Opcode },
4048     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
4049   },
4050
4051   /* PREFIX_VEX_0F38F6 */
4052   {
4053     { Bad_Opcode },
4054     { Bad_Opcode },
4055     { Bad_Opcode },
4056     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
4057   },
4058
4059   /* PREFIX_VEX_0F38F7 */
4060   {
4061     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
4062     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
4063     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
4064     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
4065   },
4066
4067   /* PREFIX_VEX_0F3AF0 */
4068   {
4069     { Bad_Opcode },
4070     { Bad_Opcode },
4071     { Bad_Opcode },
4072     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
4073   },
4074
4075 #include "i386-dis-evex-prefix.h"
4076 };
4077
4078 static const struct dis386 x86_64_table[][2] = {
4079   /* X86_64_06 */
4080   {
4081     { "pushP", { es }, 0 },
4082   },
4083
4084   /* X86_64_07 */
4085   {
4086     { "popP", { es }, 0 },
4087   },
4088
4089   /* X86_64_0E */
4090   {
4091     { "pushP", { cs }, 0 },
4092   },
4093
4094   /* X86_64_16 */
4095   {
4096     { "pushP", { ss }, 0 },
4097   },
4098
4099   /* X86_64_17 */
4100   {
4101     { "popP", { ss }, 0 },
4102   },
4103
4104   /* X86_64_1E */
4105   {
4106     { "pushP", { ds }, 0 },
4107   },
4108
4109   /* X86_64_1F */
4110   {
4111     { "popP", { ds }, 0 },
4112   },
4113
4114   /* X86_64_27 */
4115   {
4116     { "daa", { XX }, 0 },
4117   },
4118
4119   /* X86_64_2F */
4120   {
4121     { "das", { XX }, 0 },
4122   },
4123
4124   /* X86_64_37 */
4125   {
4126     { "aaa", { XX }, 0 },
4127   },
4128
4129   /* X86_64_3F */
4130   {
4131     { "aas", { XX }, 0 },
4132   },
4133
4134   /* X86_64_60 */
4135   {
4136     { "pushaP", { XX }, 0 },
4137   },
4138
4139   /* X86_64_61 */
4140   {
4141     { "popaP", { XX }, 0 },
4142   },
4143
4144   /* X86_64_62 */
4145   {
4146     { MOD_TABLE (MOD_62_32BIT) },
4147     { EVEX_TABLE (EVEX_0F) },
4148   },
4149
4150   /* X86_64_63 */
4151   {
4152     { "arpl", { Ew, Gw }, 0 },
4153     { "movs", { { OP_G, movsxd_mode }, { MOVSXD_Fixup, movsxd_mode } }, 0 },
4154   },
4155
4156   /* X86_64_6D */
4157   {
4158     { "ins{R|}", { Yzr, indirDX }, 0 },
4159     { "ins{G|}", { Yzr, indirDX }, 0 },
4160   },
4161
4162   /* X86_64_6F */
4163   {
4164     { "outs{R|}", { indirDXr, Xz }, 0 },
4165     { "outs{G|}", { indirDXr, Xz }, 0 },
4166   },
4167
4168   /* X86_64_82 */
4169   {
4170     /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
4171     { REG_TABLE (REG_80) },
4172   },
4173
4174   /* X86_64_9A */
4175   {
4176     { "{l|}call{P|}", { Ap }, 0 },
4177   },
4178
4179   /* X86_64_C2 */
4180   {
4181     { "retP",           { Iw, BND }, 0 },
4182     { "ret@",           { Iw, BND }, 0 },
4183   },
4184
4185   /* X86_64_C3 */
4186   {
4187     { "retP",           { BND }, 0 },
4188     { "ret@",           { BND }, 0 },
4189   },
4190
4191   /* X86_64_C4 */
4192   {
4193     { MOD_TABLE (MOD_C4_32BIT) },
4194     { VEX_C4_TABLE (VEX_0F) },
4195   },
4196
4197   /* X86_64_C5 */
4198   {
4199     { MOD_TABLE (MOD_C5_32BIT) },
4200     { VEX_C5_TABLE (VEX_0F) },
4201   },
4202
4203   /* X86_64_CE */
4204   {
4205     { "into", { XX }, 0 },
4206   },
4207
4208   /* X86_64_D4 */
4209   {
4210     { "aam", { Ib }, 0 },
4211   },
4212
4213   /* X86_64_D5 */
4214   {
4215     { "aad", { Ib }, 0 },
4216   },
4217
4218   /* X86_64_E8 */
4219   {
4220     { "callP",          { Jv, BND }, 0 },
4221     { "call@",          { Jv, BND }, 0 }
4222   },
4223
4224   /* X86_64_E9 */
4225   {
4226     { "jmpP",           { Jv, BND }, 0 },
4227     { "jmp@",           { Jv, BND }, 0 }
4228   },
4229
4230   /* X86_64_EA */
4231   {
4232     { "{l|}jmp{P|}", { Ap }, 0 },
4233   },
4234
4235   /* X86_64_0F01_REG_0 */
4236   {
4237     { "sgdt{Q|Q}", { M }, 0 },
4238     { "sgdt", { M }, 0 },
4239   },
4240
4241   /* X86_64_0F01_REG_1 */
4242   {
4243     { "sidt{Q|Q}", { M }, 0 },
4244     { "sidt", { M }, 0 },
4245   },
4246
4247   /* X86_64_0F01_REG_1_RM_5_PREFIX_2 */
4248   {
4249     { Bad_Opcode },
4250     { "seamret",        { Skip_MODRM }, 0 },
4251   },
4252
4253   /* X86_64_0F01_REG_1_RM_6_PREFIX_2 */
4254   {
4255     { Bad_Opcode },
4256     { "seamops",        { Skip_MODRM }, 0 },
4257   },
4258
4259   /* X86_64_0F01_REG_1_RM_7_PREFIX_2 */
4260   {
4261     { Bad_Opcode },
4262     { "seamcall",       { Skip_MODRM }, 0 },
4263   },
4264
4265   /* X86_64_0F01_REG_2 */
4266   {
4267     { "lgdt{Q|Q}", { M }, 0 },
4268     { "lgdt", { M }, 0 },
4269   },
4270
4271   /* X86_64_0F01_REG_3 */
4272   {
4273     { "lidt{Q|Q}", { M }, 0 },
4274     { "lidt", { M }, 0 },
4275   },
4276
4277   {
4278     /* X86_64_0F24 */
4279     { "movZ",           { Em, Td }, 0 },
4280   },
4281
4282   {
4283     /* X86_64_0F26 */
4284     { "movZ",           { Td, Em }, 0 },
4285   },
4286
4287   /* X86_64_VEX_0F3849 */
4288   {
4289     { Bad_Opcode },
4290     { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64) },
4291   },
4292
4293   /* X86_64_VEX_0F384B */
4294   {
4295     { Bad_Opcode },
4296     { PREFIX_TABLE (PREFIX_VEX_0F384B_X86_64) },
4297   },
4298
4299   /* X86_64_VEX_0F385C */
4300   {
4301     { Bad_Opcode },
4302     { PREFIX_TABLE (PREFIX_VEX_0F385C_X86_64) },
4303   },
4304
4305   /* X86_64_VEX_0F385E */
4306   {
4307     { Bad_Opcode },
4308     { PREFIX_TABLE (PREFIX_VEX_0F385E_X86_64) },
4309   },
4310 };
4311
4312 static const struct dis386 three_byte_table[][256] = {
4313
4314   /* THREE_BYTE_0F38 */
4315   {
4316     /* 00 */
4317     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
4318     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
4319     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
4320     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
4321     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
4322     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
4323     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
4324     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
4325     /* 08 */
4326     { "psignb",         { MX, EM }, PREFIX_OPCODE },
4327     { "psignw",         { MX, EM }, PREFIX_OPCODE },
4328     { "psignd",         { MX, EM }, PREFIX_OPCODE },
4329     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
4330     { Bad_Opcode },
4331     { Bad_Opcode },
4332     { Bad_Opcode },
4333     { Bad_Opcode },
4334     /* 10 */
4335     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_DATA },
4336     { Bad_Opcode },
4337     { Bad_Opcode },
4338     { Bad_Opcode },
4339     { "blendvps", { XM, EXx, XMM0 }, PREFIX_DATA },
4340     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_DATA },
4341     { Bad_Opcode },
4342     { "ptest",  { XM, EXx }, PREFIX_DATA },
4343     /* 18 */
4344     { Bad_Opcode },
4345     { Bad_Opcode },
4346     { Bad_Opcode },
4347     { Bad_Opcode },
4348     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
4349     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
4350     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
4351     { Bad_Opcode },
4352     /* 20 */
4353     { "pmovsxbw", { XM, EXq }, PREFIX_DATA },
4354     { "pmovsxbd", { XM, EXd }, PREFIX_DATA },
4355     { "pmovsxbq", { XM, EXw }, PREFIX_DATA },
4356     { "pmovsxwd", { XM, EXq }, PREFIX_DATA },
4357     { "pmovsxwq", { XM, EXd }, PREFIX_DATA },
4358     { "pmovsxdq", { XM, EXq }, PREFIX_DATA },
4359     { Bad_Opcode },
4360     { Bad_Opcode },
4361     /* 28 */
4362     { "pmuldq", { XM, EXx }, PREFIX_DATA },
4363     { "pcmpeqq", { XM, EXx }, PREFIX_DATA },
4364     { MOD_TABLE (MOD_0F382A) },
4365     { "packusdw", { XM, EXx }, PREFIX_DATA },
4366     { Bad_Opcode },
4367     { Bad_Opcode },
4368     { Bad_Opcode },
4369     { Bad_Opcode },
4370     /* 30 */
4371     { "pmovzxbw", { XM, EXq }, PREFIX_DATA },
4372     { "pmovzxbd", { XM, EXd }, PREFIX_DATA },
4373     { "pmovzxbq", { XM, EXw }, PREFIX_DATA },
4374     { "pmovzxwd", { XM, EXq }, PREFIX_DATA },
4375     { "pmovzxwq", { XM, EXd }, PREFIX_DATA },
4376     { "pmovzxdq", { XM, EXq }, PREFIX_DATA },
4377     { Bad_Opcode },
4378     { "pcmpgtq", { XM, EXx }, PREFIX_DATA },
4379     /* 38 */
4380     { "pminsb", { XM, EXx }, PREFIX_DATA },
4381     { "pminsd", { XM, EXx }, PREFIX_DATA },
4382     { "pminuw", { XM, EXx }, PREFIX_DATA },
4383     { "pminud", { XM, EXx }, PREFIX_DATA },
4384     { "pmaxsb", { XM, EXx }, PREFIX_DATA },
4385     { "pmaxsd", { XM, EXx }, PREFIX_DATA },
4386     { "pmaxuw", { XM, EXx }, PREFIX_DATA },
4387     { "pmaxud", { XM, EXx }, PREFIX_DATA },
4388     /* 40 */
4389     { "pmulld", { XM, EXx }, PREFIX_DATA },
4390     { "phminposuw", { XM, EXx }, PREFIX_DATA },
4391     { Bad_Opcode },
4392     { Bad_Opcode },
4393     { Bad_Opcode },
4394     { Bad_Opcode },
4395     { Bad_Opcode },
4396     { Bad_Opcode },
4397     /* 48 */
4398     { Bad_Opcode },
4399     { Bad_Opcode },
4400     { Bad_Opcode },
4401     { Bad_Opcode },
4402     { Bad_Opcode },
4403     { Bad_Opcode },
4404     { Bad_Opcode },
4405     { Bad_Opcode },
4406     /* 50 */
4407     { Bad_Opcode },
4408     { Bad_Opcode },
4409     { Bad_Opcode },
4410     { Bad_Opcode },
4411     { Bad_Opcode },
4412     { Bad_Opcode },
4413     { Bad_Opcode },
4414     { Bad_Opcode },
4415     /* 58 */
4416     { Bad_Opcode },
4417     { Bad_Opcode },
4418     { Bad_Opcode },
4419     { Bad_Opcode },
4420     { Bad_Opcode },
4421     { Bad_Opcode },
4422     { Bad_Opcode },
4423     { Bad_Opcode },
4424     /* 60 */
4425     { Bad_Opcode },
4426     { Bad_Opcode },
4427     { Bad_Opcode },
4428     { Bad_Opcode },
4429     { Bad_Opcode },
4430     { Bad_Opcode },
4431     { Bad_Opcode },
4432     { Bad_Opcode },
4433     /* 68 */
4434     { Bad_Opcode },
4435     { Bad_Opcode },
4436     { Bad_Opcode },
4437     { Bad_Opcode },
4438     { Bad_Opcode },
4439     { Bad_Opcode },
4440     { Bad_Opcode },
4441     { Bad_Opcode },
4442     /* 70 */
4443     { Bad_Opcode },
4444     { Bad_Opcode },
4445     { Bad_Opcode },
4446     { Bad_Opcode },
4447     { Bad_Opcode },
4448     { Bad_Opcode },
4449     { Bad_Opcode },
4450     { Bad_Opcode },
4451     /* 78 */
4452     { Bad_Opcode },
4453     { Bad_Opcode },
4454     { Bad_Opcode },
4455     { Bad_Opcode },
4456     { Bad_Opcode },
4457     { Bad_Opcode },
4458     { Bad_Opcode },
4459     { Bad_Opcode },
4460     /* 80 */
4461     { "invept", { Gm, Mo }, PREFIX_DATA },
4462     { "invvpid", { Gm, Mo }, PREFIX_DATA },
4463     { "invpcid", { Gm, M }, PREFIX_DATA },
4464     { Bad_Opcode },
4465     { Bad_Opcode },
4466     { Bad_Opcode },
4467     { Bad_Opcode },
4468     { Bad_Opcode },
4469     /* 88 */
4470     { Bad_Opcode },
4471     { Bad_Opcode },
4472     { Bad_Opcode },
4473     { Bad_Opcode },
4474     { Bad_Opcode },
4475     { Bad_Opcode },
4476     { Bad_Opcode },
4477     { Bad_Opcode },
4478     /* 90 */
4479     { Bad_Opcode },
4480     { Bad_Opcode },
4481     { Bad_Opcode },
4482     { Bad_Opcode },
4483     { Bad_Opcode },
4484     { Bad_Opcode },
4485     { Bad_Opcode },
4486     { Bad_Opcode },
4487     /* 98 */
4488     { Bad_Opcode },
4489     { Bad_Opcode },
4490     { Bad_Opcode },
4491     { Bad_Opcode },
4492     { Bad_Opcode },
4493     { Bad_Opcode },
4494     { Bad_Opcode },
4495     { Bad_Opcode },
4496     /* a0 */
4497     { Bad_Opcode },
4498     { Bad_Opcode },
4499     { Bad_Opcode },
4500     { Bad_Opcode },
4501     { Bad_Opcode },
4502     { Bad_Opcode },
4503     { Bad_Opcode },
4504     { Bad_Opcode },
4505     /* a8 */
4506     { Bad_Opcode },
4507     { Bad_Opcode },
4508     { Bad_Opcode },
4509     { Bad_Opcode },
4510     { Bad_Opcode },
4511     { Bad_Opcode },
4512     { Bad_Opcode },
4513     { Bad_Opcode },
4514     /* b0 */
4515     { Bad_Opcode },
4516     { Bad_Opcode },
4517     { Bad_Opcode },
4518     { Bad_Opcode },
4519     { Bad_Opcode },
4520     { Bad_Opcode },
4521     { Bad_Opcode },
4522     { Bad_Opcode },
4523     /* b8 */
4524     { Bad_Opcode },
4525     { Bad_Opcode },
4526     { Bad_Opcode },
4527     { Bad_Opcode },
4528     { Bad_Opcode },
4529     { Bad_Opcode },
4530     { Bad_Opcode },
4531     { Bad_Opcode },
4532     /* c0 */
4533     { Bad_Opcode },
4534     { Bad_Opcode },
4535     { Bad_Opcode },
4536     { Bad_Opcode },
4537     { Bad_Opcode },
4538     { Bad_Opcode },
4539     { Bad_Opcode },
4540     { Bad_Opcode },
4541     /* c8 */
4542     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4543     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4544     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4545     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4546     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4547     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4548     { Bad_Opcode },
4549     { "gf2p8mulb", { XM, EXxmm }, PREFIX_DATA },
4550     /* d0 */
4551     { Bad_Opcode },
4552     { Bad_Opcode },
4553     { Bad_Opcode },
4554     { Bad_Opcode },
4555     { Bad_Opcode },
4556     { Bad_Opcode },
4557     { Bad_Opcode },
4558     { Bad_Opcode },
4559     /* d8 */
4560     { PREFIX_TABLE (PREFIX_0F38D8) },
4561     { Bad_Opcode },
4562     { Bad_Opcode },
4563     { "aesimc", { XM, EXx }, PREFIX_DATA },
4564     { PREFIX_TABLE (PREFIX_0F38DC) },
4565     { PREFIX_TABLE (PREFIX_0F38DD) },
4566     { PREFIX_TABLE (PREFIX_0F38DE) },
4567     { PREFIX_TABLE (PREFIX_0F38DF) },
4568     /* e0 */
4569     { Bad_Opcode },
4570     { Bad_Opcode },
4571     { Bad_Opcode },
4572     { Bad_Opcode },
4573     { Bad_Opcode },
4574     { Bad_Opcode },
4575     { Bad_Opcode },
4576     { Bad_Opcode },
4577     /* e8 */
4578     { Bad_Opcode },
4579     { Bad_Opcode },
4580     { Bad_Opcode },
4581     { Bad_Opcode },
4582     { Bad_Opcode },
4583     { Bad_Opcode },
4584     { Bad_Opcode },
4585     { Bad_Opcode },
4586     /* f0 */
4587     { PREFIX_TABLE (PREFIX_0F38F0) },
4588     { PREFIX_TABLE (PREFIX_0F38F1) },
4589     { Bad_Opcode },
4590     { Bad_Opcode },
4591     { Bad_Opcode },
4592     { MOD_TABLE (MOD_0F38F5) },
4593     { PREFIX_TABLE (PREFIX_0F38F6) },
4594     { Bad_Opcode },
4595     /* f8 */
4596     { PREFIX_TABLE (PREFIX_0F38F8) },
4597     { MOD_TABLE (MOD_0F38F9) },
4598     { PREFIX_TABLE (PREFIX_0F38FA) },
4599     { PREFIX_TABLE (PREFIX_0F38FB) },
4600     { Bad_Opcode },
4601     { Bad_Opcode },
4602     { Bad_Opcode },
4603     { Bad_Opcode },
4604   },
4605   /* THREE_BYTE_0F3A */
4606   {
4607     /* 00 */
4608     { Bad_Opcode },
4609     { Bad_Opcode },
4610     { Bad_Opcode },
4611     { Bad_Opcode },
4612     { Bad_Opcode },
4613     { Bad_Opcode },
4614     { Bad_Opcode },
4615     { Bad_Opcode },
4616     /* 08 */
4617     { "roundps", { XM, EXx, Ib }, PREFIX_DATA },
4618     { "roundpd", { XM, EXx, Ib }, PREFIX_DATA },
4619     { "roundss", { XM, EXd, Ib }, PREFIX_DATA },
4620     { "roundsd", { XM, EXq, Ib }, PREFIX_DATA },
4621     { "blendps", { XM, EXx, Ib }, PREFIX_DATA },
4622     { "blendpd", { XM, EXx, Ib }, PREFIX_DATA },
4623     { "pblendw", { XM, EXx, Ib }, PREFIX_DATA },
4624     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
4625     /* 10 */
4626     { Bad_Opcode },
4627     { Bad_Opcode },
4628     { Bad_Opcode },
4629     { Bad_Opcode },
4630     { "pextrb", { Edqb, XM, Ib }, PREFIX_DATA },
4631     { "pextrw", { Edqw, XM, Ib }, PREFIX_DATA },
4632     { "pextrK", { Edq, XM, Ib }, PREFIX_DATA },
4633     { "extractps", { Edqd, XM, Ib }, PREFIX_DATA },
4634     /* 18 */
4635     { Bad_Opcode },
4636     { Bad_Opcode },
4637     { Bad_Opcode },
4638     { Bad_Opcode },
4639     { Bad_Opcode },
4640     { Bad_Opcode },
4641     { Bad_Opcode },
4642     { Bad_Opcode },
4643     /* 20 */
4644     { "pinsrb", { XM, Edqb, Ib }, PREFIX_DATA },
4645     { "insertps", { XM, EXd, Ib }, PREFIX_DATA },
4646     { "pinsrK", { XM, Edq, Ib }, PREFIX_DATA },
4647     { Bad_Opcode },
4648     { Bad_Opcode },
4649     { Bad_Opcode },
4650     { Bad_Opcode },
4651     { Bad_Opcode },
4652     /* 28 */
4653     { Bad_Opcode },
4654     { Bad_Opcode },
4655     { Bad_Opcode },
4656     { Bad_Opcode },
4657     { Bad_Opcode },
4658     { Bad_Opcode },
4659     { Bad_Opcode },
4660     { Bad_Opcode },
4661     /* 30 */
4662     { Bad_Opcode },
4663     { Bad_Opcode },
4664     { Bad_Opcode },
4665     { Bad_Opcode },
4666     { Bad_Opcode },
4667     { Bad_Opcode },
4668     { Bad_Opcode },
4669     { Bad_Opcode },
4670     /* 38 */
4671     { Bad_Opcode },
4672     { Bad_Opcode },
4673     { Bad_Opcode },
4674     { Bad_Opcode },
4675     { Bad_Opcode },
4676     { Bad_Opcode },
4677     { Bad_Opcode },
4678     { Bad_Opcode },
4679     /* 40 */
4680     { "dpps",   { XM, EXx, Ib }, PREFIX_DATA },
4681     { "dppd",   { XM, EXx, Ib }, PREFIX_DATA },
4682     { "mpsadbw", { XM, EXx, Ib }, PREFIX_DATA },
4683     { Bad_Opcode },
4684     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_DATA },
4685     { Bad_Opcode },
4686     { Bad_Opcode },
4687     { Bad_Opcode },
4688     /* 48 */
4689     { Bad_Opcode },
4690     { Bad_Opcode },
4691     { Bad_Opcode },
4692     { Bad_Opcode },
4693     { Bad_Opcode },
4694     { Bad_Opcode },
4695     { Bad_Opcode },
4696     { Bad_Opcode },
4697     /* 50 */
4698     { Bad_Opcode },
4699     { Bad_Opcode },
4700     { Bad_Opcode },
4701     { Bad_Opcode },
4702     { Bad_Opcode },
4703     { Bad_Opcode },
4704     { Bad_Opcode },
4705     { Bad_Opcode },
4706     /* 58 */
4707     { Bad_Opcode },
4708     { Bad_Opcode },
4709     { Bad_Opcode },
4710     { Bad_Opcode },
4711     { Bad_Opcode },
4712     { Bad_Opcode },
4713     { Bad_Opcode },
4714     { Bad_Opcode },
4715     /* 60 */
4716     { "pcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
4717     { "pcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
4718     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_DATA },
4719     { "pcmpistri", { XM, EXx, Ib }, PREFIX_DATA },
4720     { Bad_Opcode },
4721     { Bad_Opcode },
4722     { Bad_Opcode },
4723     { Bad_Opcode },
4724     /* 68 */
4725     { Bad_Opcode },
4726     { Bad_Opcode },
4727     { Bad_Opcode },
4728     { Bad_Opcode },
4729     { Bad_Opcode },
4730     { Bad_Opcode },
4731     { Bad_Opcode },
4732     { Bad_Opcode },
4733     /* 70 */
4734     { Bad_Opcode },
4735     { Bad_Opcode },
4736     { Bad_Opcode },
4737     { Bad_Opcode },
4738     { Bad_Opcode },
4739     { Bad_Opcode },
4740     { Bad_Opcode },
4741     { Bad_Opcode },
4742     /* 78 */
4743     { Bad_Opcode },
4744     { Bad_Opcode },
4745     { Bad_Opcode },
4746     { Bad_Opcode },
4747     { Bad_Opcode },
4748     { Bad_Opcode },
4749     { Bad_Opcode },
4750     { Bad_Opcode },
4751     /* 80 */
4752     { Bad_Opcode },
4753     { Bad_Opcode },
4754     { Bad_Opcode },
4755     { Bad_Opcode },
4756     { Bad_Opcode },
4757     { Bad_Opcode },
4758     { Bad_Opcode },
4759     { Bad_Opcode },
4760     /* 88 */
4761     { Bad_Opcode },
4762     { Bad_Opcode },
4763     { Bad_Opcode },
4764     { Bad_Opcode },
4765     { Bad_Opcode },
4766     { Bad_Opcode },
4767     { Bad_Opcode },
4768     { Bad_Opcode },
4769     /* 90 */
4770     { Bad_Opcode },
4771     { Bad_Opcode },
4772     { Bad_Opcode },
4773     { Bad_Opcode },
4774     { Bad_Opcode },
4775     { Bad_Opcode },
4776     { Bad_Opcode },
4777     { Bad_Opcode },
4778     /* 98 */
4779     { Bad_Opcode },
4780     { Bad_Opcode },
4781     { Bad_Opcode },
4782     { Bad_Opcode },
4783     { Bad_Opcode },
4784     { Bad_Opcode },
4785     { Bad_Opcode },
4786     { Bad_Opcode },
4787     /* a0 */
4788     { Bad_Opcode },
4789     { Bad_Opcode },
4790     { Bad_Opcode },
4791     { Bad_Opcode },
4792     { Bad_Opcode },
4793     { Bad_Opcode },
4794     { Bad_Opcode },
4795     { Bad_Opcode },
4796     /* a8 */
4797     { Bad_Opcode },
4798     { Bad_Opcode },
4799     { Bad_Opcode },
4800     { Bad_Opcode },
4801     { Bad_Opcode },
4802     { Bad_Opcode },
4803     { Bad_Opcode },
4804     { Bad_Opcode },
4805     /* b0 */
4806     { Bad_Opcode },
4807     { Bad_Opcode },
4808     { Bad_Opcode },
4809     { Bad_Opcode },
4810     { Bad_Opcode },
4811     { Bad_Opcode },
4812     { Bad_Opcode },
4813     { Bad_Opcode },
4814     /* b8 */
4815     { Bad_Opcode },
4816     { Bad_Opcode },
4817     { Bad_Opcode },
4818     { Bad_Opcode },
4819     { Bad_Opcode },
4820     { Bad_Opcode },
4821     { Bad_Opcode },
4822     { Bad_Opcode },
4823     /* c0 */
4824     { Bad_Opcode },
4825     { Bad_Opcode },
4826     { Bad_Opcode },
4827     { Bad_Opcode },
4828     { Bad_Opcode },
4829     { Bad_Opcode },
4830     { Bad_Opcode },
4831     { Bad_Opcode },
4832     /* c8 */
4833     { Bad_Opcode },
4834     { Bad_Opcode },
4835     { Bad_Opcode },
4836     { Bad_Opcode },
4837     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4838     { Bad_Opcode },
4839     { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_DATA },
4840     { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_DATA },
4841     /* d0 */
4842     { Bad_Opcode },
4843     { Bad_Opcode },
4844     { Bad_Opcode },
4845     { Bad_Opcode },
4846     { Bad_Opcode },
4847     { Bad_Opcode },
4848     { Bad_Opcode },
4849     { Bad_Opcode },
4850     /* d8 */
4851     { Bad_Opcode },
4852     { Bad_Opcode },
4853     { Bad_Opcode },
4854     { Bad_Opcode },
4855     { Bad_Opcode },
4856     { Bad_Opcode },
4857     { Bad_Opcode },
4858     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
4859     /* e0 */
4860     { Bad_Opcode },
4861     { Bad_Opcode },
4862     { Bad_Opcode },
4863     { Bad_Opcode },
4864     { Bad_Opcode },
4865     { Bad_Opcode },
4866     { Bad_Opcode },
4867     { Bad_Opcode },
4868     /* e8 */
4869     { Bad_Opcode },
4870     { Bad_Opcode },
4871     { Bad_Opcode },
4872     { Bad_Opcode },
4873     { Bad_Opcode },
4874     { Bad_Opcode },
4875     { Bad_Opcode },
4876     { Bad_Opcode },
4877     /* f0 */
4878     { Bad_Opcode },
4879     { Bad_Opcode },
4880     { Bad_Opcode },
4881     { Bad_Opcode },
4882     { Bad_Opcode },
4883     { Bad_Opcode },
4884     { Bad_Opcode },
4885     { Bad_Opcode },
4886     /* f8 */
4887     { Bad_Opcode },
4888     { Bad_Opcode },
4889     { Bad_Opcode },
4890     { Bad_Opcode },
4891     { Bad_Opcode },
4892     { Bad_Opcode },
4893     { Bad_Opcode },
4894     { Bad_Opcode },
4895   },
4896 };
4897
4898 static const struct dis386 xop_table[][256] = {
4899   /* XOP_08 */
4900   {
4901     /* 00 */
4902     { Bad_Opcode },
4903     { Bad_Opcode },
4904     { Bad_Opcode },
4905     { Bad_Opcode },
4906     { Bad_Opcode },
4907     { Bad_Opcode },
4908     { Bad_Opcode },
4909     { Bad_Opcode },
4910     /* 08 */
4911     { Bad_Opcode },
4912     { Bad_Opcode },
4913     { Bad_Opcode },
4914     { Bad_Opcode },
4915     { Bad_Opcode },
4916     { Bad_Opcode },
4917     { Bad_Opcode },
4918     { Bad_Opcode },
4919     /* 10 */
4920     { Bad_Opcode },
4921     { Bad_Opcode },
4922     { Bad_Opcode },
4923     { Bad_Opcode },
4924     { Bad_Opcode },
4925     { Bad_Opcode },
4926     { Bad_Opcode },
4927     { Bad_Opcode },
4928     /* 18 */
4929     { Bad_Opcode },
4930     { Bad_Opcode },
4931     { Bad_Opcode },
4932     { Bad_Opcode },
4933     { Bad_Opcode },
4934     { Bad_Opcode },
4935     { Bad_Opcode },
4936     { Bad_Opcode },
4937     /* 20 */
4938     { Bad_Opcode },
4939     { Bad_Opcode },
4940     { Bad_Opcode },
4941     { Bad_Opcode },
4942     { Bad_Opcode },
4943     { Bad_Opcode },
4944     { Bad_Opcode },
4945     { Bad_Opcode },
4946     /* 28 */
4947     { Bad_Opcode },
4948     { Bad_Opcode },
4949     { Bad_Opcode },
4950     { Bad_Opcode },
4951     { Bad_Opcode },
4952     { Bad_Opcode },
4953     { Bad_Opcode },
4954     { Bad_Opcode },
4955     /* 30 */
4956     { Bad_Opcode },
4957     { Bad_Opcode },
4958     { Bad_Opcode },
4959     { Bad_Opcode },
4960     { Bad_Opcode },
4961     { Bad_Opcode },
4962     { Bad_Opcode },
4963     { Bad_Opcode },
4964     /* 38 */
4965     { Bad_Opcode },
4966     { Bad_Opcode },
4967     { Bad_Opcode },
4968     { Bad_Opcode },
4969     { Bad_Opcode },
4970     { Bad_Opcode },
4971     { Bad_Opcode },
4972     { Bad_Opcode },
4973     /* 40 */
4974     { Bad_Opcode },
4975     { Bad_Opcode },
4976     { Bad_Opcode },
4977     { Bad_Opcode },
4978     { Bad_Opcode },
4979     { Bad_Opcode },
4980     { Bad_Opcode },
4981     { Bad_Opcode },
4982     /* 48 */
4983     { Bad_Opcode },
4984     { Bad_Opcode },
4985     { Bad_Opcode },
4986     { Bad_Opcode },
4987     { Bad_Opcode },
4988     { Bad_Opcode },
4989     { Bad_Opcode },
4990     { Bad_Opcode },
4991     /* 50 */
4992     { Bad_Opcode },
4993     { Bad_Opcode },
4994     { Bad_Opcode },
4995     { Bad_Opcode },
4996     { Bad_Opcode },
4997     { Bad_Opcode },
4998     { Bad_Opcode },
4999     { Bad_Opcode },
5000     /* 58 */
5001     { Bad_Opcode },
5002     { Bad_Opcode },
5003     { Bad_Opcode },
5004     { Bad_Opcode },
5005     { Bad_Opcode },
5006     { Bad_Opcode },
5007     { Bad_Opcode },
5008     { Bad_Opcode },
5009     /* 60 */
5010     { Bad_Opcode },
5011     { Bad_Opcode },
5012     { Bad_Opcode },
5013     { Bad_Opcode },
5014     { Bad_Opcode },
5015     { Bad_Opcode },
5016     { Bad_Opcode },
5017     { Bad_Opcode },
5018     /* 68 */
5019     { Bad_Opcode },
5020     { Bad_Opcode },
5021     { Bad_Opcode },
5022     { Bad_Opcode },
5023     { Bad_Opcode },
5024     { Bad_Opcode },
5025     { Bad_Opcode },
5026     { Bad_Opcode },
5027     /* 70 */
5028     { Bad_Opcode },
5029     { Bad_Opcode },
5030     { Bad_Opcode },
5031     { Bad_Opcode },
5032     { Bad_Opcode },
5033     { Bad_Opcode },
5034     { Bad_Opcode },
5035     { Bad_Opcode },
5036     /* 78 */
5037     { Bad_Opcode },
5038     { Bad_Opcode },
5039     { Bad_Opcode },
5040     { Bad_Opcode },
5041     { Bad_Opcode },
5042     { Bad_Opcode },
5043     { Bad_Opcode },
5044     { Bad_Opcode },
5045     /* 80 */
5046     { Bad_Opcode },
5047     { Bad_Opcode },
5048     { Bad_Opcode },
5049     { Bad_Opcode },
5050     { Bad_Opcode },
5051     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_85) },
5052     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_86) },
5053     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_87) },
5054     /* 88 */
5055     { Bad_Opcode },
5056     { Bad_Opcode },
5057     { Bad_Opcode },
5058     { Bad_Opcode },
5059     { Bad_Opcode },
5060     { Bad_Opcode },
5061     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8E) },
5062     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8F) },
5063     /* 90 */
5064     { Bad_Opcode },
5065     { Bad_Opcode },
5066     { Bad_Opcode },
5067     { Bad_Opcode },
5068     { Bad_Opcode },
5069     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_95) },
5070     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_96) },
5071     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_97) },
5072     /* 98 */
5073     { Bad_Opcode },
5074     { Bad_Opcode },
5075     { Bad_Opcode },
5076     { Bad_Opcode },
5077     { Bad_Opcode },
5078     { Bad_Opcode },
5079     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9E) },
5080     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9F) },
5081     /* a0 */
5082     { Bad_Opcode },
5083     { Bad_Opcode },
5084     { "vpcmov",         { XM, Vex, EXx, XMVexI4 }, 0 },
5085     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A3) },
5086     { Bad_Opcode },
5087     { Bad_Opcode },
5088     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A6) },
5089     { Bad_Opcode },
5090     /* a8 */
5091     { Bad_Opcode },
5092     { Bad_Opcode },
5093     { Bad_Opcode },
5094     { Bad_Opcode },
5095     { Bad_Opcode },
5096     { Bad_Opcode },
5097     { Bad_Opcode },
5098     { Bad_Opcode },
5099     /* b0 */
5100     { Bad_Opcode },
5101     { Bad_Opcode },
5102     { Bad_Opcode },
5103     { Bad_Opcode },
5104     { Bad_Opcode },
5105     { Bad_Opcode },
5106     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_B6) },
5107     { Bad_Opcode },
5108     /* b8 */
5109     { Bad_Opcode },
5110     { Bad_Opcode },
5111     { Bad_Opcode },
5112     { Bad_Opcode },
5113     { Bad_Opcode },
5114     { Bad_Opcode },
5115     { Bad_Opcode },
5116     { Bad_Opcode },
5117     /* c0 */
5118     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C0) },
5119     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C1) },
5120     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C2) },
5121     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C3) },
5122     { Bad_Opcode },
5123     { Bad_Opcode },
5124     { Bad_Opcode },
5125     { Bad_Opcode },
5126     /* c8 */
5127     { Bad_Opcode },
5128     { Bad_Opcode },
5129     { Bad_Opcode },
5130     { Bad_Opcode },
5131     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
5132     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
5133     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
5134     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
5135     /* d0 */
5136     { Bad_Opcode },
5137     { Bad_Opcode },
5138     { Bad_Opcode },
5139     { Bad_Opcode },
5140     { Bad_Opcode },
5141     { Bad_Opcode },
5142     { Bad_Opcode },
5143     { Bad_Opcode },
5144     /* d8 */
5145     { Bad_Opcode },
5146     { Bad_Opcode },
5147     { Bad_Opcode },
5148     { Bad_Opcode },
5149     { Bad_Opcode },
5150     { Bad_Opcode },
5151     { Bad_Opcode },
5152     { Bad_Opcode },
5153     /* e0 */
5154     { Bad_Opcode },
5155     { Bad_Opcode },
5156     { Bad_Opcode },
5157     { Bad_Opcode },
5158     { Bad_Opcode },
5159     { Bad_Opcode },
5160     { Bad_Opcode },
5161     { Bad_Opcode },
5162     /* e8 */
5163     { Bad_Opcode },
5164     { Bad_Opcode },
5165     { Bad_Opcode },
5166     { Bad_Opcode },
5167     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
5168     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
5169     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
5170     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
5171     /* f0 */
5172     { Bad_Opcode },
5173     { Bad_Opcode },
5174     { Bad_Opcode },
5175     { Bad_Opcode },
5176     { Bad_Opcode },
5177     { Bad_Opcode },
5178     { Bad_Opcode },
5179     { Bad_Opcode },
5180     /* f8 */
5181     { Bad_Opcode },
5182     { Bad_Opcode },
5183     { Bad_Opcode },
5184     { Bad_Opcode },
5185     { Bad_Opcode },
5186     { Bad_Opcode },
5187     { Bad_Opcode },
5188     { Bad_Opcode },
5189   },
5190   /* XOP_09 */
5191   {
5192     /* 00 */
5193     { Bad_Opcode },
5194     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_01) },
5195     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_02) },
5196     { Bad_Opcode },
5197     { Bad_Opcode },
5198     { Bad_Opcode },
5199     { Bad_Opcode },
5200     { Bad_Opcode },
5201     /* 08 */
5202     { Bad_Opcode },
5203     { Bad_Opcode },
5204     { Bad_Opcode },
5205     { Bad_Opcode },
5206     { Bad_Opcode },
5207     { Bad_Opcode },
5208     { Bad_Opcode },
5209     { Bad_Opcode },
5210     /* 10 */
5211     { Bad_Opcode },
5212     { Bad_Opcode },
5213     { MOD_TABLE (MOD_VEX_0FXOP_09_12) },
5214     { Bad_Opcode },
5215     { Bad_Opcode },
5216     { Bad_Opcode },
5217     { Bad_Opcode },
5218     { Bad_Opcode },
5219     /* 18 */
5220     { Bad_Opcode },
5221     { Bad_Opcode },
5222     { Bad_Opcode },
5223     { Bad_Opcode },
5224     { Bad_Opcode },
5225     { Bad_Opcode },
5226     { Bad_Opcode },
5227     { Bad_Opcode },
5228     /* 20 */
5229     { Bad_Opcode },
5230     { Bad_Opcode },
5231     { Bad_Opcode },
5232     { Bad_Opcode },
5233     { Bad_Opcode },
5234     { Bad_Opcode },
5235     { Bad_Opcode },
5236     { Bad_Opcode },
5237     /* 28 */
5238     { Bad_Opcode },
5239     { Bad_Opcode },
5240     { Bad_Opcode },
5241     { Bad_Opcode },
5242     { Bad_Opcode },
5243     { Bad_Opcode },
5244     { Bad_Opcode },
5245     { Bad_Opcode },
5246     /* 30 */
5247     { Bad_Opcode },
5248     { Bad_Opcode },
5249     { Bad_Opcode },
5250     { Bad_Opcode },
5251     { Bad_Opcode },
5252     { Bad_Opcode },
5253     { Bad_Opcode },
5254     { Bad_Opcode },
5255     /* 38 */
5256     { Bad_Opcode },
5257     { Bad_Opcode },
5258     { Bad_Opcode },
5259     { Bad_Opcode },
5260     { Bad_Opcode },
5261     { Bad_Opcode },
5262     { Bad_Opcode },
5263     { Bad_Opcode },
5264     /* 40 */
5265     { Bad_Opcode },
5266     { Bad_Opcode },
5267     { Bad_Opcode },
5268     { Bad_Opcode },
5269     { Bad_Opcode },
5270     { Bad_Opcode },
5271     { Bad_Opcode },
5272     { Bad_Opcode },
5273     /* 48 */
5274     { Bad_Opcode },
5275     { Bad_Opcode },
5276     { Bad_Opcode },
5277     { Bad_Opcode },
5278     { Bad_Opcode },
5279     { Bad_Opcode },
5280     { Bad_Opcode },
5281     { Bad_Opcode },
5282     /* 50 */
5283     { Bad_Opcode },
5284     { Bad_Opcode },
5285     { Bad_Opcode },
5286     { Bad_Opcode },
5287     { Bad_Opcode },
5288     { Bad_Opcode },
5289     { Bad_Opcode },
5290     { Bad_Opcode },
5291     /* 58 */
5292     { Bad_Opcode },
5293     { Bad_Opcode },
5294     { Bad_Opcode },
5295     { Bad_Opcode },
5296     { Bad_Opcode },
5297     { Bad_Opcode },
5298     { Bad_Opcode },
5299     { Bad_Opcode },
5300     /* 60 */
5301     { Bad_Opcode },
5302     { Bad_Opcode },
5303     { Bad_Opcode },
5304     { Bad_Opcode },
5305     { Bad_Opcode },
5306     { Bad_Opcode },
5307     { Bad_Opcode },
5308     { Bad_Opcode },
5309     /* 68 */
5310     { Bad_Opcode },
5311     { Bad_Opcode },
5312     { Bad_Opcode },
5313     { Bad_Opcode },
5314     { Bad_Opcode },
5315     { Bad_Opcode },
5316     { Bad_Opcode },
5317     { Bad_Opcode },
5318     /* 70 */
5319     { Bad_Opcode },
5320     { Bad_Opcode },
5321     { Bad_Opcode },
5322     { Bad_Opcode },
5323     { Bad_Opcode },
5324     { Bad_Opcode },
5325     { Bad_Opcode },
5326     { Bad_Opcode },
5327     /* 78 */
5328     { Bad_Opcode },
5329     { Bad_Opcode },
5330     { Bad_Opcode },
5331     { Bad_Opcode },
5332     { Bad_Opcode },
5333     { Bad_Opcode },
5334     { Bad_Opcode },
5335     { Bad_Opcode },
5336     /* 80 */
5337     { VEX_W_TABLE (VEX_W_0FXOP_09_80) },
5338     { VEX_W_TABLE (VEX_W_0FXOP_09_81) },
5339     { VEX_W_TABLE (VEX_W_0FXOP_09_82) },
5340     { VEX_W_TABLE (VEX_W_0FXOP_09_83) },
5341     { Bad_Opcode },
5342     { Bad_Opcode },
5343     { Bad_Opcode },
5344     { Bad_Opcode },
5345     /* 88 */
5346     { Bad_Opcode },
5347     { Bad_Opcode },
5348     { Bad_Opcode },
5349     { Bad_Opcode },
5350     { Bad_Opcode },
5351     { Bad_Opcode },
5352     { Bad_Opcode },
5353     { Bad_Opcode },
5354     /* 90 */
5355     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_90) },
5356     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_91) },
5357     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_92) },
5358     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_93) },
5359     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_94) },
5360     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_95) },
5361     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_96) },
5362     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_97) },
5363     /* 98 */
5364     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_98) },
5365     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_99) },
5366     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9A) },
5367     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9B) },
5368     { Bad_Opcode },
5369     { Bad_Opcode },
5370     { Bad_Opcode },
5371     { Bad_Opcode },
5372     /* a0 */
5373     { Bad_Opcode },
5374     { Bad_Opcode },
5375     { Bad_Opcode },
5376     { Bad_Opcode },
5377     { Bad_Opcode },
5378     { Bad_Opcode },
5379     { Bad_Opcode },
5380     { Bad_Opcode },
5381     /* a8 */
5382     { Bad_Opcode },
5383     { Bad_Opcode },
5384     { Bad_Opcode },
5385     { Bad_Opcode },
5386     { Bad_Opcode },
5387     { Bad_Opcode },
5388     { Bad_Opcode },
5389     { Bad_Opcode },
5390     /* b0 */
5391     { Bad_Opcode },
5392     { Bad_Opcode },
5393     { Bad_Opcode },
5394     { Bad_Opcode },
5395     { Bad_Opcode },
5396     { Bad_Opcode },
5397     { Bad_Opcode },
5398     { Bad_Opcode },
5399     /* b8 */
5400     { Bad_Opcode },
5401     { Bad_Opcode },
5402     { Bad_Opcode },
5403     { Bad_Opcode },
5404     { Bad_Opcode },
5405     { Bad_Opcode },
5406     { Bad_Opcode },
5407     { Bad_Opcode },
5408     /* c0 */
5409     { Bad_Opcode },
5410     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C1) },
5411     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C2) },
5412     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C3) },
5413     { Bad_Opcode },
5414     { Bad_Opcode },
5415     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C6) },
5416     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C7) },
5417     /* c8 */
5418     { Bad_Opcode },
5419     { Bad_Opcode },
5420     { Bad_Opcode },
5421     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_CB) },
5422     { Bad_Opcode },
5423     { Bad_Opcode },
5424     { Bad_Opcode },
5425     { Bad_Opcode },
5426     /* d0 */
5427     { Bad_Opcode },
5428     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D1) },
5429     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D2) },
5430     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D3) },
5431     { Bad_Opcode },
5432     { Bad_Opcode },
5433     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D6) },
5434     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D7) },
5435     /* d8 */
5436     { Bad_Opcode },
5437     { Bad_Opcode },
5438     { Bad_Opcode },
5439     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_DB) },
5440     { Bad_Opcode },
5441     { Bad_Opcode },
5442     { Bad_Opcode },
5443     { Bad_Opcode },
5444     /* e0 */
5445     { Bad_Opcode },
5446     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E1) },
5447     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E2) },
5448     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E3) },
5449     { Bad_Opcode },
5450     { Bad_Opcode },
5451     { Bad_Opcode },
5452     { Bad_Opcode },
5453     /* e8 */
5454     { Bad_Opcode },
5455     { Bad_Opcode },
5456     { Bad_Opcode },
5457     { Bad_Opcode },
5458     { Bad_Opcode },
5459     { Bad_Opcode },
5460     { Bad_Opcode },
5461     { Bad_Opcode },
5462     /* f0 */
5463     { Bad_Opcode },
5464     { Bad_Opcode },
5465     { Bad_Opcode },
5466     { Bad_Opcode },
5467     { Bad_Opcode },
5468     { Bad_Opcode },
5469     { Bad_Opcode },
5470     { Bad_Opcode },
5471     /* f8 */
5472     { Bad_Opcode },
5473     { Bad_Opcode },
5474     { Bad_Opcode },
5475     { Bad_Opcode },
5476     { Bad_Opcode },
5477     { Bad_Opcode },
5478     { Bad_Opcode },
5479     { Bad_Opcode },
5480   },
5481   /* XOP_0A */
5482   {
5483     /* 00 */
5484     { Bad_Opcode },
5485     { Bad_Opcode },
5486     { Bad_Opcode },
5487     { Bad_Opcode },
5488     { Bad_Opcode },
5489     { Bad_Opcode },
5490     { Bad_Opcode },
5491     { Bad_Opcode },
5492     /* 08 */
5493     { Bad_Opcode },
5494     { Bad_Opcode },
5495     { Bad_Opcode },
5496     { Bad_Opcode },
5497     { Bad_Opcode },
5498     { Bad_Opcode },
5499     { Bad_Opcode },
5500     { Bad_Opcode },
5501     /* 10 */
5502     { "bextrS", { Gdq, Edq, Id }, 0 },
5503     { Bad_Opcode },
5504     { VEX_LEN_TABLE (VEX_LEN_0FXOP_0A_12) },
5505     { Bad_Opcode },
5506     { Bad_Opcode },
5507     { Bad_Opcode },
5508     { Bad_Opcode },
5509     { Bad_Opcode },
5510     /* 18 */
5511     { Bad_Opcode },
5512     { Bad_Opcode },
5513     { Bad_Opcode },
5514     { Bad_Opcode },
5515     { Bad_Opcode },
5516     { Bad_Opcode },
5517     { Bad_Opcode },
5518     { Bad_Opcode },
5519     /* 20 */
5520     { Bad_Opcode },
5521     { Bad_Opcode },
5522     { Bad_Opcode },
5523     { Bad_Opcode },
5524     { Bad_Opcode },
5525     { Bad_Opcode },
5526     { Bad_Opcode },
5527     { Bad_Opcode },
5528     /* 28 */
5529     { Bad_Opcode },
5530     { Bad_Opcode },
5531     { Bad_Opcode },
5532     { Bad_Opcode },
5533     { Bad_Opcode },
5534     { Bad_Opcode },
5535     { Bad_Opcode },
5536     { Bad_Opcode },
5537     /* 30 */
5538     { Bad_Opcode },
5539     { Bad_Opcode },
5540     { Bad_Opcode },
5541     { Bad_Opcode },
5542     { Bad_Opcode },
5543     { Bad_Opcode },
5544     { Bad_Opcode },
5545     { Bad_Opcode },
5546     /* 38 */
5547     { Bad_Opcode },
5548     { Bad_Opcode },
5549     { Bad_Opcode },
5550     { Bad_Opcode },
5551     { Bad_Opcode },
5552     { Bad_Opcode },
5553     { Bad_Opcode },
5554     { Bad_Opcode },
5555     /* 40 */
5556     { Bad_Opcode },
5557     { Bad_Opcode },
5558     { Bad_Opcode },
5559     { Bad_Opcode },
5560     { Bad_Opcode },
5561     { Bad_Opcode },
5562     { Bad_Opcode },
5563     { Bad_Opcode },
5564     /* 48 */
5565     { Bad_Opcode },
5566     { Bad_Opcode },
5567     { Bad_Opcode },
5568     { Bad_Opcode },
5569     { Bad_Opcode },
5570     { Bad_Opcode },
5571     { Bad_Opcode },
5572     { Bad_Opcode },
5573     /* 50 */
5574     { Bad_Opcode },
5575     { Bad_Opcode },
5576     { Bad_Opcode },
5577     { Bad_Opcode },
5578     { Bad_Opcode },
5579     { Bad_Opcode },
5580     { Bad_Opcode },
5581     { Bad_Opcode },
5582     /* 58 */
5583     { Bad_Opcode },
5584     { Bad_Opcode },
5585     { Bad_Opcode },
5586     { Bad_Opcode },
5587     { Bad_Opcode },
5588     { Bad_Opcode },
5589     { Bad_Opcode },
5590     { Bad_Opcode },
5591     /* 60 */
5592     { Bad_Opcode },
5593     { Bad_Opcode },
5594     { Bad_Opcode },
5595     { Bad_Opcode },
5596     { Bad_Opcode },
5597     { Bad_Opcode },
5598     { Bad_Opcode },
5599     { Bad_Opcode },
5600     /* 68 */
5601     { Bad_Opcode },
5602     { Bad_Opcode },
5603     { Bad_Opcode },
5604     { Bad_Opcode },
5605     { Bad_Opcode },
5606     { Bad_Opcode },
5607     { Bad_Opcode },
5608     { Bad_Opcode },
5609     /* 70 */
5610     { Bad_Opcode },
5611     { Bad_Opcode },
5612     { Bad_Opcode },
5613     { Bad_Opcode },
5614     { Bad_Opcode },
5615     { Bad_Opcode },
5616     { Bad_Opcode },
5617     { Bad_Opcode },
5618     /* 78 */
5619     { Bad_Opcode },
5620     { Bad_Opcode },
5621     { Bad_Opcode },
5622     { Bad_Opcode },
5623     { Bad_Opcode },
5624     { Bad_Opcode },
5625     { Bad_Opcode },
5626     { Bad_Opcode },
5627     /* 80 */
5628     { Bad_Opcode },
5629     { Bad_Opcode },
5630     { Bad_Opcode },
5631     { Bad_Opcode },
5632     { Bad_Opcode },
5633     { Bad_Opcode },
5634     { Bad_Opcode },
5635     { Bad_Opcode },
5636     /* 88 */
5637     { Bad_Opcode },
5638     { Bad_Opcode },
5639     { Bad_Opcode },
5640     { Bad_Opcode },
5641     { Bad_Opcode },
5642     { Bad_Opcode },
5643     { Bad_Opcode },
5644     { Bad_Opcode },
5645     /* 90 */
5646     { Bad_Opcode },
5647     { Bad_Opcode },
5648     { Bad_Opcode },
5649     { Bad_Opcode },
5650     { Bad_Opcode },
5651     { Bad_Opcode },
5652     { Bad_Opcode },
5653     { Bad_Opcode },
5654     /* 98 */
5655     { Bad_Opcode },
5656     { Bad_Opcode },
5657     { Bad_Opcode },
5658     { Bad_Opcode },
5659     { Bad_Opcode },
5660     { Bad_Opcode },
5661     { Bad_Opcode },
5662     { Bad_Opcode },
5663     /* a0 */
5664     { Bad_Opcode },
5665     { Bad_Opcode },
5666     { Bad_Opcode },
5667     { Bad_Opcode },
5668     { Bad_Opcode },
5669     { Bad_Opcode },
5670     { Bad_Opcode },
5671     { Bad_Opcode },
5672     /* a8 */
5673     { Bad_Opcode },
5674     { Bad_Opcode },
5675     { Bad_Opcode },
5676     { Bad_Opcode },
5677     { Bad_Opcode },
5678     { Bad_Opcode },
5679     { Bad_Opcode },
5680     { Bad_Opcode },
5681     /* b0 */
5682     { Bad_Opcode },
5683     { Bad_Opcode },
5684     { Bad_Opcode },
5685     { Bad_Opcode },
5686     { Bad_Opcode },
5687     { Bad_Opcode },
5688     { Bad_Opcode },
5689     { Bad_Opcode },
5690     /* b8 */
5691     { Bad_Opcode },
5692     { Bad_Opcode },
5693     { Bad_Opcode },
5694     { Bad_Opcode },
5695     { Bad_Opcode },
5696     { Bad_Opcode },
5697     { Bad_Opcode },
5698     { Bad_Opcode },
5699     /* c0 */
5700     { Bad_Opcode },
5701     { Bad_Opcode },
5702     { Bad_Opcode },
5703     { Bad_Opcode },
5704     { Bad_Opcode },
5705     { Bad_Opcode },
5706     { Bad_Opcode },
5707     { Bad_Opcode },
5708     /* c8 */
5709     { Bad_Opcode },
5710     { Bad_Opcode },
5711     { Bad_Opcode },
5712     { Bad_Opcode },
5713     { Bad_Opcode },
5714     { Bad_Opcode },
5715     { Bad_Opcode },
5716     { Bad_Opcode },
5717     /* d0 */
5718     { Bad_Opcode },
5719     { Bad_Opcode },
5720     { Bad_Opcode },
5721     { Bad_Opcode },
5722     { Bad_Opcode },
5723     { Bad_Opcode },
5724     { Bad_Opcode },
5725     { Bad_Opcode },
5726     /* d8 */
5727     { Bad_Opcode },
5728     { Bad_Opcode },
5729     { Bad_Opcode },
5730     { Bad_Opcode },
5731     { Bad_Opcode },
5732     { Bad_Opcode },
5733     { Bad_Opcode },
5734     { Bad_Opcode },
5735     /* e0 */
5736     { Bad_Opcode },
5737     { Bad_Opcode },
5738     { Bad_Opcode },
5739     { Bad_Opcode },
5740     { Bad_Opcode },
5741     { Bad_Opcode },
5742     { Bad_Opcode },
5743     { Bad_Opcode },
5744     /* e8 */
5745     { Bad_Opcode },
5746     { Bad_Opcode },
5747     { Bad_Opcode },
5748     { Bad_Opcode },
5749     { Bad_Opcode },
5750     { Bad_Opcode },
5751     { Bad_Opcode },
5752     { Bad_Opcode },
5753     /* f0 */
5754     { Bad_Opcode },
5755     { Bad_Opcode },
5756     { Bad_Opcode },
5757     { Bad_Opcode },
5758     { Bad_Opcode },
5759     { Bad_Opcode },
5760     { Bad_Opcode },
5761     { Bad_Opcode },
5762     /* f8 */
5763     { Bad_Opcode },
5764     { Bad_Opcode },
5765     { Bad_Opcode },
5766     { Bad_Opcode },
5767     { Bad_Opcode },
5768     { Bad_Opcode },
5769     { Bad_Opcode },
5770     { Bad_Opcode },
5771   },
5772 };
5773
5774 static const struct dis386 vex_table[][256] = {
5775   /* VEX_0F */
5776   {
5777     /* 00 */
5778     { Bad_Opcode },
5779     { Bad_Opcode },
5780     { Bad_Opcode },
5781     { Bad_Opcode },
5782     { Bad_Opcode },
5783     { Bad_Opcode },
5784     { Bad_Opcode },
5785     { Bad_Opcode },
5786     /* 08 */
5787     { Bad_Opcode },
5788     { Bad_Opcode },
5789     { Bad_Opcode },
5790     { Bad_Opcode },
5791     { Bad_Opcode },
5792     { Bad_Opcode },
5793     { Bad_Opcode },
5794     { Bad_Opcode },
5795     /* 10 */
5796     { PREFIX_TABLE (PREFIX_VEX_0F10) },
5797     { PREFIX_TABLE (PREFIX_VEX_0F11) },
5798     { PREFIX_TABLE (PREFIX_VEX_0F12) },
5799     { MOD_TABLE (MOD_VEX_0F13) },
5800     { "vunpcklpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
5801     { "vunpckhpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
5802     { PREFIX_TABLE (PREFIX_VEX_0F16) },
5803     { MOD_TABLE (MOD_VEX_0F17) },
5804     /* 18 */
5805     { Bad_Opcode },
5806     { Bad_Opcode },
5807     { Bad_Opcode },
5808     { Bad_Opcode },
5809     { Bad_Opcode },
5810     { Bad_Opcode },
5811     { Bad_Opcode },
5812     { Bad_Opcode },
5813     /* 20 */
5814     { Bad_Opcode },
5815     { Bad_Opcode },
5816     { Bad_Opcode },
5817     { Bad_Opcode },
5818     { Bad_Opcode },
5819     { Bad_Opcode },
5820     { Bad_Opcode },
5821     { Bad_Opcode },
5822     /* 28 */
5823     { "vmovapX",        { XM, EXx }, PREFIX_OPCODE },
5824     { "vmovapX",        { EXxS, XM }, PREFIX_OPCODE },
5825     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
5826     { MOD_TABLE (MOD_VEX_0F2B) },
5827     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
5828     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
5829     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
5830     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
5831     /* 30 */
5832     { Bad_Opcode },
5833     { Bad_Opcode },
5834     { Bad_Opcode },
5835     { Bad_Opcode },
5836     { Bad_Opcode },
5837     { Bad_Opcode },
5838     { Bad_Opcode },
5839     { Bad_Opcode },
5840     /* 38 */
5841     { Bad_Opcode },
5842     { Bad_Opcode },
5843     { Bad_Opcode },
5844     { Bad_Opcode },
5845     { Bad_Opcode },
5846     { Bad_Opcode },
5847     { Bad_Opcode },
5848     { Bad_Opcode },
5849     /* 40 */
5850     { Bad_Opcode },
5851     { PREFIX_TABLE (PREFIX_VEX_0F41) },
5852     { PREFIX_TABLE (PREFIX_VEX_0F42) },
5853     { Bad_Opcode },
5854     { PREFIX_TABLE (PREFIX_VEX_0F44) },
5855     { PREFIX_TABLE (PREFIX_VEX_0F45) },
5856     { PREFIX_TABLE (PREFIX_VEX_0F46) },
5857     { PREFIX_TABLE (PREFIX_VEX_0F47) },
5858     /* 48 */
5859     { Bad_Opcode },
5860     { Bad_Opcode },
5861     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
5862     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
5863     { Bad_Opcode },
5864     { Bad_Opcode },
5865     { Bad_Opcode },
5866     { Bad_Opcode },
5867     /* 50 */
5868     { MOD_TABLE (MOD_VEX_0F50) },
5869     { PREFIX_TABLE (PREFIX_VEX_0F51) },
5870     { PREFIX_TABLE (PREFIX_VEX_0F52) },
5871     { PREFIX_TABLE (PREFIX_VEX_0F53) },
5872     { "vandpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
5873     { "vandnpX",        { XM, Vex, EXx }, PREFIX_OPCODE },
5874     { "vorpX",          { XM, Vex, EXx }, PREFIX_OPCODE },
5875     { "vxorpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
5876     /* 58 */
5877     { PREFIX_TABLE (PREFIX_VEX_0F58) },
5878     { PREFIX_TABLE (PREFIX_VEX_0F59) },
5879     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
5880     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
5881     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
5882     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
5883     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
5884     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
5885     /* 60 */
5886     { "vpunpcklbw",     { XM, Vex, EXx }, PREFIX_DATA },
5887     { "vpunpcklwd",     { XM, Vex, EXx }, PREFIX_DATA },
5888     { "vpunpckldq",     { XM, Vex, EXx }, PREFIX_DATA },
5889     { "vpacksswb",      { XM, Vex, EXx }, PREFIX_DATA },
5890     { "vpcmpgtb",       { XM, Vex, EXx }, PREFIX_DATA },
5891     { "vpcmpgtw",       { XM, Vex, EXx }, PREFIX_DATA },
5892     { "vpcmpgtd",       { XM, Vex, EXx }, PREFIX_DATA },
5893     { "vpackuswb",      { XM, Vex, EXx }, PREFIX_DATA },
5894     /* 68 */
5895     { "vpunpckhbw",     { XM, Vex, EXx }, PREFIX_DATA },
5896     { "vpunpckhwd",     { XM, Vex, EXx }, PREFIX_DATA },
5897     { "vpunpckhdq",     { XM, Vex, EXx }, PREFIX_DATA },
5898     { "vpackssdw",      { XM, Vex, EXx }, PREFIX_DATA },
5899     { "vpunpcklqdq",    { XM, Vex, EXx }, PREFIX_DATA },
5900     { "vpunpckhqdq",    { XM, Vex, EXx }, PREFIX_DATA },
5901     { VEX_LEN_TABLE (VEX_LEN_0F6E) },
5902     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
5903     /* 70 */
5904     { PREFIX_TABLE (PREFIX_VEX_0F70) },
5905     { REG_TABLE (REG_VEX_0F71) },
5906     { REG_TABLE (REG_VEX_0F72) },
5907     { REG_TABLE (REG_VEX_0F73) },
5908     { "vpcmpeqb",       { XM, Vex, EXx }, PREFIX_DATA },
5909     { "vpcmpeqw",       { XM, Vex, EXx }, PREFIX_DATA },
5910     { "vpcmpeqd",       { XM, Vex, EXx }, PREFIX_DATA },
5911     { VEX_LEN_TABLE (VEX_LEN_0F77) },
5912     /* 78 */
5913     { Bad_Opcode },
5914     { Bad_Opcode },
5915     { Bad_Opcode },
5916     { Bad_Opcode },
5917     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
5918     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
5919     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
5920     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
5921     /* 80 */
5922     { Bad_Opcode },
5923     { Bad_Opcode },
5924     { Bad_Opcode },
5925     { Bad_Opcode },
5926     { Bad_Opcode },
5927     { Bad_Opcode },
5928     { Bad_Opcode },
5929     { Bad_Opcode },
5930     /* 88 */
5931     { Bad_Opcode },
5932     { Bad_Opcode },
5933     { Bad_Opcode },
5934     { Bad_Opcode },
5935     { Bad_Opcode },
5936     { Bad_Opcode },
5937     { Bad_Opcode },
5938     { Bad_Opcode },
5939     /* 90 */
5940     { PREFIX_TABLE (PREFIX_VEX_0F90) },
5941     { PREFIX_TABLE (PREFIX_VEX_0F91) },
5942     { PREFIX_TABLE (PREFIX_VEX_0F92) },
5943     { PREFIX_TABLE (PREFIX_VEX_0F93) },
5944     { Bad_Opcode },
5945     { Bad_Opcode },
5946     { Bad_Opcode },
5947     { Bad_Opcode },
5948     /* 98 */
5949     { PREFIX_TABLE (PREFIX_VEX_0F98) },
5950     { PREFIX_TABLE (PREFIX_VEX_0F99) },
5951     { Bad_Opcode },
5952     { Bad_Opcode },
5953     { Bad_Opcode },
5954     { Bad_Opcode },
5955     { Bad_Opcode },
5956     { Bad_Opcode },
5957     /* a0 */
5958     { Bad_Opcode },
5959     { Bad_Opcode },
5960     { Bad_Opcode },
5961     { Bad_Opcode },
5962     { Bad_Opcode },
5963     { Bad_Opcode },
5964     { Bad_Opcode },
5965     { Bad_Opcode },
5966     /* a8 */
5967     { Bad_Opcode },
5968     { Bad_Opcode },
5969     { Bad_Opcode },
5970     { Bad_Opcode },
5971     { Bad_Opcode },
5972     { Bad_Opcode },
5973     { REG_TABLE (REG_VEX_0FAE) },
5974     { Bad_Opcode },
5975     /* b0 */
5976     { Bad_Opcode },
5977     { Bad_Opcode },
5978     { Bad_Opcode },
5979     { Bad_Opcode },
5980     { Bad_Opcode },
5981     { Bad_Opcode },
5982     { Bad_Opcode },
5983     { Bad_Opcode },
5984     /* b8 */
5985     { Bad_Opcode },
5986     { Bad_Opcode },
5987     { Bad_Opcode },
5988     { Bad_Opcode },
5989     { Bad_Opcode },
5990     { Bad_Opcode },
5991     { Bad_Opcode },
5992     { Bad_Opcode },
5993     /* c0 */
5994     { Bad_Opcode },
5995     { Bad_Opcode },
5996     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
5997     { Bad_Opcode },
5998     { VEX_LEN_TABLE (VEX_LEN_0FC4) },
5999     { VEX_LEN_TABLE (VEX_LEN_0FC5) },
6000     { "vshufpX",        { XM, Vex, EXx, Ib }, PREFIX_OPCODE },
6001     { Bad_Opcode },
6002     /* c8 */
6003     { Bad_Opcode },
6004     { Bad_Opcode },
6005     { Bad_Opcode },
6006     { Bad_Opcode },
6007     { Bad_Opcode },
6008     { Bad_Opcode },
6009     { Bad_Opcode },
6010     { Bad_Opcode },
6011     /* d0 */
6012     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
6013     { "vpsrlw",         { XM, Vex, EXxmm }, PREFIX_DATA },
6014     { "vpsrld",         { XM, Vex, EXxmm }, PREFIX_DATA },
6015     { "vpsrlq",         { XM, Vex, EXxmm }, PREFIX_DATA },
6016     { "vpaddq",         { XM, Vex, EXx }, PREFIX_DATA },
6017     { "vpmullw",        { XM, Vex, EXx }, PREFIX_DATA },
6018     { VEX_LEN_TABLE (VEX_LEN_0FD6) },
6019     { MOD_TABLE (MOD_VEX_0FD7) },
6020     /* d8 */
6021     { "vpsubusb",       { XM, Vex, EXx }, PREFIX_DATA },
6022     { "vpsubusw",       { XM, Vex, EXx }, PREFIX_DATA },
6023     { "vpminub",        { XM, Vex, EXx }, PREFIX_DATA },
6024     { "vpand",          { XM, Vex, EXx }, PREFIX_DATA },
6025     { "vpaddusb",       { XM, Vex, EXx }, PREFIX_DATA },
6026     { "vpaddusw",       { XM, Vex, EXx }, PREFIX_DATA },
6027     { "vpmaxub",        { XM, Vex, EXx }, PREFIX_DATA },
6028     { "vpandn",         { XM, Vex, EXx }, PREFIX_DATA },
6029     /* e0 */
6030     { "vpavgb",         { XM, Vex, EXx }, PREFIX_DATA },
6031     { "vpsraw",         { XM, Vex, EXxmm }, PREFIX_DATA },
6032     { "vpsrad",         { XM, Vex, EXxmm }, PREFIX_DATA },
6033     { "vpavgw",         { XM, Vex, EXx }, PREFIX_DATA },
6034     { "vpmulhuw",       { XM, Vex, EXx }, PREFIX_DATA },
6035     { "vpmulhw",        { XM, Vex, EXx }, PREFIX_DATA },
6036     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
6037     { MOD_TABLE (MOD_VEX_0FE7) },
6038     /* e8 */
6039     { "vpsubsb",        { XM, Vex, EXx }, PREFIX_DATA },
6040     { "vpsubsw",        { XM, Vex, EXx }, PREFIX_DATA },
6041     { "vpminsw",        { XM, Vex, EXx }, PREFIX_DATA },
6042     { "vpor",           { XM, Vex, EXx }, PREFIX_DATA },
6043     { "vpaddsb",        { XM, Vex, EXx }, PREFIX_DATA },
6044     { "vpaddsw",        { XM, Vex, EXx }, PREFIX_DATA },
6045     { "vpmaxsw",        { XM, Vex, EXx }, PREFIX_DATA },
6046     { "vpxor",          { XM, Vex, EXx }, PREFIX_DATA },
6047     /* f0 */
6048     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
6049     { "vpsllw",         { XM, Vex, EXxmm }, PREFIX_DATA },
6050     { "vpslld",         { XM, Vex, EXxmm }, PREFIX_DATA },
6051     { "vpsllq",         { XM, Vex, EXxmm }, PREFIX_DATA },
6052     { "vpmuludq",       { XM, Vex, EXx }, PREFIX_DATA },
6053     { "vpmaddwd",       { XM, Vex, EXx }, PREFIX_DATA },
6054     { "vpsadbw",        { XM, Vex, EXx }, PREFIX_DATA },
6055     { VEX_LEN_TABLE (VEX_LEN_0FF7) },
6056     /* f8 */
6057     { "vpsubb",         { XM, Vex, EXx }, PREFIX_DATA },
6058     { "vpsubw",         { XM, Vex, EXx }, PREFIX_DATA },
6059     { "vpsubd",         { XM, Vex, EXx }, PREFIX_DATA },
6060     { "vpsubq",         { XM, Vex, EXx }, PREFIX_DATA },
6061     { "vpaddb",         { XM, Vex, EXx }, PREFIX_DATA },
6062     { "vpaddw",         { XM, Vex, EXx }, PREFIX_DATA },
6063     { "vpaddd",         { XM, Vex, EXx }, PREFIX_DATA },
6064     { Bad_Opcode },
6065   },
6066   /* VEX_0F38 */
6067   {
6068     /* 00 */
6069     { "vpshufb",        { XM, Vex, EXx }, PREFIX_DATA },
6070     { "vphaddw",        { XM, Vex, EXx }, PREFIX_DATA },
6071     { "vphaddd",        { XM, Vex, EXx }, PREFIX_DATA },
6072     { "vphaddsw",       { XM, Vex, EXx }, PREFIX_DATA },
6073     { "vpmaddubsw",     { XM, Vex, EXx }, PREFIX_DATA },
6074     { "vphsubw",        { XM, Vex, EXx }, PREFIX_DATA },
6075     { "vphsubd",        { XM, Vex, EXx }, PREFIX_DATA },
6076     { "vphsubsw",       { XM, Vex, EXx }, PREFIX_DATA },
6077     /* 08 */
6078     { "vpsignb",        { XM, Vex, EXx }, PREFIX_DATA },
6079     { "vpsignw",        { XM, Vex, EXx }, PREFIX_DATA },
6080     { "vpsignd",        { XM, Vex, EXx }, PREFIX_DATA },
6081     { "vpmulhrsw",      { XM, Vex, EXx }, PREFIX_DATA },
6082     { VEX_W_TABLE (VEX_W_0F380C) },
6083     { VEX_W_TABLE (VEX_W_0F380D) },
6084     { VEX_W_TABLE (VEX_W_0F380E) },
6085     { VEX_W_TABLE (VEX_W_0F380F) },
6086     /* 10 */
6087     { Bad_Opcode },
6088     { Bad_Opcode },
6089     { Bad_Opcode },
6090     { VEX_W_TABLE (VEX_W_0F3813) },
6091     { Bad_Opcode },
6092     { Bad_Opcode },
6093     { VEX_LEN_TABLE (VEX_LEN_0F3816) },
6094     { "vptest",         { XM, EXx }, PREFIX_DATA },
6095     /* 18 */
6096     { VEX_W_TABLE (VEX_W_0F3818) },
6097     { VEX_LEN_TABLE (VEX_LEN_0F3819) },
6098     { MOD_TABLE (MOD_VEX_0F381A) },
6099     { Bad_Opcode },
6100     { "vpabsb",         { XM, EXx }, PREFIX_DATA },
6101     { "vpabsw",         { XM, EXx }, PREFIX_DATA },
6102     { "vpabsd",         { XM, EXx }, PREFIX_DATA },
6103     { Bad_Opcode },
6104     /* 20 */
6105     { "vpmovsxbw",      { XM, EXxmmq }, PREFIX_DATA },
6106     { "vpmovsxbd",      { XM, EXxmmqd }, PREFIX_DATA },
6107     { "vpmovsxbq",      { XM, EXxmmdw }, PREFIX_DATA },
6108     { "vpmovsxwd",      { XM, EXxmmq }, PREFIX_DATA },
6109     { "vpmovsxwq",      { XM, EXxmmqd }, PREFIX_DATA },
6110     { "vpmovsxdq",      { XM, EXxmmq }, PREFIX_DATA },
6111     { Bad_Opcode },
6112     { Bad_Opcode },
6113     /* 28 */
6114     { "vpmuldq",        { XM, Vex, EXx }, PREFIX_DATA },
6115     { "vpcmpeqq",       { XM, Vex, EXx }, PREFIX_DATA },
6116     { MOD_TABLE (MOD_VEX_0F382A) },
6117     { "vpackusdw",      { XM, Vex, EXx }, PREFIX_DATA },
6118     { MOD_TABLE (MOD_VEX_0F382C) },
6119     { MOD_TABLE (MOD_VEX_0F382D) },
6120     { MOD_TABLE (MOD_VEX_0F382E) },
6121     { MOD_TABLE (MOD_VEX_0F382F) },
6122     /* 30 */
6123     { "vpmovzxbw",      { XM, EXxmmq }, PREFIX_DATA },
6124     { "vpmovzxbd",      { XM, EXxmmqd }, PREFIX_DATA },
6125     { "vpmovzxbq",      { XM, EXxmmdw }, PREFIX_DATA },
6126     { "vpmovzxwd",      { XM, EXxmmq }, PREFIX_DATA },
6127     { "vpmovzxwq",      { XM, EXxmmqd }, PREFIX_DATA },
6128     { "vpmovzxdq",      { XM, EXxmmq }, PREFIX_DATA },
6129     { VEX_LEN_TABLE (VEX_LEN_0F3836) },
6130     { "vpcmpgtq",       { XM, Vex, EXx }, PREFIX_DATA },
6131     /* 38 */
6132     { "vpminsb",        { XM, Vex, EXx }, PREFIX_DATA },
6133     { "vpminsd",        { XM, Vex, EXx }, PREFIX_DATA },
6134     { "vpminuw",        { XM, Vex, EXx }, PREFIX_DATA },
6135     { "vpminud",        { XM, Vex, EXx }, PREFIX_DATA },
6136     { "vpmaxsb",        { XM, Vex, EXx }, PREFIX_DATA },
6137     { "vpmaxsd",        { XM, Vex, EXx }, PREFIX_DATA },
6138     { "vpmaxuw",        { XM, Vex, EXx }, PREFIX_DATA },
6139     { "vpmaxud",        { XM, Vex, EXx }, PREFIX_DATA },
6140     /* 40 */
6141     { "vpmulld",        { XM, Vex, EXx }, PREFIX_DATA },
6142     { VEX_LEN_TABLE (VEX_LEN_0F3841) },
6143     { Bad_Opcode },
6144     { Bad_Opcode },
6145     { Bad_Opcode },
6146     { "vpsrlv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6147     { VEX_W_TABLE (VEX_W_0F3846) },
6148     { "vpsllv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6149     /* 48 */
6150     { Bad_Opcode },
6151     { X86_64_TABLE (X86_64_VEX_0F3849) },
6152     { Bad_Opcode },
6153     { X86_64_TABLE (X86_64_VEX_0F384B) },
6154     { Bad_Opcode },
6155     { Bad_Opcode },
6156     { Bad_Opcode },
6157     { Bad_Opcode },
6158     /* 50 */
6159     { Bad_Opcode },
6160     { Bad_Opcode },
6161     { Bad_Opcode },
6162     { Bad_Opcode },
6163     { Bad_Opcode },
6164     { Bad_Opcode },
6165     { Bad_Opcode },
6166     { Bad_Opcode },
6167     /* 58 */
6168     { VEX_W_TABLE (VEX_W_0F3858) },
6169     { VEX_W_TABLE (VEX_W_0F3859) },
6170     { MOD_TABLE (MOD_VEX_0F385A) },
6171     { Bad_Opcode },
6172     { X86_64_TABLE (X86_64_VEX_0F385C) },
6173     { Bad_Opcode },
6174     { X86_64_TABLE (X86_64_VEX_0F385E) },
6175     { Bad_Opcode },
6176     /* 60 */
6177     { Bad_Opcode },
6178     { Bad_Opcode },
6179     { Bad_Opcode },
6180     { Bad_Opcode },
6181     { Bad_Opcode },
6182     { Bad_Opcode },
6183     { Bad_Opcode },
6184     { Bad_Opcode },
6185     /* 68 */
6186     { Bad_Opcode },
6187     { Bad_Opcode },
6188     { Bad_Opcode },
6189     { Bad_Opcode },
6190     { Bad_Opcode },
6191     { Bad_Opcode },
6192     { Bad_Opcode },
6193     { Bad_Opcode },
6194     /* 70 */
6195     { Bad_Opcode },
6196     { Bad_Opcode },
6197     { Bad_Opcode },
6198     { Bad_Opcode },
6199     { Bad_Opcode },
6200     { Bad_Opcode },
6201     { Bad_Opcode },
6202     { Bad_Opcode },
6203     /* 78 */
6204     { VEX_W_TABLE (VEX_W_0F3878) },
6205     { VEX_W_TABLE (VEX_W_0F3879) },
6206     { Bad_Opcode },
6207     { Bad_Opcode },
6208     { Bad_Opcode },
6209     { Bad_Opcode },
6210     { Bad_Opcode },
6211     { Bad_Opcode },
6212     /* 80 */
6213     { Bad_Opcode },
6214     { Bad_Opcode },
6215     { Bad_Opcode },
6216     { Bad_Opcode },
6217     { Bad_Opcode },
6218     { Bad_Opcode },
6219     { Bad_Opcode },
6220     { Bad_Opcode },
6221     /* 88 */
6222     { Bad_Opcode },
6223     { Bad_Opcode },
6224     { Bad_Opcode },
6225     { Bad_Opcode },
6226     { MOD_TABLE (MOD_VEX_0F388C) },
6227     { Bad_Opcode },
6228     { MOD_TABLE (MOD_VEX_0F388E) },
6229     { Bad_Opcode },
6230     /* 90 */
6231     { "vpgatherd%DQ", { XM, MVexVSIBDWpX, Vex }, PREFIX_DATA },
6232     { "vpgatherq%DQ", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6233     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, PREFIX_DATA },
6234     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6235     { Bad_Opcode },
6236     { Bad_Opcode },
6237     { "vfmaddsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6238     { "vfmsubadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6239     /* 98 */
6240     { "vfmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6241     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6242     { "vfmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6243     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6244     { "vfnmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6245     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6246     { "vfnmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6247     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6248     /* a0 */
6249     { Bad_Opcode },
6250     { Bad_Opcode },
6251     { Bad_Opcode },
6252     { Bad_Opcode },
6253     { Bad_Opcode },
6254     { Bad_Opcode },
6255     { "vfmaddsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6256     { "vfmsubadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6257     /* a8 */
6258     { "vfmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6259     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6260     { "vfmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6261     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6262     { "vfnmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6263     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6264     { "vfnmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6265     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6266     /* b0 */
6267     { Bad_Opcode },
6268     { Bad_Opcode },
6269     { Bad_Opcode },
6270     { Bad_Opcode },
6271     { Bad_Opcode },
6272     { Bad_Opcode },
6273     { "vfmaddsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6274     { "vfmsubadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6275     /* b8 */
6276     { "vfmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6277     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6278     { "vfmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6279     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6280     { "vfnmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6281     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6282     { "vfnmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6283     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6284     /* c0 */
6285     { Bad_Opcode },
6286     { Bad_Opcode },
6287     { Bad_Opcode },
6288     { Bad_Opcode },
6289     { Bad_Opcode },
6290     { Bad_Opcode },
6291     { Bad_Opcode },
6292     { Bad_Opcode },
6293     /* c8 */
6294     { Bad_Opcode },
6295     { Bad_Opcode },
6296     { Bad_Opcode },
6297     { Bad_Opcode },
6298     { Bad_Opcode },
6299     { Bad_Opcode },
6300     { Bad_Opcode },
6301     { VEX_W_TABLE (VEX_W_0F38CF) },
6302     /* d0 */
6303     { Bad_Opcode },
6304     { Bad_Opcode },
6305     { Bad_Opcode },
6306     { Bad_Opcode },
6307     { Bad_Opcode },
6308     { Bad_Opcode },
6309     { Bad_Opcode },
6310     { Bad_Opcode },
6311     /* d8 */
6312     { Bad_Opcode },
6313     { Bad_Opcode },
6314     { Bad_Opcode },
6315     { VEX_LEN_TABLE (VEX_LEN_0F38DB) },
6316     { "vaesenc",        { XM, Vex, EXx }, PREFIX_DATA },
6317     { "vaesenclast",    { XM, Vex, EXx }, PREFIX_DATA },
6318     { "vaesdec",        { XM, Vex, EXx }, PREFIX_DATA },
6319     { "vaesdeclast",    { XM, Vex, EXx }, PREFIX_DATA },
6320     /* e0 */
6321     { Bad_Opcode },
6322     { Bad_Opcode },
6323     { Bad_Opcode },
6324     { Bad_Opcode },
6325     { Bad_Opcode },
6326     { Bad_Opcode },
6327     { Bad_Opcode },
6328     { Bad_Opcode },
6329     /* e8 */
6330     { Bad_Opcode },
6331     { Bad_Opcode },
6332     { Bad_Opcode },
6333     { Bad_Opcode },
6334     { Bad_Opcode },
6335     { Bad_Opcode },
6336     { Bad_Opcode },
6337     { Bad_Opcode },
6338     /* f0 */
6339     { Bad_Opcode },
6340     { Bad_Opcode },
6341     { VEX_LEN_TABLE (VEX_LEN_0F38F2) },
6342     { REG_TABLE (REG_VEX_0F38F3) },
6343     { Bad_Opcode },
6344     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
6345     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
6346     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
6347     /* f8 */
6348     { Bad_Opcode },
6349     { Bad_Opcode },
6350     { Bad_Opcode },
6351     { Bad_Opcode },
6352     { Bad_Opcode },
6353     { Bad_Opcode },
6354     { Bad_Opcode },
6355     { Bad_Opcode },
6356   },
6357   /* VEX_0F3A */
6358   {
6359     /* 00 */
6360     { VEX_LEN_TABLE (VEX_LEN_0F3A00) },
6361     { VEX_LEN_TABLE (VEX_LEN_0F3A01) },
6362     { VEX_W_TABLE (VEX_W_0F3A02) },
6363     { Bad_Opcode },
6364     { VEX_W_TABLE (VEX_W_0F3A04) },
6365     { VEX_W_TABLE (VEX_W_0F3A05) },
6366     { VEX_LEN_TABLE (VEX_LEN_0F3A06) },
6367     { Bad_Opcode },
6368     /* 08 */
6369     { "vroundps",       { XM, EXx, Ib }, PREFIX_DATA },
6370     { "vroundpd",       { XM, EXx, Ib }, PREFIX_DATA },
6371     { "vroundss",       { XMScalar, VexScalar, EXxmm_md, Ib }, PREFIX_DATA },
6372     { "vroundsd",       { XMScalar, VexScalar, EXxmm_mq, Ib }, PREFIX_DATA },
6373     { "vblendps",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6374     { "vblendpd",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6375     { "vpblendw",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6376     { "vpalignr",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6377     /* 10 */
6378     { Bad_Opcode },
6379     { Bad_Opcode },
6380     { Bad_Opcode },
6381     { Bad_Opcode },
6382     { VEX_LEN_TABLE (VEX_LEN_0F3A14) },
6383     { VEX_LEN_TABLE (VEX_LEN_0F3A15) },
6384     { VEX_LEN_TABLE (VEX_LEN_0F3A16) },
6385     { VEX_LEN_TABLE (VEX_LEN_0F3A17) },
6386     /* 18 */
6387     { VEX_LEN_TABLE (VEX_LEN_0F3A18) },
6388     { VEX_LEN_TABLE (VEX_LEN_0F3A19) },
6389     { Bad_Opcode },
6390     { Bad_Opcode },
6391     { Bad_Opcode },
6392     { VEX_W_TABLE (VEX_W_0F3A1D) },
6393     { Bad_Opcode },
6394     { Bad_Opcode },
6395     /* 20 */
6396     { VEX_LEN_TABLE (VEX_LEN_0F3A20) },
6397     { VEX_LEN_TABLE (VEX_LEN_0F3A21) },
6398     { VEX_LEN_TABLE (VEX_LEN_0F3A22) },
6399     { Bad_Opcode },
6400     { Bad_Opcode },
6401     { Bad_Opcode },
6402     { Bad_Opcode },
6403     { Bad_Opcode },
6404     /* 28 */
6405     { Bad_Opcode },
6406     { Bad_Opcode },
6407     { Bad_Opcode },
6408     { Bad_Opcode },
6409     { Bad_Opcode },
6410     { Bad_Opcode },
6411     { Bad_Opcode },
6412     { Bad_Opcode },
6413     /* 30 */
6414     { VEX_LEN_TABLE (VEX_LEN_0F3A30) },
6415     { VEX_LEN_TABLE (VEX_LEN_0F3A31) },
6416     { VEX_LEN_TABLE (VEX_LEN_0F3A32) },
6417     { VEX_LEN_TABLE (VEX_LEN_0F3A33) },
6418     { Bad_Opcode },
6419     { Bad_Opcode },
6420     { Bad_Opcode },
6421     { Bad_Opcode },
6422     /* 38 */
6423     { VEX_LEN_TABLE (VEX_LEN_0F3A38) },
6424     { VEX_LEN_TABLE (VEX_LEN_0F3A39) },
6425     { Bad_Opcode },
6426     { Bad_Opcode },
6427     { Bad_Opcode },
6428     { Bad_Opcode },
6429     { Bad_Opcode },
6430     { Bad_Opcode },
6431     /* 40 */
6432     { "vdpps",          { XM, Vex, EXx, Ib }, PREFIX_DATA },
6433     { VEX_LEN_TABLE (VEX_LEN_0F3A41) },
6434     { "vmpsadbw",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6435     { Bad_Opcode },
6436     { "vpclmulqdq",     { XM, Vex, EXx, PCLMUL }, PREFIX_DATA },
6437     { Bad_Opcode },
6438     { VEX_LEN_TABLE (VEX_LEN_0F3A46) },
6439     { Bad_Opcode },
6440     /* 48 */
6441     { "vpermil2ps",     { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6442     { "vpermil2pd",     { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6443     { VEX_W_TABLE (VEX_W_0F3A4A) },
6444     { VEX_W_TABLE (VEX_W_0F3A4B) },
6445     { VEX_W_TABLE (VEX_W_0F3A4C) },
6446     { Bad_Opcode },
6447     { Bad_Opcode },
6448     { Bad_Opcode },
6449     /* 50 */
6450     { Bad_Opcode },
6451     { Bad_Opcode },
6452     { Bad_Opcode },
6453     { Bad_Opcode },
6454     { Bad_Opcode },
6455     { Bad_Opcode },
6456     { Bad_Opcode },
6457     { Bad_Opcode },
6458     /* 58 */
6459     { Bad_Opcode },
6460     { Bad_Opcode },
6461     { Bad_Opcode },
6462     { Bad_Opcode },
6463     { "vfmaddsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6464     { "vfmaddsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6465     { "vfmsubaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6466     { "vfmsubaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6467     /* 60 */
6468     { VEX_LEN_TABLE (VEX_LEN_0F3A60) },
6469     { VEX_LEN_TABLE (VEX_LEN_0F3A61) },
6470     { VEX_LEN_TABLE (VEX_LEN_0F3A62) },
6471     { VEX_LEN_TABLE (VEX_LEN_0F3A63) },
6472     { Bad_Opcode },
6473     { Bad_Opcode },
6474     { Bad_Opcode },
6475     { Bad_Opcode },
6476     /* 68 */
6477     { "vfmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6478     { "vfmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6479     { "vfmaddss",       { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
6480     { "vfmaddsd",       { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
6481     { "vfmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6482     { "vfmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6483     { "vfmsubss",       { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
6484     { "vfmsubsd",       { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
6485     /* 70 */
6486     { Bad_Opcode },
6487     { Bad_Opcode },
6488     { Bad_Opcode },
6489     { Bad_Opcode },
6490     { Bad_Opcode },
6491     { Bad_Opcode },
6492     { Bad_Opcode },
6493     { Bad_Opcode },
6494     /* 78 */
6495     { "vfnmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6496     { "vfnmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6497     { "vfnmaddss",      { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
6498     { "vfnmaddsd",      { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
6499     { "vfnmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6500     { "vfnmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6501     { "vfnmsubss",      { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
6502     { "vfnmsubsd",      { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
6503     /* 80 */
6504     { Bad_Opcode },
6505     { Bad_Opcode },
6506     { Bad_Opcode },
6507     { Bad_Opcode },
6508     { Bad_Opcode },
6509     { Bad_Opcode },
6510     { Bad_Opcode },
6511     { Bad_Opcode },
6512     /* 88 */
6513     { Bad_Opcode },
6514     { Bad_Opcode },
6515     { Bad_Opcode },
6516     { Bad_Opcode },
6517     { Bad_Opcode },
6518     { Bad_Opcode },
6519     { Bad_Opcode },
6520     { Bad_Opcode },
6521     /* 90 */
6522     { Bad_Opcode },
6523     { Bad_Opcode },
6524     { Bad_Opcode },
6525     { Bad_Opcode },
6526     { Bad_Opcode },
6527     { Bad_Opcode },
6528     { Bad_Opcode },
6529     { Bad_Opcode },
6530     /* 98 */
6531     { Bad_Opcode },
6532     { Bad_Opcode },
6533     { Bad_Opcode },
6534     { Bad_Opcode },
6535     { Bad_Opcode },
6536     { Bad_Opcode },
6537     { Bad_Opcode },
6538     { Bad_Opcode },
6539     /* a0 */
6540     { Bad_Opcode },
6541     { Bad_Opcode },
6542     { Bad_Opcode },
6543     { Bad_Opcode },
6544     { Bad_Opcode },
6545     { Bad_Opcode },
6546     { Bad_Opcode },
6547     { Bad_Opcode },
6548     /* a8 */
6549     { Bad_Opcode },
6550     { Bad_Opcode },
6551     { Bad_Opcode },
6552     { Bad_Opcode },
6553     { Bad_Opcode },
6554     { Bad_Opcode },
6555     { Bad_Opcode },
6556     { Bad_Opcode },
6557     /* b0 */
6558     { Bad_Opcode },
6559     { Bad_Opcode },
6560     { Bad_Opcode },
6561     { Bad_Opcode },
6562     { Bad_Opcode },
6563     { Bad_Opcode },
6564     { Bad_Opcode },
6565     { Bad_Opcode },
6566     /* b8 */
6567     { Bad_Opcode },
6568     { Bad_Opcode },
6569     { Bad_Opcode },
6570     { Bad_Opcode },
6571     { Bad_Opcode },
6572     { Bad_Opcode },
6573     { Bad_Opcode },
6574     { Bad_Opcode },
6575     /* c0 */
6576     { Bad_Opcode },
6577     { Bad_Opcode },
6578     { Bad_Opcode },
6579     { Bad_Opcode },
6580     { Bad_Opcode },
6581     { Bad_Opcode },
6582     { Bad_Opcode },
6583     { Bad_Opcode },
6584     /* c8 */
6585     { Bad_Opcode },
6586     { Bad_Opcode },
6587     { Bad_Opcode },
6588     { Bad_Opcode },
6589     { Bad_Opcode },
6590     { Bad_Opcode },
6591     { VEX_W_TABLE (VEX_W_0F3ACE) },
6592     { VEX_W_TABLE (VEX_W_0F3ACF) },
6593     /* d0 */
6594     { Bad_Opcode },
6595     { Bad_Opcode },
6596     { Bad_Opcode },
6597     { Bad_Opcode },
6598     { Bad_Opcode },
6599     { Bad_Opcode },
6600     { Bad_Opcode },
6601     { Bad_Opcode },
6602     /* d8 */
6603     { Bad_Opcode },
6604     { Bad_Opcode },
6605     { Bad_Opcode },
6606     { Bad_Opcode },
6607     { Bad_Opcode },
6608     { Bad_Opcode },
6609     { Bad_Opcode },
6610     { VEX_LEN_TABLE (VEX_LEN_0F3ADF) },
6611     /* e0 */
6612     { Bad_Opcode },
6613     { Bad_Opcode },
6614     { Bad_Opcode },
6615     { Bad_Opcode },
6616     { Bad_Opcode },
6617     { Bad_Opcode },
6618     { Bad_Opcode },
6619     { Bad_Opcode },
6620     /* e8 */
6621     { Bad_Opcode },
6622     { Bad_Opcode },
6623     { Bad_Opcode },
6624     { Bad_Opcode },
6625     { Bad_Opcode },
6626     { Bad_Opcode },
6627     { Bad_Opcode },
6628     { Bad_Opcode },
6629     /* f0 */
6630     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
6631     { Bad_Opcode },
6632     { Bad_Opcode },
6633     { Bad_Opcode },
6634     { Bad_Opcode },
6635     { Bad_Opcode },
6636     { Bad_Opcode },
6637     { Bad_Opcode },
6638     /* f8 */
6639     { Bad_Opcode },
6640     { Bad_Opcode },
6641     { Bad_Opcode },
6642     { Bad_Opcode },
6643     { Bad_Opcode },
6644     { Bad_Opcode },
6645     { Bad_Opcode },
6646     { Bad_Opcode },
6647   },
6648 };
6649
6650 #include "i386-dis-evex.h"
6651
6652 static const struct dis386 vex_len_table[][2] = {
6653   /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */
6654   {
6655     { "vmovlpX",        { XM, Vex, EXq }, 0 },
6656   },
6657
6658   /* VEX_LEN_0F12_P_0_M_1 */
6659   {
6660     { "vmovhlps",       { XM, Vex, EXq }, 0 },
6661   },
6662
6663   /* VEX_LEN_0F13_M_0 */
6664   {
6665     { "vmovlpX",        { EXq, XM }, PREFIX_OPCODE },
6666   },
6667
6668   /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */
6669   {
6670     { "vmovhpX",        { XM, Vex, EXq }, 0 },
6671   },
6672
6673   /* VEX_LEN_0F16_P_0_M_1 */
6674   {
6675     { "vmovlhps",       { XM, Vex, EXq }, 0 },
6676   },
6677
6678   /* VEX_LEN_0F17_M_0 */
6679   {
6680     { "vmovhpX",        { EXq, XM }, PREFIX_OPCODE },
6681   },
6682
6683   /* VEX_LEN_0F41_P_0 */
6684   {
6685     { Bad_Opcode },
6686     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
6687   },
6688   /* VEX_LEN_0F41_P_2 */
6689   {
6690     { Bad_Opcode },
6691     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
6692   },
6693   /* VEX_LEN_0F42_P_0 */
6694   {
6695     { Bad_Opcode },
6696     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
6697   },
6698   /* VEX_LEN_0F42_P_2 */
6699   {
6700     { Bad_Opcode },
6701     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
6702   },
6703   /* VEX_LEN_0F44_P_0 */
6704   {
6705     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
6706   },
6707   /* VEX_LEN_0F44_P_2 */
6708   {
6709     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
6710   },
6711   /* VEX_LEN_0F45_P_0 */
6712   {
6713     { Bad_Opcode },
6714     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
6715   },
6716   /* VEX_LEN_0F45_P_2 */
6717   {
6718     { Bad_Opcode },
6719     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
6720   },
6721   /* VEX_LEN_0F46_P_0 */
6722   {
6723     { Bad_Opcode },
6724     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
6725   },
6726   /* VEX_LEN_0F46_P_2 */
6727   {
6728     { Bad_Opcode },
6729     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
6730   },
6731   /* VEX_LEN_0F47_P_0 */
6732   {
6733     { Bad_Opcode },
6734     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
6735   },
6736   /* VEX_LEN_0F47_P_2 */
6737   {
6738     { Bad_Opcode },
6739     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
6740   },
6741   /* VEX_LEN_0F4A_P_0 */
6742   {
6743     { Bad_Opcode },
6744     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
6745   },
6746   /* VEX_LEN_0F4A_P_2 */
6747   {
6748     { Bad_Opcode },
6749     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
6750   },
6751   /* VEX_LEN_0F4B_P_0 */
6752   {
6753     { Bad_Opcode },
6754     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
6755   },
6756   /* VEX_LEN_0F4B_P_2 */
6757   {
6758     { Bad_Opcode },
6759     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
6760   },
6761
6762   /* VEX_LEN_0F6E */
6763   {
6764     { "vmovK",          { XMScalar, Edq }, PREFIX_DATA },
6765   },
6766
6767   /* VEX_LEN_0F77 */
6768   {
6769     { "vzeroupper",     { XX }, 0 },
6770     { "vzeroall",       { XX }, 0 },
6771   },
6772
6773   /* VEX_LEN_0F7E_P_1 */
6774   {
6775     { "vmovq",          { XMScalar, EXxmm_mq }, 0 },
6776   },
6777
6778   /* VEX_LEN_0F7E_P_2 */
6779   {
6780     { "vmovK",          { Edq, XMScalar }, 0 },
6781   },
6782
6783   /* VEX_LEN_0F90_P_0 */
6784   {
6785     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
6786   },
6787
6788   /* VEX_LEN_0F90_P_2 */
6789   {
6790     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
6791   },
6792
6793   /* VEX_LEN_0F91_P_0 */
6794   {
6795     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
6796   },
6797
6798   /* VEX_LEN_0F91_P_2 */
6799   {
6800     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
6801   },
6802
6803   /* VEX_LEN_0F92_P_0 */
6804   {
6805     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
6806   },
6807
6808   /* VEX_LEN_0F92_P_2 */
6809   {
6810     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
6811   },
6812
6813   /* VEX_LEN_0F92_P_3 */
6814   {
6815     { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) },
6816   },
6817
6818   /* VEX_LEN_0F93_P_0 */
6819   {
6820     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
6821   },
6822
6823   /* VEX_LEN_0F93_P_2 */
6824   {
6825     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
6826   },
6827
6828   /* VEX_LEN_0F93_P_3 */
6829   {
6830     { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) },
6831   },
6832
6833   /* VEX_LEN_0F98_P_0 */
6834   {
6835     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
6836   },
6837
6838   /* VEX_LEN_0F98_P_2 */
6839   {
6840     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
6841   },
6842
6843   /* VEX_LEN_0F99_P_0 */
6844   {
6845     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
6846   },
6847
6848   /* VEX_LEN_0F99_P_2 */
6849   {
6850     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
6851   },
6852
6853   /* VEX_LEN_0FAE_R_2_M_0 */
6854   {
6855     { "vldmxcsr",       { Md }, 0 },
6856   },
6857
6858   /* VEX_LEN_0FAE_R_3_M_0 */
6859   {
6860     { "vstmxcsr",       { Md }, 0 },
6861   },
6862
6863   /* VEX_LEN_0FC4 */
6864   {
6865     { "vpinsrw",        { XM, Vex, Edqw, Ib }, PREFIX_DATA },
6866   },
6867
6868   /* VEX_LEN_0FC5 */
6869   {
6870     { "vpextrw",        { Gdq, XS, Ib }, PREFIX_DATA },
6871   },
6872
6873   /* VEX_LEN_0FD6 */
6874   {
6875     { "vmovq",          { EXqS, XMScalar }, PREFIX_DATA },
6876   },
6877
6878   /* VEX_LEN_0FF7 */
6879   {
6880     { "vmaskmovdqu",    { XM, XS }, PREFIX_DATA },
6881   },
6882
6883   /* VEX_LEN_0F3816 */
6884   {
6885     { Bad_Opcode },
6886     { VEX_W_TABLE (VEX_W_0F3816_L_1) },
6887   },
6888
6889   /* VEX_LEN_0F3819 */
6890   {
6891     { Bad_Opcode },
6892     { VEX_W_TABLE (VEX_W_0F3819_L_1) },
6893   },
6894
6895   /* VEX_LEN_0F381A_M_0 */
6896   {
6897     { Bad_Opcode },
6898     { VEX_W_TABLE (VEX_W_0F381A_M_0_L_1) },
6899   },
6900
6901   /* VEX_LEN_0F3836 */
6902   {
6903     { Bad_Opcode },
6904     { VEX_W_TABLE (VEX_W_0F3836) },
6905   },
6906
6907   /* VEX_LEN_0F3841 */
6908   {
6909     { "vphminposuw",    { XM, EXx }, PREFIX_DATA },
6910   },
6911
6912    /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_0 */
6913   {
6914     { "ldtilecfg", { M }, 0 },
6915   },
6916
6917   /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0 */
6918   {
6919     { "tilerelease", { Skip_MODRM }, 0 },
6920   },
6921
6922   /* VEX_LEN_0F3849_X86_64_P_2_W_0_M_0 */
6923   {
6924     { "sttilecfg", { M }, 0 },
6925   },
6926
6927   /* VEX_LEN_0F3849_X86_64_P_3_W_0_M_0 */
6928   {
6929     { "tilezero", { TMM, Skip_MODRM }, 0 },
6930   },
6931
6932   /* VEX_LEN_0F384B_X86_64_P_1_W_0_M_0 */
6933   {
6934     { "tilestored", { MVexSIBMEM, TMM }, 0 },
6935   },
6936   /* VEX_LEN_0F384B_X86_64_P_2_W_0_M_0 */
6937   {
6938     { "tileloaddt1", { TMM, MVexSIBMEM }, 0 },
6939   },
6940
6941   /* VEX_LEN_0F384B_X86_64_P_3_W_0_M_0 */
6942   {
6943     { "tileloadd", { TMM, MVexSIBMEM }, 0 },
6944   },
6945
6946   /* VEX_LEN_0F385A_M_0 */
6947   {
6948     { Bad_Opcode },
6949     { VEX_W_TABLE (VEX_W_0F385A_M_0_L_0) },
6950   },
6951
6952   /* VEX_LEN_0F385C_X86_64_P_1_W_0_M_0 */
6953   {
6954     { "tdpbf16ps", { TMM, EXtmm, VexTmm }, 0 },
6955   },
6956
6957   /* VEX_LEN_0F385E_X86_64_P_0_W_0_M_0 */
6958   {
6959     { "tdpbuud", {TMM, EXtmm, VexTmm }, 0 },
6960   },
6961
6962   /* VEX_LEN_0F385E_X86_64_P_1_W_0_M_0 */
6963   {
6964     { "tdpbsud", {TMM, EXtmm, VexTmm }, 0 },
6965   },
6966
6967   /* VEX_LEN_0F385E_X86_64_P_2_W_0_M_0 */
6968   {
6969     { "tdpbusd", {TMM, EXtmm, VexTmm }, 0 },
6970   },
6971
6972   /* VEX_LEN_0F385E_X86_64_P_3_W_0_M_0 */
6973   {
6974     { "tdpbssd", {TMM, EXtmm, VexTmm }, 0 },
6975   },
6976
6977   /* VEX_LEN_0F38DB */
6978   {
6979     { "vaesimc",        { XM, EXx }, PREFIX_DATA },
6980   },
6981
6982   /* VEX_LEN_0F38F2 */
6983   {
6984     { "andnS",          { Gdq, VexGdq, Edq }, PREFIX_OPCODE },
6985   },
6986
6987   /* VEX_LEN_0F38F3_R_1 */
6988   {
6989     { "blsrS",          { VexGdq, Edq }, PREFIX_OPCODE },
6990   },
6991
6992   /* VEX_LEN_0F38F3_R_2 */
6993   {
6994     { "blsmskS",        { VexGdq, Edq }, PREFIX_OPCODE },
6995   },
6996
6997   /* VEX_LEN_0F38F3_R_3 */
6998   {
6999     { "blsiS",          { VexGdq, Edq }, PREFIX_OPCODE },
7000   },
7001
7002   /* VEX_LEN_0F38F5_P_0 */
7003   {
7004     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
7005   },
7006
7007   /* VEX_LEN_0F38F5_P_1 */
7008   {
7009     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
7010   },
7011
7012   /* VEX_LEN_0F38F5_P_3 */
7013   {
7014     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
7015   },
7016
7017   /* VEX_LEN_0F38F6_P_3 */
7018   {
7019     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
7020   },
7021
7022   /* VEX_LEN_0F38F7_P_0 */
7023   {
7024     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
7025   },
7026
7027   /* VEX_LEN_0F38F7_P_1 */
7028   {
7029     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
7030   },
7031
7032   /* VEX_LEN_0F38F7_P_2 */
7033   {
7034     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
7035   },
7036
7037   /* VEX_LEN_0F38F7_P_3 */
7038   {
7039     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
7040   },
7041
7042   /* VEX_LEN_0F3A00 */
7043   {
7044     { Bad_Opcode },
7045     { VEX_W_TABLE (VEX_W_0F3A00_L_1) },
7046   },
7047
7048   /* VEX_LEN_0F3A01 */
7049   {
7050     { Bad_Opcode },
7051     { VEX_W_TABLE (VEX_W_0F3A01_L_1) },
7052   },
7053
7054   /* VEX_LEN_0F3A06 */
7055   {
7056     { Bad_Opcode },
7057     { VEX_W_TABLE (VEX_W_0F3A06_L_1) },
7058   },
7059
7060   /* VEX_LEN_0F3A14 */
7061   {
7062     { "vpextrb",        { Edqb, XM, Ib }, PREFIX_DATA },
7063   },
7064
7065   /* VEX_LEN_0F3A15 */
7066   {
7067     { "vpextrw",        { Edqw, XM, Ib }, PREFIX_DATA },
7068   },
7069
7070   /* VEX_LEN_0F3A16  */
7071   {
7072     { "vpextrK",        { Edq, XM, Ib }, PREFIX_DATA },
7073   },
7074
7075   /* VEX_LEN_0F3A17 */
7076   {
7077     { "vextractps",     { Edqd, XM, Ib }, PREFIX_DATA },
7078   },
7079
7080   /* VEX_LEN_0F3A18 */
7081   {
7082     { Bad_Opcode },
7083     { VEX_W_TABLE (VEX_W_0F3A18_L_1) },
7084   },
7085
7086   /* VEX_LEN_0F3A19 */
7087   {
7088     { Bad_Opcode },
7089     { VEX_W_TABLE (VEX_W_0F3A19_L_1) },
7090   },
7091
7092   /* VEX_LEN_0F3A20 */
7093   {
7094     { "vpinsrb",        { XM, Vex, Edqb, Ib }, PREFIX_DATA },
7095   },
7096
7097   /* VEX_LEN_0F3A21 */
7098   {
7099     { "vinsertps",      { XM, Vex, EXd, Ib }, PREFIX_DATA },
7100   },
7101
7102   /* VEX_LEN_0F3A22 */
7103   {
7104     { "vpinsrK",        { XM, Vex, Edq, Ib }, PREFIX_DATA },
7105   },
7106
7107   /* VEX_LEN_0F3A30 */
7108   {
7109     { MOD_TABLE (MOD_VEX_0F3A30_L_0) },
7110   },
7111
7112   /* VEX_LEN_0F3A31 */
7113   {
7114     { MOD_TABLE (MOD_VEX_0F3A31_L_0) },
7115   },
7116
7117   /* VEX_LEN_0F3A32 */
7118   {
7119     { MOD_TABLE (MOD_VEX_0F3A32_L_0) },
7120   },
7121
7122   /* VEX_LEN_0F3A33 */
7123   {
7124     { MOD_TABLE (MOD_VEX_0F3A33_L_0) },
7125   },
7126
7127   /* VEX_LEN_0F3A38 */
7128   {
7129     { Bad_Opcode },
7130     { VEX_W_TABLE (VEX_W_0F3A38_L_1) },
7131   },
7132
7133   /* VEX_LEN_0F3A39 */
7134   {
7135     { Bad_Opcode },
7136     { VEX_W_TABLE (VEX_W_0F3A39_L_1) },
7137   },
7138
7139   /* VEX_LEN_0F3A41 */
7140   {
7141     { "vdppd",          { XM, Vex, EXx, Ib }, PREFIX_DATA },
7142   },
7143
7144   /* VEX_LEN_0F3A46 */
7145   {
7146     { Bad_Opcode },
7147     { VEX_W_TABLE (VEX_W_0F3A46_L_1) },
7148   },
7149
7150   /* VEX_LEN_0F3A60 */
7151   {
7152     { "vpcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7153   },
7154
7155   /* VEX_LEN_0F3A61 */
7156   {
7157     { "vpcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7158   },
7159
7160   /* VEX_LEN_0F3A62 */
7161   {
7162     { "vpcmpistrm",     { XM, EXx, Ib }, PREFIX_DATA },
7163   },
7164
7165   /* VEX_LEN_0F3A63 */
7166   {
7167     { "vpcmpistri",     { XM, EXx, Ib }, PREFIX_DATA },
7168   },
7169
7170   /* VEX_LEN_0F3ADF */
7171   {
7172     { "vaeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
7173   },
7174
7175   /* VEX_LEN_0F3AF0_P_3 */
7176   {
7177     { "rorxS",          { Gdq, Edq, Ib }, 0 },
7178   },
7179
7180   /* VEX_LEN_0FXOP_08_85 */
7181   {
7182     { VEX_W_TABLE (VEX_W_0FXOP_08_85_L_0) },
7183   },
7184
7185   /* VEX_LEN_0FXOP_08_86 */
7186   {
7187     { VEX_W_TABLE (VEX_W_0FXOP_08_86_L_0) },
7188   },
7189
7190   /* VEX_LEN_0FXOP_08_87 */
7191   {
7192     { VEX_W_TABLE (VEX_W_0FXOP_08_87_L_0) },
7193   },
7194
7195   /* VEX_LEN_0FXOP_08_8E */
7196   {
7197     { VEX_W_TABLE (VEX_W_0FXOP_08_8E_L_0) },
7198   },
7199
7200   /* VEX_LEN_0FXOP_08_8F */
7201   {
7202     { VEX_W_TABLE (VEX_W_0FXOP_08_8F_L_0) },
7203   },
7204
7205   /* VEX_LEN_0FXOP_08_95 */
7206   {
7207     { VEX_W_TABLE (VEX_W_0FXOP_08_95_L_0) },
7208   },
7209
7210   /* VEX_LEN_0FXOP_08_96 */
7211   {
7212     { VEX_W_TABLE (VEX_W_0FXOP_08_96_L_0) },
7213   },
7214
7215   /* VEX_LEN_0FXOP_08_97 */
7216   {
7217     { VEX_W_TABLE (VEX_W_0FXOP_08_97_L_0) },
7218   },
7219
7220   /* VEX_LEN_0FXOP_08_9E */
7221   {
7222     { VEX_W_TABLE (VEX_W_0FXOP_08_9E_L_0) },
7223   },
7224
7225   /* VEX_LEN_0FXOP_08_9F */
7226   {
7227     { VEX_W_TABLE (VEX_W_0FXOP_08_9F_L_0) },
7228   },
7229
7230   /* VEX_LEN_0FXOP_08_A3 */
7231   {
7232     { "vpperm",         { XM, Vex, EXx, XMVexI4 }, 0 },
7233   },
7234
7235   /* VEX_LEN_0FXOP_08_A6 */
7236   {
7237     { VEX_W_TABLE (VEX_W_0FXOP_08_A6_L_0) },
7238   },
7239
7240   /* VEX_LEN_0FXOP_08_B6 */
7241   {
7242     { VEX_W_TABLE (VEX_W_0FXOP_08_B6_L_0) },
7243   },
7244
7245   /* VEX_LEN_0FXOP_08_C0 */
7246   {
7247     { VEX_W_TABLE (VEX_W_0FXOP_08_C0_L_0) },
7248   },
7249
7250   /* VEX_LEN_0FXOP_08_C1 */
7251   {
7252     { VEX_W_TABLE (VEX_W_0FXOP_08_C1_L_0) },
7253   },
7254
7255   /* VEX_LEN_0FXOP_08_C2 */
7256   {
7257     { VEX_W_TABLE (VEX_W_0FXOP_08_C2_L_0) },
7258   },
7259
7260   /* VEX_LEN_0FXOP_08_C3 */
7261   {
7262     { VEX_W_TABLE (VEX_W_0FXOP_08_C3_L_0) },
7263   },
7264
7265   /* VEX_LEN_0FXOP_08_CC */
7266   {
7267     { VEX_W_TABLE (VEX_W_0FXOP_08_CC_L_0) },
7268   },
7269
7270   /* VEX_LEN_0FXOP_08_CD */
7271   {
7272     { VEX_W_TABLE (VEX_W_0FXOP_08_CD_L_0) },
7273   },
7274
7275   /* VEX_LEN_0FXOP_08_CE */
7276   {
7277     { VEX_W_TABLE (VEX_W_0FXOP_08_CE_L_0) },
7278   },
7279
7280   /* VEX_LEN_0FXOP_08_CF */
7281   {
7282     { VEX_W_TABLE (VEX_W_0FXOP_08_CF_L_0) },
7283   },
7284
7285   /* VEX_LEN_0FXOP_08_EC */
7286   {
7287     { VEX_W_TABLE (VEX_W_0FXOP_08_EC_L_0) },
7288   },
7289
7290   /* VEX_LEN_0FXOP_08_ED */
7291   {
7292     { VEX_W_TABLE (VEX_W_0FXOP_08_ED_L_0) },
7293   },
7294
7295   /* VEX_LEN_0FXOP_08_EE */
7296   {
7297     { VEX_W_TABLE (VEX_W_0FXOP_08_EE_L_0) },
7298   },
7299
7300   /* VEX_LEN_0FXOP_08_EF */
7301   {
7302     { VEX_W_TABLE (VEX_W_0FXOP_08_EF_L_0) },
7303   },
7304
7305   /* VEX_LEN_0FXOP_09_01 */
7306   {
7307     { REG_TABLE (REG_0FXOP_09_01_L_0) },
7308   },
7309
7310   /* VEX_LEN_0FXOP_09_02 */
7311   {
7312     { REG_TABLE (REG_0FXOP_09_02_L_0) },
7313   },
7314
7315   /* VEX_LEN_0FXOP_09_12_M_1 */
7316   {
7317     { REG_TABLE (REG_0FXOP_09_12_M_1_L_0) },
7318   },
7319
7320   /* VEX_LEN_0FXOP_09_82_W_0 */
7321   {
7322     { "vfrczss",        { XM, EXd }, 0 },
7323   },
7324
7325   /* VEX_LEN_0FXOP_09_83_W_0 */
7326   {
7327     { "vfrczsd",        { XM, EXq }, 0 },
7328   },
7329
7330   /* VEX_LEN_0FXOP_09_90 */
7331   {
7332     { "vprotb",         { XM, EXx, VexW }, 0 },
7333   },
7334
7335   /* VEX_LEN_0FXOP_09_91 */
7336   {
7337     { "vprotw",         { XM, EXx, VexW }, 0 },
7338   },
7339
7340   /* VEX_LEN_0FXOP_09_92 */
7341   {
7342     { "vprotd",         { XM, EXx, VexW }, 0 },
7343   },
7344
7345   /* VEX_LEN_0FXOP_09_93 */
7346   {
7347     { "vprotq",         { XM, EXx, VexW }, 0 },
7348   },
7349
7350   /* VEX_LEN_0FXOP_09_94 */
7351   {
7352     { "vpshlb",         { XM, EXx, VexW }, 0 },
7353   },
7354
7355   /* VEX_LEN_0FXOP_09_95 */
7356   {
7357     { "vpshlw",         { XM, EXx, VexW }, 0 },
7358   },
7359
7360   /* VEX_LEN_0FXOP_09_96 */
7361   {
7362     { "vpshld",         { XM, EXx, VexW }, 0 },
7363   },
7364
7365   /* VEX_LEN_0FXOP_09_97 */
7366   {
7367     { "vpshlq",         { XM, EXx, VexW }, 0 },
7368   },
7369
7370   /* VEX_LEN_0FXOP_09_98 */
7371   {
7372     { "vpshab",         { XM, EXx, VexW }, 0 },
7373   },
7374
7375   /* VEX_LEN_0FXOP_09_99 */
7376   {
7377     { "vpshaw",         { XM, EXx, VexW }, 0 },
7378   },
7379
7380   /* VEX_LEN_0FXOP_09_9A */
7381   {
7382     { "vpshad",         { XM, EXx, VexW }, 0 },
7383   },
7384
7385   /* VEX_LEN_0FXOP_09_9B */
7386   {
7387     { "vpshaq",         { XM, EXx, VexW }, 0 },
7388   },
7389
7390   /* VEX_LEN_0FXOP_09_C1 */
7391   {
7392     { VEX_W_TABLE (VEX_W_0FXOP_09_C1_L_0) },
7393   },
7394
7395   /* VEX_LEN_0FXOP_09_C2 */
7396   {
7397     { VEX_W_TABLE (VEX_W_0FXOP_09_C2_L_0) },
7398   },
7399
7400   /* VEX_LEN_0FXOP_09_C3 */
7401   {
7402     { VEX_W_TABLE (VEX_W_0FXOP_09_C3_L_0) },
7403   },
7404
7405   /* VEX_LEN_0FXOP_09_C6 */
7406   {
7407     { VEX_W_TABLE (VEX_W_0FXOP_09_C6_L_0) },
7408   },
7409
7410   /* VEX_LEN_0FXOP_09_C7 */
7411   {
7412     { VEX_W_TABLE (VEX_W_0FXOP_09_C7_L_0) },
7413   },
7414
7415   /* VEX_LEN_0FXOP_09_CB */
7416   {
7417     { VEX_W_TABLE (VEX_W_0FXOP_09_CB_L_0) },
7418   },
7419
7420   /* VEX_LEN_0FXOP_09_D1 */
7421   {
7422     { VEX_W_TABLE (VEX_W_0FXOP_09_D1_L_0) },
7423   },
7424
7425   /* VEX_LEN_0FXOP_09_D2 */
7426   {
7427     { VEX_W_TABLE (VEX_W_0FXOP_09_D2_L_0) },
7428   },
7429
7430   /* VEX_LEN_0FXOP_09_D3 */
7431   {
7432     { VEX_W_TABLE (VEX_W_0FXOP_09_D3_L_0) },
7433   },
7434
7435   /* VEX_LEN_0FXOP_09_D6 */
7436   {
7437     { VEX_W_TABLE (VEX_W_0FXOP_09_D6_L_0) },
7438   },
7439
7440   /* VEX_LEN_0FXOP_09_D7 */
7441   {
7442     { VEX_W_TABLE (VEX_W_0FXOP_09_D7_L_0) },
7443   },
7444
7445   /* VEX_LEN_0FXOP_09_DB */
7446   {
7447     { VEX_W_TABLE (VEX_W_0FXOP_09_DB_L_0) },
7448   },
7449
7450   /* VEX_LEN_0FXOP_09_E1 */
7451   {
7452     { VEX_W_TABLE (VEX_W_0FXOP_09_E1_L_0) },
7453   },
7454
7455   /* VEX_LEN_0FXOP_09_E2 */
7456   {
7457     { VEX_W_TABLE (VEX_W_0FXOP_09_E2_L_0) },
7458   },
7459
7460   /* VEX_LEN_0FXOP_09_E3 */
7461   {
7462     { VEX_W_TABLE (VEX_W_0FXOP_09_E3_L_0) },
7463   },
7464
7465   /* VEX_LEN_0FXOP_0A_12 */
7466   {
7467     { REG_TABLE (REG_0FXOP_0A_12_L_0) },
7468   },
7469 };
7470
7471 #include "i386-dis-evex-len.h"
7472
7473 static const struct dis386 vex_w_table[][2] = {
7474   {
7475     /* VEX_W_0F41_P_0_LEN_1 */
7476     { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
7477     { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
7478   },
7479   {
7480     /* VEX_W_0F41_P_2_LEN_1 */
7481     { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
7482     { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
7483   },
7484   {
7485     /* VEX_W_0F42_P_0_LEN_1 */
7486     { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
7487     { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
7488   },
7489   {
7490     /* VEX_W_0F42_P_2_LEN_1 */
7491     { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
7492     { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
7493   },
7494   {
7495     /* VEX_W_0F44_P_0_LEN_0 */
7496     { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
7497     { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
7498   },
7499   {
7500     /* VEX_W_0F44_P_2_LEN_0 */
7501     { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
7502     { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
7503   },
7504   {
7505     /* VEX_W_0F45_P_0_LEN_1 */
7506     { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
7507     { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
7508   },
7509   {
7510     /* VEX_W_0F45_P_2_LEN_1 */
7511     { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
7512     { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
7513   },
7514   {
7515     /* VEX_W_0F46_P_0_LEN_1 */
7516     { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
7517     { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
7518   },
7519   {
7520     /* VEX_W_0F46_P_2_LEN_1 */
7521     { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
7522     { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
7523   },
7524   {
7525     /* VEX_W_0F47_P_0_LEN_1 */
7526     { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
7527     { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
7528   },
7529   {
7530     /* VEX_W_0F47_P_2_LEN_1 */
7531     { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
7532     { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
7533   },
7534   {
7535     /* VEX_W_0F4A_P_0_LEN_1 */
7536     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
7537     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
7538   },
7539   {
7540     /* VEX_W_0F4A_P_2_LEN_1 */
7541     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
7542     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
7543   },
7544   {
7545     /* VEX_W_0F4B_P_0_LEN_1 */
7546     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
7547     { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
7548   },
7549   {
7550     /* VEX_W_0F4B_P_2_LEN_1 */
7551     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
7552   },
7553   {
7554     /* VEX_W_0F90_P_0_LEN_0 */
7555     { "kmovw",          { MaskG, MaskE }, 0 },
7556     { "kmovq",          { MaskG, MaskE }, 0 },
7557   },
7558   {
7559     /* VEX_W_0F90_P_2_LEN_0 */
7560     { "kmovb",          { MaskG, MaskBDE }, 0 },
7561     { "kmovd",          { MaskG, MaskBDE }, 0 },
7562   },
7563   {
7564     /* VEX_W_0F91_P_0_LEN_0 */
7565     { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
7566     { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
7567   },
7568   {
7569     /* VEX_W_0F91_P_2_LEN_0 */
7570     { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
7571     { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
7572   },
7573   {
7574     /* VEX_W_0F92_P_0_LEN_0 */
7575     { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
7576   },
7577   {
7578     /* VEX_W_0F92_P_2_LEN_0 */
7579     { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
7580   },
7581   {
7582     /* VEX_W_0F93_P_0_LEN_0 */
7583     { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
7584   },
7585   {
7586     /* VEX_W_0F93_P_2_LEN_0 */
7587     { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
7588   },
7589   {
7590     /* VEX_W_0F98_P_0_LEN_0 */
7591     { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
7592     { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
7593   },
7594   {
7595     /* VEX_W_0F98_P_2_LEN_0 */
7596     { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
7597     { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
7598   },
7599   {
7600     /* VEX_W_0F99_P_0_LEN_0 */
7601     { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
7602     { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
7603   },
7604   {
7605     /* VEX_W_0F99_P_2_LEN_0 */
7606     { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
7607     { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
7608   },
7609   {
7610     /* VEX_W_0F380C  */
7611     { "vpermilps",      { XM, Vex, EXx }, PREFIX_DATA },
7612   },
7613   {
7614     /* VEX_W_0F380D  */
7615     { "vpermilpd",      { XM, Vex, EXx }, PREFIX_DATA },
7616   },
7617   {
7618     /* VEX_W_0F380E  */
7619     { "vtestps",        { XM, EXx }, PREFIX_DATA },
7620   },
7621   {
7622     /* VEX_W_0F380F  */
7623     { "vtestpd",        { XM, EXx }, PREFIX_DATA },
7624   },
7625   {
7626     /* VEX_W_0F3813 */
7627     { "vcvtph2ps", { XM, EXxmmq }, PREFIX_DATA },
7628   },
7629   {
7630     /* VEX_W_0F3816_L_1  */
7631     { "vpermps",        { XM, Vex, EXx }, PREFIX_DATA },
7632   },
7633   {
7634     /* VEX_W_0F3818 */
7635     { "vbroadcastss",   { XM, EXxmm_md }, PREFIX_DATA },
7636   },
7637   {
7638     /* VEX_W_0F3819_L_1 */
7639     { "vbroadcastsd",   { XM, EXxmm_mq }, PREFIX_DATA },
7640   },
7641   {
7642     /* VEX_W_0F381A_M_0_L_1 */
7643     { "vbroadcastf128", { XM, Mxmm }, PREFIX_DATA },
7644   },
7645   {
7646     /* VEX_W_0F382C_M_0 */
7647     { "vmaskmovps",     { XM, Vex, Mx }, PREFIX_DATA },
7648   },
7649   {
7650     /* VEX_W_0F382D_M_0 */
7651     { "vmaskmovpd",     { XM, Vex, Mx }, PREFIX_DATA },
7652   },
7653   {
7654     /* VEX_W_0F382E_M_0 */
7655     { "vmaskmovps",     { Mx, Vex, XM }, PREFIX_DATA },
7656   },
7657   {
7658     /* VEX_W_0F382F_M_0 */
7659     { "vmaskmovpd",     { Mx, Vex, XM }, PREFIX_DATA },
7660   },
7661   {
7662     /* VEX_W_0F3836  */
7663     { "vpermd",         { XM, Vex, EXx }, PREFIX_DATA },
7664   },
7665   {
7666     /* VEX_W_0F3846 */
7667     { "vpsravd",        { XM, Vex, EXx }, PREFIX_DATA },
7668   },
7669   {
7670     /* VEX_W_0F3849_X86_64_P_0 */
7671     { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_0_W_0) },
7672   },
7673   {
7674     /* VEX_W_0F3849_X86_64_P_2 */
7675     { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_2_W_0) },
7676   },
7677   {
7678     /* VEX_W_0F3849_X86_64_P_3 */
7679     { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_3_W_0) },
7680   },
7681   {
7682     /* VEX_W_0F384B_X86_64_P_1 */
7683     { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_1_W_0) },
7684   },
7685   {
7686     /* VEX_W_0F384B_X86_64_P_2 */
7687     { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_2_W_0) },
7688   },
7689   {
7690     /* VEX_W_0F384B_X86_64_P_3 */
7691     { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_3_W_0) },
7692   },
7693   {
7694     /* VEX_W_0F3858 */
7695     { "vpbroadcastd", { XM, EXxmm_md }, PREFIX_DATA },
7696   },
7697   {
7698     /* VEX_W_0F3859 */
7699     { "vpbroadcastq",   { XM, EXxmm_mq }, PREFIX_DATA },
7700   },
7701   {
7702     /* VEX_W_0F385A_M_0_L_0 */
7703     { "vbroadcasti128", { XM, Mxmm }, PREFIX_DATA },
7704   },
7705   {
7706     /* VEX_W_0F385C_X86_64_P_1 */
7707     { MOD_TABLE (MOD_VEX_0F385C_X86_64_P_1_W_0) },
7708   },
7709   {
7710     /* VEX_W_0F385E_X86_64_P_0 */
7711     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_0_W_0) },
7712   },
7713   {
7714     /* VEX_W_0F385E_X86_64_P_1 */
7715     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_1_W_0) },
7716   },
7717   {
7718     /* VEX_W_0F385E_X86_64_P_2 */
7719     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_2_W_0) },
7720   },
7721   {
7722     /* VEX_W_0F385E_X86_64_P_3 */
7723     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_3_W_0) },
7724   },
7725   {
7726     /* VEX_W_0F3878 */
7727     { "vpbroadcastb",   { XM, EXxmm_mb }, PREFIX_DATA },
7728   },
7729   {
7730     /* VEX_W_0F3879 */
7731     { "vpbroadcastw",   { XM, EXxmm_mw }, PREFIX_DATA },
7732   },
7733   {
7734     /* VEX_W_0F38CF */
7735     { "vgf2p8mulb", { XM, Vex, EXx }, PREFIX_DATA },
7736   },
7737   {
7738     /* VEX_W_0F3A00_L_1 */
7739     { Bad_Opcode },
7740     { "vpermq",         { XM, EXx, Ib }, PREFIX_DATA },
7741   },
7742   {
7743     /* VEX_W_0F3A01_L_1 */
7744     { Bad_Opcode },
7745     { "vpermpd",        { XM, EXx, Ib }, PREFIX_DATA },
7746   },
7747   {
7748     /* VEX_W_0F3A02 */
7749     { "vpblendd",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
7750   },
7751   {
7752     /* VEX_W_0F3A04 */
7753     { "vpermilps",      { XM, EXx, Ib }, PREFIX_DATA },
7754   },
7755   {
7756     /* VEX_W_0F3A05 */
7757     { "vpermilpd",      { XM, EXx, Ib }, PREFIX_DATA },
7758   },
7759   {
7760     /* VEX_W_0F3A06_L_1 */
7761     { "vperm2f128",     { XM, Vex, EXx, Ib }, PREFIX_DATA },
7762   },
7763   {
7764     /* VEX_W_0F3A18_L_1 */
7765     { "vinsertf128",    { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7766   },
7767   {
7768     /* VEX_W_0F3A19_L_1 */
7769     { "vextractf128",   { EXxmm, XM, Ib }, PREFIX_DATA },
7770   },
7771   {
7772     /* VEX_W_0F3A1D */
7773     { "vcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, PREFIX_DATA },
7774   },
7775   {
7776     /* VEX_W_0F3A38_L_1 */
7777     { "vinserti128",    { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7778   },
7779   {
7780     /* VEX_W_0F3A39_L_1 */
7781     { "vextracti128",   { EXxmm, XM, Ib }, PREFIX_DATA },
7782   },
7783   {
7784     /* VEX_W_0F3A46_L_1 */
7785     { "vperm2i128",     { XM, Vex, EXx, Ib }, PREFIX_DATA },
7786   },
7787   {
7788     /* VEX_W_0F3A4A */
7789     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7790   },
7791   {
7792     /* VEX_W_0F3A4B */
7793     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7794   },
7795   {
7796     /* VEX_W_0F3A4C */
7797     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7798   },
7799   {
7800     /* VEX_W_0F3ACE */
7801     { Bad_Opcode },
7802     { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7803   },
7804   {
7805     /* VEX_W_0F3ACF */
7806     { Bad_Opcode },
7807     { "vgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, PREFIX_DATA },
7808   },
7809   /* VEX_W_0FXOP_08_85_L_0 */
7810   {
7811     { "vpmacssww",      { XM, Vex, EXx, XMVexI4 }, 0 },
7812   },
7813   /* VEX_W_0FXOP_08_86_L_0 */
7814   {
7815     { "vpmacsswd",      { XM, Vex, EXx, XMVexI4 }, 0 },
7816   },
7817   /* VEX_W_0FXOP_08_87_L_0 */
7818   {
7819     { "vpmacssdql",     { XM, Vex, EXx, XMVexI4 }, 0 },
7820   },
7821   /* VEX_W_0FXOP_08_8E_L_0 */
7822   {
7823     { "vpmacssdd",      { XM, Vex, EXx, XMVexI4 }, 0 },
7824   },
7825   /* VEX_W_0FXOP_08_8F_L_0 */
7826   {
7827     { "vpmacssdqh",     { XM, Vex, EXx, XMVexI4 }, 0 },
7828   },
7829   /* VEX_W_0FXOP_08_95_L_0 */
7830   {
7831     { "vpmacsww",       { XM, Vex, EXx, XMVexI4 }, 0 },
7832   },
7833   /* VEX_W_0FXOP_08_96_L_0 */
7834   {
7835     { "vpmacswd",       { XM, Vex, EXx, XMVexI4 }, 0 },
7836   },
7837   /* VEX_W_0FXOP_08_97_L_0 */
7838   {
7839     { "vpmacsdql",      { XM, Vex, EXx, XMVexI4 }, 0 },
7840   },
7841   /* VEX_W_0FXOP_08_9E_L_0 */
7842   {
7843     { "vpmacsdd",       { XM, Vex, EXx, XMVexI4 }, 0 },
7844   },
7845   /* VEX_W_0FXOP_08_9F_L_0 */
7846   {
7847     { "vpmacsdqh",      { XM, Vex, EXx, XMVexI4 }, 0 },
7848   },
7849   /* VEX_W_0FXOP_08_A6_L_0 */
7850   {
7851     { "vpmadcsswd",     { XM, Vex, EXx, XMVexI4 }, 0 },
7852   },
7853   /* VEX_W_0FXOP_08_B6_L_0 */
7854   {
7855     { "vpmadcswd",      { XM, Vex, EXx, XMVexI4 }, 0 },
7856   },
7857   /* VEX_W_0FXOP_08_C0_L_0 */
7858   {
7859     { "vprotb",         { XM, EXx, Ib }, 0 },
7860   },
7861   /* VEX_W_0FXOP_08_C1_L_0 */
7862   {
7863     { "vprotw",         { XM, EXx, Ib }, 0 },
7864   },
7865   /* VEX_W_0FXOP_08_C2_L_0 */
7866   {
7867     { "vprotd",         { XM, EXx, Ib }, 0 },
7868   },
7869   /* VEX_W_0FXOP_08_C3_L_0 */
7870   {
7871     { "vprotq",         { XM, EXx, Ib }, 0 },
7872   },
7873   /* VEX_W_0FXOP_08_CC_L_0 */
7874   {
7875      { "vpcomb",        { XM, Vex, EXx, VPCOM }, 0 },
7876   },
7877   /* VEX_W_0FXOP_08_CD_L_0 */
7878   {
7879      { "vpcomw",        { XM, Vex, EXx, VPCOM }, 0 },
7880   },
7881   /* VEX_W_0FXOP_08_CE_L_0 */
7882   {
7883      { "vpcomd",        { XM, Vex, EXx, VPCOM }, 0 },
7884   },
7885   /* VEX_W_0FXOP_08_CF_L_0 */
7886   {
7887      { "vpcomq",        { XM, Vex, EXx, VPCOM }, 0 },
7888   },
7889   /* VEX_W_0FXOP_08_EC_L_0 */
7890   {
7891      { "vpcomub",       { XM, Vex, EXx, VPCOM }, 0 },
7892   },
7893   /* VEX_W_0FXOP_08_ED_L_0 */
7894   {
7895      { "vpcomuw",       { XM, Vex, EXx, VPCOM }, 0 },
7896   },
7897   /* VEX_W_0FXOP_08_EE_L_0 */
7898   {
7899      { "vpcomud",       { XM, Vex, EXx, VPCOM }, 0 },
7900   },
7901   /* VEX_W_0FXOP_08_EF_L_0 */
7902   {
7903      { "vpcomuq",       { XM, Vex, EXx, VPCOM }, 0 },
7904   },
7905   /* VEX_W_0FXOP_09_80 */
7906   {
7907     { "vfrczps",        { XM, EXx }, 0 },
7908   },
7909   /* VEX_W_0FXOP_09_81 */
7910   {
7911     { "vfrczpd",        { XM, EXx }, 0 },
7912   },
7913   /* VEX_W_0FXOP_09_82 */
7914   {
7915     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_82_W_0) },
7916   },
7917   /* VEX_W_0FXOP_09_83 */
7918   {
7919     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_83_W_0) },
7920   },
7921   /* VEX_W_0FXOP_09_C1_L_0 */
7922   {
7923     { "vphaddbw",       { XM, EXxmm }, 0 },
7924   },
7925   /* VEX_W_0FXOP_09_C2_L_0 */
7926   {
7927     { "vphaddbd",       { XM, EXxmm }, 0 },
7928   },
7929   /* VEX_W_0FXOP_09_C3_L_0 */
7930   {
7931     { "vphaddbq",       { XM, EXxmm }, 0 },
7932   },
7933   /* VEX_W_0FXOP_09_C6_L_0 */
7934   {
7935     { "vphaddwd",       { XM, EXxmm }, 0 },
7936   },
7937   /* VEX_W_0FXOP_09_C7_L_0 */
7938   {
7939     { "vphaddwq",       { XM, EXxmm }, 0 },
7940   },
7941   /* VEX_W_0FXOP_09_CB_L_0 */
7942   {
7943     { "vphadddq",       { XM, EXxmm }, 0 },
7944   },
7945   /* VEX_W_0FXOP_09_D1_L_0 */
7946   {
7947     { "vphaddubw",      { XM, EXxmm }, 0 },
7948   },
7949   /* VEX_W_0FXOP_09_D2_L_0 */
7950   {
7951     { "vphaddubd",      { XM, EXxmm }, 0 },
7952   },
7953   /* VEX_W_0FXOP_09_D3_L_0 */
7954   {
7955     { "vphaddubq",      { XM, EXxmm }, 0 },
7956   },
7957   /* VEX_W_0FXOP_09_D6_L_0 */
7958   {
7959     { "vphadduwd",      { XM, EXxmm }, 0 },
7960   },
7961   /* VEX_W_0FXOP_09_D7_L_0 */
7962   {
7963     { "vphadduwq",      { XM, EXxmm }, 0 },
7964   },
7965   /* VEX_W_0FXOP_09_DB_L_0 */
7966   {
7967     { "vphaddudq",      { XM, EXxmm }, 0 },
7968   },
7969   /* VEX_W_0FXOP_09_E1_L_0 */
7970   {
7971     { "vphsubbw",       { XM, EXxmm }, 0 },
7972   },
7973   /* VEX_W_0FXOP_09_E2_L_0 */
7974   {
7975     { "vphsubwd",       { XM, EXxmm }, 0 },
7976   },
7977   /* VEX_W_0FXOP_09_E3_L_0 */
7978   {
7979     { "vphsubdq",       { XM, EXxmm }, 0 },
7980   },
7981
7982 #include "i386-dis-evex-w.h"
7983 };
7984
7985 static const struct dis386 mod_table[][2] = {
7986   {
7987     /* MOD_8D */
7988     { "leaS",           { Gv, M }, 0 },
7989   },
7990   {
7991     /* MOD_C6_REG_7 */
7992     { Bad_Opcode },
7993     { RM_TABLE (RM_C6_REG_7) },
7994   },
7995   {
7996     /* MOD_C7_REG_7 */
7997     { Bad_Opcode },
7998     { RM_TABLE (RM_C7_REG_7) },
7999   },
8000   {
8001     /* MOD_FF_REG_3 */
8002     { "{l|}call^", { indirEp }, 0 },
8003   },
8004   {
8005     /* MOD_FF_REG_5 */
8006     { "{l|}jmp^", { indirEp }, 0 },
8007   },
8008   {
8009     /* MOD_0F01_REG_0 */
8010     { X86_64_TABLE (X86_64_0F01_REG_0) },
8011     { RM_TABLE (RM_0F01_REG_0) },
8012   },
8013   {
8014     /* MOD_0F01_REG_1 */
8015     { X86_64_TABLE (X86_64_0F01_REG_1) },
8016     { RM_TABLE (RM_0F01_REG_1) },
8017   },
8018   {
8019     /* MOD_0F01_REG_2 */
8020     { X86_64_TABLE (X86_64_0F01_REG_2) },
8021     { RM_TABLE (RM_0F01_REG_2) },
8022   },
8023   {
8024     /* MOD_0F01_REG_3 */
8025     { X86_64_TABLE (X86_64_0F01_REG_3) },
8026     { RM_TABLE (RM_0F01_REG_3) },
8027   },
8028   {
8029     /* MOD_0F01_REG_5 */
8030     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) },
8031     { RM_TABLE (RM_0F01_REG_5_MOD_3) },
8032   },
8033   {
8034     /* MOD_0F01_REG_7 */
8035     { "invlpg",         { Mb }, 0 },
8036     { RM_TABLE (RM_0F01_REG_7_MOD_3) },
8037   },
8038   {
8039     /* MOD_0F12_PREFIX_0 */
8040     { "movlpX",         { XM, EXq }, 0 },
8041     { "movhlps",        { XM, EXq }, 0 },
8042   },
8043   {
8044     /* MOD_0F12_PREFIX_2 */
8045     { "movlpX", { XM, EXq }, 0 },
8046   },
8047   {
8048     /* MOD_0F13 */
8049     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
8050   },
8051   {
8052     /* MOD_0F16_PREFIX_0 */
8053     { "movhpX",         { XM, EXq }, 0 },
8054     { "movlhps",        { XM, EXq }, 0 },
8055   },
8056   {
8057     /* MOD_0F16_PREFIX_2 */
8058     { "movhpX", { XM, EXq }, 0 },
8059   },
8060   {
8061     /* MOD_0F17 */
8062     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
8063   },
8064   {
8065     /* MOD_0F18_REG_0 */
8066     { "prefetchnta",    { Mb }, 0 },
8067   },
8068   {
8069     /* MOD_0F18_REG_1 */
8070     { "prefetcht0",     { Mb }, 0 },
8071   },
8072   {
8073     /* MOD_0F18_REG_2 */
8074     { "prefetcht1",     { Mb }, 0 },
8075   },
8076   {
8077     /* MOD_0F18_REG_3 */
8078     { "prefetcht2",     { Mb }, 0 },
8079   },
8080   {
8081     /* MOD_0F18_REG_4 */
8082     { "nop/reserved",   { Mb }, 0 },
8083   },
8084   {
8085     /* MOD_0F18_REG_5 */
8086     { "nop/reserved",   { Mb }, 0 },
8087   },
8088   {
8089     /* MOD_0F18_REG_6 */
8090     { "nop/reserved",   { Mb }, 0 },
8091   },
8092   {
8093     /* MOD_0F18_REG_7 */
8094     { "nop/reserved",   { Mb }, 0 },
8095   },
8096   {
8097     /* MOD_0F1A_PREFIX_0 */
8098     { "bndldx",         { Gbnd, Mv_bnd }, 0 },
8099     { "nopQ",           { Ev }, 0 },
8100   },
8101   {
8102     /* MOD_0F1B_PREFIX_0 */
8103     { "bndstx",         { Mv_bnd, Gbnd }, 0 },
8104     { "nopQ",           { Ev }, 0 },
8105   },
8106   {
8107     /* MOD_0F1B_PREFIX_1 */
8108     { "bndmk",          { Gbnd, Mv_bnd }, 0 },
8109     { "nopQ",           { Ev }, 0 },
8110   },
8111   {
8112     /* MOD_0F1C_PREFIX_0 */
8113     { REG_TABLE (REG_0F1C_P_0_MOD_0) },
8114     { "nopQ",           { Ev }, 0 },
8115   },
8116   {
8117     /* MOD_0F1E_PREFIX_1 */
8118     { "nopQ",           { Ev }, 0 },
8119     { REG_TABLE (REG_0F1E_P_1_MOD_3) },
8120   },
8121   {
8122     /* MOD_0F2B_PREFIX_0 */
8123     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
8124   },
8125   {
8126     /* MOD_0F2B_PREFIX_1 */
8127     {"movntss",         { Md, XM }, PREFIX_OPCODE },
8128   },
8129   {
8130     /* MOD_0F2B_PREFIX_2 */
8131     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
8132   },
8133   {
8134     /* MOD_0F2B_PREFIX_3 */
8135     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
8136   },
8137   {
8138     /* MOD_0F50 */
8139     { Bad_Opcode },
8140     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
8141   },
8142   {
8143     /* MOD_0F71_REG_2 */
8144     { Bad_Opcode },
8145     { "psrlw",          { MS, Ib }, PREFIX_OPCODE },
8146   },
8147   {
8148     /* MOD_0F71_REG_4 */
8149     { Bad_Opcode },
8150     { "psraw",          { MS, Ib }, PREFIX_OPCODE },
8151   },
8152   {
8153     /* MOD_0F71_REG_6 */
8154     { Bad_Opcode },
8155     { "psllw",          { MS, Ib }, PREFIX_OPCODE },
8156   },
8157   {
8158     /* MOD_0F72_REG_2 */
8159     { Bad_Opcode },
8160     { "psrld",          { MS, Ib }, PREFIX_OPCODE },
8161   },
8162   {
8163     /* MOD_0F72_REG_4 */
8164     { Bad_Opcode },
8165     { "psrad",          { MS, Ib }, PREFIX_OPCODE },
8166   },
8167   {
8168     /* MOD_0F72_REG_6 */
8169     { Bad_Opcode },
8170     { "pslld",          { MS, Ib }, PREFIX_OPCODE },
8171   },
8172   {
8173     /* MOD_0F73_REG_2 */
8174     { Bad_Opcode },
8175     { "psrlq",          { MS, Ib }, PREFIX_OPCODE },
8176   },
8177   {
8178     /* MOD_0F73_REG_3 */
8179     { Bad_Opcode },
8180     { "psrldq",         { XS, Ib }, PREFIX_DATA },
8181   },
8182   {
8183     /* MOD_0F73_REG_6 */
8184     { Bad_Opcode },
8185     { "psllq",          { MS, Ib }, PREFIX_OPCODE },
8186   },
8187   {
8188     /* MOD_0F73_REG_7 */
8189     { Bad_Opcode },
8190     { "pslldq",         { XS, Ib }, PREFIX_DATA },
8191   },
8192   {
8193     /* MOD_0FAE_REG_0 */
8194     { "fxsave",         { FXSAVE }, 0 },
8195     { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) },
8196   },
8197   {
8198     /* MOD_0FAE_REG_1 */
8199     { "fxrstor",        { FXSAVE }, 0 },
8200     { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) },
8201   },
8202   {
8203     /* MOD_0FAE_REG_2 */
8204     { "ldmxcsr",        { Md }, 0 },
8205     { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) },
8206   },
8207   {
8208     /* MOD_0FAE_REG_3 */
8209     { "stmxcsr",        { Md }, 0 },
8210     { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) },
8211   },
8212   {
8213     /* MOD_0FAE_REG_4 */
8214     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) },
8215     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) },
8216   },
8217   {
8218     /* MOD_0FAE_REG_5 */
8219     { "xrstor",         { FXSAVE }, PREFIX_OPCODE },
8220     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) },
8221   },
8222   {
8223     /* MOD_0FAE_REG_6 */
8224     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) },
8225     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) },
8226   },
8227   {
8228     /* MOD_0FAE_REG_7 */
8229     { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) },
8230     { RM_TABLE (RM_0FAE_REG_7_MOD_3) },
8231   },
8232   {
8233     /* MOD_0FB2 */
8234     { "lssS",           { Gv, Mp }, 0 },
8235   },
8236   {
8237     /* MOD_0FB4 */
8238     { "lfsS",           { Gv, Mp }, 0 },
8239   },
8240   {
8241     /* MOD_0FB5 */
8242     { "lgsS",           { Gv, Mp }, 0 },
8243   },
8244   {
8245     /* MOD_0FC3 */
8246     { "movntiS", { Edq, Gdq }, PREFIX_OPCODE },
8247   },
8248   {
8249     /* MOD_0FC7_REG_3 */
8250     { "xrstors",        { FXSAVE }, 0 },
8251   },
8252   {
8253     /* MOD_0FC7_REG_4 */
8254     { "xsavec",         { FXSAVE }, 0 },
8255   },
8256   {
8257     /* MOD_0FC7_REG_5 */
8258     { "xsaves",         { FXSAVE }, 0 },
8259   },
8260   {
8261     /* MOD_0FC7_REG_6 */
8262     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) },
8263     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) }
8264   },
8265   {
8266     /* MOD_0FC7_REG_7 */
8267     { "vmptrst",        { Mq }, 0 },
8268     { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) }
8269   },
8270   {
8271     /* MOD_0FD7 */
8272     { Bad_Opcode },
8273     { "pmovmskb",       { Gdq, MS }, 0 },
8274   },
8275   {
8276     /* MOD_0FE7_PREFIX_2 */
8277     { "movntdq",        { Mx, XM }, 0 },
8278   },
8279   {
8280     /* MOD_0FF0_PREFIX_3 */
8281     { "lddqu",          { XM, M }, 0 },
8282   },
8283   {
8284     /* MOD_0F382A */
8285     { "movntdqa",       { XM, Mx }, PREFIX_DATA },
8286   },
8287   {
8288     /* MOD_0F38DC_PREFIX_1 */
8289     { "aesenc128kl",    { XM, M }, 0 },
8290     { "loadiwkey",      { XM, EXx }, 0 },
8291   },
8292   {
8293     /* MOD_0F38DD_PREFIX_1 */
8294     { "aesdec128kl",    { XM, M }, 0 },
8295   },
8296   {
8297     /* MOD_0F38DE_PREFIX_1 */
8298     { "aesenc256kl",    { XM, M }, 0 },
8299   },
8300   {
8301     /* MOD_0F38DF_PREFIX_1 */
8302     { "aesdec256kl",    { XM, M }, 0 },
8303   },
8304   {
8305     /* MOD_0F38F5 */
8306     { "wrussK",         { M, Gdq }, PREFIX_DATA },
8307   },
8308   {
8309     /* MOD_0F38F6_PREFIX_0 */
8310     { "wrssK",          { M, Gdq }, PREFIX_OPCODE },
8311   },
8312   {
8313     /* MOD_0F38F8_PREFIX_1 */
8314     { "enqcmds",        { Gva, M }, PREFIX_OPCODE },
8315   },
8316   {
8317     /* MOD_0F38F8_PREFIX_2 */
8318     { "movdir64b",      { Gva, M }, PREFIX_OPCODE },
8319   },
8320   {
8321     /* MOD_0F38F8_PREFIX_3 */
8322     { "enqcmd",         { Gva, M }, PREFIX_OPCODE },
8323   },
8324   {
8325     /* MOD_0F38F9 */
8326     { "movdiri",        { Edq, Gdq }, PREFIX_OPCODE },
8327   },
8328   {
8329     /* MOD_0F38FA_PREFIX_1 */
8330     { Bad_Opcode },
8331     { "encodekey128", { Gd, Ed }, 0 },
8332   },
8333   {
8334     /* MOD_0F38FB_PREFIX_1 */
8335     { Bad_Opcode },
8336     { "encodekey256", { Gd, Ed }, 0 },
8337   },
8338   {
8339     /* MOD_62_32BIT */
8340     { "bound{S|}",      { Gv, Ma }, 0 },
8341     { EVEX_TABLE (EVEX_0F) },
8342   },
8343   {
8344     /* MOD_C4_32BIT */
8345     { "lesS",           { Gv, Mp }, 0 },
8346     { VEX_C4_TABLE (VEX_0F) },
8347   },
8348   {
8349     /* MOD_C5_32BIT */
8350     { "ldsS",           { Gv, Mp }, 0 },
8351     { VEX_C5_TABLE (VEX_0F) },
8352   },
8353   {
8354     /* MOD_VEX_0F12_PREFIX_0 */
8355     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
8356     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
8357   },
8358   {
8359     /* MOD_VEX_0F12_PREFIX_2 */
8360     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0) },
8361   },
8362   {
8363     /* MOD_VEX_0F13 */
8364     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
8365   },
8366   {
8367     /* MOD_VEX_0F16_PREFIX_0 */
8368     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
8369     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
8370   },
8371   {
8372     /* MOD_VEX_0F16_PREFIX_2 */
8373     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0) },
8374   },
8375   {
8376     /* MOD_VEX_0F17 */
8377     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
8378   },
8379   {
8380     /* MOD_VEX_0F2B */
8381     { "vmovntpX",       { Mx, XM }, PREFIX_OPCODE },
8382   },
8383   {
8384     /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
8385     { Bad_Opcode },
8386     { "kandw",          { MaskG, MaskVex, MaskE }, 0 },
8387   },
8388   {
8389     /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
8390     { Bad_Opcode },
8391     { "kandq",          { MaskG, MaskVex, MaskE }, 0 },
8392   },
8393   {
8394     /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
8395     { Bad_Opcode },
8396     { "kandb",          { MaskG, MaskVex, MaskE }, 0 },
8397   },
8398   {
8399     /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
8400     { Bad_Opcode },
8401     { "kandd",          { MaskG, MaskVex, MaskE }, 0 },
8402   },
8403   {
8404     /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
8405     { Bad_Opcode },
8406     { "kandnw",         { MaskG, MaskVex, MaskE }, 0 },
8407   },
8408   {
8409     /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
8410     { Bad_Opcode },
8411     { "kandnq",         { MaskG, MaskVex, MaskE }, 0 },
8412   },
8413   {
8414     /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
8415     { Bad_Opcode },
8416     { "kandnb",         { MaskG, MaskVex, MaskE }, 0 },
8417   },
8418   {
8419     /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
8420     { Bad_Opcode },
8421     { "kandnd",         { MaskG, MaskVex, MaskE }, 0 },
8422   },
8423   {
8424     /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
8425     { Bad_Opcode },
8426     { "knotw",          { MaskG, MaskE }, 0 },
8427   },
8428   {
8429     /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
8430     { Bad_Opcode },
8431     { "knotq",          { MaskG, MaskE }, 0 },
8432   },
8433   {
8434     /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
8435     { Bad_Opcode },
8436     { "knotb",          { MaskG, MaskE }, 0 },
8437   },
8438   {
8439     /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
8440     { Bad_Opcode },
8441     { "knotd",          { MaskG, MaskE }, 0 },
8442   },
8443   {
8444     /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
8445     { Bad_Opcode },
8446     { "korw",       { MaskG, MaskVex, MaskE }, 0 },
8447   },
8448   {
8449     /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
8450     { Bad_Opcode },
8451     { "korq",       { MaskG, MaskVex, MaskE }, 0 },
8452   },
8453   {
8454     /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
8455     { Bad_Opcode },
8456     { "korb",       { MaskG, MaskVex, MaskE }, 0 },
8457   },
8458   {
8459     /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
8460     { Bad_Opcode },
8461     { "kord",       { MaskG, MaskVex, MaskE }, 0 },
8462   },
8463  {
8464     /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
8465     { Bad_Opcode },
8466     { "kxnorw",     { MaskG, MaskVex, MaskE }, 0 },
8467   },
8468   {
8469     /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
8470     { Bad_Opcode },
8471     { "kxnorq",     { MaskG, MaskVex, MaskE }, 0 },
8472   },
8473   {
8474     /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
8475     { Bad_Opcode },
8476     { "kxnorb",     { MaskG, MaskVex, MaskE }, 0 },
8477   },
8478   {
8479     /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
8480     { Bad_Opcode },
8481     { "kxnord",     { MaskG, MaskVex, MaskE }, 0 },
8482   },
8483   {
8484     /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
8485     { Bad_Opcode },
8486     { "kxorw",      { MaskG, MaskVex, MaskE }, 0 },
8487   },
8488   {
8489     /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
8490     { Bad_Opcode },
8491     { "kxorq",      { MaskG, MaskVex, MaskE }, 0 },
8492   },
8493   {
8494     /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
8495     { Bad_Opcode },
8496     { "kxorb",      { MaskG, MaskVex, MaskE }, 0 },
8497   },
8498   {
8499     /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
8500     { Bad_Opcode },
8501     { "kxord",      { MaskG, MaskVex, MaskE }, 0 },
8502   },
8503   {
8504     /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
8505     { Bad_Opcode },
8506     { "kaddw",          { MaskG, MaskVex, MaskE }, 0 },
8507   },
8508   {
8509     /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
8510     { Bad_Opcode },
8511     { "kaddq",          { MaskG, MaskVex, MaskE }, 0 },
8512   },
8513   {
8514     /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
8515     { Bad_Opcode },
8516     { "kaddb",          { MaskG, MaskVex, MaskE }, 0 },
8517   },
8518   {
8519     /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
8520     { Bad_Opcode },
8521     { "kaddd",          { MaskG, MaskVex, MaskE }, 0 },
8522   },
8523   {
8524     /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
8525     { Bad_Opcode },
8526     { "kunpckwd",   { MaskG, MaskVex, MaskE }, 0 },
8527   },
8528   {
8529     /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
8530     { Bad_Opcode },
8531     { "kunpckdq",   { MaskG, MaskVex, MaskE }, 0 },
8532   },
8533   {
8534     /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
8535     { Bad_Opcode },
8536     { "kunpckbw",   { MaskG, MaskVex, MaskE }, 0 },
8537   },
8538   {
8539     /* MOD_VEX_0F50 */
8540     { Bad_Opcode },
8541     { "vmovmskpX",      { Gdq, XS }, PREFIX_OPCODE },
8542   },
8543   {
8544     /* MOD_VEX_0F71_REG_2 */
8545     { Bad_Opcode },
8546     { "vpsrlw",         { Vex, XS, Ib }, PREFIX_DATA },
8547   },
8548   {
8549     /* MOD_VEX_0F71_REG_4 */
8550     { Bad_Opcode },
8551     { "vpsraw",         { Vex, XS, Ib }, PREFIX_DATA },
8552   },
8553   {
8554     /* MOD_VEX_0F71_REG_6 */
8555     { Bad_Opcode },
8556     { "vpsllw",         { Vex, XS, Ib }, PREFIX_DATA },
8557   },
8558   {
8559     /* MOD_VEX_0F72_REG_2 */
8560     { Bad_Opcode },
8561     { "vpsrld",         { Vex, XS, Ib }, PREFIX_DATA },
8562   },
8563   {
8564     /* MOD_VEX_0F72_REG_4 */
8565     { Bad_Opcode },
8566     { "vpsrad",         { Vex, XS, Ib }, PREFIX_DATA },
8567   },
8568   {
8569     /* MOD_VEX_0F72_REG_6 */
8570     { Bad_Opcode },
8571     { "vpslld",         { Vex, XS, Ib }, PREFIX_DATA },
8572   },
8573   {
8574     /* MOD_VEX_0F73_REG_2 */
8575     { Bad_Opcode },
8576     { "vpsrlq",         { Vex, XS, Ib }, PREFIX_DATA },
8577   },
8578   {
8579     /* MOD_VEX_0F73_REG_3 */
8580     { Bad_Opcode },
8581     { "vpsrldq",        { Vex, XS, Ib }, PREFIX_DATA },
8582   },
8583   {
8584     /* MOD_VEX_0F73_REG_6 */
8585     { Bad_Opcode },
8586     { "vpsllq",         { Vex, XS, Ib }, PREFIX_DATA },
8587   },
8588   {
8589     /* MOD_VEX_0F73_REG_7 */
8590     { Bad_Opcode },
8591     { "vpslldq",        { Vex, XS, Ib }, PREFIX_DATA },
8592   },
8593   {
8594     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
8595     { "kmovw",          { Ew, MaskG }, 0 },
8596     { Bad_Opcode },
8597   },
8598   {
8599     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
8600     { "kmovq",          { Eq, MaskG }, 0 },
8601     { Bad_Opcode },
8602   },
8603   {
8604     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
8605     { "kmovb",          { Eb, MaskG }, 0 },
8606     { Bad_Opcode },
8607   },
8608   {
8609     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
8610     { "kmovd",          { Ed, MaskG }, 0 },
8611     { Bad_Opcode },
8612   },
8613   {
8614     /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
8615     { Bad_Opcode },
8616     { "kmovw",          { MaskG, Edq }, 0 },
8617   },
8618   {
8619     /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
8620     { Bad_Opcode },
8621     { "kmovb",          { MaskG, Edq }, 0 },
8622   },
8623   {
8624     /* MOD_VEX_0F92_P_3_LEN_0 */
8625     { Bad_Opcode },
8626     { "kmovK",          { MaskG, Edq }, 0 },
8627   },
8628   {
8629     /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
8630     { Bad_Opcode },
8631     { "kmovw",          { Gdq, MaskE }, 0 },
8632   },
8633   {
8634     /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
8635     { Bad_Opcode },
8636     { "kmovb",          { Gdq, MaskE }, 0 },
8637   },
8638   {
8639     /* MOD_VEX_0F93_P_3_LEN_0 */
8640     { Bad_Opcode },
8641     { "kmovK",          { Gdq, MaskE }, 0 },
8642   },
8643   {
8644     /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
8645     { Bad_Opcode },
8646     { "kortestw", { MaskG, MaskE }, 0 },
8647   },
8648   {
8649     /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
8650     { Bad_Opcode },
8651     { "kortestq", { MaskG, MaskE }, 0 },
8652   },
8653   {
8654     /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
8655     { Bad_Opcode },
8656     { "kortestb", { MaskG, MaskE }, 0 },
8657   },
8658   {
8659     /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
8660     { Bad_Opcode },
8661     { "kortestd", { MaskG, MaskE }, 0 },
8662   },
8663   {
8664     /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
8665     { Bad_Opcode },
8666     { "ktestw", { MaskG, MaskE }, 0 },
8667   },
8668   {
8669     /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
8670     { Bad_Opcode },
8671     { "ktestq", { MaskG, MaskE }, 0 },
8672   },
8673   {
8674     /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
8675     { Bad_Opcode },
8676     { "ktestb", { MaskG, MaskE }, 0 },
8677   },
8678   {
8679     /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
8680     { Bad_Opcode },
8681     { "ktestd", { MaskG, MaskE }, 0 },
8682   },
8683   {
8684     /* MOD_VEX_0FAE_REG_2 */
8685     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
8686   },
8687   {
8688     /* MOD_VEX_0FAE_REG_3 */
8689     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
8690   },
8691   {
8692     /* MOD_VEX_0FD7 */
8693     { Bad_Opcode },
8694     { "vpmovmskb",      { Gdq, XS }, PREFIX_DATA },
8695   },
8696   {
8697     /* MOD_VEX_0FE7 */
8698     { "vmovntdq",       { Mx, XM }, PREFIX_DATA },
8699   },
8700   {
8701     /* MOD_VEX_0FF0_PREFIX_3 */
8702     { "vlddqu",         { XM, M }, 0 },
8703   },
8704   {
8705     /* MOD_VEX_0F381A */
8706     { VEX_LEN_TABLE (VEX_LEN_0F381A_M_0) },
8707   },
8708   {
8709     /* MOD_VEX_0F382A */
8710     { "vmovntdqa",      { XM, Mx }, PREFIX_DATA },
8711   },
8712   {
8713     /* MOD_VEX_0F382C */
8714     { VEX_W_TABLE (VEX_W_0F382C_M_0) },
8715   },
8716   {
8717     /* MOD_VEX_0F382D */
8718     { VEX_W_TABLE (VEX_W_0F382D_M_0) },
8719   },
8720   {
8721     /* MOD_VEX_0F382E */
8722     { VEX_W_TABLE (VEX_W_0F382E_M_0) },
8723   },
8724   {
8725     /* MOD_VEX_0F382F */
8726     { VEX_W_TABLE (VEX_W_0F382F_M_0) },
8727   },
8728   {
8729     /* MOD_VEX_0F3849_X86_64_P_0_W_0 */
8730     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0) },
8731     { REG_TABLE (REG_VEX_0F3849_X86_64_P_0_W_0_M_1) },
8732   },
8733   {
8734     /* MOD_VEX_0F3849_X86_64_P_2_W_0 */
8735     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0) },
8736   },
8737   {
8738     /* MOD_VEX_0F3849_X86_64_P_3_W_0 */
8739     { Bad_Opcode },
8740     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0) },
8741   },
8742   {
8743     /* MOD_VEX_0F384B_X86_64_P_1_W_0 */
8744     { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0) },
8745   },
8746   {
8747     /* MOD_VEX_0F384B_X86_64_P_2_W_0 */
8748     { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0) },
8749   },
8750   {
8751     /* MOD_VEX_0F384B_X86_64_P_3_W_0 */
8752     { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0) },
8753   },
8754   {
8755     /* MOD_VEX_0F385A */
8756     { VEX_LEN_TABLE (VEX_LEN_0F385A_M_0) },
8757   },
8758   {
8759     /* MOD_VEX_0F385C_X86_64_P_1_W_0 */
8760     { Bad_Opcode },
8761     { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0) },
8762   },
8763   {
8764     /* MOD_VEX_0F385E_X86_64_P_0_W_0 */
8765     { Bad_Opcode },
8766     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0) },
8767   },
8768   {
8769     /* MOD_VEX_0F385E_X86_64_P_1_W_0 */
8770     { Bad_Opcode },
8771     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0) },
8772   },
8773   {
8774     /* MOD_VEX_0F385E_X86_64_P_2_W_0 */
8775     { Bad_Opcode },
8776     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0) },
8777   },
8778   {
8779     /* MOD_VEX_0F385E_X86_64_P_3_W_0 */
8780     { Bad_Opcode },
8781     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0) },
8782   },
8783   {
8784     /* MOD_VEX_0F388C */
8785     { "vpmaskmov%DQ",   { XM, Vex, Mx }, PREFIX_DATA },
8786   },
8787   {
8788     /* MOD_VEX_0F388E */
8789     { "vpmaskmov%DQ",   { Mx, Vex, XM }, PREFIX_DATA },
8790   },
8791   {
8792     /* MOD_VEX_0F3A30_L_0 */
8793     { Bad_Opcode },
8794     { "kshiftr%BW",     { MaskG, MaskE, Ib }, PREFIX_DATA },
8795   },
8796   {
8797     /* MOD_VEX_0F3A31_L_0 */
8798     { Bad_Opcode },
8799     { "kshiftr%DQ",     { MaskG, MaskE, Ib }, PREFIX_DATA },
8800   },
8801   {
8802     /* MOD_VEX_0F3A32_L_0 */
8803     { Bad_Opcode },
8804     { "kshiftl%BW",     { MaskG, MaskE, Ib }, PREFIX_DATA },
8805   },
8806   {
8807     /* MOD_VEX_0F3A33_L_0 */
8808     { Bad_Opcode },
8809     { "kshiftl%DQ",     { MaskG, MaskE, Ib }, PREFIX_DATA },
8810   },
8811   {
8812     /* MOD_VEX_0FXOP_09_12 */
8813     { Bad_Opcode },
8814     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_12_M_1) },
8815   },
8816
8817 #include "i386-dis-evex-mod.h"
8818 };
8819
8820 static const struct dis386 rm_table[][8] = {
8821   {
8822     /* RM_C6_REG_7 */
8823     { "xabort",         { Skip_MODRM, Ib }, 0 },
8824   },
8825   {
8826     /* RM_C7_REG_7 */
8827     { "xbeginT",        { Skip_MODRM, Jdqw }, 0 },
8828   },
8829   {
8830     /* RM_0F01_REG_0 */
8831     { "enclv",          { Skip_MODRM }, 0 },
8832     { "vmcall",         { Skip_MODRM }, 0 },
8833     { "vmlaunch",       { Skip_MODRM }, 0 },
8834     { "vmresume",       { Skip_MODRM }, 0 },
8835     { "vmxoff",         { Skip_MODRM }, 0 },
8836     { "pconfig",        { Skip_MODRM }, 0 },
8837   },
8838   {
8839     /* RM_0F01_REG_1 */
8840     { "monitor",        { { OP_Monitor, 0 } }, 0 },
8841     { "mwait",          { { OP_Mwait, 0 } }, 0 },
8842     { "clac",           { Skip_MODRM }, 0 },
8843     { "stac",           { Skip_MODRM }, 0 },
8844     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_4) },
8845     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_5) },
8846     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_6) },
8847     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_7) },
8848   },
8849   {
8850     /* RM_0F01_REG_2 */
8851     { "xgetbv",         { Skip_MODRM }, 0 },
8852     { "xsetbv",         { Skip_MODRM }, 0 },
8853     { Bad_Opcode },
8854     { Bad_Opcode },
8855     { "vmfunc",         { Skip_MODRM }, 0 },
8856     { "xend",           { Skip_MODRM }, 0 },
8857     { "xtest",          { Skip_MODRM }, 0 },
8858     { "enclu",          { Skip_MODRM }, 0 },
8859   },
8860   {
8861     /* RM_0F01_REG_3 */
8862     { "vmrun",          { Skip_MODRM }, 0 },
8863     { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) },
8864     { "vmload",         { Skip_MODRM }, 0 },
8865     { "vmsave",         { Skip_MODRM }, 0 },
8866     { "stgi",           { Skip_MODRM }, 0 },
8867     { "clgi",           { Skip_MODRM }, 0 },
8868     { "skinit",         { Skip_MODRM }, 0 },
8869     { "invlpga",        { Skip_MODRM }, 0 },
8870   },
8871   {
8872     /* RM_0F01_REG_5_MOD_3 */
8873     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) },
8874     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) },
8875     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) },
8876     { Bad_Opcode },
8877     { Bad_Opcode },
8878     { Bad_Opcode },
8879     { "rdpkru",         { Skip_MODRM }, 0 },
8880     { "wrpkru",         { Skip_MODRM }, 0 },
8881   },
8882   {
8883     /* RM_0F01_REG_7_MOD_3 */
8884     { "swapgs",         { Skip_MODRM }, 0  },
8885     { "rdtscp",         { Skip_MODRM }, 0  },
8886     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) },
8887     { "mwaitx",         { { OP_Mwait, eBX_reg } }, PREFIX_OPCODE },
8888     { "clzero",         { Skip_MODRM }, 0  },
8889     { "rdpru",          { Skip_MODRM }, 0  },
8890   },
8891   {
8892     /* RM_0F1E_P_1_MOD_3_REG_7 */
8893     { "nopQ",           { Ev }, 0 },
8894     { "nopQ",           { Ev }, 0 },
8895     { "endbr64",        { Skip_MODRM },  PREFIX_OPCODE },
8896     { "endbr32",        { Skip_MODRM },  PREFIX_OPCODE },
8897     { "nopQ",           { Ev }, 0 },
8898     { "nopQ",           { Ev }, 0 },
8899     { "nopQ",           { Ev }, 0 },
8900     { "nopQ",           { Ev }, 0 },
8901   },
8902   {
8903     /* RM_0FAE_REG_6_MOD_3 */
8904     { "mfence",         { Skip_MODRM }, 0 },
8905   },
8906   {
8907     /* RM_0FAE_REG_7_MOD_3 */
8908     { "sfence",         { Skip_MODRM }, 0 },
8909
8910   },
8911   {
8912     /* RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0 */
8913     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0) },
8914   },
8915 };
8916
8917 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
8918
8919 /* We use the high bit to indicate different name for the same
8920    prefix.  */
8921 #define REP_PREFIX      (0xf3 | 0x100)
8922 #define XACQUIRE_PREFIX (0xf2 | 0x200)
8923 #define XRELEASE_PREFIX (0xf3 | 0x400)
8924 #define BND_PREFIX      (0xf2 | 0x400)
8925 #define NOTRACK_PREFIX  (0x3e | 0x100)
8926
8927 /* Remember if the current op is a jump instruction.  */
8928 static bfd_boolean op_is_jump = FALSE;
8929
8930 static int
8931 ckprefix (void)
8932 {
8933   int newrex, i, length;
8934   rex = 0;
8935   prefixes = 0;
8936   used_prefixes = 0;
8937   rex_used = 0;
8938   last_lock_prefix = -1;
8939   last_repz_prefix = -1;
8940   last_repnz_prefix = -1;
8941   last_data_prefix = -1;
8942   last_addr_prefix = -1;
8943   last_rex_prefix = -1;
8944   last_seg_prefix = -1;
8945   fwait_prefix = -1;
8946   active_seg_prefix = 0;
8947   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
8948     all_prefixes[i] = 0;
8949   i = 0;
8950   length = 0;
8951   /* The maximum instruction length is 15bytes.  */
8952   while (length < MAX_CODE_LENGTH - 1)
8953     {
8954       FETCH_DATA (the_info, codep + 1);
8955       newrex = 0;
8956       switch (*codep)
8957         {
8958         /* REX prefixes family.  */
8959         case 0x40:
8960         case 0x41:
8961         case 0x42:
8962         case 0x43:
8963         case 0x44:
8964         case 0x45:
8965         case 0x46:
8966         case 0x47:
8967         case 0x48:
8968         case 0x49:
8969         case 0x4a:
8970         case 0x4b:
8971         case 0x4c:
8972         case 0x4d:
8973         case 0x4e:
8974         case 0x4f:
8975           if (address_mode == mode_64bit)
8976             newrex = *codep;
8977           else
8978             return 1;
8979           last_rex_prefix = i;
8980           break;
8981         case 0xf3:
8982           prefixes |= PREFIX_REPZ;
8983           last_repz_prefix = i;
8984           break;
8985         case 0xf2:
8986           prefixes |= PREFIX_REPNZ;
8987           last_repnz_prefix = i;
8988           break;
8989         case 0xf0:
8990           prefixes |= PREFIX_LOCK;
8991           last_lock_prefix = i;
8992           break;
8993         case 0x2e:
8994           prefixes |= PREFIX_CS;
8995           last_seg_prefix = i;
8996           active_seg_prefix = PREFIX_CS;
8997           break;
8998         case 0x36:
8999           prefixes |= PREFIX_SS;
9000           last_seg_prefix = i;
9001           active_seg_prefix = PREFIX_SS;
9002           break;
9003         case 0x3e:
9004           prefixes |= PREFIX_DS;
9005           last_seg_prefix = i;
9006           active_seg_prefix = PREFIX_DS;
9007           break;
9008         case 0x26:
9009           prefixes |= PREFIX_ES;
9010           last_seg_prefix = i;
9011           active_seg_prefix = PREFIX_ES;
9012           break;
9013         case 0x64:
9014           prefixes |= PREFIX_FS;
9015           last_seg_prefix = i;
9016           active_seg_prefix = PREFIX_FS;
9017           break;
9018         case 0x65:
9019           prefixes |= PREFIX_GS;
9020           last_seg_prefix = i;
9021           active_seg_prefix = PREFIX_GS;
9022           break;
9023         case 0x66:
9024           prefixes |= PREFIX_DATA;
9025           last_data_prefix = i;
9026           break;
9027         case 0x67:
9028           prefixes |= PREFIX_ADDR;
9029           last_addr_prefix = i;
9030           break;
9031         case FWAIT_OPCODE:
9032           /* fwait is really an instruction.  If there are prefixes
9033              before the fwait, they belong to the fwait, *not* to the
9034              following instruction.  */
9035           fwait_prefix = i;
9036           if (prefixes || rex)
9037             {
9038               prefixes |= PREFIX_FWAIT;
9039               codep++;
9040               /* This ensures that the previous REX prefixes are noticed
9041                  as unused prefixes, as in the return case below.  */
9042               rex_used = rex;
9043               return 1;
9044             }
9045           prefixes = PREFIX_FWAIT;
9046           break;
9047         default:
9048           return 1;
9049         }
9050       /* Rex is ignored when followed by another prefix.  */
9051       if (rex)
9052         {
9053           rex_used = rex;
9054           return 1;
9055         }
9056       if (*codep != FWAIT_OPCODE)
9057         all_prefixes[i++] = *codep;
9058       rex = newrex;
9059       codep++;
9060       length++;
9061     }
9062   return 0;
9063 }
9064
9065 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
9066    prefix byte.  */
9067
9068 static const char *
9069 prefix_name (int pref, int sizeflag)
9070 {
9071   static const char *rexes [16] =
9072     {
9073       "rex",            /* 0x40 */
9074       "rex.B",          /* 0x41 */
9075       "rex.X",          /* 0x42 */
9076       "rex.XB",         /* 0x43 */
9077       "rex.R",          /* 0x44 */
9078       "rex.RB",         /* 0x45 */
9079       "rex.RX",         /* 0x46 */
9080       "rex.RXB",        /* 0x47 */
9081       "rex.W",          /* 0x48 */
9082       "rex.WB",         /* 0x49 */
9083       "rex.WX",         /* 0x4a */
9084       "rex.WXB",        /* 0x4b */
9085       "rex.WR",         /* 0x4c */
9086       "rex.WRB",        /* 0x4d */
9087       "rex.WRX",        /* 0x4e */
9088       "rex.WRXB",       /* 0x4f */
9089     };
9090
9091   switch (pref)
9092     {
9093     /* REX prefixes family.  */
9094     case 0x40:
9095     case 0x41:
9096     case 0x42:
9097     case 0x43:
9098     case 0x44:
9099     case 0x45:
9100     case 0x46:
9101     case 0x47:
9102     case 0x48:
9103     case 0x49:
9104     case 0x4a:
9105     case 0x4b:
9106     case 0x4c:
9107     case 0x4d:
9108     case 0x4e:
9109     case 0x4f:
9110       return rexes [pref - 0x40];
9111     case 0xf3:
9112       return "repz";
9113     case 0xf2:
9114       return "repnz";
9115     case 0xf0:
9116       return "lock";
9117     case 0x2e:
9118       return "cs";
9119     case 0x36:
9120       return "ss";
9121     case 0x3e:
9122       return "ds";
9123     case 0x26:
9124       return "es";
9125     case 0x64:
9126       return "fs";
9127     case 0x65:
9128       return "gs";
9129     case 0x66:
9130       return (sizeflag & DFLAG) ? "data16" : "data32";
9131     case 0x67:
9132       if (address_mode == mode_64bit)
9133         return (sizeflag & AFLAG) ? "addr32" : "addr64";
9134       else
9135         return (sizeflag & AFLAG) ? "addr16" : "addr32";
9136     case FWAIT_OPCODE:
9137       return "fwait";
9138     case REP_PREFIX:
9139       return "rep";
9140     case XACQUIRE_PREFIX:
9141       return "xacquire";
9142     case XRELEASE_PREFIX:
9143       return "xrelease";
9144     case BND_PREFIX:
9145       return "bnd";
9146     case NOTRACK_PREFIX:
9147       return "notrack";
9148     default:
9149       return NULL;
9150     }
9151 }
9152
9153 static char op_out[MAX_OPERANDS][100];
9154 static int op_ad, op_index[MAX_OPERANDS];
9155 static int two_source_ops;
9156 static bfd_vma op_address[MAX_OPERANDS];
9157 static bfd_vma op_riprel[MAX_OPERANDS];
9158 static bfd_vma start_pc;
9159
9160 /*
9161  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
9162  *   (see topic "Redundant prefixes" in the "Differences from 8086"
9163  *   section of the "Virtual 8086 Mode" chapter.)
9164  * 'pc' should be the address of this instruction, it will
9165  *   be used to print the target address if this is a relative jump or call
9166  * The function returns the length of this instruction in bytes.
9167  */
9168
9169 static char intel_syntax;
9170 static char intel_mnemonic = !SYSV386_COMPAT;
9171 static char open_char;
9172 static char close_char;
9173 static char separator_char;
9174 static char scale_char;
9175
9176 enum x86_64_isa
9177 {
9178   amd64 = 1,
9179   intel64
9180 };
9181
9182 static enum x86_64_isa isa64;
9183
9184 /* Here for backwards compatibility.  When gdb stops using
9185    print_insn_i386_att and print_insn_i386_intel these functions can
9186    disappear, and print_insn_i386 be merged into print_insn.  */
9187 int
9188 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
9189 {
9190   intel_syntax = 0;
9191
9192   return print_insn (pc, info);
9193 }
9194
9195 int
9196 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
9197 {
9198   intel_syntax = 1;
9199
9200   return print_insn (pc, info);
9201 }
9202
9203 int
9204 print_insn_i386 (bfd_vma pc, disassemble_info *info)
9205 {
9206   intel_syntax = -1;
9207
9208   return print_insn (pc, info);
9209 }
9210
9211 void
9212 print_i386_disassembler_options (FILE *stream)
9213 {
9214   fprintf (stream, _("\n\
9215 The following i386/x86-64 specific disassembler options are supported for use\n\
9216 with the -M switch (multiple options should be separated by commas):\n"));
9217
9218   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
9219   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
9220   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
9221   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
9222   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
9223   fprintf (stream, _("  att-mnemonic\n"
9224                      "              Display instruction in AT&T mnemonic\n"));
9225   fprintf (stream, _("  intel-mnemonic\n"
9226                      "              Display instruction in Intel mnemonic\n"));
9227   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
9228   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
9229   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
9230   fprintf (stream, _("  data32      Assume 32bit data size\n"));
9231   fprintf (stream, _("  data16      Assume 16bit data size\n"));
9232   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
9233   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
9234   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
9235 }
9236
9237 /* Bad opcode.  */
9238 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
9239
9240 /* Get a pointer to struct dis386 with a valid name.  */
9241
9242 static const struct dis386 *
9243 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
9244 {
9245   int vindex, vex_table_index;
9246
9247   if (dp->name != NULL)
9248     return dp;
9249
9250   switch (dp->op[0].bytemode)
9251     {
9252     case USE_REG_TABLE:
9253       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
9254       break;
9255
9256     case USE_MOD_TABLE:
9257       vindex = modrm.mod == 0x3 ? 1 : 0;
9258       dp = &mod_table[dp->op[1].bytemode][vindex];
9259       break;
9260
9261     case USE_RM_TABLE:
9262       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
9263       break;
9264
9265     case USE_PREFIX_TABLE:
9266       if (need_vex)
9267         {
9268           /* The prefix in VEX is implicit.  */
9269           switch (vex.prefix)
9270             {
9271             case 0:
9272               vindex = 0;
9273               break;
9274             case REPE_PREFIX_OPCODE:
9275               vindex = 1;
9276               break;
9277             case DATA_PREFIX_OPCODE:
9278               vindex = 2;
9279               break;
9280             case REPNE_PREFIX_OPCODE:
9281               vindex = 3;
9282               break;
9283             default:
9284               abort ();
9285               break;
9286             }
9287         }
9288       else
9289         {
9290           int last_prefix = -1;
9291           int prefix = 0;
9292           vindex = 0;
9293           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
9294              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
9295              last one wins.  */
9296           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
9297             {
9298               if (last_repz_prefix > last_repnz_prefix)
9299                 {
9300                   vindex = 1;
9301                   prefix = PREFIX_REPZ;
9302                   last_prefix = last_repz_prefix;
9303                 }
9304               else
9305                 {
9306                   vindex = 3;
9307                   prefix = PREFIX_REPNZ;
9308                   last_prefix = last_repnz_prefix;
9309                 }
9310
9311               /* Check if prefix should be ignored.  */
9312               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
9313                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
9314                    & prefix) != 0)
9315                 vindex = 0;
9316             }
9317
9318           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
9319             {
9320               vindex = 2;
9321               prefix = PREFIX_DATA;
9322               last_prefix = last_data_prefix;
9323             }
9324
9325           if (vindex != 0)
9326             {
9327               used_prefixes |= prefix;
9328               all_prefixes[last_prefix] = 0;
9329             }
9330         }
9331       dp = &prefix_table[dp->op[1].bytemode][vindex];
9332       break;
9333
9334     case USE_X86_64_TABLE:
9335       vindex = address_mode == mode_64bit ? 1 : 0;
9336       dp = &x86_64_table[dp->op[1].bytemode][vindex];
9337       break;
9338
9339     case USE_3BYTE_TABLE:
9340       FETCH_DATA (info, codep + 2);
9341       vindex = *codep++;
9342       dp = &three_byte_table[dp->op[1].bytemode][vindex];
9343       end_codep = codep;
9344       modrm.mod = (*codep >> 6) & 3;
9345       modrm.reg = (*codep >> 3) & 7;
9346       modrm.rm = *codep & 7;
9347       break;
9348
9349     case USE_VEX_LEN_TABLE:
9350       if (!need_vex)
9351         abort ();
9352
9353       switch (vex.length)
9354         {
9355         case 128:
9356           vindex = 0;
9357           break;
9358         case 256:
9359           vindex = 1;
9360           break;
9361         default:
9362           abort ();
9363           break;
9364         }
9365
9366       dp = &vex_len_table[dp->op[1].bytemode][vindex];
9367       break;
9368
9369     case USE_EVEX_LEN_TABLE:
9370       if (!vex.evex)
9371         abort ();
9372
9373       switch (vex.length)
9374         {
9375         case 128:
9376           vindex = 0;
9377           break;
9378         case 256:
9379           vindex = 1;
9380           break;
9381         case 512:
9382           vindex = 2;
9383           break;
9384         default:
9385           abort ();
9386           break;
9387         }
9388
9389       dp = &evex_len_table[dp->op[1].bytemode][vindex];
9390       break;
9391
9392     case USE_XOP_8F_TABLE:
9393       FETCH_DATA (info, codep + 3);
9394       rex = ~(*codep >> 5) & 0x7;
9395
9396       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
9397       switch ((*codep & 0x1f))
9398         {
9399         default:
9400           dp = &bad_opcode;
9401           return dp;
9402         case 0x8:
9403           vex_table_index = XOP_08;
9404           break;
9405         case 0x9:
9406           vex_table_index = XOP_09;
9407           break;
9408         case 0xa:
9409           vex_table_index = XOP_0A;
9410           break;
9411         }
9412       codep++;
9413       vex.w = *codep & 0x80;
9414       if (vex.w && address_mode == mode_64bit)
9415         rex |= REX_W;
9416
9417       vex.register_specifier = (~(*codep >> 3)) & 0xf;
9418       if (address_mode != mode_64bit)
9419         {
9420           /* In 16/32-bit mode REX_B is silently ignored.  */
9421           rex &= ~REX_B;
9422         }
9423
9424       vex.length = (*codep & 0x4) ? 256 : 128;
9425       switch ((*codep & 0x3))
9426         {
9427         case 0:
9428           break;
9429         case 1:
9430           vex.prefix = DATA_PREFIX_OPCODE;
9431           break;
9432         case 2:
9433           vex.prefix = REPE_PREFIX_OPCODE;
9434           break;
9435         case 3:
9436           vex.prefix = REPNE_PREFIX_OPCODE;
9437           break;
9438         }
9439       need_vex = 1;
9440       codep++;
9441       vindex = *codep++;
9442       dp = &xop_table[vex_table_index][vindex];
9443
9444       end_codep = codep;
9445       FETCH_DATA (info, codep + 1);
9446       modrm.mod = (*codep >> 6) & 3;
9447       modrm.reg = (*codep >> 3) & 7;
9448       modrm.rm = *codep & 7;
9449
9450       /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid
9451          having to decode the bits for every otherwise valid encoding.  */
9452       if (vex.prefix)
9453         return &bad_opcode;
9454       break;
9455
9456     case USE_VEX_C4_TABLE:
9457       /* VEX prefix.  */
9458       FETCH_DATA (info, codep + 3);
9459       rex = ~(*codep >> 5) & 0x7;
9460       switch ((*codep & 0x1f))
9461         {
9462         default:
9463           dp = &bad_opcode;
9464           return dp;
9465         case 0x1:
9466           vex_table_index = VEX_0F;
9467           break;
9468         case 0x2:
9469           vex_table_index = VEX_0F38;
9470           break;
9471         case 0x3:
9472           vex_table_index = VEX_0F3A;
9473           break;
9474         }
9475       codep++;
9476       vex.w = *codep & 0x80;
9477       if (address_mode == mode_64bit)
9478         {
9479           if (vex.w)
9480             rex |= REX_W;
9481         }
9482       else
9483         {
9484           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
9485              is ignored, other REX bits are 0 and the highest bit in
9486              VEX.vvvv is also ignored (but we mustn't clear it here).  */
9487           rex = 0;
9488         }
9489       vex.register_specifier = (~(*codep >> 3)) & 0xf;
9490       vex.length = (*codep & 0x4) ? 256 : 128;
9491       switch ((*codep & 0x3))
9492         {
9493         case 0:
9494           break;
9495         case 1:
9496           vex.prefix = DATA_PREFIX_OPCODE;
9497           break;
9498         case 2:
9499           vex.prefix = REPE_PREFIX_OPCODE;
9500           break;
9501         case 3:
9502           vex.prefix = REPNE_PREFIX_OPCODE;
9503           break;
9504         }
9505       need_vex = 1;
9506       codep++;
9507       vindex = *codep++;
9508       dp = &vex_table[vex_table_index][vindex];
9509       end_codep = codep;
9510       /* There is no MODRM byte for VEX0F 77.  */
9511       if (vex_table_index != VEX_0F || vindex != 0x77)
9512         {
9513           FETCH_DATA (info, codep + 1);
9514           modrm.mod = (*codep >> 6) & 3;
9515           modrm.reg = (*codep >> 3) & 7;
9516           modrm.rm = *codep & 7;
9517         }
9518       break;
9519
9520     case USE_VEX_C5_TABLE:
9521       /* VEX prefix.  */
9522       FETCH_DATA (info, codep + 2);
9523       rex = (*codep & 0x80) ? 0 : REX_R;
9524
9525       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
9526          VEX.vvvv is 1.  */
9527       vex.register_specifier = (~(*codep >> 3)) & 0xf;
9528       vex.length = (*codep & 0x4) ? 256 : 128;
9529       switch ((*codep & 0x3))
9530         {
9531         case 0:
9532           break;
9533         case 1:
9534           vex.prefix = DATA_PREFIX_OPCODE;
9535           break;
9536         case 2:
9537           vex.prefix = REPE_PREFIX_OPCODE;
9538           break;
9539         case 3:
9540           vex.prefix = REPNE_PREFIX_OPCODE;
9541           break;
9542         }
9543       need_vex = 1;
9544       codep++;
9545       vindex = *codep++;
9546       dp = &vex_table[dp->op[1].bytemode][vindex];
9547       end_codep = codep;
9548       /* There is no MODRM byte for VEX 77.  */
9549       if (vindex != 0x77)
9550         {
9551           FETCH_DATA (info, codep + 1);
9552           modrm.mod = (*codep >> 6) & 3;
9553           modrm.reg = (*codep >> 3) & 7;
9554           modrm.rm = *codep & 7;
9555         }
9556       break;
9557
9558     case USE_VEX_W_TABLE:
9559       if (!need_vex)
9560         abort ();
9561
9562       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
9563       break;
9564
9565     case USE_EVEX_TABLE:
9566       two_source_ops = 0;
9567       /* EVEX prefix.  */
9568       vex.evex = 1;
9569       FETCH_DATA (info, codep + 4);
9570       /* The first byte after 0x62.  */
9571       rex = ~(*codep >> 5) & 0x7;
9572       vex.r = *codep & 0x10;
9573       switch ((*codep & 0xf))
9574         {
9575         default:
9576           return &bad_opcode;
9577         case 0x1:
9578           vex_table_index = EVEX_0F;
9579           break;
9580         case 0x2:
9581           vex_table_index = EVEX_0F38;
9582           break;
9583         case 0x3:
9584           vex_table_index = EVEX_0F3A;
9585           break;
9586         }
9587
9588       /* The second byte after 0x62.  */
9589       codep++;
9590       vex.w = *codep & 0x80;
9591       if (vex.w && address_mode == mode_64bit)
9592         rex |= REX_W;
9593
9594       vex.register_specifier = (~(*codep >> 3)) & 0xf;
9595
9596       /* The U bit.  */
9597       if (!(*codep & 0x4))
9598         return &bad_opcode;
9599
9600       switch ((*codep & 0x3))
9601         {
9602         case 0:
9603           break;
9604         case 1:
9605           vex.prefix = DATA_PREFIX_OPCODE;
9606           break;
9607         case 2:
9608           vex.prefix = REPE_PREFIX_OPCODE;
9609           break;
9610         case 3:
9611           vex.prefix = REPNE_PREFIX_OPCODE;
9612           break;
9613         }
9614
9615       /* The third byte after 0x62.  */
9616       codep++;
9617
9618       /* Remember the static rounding bits.  */
9619       vex.ll = (*codep >> 5) & 3;
9620       vex.b = (*codep & 0x10) != 0;
9621
9622       vex.v = *codep & 0x8;
9623       vex.mask_register_specifier = *codep & 0x7;
9624       vex.zeroing = *codep & 0x80;
9625
9626       if (address_mode != mode_64bit)
9627         {
9628           /* In 16/32-bit mode silently ignore following bits.  */
9629           rex &= ~REX_B;
9630           vex.r = 1;
9631           vex.v = 1;
9632         }
9633
9634       need_vex = 1;
9635       codep++;
9636       vindex = *codep++;
9637       dp = &evex_table[vex_table_index][vindex];
9638       end_codep = codep;
9639       FETCH_DATA (info, codep + 1);
9640       modrm.mod = (*codep >> 6) & 3;
9641       modrm.reg = (*codep >> 3) & 7;
9642       modrm.rm = *codep & 7;
9643
9644       /* Set vector length.  */
9645       if (modrm.mod == 3 && vex.b)
9646         vex.length = 512;
9647       else
9648         {
9649           switch (vex.ll)
9650             {
9651             case 0x0:
9652               vex.length = 128;
9653               break;
9654             case 0x1:
9655               vex.length = 256;
9656               break;
9657             case 0x2:
9658               vex.length = 512;
9659               break;
9660             default:
9661               return &bad_opcode;
9662             }
9663         }
9664       break;
9665
9666     case 0:
9667       dp = &bad_opcode;
9668       break;
9669
9670     default:
9671       abort ();
9672     }
9673
9674   if (dp->name != NULL)
9675     return dp;
9676   else
9677     return get_valid_dis386 (dp, info);
9678 }
9679
9680 static void
9681 get_sib (disassemble_info *info, int sizeflag)
9682 {
9683   /* If modrm.mod == 3, operand must be register.  */
9684   if (need_modrm
9685       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
9686       && modrm.mod != 3
9687       && modrm.rm == 4)
9688     {
9689       FETCH_DATA (info, codep + 2);
9690       sib.index = (codep [1] >> 3) & 7;
9691       sib.scale = (codep [1] >> 6) & 3;
9692       sib.base = codep [1] & 7;
9693     }
9694 }
9695
9696 static int
9697 print_insn (bfd_vma pc, disassemble_info *info)
9698 {
9699   const struct dis386 *dp;
9700   int i;
9701   char *op_txt[MAX_OPERANDS];
9702   int needcomma;
9703   int sizeflag, orig_sizeflag;
9704   const char *p;
9705   struct dis_private priv;
9706   int prefix_length;
9707
9708   priv.orig_sizeflag = AFLAG | DFLAG;
9709   if ((info->mach & bfd_mach_i386_i386) != 0)
9710     address_mode = mode_32bit;
9711   else if (info->mach == bfd_mach_i386_i8086)
9712     {
9713       address_mode = mode_16bit;
9714       priv.orig_sizeflag = 0;
9715     }
9716   else
9717     address_mode = mode_64bit;
9718
9719   if (intel_syntax == (char) -1)
9720     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
9721
9722   for (p = info->disassembler_options; p != NULL; )
9723     {
9724       if (CONST_STRNEQ (p, "amd64"))
9725         isa64 = amd64;
9726       else if (CONST_STRNEQ (p, "intel64"))
9727         isa64 = intel64;
9728       else if (CONST_STRNEQ (p, "x86-64"))
9729         {
9730           address_mode = mode_64bit;
9731           priv.orig_sizeflag |= AFLAG | DFLAG;
9732         }
9733       else if (CONST_STRNEQ (p, "i386"))
9734         {
9735           address_mode = mode_32bit;
9736           priv.orig_sizeflag |= AFLAG | DFLAG;
9737         }
9738       else if (CONST_STRNEQ (p, "i8086"))
9739         {
9740           address_mode = mode_16bit;
9741           priv.orig_sizeflag &= ~(AFLAG | DFLAG);
9742         }
9743       else if (CONST_STRNEQ (p, "intel"))
9744         {
9745           intel_syntax = 1;
9746           if (CONST_STRNEQ (p + 5, "-mnemonic"))
9747             intel_mnemonic = 1;
9748         }
9749       else if (CONST_STRNEQ (p, "att"))
9750         {
9751           intel_syntax = 0;
9752           if (CONST_STRNEQ (p + 3, "-mnemonic"))
9753             intel_mnemonic = 0;
9754         }
9755       else if (CONST_STRNEQ (p, "addr"))
9756         {
9757           if (address_mode == mode_64bit)
9758             {
9759               if (p[4] == '3' && p[5] == '2')
9760                 priv.orig_sizeflag &= ~AFLAG;
9761               else if (p[4] == '6' && p[5] == '4')
9762                 priv.orig_sizeflag |= AFLAG;
9763             }
9764           else
9765             {
9766               if (p[4] == '1' && p[5] == '6')
9767                 priv.orig_sizeflag &= ~AFLAG;
9768               else if (p[4] == '3' && p[5] == '2')
9769                 priv.orig_sizeflag |= AFLAG;
9770             }
9771         }
9772       else if (CONST_STRNEQ (p, "data"))
9773         {
9774           if (p[4] == '1' && p[5] == '6')
9775             priv.orig_sizeflag &= ~DFLAG;
9776           else if (p[4] == '3' && p[5] == '2')
9777             priv.orig_sizeflag |= DFLAG;
9778         }
9779       else if (CONST_STRNEQ (p, "suffix"))
9780         priv.orig_sizeflag |= SUFFIX_ALWAYS;
9781
9782       p = strchr (p, ',');
9783       if (p != NULL)
9784         p++;
9785     }
9786
9787   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
9788     {
9789       (*info->fprintf_func) (info->stream,
9790                              _("64-bit address is disabled"));
9791       return -1;
9792     }
9793
9794   if (intel_syntax)
9795     {
9796       names64 = intel_names64;
9797       names32 = intel_names32;
9798       names16 = intel_names16;
9799       names8 = intel_names8;
9800       names8rex = intel_names8rex;
9801       names_seg = intel_names_seg;
9802       names_mm = intel_names_mm;
9803       names_bnd = intel_names_bnd;
9804       names_xmm = intel_names_xmm;
9805       names_ymm = intel_names_ymm;
9806       names_zmm = intel_names_zmm;
9807       names_tmm = intel_names_tmm;
9808       index64 = intel_index64;
9809       index32 = intel_index32;
9810       names_mask = intel_names_mask;
9811       index16 = intel_index16;
9812       open_char = '[';
9813       close_char = ']';
9814       separator_char = '+';
9815       scale_char = '*';
9816     }
9817   else
9818     {
9819       names64 = att_names64;
9820       names32 = att_names32;
9821       names16 = att_names16;
9822       names8 = att_names8;
9823       names8rex = att_names8rex;
9824       names_seg = att_names_seg;
9825       names_mm = att_names_mm;
9826       names_bnd = att_names_bnd;
9827       names_xmm = att_names_xmm;
9828       names_ymm = att_names_ymm;
9829       names_zmm = att_names_zmm;
9830       names_tmm = att_names_tmm;
9831       index64 = att_index64;
9832       index32 = att_index32;
9833       names_mask = att_names_mask;
9834       index16 = att_index16;
9835       open_char = '(';
9836       close_char =  ')';
9837       separator_char = ',';
9838       scale_char = ',';
9839     }
9840
9841   /* The output looks better if we put 7 bytes on a line, since that
9842      puts most long word instructions on a single line.  Use 8 bytes
9843      for Intel L1OM.  */
9844   if ((info->mach & bfd_mach_l1om) != 0)
9845     info->bytes_per_line = 8;
9846   else
9847     info->bytes_per_line = 7;
9848
9849   info->private_data = &priv;
9850   priv.max_fetched = priv.the_buffer;
9851   priv.insn_start = pc;
9852
9853   obuf[0] = 0;
9854   for (i = 0; i < MAX_OPERANDS; ++i)
9855     {
9856       op_out[i][0] = 0;
9857       op_index[i] = -1;
9858     }
9859
9860   the_info = info;
9861   start_pc = pc;
9862   start_codep = priv.the_buffer;
9863   codep = priv.the_buffer;
9864
9865   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
9866     {
9867       const char *name;
9868
9869       /* Getting here means we tried for data but didn't get it.  That
9870          means we have an incomplete instruction of some sort.  Just
9871          print the first byte as a prefix or a .byte pseudo-op.  */
9872       if (codep > priv.the_buffer)
9873         {
9874           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
9875           if (name != NULL)
9876             (*info->fprintf_func) (info->stream, "%s", name);
9877           else
9878             {
9879               /* Just print the first byte as a .byte instruction.  */
9880               (*info->fprintf_func) (info->stream, ".byte 0x%x",
9881                                      (unsigned int) priv.the_buffer[0]);
9882             }
9883
9884           return 1;
9885         }
9886
9887       return -1;
9888     }
9889
9890   obufp = obuf;
9891   sizeflag = priv.orig_sizeflag;
9892
9893   if (!ckprefix () || rex_used)
9894     {
9895       /* Too many prefixes or unused REX prefixes.  */
9896       for (i = 0;
9897            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
9898            i++)
9899         (*info->fprintf_func) (info->stream, "%s%s",
9900                                i == 0 ? "" : " ",
9901                                prefix_name (all_prefixes[i], sizeflag));
9902       return i;
9903     }
9904
9905   insn_codep = codep;
9906
9907   FETCH_DATA (info, codep + 1);
9908   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
9909
9910   if (((prefixes & PREFIX_FWAIT)
9911        && ((*codep < 0xd8) || (*codep > 0xdf))))
9912     {
9913       /* Handle prefixes before fwait.  */
9914       for (i = 0; i < fwait_prefix && all_prefixes[i];
9915            i++)
9916         (*info->fprintf_func) (info->stream, "%s ",
9917                                prefix_name (all_prefixes[i], sizeflag));
9918       (*info->fprintf_func) (info->stream, "fwait");
9919       return i + 1;
9920     }
9921
9922   if (*codep == 0x0f)
9923     {
9924       unsigned char threebyte;
9925
9926       codep++;
9927       FETCH_DATA (info, codep + 1);
9928       threebyte = *codep;
9929       dp = &dis386_twobyte[threebyte];
9930       need_modrm = twobyte_has_modrm[*codep];
9931       codep++;
9932     }
9933   else
9934     {
9935       dp = &dis386[*codep];
9936       need_modrm = onebyte_has_modrm[*codep];
9937       codep++;
9938     }
9939
9940   /* Save sizeflag for printing the extra prefixes later before updating
9941      it for mnemonic and operand processing.  The prefix names depend
9942      only on the address mode.  */
9943   orig_sizeflag = sizeflag;
9944   if (prefixes & PREFIX_ADDR)
9945     sizeflag ^= AFLAG;
9946   if ((prefixes & PREFIX_DATA))
9947     sizeflag ^= DFLAG;
9948
9949   end_codep = codep;
9950   if (need_modrm)
9951     {
9952       FETCH_DATA (info, codep + 1);
9953       modrm.mod = (*codep >> 6) & 3;
9954       modrm.reg = (*codep >> 3) & 7;
9955       modrm.rm = *codep & 7;
9956     }
9957
9958   need_vex = 0;
9959   memset (&vex, 0, sizeof (vex));
9960
9961   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
9962     {
9963       get_sib (info, sizeflag);
9964       dofloat (sizeflag);
9965     }
9966   else
9967     {
9968       dp = get_valid_dis386 (dp, info);
9969       if (dp != NULL && putop (dp->name, sizeflag) == 0)
9970         {
9971           get_sib (info, sizeflag);
9972           for (i = 0; i < MAX_OPERANDS; ++i)
9973             {
9974               obufp = op_out[i];
9975               op_ad = MAX_OPERANDS - 1 - i;
9976               if (dp->op[i].rtn)
9977                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
9978               /* For EVEX instruction after the last operand masking
9979                  should be printed.  */
9980               if (i == 0 && vex.evex)
9981                 {
9982                   /* Don't print {%k0}.  */
9983                   if (vex.mask_register_specifier)
9984                     {
9985                       oappend ("{");
9986                       oappend (names_mask[vex.mask_register_specifier]);
9987                       oappend ("}");
9988                     }
9989                   if (vex.zeroing)
9990                     oappend ("{z}");
9991                 }
9992             }
9993         }
9994     }
9995
9996   /* Clear instruction information.  */
9997   if (the_info)
9998     {
9999       the_info->insn_info_valid = 0;
10000       the_info->branch_delay_insns = 0;
10001       the_info->data_size = 0;
10002       the_info->insn_type = dis_noninsn;
10003       the_info->target = 0;
10004       the_info->target2 = 0;
10005     }
10006
10007   /* Reset jump operation indicator.  */
10008   op_is_jump = FALSE;
10009
10010   {
10011     int jump_detection = 0;
10012
10013     /* Extract flags.  */
10014     for (i = 0; i < MAX_OPERANDS; ++i)
10015       {
10016         if ((dp->op[i].rtn == OP_J)
10017             || (dp->op[i].rtn == OP_indirE))
10018           jump_detection |= 1;
10019         else if ((dp->op[i].rtn == BND_Fixup)
10020                  || (!dp->op[i].rtn && !dp->op[i].bytemode))
10021           jump_detection |= 2;
10022         else if ((dp->op[i].bytemode == cond_jump_mode)
10023                  || (dp->op[i].bytemode == loop_jcxz_mode))
10024           jump_detection |= 4;
10025       }
10026
10027     /* Determine if this is a jump or branch.  */
10028     if ((jump_detection & 0x3) == 0x3)
10029       {
10030         op_is_jump = TRUE;
10031         if (jump_detection & 0x4)
10032           the_info->insn_type = dis_condbranch;
10033         else
10034           the_info->insn_type =
10035             (dp->name && !strncmp(dp->name, "call", 4))
10036             ? dis_jsr : dis_branch;
10037       }
10038   }
10039
10040   /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
10041      are all 0s in inverted form.  */
10042   if (need_vex && vex.register_specifier != 0)
10043     {
10044       (*info->fprintf_func) (info->stream, "(bad)");
10045       return end_codep - priv.the_buffer;
10046     }
10047
10048   switch (dp->prefix_requirement)
10049     {
10050     case PREFIX_DATA:
10051       /* If only the data prefix is marked as mandatory, its absence renders
10052          the encoding invalid.  Most other PREFIX_OPCODE rules still apply.  */
10053       if (need_vex ? !vex.prefix : !(prefixes & PREFIX_DATA))
10054         {
10055           (*info->fprintf_func) (info->stream, "(bad)");
10056           return end_codep - priv.the_buffer;
10057         }
10058       used_prefixes |= PREFIX_DATA;
10059       /* Fall through.  */
10060     case PREFIX_OPCODE:
10061       /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
10062          unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
10063          used by putop and MMX/SSE operand and may be overridden by the
10064          PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
10065          separately.  */
10066       if (((need_vex
10067             ? vex.prefix == REPE_PREFIX_OPCODE
10068               || vex.prefix == REPNE_PREFIX_OPCODE
10069             : (prefixes
10070                & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
10071            && (used_prefixes
10072                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
10073           || (((need_vex
10074                 ? vex.prefix == DATA_PREFIX_OPCODE
10075                 : ((prefixes
10076                     & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
10077                    == PREFIX_DATA))
10078                && (used_prefixes & PREFIX_DATA) == 0))
10079           || (vex.evex && dp->prefix_requirement != PREFIX_DATA
10080               && !vex.w != !(used_prefixes & PREFIX_DATA)))
10081         {
10082           (*info->fprintf_func) (info->stream, "(bad)");
10083           return end_codep - priv.the_buffer;
10084         }
10085       break;
10086     }
10087
10088   /* Check if the REX prefix is used.  */
10089   if ((rex ^ rex_used) == 0 && !need_vex && last_rex_prefix >= 0)
10090     all_prefixes[last_rex_prefix] = 0;
10091
10092   /* Check if the SEG prefix is used.  */
10093   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
10094                    | PREFIX_FS | PREFIX_GS)) != 0
10095       && (used_prefixes & active_seg_prefix) != 0)
10096     all_prefixes[last_seg_prefix] = 0;
10097
10098   /* Check if the ADDR prefix is used.  */
10099   if ((prefixes & PREFIX_ADDR) != 0
10100       && (used_prefixes & PREFIX_ADDR) != 0)
10101     all_prefixes[last_addr_prefix] = 0;
10102
10103   /* Check if the DATA prefix is used.  */
10104   if ((prefixes & PREFIX_DATA) != 0
10105       && (used_prefixes & PREFIX_DATA) != 0
10106       && !need_vex)
10107     all_prefixes[last_data_prefix] = 0;
10108
10109   /* Print the extra prefixes.  */
10110   prefix_length = 0;
10111   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
10112     if (all_prefixes[i])
10113       {
10114         const char *name;
10115         name = prefix_name (all_prefixes[i], orig_sizeflag);
10116         if (name == NULL)
10117           abort ();
10118         prefix_length += strlen (name) + 1;
10119         (*info->fprintf_func) (info->stream, "%s ", name);
10120       }
10121
10122   /* Check maximum code length.  */
10123   if ((codep - start_codep) > MAX_CODE_LENGTH)
10124     {
10125       (*info->fprintf_func) (info->stream, "(bad)");
10126       return MAX_CODE_LENGTH;
10127     }
10128
10129   obufp = mnemonicendp;
10130   for (i = strlen (obuf) + prefix_length; i < 6; i++)
10131     oappend (" ");
10132   oappend (" ");
10133   (*info->fprintf_func) (info->stream, "%s", obuf);
10134
10135   /* The enter and bound instructions are printed with operands in the same
10136      order as the intel book; everything else is printed in reverse order.  */
10137   if (intel_syntax || two_source_ops)
10138     {
10139       bfd_vma riprel;
10140
10141       for (i = 0; i < MAX_OPERANDS; ++i)
10142         op_txt[i] = op_out[i];
10143
10144       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
10145           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
10146         {
10147           op_txt[2] = op_out[3];
10148           op_txt[3] = op_out[2];
10149         }
10150
10151       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
10152         {
10153           op_ad = op_index[i];
10154           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
10155           op_index[MAX_OPERANDS - 1 - i] = op_ad;
10156           riprel = op_riprel[i];
10157           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
10158           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
10159         }
10160     }
10161   else
10162     {
10163       for (i = 0; i < MAX_OPERANDS; ++i)
10164         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
10165     }
10166
10167   needcomma = 0;
10168   for (i = 0; i < MAX_OPERANDS; ++i)
10169     if (*op_txt[i])
10170       {
10171         if (needcomma)
10172           (*info->fprintf_func) (info->stream, ",");
10173         if (op_index[i] != -1 && !op_riprel[i])
10174           {
10175             bfd_vma target = (bfd_vma) op_address[op_index[i]];
10176
10177             if (the_info && op_is_jump)
10178               {
10179                 the_info->insn_info_valid = 1;
10180                 the_info->branch_delay_insns = 0;
10181                 the_info->data_size = 0;
10182                 the_info->target = target;
10183                 the_info->target2 = 0;
10184               }
10185             (*info->print_address_func) (target, info);
10186           }
10187         else
10188           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
10189         needcomma = 1;
10190       }
10191
10192   for (i = 0; i < MAX_OPERANDS; i++)
10193     if (op_index[i] != -1 && op_riprel[i])
10194       {
10195         (*info->fprintf_func) (info->stream, "        # ");
10196         (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
10197                                                 + op_address[op_index[i]]), info);
10198         break;
10199       }
10200   return codep - priv.the_buffer;
10201 }
10202
10203 static const char *float_mem[] = {
10204   /* d8 */
10205   "fadd{s|}",
10206   "fmul{s|}",
10207   "fcom{s|}",
10208   "fcomp{s|}",
10209   "fsub{s|}",
10210   "fsubr{s|}",
10211   "fdiv{s|}",
10212   "fdivr{s|}",
10213   /* d9 */
10214   "fld{s|}",
10215   "(bad)",
10216   "fst{s|}",
10217   "fstp{s|}",
10218   "fldenv{C|C}",
10219   "fldcw",
10220   "fNstenv{C|C}",
10221   "fNstcw",
10222   /* da */
10223   "fiadd{l|}",
10224   "fimul{l|}",
10225   "ficom{l|}",
10226   "ficomp{l|}",
10227   "fisub{l|}",
10228   "fisubr{l|}",
10229   "fidiv{l|}",
10230   "fidivr{l|}",
10231   /* db */
10232   "fild{l|}",
10233   "fisttp{l|}",
10234   "fist{l|}",
10235   "fistp{l|}",
10236   "(bad)",
10237   "fld{t|}",
10238   "(bad)",
10239   "fstp{t|}",
10240   /* dc */
10241   "fadd{l|}",
10242   "fmul{l|}",
10243   "fcom{l|}",
10244   "fcomp{l|}",
10245   "fsub{l|}",
10246   "fsubr{l|}",
10247   "fdiv{l|}",
10248   "fdivr{l|}",
10249   /* dd */
10250   "fld{l|}",
10251   "fisttp{ll|}",
10252   "fst{l||}",
10253   "fstp{l|}",
10254   "frstor{C|C}",
10255   "(bad)",
10256   "fNsave{C|C}",
10257   "fNstsw",
10258   /* de */
10259   "fiadd{s|}",
10260   "fimul{s|}",
10261   "ficom{s|}",
10262   "ficomp{s|}",
10263   "fisub{s|}",
10264   "fisubr{s|}",
10265   "fidiv{s|}",
10266   "fidivr{s|}",
10267   /* df */
10268   "fild{s|}",
10269   "fisttp{s|}",
10270   "fist{s|}",
10271   "fistp{s|}",
10272   "fbld",
10273   "fild{ll|}",
10274   "fbstp",
10275   "fistp{ll|}",
10276 };
10277
10278 static const unsigned char float_mem_mode[] = {
10279   /* d8 */
10280   d_mode,
10281   d_mode,
10282   d_mode,
10283   d_mode,
10284   d_mode,
10285   d_mode,
10286   d_mode,
10287   d_mode,
10288   /* d9 */
10289   d_mode,
10290   0,
10291   d_mode,
10292   d_mode,
10293   0,
10294   w_mode,
10295   0,
10296   w_mode,
10297   /* da */
10298   d_mode,
10299   d_mode,
10300   d_mode,
10301   d_mode,
10302   d_mode,
10303   d_mode,
10304   d_mode,
10305   d_mode,
10306   /* db */
10307   d_mode,
10308   d_mode,
10309   d_mode,
10310   d_mode,
10311   0,
10312   t_mode,
10313   0,
10314   t_mode,
10315   /* dc */
10316   q_mode,
10317   q_mode,
10318   q_mode,
10319   q_mode,
10320   q_mode,
10321   q_mode,
10322   q_mode,
10323   q_mode,
10324   /* dd */
10325   q_mode,
10326   q_mode,
10327   q_mode,
10328   q_mode,
10329   0,
10330   0,
10331   0,
10332   w_mode,
10333   /* de */
10334   w_mode,
10335   w_mode,
10336   w_mode,
10337   w_mode,
10338   w_mode,
10339   w_mode,
10340   w_mode,
10341   w_mode,
10342   /* df */
10343   w_mode,
10344   w_mode,
10345   w_mode,
10346   w_mode,
10347   t_mode,
10348   q_mode,
10349   t_mode,
10350   q_mode
10351 };
10352
10353 #define ST { OP_ST, 0 }
10354 #define STi { OP_STi, 0 }
10355
10356 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
10357 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
10358 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
10359 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
10360 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
10361 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
10362 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
10363 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
10364 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
10365
10366 static const struct dis386 float_reg[][8] = {
10367   /* d8 */
10368   {
10369     { "fadd",   { ST, STi }, 0 },
10370     { "fmul",   { ST, STi }, 0 },
10371     { "fcom",   { STi }, 0 },
10372     { "fcomp",  { STi }, 0 },
10373     { "fsub",   { ST, STi }, 0 },
10374     { "fsubr",  { ST, STi }, 0 },
10375     { "fdiv",   { ST, STi }, 0 },
10376     { "fdivr",  { ST, STi }, 0 },
10377   },
10378   /* d9 */
10379   {
10380     { "fld",    { STi }, 0 },
10381     { "fxch",   { STi }, 0 },
10382     { FGRPd9_2 },
10383     { Bad_Opcode },
10384     { FGRPd9_4 },
10385     { FGRPd9_5 },
10386     { FGRPd9_6 },
10387     { FGRPd9_7 },
10388   },
10389   /* da */
10390   {
10391     { "fcmovb", { ST, STi }, 0 },
10392     { "fcmove", { ST, STi }, 0 },
10393     { "fcmovbe",{ ST, STi }, 0 },
10394     { "fcmovu", { ST, STi }, 0 },
10395     { Bad_Opcode },
10396     { FGRPda_5 },
10397     { Bad_Opcode },
10398     { Bad_Opcode },
10399   },
10400   /* db */
10401   {
10402     { "fcmovnb",{ ST, STi }, 0 },
10403     { "fcmovne",{ ST, STi }, 0 },
10404     { "fcmovnbe",{ ST, STi }, 0 },
10405     { "fcmovnu",{ ST, STi }, 0 },
10406     { FGRPdb_4 },
10407     { "fucomi", { ST, STi }, 0 },
10408     { "fcomi",  { ST, STi }, 0 },
10409     { Bad_Opcode },
10410   },
10411   /* dc */
10412   {
10413     { "fadd",   { STi, ST }, 0 },
10414     { "fmul",   { STi, ST }, 0 },
10415     { Bad_Opcode },
10416     { Bad_Opcode },
10417     { "fsub{!M|r}",     { STi, ST }, 0 },
10418     { "fsub{M|}",       { STi, ST }, 0 },
10419     { "fdiv{!M|r}",     { STi, ST }, 0 },
10420     { "fdiv{M|}",       { STi, ST }, 0 },
10421   },
10422   /* dd */
10423   {
10424     { "ffree",  { STi }, 0 },
10425     { Bad_Opcode },
10426     { "fst",    { STi }, 0 },
10427     { "fstp",   { STi }, 0 },
10428     { "fucom",  { STi }, 0 },
10429     { "fucomp", { STi }, 0 },
10430     { Bad_Opcode },
10431     { Bad_Opcode },
10432   },
10433   /* de */
10434   {
10435     { "faddp",  { STi, ST }, 0 },
10436     { "fmulp",  { STi, ST }, 0 },
10437     { Bad_Opcode },
10438     { FGRPde_3 },
10439     { "fsub{!M|r}p",    { STi, ST }, 0 },
10440     { "fsub{M|}p",      { STi, ST }, 0 },
10441     { "fdiv{!M|r}p",    { STi, ST }, 0 },
10442     { "fdiv{M|}p",      { STi, ST }, 0 },
10443   },
10444   /* df */
10445   {
10446     { "ffreep", { STi }, 0 },
10447     { Bad_Opcode },
10448     { Bad_Opcode },
10449     { Bad_Opcode },
10450     { FGRPdf_4 },
10451     { "fucomip", { ST, STi }, 0 },
10452     { "fcomip", { ST, STi }, 0 },
10453     { Bad_Opcode },
10454   },
10455 };
10456
10457 static char *fgrps[][8] = {
10458   /* Bad opcode 0 */
10459   {
10460     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10461   },
10462
10463   /* d9_2  1 */
10464   {
10465     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10466   },
10467
10468   /* d9_4  2 */
10469   {
10470     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
10471   },
10472
10473   /* d9_5  3 */
10474   {
10475     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
10476   },
10477
10478   /* d9_6  4 */
10479   {
10480     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
10481   },
10482
10483   /* d9_7  5 */
10484   {
10485     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
10486   },
10487
10488   /* da_5  6 */
10489   {
10490     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10491   },
10492
10493   /* db_4  7 */
10494   {
10495     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
10496     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
10497   },
10498
10499   /* de_3  8 */
10500   {
10501     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10502   },
10503
10504   /* df_4  9 */
10505   {
10506     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10507   },
10508 };
10509
10510 static void
10511 swap_operand (void)
10512 {
10513   mnemonicendp[0] = '.';
10514   mnemonicendp[1] = 's';
10515   mnemonicendp += 2;
10516 }
10517
10518 static void
10519 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
10520                int sizeflag ATTRIBUTE_UNUSED)
10521 {
10522   /* Skip mod/rm byte.  */
10523   MODRM_CHECK;
10524   codep++;
10525 }
10526
10527 static void
10528 dofloat (int sizeflag)
10529 {
10530   const struct dis386 *dp;
10531   unsigned char floatop;
10532
10533   floatop = codep[-1];
10534
10535   if (modrm.mod != 3)
10536     {
10537       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
10538
10539       putop (float_mem[fp_indx], sizeflag);
10540       obufp = op_out[0];
10541       op_ad = 2;
10542       OP_E (float_mem_mode[fp_indx], sizeflag);
10543       return;
10544     }
10545   /* Skip mod/rm byte.  */
10546   MODRM_CHECK;
10547   codep++;
10548
10549   dp = &float_reg[floatop - 0xd8][modrm.reg];
10550   if (dp->name == NULL)
10551     {
10552       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
10553
10554       /* Instruction fnstsw is only one with strange arg.  */
10555       if (floatop == 0xdf && codep[-1] == 0xe0)
10556         strcpy (op_out[0], names16[0]);
10557     }
10558   else
10559     {
10560       putop (dp->name, sizeflag);
10561
10562       obufp = op_out[0];
10563       op_ad = 2;
10564       if (dp->op[0].rtn)
10565         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
10566
10567       obufp = op_out[1];
10568       op_ad = 1;
10569       if (dp->op[1].rtn)
10570         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
10571     }
10572 }
10573
10574 /* Like oappend (below), but S is a string starting with '%'.
10575    In Intel syntax, the '%' is elided.  */
10576 static void
10577 oappend_maybe_intel (const char *s)
10578 {
10579   oappend (s + intel_syntax);
10580 }
10581
10582 static void
10583 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
10584 {
10585   oappend_maybe_intel ("%st");
10586 }
10587
10588 static void
10589 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
10590 {
10591   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
10592   oappend_maybe_intel (scratchbuf);
10593 }
10594
10595 /* Capital letters in template are macros.  */
10596 static int
10597 putop (const char *in_template, int sizeflag)
10598 {
10599   const char *p;
10600   int alt = 0;
10601   int cond = 1;
10602   unsigned int l = 0, len = 0;
10603   char last[4];
10604
10605   for (p = in_template; *p; p++)
10606     {
10607       if (len > l)
10608         {
10609           if (l >= sizeof (last) || !ISUPPER (*p))
10610             abort ();
10611           last[l++] = *p;
10612           continue;
10613         }
10614       switch (*p)
10615         {
10616         default:
10617           *obufp++ = *p;
10618           break;
10619         case '%':
10620           len++;
10621           break;
10622         case '!':
10623           cond = 0;
10624           break;
10625         case '{':
10626           if (intel_syntax)
10627             {
10628               while (*++p != '|')
10629                 if (*p == '}' || *p == '\0')
10630                   abort ();
10631               alt = 1;
10632             }
10633           break;
10634         case '|':
10635           while (*++p != '}')
10636             {
10637               if (*p == '\0')
10638                 abort ();
10639             }
10640           break;
10641         case '}':
10642           alt = 0;
10643           break;
10644         case 'A':
10645           if (intel_syntax)
10646             break;
10647           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
10648             *obufp++ = 'b';
10649           break;
10650         case 'B':
10651           if (l == 0)
10652             {
10653             case_B:
10654               if (intel_syntax)
10655                 break;
10656               if (sizeflag & SUFFIX_ALWAYS)
10657                 *obufp++ = 'b';
10658             }
10659           else if (l == 1 && last[0] == 'L')
10660             {
10661               if (address_mode == mode_64bit
10662                   && !(prefixes & PREFIX_ADDR))
10663                 {
10664                   *obufp++ = 'a';
10665                   *obufp++ = 'b';
10666                   *obufp++ = 's';
10667                 }
10668
10669               goto case_B;
10670             }
10671           else
10672             abort ();
10673           break;
10674         case 'C':
10675           if (intel_syntax && !alt)
10676             break;
10677           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10678             {
10679               if (sizeflag & DFLAG)
10680                 *obufp++ = intel_syntax ? 'd' : 'l';
10681               else
10682                 *obufp++ = intel_syntax ? 'w' : 's';
10683               used_prefixes |= (prefixes & PREFIX_DATA);
10684             }
10685           break;
10686         case 'D':
10687           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
10688             break;
10689           USED_REX (REX_W);
10690           if (modrm.mod == 3)
10691             {
10692               if (rex & REX_W)
10693                 *obufp++ = 'q';
10694               else
10695                 {
10696                   if (sizeflag & DFLAG)
10697                     *obufp++ = intel_syntax ? 'd' : 'l';
10698                   else
10699                     *obufp++ = 'w';
10700                   used_prefixes |= (prefixes & PREFIX_DATA);
10701                 }
10702             }
10703           else
10704             *obufp++ = 'w';
10705           break;
10706         case 'E':               /* For jcxz/jecxz */
10707           if (address_mode == mode_64bit)
10708             {
10709               if (sizeflag & AFLAG)
10710                 *obufp++ = 'r';
10711               else
10712                 *obufp++ = 'e';
10713             }
10714           else
10715             if (sizeflag & AFLAG)
10716               *obufp++ = 'e';
10717           used_prefixes |= (prefixes & PREFIX_ADDR);
10718           break;
10719         case 'F':
10720           if (intel_syntax)
10721             break;
10722           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
10723             {
10724               if (sizeflag & AFLAG)
10725                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
10726               else
10727                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
10728               used_prefixes |= (prefixes & PREFIX_ADDR);
10729             }
10730           break;
10731         case 'G':
10732           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
10733             break;
10734           if ((rex & REX_W) || (sizeflag & DFLAG))
10735             *obufp++ = 'l';
10736           else
10737             *obufp++ = 'w';
10738           if (!(rex & REX_W))
10739             used_prefixes |= (prefixes & PREFIX_DATA);
10740           break;
10741         case 'H':
10742           if (intel_syntax)
10743             break;
10744           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
10745               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
10746             {
10747               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
10748               *obufp++ = ',';
10749               *obufp++ = 'p';
10750               if (prefixes & PREFIX_DS)
10751                 *obufp++ = 't';
10752               else
10753                 *obufp++ = 'n';
10754             }
10755           break;
10756         case 'K':
10757           USED_REX (REX_W);
10758           if (rex & REX_W)
10759             *obufp++ = 'q';
10760           else
10761             *obufp++ = 'd';
10762           break;
10763         case 'L':
10764           abort ();
10765         case 'M':
10766           if (intel_mnemonic != cond)
10767             *obufp++ = 'r';
10768           break;
10769         case 'N':
10770           if ((prefixes & PREFIX_FWAIT) == 0)
10771             *obufp++ = 'n';
10772           else
10773             used_prefixes |= PREFIX_FWAIT;
10774           break;
10775         case 'O':
10776           USED_REX (REX_W);
10777           if (rex & REX_W)
10778             *obufp++ = 'o';
10779           else if (intel_syntax && (sizeflag & DFLAG))
10780             *obufp++ = 'q';
10781           else
10782             *obufp++ = 'd';
10783           if (!(rex & REX_W))
10784             used_prefixes |= (prefixes & PREFIX_DATA);
10785           break;
10786         case '@':
10787           if (address_mode == mode_64bit
10788               && (isa64 == intel64 || (rex & REX_W)
10789                   || !(prefixes & PREFIX_DATA)))
10790             {
10791               if (sizeflag & SUFFIX_ALWAYS)
10792                 *obufp++ = 'q';
10793               break;
10794             }
10795           /* Fall through.  */
10796         case 'P':
10797           if (l == 0)
10798             {
10799               if (((need_modrm && modrm.mod == 3) || !cond)
10800                   && !(sizeflag & SUFFIX_ALWAYS))
10801                 break;
10802           /* Fall through.  */
10803         case 'T':
10804               if ((!(rex & REX_W) && (prefixes & PREFIX_DATA))
10805                   || ((sizeflag & SUFFIX_ALWAYS)
10806                       && address_mode != mode_64bit))
10807                 {
10808                   *obufp++ = (sizeflag & DFLAG) ?
10809                              intel_syntax ? 'd' : 'l' : 'w';
10810                   used_prefixes |= (prefixes & PREFIX_DATA);
10811                 }
10812               else if (sizeflag & SUFFIX_ALWAYS)
10813                 *obufp++ = 'q';
10814             }
10815           else if (l == 1 && last[0] == 'L')
10816             {
10817               if ((prefixes & PREFIX_DATA)
10818                   || (rex & REX_W)
10819                   || (sizeflag & SUFFIX_ALWAYS))
10820                 {
10821                   USED_REX (REX_W);
10822                   if (rex & REX_W)
10823                     *obufp++ = 'q';
10824                   else
10825                     {
10826                       if (sizeflag & DFLAG)
10827                         *obufp++ = intel_syntax ? 'd' : 'l';
10828                       else
10829                         *obufp++ = 'w';
10830                       used_prefixes |= (prefixes & PREFIX_DATA);
10831                     }
10832                 }
10833             }
10834           else
10835             abort ();
10836           break;
10837         case 'Q':
10838           if (l == 0)
10839             {
10840               if (intel_syntax && !alt)
10841                 break;
10842               USED_REX (REX_W);
10843               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
10844                 {
10845                   if (rex & REX_W)
10846                     *obufp++ = 'q';
10847                   else
10848                     {
10849                       if (sizeflag & DFLAG)
10850                         *obufp++ = intel_syntax ? 'd' : 'l';
10851                       else
10852                         *obufp++ = 'w';
10853                       used_prefixes |= (prefixes & PREFIX_DATA);
10854                     }
10855                 }
10856             }
10857           else if (l == 1 && last[0] == 'D')
10858             *obufp++ = vex.w ? 'q' : 'd';
10859           else if (l == 1 && last[0] == 'L')
10860             {
10861               if (cond ? modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)
10862                        : address_mode != mode_64bit)
10863                 break;
10864               if ((rex & REX_W))
10865                 {
10866                   USED_REX (REX_W);
10867                   *obufp++ = 'q';
10868                 }
10869               else if((address_mode == mode_64bit && need_modrm && cond)
10870                       || (sizeflag & SUFFIX_ALWAYS))
10871                 *obufp++ = intel_syntax? 'd' : 'l';
10872             }
10873           else
10874             abort ();
10875           break;
10876         case 'R':
10877           USED_REX (REX_W);
10878           if (rex & REX_W)
10879             *obufp++ = 'q';
10880           else if (sizeflag & DFLAG)
10881             {
10882               if (intel_syntax)
10883                   *obufp++ = 'd';
10884               else
10885                   *obufp++ = 'l';
10886             }
10887           else
10888             *obufp++ = 'w';
10889           if (intel_syntax && !p[1]
10890               && ((rex & REX_W) || (sizeflag & DFLAG)))
10891             *obufp++ = 'e';
10892           if (!(rex & REX_W))
10893             used_prefixes |= (prefixes & PREFIX_DATA);
10894           break;
10895         case 'S':
10896           if (l == 0)
10897             {
10898             case_S:
10899               if (intel_syntax)
10900                 break;
10901               if (sizeflag & SUFFIX_ALWAYS)
10902                 {
10903                   if (rex & REX_W)
10904                     *obufp++ = 'q';
10905                   else
10906                     {
10907                       if (sizeflag & DFLAG)
10908                         *obufp++ = 'l';
10909                       else
10910                         *obufp++ = 'w';
10911                       used_prefixes |= (prefixes & PREFIX_DATA);
10912                     }
10913                 }
10914             }
10915           else if (l == 1 && last[0] == 'L')
10916             {
10917               if (address_mode == mode_64bit
10918                   && !(prefixes & PREFIX_ADDR))
10919                 {
10920                   *obufp++ = 'a';
10921                   *obufp++ = 'b';
10922                   *obufp++ = 's';
10923                 }
10924
10925               goto case_S;
10926             }
10927           else
10928             abort ();
10929           break;
10930         case 'V':
10931           if (l == 0)
10932             abort ();
10933           else if (l == 1 && last[0] == 'L')
10934             {
10935               if (rex & REX_W)
10936                 {
10937                   *obufp++ = 'a';
10938                   *obufp++ = 'b';
10939                   *obufp++ = 's';
10940                 }
10941             }
10942           else
10943             abort ();
10944           goto case_S;
10945         case 'W':
10946           if (l == 0)
10947             {
10948               /* operand size flag for cwtl, cbtw */
10949               USED_REX (REX_W);
10950               if (rex & REX_W)
10951                 {
10952                   if (intel_syntax)
10953                     *obufp++ = 'd';
10954                   else
10955                     *obufp++ = 'l';
10956                 }
10957               else if (sizeflag & DFLAG)
10958                 *obufp++ = 'w';
10959               else
10960                 *obufp++ = 'b';
10961               if (!(rex & REX_W))
10962                 used_prefixes |= (prefixes & PREFIX_DATA);
10963             }
10964           else if (l == 1)
10965             {
10966               if (!need_vex)
10967                 abort ();
10968               if (last[0] == 'X')
10969                 *obufp++ = vex.w ? 'd': 's';
10970               else if (last[0] == 'B')
10971                 *obufp++ = vex.w ? 'w': 'b';
10972               else
10973                 abort ();
10974             }
10975           else
10976             abort ();
10977           break;
10978         case 'X':
10979           if (l != 0)
10980             abort ();
10981           if (need_vex
10982               ? vex.prefix == DATA_PREFIX_OPCODE
10983               : prefixes & PREFIX_DATA)
10984             {
10985               *obufp++ = 'd';
10986               used_prefixes |= PREFIX_DATA;
10987             }
10988           else
10989             *obufp++ = 's';
10990           break;
10991         case 'Y':
10992           if (l == 1 && last[0] == 'X')
10993             {
10994               if (!need_vex)
10995                 abort ();
10996               if (intel_syntax
10997                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
10998                 break;
10999               switch (vex.length)
11000                 {
11001                 case 128:
11002                   *obufp++ = 'x';
11003                   break;
11004                 case 256:
11005                   *obufp++ = 'y';
11006                   break;
11007                 case 512:
11008                   if (!vex.evex)
11009                 default:
11010                     abort ();
11011                 }
11012             }
11013           else
11014             abort ();
11015           break;
11016         case 'Z':
11017           if (l == 0)
11018             {
11019               /* These insns ignore ModR/M.mod: Force it to 3 for OP_E().  */
11020               modrm.mod = 3;
11021               if (!intel_syntax && (sizeflag & SUFFIX_ALWAYS))
11022                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
11023             }
11024           else if (l == 1 && last[0] == 'X')
11025             {
11026               if (!need_vex || !vex.evex)
11027                 abort ();
11028               if (intel_syntax
11029                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
11030                 break;
11031               switch (vex.length)
11032                 {
11033                 case 128:
11034                   *obufp++ = 'x';
11035                   break;
11036                 case 256:
11037                   *obufp++ = 'y';
11038                   break;
11039                 case 512:
11040                   *obufp++ = 'z';
11041                   break;
11042                 default:
11043                   abort ();
11044                 }
11045             }
11046           else
11047             abort ();
11048           break;
11049         case '^':
11050           if (intel_syntax)
11051             break;
11052           if (isa64 == intel64 && (rex & REX_W))
11053             {
11054               USED_REX (REX_W);
11055               *obufp++ = 'q';
11056               break;
11057             }
11058           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
11059             {
11060               if (sizeflag & DFLAG)
11061                 *obufp++ = 'l';
11062               else
11063                 *obufp++ = 'w';
11064               used_prefixes |= (prefixes & PREFIX_DATA);
11065             }
11066           break;
11067         }
11068
11069       if (len == l)
11070         len = l = 0;
11071     }
11072   *obufp = 0;
11073   mnemonicendp = obufp;
11074   return 0;
11075 }
11076
11077 static void
11078 oappend (const char *s)
11079 {
11080   obufp = stpcpy (obufp, s);
11081 }
11082
11083 static void
11084 append_seg (void)
11085 {
11086   /* Only print the active segment register.  */
11087   if (!active_seg_prefix)
11088     return;
11089
11090   used_prefixes |= active_seg_prefix;
11091   switch (active_seg_prefix)
11092     {
11093     case PREFIX_CS:
11094       oappend_maybe_intel ("%cs:");
11095       break;
11096     case PREFIX_DS:
11097       oappend_maybe_intel ("%ds:");
11098       break;
11099     case PREFIX_SS:
11100       oappend_maybe_intel ("%ss:");
11101       break;
11102     case PREFIX_ES:
11103       oappend_maybe_intel ("%es:");
11104       break;
11105     case PREFIX_FS:
11106       oappend_maybe_intel ("%fs:");
11107       break;
11108     case PREFIX_GS:
11109       oappend_maybe_intel ("%gs:");
11110       break;
11111     default:
11112       break;
11113     }
11114 }
11115
11116 static void
11117 OP_indirE (int bytemode, int sizeflag)
11118 {
11119   if (!intel_syntax)
11120     oappend ("*");
11121   OP_E (bytemode, sizeflag);
11122 }
11123
11124 static void
11125 print_operand_value (char *buf, int hex, bfd_vma disp)
11126 {
11127   if (address_mode == mode_64bit)
11128     {
11129       if (hex)
11130         {
11131           char tmp[30];
11132           int i;
11133           buf[0] = '0';
11134           buf[1] = 'x';
11135           sprintf_vma (tmp, disp);
11136           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
11137           strcpy (buf + 2, tmp + i);
11138         }
11139       else
11140         {
11141           bfd_signed_vma v = disp;
11142           char tmp[30];
11143           int i;
11144           if (v < 0)
11145             {
11146               *(buf++) = '-';
11147               v = -disp;
11148               /* Check for possible overflow on 0x8000000000000000.  */
11149               if (v < 0)
11150                 {
11151                   strcpy (buf, "9223372036854775808");
11152                   return;
11153                 }
11154             }
11155           if (!v)
11156             {
11157               strcpy (buf, "0");
11158               return;
11159             }
11160
11161           i = 0;
11162           tmp[29] = 0;
11163           while (v)
11164             {
11165               tmp[28 - i] = (v % 10) + '0';
11166               v /= 10;
11167               i++;
11168             }
11169           strcpy (buf, tmp + 29 - i);
11170         }
11171     }
11172   else
11173     {
11174       if (hex)
11175         sprintf (buf, "0x%x", (unsigned int) disp);
11176       else
11177         sprintf (buf, "%d", (int) disp);
11178     }
11179 }
11180
11181 /* Put DISP in BUF as signed hex number.  */
11182
11183 static void
11184 print_displacement (char *buf, bfd_vma disp)
11185 {
11186   bfd_signed_vma val = disp;
11187   char tmp[30];
11188   int i, j = 0;
11189
11190   if (val < 0)
11191     {
11192       buf[j++] = '-';
11193       val = -disp;
11194
11195       /* Check for possible overflow.  */
11196       if (val < 0)
11197         {
11198           switch (address_mode)
11199             {
11200             case mode_64bit:
11201               strcpy (buf + j, "0x8000000000000000");
11202               break;
11203             case mode_32bit:
11204               strcpy (buf + j, "0x80000000");
11205               break;
11206             case mode_16bit:
11207               strcpy (buf + j, "0x8000");
11208               break;
11209             }
11210           return;
11211         }
11212     }
11213
11214   buf[j++] = '0';
11215   buf[j++] = 'x';
11216
11217   sprintf_vma (tmp, (bfd_vma) val);
11218   for (i = 0; tmp[i] == '0'; i++)
11219     continue;
11220   if (tmp[i] == '\0')
11221     i--;
11222   strcpy (buf + j, tmp + i);
11223 }
11224
11225 static void
11226 intel_operand_size (int bytemode, int sizeflag)
11227 {
11228   if (vex.evex
11229       && vex.b
11230       && (bytemode == x_mode
11231           || bytemode == evex_half_bcst_xmmq_mode))
11232     {
11233       if (vex.w)
11234         oappend ("QWORD PTR ");
11235       else
11236         oappend ("DWORD PTR ");
11237       return;
11238     }
11239   switch (bytemode)
11240     {
11241     case b_mode:
11242     case b_swap_mode:
11243     case dqb_mode:
11244     case db_mode:
11245       oappend ("BYTE PTR ");
11246       break;
11247     case w_mode:
11248     case dw_mode:
11249     case dqw_mode:
11250       oappend ("WORD PTR ");
11251       break;
11252     case indir_v_mode:
11253       if (address_mode == mode_64bit && isa64 == intel64)
11254         {
11255           oappend ("QWORD PTR ");
11256           break;
11257         }
11258       /* Fall through.  */
11259     case stack_v_mode:
11260       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
11261         {
11262           oappend ("QWORD PTR ");
11263           break;
11264         }
11265       /* Fall through.  */
11266     case v_mode:
11267     case v_swap_mode:
11268     case dq_mode:
11269       USED_REX (REX_W);
11270       if (rex & REX_W)
11271         oappend ("QWORD PTR ");
11272       else if (bytemode == dq_mode)
11273         oappend ("DWORD PTR ");
11274       else
11275         {
11276           if (sizeflag & DFLAG)
11277             oappend ("DWORD PTR ");
11278           else
11279             oappend ("WORD PTR ");
11280           used_prefixes |= (prefixes & PREFIX_DATA);
11281         }
11282       break;
11283     case z_mode:
11284       if ((rex & REX_W) || (sizeflag & DFLAG))
11285         *obufp++ = 'D';
11286       oappend ("WORD PTR ");
11287       if (!(rex & REX_W))
11288         used_prefixes |= (prefixes & PREFIX_DATA);
11289       break;
11290     case a_mode:
11291       if (sizeflag & DFLAG)
11292         oappend ("QWORD PTR ");
11293       else
11294         oappend ("DWORD PTR ");
11295       used_prefixes |= (prefixes & PREFIX_DATA);
11296       break;
11297     case movsxd_mode:
11298       if (!(sizeflag & DFLAG) && isa64 == intel64)
11299         oappend ("WORD PTR ");
11300       else
11301         oappend ("DWORD PTR ");
11302       used_prefixes |= (prefixes & PREFIX_DATA);
11303       break;
11304     case d_mode:
11305     case d_swap_mode:
11306     case dqd_mode:
11307       oappend ("DWORD PTR ");
11308       break;
11309     case q_mode:
11310     case q_swap_mode:
11311       oappend ("QWORD PTR ");
11312       break;
11313     case m_mode:
11314       if (address_mode == mode_64bit)
11315         oappend ("QWORD PTR ");
11316       else
11317         oappend ("DWORD PTR ");
11318       break;
11319     case f_mode:
11320       if (sizeflag & DFLAG)
11321         oappend ("FWORD PTR ");
11322       else
11323         oappend ("DWORD PTR ");
11324       used_prefixes |= (prefixes & PREFIX_DATA);
11325       break;
11326     case t_mode:
11327       oappend ("TBYTE PTR ");
11328       break;
11329     case x_mode:
11330     case x_swap_mode:
11331     case evex_x_gscat_mode:
11332     case evex_x_nobcst_mode:
11333     case bw_unit_mode:
11334       if (need_vex)
11335         {
11336           switch (vex.length)
11337             {
11338             case 128:
11339               oappend ("XMMWORD PTR ");
11340               break;
11341             case 256:
11342               oappend ("YMMWORD PTR ");
11343               break;
11344             case 512:
11345               oappend ("ZMMWORD PTR ");
11346               break;
11347             default:
11348               abort ();
11349             }
11350         }
11351       else
11352         oappend ("XMMWORD PTR ");
11353       break;
11354     case xmm_mode:
11355       oappend ("XMMWORD PTR ");
11356       break;
11357     case ymm_mode:
11358       oappend ("YMMWORD PTR ");
11359       break;
11360     case xmmq_mode:
11361     case evex_half_bcst_xmmq_mode:
11362       if (!need_vex)
11363         abort ();
11364
11365       switch (vex.length)
11366         {
11367         case 128:
11368           oappend ("QWORD PTR ");
11369           break;
11370         case 256:
11371           oappend ("XMMWORD PTR ");
11372           break;
11373         case 512:
11374           oappend ("YMMWORD PTR ");
11375           break;
11376         default:
11377           abort ();
11378         }
11379       break;
11380     case xmm_mb_mode:
11381       if (!need_vex)
11382         abort ();
11383
11384       switch (vex.length)
11385         {
11386         case 128:
11387         case 256:
11388         case 512:
11389           oappend ("BYTE PTR ");
11390           break;
11391         default:
11392           abort ();
11393         }
11394       break;
11395     case xmm_mw_mode:
11396       if (!need_vex)
11397         abort ();
11398
11399       switch (vex.length)
11400         {
11401         case 128:
11402         case 256:
11403         case 512:
11404           oappend ("WORD PTR ");
11405           break;
11406         default:
11407           abort ();
11408         }
11409       break;
11410     case xmm_md_mode:
11411       if (!need_vex)
11412         abort ();
11413
11414       switch (vex.length)
11415         {
11416         case 128:
11417         case 256:
11418         case 512:
11419           oappend ("DWORD PTR ");
11420           break;
11421         default:
11422           abort ();
11423         }
11424       break;
11425     case xmm_mq_mode:
11426       if (!need_vex)
11427         abort ();
11428
11429       switch (vex.length)
11430         {
11431         case 128:
11432         case 256:
11433         case 512:
11434           oappend ("QWORD PTR ");
11435           break;
11436         default:
11437           abort ();
11438         }
11439       break;
11440     case xmmdw_mode:
11441       if (!need_vex)
11442         abort ();
11443
11444       switch (vex.length)
11445         {
11446         case 128:
11447           oappend ("WORD PTR ");
11448           break;
11449         case 256:
11450           oappend ("DWORD PTR ");
11451           break;
11452         case 512:
11453           oappend ("QWORD PTR ");
11454           break;
11455         default:
11456           abort ();
11457         }
11458       break;
11459     case xmmqd_mode:
11460       if (!need_vex)
11461         abort ();
11462
11463       switch (vex.length)
11464         {
11465         case 128:
11466           oappend ("DWORD PTR ");
11467           break;
11468         case 256:
11469           oappend ("QWORD PTR ");
11470           break;
11471         case 512:
11472           oappend ("XMMWORD PTR ");
11473           break;
11474         default:
11475           abort ();
11476         }
11477       break;
11478     case ymmq_mode:
11479       if (!need_vex)
11480         abort ();
11481
11482       switch (vex.length)
11483         {
11484         case 128:
11485           oappend ("QWORD PTR ");
11486           break;
11487         case 256:
11488           oappend ("YMMWORD PTR ");
11489           break;
11490         case 512:
11491           oappend ("ZMMWORD PTR ");
11492           break;
11493         default:
11494           abort ();
11495         }
11496       break;
11497     case ymmxmm_mode:
11498       if (!need_vex)
11499         abort ();
11500
11501       switch (vex.length)
11502         {
11503         case 128:
11504         case 256:
11505           oappend ("XMMWORD PTR ");
11506           break;
11507         default:
11508           abort ();
11509         }
11510       break;
11511     case o_mode:
11512       oappend ("OWORD PTR ");
11513       break;
11514     case vex_scalar_w_dq_mode:
11515       if (!need_vex)
11516         abort ();
11517
11518       if (vex.w)
11519         oappend ("QWORD PTR ");
11520       else
11521         oappend ("DWORD PTR ");
11522       break;
11523     case vex_vsib_d_w_dq_mode:
11524     case vex_vsib_q_w_dq_mode:
11525       if (!need_vex)
11526         abort ();
11527
11528       if (!vex.evex)
11529         {
11530           if (vex.w)
11531             oappend ("QWORD PTR ");
11532           else
11533             oappend ("DWORD PTR ");
11534         }
11535       else
11536         {
11537           switch (vex.length)
11538             {
11539             case 128:
11540               oappend ("XMMWORD PTR ");
11541               break;
11542             case 256:
11543               oappend ("YMMWORD PTR ");
11544               break;
11545             case 512:
11546               oappend ("ZMMWORD PTR ");
11547               break;
11548             default:
11549               abort ();
11550             }
11551         }
11552       break;
11553     case vex_vsib_q_w_d_mode:
11554     case vex_vsib_d_w_d_mode:
11555       if (!need_vex || !vex.evex)
11556         abort ();
11557
11558       switch (vex.length)
11559         {
11560         case 128:
11561           oappend ("QWORD PTR ");
11562           break;
11563         case 256:
11564           oappend ("XMMWORD PTR ");
11565           break;
11566         case 512:
11567           oappend ("YMMWORD PTR ");
11568           break;
11569         default:
11570           abort ();
11571         }
11572
11573       break;
11574     case mask_bd_mode:
11575       if (!need_vex || vex.length != 128)
11576         abort ();
11577       if (vex.w)
11578         oappend ("DWORD PTR ");
11579       else
11580         oappend ("BYTE PTR ");
11581       break;
11582     case mask_mode:
11583       if (!need_vex)
11584         abort ();
11585       if (vex.w)
11586         oappend ("QWORD PTR ");
11587       else
11588         oappend ("WORD PTR ");
11589       break;
11590     case v_bnd_mode:
11591     case v_bndmk_mode:
11592     default:
11593       break;
11594     }
11595 }
11596
11597 static void
11598 OP_E_register (int bytemode, int sizeflag)
11599 {
11600   int reg = modrm.rm;
11601   const char **names;
11602
11603   USED_REX (REX_B);
11604   if ((rex & REX_B))
11605     reg += 8;
11606
11607   if ((sizeflag & SUFFIX_ALWAYS)
11608       && (bytemode == b_swap_mode
11609           || bytemode == bnd_swap_mode
11610           || bytemode == v_swap_mode))
11611     swap_operand ();
11612
11613   switch (bytemode)
11614     {
11615     case b_mode:
11616     case b_swap_mode:
11617       if (reg & 4)
11618         USED_REX (0);
11619       if (rex)
11620         names = names8rex;
11621       else
11622         names = names8;
11623       break;
11624     case w_mode:
11625       names = names16;
11626       break;
11627     case d_mode:
11628     case dw_mode:
11629     case db_mode:
11630       names = names32;
11631       break;
11632     case q_mode:
11633       names = names64;
11634       break;
11635     case m_mode:
11636     case v_bnd_mode:
11637       names = address_mode == mode_64bit ? names64 : names32;
11638       break;
11639     case bnd_mode:
11640     case bnd_swap_mode:
11641       if (reg > 0x3)
11642         {
11643           oappend ("(bad)");
11644           return;
11645         }
11646       names = names_bnd;
11647       break;
11648     case indir_v_mode:
11649       if (address_mode == mode_64bit && isa64 == intel64)
11650         {
11651           names = names64;
11652           break;
11653         }
11654       /* Fall through.  */
11655     case stack_v_mode:
11656       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
11657         {
11658           names = names64;
11659           break;
11660         }
11661       bytemode = v_mode;
11662       /* Fall through.  */
11663     case v_mode:
11664     case v_swap_mode:
11665     case dq_mode:
11666     case dqb_mode:
11667     case dqd_mode:
11668     case dqw_mode:
11669       USED_REX (REX_W);
11670       if (rex & REX_W)
11671         names = names64;
11672       else if (bytemode != v_mode && bytemode != v_swap_mode)
11673         names = names32;
11674       else
11675         {
11676           if (sizeflag & DFLAG)
11677             names = names32;
11678           else
11679             names = names16;
11680           used_prefixes |= (prefixes & PREFIX_DATA);
11681         }
11682       break;
11683     case movsxd_mode:
11684       if (!(sizeflag & DFLAG) && isa64 == intel64)
11685         names = names16;
11686       else
11687         names = names32;
11688       used_prefixes |= (prefixes & PREFIX_DATA);
11689       break;
11690     case va_mode:
11691       names = (address_mode == mode_64bit
11692                ? names64 : names32);
11693       if (!(prefixes & PREFIX_ADDR))
11694         names = (address_mode == mode_16bit
11695                      ? names16 : names);
11696       else
11697         {
11698           /* Remove "addr16/addr32".  */
11699           all_prefixes[last_addr_prefix] = 0;
11700           names = (address_mode != mode_32bit
11701                        ? names32 : names16);
11702           used_prefixes |= PREFIX_ADDR;
11703         }
11704       break;
11705     case mask_bd_mode:
11706     case mask_mode:
11707       if (reg > 0x7)
11708         {
11709           oappend ("(bad)");
11710           return;
11711         }
11712       names = names_mask;
11713       break;
11714     case 0:
11715       return;
11716     default:
11717       oappend (INTERNAL_DISASSEMBLER_ERROR);
11718       return;
11719     }
11720   oappend (names[reg]);
11721 }
11722
11723 static void
11724 OP_E_memory (int bytemode, int sizeflag)
11725 {
11726   bfd_vma disp = 0;
11727   int add = (rex & REX_B) ? 8 : 0;
11728   int riprel = 0;
11729   int shift;
11730
11731   if (vex.evex)
11732     {
11733       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
11734       if (vex.b
11735           && bytemode != x_mode
11736           && bytemode != xmmq_mode
11737           && bytemode != evex_half_bcst_xmmq_mode)
11738         {
11739           BadOp ();
11740           return;
11741         }
11742       switch (bytemode)
11743         {
11744         case dqw_mode:
11745         case dw_mode:
11746         case xmm_mw_mode:
11747           shift = 1;
11748           break;
11749         case dqb_mode:
11750         case db_mode:
11751         case xmm_mb_mode:
11752           shift = 0;
11753           break;
11754         case dq_mode:
11755           if (address_mode != mode_64bit)
11756             {
11757         case dqd_mode:
11758         case xmm_md_mode:
11759         case d_mode:
11760         case d_swap_mode:
11761               shift = 2;
11762               break;
11763             }
11764             /* fall through */
11765         case vex_scalar_w_dq_mode:
11766         case vex_vsib_d_w_dq_mode:
11767         case vex_vsib_d_w_d_mode:
11768         case vex_vsib_q_w_dq_mode:
11769         case vex_vsib_q_w_d_mode:
11770         case evex_x_gscat_mode:
11771           shift = vex.w ? 3 : 2;
11772           break;
11773         case x_mode:
11774         case evex_half_bcst_xmmq_mode:
11775         case xmmq_mode:
11776           if (vex.b)
11777             {
11778               shift = vex.w ? 3 : 2;
11779               break;
11780             }
11781           /* Fall through.  */
11782         case xmmqd_mode:
11783         case xmmdw_mode:
11784         case ymmq_mode:
11785         case evex_x_nobcst_mode:
11786         case x_swap_mode:
11787           switch (vex.length)
11788             {
11789             case 128:
11790               shift = 4;
11791               break;
11792             case 256:
11793               shift = 5;
11794               break;
11795             case 512:
11796               shift = 6;
11797               break;
11798             default:
11799               abort ();
11800             }
11801           /* Make necessary corrections to shift for modes that need it.  */
11802           if (bytemode == xmmq_mode
11803               || bytemode == evex_half_bcst_xmmq_mode
11804               || (bytemode == ymmq_mode && vex.length == 128))
11805             shift -= 1;
11806           else if (bytemode == xmmqd_mode)
11807             shift -= 2;
11808           else if (bytemode == xmmdw_mode)
11809             shift -= 3;
11810           break;
11811         case ymm_mode:
11812           shift = 5;
11813           break;
11814         case xmm_mode:
11815           shift = 4;
11816           break;
11817         case xmm_mq_mode:
11818         case q_mode:
11819         case q_swap_mode:
11820           shift = 3;
11821           break;
11822         case bw_unit_mode:
11823           shift = vex.w ? 1 : 0;
11824           break;
11825         default:
11826           abort ();
11827         }
11828     }
11829   else
11830     shift = 0;
11831
11832   USED_REX (REX_B);
11833   if (intel_syntax)
11834     intel_operand_size (bytemode, sizeflag);
11835   append_seg ();
11836
11837   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
11838     {
11839       /* 32/64 bit address mode */
11840       int havedisp;
11841       int havesib;
11842       int havebase;
11843       int haveindex;
11844       int needindex;
11845       int needaddr32;
11846       int base, rbase;
11847       int vindex = 0;
11848       int scale = 0;
11849       int addr32flag = !((sizeflag & AFLAG)
11850                          || bytemode == v_bnd_mode
11851                          || bytemode == v_bndmk_mode
11852                          || bytemode == bnd_mode
11853                          || bytemode == bnd_swap_mode);
11854       const char **indexes64 = names64;
11855       const char **indexes32 = names32;
11856
11857       havesib = 0;
11858       havebase = 1;
11859       haveindex = 0;
11860       base = modrm.rm;
11861
11862       if (base == 4)
11863         {
11864           havesib = 1;
11865           vindex = sib.index;
11866           USED_REX (REX_X);
11867           if (rex & REX_X)
11868             vindex += 8;
11869           switch (bytemode)
11870             {
11871             case vex_vsib_d_w_dq_mode:
11872             case vex_vsib_d_w_d_mode:
11873             case vex_vsib_q_w_dq_mode:
11874             case vex_vsib_q_w_d_mode:
11875               if (!need_vex)
11876                 abort ();
11877               if (vex.evex)
11878                 {
11879                   if (!vex.v)
11880                     vindex += 16;
11881                 }
11882
11883               haveindex = 1;
11884               switch (vex.length)
11885                 {
11886                 case 128:
11887                   indexes64 = indexes32 = names_xmm;
11888                   break;
11889                 case 256:
11890                   if (!vex.w
11891                       || bytemode == vex_vsib_q_w_dq_mode
11892                       || bytemode == vex_vsib_q_w_d_mode)
11893                     indexes64 = indexes32 = names_ymm;
11894                   else
11895                     indexes64 = indexes32 = names_xmm;
11896                   break;
11897                 case 512:
11898                   if (!vex.w
11899                       || bytemode == vex_vsib_q_w_dq_mode
11900                       || bytemode == vex_vsib_q_w_d_mode)
11901                     indexes64 = indexes32 = names_zmm;
11902                   else
11903                     indexes64 = indexes32 = names_ymm;
11904                   break;
11905                 default:
11906                   abort ();
11907                 }
11908               break;
11909             default:
11910               haveindex = vindex != 4;
11911               break;
11912             }
11913           scale = sib.scale;
11914           base = sib.base;
11915           codep++;
11916         }
11917       else
11918         {
11919           /* mandatory non-vector SIB must have sib */
11920           if (bytemode == vex_sibmem_mode)
11921             {
11922               oappend ("(bad)");
11923               return;
11924             }
11925         }
11926       rbase = base + add;
11927
11928       switch (modrm.mod)
11929         {
11930         case 0:
11931           if (base == 5)
11932             {
11933               havebase = 0;
11934               if (address_mode == mode_64bit && !havesib)
11935                 riprel = 1;
11936               disp = get32s ();
11937               if (riprel && bytemode == v_bndmk_mode)
11938                 {
11939                   oappend ("(bad)");
11940                   return;
11941                 }
11942             }
11943           break;
11944         case 1:
11945           FETCH_DATA (the_info, codep + 1);
11946           disp = *codep++;
11947           if ((disp & 0x80) != 0)
11948             disp -= 0x100;
11949           if (vex.evex && shift > 0)
11950             disp <<= shift;
11951           break;
11952         case 2:
11953           disp = get32s ();
11954           break;
11955         }
11956
11957       needindex = 0;
11958       needaddr32 = 0;
11959       if (havesib
11960           && !havebase
11961           && !haveindex
11962           && address_mode != mode_16bit)
11963         {
11964           if (address_mode == mode_64bit)
11965             {
11966               if (addr32flag)
11967                 {
11968                   /* Without base nor index registers, zero-extend the
11969                      lower 32-bit displacement to 64 bits.  */
11970                   disp = (unsigned int) disp;
11971                   needindex = 1;
11972                 }
11973               needaddr32 = 1;
11974             }
11975           else
11976             {
11977               /* In 32-bit mode, we need index register to tell [offset]
11978                  from [eiz*1 + offset].  */
11979               needindex = 1;
11980             }
11981         }
11982
11983       havedisp = (havebase
11984                   || needindex
11985                   || (havesib && (haveindex || scale != 0)));
11986
11987       if (!intel_syntax)
11988         if (modrm.mod != 0 || base == 5)
11989           {
11990             if (havedisp || riprel)
11991               print_displacement (scratchbuf, disp);
11992             else
11993               print_operand_value (scratchbuf, 1, disp);
11994             oappend (scratchbuf);
11995             if (riprel)
11996               {
11997                 set_op (disp, 1);
11998                 oappend (!addr32flag ? "(%rip)" : "(%eip)");
11999               }
12000           }
12001
12002       if ((havebase || haveindex || needindex || needaddr32 || riprel)
12003           && (address_mode != mode_64bit
12004               || ((bytemode != v_bnd_mode)
12005                   && (bytemode != v_bndmk_mode)
12006                   && (bytemode != bnd_mode)
12007                   && (bytemode != bnd_swap_mode))))
12008         used_prefixes |= PREFIX_ADDR;
12009
12010       if (havedisp || (intel_syntax && riprel))
12011         {
12012           *obufp++ = open_char;
12013           if (intel_syntax && riprel)
12014             {
12015               set_op (disp, 1);
12016               oappend (!addr32flag ? "rip" : "eip");
12017             }
12018           *obufp = '\0';
12019           if (havebase)
12020             oappend (address_mode == mode_64bit && !addr32flag
12021                      ? names64[rbase] : names32[rbase]);
12022           if (havesib)
12023             {
12024               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
12025                  print index to tell base + index from base.  */
12026               if (scale != 0
12027                   || needindex
12028                   || haveindex
12029                   || (havebase && base != ESP_REG_NUM))
12030                 {
12031                   if (!intel_syntax || havebase)
12032                     {
12033                       *obufp++ = separator_char;
12034                       *obufp = '\0';
12035                     }
12036                   if (haveindex)
12037                     oappend (address_mode == mode_64bit && !addr32flag
12038                              ? indexes64[vindex] : indexes32[vindex]);
12039                   else
12040                     oappend (address_mode == mode_64bit && !addr32flag
12041                              ? index64 : index32);
12042
12043                   *obufp++ = scale_char;
12044                   *obufp = '\0';
12045                   sprintf (scratchbuf, "%d", 1 << scale);
12046                   oappend (scratchbuf);
12047                 }
12048             }
12049           if (intel_syntax
12050               && (disp || modrm.mod != 0 || base == 5))
12051             {
12052               if (!havedisp || (bfd_signed_vma) disp >= 0)
12053                 {
12054                   *obufp++ = '+';
12055                   *obufp = '\0';
12056                 }
12057               else if (modrm.mod != 1 && disp != -disp)
12058                 {
12059                   *obufp++ = '-';
12060                   *obufp = '\0';
12061                   disp = -disp;
12062                 }
12063
12064               if (havedisp)
12065                 print_displacement (scratchbuf, disp);
12066               else
12067                 print_operand_value (scratchbuf, 1, disp);
12068               oappend (scratchbuf);
12069             }
12070
12071           *obufp++ = close_char;
12072           *obufp = '\0';
12073         }
12074       else if (intel_syntax)
12075         {
12076           if (modrm.mod != 0 || base == 5)
12077             {
12078               if (!active_seg_prefix)
12079                 {
12080                   oappend (names_seg[ds_reg - es_reg]);
12081                   oappend (":");
12082                 }
12083               print_operand_value (scratchbuf, 1, disp);
12084               oappend (scratchbuf);
12085             }
12086         }
12087     }
12088   else if (bytemode == v_bnd_mode
12089            || bytemode == v_bndmk_mode
12090            || bytemode == bnd_mode
12091            || bytemode == bnd_swap_mode)
12092     {
12093       oappend ("(bad)");
12094       return;
12095     }
12096   else
12097     {
12098       /* 16 bit address mode */
12099       used_prefixes |= prefixes & PREFIX_ADDR;
12100       switch (modrm.mod)
12101         {
12102         case 0:
12103           if (modrm.rm == 6)
12104             {
12105               disp = get16 ();
12106               if ((disp & 0x8000) != 0)
12107                 disp -= 0x10000;
12108             }
12109           break;
12110         case 1:
12111           FETCH_DATA (the_info, codep + 1);
12112           disp = *codep++;
12113           if ((disp & 0x80) != 0)
12114             disp -= 0x100;
12115           if (vex.evex && shift > 0)
12116             disp <<= shift;
12117           break;
12118         case 2:
12119           disp = get16 ();
12120           if ((disp & 0x8000) != 0)
12121             disp -= 0x10000;
12122           break;
12123         }
12124
12125       if (!intel_syntax)
12126         if (modrm.mod != 0 || modrm.rm == 6)
12127           {
12128             print_displacement (scratchbuf, disp);
12129             oappend (scratchbuf);
12130           }
12131
12132       if (modrm.mod != 0 || modrm.rm != 6)
12133         {
12134           *obufp++ = open_char;
12135           *obufp = '\0';
12136           oappend (index16[modrm.rm]);
12137           if (intel_syntax
12138               && (disp || modrm.mod != 0 || modrm.rm == 6))
12139             {
12140               if ((bfd_signed_vma) disp >= 0)
12141                 {
12142                   *obufp++ = '+';
12143                   *obufp = '\0';
12144                 }
12145               else if (modrm.mod != 1)
12146                 {
12147                   *obufp++ = '-';
12148                   *obufp = '\0';
12149                   disp = -disp;
12150                 }
12151
12152               print_displacement (scratchbuf, disp);
12153               oappend (scratchbuf);
12154             }
12155
12156           *obufp++ = close_char;
12157           *obufp = '\0';
12158         }
12159       else if (intel_syntax)
12160         {
12161           if (!active_seg_prefix)
12162             {
12163               oappend (names_seg[ds_reg - es_reg]);
12164               oappend (":");
12165             }
12166           print_operand_value (scratchbuf, 1, disp & 0xffff);
12167           oappend (scratchbuf);
12168         }
12169     }
12170   if (vex.evex && vex.b
12171       && (bytemode == x_mode
12172           || bytemode == xmmq_mode
12173           || bytemode == evex_half_bcst_xmmq_mode))
12174     {
12175       if (vex.w
12176           || bytemode == xmmq_mode
12177           || bytemode == evex_half_bcst_xmmq_mode)
12178         {
12179           switch (vex.length)
12180             {
12181             case 128:
12182               oappend ("{1to2}");
12183               break;
12184             case 256:
12185               oappend ("{1to4}");
12186               break;
12187             case 512:
12188               oappend ("{1to8}");
12189               break;
12190             default:
12191               abort ();
12192             }
12193         }
12194       else
12195         {
12196           switch (vex.length)
12197             {
12198             case 128:
12199               oappend ("{1to4}");
12200               break;
12201             case 256:
12202               oappend ("{1to8}");
12203               break;
12204             case 512:
12205               oappend ("{1to16}");
12206               break;
12207             default:
12208               abort ();
12209             }
12210         }
12211     }
12212 }
12213
12214 static void
12215 OP_E (int bytemode, int sizeflag)
12216 {
12217   /* Skip mod/rm byte.  */
12218   MODRM_CHECK;
12219   codep++;
12220
12221   if (modrm.mod == 3)
12222     OP_E_register (bytemode, sizeflag);
12223   else
12224     OP_E_memory (bytemode, sizeflag);
12225 }
12226
12227 static void
12228 OP_G (int bytemode, int sizeflag)
12229 {
12230   int add = 0;
12231   const char **names;
12232   USED_REX (REX_R);
12233   if (rex & REX_R)
12234     add += 8;
12235   switch (bytemode)
12236     {
12237     case b_mode:
12238       if (modrm.reg & 4)
12239         USED_REX (0);
12240       if (rex)
12241         oappend (names8rex[modrm.reg + add]);
12242       else
12243         oappend (names8[modrm.reg + add]);
12244       break;
12245     case w_mode:
12246       oappend (names16[modrm.reg + add]);
12247       break;
12248     case d_mode:
12249     case db_mode:
12250     case dw_mode:
12251       oappend (names32[modrm.reg + add]);
12252       break;
12253     case q_mode:
12254       oappend (names64[modrm.reg + add]);
12255       break;
12256     case bnd_mode:
12257       if (modrm.reg > 0x3)
12258         {
12259           oappend ("(bad)");
12260           return;
12261         }
12262       oappend (names_bnd[modrm.reg]);
12263       break;
12264     case v_mode:
12265     case dq_mode:
12266     case dqb_mode:
12267     case dqd_mode:
12268     case dqw_mode:
12269     case movsxd_mode:
12270       USED_REX (REX_W);
12271       if (rex & REX_W)
12272         oappend (names64[modrm.reg + add]);
12273       else if (bytemode != v_mode && bytemode != movsxd_mode)
12274         oappend (names32[modrm.reg + add]);
12275       else
12276         {
12277           if (sizeflag & DFLAG)
12278             oappend (names32[modrm.reg + add]);
12279           else
12280             oappend (names16[modrm.reg + add]);
12281           used_prefixes |= (prefixes & PREFIX_DATA);
12282         }
12283       break;
12284     case va_mode:
12285       names = (address_mode == mode_64bit
12286                ? names64 : names32);
12287       if (!(prefixes & PREFIX_ADDR))
12288         {
12289           if (address_mode == mode_16bit)
12290             names = names16;
12291         }
12292       else
12293         {
12294           /* Remove "addr16/addr32".  */
12295           all_prefixes[last_addr_prefix] = 0;
12296           names = (address_mode != mode_32bit
12297                        ? names32 : names16);
12298           used_prefixes |= PREFIX_ADDR;
12299         }
12300       oappend (names[modrm.reg + add]);
12301       break;
12302     case m_mode:
12303       if (address_mode == mode_64bit)
12304         oappend (names64[modrm.reg + add]);
12305       else
12306         oappend (names32[modrm.reg + add]);
12307       break;
12308     case mask_bd_mode:
12309     case mask_mode:
12310       if ((modrm.reg + add) > 0x7)
12311         {
12312           oappend ("(bad)");
12313           return;
12314         }
12315       oappend (names_mask[modrm.reg + add]);
12316       break;
12317     default:
12318       oappend (INTERNAL_DISASSEMBLER_ERROR);
12319       break;
12320     }
12321 }
12322
12323 static bfd_vma
12324 get64 (void)
12325 {
12326   bfd_vma x;
12327 #ifdef BFD64
12328   unsigned int a;
12329   unsigned int b;
12330
12331   FETCH_DATA (the_info, codep + 8);
12332   a = *codep++ & 0xff;
12333   a |= (*codep++ & 0xff) << 8;
12334   a |= (*codep++ & 0xff) << 16;
12335   a |= (*codep++ & 0xffu) << 24;
12336   b = *codep++ & 0xff;
12337   b |= (*codep++ & 0xff) << 8;
12338   b |= (*codep++ & 0xff) << 16;
12339   b |= (*codep++ & 0xffu) << 24;
12340   x = a + ((bfd_vma) b << 32);
12341 #else
12342   abort ();
12343   x = 0;
12344 #endif
12345   return x;
12346 }
12347
12348 static bfd_signed_vma
12349 get32 (void)
12350 {
12351   bfd_vma x = 0;
12352
12353   FETCH_DATA (the_info, codep + 4);
12354   x = *codep++ & (bfd_vma) 0xff;
12355   x |= (*codep++ & (bfd_vma) 0xff) << 8;
12356   x |= (*codep++ & (bfd_vma) 0xff) << 16;
12357   x |= (*codep++ & (bfd_vma) 0xff) << 24;
12358   return x;
12359 }
12360
12361 static bfd_signed_vma
12362 get32s (void)
12363 {
12364   bfd_vma x = 0;
12365
12366   FETCH_DATA (the_info, codep + 4);
12367   x = *codep++ & (bfd_vma) 0xff;
12368   x |= (*codep++ & (bfd_vma) 0xff) << 8;
12369   x |= (*codep++ & (bfd_vma) 0xff) << 16;
12370   x |= (*codep++ & (bfd_vma) 0xff) << 24;
12371
12372   x = (x ^ ((bfd_vma) 1 << 31)) - ((bfd_vma) 1 << 31);
12373
12374   return x;
12375 }
12376
12377 static int
12378 get16 (void)
12379 {
12380   int x = 0;
12381
12382   FETCH_DATA (the_info, codep + 2);
12383   x = *codep++ & 0xff;
12384   x |= (*codep++ & 0xff) << 8;
12385   return x;
12386 }
12387
12388 static void
12389 set_op (bfd_vma op, int riprel)
12390 {
12391   op_index[op_ad] = op_ad;
12392   if (address_mode == mode_64bit)
12393     {
12394       op_address[op_ad] = op;
12395       op_riprel[op_ad] = riprel;
12396     }
12397   else
12398     {
12399       /* Mask to get a 32-bit address.  */
12400       op_address[op_ad] = op & 0xffffffff;
12401       op_riprel[op_ad] = riprel & 0xffffffff;
12402     }
12403 }
12404
12405 static void
12406 OP_REG (int code, int sizeflag)
12407 {
12408   const char *s;
12409   int add;
12410
12411   switch (code)
12412     {
12413     case es_reg: case ss_reg: case cs_reg:
12414     case ds_reg: case fs_reg: case gs_reg:
12415       oappend (names_seg[code - es_reg]);
12416       return;
12417     }
12418
12419   USED_REX (REX_B);
12420   if (rex & REX_B)
12421     add = 8;
12422   else
12423     add = 0;
12424
12425   switch (code)
12426     {
12427     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
12428     case sp_reg: case bp_reg: case si_reg: case di_reg:
12429       s = names16[code - ax_reg + add];
12430       break;
12431     case ah_reg: case ch_reg: case dh_reg: case bh_reg:
12432       USED_REX (0);
12433       /* Fall through.  */
12434     case al_reg: case cl_reg: case dl_reg: case bl_reg:
12435       if (rex)
12436         s = names8rex[code - al_reg + add];
12437       else
12438         s = names8[code - al_reg];
12439       break;
12440     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
12441     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
12442       if (address_mode == mode_64bit
12443           && ((sizeflag & DFLAG) || (rex & REX_W)))
12444         {
12445           s = names64[code - rAX_reg + add];
12446           break;
12447         }
12448       code += eAX_reg - rAX_reg;
12449       /* Fall through.  */
12450     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
12451     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
12452       USED_REX (REX_W);
12453       if (rex & REX_W)
12454         s = names64[code - eAX_reg + add];
12455       else
12456         {
12457           if (sizeflag & DFLAG)
12458             s = names32[code - eAX_reg + add];
12459           else
12460             s = names16[code - eAX_reg + add];
12461           used_prefixes |= (prefixes & PREFIX_DATA);
12462         }
12463       break;
12464     default:
12465       s = INTERNAL_DISASSEMBLER_ERROR;
12466       break;
12467     }
12468   oappend (s);
12469 }
12470
12471 static void
12472 OP_IMREG (int code, int sizeflag)
12473 {
12474   const char *s;
12475
12476   switch (code)
12477     {
12478     case indir_dx_reg:
12479       if (intel_syntax)
12480         s = "dx";
12481       else
12482         s = "(%dx)";
12483       break;
12484     case al_reg: case cl_reg:
12485       s = names8[code - al_reg];
12486       break;
12487     case eAX_reg:
12488       USED_REX (REX_W);
12489       if (rex & REX_W)
12490         {
12491           s = *names64;
12492           break;
12493         }
12494       /* Fall through.  */
12495     case z_mode_ax_reg:
12496       if ((rex & REX_W) || (sizeflag & DFLAG))
12497         s = *names32;
12498       else
12499         s = *names16;
12500       if (!(rex & REX_W))
12501         used_prefixes |= (prefixes & PREFIX_DATA);
12502       break;
12503     default:
12504       s = INTERNAL_DISASSEMBLER_ERROR;
12505       break;
12506     }
12507   oappend (s);
12508 }
12509
12510 static void
12511 OP_I (int bytemode, int sizeflag)
12512 {
12513   bfd_signed_vma op;
12514   bfd_signed_vma mask = -1;
12515
12516   switch (bytemode)
12517     {
12518     case b_mode:
12519       FETCH_DATA (the_info, codep + 1);
12520       op = *codep++;
12521       mask = 0xff;
12522       break;
12523     case v_mode:
12524       USED_REX (REX_W);
12525       if (rex & REX_W)
12526         op = get32s ();
12527       else
12528         {
12529           if (sizeflag & DFLAG)
12530             {
12531               op = get32 ();
12532               mask = 0xffffffff;
12533             }
12534           else
12535             {
12536               op = get16 ();
12537               mask = 0xfffff;
12538             }
12539           used_prefixes |= (prefixes & PREFIX_DATA);
12540         }
12541       break;
12542     case d_mode:
12543       mask = 0xffffffff;
12544       op = get32 ();
12545       break;
12546     case w_mode:
12547       mask = 0xfffff;
12548       op = get16 ();
12549       break;
12550     case const_1_mode:
12551       if (intel_syntax)
12552         oappend ("1");
12553       return;
12554     default:
12555       oappend (INTERNAL_DISASSEMBLER_ERROR);
12556       return;
12557     }
12558
12559   op &= mask;
12560   scratchbuf[0] = '$';
12561   print_operand_value (scratchbuf + 1, 1, op);
12562   oappend_maybe_intel (scratchbuf);
12563   scratchbuf[0] = '\0';
12564 }
12565
12566 static void
12567 OP_I64 (int bytemode, int sizeflag)
12568 {
12569   if (bytemode != v_mode || address_mode != mode_64bit || !(rex & REX_W))
12570     {
12571       OP_I (bytemode, sizeflag);
12572       return;
12573     }
12574
12575   USED_REX (REX_W);
12576
12577   scratchbuf[0] = '$';
12578   print_operand_value (scratchbuf + 1, 1, get64 ());
12579   oappend_maybe_intel (scratchbuf);
12580   scratchbuf[0] = '\0';
12581 }
12582
12583 static void
12584 OP_sI (int bytemode, int sizeflag)
12585 {
12586   bfd_signed_vma op;
12587
12588   switch (bytemode)
12589     {
12590     case b_mode:
12591     case b_T_mode:
12592       FETCH_DATA (the_info, codep + 1);
12593       op = *codep++;
12594       if ((op & 0x80) != 0)
12595         op -= 0x100;
12596       if (bytemode == b_T_mode)
12597         {
12598           if (address_mode != mode_64bit
12599               || !((sizeflag & DFLAG) || (rex & REX_W)))
12600             {
12601               /* The operand-size prefix is overridden by a REX prefix.  */
12602               if ((sizeflag & DFLAG) || (rex & REX_W))
12603                 op &= 0xffffffff;
12604               else
12605                 op &= 0xffff;
12606           }
12607         }
12608       else
12609         {
12610           if (!(rex & REX_W))
12611             {
12612               if (sizeflag & DFLAG)
12613                 op &= 0xffffffff;
12614               else
12615                 op &= 0xffff;
12616             }
12617         }
12618       break;
12619     case v_mode:
12620       /* The operand-size prefix is overridden by a REX prefix.  */
12621       if ((sizeflag & DFLAG) || (rex & REX_W))
12622         op = get32s ();
12623       else
12624         op = get16 ();
12625       break;
12626     default:
12627       oappend (INTERNAL_DISASSEMBLER_ERROR);
12628       return;
12629     }
12630
12631   scratchbuf[0] = '$';
12632   print_operand_value (scratchbuf + 1, 1, op);
12633   oappend_maybe_intel (scratchbuf);
12634 }
12635
12636 static void
12637 OP_J (int bytemode, int sizeflag)
12638 {
12639   bfd_vma disp;
12640   bfd_vma mask = -1;
12641   bfd_vma segment = 0;
12642
12643   switch (bytemode)
12644     {
12645     case b_mode:
12646       FETCH_DATA (the_info, codep + 1);
12647       disp = *codep++;
12648       if ((disp & 0x80) != 0)
12649         disp -= 0x100;
12650       break;
12651     case v_mode:
12652     case dqw_mode:
12653       if ((sizeflag & DFLAG)
12654           || (address_mode == mode_64bit
12655               && ((isa64 == intel64 && bytemode != dqw_mode)
12656                   || (rex & REX_W))))
12657         disp = get32s ();
12658       else
12659         {
12660           disp = get16 ();
12661           if ((disp & 0x8000) != 0)
12662             disp -= 0x10000;
12663           /* In 16bit mode, address is wrapped around at 64k within
12664              the same segment.  Otherwise, a data16 prefix on a jump
12665              instruction means that the pc is masked to 16 bits after
12666              the displacement is added!  */
12667           mask = 0xffff;
12668           if ((prefixes & PREFIX_DATA) == 0)
12669             segment = ((start_pc + (codep - start_codep))
12670                        & ~((bfd_vma) 0xffff));
12671         }
12672       if (address_mode != mode_64bit
12673           || (isa64 != intel64 && !(rex & REX_W)))
12674         used_prefixes |= (prefixes & PREFIX_DATA);
12675       break;
12676     default:
12677       oappend (INTERNAL_DISASSEMBLER_ERROR);
12678       return;
12679     }
12680   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
12681   set_op (disp, 0);
12682   print_operand_value (scratchbuf, 1, disp);
12683   oappend (scratchbuf);
12684 }
12685
12686 static void
12687 OP_SEG (int bytemode, int sizeflag)
12688 {
12689   if (bytemode == w_mode)
12690     oappend (names_seg[modrm.reg]);
12691   else
12692     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
12693 }
12694
12695 static void
12696 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
12697 {
12698   int seg, offset;
12699
12700   if (sizeflag & DFLAG)
12701     {
12702       offset = get32 ();
12703       seg = get16 ();
12704     }
12705   else
12706     {
12707       offset = get16 ();
12708       seg = get16 ();
12709     }
12710   used_prefixes |= (prefixes & PREFIX_DATA);
12711   if (intel_syntax)
12712     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
12713   else
12714     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
12715   oappend (scratchbuf);
12716 }
12717
12718 static void
12719 OP_OFF (int bytemode, int sizeflag)
12720 {
12721   bfd_vma off;
12722
12723   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12724     intel_operand_size (bytemode, sizeflag);
12725   append_seg ();
12726
12727   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
12728     off = get32 ();
12729   else
12730     off = get16 ();
12731
12732   if (intel_syntax)
12733     {
12734       if (!active_seg_prefix)
12735         {
12736           oappend (names_seg[ds_reg - es_reg]);
12737           oappend (":");
12738         }
12739     }
12740   print_operand_value (scratchbuf, 1, off);
12741   oappend (scratchbuf);
12742 }
12743
12744 static void
12745 OP_OFF64 (int bytemode, int sizeflag)
12746 {
12747   bfd_vma off;
12748
12749   if (address_mode != mode_64bit
12750       || (prefixes & PREFIX_ADDR))
12751     {
12752       OP_OFF (bytemode, sizeflag);
12753       return;
12754     }
12755
12756   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12757     intel_operand_size (bytemode, sizeflag);
12758   append_seg ();
12759
12760   off = get64 ();
12761
12762   if (intel_syntax)
12763     {
12764       if (!active_seg_prefix)
12765         {
12766           oappend (names_seg[ds_reg - es_reg]);
12767           oappend (":");
12768         }
12769     }
12770   print_operand_value (scratchbuf, 1, off);
12771   oappend (scratchbuf);
12772 }
12773
12774 static void
12775 ptr_reg (int code, int sizeflag)
12776 {
12777   const char *s;
12778
12779   *obufp++ = open_char;
12780   used_prefixes |= (prefixes & PREFIX_ADDR);
12781   if (address_mode == mode_64bit)
12782     {
12783       if (!(sizeflag & AFLAG))
12784         s = names32[code - eAX_reg];
12785       else
12786         s = names64[code - eAX_reg];
12787     }
12788   else if (sizeflag & AFLAG)
12789     s = names32[code - eAX_reg];
12790   else
12791     s = names16[code - eAX_reg];
12792   oappend (s);
12793   *obufp++ = close_char;
12794   *obufp = 0;
12795 }
12796
12797 static void
12798 OP_ESreg (int code, int sizeflag)
12799 {
12800   if (intel_syntax)
12801     {
12802       switch (codep[-1])
12803         {
12804         case 0x6d:      /* insw/insl */
12805           intel_operand_size (z_mode, sizeflag);
12806           break;
12807         case 0xa5:      /* movsw/movsl/movsq */
12808         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
12809         case 0xab:      /* stosw/stosl */
12810         case 0xaf:      /* scasw/scasl */
12811           intel_operand_size (v_mode, sizeflag);
12812           break;
12813         default:
12814           intel_operand_size (b_mode, sizeflag);
12815         }
12816     }
12817   oappend_maybe_intel ("%es:");
12818   ptr_reg (code, sizeflag);
12819 }
12820
12821 static void
12822 OP_DSreg (int code, int sizeflag)
12823 {
12824   if (intel_syntax)
12825     {
12826       switch (codep[-1])
12827         {
12828         case 0x6f:      /* outsw/outsl */
12829           intel_operand_size (z_mode, sizeflag);
12830           break;
12831         case 0xa5:      /* movsw/movsl/movsq */
12832         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
12833         case 0xad:      /* lodsw/lodsl/lodsq */
12834           intel_operand_size (v_mode, sizeflag);
12835           break;
12836         default:
12837           intel_operand_size (b_mode, sizeflag);
12838         }
12839     }
12840   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
12841      default segment register DS is printed.  */
12842   if (!active_seg_prefix)
12843     active_seg_prefix = PREFIX_DS;
12844   append_seg ();
12845   ptr_reg (code, sizeflag);
12846 }
12847
12848 static void
12849 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12850 {
12851   int add;
12852   if (rex & REX_R)
12853     {
12854       USED_REX (REX_R);
12855       add = 8;
12856     }
12857   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
12858     {
12859       all_prefixes[last_lock_prefix] = 0;
12860       used_prefixes |= PREFIX_LOCK;
12861       add = 8;
12862     }
12863   else
12864     add = 0;
12865   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
12866   oappend_maybe_intel (scratchbuf);
12867 }
12868
12869 static void
12870 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12871 {
12872   int add;
12873   USED_REX (REX_R);
12874   if (rex & REX_R)
12875     add = 8;
12876   else
12877     add = 0;
12878   if (intel_syntax)
12879     sprintf (scratchbuf, "dr%d", modrm.reg + add);
12880   else
12881     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
12882   oappend (scratchbuf);
12883 }
12884
12885 static void
12886 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12887 {
12888   sprintf (scratchbuf, "%%tr%d", modrm.reg);
12889   oappend_maybe_intel (scratchbuf);
12890 }
12891
12892 static void
12893 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12894 {
12895   int reg = modrm.reg;
12896   const char **names;
12897
12898   used_prefixes |= (prefixes & PREFIX_DATA);
12899   if (prefixes & PREFIX_DATA)
12900     {
12901       names = names_xmm;
12902       USED_REX (REX_R);
12903       if (rex & REX_R)
12904         reg += 8;
12905     }
12906   else
12907     names = names_mm;
12908   oappend (names[reg]);
12909 }
12910
12911 static void
12912 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
12913 {
12914   int reg = modrm.reg;
12915   const char **names;
12916
12917   USED_REX (REX_R);
12918   if (rex & REX_R)
12919     reg += 8;
12920   if (vex.evex)
12921     {
12922       if (!vex.r)
12923         reg += 16;
12924     }
12925
12926   if (need_vex
12927       && bytemode != xmm_mode
12928       && bytemode != xmmq_mode
12929       && bytemode != evex_half_bcst_xmmq_mode
12930       && bytemode != ymm_mode
12931       && bytemode != tmm_mode
12932       && bytemode != scalar_mode)
12933     {
12934       switch (vex.length)
12935         {
12936         case 128:
12937           names = names_xmm;
12938           break;
12939         case 256:
12940           if (vex.w
12941               || (bytemode != vex_vsib_q_w_dq_mode
12942                   && bytemode != vex_vsib_q_w_d_mode))
12943             names = names_ymm;
12944           else
12945             names = names_xmm;
12946           break;
12947         case 512:
12948           names = names_zmm;
12949           break;
12950         default:
12951           abort ();
12952         }
12953     }
12954   else if (bytemode == xmmq_mode
12955            || bytemode == evex_half_bcst_xmmq_mode)
12956     {
12957       switch (vex.length)
12958         {
12959         case 128:
12960         case 256:
12961           names = names_xmm;
12962           break;
12963         case 512:
12964           names = names_ymm;
12965           break;
12966         default:
12967           abort ();
12968         }
12969     }
12970   else if (bytemode == tmm_mode)
12971     {
12972       modrm.reg = reg;
12973       if (reg >= 8)
12974         {
12975           oappend ("(bad)");
12976           return;
12977         }
12978       names = names_tmm;
12979     }
12980   else if (bytemode == ymm_mode)
12981     names = names_ymm;
12982   else
12983     names = names_xmm;
12984   oappend (names[reg]);
12985 }
12986
12987 static void
12988 OP_EM (int bytemode, int sizeflag)
12989 {
12990   int reg;
12991   const char **names;
12992
12993   if (modrm.mod != 3)
12994     {
12995       if (intel_syntax
12996           && (bytemode == v_mode || bytemode == v_swap_mode))
12997         {
12998           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
12999           used_prefixes |= (prefixes & PREFIX_DATA);
13000         }
13001       OP_E (bytemode, sizeflag);
13002       return;
13003     }
13004
13005   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
13006     swap_operand ();
13007
13008   /* Skip mod/rm byte.  */
13009   MODRM_CHECK;
13010   codep++;
13011   used_prefixes |= (prefixes & PREFIX_DATA);
13012   reg = modrm.rm;
13013   if (prefixes & PREFIX_DATA)
13014     {
13015       names = names_xmm;
13016       USED_REX (REX_B);
13017       if (rex & REX_B)
13018         reg += 8;
13019     }
13020   else
13021     names = names_mm;
13022   oappend (names[reg]);
13023 }
13024
13025 /* cvt* are the only instructions in sse2 which have
13026    both SSE and MMX operands and also have 0x66 prefix
13027    in their opcode. 0x66 was originally used to differentiate
13028    between SSE and MMX instruction(operands). So we have to handle the
13029    cvt* separately using OP_EMC and OP_MXC */
13030 static void
13031 OP_EMC (int bytemode, int sizeflag)
13032 {
13033   if (modrm.mod != 3)
13034     {
13035       if (intel_syntax && bytemode == v_mode)
13036         {
13037           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
13038           used_prefixes |= (prefixes & PREFIX_DATA);
13039         }
13040       OP_E (bytemode, sizeflag);
13041       return;
13042     }
13043
13044   /* Skip mod/rm byte.  */
13045   MODRM_CHECK;
13046   codep++;
13047   used_prefixes |= (prefixes & PREFIX_DATA);
13048   oappend (names_mm[modrm.rm]);
13049 }
13050
13051 static void
13052 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13053 {
13054   used_prefixes |= (prefixes & PREFIX_DATA);
13055   oappend (names_mm[modrm.reg]);
13056 }
13057
13058 static void
13059 OP_EX (int bytemode, int sizeflag)
13060 {
13061   int reg;
13062   const char **names;
13063
13064   /* Skip mod/rm byte.  */
13065   MODRM_CHECK;
13066   codep++;
13067
13068   if (modrm.mod != 3)
13069     {
13070       OP_E_memory (bytemode, sizeflag);
13071       return;
13072     }
13073
13074   reg = modrm.rm;
13075   USED_REX (REX_B);
13076   if (rex & REX_B)
13077     reg += 8;
13078   if (vex.evex)
13079     {
13080       USED_REX (REX_X);
13081       if ((rex & REX_X))
13082         reg += 16;
13083     }
13084
13085   if ((sizeflag & SUFFIX_ALWAYS)
13086       && (bytemode == x_swap_mode
13087           || bytemode == d_swap_mode
13088           || bytemode == q_swap_mode))
13089     swap_operand ();
13090
13091   if (need_vex
13092       && bytemode != xmm_mode
13093       && bytemode != xmmdw_mode
13094       && bytemode != xmmqd_mode
13095       && bytemode != xmm_mb_mode
13096       && bytemode != xmm_mw_mode
13097       && bytemode != xmm_md_mode
13098       && bytemode != xmm_mq_mode
13099       && bytemode != xmmq_mode
13100       && bytemode != evex_half_bcst_xmmq_mode
13101       && bytemode != ymm_mode
13102       && bytemode != tmm_mode
13103       && bytemode != vex_scalar_w_dq_mode)
13104     {
13105       switch (vex.length)
13106         {
13107         case 128:
13108           names = names_xmm;
13109           break;
13110         case 256:
13111           names = names_ymm;
13112           break;
13113         case 512:
13114           names = names_zmm;
13115           break;
13116         default:
13117           abort ();
13118         }
13119     }
13120   else if (bytemode == xmmq_mode
13121            || bytemode == evex_half_bcst_xmmq_mode)
13122     {
13123       switch (vex.length)
13124         {
13125         case 128:
13126         case 256:
13127           names = names_xmm;
13128           break;
13129         case 512:
13130           names = names_ymm;
13131           break;
13132         default:
13133           abort ();
13134         }
13135     }
13136   else if (bytemode == tmm_mode)
13137     {
13138       modrm.rm = reg;
13139       if (reg >= 8)
13140         {
13141           oappend ("(bad)");
13142           return;
13143         }
13144       names = names_tmm;
13145     }
13146   else if (bytemode == ymm_mode)
13147     names = names_ymm;
13148   else
13149     names = names_xmm;
13150   oappend (names[reg]);
13151 }
13152
13153 static void
13154 OP_MS (int bytemode, int sizeflag)
13155 {
13156   if (modrm.mod == 3)
13157     OP_EM (bytemode, sizeflag);
13158   else
13159     BadOp ();
13160 }
13161
13162 static void
13163 OP_XS (int bytemode, int sizeflag)
13164 {
13165   if (modrm.mod == 3)
13166     OP_EX (bytemode, sizeflag);
13167   else
13168     BadOp ();
13169 }
13170
13171 static void
13172 OP_M (int bytemode, int sizeflag)
13173 {
13174   if (modrm.mod == 3)
13175     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
13176     BadOp ();
13177   else
13178     OP_E (bytemode, sizeflag);
13179 }
13180
13181 static void
13182 OP_0f07 (int bytemode, int sizeflag)
13183 {
13184   if (modrm.mod != 3 || modrm.rm != 0)
13185     BadOp ();
13186   else
13187     OP_E (bytemode, sizeflag);
13188 }
13189
13190 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
13191    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
13192
13193 static void
13194 NOP_Fixup1 (int bytemode, int sizeflag)
13195 {
13196   if ((prefixes & PREFIX_DATA) != 0
13197       || (rex != 0
13198           && rex != 0x48
13199           && address_mode == mode_64bit))
13200     OP_REG (bytemode, sizeflag);
13201   else
13202     strcpy (obuf, "nop");
13203 }
13204
13205 static void
13206 NOP_Fixup2 (int bytemode, int sizeflag)
13207 {
13208   if ((prefixes & PREFIX_DATA) != 0
13209       || (rex != 0
13210           && rex != 0x48
13211           && address_mode == mode_64bit))
13212     OP_IMREG (bytemode, sizeflag);
13213 }
13214
13215 static const char *const Suffix3DNow[] = {
13216 /* 00 */        NULL,           NULL,           NULL,           NULL,
13217 /* 04 */        NULL,           NULL,           NULL,           NULL,
13218 /* 08 */        NULL,           NULL,           NULL,           NULL,
13219 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
13220 /* 10 */        NULL,           NULL,           NULL,           NULL,
13221 /* 14 */        NULL,           NULL,           NULL,           NULL,
13222 /* 18 */        NULL,           NULL,           NULL,           NULL,
13223 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
13224 /* 20 */        NULL,           NULL,           NULL,           NULL,
13225 /* 24 */        NULL,           NULL,           NULL,           NULL,
13226 /* 28 */        NULL,           NULL,           NULL,           NULL,
13227 /* 2C */        NULL,           NULL,           NULL,           NULL,
13228 /* 30 */        NULL,           NULL,           NULL,           NULL,
13229 /* 34 */        NULL,           NULL,           NULL,           NULL,
13230 /* 38 */        NULL,           NULL,           NULL,           NULL,
13231 /* 3C */        NULL,           NULL,           NULL,           NULL,
13232 /* 40 */        NULL,           NULL,           NULL,           NULL,
13233 /* 44 */        NULL,           NULL,           NULL,           NULL,
13234 /* 48 */        NULL,           NULL,           NULL,           NULL,
13235 /* 4C */        NULL,           NULL,           NULL,           NULL,
13236 /* 50 */        NULL,           NULL,           NULL,           NULL,
13237 /* 54 */        NULL,           NULL,           NULL,           NULL,
13238 /* 58 */        NULL,           NULL,           NULL,           NULL,
13239 /* 5C */        NULL,           NULL,           NULL,           NULL,
13240 /* 60 */        NULL,           NULL,           NULL,           NULL,
13241 /* 64 */        NULL,           NULL,           NULL,           NULL,
13242 /* 68 */        NULL,           NULL,           NULL,           NULL,
13243 /* 6C */        NULL,           NULL,           NULL,           NULL,
13244 /* 70 */        NULL,           NULL,           NULL,           NULL,
13245 /* 74 */        NULL,           NULL,           NULL,           NULL,
13246 /* 78 */        NULL,           NULL,           NULL,           NULL,
13247 /* 7C */        NULL,           NULL,           NULL,           NULL,
13248 /* 80 */        NULL,           NULL,           NULL,           NULL,
13249 /* 84 */        NULL,           NULL,           NULL,           NULL,
13250 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
13251 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
13252 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
13253 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
13254 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
13255 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
13256 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
13257 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
13258 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
13259 /* AC */        NULL,           NULL,           "pfacc",        NULL,
13260 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
13261 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
13262 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
13263 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
13264 /* C0 */        NULL,           NULL,           NULL,           NULL,
13265 /* C4 */        NULL,           NULL,           NULL,           NULL,
13266 /* C8 */        NULL,           NULL,           NULL,           NULL,
13267 /* CC */        NULL,           NULL,           NULL,           NULL,
13268 /* D0 */        NULL,           NULL,           NULL,           NULL,
13269 /* D4 */        NULL,           NULL,           NULL,           NULL,
13270 /* D8 */        NULL,           NULL,           NULL,           NULL,
13271 /* DC */        NULL,           NULL,           NULL,           NULL,
13272 /* E0 */        NULL,           NULL,           NULL,           NULL,
13273 /* E4 */        NULL,           NULL,           NULL,           NULL,
13274 /* E8 */        NULL,           NULL,           NULL,           NULL,
13275 /* EC */        NULL,           NULL,           NULL,           NULL,
13276 /* F0 */        NULL,           NULL,           NULL,           NULL,
13277 /* F4 */        NULL,           NULL,           NULL,           NULL,
13278 /* F8 */        NULL,           NULL,           NULL,           NULL,
13279 /* FC */        NULL,           NULL,           NULL,           NULL,
13280 };
13281
13282 static void
13283 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13284 {
13285   const char *mnemonic;
13286
13287   FETCH_DATA (the_info, codep + 1);
13288   /* AMD 3DNow! instructions are specified by an opcode suffix in the
13289      place where an 8-bit immediate would normally go.  ie. the last
13290      byte of the instruction.  */
13291   obufp = mnemonicendp;
13292   mnemonic = Suffix3DNow[*codep++ & 0xff];
13293   if (mnemonic)
13294     oappend (mnemonic);
13295   else
13296     {
13297       /* Since a variable sized modrm/sib chunk is between the start
13298          of the opcode (0x0f0f) and the opcode suffix, we need to do
13299          all the modrm processing first, and don't know until now that
13300          we have a bad opcode.  This necessitates some cleaning up.  */
13301       op_out[0][0] = '\0';
13302       op_out[1][0] = '\0';
13303       BadOp ();
13304     }
13305   mnemonicendp = obufp;
13306 }
13307
13308 static const struct op simd_cmp_op[] =
13309 {
13310   { STRING_COMMA_LEN ("eq") },
13311   { STRING_COMMA_LEN ("lt") },
13312   { STRING_COMMA_LEN ("le") },
13313   { STRING_COMMA_LEN ("unord") },
13314   { STRING_COMMA_LEN ("neq") },
13315   { STRING_COMMA_LEN ("nlt") },
13316   { STRING_COMMA_LEN ("nle") },
13317   { STRING_COMMA_LEN ("ord") }
13318 };
13319
13320 static const struct op vex_cmp_op[] =
13321 {
13322   { STRING_COMMA_LEN ("eq_uq") },
13323   { STRING_COMMA_LEN ("nge") },
13324   { STRING_COMMA_LEN ("ngt") },
13325   { STRING_COMMA_LEN ("false") },
13326   { STRING_COMMA_LEN ("neq_oq") },
13327   { STRING_COMMA_LEN ("ge") },
13328   { STRING_COMMA_LEN ("gt") },
13329   { STRING_COMMA_LEN ("true") },
13330   { STRING_COMMA_LEN ("eq_os") },
13331   { STRING_COMMA_LEN ("lt_oq") },
13332   { STRING_COMMA_LEN ("le_oq") },
13333   { STRING_COMMA_LEN ("unord_s") },
13334   { STRING_COMMA_LEN ("neq_us") },
13335   { STRING_COMMA_LEN ("nlt_uq") },
13336   { STRING_COMMA_LEN ("nle_uq") },
13337   { STRING_COMMA_LEN ("ord_s") },
13338   { STRING_COMMA_LEN ("eq_us") },
13339   { STRING_COMMA_LEN ("nge_uq") },
13340   { STRING_COMMA_LEN ("ngt_uq") },
13341   { STRING_COMMA_LEN ("false_os") },
13342   { STRING_COMMA_LEN ("neq_os") },
13343   { STRING_COMMA_LEN ("ge_oq") },
13344   { STRING_COMMA_LEN ("gt_oq") },
13345   { STRING_COMMA_LEN ("true_us") },
13346 };
13347
13348 static void
13349 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13350 {
13351   unsigned int cmp_type;
13352
13353   FETCH_DATA (the_info, codep + 1);
13354   cmp_type = *codep++ & 0xff;
13355   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
13356     {
13357       char suffix [3];
13358       char *p = mnemonicendp - 2;
13359       suffix[0] = p[0];
13360       suffix[1] = p[1];
13361       suffix[2] = '\0';
13362       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13363       mnemonicendp += simd_cmp_op[cmp_type].len;
13364     }
13365   else if (need_vex
13366            && cmp_type < ARRAY_SIZE (simd_cmp_op) + ARRAY_SIZE (vex_cmp_op))
13367     {
13368       char suffix [3];
13369       char *p = mnemonicendp - 2;
13370       suffix[0] = p[0];
13371       suffix[1] = p[1];
13372       suffix[2] = '\0';
13373       cmp_type -= ARRAY_SIZE (simd_cmp_op);
13374       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
13375       mnemonicendp += vex_cmp_op[cmp_type].len;
13376     }
13377   else
13378     {
13379       /* We have a reserved extension byte.  Output it directly.  */
13380       scratchbuf[0] = '$';
13381       print_operand_value (scratchbuf + 1, 1, cmp_type);
13382       oappend_maybe_intel (scratchbuf);
13383       scratchbuf[0] = '\0';
13384     }
13385 }
13386
13387 static void
13388 OP_Mwait (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13389 {
13390   /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx  */
13391   if (!intel_syntax)
13392     {
13393       strcpy (op_out[0], names32[0]);
13394       strcpy (op_out[1], names32[1]);
13395       if (bytemode == eBX_reg)
13396         strcpy (op_out[2], names32[3]);
13397       two_source_ops = 1;
13398     }
13399   /* Skip mod/rm byte.  */
13400   MODRM_CHECK;
13401   codep++;
13402 }
13403
13404 static void
13405 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
13406             int sizeflag ATTRIBUTE_UNUSED)
13407 {
13408   /* monitor %{e,r,}ax,%ecx,%edx"  */
13409   if (!intel_syntax)
13410     {
13411       const char **names = (address_mode == mode_64bit
13412                             ? names64 : names32);
13413
13414       if (prefixes & PREFIX_ADDR)
13415         {
13416           /* Remove "addr16/addr32".  */
13417           all_prefixes[last_addr_prefix] = 0;
13418           names = (address_mode != mode_32bit
13419                    ? names32 : names16);
13420           used_prefixes |= PREFIX_ADDR;
13421         }
13422       else if (address_mode == mode_16bit)
13423         names = names16;
13424       strcpy (op_out[0], names[0]);
13425       strcpy (op_out[1], names32[1]);
13426       strcpy (op_out[2], names32[2]);
13427       two_source_ops = 1;
13428     }
13429   /* Skip mod/rm byte.  */
13430   MODRM_CHECK;
13431   codep++;
13432 }
13433
13434 static void
13435 BadOp (void)
13436 {
13437   /* Throw away prefixes and 1st. opcode byte.  */
13438   codep = insn_codep + 1;
13439   oappend ("(bad)");
13440 }
13441
13442 static void
13443 REP_Fixup (int bytemode, int sizeflag)
13444 {
13445   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
13446      lods and stos.  */
13447   if (prefixes & PREFIX_REPZ)
13448     all_prefixes[last_repz_prefix] = REP_PREFIX;
13449
13450   switch (bytemode)
13451     {
13452     case al_reg:
13453     case eAX_reg:
13454     case indir_dx_reg:
13455       OP_IMREG (bytemode, sizeflag);
13456       break;
13457     case eDI_reg:
13458       OP_ESreg (bytemode, sizeflag);
13459       break;
13460     case eSI_reg:
13461       OP_DSreg (bytemode, sizeflag);
13462       break;
13463     default:
13464       abort ();
13465       break;
13466     }
13467 }
13468
13469 static void
13470 SEP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13471 {
13472   if ( isa64 != amd64 )
13473     return;
13474
13475   obufp = obuf;
13476   BadOp ();
13477   mnemonicendp = obufp;
13478   ++codep;
13479 }
13480
13481 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
13482    "bnd".  */
13483
13484 static void
13485 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13486 {
13487   if (prefixes & PREFIX_REPNZ)
13488     all_prefixes[last_repnz_prefix] = BND_PREFIX;
13489 }
13490
13491 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
13492    "notrack".  */
13493
13494 static void
13495 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
13496                int sizeflag ATTRIBUTE_UNUSED)
13497 {
13498   if (active_seg_prefix == PREFIX_DS
13499       && (address_mode != mode_64bit || last_data_prefix < 0))
13500     {
13501       /* NOTRACK prefix is only valid on indirect branch instructions.
13502          NB: DATA prefix is unsupported for Intel64.  */
13503       active_seg_prefix = 0;
13504       all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
13505     }
13506 }
13507
13508 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
13509    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
13510  */
13511
13512 static void
13513 HLE_Fixup1 (int bytemode, int sizeflag)
13514 {
13515   if (modrm.mod != 3
13516       && (prefixes & PREFIX_LOCK) != 0)
13517     {
13518       if (prefixes & PREFIX_REPZ)
13519         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
13520       if (prefixes & PREFIX_REPNZ)
13521         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
13522     }
13523
13524   OP_E (bytemode, sizeflag);
13525 }
13526
13527 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
13528    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
13529  */
13530
13531 static void
13532 HLE_Fixup2 (int bytemode, int sizeflag)
13533 {
13534   if (modrm.mod != 3)
13535     {
13536       if (prefixes & PREFIX_REPZ)
13537         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
13538       if (prefixes & PREFIX_REPNZ)
13539         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
13540     }
13541
13542   OP_E (bytemode, sizeflag);
13543 }
13544
13545 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
13546    "xrelease" for memory operand.  No check for LOCK prefix.   */
13547
13548 static void
13549 HLE_Fixup3 (int bytemode, int sizeflag)
13550 {
13551   if (modrm.mod != 3
13552       && last_repz_prefix > last_repnz_prefix
13553       && (prefixes & PREFIX_REPZ) != 0)
13554     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
13555
13556   OP_E (bytemode, sizeflag);
13557 }
13558
13559 static void
13560 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
13561 {
13562   USED_REX (REX_W);
13563   if (rex & REX_W)
13564     {
13565       /* Change cmpxchg8b to cmpxchg16b.  */
13566       char *p = mnemonicendp - 2;
13567       mnemonicendp = stpcpy (p, "16b");
13568       bytemode = o_mode;
13569     }
13570   else if ((prefixes & PREFIX_LOCK) != 0)
13571     {
13572       if (prefixes & PREFIX_REPZ)
13573         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
13574       if (prefixes & PREFIX_REPNZ)
13575         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
13576     }
13577
13578   OP_M (bytemode, sizeflag);
13579 }
13580
13581 static void
13582 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
13583 {
13584   const char **names;
13585
13586   if (need_vex)
13587     {
13588       switch (vex.length)
13589         {
13590         case 128:
13591           names = names_xmm;
13592           break;
13593         case 256:
13594           names = names_ymm;
13595           break;
13596         default:
13597           abort ();
13598         }
13599     }
13600   else
13601     names = names_xmm;
13602   oappend (names[reg]);
13603 }
13604
13605 static void
13606 FXSAVE_Fixup (int bytemode, int sizeflag)
13607 {
13608   /* Add proper suffix to "fxsave" and "fxrstor".  */
13609   USED_REX (REX_W);
13610   if (rex & REX_W)
13611     {
13612       char *p = mnemonicendp;
13613       *p++ = '6';
13614       *p++ = '4';
13615       *p = '\0';
13616       mnemonicendp = p;
13617     }
13618   OP_M (bytemode, sizeflag);
13619 }
13620
13621 /* Display the destination register operand for instructions with
13622    VEX. */
13623
13624 static void
13625 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13626 {
13627   int reg;
13628   const char **names;
13629
13630   if (!need_vex)
13631     abort ();
13632
13633   reg = vex.register_specifier;
13634   vex.register_specifier = 0;
13635   if (address_mode != mode_64bit)
13636     reg &= 7;
13637   else if (vex.evex && !vex.v)
13638     reg += 16;
13639
13640   if (bytemode == vex_scalar_mode)
13641     {
13642       oappend (names_xmm[reg]);
13643       return;
13644     }
13645
13646   if (bytemode == tmm_mode)
13647     {
13648       /* All 3 TMM registers must be distinct.  */
13649       if (reg >= 8)
13650         oappend ("(bad)");
13651       else
13652         {
13653           /* This must be the 3rd operand.  */
13654           if (obufp != op_out[2])
13655             abort ();
13656           oappend (names_tmm[reg]);
13657           if (reg == modrm.reg || reg == modrm.rm)
13658             strcpy (obufp, "/(bad)");
13659         }
13660
13661       if (modrm.reg == modrm.rm || modrm.reg == reg || modrm.rm == reg)
13662         {
13663           if (modrm.reg <= 8
13664               && (modrm.reg == modrm.rm || modrm.reg == reg))
13665             strcat (op_out[0], "/(bad)");
13666           if (modrm.rm <= 8
13667               && (modrm.rm == modrm.reg || modrm.rm == reg))
13668             strcat (op_out[1], "/(bad)");
13669         }
13670
13671       return;
13672     }
13673
13674   switch (vex.length)
13675     {
13676     case 128:
13677       switch (bytemode)
13678         {
13679         case vex_mode:
13680         case vex_vsib_q_w_dq_mode:
13681         case vex_vsib_q_w_d_mode:
13682           names = names_xmm;
13683           break;
13684         case dq_mode:
13685           if (rex & REX_W)
13686             names = names64;
13687           else
13688             names = names32;
13689           break;
13690         case mask_bd_mode:
13691         case mask_mode:
13692           if (reg > 0x7)
13693             {
13694               oappend ("(bad)");
13695               return;
13696             }
13697           names = names_mask;
13698           break;
13699         default:
13700           abort ();
13701           return;
13702         }
13703       break;
13704     case 256:
13705       switch (bytemode)
13706         {
13707         case vex_mode:
13708           names = names_ymm;
13709           break;
13710         case vex_vsib_q_w_dq_mode:
13711         case vex_vsib_q_w_d_mode:
13712           names = vex.w ? names_ymm : names_xmm;
13713           break;
13714         case mask_bd_mode:
13715         case mask_mode:
13716           if (reg > 0x7)
13717             {
13718               oappend ("(bad)");
13719               return;
13720             }
13721           names = names_mask;
13722           break;
13723         default:
13724           /* See PR binutils/20893 for a reproducer.  */
13725           oappend ("(bad)");
13726           return;
13727         }
13728       break;
13729     case 512:
13730       names = names_zmm;
13731       break;
13732     default:
13733       abort ();
13734       break;
13735     }
13736   oappend (names[reg]);
13737 }
13738
13739 static void
13740 OP_VexR (int bytemode, int sizeflag)
13741 {
13742   if (modrm.mod == 3)
13743     OP_VEX (bytemode, sizeflag);
13744 }
13745
13746 static void
13747 OP_VexW (int bytemode, int sizeflag)
13748 {
13749   OP_VEX (bytemode, sizeflag);
13750
13751   if (vex.w)
13752     {
13753       /* Swap 2nd and 3rd operands.  */
13754       strcpy (scratchbuf, op_out[2]);
13755       strcpy (op_out[2], op_out[1]);
13756       strcpy (op_out[1], scratchbuf);
13757     }
13758 }
13759
13760 static void
13761 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13762 {
13763   int reg;
13764   const char **names = names_xmm;
13765
13766   FETCH_DATA (the_info, codep + 1);
13767   reg = *codep++;
13768
13769   if (bytemode != x_mode && bytemode != scalar_mode)
13770     abort ();
13771
13772   reg >>= 4;
13773   if (address_mode != mode_64bit)
13774     reg &= 7;
13775
13776   if (bytemode == x_mode && vex.length == 256)
13777     names = names_ymm;
13778
13779   oappend (names[reg]);
13780
13781   if (vex.w)
13782     {
13783       /* Swap 3rd and 4th operands.  */
13784       strcpy (scratchbuf, op_out[3]);
13785       strcpy (op_out[3], op_out[2]);
13786       strcpy (op_out[2], scratchbuf);
13787     }
13788 }
13789
13790 static void
13791 OP_VexI4 (int bytemode ATTRIBUTE_UNUSED,
13792           int sizeflag ATTRIBUTE_UNUSED)
13793 {
13794   scratchbuf[0] = '$';
13795   print_operand_value (scratchbuf + 1, 1, codep[-1] & 0xf);
13796   oappend_maybe_intel (scratchbuf);
13797 }
13798
13799 static void
13800 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
13801              int sizeflag ATTRIBUTE_UNUSED)
13802 {
13803   unsigned int cmp_type;
13804
13805   if (!vex.evex)
13806     abort ();
13807
13808   FETCH_DATA (the_info, codep + 1);
13809   cmp_type = *codep++ & 0xff;
13810   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
13811      If it's the case, print suffix, otherwise - print the immediate.  */
13812   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
13813       && cmp_type != 3
13814       && cmp_type != 7)
13815     {
13816       char suffix [3];
13817       char *p = mnemonicendp - 2;
13818
13819       /* vpcmp* can have both one- and two-lettered suffix.  */
13820       if (p[0] == 'p')
13821         {
13822           p++;
13823           suffix[0] = p[0];
13824           suffix[1] = '\0';
13825         }
13826       else
13827         {
13828           suffix[0] = p[0];
13829           suffix[1] = p[1];
13830           suffix[2] = '\0';
13831         }
13832
13833       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13834       mnemonicendp += simd_cmp_op[cmp_type].len;
13835     }
13836   else
13837     {
13838       /* We have a reserved extension byte.  Output it directly.  */
13839       scratchbuf[0] = '$';
13840       print_operand_value (scratchbuf + 1, 1, cmp_type);
13841       oappend_maybe_intel (scratchbuf);
13842       scratchbuf[0] = '\0';
13843     }
13844 }
13845
13846 static const struct op xop_cmp_op[] =
13847 {
13848   { STRING_COMMA_LEN ("lt") },
13849   { STRING_COMMA_LEN ("le") },
13850   { STRING_COMMA_LEN ("gt") },
13851   { STRING_COMMA_LEN ("ge") },
13852   { STRING_COMMA_LEN ("eq") },
13853   { STRING_COMMA_LEN ("neq") },
13854   { STRING_COMMA_LEN ("false") },
13855   { STRING_COMMA_LEN ("true") }
13856 };
13857
13858 static void
13859 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
13860              int sizeflag ATTRIBUTE_UNUSED)
13861 {
13862   unsigned int cmp_type;
13863
13864   FETCH_DATA (the_info, codep + 1);
13865   cmp_type = *codep++ & 0xff;
13866   if (cmp_type < ARRAY_SIZE (xop_cmp_op))
13867     {
13868       char suffix[3];
13869       char *p = mnemonicendp - 2;
13870
13871       /* vpcom* can have both one- and two-lettered suffix.  */
13872       if (p[0] == 'm')
13873         {
13874           p++;
13875           suffix[0] = p[0];
13876           suffix[1] = '\0';
13877         }
13878       else
13879         {
13880           suffix[0] = p[0];
13881           suffix[1] = p[1];
13882           suffix[2] = '\0';
13883         }
13884
13885       sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
13886       mnemonicendp += xop_cmp_op[cmp_type].len;
13887     }
13888   else
13889     {
13890       /* We have a reserved extension byte.  Output it directly.  */
13891       scratchbuf[0] = '$';
13892       print_operand_value (scratchbuf + 1, 1, cmp_type);
13893       oappend_maybe_intel (scratchbuf);
13894       scratchbuf[0] = '\0';
13895     }
13896 }
13897
13898 static const struct op pclmul_op[] =
13899 {
13900   { STRING_COMMA_LEN ("lql") },
13901   { STRING_COMMA_LEN ("hql") },
13902   { STRING_COMMA_LEN ("lqh") },
13903   { STRING_COMMA_LEN ("hqh") }
13904 };
13905
13906 static void
13907 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
13908               int sizeflag ATTRIBUTE_UNUSED)
13909 {
13910   unsigned int pclmul_type;
13911
13912   FETCH_DATA (the_info, codep + 1);
13913   pclmul_type = *codep++ & 0xff;
13914   switch (pclmul_type)
13915     {
13916     case 0x10:
13917       pclmul_type = 2;
13918       break;
13919     case 0x11:
13920       pclmul_type = 3;
13921       break;
13922     default:
13923       break;
13924     }
13925   if (pclmul_type < ARRAY_SIZE (pclmul_op))
13926     {
13927       char suffix [4];
13928       char *p = mnemonicendp - 3;
13929       suffix[0] = p[0];
13930       suffix[1] = p[1];
13931       suffix[2] = p[2];
13932       suffix[3] = '\0';
13933       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
13934       mnemonicendp += pclmul_op[pclmul_type].len;
13935     }
13936   else
13937     {
13938       /* We have a reserved extension byte.  Output it directly.  */
13939       scratchbuf[0] = '$';
13940       print_operand_value (scratchbuf + 1, 1, pclmul_type);
13941       oappend_maybe_intel (scratchbuf);
13942       scratchbuf[0] = '\0';
13943     }
13944 }
13945
13946 static void
13947 MOVSXD_Fixup (int bytemode, int sizeflag)
13948 {
13949   /* Add proper suffix to "movsxd".  */
13950   char *p = mnemonicendp;
13951
13952   switch (bytemode)
13953     {
13954     case movsxd_mode:
13955       if (intel_syntax)
13956         {
13957           *p++ = 'x';
13958           *p++ = 'd';
13959           goto skip;
13960         }
13961
13962       USED_REX (REX_W);
13963       if (rex & REX_W)
13964         {
13965           *p++ = 'l';
13966           *p++ = 'q';
13967         }
13968       else
13969         {
13970           *p++ = 'x';
13971           *p++ = 'd';
13972         }
13973       break;
13974     default:
13975       oappend (INTERNAL_DISASSEMBLER_ERROR);
13976       break;
13977     }
13978
13979  skip:
13980   mnemonicendp = p;
13981   *p = '\0';
13982   OP_E (bytemode, sizeflag);
13983 }
13984
13985 static void
13986 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13987 {
13988   if (!vex.evex
13989       || (bytemode != mask_mode && bytemode != mask_bd_mode))
13990     abort ();
13991
13992   USED_REX (REX_R);
13993   if ((rex & REX_R) != 0 || !vex.r)
13994     {
13995       BadOp ();
13996       return;
13997     }
13998
13999   oappend (names_mask [modrm.reg]);
14000 }
14001
14002 static void
14003 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
14004 {
14005   if (modrm.mod == 3 && vex.b)
14006     switch (bytemode)
14007       {
14008       case evex_rounding_64_mode:
14009         if (address_mode != mode_64bit)
14010           {
14011             oappend ("(bad)");
14012             break;
14013           }
14014         /* Fall through.  */
14015       case evex_rounding_mode:
14016         oappend (names_rounding[vex.ll]);
14017         break;
14018       case evex_sae_mode:
14019         oappend ("{sae}");
14020         break;
14021       default:
14022         abort ();
14023         break;
14024       }
14025 }