opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2022 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "disassemble.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40 #include "safe-ctype.h"
  41
  42 #include <setjmp.h>
  43 typedef struct instr_info instr_info;
  44
  45 static int print_insn (bfd_vma, instr_info *);
  46 static void dofloat (instr_info *, int);
  47 static void OP_ST (instr_info *, int, int);
  48 static void OP_STi (instr_info *, int, int);
  49 static int putop (instr_info *, const char *, int);
  50 static void oappend (instr_info *, const char *);
  51 static void append_seg (instr_info *);
  52 static void OP_indirE (instr_info *, int, int);
  53 static void print_operand_value (instr_info *, char *, int, bfd_vma);
  54 static void OP_E_memory (instr_info *, int, int);
  55 static void print_displacement (instr_info *, char *, bfd_vma);
  56 static void OP_E (instr_info *, int, int);
  57 static void OP_G (instr_info *, int, int);
  58 static bfd_vma get64 (instr_info *);
  59 static bfd_signed_vma get32 (instr_info *);
  60 static bfd_signed_vma get32s (instr_info *);
  61 static int get16 (instr_info *);
  62 static void set_op (instr_info *, bfd_vma, int);
  63 static void OP_Skip_MODRM (instr_info *, int, int);
  64 static void OP_REG (instr_info *, int, int);
  65 static void OP_IMREG (instr_info *, int, int);
  66 static void OP_I (instr_info *, int, int);
  67 static void OP_I64 (instr_info *, int, int);
  68 static void OP_sI (instr_info *, int, int);
  69 static void OP_J (instr_info *, int, int);
  70 static void OP_SEG (instr_info *, int, int);
  71 static void OP_DIR (instr_info *, int, int);
  72 static void OP_OFF (instr_info *, int, int);
  73 static void OP_OFF64 (instr_info *, int, int);
  74 static void ptr_reg (instr_info *, int, int);
  75 static void OP_ESreg (instr_info *, int, int);
  76 static void OP_DSreg (instr_info *, int, int);
  77 static void OP_C (instr_info *, int, int);
  78 static void OP_D (instr_info *, int, int);
  79 static void OP_T (instr_info *, int, int);
  80 static void OP_MMX (instr_info *, int, int);
  81 static void OP_XMM (instr_info *, int, int);
  82 static void OP_EM (instr_info *, int, int);
  83 static void OP_EX (instr_info *, int, int);
  84 static void OP_EMC (instr_info *, int,int);
  85 static void OP_MXC (instr_info *, int,int);
  86 static void OP_MS (instr_info *, int, int);
  87 static void OP_XS (instr_info *, int, int);
  88 static void OP_M (instr_info *, int, int);
  89 static void OP_VEX (instr_info *, int, int);
  90 static void OP_VexR (instr_info *, int, int);
  91 static void OP_VexW (instr_info *, int, int);
  92 static void OP_Rounding (instr_info *, int, int);
  93 static void OP_REG_VexI4 (instr_info *, int, int);
  94 static void OP_VexI4 (instr_info *, int, int);
  95 static void PCLMUL_Fixup (instr_info *, int, int);
  96 static void VPCMP_Fixup (instr_info *, int, int);
  97 static void VPCOM_Fixup (instr_info *, int, int);
  98 static void OP_0f07 (instr_info *, int, int);
  99 static void OP_Monitor (instr_info *, int, int);
 100 static void OP_Mwait (instr_info *, int, int);
 101 static void NOP_Fixup (instr_info *, int, int);
 102 static void OP_3DNowSuffix (instr_info *, int, int);
 103 static void CMP_Fixup (instr_info *, int, int);
 104 static void BadOp (instr_info *);
 105 static void REP_Fixup (instr_info *, int, int);
 106 static void SEP_Fixup (instr_info *, int, int);
 107 static void BND_Fixup (instr_info *, int, int);
 108 static void NOTRACK_Fixup (instr_info *, int, int);
 109 static void HLE_Fixup1 (instr_info *, int, int);
 110 static void HLE_Fixup2 (instr_info *, int, int);
 111 static void HLE_Fixup3 (instr_info *, int, int);
 112 static void CMPXCHG8B_Fixup (instr_info *, int, int);
 113 static void XMM_Fixup (instr_info *, int, int);
 114 static void FXSAVE_Fixup (instr_info *, int, int);
 115
 116 static void MOVSXD_Fixup (instr_info *, int, int);
 117 static void DistinctDest_Fixup (instr_info *, int, int);
 118
 119 struct dis_private {
 120   /* Points to first byte not fetched.  */
 121   bfd_byte *max_fetched;
 122   bfd_byte the_buffer[MAX_MNEM_SIZE];
 123   bfd_vma insn_start;
 124   int orig_sizeflag;
 125   OPCODES_SIGJMP_BUF bailout;
 126 };
 127
 128 enum address_mode
 129 {
 130   mode_16bit,
 131   mode_32bit,
 132   mode_64bit
 133 };
 134
 135 enum x86_64_isa
 136 {
 137   amd64 = 1,
 138   intel64
 139 };
 140
 141 struct instr_info
 142 {
 143   enum address_mode address_mode;
 144
 145   /* Flags for the prefixes for the current instruction.  See below.  */
 146   int prefixes;
 147
 148   /* REX prefix the current instruction.  See below.  */
 149   unsigned char rex;
 150   /* Bits of REX we've already used.  */
 151   unsigned char rex_used;
 152
 153   bool need_modrm;
 154   bool need_vex;
 155   bool has_sib;
 156
 157   /* Flags for ins->prefixes which we somehow handled when printing the
 158      current instruction.  */
 159   int used_prefixes;
 160
 161   /* Flags for EVEX bits which we somehow handled when printing the
 162      current instruction.  */
 163   int evex_used;
 164
 165   char obuf[100];
 166   char *obufp;
 167   char *mnemonicendp;
 168   char scratchbuf[100];
 169   unsigned char *start_codep;
 170   unsigned char *insn_codep;
 171   unsigned char *codep;
 172   unsigned char *end_codep;
 173   int last_lock_prefix;
 174   int last_repz_prefix;
 175   int last_repnz_prefix;
 176   int last_data_prefix;
 177   int last_addr_prefix;
 178   int last_rex_prefix;
 179   int last_seg_prefix;
 180   int fwait_prefix;
 181   /* The active segment register prefix.  */
 182   int active_seg_prefix;
 183
 184 #define MAX_CODE_LENGTH 15
 185   /* We can up to 14 ins->prefixes since the maximum instruction length is
 186      15bytes.  */
 187   int all_prefixes[MAX_CODE_LENGTH - 1];
 188   disassemble_info *info;
 189
 190   struct
 191   {
 192     int mod;
 193     int reg;
 194     int rm;
 195   }
 196   modrm;
 197
 198   struct
 199   {
 200     int scale;
 201     int index;
 202     int base;
 203   }
 204   sib;
 205
 206   struct
 207   {
 208     int register_specifier;
 209     int length;
 210     int prefix;
 211     int mask_register_specifier;
 212     int ll;
 213     bool w;
 214     bool evex;
 215     bool r;
 216     bool v;
 217     bool zeroing;
 218     bool b;
 219     bool no_broadcast;
 220   }
 221   vex;
 222
 223   /* Remember if the current op is a jump instruction.  */
 224   bool op_is_jump;
 225
 226   bool two_source_ops;
 227
 228   unsigned char op_ad;
 229   signed char op_index[MAX_OPERANDS];
 230   char op_out[MAX_OPERANDS][100];
 231   bfd_vma op_address[MAX_OPERANDS];
 232   bfd_vma op_riprel[MAX_OPERANDS];
 233   bfd_vma start_pc;
 234
 235   /* On the 386's of 1988, the maximum length of an instruction is 15 bytes.
 236    *   (see topic "Redundant ins->prefixes" in the "Differences from 8086"
 237    *   section of the "Virtual 8086 Mode" chapter.)
 238    * 'pc' should be the address of this instruction, it will
 239    *   be used to print the target address if this is a relative jump or call
 240    * The function returns the length of this instruction in bytes.
 241    */
 242   char intel_syntax;
 243   bool intel_mnemonic;
 244   char open_char;
 245   char close_char;
 246   char separator_char;
 247   char scale_char;
 248
 249   enum x86_64_isa isa64;
 250
 251 };
 252
 253 /* Mark parts used in the REX prefix.  When we are testing for
 254    empty prefix (for 8bit register REX extension), just mask it
 255    out.  Otherwise test for REX bit is excuse for existence of REX
 256    only in case value is nonzero.  */
 257 #define USED_REX(value)                                 \
 258   {                                                     \
 259     if (value)                                          \
 260       {                                                 \
 261         if ((ins->rex & value))                         \
 262           ins->rex_used |= (value) | REX_OPCODE;        \
 263       }                                                 \
 264     else                                                \
 265       ins->rex_used |= REX_OPCODE;                      \
 266   }
 267
 268
 269 #define EVEX_b_used 1
 270
 271 /* Flags stored in PREFIXES.  */
 272 #define PREFIX_REPZ 1
 273 #define PREFIX_REPNZ 2
 274 #define PREFIX_LOCK 4
 275 #define PREFIX_CS 8
 276 #define PREFIX_SS 0x10
 277 #define PREFIX_DS 0x20
 278 #define PREFIX_ES 0x40
 279 #define PREFIX_FS 0x80
 280 #define PREFIX_GS 0x100
 281 #define PREFIX_DATA 0x200
 282 #define PREFIX_ADDR 0x400
 283 #define PREFIX_FWAIT 0x800
 284
 285 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 286    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 287    on error.  */
 288 #define FETCH_DATA(info, addr) \
 289   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 290    ? 1 : fetch_data ((info), (addr)))
 291
 292 static int
 293 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 294 {
 295   int status;
 296   struct dis_private *priv = (struct dis_private *) info->private_data;
 297   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 298
 299   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 300     status = (*info->read_memory_func) (start,
 301                                         priv->max_fetched,
 302                                         addr - priv->max_fetched,
 303                                         info);
 304   else
 305     status = -1;
 306   if (status != 0)
 307     {
 308       /* If we did manage to read at least one byte, then
 309          print_insn_i386 will do something sensible.  Otherwise, print
 310          an error.  We do that here because this is where we know
 311          STATUS.  */
 312       if (priv->max_fetched == priv->the_buffer)
 313         (*info->memory_error_func) (status, start, info);
 314       OPCODES_SIGLONGJMP (priv->bailout, 1);
 315     }
 316   else
 317     priv->max_fetched = addr;
 318   return 1;
 319 }
 320
 321 /* Possible values for prefix requirement.  */
 322 #define PREFIX_IGNORED_SHIFT    16
 323 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 324 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 325 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 326 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 327 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 328
 329 /* Opcode prefixes.  */
 330 #define PREFIX_OPCODE           (PREFIX_REPZ \
 331                                  | PREFIX_REPNZ \
 332                                  | PREFIX_DATA)
 333
 334 /* Prefixes ignored.  */
 335 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 336                                  | PREFIX_IGNORED_REPNZ \
 337                                  | PREFIX_IGNORED_DATA)
 338
 339 #define XX { NULL, 0 }
 340 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 341
 342 #define Eb { OP_E, b_mode }
 343 #define Ebnd { OP_E, bnd_mode }
 344 #define EbS { OP_E, b_swap_mode }
 345 #define EbndS { OP_E, bnd_swap_mode }
 346 #define Ev { OP_E, v_mode }
 347 #define Eva { OP_E, va_mode }
 348 #define Ev_bnd { OP_E, v_bnd_mode }
 349 #define EvS { OP_E, v_swap_mode }
 350 #define Ed { OP_E, d_mode }
 351 #define Edq { OP_E, dq_mode }
 352 #define Edb { OP_E, db_mode }
 353 #define Edw { OP_E, dw_mode }
 354 #define Eq { OP_E, q_mode }
 355 #define indirEv { OP_indirE, indir_v_mode }
 356 #define indirEp { OP_indirE, f_mode }
 357 #define stackEv { OP_E, stack_v_mode }
 358 #define Em { OP_E, m_mode }
 359 #define Ew { OP_E, w_mode }
 360 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 361 #define Ma { OP_M, a_mode }
 362 #define Mb { OP_M, b_mode }
 363 #define Md { OP_M, d_mode }
 364 #define Mo { OP_M, o_mode }
 365 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 366 #define Mq { OP_M, q_mode }
 367 #define Mv { OP_M, v_mode }
 368 #define Mv_bnd { OP_M, v_bndmk_mode }
 369 #define Mx { OP_M, x_mode }
 370 #define Mxmm { OP_M, xmm_mode }
 371 #define Gb { OP_G, b_mode }
 372 #define Gbnd { OP_G, bnd_mode }
 373 #define Gv { OP_G, v_mode }
 374 #define Gd { OP_G, d_mode }
 375 #define Gdq { OP_G, dq_mode }
 376 #define Gm { OP_G, m_mode }
 377 #define Gva { OP_G, va_mode }
 378 #define Gw { OP_G, w_mode }
 379 #define Ib { OP_I, b_mode }
 380 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 381 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 382 #define Iv { OP_I, v_mode }
 383 #define sIv { OP_sI, v_mode }
 384 #define Iv64 { OP_I64, v_mode }
 385 #define Id { OP_I, d_mode }
 386 #define Iw { OP_I, w_mode }
 387 #define I1 { OP_I, const_1_mode }
 388 #define Jb { OP_J, b_mode }
 389 #define Jv { OP_J, v_mode }
 390 #define Jdqw { OP_J, dqw_mode }
 391 #define Cm { OP_C, m_mode }
 392 #define Dm { OP_D, m_mode }
 393 #define Td { OP_T, d_mode }
 394 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 395
 396 #define RMeAX { OP_REG, eAX_reg }
 397 #define RMeBX { OP_REG, eBX_reg }
 398 #define RMeCX { OP_REG, eCX_reg }
 399 #define RMeDX { OP_REG, eDX_reg }
 400 #define RMeSP { OP_REG, eSP_reg }
 401 #define RMeBP { OP_REG, eBP_reg }
 402 #define RMeSI { OP_REG, eSI_reg }
 403 #define RMeDI { OP_REG, eDI_reg }
 404 #define RMrAX { OP_REG, rAX_reg }
 405 #define RMrBX { OP_REG, rBX_reg }
 406 #define RMrCX { OP_REG, rCX_reg }
 407 #define RMrDX { OP_REG, rDX_reg }
 408 #define RMrSP { OP_REG, rSP_reg }
 409 #define RMrBP { OP_REG, rBP_reg }
 410 #define RMrSI { OP_REG, rSI_reg }
 411 #define RMrDI { OP_REG, rDI_reg }
 412 #define RMAL { OP_REG, al_reg }
 413 #define RMCL { OP_REG, cl_reg }
 414 #define RMDL { OP_REG, dl_reg }
 415 #define RMBL { OP_REG, bl_reg }
 416 #define RMAH { OP_REG, ah_reg }
 417 #define RMCH { OP_REG, ch_reg }
 418 #define RMDH { OP_REG, dh_reg }
 419 #define RMBH { OP_REG, bh_reg }
 420 #define RMAX { OP_REG, ax_reg }
 421 #define RMDX { OP_REG, dx_reg }
 422
 423 #define eAX { OP_IMREG, eAX_reg }
 424 #define AL { OP_IMREG, al_reg }
 425 #define CL { OP_IMREG, cl_reg }
 426 #define zAX { OP_IMREG, z_mode_ax_reg }
 427 #define indirDX { OP_IMREG, indir_dx_reg }
 428
 429 #define Sw { OP_SEG, w_mode }
 430 #define Sv { OP_SEG, v_mode }
 431 #define Ap { OP_DIR, 0 }
 432 #define Ob { OP_OFF64, b_mode }
 433 #define Ov { OP_OFF64, v_mode }
 434 #define Xb { OP_DSreg, eSI_reg }
 435 #define Xv { OP_DSreg, eSI_reg }
 436 #define Xz { OP_DSreg, eSI_reg }
 437 #define Yb { OP_ESreg, eDI_reg }
 438 #define Yv { OP_ESreg, eDI_reg }
 439 #define DSBX { OP_DSreg, eBX_reg }
 440
 441 #define es { OP_REG, es_reg }
 442 #define ss { OP_REG, ss_reg }
 443 #define cs { OP_REG, cs_reg }
 444 #define ds { OP_REG, ds_reg }
 445 #define fs { OP_REG, fs_reg }
 446 #define gs { OP_REG, gs_reg }
 447
 448 #define MX { OP_MMX, 0 }
 449 #define XM { OP_XMM, 0 }
 450 #define XMScalar { OP_XMM, scalar_mode }
 451 #define XMGatherD { OP_XMM, vex_vsib_d_w_dq_mode }
 452 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 453 #define XMM { OP_XMM, xmm_mode }
 454 #define TMM { OP_XMM, tmm_mode }
 455 #define XMxmmq { OP_XMM, xmmq_mode }
 456 #define EM { OP_EM, v_mode }
 457 #define EMS { OP_EM, v_swap_mode }
 458 #define EMd { OP_EM, d_mode }
 459 #define EMx { OP_EM, x_mode }
 460 #define EXbwUnit { OP_EX, bw_unit_mode }
 461 #define EXb { OP_EX, b_mode }
 462 #define EXw { OP_EX, w_mode }
 463 #define EXd { OP_EX, d_mode }
 464 #define EXdS { OP_EX, d_swap_mode }
 465 #define EXwS { OP_EX, w_swap_mode }
 466 #define EXq { OP_EX, q_mode }
 467 #define EXqS { OP_EX, q_swap_mode }
 468 #define EXdq { OP_EX, dq_mode }
 469 #define EXx { OP_EX, x_mode }
 470 #define EXxh { OP_EX, xh_mode }
 471 #define EXxS { OP_EX, x_swap_mode }
 472 #define EXxmm { OP_EX, xmm_mode }
 473 #define EXymm { OP_EX, ymm_mode }
 474 #define EXtmm { OP_EX, tmm_mode }
 475 #define EXxmmq { OP_EX, xmmq_mode }
 476 #define EXxmmqh { OP_EX, evex_half_bcst_xmmqh_mode }
 477 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 478 #define EXxmmdw { OP_EX, xmmdw_mode }
 479 #define EXxmmqd { OP_EX, xmmqd_mode }
 480 #define EXxmmqdh { OP_EX, evex_half_bcst_xmmqdh_mode }
 481 #define EXymmq { OP_EX, ymmq_mode }
 482 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 483 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 484 #define MS { OP_MS, v_mode }
 485 #define XS { OP_XS, v_mode }
 486 #define EMCq { OP_EMC, q_mode }
 487 #define MXC { OP_MXC, 0 }
 488 #define OPSUF { OP_3DNowSuffix, 0 }
 489 #define SEP { SEP_Fixup, 0 }
 490 #define CMP { CMP_Fixup, 0 }
 491 #define XMM0 { XMM_Fixup, 0 }
 492 #define FXSAVE { FXSAVE_Fixup, 0 }
 493
 494 #define Vex { OP_VEX, x_mode }
 495 #define VexW { OP_VexW, x_mode }
 496 #define VexScalar { OP_VEX, scalar_mode }
 497 #define VexScalarR { OP_VexR, scalar_mode }
 498 #define VexGatherD { OP_VEX, vex_vsib_d_w_dq_mode }
 499 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 500 #define VexGdq { OP_VEX, dq_mode }
 501 #define VexTmm { OP_VEX, tmm_mode }
 502 #define XMVexI4 { OP_REG_VexI4, x_mode }
 503 #define XMVexScalarI4 { OP_REG_VexI4, scalar_mode }
 504 #define VexI4 { OP_VexI4, 0 }
 505 #define PCLMUL { PCLMUL_Fixup, 0 }
 506 #define VPCMP { VPCMP_Fixup, 0 }
 507 #define VPCOM { VPCOM_Fixup, 0 }
 508
 509 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 510 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
 511 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 512
 513 #define MaskG { OP_G, mask_mode }
 514 #define MaskE { OP_E, mask_mode }
 515 #define MaskBDE { OP_E, mask_bd_mode }
 516 #define MaskVex { OP_VEX, mask_mode }
 517
 518 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 519 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 520
 521 #define MVexSIBMEM { OP_M, vex_sibmem_mode }
 522
 523 /* Used handle "rep" prefix for string instructions.  */
 524 #define Xbr { REP_Fixup, eSI_reg }
 525 #define Xvr { REP_Fixup, eSI_reg }
 526 #define Ybr { REP_Fixup, eDI_reg }
 527 #define Yvr { REP_Fixup, eDI_reg }
 528 #define Yzr { REP_Fixup, eDI_reg }
 529 #define indirDXr { REP_Fixup, indir_dx_reg }
 530 #define ALr { REP_Fixup, al_reg }
 531 #define eAXr { REP_Fixup, eAX_reg }
 532
 533 /* Used handle HLE prefix for lockable instructions.  */
 534 #define Ebh1 { HLE_Fixup1, b_mode }
 535 #define Evh1 { HLE_Fixup1, v_mode }
 536 #define Ebh2 { HLE_Fixup2, b_mode }
 537 #define Evh2 { HLE_Fixup2, v_mode }
 538 #define Ebh3 { HLE_Fixup3, b_mode }
 539 #define Evh3 { HLE_Fixup3, v_mode }
 540
 541 #define BND { BND_Fixup, 0 }
 542 #define NOTRACK { NOTRACK_Fixup, 0 }
 543
 544 #define cond_jump_flag { NULL, cond_jump_mode }
 545 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 546
 547 /* bits in sizeflag */
 548 #define SUFFIX_ALWAYS 4
 549 #define AFLAG 2
 550 #define DFLAG 1
 551
 552 enum
 553 {
 554   /* byte operand */
 555   b_mode = 1,
 556   /* byte operand with operand swapped */
 557   b_swap_mode,
 558   /* byte operand, sign extend like 'T' suffix */
 559   b_T_mode,
 560   /* operand size depends on prefixes */
 561   v_mode,
 562   /* operand size depends on prefixes with operand swapped */
 563   v_swap_mode,
 564   /* operand size depends on address prefix */
 565   va_mode,
 566   /* word operand */
 567   w_mode,
 568   /* double word operand  */
 569   d_mode,
 570   /* word operand with operand swapped  */
 571   w_swap_mode,
 572   /* double word operand with operand swapped */
 573   d_swap_mode,
 574   /* quad word operand */
 575   q_mode,
 576   /* quad word operand with operand swapped */
 577   q_swap_mode,
 578   /* ten-byte operand */
 579   t_mode,
 580   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 581      broadcast enabled.  */
 582   x_mode,
 583   /* Similar to x_mode, but with different EVEX mem shifts.  */
 584   evex_x_gscat_mode,
 585   /* Similar to x_mode, but with yet different EVEX mem shifts.  */
 586   bw_unit_mode,
 587   /* Similar to x_mode, but with disabled broadcast.  */
 588   evex_x_nobcst_mode,
 589   /* Similar to x_mode, but with operands swapped and disabled broadcast
 590      in EVEX.  */
 591   x_swap_mode,
 592   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 593      broadcast of 16bit enabled.  */
 594   xh_mode,
 595   /* 16-byte XMM operand */
 596   xmm_mode,
 597   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 598      memory operand (depending on vector length).  Broadcast isn't
 599      allowed.  */
 600   xmmq_mode,
 601   /* Same as xmmq_mode, but broadcast is allowed.  */
 602   evex_half_bcst_xmmq_mode,
 603   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 604      memory operand (depending on vector length).  16bit broadcast.  */
 605   evex_half_bcst_xmmqh_mode,
 606   /* 16-byte XMM, word, double word or quad word operand.  */
 607   xmmdw_mode,
 608   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 609   xmmqd_mode,
 610   /* 16-byte XMM, double word, quad word operand or xmm word operand.
 611      16bit broadcast.  */
 612   evex_half_bcst_xmmqdh_mode,
 613   /* 32-byte YMM operand */
 614   ymm_mode,
 615   /* quad word, ymmword or zmmword memory operand.  */
 616   ymmq_mode,
 617   /* TMM operand */
 618   tmm_mode,
 619   /* d_mode in 32bit, q_mode in 64bit mode.  */
 620   m_mode,
 621   /* pair of v_mode operands */
 622   a_mode,
 623   cond_jump_mode,
 624   loop_jcxz_mode,
 625   movsxd_mode,
 626   v_bnd_mode,
 627   /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode.  */
 628   v_bndmk_mode,
 629   /* operand size depends on REX.W / VEX.W.  */
 630   dq_mode,
 631   /* Displacements like v_mode without considering Intel64 ISA.  */
 632   dqw_mode,
 633   /* bounds operand */
 634   bnd_mode,
 635   /* bounds operand with operand swapped */
 636   bnd_swap_mode,
 637   /* 4- or 6-byte pointer operand */
 638   f_mode,
 639   const_1_mode,
 640   /* v_mode for indirect branch opcodes.  */
 641   indir_v_mode,
 642   /* v_mode for stack-related opcodes.  */
 643   stack_v_mode,
 644   /* non-quad operand size depends on prefixes */
 645   z_mode,
 646   /* 16-byte operand */
 647   o_mode,
 648   /* registers like d_mode, memory like b_mode.  */
 649   db_mode,
 650   /* registers like d_mode, memory like w_mode.  */
 651   dw_mode,
 652
 653   /* Operand size depends on the VEX.W bit, with VSIB dword indices.  */
 654   vex_vsib_d_w_dq_mode,
 655   /* Operand size depends on the VEX.W bit, with VSIB qword indices.  */
 656   vex_vsib_q_w_dq_mode,
 657   /* mandatory non-vector SIB.  */
 658   vex_sibmem_mode,
 659
 660   /* scalar, ignore vector length.  */
 661   scalar_mode,
 662
 663   /* Static rounding.  */
 664   evex_rounding_mode,
 665   /* Static rounding, 64-bit mode only.  */
 666   evex_rounding_64_mode,
 667   /* Supress all exceptions.  */
 668   evex_sae_mode,
 669
 670   /* Mask register operand.  */
 671   mask_mode,
 672   /* Mask register operand.  */
 673   mask_bd_mode,
 674
 675   es_reg,
 676   cs_reg,
 677   ss_reg,
 678   ds_reg,
 679   fs_reg,
 680   gs_reg,
 681
 682   eAX_reg,
 683   eCX_reg,
 684   eDX_reg,
 685   eBX_reg,
 686   eSP_reg,
 687   eBP_reg,
 688   eSI_reg,
 689   eDI_reg,
 690
 691   al_reg,
 692   cl_reg,
 693   dl_reg,
 694   bl_reg,
 695   ah_reg,
 696   ch_reg,
 697   dh_reg,
 698   bh_reg,
 699
 700   ax_reg,
 701   cx_reg,
 702   dx_reg,
 703   bx_reg,
 704   sp_reg,
 705   bp_reg,
 706   si_reg,
 707   di_reg,
 708
 709   rAX_reg,
 710   rCX_reg,
 711   rDX_reg,
 712   rBX_reg,
 713   rSP_reg,
 714   rBP_reg,
 715   rSI_reg,
 716   rDI_reg,
 717
 718   z_mode_ax_reg,
 719   indir_dx_reg
 720 };
 721
 722 enum
 723 {
 724   FLOATCODE = 1,
 725   USE_REG_TABLE,
 726   USE_MOD_TABLE,
 727   USE_RM_TABLE,
 728   USE_PREFIX_TABLE,
 729   USE_X86_64_TABLE,
 730   USE_3BYTE_TABLE,
 731   USE_XOP_8F_TABLE,
 732   USE_VEX_C4_TABLE,
 733   USE_VEX_C5_TABLE,
 734   USE_VEX_LEN_TABLE,
 735   USE_VEX_W_TABLE,
 736   USE_EVEX_TABLE,
 737   USE_EVEX_LEN_TABLE
 738 };
 739
 740 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 741
 742 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 743 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 744 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 745 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 746 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 747 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 748 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 749 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 750 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 751 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 752 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 753 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 754 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 755 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 756 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 757 #define EVEX_LEN_TABLE(I)       DIS386 (USE_EVEX_LEN_TABLE, (I))
 758
 759 enum
 760 {
 761   REG_80 = 0,
 762   REG_81,
 763   REG_83,
 764   REG_8F,
 765   REG_C0,
 766   REG_C1,
 767   REG_C6,
 768   REG_C7,
 769   REG_D0,
 770   REG_D1,
 771   REG_D2,
 772   REG_D3,
 773   REG_F6,
 774   REG_F7,
 775   REG_FE,
 776   REG_FF,
 777   REG_0F00,
 778   REG_0F01,
 779   REG_0F0D,
 780   REG_0F18,
 781   REG_0F1C_P_0_MOD_0,
 782   REG_0F1E_P_1_MOD_3,
 783   REG_0F38D8_PREFIX_1,
 784   REG_0F3A0F_PREFIX_1_MOD_3,
 785   REG_0F71_MOD_0,
 786   REG_0F72_MOD_0,
 787   REG_0F73_MOD_0,
 788   REG_0FA6,
 789   REG_0FA7,
 790   REG_0FAE,
 791   REG_0FBA,
 792   REG_0FC7,
 793   REG_VEX_0F71_M_0,
 794   REG_VEX_0F72_M_0,
 795   REG_VEX_0F73_M_0,
 796   REG_VEX_0FAE,
 797   REG_VEX_0F3849_X86_64_P_0_W_0_M_1,
 798   REG_VEX_0F38F3_L_0,
 799
 800   REG_XOP_09_01_L_0,
 801   REG_XOP_09_02_L_0,
 802   REG_XOP_09_12_M_1_L_0,
 803   REG_XOP_0A_12_L_0,
 804
 805   REG_EVEX_0F71,
 806   REG_EVEX_0F72,
 807   REG_EVEX_0F73,
 808   REG_EVEX_0F38C6_M_0_L_2,
 809   REG_EVEX_0F38C7_M_0_L_2
 810 };
 811
 812 enum
 813 {
 814   MOD_62_32BIT = 0,
 815   MOD_8D,
 816   MOD_C4_32BIT,
 817   MOD_C5_32BIT,
 818   MOD_C6_REG_7,
 819   MOD_C7_REG_7,
 820   MOD_FF_REG_3,
 821   MOD_FF_REG_5,
 822   MOD_0F01_REG_0,
 823   MOD_0F01_REG_1,
 824   MOD_0F01_REG_2,
 825   MOD_0F01_REG_3,
 826   MOD_0F01_REG_5,
 827   MOD_0F01_REG_7,
 828   MOD_0F12_PREFIX_0,
 829   MOD_0F12_PREFIX_2,
 830   MOD_0F13,
 831   MOD_0F16_PREFIX_0,
 832   MOD_0F16_PREFIX_2,
 833   MOD_0F17,
 834   MOD_0F18_REG_0,
 835   MOD_0F18_REG_1,
 836   MOD_0F18_REG_2,
 837   MOD_0F18_REG_3,
 838   MOD_0F1A_PREFIX_0,
 839   MOD_0F1B_PREFIX_0,
 840   MOD_0F1B_PREFIX_1,
 841   MOD_0F1C_PREFIX_0,
 842   MOD_0F1E_PREFIX_1,
 843   MOD_0F2B_PREFIX_0,
 844   MOD_0F2B_PREFIX_1,
 845   MOD_0F2B_PREFIX_2,
 846   MOD_0F2B_PREFIX_3,
 847   MOD_0F50,
 848   MOD_0F71,
 849   MOD_0F72,
 850   MOD_0F73,
 851   MOD_0FAE_REG_0,
 852   MOD_0FAE_REG_1,
 853   MOD_0FAE_REG_2,
 854   MOD_0FAE_REG_3,
 855   MOD_0FAE_REG_4,
 856   MOD_0FAE_REG_5,
 857   MOD_0FAE_REG_6,
 858   MOD_0FAE_REG_7,
 859   MOD_0FB2,
 860   MOD_0FB4,
 861   MOD_0FB5,
 862   MOD_0FC3,
 863   MOD_0FC7_REG_3,
 864   MOD_0FC7_REG_4,
 865   MOD_0FC7_REG_5,
 866   MOD_0FC7_REG_6,
 867   MOD_0FC7_REG_7,
 868   MOD_0FD7,
 869   MOD_0FE7_PREFIX_2,
 870   MOD_0FF0_PREFIX_3,
 871   MOD_0F382A,
 872   MOD_0F38DC_PREFIX_1,
 873   MOD_0F38DD_PREFIX_1,
 874   MOD_0F38DE_PREFIX_1,
 875   MOD_0F38DF_PREFIX_1,
 876   MOD_0F38F5,
 877   MOD_0F38F6_PREFIX_0,
 878   MOD_0F38F8_PREFIX_1,
 879   MOD_0F38F8_PREFIX_2,
 880   MOD_0F38F8_PREFIX_3,
 881   MOD_0F38F9,
 882   MOD_0F38FA_PREFIX_1,
 883   MOD_0F38FB_PREFIX_1,
 884   MOD_0F3A0F_PREFIX_1,
 885
 886   MOD_VEX_0F12_PREFIX_0,
 887   MOD_VEX_0F12_PREFIX_2,
 888   MOD_VEX_0F13,
 889   MOD_VEX_0F16_PREFIX_0,
 890   MOD_VEX_0F16_PREFIX_2,
 891   MOD_VEX_0F17,
 892   MOD_VEX_0F2B,
 893   MOD_VEX_0F41_L_1,
 894   MOD_VEX_0F42_L_1,
 895   MOD_VEX_0F44_L_0,
 896   MOD_VEX_0F45_L_1,
 897   MOD_VEX_0F46_L_1,
 898   MOD_VEX_0F47_L_1,
 899   MOD_VEX_0F4A_L_1,
 900   MOD_VEX_0F4B_L_1,
 901   MOD_VEX_0F50,
 902   MOD_VEX_0F71,
 903   MOD_VEX_0F72,
 904   MOD_VEX_0F73,
 905   MOD_VEX_0F91_L_0,
 906   MOD_VEX_0F92_L_0,
 907   MOD_VEX_0F93_L_0,
 908   MOD_VEX_0F98_L_0,
 909   MOD_VEX_0F99_L_0,
 910   MOD_VEX_0FAE_REG_2,
 911   MOD_VEX_0FAE_REG_3,
 912   MOD_VEX_0FD7,
 913   MOD_VEX_0FE7,
 914   MOD_VEX_0FF0_PREFIX_3,
 915   MOD_VEX_0F381A,
 916   MOD_VEX_0F382A,
 917   MOD_VEX_0F382C,
 918   MOD_VEX_0F382D,
 919   MOD_VEX_0F382E,
 920   MOD_VEX_0F382F,
 921   MOD_VEX_0F3849_X86_64_P_0_W_0,
 922   MOD_VEX_0F3849_X86_64_P_2_W_0,
 923   MOD_VEX_0F3849_X86_64_P_3_W_0,
 924   MOD_VEX_0F384B_X86_64_P_1_W_0,
 925   MOD_VEX_0F384B_X86_64_P_2_W_0,
 926   MOD_VEX_0F384B_X86_64_P_3_W_0,
 927   MOD_VEX_0F385A,
 928   MOD_VEX_0F385C_X86_64_P_1_W_0,
 929   MOD_VEX_0F385E_X86_64_P_0_W_0,
 930   MOD_VEX_0F385E_X86_64_P_1_W_0,
 931   MOD_VEX_0F385E_X86_64_P_2_W_0,
 932   MOD_VEX_0F385E_X86_64_P_3_W_0,
 933   MOD_VEX_0F388C,
 934   MOD_VEX_0F388E,
 935   MOD_VEX_0F3A30_L_0,
 936   MOD_VEX_0F3A31_L_0,
 937   MOD_VEX_0F3A32_L_0,
 938   MOD_VEX_0F3A33_L_0,
 939
 940   MOD_XOP_09_12,
 941
 942   MOD_EVEX_0F381A,
 943   MOD_EVEX_0F381B,
 944   MOD_EVEX_0F3828_P_1,
 945   MOD_EVEX_0F382A_P_1_W_1,
 946   MOD_EVEX_0F3838_P_1,
 947   MOD_EVEX_0F383A_P_1_W_0,
 948   MOD_EVEX_0F385A,
 949   MOD_EVEX_0F385B,
 950   MOD_EVEX_0F387A_W_0,
 951   MOD_EVEX_0F387B_W_0,
 952   MOD_EVEX_0F387C,
 953   MOD_EVEX_0F38C6,
 954   MOD_EVEX_0F38C7,
 955 };
 956
 957 enum
 958 {
 959   RM_C6_REG_7 = 0,
 960   RM_C7_REG_7,
 961   RM_0F01_REG_0,
 962   RM_0F01_REG_1,
 963   RM_0F01_REG_2,
 964   RM_0F01_REG_3,
 965   RM_0F01_REG_5_MOD_3,
 966   RM_0F01_REG_7_MOD_3,
 967   RM_0F1E_P_1_MOD_3_REG_7,
 968   RM_0FAE_REG_6_MOD_3_P_0,
 969   RM_0FAE_REG_7_MOD_3,
 970   RM_0F3A0F_P_1_MOD_3_REG_0,
 971
 972   RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0
 973 };
 974
 975 enum
 976 {
 977   PREFIX_90 = 0,
 978   PREFIX_0F01_REG_1_RM_4,
 979   PREFIX_0F01_REG_1_RM_5,
 980   PREFIX_0F01_REG_1_RM_6,
 981   PREFIX_0F01_REG_1_RM_7,
 982   PREFIX_0F01_REG_3_RM_1,
 983   PREFIX_0F01_REG_5_MOD_0,
 984   PREFIX_0F01_REG_5_MOD_3_RM_0,
 985   PREFIX_0F01_REG_5_MOD_3_RM_1,
 986   PREFIX_0F01_REG_5_MOD_3_RM_2,
 987   PREFIX_0F01_REG_5_MOD_3_RM_4,
 988   PREFIX_0F01_REG_5_MOD_3_RM_5,
 989   PREFIX_0F01_REG_5_MOD_3_RM_6,
 990   PREFIX_0F01_REG_5_MOD_3_RM_7,
 991   PREFIX_0F01_REG_7_MOD_3_RM_2,
 992   PREFIX_0F01_REG_7_MOD_3_RM_6,
 993   PREFIX_0F01_REG_7_MOD_3_RM_7,
 994   PREFIX_0F09,
 995   PREFIX_0F10,
 996   PREFIX_0F11,
 997   PREFIX_0F12,
 998   PREFIX_0F16,
 999   PREFIX_0F1A,
1000   PREFIX_0F1B,
1001   PREFIX_0F1C,
1002   PREFIX_0F1E,
1003   PREFIX_0F2A,
1004   PREFIX_0F2B,
1005   PREFIX_0F2C,
1006   PREFIX_0F2D,
1007   PREFIX_0F2E,
1008   PREFIX_0F2F,
1009   PREFIX_0F51,
1010   PREFIX_0F52,
1011   PREFIX_0F53,
1012   PREFIX_0F58,
1013   PREFIX_0F59,
1014   PREFIX_0F5A,
1015   PREFIX_0F5B,
1016   PREFIX_0F5C,
1017   PREFIX_0F5D,
1018   PREFIX_0F5E,
1019   PREFIX_0F5F,
1020   PREFIX_0F60,
1021   PREFIX_0F61,
1022   PREFIX_0F62,
1023   PREFIX_0F6F,
1024   PREFIX_0F70,
1025   PREFIX_0F78,
1026   PREFIX_0F79,
1027   PREFIX_0F7C,
1028   PREFIX_0F7D,
1029   PREFIX_0F7E,
1030   PREFIX_0F7F,
1031   PREFIX_0FAE_REG_0_MOD_3,
1032   PREFIX_0FAE_REG_1_MOD_3,
1033   PREFIX_0FAE_REG_2_MOD_3,
1034   PREFIX_0FAE_REG_3_MOD_3,
1035   PREFIX_0FAE_REG_4_MOD_0,
1036   PREFIX_0FAE_REG_4_MOD_3,
1037   PREFIX_0FAE_REG_5_MOD_3,
1038   PREFIX_0FAE_REG_6_MOD_0,
1039   PREFIX_0FAE_REG_6_MOD_3,
1040   PREFIX_0FAE_REG_7_MOD_0,
1041   PREFIX_0FB8,
1042   PREFIX_0FBC,
1043   PREFIX_0FBD,
1044   PREFIX_0FC2,
1045   PREFIX_0FC7_REG_6_MOD_0,
1046   PREFIX_0FC7_REG_6_MOD_3,
1047   PREFIX_0FC7_REG_7_MOD_3,
1048   PREFIX_0FD0,
1049   PREFIX_0FD6,
1050   PREFIX_0FE6,
1051   PREFIX_0FE7,
1052   PREFIX_0FF0,
1053   PREFIX_0FF7,
1054   PREFIX_0F38D8,
1055   PREFIX_0F38DC,
1056   PREFIX_0F38DD,
1057   PREFIX_0F38DE,
1058   PREFIX_0F38DF,
1059   PREFIX_0F38F0,
1060   PREFIX_0F38F1,
1061   PREFIX_0F38F6,
1062   PREFIX_0F38F8,
1063   PREFIX_0F38FA,
1064   PREFIX_0F38FB,
1065   PREFIX_0F3A0F,
1066   PREFIX_VEX_0F10,
1067   PREFIX_VEX_0F11,
1068   PREFIX_VEX_0F12,
1069   PREFIX_VEX_0F16,
1070   PREFIX_VEX_0F2A,
1071   PREFIX_VEX_0F2C,
1072   PREFIX_VEX_0F2D,
1073   PREFIX_VEX_0F2E,
1074   PREFIX_VEX_0F2F,
1075   PREFIX_VEX_0F41_L_1_M_1_W_0,
1076   PREFIX_VEX_0F41_L_1_M_1_W_1,
1077   PREFIX_VEX_0F42_L_1_M_1_W_0,
1078   PREFIX_VEX_0F42_L_1_M_1_W_1,
1079   PREFIX_VEX_0F44_L_0_M_1_W_0,
1080   PREFIX_VEX_0F44_L_0_M_1_W_1,
1081   PREFIX_VEX_0F45_L_1_M_1_W_0,
1082   PREFIX_VEX_0F45_L_1_M_1_W_1,
1083   PREFIX_VEX_0F46_L_1_M_1_W_0,
1084   PREFIX_VEX_0F46_L_1_M_1_W_1,
1085   PREFIX_VEX_0F47_L_1_M_1_W_0,
1086   PREFIX_VEX_0F47_L_1_M_1_W_1,
1087   PREFIX_VEX_0F4A_L_1_M_1_W_0,
1088   PREFIX_VEX_0F4A_L_1_M_1_W_1,
1089   PREFIX_VEX_0F4B_L_1_M_1_W_0,
1090   PREFIX_VEX_0F4B_L_1_M_1_W_1,
1091   PREFIX_VEX_0F51,
1092   PREFIX_VEX_0F52,
1093   PREFIX_VEX_0F53,
1094   PREFIX_VEX_0F58,
1095   PREFIX_VEX_0F59,
1096   PREFIX_VEX_0F5A,
1097   PREFIX_VEX_0F5B,
1098   PREFIX_VEX_0F5C,
1099   PREFIX_VEX_0F5D,
1100   PREFIX_VEX_0F5E,
1101   PREFIX_VEX_0F5F,
1102   PREFIX_VEX_0F6F,
1103   PREFIX_VEX_0F70,
1104   PREFIX_VEX_0F7C,
1105   PREFIX_VEX_0F7D,
1106   PREFIX_VEX_0F7E,
1107   PREFIX_VEX_0F7F,
1108   PREFIX_VEX_0F90_L_0_W_0,
1109   PREFIX_VEX_0F90_L_0_W_1,
1110   PREFIX_VEX_0F91_L_0_M_0_W_0,
1111   PREFIX_VEX_0F91_L_0_M_0_W_1,
1112   PREFIX_VEX_0F92_L_0_M_1_W_0,
1113   PREFIX_VEX_0F92_L_0_M_1_W_1,
1114   PREFIX_VEX_0F93_L_0_M_1_W_0,
1115   PREFIX_VEX_0F93_L_0_M_1_W_1,
1116   PREFIX_VEX_0F98_L_0_M_1_W_0,
1117   PREFIX_VEX_0F98_L_0_M_1_W_1,
1118   PREFIX_VEX_0F99_L_0_M_1_W_0,
1119   PREFIX_VEX_0F99_L_0_M_1_W_1,
1120   PREFIX_VEX_0FC2,
1121   PREFIX_VEX_0FD0,
1122   PREFIX_VEX_0FE6,
1123   PREFIX_VEX_0FF0,
1124   PREFIX_VEX_0F3849_X86_64,
1125   PREFIX_VEX_0F384B_X86_64,
1126   PREFIX_VEX_0F385C_X86_64,
1127   PREFIX_VEX_0F385E_X86_64,
1128   PREFIX_VEX_0F38F5_L_0,
1129   PREFIX_VEX_0F38F6_L_0,
1130   PREFIX_VEX_0F38F7_L_0,
1131   PREFIX_VEX_0F3AF0_L_0,
1132
1133   PREFIX_EVEX_0F5B,
1134   PREFIX_EVEX_0F6F,
1135   PREFIX_EVEX_0F70,
1136   PREFIX_EVEX_0F78,
1137   PREFIX_EVEX_0F79,
1138   PREFIX_EVEX_0F7A,
1139   PREFIX_EVEX_0F7B,
1140   PREFIX_EVEX_0F7E,
1141   PREFIX_EVEX_0F7F,
1142   PREFIX_EVEX_0FC2,
1143   PREFIX_EVEX_0FE6,
1144   PREFIX_EVEX_0F3810,
1145   PREFIX_EVEX_0F3811,
1146   PREFIX_EVEX_0F3812,
1147   PREFIX_EVEX_0F3813,
1148   PREFIX_EVEX_0F3814,
1149   PREFIX_EVEX_0F3815,
1150   PREFIX_EVEX_0F3820,
1151   PREFIX_EVEX_0F3821,
1152   PREFIX_EVEX_0F3822,
1153   PREFIX_EVEX_0F3823,
1154   PREFIX_EVEX_0F3824,
1155   PREFIX_EVEX_0F3825,
1156   PREFIX_EVEX_0F3826,
1157   PREFIX_EVEX_0F3827,
1158   PREFIX_EVEX_0F3828,
1159   PREFIX_EVEX_0F3829,
1160   PREFIX_EVEX_0F382A,
1161   PREFIX_EVEX_0F3830,
1162   PREFIX_EVEX_0F3831,
1163   PREFIX_EVEX_0F3832,
1164   PREFIX_EVEX_0F3833,
1165   PREFIX_EVEX_0F3834,
1166   PREFIX_EVEX_0F3835,
1167   PREFIX_EVEX_0F3838,
1168   PREFIX_EVEX_0F3839,
1169   PREFIX_EVEX_0F383A,
1170   PREFIX_EVEX_0F3852,
1171   PREFIX_EVEX_0F3853,
1172   PREFIX_EVEX_0F3868,
1173   PREFIX_EVEX_0F3872,
1174   PREFIX_EVEX_0F389A,
1175   PREFIX_EVEX_0F389B,
1176   PREFIX_EVEX_0F38AA,
1177   PREFIX_EVEX_0F38AB,
1178
1179   PREFIX_EVEX_0F3A08,
1180   PREFIX_EVEX_0F3A0A,
1181   PREFIX_EVEX_0F3A26,
1182   PREFIX_EVEX_0F3A27,
1183   PREFIX_EVEX_0F3A56,
1184   PREFIX_EVEX_0F3A57,
1185   PREFIX_EVEX_0F3A66,
1186   PREFIX_EVEX_0F3A67,
1187   PREFIX_EVEX_0F3AC2,
1188
1189   PREFIX_EVEX_MAP5_10,
1190   PREFIX_EVEX_MAP5_11,
1191   PREFIX_EVEX_MAP5_1D,
1192   PREFIX_EVEX_MAP5_2A,
1193   PREFIX_EVEX_MAP5_2C,
1194   PREFIX_EVEX_MAP5_2D,
1195   PREFIX_EVEX_MAP5_2E,
1196   PREFIX_EVEX_MAP5_2F,
1197   PREFIX_EVEX_MAP5_51,
1198   PREFIX_EVEX_MAP5_58,
1199   PREFIX_EVEX_MAP5_59,
1200   PREFIX_EVEX_MAP5_5A,
1201   PREFIX_EVEX_MAP5_5B,
1202   PREFIX_EVEX_MAP5_5C,
1203   PREFIX_EVEX_MAP5_5D,
1204   PREFIX_EVEX_MAP5_5E,
1205   PREFIX_EVEX_MAP5_5F,
1206   PREFIX_EVEX_MAP5_78,
1207   PREFIX_EVEX_MAP5_79,
1208   PREFIX_EVEX_MAP5_7A,
1209   PREFIX_EVEX_MAP5_7B,
1210   PREFIX_EVEX_MAP5_7C,
1211   PREFIX_EVEX_MAP5_7D,
1212
1213   PREFIX_EVEX_MAP6_13,
1214   PREFIX_EVEX_MAP6_56,
1215   PREFIX_EVEX_MAP6_57,
1216   PREFIX_EVEX_MAP6_D6,
1217   PREFIX_EVEX_MAP6_D7,
1218 };
1219
1220 enum
1221 {
1222   X86_64_06 = 0,
1223   X86_64_07,
1224   X86_64_0E,
1225   X86_64_16,
1226   X86_64_17,
1227   X86_64_1E,
1228   X86_64_1F,
1229   X86_64_27,
1230   X86_64_2F,
1231   X86_64_37,
1232   X86_64_3F,
1233   X86_64_60,
1234   X86_64_61,
1235   X86_64_62,
1236   X86_64_63,
1237   X86_64_6D,
1238   X86_64_6F,
1239   X86_64_82,
1240   X86_64_9A,
1241   X86_64_C2,
1242   X86_64_C3,
1243   X86_64_C4,
1244   X86_64_C5,
1245   X86_64_CE,
1246   X86_64_D4,
1247   X86_64_D5,
1248   X86_64_E8,
1249   X86_64_E9,
1250   X86_64_EA,
1251   X86_64_0F01_REG_0,
1252   X86_64_0F01_REG_1,
1253   X86_64_0F01_REG_1_RM_5_PREFIX_2,
1254   X86_64_0F01_REG_1_RM_6_PREFIX_2,
1255   X86_64_0F01_REG_1_RM_7_PREFIX_2,
1256   X86_64_0F01_REG_2,
1257   X86_64_0F01_REG_3,
1258   X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1,
1259   X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1,
1260   X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1,
1261   X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1,
1262   X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1,
1263   X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3,
1264   X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1,
1265   X86_64_0F24,
1266   X86_64_0F26,
1267   X86_64_0FC7_REG_6_MOD_3_PREFIX_1,
1268
1269   X86_64_VEX_0F3849,
1270   X86_64_VEX_0F384B,
1271   X86_64_VEX_0F385C,
1272   X86_64_VEX_0F385E
1273 };
1274
1275 enum
1276 {
1277   THREE_BYTE_0F38 = 0,
1278   THREE_BYTE_0F3A
1279 };
1280
1281 enum
1282 {
1283   XOP_08 = 0,
1284   XOP_09,
1285   XOP_0A
1286 };
1287
1288 enum
1289 {
1290   VEX_0F = 0,
1291   VEX_0F38,
1292   VEX_0F3A
1293 };
1294
1295 enum
1296 {
1297   EVEX_0F = 0,
1298   EVEX_0F38,
1299   EVEX_0F3A,
1300   EVEX_MAP5,
1301   EVEX_MAP6,
1302 };
1303
1304 enum
1305 {
1306   VEX_LEN_0F12_P_0_M_0 = 0,
1307   VEX_LEN_0F12_P_0_M_1,
1308 #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0
1309   VEX_LEN_0F13_M_0,
1310   VEX_LEN_0F16_P_0_M_0,
1311   VEX_LEN_0F16_P_0_M_1,
1312 #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0
1313   VEX_LEN_0F17_M_0,
1314   VEX_LEN_0F41,
1315   VEX_LEN_0F42,
1316   VEX_LEN_0F44,
1317   VEX_LEN_0F45,
1318   VEX_LEN_0F46,
1319   VEX_LEN_0F47,
1320   VEX_LEN_0F4A,
1321   VEX_LEN_0F4B,
1322   VEX_LEN_0F6E,
1323   VEX_LEN_0F77,
1324   VEX_LEN_0F7E_P_1,
1325   VEX_LEN_0F7E_P_2,
1326   VEX_LEN_0F90,
1327   VEX_LEN_0F91,
1328   VEX_LEN_0F92,
1329   VEX_LEN_0F93,
1330   VEX_LEN_0F98,
1331   VEX_LEN_0F99,
1332   VEX_LEN_0FAE_R_2_M_0,
1333   VEX_LEN_0FAE_R_3_M_0,
1334   VEX_LEN_0FC4,
1335   VEX_LEN_0FC5,
1336   VEX_LEN_0FD6,
1337   VEX_LEN_0FF7,
1338   VEX_LEN_0F3816,
1339   VEX_LEN_0F3819,
1340   VEX_LEN_0F381A_M_0,
1341   VEX_LEN_0F3836,
1342   VEX_LEN_0F3841,
1343   VEX_LEN_0F3849_X86_64_P_0_W_0_M_0,
1344   VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0,
1345   VEX_LEN_0F3849_X86_64_P_2_W_0_M_0,
1346   VEX_LEN_0F3849_X86_64_P_3_W_0_M_0,
1347   VEX_LEN_0F384B_X86_64_P_1_W_0_M_0,
1348   VEX_LEN_0F384B_X86_64_P_2_W_0_M_0,
1349   VEX_LEN_0F384B_X86_64_P_3_W_0_M_0,
1350   VEX_LEN_0F385A_M_0,
1351   VEX_LEN_0F385C_X86_64_P_1_W_0_M_0,
1352   VEX_LEN_0F385E_X86_64_P_0_W_0_M_0,
1353   VEX_LEN_0F385E_X86_64_P_1_W_0_M_0,
1354   VEX_LEN_0F385E_X86_64_P_2_W_0_M_0,
1355   VEX_LEN_0F385E_X86_64_P_3_W_0_M_0,
1356   VEX_LEN_0F38DB,
1357   VEX_LEN_0F38F2,
1358   VEX_LEN_0F38F3,
1359   VEX_LEN_0F38F5,
1360   VEX_LEN_0F38F6,
1361   VEX_LEN_0F38F7,
1362   VEX_LEN_0F3A00,
1363   VEX_LEN_0F3A01,
1364   VEX_LEN_0F3A06,
1365   VEX_LEN_0F3A14,
1366   VEX_LEN_0F3A15,
1367   VEX_LEN_0F3A16,
1368   VEX_LEN_0F3A17,
1369   VEX_LEN_0F3A18,
1370   VEX_LEN_0F3A19,
1371   VEX_LEN_0F3A20,
1372   VEX_LEN_0F3A21,
1373   VEX_LEN_0F3A22,
1374   VEX_LEN_0F3A30,
1375   VEX_LEN_0F3A31,
1376   VEX_LEN_0F3A32,
1377   VEX_LEN_0F3A33,
1378   VEX_LEN_0F3A38,
1379   VEX_LEN_0F3A39,
1380   VEX_LEN_0F3A41,
1381   VEX_LEN_0F3A46,
1382   VEX_LEN_0F3A60,
1383   VEX_LEN_0F3A61,
1384   VEX_LEN_0F3A62,
1385   VEX_LEN_0F3A63,
1386   VEX_LEN_0F3ADF,
1387   VEX_LEN_0F3AF0,
1388   VEX_LEN_0FXOP_08_85,
1389   VEX_LEN_0FXOP_08_86,
1390   VEX_LEN_0FXOP_08_87,
1391   VEX_LEN_0FXOP_08_8E,
1392   VEX_LEN_0FXOP_08_8F,
1393   VEX_LEN_0FXOP_08_95,
1394   VEX_LEN_0FXOP_08_96,
1395   VEX_LEN_0FXOP_08_97,
1396   VEX_LEN_0FXOP_08_9E,
1397   VEX_LEN_0FXOP_08_9F,
1398   VEX_LEN_0FXOP_08_A3,
1399   VEX_LEN_0FXOP_08_A6,
1400   VEX_LEN_0FXOP_08_B6,
1401   VEX_LEN_0FXOP_08_C0,
1402   VEX_LEN_0FXOP_08_C1,
1403   VEX_LEN_0FXOP_08_C2,
1404   VEX_LEN_0FXOP_08_C3,
1405   VEX_LEN_0FXOP_08_CC,
1406   VEX_LEN_0FXOP_08_CD,
1407   VEX_LEN_0FXOP_08_CE,
1408   VEX_LEN_0FXOP_08_CF,
1409   VEX_LEN_0FXOP_08_EC,
1410   VEX_LEN_0FXOP_08_ED,
1411   VEX_LEN_0FXOP_08_EE,
1412   VEX_LEN_0FXOP_08_EF,
1413   VEX_LEN_0FXOP_09_01,
1414   VEX_LEN_0FXOP_09_02,
1415   VEX_LEN_0FXOP_09_12_M_1,
1416   VEX_LEN_0FXOP_09_82_W_0,
1417   VEX_LEN_0FXOP_09_83_W_0,
1418   VEX_LEN_0FXOP_09_90,
1419   VEX_LEN_0FXOP_09_91,
1420   VEX_LEN_0FXOP_09_92,
1421   VEX_LEN_0FXOP_09_93,
1422   VEX_LEN_0FXOP_09_94,
1423   VEX_LEN_0FXOP_09_95,
1424   VEX_LEN_0FXOP_09_96,
1425   VEX_LEN_0FXOP_09_97,
1426   VEX_LEN_0FXOP_09_98,
1427   VEX_LEN_0FXOP_09_99,
1428   VEX_LEN_0FXOP_09_9A,
1429   VEX_LEN_0FXOP_09_9B,
1430   VEX_LEN_0FXOP_09_C1,
1431   VEX_LEN_0FXOP_09_C2,
1432   VEX_LEN_0FXOP_09_C3,
1433   VEX_LEN_0FXOP_09_C6,
1434   VEX_LEN_0FXOP_09_C7,
1435   VEX_LEN_0FXOP_09_CB,
1436   VEX_LEN_0FXOP_09_D1,
1437   VEX_LEN_0FXOP_09_D2,
1438   VEX_LEN_0FXOP_09_D3,
1439   VEX_LEN_0FXOP_09_D6,
1440   VEX_LEN_0FXOP_09_D7,
1441   VEX_LEN_0FXOP_09_DB,
1442   VEX_LEN_0FXOP_09_E1,
1443   VEX_LEN_0FXOP_09_E2,
1444   VEX_LEN_0FXOP_09_E3,
1445   VEX_LEN_0FXOP_0A_12,
1446 };
1447
1448 enum
1449 {
1450   EVEX_LEN_0F3816 = 0,
1451   EVEX_LEN_0F3819,
1452   EVEX_LEN_0F381A_M_0,
1453   EVEX_LEN_0F381B_M_0,
1454   EVEX_LEN_0F3836,
1455   EVEX_LEN_0F385A_M_0,
1456   EVEX_LEN_0F385B_M_0,
1457   EVEX_LEN_0F38C6_M_0,
1458   EVEX_LEN_0F38C7_M_0,
1459   EVEX_LEN_0F3A00,
1460   EVEX_LEN_0F3A01,
1461   EVEX_LEN_0F3A18,
1462   EVEX_LEN_0F3A19,
1463   EVEX_LEN_0F3A1A,
1464   EVEX_LEN_0F3A1B,
1465   EVEX_LEN_0F3A23,
1466   EVEX_LEN_0F3A38,
1467   EVEX_LEN_0F3A39,
1468   EVEX_LEN_0F3A3A,
1469   EVEX_LEN_0F3A3B,
1470   EVEX_LEN_0F3A43
1471 };
1472
1473 enum
1474 {
1475   VEX_W_0F41_L_1_M_1 = 0,
1476   VEX_W_0F42_L_1_M_1,
1477   VEX_W_0F44_L_0_M_1,
1478   VEX_W_0F45_L_1_M_1,
1479   VEX_W_0F46_L_1_M_1,
1480   VEX_W_0F47_L_1_M_1,
1481   VEX_W_0F4A_L_1_M_1,
1482   VEX_W_0F4B_L_1_M_1,
1483   VEX_W_0F90_L_0,
1484   VEX_W_0F91_L_0_M_0,
1485   VEX_W_0F92_L_0_M_1,
1486   VEX_W_0F93_L_0_M_1,
1487   VEX_W_0F98_L_0_M_1,
1488   VEX_W_0F99_L_0_M_1,
1489   VEX_W_0F380C,
1490   VEX_W_0F380D,
1491   VEX_W_0F380E,
1492   VEX_W_0F380F,
1493   VEX_W_0F3813,
1494   VEX_W_0F3816_L_1,
1495   VEX_W_0F3818,
1496   VEX_W_0F3819_L_1,
1497   VEX_W_0F381A_M_0_L_1,
1498   VEX_W_0F382C_M_0,
1499   VEX_W_0F382D_M_0,
1500   VEX_W_0F382E_M_0,
1501   VEX_W_0F382F_M_0,
1502   VEX_W_0F3836,
1503   VEX_W_0F3846,
1504   VEX_W_0F3849_X86_64_P_0,
1505   VEX_W_0F3849_X86_64_P_2,
1506   VEX_W_0F3849_X86_64_P_3,
1507   VEX_W_0F384B_X86_64_P_1,
1508   VEX_W_0F384B_X86_64_P_2,
1509   VEX_W_0F384B_X86_64_P_3,
1510   VEX_W_0F3850,
1511   VEX_W_0F3851,
1512   VEX_W_0F3852,
1513   VEX_W_0F3853,
1514   VEX_W_0F3858,
1515   VEX_W_0F3859,
1516   VEX_W_0F385A_M_0_L_0,
1517   VEX_W_0F385C_X86_64_P_1,
1518   VEX_W_0F385E_X86_64_P_0,
1519   VEX_W_0F385E_X86_64_P_1,
1520   VEX_W_0F385E_X86_64_P_2,
1521   VEX_W_0F385E_X86_64_P_3,
1522   VEX_W_0F3878,
1523   VEX_W_0F3879,
1524   VEX_W_0F38CF,
1525   VEX_W_0F3A00_L_1,
1526   VEX_W_0F3A01_L_1,
1527   VEX_W_0F3A02,
1528   VEX_W_0F3A04,
1529   VEX_W_0F3A05,
1530   VEX_W_0F3A06_L_1,
1531   VEX_W_0F3A18_L_1,
1532   VEX_W_0F3A19_L_1,
1533   VEX_W_0F3A1D,
1534   VEX_W_0F3A38_L_1,
1535   VEX_W_0F3A39_L_1,
1536   VEX_W_0F3A46_L_1,
1537   VEX_W_0F3A4A,
1538   VEX_W_0F3A4B,
1539   VEX_W_0F3A4C,
1540   VEX_W_0F3ACE,
1541   VEX_W_0F3ACF,
1542
1543   VEX_W_0FXOP_08_85_L_0,
1544   VEX_W_0FXOP_08_86_L_0,
1545   VEX_W_0FXOP_08_87_L_0,
1546   VEX_W_0FXOP_08_8E_L_0,
1547   VEX_W_0FXOP_08_8F_L_0,
1548   VEX_W_0FXOP_08_95_L_0,
1549   VEX_W_0FXOP_08_96_L_0,
1550   VEX_W_0FXOP_08_97_L_0,
1551   VEX_W_0FXOP_08_9E_L_0,
1552   VEX_W_0FXOP_08_9F_L_0,
1553   VEX_W_0FXOP_08_A6_L_0,
1554   VEX_W_0FXOP_08_B6_L_0,
1555   VEX_W_0FXOP_08_C0_L_0,
1556   VEX_W_0FXOP_08_C1_L_0,
1557   VEX_W_0FXOP_08_C2_L_0,
1558   VEX_W_0FXOP_08_C3_L_0,
1559   VEX_W_0FXOP_08_CC_L_0,
1560   VEX_W_0FXOP_08_CD_L_0,
1561   VEX_W_0FXOP_08_CE_L_0,
1562   VEX_W_0FXOP_08_CF_L_0,
1563   VEX_W_0FXOP_08_EC_L_0,
1564   VEX_W_0FXOP_08_ED_L_0,
1565   VEX_W_0FXOP_08_EE_L_0,
1566   VEX_W_0FXOP_08_EF_L_0,
1567
1568   VEX_W_0FXOP_09_80,
1569   VEX_W_0FXOP_09_81,
1570   VEX_W_0FXOP_09_82,
1571   VEX_W_0FXOP_09_83,
1572   VEX_W_0FXOP_09_C1_L_0,
1573   VEX_W_0FXOP_09_C2_L_0,
1574   VEX_W_0FXOP_09_C3_L_0,
1575   VEX_W_0FXOP_09_C6_L_0,
1576   VEX_W_0FXOP_09_C7_L_0,
1577   VEX_W_0FXOP_09_CB_L_0,
1578   VEX_W_0FXOP_09_D1_L_0,
1579   VEX_W_0FXOP_09_D2_L_0,
1580   VEX_W_0FXOP_09_D3_L_0,
1581   VEX_W_0FXOP_09_D6_L_0,
1582   VEX_W_0FXOP_09_D7_L_0,
1583   VEX_W_0FXOP_09_DB_L_0,
1584   VEX_W_0FXOP_09_E1_L_0,
1585   VEX_W_0FXOP_09_E2_L_0,
1586   VEX_W_0FXOP_09_E3_L_0,
1587
1588   EVEX_W_0F5B_P_0,
1589   EVEX_W_0F62,
1590   EVEX_W_0F66,
1591   EVEX_W_0F6A,
1592   EVEX_W_0F6B,
1593   EVEX_W_0F6C,
1594   EVEX_W_0F6D,
1595   EVEX_W_0F6F_P_1,
1596   EVEX_W_0F6F_P_2,
1597   EVEX_W_0F6F_P_3,
1598   EVEX_W_0F70_P_2,
1599   EVEX_W_0F72_R_2,
1600   EVEX_W_0F72_R_6,
1601   EVEX_W_0F73_R_2,
1602   EVEX_W_0F73_R_6,
1603   EVEX_W_0F76,
1604   EVEX_W_0F78_P_0,
1605   EVEX_W_0F78_P_2,
1606   EVEX_W_0F79_P_0,
1607   EVEX_W_0F79_P_2,
1608   EVEX_W_0F7A_P_1,
1609   EVEX_W_0F7A_P_2,
1610   EVEX_W_0F7A_P_3,
1611   EVEX_W_0F7B_P_2,
1612   EVEX_W_0F7E_P_1,
1613   EVEX_W_0F7F_P_1,
1614   EVEX_W_0F7F_P_2,
1615   EVEX_W_0F7F_P_3,
1616   EVEX_W_0FD2,
1617   EVEX_W_0FD3,
1618   EVEX_W_0FD4,
1619   EVEX_W_0FD6,
1620   EVEX_W_0FE6_P_1,
1621   EVEX_W_0FE7,
1622   EVEX_W_0FF2,
1623   EVEX_W_0FF3,
1624   EVEX_W_0FF4,
1625   EVEX_W_0FFA,
1626   EVEX_W_0FFB,
1627   EVEX_W_0FFE,
1628
1629   EVEX_W_0F3810_P_1,
1630   EVEX_W_0F3810_P_2,
1631   EVEX_W_0F3811_P_1,
1632   EVEX_W_0F3811_P_2,
1633   EVEX_W_0F3812_P_1,
1634   EVEX_W_0F3812_P_2,
1635   EVEX_W_0F3813_P_1,
1636   EVEX_W_0F3814_P_1,
1637   EVEX_W_0F3815_P_1,
1638   EVEX_W_0F3819_L_n,
1639   EVEX_W_0F381A_M_0_L_n,
1640   EVEX_W_0F381B_M_0_L_2,
1641   EVEX_W_0F381E,
1642   EVEX_W_0F381F,
1643   EVEX_W_0F3820_P_1,
1644   EVEX_W_0F3821_P_1,
1645   EVEX_W_0F3822_P_1,
1646   EVEX_W_0F3823_P_1,
1647   EVEX_W_0F3824_P_1,
1648   EVEX_W_0F3825_P_1,
1649   EVEX_W_0F3825_P_2,
1650   EVEX_W_0F3828_P_2,
1651   EVEX_W_0F3829_P_2,
1652   EVEX_W_0F382A_P_1,
1653   EVEX_W_0F382A_P_2,
1654   EVEX_W_0F382B,
1655   EVEX_W_0F3830_P_1,
1656   EVEX_W_0F3831_P_1,
1657   EVEX_W_0F3832_P_1,
1658   EVEX_W_0F3833_P_1,
1659   EVEX_W_0F3834_P_1,
1660   EVEX_W_0F3835_P_1,
1661   EVEX_W_0F3835_P_2,
1662   EVEX_W_0F3837,
1663   EVEX_W_0F383A_P_1,
1664   EVEX_W_0F3859,
1665   EVEX_W_0F385A_M_0_L_n,
1666   EVEX_W_0F385B_M_0_L_2,
1667   EVEX_W_0F3870,
1668   EVEX_W_0F3872_P_2,
1669   EVEX_W_0F387A,
1670   EVEX_W_0F387B,
1671   EVEX_W_0F3883,
1672
1673   EVEX_W_0F3A18_L_n,
1674   EVEX_W_0F3A19_L_n,
1675   EVEX_W_0F3A1A_L_2,
1676   EVEX_W_0F3A1B_L_2,
1677   EVEX_W_0F3A21,
1678   EVEX_W_0F3A23_L_n,
1679   EVEX_W_0F3A38_L_n,
1680   EVEX_W_0F3A39_L_n,
1681   EVEX_W_0F3A3A_L_2,
1682   EVEX_W_0F3A3B_L_2,
1683   EVEX_W_0F3A42,
1684   EVEX_W_0F3A43_L_n,
1685   EVEX_W_0F3A70,
1686   EVEX_W_0F3A72,
1687
1688   EVEX_W_MAP5_5B_P_0,
1689   EVEX_W_MAP5_7A_P_3,
1690 };
1691
1692 typedef void (*op_rtn) (instr_info *ins, int bytemode, int sizeflag);
1693
1694 struct dis386 {
1695   const char *name;
1696   struct
1697     {
1698       op_rtn rtn;
1699       int bytemode;
1700     } op[MAX_OPERANDS];
1701   unsigned int prefix_requirement;
1702 };
1703
1704 /* Upper case letters in the instruction names here are macros.
1705    'A' => print 'b' if no register operands or suffix_always is true
1706    'B' => print 'b' if suffix_always is true
1707    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1708           size prefix
1709    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1710           suffix_always is true
1711    'E' => print 'e' if 32-bit form of jcxz
1712    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1713    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1714    'H' => print ",pt" or ",pn" branch hint
1715    'I' unused.
1716    'J' unused.
1717    'K' => print 'd' or 'q' if rex prefix is present.
1718    'L' unused.
1719    'M' => print 'r' if intel_mnemonic is false.
1720    'N' => print 'n' if instruction has no wait "prefix"
1721    'O' => print 'd' or 'o' (or 'q' in Intel mode)
1722    'P' => behave as 'T' except with register operand outside of suffix_always
1723           mode
1724    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1725           is true
1726    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1727    'S' => print 'w', 'l' or 'q' if suffix_always is true
1728    'T' => print 'w', 'l'/'d', or 'q' if instruction has an operand size
1729           prefix or if suffix_always is true.
1730    'U' unused.
1731    'V' unused.
1732    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1733    'X' => print 's', 'd' depending on data16 prefix (for XMM)
1734    'Y' unused.
1735    'Z' => print 'q' in 64bit mode and 'l' otherwise, if suffix_always is true.
1736    '!' => change condition from true to false or from false to true.
1737    '%' => add 1 upper case letter to the macro.
1738    '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
1739           prefix or suffix_always is true (lcall/ljmp).
1740    '@' => in 64bit mode for Intel64 ISA or if instruction
1741           has no operand sizing prefix, print 'q' if suffix_always is true or
1742           nothing otherwise; behave as 'P' in all other cases
1743
1744    2 upper case letter macros:
1745    "XY" => print 'x' or 'y' if suffix_always is true or no register
1746            operands and no broadcast.
1747    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
1748            register operands and no broadcast.
1749    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1750    "XD" => print 'd' if !EVEX or EVEX.W=1, EVEX.W=0 is not a valid encoding
1751    "XH" => print 'h' if EVEX.W=0, EVEX.W=1 is not a valid encoding (for FP16)
1752    "XS" => print 's' if !EVEX or EVEX.W=0, EVEX.W=1 is not a valid encoding
1753    "XV" => print "{vex3}" pseudo prefix
1754    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond
1755            being false, or no operand at all in 64bit mode, or if suffix_always
1756            is true.
1757    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1758    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1759    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1760    "DQ" => print 'd' or 'q' depending on the VEX.W bit
1761    "BW" => print 'b' or 'w' depending on the VEX.W bit
1762    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
1763            an operand size prefix, or suffix_always is true.  print
1764            'q' if rex prefix is present.
1765
1766    Many of the above letters print nothing in Intel mode.  See "putop"
1767    for the details.
1768
1769    Braces '{' and '}', and vertical bars '|', indicate alternative
1770    mnemonic strings for AT&T and Intel.  */
1771
1772 static const struct dis386 dis386[] = {
1773   /* 00 */
1774   { "addB",             { Ebh1, Gb }, 0 },
1775   { "addS",             { Evh1, Gv }, 0 },
1776   { "addB",             { Gb, EbS }, 0 },
1777   { "addS",             { Gv, EvS }, 0 },
1778   { "addB",             { AL, Ib }, 0 },
1779   { "addS",             { eAX, Iv }, 0 },
1780   { X86_64_TABLE (X86_64_06) },
1781   { X86_64_TABLE (X86_64_07) },
1782   /* 08 */
1783   { "orB",              { Ebh1, Gb }, 0 },
1784   { "orS",              { Evh1, Gv }, 0 },
1785   { "orB",              { Gb, EbS }, 0 },
1786   { "orS",              { Gv, EvS }, 0 },
1787   { "orB",              { AL, Ib }, 0 },
1788   { "orS",              { eAX, Iv }, 0 },
1789   { X86_64_TABLE (X86_64_0E) },
1790   { Bad_Opcode },       /* 0x0f extended opcode escape */
1791   /* 10 */
1792   { "adcB",             { Ebh1, Gb }, 0 },
1793   { "adcS",             { Evh1, Gv }, 0 },
1794   { "adcB",             { Gb, EbS }, 0 },
1795   { "adcS",             { Gv, EvS }, 0 },
1796   { "adcB",             { AL, Ib }, 0 },
1797   { "adcS",             { eAX, Iv }, 0 },
1798   { X86_64_TABLE (X86_64_16) },
1799   { X86_64_TABLE (X86_64_17) },
1800   /* 18 */
1801   { "sbbB",             { Ebh1, Gb }, 0 },
1802   { "sbbS",             { Evh1, Gv }, 0 },
1803   { "sbbB",             { Gb, EbS }, 0 },
1804   { "sbbS",             { Gv, EvS }, 0 },
1805   { "sbbB",             { AL, Ib }, 0 },
1806   { "sbbS",             { eAX, Iv }, 0 },
1807   { X86_64_TABLE (X86_64_1E) },
1808   { X86_64_TABLE (X86_64_1F) },
1809   /* 20 */
1810   { "andB",             { Ebh1, Gb }, 0 },
1811   { "andS",             { Evh1, Gv }, 0 },
1812   { "andB",             { Gb, EbS }, 0 },
1813   { "andS",             { Gv, EvS }, 0 },
1814   { "andB",             { AL, Ib }, 0 },
1815   { "andS",             { eAX, Iv }, 0 },
1816   { Bad_Opcode },       /* SEG ES prefix */
1817   { X86_64_TABLE (X86_64_27) },
1818   /* 28 */
1819   { "subB",             { Ebh1, Gb }, 0 },
1820   { "subS",             { Evh1, Gv }, 0 },
1821   { "subB",             { Gb, EbS }, 0 },
1822   { "subS",             { Gv, EvS }, 0 },
1823   { "subB",             { AL, Ib }, 0 },
1824   { "subS",             { eAX, Iv }, 0 },
1825   { Bad_Opcode },       /* SEG CS prefix */
1826   { X86_64_TABLE (X86_64_2F) },
1827   /* 30 */
1828   { "xorB",             { Ebh1, Gb }, 0 },
1829   { "xorS",             { Evh1, Gv }, 0 },
1830   { "xorB",             { Gb, EbS }, 0 },
1831   { "xorS",             { Gv, EvS }, 0 },
1832   { "xorB",             { AL, Ib }, 0 },
1833   { "xorS",             { eAX, Iv }, 0 },
1834   { Bad_Opcode },       /* SEG SS prefix */
1835   { X86_64_TABLE (X86_64_37) },
1836   /* 38 */
1837   { "cmpB",             { Eb, Gb }, 0 },
1838   { "cmpS",             { Ev, Gv }, 0 },
1839   { "cmpB",             { Gb, EbS }, 0 },
1840   { "cmpS",             { Gv, EvS }, 0 },
1841   { "cmpB",             { AL, Ib }, 0 },
1842   { "cmpS",             { eAX, Iv }, 0 },
1843   { Bad_Opcode },       /* SEG DS prefix */
1844   { X86_64_TABLE (X86_64_3F) },
1845   /* 40 */
1846   { "inc{S|}",          { RMeAX }, 0 },
1847   { "inc{S|}",          { RMeCX }, 0 },
1848   { "inc{S|}",          { RMeDX }, 0 },
1849   { "inc{S|}",          { RMeBX }, 0 },
1850   { "inc{S|}",          { RMeSP }, 0 },
1851   { "inc{S|}",          { RMeBP }, 0 },
1852   { "inc{S|}",          { RMeSI }, 0 },
1853   { "inc{S|}",          { RMeDI }, 0 },
1854   /* 48 */
1855   { "dec{S|}",          { RMeAX }, 0 },
1856   { "dec{S|}",          { RMeCX }, 0 },
1857   { "dec{S|}",          { RMeDX }, 0 },
1858   { "dec{S|}",          { RMeBX }, 0 },
1859   { "dec{S|}",          { RMeSP }, 0 },
1860   { "dec{S|}",          { RMeBP }, 0 },
1861   { "dec{S|}",          { RMeSI }, 0 },
1862   { "dec{S|}",          { RMeDI }, 0 },
1863   /* 50 */
1864   { "push{!P|}",                { RMrAX }, 0 },
1865   { "push{!P|}",                { RMrCX }, 0 },
1866   { "push{!P|}",                { RMrDX }, 0 },
1867   { "push{!P|}",                { RMrBX }, 0 },
1868   { "push{!P|}",                { RMrSP }, 0 },
1869   { "push{!P|}",                { RMrBP }, 0 },
1870   { "push{!P|}",                { RMrSI }, 0 },
1871   { "push{!P|}",                { RMrDI }, 0 },
1872   /* 58 */
1873   { "pop{!P|}",         { RMrAX }, 0 },
1874   { "pop{!P|}",         { RMrCX }, 0 },
1875   { "pop{!P|}",         { RMrDX }, 0 },
1876   { "pop{!P|}",         { RMrBX }, 0 },
1877   { "pop{!P|}",         { RMrSP }, 0 },
1878   { "pop{!P|}",         { RMrBP }, 0 },
1879   { "pop{!P|}",         { RMrSI }, 0 },
1880   { "pop{!P|}",         { RMrDI }, 0 },
1881   /* 60 */
1882   { X86_64_TABLE (X86_64_60) },
1883   { X86_64_TABLE (X86_64_61) },
1884   { X86_64_TABLE (X86_64_62) },
1885   { X86_64_TABLE (X86_64_63) },
1886   { Bad_Opcode },       /* seg fs */
1887   { Bad_Opcode },       /* seg gs */
1888   { Bad_Opcode },       /* op size prefix */
1889   { Bad_Opcode },       /* adr size prefix */
1890   /* 68 */
1891   { "pushP",            { sIv }, 0 },
1892   { "imulS",            { Gv, Ev, Iv }, 0 },
1893   { "pushP",            { sIbT }, 0 },
1894   { "imulS",            { Gv, Ev, sIb }, 0 },
1895   { "ins{b|}",          { Ybr, indirDX }, 0 },
1896   { X86_64_TABLE (X86_64_6D) },
1897   { "outs{b|}",         { indirDXr, Xb }, 0 },
1898   { X86_64_TABLE (X86_64_6F) },
1899   /* 70 */
1900   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
1901   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
1902   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
1903   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
1904   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
1905   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
1906   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
1907   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
1908   /* 78 */
1909   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
1910   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
1911   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
1912   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
1913   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
1914   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
1915   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
1916   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
1917   /* 80 */
1918   { REG_TABLE (REG_80) },
1919   { REG_TABLE (REG_81) },
1920   { X86_64_TABLE (X86_64_82) },
1921   { REG_TABLE (REG_83) },
1922   { "testB",            { Eb, Gb }, 0 },
1923   { "testS",            { Ev, Gv }, 0 },
1924   { "xchgB",            { Ebh2, Gb }, 0 },
1925   { "xchgS",            { Evh2, Gv }, 0 },
1926   /* 88 */
1927   { "movB",             { Ebh3, Gb }, 0 },
1928   { "movS",             { Evh3, Gv }, 0 },
1929   { "movB",             { Gb, EbS }, 0 },
1930   { "movS",             { Gv, EvS }, 0 },
1931   { "movD",             { Sv, Sw }, 0 },
1932   { MOD_TABLE (MOD_8D) },
1933   { "movD",             { Sw, Sv }, 0 },
1934   { REG_TABLE (REG_8F) },
1935   /* 90 */
1936   { PREFIX_TABLE (PREFIX_90) },
1937   { "xchgS",            { RMeCX, eAX }, 0 },
1938   { "xchgS",            { RMeDX, eAX }, 0 },
1939   { "xchgS",            { RMeBX, eAX }, 0 },
1940   { "xchgS",            { RMeSP, eAX }, 0 },
1941   { "xchgS",            { RMeBP, eAX }, 0 },
1942   { "xchgS",            { RMeSI, eAX }, 0 },
1943   { "xchgS",            { RMeDI, eAX }, 0 },
1944   /* 98 */
1945   { "cW{t|}R",          { XX }, 0 },
1946   { "cR{t|}O",          { XX }, 0 },
1947   { X86_64_TABLE (X86_64_9A) },
1948   { Bad_Opcode },       /* fwait */
1949   { "pushfP",           { XX }, 0 },
1950   { "popfP",            { XX }, 0 },
1951   { "sahf",             { XX }, 0 },
1952   { "lahf",             { XX }, 0 },
1953   /* a0 */
1954   { "mov%LB",           { AL, Ob }, 0 },
1955   { "mov%LS",           { eAX, Ov }, 0 },
1956   { "mov%LB",           { Ob, AL }, 0 },
1957   { "mov%LS",           { Ov, eAX }, 0 },
1958   { "movs{b|}",         { Ybr, Xb }, 0 },
1959   { "movs{R|}",         { Yvr, Xv }, 0 },
1960   { "cmps{b|}",         { Xb, Yb }, 0 },
1961   { "cmps{R|}",         { Xv, Yv }, 0 },
1962   /* a8 */
1963   { "testB",            { AL, Ib }, 0 },
1964   { "testS",            { eAX, Iv }, 0 },
1965   { "stosB",            { Ybr, AL }, 0 },
1966   { "stosS",            { Yvr, eAX }, 0 },
1967   { "lodsB",            { ALr, Xb }, 0 },
1968   { "lodsS",            { eAXr, Xv }, 0 },
1969   { "scasB",            { AL, Yb }, 0 },
1970   { "scasS",            { eAX, Yv }, 0 },
1971   /* b0 */
1972   { "movB",             { RMAL, Ib }, 0 },
1973   { "movB",             { RMCL, Ib }, 0 },
1974   { "movB",             { RMDL, Ib }, 0 },
1975   { "movB",             { RMBL, Ib }, 0 },
1976   { "movB",             { RMAH, Ib }, 0 },
1977   { "movB",             { RMCH, Ib }, 0 },
1978   { "movB",             { RMDH, Ib }, 0 },
1979   { "movB",             { RMBH, Ib }, 0 },
1980   /* b8 */
1981   { "mov%LV",           { RMeAX, Iv64 }, 0 },
1982   { "mov%LV",           { RMeCX, Iv64 }, 0 },
1983   { "mov%LV",           { RMeDX, Iv64 }, 0 },
1984   { "mov%LV",           { RMeBX, Iv64 }, 0 },
1985   { "mov%LV",           { RMeSP, Iv64 }, 0 },
1986   { "mov%LV",           { RMeBP, Iv64 }, 0 },
1987   { "mov%LV",           { RMeSI, Iv64 }, 0 },
1988   { "mov%LV",           { RMeDI, Iv64 }, 0 },
1989   /* c0 */
1990   { REG_TABLE (REG_C0) },
1991   { REG_TABLE (REG_C1) },
1992   { X86_64_TABLE (X86_64_C2) },
1993   { X86_64_TABLE (X86_64_C3) },
1994   { X86_64_TABLE (X86_64_C4) },
1995   { X86_64_TABLE (X86_64_C5) },
1996   { REG_TABLE (REG_C6) },
1997   { REG_TABLE (REG_C7) },
1998   /* c8 */
1999   { "enterP",           { Iw, Ib }, 0 },
2000   { "leaveP",           { XX }, 0 },
2001   { "{l|}ret{|f}%LP",   { Iw }, 0 },
2002   { "{l|}ret{|f}%LP",   { XX }, 0 },
2003   { "int3",             { XX }, 0 },
2004   { "int",              { Ib }, 0 },
2005   { X86_64_TABLE (X86_64_CE) },
2006   { "iret%LP",          { XX }, 0 },
2007   /* d0 */
2008   { REG_TABLE (REG_D0) },
2009   { REG_TABLE (REG_D1) },
2010   { REG_TABLE (REG_D2) },
2011   { REG_TABLE (REG_D3) },
2012   { X86_64_TABLE (X86_64_D4) },
2013   { X86_64_TABLE (X86_64_D5) },
2014   { Bad_Opcode },
2015   { "xlat",             { DSBX }, 0 },
2016   /* d8 */
2017   { FLOAT },
2018   { FLOAT },
2019   { FLOAT },
2020   { FLOAT },
2021   { FLOAT },
2022   { FLOAT },
2023   { FLOAT },
2024   { FLOAT },
2025   /* e0 */
2026   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2027   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2028   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2029   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2030   { "inB",              { AL, Ib }, 0 },
2031   { "inG",              { zAX, Ib }, 0 },
2032   { "outB",             { Ib, AL }, 0 },
2033   { "outG",             { Ib, zAX }, 0 },
2034   /* e8 */
2035   { X86_64_TABLE (X86_64_E8) },
2036   { X86_64_TABLE (X86_64_E9) },
2037   { X86_64_TABLE (X86_64_EA) },
2038   { "jmp",              { Jb, BND }, 0 },
2039   { "inB",              { AL, indirDX }, 0 },
2040   { "inG",              { zAX, indirDX }, 0 },
2041   { "outB",             { indirDX, AL }, 0 },
2042   { "outG",             { indirDX, zAX }, 0 },
2043   /* f0 */
2044   { Bad_Opcode },       /* lock prefix */
2045   { "int1",             { XX }, 0 },
2046   { Bad_Opcode },       /* repne */
2047   { Bad_Opcode },       /* repz */
2048   { "hlt",              { XX }, 0 },
2049   { "cmc",              { XX }, 0 },
2050   { REG_TABLE (REG_F6) },
2051   { REG_TABLE (REG_F7) },
2052   /* f8 */
2053   { "clc",              { XX }, 0 },
2054   { "stc",              { XX }, 0 },
2055   { "cli",              { XX }, 0 },
2056   { "sti",              { XX }, 0 },
2057   { "cld",              { XX }, 0 },
2058   { "std",              { XX }, 0 },
2059   { REG_TABLE (REG_FE) },
2060   { REG_TABLE (REG_FF) },
2061 };
2062
2063 static const struct dis386 dis386_twobyte[] = {
2064   /* 00 */
2065   { REG_TABLE (REG_0F00 ) },
2066   { REG_TABLE (REG_0F01 ) },
2067   { "larS",             { Gv, Ew }, 0 },
2068   { "lslS",             { Gv, Ew }, 0 },
2069   { Bad_Opcode },
2070   { "syscall",          { XX }, 0 },
2071   { "clts",             { XX }, 0 },
2072   { "sysret%LQ",                { XX }, 0 },
2073   /* 08 */
2074   { "invd",             { XX }, 0 },
2075   { PREFIX_TABLE (PREFIX_0F09) },
2076   { Bad_Opcode },
2077   { "ud2",              { XX }, 0 },
2078   { Bad_Opcode },
2079   { REG_TABLE (REG_0F0D) },
2080   { "femms",            { XX }, 0 },
2081   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2082   /* 10 */
2083   { PREFIX_TABLE (PREFIX_0F10) },
2084   { PREFIX_TABLE (PREFIX_0F11) },
2085   { PREFIX_TABLE (PREFIX_0F12) },
2086   { MOD_TABLE (MOD_0F13) },
2087   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2088   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2089   { PREFIX_TABLE (PREFIX_0F16) },
2090   { MOD_TABLE (MOD_0F17) },
2091   /* 18 */
2092   { REG_TABLE (REG_0F18) },
2093   { "nopQ",             { Ev }, 0 },
2094   { PREFIX_TABLE (PREFIX_0F1A) },
2095   { PREFIX_TABLE (PREFIX_0F1B) },
2096   { PREFIX_TABLE (PREFIX_0F1C) },
2097   { "nopQ",             { Ev }, 0 },
2098   { PREFIX_TABLE (PREFIX_0F1E) },
2099   { "nopQ",             { Ev }, 0 },
2100   /* 20 */
2101   { "movZ",             { Em, Cm }, 0 },
2102   { "movZ",             { Em, Dm }, 0 },
2103   { "movZ",             { Cm, Em }, 0 },
2104   { "movZ",             { Dm, Em }, 0 },
2105   { X86_64_TABLE (X86_64_0F24) },
2106   { Bad_Opcode },
2107   { X86_64_TABLE (X86_64_0F26) },
2108   { Bad_Opcode },
2109   /* 28 */
2110   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2111   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2112   { PREFIX_TABLE (PREFIX_0F2A) },
2113   { PREFIX_TABLE (PREFIX_0F2B) },
2114   { PREFIX_TABLE (PREFIX_0F2C) },
2115   { PREFIX_TABLE (PREFIX_0F2D) },
2116   { PREFIX_TABLE (PREFIX_0F2E) },
2117   { PREFIX_TABLE (PREFIX_0F2F) },
2118   /* 30 */
2119   { "wrmsr",            { XX }, 0 },
2120   { "rdtsc",            { XX }, 0 },
2121   { "rdmsr",            { XX }, 0 },
2122   { "rdpmc",            { XX }, 0 },
2123   { "sysenter",         { SEP }, 0 },
2124   { "sysexit%LQ",       { SEP }, 0 },
2125   { Bad_Opcode },
2126   { "getsec",           { XX }, 0 },
2127   /* 38 */
2128   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2129   { Bad_Opcode },
2130   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2131   { Bad_Opcode },
2132   { Bad_Opcode },
2133   { Bad_Opcode },
2134   { Bad_Opcode },
2135   { Bad_Opcode },
2136   /* 40 */
2137   { "cmovoS",           { Gv, Ev }, 0 },
2138   { "cmovnoS",          { Gv, Ev }, 0 },
2139   { "cmovbS",           { Gv, Ev }, 0 },
2140   { "cmovaeS",          { Gv, Ev }, 0 },
2141   { "cmoveS",           { Gv, Ev }, 0 },
2142   { "cmovneS",          { Gv, Ev }, 0 },
2143   { "cmovbeS",          { Gv, Ev }, 0 },
2144   { "cmovaS",           { Gv, Ev }, 0 },
2145   /* 48 */
2146   { "cmovsS",           { Gv, Ev }, 0 },
2147   { "cmovnsS",          { Gv, Ev }, 0 },
2148   { "cmovpS",           { Gv, Ev }, 0 },
2149   { "cmovnpS",          { Gv, Ev }, 0 },
2150   { "cmovlS",           { Gv, Ev }, 0 },
2151   { "cmovgeS",          { Gv, Ev }, 0 },
2152   { "cmovleS",          { Gv, Ev }, 0 },
2153   { "cmovgS",           { Gv, Ev }, 0 },
2154   /* 50 */
2155   { MOD_TABLE (MOD_0F50) },
2156   { PREFIX_TABLE (PREFIX_0F51) },
2157   { PREFIX_TABLE (PREFIX_0F52) },
2158   { PREFIX_TABLE (PREFIX_0F53) },
2159   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2160   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2161   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2162   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2163   /* 58 */
2164   { PREFIX_TABLE (PREFIX_0F58) },
2165   { PREFIX_TABLE (PREFIX_0F59) },
2166   { PREFIX_TABLE (PREFIX_0F5A) },
2167   { PREFIX_TABLE (PREFIX_0F5B) },
2168   { PREFIX_TABLE (PREFIX_0F5C) },
2169   { PREFIX_TABLE (PREFIX_0F5D) },
2170   { PREFIX_TABLE (PREFIX_0F5E) },
2171   { PREFIX_TABLE (PREFIX_0F5F) },
2172   /* 60 */
2173   { PREFIX_TABLE (PREFIX_0F60) },
2174   { PREFIX_TABLE (PREFIX_0F61) },
2175   { PREFIX_TABLE (PREFIX_0F62) },
2176   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2177   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2178   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2179   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2180   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2181   /* 68 */
2182   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2183   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2184   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2185   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2186   { "punpcklqdq", { XM, EXx }, PREFIX_DATA },
2187   { "punpckhqdq", { XM, EXx }, PREFIX_DATA },
2188   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2189   { PREFIX_TABLE (PREFIX_0F6F) },
2190   /* 70 */
2191   { PREFIX_TABLE (PREFIX_0F70) },
2192   { MOD_TABLE (MOD_0F71) },
2193   { MOD_TABLE (MOD_0F72) },
2194   { MOD_TABLE (MOD_0F73) },
2195   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2196   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2197   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2198   { "emms",             { XX }, PREFIX_OPCODE },
2199   /* 78 */
2200   { PREFIX_TABLE (PREFIX_0F78) },
2201   { PREFIX_TABLE (PREFIX_0F79) },
2202   { Bad_Opcode },
2203   { Bad_Opcode },
2204   { PREFIX_TABLE (PREFIX_0F7C) },
2205   { PREFIX_TABLE (PREFIX_0F7D) },
2206   { PREFIX_TABLE (PREFIX_0F7E) },
2207   { PREFIX_TABLE (PREFIX_0F7F) },
2208   /* 80 */
2209   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2210   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2211   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2212   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2213   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2214   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2215   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2216   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2217   /* 88 */
2218   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2219   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2220   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2221   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2222   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2223   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2224   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2225   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2226   /* 90 */
2227   { "seto",             { Eb }, 0 },
2228   { "setno",            { Eb }, 0 },
2229   { "setb",             { Eb }, 0 },
2230   { "setae",            { Eb }, 0 },
2231   { "sete",             { Eb }, 0 },
2232   { "setne",            { Eb }, 0 },
2233   { "setbe",            { Eb }, 0 },
2234   { "seta",             { Eb }, 0 },
2235   /* 98 */
2236   { "sets",             { Eb }, 0 },
2237   { "setns",            { Eb }, 0 },
2238   { "setp",             { Eb }, 0 },
2239   { "setnp",            { Eb }, 0 },
2240   { "setl",             { Eb }, 0 },
2241   { "setge",            { Eb }, 0 },
2242   { "setle",            { Eb }, 0 },
2243   { "setg",             { Eb }, 0 },
2244   /* a0 */
2245   { "pushP",            { fs }, 0 },
2246   { "popP",             { fs }, 0 },
2247   { "cpuid",            { XX }, 0 },
2248   { "btS",              { Ev, Gv }, 0 },
2249   { "shldS",            { Ev, Gv, Ib }, 0 },
2250   { "shldS",            { Ev, Gv, CL }, 0 },
2251   { REG_TABLE (REG_0FA6) },
2252   { REG_TABLE (REG_0FA7) },
2253   /* a8 */
2254   { "pushP",            { gs }, 0 },
2255   { "popP",             { gs }, 0 },
2256   { "rsm",              { XX }, 0 },
2257   { "btsS",             { Evh1, Gv }, 0 },
2258   { "shrdS",            { Ev, Gv, Ib }, 0 },
2259   { "shrdS",            { Ev, Gv, CL }, 0 },
2260   { REG_TABLE (REG_0FAE) },
2261   { "imulS",            { Gv, Ev }, 0 },
2262   /* b0 */
2263   { "cmpxchgB",         { Ebh1, Gb }, 0 },
2264   { "cmpxchgS",         { Evh1, Gv }, 0 },
2265   { MOD_TABLE (MOD_0FB2) },
2266   { "btrS",             { Evh1, Gv }, 0 },
2267   { MOD_TABLE (MOD_0FB4) },
2268   { MOD_TABLE (MOD_0FB5) },
2269   { "movz{bR|x}",       { Gv, Eb }, 0 },
2270   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2271   /* b8 */
2272   { PREFIX_TABLE (PREFIX_0FB8) },
2273   { "ud1S",             { Gv, Ev }, 0 },
2274   { REG_TABLE (REG_0FBA) },
2275   { "btcS",             { Evh1, Gv }, 0 },
2276   { PREFIX_TABLE (PREFIX_0FBC) },
2277   { PREFIX_TABLE (PREFIX_0FBD) },
2278   { "movs{bR|x}",       { Gv, Eb }, 0 },
2279   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2280   /* c0 */
2281   { "xaddB",            { Ebh1, Gb }, 0 },
2282   { "xaddS",            { Evh1, Gv }, 0 },
2283   { PREFIX_TABLE (PREFIX_0FC2) },
2284   { MOD_TABLE (MOD_0FC3) },
2285   { "pinsrw",           { MX, Edw, Ib }, PREFIX_OPCODE },
2286   { "pextrw",           { Gd, MS, Ib }, PREFIX_OPCODE },
2287   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
2288   { REG_TABLE (REG_0FC7) },
2289   /* c8 */
2290   { "bswap",            { RMeAX }, 0 },
2291   { "bswap",            { RMeCX }, 0 },
2292   { "bswap",            { RMeDX }, 0 },
2293   { "bswap",            { RMeBX }, 0 },
2294   { "bswap",            { RMeSP }, 0 },
2295   { "bswap",            { RMeBP }, 0 },
2296   { "bswap",            { RMeSI }, 0 },
2297   { "bswap",            { RMeDI }, 0 },
2298   /* d0 */
2299   { PREFIX_TABLE (PREFIX_0FD0) },
2300   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
2301   { "psrld",            { MX, EM }, PREFIX_OPCODE },
2302   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
2303   { "paddq",            { MX, EM }, PREFIX_OPCODE },
2304   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
2305   { PREFIX_TABLE (PREFIX_0FD6) },
2306   { MOD_TABLE (MOD_0FD7) },
2307   /* d8 */
2308   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
2309   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
2310   { "pminub",           { MX, EM }, PREFIX_OPCODE },
2311   { "pand",             { MX, EM }, PREFIX_OPCODE },
2312   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
2313   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
2314   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
2315   { "pandn",            { MX, EM }, PREFIX_OPCODE },
2316   /* e0 */
2317   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
2318   { "psraw",            { MX, EM }, PREFIX_OPCODE },
2319   { "psrad",            { MX, EM }, PREFIX_OPCODE },
2320   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
2321   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
2322   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
2323   { PREFIX_TABLE (PREFIX_0FE6) },
2324   { PREFIX_TABLE (PREFIX_0FE7) },
2325   /* e8 */
2326   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
2327   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
2328   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
2329   { "por",              { MX, EM }, PREFIX_OPCODE },
2330   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
2331   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
2332   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
2333   { "pxor",             { MX, EM }, PREFIX_OPCODE },
2334   /* f0 */
2335   { PREFIX_TABLE (PREFIX_0FF0) },
2336   { "psllw",            { MX, EM }, PREFIX_OPCODE },
2337   { "pslld",            { MX, EM }, PREFIX_OPCODE },
2338   { "psllq",            { MX, EM }, PREFIX_OPCODE },
2339   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
2340   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
2341   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
2342   { PREFIX_TABLE (PREFIX_0FF7) },
2343   /* f8 */
2344   { "psubb",            { MX, EM }, PREFIX_OPCODE },
2345   { "psubw",            { MX, EM }, PREFIX_OPCODE },
2346   { "psubd",            { MX, EM }, PREFIX_OPCODE },
2347   { "psubq",            { MX, EM }, PREFIX_OPCODE },
2348   { "paddb",            { MX, EM }, PREFIX_OPCODE },
2349   { "paddw",            { MX, EM }, PREFIX_OPCODE },
2350   { "paddd",            { MX, EM }, PREFIX_OPCODE },
2351   { "ud0S",             { Gv, Ev }, 0 },
2352 };
2353
2354 static const bool onebyte_has_modrm[256] = {
2355   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2356   /*       -------------------------------        */
2357   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2358   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2359   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2360   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2361   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2362   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2363   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2364   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2365   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2366   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2367   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2368   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2369   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2370   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2371   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2372   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2373   /*       -------------------------------        */
2374   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2375 };
2376
2377 static const bool twobyte_has_modrm[256] = {
2378   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2379   /*       -------------------------------        */
2380   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2381   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2382   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2383   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2384   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2385   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2386   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2387   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2388   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2389   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2390   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2391   /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2392   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2393   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2394   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2395   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1  /* ff */
2396   /*       -------------------------------        */
2397   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2398 };
2399
2400
2401 struct op
2402   {
2403     const char *name;
2404     unsigned int len;
2405   };
2406
2407 /* If we are accessing mod/rm/reg without need_modrm set, then the
2408    values are stale.  Hitting this abort likely indicates that you
2409    need to update onebyte_has_modrm or twobyte_has_modrm.  */
2410 #define MODRM_CHECK  if (!ins->need_modrm) abort ()
2411
2412 static const char *const intel_index16[] = {
2413   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2414 };
2415
2416 static const char *const att_names64[] = {
2417   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2418   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2419 };
2420 static const char *const att_names32[] = {
2421   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2422   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2423 };
2424 static const char *const att_names16[] = {
2425   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2426   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2427 };
2428 static const char *const att_names8[] = {
2429   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2430 };
2431 static const char *const att_names8rex[] = {
2432   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2433   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2434 };
2435 static const char *const att_names_seg[] = {
2436   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2437 };
2438 static const char att_index64[] = "%riz";
2439 static const char att_index32[] = "%eiz";
2440 static const char *const att_index16[] = {
2441   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2442 };
2443
2444 static const char *const att_names_mm[] = {
2445   "%mm0", "%mm1", "%mm2", "%mm3",
2446   "%mm4", "%mm5", "%mm6", "%mm7"
2447 };
2448
2449 static const char *const att_names_bnd[] = {
2450   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
2451 };
2452
2453 static const char *const att_names_xmm[] = {
2454   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2455   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2456   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2457   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
2458   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
2459   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
2460   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
2461   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
2462 };
2463
2464 static const char *const att_names_ymm[] = {
2465   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2466   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2467   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2468   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
2469   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
2470   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
2471   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
2472   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
2473 };
2474
2475 static const char *const att_names_zmm[] = {
2476   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
2477   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
2478   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
2479   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
2480   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
2481   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
2482   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
2483   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
2484 };
2485
2486 static const char *const att_names_tmm[] = {
2487   "%tmm0", "%tmm1", "%tmm2", "%tmm3",
2488   "%tmm4", "%tmm5", "%tmm6", "%tmm7"
2489 };
2490
2491 static const char *const att_names_mask[] = {
2492   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
2493 };
2494
2495 static const char *const names_rounding[] =
2496 {
2497   "{rn-",
2498   "{rd-",
2499   "{ru-",
2500   "{rz-"
2501 };
2502
2503 static const struct dis386 reg_table[][8] = {
2504   /* REG_80 */
2505   {
2506     { "addA",   { Ebh1, Ib }, 0 },
2507     { "orA",    { Ebh1, Ib }, 0 },
2508     { "adcA",   { Ebh1, Ib }, 0 },
2509     { "sbbA",   { Ebh1, Ib }, 0 },
2510     { "andA",   { Ebh1, Ib }, 0 },
2511     { "subA",   { Ebh1, Ib }, 0 },
2512     { "xorA",   { Ebh1, Ib }, 0 },
2513     { "cmpA",   { Eb, Ib }, 0 },
2514   },
2515   /* REG_81 */
2516   {
2517     { "addQ",   { Evh1, Iv }, 0 },
2518     { "orQ",    { Evh1, Iv }, 0 },
2519     { "adcQ",   { Evh1, Iv }, 0 },
2520     { "sbbQ",   { Evh1, Iv }, 0 },
2521     { "andQ",   { Evh1, Iv }, 0 },
2522     { "subQ",   { Evh1, Iv }, 0 },
2523     { "xorQ",   { Evh1, Iv }, 0 },
2524     { "cmpQ",   { Ev, Iv }, 0 },
2525   },
2526   /* REG_83 */
2527   {
2528     { "addQ",   { Evh1, sIb }, 0 },
2529     { "orQ",    { Evh1, sIb }, 0 },
2530     { "adcQ",   { Evh1, sIb }, 0 },
2531     { "sbbQ",   { Evh1, sIb }, 0 },
2532     { "andQ",   { Evh1, sIb }, 0 },
2533     { "subQ",   { Evh1, sIb }, 0 },
2534     { "xorQ",   { Evh1, sIb }, 0 },
2535     { "cmpQ",   { Ev, sIb }, 0 },
2536   },
2537   /* REG_8F */
2538   {
2539     { "pop{P|}", { stackEv }, 0 },
2540     { XOP_8F_TABLE (XOP_09) },
2541     { Bad_Opcode },
2542     { Bad_Opcode },
2543     { Bad_Opcode },
2544     { XOP_8F_TABLE (XOP_09) },
2545   },
2546   /* REG_C0 */
2547   {
2548     { "rolA",   { Eb, Ib }, 0 },
2549     { "rorA",   { Eb, Ib }, 0 },
2550     { "rclA",   { Eb, Ib }, 0 },
2551     { "rcrA",   { Eb, Ib }, 0 },
2552     { "shlA",   { Eb, Ib }, 0 },
2553     { "shrA",   { Eb, Ib }, 0 },
2554     { "shlA",   { Eb, Ib }, 0 },
2555     { "sarA",   { Eb, Ib }, 0 },
2556   },
2557   /* REG_C1 */
2558   {
2559     { "rolQ",   { Ev, Ib }, 0 },
2560     { "rorQ",   { Ev, Ib }, 0 },
2561     { "rclQ",   { Ev, Ib }, 0 },
2562     { "rcrQ",   { Ev, Ib }, 0 },
2563     { "shlQ",   { Ev, Ib }, 0 },
2564     { "shrQ",   { Ev, Ib }, 0 },
2565     { "shlQ",   { Ev, Ib }, 0 },
2566     { "sarQ",   { Ev, Ib }, 0 },
2567   },
2568   /* REG_C6 */
2569   {
2570     { "movA",   { Ebh3, Ib }, 0 },
2571     { Bad_Opcode },
2572     { Bad_Opcode },
2573     { Bad_Opcode },
2574     { Bad_Opcode },
2575     { Bad_Opcode },
2576     { Bad_Opcode },
2577     { MOD_TABLE (MOD_C6_REG_7) },
2578   },
2579   /* REG_C7 */
2580   {
2581     { "movQ",   { Evh3, Iv }, 0 },
2582     { Bad_Opcode },
2583     { Bad_Opcode },
2584     { Bad_Opcode },
2585     { Bad_Opcode },
2586     { Bad_Opcode },
2587     { Bad_Opcode },
2588     { MOD_TABLE (MOD_C7_REG_7) },
2589   },
2590   /* REG_D0 */
2591   {
2592     { "rolA",   { Eb, I1 }, 0 },
2593     { "rorA",   { Eb, I1 }, 0 },
2594     { "rclA",   { Eb, I1 }, 0 },
2595     { "rcrA",   { Eb, I1 }, 0 },
2596     { "shlA",   { Eb, I1 }, 0 },
2597     { "shrA",   { Eb, I1 }, 0 },
2598     { "shlA",   { Eb, I1 }, 0 },
2599     { "sarA",   { Eb, I1 }, 0 },
2600   },
2601   /* REG_D1 */
2602   {
2603     { "rolQ",   { Ev, I1 }, 0 },
2604     { "rorQ",   { Ev, I1 }, 0 },
2605     { "rclQ",   { Ev, I1 }, 0 },
2606     { "rcrQ",   { Ev, I1 }, 0 },
2607     { "shlQ",   { Ev, I1 }, 0 },
2608     { "shrQ",   { Ev, I1 }, 0 },
2609     { "shlQ",   { Ev, I1 }, 0 },
2610     { "sarQ",   { Ev, I1 }, 0 },
2611   },
2612   /* REG_D2 */
2613   {
2614     { "rolA",   { Eb, CL }, 0 },
2615     { "rorA",   { Eb, CL }, 0 },
2616     { "rclA",   { Eb, CL }, 0 },
2617     { "rcrA",   { Eb, CL }, 0 },
2618     { "shlA",   { Eb, CL }, 0 },
2619     { "shrA",   { Eb, CL }, 0 },
2620     { "shlA",   { Eb, CL }, 0 },
2621     { "sarA",   { Eb, CL }, 0 },
2622   },
2623   /* REG_D3 */
2624   {
2625     { "rolQ",   { Ev, CL }, 0 },
2626     { "rorQ",   { Ev, CL }, 0 },
2627     { "rclQ",   { Ev, CL }, 0 },
2628     { "rcrQ",   { Ev, CL }, 0 },
2629     { "shlQ",   { Ev, CL }, 0 },
2630     { "shrQ",   { Ev, CL }, 0 },
2631     { "shlQ",   { Ev, CL }, 0 },
2632     { "sarQ",   { Ev, CL }, 0 },
2633   },
2634   /* REG_F6 */
2635   {
2636     { "testA",  { Eb, Ib }, 0 },
2637     { "testA",  { Eb, Ib }, 0 },
2638     { "notA",   { Ebh1 }, 0 },
2639     { "negA",   { Ebh1 }, 0 },
2640     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
2641     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
2642     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
2643     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
2644   },
2645   /* REG_F7 */
2646   {
2647     { "testQ",  { Ev, Iv }, 0 },
2648     { "testQ",  { Ev, Iv }, 0 },
2649     { "notQ",   { Evh1 }, 0 },
2650     { "negQ",   { Evh1 }, 0 },
2651     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
2652     { "imulQ",  { Ev }, 0 },
2653     { "divQ",   { Ev }, 0 },
2654     { "idivQ",  { Ev }, 0 },
2655   },
2656   /* REG_FE */
2657   {
2658     { "incA",   { Ebh1 }, 0 },
2659     { "decA",   { Ebh1 }, 0 },
2660   },
2661   /* REG_FF */
2662   {
2663     { "incQ",   { Evh1 }, 0 },
2664     { "decQ",   { Evh1 }, 0 },
2665     { "call{@|}", { NOTRACK, indirEv, BND }, 0 },
2666     { MOD_TABLE (MOD_FF_REG_3) },
2667     { "jmp{@|}", { NOTRACK, indirEv, BND }, 0 },
2668     { MOD_TABLE (MOD_FF_REG_5) },
2669     { "push{P|}", { stackEv }, 0 },
2670     { Bad_Opcode },
2671   },
2672   /* REG_0F00 */
2673   {
2674     { "sldtD",  { Sv }, 0 },
2675     { "strD",   { Sv }, 0 },
2676     { "lldt",   { Ew }, 0 },
2677     { "ltr",    { Ew }, 0 },
2678     { "verr",   { Ew }, 0 },
2679     { "verw",   { Ew }, 0 },
2680     { Bad_Opcode },
2681     { Bad_Opcode },
2682   },
2683   /* REG_0F01 */
2684   {
2685     { MOD_TABLE (MOD_0F01_REG_0) },
2686     { MOD_TABLE (MOD_0F01_REG_1) },
2687     { MOD_TABLE (MOD_0F01_REG_2) },
2688     { MOD_TABLE (MOD_0F01_REG_3) },
2689     { "smswD",  { Sv }, 0 },
2690     { MOD_TABLE (MOD_0F01_REG_5) },
2691     { "lmsw",   { Ew }, 0 },
2692     { MOD_TABLE (MOD_0F01_REG_7) },
2693   },
2694   /* REG_0F0D */
2695   {
2696     { "prefetch",       { Mb }, 0 },
2697     { "prefetchw",      { Mb }, 0 },
2698     { "prefetchwt1",    { Mb }, 0 },
2699     { "prefetch",       { Mb }, 0 },
2700     { "prefetch",       { Mb }, 0 },
2701     { "prefetch",       { Mb }, 0 },
2702     { "prefetch",       { Mb }, 0 },
2703     { "prefetch",       { Mb }, 0 },
2704   },
2705   /* REG_0F18 */
2706   {
2707     { MOD_TABLE (MOD_0F18_REG_0) },
2708     { MOD_TABLE (MOD_0F18_REG_1) },
2709     { MOD_TABLE (MOD_0F18_REG_2) },
2710     { MOD_TABLE (MOD_0F18_REG_3) },
2711     { "nopQ",           { Ev }, 0 },
2712     { "nopQ",           { Ev }, 0 },
2713     { "nopQ",           { Ev }, 0 },
2714     { "nopQ",           { Ev }, 0 },
2715   },
2716   /* REG_0F1C_P_0_MOD_0 */
2717   {
2718     { "cldemote",       { Mb }, 0 },
2719     { "nopQ",           { Ev }, 0 },
2720     { "nopQ",           { Ev }, 0 },
2721     { "nopQ",           { Ev }, 0 },
2722     { "nopQ",           { Ev }, 0 },
2723     { "nopQ",           { Ev }, 0 },
2724     { "nopQ",           { Ev }, 0 },
2725     { "nopQ",           { Ev }, 0 },
2726   },
2727   /* REG_0F1E_P_1_MOD_3 */
2728   {
2729     { "nopQ",           { Ev }, PREFIX_IGNORED },
2730     { "rdsspK",         { Edq }, 0 },
2731     { "nopQ",           { Ev }, PREFIX_IGNORED },
2732     { "nopQ",           { Ev }, PREFIX_IGNORED },
2733     { "nopQ",           { Ev }, PREFIX_IGNORED },
2734     { "nopQ",           { Ev }, PREFIX_IGNORED },
2735     { "nopQ",           { Ev }, PREFIX_IGNORED },
2736     { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) },
2737   },
2738   /* REG_0F38D8_PREFIX_1 */
2739   {
2740     { "aesencwide128kl",        { M }, 0 },
2741     { "aesdecwide128kl",        { M }, 0 },
2742     { "aesencwide256kl",        { M }, 0 },
2743     { "aesdecwide256kl",        { M }, 0 },
2744   },
2745   /* REG_0F3A0F_PREFIX_1_MOD_3 */
2746   {
2747     { RM_TABLE (RM_0F3A0F_P_1_MOD_3_REG_0) },
2748   },
2749   /* REG_0F71_MOD_0 */
2750   {
2751     { Bad_Opcode },
2752     { Bad_Opcode },
2753     { "psrlw",          { MS, Ib }, PREFIX_OPCODE },
2754     { Bad_Opcode },
2755     { "psraw",          { MS, Ib }, PREFIX_OPCODE },
2756     { Bad_Opcode },
2757     { "psllw",          { MS, Ib }, PREFIX_OPCODE },
2758   },
2759   /* REG_0F72_MOD_0 */
2760   {
2761     { Bad_Opcode },
2762     { Bad_Opcode },
2763     { "psrld",          { MS, Ib }, PREFIX_OPCODE },
2764     { Bad_Opcode },
2765     { "psrad",          { MS, Ib }, PREFIX_OPCODE },
2766     { Bad_Opcode },
2767     { "pslld",          { MS, Ib }, PREFIX_OPCODE },
2768   },
2769   /* REG_0F73_MOD_0 */
2770   {
2771     { Bad_Opcode },
2772     { Bad_Opcode },
2773     { "psrlq",          { MS, Ib }, PREFIX_OPCODE },
2774     { "psrldq",         { XS, Ib }, PREFIX_DATA },
2775     { Bad_Opcode },
2776     { Bad_Opcode },
2777     { "psllq",          { MS, Ib }, PREFIX_OPCODE },
2778     { "pslldq",         { XS, Ib }, PREFIX_DATA },
2779   },
2780   /* REG_0FA6 */
2781   {
2782     { "montmul",        { { OP_0f07, 0 } }, 0 },
2783     { "xsha1",          { { OP_0f07, 0 } }, 0 },
2784     { "xsha256",        { { OP_0f07, 0 } }, 0 },
2785   },
2786   /* REG_0FA7 */
2787   {
2788     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
2789     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
2790     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
2791     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
2792     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
2793     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
2794   },
2795   /* REG_0FAE */
2796   {
2797     { MOD_TABLE (MOD_0FAE_REG_0) },
2798     { MOD_TABLE (MOD_0FAE_REG_1) },
2799     { MOD_TABLE (MOD_0FAE_REG_2) },
2800     { MOD_TABLE (MOD_0FAE_REG_3) },
2801     { MOD_TABLE (MOD_0FAE_REG_4) },
2802     { MOD_TABLE (MOD_0FAE_REG_5) },
2803     { MOD_TABLE (MOD_0FAE_REG_6) },
2804     { MOD_TABLE (MOD_0FAE_REG_7) },
2805   },
2806   /* REG_0FBA */
2807   {
2808     { Bad_Opcode },
2809     { Bad_Opcode },
2810     { Bad_Opcode },
2811     { Bad_Opcode },
2812     { "btQ",    { Ev, Ib }, 0 },
2813     { "btsQ",   { Evh1, Ib }, 0 },
2814     { "btrQ",   { Evh1, Ib }, 0 },
2815     { "btcQ",   { Evh1, Ib }, 0 },
2816   },
2817   /* REG_0FC7 */
2818   {
2819     { Bad_Opcode },
2820     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
2821     { Bad_Opcode },
2822     { MOD_TABLE (MOD_0FC7_REG_3) },
2823     { MOD_TABLE (MOD_0FC7_REG_4) },
2824     { MOD_TABLE (MOD_0FC7_REG_5) },
2825     { MOD_TABLE (MOD_0FC7_REG_6) },
2826     { MOD_TABLE (MOD_0FC7_REG_7) },
2827   },
2828   /* REG_VEX_0F71_M_0 */
2829   {
2830     { Bad_Opcode },
2831     { Bad_Opcode },
2832     { "vpsrlw",         { Vex, XS, Ib }, PREFIX_DATA },
2833     { Bad_Opcode },
2834     { "vpsraw",         { Vex, XS, Ib }, PREFIX_DATA },
2835     { Bad_Opcode },
2836     { "vpsllw",         { Vex, XS, Ib }, PREFIX_DATA },
2837   },
2838   /* REG_VEX_0F72_M_0 */
2839   {
2840     { Bad_Opcode },
2841     { Bad_Opcode },
2842     { "vpsrld",         { Vex, XS, Ib }, PREFIX_DATA },
2843     { Bad_Opcode },
2844     { "vpsrad",         { Vex, XS, Ib }, PREFIX_DATA },
2845     { Bad_Opcode },
2846     { "vpslld",         { Vex, XS, Ib }, PREFIX_DATA },
2847   },
2848   /* REG_VEX_0F73_M_0 */
2849   {
2850     { Bad_Opcode },
2851     { Bad_Opcode },
2852     { "vpsrlq",         { Vex, XS, Ib }, PREFIX_DATA },
2853     { "vpsrldq",        { Vex, XS, Ib }, PREFIX_DATA },
2854     { Bad_Opcode },
2855     { Bad_Opcode },
2856     { "vpsllq",         { Vex, XS, Ib }, PREFIX_DATA },
2857     { "vpslldq",        { Vex, XS, Ib }, PREFIX_DATA },
2858   },
2859   /* REG_VEX_0FAE */
2860   {
2861     { Bad_Opcode },
2862     { Bad_Opcode },
2863     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
2864     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
2865   },
2866   /* REG_VEX_0F3849_X86_64_P_0_W_0_M_1 */
2867   {
2868     { RM_TABLE (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0) },
2869   },
2870   /* REG_VEX_0F38F3_L_0 */
2871   {
2872     { Bad_Opcode },
2873     { "blsrS",          { VexGdq, Edq }, PREFIX_OPCODE },
2874     { "blsmskS",        { VexGdq, Edq }, PREFIX_OPCODE },
2875     { "blsiS",          { VexGdq, Edq }, PREFIX_OPCODE },
2876   },
2877   /* REG_XOP_09_01_L_0 */
2878   {
2879     { Bad_Opcode },
2880     { "blcfill",        { VexGdq, Edq }, 0 },
2881     { "blsfill",        { VexGdq, Edq }, 0 },
2882     { "blcs",   { VexGdq, Edq }, 0 },
2883     { "tzmsk",  { VexGdq, Edq }, 0 },
2884     { "blcic",  { VexGdq, Edq }, 0 },
2885     { "blsic",  { VexGdq, Edq }, 0 },
2886     { "t1mskc", { VexGdq, Edq }, 0 },
2887   },
2888   /* REG_XOP_09_02_L_0 */
2889   {
2890     { Bad_Opcode },
2891     { "blcmsk", { VexGdq, Edq }, 0 },
2892     { Bad_Opcode },
2893     { Bad_Opcode },
2894     { Bad_Opcode },
2895     { Bad_Opcode },
2896     { "blci",   { VexGdq, Edq }, 0 },
2897   },
2898   /* REG_XOP_09_12_M_1_L_0 */
2899   {
2900     { "llwpcb", { Edq }, 0 },
2901     { "slwpcb", { Edq }, 0 },
2902   },
2903   /* REG_XOP_0A_12_L_0 */
2904   {
2905     { "lwpins", { VexGdq, Ed, Id }, 0 },
2906     { "lwpval", { VexGdq, Ed, Id }, 0 },
2907   },
2908
2909 #include "i386-dis-evex-reg.h"
2910 };
2911
2912 static const struct dis386 prefix_table[][4] = {
2913   /* PREFIX_90 */
2914   {
2915     { "xchgS", { { NOP_Fixup, 0 }, { NOP_Fixup, 1 } }, 0 },
2916     { "pause", { XX }, 0 },
2917     { "xchgS", { { NOP_Fixup, 0 }, { NOP_Fixup, 1 } }, 0 },
2918     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
2919   },
2920
2921   /* PREFIX_0F01_REG_1_RM_4 */
2922   {
2923     { Bad_Opcode },
2924     { Bad_Opcode },
2925     { "tdcall",         { Skip_MODRM }, 0 },
2926     { Bad_Opcode },
2927   },
2928
2929   /* PREFIX_0F01_REG_1_RM_5 */
2930   {
2931     { Bad_Opcode },
2932     { Bad_Opcode },
2933     { X86_64_TABLE (X86_64_0F01_REG_1_RM_5_PREFIX_2) },
2934     { Bad_Opcode },
2935   },
2936
2937   /* PREFIX_0F01_REG_1_RM_6 */
2938   {
2939     { Bad_Opcode },
2940     { Bad_Opcode },
2941     { X86_64_TABLE (X86_64_0F01_REG_1_RM_6_PREFIX_2) },
2942     { Bad_Opcode },
2943   },
2944
2945   /* PREFIX_0F01_REG_1_RM_7 */
2946   {
2947     { "encls",          { Skip_MODRM }, 0 },
2948     { Bad_Opcode },
2949     { X86_64_TABLE (X86_64_0F01_REG_1_RM_7_PREFIX_2) },
2950     { Bad_Opcode },
2951   },
2952
2953   /* PREFIX_0F01_REG_3_RM_1 */
2954   {
2955     { "vmmcall",        { Skip_MODRM }, 0 },
2956     { "vmgexit",        { Skip_MODRM }, 0 },
2957     { Bad_Opcode },
2958     { "vmgexit",        { Skip_MODRM }, 0 },
2959   },
2960
2961   /* PREFIX_0F01_REG_5_MOD_0 */
2962   {
2963     { Bad_Opcode },
2964     { "rstorssp",       { Mq }, PREFIX_OPCODE },
2965   },
2966
2967   /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
2968   {
2969     { "serialize",      { Skip_MODRM }, PREFIX_OPCODE },
2970     { "setssbsy",       { Skip_MODRM }, PREFIX_OPCODE },
2971     { Bad_Opcode },
2972     { "xsusldtrk",      { Skip_MODRM }, PREFIX_OPCODE },
2973   },
2974
2975   /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
2976   {
2977     { Bad_Opcode },
2978     { Bad_Opcode },
2979     { Bad_Opcode },
2980     { "xresldtrk",     { Skip_MODRM }, PREFIX_OPCODE },
2981   },
2982
2983   /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
2984   {
2985     { Bad_Opcode },
2986     { "saveprevssp",    { Skip_MODRM }, PREFIX_OPCODE },
2987   },
2988
2989   /* PREFIX_0F01_REG_5_MOD_3_RM_4 */
2990   {
2991     { Bad_Opcode },
2992     { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1) },
2993   },
2994
2995   /* PREFIX_0F01_REG_5_MOD_3_RM_5 */
2996   {
2997     { Bad_Opcode },
2998     { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1) },
2999   },
3000
3001   /* PREFIX_0F01_REG_5_MOD_3_RM_6 */
3002   {
3003     { "rdpkru", { Skip_MODRM }, 0 },
3004     { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1) },
3005   },
3006
3007   /* PREFIX_0F01_REG_5_MOD_3_RM_7 */
3008   {
3009     { "wrpkru", { Skip_MODRM }, 0 },
3010     { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1) },
3011   },
3012
3013   /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3014   {
3015     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
3016     { "mcommit",        { Skip_MODRM }, 0 },
3017   },
3018
3019   /* PREFIX_0F01_REG_7_MOD_3_RM_6 */
3020   {
3021     { "invlpgb",        { Skip_MODRM }, 0 },
3022     { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1) },
3023     { Bad_Opcode },
3024     { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3) },
3025   },
3026
3027   /* PREFIX_0F01_REG_7_MOD_3_RM_7 */
3028   {
3029     { "tlbsync",        { Skip_MODRM }, 0 },
3030     { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1) },
3031     { Bad_Opcode },
3032     { "pvalidate",      { Skip_MODRM }, 0 },
3033   },
3034
3035   /* PREFIX_0F09 */
3036   {
3037     { "wbinvd",   { XX }, 0 },
3038     { "wbnoinvd", { XX }, 0 },
3039   },
3040
3041   /* PREFIX_0F10 */
3042   {
3043     { "movups", { XM, EXx }, PREFIX_OPCODE },
3044     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3045     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3046     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3047   },
3048
3049   /* PREFIX_0F11 */
3050   {
3051     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3052     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3053     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3054     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3055   },
3056
3057   /* PREFIX_0F12 */
3058   {
3059     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3060     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3061     { MOD_TABLE (MOD_0F12_PREFIX_2) },
3062     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3063   },
3064
3065   /* PREFIX_0F16 */
3066   {
3067     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3068     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3069     { MOD_TABLE (MOD_0F16_PREFIX_2) },
3070   },
3071
3072   /* PREFIX_0F1A */
3073   {
3074     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3075     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3076     { "bndmov", { Gbnd, Ebnd }, 0 },
3077     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3078   },
3079
3080   /* PREFIX_0F1B */
3081   {
3082     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3083     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3084     { "bndmov", { EbndS, Gbnd }, 0 },
3085     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3086   },
3087
3088   /* PREFIX_0F1C */
3089   {
3090     { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3091     { "nopQ",   { Ev }, PREFIX_IGNORED },
3092     { "nopQ",   { Ev }, 0 },
3093     { "nopQ",   { Ev }, PREFIX_IGNORED },
3094   },
3095
3096   /* PREFIX_0F1E */
3097   {
3098     { "nopQ",   { Ev }, 0 },
3099     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3100     { "nopQ",   { Ev }, 0 },
3101     { NULL,     { XX }, PREFIX_IGNORED },
3102   },
3103
3104   /* PREFIX_0F2A */
3105   {
3106     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3107     { "cvtsi2ss{%LQ|}", { XM, Edq }, PREFIX_OPCODE },
3108     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3109     { "cvtsi2sd{%LQ|}", { XM, Edq }, 0 },
3110   },
3111
3112   /* PREFIX_0F2B */
3113   {
3114     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3115     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3116     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3117     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3118   },
3119
3120   /* PREFIX_0F2C */
3121   {
3122     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3123     { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
3124     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3125     { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3126   },
3127
3128   /* PREFIX_0F2D */
3129   {
3130     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3131     { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
3132     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3133     { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3134   },
3135
3136   /* PREFIX_0F2E */
3137   {
3138     { "ucomiss",{ XM, EXd }, 0 },
3139     { Bad_Opcode },
3140     { "ucomisd",{ XM, EXq }, 0 },
3141   },
3142
3143   /* PREFIX_0F2F */
3144   {
3145     { "comiss", { XM, EXd }, 0 },
3146     { Bad_Opcode },
3147     { "comisd", { XM, EXq }, 0 },
3148   },
3149
3150   /* PREFIX_0F51 */
3151   {
3152     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3153     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3154     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3155     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3156   },
3157
3158   /* PREFIX_0F52 */
3159   {
3160     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3161     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3162   },
3163
3164   /* PREFIX_0F53 */
3165   {
3166     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3167     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3168   },
3169
3170   /* PREFIX_0F58 */
3171   {
3172     { "addps", { XM, EXx }, PREFIX_OPCODE },
3173     { "addss", { XM, EXd }, PREFIX_OPCODE },
3174     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3175     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3176   },
3177
3178   /* PREFIX_0F59 */
3179   {
3180     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3181     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3182     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3183     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3184   },
3185
3186   /* PREFIX_0F5A */
3187   {
3188     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3189     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3190     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3191     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3192   },
3193
3194   /* PREFIX_0F5B */
3195   {
3196     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3197     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3198     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3199   },
3200
3201   /* PREFIX_0F5C */
3202   {
3203     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3204     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3205     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3206     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3207   },
3208
3209   /* PREFIX_0F5D */
3210   {
3211     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3212     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3213     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3214     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3215   },
3216
3217   /* PREFIX_0F5E */
3218   {
3219     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3220     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3221     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3222     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3223   },
3224
3225   /* PREFIX_0F5F */
3226   {
3227     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3228     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3229     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3230     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3231   },
3232
3233   /* PREFIX_0F60 */
3234   {
3235     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3236     { Bad_Opcode },
3237     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3238   },
3239
3240   /* PREFIX_0F61 */
3241   {
3242     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3243     { Bad_Opcode },
3244     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3245   },
3246
3247   /* PREFIX_0F62 */
3248   {
3249     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3250     { Bad_Opcode },
3251     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3252   },
3253
3254   /* PREFIX_0F6F */
3255   {
3256     { "movq",   { MX, EM }, PREFIX_OPCODE },
3257     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3258     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3259   },
3260
3261   /* PREFIX_0F70 */
3262   {
3263     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3264     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3265     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3266     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3267   },
3268
3269   /* PREFIX_0F78 */
3270   {
3271     {"vmread",  { Em, Gm }, 0 },
3272     { Bad_Opcode },
3273     {"extrq",   { XS, Ib, Ib }, 0 },
3274     {"insertq", { XM, XS, Ib, Ib }, 0 },
3275   },
3276
3277   /* PREFIX_0F79 */
3278   {
3279     {"vmwrite", { Gm, Em }, 0 },
3280     { Bad_Opcode },
3281     {"extrq",   { XM, XS }, 0 },
3282     {"insertq", { XM, XS }, 0 },
3283   },
3284
3285   /* PREFIX_0F7C */
3286   {
3287     { Bad_Opcode },
3288     { Bad_Opcode },
3289     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3290     { "haddps", { XM, EXx }, PREFIX_OPCODE },
3291   },
3292
3293   /* PREFIX_0F7D */
3294   {
3295     { Bad_Opcode },
3296     { Bad_Opcode },
3297     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3298     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3299   },
3300
3301   /* PREFIX_0F7E */
3302   {
3303     { "movK",   { Edq, MX }, PREFIX_OPCODE },
3304     { "movq",   { XM, EXq }, PREFIX_OPCODE },
3305     { "movK",   { Edq, XM }, PREFIX_OPCODE },
3306   },
3307
3308   /* PREFIX_0F7F */
3309   {
3310     { "movq",   { EMS, MX }, PREFIX_OPCODE },
3311     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3312     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3313   },
3314
3315   /* PREFIX_0FAE_REG_0_MOD_3 */
3316   {
3317     { Bad_Opcode },
3318     { "rdfsbase", { Ev }, 0 },
3319   },
3320
3321   /* PREFIX_0FAE_REG_1_MOD_3 */
3322   {
3323     { Bad_Opcode },
3324     { "rdgsbase", { Ev }, 0 },
3325   },
3326
3327   /* PREFIX_0FAE_REG_2_MOD_3 */
3328   {
3329     { Bad_Opcode },
3330     { "wrfsbase", { Ev }, 0 },
3331   },
3332
3333   /* PREFIX_0FAE_REG_3_MOD_3 */
3334   {
3335     { Bad_Opcode },
3336     { "wrgsbase", { Ev }, 0 },
3337   },
3338
3339   /* PREFIX_0FAE_REG_4_MOD_0 */
3340   {
3341     { "xsave",  { FXSAVE }, 0 },
3342     { "ptwrite{%LQ|}", { Edq }, 0 },
3343   },
3344
3345   /* PREFIX_0FAE_REG_4_MOD_3 */
3346   {
3347     { Bad_Opcode },
3348     { "ptwrite{%LQ|}", { Edq }, 0 },
3349   },
3350
3351   /* PREFIX_0FAE_REG_5_MOD_3 */
3352   {
3353     { "lfence",         { Skip_MODRM }, 0 },
3354     { "incsspK",        { Edq }, PREFIX_OPCODE },
3355   },
3356
3357   /* PREFIX_0FAE_REG_6_MOD_0 */
3358   {
3359     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE },
3360     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
3361     { "clwb",   { Mb }, PREFIX_OPCODE },
3362   },
3363
3364   /* PREFIX_0FAE_REG_6_MOD_3 */
3365   {
3366     { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) },
3367     { "umonitor",       { Eva }, PREFIX_OPCODE },
3368     { "tpause", { Edq }, PREFIX_OPCODE },
3369     { "umwait", { Edq }, PREFIX_OPCODE },
3370   },
3371
3372   /* PREFIX_0FAE_REG_7_MOD_0 */
3373   {
3374     { "clflush",        { Mb }, 0 },
3375     { Bad_Opcode },
3376     { "clflushopt",     { Mb }, 0 },
3377   },
3378
3379   /* PREFIX_0FB8 */
3380   {
3381     { Bad_Opcode },
3382     { "popcntS", { Gv, Ev }, 0 },
3383   },
3384
3385   /* PREFIX_0FBC */
3386   {
3387     { "bsfS",   { Gv, Ev }, 0 },
3388     { "tzcntS", { Gv, Ev }, 0 },
3389     { "bsfS",   { Gv, Ev }, 0 },
3390   },
3391
3392   /* PREFIX_0FBD */
3393   {
3394     { "bsrS",   { Gv, Ev }, 0 },
3395     { "lzcntS", { Gv, Ev }, 0 },
3396     { "bsrS",   { Gv, Ev }, 0 },
3397   },
3398
3399   /* PREFIX_0FC2 */
3400   {
3401     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
3402     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
3403     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
3404     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
3405   },
3406
3407   /* PREFIX_0FC7_REG_6_MOD_0 */
3408   {
3409     { "vmptrld",{ Mq }, 0 },
3410     { "vmxon",  { Mq }, 0 },
3411     { "vmclear",{ Mq }, 0 },
3412   },
3413
3414   /* PREFIX_0FC7_REG_6_MOD_3 */
3415   {
3416     { "rdrand", { Ev }, 0 },
3417     { X86_64_TABLE (X86_64_0FC7_REG_6_MOD_3_PREFIX_1) },
3418     { "rdrand", { Ev }, 0 }
3419   },
3420
3421   /* PREFIX_0FC7_REG_7_MOD_3 */
3422   {
3423     { "rdseed", { Ev }, 0 },
3424     { "rdpid",  { Em }, 0 },
3425     { "rdseed", { Ev }, 0 },
3426   },
3427
3428   /* PREFIX_0FD0 */
3429   {
3430     { Bad_Opcode },
3431     { Bad_Opcode },
3432     { "addsubpd", { XM, EXx }, 0 },
3433     { "addsubps", { XM, EXx }, 0 },
3434   },
3435
3436   /* PREFIX_0FD6 */
3437   {
3438     { Bad_Opcode },
3439     { "movq2dq",{ XM, MS }, 0 },
3440     { "movq",   { EXqS, XM }, 0 },
3441     { "movdq2q",{ MX, XS }, 0 },
3442   },
3443
3444   /* PREFIX_0FE6 */
3445   {
3446     { Bad_Opcode },
3447     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
3448     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
3449     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
3450   },
3451
3452   /* PREFIX_0FE7 */
3453   {
3454     { "movntq", { Mq, MX }, PREFIX_OPCODE },
3455     { Bad_Opcode },
3456     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
3457   },
3458
3459   /* PREFIX_0FF0 */
3460   {
3461     { Bad_Opcode },
3462     { Bad_Opcode },
3463     { Bad_Opcode },
3464     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
3465   },
3466
3467   /* PREFIX_0FF7 */
3468   {
3469     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
3470     { Bad_Opcode },
3471     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
3472   },
3473
3474   /* PREFIX_0F38D8 */
3475   {
3476     { Bad_Opcode },
3477     { REG_TABLE (REG_0F38D8_PREFIX_1) },
3478   },
3479
3480   /* PREFIX_0F38DC */
3481   {
3482     { Bad_Opcode },
3483     { MOD_TABLE (MOD_0F38DC_PREFIX_1) },
3484     { "aesenc", { XM, EXx }, 0 },
3485   },
3486
3487   /* PREFIX_0F38DD */
3488   {
3489     { Bad_Opcode },
3490     { MOD_TABLE (MOD_0F38DD_PREFIX_1) },
3491     { "aesenclast", { XM, EXx }, 0 },
3492   },
3493
3494   /* PREFIX_0F38DE */
3495   {
3496     { Bad_Opcode },
3497     { MOD_TABLE (MOD_0F38DE_PREFIX_1) },
3498     { "aesdec", { XM, EXx }, 0 },
3499   },
3500
3501   /* PREFIX_0F38DF */
3502   {
3503     { Bad_Opcode },
3504     { MOD_TABLE (MOD_0F38DF_PREFIX_1) },
3505     { "aesdeclast", { XM, EXx }, 0 },
3506   },
3507
3508   /* PREFIX_0F38F0 */
3509   {
3510     { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3511     { Bad_Opcode },
3512     { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3513     { "crc32A", { Gdq, Eb }, PREFIX_OPCODE },
3514   },
3515
3516   /* PREFIX_0F38F1 */
3517   {
3518     { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3519     { Bad_Opcode },
3520     { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3521     { "crc32Q", { Gdq, Ev }, PREFIX_OPCODE },
3522   },
3523
3524   /* PREFIX_0F38F6 */
3525   {
3526     { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
3527     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
3528     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
3529     { Bad_Opcode },
3530   },
3531
3532   /* PREFIX_0F38F8 */
3533   {
3534     { Bad_Opcode },
3535     { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
3536     { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
3537     { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
3538   },
3539   /* PREFIX_0F38FA */
3540   {
3541     { Bad_Opcode },
3542     { MOD_TABLE (MOD_0F38FA_PREFIX_1) },
3543   },
3544
3545   /* PREFIX_0F38FB */
3546   {
3547     { Bad_Opcode },
3548     { MOD_TABLE (MOD_0F38FB_PREFIX_1) },
3549   },
3550
3551   /* PREFIX_0F3A0F */
3552   {
3553     { Bad_Opcode },
3554     { MOD_TABLE (MOD_0F3A0F_PREFIX_1)},
3555   },
3556
3557   /* PREFIX_VEX_0F10 */
3558   {
3559     { "vmovupX",        { XM, EXEvexXNoBcst }, PREFIX_OPCODE },
3560     { "vmovs%XS",       { XMScalar, VexScalarR, EXd }, 0 },
3561     { "vmovupX",        { XM, EXEvexXNoBcst }, PREFIX_OPCODE },
3562     { "vmovs%XD",       { XMScalar, VexScalarR, EXq }, 0 },
3563   },
3564
3565   /* PREFIX_VEX_0F11 */
3566   {
3567     { "vmovupX",        { EXxS, XM }, PREFIX_OPCODE },
3568     { "vmovs%XS",       { EXdS, VexScalarR, XMScalar }, 0 },
3569     { "vmovupX",        { EXxS, XM }, PREFIX_OPCODE },
3570     { "vmovs%XD",       { EXqS, VexScalarR, XMScalar }, 0 },
3571   },
3572
3573   /* PREFIX_VEX_0F12 */
3574   {
3575     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
3576     { "vmov%XSldup",    { XM, EXEvexXNoBcst }, 0 },
3577     { MOD_TABLE (MOD_VEX_0F12_PREFIX_2) },
3578     { "vmov%XDdup",     { XM, EXymmq }, 0 },
3579   },
3580
3581   /* PREFIX_VEX_0F16 */
3582   {
3583     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
3584     { "vmov%XShdup",    { XM, EXEvexXNoBcst }, 0 },
3585     { MOD_TABLE (MOD_VEX_0F16_PREFIX_2) },
3586   },
3587
3588   /* PREFIX_VEX_0F2A */
3589   {
3590     { Bad_Opcode },
3591     { "vcvtsi2ss{%LQ|}",        { XMScalar, VexScalar, EXxEVexR, Edq }, 0 },
3592     { Bad_Opcode },
3593     { "vcvtsi2sd{%LQ|}",        { XMScalar, VexScalar, EXxEVexR64, Edq }, 0 },
3594   },
3595
3596   /* PREFIX_VEX_0F2C */
3597   {
3598     { Bad_Opcode },
3599     { "vcvttss2si",     { Gdq, EXd, EXxEVexS }, 0 },
3600     { Bad_Opcode },
3601     { "vcvttsd2si",     { Gdq, EXq, EXxEVexS }, 0 },
3602   },
3603
3604   /* PREFIX_VEX_0F2D */
3605   {
3606     { Bad_Opcode },
3607     { "vcvtss2si",      { Gdq, EXd, EXxEVexR }, 0 },
3608     { Bad_Opcode },
3609     { "vcvtsd2si",      { Gdq, EXq, EXxEVexR }, 0 },
3610   },
3611
3612   /* PREFIX_VEX_0F2E */
3613   {
3614     { "vucomisX",       { XMScalar, EXd, EXxEVexS }, PREFIX_OPCODE },
3615     { Bad_Opcode },
3616     { "vucomisX",       { XMScalar, EXq, EXxEVexS }, PREFIX_OPCODE },
3617   },
3618
3619   /* PREFIX_VEX_0F2F */
3620   {
3621     { "vcomisX",        { XMScalar, EXd, EXxEVexS }, PREFIX_OPCODE },
3622     { Bad_Opcode },
3623     { "vcomisX",        { XMScalar, EXq, EXxEVexS }, PREFIX_OPCODE },
3624   },
3625
3626   /* PREFIX_VEX_0F41_L_1_M_1_W_0 */
3627   {
3628     { "kandw",          { MaskG, MaskVex, MaskE }, 0 },
3629     { Bad_Opcode },
3630     { "kandb",          { MaskG, MaskVex, MaskE }, 0 },
3631   },
3632
3633   /* PREFIX_VEX_0F41_L_1_M_1_W_1 */
3634   {
3635     { "kandq",          { MaskG, MaskVex, MaskE }, 0 },
3636     { Bad_Opcode },
3637     { "kandd",          { MaskG, MaskVex, MaskE }, 0 },
3638   },
3639
3640   /* PREFIX_VEX_0F42_L_1_M_1_W_0 */
3641   {
3642     { "kandnw",         { MaskG, MaskVex, MaskE }, 0 },
3643     { Bad_Opcode },
3644     { "kandnb",         { MaskG, MaskVex, MaskE }, 0 },
3645   },
3646
3647   /* PREFIX_VEX_0F42_L_1_M_1_W_1 */
3648   {
3649     { "kandnq",         { MaskG, MaskVex, MaskE }, 0 },
3650     { Bad_Opcode },
3651     { "kandnd",         { MaskG, MaskVex, MaskE }, 0 },
3652   },
3653
3654   /* PREFIX_VEX_0F44_L_0_M_1_W_0 */
3655   {
3656     { "knotw",          { MaskG, MaskE }, 0 },
3657     { Bad_Opcode },
3658     { "knotb",          { MaskG, MaskE }, 0 },
3659   },
3660
3661   /* PREFIX_VEX_0F44_L_0_M_1_W_1 */
3662   {
3663     { "knotq",          { MaskG, MaskE }, 0 },
3664     { Bad_Opcode },
3665     { "knotd",          { MaskG, MaskE }, 0 },
3666   },
3667
3668   /* PREFIX_VEX_0F45_L_1_M_1_W_0 */
3669   {
3670     { "korw",       { MaskG, MaskVex, MaskE }, 0 },
3671     { Bad_Opcode },
3672     { "korb",       { MaskG, MaskVex, MaskE }, 0 },
3673   },
3674
3675   /* PREFIX_VEX_0F45_L_1_M_1_W_1 */
3676   {
3677     { "korq",       { MaskG, MaskVex, MaskE }, 0 },
3678     { Bad_Opcode },
3679     { "kord",       { MaskG, MaskVex, MaskE }, 0 },
3680   },
3681
3682   /* PREFIX_VEX_0F46_L_1_M_1_W_0 */
3683   {
3684     { "kxnorw",     { MaskG, MaskVex, MaskE }, 0 },
3685     { Bad_Opcode },
3686     { "kxnorb",     { MaskG, MaskVex, MaskE }, 0 },
3687   },
3688
3689   /* PREFIX_VEX_0F46_L_1_M_1_W_1 */
3690   {
3691     { "kxnorq",     { MaskG, MaskVex, MaskE }, 0 },
3692     { Bad_Opcode },
3693     { "kxnord",     { MaskG, MaskVex, MaskE }, 0 },
3694   },
3695
3696   /* PREFIX_VEX_0F47_L_1_M_1_W_0 */
3697   {
3698     { "kxorw",      { MaskG, MaskVex, MaskE }, 0 },
3699     { Bad_Opcode },
3700     { "kxorb",      { MaskG, MaskVex, MaskE }, 0 },
3701   },
3702
3703   /* PREFIX_VEX_0F47_L_1_M_1_W_1 */
3704   {
3705     { "kxorq",      { MaskG, MaskVex, MaskE }, 0 },
3706     { Bad_Opcode },
3707     { "kxord",      { MaskG, MaskVex, MaskE }, 0 },
3708   },
3709
3710   /* PREFIX_VEX_0F4A_L_1_M_1_W_0 */
3711   {
3712     { "kaddw",          { MaskG, MaskVex, MaskE }, 0 },
3713     { Bad_Opcode },
3714     { "kaddb",          { MaskG, MaskVex, MaskE }, 0 },
3715   },
3716
3717   /* PREFIX_VEX_0F4A_L_1_M_1_W_1 */
3718   {
3719     { "kaddq",          { MaskG, MaskVex, MaskE }, 0 },
3720     { Bad_Opcode },
3721     { "kaddd",          { MaskG, MaskVex, MaskE }, 0 },
3722   },
3723
3724   /* PREFIX_VEX_0F4B_L_1_M_1_W_0 */
3725   {
3726     { "kunpckwd",   { MaskG, MaskVex, MaskE }, 0 },
3727     { Bad_Opcode },
3728     { "kunpckbw",   { MaskG, MaskVex, MaskE }, 0 },
3729   },
3730
3731   /* PREFIX_VEX_0F4B_L_1_M_1_W_1 */
3732   {
3733     { "kunpckdq",   { MaskG, MaskVex, MaskE }, 0 },
3734   },
3735
3736   /* PREFIX_VEX_0F51 */
3737   {
3738     { "vsqrtpX",        { XM, EXx, EXxEVexR }, PREFIX_OPCODE },
3739     { "vsqrts%XS",      { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3740     { "vsqrtpX",        { XM, EXx, EXxEVexR }, PREFIX_OPCODE },
3741     { "vsqrts%XD",      { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3742   },
3743
3744   /* PREFIX_VEX_0F52 */
3745   {
3746     { "vrsqrtps",       { XM, EXx }, 0 },
3747     { "vrsqrtss",       { XMScalar, VexScalar, EXd }, 0 },
3748   },
3749
3750   /* PREFIX_VEX_0F53 */
3751   {
3752     { "vrcpps",         { XM, EXx }, 0 },
3753     { "vrcpss",         { XMScalar, VexScalar, EXd }, 0 },
3754   },
3755
3756   /* PREFIX_VEX_0F58 */
3757   {
3758     { "vaddpX",         { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
3759     { "vadds%XS",       { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3760     { "vaddpX",         { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
3761     { "vadds%XD",       { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3762   },
3763
3764   /* PREFIX_VEX_0F59 */
3765   {
3766     { "vmulpX",         { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
3767     { "vmuls%XS",       { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3768     { "vmulpX",         { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
3769     { "vmuls%XD",       { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3770   },
3771
3772   /* PREFIX_VEX_0F5A */
3773   {
3774     { "vcvtp%XS2pd", { XM, EXEvexHalfBcstXmmq, EXxEVexS }, 0 },
3775     { "vcvts%XS2sd", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
3776     { "vcvtp%XD2ps%XY", { XMxmmq, EXx, EXxEVexR }, 0 },
3777     { "vcvts%XD2ss", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3778   },
3779
3780   /* PREFIX_VEX_0F5B */
3781   {
3782     { "vcvtdq2ps",      { XM, EXx }, 0 },
3783     { "vcvttps2dq",     { XM, EXx }, 0 },
3784     { "vcvtps2dq",      { XM, EXx }, 0 },
3785   },
3786
3787   /* PREFIX_VEX_0F5C */
3788   {
3789     { "vsubpX",         { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
3790     { "vsubs%XS",       { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3791     { "vsubpX",         { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
3792     { "vsubs%XD",       { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3793   },
3794
3795   /* PREFIX_VEX_0F5D */
3796   {
3797     { "vminpX",         { XM, Vex, EXx, EXxEVexS }, PREFIX_OPCODE },
3798     { "vmins%XS",       { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
3799     { "vminpX",         { XM, Vex, EXx, EXxEVexS }, PREFIX_OPCODE },
3800     { "vmins%XD",       { XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
3801   },
3802
3803   /* PREFIX_VEX_0F5E */
3804   {
3805     { "vdivpX",         { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
3806     { "vdivs%XS",       { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3807     { "vdivpX",         { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
3808     { "vdivs%XD",       { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3809   },
3810
3811   /* PREFIX_VEX_0F5F */
3812   {
3813     { "vmaxpX",         { XM, Vex, EXx, EXxEVexS }, PREFIX_OPCODE },
3814     { "vmaxs%XS",       { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
3815     { "vmaxpX",         { XM, Vex, EXx, EXxEVexS }, PREFIX_OPCODE },
3816     { "vmaxs%XD",       { XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
3817   },
3818
3819   /* PREFIX_VEX_0F6F */
3820   {
3821     { Bad_Opcode },
3822     { "vmovdqu",        { XM, EXx }, 0 },
3823     { "vmovdqa",        { XM, EXx }, 0 },
3824   },
3825
3826   /* PREFIX_VEX_0F70 */
3827   {
3828     { Bad_Opcode },
3829     { "vpshufhw",       { XM, EXx, Ib }, 0 },
3830     { "vpshufd",        { XM, EXx, Ib }, 0 },
3831     { "vpshuflw",       { XM, EXx, Ib }, 0 },
3832   },
3833
3834   /* PREFIX_VEX_0F7C */
3835   {
3836     { Bad_Opcode },
3837     { Bad_Opcode },
3838     { "vhaddpd",        { XM, Vex, EXx }, 0 },
3839     { "vhaddps",        { XM, Vex, EXx }, 0 },
3840   },
3841
3842   /* PREFIX_VEX_0F7D */
3843   {
3844     { Bad_Opcode },
3845     { Bad_Opcode },
3846     { "vhsubpd",        { XM, Vex, EXx }, 0 },
3847     { "vhsubps",        { XM, Vex, EXx }, 0 },
3848   },
3849
3850   /* PREFIX_VEX_0F7E */
3851   {
3852     { Bad_Opcode },
3853     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
3854     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
3855   },
3856
3857   /* PREFIX_VEX_0F7F */
3858   {
3859     { Bad_Opcode },
3860     { "vmovdqu",        { EXxS, XM }, 0 },
3861     { "vmovdqa",        { EXxS, XM }, 0 },
3862   },
3863
3864   /* PREFIX_VEX_0F90_L_0_W_0 */
3865   {
3866     { "kmovw",          { MaskG, MaskE }, 0 },
3867     { Bad_Opcode },
3868     { "kmovb",          { MaskG, MaskBDE }, 0 },
3869   },
3870
3871   /* PREFIX_VEX_0F90_L_0_W_1 */
3872   {
3873     { "kmovq",          { MaskG, MaskE }, 0 },
3874     { Bad_Opcode },
3875     { "kmovd",          { MaskG, MaskBDE }, 0 },
3876   },
3877
3878   /* PREFIX_VEX_0F91_L_0_M_0_W_0 */
3879   {
3880     { "kmovw",          { Ew, MaskG }, 0 },
3881     { Bad_Opcode },
3882     { "kmovb",          { Eb, MaskG }, 0 },
3883   },
3884
3885   /* PREFIX_VEX_0F91_L_0_M_0_W_1 */
3886   {
3887     { "kmovq",          { Eq, MaskG }, 0 },
3888     { Bad_Opcode },
3889     { "kmovd",          { Ed, MaskG }, 0 },
3890   },
3891
3892   /* PREFIX_VEX_0F92_L_0_M_1_W_0 */
3893   {
3894     { "kmovw",          { MaskG, Edq }, 0 },
3895     { Bad_Opcode },
3896     { "kmovb",          { MaskG, Edq }, 0 },
3897     { "kmovd",          { MaskG, Edq }, 0 },
3898   },
3899
3900   /* PREFIX_VEX_0F92_L_0_M_1_W_1 */
3901   {
3902     { Bad_Opcode },
3903     { Bad_Opcode },
3904     { Bad_Opcode },
3905     { "kmovK",          { MaskG, Edq }, 0 },
3906   },
3907
3908   /* PREFIX_VEX_0F93_L_0_M_1_W_0 */
3909   {
3910     { "kmovw",          { Gdq, MaskE }, 0 },
3911     { Bad_Opcode },
3912     { "kmovb",          { Gdq, MaskE }, 0 },
3913     { "kmovd",          { Gdq, MaskE }, 0 },
3914   },
3915
3916   /* PREFIX_VEX_0F93_L_0_M_1_W_1 */
3917   {
3918     { Bad_Opcode },
3919     { Bad_Opcode },
3920     { Bad_Opcode },
3921     { "kmovK",          { Gdq, MaskE }, 0 },
3922   },
3923
3924   /* PREFIX_VEX_0F98_L_0_M_1_W_0 */
3925   {
3926     { "kortestw", { MaskG, MaskE }, 0 },
3927     { Bad_Opcode },
3928     { "kortestb", { MaskG, MaskE }, 0 },
3929   },
3930
3931   /* PREFIX_VEX_0F98_L_0_M_1_W_1 */
3932   {
3933     { "kortestq", { MaskG, MaskE }, 0 },
3934     { Bad_Opcode },
3935     { "kortestd", { MaskG, MaskE }, 0 },
3936   },
3937
3938   /* PREFIX_VEX_0F99_L_0_M_1_W_0 */
3939   {
3940     { "ktestw", { MaskG, MaskE }, 0 },
3941     { Bad_Opcode },
3942     { "ktestb", { MaskG, MaskE }, 0 },
3943   },
3944
3945   /* PREFIX_VEX_0F99_L_0_M_1_W_1 */
3946   {
3947     { "ktestq", { MaskG, MaskE }, 0 },
3948     { Bad_Opcode },
3949     { "ktestd", { MaskG, MaskE }, 0 },
3950   },
3951
3952   /* PREFIX_VEX_0FC2 */
3953   {
3954     { "vcmpps",         { XM, Vex, EXx, CMP }, 0 },
3955     { "vcmpss",         { XMScalar, VexScalar, EXd, CMP }, 0 },
3956     { "vcmppd",         { XM, Vex, EXx, CMP }, 0 },
3957     { "vcmpsd",         { XMScalar, VexScalar, EXq, CMP }, 0 },
3958   },
3959
3960   /* PREFIX_VEX_0FD0 */
3961   {
3962     { Bad_Opcode },
3963     { Bad_Opcode },
3964     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
3965     { "vaddsubps",      { XM, Vex, EXx }, 0 },
3966   },
3967
3968   /* PREFIX_VEX_0FE6 */
3969   {
3970     { Bad_Opcode },
3971     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
3972     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
3973     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
3974   },
3975
3976   /* PREFIX_VEX_0FF0 */
3977   {
3978     { Bad_Opcode },
3979     { Bad_Opcode },
3980     { Bad_Opcode },
3981     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
3982   },
3983
3984   /* PREFIX_VEX_0F3849_X86_64 */
3985   {
3986     { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_0) },
3987     { Bad_Opcode },
3988     { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_2) },
3989     { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_3) },
3990   },
3991
3992   /* PREFIX_VEX_0F384B_X86_64 */
3993   {
3994     { Bad_Opcode },
3995     { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_1) },
3996     { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_2) },
3997     { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_3) },
3998   },
3999
4000   /* PREFIX_VEX_0F385C_X86_64 */
4001   {
4002     { Bad_Opcode },
4003     { VEX_W_TABLE (VEX_W_0F385C_X86_64_P_1) },
4004     { Bad_Opcode },
4005   },
4006
4007   /* PREFIX_VEX_0F385E_X86_64 */
4008   {
4009     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_0) },
4010     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_1) },
4011     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_2) },
4012     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_3) },
4013   },
4014
4015   /* PREFIX_VEX_0F38F5_L_0 */
4016   {
4017     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
4018     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
4019     { Bad_Opcode },
4020     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
4021   },
4022
4023   /* PREFIX_VEX_0F38F6_L_0 */
4024   {
4025     { Bad_Opcode },
4026     { Bad_Opcode },
4027     { Bad_Opcode },
4028     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
4029   },
4030
4031   /* PREFIX_VEX_0F38F7_L_0 */
4032   {
4033     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
4034     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
4035     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
4036     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
4037   },
4038
4039   /* PREFIX_VEX_0F3AF0_L_0 */
4040   {
4041     { Bad_Opcode },
4042     { Bad_Opcode },
4043     { Bad_Opcode },
4044     { "rorxS",          { Gdq, Edq, Ib }, 0 },
4045   },
4046
4047 #include "i386-dis-evex-prefix.h"
4048 };
4049
4050 static const struct dis386 x86_64_table[][2] = {
4051   /* X86_64_06 */
4052   {
4053     { "pushP", { es }, 0 },
4054   },
4055
4056   /* X86_64_07 */
4057   {
4058     { "popP", { es }, 0 },
4059   },
4060
4061   /* X86_64_0E */
4062   {
4063     { "pushP", { cs }, 0 },
4064   },
4065
4066   /* X86_64_16 */
4067   {
4068     { "pushP", { ss }, 0 },
4069   },
4070
4071   /* X86_64_17 */
4072   {
4073     { "popP", { ss }, 0 },
4074   },
4075
4076   /* X86_64_1E */
4077   {
4078     { "pushP", { ds }, 0 },
4079   },
4080
4081   /* X86_64_1F */
4082   {
4083     { "popP", { ds }, 0 },
4084   },
4085
4086   /* X86_64_27 */
4087   {
4088     { "daa", { XX }, 0 },
4089   },
4090
4091   /* X86_64_2F */
4092   {
4093     { "das", { XX }, 0 },
4094   },
4095
4096   /* X86_64_37 */
4097   {
4098     { "aaa", { XX }, 0 },
4099   },
4100
4101   /* X86_64_3F */
4102   {
4103     { "aas", { XX }, 0 },
4104   },
4105
4106   /* X86_64_60 */
4107   {
4108     { "pushaP", { XX }, 0 },
4109   },
4110
4111   /* X86_64_61 */
4112   {
4113     { "popaP", { XX }, 0 },
4114   },
4115
4116   /* X86_64_62 */
4117   {
4118     { MOD_TABLE (MOD_62_32BIT) },
4119     { EVEX_TABLE (EVEX_0F) },
4120   },
4121
4122   /* X86_64_63 */
4123   {
4124     { "arpl", { Ew, Gw }, 0 },
4125     { "movs", { Gv, { MOVSXD_Fixup, movsxd_mode } }, 0 },
4126   },
4127
4128   /* X86_64_6D */
4129   {
4130     { "ins{R|}", { Yzr, indirDX }, 0 },
4131     { "ins{G|}", { Yzr, indirDX }, 0 },
4132   },
4133
4134   /* X86_64_6F */
4135   {
4136     { "outs{R|}", { indirDXr, Xz }, 0 },
4137     { "outs{G|}", { indirDXr, Xz }, 0 },
4138   },
4139
4140   /* X86_64_82 */
4141   {
4142     /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
4143     { REG_TABLE (REG_80) },
4144   },
4145
4146   /* X86_64_9A */
4147   {
4148     { "{l|}call{P|}", { Ap }, 0 },
4149   },
4150
4151   /* X86_64_C2 */
4152   {
4153     { "retP",           { Iw, BND }, 0 },
4154     { "ret@",           { Iw, BND }, 0 },
4155   },
4156
4157   /* X86_64_C3 */
4158   {
4159     { "retP",           { BND }, 0 },
4160     { "ret@",           { BND }, 0 },
4161   },
4162
4163   /* X86_64_C4 */
4164   {
4165     { MOD_TABLE (MOD_C4_32BIT) },
4166     { VEX_C4_TABLE (VEX_0F) },
4167   },
4168
4169   /* X86_64_C5 */
4170   {
4171     { MOD_TABLE (MOD_C5_32BIT) },
4172     { VEX_C5_TABLE (VEX_0F) },
4173   },
4174
4175   /* X86_64_CE */
4176   {
4177     { "into", { XX }, 0 },
4178   },
4179
4180   /* X86_64_D4 */
4181   {
4182     { "aam", { Ib }, 0 },
4183   },
4184
4185   /* X86_64_D5 */
4186   {
4187     { "aad", { Ib }, 0 },
4188   },
4189
4190   /* X86_64_E8 */
4191   {
4192     { "callP",          { Jv, BND }, 0 },
4193     { "call@",          { Jv, BND }, 0 }
4194   },
4195
4196   /* X86_64_E9 */
4197   {
4198     { "jmpP",           { Jv, BND }, 0 },
4199     { "jmp@",           { Jv, BND }, 0 }
4200   },
4201
4202   /* X86_64_EA */
4203   {
4204     { "{l|}jmp{P|}", { Ap }, 0 },
4205   },
4206
4207   /* X86_64_0F01_REG_0 */
4208   {
4209     { "sgdt{Q|Q}", { M }, 0 },
4210     { "sgdt", { M }, 0 },
4211   },
4212
4213   /* X86_64_0F01_REG_1 */
4214   {
4215     { "sidt{Q|Q}", { M }, 0 },
4216     { "sidt", { M }, 0 },
4217   },
4218
4219   /* X86_64_0F01_REG_1_RM_5_PREFIX_2 */
4220   {
4221     { Bad_Opcode },
4222     { "seamret",        { Skip_MODRM }, 0 },
4223   },
4224
4225   /* X86_64_0F01_REG_1_RM_6_PREFIX_2 */
4226   {
4227     { Bad_Opcode },
4228     { "seamops",        { Skip_MODRM }, 0 },
4229   },
4230
4231   /* X86_64_0F01_REG_1_RM_7_PREFIX_2 */
4232   {
4233     { Bad_Opcode },
4234     { "seamcall",       { Skip_MODRM }, 0 },
4235   },
4236
4237   /* X86_64_0F01_REG_2 */
4238   {
4239     { "lgdt{Q|Q}", { M }, 0 },
4240     { "lgdt", { M }, 0 },
4241   },
4242
4243   /* X86_64_0F01_REG_3 */
4244   {
4245     { "lidt{Q|Q}", { M }, 0 },
4246     { "lidt", { M }, 0 },
4247   },
4248
4249   /* X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1 */
4250   {
4251     { Bad_Opcode },
4252     { "uiret",  { Skip_MODRM }, 0 },
4253   },
4254
4255   /* X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1 */
4256   {
4257     { Bad_Opcode },
4258     { "testui", { Skip_MODRM }, 0 },
4259   },
4260
4261   /* X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1 */
4262   {
4263     { Bad_Opcode },
4264     { "clui",   { Skip_MODRM }, 0 },
4265   },
4266
4267   /* X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1 */
4268   {
4269     { Bad_Opcode },
4270     { "stui",   { Skip_MODRM }, 0 },
4271   },
4272
4273   /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1 */
4274   {
4275     { Bad_Opcode },
4276     { "rmpadjust",      { Skip_MODRM }, 0 },
4277   },
4278
4279   /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3 */
4280   {
4281     { Bad_Opcode },
4282     { "rmpupdate",      { Skip_MODRM }, 0 },
4283   },
4284
4285   /* X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1 */
4286   {
4287     { Bad_Opcode },
4288     { "psmash", { Skip_MODRM }, 0 },
4289   },
4290
4291   {
4292     /* X86_64_0F24 */
4293     { "movZ",           { Em, Td }, 0 },
4294   },
4295
4296   {
4297     /* X86_64_0F26 */
4298     { "movZ",           { Td, Em }, 0 },
4299   },
4300
4301   /* X86_64_0FC7_REG_6_MOD_3_PREFIX_1 */
4302   {
4303     { Bad_Opcode },
4304     { "senduipi",       { Eq }, 0 },
4305   },
4306
4307   /* X86_64_VEX_0F3849 */
4308   {
4309     { Bad_Opcode },
4310     { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64) },
4311   },
4312
4313   /* X86_64_VEX_0F384B */
4314   {
4315     { Bad_Opcode },
4316     { PREFIX_TABLE (PREFIX_VEX_0F384B_X86_64) },
4317   },
4318
4319   /* X86_64_VEX_0F385C */
4320   {
4321     { Bad_Opcode },
4322     { PREFIX_TABLE (PREFIX_VEX_0F385C_X86_64) },
4323   },
4324
4325   /* X86_64_VEX_0F385E */
4326   {
4327     { Bad_Opcode },
4328     { PREFIX_TABLE (PREFIX_VEX_0F385E_X86_64) },
4329   },
4330 };
4331
4332 static const struct dis386 three_byte_table[][256] = {
4333
4334   /* THREE_BYTE_0F38 */
4335   {
4336     /* 00 */
4337     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
4338     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
4339     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
4340     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
4341     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
4342     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
4343     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
4344     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
4345     /* 08 */
4346     { "psignb",         { MX, EM }, PREFIX_OPCODE },
4347     { "psignw",         { MX, EM }, PREFIX_OPCODE },
4348     { "psignd",         { MX, EM }, PREFIX_OPCODE },
4349     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
4350     { Bad_Opcode },
4351     { Bad_Opcode },
4352     { Bad_Opcode },
4353     { Bad_Opcode },
4354     /* 10 */
4355     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_DATA },
4356     { Bad_Opcode },
4357     { Bad_Opcode },
4358     { Bad_Opcode },
4359     { "blendvps", { XM, EXx, XMM0 }, PREFIX_DATA },
4360     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_DATA },
4361     { Bad_Opcode },
4362     { "ptest",  { XM, EXx }, PREFIX_DATA },
4363     /* 18 */
4364     { Bad_Opcode },
4365     { Bad_Opcode },
4366     { Bad_Opcode },
4367     { Bad_Opcode },
4368     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
4369     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
4370     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
4371     { Bad_Opcode },
4372     /* 20 */
4373     { "pmovsxbw", { XM, EXq }, PREFIX_DATA },
4374     { "pmovsxbd", { XM, EXd }, PREFIX_DATA },
4375     { "pmovsxbq", { XM, EXw }, PREFIX_DATA },
4376     { "pmovsxwd", { XM, EXq }, PREFIX_DATA },
4377     { "pmovsxwq", { XM, EXd }, PREFIX_DATA },
4378     { "pmovsxdq", { XM, EXq }, PREFIX_DATA },
4379     { Bad_Opcode },
4380     { Bad_Opcode },
4381     /* 28 */
4382     { "pmuldq", { XM, EXx }, PREFIX_DATA },
4383     { "pcmpeqq", { XM, EXx }, PREFIX_DATA },
4384     { MOD_TABLE (MOD_0F382A) },
4385     { "packusdw", { XM, EXx }, PREFIX_DATA },
4386     { Bad_Opcode },
4387     { Bad_Opcode },
4388     { Bad_Opcode },
4389     { Bad_Opcode },
4390     /* 30 */
4391     { "pmovzxbw", { XM, EXq }, PREFIX_DATA },
4392     { "pmovzxbd", { XM, EXd }, PREFIX_DATA },
4393     { "pmovzxbq", { XM, EXw }, PREFIX_DATA },
4394     { "pmovzxwd", { XM, EXq }, PREFIX_DATA },
4395     { "pmovzxwq", { XM, EXd }, PREFIX_DATA },
4396     { "pmovzxdq", { XM, EXq }, PREFIX_DATA },
4397     { Bad_Opcode },
4398     { "pcmpgtq", { XM, EXx }, PREFIX_DATA },
4399     /* 38 */
4400     { "pminsb", { XM, EXx }, PREFIX_DATA },
4401     { "pminsd", { XM, EXx }, PREFIX_DATA },
4402     { "pminuw", { XM, EXx }, PREFIX_DATA },
4403     { "pminud", { XM, EXx }, PREFIX_DATA },
4404     { "pmaxsb", { XM, EXx }, PREFIX_DATA },
4405     { "pmaxsd", { XM, EXx }, PREFIX_DATA },
4406     { "pmaxuw", { XM, EXx }, PREFIX_DATA },
4407     { "pmaxud", { XM, EXx }, PREFIX_DATA },
4408     /* 40 */
4409     { "pmulld", { XM, EXx }, PREFIX_DATA },
4410     { "phminposuw", { XM, EXx }, PREFIX_DATA },
4411     { Bad_Opcode },
4412     { Bad_Opcode },
4413     { Bad_Opcode },
4414     { Bad_Opcode },
4415     { Bad_Opcode },
4416     { Bad_Opcode },
4417     /* 48 */
4418     { Bad_Opcode },
4419     { Bad_Opcode },
4420     { Bad_Opcode },
4421     { Bad_Opcode },
4422     { Bad_Opcode },
4423     { Bad_Opcode },
4424     { Bad_Opcode },
4425     { Bad_Opcode },
4426     /* 50 */
4427     { Bad_Opcode },
4428     { Bad_Opcode },
4429     { Bad_Opcode },
4430     { Bad_Opcode },
4431     { Bad_Opcode },
4432     { Bad_Opcode },
4433     { Bad_Opcode },
4434     { Bad_Opcode },
4435     /* 58 */
4436     { Bad_Opcode },
4437     { Bad_Opcode },
4438     { Bad_Opcode },
4439     { Bad_Opcode },
4440     { Bad_Opcode },
4441     { Bad_Opcode },
4442     { Bad_Opcode },
4443     { Bad_Opcode },
4444     /* 60 */
4445     { Bad_Opcode },
4446     { Bad_Opcode },
4447     { Bad_Opcode },
4448     { Bad_Opcode },
4449     { Bad_Opcode },
4450     { Bad_Opcode },
4451     { Bad_Opcode },
4452     { Bad_Opcode },
4453     /* 68 */
4454     { Bad_Opcode },
4455     { Bad_Opcode },
4456     { Bad_Opcode },
4457     { Bad_Opcode },
4458     { Bad_Opcode },
4459     { Bad_Opcode },
4460     { Bad_Opcode },
4461     { Bad_Opcode },
4462     /* 70 */
4463     { Bad_Opcode },
4464     { Bad_Opcode },
4465     { Bad_Opcode },
4466     { Bad_Opcode },
4467     { Bad_Opcode },
4468     { Bad_Opcode },
4469     { Bad_Opcode },
4470     { Bad_Opcode },
4471     /* 78 */
4472     { Bad_Opcode },
4473     { Bad_Opcode },
4474     { Bad_Opcode },
4475     { Bad_Opcode },
4476     { Bad_Opcode },
4477     { Bad_Opcode },
4478     { Bad_Opcode },
4479     { Bad_Opcode },
4480     /* 80 */
4481     { "invept", { Gm, Mo }, PREFIX_DATA },
4482     { "invvpid", { Gm, Mo }, PREFIX_DATA },
4483     { "invpcid", { Gm, M }, PREFIX_DATA },
4484     { Bad_Opcode },
4485     { Bad_Opcode },
4486     { Bad_Opcode },
4487     { Bad_Opcode },
4488     { Bad_Opcode },
4489     /* 88 */
4490     { Bad_Opcode },
4491     { Bad_Opcode },
4492     { Bad_Opcode },
4493     { Bad_Opcode },
4494     { Bad_Opcode },
4495     { Bad_Opcode },
4496     { Bad_Opcode },
4497     { Bad_Opcode },
4498     /* 90 */
4499     { Bad_Opcode },
4500     { Bad_Opcode },
4501     { Bad_Opcode },
4502     { Bad_Opcode },
4503     { Bad_Opcode },
4504     { Bad_Opcode },
4505     { Bad_Opcode },
4506     { Bad_Opcode },
4507     /* 98 */
4508     { Bad_Opcode },
4509     { Bad_Opcode },
4510     { Bad_Opcode },
4511     { Bad_Opcode },
4512     { Bad_Opcode },
4513     { Bad_Opcode },
4514     { Bad_Opcode },
4515     { Bad_Opcode },
4516     /* a0 */
4517     { Bad_Opcode },
4518     { Bad_Opcode },
4519     { Bad_Opcode },
4520     { Bad_Opcode },
4521     { Bad_Opcode },
4522     { Bad_Opcode },
4523     { Bad_Opcode },
4524     { Bad_Opcode },
4525     /* a8 */
4526     { Bad_Opcode },
4527     { Bad_Opcode },
4528     { Bad_Opcode },
4529     { Bad_Opcode },
4530     { Bad_Opcode },
4531     { Bad_Opcode },
4532     { Bad_Opcode },
4533     { Bad_Opcode },
4534     /* b0 */
4535     { Bad_Opcode },
4536     { Bad_Opcode },
4537     { Bad_Opcode },
4538     { Bad_Opcode },
4539     { Bad_Opcode },
4540     { Bad_Opcode },
4541     { Bad_Opcode },
4542     { Bad_Opcode },
4543     /* b8 */
4544     { Bad_Opcode },
4545     { Bad_Opcode },
4546     { Bad_Opcode },
4547     { Bad_Opcode },
4548     { Bad_Opcode },
4549     { Bad_Opcode },
4550     { Bad_Opcode },
4551     { Bad_Opcode },
4552     /* c0 */
4553     { Bad_Opcode },
4554     { Bad_Opcode },
4555     { Bad_Opcode },
4556     { Bad_Opcode },
4557     { Bad_Opcode },
4558     { Bad_Opcode },
4559     { Bad_Opcode },
4560     { Bad_Opcode },
4561     /* c8 */
4562     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4563     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4564     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4565     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4566     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4567     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4568     { Bad_Opcode },
4569     { "gf2p8mulb", { XM, EXxmm }, PREFIX_DATA },
4570     /* d0 */
4571     { Bad_Opcode },
4572     { Bad_Opcode },
4573     { Bad_Opcode },
4574     { Bad_Opcode },
4575     { Bad_Opcode },
4576     { Bad_Opcode },
4577     { Bad_Opcode },
4578     { Bad_Opcode },
4579     /* d8 */
4580     { PREFIX_TABLE (PREFIX_0F38D8) },
4581     { Bad_Opcode },
4582     { Bad_Opcode },
4583     { "aesimc", { XM, EXx }, PREFIX_DATA },
4584     { PREFIX_TABLE (PREFIX_0F38DC) },
4585     { PREFIX_TABLE (PREFIX_0F38DD) },
4586     { PREFIX_TABLE (PREFIX_0F38DE) },
4587     { PREFIX_TABLE (PREFIX_0F38DF) },
4588     /* e0 */
4589     { Bad_Opcode },
4590     { Bad_Opcode },
4591     { Bad_Opcode },
4592     { Bad_Opcode },
4593     { Bad_Opcode },
4594     { Bad_Opcode },
4595     { Bad_Opcode },
4596     { Bad_Opcode },
4597     /* e8 */
4598     { Bad_Opcode },
4599     { Bad_Opcode },
4600     { Bad_Opcode },
4601     { Bad_Opcode },
4602     { Bad_Opcode },
4603     { Bad_Opcode },
4604     { Bad_Opcode },
4605     { Bad_Opcode },
4606     /* f0 */
4607     { PREFIX_TABLE (PREFIX_0F38F0) },
4608     { PREFIX_TABLE (PREFIX_0F38F1) },
4609     { Bad_Opcode },
4610     { Bad_Opcode },
4611     { Bad_Opcode },
4612     { MOD_TABLE (MOD_0F38F5) },
4613     { PREFIX_TABLE (PREFIX_0F38F6) },
4614     { Bad_Opcode },
4615     /* f8 */
4616     { PREFIX_TABLE (PREFIX_0F38F8) },
4617     { MOD_TABLE (MOD_0F38F9) },
4618     { PREFIX_TABLE (PREFIX_0F38FA) },
4619     { PREFIX_TABLE (PREFIX_0F38FB) },
4620     { Bad_Opcode },
4621     { Bad_Opcode },
4622     { Bad_Opcode },
4623     { Bad_Opcode },
4624   },
4625   /* THREE_BYTE_0F3A */
4626   {
4627     /* 00 */
4628     { Bad_Opcode },
4629     { Bad_Opcode },
4630     { Bad_Opcode },
4631     { Bad_Opcode },
4632     { Bad_Opcode },
4633     { Bad_Opcode },
4634     { Bad_Opcode },
4635     { Bad_Opcode },
4636     /* 08 */
4637     { "roundps", { XM, EXx, Ib }, PREFIX_DATA },
4638     { "roundpd", { XM, EXx, Ib }, PREFIX_DATA },
4639     { "roundss", { XM, EXd, Ib }, PREFIX_DATA },
4640     { "roundsd", { XM, EXq, Ib }, PREFIX_DATA },
4641     { "blendps", { XM, EXx, Ib }, PREFIX_DATA },
4642     { "blendpd", { XM, EXx, Ib }, PREFIX_DATA },
4643     { "pblendw", { XM, EXx, Ib }, PREFIX_DATA },
4644     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
4645     /* 10 */
4646     { Bad_Opcode },
4647     { Bad_Opcode },
4648     { Bad_Opcode },
4649     { Bad_Opcode },
4650     { "pextrb", { Edb, XM, Ib }, PREFIX_DATA },
4651     { "pextrw", { Edw, XM, Ib }, PREFIX_DATA },
4652     { "pextrK", { Edq, XM, Ib }, PREFIX_DATA },
4653     { "extractps", { Ed, XM, Ib }, PREFIX_DATA },
4654     /* 18 */
4655     { Bad_Opcode },
4656     { Bad_Opcode },
4657     { Bad_Opcode },
4658     { Bad_Opcode },
4659     { Bad_Opcode },
4660     { Bad_Opcode },
4661     { Bad_Opcode },
4662     { Bad_Opcode },
4663     /* 20 */
4664     { "pinsrb", { XM, Edb, Ib }, PREFIX_DATA },
4665     { "insertps", { XM, EXd, Ib }, PREFIX_DATA },
4666     { "pinsrK", { XM, Edq, Ib }, PREFIX_DATA },
4667     { Bad_Opcode },
4668     { Bad_Opcode },
4669     { Bad_Opcode },
4670     { Bad_Opcode },
4671     { Bad_Opcode },
4672     /* 28 */
4673     { Bad_Opcode },
4674     { Bad_Opcode },
4675     { Bad_Opcode },
4676     { Bad_Opcode },
4677     { Bad_Opcode },
4678     { Bad_Opcode },
4679     { Bad_Opcode },
4680     { Bad_Opcode },
4681     /* 30 */
4682     { Bad_Opcode },
4683     { Bad_Opcode },
4684     { Bad_Opcode },
4685     { Bad_Opcode },
4686     { Bad_Opcode },
4687     { Bad_Opcode },
4688     { Bad_Opcode },
4689     { Bad_Opcode },
4690     /* 38 */
4691     { Bad_Opcode },
4692     { Bad_Opcode },
4693     { Bad_Opcode },
4694     { Bad_Opcode },
4695     { Bad_Opcode },
4696     { Bad_Opcode },
4697     { Bad_Opcode },
4698     { Bad_Opcode },
4699     /* 40 */
4700     { "dpps",   { XM, EXx, Ib }, PREFIX_DATA },
4701     { "dppd",   { XM, EXx, Ib }, PREFIX_DATA },
4702     { "mpsadbw", { XM, EXx, Ib }, PREFIX_DATA },
4703     { Bad_Opcode },
4704     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_DATA },
4705     { Bad_Opcode },
4706     { Bad_Opcode },
4707     { Bad_Opcode },
4708     /* 48 */
4709     { Bad_Opcode },
4710     { Bad_Opcode },
4711     { Bad_Opcode },
4712     { Bad_Opcode },
4713     { Bad_Opcode },
4714     { Bad_Opcode },
4715     { Bad_Opcode },
4716     { Bad_Opcode },
4717     /* 50 */
4718     { Bad_Opcode },
4719     { Bad_Opcode },
4720     { Bad_Opcode },
4721     { Bad_Opcode },
4722     { Bad_Opcode },
4723     { Bad_Opcode },
4724     { Bad_Opcode },
4725     { Bad_Opcode },
4726     /* 58 */
4727     { Bad_Opcode },
4728     { Bad_Opcode },
4729     { Bad_Opcode },
4730     { Bad_Opcode },
4731     { Bad_Opcode },
4732     { Bad_Opcode },
4733     { Bad_Opcode },
4734     { Bad_Opcode },
4735     /* 60 */
4736     { "pcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
4737     { "pcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
4738     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_DATA },
4739     { "pcmpistri", { XM, EXx, Ib }, PREFIX_DATA },
4740     { Bad_Opcode },
4741     { Bad_Opcode },
4742     { Bad_Opcode },
4743     { Bad_Opcode },
4744     /* 68 */
4745     { Bad_Opcode },
4746     { Bad_Opcode },
4747     { Bad_Opcode },
4748     { Bad_Opcode },
4749     { Bad_Opcode },
4750     { Bad_Opcode },
4751     { Bad_Opcode },
4752     { Bad_Opcode },
4753     /* 70 */
4754     { Bad_Opcode },
4755     { Bad_Opcode },
4756     { Bad_Opcode },
4757     { Bad_Opcode },
4758     { Bad_Opcode },
4759     { Bad_Opcode },
4760     { Bad_Opcode },
4761     { Bad_Opcode },
4762     /* 78 */
4763     { Bad_Opcode },
4764     { Bad_Opcode },
4765     { Bad_Opcode },
4766     { Bad_Opcode },
4767     { Bad_Opcode },
4768     { Bad_Opcode },
4769     { Bad_Opcode },
4770     { Bad_Opcode },
4771     /* 80 */
4772     { Bad_Opcode },
4773     { Bad_Opcode },
4774     { Bad_Opcode },
4775     { Bad_Opcode },
4776     { Bad_Opcode },
4777     { Bad_Opcode },
4778     { Bad_Opcode },
4779     { Bad_Opcode },
4780     /* 88 */
4781     { Bad_Opcode },
4782     { Bad_Opcode },
4783     { Bad_Opcode },
4784     { Bad_Opcode },
4785     { Bad_Opcode },
4786     { Bad_Opcode },
4787     { Bad_Opcode },
4788     { Bad_Opcode },
4789     /* 90 */
4790     { Bad_Opcode },
4791     { Bad_Opcode },
4792     { Bad_Opcode },
4793     { Bad_Opcode },
4794     { Bad_Opcode },
4795     { Bad_Opcode },
4796     { Bad_Opcode },
4797     { Bad_Opcode },
4798     /* 98 */
4799     { Bad_Opcode },
4800     { Bad_Opcode },
4801     { Bad_Opcode },
4802     { Bad_Opcode },
4803     { Bad_Opcode },
4804     { Bad_Opcode },
4805     { Bad_Opcode },
4806     { Bad_Opcode },
4807     /* a0 */
4808     { Bad_Opcode },
4809     { Bad_Opcode },
4810     { Bad_Opcode },
4811     { Bad_Opcode },
4812     { Bad_Opcode },
4813     { Bad_Opcode },
4814     { Bad_Opcode },
4815     { Bad_Opcode },
4816     /* a8 */
4817     { Bad_Opcode },
4818     { Bad_Opcode },
4819     { Bad_Opcode },
4820     { Bad_Opcode },
4821     { Bad_Opcode },
4822     { Bad_Opcode },
4823     { Bad_Opcode },
4824     { Bad_Opcode },
4825     /* b0 */
4826     { Bad_Opcode },
4827     { Bad_Opcode },
4828     { Bad_Opcode },
4829     { Bad_Opcode },
4830     { Bad_Opcode },
4831     { Bad_Opcode },
4832     { Bad_Opcode },
4833     { Bad_Opcode },
4834     /* b8 */
4835     { Bad_Opcode },
4836     { Bad_Opcode },
4837     { Bad_Opcode },
4838     { Bad_Opcode },
4839     { Bad_Opcode },
4840     { Bad_Opcode },
4841     { Bad_Opcode },
4842     { Bad_Opcode },
4843     /* c0 */
4844     { Bad_Opcode },
4845     { Bad_Opcode },
4846     { Bad_Opcode },
4847     { Bad_Opcode },
4848     { Bad_Opcode },
4849     { Bad_Opcode },
4850     { Bad_Opcode },
4851     { Bad_Opcode },
4852     /* c8 */
4853     { Bad_Opcode },
4854     { Bad_Opcode },
4855     { Bad_Opcode },
4856     { Bad_Opcode },
4857     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4858     { Bad_Opcode },
4859     { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_DATA },
4860     { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_DATA },
4861     /* d0 */
4862     { Bad_Opcode },
4863     { Bad_Opcode },
4864     { Bad_Opcode },
4865     { Bad_Opcode },
4866     { Bad_Opcode },
4867     { Bad_Opcode },
4868     { Bad_Opcode },
4869     { Bad_Opcode },
4870     /* d8 */
4871     { Bad_Opcode },
4872     { Bad_Opcode },
4873     { Bad_Opcode },
4874     { Bad_Opcode },
4875     { Bad_Opcode },
4876     { Bad_Opcode },
4877     { Bad_Opcode },
4878     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
4879     /* e0 */
4880     { Bad_Opcode },
4881     { Bad_Opcode },
4882     { Bad_Opcode },
4883     { Bad_Opcode },
4884     { Bad_Opcode },
4885     { Bad_Opcode },
4886     { Bad_Opcode },
4887     { Bad_Opcode },
4888     /* e8 */
4889     { Bad_Opcode },
4890     { Bad_Opcode },
4891     { Bad_Opcode },
4892     { Bad_Opcode },
4893     { Bad_Opcode },
4894     { Bad_Opcode },
4895     { Bad_Opcode },
4896     { Bad_Opcode },
4897     /* f0 */
4898     { PREFIX_TABLE (PREFIX_0F3A0F) },
4899     { Bad_Opcode },
4900     { Bad_Opcode },
4901     { Bad_Opcode },
4902     { Bad_Opcode },
4903     { Bad_Opcode },
4904     { Bad_Opcode },
4905     { Bad_Opcode },
4906     /* f8 */
4907     { Bad_Opcode },
4908     { Bad_Opcode },
4909     { Bad_Opcode },
4910     { Bad_Opcode },
4911     { Bad_Opcode },
4912     { Bad_Opcode },
4913     { Bad_Opcode },
4914     { Bad_Opcode },
4915   },
4916 };
4917
4918 static const struct dis386 xop_table[][256] = {
4919   /* XOP_08 */
4920   {
4921     /* 00 */
4922     { Bad_Opcode },
4923     { Bad_Opcode },
4924     { Bad_Opcode },
4925     { Bad_Opcode },
4926     { Bad_Opcode },
4927     { Bad_Opcode },
4928     { Bad_Opcode },
4929     { Bad_Opcode },
4930     /* 08 */
4931     { Bad_Opcode },
4932     { Bad_Opcode },
4933     { Bad_Opcode },
4934     { Bad_Opcode },
4935     { Bad_Opcode },
4936     { Bad_Opcode },
4937     { Bad_Opcode },
4938     { Bad_Opcode },
4939     /* 10 */
4940     { Bad_Opcode },
4941     { Bad_Opcode },
4942     { Bad_Opcode },
4943     { Bad_Opcode },
4944     { Bad_Opcode },
4945     { Bad_Opcode },
4946     { Bad_Opcode },
4947     { Bad_Opcode },
4948     /* 18 */
4949     { Bad_Opcode },
4950     { Bad_Opcode },
4951     { Bad_Opcode },
4952     { Bad_Opcode },
4953     { Bad_Opcode },
4954     { Bad_Opcode },
4955     { Bad_Opcode },
4956     { Bad_Opcode },
4957     /* 20 */
4958     { Bad_Opcode },
4959     { Bad_Opcode },
4960     { Bad_Opcode },
4961     { Bad_Opcode },
4962     { Bad_Opcode },
4963     { Bad_Opcode },
4964     { Bad_Opcode },
4965     { Bad_Opcode },
4966     /* 28 */
4967     { Bad_Opcode },
4968     { Bad_Opcode },
4969     { Bad_Opcode },
4970     { Bad_Opcode },
4971     { Bad_Opcode },
4972     { Bad_Opcode },
4973     { Bad_Opcode },
4974     { Bad_Opcode },
4975     /* 30 */
4976     { Bad_Opcode },
4977     { Bad_Opcode },
4978     { Bad_Opcode },
4979     { Bad_Opcode },
4980     { Bad_Opcode },
4981     { Bad_Opcode },
4982     { Bad_Opcode },
4983     { Bad_Opcode },
4984     /* 38 */
4985     { Bad_Opcode },
4986     { Bad_Opcode },
4987     { Bad_Opcode },
4988     { Bad_Opcode },
4989     { Bad_Opcode },
4990     { Bad_Opcode },
4991     { Bad_Opcode },
4992     { Bad_Opcode },
4993     /* 40 */
4994     { Bad_Opcode },
4995     { Bad_Opcode },
4996     { Bad_Opcode },
4997     { Bad_Opcode },
4998     { Bad_Opcode },
4999     { Bad_Opcode },
5000     { Bad_Opcode },
5001     { Bad_Opcode },
5002     /* 48 */
5003     { Bad_Opcode },
5004     { Bad_Opcode },
5005     { Bad_Opcode },
5006     { Bad_Opcode },
5007     { Bad_Opcode },
5008     { Bad_Opcode },
5009     { Bad_Opcode },
5010     { Bad_Opcode },
5011     /* 50 */
5012     { Bad_Opcode },
5013     { Bad_Opcode },
5014     { Bad_Opcode },
5015     { Bad_Opcode },
5016     { Bad_Opcode },
5017     { Bad_Opcode },
5018     { Bad_Opcode },
5019     { Bad_Opcode },
5020     /* 58 */
5021     { Bad_Opcode },
5022     { Bad_Opcode },
5023     { Bad_Opcode },
5024     { Bad_Opcode },
5025     { Bad_Opcode },
5026     { Bad_Opcode },
5027     { Bad_Opcode },
5028     { Bad_Opcode },
5029     /* 60 */
5030     { Bad_Opcode },
5031     { Bad_Opcode },
5032     { Bad_Opcode },
5033     { Bad_Opcode },
5034     { Bad_Opcode },
5035     { Bad_Opcode },
5036     { Bad_Opcode },
5037     { Bad_Opcode },
5038     /* 68 */
5039     { Bad_Opcode },
5040     { Bad_Opcode },
5041     { Bad_Opcode },
5042     { Bad_Opcode },
5043     { Bad_Opcode },
5044     { Bad_Opcode },
5045     { Bad_Opcode },
5046     { Bad_Opcode },
5047     /* 70 */
5048     { Bad_Opcode },
5049     { Bad_Opcode },
5050     { Bad_Opcode },
5051     { Bad_Opcode },
5052     { Bad_Opcode },
5053     { Bad_Opcode },
5054     { Bad_Opcode },
5055     { Bad_Opcode },
5056     /* 78 */
5057     { Bad_Opcode },
5058     { Bad_Opcode },
5059     { Bad_Opcode },
5060     { Bad_Opcode },
5061     { Bad_Opcode },
5062     { Bad_Opcode },
5063     { Bad_Opcode },
5064     { Bad_Opcode },
5065     /* 80 */
5066     { Bad_Opcode },
5067     { Bad_Opcode },
5068     { Bad_Opcode },
5069     { Bad_Opcode },
5070     { Bad_Opcode },
5071     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_85) },
5072     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_86) },
5073     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_87) },
5074     /* 88 */
5075     { Bad_Opcode },
5076     { Bad_Opcode },
5077     { Bad_Opcode },
5078     { Bad_Opcode },
5079     { Bad_Opcode },
5080     { Bad_Opcode },
5081     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8E) },
5082     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8F) },
5083     /* 90 */
5084     { Bad_Opcode },
5085     { Bad_Opcode },
5086     { Bad_Opcode },
5087     { Bad_Opcode },
5088     { Bad_Opcode },
5089     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_95) },
5090     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_96) },
5091     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_97) },
5092     /* 98 */
5093     { Bad_Opcode },
5094     { Bad_Opcode },
5095     { Bad_Opcode },
5096     { Bad_Opcode },
5097     { Bad_Opcode },
5098     { Bad_Opcode },
5099     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9E) },
5100     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9F) },
5101     /* a0 */
5102     { Bad_Opcode },
5103     { Bad_Opcode },
5104     { "vpcmov",         { XM, Vex, EXx, XMVexI4 }, 0 },
5105     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A3) },
5106     { Bad_Opcode },
5107     { Bad_Opcode },
5108     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A6) },
5109     { Bad_Opcode },
5110     /* a8 */
5111     { Bad_Opcode },
5112     { Bad_Opcode },
5113     { Bad_Opcode },
5114     { Bad_Opcode },
5115     { Bad_Opcode },
5116     { Bad_Opcode },
5117     { Bad_Opcode },
5118     { Bad_Opcode },
5119     /* b0 */
5120     { Bad_Opcode },
5121     { Bad_Opcode },
5122     { Bad_Opcode },
5123     { Bad_Opcode },
5124     { Bad_Opcode },
5125     { Bad_Opcode },
5126     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_B6) },
5127     { Bad_Opcode },
5128     /* b8 */
5129     { Bad_Opcode },
5130     { Bad_Opcode },
5131     { Bad_Opcode },
5132     { Bad_Opcode },
5133     { Bad_Opcode },
5134     { Bad_Opcode },
5135     { Bad_Opcode },
5136     { Bad_Opcode },
5137     /* c0 */
5138     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C0) },
5139     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C1) },
5140     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C2) },
5141     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C3) },
5142     { Bad_Opcode },
5143     { Bad_Opcode },
5144     { Bad_Opcode },
5145     { Bad_Opcode },
5146     /* c8 */
5147     { Bad_Opcode },
5148     { Bad_Opcode },
5149     { Bad_Opcode },
5150     { Bad_Opcode },
5151     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
5152     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
5153     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
5154     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
5155     /* d0 */
5156     { Bad_Opcode },
5157     { Bad_Opcode },
5158     { Bad_Opcode },
5159     { Bad_Opcode },
5160     { Bad_Opcode },
5161     { Bad_Opcode },
5162     { Bad_Opcode },
5163     { Bad_Opcode },
5164     /* d8 */
5165     { Bad_Opcode },
5166     { Bad_Opcode },
5167     { Bad_Opcode },
5168     { Bad_Opcode },
5169     { Bad_Opcode },
5170     { Bad_Opcode },
5171     { Bad_Opcode },
5172     { Bad_Opcode },
5173     /* e0 */
5174     { Bad_Opcode },
5175     { Bad_Opcode },
5176     { Bad_Opcode },
5177     { Bad_Opcode },
5178     { Bad_Opcode },
5179     { Bad_Opcode },
5180     { Bad_Opcode },
5181     { Bad_Opcode },
5182     /* e8 */
5183     { Bad_Opcode },
5184     { Bad_Opcode },
5185     { Bad_Opcode },
5186     { Bad_Opcode },
5187     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
5188     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
5189     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
5190     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
5191     /* f0 */
5192     { Bad_Opcode },
5193     { Bad_Opcode },
5194     { Bad_Opcode },
5195     { Bad_Opcode },
5196     { Bad_Opcode },
5197     { Bad_Opcode },
5198     { Bad_Opcode },
5199     { Bad_Opcode },
5200     /* f8 */
5201     { Bad_Opcode },
5202     { Bad_Opcode },
5203     { Bad_Opcode },
5204     { Bad_Opcode },
5205     { Bad_Opcode },
5206     { Bad_Opcode },
5207     { Bad_Opcode },
5208     { Bad_Opcode },
5209   },
5210   /* XOP_09 */
5211   {
5212     /* 00 */
5213     { Bad_Opcode },
5214     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_01) },
5215     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_02) },
5216     { Bad_Opcode },
5217     { Bad_Opcode },
5218     { Bad_Opcode },
5219     { Bad_Opcode },
5220     { Bad_Opcode },
5221     /* 08 */
5222     { Bad_Opcode },
5223     { Bad_Opcode },
5224     { Bad_Opcode },
5225     { Bad_Opcode },
5226     { Bad_Opcode },
5227     { Bad_Opcode },
5228     { Bad_Opcode },
5229     { Bad_Opcode },
5230     /* 10 */
5231     { Bad_Opcode },
5232     { Bad_Opcode },
5233     { MOD_TABLE (MOD_XOP_09_12) },
5234     { Bad_Opcode },
5235     { Bad_Opcode },
5236     { Bad_Opcode },
5237     { Bad_Opcode },
5238     { Bad_Opcode },
5239     /* 18 */
5240     { Bad_Opcode },
5241     { Bad_Opcode },
5242     { Bad_Opcode },
5243     { Bad_Opcode },
5244     { Bad_Opcode },
5245     { Bad_Opcode },
5246     { Bad_Opcode },
5247     { Bad_Opcode },
5248     /* 20 */
5249     { Bad_Opcode },
5250     { Bad_Opcode },
5251     { Bad_Opcode },
5252     { Bad_Opcode },
5253     { Bad_Opcode },
5254     { Bad_Opcode },
5255     { Bad_Opcode },
5256     { Bad_Opcode },
5257     /* 28 */
5258     { Bad_Opcode },
5259     { Bad_Opcode },
5260     { Bad_Opcode },
5261     { Bad_Opcode },
5262     { Bad_Opcode },
5263     { Bad_Opcode },
5264     { Bad_Opcode },
5265     { Bad_Opcode },
5266     /* 30 */
5267     { Bad_Opcode },
5268     { Bad_Opcode },
5269     { Bad_Opcode },
5270     { Bad_Opcode },
5271     { Bad_Opcode },
5272     { Bad_Opcode },
5273     { Bad_Opcode },
5274     { Bad_Opcode },
5275     /* 38 */
5276     { Bad_Opcode },
5277     { Bad_Opcode },
5278     { Bad_Opcode },
5279     { Bad_Opcode },
5280     { Bad_Opcode },
5281     { Bad_Opcode },
5282     { Bad_Opcode },
5283     { Bad_Opcode },
5284     /* 40 */
5285     { Bad_Opcode },
5286     { Bad_Opcode },
5287     { Bad_Opcode },
5288     { Bad_Opcode },
5289     { Bad_Opcode },
5290     { Bad_Opcode },
5291     { Bad_Opcode },
5292     { Bad_Opcode },
5293     /* 48 */
5294     { Bad_Opcode },
5295     { Bad_Opcode },
5296     { Bad_Opcode },
5297     { Bad_Opcode },
5298     { Bad_Opcode },
5299     { Bad_Opcode },
5300     { Bad_Opcode },
5301     { Bad_Opcode },
5302     /* 50 */
5303     { Bad_Opcode },
5304     { Bad_Opcode },
5305     { Bad_Opcode },
5306     { Bad_Opcode },
5307     { Bad_Opcode },
5308     { Bad_Opcode },
5309     { Bad_Opcode },
5310     { Bad_Opcode },
5311     /* 58 */
5312     { Bad_Opcode },
5313     { Bad_Opcode },
5314     { Bad_Opcode },
5315     { Bad_Opcode },
5316     { Bad_Opcode },
5317     { Bad_Opcode },
5318     { Bad_Opcode },
5319     { Bad_Opcode },
5320     /* 60 */
5321     { Bad_Opcode },
5322     { Bad_Opcode },
5323     { Bad_Opcode },
5324     { Bad_Opcode },
5325     { Bad_Opcode },
5326     { Bad_Opcode },
5327     { Bad_Opcode },
5328     { Bad_Opcode },
5329     /* 68 */
5330     { Bad_Opcode },
5331     { Bad_Opcode },
5332     { Bad_Opcode },
5333     { Bad_Opcode },
5334     { Bad_Opcode },
5335     { Bad_Opcode },
5336     { Bad_Opcode },
5337     { Bad_Opcode },
5338     /* 70 */
5339     { Bad_Opcode },
5340     { Bad_Opcode },
5341     { Bad_Opcode },
5342     { Bad_Opcode },
5343     { Bad_Opcode },
5344     { Bad_Opcode },
5345     { Bad_Opcode },
5346     { Bad_Opcode },
5347     /* 78 */
5348     { Bad_Opcode },
5349     { Bad_Opcode },
5350     { Bad_Opcode },
5351     { Bad_Opcode },
5352     { Bad_Opcode },
5353     { Bad_Opcode },
5354     { Bad_Opcode },
5355     { Bad_Opcode },
5356     /* 80 */
5357     { VEX_W_TABLE (VEX_W_0FXOP_09_80) },
5358     { VEX_W_TABLE (VEX_W_0FXOP_09_81) },
5359     { VEX_W_TABLE (VEX_W_0FXOP_09_82) },
5360     { VEX_W_TABLE (VEX_W_0FXOP_09_83) },
5361     { Bad_Opcode },
5362     { Bad_Opcode },
5363     { Bad_Opcode },
5364     { Bad_Opcode },
5365     /* 88 */
5366     { Bad_Opcode },
5367     { Bad_Opcode },
5368     { Bad_Opcode },
5369     { Bad_Opcode },
5370     { Bad_Opcode },
5371     { Bad_Opcode },
5372     { Bad_Opcode },
5373     { Bad_Opcode },
5374     /* 90 */
5375     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_90) },
5376     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_91) },
5377     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_92) },
5378     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_93) },
5379     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_94) },
5380     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_95) },
5381     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_96) },
5382     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_97) },
5383     /* 98 */
5384     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_98) },
5385     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_99) },
5386     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9A) },
5387     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9B) },
5388     { Bad_Opcode },
5389     { Bad_Opcode },
5390     { Bad_Opcode },
5391     { Bad_Opcode },
5392     /* a0 */
5393     { Bad_Opcode },
5394     { Bad_Opcode },
5395     { Bad_Opcode },
5396     { Bad_Opcode },
5397     { Bad_Opcode },
5398     { Bad_Opcode },
5399     { Bad_Opcode },
5400     { Bad_Opcode },
5401     /* a8 */
5402     { Bad_Opcode },
5403     { Bad_Opcode },
5404     { Bad_Opcode },
5405     { Bad_Opcode },
5406     { Bad_Opcode },
5407     { Bad_Opcode },
5408     { Bad_Opcode },
5409     { Bad_Opcode },
5410     /* b0 */
5411     { Bad_Opcode },
5412     { Bad_Opcode },
5413     { Bad_Opcode },
5414     { Bad_Opcode },
5415     { Bad_Opcode },
5416     { Bad_Opcode },
5417     { Bad_Opcode },
5418     { Bad_Opcode },
5419     /* b8 */
5420     { Bad_Opcode },
5421     { Bad_Opcode },
5422     { Bad_Opcode },
5423     { Bad_Opcode },
5424     { Bad_Opcode },
5425     { Bad_Opcode },
5426     { Bad_Opcode },
5427     { Bad_Opcode },
5428     /* c0 */
5429     { Bad_Opcode },
5430     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C1) },
5431     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C2) },
5432     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C3) },
5433     { Bad_Opcode },
5434     { Bad_Opcode },
5435     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C6) },
5436     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C7) },
5437     /* c8 */
5438     { Bad_Opcode },
5439     { Bad_Opcode },
5440     { Bad_Opcode },
5441     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_CB) },
5442     { Bad_Opcode },
5443     { Bad_Opcode },
5444     { Bad_Opcode },
5445     { Bad_Opcode },
5446     /* d0 */
5447     { Bad_Opcode },
5448     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D1) },
5449     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D2) },
5450     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D3) },
5451     { Bad_Opcode },
5452     { Bad_Opcode },
5453     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D6) },
5454     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D7) },
5455     /* d8 */
5456     { Bad_Opcode },
5457     { Bad_Opcode },
5458     { Bad_Opcode },
5459     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_DB) },
5460     { Bad_Opcode },
5461     { Bad_Opcode },
5462     { Bad_Opcode },
5463     { Bad_Opcode },
5464     /* e0 */
5465     { Bad_Opcode },
5466     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E1) },
5467     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E2) },
5468     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E3) },
5469     { Bad_Opcode },
5470     { Bad_Opcode },
5471     { Bad_Opcode },
5472     { Bad_Opcode },
5473     /* e8 */
5474     { Bad_Opcode },
5475     { Bad_Opcode },
5476     { Bad_Opcode },
5477     { Bad_Opcode },
5478     { Bad_Opcode },
5479     { Bad_Opcode },
5480     { Bad_Opcode },
5481     { Bad_Opcode },
5482     /* f0 */
5483     { Bad_Opcode },
5484     { Bad_Opcode },
5485     { Bad_Opcode },
5486     { Bad_Opcode },
5487     { Bad_Opcode },
5488     { Bad_Opcode },
5489     { Bad_Opcode },
5490     { Bad_Opcode },
5491     /* f8 */
5492     { Bad_Opcode },
5493     { Bad_Opcode },
5494     { Bad_Opcode },
5495     { Bad_Opcode },
5496     { Bad_Opcode },
5497     { Bad_Opcode },
5498     { Bad_Opcode },
5499     { Bad_Opcode },
5500   },
5501   /* XOP_0A */
5502   {
5503     /* 00 */
5504     { Bad_Opcode },
5505     { Bad_Opcode },
5506     { Bad_Opcode },
5507     { Bad_Opcode },
5508     { Bad_Opcode },
5509     { Bad_Opcode },
5510     { Bad_Opcode },
5511     { Bad_Opcode },
5512     /* 08 */
5513     { Bad_Opcode },
5514     { Bad_Opcode },
5515     { Bad_Opcode },
5516     { Bad_Opcode },
5517     { Bad_Opcode },
5518     { Bad_Opcode },
5519     { Bad_Opcode },
5520     { Bad_Opcode },
5521     /* 10 */
5522     { "bextrS", { Gdq, Edq, Id }, 0 },
5523     { Bad_Opcode },
5524     { VEX_LEN_TABLE (VEX_LEN_0FXOP_0A_12) },
5525     { Bad_Opcode },
5526     { Bad_Opcode },
5527     { Bad_Opcode },
5528     { Bad_Opcode },
5529     { Bad_Opcode },
5530     /* 18 */
5531     { Bad_Opcode },
5532     { Bad_Opcode },
5533     { Bad_Opcode },
5534     { Bad_Opcode },
5535     { Bad_Opcode },
5536     { Bad_Opcode },
5537     { Bad_Opcode },
5538     { Bad_Opcode },
5539     /* 20 */
5540     { Bad_Opcode },
5541     { Bad_Opcode },
5542     { Bad_Opcode },
5543     { Bad_Opcode },
5544     { Bad_Opcode },
5545     { Bad_Opcode },
5546     { Bad_Opcode },
5547     { Bad_Opcode },
5548     /* 28 */
5549     { Bad_Opcode },
5550     { Bad_Opcode },
5551     { Bad_Opcode },
5552     { Bad_Opcode },
5553     { Bad_Opcode },
5554     { Bad_Opcode },
5555     { Bad_Opcode },
5556     { Bad_Opcode },
5557     /* 30 */
5558     { Bad_Opcode },
5559     { Bad_Opcode },
5560     { Bad_Opcode },
5561     { Bad_Opcode },
5562     { Bad_Opcode },
5563     { Bad_Opcode },
5564     { Bad_Opcode },
5565     { Bad_Opcode },
5566     /* 38 */
5567     { Bad_Opcode },
5568     { Bad_Opcode },
5569     { Bad_Opcode },
5570     { Bad_Opcode },
5571     { Bad_Opcode },
5572     { Bad_Opcode },
5573     { Bad_Opcode },
5574     { Bad_Opcode },
5575     /* 40 */
5576     { Bad_Opcode },
5577     { Bad_Opcode },
5578     { Bad_Opcode },
5579     { Bad_Opcode },
5580     { Bad_Opcode },
5581     { Bad_Opcode },
5582     { Bad_Opcode },
5583     { Bad_Opcode },
5584     /* 48 */
5585     { Bad_Opcode },
5586     { Bad_Opcode },
5587     { Bad_Opcode },
5588     { Bad_Opcode },
5589     { Bad_Opcode },
5590     { Bad_Opcode },
5591     { Bad_Opcode },
5592     { Bad_Opcode },
5593     /* 50 */
5594     { Bad_Opcode },
5595     { Bad_Opcode },
5596     { Bad_Opcode },
5597     { Bad_Opcode },
5598     { Bad_Opcode },
5599     { Bad_Opcode },
5600     { Bad_Opcode },
5601     { Bad_Opcode },
5602     /* 58 */
5603     { Bad_Opcode },
5604     { Bad_Opcode },
5605     { Bad_Opcode },
5606     { Bad_Opcode },
5607     { Bad_Opcode },
5608     { Bad_Opcode },
5609     { Bad_Opcode },
5610     { Bad_Opcode },
5611     /* 60 */
5612     { Bad_Opcode },
5613     { Bad_Opcode },
5614     { Bad_Opcode },
5615     { Bad_Opcode },
5616     { Bad_Opcode },
5617     { Bad_Opcode },
5618     { Bad_Opcode },
5619     { Bad_Opcode },
5620     /* 68 */
5621     { Bad_Opcode },
5622     { Bad_Opcode },
5623     { Bad_Opcode },
5624     { Bad_Opcode },
5625     { Bad_Opcode },
5626     { Bad_Opcode },
5627     { Bad_Opcode },
5628     { Bad_Opcode },
5629     /* 70 */
5630     { Bad_Opcode },
5631     { Bad_Opcode },
5632     { Bad_Opcode },
5633     { Bad_Opcode },
5634     { Bad_Opcode },
5635     { Bad_Opcode },
5636     { Bad_Opcode },
5637     { Bad_Opcode },
5638     /* 78 */
5639     { Bad_Opcode },
5640     { Bad_Opcode },
5641     { Bad_Opcode },
5642     { Bad_Opcode },
5643     { Bad_Opcode },
5644     { Bad_Opcode },
5645     { Bad_Opcode },
5646     { Bad_Opcode },
5647     /* 80 */
5648     { Bad_Opcode },
5649     { Bad_Opcode },
5650     { Bad_Opcode },
5651     { Bad_Opcode },
5652     { Bad_Opcode },
5653     { Bad_Opcode },
5654     { Bad_Opcode },
5655     { Bad_Opcode },
5656     /* 88 */
5657     { Bad_Opcode },
5658     { Bad_Opcode },
5659     { Bad_Opcode },
5660     { Bad_Opcode },
5661     { Bad_Opcode },
5662     { Bad_Opcode },
5663     { Bad_Opcode },
5664     { Bad_Opcode },
5665     /* 90 */
5666     { Bad_Opcode },
5667     { Bad_Opcode },
5668     { Bad_Opcode },
5669     { Bad_Opcode },
5670     { Bad_Opcode },
5671     { Bad_Opcode },
5672     { Bad_Opcode },
5673     { Bad_Opcode },
5674     /* 98 */
5675     { Bad_Opcode },
5676     { Bad_Opcode },
5677     { Bad_Opcode },
5678     { Bad_Opcode },
5679     { Bad_Opcode },
5680     { Bad_Opcode },
5681     { Bad_Opcode },
5682     { Bad_Opcode },
5683     /* a0 */
5684     { Bad_Opcode },
5685     { Bad_Opcode },
5686     { Bad_Opcode },
5687     { Bad_Opcode },
5688     { Bad_Opcode },
5689     { Bad_Opcode },
5690     { Bad_Opcode },
5691     { Bad_Opcode },
5692     /* a8 */
5693     { Bad_Opcode },
5694     { Bad_Opcode },
5695     { Bad_Opcode },
5696     { Bad_Opcode },
5697     { Bad_Opcode },
5698     { Bad_Opcode },
5699     { Bad_Opcode },
5700     { Bad_Opcode },
5701     /* b0 */
5702     { Bad_Opcode },
5703     { Bad_Opcode },
5704     { Bad_Opcode },
5705     { Bad_Opcode },
5706     { Bad_Opcode },
5707     { Bad_Opcode },
5708     { Bad_Opcode },
5709     { Bad_Opcode },
5710     /* b8 */
5711     { Bad_Opcode },
5712     { Bad_Opcode },
5713     { Bad_Opcode },
5714     { Bad_Opcode },
5715     { Bad_Opcode },
5716     { Bad_Opcode },
5717     { Bad_Opcode },
5718     { Bad_Opcode },
5719     /* c0 */
5720     { Bad_Opcode },
5721     { Bad_Opcode },
5722     { Bad_Opcode },
5723     { Bad_Opcode },
5724     { Bad_Opcode },
5725     { Bad_Opcode },
5726     { Bad_Opcode },
5727     { Bad_Opcode },
5728     /* c8 */
5729     { Bad_Opcode },
5730     { Bad_Opcode },
5731     { Bad_Opcode },
5732     { Bad_Opcode },
5733     { Bad_Opcode },
5734     { Bad_Opcode },
5735     { Bad_Opcode },
5736     { Bad_Opcode },
5737     /* d0 */
5738     { Bad_Opcode },
5739     { Bad_Opcode },
5740     { Bad_Opcode },
5741     { Bad_Opcode },
5742     { Bad_Opcode },
5743     { Bad_Opcode },
5744     { Bad_Opcode },
5745     { Bad_Opcode },
5746     /* d8 */
5747     { Bad_Opcode },
5748     { Bad_Opcode },
5749     { Bad_Opcode },
5750     { Bad_Opcode },
5751     { Bad_Opcode },
5752     { Bad_Opcode },
5753     { Bad_Opcode },
5754     { Bad_Opcode },
5755     /* e0 */
5756     { Bad_Opcode },
5757     { Bad_Opcode },
5758     { Bad_Opcode },
5759     { Bad_Opcode },
5760     { Bad_Opcode },
5761     { Bad_Opcode },
5762     { Bad_Opcode },
5763     { Bad_Opcode },
5764     /* e8 */
5765     { Bad_Opcode },
5766     { Bad_Opcode },
5767     { Bad_Opcode },
5768     { Bad_Opcode },
5769     { Bad_Opcode },
5770     { Bad_Opcode },
5771     { Bad_Opcode },
5772     { Bad_Opcode },
5773     /* f0 */
5774     { Bad_Opcode },
5775     { Bad_Opcode },
5776     { Bad_Opcode },
5777     { Bad_Opcode },
5778     { Bad_Opcode },
5779     { Bad_Opcode },
5780     { Bad_Opcode },
5781     { Bad_Opcode },
5782     /* f8 */
5783     { Bad_Opcode },
5784     { Bad_Opcode },
5785     { Bad_Opcode },
5786     { Bad_Opcode },
5787     { Bad_Opcode },
5788     { Bad_Opcode },
5789     { Bad_Opcode },
5790     { Bad_Opcode },
5791   },
5792 };
5793
5794 static const struct dis386 vex_table[][256] = {
5795   /* VEX_0F */
5796   {
5797     /* 00 */
5798     { Bad_Opcode },
5799     { Bad_Opcode },
5800     { Bad_Opcode },
5801     { Bad_Opcode },
5802     { Bad_Opcode },
5803     { Bad_Opcode },
5804     { Bad_Opcode },
5805     { Bad_Opcode },
5806     /* 08 */
5807     { Bad_Opcode },
5808     { Bad_Opcode },
5809     { Bad_Opcode },
5810     { Bad_Opcode },
5811     { Bad_Opcode },
5812     { Bad_Opcode },
5813     { Bad_Opcode },
5814     { Bad_Opcode },
5815     /* 10 */
5816     { PREFIX_TABLE (PREFIX_VEX_0F10) },
5817     { PREFIX_TABLE (PREFIX_VEX_0F11) },
5818     { PREFIX_TABLE (PREFIX_VEX_0F12) },
5819     { MOD_TABLE (MOD_VEX_0F13) },
5820     { "vunpcklpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
5821     { "vunpckhpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
5822     { PREFIX_TABLE (PREFIX_VEX_0F16) },
5823     { MOD_TABLE (MOD_VEX_0F17) },
5824     /* 18 */
5825     { Bad_Opcode },
5826     { Bad_Opcode },
5827     { Bad_Opcode },
5828     { Bad_Opcode },
5829     { Bad_Opcode },
5830     { Bad_Opcode },
5831     { Bad_Opcode },
5832     { Bad_Opcode },
5833     /* 20 */
5834     { Bad_Opcode },
5835     { Bad_Opcode },
5836     { Bad_Opcode },
5837     { Bad_Opcode },
5838     { Bad_Opcode },
5839     { Bad_Opcode },
5840     { Bad_Opcode },
5841     { Bad_Opcode },
5842     /* 28 */
5843     { "vmovapX",        { XM, EXx }, PREFIX_OPCODE },
5844     { "vmovapX",        { EXxS, XM }, PREFIX_OPCODE },
5845     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
5846     { MOD_TABLE (MOD_VEX_0F2B) },
5847     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
5848     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
5849     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
5850     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
5851     /* 30 */
5852     { Bad_Opcode },
5853     { Bad_Opcode },
5854     { Bad_Opcode },
5855     { Bad_Opcode },
5856     { Bad_Opcode },
5857     { Bad_Opcode },
5858     { Bad_Opcode },
5859     { Bad_Opcode },
5860     /* 38 */
5861     { Bad_Opcode },
5862     { Bad_Opcode },
5863     { Bad_Opcode },
5864     { Bad_Opcode },
5865     { Bad_Opcode },
5866     { Bad_Opcode },
5867     { Bad_Opcode },
5868     { Bad_Opcode },
5869     /* 40 */
5870     { Bad_Opcode },
5871     { VEX_LEN_TABLE (VEX_LEN_0F41) },
5872     { VEX_LEN_TABLE (VEX_LEN_0F42) },
5873     { Bad_Opcode },
5874     { VEX_LEN_TABLE (VEX_LEN_0F44) },
5875     { VEX_LEN_TABLE (VEX_LEN_0F45) },
5876     { VEX_LEN_TABLE (VEX_LEN_0F46) },
5877     { VEX_LEN_TABLE (VEX_LEN_0F47) },
5878     /* 48 */
5879     { Bad_Opcode },
5880     { Bad_Opcode },
5881     { VEX_LEN_TABLE (VEX_LEN_0F4A) },
5882     { VEX_LEN_TABLE (VEX_LEN_0F4B) },
5883     { Bad_Opcode },
5884     { Bad_Opcode },
5885     { Bad_Opcode },
5886     { Bad_Opcode },
5887     /* 50 */
5888     { MOD_TABLE (MOD_VEX_0F50) },
5889     { PREFIX_TABLE (PREFIX_VEX_0F51) },
5890     { PREFIX_TABLE (PREFIX_VEX_0F52) },
5891     { PREFIX_TABLE (PREFIX_VEX_0F53) },
5892     { "vandpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
5893     { "vandnpX",        { XM, Vex, EXx }, PREFIX_OPCODE },
5894     { "vorpX",          { XM, Vex, EXx }, PREFIX_OPCODE },
5895     { "vxorpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
5896     /* 58 */
5897     { PREFIX_TABLE (PREFIX_VEX_0F58) },
5898     { PREFIX_TABLE (PREFIX_VEX_0F59) },
5899     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
5900     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
5901     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
5902     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
5903     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
5904     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
5905     /* 60 */
5906     { "vpunpcklbw",     { XM, Vex, EXx }, PREFIX_DATA },
5907     { "vpunpcklwd",     { XM, Vex, EXx }, PREFIX_DATA },
5908     { "vpunpckldq",     { XM, Vex, EXx }, PREFIX_DATA },
5909     { "vpacksswb",      { XM, Vex, EXx }, PREFIX_DATA },
5910     { "vpcmpgtb",       { XM, Vex, EXx }, PREFIX_DATA },
5911     { "vpcmpgtw",       { XM, Vex, EXx }, PREFIX_DATA },
5912     { "vpcmpgtd",       { XM, Vex, EXx }, PREFIX_DATA },
5913     { "vpackuswb",      { XM, Vex, EXx }, PREFIX_DATA },
5914     /* 68 */
5915     { "vpunpckhbw",     { XM, Vex, EXx }, PREFIX_DATA },
5916     { "vpunpckhwd",     { XM, Vex, EXx }, PREFIX_DATA },
5917     { "vpunpckhdq",     { XM, Vex, EXx }, PREFIX_DATA },
5918     { "vpackssdw",      { XM, Vex, EXx }, PREFIX_DATA },
5919     { "vpunpcklqdq",    { XM, Vex, EXx }, PREFIX_DATA },
5920     { "vpunpckhqdq",    { XM, Vex, EXx }, PREFIX_DATA },
5921     { VEX_LEN_TABLE (VEX_LEN_0F6E) },
5922     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
5923     /* 70 */
5924     { PREFIX_TABLE (PREFIX_VEX_0F70) },
5925     { MOD_TABLE (MOD_VEX_0F71) },
5926     { MOD_TABLE (MOD_VEX_0F72) },
5927     { MOD_TABLE (MOD_VEX_0F73) },
5928     { "vpcmpeqb",       { XM, Vex, EXx }, PREFIX_DATA },
5929     { "vpcmpeqw",       { XM, Vex, EXx }, PREFIX_DATA },
5930     { "vpcmpeqd",       { XM, Vex, EXx }, PREFIX_DATA },
5931     { VEX_LEN_TABLE (VEX_LEN_0F77) },
5932     /* 78 */
5933     { Bad_Opcode },
5934     { Bad_Opcode },
5935     { Bad_Opcode },
5936     { Bad_Opcode },
5937     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
5938     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
5939     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
5940     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
5941     /* 80 */
5942     { Bad_Opcode },
5943     { Bad_Opcode },
5944     { Bad_Opcode },
5945     { Bad_Opcode },
5946     { Bad_Opcode },
5947     { Bad_Opcode },
5948     { Bad_Opcode },
5949     { Bad_Opcode },
5950     /* 88 */
5951     { Bad_Opcode },
5952     { Bad_Opcode },
5953     { Bad_Opcode },
5954     { Bad_Opcode },
5955     { Bad_Opcode },
5956     { Bad_Opcode },
5957     { Bad_Opcode },
5958     { Bad_Opcode },
5959     /* 90 */
5960     { VEX_LEN_TABLE (VEX_LEN_0F90) },
5961     { VEX_LEN_TABLE (VEX_LEN_0F91) },
5962     { VEX_LEN_TABLE (VEX_LEN_0F92) },
5963     { VEX_LEN_TABLE (VEX_LEN_0F93) },
5964     { Bad_Opcode },
5965     { Bad_Opcode },
5966     { Bad_Opcode },
5967     { Bad_Opcode },
5968     /* 98 */
5969     { VEX_LEN_TABLE (VEX_LEN_0F98) },
5970     { VEX_LEN_TABLE (VEX_LEN_0F99) },
5971     { Bad_Opcode },
5972     { Bad_Opcode },
5973     { Bad_Opcode },
5974     { Bad_Opcode },
5975     { Bad_Opcode },
5976     { Bad_Opcode },
5977     /* a0 */
5978     { Bad_Opcode },
5979     { Bad_Opcode },
5980     { Bad_Opcode },
5981     { Bad_Opcode },
5982     { Bad_Opcode },
5983     { Bad_Opcode },
5984     { Bad_Opcode },
5985     { Bad_Opcode },
5986     /* a8 */
5987     { Bad_Opcode },
5988     { Bad_Opcode },
5989     { Bad_Opcode },
5990     { Bad_Opcode },
5991     { Bad_Opcode },
5992     { Bad_Opcode },
5993     { REG_TABLE (REG_VEX_0FAE) },
5994     { Bad_Opcode },
5995     /* b0 */
5996     { Bad_Opcode },
5997     { Bad_Opcode },
5998     { Bad_Opcode },
5999     { Bad_Opcode },
6000     { Bad_Opcode },
6001     { Bad_Opcode },
6002     { Bad_Opcode },
6003     { Bad_Opcode },
6004     /* b8 */
6005     { Bad_Opcode },
6006     { Bad_Opcode },
6007     { Bad_Opcode },
6008     { Bad_Opcode },
6009     { Bad_Opcode },
6010     { Bad_Opcode },
6011     { Bad_Opcode },
6012     { Bad_Opcode },
6013     /* c0 */
6014     { Bad_Opcode },
6015     { Bad_Opcode },
6016     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
6017     { Bad_Opcode },
6018     { VEX_LEN_TABLE (VEX_LEN_0FC4) },
6019     { VEX_LEN_TABLE (VEX_LEN_0FC5) },
6020     { "vshufpX",        { XM, Vex, EXx, Ib }, PREFIX_OPCODE },
6021     { Bad_Opcode },
6022     /* c8 */
6023     { Bad_Opcode },
6024     { Bad_Opcode },
6025     { Bad_Opcode },
6026     { Bad_Opcode },
6027     { Bad_Opcode },
6028     { Bad_Opcode },
6029     { Bad_Opcode },
6030     { Bad_Opcode },
6031     /* d0 */
6032     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
6033     { "vpsrlw",         { XM, Vex, EXxmm }, PREFIX_DATA },
6034     { "vpsrld",         { XM, Vex, EXxmm }, PREFIX_DATA },
6035     { "vpsrlq",         { XM, Vex, EXxmm }, PREFIX_DATA },
6036     { "vpaddq",         { XM, Vex, EXx }, PREFIX_DATA },
6037     { "vpmullw",        { XM, Vex, EXx }, PREFIX_DATA },
6038     { VEX_LEN_TABLE (VEX_LEN_0FD6) },
6039     { MOD_TABLE (MOD_VEX_0FD7) },
6040     /* d8 */
6041     { "vpsubusb",       { XM, Vex, EXx }, PREFIX_DATA },
6042     { "vpsubusw",       { XM, Vex, EXx }, PREFIX_DATA },
6043     { "vpminub",        { XM, Vex, EXx }, PREFIX_DATA },
6044     { "vpand",          { XM, Vex, EXx }, PREFIX_DATA },
6045     { "vpaddusb",       { XM, Vex, EXx }, PREFIX_DATA },
6046     { "vpaddusw",       { XM, Vex, EXx }, PREFIX_DATA },
6047     { "vpmaxub",        { XM, Vex, EXx }, PREFIX_DATA },
6048     { "vpandn",         { XM, Vex, EXx }, PREFIX_DATA },
6049     /* e0 */
6050     { "vpavgb",         { XM, Vex, EXx }, PREFIX_DATA },
6051     { "vpsraw",         { XM, Vex, EXxmm }, PREFIX_DATA },
6052     { "vpsrad",         { XM, Vex, EXxmm }, PREFIX_DATA },
6053     { "vpavgw",         { XM, Vex, EXx }, PREFIX_DATA },
6054     { "vpmulhuw",       { XM, Vex, EXx }, PREFIX_DATA },
6055     { "vpmulhw",        { XM, Vex, EXx }, PREFIX_DATA },
6056     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
6057     { MOD_TABLE (MOD_VEX_0FE7) },
6058     /* e8 */
6059     { "vpsubsb",        { XM, Vex, EXx }, PREFIX_DATA },
6060     { "vpsubsw",        { XM, Vex, EXx }, PREFIX_DATA },
6061     { "vpminsw",        { XM, Vex, EXx }, PREFIX_DATA },
6062     { "vpor",           { XM, Vex, EXx }, PREFIX_DATA },
6063     { "vpaddsb",        { XM, Vex, EXx }, PREFIX_DATA },
6064     { "vpaddsw",        { XM, Vex, EXx }, PREFIX_DATA },
6065     { "vpmaxsw",        { XM, Vex, EXx }, PREFIX_DATA },
6066     { "vpxor",          { XM, Vex, EXx }, PREFIX_DATA },
6067     /* f0 */
6068     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
6069     { "vpsllw",         { XM, Vex, EXxmm }, PREFIX_DATA },
6070     { "vpslld",         { XM, Vex, EXxmm }, PREFIX_DATA },
6071     { "vpsllq",         { XM, Vex, EXxmm }, PREFIX_DATA },
6072     { "vpmuludq",       { XM, Vex, EXx }, PREFIX_DATA },
6073     { "vpmaddwd",       { XM, Vex, EXx }, PREFIX_DATA },
6074     { "vpsadbw",        { XM, Vex, EXx }, PREFIX_DATA },
6075     { VEX_LEN_TABLE (VEX_LEN_0FF7) },
6076     /* f8 */
6077     { "vpsubb",         { XM, Vex, EXx }, PREFIX_DATA },
6078     { "vpsubw",         { XM, Vex, EXx }, PREFIX_DATA },
6079     { "vpsubd",         { XM, Vex, EXx }, PREFIX_DATA },
6080     { "vpsubq",         { XM, Vex, EXx }, PREFIX_DATA },
6081     { "vpaddb",         { XM, Vex, EXx }, PREFIX_DATA },
6082     { "vpaddw",         { XM, Vex, EXx }, PREFIX_DATA },
6083     { "vpaddd",         { XM, Vex, EXx }, PREFIX_DATA },
6084     { Bad_Opcode },
6085   },
6086   /* VEX_0F38 */
6087   {
6088     /* 00 */
6089     { "vpshufb",        { XM, Vex, EXx }, PREFIX_DATA },
6090     { "vphaddw",        { XM, Vex, EXx }, PREFIX_DATA },
6091     { "vphaddd",        { XM, Vex, EXx }, PREFIX_DATA },
6092     { "vphaddsw",       { XM, Vex, EXx }, PREFIX_DATA },
6093     { "vpmaddubsw",     { XM, Vex, EXx }, PREFIX_DATA },
6094     { "vphsubw",        { XM, Vex, EXx }, PREFIX_DATA },
6095     { "vphsubd",        { XM, Vex, EXx }, PREFIX_DATA },
6096     { "vphsubsw",       { XM, Vex, EXx }, PREFIX_DATA },
6097     /* 08 */
6098     { "vpsignb",        { XM, Vex, EXx }, PREFIX_DATA },
6099     { "vpsignw",        { XM, Vex, EXx }, PREFIX_DATA },
6100     { "vpsignd",        { XM, Vex, EXx }, PREFIX_DATA },
6101     { "vpmulhrsw",      { XM, Vex, EXx }, PREFIX_DATA },
6102     { VEX_W_TABLE (VEX_W_0F380C) },
6103     { VEX_W_TABLE (VEX_W_0F380D) },
6104     { VEX_W_TABLE (VEX_W_0F380E) },
6105     { VEX_W_TABLE (VEX_W_0F380F) },
6106     /* 10 */
6107     { Bad_Opcode },
6108     { Bad_Opcode },
6109     { Bad_Opcode },
6110     { VEX_W_TABLE (VEX_W_0F3813) },
6111     { Bad_Opcode },
6112     { Bad_Opcode },
6113     { VEX_LEN_TABLE (VEX_LEN_0F3816) },
6114     { "vptest",         { XM, EXx }, PREFIX_DATA },
6115     /* 18 */
6116     { VEX_W_TABLE (VEX_W_0F3818) },
6117     { VEX_LEN_TABLE (VEX_LEN_0F3819) },
6118     { MOD_TABLE (MOD_VEX_0F381A) },
6119     { Bad_Opcode },
6120     { "vpabsb",         { XM, EXx }, PREFIX_DATA },
6121     { "vpabsw",         { XM, EXx }, PREFIX_DATA },
6122     { "vpabsd",         { XM, EXx }, PREFIX_DATA },
6123     { Bad_Opcode },
6124     /* 20 */
6125     { "vpmovsxbw",      { XM, EXxmmq }, PREFIX_DATA },
6126     { "vpmovsxbd",      { XM, EXxmmqd }, PREFIX_DATA },
6127     { "vpmovsxbq",      { XM, EXxmmdw }, PREFIX_DATA },
6128     { "vpmovsxwd",      { XM, EXxmmq }, PREFIX_DATA },
6129     { "vpmovsxwq",      { XM, EXxmmqd }, PREFIX_DATA },
6130     { "vpmovsxdq",      { XM, EXxmmq }, PREFIX_DATA },
6131     { Bad_Opcode },
6132     { Bad_Opcode },
6133     /* 28 */
6134     { "vpmuldq",        { XM, Vex, EXx }, PREFIX_DATA },
6135     { "vpcmpeqq",       { XM, Vex, EXx }, PREFIX_DATA },
6136     { MOD_TABLE (MOD_VEX_0F382A) },
6137     { "vpackusdw",      { XM, Vex, EXx }, PREFIX_DATA },
6138     { MOD_TABLE (MOD_VEX_0F382C) },
6139     { MOD_TABLE (MOD_VEX_0F382D) },
6140     { MOD_TABLE (MOD_VEX_0F382E) },
6141     { MOD_TABLE (MOD_VEX_0F382F) },
6142     /* 30 */
6143     { "vpmovzxbw",      { XM, EXxmmq }, PREFIX_DATA },
6144     { "vpmovzxbd",      { XM, EXxmmqd }, PREFIX_DATA },
6145     { "vpmovzxbq",      { XM, EXxmmdw }, PREFIX_DATA },
6146     { "vpmovzxwd",      { XM, EXxmmq }, PREFIX_DATA },
6147     { "vpmovzxwq",      { XM, EXxmmqd }, PREFIX_DATA },
6148     { "vpmovzxdq",      { XM, EXxmmq }, PREFIX_DATA },
6149     { VEX_LEN_TABLE (VEX_LEN_0F3836) },
6150     { "vpcmpgtq",       { XM, Vex, EXx }, PREFIX_DATA },
6151     /* 38 */
6152     { "vpminsb",        { XM, Vex, EXx }, PREFIX_DATA },
6153     { "vpminsd",        { XM, Vex, EXx }, PREFIX_DATA },
6154     { "vpminuw",        { XM, Vex, EXx }, PREFIX_DATA },
6155     { "vpminud",        { XM, Vex, EXx }, PREFIX_DATA },
6156     { "vpmaxsb",        { XM, Vex, EXx }, PREFIX_DATA },
6157     { "vpmaxsd",        { XM, Vex, EXx }, PREFIX_DATA },
6158     { "vpmaxuw",        { XM, Vex, EXx }, PREFIX_DATA },
6159     { "vpmaxud",        { XM, Vex, EXx }, PREFIX_DATA },
6160     /* 40 */
6161     { "vpmulld",        { XM, Vex, EXx }, PREFIX_DATA },
6162     { VEX_LEN_TABLE (VEX_LEN_0F3841) },
6163     { Bad_Opcode },
6164     { Bad_Opcode },
6165     { Bad_Opcode },
6166     { "vpsrlv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6167     { VEX_W_TABLE (VEX_W_0F3846) },
6168     { "vpsllv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6169     /* 48 */
6170     { Bad_Opcode },
6171     { X86_64_TABLE (X86_64_VEX_0F3849) },
6172     { Bad_Opcode },
6173     { X86_64_TABLE (X86_64_VEX_0F384B) },
6174     { Bad_Opcode },
6175     { Bad_Opcode },
6176     { Bad_Opcode },
6177     { Bad_Opcode },
6178     /* 50 */
6179     { VEX_W_TABLE (VEX_W_0F3850) },
6180     { VEX_W_TABLE (VEX_W_0F3851) },
6181     { VEX_W_TABLE (VEX_W_0F3852) },
6182     { VEX_W_TABLE (VEX_W_0F3853) },
6183     { Bad_Opcode },
6184     { Bad_Opcode },
6185     { Bad_Opcode },
6186     { Bad_Opcode },
6187     /* 58 */
6188     { VEX_W_TABLE (VEX_W_0F3858) },
6189     { VEX_W_TABLE (VEX_W_0F3859) },
6190     { MOD_TABLE (MOD_VEX_0F385A) },
6191     { Bad_Opcode },
6192     { X86_64_TABLE (X86_64_VEX_0F385C) },
6193     { Bad_Opcode },
6194     { X86_64_TABLE (X86_64_VEX_0F385E) },
6195     { Bad_Opcode },
6196     /* 60 */
6197     { Bad_Opcode },
6198     { Bad_Opcode },
6199     { Bad_Opcode },
6200     { Bad_Opcode },
6201     { Bad_Opcode },
6202     { Bad_Opcode },
6203     { Bad_Opcode },
6204     { Bad_Opcode },
6205     /* 68 */
6206     { Bad_Opcode },
6207     { Bad_Opcode },
6208     { Bad_Opcode },
6209     { Bad_Opcode },
6210     { Bad_Opcode },
6211     { Bad_Opcode },
6212     { Bad_Opcode },
6213     { Bad_Opcode },
6214     /* 70 */
6215     { Bad_Opcode },
6216     { Bad_Opcode },
6217     { Bad_Opcode },
6218     { Bad_Opcode },
6219     { Bad_Opcode },
6220     { Bad_Opcode },
6221     { Bad_Opcode },
6222     { Bad_Opcode },
6223     /* 78 */
6224     { VEX_W_TABLE (VEX_W_0F3878) },
6225     { VEX_W_TABLE (VEX_W_0F3879) },
6226     { Bad_Opcode },
6227     { Bad_Opcode },
6228     { Bad_Opcode },
6229     { Bad_Opcode },
6230     { Bad_Opcode },
6231     { Bad_Opcode },
6232     /* 80 */
6233     { Bad_Opcode },
6234     { Bad_Opcode },
6235     { Bad_Opcode },
6236     { Bad_Opcode },
6237     { Bad_Opcode },
6238     { Bad_Opcode },
6239     { Bad_Opcode },
6240     { Bad_Opcode },
6241     /* 88 */
6242     { Bad_Opcode },
6243     { Bad_Opcode },
6244     { Bad_Opcode },
6245     { Bad_Opcode },
6246     { MOD_TABLE (MOD_VEX_0F388C) },
6247     { Bad_Opcode },
6248     { MOD_TABLE (MOD_VEX_0F388E) },
6249     { Bad_Opcode },
6250     /* 90 */
6251     { "vpgatherd%DQ", { XM, MVexVSIBDWpX, VexGatherD }, PREFIX_DATA },
6252     { "vpgatherq%DQ", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6253     { "vgatherdp%XW", { XM, MVexVSIBDWpX, VexGatherD }, PREFIX_DATA },
6254     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6255     { Bad_Opcode },
6256     { Bad_Opcode },
6257     { "vfmaddsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6258     { "vfmsubadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6259     /* 98 */
6260     { "vfmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6261     { "vfmadd132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6262     { "vfmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6263     { "vfmsub132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6264     { "vfnmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6265     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6266     { "vfnmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6267     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6268     /* a0 */
6269     { Bad_Opcode },
6270     { Bad_Opcode },
6271     { Bad_Opcode },
6272     { Bad_Opcode },
6273     { Bad_Opcode },
6274     { Bad_Opcode },
6275     { "vfmaddsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6276     { "vfmsubadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6277     /* a8 */
6278     { "vfmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6279     { "vfmadd213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6280     { "vfmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6281     { "vfmsub213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6282     { "vfnmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6283     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6284     { "vfnmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6285     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6286     /* b0 */
6287     { Bad_Opcode },
6288     { Bad_Opcode },
6289     { Bad_Opcode },
6290     { Bad_Opcode },
6291     { Bad_Opcode },
6292     { Bad_Opcode },
6293     { "vfmaddsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6294     { "vfmsubadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6295     /* b8 */
6296     { "vfmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6297     { "vfmadd231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6298     { "vfmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6299     { "vfmsub231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6300     { "vfnmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6301     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6302     { "vfnmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6303     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6304     /* c0 */
6305     { Bad_Opcode },
6306     { Bad_Opcode },
6307     { Bad_Opcode },
6308     { Bad_Opcode },
6309     { Bad_Opcode },
6310     { Bad_Opcode },
6311     { Bad_Opcode },
6312     { Bad_Opcode },
6313     /* c8 */
6314     { Bad_Opcode },
6315     { Bad_Opcode },
6316     { Bad_Opcode },
6317     { Bad_Opcode },
6318     { Bad_Opcode },
6319     { Bad_Opcode },
6320     { Bad_Opcode },
6321     { VEX_W_TABLE (VEX_W_0F38CF) },
6322     /* d0 */
6323     { Bad_Opcode },
6324     { Bad_Opcode },
6325     { Bad_Opcode },
6326     { Bad_Opcode },
6327     { Bad_Opcode },
6328     { Bad_Opcode },
6329     { Bad_Opcode },
6330     { Bad_Opcode },
6331     /* d8 */
6332     { Bad_Opcode },
6333     { Bad_Opcode },
6334     { Bad_Opcode },
6335     { VEX_LEN_TABLE (VEX_LEN_0F38DB) },
6336     { "vaesenc",        { XM, Vex, EXx }, PREFIX_DATA },
6337     { "vaesenclast",    { XM, Vex, EXx }, PREFIX_DATA },
6338     { "vaesdec",        { XM, Vex, EXx }, PREFIX_DATA },
6339     { "vaesdeclast",    { XM, Vex, EXx }, PREFIX_DATA },
6340     /* e0 */
6341     { Bad_Opcode },
6342     { Bad_Opcode },
6343     { Bad_Opcode },
6344     { Bad_Opcode },
6345     { Bad_Opcode },
6346     { Bad_Opcode },
6347     { Bad_Opcode },
6348     { Bad_Opcode },
6349     /* e8 */
6350     { Bad_Opcode },
6351     { Bad_Opcode },
6352     { Bad_Opcode },
6353     { Bad_Opcode },
6354     { Bad_Opcode },
6355     { Bad_Opcode },
6356     { Bad_Opcode },
6357     { Bad_Opcode },
6358     /* f0 */
6359     { Bad_Opcode },
6360     { Bad_Opcode },
6361     { VEX_LEN_TABLE (VEX_LEN_0F38F2) },
6362     { VEX_LEN_TABLE (VEX_LEN_0F38F3) },
6363     { Bad_Opcode },
6364     { VEX_LEN_TABLE (VEX_LEN_0F38F5) },
6365     { VEX_LEN_TABLE (VEX_LEN_0F38F6) },
6366     { VEX_LEN_TABLE (VEX_LEN_0F38F7) },
6367     /* f8 */
6368     { Bad_Opcode },
6369     { Bad_Opcode },
6370     { Bad_Opcode },
6371     { Bad_Opcode },
6372     { Bad_Opcode },
6373     { Bad_Opcode },
6374     { Bad_Opcode },
6375     { Bad_Opcode },
6376   },
6377   /* VEX_0F3A */
6378   {
6379     /* 00 */
6380     { VEX_LEN_TABLE (VEX_LEN_0F3A00) },
6381     { VEX_LEN_TABLE (VEX_LEN_0F3A01) },
6382     { VEX_W_TABLE (VEX_W_0F3A02) },
6383     { Bad_Opcode },
6384     { VEX_W_TABLE (VEX_W_0F3A04) },
6385     { VEX_W_TABLE (VEX_W_0F3A05) },
6386     { VEX_LEN_TABLE (VEX_LEN_0F3A06) },
6387     { Bad_Opcode },
6388     /* 08 */
6389     { "vroundps",       { XM, EXx, Ib }, PREFIX_DATA },
6390     { "vroundpd",       { XM, EXx, Ib }, PREFIX_DATA },
6391     { "vroundss",       { XMScalar, VexScalar, EXd, Ib }, PREFIX_DATA },
6392     { "vroundsd",       { XMScalar, VexScalar, EXq, Ib }, PREFIX_DATA },
6393     { "vblendps",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6394     { "vblendpd",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6395     { "vpblendw",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6396     { "vpalignr",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6397     /* 10 */
6398     { Bad_Opcode },
6399     { Bad_Opcode },
6400     { Bad_Opcode },
6401     { Bad_Opcode },
6402     { VEX_LEN_TABLE (VEX_LEN_0F3A14) },
6403     { VEX_LEN_TABLE (VEX_LEN_0F3A15) },
6404     { VEX_LEN_TABLE (VEX_LEN_0F3A16) },
6405     { VEX_LEN_TABLE (VEX_LEN_0F3A17) },
6406     /* 18 */
6407     { VEX_LEN_TABLE (VEX_LEN_0F3A18) },
6408     { VEX_LEN_TABLE (VEX_LEN_0F3A19) },
6409     { Bad_Opcode },
6410     { Bad_Opcode },
6411     { Bad_Opcode },
6412     { VEX_W_TABLE (VEX_W_0F3A1D) },
6413     { Bad_Opcode },
6414     { Bad_Opcode },
6415     /* 20 */
6416     { VEX_LEN_TABLE (VEX_LEN_0F3A20) },
6417     { VEX_LEN_TABLE (VEX_LEN_0F3A21) },
6418     { VEX_LEN_TABLE (VEX_LEN_0F3A22) },
6419     { Bad_Opcode },
6420     { Bad_Opcode },
6421     { Bad_Opcode },
6422     { Bad_Opcode },
6423     { Bad_Opcode },
6424     /* 28 */
6425     { Bad_Opcode },
6426     { Bad_Opcode },
6427     { Bad_Opcode },
6428     { Bad_Opcode },
6429     { Bad_Opcode },
6430     { Bad_Opcode },
6431     { Bad_Opcode },
6432     { Bad_Opcode },
6433     /* 30 */
6434     { VEX_LEN_TABLE (VEX_LEN_0F3A30) },
6435     { VEX_LEN_TABLE (VEX_LEN_0F3A31) },
6436     { VEX_LEN_TABLE (VEX_LEN_0F3A32) },
6437     { VEX_LEN_TABLE (VEX_LEN_0F3A33) },
6438     { Bad_Opcode },
6439     { Bad_Opcode },
6440     { Bad_Opcode },
6441     { Bad_Opcode },
6442     /* 38 */
6443     { VEX_LEN_TABLE (VEX_LEN_0F3A38) },
6444     { VEX_LEN_TABLE (VEX_LEN_0F3A39) },
6445     { Bad_Opcode },
6446     { Bad_Opcode },
6447     { Bad_Opcode },
6448     { Bad_Opcode },
6449     { Bad_Opcode },
6450     { Bad_Opcode },
6451     /* 40 */
6452     { "vdpps",          { XM, Vex, EXx, Ib }, PREFIX_DATA },
6453     { VEX_LEN_TABLE (VEX_LEN_0F3A41) },
6454     { "vmpsadbw",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6455     { Bad_Opcode },
6456     { "vpclmulqdq",     { XM, Vex, EXx, PCLMUL }, PREFIX_DATA },
6457     { Bad_Opcode },
6458     { VEX_LEN_TABLE (VEX_LEN_0F3A46) },
6459     { Bad_Opcode },
6460     /* 48 */
6461     { "vpermil2ps",     { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6462     { "vpermil2pd",     { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6463     { VEX_W_TABLE (VEX_W_0F3A4A) },
6464     { VEX_W_TABLE (VEX_W_0F3A4B) },
6465     { VEX_W_TABLE (VEX_W_0F3A4C) },
6466     { Bad_Opcode },
6467     { Bad_Opcode },
6468     { Bad_Opcode },
6469     /* 50 */
6470     { Bad_Opcode },
6471     { Bad_Opcode },
6472     { Bad_Opcode },
6473     { Bad_Opcode },
6474     { Bad_Opcode },
6475     { Bad_Opcode },
6476     { Bad_Opcode },
6477     { Bad_Opcode },
6478     /* 58 */
6479     { Bad_Opcode },
6480     { Bad_Opcode },
6481     { Bad_Opcode },
6482     { Bad_Opcode },
6483     { "vfmaddsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6484     { "vfmaddsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6485     { "vfmsubaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6486     { "vfmsubaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6487     /* 60 */
6488     { VEX_LEN_TABLE (VEX_LEN_0F3A60) },
6489     { VEX_LEN_TABLE (VEX_LEN_0F3A61) },
6490     { VEX_LEN_TABLE (VEX_LEN_0F3A62) },
6491     { VEX_LEN_TABLE (VEX_LEN_0F3A63) },
6492     { Bad_Opcode },
6493     { Bad_Opcode },
6494     { Bad_Opcode },
6495     { Bad_Opcode },
6496     /* 68 */
6497     { "vfmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6498     { "vfmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6499     { "vfmaddss",       { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6500     { "vfmaddsd",       { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6501     { "vfmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6502     { "vfmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6503     { "vfmsubss",       { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6504     { "vfmsubsd",       { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6505     /* 70 */
6506     { Bad_Opcode },
6507     { Bad_Opcode },
6508     { Bad_Opcode },
6509     { Bad_Opcode },
6510     { Bad_Opcode },
6511     { Bad_Opcode },
6512     { Bad_Opcode },
6513     { Bad_Opcode },
6514     /* 78 */
6515     { "vfnmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6516     { "vfnmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6517     { "vfnmaddss",      { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6518     { "vfnmaddsd",      { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6519     { "vfnmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6520     { "vfnmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6521     { "vfnmsubss",      { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6522     { "vfnmsubsd",      { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6523     /* 80 */
6524     { Bad_Opcode },
6525     { Bad_Opcode },
6526     { Bad_Opcode },
6527     { Bad_Opcode },
6528     { Bad_Opcode },
6529     { Bad_Opcode },
6530     { Bad_Opcode },
6531     { Bad_Opcode },
6532     /* 88 */
6533     { Bad_Opcode },
6534     { Bad_Opcode },
6535     { Bad_Opcode },
6536     { Bad_Opcode },
6537     { Bad_Opcode },
6538     { Bad_Opcode },
6539     { Bad_Opcode },
6540     { Bad_Opcode },
6541     /* 90 */
6542     { Bad_Opcode },
6543     { Bad_Opcode },
6544     { Bad_Opcode },
6545     { Bad_Opcode },
6546     { Bad_Opcode },
6547     { Bad_Opcode },
6548     { Bad_Opcode },
6549     { Bad_Opcode },
6550     /* 98 */
6551     { Bad_Opcode },
6552     { Bad_Opcode },
6553     { Bad_Opcode },
6554     { Bad_Opcode },
6555     { Bad_Opcode },
6556     { Bad_Opcode },
6557     { Bad_Opcode },
6558     { Bad_Opcode },
6559     /* a0 */
6560     { Bad_Opcode },
6561     { Bad_Opcode },
6562     { Bad_Opcode },
6563     { Bad_Opcode },
6564     { Bad_Opcode },
6565     { Bad_Opcode },
6566     { Bad_Opcode },
6567     { Bad_Opcode },
6568     /* a8 */
6569     { Bad_Opcode },
6570     { Bad_Opcode },
6571     { Bad_Opcode },
6572     { Bad_Opcode },
6573     { Bad_Opcode },
6574     { Bad_Opcode },
6575     { Bad_Opcode },
6576     { Bad_Opcode },
6577     /* b0 */
6578     { Bad_Opcode },
6579     { Bad_Opcode },
6580     { Bad_Opcode },
6581     { Bad_Opcode },
6582     { Bad_Opcode },
6583     { Bad_Opcode },
6584     { Bad_Opcode },
6585     { Bad_Opcode },
6586     /* b8 */
6587     { Bad_Opcode },
6588     { Bad_Opcode },
6589     { Bad_Opcode },
6590     { Bad_Opcode },
6591     { Bad_Opcode },
6592     { Bad_Opcode },
6593     { Bad_Opcode },
6594     { Bad_Opcode },
6595     /* c0 */
6596     { Bad_Opcode },
6597     { Bad_Opcode },
6598     { Bad_Opcode },
6599     { Bad_Opcode },
6600     { Bad_Opcode },
6601     { Bad_Opcode },
6602     { Bad_Opcode },
6603     { Bad_Opcode },
6604     /* c8 */
6605     { Bad_Opcode },
6606     { Bad_Opcode },
6607     { Bad_Opcode },
6608     { Bad_Opcode },
6609     { Bad_Opcode },
6610     { Bad_Opcode },
6611     { VEX_W_TABLE (VEX_W_0F3ACE) },
6612     { VEX_W_TABLE (VEX_W_0F3ACF) },
6613     /* d0 */
6614     { Bad_Opcode },
6615     { Bad_Opcode },
6616     { Bad_Opcode },
6617     { Bad_Opcode },
6618     { Bad_Opcode },
6619     { Bad_Opcode },
6620     { Bad_Opcode },
6621     { Bad_Opcode },
6622     /* d8 */
6623     { Bad_Opcode },
6624     { Bad_Opcode },
6625     { Bad_Opcode },
6626     { Bad_Opcode },
6627     { Bad_Opcode },
6628     { Bad_Opcode },
6629     { Bad_Opcode },
6630     { VEX_LEN_TABLE (VEX_LEN_0F3ADF) },
6631     /* e0 */
6632     { Bad_Opcode },
6633     { Bad_Opcode },
6634     { Bad_Opcode },
6635     { Bad_Opcode },
6636     { Bad_Opcode },
6637     { Bad_Opcode },
6638     { Bad_Opcode },
6639     { Bad_Opcode },
6640     /* e8 */
6641     { Bad_Opcode },
6642     { Bad_Opcode },
6643     { Bad_Opcode },
6644     { Bad_Opcode },
6645     { Bad_Opcode },
6646     { Bad_Opcode },
6647     { Bad_Opcode },
6648     { Bad_Opcode },
6649     /* f0 */
6650     { VEX_LEN_TABLE (VEX_LEN_0F3AF0) },
6651     { Bad_Opcode },
6652     { Bad_Opcode },
6653     { Bad_Opcode },
6654     { Bad_Opcode },
6655     { Bad_Opcode },
6656     { Bad_Opcode },
6657     { Bad_Opcode },
6658     /* f8 */
6659     { Bad_Opcode },
6660     { Bad_Opcode },
6661     { Bad_Opcode },
6662     { Bad_Opcode },
6663     { Bad_Opcode },
6664     { Bad_Opcode },
6665     { Bad_Opcode },
6666     { Bad_Opcode },
6667   },
6668 };
6669
6670 #include "i386-dis-evex.h"
6671
6672 static const struct dis386 vex_len_table[][2] = {
6673   /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */
6674   {
6675     { "vmovlpX",        { XM, Vex, EXq }, PREFIX_OPCODE },
6676   },
6677
6678   /* VEX_LEN_0F12_P_0_M_1 */
6679   {
6680     { "vmovhlp%XS",     { XM, Vex, EXq }, 0 },
6681   },
6682
6683   /* VEX_LEN_0F13_M_0 */
6684   {
6685     { "vmovlpX",        { EXq, XM }, PREFIX_OPCODE },
6686   },
6687
6688   /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */
6689   {
6690     { "vmovhpX",        { XM, Vex, EXq }, PREFIX_OPCODE },
6691   },
6692
6693   /* VEX_LEN_0F16_P_0_M_1 */
6694   {
6695     { "vmovlhp%XS",     { XM, Vex, EXq }, 0 },
6696   },
6697
6698   /* VEX_LEN_0F17_M_0 */
6699   {
6700     { "vmovhpX",        { EXq, XM }, PREFIX_OPCODE },
6701   },
6702
6703   /* VEX_LEN_0F41 */
6704   {
6705     { Bad_Opcode },
6706     { MOD_TABLE (MOD_VEX_0F41_L_1) },
6707   },
6708
6709   /* VEX_LEN_0F42 */
6710   {
6711     { Bad_Opcode },
6712     { MOD_TABLE (MOD_VEX_0F42_L_1) },
6713   },
6714
6715   /* VEX_LEN_0F44 */
6716   {
6717     { MOD_TABLE (MOD_VEX_0F44_L_0) },
6718   },
6719
6720   /* VEX_LEN_0F45 */
6721   {
6722     { Bad_Opcode },
6723     { MOD_TABLE (MOD_VEX_0F45_L_1) },
6724   },
6725
6726   /* VEX_LEN_0F46 */
6727   {
6728     { Bad_Opcode },
6729     { MOD_TABLE (MOD_VEX_0F46_L_1) },
6730   },
6731
6732   /* VEX_LEN_0F47 */
6733   {
6734     { Bad_Opcode },
6735     { MOD_TABLE (MOD_VEX_0F47_L_1) },
6736   },
6737
6738   /* VEX_LEN_0F4A */
6739   {
6740     { Bad_Opcode },
6741     { MOD_TABLE (MOD_VEX_0F4A_L_1) },
6742   },
6743
6744   /* VEX_LEN_0F4B */
6745   {
6746     { Bad_Opcode },
6747     { MOD_TABLE (MOD_VEX_0F4B_L_1) },
6748   },
6749
6750   /* VEX_LEN_0F6E */
6751   {
6752     { "vmovK",          { XMScalar, Edq }, PREFIX_DATA },
6753   },
6754
6755   /* VEX_LEN_0F77 */
6756   {
6757     { "vzeroupper",     { XX }, 0 },
6758     { "vzeroall",       { XX }, 0 },
6759   },
6760
6761   /* VEX_LEN_0F7E_P_1 */
6762   {
6763     { "vmovq",          { XMScalar, EXq }, 0 },
6764   },
6765
6766   /* VEX_LEN_0F7E_P_2 */
6767   {
6768     { "vmovK",          { Edq, XMScalar }, 0 },
6769   },
6770
6771   /* VEX_LEN_0F90 */
6772   {
6773     { VEX_W_TABLE (VEX_W_0F90_L_0) },
6774   },
6775
6776   /* VEX_LEN_0F91 */
6777   {
6778     { MOD_TABLE (MOD_VEX_0F91_L_0) },
6779   },
6780
6781   /* VEX_LEN_0F92 */
6782   {
6783     { MOD_TABLE (MOD_VEX_0F92_L_0) },
6784   },
6785
6786   /* VEX_LEN_0F93 */
6787   {
6788     { MOD_TABLE (MOD_VEX_0F93_L_0) },
6789   },
6790
6791   /* VEX_LEN_0F98 */
6792   {
6793     { MOD_TABLE (MOD_VEX_0F98_L_0) },
6794   },
6795
6796   /* VEX_LEN_0F99 */
6797   {
6798     { MOD_TABLE (MOD_VEX_0F99_L_0) },
6799   },
6800
6801   /* VEX_LEN_0FAE_R_2_M_0 */
6802   {
6803     { "vldmxcsr",       { Md }, 0 },
6804   },
6805
6806   /* VEX_LEN_0FAE_R_3_M_0 */
6807   {
6808     { "vstmxcsr",       { Md }, 0 },
6809   },
6810
6811   /* VEX_LEN_0FC4 */
6812   {
6813     { "vpinsrw",        { XM, Vex, Edw, Ib }, PREFIX_DATA },
6814   },
6815
6816   /* VEX_LEN_0FC5 */
6817   {
6818     { "vpextrw",        { Gd, XS, Ib }, PREFIX_DATA },
6819   },
6820
6821   /* VEX_LEN_0FD6 */
6822   {
6823     { "vmovq",          { EXqS, XMScalar }, PREFIX_DATA },
6824   },
6825
6826   /* VEX_LEN_0FF7 */
6827   {
6828     { "vmaskmovdqu",    { XM, XS }, PREFIX_DATA },
6829   },
6830
6831   /* VEX_LEN_0F3816 */
6832   {
6833     { Bad_Opcode },
6834     { VEX_W_TABLE (VEX_W_0F3816_L_1) },
6835   },
6836
6837   /* VEX_LEN_0F3819 */
6838   {
6839     { Bad_Opcode },
6840     { VEX_W_TABLE (VEX_W_0F3819_L_1) },
6841   },
6842
6843   /* VEX_LEN_0F381A_M_0 */
6844   {
6845     { Bad_Opcode },
6846     { VEX_W_TABLE (VEX_W_0F381A_M_0_L_1) },
6847   },
6848
6849   /* VEX_LEN_0F3836 */
6850   {
6851     { Bad_Opcode },
6852     { VEX_W_TABLE (VEX_W_0F3836) },
6853   },
6854
6855   /* VEX_LEN_0F3841 */
6856   {
6857     { "vphminposuw",    { XM, EXx }, PREFIX_DATA },
6858   },
6859
6860    /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_0 */
6861   {
6862     { "ldtilecfg", { M }, 0 },
6863   },
6864
6865   /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0 */
6866   {
6867     { "tilerelease", { Skip_MODRM }, 0 },
6868   },
6869
6870   /* VEX_LEN_0F3849_X86_64_P_2_W_0_M_0 */
6871   {
6872     { "sttilecfg", { M }, 0 },
6873   },
6874
6875   /* VEX_LEN_0F3849_X86_64_P_3_W_0_M_0 */
6876   {
6877     { "tilezero", { TMM, Skip_MODRM }, 0 },
6878   },
6879
6880   /* VEX_LEN_0F384B_X86_64_P_1_W_0_M_0 */
6881   {
6882     { "tilestored", { MVexSIBMEM, TMM }, 0 },
6883   },
6884   /* VEX_LEN_0F384B_X86_64_P_2_W_0_M_0 */
6885   {
6886     { "tileloaddt1", { TMM, MVexSIBMEM }, 0 },
6887   },
6888
6889   /* VEX_LEN_0F384B_X86_64_P_3_W_0_M_0 */
6890   {
6891     { "tileloadd", { TMM, MVexSIBMEM }, 0 },
6892   },
6893
6894   /* VEX_LEN_0F385A_M_0 */
6895   {
6896     { Bad_Opcode },
6897     { VEX_W_TABLE (VEX_W_0F385A_M_0_L_0) },
6898   },
6899
6900   /* VEX_LEN_0F385C_X86_64_P_1_W_0_M_0 */
6901   {
6902     { "tdpbf16ps", { TMM, EXtmm, VexTmm }, 0 },
6903   },
6904
6905   /* VEX_LEN_0F385E_X86_64_P_0_W_0_M_0 */
6906   {
6907     { "tdpbuud", {TMM, EXtmm, VexTmm }, 0 },
6908   },
6909
6910   /* VEX_LEN_0F385E_X86_64_P_1_W_0_M_0 */
6911   {
6912     { "tdpbsud", {TMM, EXtmm, VexTmm }, 0 },
6913   },
6914
6915   /* VEX_LEN_0F385E_X86_64_P_2_W_0_M_0 */
6916   {
6917     { "tdpbusd", {TMM, EXtmm, VexTmm }, 0 },
6918   },
6919
6920   /* VEX_LEN_0F385E_X86_64_P_3_W_0_M_0 */
6921   {
6922     { "tdpbssd", {TMM, EXtmm, VexTmm }, 0 },
6923   },
6924
6925   /* VEX_LEN_0F38DB */
6926   {
6927     { "vaesimc",        { XM, EXx }, PREFIX_DATA },
6928   },
6929
6930   /* VEX_LEN_0F38F2 */
6931   {
6932     { "andnS",          { Gdq, VexGdq, Edq }, PREFIX_OPCODE },
6933   },
6934
6935   /* VEX_LEN_0F38F3 */
6936   {
6937     { REG_TABLE(REG_VEX_0F38F3_L_0) },
6938   },
6939
6940   /* VEX_LEN_0F38F5 */
6941   {
6942     { PREFIX_TABLE(PREFIX_VEX_0F38F5_L_0) },
6943   },
6944
6945   /* VEX_LEN_0F38F6 */
6946   {
6947     { PREFIX_TABLE(PREFIX_VEX_0F38F6_L_0) },
6948   },
6949
6950   /* VEX_LEN_0F38F7 */
6951   {
6952     { PREFIX_TABLE(PREFIX_VEX_0F38F7_L_0) },
6953   },
6954
6955   /* VEX_LEN_0F3A00 */
6956   {
6957     { Bad_Opcode },
6958     { VEX_W_TABLE (VEX_W_0F3A00_L_1) },
6959   },
6960
6961   /* VEX_LEN_0F3A01 */
6962   {
6963     { Bad_Opcode },
6964     { VEX_W_TABLE (VEX_W_0F3A01_L_1) },
6965   },
6966
6967   /* VEX_LEN_0F3A06 */
6968   {
6969     { Bad_Opcode },
6970     { VEX_W_TABLE (VEX_W_0F3A06_L_1) },
6971   },
6972
6973   /* VEX_LEN_0F3A14 */
6974   {
6975     { "vpextrb",        { Edb, XM, Ib }, PREFIX_DATA },
6976   },
6977
6978   /* VEX_LEN_0F3A15 */
6979   {
6980     { "vpextrw",        { Edw, XM, Ib }, PREFIX_DATA },
6981   },
6982
6983   /* VEX_LEN_0F3A16  */
6984   {
6985     { "vpextrK",        { Edq, XM, Ib }, PREFIX_DATA },
6986   },
6987
6988   /* VEX_LEN_0F3A17 */
6989   {
6990     { "vextractps",     { Ed, XM, Ib }, PREFIX_DATA },
6991   },
6992
6993   /* VEX_LEN_0F3A18 */
6994   {
6995     { Bad_Opcode },
6996     { VEX_W_TABLE (VEX_W_0F3A18_L_1) },
6997   },
6998
6999   /* VEX_LEN_0F3A19 */
7000   {
7001     { Bad_Opcode },
7002     { VEX_W_TABLE (VEX_W_0F3A19_L_1) },
7003   },
7004
7005   /* VEX_LEN_0F3A20 */
7006   {
7007     { "vpinsrb",        { XM, Vex, Edb, Ib }, PREFIX_DATA },
7008   },
7009
7010   /* VEX_LEN_0F3A21 */
7011   {
7012     { "vinsertps",      { XM, Vex, EXd, Ib }, PREFIX_DATA },
7013   },
7014
7015   /* VEX_LEN_0F3A22 */
7016   {
7017     { "vpinsrK",        { XM, Vex, Edq, Ib }, PREFIX_DATA },
7018   },
7019
7020   /* VEX_LEN_0F3A30 */
7021   {
7022     { MOD_TABLE (MOD_VEX_0F3A30_L_0) },
7023   },
7024
7025   /* VEX_LEN_0F3A31 */
7026   {
7027     { MOD_TABLE (MOD_VEX_0F3A31_L_0) },
7028   },
7029
7030   /* VEX_LEN_0F3A32 */
7031   {
7032     { MOD_TABLE (MOD_VEX_0F3A32_L_0) },
7033   },
7034
7035   /* VEX_LEN_0F3A33 */
7036   {
7037     { MOD_TABLE (MOD_VEX_0F3A33_L_0) },
7038   },
7039
7040   /* VEX_LEN_0F3A38 */
7041   {
7042     { Bad_Opcode },
7043     { VEX_W_TABLE (VEX_W_0F3A38_L_1) },
7044   },
7045
7046   /* VEX_LEN_0F3A39 */
7047   {
7048     { Bad_Opcode },
7049     { VEX_W_TABLE (VEX_W_0F3A39_L_1) },
7050   },
7051
7052   /* VEX_LEN_0F3A41 */
7053   {
7054     { "vdppd",          { XM, Vex, EXx, Ib }, PREFIX_DATA },
7055   },
7056
7057   /* VEX_LEN_0F3A46 */
7058   {
7059     { Bad_Opcode },
7060     { VEX_W_TABLE (VEX_W_0F3A46_L_1) },
7061   },
7062
7063   /* VEX_LEN_0F3A60 */
7064   {
7065     { "vpcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7066   },
7067
7068   /* VEX_LEN_0F3A61 */
7069   {
7070     { "vpcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7071   },
7072
7073   /* VEX_LEN_0F3A62 */
7074   {
7075     { "vpcmpistrm",     { XM, EXx, Ib }, PREFIX_DATA },
7076   },
7077
7078   /* VEX_LEN_0F3A63 */
7079   {
7080     { "vpcmpistri",     { XM, EXx, Ib }, PREFIX_DATA },
7081   },
7082
7083   /* VEX_LEN_0F3ADF */
7084   {
7085     { "vaeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
7086   },
7087
7088   /* VEX_LEN_0F3AF0 */
7089   {
7090     { PREFIX_TABLE (PREFIX_VEX_0F3AF0_L_0) },
7091   },
7092
7093   /* VEX_LEN_0FXOP_08_85 */
7094   {
7095     { VEX_W_TABLE (VEX_W_0FXOP_08_85_L_0) },
7096   },
7097
7098   /* VEX_LEN_0FXOP_08_86 */
7099   {
7100     { VEX_W_TABLE (VEX_W_0FXOP_08_86_L_0) },
7101   },
7102
7103   /* VEX_LEN_0FXOP_08_87 */
7104   {
7105     { VEX_W_TABLE (VEX_W_0FXOP_08_87_L_0) },
7106   },
7107
7108   /* VEX_LEN_0FXOP_08_8E */
7109   {
7110     { VEX_W_TABLE (VEX_W_0FXOP_08_8E_L_0) },
7111   },
7112
7113   /* VEX_LEN_0FXOP_08_8F */
7114   {
7115     { VEX_W_TABLE (VEX_W_0FXOP_08_8F_L_0) },
7116   },
7117
7118   /* VEX_LEN_0FXOP_08_95 */
7119   {
7120     { VEX_W_TABLE (VEX_W_0FXOP_08_95_L_0) },
7121   },
7122
7123   /* VEX_LEN_0FXOP_08_96 */
7124   {
7125     { VEX_W_TABLE (VEX_W_0FXOP_08_96_L_0) },
7126   },
7127
7128   /* VEX_LEN_0FXOP_08_97 */
7129   {
7130     { VEX_W_TABLE (VEX_W_0FXOP_08_97_L_0) },
7131   },
7132
7133   /* VEX_LEN_0FXOP_08_9E */
7134   {
7135     { VEX_W_TABLE (VEX_W_0FXOP_08_9E_L_0) },
7136   },
7137
7138   /* VEX_LEN_0FXOP_08_9F */
7139   {
7140     { VEX_W_TABLE (VEX_W_0FXOP_08_9F_L_0) },
7141   },
7142
7143   /* VEX_LEN_0FXOP_08_A3 */
7144   {
7145     { "vpperm",         { XM, Vex, EXx, XMVexI4 }, 0 },
7146   },
7147
7148   /* VEX_LEN_0FXOP_08_A6 */
7149   {
7150     { VEX_W_TABLE (VEX_W_0FXOP_08_A6_L_0) },
7151   },
7152
7153   /* VEX_LEN_0FXOP_08_B6 */
7154   {
7155     { VEX_W_TABLE (VEX_W_0FXOP_08_B6_L_0) },
7156   },
7157
7158   /* VEX_LEN_0FXOP_08_C0 */
7159   {
7160     { VEX_W_TABLE (VEX_W_0FXOP_08_C0_L_0) },
7161   },
7162
7163   /* VEX_LEN_0FXOP_08_C1 */
7164   {
7165     { VEX_W_TABLE (VEX_W_0FXOP_08_C1_L_0) },
7166   },
7167
7168   /* VEX_LEN_0FXOP_08_C2 */
7169   {
7170     { VEX_W_TABLE (VEX_W_0FXOP_08_C2_L_0) },
7171   },
7172
7173   /* VEX_LEN_0FXOP_08_C3 */
7174   {
7175     { VEX_W_TABLE (VEX_W_0FXOP_08_C3_L_0) },
7176   },
7177
7178   /* VEX_LEN_0FXOP_08_CC */
7179   {
7180     { VEX_W_TABLE (VEX_W_0FXOP_08_CC_L_0) },
7181   },
7182
7183   /* VEX_LEN_0FXOP_08_CD */
7184   {
7185     { VEX_W_TABLE (VEX_W_0FXOP_08_CD_L_0) },
7186   },
7187
7188   /* VEX_LEN_0FXOP_08_CE */
7189   {
7190     { VEX_W_TABLE (VEX_W_0FXOP_08_CE_L_0) },
7191   },
7192
7193   /* VEX_LEN_0FXOP_08_CF */
7194   {
7195     { VEX_W_TABLE (VEX_W_0FXOP_08_CF_L_0) },
7196   },
7197
7198   /* VEX_LEN_0FXOP_08_EC */
7199   {
7200     { VEX_W_TABLE (VEX_W_0FXOP_08_EC_L_0) },
7201   },
7202
7203   /* VEX_LEN_0FXOP_08_ED */
7204   {
7205     { VEX_W_TABLE (VEX_W_0FXOP_08_ED_L_0) },
7206   },
7207
7208   /* VEX_LEN_0FXOP_08_EE */
7209   {
7210     { VEX_W_TABLE (VEX_W_0FXOP_08_EE_L_0) },
7211   },
7212
7213   /* VEX_LEN_0FXOP_08_EF */
7214   {
7215     { VEX_W_TABLE (VEX_W_0FXOP_08_EF_L_0) },
7216   },
7217
7218   /* VEX_LEN_0FXOP_09_01 */
7219   {
7220     { REG_TABLE (REG_XOP_09_01_L_0) },
7221   },
7222
7223   /* VEX_LEN_0FXOP_09_02 */
7224   {
7225     { REG_TABLE (REG_XOP_09_02_L_0) },
7226   },
7227
7228   /* VEX_LEN_0FXOP_09_12_M_1 */
7229   {
7230     { REG_TABLE (REG_XOP_09_12_M_1_L_0) },
7231   },
7232
7233   /* VEX_LEN_0FXOP_09_82_W_0 */
7234   {
7235     { "vfrczss",        { XM, EXd }, 0 },
7236   },
7237
7238   /* VEX_LEN_0FXOP_09_83_W_0 */
7239   {
7240     { "vfrczsd",        { XM, EXq }, 0 },
7241   },
7242
7243   /* VEX_LEN_0FXOP_09_90 */
7244   {
7245     { "vprotb",         { XM, EXx, VexW }, 0 },
7246   },
7247
7248   /* VEX_LEN_0FXOP_09_91 */
7249   {
7250     { "vprotw",         { XM, EXx, VexW }, 0 },
7251   },
7252
7253   /* VEX_LEN_0FXOP_09_92 */
7254   {
7255     { "vprotd",         { XM, EXx, VexW }, 0 },
7256   },
7257
7258   /* VEX_LEN_0FXOP_09_93 */
7259   {
7260     { "vprotq",         { XM, EXx, VexW }, 0 },
7261   },
7262
7263   /* VEX_LEN_0FXOP_09_94 */
7264   {
7265     { "vpshlb",         { XM, EXx, VexW }, 0 },
7266   },
7267
7268   /* VEX_LEN_0FXOP_09_95 */
7269   {
7270     { "vpshlw",         { XM, EXx, VexW }, 0 },
7271   },
7272
7273   /* VEX_LEN_0FXOP_09_96 */
7274   {
7275     { "vpshld",         { XM, EXx, VexW }, 0 },
7276   },
7277
7278   /* VEX_LEN_0FXOP_09_97 */
7279   {
7280     { "vpshlq",         { XM, EXx, VexW }, 0 },
7281   },
7282
7283   /* VEX_LEN_0FXOP_09_98 */
7284   {
7285     { "vpshab",         { XM, EXx, VexW }, 0 },
7286   },
7287
7288   /* VEX_LEN_0FXOP_09_99 */
7289   {
7290     { "vpshaw",         { XM, EXx, VexW }, 0 },
7291   },
7292
7293   /* VEX_LEN_0FXOP_09_9A */
7294   {
7295     { "vpshad",         { XM, EXx, VexW }, 0 },
7296   },
7297
7298   /* VEX_LEN_0FXOP_09_9B */
7299   {
7300     { "vpshaq",         { XM, EXx, VexW }, 0 },
7301   },
7302
7303   /* VEX_LEN_0FXOP_09_C1 */
7304   {
7305     { VEX_W_TABLE (VEX_W_0FXOP_09_C1_L_0) },
7306   },
7307
7308   /* VEX_LEN_0FXOP_09_C2 */
7309   {
7310     { VEX_W_TABLE (VEX_W_0FXOP_09_C2_L_0) },
7311   },
7312
7313   /* VEX_LEN_0FXOP_09_C3 */
7314   {
7315     { VEX_W_TABLE (VEX_W_0FXOP_09_C3_L_0) },
7316   },
7317
7318   /* VEX_LEN_0FXOP_09_C6 */
7319   {
7320     { VEX_W_TABLE (VEX_W_0FXOP_09_C6_L_0) },
7321   },
7322
7323   /* VEX_LEN_0FXOP_09_C7 */
7324   {
7325     { VEX_W_TABLE (VEX_W_0FXOP_09_C7_L_0) },
7326   },
7327
7328   /* VEX_LEN_0FXOP_09_CB */
7329   {
7330     { VEX_W_TABLE (VEX_W_0FXOP_09_CB_L_0) },
7331   },
7332
7333   /* VEX_LEN_0FXOP_09_D1 */
7334   {
7335     { VEX_W_TABLE (VEX_W_0FXOP_09_D1_L_0) },
7336   },
7337
7338   /* VEX_LEN_0FXOP_09_D2 */
7339   {
7340     { VEX_W_TABLE (VEX_W_0FXOP_09_D2_L_0) },
7341   },
7342
7343   /* VEX_LEN_0FXOP_09_D3 */
7344   {
7345     { VEX_W_TABLE (VEX_W_0FXOP_09_D3_L_0) },
7346   },
7347
7348   /* VEX_LEN_0FXOP_09_D6 */
7349   {
7350     { VEX_W_TABLE (VEX_W_0FXOP_09_D6_L_0) },
7351   },
7352
7353   /* VEX_LEN_0FXOP_09_D7 */
7354   {
7355     { VEX_W_TABLE (VEX_W_0FXOP_09_D7_L_0) },
7356   },
7357
7358   /* VEX_LEN_0FXOP_09_DB */
7359   {
7360     { VEX_W_TABLE (VEX_W_0FXOP_09_DB_L_0) },
7361   },
7362
7363   /* VEX_LEN_0FXOP_09_E1 */
7364   {
7365     { VEX_W_TABLE (VEX_W_0FXOP_09_E1_L_0) },
7366   },
7367
7368   /* VEX_LEN_0FXOP_09_E2 */
7369   {
7370     { VEX_W_TABLE (VEX_W_0FXOP_09_E2_L_0) },
7371   },
7372
7373   /* VEX_LEN_0FXOP_09_E3 */
7374   {
7375     { VEX_W_TABLE (VEX_W_0FXOP_09_E3_L_0) },
7376   },
7377
7378   /* VEX_LEN_0FXOP_0A_12 */
7379   {
7380     { REG_TABLE (REG_XOP_0A_12_L_0) },
7381   },
7382 };
7383
7384 #include "i386-dis-evex-len.h"
7385
7386 static const struct dis386 vex_w_table[][2] = {
7387   {
7388     /* VEX_W_0F41_L_1_M_1 */
7389     { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_M_1_W_0) },
7390     { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_M_1_W_1) },
7391   },
7392   {
7393     /* VEX_W_0F42_L_1_M_1 */
7394     { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_M_1_W_0) },
7395     { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_M_1_W_1) },
7396   },
7397   {
7398     /* VEX_W_0F44_L_0_M_1 */
7399     { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_M_1_W_0) },
7400     { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_M_1_W_1) },
7401   },
7402   {
7403     /* VEX_W_0F45_L_1_M_1 */
7404     { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_M_1_W_0) },
7405     { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_M_1_W_1) },
7406   },
7407   {
7408     /* VEX_W_0F46_L_1_M_1 */
7409     { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_M_1_W_0) },
7410     { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_M_1_W_1) },
7411   },
7412   {
7413     /* VEX_W_0F47_L_1_M_1 */
7414     { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_M_1_W_0) },
7415     { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_M_1_W_1) },
7416   },
7417   {
7418     /* VEX_W_0F4A_L_1_M_1 */
7419     { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_M_1_W_0) },
7420     { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_M_1_W_1) },
7421   },
7422   {
7423     /* VEX_W_0F4B_L_1_M_1 */
7424     { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_M_1_W_0) },
7425     { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_M_1_W_1) },
7426   },
7427   {
7428     /* VEX_W_0F90_L_0 */
7429     { PREFIX_TABLE (PREFIX_VEX_0F90_L_0_W_0) },
7430     { PREFIX_TABLE (PREFIX_VEX_0F90_L_0_W_1) },
7431   },
7432   {
7433     /* VEX_W_0F91_L_0_M_0 */
7434     { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_M_0_W_0) },
7435     { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_M_0_W_1) },
7436   },
7437   {
7438     /* VEX_W_0F92_L_0_M_1 */
7439     { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_M_1_W_0) },
7440     { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_M_1_W_1) },
7441   },
7442   {
7443     /* VEX_W_0F93_L_0_M_1 */
7444     { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_M_1_W_0) },
7445     { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_M_1_W_1) },
7446   },
7447   {
7448     /* VEX_W_0F98_L_0_M_1 */
7449     { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_M_1_W_0) },
7450     { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_M_1_W_1) },
7451   },
7452   {
7453     /* VEX_W_0F99_L_0_M_1 */
7454     { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_M_1_W_0) },
7455     { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_M_1_W_1) },
7456   },
7457   {
7458     /* VEX_W_0F380C  */
7459     { "vpermilps",      { XM, Vex, EXx }, PREFIX_DATA },
7460   },
7461   {
7462     /* VEX_W_0F380D  */
7463     { "vpermilpd",      { XM, Vex, EXx }, PREFIX_DATA },
7464   },
7465   {
7466     /* VEX_W_0F380E  */
7467     { "vtestps",        { XM, EXx }, PREFIX_DATA },
7468   },
7469   {
7470     /* VEX_W_0F380F  */
7471     { "vtestpd",        { XM, EXx }, PREFIX_DATA },
7472   },
7473   {
7474     /* VEX_W_0F3813 */
7475     { "vcvtph2ps", { XM, EXxmmq }, PREFIX_DATA },
7476   },
7477   {
7478     /* VEX_W_0F3816_L_1  */
7479     { "vpermps",        { XM, Vex, EXx }, PREFIX_DATA },
7480   },
7481   {
7482     /* VEX_W_0F3818 */
7483     { "vbroadcastss",   { XM, EXd }, PREFIX_DATA },
7484   },
7485   {
7486     /* VEX_W_0F3819_L_1 */
7487     { "vbroadcastsd",   { XM, EXq }, PREFIX_DATA },
7488   },
7489   {
7490     /* VEX_W_0F381A_M_0_L_1 */
7491     { "vbroadcastf128", { XM, Mxmm }, PREFIX_DATA },
7492   },
7493   {
7494     /* VEX_W_0F382C_M_0 */
7495     { "vmaskmovps",     { XM, Vex, Mx }, PREFIX_DATA },
7496   },
7497   {
7498     /* VEX_W_0F382D_M_0 */
7499     { "vmaskmovpd",     { XM, Vex, Mx }, PREFIX_DATA },
7500   },
7501   {
7502     /* VEX_W_0F382E_M_0 */
7503     { "vmaskmovps",     { Mx, Vex, XM }, PREFIX_DATA },
7504   },
7505   {
7506     /* VEX_W_0F382F_M_0 */
7507     { "vmaskmovpd",     { Mx, Vex, XM }, PREFIX_DATA },
7508   },
7509   {
7510     /* VEX_W_0F3836  */
7511     { "vpermd",         { XM, Vex, EXx }, PREFIX_DATA },
7512   },
7513   {
7514     /* VEX_W_0F3846 */
7515     { "vpsravd",        { XM, Vex, EXx }, PREFIX_DATA },
7516   },
7517   {
7518     /* VEX_W_0F3849_X86_64_P_0 */
7519     { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_0_W_0) },
7520   },
7521   {
7522     /* VEX_W_0F3849_X86_64_P_2 */
7523     { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_2_W_0) },
7524   },
7525   {
7526     /* VEX_W_0F3849_X86_64_P_3 */
7527     { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_3_W_0) },
7528   },
7529   {
7530     /* VEX_W_0F384B_X86_64_P_1 */
7531     { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_1_W_0) },
7532   },
7533   {
7534     /* VEX_W_0F384B_X86_64_P_2 */
7535     { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_2_W_0) },
7536   },
7537   {
7538     /* VEX_W_0F384B_X86_64_P_3 */
7539     { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_3_W_0) },
7540   },
7541   {
7542     /* VEX_W_0F3850 */
7543     { "%XV vpdpbusd",   { XM, Vex, EXx }, 0 },
7544   },
7545   {
7546     /* VEX_W_0F3851 */
7547     { "%XV vpdpbusds",  { XM, Vex, EXx }, 0 },
7548   },
7549   {
7550     /* VEX_W_0F3852 */
7551     { "%XV vpdpwssd",   { XM, Vex, EXx }, 0 },
7552   },
7553   {
7554     /* VEX_W_0F3853 */
7555     { "%XV vpdpwssds",  { XM, Vex, EXx }, 0 },
7556   },
7557   {
7558     /* VEX_W_0F3858 */
7559     { "vpbroadcastd", { XM, EXd }, PREFIX_DATA },
7560   },
7561   {
7562     /* VEX_W_0F3859 */
7563     { "vpbroadcastq", { XM, EXq }, PREFIX_DATA },
7564   },
7565   {
7566     /* VEX_W_0F385A_M_0_L_0 */
7567     { "vbroadcasti128", { XM, Mxmm }, PREFIX_DATA },
7568   },
7569   {
7570     /* VEX_W_0F385C_X86_64_P_1 */
7571     { MOD_TABLE (MOD_VEX_0F385C_X86_64_P_1_W_0) },
7572   },
7573   {
7574     /* VEX_W_0F385E_X86_64_P_0 */
7575     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_0_W_0) },
7576   },
7577   {
7578     /* VEX_W_0F385E_X86_64_P_1 */
7579     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_1_W_0) },
7580   },
7581   {
7582     /* VEX_W_0F385E_X86_64_P_2 */
7583     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_2_W_0) },
7584   },
7585   {
7586     /* VEX_W_0F385E_X86_64_P_3 */
7587     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_3_W_0) },
7588   },
7589   {
7590     /* VEX_W_0F3878 */
7591     { "vpbroadcastb",   { XM, EXb }, PREFIX_DATA },
7592   },
7593   {
7594     /* VEX_W_0F3879 */
7595     { "vpbroadcastw",   { XM, EXw }, PREFIX_DATA },
7596   },
7597   {
7598     /* VEX_W_0F38CF */
7599     { "vgf2p8mulb", { XM, Vex, EXx }, PREFIX_DATA },
7600   },
7601   {
7602     /* VEX_W_0F3A00_L_1 */
7603     { Bad_Opcode },
7604     { "vpermq",         { XM, EXx, Ib }, PREFIX_DATA },
7605   },
7606   {
7607     /* VEX_W_0F3A01_L_1 */
7608     { Bad_Opcode },
7609     { "vpermpd",        { XM, EXx, Ib }, PREFIX_DATA },
7610   },
7611   {
7612     /* VEX_W_0F3A02 */
7613     { "vpblendd",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
7614   },
7615   {
7616     /* VEX_W_0F3A04 */
7617     { "vpermilps",      { XM, EXx, Ib }, PREFIX_DATA },
7618   },
7619   {
7620     /* VEX_W_0F3A05 */
7621     { "vpermilpd",      { XM, EXx, Ib }, PREFIX_DATA },
7622   },
7623   {
7624     /* VEX_W_0F3A06_L_1 */
7625     { "vperm2f128",     { XM, Vex, EXx, Ib }, PREFIX_DATA },
7626   },
7627   {
7628     /* VEX_W_0F3A18_L_1 */
7629     { "vinsertf128",    { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7630   },
7631   {
7632     /* VEX_W_0F3A19_L_1 */
7633     { "vextractf128",   { EXxmm, XM, Ib }, PREFIX_DATA },
7634   },
7635   {
7636     /* VEX_W_0F3A1D */
7637     { "vcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, PREFIX_DATA },
7638   },
7639   {
7640     /* VEX_W_0F3A38_L_1 */
7641     { "vinserti128",    { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7642   },
7643   {
7644     /* VEX_W_0F3A39_L_1 */
7645     { "vextracti128",   { EXxmm, XM, Ib }, PREFIX_DATA },
7646   },
7647   {
7648     /* VEX_W_0F3A46_L_1 */
7649     { "vperm2i128",     { XM, Vex, EXx, Ib }, PREFIX_DATA },
7650   },
7651   {
7652     /* VEX_W_0F3A4A */
7653     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7654   },
7655   {
7656     /* VEX_W_0F3A4B */
7657     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7658   },
7659   {
7660     /* VEX_W_0F3A4C */
7661     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7662   },
7663   {
7664     /* VEX_W_0F3ACE */
7665     { Bad_Opcode },
7666     { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7667   },
7668   {
7669     /* VEX_W_0F3ACF */
7670     { Bad_Opcode },
7671     { "vgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, PREFIX_DATA },
7672   },
7673   /* VEX_W_0FXOP_08_85_L_0 */
7674   {
7675     { "vpmacssww",      { XM, Vex, EXx, XMVexI4 }, 0 },
7676   },
7677   /* VEX_W_0FXOP_08_86_L_0 */
7678   {
7679     { "vpmacsswd",      { XM, Vex, EXx, XMVexI4 }, 0 },
7680   },
7681   /* VEX_W_0FXOP_08_87_L_0 */
7682   {
7683     { "vpmacssdql",     { XM, Vex, EXx, XMVexI4 }, 0 },
7684   },
7685   /* VEX_W_0FXOP_08_8E_L_0 */
7686   {
7687     { "vpmacssdd",      { XM, Vex, EXx, XMVexI4 }, 0 },
7688   },
7689   /* VEX_W_0FXOP_08_8F_L_0 */
7690   {
7691     { "vpmacssdqh",     { XM, Vex, EXx, XMVexI4 }, 0 },
7692   },
7693   /* VEX_W_0FXOP_08_95_L_0 */
7694   {
7695     { "vpmacsww",       { XM, Vex, EXx, XMVexI4 }, 0 },
7696   },
7697   /* VEX_W_0FXOP_08_96_L_0 */
7698   {
7699     { "vpmacswd",       { XM, Vex, EXx, XMVexI4 }, 0 },
7700   },
7701   /* VEX_W_0FXOP_08_97_L_0 */
7702   {
7703     { "vpmacsdql",      { XM, Vex, EXx, XMVexI4 }, 0 },
7704   },
7705   /* VEX_W_0FXOP_08_9E_L_0 */
7706   {
7707     { "vpmacsdd",       { XM, Vex, EXx, XMVexI4 }, 0 },
7708   },
7709   /* VEX_W_0FXOP_08_9F_L_0 */
7710   {
7711     { "vpmacsdqh",      { XM, Vex, EXx, XMVexI4 }, 0 },
7712   },
7713   /* VEX_W_0FXOP_08_A6_L_0 */
7714   {
7715     { "vpmadcsswd",     { XM, Vex, EXx, XMVexI4 }, 0 },
7716   },
7717   /* VEX_W_0FXOP_08_B6_L_0 */
7718   {
7719     { "vpmadcswd",      { XM, Vex, EXx, XMVexI4 }, 0 },
7720   },
7721   /* VEX_W_0FXOP_08_C0_L_0 */
7722   {
7723     { "vprotb",         { XM, EXx, Ib }, 0 },
7724   },
7725   /* VEX_W_0FXOP_08_C1_L_0 */
7726   {
7727     { "vprotw",         { XM, EXx, Ib }, 0 },
7728   },
7729   /* VEX_W_0FXOP_08_C2_L_0 */
7730   {
7731     { "vprotd",         { XM, EXx, Ib }, 0 },
7732   },
7733   /* VEX_W_0FXOP_08_C3_L_0 */
7734   {
7735     { "vprotq",         { XM, EXx, Ib }, 0 },
7736   },
7737   /* VEX_W_0FXOP_08_CC_L_0 */
7738   {
7739      { "vpcomb",        { XM, Vex, EXx, VPCOM }, 0 },
7740   },
7741   /* VEX_W_0FXOP_08_CD_L_0 */
7742   {
7743      { "vpcomw",        { XM, Vex, EXx, VPCOM }, 0 },
7744   },
7745   /* VEX_W_0FXOP_08_CE_L_0 */
7746   {
7747      { "vpcomd",        { XM, Vex, EXx, VPCOM }, 0 },
7748   },
7749   /* VEX_W_0FXOP_08_CF_L_0 */
7750   {
7751      { "vpcomq",        { XM, Vex, EXx, VPCOM }, 0 },
7752   },
7753   /* VEX_W_0FXOP_08_EC_L_0 */
7754   {
7755      { "vpcomub",       { XM, Vex, EXx, VPCOM }, 0 },
7756   },
7757   /* VEX_W_0FXOP_08_ED_L_0 */
7758   {
7759      { "vpcomuw",       { XM, Vex, EXx, VPCOM }, 0 },
7760   },
7761   /* VEX_W_0FXOP_08_EE_L_0 */
7762   {
7763      { "vpcomud",       { XM, Vex, EXx, VPCOM }, 0 },
7764   },
7765   /* VEX_W_0FXOP_08_EF_L_0 */
7766   {
7767      { "vpcomuq",       { XM, Vex, EXx, VPCOM }, 0 },
7768   },
7769   /* VEX_W_0FXOP_09_80 */
7770   {
7771     { "vfrczps",        { XM, EXx }, 0 },
7772   },
7773   /* VEX_W_0FXOP_09_81 */
7774   {
7775     { "vfrczpd",        { XM, EXx }, 0 },
7776   },
7777   /* VEX_W_0FXOP_09_82 */
7778   {
7779     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_82_W_0) },
7780   },
7781   /* VEX_W_0FXOP_09_83 */
7782   {
7783     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_83_W_0) },
7784   },
7785   /* VEX_W_0FXOP_09_C1_L_0 */
7786   {
7787     { "vphaddbw",       { XM, EXxmm }, 0 },
7788   },
7789   /* VEX_W_0FXOP_09_C2_L_0 */
7790   {
7791     { "vphaddbd",       { XM, EXxmm }, 0 },
7792   },
7793   /* VEX_W_0FXOP_09_C3_L_0 */
7794   {
7795     { "vphaddbq",       { XM, EXxmm }, 0 },
7796   },
7797   /* VEX_W_0FXOP_09_C6_L_0 */
7798   {
7799     { "vphaddwd",       { XM, EXxmm }, 0 },
7800   },
7801   /* VEX_W_0FXOP_09_C7_L_0 */
7802   {
7803     { "vphaddwq",       { XM, EXxmm }, 0 },
7804   },
7805   /* VEX_W_0FXOP_09_CB_L_0 */
7806   {
7807     { "vphadddq",       { XM, EXxmm }, 0 },
7808   },
7809   /* VEX_W_0FXOP_09_D1_L_0 */
7810   {
7811     { "vphaddubw",      { XM, EXxmm }, 0 },
7812   },
7813   /* VEX_W_0FXOP_09_D2_L_0 */
7814   {
7815     { "vphaddubd",      { XM, EXxmm }, 0 },
7816   },
7817   /* VEX_W_0FXOP_09_D3_L_0 */
7818   {
7819     { "vphaddubq",      { XM, EXxmm }, 0 },
7820   },
7821   /* VEX_W_0FXOP_09_D6_L_0 */
7822   {
7823     { "vphadduwd",      { XM, EXxmm }, 0 },
7824   },
7825   /* VEX_W_0FXOP_09_D7_L_0 */
7826   {
7827     { "vphadduwq",      { XM, EXxmm }, 0 },
7828   },
7829   /* VEX_W_0FXOP_09_DB_L_0 */
7830   {
7831     { "vphaddudq",      { XM, EXxmm }, 0 },
7832   },
7833   /* VEX_W_0FXOP_09_E1_L_0 */
7834   {
7835     { "vphsubbw",       { XM, EXxmm }, 0 },
7836   },
7837   /* VEX_W_0FXOP_09_E2_L_0 */
7838   {
7839     { "vphsubwd",       { XM, EXxmm }, 0 },
7840   },
7841   /* VEX_W_0FXOP_09_E3_L_0 */
7842   {
7843     { "vphsubdq",       { XM, EXxmm }, 0 },
7844   },
7845
7846 #include "i386-dis-evex-w.h"
7847 };
7848
7849 static const struct dis386 mod_table[][2] = {
7850   {
7851     /* MOD_62_32BIT */
7852     { "bound{S|}",      { Gv, Ma }, 0 },
7853     { EVEX_TABLE (EVEX_0F) },
7854   },
7855   {
7856     /* MOD_8D */
7857     { "leaS",           { Gv, M }, 0 },
7858   },
7859   {
7860     /* MOD_C4_32BIT */
7861     { "lesS",           { Gv, Mp }, 0 },
7862     { VEX_C4_TABLE (VEX_0F) },
7863   },
7864   {
7865     /* MOD_C5_32BIT */
7866     { "ldsS",           { Gv, Mp }, 0 },
7867     { VEX_C5_TABLE (VEX_0F) },
7868   },
7869   {
7870     /* MOD_C6_REG_7 */
7871     { Bad_Opcode },
7872     { RM_TABLE (RM_C6_REG_7) },
7873   },
7874   {
7875     /* MOD_C7_REG_7 */
7876     { Bad_Opcode },
7877     { RM_TABLE (RM_C7_REG_7) },
7878   },
7879   {
7880     /* MOD_FF_REG_3 */
7881     { "{l|}call^", { indirEp }, 0 },
7882   },
7883   {
7884     /* MOD_FF_REG_5 */
7885     { "{l|}jmp^", { indirEp }, 0 },
7886   },
7887   {
7888     /* MOD_0F01_REG_0 */
7889     { X86_64_TABLE (X86_64_0F01_REG_0) },
7890     { RM_TABLE (RM_0F01_REG_0) },
7891   },
7892   {
7893     /* MOD_0F01_REG_1 */
7894     { X86_64_TABLE (X86_64_0F01_REG_1) },
7895     { RM_TABLE (RM_0F01_REG_1) },
7896   },
7897   {
7898     /* MOD_0F01_REG_2 */
7899     { X86_64_TABLE (X86_64_0F01_REG_2) },
7900     { RM_TABLE (RM_0F01_REG_2) },
7901   },
7902   {
7903     /* MOD_0F01_REG_3 */
7904     { X86_64_TABLE (X86_64_0F01_REG_3) },
7905     { RM_TABLE (RM_0F01_REG_3) },
7906   },
7907   {
7908     /* MOD_0F01_REG_5 */
7909     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) },
7910     { RM_TABLE (RM_0F01_REG_5_MOD_3) },
7911   },
7912   {
7913     /* MOD_0F01_REG_7 */
7914     { "invlpg",         { Mb }, 0 },
7915     { RM_TABLE (RM_0F01_REG_7_MOD_3) },
7916   },
7917   {
7918     /* MOD_0F12_PREFIX_0 */
7919     { "movlpX",         { XM, EXq }, 0 },
7920     { "movhlps",        { XM, EXq }, 0 },
7921   },
7922   {
7923     /* MOD_0F12_PREFIX_2 */
7924     { "movlpX", { XM, EXq }, 0 },
7925   },
7926   {
7927     /* MOD_0F13 */
7928     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
7929   },
7930   {
7931     /* MOD_0F16_PREFIX_0 */
7932     { "movhpX",         { XM, EXq }, 0 },
7933     { "movlhps",        { XM, EXq }, 0 },
7934   },
7935   {
7936     /* MOD_0F16_PREFIX_2 */
7937     { "movhpX", { XM, EXq }, 0 },
7938   },
7939   {
7940     /* MOD_0F17 */
7941     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
7942   },
7943   {
7944     /* MOD_0F18_REG_0 */
7945     { "prefetchnta",    { Mb }, 0 },
7946     { "nopQ",           { Ev }, 0 },
7947   },
7948   {
7949     /* MOD_0F18_REG_1 */
7950     { "prefetcht0",     { Mb }, 0 },
7951     { "nopQ",           { Ev }, 0 },
7952   },
7953   {
7954     /* MOD_0F18_REG_2 */
7955     { "prefetcht1",     { Mb }, 0 },
7956     { "nopQ",           { Ev }, 0 },
7957   },
7958   {
7959     /* MOD_0F18_REG_3 */
7960     { "prefetcht2",     { Mb }, 0 },
7961     { "nopQ",           { Ev }, 0 },
7962   },
7963   {
7964     /* MOD_0F1A_PREFIX_0 */
7965     { "bndldx",         { Gbnd, Mv_bnd }, 0 },
7966     { "nopQ",           { Ev }, 0 },
7967   },
7968   {
7969     /* MOD_0F1B_PREFIX_0 */
7970     { "bndstx",         { Mv_bnd, Gbnd }, 0 },
7971     { "nopQ",           { Ev }, 0 },
7972   },
7973   {
7974     /* MOD_0F1B_PREFIX_1 */
7975     { "bndmk",          { Gbnd, Mv_bnd }, 0 },
7976     { "nopQ",           { Ev }, PREFIX_IGNORED },
7977   },
7978   {
7979     /* MOD_0F1C_PREFIX_0 */
7980     { REG_TABLE (REG_0F1C_P_0_MOD_0) },
7981     { "nopQ",           { Ev }, 0 },
7982   },
7983   {
7984     /* MOD_0F1E_PREFIX_1 */
7985     { "nopQ",           { Ev }, PREFIX_IGNORED },
7986     { REG_TABLE (REG_0F1E_P_1_MOD_3) },
7987   },
7988   {
7989     /* MOD_0F2B_PREFIX_0 */
7990     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
7991   },
7992   {
7993     /* MOD_0F2B_PREFIX_1 */
7994     {"movntss",         { Md, XM }, PREFIX_OPCODE },
7995   },
7996   {
7997     /* MOD_0F2B_PREFIX_2 */
7998     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
7999   },
8000   {
8001     /* MOD_0F2B_PREFIX_3 */
8002     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
8003   },
8004   {
8005     /* MOD_0F50 */
8006     { Bad_Opcode },
8007     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
8008   },
8009   {
8010     /* MOD_0F71 */
8011     { Bad_Opcode },
8012     { REG_TABLE (REG_0F71_MOD_0) },
8013   },
8014   {
8015     /* MOD_0F72 */
8016     { Bad_Opcode },
8017     { REG_TABLE (REG_0F72_MOD_0) },
8018   },
8019   {
8020     /* MOD_0F73 */
8021     { Bad_Opcode },
8022     { REG_TABLE (REG_0F73_MOD_0) },
8023   },
8024   {
8025     /* MOD_0FAE_REG_0 */
8026     { "fxsave",         { FXSAVE }, 0 },
8027     { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) },
8028   },
8029   {
8030     /* MOD_0FAE_REG_1 */
8031     { "fxrstor",        { FXSAVE }, 0 },
8032     { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) },
8033   },
8034   {
8035     /* MOD_0FAE_REG_2 */
8036     { "ldmxcsr",        { Md }, 0 },
8037     { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) },
8038   },
8039   {
8040     /* MOD_0FAE_REG_3 */
8041     { "stmxcsr",        { Md }, 0 },
8042     { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) },
8043   },
8044   {
8045     /* MOD_0FAE_REG_4 */
8046     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) },
8047     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) },
8048   },
8049   {
8050     /* MOD_0FAE_REG_5 */
8051     { "xrstor",         { FXSAVE }, PREFIX_OPCODE },
8052     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) },
8053   },
8054   {
8055     /* MOD_0FAE_REG_6 */
8056     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) },
8057     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) },
8058   },
8059   {
8060     /* MOD_0FAE_REG_7 */
8061     { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) },
8062     { RM_TABLE (RM_0FAE_REG_7_MOD_3) },
8063   },
8064   {
8065     /* MOD_0FB2 */
8066     { "lssS",           { Gv, Mp }, 0 },
8067   },
8068   {
8069     /* MOD_0FB4 */
8070     { "lfsS",           { Gv, Mp }, 0 },
8071   },
8072   {
8073     /* MOD_0FB5 */
8074     { "lgsS",           { Gv, Mp }, 0 },
8075   },
8076   {
8077     /* MOD_0FC3 */
8078     { "movntiS", { Edq, Gdq }, PREFIX_OPCODE },
8079   },
8080   {
8081     /* MOD_0FC7_REG_3 */
8082     { "xrstors",        { FXSAVE }, 0 },
8083   },
8084   {
8085     /* MOD_0FC7_REG_4 */
8086     { "xsavec",         { FXSAVE }, 0 },
8087   },
8088   {
8089     /* MOD_0FC7_REG_5 */
8090     { "xsaves",         { FXSAVE }, 0 },
8091   },
8092   {
8093     /* MOD_0FC7_REG_6 */
8094     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) },
8095     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) }
8096   },
8097   {
8098     /* MOD_0FC7_REG_7 */
8099     { "vmptrst",        { Mq }, 0 },
8100     { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) }
8101   },
8102   {
8103     /* MOD_0FD7 */
8104     { Bad_Opcode },
8105     { "pmovmskb",       { Gdq, MS }, 0 },
8106   },
8107   {
8108     /* MOD_0FE7_PREFIX_2 */
8109     { "movntdq",        { Mx, XM }, 0 },
8110   },
8111   {
8112     /* MOD_0FF0_PREFIX_3 */
8113     { "lddqu",          { XM, M }, 0 },
8114   },
8115   {
8116     /* MOD_0F382A */
8117     { "movntdqa",       { XM, Mx }, PREFIX_DATA },
8118   },
8119   {
8120     /* MOD_0F38DC_PREFIX_1 */
8121     { "aesenc128kl",    { XM, M }, 0 },
8122     { "loadiwkey",      { XM, EXx }, 0 },
8123   },
8124   {
8125     /* MOD_0F38DD_PREFIX_1 */
8126     { "aesdec128kl",    { XM, M }, 0 },
8127   },
8128   {
8129     /* MOD_0F38DE_PREFIX_1 */
8130     { "aesenc256kl",    { XM, M }, 0 },
8131   },
8132   {
8133     /* MOD_0F38DF_PREFIX_1 */
8134     { "aesdec256kl",    { XM, M }, 0 },
8135   },
8136   {
8137     /* MOD_0F38F5 */
8138     { "wrussK",         { M, Gdq }, PREFIX_DATA },
8139   },
8140   {
8141     /* MOD_0F38F6_PREFIX_0 */
8142     { "wrssK",          { M, Gdq }, PREFIX_OPCODE },
8143   },
8144   {
8145     /* MOD_0F38F8_PREFIX_1 */
8146     { "enqcmds",        { Gva, M }, PREFIX_OPCODE },
8147   },
8148   {
8149     /* MOD_0F38F8_PREFIX_2 */
8150     { "movdir64b",      { Gva, M }, PREFIX_OPCODE },
8151   },
8152   {
8153     /* MOD_0F38F8_PREFIX_3 */
8154     { "enqcmd",         { Gva, M }, PREFIX_OPCODE },
8155   },
8156   {
8157     /* MOD_0F38F9 */
8158     { "movdiri",        { Edq, Gdq }, PREFIX_OPCODE },
8159   },
8160   {
8161     /* MOD_0F38FA_PREFIX_1 */
8162     { Bad_Opcode },
8163     { "encodekey128", { Gd, Ed }, 0 },
8164   },
8165   {
8166     /* MOD_0F38FB_PREFIX_1 */
8167     { Bad_Opcode },
8168     { "encodekey256", { Gd, Ed }, 0 },
8169   },
8170   {
8171     /* MOD_0F3A0F_PREFIX_1 */
8172     { Bad_Opcode },
8173     { REG_TABLE (REG_0F3A0F_PREFIX_1_MOD_3) },
8174   },
8175   {
8176     /* MOD_VEX_0F12_PREFIX_0 */
8177     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
8178     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
8179   },
8180   {
8181     /* MOD_VEX_0F12_PREFIX_2 */
8182     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0) },
8183   },
8184   {
8185     /* MOD_VEX_0F13 */
8186     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
8187   },
8188   {
8189     /* MOD_VEX_0F16_PREFIX_0 */
8190     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
8191     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
8192   },
8193   {
8194     /* MOD_VEX_0F16_PREFIX_2 */
8195     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0) },
8196   },
8197   {
8198     /* MOD_VEX_0F17 */
8199     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
8200   },
8201   {
8202     /* MOD_VEX_0F2B */
8203     { "vmovntpX",       { Mx, XM }, PREFIX_OPCODE },
8204   },
8205   {
8206     /* MOD_VEX_0F41_L_1 */
8207     { Bad_Opcode },
8208     { VEX_W_TABLE (VEX_W_0F41_L_1_M_1) },
8209   },
8210   {
8211     /* MOD_VEX_0F42_L_1 */
8212     { Bad_Opcode },
8213     { VEX_W_TABLE (VEX_W_0F42_L_1_M_1) },
8214   },
8215   {
8216     /* MOD_VEX_0F44_L_0 */
8217     { Bad_Opcode },
8218     { VEX_W_TABLE (VEX_W_0F44_L_0_M_1) },
8219   },
8220   {
8221     /* MOD_VEX_0F45_L_1 */
8222     { Bad_Opcode },
8223     { VEX_W_TABLE (VEX_W_0F45_L_1_M_1) },
8224   },
8225   {
8226     /* MOD_VEX_0F46_L_1 */
8227     { Bad_Opcode },
8228     { VEX_W_TABLE (VEX_W_0F46_L_1_M_1) },
8229   },
8230   {
8231     /* MOD_VEX_0F47_L_1 */
8232     { Bad_Opcode },
8233     { VEX_W_TABLE (VEX_W_0F47_L_1_M_1) },
8234   },
8235   {
8236     /* MOD_VEX_0F4A_L_1 */
8237     { Bad_Opcode },
8238     { VEX_W_TABLE (VEX_W_0F4A_L_1_M_1) },
8239   },
8240   {
8241     /* MOD_VEX_0F4B_L_1 */
8242     { Bad_Opcode },
8243     { VEX_W_TABLE (VEX_W_0F4B_L_1_M_1) },
8244   },
8245   {
8246     /* MOD_VEX_0F50 */
8247     { Bad_Opcode },
8248     { "vmovmskpX",      { Gdq, XS }, PREFIX_OPCODE },
8249   },
8250   {
8251     /* MOD_VEX_0F71 */
8252     { Bad_Opcode },
8253     { REG_TABLE (REG_VEX_0F71_M_0) },
8254   },
8255   {
8256     /* MOD_VEX_0F72 */
8257     { Bad_Opcode },
8258     { REG_TABLE (REG_VEX_0F72_M_0) },
8259   },
8260   {
8261     /* MOD_VEX_0F73 */
8262     { Bad_Opcode },
8263     { REG_TABLE (REG_VEX_0F73_M_0) },
8264   },
8265   {
8266     /* MOD_VEX_0F91_L_0 */
8267     { VEX_W_TABLE (VEX_W_0F91_L_0_M_0) },
8268   },
8269   {
8270     /* MOD_VEX_0F92_L_0 */
8271     { Bad_Opcode },
8272     { VEX_W_TABLE (VEX_W_0F92_L_0_M_1) },
8273   },
8274   {
8275     /* MOD_VEX_0F93_L_0 */
8276     { Bad_Opcode },
8277     { VEX_W_TABLE (VEX_W_0F93_L_0_M_1) },
8278   },
8279   {
8280     /* MOD_VEX_0F98_L_0 */
8281     { Bad_Opcode },
8282     { VEX_W_TABLE (VEX_W_0F98_L_0_M_1) },
8283   },
8284   {
8285     /* MOD_VEX_0F99_L_0 */
8286     { Bad_Opcode },
8287     { VEX_W_TABLE (VEX_W_0F99_L_0_M_1) },
8288   },
8289   {
8290     /* MOD_VEX_0FAE_REG_2 */
8291     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
8292   },
8293   {
8294     /* MOD_VEX_0FAE_REG_3 */
8295     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
8296   },
8297   {
8298     /* MOD_VEX_0FD7 */
8299     { Bad_Opcode },
8300     { "vpmovmskb",      { Gdq, XS }, PREFIX_DATA },
8301   },
8302   {
8303     /* MOD_VEX_0FE7 */
8304     { "vmovntdq",       { Mx, XM }, PREFIX_DATA },
8305   },
8306   {
8307     /* MOD_VEX_0FF0_PREFIX_3 */
8308     { "vlddqu",         { XM, M }, 0 },
8309   },
8310   {
8311     /* MOD_VEX_0F381A */
8312     { VEX_LEN_TABLE (VEX_LEN_0F381A_M_0) },
8313   },
8314   {
8315     /* MOD_VEX_0F382A */
8316     { "vmovntdqa",      { XM, Mx }, PREFIX_DATA },
8317   },
8318   {
8319     /* MOD_VEX_0F382C */
8320     { VEX_W_TABLE (VEX_W_0F382C_M_0) },
8321   },
8322   {
8323     /* MOD_VEX_0F382D */
8324     { VEX_W_TABLE (VEX_W_0F382D_M_0) },
8325   },
8326   {
8327     /* MOD_VEX_0F382E */
8328     { VEX_W_TABLE (VEX_W_0F382E_M_0) },
8329   },
8330   {
8331     /* MOD_VEX_0F382F */
8332     { VEX_W_TABLE (VEX_W_0F382F_M_0) },
8333   },
8334   {
8335     /* MOD_VEX_0F3849_X86_64_P_0_W_0 */
8336     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0) },
8337     { REG_TABLE (REG_VEX_0F3849_X86_64_P_0_W_0_M_1) },
8338   },
8339   {
8340     /* MOD_VEX_0F3849_X86_64_P_2_W_0 */
8341     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0) },
8342   },
8343   {
8344     /* MOD_VEX_0F3849_X86_64_P_3_W_0 */
8345     { Bad_Opcode },
8346     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0) },
8347   },
8348   {
8349     /* MOD_VEX_0F384B_X86_64_P_1_W_0 */
8350     { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0) },
8351   },
8352   {
8353     /* MOD_VEX_0F384B_X86_64_P_2_W_0 */
8354     { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0) },
8355   },
8356   {
8357     /* MOD_VEX_0F384B_X86_64_P_3_W_0 */
8358     { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0) },
8359   },
8360   {
8361     /* MOD_VEX_0F385A */
8362     { VEX_LEN_TABLE (VEX_LEN_0F385A_M_0) },
8363   },
8364   {
8365     /* MOD_VEX_0F385C_X86_64_P_1_W_0 */
8366     { Bad_Opcode },
8367     { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0) },
8368   },
8369   {
8370     /* MOD_VEX_0F385E_X86_64_P_0_W_0 */
8371     { Bad_Opcode },
8372     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0) },
8373   },
8374   {
8375     /* MOD_VEX_0F385E_X86_64_P_1_W_0 */
8376     { Bad_Opcode },
8377     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0) },
8378   },
8379   {
8380     /* MOD_VEX_0F385E_X86_64_P_2_W_0 */
8381     { Bad_Opcode },
8382     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0) },
8383   },
8384   {
8385     /* MOD_VEX_0F385E_X86_64_P_3_W_0 */
8386     { Bad_Opcode },
8387     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0) },
8388   },
8389   {
8390     /* MOD_VEX_0F388C */
8391     { "vpmaskmov%DQ",   { XM, Vex, Mx }, PREFIX_DATA },
8392   },
8393   {
8394     /* MOD_VEX_0F388E */
8395     { "vpmaskmov%DQ",   { Mx, Vex, XM }, PREFIX_DATA },
8396   },
8397   {
8398     /* MOD_VEX_0F3A30_L_0 */
8399     { Bad_Opcode },
8400     { "kshiftr%BW",     { MaskG, MaskE, Ib }, PREFIX_DATA },
8401   },
8402   {
8403     /* MOD_VEX_0F3A31_L_0 */
8404     { Bad_Opcode },
8405     { "kshiftr%DQ",     { MaskG, MaskE, Ib }, PREFIX_DATA },
8406   },
8407   {
8408     /* MOD_VEX_0F3A32_L_0 */
8409     { Bad_Opcode },
8410     { "kshiftl%BW",     { MaskG, MaskE, Ib }, PREFIX_DATA },
8411   },
8412   {
8413     /* MOD_VEX_0F3A33_L_0 */
8414     { Bad_Opcode },
8415     { "kshiftl%DQ",     { MaskG, MaskE, Ib }, PREFIX_DATA },
8416   },
8417   {
8418     /* MOD_XOP_09_12 */
8419     { Bad_Opcode },
8420     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_12_M_1) },
8421   },
8422
8423 #include "i386-dis-evex-mod.h"
8424 };
8425
8426 static const struct dis386 rm_table[][8] = {
8427   {
8428     /* RM_C6_REG_7 */
8429     { "xabort",         { Skip_MODRM, Ib }, 0 },
8430   },
8431   {
8432     /* RM_C7_REG_7 */
8433     { "xbeginT",        { Skip_MODRM, Jdqw }, 0 },
8434   },
8435   {
8436     /* RM_0F01_REG_0 */
8437     { "enclv",          { Skip_MODRM }, 0 },
8438     { "vmcall",         { Skip_MODRM }, 0 },
8439     { "vmlaunch",       { Skip_MODRM }, 0 },
8440     { "vmresume",       { Skip_MODRM }, 0 },
8441     { "vmxoff",         { Skip_MODRM }, 0 },
8442     { "pconfig",        { Skip_MODRM }, 0 },
8443   },
8444   {
8445     /* RM_0F01_REG_1 */
8446     { "monitor",        { { OP_Monitor, 0 } }, 0 },
8447     { "mwait",          { { OP_Mwait, 0 } }, 0 },
8448     { "clac",           { Skip_MODRM }, 0 },
8449     { "stac",           { Skip_MODRM }, 0 },
8450     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_4) },
8451     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_5) },
8452     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_6) },
8453     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_7) },
8454   },
8455   {
8456     /* RM_0F01_REG_2 */
8457     { "xgetbv",         { Skip_MODRM }, 0 },
8458     { "xsetbv",         { Skip_MODRM }, 0 },
8459     { Bad_Opcode },
8460     { Bad_Opcode },
8461     { "vmfunc",         { Skip_MODRM }, 0 },
8462     { "xend",           { Skip_MODRM }, 0 },
8463     { "xtest",          { Skip_MODRM }, 0 },
8464     { "enclu",          { Skip_MODRM }, 0 },
8465   },
8466   {
8467     /* RM_0F01_REG_3 */
8468     { "vmrun",          { Skip_MODRM }, 0 },
8469     { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) },
8470     { "vmload",         { Skip_MODRM }, 0 },
8471     { "vmsave",         { Skip_MODRM }, 0 },
8472     { "stgi",           { Skip_MODRM }, 0 },
8473     { "clgi",           { Skip_MODRM }, 0 },
8474     { "skinit",         { Skip_MODRM }, 0 },
8475     { "invlpga",        { Skip_MODRM }, 0 },
8476   },
8477   {
8478     /* RM_0F01_REG_5_MOD_3 */
8479     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) },
8480     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) },
8481     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) },
8482     { Bad_Opcode },
8483     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_4) },
8484     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_5) },
8485     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_6) },
8486     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_7) },
8487   },
8488   {
8489     /* RM_0F01_REG_7_MOD_3 */
8490     { "swapgs",         { Skip_MODRM }, 0  },
8491     { "rdtscp",         { Skip_MODRM }, 0  },
8492     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) },
8493     { "mwaitx",         { { OP_Mwait, eBX_reg } }, PREFIX_OPCODE },
8494     { "clzero",         { Skip_MODRM }, 0  },
8495     { "rdpru",          { Skip_MODRM }, 0  },
8496     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_6) },
8497     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_7) },
8498   },
8499   {
8500     /* RM_0F1E_P_1_MOD_3_REG_7 */
8501     { "nopQ",           { Ev }, PREFIX_IGNORED },
8502     { "nopQ",           { Ev }, PREFIX_IGNORED },
8503     { "endbr64",        { Skip_MODRM }, 0 },
8504     { "endbr32",        { Skip_MODRM }, 0 },
8505     { "nopQ",           { Ev }, PREFIX_IGNORED },
8506     { "nopQ",           { Ev }, PREFIX_IGNORED },
8507     { "nopQ",           { Ev }, PREFIX_IGNORED },
8508     { "nopQ",           { Ev }, PREFIX_IGNORED },
8509   },
8510   {
8511     /* RM_0FAE_REG_6_MOD_3 */
8512     { "mfence",         { Skip_MODRM }, 0 },
8513   },
8514   {
8515     /* RM_0FAE_REG_7_MOD_3 */
8516     { "sfence",         { Skip_MODRM }, 0 },
8517   },
8518   {
8519     /* RM_0F3A0F_P_1_MOD_3_REG_0 */
8520     { "hreset",         { Skip_MODRM, Ib }, 0 },
8521   },
8522   {
8523     /* RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0 */
8524     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0) },
8525   },
8526 };
8527
8528 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
8529
8530 /* We use the high bit to indicate different name for the same
8531    prefix.  */
8532 #define REP_PREFIX      (0xf3 | 0x100)
8533 #define XACQUIRE_PREFIX (0xf2 | 0x200)
8534 #define XRELEASE_PREFIX (0xf3 | 0x400)
8535 #define BND_PREFIX      (0xf2 | 0x400)
8536 #define NOTRACK_PREFIX  (0x3e | 0x100)
8537
8538 static int
8539 ckprefix (instr_info *ins)
8540 {
8541   int newrex, i, length;
8542   ins->rex = 0;
8543   ins->prefixes = 0;
8544   ins->used_prefixes = 0;
8545   ins->rex_used = 0;
8546   ins->evex_used = 0;
8547   ins->last_lock_prefix = -1;
8548   ins->last_repz_prefix = -1;
8549   ins->last_repnz_prefix = -1;
8550   ins->last_data_prefix = -1;
8551   ins->last_addr_prefix = -1;
8552   ins->last_rex_prefix = -1;
8553   ins->last_seg_prefix = -1;
8554   ins->fwait_prefix = -1;
8555   ins->active_seg_prefix = 0;
8556   for (i = 0; i < (int) ARRAY_SIZE (ins->all_prefixes); i++)
8557     ins->all_prefixes[i] = 0;
8558   i = 0;
8559   length = 0;
8560   /* The maximum instruction length is 15bytes.  */
8561   while (length < MAX_CODE_LENGTH - 1)
8562     {
8563       FETCH_DATA (ins->info, ins->codep + 1);
8564       newrex = 0;
8565       switch (*ins->codep)
8566         {
8567         /* REX prefixes family.  */
8568         case 0x40:
8569         case 0x41:
8570         case 0x42:
8571         case 0x43:
8572         case 0x44:
8573         case 0x45:
8574         case 0x46:
8575         case 0x47:
8576         case 0x48:
8577         case 0x49:
8578         case 0x4a:
8579         case 0x4b:
8580         case 0x4c:
8581         case 0x4d:
8582         case 0x4e:
8583         case 0x4f:
8584           if (ins->address_mode == mode_64bit)
8585             newrex = *ins->codep;
8586           else
8587             return 1;
8588           ins->last_rex_prefix = i;
8589           break;
8590         case 0xf3:
8591           ins->prefixes |= PREFIX_REPZ;
8592           ins->last_repz_prefix = i;
8593           break;
8594         case 0xf2:
8595           ins->prefixes |= PREFIX_REPNZ;
8596           ins->last_repnz_prefix = i;
8597           break;
8598         case 0xf0:
8599           ins->prefixes |= PREFIX_LOCK;
8600           ins->last_lock_prefix = i;
8601           break;
8602         case 0x2e:
8603           ins->prefixes |= PREFIX_CS;
8604           ins->last_seg_prefix = i;
8605           if (ins->address_mode != mode_64bit)
8606             ins->active_seg_prefix = PREFIX_CS;
8607           break;
8608         case 0x36:
8609           ins->prefixes |= PREFIX_SS;
8610           ins->last_seg_prefix = i;
8611           if (ins->address_mode != mode_64bit)
8612             ins->active_seg_prefix = PREFIX_SS;
8613           break;
8614         case 0x3e:
8615           ins->prefixes |= PREFIX_DS;
8616           ins->last_seg_prefix = i;
8617           if (ins->address_mode != mode_64bit)
8618             ins->active_seg_prefix = PREFIX_DS;
8619           break;
8620         case 0x26:
8621           ins->prefixes |= PREFIX_ES;
8622           ins->last_seg_prefix = i;
8623           if (ins->address_mode != mode_64bit)
8624             ins->active_seg_prefix = PREFIX_ES;
8625           break;
8626         case 0x64:
8627           ins->prefixes |= PREFIX_FS;
8628           ins->last_seg_prefix = i;
8629           ins->active_seg_prefix = PREFIX_FS;
8630           break;
8631         case 0x65:
8632           ins->prefixes |= PREFIX_GS;
8633           ins->last_seg_prefix = i;
8634           ins->active_seg_prefix = PREFIX_GS;
8635           break;
8636         case 0x66:
8637           ins->prefixes |= PREFIX_DATA;
8638           ins->last_data_prefix = i;
8639           break;
8640         case 0x67:
8641           ins->prefixes |= PREFIX_ADDR;
8642           ins->last_addr_prefix = i;
8643           break;
8644         case FWAIT_OPCODE:
8645           /* fwait is really an instruction.  If there are prefixes
8646              before the fwait, they belong to the fwait, *not* to the
8647              following instruction.  */
8648           ins->fwait_prefix = i;
8649           if (ins->prefixes || ins->rex)
8650             {
8651               ins->prefixes |= PREFIX_FWAIT;
8652               ins->codep++;
8653               /* This ensures that the previous REX prefixes are noticed
8654                  as unused prefixes, as in the return case below.  */
8655               ins->rex_used = ins->rex;
8656               return 1;
8657             }
8658           ins->prefixes = PREFIX_FWAIT;
8659           break;
8660         default:
8661           return 1;
8662         }
8663       /* Rex is ignored when followed by another prefix.  */
8664       if (ins->rex)
8665         {
8666           ins->rex_used = ins->rex;
8667           return 1;
8668         }
8669       if (*ins->codep != FWAIT_OPCODE)
8670         ins->all_prefixes[i++] = *ins->codep;
8671       ins->rex = newrex;
8672       ins->codep++;
8673       length++;
8674     }
8675   return 0;
8676 }
8677
8678 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
8679    prefix byte.  */
8680
8681 static const char *
8682 prefix_name (instr_info *ins, int pref, int sizeflag)
8683 {
8684   static const char *rexes [16] =
8685     {
8686       "rex",            /* 0x40 */
8687       "rex.B",          /* 0x41 */
8688       "rex.X",          /* 0x42 */
8689       "rex.XB",         /* 0x43 */
8690       "rex.R",          /* 0x44 */
8691       "rex.RB",         /* 0x45 */
8692       "rex.RX",         /* 0x46 */
8693       "rex.RXB",        /* 0x47 */
8694       "rex.W",          /* 0x48 */
8695       "rex.WB",         /* 0x49 */
8696       "rex.WX",         /* 0x4a */
8697       "rex.WXB",        /* 0x4b */
8698       "rex.WR",         /* 0x4c */
8699       "rex.WRB",        /* 0x4d */
8700       "rex.WRX",        /* 0x4e */
8701       "rex.WRXB",       /* 0x4f */
8702     };
8703
8704   switch (pref)
8705     {
8706     /* REX prefixes family.  */
8707     case 0x40:
8708     case 0x41:
8709     case 0x42:
8710     case 0x43:
8711     case 0x44:
8712     case 0x45:
8713     case 0x46:
8714     case 0x47:
8715     case 0x48:
8716     case 0x49:
8717     case 0x4a:
8718     case 0x4b:
8719     case 0x4c:
8720     case 0x4d:
8721     case 0x4e:
8722     case 0x4f:
8723       return rexes [pref - 0x40];
8724     case 0xf3:
8725       return "repz";
8726     case 0xf2:
8727       return "repnz";
8728     case 0xf0:
8729       return "lock";
8730     case 0x2e:
8731       return "cs";
8732     case 0x36:
8733       return "ss";
8734     case 0x3e:
8735       return "ds";
8736     case 0x26:
8737       return "es";
8738     case 0x64:
8739       return "fs";
8740     case 0x65:
8741       return "gs";
8742     case 0x66:
8743       return (sizeflag & DFLAG) ? "data16" : "data32";
8744     case 0x67:
8745       if (ins->address_mode == mode_64bit)
8746         return (sizeflag & AFLAG) ? "addr32" : "addr64";
8747       else
8748         return (sizeflag & AFLAG) ? "addr16" : "addr32";
8749     case FWAIT_OPCODE:
8750       return "fwait";
8751     case REP_PREFIX:
8752       return "rep";
8753     case XACQUIRE_PREFIX:
8754       return "xacquire";
8755     case XRELEASE_PREFIX:
8756       return "xrelease";
8757     case BND_PREFIX:
8758       return "bnd";
8759     case NOTRACK_PREFIX:
8760       return "notrack";
8761     default:
8762       return NULL;
8763     }
8764 }
8765
8766 /* Here for backwards compatibility.  When gdb stops using
8767    print_insn_i386_att and print_insn_i386_intel these functions can
8768    disappear, and print_insn_i386 be merged into print_insn.  */
8769 int
8770 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
8771 {
8772   instr_info ins;
8773   ins.info = info;
8774   ins.intel_syntax = 0;
8775
8776   return print_insn (pc, &ins);
8777 }
8778
8779 int
8780 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
8781 {
8782   instr_info ins;
8783   ins.info = info;
8784   ins.intel_syntax = 1;
8785
8786   return print_insn (pc, &ins);
8787 }
8788
8789 int
8790 print_insn_i386 (bfd_vma pc, disassemble_info *info)
8791 {
8792   instr_info ins;
8793   ins.info = info;
8794   ins.intel_syntax = -1;
8795
8796   return print_insn (pc, &ins);
8797 }
8798
8799 void
8800 print_i386_disassembler_options (FILE *stream)
8801 {
8802   fprintf (stream, _("\n\
8803 The following i386/x86-64 specific disassembler options are supported for use\n\
8804 with the -M switch (multiple options should be separated by commas):\n"));
8805
8806   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
8807   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
8808   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
8809   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
8810   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
8811   fprintf (stream, _("  att-mnemonic\n"
8812                      "              Display instruction in AT&T mnemonic\n"));
8813   fprintf (stream, _("  intel-mnemonic\n"
8814                      "              Display instruction in Intel mnemonic\n"));
8815   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
8816   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
8817   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
8818   fprintf (stream, _("  data32      Assume 32bit data size\n"));
8819   fprintf (stream, _("  data16      Assume 16bit data size\n"));
8820   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
8821   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
8822   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
8823 }
8824
8825 /* Bad opcode.  */
8826 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
8827
8828 /* Get a pointer to struct dis386 with a valid name.  */
8829
8830 static const struct dis386 *
8831 get_valid_dis386 (const struct dis386 *dp, instr_info *ins)
8832 {
8833   int vindex, vex_table_index;
8834
8835   if (dp->name != NULL)
8836     return dp;
8837
8838   switch (dp->op[0].bytemode)
8839     {
8840     case USE_REG_TABLE:
8841       dp = &reg_table[dp->op[1].bytemode][ins->modrm.reg];
8842       break;
8843
8844     case USE_MOD_TABLE:
8845       vindex = ins->modrm.mod == 0x3 ? 1 : 0;
8846       dp = &mod_table[dp->op[1].bytemode][vindex];
8847       break;
8848
8849     case USE_RM_TABLE:
8850       dp = &rm_table[dp->op[1].bytemode][ins->modrm.rm];
8851       break;
8852
8853     case USE_PREFIX_TABLE:
8854       if (ins->need_vex)
8855         {
8856           /* The prefix in VEX is implicit.  */
8857           switch (ins->vex.prefix)
8858             {
8859             case 0:
8860               vindex = 0;
8861               break;
8862             case REPE_PREFIX_OPCODE:
8863               vindex = 1;
8864               break;
8865             case DATA_PREFIX_OPCODE:
8866               vindex = 2;
8867               break;
8868             case REPNE_PREFIX_OPCODE:
8869               vindex = 3;
8870               break;
8871             default:
8872               abort ();
8873               break;
8874             }
8875         }
8876       else
8877         {
8878           int last_prefix = -1;
8879           int prefix = 0;
8880           vindex = 0;
8881           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
8882              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
8883              last one wins.  */
8884           if ((ins->prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
8885             {
8886               if (ins->last_repz_prefix > ins->last_repnz_prefix)
8887                 {
8888                   vindex = 1;
8889                   prefix = PREFIX_REPZ;
8890                   last_prefix = ins->last_repz_prefix;
8891                 }
8892               else
8893                 {
8894                   vindex = 3;
8895                   prefix = PREFIX_REPNZ;
8896                   last_prefix = ins->last_repnz_prefix;
8897                 }
8898
8899               /* Check if prefix should be ignored.  */
8900               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
8901                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
8902                    & prefix) != 0
8903                   && !prefix_table[dp->op[1].bytemode][vindex].name)
8904                 vindex = 0;
8905             }
8906
8907           if (vindex == 0 && (ins->prefixes & PREFIX_DATA) != 0)
8908             {
8909               vindex = 2;
8910               prefix = PREFIX_DATA;
8911               last_prefix = ins->last_data_prefix;
8912             }
8913
8914           if (vindex != 0)
8915             {
8916               ins->used_prefixes |= prefix;
8917               ins->all_prefixes[last_prefix] = 0;
8918             }
8919         }
8920       dp = &prefix_table[dp->op[1].bytemode][vindex];
8921       break;
8922
8923     case USE_X86_64_TABLE:
8924       vindex = ins->address_mode == mode_64bit ? 1 : 0;
8925       dp = &x86_64_table[dp->op[1].bytemode][vindex];
8926       break;
8927
8928     case USE_3BYTE_TABLE:
8929       FETCH_DATA (ins->info, ins->codep + 2);
8930       vindex = *ins->codep++;
8931       dp = &three_byte_table[dp->op[1].bytemode][vindex];
8932       ins->end_codep = ins->codep;
8933       ins->modrm.mod = (*ins->codep >> 6) & 3;
8934       ins->modrm.reg = (*ins->codep >> 3) & 7;
8935       ins->modrm.rm = *ins->codep & 7;
8936       break;
8937
8938     case USE_VEX_LEN_TABLE:
8939       if (!ins->need_vex)
8940         abort ();
8941
8942       switch (ins->vex.length)
8943         {
8944         case 128:
8945           vindex = 0;
8946           break;
8947         case 512:
8948           /* This allows re-using in particular table entries where only
8949              128-bit operand size (VEX.L=0 / EVEX.L'L=0) are valid.  */
8950           if (ins->vex.evex)
8951             {
8952         case 256:
8953               vindex = 1;
8954               break;
8955             }
8956         /* Fall through.  */
8957         default:
8958           abort ();
8959           break;
8960         }
8961
8962       dp = &vex_len_table[dp->op[1].bytemode][vindex];
8963       break;
8964
8965     case USE_EVEX_LEN_TABLE:
8966       if (!ins->vex.evex)
8967         abort ();
8968
8969       switch (ins->vex.length)
8970         {
8971         case 128:
8972           vindex = 0;
8973           break;
8974         case 256:
8975           vindex = 1;
8976           break;
8977         case 512:
8978           vindex = 2;
8979           break;
8980         default:
8981           abort ();
8982           break;
8983         }
8984
8985       dp = &evex_len_table[dp->op[1].bytemode][vindex];
8986       break;
8987
8988     case USE_XOP_8F_TABLE:
8989       FETCH_DATA (ins->info, ins->codep + 3);
8990       ins->rex = ~(*ins->codep >> 5) & 0x7;
8991
8992       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
8993       switch ((*ins->codep & 0x1f))
8994         {
8995         default:
8996           dp = &bad_opcode;
8997           return dp;
8998         case 0x8:
8999           vex_table_index = XOP_08;
9000           break;
9001         case 0x9:
9002           vex_table_index = XOP_09;
9003           break;
9004         case 0xa:
9005           vex_table_index = XOP_0A;
9006           break;
9007         }
9008       ins->codep++;
9009       ins->vex.w = *ins->codep & 0x80;
9010       if (ins->vex.w && ins->address_mode == mode_64bit)
9011         ins->rex |= REX_W;
9012
9013       ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
9014       if (ins->address_mode != mode_64bit)
9015         {
9016           /* In 16/32-bit mode REX_B is silently ignored.  */
9017           ins->rex &= ~REX_B;
9018         }
9019
9020       ins->vex.length = (*ins->codep & 0x4) ? 256 : 128;
9021       switch ((*ins->codep & 0x3))
9022         {
9023         case 0:
9024           break;
9025         case 1:
9026           ins->vex.prefix = DATA_PREFIX_OPCODE;
9027           break;
9028         case 2:
9029           ins->vex.prefix = REPE_PREFIX_OPCODE;
9030           break;
9031         case 3:
9032           ins->vex.prefix = REPNE_PREFIX_OPCODE;
9033           break;
9034         }
9035       ins->need_vex = true;
9036       ins->codep++;
9037       vindex = *ins->codep++;
9038       dp = &xop_table[vex_table_index][vindex];
9039
9040       ins->end_codep = ins->codep;
9041       FETCH_DATA (ins->info, ins->codep + 1);
9042       ins->modrm.mod = (*ins->codep >> 6) & 3;
9043       ins->modrm.reg = (*ins->codep >> 3) & 7;
9044       ins->modrm.rm = *ins->codep & 7;
9045
9046       /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid
9047          having to decode the bits for every otherwise valid encoding.  */
9048       if (ins->vex.prefix)
9049         return &bad_opcode;
9050       break;
9051
9052     case USE_VEX_C4_TABLE:
9053       /* VEX prefix.  */
9054       FETCH_DATA (ins->info, ins->codep + 3);
9055       ins->rex = ~(*ins->codep >> 5) & 0x7;
9056       switch ((*ins->codep & 0x1f))
9057         {
9058         default:
9059           dp = &bad_opcode;
9060           return dp;
9061         case 0x1:
9062           vex_table_index = VEX_0F;
9063           break;
9064         case 0x2:
9065           vex_table_index = VEX_0F38;
9066           break;
9067         case 0x3:
9068           vex_table_index = VEX_0F3A;
9069           break;
9070         }
9071       ins->codep++;
9072       ins->vex.w = *ins->codep & 0x80;
9073       if (ins->address_mode == mode_64bit)
9074         {
9075           if (ins->vex.w)
9076             ins->rex |= REX_W;
9077         }
9078       else
9079         {
9080           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
9081              is ignored, other REX bits are 0 and the highest bit in
9082              VEX.vvvv is also ignored (but we mustn't clear it here).  */
9083           ins->rex = 0;
9084         }
9085       ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
9086       ins->vex.length = (*ins->codep & 0x4) ? 256 : 128;
9087       switch ((*ins->codep & 0x3))
9088         {
9089         case 0:
9090           break;
9091         case 1:
9092           ins->vex.prefix = DATA_PREFIX_OPCODE;
9093           break;
9094         case 2:
9095           ins->vex.prefix = REPE_PREFIX_OPCODE;
9096           break;
9097         case 3:
9098           ins->vex.prefix = REPNE_PREFIX_OPCODE;
9099           break;
9100         }
9101       ins->need_vex = true;
9102       ins->codep++;
9103       vindex = *ins->codep++;
9104       dp = &vex_table[vex_table_index][vindex];
9105       ins->end_codep = ins->codep;
9106       /* There is no MODRM byte for VEX0F 77.  */
9107       if (vex_table_index != VEX_0F || vindex != 0x77)
9108         {
9109           FETCH_DATA (ins->info, ins->codep + 1);
9110           ins->modrm.mod = (*ins->codep >> 6) & 3;
9111           ins->modrm.reg = (*ins->codep >> 3) & 7;
9112           ins->modrm.rm = *ins->codep & 7;
9113         }
9114       break;
9115
9116     case USE_VEX_C5_TABLE:
9117       /* VEX prefix.  */
9118       FETCH_DATA (ins->info, ins->codep + 2);
9119       ins->rex = (*ins->codep & 0x80) ? 0 : REX_R;
9120
9121       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
9122          VEX.vvvv is 1.  */
9123       ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
9124       ins->vex.length = (*ins->codep & 0x4) ? 256 : 128;
9125       switch ((*ins->codep & 0x3))
9126         {
9127         case 0:
9128           break;
9129         case 1:
9130           ins->vex.prefix = DATA_PREFIX_OPCODE;
9131           break;
9132         case 2:
9133           ins->vex.prefix = REPE_PREFIX_OPCODE;
9134           break;
9135         case 3:
9136           ins->vex.prefix = REPNE_PREFIX_OPCODE;
9137           break;
9138         }
9139       ins->need_vex = true;
9140       ins->codep++;
9141       vindex = *ins->codep++;
9142       dp = &vex_table[dp->op[1].bytemode][vindex];
9143       ins->end_codep = ins->codep;
9144       /* There is no MODRM byte for VEX 77.  */
9145       if (vindex != 0x77)
9146         {
9147           FETCH_DATA (ins->info, ins->codep + 1);
9148           ins->modrm.mod = (*ins->codep >> 6) & 3;
9149           ins->modrm.reg = (*ins->codep >> 3) & 7;
9150           ins->modrm.rm = *ins->codep & 7;
9151         }
9152       break;
9153
9154     case USE_VEX_W_TABLE:
9155       if (!ins->need_vex)
9156         abort ();
9157
9158       dp = &vex_w_table[dp->op[1].bytemode][ins->vex.w];
9159       break;
9160
9161     case USE_EVEX_TABLE:
9162       ins->two_source_ops = false;
9163       /* EVEX prefix.  */
9164       ins->vex.evex = true;
9165       FETCH_DATA (ins->info, ins->codep + 4);
9166       /* The first byte after 0x62.  */
9167       ins->rex = ~(*ins->codep >> 5) & 0x7;
9168       ins->vex.r = *ins->codep & 0x10;
9169       switch ((*ins->codep & 0xf))
9170         {
9171         default:
9172           return &bad_opcode;
9173         case 0x1:
9174           vex_table_index = EVEX_0F;
9175           break;
9176         case 0x2:
9177           vex_table_index = EVEX_0F38;
9178           break;
9179         case 0x3:
9180           vex_table_index = EVEX_0F3A;
9181           break;
9182         case 0x5:
9183           vex_table_index = EVEX_MAP5;
9184           break;
9185         case 0x6:
9186           vex_table_index = EVEX_MAP6;
9187           break;
9188         }
9189
9190       /* The second byte after 0x62.  */
9191       ins->codep++;
9192       ins->vex.w = *ins->codep & 0x80;
9193       if (ins->vex.w && ins->address_mode == mode_64bit)
9194         ins->rex |= REX_W;
9195
9196       ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
9197
9198       /* The U bit.  */
9199       if (!(*ins->codep & 0x4))
9200         return &bad_opcode;
9201
9202       switch ((*ins->codep & 0x3))
9203         {
9204         case 0:
9205           break;
9206         case 1:
9207           ins->vex.prefix = DATA_PREFIX_OPCODE;
9208           break;
9209         case 2:
9210           ins->vex.prefix = REPE_PREFIX_OPCODE;
9211           break;
9212         case 3:
9213           ins->vex.prefix = REPNE_PREFIX_OPCODE;
9214           break;
9215         }
9216
9217       /* The third byte after 0x62.  */
9218       ins->codep++;
9219
9220       /* Remember the static rounding bits.  */
9221       ins->vex.ll = (*ins->codep >> 5) & 3;
9222       ins->vex.b = *ins->codep & 0x10;
9223
9224       ins->vex.v = *ins->codep & 0x8;
9225       ins->vex.mask_register_specifier = *ins->codep & 0x7;
9226       ins->vex.zeroing = *ins->codep & 0x80;
9227
9228       if (ins->address_mode != mode_64bit)
9229         {
9230           /* In 16/32-bit mode silently ignore following bits.  */
9231           ins->rex &= ~REX_B;
9232           ins->vex.r = true;
9233         }
9234
9235       ins->need_vex = true;
9236       ins->codep++;
9237       vindex = *ins->codep++;
9238       dp = &evex_table[vex_table_index][vindex];
9239       ins->end_codep = ins->codep;
9240       FETCH_DATA (ins->info, ins->codep + 1);
9241       ins->modrm.mod = (*ins->codep >> 6) & 3;
9242       ins->modrm.reg = (*ins->codep >> 3) & 7;
9243       ins->modrm.rm = *ins->codep & 7;
9244
9245       /* Set vector length.  */
9246       if (ins->modrm.mod == 3 && ins->vex.b)
9247         ins->vex.length = 512;
9248       else
9249         {
9250           switch (ins->vex.ll)
9251             {
9252             case 0x0:
9253               ins->vex.length = 128;
9254               break;
9255             case 0x1:
9256               ins->vex.length = 256;
9257               break;
9258             case 0x2:
9259               ins->vex.length = 512;
9260               break;
9261             default:
9262               return &bad_opcode;
9263             }
9264         }
9265       break;
9266
9267     case 0:
9268       dp = &bad_opcode;
9269       break;
9270
9271     default:
9272       abort ();
9273     }
9274
9275   if (dp->name != NULL)
9276     return dp;
9277   else
9278     return get_valid_dis386 (dp, ins);
9279 }
9280
9281 static void
9282 get_sib (instr_info *ins, int sizeflag)
9283 {
9284   /* If modrm.mod == 3, operand must be register.  */
9285   if (ins->need_modrm
9286       && ((sizeflag & AFLAG) || ins->address_mode == mode_64bit)
9287       && ins->modrm.mod != 3
9288       && ins->modrm.rm == 4)
9289     {
9290       FETCH_DATA (ins->info, ins->codep + 2);
9291       ins->sib.index = (ins->codep[1] >> 3) & 7;
9292       ins->sib.scale = (ins->codep[1] >> 6) & 3;
9293       ins->sib.base = ins->codep[1] & 7;
9294       ins->has_sib = true;
9295     }
9296   else
9297     ins->has_sib = false;
9298 }
9299
9300 /* Like oappend (below), but S is a string starting with '%'.
9301    In Intel syntax, the '%' is elided.  */
9302 static void
9303 oappend_maybe_intel (instr_info *ins, const char *s)
9304 {
9305   oappend (ins, s + ins->intel_syntax);
9306 }
9307
9308 static int
9309 print_insn (bfd_vma pc, instr_info *ins)
9310 {
9311   const struct dis386 *dp;
9312   int i;
9313   char *op_txt[MAX_OPERANDS];
9314   int needcomma;
9315   int sizeflag, orig_sizeflag;
9316   const char *p;
9317   struct dis_private priv;
9318   int prefix_length;
9319
9320   ins->isa64 = 0;
9321   ins->intel_mnemonic = !SYSV386_COMPAT;
9322   ins->op_is_jump = false;
9323   priv.orig_sizeflag = AFLAG | DFLAG;
9324   if ((ins->info->mach & bfd_mach_i386_i386) != 0)
9325     ins->address_mode = mode_32bit;
9326   else if (ins->info->mach == bfd_mach_i386_i8086)
9327     {
9328       ins->address_mode = mode_16bit;
9329       priv.orig_sizeflag = 0;
9330     }
9331   else
9332     ins->address_mode = mode_64bit;
9333
9334   if (ins->intel_syntax == (char) -1)
9335     ins->intel_syntax = (ins->info->mach & bfd_mach_i386_intel_syntax) != 0;
9336
9337   for (p = ins->info->disassembler_options; p != NULL;)
9338     {
9339       if (startswith (p, "amd64"))
9340         ins->isa64 = amd64;
9341       else if (startswith (p, "intel64"))
9342         ins->isa64 = intel64;
9343       else if (startswith (p, "x86-64"))
9344         {
9345           ins->address_mode = mode_64bit;
9346           priv.orig_sizeflag |= AFLAG | DFLAG;
9347         }
9348       else if (startswith (p, "i386"))
9349         {
9350           ins->address_mode = mode_32bit;
9351           priv.orig_sizeflag |= AFLAG | DFLAG;
9352         }
9353       else if (startswith (p, "i8086"))
9354         {
9355           ins->address_mode = mode_16bit;
9356           priv.orig_sizeflag &= ~(AFLAG | DFLAG);
9357         }
9358       else if (startswith (p, "intel"))
9359         {
9360           ins->intel_syntax = 1;
9361           if (startswith (p + 5, "-mnemonic"))
9362             ins->intel_mnemonic = true;
9363         }
9364       else if (startswith (p, "att"))
9365         {
9366           ins->intel_syntax = 0;
9367           if (startswith (p + 3, "-mnemonic"))
9368             ins->intel_mnemonic = false;
9369         }
9370       else if (startswith (p, "addr"))
9371         {
9372           if (ins->address_mode == mode_64bit)
9373             {
9374               if (p[4] == '3' && p[5] == '2')
9375                 priv.orig_sizeflag &= ~AFLAG;
9376               else if (p[4] == '6' && p[5] == '4')
9377                 priv.orig_sizeflag |= AFLAG;
9378             }
9379           else
9380             {
9381               if (p[4] == '1' && p[5] == '6')
9382                 priv.orig_sizeflag &= ~AFLAG;
9383               else if (p[4] == '3' && p[5] == '2')
9384                 priv.orig_sizeflag |= AFLAG;
9385             }
9386         }
9387       else if (startswith (p, "data"))
9388         {
9389           if (p[4] == '1' && p[5] == '6')
9390             priv.orig_sizeflag &= ~DFLAG;
9391           else if (p[4] == '3' && p[5] == '2')
9392             priv.orig_sizeflag |= DFLAG;
9393         }
9394       else if (startswith (p, "suffix"))
9395         priv.orig_sizeflag |= SUFFIX_ALWAYS;
9396
9397       p = strchr (p, ',');
9398       if (p != NULL)
9399         p++;
9400     }
9401
9402   if (ins->address_mode == mode_64bit && sizeof (bfd_vma) < 8)
9403     {
9404       (*ins->info->fprintf_styled_func) (ins->info->stream, dis_style_text,
9405                                          _("64-bit address is disabled"));
9406       return -1;
9407     }
9408
9409   if (ins->intel_syntax)
9410     {
9411       ins->open_char = '[';
9412       ins->close_char = ']';
9413       ins->separator_char = '+';
9414       ins->scale_char = '*';
9415     }
9416   else
9417     {
9418       ins->open_char = '(';
9419       ins->close_char =  ')';
9420       ins->separator_char = ',';
9421       ins->scale_char = ',';
9422     }
9423
9424   /* The output looks better if we put 7 bytes on a line, since that
9425      puts most long word instructions on a single line.  */
9426   ins->info->bytes_per_line = 7;
9427
9428   ins->info->private_data = &priv;
9429   priv.max_fetched = priv.the_buffer;
9430   priv.insn_start = pc;
9431
9432   ins->obuf[0] = 0;
9433   for (i = 0; i < MAX_OPERANDS; ++i)
9434     {
9435       ins->op_out[i][0] = 0;
9436       ins->op_index[i] = -1;
9437     }
9438
9439   ins->start_pc = pc;
9440   ins->start_codep = priv.the_buffer;
9441   ins->codep = priv.the_buffer;
9442
9443   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
9444     {
9445       const char *name;
9446
9447       /* Getting here means we tried for data but didn't get it.  That
9448          means we have an incomplete instruction of some sort.  Just
9449          print the first byte as a prefix or a .byte pseudo-op.  */
9450       if (ins->codep > priv.the_buffer)
9451         {
9452           name = prefix_name (ins, priv.the_buffer[0], priv.orig_sizeflag);
9453           if (name != NULL)
9454             (*ins->info->fprintf_styled_func)
9455               (ins->info->stream, dis_style_mnemonic, "%s", name);
9456           else
9457             {
9458               /* Just print the first byte as a .byte instruction.  */
9459               (*ins->info->fprintf_styled_func)
9460                 (ins->info->stream, dis_style_assembler_directive, ".byte ");
9461               (*ins->info->fprintf_styled_func)
9462                 (ins->info->stream, dis_style_immediate, "0x%x",
9463                  (unsigned int) priv.the_buffer[0]);
9464             }
9465
9466           return 1;
9467         }
9468
9469       return -1;
9470     }
9471
9472   ins->obufp = ins->obuf;
9473   sizeflag = priv.orig_sizeflag;
9474
9475   if (!ckprefix (ins) || ins->rex_used)
9476     {
9477       /* Too many ins->prefixes or unused REX ins->prefixes.  */
9478       for (i = 0;
9479            i < (int) ARRAY_SIZE (ins->all_prefixes) && ins->all_prefixes[i];
9480            i++)
9481         (*ins->info->fprintf_styled_func)
9482           (ins->info->stream, dis_style_mnemonic, "%s%s",
9483            (i == 0 ? "" : " "), prefix_name (ins, ins->all_prefixes[i],
9484                                              sizeflag));
9485       return i;
9486     }
9487
9488   ins->insn_codep = ins->codep;
9489
9490   FETCH_DATA (ins->info, ins->codep + 1);
9491   ins->two_source_ops = (*ins->codep == 0x62) || (*ins->codep == 0xc8);
9492
9493   if (((ins->prefixes & PREFIX_FWAIT)
9494        && ((*ins->codep < 0xd8) || (*ins->codep > 0xdf))))
9495     {
9496       /* Handle ins->prefixes before fwait.  */
9497       for (i = 0; i < ins->fwait_prefix && ins->all_prefixes[i];
9498            i++)
9499         (*ins->info->fprintf_styled_func)
9500           (ins->info->stream, dis_style_mnemonic, "%s ",
9501            prefix_name (ins, ins->all_prefixes[i], sizeflag));
9502       (*ins->info->fprintf_styled_func)
9503         (ins->info->stream, dis_style_mnemonic, "fwait");
9504       return i + 1;
9505     }
9506
9507   if (*ins->codep == 0x0f)
9508     {
9509       unsigned char threebyte;
9510
9511       ins->codep++;
9512       FETCH_DATA (ins->info, ins->codep + 1);
9513       threebyte = *ins->codep;
9514       dp = &dis386_twobyte[threebyte];
9515       ins->need_modrm = twobyte_has_modrm[threebyte];
9516       ins->codep++;
9517     }
9518   else
9519     {
9520       dp = &dis386[*ins->codep];
9521       ins->need_modrm = onebyte_has_modrm[*ins->codep];
9522       ins->codep++;
9523     }
9524
9525   /* Save sizeflag for printing the extra ins->prefixes later before updating
9526      it for mnemonic and operand processing.  The prefix names depend
9527      only on the address mode.  */
9528   orig_sizeflag = sizeflag;
9529   if (ins->prefixes & PREFIX_ADDR)
9530     sizeflag ^= AFLAG;
9531   if ((ins->prefixes & PREFIX_DATA))
9532     sizeflag ^= DFLAG;
9533
9534   ins->end_codep = ins->codep;
9535   if (ins->need_modrm)
9536     {
9537       FETCH_DATA (ins->info, ins->codep + 1);
9538       ins->modrm.mod = (*ins->codep >> 6) & 3;
9539       ins->modrm.reg = (*ins->codep >> 3) & 7;
9540       ins->modrm.rm = *ins->codep & 7;
9541     }
9542   else
9543     memset (&ins->modrm, 0, sizeof (ins->modrm));
9544
9545   ins->need_vex = false;
9546   memset (&ins->vex, 0, sizeof (ins->vex));
9547
9548   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
9549     {
9550       get_sib (ins, sizeflag);
9551       dofloat (ins, sizeflag);
9552     }
9553   else
9554     {
9555       dp = get_valid_dis386 (dp, ins);
9556       if (dp != NULL && putop (ins, dp->name, sizeflag) == 0)
9557         {
9558           get_sib (ins, sizeflag);
9559           for (i = 0; i < MAX_OPERANDS; ++i)
9560             {
9561               ins->obufp = ins->op_out[i];
9562               ins->op_ad = MAX_OPERANDS - 1 - i;
9563               if (dp->op[i].rtn)
9564                 (*dp->op[i].rtn) (ins, dp->op[i].bytemode, sizeflag);
9565               /* For EVEX instruction after the last operand masking
9566                  should be printed.  */
9567               if (i == 0 && ins->vex.evex)
9568                 {
9569                   /* Don't print {%k0}.  */
9570                   if (ins->vex.mask_register_specifier)
9571                     {
9572                       oappend (ins, "{");
9573                       oappend_maybe_intel (ins,
9574                                            att_names_mask
9575                                            [ins->vex.mask_register_specifier]);
9576                       oappend (ins, "}");
9577                     }
9578                   if (ins->vex.zeroing)
9579                     oappend (ins, "{z}");
9580
9581                   /* S/G insns require a mask and don't allow
9582                      zeroing-masking.  */
9583                   if ((dp->op[0].bytemode == vex_vsib_d_w_dq_mode
9584                        || dp->op[0].bytemode == vex_vsib_q_w_dq_mode)
9585                       && (ins->vex.mask_register_specifier == 0
9586                           || ins->vex.zeroing))
9587                     oappend (ins, "/(bad)");
9588                 }
9589             }
9590
9591           /* Check whether rounding control was enabled for an insn not
9592              supporting it.  */
9593           if (ins->modrm.mod == 3 && ins->vex.b
9594               && !(ins->evex_used & EVEX_b_used))
9595             {
9596               for (i = 0; i < MAX_OPERANDS; ++i)
9597                 {
9598                   ins->obufp = ins->op_out[i];
9599                   if (*ins->obufp)
9600                     continue;
9601                   oappend (ins, names_rounding[ins->vex.ll]);
9602                   oappend (ins, "bad}");
9603                   break;
9604                 }
9605             }
9606         }
9607     }
9608
9609   /* Clear instruction information.  */
9610   ins->info->insn_info_valid = 0;
9611   ins->info->branch_delay_insns = 0;
9612   ins->info->data_size = 0;
9613   ins->info->insn_type = dis_noninsn;
9614   ins->info->target = 0;
9615   ins->info->target2 = 0;
9616
9617   /* Reset jump operation indicator.  */
9618   ins->op_is_jump = false;
9619   {
9620     int jump_detection = 0;
9621
9622     /* Extract flags.  */
9623     for (i = 0; i < MAX_OPERANDS; ++i)
9624       {
9625         if ((dp->op[i].rtn == OP_J)
9626             || (dp->op[i].rtn == OP_indirE))
9627           jump_detection |= 1;
9628         else if ((dp->op[i].rtn == BND_Fixup)
9629                  || (!dp->op[i].rtn && !dp->op[i].bytemode))
9630           jump_detection |= 2;
9631         else if ((dp->op[i].bytemode == cond_jump_mode)
9632                  || (dp->op[i].bytemode == loop_jcxz_mode))
9633           jump_detection |= 4;
9634       }
9635
9636     /* Determine if this is a jump or branch.  */
9637     if ((jump_detection & 0x3) == 0x3)
9638       {
9639         ins->op_is_jump = true;
9640         if (jump_detection & 0x4)
9641           ins->info->insn_type = dis_condbranch;
9642         else
9643           ins->info->insn_type = (dp->name && !strncmp (dp->name, "call", 4))
9644             ? dis_jsr : dis_branch;
9645       }
9646   }
9647
9648   /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
9649      are all 0s in inverted form.  */
9650   if (ins->need_vex && ins->vex.register_specifier != 0)
9651     {
9652       (*ins->info->fprintf_styled_func) (ins->info->stream, dis_style_text,
9653                                          "(bad)");
9654       return ins->end_codep - priv.the_buffer;
9655     }
9656
9657   /* If EVEX.z is set, there must be an actual mask register in use.  */
9658   if (ins->vex.zeroing && ins->vex.mask_register_specifier == 0)
9659     {
9660       (*ins->info->fprintf_styled_func) (ins->info->stream, dis_style_text,
9661                                          "(bad)");
9662       return ins->end_codep - priv.the_buffer;
9663     }
9664
9665   switch (dp->prefix_requirement)
9666     {
9667     case PREFIX_DATA:
9668       /* If only the data prefix is marked as mandatory, its absence renders
9669          the encoding invalid.  Most other PREFIX_OPCODE rules still apply.  */
9670       if (ins->need_vex ? !ins->vex.prefix : !(ins->prefixes & PREFIX_DATA))
9671         {
9672           (*ins->info->fprintf_styled_func) (ins->info->stream,
9673                                              dis_style_text, "(bad)");
9674           return ins->end_codep - priv.the_buffer;
9675         }
9676       ins->used_prefixes |= PREFIX_DATA;
9677       /* Fall through.  */
9678     case PREFIX_OPCODE:
9679       /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
9680          unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
9681          used by putop and MMX/SSE operand and may be overridden by the
9682          PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
9683          separately.  */
9684       if (((ins->need_vex
9685             ? ins->vex.prefix == REPE_PREFIX_OPCODE
9686               || ins->vex.prefix == REPNE_PREFIX_OPCODE
9687             : (ins->prefixes
9688                & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
9689            && (ins->used_prefixes
9690                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
9691           || (((ins->need_vex
9692                 ? ins->vex.prefix == DATA_PREFIX_OPCODE
9693                 : ((ins->prefixes
9694                     & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
9695                    == PREFIX_DATA))
9696                && (ins->used_prefixes & PREFIX_DATA) == 0))
9697           || (ins->vex.evex && dp->prefix_requirement != PREFIX_DATA
9698               && !ins->vex.w != !(ins->used_prefixes & PREFIX_DATA)))
9699         {
9700           (*ins->info->fprintf_styled_func) (ins->info->stream,
9701                                              dis_style_text, "(bad)");
9702           return ins->end_codep - priv.the_buffer;
9703         }
9704       break;
9705
9706     case PREFIX_IGNORED:
9707       /* Zap data size and rep prefixes from used_prefixes and reinstate their
9708          origins in all_prefixes.  */
9709       ins->used_prefixes &= ~PREFIX_OPCODE;
9710       if (ins->last_data_prefix >= 0)
9711         ins->all_prefixes[ins->last_data_prefix] = 0x66;
9712       if (ins->last_repz_prefix >= 0)
9713         ins->all_prefixes[ins->last_repz_prefix] = 0xf3;
9714       if (ins->last_repnz_prefix >= 0)
9715         ins->all_prefixes[ins->last_repnz_prefix] = 0xf2;
9716       break;
9717     }
9718
9719   /* Check if the REX prefix is used.  */
9720   if ((ins->rex ^ ins->rex_used) == 0
9721       && !ins->need_vex && ins->last_rex_prefix >= 0)
9722     ins->all_prefixes[ins->last_rex_prefix] = 0;
9723
9724   /* Check if the SEG prefix is used.  */
9725   if ((ins->prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
9726                    | PREFIX_FS | PREFIX_GS)) != 0
9727       && (ins->used_prefixes & ins->active_seg_prefix) != 0)
9728     ins->all_prefixes[ins->last_seg_prefix] = 0;
9729
9730   /* Check if the ADDR prefix is used.  */
9731   if ((ins->prefixes & PREFIX_ADDR) != 0
9732       && (ins->used_prefixes & PREFIX_ADDR) != 0)
9733     ins->all_prefixes[ins->last_addr_prefix] = 0;
9734
9735   /* Check if the DATA prefix is used.  */
9736   if ((ins->prefixes & PREFIX_DATA) != 0
9737       && (ins->used_prefixes & PREFIX_DATA) != 0
9738       && !ins->need_vex)
9739     ins->all_prefixes[ins->last_data_prefix] = 0;
9740
9741   /* Print the extra ins->prefixes.  */
9742   prefix_length = 0;
9743   for (i = 0; i < (int) ARRAY_SIZE (ins->all_prefixes); i++)
9744     if (ins->all_prefixes[i])
9745       {
9746         const char *name;
9747         name = prefix_name (ins, ins->all_prefixes[i], orig_sizeflag);
9748         if (name == NULL)
9749           abort ();
9750         prefix_length += strlen (name) + 1;
9751         (*ins->info->fprintf_styled_func)
9752           (ins->info->stream, dis_style_mnemonic, "%s ", name);
9753       }
9754
9755   /* Check maximum code length.  */
9756   if ((ins->codep - ins->start_codep) > MAX_CODE_LENGTH)
9757     {
9758       (*ins->info->fprintf_styled_func)
9759         (ins->info->stream, dis_style_text, "(bad)");
9760       return MAX_CODE_LENGTH;
9761     }
9762
9763   ins->obufp = ins->mnemonicendp;
9764   for (i = strlen (ins->obuf) + prefix_length; i < 6; i++)
9765     oappend (ins, " ");
9766   oappend (ins, " ");
9767   (*ins->info->fprintf_styled_func)
9768     (ins->info->stream, dis_style_mnemonic, "%s", ins->obuf);
9769
9770   /* The enter and bound instructions are printed with operands in the same
9771      order as the intel book; everything else is printed in reverse order.  */
9772   if (ins->intel_syntax || ins->two_source_ops)
9773     {
9774       bfd_vma riprel;
9775
9776       for (i = 0; i < MAX_OPERANDS; ++i)
9777         op_txt[i] = ins->op_out[i];
9778
9779       if (ins->intel_syntax && dp && dp->op[2].rtn == OP_Rounding
9780           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
9781         {
9782           op_txt[2] = ins->op_out[3];
9783           op_txt[3] = ins->op_out[2];
9784         }
9785
9786       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
9787         {
9788           ins->op_ad = ins->op_index[i];
9789           ins->op_index[i] = ins->op_index[MAX_OPERANDS - 1 - i];
9790           ins->op_index[MAX_OPERANDS - 1 - i] = ins->op_ad;
9791           riprel = ins->op_riprel[i];
9792           ins->op_riprel[i] = ins->op_riprel[MAX_OPERANDS - 1 - i];
9793           ins->op_riprel[MAX_OPERANDS - 1 - i] = riprel;
9794         }
9795     }
9796   else
9797     {
9798       for (i = 0; i < MAX_OPERANDS; ++i)
9799         op_txt[MAX_OPERANDS - 1 - i] = ins->op_out[i];
9800     }
9801
9802   needcomma = 0;
9803   for (i = 0; i < MAX_OPERANDS; ++i)
9804     if (*op_txt[i])
9805       {
9806         if (needcomma)
9807           (*ins->info->fprintf_styled_func) (ins->info->stream,
9808                                              dis_style_text, ",");
9809         if (ins->op_index[i] != -1 && !ins->op_riprel[i])
9810           {
9811             bfd_vma target = (bfd_vma) ins->op_address[ins->op_index[i]];
9812
9813             if (ins->op_is_jump)
9814               {
9815                 ins->info->insn_info_valid = 1;
9816                 ins->info->branch_delay_insns = 0;
9817                 ins->info->data_size = 0;
9818                 ins->info->target = target;
9819                 ins->info->target2 = 0;
9820               }
9821             (*ins->info->print_address_func) (target, ins->info);
9822           }
9823         else
9824           (*ins->info->fprintf_styled_func) (ins->info->stream,
9825                                              dis_style_text, "%s",
9826                                              op_txt[i]);
9827         needcomma = 1;
9828       }
9829
9830   for (i = 0; i < MAX_OPERANDS; i++)
9831     if (ins->op_index[i] != -1 && ins->op_riprel[i])
9832       {
9833         (*ins->info->fprintf_styled_func) (ins->info->stream,
9834                                            dis_style_comment_start,
9835                                            "        # ");
9836         (*ins->info->print_address_func) ((bfd_vma)
9837                         (ins->start_pc + (ins->codep - ins->start_codep)
9838                          + ins->op_address[ins->op_index[i]]), ins->info);
9839         break;
9840       }
9841   return ins->codep - priv.the_buffer;
9842 }
9843
9844 static const char *float_mem[] = {
9845   /* d8 */
9846   "fadd{s|}",
9847   "fmul{s|}",
9848   "fcom{s|}",
9849   "fcomp{s|}",
9850   "fsub{s|}",
9851   "fsubr{s|}",
9852   "fdiv{s|}",
9853   "fdivr{s|}",
9854   /* d9 */
9855   "fld{s|}",
9856   "(bad)",
9857   "fst{s|}",
9858   "fstp{s|}",
9859   "fldenv{C|C}",
9860   "fldcw",
9861   "fNstenv{C|C}",
9862   "fNstcw",
9863   /* da */
9864   "fiadd{l|}",
9865   "fimul{l|}",
9866   "ficom{l|}",
9867   "ficomp{l|}",
9868   "fisub{l|}",
9869   "fisubr{l|}",
9870   "fidiv{l|}",
9871   "fidivr{l|}",
9872   /* db */
9873   "fild{l|}",
9874   "fisttp{l|}",
9875   "fist{l|}",
9876   "fistp{l|}",
9877   "(bad)",
9878   "fld{t|}",
9879   "(bad)",
9880   "fstp{t|}",
9881   /* dc */
9882   "fadd{l|}",
9883   "fmul{l|}",
9884   "fcom{l|}",
9885   "fcomp{l|}",
9886   "fsub{l|}",
9887   "fsubr{l|}",
9888   "fdiv{l|}",
9889   "fdivr{l|}",
9890   /* dd */
9891   "fld{l|}",
9892   "fisttp{ll|}",
9893   "fst{l||}",
9894   "fstp{l|}",
9895   "frstor{C|C}",
9896   "(bad)",
9897   "fNsave{C|C}",
9898   "fNstsw",
9899   /* de */
9900   "fiadd{s|}",
9901   "fimul{s|}",
9902   "ficom{s|}",
9903   "ficomp{s|}",
9904   "fisub{s|}",
9905   "fisubr{s|}",
9906   "fidiv{s|}",
9907   "fidivr{s|}",
9908   /* df */
9909   "fild{s|}",
9910   "fisttp{s|}",
9911   "fist{s|}",
9912   "fistp{s|}",
9913   "fbld",
9914   "fild{ll|}",
9915   "fbstp",
9916   "fistp{ll|}",
9917 };
9918
9919 static const unsigned char float_mem_mode[] = {
9920   /* d8 */
9921   d_mode,
9922   d_mode,
9923   d_mode,
9924   d_mode,
9925   d_mode,
9926   d_mode,
9927   d_mode,
9928   d_mode,
9929   /* d9 */
9930   d_mode,
9931   0,
9932   d_mode,
9933   d_mode,
9934   0,
9935   w_mode,
9936   0,
9937   w_mode,
9938   /* da */
9939   d_mode,
9940   d_mode,
9941   d_mode,
9942   d_mode,
9943   d_mode,
9944   d_mode,
9945   d_mode,
9946   d_mode,
9947   /* db */
9948   d_mode,
9949   d_mode,
9950   d_mode,
9951   d_mode,
9952   0,
9953   t_mode,
9954   0,
9955   t_mode,
9956   /* dc */
9957   q_mode,
9958   q_mode,
9959   q_mode,
9960   q_mode,
9961   q_mode,
9962   q_mode,
9963   q_mode,
9964   q_mode,
9965   /* dd */
9966   q_mode,
9967   q_mode,
9968   q_mode,
9969   q_mode,
9970   0,
9971   0,
9972   0,
9973   w_mode,
9974   /* de */
9975   w_mode,
9976   w_mode,
9977   w_mode,
9978   w_mode,
9979   w_mode,
9980   w_mode,
9981   w_mode,
9982   w_mode,
9983   /* df */
9984   w_mode,
9985   w_mode,
9986   w_mode,
9987   w_mode,
9988   t_mode,
9989   q_mode,
9990   t_mode,
9991   q_mode
9992 };
9993
9994 #define ST { OP_ST, 0 }
9995 #define STi { OP_STi, 0 }
9996
9997 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
9998 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
9999 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
10000 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
10001 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
10002 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
10003 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
10004 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
10005 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
10006
10007 static const struct dis386 float_reg[][8] = {
10008   /* d8 */
10009   {
10010     { "fadd",   { ST, STi }, 0 },
10011     { "fmul",   { ST, STi }, 0 },
10012     { "fcom",   { STi }, 0 },
10013     { "fcomp",  { STi }, 0 },
10014     { "fsub",   { ST, STi }, 0 },
10015     { "fsubr",  { ST, STi }, 0 },
10016     { "fdiv",   { ST, STi }, 0 },
10017     { "fdivr",  { ST, STi }, 0 },
10018   },
10019   /* d9 */
10020   {
10021     { "fld",    { STi }, 0 },
10022     { "fxch",   { STi }, 0 },
10023     { FGRPd9_2 },
10024     { Bad_Opcode },
10025     { FGRPd9_4 },
10026     { FGRPd9_5 },
10027     { FGRPd9_6 },
10028     { FGRPd9_7 },
10029   },
10030   /* da */
10031   {
10032     { "fcmovb", { ST, STi }, 0 },
10033     { "fcmove", { ST, STi }, 0 },
10034     { "fcmovbe",{ ST, STi }, 0 },
10035     { "fcmovu", { ST, STi }, 0 },
10036     { Bad_Opcode },
10037     { FGRPda_5 },
10038     { Bad_Opcode },
10039     { Bad_Opcode },
10040   },
10041   /* db */
10042   {
10043     { "fcmovnb",{ ST, STi }, 0 },
10044     { "fcmovne",{ ST, STi }, 0 },
10045     { "fcmovnbe",{ ST, STi }, 0 },
10046     { "fcmovnu",{ ST, STi }, 0 },
10047     { FGRPdb_4 },
10048     { "fucomi", { ST, STi }, 0 },
10049     { "fcomi",  { ST, STi }, 0 },
10050     { Bad_Opcode },
10051   },
10052   /* dc */
10053   {
10054     { "fadd",   { STi, ST }, 0 },
10055     { "fmul",   { STi, ST }, 0 },
10056     { Bad_Opcode },
10057     { Bad_Opcode },
10058     { "fsub{!M|r}",     { STi, ST }, 0 },
10059     { "fsub{M|}",       { STi, ST }, 0 },
10060     { "fdiv{!M|r}",     { STi, ST }, 0 },
10061     { "fdiv{M|}",       { STi, ST }, 0 },
10062   },
10063   /* dd */
10064   {
10065     { "ffree",  { STi }, 0 },
10066     { Bad_Opcode },
10067     { "fst",    { STi }, 0 },
10068     { "fstp",   { STi }, 0 },
10069     { "fucom",  { STi }, 0 },
10070     { "fucomp", { STi }, 0 },
10071     { Bad_Opcode },
10072     { Bad_Opcode },
10073   },
10074   /* de */
10075   {
10076     { "faddp",  { STi, ST }, 0 },
10077     { "fmulp",  { STi, ST }, 0 },
10078     { Bad_Opcode },
10079     { FGRPde_3 },
10080     { "fsub{!M|r}p",    { STi, ST }, 0 },
10081     { "fsub{M|}p",      { STi, ST }, 0 },
10082     { "fdiv{!M|r}p",    { STi, ST }, 0 },
10083     { "fdiv{M|}p",      { STi, ST }, 0 },
10084   },
10085   /* df */
10086   {
10087     { "ffreep", { STi }, 0 },
10088     { Bad_Opcode },
10089     { Bad_Opcode },
10090     { Bad_Opcode },
10091     { FGRPdf_4 },
10092     { "fucomip", { ST, STi }, 0 },
10093     { "fcomip", { ST, STi }, 0 },
10094     { Bad_Opcode },
10095   },
10096 };
10097
10098 static const char *const fgrps[][8] = {
10099   /* Bad opcode 0 */
10100   {
10101     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10102   },
10103
10104   /* d9_2  1 */
10105   {
10106     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10107   },
10108
10109   /* d9_4  2 */
10110   {
10111     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
10112   },
10113
10114   /* d9_5  3 */
10115   {
10116     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
10117   },
10118
10119   /* d9_6  4 */
10120   {
10121     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
10122   },
10123
10124   /* d9_7  5 */
10125   {
10126     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
10127   },
10128
10129   /* da_5  6 */
10130   {
10131     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10132   },
10133
10134   /* db_4  7 */
10135   {
10136     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
10137     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
10138   },
10139
10140   /* de_3  8 */
10141   {
10142     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10143   },
10144
10145   /* df_4  9 */
10146   {
10147     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10148   },
10149 };
10150
10151 static void
10152 swap_operand (instr_info *ins)
10153 {
10154   ins->mnemonicendp[0] = '.';
10155   ins->mnemonicendp[1] = 's';
10156   ins->mnemonicendp[2] = '\0';
10157   ins->mnemonicendp += 2;
10158 }
10159
10160 static void
10161 OP_Skip_MODRM (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
10162                int sizeflag ATTRIBUTE_UNUSED)
10163 {
10164   /* Skip mod/rm byte.  */
10165   MODRM_CHECK;
10166   ins->codep++;
10167 }
10168
10169 static void
10170 dofloat (instr_info *ins, int sizeflag)
10171 {
10172   const struct dis386 *dp;
10173   unsigned char floatop;
10174
10175   floatop = ins->codep[-1];
10176
10177   if (ins->modrm.mod != 3)
10178     {
10179       int fp_indx = (floatop - 0xd8) * 8 + ins->modrm.reg;
10180
10181       putop (ins, float_mem[fp_indx], sizeflag);
10182       ins->obufp = ins->op_out[0];
10183       ins->op_ad = 2;
10184       OP_E (ins, float_mem_mode[fp_indx], sizeflag);
10185       return;
10186     }
10187   /* Skip mod/rm byte.  */
10188   MODRM_CHECK;
10189   ins->codep++;
10190
10191   dp = &float_reg[floatop - 0xd8][ins->modrm.reg];
10192   if (dp->name == NULL)
10193     {
10194       putop (ins, fgrps[dp->op[0].bytemode][ins->modrm.rm], sizeflag);
10195
10196       /* Instruction fnstsw is only one with strange arg.  */
10197       if (floatop == 0xdf && ins->codep[-1] == 0xe0)
10198         strcpy (ins->op_out[0], att_names16[0] + ins->intel_syntax);
10199     }
10200   else
10201     {
10202       putop (ins, dp->name, sizeflag);
10203
10204       ins->obufp = ins->op_out[0];
10205       ins->op_ad = 2;
10206       if (dp->op[0].rtn)
10207         (*dp->op[0].rtn) (ins, dp->op[0].bytemode, sizeflag);
10208
10209       ins->obufp = ins->op_out[1];
10210       ins->op_ad = 1;
10211       if (dp->op[1].rtn)
10212         (*dp->op[1].rtn) (ins, dp->op[1].bytemode, sizeflag);
10213     }
10214 }
10215
10216 static void
10217 OP_ST (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
10218        int sizeflag ATTRIBUTE_UNUSED)
10219 {
10220   oappend_maybe_intel (ins, "%st");
10221 }
10222
10223 static void
10224 OP_STi (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
10225         int sizeflag ATTRIBUTE_UNUSED)
10226 {
10227   sprintf (ins->scratchbuf, "%%st(%d)", ins->modrm.rm);
10228   oappend_maybe_intel (ins, ins->scratchbuf);
10229 }
10230
10231 /* Capital letters in template are macros.  */
10232 static int
10233 putop (instr_info *ins, const char *in_template, int sizeflag)
10234 {
10235   const char *p;
10236   int alt = 0;
10237   int cond = 1;
10238   unsigned int l = 0, len = 0;
10239   char last[4];
10240
10241   for (p = in_template; *p; p++)
10242     {
10243       if (len > l)
10244         {
10245           if (l >= sizeof (last) || !ISUPPER (*p))
10246             abort ();
10247           last[l++] = *p;
10248           continue;
10249         }
10250       switch (*p)
10251         {
10252         default:
10253           *ins->obufp++ = *p;
10254           break;
10255         case '%':
10256           len++;
10257           break;
10258         case '!':
10259           cond = 0;
10260           break;
10261         case '{':
10262           if (ins->intel_syntax)
10263             {
10264               while (*++p != '|')
10265                 if (*p == '}' || *p == '\0')
10266                   abort ();
10267               alt = 1;
10268             }
10269           break;
10270         case '|':
10271           while (*++p != '}')
10272             {
10273               if (*p == '\0')
10274                 abort ();
10275             }
10276           break;
10277         case '}':
10278           alt = 0;
10279           break;
10280         case 'A':
10281           if (ins->intel_syntax)
10282             break;
10283           if ((ins->need_modrm && ins->modrm.mod != 3)
10284               || (sizeflag & SUFFIX_ALWAYS))
10285             *ins->obufp++ = 'b';
10286           break;
10287         case 'B':
10288           if (l == 0)
10289             {
10290             case_B:
10291               if (ins->intel_syntax)
10292                 break;
10293               if (sizeflag & SUFFIX_ALWAYS)
10294                 *ins->obufp++ = 'b';
10295             }
10296           else if (l == 1 && last[0] == 'L')
10297             {
10298               if (ins->address_mode == mode_64bit
10299                   && !(ins->prefixes & PREFIX_ADDR))
10300                 {
10301                   *ins->obufp++ = 'a';
10302                   *ins->obufp++ = 'b';
10303                   *ins->obufp++ = 's';
10304                 }
10305
10306               goto case_B;
10307             }
10308           else
10309             abort ();
10310           break;
10311         case 'C':
10312           if (ins->intel_syntax && !alt)
10313             break;
10314           if ((ins->prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10315             {
10316               if (sizeflag & DFLAG)
10317                 *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10318               else
10319                 *ins->obufp++ = ins->intel_syntax ? 'w' : 's';
10320               ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10321             }
10322           break;
10323         case 'D':
10324           if (l == 1)
10325             {
10326               switch (last[0])
10327               {
10328               case 'X':
10329                 if (!ins->vex.evex || ins->vex.w)
10330                   *ins->obufp++ = 'd';
10331                 else
10332                   oappend (ins, "{bad}");
10333                 break;
10334               default:
10335                 abort ();
10336               }
10337               break;
10338             }
10339           if (l)
10340             abort ();
10341           if (ins->intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
10342             break;
10343           USED_REX (REX_W);
10344           if (ins->modrm.mod == 3)
10345             {
10346               if (ins->rex & REX_W)
10347                 *ins->obufp++ = 'q';
10348               else
10349                 {
10350                   if (sizeflag & DFLAG)
10351                     *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10352                   else
10353                     *ins->obufp++ = 'w';
10354                   ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10355                 }
10356             }
10357           else
10358             *ins->obufp++ = 'w';
10359           break;
10360         case 'E':               /* For jcxz/jecxz */
10361           if (ins->address_mode == mode_64bit)
10362             {
10363               if (sizeflag & AFLAG)
10364                 *ins->obufp++ = 'r';
10365               else
10366                 *ins->obufp++ = 'e';
10367             }
10368           else
10369             if (sizeflag & AFLAG)
10370               *ins->obufp++ = 'e';
10371           ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR);
10372           break;
10373         case 'F':
10374           if (ins->intel_syntax)
10375             break;
10376           if ((ins->prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
10377             {
10378               if (sizeflag & AFLAG)
10379                 *ins->obufp++ = ins->address_mode == mode_64bit ? 'q' : 'l';
10380               else
10381                 *ins->obufp++ = ins->address_mode == mode_64bit ? 'l' : 'w';
10382               ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR);
10383             }
10384           break;
10385         case 'G':
10386           if (ins->intel_syntax || (ins->obufp[-1] != 's'
10387                                     && !(sizeflag & SUFFIX_ALWAYS)))
10388             break;
10389           if ((ins->rex & REX_W) || (sizeflag & DFLAG))
10390             *ins->obufp++ = 'l';
10391           else
10392             *ins->obufp++ = 'w';
10393           if (!(ins->rex & REX_W))
10394             ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10395           break;
10396         case 'H':
10397           if (l == 0)
10398             {
10399               if (ins->intel_syntax)
10400                 break;
10401               if ((ins->prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
10402                   || (ins->prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
10403                 {
10404                   ins->used_prefixes |= ins->prefixes & (PREFIX_CS | PREFIX_DS);
10405                   *ins->obufp++ = ',';
10406                   *ins->obufp++ = 'p';
10407
10408                   /* Set active_seg_prefix even if not set in 64-bit mode
10409                      because here it is a valid branch hint. */
10410                   if (ins->prefixes & PREFIX_DS)
10411                     {
10412                       ins->active_seg_prefix = PREFIX_DS;
10413                       *ins->obufp++ = 't';
10414                     }
10415                   else
10416                     {
10417                       ins->active_seg_prefix = PREFIX_CS;
10418                       *ins->obufp++ = 'n';
10419                     }
10420                 }
10421             }
10422           else if (l == 1 && last[0] == 'X')
10423             {
10424               if (!ins->vex.w)
10425                 *ins->obufp++ = 'h';
10426               else
10427                 oappend (ins, "{bad}");
10428             }
10429           else
10430             abort ();
10431           break;
10432         case 'K':
10433           USED_REX (REX_W);
10434           if (ins->rex & REX_W)
10435             *ins->obufp++ = 'q';
10436           else
10437             *ins->obufp++ = 'd';
10438           break;
10439         case 'L':
10440           abort ();
10441         case 'M':
10442           if (ins->intel_mnemonic != cond)
10443             *ins->obufp++ = 'r';
10444           break;
10445         case 'N':
10446           if ((ins->prefixes & PREFIX_FWAIT) == 0)
10447             *ins->obufp++ = 'n';
10448           else
10449             ins->used_prefixes |= PREFIX_FWAIT;
10450           break;
10451         case 'O':
10452           USED_REX (REX_W);
10453           if (ins->rex & REX_W)
10454             *ins->obufp++ = 'o';
10455           else if (ins->intel_syntax && (sizeflag & DFLAG))
10456             *ins->obufp++ = 'q';
10457           else
10458             *ins->obufp++ = 'd';
10459           if (!(ins->rex & REX_W))
10460             ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10461           break;
10462         case '@':
10463           if (ins->address_mode == mode_64bit
10464               && (ins->isa64 == intel64 || (ins->rex & REX_W)
10465                   || !(ins->prefixes & PREFIX_DATA)))
10466             {
10467               if (sizeflag & SUFFIX_ALWAYS)
10468                 *ins->obufp++ = 'q';
10469               break;
10470             }
10471           /* Fall through.  */
10472         case 'P':
10473           if (l == 0)
10474             {
10475               if ((ins->modrm.mod == 3 || !cond)
10476                   && !(sizeflag & SUFFIX_ALWAYS))
10477                 break;
10478           /* Fall through.  */
10479         case 'T':
10480               if ((!(ins->rex & REX_W) && (ins->prefixes & PREFIX_DATA))
10481                   || ((sizeflag & SUFFIX_ALWAYS)
10482                       && ins->address_mode != mode_64bit))
10483                 {
10484                   *ins->obufp++ = (sizeflag & DFLAG)
10485                                   ? ins->intel_syntax ? 'd' : 'l' : 'w';
10486                   ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10487                 }
10488               else if (sizeflag & SUFFIX_ALWAYS)
10489                 *ins->obufp++ = 'q';
10490             }
10491           else if (l == 1 && last[0] == 'L')
10492             {
10493               if ((ins->prefixes & PREFIX_DATA)
10494                   || (ins->rex & REX_W)
10495                   || (sizeflag & SUFFIX_ALWAYS))
10496                 {
10497                   USED_REX (REX_W);
10498                   if (ins->rex & REX_W)
10499                     *ins->obufp++ = 'q';
10500                   else
10501                     {
10502                       if (sizeflag & DFLAG)
10503                         *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10504                       else
10505                         *ins->obufp++ = 'w';
10506                       ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10507                     }
10508                 }
10509             }
10510           else
10511             abort ();
10512           break;
10513         case 'Q':
10514           if (l == 0)
10515             {
10516               if (ins->intel_syntax && !alt)
10517                 break;
10518               USED_REX (REX_W);
10519               if ((ins->need_modrm && ins->modrm.mod != 3)
10520                   || (sizeflag & SUFFIX_ALWAYS))
10521                 {
10522                   if (ins->rex & REX_W)
10523                     *ins->obufp++ = 'q';
10524                   else
10525                     {
10526                       if (sizeflag & DFLAG)
10527                         *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10528                       else
10529                         *ins->obufp++ = 'w';
10530                       ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10531                     }
10532                 }
10533             }
10534           else if (l == 1 && last[0] == 'D')
10535             *ins->obufp++ = ins->vex.w ? 'q' : 'd';
10536           else if (l == 1 && last[0] == 'L')
10537             {
10538               if (cond ? ins->modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)
10539                        : ins->address_mode != mode_64bit)
10540                 break;
10541               if ((ins->rex & REX_W))
10542                 {
10543                   USED_REX (REX_W);
10544                   *ins->obufp++ = 'q';
10545                 }
10546               else if ((ins->address_mode == mode_64bit && cond)
10547                       || (sizeflag & SUFFIX_ALWAYS))
10548                 *ins->obufp++ = ins->intel_syntax? 'd' : 'l';
10549             }
10550           else
10551             abort ();
10552           break;
10553         case 'R':
10554           USED_REX (REX_W);
10555           if (ins->rex & REX_W)
10556             *ins->obufp++ = 'q';
10557           else if (sizeflag & DFLAG)
10558             {
10559               if (ins->intel_syntax)
10560                   *ins->obufp++ = 'd';
10561               else
10562                   *ins->obufp++ = 'l';
10563             }
10564           else
10565             *ins->obufp++ = 'w';
10566           if (ins->intel_syntax && !p[1]
10567               && ((ins->rex & REX_W) || (sizeflag & DFLAG)))
10568             *ins->obufp++ = 'e';
10569           if (!(ins->rex & REX_W))
10570             ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10571           break;
10572         case 'S':
10573           if (l == 0)
10574             {
10575             case_S:
10576               if (ins->intel_syntax)
10577                 break;
10578               if (sizeflag & SUFFIX_ALWAYS)
10579                 {
10580                   if (ins->rex & REX_W)
10581                     *ins->obufp++ = 'q';
10582                   else
10583                     {
10584                       if (sizeflag & DFLAG)
10585                         *ins->obufp++ = 'l';
10586                       else
10587                         *ins->obufp++ = 'w';
10588                       ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10589                     }
10590                 }
10591               break;
10592             }
10593           if (l != 1)
10594             abort ();
10595           switch (last[0])
10596             {
10597             case 'L':
10598               if (ins->address_mode == mode_64bit
10599                   && !(ins->prefixes & PREFIX_ADDR))
10600                 {
10601                   *ins->obufp++ = 'a';
10602                   *ins->obufp++ = 'b';
10603                   *ins->obufp++ = 's';
10604                 }
10605
10606               goto case_S;
10607             case 'X':
10608               if (!ins->vex.evex || !ins->vex.w)
10609                 *ins->obufp++ = 's';
10610               else
10611                 oappend (ins, "{bad}");
10612               break;
10613             default:
10614               abort ();
10615             }
10616           break;
10617         case 'V':
10618           if (l == 0)
10619             abort ();
10620           else if (l == 1
10621                    && (last[0] == 'L' || last[0] == 'X'))
10622             {
10623               if (last[0] == 'X')
10624                 {
10625                   *ins->obufp++ = '{';
10626                   *ins->obufp++ = 'v';
10627                   *ins->obufp++ = 'e';
10628                   *ins->obufp++ = 'x';
10629                   *ins->obufp++ = '}';
10630                 }
10631               else if (ins->rex & REX_W)
10632                 {
10633                   *ins->obufp++ = 'a';
10634                   *ins->obufp++ = 'b';
10635                   *ins->obufp++ = 's';
10636                 }
10637             }
10638           else
10639             abort ();
10640           goto case_S;
10641         case 'W':
10642           if (l == 0)
10643             {
10644               /* operand size flag for cwtl, cbtw */
10645               USED_REX (REX_W);
10646               if (ins->rex & REX_W)
10647                 {
10648                   if (ins->intel_syntax)
10649                     *ins->obufp++ = 'd';
10650                   else
10651                     *ins->obufp++ = 'l';
10652                 }
10653               else if (sizeflag & DFLAG)
10654                 *ins->obufp++ = 'w';
10655               else
10656                 *ins->obufp++ = 'b';
10657               if (!(ins->rex & REX_W))
10658                 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10659             }
10660           else if (l == 1)
10661             {
10662               if (!ins->need_vex)
10663                 abort ();
10664               if (last[0] == 'X')
10665                 *ins->obufp++ = ins->vex.w ? 'd': 's';
10666               else if (last[0] == 'B')
10667                 *ins->obufp++ = ins->vex.w ? 'w': 'b';
10668               else
10669                 abort ();
10670             }
10671           else
10672             abort ();
10673           break;
10674         case 'X':
10675           if (l != 0)
10676             abort ();
10677           if (ins->need_vex
10678               ? ins->vex.prefix == DATA_PREFIX_OPCODE
10679               : ins->prefixes & PREFIX_DATA)
10680             {
10681               *ins->obufp++ = 'd';
10682               ins->used_prefixes |= PREFIX_DATA;
10683             }
10684           else
10685             *ins->obufp++ = 's';
10686           break;
10687         case 'Y':
10688           if (l == 1 && last[0] == 'X')
10689             {
10690               if (!ins->need_vex)
10691                 abort ();
10692               if (ins->intel_syntax
10693                   || ((ins->modrm.mod == 3 || ins->vex.b)
10694                       && !(sizeflag & SUFFIX_ALWAYS)))
10695                 break;
10696               switch (ins->vex.length)
10697                 {
10698                 case 128:
10699                   *ins->obufp++ = 'x';
10700                   break;
10701                 case 256:
10702                   *ins->obufp++ = 'y';
10703                   break;
10704                 case 512:
10705                   if (!ins->vex.evex)
10706                 default:
10707                     abort ();
10708                 }
10709             }
10710           else
10711             abort ();
10712           break;
10713         case 'Z':
10714           if (l == 0)
10715             {
10716               /* These insns ignore ModR/M.mod: Force it to 3 for OP_E().  */
10717               ins->modrm.mod = 3;
10718               if (!ins->intel_syntax && (sizeflag & SUFFIX_ALWAYS))
10719                 *ins->obufp++ = ins->address_mode == mode_64bit ? 'q' : 'l';
10720             }
10721           else if (l == 1 && last[0] == 'X')
10722             {
10723               if (!ins->vex.evex)
10724                 abort ();
10725               if (ins->intel_syntax
10726                   || ((ins->modrm.mod == 3 || ins->vex.b)
10727                       && !(sizeflag & SUFFIX_ALWAYS)))
10728                 break;
10729               switch (ins->vex.length)
10730                 {
10731                 case 128:
10732                   *ins->obufp++ = 'x';
10733                   break;
10734                 case 256:
10735                   *ins->obufp++ = 'y';
10736                   break;
10737                 case 512:
10738                   *ins->obufp++ = 'z';
10739                   break;
10740                 default:
10741                   abort ();
10742                 }
10743             }
10744           else
10745             abort ();
10746           break;
10747         case '^':
10748           if (ins->intel_syntax)
10749             break;
10750           if (ins->isa64 == intel64 && (ins->rex & REX_W))
10751             {
10752               USED_REX (REX_W);
10753               *ins->obufp++ = 'q';
10754               break;
10755             }
10756           if ((ins->prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10757             {
10758               if (sizeflag & DFLAG)
10759                 *ins->obufp++ = 'l';
10760               else
10761                 *ins->obufp++ = 'w';
10762               ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10763             }
10764           break;
10765         }
10766
10767       if (len == l)
10768         len = l = 0;
10769     }
10770   *ins->obufp = 0;
10771   ins->mnemonicendp = ins->obufp;
10772   return 0;
10773 }
10774
10775 static void
10776 oappend (instr_info *ins, const char *s)
10777 {
10778   ins->obufp = stpcpy (ins->obufp, s);
10779 }
10780
10781 static void
10782 append_seg (instr_info *ins)
10783 {
10784   /* Only print the active segment register.  */
10785   if (!ins->active_seg_prefix)
10786     return;
10787
10788   ins->used_prefixes |= ins->active_seg_prefix;
10789   switch (ins->active_seg_prefix)
10790     {
10791     case PREFIX_CS:
10792       oappend_maybe_intel (ins, "%cs:");
10793       break;
10794     case PREFIX_DS:
10795       oappend_maybe_intel (ins, "%ds:");
10796       break;
10797     case PREFIX_SS:
10798       oappend_maybe_intel (ins, "%ss:");
10799       break;
10800     case PREFIX_ES:
10801       oappend_maybe_intel (ins, "%es:");
10802       break;
10803     case PREFIX_FS:
10804       oappend_maybe_intel (ins, "%fs:");
10805       break;
10806     case PREFIX_GS:
10807       oappend_maybe_intel (ins, "%gs:");
10808       break;
10809     default:
10810       break;
10811     }
10812 }
10813
10814 static void
10815 OP_indirE (instr_info *ins, int bytemode, int sizeflag)
10816 {
10817   if (!ins->intel_syntax)
10818     oappend (ins, "*");
10819   OP_E (ins, bytemode, sizeflag);
10820 }
10821
10822 static void
10823 print_operand_value (instr_info *ins, char *buf, int hex, bfd_vma disp)
10824 {
10825   if (ins->address_mode == mode_64bit)
10826     {
10827       if (hex)
10828         {
10829           char tmp[30];
10830           int i;
10831           buf[0] = '0';
10832           buf[1] = 'x';
10833           sprintf_vma (tmp, disp);
10834           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
10835           strcpy (buf + 2, tmp + i);
10836         }
10837       else
10838         {
10839           bfd_signed_vma v = disp;
10840           char tmp[30];
10841           int i;
10842           if (v < 0)
10843             {
10844               *(buf++) = '-';
10845               v = -disp;
10846               /* Check for possible overflow on 0x8000000000000000.  */
10847               if (v < 0)
10848                 {
10849                   strcpy (buf, "9223372036854775808");
10850                   return;
10851                 }
10852             }
10853           if (!v)
10854             {
10855               strcpy (buf, "0");
10856               return;
10857             }
10858
10859           i = 0;
10860           tmp[29] = 0;
10861           while (v)
10862             {
10863               tmp[28 - i] = (v % 10) + '0';
10864               v /= 10;
10865               i++;
10866             }
10867           strcpy (buf, tmp + 29 - i);
10868         }
10869     }
10870   else
10871     {
10872       if (hex)
10873         sprintf (buf, "0x%x", (unsigned int) disp);
10874       else
10875         sprintf (buf, "%d", (int) disp);
10876     }
10877 }
10878
10879 /* Put DISP in BUF as signed hex number.  */
10880
10881 static void
10882 print_displacement (instr_info *ins, char *buf, bfd_vma disp)
10883 {
10884   bfd_signed_vma val = disp;
10885   char tmp[30];
10886   int i, j = 0;
10887
10888   if (val < 0)
10889     {
10890       buf[j++] = '-';
10891       val = -disp;
10892
10893       /* Check for possible overflow.  */
10894       if (val < 0)
10895         {
10896           switch (ins->address_mode)
10897             {
10898             case mode_64bit:
10899               strcpy (buf + j, "0x8000000000000000");
10900               break;
10901             case mode_32bit:
10902               strcpy (buf + j, "0x80000000");
10903               break;
10904             case mode_16bit:
10905               strcpy (buf + j, "0x8000");
10906               break;
10907             }
10908           return;
10909         }
10910     }
10911
10912   buf[j++] = '0';
10913   buf[j++] = 'x';
10914
10915   sprintf_vma (tmp, (bfd_vma) val);
10916   for (i = 0; tmp[i] == '0'; i++)
10917     continue;
10918   if (tmp[i] == '\0')
10919     i--;
10920   strcpy (buf + j, tmp + i);
10921 }
10922
10923 static void
10924 intel_operand_size (instr_info *ins, int bytemode, int sizeflag)
10925 {
10926   if (ins->vex.b)
10927     {
10928       if (!ins->vex.no_broadcast)
10929         switch (bytemode)
10930           {
10931           case x_mode:
10932           case evex_half_bcst_xmmq_mode:
10933             if (ins->vex.w)
10934               oappend (ins, "QWORD PTR ");
10935             else
10936               oappend (ins, "DWORD PTR ");
10937             break;
10938           case xh_mode:
10939           case evex_half_bcst_xmmqh_mode:
10940           case evex_half_bcst_xmmqdh_mode:
10941             oappend (ins, "WORD PTR ");
10942             break;
10943           default:
10944             ins->vex.no_broadcast = true;
10945             break;
10946           }
10947       return;
10948     }
10949   switch (bytemode)
10950     {
10951     case b_mode:
10952     case b_swap_mode:
10953     case db_mode:
10954       oappend (ins, "BYTE PTR ");
10955       break;
10956     case w_mode:
10957     case w_swap_mode:
10958     case dw_mode:
10959       oappend (ins, "WORD PTR ");
10960       break;
10961     case indir_v_mode:
10962       if (ins->address_mode == mode_64bit && ins->isa64 == intel64)
10963         {
10964           oappend (ins, "QWORD PTR ");
10965           break;
10966         }
10967       /* Fall through.  */
10968     case stack_v_mode:
10969       if (ins->address_mode == mode_64bit && ((sizeflag & DFLAG)
10970                                               || (ins->rex & REX_W)))
10971         {
10972           oappend (ins, "QWORD PTR ");
10973           break;
10974         }
10975       /* Fall through.  */
10976     case v_mode:
10977     case v_swap_mode:
10978     case dq_mode:
10979       USED_REX (REX_W);
10980       if (ins->rex & REX_W)
10981         oappend (ins, "QWORD PTR ");
10982       else if (bytemode == dq_mode)
10983         oappend (ins, "DWORD PTR ");
10984       else
10985         {
10986           if (sizeflag & DFLAG)
10987             oappend (ins, "DWORD PTR ");
10988           else
10989             oappend (ins, "WORD PTR ");
10990           ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10991         }
10992       break;
10993     case z_mode:
10994       if ((ins->rex & REX_W) || (sizeflag & DFLAG))
10995         *ins->obufp++ = 'D';
10996       oappend (ins, "WORD PTR ");
10997       if (!(ins->rex & REX_W))
10998         ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10999       break;
11000     case a_mode:
11001       if (sizeflag & DFLAG)
11002         oappend (ins, "QWORD PTR ");
11003       else
11004         oappend (ins, "DWORD PTR ");
11005       ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11006       break;
11007     case movsxd_mode:
11008       if (!(sizeflag & DFLAG) && ins->isa64 == intel64)
11009         oappend (ins, "WORD PTR ");
11010       else
11011         oappend (ins, "DWORD PTR ");
11012       ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11013       break;
11014     case d_mode:
11015     case d_swap_mode:
11016       oappend (ins, "DWORD PTR ");
11017       break;
11018     case q_mode:
11019     case q_swap_mode:
11020       oappend (ins, "QWORD PTR ");
11021       break;
11022     case m_mode:
11023       if (ins->address_mode == mode_64bit)
11024         oappend (ins, "QWORD PTR ");
11025       else
11026         oappend (ins, "DWORD PTR ");
11027       break;
11028     case f_mode:
11029       if (sizeflag & DFLAG)
11030         oappend (ins, "FWORD PTR ");
11031       else
11032         oappend (ins, "DWORD PTR ");
11033       ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11034       break;
11035     case t_mode:
11036       oappend (ins, "TBYTE PTR ");
11037       break;
11038     case x_mode:
11039     case xh_mode:
11040     case x_swap_mode:
11041     case evex_x_gscat_mode:
11042     case evex_x_nobcst_mode:
11043     case bw_unit_mode:
11044       if (ins->need_vex)
11045         {
11046           switch (ins->vex.length)
11047             {
11048             case 128:
11049               oappend (ins, "XMMWORD PTR ");
11050               break;
11051             case 256:
11052               oappend (ins, "YMMWORD PTR ");
11053               break;
11054             case 512:
11055               oappend (ins, "ZMMWORD PTR ");
11056               break;
11057             default:
11058               abort ();
11059             }
11060         }
11061       else
11062         oappend (ins, "XMMWORD PTR ");
11063       break;
11064     case xmm_mode:
11065       oappend (ins, "XMMWORD PTR ");
11066       break;
11067     case ymm_mode:
11068       oappend (ins, "YMMWORD PTR ");
11069       break;
11070     case xmmq_mode:
11071     case evex_half_bcst_xmmqh_mode:
11072     case evex_half_bcst_xmmq_mode:
11073       if (!ins->need_vex)
11074         abort ();
11075
11076       switch (ins->vex.length)
11077         {
11078         case 128:
11079           oappend (ins, "QWORD PTR ");
11080           break;
11081         case 256:
11082           oappend (ins, "XMMWORD PTR ");
11083           break;
11084         case 512:
11085           oappend (ins, "YMMWORD PTR ");
11086           break;
11087         default:
11088           abort ();
11089         }
11090       break;
11091     case xmmdw_mode:
11092       if (!ins->need_vex)
11093         abort ();
11094
11095       switch (ins->vex.length)
11096         {
11097         case 128:
11098           oappend (ins, "WORD PTR ");
11099           break;
11100         case 256:
11101           oappend (ins, "DWORD PTR ");
11102           break;
11103         case 512:
11104           oappend (ins, "QWORD PTR ");
11105           break;
11106         default:
11107           abort ();
11108         }
11109       break;
11110     case xmmqd_mode:
11111     case evex_half_bcst_xmmqdh_mode:
11112       if (!ins->need_vex)
11113         abort ();
11114
11115       switch (ins->vex.length)
11116         {
11117         case 128:
11118           oappend (ins, "DWORD PTR ");
11119           break;
11120         case 256:
11121           oappend (ins, "QWORD PTR ");
11122           break;
11123         case 512:
11124           oappend (ins, "XMMWORD PTR ");
11125           break;
11126         default:
11127           abort ();
11128         }
11129       break;
11130     case ymmq_mode:
11131       if (!ins->need_vex)
11132         abort ();
11133
11134       switch (ins->vex.length)
11135         {
11136         case 128:
11137           oappend (ins, "QWORD PTR ");
11138           break;
11139         case 256:
11140           oappend (ins, "YMMWORD PTR ");
11141           break;
11142         case 512:
11143           oappend (ins, "ZMMWORD PTR ");
11144           break;
11145         default:
11146           abort ();
11147         }
11148       break;
11149     case o_mode:
11150       oappend (ins, "OWORD PTR ");
11151       break;
11152     case vex_vsib_d_w_dq_mode:
11153     case vex_vsib_q_w_dq_mode:
11154       if (!ins->need_vex)
11155         abort ();
11156       if (ins->vex.w)
11157         oappend (ins, "QWORD PTR ");
11158       else
11159         oappend (ins, "DWORD PTR ");
11160       break;
11161     case mask_bd_mode:
11162       if (!ins->need_vex || ins->vex.length != 128)
11163         abort ();
11164       if (ins->vex.w)
11165         oappend (ins, "DWORD PTR ");
11166       else
11167         oappend (ins, "BYTE PTR ");
11168       break;
11169     case mask_mode:
11170       if (!ins->need_vex)
11171         abort ();
11172       if (ins->vex.w)
11173         oappend (ins, "QWORD PTR ");
11174       else
11175         oappend (ins, "WORD PTR ");
11176       break;
11177     case v_bnd_mode:
11178     case v_bndmk_mode:
11179     default:
11180       break;
11181     }
11182 }
11183
11184 static void
11185 print_register (instr_info *ins, unsigned int reg, unsigned int rexmask,
11186                 int bytemode, int sizeflag)
11187 {
11188   const char *const *names;
11189
11190   USED_REX (rexmask);
11191   if (ins->rex & rexmask)
11192     reg += 8;
11193
11194   switch (bytemode)
11195     {
11196     case b_mode:
11197     case b_swap_mode:
11198       if (reg & 4)
11199         USED_REX (0);
11200       if (ins->rex)
11201         names = att_names8rex;
11202       else
11203         names = att_names8;
11204       break;
11205     case w_mode:
11206       names = att_names16;
11207       break;
11208     case d_mode:
11209     case dw_mode:
11210     case db_mode:
11211       names = att_names32;
11212       break;
11213     case q_mode:
11214       names = att_names64;
11215       break;
11216     case m_mode:
11217     case v_bnd_mode:
11218       names = ins->address_mode == mode_64bit ? att_names64 : att_names32;
11219       break;
11220     case bnd_mode:
11221     case bnd_swap_mode:
11222       if (reg > 0x3)
11223         {
11224           oappend (ins, "(bad)");
11225           return;
11226         }
11227       names = att_names_bnd;
11228       break;
11229     case indir_v_mode:
11230       if (ins->address_mode == mode_64bit && ins->isa64 == intel64)
11231         {
11232           names = att_names64;
11233           break;
11234         }
11235       /* Fall through.  */
11236     case stack_v_mode:
11237       if (ins->address_mode == mode_64bit && ((sizeflag & DFLAG)
11238                                               || (ins->rex & REX_W)))
11239         {
11240           names = att_names64;
11241           break;
11242         }
11243       bytemode = v_mode;
11244       /* Fall through.  */
11245     case v_mode:
11246     case v_swap_mode:
11247     case dq_mode:
11248       USED_REX (REX_W);
11249       if (ins->rex & REX_W)
11250         names = att_names64;
11251       else if (bytemode != v_mode && bytemode != v_swap_mode)
11252         names = att_names32;
11253       else
11254         {
11255           if (sizeflag & DFLAG)
11256             names = att_names32;
11257           else
11258             names = att_names16;
11259           ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11260         }
11261       break;
11262     case movsxd_mode:
11263       if (!(sizeflag & DFLAG) && ins->isa64 == intel64)
11264         names = att_names16;
11265       else
11266         names = att_names32;
11267       ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11268       break;
11269     case va_mode:
11270       names = (ins->address_mode == mode_64bit
11271                ? att_names64 : att_names32);
11272       if (!(ins->prefixes & PREFIX_ADDR))
11273         names = (ins->address_mode == mode_16bit
11274                      ? att_names16 : names);
11275       else
11276         {
11277           /* Remove "addr16/addr32".  */
11278           ins->all_prefixes[ins->last_addr_prefix] = 0;
11279           names = (ins->address_mode != mode_32bit
11280                        ? att_names32 : att_names16);
11281           ins->used_prefixes |= PREFIX_ADDR;
11282         }
11283       break;
11284     case mask_bd_mode:
11285     case mask_mode:
11286       if (reg > 0x7)
11287         {
11288           oappend (ins, "(bad)");
11289           return;
11290         }
11291       names = att_names_mask;
11292       break;
11293     case 0:
11294       return;
11295     default:
11296       oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
11297       return;
11298     }
11299   oappend_maybe_intel (ins, names[reg]);
11300 }
11301
11302 static void
11303 OP_E_memory (instr_info *ins, int bytemode, int sizeflag)
11304 {
11305   bfd_vma disp = 0;
11306   int add = (ins->rex & REX_B) ? 8 : 0;
11307   int riprel = 0;
11308   int shift;
11309
11310   if (ins->vex.evex)
11311     {
11312       switch (bytemode)
11313         {
11314         case dw_mode:
11315         case w_mode:
11316         case w_swap_mode:
11317           shift = 1;
11318           break;
11319         case db_mode:
11320         case b_mode:
11321           shift = 0;
11322           break;
11323         case dq_mode:
11324           if (ins->address_mode != mode_64bit)
11325             {
11326         case d_mode:
11327         case d_swap_mode:
11328               shift = 2;
11329               break;
11330             }
11331             /* fall through */
11332         case vex_vsib_d_w_dq_mode:
11333         case vex_vsib_q_w_dq_mode:
11334         case evex_x_gscat_mode:
11335           shift = ins->vex.w ? 3 : 2;
11336           break;
11337         case xh_mode:
11338         case evex_half_bcst_xmmqh_mode:
11339         case evex_half_bcst_xmmqdh_mode:
11340           if (ins->vex.b)
11341             {
11342               shift = ins->vex.w ? 2 : 1;
11343               break;
11344             }
11345           /* Fall through.  */
11346         case x_mode:
11347         case evex_half_bcst_xmmq_mode:
11348           if (ins->vex.b)
11349             {
11350               shift = ins->vex.w ? 3 : 2;
11351               break;
11352             }
11353           /* Fall through.  */
11354         case xmmqd_mode:
11355         case xmmdw_mode:
11356         case xmmq_mode:
11357         case ymmq_mode:
11358         case evex_x_nobcst_mode:
11359         case x_swap_mode:
11360           switch (ins->vex.length)
11361             {
11362             case 128:
11363               shift = 4;
11364               break;
11365             case 256:
11366               shift = 5;
11367               break;
11368             case 512:
11369               shift = 6;
11370               break;
11371             default:
11372               abort ();
11373             }
11374           /* Make necessary corrections to shift for modes that need it.  */
11375           if (bytemode == xmmq_mode
11376               || bytemode == evex_half_bcst_xmmqh_mode
11377               || bytemode == evex_half_bcst_xmmq_mode
11378               || (bytemode == ymmq_mode && ins->vex.length == 128))
11379             shift -= 1;
11380           else if (bytemode == xmmqd_mode
11381                    || bytemode == evex_half_bcst_xmmqdh_mode)
11382             shift -= 2;
11383           else if (bytemode == xmmdw_mode)
11384             shift -= 3;
11385           break;
11386         case ymm_mode:
11387           shift = 5;
11388           break;
11389         case xmm_mode:
11390           shift = 4;
11391           break;
11392         case q_mode:
11393         case q_swap_mode:
11394           shift = 3;
11395           break;
11396         case bw_unit_mode:
11397           shift = ins->vex.w ? 1 : 0;
11398           break;
11399         default:
11400           abort ();
11401         }
11402     }
11403   else
11404     shift = 0;
11405
11406   USED_REX (REX_B);
11407   if (ins->intel_syntax)
11408     intel_operand_size (ins, bytemode, sizeflag);
11409   append_seg (ins);
11410
11411   if ((sizeflag & AFLAG) || ins->address_mode == mode_64bit)
11412     {
11413       /* 32/64 bit address mode */
11414       int havedisp;
11415       int havebase;
11416       int needindex;
11417       int needaddr32;
11418       int base, rbase;
11419       int vindex = 0;
11420       int scale = 0;
11421       int addr32flag = !((sizeflag & AFLAG)
11422                          || bytemode == v_bnd_mode
11423                          || bytemode == v_bndmk_mode
11424                          || bytemode == bnd_mode
11425                          || bytemode == bnd_swap_mode);
11426       bool check_gather = false;
11427       const char *const *indexes = NULL;
11428
11429       havebase = 1;
11430       base = ins->modrm.rm;
11431
11432       if (base == 4)
11433         {
11434           vindex = ins->sib.index;
11435           USED_REX (REX_X);
11436           if (ins->rex & REX_X)
11437             vindex += 8;
11438           switch (bytemode)
11439             {
11440             case vex_vsib_d_w_dq_mode:
11441             case vex_vsib_q_w_dq_mode:
11442               if (!ins->need_vex)
11443                 abort ();
11444               if (ins->vex.evex)
11445                 {
11446                   if (!ins->vex.v)
11447                     vindex += 16;
11448                   check_gather = ins->obufp == ins->op_out[1];
11449                 }
11450
11451               switch (ins->vex.length)
11452                 {
11453                 case 128:
11454                   indexes = att_names_xmm;
11455                   break;
11456                 case 256:
11457                   if (!ins->vex.w
11458                       || bytemode == vex_vsib_q_w_dq_mode)
11459                     indexes = att_names_ymm;
11460                   else
11461                     indexes = att_names_xmm;
11462                   break;
11463                 case 512:
11464                   if (!ins->vex.w
11465                       || bytemode == vex_vsib_q_w_dq_mode)
11466                     indexes = att_names_zmm;
11467                   else
11468                     indexes = att_names_ymm;
11469                   break;
11470                 default:
11471                   abort ();
11472                 }
11473               break;
11474             default:
11475               if (vindex != 4)
11476                 indexes = ins->address_mode == mode_64bit && !addr32flag
11477                           ? att_names64 : att_names32;
11478               break;
11479             }
11480           scale = ins->sib.scale;
11481           base = ins->sib.base;
11482           ins->codep++;
11483         }
11484       else
11485         {
11486           /* Check for mandatory SIB.  */
11487           if (bytemode == vex_vsib_d_w_dq_mode
11488               || bytemode == vex_vsib_q_w_dq_mode
11489               || bytemode == vex_sibmem_mode)
11490             {
11491               oappend (ins, "(bad)");
11492               return;
11493             }
11494         }
11495       rbase = base + add;
11496
11497       switch (ins->modrm.mod)
11498         {
11499         case 0:
11500           if (base == 5)
11501             {
11502               havebase = 0;
11503               if (ins->address_mode == mode_64bit && !ins->has_sib)
11504                 riprel = 1;
11505               disp = get32s (ins);
11506               if (riprel && bytemode == v_bndmk_mode)
11507                 {
11508                   oappend (ins, "(bad)");
11509                   return;
11510                 }
11511             }
11512           break;
11513         case 1:
11514           FETCH_DATA (ins->info, ins->codep + 1);
11515           disp = *ins->codep++;
11516           if ((disp & 0x80) != 0)
11517             disp -= 0x100;
11518           if (ins->vex.evex && shift > 0)
11519             disp <<= shift;
11520           break;
11521         case 2:
11522           disp = get32s (ins);
11523           break;
11524         }
11525
11526       needindex = 0;
11527       needaddr32 = 0;
11528       if (ins->has_sib
11529           && !havebase
11530           && !indexes
11531           && ins->address_mode != mode_16bit)
11532         {
11533           if (ins->address_mode == mode_64bit)
11534             {
11535               if (addr32flag)
11536                 {
11537                   /* Without base nor index registers, zero-extend the
11538                      lower 32-bit displacement to 64 bits.  */
11539                   disp = (unsigned int) disp;
11540                   needindex = 1;
11541                 }
11542               needaddr32 = 1;
11543             }
11544           else
11545             {
11546               /* In 32-bit mode, we need index register to tell [offset]
11547                  from [eiz*1 + offset].  */
11548               needindex = 1;
11549             }
11550         }
11551
11552       havedisp = (havebase
11553                   || needindex
11554                   || (ins->has_sib && (indexes || scale != 0)));
11555
11556       if (!ins->intel_syntax)
11557         if (ins->modrm.mod != 0 || base == 5)
11558           {
11559             if (havedisp || riprel)
11560               print_displacement (ins, ins->scratchbuf, disp);
11561             else
11562               print_operand_value (ins, ins->scratchbuf, 1, disp);
11563             oappend (ins, ins->scratchbuf);
11564             if (riprel)
11565               {
11566                 set_op (ins, disp, 1);
11567                 oappend (ins, !addr32flag ? "(%rip)" : "(%eip)");
11568               }
11569           }
11570
11571       if ((havebase || indexes || needindex || needaddr32 || riprel)
11572           && (ins->address_mode != mode_64bit
11573               || ((bytemode != v_bnd_mode)
11574                   && (bytemode != v_bndmk_mode)
11575                   && (bytemode != bnd_mode)
11576                   && (bytemode != bnd_swap_mode))))
11577         ins->used_prefixes |= PREFIX_ADDR;
11578
11579       if (havedisp || (ins->intel_syntax && riprel))
11580         {
11581           *ins->obufp++ = ins->open_char;
11582           if (ins->intel_syntax && riprel)
11583             {
11584               set_op (ins, disp, 1);
11585               oappend (ins, !addr32flag ? "rip" : "eip");
11586             }
11587           *ins->obufp = '\0';
11588           if (havebase)
11589             oappend_maybe_intel (ins,
11590                                  (ins->address_mode == mode_64bit && !addr32flag
11591                                   ? att_names64 : att_names32)[rbase]);
11592           if (ins->has_sib)
11593             {
11594               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
11595                  print index to tell base + index from base.  */
11596               if (scale != 0
11597                   || needindex
11598                   || indexes
11599                   || (havebase && base != ESP_REG_NUM))
11600                 {
11601                   if (!ins->intel_syntax || havebase)
11602                     {
11603                       *ins->obufp++ = ins->separator_char;
11604                       *ins->obufp = '\0';
11605                     }
11606                   if (indexes)
11607                     {
11608                       if (ins->address_mode == mode_64bit || vindex < 16)
11609                         oappend_maybe_intel (ins, indexes[vindex]);
11610                       else
11611                         oappend (ins, "(bad)");
11612                     }
11613                   else
11614                     oappend_maybe_intel (ins,
11615                                          ins->address_mode == mode_64bit
11616                                          && !addr32flag ? att_index64
11617                                                         : att_index32);
11618
11619                   *ins->obufp++ = ins->scale_char;
11620                   *ins->obufp = '\0';
11621                   sprintf (ins->scratchbuf, "%d", 1 << scale);
11622                   oappend (ins, ins->scratchbuf);
11623                 }
11624             }
11625           if (ins->intel_syntax
11626               && (disp || ins->modrm.mod != 0 || base == 5))
11627             {
11628               if (!havedisp || (bfd_signed_vma) disp >= 0)
11629                 {
11630                   *ins->obufp++ = '+';
11631                   *ins->obufp = '\0';
11632                 }
11633               else if (ins->modrm.mod != 1 && disp != -disp)
11634                 {
11635                   *ins->obufp++ = '-';
11636                   *ins->obufp = '\0';
11637                   disp = -disp;
11638                 }
11639
11640               if (havedisp)
11641                 print_displacement (ins, ins->scratchbuf, disp);
11642               else
11643                 print_operand_value (ins, ins->scratchbuf, 1, disp);
11644               oappend (ins, ins->scratchbuf);
11645             }
11646
11647           *ins->obufp++ = ins->close_char;
11648           *ins->obufp = '\0';
11649
11650           if (check_gather)
11651             {
11652               /* Both XMM/YMM/ZMM registers must be distinct.  */
11653               int modrm_reg = ins->modrm.reg;
11654
11655               if (ins->rex & REX_R)
11656                 modrm_reg += 8;
11657               if (!ins->vex.r)
11658                 modrm_reg += 16;
11659               if (vindex == modrm_reg)
11660                 oappend (ins, "/(bad)");
11661             }
11662         }
11663       else if (ins->intel_syntax)
11664         {
11665           if (ins->modrm.mod != 0 || base == 5)
11666             {
11667               if (!ins->active_seg_prefix)
11668                 {
11669                   oappend_maybe_intel (ins, att_names_seg[ds_reg - es_reg]);
11670                   oappend (ins, ":");
11671                 }
11672               print_operand_value (ins, ins->scratchbuf, 1, disp);
11673               oappend (ins, ins->scratchbuf);
11674             }
11675         }
11676     }
11677   else if (bytemode == v_bnd_mode
11678            || bytemode == v_bndmk_mode
11679            || bytemode == bnd_mode
11680            || bytemode == bnd_swap_mode
11681            || bytemode == vex_vsib_d_w_dq_mode
11682            || bytemode == vex_vsib_q_w_dq_mode)
11683     {
11684       oappend (ins, "(bad)");
11685       return;
11686     }
11687   else
11688     {
11689       /* 16 bit address mode */
11690       ins->used_prefixes |= ins->prefixes & PREFIX_ADDR;
11691       switch (ins->modrm.mod)
11692         {
11693         case 0:
11694           if (ins->modrm.rm == 6)
11695             {
11696               disp = get16 (ins);
11697               if ((disp & 0x8000) != 0)
11698                 disp -= 0x10000;
11699             }
11700           break;
11701         case 1:
11702           FETCH_DATA (ins->info, ins->codep + 1);
11703           disp = *ins->codep++;
11704           if ((disp & 0x80) != 0)
11705             disp -= 0x100;
11706           if (ins->vex.evex && shift > 0)
11707             disp <<= shift;
11708           break;
11709         case 2:
11710           disp = get16 (ins);
11711           if ((disp & 0x8000) != 0)
11712             disp -= 0x10000;
11713           break;
11714         }
11715
11716       if (!ins->intel_syntax)
11717         if (ins->modrm.mod != 0 || ins->modrm.rm == 6)
11718           {
11719             print_displacement (ins, ins->scratchbuf, disp);
11720             oappend (ins, ins->scratchbuf);
11721           }
11722
11723       if (ins->modrm.mod != 0 || ins->modrm.rm != 6)
11724         {
11725           *ins->obufp++ = ins->open_char;
11726           *ins->obufp = '\0';
11727           oappend (ins,
11728                    (ins->intel_syntax ? intel_index16
11729                                       : att_index16)[ins->modrm.rm]);
11730           if (ins->intel_syntax
11731               && (disp || ins->modrm.mod != 0 || ins->modrm.rm == 6))
11732             {
11733               if ((bfd_signed_vma) disp >= 0)
11734                 {
11735                   *ins->obufp++ = '+';
11736                   *ins->obufp = '\0';
11737                 }
11738               else if (ins->modrm.mod != 1)
11739                 {
11740                   *ins->obufp++ = '-';
11741                   *ins->obufp = '\0';
11742                   disp = -disp;
11743                 }
11744
11745               print_displacement (ins, ins->scratchbuf, disp);
11746               oappend (ins, ins->scratchbuf);
11747             }
11748
11749           *ins->obufp++ = ins->close_char;
11750           *ins->obufp = '\0';
11751         }
11752       else if (ins->intel_syntax)
11753         {
11754           if (!ins->active_seg_prefix)
11755             {
11756               oappend_maybe_intel (ins, att_names_seg[ds_reg - es_reg]);
11757               oappend (ins, ":");
11758             }
11759           print_operand_value (ins, ins->scratchbuf, 1, disp & 0xffff);
11760           oappend (ins, ins->scratchbuf);
11761         }
11762     }
11763   if (ins->vex.b)
11764     {
11765       ins->evex_used |= EVEX_b_used;
11766
11767       /* Broadcast can only ever be valid for memory sources.  */
11768       if (ins->obufp == ins->op_out[0])
11769         ins->vex.no_broadcast = true;
11770
11771       if (!ins->vex.no_broadcast)
11772         {
11773           if (bytemode == xh_mode)
11774             {
11775               if (ins->vex.w)
11776                 oappend (ins, "{bad}");
11777               else
11778                 {
11779                   switch (ins->vex.length)
11780                     {
11781                     case 128:
11782                       oappend (ins, "{1to8}");
11783                       break;
11784                     case 256:
11785                       oappend (ins, "{1to16}");
11786                       break;
11787                     case 512:
11788                       oappend (ins, "{1to32}");
11789                       break;
11790                     default:
11791                       abort ();
11792                     }
11793                 }
11794             }
11795           else if (bytemode == q_mode
11796                    || bytemode == ymmq_mode)
11797             ins->vex.no_broadcast = true;
11798           else if (ins->vex.w
11799                    || bytemode == evex_half_bcst_xmmqdh_mode
11800                    || bytemode == evex_half_bcst_xmmq_mode)
11801             {
11802               switch (ins->vex.length)
11803                 {
11804                 case 128:
11805                   oappend (ins, "{1to2}");
11806                   break;
11807                 case 256:
11808                   oappend (ins, "{1to4}");
11809                   break;
11810                 case 512:
11811                   oappend (ins, "{1to8}");
11812                   break;
11813                 default:
11814                   abort ();
11815                 }
11816             }
11817           else if (bytemode == x_mode
11818                    || bytemode == evex_half_bcst_xmmqh_mode)
11819             {
11820               switch (ins->vex.length)
11821                 {
11822                 case 128:
11823                   oappend (ins, "{1to4}");
11824                   break;
11825                 case 256:
11826                   oappend (ins, "{1to8}");
11827                   break;
11828                 case 512:
11829                   oappend (ins, "{1to16}");
11830                   break;
11831                 default:
11832                   abort ();
11833                 }
11834             }
11835           else
11836             ins->vex.no_broadcast = true;
11837         }
11838       if (ins->vex.no_broadcast)
11839         oappend (ins, "{bad}");
11840     }
11841 }
11842
11843 static void
11844 OP_E (instr_info *ins, int bytemode, int sizeflag)
11845 {
11846   /* Skip mod/rm byte.  */
11847   MODRM_CHECK;
11848   ins->codep++;
11849
11850   if (ins->modrm.mod == 3)
11851     {
11852       if ((sizeflag & SUFFIX_ALWAYS)
11853           && (bytemode == b_swap_mode
11854               || bytemode == bnd_swap_mode
11855               || bytemode == v_swap_mode))
11856         swap_operand (ins);
11857
11858       print_register (ins, ins->modrm.rm, REX_B, bytemode, sizeflag);
11859     }
11860   else
11861     OP_E_memory (ins, bytemode, sizeflag);
11862 }
11863
11864 static void
11865 OP_G (instr_info *ins, int bytemode, int sizeflag)
11866 {
11867   if (ins->vex.evex && !ins->vex.r && ins->address_mode == mode_64bit)
11868     {
11869       oappend (ins, "(bad)");
11870       return;
11871     }
11872
11873   print_register (ins, ins->modrm.reg, REX_R, bytemode, sizeflag);
11874 }
11875
11876 #ifdef BFD64
11877 static bfd_vma
11878 get64 (instr_info *ins)
11879 {
11880   bfd_vma x;
11881   unsigned int a;
11882   unsigned int b;
11883
11884   FETCH_DATA (ins->info, ins->codep + 8);
11885   a = *ins->codep++ & 0xff;
11886   a |= (*ins->codep++ & 0xff) << 8;
11887   a |= (*ins->codep++ & 0xff) << 16;
11888   a |= (*ins->codep++ & 0xffu) << 24;
11889   b = *ins->codep++ & 0xff;
11890   b |= (*ins->codep++ & 0xff) << 8;
11891   b |= (*ins->codep++ & 0xff) << 16;
11892   b |= (*ins->codep++ & 0xffu) << 24;
11893   x = a + ((bfd_vma) b << 32);
11894   return x;
11895 }
11896 #else
11897 static bfd_vma
11898 get64 (instr_info *ins ATTRIBUTE_UNUSED)
11899 {
11900   abort ();
11901   return 0;
11902 }
11903 #endif
11904
11905 static bfd_signed_vma
11906 get32 (instr_info *ins)
11907 {
11908   bfd_vma x = 0;
11909
11910   FETCH_DATA (ins->info, ins->codep + 4);
11911   x = *ins->codep++ & (bfd_vma) 0xff;
11912   x |= (*ins->codep++ & (bfd_vma) 0xff) << 8;
11913   x |= (*ins->codep++ & (bfd_vma) 0xff) << 16;
11914   x |= (*ins->codep++ & (bfd_vma) 0xff) << 24;
11915   return x;
11916 }
11917
11918 static bfd_signed_vma
11919 get32s (instr_info *ins)
11920 {
11921   bfd_vma x = 0;
11922
11923   FETCH_DATA (ins->info, ins->codep + 4);
11924   x = *ins->codep++ & (bfd_vma) 0xff;
11925   x |= (*ins->codep++ & (bfd_vma) 0xff) << 8;
11926   x |= (*ins->codep++ & (bfd_vma) 0xff) << 16;
11927   x |= (*ins->codep++ & (bfd_vma) 0xff) << 24;
11928
11929   x = (x ^ ((bfd_vma) 1 << 31)) - ((bfd_vma) 1 << 31);
11930
11931   return x;
11932 }
11933
11934 static int
11935 get16 (instr_info *ins)
11936 {
11937   int x = 0;
11938
11939   FETCH_DATA (ins->info, ins->codep + 2);
11940   x = *ins->codep++ & 0xff;
11941   x |= (*ins->codep++ & 0xff) << 8;
11942   return x;
11943 }
11944
11945 static void
11946 set_op (instr_info *ins, bfd_vma op, int riprel)
11947 {
11948   ins->op_index[ins->op_ad] = ins->op_ad;
11949   if (ins->address_mode == mode_64bit)
11950     {
11951       ins->op_address[ins->op_ad] = op;
11952       ins->op_riprel[ins->op_ad] = riprel;
11953     }
11954   else
11955     {
11956       /* Mask to get a 32-bit address.  */
11957       ins->op_address[ins->op_ad] = op & 0xffffffff;
11958       ins->op_riprel[ins->op_ad] = riprel & 0xffffffff;
11959     }
11960 }
11961
11962 static void
11963 OP_REG (instr_info *ins, int code, int sizeflag)
11964 {
11965   const char *s;
11966   int add;
11967
11968   switch (code)
11969     {
11970     case es_reg: case ss_reg: case cs_reg:
11971     case ds_reg: case fs_reg: case gs_reg:
11972       oappend_maybe_intel (ins, att_names_seg[code - es_reg]);
11973       return;
11974     }
11975
11976   USED_REX (REX_B);
11977   if (ins->rex & REX_B)
11978     add = 8;
11979   else
11980     add = 0;
11981
11982   switch (code)
11983     {
11984     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
11985     case sp_reg: case bp_reg: case si_reg: case di_reg:
11986       s = att_names16[code - ax_reg + add];
11987       break;
11988     case ah_reg: case ch_reg: case dh_reg: case bh_reg:
11989       USED_REX (0);
11990       /* Fall through.  */
11991     case al_reg: case cl_reg: case dl_reg: case bl_reg:
11992       if (ins->rex)
11993         s = att_names8rex[code - al_reg + add];
11994       else
11995         s = att_names8[code - al_reg];
11996       break;
11997     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
11998     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
11999       if (ins->address_mode == mode_64bit
12000           && ((sizeflag & DFLAG) || (ins->rex & REX_W)))
12001         {
12002           s = att_names64[code - rAX_reg + add];
12003           break;
12004         }
12005       code += eAX_reg - rAX_reg;
12006       /* Fall through.  */
12007     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
12008     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
12009       USED_REX (REX_W);
12010       if (ins->rex & REX_W)
12011         s = att_names64[code - eAX_reg + add];
12012       else
12013         {
12014           if (sizeflag & DFLAG)
12015             s = att_names32[code - eAX_reg + add];
12016           else
12017             s = att_names16[code - eAX_reg + add];
12018           ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12019         }
12020       break;
12021     default:
12022       oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12023       return;
12024     }
12025   oappend_maybe_intel (ins, s);
12026 }
12027
12028 static void
12029 OP_IMREG (instr_info *ins, int code, int sizeflag)
12030 {
12031   const char *s;
12032
12033   switch (code)
12034     {
12035     case indir_dx_reg:
12036       if (!ins->intel_syntax)
12037         {
12038           oappend (ins, "(%dx)");
12039           return;
12040         }
12041       s = att_names16[dx_reg - ax_reg];
12042       break;
12043     case al_reg: case cl_reg:
12044       s = att_names8[code - al_reg];
12045       break;
12046     case eAX_reg:
12047       USED_REX (REX_W);
12048       if (ins->rex & REX_W)
12049         {
12050           s = *att_names64;
12051           break;
12052         }
12053       /* Fall through.  */
12054     case z_mode_ax_reg:
12055       if ((ins->rex & REX_W) || (sizeflag & DFLAG))
12056         s = *att_names32;
12057       else
12058         s = *att_names16;
12059       if (!(ins->rex & REX_W))
12060         ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12061       break;
12062     default:
12063       oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12064       return;
12065     }
12066   oappend_maybe_intel (ins, s);
12067 }
12068
12069 static void
12070 OP_I (instr_info *ins, int bytemode, int sizeflag)
12071 {
12072   bfd_signed_vma op;
12073   bfd_signed_vma mask = -1;
12074
12075   switch (bytemode)
12076     {
12077     case b_mode:
12078       FETCH_DATA (ins->info, ins->codep + 1);
12079       op = *ins->codep++;
12080       mask = 0xff;
12081       break;
12082     case v_mode:
12083       USED_REX (REX_W);
12084       if (ins->rex & REX_W)
12085         op = get32s (ins);
12086       else
12087         {
12088           if (sizeflag & DFLAG)
12089             {
12090               op = get32 (ins);
12091               mask = 0xffffffff;
12092             }
12093           else
12094             {
12095               op = get16 (ins);
12096               mask = 0xfffff;
12097             }
12098           ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12099         }
12100       break;
12101     case d_mode:
12102       mask = 0xffffffff;
12103       op = get32 (ins);
12104       break;
12105     case w_mode:
12106       mask = 0xfffff;
12107       op = get16 (ins);
12108       break;
12109     case const_1_mode:
12110       if (ins->intel_syntax)
12111         oappend (ins, "1");
12112       return;
12113     default:
12114       oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12115       return;
12116     }
12117
12118   op &= mask;
12119   ins->scratchbuf[0] = '$';
12120   print_operand_value (ins, ins->scratchbuf + 1, 1, op);
12121   oappend_maybe_intel (ins, ins->scratchbuf);
12122   ins->scratchbuf[0] = '\0';
12123 }
12124
12125 static void
12126 OP_I64 (instr_info *ins, int bytemode, int sizeflag)
12127 {
12128   if (bytemode != v_mode || ins->address_mode != mode_64bit
12129       || !(ins->rex & REX_W))
12130     {
12131       OP_I (ins, bytemode, sizeflag);
12132       return;
12133     }
12134
12135   USED_REX (REX_W);
12136
12137   ins->scratchbuf[0] = '$';
12138   print_operand_value (ins, ins->scratchbuf + 1, 1, get64 (ins));
12139   oappend_maybe_intel (ins, ins->scratchbuf);
12140   ins->scratchbuf[0] = '\0';
12141 }
12142
12143 static void
12144 OP_sI (instr_info *ins, int bytemode, int sizeflag)
12145 {
12146   bfd_signed_vma op;
12147
12148   switch (bytemode)
12149     {
12150     case b_mode:
12151     case b_T_mode:
12152       FETCH_DATA (ins->info, ins->codep + 1);
12153       op = *ins->codep++;
12154       if ((op & 0x80) != 0)
12155         op -= 0x100;
12156       if (bytemode == b_T_mode)
12157         {
12158           if (ins->address_mode != mode_64bit
12159               || !((sizeflag & DFLAG) || (ins->rex & REX_W)))
12160             {
12161               /* The operand-size prefix is overridden by a REX prefix.  */
12162               if ((sizeflag & DFLAG) || (ins->rex & REX_W))
12163                 op &= 0xffffffff;
12164               else
12165                 op &= 0xffff;
12166           }
12167         }
12168       else
12169         {
12170           if (!(ins->rex & REX_W))
12171             {
12172               if (sizeflag & DFLAG)
12173                 op &= 0xffffffff;
12174               else
12175                 op &= 0xffff;
12176             }
12177         }
12178       break;
12179     case v_mode:
12180       /* The operand-size prefix is overridden by a REX prefix.  */
12181       if ((sizeflag & DFLAG) || (ins->rex & REX_W))
12182         op = get32s (ins);
12183       else
12184         op = get16 (ins);
12185       break;
12186     default:
12187       oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12188       return;
12189     }
12190
12191   ins->scratchbuf[0] = '$';
12192   print_operand_value (ins, ins->scratchbuf + 1, 1, op);
12193   oappend_maybe_intel (ins, ins->scratchbuf);
12194 }
12195
12196 static void
12197 OP_J (instr_info *ins, int bytemode, int sizeflag)
12198 {
12199   bfd_vma disp;
12200   bfd_vma mask = -1;
12201   bfd_vma segment = 0;
12202
12203   switch (bytemode)
12204     {
12205     case b_mode:
12206       FETCH_DATA (ins->info, ins->codep + 1);
12207       disp = *ins->codep++;
12208       if ((disp & 0x80) != 0)
12209         disp -= 0x100;
12210       break;
12211     case v_mode:
12212     case dqw_mode:
12213       if ((sizeflag & DFLAG)
12214           || (ins->address_mode == mode_64bit
12215               && ((ins->isa64 == intel64 && bytemode != dqw_mode)
12216                   || (ins->rex & REX_W))))
12217         disp = get32s (ins);
12218       else
12219         {
12220           disp = get16 (ins);
12221           if ((disp & 0x8000) != 0)
12222             disp -= 0x10000;
12223           /* In 16bit mode, address is wrapped around at 64k within
12224              the same segment.  Otherwise, a data16 prefix on a jump
12225              instruction means that the pc is masked to 16 bits after
12226              the displacement is added!  */
12227           mask = 0xffff;
12228           if ((ins->prefixes & PREFIX_DATA) == 0)
12229             segment = ((ins->start_pc + (ins->codep - ins->start_codep))
12230                        & ~((bfd_vma) 0xffff));
12231         }
12232       if (ins->address_mode != mode_64bit
12233           || (ins->isa64 != intel64 && !(ins->rex & REX_W)))
12234         ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12235       break;
12236     default:
12237       oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12238       return;
12239     }
12240   disp = ((ins->start_pc + (ins->codep - ins->start_codep) + disp) & mask)
12241          | segment;
12242   set_op (ins, disp, 0);
12243   print_operand_value (ins, ins->scratchbuf, 1, disp);
12244   oappend (ins, ins->scratchbuf);
12245 }
12246
12247 static void
12248 OP_SEG (instr_info *ins, int bytemode, int sizeflag)
12249 {
12250   if (bytemode == w_mode)
12251     oappend_maybe_intel (ins, att_names_seg[ins->modrm.reg]);
12252   else
12253     OP_E (ins, ins->modrm.mod == 3 ? bytemode : w_mode, sizeflag);
12254 }
12255
12256 static void
12257 OP_DIR (instr_info *ins, int dummy ATTRIBUTE_UNUSED, int sizeflag)
12258 {
12259   int seg, offset;
12260
12261   if (sizeflag & DFLAG)
12262     {
12263       offset = get32 (ins);
12264       seg = get16 (ins);
12265     }
12266   else
12267     {
12268       offset = get16 (ins);
12269       seg = get16 (ins);
12270     }
12271   ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12272   if (ins->intel_syntax)
12273     sprintf (ins->scratchbuf, "0x%x:0x%x", seg, offset);
12274   else
12275     sprintf (ins->scratchbuf, "$0x%x,$0x%x", seg, offset);
12276   oappend (ins, ins->scratchbuf);
12277 }
12278
12279 static void
12280 OP_OFF (instr_info *ins, int bytemode, int sizeflag)
12281 {
12282   bfd_vma off;
12283
12284   if (ins->intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12285     intel_operand_size (ins, bytemode, sizeflag);
12286   append_seg (ins);
12287
12288   if ((sizeflag & AFLAG) || ins->address_mode == mode_64bit)
12289     off = get32 (ins);
12290   else
12291     off = get16 (ins);
12292
12293   if (ins->intel_syntax)
12294     {
12295       if (!ins->active_seg_prefix)
12296         {
12297           oappend_maybe_intel (ins, att_names_seg[ds_reg - es_reg]);
12298           oappend (ins, ":");
12299         }
12300     }
12301   print_operand_value (ins, ins->scratchbuf, 1, off);
12302   oappend (ins, ins->scratchbuf);
12303 }
12304
12305 static void
12306 OP_OFF64 (instr_info *ins, int bytemode, int sizeflag)
12307 {
12308   bfd_vma off;
12309
12310   if (ins->address_mode != mode_64bit
12311       || (ins->prefixes & PREFIX_ADDR))
12312     {
12313       OP_OFF (ins, bytemode, sizeflag);
12314       return;
12315     }
12316
12317   if (ins->intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12318     intel_operand_size (ins, bytemode, sizeflag);
12319   append_seg (ins);
12320
12321   off = get64 (ins);
12322
12323   if (ins->intel_syntax)
12324     {
12325       if (!ins->active_seg_prefix)
12326         {
12327           oappend_maybe_intel (ins, att_names_seg[ds_reg - es_reg]);
12328           oappend (ins, ":");
12329         }
12330     }
12331   print_operand_value (ins, ins->scratchbuf, 1, off);
12332   oappend (ins, ins->scratchbuf);
12333 }
12334
12335 static void
12336 ptr_reg (instr_info *ins, int code, int sizeflag)
12337 {
12338   const char *s;
12339
12340   *ins->obufp++ = ins->open_char;
12341   ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR);
12342   if (ins->address_mode == mode_64bit)
12343     {
12344       if (!(sizeflag & AFLAG))
12345         s = att_names32[code - eAX_reg];
12346       else
12347         s = att_names64[code - eAX_reg];
12348     }
12349   else if (sizeflag & AFLAG)
12350     s = att_names32[code - eAX_reg];
12351   else
12352     s = att_names16[code - eAX_reg];
12353   oappend_maybe_intel (ins, s);
12354   *ins->obufp++ = ins->close_char;
12355   *ins->obufp = 0;
12356 }
12357
12358 static void
12359 OP_ESreg (instr_info *ins, int code, int sizeflag)
12360 {
12361   if (ins->intel_syntax)
12362     {
12363       switch (ins->codep[-1])
12364         {
12365         case 0x6d:      /* insw/insl */
12366           intel_operand_size (ins, z_mode, sizeflag);
12367           break;
12368         case 0xa5:      /* movsw/movsl/movsq */
12369         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
12370         case 0xab:      /* stosw/stosl */
12371         case 0xaf:      /* scasw/scasl */
12372           intel_operand_size (ins, v_mode, sizeflag);
12373           break;
12374         default:
12375           intel_operand_size (ins, b_mode, sizeflag);
12376         }
12377     }
12378   oappend_maybe_intel (ins, "%es:");
12379   ptr_reg (ins, code, sizeflag);
12380 }
12381
12382 static void
12383 OP_DSreg (instr_info *ins, int code, int sizeflag)
12384 {
12385   if (ins->intel_syntax)
12386     {
12387       switch (ins->codep[-1])
12388         {
12389         case 0x6f:      /* outsw/outsl */
12390           intel_operand_size (ins, z_mode, sizeflag);
12391           break;
12392         case 0xa5:      /* movsw/movsl/movsq */
12393         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
12394         case 0xad:      /* lodsw/lodsl/lodsq */
12395           intel_operand_size (ins, v_mode, sizeflag);
12396           break;
12397         default:
12398           intel_operand_size (ins, b_mode, sizeflag);
12399         }
12400     }
12401   /* Set ins->active_seg_prefix to PREFIX_DS if it is unset so that the
12402      default segment register DS is printed.  */
12403   if (!ins->active_seg_prefix)
12404     ins->active_seg_prefix = PREFIX_DS;
12405   append_seg (ins);
12406   ptr_reg (ins, code, sizeflag);
12407 }
12408
12409 static void
12410 OP_C (instr_info *ins, int dummy ATTRIBUTE_UNUSED,
12411       int sizeflag ATTRIBUTE_UNUSED)
12412 {
12413   int add;
12414   if (ins->rex & REX_R)
12415     {
12416       USED_REX (REX_R);
12417       add = 8;
12418     }
12419   else if (ins->address_mode != mode_64bit && (ins->prefixes & PREFIX_LOCK))
12420     {
12421       ins->all_prefixes[ins->last_lock_prefix] = 0;
12422       ins->used_prefixes |= PREFIX_LOCK;
12423       add = 8;
12424     }
12425   else
12426     add = 0;
12427   sprintf (ins->scratchbuf, "%%cr%d", ins->modrm.reg + add);
12428   oappend_maybe_intel (ins, ins->scratchbuf);
12429 }
12430
12431 static void
12432 OP_D (instr_info *ins, int dummy ATTRIBUTE_UNUSED,
12433       int sizeflag ATTRIBUTE_UNUSED)
12434 {
12435   int add;
12436   USED_REX (REX_R);
12437   if (ins->rex & REX_R)
12438     add = 8;
12439   else
12440     add = 0;
12441   if (ins->intel_syntax)
12442     sprintf (ins->scratchbuf, "dr%d", ins->modrm.reg + add);
12443   else
12444     sprintf (ins->scratchbuf, "%%db%d", ins->modrm.reg + add);
12445   oappend (ins, ins->scratchbuf);
12446 }
12447
12448 static void
12449 OP_T (instr_info *ins, int dummy ATTRIBUTE_UNUSED,
12450       int sizeflag ATTRIBUTE_UNUSED)
12451 {
12452   sprintf (ins->scratchbuf, "%%tr%d", ins->modrm.reg);
12453   oappend_maybe_intel (ins, ins->scratchbuf);
12454 }
12455
12456 static void
12457 OP_MMX (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
12458         int sizeflag ATTRIBUTE_UNUSED)
12459 {
12460   int reg = ins->modrm.reg;
12461   const char *const *names;
12462
12463   ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12464   if (ins->prefixes & PREFIX_DATA)
12465     {
12466       names = att_names_xmm;
12467       USED_REX (REX_R);
12468       if (ins->rex & REX_R)
12469         reg += 8;
12470     }
12471   else
12472     names = att_names_mm;
12473   oappend_maybe_intel (ins, names[reg]);
12474 }
12475
12476 static void
12477 print_vector_reg (instr_info *ins, unsigned int reg, int bytemode)
12478 {
12479   const char *const *names;
12480
12481   if (bytemode == xmmq_mode
12482       || bytemode == evex_half_bcst_xmmqh_mode
12483       || bytemode == evex_half_bcst_xmmq_mode)
12484     {
12485       switch (ins->vex.length)
12486         {
12487         case 128:
12488         case 256:
12489           names = att_names_xmm;
12490           break;
12491         case 512:
12492           names = att_names_ymm;
12493           break;
12494         default:
12495           abort ();
12496         }
12497     }
12498   else if (bytemode == ymm_mode)
12499     names = att_names_ymm;
12500   else if (bytemode == tmm_mode)
12501     {
12502       if (reg >= 8)
12503         {
12504           oappend (ins, "(bad)");
12505           return;
12506         }
12507       names = att_names_tmm;
12508     }
12509   else if (ins->need_vex
12510            && bytemode != xmm_mode
12511            && bytemode != scalar_mode
12512            && bytemode != xmmdw_mode
12513            && bytemode != xmmqd_mode
12514            && bytemode != evex_half_bcst_xmmqdh_mode
12515            && bytemode != w_swap_mode
12516            && bytemode != b_mode
12517            && bytemode != w_mode
12518            && bytemode != d_mode
12519            && bytemode != q_mode)
12520     {
12521       switch (ins->vex.length)
12522         {
12523         case 128:
12524           names = att_names_xmm;
12525           break;
12526         case 256:
12527           if (ins->vex.w
12528               || bytemode != vex_vsib_q_w_dq_mode)
12529             names = att_names_ymm;
12530           else
12531             names = att_names_xmm;
12532           break;
12533         case 512:
12534           if (ins->vex.w
12535               || bytemode != vex_vsib_q_w_dq_mode)
12536             names = att_names_zmm;
12537           else
12538             names = att_names_ymm;
12539           break;
12540         default:
12541           abort ();
12542         }
12543     }
12544   else
12545     names = att_names_xmm;
12546   oappend_maybe_intel (ins, names[reg]);
12547 }
12548
12549 static void
12550 OP_XMM (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
12551 {
12552   unsigned int reg = ins->modrm.reg;
12553
12554   USED_REX (REX_R);
12555   if (ins->rex & REX_R)
12556     reg += 8;
12557   if (ins->vex.evex)
12558     {
12559       if (!ins->vex.r)
12560         reg += 16;
12561     }
12562
12563   if (bytemode == tmm_mode)
12564     ins->modrm.reg = reg;
12565   else if (bytemode == scalar_mode)
12566     ins->vex.no_broadcast = true;
12567
12568   print_vector_reg (ins, reg, bytemode);
12569 }
12570
12571 static void
12572 OP_EM (instr_info *ins, int bytemode, int sizeflag)
12573 {
12574   int reg;
12575   const char *const *names;
12576
12577   if (ins->modrm.mod != 3)
12578     {
12579       if (ins->intel_syntax
12580           && (bytemode == v_mode || bytemode == v_swap_mode))
12581         {
12582           bytemode = (ins->prefixes & PREFIX_DATA) ? x_mode : q_mode;
12583           ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12584         }
12585       OP_E (ins, bytemode, sizeflag);
12586       return;
12587     }
12588
12589   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
12590     swap_operand (ins);
12591
12592   /* Skip mod/rm byte.  */
12593   MODRM_CHECK;
12594   ins->codep++;
12595   ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12596   reg = ins->modrm.rm;
12597   if (ins->prefixes & PREFIX_DATA)
12598     {
12599       names = att_names_xmm;
12600       USED_REX (REX_B);
12601       if (ins->rex & REX_B)
12602         reg += 8;
12603     }
12604   else
12605     names = att_names_mm;
12606   oappend_maybe_intel (ins, names[reg]);
12607 }
12608
12609 /* cvt* are the only instructions in sse2 which have
12610    both SSE and MMX operands and also have 0x66 prefix
12611    in their opcode. 0x66 was originally used to differentiate
12612    between SSE and MMX instruction(operands). So we have to handle the
12613    cvt* separately using OP_EMC and OP_MXC */
12614 static void
12615 OP_EMC (instr_info *ins, int bytemode, int sizeflag)
12616 {
12617   if (ins->modrm.mod != 3)
12618     {
12619       if (ins->intel_syntax && bytemode == v_mode)
12620         {
12621           bytemode = (ins->prefixes & PREFIX_DATA) ? x_mode : q_mode;
12622           ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12623         }
12624       OP_E (ins, bytemode, sizeflag);
12625       return;
12626     }
12627
12628   /* Skip mod/rm byte.  */
12629   MODRM_CHECK;
12630   ins->codep++;
12631   ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12632   oappend_maybe_intel (ins, att_names_mm[ins->modrm.rm]);
12633 }
12634
12635 static void
12636 OP_MXC (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
12637         int sizeflag ATTRIBUTE_UNUSED)
12638 {
12639   ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12640   oappend_maybe_intel (ins, att_names_mm[ins->modrm.reg]);
12641 }
12642
12643 static void
12644 OP_EX (instr_info *ins, int bytemode, int sizeflag)
12645 {
12646   int reg;
12647
12648   /* Skip mod/rm byte.  */
12649   MODRM_CHECK;
12650   ins->codep++;
12651
12652   if (bytemode == dq_mode)
12653     bytemode = ins->vex.w ? q_mode : d_mode;
12654
12655   if (ins->modrm.mod != 3)
12656     {
12657       OP_E_memory (ins, bytemode, sizeflag);
12658       return;
12659     }
12660
12661   reg = ins->modrm.rm;
12662   USED_REX (REX_B);
12663   if (ins->rex & REX_B)
12664     reg += 8;
12665   if (ins->vex.evex)
12666     {
12667       USED_REX (REX_X);
12668       if ((ins->rex & REX_X))
12669         reg += 16;
12670     }
12671
12672   if ((sizeflag & SUFFIX_ALWAYS)
12673       && (bytemode == x_swap_mode
12674           || bytemode == w_swap_mode
12675           || bytemode == d_swap_mode
12676           || bytemode == q_swap_mode))
12677     swap_operand (ins);
12678
12679   if (bytemode == tmm_mode)
12680     ins->modrm.rm = reg;
12681
12682   print_vector_reg (ins, reg, bytemode);
12683 }
12684
12685 static void
12686 OP_MS (instr_info *ins, int bytemode, int sizeflag)
12687 {
12688   if (ins->modrm.mod == 3)
12689     OP_EM (ins, bytemode, sizeflag);
12690   else
12691     BadOp (ins);
12692 }
12693
12694 static void
12695 OP_XS (instr_info *ins, int bytemode, int sizeflag)
12696 {
12697   if (ins->modrm.mod == 3)
12698     OP_EX (ins, bytemode, sizeflag);
12699   else
12700     BadOp (ins);
12701 }
12702
12703 static void
12704 OP_M (instr_info *ins, int bytemode, int sizeflag)
12705 {
12706   if (ins->modrm.mod == 3)
12707     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
12708     BadOp (ins);
12709   else
12710     OP_E (ins, bytemode, sizeflag);
12711 }
12712
12713 static void
12714 OP_0f07 (instr_info *ins, int bytemode, int sizeflag)
12715 {
12716   if (ins->modrm.mod != 3 || ins->modrm.rm != 0)
12717     BadOp (ins);
12718   else
12719     OP_E (ins, bytemode, sizeflag);
12720 }
12721
12722 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
12723    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
12724
12725 static void
12726 NOP_Fixup (instr_info *ins, int opnd, int sizeflag)
12727 {
12728   if ((ins->prefixes & PREFIX_DATA) == 0 && (ins->rex & REX_B) == 0)
12729     strcpy (ins->obuf, "nop");
12730   else if (opnd == 0)
12731     OP_REG (ins, eAX_reg, sizeflag);
12732   else
12733     OP_IMREG (ins, eAX_reg, sizeflag);
12734 }
12735
12736 static const char *const Suffix3DNow[] = {
12737 /* 00 */        NULL,           NULL,           NULL,           NULL,
12738 /* 04 */        NULL,           NULL,           NULL,           NULL,
12739 /* 08 */        NULL,           NULL,           NULL,           NULL,
12740 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
12741 /* 10 */        NULL,           NULL,           NULL,           NULL,
12742 /* 14 */        NULL,           NULL,           NULL,           NULL,
12743 /* 18 */        NULL,           NULL,           NULL,           NULL,
12744 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
12745 /* 20 */        NULL,           NULL,           NULL,           NULL,
12746 /* 24 */        NULL,           NULL,           NULL,           NULL,
12747 /* 28 */        NULL,           NULL,           NULL,           NULL,
12748 /* 2C */        NULL,           NULL,           NULL,           NULL,
12749 /* 30 */        NULL,           NULL,           NULL,           NULL,
12750 /* 34 */        NULL,           NULL,           NULL,           NULL,
12751 /* 38 */        NULL,           NULL,           NULL,           NULL,
12752 /* 3C */        NULL,           NULL,           NULL,           NULL,
12753 /* 40 */        NULL,           NULL,           NULL,           NULL,
12754 /* 44 */        NULL,           NULL,           NULL,           NULL,
12755 /* 48 */        NULL,           NULL,           NULL,           NULL,
12756 /* 4C */        NULL,           NULL,           NULL,           NULL,
12757 /* 50 */        NULL,           NULL,           NULL,           NULL,
12758 /* 54 */        NULL,           NULL,           NULL,           NULL,
12759 /* 58 */        NULL,           NULL,           NULL,           NULL,
12760 /* 5C */        NULL,           NULL,           NULL,           NULL,
12761 /* 60 */        NULL,           NULL,           NULL,           NULL,
12762 /* 64 */        NULL,           NULL,           NULL,           NULL,
12763 /* 68 */        NULL,           NULL,           NULL,           NULL,
12764 /* 6C */        NULL,           NULL,           NULL,           NULL,
12765 /* 70 */        NULL,           NULL,           NULL,           NULL,
12766 /* 74 */        NULL,           NULL,           NULL,           NULL,
12767 /* 78 */        NULL,           NULL,           NULL,           NULL,
12768 /* 7C */        NULL,           NULL,           NULL,           NULL,
12769 /* 80 */        NULL,           NULL,           NULL,           NULL,
12770 /* 84 */        NULL,           NULL,           NULL,           NULL,
12771 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
12772 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
12773 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
12774 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
12775 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
12776 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
12777 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
12778 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
12779 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
12780 /* AC */        NULL,           NULL,           "pfacc",        NULL,
12781 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
12782 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
12783 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
12784 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
12785 /* C0 */        NULL,           NULL,           NULL,           NULL,
12786 /* C4 */        NULL,           NULL,           NULL,           NULL,
12787 /* C8 */        NULL,           NULL,           NULL,           NULL,
12788 /* CC */        NULL,           NULL,           NULL,           NULL,
12789 /* D0 */        NULL,           NULL,           NULL,           NULL,
12790 /* D4 */        NULL,           NULL,           NULL,           NULL,
12791 /* D8 */        NULL,           NULL,           NULL,           NULL,
12792 /* DC */        NULL,           NULL,           NULL,           NULL,
12793 /* E0 */        NULL,           NULL,           NULL,           NULL,
12794 /* E4 */        NULL,           NULL,           NULL,           NULL,
12795 /* E8 */        NULL,           NULL,           NULL,           NULL,
12796 /* EC */        NULL,           NULL,           NULL,           NULL,
12797 /* F0 */        NULL,           NULL,           NULL,           NULL,
12798 /* F4 */        NULL,           NULL,           NULL,           NULL,
12799 /* F8 */        NULL,           NULL,           NULL,           NULL,
12800 /* FC */        NULL,           NULL,           NULL,           NULL,
12801 };
12802
12803 static void
12804 OP_3DNowSuffix (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
12805                 int sizeflag ATTRIBUTE_UNUSED)
12806 {
12807   const char *mnemonic;
12808
12809   FETCH_DATA (ins->info, ins->codep + 1);
12810   /* AMD 3DNow! instructions are specified by an opcode suffix in the
12811      place where an 8-bit immediate would normally go.  ie. the last
12812      byte of the instruction.  */
12813   ins->obufp = ins->mnemonicendp;
12814   mnemonic = Suffix3DNow[*ins->codep++ & 0xff];
12815   if (mnemonic)
12816     oappend (ins, mnemonic);
12817   else
12818     {
12819       /* Since a variable sized ins->modrm/ins->sib chunk is between the start
12820          of the opcode (0x0f0f) and the opcode suffix, we need to do
12821          all the ins->modrm processing first, and don't know until now that
12822          we have a bad opcode.  This necessitates some cleaning up.  */
12823       ins->op_out[0][0] = '\0';
12824       ins->op_out[1][0] = '\0';
12825       BadOp (ins);
12826     }
12827   ins->mnemonicendp = ins->obufp;
12828 }
12829
12830 static const struct op simd_cmp_op[] =
12831 {
12832   { STRING_COMMA_LEN ("eq") },
12833   { STRING_COMMA_LEN ("lt") },
12834   { STRING_COMMA_LEN ("le") },
12835   { STRING_COMMA_LEN ("unord") },
12836   { STRING_COMMA_LEN ("neq") },
12837   { STRING_COMMA_LEN ("nlt") },
12838   { STRING_COMMA_LEN ("nle") },
12839   { STRING_COMMA_LEN ("ord") }
12840 };
12841
12842 static const struct op vex_cmp_op[] =
12843 {
12844   { STRING_COMMA_LEN ("eq_uq") },
12845   { STRING_COMMA_LEN ("nge") },
12846   { STRING_COMMA_LEN ("ngt") },
12847   { STRING_COMMA_LEN ("false") },
12848   { STRING_COMMA_LEN ("neq_oq") },
12849   { STRING_COMMA_LEN ("ge") },
12850   { STRING_COMMA_LEN ("gt") },
12851   { STRING_COMMA_LEN ("true") },
12852   { STRING_COMMA_LEN ("eq_os") },
12853   { STRING_COMMA_LEN ("lt_oq") },
12854   { STRING_COMMA_LEN ("le_oq") },
12855   { STRING_COMMA_LEN ("unord_s") },
12856   { STRING_COMMA_LEN ("neq_us") },
12857   { STRING_COMMA_LEN ("nlt_uq") },
12858   { STRING_COMMA_LEN ("nle_uq") },
12859   { STRING_COMMA_LEN ("ord_s") },
12860   { STRING_COMMA_LEN ("eq_us") },
12861   { STRING_COMMA_LEN ("nge_uq") },
12862   { STRING_COMMA_LEN ("ngt_uq") },
12863   { STRING_COMMA_LEN ("false_os") },
12864   { STRING_COMMA_LEN ("neq_os") },
12865   { STRING_COMMA_LEN ("ge_oq") },
12866   { STRING_COMMA_LEN ("gt_oq") },
12867   { STRING_COMMA_LEN ("true_us") },
12868 };
12869
12870 static void
12871 CMP_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
12872            int sizeflag ATTRIBUTE_UNUSED)
12873 {
12874   unsigned int cmp_type;
12875
12876   FETCH_DATA (ins->info, ins->codep + 1);
12877   cmp_type = *ins->codep++ & 0xff;
12878   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
12879     {
12880       char suffix[3];
12881       char *p = ins->mnemonicendp - 2;
12882       suffix[0] = p[0];
12883       suffix[1] = p[1];
12884       suffix[2] = '\0';
12885       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
12886       ins->mnemonicendp += simd_cmp_op[cmp_type].len;
12887     }
12888   else if (ins->need_vex
12889            && cmp_type < ARRAY_SIZE (simd_cmp_op) + ARRAY_SIZE (vex_cmp_op))
12890     {
12891       char suffix[3];
12892       char *p = ins->mnemonicendp - 2;
12893       suffix[0] = p[0];
12894       suffix[1] = p[1];
12895       suffix[2] = '\0';
12896       cmp_type -= ARRAY_SIZE (simd_cmp_op);
12897       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
12898       ins->mnemonicendp += vex_cmp_op[cmp_type].len;
12899     }
12900   else
12901     {
12902       /* We have a reserved extension byte.  Output it directly.  */
12903       ins->scratchbuf[0] = '$';
12904       print_operand_value (ins, ins->scratchbuf + 1, 1, cmp_type);
12905       oappend_maybe_intel (ins, ins->scratchbuf);
12906       ins->scratchbuf[0] = '\0';
12907     }
12908 }
12909
12910 static void
12911 OP_Mwait (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
12912 {
12913   /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx  */
12914   if (!ins->intel_syntax)
12915     {
12916       strcpy (ins->op_out[0], att_names32[0] + ins->intel_syntax);
12917       strcpy (ins->op_out[1], att_names32[1] + ins->intel_syntax);
12918       if (bytemode == eBX_reg)
12919         strcpy (ins->op_out[2], att_names32[3] + ins->intel_syntax);
12920       ins->two_source_ops = true;
12921     }
12922   /* Skip mod/rm byte.  */
12923   MODRM_CHECK;
12924   ins->codep++;
12925 }
12926
12927 static void
12928 OP_Monitor (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
12929             int sizeflag ATTRIBUTE_UNUSED)
12930 {
12931   /* monitor %{e,r,}ax,%ecx,%edx"  */
12932   if (!ins->intel_syntax)
12933     {
12934       const char *const *names = (ins->address_mode == mode_64bit
12935                                   ? att_names64 : att_names32);
12936
12937       if (ins->prefixes & PREFIX_ADDR)
12938         {
12939           /* Remove "addr16/addr32".  */
12940           ins->all_prefixes[ins->last_addr_prefix] = 0;
12941           names = (ins->address_mode != mode_32bit
12942                    ? att_names32 : att_names16);
12943           ins->used_prefixes |= PREFIX_ADDR;
12944         }
12945       else if (ins->address_mode == mode_16bit)
12946         names = att_names16;
12947       strcpy (ins->op_out[0], names[0] + ins->intel_syntax);
12948       strcpy (ins->op_out[1], att_names32[1] + ins->intel_syntax);
12949       strcpy (ins->op_out[2], att_names32[2] + ins->intel_syntax);
12950       ins->two_source_ops = true;
12951     }
12952   /* Skip mod/rm byte.  */
12953   MODRM_CHECK;
12954   ins->codep++;
12955 }
12956
12957 static void
12958 BadOp (instr_info *ins)
12959 {
12960   /* Throw away prefixes and 1st. opcode byte.  */
12961   ins->codep = ins->insn_codep + 1;
12962   oappend (ins, "(bad)");
12963 }
12964
12965 static void
12966 REP_Fixup (instr_info *ins, int bytemode, int sizeflag)
12967 {
12968   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
12969      lods and stos.  */
12970   if (ins->prefixes & PREFIX_REPZ)
12971     ins->all_prefixes[ins->last_repz_prefix] = REP_PREFIX;
12972
12973   switch (bytemode)
12974     {
12975     case al_reg:
12976     case eAX_reg:
12977     case indir_dx_reg:
12978       OP_IMREG (ins, bytemode, sizeflag);
12979       break;
12980     case eDI_reg:
12981       OP_ESreg (ins, bytemode, sizeflag);
12982       break;
12983     case eSI_reg:
12984       OP_DSreg (ins, bytemode, sizeflag);
12985       break;
12986     default:
12987       abort ();
12988       break;
12989     }
12990 }
12991
12992 static void
12993 SEP_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
12994            int sizeflag ATTRIBUTE_UNUSED)
12995 {
12996   if (ins->isa64 != amd64)
12997     return;
12998
12999   ins->obufp = ins->obuf;
13000   BadOp (ins);
13001   ins->mnemonicendp = ins->obufp;
13002   ++ins->codep;
13003 }
13004
13005 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
13006    "bnd".  */
13007
13008 static void
13009 BND_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13010            int sizeflag ATTRIBUTE_UNUSED)
13011 {
13012   if (ins->prefixes & PREFIX_REPNZ)
13013     ins->all_prefixes[ins->last_repnz_prefix] = BND_PREFIX;
13014 }
13015
13016 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
13017    "notrack".  */
13018
13019 static void
13020 NOTRACK_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13021                int sizeflag ATTRIBUTE_UNUSED)
13022 {
13023   /* Since active_seg_prefix is not set in 64-bit mode, check whether
13024      we've seen a PREFIX_DS.  */
13025   if ((ins->prefixes & PREFIX_DS) != 0
13026       && (ins->address_mode != mode_64bit || ins->last_data_prefix < 0))
13027     {
13028       /* NOTRACK prefix is only valid on indirect branch instructions.
13029          NB: DATA prefix is unsupported for Intel64.  */
13030       ins->active_seg_prefix = 0;
13031       ins->all_prefixes[ins->last_seg_prefix] = NOTRACK_PREFIX;
13032     }
13033 }
13034
13035 /* Similar to OP_E.  But the 0xf2/0xf3 ins->prefixes should be displayed as
13036    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
13037  */
13038
13039 static void
13040 HLE_Fixup1 (instr_info *ins, int bytemode, int sizeflag)
13041 {
13042   if (ins->modrm.mod != 3
13043       && (ins->prefixes & PREFIX_LOCK) != 0)
13044     {
13045       if (ins->prefixes & PREFIX_REPZ)
13046         ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13047       if (ins->prefixes & PREFIX_REPNZ)
13048         ins->all_prefixes[ins->last_repnz_prefix] = XACQUIRE_PREFIX;
13049     }
13050
13051   OP_E (ins, bytemode, sizeflag);
13052 }
13053
13054 /* Similar to OP_E.  But the 0xf2/0xf3 ins->prefixes should be displayed as
13055    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
13056  */
13057
13058 static void
13059 HLE_Fixup2 (instr_info *ins, int bytemode, int sizeflag)
13060 {
13061   if (ins->modrm.mod != 3)
13062     {
13063       if (ins->prefixes & PREFIX_REPZ)
13064         ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13065       if (ins->prefixes & PREFIX_REPNZ)
13066         ins->all_prefixes[ins->last_repnz_prefix] = XACQUIRE_PREFIX;
13067     }
13068
13069   OP_E (ins, bytemode, sizeflag);
13070 }
13071
13072 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
13073    "xrelease" for memory operand.  No check for LOCK prefix.   */
13074
13075 static void
13076 HLE_Fixup3 (instr_info *ins, int bytemode, int sizeflag)
13077 {
13078   if (ins->modrm.mod != 3
13079       && ins->last_repz_prefix > ins->last_repnz_prefix
13080       && (ins->prefixes & PREFIX_REPZ) != 0)
13081     ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13082
13083   OP_E (ins, bytemode, sizeflag);
13084 }
13085
13086 static void
13087 CMPXCHG8B_Fixup (instr_info *ins, int bytemode, int sizeflag)
13088 {
13089   USED_REX (REX_W);
13090   if (ins->rex & REX_W)
13091     {
13092       /* Change cmpxchg8b to cmpxchg16b.  */
13093       char *p = ins->mnemonicendp - 2;
13094       ins->mnemonicendp = stpcpy (p, "16b");
13095       bytemode = o_mode;
13096     }
13097   else if ((ins->prefixes & PREFIX_LOCK) != 0)
13098     {
13099       if (ins->prefixes & PREFIX_REPZ)
13100         ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13101       if (ins->prefixes & PREFIX_REPNZ)
13102         ins->all_prefixes[ins->last_repnz_prefix] = XACQUIRE_PREFIX;
13103     }
13104
13105   OP_M (ins, bytemode, sizeflag);
13106 }
13107
13108 static void
13109 XMM_Fixup (instr_info *ins, int reg, int sizeflag ATTRIBUTE_UNUSED)
13110 {
13111   const char *const *names = att_names_xmm;
13112
13113   if (ins->need_vex)
13114     {
13115       switch (ins->vex.length)
13116         {
13117         case 128:
13118           break;
13119         case 256:
13120           names = att_names_ymm;
13121           break;
13122         default:
13123           abort ();
13124         }
13125     }
13126   oappend_maybe_intel (ins, names[reg]);
13127 }
13128
13129 static void
13130 FXSAVE_Fixup (instr_info *ins, int bytemode, int sizeflag)
13131 {
13132   /* Add proper suffix to "fxsave" and "fxrstor".  */
13133   USED_REX (REX_W);
13134   if (ins->rex & REX_W)
13135     {
13136       char *p = ins->mnemonicendp;
13137       *p++ = '6';
13138       *p++ = '4';
13139       *p = '\0';
13140       ins->mnemonicendp = p;
13141     }
13142   OP_M (ins, bytemode, sizeflag);
13143 }
13144
13145 /* Display the destination register operand for instructions with
13146    VEX. */
13147
13148 static void
13149 OP_VEX (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13150 {
13151   int reg, modrm_reg, sib_index = -1;
13152   const char *const *names;
13153
13154   if (!ins->need_vex)
13155     abort ();
13156
13157   reg = ins->vex.register_specifier;
13158   ins->vex.register_specifier = 0;
13159   if (ins->address_mode != mode_64bit)
13160     {
13161       if (ins->vex.evex && !ins->vex.v)
13162         {
13163           oappend (ins, "(bad)");
13164           return;
13165         }
13166
13167       reg &= 7;
13168     }
13169   else if (ins->vex.evex && !ins->vex.v)
13170     reg += 16;
13171
13172   switch (bytemode)
13173     {
13174     case scalar_mode:
13175       oappend_maybe_intel (ins, att_names_xmm[reg]);
13176       return;
13177
13178     case vex_vsib_d_w_dq_mode:
13179     case vex_vsib_q_w_dq_mode:
13180       /* This must be the 3rd operand.  */
13181       if (ins->obufp != ins->op_out[2])
13182         abort ();
13183       if (ins->vex.length == 128
13184           || (bytemode != vex_vsib_d_w_dq_mode
13185               && !ins->vex.w))
13186         oappend_maybe_intel (ins, att_names_xmm[reg]);
13187       else
13188         oappend_maybe_intel (ins, att_names_ymm[reg]);
13189
13190       /* All 3 XMM/YMM registers must be distinct.  */
13191       modrm_reg = ins->modrm.reg;
13192       if (ins->rex & REX_R)
13193         modrm_reg += 8;
13194
13195       if (ins->has_sib && ins->modrm.rm == 4)
13196         {
13197           sib_index = ins->sib.index;
13198           if (ins->rex & REX_X)
13199             sib_index += 8;
13200         }
13201
13202       if (reg == modrm_reg || reg == sib_index)
13203         strcpy (ins->obufp, "/(bad)");
13204       if (modrm_reg == sib_index || modrm_reg == reg)
13205         strcat (ins->op_out[0], "/(bad)");
13206       if (sib_index == modrm_reg || sib_index == reg)
13207         strcat (ins->op_out[1], "/(bad)");
13208
13209       return;
13210
13211     case tmm_mode:
13212       /* All 3 TMM registers must be distinct.  */
13213       if (reg >= 8)
13214         oappend (ins, "(bad)");
13215       else
13216         {
13217           /* This must be the 3rd operand.  */
13218           if (ins->obufp != ins->op_out[2])
13219             abort ();
13220           oappend_maybe_intel (ins, att_names_tmm[reg]);
13221           if (reg == ins->modrm.reg || reg == ins->modrm.rm)
13222             strcpy (ins->obufp, "/(bad)");
13223         }
13224
13225       if (ins->modrm.reg == ins->modrm.rm || ins->modrm.reg == reg
13226           || ins->modrm.rm == reg)
13227         {
13228           if (ins->modrm.reg <= 8
13229               && (ins->modrm.reg == ins->modrm.rm || ins->modrm.reg == reg))
13230             strcat (ins->op_out[0], "/(bad)");
13231           if (ins->modrm.rm <= 8
13232               && (ins->modrm.rm == ins->modrm.reg || ins->modrm.rm == reg))
13233             strcat (ins->op_out[1], "/(bad)");
13234         }
13235
13236       return;
13237     }
13238
13239   switch (ins->vex.length)
13240     {
13241     case 128:
13242       switch (bytemode)
13243         {
13244         case x_mode:
13245           names = att_names_xmm;
13246           break;
13247         case dq_mode:
13248           if (ins->rex & REX_W)
13249             names = att_names64;
13250           else
13251             names = att_names32;
13252           break;
13253         case mask_bd_mode:
13254         case mask_mode:
13255           if (reg > 0x7)
13256             {
13257               oappend (ins, "(bad)");
13258               return;
13259             }
13260           names = att_names_mask;
13261           break;
13262         default:
13263           abort ();
13264           return;
13265         }
13266       break;
13267     case 256:
13268       switch (bytemode)
13269         {
13270         case x_mode:
13271           names = att_names_ymm;
13272           break;
13273         case mask_bd_mode:
13274         case mask_mode:
13275           if (reg > 0x7)
13276             {
13277               oappend (ins, "(bad)");
13278               return;
13279             }
13280           names = att_names_mask;
13281           break;
13282         default:
13283           /* See PR binutils/20893 for a reproducer.  */
13284           oappend (ins, "(bad)");
13285           return;
13286         }
13287       break;
13288     case 512:
13289       names = att_names_zmm;
13290       break;
13291     default:
13292       abort ();
13293       break;
13294     }
13295   oappend_maybe_intel (ins, names[reg]);
13296 }
13297
13298 static void
13299 OP_VexR (instr_info *ins, int bytemode, int sizeflag)
13300 {
13301   if (ins->modrm.mod == 3)
13302     OP_VEX (ins, bytemode, sizeflag);
13303 }
13304
13305 static void
13306 OP_VexW (instr_info *ins, int bytemode, int sizeflag)
13307 {
13308   OP_VEX (ins, bytemode, sizeflag);
13309
13310   if (ins->vex.w)
13311     {
13312       /* Swap 2nd and 3rd operands.  */
13313       strcpy (ins->scratchbuf, ins->op_out[2]);
13314       strcpy (ins->op_out[2], ins->op_out[1]);
13315       strcpy (ins->op_out[1], ins->scratchbuf);
13316     }
13317 }
13318
13319 static void
13320 OP_REG_VexI4 (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13321 {
13322   int reg;
13323   const char *const *names = att_names_xmm;
13324
13325   FETCH_DATA (ins->info, ins->codep + 1);
13326   reg = *ins->codep++;
13327
13328   if (bytemode != x_mode && bytemode != scalar_mode)
13329     abort ();
13330
13331   reg >>= 4;
13332   if (ins->address_mode != mode_64bit)
13333     reg &= 7;
13334
13335   if (bytemode == x_mode && ins->vex.length == 256)
13336     names = att_names_ymm;
13337
13338   oappend_maybe_intel (ins, names[reg]);
13339
13340   if (ins->vex.w)
13341     {
13342       /* Swap 3rd and 4th operands.  */
13343       strcpy (ins->scratchbuf, ins->op_out[3]);
13344       strcpy (ins->op_out[3], ins->op_out[2]);
13345       strcpy (ins->op_out[2], ins->scratchbuf);
13346     }
13347 }
13348
13349 static void
13350 OP_VexI4 (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13351           int sizeflag ATTRIBUTE_UNUSED)
13352 {
13353   ins->scratchbuf[0] = '$';
13354   print_operand_value (ins, ins->scratchbuf + 1, 1, ins->codep[-1] & 0xf);
13355   oappend_maybe_intel (ins, ins->scratchbuf);
13356 }
13357
13358 static void
13359 VPCMP_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13360              int sizeflag ATTRIBUTE_UNUSED)
13361 {
13362   unsigned int cmp_type;
13363
13364   if (!ins->vex.evex)
13365     abort ();
13366
13367   FETCH_DATA (ins->info, ins->codep + 1);
13368   cmp_type = *ins->codep++ & 0xff;
13369   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
13370      If it's the case, print suffix, otherwise - print the immediate.  */
13371   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
13372       && cmp_type != 3
13373       && cmp_type != 7)
13374     {
13375       char suffix[3];
13376       char *p = ins->mnemonicendp - 2;
13377
13378       /* vpcmp* can have both one- and two-lettered suffix.  */
13379       if (p[0] == 'p')
13380         {
13381           p++;
13382           suffix[0] = p[0];
13383           suffix[1] = '\0';
13384         }
13385       else
13386         {
13387           suffix[0] = p[0];
13388           suffix[1] = p[1];
13389           suffix[2] = '\0';
13390         }
13391
13392       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13393       ins->mnemonicendp += simd_cmp_op[cmp_type].len;
13394     }
13395   else
13396     {
13397       /* We have a reserved extension byte.  Output it directly.  */
13398       ins->scratchbuf[0] = '$';
13399       print_operand_value (ins, ins->scratchbuf + 1, 1, cmp_type);
13400       oappend_maybe_intel (ins, ins->scratchbuf);
13401       ins->scratchbuf[0] = '\0';
13402     }
13403 }
13404
13405 static const struct op xop_cmp_op[] =
13406 {
13407   { STRING_COMMA_LEN ("lt") },
13408   { STRING_COMMA_LEN ("le") },
13409   { STRING_COMMA_LEN ("gt") },
13410   { STRING_COMMA_LEN ("ge") },
13411   { STRING_COMMA_LEN ("eq") },
13412   { STRING_COMMA_LEN ("neq") },
13413   { STRING_COMMA_LEN ("false") },
13414   { STRING_COMMA_LEN ("true") }
13415 };
13416
13417 static void
13418 VPCOM_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13419              int sizeflag ATTRIBUTE_UNUSED)
13420 {
13421   unsigned int cmp_type;
13422
13423   FETCH_DATA (ins->info, ins->codep + 1);
13424   cmp_type = *ins->codep++ & 0xff;
13425   if (cmp_type < ARRAY_SIZE (xop_cmp_op))
13426     {
13427       char suffix[3];
13428       char *p = ins->mnemonicendp - 2;
13429
13430       /* vpcom* can have both one- and two-lettered suffix.  */
13431       if (p[0] == 'm')
13432         {
13433           p++;
13434           suffix[0] = p[0];
13435           suffix[1] = '\0';
13436         }
13437       else
13438         {
13439           suffix[0] = p[0];
13440           suffix[1] = p[1];
13441           suffix[2] = '\0';
13442         }
13443
13444       sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
13445       ins->mnemonicendp += xop_cmp_op[cmp_type].len;
13446     }
13447   else
13448     {
13449       /* We have a reserved extension byte.  Output it directly.  */
13450       ins->scratchbuf[0] = '$';
13451       print_operand_value (ins, ins->scratchbuf + 1, 1, cmp_type);
13452       oappend_maybe_intel (ins, ins->scratchbuf);
13453       ins->scratchbuf[0] = '\0';
13454     }
13455 }
13456
13457 static const struct op pclmul_op[] =
13458 {
13459   { STRING_COMMA_LEN ("lql") },
13460   { STRING_COMMA_LEN ("hql") },
13461   { STRING_COMMA_LEN ("lqh") },
13462   { STRING_COMMA_LEN ("hqh") }
13463 };
13464
13465 static void
13466 PCLMUL_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13467               int sizeflag ATTRIBUTE_UNUSED)
13468 {
13469   unsigned int pclmul_type;
13470
13471   FETCH_DATA (ins->info, ins->codep + 1);
13472   pclmul_type = *ins->codep++ & 0xff;
13473   switch (pclmul_type)
13474     {
13475     case 0x10:
13476       pclmul_type = 2;
13477       break;
13478     case 0x11:
13479       pclmul_type = 3;
13480       break;
13481     default:
13482       break;
13483     }
13484   if (pclmul_type < ARRAY_SIZE (pclmul_op))
13485     {
13486       char suffix[4];
13487       char *p = ins->mnemonicendp - 3;
13488       suffix[0] = p[0];
13489       suffix[1] = p[1];
13490       suffix[2] = p[2];
13491       suffix[3] = '\0';
13492       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
13493       ins->mnemonicendp += pclmul_op[pclmul_type].len;
13494     }
13495   else
13496     {
13497       /* We have a reserved extension byte.  Output it directly.  */
13498       ins->scratchbuf[0] = '$';
13499       print_operand_value (ins, ins->scratchbuf + 1, 1, pclmul_type);
13500       oappend_maybe_intel (ins, ins->scratchbuf);
13501       ins->scratchbuf[0] = '\0';
13502     }
13503 }
13504
13505 static void
13506 MOVSXD_Fixup (instr_info *ins, int bytemode, int sizeflag)
13507 {
13508   /* Add proper suffix to "movsxd".  */
13509   char *p = ins->mnemonicendp;
13510
13511   switch (bytemode)
13512     {
13513     case movsxd_mode:
13514       if (!ins->intel_syntax)
13515         {
13516           USED_REX (REX_W);
13517           if (ins->rex & REX_W)
13518             {
13519               *p++ = 'l';
13520               *p++ = 'q';
13521               break;
13522             }
13523         }
13524
13525       *p++ = 'x';
13526       *p++ = 'd';
13527       break;
13528     default:
13529       oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
13530       break;
13531     }
13532
13533   ins->mnemonicendp = p;
13534   *p = '\0';
13535   OP_E (ins, bytemode, sizeflag);
13536 }
13537
13538 static void
13539 DistinctDest_Fixup (instr_info *ins, int bytemode, int sizeflag)
13540 {
13541   unsigned int reg = ins->vex.register_specifier;
13542   unsigned int modrm_reg = ins->modrm.reg;
13543   unsigned int modrm_rm = ins->modrm.rm;
13544
13545   /* Calc destination register number.  */
13546   if (ins->rex & REX_R)
13547     modrm_reg += 8;
13548   if (!ins->vex.r)
13549     modrm_reg += 16;
13550
13551   /* Calc src1 register number.  */
13552   if (ins->address_mode != mode_64bit)
13553     reg &= 7;
13554   else if (ins->vex.evex && !ins->vex.v)
13555     reg += 16;
13556
13557   /* Calc src2 register number.  */
13558   if (ins->modrm.mod == 3)
13559     {
13560       if (ins->rex & REX_B)
13561         modrm_rm += 8;
13562       if (ins->rex & REX_X)
13563         modrm_rm += 16;
13564     }
13565
13566   /* Destination and source registers must be distinct, output bad if
13567      dest == src1 or dest == src2.  */
13568   if (modrm_reg == reg
13569       || (ins->modrm.mod == 3
13570           && modrm_reg == modrm_rm))
13571     {
13572       oappend (ins, "(bad)");
13573     }
13574   else
13575     OP_XMM (ins, bytemode, sizeflag);
13576 }
13577
13578 static void
13579 OP_Rounding (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13580 {
13581   if (ins->modrm.mod != 3 || !ins->vex.b)
13582     return;
13583
13584   switch (bytemode)
13585     {
13586     case evex_rounding_64_mode:
13587       if (ins->address_mode != mode_64bit || !ins->vex.w)
13588         return;
13589       /* Fall through.  */
13590     case evex_rounding_mode:
13591       ins->evex_used |= EVEX_b_used;
13592       oappend (ins, names_rounding[ins->vex.ll]);
13593       break;
13594     case evex_sae_mode:
13595       ins->evex_used |= EVEX_b_used;
13596       oappend (ins, "{");
13597       break;
13598     default:
13599       abort ();
13600     }
13601   oappend (ins, "sae}");
13602 }