opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
   3    2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
   4    Free Software Foundation, Inc.
   5
   6    This file is part of the GNU opcodes library.
   7
   8    This library is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3, or (at your option)
  11    any later version.
  12
  13    It is distributed in the hope that it will be useful, but WITHOUT
  14    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16    License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; if not, write to the Free Software
  20    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  21    MA 02110-1301, USA.  */
  22
  23
  24 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  25    July 1988
  26     modified by John Hassey (hassey@dg-rtp.dg.com)
  27     x86-64 support added by Jan Hubicka (jh@suse.cz)
  28     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  29
  30 /* The main tables describing the instructions is essentially a copy
  31    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  32    Programmers Manual.  Usually, there is a capital letter, followed
  33    by a small letter.  The capital letter tell the addressing mode,
  34    and the small letter tells about the operand size.  Refer to
  35    the Intel manual for details.  */
  36
  37 #include "sysdep.h"
  38 #include "dis-asm.h"
  39 #include "opintl.h"
  40 #include "opcode/i386.h"
  41 #include "libiberty.h"
  42
  43 #include <setjmp.h>
  44
  45 static int fetch_data (struct disassemble_info *, bfd_byte *);
  46 static void ckprefix (void);
  47 static const char *prefix_name (int, int);
  48 static int print_insn (bfd_vma, disassemble_info *);
  49 static void dofloat (int);
  50 static void OP_ST (int, int);
  51 static void OP_STi (int, int);
  52 static int putop (const char *, int);
  53 static void oappend (const char *);
  54 static void append_seg (void);
  55 static void OP_indirE (int, int);
  56 static void print_operand_value (char *, int, bfd_vma);
  57 static void OP_E_register (int, int);
  58 static void OP_E_memory (int, int);
  59 static void OP_E_extended (int, int);
  60 static void print_displacement (char *, bfd_vma);
  61 static void OP_E (int, int);
  62 static void OP_G (int, int);
  63 static bfd_vma get64 (void);
  64 static bfd_signed_vma get32 (void);
  65 static bfd_signed_vma get32s (void);
  66 static int get16 (void);
  67 static void set_op (bfd_vma, int);
  68 static void OP_Skip_MODRM (int, int);
  69 static void OP_REG (int, int);
  70 static void OP_IMREG (int, int);
  71 static void OP_I (int, int);
  72 static void OP_I64 (int, int);
  73 static void OP_sI (int, int);
  74 static void OP_J (int, int);
  75 static void OP_SEG (int, int);
  76 static void OP_DIR (int, int);
  77 static void OP_OFF (int, int);
  78 static void OP_OFF64 (int, int);
  79 static void ptr_reg (int, int);
  80 static void OP_ESreg (int, int);
  81 static void OP_DSreg (int, int);
  82 static void OP_C (int, int);
  83 static void OP_D (int, int);
  84 static void OP_T (int, int);
  85 static void OP_R (int, int);
  86 static void OP_MMX (int, int);
  87 static void OP_XMM (int, int);
  88 static void OP_EM (int, int);
  89 static void OP_EX (int, int);
  90 static void OP_EMC (int,int);
  91 static void OP_MXC (int,int);
  92 static void OP_MS (int, int);
  93 static void OP_XS (int, int);
  94 static void OP_M (int, int);
  95 static void OP_VEX (int, int);
  96 static void OP_EX_Vex (int, int);
  97 static void OP_EX_VexW (int, int);
  98 static void OP_XMM_Vex (int, int);
  99 static void OP_XMM_VexW (int, int);
 100 static void OP_REG_VexI4 (int, int);
 101 static void PCLMUL_Fixup (int, int);
 102 static void VEXI4_Fixup (int, int);
 103 static void VZERO_Fixup (int, int);
 104 static void VCMP_Fixup (int, int);
 105 static void OP_0f07 (int, int);
 106 static void OP_Monitor (int, int);
 107 static void OP_Mwait (int, int);
 108 static void NOP_Fixup1 (int, int);
 109 static void NOP_Fixup2 (int, int);
 110 static void OP_3DNowSuffix (int, int);
 111 static void CMP_Fixup (int, int);
 112 static void BadOp (void);
 113 static void REP_Fixup (int, int);
 114 static void CMPXCHG8B_Fixup (int, int);
 115 static void XMM_Fixup (int, int);
 116 static void CRC32_Fixup (int, int);
 117 static void OP_LWPCB_E (int, int);
 118 static void OP_LWP_E (int, int);
 119 static void OP_LWP_I (int, int);
 120
 121 static void MOVBE_Fixup (int, int);
 122
 123 struct dis_private {
 124   /* Points to first byte not fetched.  */
 125   bfd_byte *max_fetched;
 126   bfd_byte the_buffer[MAX_MNEM_SIZE];
 127   bfd_vma insn_start;
 128   int orig_sizeflag;
 129   jmp_buf bailout;
 130 };
 131
 132 enum address_mode
 133 {
 134   mode_16bit,
 135   mode_32bit,
 136   mode_64bit
 137 };
 138
 139 enum address_mode address_mode;
 140
 141 /* Flags for the prefixes for the current instruction.  See below.  */
 142 static int prefixes;
 143
 144 /* REX prefix the current instruction.  See below.  */
 145 static int rex;
 146 /* Bits of REX we've already used.  */
 147 static int rex_used;
 148 /* Original REX prefix.  */
 149 static int rex_original;
 150 /* REX bits in original REX prefix ignored.  It may not be the same
 151    as rex_original since some bits may not be ignored.  */
 152 static int rex_ignored;
 153 /* Mark parts used in the REX prefix.  When we are testing for
 154    empty prefix (for 8bit register REX extension), just mask it
 155    out.  Otherwise test for REX bit is excuse for existence of REX
 156    only in case value is nonzero.  */
 157 #define USED_REX(value)                                 \
 158   {                                                     \
 159     if (value)                                          \
 160       {                                                 \
 161         if ((rex & value))                              \
 162           rex_used |= (value) | REX_OPCODE;             \
 163       }                                                 \
 164     else                                                \
 165       rex_used |= REX_OPCODE;                           \
 166   }
 167
 168 /* Flags for prefixes which we somehow handled when printing the
 169    current instruction.  */
 170 static int used_prefixes;
 171
 172 /* Flags stored in PREFIXES.  */
 173 #define PREFIX_REPZ 1
 174 #define PREFIX_REPNZ 2
 175 #define PREFIX_LOCK 4
 176 #define PREFIX_CS 8
 177 #define PREFIX_SS 0x10
 178 #define PREFIX_DS 0x20
 179 #define PREFIX_ES 0x40
 180 #define PREFIX_FS 0x80
 181 #define PREFIX_GS 0x100
 182 #define PREFIX_DATA 0x200
 183 #define PREFIX_ADDR 0x400
 184 #define PREFIX_FWAIT 0x800
 185
 186 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 187    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 188    on error.  */
 189 #define FETCH_DATA(info, addr) \
 190   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 191    ? 1 : fetch_data ((info), (addr)))
 192
 193 static int
 194 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 195 {
 196   int status;
 197   struct dis_private *priv = (struct dis_private *) info->private_data;
 198   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 199
 200   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 201     status = (*info->read_memory_func) (start,
 202                                         priv->max_fetched,
 203                                         addr - priv->max_fetched,
 204                                         info);
 205   else
 206     status = -1;
 207   if (status != 0)
 208     {
 209       /* If we did manage to read at least one byte, then
 210          print_insn_i386 will do something sensible.  Otherwise, print
 211          an error.  We do that here because this is where we know
 212          STATUS.  */
 213       if (priv->max_fetched == priv->the_buffer)
 214         (*info->memory_error_func) (status, start, info);
 215       longjmp (priv->bailout, 1);
 216     }
 217   else
 218     priv->max_fetched = addr;
 219   return 1;
 220 }
 221
 222 #define XX { NULL, 0 }
 223
 224 #define Eb { OP_E, b_mode }
 225 #define EbS { OP_E, b_swap_mode }
 226 #define Ev { OP_E, v_mode }
 227 #define EvS { OP_E, v_swap_mode }
 228 #define Ed { OP_E, d_mode }
 229 #define Edq { OP_E, dq_mode }
 230 #define Edqw { OP_E, dqw_mode }
 231 #define Edqb { OP_E, dqb_mode }
 232 #define Edqd { OP_E, dqd_mode }
 233 #define Eq { OP_E, q_mode }
 234 #define indirEv { OP_indirE, stack_v_mode }
 235 #define indirEp { OP_indirE, f_mode }
 236 #define stackEv { OP_E, stack_v_mode }
 237 #define Em { OP_E, m_mode }
 238 #define Ew { OP_E, w_mode }
 239 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 240 #define Ma { OP_M, a_mode }
 241 #define Mb { OP_M, b_mode }
 242 #define Md { OP_M, d_mode }
 243 #define Mo { OP_M, o_mode }
 244 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 245 #define Mq { OP_M, q_mode }
 246 #define Mx { OP_M, x_mode }
 247 #define Mxmm { OP_M, xmm_mode }
 248 #define Gb { OP_G, b_mode }
 249 #define Gv { OP_G, v_mode }
 250 #define Gd { OP_G, d_mode }
 251 #define Gdq { OP_G, dq_mode }
 252 #define Gm { OP_G, m_mode }
 253 #define Gw { OP_G, w_mode }
 254 #define Rd { OP_R, d_mode }
 255 #define Rm { OP_R, m_mode }
 256 #define Ib { OP_I, b_mode }
 257 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 258 #define Iv { OP_I, v_mode }
 259 #define Iq { OP_I, q_mode }
 260 #define Iv64 { OP_I64, v_mode }
 261 #define Iw { OP_I, w_mode }
 262 #define I1 { OP_I, const_1_mode }
 263 #define Jb { OP_J, b_mode }
 264 #define Jv { OP_J, v_mode }
 265 #define Cm { OP_C, m_mode }
 266 #define Dm { OP_D, m_mode }
 267 #define Td { OP_T, d_mode }
 268 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 269
 270 #define RMeAX { OP_REG, eAX_reg }
 271 #define RMeBX { OP_REG, eBX_reg }
 272 #define RMeCX { OP_REG, eCX_reg }
 273 #define RMeDX { OP_REG, eDX_reg }
 274 #define RMeSP { OP_REG, eSP_reg }
 275 #define RMeBP { OP_REG, eBP_reg }
 276 #define RMeSI { OP_REG, eSI_reg }
 277 #define RMeDI { OP_REG, eDI_reg }
 278 #define RMrAX { OP_REG, rAX_reg }
 279 #define RMrBX { OP_REG, rBX_reg }
 280 #define RMrCX { OP_REG, rCX_reg }
 281 #define RMrDX { OP_REG, rDX_reg }
 282 #define RMrSP { OP_REG, rSP_reg }
 283 #define RMrBP { OP_REG, rBP_reg }
 284 #define RMrSI { OP_REG, rSI_reg }
 285 #define RMrDI { OP_REG, rDI_reg }
 286 #define RMAL { OP_REG, al_reg }
 287 #define RMAL { OP_REG, al_reg }
 288 #define RMCL { OP_REG, cl_reg }
 289 #define RMDL { OP_REG, dl_reg }
 290 #define RMBL { OP_REG, bl_reg }
 291 #define RMAH { OP_REG, ah_reg }
 292 #define RMCH { OP_REG, ch_reg }
 293 #define RMDH { OP_REG, dh_reg }
 294 #define RMBH { OP_REG, bh_reg }
 295 #define RMAX { OP_REG, ax_reg }
 296 #define RMDX { OP_REG, dx_reg }
 297
 298 #define eAX { OP_IMREG, eAX_reg }
 299 #define eBX { OP_IMREG, eBX_reg }
 300 #define eCX { OP_IMREG, eCX_reg }
 301 #define eDX { OP_IMREG, eDX_reg }
 302 #define eSP { OP_IMREG, eSP_reg }
 303 #define eBP { OP_IMREG, eBP_reg }
 304 #define eSI { OP_IMREG, eSI_reg }
 305 #define eDI { OP_IMREG, eDI_reg }
 306 #define AL { OP_IMREG, al_reg }
 307 #define CL { OP_IMREG, cl_reg }
 308 #define DL { OP_IMREG, dl_reg }
 309 #define BL { OP_IMREG, bl_reg }
 310 #define AH { OP_IMREG, ah_reg }
 311 #define CH { OP_IMREG, ch_reg }
 312 #define DH { OP_IMREG, dh_reg }
 313 #define BH { OP_IMREG, bh_reg }
 314 #define AX { OP_IMREG, ax_reg }
 315 #define DX { OP_IMREG, dx_reg }
 316 #define zAX { OP_IMREG, z_mode_ax_reg }
 317 #define indirDX { OP_IMREG, indir_dx_reg }
 318
 319 #define Sw { OP_SEG, w_mode }
 320 #define Sv { OP_SEG, v_mode }
 321 #define Ap { OP_DIR, 0 }
 322 #define Ob { OP_OFF64, b_mode }
 323 #define Ov { OP_OFF64, v_mode }
 324 #define Xb { OP_DSreg, eSI_reg }
 325 #define Xv { OP_DSreg, eSI_reg }
 326 #define Xz { OP_DSreg, eSI_reg }
 327 #define Yb { OP_ESreg, eDI_reg }
 328 #define Yv { OP_ESreg, eDI_reg }
 329 #define DSBX { OP_DSreg, eBX_reg }
 330
 331 #define es { OP_REG, es_reg }
 332 #define ss { OP_REG, ss_reg }
 333 #define cs { OP_REG, cs_reg }
 334 #define ds { OP_REG, ds_reg }
 335 #define fs { OP_REG, fs_reg }
 336 #define gs { OP_REG, gs_reg }
 337
 338 #define MX { OP_MMX, 0 }
 339 #define XM { OP_XMM, 0 }
 340 #define XMM { OP_XMM, xmm_mode }
 341 #define EM { OP_EM, v_mode }
 342 #define EMS { OP_EM, v_swap_mode }
 343 #define EMd { OP_EM, d_mode }
 344 #define EMx { OP_EM, x_mode }
 345 #define EXw { OP_EX, w_mode }
 346 #define EXd { OP_EX, d_mode }
 347 #define EXdS { OP_EX, d_swap_mode }
 348 #define EXq { OP_EX, q_mode }
 349 #define EXqS { OP_EX, q_swap_mode }
 350 #define EXx { OP_EX, x_mode }
 351 #define EXxS { OP_EX, x_swap_mode }
 352 #define EXxmm { OP_EX, xmm_mode }
 353 #define EXxmmq { OP_EX, xmmq_mode }
 354 #define EXymmq { OP_EX, ymmq_mode }
 355 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 356 #define MS { OP_MS, v_mode }
 357 #define XS { OP_XS, v_mode }
 358 #define EMCq { OP_EMC, q_mode }
 359 #define MXC { OP_MXC, 0 }
 360 #define OPSUF { OP_3DNowSuffix, 0 }
 361 #define CMP { CMP_Fixup, 0 }
 362 #define XMM0 { XMM_Fixup, 0 }
 363
 364 #define Vex { OP_VEX, vex_mode }
 365 #define Vex128 { OP_VEX, vex128_mode }
 366 #define Vex256 { OP_VEX, vex256_mode }
 367 #define VexI4 { VEXI4_Fixup, 0}
 368 #define EXdVex { OP_EX_Vex, d_mode }
 369 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 370 #define EXqVex { OP_EX_Vex, q_mode }
 371 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 372 #define EXVexW { OP_EX_VexW, x_mode }
 373 #define EXdVexW { OP_EX_VexW, d_mode }
 374 #define EXqVexW { OP_EX_VexW, q_mode }
 375 #define XMVex { OP_XMM_Vex, 0 }
 376 #define XMVexW { OP_XMM_VexW, 0 }
 377 #define XMVexI4 { OP_REG_VexI4, x_mode }
 378 #define PCLMUL { PCLMUL_Fixup, 0 }
 379 #define VZERO { VZERO_Fixup, 0 }
 380 #define VCMP { VCMP_Fixup, 0 }
 381
 382 /* Used handle "rep" prefix for string instructions.  */
 383 #define Xbr { REP_Fixup, eSI_reg }
 384 #define Xvr { REP_Fixup, eSI_reg }
 385 #define Ybr { REP_Fixup, eDI_reg }
 386 #define Yvr { REP_Fixup, eDI_reg }
 387 #define Yzr { REP_Fixup, eDI_reg }
 388 #define indirDXr { REP_Fixup, indir_dx_reg }
 389 #define ALr { REP_Fixup, al_reg }
 390 #define eAXr { REP_Fixup, eAX_reg }
 391
 392 #define cond_jump_flag { NULL, cond_jump_mode }
 393 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 394
 395 /* bits in sizeflag */
 396 #define SUFFIX_ALWAYS 4
 397 #define AFLAG 2
 398 #define DFLAG 1
 399
 400 enum
 401 {
 402   /* byte operand */
 403   b_mode = 1,
 404   /* byte operand with operand swapped */
 405   b_swap_mode,
 406   /* operand size depends on prefixes */
 407   v_mode,
 408   /* operand size depends on prefixes with operand swapped */
 409   v_swap_mode,
 410   /* word operand */
 411   w_mode,
 412   /* double word operand  */
 413   d_mode,
 414   /* double word operand with operand swapped */
 415   d_swap_mode,
 416   /* quad word operand */
 417   q_mode,
 418   /* quad word operand with operand swapped */
 419   q_swap_mode,
 420   /* ten-byte operand */
 421   t_mode,
 422   /* 16-byte XMM or 32-byte YMM operand */
 423   x_mode,
 424   /* 16-byte XMM or 32-byte YMM operand with operand swapped */
 425   x_swap_mode,
 426   /* 16-byte XMM operand */
 427   xmm_mode,
 428   /* 16-byte XMM or quad word operand */
 429   xmmq_mode,
 430   /* 32-byte YMM or quad word operand */
 431   ymmq_mode,
 432   /* d_mode in 32bit, q_mode in 64bit mode.  */
 433   m_mode,
 434   /* pair of v_mode operands */
 435   a_mode,
 436   cond_jump_mode,
 437   loop_jcxz_mode,
 438   /* operand size depends on REX prefixes.  */
 439   dq_mode,
 440   /* registers like dq_mode, memory like w_mode.  */
 441   dqw_mode,
 442   /* 4- or 6-byte pointer operand */
 443   f_mode,
 444   const_1_mode,
 445   /* v_mode for stack-related opcodes.  */
 446   stack_v_mode,
 447   /* non-quad operand size depends on prefixes */
 448   z_mode,
 449   /* 16-byte operand */
 450   o_mode,
 451   /* registers like dq_mode, memory like b_mode.  */
 452   dqb_mode,
 453   /* registers like dq_mode, memory like d_mode.  */
 454   dqd_mode,
 455   /* normal vex mode */
 456   vex_mode,
 457   /* 128bit vex mode */
 458   vex128_mode,
 459   /* 256bit vex mode */
 460   vex256_mode,
 461   /* operand size depends on the VEX.W bit.  */
 462   vex_w_dq_mode,
 463
 464   es_reg,
 465   cs_reg,
 466   ss_reg,
 467   ds_reg,
 468   fs_reg,
 469   gs_reg,
 470
 471   eAX_reg,
 472   eCX_reg,
 473   eDX_reg,
 474   eBX_reg,
 475   eSP_reg,
 476   eBP_reg,
 477   eSI_reg,
 478   eDI_reg,
 479
 480   al_reg,
 481   cl_reg,
 482   dl_reg,
 483   bl_reg,
 484   ah_reg,
 485   ch_reg,
 486   dh_reg,
 487   bh_reg,
 488
 489   ax_reg,
 490   cx_reg,
 491   dx_reg,
 492   bx_reg,
 493   sp_reg,
 494   bp_reg,
 495   si_reg,
 496   di_reg,
 497
 498   rAX_reg,
 499   rCX_reg,
 500   rDX_reg,
 501   rBX_reg,
 502   rSP_reg,
 503   rBP_reg,
 504   rSI_reg,
 505   rDI_reg,
 506
 507   z_mode_ax_reg,
 508   indir_dx_reg
 509 };
 510
 511 enum
 512 {
 513   FLOATCODE = 1,
 514   USE_REG_TABLE,
 515   USE_MOD_TABLE,
 516   USE_RM_TABLE,
 517   USE_PREFIX_TABLE,
 518   USE_X86_64_TABLE,
 519   USE_3BYTE_TABLE,
 520   USE_XOP_8F_TABLE,
 521   USE_VEX_C4_TABLE,
 522   USE_VEX_C5_TABLE,
 523   USE_VEX_LEN_TABLE
 524 };
 525
 526 #define FLOAT                   NULL, { { NULL, FLOATCODE } }
 527
 528 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }
 529 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 530 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 531 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 532 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 533 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 534 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 535 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 536 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 537 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 538 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 539
 540 enum
 541 {
 542   REG_80 = 0,
 543   REG_81,
 544   REG_82,
 545   REG_8F,
 546   REG_C0,
 547   REG_C1,
 548   REG_C6,
 549   REG_C7,
 550   REG_D0,
 551   REG_D1,
 552   REG_D2,
 553   REG_D3,
 554   REG_F6,
 555   REG_F7,
 556   REG_FE,
 557   REG_FF,
 558   REG_0F00,
 559   REG_0F01,
 560   REG_0F0D,
 561   REG_0F18,
 562   REG_0F71,
 563   REG_0F72,
 564   REG_0F73,
 565   REG_0FA6,
 566   REG_0FA7,
 567   REG_0FAE,
 568   REG_0FBA,
 569   REG_0FC7,
 570   REG_VEX_71,
 571   REG_VEX_72,
 572   REG_VEX_73,
 573   REG_VEX_AE,
 574   REG_XOP_LWPCB,
 575   REG_XOP_LWP
 576 };
 577
 578 enum
 579 {
 580   MOD_8D = 0,
 581   MOD_0F01_REG_0,
 582   MOD_0F01_REG_1,
 583   MOD_0F01_REG_2,
 584   MOD_0F01_REG_3,
 585   MOD_0F01_REG_7,
 586   MOD_0F12_PREFIX_0,
 587   MOD_0F13,
 588   MOD_0F16_PREFIX_0,
 589   MOD_0F17,
 590   MOD_0F18_REG_0,
 591   MOD_0F18_REG_1,
 592   MOD_0F18_REG_2,
 593   MOD_0F18_REG_3,
 594   MOD_0F20,
 595   MOD_0F21,
 596   MOD_0F22,
 597   MOD_0F23,
 598   MOD_0F24,
 599   MOD_0F26,
 600   MOD_0F2B_PREFIX_0,
 601   MOD_0F2B_PREFIX_1,
 602   MOD_0F2B_PREFIX_2,
 603   MOD_0F2B_PREFIX_3,
 604   MOD_0F51,
 605   MOD_0F71_REG_2,
 606   MOD_0F71_REG_4,
 607   MOD_0F71_REG_6,
 608   MOD_0F72_REG_2,
 609   MOD_0F72_REG_4,
 610   MOD_0F72_REG_6,
 611   MOD_0F73_REG_2,
 612   MOD_0F73_REG_3,
 613   MOD_0F73_REG_6,
 614   MOD_0F73_REG_7,
 615   MOD_0FAE_REG_0,
 616   MOD_0FAE_REG_1,
 617   MOD_0FAE_REG_2,
 618   MOD_0FAE_REG_3,
 619   MOD_0FAE_REG_4,
 620   MOD_0FAE_REG_5,
 621   MOD_0FAE_REG_6,
 622   MOD_0FAE_REG_7,
 623   MOD_0FB2,
 624   MOD_0FB4,
 625   MOD_0FB5,
 626   MOD_0FC7_REG_6,
 627   MOD_0FC7_REG_7,
 628   MOD_0FD7,
 629   MOD_0FE7_PREFIX_2,
 630   MOD_0FF0_PREFIX_3,
 631   MOD_0F382A_PREFIX_2,
 632   MOD_62_32BIT,
 633   MOD_C4_32BIT,
 634   MOD_C5_32BIT,
 635   MOD_VEX_12_PREFIX_0,
 636   MOD_VEX_13,
 637   MOD_VEX_16_PREFIX_0,
 638   MOD_VEX_17,
 639   MOD_VEX_2B,
 640   MOD_VEX_51,
 641   MOD_VEX_71_REG_2,
 642   MOD_VEX_71_REG_4,
 643   MOD_VEX_71_REG_6,
 644   MOD_VEX_72_REG_2,
 645   MOD_VEX_72_REG_4,
 646   MOD_VEX_72_REG_6,
 647   MOD_VEX_73_REG_2,
 648   MOD_VEX_73_REG_3,
 649   MOD_VEX_73_REG_6,
 650   MOD_VEX_73_REG_7,
 651   MOD_VEX_AE_REG_2,
 652   MOD_VEX_AE_REG_3,
 653   MOD_VEX_D7_PREFIX_2,
 654   MOD_VEX_E7_PREFIX_2,
 655   MOD_VEX_F0_PREFIX_3,
 656   MOD_VEX_3818_PREFIX_2,
 657   MOD_VEX_3819_PREFIX_2,
 658   MOD_VEX_381A_PREFIX_2,
 659   MOD_VEX_382A_PREFIX_2,
 660   MOD_VEX_382C_PREFIX_2,
 661   MOD_VEX_382D_PREFIX_2,
 662   MOD_VEX_382E_PREFIX_2,
 663   MOD_VEX_382F_PREFIX_2
 664 };
 665
 666 enum
 667 {
 668   RM_0F01_REG_0 = 0,
 669   RM_0F01_REG_1,
 670   RM_0F01_REG_2,
 671   RM_0F01_REG_3,
 672   RM_0F01_REG_7,
 673   RM_0FAE_REG_5,
 674   RM_0FAE_REG_6,
 675   RM_0FAE_REG_7
 676 };
 677
 678 enum
 679 {
 680   PREFIX_90 = 0,
 681   PREFIX_0F10,
 682   PREFIX_0F11,
 683   PREFIX_0F12,
 684   PREFIX_0F16,
 685   PREFIX_0F2A,
 686   PREFIX_0F2B,
 687   PREFIX_0F2C,
 688   PREFIX_0F2D,
 689   PREFIX_0F2E,
 690   PREFIX_0F2F,
 691   PREFIX_0F51,
 692   PREFIX_0F52,
 693   PREFIX_0F53,
 694   PREFIX_0F58,
 695   PREFIX_0F59,
 696   PREFIX_0F5A,
 697   PREFIX_0F5B,
 698   PREFIX_0F5C,
 699   PREFIX_0F5D,
 700   PREFIX_0F5E,
 701   PREFIX_0F5F,
 702   PREFIX_0F60,
 703   PREFIX_0F61,
 704   PREFIX_0F62,
 705   PREFIX_0F6C,
 706   PREFIX_0F6D,
 707   PREFIX_0F6F,
 708   PREFIX_0F70,
 709   PREFIX_0F73_REG_3,
 710   PREFIX_0F73_REG_7,
 711   PREFIX_0F78,
 712   PREFIX_0F79,
 713   PREFIX_0F7C,
 714   PREFIX_0F7D,
 715   PREFIX_0F7E,
 716   PREFIX_0F7F,
 717   PREFIX_0FB8,
 718   PREFIX_0FBD,
 719   PREFIX_0FC2,
 720   PREFIX_0FC3,
 721   PREFIX_0FC7_REG_6,
 722   PREFIX_0FD0,
 723   PREFIX_0FD6,
 724   PREFIX_0FE6,
 725   PREFIX_0FE7,
 726   PREFIX_0FF0,
 727   PREFIX_0FF7,
 728   PREFIX_0F3810,
 729   PREFIX_0F3814,
 730   PREFIX_0F3815,
 731   PREFIX_0F3817,
 732   PREFIX_0F3820,
 733   PREFIX_0F3821,
 734   PREFIX_0F3822,
 735   PREFIX_0F3823,
 736   PREFIX_0F3824,
 737   PREFIX_0F3825,
 738   PREFIX_0F3828,
 739   PREFIX_0F3829,
 740   PREFIX_0F382A,
 741   PREFIX_0F382B,
 742   PREFIX_0F3830,
 743   PREFIX_0F3831,
 744   PREFIX_0F3832,
 745   PREFIX_0F3833,
 746   PREFIX_0F3834,
 747   PREFIX_0F3835,
 748   PREFIX_0F3837,
 749   PREFIX_0F3838,
 750   PREFIX_0F3839,
 751   PREFIX_0F383A,
 752   PREFIX_0F383B,
 753   PREFIX_0F383C,
 754   PREFIX_0F383D,
 755   PREFIX_0F383E,
 756   PREFIX_0F383F,
 757   PREFIX_0F3840,
 758   PREFIX_0F3841,
 759   PREFIX_0F3880,
 760   PREFIX_0F3881,
 761   PREFIX_0F38DB,
 762   PREFIX_0F38DC,
 763   PREFIX_0F38DD,
 764   PREFIX_0F38DE,
 765   PREFIX_0F38DF,
 766   PREFIX_0F38F0,
 767   PREFIX_0F38F1,
 768   PREFIX_0F3A08,
 769   PREFIX_0F3A09,
 770   PREFIX_0F3A0A,
 771   PREFIX_0F3A0B,
 772   PREFIX_0F3A0C,
 773   PREFIX_0F3A0D,
 774   PREFIX_0F3A0E,
 775   PREFIX_0F3A14,
 776   PREFIX_0F3A15,
 777   PREFIX_0F3A16,
 778   PREFIX_0F3A17,
 779   PREFIX_0F3A20,
 780   PREFIX_0F3A21,
 781   PREFIX_0F3A22,
 782   PREFIX_0F3A40,
 783   PREFIX_0F3A41,
 784   PREFIX_0F3A42,
 785   PREFIX_0F3A44,
 786   PREFIX_0F3A60,
 787   PREFIX_0F3A61,
 788   PREFIX_0F3A62,
 789   PREFIX_0F3A63,
 790   PREFIX_0F3ADF,
 791   PREFIX_VEX_10,
 792   PREFIX_VEX_11,
 793   PREFIX_VEX_12,
 794   PREFIX_VEX_16,
 795   PREFIX_VEX_2A,
 796   PREFIX_VEX_2C,
 797   PREFIX_VEX_2D,
 798   PREFIX_VEX_2E,
 799   PREFIX_VEX_2F,
 800   PREFIX_VEX_51,
 801   PREFIX_VEX_52,
 802   PREFIX_VEX_53,
 803   PREFIX_VEX_58,
 804   PREFIX_VEX_59,
 805   PREFIX_VEX_5A,
 806   PREFIX_VEX_5B,
 807   PREFIX_VEX_5C,
 808   PREFIX_VEX_5D,
 809   PREFIX_VEX_5E,
 810   PREFIX_VEX_5F,
 811   PREFIX_VEX_60,
 812   PREFIX_VEX_61,
 813   PREFIX_VEX_62,
 814   PREFIX_VEX_63,
 815   PREFIX_VEX_64,
 816   PREFIX_VEX_65,
 817   PREFIX_VEX_66,
 818   PREFIX_VEX_67,
 819   PREFIX_VEX_68,
 820   PREFIX_VEX_69,
 821   PREFIX_VEX_6A,
 822   PREFIX_VEX_6B,
 823   PREFIX_VEX_6C,
 824   PREFIX_VEX_6D,
 825   PREFIX_VEX_6E,
 826   PREFIX_VEX_6F,
 827   PREFIX_VEX_70,
 828   PREFIX_VEX_71_REG_2,
 829   PREFIX_VEX_71_REG_4,
 830   PREFIX_VEX_71_REG_6,
 831   PREFIX_VEX_72_REG_2,
 832   PREFIX_VEX_72_REG_4,
 833   PREFIX_VEX_72_REG_6,
 834   PREFIX_VEX_73_REG_2,
 835   PREFIX_VEX_73_REG_3,
 836   PREFIX_VEX_73_REG_6,
 837   PREFIX_VEX_73_REG_7,
 838   PREFIX_VEX_74,
 839   PREFIX_VEX_75,
 840   PREFIX_VEX_76,
 841   PREFIX_VEX_77,
 842   PREFIX_VEX_7C,
 843   PREFIX_VEX_7D,
 844   PREFIX_VEX_7E,
 845   PREFIX_VEX_7F,
 846   PREFIX_VEX_C2,
 847   PREFIX_VEX_C4,
 848   PREFIX_VEX_C5,
 849   PREFIX_VEX_D0,
 850   PREFIX_VEX_D1,
 851   PREFIX_VEX_D2,
 852   PREFIX_VEX_D3,
 853   PREFIX_VEX_D4,
 854   PREFIX_VEX_D5,
 855   PREFIX_VEX_D6,
 856   PREFIX_VEX_D7,
 857   PREFIX_VEX_D8,
 858   PREFIX_VEX_D9,
 859   PREFIX_VEX_DA,
 860   PREFIX_VEX_DB,
 861   PREFIX_VEX_DC,
 862   PREFIX_VEX_DD,
 863   PREFIX_VEX_DE,
 864   PREFIX_VEX_DF,
 865   PREFIX_VEX_E0,
 866   PREFIX_VEX_E1,
 867   PREFIX_VEX_E2,
 868   PREFIX_VEX_E3,
 869   PREFIX_VEX_E4,
 870   PREFIX_VEX_E5,
 871   PREFIX_VEX_E6,
 872   PREFIX_VEX_E7,
 873   PREFIX_VEX_E8,
 874   PREFIX_VEX_E9,
 875   PREFIX_VEX_EA,
 876   PREFIX_VEX_EB,
 877   PREFIX_VEX_EC,
 878   PREFIX_VEX_ED,
 879   PREFIX_VEX_EE,
 880   PREFIX_VEX_EF,
 881   PREFIX_VEX_F0,
 882   PREFIX_VEX_F1,
 883   PREFIX_VEX_F2,
 884   PREFIX_VEX_F3,
 885   PREFIX_VEX_F4,
 886   PREFIX_VEX_F5,
 887   PREFIX_VEX_F6,
 888   PREFIX_VEX_F7,
 889   PREFIX_VEX_F8,
 890   PREFIX_VEX_F9,
 891   PREFIX_VEX_FA,
 892   PREFIX_VEX_FB,
 893   PREFIX_VEX_FC,
 894   PREFIX_VEX_FD,
 895   PREFIX_VEX_FE,
 896   PREFIX_VEX_3800,
 897   PREFIX_VEX_3801,
 898   PREFIX_VEX_3802,
 899   PREFIX_VEX_3803,
 900   PREFIX_VEX_3804,
 901   PREFIX_VEX_3805,
 902   PREFIX_VEX_3806,
 903   PREFIX_VEX_3807,
 904   PREFIX_VEX_3808,
 905   PREFIX_VEX_3809,
 906   PREFIX_VEX_380A,
 907   PREFIX_VEX_380B,
 908   PREFIX_VEX_380C,
 909   PREFIX_VEX_380D,
 910   PREFIX_VEX_380E,
 911   PREFIX_VEX_380F,
 912   PREFIX_VEX_3817,
 913   PREFIX_VEX_3818,
 914   PREFIX_VEX_3819,
 915   PREFIX_VEX_381A,
 916   PREFIX_VEX_381C,
 917   PREFIX_VEX_381D,
 918   PREFIX_VEX_381E,
 919   PREFIX_VEX_3820,
 920   PREFIX_VEX_3821,
 921   PREFIX_VEX_3822,
 922   PREFIX_VEX_3823,
 923   PREFIX_VEX_3824,
 924   PREFIX_VEX_3825,
 925   PREFIX_VEX_3828,
 926   PREFIX_VEX_3829,
 927   PREFIX_VEX_382A,
 928   PREFIX_VEX_382B,
 929   PREFIX_VEX_382C,
 930   PREFIX_VEX_382D,
 931   PREFIX_VEX_382E,
 932   PREFIX_VEX_382F,
 933   PREFIX_VEX_3830,
 934   PREFIX_VEX_3831,
 935   PREFIX_VEX_3832,
 936   PREFIX_VEX_3833,
 937   PREFIX_VEX_3834,
 938   PREFIX_VEX_3835,
 939   PREFIX_VEX_3837,
 940   PREFIX_VEX_3838,
 941   PREFIX_VEX_3839,
 942   PREFIX_VEX_383A,
 943   PREFIX_VEX_383B,
 944   PREFIX_VEX_383C,
 945   PREFIX_VEX_383D,
 946   PREFIX_VEX_383E,
 947   PREFIX_VEX_383F,
 948   PREFIX_VEX_3840,
 949   PREFIX_VEX_3841,
 950   PREFIX_VEX_3896,
 951   PREFIX_VEX_3897,
 952   PREFIX_VEX_3898,
 953   PREFIX_VEX_3899,
 954   PREFIX_VEX_389A,
 955   PREFIX_VEX_389B,
 956   PREFIX_VEX_389C,
 957   PREFIX_VEX_389D,
 958   PREFIX_VEX_389E,
 959   PREFIX_VEX_389F,
 960   PREFIX_VEX_38A6,
 961   PREFIX_VEX_38A7,
 962   PREFIX_VEX_38A8,
 963   PREFIX_VEX_38A9,
 964   PREFIX_VEX_38AA,
 965   PREFIX_VEX_38AB,
 966   PREFIX_VEX_38AC,
 967   PREFIX_VEX_38AD,
 968   PREFIX_VEX_38AE,
 969   PREFIX_VEX_38AF,
 970   PREFIX_VEX_38B6,
 971   PREFIX_VEX_38B7,
 972   PREFIX_VEX_38B8,
 973   PREFIX_VEX_38B9,
 974   PREFIX_VEX_38BA,
 975   PREFIX_VEX_38BB,
 976   PREFIX_VEX_38BC,
 977   PREFIX_VEX_38BD,
 978   PREFIX_VEX_38BE,
 979   PREFIX_VEX_38BF,
 980   PREFIX_VEX_38DB,
 981   PREFIX_VEX_38DC,
 982   PREFIX_VEX_38DD,
 983   PREFIX_VEX_38DE,
 984   PREFIX_VEX_38DF,
 985   PREFIX_VEX_3A04,
 986   PREFIX_VEX_3A05,
 987   PREFIX_VEX_3A06,
 988   PREFIX_VEX_3A08,
 989   PREFIX_VEX_3A09,
 990   PREFIX_VEX_3A0A,
 991   PREFIX_VEX_3A0B,
 992   PREFIX_VEX_3A0C,
 993   PREFIX_VEX_3A0D,
 994   PREFIX_VEX_3A0E,
 995   PREFIX_VEX_3A0F,
 996   PREFIX_VEX_3A14,
 997   PREFIX_VEX_3A15,
 998   PREFIX_VEX_3A16,
 999   PREFIX_VEX_3A17,
1000   PREFIX_VEX_3A18,
1001   PREFIX_VEX_3A19,
1002   PREFIX_VEX_3A20,
1003   PREFIX_VEX_3A21,
1004   PREFIX_VEX_3A22,
1005   PREFIX_VEX_3A40,
1006   PREFIX_VEX_3A41,
1007   PREFIX_VEX_3A42,
1008   PREFIX_VEX_3A44,
1009   PREFIX_VEX_3A4A,
1010   PREFIX_VEX_3A4B,
1011   PREFIX_VEX_3A4C,
1012   PREFIX_VEX_3A5C,
1013   PREFIX_VEX_3A5D,
1014   PREFIX_VEX_3A5E,
1015   PREFIX_VEX_3A5F,
1016   PREFIX_VEX_3A60,
1017   PREFIX_VEX_3A61,
1018   PREFIX_VEX_3A62,
1019   PREFIX_VEX_3A63,
1020   PREFIX_VEX_3A68,
1021   PREFIX_VEX_3A69,
1022   PREFIX_VEX_3A6A,
1023   PREFIX_VEX_3A6B,
1024   PREFIX_VEX_3A6C,
1025   PREFIX_VEX_3A6D,
1026   PREFIX_VEX_3A6E,
1027   PREFIX_VEX_3A6F,
1028   PREFIX_VEX_3A78,
1029   PREFIX_VEX_3A79,
1030   PREFIX_VEX_3A7A,
1031   PREFIX_VEX_3A7B,
1032   PREFIX_VEX_3A7C,
1033   PREFIX_VEX_3A7D,
1034   PREFIX_VEX_3A7E,
1035   PREFIX_VEX_3A7F,
1036   PREFIX_VEX_3ADF
1037 };
1038
1039 enum
1040 {
1041   X86_64_06 = 0,
1042   X86_64_07,
1043   X86_64_0D,
1044   X86_64_16,
1045   X86_64_17,
1046   X86_64_1E,
1047   X86_64_1F,
1048   X86_64_27,
1049   X86_64_2F,
1050   X86_64_37,
1051   X86_64_3F,
1052   X86_64_60,
1053   X86_64_61,
1054   X86_64_62,
1055   X86_64_63,
1056   X86_64_6D,
1057   X86_64_6F,
1058   X86_64_9A,
1059   X86_64_C4,
1060   X86_64_C5,
1061   X86_64_CE,
1062   X86_64_D4,
1063   X86_64_D5,
1064   X86_64_EA,
1065   X86_64_0F01_REG_0,
1066   X86_64_0F01_REG_1,
1067   X86_64_0F01_REG_2,
1068   X86_64_0F01_REG_3
1069 };
1070
1071 enum
1072 {
1073   THREE_BYTE_0F38 = 0,
1074   THREE_BYTE_0F3A,
1075   THREE_BYTE_0F7A
1076 };
1077
1078 enum
1079 {
1080   XOP_09 = 0,
1081   XOP_0A
1082 };
1083
1084 enum
1085 {
1086   VEX_0F = 0,
1087   VEX_0F38,
1088   VEX_0F3A
1089 };
1090
1091 enum
1092 {
1093   VEX_LEN_10_P_1 = 0,
1094   VEX_LEN_10_P_3,
1095   VEX_LEN_11_P_1,
1096   VEX_LEN_11_P_3,
1097   VEX_LEN_12_P_0_M_0,
1098   VEX_LEN_12_P_0_M_1,
1099   VEX_LEN_12_P_2,
1100   VEX_LEN_13_M_0,
1101   VEX_LEN_16_P_0_M_0,
1102   VEX_LEN_16_P_0_M_1,
1103   VEX_LEN_16_P_2,
1104   VEX_LEN_17_M_0,
1105   VEX_LEN_2A_P_1,
1106   VEX_LEN_2A_P_3,
1107   VEX_LEN_2C_P_1,
1108   VEX_LEN_2C_P_3,
1109   VEX_LEN_2D_P_1,
1110   VEX_LEN_2D_P_3,
1111   VEX_LEN_2E_P_0,
1112   VEX_LEN_2E_P_2,
1113   VEX_LEN_2F_P_0,
1114   VEX_LEN_2F_P_2,
1115   VEX_LEN_51_P_1,
1116   VEX_LEN_51_P_3,
1117   VEX_LEN_52_P_1,
1118   VEX_LEN_53_P_1,
1119   VEX_LEN_58_P_1,
1120   VEX_LEN_58_P_3,
1121   VEX_LEN_59_P_1,
1122   VEX_LEN_59_P_3,
1123   VEX_LEN_5A_P_1,
1124   VEX_LEN_5A_P_3,
1125   VEX_LEN_5C_P_1,
1126   VEX_LEN_5C_P_3,
1127   VEX_LEN_5D_P_1,
1128   VEX_LEN_5D_P_3,
1129   VEX_LEN_5E_P_1,
1130   VEX_LEN_5E_P_3,
1131   VEX_LEN_5F_P_1,
1132   VEX_LEN_5F_P_3,
1133   VEX_LEN_60_P_2,
1134   VEX_LEN_61_P_2,
1135   VEX_LEN_62_P_2,
1136   VEX_LEN_63_P_2,
1137   VEX_LEN_64_P_2,
1138   VEX_LEN_65_P_2,
1139   VEX_LEN_66_P_2,
1140   VEX_LEN_67_P_2,
1141   VEX_LEN_68_P_2,
1142   VEX_LEN_69_P_2,
1143   VEX_LEN_6A_P_2,
1144   VEX_LEN_6B_P_2,
1145   VEX_LEN_6C_P_2,
1146   VEX_LEN_6D_P_2,
1147   VEX_LEN_6E_P_2,
1148   VEX_LEN_70_P_1,
1149   VEX_LEN_70_P_2,
1150   VEX_LEN_70_P_3,
1151   VEX_LEN_71_R_2_P_2,
1152   VEX_LEN_71_R_4_P_2,
1153   VEX_LEN_71_R_6_P_2,
1154   VEX_LEN_72_R_2_P_2,
1155   VEX_LEN_72_R_4_P_2,
1156   VEX_LEN_72_R_6_P_2,
1157   VEX_LEN_73_R_2_P_2,
1158   VEX_LEN_73_R_3_P_2,
1159   VEX_LEN_73_R_6_P_2,
1160   VEX_LEN_73_R_7_P_2,
1161   VEX_LEN_74_P_2,
1162   VEX_LEN_75_P_2,
1163   VEX_LEN_76_P_2,
1164   VEX_LEN_7E_P_1,
1165   VEX_LEN_7E_P_2,
1166   VEX_LEN_AE_R_2_M_0,
1167   VEX_LEN_AE_R_3_M_0,
1168   VEX_LEN_C2_P_1,
1169   VEX_LEN_C2_P_3,
1170   VEX_LEN_C4_P_2,
1171   VEX_LEN_C5_P_2,
1172   VEX_LEN_D1_P_2,
1173   VEX_LEN_D2_P_2,
1174   VEX_LEN_D3_P_2,
1175   VEX_LEN_D4_P_2,
1176   VEX_LEN_D5_P_2,
1177   VEX_LEN_D6_P_2,
1178   VEX_LEN_D7_P_2_M_1,
1179   VEX_LEN_D8_P_2,
1180   VEX_LEN_D9_P_2,
1181   VEX_LEN_DA_P_2,
1182   VEX_LEN_DB_P_2,
1183   VEX_LEN_DC_P_2,
1184   VEX_LEN_DD_P_2,
1185   VEX_LEN_DE_P_2,
1186   VEX_LEN_DF_P_2,
1187   VEX_LEN_E0_P_2,
1188   VEX_LEN_E1_P_2,
1189   VEX_LEN_E2_P_2,
1190   VEX_LEN_E3_P_2,
1191   VEX_LEN_E4_P_2,
1192   VEX_LEN_E5_P_2,
1193   VEX_LEN_E8_P_2,
1194   VEX_LEN_E9_P_2,
1195   VEX_LEN_EA_P_2,
1196   VEX_LEN_EB_P_2,
1197   VEX_LEN_EC_P_2,
1198   VEX_LEN_ED_P_2,
1199   VEX_LEN_EE_P_2,
1200   VEX_LEN_EF_P_2,
1201   VEX_LEN_F1_P_2,
1202   VEX_LEN_F2_P_2,
1203   VEX_LEN_F3_P_2,
1204   VEX_LEN_F4_P_2,
1205   VEX_LEN_F5_P_2,
1206   VEX_LEN_F6_P_2,
1207   VEX_LEN_F7_P_2,
1208   VEX_LEN_F8_P_2,
1209   VEX_LEN_F9_P_2,
1210   VEX_LEN_FA_P_2,
1211   VEX_LEN_FB_P_2,
1212   VEX_LEN_FC_P_2,
1213   VEX_LEN_FD_P_2,
1214   VEX_LEN_FE_P_2,
1215   VEX_LEN_3800_P_2,
1216   VEX_LEN_3801_P_2,
1217   VEX_LEN_3802_P_2,
1218   VEX_LEN_3803_P_2,
1219   VEX_LEN_3804_P_2,
1220   VEX_LEN_3805_P_2,
1221   VEX_LEN_3806_P_2,
1222   VEX_LEN_3807_P_2,
1223   VEX_LEN_3808_P_2,
1224   VEX_LEN_3809_P_2,
1225   VEX_LEN_380A_P_2,
1226   VEX_LEN_380B_P_2,
1227   VEX_LEN_3819_P_2_M_0,
1228   VEX_LEN_381A_P_2_M_0,
1229   VEX_LEN_381C_P_2,
1230   VEX_LEN_381D_P_2,
1231   VEX_LEN_381E_P_2,
1232   VEX_LEN_3820_P_2,
1233   VEX_LEN_3821_P_2,
1234   VEX_LEN_3822_P_2,
1235   VEX_LEN_3823_P_2,
1236   VEX_LEN_3824_P_2,
1237   VEX_LEN_3825_P_2,
1238   VEX_LEN_3828_P_2,
1239   VEX_LEN_3829_P_2,
1240   VEX_LEN_382A_P_2_M_0,
1241   VEX_LEN_382B_P_2,
1242   VEX_LEN_3830_P_2,
1243   VEX_LEN_3831_P_2,
1244   VEX_LEN_3832_P_2,
1245   VEX_LEN_3833_P_2,
1246   VEX_LEN_3834_P_2,
1247   VEX_LEN_3835_P_2,
1248   VEX_LEN_3837_P_2,
1249   VEX_LEN_3838_P_2,
1250   VEX_LEN_3839_P_2,
1251   VEX_LEN_383A_P_2,
1252   VEX_LEN_383B_P_2,
1253   VEX_LEN_383C_P_2,
1254   VEX_LEN_383D_P_2,
1255   VEX_LEN_383E_P_2,
1256   VEX_LEN_383F_P_2,
1257   VEX_LEN_3840_P_2,
1258   VEX_LEN_3841_P_2,
1259   VEX_LEN_38DB_P_2,
1260   VEX_LEN_38DC_P_2,
1261   VEX_LEN_38DD_P_2,
1262   VEX_LEN_38DE_P_2,
1263   VEX_LEN_38DF_P_2,
1264   VEX_LEN_3A06_P_2,
1265   VEX_LEN_3A0A_P_2,
1266   VEX_LEN_3A0B_P_2,
1267   VEX_LEN_3A0E_P_2,
1268   VEX_LEN_3A0F_P_2,
1269   VEX_LEN_3A14_P_2,
1270   VEX_LEN_3A15_P_2,
1271   VEX_LEN_3A16_P_2,
1272   VEX_LEN_3A17_P_2,
1273   VEX_LEN_3A18_P_2,
1274   VEX_LEN_3A19_P_2,
1275   VEX_LEN_3A20_P_2,
1276   VEX_LEN_3A21_P_2,
1277   VEX_LEN_3A22_P_2,
1278   VEX_LEN_3A41_P_2,
1279   VEX_LEN_3A42_P_2,
1280   VEX_LEN_3A44_P_2,
1281   VEX_LEN_3A4C_P_2,
1282   VEX_LEN_3A60_P_2,
1283   VEX_LEN_3A61_P_2,
1284   VEX_LEN_3A62_P_2,
1285   VEX_LEN_3A63_P_2,
1286   VEX_LEN_3A6A_P_2,
1287   VEX_LEN_3A6B_P_2,
1288   VEX_LEN_3A6E_P_2,
1289   VEX_LEN_3A6F_P_2,
1290   VEX_LEN_3A7A_P_2,
1291   VEX_LEN_3A7B_P_2,
1292   VEX_LEN_3A7E_P_2,
1293   VEX_LEN_3A7F_P_2,
1294   VEX_LEN_3ADF_P_2
1295 };
1296
1297 typedef void (*op_rtn) (int bytemode, int sizeflag);
1298
1299 struct dis386 {
1300   const char *name;
1301   struct
1302     {
1303       op_rtn rtn;
1304       int bytemode;
1305     } op[MAX_OPERANDS];
1306 };
1307
1308 /* Upper case letters in the instruction names here are macros.
1309    'A' => print 'b' if no register operands or suffix_always is true
1310    'B' => print 'b' if suffix_always is true
1311    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1312           size prefix
1313    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1314           suffix_always is true
1315    'E' => print 'e' if 32-bit form of jcxz
1316    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1317    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1318    'H' => print ",pt" or ",pn" branch hint
1319    'I' => honor following macro letter even in Intel mode (implemented only
1320           for some of the macro letters)
1321    'J' => print 'l'
1322    'K' => print 'd' or 'q' if rex prefix is present.
1323    'L' => print 'l' if suffix_always is true
1324    'M' => print 'r' if intel_mnemonic is false.
1325    'N' => print 'n' if instruction has no wait "prefix"
1326    'O' => print 'd' or 'o' (or 'q' in Intel mode)
1327    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
1328           or suffix_always is true.  print 'q' if rex prefix is present.
1329    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1330           is true
1331    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1332    'S' => print 'w', 'l' or 'q' if suffix_always is true
1333    'T' => print 'q' in 64bit mode and behave as 'P' otherwise
1334    'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
1335    'V' => print 'q' in 64bit mode and behave as 'S' otherwise
1336    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1337    'X' => print 's', 'd' depending on data16 prefix (for XMM)
1338    'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
1339           suffix_always is true.
1340    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
1341    '!' => change condition from true to false or from false to true.
1342    '%' => add 1 upper case letter to the macro.
1343
1344    2 upper case letter macros:
1345    "XY" => print 'x' or 'y' if no register operands or suffix_always
1346            is true.
1347    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1348    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
1349            or suffix_always is true
1350    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1351    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1352    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1353
1354    Many of the above letters print nothing in Intel mode.  See "putop"
1355    for the details.
1356
1357    Braces '{' and '}', and vertical bars '|', indicate alternative
1358    mnemonic strings for AT&T and Intel.  */
1359
1360 static const struct dis386 dis386[] = {
1361   /* 00 */
1362   { "addB",             { Eb, Gb } },
1363   { "addS",             { Ev, Gv } },
1364   { "addB",             { Gb, EbS } },
1365   { "addS",             { Gv, EvS } },
1366   { "addB",             { AL, Ib } },
1367   { "addS",             { eAX, Iv } },
1368   { X86_64_TABLE (X86_64_06) },
1369   { X86_64_TABLE (X86_64_07) },
1370   /* 08 */
1371   { "orB",              { Eb, Gb } },
1372   { "orS",              { Ev, Gv } },
1373   { "orB",              { Gb, EbS } },
1374   { "orS",              { Gv, EvS } },
1375   { "orB",              { AL, Ib } },
1376   { "orS",              { eAX, Iv } },
1377   { X86_64_TABLE (X86_64_0D) },
1378   { "(bad)",            { XX } },       /* 0x0f extended opcode escape */
1379   /* 10 */
1380   { "adcB",             { Eb, Gb } },
1381   { "adcS",             { Ev, Gv } },
1382   { "adcB",             { Gb, EbS } },
1383   { "adcS",             { Gv, EvS } },
1384   { "adcB",             { AL, Ib } },
1385   { "adcS",             { eAX, Iv } },
1386   { X86_64_TABLE (X86_64_16) },
1387   { X86_64_TABLE (X86_64_17) },
1388   /* 18 */
1389   { "sbbB",             { Eb, Gb } },
1390   { "sbbS",             { Ev, Gv } },
1391   { "sbbB",             { Gb, EbS } },
1392   { "sbbS",             { Gv, EvS } },
1393   { "sbbB",             { AL, Ib } },
1394   { "sbbS",             { eAX, Iv } },
1395   { X86_64_TABLE (X86_64_1E) },
1396   { X86_64_TABLE (X86_64_1F) },
1397   /* 20 */
1398   { "andB",             { Eb, Gb } },
1399   { "andS",             { Ev, Gv } },
1400   { "andB",             { Gb, EbS } },
1401   { "andS",             { Gv, EvS } },
1402   { "andB",             { AL, Ib } },
1403   { "andS",             { eAX, Iv } },
1404   { "(bad)",            { XX } },       /* SEG ES prefix */
1405   { X86_64_TABLE (X86_64_27) },
1406   /* 28 */
1407   { "subB",             { Eb, Gb } },
1408   { "subS",             { Ev, Gv } },
1409   { "subB",             { Gb, EbS } },
1410   { "subS",             { Gv, EvS } },
1411   { "subB",             { AL, Ib } },
1412   { "subS",             { eAX, Iv } },
1413   { "(bad)",            { XX } },       /* SEG CS prefix */
1414   { X86_64_TABLE (X86_64_2F) },
1415   /* 30 */
1416   { "xorB",             { Eb, Gb } },
1417   { "xorS",             { Ev, Gv } },
1418   { "xorB",             { Gb, EbS } },
1419   { "xorS",             { Gv, EvS } },
1420   { "xorB",             { AL, Ib } },
1421   { "xorS",             { eAX, Iv } },
1422   { "(bad)",            { XX } },       /* SEG SS prefix */
1423   { X86_64_TABLE (X86_64_37) },
1424   /* 38 */
1425   { "cmpB",             { Eb, Gb } },
1426   { "cmpS",             { Ev, Gv } },
1427   { "cmpB",             { Gb, EbS } },
1428   { "cmpS",             { Gv, EvS } },
1429   { "cmpB",             { AL, Ib } },
1430   { "cmpS",             { eAX, Iv } },
1431   { "(bad)",            { XX } },       /* SEG DS prefix */
1432   { X86_64_TABLE (X86_64_3F) },
1433   /* 40 */
1434   { "inc{S|}",          { RMeAX } },
1435   { "inc{S|}",          { RMeCX } },
1436   { "inc{S|}",          { RMeDX } },
1437   { "inc{S|}",          { RMeBX } },
1438   { "inc{S|}",          { RMeSP } },
1439   { "inc{S|}",          { RMeBP } },
1440   { "inc{S|}",          { RMeSI } },
1441   { "inc{S|}",          { RMeDI } },
1442   /* 48 */
1443   { "dec{S|}",          { RMeAX } },
1444   { "dec{S|}",          { RMeCX } },
1445   { "dec{S|}",          { RMeDX } },
1446   { "dec{S|}",          { RMeBX } },
1447   { "dec{S|}",          { RMeSP } },
1448   { "dec{S|}",          { RMeBP } },
1449   { "dec{S|}",          { RMeSI } },
1450   { "dec{S|}",          { RMeDI } },
1451   /* 50 */
1452   { "pushV",            { RMrAX } },
1453   { "pushV",            { RMrCX } },
1454   { "pushV",            { RMrDX } },
1455   { "pushV",            { RMrBX } },
1456   { "pushV",            { RMrSP } },
1457   { "pushV",            { RMrBP } },
1458   { "pushV",            { RMrSI } },
1459   { "pushV",            { RMrDI } },
1460   /* 58 */
1461   { "popV",             { RMrAX } },
1462   { "popV",             { RMrCX } },
1463   { "popV",             { RMrDX } },
1464   { "popV",             { RMrBX } },
1465   { "popV",             { RMrSP } },
1466   { "popV",             { RMrBP } },
1467   { "popV",             { RMrSI } },
1468   { "popV",             { RMrDI } },
1469   /* 60 */
1470   { X86_64_TABLE (X86_64_60) },
1471   { X86_64_TABLE (X86_64_61) },
1472   { X86_64_TABLE (X86_64_62) },
1473   { X86_64_TABLE (X86_64_63) },
1474   { "(bad)",            { XX } },       /* seg fs */
1475   { "(bad)",            { XX } },       /* seg gs */
1476   { "(bad)",            { XX } },       /* op size prefix */
1477   { "(bad)",            { XX } },       /* adr size prefix */
1478   /* 68 */
1479   { "pushT",            { Iq } },
1480   { "imulS",            { Gv, Ev, Iv } },
1481   { "pushT",            { sIb } },
1482   { "imulS",            { Gv, Ev, sIb } },
1483   { "ins{b|}",          { Ybr, indirDX } },
1484   { X86_64_TABLE (X86_64_6D) },
1485   { "outs{b|}",         { indirDXr, Xb } },
1486   { X86_64_TABLE (X86_64_6F) },
1487   /* 70 */
1488   { "joH",              { Jb, XX, cond_jump_flag } },
1489   { "jnoH",             { Jb, XX, cond_jump_flag } },
1490   { "jbH",              { Jb, XX, cond_jump_flag } },
1491   { "jaeH",             { Jb, XX, cond_jump_flag } },
1492   { "jeH",              { Jb, XX, cond_jump_flag } },
1493   { "jneH",             { Jb, XX, cond_jump_flag } },
1494   { "jbeH",             { Jb, XX, cond_jump_flag } },
1495   { "jaH",              { Jb, XX, cond_jump_flag } },
1496   /* 78 */
1497   { "jsH",              { Jb, XX, cond_jump_flag } },
1498   { "jnsH",             { Jb, XX, cond_jump_flag } },
1499   { "jpH",              { Jb, XX, cond_jump_flag } },
1500   { "jnpH",             { Jb, XX, cond_jump_flag } },
1501   { "jlH",              { Jb, XX, cond_jump_flag } },
1502   { "jgeH",             { Jb, XX, cond_jump_flag } },
1503   { "jleH",             { Jb, XX, cond_jump_flag } },
1504   { "jgH",              { Jb, XX, cond_jump_flag } },
1505   /* 80 */
1506   { REG_TABLE (REG_80) },
1507   { REG_TABLE (REG_81) },
1508   { "(bad)",            { XX } },
1509   { REG_TABLE (REG_82) },
1510   { "testB",            { Eb, Gb } },
1511   { "testS",            { Ev, Gv } },
1512   { "xchgB",            { Eb, Gb } },
1513   { "xchgS",            { Ev, Gv } },
1514   /* 88 */
1515   { "movB",             { Eb, Gb } },
1516   { "movS",             { Ev, Gv } },
1517   { "movB",             { Gb, EbS } },
1518   { "movS",             { Gv, EvS } },
1519   { "movD",             { Sv, Sw } },
1520   { MOD_TABLE (MOD_8D) },
1521   { "movD",             { Sw, Sv } },
1522   { REG_TABLE (REG_8F) },
1523   /* 90 */
1524   { PREFIX_TABLE (PREFIX_90) },
1525   { "xchgS",            { RMeCX, eAX } },
1526   { "xchgS",            { RMeDX, eAX } },
1527   { "xchgS",            { RMeBX, eAX } },
1528   { "xchgS",            { RMeSP, eAX } },
1529   { "xchgS",            { RMeBP, eAX } },
1530   { "xchgS",            { RMeSI, eAX } },
1531   { "xchgS",            { RMeDI, eAX } },
1532   /* 98 */
1533   { "cW{t|}R",          { XX } },
1534   { "cR{t|}O",          { XX } },
1535   { X86_64_TABLE (X86_64_9A) },
1536   { "(bad)",            { XX } },       /* fwait */
1537   { "pushfT",           { XX } },
1538   { "popfT",            { XX } },
1539   { "sahf",             { XX } },
1540   { "lahf",             { XX } },
1541   /* a0 */
1542   { "mov%LB",           { AL, Ob } },
1543   { "mov%LS",           { eAX, Ov } },
1544   { "mov%LB",           { Ob, AL } },
1545   { "mov%LS",           { Ov, eAX } },
1546   { "movs{b|}",         { Ybr, Xb } },
1547   { "movs{R|}",         { Yvr, Xv } },
1548   { "cmps{b|}",         { Xb, Yb } },
1549   { "cmps{R|}",         { Xv, Yv } },
1550   /* a8 */
1551   { "testB",            { AL, Ib } },
1552   { "testS",            { eAX, Iv } },
1553   { "stosB",            { Ybr, AL } },
1554   { "stosS",            { Yvr, eAX } },
1555   { "lodsB",            { ALr, Xb } },
1556   { "lodsS",            { eAXr, Xv } },
1557   { "scasB",            { AL, Yb } },
1558   { "scasS",            { eAX, Yv } },
1559   /* b0 */
1560   { "movB",             { RMAL, Ib } },
1561   { "movB",             { RMCL, Ib } },
1562   { "movB",             { RMDL, Ib } },
1563   { "movB",             { RMBL, Ib } },
1564   { "movB",             { RMAH, Ib } },
1565   { "movB",             { RMCH, Ib } },
1566   { "movB",             { RMDH, Ib } },
1567   { "movB",             { RMBH, Ib } },
1568   /* b8 */
1569   { "mov%LV",           { RMeAX, Iv64 } },
1570   { "mov%LV",           { RMeCX, Iv64 } },
1571   { "mov%LV",           { RMeDX, Iv64 } },
1572   { "mov%LV",           { RMeBX, Iv64 } },
1573   { "mov%LV",           { RMeSP, Iv64 } },
1574   { "mov%LV",           { RMeBP, Iv64 } },
1575   { "mov%LV",           { RMeSI, Iv64 } },
1576   { "mov%LV",           { RMeDI, Iv64 } },
1577   /* c0 */
1578   { REG_TABLE (REG_C0) },
1579   { REG_TABLE (REG_C1) },
1580   { "retT",             { Iw } },
1581   { "retT",             { XX } },
1582   { X86_64_TABLE (X86_64_C4) },
1583   { X86_64_TABLE (X86_64_C5) },
1584   { REG_TABLE (REG_C6) },
1585   { REG_TABLE (REG_C7) },
1586   /* c8 */
1587   { "enterT",           { Iw, Ib } },
1588   { "leaveT",           { XX } },
1589   { "Jret{|f}P",        { Iw } },
1590   { "Jret{|f}P",        { XX } },
1591   { "int3",             { XX } },
1592   { "int",              { Ib } },
1593   { X86_64_TABLE (X86_64_CE) },
1594   { "iretP",            { XX } },
1595   /* d0 */
1596   { REG_TABLE (REG_D0) },
1597   { REG_TABLE (REG_D1) },
1598   { REG_TABLE (REG_D2) },
1599   { REG_TABLE (REG_D3) },
1600   { X86_64_TABLE (X86_64_D4) },
1601   { X86_64_TABLE (X86_64_D5) },
1602   { "(bad)",            { XX } },
1603   { "xlat",             { DSBX } },
1604   /* d8 */
1605   { FLOAT },
1606   { FLOAT },
1607   { FLOAT },
1608   { FLOAT },
1609   { FLOAT },
1610   { FLOAT },
1611   { FLOAT },
1612   { FLOAT },
1613   /* e0 */
1614   { "loopneFH",         { Jb, XX, loop_jcxz_flag } },
1615   { "loopeFH",          { Jb, XX, loop_jcxz_flag } },
1616   { "loopFH",           { Jb, XX, loop_jcxz_flag } },
1617   { "jEcxzH",           { Jb, XX, loop_jcxz_flag } },
1618   { "inB",              { AL, Ib } },
1619   { "inG",              { zAX, Ib } },
1620   { "outB",             { Ib, AL } },
1621   { "outG",             { Ib, zAX } },
1622   /* e8 */
1623   { "callT",            { Jv } },
1624   { "jmpT",             { Jv } },
1625   { X86_64_TABLE (X86_64_EA) },
1626   { "jmp",              { Jb } },
1627   { "inB",              { AL, indirDX } },
1628   { "inG",              { zAX, indirDX } },
1629   { "outB",             { indirDX, AL } },
1630   { "outG",             { indirDX, zAX } },
1631   /* f0 */
1632   { "(bad)",            { XX } },       /* lock prefix */
1633   { "icebp",            { XX } },
1634   { "(bad)",            { XX } },       /* repne */
1635   { "(bad)",            { XX } },       /* repz */
1636   { "hlt",              { XX } },
1637   { "cmc",              { XX } },
1638   { REG_TABLE (REG_F6) },
1639   { REG_TABLE (REG_F7) },
1640   /* f8 */
1641   { "clc",              { XX } },
1642   { "stc",              { XX } },
1643   { "cli",              { XX } },
1644   { "sti",              { XX } },
1645   { "cld",              { XX } },
1646   { "std",              { XX } },
1647   { REG_TABLE (REG_FE) },
1648   { REG_TABLE (REG_FF) },
1649 };
1650
1651 static const struct dis386 dis386_twobyte[] = {
1652   /* 00 */
1653   { REG_TABLE (REG_0F00 ) },
1654   { REG_TABLE (REG_0F01 ) },
1655   { "larS",             { Gv, Ew } },
1656   { "lslS",             { Gv, Ew } },
1657   { "(bad)",            { XX } },
1658   { "syscall",          { XX } },
1659   { "clts",             { XX } },
1660   { "sysretP",          { XX } },
1661   /* 08 */
1662   { "invd",             { XX } },
1663   { "wbinvd",           { XX } },
1664   { "(bad)",            { XX } },
1665   { "ud2a",             { XX } },
1666   { "(bad)",            { XX } },
1667   { REG_TABLE (REG_0F0D) },
1668   { "femms",            { XX } },
1669   { "",                 { MX, EM, OPSUF } }, /* See OP_3DNowSuffix.  */
1670   /* 10 */
1671   { PREFIX_TABLE (PREFIX_0F10) },
1672   { PREFIX_TABLE (PREFIX_0F11) },
1673   { PREFIX_TABLE (PREFIX_0F12) },
1674   { MOD_TABLE (MOD_0F13) },
1675   { "unpcklpX",         { XM, EXx } },
1676   { "unpckhpX",         { XM, EXx } },
1677   { PREFIX_TABLE (PREFIX_0F16) },
1678   { MOD_TABLE (MOD_0F17) },
1679   /* 18 */
1680   { REG_TABLE (REG_0F18) },
1681   { "nopQ",             { Ev } },
1682   { "nopQ",             { Ev } },
1683   { "nopQ",             { Ev } },
1684   { "nopQ",             { Ev } },
1685   { "nopQ",             { Ev } },
1686   { "nopQ",             { Ev } },
1687   { "nopQ",             { Ev } },
1688   /* 20 */
1689   { MOD_TABLE (MOD_0F20) },
1690   { MOD_TABLE (MOD_0F21) },
1691   { MOD_TABLE (MOD_0F22) },
1692   { MOD_TABLE (MOD_0F23) },
1693   { MOD_TABLE (MOD_0F24) },
1694   { "(bad)",            { XX } },
1695   { MOD_TABLE (MOD_0F26) },
1696   { "(bad)",            { XX } },
1697   /* 28 */
1698   { "movapX",           { XM, EXx } },
1699   { "movapX",           { EXxS, XM } },
1700   { PREFIX_TABLE (PREFIX_0F2A) },
1701   { PREFIX_TABLE (PREFIX_0F2B) },
1702   { PREFIX_TABLE (PREFIX_0F2C) },
1703   { PREFIX_TABLE (PREFIX_0F2D) },
1704   { PREFIX_TABLE (PREFIX_0F2E) },
1705   { PREFIX_TABLE (PREFIX_0F2F) },
1706   /* 30 */
1707   { "wrmsr",            { XX } },
1708   { "rdtsc",            { XX } },
1709   { "rdmsr",            { XX } },
1710   { "rdpmc",            { XX } },
1711   { "sysenter",         { XX } },
1712   { "sysexit",          { XX } },
1713   { "(bad)",            { XX } },
1714   { "getsec",           { XX } },
1715   /* 38 */
1716   { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
1717   { "(bad)",            { XX } },
1718   { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
1719   { "(bad)",            { XX } },
1720   { "(bad)",            { XX } },
1721   { "(bad)",            { XX } },
1722   { "(bad)",            { XX } },
1723   { "(bad)",            { XX } },
1724   /* 40 */
1725   { "cmovoS",           { Gv, Ev } },
1726   { "cmovnoS",          { Gv, Ev } },
1727   { "cmovbS",           { Gv, Ev } },
1728   { "cmovaeS",          { Gv, Ev } },
1729   { "cmoveS",           { Gv, Ev } },
1730   { "cmovneS",          { Gv, Ev } },
1731   { "cmovbeS",          { Gv, Ev } },
1732   { "cmovaS",           { Gv, Ev } },
1733   /* 48 */
1734   { "cmovsS",           { Gv, Ev } },
1735   { "cmovnsS",          { Gv, Ev } },
1736   { "cmovpS",           { Gv, Ev } },
1737   { "cmovnpS",          { Gv, Ev } },
1738   { "cmovlS",           { Gv, Ev } },
1739   { "cmovgeS",          { Gv, Ev } },
1740   { "cmovleS",          { Gv, Ev } },
1741   { "cmovgS",           { Gv, Ev } },
1742   /* 50 */
1743   { MOD_TABLE (MOD_0F51) },
1744   { PREFIX_TABLE (PREFIX_0F51) },
1745   { PREFIX_TABLE (PREFIX_0F52) },
1746   { PREFIX_TABLE (PREFIX_0F53) },
1747   { "andpX",            { XM, EXx } },
1748   { "andnpX",           { XM, EXx } },
1749   { "orpX",             { XM, EXx } },
1750   { "xorpX",            { XM, EXx } },
1751   /* 58 */
1752   { PREFIX_TABLE (PREFIX_0F58) },
1753   { PREFIX_TABLE (PREFIX_0F59) },
1754   { PREFIX_TABLE (PREFIX_0F5A) },
1755   { PREFIX_TABLE (PREFIX_0F5B) },
1756   { PREFIX_TABLE (PREFIX_0F5C) },
1757   { PREFIX_TABLE (PREFIX_0F5D) },
1758   { PREFIX_TABLE (PREFIX_0F5E) },
1759   { PREFIX_TABLE (PREFIX_0F5F) },
1760   /* 60 */
1761   { PREFIX_TABLE (PREFIX_0F60) },
1762   { PREFIX_TABLE (PREFIX_0F61) },
1763   { PREFIX_TABLE (PREFIX_0F62) },
1764   { "packsswb",         { MX, EM } },
1765   { "pcmpgtb",          { MX, EM } },
1766   { "pcmpgtw",          { MX, EM } },
1767   { "pcmpgtd",          { MX, EM } },
1768   { "packuswb",         { MX, EM } },
1769   /* 68 */
1770   { "punpckhbw",        { MX, EM } },
1771   { "punpckhwd",        { MX, EM } },
1772   { "punpckhdq",        { MX, EM } },
1773   { "packssdw",         { MX, EM } },
1774   { PREFIX_TABLE (PREFIX_0F6C) },
1775   { PREFIX_TABLE (PREFIX_0F6D) },
1776   { "movK",             { MX, Edq } },
1777   { PREFIX_TABLE (PREFIX_0F6F) },
1778   /* 70 */
1779   { PREFIX_TABLE (PREFIX_0F70) },
1780   { REG_TABLE (REG_0F71) },
1781   { REG_TABLE (REG_0F72) },
1782   { REG_TABLE (REG_0F73) },
1783   { "pcmpeqb",          { MX, EM } },
1784   { "pcmpeqw",          { MX, EM } },
1785   { "pcmpeqd",          { MX, EM } },
1786   { "emms",             { XX } },
1787   /* 78 */
1788   { PREFIX_TABLE (PREFIX_0F78) },
1789   { PREFIX_TABLE (PREFIX_0F79) },
1790   { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
1791   { "(bad)",            { XX } },
1792   { PREFIX_TABLE (PREFIX_0F7C) },
1793   { PREFIX_TABLE (PREFIX_0F7D) },
1794   { PREFIX_TABLE (PREFIX_0F7E) },
1795   { PREFIX_TABLE (PREFIX_0F7F) },
1796   /* 80 */
1797   { "joH",              { Jv, XX, cond_jump_flag } },
1798   { "jnoH",             { Jv, XX, cond_jump_flag } },
1799   { "jbH",              { Jv, XX, cond_jump_flag } },
1800   { "jaeH",             { Jv, XX, cond_jump_flag } },
1801   { "jeH",              { Jv, XX, cond_jump_flag } },
1802   { "jneH",             { Jv, XX, cond_jump_flag } },
1803   { "jbeH",             { Jv, XX, cond_jump_flag } },
1804   { "jaH",              { Jv, XX, cond_jump_flag } },
1805   /* 88 */
1806   { "jsH",              { Jv, XX, cond_jump_flag } },
1807   { "jnsH",             { Jv, XX, cond_jump_flag } },
1808   { "jpH",              { Jv, XX, cond_jump_flag } },
1809   { "jnpH",             { Jv, XX, cond_jump_flag } },
1810   { "jlH",              { Jv, XX, cond_jump_flag } },
1811   { "jgeH",             { Jv, XX, cond_jump_flag } },
1812   { "jleH",             { Jv, XX, cond_jump_flag } },
1813   { "jgH",              { Jv, XX, cond_jump_flag } },
1814   /* 90 */
1815   { "seto",             { Eb } },
1816   { "setno",            { Eb } },
1817   { "setb",             { Eb } },
1818   { "setae",            { Eb } },
1819   { "sete",             { Eb } },
1820   { "setne",            { Eb } },
1821   { "setbe",            { Eb } },
1822   { "seta",             { Eb } },
1823   /* 98 */
1824   { "sets",             { Eb } },
1825   { "setns",            { Eb } },
1826   { "setp",             { Eb } },
1827   { "setnp",            { Eb } },
1828   { "setl",             { Eb } },
1829   { "setge",            { Eb } },
1830   { "setle",            { Eb } },
1831   { "setg",             { Eb } },
1832   /* a0 */
1833   { "pushT",            { fs } },
1834   { "popT",             { fs } },
1835   { "cpuid",            { XX } },
1836   { "btS",              { Ev, Gv } },
1837   { "shldS",            { Ev, Gv, Ib } },
1838   { "shldS",            { Ev, Gv, CL } },
1839   { REG_TABLE (REG_0FA6) },
1840   { REG_TABLE (REG_0FA7) },
1841   /* a8 */
1842   { "pushT",            { gs } },
1843   { "popT",             { gs } },
1844   { "rsm",              { XX } },
1845   { "btsS",             { Ev, Gv } },
1846   { "shrdS",            { Ev, Gv, Ib } },
1847   { "shrdS",            { Ev, Gv, CL } },
1848   { REG_TABLE (REG_0FAE) },
1849   { "imulS",            { Gv, Ev } },
1850   /* b0 */
1851   { "cmpxchgB",         { Eb, Gb } },
1852   { "cmpxchgS",         { Ev, Gv } },
1853   { MOD_TABLE (MOD_0FB2) },
1854   { "btrS",             { Ev, Gv } },
1855   { MOD_TABLE (MOD_0FB4) },
1856   { MOD_TABLE (MOD_0FB5) },
1857   { "movz{bR|x}",       { Gv, Eb } },
1858   { "movz{wR|x}",       { Gv, Ew } }, /* yes, there really is movzww ! */
1859   /* b8 */
1860   { PREFIX_TABLE (PREFIX_0FB8) },
1861   { "ud2b",             { XX } },
1862   { REG_TABLE (REG_0FBA) },
1863   { "btcS",             { Ev, Gv } },
1864   { "bsfS",             { Gv, Ev } },
1865   { PREFIX_TABLE (PREFIX_0FBD) },
1866   { "movs{bR|x}",       { Gv, Eb } },
1867   { "movs{wR|x}",       { Gv, Ew } }, /* yes, there really is movsww ! */
1868   /* c0 */
1869   { "xaddB",            { Eb, Gb } },
1870   { "xaddS",            { Ev, Gv } },
1871   { PREFIX_TABLE (PREFIX_0FC2) },
1872   { PREFIX_TABLE (PREFIX_0FC3) },
1873   { "pinsrw",           { MX, Edqw, Ib } },
1874   { "pextrw",           { Gdq, MS, Ib } },
1875   { "shufpX",           { XM, EXx, Ib } },
1876   { REG_TABLE (REG_0FC7) },
1877   /* c8 */
1878   { "bswap",            { RMeAX } },
1879   { "bswap",            { RMeCX } },
1880   { "bswap",            { RMeDX } },
1881   { "bswap",            { RMeBX } },
1882   { "bswap",            { RMeSP } },
1883   { "bswap",            { RMeBP } },
1884   { "bswap",            { RMeSI } },
1885   { "bswap",            { RMeDI } },
1886   /* d0 */
1887   { PREFIX_TABLE (PREFIX_0FD0) },
1888   { "psrlw",            { MX, EM } },
1889   { "psrld",            { MX, EM } },
1890   { "psrlq",            { MX, EM } },
1891   { "paddq",            { MX, EM } },
1892   { "pmullw",           { MX, EM } },
1893   { PREFIX_TABLE (PREFIX_0FD6) },
1894   { MOD_TABLE (MOD_0FD7) },
1895   /* d8 */
1896   { "psubusb",          { MX, EM } },
1897   { "psubusw",          { MX, EM } },
1898   { "pminub",           { MX, EM } },
1899   { "pand",             { MX, EM } },
1900   { "paddusb",          { MX, EM } },
1901   { "paddusw",          { MX, EM } },
1902   { "pmaxub",           { MX, EM } },
1903   { "pandn",            { MX, EM } },
1904   /* e0 */
1905   { "pavgb",            { MX, EM } },
1906   { "psraw",            { MX, EM } },
1907   { "psrad",            { MX, EM } },
1908   { "pavgw",            { MX, EM } },
1909   { "pmulhuw",          { MX, EM } },
1910   { "pmulhw",           { MX, EM } },
1911   { PREFIX_TABLE (PREFIX_0FE6) },
1912   { PREFIX_TABLE (PREFIX_0FE7) },
1913   /* e8 */
1914   { "psubsb",           { MX, EM } },
1915   { "psubsw",           { MX, EM } },
1916   { "pminsw",           { MX, EM } },
1917   { "por",              { MX, EM } },
1918   { "paddsb",           { MX, EM } },
1919   { "paddsw",           { MX, EM } },
1920   { "pmaxsw",           { MX, EM } },
1921   { "pxor",             { MX, EM } },
1922   /* f0 */
1923   { PREFIX_TABLE (PREFIX_0FF0) },
1924   { "psllw",            { MX, EM } },
1925   { "pslld",            { MX, EM } },
1926   { "psllq",            { MX, EM } },
1927   { "pmuludq",          { MX, EM } },
1928   { "pmaddwd",          { MX, EM } },
1929   { "psadbw",           { MX, EM } },
1930   { PREFIX_TABLE (PREFIX_0FF7) },
1931   /* f8 */
1932   { "psubb",            { MX, EM } },
1933   { "psubw",            { MX, EM } },
1934   { "psubd",            { MX, EM } },
1935   { "psubq",            { MX, EM } },
1936   { "paddb",            { MX, EM } },
1937   { "paddw",            { MX, EM } },
1938   { "paddd",            { MX, EM } },
1939   { "(bad)",            { XX } },
1940 };
1941
1942 static const unsigned char onebyte_has_modrm[256] = {
1943   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
1944   /*       -------------------------------        */
1945   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
1946   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
1947   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
1948   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
1949   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
1950   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
1951   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
1952   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
1953   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
1954   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
1955   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
1956   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
1957   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
1958   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
1959   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
1960   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
1961   /*       -------------------------------        */
1962   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
1963 };
1964
1965 static const unsigned char twobyte_has_modrm[256] = {
1966   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
1967   /*       -------------------------------        */
1968   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
1969   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
1970   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
1971   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
1972   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
1973   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
1974   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
1975   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
1976   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
1977   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
1978   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
1979   /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
1980   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
1981   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
1982   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
1983   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
1984   /*       -------------------------------        */
1985   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
1986 };
1987
1988 static char obuf[100];
1989 static char *obufp;
1990 static char *mnemonicendp;
1991 static char scratchbuf[100];
1992 static unsigned char *start_codep;
1993 static unsigned char *insn_codep;
1994 static unsigned char *codep;
1995 static const char *lock_prefix;
1996 static const char *data_prefix;
1997 static const char *addr_prefix;
1998 static const char *repz_prefix;
1999 static const char *repnz_prefix;
2000 static const char **all_prefixes[5];
2001 static disassemble_info *the_info;
2002 static struct
2003   {
2004     int mod;
2005     int reg;
2006     int rm;
2007   }
2008 modrm;
2009 static unsigned char need_modrm;
2010 static struct
2011   {
2012     int register_specifier;
2013     int length;
2014     int prefix;
2015     int w;
2016   }
2017 vex;
2018 static unsigned char need_vex;
2019 static unsigned char need_vex_reg;
2020 static unsigned char vex_w_done;
2021
2022 struct op
2023   {
2024     const char *name;
2025     unsigned int len;
2026   };
2027
2028 /* If we are accessing mod/rm/reg without need_modrm set, then the
2029    values are stale.  Hitting this abort likely indicates that you
2030    need to update onebyte_has_modrm or twobyte_has_modrm.  */
2031 #define MODRM_CHECK  if (!need_modrm) abort ()
2032
2033 static const char **names64;
2034 static const char **names32;
2035 static const char **names16;
2036 static const char **names8;
2037 static const char **names8rex;
2038 static const char **names_seg;
2039 static const char *index64;
2040 static const char *index32;
2041 static const char **index16;
2042
2043 static const char *intel_names64[] = {
2044   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2045   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2046 };
2047 static const char *intel_names32[] = {
2048   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2049   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2050 };
2051 static const char *intel_names16[] = {
2052   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2053   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2054 };
2055 static const char *intel_names8[] = {
2056   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2057 };
2058 static const char *intel_names8rex[] = {
2059   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2060   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2061 };
2062 static const char *intel_names_seg[] = {
2063   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2064 };
2065 static const char *intel_index64 = "riz";
2066 static const char *intel_index32 = "eiz";
2067 static const char *intel_index16[] = {
2068   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2069 };
2070
2071 static const char *att_names64[] = {
2072   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2073   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2074 };
2075 static const char *att_names32[] = {
2076   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2077   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2078 };
2079 static const char *att_names16[] = {
2080   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2081   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2082 };
2083 static const char *att_names8[] = {
2084   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2085 };
2086 static const char *att_names8rex[] = {
2087   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2088   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2089 };
2090 static const char *att_names_seg[] = {
2091   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2092 };
2093 static const char *att_index64 = "%riz";
2094 static const char *att_index32 = "%eiz";
2095 static const char *att_index16[] = {
2096   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2097 };
2098
2099 static const struct dis386 reg_table[][8] = {
2100   /* REG_80 */
2101   {
2102     { "addA",   { Eb, Ib } },
2103     { "orA",    { Eb, Ib } },
2104     { "adcA",   { Eb, Ib } },
2105     { "sbbA",   { Eb, Ib } },
2106     { "andA",   { Eb, Ib } },
2107     { "subA",   { Eb, Ib } },
2108     { "xorA",   { Eb, Ib } },
2109     { "cmpA",   { Eb, Ib } },
2110   },
2111   /* REG_81 */
2112   {
2113     { "addQ",   { Ev, Iv } },
2114     { "orQ",    { Ev, Iv } },
2115     { "adcQ",   { Ev, Iv } },
2116     { "sbbQ",   { Ev, Iv } },
2117     { "andQ",   { Ev, Iv } },
2118     { "subQ",   { Ev, Iv } },
2119     { "xorQ",   { Ev, Iv } },
2120     { "cmpQ",   { Ev, Iv } },
2121   },
2122   /* REG_82 */
2123   {
2124     { "addQ",   { Ev, sIb } },
2125     { "orQ",    { Ev, sIb } },
2126     { "adcQ",   { Ev, sIb } },
2127     { "sbbQ",   { Ev, sIb } },
2128     { "andQ",   { Ev, sIb } },
2129     { "subQ",   { Ev, sIb } },
2130     { "xorQ",   { Ev, sIb } },
2131     { "cmpQ",   { Ev, sIb } },
2132   },
2133   /* REG_8F */
2134   {
2135     { "popU",   { stackEv } },
2136     { XOP_8F_TABLE (XOP_09) },
2137     { "(bad)",  { XX } },
2138     { "(bad)",  { XX } },
2139     { "(bad)",  { XX } },
2140     { XOP_8F_TABLE (XOP_09) },
2141     { "(bad)",  { XX } },
2142     { "(bad)",  { XX } },
2143   },
2144   /* REG_C0 */
2145   {
2146     { "rolA",   { Eb, Ib } },
2147     { "rorA",   { Eb, Ib } },
2148     { "rclA",   { Eb, Ib } },
2149     { "rcrA",   { Eb, Ib } },
2150     { "shlA",   { Eb, Ib } },
2151     { "shrA",   { Eb, Ib } },
2152     { "(bad)",  { XX } },
2153     { "sarA",   { Eb, Ib } },
2154   },
2155   /* REG_C1 */
2156   {
2157     { "rolQ",   { Ev, Ib } },
2158     { "rorQ",   { Ev, Ib } },
2159     { "rclQ",   { Ev, Ib } },
2160     { "rcrQ",   { Ev, Ib } },
2161     { "shlQ",   { Ev, Ib } },
2162     { "shrQ",   { Ev, Ib } },
2163     { "(bad)",  { XX } },
2164     { "sarQ",   { Ev, Ib } },
2165   },
2166   /* REG_C6 */
2167   {
2168     { "movA",   { Eb, Ib } },
2169     { "(bad)",  { XX } },
2170     { "(bad)",  { XX } },
2171     { "(bad)",  { XX } },
2172     { "(bad)",  { XX } },
2173     { "(bad)",  { XX } },
2174     { "(bad)",  { XX } },
2175     { "(bad)",  { XX } },
2176   },
2177   /* REG_C7 */
2178   {
2179     { "movQ",   { Ev, Iv } },
2180     { "(bad)",  { XX } },
2181     { "(bad)",  { XX } },
2182     { "(bad)",  { XX } },
2183     { "(bad)",  { XX } },
2184     { "(bad)",  { XX } },
2185     { "(bad)",  { XX } },
2186     { "(bad)",  { XX } },
2187   },
2188   /* REG_D0 */
2189   {
2190     { "rolA",   { Eb, I1 } },
2191     { "rorA",   { Eb, I1 } },
2192     { "rclA",   { Eb, I1 } },
2193     { "rcrA",   { Eb, I1 } },
2194     { "shlA",   { Eb, I1 } },
2195     { "shrA",   { Eb, I1 } },
2196     { "(bad)",  { XX } },
2197     { "sarA",   { Eb, I1 } },
2198   },
2199   /* REG_D1 */
2200   {
2201     { "rolQ",   { Ev, I1 } },
2202     { "rorQ",   { Ev, I1 } },
2203     { "rclQ",   { Ev, I1 } },
2204     { "rcrQ",   { Ev, I1 } },
2205     { "shlQ",   { Ev, I1 } },
2206     { "shrQ",   { Ev, I1 } },
2207     { "(bad)",  { XX } },
2208     { "sarQ",   { Ev, I1 } },
2209   },
2210   /* REG_D2 */
2211   {
2212     { "rolA",   { Eb, CL } },
2213     { "rorA",   { Eb, CL } },
2214     { "rclA",   { Eb, CL } },
2215     { "rcrA",   { Eb, CL } },
2216     { "shlA",   { Eb, CL } },
2217     { "shrA",   { Eb, CL } },
2218     { "(bad)",  { XX } },
2219     { "sarA",   { Eb, CL } },
2220   },
2221   /* REG_D3 */
2222   {
2223     { "rolQ",   { Ev, CL } },
2224     { "rorQ",   { Ev, CL } },
2225     { "rclQ",   { Ev, CL } },
2226     { "rcrQ",   { Ev, CL } },
2227     { "shlQ",   { Ev, CL } },
2228     { "shrQ",   { Ev, CL } },
2229     { "(bad)",  { XX } },
2230     { "sarQ",   { Ev, CL } },
2231   },
2232   /* REG_F6 */
2233   {
2234     { "testA",  { Eb, Ib } },
2235     { "(bad)",  { XX } },
2236     { "notA",   { Eb } },
2237     { "negA",   { Eb } },
2238     { "mulA",   { Eb } },       /* Don't print the implicit %al register,  */
2239     { "imulA",  { Eb } },       /* to distinguish these opcodes from other */
2240     { "divA",   { Eb } },       /* mul/imul opcodes.  Do the same for div  */
2241     { "idivA",  { Eb } },       /* and idiv for consistency.               */
2242   },
2243   /* REG_F7 */
2244   {
2245     { "testQ",  { Ev, Iv } },
2246     { "(bad)",  { XX } },
2247     { "notQ",   { Ev } },
2248     { "negQ",   { Ev } },
2249     { "mulQ",   { Ev } },       /* Don't print the implicit register.  */
2250     { "imulQ",  { Ev } },
2251     { "divQ",   { Ev } },
2252     { "idivQ",  { Ev } },
2253   },
2254   /* REG_FE */
2255   {
2256     { "incA",   { Eb } },
2257     { "decA",   { Eb } },
2258     { "(bad)",  { XX } },
2259     { "(bad)",  { XX } },
2260     { "(bad)",  { XX } },
2261     { "(bad)",  { XX } },
2262     { "(bad)",  { XX } },
2263     { "(bad)",  { XX } },
2264   },
2265   /* REG_FF */
2266   {
2267     { "incQ",   { Ev } },
2268     { "decQ",   { Ev } },
2269     { "callT",  { indirEv } },
2270     { "JcallT", { indirEp } },
2271     { "jmpT",   { indirEv } },
2272     { "JjmpT",  { indirEp } },
2273     { "pushU",  { stackEv } },
2274     { "(bad)",  { XX } },
2275   },
2276   /* REG_0F00 */
2277   {
2278     { "sldtD",  { Sv } },
2279     { "strD",   { Sv } },
2280     { "lldt",   { Ew } },
2281     { "ltr",    { Ew } },
2282     { "verr",   { Ew } },
2283     { "verw",   { Ew } },
2284     { "(bad)",  { XX } },
2285     { "(bad)",  { XX } },
2286   },
2287   /* REG_0F01 */
2288   {
2289     { MOD_TABLE (MOD_0F01_REG_0) },
2290     { MOD_TABLE (MOD_0F01_REG_1) },
2291     { MOD_TABLE (MOD_0F01_REG_2) },
2292     { MOD_TABLE (MOD_0F01_REG_3) },
2293     { "smswD",  { Sv } },
2294     { "(bad)",  { XX } },
2295     { "lmsw",   { Ew } },
2296     { MOD_TABLE (MOD_0F01_REG_7) },
2297   },
2298   /* REG_0F0D */
2299   {
2300     { "prefetch",       { Eb } },
2301     { "prefetchw",      { Eb } },
2302     { "(bad)",          { XX } },
2303     { "(bad)",          { XX } },
2304     { "(bad)",          { XX } },
2305     { "(bad)",          { XX } },
2306     { "(bad)",          { XX } },
2307     { "(bad)",          { XX } },
2308   },
2309   /* REG_0F18 */
2310   {
2311     { MOD_TABLE (MOD_0F18_REG_0) },
2312     { MOD_TABLE (MOD_0F18_REG_1) },
2313     { MOD_TABLE (MOD_0F18_REG_2) },
2314     { MOD_TABLE (MOD_0F18_REG_3) },
2315     { "(bad)",  { XX } },
2316     { "(bad)",  { XX } },
2317     { "(bad)",  { XX } },
2318     { "(bad)",  { XX } },
2319   },
2320   /* REG_0F71 */
2321   {
2322     { "(bad)",  { XX } },
2323     { "(bad)",  { XX } },
2324     { MOD_TABLE (MOD_0F71_REG_2) },
2325     { "(bad)",  { XX } },
2326     { MOD_TABLE (MOD_0F71_REG_4) },
2327     { "(bad)",  { XX } },
2328     { MOD_TABLE (MOD_0F71_REG_6) },
2329     { "(bad)",  { XX } },
2330   },
2331   /* REG_0F72 */
2332   {
2333     { "(bad)",  { XX } },
2334     { "(bad)",  { XX } },
2335     { MOD_TABLE (MOD_0F72_REG_2) },
2336     { "(bad)",  { XX } },
2337     { MOD_TABLE (MOD_0F72_REG_4) },
2338     { "(bad)",  { XX } },
2339     { MOD_TABLE (MOD_0F72_REG_6) },
2340     { "(bad)",  { XX } },
2341   },
2342   /* REG_0F73 */
2343   {
2344     { "(bad)",  { XX } },
2345     { "(bad)",  { XX } },
2346     { MOD_TABLE (MOD_0F73_REG_2) },
2347     { MOD_TABLE (MOD_0F73_REG_3) },
2348     { "(bad)",  { XX } },
2349     { "(bad)",  { XX } },
2350     { MOD_TABLE (MOD_0F73_REG_6) },
2351     { MOD_TABLE (MOD_0F73_REG_7) },
2352   },
2353   /* REG_0FA6 */
2354   {
2355     { "montmul",        { { OP_0f07, 0 } } },
2356     { "xsha1",          { { OP_0f07, 0 } } },
2357     { "xsha256",        { { OP_0f07, 0 } } },
2358     { "(bad)",          { { OP_0f07, 0 } } },
2359     { "(bad)",          { { OP_0f07, 0 } } },
2360     { "(bad)",          { { OP_0f07, 0 } } },
2361     { "(bad)",          { { OP_0f07, 0 } } },
2362     { "(bad)",          { { OP_0f07, 0 } } },
2363   },
2364   /* REG_0FA7 */
2365   {
2366     { "xstore-rng",     { { OP_0f07, 0 } } },
2367     { "xcrypt-ecb",     { { OP_0f07, 0 } } },
2368     { "xcrypt-cbc",     { { OP_0f07, 0 } } },
2369     { "xcrypt-ctr",     { { OP_0f07, 0 } } },
2370     { "xcrypt-cfb",     { { OP_0f07, 0 } } },
2371     { "xcrypt-ofb",     { { OP_0f07, 0 } } },
2372     { "(bad)",          { { OP_0f07, 0 } } },
2373     { "(bad)",          { { OP_0f07, 0 } } },
2374   },
2375   /* REG_0FAE */
2376   {
2377     { MOD_TABLE (MOD_0FAE_REG_0) },
2378     { MOD_TABLE (MOD_0FAE_REG_1) },
2379     { MOD_TABLE (MOD_0FAE_REG_2) },
2380     { MOD_TABLE (MOD_0FAE_REG_3) },
2381     { MOD_TABLE (MOD_0FAE_REG_4) },
2382     { MOD_TABLE (MOD_0FAE_REG_5) },
2383     { MOD_TABLE (MOD_0FAE_REG_6) },
2384     { MOD_TABLE (MOD_0FAE_REG_7) },
2385   },
2386   /* REG_0FBA */
2387   {
2388     { "(bad)",  { XX } },
2389     { "(bad)",  { XX } },
2390     { "(bad)",  { XX } },
2391     { "(bad)",  { XX } },
2392     { "btQ",    { Ev, Ib } },
2393     { "btsQ",   { Ev, Ib } },
2394     { "btrQ",   { Ev, Ib } },
2395     { "btcQ",   { Ev, Ib } },
2396   },
2397   /* REG_0FC7 */
2398   {
2399     { "(bad)",  { XX } },
2400     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
2401     { "(bad)",  { XX } },
2402     { "(bad)",  { XX } },
2403     { "(bad)",  { XX } },
2404     { "(bad)",  { XX } },
2405     { MOD_TABLE (MOD_0FC7_REG_6) },
2406     { MOD_TABLE (MOD_0FC7_REG_7) },
2407   },
2408   /* REG_VEX_71 */
2409   {
2410     { "(bad)",  { XX } },
2411     { "(bad)",  { XX } },
2412     { MOD_TABLE (MOD_VEX_71_REG_2) },
2413     { "(bad)",  { XX } },
2414     { MOD_TABLE (MOD_VEX_71_REG_4) },
2415     { "(bad)",  { XX } },
2416     { MOD_TABLE (MOD_VEX_71_REG_6) },
2417     { "(bad)",  { XX } },
2418   },
2419   /* REG_VEX_72 */
2420   {
2421     { "(bad)",  { XX } },
2422     { "(bad)",  { XX } },
2423     { MOD_TABLE (MOD_VEX_72_REG_2) },
2424     { "(bad)",  { XX } },
2425     { MOD_TABLE (MOD_VEX_72_REG_4) },
2426     { "(bad)",  { XX } },
2427     { MOD_TABLE (MOD_VEX_72_REG_6) },
2428     { "(bad)",  { XX } },
2429   },
2430   /* REG_VEX_73 */
2431   {
2432     { "(bad)",  { XX } },
2433     { "(bad)",  { XX } },
2434     { MOD_TABLE (MOD_VEX_73_REG_2) },
2435     { MOD_TABLE (MOD_VEX_73_REG_3) },
2436     { "(bad)",  { XX } },
2437     { "(bad)",  { XX } },
2438     { MOD_TABLE (MOD_VEX_73_REG_6) },
2439     { MOD_TABLE (MOD_VEX_73_REG_7) },
2440   },
2441   /* REG_VEX_AE */
2442   {
2443     { "(bad)",  { XX } },
2444     { "(bad)",  { XX } },
2445     { MOD_TABLE (MOD_VEX_AE_REG_2) },
2446     { MOD_TABLE (MOD_VEX_AE_REG_3) },
2447     { "(bad)",  { XX } },
2448     { "(bad)",  { XX } },
2449     { "(bad)",  { XX } },
2450     { "(bad)",  { XX } },
2451   },
2452   /* REG_XOP_LWPCB */
2453   {
2454     { "llwpcb", { { OP_LWPCB_E, 0 } } },
2455     { "slwpcb", { { OP_LWPCB_E, 0 } } },
2456     { "(bad)",  { XX } },
2457     { "(bad)",  { XX } },
2458     { "(bad)",  { XX } },
2459     { "(bad)",  { XX } },
2460     { "(bad)",  { XX } },
2461     { "(bad)",  { XX } },
2462   },
2463   /* REG_XOP_LWP */
2464   {
2465     { "lwpins", { { OP_LWP_E, 0 }, Ed, { OP_LWP_I, 0 } } },
2466     { "lwpval", { { OP_LWP_E, 0 }, Ed, { OP_LWP_I, 0 } } },
2467     { "(bad)",  { XX } },
2468     { "(bad)",  { XX } },
2469     { "(bad)",  { XX } },
2470     { "(bad)",  { XX } },
2471     { "(bad)",  { XX } },
2472     { "(bad)",  { XX } },
2473   },
2474 };
2475
2476 static const struct dis386 prefix_table[][4] = {
2477   /* PREFIX_90 */
2478   {
2479     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2480     { "pause", { XX } },
2481     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2482     { "(bad)", { XX } },
2483   },
2484
2485   /* PREFIX_0F10 */
2486   {
2487     { "movups", { XM, EXx } },
2488     { "movss",  { XM, EXd } },
2489     { "movupd", { XM, EXx } },
2490     { "movsd",  { XM, EXq } },
2491   },
2492
2493   /* PREFIX_0F11 */
2494   {
2495     { "movups", { EXxS, XM } },
2496     { "movss",  { EXdS, XM } },
2497     { "movupd", { EXxS, XM } },
2498     { "movsd",  { EXqS, XM } },
2499   },
2500
2501   /* PREFIX_0F12 */
2502   {
2503     { MOD_TABLE (MOD_0F12_PREFIX_0) },
2504     { "movsldup", { XM, EXx } },
2505     { "movlpd", { XM, EXq } },
2506     { "movddup", { XM, EXq } },
2507   },
2508
2509   /* PREFIX_0F16 */
2510   {
2511     { MOD_TABLE (MOD_0F16_PREFIX_0) },
2512     { "movshdup", { XM, EXx } },
2513     { "movhpd", { XM, EXq } },
2514     { "(bad)",  { XX } },
2515   },
2516
2517   /* PREFIX_0F2A */
2518   {
2519     { "cvtpi2ps", { XM, EMCq } },
2520     { "cvtsi2ss%LQ", { XM, Ev } },
2521     { "cvtpi2pd", { XM, EMCq } },
2522     { "cvtsi2sd%LQ", { XM, Ev } },
2523   },
2524
2525   /* PREFIX_0F2B */
2526   {
2527     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
2528     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
2529     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
2530     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
2531   },
2532
2533   /* PREFIX_0F2C */
2534   {
2535     { "cvttps2pi", { MXC, EXq } },
2536     { "cvttss2siY", { Gv, EXd } },
2537     { "cvttpd2pi", { MXC, EXx } },
2538     { "cvttsd2siY", { Gv, EXq } },
2539   },
2540
2541   /* PREFIX_0F2D */
2542   {
2543     { "cvtps2pi", { MXC, EXq } },
2544     { "cvtss2siY", { Gv, EXd } },
2545     { "cvtpd2pi", { MXC, EXx } },
2546     { "cvtsd2siY", { Gv, EXq } },
2547   },
2548
2549   /* PREFIX_0F2E */
2550   {
2551     { "ucomiss",{ XM, EXd } },
2552     { "(bad)",  { XX } },
2553     { "ucomisd",{ XM, EXq } },
2554     { "(bad)",  { XX } },
2555   },
2556
2557   /* PREFIX_0F2F */
2558   {
2559     { "comiss", { XM, EXd } },
2560     { "(bad)",  { XX } },
2561     { "comisd", { XM, EXq } },
2562     { "(bad)",  { XX } },
2563   },
2564
2565   /* PREFIX_0F51 */
2566   {
2567     { "sqrtps", { XM, EXx } },
2568     { "sqrtss", { XM, EXd } },
2569     { "sqrtpd", { XM, EXx } },
2570     { "sqrtsd", { XM, EXq } },
2571   },
2572
2573   /* PREFIX_0F52 */
2574   {
2575     { "rsqrtps",{ XM, EXx } },
2576     { "rsqrtss",{ XM, EXd } },
2577     { "(bad)",  { XX } },
2578     { "(bad)",  { XX } },
2579   },
2580
2581   /* PREFIX_0F53 */
2582   {
2583     { "rcpps",  { XM, EXx } },
2584     { "rcpss",  { XM, EXd } },
2585     { "(bad)",  { XX } },
2586     { "(bad)",  { XX } },
2587   },
2588
2589   /* PREFIX_0F58 */
2590   {
2591     { "addps", { XM, EXx } },
2592     { "addss", { XM, EXd } },
2593     { "addpd", { XM, EXx } },
2594     { "addsd", { XM, EXq } },
2595   },
2596
2597   /* PREFIX_0F59 */
2598   {
2599     { "mulps",  { XM, EXx } },
2600     { "mulss",  { XM, EXd } },
2601     { "mulpd",  { XM, EXx } },
2602     { "mulsd",  { XM, EXq } },
2603   },
2604
2605   /* PREFIX_0F5A */
2606   {
2607     { "cvtps2pd", { XM, EXq } },
2608     { "cvtss2sd", { XM, EXd } },
2609     { "cvtpd2ps", { XM, EXx } },
2610     { "cvtsd2ss", { XM, EXq } },
2611   },
2612
2613   /* PREFIX_0F5B */
2614   {
2615     { "cvtdq2ps", { XM, EXx } },
2616     { "cvttps2dq", { XM, EXx } },
2617     { "cvtps2dq", { XM, EXx } },
2618     { "(bad)",  { XX } },
2619   },
2620
2621   /* PREFIX_0F5C */
2622   {
2623     { "subps",  { XM, EXx } },
2624     { "subss",  { XM, EXd } },
2625     { "subpd",  { XM, EXx } },
2626     { "subsd",  { XM, EXq } },
2627   },
2628
2629   /* PREFIX_0F5D */
2630   {
2631     { "minps",  { XM, EXx } },
2632     { "minss",  { XM, EXd } },
2633     { "minpd",  { XM, EXx } },
2634     { "minsd",  { XM, EXq } },
2635   },
2636
2637   /* PREFIX_0F5E */
2638   {
2639     { "divps",  { XM, EXx } },
2640     { "divss",  { XM, EXd } },
2641     { "divpd",  { XM, EXx } },
2642     { "divsd",  { XM, EXq } },
2643   },
2644
2645   /* PREFIX_0F5F */
2646   {
2647     { "maxps",  { XM, EXx } },
2648     { "maxss",  { XM, EXd } },
2649     { "maxpd",  { XM, EXx } },
2650     { "maxsd",  { XM, EXq } },
2651   },
2652
2653   /* PREFIX_0F60 */
2654   {
2655     { "punpcklbw",{ MX, EMd } },
2656     { "(bad)",  { XX } },
2657     { "punpcklbw",{ MX, EMx } },
2658     { "(bad)",  { XX } },
2659   },
2660
2661   /* PREFIX_0F61 */
2662   {
2663     { "punpcklwd",{ MX, EMd } },
2664     { "(bad)",  { XX } },
2665     { "punpcklwd",{ MX, EMx } },
2666     { "(bad)",  { XX } },
2667   },
2668
2669   /* PREFIX_0F62 */
2670   {
2671     { "punpckldq",{ MX, EMd } },
2672     { "(bad)",  { XX } },
2673     { "punpckldq",{ MX, EMx } },
2674     { "(bad)",  { XX } },
2675   },
2676
2677   /* PREFIX_0F6C */
2678   {
2679     { "(bad)",  { XX } },
2680     { "(bad)",  { XX } },
2681     { "punpcklqdq", { XM, EXx } },
2682     { "(bad)",  { XX } },
2683   },
2684
2685   /* PREFIX_0F6D */
2686   {
2687     { "(bad)",  { XX } },
2688     { "(bad)",  { XX } },
2689     { "punpckhqdq", { XM, EXx } },
2690     { "(bad)",  { XX } },
2691   },
2692
2693   /* PREFIX_0F6F */
2694   {
2695     { "movq",   { MX, EM } },
2696     { "movdqu", { XM, EXx } },
2697     { "movdqa", { XM, EXx } },
2698     { "(bad)",  { XX } },
2699   },
2700
2701   /* PREFIX_0F70 */
2702   {
2703     { "pshufw", { MX, EM, Ib } },
2704     { "pshufhw",{ XM, EXx, Ib } },
2705     { "pshufd", { XM, EXx, Ib } },
2706     { "pshuflw",{ XM, EXx, Ib } },
2707   },
2708
2709   /* PREFIX_0F73_REG_3 */
2710   {
2711     { "(bad)",  { XX } },
2712     { "(bad)",  { XX } },
2713     { "psrldq", { XS, Ib } },
2714     { "(bad)",  { XX } },
2715   },
2716
2717   /* PREFIX_0F73_REG_7 */
2718   {
2719     { "(bad)",  { XX } },
2720     { "(bad)",  { XX } },
2721     { "pslldq", { XS, Ib } },
2722     { "(bad)",  { XX } },
2723   },
2724
2725   /* PREFIX_0F78 */
2726   {
2727     {"vmread",  { Em, Gm } },
2728     {"(bad)",   { XX } },
2729     {"extrq",   { XS, Ib, Ib } },
2730     {"insertq", { XM, XS, Ib, Ib } },
2731   },
2732
2733   /* PREFIX_0F79 */
2734   {
2735     {"vmwrite", { Gm, Em } },
2736     {"(bad)",   { XX } },
2737     {"extrq",   { XM, XS } },
2738     {"insertq", { XM, XS } },
2739   },
2740
2741   /* PREFIX_0F7C */
2742   {
2743     { "(bad)",  { XX } },
2744     { "(bad)",  { XX } },
2745     { "haddpd", { XM, EXx } },
2746     { "haddps", { XM, EXx } },
2747   },
2748
2749   /* PREFIX_0F7D */
2750   {
2751     { "(bad)",  { XX } },
2752     { "(bad)",  { XX } },
2753     { "hsubpd", { XM, EXx } },
2754     { "hsubps", { XM, EXx } },
2755   },
2756
2757   /* PREFIX_0F7E */
2758   {
2759     { "movK",   { Edq, MX } },
2760     { "movq",   { XM, EXq } },
2761     { "movK",   { Edq, XM } },
2762     { "(bad)",  { XX } },
2763   },
2764
2765   /* PREFIX_0F7F */
2766   {
2767     { "movq",   { EMS, MX } },
2768     { "movdqu", { EXxS, XM } },
2769     { "movdqa", { EXxS, XM } },
2770     { "(bad)",  { XX } },
2771   },
2772
2773   /* PREFIX_0FB8 */
2774   {
2775     { "(bad)", { XX } },
2776     { "popcntS", { Gv, Ev } },
2777     { "(bad)", { XX } },
2778     { "(bad)", { XX } },
2779   },
2780
2781   /* PREFIX_0FBD */
2782   {
2783     { "bsrS",   { Gv, Ev } },
2784     { "lzcntS", { Gv, Ev } },
2785     { "bsrS",   { Gv, Ev } },
2786     { "(bad)",  { XX } },
2787   },
2788
2789   /* PREFIX_0FC2 */
2790   {
2791     { "cmpps",  { XM, EXx, CMP } },
2792     { "cmpss",  { XM, EXd, CMP } },
2793     { "cmppd",  { XM, EXx, CMP } },
2794     { "cmpsd",  { XM, EXq, CMP } },
2795   },
2796
2797   /* PREFIX_0FC3 */
2798   {
2799     { "movntiS", { Ma, Gv } },
2800     { "(bad)",  { XX } },
2801     { "(bad)",  { XX } },
2802     { "(bad)",  { XX } },
2803   },
2804
2805   /* PREFIX_0FC7_REG_6 */
2806   {
2807     { "vmptrld",{ Mq } },
2808     { "vmxon",  { Mq } },
2809     { "vmclear",{ Mq } },
2810     { "(bad)",  { XX } },
2811   },
2812
2813   /* PREFIX_0FD0 */
2814   {
2815     { "(bad)",  { XX } },
2816     { "(bad)",  { XX } },
2817     { "addsubpd", { XM, EXx } },
2818     { "addsubps", { XM, EXx } },
2819   },
2820
2821   /* PREFIX_0FD6 */
2822   {
2823     { "(bad)",  { XX } },
2824     { "movq2dq",{ XM, MS } },
2825     { "movq",   { EXqS, XM } },
2826     { "movdq2q",{ MX, XS } },
2827   },
2828
2829   /* PREFIX_0FE6 */
2830   {
2831     { "(bad)",  { XX } },
2832     { "cvtdq2pd", { XM, EXq } },
2833     { "cvttpd2dq", { XM, EXx } },
2834     { "cvtpd2dq", { XM, EXx } },
2835   },
2836
2837   /* PREFIX_0FE7 */
2838   {
2839     { "movntq", { Mq, MX } },
2840     { "(bad)",  { XX } },
2841     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
2842     { "(bad)",  { XX } },
2843   },
2844
2845   /* PREFIX_0FF0 */
2846   {
2847     { "(bad)",  { XX } },
2848     { "(bad)",  { XX } },
2849     { "(bad)",  { XX } },
2850     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
2851   },
2852
2853   /* PREFIX_0FF7 */
2854   {
2855     { "maskmovq", { MX, MS } },
2856     { "(bad)",  { XX } },
2857     { "maskmovdqu", { XM, XS } },
2858     { "(bad)",  { XX } },
2859   },
2860
2861   /* PREFIX_0F3810 */
2862   {
2863     { "(bad)",  { XX } },
2864     { "(bad)",  { XX } },
2865     { "pblendvb", { XM, EXx, XMM0 } },
2866     { "(bad)",  { XX } },
2867   },
2868
2869   /* PREFIX_0F3814 */
2870   {
2871     { "(bad)",  { XX } },
2872     { "(bad)",  { XX } },
2873     { "blendvps", { XM, EXx, XMM0 } },
2874     { "(bad)",  { XX } },
2875   },
2876
2877   /* PREFIX_0F3815 */
2878   {
2879     { "(bad)",  { XX } },
2880     { "(bad)",  { XX } },
2881     { "blendvpd", { XM, EXx, XMM0 } },
2882     { "(bad)",  { XX } },
2883   },
2884
2885   /* PREFIX_0F3817 */
2886   {
2887     { "(bad)",  { XX } },
2888     { "(bad)",  { XX } },
2889     { "ptest",  { XM, EXx } },
2890     { "(bad)",  { XX } },
2891   },
2892
2893   /* PREFIX_0F3820 */
2894   {
2895     { "(bad)",  { XX } },
2896     { "(bad)",  { XX } },
2897     { "pmovsxbw", { XM, EXq } },
2898     { "(bad)",  { XX } },
2899   },
2900
2901   /* PREFIX_0F3821 */
2902   {
2903     { "(bad)",  { XX } },
2904     { "(bad)",  { XX } },
2905     { "pmovsxbd", { XM, EXd } },
2906     { "(bad)",  { XX } },
2907   },
2908
2909   /* PREFIX_0F3822 */
2910   {
2911     { "(bad)",  { XX } },
2912     { "(bad)",  { XX } },
2913     { "pmovsxbq", { XM, EXw } },
2914     { "(bad)",  { XX } },
2915   },
2916
2917   /* PREFIX_0F3823 */
2918   {
2919     { "(bad)",  { XX } },
2920     { "(bad)",  { XX } },
2921     { "pmovsxwd", { XM, EXq } },
2922     { "(bad)",  { XX } },
2923   },
2924
2925   /* PREFIX_0F3824 */
2926   {
2927     { "(bad)",  { XX } },
2928     { "(bad)",  { XX } },
2929     { "pmovsxwq", { XM, EXd } },
2930     { "(bad)",  { XX } },
2931   },
2932
2933   /* PREFIX_0F3825 */
2934   {
2935     { "(bad)",  { XX } },
2936     { "(bad)",  { XX } },
2937     { "pmovsxdq", { XM, EXq } },
2938     { "(bad)",  { XX } },
2939   },
2940
2941   /* PREFIX_0F3828 */
2942   {
2943     { "(bad)",  { XX } },
2944     { "(bad)",  { XX } },
2945     { "pmuldq", { XM, EXx } },
2946     { "(bad)",  { XX } },
2947   },
2948
2949   /* PREFIX_0F3829 */
2950   {
2951     { "(bad)",  { XX } },
2952     { "(bad)",  { XX } },
2953     { "pcmpeqq", { XM, EXx } },
2954     { "(bad)",  { XX } },
2955   },
2956
2957   /* PREFIX_0F382A */
2958   {
2959     { "(bad)",  { XX } },
2960     { "(bad)",  { XX } },
2961     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
2962     { "(bad)",  { XX } },
2963   },
2964
2965   /* PREFIX_0F382B */
2966   {
2967     { "(bad)",  { XX } },
2968     { "(bad)",  { XX } },
2969     { "packusdw", { XM, EXx } },
2970     { "(bad)",  { XX } },
2971   },
2972
2973   /* PREFIX_0F3830 */
2974   {
2975     { "(bad)",  { XX } },
2976     { "(bad)",  { XX } },
2977     { "pmovzxbw", { XM, EXq } },
2978     { "(bad)",  { XX } },
2979   },
2980
2981   /* PREFIX_0F3831 */
2982   {
2983     { "(bad)",  { XX } },
2984     { "(bad)",  { XX } },
2985     { "pmovzxbd", { XM, EXd } },
2986     { "(bad)",  { XX } },
2987   },
2988
2989   /* PREFIX_0F3832 */
2990   {
2991     { "(bad)",  { XX } },
2992     { "(bad)",  { XX } },
2993     { "pmovzxbq", { XM, EXw } },
2994     { "(bad)",  { XX } },
2995   },
2996
2997   /* PREFIX_0F3833 */
2998   {
2999     { "(bad)",  { XX } },
3000     { "(bad)",  { XX } },
3001     { "pmovzxwd", { XM, EXq } },
3002     { "(bad)",  { XX } },
3003   },
3004
3005   /* PREFIX_0F3834 */
3006   {
3007     { "(bad)",  { XX } },
3008     { "(bad)",  { XX } },
3009     { "pmovzxwq", { XM, EXd } },
3010     { "(bad)",  { XX } },
3011   },
3012
3013   /* PREFIX_0F3835 */
3014   {
3015     { "(bad)",  { XX } },
3016     { "(bad)",  { XX } },
3017     { "pmovzxdq", { XM, EXq } },
3018     { "(bad)",  { XX } },
3019   },
3020
3021   /* PREFIX_0F3837 */
3022   {
3023     { "(bad)",  { XX } },
3024     { "(bad)",  { XX } },
3025     { "pcmpgtq", { XM, EXx } },
3026     { "(bad)",  { XX } },
3027   },
3028
3029   /* PREFIX_0F3838 */
3030   {
3031     { "(bad)",  { XX } },
3032     { "(bad)",  { XX } },
3033     { "pminsb", { XM, EXx } },
3034     { "(bad)",  { XX } },
3035   },
3036
3037   /* PREFIX_0F3839 */
3038   {
3039     { "(bad)",  { XX } },
3040     { "(bad)",  { XX } },
3041     { "pminsd", { XM, EXx } },
3042     { "(bad)",  { XX } },
3043   },
3044
3045   /* PREFIX_0F383A */
3046   {
3047     { "(bad)",  { XX } },
3048     { "(bad)",  { XX } },
3049     { "pminuw", { XM, EXx } },
3050     { "(bad)",  { XX } },
3051   },
3052
3053   /* PREFIX_0F383B */
3054   {
3055     { "(bad)",  { XX } },
3056     { "(bad)",  { XX } },
3057     { "pminud", { XM, EXx } },
3058     { "(bad)",  { XX } },
3059   },
3060
3061   /* PREFIX_0F383C */
3062   {
3063     { "(bad)",  { XX } },
3064     { "(bad)",  { XX } },
3065     { "pmaxsb", { XM, EXx } },
3066     { "(bad)",  { XX } },
3067   },
3068
3069   /* PREFIX_0F383D */
3070   {
3071     { "(bad)",  { XX } },
3072     { "(bad)",  { XX } },
3073     { "pmaxsd", { XM, EXx } },
3074     { "(bad)",  { XX } },
3075   },
3076
3077   /* PREFIX_0F383E */
3078   {
3079     { "(bad)",  { XX } },
3080     { "(bad)",  { XX } },
3081     { "pmaxuw", { XM, EXx } },
3082     { "(bad)",  { XX } },
3083   },
3084
3085   /* PREFIX_0F383F */
3086   {
3087     { "(bad)",  { XX } },
3088     { "(bad)",  { XX } },
3089     { "pmaxud", { XM, EXx } },
3090     { "(bad)",  { XX } },
3091   },
3092
3093   /* PREFIX_0F3840 */
3094   {
3095     { "(bad)",  { XX } },
3096     { "(bad)",  { XX } },
3097     { "pmulld", { XM, EXx } },
3098     { "(bad)",  { XX } },
3099   },
3100
3101   /* PREFIX_0F3841 */
3102   {
3103     { "(bad)",  { XX } },
3104     { "(bad)",  { XX } },
3105     { "phminposuw", { XM, EXx } },
3106     { "(bad)",  { XX } },
3107   },
3108
3109   /* PREFIX_0F3880 */
3110   {
3111     { "(bad)",  { XX } },
3112     { "(bad)",  { XX } },
3113     { "invept", { Gm, Mo } },
3114     { "(bad)",  { XX } },
3115   },
3116
3117   /* PREFIX_0F3881 */
3118   {
3119     { "(bad)",  { XX } },
3120     { "(bad)",  { XX } },
3121     { "invvpid", { Gm, Mo } },
3122     { "(bad)",  { XX } },
3123   },
3124
3125   /* PREFIX_0F38DB */
3126   {
3127     { "(bad)",  { XX } },
3128     { "(bad)",  { XX } },
3129     { "aesimc", { XM, EXx } },
3130     { "(bad)",  { XX } },
3131   },
3132
3133   /* PREFIX_0F38DC */
3134   {
3135     { "(bad)",  { XX } },
3136     { "(bad)",  { XX } },
3137     { "aesenc", { XM, EXx } },
3138     { "(bad)",  { XX } },
3139   },
3140
3141   /* PREFIX_0F38DD */
3142   {
3143     { "(bad)",  { XX } },
3144     { "(bad)",  { XX } },
3145     { "aesenclast", { XM, EXx } },
3146     { "(bad)",  { XX } },
3147   },
3148
3149   /* PREFIX_0F38DE */
3150   {
3151     { "(bad)",  { XX } },
3152     { "(bad)",  { XX } },
3153     { "aesdec", { XM, EXx } },
3154     { "(bad)",  { XX } },
3155   },
3156
3157   /* PREFIX_0F38DF */
3158   {
3159     { "(bad)",  { XX } },
3160     { "(bad)",  { XX } },
3161     { "aesdeclast", { XM, EXx } },
3162     { "(bad)",  { XX } },
3163   },
3164
3165   /* PREFIX_0F38F0 */
3166   {
3167     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
3168     { "(bad)",  { XX } },
3169     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
3170     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } } },
3171   },
3172
3173   /* PREFIX_0F38F1 */
3174   {
3175     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
3176     { "(bad)",  { XX } },
3177     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
3178     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } } },
3179   },
3180
3181   /* PREFIX_0F3A08 */
3182   {
3183     { "(bad)",  { XX } },
3184     { "(bad)",  { XX } },
3185     { "roundps", { XM, EXx, Ib } },
3186     { "(bad)",  { XX } },
3187   },
3188
3189   /* PREFIX_0F3A09 */
3190   {
3191     { "(bad)",  { XX } },
3192     { "(bad)",  { XX } },
3193     { "roundpd", { XM, EXx, Ib } },
3194     { "(bad)",  { XX } },
3195   },
3196
3197   /* PREFIX_0F3A0A */
3198   {
3199     { "(bad)",  { XX } },
3200     { "(bad)",  { XX } },
3201     { "roundss", { XM, EXd, Ib } },
3202     { "(bad)",  { XX } },
3203   },
3204
3205   /* PREFIX_0F3A0B */
3206   {
3207     { "(bad)",  { XX } },
3208     { "(bad)",  { XX } },
3209     { "roundsd", { XM, EXq, Ib } },
3210     { "(bad)",  { XX } },
3211   },
3212
3213   /* PREFIX_0F3A0C */
3214   {
3215     { "(bad)",  { XX } },
3216     { "(bad)",  { XX } },
3217     { "blendps", { XM, EXx, Ib } },
3218     { "(bad)",  { XX } },
3219   },
3220
3221   /* PREFIX_0F3A0D */
3222   {
3223     { "(bad)",  { XX } },
3224     { "(bad)",  { XX } },
3225     { "blendpd", { XM, EXx, Ib } },
3226     { "(bad)",  { XX } },
3227   },
3228
3229   /* PREFIX_0F3A0E */
3230   {
3231     { "(bad)",  { XX } },
3232     { "(bad)",  { XX } },
3233     { "pblendw", { XM, EXx, Ib } },
3234     { "(bad)",  { XX } },
3235   },
3236
3237   /* PREFIX_0F3A14 */
3238   {
3239     { "(bad)",  { XX } },
3240     { "(bad)",  { XX } },
3241     { "pextrb", { Edqb, XM, Ib } },
3242     { "(bad)",  { XX } },
3243   },
3244
3245   /* PREFIX_0F3A15 */
3246   {
3247     { "(bad)",  { XX } },
3248     { "(bad)",  { XX } },
3249     { "pextrw", { Edqw, XM, Ib } },
3250     { "(bad)",  { XX } },
3251   },
3252
3253   /* PREFIX_0F3A16 */
3254   {
3255     { "(bad)",  { XX } },
3256     { "(bad)",  { XX } },
3257     { "pextrK", { Edq, XM, Ib } },
3258     { "(bad)",  { XX } },
3259   },
3260
3261   /* PREFIX_0F3A17 */
3262   {
3263     { "(bad)",  { XX } },
3264     { "(bad)",  { XX } },
3265     { "extractps", { Edqd, XM, Ib } },
3266     { "(bad)",  { XX } },
3267   },
3268
3269   /* PREFIX_0F3A20 */
3270   {
3271     { "(bad)",  { XX } },
3272     { "(bad)",  { XX } },
3273     { "pinsrb", { XM, Edqb, Ib } },
3274     { "(bad)",  { XX } },
3275   },
3276
3277   /* PREFIX_0F3A21 */
3278   {
3279     { "(bad)",  { XX } },
3280     { "(bad)",  { XX } },
3281     { "insertps", { XM, EXd, Ib } },
3282     { "(bad)",  { XX } },
3283   },
3284
3285   /* PREFIX_0F3A22 */
3286   {
3287     { "(bad)",  { XX } },
3288     { "(bad)",  { XX } },
3289     { "pinsrK", { XM, Edq, Ib } },
3290     { "(bad)",  { XX } },
3291   },
3292
3293   /* PREFIX_0F3A40 */
3294   {
3295     { "(bad)",  { XX } },
3296     { "(bad)",  { XX } },
3297     { "dpps",   { XM, EXx, Ib } },
3298     { "(bad)",  { XX } },
3299   },
3300
3301   /* PREFIX_0F3A41 */
3302   {
3303     { "(bad)",  { XX } },
3304     { "(bad)",  { XX } },
3305     { "dppd",   { XM, EXx, Ib } },
3306     { "(bad)",  { XX } },
3307   },
3308
3309   /* PREFIX_0F3A42 */
3310   {
3311     { "(bad)",  { XX } },
3312     { "(bad)",  { XX } },
3313     { "mpsadbw", { XM, EXx, Ib } },
3314     { "(bad)",  { XX } },
3315   },
3316
3317   /* PREFIX_0F3A44 */
3318   {
3319     { "(bad)",  { XX } },
3320     { "(bad)",  { XX } },
3321     { "pclmulqdq", { XM, EXx, PCLMUL } },
3322     { "(bad)",  { XX } },
3323   },
3324
3325   /* PREFIX_0F3A60 */
3326   {
3327     { "(bad)",  { XX } },
3328     { "(bad)",  { XX } },
3329     { "pcmpestrm", { XM, EXx, Ib } },
3330     { "(bad)",  { XX } },
3331   },
3332
3333   /* PREFIX_0F3A61 */
3334   {
3335     { "(bad)",  { XX } },
3336     { "(bad)",  { XX } },
3337     { "pcmpestri", { XM, EXx, Ib } },
3338     { "(bad)",  { XX } },
3339   },
3340
3341   /* PREFIX_0F3A62 */
3342   {
3343     { "(bad)",  { XX } },
3344     { "(bad)",  { XX } },
3345     { "pcmpistrm", { XM, EXx, Ib } },
3346     { "(bad)",  { XX } },
3347   },
3348
3349   /* PREFIX_0F3A63 */
3350   {
3351     { "(bad)",  { XX } },
3352     { "(bad)",  { XX } },
3353     { "pcmpistri", { XM, EXx, Ib } },
3354     { "(bad)",  { XX } },
3355   },
3356
3357   /* PREFIX_0F3ADF */
3358   {
3359     { "(bad)",  { XX } },
3360     { "(bad)",  { XX } },
3361     { "aeskeygenassist", { XM, EXx, Ib } },
3362     { "(bad)",  { XX } },
3363   },
3364
3365   /* PREFIX_VEX_10 */
3366   {
3367     { "vmovups", { XM, EXx } },
3368     { VEX_LEN_TABLE (VEX_LEN_10_P_1) },
3369     { "vmovupd", { XM, EXx } },
3370     { VEX_LEN_TABLE (VEX_LEN_10_P_3) },
3371   },
3372
3373   /* PREFIX_VEX_11 */
3374   {
3375     { "vmovups", { EXxS, XM } },
3376     { VEX_LEN_TABLE (VEX_LEN_11_P_1) },
3377     { "vmovupd", { EXxS, XM } },
3378     { VEX_LEN_TABLE (VEX_LEN_11_P_3) },
3379   },
3380
3381   /* PREFIX_VEX_12 */
3382   {
3383     { MOD_TABLE (MOD_VEX_12_PREFIX_0) },
3384     { "vmovsldup", { XM, EXx } },
3385     { VEX_LEN_TABLE (VEX_LEN_12_P_2) },
3386     { "vmovddup", { XM, EXymmq } },
3387   },
3388
3389   /* PREFIX_VEX_16 */
3390   {
3391     { MOD_TABLE (MOD_VEX_16_PREFIX_0) },
3392     { "vmovshdup", { XM, EXx } },
3393     { VEX_LEN_TABLE (VEX_LEN_16_P_2) },
3394     { "(bad)",  { XX } },
3395   },
3396
3397   /* PREFIX_VEX_2A */
3398   {
3399     { "(bad)",  { XX } },
3400     { VEX_LEN_TABLE (VEX_LEN_2A_P_1) },
3401     { "(bad)",  { XX } },
3402     { VEX_LEN_TABLE (VEX_LEN_2A_P_3) },
3403   },
3404
3405   /* PREFIX_VEX_2C */
3406   {
3407     { "(bad)",  { XX } },
3408     { VEX_LEN_TABLE (VEX_LEN_2C_P_1) },
3409     { "(bad)",  { XX } },
3410     { VEX_LEN_TABLE (VEX_LEN_2C_P_3) },
3411   },
3412
3413   /* PREFIX_VEX_2D */
3414   {
3415     { "(bad)",  { XX } },
3416     { VEX_LEN_TABLE (VEX_LEN_2D_P_1) },
3417     { "(bad)",  { XX } },
3418     { VEX_LEN_TABLE (VEX_LEN_2D_P_3) },
3419   },
3420
3421   /* PREFIX_VEX_2E */
3422   {
3423     { VEX_LEN_TABLE (VEX_LEN_2E_P_0) },
3424     { "(bad)",  { XX } },
3425     { VEX_LEN_TABLE (VEX_LEN_2E_P_2) },
3426     { "(bad)",  { XX } },
3427   },
3428
3429   /* PREFIX_VEX_2F */
3430   {
3431     { VEX_LEN_TABLE (VEX_LEN_2F_P_0) },
3432     { "(bad)",  { XX } },
3433     { VEX_LEN_TABLE (VEX_LEN_2F_P_2) },
3434     { "(bad)",  { XX } },
3435   },
3436
3437   /* PREFIX_VEX_51 */
3438   {
3439     { "vsqrtps", { XM, EXx } },
3440     { VEX_LEN_TABLE (VEX_LEN_51_P_1) },
3441     { "vsqrtpd", { XM, EXx } },
3442     { VEX_LEN_TABLE (VEX_LEN_51_P_3) },
3443   },
3444
3445   /* PREFIX_VEX_52 */
3446   {
3447     { "vrsqrtps", { XM, EXx } },
3448     { VEX_LEN_TABLE (VEX_LEN_52_P_1) },
3449     { "(bad)",  { XX } },
3450     { "(bad)",  { XX } },
3451   },
3452
3453   /* PREFIX_VEX_53 */
3454   {
3455     { "vrcpps", { XM, EXx } },
3456     { VEX_LEN_TABLE (VEX_LEN_53_P_1) },
3457     { "(bad)",  { XX } },
3458     { "(bad)",  { XX } },
3459   },
3460
3461   /* PREFIX_VEX_58 */
3462   {
3463     { "vaddps", { XM, Vex, EXx } },
3464     { VEX_LEN_TABLE (VEX_LEN_58_P_1) },
3465     { "vaddpd", { XM, Vex, EXx } },
3466     { VEX_LEN_TABLE (VEX_LEN_58_P_3) },
3467   },
3468
3469   /* PREFIX_VEX_59 */
3470   {
3471     { "vmulps", { XM, Vex, EXx } },
3472     { VEX_LEN_TABLE (VEX_LEN_59_P_1) },
3473     { "vmulpd", { XM, Vex, EXx } },
3474     { VEX_LEN_TABLE (VEX_LEN_59_P_3) },
3475   },
3476
3477   /* PREFIX_VEX_5A */
3478   {
3479     { "vcvtps2pd", { XM, EXxmmq } },
3480     { VEX_LEN_TABLE (VEX_LEN_5A_P_1) },
3481     { "vcvtpd2ps%XY", { XMM, EXx } },
3482     { VEX_LEN_TABLE (VEX_LEN_5A_P_3) },
3483   },
3484
3485   /* PREFIX_VEX_5B */
3486   {
3487     { "vcvtdq2ps", { XM, EXx } },
3488     { "vcvttps2dq", { XM, EXx } },
3489     { "vcvtps2dq", { XM, EXx } },
3490     { "(bad)",  { XX } },
3491   },
3492
3493   /* PREFIX_VEX_5C */
3494   {
3495     { "vsubps", { XM, Vex, EXx } },
3496     { VEX_LEN_TABLE (VEX_LEN_5C_P_1) },
3497     { "vsubpd", { XM, Vex, EXx } },
3498     { VEX_LEN_TABLE (VEX_LEN_5C_P_3) },
3499   },
3500
3501   /* PREFIX_VEX_5D */
3502   {
3503     { "vminps", { XM, Vex, EXx } },
3504     { VEX_LEN_TABLE (VEX_LEN_5D_P_1) },
3505     { "vminpd", { XM, Vex, EXx } },
3506     { VEX_LEN_TABLE (VEX_LEN_5D_P_3) },
3507   },
3508
3509   /* PREFIX_VEX_5E */
3510   {
3511     { "vdivps", { XM, Vex, EXx } },
3512     { VEX_LEN_TABLE (VEX_LEN_5E_P_1) },
3513     { "vdivpd", { XM, Vex, EXx } },
3514     { VEX_LEN_TABLE (VEX_LEN_5E_P_3) },
3515   },
3516
3517   /* PREFIX_VEX_5F */
3518   {
3519     { "vmaxps", { XM, Vex, EXx } },
3520     { VEX_LEN_TABLE (VEX_LEN_5F_P_1) },
3521     { "vmaxpd", { XM, Vex, EXx } },
3522     { VEX_LEN_TABLE (VEX_LEN_5F_P_3) },
3523   },
3524
3525   /* PREFIX_VEX_60 */
3526   {
3527     { "(bad)",  { XX } },
3528     { "(bad)",  { XX } },
3529     { VEX_LEN_TABLE (VEX_LEN_60_P_2) },
3530     { "(bad)",  { XX } },
3531   },
3532
3533   /* PREFIX_VEX_61 */
3534   {
3535     { "(bad)",  { XX } },
3536     { "(bad)",  { XX } },
3537     { VEX_LEN_TABLE (VEX_LEN_61_P_2) },
3538     { "(bad)",  { XX } },
3539   },
3540
3541   /* PREFIX_VEX_62 */
3542   {
3543     { "(bad)",  { XX } },
3544     { "(bad)",  { XX } },
3545     { VEX_LEN_TABLE (VEX_LEN_62_P_2) },
3546     { "(bad)",  { XX } },
3547   },
3548
3549   /* PREFIX_VEX_63 */
3550   {
3551     { "(bad)",  { XX } },
3552     { "(bad)",  { XX } },
3553     { VEX_LEN_TABLE (VEX_LEN_63_P_2) },
3554     { "(bad)",  { XX } },
3555   },
3556
3557   /* PREFIX_VEX_64 */
3558   {
3559     { "(bad)",  { XX } },
3560     { "(bad)",  { XX } },
3561     { VEX_LEN_TABLE (VEX_LEN_64_P_2) },
3562     { "(bad)",  { XX } },
3563   },
3564
3565   /* PREFIX_VEX_65 */
3566   {
3567     { "(bad)",  { XX } },
3568     { "(bad)",  { XX } },
3569     { VEX_LEN_TABLE (VEX_LEN_65_P_2) },
3570     { "(bad)",  { XX } },
3571   },
3572
3573   /* PREFIX_VEX_66 */
3574   {
3575     { "(bad)",  { XX } },
3576     { "(bad)",  { XX } },
3577     { VEX_LEN_TABLE (VEX_LEN_66_P_2) },
3578     { "(bad)",  { XX } },
3579   },
3580
3581   /* PREFIX_VEX_67 */
3582   {
3583     { "(bad)",  { XX } },
3584     { "(bad)",  { XX } },
3585     { VEX_LEN_TABLE (VEX_LEN_67_P_2) },
3586     { "(bad)",  { XX } },
3587   },
3588
3589   /* PREFIX_VEX_68 */
3590   {
3591     { "(bad)",  { XX } },
3592     { "(bad)",  { XX } },
3593     { VEX_LEN_TABLE (VEX_LEN_68_P_2) },
3594     { "(bad)",  { XX } },
3595   },
3596
3597   /* PREFIX_VEX_69 */
3598   {
3599     { "(bad)",  { XX } },
3600     { "(bad)",  { XX } },
3601     { VEX_LEN_TABLE (VEX_LEN_69_P_2) },
3602     { "(bad)",  { XX } },
3603   },
3604
3605   /* PREFIX_VEX_6A */
3606   {
3607     { "(bad)",  { XX } },
3608     { "(bad)",  { XX } },
3609     { VEX_LEN_TABLE (VEX_LEN_6A_P_2) },
3610     { "(bad)",  { XX } },
3611   },
3612
3613   /* PREFIX_VEX_6B */
3614   {
3615     { "(bad)",  { XX } },
3616     { "(bad)",  { XX } },
3617     { VEX_LEN_TABLE (VEX_LEN_6B_P_2) },
3618     { "(bad)",  { XX } },
3619   },
3620
3621   /* PREFIX_VEX_6C */
3622   {
3623     { "(bad)",  { XX } },
3624     { "(bad)",  { XX } },
3625     { VEX_LEN_TABLE (VEX_LEN_6C_P_2) },
3626     { "(bad)",  { XX } },
3627   },
3628
3629   /* PREFIX_VEX_6D */
3630   {
3631     { "(bad)",  { XX } },
3632     { "(bad)",  { XX } },
3633     { VEX_LEN_TABLE (VEX_LEN_6D_P_2) },
3634     { "(bad)",  { XX } },
3635   },
3636
3637   /* PREFIX_VEX_6E */
3638   {
3639     { "(bad)",  { XX } },
3640     { "(bad)",  { XX } },
3641     { VEX_LEN_TABLE (VEX_LEN_6E_P_2) },
3642     { "(bad)",  { XX } },
3643   },
3644
3645   /* PREFIX_VEX_6F */
3646   {
3647     { "(bad)",  { XX } },
3648     { "vmovdqu", { XM, EXx } },
3649     { "vmovdqa", { XM, EXx } },
3650     { "(bad)",  { XX } },
3651   },
3652
3653   /* PREFIX_VEX_70 */
3654   {
3655     { "(bad)",  { XX } },
3656     { VEX_LEN_TABLE (VEX_LEN_70_P_1) },
3657     { VEX_LEN_TABLE (VEX_LEN_70_P_2) },
3658     { VEX_LEN_TABLE (VEX_LEN_70_P_3) },
3659   },
3660
3661   /* PREFIX_VEX_71_REG_2 */
3662   {
3663     { "(bad)",  { XX } },
3664     { "(bad)",  { XX } },
3665     { VEX_LEN_TABLE (VEX_LEN_71_R_2_P_2) },
3666     { "(bad)",  { XX } },
3667   },
3668
3669   /* PREFIX_VEX_71_REG_4 */
3670   {
3671     { "(bad)",  { XX } },
3672     { "(bad)",  { XX } },
3673     { VEX_LEN_TABLE (VEX_LEN_71_R_4_P_2) },
3674     { "(bad)",  { XX } },
3675   },
3676
3677   /* PREFIX_VEX_71_REG_6 */
3678   {
3679     { "(bad)",  { XX } },
3680     { "(bad)",  { XX } },
3681     { VEX_LEN_TABLE (VEX_LEN_71_R_6_P_2) },
3682     { "(bad)",  { XX } },
3683   },
3684
3685   /* PREFIX_VEX_72_REG_2 */
3686   {
3687     { "(bad)",  { XX } },
3688     { "(bad)",  { XX } },
3689     { VEX_LEN_TABLE (VEX_LEN_72_R_2_P_2) },
3690     { "(bad)",  { XX } },
3691   },
3692
3693   /* PREFIX_VEX_72_REG_4 */
3694   {
3695     { "(bad)",  { XX } },
3696     { "(bad)",  { XX } },
3697     { VEX_LEN_TABLE (VEX_LEN_72_R_4_P_2) },
3698     { "(bad)",  { XX } },
3699   },
3700
3701   /* PREFIX_VEX_72_REG_6 */
3702   {
3703     { "(bad)",  { XX } },
3704     { "(bad)",  { XX } },
3705     { VEX_LEN_TABLE (VEX_LEN_72_R_6_P_2) },
3706     { "(bad)",  { XX } },
3707   },
3708
3709   /* PREFIX_VEX_73_REG_2 */
3710   {
3711     { "(bad)",  { XX } },
3712     { "(bad)",  { XX } },
3713     { VEX_LEN_TABLE (VEX_LEN_73_R_2_P_2) },
3714     { "(bad)",  { XX } },
3715   },
3716
3717   /* PREFIX_VEX_73_REG_3 */
3718   {
3719     { "(bad)",  { XX } },
3720     { "(bad)",  { XX } },
3721     { VEX_LEN_TABLE (VEX_LEN_73_R_3_P_2) },
3722     { "(bad)",  { XX } },
3723   },
3724
3725   /* PREFIX_VEX_73_REG_6 */
3726   {
3727     { "(bad)",  { XX } },
3728     { "(bad)",  { XX } },
3729     { VEX_LEN_TABLE (VEX_LEN_73_R_6_P_2) },
3730     { "(bad)",  { XX } },
3731   },
3732
3733   /* PREFIX_VEX_73_REG_7 */
3734   {
3735     { "(bad)",  { XX } },
3736     { "(bad)",  { XX } },
3737     { VEX_LEN_TABLE (VEX_LEN_73_R_7_P_2) },
3738     { "(bad)",  { XX } },
3739   },
3740
3741   /* PREFIX_VEX_74 */
3742   {
3743     { "(bad)",  { XX } },
3744     { "(bad)",  { XX } },
3745     { VEX_LEN_TABLE (VEX_LEN_74_P_2) },
3746     { "(bad)",  { XX } },
3747   },
3748
3749   /* PREFIX_VEX_75 */
3750   {
3751     { "(bad)",  { XX } },
3752     { "(bad)",  { XX } },
3753     { VEX_LEN_TABLE (VEX_LEN_75_P_2) },
3754     { "(bad)",  { XX } },
3755   },
3756
3757   /* PREFIX_VEX_76 */
3758   {
3759     { "(bad)",  { XX } },
3760     { "(bad)",  { XX } },
3761     { VEX_LEN_TABLE (VEX_LEN_76_P_2) },
3762     { "(bad)",  { XX } },
3763   },
3764
3765   /* PREFIX_VEX_77 */
3766   {
3767     { "",       { VZERO } },
3768     { "(bad)",  { XX } },
3769     { "(bad)",  { XX } },
3770     { "(bad)",  { XX } },
3771   },
3772
3773   /* PREFIX_VEX_7C */
3774   {
3775     { "(bad)",  { XX } },
3776     { "(bad)",  { XX } },
3777     { "vhaddpd", { XM, Vex, EXx } },
3778     { "vhaddps", { XM, Vex, EXx } },
3779   },
3780
3781   /* PREFIX_VEX_7D */
3782   {
3783     { "(bad)",  { XX } },
3784     { "(bad)",  { XX } },
3785     { "vhsubpd", { XM, Vex, EXx } },
3786     { "vhsubps", { XM, Vex, EXx } },
3787   },
3788
3789   /* PREFIX_VEX_7E */
3790   {
3791     { "(bad)",  { XX } },
3792     { VEX_LEN_TABLE (VEX_LEN_7E_P_1) },
3793     { VEX_LEN_TABLE (VEX_LEN_7E_P_2) },
3794     { "(bad)",  { XX } },
3795   },
3796
3797   /* PREFIX_VEX_7F */
3798   {
3799     { "(bad)",  { XX } },
3800     { "vmovdqu", { EXxS, XM } },
3801     { "vmovdqa", { EXxS, XM } },
3802     { "(bad)",  { XX } },
3803   },
3804
3805   /* PREFIX_VEX_C2 */
3806   {
3807     { "vcmpps", { XM, Vex, EXx, VCMP } },
3808     { VEX_LEN_TABLE (VEX_LEN_C2_P_1) },
3809     { "vcmppd", { XM, Vex, EXx, VCMP } },
3810     { VEX_LEN_TABLE (VEX_LEN_C2_P_3) },
3811   },
3812
3813   /* PREFIX_VEX_C4 */
3814   {
3815     { "(bad)",  { XX } },
3816     { "(bad)",  { XX } },
3817     { VEX_LEN_TABLE (VEX_LEN_C4_P_2) },
3818     { "(bad)",  { XX } },
3819   },
3820
3821   /* PREFIX_VEX_C5 */
3822   {
3823     { "(bad)",  { XX } },
3824     { "(bad)",  { XX } },
3825     { VEX_LEN_TABLE (VEX_LEN_C5_P_2) },
3826     { "(bad)",  { XX } },
3827   },
3828
3829   /* PREFIX_VEX_D0 */
3830   {
3831     { "(bad)",  { XX } },
3832     { "(bad)",  { XX } },
3833     { "vaddsubpd", { XM, Vex, EXx } },
3834     { "vaddsubps", { XM, Vex, EXx } },
3835   },
3836
3837   /* PREFIX_VEX_D1 */
3838   {
3839     { "(bad)",  { XX } },
3840     { "(bad)",  { XX } },
3841     { VEX_LEN_TABLE (VEX_LEN_D1_P_2) },
3842     { "(bad)",  { XX } },
3843   },
3844
3845   /* PREFIX_VEX_D2 */
3846   {
3847     { "(bad)",  { XX } },
3848     { "(bad)",  { XX } },
3849     { VEX_LEN_TABLE (VEX_LEN_D2_P_2) },
3850     { "(bad)",  { XX } },
3851   },
3852
3853   /* PREFIX_VEX_D3 */
3854   {
3855     { "(bad)",  { XX } },
3856     { "(bad)",  { XX } },
3857     { VEX_LEN_TABLE (VEX_LEN_D3_P_2) },
3858     { "(bad)",  { XX } },
3859   },
3860
3861   /* PREFIX_VEX_D4 */
3862   {
3863     { "(bad)",  { XX } },
3864     { "(bad)",  { XX } },
3865     { VEX_LEN_TABLE (VEX_LEN_D4_P_2) },
3866     { "(bad)",  { XX } },
3867   },
3868
3869   /* PREFIX_VEX_D5 */
3870   {
3871     { "(bad)",  { XX } },
3872     { "(bad)",  { XX } },
3873     { VEX_LEN_TABLE (VEX_LEN_D5_P_2) },
3874     { "(bad)",  { XX } },
3875   },
3876
3877   /* PREFIX_VEX_D6 */
3878   {
3879     { "(bad)",  { XX } },
3880     { "(bad)",  { XX } },
3881     { VEX_LEN_TABLE (VEX_LEN_D6_P_2) },
3882     { "(bad)",  { XX } },
3883   },
3884
3885   /* PREFIX_VEX_D7 */
3886   {
3887     { "(bad)",  { XX } },
3888     { "(bad)",  { XX } },
3889     { MOD_TABLE (MOD_VEX_D7_PREFIX_2) },
3890     { "(bad)",  { XX } },
3891   },
3892
3893   /* PREFIX_VEX_D8 */
3894   {
3895     { "(bad)",  { XX } },
3896     { "(bad)",  { XX } },
3897     { VEX_LEN_TABLE (VEX_LEN_D8_P_2) },
3898     { "(bad)",  { XX } },
3899   },
3900
3901   /* PREFIX_VEX_D9 */
3902   {
3903     { "(bad)",  { XX } },
3904     { "(bad)",  { XX } },
3905     { VEX_LEN_TABLE (VEX_LEN_D9_P_2) },
3906     { "(bad)",  { XX } },
3907   },
3908
3909   /* PREFIX_VEX_DA */
3910   {
3911     { "(bad)",  { XX } },
3912     { "(bad)",  { XX } },
3913     { VEX_LEN_TABLE (VEX_LEN_DA_P_2) },
3914     { "(bad)",  { XX } },
3915   },
3916
3917   /* PREFIX_VEX_DB */
3918   {
3919     { "(bad)",  { XX } },
3920     { "(bad)",  { XX } },
3921     { VEX_LEN_TABLE (VEX_LEN_DB_P_2) },
3922     { "(bad)",  { XX } },
3923   },
3924
3925   /* PREFIX_VEX_DC */
3926   {
3927     { "(bad)",  { XX } },
3928     { "(bad)",  { XX } },
3929     { VEX_LEN_TABLE (VEX_LEN_DC_P_2) },
3930     { "(bad)",  { XX } },
3931   },
3932
3933   /* PREFIX_VEX_DD */
3934   {
3935     { "(bad)",  { XX } },
3936     { "(bad)",  { XX } },
3937     { VEX_LEN_TABLE (VEX_LEN_DD_P_2) },
3938     { "(bad)",  { XX } },
3939   },
3940
3941   /* PREFIX_VEX_DE */
3942   {
3943     { "(bad)",  { XX } },
3944     { "(bad)",  { XX } },
3945     { VEX_LEN_TABLE (VEX_LEN_DE_P_2) },
3946     { "(bad)",  { XX } },
3947   },
3948
3949   /* PREFIX_VEX_DF */
3950   {
3951     { "(bad)",  { XX } },
3952     { "(bad)",  { XX } },
3953     { VEX_LEN_TABLE (VEX_LEN_DF_P_2) },
3954     { "(bad)",  { XX } },
3955   },
3956
3957   /* PREFIX_VEX_E0 */
3958   {
3959     { "(bad)",  { XX } },
3960     { "(bad)",  { XX } },
3961     { VEX_LEN_TABLE (VEX_LEN_E0_P_2) },
3962     { "(bad)",  { XX } },
3963   },
3964
3965   /* PREFIX_VEX_E1 */
3966   {
3967     { "(bad)",  { XX } },
3968     { "(bad)",  { XX } },
3969     { VEX_LEN_TABLE (VEX_LEN_E1_P_2) },
3970     { "(bad)",  { XX } },
3971   },
3972
3973   /* PREFIX_VEX_E2 */
3974   {
3975     { "(bad)",  { XX } },
3976     { "(bad)",  { XX } },
3977     { VEX_LEN_TABLE (VEX_LEN_E2_P_2) },
3978     { "(bad)",  { XX } },
3979   },
3980
3981   /* PREFIX_VEX_E3 */
3982   {
3983     { "(bad)",  { XX } },
3984     { "(bad)",  { XX } },
3985     { VEX_LEN_TABLE (VEX_LEN_E3_P_2) },
3986     { "(bad)",  { XX } },
3987   },
3988
3989   /* PREFIX_VEX_E4 */
3990   {
3991     { "(bad)",  { XX } },
3992     { "(bad)",  { XX } },
3993     { VEX_LEN_TABLE (VEX_LEN_E4_P_2) },
3994     { "(bad)",  { XX } },
3995   },
3996
3997   /* PREFIX_VEX_E5 */
3998   {
3999     { "(bad)",  { XX } },
4000     { "(bad)",  { XX } },
4001     { VEX_LEN_TABLE (VEX_LEN_E5_P_2) },
4002     { "(bad)",  { XX } },
4003   },
4004
4005   /* PREFIX_VEX_E6 */
4006   {
4007     { "(bad)",  { XX } },
4008     { "vcvtdq2pd", { XM, EXxmmq } },
4009     { "vcvttpd2dq%XY", { XMM, EXx } },
4010     { "vcvtpd2dq%XY", { XMM, EXx } },
4011   },
4012
4013   /* PREFIX_VEX_E7 */
4014   {
4015     { "(bad)",  { XX } },
4016     { "(bad)",  { XX } },
4017     { MOD_TABLE (MOD_VEX_E7_PREFIX_2) },
4018     { "(bad)",  { XX } },
4019   },
4020
4021   /* PREFIX_VEX_E8 */
4022   {
4023     { "(bad)",  { XX } },
4024     { "(bad)",  { XX } },
4025     { VEX_LEN_TABLE (VEX_LEN_E8_P_2) },
4026     { "(bad)",  { XX } },
4027   },
4028
4029   /* PREFIX_VEX_E9 */
4030   {
4031     { "(bad)",  { XX } },
4032     { "(bad)",  { XX } },
4033     { VEX_LEN_TABLE (VEX_LEN_E9_P_2) },
4034     { "(bad)",  { XX } },
4035   },
4036
4037   /* PREFIX_VEX_EA */
4038   {
4039     { "(bad)",  { XX } },
4040     { "(bad)",  { XX } },
4041     { VEX_LEN_TABLE (VEX_LEN_EA_P_2) },
4042     { "(bad)",  { XX } },
4043   },
4044
4045   /* PREFIX_VEX_EB */
4046   {
4047     { "(bad)",  { XX } },
4048     { "(bad)",  { XX } },
4049     { VEX_LEN_TABLE (VEX_LEN_EB_P_2) },
4050     { "(bad)",  { XX } },
4051   },
4052
4053   /* PREFIX_VEX_EC */
4054   {
4055     { "(bad)",  { XX } },
4056     { "(bad)",  { XX } },
4057     { VEX_LEN_TABLE (VEX_LEN_EC_P_2) },
4058     { "(bad)",  { XX } },
4059   },
4060
4061   /* PREFIX_VEX_ED */
4062   {
4063     { "(bad)",  { XX } },
4064     { "(bad)",  { XX } },
4065     { VEX_LEN_TABLE (VEX_LEN_ED_P_2) },
4066     { "(bad)",  { XX } },
4067   },
4068
4069   /* PREFIX_VEX_EE */
4070   {
4071     { "(bad)",  { XX } },
4072     { "(bad)",  { XX } },
4073     { VEX_LEN_TABLE (VEX_LEN_EE_P_2) },
4074     { "(bad)",  { XX } },
4075   },
4076
4077   /* PREFIX_VEX_EF */
4078   {
4079     { "(bad)",  { XX } },
4080     { "(bad)",  { XX } },
4081     { VEX_LEN_TABLE (VEX_LEN_EF_P_2) },
4082     { "(bad)",  { XX } },
4083   },
4084
4085   /* PREFIX_VEX_F0 */
4086   {
4087     { "(bad)",  { XX } },
4088     { "(bad)",  { XX } },
4089     { "(bad)",  { XX } },
4090     { MOD_TABLE (MOD_VEX_F0_PREFIX_3) },
4091   },
4092
4093   /* PREFIX_VEX_F1 */
4094   {
4095     { "(bad)",  { XX } },
4096     { "(bad)",  { XX } },
4097     { VEX_LEN_TABLE (VEX_LEN_F1_P_2) },
4098     { "(bad)",  { XX } },
4099   },
4100
4101   /* PREFIX_VEX_F2 */
4102   {
4103     { "(bad)",  { XX } },
4104     { "(bad)",  { XX } },
4105     { VEX_LEN_TABLE (VEX_LEN_F2_P_2) },
4106     { "(bad)",  { XX } },
4107   },
4108
4109   /* PREFIX_VEX_F3 */
4110   {
4111     { "(bad)",  { XX } },
4112     { "(bad)",  { XX } },
4113     { VEX_LEN_TABLE (VEX_LEN_F3_P_2) },
4114     { "(bad)",  { XX } },
4115   },
4116
4117   /* PREFIX_VEX_F4 */
4118   {
4119     { "(bad)",  { XX } },
4120     { "(bad)",  { XX } },
4121     { VEX_LEN_TABLE (VEX_LEN_F4_P_2) },
4122     { "(bad)",  { XX } },
4123   },
4124
4125   /* PREFIX_VEX_F5 */
4126   {
4127     { "(bad)",  { XX } },
4128     { "(bad)",  { XX } },
4129     { VEX_LEN_TABLE (VEX_LEN_F5_P_2) },
4130     { "(bad)",  { XX } },
4131   },
4132
4133   /* PREFIX_VEX_F6 */
4134   {
4135     { "(bad)",  { XX } },
4136     { "(bad)",  { XX } },
4137     { VEX_LEN_TABLE (VEX_LEN_F6_P_2) },
4138     { "(bad)",  { XX } },
4139   },
4140
4141   /* PREFIX_VEX_F7 */
4142   {
4143     { "(bad)",  { XX } },
4144     { "(bad)",  { XX } },
4145     { VEX_LEN_TABLE (VEX_LEN_F7_P_2) },
4146     { "(bad)",  { XX } },
4147   },
4148
4149   /* PREFIX_VEX_F8 */
4150   {
4151     { "(bad)",  { XX } },
4152     { "(bad)",  { XX } },
4153     { VEX_LEN_TABLE (VEX_LEN_F8_P_2) },
4154     { "(bad)",  { XX } },
4155   },
4156
4157   /* PREFIX_VEX_F9 */
4158   {
4159     { "(bad)",  { XX } },
4160     { "(bad)",  { XX } },
4161     { VEX_LEN_TABLE (VEX_LEN_F9_P_2) },
4162     { "(bad)",  { XX } },
4163   },
4164
4165   /* PREFIX_VEX_FA */
4166   {
4167     { "(bad)",  { XX } },
4168     { "(bad)",  { XX } },
4169     { VEX_LEN_TABLE (VEX_LEN_FA_P_2) },
4170     { "(bad)",  { XX } },
4171   },
4172
4173   /* PREFIX_VEX_FB */
4174   {
4175     { "(bad)",  { XX } },
4176     { "(bad)",  { XX } },
4177     { VEX_LEN_TABLE (VEX_LEN_FB_P_2) },
4178     { "(bad)",  { XX } },
4179   },
4180
4181   /* PREFIX_VEX_FC */
4182   {
4183     { "(bad)",  { XX } },
4184     { "(bad)",  { XX } },
4185     { VEX_LEN_TABLE (VEX_LEN_FC_P_2) },
4186     { "(bad)",  { XX } },
4187   },
4188
4189   /* PREFIX_VEX_FD */
4190   {
4191     { "(bad)",  { XX } },
4192     { "(bad)",  { XX } },
4193     { VEX_LEN_TABLE (VEX_LEN_FD_P_2) },
4194     { "(bad)",  { XX } },
4195   },
4196
4197   /* PREFIX_VEX_FE */
4198   {
4199     { "(bad)",  { XX } },
4200     { "(bad)",  { XX } },
4201     { VEX_LEN_TABLE (VEX_LEN_FE_P_2) },
4202     { "(bad)",  { XX } },
4203   },
4204
4205   /* PREFIX_VEX_3800 */
4206   {
4207     { "(bad)",  { XX } },
4208     { "(bad)",  { XX } },
4209     { VEX_LEN_TABLE (VEX_LEN_3800_P_2) },
4210     { "(bad)",  { XX } },
4211   },
4212
4213   /* PREFIX_VEX_3801 */
4214   {
4215     { "(bad)",  { XX } },
4216     { "(bad)",  { XX } },
4217     { VEX_LEN_TABLE (VEX_LEN_3801_P_2) },
4218     { "(bad)",  { XX } },
4219   },
4220
4221   /* PREFIX_VEX_3802 */
4222   {
4223     { "(bad)",  { XX } },
4224     { "(bad)",  { XX } },
4225     { VEX_LEN_TABLE (VEX_LEN_3802_P_2) },
4226     { "(bad)",  { XX } },
4227   },
4228
4229   /* PREFIX_VEX_3803 */
4230   {
4231     { "(bad)",  { XX } },
4232     { "(bad)",  { XX } },
4233     { VEX_LEN_TABLE (VEX_LEN_3803_P_2) },
4234     { "(bad)",  { XX } },
4235   },
4236
4237   /* PREFIX_VEX_3804 */
4238   {
4239     { "(bad)",  { XX } },
4240     { "(bad)",  { XX } },
4241     { VEX_LEN_TABLE (VEX_LEN_3804_P_2) },
4242     { "(bad)",  { XX } },
4243   },
4244
4245   /* PREFIX_VEX_3805 */
4246   {
4247     { "(bad)",  { XX } },
4248     { "(bad)",  { XX } },
4249     { VEX_LEN_TABLE (VEX_LEN_3805_P_2) },
4250     { "(bad)",  { XX } },
4251   },
4252
4253   /* PREFIX_VEX_3806 */
4254   {
4255     { "(bad)",  { XX } },
4256     { "(bad)",  { XX } },
4257     { VEX_LEN_TABLE (VEX_LEN_3806_P_2) },
4258     { "(bad)",  { XX } },
4259   },
4260
4261   /* PREFIX_VEX_3807 */
4262   {
4263     { "(bad)",  { XX } },
4264     { "(bad)",  { XX } },
4265     { VEX_LEN_TABLE (VEX_LEN_3807_P_2) },
4266     { "(bad)",  { XX } },
4267   },
4268
4269   /* PREFIX_VEX_3808 */
4270   {
4271     { "(bad)",  { XX } },
4272     { "(bad)",  { XX } },
4273     { VEX_LEN_TABLE (VEX_LEN_3808_P_2) },
4274     { "(bad)",  { XX } },
4275   },
4276
4277   /* PREFIX_VEX_3809 */
4278   {
4279     { "(bad)",  { XX } },
4280     { "(bad)",  { XX } },
4281     { VEX_LEN_TABLE (VEX_LEN_3809_P_2) },
4282     { "(bad)",  { XX } },
4283   },
4284
4285   /* PREFIX_VEX_380A */
4286   {
4287     { "(bad)",  { XX } },
4288     { "(bad)",  { XX } },
4289     { VEX_LEN_TABLE (VEX_LEN_380A_P_2) },
4290     { "(bad)",  { XX } },
4291   },
4292
4293   /* PREFIX_VEX_380B */
4294   {
4295     { "(bad)",  { XX } },
4296     { "(bad)",  { XX } },
4297     { VEX_LEN_TABLE (VEX_LEN_380B_P_2) },
4298     { "(bad)",  { XX } },
4299   },
4300
4301   /* PREFIX_VEX_380C */
4302   {
4303     { "(bad)",  { XX } },
4304     { "(bad)",  { XX } },
4305     { "vpermilps", { XM, Vex, EXx } },
4306     { "(bad)",  { XX } },
4307   },
4308
4309   /* PREFIX_VEX_380D */
4310   {
4311     { "(bad)",  { XX } },
4312     { "(bad)",  { XX } },
4313     { "vpermilpd", { XM, Vex, EXx } },
4314     { "(bad)",  { XX } },
4315   },
4316
4317   /* PREFIX_VEX_380E */
4318   {
4319     { "(bad)",  { XX } },
4320     { "(bad)",  { XX } },
4321     { "vtestps", { XM, EXx } },
4322     { "(bad)",  { XX } },
4323   },
4324
4325   /* PREFIX_VEX_380F */
4326   {
4327     { "(bad)",  { XX } },
4328     { "(bad)",  { XX } },
4329     { "vtestpd", { XM, EXx } },
4330     { "(bad)",  { XX } },
4331   },
4332
4333   /* PREFIX_VEX_3817 */
4334   {
4335     { "(bad)",  { XX } },
4336     { "(bad)",  { XX } },
4337     { "vptest", { XM, EXx } },
4338     { "(bad)",  { XX } },
4339   },
4340
4341   /* PREFIX_VEX_3818 */
4342   {
4343     { "(bad)",  { XX } },
4344     { "(bad)",  { XX } },
4345     { MOD_TABLE (MOD_VEX_3818_PREFIX_2) },
4346     { "(bad)",  { XX } },
4347   },
4348
4349   /* PREFIX_VEX_3819 */
4350   {
4351     { "(bad)",  { XX } },
4352     { "(bad)",  { XX } },
4353     { MOD_TABLE (MOD_VEX_3819_PREFIX_2) },
4354     { "(bad)",  { XX } },
4355   },
4356
4357   /* PREFIX_VEX_381A */
4358   {
4359     { "(bad)",  { XX } },
4360     { "(bad)",  { XX } },
4361     { MOD_TABLE (MOD_VEX_381A_PREFIX_2) },
4362     { "(bad)",  { XX } },
4363   },
4364
4365   /* PREFIX_VEX_381C */
4366   {
4367     { "(bad)",  { XX } },
4368     { "(bad)",  { XX } },
4369     { VEX_LEN_TABLE (VEX_LEN_381C_P_2) },
4370     { "(bad)",  { XX } },
4371   },
4372
4373   /* PREFIX_VEX_381D */
4374   {
4375     { "(bad)",  { XX } },
4376     { "(bad)",  { XX } },
4377     { VEX_LEN_TABLE (VEX_LEN_381D_P_2) },
4378     { "(bad)",  { XX } },
4379   },
4380
4381   /* PREFIX_VEX_381E */
4382   {
4383     { "(bad)",  { XX } },
4384     { "(bad)",  { XX } },
4385     { VEX_LEN_TABLE (VEX_LEN_381E_P_2) },
4386     { "(bad)",  { XX } },
4387   },
4388
4389   /* PREFIX_VEX_3820 */
4390   {
4391     { "(bad)",  { XX } },
4392     { "(bad)",  { XX } },
4393     { VEX_LEN_TABLE (VEX_LEN_3820_P_2) },
4394     { "(bad)",  { XX } },
4395   },
4396
4397   /* PREFIX_VEX_3821 */
4398   {
4399     { "(bad)",  { XX } },
4400     { "(bad)",  { XX } },
4401     { VEX_LEN_TABLE (VEX_LEN_3821_P_2) },
4402     { "(bad)",  { XX } },
4403   },
4404
4405   /* PREFIX_VEX_3822 */
4406   {
4407     { "(bad)",  { XX } },
4408     { "(bad)",  { XX } },
4409     { VEX_LEN_TABLE (VEX_LEN_3822_P_2) },
4410     { "(bad)",  { XX } },
4411   },
4412
4413   /* PREFIX_VEX_3823 */
4414   {
4415     { "(bad)",  { XX } },
4416     { "(bad)",  { XX } },
4417     { VEX_LEN_TABLE (VEX_LEN_3823_P_2) },
4418     { "(bad)",  { XX } },
4419   },
4420
4421   /* PREFIX_VEX_3824 */
4422   {
4423     { "(bad)",  { XX } },
4424     { "(bad)",  { XX } },
4425     { VEX_LEN_TABLE (VEX_LEN_3824_P_2) },
4426     { "(bad)",  { XX } },
4427   },
4428
4429   /* PREFIX_VEX_3825 */
4430   {
4431     { "(bad)",  { XX } },
4432     { "(bad)",  { XX } },
4433     { VEX_LEN_TABLE (VEX_LEN_3825_P_2) },
4434     { "(bad)",  { XX } },
4435   },
4436
4437   /* PREFIX_VEX_3828 */
4438   {
4439     { "(bad)",  { XX } },
4440     { "(bad)",  { XX } },
4441     { VEX_LEN_TABLE (VEX_LEN_3828_P_2) },
4442     { "(bad)",  { XX } },
4443   },
4444
4445   /* PREFIX_VEX_3829 */
4446   {
4447     { "(bad)",  { XX } },
4448     { "(bad)",  { XX } },
4449     { VEX_LEN_TABLE (VEX_LEN_3829_P_2) },
4450     { "(bad)",  { XX } },
4451   },
4452
4453   /* PREFIX_VEX_382A */
4454   {
4455     { "(bad)",  { XX } },
4456     { "(bad)",  { XX } },
4457     { MOD_TABLE (MOD_VEX_382A_PREFIX_2) },
4458     { "(bad)",  { XX } },
4459   },
4460
4461   /* PREFIX_VEX_382B */
4462   {
4463     { "(bad)",  { XX } },
4464     { "(bad)",  { XX } },
4465     { VEX_LEN_TABLE (VEX_LEN_382B_P_2) },
4466     { "(bad)",  { XX } },
4467   },
4468
4469   /* PREFIX_VEX_382C */
4470   {
4471     { "(bad)",  { XX } },
4472     { "(bad)",  { XX } },
4473      { MOD_TABLE (MOD_VEX_382C_PREFIX_2) },
4474     { "(bad)",  { XX } },
4475   },
4476
4477   /* PREFIX_VEX_382D */
4478   {
4479     { "(bad)",  { XX } },
4480     { "(bad)",  { XX } },
4481      { MOD_TABLE (MOD_VEX_382D_PREFIX_2) },
4482     { "(bad)",  { XX } },
4483   },
4484
4485   /* PREFIX_VEX_382E */
4486   {
4487     { "(bad)",  { XX } },
4488     { "(bad)",  { XX } },
4489      { MOD_TABLE (MOD_VEX_382E_PREFIX_2) },
4490     { "(bad)",  { XX } },
4491   },
4492
4493   /* PREFIX_VEX_382F */
4494   {
4495     { "(bad)",  { XX } },
4496     { "(bad)",  { XX } },
4497      { MOD_TABLE (MOD_VEX_382F_PREFIX_2) },
4498     { "(bad)",  { XX } },
4499   },
4500
4501   /* PREFIX_VEX_3830 */
4502   {
4503     { "(bad)",  { XX } },
4504     { "(bad)",  { XX } },
4505     { VEX_LEN_TABLE (VEX_LEN_3830_P_2) },
4506     { "(bad)",  { XX } },
4507   },
4508
4509   /* PREFIX_VEX_3831 */
4510   {
4511     { "(bad)",  { XX } },
4512     { "(bad)",  { XX } },
4513     { VEX_LEN_TABLE (VEX_LEN_3831_P_2) },
4514     { "(bad)",  { XX } },
4515   },
4516
4517   /* PREFIX_VEX_3832 */
4518   {
4519     { "(bad)",  { XX } },
4520     { "(bad)",  { XX } },
4521     { VEX_LEN_TABLE (VEX_LEN_3832_P_2) },
4522     { "(bad)",  { XX } },
4523   },
4524
4525   /* PREFIX_VEX_3833 */
4526   {
4527     { "(bad)",  { XX } },
4528     { "(bad)",  { XX } },
4529     { VEX_LEN_TABLE (VEX_LEN_3833_P_2) },
4530     { "(bad)",  { XX } },
4531   },
4532
4533   /* PREFIX_VEX_3834 */
4534   {
4535     { "(bad)",  { XX } },
4536     { "(bad)",  { XX } },
4537     { VEX_LEN_TABLE (VEX_LEN_3834_P_2) },
4538     { "(bad)",  { XX } },
4539   },
4540
4541   /* PREFIX_VEX_3835 */
4542   {
4543     { "(bad)",  { XX } },
4544     { "(bad)",  { XX } },
4545     { VEX_LEN_TABLE (VEX_LEN_3835_P_2) },
4546     { "(bad)",  { XX } },
4547   },
4548
4549   /* PREFIX_VEX_3837 */
4550   {
4551     { "(bad)",  { XX } },
4552     { "(bad)",  { XX } },
4553     { VEX_LEN_TABLE (VEX_LEN_3837_P_2) },
4554     { "(bad)",  { XX } },
4555   },
4556
4557   /* PREFIX_VEX_3838 */
4558   {
4559     { "(bad)",  { XX } },
4560     { "(bad)",  { XX } },
4561     { VEX_LEN_TABLE (VEX_LEN_3838_P_2) },
4562     { "(bad)",  { XX } },
4563   },
4564
4565   /* PREFIX_VEX_3839 */
4566   {
4567     { "(bad)",  { XX } },
4568     { "(bad)",  { XX } },
4569     { VEX_LEN_TABLE (VEX_LEN_3839_P_2) },
4570     { "(bad)",  { XX } },
4571   },
4572
4573   /* PREFIX_VEX_383A */
4574   {
4575     { "(bad)",  { XX } },
4576     { "(bad)",  { XX } },
4577     { VEX_LEN_TABLE (VEX_LEN_383A_P_2) },
4578     { "(bad)",  { XX } },
4579   },
4580
4581   /* PREFIX_VEX_383B */
4582   {
4583     { "(bad)",  { XX } },
4584     { "(bad)",  { XX } },
4585     { VEX_LEN_TABLE (VEX_LEN_383B_P_2) },
4586     { "(bad)",  { XX } },
4587   },
4588
4589   /* PREFIX_VEX_383C */
4590   {
4591     { "(bad)",  { XX } },
4592     { "(bad)",  { XX } },
4593     { VEX_LEN_TABLE (VEX_LEN_383C_P_2) },
4594     { "(bad)",  { XX } },
4595   },
4596
4597   /* PREFIX_VEX_383D */
4598   {
4599     { "(bad)",  { XX } },
4600     { "(bad)",  { XX } },
4601     { VEX_LEN_TABLE (VEX_LEN_383D_P_2) },
4602     { "(bad)",  { XX } },
4603   },
4604
4605   /* PREFIX_VEX_383E */
4606   {
4607     { "(bad)",  { XX } },
4608     { "(bad)",  { XX } },
4609     { VEX_LEN_TABLE (VEX_LEN_383E_P_2) },
4610     { "(bad)",  { XX } },
4611   },
4612
4613   /* PREFIX_VEX_383F */
4614   {
4615     { "(bad)",  { XX } },
4616     { "(bad)",  { XX } },
4617     { VEX_LEN_TABLE (VEX_LEN_383F_P_2) },
4618     { "(bad)",  { XX } },
4619   },
4620
4621   /* PREFIX_VEX_3840 */
4622   {
4623     { "(bad)",  { XX } },
4624     { "(bad)",  { XX } },
4625     { VEX_LEN_TABLE (VEX_LEN_3840_P_2) },
4626     { "(bad)",  { XX } },
4627   },
4628
4629   /* PREFIX_VEX_3841 */
4630   {
4631     { "(bad)",  { XX } },
4632     { "(bad)",  { XX } },
4633     { VEX_LEN_TABLE (VEX_LEN_3841_P_2) },
4634     { "(bad)",  { XX } },
4635   },
4636
4637   /* PREFIX_VEX_3896 */
4638   {
4639     { "(bad)",  { XX } },
4640     { "(bad)",  { XX } },
4641     { "vfmaddsub132p%XW", { XM, Vex, EXx } },
4642     { "(bad)",  { XX } },
4643   },
4644
4645   /* PREFIX_VEX_3897 */
4646   {
4647     { "(bad)",  { XX } },
4648     { "(bad)",  { XX } },
4649     { "vfmsubadd132p%XW", { XM, Vex, EXx } },
4650     { "(bad)",  { XX } },
4651   },
4652
4653   /* PREFIX_VEX_3898 */
4654   {
4655     { "(bad)",  { XX } },
4656     { "(bad)",  { XX } },
4657     { "vfmadd132p%XW", { XM, Vex, EXx } },
4658     { "(bad)",  { XX } },
4659   },
4660
4661   /* PREFIX_VEX_3899 */
4662   {
4663     { "(bad)",  { XX } },
4664     { "(bad)",  { XX } },
4665     { "vfmadd132s%XW", { XM, Vex, EXVexWdq } },
4666     { "(bad)",  { XX } },
4667   },
4668
4669   /* PREFIX_VEX_389A */
4670   {
4671     { "(bad)",  { XX } },
4672     { "(bad)",  { XX } },
4673     { "vfmsub132p%XW", { XM, Vex, EXx } },
4674     { "(bad)",  { XX } },
4675   },
4676
4677   /* PREFIX_VEX_389B */
4678   {
4679     { "(bad)",  { XX } },
4680     { "(bad)",  { XX } },
4681     { "vfmsub132s%XW", { XM, Vex, EXVexWdq } },
4682     { "(bad)",  { XX } },
4683   },
4684
4685   /* PREFIX_VEX_389C */
4686   {
4687     { "(bad)",  { XX } },
4688     { "(bad)",  { XX } },
4689     { "vfnmadd132p%XW", { XM, Vex, EXx } },
4690     { "(bad)",  { XX } },
4691   },
4692
4693   /* PREFIX_VEX_389D */
4694   {
4695     { "(bad)",  { XX } },
4696     { "(bad)",  { XX } },
4697     { "vfnmadd132s%XW", { XM, Vex, EXVexWdq } },
4698     { "(bad)",  { XX } },
4699   },
4700
4701   /* PREFIX_VEX_389E */
4702   {
4703     { "(bad)",  { XX } },
4704     { "(bad)",  { XX } },
4705     { "vfnmsub132p%XW", { XM, Vex, EXx } },
4706     { "(bad)",  { XX } },
4707   },
4708
4709   /* PREFIX_VEX_389F */
4710   {
4711     { "(bad)",  { XX } },
4712     { "(bad)",  { XX } },
4713     { "vfnmsub132s%XW", { XM, Vex, EXVexWdq } },
4714     { "(bad)",  { XX } },
4715   },
4716
4717   /* PREFIX_VEX_38A6 */
4718   {
4719     { "(bad)",  { XX } },
4720     { "(bad)",  { XX } },
4721     { "vfmaddsub213p%XW", { XM, Vex, EXx } },
4722     { "(bad)",  { XX } },
4723   },
4724
4725   /* PREFIX_VEX_38A7 */
4726   {
4727     { "(bad)",  { XX } },
4728     { "(bad)",  { XX } },
4729     { "vfmsubadd213p%XW", { XM, Vex, EXx } },
4730     { "(bad)",  { XX } },
4731   },
4732
4733   /* PREFIX_VEX_38A8 */
4734   {
4735     { "(bad)",  { XX } },
4736     { "(bad)",  { XX } },
4737     { "vfmadd213p%XW", { XM, Vex, EXx } },
4738     { "(bad)",  { XX } },
4739   },
4740
4741   /* PREFIX_VEX_38A9 */
4742   {
4743     { "(bad)",  { XX } },
4744     { "(bad)",  { XX } },
4745     { "vfmadd213s%XW", { XM, Vex, EXVexWdq } },
4746     { "(bad)",  { XX } },
4747   },
4748
4749   /* PREFIX_VEX_38AA */
4750   {
4751     { "(bad)",  { XX } },
4752     { "(bad)",  { XX } },
4753     { "vfmsub213p%XW", { XM, Vex, EXx } },
4754     { "(bad)",  { XX } },
4755   },
4756
4757   /* PREFIX_VEX_38AB */
4758   {
4759     { "(bad)",  { XX } },
4760     { "(bad)",  { XX } },
4761     { "vfmsub213s%XW", { XM, Vex, EXVexWdq } },
4762     { "(bad)",  { XX } },
4763   },
4764
4765   /* PREFIX_VEX_38AC */
4766   {
4767     { "(bad)",  { XX } },
4768     { "(bad)",  { XX } },
4769     { "vfnmadd213p%XW", { XM, Vex, EXx } },
4770     { "(bad)",  { XX } },
4771   },
4772
4773   /* PREFIX_VEX_38AD */
4774   {
4775     { "(bad)",  { XX } },
4776     { "(bad)",  { XX } },
4777     { "vfnmadd213s%XW", { XM, Vex, EXVexWdq } },
4778     { "(bad)",  { XX } },
4779   },
4780
4781   /* PREFIX_VEX_38AE */
4782   {
4783     { "(bad)",  { XX } },
4784     { "(bad)",  { XX } },
4785     { "vfnmsub213p%XW", { XM, Vex, EXx } },
4786     { "(bad)",  { XX } },
4787   },
4788
4789   /* PREFIX_VEX_38AF */
4790   {
4791     { "(bad)",  { XX } },
4792     { "(bad)",  { XX } },
4793     { "vfnmsub213s%XW", { XM, Vex, EXVexWdq } },
4794     { "(bad)",  { XX } },
4795   },
4796
4797   /* PREFIX_VEX_38B6 */
4798   {
4799     { "(bad)",  { XX } },
4800     { "(bad)",  { XX } },
4801     { "vfmaddsub231p%XW", { XM, Vex, EXx } },
4802     { "(bad)",  { XX } },
4803   },
4804
4805   /* PREFIX_VEX_38B7 */
4806   {
4807     { "(bad)",  { XX } },
4808     { "(bad)",  { XX } },
4809     { "vfmsubadd231p%XW", { XM, Vex, EXx } },
4810     { "(bad)",  { XX } },
4811   },
4812
4813   /* PREFIX_VEX_38B8 */
4814   {
4815     { "(bad)",  { XX } },
4816     { "(bad)",  { XX } },
4817     { "vfmadd231p%XW", { XM, Vex, EXx } },
4818     { "(bad)",  { XX } },
4819   },
4820
4821   /* PREFIX_VEX_38B9 */
4822   {
4823     { "(bad)",  { XX } },
4824     { "(bad)",  { XX } },
4825     { "vfmadd231s%XW", { XM, Vex, EXVexWdq } },
4826     { "(bad)",  { XX } },
4827   },
4828
4829   /* PREFIX_VEX_38BA */
4830   {
4831     { "(bad)",  { XX } },
4832     { "(bad)",  { XX } },
4833     { "vfmsub231p%XW", { XM, Vex, EXx } },
4834     { "(bad)",  { XX } },
4835   },
4836
4837   /* PREFIX_VEX_38BB */
4838   {
4839     { "(bad)",  { XX } },
4840     { "(bad)",  { XX } },
4841     { "vfmsub231s%XW", { XM, Vex, EXVexWdq } },
4842     { "(bad)",  { XX } },
4843   },
4844
4845   /* PREFIX_VEX_38BC */
4846   {
4847     { "(bad)",  { XX } },
4848     { "(bad)",  { XX } },
4849     { "vfnmadd231p%XW", { XM, Vex, EXx } },
4850     { "(bad)",  { XX } },
4851   },
4852
4853   /* PREFIX_VEX_38BD */
4854   {
4855     { "(bad)",  { XX } },
4856     { "(bad)",  { XX } },
4857     { "vfnmadd231s%XW", { XM, Vex, EXVexWdq } },
4858     { "(bad)",  { XX } },
4859   },
4860
4861   /* PREFIX_VEX_38BE */
4862   {
4863     { "(bad)",  { XX } },
4864     { "(bad)",  { XX } },
4865     { "vfnmsub231p%XW", { XM, Vex, EXx } },
4866     { "(bad)",  { XX } },
4867   },
4868
4869   /* PREFIX_VEX_38BF */
4870   {
4871     { "(bad)",  { XX } },
4872     { "(bad)",  { XX } },
4873     { "vfnmsub231s%XW", { XM, Vex, EXVexWdq } },
4874     { "(bad)",  { XX } },
4875   },
4876
4877   /* PREFIX_VEX_38DB */
4878   {
4879     { "(bad)",  { XX } },
4880     { "(bad)",  { XX } },
4881     { VEX_LEN_TABLE (VEX_LEN_38DB_P_2) },
4882     { "(bad)",  { XX } },
4883   },
4884
4885   /* PREFIX_VEX_38DC */
4886   {
4887     { "(bad)",  { XX } },
4888     { "(bad)",  { XX } },
4889     { VEX_LEN_TABLE (VEX_LEN_38DC_P_2) },
4890     { "(bad)",  { XX } },
4891   },
4892
4893   /* PREFIX_VEX_38DD */
4894   {
4895     { "(bad)",  { XX } },
4896     { "(bad)",  { XX } },
4897     { VEX_LEN_TABLE (VEX_LEN_38DD_P_2) },
4898     { "(bad)",  { XX } },
4899   },
4900
4901   /* PREFIX_VEX_38DE */
4902   {
4903     { "(bad)",  { XX } },
4904     { "(bad)",  { XX } },
4905     { VEX_LEN_TABLE (VEX_LEN_38DE_P_2) },
4906     { "(bad)",  { XX } },
4907   },
4908
4909   /* PREFIX_VEX_38DF */
4910   {
4911     { "(bad)",  { XX } },
4912     { "(bad)",  { XX } },
4913     { VEX_LEN_TABLE (VEX_LEN_38DF_P_2) },
4914     { "(bad)",  { XX } },
4915   },
4916
4917   /* PREFIX_VEX_3A04 */
4918   {
4919     { "(bad)",  { XX } },
4920     { "(bad)",  { XX } },
4921     { "vpermilps", { XM, EXx, Ib } },
4922     { "(bad)",  { XX } },
4923   },
4924
4925   /* PREFIX_VEX_3A05 */
4926   {
4927     { "(bad)",  { XX } },
4928     { "(bad)",  { XX } },
4929     { "vpermilpd", { XM, EXx, Ib } },
4930     { "(bad)",  { XX } },
4931   },
4932
4933   /* PREFIX_VEX_3A06 */
4934   {
4935     { "(bad)",  { XX } },
4936     { "(bad)",  { XX } },
4937     { VEX_LEN_TABLE (VEX_LEN_3A06_P_2) },
4938     { "(bad)",  { XX } },
4939   },
4940
4941   /* PREFIX_VEX_3A08 */
4942   {
4943     { "(bad)",  { XX } },
4944     { "(bad)",  { XX } },
4945     { "vroundps", { XM, EXx, Ib } },
4946     { "(bad)",  { XX } },
4947   },
4948
4949   /* PREFIX_VEX_3A09 */
4950   {
4951     { "(bad)",  { XX } },
4952     { "(bad)",  { XX } },
4953     { "vroundpd", { XM, EXx, Ib } },
4954     { "(bad)",  { XX } },
4955   },
4956
4957   /* PREFIX_VEX_3A0A */
4958   {
4959     { "(bad)",  { XX } },
4960     { "(bad)",  { XX } },
4961     { VEX_LEN_TABLE (VEX_LEN_3A0A_P_2) },
4962     { "(bad)",  { XX } },
4963   },
4964
4965   /* PREFIX_VEX_3A0B */
4966   {
4967     { "(bad)",  { XX } },
4968     { "(bad)",  { XX } },
4969     { VEX_LEN_TABLE (VEX_LEN_3A0B_P_2) },
4970     { "(bad)",  { XX } },
4971   },
4972
4973   /* PREFIX_VEX_3A0C */
4974   {
4975     { "(bad)",  { XX } },
4976     { "(bad)",  { XX } },
4977     { "vblendps", { XM, Vex, EXx, Ib } },
4978     { "(bad)",  { XX } },
4979   },
4980
4981   /* PREFIX_VEX_3A0D */
4982   {
4983     { "(bad)",  { XX } },
4984     { "(bad)",  { XX } },
4985     { "vblendpd", { XM, Vex, EXx, Ib } },
4986     { "(bad)",  { XX } },
4987   },
4988
4989   /* PREFIX_VEX_3A0E */
4990   {
4991     { "(bad)",  { XX } },
4992     { "(bad)",  { XX } },
4993     { VEX_LEN_TABLE (VEX_LEN_3A0E_P_2) },
4994     { "(bad)",  { XX } },
4995   },
4996
4997   /* PREFIX_VEX_3A0F */
4998   {
4999     { "(bad)",  { XX } },
5000     { "(bad)",  { XX } },
5001     { VEX_LEN_TABLE (VEX_LEN_3A0F_P_2) },
5002     { "(bad)",  { XX } },
5003   },
5004
5005   /* PREFIX_VEX_3A14 */
5006   {
5007     { "(bad)",  { XX } },
5008     { "(bad)",  { XX } },
5009     { VEX_LEN_TABLE (VEX_LEN_3A14_P_2) },
5010     { "(bad)",  { XX } },
5011   },
5012
5013   /* PREFIX_VEX_3A15 */
5014   {
5015     { "(bad)",  { XX } },
5016     { "(bad)",  { XX } },
5017     { VEX_LEN_TABLE (VEX_LEN_3A15_P_2) },
5018     { "(bad)",  { XX } },
5019   },
5020
5021   /* PREFIX_VEX_3A16 */
5022   {
5023     { "(bad)",  { XX } },
5024     { "(bad)",  { XX } },
5025     { VEX_LEN_TABLE (VEX_LEN_3A16_P_2) },
5026     { "(bad)",  { XX } },
5027   },
5028
5029   /* PREFIX_VEX_3A17 */
5030   {
5031     { "(bad)",  { XX } },
5032     { "(bad)",  { XX } },
5033     { VEX_LEN_TABLE (VEX_LEN_3A17_P_2) },
5034     { "(bad)",  { XX } },
5035   },
5036
5037   /* PREFIX_VEX_3A18 */
5038   {
5039     { "(bad)",  { XX } },
5040     { "(bad)",  { XX } },
5041     { VEX_LEN_TABLE (VEX_LEN_3A18_P_2) },
5042     { "(bad)",  { XX } },
5043   },
5044
5045   /* PREFIX_VEX_3A19 */
5046   {
5047     { "(bad)",  { XX } },
5048     { "(bad)",  { XX } },
5049     { VEX_LEN_TABLE (VEX_LEN_3A19_P_2) },
5050     { "(bad)",  { XX } },
5051   },
5052
5053   /* PREFIX_VEX_3A20 */
5054   {
5055     { "(bad)",  { XX } },
5056     { "(bad)",  { XX } },
5057     { VEX_LEN_TABLE (VEX_LEN_3A20_P_2) },
5058     { "(bad)",  { XX } },
5059   },
5060
5061   /* PREFIX_VEX_3A21 */
5062   {
5063     { "(bad)",  { XX } },
5064     { "(bad)",  { XX } },
5065     { VEX_LEN_TABLE (VEX_LEN_3A21_P_2) },
5066     { "(bad)",  { XX } },
5067   },
5068
5069   /* PREFIX_VEX_3A22 */
5070   {
5071     { "(bad)",  { XX } },
5072     { "(bad)",  { XX } },
5073     { VEX_LEN_TABLE (VEX_LEN_3A22_P_2) },
5074     { "(bad)",  { XX } },
5075   },
5076
5077   /* PREFIX_VEX_3A40 */
5078   {
5079     { "(bad)",  { XX } },
5080     { "(bad)",  { XX } },
5081     { "vdpps",  { XM, Vex, EXx, Ib } },
5082     { "(bad)",  { XX } },
5083   },
5084
5085   /* PREFIX_VEX_3A41 */
5086   {
5087     { "(bad)",  { XX } },
5088     { "(bad)",  { XX } },
5089     { VEX_LEN_TABLE (VEX_LEN_3A41_P_2) },
5090     { "(bad)",  { XX } },
5091   },
5092
5093   /* PREFIX_VEX_3A42 */
5094   {
5095     { "(bad)",  { XX } },
5096     { "(bad)",  { XX } },
5097     { VEX_LEN_TABLE (VEX_LEN_3A42_P_2) },
5098     { "(bad)",  { XX } },
5099   },
5100
5101   /* PREFIX_VEX_3A44 */
5102   {
5103     { "(bad)",  { XX } },
5104     { "(bad)",  { XX } },
5105     { VEX_LEN_TABLE (VEX_LEN_3A44_P_2) },
5106     { "(bad)",  { XX } },
5107   },
5108
5109   /* PREFIX_VEX_3A4A */
5110   {
5111     { "(bad)",  { XX } },
5112     { "(bad)",  { XX } },
5113     { "vblendvps", { XM, Vex, EXx, XMVexI4 } },
5114     { "(bad)",  { XX } },
5115   },
5116
5117   /* PREFIX_VEX_3A4B */
5118   {
5119     { "(bad)",  { XX } },
5120     { "(bad)",  { XX } },
5121     { "vblendvpd", { XM, Vex, EXx, XMVexI4 } },
5122     { "(bad)",  { XX } },
5123   },
5124
5125   /* PREFIX_VEX_3A4C */
5126   {
5127     { "(bad)",  { XX } },
5128     { "(bad)",  { XX } },
5129     { VEX_LEN_TABLE (VEX_LEN_3A4C_P_2) },
5130     { "(bad)",  { XX } },
5131   },
5132
5133   /* PREFIX_VEX_3A5C */
5134   {
5135     { "(bad)",  { XX } },
5136     { "(bad)",  { XX } },
5137     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5138     { "(bad)",  { XX } },
5139   },
5140
5141   /* PREFIX_VEX_3A5D */
5142   {
5143     { "(bad)",  { XX } },
5144     { "(bad)",  { XX } },
5145     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5146     { "(bad)",  { XX } },
5147   },
5148
5149   /* PREFIX_VEX_3A5E */
5150   {
5151     { "(bad)",  { XX } },
5152     { "(bad)",  { XX } },
5153     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5154     { "(bad)",  { XX } },
5155   },
5156
5157   /* PREFIX_VEX_3A5F */
5158   {
5159     { "(bad)",  { XX } },
5160     { "(bad)",  { XX } },
5161     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5162     { "(bad)",  { XX } },
5163   },
5164
5165   /* PREFIX_VEX_3A60 */
5166   {
5167     { "(bad)",  { XX } },
5168     { "(bad)",  { XX } },
5169     { VEX_LEN_TABLE (VEX_LEN_3A60_P_2) },
5170     { "(bad)",  { XX } },
5171   },
5172
5173   /* PREFIX_VEX_3A61 */
5174   {
5175     { "(bad)",  { XX } },
5176     { "(bad)",  { XX } },
5177     { VEX_LEN_TABLE (VEX_LEN_3A61_P_2) },
5178     { "(bad)",  { XX } },
5179   },
5180
5181   /* PREFIX_VEX_3A62 */
5182   {
5183     { "(bad)",  { XX } },
5184     { "(bad)",  { XX } },
5185     { VEX_LEN_TABLE (VEX_LEN_3A62_P_2) },
5186     { "(bad)",  { XX } },
5187   },
5188
5189   /* PREFIX_VEX_3A63 */
5190   {
5191     { "(bad)",  { XX } },
5192     { "(bad)",  { XX } },
5193     { VEX_LEN_TABLE (VEX_LEN_3A63_P_2) },
5194     { "(bad)",  { XX } },
5195   },
5196
5197   /* PREFIX_VEX_3A68 */
5198   {
5199     { "(bad)",  { XX } },
5200     { "(bad)",  { XX } },
5201     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5202     { "(bad)",  { XX } },
5203   },
5204
5205   /* PREFIX_VEX_3A69 */
5206   {
5207     { "(bad)",  { XX } },
5208     { "(bad)",  { XX } },
5209     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5210     { "(bad)",  { XX } },
5211   },
5212
5213   /* PREFIX_VEX_3A6A */
5214   {
5215     { "(bad)",  { XX } },
5216     { "(bad)",  { XX } },
5217     { VEX_LEN_TABLE (VEX_LEN_3A6A_P_2) },
5218     { "(bad)",  { XX } },
5219   },
5220
5221   /* PREFIX_VEX_3A6B */
5222   {
5223     { "(bad)",  { XX } },
5224     { "(bad)",  { XX } },
5225     { VEX_LEN_TABLE (VEX_LEN_3A6B_P_2) },
5226     { "(bad)",  { XX } },
5227   },
5228
5229   /* PREFIX_VEX_3A6C */
5230   {
5231     { "(bad)",  { XX } },
5232     { "(bad)",  { XX } },
5233     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5234     { "(bad)",  { XX } },
5235   },
5236
5237   /* PREFIX_VEX_3A6D */
5238   {
5239     { "(bad)",  { XX } },
5240     { "(bad)",  { XX } },
5241     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5242     { "(bad)",  { XX } },
5243   },
5244
5245   /* PREFIX_VEX_3A6E */
5246   {
5247     { "(bad)",  { XX } },
5248     { "(bad)",  { XX } },
5249     { VEX_LEN_TABLE (VEX_LEN_3A6E_P_2) },
5250     { "(bad)",  { XX } },
5251   },
5252
5253   /* PREFIX_VEX_3A6F */
5254   {
5255     { "(bad)",  { XX } },
5256     { "(bad)",  { XX } },
5257     { VEX_LEN_TABLE (VEX_LEN_3A6F_P_2) },
5258     { "(bad)",  { XX } },
5259   },
5260
5261   /* PREFIX_VEX_3A78 */
5262   {
5263     { "(bad)",  { XX } },
5264     { "(bad)",  { XX } },
5265     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5266     { "(bad)",  { XX } },
5267   },
5268
5269   /* PREFIX_VEX_3A79 */
5270   {
5271     { "(bad)",  { XX } },
5272     { "(bad)",  { XX } },
5273     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5274     { "(bad)",  { XX } },
5275   },
5276
5277   /* PREFIX_VEX_3A7A */
5278   {
5279     { "(bad)",  { XX } },
5280     { "(bad)",  { XX } },
5281     { VEX_LEN_TABLE (VEX_LEN_3A7A_P_2) },
5282     { "(bad)",  { XX } },
5283   },
5284
5285   /* PREFIX_VEX_3A7B */
5286   {
5287     { "(bad)",  { XX } },
5288     { "(bad)",  { XX } },
5289     { VEX_LEN_TABLE (VEX_LEN_3A7B_P_2) },
5290     { "(bad)",  { XX } },
5291   },
5292
5293   /* PREFIX_VEX_3A7C */
5294   {
5295     { "(bad)",  { XX } },
5296     { "(bad)",  { XX } },
5297     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5298     { "(bad)",  { XX } },
5299   },
5300
5301   /* PREFIX_VEX_3A7D */
5302   {
5303     { "(bad)",  { XX } },
5304     { "(bad)",  { XX } },
5305     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5306     { "(bad)",  { XX } },
5307   },
5308
5309   /* PREFIX_VEX_3A7E */
5310   {
5311     { "(bad)",  { XX } },
5312     { "(bad)",  { XX } },
5313     { VEX_LEN_TABLE (VEX_LEN_3A7E_P_2) },
5314     { "(bad)",  { XX } },
5315   },
5316
5317   /* PREFIX_VEX_3A7F */
5318   {
5319     { "(bad)",  { XX } },
5320     { "(bad)",  { XX } },
5321     { VEX_LEN_TABLE (VEX_LEN_3A7F_P_2) },
5322     { "(bad)",  { XX } },
5323   },
5324
5325   /* PREFIX_VEX_3ADF */
5326   {
5327     { "(bad)",  { XX } },
5328     { "(bad)",  { XX } },
5329     { VEX_LEN_TABLE (VEX_LEN_3ADF_P_2) },
5330     { "(bad)",  { XX } },
5331   },
5332 };
5333
5334 static const struct dis386 x86_64_table[][2] = {
5335   /* X86_64_06 */
5336   {
5337     { "push{T|}", { es } },
5338     { "(bad)", { XX } },
5339   },
5340
5341   /* X86_64_07 */
5342   {
5343     { "pop{T|}", { es } },
5344     { "(bad)", { XX } },
5345   },
5346
5347   /* X86_64_0D */
5348   {
5349     { "push{T|}", { cs } },
5350     { "(bad)", { XX } },
5351   },
5352
5353   /* X86_64_16 */
5354   {
5355     { "push{T|}", { ss } },
5356     { "(bad)", { XX } },
5357   },
5358
5359   /* X86_64_17 */
5360   {
5361     { "pop{T|}", { ss } },
5362     { "(bad)", { XX } },
5363   },
5364
5365   /* X86_64_1E */
5366   {
5367     { "push{T|}", { ds } },
5368     { "(bad)", { XX } },
5369   },
5370
5371   /* X86_64_1F */
5372   {
5373     { "pop{T|}", { ds } },
5374     { "(bad)", { XX } },
5375   },
5376
5377   /* X86_64_27 */
5378   {
5379     { "daa", { XX } },
5380     { "(bad)", { XX } },
5381   },
5382
5383   /* X86_64_2F */
5384   {
5385     { "das", { XX } },
5386     { "(bad)", { XX } },
5387   },
5388
5389   /* X86_64_37 */
5390   {
5391     { "aaa", { XX } },
5392     { "(bad)", { XX } },
5393   },
5394
5395   /* X86_64_3F */
5396   {
5397     { "aas", { XX } },
5398     { "(bad)", { XX } },
5399   },
5400
5401   /* X86_64_60 */
5402   {
5403     { "pusha{P|}", { XX } },
5404     { "(bad)", { XX } },
5405   },
5406
5407   /* X86_64_61 */
5408   {
5409     { "popa{P|}", { XX } },
5410     { "(bad)", { XX } },
5411   },
5412
5413   /* X86_64_62 */
5414   {
5415     { MOD_TABLE (MOD_62_32BIT) },
5416     { "(bad)", { XX } },
5417   },
5418
5419   /* X86_64_63 */
5420   {
5421     { "arpl", { Ew, Gw } },
5422     { "movs{lq|xd}", { Gv, Ed } },
5423   },
5424
5425   /* X86_64_6D */
5426   {
5427     { "ins{R|}", { Yzr, indirDX } },
5428     { "ins{G|}", { Yzr, indirDX } },
5429   },
5430
5431   /* X86_64_6F */
5432   {
5433     { "outs{R|}", { indirDXr, Xz } },
5434     { "outs{G|}", { indirDXr, Xz } },
5435   },
5436
5437   /* X86_64_9A */
5438   {
5439     { "Jcall{T|}", { Ap } },
5440     { "(bad)", { XX } },
5441   },
5442
5443   /* X86_64_C4 */
5444   {
5445     { MOD_TABLE (MOD_C4_32BIT) },
5446     { VEX_C4_TABLE (VEX_0F) },
5447   },
5448
5449   /* X86_64_C5 */
5450   {
5451     { MOD_TABLE (MOD_C5_32BIT) },
5452     { VEX_C5_TABLE (VEX_0F) },
5453   },
5454
5455   /* X86_64_CE */
5456   {
5457     { "into", { XX } },
5458     { "(bad)", { XX } },
5459   },
5460
5461   /* X86_64_D4 */
5462   {
5463     { "aam", { sIb } },
5464     { "(bad)", { XX } },
5465   },
5466
5467   /* X86_64_D5 */
5468   {
5469     { "aad", { sIb } },
5470     { "(bad)", { XX } },
5471   },
5472
5473   /* X86_64_EA */
5474   {
5475     { "Jjmp{T|}", { Ap } },
5476     { "(bad)", { XX } },
5477   },
5478
5479   /* X86_64_0F01_REG_0 */
5480   {
5481     { "sgdt{Q|IQ}", { M } },
5482     { "sgdt", { M } },
5483   },
5484
5485   /* X86_64_0F01_REG_1 */
5486   {
5487     { "sidt{Q|IQ}", { M } },
5488     { "sidt", { M } },
5489   },
5490
5491   /* X86_64_0F01_REG_2 */
5492   {
5493     { "lgdt{Q|Q}", { M } },
5494     { "lgdt", { M } },
5495   },
5496
5497   /* X86_64_0F01_REG_3 */
5498   {
5499     { "lidt{Q|Q}", { M } },
5500     { "lidt", { M } },
5501   },
5502 };
5503
5504 static const struct dis386 three_byte_table[][256] = {
5505
5506   /* THREE_BYTE_0F38 */
5507   {
5508     /* 00 */
5509     { "pshufb",         { MX, EM } },
5510     { "phaddw",         { MX, EM } },
5511     { "phaddd",         { MX, EM } },
5512     { "phaddsw",        { MX, EM } },
5513     { "pmaddubsw",      { MX, EM } },
5514     { "phsubw",         { MX, EM } },
5515     { "phsubd",         { MX, EM } },
5516     { "phsubsw",        { MX, EM } },
5517     /* 08 */
5518     { "psignb",         { MX, EM } },
5519     { "psignw",         { MX, EM } },
5520     { "psignd",         { MX, EM } },
5521     { "pmulhrsw",       { MX, EM } },
5522     { "(bad)",          { XX } },
5523     { "(bad)",          { XX } },
5524     { "(bad)",          { XX } },
5525     { "(bad)",          { XX } },
5526     /* 10 */
5527     { PREFIX_TABLE (PREFIX_0F3810) },
5528     { "(bad)",          { XX } },
5529     { "(bad)",          { XX } },
5530     { "(bad)",          { XX } },
5531     { PREFIX_TABLE (PREFIX_0F3814) },
5532     { PREFIX_TABLE (PREFIX_0F3815) },
5533     { "(bad)",          { XX } },
5534     { PREFIX_TABLE (PREFIX_0F3817) },
5535     /* 18 */
5536     { "(bad)",          { XX } },
5537     { "(bad)",          { XX } },
5538     { "(bad)",          { XX } },
5539     { "(bad)",          { XX } },
5540     { "pabsb",          { MX, EM } },
5541     { "pabsw",          { MX, EM } },
5542     { "pabsd",          { MX, EM } },
5543     { "(bad)",          { XX } },
5544     /* 20 */
5545     { PREFIX_TABLE (PREFIX_0F3820) },
5546     { PREFIX_TABLE (PREFIX_0F3821) },
5547     { PREFIX_TABLE (PREFIX_0F3822) },
5548     { PREFIX_TABLE (PREFIX_0F3823) },
5549     { PREFIX_TABLE (PREFIX_0F3824) },
5550     { PREFIX_TABLE (PREFIX_0F3825) },
5551     { "(bad)",          { XX } },
5552     { "(bad)",          { XX } },
5553     /* 28 */
5554     { PREFIX_TABLE (PREFIX_0F3828) },
5555     { PREFIX_TABLE (PREFIX_0F3829) },
5556     { PREFIX_TABLE (PREFIX_0F382A) },
5557     { PREFIX_TABLE (PREFIX_0F382B) },
5558     { "(bad)",          { XX } },
5559     { "(bad)",          { XX } },
5560     { "(bad)",          { XX } },
5561     { "(bad)",          { XX } },
5562     /* 30 */
5563     { PREFIX_TABLE (PREFIX_0F3830) },
5564     { PREFIX_TABLE (PREFIX_0F3831) },
5565     { PREFIX_TABLE (PREFIX_0F3832) },
5566     { PREFIX_TABLE (PREFIX_0F3833) },
5567     { PREFIX_TABLE (PREFIX_0F3834) },
5568     { PREFIX_TABLE (PREFIX_0F3835) },
5569     { "(bad)",          { XX } },
5570     { PREFIX_TABLE (PREFIX_0F3837) },
5571     /* 38 */
5572     { PREFIX_TABLE (PREFIX_0F3838) },
5573     { PREFIX_TABLE (PREFIX_0F3839) },
5574     { PREFIX_TABLE (PREFIX_0F383A) },
5575     { PREFIX_TABLE (PREFIX_0F383B) },
5576     { PREFIX_TABLE (PREFIX_0F383C) },
5577     { PREFIX_TABLE (PREFIX_0F383D) },
5578     { PREFIX_TABLE (PREFIX_0F383E) },
5579     { PREFIX_TABLE (PREFIX_0F383F) },
5580     /* 40 */
5581     { PREFIX_TABLE (PREFIX_0F3840) },
5582     { PREFIX_TABLE (PREFIX_0F3841) },
5583     { "(bad)",          { XX } },
5584     { "(bad)",          { XX } },
5585     { "(bad)",          { XX } },
5586     { "(bad)",          { XX } },
5587     { "(bad)",          { XX } },
5588     { "(bad)",          { XX } },
5589     /* 48 */
5590     { "(bad)",          { XX } },
5591     { "(bad)",          { XX } },
5592     { "(bad)",          { XX } },
5593     { "(bad)",          { XX } },
5594     { "(bad)",          { XX } },
5595     { "(bad)",          { XX } },
5596     { "(bad)",          { XX } },
5597     { "(bad)",          { XX } },
5598     /* 50 */
5599     { "(bad)",          { XX } },
5600     { "(bad)",          { XX } },
5601     { "(bad)",          { XX } },
5602     { "(bad)",          { XX } },
5603     { "(bad)",          { XX } },
5604     { "(bad)",          { XX } },
5605     { "(bad)",          { XX } },
5606     { "(bad)",          { XX } },
5607     /* 58 */
5608     { "(bad)",          { XX } },
5609     { "(bad)",          { XX } },
5610     { "(bad)",          { XX } },
5611     { "(bad)",          { XX } },
5612     { "(bad)",          { XX } },
5613     { "(bad)",          { XX } },
5614     { "(bad)",          { XX } },
5615     { "(bad)",          { XX } },
5616     /* 60 */
5617     { "(bad)",          { XX } },
5618     { "(bad)",          { XX } },
5619     { "(bad)",          { XX } },
5620     { "(bad)",          { XX } },
5621     { "(bad)",          { XX } },
5622     { "(bad)",          { XX } },
5623     { "(bad)",          { XX } },
5624     { "(bad)",          { XX } },
5625     /* 68 */
5626     { "(bad)",          { XX } },
5627     { "(bad)",          { XX } },
5628     { "(bad)",          { XX } },
5629     { "(bad)",          { XX } },
5630     { "(bad)",          { XX } },
5631     { "(bad)",          { XX } },
5632     { "(bad)",          { XX } },
5633     { "(bad)",          { XX } },
5634     /* 70 */
5635     { "(bad)",          { XX } },
5636     { "(bad)",          { XX } },
5637     { "(bad)",          { XX } },
5638     { "(bad)",          { XX } },
5639     { "(bad)",          { XX } },
5640     { "(bad)",          { XX } },
5641     { "(bad)",          { XX } },
5642     { "(bad)",          { XX } },
5643     /* 78 */
5644     { "(bad)",          { XX } },
5645     { "(bad)",          { XX } },
5646     { "(bad)",          { XX } },
5647     { "(bad)",          { XX } },
5648     { "(bad)",          { XX } },
5649     { "(bad)",          { XX } },
5650     { "(bad)",          { XX } },
5651     { "(bad)",          { XX } },
5652     /* 80 */
5653     { PREFIX_TABLE (PREFIX_0F3880) },
5654     { PREFIX_TABLE (PREFIX_0F3881) },
5655     { "(bad)",          { XX } },
5656     { "(bad)",          { XX } },
5657     { "(bad)",          { XX } },
5658     { "(bad)",          { XX } },
5659     { "(bad)",          { XX } },
5660     { "(bad)",          { XX } },
5661     /* 88 */
5662     { "(bad)",          { XX } },
5663     { "(bad)",          { XX } },
5664     { "(bad)",          { XX } },
5665     { "(bad)",          { XX } },
5666     { "(bad)",          { XX } },
5667     { "(bad)",          { XX } },
5668     { "(bad)",          { XX } },
5669     { "(bad)",          { XX } },
5670     /* 90 */
5671     { "(bad)",          { XX } },
5672     { "(bad)",          { XX } },
5673     { "(bad)",          { XX } },
5674     { "(bad)",          { XX } },
5675     { "(bad)",          { XX } },
5676     { "(bad)",          { XX } },
5677     { "(bad)",          { XX } },
5678     { "(bad)",          { XX } },
5679     /* 98 */
5680     { "(bad)",          { XX } },
5681     { "(bad)",          { XX } },
5682     { "(bad)",          { XX } },
5683     { "(bad)",          { XX } },
5684     { "(bad)",          { XX } },
5685     { "(bad)",          { XX } },
5686     { "(bad)",          { XX } },
5687     { "(bad)",          { XX } },
5688     /* a0 */
5689     { "(bad)",          { XX } },
5690     { "(bad)",          { XX } },
5691     { "(bad)",          { XX } },
5692     { "(bad)",          { XX } },
5693     { "(bad)",          { XX } },
5694     { "(bad)",          { XX } },
5695     { "(bad)",          { XX } },
5696     { "(bad)",          { XX } },
5697     /* a8 */
5698     { "(bad)",          { XX } },
5699     { "(bad)",          { XX } },
5700     { "(bad)",          { XX } },
5701     { "(bad)",          { XX } },
5702     { "(bad)",          { XX } },
5703     { "(bad)",          { XX } },
5704     { "(bad)",          { XX } },
5705     { "(bad)",          { XX } },
5706     /* b0 */
5707     { "(bad)",          { XX } },
5708     { "(bad)",          { XX } },
5709     { "(bad)",          { XX } },
5710     { "(bad)",          { XX } },
5711     { "(bad)",          { XX } },
5712     { "(bad)",          { XX } },
5713     { "(bad)",          { XX } },
5714     { "(bad)",          { XX } },
5715     /* b8 */
5716     { "(bad)",          { XX } },
5717     { "(bad)",          { XX } },
5718     { "(bad)",          { XX } },
5719     { "(bad)",          { XX } },
5720     { "(bad)",          { XX } },
5721     { "(bad)",          { XX } },
5722     { "(bad)",          { XX } },
5723     { "(bad)",          { XX } },
5724     /* c0 */
5725     { "(bad)",          { XX } },
5726     { "(bad)",          { XX } },
5727     { "(bad)",          { XX } },
5728     { "(bad)",          { XX } },
5729     { "(bad)",          { XX } },
5730     { "(bad)",          { XX } },
5731     { "(bad)",          { XX } },
5732     { "(bad)",          { XX } },
5733     /* c8 */
5734     { "(bad)",          { XX } },
5735     { "(bad)",          { XX } },
5736     { "(bad)",          { XX } },
5737     { "(bad)",          { XX } },
5738     { "(bad)",          { XX } },
5739     { "(bad)",          { XX } },
5740     { "(bad)",          { XX } },
5741     { "(bad)",          { XX } },
5742     /* d0 */
5743     { "(bad)",          { XX } },
5744     { "(bad)",          { XX } },
5745     { "(bad)",          { XX } },
5746     { "(bad)",          { XX } },
5747     { "(bad)",          { XX } },
5748     { "(bad)",          { XX } },
5749     { "(bad)",          { XX } },
5750     { "(bad)",          { XX } },
5751     /* d8 */
5752     { "(bad)",          { XX } },
5753     { "(bad)",          { XX } },
5754     { "(bad)",          { XX } },
5755     { PREFIX_TABLE (PREFIX_0F38DB) },
5756     { PREFIX_TABLE (PREFIX_0F38DC) },
5757     { PREFIX_TABLE (PREFIX_0F38DD) },
5758     { PREFIX_TABLE (PREFIX_0F38DE) },
5759     { PREFIX_TABLE (PREFIX_0F38DF) },
5760     /* e0 */
5761     { "(bad)",          { XX } },
5762     { "(bad)",          { XX } },
5763     { "(bad)",          { XX } },
5764     { "(bad)",          { XX } },
5765     { "(bad)",          { XX } },
5766     { "(bad)",          { XX } },
5767     { "(bad)",          { XX } },
5768     { "(bad)",          { XX } },
5769     /* e8 */
5770     { "(bad)",          { XX } },
5771     { "(bad)",          { XX } },
5772     { "(bad)",          { XX } },
5773     { "(bad)",          { XX } },
5774     { "(bad)",          { XX } },
5775     { "(bad)",          { XX } },
5776     { "(bad)",          { XX } },
5777     { "(bad)",          { XX } },
5778     /* f0 */
5779     { PREFIX_TABLE (PREFIX_0F38F0) },
5780     { PREFIX_TABLE (PREFIX_0F38F1) },
5781     { "(bad)",          { XX } },
5782     { "(bad)",          { XX } },
5783     { "(bad)",          { XX } },
5784     { "(bad)",          { XX } },
5785     { "(bad)",          { XX } },
5786     { "(bad)",          { XX } },
5787     /* f8 */
5788     { "(bad)",          { XX } },
5789     { "(bad)",          { XX } },
5790     { "(bad)",          { XX } },
5791     { "(bad)",          { XX } },
5792     { "(bad)",          { XX } },
5793     { "(bad)",          { XX } },
5794     { "(bad)",          { XX } },
5795     { "(bad)",          { XX } },
5796   },
5797   /* THREE_BYTE_0F3A */
5798   {
5799     /* 00 */
5800     { "(bad)",          { XX } },
5801     { "(bad)",          { XX } },
5802     { "(bad)",          { XX } },
5803     { "(bad)",          { XX } },
5804     { "(bad)",          { XX } },
5805     { "(bad)",          { XX } },
5806     { "(bad)",          { XX } },
5807     { "(bad)",          { XX } },
5808     /* 08 */
5809     { PREFIX_TABLE (PREFIX_0F3A08) },
5810     { PREFIX_TABLE (PREFIX_0F3A09) },
5811     { PREFIX_TABLE (PREFIX_0F3A0A) },
5812     { PREFIX_TABLE (PREFIX_0F3A0B) },
5813     { PREFIX_TABLE (PREFIX_0F3A0C) },
5814     { PREFIX_TABLE (PREFIX_0F3A0D) },
5815     { PREFIX_TABLE (PREFIX_0F3A0E) },
5816     { "palignr",        { MX, EM, Ib } },
5817     /* 10 */
5818     { "(bad)",          { XX } },
5819     { "(bad)",          { XX } },
5820     { "(bad)",          { XX } },
5821     { "(bad)",          { XX } },
5822     { PREFIX_TABLE (PREFIX_0F3A14) },
5823     { PREFIX_TABLE (PREFIX_0F3A15) },
5824     { PREFIX_TABLE (PREFIX_0F3A16) },
5825     { PREFIX_TABLE (PREFIX_0F3A17) },
5826     /* 18 */
5827     { "(bad)",          { XX } },
5828     { "(bad)",          { XX } },
5829     { "(bad)",          { XX } },
5830     { "(bad)",          { XX } },
5831     { "(bad)",          { XX } },
5832     { "(bad)",          { XX } },
5833     { "(bad)",          { XX } },
5834     { "(bad)",          { XX } },
5835     /* 20 */
5836     { PREFIX_TABLE (PREFIX_0F3A20) },
5837     { PREFIX_TABLE (PREFIX_0F3A21) },
5838     { PREFIX_TABLE (PREFIX_0F3A22) },
5839     { "(bad)",          { XX } },
5840     { "(bad)",          { XX } },
5841     { "(bad)",          { XX } },
5842     { "(bad)",          { XX } },
5843     { "(bad)",          { XX } },
5844     /* 28 */
5845     { "(bad)",          { XX } },
5846     { "(bad)",          { XX } },
5847     { "(bad)",          { XX } },
5848     { "(bad)",          { XX } },
5849     { "(bad)",          { XX } },
5850     { "(bad)",          { XX } },
5851     { "(bad)",          { XX } },
5852     { "(bad)",          { XX } },
5853     /* 30 */
5854     { "(bad)",          { XX } },
5855     { "(bad)",          { XX } },
5856     { "(bad)",          { XX } },
5857     { "(bad)",          { XX } },
5858     { "(bad)",          { XX } },
5859     { "(bad)",          { XX } },
5860     { "(bad)",          { XX } },
5861     { "(bad)",          { XX } },
5862     /* 38 */
5863     { "(bad)",          { XX } },
5864     { "(bad)",          { XX } },
5865     { "(bad)",          { XX } },
5866     { "(bad)",          { XX } },
5867     { "(bad)",          { XX } },
5868     { "(bad)",          { XX } },
5869     { "(bad)",          { XX } },
5870     { "(bad)",          { XX } },
5871     /* 40 */
5872     { PREFIX_TABLE (PREFIX_0F3A40) },
5873     { PREFIX_TABLE (PREFIX_0F3A41) },
5874     { PREFIX_TABLE (PREFIX_0F3A42) },
5875     { "(bad)",          { XX } },
5876     { PREFIX_TABLE (PREFIX_0F3A44) },
5877     { "(bad)",          { XX } },
5878     { "(bad)",          { XX } },
5879     { "(bad)",          { XX } },
5880     /* 48 */
5881     { "(bad)",          { XX } },
5882     { "(bad)",          { XX } },
5883     { "(bad)",          { XX } },
5884     { "(bad)",          { XX } },
5885     { "(bad)",          { XX } },
5886     { "(bad)",          { XX } },
5887     { "(bad)",          { XX } },
5888     { "(bad)",          { XX } },
5889     /* 50 */
5890     { "(bad)",          { XX } },
5891     { "(bad)",          { XX } },
5892     { "(bad)",          { XX } },
5893     { "(bad)",          { XX } },
5894     { "(bad)",          { XX } },
5895     { "(bad)",          { XX } },
5896     { "(bad)",          { XX } },
5897     { "(bad)",          { XX } },
5898     /* 58 */
5899     { "(bad)",          { XX } },
5900     { "(bad)",          { XX } },
5901     { "(bad)",          { XX } },
5902     { "(bad)",          { XX } },
5903     { "(bad)",          { XX } },
5904     { "(bad)",          { XX } },
5905     { "(bad)",          { XX } },
5906     { "(bad)",          { XX } },
5907     /* 60 */
5908     { PREFIX_TABLE (PREFIX_0F3A60) },
5909     { PREFIX_TABLE (PREFIX_0F3A61) },
5910     { PREFIX_TABLE (PREFIX_0F3A62) },
5911     { PREFIX_TABLE (PREFIX_0F3A63) },
5912     { "(bad)",          { XX } },
5913     { "(bad)",          { XX } },
5914     { "(bad)",          { XX } },
5915     { "(bad)",          { XX } },
5916     /* 68 */
5917     { "(bad)",          { XX } },
5918     { "(bad)",          { XX } },
5919     { "(bad)",          { XX } },
5920     { "(bad)",          { XX } },
5921     { "(bad)",          { XX } },
5922     { "(bad)",          { XX } },
5923     { "(bad)",          { XX } },
5924     { "(bad)",          { XX } },
5925     /* 70 */
5926     { "(bad)",          { XX } },
5927     { "(bad)",          { XX } },
5928     { "(bad)",          { XX } },
5929     { "(bad)",          { XX } },
5930     { "(bad)",          { XX } },
5931     { "(bad)",          { XX } },
5932     { "(bad)",          { XX } },
5933     { "(bad)",          { XX } },
5934     /* 78 */
5935     { "(bad)",          { XX } },
5936     { "(bad)",          { XX } },
5937     { "(bad)",          { XX } },
5938     { "(bad)",          { XX } },
5939     { "(bad)",          { XX } },
5940     { "(bad)",          { XX } },
5941     { "(bad)",          { XX } },
5942     { "(bad)",          { XX } },
5943     /* 80 */
5944     { "(bad)",          { XX } },
5945     { "(bad)",          { XX } },
5946     { "(bad)",          { XX } },
5947     { "(bad)",          { XX } },
5948     { "(bad)",          { XX } },
5949     { "(bad)",          { XX } },
5950     { "(bad)",          { XX } },
5951     { "(bad)",          { XX } },
5952     /* 88 */
5953     { "(bad)",          { XX } },
5954     { "(bad)",          { XX } },
5955     { "(bad)",          { XX } },
5956     { "(bad)",          { XX } },
5957     { "(bad)",          { XX } },
5958     { "(bad)",          { XX } },
5959     { "(bad)",          { XX } },
5960     { "(bad)",          { XX } },
5961     /* 90 */
5962     { "(bad)",          { XX } },
5963     { "(bad)",          { XX } },
5964     { "(bad)",          { XX } },
5965     { "(bad)",          { XX } },
5966     { "(bad)",          { XX } },
5967     { "(bad)",          { XX } },
5968     { "(bad)",          { XX } },
5969     { "(bad)",          { XX } },
5970     /* 98 */
5971     { "(bad)",          { XX } },
5972     { "(bad)",          { XX } },
5973     { "(bad)",          { XX } },
5974     { "(bad)",          { XX } },
5975     { "(bad)",          { XX } },
5976     { "(bad)",          { XX } },
5977     { "(bad)",          { XX } },
5978     { "(bad)",          { XX } },
5979     /* a0 */
5980     { "(bad)",          { XX } },
5981     { "(bad)",          { XX } },
5982     { "(bad)",          { XX } },
5983     { "(bad)",          { XX } },
5984     { "(bad)",          { XX } },
5985     { "(bad)",          { XX } },
5986     { "(bad)",          { XX } },
5987     { "(bad)",          { XX } },
5988     /* a8 */
5989     { "(bad)",          { XX } },
5990     { "(bad)",          { XX } },
5991     { "(bad)",          { XX } },
5992     { "(bad)",          { XX } },
5993     { "(bad)",          { XX } },
5994     { "(bad)",          { XX } },
5995     { "(bad)",          { XX } },
5996     { "(bad)",          { XX } },
5997     /* b0 */
5998     { "(bad)",          { XX } },
5999     { "(bad)",          { XX } },
6000     { "(bad)",          { XX } },
6001     { "(bad)",          { XX } },
6002     { "(bad)",          { XX } },
6003     { "(bad)",          { XX } },
6004     { "(bad)",          { XX } },
6005     { "(bad)",          { XX } },
6006     /* b8 */
6007     { "(bad)",          { XX } },
6008     { "(bad)",          { XX } },
6009     { "(bad)",          { XX } },
6010     { "(bad)",          { XX } },
6011     { "(bad)",          { XX } },
6012     { "(bad)",          { XX } },
6013     { "(bad)",          { XX } },
6014     { "(bad)",          { XX } },
6015     /* c0 */
6016     { "(bad)",          { XX } },
6017     { "(bad)",          { XX } },
6018     { "(bad)",          { XX } },
6019     { "(bad)",          { XX } },
6020     { "(bad)",          { XX } },
6021     { "(bad)",          { XX } },
6022     { "(bad)",          { XX } },
6023     { "(bad)",          { XX } },
6024     /* c8 */
6025     { "(bad)",          { XX } },
6026     { "(bad)",          { XX } },
6027     { "(bad)",          { XX } },
6028     { "(bad)",          { XX } },
6029     { "(bad)",          { XX } },
6030     { "(bad)",          { XX } },
6031     { "(bad)",          { XX } },
6032     { "(bad)",          { XX } },
6033     /* d0 */
6034     { "(bad)",          { XX } },
6035     { "(bad)",          { XX } },
6036     { "(bad)",          { XX } },
6037     { "(bad)",          { XX } },
6038     { "(bad)",          { XX } },
6039     { "(bad)",          { XX } },
6040     { "(bad)",          { XX } },
6041     { "(bad)",          { XX } },
6042     /* d8 */
6043     { "(bad)",          { XX } },
6044     { "(bad)",          { XX } },
6045     { "(bad)",          { XX } },
6046     { "(bad)",          { XX } },
6047     { "(bad)",          { XX } },
6048     { "(bad)",          { XX } },
6049     { "(bad)",          { XX } },
6050     { PREFIX_TABLE (PREFIX_0F3ADF) },
6051     /* e0 */
6052     { "(bad)",          { XX } },
6053     { "(bad)",          { XX } },
6054     { "(bad)",          { XX } },
6055     { "(bad)",          { XX } },
6056     { "(bad)",          { XX } },
6057     { "(bad)",          { XX } },
6058     { "(bad)",          { XX } },
6059     { "(bad)",          { XX } },
6060     /* e8 */
6061     { "(bad)",          { XX } },
6062     { "(bad)",          { XX } },
6063     { "(bad)",          { XX } },
6064     { "(bad)",          { XX } },
6065     { "(bad)",          { XX } },
6066     { "(bad)",          { XX } },
6067     { "(bad)",          { XX } },
6068     { "(bad)",          { XX } },
6069     /* f0 */
6070     { "(bad)",          { XX } },
6071     { "(bad)",          { XX } },
6072     { "(bad)",          { XX } },
6073     { "(bad)",          { XX } },
6074     { "(bad)",          { XX } },
6075     { "(bad)",          { XX } },
6076     { "(bad)",          { XX } },
6077     { "(bad)",          { XX } },
6078     /* f8 */
6079     { "(bad)",          { XX } },
6080     { "(bad)",          { XX } },
6081     { "(bad)",          { XX } },
6082     { "(bad)",          { XX } },
6083     { "(bad)",          { XX } },
6084     { "(bad)",          { XX } },
6085     { "(bad)",          { XX } },
6086     { "(bad)",          { XX } },
6087   },
6088
6089   /* THREE_BYTE_0F7A */
6090   {
6091     /* 00 */
6092     { "(bad)",          { XX } },
6093     { "(bad)",          { XX } },
6094     { "(bad)",          { XX } },
6095     { "(bad)",          { XX } },
6096     { "(bad)",          { XX } },
6097     { "(bad)",          { XX } },
6098     { "(bad)",          { XX } },
6099     { "(bad)",          { XX } },
6100     /* 08 */
6101     { "(bad)",          { XX } },
6102     { "(bad)",          { XX } },
6103     { "(bad)",          { XX } },
6104     { "(bad)",          { XX } },
6105     { "(bad)",          { XX } },
6106     { "(bad)",          { XX } },
6107     { "(bad)",          { XX } },
6108     { "(bad)",          { XX } },
6109     /* 10 */
6110     { "(bad)",          { XX } },
6111     { "(bad)",          { XX } },
6112     { "(bad)",          { XX } },
6113     { "(bad)",          { XX } },
6114     { "(bad)",          { XX } },
6115     { "(bad)",          { XX } },
6116     { "(bad)",          { XX } },
6117     { "(bad)",          { XX } },
6118     /* 18 */
6119     { "(bad)",          { XX } },
6120     { "(bad)",          { XX } },
6121     { "(bad)",          { XX } },
6122     { "(bad)",          { XX } },
6123     { "(bad)",          { XX } },
6124     { "(bad)",          { XX } },
6125     { "(bad)",          { XX } },
6126     { "(bad)",          { XX } },
6127     /* 20 */
6128     { "ptest",          { XX } },
6129     { "(bad)",          { XX } },
6130     { "(bad)",          { XX } },
6131     { "(bad)",          { XX } },
6132     { "(bad)",          { XX } },
6133     { "(bad)",          { XX } },
6134     { "(bad)",          { XX } },
6135     { "(bad)",          { XX } },
6136     /* 28 */
6137     { "(bad)",          { XX } },
6138     { "(bad)",          { XX } },
6139     { "(bad)",          { XX } },
6140     { "(bad)",          { XX } },
6141     { "(bad)",          { XX } },
6142     { "(bad)",          { XX } },
6143     { "(bad)",          { XX } },
6144     { "(bad)",          { XX } },
6145     /* 30 */
6146     { "(bad)",          { XX } },
6147     { "(bad)",          { XX } },
6148     { "(bad)",          { XX } },
6149     { "(bad)",          { XX } },
6150     { "(bad)",          { XX } },
6151     { "(bad)",          { XX } },
6152     { "(bad)",          { XX } },
6153     { "(bad)",          { XX } },
6154     /* 38 */
6155     { "(bad)",          { XX } },
6156     { "(bad)",          { XX } },
6157     { "(bad)",          { XX } },
6158     { "(bad)",          { XX } },
6159     { "(bad)",          { XX } },
6160     { "(bad)",          { XX } },
6161     { "(bad)",          { XX } },
6162     { "(bad)",          { XX } },
6163     /* 40 */
6164     { "(bad)",          { XX } },
6165     { "phaddbw",        { XM, EXq } },
6166     { "phaddbd",        { XM, EXq } },
6167     { "phaddbq",        { XM, EXq } },
6168     { "(bad)",          { XX } },
6169     { "(bad)",          { XX } },
6170     { "phaddwd",        { XM, EXq } },
6171     { "phaddwq",        { XM, EXq } },
6172     /* 48 */
6173     { "(bad)",          { XX } },
6174     { "(bad)",          { XX } },
6175     { "(bad)",          { XX } },
6176     { "phadddq",        { XM, EXq } },
6177     { "(bad)",          { XX } },
6178     { "(bad)",          { XX } },
6179     { "(bad)",          { XX } },
6180     { "(bad)",          { XX } },
6181     /* 50 */
6182     { "(bad)",          { XX } },
6183     { "phaddubw",       { XM, EXq } },
6184     { "phaddubd",       { XM, EXq } },
6185     { "phaddubq",       { XM, EXq } },
6186     { "(bad)",          { XX } },
6187     { "(bad)",          { XX } },
6188     { "phadduwd",       { XM, EXq } },
6189     { "phadduwq",       { XM, EXq } },
6190     /* 58 */
6191     { "(bad)",          { XX } },
6192     { "(bad)",          { XX } },
6193     { "(bad)",          { XX } },
6194     { "phaddudq",       { XM, EXq } },
6195     { "(bad)",          { XX } },
6196     { "(bad)",          { XX } },
6197     { "(bad)",          { XX } },
6198     { "(bad)",          { XX } },
6199     /* 60 */
6200     { "(bad)",          { XX } },
6201     { "phsubbw",        { XM, EXq } },
6202     { "phsubbd",        { XM, EXq } },
6203     { "phsubbq",        { XM, EXq } },
6204     { "(bad)",          { XX } },
6205     { "(bad)",          { XX } },
6206     { "(bad)",          { XX } },
6207     { "(bad)",          { XX } },
6208     /* 68 */
6209     { "(bad)",          { XX } },
6210     { "(bad)",          { XX } },
6211     { "(bad)",          { XX } },
6212     { "(bad)",          { XX } },
6213     { "(bad)",          { XX } },
6214     { "(bad)",          { XX } },
6215     { "(bad)",          { XX } },
6216     { "(bad)",          { XX } },
6217     /* 70 */
6218     { "(bad)",          { XX } },
6219     { "(bad)",          { XX } },
6220     { "(bad)",          { XX } },
6221     { "(bad)",          { XX } },
6222     { "(bad)",          { XX } },
6223     { "(bad)",          { XX } },
6224     { "(bad)",          { XX } },
6225     { "(bad)",          { XX } },
6226     /* 78 */
6227     { "(bad)",          { XX } },
6228     { "(bad)",          { XX } },
6229     { "(bad)",          { XX } },
6230     { "(bad)",          { XX } },
6231     { "(bad)",          { XX } },
6232     { "(bad)",          { XX } },
6233     { "(bad)",          { XX } },
6234     { "(bad)",          { XX } },
6235     /* 80 */
6236     { "(bad)",          { XX } },
6237     { "(bad)",          { XX } },
6238     { "(bad)",          { XX } },
6239     { "(bad)",          { XX } },
6240     { "(bad)",          { XX } },
6241     { "(bad)",          { XX } },
6242     { "(bad)",          { XX } },
6243     { "(bad)",          { XX } },
6244     /* 88 */
6245     { "(bad)",          { XX } },
6246     { "(bad)",          { XX } },
6247     { "(bad)",          { XX } },
6248     { "(bad)",          { XX } },
6249     { "(bad)",          { XX } },
6250     { "(bad)",          { XX } },
6251     { "(bad)",          { XX } },
6252     { "(bad)",          { XX } },
6253     /* 90 */
6254     { "(bad)",          { XX } },
6255     { "(bad)",          { XX } },
6256     { "(bad)",          { XX } },
6257     { "(bad)",          { XX } },
6258     { "(bad)",          { XX } },
6259     { "(bad)",          { XX } },
6260     { "(bad)",          { XX } },
6261     { "(bad)",          { XX } },
6262     /* 98 */
6263     { "(bad)",          { XX } },
6264     { "(bad)",          { XX } },
6265     { "(bad)",          { XX } },
6266     { "(bad)",          { XX } },
6267     { "(bad)",          { XX } },
6268     { "(bad)",          { XX } },
6269     { "(bad)",          { XX } },
6270     { "(bad)",          { XX } },
6271     /* a0 */
6272     { "(bad)",          { XX } },
6273     { "(bad)",          { XX } },
6274     { "(bad)",          { XX } },
6275     { "(bad)",          { XX } },
6276     { "(bad)",          { XX } },
6277     { "(bad)",          { XX } },
6278     { "(bad)",          { XX } },
6279     { "(bad)",          { XX } },
6280     /* a8 */
6281     { "(bad)",          { XX } },
6282     { "(bad)",          { XX } },
6283     { "(bad)",          { XX } },
6284     { "(bad)",          { XX } },
6285     { "(bad)",          { XX } },
6286     { "(bad)",          { XX } },
6287     { "(bad)",          { XX } },
6288     { "(bad)",          { XX } },
6289     /* b0 */
6290     { "(bad)",          { XX } },
6291     { "(bad)",          { XX } },
6292     { "(bad)",          { XX } },
6293     { "(bad)",          { XX } },
6294     { "(bad)",          { XX } },
6295     { "(bad)",          { XX } },
6296     { "(bad)",          { XX } },
6297     { "(bad)",          { XX } },
6298     /* b8 */
6299     { "(bad)",          { XX } },
6300     { "(bad)",          { XX } },
6301     { "(bad)",          { XX } },
6302     { "(bad)",          { XX } },
6303     { "(bad)",          { XX } },
6304     { "(bad)",          { XX } },
6305     { "(bad)",          { XX } },
6306     { "(bad)",          { XX } },
6307     /* c0 */
6308     { "(bad)",          { XX } },
6309     { "(bad)",          { XX } },
6310     { "(bad)",          { XX } },
6311     { "(bad)",          { XX } },
6312     { "(bad)",          { XX } },
6313     { "(bad)",          { XX } },
6314     { "(bad)",          { XX } },
6315     { "(bad)",          { XX } },
6316     /* c8 */
6317     { "(bad)",          { XX } },
6318     { "(bad)",          { XX } },
6319     { "(bad)",          { XX } },
6320     { "(bad)",          { XX } },
6321     { "(bad)",          { XX } },
6322     { "(bad)",          { XX } },
6323     { "(bad)",          { XX } },
6324     { "(bad)",          { XX } },
6325     /* d0 */
6326     { "(bad)",          { XX } },
6327     { "(bad)",          { XX } },
6328     { "(bad)",          { XX } },
6329     { "(bad)",          { XX } },
6330     { "(bad)",          { XX } },
6331     { "(bad)",          { XX } },
6332     { "(bad)",          { XX } },
6333     { "(bad)",          { XX } },
6334     /* d8 */
6335     { "(bad)",          { XX } },
6336     { "(bad)",          { XX } },
6337     { "(bad)",          { XX } },
6338     { "(bad)",          { XX } },
6339     { "(bad)",          { XX } },
6340     { "(bad)",          { XX } },
6341     { "(bad)",          { XX } },
6342     { "(bad)",          { XX } },
6343     /* e0 */
6344     { "(bad)",          { XX } },
6345     { "(bad)",          { XX } },
6346     { "(bad)",          { XX } },
6347     { "(bad)",          { XX } },
6348     { "(bad)",          { XX } },
6349     { "(bad)",          { XX } },
6350     { "(bad)",          { XX } },
6351     { "(bad)",          { XX } },
6352     /* e8 */
6353     { "(bad)",          { XX } },
6354     { "(bad)",          { XX } },
6355     { "(bad)",          { XX } },
6356     { "(bad)",          { XX } },
6357     { "(bad)",          { XX } },
6358     { "(bad)",          { XX } },
6359     { "(bad)",          { XX } },
6360     { "(bad)",          { XX } },
6361     /* f0 */
6362     { "(bad)",          { XX } },
6363     { "(bad)",          { XX } },
6364     { "(bad)",          { XX } },
6365     { "(bad)",          { XX } },
6366     { "(bad)",          { XX } },
6367     { "(bad)",          { XX } },
6368     { "(bad)",          { XX } },
6369     { "(bad)",          { XX } },
6370     /* f8 */
6371     { "(bad)",          { XX } },
6372     { "(bad)",          { XX } },
6373     { "(bad)",          { XX } },
6374     { "(bad)",          { XX } },
6375     { "(bad)",          { XX } },
6376     { "(bad)",          { XX } },
6377     { "(bad)",          { XX } },
6378     { "(bad)",          { XX } },
6379   },
6380 };
6381
6382 static const struct dis386 xop_table[][256] = {
6383   /* XOP_09 */
6384   {
6385     /* 00 */
6386     { "(bad)",          { XX } },
6387     { "(bad)",          { XX } },
6388     { "(bad)",          { XX } },
6389     { "(bad)",          { XX } },
6390     { "(bad)",          { XX } },
6391     { "(bad)",          { XX } },
6392     { "(bad)",          { XX } },
6393     { "(bad)",          { XX } },
6394     /* 08 */
6395     { "(bad)",          { XX } },
6396     { "(bad)",          { XX } },
6397     { "(bad)",          { XX } },
6398     { "(bad)",          { XX } },
6399     { "(bad)",          { XX } },
6400     { "(bad)",          { XX } },
6401     { "(bad)",          { XX } },
6402     { "(bad)",          { XX } },
6403     /* 10 */
6404     { "(bad)",          { XX } },
6405     { "(bad)",          { XX } },
6406     { REG_TABLE (REG_XOP_LWPCB) },
6407     { "(bad)",          { XX } },
6408     { "(bad)",          { XX } },
6409     { "(bad)",          { XX } },
6410     { "(bad)",          { XX } },
6411     { "(bad)",          { XX } },
6412     /* 18 */
6413     { "(bad)",          { XX } },
6414     { "(bad)",          { XX } },
6415     { "(bad)",          { XX } },
6416     { "(bad)",          { XX } },
6417     { "(bad)",          { XX } },
6418     { "(bad)",          { XX } },
6419     { "(bad)",          { XX } },
6420     { "(bad)",          { XX } },
6421     /* 20 */
6422     { "(bad)",          { XX } },
6423     { "(bad)",          { XX } },
6424     { "(bad)",          { XX } },
6425     { "(bad)",          { XX } },
6426     { "(bad)",          { XX } },
6427     { "(bad)",          { XX } },
6428     { "(bad)",          { XX } },
6429     { "(bad)",          { XX } },
6430     /* 28 */
6431     { "(bad)",          { XX } },
6432     { "(bad)",          { XX } },
6433     { "(bad)",          { XX } },
6434     { "(bad)",          { XX } },
6435     { "(bad)",          { XX } },
6436     { "(bad)",          { XX } },
6437     { "(bad)",          { XX } },
6438     { "(bad)",          { XX } },
6439     /* 30 */
6440     { "(bad)",          { XX } },
6441     { "(bad)",          { XX } },
6442     { "(bad)",          { XX } },
6443     { "(bad)",          { XX } },
6444     { "(bad)",          { XX } },
6445     { "(bad)",          { XX } },
6446     { "(bad)",          { XX } },
6447     { "(bad)",          { XX } },
6448     /* 38 */
6449     { "(bad)",          { XX } },
6450     { "(bad)",          { XX } },
6451     { "(bad)",          { XX } },
6452     { "(bad)",          { XX } },
6453     { "(bad)",          { XX } },
6454     { "(bad)",          { XX } },
6455     { "(bad)",          { XX } },
6456     { "(bad)",          { XX } },
6457     /* 40 */
6458     { "(bad)",          { XX } },
6459     { "(bad)",          { XX } },
6460     { "(bad)",          { XX } },
6461     { "(bad)",          { XX } },
6462     { "(bad)",          { XX } },
6463     { "(bad)",          { XX } },
6464     { "(bad)",          { XX } },
6465     { "(bad)",          { XX } },
6466     /* 48 */
6467     { "(bad)",          { XX } },
6468     { "(bad)",          { XX } },
6469     { "(bad)",          { XX } },
6470     { "(bad)",          { XX } },
6471     { "(bad)",          { XX } },
6472     { "(bad)",          { XX } },
6473     { "(bad)",          { XX } },
6474     { "(bad)",          { XX } },
6475     /* 50 */
6476     { "(bad)",          { XX } },
6477     { "(bad)",          { XX } },
6478     { "(bad)",          { XX } },
6479     { "(bad)",          { XX } },
6480     { "(bad)",          { XX } },
6481     { "(bad)",          { XX } },
6482     { "(bad)",          { XX } },
6483     { "(bad)",          { XX } },
6484     /* 58 */
6485     { "(bad)",          { XX } },
6486     { "(bad)",          { XX } },
6487     { "(bad)",          { XX } },
6488     { "(bad)",          { XX } },
6489     { "(bad)",          { XX } },
6490     { "(bad)",          { XX } },
6491     { "(bad)",          { XX } },
6492     { "(bad)",          { XX } },
6493     /* 60 */
6494     { "(bad)",          { XX } },
6495     { "(bad)",          { XX } },
6496     { "(bad)",          { XX } },
6497     { "(bad)",          { XX } },
6498     { "(bad)",          { XX } },
6499     { "(bad)",          { XX } },
6500     { "(bad)",          { XX } },
6501     { "(bad)",          { XX } },
6502     /* 68 */
6503     { "(bad)",          { XX } },
6504     { "(bad)",          { XX } },
6505     { "(bad)",          { XX } },
6506     { "(bad)",          { XX } },
6507     { "(bad)",          { XX } },
6508     { "(bad)",          { XX } },
6509     { "(bad)",          { XX } },
6510     { "(bad)",          { XX } },
6511     /* 70 */
6512     { "(bad)",          { XX } },
6513     { "(bad)",          { XX } },
6514     { "(bad)",          { XX } },
6515     { "(bad)",          { XX } },
6516     { "(bad)",          { XX } },
6517     { "(bad)",          { XX } },
6518     { "(bad)",          { XX } },
6519     { "(bad)",          { XX } },
6520     /* 78 */
6521     { "(bad)",          { XX } },
6522     { "(bad)",          { XX } },
6523     { "(bad)",          { XX } },
6524     { "(bad)",          { XX } },
6525     { "(bad)",          { XX } },
6526     { "(bad)",          { XX } },
6527     { "(bad)",          { XX } },
6528     { "(bad)",          { XX } },
6529     /* 80 */
6530     { "(bad)",          { XX } },
6531     { "(bad)",          { XX } },
6532     { "(bad)",          { XX } },
6533     { "(bad)",          { XX } },
6534     { "(bad)",          { XX } },
6535     { "(bad)",          { XX } },
6536     { "(bad)",          { XX } },
6537     { "(bad)",          { XX } },
6538     /* 88 */
6539     { "(bad)",          { XX } },
6540     { "(bad)",          { XX } },
6541     { "(bad)",          { XX } },
6542     { "(bad)",          { XX } },
6543     { "(bad)",          { XX } },
6544     { "(bad)",          { XX } },
6545     { "(bad)",          { XX } },
6546     { "(bad)",          { XX } },
6547     /* 90 */
6548     { "(bad)",          { XX } },
6549     { "(bad)",          { XX } },
6550     { "(bad)",          { XX } },
6551     { "(bad)",          { XX } },
6552     { "(bad)",          { XX } },
6553     { "(bad)",          { XX } },
6554     { "(bad)",          { XX } },
6555     { "(bad)",          { XX } },
6556     /* 98 */
6557     { "(bad)",          { XX } },
6558     { "(bad)",          { XX } },
6559     { "(bad)",          { XX } },
6560     { "(bad)",          { XX } },
6561     { "(bad)",          { XX } },
6562     { "(bad)",          { XX } },
6563     { "(bad)",          { XX } },
6564     { "(bad)",          { XX } },
6565     /* a0 */
6566     { "(bad)",          { XX } },
6567     { "(bad)",          { XX } },
6568     { "(bad)",          { XX } },
6569     { "(bad)",          { XX } },
6570     { "(bad)",          { XX } },
6571     { "(bad)",          { XX } },
6572     { "(bad)",          { XX } },
6573     { "(bad)",          { XX } },
6574     /* a8 */
6575     { "(bad)",          { XX } },
6576     { "(bad)",          { XX } },
6577     { "(bad)",          { XX } },
6578     { "(bad)",          { XX } },
6579     { "(bad)",          { XX } },
6580     { "(bad)",          { XX } },
6581     { "(bad)",          { XX } },
6582     { "(bad)",          { XX } },
6583     /* b0 */
6584     { "(bad)",          { XX } },
6585     { "(bad)",          { XX } },
6586     { "(bad)",          { XX } },
6587     { "(bad)",          { XX } },
6588     { "(bad)",          { XX } },
6589     { "(bad)",          { XX } },
6590     { "(bad)",          { XX } },
6591     { "(bad)",          { XX } },
6592     /* b8 */
6593     { "(bad)",          { XX } },
6594     { "(bad)",          { XX } },
6595     { "(bad)",          { XX } },
6596     { "(bad)",          { XX } },
6597     { "(bad)",          { XX } },
6598     { "(bad)",          { XX } },
6599     { "(bad)",          { XX } },
6600     { "(bad)",          { XX } },
6601     /* c0 */
6602     { "(bad)",          { XX } },
6603     { "(bad)",          { XX } },
6604     { "(bad)",          { XX } },
6605     { "(bad)",          { XX } },
6606     { "(bad)",          { XX } },
6607     { "(bad)",          { XX } },
6608     { "(bad)",          { XX } },
6609     { "(bad)",          { XX } },
6610     /* c8 */
6611     { "(bad)",          { XX } },
6612     { "(bad)",          { XX } },
6613     { "(bad)",          { XX } },
6614     { "(bad)",          { XX } },
6615     { "(bad)",          { XX } },
6616     { "(bad)",          { XX } },
6617     { "(bad)",          { XX } },
6618     { "(bad)",          { XX } },
6619     /* d0 */
6620     { "(bad)",          { XX } },
6621     { "(bad)",          { XX } },
6622     { "(bad)",          { XX } },
6623     { "(bad)",          { XX } },
6624     { "(bad)",          { XX } },
6625     { "(bad)",          { XX } },
6626     { "(bad)",          { XX } },
6627     { "(bad)",          { XX } },
6628     /* d8 */
6629     { "(bad)",          { XX } },
6630     { "(bad)",          { XX } },
6631     { "(bad)",          { XX } },
6632     { "(bad)",          { XX } },
6633     { "(bad)",          { XX } },
6634     { "(bad)",          { XX } },
6635     { "(bad)",          { XX } },
6636     { "(bad)",          { XX } },
6637     /* e0 */
6638     { "(bad)",          { XX } },
6639     { "(bad)",          { XX } },
6640     { "(bad)",          { XX } },
6641     { "(bad)",          { XX } },
6642     { "(bad)",          { XX } },
6643     { "(bad)",          { XX } },
6644     { "(bad)",          { XX } },
6645     { "(bad)",          { XX } },
6646     /* e8 */
6647     { "(bad)",          { XX } },
6648     { "(bad)",          { XX } },
6649     { "(bad)",          { XX } },
6650     { "(bad)",          { XX } },
6651     { "(bad)",          { XX } },
6652     { "(bad)",          { XX } },
6653     { "(bad)",          { XX } },
6654     { "(bad)",          { XX } },
6655     /* f0 */
6656     { "(bad)",          { XX } },
6657     { "(bad)",          { XX } },
6658     { "(bad)",          { XX } },
6659     { "(bad)",          { XX } },
6660     { "(bad)",          { XX } },
6661     { "(bad)",          { XX } },
6662     { "(bad)",          { XX } },
6663     { "(bad)",          { XX } },
6664     /* f8 */
6665     { "(bad)",          { XX } },
6666     { "(bad)",          { XX } },
6667     { "(bad)",          { XX } },
6668     { "(bad)",          { XX } },
6669     { "(bad)",          { XX } },
6670     { "(bad)",          { XX } },
6671     { "(bad)",          { XX } },
6672     { "(bad)",          { XX } },
6673   },
6674   /* XOP_0A */
6675   {
6676     /* 00 */
6677     { "(bad)",          { XX } },
6678     { "(bad)",          { XX } },
6679     { "(bad)",          { XX } },
6680     { "(bad)",          { XX } },
6681     { "(bad)",          { XX } },
6682     { "(bad)",          { XX } },
6683     { "(bad)",          { XX } },
6684     { "(bad)",          { XX } },
6685     /* 08 */
6686     { "(bad)",          { XX } },
6687     { "(bad)",          { XX } },
6688     { "(bad)",          { XX } },
6689     { "(bad)",          { XX } },
6690     { "(bad)",          { XX } },
6691     { "(bad)",          { XX } },
6692     { "(bad)",          { XX } },
6693     { "(bad)",          { XX } },
6694     /* 10 */
6695     { "(bad)",          { XX } },
6696     { "(bad)",          { XX } },
6697     { REG_TABLE (REG_XOP_LWP) },
6698     { "(bad)",          { XX } },
6699     { "(bad)",          { XX } },
6700     { "(bad)",          { XX } },
6701     { "(bad)",          { XX } },
6702     { "(bad)",          { XX } },
6703     /* 18 */
6704     { "(bad)",          { XX } },
6705     { "(bad)",          { XX } },
6706     { "(bad)",          { XX } },
6707     { "(bad)",          { XX } },
6708     { "(bad)",          { XX } },
6709     { "(bad)",          { XX } },
6710     { "(bad)",          { XX } },
6711     { "(bad)",          { XX } },
6712     /* 20 */
6713     { "(bad)",          { XX } },
6714     { "(bad)",          { XX } },
6715     { "(bad)",          { XX } },
6716     { "(bad)",          { XX } },
6717     { "(bad)",          { XX } },
6718     { "(bad)",          { XX } },
6719     { "(bad)",          { XX } },
6720     { "(bad)",          { XX } },
6721     /* 28 */
6722     { "(bad)",          { XX } },
6723     { "(bad)",          { XX } },
6724     { "(bad)",          { XX } },
6725     { "(bad)",          { XX } },
6726     { "(bad)",          { XX } },
6727     { "(bad)",          { XX } },
6728     { "(bad)",          { XX } },
6729     { "(bad)",          { XX } },
6730     /* 30 */
6731     { "(bad)",          { XX } },
6732     { "(bad)",          { XX } },
6733     { "(bad)",          { XX } },
6734     { "(bad)",          { XX } },
6735     { "(bad)",          { XX } },
6736     { "(bad)",          { XX } },
6737     { "(bad)",          { XX } },
6738     { "(bad)",          { XX } },
6739     /* 38 */
6740     { "(bad)",          { XX } },
6741     { "(bad)",          { XX } },
6742     { "(bad)",          { XX } },
6743     { "(bad)",          { XX } },
6744     { "(bad)",          { XX } },
6745     { "(bad)",          { XX } },
6746     { "(bad)",          { XX } },
6747     { "(bad)",          { XX } },
6748     /* 40 */
6749     { "(bad)",          { XX } },
6750     { "(bad)",          { XX } },
6751     { "(bad)",          { XX } },
6752     { "(bad)",          { XX } },
6753     { "(bad)",          { XX } },
6754     { "(bad)",          { XX } },
6755     { "(bad)",          { XX } },
6756     { "(bad)",          { XX } },
6757     /* 48 */
6758     { "(bad)",          { XX } },
6759     { "(bad)",          { XX } },
6760     { "(bad)",          { XX } },
6761     { "(bad)",          { XX } },
6762     { "(bad)",          { XX } },
6763     { "(bad)",          { XX } },
6764     { "(bad)",          { XX } },
6765     { "(bad)",          { XX } },
6766     /* 50 */
6767     { "(bad)",          { XX } },
6768     { "(bad)",          { XX } },
6769     { "(bad)",          { XX } },
6770     { "(bad)",          { XX } },
6771     { "(bad)",          { XX } },
6772     { "(bad)",          { XX } },
6773     { "(bad)",          { XX } },
6774     { "(bad)",          { XX } },
6775     /* 58 */
6776     { "(bad)",          { XX } },
6777     { "(bad)",          { XX } },
6778     { "(bad)",          { XX } },
6779     { "(bad)",          { XX } },
6780     { "(bad)",          { XX } },
6781     { "(bad)",          { XX } },
6782     { "(bad)",          { XX } },
6783     { "(bad)",          { XX } },
6784     /* 60 */
6785     { "(bad)",          { XX } },
6786     { "(bad)",          { XX } },
6787     { "(bad)",          { XX } },
6788     { "(bad)",          { XX } },
6789     { "(bad)",          { XX } },
6790     { "(bad)",          { XX } },
6791     { "(bad)",          { XX } },
6792     { "(bad)",          { XX } },
6793     /* 68 */
6794     { "(bad)",          { XX } },
6795     { "(bad)",          { XX } },
6796     { "(bad)",          { XX } },
6797     { "(bad)",          { XX } },
6798     { "(bad)",          { XX } },
6799     { "(bad)",          { XX } },
6800     { "(bad)",          { XX } },
6801     { "(bad)",          { XX } },
6802     /* 70 */
6803     { "(bad)",          { XX } },
6804     { "(bad)",          { XX } },
6805     { "(bad)",          { XX } },
6806     { "(bad)",          { XX } },
6807     { "(bad)",          { XX } },
6808     { "(bad)",          { XX } },
6809     { "(bad)",          { XX } },
6810     { "(bad)",          { XX } },
6811     /* 78 */
6812     { "(bad)",          { XX } },
6813     { "(bad)",          { XX } },
6814     { "(bad)",          { XX } },
6815     { "(bad)",          { XX } },
6816     { "(bad)",          { XX } },
6817     { "(bad)",          { XX } },
6818     { "(bad)",          { XX } },
6819     { "(bad)",          { XX } },
6820     /* 80 */
6821     { "(bad)",          { XX } },
6822     { "(bad)",          { XX } },
6823     { "(bad)",          { XX } },
6824     { "(bad)",          { XX } },
6825     { "(bad)",          { XX } },
6826     { "(bad)",          { XX } },
6827     { "(bad)",          { XX } },
6828     { "(bad)",          { XX } },
6829     /* 88 */
6830     { "(bad)",          { XX } },
6831     { "(bad)",          { XX } },
6832     { "(bad)",          { XX } },
6833     { "(bad)",          { XX } },
6834     { "(bad)",          { XX } },
6835     { "(bad)",          { XX } },
6836     { "(bad)",          { XX } },
6837     { "(bad)",          { XX } },
6838     /* 90 */
6839     { "(bad)",          { XX } },
6840     { "(bad)",          { XX } },
6841     { "(bad)",          { XX } },
6842     { "(bad)",          { XX } },
6843     { "(bad)",          { XX } },
6844     { "(bad)",          { XX } },
6845     { "(bad)",          { XX } },
6846     { "(bad)",          { XX } },
6847     /* 98 */
6848     { "(bad)",          { XX } },
6849     { "(bad)",          { XX } },
6850     { "(bad)",          { XX } },
6851     { "(bad)",          { XX } },
6852     { "(bad)",          { XX } },
6853     { "(bad)",          { XX } },
6854     { "(bad)",          { XX } },
6855     { "(bad)",          { XX } },
6856     /* a0 */
6857     { "(bad)",          { XX } },
6858     { "(bad)",          { XX } },
6859     { "(bad)",          { XX } },
6860     { "(bad)",          { XX } },
6861     { "(bad)",          { XX } },
6862     { "(bad)",          { XX } },
6863     { "(bad)",          { XX } },
6864     { "(bad)",          { XX } },
6865     /* a8 */
6866     { "(bad)",          { XX } },
6867     { "(bad)",          { XX } },
6868     { "(bad)",          { XX } },
6869     { "(bad)",          { XX } },
6870     { "(bad)",          { XX } },
6871     { "(bad)",          { XX } },
6872     { "(bad)",          { XX } },
6873     { "(bad)",          { XX } },
6874     /* b0 */
6875     { "(bad)",          { XX } },
6876     { "(bad)",          { XX } },
6877     { "(bad)",          { XX } },
6878     { "(bad)",          { XX } },
6879     { "(bad)",          { XX } },
6880     { "(bad)",          { XX } },
6881     { "(bad)",          { XX } },
6882     { "(bad)",          { XX } },
6883     /* b8 */
6884     { "(bad)",          { XX } },
6885     { "(bad)",          { XX } },
6886     { "(bad)",          { XX } },
6887     { "(bad)",          { XX } },
6888     { "(bad)",          { XX } },
6889     { "(bad)",          { XX } },
6890     { "(bad)",          { XX } },
6891     { "(bad)",          { XX } },
6892     /* c0 */
6893     { "(bad)",          { XX } },
6894     { "(bad)",          { XX } },
6895     { "(bad)",          { XX } },
6896     { "(bad)",          { XX } },
6897     { "(bad)",          { XX } },
6898     { "(bad)",          { XX } },
6899     { "(bad)",          { XX } },
6900     { "(bad)",          { XX } },
6901     /* c8 */
6902     { "(bad)",          { XX } },
6903     { "(bad)",          { XX } },
6904     { "(bad)",          { XX } },
6905     { "(bad)",          { XX } },
6906     { "(bad)",          { XX } },
6907     { "(bad)",          { XX } },
6908     { "(bad)",          { XX } },
6909     { "(bad)",          { XX } },
6910     /* d0 */
6911     { "(bad)",          { XX } },
6912     { "(bad)",          { XX } },
6913     { "(bad)",          { XX } },
6914     { "(bad)",          { XX } },
6915     { "(bad)",          { XX } },
6916     { "(bad)",          { XX } },
6917     { "(bad)",          { XX } },
6918     { "(bad)",          { XX } },
6919     /* d8 */
6920     { "(bad)",          { XX } },
6921     { "(bad)",          { XX } },
6922     { "(bad)",          { XX } },
6923     { "(bad)",          { XX } },
6924     { "(bad)",          { XX } },
6925     { "(bad)",          { XX } },
6926     { "(bad)",          { XX } },
6927     { "(bad)",          { XX } },
6928     /* e0 */
6929     { "(bad)",          { XX } },
6930     { "(bad)",          { XX } },
6931     { "(bad)",          { XX } },
6932     { "(bad)",          { XX } },
6933     { "(bad)",          { XX } },
6934     { "(bad)",          { XX } },
6935     { "(bad)",          { XX } },
6936     { "(bad)",          { XX } },
6937     /* e8 */
6938     { "(bad)",          { XX } },
6939     { "(bad)",          { XX } },
6940     { "(bad)",          { XX } },
6941     { "(bad)",          { XX } },
6942     { "(bad)",          { XX } },
6943     { "(bad)",          { XX } },
6944     { "(bad)",          { XX } },
6945     { "(bad)",          { XX } },
6946     /* f0 */
6947     { "(bad)",          { XX } },
6948     { "(bad)",          { XX } },
6949     { "(bad)",          { XX } },
6950     { "(bad)",          { XX } },
6951     { "(bad)",          { XX } },
6952     { "(bad)",          { XX } },
6953     { "(bad)",          { XX } },
6954     { "(bad)",          { XX } },
6955     /* f8 */
6956     { "(bad)",          { XX } },
6957     { "(bad)",          { XX } },
6958     { "(bad)",          { XX } },
6959     { "(bad)",          { XX } },
6960     { "(bad)",          { XX } },
6961     { "(bad)",          { XX } },
6962     { "(bad)",          { XX } },
6963     { "(bad)",          { XX } },
6964   },
6965 };
6966
6967 static const struct dis386 vex_table[][256] = {
6968   /* VEX_0F */
6969   {
6970     /* 00 */
6971     { "(bad)",          { XX } },
6972     { "(bad)",          { XX } },
6973     { "(bad)",          { XX } },
6974     { "(bad)",          { XX } },
6975     { "(bad)",          { XX } },
6976     { "(bad)",          { XX } },
6977     { "(bad)",          { XX } },
6978     { "(bad)",          { XX } },
6979     /* 08 */
6980     { "(bad)",          { XX } },
6981     { "(bad)",          { XX } },
6982     { "(bad)",          { XX } },
6983     { "(bad)",          { XX } },
6984     { "(bad)",          { XX } },
6985     { "(bad)",          { XX } },
6986     { "(bad)",          { XX } },
6987     { "(bad)",          { XX } },
6988     /* 10 */
6989     { PREFIX_TABLE (PREFIX_VEX_10) },
6990     { PREFIX_TABLE (PREFIX_VEX_11) },
6991     { PREFIX_TABLE (PREFIX_VEX_12) },
6992     { MOD_TABLE (MOD_VEX_13) },
6993     { "vunpcklpX",      { XM, Vex, EXx } },
6994     { "vunpckhpX",      { XM, Vex, EXx } },
6995     { PREFIX_TABLE (PREFIX_VEX_16) },
6996     { MOD_TABLE (MOD_VEX_17) },
6997     /* 18 */
6998     { "(bad)",          { XX } },
6999     { "(bad)",          { XX } },
7000     { "(bad)",          { XX } },
7001     { "(bad)",          { XX } },
7002     { "(bad)",          { XX } },
7003     { "(bad)",          { XX } },
7004     { "(bad)",          { XX } },
7005     { "(bad)",          { XX } },
7006     /* 20 */
7007     { "(bad)",          { XX } },
7008     { "(bad)",          { XX } },
7009     { "(bad)",          { XX } },
7010     { "(bad)",          { XX } },
7011     { "(bad)",          { XX } },
7012     { "(bad)",          { XX } },
7013     { "(bad)",          { XX } },
7014     { "(bad)",          { XX } },
7015     /* 28 */
7016     { "vmovapX",        { XM, EXx } },
7017     { "vmovapX",        { EXxS, XM } },
7018     { PREFIX_TABLE (PREFIX_VEX_2A) },
7019     { MOD_TABLE (MOD_VEX_2B) },
7020     { PREFIX_TABLE (PREFIX_VEX_2C) },
7021     { PREFIX_TABLE (PREFIX_VEX_2D) },
7022     { PREFIX_TABLE (PREFIX_VEX_2E) },
7023     { PREFIX_TABLE (PREFIX_VEX_2F) },
7024     /* 30 */
7025     { "(bad)",          { XX } },
7026     { "(bad)",          { XX } },
7027     { "(bad)",          { XX } },
7028     { "(bad)",          { XX } },
7029     { "(bad)",          { XX } },
7030     { "(bad)",          { XX } },
7031     { "(bad)",          { XX } },
7032     { "(bad)",          { XX } },
7033     /* 38 */
7034     { "(bad)",          { XX } },
7035     { "(bad)",          { XX } },
7036     { "(bad)",          { XX } },
7037     { "(bad)",          { XX } },
7038     { "(bad)",          { XX } },
7039     { "(bad)",          { XX } },
7040     { "(bad)",          { XX } },
7041     { "(bad)",          { XX } },
7042     /* 40 */
7043     { "(bad)",          { XX } },
7044     { "(bad)",          { XX } },
7045     { "(bad)",          { XX } },
7046     { "(bad)",          { XX } },
7047     { "(bad)",          { XX } },
7048     { "(bad)",          { XX } },
7049     { "(bad)",          { XX } },
7050     { "(bad)",          { XX } },
7051     /* 48 */
7052     { "(bad)",          { XX } },
7053     { "(bad)",          { XX } },
7054     { "(bad)",          { XX } },
7055     { "(bad)",          { XX } },
7056     { "(bad)",          { XX } },
7057     { "(bad)",          { XX } },
7058     { "(bad)",          { XX } },
7059     { "(bad)",          { XX } },
7060     /* 50 */
7061     { MOD_TABLE (MOD_VEX_51) },
7062     { PREFIX_TABLE (PREFIX_VEX_51) },
7063     { PREFIX_TABLE (PREFIX_VEX_52) },
7064     { PREFIX_TABLE (PREFIX_VEX_53) },
7065     { "vandpX",         { XM, Vex, EXx } },
7066     { "vandnpX",        { XM, Vex, EXx } },
7067     { "vorpX",          { XM, Vex, EXx } },
7068     { "vxorpX",         { XM, Vex, EXx } },
7069     /* 58 */
7070     { PREFIX_TABLE (PREFIX_VEX_58) },
7071     { PREFIX_TABLE (PREFIX_VEX_59) },
7072     { PREFIX_TABLE (PREFIX_VEX_5A) },
7073     { PREFIX_TABLE (PREFIX_VEX_5B) },
7074     { PREFIX_TABLE (PREFIX_VEX_5C) },
7075     { PREFIX_TABLE (PREFIX_VEX_5D) },
7076     { PREFIX_TABLE (PREFIX_VEX_5E) },
7077     { PREFIX_TABLE (PREFIX_VEX_5F) },
7078     /* 60 */
7079     { PREFIX_TABLE (PREFIX_VEX_60) },
7080     { PREFIX_TABLE (PREFIX_VEX_61) },
7081     { PREFIX_TABLE (PREFIX_VEX_62) },
7082     { PREFIX_TABLE (PREFIX_VEX_63) },
7083     { PREFIX_TABLE (PREFIX_VEX_64) },
7084     { PREFIX_TABLE (PREFIX_VEX_65) },
7085     { PREFIX_TABLE (PREFIX_VEX_66) },
7086     { PREFIX_TABLE (PREFIX_VEX_67) },
7087     /* 68 */
7088     { PREFIX_TABLE (PREFIX_VEX_68) },
7089     { PREFIX_TABLE (PREFIX_VEX_69) },
7090     { PREFIX_TABLE (PREFIX_VEX_6A) },
7091     { PREFIX_TABLE (PREFIX_VEX_6B) },
7092     { PREFIX_TABLE (PREFIX_VEX_6C) },
7093     { PREFIX_TABLE (PREFIX_VEX_6D) },
7094     { PREFIX_TABLE (PREFIX_VEX_6E) },
7095     { PREFIX_TABLE (PREFIX_VEX_6F) },
7096     /* 70 */
7097     { PREFIX_TABLE (PREFIX_VEX_70) },
7098     { REG_TABLE (REG_VEX_71) },
7099     { REG_TABLE (REG_VEX_72) },
7100     { REG_TABLE (REG_VEX_73) },
7101     { PREFIX_TABLE (PREFIX_VEX_74) },
7102     { PREFIX_TABLE (PREFIX_VEX_75) },
7103     { PREFIX_TABLE (PREFIX_VEX_76) },
7104     { PREFIX_TABLE (PREFIX_VEX_77) },
7105     /* 78 */
7106     { "(bad)",          { XX } },
7107     { "(bad)",          { XX } },
7108     { "(bad)",          { XX } },
7109     { "(bad)",          { XX } },
7110     { PREFIX_TABLE (PREFIX_VEX_7C) },
7111     { PREFIX_TABLE (PREFIX_VEX_7D) },
7112     { PREFIX_TABLE (PREFIX_VEX_7E) },
7113     { PREFIX_TABLE (PREFIX_VEX_7F) },
7114     /* 80 */
7115     { "(bad)",          { XX } },
7116     { "(bad)",          { XX } },
7117     { "(bad)",          { XX } },
7118     { "(bad)",          { XX } },
7119     { "(bad)",          { XX } },
7120     { "(bad)",          { XX } },
7121     { "(bad)",          { XX } },
7122     { "(bad)",          { XX } },
7123     /* 88 */
7124     { "(bad)",          { XX } },
7125     { "(bad)",          { XX } },
7126     { "(bad)",          { XX } },
7127     { "(bad)",          { XX } },
7128     { "(bad)",          { XX } },
7129     { "(bad)",          { XX } },
7130     { "(bad)",          { XX } },
7131     { "(bad)",          { XX } },
7132     /* 90 */
7133     { "(bad)",          { XX } },
7134     { "(bad)",          { XX } },
7135     { "(bad)",          { XX } },
7136     { "(bad)",          { XX } },
7137     { "(bad)",          { XX } },
7138     { "(bad)",          { XX } },
7139     { "(bad)",          { XX } },
7140     { "(bad)",          { XX } },
7141     /* 98 */
7142     { "(bad)",          { XX } },
7143     { "(bad)",          { XX } },
7144     { "(bad)",          { XX } },
7145     { "(bad)",          { XX } },
7146     { "(bad)",          { XX } },
7147     { "(bad)",          { XX } },
7148     { "(bad)",          { XX } },
7149     { "(bad)",          { XX } },
7150     /* a0 */
7151     { "(bad)",          { XX } },
7152     { "(bad)",          { XX } },
7153     { "(bad)",          { XX } },
7154     { "(bad)",          { XX } },
7155     { "(bad)",          { XX } },
7156     { "(bad)",          { XX } },
7157     { "(bad)",          { XX } },
7158     { "(bad)",          { XX } },
7159     /* a8 */
7160     { "(bad)",          { XX } },
7161     { "(bad)",          { XX } },
7162     { "(bad)",          { XX } },
7163     { "(bad)",          { XX } },
7164     { "(bad)",          { XX } },
7165     { "(bad)",          { XX } },
7166     { REG_TABLE (REG_VEX_AE) },
7167     { "(bad)",          { XX } },
7168     /* b0 */
7169     { "(bad)",          { XX } },
7170     { "(bad)",          { XX } },
7171     { "(bad)",          { XX } },
7172     { "(bad)",          { XX } },
7173     { "(bad)",          { XX } },
7174     { "(bad)",          { XX } },
7175     { "(bad)",          { XX } },
7176     { "(bad)",          { XX } },
7177     /* b8 */
7178     { "(bad)",          { XX } },
7179     { "(bad)",          { XX } },
7180     { "(bad)",          { XX } },
7181     { "(bad)",          { XX } },
7182     { "(bad)",          { XX } },
7183     { "(bad)",          { XX } },
7184     { "(bad)",          { XX } },
7185     { "(bad)",          { XX } },
7186     /* c0 */
7187     { "(bad)",          { XX } },
7188     { "(bad)",          { XX } },
7189     { PREFIX_TABLE (PREFIX_VEX_C2) },
7190     { "(bad)",          { XX } },
7191     { PREFIX_TABLE (PREFIX_VEX_C4) },
7192     { PREFIX_TABLE (PREFIX_VEX_C5) },
7193     { "vshufpX",        { XM, Vex, EXx, Ib } },
7194     { "(bad)",          { XX } },
7195     /* c8 */
7196     { "(bad)",          { XX } },
7197     { "(bad)",          { XX } },
7198     { "(bad)",          { XX } },
7199     { "(bad)",          { XX } },
7200     { "(bad)",          { XX } },
7201     { "(bad)",          { XX } },
7202     { "(bad)",          { XX } },
7203     { "(bad)",          { XX } },
7204     /* d0 */
7205     { PREFIX_TABLE (PREFIX_VEX_D0) },
7206     { PREFIX_TABLE (PREFIX_VEX_D1) },
7207     { PREFIX_TABLE (PREFIX_VEX_D2) },
7208     { PREFIX_TABLE (PREFIX_VEX_D3) },
7209     { PREFIX_TABLE (PREFIX_VEX_D4) },
7210     { PREFIX_TABLE (PREFIX_VEX_D5) },
7211     { PREFIX_TABLE (PREFIX_VEX_D6) },
7212     { PREFIX_TABLE (PREFIX_VEX_D7) },
7213     /* d8 */
7214     { PREFIX_TABLE (PREFIX_VEX_D8) },
7215     { PREFIX_TABLE (PREFIX_VEX_D9) },
7216     { PREFIX_TABLE (PREFIX_VEX_DA) },
7217     { PREFIX_TABLE (PREFIX_VEX_DB) },
7218     { PREFIX_TABLE (PREFIX_VEX_DC) },
7219     { PREFIX_TABLE (PREFIX_VEX_DD) },
7220     { PREFIX_TABLE (PREFIX_VEX_DE) },
7221     { PREFIX_TABLE (PREFIX_VEX_DF) },
7222     /* e0 */
7223     { PREFIX_TABLE (PREFIX_VEX_E0) },
7224     { PREFIX_TABLE (PREFIX_VEX_E1) },
7225     { PREFIX_TABLE (PREFIX_VEX_E2) },
7226     { PREFIX_TABLE (PREFIX_VEX_E3) },
7227     { PREFIX_TABLE (PREFIX_VEX_E4) },
7228     { PREFIX_TABLE (PREFIX_VEX_E5) },
7229     { PREFIX_TABLE (PREFIX_VEX_E6) },
7230     { PREFIX_TABLE (PREFIX_VEX_E7) },
7231     /* e8 */
7232     { PREFIX_TABLE (PREFIX_VEX_E8) },
7233     { PREFIX_TABLE (PREFIX_VEX_E9) },
7234     { PREFIX_TABLE (PREFIX_VEX_EA) },
7235     { PREFIX_TABLE (PREFIX_VEX_EB) },
7236     { PREFIX_TABLE (PREFIX_VEX_EC) },
7237     { PREFIX_TABLE (PREFIX_VEX_ED) },
7238     { PREFIX_TABLE (PREFIX_VEX_EE) },
7239     { PREFIX_TABLE (PREFIX_VEX_EF) },
7240     /* f0 */
7241     { PREFIX_TABLE (PREFIX_VEX_F0) },
7242     { PREFIX_TABLE (PREFIX_VEX_F1) },
7243     { PREFIX_TABLE (PREFIX_VEX_F2) },
7244     { PREFIX_TABLE (PREFIX_VEX_F3) },
7245     { PREFIX_TABLE (PREFIX_VEX_F4) },
7246     { PREFIX_TABLE (PREFIX_VEX_F5) },
7247     { PREFIX_TABLE (PREFIX_VEX_F6) },
7248     { PREFIX_TABLE (PREFIX_VEX_F7) },
7249     /* f8 */
7250     { PREFIX_TABLE (PREFIX_VEX_F8) },
7251     { PREFIX_TABLE (PREFIX_VEX_F9) },
7252     { PREFIX_TABLE (PREFIX_VEX_FA) },
7253     { PREFIX_TABLE (PREFIX_VEX_FB) },
7254     { PREFIX_TABLE (PREFIX_VEX_FC) },
7255     { PREFIX_TABLE (PREFIX_VEX_FD) },
7256     { PREFIX_TABLE (PREFIX_VEX_FE) },
7257     { "(bad)",          { XX } },
7258   },
7259   /* VEX_0F38 */
7260   {
7261     /* 00 */
7262     { PREFIX_TABLE (PREFIX_VEX_3800) },
7263     { PREFIX_TABLE (PREFIX_VEX_3801) },
7264     { PREFIX_TABLE (PREFIX_VEX_3802) },
7265     { PREFIX_TABLE (PREFIX_VEX_3803) },
7266     { PREFIX_TABLE (PREFIX_VEX_3804) },
7267     { PREFIX_TABLE (PREFIX_VEX_3805) },
7268     { PREFIX_TABLE (PREFIX_VEX_3806) },
7269     { PREFIX_TABLE (PREFIX_VEX_3807) },
7270     /* 08 */
7271     { PREFIX_TABLE (PREFIX_VEX_3808) },
7272     { PREFIX_TABLE (PREFIX_VEX_3809) },
7273     { PREFIX_TABLE (PREFIX_VEX_380A) },
7274     { PREFIX_TABLE (PREFIX_VEX_380B) },
7275     { PREFIX_TABLE (PREFIX_VEX_380C) },
7276     { PREFIX_TABLE (PREFIX_VEX_380D) },
7277     { PREFIX_TABLE (PREFIX_VEX_380E) },
7278     { PREFIX_TABLE (PREFIX_VEX_380F) },
7279     /* 10 */
7280     { "(bad)",          { XX } },
7281     { "(bad)",          { XX } },
7282     { "(bad)",          { XX } },
7283     { "(bad)",          { XX } },
7284     { "(bad)",          { XX } },
7285     { "(bad)",          { XX } },
7286     { "(bad)",          { XX } },
7287     { PREFIX_TABLE (PREFIX_VEX_3817) },
7288     /* 18 */
7289     { PREFIX_TABLE (PREFIX_VEX_3818) },
7290     { PREFIX_TABLE (PREFIX_VEX_3819) },
7291     { PREFIX_TABLE (PREFIX_VEX_381A) },
7292     { "(bad)",          { XX } },
7293     { PREFIX_TABLE (PREFIX_VEX_381C) },
7294     { PREFIX_TABLE (PREFIX_VEX_381D) },
7295     { PREFIX_TABLE (PREFIX_VEX_381E) },
7296     { "(bad)",          { XX } },
7297     /* 20 */
7298     { PREFIX_TABLE (PREFIX_VEX_3820) },
7299     { PREFIX_TABLE (PREFIX_VEX_3821) },
7300     { PREFIX_TABLE (PREFIX_VEX_3822) },
7301     { PREFIX_TABLE (PREFIX_VEX_3823) },
7302     { PREFIX_TABLE (PREFIX_VEX_3824) },
7303     { PREFIX_TABLE (PREFIX_VEX_3825) },
7304     { "(bad)",          { XX } },
7305     { "(bad)",          { XX } },
7306     /* 28 */
7307     { PREFIX_TABLE (PREFIX_VEX_3828) },
7308     { PREFIX_TABLE (PREFIX_VEX_3829) },
7309     { PREFIX_TABLE (PREFIX_VEX_382A) },
7310     { PREFIX_TABLE (PREFIX_VEX_382B) },
7311     { PREFIX_TABLE (PREFIX_VEX_382C) },
7312     { PREFIX_TABLE (PREFIX_VEX_382D) },
7313     { PREFIX_TABLE (PREFIX_VEX_382E) },
7314     { PREFIX_TABLE (PREFIX_VEX_382F) },
7315     /* 30 */
7316     { PREFIX_TABLE (PREFIX_VEX_3830) },
7317     { PREFIX_TABLE (PREFIX_VEX_3831) },
7318     { PREFIX_TABLE (PREFIX_VEX_3832) },
7319     { PREFIX_TABLE (PREFIX_VEX_3833) },
7320     { PREFIX_TABLE (PREFIX_VEX_3834) },
7321     { PREFIX_TABLE (PREFIX_VEX_3835) },
7322     { "(bad)",          { XX } },
7323     { PREFIX_TABLE (PREFIX_VEX_3837) },
7324     /* 38 */
7325     { PREFIX_TABLE (PREFIX_VEX_3838) },
7326     { PREFIX_TABLE (PREFIX_VEX_3839) },
7327     { PREFIX_TABLE (PREFIX_VEX_383A) },
7328     { PREFIX_TABLE (PREFIX_VEX_383B) },
7329     { PREFIX_TABLE (PREFIX_VEX_383C) },
7330     { PREFIX_TABLE (PREFIX_VEX_383D) },
7331     { PREFIX_TABLE (PREFIX_VEX_383E) },
7332     { PREFIX_TABLE (PREFIX_VEX_383F) },
7333     /* 40 */
7334     { PREFIX_TABLE (PREFIX_VEX_3840) },
7335     { PREFIX_TABLE (PREFIX_VEX_3841) },
7336     { "(bad)",          { XX } },
7337     { "(bad)",          { XX } },
7338     { "(bad)",          { XX } },
7339     { "(bad)",          { XX } },
7340     { "(bad)",          { XX } },
7341     { "(bad)",          { XX } },
7342     /* 48 */
7343     { "(bad)",          { XX } },
7344     { "(bad)",          { XX } },
7345     { "(bad)",          { XX } },
7346     { "(bad)",          { XX } },
7347     { "(bad)",          { XX } },
7348     { "(bad)",          { XX } },
7349     { "(bad)",          { XX } },
7350     { "(bad)",          { XX } },
7351     /* 50 */
7352     { "(bad)",          { XX } },
7353     { "(bad)",          { XX } },
7354     { "(bad)",          { XX } },
7355     { "(bad)",          { XX } },
7356     { "(bad)",          { XX } },
7357     { "(bad)",          { XX } },
7358     { "(bad)",          { XX } },
7359     { "(bad)",          { XX } },
7360     /* 58 */
7361     { "(bad)",          { XX } },
7362     { "(bad)",          { XX } },
7363     { "(bad)",          { XX } },
7364     { "(bad)",          { XX } },
7365     { "(bad)",          { XX } },
7366     { "(bad)",          { XX } },
7367     { "(bad)",          { XX } },
7368     { "(bad)",          { XX } },
7369     /* 60 */
7370     { "(bad)",          { XX } },
7371     { "(bad)",          { XX } },
7372     { "(bad)",          { XX } },
7373     { "(bad)",          { XX } },
7374     { "(bad)",          { XX } },
7375     { "(bad)",          { XX } },
7376     { "(bad)",          { XX } },
7377     { "(bad)",          { XX } },
7378     /* 68 */
7379     { "(bad)",          { XX } },
7380     { "(bad)",          { XX } },
7381     { "(bad)",          { XX } },
7382     { "(bad)",          { XX } },
7383     { "(bad)",          { XX } },
7384     { "(bad)",          { XX } },
7385     { "(bad)",          { XX } },
7386     { "(bad)",          { XX } },
7387     /* 70 */
7388     { "(bad)",          { XX } },
7389     { "(bad)",          { XX } },
7390     { "(bad)",          { XX } },
7391     { "(bad)",          { XX } },
7392     { "(bad)",          { XX } },
7393     { "(bad)",          { XX } },
7394     { "(bad)",          { XX } },
7395     { "(bad)",          { XX } },
7396     /* 78 */
7397     { "(bad)",          { XX } },
7398     { "(bad)",          { XX } },
7399     { "(bad)",          { XX } },
7400     { "(bad)",          { XX } },
7401     { "(bad)",          { XX } },
7402     { "(bad)",          { XX } },
7403     { "(bad)",          { XX } },
7404     { "(bad)",          { XX } },
7405     /* 80 */
7406     { "(bad)",          { XX } },
7407     { "(bad)",          { XX } },
7408     { "(bad)",          { XX } },
7409     { "(bad)",          { XX } },
7410     { "(bad)",          { XX } },
7411     { "(bad)",          { XX } },
7412     { "(bad)",          { XX } },
7413     { "(bad)",          { XX } },
7414     /* 88 */
7415     { "(bad)",          { XX } },
7416     { "(bad)",          { XX } },
7417     { "(bad)",          { XX } },
7418     { "(bad)",          { XX } },
7419     { "(bad)",          { XX } },
7420     { "(bad)",          { XX } },
7421     { "(bad)",          { XX } },
7422     { "(bad)",          { XX } },
7423     /* 90 */
7424     { "(bad)",          { XX } },
7425     { "(bad)",          { XX } },
7426     { "(bad)",          { XX } },
7427     { "(bad)",          { XX } },
7428     { "(bad)",          { XX } },
7429     { "(bad)",          { XX } },
7430     { PREFIX_TABLE (PREFIX_VEX_3896) },
7431     { PREFIX_TABLE (PREFIX_VEX_3897) },
7432     /* 98 */
7433     { PREFIX_TABLE (PREFIX_VEX_3898) },
7434     { PREFIX_TABLE (PREFIX_VEX_3899) },
7435     { PREFIX_TABLE (PREFIX_VEX_389A) },
7436     { PREFIX_TABLE (PREFIX_VEX_389B) },
7437     { PREFIX_TABLE (PREFIX_VEX_389C) },
7438     { PREFIX_TABLE (PREFIX_VEX_389D) },
7439     { PREFIX_TABLE (PREFIX_VEX_389E) },
7440     { PREFIX_TABLE (PREFIX_VEX_389F) },
7441     /* a0 */
7442     { "(bad)",          { XX } },
7443     { "(bad)",          { XX } },
7444     { "(bad)",          { XX } },
7445     { "(bad)",          { XX } },
7446     { "(bad)",          { XX } },
7447     { "(bad)",          { XX } },
7448     { PREFIX_TABLE (PREFIX_VEX_38A6) },
7449     { PREFIX_TABLE (PREFIX_VEX_38A7) },
7450     /* a8 */
7451     { PREFIX_TABLE (PREFIX_VEX_38A8) },
7452     { PREFIX_TABLE (PREFIX_VEX_38A9) },
7453     { PREFIX_TABLE (PREFIX_VEX_38AA) },
7454     { PREFIX_TABLE (PREFIX_VEX_38AB) },
7455     { PREFIX_TABLE (PREFIX_VEX_38AC) },
7456     { PREFIX_TABLE (PREFIX_VEX_38AD) },
7457     { PREFIX_TABLE (PREFIX_VEX_38AE) },
7458     { PREFIX_TABLE (PREFIX_VEX_38AF) },
7459     /* b0 */
7460     { "(bad)",          { XX } },
7461     { "(bad)",          { XX } },
7462     { "(bad)",          { XX } },
7463     { "(bad)",          { XX } },
7464     { "(bad)",          { XX } },
7465     { "(bad)",          { XX } },
7466     { PREFIX_TABLE (PREFIX_VEX_38B6) },
7467     { PREFIX_TABLE (PREFIX_VEX_38B7) },
7468     /* b8 */
7469     { PREFIX_TABLE (PREFIX_VEX_38B8) },
7470     { PREFIX_TABLE (PREFIX_VEX_38B9) },
7471     { PREFIX_TABLE (PREFIX_VEX_38BA) },
7472     { PREFIX_TABLE (PREFIX_VEX_38BB) },
7473     { PREFIX_TABLE (PREFIX_VEX_38BC) },
7474     { PREFIX_TABLE (PREFIX_VEX_38BD) },
7475     { PREFIX_TABLE (PREFIX_VEX_38BE) },
7476     { PREFIX_TABLE (PREFIX_VEX_38BF) },
7477     /* c0 */
7478     { "(bad)",          { XX } },
7479     { "(bad)",          { XX } },
7480     { "(bad)",          { XX } },
7481     { "(bad)",          { XX } },
7482     { "(bad)",          { XX } },
7483     { "(bad)",          { XX } },
7484     { "(bad)",          { XX } },
7485     { "(bad)",          { XX } },
7486     /* c8 */
7487     { "(bad)",          { XX } },
7488     { "(bad)",          { XX } },
7489     { "(bad)",          { XX } },
7490     { "(bad)",          { XX } },
7491     { "(bad)",          { XX } },
7492     { "(bad)",          { XX } },
7493     { "(bad)",          { XX } },
7494     { "(bad)",          { XX } },
7495     /* d0 */
7496     { "(bad)",          { XX } },
7497     { "(bad)",          { XX } },
7498     { "(bad)",          { XX } },
7499     { "(bad)",          { XX } },
7500     { "(bad)",          { XX } },
7501     { "(bad)",          { XX } },
7502     { "(bad)",          { XX } },
7503     { "(bad)",          { XX } },
7504     /* d8 */
7505     { "(bad)",          { XX } },
7506     { "(bad)",          { XX } },
7507     { "(bad)",          { XX } },
7508     { PREFIX_TABLE (PREFIX_VEX_38DB) },
7509     { PREFIX_TABLE (PREFIX_VEX_38DC) },
7510     { PREFIX_TABLE (PREFIX_VEX_38DD) },
7511     { PREFIX_TABLE (PREFIX_VEX_38DE) },
7512     { PREFIX_TABLE (PREFIX_VEX_38DF) },
7513     /* e0 */
7514     { "(bad)",          { XX } },
7515     { "(bad)",          { XX } },
7516     { "(bad)",          { XX } },
7517     { "(bad)",          { XX } },
7518     { "(bad)",          { XX } },
7519     { "(bad)",          { XX } },
7520     { "(bad)",          { XX } },
7521     { "(bad)",          { XX } },
7522     /* e8 */
7523     { "(bad)",          { XX } },
7524     { "(bad)",          { XX } },
7525     { "(bad)",          { XX } },
7526     { "(bad)",          { XX } },
7527     { "(bad)",          { XX } },
7528     { "(bad)",          { XX } },
7529     { "(bad)",          { XX } },
7530     { "(bad)",          { XX } },
7531     /* f0 */
7532     { "(bad)",          { XX } },
7533     { "(bad)",          { XX } },
7534     { "(bad)",          { XX } },
7535     { "(bad)",          { XX } },
7536     { "(bad)",          { XX } },
7537     { "(bad)",          { XX } },
7538     { "(bad)",          { XX } },
7539     { "(bad)",          { XX } },
7540     /* f8 */
7541     { "(bad)",          { XX } },
7542     { "(bad)",          { XX } },
7543     { "(bad)",          { XX } },
7544     { "(bad)",          { XX } },
7545     { "(bad)",          { XX } },
7546     { "(bad)",          { XX } },
7547     { "(bad)",          { XX } },
7548     { "(bad)",          { XX } },
7549   },
7550   /* VEX_0F3A */
7551   {
7552     /* 00 */
7553     { "(bad)",          { XX } },
7554     { "(bad)",          { XX } },
7555     { "(bad)",          { XX } },
7556     { "(bad)",          { XX } },
7557     { PREFIX_TABLE (PREFIX_VEX_3A04) },
7558     { PREFIX_TABLE (PREFIX_VEX_3A05) },
7559     { PREFIX_TABLE (PREFIX_VEX_3A06) },
7560     { "(bad)",          { XX } },
7561     /* 08 */
7562     { PREFIX_TABLE (PREFIX_VEX_3A08) },
7563     { PREFIX_TABLE (PREFIX_VEX_3A09) },
7564     { PREFIX_TABLE (PREFIX_VEX_3A0A) },
7565     { PREFIX_TABLE (PREFIX_VEX_3A0B) },
7566     { PREFIX_TABLE (PREFIX_VEX_3A0C) },
7567     { PREFIX_TABLE (PREFIX_VEX_3A0D) },
7568     { PREFIX_TABLE (PREFIX_VEX_3A0E) },
7569     { PREFIX_TABLE (PREFIX_VEX_3A0F) },
7570     /* 10 */
7571     { "(bad)",          { XX } },
7572     { "(bad)",          { XX } },
7573     { "(bad)",          { XX } },
7574     { "(bad)",          { XX } },
7575     { PREFIX_TABLE (PREFIX_VEX_3A14) },
7576     { PREFIX_TABLE (PREFIX_VEX_3A15) },
7577     { PREFIX_TABLE (PREFIX_VEX_3A16) },
7578     { PREFIX_TABLE (PREFIX_VEX_3A17) },
7579     /* 18 */
7580     { PREFIX_TABLE (PREFIX_VEX_3A18) },
7581     { PREFIX_TABLE (PREFIX_VEX_3A19) },
7582     { "(bad)",          { XX } },
7583     { "(bad)",          { XX } },
7584     { "(bad)",          { XX } },
7585     { "(bad)",          { XX } },
7586     { "(bad)",          { XX } },
7587     { "(bad)",          { XX } },
7588     /* 20 */
7589     { PREFIX_TABLE (PREFIX_VEX_3A20) },
7590     { PREFIX_TABLE (PREFIX_VEX_3A21) },
7591     { PREFIX_TABLE (PREFIX_VEX_3A22) },
7592     { "(bad)",          { XX } },
7593     { "(bad)",          { XX } },
7594     { "(bad)",          { XX } },
7595     { "(bad)",          { XX } },
7596     { "(bad)",          { XX } },
7597     /* 28 */
7598     { "(bad)",          { XX } },
7599     { "(bad)",          { XX } },
7600     { "(bad)",          { XX } },
7601     { "(bad)",          { XX } },
7602     { "(bad)",          { XX } },
7603     { "(bad)",          { XX } },
7604     { "(bad)",          { XX } },
7605     { "(bad)",          { XX } },
7606     /* 30 */
7607     { "(bad)",          { XX } },
7608     { "(bad)",          { XX } },
7609     { "(bad)",          { XX } },
7610     { "(bad)",          { XX } },
7611     { "(bad)",          { XX } },
7612     { "(bad)",          { XX } },
7613     { "(bad)",          { XX } },
7614     { "(bad)",          { XX } },
7615     /* 38 */
7616     { "(bad)",          { XX } },
7617     { "(bad)",          { XX } },
7618     { "(bad)",          { XX } },
7619     { "(bad)",          { XX } },
7620     { "(bad)",          { XX } },
7621     { "(bad)",          { XX } },
7622     { "(bad)",          { XX } },
7623     { "(bad)",          { XX } },
7624     /* 40 */
7625     { PREFIX_TABLE (PREFIX_VEX_3A40) },
7626     { PREFIX_TABLE (PREFIX_VEX_3A41) },
7627     { PREFIX_TABLE (PREFIX_VEX_3A42) },
7628     { "(bad)",          { XX } },
7629     { PREFIX_TABLE (PREFIX_VEX_3A44) },
7630     { "(bad)",          { XX } },
7631     { "(bad)",          { XX } },
7632     { "(bad)",          { XX } },
7633     /* 48 */
7634     { "(bad)",          { XX } },
7635     { "(bad)",          { XX } },
7636     { PREFIX_TABLE (PREFIX_VEX_3A4A) },
7637     { PREFIX_TABLE (PREFIX_VEX_3A4B) },
7638     { PREFIX_TABLE (PREFIX_VEX_3A4C) },
7639     { "(bad)",          { XX } },
7640     { "(bad)",          { XX } },
7641     { "(bad)",          { XX } },
7642     /* 50 */
7643     { "(bad)",          { XX } },
7644     { "(bad)",          { XX } },
7645     { "(bad)",          { XX } },
7646     { "(bad)",          { XX } },
7647     { "(bad)",          { XX } },
7648     { "(bad)",          { XX } },
7649     { "(bad)",          { XX } },
7650     { "(bad)",          { XX } },
7651     /* 58 */
7652     { "(bad)",          { XX } },
7653     { "(bad)",          { XX } },
7654     { "(bad)",          { XX } },
7655     { "(bad)",          { XX } },
7656     { PREFIX_TABLE (PREFIX_VEX_3A5C) },
7657     { PREFIX_TABLE (PREFIX_VEX_3A5D) },
7658     { PREFIX_TABLE (PREFIX_VEX_3A5E) },
7659     { PREFIX_TABLE (PREFIX_VEX_3A5F) },
7660     /* 60 */
7661     { PREFIX_TABLE (PREFIX_VEX_3A60) },
7662     { PREFIX_TABLE (PREFIX_VEX_3A61) },
7663     { PREFIX_TABLE (PREFIX_VEX_3A62) },
7664     { PREFIX_TABLE (PREFIX_VEX_3A63) },
7665     { "(bad)",          { XX } },
7666     { "(bad)",          { XX } },
7667     { "(bad)",          { XX } },
7668     { "(bad)",          { XX } },
7669     /* 68 */
7670     { PREFIX_TABLE (PREFIX_VEX_3A68) },
7671     { PREFIX_TABLE (PREFIX_VEX_3A69) },
7672     { PREFIX_TABLE (PREFIX_VEX_3A6A) },
7673     { PREFIX_TABLE (PREFIX_VEX_3A6B) },
7674     { PREFIX_TABLE (PREFIX_VEX_3A6C) },
7675     { PREFIX_TABLE (PREFIX_VEX_3A6D) },
7676     { PREFIX_TABLE (PREFIX_VEX_3A6E) },
7677     { PREFIX_TABLE (PREFIX_VEX_3A6F) },
7678     /* 70 */
7679     { "(bad)",          { XX } },
7680     { "(bad)",          { XX } },
7681     { "(bad)",          { XX } },
7682     { "(bad)",          { XX } },
7683     { "(bad)",          { XX } },
7684     { "(bad)",          { XX } },
7685     { "(bad)",          { XX } },
7686     { "(bad)",          { XX } },
7687     /* 78 */
7688     { PREFIX_TABLE (PREFIX_VEX_3A78) },
7689     { PREFIX_TABLE (PREFIX_VEX_3A79) },
7690     { PREFIX_TABLE (PREFIX_VEX_3A7A) },
7691     { PREFIX_TABLE (PREFIX_VEX_3A7B) },
7692     { PREFIX_TABLE (PREFIX_VEX_3A7C) },
7693     { PREFIX_TABLE (PREFIX_VEX_3A7D) },
7694     { PREFIX_TABLE (PREFIX_VEX_3A7E) },
7695     { PREFIX_TABLE (PREFIX_VEX_3A7F) },
7696     /* 80 */
7697     { "(bad)",          { XX } },
7698     { "(bad)",          { XX } },
7699     { "(bad)",          { XX } },
7700     { "(bad)",          { XX } },
7701     { "(bad)",          { XX } },
7702     { "(bad)",          { XX } },
7703     { "(bad)",          { XX } },
7704     { "(bad)",          { XX } },
7705     /* 88 */
7706     { "(bad)",          { XX } },
7707     { "(bad)",          { XX } },
7708     { "(bad)",          { XX } },
7709     { "(bad)",          { XX } },
7710     { "(bad)",          { XX } },
7711     { "(bad)",          { XX } },
7712     { "(bad)",          { XX } },
7713     { "(bad)",          { XX } },
7714     /* 90 */
7715     { "(bad)",          { XX } },
7716     { "(bad)",          { XX } },
7717     { "(bad)",          { XX } },
7718     { "(bad)",          { XX } },
7719     { "(bad)",          { XX } },
7720     { "(bad)",          { XX } },
7721     { "(bad)",          { XX } },
7722     { "(bad)",          { XX } },
7723     /* 98 */
7724     { "(bad)",          { XX } },
7725     { "(bad)",          { XX } },
7726     { "(bad)",          { XX } },
7727     { "(bad)",          { XX } },
7728     { "(bad)",          { XX } },
7729     { "(bad)",          { XX } },
7730     { "(bad)",          { XX } },
7731     { "(bad)",          { XX } },
7732     /* a0 */
7733     { "(bad)",          { XX } },
7734     { "(bad)",          { XX } },
7735     { "(bad)",          { XX } },
7736     { "(bad)",          { XX } },
7737     { "(bad)",          { XX } },
7738     { "(bad)",          { XX } },
7739     { "(bad)",          { XX } },
7740     { "(bad)",          { XX } },
7741     /* a8 */
7742     { "(bad)",          { XX } },
7743     { "(bad)",          { XX } },
7744     { "(bad)",          { XX } },
7745     { "(bad)",          { XX } },
7746     { "(bad)",          { XX } },
7747     { "(bad)",          { XX } },
7748     { "(bad)",          { XX } },
7749     { "(bad)",          { XX } },
7750     /* b0 */
7751     { "(bad)",          { XX } },
7752     { "(bad)",          { XX } },
7753     { "(bad)",          { XX } },
7754     { "(bad)",          { XX } },
7755     { "(bad)",          { XX } },
7756     { "(bad)",          { XX } },
7757     { "(bad)",          { XX } },
7758     { "(bad)",          { XX } },
7759     /* b8 */
7760     { "(bad)",          { XX } },
7761     { "(bad)",          { XX } },
7762     { "(bad)",          { XX } },
7763     { "(bad)",          { XX } },
7764     { "(bad)",          { XX } },
7765     { "(bad)",          { XX } },
7766     { "(bad)",          { XX } },
7767     { "(bad)",          { XX } },
7768     /* c0 */
7769     { "(bad)",          { XX } },
7770     { "(bad)",          { XX } },
7771     { "(bad)",          { XX } },
7772     { "(bad)",          { XX } },
7773     { "(bad)",          { XX } },
7774     { "(bad)",          { XX } },
7775     { "(bad)",          { XX } },
7776     { "(bad)",          { XX } },
7777     /* c8 */
7778     { "(bad)",          { XX } },
7779     { "(bad)",          { XX } },
7780     { "(bad)",          { XX } },
7781     { "(bad)",          { XX } },
7782     { "(bad)",          { XX } },
7783     { "(bad)",          { XX } },
7784     { "(bad)",          { XX } },
7785     { "(bad)",          { XX } },
7786     /* d0 */
7787     { "(bad)",          { XX } },
7788     { "(bad)",          { XX } },
7789     { "(bad)",          { XX } },
7790     { "(bad)",          { XX } },
7791     { "(bad)",          { XX } },
7792     { "(bad)",          { XX } },
7793     { "(bad)",          { XX } },
7794     { "(bad)",          { XX } },
7795     /* d8 */
7796     { "(bad)",          { XX } },
7797     { "(bad)",          { XX } },
7798     { "(bad)",          { XX } },
7799     { "(bad)",          { XX } },
7800     { "(bad)",          { XX } },
7801     { "(bad)",          { XX } },
7802     { "(bad)",          { XX } },
7803     { PREFIX_TABLE (PREFIX_VEX_3ADF) },
7804     /* e0 */
7805     { "(bad)",          { XX } },
7806     { "(bad)",          { XX } },
7807     { "(bad)",          { XX } },
7808     { "(bad)",          { XX } },
7809     { "(bad)",          { XX } },
7810     { "(bad)",          { XX } },
7811     { "(bad)",          { XX } },
7812     { "(bad)",          { XX } },
7813     /* e8 */
7814     { "(bad)",          { XX } },
7815     { "(bad)",          { XX } },
7816     { "(bad)",          { XX } },
7817     { "(bad)",          { XX } },
7818     { "(bad)",          { XX } },
7819     { "(bad)",          { XX } },
7820     { "(bad)",          { XX } },
7821     { "(bad)",          { XX } },
7822     /* f0 */
7823     { "(bad)",          { XX } },
7824     { "(bad)",          { XX } },
7825     { "(bad)",          { XX } },
7826     { "(bad)",          { XX } },
7827     { "(bad)",          { XX } },
7828     { "(bad)",          { XX } },
7829     { "(bad)",          { XX } },
7830     { "(bad)",          { XX } },
7831     /* f8 */
7832     { "(bad)",          { XX } },
7833     { "(bad)",          { XX } },
7834     { "(bad)",          { XX } },
7835     { "(bad)",          { XX } },
7836     { "(bad)",          { XX } },
7837     { "(bad)",          { XX } },
7838     { "(bad)",          { XX } },
7839     { "(bad)",          { XX } },
7840   },
7841 };
7842
7843 static const struct dis386 vex_len_table[][2] = {
7844   /* VEX_LEN_10_P_1 */
7845   {
7846     { "vmovss",         { XMVex, Vex128, EXd } },
7847     { "(bad)",          { XX } },
7848   },
7849
7850   /* VEX_LEN_10_P_3 */
7851   {
7852     { "vmovsd",         { XMVex, Vex128, EXq } },
7853     { "(bad)",          { XX } },
7854   },
7855
7856   /* VEX_LEN_11_P_1 */
7857   {
7858     { "vmovss",         { EXdVexS, Vex128, XM } },
7859     { "(bad)",          { XX } },
7860   },
7861
7862   /* VEX_LEN_11_P_3 */
7863   {
7864     { "vmovsd",         { EXqVexS, Vex128, XM } },
7865     { "(bad)",          { XX } },
7866   },
7867
7868   /* VEX_LEN_12_P_0_M_0 */
7869   {
7870     { "vmovlps",        { XM, Vex128, EXq } },
7871     { "(bad)",          { XX } },
7872   },
7873
7874   /* VEX_LEN_12_P_0_M_1 */
7875   {
7876     { "vmovhlps",       { XM, Vex128, EXq } },
7877     { "(bad)",          { XX } },
7878   },
7879
7880   /* VEX_LEN_12_P_2 */
7881   {
7882     { "vmovlpd",        { XM, Vex128, EXq } },
7883     { "(bad)",          { XX } },
7884   },
7885
7886   /* VEX_LEN_13_M_0 */
7887   {
7888     { "vmovlpX",        { EXq, XM } },
7889     { "(bad)",          { XX } },
7890   },
7891
7892   /* VEX_LEN_16_P_0_M_0 */
7893   {
7894     { "vmovhps",        { XM, Vex128, EXq } },
7895     { "(bad)",          { XX } },
7896   },
7897
7898   /* VEX_LEN_16_P_0_M_1 */
7899   {
7900     { "vmovlhps",       { XM, Vex128, EXq } },
7901     { "(bad)",          { XX } },
7902   },
7903
7904   /* VEX_LEN_16_P_2 */
7905   {
7906     { "vmovhpd",        { XM, Vex128, EXq } },
7907     { "(bad)",          { XX } },
7908   },
7909
7910   /* VEX_LEN_17_M_0 */
7911   {
7912     { "vmovhpX",        { EXq, XM } },
7913     { "(bad)",          { XX } },
7914   },
7915
7916   /* VEX_LEN_2A_P_1 */
7917   {
7918     { "vcvtsi2ss%LQ",   { XM, Vex128, Ev } },
7919     { "(bad)",          { XX } },
7920   },
7921
7922   /* VEX_LEN_2A_P_3 */
7923   {
7924     { "vcvtsi2sd%LQ",   { XM, Vex128, Ev } },
7925     { "(bad)",          { XX } },
7926   },
7927
7928   /* VEX_LEN_2C_P_1 */
7929   {
7930     { "vcvttss2siY",    { Gv, EXd } },
7931     { "(bad)",          { XX } },
7932   },
7933
7934   /* VEX_LEN_2C_P_3 */
7935   {
7936     { "vcvttsd2siY",    { Gv, EXq } },
7937     { "(bad)",          { XX } },
7938   },
7939
7940   /* VEX_LEN_2D_P_1 */
7941   {
7942     { "vcvtss2siY",     { Gv, EXd } },
7943     { "(bad)",          { XX } },
7944   },
7945
7946   /* VEX_LEN_2D_P_3 */
7947   {
7948     { "vcvtsd2siY",     { Gv, EXq } },
7949     { "(bad)",          { XX } },
7950   },
7951
7952   /* VEX_LEN_2E_P_0 */
7953   {
7954     { "vucomiss",       { XM, EXd } },
7955     { "(bad)",          { XX } },
7956   },
7957
7958   /* VEX_LEN_2E_P_2 */
7959   {
7960     { "vucomisd",       { XM, EXq } },
7961     { "(bad)",          { XX } },
7962   },
7963
7964   /* VEX_LEN_2F_P_0 */
7965   {
7966     { "vcomiss",        { XM, EXd } },
7967     { "(bad)",          { XX } },
7968   },
7969
7970   /* VEX_LEN_2F_P_2 */
7971   {
7972     { "vcomisd",        { XM, EXq } },
7973     { "(bad)",          { XX } },
7974   },
7975
7976   /* VEX_LEN_51_P_1 */
7977   {
7978     { "vsqrtss",        { XM, Vex128, EXd } },
7979     { "(bad)",          { XX } },
7980   },
7981
7982   /* VEX_LEN_51_P_3 */
7983   {
7984     { "vsqrtsd",        { XM, Vex128, EXq } },
7985     { "(bad)",          { XX } },
7986   },
7987
7988   /* VEX_LEN_52_P_1 */
7989   {
7990     { "vrsqrtss",       { XM, Vex128, EXd } },
7991     { "(bad)",          { XX } },
7992   },
7993
7994   /* VEX_LEN_53_P_1 */
7995   {
7996     { "vrcpss",         { XM, Vex128, EXd } },
7997     { "(bad)",          { XX } },
7998   },
7999
8000   /* VEX_LEN_58_P_1 */
8001   {
8002     { "vaddss",         { XM, Vex128, EXd } },
8003     { "(bad)",          { XX } },
8004   },
8005
8006   /* VEX_LEN_58_P_3 */
8007   {
8008     { "vaddsd",         { XM, Vex128, EXq } },
8009     { "(bad)",          { XX } },
8010   },
8011
8012   /* VEX_LEN_59_P_1 */
8013   {
8014     { "vmulss",         { XM, Vex128, EXd } },
8015     { "(bad)",          { XX } },
8016   },
8017
8018   /* VEX_LEN_59_P_3 */
8019   {
8020     { "vmulsd",         { XM, Vex128, EXq } },
8021     { "(bad)",          { XX } },
8022   },
8023
8024   /* VEX_LEN_5A_P_1 */
8025   {
8026     { "vcvtss2sd",      { XM, Vex128, EXd } },
8027     { "(bad)",          { XX } },
8028   },
8029
8030   /* VEX_LEN_5A_P_3 */
8031   {
8032     { "vcvtsd2ss",      { XM, Vex128, EXq } },
8033     { "(bad)",          { XX } },
8034   },
8035
8036   /* VEX_LEN_5C_P_1 */
8037   {
8038     { "vsubss",         { XM, Vex128, EXd } },
8039     { "(bad)",          { XX } },
8040   },
8041
8042   /* VEX_LEN_5C_P_3 */
8043   {
8044     { "vsubsd",         { XM, Vex128, EXq } },
8045     { "(bad)",          { XX } },
8046   },
8047
8048   /* VEX_LEN_5D_P_1 */
8049   {
8050     { "vminss",         { XM, Vex128, EXd } },
8051     { "(bad)",          { XX } },
8052   },
8053
8054   /* VEX_LEN_5D_P_3 */
8055   {
8056     { "vminsd",         { XM, Vex128, EXq } },
8057     { "(bad)",          { XX } },
8058   },
8059
8060   /* VEX_LEN_5E_P_1 */
8061   {
8062     { "vdivss",         { XM, Vex128, EXd } },
8063     { "(bad)",          { XX } },
8064   },
8065
8066   /* VEX_LEN_5E_P_3 */
8067   {
8068     { "vdivsd",         { XM, Vex128, EXq } },
8069     { "(bad)",          { XX } },
8070   },
8071
8072   /* VEX_LEN_5F_P_1 */
8073   {
8074     { "vmaxss",         { XM, Vex128, EXd } },
8075     { "(bad)",          { XX } },
8076   },
8077
8078   /* VEX_LEN_5F_P_3 */
8079   {
8080     { "vmaxsd",         { XM, Vex128, EXq } },
8081     { "(bad)",          { XX } },
8082   },
8083
8084   /* VEX_LEN_60_P_2 */
8085   {
8086     { "vpunpcklbw",     { XM, Vex128, EXx } },
8087     { "(bad)",          { XX } },
8088   },
8089
8090   /* VEX_LEN_61_P_2 */
8091   {
8092     { "vpunpcklwd",     { XM, Vex128, EXx } },
8093     { "(bad)",          { XX } },
8094   },
8095
8096   /* VEX_LEN_62_P_2 */
8097   {
8098     { "vpunpckldq",     { XM, Vex128, EXx } },
8099     { "(bad)",          { XX } },
8100   },
8101
8102   /* VEX_LEN_63_P_2 */
8103   {
8104     { "vpacksswb",      { XM, Vex128, EXx } },
8105     { "(bad)",          { XX } },
8106   },
8107
8108   /* VEX_LEN_64_P_2 */
8109   {
8110     { "vpcmpgtb",       { XM, Vex128, EXx } },
8111     { "(bad)",          { XX } },
8112   },
8113
8114   /* VEX_LEN_65_P_2 */
8115   {
8116     { "vpcmpgtw",       { XM, Vex128, EXx } },
8117     { "(bad)",          { XX } },
8118   },
8119
8120   /* VEX_LEN_66_P_2 */
8121   {
8122     { "vpcmpgtd",       { XM, Vex128, EXx } },
8123     { "(bad)",          { XX } },
8124   },
8125
8126   /* VEX_LEN_67_P_2 */
8127   {
8128     { "vpackuswb",      { XM, Vex128, EXx } },
8129     { "(bad)",          { XX } },
8130   },
8131
8132   /* VEX_LEN_68_P_2 */
8133   {
8134     { "vpunpckhbw",     { XM, Vex128, EXx } },
8135     { "(bad)",          { XX } },
8136   },
8137
8138   /* VEX_LEN_69_P_2 */
8139   {
8140     { "vpunpckhwd",     { XM, Vex128, EXx } },
8141     { "(bad)",          { XX } },
8142   },
8143
8144   /* VEX_LEN_6A_P_2 */
8145   {
8146     { "vpunpckhdq",     { XM, Vex128, EXx } },
8147     { "(bad)",          { XX } },
8148   },
8149
8150   /* VEX_LEN_6B_P_2 */
8151   {
8152     { "vpackssdw",      { XM, Vex128, EXx } },
8153     { "(bad)",          { XX } },
8154   },
8155
8156   /* VEX_LEN_6C_P_2 */
8157   {
8158     { "vpunpcklqdq",    { XM, Vex128, EXx } },
8159     { "(bad)",          { XX } },
8160   },
8161
8162   /* VEX_LEN_6D_P_2 */
8163   {
8164     { "vpunpckhqdq",    { XM, Vex128, EXx } },
8165     { "(bad)",          { XX } },
8166   },
8167
8168   /* VEX_LEN_6E_P_2 */
8169   {
8170     { "vmovK",          { XM, Edq } },
8171     { "(bad)",          { XX } },
8172   },
8173
8174   /* VEX_LEN_70_P_1 */
8175   {
8176     { "vpshufhw",       { XM, EXx, Ib } },
8177     { "(bad)",          { XX } },
8178   },
8179
8180   /* VEX_LEN_70_P_2 */
8181   {
8182     { "vpshufd",        { XM, EXx, Ib } },
8183     { "(bad)",          { XX } },
8184   },
8185
8186   /* VEX_LEN_70_P_3 */
8187   {
8188     { "vpshuflw",       { XM, EXx, Ib } },
8189     { "(bad)",          { XX } },
8190   },
8191
8192   /* VEX_LEN_71_R_2_P_2 */
8193   {
8194     { "vpsrlw",         { Vex128, XS, Ib } },
8195     { "(bad)",          { XX } },
8196   },
8197
8198   /* VEX_LEN_71_R_4_P_2 */
8199   {
8200     { "vpsraw",         { Vex128, XS, Ib } },
8201     { "(bad)",          { XX } },
8202   },
8203
8204   /* VEX_LEN_71_R_6_P_2 */
8205   {
8206     { "vpsllw",         { Vex128, XS, Ib } },
8207     { "(bad)",          { XX } },
8208   },
8209
8210   /* VEX_LEN_72_R_2_P_2 */
8211   {
8212     { "vpsrld",         { Vex128, XS, Ib } },
8213     { "(bad)",          { XX } },
8214   },
8215
8216   /* VEX_LEN_72_R_4_P_2 */
8217   {
8218     { "vpsrad",         { Vex128, XS, Ib } },
8219     { "(bad)",          { XX } },
8220   },
8221
8222   /* VEX_LEN_72_R_6_P_2 */
8223   {
8224     { "vpslld",         { Vex128, XS, Ib } },
8225     { "(bad)",          { XX } },
8226   },
8227
8228   /* VEX_LEN_73_R_2_P_2 */
8229   {
8230     { "vpsrlq",         { Vex128, XS, Ib } },
8231     { "(bad)",          { XX } },
8232   },
8233
8234   /* VEX_LEN_73_R_3_P_2 */
8235   {
8236     { "vpsrldq",        { Vex128, XS, Ib } },
8237     { "(bad)",          { XX } },
8238   },
8239
8240   /* VEX_LEN_73_R_6_P_2 */
8241   {
8242     { "vpsllq",         { Vex128, XS, Ib } },
8243     { "(bad)",          { XX } },
8244   },
8245
8246   /* VEX_LEN_73_R_7_P_2 */
8247   {
8248     { "vpslldq",        { Vex128, XS, Ib } },
8249     { "(bad)",          { XX } },
8250   },
8251
8252   /* VEX_LEN_74_P_2 */
8253   {
8254     { "vpcmpeqb",       { XM, Vex128, EXx } },
8255     { "(bad)",          { XX } },
8256   },
8257
8258   /* VEX_LEN_75_P_2 */
8259   {
8260     { "vpcmpeqw",       { XM, Vex128, EXx } },
8261     { "(bad)",          { XX } },
8262   },
8263
8264   /* VEX_LEN_76_P_2 */
8265   {
8266     { "vpcmpeqd",       { XM, Vex128, EXx } },
8267     { "(bad)",          { XX } },
8268   },
8269
8270   /* VEX_LEN_7E_P_1 */
8271   {
8272     { "vmovq",          { XM, EXq } },
8273     { "(bad)",          { XX } },
8274   },
8275
8276   /* VEX_LEN_7E_P_2 */
8277   {
8278     { "vmovK",          { Edq, XM } },
8279     { "(bad)",          { XX } },
8280   },
8281
8282   /* VEX_LEN_AE_R_2_M_0 */
8283   {
8284     { "vldmxcsr",       { Md } },
8285     { "(bad)",          { XX } },
8286   },
8287
8288   /* VEX_LEN_AE_R_3_M_0 */
8289   {
8290     { "vstmxcsr",       { Md } },
8291     { "(bad)",          { XX } },
8292   },
8293
8294   /* VEX_LEN_C2_P_1 */
8295   {
8296     { "vcmpss",         { XM, Vex128, EXd, VCMP } },
8297     { "(bad)",          { XX } },
8298   },
8299
8300   /* VEX_LEN_C2_P_3 */
8301   {
8302     { "vcmpsd",         { XM, Vex128, EXq, VCMP } },
8303     { "(bad)",          { XX } },
8304   },
8305
8306   /* VEX_LEN_C4_P_2 */
8307   {
8308     { "vpinsrw",        { XM, Vex128, Edqw, Ib } },
8309     { "(bad)",          { XX } },
8310   },
8311
8312   /* VEX_LEN_C5_P_2 */
8313   {
8314     { "vpextrw",        { Gdq, XS, Ib } },
8315     { "(bad)",          { XX } },
8316   },
8317
8318   /* VEX_LEN_D1_P_2 */
8319   {
8320     { "vpsrlw",         { XM, Vex128, EXx } },
8321     { "(bad)",          { XX } },
8322   },
8323
8324   /* VEX_LEN_D2_P_2 */
8325   {
8326     { "vpsrld",         { XM, Vex128, EXx } },
8327     { "(bad)",          { XX } },
8328   },
8329
8330   /* VEX_LEN_D3_P_2 */
8331   {
8332     { "vpsrlq",         { XM, Vex128, EXx } },
8333     { "(bad)",          { XX } },
8334   },
8335
8336   /* VEX_LEN_D4_P_2 */
8337   {
8338     { "vpaddq",         { XM, Vex128, EXx } },
8339     { "(bad)",          { XX } },
8340   },
8341
8342   /* VEX_LEN_D5_P_2 */
8343   {
8344     { "vpmullw",        { XM, Vex128, EXx } },
8345     { "(bad)",          { XX } },
8346   },
8347
8348   /* VEX_LEN_D6_P_2 */
8349   {
8350     { "vmovq",          { EXqS, XM } },
8351     { "(bad)",          { XX } },
8352   },
8353
8354   /* VEX_LEN_D7_P_2_M_1 */
8355   {
8356     { "vpmovmskb",      { Gdq, XS } },
8357     { "(bad)",          { XX } },
8358   },
8359
8360   /* VEX_LEN_D8_P_2 */
8361   {
8362     { "vpsubusb",       { XM, Vex128, EXx } },
8363     { "(bad)",          { XX } },
8364   },
8365
8366   /* VEX_LEN_D9_P_2 */
8367   {
8368     { "vpsubusw",       { XM, Vex128, EXx } },
8369     { "(bad)",          { XX } },
8370   },
8371
8372   /* VEX_LEN_DA_P_2 */
8373   {
8374     { "vpminub",        { XM, Vex128, EXx } },
8375     { "(bad)",          { XX } },
8376   },
8377
8378   /* VEX_LEN_DB_P_2 */
8379   {
8380     { "vpand",          { XM, Vex128, EXx } },
8381     { "(bad)",          { XX } },
8382   },
8383
8384   /* VEX_LEN_DC_P_2 */
8385   {
8386     { "vpaddusb",       { XM, Vex128, EXx } },
8387     { "(bad)",          { XX } },
8388   },
8389
8390   /* VEX_LEN_DD_P_2 */
8391   {
8392     { "vpaddusw",       { XM, Vex128, EXx } },
8393     { "(bad)",          { XX } },
8394   },
8395
8396   /* VEX_LEN_DE_P_2 */
8397   {
8398     { "vpmaxub",        { XM, Vex128, EXx } },
8399     { "(bad)",          { XX } },
8400   },
8401
8402   /* VEX_LEN_DF_P_2 */
8403   {
8404     { "vpandn",         { XM, Vex128, EXx } },
8405     { "(bad)",          { XX } },
8406   },
8407
8408   /* VEX_LEN_E0_P_2 */
8409   {
8410     { "vpavgb",         { XM, Vex128, EXx } },
8411     { "(bad)",          { XX } },
8412   },
8413
8414   /* VEX_LEN_E1_P_2 */
8415   {
8416     { "vpsraw",         { XM, Vex128, EXx } },
8417     { "(bad)",          { XX } },
8418   },
8419
8420   /* VEX_LEN_E2_P_2 */
8421   {
8422     { "vpsrad",         { XM, Vex128, EXx } },
8423     { "(bad)",          { XX } },
8424   },
8425
8426   /* VEX_LEN_E3_P_2 */
8427   {
8428     { "vpavgw",         { XM, Vex128, EXx } },
8429     { "(bad)",          { XX } },
8430   },
8431
8432   /* VEX_LEN_E4_P_2 */
8433   {
8434     { "vpmulhuw",       { XM, Vex128, EXx } },
8435     { "(bad)",          { XX } },
8436   },
8437
8438   /* VEX_LEN_E5_P_2 */
8439   {
8440     { "vpmulhw",        { XM, Vex128, EXx } },
8441     { "(bad)",          { XX } },
8442   },
8443
8444   /* VEX_LEN_E8_P_2 */
8445   {
8446     { "vpsubsb",        { XM, Vex128, EXx } },
8447     { "(bad)",          { XX } },
8448   },
8449
8450   /* VEX_LEN_E9_P_2 */
8451   {
8452     { "vpsubsw",        { XM, Vex128, EXx } },
8453     { "(bad)",          { XX } },
8454   },
8455
8456   /* VEX_LEN_EA_P_2 */
8457   {
8458     { "vpminsw",        { XM, Vex128, EXx } },
8459     { "(bad)",          { XX } },
8460   },
8461
8462   /* VEX_LEN_EB_P_2 */
8463   {
8464     { "vpor",           { XM, Vex128, EXx } },
8465     { "(bad)",          { XX } },
8466   },
8467
8468   /* VEX_LEN_EC_P_2 */
8469   {
8470     { "vpaddsb",        { XM, Vex128, EXx } },
8471     { "(bad)",          { XX } },
8472   },
8473
8474   /* VEX_LEN_ED_P_2 */
8475   {
8476     { "vpaddsw",        { XM, Vex128, EXx } },
8477     { "(bad)",          { XX } },
8478   },
8479
8480   /* VEX_LEN_EE_P_2 */
8481   {
8482     { "vpmaxsw",        { XM, Vex128, EXx } },
8483     { "(bad)",          { XX } },
8484   },
8485
8486   /* VEX_LEN_EF_P_2 */
8487   {
8488     { "vpxor",          { XM, Vex128, EXx } },
8489     { "(bad)",          { XX } },
8490   },
8491
8492   /* VEX_LEN_F1_P_2 */
8493   {
8494     { "vpsllw",         { XM, Vex128, EXx } },
8495     { "(bad)",          { XX } },
8496   },
8497
8498   /* VEX_LEN_F2_P_2 */
8499   {
8500     { "vpslld",         { XM, Vex128, EXx } },
8501     { "(bad)",          { XX } },
8502   },
8503
8504   /* VEX_LEN_F3_P_2 */
8505   {
8506     { "vpsllq",         { XM, Vex128, EXx } },
8507     { "(bad)",          { XX } },
8508   },
8509
8510   /* VEX_LEN_F4_P_2 */
8511   {
8512     { "vpmuludq",       { XM, Vex128, EXx } },
8513     { "(bad)",          { XX } },
8514   },
8515
8516   /* VEX_LEN_F5_P_2 */
8517   {
8518     { "vpmaddwd",       { XM, Vex128, EXx } },
8519     { "(bad)",          { XX } },
8520   },
8521
8522   /* VEX_LEN_F6_P_2 */
8523   {
8524     { "vpsadbw",        { XM, Vex128, EXx } },
8525     { "(bad)",          { XX } },
8526   },
8527
8528   /* VEX_LEN_F7_P_2 */
8529   {
8530     { "vmaskmovdqu",    { XM, XS } },
8531     { "(bad)",          { XX } },
8532   },
8533
8534   /* VEX_LEN_F8_P_2 */
8535   {
8536     { "vpsubb",         { XM, Vex128, EXx } },
8537     { "(bad)",          { XX } },
8538   },
8539
8540   /* VEX_LEN_F9_P_2 */
8541   {
8542     { "vpsubw",         { XM, Vex128, EXx } },
8543     { "(bad)",          { XX } },
8544   },
8545
8546   /* VEX_LEN_FA_P_2 */
8547   {
8548     { "vpsubd",         { XM, Vex128, EXx } },
8549     { "(bad)",          { XX } },
8550   },
8551
8552   /* VEX_LEN_FB_P_2 */
8553   {
8554     { "vpsubq",         { XM, Vex128, EXx } },
8555     { "(bad)",          { XX } },
8556   },
8557
8558   /* VEX_LEN_FC_P_2 */
8559   {
8560     { "vpaddb",         { XM, Vex128, EXx } },
8561     { "(bad)",          { XX } },
8562   },
8563
8564   /* VEX_LEN_FD_P_2 */
8565   {
8566     { "vpaddw",         { XM, Vex128, EXx } },
8567     { "(bad)",          { XX } },
8568   },
8569
8570   /* VEX_LEN_FE_P_2 */
8571   {
8572     { "vpaddd",         { XM, Vex128, EXx } },
8573     { "(bad)",          { XX } },
8574   },
8575
8576   /* VEX_LEN_3800_P_2 */
8577   {
8578     { "vpshufb",        { XM, Vex128, EXx } },
8579     { "(bad)",          { XX } },
8580   },
8581
8582   /* VEX_LEN_3801_P_2 */
8583   {
8584     { "vphaddw",        { XM, Vex128, EXx } },
8585     { "(bad)",          { XX } },
8586   },
8587
8588   /* VEX_LEN_3802_P_2 */
8589   {
8590     { "vphaddd",        { XM, Vex128, EXx } },
8591     { "(bad)",          { XX } },
8592   },
8593
8594   /* VEX_LEN_3803_P_2 */
8595   {
8596     { "vphaddsw",       { XM, Vex128, EXx } },
8597     { "(bad)",          { XX } },
8598   },
8599
8600   /* VEX_LEN_3804_P_2 */
8601   {
8602     { "vpmaddubsw",     { XM, Vex128, EXx } },
8603     { "(bad)",          { XX } },
8604   },
8605
8606   /* VEX_LEN_3805_P_2 */
8607   {
8608     { "vphsubw",        { XM, Vex128, EXx } },
8609     { "(bad)",          { XX } },
8610   },
8611
8612   /* VEX_LEN_3806_P_2 */
8613   {
8614     { "vphsubd",        { XM, Vex128, EXx } },
8615     { "(bad)",          { XX } },
8616   },
8617
8618   /* VEX_LEN_3807_P_2 */
8619   {
8620     { "vphsubsw",       { XM, Vex128, EXx } },
8621     { "(bad)",          { XX } },
8622   },
8623
8624   /* VEX_LEN_3808_P_2 */
8625   {
8626     { "vpsignb",        { XM, Vex128, EXx } },
8627     { "(bad)",          { XX } },
8628   },
8629
8630   /* VEX_LEN_3809_P_2 */
8631   {
8632     { "vpsignw",        { XM, Vex128, EXx } },
8633     { "(bad)",          { XX } },
8634   },
8635
8636   /* VEX_LEN_380A_P_2 */
8637   {
8638     { "vpsignd",        { XM, Vex128, EXx } },
8639     { "(bad)",          { XX } },
8640   },
8641
8642   /* VEX_LEN_380B_P_2 */
8643   {
8644     { "vpmulhrsw",      { XM, Vex128, EXx } },
8645     { "(bad)",          { XX } },
8646   },
8647
8648   /* VEX_LEN_3819_P_2_M_0 */
8649   {
8650     { "(bad)",          { XX } },
8651     { "vbroadcastsd",   { XM, Mq } },
8652   },
8653
8654   /* VEX_LEN_381A_P_2_M_0 */
8655   {
8656     { "(bad)",          { XX } },
8657     { "vbroadcastf128", { XM, Mxmm } },
8658   },
8659
8660   /* VEX_LEN_381C_P_2 */
8661   {
8662     { "vpabsb",         { XM, EXx } },
8663     { "(bad)",          { XX } },
8664   },
8665
8666   /* VEX_LEN_381D_P_2 */
8667   {
8668     { "vpabsw",         { XM, EXx } },
8669     { "(bad)",          { XX } },
8670   },
8671
8672   /* VEX_LEN_381E_P_2 */
8673   {
8674     { "vpabsd",         { XM, EXx } },
8675     { "(bad)",          { XX } },
8676   },
8677
8678   /* VEX_LEN_3820_P_2 */
8679   {
8680     { "vpmovsxbw",      { XM, EXq } },
8681     { "(bad)",          { XX } },
8682   },
8683
8684   /* VEX_LEN_3821_P_2 */
8685   {
8686     { "vpmovsxbd",      { XM, EXd } },
8687     { "(bad)",          { XX } },
8688   },
8689
8690   /* VEX_LEN_3822_P_2 */
8691   {
8692     { "vpmovsxbq",      { XM, EXw } },
8693     { "(bad)",          { XX } },
8694   },
8695
8696   /* VEX_LEN_3823_P_2 */
8697   {
8698     { "vpmovsxwd",      { XM, EXq } },
8699     { "(bad)",          { XX } },
8700   },
8701
8702   /* VEX_LEN_3824_P_2 */
8703   {
8704     { "vpmovsxwq",      { XM, EXd } },
8705     { "(bad)",          { XX } },
8706   },
8707
8708   /* VEX_LEN_3825_P_2 */
8709   {
8710     { "vpmovsxdq",      { XM, EXq } },
8711     { "(bad)",          { XX } },
8712   },
8713
8714   /* VEX_LEN_3828_P_2 */
8715   {
8716     { "vpmuldq",        { XM, Vex128, EXx } },
8717     { "(bad)",          { XX } },
8718   },
8719
8720   /* VEX_LEN_3829_P_2 */
8721   {
8722     { "vpcmpeqq",       { XM, Vex128, EXx } },
8723     { "(bad)",          { XX } },
8724   },
8725
8726   /* VEX_LEN_382A_P_2_M_0 */
8727   {
8728     { "vmovntdqa",      { XM, Mx } },
8729     { "(bad)",          { XX } },
8730   },
8731
8732   /* VEX_LEN_382B_P_2 */
8733   {
8734     { "vpackusdw",      { XM, Vex128, EXx } },
8735     { "(bad)",          { XX } },
8736   },
8737
8738   /* VEX_LEN_3830_P_2 */
8739   {
8740     { "vpmovzxbw",      { XM, EXq } },
8741     { "(bad)",          { XX } },
8742   },
8743
8744   /* VEX_LEN_3831_P_2 */
8745   {
8746     { "vpmovzxbd",      { XM, EXd } },
8747     { "(bad)",          { XX } },
8748   },
8749
8750   /* VEX_LEN_3832_P_2 */
8751   {
8752     { "vpmovzxbq",      { XM, EXw } },
8753     { "(bad)",          { XX } },
8754   },
8755
8756   /* VEX_LEN_3833_P_2 */
8757   {
8758     { "vpmovzxwd",      { XM, EXq } },
8759     { "(bad)",          { XX } },
8760   },
8761
8762   /* VEX_LEN_3834_P_2 */
8763   {
8764     { "vpmovzxwq",      { XM, EXd } },
8765     { "(bad)",          { XX } },
8766   },
8767
8768   /* VEX_LEN_3835_P_2 */
8769   {
8770     { "vpmovzxdq",      { XM, EXq } },
8771     { "(bad)",          { XX } },
8772   },
8773
8774   /* VEX_LEN_3837_P_2 */
8775   {
8776     { "vpcmpgtq",       { XM, Vex128, EXx } },
8777     { "(bad)",          { XX } },
8778   },
8779
8780   /* VEX_LEN_3838_P_2 */
8781   {
8782     { "vpminsb",        { XM, Vex128, EXx } },
8783     { "(bad)",          { XX } },
8784   },
8785
8786   /* VEX_LEN_3839_P_2 */
8787   {
8788     { "vpminsd",        { XM, Vex128, EXx } },
8789     { "(bad)",          { XX } },
8790   },
8791
8792   /* VEX_LEN_383A_P_2 */
8793   {
8794     { "vpminuw",        { XM, Vex128, EXx } },
8795     { "(bad)",          { XX } },
8796   },
8797
8798   /* VEX_LEN_383B_P_2 */
8799   {
8800     { "vpminud",        { XM, Vex128, EXx } },
8801     { "(bad)",          { XX } },
8802   },
8803
8804   /* VEX_LEN_383C_P_2 */
8805   {
8806     { "vpmaxsb",        { XM, Vex128, EXx } },
8807     { "(bad)",          { XX } },
8808   },
8809
8810   /* VEX_LEN_383D_P_2 */
8811   {
8812     { "vpmaxsd",        { XM, Vex128, EXx } },
8813     { "(bad)",          { XX } },
8814   },
8815
8816   /* VEX_LEN_383E_P_2 */
8817   {
8818     { "vpmaxuw",        { XM, Vex128, EXx } },
8819     { "(bad)",          { XX } },
8820   },
8821
8822   /* VEX_LEN_383F_P_2 */
8823   {
8824     { "vpmaxud",        { XM, Vex128, EXx } },
8825     { "(bad)",          { XX } },
8826   },
8827
8828   /* VEX_LEN_3840_P_2 */
8829   {
8830     { "vpmulld",        { XM, Vex128, EXx } },
8831     { "(bad)",          { XX } },
8832   },
8833
8834   /* VEX_LEN_3841_P_2 */
8835   {
8836     { "vphminposuw",    { XM, EXx } },
8837     { "(bad)",          { XX } },
8838   },
8839
8840   /* VEX_LEN_38DB_P_2 */
8841   {
8842     { "vaesimc",        { XM, EXx } },
8843     { "(bad)",          { XX } },
8844   },
8845
8846   /* VEX_LEN_38DC_P_2 */
8847   {
8848     { "vaesenc",        { XM, Vex128, EXx } },
8849     { "(bad)",          { XX } },
8850   },
8851
8852   /* VEX_LEN_38DD_P_2 */
8853   {
8854     { "vaesenclast",    { XM, Vex128, EXx } },
8855     { "(bad)",          { XX } },
8856   },
8857
8858   /* VEX_LEN_38DE_P_2 */
8859   {
8860     { "vaesdec",        { XM, Vex128, EXx } },
8861     { "(bad)",          { XX } },
8862   },
8863
8864   /* VEX_LEN_38DF_P_2 */
8865   {
8866     { "vaesdeclast",    { XM, Vex128, EXx } },
8867     { "(bad)",          { XX } },
8868   },
8869
8870   /* VEX_LEN_3A06_P_2 */
8871   {
8872     { "(bad)",          { XX } },
8873     { "vperm2f128",     { XM, Vex256, EXx, Ib } },
8874   },
8875
8876   /* VEX_LEN_3A0A_P_2 */
8877   {
8878     { "vroundss",       { XM, Vex128, EXd, Ib } },
8879     { "(bad)",          { XX } },
8880   },
8881
8882   /* VEX_LEN_3A0B_P_2 */
8883   {
8884     { "vroundsd",       { XM, Vex128, EXq, Ib } },
8885     { "(bad)",          { XX } },
8886   },
8887
8888   /* VEX_LEN_3A0E_P_2 */
8889   {
8890     { "vpblendw",       { XM, Vex128, EXx, Ib } },
8891     { "(bad)",          { XX } },
8892   },
8893
8894   /* VEX_LEN_3A0F_P_2 */
8895   {
8896     { "vpalignr",       { XM, Vex128, EXx, Ib } },
8897     { "(bad)",          { XX } },
8898   },
8899
8900   /* VEX_LEN_3A14_P_2 */
8901   {
8902     { "vpextrb",        { Edqb, XM, Ib } },
8903     { "(bad)",          { XX } },
8904   },
8905
8906   /* VEX_LEN_3A15_P_2 */
8907   {
8908     { "vpextrw",        { Edqw, XM, Ib } },
8909     { "(bad)",          { XX } },
8910   },
8911
8912   /* VEX_LEN_3A16_P_2  */
8913   {
8914     { "vpextrK",        { Edq, XM, Ib } },
8915     { "(bad)",          { XX } },
8916   },
8917
8918   /* VEX_LEN_3A17_P_2 */
8919   {
8920     { "vextractps",     { Edqd, XM, Ib } },
8921     { "(bad)",          { XX } },
8922   },
8923
8924   /* VEX_LEN_3A18_P_2 */
8925   {
8926     { "(bad)",          { XX } },
8927     { "vinsertf128",    { XM, Vex256, EXxmm, Ib } },
8928   },
8929
8930   /* VEX_LEN_3A19_P_2 */
8931   {
8932     { "(bad)",          { XX } },
8933     { "vextractf128",   { EXxmm, XM, Ib } },
8934   },
8935
8936   /* VEX_LEN_3A20_P_2 */
8937   {
8938     { "vpinsrb",        { XM, Vex128, Edqb, Ib } },
8939     { "(bad)",          { XX } },
8940   },
8941
8942   /* VEX_LEN_3A21_P_2 */
8943   {
8944     { "vinsertps",      { XM, Vex128, EXd, Ib } },
8945     { "(bad)",          { XX } },
8946   },
8947
8948   /* VEX_LEN_3A22_P_2 */
8949   {
8950     { "vpinsrK",        { XM, Vex128, Edq, Ib } },
8951     { "(bad)",          { XX } },
8952   },
8953
8954   /* VEX_LEN_3A41_P_2 */
8955   {
8956     { "vdppd",          { XM, Vex128, EXx, Ib } },
8957     { "(bad)",          { XX } },
8958   },
8959
8960   /* VEX_LEN_3A42_P_2 */
8961   {
8962     { "vmpsadbw",       { XM, Vex128, EXx, Ib } },
8963     { "(bad)",          { XX } },
8964   },
8965
8966   /* VEX_LEN_3A44_P_2 */
8967   {
8968     { "vpclmulqdq",     { XM, Vex128, EXx, PCLMUL } },
8969     { "(bad)",          { XX } },
8970   },
8971
8972   /* VEX_LEN_3A4C_P_2 */
8973   {
8974     { "vpblendvb",      { XM, Vex128, EXx, XMVexI4 } },
8975     { "(bad)",          { XX } },
8976   },
8977
8978   /* VEX_LEN_3A60_P_2 */
8979   {
8980     { "vpcmpestrm",     { XM, EXx, Ib } },
8981     { "(bad)",          { XX } },
8982   },
8983
8984   /* VEX_LEN_3A61_P_2 */
8985   {
8986     { "vpcmpestri",     { XM, EXx, Ib } },
8987     { "(bad)",          { XX } },
8988   },
8989
8990   /* VEX_LEN_3A62_P_2 */
8991   {
8992     { "vpcmpistrm",     { XM, EXx, Ib } },
8993     { "(bad)",          { XX } },
8994   },
8995
8996   /* VEX_LEN_3A63_P_2 */
8997   {
8998     { "vpcmpistri",     { XM, EXx, Ib } },
8999     { "(bad)",          { XX } },
9000   },
9001
9002   /* VEX_LEN_3A6A_P_2 */
9003   {
9004     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9005     { "(bad)",          { XX } },
9006   },
9007
9008   /* VEX_LEN_3A6B_P_2 */
9009   {
9010     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9011     { "(bad)",          { XX } },
9012   },
9013
9014   /* VEX_LEN_3A6E_P_2 */
9015   {
9016     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9017     { "(bad)",          { XX } },
9018   },
9019
9020   /* VEX_LEN_3A6F_P_2 */
9021   {
9022     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9023     { "(bad)",          { XX } },
9024   },
9025
9026   /* VEX_LEN_3A7A_P_2 */
9027   {
9028     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9029     { "(bad)",          { XX } },
9030   },
9031
9032   /* VEX_LEN_3A7B_P_2 */
9033   {
9034     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9035     { "(bad)",          { XX } },
9036   },
9037
9038   /* VEX_LEN_3A7E_P_2 */
9039   {
9040     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9041     { "(bad)",          { XX } },
9042   },
9043
9044   /* VEX_LEN_3A7F_P_2 */
9045   {
9046     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9047     { "(bad)",          { XX } },
9048   },
9049
9050   /* VEX_LEN_3ADF_P_2 */
9051   {
9052     { "vaeskeygenassist", { XM, EXx, Ib } },
9053     { "(bad)",          { XX } },
9054   },
9055 };
9056
9057 static const struct dis386 mod_table[][2] = {
9058   {
9059     /* MOD_8D */
9060     { "leaS",           { Gv, M } },
9061     { "(bad)",          { XX } },
9062   },
9063   {
9064     /* MOD_0F01_REG_0 */
9065     { X86_64_TABLE (X86_64_0F01_REG_0) },
9066     { RM_TABLE (RM_0F01_REG_0) },
9067   },
9068   {
9069     /* MOD_0F01_REG_1 */
9070     { X86_64_TABLE (X86_64_0F01_REG_1) },
9071     { RM_TABLE (RM_0F01_REG_1) },
9072   },
9073   {
9074     /* MOD_0F01_REG_2 */
9075     { X86_64_TABLE (X86_64_0F01_REG_2) },
9076     { RM_TABLE (RM_0F01_REG_2) },
9077   },
9078   {
9079     /* MOD_0F01_REG_3 */
9080     { X86_64_TABLE (X86_64_0F01_REG_3) },
9081     { RM_TABLE (RM_0F01_REG_3) },
9082   },
9083   {
9084     /* MOD_0F01_REG_7 */
9085     { "invlpg",         { Mb } },
9086     { RM_TABLE (RM_0F01_REG_7) },
9087   },
9088   {
9089     /* MOD_0F12_PREFIX_0 */
9090     { "movlps",         { XM, EXq } },
9091     { "movhlps",        { XM, EXq } },
9092   },
9093   {
9094     /* MOD_0F13 */
9095     { "movlpX",         { EXq, XM } },
9096     { "(bad)",          { XX } },
9097   },
9098   {
9099     /* MOD_0F16_PREFIX_0 */
9100     { "movhps",         { XM, EXq } },
9101     { "movlhps",        { XM, EXq } },
9102   },
9103   {
9104     /* MOD_0F17 */
9105     { "movhpX",         { EXq, XM } },
9106     { "(bad)",          { XX } },
9107   },
9108   {
9109     /* MOD_0F18_REG_0 */
9110     { "prefetchnta",    { Mb } },
9111     { "(bad)",          { XX } },
9112   },
9113   {
9114     /* MOD_0F18_REG_1 */
9115     { "prefetcht0",     { Mb } },
9116     { "(bad)",          { XX } },
9117   },
9118   {
9119     /* MOD_0F18_REG_2 */
9120     { "prefetcht1",     { Mb } },
9121     { "(bad)",          { XX } },
9122   },
9123   {
9124     /* MOD_0F18_REG_3 */
9125     { "prefetcht2",     { Mb } },
9126     { "(bad)",          { XX } },
9127   },
9128   {
9129     /* MOD_0F20 */
9130     { "(bad)",          { XX } },
9131     { "movZ",           { Rm, Cm } },
9132   },
9133   {
9134     /* MOD_0F21 */
9135     { "(bad)",          { XX } },
9136     { "movZ",           { Rm, Dm } },
9137   },
9138   {
9139     /* MOD_0F22 */
9140     { "(bad)",          { XX } },
9141     { "movZ",           { Cm, Rm } },
9142   },
9143   {
9144     /* MOD_0F23 */
9145     { "(bad)",          { XX } },
9146     { "movZ",           { Dm, Rm } },
9147   },
9148   {
9149     /* MOD_0F24 */
9150     { "(bad)",          { XX } },
9151     { "movL",           { Rd, Td } },
9152   },
9153   {
9154     /* MOD_0F26 */
9155     { "(bad)",          { XX } },
9156     { "movL",           { Td, Rd } },
9157   },
9158   {
9159     /* MOD_0F2B_PREFIX_0 */
9160     {"movntps",         { Mx, XM } },
9161     { "(bad)",          { XX } },
9162   },
9163   {
9164     /* MOD_0F2B_PREFIX_1 */
9165     {"movntss",         { Md, XM } },
9166     { "(bad)",          { XX } },
9167   },
9168   {
9169     /* MOD_0F2B_PREFIX_2 */
9170     {"movntpd",         { Mx, XM } },
9171     { "(bad)",          { XX } },
9172   },
9173   {
9174     /* MOD_0F2B_PREFIX_3 */
9175     {"movntsd",         { Mq, XM } },
9176     { "(bad)",          { XX } },
9177   },
9178   {
9179     /* MOD_0F51 */
9180     { "(bad)",          { XX } },
9181     { "movmskpX",       { Gdq, XS } },
9182   },
9183   {
9184     /* MOD_0F71_REG_2 */
9185     { "(bad)",          { XX } },
9186     { "psrlw",          { MS, Ib } },
9187   },
9188   {
9189     /* MOD_0F71_REG_4 */
9190     { "(bad)",          { XX } },
9191     { "psraw",          { MS, Ib } },
9192   },
9193   {
9194     /* MOD_0F71_REG_6 */
9195     { "(bad)",          { XX } },
9196     { "psllw",          { MS, Ib } },
9197   },
9198   {
9199     /* MOD_0F72_REG_2 */
9200     { "(bad)",          { XX } },
9201     { "psrld",          { MS, Ib } },
9202   },
9203   {
9204     /* MOD_0F72_REG_4 */
9205     { "(bad)",          { XX } },
9206     { "psrad",          { MS, Ib } },
9207   },
9208   {
9209     /* MOD_0F72_REG_6 */
9210     { "(bad)",          { XX } },
9211     { "pslld",          { MS, Ib } },
9212   },
9213   {
9214     /* MOD_0F73_REG_2 */
9215     { "(bad)",          { XX } },
9216     { "psrlq",          { MS, Ib } },
9217   },
9218   {
9219     /* MOD_0F73_REG_3 */
9220     { "(bad)",          { XX } },
9221     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
9222   },
9223   {
9224     /* MOD_0F73_REG_6 */
9225     { "(bad)",          { XX } },
9226     { "psllq",          { MS, Ib } },
9227   },
9228   {
9229     /* MOD_0F73_REG_7 */
9230     { "(bad)",          { XX } },
9231     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
9232   },
9233   {
9234     /* MOD_0FAE_REG_0 */
9235     { "fxsave",         { M } },
9236     { "(bad)",          { XX } },
9237   },
9238   {
9239     /* MOD_0FAE_REG_1 */
9240     { "fxrstor",        { M } },
9241     { "(bad)",          { XX } },
9242   },
9243   {
9244     /* MOD_0FAE_REG_2 */
9245     { "ldmxcsr",        { Md } },
9246     { "(bad)",          { XX } },
9247   },
9248   {
9249     /* MOD_0FAE_REG_3 */
9250     { "stmxcsr",        { Md } },
9251     { "(bad)",          { XX } },
9252   },
9253   {
9254     /* MOD_0FAE_REG_4 */
9255     { "xsave",          { M } },
9256     { "(bad)",          { XX } },
9257   },
9258   {
9259     /* MOD_0FAE_REG_5 */
9260     { "xrstor",         { M } },
9261     { RM_TABLE (RM_0FAE_REG_5) },
9262   },
9263   {
9264     /* MOD_0FAE_REG_6 */
9265     { "xsaveopt",       { M } },
9266     { RM_TABLE (RM_0FAE_REG_6) },
9267   },
9268   {
9269     /* MOD_0FAE_REG_7 */
9270     { "clflush",        { Mb } },
9271     { RM_TABLE (RM_0FAE_REG_7) },
9272   },
9273   {
9274     /* MOD_0FB2 */
9275     { "lssS",           { Gv, Mp } },
9276     { "(bad)",          { XX } },
9277   },
9278   {
9279     /* MOD_0FB4 */
9280     { "lfsS",           { Gv, Mp } },
9281     { "(bad)",          { XX } },
9282   },
9283   {
9284     /* MOD_0FB5 */
9285     { "lgsS",           { Gv, Mp } },
9286     { "(bad)",          { XX } },
9287   },
9288   {
9289     /* MOD_0FC7_REG_6 */
9290     { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
9291     { "(bad)",          { XX } },
9292   },
9293   {
9294     /* MOD_0FC7_REG_7 */
9295     { "vmptrst",        { Mq } },
9296     { "(bad)",          { XX } },
9297   },
9298   {
9299     /* MOD_0FD7 */
9300     { "(bad)",          { XX } },
9301     { "pmovmskb",       { Gdq, MS } },
9302   },
9303   {
9304     /* MOD_0FE7_PREFIX_2 */
9305     { "movntdq",        { Mx, XM } },
9306     { "(bad)",          { XX } },
9307   },
9308   {
9309     /* MOD_0FF0_PREFIX_3 */
9310     { "lddqu",          { XM, M } },
9311     { "(bad)",          { XX } },
9312   },
9313   {
9314     /* MOD_0F382A_PREFIX_2 */
9315     { "movntdqa",       { XM, Mx } },
9316     { "(bad)",          { XX } },
9317   },
9318   {
9319     /* MOD_62_32BIT */
9320     { "bound{S|}",      { Gv, Ma } },
9321     { "(bad)",          { XX } },
9322   },
9323   {
9324     /* MOD_C4_32BIT */
9325     { "lesS",           { Gv, Mp } },
9326     { VEX_C4_TABLE (VEX_0F) },
9327   },
9328   {
9329     /* MOD_C5_32BIT */
9330     { "ldsS",           { Gv, Mp } },
9331     { VEX_C5_TABLE (VEX_0F) },
9332   },
9333   {
9334     /* MOD_VEX_12_PREFIX_0 */
9335     { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_0) },
9336     { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_1) },
9337   },
9338   {
9339     /* MOD_VEX_13 */
9340     { VEX_LEN_TABLE (VEX_LEN_13_M_0) },
9341     { "(bad)",          { XX } },
9342   },
9343   {
9344     /* MOD_VEX_16_PREFIX_0 */
9345     { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_0) },
9346     { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_1) },
9347   },
9348   {
9349     /* MOD_VEX_17 */
9350     { VEX_LEN_TABLE (VEX_LEN_17_M_0) },
9351     { "(bad)",          { XX } },
9352   },
9353   {
9354     /* MOD_VEX_2B */
9355     { "vmovntpX",       { Mx, XM } },
9356     { "(bad)",          { XX } },
9357   },
9358   {
9359     /* MOD_VEX_51 */
9360     { "(bad)",          { XX } },
9361     { "vmovmskpX",      { Gdq, XS } },
9362   },
9363   {
9364     /* MOD_VEX_71_REG_2 */
9365     { "(bad)",          { XX } },
9366     { PREFIX_TABLE (PREFIX_VEX_71_REG_2) },
9367   },
9368   {
9369     /* MOD_VEX_71_REG_4 */
9370     { "(bad)",          { XX } },
9371     { PREFIX_TABLE (PREFIX_VEX_71_REG_4) },
9372   },
9373   {
9374     /* MOD_VEX_71_REG_6 */
9375     { "(bad)",          { XX } },
9376     { PREFIX_TABLE (PREFIX_VEX_71_REG_6) },
9377   },
9378   {
9379     /* MOD_VEX_72_REG_2 */
9380     { "(bad)",          { XX } },
9381     { PREFIX_TABLE (PREFIX_VEX_72_REG_2) },
9382   },
9383   {
9384     /* MOD_VEX_72_REG_4 */
9385     { "(bad)",          { XX } },
9386     { PREFIX_TABLE (PREFIX_VEX_72_REG_4) },
9387   },
9388   {
9389     /* MOD_VEX_72_REG_6 */
9390     { "(bad)",          { XX } },
9391     { PREFIX_TABLE (PREFIX_VEX_72_REG_6) },
9392   },
9393   {
9394     /* MOD_VEX_73_REG_2 */
9395     { "(bad)",          { XX } },
9396     { PREFIX_TABLE (PREFIX_VEX_73_REG_2) },
9397   },
9398   {
9399     /* MOD_VEX_73_REG_3 */
9400     { "(bad)",          { XX } },
9401     { PREFIX_TABLE (PREFIX_VEX_73_REG_3) },
9402   },
9403   {
9404     /* MOD_VEX_73_REG_6 */
9405     { "(bad)",          { XX } },
9406     { PREFIX_TABLE (PREFIX_VEX_73_REG_6) },
9407   },
9408   {
9409     /* MOD_VEX_73_REG_7 */
9410     { "(bad)",          { XX } },
9411     { PREFIX_TABLE (PREFIX_VEX_73_REG_7) },
9412   },
9413   {
9414     /* MOD_VEX_AE_REG_2 */
9415     { VEX_LEN_TABLE (VEX_LEN_AE_R_2_M_0) },
9416     { "(bad)",          { XX } },
9417   },
9418   {
9419     /* MOD_VEX_AE_REG_3 */
9420     { VEX_LEN_TABLE (VEX_LEN_AE_R_3_M_0) },
9421     { "(bad)",          { XX } },
9422   },
9423   {
9424     /* MOD_VEX_D7_PREFIX_2 */
9425     { "(bad)",          { XX } },
9426     { VEX_LEN_TABLE (VEX_LEN_D7_P_2_M_1) },
9427   },
9428   {
9429     /* MOD_VEX_E7_PREFIX_2 */
9430     { "vmovntdq",       { Mx, XM } },
9431     { "(bad)",          { XX } },
9432   },
9433   {
9434     /* MOD_VEX_F0_PREFIX_3 */
9435     { "vlddqu",         { XM, M } },
9436     { "(bad)",          { XX } },
9437   },
9438   {
9439     /* MOD_VEX_3818_PREFIX_2 */
9440     { "vbroadcastss",   { XM, Md } },
9441     { "(bad)",          { XX } },
9442   },
9443   {
9444     /* MOD_VEX_3819_PREFIX_2 */
9445     { VEX_LEN_TABLE (VEX_LEN_3819_P_2_M_0) },
9446     { "(bad)",          { XX } },
9447   },
9448   {
9449     /* MOD_VEX_381A_PREFIX_2 */
9450     { VEX_LEN_TABLE (VEX_LEN_381A_P_2_M_0) },
9451     { "(bad)",          { XX } },
9452   },
9453   {
9454     /* MOD_VEX_382A_PREFIX_2 */
9455     { VEX_LEN_TABLE (VEX_LEN_382A_P_2_M_0) },
9456     { "(bad)",          { XX } },
9457   },
9458   {
9459     /* MOD_VEX_382C_PREFIX_2 */
9460     { "vmaskmovps",     { XM, Vex, Mx } },
9461     { "(bad)",          { XX } },
9462   },
9463   {
9464     /* MOD_VEX_382D_PREFIX_2 */
9465     { "vmaskmovpd",     { XM, Vex, Mx } },
9466     { "(bad)",          { XX } },
9467   },
9468   {
9469     /* MOD_VEX_382E_PREFIX_2 */
9470     { "vmaskmovps",     { Mx, Vex, XM } },
9471     { "(bad)",          { XX } },
9472   },
9473   {
9474     /* MOD_VEX_382F_PREFIX_2 */
9475     { "vmaskmovpd",     { Mx, Vex, XM } },
9476     { "(bad)",          { XX } },
9477   },
9478 };
9479
9480 static const struct dis386 rm_table[][8] = {
9481   {
9482     /* RM_0F01_REG_0 */
9483     { "(bad)",          { XX } },
9484     { "vmcall",         { Skip_MODRM } },
9485     { "vmlaunch",       { Skip_MODRM } },
9486     { "vmresume",       { Skip_MODRM } },
9487     { "vmxoff",         { Skip_MODRM } },
9488     { "(bad)",          { XX } },
9489     { "(bad)",          { XX } },
9490     { "(bad)",          { XX } },
9491   },
9492   {
9493     /* RM_0F01_REG_1 */
9494     { "monitor",        { { OP_Monitor, 0 } } },
9495     { "mwait",          { { OP_Mwait, 0 } } },
9496     { "(bad)",          { XX } },
9497     { "(bad)",          { XX } },
9498     { "(bad)",          { XX } },
9499     { "(bad)",          { XX } },
9500     { "(bad)",          { XX } },
9501     { "(bad)",          { XX } },
9502   },
9503   {
9504     /* RM_0F01_REG_2 */
9505     { "xgetbv",         { Skip_MODRM } },
9506     { "xsetbv",         { Skip_MODRM } },
9507     { "(bad)",          { XX } },
9508     { "(bad)",          { XX } },
9509     { "(bad)",          { XX } },
9510     { "(bad)",          { XX } },
9511     { "(bad)",          { XX } },
9512     { "(bad)",          { XX } },
9513   },
9514   {
9515     /* RM_0F01_REG_3 */
9516     { "vmrun",          { Skip_MODRM } },
9517     { "vmmcall",        { Skip_MODRM } },
9518     { "vmload",         { Skip_MODRM } },
9519     { "vmsave",         { Skip_MODRM } },
9520     { "stgi",           { Skip_MODRM } },
9521     { "clgi",           { Skip_MODRM } },
9522     { "skinit",         { Skip_MODRM } },
9523     { "invlpga",        { Skip_MODRM } },
9524   },
9525   {
9526     /* RM_0F01_REG_7 */
9527     { "swapgs",         { Skip_MODRM } },
9528     { "rdtscp",         { Skip_MODRM } },
9529     { "(bad)",          { XX } },
9530     { "(bad)",          { XX } },
9531     { "(bad)",          { XX } },
9532     { "(bad)",          { XX } },
9533     { "(bad)",          { XX } },
9534     { "(bad)",          { XX } },
9535   },
9536   {
9537     /* RM_0FAE_REG_5 */
9538     { "lfence",         { Skip_MODRM } },
9539     { "(bad)",          { XX } },
9540     { "(bad)",          { XX } },
9541     { "(bad)",          { XX } },
9542     { "(bad)",          { XX } },
9543     { "(bad)",          { XX } },
9544     { "(bad)",          { XX } },
9545     { "(bad)",          { XX } },
9546   },
9547   {
9548     /* RM_0FAE_REG_6 */
9549     { "mfence",         { Skip_MODRM } },
9550     { "(bad)",          { XX } },
9551     { "(bad)",          { XX } },
9552     { "(bad)",          { XX } },
9553     { "(bad)",          { XX } },
9554     { "(bad)",          { XX } },
9555     { "(bad)",          { XX } },
9556     { "(bad)",          { XX } },
9557   },
9558   {
9559     /* RM_0FAE_REG_7 */
9560     { "sfence",         { Skip_MODRM } },
9561     { "(bad)",          { XX } },
9562     { "(bad)",          { XX } },
9563     { "(bad)",          { XX } },
9564     { "(bad)",          { XX } },
9565     { "(bad)",          { XX } },
9566     { "(bad)",          { XX } },
9567     { "(bad)",          { XX } },
9568   },
9569 };
9570
9571 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
9572
9573 static void
9574 ckprefix (void)
9575 {
9576   int newrex, i;
9577   rex = 0;
9578   rex_original = 0;
9579   rex_ignored = 0;
9580   prefixes = 0;
9581   used_prefixes = 0;
9582   rex_used = 0;
9583   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
9584     all_prefixes[i] = 0;
9585   i = 0;
9586   while (1)
9587     {
9588       FETCH_DATA (the_info, codep + 1);
9589       newrex = 0;
9590       switch (*codep)
9591         {
9592         /* REX prefixes family.  */
9593         case 0x40:
9594         case 0x41:
9595         case 0x42:
9596         case 0x43:
9597         case 0x44:
9598         case 0x45:
9599         case 0x46:
9600         case 0x47:
9601         case 0x48:
9602         case 0x49:
9603         case 0x4a:
9604         case 0x4b:
9605         case 0x4c:
9606         case 0x4d:
9607         case 0x4e:
9608         case 0x4f:
9609             if (address_mode == mode_64bit)
9610               newrex = *codep;
9611             else
9612               return;
9613           break;
9614         case 0xf3:
9615           if ((prefixes & PREFIX_REPZ) == 0)
9616             {
9617               all_prefixes[i] = &repz_prefix;
9618               i++;
9619             }
9620           prefixes |= PREFIX_REPZ;
9621           break;
9622         case 0xf2:
9623           if ((prefixes & PREFIX_REPNZ) == 0)
9624             {
9625               all_prefixes[i] = &repnz_prefix;
9626               i++;
9627             }
9628           prefixes |= PREFIX_REPNZ;
9629           break;
9630         case 0xf0:
9631           if ((prefixes & PREFIX_LOCK) == 0)
9632             {
9633               all_prefixes[i] = &lock_prefix;
9634               i++;
9635             }
9636           prefixes |= PREFIX_LOCK;
9637           break;
9638         case 0x2e:
9639           prefixes |= PREFIX_CS;
9640           break;
9641         case 0x36:
9642           prefixes |= PREFIX_SS;
9643           break;
9644         case 0x3e:
9645           prefixes |= PREFIX_DS;
9646           break;
9647         case 0x26:
9648           prefixes |= PREFIX_ES;
9649           break;
9650         case 0x64:
9651           prefixes |= PREFIX_FS;
9652           break;
9653         case 0x65:
9654           prefixes |= PREFIX_GS;
9655           break;
9656         case 0x66:
9657           if ((prefixes & PREFIX_DATA) == 0)
9658             {
9659               all_prefixes[i] = &data_prefix;
9660               i++;
9661             }
9662           prefixes |= PREFIX_DATA;
9663           break;
9664         case 0x67:
9665           if ((prefixes & PREFIX_ADDR) == 0)
9666             {
9667               all_prefixes[i] = &addr_prefix;
9668               i++;
9669             }
9670           prefixes |= PREFIX_ADDR;
9671           break;
9672         case FWAIT_OPCODE:
9673           /* fwait is really an instruction.  If there are prefixes
9674              before the fwait, they belong to the fwait, *not* to the
9675              following instruction.  */
9676           if (prefixes || rex)
9677             {
9678               prefixes |= PREFIX_FWAIT;
9679               codep++;
9680               return;
9681             }
9682           prefixes = PREFIX_FWAIT;
9683           break;
9684         default:
9685           return;
9686         }
9687       /* Rex is ignored when followed by another prefix.  */
9688       if (rex)
9689         {
9690           rex_used = rex;
9691           return;
9692         }
9693       rex = newrex;
9694       rex_original = rex;
9695       codep++;
9696     }
9697 }
9698
9699 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
9700    prefix byte.  */
9701
9702 static const char *
9703 prefix_name (int pref, int sizeflag)
9704 {
9705   static const char *rexes [16] =
9706     {
9707       "rex",            /* 0x40 */
9708       "rex.B",          /* 0x41 */
9709       "rex.X",          /* 0x42 */
9710       "rex.XB",         /* 0x43 */
9711       "rex.R",          /* 0x44 */
9712       "rex.RB",         /* 0x45 */
9713       "rex.RX",         /* 0x46 */
9714       "rex.RXB",        /* 0x47 */
9715       "rex.W",          /* 0x48 */
9716       "rex.WB",         /* 0x49 */
9717       "rex.WX",         /* 0x4a */
9718       "rex.WXB",        /* 0x4b */
9719       "rex.WR",         /* 0x4c */
9720       "rex.WRB",        /* 0x4d */
9721       "rex.WRX",        /* 0x4e */
9722       "rex.WRXB",       /* 0x4f */
9723     };
9724
9725   switch (pref)
9726     {
9727     /* REX prefixes family.  */
9728     case 0x40:
9729     case 0x41:
9730     case 0x42:
9731     case 0x43:
9732     case 0x44:
9733     case 0x45:
9734     case 0x46:
9735     case 0x47:
9736     case 0x48:
9737     case 0x49:
9738     case 0x4a:
9739     case 0x4b:
9740     case 0x4c:
9741     case 0x4d:
9742     case 0x4e:
9743     case 0x4f:
9744       return rexes [pref - 0x40];
9745     case 0xf3:
9746       return "repz";
9747     case 0xf2:
9748       return "repnz";
9749     case 0xf0:
9750       return "lock";
9751     case 0x2e:
9752       return "cs";
9753     case 0x36:
9754       return "ss";
9755     case 0x3e:
9756       return "ds";
9757     case 0x26:
9758       return "es";
9759     case 0x64:
9760       return "fs";
9761     case 0x65:
9762       return "gs";
9763     case 0x66:
9764       return (sizeflag & DFLAG) ? "data16" : "data32";
9765     case 0x67:
9766       if (address_mode == mode_64bit)
9767         return (sizeflag & AFLAG) ? "addr32" : "addr64";
9768       else
9769         return (sizeflag & AFLAG) ? "addr16" : "addr32";
9770     case FWAIT_OPCODE:
9771       return "fwait";
9772     default:
9773       return NULL;
9774     }
9775 }
9776
9777 static char op_out[MAX_OPERANDS][100];
9778 static int op_ad, op_index[MAX_OPERANDS];
9779 static int two_source_ops;
9780 static bfd_vma op_address[MAX_OPERANDS];
9781 static bfd_vma op_riprel[MAX_OPERANDS];
9782 static bfd_vma start_pc;
9783
9784 /*
9785  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
9786  *   (see topic "Redundant prefixes" in the "Differences from 8086"
9787  *   section of the "Virtual 8086 Mode" chapter.)
9788  * 'pc' should be the address of this instruction, it will
9789  *   be used to print the target address if this is a relative jump or call
9790  * The function returns the length of this instruction in bytes.
9791  */
9792
9793 static char intel_syntax;
9794 static char intel_mnemonic = !SYSV386_COMPAT;
9795 static char open_char;
9796 static char close_char;
9797 static char separator_char;
9798 static char scale_char;
9799
9800 /* Here for backwards compatibility.  When gdb stops using
9801    print_insn_i386_att and print_insn_i386_intel these functions can
9802    disappear, and print_insn_i386 be merged into print_insn.  */
9803 int
9804 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
9805 {
9806   intel_syntax = 0;
9807
9808   return print_insn (pc, info);
9809 }
9810
9811 int
9812 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
9813 {
9814   intel_syntax = 1;
9815
9816   return print_insn (pc, info);
9817 }
9818
9819 int
9820 print_insn_i386 (bfd_vma pc, disassemble_info *info)
9821 {
9822   intel_syntax = -1;
9823
9824   return print_insn (pc, info);
9825 }
9826
9827 void
9828 print_i386_disassembler_options (FILE *stream)
9829 {
9830   fprintf (stream, _("\n\
9831 The following i386/x86-64 specific disassembler options are supported for use\n\
9832 with the -M switch (multiple options should be separated by commas):\n"));
9833
9834   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
9835   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
9836   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
9837   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
9838   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
9839   fprintf (stream, _("  att-mnemonic\n"
9840                      "              Display instruction in AT&T mnemonic\n"));
9841   fprintf (stream, _("  intel-mnemonic\n"
9842                      "              Display instruction in Intel mnemonic\n"));
9843   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
9844   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
9845   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
9846   fprintf (stream, _("  data32      Assume 32bit data size\n"));
9847   fprintf (stream, _("  data16      Assume 16bit data size\n"));
9848   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
9849 }
9850
9851 /* Get a pointer to struct dis386 with a valid name.  */
9852
9853 static const struct dis386 *
9854 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
9855 {
9856   int index, vex_table_index;
9857
9858   if (dp->name != NULL)
9859     return dp;
9860
9861   switch (dp->op[0].bytemode)
9862     {
9863     case USE_REG_TABLE:
9864       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
9865       break;
9866
9867     case USE_MOD_TABLE:
9868       index = modrm.mod == 0x3 ? 1 : 0;
9869       dp = &mod_table[dp->op[1].bytemode][index];
9870       break;
9871
9872     case USE_RM_TABLE:
9873       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
9874       break;
9875
9876     case USE_PREFIX_TABLE:
9877       if (need_vex)
9878         {
9879           /* The prefix in VEX is implicit.  */
9880           switch (vex.prefix)
9881             {
9882             case 0:
9883               index = 0;
9884               break;
9885             case REPE_PREFIX_OPCODE:
9886               index = 1;
9887               break;
9888             case DATA_PREFIX_OPCODE:
9889               index = 2;
9890               break;
9891             case REPNE_PREFIX_OPCODE:
9892               index = 3;
9893               break;
9894             default:
9895               abort ();
9896               break;
9897             }
9898         }
9899       else
9900         {
9901           index = 0;
9902           used_prefixes |= (prefixes & PREFIX_REPZ);
9903           if (prefixes & PREFIX_REPZ)
9904             {
9905               index = 1;
9906               repz_prefix = NULL;
9907             }
9908           else
9909             {
9910               /* We should check PREFIX_REPNZ and PREFIX_REPZ before
9911                  PREFIX_DATA.  */
9912               used_prefixes |= (prefixes & PREFIX_REPNZ);
9913               if (prefixes & PREFIX_REPNZ)
9914                 {
9915                   index = 3;
9916                   repnz_prefix = NULL;
9917                 }
9918               else
9919                 {
9920                   used_prefixes |= (prefixes & PREFIX_DATA);
9921                   if (prefixes & PREFIX_DATA)
9922                     {
9923                       index = 2;
9924                       data_prefix = NULL;
9925                     }
9926                 }
9927             }
9928         }
9929       dp = &prefix_table[dp->op[1].bytemode][index];
9930       break;
9931
9932     case USE_X86_64_TABLE:
9933       index = address_mode == mode_64bit ? 1 : 0;
9934       dp = &x86_64_table[dp->op[1].bytemode][index];
9935       break;
9936
9937     case USE_3BYTE_TABLE:
9938       FETCH_DATA (info, codep + 2);
9939       index = *codep++;
9940       dp = &three_byte_table[dp->op[1].bytemode][index];
9941       modrm.mod = (*codep >> 6) & 3;
9942       modrm.reg = (*codep >> 3) & 7;
9943       modrm.rm = *codep & 7;
9944       break;
9945
9946     case USE_VEX_LEN_TABLE:
9947       if (!need_vex)
9948         abort ();
9949
9950       switch (vex.length)
9951         {
9952         case 128:
9953           index = 0;
9954           break;
9955         case 256:
9956           index = 1;
9957           break;
9958         default:
9959           abort ();
9960           break;
9961         }
9962
9963       dp = &vex_len_table[dp->op[1].bytemode][index];
9964       break;
9965
9966     case USE_XOP_8F_TABLE:
9967       FETCH_DATA (info, codep + 3);
9968       /* All bits in the REX prefix are ignored.  */
9969       rex_ignored = rex;
9970       rex = ~(*codep >> 5) & 0x7;
9971
9972       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
9973       switch ((*codep & 0x1f))
9974         {
9975         default:
9976           BadOp ();
9977         case 0x9:
9978           vex_table_index = XOP_09;
9979           break;
9980         case 0xa:
9981           vex_table_index = XOP_0A;
9982           break;
9983         }
9984       codep++;
9985       vex.w = *codep & 0x80;
9986       if (vex.w && address_mode == mode_64bit)
9987         rex |= REX_W;
9988
9989       vex.register_specifier = (~(*codep >> 3)) & 0xf;
9990       if (address_mode != mode_64bit
9991           && vex.register_specifier > 0x7)
9992         BadOp ();
9993
9994       vex.length = (*codep & 0x4) ? 256 : 128;
9995       switch ((*codep & 0x3))
9996         {
9997         case 0:
9998           vex.prefix = 0;
9999           break;
10000         case 1:
10001           vex.prefix = DATA_PREFIX_OPCODE;
10002           break;
10003         case 2:
10004           vex.prefix = REPE_PREFIX_OPCODE;
10005           break;
10006         case 3:
10007           vex.prefix = REPNE_PREFIX_OPCODE;
10008           break;
10009         }
10010       need_vex = 1;
10011       need_vex_reg = 1;
10012       codep++;
10013       index = *codep++;
10014       dp = &xop_table[vex_table_index][index];
10015
10016       FETCH_DATA (info, codep + 1);
10017       modrm.mod = (*codep >> 6) & 3;
10018       modrm.reg = (*codep >> 3) & 7;
10019       modrm.rm = *codep & 7;
10020       break;
10021
10022     case USE_VEX_C4_TABLE:
10023       FETCH_DATA (info, codep + 3);
10024       /* All bits in the REX prefix are ignored.  */
10025       rex_ignored = rex;
10026       rex = ~(*codep >> 5) & 0x7;
10027       switch ((*codep & 0x1f))
10028         {
10029         default:
10030           BadOp ();
10031         case 0x1:
10032           vex_table_index = VEX_0F;
10033           break;
10034         case 0x2:
10035           vex_table_index = VEX_0F38;
10036           break;
10037         case 0x3:
10038           vex_table_index = VEX_0F3A;
10039           break;
10040         }
10041       codep++;
10042       vex.w = *codep & 0x80;
10043       if (vex.w && address_mode == mode_64bit)
10044         rex |= REX_W;
10045
10046       vex.register_specifier = (~(*codep >> 3)) & 0xf;
10047       if (address_mode != mode_64bit
10048           && vex.register_specifier > 0x7)
10049         BadOp ();
10050
10051       vex.length = (*codep & 0x4) ? 256 : 128;
10052       switch ((*codep & 0x3))
10053         {
10054         case 0:
10055           vex.prefix = 0;
10056           break;
10057         case 1:
10058           vex.prefix = DATA_PREFIX_OPCODE;
10059           break;
10060         case 2:
10061           vex.prefix = REPE_PREFIX_OPCODE;
10062           break;
10063         case 3:
10064           vex.prefix = REPNE_PREFIX_OPCODE;
10065           break;
10066         }
10067       need_vex = 1;
10068       need_vex_reg = 1;
10069       codep++;
10070       index = *codep++;
10071       dp = &vex_table[vex_table_index][index];
10072       /* There is no MODRM byte for VEX [82|77].  */
10073       if (index != 0x77 && index != 0x82)
10074         {
10075           FETCH_DATA (info, codep + 1);
10076           modrm.mod = (*codep >> 6) & 3;
10077           modrm.reg = (*codep >> 3) & 7;
10078           modrm.rm = *codep & 7;
10079         }
10080       break;
10081
10082     case USE_VEX_C5_TABLE:
10083       FETCH_DATA (info, codep + 2);
10084       /* All bits in the REX prefix are ignored.  */
10085       rex_ignored = rex;
10086       rex = (*codep & 0x80) ? 0 : REX_R;
10087
10088       vex.register_specifier = (~(*codep >> 3)) & 0xf;
10089       if (address_mode != mode_64bit
10090           && vex.register_specifier > 0x7)
10091         BadOp ();
10092
10093       vex.length = (*codep & 0x4) ? 256 : 128;
10094       switch ((*codep & 0x3))
10095         {
10096         case 0:
10097           vex.prefix = 0;
10098           break;
10099         case 1:
10100           vex.prefix = DATA_PREFIX_OPCODE;
10101           break;
10102         case 2:
10103           vex.prefix = REPE_PREFIX_OPCODE;
10104           break;
10105         case 3:
10106           vex.prefix = REPNE_PREFIX_OPCODE;
10107           break;
10108         }
10109       need_vex = 1;
10110       need_vex_reg = 1;
10111       codep++;
10112       index = *codep++;
10113       dp = &vex_table[dp->op[1].bytemode][index];
10114       /* There is no MODRM byte for VEX [82|77].  */
10115       if (index != 0x77 && index != 0x82)
10116         {
10117           FETCH_DATA (info, codep + 1);
10118           modrm.mod = (*codep >> 6) & 3;
10119           modrm.reg = (*codep >> 3) & 7;
10120           modrm.rm = *codep & 7;
10121         }
10122       break;
10123
10124     default:
10125       abort ();
10126     }
10127
10128   if (dp->name != NULL)
10129     return dp;
10130   else
10131     return get_valid_dis386 (dp, info);
10132 }
10133
10134 static int
10135 print_insn (bfd_vma pc, disassemble_info *info)
10136 {
10137   const struct dis386 *dp;
10138   int i;
10139   char *op_txt[MAX_OPERANDS];
10140   int needcomma;
10141   int sizeflag;
10142   const char *p;
10143   struct dis_private priv;
10144   unsigned char op;
10145   char prefix_obuf[32];
10146   char *prefix_obufp;
10147
10148   if (info->mach == bfd_mach_x86_64_intel_syntax
10149       || info->mach == bfd_mach_x86_64
10150       || info->mach == bfd_mach_l1om
10151       || info->mach == bfd_mach_l1om_intel_syntax)
10152     address_mode = mode_64bit;
10153   else
10154     address_mode = mode_32bit;
10155
10156   if (intel_syntax == (char) -1)
10157     intel_syntax = (info->mach == bfd_mach_i386_i386_intel_syntax
10158                     || info->mach == bfd_mach_x86_64_intel_syntax
10159                     || info->mach == bfd_mach_l1om_intel_syntax);
10160
10161   if (info->mach == bfd_mach_i386_i386
10162       || info->mach == bfd_mach_x86_64
10163       || info->mach == bfd_mach_l1om
10164       || info->mach == bfd_mach_i386_i386_intel_syntax
10165       || info->mach == bfd_mach_x86_64_intel_syntax
10166       || info->mach == bfd_mach_l1om_intel_syntax)
10167     priv.orig_sizeflag = AFLAG | DFLAG;
10168   else if (info->mach == bfd_mach_i386_i8086)
10169     priv.orig_sizeflag = 0;
10170   else
10171     abort ();
10172
10173   for (p = info->disassembler_options; p != NULL; )
10174     {
10175       if (CONST_STRNEQ (p, "x86-64"))
10176         {
10177           address_mode = mode_64bit;
10178           priv.orig_sizeflag = AFLAG | DFLAG;
10179         }
10180       else if (CONST_STRNEQ (p, "i386"))
10181         {
10182           address_mode = mode_32bit;
10183           priv.orig_sizeflag = AFLAG | DFLAG;
10184         }
10185       else if (CONST_STRNEQ (p, "i8086"))
10186         {
10187           address_mode = mode_16bit;
10188           priv.orig_sizeflag = 0;
10189         }
10190       else if (CONST_STRNEQ (p, "intel"))
10191         {
10192           intel_syntax = 1;
10193           if (CONST_STRNEQ (p + 5, "-mnemonic"))
10194             intel_mnemonic = 1;
10195         }
10196       else if (CONST_STRNEQ (p, "att"))
10197         {
10198           intel_syntax = 0;
10199           if (CONST_STRNEQ (p + 3, "-mnemonic"))
10200             intel_mnemonic = 0;
10201         }
10202       else if (CONST_STRNEQ (p, "addr"))
10203         {
10204           if (address_mode == mode_64bit)
10205             {
10206               if (p[4] == '3' && p[5] == '2')
10207                 priv.orig_sizeflag &= ~AFLAG;
10208               else if (p[4] == '6' && p[5] == '4')
10209                 priv.orig_sizeflag |= AFLAG;
10210             }
10211           else
10212             {
10213               if (p[4] == '1' && p[5] == '6')
10214                 priv.orig_sizeflag &= ~AFLAG;
10215               else if (p[4] == '3' && p[5] == '2')
10216                 priv.orig_sizeflag |= AFLAG;
10217             }
10218         }
10219       else if (CONST_STRNEQ (p, "data"))
10220         {
10221           if (p[4] == '1' && p[5] == '6')
10222             priv.orig_sizeflag &= ~DFLAG;
10223           else if (p[4] == '3' && p[5] == '2')
10224             priv.orig_sizeflag |= DFLAG;
10225         }
10226       else if (CONST_STRNEQ (p, "suffix"))
10227         priv.orig_sizeflag |= SUFFIX_ALWAYS;
10228
10229       p = strchr (p, ',');
10230       if (p != NULL)
10231         p++;
10232     }
10233
10234   if (intel_syntax)
10235     {
10236       names64 = intel_names64;
10237       names32 = intel_names32;
10238       names16 = intel_names16;
10239       names8 = intel_names8;
10240       names8rex = intel_names8rex;
10241       names_seg = intel_names_seg;
10242       index64 = intel_index64;
10243       index32 = intel_index32;
10244       index16 = intel_index16;
10245       open_char = '[';
10246       close_char = ']';
10247       separator_char = '+';
10248       scale_char = '*';
10249     }
10250   else
10251     {
10252       names64 = att_names64;
10253       names32 = att_names32;
10254       names16 = att_names16;
10255       names8 = att_names8;
10256       names8rex = att_names8rex;
10257       names_seg = att_names_seg;
10258       index64 = att_index64;
10259       index32 = att_index32;
10260       index16 = att_index16;
10261       open_char = '(';
10262       close_char =  ')';
10263       separator_char = ',';
10264       scale_char = ',';
10265     }
10266
10267   /* The output looks better if we put 7 bytes on a line, since that
10268      puts most long word instructions on a single line.  Use 8 bytes
10269      for Intel L1OM.  */
10270   if (info->mach == bfd_mach_l1om
10271       || info->mach == bfd_mach_l1om_intel_syntax)
10272     info->bytes_per_line = 8;
10273   else
10274     info->bytes_per_line = 7;
10275
10276   info->private_data = &priv;
10277   priv.max_fetched = priv.the_buffer;
10278   priv.insn_start = pc;
10279
10280   obuf[0] = 0;
10281   for (i = 0; i < MAX_OPERANDS; ++i)
10282     {
10283       op_out[i][0] = 0;
10284       op_index[i] = -1;
10285     }
10286
10287   the_info = info;
10288   start_pc = pc;
10289   start_codep = priv.the_buffer;
10290   codep = priv.the_buffer;
10291
10292   if (setjmp (priv.bailout) != 0)
10293     {
10294       const char *name;
10295
10296       /* Getting here means we tried for data but didn't get it.  That
10297          means we have an incomplete instruction of some sort.  Just
10298          print the first byte as a prefix or a .byte pseudo-op.  */
10299       if (codep > priv.the_buffer)
10300         {
10301           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
10302           if (name != NULL)
10303             (*info->fprintf_func) (info->stream, "%s", name);
10304           else
10305             {
10306               /* Just print the first byte as a .byte instruction.  */
10307               (*info->fprintf_func) (info->stream, ".byte 0x%x",
10308                                      (unsigned int) priv.the_buffer[0]);
10309             }
10310
10311           return 1;
10312         }
10313
10314       return -1;
10315     }
10316
10317   obufp = obuf;
10318   ckprefix ();
10319
10320   insn_codep = codep;
10321   sizeflag = priv.orig_sizeflag;
10322
10323   FETCH_DATA (info, codep + 1);
10324   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
10325
10326   if (((prefixes & PREFIX_FWAIT)
10327        && ((*codep < 0xd8) || (*codep > 0xdf)))
10328       || (rex && rex_used))
10329     {
10330       const char *name;
10331
10332       /* fwait not followed by floating point instruction, or rex followed
10333          by other prefixes.  Print the first prefix.  */
10334       name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
10335       if (name == NULL)
10336         name = INTERNAL_DISASSEMBLER_ERROR;
10337       (*info->fprintf_func) (info->stream, "%s", name);
10338       return 1;
10339     }
10340
10341   op = 0;
10342
10343   if (*codep == 0x0f)
10344     {
10345       unsigned char threebyte;
10346       FETCH_DATA (info, codep + 2);
10347       threebyte = *++codep;
10348       dp = &dis386_twobyte[threebyte];
10349       need_modrm = twobyte_has_modrm[*codep];
10350       codep++;
10351     }
10352   else
10353     {
10354       dp = &dis386[*codep];
10355       need_modrm = onebyte_has_modrm[*codep];
10356       codep++;
10357     }
10358
10359   if ((prefixes & PREFIX_REPZ))
10360     {
10361       repz_prefix = "repz ";
10362       used_prefixes |= PREFIX_REPZ;
10363     }
10364   else
10365     repz_prefix = NULL;
10366
10367   if ((prefixes & PREFIX_REPNZ))
10368     {
10369       repnz_prefix = "repnz ";
10370       used_prefixes |= PREFIX_REPNZ;
10371     }
10372   else
10373     repnz_prefix = NULL;
10374
10375   if ((prefixes & PREFIX_LOCK))
10376     {
10377       lock_prefix = "lock ";
10378       used_prefixes |= PREFIX_LOCK;
10379     }
10380   else
10381     lock_prefix = NULL;
10382
10383   addr_prefix = NULL;
10384   if (prefixes & PREFIX_ADDR)
10385     {
10386       sizeflag ^= AFLAG;
10387       if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax)
10388         {
10389           if ((sizeflag & AFLAG) || address_mode == mode_64bit)
10390             addr_prefix = "addr32 ";
10391           else
10392             addr_prefix = "addr16 ";
10393           used_prefixes |= PREFIX_ADDR;
10394         }
10395     }
10396
10397   data_prefix = NULL;
10398   if ((prefixes & PREFIX_DATA))
10399     {
10400       sizeflag ^= DFLAG;
10401       if (dp->op[2].bytemode == cond_jump_mode
10402           && dp->op[0].bytemode == v_mode
10403           && !intel_syntax)
10404         {
10405           if (sizeflag & DFLAG)
10406             data_prefix = "data32 ";
10407           else
10408             data_prefix = "data16 ";
10409           used_prefixes |= PREFIX_DATA;
10410         }
10411     }
10412
10413   if (need_modrm)
10414     {
10415       FETCH_DATA (info, codep + 1);
10416       modrm.mod = (*codep >> 6) & 3;
10417       modrm.reg = (*codep >> 3) & 7;
10418       modrm.rm = *codep & 7;
10419     }
10420
10421    need_vex = 0;
10422    need_vex_reg = 0;
10423    vex_w_done = 0;
10424
10425   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
10426     {
10427       dofloat (sizeflag);
10428     }
10429   else
10430     {
10431       dp = get_valid_dis386 (dp, info);
10432       if (dp != NULL && putop (dp->name, sizeflag) == 0)
10433         {
10434           for (i = 0; i < MAX_OPERANDS; ++i)
10435             {
10436               obufp = op_out[i];
10437               op_ad = MAX_OPERANDS - 1 - i;
10438               if (dp->op[i].rtn)
10439                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
10440             }
10441         }
10442     }
10443
10444   /* See if any prefixes were not used.  If so, print the first one
10445      separately.  If we don't do this, we'll wind up printing an
10446      instruction stream which does not precisely correspond to the
10447      bytes we are disassembling.  */
10448   if ((prefixes & ~used_prefixes) != 0)
10449     {
10450       const char *name;
10451
10452       name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
10453       if (name == NULL)
10454         name = INTERNAL_DISASSEMBLER_ERROR;
10455       (*info->fprintf_func) (info->stream, "%s", name);
10456       return 1;
10457     }
10458   if ((rex_original & ~rex_used) || rex_ignored)
10459     {
10460       const char *name;
10461       name = prefix_name (rex_original, priv.orig_sizeflag);
10462       if (name == NULL)
10463         name = INTERNAL_DISASSEMBLER_ERROR;
10464       (*info->fprintf_func) (info->stream, "%s ", name);
10465     }
10466
10467   prefix_obuf[0] = 0;
10468   prefix_obufp = prefix_obuf;
10469   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
10470     if (all_prefixes[i] && *all_prefixes[i])
10471       prefix_obufp = stpcpy (prefix_obufp, *all_prefixes[i]);
10472
10473   if (prefix_obuf[0] != 0)
10474     (*info->fprintf_func) (info->stream, "%s", prefix_obuf);
10475
10476   obufp = mnemonicendp;
10477   for (i = strlen (obuf) + strlen (prefix_obuf); i < 6; i++)
10478     oappend (" ");
10479   oappend (" ");
10480   (*info->fprintf_func) (info->stream, "%s", obuf);
10481
10482   /* The enter and bound instructions are printed with operands in the same
10483      order as the intel book; everything else is printed in reverse order.  */
10484   if (intel_syntax || two_source_ops)
10485     {
10486       bfd_vma riprel;
10487
10488       for (i = 0; i < MAX_OPERANDS; ++i)
10489         op_txt[i] = op_out[i];
10490
10491       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
10492         {
10493           op_ad = op_index[i];
10494           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
10495           op_index[MAX_OPERANDS - 1 - i] = op_ad;
10496           riprel = op_riprel[i];
10497           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
10498           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
10499         }
10500     }
10501   else
10502     {
10503       for (i = 0; i < MAX_OPERANDS; ++i)
10504         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
10505     }
10506
10507   needcomma = 0;
10508   for (i = 0; i < MAX_OPERANDS; ++i)
10509     if (*op_txt[i])
10510       {
10511         if (needcomma)
10512           (*info->fprintf_func) (info->stream, ",");
10513         if (op_index[i] != -1 && !op_riprel[i])
10514           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
10515         else
10516           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
10517         needcomma = 1;
10518       }
10519
10520   for (i = 0; i < MAX_OPERANDS; i++)
10521     if (op_index[i] != -1 && op_riprel[i])
10522       {
10523         (*info->fprintf_func) (info->stream, "        # ");
10524         (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
10525                                                 + op_address[op_index[i]]), info);
10526         break;
10527       }
10528   return codep - priv.the_buffer;
10529 }
10530
10531 static const char *float_mem[] = {
10532   /* d8 */
10533   "fadd{s|}",
10534   "fmul{s|}",
10535   "fcom{s|}",
10536   "fcomp{s|}",
10537   "fsub{s|}",
10538   "fsubr{s|}",
10539   "fdiv{s|}",
10540   "fdivr{s|}",
10541   /* d9 */
10542   "fld{s|}",
10543   "(bad)",
10544   "fst{s|}",
10545   "fstp{s|}",
10546   "fldenvIC",
10547   "fldcw",
10548   "fNstenvIC",
10549   "fNstcw",
10550   /* da */
10551   "fiadd{l|}",
10552   "fimul{l|}",
10553   "ficom{l|}",
10554   "ficomp{l|}",
10555   "fisub{l|}",
10556   "fisubr{l|}",
10557   "fidiv{l|}",
10558   "fidivr{l|}",
10559   /* db */
10560   "fild{l|}",
10561   "fisttp{l|}",
10562   "fist{l|}",
10563   "fistp{l|}",
10564   "(bad)",
10565   "fld{t||t|}",
10566   "(bad)",
10567   "fstp{t||t|}",
10568   /* dc */
10569   "fadd{l|}",
10570   "fmul{l|}",
10571   "fcom{l|}",
10572   "fcomp{l|}",
10573   "fsub{l|}",
10574   "fsubr{l|}",
10575   "fdiv{l|}",
10576   "fdivr{l|}",
10577   /* dd */
10578   "fld{l|}",
10579   "fisttp{ll|}",
10580   "fst{l||}",
10581   "fstp{l|}",
10582   "frstorIC",
10583   "(bad)",
10584   "fNsaveIC",
10585   "fNstsw",
10586   /* de */
10587   "fiadd",
10588   "fimul",
10589   "ficom",
10590   "ficomp",
10591   "fisub",
10592   "fisubr",
10593   "fidiv",
10594   "fidivr",
10595   /* df */
10596   "fild",
10597   "fisttp",
10598   "fist",
10599   "fistp",
10600   "fbld",
10601   "fild{ll|}",
10602   "fbstp",
10603   "fistp{ll|}",
10604 };
10605
10606 static const unsigned char float_mem_mode[] = {
10607   /* d8 */
10608   d_mode,
10609   d_mode,
10610   d_mode,
10611   d_mode,
10612   d_mode,
10613   d_mode,
10614   d_mode,
10615   d_mode,
10616   /* d9 */
10617   d_mode,
10618   0,
10619   d_mode,
10620   d_mode,
10621   0,
10622   w_mode,
10623   0,
10624   w_mode,
10625   /* da */
10626   d_mode,
10627   d_mode,
10628   d_mode,
10629   d_mode,
10630   d_mode,
10631   d_mode,
10632   d_mode,
10633   d_mode,
10634   /* db */
10635   d_mode,
10636   d_mode,
10637   d_mode,
10638   d_mode,
10639   0,
10640   t_mode,
10641   0,
10642   t_mode,
10643   /* dc */
10644   q_mode,
10645   q_mode,
10646   q_mode,
10647   q_mode,
10648   q_mode,
10649   q_mode,
10650   q_mode,
10651   q_mode,
10652   /* dd */
10653   q_mode,
10654   q_mode,
10655   q_mode,
10656   q_mode,
10657   0,
10658   0,
10659   0,
10660   w_mode,
10661   /* de */
10662   w_mode,
10663   w_mode,
10664   w_mode,
10665   w_mode,
10666   w_mode,
10667   w_mode,
10668   w_mode,
10669   w_mode,
10670   /* df */
10671   w_mode,
10672   w_mode,
10673   w_mode,
10674   w_mode,
10675   t_mode,
10676   q_mode,
10677   t_mode,
10678   q_mode
10679 };
10680
10681 #define ST { OP_ST, 0 }
10682 #define STi { OP_STi, 0 }
10683
10684 #define FGRPd9_2 NULL, { { NULL, 0 } }
10685 #define FGRPd9_4 NULL, { { NULL, 1 } }
10686 #define FGRPd9_5 NULL, { { NULL, 2 } }
10687 #define FGRPd9_6 NULL, { { NULL, 3 } }
10688 #define FGRPd9_7 NULL, { { NULL, 4 } }
10689 #define FGRPda_5 NULL, { { NULL, 5 } }
10690 #define FGRPdb_4 NULL, { { NULL, 6 } }
10691 #define FGRPde_3 NULL, { { NULL, 7 } }
10692 #define FGRPdf_4 NULL, { { NULL, 8 } }
10693
10694 static const struct dis386 float_reg[][8] = {
10695   /* d8 */
10696   {
10697     { "fadd",   { ST, STi } },
10698     { "fmul",   { ST, STi } },
10699     { "fcom",   { STi } },
10700     { "fcomp",  { STi } },
10701     { "fsub",   { ST, STi } },
10702     { "fsubr",  { ST, STi } },
10703     { "fdiv",   { ST, STi } },
10704     { "fdivr",  { ST, STi } },
10705   },
10706   /* d9 */
10707   {
10708     { "fld",    { STi } },
10709     { "fxch",   { STi } },
10710     { FGRPd9_2 },
10711     { "(bad)",  { XX } },
10712     { FGRPd9_4 },
10713     { FGRPd9_5 },
10714     { FGRPd9_6 },
10715     { FGRPd9_7 },
10716   },
10717   /* da */
10718   {
10719     { "fcmovb", { ST, STi } },
10720     { "fcmove", { ST, STi } },
10721     { "fcmovbe",{ ST, STi } },
10722     { "fcmovu", { ST, STi } },
10723     { "(bad)",  { XX } },
10724     { FGRPda_5 },
10725     { "(bad)",  { XX } },
10726     { "(bad)",  { XX } },
10727   },
10728   /* db */
10729   {
10730     { "fcmovnb",{ ST, STi } },
10731     { "fcmovne",{ ST, STi } },
10732     { "fcmovnbe",{ ST, STi } },
10733     { "fcmovnu",{ ST, STi } },
10734     { FGRPdb_4 },
10735     { "fucomi", { ST, STi } },
10736     { "fcomi",  { ST, STi } },
10737     { "(bad)",  { XX } },
10738   },
10739   /* dc */
10740   {
10741     { "fadd",   { STi, ST } },
10742     { "fmul",   { STi, ST } },
10743     { "(bad)",  { XX } },
10744     { "(bad)",  { XX } },
10745     { "fsub!M", { STi, ST } },
10746     { "fsubM",  { STi, ST } },
10747     { "fdiv!M", { STi, ST } },
10748     { "fdivM",  { STi, ST } },
10749   },
10750   /* dd */
10751   {
10752     { "ffree",  { STi } },
10753     { "(bad)",  { XX } },
10754     { "fst",    { STi } },
10755     { "fstp",   { STi } },
10756     { "fucom",  { STi } },
10757     { "fucomp", { STi } },
10758     { "(bad)",  { XX } },
10759     { "(bad)",  { XX } },
10760   },
10761   /* de */
10762   {
10763     { "faddp",  { STi, ST } },
10764     { "fmulp",  { STi, ST } },
10765     { "(bad)",  { XX } },
10766     { FGRPde_3 },
10767     { "fsub!Mp", { STi, ST } },
10768     { "fsubMp", { STi, ST } },
10769     { "fdiv!Mp", { STi, ST } },
10770     { "fdivMp", { STi, ST } },
10771   },
10772   /* df */
10773   {
10774     { "ffreep", { STi } },
10775     { "(bad)",  { XX } },
10776     { "(bad)",  { XX } },
10777     { "(bad)",  { XX } },
10778     { FGRPdf_4 },
10779     { "fucomip", { ST, STi } },
10780     { "fcomip", { ST, STi } },
10781     { "(bad)",  { XX } },
10782   },
10783 };
10784
10785 static char *fgrps[][8] = {
10786   /* d9_2  0 */
10787   {
10788     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10789   },
10790
10791   /* d9_4  1 */
10792   {
10793     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
10794   },
10795
10796   /* d9_5  2 */
10797   {
10798     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
10799   },
10800
10801   /* d9_6  3 */
10802   {
10803     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
10804   },
10805
10806   /* d9_7  4 */
10807   {
10808     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
10809   },
10810
10811   /* da_5  5 */
10812   {
10813     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10814   },
10815
10816   /* db_4  6 */
10817   {
10818     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
10819     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
10820   },
10821
10822   /* de_3  7 */
10823   {
10824     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10825   },
10826
10827   /* df_4  8 */
10828   {
10829     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10830   },
10831 };
10832
10833 static void
10834 swap_operand (void)
10835 {
10836   mnemonicendp[0] = '.';
10837   mnemonicendp[1] = 's';
10838   mnemonicendp += 2;
10839 }
10840
10841 static void
10842 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
10843                int sizeflag ATTRIBUTE_UNUSED)
10844 {
10845   /* Skip mod/rm byte.  */
10846   MODRM_CHECK;
10847   codep++;
10848 }
10849
10850 static void
10851 dofloat (int sizeflag)
10852 {
10853   const struct dis386 *dp;
10854   unsigned char floatop;
10855
10856   floatop = codep[-1];
10857
10858   if (modrm.mod != 3)
10859     {
10860       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
10861
10862       putop (float_mem[fp_indx], sizeflag);
10863       obufp = op_out[0];
10864       op_ad = 2;
10865       OP_E (float_mem_mode[fp_indx], sizeflag);
10866       return;
10867     }
10868   /* Skip mod/rm byte.  */
10869   MODRM_CHECK;
10870   codep++;
10871
10872   dp = &float_reg[floatop - 0xd8][modrm.reg];
10873   if (dp->name == NULL)
10874     {
10875       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
10876
10877       /* Instruction fnstsw is only one with strange arg.  */
10878       if (floatop == 0xdf && codep[-1] == 0xe0)
10879         strcpy (op_out[0], names16[0]);
10880     }
10881   else
10882     {
10883       putop (dp->name, sizeflag);
10884
10885       obufp = op_out[0];
10886       op_ad = 2;
10887       if (dp->op[0].rtn)
10888         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
10889
10890       obufp = op_out[1];
10891       op_ad = 1;
10892       if (dp->op[1].rtn)
10893         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
10894     }
10895 }
10896
10897 static void
10898 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
10899 {
10900   oappend ("%st" + intel_syntax);
10901 }
10902
10903 static void
10904 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
10905 {
10906   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
10907   oappend (scratchbuf + intel_syntax);
10908 }
10909
10910 /* Capital letters in template are macros.  */
10911 static int
10912 putop (const char *in_template, int sizeflag)
10913 {
10914   const char *p;
10915   int alt = 0;
10916   int cond = 1;
10917   unsigned int l = 0, len = 1;
10918   char last[4];
10919
10920 #define SAVE_LAST(c)                    \
10921   if (l < len && l < sizeof (last))     \
10922     last[l++] = c;                      \
10923   else                                  \
10924     abort ();
10925
10926   for (p = in_template; *p; p++)
10927     {
10928       switch (*p)
10929         {
10930         default:
10931           *obufp++ = *p;
10932           break;
10933         case '%':
10934           len++;
10935           break;
10936         case '!':
10937           cond = 0;
10938           break;
10939         case '{':
10940           alt = 0;
10941           if (intel_syntax)
10942             {
10943               while (*++p != '|')
10944                 if (*p == '}' || *p == '\0')
10945                   abort ();
10946             }
10947           /* Fall through.  */
10948         case 'I':
10949           alt = 1;
10950           continue;
10951         case '|':
10952           while (*++p != '}')
10953             {
10954               if (*p == '\0')
10955                 abort ();
10956             }
10957           break;
10958         case '}':
10959           break;
10960         case 'A':
10961           if (intel_syntax)
10962             break;
10963           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
10964             *obufp++ = 'b';
10965           break;
10966         case 'B':
10967           if (l == 0 && len == 1)
10968             {
10969 case_B:
10970               if (intel_syntax)
10971                 break;
10972               if (sizeflag & SUFFIX_ALWAYS)
10973                 *obufp++ = 'b';
10974             }
10975           else
10976             {
10977               if (l != 1
10978                   || len != 2
10979                   || last[0] != 'L')
10980                 {
10981                   SAVE_LAST (*p);
10982                   break;
10983                 }
10984
10985               if (address_mode == mode_64bit
10986                   && !(prefixes & PREFIX_ADDR))
10987                 {
10988                   *obufp++ = 'a';
10989                   *obufp++ = 'b';
10990                   *obufp++ = 's';
10991                 }
10992
10993               goto case_B;
10994             }
10995           break;
10996         case 'C':
10997           if (intel_syntax && !alt)
10998             break;
10999           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
11000             {
11001               if (sizeflag & DFLAG)
11002                 *obufp++ = intel_syntax ? 'd' : 'l';
11003               else
11004                 *obufp++ = intel_syntax ? 'w' : 's';
11005               used_prefixes |= (prefixes & PREFIX_DATA);
11006             }
11007           break;
11008         case 'D':
11009           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
11010             break;
11011           USED_REX (REX_W);
11012           if (modrm.mod == 3)
11013             {
11014               if (rex & REX_W)
11015                 *obufp++ = 'q';
11016               else if (sizeflag & DFLAG)
11017                 *obufp++ = intel_syntax ? 'd' : 'l';
11018               else
11019                 *obufp++ = 'w';
11020               used_prefixes |= (prefixes & PREFIX_DATA);
11021             }
11022           else
11023             *obufp++ = 'w';
11024           break;
11025         case 'E':               /* For jcxz/jecxz */
11026           if (address_mode == mode_64bit)
11027             {
11028               if (sizeflag & AFLAG)
11029                 *obufp++ = 'r';
11030               else
11031                 *obufp++ = 'e';
11032             }
11033           else
11034             if (sizeflag & AFLAG)
11035               *obufp++ = 'e';
11036           used_prefixes |= (prefixes & PREFIX_ADDR);
11037           break;
11038         case 'F':
11039           if (intel_syntax)
11040             break;
11041           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
11042             {
11043               if (sizeflag & AFLAG)
11044                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
11045               else
11046                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
11047               used_prefixes |= (prefixes & PREFIX_ADDR);
11048             }
11049           break;
11050         case 'G':
11051           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
11052             break;
11053           if ((rex & REX_W) || (sizeflag & DFLAG))
11054             *obufp++ = 'l';
11055           else
11056             *obufp++ = 'w';
11057           if (!(rex & REX_W))
11058             used_prefixes |= (prefixes & PREFIX_DATA);
11059           break;
11060         case 'H':
11061           if (intel_syntax)
11062             break;
11063           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
11064               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
11065             {
11066               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
11067               *obufp++ = ',';
11068               *obufp++ = 'p';
11069               if (prefixes & PREFIX_DS)
11070                 *obufp++ = 't';
11071               else
11072                 *obufp++ = 'n';
11073             }
11074           break;
11075         case 'J':
11076           if (intel_syntax)
11077             break;
11078           *obufp++ = 'l';
11079           break;
11080         case 'K':
11081           USED_REX (REX_W);
11082           if (rex & REX_W)
11083             *obufp++ = 'q';
11084           else
11085             *obufp++ = 'd';
11086           break;
11087         case 'Z':
11088           if (intel_syntax)
11089             break;
11090           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
11091             {
11092               *obufp++ = 'q';
11093               break;
11094             }
11095           /* Fall through.  */
11096           goto case_L;
11097         case 'L':
11098           if (l != 0 || len != 1)
11099             {
11100               SAVE_LAST (*p);
11101               break;
11102             }
11103 case_L:
11104           if (intel_syntax)
11105             break;
11106           if (sizeflag & SUFFIX_ALWAYS)
11107             *obufp++ = 'l';
11108           break;
11109         case 'M':
11110           if (intel_mnemonic != cond)
11111             *obufp++ = 'r';
11112           break;
11113         case 'N':
11114           if ((prefixes & PREFIX_FWAIT) == 0)
11115             *obufp++ = 'n';
11116           else
11117             used_prefixes |= PREFIX_FWAIT;
11118           break;
11119         case 'O':
11120           USED_REX (REX_W);
11121           if (rex & REX_W)
11122             *obufp++ = 'o';
11123           else if (intel_syntax && (sizeflag & DFLAG))
11124             *obufp++ = 'q';
11125           else
11126             *obufp++ = 'd';
11127           if (!(rex & REX_W))
11128             used_prefixes |= (prefixes & PREFIX_DATA);
11129           break;
11130         case 'T':
11131           if (intel_syntax)
11132             break;
11133           if (address_mode == mode_64bit && (sizeflag & DFLAG))
11134             {
11135               *obufp++ = 'q';
11136               break;
11137             }
11138           /* Fall through.  */
11139         case 'P':
11140           if (intel_syntax)
11141             break;
11142           if ((prefixes & PREFIX_DATA)
11143               || (rex & REX_W)
11144               || (sizeflag & SUFFIX_ALWAYS))
11145             {
11146               USED_REX (REX_W);
11147               if (rex & REX_W)
11148                 *obufp++ = 'q';
11149               else
11150                 {
11151                    if (sizeflag & DFLAG)
11152                       *obufp++ = 'l';
11153                    else
11154                      *obufp++ = 'w';
11155                 }
11156               used_prefixes |= (prefixes & PREFIX_DATA);
11157             }
11158           break;
11159         case 'U':
11160           if (intel_syntax)
11161             break;
11162           if (address_mode == mode_64bit && (sizeflag & DFLAG))
11163             {
11164               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
11165                 *obufp++ = 'q';
11166               break;
11167             }
11168           /* Fall through.  */
11169           goto case_Q;
11170         case 'Q':
11171           if (l == 0 && len == 1)
11172             {
11173 case_Q:
11174               if (intel_syntax && !alt)
11175                 break;
11176               USED_REX (REX_W);
11177               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
11178                 {
11179                   if (rex & REX_W)
11180                     *obufp++ = 'q';
11181                   else
11182                     {
11183                       if (sizeflag & DFLAG)
11184                         *obufp++ = intel_syntax ? 'd' : 'l';
11185                       else
11186                         *obufp++ = 'w';
11187                     }
11188                   used_prefixes |= (prefixes & PREFIX_DATA);
11189                 }
11190             }
11191           else
11192             {
11193               if (l != 1 || len != 2 || last[0] != 'L')
11194                 {
11195                   SAVE_LAST (*p);
11196                   break;
11197                 }
11198               if (intel_syntax
11199                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
11200                 break;
11201               if ((rex & REX_W))
11202                 {
11203                   USED_REX (REX_W);
11204                   *obufp++ = 'q';
11205                 }
11206               else
11207                 *obufp++ = 'l';
11208             }
11209           break;
11210         case 'R':
11211           USED_REX (REX_W);
11212           if (rex & REX_W)
11213             *obufp++ = 'q';
11214           else if (sizeflag & DFLAG)
11215             {
11216               if (intel_syntax)
11217                   *obufp++ = 'd';
11218               else
11219                   *obufp++ = 'l';
11220             }
11221           else
11222             *obufp++ = 'w';
11223           if (intel_syntax && !p[1]
11224               && ((rex & REX_W) || (sizeflag & DFLAG)))
11225             *obufp++ = 'e';
11226           if (!(rex & REX_W))
11227             used_prefixes |= (prefixes & PREFIX_DATA);
11228           break;
11229         case 'V':
11230           if (l == 0 && len == 1)
11231             {
11232               if (intel_syntax)
11233                 break;
11234               if (address_mode == mode_64bit && (sizeflag & DFLAG))
11235                 {
11236                   if (sizeflag & SUFFIX_ALWAYS)
11237                     *obufp++ = 'q';
11238                   break;
11239                 }
11240             }
11241           else
11242             {
11243               if (l != 1
11244                   || len != 2
11245                   || last[0] != 'L')
11246                 {
11247                   SAVE_LAST (*p);
11248                   break;
11249                 }
11250
11251               if (rex & REX_W)
11252                 {
11253                   *obufp++ = 'a';
11254                   *obufp++ = 'b';
11255                   *obufp++ = 's';
11256                 }
11257             }
11258           /* Fall through.  */
11259           goto case_S;
11260         case 'S':
11261           if (l == 0 && len == 1)
11262             {
11263 case_S:
11264               if (intel_syntax)
11265                 break;
11266               if (sizeflag & SUFFIX_ALWAYS)
11267                 {
11268                   if (rex & REX_W)
11269                     *obufp++ = 'q';
11270                   else
11271                     {
11272                       if (sizeflag & DFLAG)
11273                         *obufp++ = 'l';
11274                       else
11275                         *obufp++ = 'w';
11276                       used_prefixes |= (prefixes & PREFIX_DATA);
11277                     }
11278                 }
11279             }
11280           else
11281             {
11282               if (l != 1
11283                   || len != 2
11284                   || last[0] != 'L')
11285                 {
11286                   SAVE_LAST (*p);
11287                   break;
11288                 }
11289
11290               if (address_mode == mode_64bit
11291                   && !(prefixes & PREFIX_ADDR))
11292                 {
11293                   *obufp++ = 'a';
11294                   *obufp++ = 'b';
11295                   *obufp++ = 's';
11296                 }
11297
11298               goto case_S;
11299             }
11300           break;
11301         case 'X':
11302           if (l != 0 || len != 1)
11303             {
11304               SAVE_LAST (*p);
11305               break;
11306             }
11307           if (need_vex && vex.prefix)
11308             {
11309               if (vex.prefix == DATA_PREFIX_OPCODE)
11310                 *obufp++ = 'd';
11311               else
11312                 *obufp++ = 's';
11313             }
11314           else if (prefixes & PREFIX_DATA)
11315             *obufp++ = 'd';
11316           else
11317             *obufp++ = 's';
11318           used_prefixes |= (prefixes & PREFIX_DATA);
11319           break;
11320         case 'Y':
11321           if (l == 0 && len == 1)
11322             {
11323               if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
11324                 break;
11325               if (rex & REX_W)
11326                 {
11327                   USED_REX (REX_W);
11328                   *obufp++ = 'q';
11329                 }
11330               break;
11331             }
11332           else
11333             {
11334               if (l != 1 || len != 2 || last[0] != 'X')
11335                 {
11336                   SAVE_LAST (*p);
11337                   break;
11338                 }
11339               if (!need_vex)
11340                 abort ();
11341               if (intel_syntax
11342                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
11343                 break;
11344               switch (vex.length)
11345                 {
11346                 case 128:
11347                   *obufp++ = 'x';
11348                   break;
11349                 case 256:
11350                   *obufp++ = 'y';
11351                   break;
11352                 default:
11353                   abort ();
11354                 }
11355             }
11356           break;
11357         case 'W':
11358           if (l == 0 && len == 1)
11359             {
11360               /* operand size flag for cwtl, cbtw */
11361               USED_REX (REX_W);
11362               if (rex & REX_W)
11363                 {
11364                   if (intel_syntax)
11365                     *obufp++ = 'd';
11366                   else
11367                     *obufp++ = 'l';
11368                 }
11369               else if (sizeflag & DFLAG)
11370                 *obufp++ = 'w';
11371               else
11372                 *obufp++ = 'b';
11373               if (!(rex & REX_W))
11374                 used_prefixes |= (prefixes & PREFIX_DATA);
11375             }
11376           else
11377             {
11378               if (l != 1 || len != 2 || last[0] != 'X')
11379                 {
11380                   SAVE_LAST (*p);
11381                   break;
11382                 }
11383               if (!need_vex)
11384                 abort ();
11385               *obufp++ = vex.w ? 'd': 's';
11386             }
11387           break;
11388         }
11389       alt = 0;
11390     }
11391   *obufp = 0;
11392   mnemonicendp = obufp;
11393   return 0;
11394 }
11395
11396 static void
11397 oappend (const char *s)
11398 {
11399   obufp = stpcpy (obufp, s);
11400 }
11401
11402 static void
11403 append_seg (void)
11404 {
11405   if (prefixes & PREFIX_CS)
11406     {
11407       used_prefixes |= PREFIX_CS;
11408       oappend ("%cs:" + intel_syntax);
11409     }
11410   if (prefixes & PREFIX_DS)
11411     {
11412       used_prefixes |= PREFIX_DS;
11413       oappend ("%ds:" + intel_syntax);
11414     }
11415   if (prefixes & PREFIX_SS)
11416     {
11417       used_prefixes |= PREFIX_SS;
11418       oappend ("%ss:" + intel_syntax);
11419     }
11420   if (prefixes & PREFIX_ES)
11421     {
11422       used_prefixes |= PREFIX_ES;
11423       oappend ("%es:" + intel_syntax);
11424     }
11425   if (prefixes & PREFIX_FS)
11426     {
11427       used_prefixes |= PREFIX_FS;
11428       oappend ("%fs:" + intel_syntax);
11429     }
11430   if (prefixes & PREFIX_GS)
11431     {
11432       used_prefixes |= PREFIX_GS;
11433       oappend ("%gs:" + intel_syntax);
11434     }
11435 }
11436
11437 static void
11438 OP_indirE (int bytemode, int sizeflag)
11439 {
11440   if (!intel_syntax)
11441     oappend ("*");
11442   OP_E (bytemode, sizeflag);
11443 }
11444
11445 static void
11446 print_operand_value (char *buf, int hex, bfd_vma disp)
11447 {
11448   if (address_mode == mode_64bit)
11449     {
11450       if (hex)
11451         {
11452           char tmp[30];
11453           int i;
11454           buf[0] = '0';
11455           buf[1] = 'x';
11456           sprintf_vma (tmp, disp);
11457           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
11458           strcpy (buf + 2, tmp + i);
11459         }
11460       else
11461         {
11462           bfd_signed_vma v = disp;
11463           char tmp[30];
11464           int i;
11465           if (v < 0)
11466             {
11467               *(buf++) = '-';
11468               v = -disp;
11469               /* Check for possible overflow on 0x8000000000000000.  */
11470               if (v < 0)
11471                 {
11472                   strcpy (buf, "9223372036854775808");
11473                   return;
11474                 }
11475             }
11476           if (!v)
11477             {
11478               strcpy (buf, "0");
11479               return;
11480             }
11481
11482           i = 0;
11483           tmp[29] = 0;
11484           while (v)
11485             {
11486               tmp[28 - i] = (v % 10) + '0';
11487               v /= 10;
11488               i++;
11489             }
11490           strcpy (buf, tmp + 29 - i);
11491         }
11492     }
11493   else
11494     {
11495       if (hex)
11496         sprintf (buf, "0x%x", (unsigned int) disp);
11497       else
11498         sprintf (buf, "%d", (int) disp);
11499     }
11500 }
11501
11502 /* Put DISP in BUF as signed hex number.  */
11503
11504 static void
11505 print_displacement (char *buf, bfd_vma disp)
11506 {
11507   bfd_signed_vma val = disp;
11508   char tmp[30];
11509   int i, j = 0;
11510
11511   if (val < 0)
11512     {
11513       buf[j++] = '-';
11514       val = -disp;
11515
11516       /* Check for possible overflow.  */
11517       if (val < 0)
11518         {
11519           switch (address_mode)
11520             {
11521             case mode_64bit:
11522               strcpy (buf + j, "0x8000000000000000");
11523               break;
11524             case mode_32bit:
11525               strcpy (buf + j, "0x80000000");
11526               break;
11527             case mode_16bit:
11528               strcpy (buf + j, "0x8000");
11529               break;
11530             }
11531           return;
11532         }
11533     }
11534
11535   buf[j++] = '0';
11536   buf[j++] = 'x';
11537
11538   sprintf_vma (tmp, (bfd_vma) val);
11539   for (i = 0; tmp[i] == '0'; i++)
11540     continue;
11541   if (tmp[i] == '\0')
11542     i--;
11543   strcpy (buf + j, tmp + i);
11544 }
11545
11546 static void
11547 intel_operand_size (int bytemode, int sizeflag)
11548 {
11549   switch (bytemode)
11550     {
11551     case b_mode:
11552     case b_swap_mode:
11553     case dqb_mode:
11554       oappend ("BYTE PTR ");
11555       break;
11556     case w_mode:
11557     case dqw_mode:
11558       oappend ("WORD PTR ");
11559       break;
11560     case stack_v_mode:
11561       if (address_mode == mode_64bit && (sizeflag & DFLAG))
11562         {
11563           oappend ("QWORD PTR ");
11564           used_prefixes |= (prefixes & PREFIX_DATA);
11565           break;
11566         }
11567       /* FALLTHRU */
11568     case v_mode:
11569     case v_swap_mode:
11570     case dq_mode:
11571       USED_REX (REX_W);
11572       if (rex & REX_W)
11573         oappend ("QWORD PTR ");
11574       else if ((sizeflag & DFLAG) || bytemode == dq_mode)
11575         oappend ("DWORD PTR ");
11576       else
11577         oappend ("WORD PTR ");
11578       used_prefixes |= (prefixes & PREFIX_DATA);
11579       break;
11580     case z_mode:
11581       if ((rex & REX_W) || (sizeflag & DFLAG))
11582         *obufp++ = 'D';
11583       oappend ("WORD PTR ");
11584       if (!(rex & REX_W))
11585         used_prefixes |= (prefixes & PREFIX_DATA);
11586       break;
11587     case a_mode:
11588       if (sizeflag & DFLAG)
11589         oappend ("QWORD PTR ");
11590       else
11591         oappend ("DWORD PTR ");
11592       used_prefixes |= (prefixes & PREFIX_DATA);
11593       break;
11594     case d_mode:
11595     case d_swap_mode:
11596     case dqd_mode:
11597       oappend ("DWORD PTR ");
11598       break;
11599     case q_mode:
11600     case q_swap_mode:
11601       oappend ("QWORD PTR ");
11602       break;
11603     case m_mode:
11604       if (address_mode == mode_64bit)
11605         oappend ("QWORD PTR ");
11606       else
11607         oappend ("DWORD PTR ");
11608       break;
11609     case f_mode:
11610       if (sizeflag & DFLAG)
11611         oappend ("FWORD PTR ");
11612       else
11613         oappend ("DWORD PTR ");
11614       used_prefixes |= (prefixes & PREFIX_DATA);
11615       break;
11616     case t_mode:
11617       oappend ("TBYTE PTR ");
11618       break;
11619     case x_mode:
11620     case x_swap_mode:
11621       if (need_vex)
11622         {
11623           switch (vex.length)
11624             {
11625             case 128:
11626               oappend ("XMMWORD PTR ");
11627               break;
11628             case 256:
11629               oappend ("YMMWORD PTR ");
11630               break;
11631             default:
11632               abort ();
11633             }
11634         }
11635       else
11636         oappend ("XMMWORD PTR ");
11637       break;
11638     case xmm_mode:
11639       oappend ("XMMWORD PTR ");
11640       break;
11641     case xmmq_mode:
11642       if (!need_vex)
11643         abort ();
11644
11645       switch (vex.length)
11646         {
11647         case 128:
11648           oappend ("QWORD PTR ");
11649           break;
11650         case 256:
11651           oappend ("XMMWORD PTR ");
11652           break;
11653         default:
11654           abort ();
11655         }
11656       break;
11657     case ymmq_mode:
11658       if (!need_vex)
11659         abort ();
11660
11661       switch (vex.length)
11662         {
11663         case 128:
11664           oappend ("QWORD PTR ");
11665           break;
11666         case 256:
11667           oappend ("YMMWORD PTR ");
11668           break;
11669         default:
11670           abort ();
11671         }
11672       break;
11673     case o_mode:
11674       oappend ("OWORD PTR ");
11675       break;
11676     case vex_w_dq_mode:
11677       if (!need_vex)
11678         abort ();
11679
11680       if (vex.w)
11681         oappend ("QWORD PTR ");
11682       else
11683         oappend ("DWORD PTR ");
11684       break;
11685     default:
11686       break;
11687     }
11688 }
11689
11690 static void
11691 OP_E_register (int bytemode, int sizeflag)
11692 {
11693   int reg = modrm.rm;
11694   const char **names;
11695
11696   USED_REX (REX_B);
11697   if ((rex & REX_B))
11698     reg += 8;
11699
11700   if ((sizeflag & SUFFIX_ALWAYS)
11701       && (bytemode == b_swap_mode || bytemode == v_swap_mode))
11702     swap_operand ();
11703
11704   switch (bytemode)
11705     {
11706     case b_mode:
11707     case b_swap_mode:
11708       USED_REX (0);
11709       if (rex)
11710         names = names8rex;
11711       else
11712         names = names8;
11713       break;
11714     case w_mode:
11715       names = names16;
11716       break;
11717     case d_mode:
11718       names = names32;
11719       break;
11720     case q_mode:
11721       names = names64;
11722       break;
11723     case m_mode:
11724       names = address_mode == mode_64bit ? names64 : names32;
11725       break;
11726     case stack_v_mode:
11727       if (address_mode == mode_64bit && (sizeflag & DFLAG))
11728         {
11729           names = names64;
11730           used_prefixes |= (prefixes & PREFIX_DATA);
11731           break;
11732         }
11733       bytemode = v_mode;
11734       /* FALLTHRU */
11735     case v_mode:
11736     case v_swap_mode:
11737     case dq_mode:
11738     case dqb_mode:
11739     case dqd_mode:
11740     case dqw_mode:
11741       USED_REX (REX_W);
11742       if (rex & REX_W)
11743         names = names64;
11744       else if ((sizeflag & DFLAG)
11745                || (bytemode != v_mode
11746                    && bytemode != v_swap_mode))
11747         names = names32;
11748       else
11749         names = names16;
11750       used_prefixes |= (prefixes & PREFIX_DATA);
11751       break;
11752     case 0:
11753       return;
11754     default:
11755       oappend (INTERNAL_DISASSEMBLER_ERROR);
11756       return;
11757     }
11758   oappend (names[reg]);
11759 }
11760
11761 static void
11762 OP_E_memory (int bytemode, int sizeflag)
11763 {
11764   bfd_vma disp = 0;
11765   int add = (rex & REX_B) ? 8 : 0;
11766   int riprel = 0;
11767
11768   USED_REX (REX_B);
11769   if (intel_syntax)
11770     intel_operand_size (bytemode, sizeflag);
11771   append_seg ();
11772
11773   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
11774     {
11775       /* 32/64 bit address mode */
11776       int havedisp;
11777       int havesib;
11778       int havebase;
11779       int haveindex;
11780       int needindex;
11781       int base, rbase;
11782       int index = 0;
11783       int scale = 0;
11784
11785       havesib = 0;
11786       havebase = 1;
11787       haveindex = 0;
11788       base = modrm.rm;
11789
11790       if (base == 4)
11791         {
11792           havesib = 1;
11793           FETCH_DATA (the_info, codep + 1);
11794           index = (*codep >> 3) & 7;
11795           scale = (*codep >> 6) & 3;
11796           base = *codep & 7;
11797           USED_REX (REX_X);
11798           if (rex & REX_X)
11799             index += 8;
11800           haveindex = index != 4;
11801           codep++;
11802         }
11803       rbase = base + add;
11804
11805       switch (modrm.mod)
11806         {
11807         case 0:
11808           if (base == 5)
11809             {
11810               havebase = 0;
11811               if (address_mode == mode_64bit && !havesib)
11812                 riprel = 1;
11813               disp = get32s ();
11814             }
11815           break;
11816         case 1:
11817           FETCH_DATA (the_info, codep + 1);
11818           disp = *codep++;
11819           if ((disp & 0x80) != 0)
11820             disp -= 0x100;
11821           break;
11822         case 2:
11823           disp = get32s ();
11824           break;
11825         }
11826
11827       /* In 32bit mode, we need index register to tell [offset] from
11828          [eiz*1 + offset].  */
11829       needindex = (havesib
11830                    && !havebase
11831                    && !haveindex
11832                    && address_mode == mode_32bit);
11833       havedisp = (havebase
11834                   || needindex
11835                   || (havesib && (haveindex || scale != 0)));
11836
11837       if (!intel_syntax)
11838         if (modrm.mod != 0 || base == 5)
11839           {
11840             if (havedisp || riprel)
11841               print_displacement (scratchbuf, disp);
11842             else
11843               print_operand_value (scratchbuf, 1, disp);
11844             oappend (scratchbuf);
11845             if (riprel)
11846               {
11847                 set_op (disp, 1);
11848                 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
11849               }
11850           }
11851
11852       if (havebase || haveindex || riprel)
11853         used_prefixes |= PREFIX_ADDR;
11854
11855       if (havedisp || (intel_syntax && riprel))
11856         {
11857           *obufp++ = open_char;
11858           if (intel_syntax && riprel)
11859             {
11860               set_op (disp, 1);
11861               oappend (sizeflag & AFLAG ? "rip" : "eip");
11862             }
11863           *obufp = '\0';
11864           if (havebase)
11865             oappend (address_mode == mode_64bit && (sizeflag & AFLAG)
11866                      ? names64[rbase] : names32[rbase]);
11867           if (havesib)
11868             {
11869               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
11870                  print index to tell base + index from base.  */
11871               if (scale != 0
11872                   || needindex
11873                   || haveindex
11874                   || (havebase && base != ESP_REG_NUM))
11875                 {
11876                   if (!intel_syntax || havebase)
11877                     {
11878                       *obufp++ = separator_char;
11879                       *obufp = '\0';
11880                     }
11881                   if (haveindex)
11882                     oappend (address_mode == mode_64bit
11883                              && (sizeflag & AFLAG)
11884                              ? names64[index] : names32[index]);
11885                   else
11886                     oappend (address_mode == mode_64bit
11887                              && (sizeflag & AFLAG)
11888                              ? index64 : index32);
11889
11890                   *obufp++ = scale_char;
11891                   *obufp = '\0';
11892                   sprintf (scratchbuf, "%d", 1 << scale);
11893                   oappend (scratchbuf);
11894                 }
11895             }
11896           if (intel_syntax
11897               && (disp || modrm.mod != 0 || base == 5))
11898             {
11899               if (!havedisp || (bfd_signed_vma) disp >= 0)
11900                 {
11901                   *obufp++ = '+';
11902                   *obufp = '\0';
11903                 }
11904               else if (modrm.mod != 1 && disp != -disp)
11905                 {
11906                   *obufp++ = '-';
11907                   *obufp = '\0';
11908                   disp = - (bfd_signed_vma) disp;
11909                 }
11910
11911               if (havedisp)
11912                 print_displacement (scratchbuf, disp);
11913               else
11914                 print_operand_value (scratchbuf, 1, disp);
11915               oappend (scratchbuf);
11916             }
11917
11918           *obufp++ = close_char;
11919           *obufp = '\0';
11920         }
11921       else if (intel_syntax)
11922         {
11923           if (modrm.mod != 0 || base == 5)
11924             {
11925               if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
11926                               | PREFIX_ES | PREFIX_FS | PREFIX_GS))
11927                 ;
11928               else
11929                 {
11930                   oappend (names_seg[ds_reg - es_reg]);
11931                   oappend (":");
11932                 }
11933               print_operand_value (scratchbuf, 1, disp);
11934               oappend (scratchbuf);
11935             }
11936         }
11937     }
11938   else
11939     { /* 16 bit address mode */
11940       switch (modrm.mod)
11941         {
11942         case 0:
11943           if (modrm.rm == 6)
11944             {
11945               disp = get16 ();
11946               if ((disp & 0x8000) != 0)
11947                 disp -= 0x10000;
11948             }
11949           break;
11950         case 1:
11951           FETCH_DATA (the_info, codep + 1);
11952           disp = *codep++;
11953           if ((disp & 0x80) != 0)
11954             disp -= 0x100;
11955           break;
11956         case 2:
11957           disp = get16 ();
11958           if ((disp & 0x8000) != 0)
11959             disp -= 0x10000;
11960           break;
11961         }
11962
11963       if (!intel_syntax)
11964         if (modrm.mod != 0 || modrm.rm == 6)
11965           {
11966             print_displacement (scratchbuf, disp);
11967             oappend (scratchbuf);
11968           }
11969
11970       if (modrm.mod != 0 || modrm.rm != 6)
11971         {
11972           *obufp++ = open_char;
11973           *obufp = '\0';
11974           oappend (index16[modrm.rm]);
11975           if (intel_syntax
11976               && (disp || modrm.mod != 0 || modrm.rm == 6))
11977             {
11978               if ((bfd_signed_vma) disp >= 0)
11979                 {
11980                   *obufp++ = '+';
11981                   *obufp = '\0';
11982                 }
11983               else if (modrm.mod != 1)
11984                 {
11985                   *obufp++ = '-';
11986                   *obufp = '\0';
11987                   disp = - (bfd_signed_vma) disp;
11988                 }
11989
11990               print_displacement (scratchbuf, disp);
11991               oappend (scratchbuf);
11992             }
11993
11994           *obufp++ = close_char;
11995           *obufp = '\0';
11996         }
11997       else if (intel_syntax)
11998         {
11999           if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
12000                           | PREFIX_ES | PREFIX_FS | PREFIX_GS))
12001             ;
12002           else
12003             {
12004               oappend (names_seg[ds_reg - es_reg]);
12005               oappend (":");
12006             }
12007           print_operand_value (scratchbuf, 1, disp & 0xffff);
12008           oappend (scratchbuf);
12009         }
12010     }
12011 }
12012
12013 static void
12014 OP_E_extended (int bytemode, int sizeflag)
12015 {
12016   /* Skip mod/rm byte.  */
12017   MODRM_CHECK;
12018   codep++;
12019
12020   if (modrm.mod == 3)
12021     OP_E_register (bytemode, sizeflag);
12022   else
12023     OP_E_memory (bytemode, sizeflag);
12024 }
12025
12026 static void
12027 OP_E (int bytemode, int sizeflag)
12028 {
12029   OP_E_extended (bytemode, sizeflag);
12030 }
12031
12032
12033 static void
12034 OP_G (int bytemode, int sizeflag)
12035 {
12036   int add = 0;
12037   USED_REX (REX_R);
12038   if (rex & REX_R)
12039     add += 8;
12040   switch (bytemode)
12041     {
12042     case b_mode:
12043       USED_REX (0);
12044       if (rex)
12045         oappend (names8rex[modrm.reg + add]);
12046       else
12047         oappend (names8[modrm.reg + add]);
12048       break;
12049     case w_mode:
12050       oappend (names16[modrm.reg + add]);
12051       break;
12052     case d_mode:
12053       oappend (names32[modrm.reg + add]);
12054       break;
12055     case q_mode:
12056       oappend (names64[modrm.reg + add]);
12057       break;
12058     case v_mode:
12059     case dq_mode:
12060     case dqb_mode:
12061     case dqd_mode:
12062     case dqw_mode:
12063       USED_REX (REX_W);
12064       if (rex & REX_W)
12065         oappend (names64[modrm.reg + add]);
12066       else if ((sizeflag & DFLAG) || bytemode != v_mode)
12067         oappend (names32[modrm.reg + add]);
12068       else
12069         oappend (names16[modrm.reg + add]);
12070       used_prefixes |= (prefixes & PREFIX_DATA);
12071       break;
12072     case m_mode:
12073       if (address_mode == mode_64bit)
12074         oappend (names64[modrm.reg + add]);
12075       else
12076         oappend (names32[modrm.reg + add]);
12077       break;
12078     default:
12079       oappend (INTERNAL_DISASSEMBLER_ERROR);
12080       break;
12081     }
12082 }
12083
12084 static bfd_vma
12085 get64 (void)
12086 {
12087   bfd_vma x;
12088 #ifdef BFD64
12089   unsigned int a;
12090   unsigned int b;
12091
12092   FETCH_DATA (the_info, codep + 8);
12093   a = *codep++ & 0xff;
12094   a |= (*codep++ & 0xff) << 8;
12095   a |= (*codep++ & 0xff) << 16;
12096   a |= (*codep++ & 0xff) << 24;
12097   b = *codep++ & 0xff;
12098   b |= (*codep++ & 0xff) << 8;
12099   b |= (*codep++ & 0xff) << 16;
12100   b |= (*codep++ & 0xff) << 24;
12101   x = a + ((bfd_vma) b << 32);
12102 #else
12103   abort ();
12104   x = 0;
12105 #endif
12106   return x;
12107 }
12108
12109 static bfd_signed_vma
12110 get32 (void)
12111 {
12112   bfd_signed_vma x = 0;
12113
12114   FETCH_DATA (the_info, codep + 4);
12115   x = *codep++ & (bfd_signed_vma) 0xff;
12116   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
12117   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
12118   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
12119   return x;
12120 }
12121
12122 static bfd_signed_vma
12123 get32s (void)
12124 {
12125   bfd_signed_vma x = 0;
12126
12127   FETCH_DATA (the_info, codep + 4);
12128   x = *codep++ & (bfd_signed_vma) 0xff;
12129   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
12130   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
12131   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
12132
12133   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
12134
12135   return x;
12136 }
12137
12138 static int
12139 get16 (void)
12140 {
12141   int x = 0;
12142
12143   FETCH_DATA (the_info, codep + 2);
12144   x = *codep++ & 0xff;
12145   x |= (*codep++ & 0xff) << 8;
12146   return x;
12147 }
12148
12149 static void
12150 set_op (bfd_vma op, int riprel)
12151 {
12152   op_index[op_ad] = op_ad;
12153   if (address_mode == mode_64bit)
12154     {
12155       op_address[op_ad] = op;
12156       op_riprel[op_ad] = riprel;
12157     }
12158   else
12159     {
12160       /* Mask to get a 32-bit address.  */
12161       op_address[op_ad] = op & 0xffffffff;
12162       op_riprel[op_ad] = riprel & 0xffffffff;
12163     }
12164 }
12165
12166 static void
12167 OP_REG (int code, int sizeflag)
12168 {
12169   const char *s;
12170   int add;
12171   USED_REX (REX_B);
12172   if (rex & REX_B)
12173     add = 8;
12174   else
12175     add = 0;
12176
12177   switch (code)
12178     {
12179     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
12180     case sp_reg: case bp_reg: case si_reg: case di_reg:
12181       s = names16[code - ax_reg + add];
12182       break;
12183     case es_reg: case ss_reg: case cs_reg:
12184     case ds_reg: case fs_reg: case gs_reg:
12185       s = names_seg[code - es_reg + add];
12186       break;
12187     case al_reg: case ah_reg: case cl_reg: case ch_reg:
12188     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
12189       USED_REX (0);
12190       if (rex)
12191         s = names8rex[code - al_reg + add];
12192       else
12193         s = names8[code - al_reg];
12194       break;
12195     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
12196     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
12197       if (address_mode == mode_64bit && (sizeflag & DFLAG))
12198         {
12199           s = names64[code - rAX_reg + add];
12200           break;
12201         }
12202       code += eAX_reg - rAX_reg;
12203       /* Fall through.  */
12204     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
12205     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
12206       USED_REX (REX_W);
12207       if (rex & REX_W)
12208         s = names64[code - eAX_reg + add];
12209       else if (sizeflag & DFLAG)
12210         s = names32[code - eAX_reg + add];
12211       else
12212         s = names16[code - eAX_reg + add];
12213       used_prefixes |= (prefixes & PREFIX_DATA);
12214       break;
12215     default:
12216       s = INTERNAL_DISASSEMBLER_ERROR;
12217       break;
12218     }
12219   oappend (s);
12220 }
12221
12222 static void
12223 OP_IMREG (int code, int sizeflag)
12224 {
12225   const char *s;
12226
12227   switch (code)
12228     {
12229     case indir_dx_reg:
12230       if (intel_syntax)
12231         s = "dx";
12232       else
12233         s = "(%dx)";
12234       break;
12235     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
12236     case sp_reg: case bp_reg: case si_reg: case di_reg:
12237       s = names16[code - ax_reg];
12238       break;
12239     case es_reg: case ss_reg: case cs_reg:
12240     case ds_reg: case fs_reg: case gs_reg:
12241       s = names_seg[code - es_reg];
12242       break;
12243     case al_reg: case ah_reg: case cl_reg: case ch_reg:
12244     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
12245       USED_REX (0);
12246       if (rex)
12247         s = names8rex[code - al_reg];
12248       else
12249         s = names8[code - al_reg];
12250       break;
12251     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
12252     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
12253       USED_REX (REX_W);
12254       if (rex & REX_W)
12255         s = names64[code - eAX_reg];
12256       else if (sizeflag & DFLAG)
12257         s = names32[code - eAX_reg];
12258       else
12259         s = names16[code - eAX_reg];
12260       used_prefixes |= (prefixes & PREFIX_DATA);
12261       break;
12262     case z_mode_ax_reg:
12263       if ((rex & REX_W) || (sizeflag & DFLAG))
12264         s = *names32;
12265       else
12266         s = *names16;
12267       if (!(rex & REX_W))
12268         used_prefixes |= (prefixes & PREFIX_DATA);
12269       break;
12270     default:
12271       s = INTERNAL_DISASSEMBLER_ERROR;
12272       break;
12273     }
12274   oappend (s);
12275 }
12276
12277 static void
12278 OP_I (int bytemode, int sizeflag)
12279 {
12280   bfd_signed_vma op;
12281   bfd_signed_vma mask = -1;
12282
12283   switch (bytemode)
12284     {
12285     case b_mode:
12286       FETCH_DATA (the_info, codep + 1);
12287       op = *codep++;
12288       mask = 0xff;
12289       break;
12290     case q_mode:
12291       if (address_mode == mode_64bit)
12292         {
12293           op = get32s ();
12294           break;
12295         }
12296       /* Fall through.  */
12297     case v_mode:
12298       USED_REX (REX_W);
12299       if (rex & REX_W)
12300         op = get32s ();
12301       else if (sizeflag & DFLAG)
12302         {
12303           op = get32 ();
12304           mask = 0xffffffff;
12305         }
12306       else
12307         {
12308           op = get16 ();
12309           mask = 0xfffff;
12310         }
12311       used_prefixes |= (prefixes & PREFIX_DATA);
12312       break;
12313     case w_mode:
12314       mask = 0xfffff;
12315       op = get16 ();
12316       break;
12317     case const_1_mode:
12318       if (intel_syntax)
12319         oappend ("1");
12320       return;
12321     default:
12322       oappend (INTERNAL_DISASSEMBLER_ERROR);
12323       return;
12324     }
12325
12326   op &= mask;
12327   scratchbuf[0] = '$';
12328   print_operand_value (scratchbuf + 1, 1, op);
12329   oappend (scratchbuf + intel_syntax);
12330   scratchbuf[0] = '\0';
12331 }
12332
12333 static void
12334 OP_I64 (int bytemode, int sizeflag)
12335 {
12336   bfd_signed_vma op;
12337   bfd_signed_vma mask = -1;
12338
12339   if (address_mode != mode_64bit)
12340     {
12341       OP_I (bytemode, sizeflag);
12342       return;
12343     }
12344
12345   switch (bytemode)
12346     {
12347     case b_mode:
12348       FETCH_DATA (the_info, codep + 1);
12349       op = *codep++;
12350       mask = 0xff;
12351       break;
12352     case v_mode:
12353       USED_REX (REX_W);
12354       if (rex & REX_W)
12355         op = get64 ();
12356       else if (sizeflag & DFLAG)
12357         {
12358           op = get32 ();
12359           mask = 0xffffffff;
12360         }
12361       else
12362         {
12363           op = get16 ();
12364           mask = 0xfffff;
12365         }
12366       used_prefixes |= (prefixes & PREFIX_DATA);
12367       break;
12368     case w_mode:
12369       mask = 0xfffff;
12370       op = get16 ();
12371       break;
12372     default:
12373       oappend (INTERNAL_DISASSEMBLER_ERROR);
12374       return;
12375     }
12376
12377   op &= mask;
12378   scratchbuf[0] = '$';
12379   print_operand_value (scratchbuf + 1, 1, op);
12380   oappend (scratchbuf + intel_syntax);
12381   scratchbuf[0] = '\0';
12382 }
12383
12384 static void
12385 OP_sI (int bytemode, int sizeflag)
12386 {
12387   bfd_signed_vma op;
12388   bfd_signed_vma mask = -1;
12389
12390   switch (bytemode)
12391     {
12392     case b_mode:
12393       FETCH_DATA (the_info, codep + 1);
12394       op = *codep++;
12395       if ((op & 0x80) != 0)
12396         op -= 0x100;
12397       mask = 0xffffffff;
12398       break;
12399     case v_mode:
12400       USED_REX (REX_W);
12401       if (rex & REX_W)
12402         op = get32s ();
12403       else if (sizeflag & DFLAG)
12404         {
12405           op = get32s ();
12406           mask = 0xffffffff;
12407         }
12408       else
12409         {
12410           mask = 0xffffffff;
12411           op = get16 ();
12412           if ((op & 0x8000) != 0)
12413             op -= 0x10000;
12414         }
12415       used_prefixes |= (prefixes & PREFIX_DATA);
12416       break;
12417     case w_mode:
12418       op = get16 ();
12419       mask = 0xffffffff;
12420       if ((op & 0x8000) != 0)
12421         op -= 0x10000;
12422       break;
12423     default:
12424       oappend (INTERNAL_DISASSEMBLER_ERROR);
12425       return;
12426     }
12427
12428   scratchbuf[0] = '$';
12429   print_operand_value (scratchbuf + 1, 1, op);
12430   oappend (scratchbuf + intel_syntax);
12431 }
12432
12433 static void
12434 OP_J (int bytemode, int sizeflag)
12435 {
12436   bfd_vma disp;
12437   bfd_vma mask = -1;
12438   bfd_vma segment = 0;
12439
12440   switch (bytemode)
12441     {
12442     case b_mode:
12443       FETCH_DATA (the_info, codep + 1);
12444       disp = *codep++;
12445       if ((disp & 0x80) != 0)
12446         disp -= 0x100;
12447       break;
12448     case v_mode:
12449       if ((sizeflag & DFLAG) || (rex & REX_W))
12450         disp = get32s ();
12451       else
12452         {
12453           disp = get16 ();
12454           if ((disp & 0x8000) != 0)
12455             disp -= 0x10000;
12456           /* In 16bit mode, address is wrapped around at 64k within
12457              the same segment.  Otherwise, a data16 prefix on a jump
12458              instruction means that the pc is masked to 16 bits after
12459              the displacement is added!  */
12460           mask = 0xffff;
12461           if ((prefixes & PREFIX_DATA) == 0)
12462             segment = ((start_pc + codep - start_codep)
12463                        & ~((bfd_vma) 0xffff));
12464         }
12465       used_prefixes |= (prefixes & PREFIX_DATA);
12466       break;
12467     default:
12468       oappend (INTERNAL_DISASSEMBLER_ERROR);
12469       return;
12470     }
12471   disp = ((start_pc + codep - start_codep + disp) & mask) | segment;
12472   set_op (disp, 0);
12473   print_operand_value (scratchbuf, 1, disp);
12474   oappend (scratchbuf);
12475 }
12476
12477 static void
12478 OP_SEG (int bytemode, int sizeflag)
12479 {
12480   if (bytemode == w_mode)
12481     oappend (names_seg[modrm.reg]);
12482   else
12483     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
12484 }
12485
12486 static void
12487 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
12488 {
12489   int seg, offset;
12490
12491   if (sizeflag & DFLAG)
12492     {
12493       offset = get32 ();
12494       seg = get16 ();
12495     }
12496   else
12497     {
12498       offset = get16 ();
12499       seg = get16 ();
12500     }
12501   used_prefixes |= (prefixes & PREFIX_DATA);
12502   if (intel_syntax)
12503     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
12504   else
12505     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
12506   oappend (scratchbuf);
12507 }
12508
12509 static void
12510 OP_OFF (int bytemode, int sizeflag)
12511 {
12512   bfd_vma off;
12513
12514   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12515     intel_operand_size (bytemode, sizeflag);
12516   append_seg ();
12517
12518   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
12519     off = get32 ();
12520   else
12521     off = get16 ();
12522
12523   if (intel_syntax)
12524     {
12525       if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
12526                         | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
12527         {
12528           oappend (names_seg[ds_reg - es_reg]);
12529           oappend (":");
12530         }
12531     }
12532   print_operand_value (scratchbuf, 1, off);
12533   oappend (scratchbuf);
12534 }
12535
12536 static void
12537 OP_OFF64 (int bytemode, int sizeflag)
12538 {
12539   bfd_vma off;
12540
12541   if (address_mode != mode_64bit
12542       || (prefixes & PREFIX_ADDR))
12543     {
12544       OP_OFF (bytemode, sizeflag);
12545       return;
12546     }
12547
12548   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12549     intel_operand_size (bytemode, sizeflag);
12550   append_seg ();
12551
12552   off = get64 ();
12553
12554   if (intel_syntax)
12555     {
12556       if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
12557                         | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
12558         {
12559           oappend (names_seg[ds_reg - es_reg]);
12560           oappend (":");
12561         }
12562     }
12563   print_operand_value (scratchbuf, 1, off);
12564   oappend (scratchbuf);
12565 }
12566
12567 static void
12568 ptr_reg (int code, int sizeflag)
12569 {
12570   const char *s;
12571
12572   *obufp++ = open_char;
12573   used_prefixes |= (prefixes & PREFIX_ADDR);
12574   if (address_mode == mode_64bit)
12575     {
12576       if (!(sizeflag & AFLAG))
12577         s = names32[code - eAX_reg];
12578       else
12579         s = names64[code - eAX_reg];
12580     }
12581   else if (sizeflag & AFLAG)
12582     s = names32[code - eAX_reg];
12583   else
12584     s = names16[code - eAX_reg];
12585   oappend (s);
12586   *obufp++ = close_char;
12587   *obufp = 0;
12588 }
12589
12590 static void
12591 OP_ESreg (int code, int sizeflag)
12592 {
12593   if (intel_syntax)
12594     {
12595       switch (codep[-1])
12596         {
12597         case 0x6d:      /* insw/insl */
12598           intel_operand_size (z_mode, sizeflag);
12599           break;
12600         case 0xa5:      /* movsw/movsl/movsq */
12601         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
12602         case 0xab:      /* stosw/stosl */
12603         case 0xaf:      /* scasw/scasl */
12604           intel_operand_size (v_mode, sizeflag);
12605           break;
12606         default:
12607           intel_operand_size (b_mode, sizeflag);
12608         }
12609     }
12610   oappend ("%es:" + intel_syntax);
12611   ptr_reg (code, sizeflag);
12612 }
12613
12614 static void
12615 OP_DSreg (int code, int sizeflag)
12616 {
12617   if (intel_syntax)
12618     {
12619       switch (codep[-1])
12620         {
12621         case 0x6f:      /* outsw/outsl */
12622           intel_operand_size (z_mode, sizeflag);
12623           break;
12624         case 0xa5:      /* movsw/movsl/movsq */
12625         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
12626         case 0xad:      /* lodsw/lodsl/lodsq */
12627           intel_operand_size (v_mode, sizeflag);
12628           break;
12629         default:
12630           intel_operand_size (b_mode, sizeflag);
12631         }
12632     }
12633   if ((prefixes
12634        & (PREFIX_CS
12635           | PREFIX_DS
12636           | PREFIX_SS
12637           | PREFIX_ES
12638           | PREFIX_FS
12639           | PREFIX_GS)) == 0)
12640     prefixes |= PREFIX_DS;
12641   append_seg ();
12642   ptr_reg (code, sizeflag);
12643 }
12644
12645 static void
12646 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12647 {
12648   int add;
12649   if (rex & REX_R)
12650     {
12651       USED_REX (REX_R);
12652       add = 8;
12653     }
12654   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
12655     {
12656       lock_prefix = NULL;
12657       used_prefixes |= PREFIX_LOCK;
12658       add = 8;
12659     }
12660   else
12661     add = 0;
12662   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
12663   oappend (scratchbuf + intel_syntax);
12664 }
12665
12666 static void
12667 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12668 {
12669   int add;
12670   USED_REX (REX_R);
12671   if (rex & REX_R)
12672     add = 8;
12673   else
12674     add = 0;
12675   if (intel_syntax)
12676     sprintf (scratchbuf, "db%d", modrm.reg + add);
12677   else
12678     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
12679   oappend (scratchbuf);
12680 }
12681
12682 static void
12683 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12684 {
12685   sprintf (scratchbuf, "%%tr%d", modrm.reg);
12686   oappend (scratchbuf + intel_syntax);
12687 }
12688
12689 static void
12690 OP_R (int bytemode, int sizeflag)
12691 {
12692   if (modrm.mod == 3)
12693     OP_E (bytemode, sizeflag);
12694   else
12695     BadOp ();
12696 }
12697
12698 static void
12699 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12700 {
12701   used_prefixes |= (prefixes & PREFIX_DATA);
12702   if (prefixes & PREFIX_DATA)
12703     {
12704       int add;
12705       USED_REX (REX_R);
12706       if (rex & REX_R)
12707         add = 8;
12708       else
12709         add = 0;
12710       sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
12711     }
12712   else
12713     sprintf (scratchbuf, "%%mm%d", modrm.reg);
12714   oappend (scratchbuf + intel_syntax);
12715 }
12716
12717 static void
12718 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
12719 {
12720   int add;
12721   USED_REX (REX_R);
12722   if (rex & REX_R)
12723     add = 8;
12724   else
12725     add = 0;
12726   if (need_vex && bytemode != xmm_mode)
12727     {
12728       switch (vex.length)
12729         {
12730         case 128:
12731           sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
12732           break;
12733         case 256:
12734           sprintf (scratchbuf, "%%ymm%d", modrm.reg + add);
12735           break;
12736         default:
12737           abort ();
12738         }
12739     }
12740   else
12741     sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
12742   oappend (scratchbuf + intel_syntax);
12743 }
12744
12745 static void
12746 OP_EM (int bytemode, int sizeflag)
12747 {
12748   if (modrm.mod != 3)
12749     {
12750       if (intel_syntax
12751           && (bytemode == v_mode || bytemode == v_swap_mode))
12752         {
12753           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
12754           used_prefixes |= (prefixes & PREFIX_DATA);
12755         }
12756       OP_E (bytemode, sizeflag);
12757       return;
12758     }
12759
12760   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
12761     swap_operand ();
12762
12763   /* Skip mod/rm byte.  */
12764   MODRM_CHECK;
12765   codep++;
12766   used_prefixes |= (prefixes & PREFIX_DATA);
12767   if (prefixes & PREFIX_DATA)
12768     {
12769       int add;
12770
12771       USED_REX (REX_B);
12772       if (rex & REX_B)
12773         add = 8;
12774       else
12775         add = 0;
12776       sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
12777     }
12778   else
12779     sprintf (scratchbuf, "%%mm%d", modrm.rm);
12780   oappend (scratchbuf + intel_syntax);
12781 }
12782
12783 /* cvt* are the only instructions in sse2 which have
12784    both SSE and MMX operands and also have 0x66 prefix
12785    in their opcode. 0x66 was originally used to differentiate
12786    between SSE and MMX instruction(operands). So we have to handle the
12787    cvt* separately using OP_EMC and OP_MXC */
12788 static void
12789 OP_EMC (int bytemode, int sizeflag)
12790 {
12791   if (modrm.mod != 3)
12792     {
12793       if (intel_syntax && bytemode == v_mode)
12794         {
12795           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
12796           used_prefixes |= (prefixes & PREFIX_DATA);
12797         }
12798       OP_E (bytemode, sizeflag);
12799       return;
12800     }
12801
12802   /* Skip mod/rm byte.  */
12803   MODRM_CHECK;
12804   codep++;
12805   used_prefixes |= (prefixes & PREFIX_DATA);
12806   sprintf (scratchbuf, "%%mm%d", modrm.rm);
12807   oappend (scratchbuf + intel_syntax);
12808 }
12809
12810 static void
12811 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12812 {
12813   used_prefixes |= (prefixes & PREFIX_DATA);
12814   sprintf (scratchbuf, "%%mm%d", modrm.reg);
12815   oappend (scratchbuf + intel_syntax);
12816 }
12817
12818 static void
12819 OP_EX (int bytemode, int sizeflag)
12820 {
12821   int add;
12822
12823   /* Skip mod/rm byte.  */
12824   MODRM_CHECK;
12825   codep++;
12826
12827   if (modrm.mod != 3)
12828     {
12829       OP_E_memory (bytemode, sizeflag);
12830       return;
12831     }
12832
12833   USED_REX (REX_B);
12834   if (rex & REX_B)
12835     add = 8;
12836   else
12837     add = 0;
12838
12839   if ((sizeflag & SUFFIX_ALWAYS)
12840       && (bytemode == x_swap_mode
12841           || bytemode == d_swap_mode
12842           || bytemode == q_swap_mode))
12843     swap_operand ();
12844
12845   if (need_vex
12846       && bytemode != xmm_mode
12847       && bytemode != xmmq_mode)
12848     {
12849       switch (vex.length)
12850         {
12851         case 128:
12852           sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
12853           break;
12854         case 256:
12855           sprintf (scratchbuf, "%%ymm%d", modrm.rm + add);
12856           break;
12857         default:
12858           abort ();
12859         }
12860     }
12861   else
12862     sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
12863   oappend (scratchbuf + intel_syntax);
12864 }
12865
12866 static void
12867 OP_MS (int bytemode, int sizeflag)
12868 {
12869   if (modrm.mod == 3)
12870     OP_EM (bytemode, sizeflag);
12871   else
12872     BadOp ();
12873 }
12874
12875 static void
12876 OP_XS (int bytemode, int sizeflag)
12877 {
12878   if (modrm.mod == 3)
12879     OP_EX (bytemode, sizeflag);
12880   else
12881     BadOp ();
12882 }
12883
12884 static void
12885 OP_M (int bytemode, int sizeflag)
12886 {
12887   if (modrm.mod == 3)
12888     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
12889     BadOp ();
12890   else
12891     OP_E (bytemode, sizeflag);
12892 }
12893
12894 static void
12895 OP_0f07 (int bytemode, int sizeflag)
12896 {
12897   if (modrm.mod != 3 || modrm.rm != 0)
12898     BadOp ();
12899   else
12900     OP_E (bytemode, sizeflag);
12901 }
12902
12903 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
12904    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
12905
12906 static void
12907 NOP_Fixup1 (int bytemode, int sizeflag)
12908 {
12909   if ((prefixes & PREFIX_DATA) != 0
12910       || (rex != 0
12911           && rex != 0x48
12912           && address_mode == mode_64bit))
12913     OP_REG (bytemode, sizeflag);
12914   else
12915     strcpy (obuf, "nop");
12916 }
12917
12918 static void
12919 NOP_Fixup2 (int bytemode, int sizeflag)
12920 {
12921   if ((prefixes & PREFIX_DATA) != 0
12922       || (rex != 0
12923           && rex != 0x48
12924           && address_mode == mode_64bit))
12925     OP_IMREG (bytemode, sizeflag);
12926 }
12927
12928 static const char *const Suffix3DNow[] = {
12929 /* 00 */        NULL,           NULL,           NULL,           NULL,
12930 /* 04 */        NULL,           NULL,           NULL,           NULL,
12931 /* 08 */        NULL,           NULL,           NULL,           NULL,
12932 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
12933 /* 10 */        NULL,           NULL,           NULL,           NULL,
12934 /* 14 */        NULL,           NULL,           NULL,           NULL,
12935 /* 18 */        NULL,           NULL,           NULL,           NULL,
12936 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
12937 /* 20 */        NULL,           NULL,           NULL,           NULL,
12938 /* 24 */        NULL,           NULL,           NULL,           NULL,
12939 /* 28 */        NULL,           NULL,           NULL,           NULL,
12940 /* 2C */        NULL,           NULL,           NULL,           NULL,
12941 /* 30 */        NULL,           NULL,           NULL,           NULL,
12942 /* 34 */        NULL,           NULL,           NULL,           NULL,
12943 /* 38 */        NULL,           NULL,           NULL,           NULL,
12944 /* 3C */        NULL,           NULL,           NULL,           NULL,
12945 /* 40 */        NULL,           NULL,           NULL,           NULL,
12946 /* 44 */        NULL,           NULL,           NULL,           NULL,
12947 /* 48 */        NULL,           NULL,           NULL,           NULL,
12948 /* 4C */        NULL,           NULL,           NULL,           NULL,
12949 /* 50 */        NULL,           NULL,           NULL,           NULL,
12950 /* 54 */        NULL,           NULL,           NULL,           NULL,
12951 /* 58 */        NULL,           NULL,           NULL,           NULL,
12952 /* 5C */        NULL,           NULL,           NULL,           NULL,
12953 /* 60 */        NULL,           NULL,           NULL,           NULL,
12954 /* 64 */        NULL,           NULL,           NULL,           NULL,
12955 /* 68 */        NULL,           NULL,           NULL,           NULL,
12956 /* 6C */        NULL,           NULL,           NULL,           NULL,
12957 /* 70 */        NULL,           NULL,           NULL,           NULL,
12958 /* 74 */        NULL,           NULL,           NULL,           NULL,
12959 /* 78 */        NULL,           NULL,           NULL,           NULL,
12960 /* 7C */        NULL,           NULL,           NULL,           NULL,
12961 /* 80 */        NULL,           NULL,           NULL,           NULL,
12962 /* 84 */        NULL,           NULL,           NULL,           NULL,
12963 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
12964 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
12965 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
12966 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
12967 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
12968 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
12969 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
12970 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
12971 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
12972 /* AC */        NULL,           NULL,           "pfacc",        NULL,
12973 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
12974 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
12975 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
12976 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
12977 /* C0 */        NULL,           NULL,           NULL,           NULL,
12978 /* C4 */        NULL,           NULL,           NULL,           NULL,
12979 /* C8 */        NULL,           NULL,           NULL,           NULL,
12980 /* CC */        NULL,           NULL,           NULL,           NULL,
12981 /* D0 */        NULL,           NULL,           NULL,           NULL,
12982 /* D4 */        NULL,           NULL,           NULL,           NULL,
12983 /* D8 */        NULL,           NULL,           NULL,           NULL,
12984 /* DC */        NULL,           NULL,           NULL,           NULL,
12985 /* E0 */        NULL,           NULL,           NULL,           NULL,
12986 /* E4 */        NULL,           NULL,           NULL,           NULL,
12987 /* E8 */        NULL,           NULL,           NULL,           NULL,
12988 /* EC */        NULL,           NULL,           NULL,           NULL,
12989 /* F0 */        NULL,           NULL,           NULL,           NULL,
12990 /* F4 */        NULL,           NULL,           NULL,           NULL,
12991 /* F8 */        NULL,           NULL,           NULL,           NULL,
12992 /* FC */        NULL,           NULL,           NULL,           NULL,
12993 };
12994
12995 static void
12996 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12997 {
12998   const char *mnemonic;
12999
13000   FETCH_DATA (the_info, codep + 1);
13001   /* AMD 3DNow! instructions are specified by an opcode suffix in the
13002      place where an 8-bit immediate would normally go.  ie. the last
13003      byte of the instruction.  */
13004   obufp = mnemonicendp;
13005   mnemonic = Suffix3DNow[*codep++ & 0xff];
13006   if (mnemonic)
13007     oappend (mnemonic);
13008   else
13009     {
13010       /* Since a variable sized modrm/sib chunk is between the start
13011          of the opcode (0x0f0f) and the opcode suffix, we need to do
13012          all the modrm processing first, and don't know until now that
13013          we have a bad opcode.  This necessitates some cleaning up.  */
13014       op_out[0][0] = '\0';
13015       op_out[1][0] = '\0';
13016       BadOp ();
13017     }
13018   mnemonicendp = obufp;
13019 }
13020
13021 static struct op simd_cmp_op[] =
13022 {
13023   { STRING_COMMA_LEN ("eq") },
13024   { STRING_COMMA_LEN ("lt") },
13025   { STRING_COMMA_LEN ("le") },
13026   { STRING_COMMA_LEN ("unord") },
13027   { STRING_COMMA_LEN ("neq") },
13028   { STRING_COMMA_LEN ("nlt") },
13029   { STRING_COMMA_LEN ("nle") },
13030   { STRING_COMMA_LEN ("ord") }
13031 };
13032
13033 static void
13034 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13035 {
13036   unsigned int cmp_type;
13037
13038   FETCH_DATA (the_info, codep + 1);
13039   cmp_type = *codep++ & 0xff;
13040   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
13041     {
13042       char suffix [3];
13043       char *p = mnemonicendp - 2;
13044       suffix[0] = p[0];
13045       suffix[1] = p[1];
13046       suffix[2] = '\0';
13047       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13048       mnemonicendp += simd_cmp_op[cmp_type].len;
13049     }
13050   else
13051     {
13052       /* We have a reserved extension byte.  Output it directly.  */
13053       scratchbuf[0] = '$';
13054       print_operand_value (scratchbuf + 1, 1, cmp_type);
13055       oappend (scratchbuf + intel_syntax);
13056       scratchbuf[0] = '\0';
13057     }
13058 }
13059
13060 static void
13061 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
13062           int sizeflag ATTRIBUTE_UNUSED)
13063 {
13064   /* mwait %eax,%ecx  */
13065   if (!intel_syntax)
13066     {
13067       const char **names = (address_mode == mode_64bit
13068                             ? names64 : names32);
13069       strcpy (op_out[0], names[0]);
13070       strcpy (op_out[1], names[1]);
13071       two_source_ops = 1;
13072     }
13073   /* Skip mod/rm byte.  */
13074   MODRM_CHECK;
13075   codep++;
13076 }
13077
13078 static void
13079 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
13080             int sizeflag ATTRIBUTE_UNUSED)
13081 {
13082   /* monitor %eax,%ecx,%edx"  */
13083   if (!intel_syntax)
13084     {
13085       const char **op1_names;
13086       const char **names = (address_mode == mode_64bit
13087                             ? names64 : names32);
13088
13089       if (!(prefixes & PREFIX_ADDR))
13090         op1_names = (address_mode == mode_16bit
13091                      ? names16 : names);
13092       else
13093         {
13094           /* Remove "addr16/addr32".  */
13095           addr_prefix = NULL;
13096           op1_names = (address_mode != mode_32bit
13097                        ? names32 : names16);
13098           used_prefixes |= PREFIX_ADDR;
13099         }
13100       strcpy (op_out[0], op1_names[0]);
13101       strcpy (op_out[1], names[1]);
13102       strcpy (op_out[2], names[2]);
13103       two_source_ops = 1;
13104     }
13105   /* Skip mod/rm byte.  */
13106   MODRM_CHECK;
13107   codep++;
13108 }
13109
13110 static void
13111 BadOp (void)
13112 {
13113   /* Throw away prefixes and 1st. opcode byte.  */
13114   codep = insn_codep + 1;
13115   oappend ("(bad)");
13116 }
13117
13118 static void
13119 REP_Fixup (int bytemode, int sizeflag)
13120 {
13121   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
13122      lods and stos.  */
13123   if (prefixes & PREFIX_REPZ)
13124     repz_prefix = "rep ";
13125
13126   switch (bytemode)
13127     {
13128     case al_reg:
13129     case eAX_reg:
13130     case indir_dx_reg:
13131       OP_IMREG (bytemode, sizeflag);
13132       break;
13133     case eDI_reg:
13134       OP_ESreg (bytemode, sizeflag);
13135       break;
13136     case eSI_reg:
13137       OP_DSreg (bytemode, sizeflag);
13138       break;
13139     default:
13140       abort ();
13141       break;
13142     }
13143 }
13144
13145 static void
13146 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
13147 {
13148   USED_REX (REX_W);
13149   if (rex & REX_W)
13150     {
13151       /* Change cmpxchg8b to cmpxchg16b.  */
13152       char *p = mnemonicendp - 2;
13153       mnemonicendp = stpcpy (p, "16b");
13154       bytemode = o_mode;
13155     }
13156   OP_M (bytemode, sizeflag);
13157 }
13158
13159 static void
13160 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
13161 {
13162   if (need_vex)
13163     {
13164       switch (vex.length)
13165         {
13166         case 128:
13167           sprintf (scratchbuf, "%%xmm%d", reg);
13168           break;
13169         case 256:
13170           sprintf (scratchbuf, "%%ymm%d", reg);
13171           break;
13172         default:
13173           abort ();
13174         }
13175     }
13176   else
13177     sprintf (scratchbuf, "%%xmm%d", reg);
13178   oappend (scratchbuf + intel_syntax);
13179 }
13180
13181 static void
13182 CRC32_Fixup (int bytemode, int sizeflag)
13183 {
13184   /* Add proper suffix to "crc32".  */
13185   char *p = mnemonicendp;
13186
13187   switch (bytemode)
13188     {
13189     case b_mode:
13190       if (intel_syntax)
13191         goto skip;
13192
13193       *p++ = 'b';
13194       break;
13195     case v_mode:
13196       if (intel_syntax)
13197         goto skip;
13198
13199       USED_REX (REX_W);
13200       if (rex & REX_W)
13201         *p++ = 'q';
13202       else if (sizeflag & DFLAG)
13203         *p++ = 'l';
13204       else
13205         *p++ = 'w';
13206       used_prefixes |= (prefixes & PREFIX_DATA);
13207       break;
13208     default:
13209       oappend (INTERNAL_DISASSEMBLER_ERROR);
13210       break;
13211     }
13212   mnemonicendp = p;
13213   *p = '\0';
13214
13215 skip:
13216   if (modrm.mod == 3)
13217     {
13218       int add;
13219
13220       /* Skip mod/rm byte.  */
13221       MODRM_CHECK;
13222       codep++;
13223
13224       USED_REX (REX_B);
13225       add = (rex & REX_B) ? 8 : 0;
13226       if (bytemode == b_mode)
13227         {
13228           USED_REX (0);
13229           if (rex)
13230             oappend (names8rex[modrm.rm + add]);
13231           else
13232             oappend (names8[modrm.rm + add]);
13233         }
13234       else
13235         {
13236           USED_REX (REX_W);
13237           if (rex & REX_W)
13238             oappend (names64[modrm.rm + add]);
13239           else if ((prefixes & PREFIX_DATA))
13240             oappend (names16[modrm.rm + add]);
13241           else
13242             oappend (names32[modrm.rm + add]);
13243         }
13244     }
13245   else
13246     OP_E (bytemode, sizeflag);
13247 }
13248
13249 /* Display the destination register operand for instructions with
13250    VEX. */
13251
13252 static void
13253 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13254 {
13255   if (!need_vex)
13256     abort ();
13257
13258   if (!need_vex_reg)
13259     return;
13260
13261   switch (vex.length)
13262     {
13263     case 128:
13264       switch (bytemode)
13265         {
13266         case vex_mode:
13267         case vex128_mode:
13268           break;
13269         default:
13270           abort ();
13271           return;
13272         }
13273
13274       sprintf (scratchbuf, "%%xmm%d", vex.register_specifier);
13275       break;
13276     case 256:
13277       switch (bytemode)
13278         {
13279         case vex_mode:
13280         case vex256_mode:
13281           break;
13282         default:
13283           abort ();
13284           return;
13285         }
13286
13287       sprintf (scratchbuf, "%%ymm%d", vex.register_specifier);
13288       break;
13289     default:
13290       abort ();
13291       break;
13292     }
13293   oappend (scratchbuf + intel_syntax);
13294 }
13295
13296 /* Get the VEX immediate byte without moving codep.  */
13297
13298 static unsigned char
13299 get_vex_imm8 (int sizeflag)
13300 {
13301   int bytes_before_imm = 0;
13302
13303   /* Skip mod/rm byte.   */
13304   MODRM_CHECK;
13305   codep++;
13306
13307   if (modrm.mod != 3)
13308     {
13309       /* There are SIB/displacement bytes.  */
13310       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
13311         {
13312           /* 32/64 bit address mode */
13313           int base = modrm.rm;
13314
13315           /* Check SIB byte.  */
13316           if (base == 4)
13317             {
13318               FETCH_DATA (the_info, codep + 1);
13319               base = *codep & 7;
13320               bytes_before_imm++;
13321             }
13322
13323           switch (modrm.mod)
13324             {
13325             case 0:
13326               /* When modrm.rm == 5 or modrm.rm == 4 and base in
13327                  SIB == 5, there is a 4 byte displacement.  */
13328               if (base != 5)
13329                 /* No displacement. */
13330                 break;
13331             case 2:
13332               /* 4 byte displacement.  */
13333               bytes_before_imm += 4;
13334               break;
13335             case 1:
13336               /* 1 byte displacement.  */
13337               bytes_before_imm++;
13338               break;
13339             }
13340         }
13341       else
13342         { /* 16 bit address mode */
13343           switch (modrm.mod)
13344             {
13345             case 0:
13346               /* When modrm.rm == 6, there is a 2 byte displacement.  */
13347               if (modrm.rm != 6)
13348                 /* No displacement. */
13349                 break;
13350             case 2:
13351               /* 2 byte displacement.  */
13352               bytes_before_imm += 2;
13353               break;
13354             case 1:
13355               /* 1 byte displacement.  */
13356               bytes_before_imm++;
13357               break;
13358             }
13359         }
13360     }
13361
13362   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
13363   return codep [bytes_before_imm];
13364 }
13365
13366 static void
13367 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
13368 {
13369   if (reg == -1 && modrm.mod != 3)
13370     {
13371       OP_E_memory (bytemode, sizeflag);
13372       return;
13373     }
13374   else
13375     {
13376       if (reg == -1)
13377         {
13378           reg = modrm.rm;
13379           USED_REX (REX_B);
13380           if (rex & REX_B)
13381             reg += 8;
13382         }
13383       else if (reg > 7 && address_mode != mode_64bit)
13384         BadOp ();
13385     }
13386
13387   switch (vex.length)
13388     {
13389     case 128:
13390       sprintf (scratchbuf, "%%xmm%d", reg);
13391       break;
13392     case 256:
13393       sprintf (scratchbuf, "%%ymm%d", reg);
13394       break;
13395     default:
13396       abort ();
13397     }
13398   oappend (scratchbuf + intel_syntax);
13399 }
13400
13401 static void
13402 OP_EX_VexW (int bytemode, int sizeflag)
13403 {
13404   int reg = -1;
13405
13406   if (!vex_w_done)
13407     {
13408       vex_w_done = 1;
13409       if (vex.w)
13410         reg = get_vex_imm8 (sizeflag) >> 4;
13411     }
13412   else
13413     {
13414       if (!vex.w)
13415         reg = get_vex_imm8 (sizeflag) >> 4;
13416     }
13417
13418   OP_EX_VexReg (bytemode, sizeflag, reg);
13419 }
13420
13421 static void
13422 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
13423              int sizeflag ATTRIBUTE_UNUSED)
13424 {
13425   /* Skip the immediate byte and check for invalid bits.  */
13426   FETCH_DATA (the_info, codep + 1);
13427   if (*codep++ & 0xf)
13428     BadOp ();
13429 }
13430
13431 static void
13432 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13433 {
13434   int reg;
13435   FETCH_DATA (the_info, codep + 1);
13436   reg = *codep++;
13437
13438   if (bytemode != x_mode)
13439     abort ();
13440
13441   if (reg & 0xf)
13442       BadOp ();
13443
13444   reg >>= 4;
13445   if (reg > 7 && address_mode != mode_64bit)
13446     BadOp ();
13447
13448   switch (vex.length)
13449     {
13450     case 128:
13451       sprintf (scratchbuf, "%%xmm%d", reg);
13452       break;
13453     case 256:
13454       sprintf (scratchbuf, "%%ymm%d", reg);
13455       break;
13456     default:
13457       abort ();
13458     }
13459   oappend (scratchbuf + intel_syntax);
13460 }
13461
13462 static void
13463 OP_XMM_VexW (int bytemode, int sizeflag)
13464 {
13465   /* Turn off the REX.W bit since it is used for swapping operands
13466      now.  */
13467   rex &= ~REX_W;
13468   OP_XMM (bytemode, sizeflag);
13469 }
13470
13471 static void
13472 OP_EX_Vex (int bytemode, int sizeflag)
13473 {
13474   if (modrm.mod != 3)
13475     {
13476       if (vex.register_specifier != 0)
13477         BadOp ();
13478       need_vex_reg = 0;
13479     }
13480   OP_EX (bytemode, sizeflag);
13481 }
13482
13483 static void
13484 OP_XMM_Vex (int bytemode, int sizeflag)
13485 {
13486   if (modrm.mod != 3)
13487     {
13488       if (vex.register_specifier != 0)
13489         BadOp ();
13490       need_vex_reg = 0;
13491     }
13492   OP_XMM (bytemode, sizeflag);
13493 }
13494
13495 static void
13496 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13497 {
13498   switch (vex.length)
13499     {
13500     case 128:
13501       mnemonicendp = stpcpy (obuf, "vzeroupper");
13502       break;
13503     case 256:
13504       mnemonicendp = stpcpy (obuf, "vzeroall");
13505       break;
13506     default:
13507       abort ();
13508     }
13509 }
13510
13511 static struct op vex_cmp_op[] =
13512 {
13513   { STRING_COMMA_LEN ("eq") },
13514   { STRING_COMMA_LEN ("lt") },
13515   { STRING_COMMA_LEN ("le") },
13516   { STRING_COMMA_LEN ("unord") },
13517   { STRING_COMMA_LEN ("neq") },
13518   { STRING_COMMA_LEN ("nlt") },
13519   { STRING_COMMA_LEN ("nle") },
13520   { STRING_COMMA_LEN ("ord") },
13521   { STRING_COMMA_LEN ("eq_uq") },
13522   { STRING_COMMA_LEN ("nge") },
13523   { STRING_COMMA_LEN ("ngt") },
13524   { STRING_COMMA_LEN ("false") },
13525   { STRING_COMMA_LEN ("neq_oq") },
13526   { STRING_COMMA_LEN ("ge") },
13527   { STRING_COMMA_LEN ("gt") },
13528   { STRING_COMMA_LEN ("true") },
13529   { STRING_COMMA_LEN ("eq_os") },
13530   { STRING_COMMA_LEN ("lt_oq") },
13531   { STRING_COMMA_LEN ("le_oq") },
13532   { STRING_COMMA_LEN ("unord_s") },
13533   { STRING_COMMA_LEN ("neq_us") },
13534   { STRING_COMMA_LEN ("nlt_uq") },
13535   { STRING_COMMA_LEN ("nle_uq") },
13536   { STRING_COMMA_LEN ("ord_s") },
13537   { STRING_COMMA_LEN ("eq_us") },
13538   { STRING_COMMA_LEN ("nge_uq") },
13539   { STRING_COMMA_LEN ("ngt_uq") },
13540   { STRING_COMMA_LEN ("false_os") },
13541   { STRING_COMMA_LEN ("neq_os") },
13542   { STRING_COMMA_LEN ("ge_oq") },
13543   { STRING_COMMA_LEN ("gt_oq") },
13544   { STRING_COMMA_LEN ("true_us") },
13545 };
13546
13547 static void
13548 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13549 {
13550   unsigned int cmp_type;
13551
13552   FETCH_DATA (the_info, codep + 1);
13553   cmp_type = *codep++ & 0xff;
13554   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
13555     {
13556       char suffix [3];
13557       char *p = mnemonicendp - 2;
13558       suffix[0] = p[0];
13559       suffix[1] = p[1];
13560       suffix[2] = '\0';
13561       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
13562       mnemonicendp += vex_cmp_op[cmp_type].len;
13563     }
13564   else
13565     {
13566       /* We have a reserved extension byte.  Output it directly.  */
13567       scratchbuf[0] = '$';
13568       print_operand_value (scratchbuf + 1, 1, cmp_type);
13569       oappend (scratchbuf + intel_syntax);
13570       scratchbuf[0] = '\0';
13571     }
13572 }
13573
13574 static const struct op pclmul_op[] =
13575 {
13576   { STRING_COMMA_LEN ("lql") },
13577   { STRING_COMMA_LEN ("hql") },
13578   { STRING_COMMA_LEN ("lqh") },
13579   { STRING_COMMA_LEN ("hqh") }
13580 };
13581
13582 static void
13583 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
13584               int sizeflag ATTRIBUTE_UNUSED)
13585 {
13586   unsigned int pclmul_type;
13587
13588   FETCH_DATA (the_info, codep + 1);
13589   pclmul_type = *codep++ & 0xff;
13590   switch (pclmul_type)
13591     {
13592     case 0x10:
13593       pclmul_type = 2;
13594       break;
13595     case 0x11:
13596       pclmul_type = 3;
13597       break;
13598     default:
13599       break;
13600     }
13601   if (pclmul_type < ARRAY_SIZE (pclmul_op))
13602     {
13603       char suffix [4];
13604       char *p = mnemonicendp - 3;
13605       suffix[0] = p[0];
13606       suffix[1] = p[1];
13607       suffix[2] = p[2];
13608       suffix[3] = '\0';
13609       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
13610       mnemonicendp += pclmul_op[pclmul_type].len;
13611     }
13612   else
13613     {
13614       /* We have a reserved extension byte.  Output it directly.  */
13615       scratchbuf[0] = '$';
13616       print_operand_value (scratchbuf + 1, 1, pclmul_type);
13617       oappend (scratchbuf + intel_syntax);
13618       scratchbuf[0] = '\0';
13619     }
13620 }
13621
13622 static void
13623 MOVBE_Fixup (int bytemode, int sizeflag)
13624 {
13625   /* Add proper suffix to "movbe".  */
13626   char *p = mnemonicendp;
13627
13628   switch (bytemode)
13629     {
13630     case v_mode:
13631       if (intel_syntax)
13632         goto skip;
13633
13634       USED_REX (REX_W);
13635       if (sizeflag & SUFFIX_ALWAYS)
13636         {
13637           if (rex & REX_W)
13638             *p++ = 'q';
13639           else if (sizeflag & DFLAG)
13640             *p++ = 'l';
13641           else
13642             *p++ = 'w';
13643         }
13644       used_prefixes |= (prefixes & PREFIX_DATA);
13645       break;
13646     default:
13647       oappend (INTERNAL_DISASSEMBLER_ERROR);
13648       break;
13649     }
13650   mnemonicendp = p;
13651   *p = '\0';
13652
13653 skip:
13654   OP_M (bytemode, sizeflag);
13655 }
13656
13657 static void
13658 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13659 {
13660   int reg;
13661   const char **names;
13662
13663   /* Skip mod/rm byte.  */
13664   MODRM_CHECK;
13665   codep++;
13666
13667   if (vex.w)
13668     names = names64;
13669   else if (vex.length == 256)
13670     names = names32;
13671   else
13672     names = names16;
13673
13674   reg = modrm.rm;
13675   USED_REX (REX_B);
13676   if (rex & REX_B)
13677     reg += 8;
13678
13679   oappend (names[reg]);
13680 }
13681
13682 static void
13683 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13684 {
13685   const char **names;
13686
13687   if (vex.w)
13688     names = names64;
13689   else if (vex.length == 256)
13690     names = names32;
13691   else
13692     names = names16;
13693
13694   oappend (names[vex.register_specifier]);
13695 }
13696
13697 static void
13698 OP_LWP_I (int bytemode ATTRIBUTE_UNUSED, int sizeflag)
13699 {
13700   if (vex.w || vex.length == 256)
13701     OP_I (q_mode, sizeflag);
13702   else
13703     OP_I (w_mode, sizeflag);
13704 }
13705