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PR 5233
[binutils-gdb.git] / opcodes / i386-dis.c
1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
4
5 This file is part of the GNU opcodes library.
6
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
11
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
21
22
23 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 July 1988
25 modified by John Hassey (hassey@dg-rtp.dg.com)
26 x86-64 support added by Jan Hubicka (jh@suse.cz)
27 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28
29 /* The main tables describing the instructions is essentially a copy
30 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
31 Programmers Manual. Usually, there is a capital letter, followed
32 by a small letter. The capital letter tell the addressing mode,
33 and the small letter tells about the operand size. Refer to
34 the Intel manual for details. */
35
36 #include "sysdep.h"
37 #include "dis-asm.h"
38 #include "opintl.h"
39 #include "opcode/i386.h"
40 #include "libiberty.h"
41
42 #include <setjmp.h>
43
44 static int fetch_data (struct disassemble_info *, bfd_byte *);
45 static void ckprefix (void);
46 static const char *prefix_name (int, int);
47 static int print_insn (bfd_vma, disassemble_info *);
48 static void dofloat (int);
49 static void OP_ST (int, int);
50 static void OP_STi (int, int);
51 static int putop (const char *, int);
52 static void oappend (const char *);
53 static void append_seg (void);
54 static void OP_indirE (int, int);
55 static void print_operand_value (char *, int, bfd_vma);
56 static void OP_E_extended (int, int, int);
57 static void print_displacement (char *, bfd_vma);
58 static void OP_E (int, int);
59 static void OP_G (int, int);
60 static bfd_vma get64 (void);
61 static bfd_signed_vma get32 (void);
62 static bfd_signed_vma get32s (void);
63 static int get16 (void);
64 static void set_op (bfd_vma, int);
65 static void OP_Skip_MODRM (int, int);
66 static void OP_REG (int, int);
67 static void OP_IMREG (int, int);
68 static void OP_I (int, int);
69 static void OP_I64 (int, int);
70 static void OP_sI (int, int);
71 static void OP_J (int, int);
72 static void OP_SEG (int, int);
73 static void OP_DIR (int, int);
74 static void OP_OFF (int, int);
75 static void OP_OFF64 (int, int);
76 static void ptr_reg (int, int);
77 static void OP_ESreg (int, int);
78 static void OP_DSreg (int, int);
79 static void OP_C (int, int);
80 static void OP_D (int, int);
81 static void OP_T (int, int);
82 static void OP_R (int, int);
83 static void OP_MMX (int, int);
84 static void OP_XMM (int, int);
85 static void OP_EM (int, int);
86 static void OP_EX (int, int);
87 static void OP_EMC (int,int);
88 static void OP_MXC (int,int);
89 static void OP_MS (int, int);
90 static void OP_XS (int, int);
91 static void OP_M (int, int);
92 static void OP_0f07 (int, int);
93 static void OP_Monitor (int, int);
94 static void OP_Mwait (int, int);
95 static void NOP_Fixup1 (int, int);
96 static void NOP_Fixup2 (int, int);
97 static void OP_3DNowSuffix (int, int);
98 static void CMP_Fixup (int, int);
99 static void BadOp (void);
100 static void REP_Fixup (int, int);
101 static void CMPXCHG8B_Fixup (int, int);
102 static void XMM_Fixup (int, int);
103 static void CRC32_Fixup (int, int);
104 static void print_drex_arg (unsigned int, int, int);
105 static void OP_DREX4 (int, int);
106 static void OP_DREX3 (int, int);
107 static void OP_DREX_ICMP (int, int);
108 static void OP_DREX_FCMP (int, int);
109
110 struct dis_private {
111 /* Points to first byte not fetched. */
112 bfd_byte *max_fetched;
113 bfd_byte the_buffer[MAX_MNEM_SIZE];
114 bfd_vma insn_start;
115 int orig_sizeflag;
116 jmp_buf bailout;
117 };
118
119 enum address_mode
120 {
121 mode_16bit,
122 mode_32bit,
123 mode_64bit
124 };
125
126 enum address_mode address_mode;
127
128 /* Flags for the prefixes for the current instruction. See below. */
129 static int prefixes;
130
131 /* REX prefix the current instruction. See below. */
132 static int rex;
133 /* Bits of REX we've already used. */
134 static int rex_used;
135 /* Mark parts used in the REX prefix. When we are testing for
136 empty prefix (for 8bit register REX extension), just mask it
137 out. Otherwise test for REX bit is excuse for existence of REX
138 only in case value is nonzero. */
139 #define USED_REX(value) \
140 { \
141 if (value) \
142 { \
143 if ((rex & value)) \
144 rex_used |= (value) | REX_OPCODE; \
145 } \
146 else \
147 rex_used |= REX_OPCODE; \
148 }
149
150 /* Special 'registers' for DREX handling */
151 #define DREX_REG_UNKNOWN 1000 /* not initialized */
152 #define DREX_REG_MEMORY 1001 /* use MODRM/SIB/OFFSET memory */
153
154 /* The DREX byte has the following fields:
155 Bits 7-4 -- DREX.Dest, xmm destination register
156 Bit 3 -- DREX.OC0, operand config bit defines operand order
157 Bit 2 -- DREX.R, equivalent to REX_R bit, to extend ModRM register
158 Bit 1 -- DREX.X, equivalent to REX_X bit, to extend SIB index field
159 Bit 0 -- DREX.W, equivalent to REX_B bit, to extend ModRM r/m field,
160 SIB base field, or opcode reg field. */
161 #define DREX_XMM(drex) ((drex >> 4) & 0xf)
162 #define DREX_OC0(drex) ((drex >> 3) & 0x1)
163
164 /* Flags for prefixes which we somehow handled when printing the
165 current instruction. */
166 static int used_prefixes;
167
168 /* Flags stored in PREFIXES. */
169 #define PREFIX_REPZ 1
170 #define PREFIX_REPNZ 2
171 #define PREFIX_LOCK 4
172 #define PREFIX_CS 8
173 #define PREFIX_SS 0x10
174 #define PREFIX_DS 0x20
175 #define PREFIX_ES 0x40
176 #define PREFIX_FS 0x80
177 #define PREFIX_GS 0x100
178 #define PREFIX_DATA 0x200
179 #define PREFIX_ADDR 0x400
180 #define PREFIX_FWAIT 0x800
181
182 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
183 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
184 on error. */
185 #define FETCH_DATA(info, addr) \
186 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
187 ? 1 : fetch_data ((info), (addr)))
188
189 static int
190 fetch_data (struct disassemble_info *info, bfd_byte *addr)
191 {
192 int status;
193 struct dis_private *priv = (struct dis_private *) info->private_data;
194 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
195
196 if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
197 status = (*info->read_memory_func) (start,
198 priv->max_fetched,
199 addr - priv->max_fetched,
200 info);
201 else
202 status = -1;
203 if (status != 0)
204 {
205 /* If we did manage to read at least one byte, then
206 print_insn_i386 will do something sensible. Otherwise, print
207 an error. We do that here because this is where we know
208 STATUS. */
209 if (priv->max_fetched == priv->the_buffer)
210 (*info->memory_error_func) (status, start, info);
211 longjmp (priv->bailout, 1);
212 }
213 else
214 priv->max_fetched = addr;
215 return 1;
216 }
217
218 #define XX { NULL, 0 }
219
220 #define Eb { OP_E, b_mode }
221 #define Ev { OP_E, v_mode }
222 #define Ed { OP_E, d_mode }
223 #define Edq { OP_E, dq_mode }
224 #define Edqw { OP_E, dqw_mode }
225 #define Edqb { OP_E, dqb_mode }
226 #define Edqd { OP_E, dqd_mode }
227 #define Eq { OP_E, q_mode }
228 #define indirEv { OP_indirE, stack_v_mode }
229 #define indirEp { OP_indirE, f_mode }
230 #define stackEv { OP_E, stack_v_mode }
231 #define Em { OP_E, m_mode }
232 #define Ew { OP_E, w_mode }
233 #define M { OP_M, 0 } /* lea, lgdt, etc. */
234 #define Ma { OP_M, v_mode }
235 #define Mb { OP_M, b_mode }
236 #define Md { OP_M, d_mode }
237 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
238 #define Mq { OP_M, q_mode }
239 #define Gb { OP_G, b_mode }
240 #define Gv { OP_G, v_mode }
241 #define Gd { OP_G, d_mode }
242 #define Gdq { OP_G, dq_mode }
243 #define Gm { OP_G, m_mode }
244 #define Gw { OP_G, w_mode }
245 #define Rd { OP_R, d_mode }
246 #define Rm { OP_R, m_mode }
247 #define Ib { OP_I, b_mode }
248 #define sIb { OP_sI, b_mode } /* sign extened byte */
249 #define Iv { OP_I, v_mode }
250 #define Iq { OP_I, q_mode }
251 #define Iv64 { OP_I64, v_mode }
252 #define Iw { OP_I, w_mode }
253 #define I1 { OP_I, const_1_mode }
254 #define Jb { OP_J, b_mode }
255 #define Jv { OP_J, v_mode }
256 #define Cm { OP_C, m_mode }
257 #define Dm { OP_D, m_mode }
258 #define Td { OP_T, d_mode }
259 #define Skip_MODRM { OP_Skip_MODRM, 0 }
260
261 #define RMeAX { OP_REG, eAX_reg }
262 #define RMeBX { OP_REG, eBX_reg }
263 #define RMeCX { OP_REG, eCX_reg }
264 #define RMeDX { OP_REG, eDX_reg }
265 #define RMeSP { OP_REG, eSP_reg }
266 #define RMeBP { OP_REG, eBP_reg }
267 #define RMeSI { OP_REG, eSI_reg }
268 #define RMeDI { OP_REG, eDI_reg }
269 #define RMrAX { OP_REG, rAX_reg }
270 #define RMrBX { OP_REG, rBX_reg }
271 #define RMrCX { OP_REG, rCX_reg }
272 #define RMrDX { OP_REG, rDX_reg }
273 #define RMrSP { OP_REG, rSP_reg }
274 #define RMrBP { OP_REG, rBP_reg }
275 #define RMrSI { OP_REG, rSI_reg }
276 #define RMrDI { OP_REG, rDI_reg }
277 #define RMAL { OP_REG, al_reg }
278 #define RMAL { OP_REG, al_reg }
279 #define RMCL { OP_REG, cl_reg }
280 #define RMDL { OP_REG, dl_reg }
281 #define RMBL { OP_REG, bl_reg }
282 #define RMAH { OP_REG, ah_reg }
283 #define RMCH { OP_REG, ch_reg }
284 #define RMDH { OP_REG, dh_reg }
285 #define RMBH { OP_REG, bh_reg }
286 #define RMAX { OP_REG, ax_reg }
287 #define RMDX { OP_REG, dx_reg }
288
289 #define eAX { OP_IMREG, eAX_reg }
290 #define eBX { OP_IMREG, eBX_reg }
291 #define eCX { OP_IMREG, eCX_reg }
292 #define eDX { OP_IMREG, eDX_reg }
293 #define eSP { OP_IMREG, eSP_reg }
294 #define eBP { OP_IMREG, eBP_reg }
295 #define eSI { OP_IMREG, eSI_reg }
296 #define eDI { OP_IMREG, eDI_reg }
297 #define AL { OP_IMREG, al_reg }
298 #define CL { OP_IMREG, cl_reg }
299 #define DL { OP_IMREG, dl_reg }
300 #define BL { OP_IMREG, bl_reg }
301 #define AH { OP_IMREG, ah_reg }
302 #define CH { OP_IMREG, ch_reg }
303 #define DH { OP_IMREG, dh_reg }
304 #define BH { OP_IMREG, bh_reg }
305 #define AX { OP_IMREG, ax_reg }
306 #define DX { OP_IMREG, dx_reg }
307 #define zAX { OP_IMREG, z_mode_ax_reg }
308 #define indirDX { OP_IMREG, indir_dx_reg }
309
310 #define Sw { OP_SEG, w_mode }
311 #define Sv { OP_SEG, v_mode }
312 #define Ap { OP_DIR, 0 }
313 #define Ob { OP_OFF64, b_mode }
314 #define Ov { OP_OFF64, v_mode }
315 #define Xb { OP_DSreg, eSI_reg }
316 #define Xv { OP_DSreg, eSI_reg }
317 #define Xz { OP_DSreg, eSI_reg }
318 #define Yb { OP_ESreg, eDI_reg }
319 #define Yv { OP_ESreg, eDI_reg }
320 #define DSBX { OP_DSreg, eBX_reg }
321
322 #define es { OP_REG, es_reg }
323 #define ss { OP_REG, ss_reg }
324 #define cs { OP_REG, cs_reg }
325 #define ds { OP_REG, ds_reg }
326 #define fs { OP_REG, fs_reg }
327 #define gs { OP_REG, gs_reg }
328
329 #define MX { OP_MMX, 0 }
330 #define XM { OP_XMM, 0 }
331 #define EM { OP_EM, v_mode }
332 #define EMd { OP_EM, d_mode }
333 #define EMx { OP_EM, x_mode }
334 #define EXw { OP_EX, w_mode }
335 #define EXd { OP_EX, d_mode }
336 #define EXq { OP_EX, q_mode }
337 #define EXx { OP_EX, x_mode }
338 #define MS { OP_MS, v_mode }
339 #define XS { OP_XS, v_mode }
340 #define EMCq { OP_EMC, q_mode }
341 #define MXC { OP_MXC, 0 }
342 #define OPSUF { OP_3DNowSuffix, 0 }
343 #define CMP { CMP_Fixup, 0 }
344 #define XMM0 { XMM_Fixup, 0 }
345
346 /* Used handle "rep" prefix for string instructions. */
347 #define Xbr { REP_Fixup, eSI_reg }
348 #define Xvr { REP_Fixup, eSI_reg }
349 #define Ybr { REP_Fixup, eDI_reg }
350 #define Yvr { REP_Fixup, eDI_reg }
351 #define Yzr { REP_Fixup, eDI_reg }
352 #define indirDXr { REP_Fixup, indir_dx_reg }
353 #define ALr { REP_Fixup, al_reg }
354 #define eAXr { REP_Fixup, eAX_reg }
355
356 #define cond_jump_flag { NULL, cond_jump_mode }
357 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
358
359 /* bits in sizeflag */
360 #define SUFFIX_ALWAYS 4
361 #define AFLAG 2
362 #define DFLAG 1
363
364 /* byte operand */
365 #define b_mode 1
366 /* operand size depends on prefixes */
367 #define v_mode (b_mode + 1)
368 /* word operand */
369 #define w_mode (v_mode + 1)
370 /* double word operand */
371 #define d_mode (w_mode + 1)
372 /* quad word operand */
373 #define q_mode (d_mode + 1)
374 /* ten-byte operand */
375 #define t_mode (q_mode + 1)
376 /* 16-byte XMM operand */
377 #define x_mode (t_mode + 1)
378 /* d_mode in 32bit, q_mode in 64bit mode. */
379 #define m_mode (x_mode + 1)
380 #define cond_jump_mode (m_mode + 1)
381 #define loop_jcxz_mode (cond_jump_mode + 1)
382 /* operand size depends on REX prefixes. */
383 #define dq_mode (loop_jcxz_mode + 1)
384 /* registers like dq_mode, memory like w_mode. */
385 #define dqw_mode (dq_mode + 1)
386 /* 4- or 6-byte pointer operand */
387 #define f_mode (dqw_mode + 1)
388 #define const_1_mode (f_mode + 1)
389 /* v_mode for stack-related opcodes. */
390 #define stack_v_mode (const_1_mode + 1)
391 /* non-quad operand size depends on prefixes */
392 #define z_mode (stack_v_mode + 1)
393 /* 16-byte operand */
394 #define o_mode (z_mode + 1)
395 /* registers like dq_mode, memory like b_mode. */
396 #define dqb_mode (o_mode + 1)
397 /* registers like dq_mode, memory like d_mode. */
398 #define dqd_mode (dqb_mode + 1)
399
400 #define es_reg (dqd_mode + 1)
401 #define cs_reg (es_reg + 1)
402 #define ss_reg (cs_reg + 1)
403 #define ds_reg (ss_reg + 1)
404 #define fs_reg (ds_reg + 1)
405 #define gs_reg (fs_reg + 1)
406
407 #define eAX_reg (gs_reg + 1)
408 #define eCX_reg (eAX_reg + 1)
409 #define eDX_reg (eCX_reg + 1)
410 #define eBX_reg (eDX_reg + 1)
411 #define eSP_reg (eBX_reg + 1)
412 #define eBP_reg (eSP_reg + 1)
413 #define eSI_reg (eBP_reg + 1)
414 #define eDI_reg (eSI_reg + 1)
415
416 #define al_reg (eDI_reg + 1)
417 #define cl_reg (al_reg + 1)
418 #define dl_reg (cl_reg + 1)
419 #define bl_reg (dl_reg + 1)
420 #define ah_reg (bl_reg + 1)
421 #define ch_reg (ah_reg + 1)
422 #define dh_reg (ch_reg + 1)
423 #define bh_reg (dh_reg + 1)
424
425 #define ax_reg (bh_reg + 1)
426 #define cx_reg (ax_reg + 1)
427 #define dx_reg (cx_reg + 1)
428 #define bx_reg (dx_reg + 1)
429 #define sp_reg (bx_reg + 1)
430 #define bp_reg (sp_reg + 1)
431 #define si_reg (bp_reg + 1)
432 #define di_reg (si_reg + 1)
433
434 #define rAX_reg (di_reg + 1)
435 #define rCX_reg (rAX_reg + 1)
436 #define rDX_reg (rCX_reg + 1)
437 #define rBX_reg (rDX_reg + 1)
438 #define rSP_reg (rBX_reg + 1)
439 #define rBP_reg (rSP_reg + 1)
440 #define rSI_reg (rBP_reg + 1)
441 #define rDI_reg (rSI_reg + 1)
442
443 #define z_mode_ax_reg (rDI_reg + 1)
444 #define indir_dx_reg (z_mode_ax_reg + 1)
445
446 #define MAX_BYTEMODE indir_dx_reg
447
448 /* Flags that are OR'ed into the bytemode field to pass extra
449 information. */
450 #define DREX_OC1 0x10000 /* OC1 bit set */
451 #define DREX_NO_OC0 0x20000 /* OC0 bit not used */
452 #define DREX_MASK 0x40000 /* mask to delete */
453
454 #if MAX_BYTEMODE >= DREX_OC1
455 #error MAX_BYTEMODE must be less than DREX_OC1
456 #endif
457
458 #define FLOATCODE 1
459 #define USE_REG_TABLE (FLOATCODE + 1)
460 #define USE_MOD_TABLE (USE_REG_TABLE + 1)
461 #define USE_RM_TABLE (USE_MOD_TABLE + 1)
462 #define USE_PREFIX_TABLE (USE_RM_TABLE + 1)
463 #define USE_X86_64_TABLE (USE_PREFIX_TABLE + 1)
464 #define USE_3BYTE_TABLE (USE_X86_64_TABLE + 1)
465
466 #define FLOAT NULL, { { NULL, FLOATCODE } }
467
468 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }
469 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
470 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
471 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
472 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
473 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
474 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
475
476 #define REG_80 0
477 #define REG_81 (REG_80 + 1)
478 #define REG_82 (REG_81 + 1)
479 #define REG_8F (REG_82 + 1)
480 #define REG_C0 (REG_8F + 1)
481 #define REG_C1 (REG_C0 + 1)
482 #define REG_C6 (REG_C1 + 1)
483 #define REG_C7 (REG_C6 + 1)
484 #define REG_D0 (REG_C7 + 1)
485 #define REG_D1 (REG_D0 + 1)
486 #define REG_D2 (REG_D1 + 1)
487 #define REG_D3 (REG_D2 + 1)
488 #define REG_F6 (REG_D3 + 1)
489 #define REG_F7 (REG_F6 + 1)
490 #define REG_FE (REG_F7 + 1)
491 #define REG_FF (REG_FE + 1)
492 #define REG_0F00 (REG_FF + 1)
493 #define REG_0F01 (REG_0F00 + 1)
494 #define REG_0F0E (REG_0F01 + 1)
495 #define REG_0F18 (REG_0F0E + 1)
496 #define REG_0F71 (REG_0F18 + 1)
497 #define REG_0F72 (REG_0F71 + 1)
498 #define REG_0F73 (REG_0F72 + 1)
499 #define REG_0FA6 (REG_0F73 + 1)
500 #define REG_0FA7 (REG_0FA6 + 1)
501 #define REG_0FAE (REG_0FA7 + 1)
502 #define REG_0FBA (REG_0FAE + 1)
503 #define REG_0FC7 (REG_0FBA + 1)
504
505 #define MOD_8D 0
506 #define MOD_0F01_REG_0 (MOD_8D + 1)
507 #define MOD_0F01_REG_1 (MOD_0F01_REG_0 + 1)
508 #define MOD_0F01_REG_2 (MOD_0F01_REG_1 + 1)
509 #define MOD_0F01_REG_3 (MOD_0F01_REG_2 + 1)
510 #define MOD_0F01_REG_7 (MOD_0F01_REG_3 + 1)
511 #define MOD_0F12_PREFIX_0 (MOD_0F01_REG_7 + 1)
512 #define MOD_0F13 (MOD_0F12_PREFIX_0 + 1)
513 #define MOD_0F16_PREFIX_0 (MOD_0F13 + 1)
514 #define MOD_0F17 (MOD_0F16_PREFIX_0 + 1)
515 #define MOD_0F18_REG_0 (MOD_0F17 + 1)
516 #define MOD_0F18_REG_1 (MOD_0F18_REG_0 + 1)
517 #define MOD_0F18_REG_2 (MOD_0F18_REG_1 + 1)
518 #define MOD_0F18_REG_3 (MOD_0F18_REG_2 + 1)
519 #define MOD_0F20 (MOD_0F18_REG_3 + 1)
520 #define MOD_0F21 (MOD_0F20 + 1)
521 #define MOD_0F22 (MOD_0F21 + 1)
522 #define MOD_0F23 (MOD_0F22 + 1)
523 #define MOD_0F24 (MOD_0F23 + 1)
524 #define MOD_0F26 (MOD_0F24 + 1)
525 #define MOD_0F2B_PREFIX_0 (MOD_0F26 + 1)
526 #define MOD_0F2B_PREFIX_1 (MOD_0F2B_PREFIX_0 + 1)
527 #define MOD_0F2B_PREFIX_2 (MOD_0F2B_PREFIX_1 + 1)
528 #define MOD_0F2B_PREFIX_3 (MOD_0F2B_PREFIX_2 + 1)
529 #define MOD_0F51 (MOD_0F2B_PREFIX_3 + 1)
530 #define MOD_0F71_REG_2 (MOD_0F51 + 1)
531 #define MOD_0F71_REG_4 (MOD_0F71_REG_2 + 1)
532 #define MOD_0F71_REG_6 (MOD_0F71_REG_4 + 1)
533 #define MOD_0F72_REG_2 (MOD_0F71_REG_6 + 1)
534 #define MOD_0F72_REG_4 (MOD_0F72_REG_2 + 1)
535 #define MOD_0F72_REG_6 (MOD_0F72_REG_4 + 1)
536 #define MOD_0F73_REG_2 (MOD_0F72_REG_6 + 1)
537 #define MOD_0F73_REG_3 (MOD_0F73_REG_2 + 1)
538 #define MOD_0F73_REG_6 (MOD_0F73_REG_3 + 1)
539 #define MOD_0F73_REG_7 (MOD_0F73_REG_6 + 1)
540 #define MOD_0FAE_REG_0 (MOD_0F73_REG_7 + 1)
541 #define MOD_0FAE_REG_1 (MOD_0FAE_REG_0 + 1)
542 #define MOD_0FAE_REG_2 (MOD_0FAE_REG_1 + 1)
543 #define MOD_0FAE_REG_3 (MOD_0FAE_REG_2 + 1)
544 #define MOD_0FAE_REG_5 (MOD_0FAE_REG_3 + 1)
545 #define MOD_0FAE_REG_6 (MOD_0FAE_REG_5 + 1)
546 #define MOD_0FAE_REG_7 (MOD_0FAE_REG_6 + 1)
547 #define MOD_0FB2 (MOD_0FAE_REG_7 + 1)
548 #define MOD_0FB4 (MOD_0FB2 + 1)
549 #define MOD_0FB5 (MOD_0FB4 + 1)
550 #define MOD_0FC7_REG_6 (MOD_0FB5 + 1)
551 #define MOD_0FC7_REG_7 (MOD_0FC7_REG_6 + 1)
552 #define MOD_0FD7 (MOD_0FC7_REG_7 + 1)
553 #define MOD_0FE7_PREFIX_2 (MOD_0FD7 + 1)
554 #define MOD_0FF0_PREFIX_3 (MOD_0FE7_PREFIX_2 + 1)
555 #define MOD_0F382A_PREFIX_2 (MOD_0FF0_PREFIX_3 + 1)
556 #define MOD_62_32BIT (MOD_0F382A_PREFIX_2 + 1)
557 #define MOD_C4_32BIT (MOD_62_32BIT + 1)
558 #define MOD_C5_32BIT (MOD_C4_32BIT + 1)
559
560 #define RM_0F01_REG_0 0
561 #define RM_0F01_REG_1 (RM_0F01_REG_0 + 1)
562 #define RM_0F01_REG_3 (RM_0F01_REG_1 + 1)
563 #define RM_0F01_REG_7 (RM_0F01_REG_3 + 1)
564 #define RM_0FAE_REG_5 (RM_0F01_REG_7 + 1)
565 #define RM_0FAE_REG_6 (RM_0FAE_REG_5 + 1)
566 #define RM_0FAE_REG_7 (RM_0FAE_REG_6 + 1)
567
568 #define PREFIX_90 0
569 #define PREFIX_0F10 (PREFIX_90 + 1)
570 #define PREFIX_0F11 (PREFIX_0F10 + 1)
571 #define PREFIX_0F12 (PREFIX_0F11 + 1)
572 #define PREFIX_0F16 (PREFIX_0F12 + 1)
573 #define PREFIX_0F2A (PREFIX_0F16 + 1)
574 #define PREFIX_0F2B (PREFIX_0F2A + 1)
575 #define PREFIX_0F2C (PREFIX_0F2B + 1)
576 #define PREFIX_0F2D (PREFIX_0F2C + 1)
577 #define PREFIX_0F2E (PREFIX_0F2D + 1)
578 #define PREFIX_0F2F (PREFIX_0F2E + 1)
579 #define PREFIX_0F51 (PREFIX_0F2F + 1)
580 #define PREFIX_0F52 (PREFIX_0F51 + 1)
581 #define PREFIX_0F53 (PREFIX_0F52 + 1)
582 #define PREFIX_0F58 (PREFIX_0F53 + 1)
583 #define PREFIX_0F59 (PREFIX_0F58 + 1)
584 #define PREFIX_0F5A (PREFIX_0F59 + 1)
585 #define PREFIX_0F5B (PREFIX_0F5A + 1)
586 #define PREFIX_0F5C (PREFIX_0F5B + 1)
587 #define PREFIX_0F5D (PREFIX_0F5C + 1)
588 #define PREFIX_0F5E (PREFIX_0F5D + 1)
589 #define PREFIX_0F5F (PREFIX_0F5E + 1)
590 #define PREFIX_0F60 (PREFIX_0F5F + 1)
591 #define PREFIX_0F61 (PREFIX_0F60 + 1)
592 #define PREFIX_0F62 (PREFIX_0F61 + 1)
593 #define PREFIX_0F6C (PREFIX_0F62 + 1)
594 #define PREFIX_0F6D (PREFIX_0F6C + 1)
595 #define PREFIX_0F6F (PREFIX_0F6D + 1)
596 #define PREFIX_0F70 (PREFIX_0F6F + 1)
597 #define PREFIX_0F73_REG_3 (PREFIX_0F70 + 1)
598 #define PREFIX_0F73_REG_7 (PREFIX_0F73_REG_3 + 1)
599 #define PREFIX_0F78 (PREFIX_0F73_REG_7 + 1)
600 #define PREFIX_0F79 (PREFIX_0F78 + 1)
601 #define PREFIX_0F7C (PREFIX_0F79 + 1)
602 #define PREFIX_0F7D (PREFIX_0F7C + 1)
603 #define PREFIX_0F7E (PREFIX_0F7D + 1)
604 #define PREFIX_0F7F (PREFIX_0F7E + 1)
605 #define PREFIX_0FB8 (PREFIX_0F7F + 1)
606 #define PREFIX_0FBD (PREFIX_0FB8 + 1)
607 #define PREFIX_0FC2 (PREFIX_0FBD + 1)
608 #define PREFIX_0FC7_REG_6 (PREFIX_0FC2 + 1)
609 #define PREFIX_0FD0 (PREFIX_0FC7_REG_6 + 1)
610 #define PREFIX_0FD6 (PREFIX_0FD0 + 1)
611 #define PREFIX_0FE6 (PREFIX_0FD6 + 1)
612 #define PREFIX_0FE7 (PREFIX_0FE6 + 1)
613 #define PREFIX_0FF0 (PREFIX_0FE7 + 1)
614 #define PREFIX_0FF7 (PREFIX_0FF0 + 1)
615 #define PREFIX_0F3810 (PREFIX_0FF7 + 1)
616 #define PREFIX_0F3814 (PREFIX_0F3810 + 1)
617 #define PREFIX_0F3815 (PREFIX_0F3814 + 1)
618 #define PREFIX_0F3817 (PREFIX_0F3815 + 1)
619 #define PREFIX_0F3820 (PREFIX_0F3817 + 1)
620 #define PREFIX_0F3821 (PREFIX_0F3820 + 1)
621 #define PREFIX_0F3822 (PREFIX_0F3821 + 1)
622 #define PREFIX_0F3823 (PREFIX_0F3822 + 1)
623 #define PREFIX_0F3824 (PREFIX_0F3823 + 1)
624 #define PREFIX_0F3825 (PREFIX_0F3824 + 1)
625 #define PREFIX_0F3828 (PREFIX_0F3825 + 1)
626 #define PREFIX_0F3829 (PREFIX_0F3828 + 1)
627 #define PREFIX_0F382A (PREFIX_0F3829 + 1)
628 #define PREFIX_0F382B (PREFIX_0F382A + 1)
629 #define PREFIX_0F3830 (PREFIX_0F382B + 1)
630 #define PREFIX_0F3831 (PREFIX_0F3830 + 1)
631 #define PREFIX_0F3832 (PREFIX_0F3831 + 1)
632 #define PREFIX_0F3833 (PREFIX_0F3832 + 1)
633 #define PREFIX_0F3834 (PREFIX_0F3833 + 1)
634 #define PREFIX_0F3835 (PREFIX_0F3834 + 1)
635 #define PREFIX_0F3837 (PREFIX_0F3835 + 1)
636 #define PREFIX_0F3838 (PREFIX_0F3837 + 1)
637 #define PREFIX_0F3839 (PREFIX_0F3838 + 1)
638 #define PREFIX_0F383A (PREFIX_0F3839 + 1)
639 #define PREFIX_0F383B (PREFIX_0F383A + 1)
640 #define PREFIX_0F383C (PREFIX_0F383B + 1)
641 #define PREFIX_0F383D (PREFIX_0F383C + 1)
642 #define PREFIX_0F383E (PREFIX_0F383D + 1)
643 #define PREFIX_0F383F (PREFIX_0F383E + 1)
644 #define PREFIX_0F3840 (PREFIX_0F383F + 1)
645 #define PREFIX_0F3841 (PREFIX_0F3840 + 1)
646 #define PREFIX_0F38F0 (PREFIX_0F3841 + 1)
647 #define PREFIX_0F38F1 (PREFIX_0F38F0 + 1)
648 #define PREFIX_0F3A08 (PREFIX_0F38F1 + 1)
649 #define PREFIX_0F3A09 (PREFIX_0F3A08 + 1)
650 #define PREFIX_0F3A0A (PREFIX_0F3A09 + 1)
651 #define PREFIX_0F3A0B (PREFIX_0F3A0A + 1)
652 #define PREFIX_0F3A0C (PREFIX_0F3A0B + 1)
653 #define PREFIX_0F3A0D (PREFIX_0F3A0C + 1)
654 #define PREFIX_0F3A0E (PREFIX_0F3A0D + 1)
655 #define PREFIX_0F3A14 (PREFIX_0F3A0E + 1)
656 #define PREFIX_0F3A15 (PREFIX_0F3A14 + 1)
657 #define PREFIX_0F3A16 (PREFIX_0F3A15 + 1)
658 #define PREFIX_0F3A17 (PREFIX_0F3A16 + 1)
659 #define PREFIX_0F3A20 (PREFIX_0F3A17 + 1)
660 #define PREFIX_0F3A21 (PREFIX_0F3A20 + 1)
661 #define PREFIX_0F3A22 (PREFIX_0F3A21 + 1)
662 #define PREFIX_0F3A40 (PREFIX_0F3A22 + 1)
663 #define PREFIX_0F3A41 (PREFIX_0F3A40 + 1)
664 #define PREFIX_0F3A42 (PREFIX_0F3A41 + 1)
665 #define PREFIX_0F3A60 (PREFIX_0F3A42 + 1)
666 #define PREFIX_0F3A61 (PREFIX_0F3A60 + 1)
667 #define PREFIX_0F3A62 (PREFIX_0F3A61 + 1)
668 #define PREFIX_0F3A63 (PREFIX_0F3A62 + 1)
669
670 #define X86_64_06 0
671 #define X86_64_07 (X86_64_06 + 1)
672 #define X86_64_0D (X86_64_07 + 1)
673 #define X86_64_16 (X86_64_0D + 1)
674 #define X86_64_17 (X86_64_16 + 1)
675 #define X86_64_1E (X86_64_17 + 1)
676 #define X86_64_1F (X86_64_1E + 1)
677 #define X86_64_27 (X86_64_1F + 1)
678 #define X86_64_2F (X86_64_27 + 1)
679 #define X86_64_37 (X86_64_2F + 1)
680 #define X86_64_3F (X86_64_37 + 1)
681 #define X86_64_60 (X86_64_3F + 1)
682 #define X86_64_61 (X86_64_60 + 1)
683 #define X86_64_62 (X86_64_61 + 1)
684 #define X86_64_63 (X86_64_62 + 1)
685 #define X86_64_6D (X86_64_63 + 1)
686 #define X86_64_6F (X86_64_6D + 1)
687 #define X86_64_9A (X86_64_6F + 1)
688 #define X86_64_C4 (X86_64_9A + 1)
689 #define X86_64_C5 (X86_64_C4 + 1)
690 #define X86_64_CE (X86_64_C5 + 1)
691 #define X86_64_D4 (X86_64_CE + 1)
692 #define X86_64_D5 (X86_64_D4 + 1)
693 #define X86_64_EA (X86_64_D5 + 1)
694 #define X86_64_0F01_REG_0 (X86_64_EA + 1)
695 #define X86_64_0F01_REG_1 (X86_64_0F01_REG_0 + 1)
696 #define X86_64_0F01_REG_2 (X86_64_0F01_REG_1 + 1)
697 #define X86_64_0F01_REG_3 (X86_64_0F01_REG_2 + 1)
698
699 #define THREE_BYTE_0F24 0
700 #define THREE_BYTE_0F25 (THREE_BYTE_0F24 + 1)
701 #define THREE_BYTE_0F38 (THREE_BYTE_0F25 + 1)
702 #define THREE_BYTE_0F3A (THREE_BYTE_0F38 + 1)
703 #define THREE_BYTE_0F7A (THREE_BYTE_0F3A + 1)
704 #define THREE_BYTE_0F7B (THREE_BYTE_0F7A + 1)
705
706 typedef void (*op_rtn) (int bytemode, int sizeflag);
707
708 struct dis386 {
709 const char *name;
710 struct
711 {
712 op_rtn rtn;
713 int bytemode;
714 } op[MAX_OPERANDS];
715 };
716
717 /* Upper case letters in the instruction names here are macros.
718 'A' => print 'b' if no register operands or suffix_always is true
719 'B' => print 'b' if suffix_always is true
720 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
721 . size prefix
722 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
723 . suffix_always is true
724 'E' => print 'e' if 32-bit form of jcxz
725 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
726 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
727 'H' => print ",pt" or ",pn" branch hint
728 'I' => honor following macro letter even in Intel mode (implemented only
729 . for some of the macro letters)
730 'J' => print 'l'
731 'K' => print 'd' or 'q' if rex prefix is present.
732 'L' => print 'l' if suffix_always is true
733 'N' => print 'n' if instruction has no wait "prefix"
734 'O' => print 'd' or 'o' (or 'q' in Intel mode)
735 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
736 . or suffix_always is true. print 'q' if rex prefix is present.
737 'Q' => print 'w', 'l' or 'q' if no register operands or suffix_always
738 . is true
739 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
740 'S' => print 'w', 'l' or 'q' if suffix_always is true
741 'T' => print 'q' in 64bit mode and behave as 'P' otherwise
742 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
743 'V' => print 'q' in 64bit mode and behave as 'S' otherwise
744 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
745 'X' => print 's', 'd' depending on data16 prefix (for XMM)
746 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
747 suffix_always is true.
748 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
749
750 Many of the above letters print nothing in Intel mode. See "putop"
751 for the details.
752
753 Braces '{' and '}', and vertical bars '|', indicate alternative
754 mnemonic strings for AT&T and Intel. */
755
756 static const struct dis386 dis386[] = {
757 /* 00 */
758 { "addB", { Eb, Gb } },
759 { "addS", { Ev, Gv } },
760 { "addB", { Gb, Eb } },
761 { "addS", { Gv, Ev } },
762 { "addB", { AL, Ib } },
763 { "addS", { eAX, Iv } },
764 { X86_64_TABLE (X86_64_06) },
765 { X86_64_TABLE (X86_64_07) },
766 /* 08 */
767 { "orB", { Eb, Gb } },
768 { "orS", { Ev, Gv } },
769 { "orB", { Gb, Eb } },
770 { "orS", { Gv, Ev } },
771 { "orB", { AL, Ib } },
772 { "orS", { eAX, Iv } },
773 { X86_64_TABLE (X86_64_0D) },
774 { "(bad)", { XX } }, /* 0x0f extended opcode escape */
775 /* 10 */
776 { "adcB", { Eb, Gb } },
777 { "adcS", { Ev, Gv } },
778 { "adcB", { Gb, Eb } },
779 { "adcS", { Gv, Ev } },
780 { "adcB", { AL, Ib } },
781 { "adcS", { eAX, Iv } },
782 { X86_64_TABLE (X86_64_16) },
783 { X86_64_TABLE (X86_64_17) },
784 /* 18 */
785 { "sbbB", { Eb, Gb } },
786 { "sbbS", { Ev, Gv } },
787 { "sbbB", { Gb, Eb } },
788 { "sbbS", { Gv, Ev } },
789 { "sbbB", { AL, Ib } },
790 { "sbbS", { eAX, Iv } },
791 { X86_64_TABLE (X86_64_1E) },
792 { X86_64_TABLE (X86_64_1F) },
793 /* 20 */
794 { "andB", { Eb, Gb } },
795 { "andS", { Ev, Gv } },
796 { "andB", { Gb, Eb } },
797 { "andS", { Gv, Ev } },
798 { "andB", { AL, Ib } },
799 { "andS", { eAX, Iv } },
800 { "(bad)", { XX } }, /* SEG ES prefix */
801 { X86_64_TABLE (X86_64_27) },
802 /* 28 */
803 { "subB", { Eb, Gb } },
804 { "subS", { Ev, Gv } },
805 { "subB", { Gb, Eb } },
806 { "subS", { Gv, Ev } },
807 { "subB", { AL, Ib } },
808 { "subS", { eAX, Iv } },
809 { "(bad)", { XX } }, /* SEG CS prefix */
810 { X86_64_TABLE (X86_64_2F) },
811 /* 30 */
812 { "xorB", { Eb, Gb } },
813 { "xorS", { Ev, Gv } },
814 { "xorB", { Gb, Eb } },
815 { "xorS", { Gv, Ev } },
816 { "xorB", { AL, Ib } },
817 { "xorS", { eAX, Iv } },
818 { "(bad)", { XX } }, /* SEG SS prefix */
819 { X86_64_TABLE (X86_64_37) },
820 /* 38 */
821 { "cmpB", { Eb, Gb } },
822 { "cmpS", { Ev, Gv } },
823 { "cmpB", { Gb, Eb } },
824 { "cmpS", { Gv, Ev } },
825 { "cmpB", { AL, Ib } },
826 { "cmpS", { eAX, Iv } },
827 { "(bad)", { XX } }, /* SEG DS prefix */
828 { X86_64_TABLE (X86_64_3F) },
829 /* 40 */
830 { "inc{S|}", { RMeAX } },
831 { "inc{S|}", { RMeCX } },
832 { "inc{S|}", { RMeDX } },
833 { "inc{S|}", { RMeBX } },
834 { "inc{S|}", { RMeSP } },
835 { "inc{S|}", { RMeBP } },
836 { "inc{S|}", { RMeSI } },
837 { "inc{S|}", { RMeDI } },
838 /* 48 */
839 { "dec{S|}", { RMeAX } },
840 { "dec{S|}", { RMeCX } },
841 { "dec{S|}", { RMeDX } },
842 { "dec{S|}", { RMeBX } },
843 { "dec{S|}", { RMeSP } },
844 { "dec{S|}", { RMeBP } },
845 { "dec{S|}", { RMeSI } },
846 { "dec{S|}", { RMeDI } },
847 /* 50 */
848 { "pushV", { RMrAX } },
849 { "pushV", { RMrCX } },
850 { "pushV", { RMrDX } },
851 { "pushV", { RMrBX } },
852 { "pushV", { RMrSP } },
853 { "pushV", { RMrBP } },
854 { "pushV", { RMrSI } },
855 { "pushV", { RMrDI } },
856 /* 58 */
857 { "popV", { RMrAX } },
858 { "popV", { RMrCX } },
859 { "popV", { RMrDX } },
860 { "popV", { RMrBX } },
861 { "popV", { RMrSP } },
862 { "popV", { RMrBP } },
863 { "popV", { RMrSI } },
864 { "popV", { RMrDI } },
865 /* 60 */
866 { X86_64_TABLE (X86_64_60) },
867 { X86_64_TABLE (X86_64_61) },
868 { X86_64_TABLE (X86_64_62) },
869 { X86_64_TABLE (X86_64_63) },
870 { "(bad)", { XX } }, /* seg fs */
871 { "(bad)", { XX } }, /* seg gs */
872 { "(bad)", { XX } }, /* op size prefix */
873 { "(bad)", { XX } }, /* adr size prefix */
874 /* 68 */
875 { "pushT", { Iq } },
876 { "imulS", { Gv, Ev, Iv } },
877 { "pushT", { sIb } },
878 { "imulS", { Gv, Ev, sIb } },
879 { "ins{b|}", { Ybr, indirDX } },
880 { X86_64_TABLE (X86_64_6D) },
881 { "outs{b|}", { indirDXr, Xb } },
882 { X86_64_TABLE (X86_64_6F) },
883 /* 70 */
884 { "joH", { Jb, XX, cond_jump_flag } },
885 { "jnoH", { Jb, XX, cond_jump_flag } },
886 { "jbH", { Jb, XX, cond_jump_flag } },
887 { "jaeH", { Jb, XX, cond_jump_flag } },
888 { "jeH", { Jb, XX, cond_jump_flag } },
889 { "jneH", { Jb, XX, cond_jump_flag } },
890 { "jbeH", { Jb, XX, cond_jump_flag } },
891 { "jaH", { Jb, XX, cond_jump_flag } },
892 /* 78 */
893 { "jsH", { Jb, XX, cond_jump_flag } },
894 { "jnsH", { Jb, XX, cond_jump_flag } },
895 { "jpH", { Jb, XX, cond_jump_flag } },
896 { "jnpH", { Jb, XX, cond_jump_flag } },
897 { "jlH", { Jb, XX, cond_jump_flag } },
898 { "jgeH", { Jb, XX, cond_jump_flag } },
899 { "jleH", { Jb, XX, cond_jump_flag } },
900 { "jgH", { Jb, XX, cond_jump_flag } },
901 /* 80 */
902 { REG_TABLE (REG_80) },
903 { REG_TABLE (REG_81) },
904 { "(bad)", { XX } },
905 { REG_TABLE (REG_82) },
906 { "testB", { Eb, Gb } },
907 { "testS", { Ev, Gv } },
908 { "xchgB", { Eb, Gb } },
909 { "xchgS", { Ev, Gv } },
910 /* 88 */
911 { "movB", { Eb, Gb } },
912 { "movS", { Ev, Gv } },
913 { "movB", { Gb, Eb } },
914 { "movS", { Gv, Ev } },
915 { "movD", { Sv, Sw } },
916 { MOD_TABLE (MOD_8D) },
917 { "movD", { Sw, Sv } },
918 { REG_TABLE (REG_8F) },
919 /* 90 */
920 { PREFIX_TABLE (PREFIX_90) },
921 { "xchgS", { RMeCX, eAX } },
922 { "xchgS", { RMeDX, eAX } },
923 { "xchgS", { RMeBX, eAX } },
924 { "xchgS", { RMeSP, eAX } },
925 { "xchgS", { RMeBP, eAX } },
926 { "xchgS", { RMeSI, eAX } },
927 { "xchgS", { RMeDI, eAX } },
928 /* 98 */
929 { "cW{t|}R", { XX } },
930 { "cR{t|}O", { XX } },
931 { X86_64_TABLE (X86_64_9A) },
932 { "(bad)", { XX } }, /* fwait */
933 { "pushfT", { XX } },
934 { "popfT", { XX } },
935 { "sahf", { XX } },
936 { "lahf", { XX } },
937 /* a0 */
938 { "movB", { AL, Ob } },
939 { "movS", { eAX, Ov } },
940 { "movB", { Ob, AL } },
941 { "movS", { Ov, eAX } },
942 { "movs{b|}", { Ybr, Xb } },
943 { "movs{R|}", { Yvr, Xv } },
944 { "cmps{b|}", { Xb, Yb } },
945 { "cmps{R|}", { Xv, Yv } },
946 /* a8 */
947 { "testB", { AL, Ib } },
948 { "testS", { eAX, Iv } },
949 { "stosB", { Ybr, AL } },
950 { "stosS", { Yvr, eAX } },
951 { "lodsB", { ALr, Xb } },
952 { "lodsS", { eAXr, Xv } },
953 { "scasB", { AL, Yb } },
954 { "scasS", { eAX, Yv } },
955 /* b0 */
956 { "movB", { RMAL, Ib } },
957 { "movB", { RMCL, Ib } },
958 { "movB", { RMDL, Ib } },
959 { "movB", { RMBL, Ib } },
960 { "movB", { RMAH, Ib } },
961 { "movB", { RMCH, Ib } },
962 { "movB", { RMDH, Ib } },
963 { "movB", { RMBH, Ib } },
964 /* b8 */
965 { "movS", { RMeAX, Iv64 } },
966 { "movS", { RMeCX, Iv64 } },
967 { "movS", { RMeDX, Iv64 } },
968 { "movS", { RMeBX, Iv64 } },
969 { "movS", { RMeSP, Iv64 } },
970 { "movS", { RMeBP, Iv64 } },
971 { "movS", { RMeSI, Iv64 } },
972 { "movS", { RMeDI, Iv64 } },
973 /* c0 */
974 { REG_TABLE (REG_C0) },
975 { REG_TABLE (REG_C1) },
976 { "retT", { Iw } },
977 { "retT", { XX } },
978 { X86_64_TABLE (X86_64_C4) },
979 { X86_64_TABLE (X86_64_C5) },
980 { REG_TABLE (REG_C6) },
981 { REG_TABLE (REG_C7) },
982 /* c8 */
983 { "enterT", { Iw, Ib } },
984 { "leaveT", { XX } },
985 { "lretP", { Iw } },
986 { "lretP", { XX } },
987 { "int3", { XX } },
988 { "int", { Ib } },
989 { X86_64_TABLE (X86_64_CE) },
990 { "iretP", { XX } },
991 /* d0 */
992 { REG_TABLE (REG_D0) },
993 { REG_TABLE (REG_D1) },
994 { REG_TABLE (REG_D2) },
995 { REG_TABLE (REG_D3) },
996 { X86_64_TABLE (X86_64_D4) },
997 { X86_64_TABLE (X86_64_D5) },
998 { "(bad)", { XX } },
999 { "xlat", { DSBX } },
1000 /* d8 */
1001 { FLOAT },
1002 { FLOAT },
1003 { FLOAT },
1004 { FLOAT },
1005 { FLOAT },
1006 { FLOAT },
1007 { FLOAT },
1008 { FLOAT },
1009 /* e0 */
1010 { "loopneFH", { Jb, XX, loop_jcxz_flag } },
1011 { "loopeFH", { Jb, XX, loop_jcxz_flag } },
1012 { "loopFH", { Jb, XX, loop_jcxz_flag } },
1013 { "jEcxzH", { Jb, XX, loop_jcxz_flag } },
1014 { "inB", { AL, Ib } },
1015 { "inG", { zAX, Ib } },
1016 { "outB", { Ib, AL } },
1017 { "outG", { Ib, zAX } },
1018 /* e8 */
1019 { "callT", { Jv } },
1020 { "jmpT", { Jv } },
1021 { X86_64_TABLE (X86_64_EA) },
1022 { "jmp", { Jb } },
1023 { "inB", { AL, indirDX } },
1024 { "inG", { zAX, indirDX } },
1025 { "outB", { indirDX, AL } },
1026 { "outG", { indirDX, zAX } },
1027 /* f0 */
1028 { "(bad)", { XX } }, /* lock prefix */
1029 { "icebp", { XX } },
1030 { "(bad)", { XX } }, /* repne */
1031 { "(bad)", { XX } }, /* repz */
1032 { "hlt", { XX } },
1033 { "cmc", { XX } },
1034 { REG_TABLE (REG_F6) },
1035 { REG_TABLE (REG_F7) },
1036 /* f8 */
1037 { "clc", { XX } },
1038 { "stc", { XX } },
1039 { "cli", { XX } },
1040 { "sti", { XX } },
1041 { "cld", { XX } },
1042 { "std", { XX } },
1043 { REG_TABLE (REG_FE) },
1044 { REG_TABLE (REG_FF) },
1045 };
1046
1047 static const struct dis386 dis386_twobyte[] = {
1048 /* 00 */
1049 { REG_TABLE (REG_0F00 ) },
1050 { REG_TABLE (REG_0F01 ) },
1051 { "larS", { Gv, Ew } },
1052 { "lslS", { Gv, Ew } },
1053 { "(bad)", { XX } },
1054 { "syscall", { XX } },
1055 { "clts", { XX } },
1056 { "sysretP", { XX } },
1057 /* 08 */
1058 { "invd", { XX } },
1059 { "wbinvd", { XX } },
1060 { "(bad)", { XX } },
1061 { "ud2a", { XX } },
1062 { "(bad)", { XX } },
1063 { REG_TABLE (REG_0F0E) },
1064 { "femms", { XX } },
1065 { "", { MX, EM, OPSUF } }, /* See OP_3DNowSuffix. */
1066 /* 10 */
1067 { PREFIX_TABLE (PREFIX_0F10) },
1068 { PREFIX_TABLE (PREFIX_0F11) },
1069 { PREFIX_TABLE (PREFIX_0F12) },
1070 { MOD_TABLE (MOD_0F13) },
1071 { "unpcklpX", { XM, EXx } },
1072 { "unpckhpX", { XM, EXx } },
1073 { PREFIX_TABLE (PREFIX_0F16) },
1074 { MOD_TABLE (MOD_0F17) },
1075 /* 18 */
1076 { REG_TABLE (REG_0F18) },
1077 { "(bad)", { XX } },
1078 { "(bad)", { XX } },
1079 { "(bad)", { XX } },
1080 { "(bad)", { XX } },
1081 { "(bad)", { XX } },
1082 { "(bad)", { XX } },
1083 { "nopQ", { Ev } },
1084 /* 20 */
1085 { MOD_TABLE (MOD_0F20) },
1086 { MOD_TABLE (MOD_0F21) },
1087 { MOD_TABLE (MOD_0F22) },
1088 { MOD_TABLE (MOD_0F23) },
1089 { MOD_TABLE (MOD_0F24) },
1090 { THREE_BYTE_TABLE (THREE_BYTE_0F25) },
1091 { MOD_TABLE (MOD_0F26) },
1092 { "(bad)", { XX } },
1093 /* 28 */
1094 { "movapX", { XM, EXx } },
1095 { "movapX", { EXx, XM } },
1096 { PREFIX_TABLE (PREFIX_0F2A) },
1097 { PREFIX_TABLE (PREFIX_0F2B) },
1098 { PREFIX_TABLE (PREFIX_0F2C) },
1099 { PREFIX_TABLE (PREFIX_0F2D) },
1100 { PREFIX_TABLE (PREFIX_0F2E) },
1101 { PREFIX_TABLE (PREFIX_0F2F) },
1102 /* 30 */
1103 { "wrmsr", { XX } },
1104 { "rdtsc", { XX } },
1105 { "rdmsr", { XX } },
1106 { "rdpmc", { XX } },
1107 { "sysenter", { XX } },
1108 { "sysexit", { XX } },
1109 { "(bad)", { XX } },
1110 { "getsec", { XX } },
1111 /* 38 */
1112 { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
1113 { "(bad)", { XX } },
1114 { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
1115 { "(bad)", { XX } },
1116 { "(bad)", { XX } },
1117 { "(bad)", { XX } },
1118 { "(bad)", { XX } },
1119 { "(bad)", { XX } },
1120 /* 40 */
1121 { "cmovo", { Gv, Ev } },
1122 { "cmovno", { Gv, Ev } },
1123 { "cmovb", { Gv, Ev } },
1124 { "cmovae", { Gv, Ev } },
1125 { "cmove", { Gv, Ev } },
1126 { "cmovne", { Gv, Ev } },
1127 { "cmovbe", { Gv, Ev } },
1128 { "cmova", { Gv, Ev } },
1129 /* 48 */
1130 { "cmovs", { Gv, Ev } },
1131 { "cmovns", { Gv, Ev } },
1132 { "cmovp", { Gv, Ev } },
1133 { "cmovnp", { Gv, Ev } },
1134 { "cmovl", { Gv, Ev } },
1135 { "cmovge", { Gv, Ev } },
1136 { "cmovle", { Gv, Ev } },
1137 { "cmovg", { Gv, Ev } },
1138 /* 50 */
1139 { MOD_TABLE (MOD_0F51) },
1140 { PREFIX_TABLE (PREFIX_0F51) },
1141 { PREFIX_TABLE (PREFIX_0F52) },
1142 { PREFIX_TABLE (PREFIX_0F53) },
1143 { "andpX", { XM, EXx } },
1144 { "andnpX", { XM, EXx } },
1145 { "orpX", { XM, EXx } },
1146 { "xorpX", { XM, EXx } },
1147 /* 58 */
1148 { PREFIX_TABLE (PREFIX_0F58) },
1149 { PREFIX_TABLE (PREFIX_0F59) },
1150 { PREFIX_TABLE (PREFIX_0F5A) },
1151 { PREFIX_TABLE (PREFIX_0F5B) },
1152 { PREFIX_TABLE (PREFIX_0F5C) },
1153 { PREFIX_TABLE (PREFIX_0F5D) },
1154 { PREFIX_TABLE (PREFIX_0F5E) },
1155 { PREFIX_TABLE (PREFIX_0F5F) },
1156 /* 60 */
1157 { PREFIX_TABLE (PREFIX_0F60) },
1158 { PREFIX_TABLE (PREFIX_0F61) },
1159 { PREFIX_TABLE (PREFIX_0F62) },
1160 { "packsswb", { MX, EM } },
1161 { "pcmpgtb", { MX, EM } },
1162 { "pcmpgtw", { MX, EM } },
1163 { "pcmpgtd", { MX, EM } },
1164 { "packuswb", { MX, EM } },
1165 /* 68 */
1166 { "punpckhbw", { MX, EM } },
1167 { "punpckhwd", { MX, EM } },
1168 { "punpckhdq", { MX, EM } },
1169 { "packssdw", { MX, EM } },
1170 { PREFIX_TABLE (PREFIX_0F6C) },
1171 { PREFIX_TABLE (PREFIX_0F6D) },
1172 { "movK", { MX, Edq } },
1173 { PREFIX_TABLE (PREFIX_0F6F) },
1174 /* 70 */
1175 { PREFIX_TABLE (PREFIX_0F70) },
1176 { REG_TABLE (REG_0F71) },
1177 { REG_TABLE (REG_0F72) },
1178 { REG_TABLE (REG_0F73) },
1179 { "pcmpeqb", { MX, EM } },
1180 { "pcmpeqw", { MX, EM } },
1181 { "pcmpeqd", { MX, EM } },
1182 { "emms", { XX } },
1183 /* 78 */
1184 { PREFIX_TABLE (PREFIX_0F78) },
1185 { PREFIX_TABLE (PREFIX_0F79) },
1186 { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
1187 { THREE_BYTE_TABLE (THREE_BYTE_0F7B) },
1188 { PREFIX_TABLE (PREFIX_0F7C) },
1189 { PREFIX_TABLE (PREFIX_0F7D) },
1190 { PREFIX_TABLE (PREFIX_0F7E) },
1191 { PREFIX_TABLE (PREFIX_0F7F) },
1192 /* 80 */
1193 { "joH", { Jv, XX, cond_jump_flag } },
1194 { "jnoH", { Jv, XX, cond_jump_flag } },
1195 { "jbH", { Jv, XX, cond_jump_flag } },
1196 { "jaeH", { Jv, XX, cond_jump_flag } },
1197 { "jeH", { Jv, XX, cond_jump_flag } },
1198 { "jneH", { Jv, XX, cond_jump_flag } },
1199 { "jbeH", { Jv, XX, cond_jump_flag } },
1200 { "jaH", { Jv, XX, cond_jump_flag } },
1201 /* 88 */
1202 { "jsH", { Jv, XX, cond_jump_flag } },
1203 { "jnsH", { Jv, XX, cond_jump_flag } },
1204 { "jpH", { Jv, XX, cond_jump_flag } },
1205 { "jnpH", { Jv, XX, cond_jump_flag } },
1206 { "jlH", { Jv, XX, cond_jump_flag } },
1207 { "jgeH", { Jv, XX, cond_jump_flag } },
1208 { "jleH", { Jv, XX, cond_jump_flag } },
1209 { "jgH", { Jv, XX, cond_jump_flag } },
1210 /* 90 */
1211 { "seto", { Eb } },
1212 { "setno", { Eb } },
1213 { "setb", { Eb } },
1214 { "setae", { Eb } },
1215 { "sete", { Eb } },
1216 { "setne", { Eb } },
1217 { "setbe", { Eb } },
1218 { "seta", { Eb } },
1219 /* 98 */
1220 { "sets", { Eb } },
1221 { "setns", { Eb } },
1222 { "setp", { Eb } },
1223 { "setnp", { Eb } },
1224 { "setl", { Eb } },
1225 { "setge", { Eb } },
1226 { "setle", { Eb } },
1227 { "setg", { Eb } },
1228 /* a0 */
1229 { "pushT", { fs } },
1230 { "popT", { fs } },
1231 { "cpuid", { XX } },
1232 { "btS", { Ev, Gv } },
1233 { "shldS", { Ev, Gv, Ib } },
1234 { "shldS", { Ev, Gv, CL } },
1235 { REG_TABLE (REG_0FA6) },
1236 { REG_TABLE (REG_0FA7) },
1237 /* a8 */
1238 { "pushT", { gs } },
1239 { "popT", { gs } },
1240 { "rsm", { XX } },
1241 { "btsS", { Ev, Gv } },
1242 { "shrdS", { Ev, Gv, Ib } },
1243 { "shrdS", { Ev, Gv, CL } },
1244 { REG_TABLE (REG_0FAE) },
1245 { "imulS", { Gv, Ev } },
1246 /* b0 */
1247 { "cmpxchgB", { Eb, Gb } },
1248 { "cmpxchgS", { Ev, Gv } },
1249 { MOD_TABLE (MOD_0FB2) },
1250 { "btrS", { Ev, Gv } },
1251 { MOD_TABLE (MOD_0FB4) },
1252 { MOD_TABLE (MOD_0FB5) },
1253 { "movz{bR|x}", { Gv, Eb } },
1254 { "movz{wR|x}", { Gv, Ew } }, /* yes, there really is movzww ! */
1255 /* b8 */
1256 { PREFIX_TABLE (PREFIX_0FB8) },
1257 { "ud2b", { XX } },
1258 { REG_TABLE (REG_0FBA) },
1259 { "btcS", { Ev, Gv } },
1260 { "bsfS", { Gv, Ev } },
1261 { PREFIX_TABLE (PREFIX_0FBD) },
1262 { "movs{bR|x}", { Gv, Eb } },
1263 { "movs{wR|x}", { Gv, Ew } }, /* yes, there really is movsww ! */
1264 /* c0 */
1265 { "xaddB", { Eb, Gb } },
1266 { "xaddS", { Ev, Gv } },
1267 { PREFIX_TABLE (PREFIX_0FC2) },
1268 { "movntiS", { Ev, Gv } },
1269 { "pinsrw", { MX, Edqw, Ib } },
1270 { "pextrw", { Gdq, MS, Ib } },
1271 { "shufpX", { XM, EXx, Ib } },
1272 { REG_TABLE (REG_0FC7) },
1273 /* c8 */
1274 { "bswap", { RMeAX } },
1275 { "bswap", { RMeCX } },
1276 { "bswap", { RMeDX } },
1277 { "bswap", { RMeBX } },
1278 { "bswap", { RMeSP } },
1279 { "bswap", { RMeBP } },
1280 { "bswap", { RMeSI } },
1281 { "bswap", { RMeDI } },
1282 /* d0 */
1283 { PREFIX_TABLE (PREFIX_0FD0) },
1284 { "psrlw", { MX, EM } },
1285 { "psrld", { MX, EM } },
1286 { "psrlq", { MX, EM } },
1287 { "paddq", { MX, EM } },
1288 { "pmullw", { MX, EM } },
1289 { PREFIX_TABLE (PREFIX_0FD6) },
1290 { MOD_TABLE (MOD_0FD7) },
1291 /* d8 */
1292 { "psubusb", { MX, EM } },
1293 { "psubusw", { MX, EM } },
1294 { "pminub", { MX, EM } },
1295 { "pand", { MX, EM } },
1296 { "paddusb", { MX, EM } },
1297 { "paddusw", { MX, EM } },
1298 { "pmaxub", { MX, EM } },
1299 { "pandn", { MX, EM } },
1300 /* e0 */
1301 { "pavgb", { MX, EM } },
1302 { "psraw", { MX, EM } },
1303 { "psrad", { MX, EM } },
1304 { "pavgw", { MX, EM } },
1305 { "pmulhuw", { MX, EM } },
1306 { "pmulhw", { MX, EM } },
1307 { PREFIX_TABLE (PREFIX_0FE6) },
1308 { PREFIX_TABLE (PREFIX_0FE7) },
1309 /* e8 */
1310 { "psubsb", { MX, EM } },
1311 { "psubsw", { MX, EM } },
1312 { "pminsw", { MX, EM } },
1313 { "por", { MX, EM } },
1314 { "paddsb", { MX, EM } },
1315 { "paddsw", { MX, EM } },
1316 { "pmaxsw", { MX, EM } },
1317 { "pxor", { MX, EM } },
1318 /* f0 */
1319 { PREFIX_TABLE (PREFIX_0FF0) },
1320 { "psllw", { MX, EM } },
1321 { "pslld", { MX, EM } },
1322 { "psllq", { MX, EM } },
1323 { "pmuludq", { MX, EM } },
1324 { "pmaddwd", { MX, EM } },
1325 { "psadbw", { MX, EM } },
1326 { PREFIX_TABLE (PREFIX_0FF7) },
1327 /* f8 */
1328 { "psubb", { MX, EM } },
1329 { "psubw", { MX, EM } },
1330 { "psubd", { MX, EM } },
1331 { "psubq", { MX, EM } },
1332 { "paddb", { MX, EM } },
1333 { "paddw", { MX, EM } },
1334 { "paddd", { MX, EM } },
1335 { "(bad)", { XX } },
1336 };
1337
1338 static const unsigned char onebyte_has_modrm[256] = {
1339 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1340 /* ------------------------------- */
1341 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
1342 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
1343 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
1344 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
1345 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
1346 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
1347 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
1348 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
1349 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
1350 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
1351 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
1352 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
1353 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
1354 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
1355 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
1356 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
1357 /* ------------------------------- */
1358 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1359 };
1360
1361 static const unsigned char twobyte_has_modrm[256] = {
1362 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1363 /* ------------------------------- */
1364 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
1365 /* 10 */ 1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,1, /* 1f */
1366 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
1367 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
1368 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
1369 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
1370 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
1371 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
1372 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
1373 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
1374 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
1375 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
1376 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
1377 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
1378 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
1379 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
1380 /* ------------------------------- */
1381 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1382 };
1383
1384 static char obuf[100];
1385 static char *obufp;
1386 static char scratchbuf[100];
1387 static unsigned char *start_codep;
1388 static unsigned char *insn_codep;
1389 static unsigned char *codep;
1390 static const char *lock_prefix;
1391 static const char *data_prefix;
1392 static const char *addr_prefix;
1393 static const char *repz_prefix;
1394 static const char *repnz_prefix;
1395 static disassemble_info *the_info;
1396 static struct
1397 {
1398 int mod;
1399 int reg;
1400 int rm;
1401 }
1402 modrm;
1403 static unsigned char need_modrm;
1404
1405 /* If we are accessing mod/rm/reg without need_modrm set, then the
1406 values are stale. Hitting this abort likely indicates that you
1407 need to update onebyte_has_modrm or twobyte_has_modrm. */
1408 #define MODRM_CHECK if (!need_modrm) abort ()
1409
1410 static const char **names64;
1411 static const char **names32;
1412 static const char **names16;
1413 static const char **names8;
1414 static const char **names8rex;
1415 static const char **names_seg;
1416 static const char *index64;
1417 static const char *index32;
1418 static const char **index16;
1419
1420 static const char *intel_names64[] = {
1421 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
1422 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
1423 };
1424 static const char *intel_names32[] = {
1425 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
1426 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
1427 };
1428 static const char *intel_names16[] = {
1429 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
1430 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
1431 };
1432 static const char *intel_names8[] = {
1433 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
1434 };
1435 static const char *intel_names8rex[] = {
1436 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
1437 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
1438 };
1439 static const char *intel_names_seg[] = {
1440 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
1441 };
1442 static const char *intel_index64 = "riz";
1443 static const char *intel_index32 = "eiz";
1444 static const char *intel_index16[] = {
1445 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
1446 };
1447
1448 static const char *att_names64[] = {
1449 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
1450 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
1451 };
1452 static const char *att_names32[] = {
1453 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
1454 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
1455 };
1456 static const char *att_names16[] = {
1457 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
1458 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
1459 };
1460 static const char *att_names8[] = {
1461 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
1462 };
1463 static const char *att_names8rex[] = {
1464 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
1465 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
1466 };
1467 static const char *att_names_seg[] = {
1468 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
1469 };
1470 static const char *att_index64 = "%riz";
1471 static const char *att_index32 = "%eiz";
1472 static const char *att_index16[] = {
1473 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
1474 };
1475
1476 static const struct dis386 reg_table[][8] = {
1477 /* REG_80 */
1478 {
1479 { "addA", { Eb, Ib } },
1480 { "orA", { Eb, Ib } },
1481 { "adcA", { Eb, Ib } },
1482 { "sbbA", { Eb, Ib } },
1483 { "andA", { Eb, Ib } },
1484 { "subA", { Eb, Ib } },
1485 { "xorA", { Eb, Ib } },
1486 { "cmpA", { Eb, Ib } },
1487 },
1488 /* REG_81 */
1489 {
1490 { "addQ", { Ev, Iv } },
1491 { "orQ", { Ev, Iv } },
1492 { "adcQ", { Ev, Iv } },
1493 { "sbbQ", { Ev, Iv } },
1494 { "andQ", { Ev, Iv } },
1495 { "subQ", { Ev, Iv } },
1496 { "xorQ", { Ev, Iv } },
1497 { "cmpQ", { Ev, Iv } },
1498 },
1499 /* REG_82 */
1500 {
1501 { "addQ", { Ev, sIb } },
1502 { "orQ", { Ev, sIb } },
1503 { "adcQ", { Ev, sIb } },
1504 { "sbbQ", { Ev, sIb } },
1505 { "andQ", { Ev, sIb } },
1506 { "subQ", { Ev, sIb } },
1507 { "xorQ", { Ev, sIb } },
1508 { "cmpQ", { Ev, sIb } },
1509 },
1510 /* REG_8F */
1511 {
1512 { "popU", { stackEv } },
1513 { "(bad)", { XX } },
1514 { "(bad)", { XX } },
1515 { "(bad)", { XX } },
1516 { "(bad)", { XX } },
1517 { "(bad)", { XX } },
1518 { "(bad)", { XX } },
1519 { "(bad)", { XX } },
1520 },
1521 /* REG_C0 */
1522 {
1523 { "rolA", { Eb, Ib } },
1524 { "rorA", { Eb, Ib } },
1525 { "rclA", { Eb, Ib } },
1526 { "rcrA", { Eb, Ib } },
1527 { "shlA", { Eb, Ib } },
1528 { "shrA", { Eb, Ib } },
1529 { "(bad)", { XX } },
1530 { "sarA", { Eb, Ib } },
1531 },
1532 /* REG_C1 */
1533 {
1534 { "rolQ", { Ev, Ib } },
1535 { "rorQ", { Ev, Ib } },
1536 { "rclQ", { Ev, Ib } },
1537 { "rcrQ", { Ev, Ib } },
1538 { "shlQ", { Ev, Ib } },
1539 { "shrQ", { Ev, Ib } },
1540 { "(bad)", { XX } },
1541 { "sarQ", { Ev, Ib } },
1542 },
1543 /* REG_C6 */
1544 {
1545 { "movA", { Eb, Ib } },
1546 { "(bad)", { XX } },
1547 { "(bad)", { XX } },
1548 { "(bad)", { XX } },
1549 { "(bad)", { XX } },
1550 { "(bad)", { XX } },
1551 { "(bad)", { XX } },
1552 { "(bad)", { XX } },
1553 },
1554 /* REG_C7 */
1555 {
1556 { "movQ", { Ev, Iv } },
1557 { "(bad)", { XX } },
1558 { "(bad)", { XX } },
1559 { "(bad)", { XX } },
1560 { "(bad)", { XX } },
1561 { "(bad)", { XX } },
1562 { "(bad)", { XX } },
1563 { "(bad)", { XX } },
1564 },
1565 /* REG_D0 */
1566 {
1567 { "rolA", { Eb, I1 } },
1568 { "rorA", { Eb, I1 } },
1569 { "rclA", { Eb, I1 } },
1570 { "rcrA", { Eb, I1 } },
1571 { "shlA", { Eb, I1 } },
1572 { "shrA", { Eb, I1 } },
1573 { "(bad)", { XX } },
1574 { "sarA", { Eb, I1 } },
1575 },
1576 /* REG_D1 */
1577 {
1578 { "rolQ", { Ev, I1 } },
1579 { "rorQ", { Ev, I1 } },
1580 { "rclQ", { Ev, I1 } },
1581 { "rcrQ", { Ev, I1 } },
1582 { "shlQ", { Ev, I1 } },
1583 { "shrQ", { Ev, I1 } },
1584 { "(bad)", { XX } },
1585 { "sarQ", { Ev, I1 } },
1586 },
1587 /* REG_D2 */
1588 {
1589 { "rolA", { Eb, CL } },
1590 { "rorA", { Eb, CL } },
1591 { "rclA", { Eb, CL } },
1592 { "rcrA", { Eb, CL } },
1593 { "shlA", { Eb, CL } },
1594 { "shrA", { Eb, CL } },
1595 { "(bad)", { XX } },
1596 { "sarA", { Eb, CL } },
1597 },
1598 /* REG_D3 */
1599 {
1600 { "rolQ", { Ev, CL } },
1601 { "rorQ", { Ev, CL } },
1602 { "rclQ", { Ev, CL } },
1603 { "rcrQ", { Ev, CL } },
1604 { "shlQ", { Ev, CL } },
1605 { "shrQ", { Ev, CL } },
1606 { "(bad)", { XX } },
1607 { "sarQ", { Ev, CL } },
1608 },
1609 /* REG_F6 */
1610 {
1611 { "testA", { Eb, Ib } },
1612 { "(bad)", { XX } },
1613 { "notA", { Eb } },
1614 { "negA", { Eb } },
1615 { "mulA", { Eb } }, /* Don't print the implicit %al register, */
1616 { "imulA", { Eb } }, /* to distinguish these opcodes from other */
1617 { "divA", { Eb } }, /* mul/imul opcodes. Do the same for div */
1618 { "idivA", { Eb } }, /* and idiv for consistency. */
1619 },
1620 /* REG_F7 */
1621 {
1622 { "testQ", { Ev, Iv } },
1623 { "(bad)", { XX } },
1624 { "notQ", { Ev } },
1625 { "negQ", { Ev } },
1626 { "mulQ", { Ev } }, /* Don't print the implicit register. */
1627 { "imulQ", { Ev } },
1628 { "divQ", { Ev } },
1629 { "idivQ", { Ev } },
1630 },
1631 /* REG_FE */
1632 {
1633 { "incA", { Eb } },
1634 { "decA", { Eb } },
1635 { "(bad)", { XX } },
1636 { "(bad)", { XX } },
1637 { "(bad)", { XX } },
1638 { "(bad)", { XX } },
1639 { "(bad)", { XX } },
1640 { "(bad)", { XX } },
1641 },
1642 /* REG_FF */
1643 {
1644 { "incQ", { Ev } },
1645 { "decQ", { Ev } },
1646 { "callT", { indirEv } },
1647 { "JcallT", { indirEp } },
1648 { "jmpT", { indirEv } },
1649 { "JjmpT", { indirEp } },
1650 { "pushU", { stackEv } },
1651 { "(bad)", { XX } },
1652 },
1653 /* REG_0F00 */
1654 {
1655 { "sldtD", { Sv } },
1656 { "strD", { Sv } },
1657 { "lldt", { Ew } },
1658 { "ltr", { Ew } },
1659 { "verr", { Ew } },
1660 { "verw", { Ew } },
1661 { "(bad)", { XX } },
1662 { "(bad)", { XX } },
1663 },
1664 /* REG_0F01 */
1665 {
1666 { MOD_TABLE (MOD_0F01_REG_0) },
1667 { MOD_TABLE (MOD_0F01_REG_1) },
1668 { MOD_TABLE (MOD_0F01_REG_2) },
1669 { MOD_TABLE (MOD_0F01_REG_3) },
1670 { "smswD", { Sv } },
1671 { "(bad)", { XX } },
1672 { "lmsw", { Ew } },
1673 { MOD_TABLE (MOD_0F01_REG_7) },
1674 },
1675 /* REG_0F0E */
1676 {
1677 { "prefetch", { Eb } },
1678 { "prefetchw", { Eb } },
1679 { "(bad)", { XX } },
1680 { "(bad)", { XX } },
1681 { "(bad)", { XX } },
1682 { "(bad)", { XX } },
1683 { "(bad)", { XX } },
1684 { "(bad)", { XX } },
1685 },
1686 /* REG_0F18 */
1687 {
1688 { MOD_TABLE (MOD_0F18_REG_0) },
1689 { MOD_TABLE (MOD_0F18_REG_1) },
1690 { MOD_TABLE (MOD_0F18_REG_2) },
1691 { MOD_TABLE (MOD_0F18_REG_3) },
1692 { "(bad)", { XX } },
1693 { "(bad)", { XX } },
1694 { "(bad)", { XX } },
1695 { "(bad)", { XX } },
1696 },
1697 /* REG_0F71 */
1698 {
1699 { "(bad)", { XX } },
1700 { "(bad)", { XX } },
1701 { MOD_TABLE (MOD_0F71_REG_2) },
1702 { "(bad)", { XX } },
1703 { MOD_TABLE (MOD_0F71_REG_4) },
1704 { "(bad)", { XX } },
1705 { MOD_TABLE (MOD_0F71_REG_6) },
1706 { "(bad)", { XX } },
1707 },
1708 /* REG_0F72 */
1709 {
1710 { "(bad)", { XX } },
1711 { "(bad)", { XX } },
1712 { MOD_TABLE (MOD_0F72_REG_2) },
1713 { "(bad)", { XX } },
1714 { MOD_TABLE (MOD_0F72_REG_4) },
1715 { "(bad)", { XX } },
1716 { MOD_TABLE (MOD_0F72_REG_6) },
1717 { "(bad)", { XX } },
1718 },
1719 /* REG_0F73 */
1720 {
1721 { "(bad)", { XX } },
1722 { "(bad)", { XX } },
1723 { MOD_TABLE (MOD_0F73_REG_2) },
1724 { MOD_TABLE (MOD_0F73_REG_3) },
1725 { "(bad)", { XX } },
1726 { "(bad)", { XX } },
1727 { MOD_TABLE (MOD_0F73_REG_6) },
1728 { MOD_TABLE (MOD_0F73_REG_7) },
1729 },
1730 /* REG_0FA6 */
1731 {
1732 { "montmul", { { OP_0f07, 0 } } },
1733 { "xsha1", { { OP_0f07, 0 } } },
1734 { "xsha256", { { OP_0f07, 0 } } },
1735 { "(bad)", { { OP_0f07, 0 } } },
1736 { "(bad)", { { OP_0f07, 0 } } },
1737 { "(bad)", { { OP_0f07, 0 } } },
1738 { "(bad)", { { OP_0f07, 0 } } },
1739 { "(bad)", { { OP_0f07, 0 } } },
1740 },
1741 /* REG_0FA7 */
1742 {
1743 { "xstore-rng", { { OP_0f07, 0 } } },
1744 { "xcrypt-ecb", { { OP_0f07, 0 } } },
1745 { "xcrypt-cbc", { { OP_0f07, 0 } } },
1746 { "xcrypt-ctr", { { OP_0f07, 0 } } },
1747 { "xcrypt-cfb", { { OP_0f07, 0 } } },
1748 { "xcrypt-ofb", { { OP_0f07, 0 } } },
1749 { "(bad)", { { OP_0f07, 0 } } },
1750 { "(bad)", { { OP_0f07, 0 } } },
1751 },
1752 /* REG_0FAE */
1753 {
1754 { MOD_TABLE (MOD_0FAE_REG_0) },
1755 { MOD_TABLE (MOD_0FAE_REG_1) },
1756 { MOD_TABLE (MOD_0FAE_REG_2) },
1757 { MOD_TABLE (MOD_0FAE_REG_3) },
1758 { "(bad)", { XX } },
1759 { MOD_TABLE (MOD_0FAE_REG_5) },
1760 { MOD_TABLE (MOD_0FAE_REG_6) },
1761 { MOD_TABLE (MOD_0FAE_REG_7) },
1762 },
1763 /* REG_0FBA */
1764 {
1765 { "(bad)", { XX } },
1766 { "(bad)", { XX } },
1767 { "(bad)", { XX } },
1768 { "(bad)", { XX } },
1769 { "btQ", { Ev, Ib } },
1770 { "btsQ", { Ev, Ib } },
1771 { "btrQ", { Ev, Ib } },
1772 { "btcQ", { Ev, Ib } },
1773 },
1774 /* REG_0FC7 */
1775 {
1776 { "(bad)", { XX } },
1777 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
1778 { "(bad)", { XX } },
1779 { "(bad)", { XX } },
1780 { "(bad)", { XX } },
1781 { "(bad)", { XX } },
1782 { MOD_TABLE (MOD_0FC7_REG_6) },
1783 { MOD_TABLE (MOD_0FC7_REG_7) },
1784 },
1785 };
1786
1787 static const struct dis386 prefix_table[][4] = {
1788 /* PREFIX_90 */
1789 {
1790 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
1791 { "pause", { XX } },
1792 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
1793 { "(bad)", { XX } },
1794 },
1795
1796 /* PREFIX_0F10 */
1797 {
1798 { "movups", { XM, EXx } },
1799 { "movss", { XM, EXd } },
1800 { "movupd", { XM, EXx } },
1801 { "movsd", { XM, EXq } },
1802 },
1803
1804 /* PREFIX_0F11 */
1805 {
1806 { "movups", { EXx, XM } },
1807 { "movss", { EXd, XM } },
1808 { "movupd", { EXx, XM } },
1809 { "movsd", { EXq, XM } },
1810 },
1811
1812 /* PREFIX_0F12 */
1813 {
1814 { MOD_TABLE (MOD_0F12_PREFIX_0) },
1815 { "movsldup", { XM, EXx } },
1816 { "movlpd", { XM, EXq } },
1817 { "movddup", { XM, EXq } },
1818 },
1819
1820 /* PREFIX_0F16 */
1821 {
1822 { MOD_TABLE (MOD_0F16_PREFIX_0) },
1823 { "movshdup", { XM, EXx } },
1824 { "movhpd", { XM, EXq } },
1825 { "(bad)", { XX } },
1826 },
1827
1828 /* PREFIX_0F2A */
1829 {
1830 { "cvtpi2ps", { XM, EMCq } },
1831 { "cvtsi2ssY", { XM, Ev } },
1832 { "cvtpi2pd", { XM, EMCq } },
1833 { "cvtsi2sdY", { XM, Ev } },
1834 },
1835
1836 /* PREFIX_0F2B */
1837 {
1838 { MOD_TABLE (MOD_0F2B_PREFIX_0) },
1839 { MOD_TABLE (MOD_0F2B_PREFIX_1) },
1840 { MOD_TABLE (MOD_0F2B_PREFIX_2) },
1841 { MOD_TABLE (MOD_0F2B_PREFIX_3) },
1842 },
1843
1844 /* PREFIX_0F2C */
1845 {
1846 { "cvttps2pi", { MXC, EXq } },
1847 { "cvttss2siY", { Gv, EXd } },
1848 { "cvttpd2pi", { MXC, EXx } },
1849 { "cvttsd2siY", { Gv, EXq } },
1850 },
1851
1852 /* PREFIX_0F2D */
1853 {
1854 { "cvtps2pi", { MXC, EXq } },
1855 { "cvtss2siY", { Gv, EXd } },
1856 { "cvtpd2pi", { MXC, EXx } },
1857 { "cvtsd2siY", { Gv, EXq } },
1858 },
1859
1860 /* PREFIX_0F2E */
1861 {
1862 { "ucomiss",{ XM, EXd } },
1863 { "(bad)", { XX } },
1864 { "ucomisd",{ XM, EXq } },
1865 { "(bad)", { XX } },
1866 },
1867
1868 /* PREFIX_0F2F */
1869 {
1870 { "comiss", { XM, EXd } },
1871 { "(bad)", { XX } },
1872 { "comisd", { XM, EXq } },
1873 { "(bad)", { XX } },
1874 },
1875
1876 /* PREFIX_0F51 */
1877 {
1878 { "sqrtps", { XM, EXx } },
1879 { "sqrtss", { XM, EXd } },
1880 { "sqrtpd", { XM, EXx } },
1881 { "sqrtsd", { XM, EXq } },
1882 },
1883
1884 /* PREFIX_0F52 */
1885 {
1886 { "rsqrtps",{ XM, EXx } },
1887 { "rsqrtss",{ XM, EXd } },
1888 { "(bad)", { XX } },
1889 { "(bad)", { XX } },
1890 },
1891
1892 /* PREFIX_0F53 */
1893 {
1894 { "rcpps", { XM, EXx } },
1895 { "rcpss", { XM, EXd } },
1896 { "(bad)", { XX } },
1897 { "(bad)", { XX } },
1898 },
1899
1900 /* PREFIX_0F58 */
1901 {
1902 { "addps", { XM, EXx } },
1903 { "addss", { XM, EXd } },
1904 { "addpd", { XM, EXx } },
1905 { "addsd", { XM, EXq } },
1906 },
1907
1908 /* PREFIX_0F59 */
1909 {
1910 { "mulps", { XM, EXx } },
1911 { "mulss", { XM, EXd } },
1912 { "mulpd", { XM, EXx } },
1913 { "mulsd", { XM, EXq } },
1914 },
1915
1916 /* PREFIX_0F5A */
1917 {
1918 { "cvtps2pd", { XM, EXq } },
1919 { "cvtss2sd", { XM, EXd } },
1920 { "cvtpd2ps", { XM, EXx } },
1921 { "cvtsd2ss", { XM, EXq } },
1922 },
1923
1924 /* PREFIX_0F5B */
1925 {
1926 { "cvtdq2ps", { XM, EXx } },
1927 { "cvttps2dq", { XM, EXx } },
1928 { "cvtps2dq", { XM, EXx } },
1929 { "(bad)", { XX } },
1930 },
1931
1932 /* PREFIX_0F5C */
1933 {
1934 { "subps", { XM, EXx } },
1935 { "subss", { XM, EXd } },
1936 { "subpd", { XM, EXx } },
1937 { "subsd", { XM, EXq } },
1938 },
1939
1940 /* PREFIX_0F5D */
1941 {
1942 { "minps", { XM, EXx } },
1943 { "minss", { XM, EXd } },
1944 { "minpd", { XM, EXx } },
1945 { "minsd", { XM, EXq } },
1946 },
1947
1948 /* PREFIX_0F5E */
1949 {
1950 { "divps", { XM, EXx } },
1951 { "divss", { XM, EXd } },
1952 { "divpd", { XM, EXx } },
1953 { "divsd", { XM, EXq } },
1954 },
1955
1956 /* PREFIX_0F5F */
1957 {
1958 { "maxps", { XM, EXx } },
1959 { "maxss", { XM, EXd } },
1960 { "maxpd", { XM, EXx } },
1961 { "maxsd", { XM, EXq } },
1962 },
1963
1964 /* PREFIX_0F60 */
1965 {
1966 { "punpcklbw",{ MX, EMd } },
1967 { "(bad)", { XX } },
1968 { "punpcklbw",{ MX, EMx } },
1969 { "(bad)", { XX } },
1970 },
1971
1972 /* PREFIX_0F61 */
1973 {
1974 { "punpcklwd",{ MX, EMd } },
1975 { "(bad)", { XX } },
1976 { "punpcklwd",{ MX, EMx } },
1977 { "(bad)", { XX } },
1978 },
1979
1980 /* PREFIX_0F62 */
1981 {
1982 { "punpckldq",{ MX, EMd } },
1983 { "(bad)", { XX } },
1984 { "punpckldq",{ MX, EMx } },
1985 { "(bad)", { XX } },
1986 },
1987
1988 /* PREFIX_0F6C */
1989 {
1990 { "(bad)", { XX } },
1991 { "(bad)", { XX } },
1992 { "punpcklqdq", { XM, EXx } },
1993 { "(bad)", { XX } },
1994 },
1995
1996 /* PREFIX_0F6D */
1997 {
1998 { "(bad)", { XX } },
1999 { "(bad)", { XX } },
2000 { "punpckhqdq", { XM, EXx } },
2001 { "(bad)", { XX } },
2002 },
2003
2004 /* PREFIX_0F6F */
2005 {
2006 { "movq", { MX, EM } },
2007 { "movdqu", { XM, EXx } },
2008 { "movdqa", { XM, EXx } },
2009 { "(bad)", { XX } },
2010 },
2011
2012 /* PREFIX_0F70 */
2013 {
2014 { "pshufw", { MX, EM, Ib } },
2015 { "pshufhw",{ XM, EXx, Ib } },
2016 { "pshufd", { XM, EXx, Ib } },
2017 { "pshuflw",{ XM, EXx, Ib } },
2018 },
2019
2020 /* PREFIX_0F73_REG_3 */
2021 {
2022 { "(bad)", { XX } },
2023 { "(bad)", { XX } },
2024 { "psrldq", { XS, Ib } },
2025 { "(bad)", { XX } },
2026 },
2027
2028 /* PREFIX_0F73_REG_7 */
2029 {
2030 { "(bad)", { XX } },
2031 { "(bad)", { XX } },
2032 { "pslldq", { XS, Ib } },
2033 { "(bad)", { XX } },
2034 },
2035
2036 /* PREFIX_0F78 */
2037 {
2038 {"vmread", { Em, Gm } },
2039 {"(bad)", { XX } },
2040 {"extrq", { XS, Ib, Ib } },
2041 {"insertq", { XM, XS, Ib, Ib } },
2042 },
2043
2044 /* PREFIX_0F79 */
2045 {
2046 {"vmwrite", { Gm, Em } },
2047 {"(bad)", { XX } },
2048 {"extrq", { XM, XS } },
2049 {"insertq", { XM, XS } },
2050 },
2051
2052 /* PREFIX_0F7C */
2053 {
2054 { "(bad)", { XX } },
2055 { "(bad)", { XX } },
2056 { "haddpd", { XM, EXx } },
2057 { "haddps", { XM, EXx } },
2058 },
2059
2060 /* PREFIX_0F7D */
2061 {
2062 { "(bad)", { XX } },
2063 { "(bad)", { XX } },
2064 { "hsubpd", { XM, EXx } },
2065 { "hsubps", { XM, EXx } },
2066 },
2067
2068 /* PREFIX_0F7E */
2069 {
2070 { "movK", { Edq, MX } },
2071 { "movq", { XM, EXq } },
2072 { "movK", { Edq, XM } },
2073 { "(bad)", { XX } },
2074 },
2075
2076 /* PREFIX_0F7F */
2077 {
2078 { "movq", { EM, MX } },
2079 { "movdqu", { EXx, XM } },
2080 { "movdqa", { EXx, XM } },
2081 { "(bad)", { XX } },
2082 },
2083
2084 /* PREFIX_0FB8 */
2085 {
2086 { "(bad)", { XX } },
2087 { "popcntS", { Gv, Ev } },
2088 { "(bad)", { XX } },
2089 { "(bad)", { XX } },
2090 },
2091
2092 /* PREFIX_0FBD */
2093 {
2094 { "bsrS", { Gv, Ev } },
2095 { "lzcntS", { Gv, Ev } },
2096 { "bsrS", { Gv, Ev } },
2097 { "(bad)", { XX } },
2098 },
2099
2100 /* PREFIX_0FC2 */
2101 {
2102 { "cmpps", { XM, EXx, CMP } },
2103 { "cmpss", { XM, EXd, CMP } },
2104 { "cmppd", { XM, EXx, CMP } },
2105 { "cmpsd", { XM, EXq, CMP } },
2106 },
2107
2108 /* PREFIX_0FC7_REG_6 */
2109 {
2110 { "vmptrld",{ Mq } },
2111 { "vmxon", { Mq } },
2112 { "vmclear",{ Mq } },
2113 { "(bad)", { XX } },
2114 },
2115
2116 /* PREFIX_0FD0 */
2117 {
2118 { "(bad)", { XX } },
2119 { "(bad)", { XX } },
2120 { "addsubpd", { XM, EXx } },
2121 { "addsubps", { XM, EXx } },
2122 },
2123
2124 /* PREFIX_0FD6 */
2125 {
2126 { "(bad)", { XX } },
2127 { "movq2dq",{ XM, MS } },
2128 { "movq", { EXq, XM } },
2129 { "movdq2q",{ MX, XS } },
2130 },
2131
2132 /* PREFIX_0FE6 */
2133 {
2134 { "(bad)", { XX } },
2135 { "cvtdq2pd", { XM, EXq } },
2136 { "cvttpd2dq", { XM, EXx } },
2137 { "cvtpd2dq", { XM, EXx } },
2138 },
2139
2140 /* PREFIX_0FE7 */
2141 {
2142 { "movntq", { EM, MX } },
2143 { "(bad)", { XX } },
2144 { MOD_TABLE (MOD_0FE7_PREFIX_2) },
2145 { "(bad)", { XX } },
2146 },
2147
2148 /* PREFIX_0FF0 */
2149 {
2150 { "(bad)", { XX } },
2151 { "(bad)", { XX } },
2152 { "(bad)", { XX } },
2153 { MOD_TABLE (MOD_0FF0_PREFIX_3) },
2154 },
2155
2156 /* PREFIX_0FF7 */
2157 {
2158 { "maskmovq", { MX, MS } },
2159 { "(bad)", { XX } },
2160 { "maskmovdqu", { XM, XS } },
2161 { "(bad)", { XX } },
2162 },
2163
2164 /* PREFIX_0F3810 */
2165 {
2166 { "(bad)", { XX } },
2167 { "(bad)", { XX } },
2168 { "pblendvb", { XM, EXx, XMM0 } },
2169 { "(bad)", { XX } },
2170 },
2171
2172 /* PREFIX_0F3814 */
2173 {
2174 { "(bad)", { XX } },
2175 { "(bad)", { XX } },
2176 { "blendvps", { XM, EXx, XMM0 } },
2177 { "(bad)", { XX } },
2178 },
2179
2180 /* PREFIX_0F3815 */
2181 {
2182 { "(bad)", { XX } },
2183 { "(bad)", { XX } },
2184 { "blendvpd", { XM, EXx, XMM0 } },
2185 { "(bad)", { XX } },
2186 },
2187
2188 /* PREFIX_0F3817 */
2189 {
2190 { "(bad)", { XX } },
2191 { "(bad)", { XX } },
2192 { "ptest", { XM, EXx } },
2193 { "(bad)", { XX } },
2194 },
2195
2196 /* PREFIX_0F3820 */
2197 {
2198 { "(bad)", { XX } },
2199 { "(bad)", { XX } },
2200 { "pmovsxbw", { XM, EXq } },
2201 { "(bad)", { XX } },
2202 },
2203
2204 /* PREFIX_0F3821 */
2205 {
2206 { "(bad)", { XX } },
2207 { "(bad)", { XX } },
2208 { "pmovsxbd", { XM, EXd } },
2209 { "(bad)", { XX } },
2210 },
2211
2212 /* PREFIX_0F3822 */
2213 {
2214 { "(bad)", { XX } },
2215 { "(bad)", { XX } },
2216 { "pmovsxbq", { XM, EXw } },
2217 { "(bad)", { XX } },
2218 },
2219
2220 /* PREFIX_0F3823 */
2221 {
2222 { "(bad)", { XX } },
2223 { "(bad)", { XX } },
2224 { "pmovsxwd", { XM, EXq } },
2225 { "(bad)", { XX } },
2226 },
2227
2228 /* PREFIX_0F3824 */
2229 {
2230 { "(bad)", { XX } },
2231 { "(bad)", { XX } },
2232 { "pmovsxwq", { XM, EXd } },
2233 { "(bad)", { XX } },
2234 },
2235
2236 /* PREFIX_0F3825 */
2237 {
2238 { "(bad)", { XX } },
2239 { "(bad)", { XX } },
2240 { "pmovsxdq", { XM, EXq } },
2241 { "(bad)", { XX } },
2242 },
2243
2244 /* PREFIX_0F3828 */
2245 {
2246 { "(bad)", { XX } },
2247 { "(bad)", { XX } },
2248 { "pmuldq", { XM, EXx } },
2249 { "(bad)", { XX } },
2250 },
2251
2252 /* PREFIX_0F3829 */
2253 {
2254 { "(bad)", { XX } },
2255 { "(bad)", { XX } },
2256 { "pcmpeqq", { XM, EXx } },
2257 { "(bad)", { XX } },
2258 },
2259
2260 /* PREFIX_0F382A */
2261 {
2262 { "(bad)", { XX } },
2263 { "(bad)", { XX } },
2264 { MOD_TABLE (MOD_0F382A_PREFIX_2) },
2265 { "(bad)", { XX } },
2266 },
2267
2268 /* PREFIX_0F382B */
2269 {
2270 { "(bad)", { XX } },
2271 { "(bad)", { XX } },
2272 { "packusdw", { XM, EXx } },
2273 { "(bad)", { XX } },
2274 },
2275
2276 /* PREFIX_0F3830 */
2277 {
2278 { "(bad)", { XX } },
2279 { "(bad)", { XX } },
2280 { "pmovzxbw", { XM, EXq } },
2281 { "(bad)", { XX } },
2282 },
2283
2284 /* PREFIX_0F3831 */
2285 {
2286 { "(bad)", { XX } },
2287 { "(bad)", { XX } },
2288 { "pmovzxbd", { XM, EXd } },
2289 { "(bad)", { XX } },
2290 },
2291
2292 /* PREFIX_0F3832 */
2293 {
2294 { "(bad)", { XX } },
2295 { "(bad)", { XX } },
2296 { "pmovzxbq", { XM, EXw } },
2297 { "(bad)", { XX } },
2298 },
2299
2300 /* PREFIX_0F3833 */
2301 {
2302 { "(bad)", { XX } },
2303 { "(bad)", { XX } },
2304 { "pmovzxwd", { XM, EXq } },
2305 { "(bad)", { XX } },
2306 },
2307
2308 /* PREFIX_0F3834 */
2309 {
2310 { "(bad)", { XX } },
2311 { "(bad)", { XX } },
2312 { "pmovzxwq", { XM, EXd } },
2313 { "(bad)", { XX } },
2314 },
2315
2316 /* PREFIX_0F3835 */
2317 {
2318 { "(bad)", { XX } },
2319 { "(bad)", { XX } },
2320 { "pmovzxdq", { XM, EXq } },
2321 { "(bad)", { XX } },
2322 },
2323
2324 /* PREFIX_0F3837 */
2325 {
2326 { "(bad)", { XX } },
2327 { "(bad)", { XX } },
2328 { "pcmpgtq", { XM, EXx } },
2329 { "(bad)", { XX } },
2330 },
2331
2332 /* PREFIX_0F3838 */
2333 {
2334 { "(bad)", { XX } },
2335 { "(bad)", { XX } },
2336 { "pminsb", { XM, EXx } },
2337 { "(bad)", { XX } },
2338 },
2339
2340 /* PREFIX_0F3839 */
2341 {
2342 { "(bad)", { XX } },
2343 { "(bad)", { XX } },
2344 { "pminsd", { XM, EXx } },
2345 { "(bad)", { XX } },
2346 },
2347
2348 /* PREFIX_0F383A */
2349 {
2350 { "(bad)", { XX } },
2351 { "(bad)", { XX } },
2352 { "pminuw", { XM, EXx } },
2353 { "(bad)", { XX } },
2354 },
2355
2356 /* PREFIX_0F383B */
2357 {
2358 { "(bad)", { XX } },
2359 { "(bad)", { XX } },
2360 { "pminud", { XM, EXx } },
2361 { "(bad)", { XX } },
2362 },
2363
2364 /* PREFIX_0F383C */
2365 {
2366 { "(bad)", { XX } },
2367 { "(bad)", { XX } },
2368 { "pmaxsb", { XM, EXx } },
2369 { "(bad)", { XX } },
2370 },
2371
2372 /* PREFIX_0F383D */
2373 {
2374 { "(bad)", { XX } },
2375 { "(bad)", { XX } },
2376 { "pmaxsd", { XM, EXx } },
2377 { "(bad)", { XX } },
2378 },
2379
2380 /* PREFIX_0F383E */
2381 {
2382 { "(bad)", { XX } },
2383 { "(bad)", { XX } },
2384 { "pmaxuw", { XM, EXx } },
2385 { "(bad)", { XX } },
2386 },
2387
2388 /* PREFIX_0F383F */
2389 {
2390 { "(bad)", { XX } },
2391 { "(bad)", { XX } },
2392 { "pmaxud", { XM, EXx } },
2393 { "(bad)", { XX } },
2394 },
2395
2396 /* PREFIX_0F3840 */
2397 {
2398 { "(bad)", { XX } },
2399 { "(bad)", { XX } },
2400 { "pmulld", { XM, EXx } },
2401 { "(bad)", { XX } },
2402 },
2403
2404 /* PREFIX_0F3841 */
2405 {
2406 { "(bad)", { XX } },
2407 { "(bad)", { XX } },
2408 { "phminposuw", { XM, EXx } },
2409 { "(bad)", { XX } },
2410 },
2411
2412 /* PREFIX_0F38F0 */
2413 {
2414 { "(bad)", { XX } },
2415 { "(bad)", { XX } },
2416 { "(bad)", { XX } },
2417 { "crc32", { Gdq, { CRC32_Fixup, b_mode } } },
2418 },
2419
2420 /* PREFIX_0F38F1 */
2421 {
2422 { "(bad)", { XX } },
2423 { "(bad)", { XX } },
2424 { "(bad)", { XX } },
2425 { "crc32", { Gdq, { CRC32_Fixup, v_mode } } },
2426 },
2427
2428 /* PREFIX_0F3A08 */
2429 {
2430 { "(bad)", { XX } },
2431 { "(bad)", { XX } },
2432 { "roundps", { XM, EXx, Ib } },
2433 { "(bad)", { XX } },
2434 },
2435
2436 /* PREFIX_0F3A09 */
2437 {
2438 { "(bad)", { XX } },
2439 { "(bad)", { XX } },
2440 { "roundpd", { XM, EXx, Ib } },
2441 { "(bad)", { XX } },
2442 },
2443
2444 /* PREFIX_0F3A0A */
2445 {
2446 { "(bad)", { XX } },
2447 { "(bad)", { XX } },
2448 { "roundss", { XM, EXd, Ib } },
2449 { "(bad)", { XX } },
2450 },
2451
2452 /* PREFIX_0F3A0B */
2453 {
2454 { "(bad)", { XX } },
2455 { "(bad)", { XX } },
2456 { "roundsd", { XM, EXq, Ib } },
2457 { "(bad)", { XX } },
2458 },
2459
2460 /* PREFIX_0F3A0C */
2461 {
2462 { "(bad)", { XX } },
2463 { "(bad)", { XX } },
2464 { "blendps", { XM, EXx, Ib } },
2465 { "(bad)", { XX } },
2466 },
2467
2468 /* PREFIX_0F3A0D */
2469 {
2470 { "(bad)", { XX } },
2471 { "(bad)", { XX } },
2472 { "blendpd", { XM, EXx, Ib } },
2473 { "(bad)", { XX } },
2474 },
2475
2476 /* PREFIX_0F3A0E */
2477 {
2478 { "(bad)", { XX } },
2479 { "(bad)", { XX } },
2480 { "pblendw", { XM, EXx, Ib } },
2481 { "(bad)", { XX } },
2482 },
2483
2484 /* PREFIX_0F3A14 */
2485 {
2486 { "(bad)", { XX } },
2487 { "(bad)", { XX } },
2488 { "pextrb", { Edqb, XM, Ib } },
2489 { "(bad)", { XX } },
2490 },
2491
2492 /* PREFIX_0F3A15 */
2493 {
2494 { "(bad)", { XX } },
2495 { "(bad)", { XX } },
2496 { "pextrw", { Edqw, XM, Ib } },
2497 { "(bad)", { XX } },
2498 },
2499
2500 /* PREFIX_0F3A16 */
2501 {
2502 { "(bad)", { XX } },
2503 { "(bad)", { XX } },
2504 { "pextrK", { Edq, XM, Ib } },
2505 { "(bad)", { XX } },
2506 },
2507
2508 /* PREFIX_0F3A17 */
2509 {
2510 { "(bad)", { XX } },
2511 { "(bad)", { XX } },
2512 { "extractps", { Edqd, XM, Ib } },
2513 { "(bad)", { XX } },
2514 },
2515
2516 /* PREFIX_0F3A20 */
2517 {
2518 { "(bad)", { XX } },
2519 { "(bad)", { XX } },
2520 { "pinsrb", { XM, Edqb, Ib } },
2521 { "(bad)", { XX } },
2522 },
2523
2524 /* PREFIX_0F3A21 */
2525 {
2526 { "(bad)", { XX } },
2527 { "(bad)", { XX } },
2528 { "insertps", { XM, EXd, Ib } },
2529 { "(bad)", { XX } },
2530 },
2531
2532 /* PREFIX_0F3A22 */
2533 {
2534 { "(bad)", { XX } },
2535 { "(bad)", { XX } },
2536 { "pinsrK", { XM, Edq, Ib } },
2537 { "(bad)", { XX } },
2538 },
2539
2540 /* PREFIX_0F3A40 */
2541 {
2542 { "(bad)", { XX } },
2543 { "(bad)", { XX } },
2544 { "dpps", { XM, EXx, Ib } },
2545 { "(bad)", { XX } },
2546 },
2547
2548 /* PREFIX_0F3A41 */
2549 {
2550 { "(bad)", { XX } },
2551 { "(bad)", { XX } },
2552 { "dppd", { XM, EXx, Ib } },
2553 { "(bad)", { XX } },
2554 },
2555
2556 /* PREFIX_0F3A42 */
2557 {
2558 { "(bad)", { XX } },
2559 { "(bad)", { XX } },
2560 { "mpsadbw", { XM, EXx, Ib } },
2561 { "(bad)", { XX } },
2562 },
2563
2564 /* PREFIX_0F3A60 */
2565 {
2566 { "(bad)", { XX } },
2567 { "(bad)", { XX } },
2568 { "pcmpestrm", { XM, EXx, Ib } },
2569 { "(bad)", { XX } },
2570 },
2571
2572 /* PREFIX_0F3A61 */
2573 {
2574 { "(bad)", { XX } },
2575 { "(bad)", { XX } },
2576 { "pcmpestri", { XM, EXx, Ib } },
2577 { "(bad)", { XX } },
2578 },
2579
2580 /* PREFIX_0F3A62 */
2581 {
2582 { "(bad)", { XX } },
2583 { "(bad)", { XX } },
2584 { "pcmpistrm", { XM, EXx, Ib } },
2585 { "(bad)", { XX } },
2586 },
2587
2588 /* PREFIX_0F3A63 */
2589 {
2590 { "(bad)", { XX } },
2591 { "(bad)", { XX } },
2592 { "pcmpistri", { XM, EXx, Ib } },
2593 { "(bad)", { XX } },
2594 },
2595 };
2596
2597 static const struct dis386 x86_64_table[][2] = {
2598 /* X86_64_06 */
2599 {
2600 { "push{T|}", { es } },
2601 { "(bad)", { XX } },
2602 },
2603
2604 /* X86_64_07 */
2605 {
2606 { "pop{T|}", { es } },
2607 { "(bad)", { XX } },
2608 },
2609
2610 /* X86_64_0D */
2611 {
2612 { "push{T|}", { cs } },
2613 { "(bad)", { XX } },
2614 },
2615
2616 /* X86_64_16 */
2617 {
2618 { "push{T|}", { ss } },
2619 { "(bad)", { XX } },
2620 },
2621
2622 /* X86_64_17 */
2623 {
2624 { "pop{T|}", { ss } },
2625 { "(bad)", { XX } },
2626 },
2627
2628 /* X86_64_1E */
2629 {
2630 { "push{T|}", { ds } },
2631 { "(bad)", { XX } },
2632 },
2633
2634 /* X86_64_1F */
2635 {
2636 { "pop{T|}", { ds } },
2637 { "(bad)", { XX } },
2638 },
2639
2640 /* X86_64_27 */
2641 {
2642 { "daa", { XX } },
2643 { "(bad)", { XX } },
2644 },
2645
2646 /* X86_64_2F */
2647 {
2648 { "das", { XX } },
2649 { "(bad)", { XX } },
2650 },
2651
2652 /* X86_64_37 */
2653 {
2654 { "aaa", { XX } },
2655 { "(bad)", { XX } },
2656 },
2657
2658 /* X86_64_3F */
2659 {
2660 { "aas", { XX } },
2661 { "(bad)", { XX } },
2662 },
2663
2664 /* X86_64_60 */
2665 {
2666 { "pusha{P|}", { XX } },
2667 { "(bad)", { XX } },
2668 },
2669
2670 /* X86_64_61 */
2671 {
2672 { "popa{P|}", { XX } },
2673 { "(bad)", { XX } },
2674 },
2675
2676 /* X86_64_62 */
2677 {
2678 { MOD_TABLE (MOD_62_32BIT) },
2679 { "(bad)", { XX } },
2680 },
2681
2682 /* X86_64_63 */
2683 {
2684 { "arpl", { Ew, Gw } },
2685 { "movs{lq|xd}", { Gv, Ed } },
2686 },
2687
2688 /* X86_64_6D */
2689 {
2690 { "ins{R|}", { Yzr, indirDX } },
2691 { "ins{G|}", { Yzr, indirDX } },
2692 },
2693
2694 /* X86_64_6F */
2695 {
2696 { "outs{R|}", { indirDXr, Xz } },
2697 { "outs{G|}", { indirDXr, Xz } },
2698 },
2699
2700 /* X86_64_9A */
2701 {
2702 { "Jcall{T|}", { Ap } },
2703 { "(bad)", { XX } },
2704 },
2705
2706 /* X86_64_C4 */
2707 {
2708 { MOD_TABLE (MOD_C4_32BIT) },
2709 { "(bad)", { XX } },
2710 },
2711
2712 /* X86_64_C5 */
2713 {
2714 { MOD_TABLE (MOD_C5_32BIT) },
2715 { "(bad)", { XX } },
2716 },
2717
2718 /* X86_64_CE */
2719 {
2720 { "into", { XX } },
2721 { "(bad)", { XX } },
2722 },
2723
2724 /* X86_64_D4 */
2725 {
2726 { "aam", { sIb } },
2727 { "(bad)", { XX } },
2728 },
2729
2730 /* X86_64_D5 */
2731 {
2732 { "aad", { sIb } },
2733 { "(bad)", { XX } },
2734 },
2735
2736 /* X86_64_EA */
2737 {
2738 { "Jjmp{T|}", { Ap } },
2739 { "(bad)", { XX } },
2740 },
2741
2742 /* X86_64_0F01_REG_0 */
2743 {
2744 { "sgdt{Q|IQ}", { M } },
2745 { "sgdt", { M } },
2746 },
2747
2748 /* X86_64_0F01_REG_1 */
2749 {
2750 { "sidt{Q|IQ}", { M } },
2751 { "sidt", { M } },
2752 },
2753
2754 /* X86_64_0F01_REG_2 */
2755 {
2756 { "lgdt{Q|Q}", { M } },
2757 { "lgdt", { M } },
2758 },
2759
2760 /* X86_64_0F01_REG_3 */
2761 {
2762 { "lidt{Q|Q}", { M } },
2763 { "lidt", { M } },
2764 },
2765 };
2766
2767 static const struct dis386 three_byte_table[][256] = {
2768 /* THREE_BYTE_0F24 */
2769 {
2770 /* 00 */
2771 { "fmaddps", { { OP_DREX4, q_mode } } },
2772 { "fmaddpd", { { OP_DREX4, q_mode } } },
2773 { "fmaddss", { { OP_DREX4, w_mode } } },
2774 { "fmaddsd", { { OP_DREX4, d_mode } } },
2775 { "fmaddps", { { OP_DREX4, DREX_OC1 + q_mode } } },
2776 { "fmaddpd", { { OP_DREX4, DREX_OC1 + q_mode } } },
2777 { "fmaddss", { { OP_DREX4, DREX_OC1 + w_mode } } },
2778 { "fmaddsd", { { OP_DREX4, DREX_OC1 + d_mode } } },
2779 /* 08 */
2780 { "fmsubps", { { OP_DREX4, q_mode } } },
2781 { "fmsubpd", { { OP_DREX4, q_mode } } },
2782 { "fmsubss", { { OP_DREX4, w_mode } } },
2783 { "fmsubsd", { { OP_DREX4, d_mode } } },
2784 { "fmsubps", { { OP_DREX4, DREX_OC1 + q_mode } } },
2785 { "fmsubpd", { { OP_DREX4, DREX_OC1 + q_mode } } },
2786 { "fmsubss", { { OP_DREX4, DREX_OC1 + w_mode } } },
2787 { "fmsubsd", { { OP_DREX4, DREX_OC1 + d_mode } } },
2788 /* 10 */
2789 { "fnmaddps", { { OP_DREX4, q_mode } } },
2790 { "fnmaddpd", { { OP_DREX4, q_mode } } },
2791 { "fnmaddss", { { OP_DREX4, w_mode } } },
2792 { "fnmaddsd", { { OP_DREX4, d_mode } } },
2793 { "fnmaddps", { { OP_DREX4, DREX_OC1 + q_mode } } },
2794 { "fnmaddpd", { { OP_DREX4, DREX_OC1 + q_mode } } },
2795 { "fnmaddss", { { OP_DREX4, DREX_OC1 + w_mode } } },
2796 { "fnmaddsd", { { OP_DREX4, DREX_OC1 + d_mode } } },
2797 /* 18 */
2798 { "fnmsubps", { { OP_DREX4, q_mode } } },
2799 { "fnmsubpd", { { OP_DREX4, q_mode } } },
2800 { "fnmsubss", { { OP_DREX4, w_mode } } },
2801 { "fnmsubsd", { { OP_DREX4, d_mode } } },
2802 { "fnmsubps", { { OP_DREX4, DREX_OC1 + q_mode } } },
2803 { "fnmsubpd", { { OP_DREX4, DREX_OC1 + q_mode } } },
2804 { "fnmsubss", { { OP_DREX4, DREX_OC1 + w_mode } } },
2805 { "fnmsubsd", { { OP_DREX4, DREX_OC1 + d_mode } } },
2806 /* 20 */
2807 { "permps", { { OP_DREX4, q_mode } } },
2808 { "permpd", { { OP_DREX4, q_mode } } },
2809 { "pcmov", { { OP_DREX4, q_mode } } },
2810 { "pperm", { { OP_DREX4, q_mode } } },
2811 { "permps", { { OP_DREX4, DREX_OC1 + q_mode } } },
2812 { "permpd", { { OP_DREX4, DREX_OC1 + q_mode } } },
2813 { "pcmov", { { OP_DREX4, DREX_OC1 + w_mode } } },
2814 { "pperm", { { OP_DREX4, DREX_OC1 + d_mode } } },
2815 /* 28 */
2816 { "(bad)", { XX } },
2817 { "(bad)", { XX } },
2818 { "(bad)", { XX } },
2819 { "(bad)", { XX } },
2820 { "(bad)", { XX } },
2821 { "(bad)", { XX } },
2822 { "(bad)", { XX } },
2823 { "(bad)", { XX } },
2824 /* 30 */
2825 { "(bad)", { XX } },
2826 { "(bad)", { XX } },
2827 { "(bad)", { XX } },
2828 { "(bad)", { XX } },
2829 { "(bad)", { XX } },
2830 { "(bad)", { XX } },
2831 { "(bad)", { XX } },
2832 { "(bad)", { XX } },
2833 /* 38 */
2834 { "(bad)", { XX } },
2835 { "(bad)", { XX } },
2836 { "(bad)", { XX } },
2837 { "(bad)", { XX } },
2838 { "(bad)", { XX } },
2839 { "(bad)", { XX } },
2840 { "(bad)", { XX } },
2841 { "(bad)", { XX } },
2842 /* 40 */
2843 { "protb", { { OP_DREX3, q_mode } } },
2844 { "protw", { { OP_DREX3, q_mode } } },
2845 { "protd", { { OP_DREX3, q_mode } } },
2846 { "protq", { { OP_DREX3, q_mode } } },
2847 { "pshlb", { { OP_DREX3, q_mode } } },
2848 { "pshlw", { { OP_DREX3, q_mode } } },
2849 { "pshld", { { OP_DREX3, q_mode } } },
2850 { "pshlq", { { OP_DREX3, q_mode } } },
2851 /* 48 */
2852 { "pshab", { { OP_DREX3, q_mode } } },
2853 { "pshaw", { { OP_DREX3, q_mode } } },
2854 { "pshad", { { OP_DREX3, q_mode } } },
2855 { "pshaq", { { OP_DREX3, q_mode } } },
2856 { "(bad)", { XX } },
2857 { "(bad)", { XX } },
2858 { "(bad)", { XX } },
2859 { "(bad)", { XX } },
2860 /* 50 */
2861 { "(bad)", { XX } },
2862 { "(bad)", { XX } },
2863 { "(bad)", { XX } },
2864 { "(bad)", { XX } },
2865 { "(bad)", { XX } },
2866 { "(bad)", { XX } },
2867 { "(bad)", { XX } },
2868 { "(bad)", { XX } },
2869 /* 58 */
2870 { "(bad)", { XX } },
2871 { "(bad)", { XX } },
2872 { "(bad)", { XX } },
2873 { "(bad)", { XX } },
2874 { "(bad)", { XX } },
2875 { "(bad)", { XX } },
2876 { "(bad)", { XX } },
2877 { "(bad)", { XX } },
2878 /* 60 */
2879 { "(bad)", { XX } },
2880 { "(bad)", { XX } },
2881 { "(bad)", { XX } },
2882 { "(bad)", { XX } },
2883 { "(bad)", { XX } },
2884 { "(bad)", { XX } },
2885 { "(bad)", { XX } },
2886 { "(bad)", { XX } },
2887 /* 68 */
2888 { "(bad)", { XX } },
2889 { "(bad)", { XX } },
2890 { "(bad)", { XX } },
2891 { "(bad)", { XX } },
2892 { "(bad)", { XX } },
2893 { "(bad)", { XX } },
2894 { "(bad)", { XX } },
2895 { "(bad)", { XX } },
2896 /* 70 */
2897 { "(bad)", { XX } },
2898 { "(bad)", { XX } },
2899 { "(bad)", { XX } },
2900 { "(bad)", { XX } },
2901 { "(bad)", { XX } },
2902 { "(bad)", { XX } },
2903 { "(bad)", { XX } },
2904 { "(bad)", { XX } },
2905 /* 78 */
2906 { "(bad)", { XX } },
2907 { "(bad)", { XX } },
2908 { "(bad)", { XX } },
2909 { "(bad)", { XX } },
2910 { "(bad)", { XX } },
2911 { "(bad)", { XX } },
2912 { "(bad)", { XX } },
2913 { "(bad)", { XX } },
2914 /* 80 */
2915 { "(bad)", { XX } },
2916 { "(bad)", { XX } },
2917 { "(bad)", { XX } },
2918 { "(bad)", { XX } },
2919 { "(bad)", { XX } },
2920 { "pmacssww", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
2921 { "pmacsswd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
2922 { "pmacssdql", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
2923 /* 88 */
2924 { "(bad)", { XX } },
2925 { "(bad)", { XX } },
2926 { "(bad)", { XX } },
2927 { "(bad)", { XX } },
2928 { "(bad)", { XX } },
2929 { "(bad)", { XX } },
2930 { "pmacssdd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
2931 { "pmacssdqh", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
2932 /* 90 */
2933 { "(bad)", { XX } },
2934 { "(bad)", { XX } },
2935 { "(bad)", { XX } },
2936 { "(bad)", { XX } },
2937 { "(bad)", { XX } },
2938 { "pmacsww", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
2939 { "pmacswd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
2940 { "pmacsdql", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
2941 /* 98 */
2942 { "(bad)", { XX } },
2943 { "(bad)", { XX } },
2944 { "(bad)", { XX } },
2945 { "(bad)", { XX } },
2946 { "(bad)", { XX } },
2947 { "(bad)", { XX } },
2948 { "pmacsdd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
2949 { "pmacsdqh", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
2950 /* a0 */
2951 { "(bad)", { XX } },
2952 { "(bad)", { XX } },
2953 { "(bad)", { XX } },
2954 { "(bad)", { XX } },
2955 { "(bad)", { XX } },
2956 { "(bad)", { XX } },
2957 { "pmadcsswd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
2958 { "(bad)", { XX } },
2959 /* a8 */
2960 { "(bad)", { XX } },
2961 { "(bad)", { XX } },
2962 { "(bad)", { XX } },
2963 { "(bad)", { XX } },
2964 { "(bad)", { XX } },
2965 { "(bad)", { XX } },
2966 { "(bad)", { XX } },
2967 { "(bad)", { XX } },
2968 /* b0 */
2969 { "(bad)", { XX } },
2970 { "(bad)", { XX } },
2971 { "(bad)", { XX } },
2972 { "(bad)", { XX } },
2973 { "(bad)", { XX } },
2974 { "(bad)", { XX } },
2975 { "pmadcswd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
2976 { "(bad)", { XX } },
2977 /* b8 */
2978 { "(bad)", { XX } },
2979 { "(bad)", { XX } },
2980 { "(bad)", { XX } },
2981 { "(bad)", { XX } },
2982 { "(bad)", { XX } },
2983 { "(bad)", { XX } },
2984 { "(bad)", { XX } },
2985 { "(bad)", { XX } },
2986 /* c0 */
2987 { "(bad)", { XX } },
2988 { "(bad)", { XX } },
2989 { "(bad)", { XX } },
2990 { "(bad)", { XX } },
2991 { "(bad)", { XX } },
2992 { "(bad)", { XX } },
2993 { "(bad)", { XX } },
2994 { "(bad)", { XX } },
2995 /* c8 */
2996 { "(bad)", { XX } },
2997 { "(bad)", { XX } },
2998 { "(bad)", { XX } },
2999 { "(bad)", { XX } },
3000 { "(bad)", { XX } },
3001 { "(bad)", { XX } },
3002 { "(bad)", { XX } },
3003 { "(bad)", { XX } },
3004 /* d0 */
3005 { "(bad)", { XX } },
3006 { "(bad)", { XX } },
3007 { "(bad)", { XX } },
3008 { "(bad)", { XX } },
3009 { "(bad)", { XX } },
3010 { "(bad)", { XX } },
3011 { "(bad)", { XX } },
3012 { "(bad)", { XX } },
3013 /* d8 */
3014 { "(bad)", { XX } },
3015 { "(bad)", { XX } },
3016 { "(bad)", { XX } },
3017 { "(bad)", { XX } },
3018 { "(bad)", { XX } },
3019 { "(bad)", { XX } },
3020 { "(bad)", { XX } },
3021 { "(bad)", { XX } },
3022 /* e0 */
3023 { "(bad)", { XX } },
3024 { "(bad)", { XX } },
3025 { "(bad)", { XX } },
3026 { "(bad)", { XX } },
3027 { "(bad)", { XX } },
3028 { "(bad)", { XX } },
3029 { "(bad)", { XX } },
3030 { "(bad)", { XX } },
3031 /* e8 */
3032 { "(bad)", { XX } },
3033 { "(bad)", { XX } },
3034 { "(bad)", { XX } },
3035 { "(bad)", { XX } },
3036 { "(bad)", { XX } },
3037 { "(bad)", { XX } },
3038 { "(bad)", { XX } },
3039 { "(bad)", { XX } },
3040 /* f0 */
3041 { "(bad)", { XX } },
3042 { "(bad)", { XX } },
3043 { "(bad)", { XX } },
3044 { "(bad)", { XX } },
3045 { "(bad)", { XX } },
3046 { "(bad)", { XX } },
3047 { "(bad)", { XX } },
3048 { "(bad)", { XX } },
3049 /* f8 */
3050 { "(bad)", { XX } },
3051 { "(bad)", { XX } },
3052 { "(bad)", { XX } },
3053 { "(bad)", { XX } },
3054 { "(bad)", { XX } },
3055 { "(bad)", { XX } },
3056 { "(bad)", { XX } },
3057 { "(bad)", { XX } },
3058 },
3059 /* THREE_BYTE_0F25 */
3060 {
3061 /* 00 */
3062 { "(bad)", { XX } },
3063 { "(bad)", { XX } },
3064 { "(bad)", { XX } },
3065 { "(bad)", { XX } },
3066 { "(bad)", { XX } },
3067 { "(bad)", { XX } },
3068 { "(bad)", { XX } },
3069 { "(bad)", { XX } },
3070 /* 08 */
3071 { "(bad)", { XX } },
3072 { "(bad)", { XX } },
3073 { "(bad)", { XX } },
3074 { "(bad)", { XX } },
3075 { "(bad)", { XX } },
3076 { "(bad)", { XX } },
3077 { "(bad)", { XX } },
3078 { "(bad)", { XX } },
3079 /* 10 */
3080 { "(bad)", { XX } },
3081 { "(bad)", { XX } },
3082 { "(bad)", { XX } },
3083 { "(bad)", { XX } },
3084 { "(bad)", { XX } },
3085 { "(bad)", { XX } },
3086 { "(bad)", { XX } },
3087 { "(bad)", { XX } },
3088 /* 18 */
3089 { "(bad)", { XX } },
3090 { "(bad)", { XX } },
3091 { "(bad)", { XX } },
3092 { "(bad)", { XX } },
3093 { "(bad)", { XX } },
3094 { "(bad)", { XX } },
3095 { "(bad)", { XX } },
3096 { "(bad)", { XX } },
3097 /* 20 */
3098 { "(bad)", { XX } },
3099 { "(bad)", { XX } },
3100 { "(bad)", { XX } },
3101 { "(bad)", { XX } },
3102 { "(bad)", { XX } },
3103 { "(bad)", { XX } },
3104 { "(bad)", { XX } },
3105 { "(bad)", { XX } },
3106 /* 28 */
3107 { "(bad)", { XX } },
3108 { "(bad)", { XX } },
3109 { "(bad)", { XX } },
3110 { "(bad)", { XX } },
3111 { "comps", { { OP_DREX3, q_mode }, { OP_DREX_FCMP, b_mode } } },
3112 { "compd", { { OP_DREX3, q_mode }, { OP_DREX_FCMP, b_mode } } },
3113 { "comss", { { OP_DREX3, w_mode }, { OP_DREX_FCMP, b_mode } } },
3114 { "comsd", { { OP_DREX3, d_mode }, { OP_DREX_FCMP, b_mode } } },
3115 /* 30 */
3116 { "(bad)", { XX } },
3117 { "(bad)", { XX } },
3118 { "(bad)", { XX } },
3119 { "(bad)", { XX } },
3120 { "(bad)", { XX } },
3121 { "(bad)", { XX } },
3122 { "(bad)", { XX } },
3123 { "(bad)", { XX } },
3124 /* 38 */
3125 { "(bad)", { XX } },
3126 { "(bad)", { XX } },
3127 { "(bad)", { XX } },
3128 { "(bad)", { XX } },
3129 { "(bad)", { XX } },
3130 { "(bad)", { XX } },
3131 { "(bad)", { XX } },
3132 { "(bad)", { XX } },
3133 /* 40 */
3134 { "(bad)", { XX } },
3135 { "(bad)", { XX } },
3136 { "(bad)", { XX } },
3137 { "(bad)", { XX } },
3138 { "(bad)", { XX } },
3139 { "(bad)", { XX } },
3140 { "(bad)", { XX } },
3141 { "(bad)", { XX } },
3142 /* 48 */
3143 { "(bad)", { XX } },
3144 { "(bad)", { XX } },
3145 { "(bad)", { XX } },
3146 { "(bad)", { XX } },
3147 { "pcomb", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
3148 { "pcomw", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
3149 { "pcomd", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
3150 { "pcomq", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
3151 /* 50 */
3152 { "(bad)", { XX } },
3153 { "(bad)", { XX } },
3154 { "(bad)", { XX } },
3155 { "(bad)", { XX } },
3156 { "(bad)", { XX } },
3157 { "(bad)", { XX } },
3158 { "(bad)", { XX } },
3159 { "(bad)", { XX } },
3160 /* 58 */
3161 { "(bad)", { XX } },
3162 { "(bad)", { XX } },
3163 { "(bad)", { XX } },
3164 { "(bad)", { XX } },
3165 { "(bad)", { XX } },
3166 { "(bad)", { XX } },
3167 { "(bad)", { XX } },
3168 { "(bad)", { XX } },
3169 /* 60 */
3170 { "(bad)", { XX } },
3171 { "(bad)", { XX } },
3172 { "(bad)", { XX } },
3173 { "(bad)", { XX } },
3174 { "(bad)", { XX } },
3175 { "(bad)", { XX } },
3176 { "(bad)", { XX } },
3177 { "(bad)", { XX } },
3178 /* 68 */
3179 { "(bad)", { XX } },
3180 { "(bad)", { XX } },
3181 { "(bad)", { XX } },
3182 { "(bad)", { XX } },
3183 { "pcomub", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
3184 { "pcomuw", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
3185 { "pcomud", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
3186 { "pcomuq", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
3187 /* 70 */
3188 { "(bad)", { XX } },
3189 { "(bad)", { XX } },
3190 { "(bad)", { XX } },
3191 { "(bad)", { XX } },
3192 { "(bad)", { XX } },
3193 { "(bad)", { XX } },
3194 { "(bad)", { XX } },
3195 { "(bad)", { XX } },
3196 /* 78 */
3197 { "(bad)", { XX } },
3198 { "(bad)", { XX } },
3199 { "(bad)", { XX } },
3200 { "(bad)", { XX } },
3201 { "(bad)", { XX } },
3202 { "(bad)", { XX } },
3203 { "(bad)", { XX } },
3204 { "(bad)", { XX } },
3205 /* 80 */
3206 { "(bad)", { XX } },
3207 { "(bad)", { XX } },
3208 { "(bad)", { XX } },
3209 { "(bad)", { XX } },
3210 { "(bad)", { XX } },
3211 { "(bad)", { XX } },
3212 { "(bad)", { XX } },
3213 { "(bad)", { XX } },
3214 /* 88 */
3215 { "(bad)", { XX } },
3216 { "(bad)", { XX } },
3217 { "(bad)", { XX } },
3218 { "(bad)", { XX } },
3219 { "(bad)", { XX } },
3220 { "(bad)", { XX } },
3221 { "(bad)", { XX } },
3222 { "(bad)", { XX } },
3223 /* 90 */
3224 { "(bad)", { XX } },
3225 { "(bad)", { XX } },
3226 { "(bad)", { XX } },
3227 { "(bad)", { XX } },
3228 { "(bad)", { XX } },
3229 { "(bad)", { XX } },
3230 { "(bad)", { XX } },
3231 { "(bad)", { XX } },
3232 /* 98 */
3233 { "(bad)", { XX } },
3234 { "(bad)", { XX } },
3235 { "(bad)", { XX } },
3236 { "(bad)", { XX } },
3237 { "(bad)", { XX } },
3238 { "(bad)", { XX } },
3239 { "(bad)", { XX } },
3240 { "(bad)", { XX } },
3241 /* a0 */
3242 { "(bad)", { XX } },
3243 { "(bad)", { XX } },
3244 { "(bad)", { XX } },
3245 { "(bad)", { XX } },
3246 { "(bad)", { XX } },
3247 { "(bad)", { XX } },
3248 { "(bad)", { XX } },
3249 { "(bad)", { XX } },
3250 /* a8 */
3251 { "(bad)", { XX } },
3252 { "(bad)", { XX } },
3253 { "(bad)", { XX } },
3254 { "(bad)", { XX } },
3255 { "(bad)", { XX } },
3256 { "(bad)", { XX } },
3257 { "(bad)", { XX } },
3258 { "(bad)", { XX } },
3259 /* b0 */
3260 { "(bad)", { XX } },
3261 { "(bad)", { XX } },
3262 { "(bad)", { XX } },
3263 { "(bad)", { XX } },
3264 { "(bad)", { XX } },
3265 { "(bad)", { XX } },
3266 { "(bad)", { XX } },
3267 { "(bad)", { XX } },
3268 /* b8 */
3269 { "(bad)", { XX } },
3270 { "(bad)", { XX } },
3271 { "(bad)", { XX } },
3272 { "(bad)", { XX } },
3273 { "(bad)", { XX } },
3274 { "(bad)", { XX } },
3275 { "(bad)", { XX } },
3276 { "(bad)", { XX } },
3277 /* c0 */
3278 { "(bad)", { XX } },
3279 { "(bad)", { XX } },
3280 { "(bad)", { XX } },
3281 { "(bad)", { XX } },
3282 { "(bad)", { XX } },
3283 { "(bad)", { XX } },
3284 { "(bad)", { XX } },
3285 { "(bad)", { XX } },
3286 /* c8 */
3287 { "(bad)", { XX } },
3288 { "(bad)", { XX } },
3289 { "(bad)", { XX } },
3290 { "(bad)", { XX } },
3291 { "(bad)", { XX } },
3292 { "(bad)", { XX } },
3293 { "(bad)", { XX } },
3294 { "(bad)", { XX } },
3295 /* d0 */
3296 { "(bad)", { XX } },
3297 { "(bad)", { XX } },
3298 { "(bad)", { XX } },
3299 { "(bad)", { XX } },
3300 { "(bad)", { XX } },
3301 { "(bad)", { XX } },
3302 { "(bad)", { XX } },
3303 { "(bad)", { XX } },
3304 /* d8 */
3305 { "(bad)", { XX } },
3306 { "(bad)", { XX } },
3307 { "(bad)", { XX } },
3308 { "(bad)", { XX } },
3309 { "(bad)", { XX } },
3310 { "(bad)", { XX } },
3311 { "(bad)", { XX } },
3312 { "(bad)", { XX } },
3313 /* e0 */
3314 { "(bad)", { XX } },
3315 { "(bad)", { XX } },
3316 { "(bad)", { XX } },
3317 { "(bad)", { XX } },
3318 { "(bad)", { XX } },
3319 { "(bad)", { XX } },
3320 { "(bad)", { XX } },
3321 { "(bad)", { XX } },
3322 /* e8 */
3323 { "(bad)", { XX } },
3324 { "(bad)", { XX } },
3325 { "(bad)", { XX } },
3326 { "(bad)", { XX } },
3327 { "(bad)", { XX } },
3328 { "(bad)", { XX } },
3329 { "(bad)", { XX } },
3330 { "(bad)", { XX } },
3331 /* f0 */
3332 { "(bad)", { XX } },
3333 { "(bad)", { XX } },
3334 { "(bad)", { XX } },
3335 { "(bad)", { XX } },
3336 { "(bad)", { XX } },
3337 { "(bad)", { XX } },
3338 { "(bad)", { XX } },
3339 { "(bad)", { XX } },
3340 /* f8 */
3341 { "(bad)", { XX } },
3342 { "(bad)", { XX } },
3343 { "(bad)", { XX } },
3344 { "(bad)", { XX } },
3345 { "(bad)", { XX } },
3346 { "(bad)", { XX } },
3347 { "(bad)", { XX } },
3348 { "(bad)", { XX } },
3349 },
3350 /* THREE_BYTE_0F38 */
3351 {
3352 /* 00 */
3353 { "pshufb", { MX, EM } },
3354 { "phaddw", { MX, EM } },
3355 { "phaddd", { MX, EM } },
3356 { "phaddsw", { MX, EM } },
3357 { "pmaddubsw", { MX, EM } },
3358 { "phsubw", { MX, EM } },
3359 { "phsubd", { MX, EM } },
3360 { "phsubsw", { MX, EM } },
3361 /* 08 */
3362 { "psignb", { MX, EM } },
3363 { "psignw", { MX, EM } },
3364 { "psignd", { MX, EM } },
3365 { "pmulhrsw", { MX, EM } },
3366 { "(bad)", { XX } },
3367 { "(bad)", { XX } },
3368 { "(bad)", { XX } },
3369 { "(bad)", { XX } },
3370 /* 10 */
3371 { PREFIX_TABLE (PREFIX_0F3810) },
3372 { "(bad)", { XX } },
3373 { "(bad)", { XX } },
3374 { "(bad)", { XX } },
3375 { PREFIX_TABLE (PREFIX_0F3814) },
3376 { PREFIX_TABLE (PREFIX_0F3815) },
3377 { "(bad)", { XX } },
3378 { PREFIX_TABLE (PREFIX_0F3817) },
3379 /* 18 */
3380 { "(bad)", { XX } },
3381 { "(bad)", { XX } },
3382 { "(bad)", { XX } },
3383 { "(bad)", { XX } },
3384 { "pabsb", { MX, EM } },
3385 { "pabsw", { MX, EM } },
3386 { "pabsd", { MX, EM } },
3387 { "(bad)", { XX } },
3388 /* 20 */
3389 { PREFIX_TABLE (PREFIX_0F3820) },
3390 { PREFIX_TABLE (PREFIX_0F3821) },
3391 { PREFIX_TABLE (PREFIX_0F3822) },
3392 { PREFIX_TABLE (PREFIX_0F3823) },
3393 { PREFIX_TABLE (PREFIX_0F3824) },
3394 { PREFIX_TABLE (PREFIX_0F3825) },
3395 { "(bad)", { XX } },
3396 { "(bad)", { XX } },
3397 /* 28 */
3398 { PREFIX_TABLE (PREFIX_0F3828) },
3399 { PREFIX_TABLE (PREFIX_0F3829) },
3400 { PREFIX_TABLE (PREFIX_0F382A) },
3401 { PREFIX_TABLE (PREFIX_0F382B) },
3402 { "(bad)", { XX } },
3403 { "(bad)", { XX } },
3404 { "(bad)", { XX } },
3405 { "(bad)", { XX } },
3406 /* 30 */
3407 { PREFIX_TABLE (PREFIX_0F3830) },
3408 { PREFIX_TABLE (PREFIX_0F3831) },
3409 { PREFIX_TABLE (PREFIX_0F3832) },
3410 { PREFIX_TABLE (PREFIX_0F3833) },
3411 { PREFIX_TABLE (PREFIX_0F3834) },
3412 { PREFIX_TABLE (PREFIX_0F3835) },
3413 { "(bad)", { XX } },
3414 { PREFIX_TABLE (PREFIX_0F3837) },
3415 /* 38 */
3416 { PREFIX_TABLE (PREFIX_0F3838) },
3417 { PREFIX_TABLE (PREFIX_0F3839) },
3418 { PREFIX_TABLE (PREFIX_0F383A) },
3419 { PREFIX_TABLE (PREFIX_0F383B) },
3420 { PREFIX_TABLE (PREFIX_0F383C) },
3421 { PREFIX_TABLE (PREFIX_0F383D) },
3422 { PREFIX_TABLE (PREFIX_0F383E) },
3423 { PREFIX_TABLE (PREFIX_0F383F) },
3424 /* 40 */
3425 { PREFIX_TABLE (PREFIX_0F3840) },
3426 { PREFIX_TABLE (PREFIX_0F3841) },
3427 { "(bad)", { XX } },
3428 { "(bad)", { XX } },
3429 { "(bad)", { XX } },
3430 { "(bad)", { XX } },
3431 { "(bad)", { XX } },
3432 { "(bad)", { XX } },
3433 /* 48 */
3434 { "(bad)", { XX } },
3435 { "(bad)", { XX } },
3436 { "(bad)", { XX } },
3437 { "(bad)", { XX } },
3438 { "(bad)", { XX } },
3439 { "(bad)", { XX } },
3440 { "(bad)", { XX } },
3441 { "(bad)", { XX } },
3442 /* 50 */
3443 { "(bad)", { XX } },
3444 { "(bad)", { XX } },
3445 { "(bad)", { XX } },
3446 { "(bad)", { XX } },
3447 { "(bad)", { XX } },
3448 { "(bad)", { XX } },
3449 { "(bad)", { XX } },
3450 { "(bad)", { XX } },
3451 /* 58 */
3452 { "(bad)", { XX } },
3453 { "(bad)", { XX } },
3454 { "(bad)", { XX } },
3455 { "(bad)", { XX } },
3456 { "(bad)", { XX } },
3457 { "(bad)", { XX } },
3458 { "(bad)", { XX } },
3459 { "(bad)", { XX } },
3460 /* 60 */
3461 { "(bad)", { XX } },
3462 { "(bad)", { XX } },
3463 { "(bad)", { XX } },
3464 { "(bad)", { XX } },
3465 { "(bad)", { XX } },
3466 { "(bad)", { XX } },
3467 { "(bad)", { XX } },
3468 { "(bad)", { XX } },
3469 /* 68 */
3470 { "(bad)", { XX } },
3471 { "(bad)", { XX } },
3472 { "(bad)", { XX } },
3473 { "(bad)", { XX } },
3474 { "(bad)", { XX } },
3475 { "(bad)", { XX } },
3476 { "(bad)", { XX } },
3477 { "(bad)", { XX } },
3478 /* 70 */
3479 { "(bad)", { XX } },
3480 { "(bad)", { XX } },
3481 { "(bad)", { XX } },
3482 { "(bad)", { XX } },
3483 { "(bad)", { XX } },
3484 { "(bad)", { XX } },
3485 { "(bad)", { XX } },
3486 { "(bad)", { XX } },
3487 /* 78 */
3488 { "(bad)", { XX } },
3489 { "(bad)", { XX } },
3490 { "(bad)", { XX } },
3491 { "(bad)", { XX } },
3492 { "(bad)", { XX } },
3493 { "(bad)", { XX } },
3494 { "(bad)", { XX } },
3495 { "(bad)", { XX } },
3496 /* 80 */
3497 { "(bad)", { XX } },
3498 { "(bad)", { XX } },
3499 { "(bad)", { XX } },
3500 { "(bad)", { XX } },
3501 { "(bad)", { XX } },
3502 { "(bad)", { XX } },
3503 { "(bad)", { XX } },
3504 { "(bad)", { XX } },
3505 /* 88 */
3506 { "(bad)", { XX } },
3507 { "(bad)", { XX } },
3508 { "(bad)", { XX } },
3509 { "(bad)", { XX } },
3510 { "(bad)", { XX } },
3511 { "(bad)", { XX } },
3512 { "(bad)", { XX } },
3513 { "(bad)", { XX } },
3514 /* 90 */
3515 { "(bad)", { XX } },
3516 { "(bad)", { XX } },
3517 { "(bad)", { XX } },
3518 { "(bad)", { XX } },
3519 { "(bad)", { XX } },
3520 { "(bad)", { XX } },
3521 { "(bad)", { XX } },
3522 { "(bad)", { XX } },
3523 /* 98 */
3524 { "(bad)", { XX } },
3525 { "(bad)", { XX } },
3526 { "(bad)", { XX } },
3527 { "(bad)", { XX } },
3528 { "(bad)", { XX } },
3529 { "(bad)", { XX } },
3530 { "(bad)", { XX } },
3531 { "(bad)", { XX } },
3532 /* a0 */
3533 { "(bad)", { XX } },
3534 { "(bad)", { XX } },
3535 { "(bad)", { XX } },
3536 { "(bad)", { XX } },
3537 { "(bad)", { XX } },
3538 { "(bad)", { XX } },
3539 { "(bad)", { XX } },
3540 { "(bad)", { XX } },
3541 /* a8 */
3542 { "(bad)", { XX } },
3543 { "(bad)", { XX } },
3544 { "(bad)", { XX } },
3545 { "(bad)", { XX } },
3546 { "(bad)", { XX } },
3547 { "(bad)", { XX } },
3548 { "(bad)", { XX } },
3549 { "(bad)", { XX } },
3550 /* b0 */
3551 { "(bad)", { XX } },
3552 { "(bad)", { XX } },
3553 { "(bad)", { XX } },
3554 { "(bad)", { XX } },
3555 { "(bad)", { XX } },
3556 { "(bad)", { XX } },
3557 { "(bad)", { XX } },
3558 { "(bad)", { XX } },
3559 /* b8 */
3560 { "(bad)", { XX } },
3561 { "(bad)", { XX } },
3562 { "(bad)", { XX } },
3563 { "(bad)", { XX } },
3564 { "(bad)", { XX } },
3565 { "(bad)", { XX } },
3566 { "(bad)", { XX } },
3567 { "(bad)", { XX } },
3568 /* c0 */
3569 { "(bad)", { XX } },
3570 { "(bad)", { XX } },
3571 { "(bad)", { XX } },
3572 { "(bad)", { XX } },
3573 { "(bad)", { XX } },
3574 { "(bad)", { XX } },
3575 { "(bad)", { XX } },
3576 { "(bad)", { XX } },
3577 /* c8 */
3578 { "(bad)", { XX } },
3579 { "(bad)", { XX } },
3580 { "(bad)", { XX } },
3581 { "(bad)", { XX } },
3582 { "(bad)", { XX } },
3583 { "(bad)", { XX } },
3584 { "(bad)", { XX } },
3585 { "(bad)", { XX } },
3586 /* d0 */
3587 { "(bad)", { XX } },
3588 { "(bad)", { XX } },
3589 { "(bad)", { XX } },
3590 { "(bad)", { XX } },
3591 { "(bad)", { XX } },
3592 { "(bad)", { XX } },
3593 { "(bad)", { XX } },
3594 { "(bad)", { XX } },
3595 /* d8 */
3596 { "(bad)", { XX } },
3597 { "(bad)", { XX } },
3598 { "(bad)", { XX } },
3599 { "(bad)", { XX } },
3600 { "(bad)", { XX } },
3601 { "(bad)", { XX } },
3602 { "(bad)", { XX } },
3603 { "(bad)", { XX } },
3604 /* e0 */
3605 { "(bad)", { XX } },
3606 { "(bad)", { XX } },
3607 { "(bad)", { XX } },
3608 { "(bad)", { XX } },
3609 { "(bad)", { XX } },
3610 { "(bad)", { XX } },
3611 { "(bad)", { XX } },
3612 { "(bad)", { XX } },
3613 /* e8 */
3614 { "(bad)", { XX } },
3615 { "(bad)", { XX } },
3616 { "(bad)", { XX } },
3617 { "(bad)", { XX } },
3618 { "(bad)", { XX } },
3619 { "(bad)", { XX } },
3620 { "(bad)", { XX } },
3621 { "(bad)", { XX } },
3622 /* f0 */
3623 { PREFIX_TABLE (PREFIX_0F38F0) },
3624 { PREFIX_TABLE (PREFIX_0F38F1) },
3625 { "(bad)", { XX } },
3626 { "(bad)", { XX } },
3627 { "(bad)", { XX } },
3628 { "(bad)", { XX } },
3629 { "(bad)", { XX } },
3630 { "(bad)", { XX } },
3631 /* f8 */
3632 { "(bad)", { XX } },
3633 { "(bad)", { XX } },
3634 { "(bad)", { XX } },
3635 { "(bad)", { XX } },
3636 { "(bad)", { XX } },
3637 { "(bad)", { XX } },
3638 { "(bad)", { XX } },
3639 { "(bad)", { XX } },
3640 },
3641 /* THREE_BYTE_0F3A */
3642 {
3643 /* 00 */
3644 { "(bad)", { XX } },
3645 { "(bad)", { XX } },
3646 { "(bad)", { XX } },
3647 { "(bad)", { XX } },
3648 { "(bad)", { XX } },
3649 { "(bad)", { XX } },
3650 { "(bad)", { XX } },
3651 { "(bad)", { XX } },
3652 /* 08 */
3653 { PREFIX_TABLE (PREFIX_0F3A08) },
3654 { PREFIX_TABLE (PREFIX_0F3A09) },
3655 { PREFIX_TABLE (PREFIX_0F3A0A) },
3656 { PREFIX_TABLE (PREFIX_0F3A0B) },
3657 { PREFIX_TABLE (PREFIX_0F3A0C) },
3658 { PREFIX_TABLE (PREFIX_0F3A0D) },
3659 { PREFIX_TABLE (PREFIX_0F3A0E) },
3660 { "palignr", { MX, EM, Ib } },
3661 /* 10 */
3662 { "(bad)", { XX } },
3663 { "(bad)", { XX } },
3664 { "(bad)", { XX } },
3665 { "(bad)", { XX } },
3666 { PREFIX_TABLE (PREFIX_0F3A14) },
3667 { PREFIX_TABLE (PREFIX_0F3A15) },
3668 { PREFIX_TABLE (PREFIX_0F3A16) },
3669 { PREFIX_TABLE (PREFIX_0F3A17) },
3670 /* 18 */
3671 { "(bad)", { XX } },
3672 { "(bad)", { XX } },
3673 { "(bad)", { XX } },
3674 { "(bad)", { XX } },
3675 { "(bad)", { XX } },
3676 { "(bad)", { XX } },
3677 { "(bad)", { XX } },
3678 { "(bad)", { XX } },
3679 /* 20 */
3680 { PREFIX_TABLE (PREFIX_0F3A20) },
3681 { PREFIX_TABLE (PREFIX_0F3A21) },
3682 { PREFIX_TABLE (PREFIX_0F3A22) },
3683 { "(bad)", { XX } },
3684 { "(bad)", { XX } },
3685 { "(bad)", { XX } },
3686 { "(bad)", { XX } },
3687 { "(bad)", { XX } },
3688 /* 28 */
3689 { "(bad)", { XX } },
3690 { "(bad)", { XX } },
3691 { "(bad)", { XX } },
3692 { "(bad)", { XX } },
3693 { "(bad)", { XX } },
3694 { "(bad)", { XX } },
3695 { "(bad)", { XX } },
3696 { "(bad)", { XX } },
3697 /* 30 */
3698 { "(bad)", { XX } },
3699 { "(bad)", { XX } },
3700 { "(bad)", { XX } },
3701 { "(bad)", { XX } },
3702 { "(bad)", { XX } },
3703 { "(bad)", { XX } },
3704 { "(bad)", { XX } },
3705 { "(bad)", { XX } },
3706 /* 38 */
3707 { "(bad)", { XX } },
3708 { "(bad)", { XX } },
3709 { "(bad)", { XX } },
3710 { "(bad)", { XX } },
3711 { "(bad)", { XX } },
3712 { "(bad)", { XX } },
3713 { "(bad)", { XX } },
3714 { "(bad)", { XX } },
3715 /* 40 */
3716 { PREFIX_TABLE (PREFIX_0F3A40) },
3717 { PREFIX_TABLE (PREFIX_0F3A41) },
3718 { PREFIX_TABLE (PREFIX_0F3A42) },
3719 { "(bad)", { XX } },
3720 { "(bad)", { XX } },
3721 { "(bad)", { XX } },
3722 { "(bad)", { XX } },
3723 { "(bad)", { XX } },
3724 /* 48 */
3725 { "(bad)", { XX } },
3726 { "(bad)", { XX } },
3727 { "(bad)", { XX } },
3728 { "(bad)", { XX } },
3729 { "(bad)", { XX } },
3730 { "(bad)", { XX } },
3731 { "(bad)", { XX } },
3732 { "(bad)", { XX } },
3733 /* 50 */
3734 { "(bad)", { XX } },
3735 { "(bad)", { XX } },
3736 { "(bad)", { XX } },
3737 { "(bad)", { XX } },
3738 { "(bad)", { XX } },
3739 { "(bad)", { XX } },
3740 { "(bad)", { XX } },
3741 { "(bad)", { XX } },
3742 /* 58 */
3743 { "(bad)", { XX } },
3744 { "(bad)", { XX } },
3745 { "(bad)", { XX } },
3746 { "(bad)", { XX } },
3747 { "(bad)", { XX } },
3748 { "(bad)", { XX } },
3749 { "(bad)", { XX } },
3750 { "(bad)", { XX } },
3751 /* 60 */
3752 { PREFIX_TABLE (PREFIX_0F3A60) },
3753 { PREFIX_TABLE (PREFIX_0F3A61) },
3754 { PREFIX_TABLE (PREFIX_0F3A62) },
3755 { PREFIX_TABLE (PREFIX_0F3A63) },
3756 { "(bad)", { XX } },
3757 { "(bad)", { XX } },
3758 { "(bad)", { XX } },
3759 { "(bad)", { XX } },
3760 /* 68 */
3761 { "(bad)", { XX } },
3762 { "(bad)", { XX } },
3763 { "(bad)", { XX } },
3764 { "(bad)", { XX } },
3765 { "(bad)", { XX } },
3766 { "(bad)", { XX } },
3767 { "(bad)", { XX } },
3768 { "(bad)", { XX } },
3769 /* 70 */
3770 { "(bad)", { XX } },
3771 { "(bad)", { XX } },
3772 { "(bad)", { XX } },
3773 { "(bad)", { XX } },
3774 { "(bad)", { XX } },
3775 { "(bad)", { XX } },
3776 { "(bad)", { XX } },
3777 { "(bad)", { XX } },
3778 /* 78 */
3779 { "(bad)", { XX } },
3780 { "(bad)", { XX } },
3781 { "(bad)", { XX } },
3782 { "(bad)", { XX } },
3783 { "(bad)", { XX } },
3784 { "(bad)", { XX } },
3785 { "(bad)", { XX } },
3786 { "(bad)", { XX } },
3787 /* 80 */
3788 { "(bad)", { XX } },
3789 { "(bad)", { XX } },
3790 { "(bad)", { XX } },
3791 { "(bad)", { XX } },
3792 { "(bad)", { XX } },
3793 { "(bad)", { XX } },
3794 { "(bad)", { XX } },
3795 { "(bad)", { XX } },
3796 /* 88 */
3797 { "(bad)", { XX } },
3798 { "(bad)", { XX } },
3799 { "(bad)", { XX } },
3800 { "(bad)", { XX } },
3801 { "(bad)", { XX } },
3802 { "(bad)", { XX } },
3803 { "(bad)", { XX } },
3804 { "(bad)", { XX } },
3805 /* 90 */
3806 { "(bad)", { XX } },
3807 { "(bad)", { XX } },
3808 { "(bad)", { XX } },
3809 { "(bad)", { XX } },
3810 { "(bad)", { XX } },
3811 { "(bad)", { XX } },
3812 { "(bad)", { XX } },
3813 { "(bad)", { XX } },
3814 /* 98 */
3815 { "(bad)", { XX } },
3816 { "(bad)", { XX } },
3817 { "(bad)", { XX } },
3818 { "(bad)", { XX } },
3819 { "(bad)", { XX } },
3820 { "(bad)", { XX } },
3821 { "(bad)", { XX } },
3822 { "(bad)", { XX } },
3823 /* a0 */
3824 { "(bad)", { XX } },
3825 { "(bad)", { XX } },
3826 { "(bad)", { XX } },
3827 { "(bad)", { XX } },
3828 { "(bad)", { XX } },
3829 { "(bad)", { XX } },
3830 { "(bad)", { XX } },
3831 { "(bad)", { XX } },
3832 /* a8 */
3833 { "(bad)", { XX } },
3834 { "(bad)", { XX } },
3835 { "(bad)", { XX } },
3836 { "(bad)", { XX } },
3837 { "(bad)", { XX } },
3838 { "(bad)", { XX } },
3839 { "(bad)", { XX } },
3840 { "(bad)", { XX } },
3841 /* b0 */
3842 { "(bad)", { XX } },
3843 { "(bad)", { XX } },
3844 { "(bad)", { XX } },
3845 { "(bad)", { XX } },
3846 { "(bad)", { XX } },
3847 { "(bad)", { XX } },
3848 { "(bad)", { XX } },
3849 { "(bad)", { XX } },
3850 /* b8 */
3851 { "(bad)", { XX } },
3852 { "(bad)", { XX } },
3853 { "(bad)", { XX } },
3854 { "(bad)", { XX } },
3855 { "(bad)", { XX } },
3856 { "(bad)", { XX } },
3857 { "(bad)", { XX } },
3858 { "(bad)", { XX } },
3859 /* c0 */
3860 { "(bad)", { XX } },
3861 { "(bad)", { XX } },
3862 { "(bad)", { XX } },
3863 { "(bad)", { XX } },
3864 { "(bad)", { XX } },
3865 { "(bad)", { XX } },
3866 { "(bad)", { XX } },
3867 { "(bad)", { XX } },
3868 /* c8 */
3869 { "(bad)", { XX } },
3870 { "(bad)", { XX } },
3871 { "(bad)", { XX } },
3872 { "(bad)", { XX } },
3873 { "(bad)", { XX } },
3874 { "(bad)", { XX } },
3875 { "(bad)", { XX } },
3876 { "(bad)", { XX } },
3877 /* d0 */
3878 { "(bad)", { XX } },
3879 { "(bad)", { XX } },
3880 { "(bad)", { XX } },
3881 { "(bad)", { XX } },
3882 { "(bad)", { XX } },
3883 { "(bad)", { XX } },
3884 { "(bad)", { XX } },
3885 { "(bad)", { XX } },
3886 /* d8 */
3887 { "(bad)", { XX } },
3888 { "(bad)", { XX } },
3889 { "(bad)", { XX } },
3890 { "(bad)", { XX } },
3891 { "(bad)", { XX } },
3892 { "(bad)", { XX } },
3893 { "(bad)", { XX } },
3894 { "(bad)", { XX } },
3895 /* e0 */
3896 { "(bad)", { XX } },
3897 { "(bad)", { XX } },
3898 { "(bad)", { XX } },
3899 { "(bad)", { XX } },
3900 { "(bad)", { XX } },
3901 { "(bad)", { XX } },
3902 { "(bad)", { XX } },
3903 { "(bad)", { XX } },
3904 /* e8 */
3905 { "(bad)", { XX } },
3906 { "(bad)", { XX } },
3907 { "(bad)", { XX } },
3908 { "(bad)", { XX } },
3909 { "(bad)", { XX } },
3910 { "(bad)", { XX } },
3911 { "(bad)", { XX } },
3912 { "(bad)", { XX } },
3913 /* f0 */
3914 { "(bad)", { XX } },
3915 { "(bad)", { XX } },
3916 { "(bad)", { XX } },
3917 { "(bad)", { XX } },
3918 { "(bad)", { XX } },
3919 { "(bad)", { XX } },
3920 { "(bad)", { XX } },
3921 { "(bad)", { XX } },
3922 /* f8 */
3923 { "(bad)", { XX } },
3924 { "(bad)", { XX } },
3925 { "(bad)", { XX } },
3926 { "(bad)", { XX } },
3927 { "(bad)", { XX } },
3928 { "(bad)", { XX } },
3929 { "(bad)", { XX } },
3930 { "(bad)", { XX } },
3931 },
3932 /* THREE_BYTE_0F7A */
3933 {
3934 /* 00 */
3935 { "(bad)", { XX } },
3936 { "(bad)", { XX } },
3937 { "(bad)", { XX } },
3938 { "(bad)", { XX } },
3939 { "(bad)", { XX } },
3940 { "(bad)", { XX } },
3941 { "(bad)", { XX } },
3942 { "(bad)", { XX } },
3943 /* 08 */
3944 { "(bad)", { XX } },
3945 { "(bad)", { XX } },
3946 { "(bad)", { XX } },
3947 { "(bad)", { XX } },
3948 { "(bad)", { XX } },
3949 { "(bad)", { XX } },
3950 { "(bad)", { XX } },
3951 { "(bad)", { XX } },
3952 /* 10 */
3953 { "frczps", { XM, EXq } },
3954 { "frczpd", { XM, EXq } },
3955 { "frczss", { XM, EXq } },
3956 { "frczsd", { XM, EXq } },
3957 { "(bad)", { XX } },
3958 { "(bad)", { XX } },
3959 { "(bad)", { XX } },
3960 { "(bad)", { XX } },
3961 /* 18 */
3962 { "(bad)", { XX } },
3963 { "(bad)", { XX } },
3964 { "(bad)", { XX } },
3965 { "(bad)", { XX } },
3966 { "(bad)", { XX } },
3967 { "(bad)", { XX } },
3968 { "(bad)", { XX } },
3969 { "(bad)", { XX } },
3970 /* 20 */
3971 { "ptest", { XX } },
3972 { "(bad)", { XX } },
3973 { "(bad)", { XX } },
3974 { "(bad)", { XX } },
3975 { "(bad)", { XX } },
3976 { "(bad)", { XX } },
3977 { "(bad)", { XX } },
3978 { "(bad)", { XX } },
3979 /* 28 */
3980 { "(bad)", { XX } },
3981 { "(bad)", { XX } },
3982 { "(bad)", { XX } },
3983 { "(bad)", { XX } },
3984 { "(bad)", { XX } },
3985 { "(bad)", { XX } },
3986 { "(bad)", { XX } },
3987 { "(bad)", { XX } },
3988 /* 30 */
3989 { "cvtph2ps", { XM, EXd } },
3990 { "cvtps2ph", { EXd, XM } },
3991 { "(bad)", { XX } },
3992 { "(bad)", { XX } },
3993 { "(bad)", { XX } },
3994 { "(bad)", { XX } },
3995 { "(bad)", { XX } },
3996 { "(bad)", { XX } },
3997 /* 38 */
3998 { "(bad)", { XX } },
3999 { "(bad)", { XX } },
4000 { "(bad)", { XX } },
4001 { "(bad)", { XX } },
4002 { "(bad)", { XX } },
4003 { "(bad)", { XX } },
4004 { "(bad)", { XX } },
4005 { "(bad)", { XX } },
4006 /* 40 */
4007 { "(bad)", { XX } },
4008 { "phaddbw", { XM, EXq } },
4009 { "phaddbd", { XM, EXq } },
4010 { "phaddbq", { XM, EXq } },
4011 { "(bad)", { XX } },
4012 { "(bad)", { XX } },
4013 { "phaddwd", { XM, EXq } },
4014 { "phaddwq", { XM, EXq } },
4015 /* 48 */
4016 { "(bad)", { XX } },
4017 { "(bad)", { XX } },
4018 { "(bad)", { XX } },
4019 { "phadddq", { XM, EXq } },
4020 { "(bad)", { XX } },
4021 { "(bad)", { XX } },
4022 { "(bad)", { XX } },
4023 { "(bad)", { XX } },
4024 /* 50 */
4025 { "(bad)", { XX } },
4026 { "phaddubw", { XM, EXq } },
4027 { "phaddubd", { XM, EXq } },
4028 { "phaddubq", { XM, EXq } },
4029 { "(bad)", { XX } },
4030 { "(bad)", { XX } },
4031 { "phadduwd", { XM, EXq } },
4032 { "phadduwq", { XM, EXq } },
4033 /* 58 */
4034 { "(bad)", { XX } },
4035 { "(bad)", { XX } },
4036 { "(bad)", { XX } },
4037 { "phaddudq", { XM, EXq } },
4038 { "(bad)", { XX } },
4039 { "(bad)", { XX } },
4040 { "(bad)", { XX } },
4041 { "(bad)", { XX } },
4042 /* 60 */
4043 { "(bad)", { XX } },
4044 { "phsubbw", { XM, EXq } },
4045 { "phsubbd", { XM, EXq } },
4046 { "phsubbq", { XM, EXq } },
4047 { "(bad)", { XX } },
4048 { "(bad)", { XX } },
4049 { "(bad)", { XX } },
4050 { "(bad)", { XX } },
4051 /* 68 */
4052 { "(bad)", { XX } },
4053 { "(bad)", { XX } },
4054 { "(bad)", { XX } },
4055 { "(bad)", { XX } },
4056 { "(bad)", { XX } },
4057 { "(bad)", { XX } },
4058 { "(bad)", { XX } },
4059 { "(bad)", { XX } },
4060 /* 70 */
4061 { "(bad)", { XX } },
4062 { "(bad)", { XX } },
4063 { "(bad)", { XX } },
4064 { "(bad)", { XX } },
4065 { "(bad)", { XX } },
4066 { "(bad)", { XX } },
4067 { "(bad)", { XX } },
4068 { "(bad)", { XX } },
4069 /* 78 */
4070 { "(bad)", { XX } },
4071 { "(bad)", { XX } },
4072 { "(bad)", { XX } },
4073 { "(bad)", { XX } },
4074 { "(bad)", { XX } },
4075 { "(bad)", { XX } },
4076 { "(bad)", { XX } },
4077 { "(bad)", { XX } },
4078 /* 80 */
4079 { "(bad)", { XX } },
4080 { "(bad)", { XX } },
4081 { "(bad)", { XX } },
4082 { "(bad)", { XX } },
4083 { "(bad)", { XX } },
4084 { "(bad)", { XX } },
4085 { "(bad)", { XX } },
4086 { "(bad)", { XX } },
4087 /* 88 */
4088 { "(bad)", { XX } },
4089 { "(bad)", { XX } },
4090 { "(bad)", { XX } },
4091 { "(bad)", { XX } },
4092 { "(bad)", { XX } },
4093 { "(bad)", { XX } },
4094 { "(bad)", { XX } },
4095 { "(bad)", { XX } },
4096 /* 90 */
4097 { "(bad)", { XX } },
4098 { "(bad)", { XX } },
4099 { "(bad)", { XX } },
4100 { "(bad)", { XX } },
4101 { "(bad)", { XX } },
4102 { "(bad)", { XX } },
4103 { "(bad)", { XX } },
4104 { "(bad)", { XX } },
4105 /* 98 */
4106 { "(bad)", { XX } },
4107 { "(bad)", { XX } },
4108 { "(bad)", { XX } },
4109 { "(bad)", { XX } },
4110 { "(bad)", { XX } },
4111 { "(bad)", { XX } },
4112 { "(bad)", { XX } },
4113 { "(bad)", { XX } },
4114 /* a0 */
4115 { "(bad)", { XX } },
4116 { "(bad)", { XX } },
4117 { "(bad)", { XX } },
4118 { "(bad)", { XX } },
4119 { "(bad)", { XX } },
4120 { "(bad)", { XX } },
4121 { "(bad)", { XX } },
4122 { "(bad)", { XX } },
4123 /* a8 */
4124 { "(bad)", { XX } },
4125 { "(bad)", { XX } },
4126 { "(bad)", { XX } },
4127 { "(bad)", { XX } },
4128 { "(bad)", { XX } },
4129 { "(bad)", { XX } },
4130 { "(bad)", { XX } },
4131 { "(bad)", { XX } },
4132 /* b0 */
4133 { "(bad)", { XX } },
4134 { "(bad)", { XX } },
4135 { "(bad)", { XX } },
4136 { "(bad)", { XX } },
4137 { "(bad)", { XX } },
4138 { "(bad)", { XX } },
4139 { "(bad)", { XX } },
4140 { "(bad)", { XX } },
4141 /* b8 */
4142 { "(bad)", { XX } },
4143 { "(bad)", { XX } },
4144 { "(bad)", { XX } },
4145 { "(bad)", { XX } },
4146 { "(bad)", { XX } },
4147 { "(bad)", { XX } },
4148 { "(bad)", { XX } },
4149 { "(bad)", { XX } },
4150 /* c0 */
4151 { "(bad)", { XX } },
4152 { "(bad)", { XX } },
4153 { "(bad)", { XX } },
4154 { "(bad)", { XX } },
4155 { "(bad)", { XX } },
4156 { "(bad)", { XX } },
4157 { "(bad)", { XX } },
4158 { "(bad)", { XX } },
4159 /* c8 */
4160 { "(bad)", { XX } },
4161 { "(bad)", { XX } },
4162 { "(bad)", { XX } },
4163 { "(bad)", { XX } },
4164 { "(bad)", { XX } },
4165 { "(bad)", { XX } },
4166 { "(bad)", { XX } },
4167 { "(bad)", { XX } },
4168 /* d0 */
4169 { "(bad)", { XX } },
4170 { "(bad)", { XX } },
4171 { "(bad)", { XX } },
4172 { "(bad)", { XX } },
4173 { "(bad)", { XX } },
4174 { "(bad)", { XX } },
4175 { "(bad)", { XX } },
4176 { "(bad)", { XX } },
4177 /* d8 */
4178 { "(bad)", { XX } },
4179 { "(bad)", { XX } },
4180 { "(bad)", { XX } },
4181 { "(bad)", { XX } },
4182 { "(bad)", { XX } },
4183 { "(bad)", { XX } },
4184 { "(bad)", { XX } },
4185 { "(bad)", { XX } },
4186 /* e0 */
4187 { "(bad)", { XX } },
4188 { "(bad)", { XX } },
4189 { "(bad)", { XX } },
4190 { "(bad)", { XX } },
4191 { "(bad)", { XX } },
4192 { "(bad)", { XX } },
4193 { "(bad)", { XX } },
4194 { "(bad)", { XX } },
4195 /* e8 */
4196 { "(bad)", { XX } },
4197 { "(bad)", { XX } },
4198 { "(bad)", { XX } },
4199 { "(bad)", { XX } },
4200 { "(bad)", { XX } },
4201 { "(bad)", { XX } },
4202 { "(bad)", { XX } },
4203 { "(bad)", { XX } },
4204 /* f0 */
4205 { "(bad)", { XX } },
4206 { "(bad)", { XX } },
4207 { "(bad)", { XX } },
4208 { "(bad)", { XX } },
4209 { "(bad)", { XX } },
4210 { "(bad)", { XX } },
4211 { "(bad)", { XX } },
4212 { "(bad)", { XX } },
4213 /* f8 */
4214 { "(bad)", { XX } },
4215 { "(bad)", { XX } },
4216 { "(bad)", { XX } },
4217 { "(bad)", { XX } },
4218 { "(bad)", { XX } },
4219 { "(bad)", { XX } },
4220 { "(bad)", { XX } },
4221 { "(bad)", { XX } },
4222 },
4223 /* THREE_BYTE_0F7B */
4224 {
4225 /* 00 */
4226 { "(bad)", { XX } },
4227 { "(bad)", { XX } },
4228 { "(bad)", { XX } },
4229 { "(bad)", { XX } },
4230 { "(bad)", { XX } },
4231 { "(bad)", { XX } },
4232 { "(bad)", { XX } },
4233 { "(bad)", { XX } },
4234 /* 08 */
4235 { "(bad)", { XX } },
4236 { "(bad)", { XX } },
4237 { "(bad)", { XX } },
4238 { "(bad)", { XX } },
4239 { "(bad)", { XX } },
4240 { "(bad)", { XX } },
4241 { "(bad)", { XX } },
4242 { "(bad)", { XX } },
4243 /* 10 */
4244 { "(bad)", { XX } },
4245 { "(bad)", { XX } },
4246 { "(bad)", { XX } },
4247 { "(bad)", { XX } },
4248 { "(bad)", { XX } },
4249 { "(bad)", { XX } },
4250 { "(bad)", { XX } },
4251 { "(bad)", { XX } },
4252 /* 18 */
4253 { "(bad)", { XX } },
4254 { "(bad)", { XX } },
4255 { "(bad)", { XX } },
4256 { "(bad)", { XX } },
4257 { "(bad)", { XX } },
4258 { "(bad)", { XX } },
4259 { "(bad)", { XX } },
4260 { "(bad)", { XX } },
4261 /* 20 */
4262 { "(bad)", { XX } },
4263 { "(bad)", { XX } },
4264 { "(bad)", { XX } },
4265 { "(bad)", { XX } },
4266 { "(bad)", { XX } },
4267 { "(bad)", { XX } },
4268 { "(bad)", { XX } },
4269 { "(bad)", { XX } },
4270 /* 28 */
4271 { "(bad)", { XX } },
4272 { "(bad)", { XX } },
4273 { "(bad)", { XX } },
4274 { "(bad)", { XX } },
4275 { "(bad)", { XX } },
4276 { "(bad)", { XX } },
4277 { "(bad)", { XX } },
4278 { "(bad)", { XX } },
4279 /* 30 */
4280 { "(bad)", { XX } },
4281 { "(bad)", { XX } },
4282 { "(bad)", { XX } },
4283 { "(bad)", { XX } },
4284 { "(bad)", { XX } },
4285 { "(bad)", { XX } },
4286 { "(bad)", { XX } },
4287 { "(bad)", { XX } },
4288 /* 38 */
4289 { "(bad)", { XX } },
4290 { "(bad)", { XX } },
4291 { "(bad)", { XX } },
4292 { "(bad)", { XX } },
4293 { "(bad)", { XX } },
4294 { "(bad)", { XX } },
4295 { "(bad)", { XX } },
4296 { "(bad)", { XX } },
4297 /* 40 */
4298 { "protb", { XM, EXq, Ib } },
4299 { "protw", { XM, EXq, Ib } },
4300 { "protd", { XM, EXq, Ib } },
4301 { "protq", { XM, EXq, Ib } },
4302 { "pshlb", { XM, EXq, Ib } },
4303 { "pshlw", { XM, EXq, Ib } },
4304 { "pshld", { XM, EXq, Ib } },
4305 { "pshlq", { XM, EXq, Ib } },
4306 /* 48 */
4307 { "pshab", { XM, EXq, Ib } },
4308 { "pshaw", { XM, EXq, Ib } },
4309 { "pshad", { XM, EXq, Ib } },
4310 { "pshaq", { XM, EXq, Ib } },
4311 { "(bad)", { XX } },
4312 { "(bad)", { XX } },
4313 { "(bad)", { XX } },
4314 { "(bad)", { XX } },
4315 /* 50 */
4316 { "(bad)", { XX } },
4317 { "(bad)", { XX } },
4318 { "(bad)", { XX } },
4319 { "(bad)", { XX } },
4320 { "(bad)", { XX } },
4321 { "(bad)", { XX } },
4322 { "(bad)", { XX } },
4323 { "(bad)", { XX } },
4324 /* 58 */
4325 { "(bad)", { XX } },
4326 { "(bad)", { XX } },
4327 { "(bad)", { XX } },
4328 { "(bad)", { XX } },
4329 { "(bad)", { XX } },
4330 { "(bad)", { XX } },
4331 { "(bad)", { XX } },
4332 { "(bad)", { XX } },
4333 /* 60 */
4334 { "(bad)", { XX } },
4335 { "(bad)", { XX } },
4336 { "(bad)", { XX } },
4337 { "(bad)", { XX } },
4338 { "(bad)", { XX } },
4339 { "(bad)", { XX } },
4340 { "(bad)", { XX } },
4341 { "(bad)", { XX } },
4342 /* 68 */
4343 { "(bad)", { XX } },
4344 { "(bad)", { XX } },
4345 { "(bad)", { XX } },
4346 { "(bad)", { XX } },
4347 { "(bad)", { XX } },
4348 { "(bad)", { XX } },
4349 { "(bad)", { XX } },
4350 { "(bad)", { XX } },
4351 /* 70 */
4352 { "(bad)", { XX } },
4353 { "(bad)", { XX } },
4354 { "(bad)", { XX } },
4355 { "(bad)", { XX } },
4356 { "(bad)", { XX } },
4357 { "(bad)", { XX } },
4358 { "(bad)", { XX } },
4359 { "(bad)", { XX } },
4360 /* 78 */
4361 { "(bad)", { XX } },
4362 { "(bad)", { XX } },
4363 { "(bad)", { XX } },
4364 { "(bad)", { XX } },
4365 { "(bad)", { XX } },
4366 { "(bad)", { XX } },
4367 { "(bad)", { XX } },
4368 { "(bad)", { XX } },
4369 /* 80 */
4370 { "(bad)", { XX } },
4371 { "(bad)", { XX } },
4372 { "(bad)", { XX } },
4373 { "(bad)", { XX } },
4374 { "(bad)", { XX } },
4375 { "(bad)", { XX } },
4376 { "(bad)", { XX } },
4377 { "(bad)", { XX } },
4378 /* 88 */
4379 { "(bad)", { XX } },
4380 { "(bad)", { XX } },
4381 { "(bad)", { XX } },
4382 { "(bad)", { XX } },
4383 { "(bad)", { XX } },
4384 { "(bad)", { XX } },
4385 { "(bad)", { XX } },
4386 { "(bad)", { XX } },
4387 /* 90 */
4388 { "(bad)", { XX } },
4389 { "(bad)", { XX } },
4390 { "(bad)", { XX } },
4391 { "(bad)", { XX } },
4392 { "(bad)", { XX } },
4393 { "(bad)", { XX } },
4394 { "(bad)", { XX } },
4395 { "(bad)", { XX } },
4396 /* 98 */
4397 { "(bad)", { XX } },
4398 { "(bad)", { XX } },
4399 { "(bad)", { XX } },
4400 { "(bad)", { XX } },
4401 { "(bad)", { XX } },
4402 { "(bad)", { XX } },
4403 { "(bad)", { XX } },
4404 { "(bad)", { XX } },
4405 /* a0 */
4406 { "(bad)", { XX } },
4407 { "(bad)", { XX } },
4408 { "(bad)", { XX } },
4409 { "(bad)", { XX } },
4410 { "(bad)", { XX } },
4411 { "(bad)", { XX } },
4412 { "(bad)", { XX } },
4413 { "(bad)", { XX } },
4414 /* a8 */
4415 { "(bad)", { XX } },
4416 { "(bad)", { XX } },
4417 { "(bad)", { XX } },
4418 { "(bad)", { XX } },
4419 { "(bad)", { XX } },
4420 { "(bad)", { XX } },
4421 { "(bad)", { XX } },
4422 { "(bad)", { XX } },
4423 /* b0 */
4424 { "(bad)", { XX } },
4425 { "(bad)", { XX } },
4426 { "(bad)", { XX } },
4427 { "(bad)", { XX } },
4428 { "(bad)", { XX } },
4429 { "(bad)", { XX } },
4430 { "(bad)", { XX } },
4431 { "(bad)", { XX } },
4432 /* b8 */
4433 { "(bad)", { XX } },
4434 { "(bad)", { XX } },
4435 { "(bad)", { XX } },
4436 { "(bad)", { XX } },
4437 { "(bad)", { XX } },
4438 { "(bad)", { XX } },
4439 { "(bad)", { XX } },
4440 { "(bad)", { XX } },
4441 /* c0 */
4442 { "(bad)", { XX } },
4443 { "(bad)", { XX } },
4444 { "(bad)", { XX } },
4445 { "(bad)", { XX } },
4446 { "(bad)", { XX } },
4447 { "(bad)", { XX } },
4448 { "(bad)", { XX } },
4449 { "(bad)", { XX } },
4450 /* c8 */
4451 { "(bad)", { XX } },
4452 { "(bad)", { XX } },
4453 { "(bad)", { XX } },
4454 { "(bad)", { XX } },
4455 { "(bad)", { XX } },
4456 { "(bad)", { XX } },
4457 { "(bad)", { XX } },
4458 { "(bad)", { XX } },
4459 /* d0 */
4460 { "(bad)", { XX } },
4461 { "(bad)", { XX } },
4462 { "(bad)", { XX } },
4463 { "(bad)", { XX } },
4464 { "(bad)", { XX } },
4465 { "(bad)", { XX } },
4466 { "(bad)", { XX } },
4467 { "(bad)", { XX } },
4468 /* d8 */
4469 { "(bad)", { XX } },
4470 { "(bad)", { XX } },
4471 { "(bad)", { XX } },
4472 { "(bad)", { XX } },
4473 { "(bad)", { XX } },
4474 { "(bad)", { XX } },
4475 { "(bad)", { XX } },
4476 { "(bad)", { XX } },
4477 /* e0 */
4478 { "(bad)", { XX } },
4479 { "(bad)", { XX } },
4480 { "(bad)", { XX } },
4481 { "(bad)", { XX } },
4482 { "(bad)", { XX } },
4483 { "(bad)", { XX } },
4484 { "(bad)", { XX } },
4485 { "(bad)", { XX } },
4486 /* e8 */
4487 { "(bad)", { XX } },
4488 { "(bad)", { XX } },
4489 { "(bad)", { XX } },
4490 { "(bad)", { XX } },
4491 { "(bad)", { XX } },
4492 { "(bad)", { XX } },
4493 { "(bad)", { XX } },
4494 { "(bad)", { XX } },
4495 /* f0 */
4496 { "(bad)", { XX } },
4497 { "(bad)", { XX } },
4498 { "(bad)", { XX } },
4499 { "(bad)", { XX } },
4500 { "(bad)", { XX } },
4501 { "(bad)", { XX } },
4502 { "(bad)", { XX } },
4503 { "(bad)", { XX } },
4504 /* f8 */
4505 { "(bad)", { XX } },
4506 { "(bad)", { XX } },
4507 { "(bad)", { XX } },
4508 { "(bad)", { XX } },
4509 { "(bad)", { XX } },
4510 { "(bad)", { XX } },
4511 { "(bad)", { XX } },
4512 { "(bad)", { XX } },
4513 }
4514 };
4515
4516 static const struct dis386 mod_table[][2] = {
4517 {
4518 /* MOD_8D */
4519 { "leaS", { Gv, M } },
4520 { "(bad)", { XX } },
4521 },
4522 {
4523 /* MOD_0F01_REG_0 */
4524 { X86_64_TABLE (X86_64_0F01_REG_0) },
4525 { RM_TABLE (RM_0F01_REG_0) },
4526 },
4527 {
4528 /* MOD_0F01_REG_1 */
4529 { X86_64_TABLE (X86_64_0F01_REG_1) },
4530 { RM_TABLE (RM_0F01_REG_1) },
4531 },
4532 {
4533 /* MOD_0F01_REG_2 */
4534 { X86_64_TABLE (X86_64_0F01_REG_2) },
4535 { "(bad)", { XX } },
4536 },
4537 {
4538 /* MOD_0F01_REG_3 */
4539 { X86_64_TABLE (X86_64_0F01_REG_3) },
4540 { RM_TABLE (RM_0F01_REG_3) },
4541 },
4542 {
4543 /* MOD_0F01_REG_7 */
4544 { "invlpg", { Mb } },
4545 { RM_TABLE (RM_0F01_REG_7) },
4546 },
4547 {
4548 /* MOD_0F12_PREFIX_0 */
4549 { "movlps", { XM, EXq } },
4550 { "movhlps", { XM, EXq } },
4551 },
4552 {
4553 /* MOD_0F13 */
4554 { "movlpX", { EXq, XM } },
4555 { "(bad)", { XX } },
4556 },
4557 {
4558 /* MOD_0F16_PREFIX_0 */
4559 { "movhps", { XM, EXq } },
4560 { "movlhps", { XM, EXq } },
4561 },
4562 {
4563 /* MOD_0F17 */
4564 { "movhpX", { EXq, XM } },
4565 { "(bad)", { XX } },
4566 },
4567 {
4568 /* MOD_0F18_REG_0 */
4569 { "prefetchnta", { Mb } },
4570 { "(bad)", { XX } },
4571 },
4572 {
4573 /* MOD_0F18_REG_1 */
4574 { "prefetcht0", { Mb } },
4575 { "(bad)", { XX } },
4576 },
4577 {
4578 /* MOD_0F18_REG_2 */
4579 { "prefetcht1", { Mb } },
4580 { "(bad)", { XX } },
4581 },
4582 {
4583 /* MOD_0F18_REG_3 */
4584 { "prefetcht2", { Mb } },
4585 { "(bad)", { XX } },
4586 },
4587 {
4588 /* MOD_0F20 */
4589 { "(bad)", { XX } },
4590 { "movZ", { Rm, Cm } },
4591 },
4592 {
4593 /* MOD_0F21 */
4594 { "(bad)", { XX } },
4595 { "movZ", { Rm, Dm } },
4596 },
4597 {
4598 /* MOD_0F22 */
4599 { "(bad)", { XX } },
4600 { "movZ", { Cm, Rm } },
4601 },
4602 {
4603 /* MOD_0F23 */
4604 { "(bad)", { XX } },
4605 { "movZ", { Dm, Rm } },
4606 },
4607 {
4608 /* MOD_0F24 */
4609 { THREE_BYTE_TABLE (THREE_BYTE_0F24) },
4610 { "movL", { Rd, Td } },
4611 },
4612 {
4613 /* MOD_0F26 */
4614 { "(bad)", { XX } },
4615 { "movL", { Td, Rd } },
4616 },
4617 {
4618 /* MOD_0F2B_PREFIX_0 */
4619 {"movntps", { Ev, XM } },
4620 { "(bad)", { XX } },
4621 },
4622 {
4623 /* MOD_0F2B_PREFIX_1 */
4624 {"movntss", { Ed, XM } },
4625 { "(bad)", { XX } },
4626 },
4627 {
4628 /* MOD_0F2B_PREFIX_2 */
4629 {"movntpd", { Ev, XM } },
4630 { "(bad)", { XX } },
4631 },
4632 {
4633 /* MOD_0F2B_PREFIX_3 */
4634 {"movntsd", { Eq, XM } },
4635 { "(bad)", { XX } },
4636 },
4637 {
4638 /* MOD_0F51 */
4639 { "(bad)", { XX } },
4640 { "movmskpX", { Gdq, XS } },
4641 },
4642 {
4643 /* MOD_0F71_REG_2 */
4644 { "(bad)", { XX } },
4645 { "psrlw", { MS, Ib } },
4646 },
4647 {
4648 /* MOD_0F71_REG_4 */
4649 { "(bad)", { XX } },
4650 { "psraw", { MS, Ib } },
4651 },
4652 {
4653 /* MOD_0F71_REG_6 */
4654 { "(bad)", { XX } },
4655 { "psllw", { MS, Ib } },
4656 },
4657 {
4658 /* MOD_0F72_REG_2 */
4659 { "(bad)", { XX } },
4660 { "psrld", { MS, Ib } },
4661 },
4662 {
4663 /* MOD_0F72_REG_4 */
4664 { "(bad)", { XX } },
4665 { "psrad", { MS, Ib } },
4666 },
4667 {
4668 /* MOD_0F72_REG_6 */
4669 { "(bad)", { XX } },
4670 { "pslld", { MS, Ib } },
4671 },
4672 {
4673 /* MOD_0F73_REG_2 */
4674 { "(bad)", { XX } },
4675 { "psrlq", { MS, Ib } },
4676 },
4677 {
4678 /* MOD_0F73_REG_3 */
4679 { "(bad)", { XX } },
4680 { PREFIX_TABLE (PREFIX_0F73_REG_3) },
4681 },
4682 {
4683 /* MOD_0F73_REG_6 */
4684 { "(bad)", { XX } },
4685 { "psllq", { MS, Ib } },
4686 },
4687 {
4688 /* MOD_0F73_REG_7 */
4689 { "(bad)", { XX } },
4690 { PREFIX_TABLE (PREFIX_0F73_REG_7) },
4691 },
4692 {
4693 /* MOD_0FAE_REG_0 */
4694 { "fxsave", { M } },
4695 { "(bad)", { XX } },
4696 },
4697 {
4698 /* MOD_0FAE_REG_1 */
4699 { "fxrstor", { M } },
4700 { "(bad)", { XX } },
4701 },
4702 {
4703 /* MOD_0FAE_REG_2 */
4704 { "ldmxcsr", { Md } },
4705 { "(bad)", { XX } },
4706 },
4707 {
4708 /* MOD_0FAE_REG_3 */
4709 { "stmxcsr", { Md } },
4710 { "(bad)", { XX } },
4711 },
4712 {
4713 /* MOD_0FAE_REG_5 */
4714 { "(bad)", { XX } },
4715 { RM_TABLE (RM_0FAE_REG_5) },
4716 },
4717 {
4718 /* MOD_0FAE_REG_6 */
4719 { "(bad)", { XX } },
4720 { RM_TABLE (RM_0FAE_REG_6) },
4721 },
4722 {
4723 /* MOD_0FAE_REG_7 */
4724 { "clflush", { Mb } },
4725 { RM_TABLE (RM_0FAE_REG_7) },
4726 },
4727 {
4728 /* MOD_0FB2 */
4729 { "lssS", { Gv, Mp } },
4730 { "(bad)", { XX } },
4731 },
4732 {
4733 /* MOD_0FB4 */
4734 { "lfsS", { Gv, Mp } },
4735 { "(bad)", { XX } },
4736 },
4737 {
4738 /* MOD_0FB5 */
4739 { "lgsS", { Gv, Mp } },
4740 { "(bad)", { XX } },
4741 },
4742 {
4743 /* MOD_0FC7_REG_6 */
4744 { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
4745 { "(bad)", { XX } },
4746 },
4747 {
4748 /* MOD_0FC7_REG_7 */
4749 { "vmptrst", { Mq } },
4750 { "(bad)", { XX } },
4751 },
4752 {
4753 /* MOD_0FD7 */
4754 { "(bad)", { XX } },
4755 { "pmovmskb", { Gdq, MS } },
4756 },
4757 {
4758 /* MOD_0FE7_PREFIX_2 */
4759 { "movntdq", { EM, XM } },
4760 { "(bad)", { XX } },
4761 },
4762 {
4763 /* MOD_0FF0_PREFIX_3 */
4764 { "lddqu", { XM, M } },
4765 { "(bad)", { XX } },
4766 },
4767 {
4768 /* MOD_0F382A_PREFIX_2 */
4769 { "movntdqa", { XM, EM } },
4770 { "(bad)", { XX } },
4771 },
4772 {
4773 /* MOD_62_32BIT */
4774 { "bound{S|}", { Gv, Ma } },
4775 { "(bad)", { XX } },
4776 },
4777 {
4778 /* MOD_C4_32BIT */
4779 { "lesS", { Gv, Mp } },
4780 { "(bad)", { XX } },
4781 },
4782 {
4783 /* MOD_C5_32BIT */
4784 { "ldsS", { Gv, Mp } },
4785 { "(bad)", { XX } },
4786 },
4787 };
4788
4789 static const struct dis386 rm_table[][8] = {
4790 {
4791 /* RM_0F01_REG_0 */
4792 { "(bad)", { XX } },
4793 { "vmcall", { Skip_MODRM } },
4794 { "vmlaunch", { Skip_MODRM } },
4795 { "vmresume", { Skip_MODRM } },
4796 { "vmxoff", { Skip_MODRM } },
4797 { "(bad)", { XX } },
4798 { "(bad)", { XX } },
4799 { "(bad)", { XX } },
4800 },
4801 {
4802 /* RM_0F01_REG_1 */
4803 { "monitor", { { OP_Monitor, 0 } } },
4804 { "mwait", { { OP_Mwait, 0 } } },
4805 { "(bad)", { XX } },
4806 { "(bad)", { XX } },
4807 { "(bad)", { XX } },
4808 { "(bad)", { XX } },
4809 { "(bad)", { XX } },
4810 { "(bad)", { XX } },
4811 },
4812 {
4813 /* RM_0F01_REG_3 */
4814 { "vmrun", { Skip_MODRM } },
4815 { "vmmcall", { Skip_MODRM } },
4816 { "vmload", { Skip_MODRM } },
4817 { "vmsave", { Skip_MODRM } },
4818 { "stgi", { Skip_MODRM } },
4819 { "clgi", { Skip_MODRM } },
4820 { "skinit", { Skip_MODRM } },
4821 { "invlpga", { Skip_MODRM } },
4822 },
4823 {
4824 /* RM_0F01_REG_7 */
4825 { "swapgs", { Skip_MODRM } },
4826 { "rdtscp", { Skip_MODRM } },
4827 { "(bad)", { XX } },
4828 { "(bad)", { XX } },
4829 { "(bad)", { XX } },
4830 { "(bad)", { XX } },
4831 { "(bad)", { XX } },
4832 { "(bad)", { XX } },
4833 },
4834 {
4835 /* RM_0FAE_REG_5 */
4836 { "lfence", { Skip_MODRM } },
4837 { "(bad)", { XX } },
4838 { "(bad)", { XX } },
4839 { "(bad)", { XX } },
4840 { "(bad)", { XX } },
4841 { "(bad)", { XX } },
4842 { "(bad)", { XX } },
4843 { "(bad)", { XX } },
4844 },
4845 {
4846 /* RM_0FAE_REG_6 */
4847 { "mfence", { Skip_MODRM } },
4848 { "(bad)", { XX } },
4849 { "(bad)", { XX } },
4850 { "(bad)", { XX } },
4851 { "(bad)", { XX } },
4852 { "(bad)", { XX } },
4853 { "(bad)", { XX } },
4854 { "(bad)", { XX } },
4855 },
4856 {
4857 /* RM_0FAE_REG_7 */
4858 { "sfence", { Skip_MODRM } },
4859 { "(bad)", { XX } },
4860 { "(bad)", { XX } },
4861 { "(bad)", { XX } },
4862 { "(bad)", { XX } },
4863 { "(bad)", { XX } },
4864 { "(bad)", { XX } },
4865 { "(bad)", { XX } },
4866 },
4867 };
4868
4869 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
4870
4871 static void
4872 ckprefix (void)
4873 {
4874 int newrex;
4875 rex = 0;
4876 prefixes = 0;
4877 used_prefixes = 0;
4878 rex_used = 0;
4879 while (1)
4880 {
4881 FETCH_DATA (the_info, codep + 1);
4882 newrex = 0;
4883 switch (*codep)
4884 {
4885 /* REX prefixes family. */
4886 case 0x40:
4887 case 0x41:
4888 case 0x42:
4889 case 0x43:
4890 case 0x44:
4891 case 0x45:
4892 case 0x46:
4893 case 0x47:
4894 case 0x48:
4895 case 0x49:
4896 case 0x4a:
4897 case 0x4b:
4898 case 0x4c:
4899 case 0x4d:
4900 case 0x4e:
4901 case 0x4f:
4902 if (address_mode == mode_64bit)
4903 newrex = *codep;
4904 else
4905 return;
4906 break;
4907 case 0xf3:
4908 prefixes |= PREFIX_REPZ;
4909 break;
4910 case 0xf2:
4911 prefixes |= PREFIX_REPNZ;
4912 break;
4913 case 0xf0:
4914 prefixes |= PREFIX_LOCK;
4915 break;
4916 case 0x2e:
4917 prefixes |= PREFIX_CS;
4918 break;
4919 case 0x36:
4920 prefixes |= PREFIX_SS;
4921 break;
4922 case 0x3e:
4923 prefixes |= PREFIX_DS;
4924 break;
4925 case 0x26:
4926 prefixes |= PREFIX_ES;
4927 break;
4928 case 0x64:
4929 prefixes |= PREFIX_FS;
4930 break;
4931 case 0x65:
4932 prefixes |= PREFIX_GS;
4933 break;
4934 case 0x66:
4935 prefixes |= PREFIX_DATA;
4936 break;
4937 case 0x67:
4938 prefixes |= PREFIX_ADDR;
4939 break;
4940 case FWAIT_OPCODE:
4941 /* fwait is really an instruction. If there are prefixes
4942 before the fwait, they belong to the fwait, *not* to the
4943 following instruction. */
4944 if (prefixes || rex)
4945 {
4946 prefixes |= PREFIX_FWAIT;
4947 codep++;
4948 return;
4949 }
4950 prefixes = PREFIX_FWAIT;
4951 break;
4952 default:
4953 return;
4954 }
4955 /* Rex is ignored when followed by another prefix. */
4956 if (rex)
4957 {
4958 rex_used = rex;
4959 return;
4960 }
4961 rex = newrex;
4962 codep++;
4963 }
4964 }
4965
4966 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
4967 prefix byte. */
4968
4969 static const char *
4970 prefix_name (int pref, int sizeflag)
4971 {
4972 static const char *rexes [16] =
4973 {
4974 "rex", /* 0x40 */
4975 "rex.B", /* 0x41 */
4976 "rex.X", /* 0x42 */
4977 "rex.XB", /* 0x43 */
4978 "rex.R", /* 0x44 */
4979 "rex.RB", /* 0x45 */
4980 "rex.RX", /* 0x46 */
4981 "rex.RXB", /* 0x47 */
4982 "rex.W", /* 0x48 */
4983 "rex.WB", /* 0x49 */
4984 "rex.WX", /* 0x4a */
4985 "rex.WXB", /* 0x4b */
4986 "rex.WR", /* 0x4c */
4987 "rex.WRB", /* 0x4d */
4988 "rex.WRX", /* 0x4e */
4989 "rex.WRXB", /* 0x4f */
4990 };
4991
4992 switch (pref)
4993 {
4994 /* REX prefixes family. */
4995 case 0x40:
4996 case 0x41:
4997 case 0x42:
4998 case 0x43:
4999 case 0x44:
5000 case 0x45:
5001 case 0x46:
5002 case 0x47:
5003 case 0x48:
5004 case 0x49:
5005 case 0x4a:
5006 case 0x4b:
5007 case 0x4c:
5008 case 0x4d:
5009 case 0x4e:
5010 case 0x4f:
5011 return rexes [pref - 0x40];
5012 case 0xf3:
5013 return "repz";
5014 case 0xf2:
5015 return "repnz";
5016 case 0xf0:
5017 return "lock";
5018 case 0x2e:
5019 return "cs";
5020 case 0x36:
5021 return "ss";
5022 case 0x3e:
5023 return "ds";
5024 case 0x26:
5025 return "es";
5026 case 0x64:
5027 return "fs";
5028 case 0x65:
5029 return "gs";
5030 case 0x66:
5031 return (sizeflag & DFLAG) ? "data16" : "data32";
5032 case 0x67:
5033 if (address_mode == mode_64bit)
5034 return (sizeflag & AFLAG) ? "addr32" : "addr64";
5035 else
5036 return (sizeflag & AFLAG) ? "addr16" : "addr32";
5037 case FWAIT_OPCODE:
5038 return "fwait";
5039 default:
5040 return NULL;
5041 }
5042 }
5043
5044 static char op_out[MAX_OPERANDS][100];
5045 static int op_ad, op_index[MAX_OPERANDS];
5046 static int two_source_ops;
5047 static bfd_vma op_address[MAX_OPERANDS];
5048 static bfd_vma op_riprel[MAX_OPERANDS];
5049 static bfd_vma start_pc;
5050
5051 /*
5052 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
5053 * (see topic "Redundant prefixes" in the "Differences from 8086"
5054 * section of the "Virtual 8086 Mode" chapter.)
5055 * 'pc' should be the address of this instruction, it will
5056 * be used to print the target address if this is a relative jump or call
5057 * The function returns the length of this instruction in bytes.
5058 */
5059
5060 static char intel_syntax;
5061 static char open_char;
5062 static char close_char;
5063 static char separator_char;
5064 static char scale_char;
5065
5066 /* Here for backwards compatibility. When gdb stops using
5067 print_insn_i386_att and print_insn_i386_intel these functions can
5068 disappear, and print_insn_i386 be merged into print_insn. */
5069 int
5070 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
5071 {
5072 intel_syntax = 0;
5073
5074 return print_insn (pc, info);
5075 }
5076
5077 int
5078 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
5079 {
5080 intel_syntax = 1;
5081
5082 return print_insn (pc, info);
5083 }
5084
5085 int
5086 print_insn_i386 (bfd_vma pc, disassemble_info *info)
5087 {
5088 intel_syntax = -1;
5089
5090 return print_insn (pc, info);
5091 }
5092
5093 void
5094 print_i386_disassembler_options (FILE *stream)
5095 {
5096 fprintf (stream, _("\n\
5097 The following i386/x86-64 specific disassembler options are supported for use\n\
5098 with the -M switch (multiple options should be separated by commas):\n"));
5099
5100 fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n"));
5101 fprintf (stream, _(" i386 Disassemble in 32bit mode\n"));
5102 fprintf (stream, _(" i8086 Disassemble in 16bit mode\n"));
5103 fprintf (stream, _(" att Display instruction in AT&T syntax\n"));
5104 fprintf (stream, _(" intel Display instruction in Intel syntax\n"));
5105 fprintf (stream, _(" addr64 Assume 64bit address size\n"));
5106 fprintf (stream, _(" addr32 Assume 32bit address size\n"));
5107 fprintf (stream, _(" addr16 Assume 16bit address size\n"));
5108 fprintf (stream, _(" data32 Assume 32bit data size\n"));
5109 fprintf (stream, _(" data16 Assume 16bit data size\n"));
5110 fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n"));
5111 }
5112
5113 /* Get a pointer to struct dis386 with a valid name. */
5114
5115 static const struct dis386 *
5116 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
5117 {
5118 int index;
5119
5120 if (dp->name != NULL)
5121 return dp;
5122
5123 switch (dp->op[0].bytemode)
5124 {
5125 case USE_REG_TABLE:
5126 dp = &reg_table[dp->op[1].bytemode][modrm.reg];
5127 break;
5128
5129 case USE_MOD_TABLE:
5130 index = modrm.mod == 0x3 ? 1 : 0;
5131 dp = &mod_table[dp->op[1].bytemode][index];
5132 break;
5133
5134 case USE_RM_TABLE:
5135 dp = &rm_table[dp->op[1].bytemode][modrm.rm];
5136 break;
5137
5138 case USE_PREFIX_TABLE:
5139 index = 0;
5140 used_prefixes |= (prefixes & PREFIX_REPZ);
5141 if (prefixes & PREFIX_REPZ)
5142 {
5143 index = 1;
5144 repz_prefix = NULL;
5145 }
5146 else
5147 {
5148 /* We should check PREFIX_REPNZ and PREFIX_REPZ before
5149 PREFIX_DATA. */
5150 used_prefixes |= (prefixes & PREFIX_REPNZ);
5151 if (prefixes & PREFIX_REPNZ)
5152 {
5153 index = 3;
5154 repnz_prefix = NULL;
5155 }
5156 else
5157 {
5158 used_prefixes |= (prefixes & PREFIX_DATA);
5159 if (prefixes & PREFIX_DATA)
5160 {
5161 index = 2;
5162 data_prefix = NULL;
5163 }
5164 }
5165 }
5166 dp = &prefix_table[dp->op[1].bytemode][index];
5167 break;
5168
5169 case USE_X86_64_TABLE:
5170 index = address_mode == mode_64bit ? 1 : 0;
5171 dp = &x86_64_table[dp->op[1].bytemode][index];
5172 break;
5173
5174 case USE_3BYTE_TABLE:
5175 FETCH_DATA (info, codep + 2);
5176 index = *codep++;
5177 dp = &three_byte_table[dp->op[1].bytemode][index];
5178 modrm.mod = (*codep >> 6) & 3;
5179 modrm.reg = (*codep >> 3) & 7;
5180 modrm.rm = *codep & 7;
5181 break;
5182
5183 default:
5184 oappend (INTERNAL_DISASSEMBLER_ERROR);
5185 return NULL;
5186 }
5187
5188 if (dp->name != NULL)
5189 return dp;
5190 else
5191 return get_valid_dis386 (dp, info);
5192 }
5193
5194 static int
5195 print_insn (bfd_vma pc, disassemble_info *info)
5196 {
5197 const struct dis386 *dp;
5198 int i;
5199 char *op_txt[MAX_OPERANDS];
5200 int needcomma;
5201 int sizeflag;
5202 const char *p;
5203 struct dis_private priv;
5204 unsigned char op;
5205 char prefix_obuf[32];
5206 char *prefix_obufp;
5207
5208 if (info->mach == bfd_mach_x86_64_intel_syntax
5209 || info->mach == bfd_mach_x86_64)
5210 address_mode = mode_64bit;
5211 else
5212 address_mode = mode_32bit;
5213
5214 if (intel_syntax == (char) -1)
5215 intel_syntax = (info->mach == bfd_mach_i386_i386_intel_syntax
5216 || info->mach == bfd_mach_x86_64_intel_syntax);
5217
5218 if (info->mach == bfd_mach_i386_i386
5219 || info->mach == bfd_mach_x86_64
5220 || info->mach == bfd_mach_i386_i386_intel_syntax
5221 || info->mach == bfd_mach_x86_64_intel_syntax)
5222 priv.orig_sizeflag = AFLAG | DFLAG;
5223 else if (info->mach == bfd_mach_i386_i8086)
5224 priv.orig_sizeflag = 0;
5225 else
5226 abort ();
5227
5228 for (p = info->disassembler_options; p != NULL; )
5229 {
5230 if (CONST_STRNEQ (p, "x86-64"))
5231 {
5232 address_mode = mode_64bit;
5233 priv.orig_sizeflag = AFLAG | DFLAG;
5234 }
5235 else if (CONST_STRNEQ (p, "i386"))
5236 {
5237 address_mode = mode_32bit;
5238 priv.orig_sizeflag = AFLAG | DFLAG;
5239 }
5240 else if (CONST_STRNEQ (p, "i8086"))
5241 {
5242 address_mode = mode_16bit;
5243 priv.orig_sizeflag = 0;
5244 }
5245 else if (CONST_STRNEQ (p, "intel"))
5246 {
5247 intel_syntax = 1;
5248 }
5249 else if (CONST_STRNEQ (p, "att"))
5250 {
5251 intel_syntax = 0;
5252 }
5253 else if (CONST_STRNEQ (p, "addr"))
5254 {
5255 if (address_mode == mode_64bit)
5256 {
5257 if (p[4] == '3' && p[5] == '2')
5258 priv.orig_sizeflag &= ~AFLAG;
5259 else if (p[4] == '6' && p[5] == '4')
5260 priv.orig_sizeflag |= AFLAG;
5261 }
5262 else
5263 {
5264 if (p[4] == '1' && p[5] == '6')
5265 priv.orig_sizeflag &= ~AFLAG;
5266 else if (p[4] == '3' && p[5] == '2')
5267 priv.orig_sizeflag |= AFLAG;
5268 }
5269 }
5270 else if (CONST_STRNEQ (p, "data"))
5271 {
5272 if (p[4] == '1' && p[5] == '6')
5273 priv.orig_sizeflag &= ~DFLAG;
5274 else if (p[4] == '3' && p[5] == '2')
5275 priv.orig_sizeflag |= DFLAG;
5276 }
5277 else if (CONST_STRNEQ (p, "suffix"))
5278 priv.orig_sizeflag |= SUFFIX_ALWAYS;
5279
5280 p = strchr (p, ',');
5281 if (p != NULL)
5282 p++;
5283 }
5284
5285 if (intel_syntax)
5286 {
5287 names64 = intel_names64;
5288 names32 = intel_names32;
5289 names16 = intel_names16;
5290 names8 = intel_names8;
5291 names8rex = intel_names8rex;
5292 names_seg = intel_names_seg;
5293 index64 = intel_index64;
5294 index32 = intel_index32;
5295 index16 = intel_index16;
5296 open_char = '[';
5297 close_char = ']';
5298 separator_char = '+';
5299 scale_char = '*';
5300 }
5301 else
5302 {
5303 names64 = att_names64;
5304 names32 = att_names32;
5305 names16 = att_names16;
5306 names8 = att_names8;
5307 names8rex = att_names8rex;
5308 names_seg = att_names_seg;
5309 index64 = att_index64;
5310 index32 = att_index32;
5311 index16 = att_index16;
5312 open_char = '(';
5313 close_char = ')';
5314 separator_char = ',';
5315 scale_char = ',';
5316 }
5317
5318 /* The output looks better if we put 7 bytes on a line, since that
5319 puts most long word instructions on a single line. */
5320 info->bytes_per_line = 7;
5321
5322 info->private_data = &priv;
5323 priv.max_fetched = priv.the_buffer;
5324 priv.insn_start = pc;
5325
5326 obuf[0] = 0;
5327 for (i = 0; i < MAX_OPERANDS; ++i)
5328 {
5329 op_out[i][0] = 0;
5330 op_index[i] = -1;
5331 }
5332
5333 the_info = info;
5334 start_pc = pc;
5335 start_codep = priv.the_buffer;
5336 codep = priv.the_buffer;
5337
5338 if (setjmp (priv.bailout) != 0)
5339 {
5340 const char *name;
5341
5342 /* Getting here means we tried for data but didn't get it. That
5343 means we have an incomplete instruction of some sort. Just
5344 print the first byte as a prefix or a .byte pseudo-op. */
5345 if (codep > priv.the_buffer)
5346 {
5347 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
5348 if (name != NULL)
5349 (*info->fprintf_func) (info->stream, "%s", name);
5350 else
5351 {
5352 /* Just print the first byte as a .byte instruction. */
5353 (*info->fprintf_func) (info->stream, ".byte 0x%x",
5354 (unsigned int) priv.the_buffer[0]);
5355 }
5356
5357 return 1;
5358 }
5359
5360 return -1;
5361 }
5362
5363 obufp = obuf;
5364 ckprefix ();
5365
5366 insn_codep = codep;
5367 sizeflag = priv.orig_sizeflag;
5368
5369 FETCH_DATA (info, codep + 1);
5370 two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
5371
5372 if (((prefixes & PREFIX_FWAIT)
5373 && ((*codep < 0xd8) || (*codep > 0xdf)))
5374 || (rex && rex_used))
5375 {
5376 const char *name;
5377
5378 /* fwait not followed by floating point instruction, or rex followed
5379 by other prefixes. Print the first prefix. */
5380 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
5381 if (name == NULL)
5382 name = INTERNAL_DISASSEMBLER_ERROR;
5383 (*info->fprintf_func) (info->stream, "%s", name);
5384 return 1;
5385 }
5386
5387 op = 0;
5388 if (*codep == 0x0f)
5389 {
5390 unsigned char threebyte;
5391 FETCH_DATA (info, codep + 2);
5392 threebyte = *++codep;
5393 dp = &dis386_twobyte[threebyte];
5394 need_modrm = twobyte_has_modrm[*codep];
5395 codep++;
5396 }
5397 else
5398 {
5399 dp = &dis386[*codep];
5400 need_modrm = onebyte_has_modrm[*codep];
5401 codep++;
5402 }
5403
5404 if ((prefixes & PREFIX_REPZ))
5405 {
5406 repz_prefix = "repz ";
5407 used_prefixes |= PREFIX_REPZ;
5408 }
5409 else
5410 repz_prefix = NULL;
5411
5412 if ((prefixes & PREFIX_REPNZ))
5413 {
5414 repnz_prefix = "repnz ";
5415 used_prefixes |= PREFIX_REPNZ;
5416 }
5417 else
5418 repnz_prefix = NULL;
5419
5420 if ((prefixes & PREFIX_LOCK))
5421 {
5422 lock_prefix = "lock ";
5423 used_prefixes |= PREFIX_LOCK;
5424 }
5425 else
5426 lock_prefix = NULL;
5427
5428 addr_prefix = NULL;
5429 if (prefixes & PREFIX_ADDR)
5430 {
5431 sizeflag ^= AFLAG;
5432 if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax)
5433 {
5434 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
5435 addr_prefix = "addr32 ";
5436 else
5437 addr_prefix = "addr16 ";
5438 used_prefixes |= PREFIX_ADDR;
5439 }
5440 }
5441
5442 data_prefix = NULL;
5443 if ((prefixes & PREFIX_DATA))
5444 {
5445 sizeflag ^= DFLAG;
5446 if (dp->op[2].bytemode == cond_jump_mode
5447 && dp->op[0].bytemode == v_mode
5448 && !intel_syntax)
5449 {
5450 if (sizeflag & DFLAG)
5451 data_prefix = "data32 ";
5452 else
5453 data_prefix = "data16 ";
5454 used_prefixes |= PREFIX_DATA;
5455 }
5456 }
5457
5458 if (need_modrm)
5459 {
5460 FETCH_DATA (info, codep + 1);
5461 modrm.mod = (*codep >> 6) & 3;
5462 modrm.reg = (*codep >> 3) & 7;
5463 modrm.rm = *codep & 7;
5464 }
5465
5466 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
5467 {
5468 dofloat (sizeflag);
5469 }
5470 else
5471 {
5472 dp = get_valid_dis386 (dp, info);
5473 if (dp != NULL && putop (dp->name, sizeflag) == 0)
5474 {
5475 for (i = 0; i < MAX_OPERANDS; ++i)
5476 {
5477 obufp = op_out[i];
5478 op_ad = MAX_OPERANDS - 1 - i;
5479 if (dp->op[i].rtn)
5480 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
5481 }
5482 }
5483 }
5484
5485 /* See if any prefixes were not used. If so, print the first one
5486 separately. If we don't do this, we'll wind up printing an
5487 instruction stream which does not precisely correspond to the
5488 bytes we are disassembling. */
5489 if ((prefixes & ~used_prefixes) != 0)
5490 {
5491 const char *name;
5492
5493 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
5494 if (name == NULL)
5495 name = INTERNAL_DISASSEMBLER_ERROR;
5496 (*info->fprintf_func) (info->stream, "%s", name);
5497 return 1;
5498 }
5499 if (rex & ~rex_used)
5500 {
5501 const char *name;
5502 name = prefix_name (rex | 0x40, priv.orig_sizeflag);
5503 if (name == NULL)
5504 name = INTERNAL_DISASSEMBLER_ERROR;
5505 (*info->fprintf_func) (info->stream, "%s ", name);
5506 }
5507
5508 prefix_obuf[0] = 0;
5509 prefix_obufp = prefix_obuf;
5510 if (lock_prefix)
5511 prefix_obufp = stpcpy (prefix_obufp, lock_prefix);
5512 if (repz_prefix)
5513 prefix_obufp = stpcpy (prefix_obufp, repz_prefix);
5514 if (repnz_prefix)
5515 prefix_obufp = stpcpy (prefix_obufp, repnz_prefix);
5516 if (addr_prefix)
5517 prefix_obufp = stpcpy (prefix_obufp, addr_prefix);
5518 if (data_prefix)
5519 prefix_obufp = stpcpy (prefix_obufp, data_prefix);
5520
5521 if (prefix_obuf[0] != 0)
5522 (*info->fprintf_func) (info->stream, "%s", prefix_obuf);
5523
5524 obufp = obuf + strlen (obuf);
5525 for (i = strlen (obuf) + strlen (prefix_obuf); i < 6; i++)
5526 oappend (" ");
5527 oappend (" ");
5528 (*info->fprintf_func) (info->stream, "%s", obuf);
5529
5530 /* The enter and bound instructions are printed with operands in the same
5531 order as the intel book; everything else is printed in reverse order. */
5532 if (intel_syntax || two_source_ops)
5533 {
5534 bfd_vma riprel;
5535
5536 for (i = 0; i < MAX_OPERANDS; ++i)
5537 op_txt[i] = op_out[i];
5538
5539 for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
5540 {
5541 op_ad = op_index[i];
5542 op_index[i] = op_index[MAX_OPERANDS - 1 - i];
5543 op_index[MAX_OPERANDS - 1 - i] = op_ad;
5544 riprel = op_riprel[i];
5545 op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
5546 op_riprel[MAX_OPERANDS - 1 - i] = riprel;
5547 }
5548 }
5549 else
5550 {
5551 for (i = 0; i < MAX_OPERANDS; ++i)
5552 op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
5553 }
5554
5555 needcomma = 0;
5556 for (i = 0; i < MAX_OPERANDS; ++i)
5557 if (*op_txt[i])
5558 {
5559 if (needcomma)
5560 (*info->fprintf_func) (info->stream, ",");
5561 if (op_index[i] != -1 && !op_riprel[i])
5562 (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
5563 else
5564 (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
5565 needcomma = 1;
5566 }
5567
5568 for (i = 0; i < MAX_OPERANDS; i++)
5569 if (op_index[i] != -1 && op_riprel[i])
5570 {
5571 (*info->fprintf_func) (info->stream, " # ");
5572 (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
5573 + op_address[op_index[i]]), info);
5574 break;
5575 }
5576 return codep - priv.the_buffer;
5577 }
5578
5579 static const char *float_mem[] = {
5580 /* d8 */
5581 "fadd{s|}",
5582 "fmul{s|}",
5583 "fcom{s|}",
5584 "fcomp{s|}",
5585 "fsub{s|}",
5586 "fsubr{s|}",
5587 "fdiv{s|}",
5588 "fdivr{s|}",
5589 /* d9 */
5590 "fld{s|}",
5591 "(bad)",
5592 "fst{s|}",
5593 "fstp{s|}",
5594 "fldenvIC",
5595 "fldcw",
5596 "fNstenvIC",
5597 "fNstcw",
5598 /* da */
5599 "fiadd{l|}",
5600 "fimul{l|}",
5601 "ficom{l|}",
5602 "ficomp{l|}",
5603 "fisub{l|}",
5604 "fisubr{l|}",
5605 "fidiv{l|}",
5606 "fidivr{l|}",
5607 /* db */
5608 "fild{l|}",
5609 "fisttp{l|}",
5610 "fist{l|}",
5611 "fistp{l|}",
5612 "(bad)",
5613 "fld{t||t|}",
5614 "(bad)",
5615 "fstp{t||t|}",
5616 /* dc */
5617 "fadd{l|}",
5618 "fmul{l|}",
5619 "fcom{l|}",
5620 "fcomp{l|}",
5621 "fsub{l|}",
5622 "fsubr{l|}",
5623 "fdiv{l|}",
5624 "fdivr{l|}",
5625 /* dd */
5626 "fld{l|}",
5627 "fisttp{ll|}",
5628 "fst{l||}",
5629 "fstp{l|}",
5630 "frstorIC",
5631 "(bad)",
5632 "fNsaveIC",
5633 "fNstsw",
5634 /* de */
5635 "fiadd",
5636 "fimul",
5637 "ficom",
5638 "ficomp",
5639 "fisub",
5640 "fisubr",
5641 "fidiv",
5642 "fidivr",
5643 /* df */
5644 "fild",
5645 "fisttp",
5646 "fist",
5647 "fistp",
5648 "fbld",
5649 "fild{ll|}",
5650 "fbstp",
5651 "fistp{ll|}",
5652 };
5653
5654 static const unsigned char float_mem_mode[] = {
5655 /* d8 */
5656 d_mode,
5657 d_mode,
5658 d_mode,
5659 d_mode,
5660 d_mode,
5661 d_mode,
5662 d_mode,
5663 d_mode,
5664 /* d9 */
5665 d_mode,
5666 0,
5667 d_mode,
5668 d_mode,
5669 0,
5670 w_mode,
5671 0,
5672 w_mode,
5673 /* da */
5674 d_mode,
5675 d_mode,
5676 d_mode,
5677 d_mode,
5678 d_mode,
5679 d_mode,
5680 d_mode,
5681 d_mode,
5682 /* db */
5683 d_mode,
5684 d_mode,
5685 d_mode,
5686 d_mode,
5687 0,
5688 t_mode,
5689 0,
5690 t_mode,
5691 /* dc */
5692 q_mode,
5693 q_mode,
5694 q_mode,
5695 q_mode,
5696 q_mode,
5697 q_mode,
5698 q_mode,
5699 q_mode,
5700 /* dd */
5701 q_mode,
5702 q_mode,
5703 q_mode,
5704 q_mode,
5705 0,
5706 0,
5707 0,
5708 w_mode,
5709 /* de */
5710 w_mode,
5711 w_mode,
5712 w_mode,
5713 w_mode,
5714 w_mode,
5715 w_mode,
5716 w_mode,
5717 w_mode,
5718 /* df */
5719 w_mode,
5720 w_mode,
5721 w_mode,
5722 w_mode,
5723 t_mode,
5724 q_mode,
5725 t_mode,
5726 q_mode
5727 };
5728
5729 #define ST { OP_ST, 0 }
5730 #define STi { OP_STi, 0 }
5731
5732 #define FGRPd9_2 NULL, { { NULL, 0 } }
5733 #define FGRPd9_4 NULL, { { NULL, 1 } }
5734 #define FGRPd9_5 NULL, { { NULL, 2 } }
5735 #define FGRPd9_6 NULL, { { NULL, 3 } }
5736 #define FGRPd9_7 NULL, { { NULL, 4 } }
5737 #define FGRPda_5 NULL, { { NULL, 5 } }
5738 #define FGRPdb_4 NULL, { { NULL, 6 } }
5739 #define FGRPde_3 NULL, { { NULL, 7 } }
5740 #define FGRPdf_4 NULL, { { NULL, 8 } }
5741
5742 static const struct dis386 float_reg[][8] = {
5743 /* d8 */
5744 {
5745 { "fadd", { ST, STi } },
5746 { "fmul", { ST, STi } },
5747 { "fcom", { STi } },
5748 { "fcomp", { STi } },
5749 { "fsub", { ST, STi } },
5750 { "fsubr", { ST, STi } },
5751 { "fdiv", { ST, STi } },
5752 { "fdivr", { ST, STi } },
5753 },
5754 /* d9 */
5755 {
5756 { "fld", { STi } },
5757 { "fxch", { STi } },
5758 { FGRPd9_2 },
5759 { "(bad)", { XX } },
5760 { FGRPd9_4 },
5761 { FGRPd9_5 },
5762 { FGRPd9_6 },
5763 { FGRPd9_7 },
5764 },
5765 /* da */
5766 {
5767 { "fcmovb", { ST, STi } },
5768 { "fcmove", { ST, STi } },
5769 { "fcmovbe",{ ST, STi } },
5770 { "fcmovu", { ST, STi } },
5771 { "(bad)", { XX } },
5772 { FGRPda_5 },
5773 { "(bad)", { XX } },
5774 { "(bad)", { XX } },
5775 },
5776 /* db */
5777 {
5778 { "fcmovnb",{ ST, STi } },
5779 { "fcmovne",{ ST, STi } },
5780 { "fcmovnbe",{ ST, STi } },
5781 { "fcmovnu",{ ST, STi } },
5782 { FGRPdb_4 },
5783 { "fucomi", { ST, STi } },
5784 { "fcomi", { ST, STi } },
5785 { "(bad)", { XX } },
5786 },
5787 /* dc */
5788 {
5789 { "fadd", { STi, ST } },
5790 { "fmul", { STi, ST } },
5791 { "(bad)", { XX } },
5792 { "(bad)", { XX } },
5793 #if SYSV386_COMPAT
5794 { "fsub", { STi, ST } },
5795 { "fsubr", { STi, ST } },
5796 { "fdiv", { STi, ST } },
5797 { "fdivr", { STi, ST } },
5798 #else
5799 { "fsubr", { STi, ST } },
5800 { "fsub", { STi, ST } },
5801 { "fdivr", { STi, ST } },
5802 { "fdiv", { STi, ST } },
5803 #endif
5804 },
5805 /* dd */
5806 {
5807 { "ffree", { STi } },
5808 { "(bad)", { XX } },
5809 { "fst", { STi } },
5810 { "fstp", { STi } },
5811 { "fucom", { STi } },
5812 { "fucomp", { STi } },
5813 { "(bad)", { XX } },
5814 { "(bad)", { XX } },
5815 },
5816 /* de */
5817 {
5818 { "faddp", { STi, ST } },
5819 { "fmulp", { STi, ST } },
5820 { "(bad)", { XX } },
5821 { FGRPde_3 },
5822 #if SYSV386_COMPAT
5823 { "fsubp", { STi, ST } },
5824 { "fsubrp", { STi, ST } },
5825 { "fdivp", { STi, ST } },
5826 { "fdivrp", { STi, ST } },
5827 #else
5828 { "fsubrp", { STi, ST } },
5829 { "fsubp", { STi, ST } },
5830 { "fdivrp", { STi, ST } },
5831 { "fdivp", { STi, ST } },
5832 #endif
5833 },
5834 /* df */
5835 {
5836 { "ffreep", { STi } },
5837 { "(bad)", { XX } },
5838 { "(bad)", { XX } },
5839 { "(bad)", { XX } },
5840 { FGRPdf_4 },
5841 { "fucomip", { ST, STi } },
5842 { "fcomip", { ST, STi } },
5843 { "(bad)", { XX } },
5844 },
5845 };
5846
5847 static char *fgrps[][8] = {
5848 /* d9_2 0 */
5849 {
5850 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
5851 },
5852
5853 /* d9_4 1 */
5854 {
5855 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
5856 },
5857
5858 /* d9_5 2 */
5859 {
5860 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
5861 },
5862
5863 /* d9_6 3 */
5864 {
5865 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
5866 },
5867
5868 /* d9_7 4 */
5869 {
5870 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
5871 },
5872
5873 /* da_5 5 */
5874 {
5875 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
5876 },
5877
5878 /* db_4 6 */
5879 {
5880 "feni(287 only)","fdisi(287 only)","fNclex","fNinit",
5881 "fNsetpm(287 only)","(bad)","(bad)","(bad)",
5882 },
5883
5884 /* de_3 7 */
5885 {
5886 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
5887 },
5888
5889 /* df_4 8 */
5890 {
5891 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
5892 },
5893 };
5894
5895 static void
5896 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
5897 int sizeflag ATTRIBUTE_UNUSED)
5898 {
5899 /* Skip mod/rm byte. */
5900 MODRM_CHECK;
5901 codep++;
5902 }
5903
5904 static void
5905 dofloat (int sizeflag)
5906 {
5907 const struct dis386 *dp;
5908 unsigned char floatop;
5909
5910 floatop = codep[-1];
5911
5912 if (modrm.mod != 3)
5913 {
5914 int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
5915
5916 putop (float_mem[fp_indx], sizeflag);
5917 obufp = op_out[0];
5918 op_ad = 2;
5919 OP_E (float_mem_mode[fp_indx], sizeflag);
5920 return;
5921 }
5922 /* Skip mod/rm byte. */
5923 MODRM_CHECK;
5924 codep++;
5925
5926 dp = &float_reg[floatop - 0xd8][modrm.reg];
5927 if (dp->name == NULL)
5928 {
5929 putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
5930
5931 /* Instruction fnstsw is only one with strange arg. */
5932 if (floatop == 0xdf && codep[-1] == 0xe0)
5933 strcpy (op_out[0], names16[0]);
5934 }
5935 else
5936 {
5937 putop (dp->name, sizeflag);
5938
5939 obufp = op_out[0];
5940 op_ad = 2;
5941 if (dp->op[0].rtn)
5942 (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
5943
5944 obufp = op_out[1];
5945 op_ad = 1;
5946 if (dp->op[1].rtn)
5947 (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
5948 }
5949 }
5950
5951 static void
5952 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
5953 {
5954 oappend ("%st" + intel_syntax);
5955 }
5956
5957 static void
5958 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
5959 {
5960 sprintf (scratchbuf, "%%st(%d)", modrm.rm);
5961 oappend (scratchbuf + intel_syntax);
5962 }
5963
5964 /* Capital letters in template are macros. */
5965 static int
5966 putop (const char *template, int sizeflag)
5967 {
5968 const char *p;
5969 int alt = 0;
5970
5971 for (p = template; *p; p++)
5972 {
5973 switch (*p)
5974 {
5975 default:
5976 *obufp++ = *p;
5977 break;
5978 case '{':
5979 alt = 0;
5980 if (intel_syntax)
5981 {
5982 while (*++p != '|')
5983 if (*p == '}' || *p == '\0')
5984 abort ();
5985 }
5986 /* Fall through. */
5987 case 'I':
5988 alt = 1;
5989 continue;
5990 case '|':
5991 while (*++p != '}')
5992 {
5993 if (*p == '\0')
5994 abort ();
5995 }
5996 break;
5997 case '}':
5998 break;
5999 case 'A':
6000 if (intel_syntax)
6001 break;
6002 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
6003 *obufp++ = 'b';
6004 break;
6005 case 'B':
6006 if (intel_syntax)
6007 break;
6008 if (sizeflag & SUFFIX_ALWAYS)
6009 *obufp++ = 'b';
6010 break;
6011 case 'C':
6012 if (intel_syntax && !alt)
6013 break;
6014 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
6015 {
6016 if (sizeflag & DFLAG)
6017 *obufp++ = intel_syntax ? 'd' : 'l';
6018 else
6019 *obufp++ = intel_syntax ? 'w' : 's';
6020 used_prefixes |= (prefixes & PREFIX_DATA);
6021 }
6022 break;
6023 case 'D':
6024 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
6025 break;
6026 USED_REX (REX_W);
6027 if (modrm.mod == 3)
6028 {
6029 if (rex & REX_W)
6030 *obufp++ = 'q';
6031 else if (sizeflag & DFLAG)
6032 *obufp++ = intel_syntax ? 'd' : 'l';
6033 else
6034 *obufp++ = 'w';
6035 used_prefixes |= (prefixes & PREFIX_DATA);
6036 }
6037 else
6038 *obufp++ = 'w';
6039 break;
6040 case 'E': /* For jcxz/jecxz */
6041 if (address_mode == mode_64bit)
6042 {
6043 if (sizeflag & AFLAG)
6044 *obufp++ = 'r';
6045 else
6046 *obufp++ = 'e';
6047 }
6048 else
6049 if (sizeflag & AFLAG)
6050 *obufp++ = 'e';
6051 used_prefixes |= (prefixes & PREFIX_ADDR);
6052 break;
6053 case 'F':
6054 if (intel_syntax)
6055 break;
6056 if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
6057 {
6058 if (sizeflag & AFLAG)
6059 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
6060 else
6061 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
6062 used_prefixes |= (prefixes & PREFIX_ADDR);
6063 }
6064 break;
6065 case 'G':
6066 if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
6067 break;
6068 if ((rex & REX_W) || (sizeflag & DFLAG))
6069 *obufp++ = 'l';
6070 else
6071 *obufp++ = 'w';
6072 if (!(rex & REX_W))
6073 used_prefixes |= (prefixes & PREFIX_DATA);
6074 break;
6075 case 'H':
6076 if (intel_syntax)
6077 break;
6078 if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
6079 || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
6080 {
6081 used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
6082 *obufp++ = ',';
6083 *obufp++ = 'p';
6084 if (prefixes & PREFIX_DS)
6085 *obufp++ = 't';
6086 else
6087 *obufp++ = 'n';
6088 }
6089 break;
6090 case 'J':
6091 if (intel_syntax)
6092 break;
6093 *obufp++ = 'l';
6094 break;
6095 case 'K':
6096 USED_REX (REX_W);
6097 if (rex & REX_W)
6098 *obufp++ = 'q';
6099 else
6100 *obufp++ = 'd';
6101 break;
6102 case 'Z':
6103 if (intel_syntax)
6104 break;
6105 if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
6106 {
6107 *obufp++ = 'q';
6108 break;
6109 }
6110 /* Fall through. */
6111 case 'L':
6112 if (intel_syntax)
6113 break;
6114 if (sizeflag & SUFFIX_ALWAYS)
6115 *obufp++ = 'l';
6116 break;
6117 case 'N':
6118 if ((prefixes & PREFIX_FWAIT) == 0)
6119 *obufp++ = 'n';
6120 else
6121 used_prefixes |= PREFIX_FWAIT;
6122 break;
6123 case 'O':
6124 USED_REX (REX_W);
6125 if (rex & REX_W)
6126 *obufp++ = 'o';
6127 else if (intel_syntax && (sizeflag & DFLAG))
6128 *obufp++ = 'q';
6129 else
6130 *obufp++ = 'd';
6131 if (!(rex & REX_W))
6132 used_prefixes |= (prefixes & PREFIX_DATA);
6133 break;
6134 case 'T':
6135 if (intel_syntax)
6136 break;
6137 if (address_mode == mode_64bit && (sizeflag & DFLAG))
6138 {
6139 *obufp++ = 'q';
6140 break;
6141 }
6142 /* Fall through. */
6143 case 'P':
6144 if (intel_syntax)
6145 break;
6146 if ((prefixes & PREFIX_DATA)
6147 || (rex & REX_W)
6148 || (sizeflag & SUFFIX_ALWAYS))
6149 {
6150 USED_REX (REX_W);
6151 if (rex & REX_W)
6152 *obufp++ = 'q';
6153 else
6154 {
6155 if (sizeflag & DFLAG)
6156 *obufp++ = 'l';
6157 else
6158 *obufp++ = 'w';
6159 }
6160 used_prefixes |= (prefixes & PREFIX_DATA);
6161 }
6162 break;
6163 case 'U':
6164 if (intel_syntax)
6165 break;
6166 if (address_mode == mode_64bit && (sizeflag & DFLAG))
6167 {
6168 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
6169 *obufp++ = 'q';
6170 break;
6171 }
6172 /* Fall through. */
6173 case 'Q':
6174 if (intel_syntax && !alt)
6175 break;
6176 USED_REX (REX_W);
6177 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
6178 {
6179 if (rex & REX_W)
6180 *obufp++ = 'q';
6181 else
6182 {
6183 if (sizeflag & DFLAG)
6184 *obufp++ = intel_syntax ? 'd' : 'l';
6185 else
6186 *obufp++ = 'w';
6187 }
6188 used_prefixes |= (prefixes & PREFIX_DATA);
6189 }
6190 break;
6191 case 'R':
6192 USED_REX (REX_W);
6193 if (rex & REX_W)
6194 *obufp++ = 'q';
6195 else if (sizeflag & DFLAG)
6196 {
6197 if (intel_syntax)
6198 *obufp++ = 'd';
6199 else
6200 *obufp++ = 'l';
6201 }
6202 else
6203 *obufp++ = 'w';
6204 if (intel_syntax && !p[1]
6205 && ((rex & REX_W) || (sizeflag & DFLAG)))
6206 *obufp++ = 'e';
6207 if (!(rex & REX_W))
6208 used_prefixes |= (prefixes & PREFIX_DATA);
6209 break;
6210 case 'V':
6211 if (intel_syntax)
6212 break;
6213 if (address_mode == mode_64bit && (sizeflag & DFLAG))
6214 {
6215 if (sizeflag & SUFFIX_ALWAYS)
6216 *obufp++ = 'q';
6217 break;
6218 }
6219 /* Fall through. */
6220 case 'S':
6221 if (intel_syntax)
6222 break;
6223 if (sizeflag & SUFFIX_ALWAYS)
6224 {
6225 if (rex & REX_W)
6226 *obufp++ = 'q';
6227 else
6228 {
6229 if (sizeflag & DFLAG)
6230 *obufp++ = 'l';
6231 else
6232 *obufp++ = 'w';
6233 used_prefixes |= (prefixes & PREFIX_DATA);
6234 }
6235 }
6236 break;
6237 case 'X':
6238 if (prefixes & PREFIX_DATA)
6239 *obufp++ = 'd';
6240 else
6241 *obufp++ = 's';
6242 used_prefixes |= (prefixes & PREFIX_DATA);
6243 break;
6244 case 'Y':
6245 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
6246 break;
6247 if (rex & REX_W)
6248 {
6249 USED_REX (REX_W);
6250 *obufp++ = 'q';
6251 }
6252 break;
6253 /* implicit operand size 'l' for i386 or 'q' for x86-64 */
6254 case 'W':
6255 /* operand size flag for cwtl, cbtw */
6256 USED_REX (REX_W);
6257 if (rex & REX_W)
6258 {
6259 if (intel_syntax)
6260 *obufp++ = 'd';
6261 else
6262 *obufp++ = 'l';
6263 }
6264 else if (sizeflag & DFLAG)
6265 *obufp++ = 'w';
6266 else
6267 *obufp++ = 'b';
6268 if (!(rex & REX_W))
6269 used_prefixes |= (prefixes & PREFIX_DATA);
6270 break;
6271 }
6272 alt = 0;
6273 }
6274 *obufp = 0;
6275 return 0;
6276 }
6277
6278 static void
6279 oappend (const char *s)
6280 {
6281 strcpy (obufp, s);
6282 obufp += strlen (s);
6283 }
6284
6285 static void
6286 append_seg (void)
6287 {
6288 if (prefixes & PREFIX_CS)
6289 {
6290 used_prefixes |= PREFIX_CS;
6291 oappend ("%cs:" + intel_syntax);
6292 }
6293 if (prefixes & PREFIX_DS)
6294 {
6295 used_prefixes |= PREFIX_DS;
6296 oappend ("%ds:" + intel_syntax);
6297 }
6298 if (prefixes & PREFIX_SS)
6299 {
6300 used_prefixes |= PREFIX_SS;
6301 oappend ("%ss:" + intel_syntax);
6302 }
6303 if (prefixes & PREFIX_ES)
6304 {
6305 used_prefixes |= PREFIX_ES;
6306 oappend ("%es:" + intel_syntax);
6307 }
6308 if (prefixes & PREFIX_FS)
6309 {
6310 used_prefixes |= PREFIX_FS;
6311 oappend ("%fs:" + intel_syntax);
6312 }
6313 if (prefixes & PREFIX_GS)
6314 {
6315 used_prefixes |= PREFIX_GS;
6316 oappend ("%gs:" + intel_syntax);
6317 }
6318 }
6319
6320 static void
6321 OP_indirE (int bytemode, int sizeflag)
6322 {
6323 if (!intel_syntax)
6324 oappend ("*");
6325 OP_E (bytemode, sizeflag);
6326 }
6327
6328 static void
6329 print_operand_value (char *buf, int hex, bfd_vma disp)
6330 {
6331 if (address_mode == mode_64bit)
6332 {
6333 if (hex)
6334 {
6335 char tmp[30];
6336 int i;
6337 buf[0] = '0';
6338 buf[1] = 'x';
6339 sprintf_vma (tmp, disp);
6340 for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
6341 strcpy (buf + 2, tmp + i);
6342 }
6343 else
6344 {
6345 bfd_signed_vma v = disp;
6346 char tmp[30];
6347 int i;
6348 if (v < 0)
6349 {
6350 *(buf++) = '-';
6351 v = -disp;
6352 /* Check for possible overflow on 0x8000000000000000. */
6353 if (v < 0)
6354 {
6355 strcpy (buf, "9223372036854775808");
6356 return;
6357 }
6358 }
6359 if (!v)
6360 {
6361 strcpy (buf, "0");
6362 return;
6363 }
6364
6365 i = 0;
6366 tmp[29] = 0;
6367 while (v)
6368 {
6369 tmp[28 - i] = (v % 10) + '0';
6370 v /= 10;
6371 i++;
6372 }
6373 strcpy (buf, tmp + 29 - i);
6374 }
6375 }
6376 else
6377 {
6378 if (hex)
6379 sprintf (buf, "0x%x", (unsigned int) disp);
6380 else
6381 sprintf (buf, "%d", (int) disp);
6382 }
6383 }
6384
6385 /* Put DISP in BUF as signed hex number. */
6386
6387 static void
6388 print_displacement (char *buf, bfd_vma disp)
6389 {
6390 bfd_signed_vma val = disp;
6391 char tmp[30];
6392 int i, j = 0;
6393
6394 if (val < 0)
6395 {
6396 buf[j++] = '-';
6397 val = -disp;
6398
6399 /* Check for possible overflow. */
6400 if (val < 0)
6401 {
6402 switch (address_mode)
6403 {
6404 case mode_64bit:
6405 strcpy (buf + j, "0x8000000000000000");
6406 break;
6407 case mode_32bit:
6408 strcpy (buf + j, "0x80000000");
6409 break;
6410 case mode_16bit:
6411 strcpy (buf + j, "0x8000");
6412 break;
6413 }
6414 return;
6415 }
6416 }
6417
6418 buf[j++] = '0';
6419 buf[j++] = 'x';
6420
6421 sprintf_vma (tmp, val);
6422 for (i = 0; tmp[i] == '0'; i++)
6423 continue;
6424 if (tmp[i] == '\0')
6425 i--;
6426 strcpy (buf + j, tmp + i);
6427 }
6428
6429 static void
6430 intel_operand_size (int bytemode, int sizeflag)
6431 {
6432 switch (bytemode)
6433 {
6434 case b_mode:
6435 case dqb_mode:
6436 oappend ("BYTE PTR ");
6437 break;
6438 case w_mode:
6439 case dqw_mode:
6440 oappend ("WORD PTR ");
6441 break;
6442 case stack_v_mode:
6443 if (address_mode == mode_64bit && (sizeflag & DFLAG))
6444 {
6445 oappend ("QWORD PTR ");
6446 used_prefixes |= (prefixes & PREFIX_DATA);
6447 break;
6448 }
6449 /* FALLTHRU */
6450 case v_mode:
6451 case dq_mode:
6452 USED_REX (REX_W);
6453 if (rex & REX_W)
6454 oappend ("QWORD PTR ");
6455 else if ((sizeflag & DFLAG) || bytemode == dq_mode)
6456 oappend ("DWORD PTR ");
6457 else
6458 oappend ("WORD PTR ");
6459 used_prefixes |= (prefixes & PREFIX_DATA);
6460 break;
6461 case z_mode:
6462 if ((rex & REX_W) || (sizeflag & DFLAG))
6463 *obufp++ = 'D';
6464 oappend ("WORD PTR ");
6465 if (!(rex & REX_W))
6466 used_prefixes |= (prefixes & PREFIX_DATA);
6467 break;
6468 case d_mode:
6469 case dqd_mode:
6470 oappend ("DWORD PTR ");
6471 break;
6472 case q_mode:
6473 oappend ("QWORD PTR ");
6474 break;
6475 case m_mode:
6476 if (address_mode == mode_64bit)
6477 oappend ("QWORD PTR ");
6478 else
6479 oappend ("DWORD PTR ");
6480 break;
6481 case f_mode:
6482 if (sizeflag & DFLAG)
6483 oappend ("FWORD PTR ");
6484 else
6485 oappend ("DWORD PTR ");
6486 used_prefixes |= (prefixes & PREFIX_DATA);
6487 break;
6488 case t_mode:
6489 oappend ("TBYTE PTR ");
6490 break;
6491 case x_mode:
6492 oappend ("XMMWORD PTR ");
6493 break;
6494 case o_mode:
6495 oappend ("OWORD PTR ");
6496 break;
6497 default:
6498 break;
6499 }
6500 }
6501
6502 static void
6503 OP_E_extended (int bytemode, int sizeflag, int has_drex)
6504 {
6505 bfd_vma disp;
6506 int add = 0;
6507 int riprel = 0;
6508 USED_REX (REX_B);
6509 if (rex & REX_B)
6510 add += 8;
6511
6512 /* Skip mod/rm byte. */
6513 MODRM_CHECK;
6514 codep++;
6515
6516 if (modrm.mod == 3)
6517 {
6518 switch (bytemode)
6519 {
6520 case b_mode:
6521 USED_REX (0);
6522 if (rex)
6523 oappend (names8rex[modrm.rm + add]);
6524 else
6525 oappend (names8[modrm.rm + add]);
6526 break;
6527 case w_mode:
6528 oappend (names16[modrm.rm + add]);
6529 break;
6530 case d_mode:
6531 oappend (names32[modrm.rm + add]);
6532 break;
6533 case q_mode:
6534 oappend (names64[modrm.rm + add]);
6535 break;
6536 case m_mode:
6537 if (address_mode == mode_64bit)
6538 oappend (names64[modrm.rm + add]);
6539 else
6540 oappend (names32[modrm.rm + add]);
6541 break;
6542 case stack_v_mode:
6543 if (address_mode == mode_64bit && (sizeflag & DFLAG))
6544 {
6545 oappend (names64[modrm.rm + add]);
6546 used_prefixes |= (prefixes & PREFIX_DATA);
6547 break;
6548 }
6549 bytemode = v_mode;
6550 /* FALLTHRU */
6551 case v_mode:
6552 case dq_mode:
6553 case dqb_mode:
6554 case dqd_mode:
6555 case dqw_mode:
6556 USED_REX (REX_W);
6557 if (rex & REX_W)
6558 oappend (names64[modrm.rm + add]);
6559 else if ((sizeflag & DFLAG) || bytemode != v_mode)
6560 oappend (names32[modrm.rm + add]);
6561 else
6562 oappend (names16[modrm.rm + add]);
6563 used_prefixes |= (prefixes & PREFIX_DATA);
6564 break;
6565 case 0:
6566 break;
6567 default:
6568 oappend (INTERNAL_DISASSEMBLER_ERROR);
6569 break;
6570 }
6571 return;
6572 }
6573
6574 disp = 0;
6575 if (intel_syntax)
6576 intel_operand_size (bytemode, sizeflag);
6577 append_seg ();
6578
6579 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
6580 {
6581 /* 32/64 bit address mode */
6582 int havedisp;
6583 int havesib;
6584 int havebase;
6585 int haveindex;
6586 int needindex;
6587 int base;
6588 int index = 0;
6589 int scale = 0;
6590
6591 havesib = 0;
6592 havebase = 1;
6593 haveindex = 0;
6594 base = modrm.rm;
6595
6596 if (base == 4)
6597 {
6598 havesib = 1;
6599 FETCH_DATA (the_info, codep + 1);
6600 index = (*codep >> 3) & 7;
6601 scale = (*codep >> 6) & 3;
6602 base = *codep & 7;
6603 USED_REX (REX_X);
6604 if (rex & REX_X)
6605 index += 8;
6606 haveindex = index != 4;
6607 codep++;
6608 }
6609 base += add;
6610
6611 /* If we have a DREX byte, skip it now
6612 (it has already been handled) */
6613 if (has_drex)
6614 {
6615 FETCH_DATA (the_info, codep + 1);
6616 codep++;
6617 }
6618
6619 switch (modrm.mod)
6620 {
6621 case 0:
6622 if ((base & 7) == 5)
6623 {
6624 havebase = 0;
6625 if (address_mode == mode_64bit && !havesib)
6626 riprel = 1;
6627 disp = get32s ();
6628 }
6629 break;
6630 case 1:
6631 FETCH_DATA (the_info, codep + 1);
6632 disp = *codep++;
6633 if ((disp & 0x80) != 0)
6634 disp -= 0x100;
6635 break;
6636 case 2:
6637 disp = get32s ();
6638 break;
6639 }
6640
6641 /* In 32bit mode, we need index register to tell [offset] from
6642 [eiz*1 + offset]. */
6643 needindex = (havesib
6644 && !havebase
6645 && !haveindex
6646 && address_mode == mode_32bit);
6647 havedisp = (havebase
6648 || needindex
6649 || (havesib && (haveindex || scale != 0)));
6650
6651 if (!intel_syntax)
6652 if (modrm.mod != 0 || (base & 7) == 5)
6653 {
6654 if (havedisp || riprel)
6655 print_displacement (scratchbuf, disp);
6656 else
6657 print_operand_value (scratchbuf, 1, disp);
6658 oappend (scratchbuf);
6659 if (riprel)
6660 {
6661 set_op (disp, 1);
6662 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
6663 }
6664 }
6665
6666 if (havebase || haveindex || riprel)
6667 used_prefixes |= PREFIX_ADDR;
6668
6669 if (havedisp || (intel_syntax && riprel))
6670 {
6671 *obufp++ = open_char;
6672 if (intel_syntax && riprel)
6673 {
6674 set_op (disp, 1);
6675 oappend (sizeflag & AFLAG ? "rip" : "eip");
6676 }
6677 *obufp = '\0';
6678 if (havebase)
6679 oappend (address_mode == mode_64bit && (sizeflag & AFLAG)
6680 ? names64[base] : names32[base]);
6681 if (havesib)
6682 {
6683 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
6684 print index to tell base + index from base. */
6685 if (scale != 0
6686 || needindex
6687 || haveindex
6688 || (havebase && base != ESP_REG_NUM))
6689 {
6690 if (!intel_syntax || havebase)
6691 {
6692 *obufp++ = separator_char;
6693 *obufp = '\0';
6694 }
6695 if (haveindex)
6696 oappend (address_mode == mode_64bit
6697 && (sizeflag & AFLAG)
6698 ? names64[index] : names32[index]);
6699 else
6700 oappend (address_mode == mode_64bit
6701 && (sizeflag & AFLAG)
6702 ? index64 : index32);
6703
6704 *obufp++ = scale_char;
6705 *obufp = '\0';
6706 sprintf (scratchbuf, "%d", 1 << scale);
6707 oappend (scratchbuf);
6708 }
6709 }
6710 if (intel_syntax
6711 && (disp || modrm.mod != 0 || (base & 7) == 5))
6712 {
6713 if (!havedisp || (bfd_signed_vma) disp >= 0)
6714 {
6715 *obufp++ = '+';
6716 *obufp = '\0';
6717 }
6718 else if (modrm.mod != 1)
6719 {
6720 *obufp++ = '-';
6721 *obufp = '\0';
6722 disp = - (bfd_signed_vma) disp;
6723 }
6724
6725 if (havedisp)
6726 print_displacement (scratchbuf, disp);
6727 else
6728 print_operand_value (scratchbuf, 1, disp);
6729 oappend (scratchbuf);
6730 }
6731
6732 *obufp++ = close_char;
6733 *obufp = '\0';
6734 }
6735 else if (intel_syntax)
6736 {
6737 if (modrm.mod != 0 || (base & 7) == 5)
6738 {
6739 if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
6740 | PREFIX_ES | PREFIX_FS | PREFIX_GS))
6741 ;
6742 else
6743 {
6744 oappend (names_seg[ds_reg - es_reg]);
6745 oappend (":");
6746 }
6747 print_operand_value (scratchbuf, 1, disp);
6748 oappend (scratchbuf);
6749 }
6750 }
6751 }
6752 else
6753 { /* 16 bit address mode */
6754 switch (modrm.mod)
6755 {
6756 case 0:
6757 if (modrm.rm == 6)
6758 {
6759 disp = get16 ();
6760 if ((disp & 0x8000) != 0)
6761 disp -= 0x10000;
6762 }
6763 break;
6764 case 1:
6765 FETCH_DATA (the_info, codep + 1);
6766 disp = *codep++;
6767 if ((disp & 0x80) != 0)
6768 disp -= 0x100;
6769 break;
6770 case 2:
6771 disp = get16 ();
6772 if ((disp & 0x8000) != 0)
6773 disp -= 0x10000;
6774 break;
6775 }
6776
6777 if (!intel_syntax)
6778 if (modrm.mod != 0 || modrm.rm == 6)
6779 {
6780 print_displacement (scratchbuf, disp);
6781 oappend (scratchbuf);
6782 }
6783
6784 if (modrm.mod != 0 || modrm.rm != 6)
6785 {
6786 *obufp++ = open_char;
6787 *obufp = '\0';
6788 oappend (index16[modrm.rm]);
6789 if (intel_syntax
6790 && (disp || modrm.mod != 0 || modrm.rm == 6))
6791 {
6792 if ((bfd_signed_vma) disp >= 0)
6793 {
6794 *obufp++ = '+';
6795 *obufp = '\0';
6796 }
6797 else if (modrm.mod != 1)
6798 {
6799 *obufp++ = '-';
6800 *obufp = '\0';
6801 disp = - (bfd_signed_vma) disp;
6802 }
6803
6804 print_displacement (scratchbuf, disp);
6805 oappend (scratchbuf);
6806 }
6807
6808 *obufp++ = close_char;
6809 *obufp = '\0';
6810 }
6811 else if (intel_syntax)
6812 {
6813 if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
6814 | PREFIX_ES | PREFIX_FS | PREFIX_GS))
6815 ;
6816 else
6817 {
6818 oappend (names_seg[ds_reg - es_reg]);
6819 oappend (":");
6820 }
6821 print_operand_value (scratchbuf, 1, disp & 0xffff);
6822 oappend (scratchbuf);
6823 }
6824 }
6825 }
6826
6827 static void
6828 OP_E (int bytemode, int sizeflag)
6829 {
6830 OP_E_extended (bytemode, sizeflag, 0);
6831 }
6832
6833
6834 static void
6835 OP_G (int bytemode, int sizeflag)
6836 {
6837 int add = 0;
6838 USED_REX (REX_R);
6839 if (rex & REX_R)
6840 add += 8;
6841 switch (bytemode)
6842 {
6843 case b_mode:
6844 USED_REX (0);
6845 if (rex)
6846 oappend (names8rex[modrm.reg + add]);
6847 else
6848 oappend (names8[modrm.reg + add]);
6849 break;
6850 case w_mode:
6851 oappend (names16[modrm.reg + add]);
6852 break;
6853 case d_mode:
6854 oappend (names32[modrm.reg + add]);
6855 break;
6856 case q_mode:
6857 oappend (names64[modrm.reg + add]);
6858 break;
6859 case v_mode:
6860 case dq_mode:
6861 case dqb_mode:
6862 case dqd_mode:
6863 case dqw_mode:
6864 USED_REX (REX_W);
6865 if (rex & REX_W)
6866 oappend (names64[modrm.reg + add]);
6867 else if ((sizeflag & DFLAG) || bytemode != v_mode)
6868 oappend (names32[modrm.reg + add]);
6869 else
6870 oappend (names16[modrm.reg + add]);
6871 used_prefixes |= (prefixes & PREFIX_DATA);
6872 break;
6873 case m_mode:
6874 if (address_mode == mode_64bit)
6875 oappend (names64[modrm.reg + add]);
6876 else
6877 oappend (names32[modrm.reg + add]);
6878 break;
6879 default:
6880 oappend (INTERNAL_DISASSEMBLER_ERROR);
6881 break;
6882 }
6883 }
6884
6885 static bfd_vma
6886 get64 (void)
6887 {
6888 bfd_vma x;
6889 #ifdef BFD64
6890 unsigned int a;
6891 unsigned int b;
6892
6893 FETCH_DATA (the_info, codep + 8);
6894 a = *codep++ & 0xff;
6895 a |= (*codep++ & 0xff) << 8;
6896 a |= (*codep++ & 0xff) << 16;
6897 a |= (*codep++ & 0xff) << 24;
6898 b = *codep++ & 0xff;
6899 b |= (*codep++ & 0xff) << 8;
6900 b |= (*codep++ & 0xff) << 16;
6901 b |= (*codep++ & 0xff) << 24;
6902 x = a + ((bfd_vma) b << 32);
6903 #else
6904 abort ();
6905 x = 0;
6906 #endif
6907 return x;
6908 }
6909
6910 static bfd_signed_vma
6911 get32 (void)
6912 {
6913 bfd_signed_vma x = 0;
6914
6915 FETCH_DATA (the_info, codep + 4);
6916 x = *codep++ & (bfd_signed_vma) 0xff;
6917 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
6918 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
6919 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
6920 return x;
6921 }
6922
6923 static bfd_signed_vma
6924 get32s (void)
6925 {
6926 bfd_signed_vma x = 0;
6927
6928 FETCH_DATA (the_info, codep + 4);
6929 x = *codep++ & (bfd_signed_vma) 0xff;
6930 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
6931 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
6932 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
6933
6934 x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
6935
6936 return x;
6937 }
6938
6939 static int
6940 get16 (void)
6941 {
6942 int x = 0;
6943
6944 FETCH_DATA (the_info, codep + 2);
6945 x = *codep++ & 0xff;
6946 x |= (*codep++ & 0xff) << 8;
6947 return x;
6948 }
6949
6950 static void
6951 set_op (bfd_vma op, int riprel)
6952 {
6953 op_index[op_ad] = op_ad;
6954 if (address_mode == mode_64bit)
6955 {
6956 op_address[op_ad] = op;
6957 op_riprel[op_ad] = riprel;
6958 }
6959 else
6960 {
6961 /* Mask to get a 32-bit address. */
6962 op_address[op_ad] = op & 0xffffffff;
6963 op_riprel[op_ad] = riprel & 0xffffffff;
6964 }
6965 }
6966
6967 static void
6968 OP_REG (int code, int sizeflag)
6969 {
6970 const char *s;
6971 int add;
6972 USED_REX (REX_B);
6973 if (rex & REX_B)
6974 add = 8;
6975 else
6976 add = 0;
6977
6978 switch (code)
6979 {
6980 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
6981 case sp_reg: case bp_reg: case si_reg: case di_reg:
6982 s = names16[code - ax_reg + add];
6983 break;
6984 case es_reg: case ss_reg: case cs_reg:
6985 case ds_reg: case fs_reg: case gs_reg:
6986 s = names_seg[code - es_reg + add];
6987 break;
6988 case al_reg: case ah_reg: case cl_reg: case ch_reg:
6989 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
6990 USED_REX (0);
6991 if (rex)
6992 s = names8rex[code - al_reg + add];
6993 else
6994 s = names8[code - al_reg];
6995 break;
6996 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
6997 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
6998 if (address_mode == mode_64bit && (sizeflag & DFLAG))
6999 {
7000 s = names64[code - rAX_reg + add];
7001 break;
7002 }
7003 code += eAX_reg - rAX_reg;
7004 /* Fall through. */
7005 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
7006 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
7007 USED_REX (REX_W);
7008 if (rex & REX_W)
7009 s = names64[code - eAX_reg + add];
7010 else if (sizeflag & DFLAG)
7011 s = names32[code - eAX_reg + add];
7012 else
7013 s = names16[code - eAX_reg + add];
7014 used_prefixes |= (prefixes & PREFIX_DATA);
7015 break;
7016 default:
7017 s = INTERNAL_DISASSEMBLER_ERROR;
7018 break;
7019 }
7020 oappend (s);
7021 }
7022
7023 static void
7024 OP_IMREG (int code, int sizeflag)
7025 {
7026 const char *s;
7027
7028 switch (code)
7029 {
7030 case indir_dx_reg:
7031 if (intel_syntax)
7032 s = "dx";
7033 else
7034 s = "(%dx)";
7035 break;
7036 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
7037 case sp_reg: case bp_reg: case si_reg: case di_reg:
7038 s = names16[code - ax_reg];
7039 break;
7040 case es_reg: case ss_reg: case cs_reg:
7041 case ds_reg: case fs_reg: case gs_reg:
7042 s = names_seg[code - es_reg];
7043 break;
7044 case al_reg: case ah_reg: case cl_reg: case ch_reg:
7045 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
7046 USED_REX (0);
7047 if (rex)
7048 s = names8rex[code - al_reg];
7049 else
7050 s = names8[code - al_reg];
7051 break;
7052 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
7053 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
7054 USED_REX (REX_W);
7055 if (rex & REX_W)
7056 s = names64[code - eAX_reg];
7057 else if (sizeflag & DFLAG)
7058 s = names32[code - eAX_reg];
7059 else
7060 s = names16[code - eAX_reg];
7061 used_prefixes |= (prefixes & PREFIX_DATA);
7062 break;
7063 case z_mode_ax_reg:
7064 if ((rex & REX_W) || (sizeflag & DFLAG))
7065 s = *names32;
7066 else
7067 s = *names16;
7068 if (!(rex & REX_W))
7069 used_prefixes |= (prefixes & PREFIX_DATA);
7070 break;
7071 default:
7072 s = INTERNAL_DISASSEMBLER_ERROR;
7073 break;
7074 }
7075 oappend (s);
7076 }
7077
7078 static void
7079 OP_I (int bytemode, int sizeflag)
7080 {
7081 bfd_signed_vma op;
7082 bfd_signed_vma mask = -1;
7083
7084 switch (bytemode)
7085 {
7086 case b_mode:
7087 FETCH_DATA (the_info, codep + 1);
7088 op = *codep++;
7089 mask = 0xff;
7090 break;
7091 case q_mode:
7092 if (address_mode == mode_64bit)
7093 {
7094 op = get32s ();
7095 break;
7096 }
7097 /* Fall through. */
7098 case v_mode:
7099 USED_REX (REX_W);
7100 if (rex & REX_W)
7101 op = get32s ();
7102 else if (sizeflag & DFLAG)
7103 {
7104 op = get32 ();
7105 mask = 0xffffffff;
7106 }
7107 else
7108 {
7109 op = get16 ();
7110 mask = 0xfffff;
7111 }
7112 used_prefixes |= (prefixes & PREFIX_DATA);
7113 break;
7114 case w_mode:
7115 mask = 0xfffff;
7116 op = get16 ();
7117 break;
7118 case const_1_mode:
7119 if (intel_syntax)
7120 oappend ("1");
7121 return;
7122 default:
7123 oappend (INTERNAL_DISASSEMBLER_ERROR);
7124 return;
7125 }
7126
7127 op &= mask;
7128 scratchbuf[0] = '$';
7129 print_operand_value (scratchbuf + 1, 1, op);
7130 oappend (scratchbuf + intel_syntax);
7131 scratchbuf[0] = '\0';
7132 }
7133
7134 static void
7135 OP_I64 (int bytemode, int sizeflag)
7136 {
7137 bfd_signed_vma op;
7138 bfd_signed_vma mask = -1;
7139
7140 if (address_mode != mode_64bit)
7141 {
7142 OP_I (bytemode, sizeflag);
7143 return;
7144 }
7145
7146 switch (bytemode)
7147 {
7148 case b_mode:
7149 FETCH_DATA (the_info, codep + 1);
7150 op = *codep++;
7151 mask = 0xff;
7152 break;
7153 case v_mode:
7154 USED_REX (REX_W);
7155 if (rex & REX_W)
7156 op = get64 ();
7157 else if (sizeflag & DFLAG)
7158 {
7159 op = get32 ();
7160 mask = 0xffffffff;
7161 }
7162 else
7163 {
7164 op = get16 ();
7165 mask = 0xfffff;
7166 }
7167 used_prefixes |= (prefixes & PREFIX_DATA);
7168 break;
7169 case w_mode:
7170 mask = 0xfffff;
7171 op = get16 ();
7172 break;
7173 default:
7174 oappend (INTERNAL_DISASSEMBLER_ERROR);
7175 return;
7176 }
7177
7178 op &= mask;
7179 scratchbuf[0] = '$';
7180 print_operand_value (scratchbuf + 1, 1, op);
7181 oappend (scratchbuf + intel_syntax);
7182 scratchbuf[0] = '\0';
7183 }
7184
7185 static void
7186 OP_sI (int bytemode, int sizeflag)
7187 {
7188 bfd_signed_vma op;
7189 bfd_signed_vma mask = -1;
7190
7191 switch (bytemode)
7192 {
7193 case b_mode:
7194 FETCH_DATA (the_info, codep + 1);
7195 op = *codep++;
7196 if ((op & 0x80) != 0)
7197 op -= 0x100;
7198 mask = 0xffffffff;
7199 break;
7200 case v_mode:
7201 USED_REX (REX_W);
7202 if (rex & REX_W)
7203 op = get32s ();
7204 else if (sizeflag & DFLAG)
7205 {
7206 op = get32s ();
7207 mask = 0xffffffff;
7208 }
7209 else
7210 {
7211 mask = 0xffffffff;
7212 op = get16 ();
7213 if ((op & 0x8000) != 0)
7214 op -= 0x10000;
7215 }
7216 used_prefixes |= (prefixes & PREFIX_DATA);
7217 break;
7218 case w_mode:
7219 op = get16 ();
7220 mask = 0xffffffff;
7221 if ((op & 0x8000) != 0)
7222 op -= 0x10000;
7223 break;
7224 default:
7225 oappend (INTERNAL_DISASSEMBLER_ERROR);
7226 return;
7227 }
7228
7229 scratchbuf[0] = '$';
7230 print_operand_value (scratchbuf + 1, 1, op);
7231 oappend (scratchbuf + intel_syntax);
7232 }
7233
7234 static void
7235 OP_J (int bytemode, int sizeflag)
7236 {
7237 bfd_vma disp;
7238 bfd_vma mask = -1;
7239 bfd_vma segment = 0;
7240
7241 switch (bytemode)
7242 {
7243 case b_mode:
7244 FETCH_DATA (the_info, codep + 1);
7245 disp = *codep++;
7246 if ((disp & 0x80) != 0)
7247 disp -= 0x100;
7248 break;
7249 case v_mode:
7250 if ((sizeflag & DFLAG) || (rex & REX_W))
7251 disp = get32s ();
7252 else
7253 {
7254 disp = get16 ();
7255 if ((disp & 0x8000) != 0)
7256 disp -= 0x10000;
7257 /* In 16bit mode, address is wrapped around at 64k within
7258 the same segment. Otherwise, a data16 prefix on a jump
7259 instruction means that the pc is masked to 16 bits after
7260 the displacement is added! */
7261 mask = 0xffff;
7262 if ((prefixes & PREFIX_DATA) == 0)
7263 segment = ((start_pc + codep - start_codep)
7264 & ~((bfd_vma) 0xffff));
7265 }
7266 used_prefixes |= (prefixes & PREFIX_DATA);
7267 break;
7268 default:
7269 oappend (INTERNAL_DISASSEMBLER_ERROR);
7270 return;
7271 }
7272 disp = ((start_pc + codep - start_codep + disp) & mask) | segment;
7273 set_op (disp, 0);
7274 print_operand_value (scratchbuf, 1, disp);
7275 oappend (scratchbuf);
7276 }
7277
7278 static void
7279 OP_SEG (int bytemode, int sizeflag)
7280 {
7281 if (bytemode == w_mode)
7282 oappend (names_seg[modrm.reg]);
7283 else
7284 OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
7285 }
7286
7287 static void
7288 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
7289 {
7290 int seg, offset;
7291
7292 if (sizeflag & DFLAG)
7293 {
7294 offset = get32 ();
7295 seg = get16 ();
7296 }
7297 else
7298 {
7299 offset = get16 ();
7300 seg = get16 ();
7301 }
7302 used_prefixes |= (prefixes & PREFIX_DATA);
7303 if (intel_syntax)
7304 sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
7305 else
7306 sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
7307 oappend (scratchbuf);
7308 }
7309
7310 static void
7311 OP_OFF (int bytemode, int sizeflag)
7312 {
7313 bfd_vma off;
7314
7315 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
7316 intel_operand_size (bytemode, sizeflag);
7317 append_seg ();
7318
7319 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
7320 off = get32 ();
7321 else
7322 off = get16 ();
7323
7324 if (intel_syntax)
7325 {
7326 if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
7327 | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
7328 {
7329 oappend (names_seg[ds_reg - es_reg]);
7330 oappend (":");
7331 }
7332 }
7333 print_operand_value (scratchbuf, 1, off);
7334 oappend (scratchbuf);
7335 }
7336
7337 static void
7338 OP_OFF64 (int bytemode, int sizeflag)
7339 {
7340 bfd_vma off;
7341
7342 if (address_mode != mode_64bit
7343 || (prefixes & PREFIX_ADDR))
7344 {
7345 OP_OFF (bytemode, sizeflag);
7346 return;
7347 }
7348
7349 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
7350 intel_operand_size (bytemode, sizeflag);
7351 append_seg ();
7352
7353 off = get64 ();
7354
7355 if (intel_syntax)
7356 {
7357 if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
7358 | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
7359 {
7360 oappend (names_seg[ds_reg - es_reg]);
7361 oappend (":");
7362 }
7363 }
7364 print_operand_value (scratchbuf, 1, off);
7365 oappend (scratchbuf);
7366 }
7367
7368 static void
7369 ptr_reg (int code, int sizeflag)
7370 {
7371 const char *s;
7372
7373 *obufp++ = open_char;
7374 used_prefixes |= (prefixes & PREFIX_ADDR);
7375 if (address_mode == mode_64bit)
7376 {
7377 if (!(sizeflag & AFLAG))
7378 s = names32[code - eAX_reg];
7379 else
7380 s = names64[code - eAX_reg];
7381 }
7382 else if (sizeflag & AFLAG)
7383 s = names32[code - eAX_reg];
7384 else
7385 s = names16[code - eAX_reg];
7386 oappend (s);
7387 *obufp++ = close_char;
7388 *obufp = 0;
7389 }
7390
7391 static void
7392 OP_ESreg (int code, int sizeflag)
7393 {
7394 if (intel_syntax)
7395 {
7396 switch (codep[-1])
7397 {
7398 case 0x6d: /* insw/insl */
7399 intel_operand_size (z_mode, sizeflag);
7400 break;
7401 case 0xa5: /* movsw/movsl/movsq */
7402 case 0xa7: /* cmpsw/cmpsl/cmpsq */
7403 case 0xab: /* stosw/stosl */
7404 case 0xaf: /* scasw/scasl */
7405 intel_operand_size (v_mode, sizeflag);
7406 break;
7407 default:
7408 intel_operand_size (b_mode, sizeflag);
7409 }
7410 }
7411 oappend ("%es:" + intel_syntax);
7412 ptr_reg (code, sizeflag);
7413 }
7414
7415 static void
7416 OP_DSreg (int code, int sizeflag)
7417 {
7418 if (intel_syntax)
7419 {
7420 switch (codep[-1])
7421 {
7422 case 0x6f: /* outsw/outsl */
7423 intel_operand_size (z_mode, sizeflag);
7424 break;
7425 case 0xa5: /* movsw/movsl/movsq */
7426 case 0xa7: /* cmpsw/cmpsl/cmpsq */
7427 case 0xad: /* lodsw/lodsl/lodsq */
7428 intel_operand_size (v_mode, sizeflag);
7429 break;
7430 default:
7431 intel_operand_size (b_mode, sizeflag);
7432 }
7433 }
7434 if ((prefixes
7435 & (PREFIX_CS
7436 | PREFIX_DS
7437 | PREFIX_SS
7438 | PREFIX_ES
7439 | PREFIX_FS
7440 | PREFIX_GS)) == 0)
7441 prefixes |= PREFIX_DS;
7442 append_seg ();
7443 ptr_reg (code, sizeflag);
7444 }
7445
7446 static void
7447 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
7448 {
7449 int add;
7450 if (rex & REX_R)
7451 {
7452 USED_REX (REX_R);
7453 add = 8;
7454 }
7455 else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
7456 {
7457 lock_prefix = NULL;
7458 used_prefixes |= PREFIX_LOCK;
7459 add = 8;
7460 }
7461 else
7462 add = 0;
7463 sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
7464 oappend (scratchbuf + intel_syntax);
7465 }
7466
7467 static void
7468 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
7469 {
7470 int add;
7471 USED_REX (REX_R);
7472 if (rex & REX_R)
7473 add = 8;
7474 else
7475 add = 0;
7476 if (intel_syntax)
7477 sprintf (scratchbuf, "db%d", modrm.reg + add);
7478 else
7479 sprintf (scratchbuf, "%%db%d", modrm.reg + add);
7480 oappend (scratchbuf);
7481 }
7482
7483 static void
7484 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
7485 {
7486 sprintf (scratchbuf, "%%tr%d", modrm.reg);
7487 oappend (scratchbuf + intel_syntax);
7488 }
7489
7490 static void
7491 OP_R (int bytemode, int sizeflag)
7492 {
7493 if (modrm.mod == 3)
7494 OP_E (bytemode, sizeflag);
7495 else
7496 BadOp ();
7497 }
7498
7499 static void
7500 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
7501 {
7502 used_prefixes |= (prefixes & PREFIX_DATA);
7503 if (prefixes & PREFIX_DATA)
7504 {
7505 int add;
7506 USED_REX (REX_R);
7507 if (rex & REX_R)
7508 add = 8;
7509 else
7510 add = 0;
7511 sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
7512 }
7513 else
7514 sprintf (scratchbuf, "%%mm%d", modrm.reg);
7515 oappend (scratchbuf + intel_syntax);
7516 }
7517
7518 static void
7519 OP_XMM (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
7520 {
7521 int add;
7522 USED_REX (REX_R);
7523 if (rex & REX_R)
7524 add = 8;
7525 else
7526 add = 0;
7527 sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
7528 oappend (scratchbuf + intel_syntax);
7529 }
7530
7531 static void
7532 OP_EM (int bytemode, int sizeflag)
7533 {
7534 if (modrm.mod != 3)
7535 {
7536 if (intel_syntax && bytemode == v_mode)
7537 {
7538 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
7539 used_prefixes |= (prefixes & PREFIX_DATA);
7540 }
7541 OP_E (bytemode, sizeflag);
7542 return;
7543 }
7544
7545 /* Skip mod/rm byte. */
7546 MODRM_CHECK;
7547 codep++;
7548 used_prefixes |= (prefixes & PREFIX_DATA);
7549 if (prefixes & PREFIX_DATA)
7550 {
7551 int add;
7552
7553 USED_REX (REX_B);
7554 if (rex & REX_B)
7555 add = 8;
7556 else
7557 add = 0;
7558 sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
7559 }
7560 else
7561 sprintf (scratchbuf, "%%mm%d", modrm.rm);
7562 oappend (scratchbuf + intel_syntax);
7563 }
7564
7565 /* cvt* are the only instructions in sse2 which have
7566 both SSE and MMX operands and also have 0x66 prefix
7567 in their opcode. 0x66 was originally used to differentiate
7568 between SSE and MMX instruction(operands). So we have to handle the
7569 cvt* separately using OP_EMC and OP_MXC */
7570 static void
7571 OP_EMC (int bytemode, int sizeflag)
7572 {
7573 if (modrm.mod != 3)
7574 {
7575 if (intel_syntax && bytemode == v_mode)
7576 {
7577 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
7578 used_prefixes |= (prefixes & PREFIX_DATA);
7579 }
7580 OP_E (bytemode, sizeflag);
7581 return;
7582 }
7583
7584 /* Skip mod/rm byte. */
7585 MODRM_CHECK;
7586 codep++;
7587 used_prefixes |= (prefixes & PREFIX_DATA);
7588 sprintf (scratchbuf, "%%mm%d", modrm.rm);
7589 oappend (scratchbuf + intel_syntax);
7590 }
7591
7592 static void
7593 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
7594 {
7595 used_prefixes |= (prefixes & PREFIX_DATA);
7596 sprintf (scratchbuf, "%%mm%d", modrm.reg);
7597 oappend (scratchbuf + intel_syntax);
7598 }
7599
7600 static void
7601 OP_EX (int bytemode, int sizeflag)
7602 {
7603 int add;
7604 if (modrm.mod != 3)
7605 {
7606 OP_E (bytemode, sizeflag);
7607 return;
7608 }
7609 USED_REX (REX_B);
7610 if (rex & REX_B)
7611 add = 8;
7612 else
7613 add = 0;
7614
7615 /* Skip mod/rm byte. */
7616 MODRM_CHECK;
7617 codep++;
7618 sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
7619 oappend (scratchbuf + intel_syntax);
7620 }
7621
7622 static void
7623 OP_MS (int bytemode, int sizeflag)
7624 {
7625 if (modrm.mod == 3)
7626 OP_EM (bytemode, sizeflag);
7627 else
7628 BadOp ();
7629 }
7630
7631 static void
7632 OP_XS (int bytemode, int sizeflag)
7633 {
7634 if (modrm.mod == 3)
7635 OP_EX (bytemode, sizeflag);
7636 else
7637 BadOp ();
7638 }
7639
7640 static void
7641 OP_M (int bytemode, int sizeflag)
7642 {
7643 if (modrm.mod == 3)
7644 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
7645 BadOp ();
7646 else
7647 OP_E (bytemode, sizeflag);
7648 }
7649
7650 static void
7651 OP_0f07 (int bytemode, int sizeflag)
7652 {
7653 if (modrm.mod != 3 || modrm.rm != 0)
7654 BadOp ();
7655 else
7656 OP_E (bytemode, sizeflag);
7657 }
7658
7659 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
7660 32bit mode and "xchg %rax,%rax" in 64bit mode. */
7661
7662 static void
7663 NOP_Fixup1 (int bytemode, int sizeflag)
7664 {
7665 if ((prefixes & PREFIX_DATA) != 0
7666 || (rex != 0
7667 && rex != 0x48
7668 && address_mode == mode_64bit))
7669 OP_REG (bytemode, sizeflag);
7670 else
7671 strcpy (obuf, "nop");
7672 }
7673
7674 static void
7675 NOP_Fixup2 (int bytemode, int sizeflag)
7676 {
7677 if ((prefixes & PREFIX_DATA) != 0
7678 || (rex != 0
7679 && rex != 0x48
7680 && address_mode == mode_64bit))
7681 OP_IMREG (bytemode, sizeflag);
7682 }
7683
7684 static const char *const Suffix3DNow[] = {
7685 /* 00 */ NULL, NULL, NULL, NULL,
7686 /* 04 */ NULL, NULL, NULL, NULL,
7687 /* 08 */ NULL, NULL, NULL, NULL,
7688 /* 0C */ "pi2fw", "pi2fd", NULL, NULL,
7689 /* 10 */ NULL, NULL, NULL, NULL,
7690 /* 14 */ NULL, NULL, NULL, NULL,
7691 /* 18 */ NULL, NULL, NULL, NULL,
7692 /* 1C */ "pf2iw", "pf2id", NULL, NULL,
7693 /* 20 */ NULL, NULL, NULL, NULL,
7694 /* 24 */ NULL, NULL, NULL, NULL,
7695 /* 28 */ NULL, NULL, NULL, NULL,
7696 /* 2C */ NULL, NULL, NULL, NULL,
7697 /* 30 */ NULL, NULL, NULL, NULL,
7698 /* 34 */ NULL, NULL, NULL, NULL,
7699 /* 38 */ NULL, NULL, NULL, NULL,
7700 /* 3C */ NULL, NULL, NULL, NULL,
7701 /* 40 */ NULL, NULL, NULL, NULL,
7702 /* 44 */ NULL, NULL, NULL, NULL,
7703 /* 48 */ NULL, NULL, NULL, NULL,
7704 /* 4C */ NULL, NULL, NULL, NULL,
7705 /* 50 */ NULL, NULL, NULL, NULL,
7706 /* 54 */ NULL, NULL, NULL, NULL,
7707 /* 58 */ NULL, NULL, NULL, NULL,
7708 /* 5C */ NULL, NULL, NULL, NULL,
7709 /* 60 */ NULL, NULL, NULL, NULL,
7710 /* 64 */ NULL, NULL, NULL, NULL,
7711 /* 68 */ NULL, NULL, NULL, NULL,
7712 /* 6C */ NULL, NULL, NULL, NULL,
7713 /* 70 */ NULL, NULL, NULL, NULL,
7714 /* 74 */ NULL, NULL, NULL, NULL,
7715 /* 78 */ NULL, NULL, NULL, NULL,
7716 /* 7C */ NULL, NULL, NULL, NULL,
7717 /* 80 */ NULL, NULL, NULL, NULL,
7718 /* 84 */ NULL, NULL, NULL, NULL,
7719 /* 88 */ NULL, NULL, "pfnacc", NULL,
7720 /* 8C */ NULL, NULL, "pfpnacc", NULL,
7721 /* 90 */ "pfcmpge", NULL, NULL, NULL,
7722 /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt",
7723 /* 98 */ NULL, NULL, "pfsub", NULL,
7724 /* 9C */ NULL, NULL, "pfadd", NULL,
7725 /* A0 */ "pfcmpgt", NULL, NULL, NULL,
7726 /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1",
7727 /* A8 */ NULL, NULL, "pfsubr", NULL,
7728 /* AC */ NULL, NULL, "pfacc", NULL,
7729 /* B0 */ "pfcmpeq", NULL, NULL, NULL,
7730 /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw",
7731 /* B8 */ NULL, NULL, NULL, "pswapd",
7732 /* BC */ NULL, NULL, NULL, "pavgusb",
7733 /* C0 */ NULL, NULL, NULL, NULL,
7734 /* C4 */ NULL, NULL, NULL, NULL,
7735 /* C8 */ NULL, NULL, NULL, NULL,
7736 /* CC */ NULL, NULL, NULL, NULL,
7737 /* D0 */ NULL, NULL, NULL, NULL,
7738 /* D4 */ NULL, NULL, NULL, NULL,
7739 /* D8 */ NULL, NULL, NULL, NULL,
7740 /* DC */ NULL, NULL, NULL, NULL,
7741 /* E0 */ NULL, NULL, NULL, NULL,
7742 /* E4 */ NULL, NULL, NULL, NULL,
7743 /* E8 */ NULL, NULL, NULL, NULL,
7744 /* EC */ NULL, NULL, NULL, NULL,
7745 /* F0 */ NULL, NULL, NULL, NULL,
7746 /* F4 */ NULL, NULL, NULL, NULL,
7747 /* F8 */ NULL, NULL, NULL, NULL,
7748 /* FC */ NULL, NULL, NULL, NULL,
7749 };
7750
7751 static void
7752 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
7753 {
7754 const char *mnemonic;
7755
7756 FETCH_DATA (the_info, codep + 1);
7757 /* AMD 3DNow! instructions are specified by an opcode suffix in the
7758 place where an 8-bit immediate would normally go. ie. the last
7759 byte of the instruction. */
7760 obufp = obuf + strlen (obuf);
7761 mnemonic = Suffix3DNow[*codep++ & 0xff];
7762 if (mnemonic)
7763 oappend (mnemonic);
7764 else
7765 {
7766 /* Since a variable sized modrm/sib chunk is between the start
7767 of the opcode (0x0f0f) and the opcode suffix, we need to do
7768 all the modrm processing first, and don't know until now that
7769 we have a bad opcode. This necessitates some cleaning up. */
7770 op_out[0][0] = '\0';
7771 op_out[1][0] = '\0';
7772 BadOp ();
7773 }
7774 }
7775
7776 static const char *simd_cmp_op[] = {
7777 "eq",
7778 "lt",
7779 "le",
7780 "unord",
7781 "neq",
7782 "nlt",
7783 "nle",
7784 "ord"
7785 };
7786
7787 static void
7788 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
7789 {
7790 unsigned int cmp_type;
7791
7792 FETCH_DATA (the_info, codep + 1);
7793 cmp_type = *codep++ & 0xff;
7794 if (cmp_type < 8)
7795 {
7796 char suffix [3];
7797 char *p = obuf + strlen (obuf) - 2;
7798 suffix[0] = p[0];
7799 suffix[1] = p[1];
7800 suffix[2] = '\0';
7801 sprintf (p, "%s%s", simd_cmp_op[cmp_type], suffix);
7802 }
7803 else
7804 {
7805 /* We have a reserved extension byte. Output it directly. */
7806 scratchbuf[0] = '$';
7807 print_operand_value (scratchbuf + 1, 1, cmp_type);
7808 oappend (scratchbuf + intel_syntax);
7809 scratchbuf[0] = '\0';
7810 }
7811 }
7812
7813 static void
7814 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
7815 int sizeflag ATTRIBUTE_UNUSED)
7816 {
7817 /* mwait %eax,%ecx */
7818 if (!intel_syntax)
7819 {
7820 const char **names = (address_mode == mode_64bit
7821 ? names64 : names32);
7822 strcpy (op_out[0], names[0]);
7823 strcpy (op_out[1], names[1]);
7824 two_source_ops = 1;
7825 }
7826 /* Skip mod/rm byte. */
7827 MODRM_CHECK;
7828 codep++;
7829 }
7830
7831 static void
7832 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
7833 int sizeflag ATTRIBUTE_UNUSED)
7834 {
7835 /* monitor %eax,%ecx,%edx" */
7836 if (!intel_syntax)
7837 {
7838 const char **op1_names;
7839 const char **names = (address_mode == mode_64bit
7840 ? names64 : names32);
7841
7842 if (!(prefixes & PREFIX_ADDR))
7843 op1_names = (address_mode == mode_16bit
7844 ? names16 : names);
7845 else
7846 {
7847 /* Remove "addr16/addr32". */
7848 addr_prefix = NULL;
7849 op1_names = (address_mode != mode_32bit
7850 ? names32 : names16);
7851 used_prefixes |= PREFIX_ADDR;
7852 }
7853 strcpy (op_out[0], op1_names[0]);
7854 strcpy (op_out[1], names[1]);
7855 strcpy (op_out[2], names[2]);
7856 two_source_ops = 1;
7857 }
7858 /* Skip mod/rm byte. */
7859 MODRM_CHECK;
7860 codep++;
7861 }
7862
7863 static void
7864 BadOp (void)
7865 {
7866 /* Throw away prefixes and 1st. opcode byte. */
7867 codep = insn_codep + 1;
7868 oappend ("(bad)");
7869 }
7870
7871 static void
7872 REP_Fixup (int bytemode, int sizeflag)
7873 {
7874 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
7875 lods and stos. */
7876 if (prefixes & PREFIX_REPZ)
7877 repz_prefix = "rep ";
7878
7879 switch (bytemode)
7880 {
7881 case al_reg:
7882 case eAX_reg:
7883 case indir_dx_reg:
7884 OP_IMREG (bytemode, sizeflag);
7885 break;
7886 case eDI_reg:
7887 OP_ESreg (bytemode, sizeflag);
7888 break;
7889 case eSI_reg:
7890 OP_DSreg (bytemode, sizeflag);
7891 break;
7892 default:
7893 abort ();
7894 break;
7895 }
7896 }
7897
7898 static void
7899 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
7900 {
7901 USED_REX (REX_W);
7902 if (rex & REX_W)
7903 {
7904 /* Change cmpxchg8b to cmpxchg16b. */
7905 char *p = obuf + strlen (obuf) - 2;
7906 strcpy (p, "16b");
7907 bytemode = o_mode;
7908 }
7909 OP_M (bytemode, sizeflag);
7910 }
7911
7912 static void
7913 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
7914 {
7915 sprintf (scratchbuf, "%%xmm%d", reg);
7916 oappend (scratchbuf + intel_syntax);
7917 }
7918
7919 static void
7920 CRC32_Fixup (int bytemode, int sizeflag)
7921 {
7922 /* Add proper suffix to "crc32". */
7923 char *p = obuf + strlen (obuf);
7924
7925 switch (bytemode)
7926 {
7927 case b_mode:
7928 if (intel_syntax)
7929 break;
7930
7931 *p++ = 'b';
7932 break;
7933 case v_mode:
7934 if (intel_syntax)
7935 break;
7936
7937 USED_REX (REX_W);
7938 if (rex & REX_W)
7939 *p++ = 'q';
7940 else if (sizeflag & DFLAG)
7941 *p++ = 'l';
7942 else
7943 *p++ = 'w';
7944 used_prefixes |= (prefixes & PREFIX_DATA);
7945 break;
7946 default:
7947 oappend (INTERNAL_DISASSEMBLER_ERROR);
7948 break;
7949 }
7950 *p = '\0';
7951
7952 if (modrm.mod == 3)
7953 {
7954 int add;
7955
7956 /* Skip mod/rm byte. */
7957 MODRM_CHECK;
7958 codep++;
7959
7960 USED_REX (REX_B);
7961 add = (rex & REX_B) ? 8 : 0;
7962 if (bytemode == b_mode)
7963 {
7964 USED_REX (0);
7965 if (rex)
7966 oappend (names8rex[modrm.rm + add]);
7967 else
7968 oappend (names8[modrm.rm + add]);
7969 }
7970 else
7971 {
7972 USED_REX (REX_W);
7973 if (rex & REX_W)
7974 oappend (names64[modrm.rm + add]);
7975 else if ((prefixes & PREFIX_DATA))
7976 oappend (names16[modrm.rm + add]);
7977 else
7978 oappend (names32[modrm.rm + add]);
7979 }
7980 }
7981 else
7982 OP_E (bytemode, sizeflag);
7983 }
7984
7985 /* Print a DREX argument as either a register or memory operation. */
7986 static void
7987 print_drex_arg (unsigned int reg, int bytemode, int sizeflag)
7988 {
7989 if (reg == DREX_REG_UNKNOWN)
7990 BadOp ();
7991
7992 else if (reg != DREX_REG_MEMORY)
7993 {
7994 sprintf (scratchbuf, "%%xmm%d", reg);
7995 oappend (scratchbuf + intel_syntax);
7996 }
7997
7998 else
7999 OP_E_extended (bytemode, sizeflag, 1);
8000 }
8001
8002 /* SSE5 instructions that have 4 arguments are encoded as:
8003 0f 24 <sub-opcode> <modrm> <optional-sib> <drex> <offset>.
8004
8005 The <sub-opcode> byte has 1 bit (0x4) that is combined with 1 bit in
8006 the DREX field (0x8) to determine how the arguments are laid out.
8007 The destination register must be the same register as one of the
8008 inputs, and it is encoded in the DREX byte. No REX prefix is used
8009 for these instructions, since the DREX field contains the 3 extension
8010 bits provided by the REX prefix.
8011
8012 The bytemode argument adds 2 extra bits for passing extra information:
8013 DREX_OC1 -- Set the OC1 bit to indicate dest == 1st arg
8014 DREX_NO_OC0 -- OC0 in DREX is invalid
8015 (but pretend it is set). */
8016
8017 static void
8018 OP_DREX4 (int flag_bytemode, int sizeflag)
8019 {
8020 unsigned int drex_byte;
8021 unsigned int regs[4];
8022 unsigned int modrm_regmem;
8023 unsigned int modrm_reg;
8024 unsigned int drex_reg;
8025 int bytemode;
8026 int rex_save = rex;
8027 int rex_used_save = rex_used;
8028 int has_sib = 0;
8029 int oc1 = (flag_bytemode & DREX_OC1) ? 2 : 0;
8030 int oc0;
8031 int i;
8032
8033 bytemode = flag_bytemode & ~ DREX_MASK;
8034
8035 for (i = 0; i < 4; i++)
8036 regs[i] = DREX_REG_UNKNOWN;
8037
8038 /* Determine if we have a SIB byte in addition to MODRM before the
8039 DREX byte. */
8040 if (((sizeflag & AFLAG) || address_mode == mode_64bit)
8041 && (modrm.mod != 3)
8042 && (modrm.rm == 4))
8043 has_sib = 1;
8044
8045 /* Get the DREX byte. */
8046 FETCH_DATA (the_info, codep + 2 + has_sib);
8047 drex_byte = codep[has_sib+1];
8048 drex_reg = DREX_XMM (drex_byte);
8049 modrm_reg = modrm.reg + ((drex_byte & REX_R) ? 8 : 0);
8050
8051 /* Is OC0 legal? If not, hardwire oc0 == 1. */
8052 if (flag_bytemode & DREX_NO_OC0)
8053 {
8054 oc0 = 1;
8055 if (DREX_OC0 (drex_byte))
8056 BadOp ();
8057 }
8058 else
8059 oc0 = DREX_OC0 (drex_byte);
8060
8061 if (modrm.mod == 3)
8062 {
8063 /* regmem == register */
8064 modrm_regmem = modrm.rm + ((drex_byte & REX_B) ? 8 : 0);
8065 rex = rex_used = 0;
8066 /* skip modrm/drex since we don't call OP_E_extended */
8067 codep += 2;
8068 }
8069 else
8070 {
8071 /* regmem == memory, fill in appropriate REX bits */
8072 modrm_regmem = DREX_REG_MEMORY;
8073 rex = drex_byte & (REX_B | REX_X | REX_R);
8074 if (rex)
8075 rex |= REX_OPCODE;
8076 rex_used = rex;
8077 }
8078
8079 /* Based on the OC1/OC0 bits, lay out the arguments in the correct
8080 order. */
8081 switch (oc0 + oc1)
8082 {
8083 default:
8084 BadOp ();
8085 return;
8086
8087 case 0:
8088 regs[0] = modrm_regmem;
8089 regs[1] = modrm_reg;
8090 regs[2] = drex_reg;
8091 regs[3] = drex_reg;
8092 break;
8093
8094 case 1:
8095 regs[0] = modrm_reg;
8096 regs[1] = modrm_regmem;
8097 regs[2] = drex_reg;
8098 regs[3] = drex_reg;
8099 break;
8100
8101 case 2:
8102 regs[0] = drex_reg;
8103 regs[1] = modrm_regmem;
8104 regs[2] = modrm_reg;
8105 regs[3] = drex_reg;
8106 break;
8107
8108 case 3:
8109 regs[0] = drex_reg;
8110 regs[1] = modrm_reg;
8111 regs[2] = modrm_regmem;
8112 regs[3] = drex_reg;
8113 break;
8114 }
8115
8116 /* Print out the arguments. */
8117 for (i = 0; i < 4; i++)
8118 {
8119 int j = (intel_syntax) ? 3 - i : i;
8120 if (i > 0)
8121 {
8122 *obufp++ = ',';
8123 *obufp = '\0';
8124 }
8125
8126 print_drex_arg (regs[j], bytemode, sizeflag);
8127 }
8128
8129 rex = rex_save;
8130 rex_used = rex_used_save;
8131 }
8132
8133 /* SSE5 instructions that have 3 arguments, and are encoded as:
8134 0f 24 <sub-opcode> <modrm> <optional-sib> <drex> <offset> (or)
8135 0f 25 <sub-opcode> <modrm> <optional-sib> <drex> <offset> <cmp-byte>
8136
8137 The DREX field has 1 bit (0x8) to determine how the arguments are
8138 laid out. The destination register is encoded in the DREX byte.
8139 No REX prefix is used for these instructions, since the DREX field
8140 contains the 3 extension bits provided by the REX prefix. */
8141
8142 static void
8143 OP_DREX3 (int flag_bytemode, int sizeflag)
8144 {
8145 unsigned int drex_byte;
8146 unsigned int regs[3];
8147 unsigned int modrm_regmem;
8148 unsigned int modrm_reg;
8149 unsigned int drex_reg;
8150 int bytemode;
8151 int rex_save = rex;
8152 int rex_used_save = rex_used;
8153 int has_sib = 0;
8154 int oc0;
8155 int i;
8156
8157 bytemode = flag_bytemode & ~ DREX_MASK;
8158
8159 for (i = 0; i < 3; i++)
8160 regs[i] = DREX_REG_UNKNOWN;
8161
8162 /* Determine if we have a SIB byte in addition to MODRM before the
8163 DREX byte. */
8164 if (((sizeflag & AFLAG) || address_mode == mode_64bit)
8165 && (modrm.mod != 3)
8166 && (modrm.rm == 4))
8167 has_sib = 1;
8168
8169 /* Get the DREX byte. */
8170 FETCH_DATA (the_info, codep + 2 + has_sib);
8171 drex_byte = codep[has_sib+1];
8172 drex_reg = DREX_XMM (drex_byte);
8173 modrm_reg = modrm.reg + ((drex_byte & REX_R) ? 8 : 0);
8174
8175 /* Is OC0 legal? If not, hardwire oc0 == 0 */
8176 oc0 = DREX_OC0 (drex_byte);
8177 if ((flag_bytemode & DREX_NO_OC0) && oc0)
8178 BadOp ();
8179
8180 if (modrm.mod == 3)
8181 {
8182 /* regmem == register */
8183 modrm_regmem = modrm.rm + ((drex_byte & REX_B) ? 8 : 0);
8184 rex = rex_used = 0;
8185 /* skip modrm/drex since we don't call OP_E_extended. */
8186 codep += 2;
8187 }
8188 else
8189 {
8190 /* regmem == memory, fill in appropriate REX bits. */
8191 modrm_regmem = DREX_REG_MEMORY;
8192 rex = drex_byte & (REX_B | REX_X | REX_R);
8193 if (rex)
8194 rex |= REX_OPCODE;
8195 rex_used = rex;
8196 }
8197
8198 /* Based on the OC1/OC0 bits, lay out the arguments in the correct
8199 order. */
8200 switch (oc0)
8201 {
8202 default:
8203 BadOp ();
8204 return;
8205
8206 case 0:
8207 regs[0] = modrm_regmem;
8208 regs[1] = modrm_reg;
8209 regs[2] = drex_reg;
8210 break;
8211
8212 case 1:
8213 regs[0] = modrm_reg;
8214 regs[1] = modrm_regmem;
8215 regs[2] = drex_reg;
8216 break;
8217 }
8218
8219 /* Print out the arguments. */
8220 for (i = 0; i < 3; i++)
8221 {
8222 int j = (intel_syntax) ? 2 - i : i;
8223 if (i > 0)
8224 {
8225 *obufp++ = ',';
8226 *obufp = '\0';
8227 }
8228
8229 print_drex_arg (regs[j], bytemode, sizeflag);
8230 }
8231
8232 rex = rex_save;
8233 rex_used = rex_used_save;
8234 }
8235
8236 /* Emit a floating point comparison for comp<xx> instructions. */
8237
8238 static void
8239 OP_DREX_FCMP (int bytemode ATTRIBUTE_UNUSED,
8240 int sizeflag ATTRIBUTE_UNUSED)
8241 {
8242 unsigned char byte;
8243
8244 static const char *const cmp_test[] = {
8245 "eq",
8246 "lt",
8247 "le",
8248 "unord",
8249 "ne",
8250 "nlt",
8251 "nle",
8252 "ord",
8253 "ueq",
8254 "ult",
8255 "ule",
8256 "false",
8257 "une",
8258 "unlt",
8259 "unle",
8260 "true"
8261 };
8262
8263 FETCH_DATA (the_info, codep + 1);
8264 byte = *codep & 0xff;
8265
8266 if (byte >= ARRAY_SIZE (cmp_test)
8267 || obuf[0] != 'c'
8268 || obuf[1] != 'o'
8269 || obuf[2] != 'm')
8270 {
8271 /* The instruction isn't one we know about, so just append the
8272 extension byte as a numeric value. */
8273 OP_I (b_mode, 0);
8274 }
8275
8276 else
8277 {
8278 sprintf (scratchbuf, "com%s%s", cmp_test[byte], obuf+3);
8279 strcpy (obuf, scratchbuf);
8280 codep++;
8281 }
8282 }
8283
8284 /* Emit an integer point comparison for pcom<xx> instructions,
8285 rewriting the instruction to have the test inside of it. */
8286
8287 static void
8288 OP_DREX_ICMP (int bytemode ATTRIBUTE_UNUSED,
8289 int sizeflag ATTRIBUTE_UNUSED)
8290 {
8291 unsigned char byte;
8292
8293 static const char *const cmp_test[] = {
8294 "lt",
8295 "le",
8296 "gt",
8297 "ge",
8298 "eq",
8299 "ne",
8300 "false",
8301 "true"
8302 };
8303
8304 FETCH_DATA (the_info, codep + 1);
8305 byte = *codep & 0xff;
8306
8307 if (byte >= ARRAY_SIZE (cmp_test)
8308 || obuf[0] != 'p'
8309 || obuf[1] != 'c'
8310 || obuf[2] != 'o'
8311 || obuf[3] != 'm')
8312 {
8313 /* The instruction isn't one we know about, so just print the
8314 comparison test byte as a numeric value. */
8315 OP_I (b_mode, 0);
8316 }
8317
8318 else
8319 {
8320 sprintf (scratchbuf, "pcom%s%s", cmp_test[byte], obuf+4);
8321 strcpy (obuf, scratchbuf);
8322 codep++;
8323 }
8324 }