1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2021 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
36 #include "disassemble.h"
38 #include "opcode/i386.h"
39 #include "libiberty.h"
40 #include "safe-ctype.h"
44 static int print_insn (bfd_vma
, disassemble_info
*);
45 static void dofloat (int);
46 static void OP_ST (int, int);
47 static void OP_STi (int, int);
48 static int putop (const char *, int);
49 static void oappend (const char *);
50 static void append_seg (void);
51 static void OP_indirE (int, int);
52 static void print_operand_value (char *, int, bfd_vma
);
53 static void OP_E_register (int, int);
54 static void OP_E_memory (int, int);
55 static void print_displacement (char *, bfd_vma
);
56 static void OP_E (int, int);
57 static void OP_G (int, int);
58 static bfd_vma
get64 (void);
59 static bfd_signed_vma
get32 (void);
60 static bfd_signed_vma
get32s (void);
61 static int get16 (void);
62 static void set_op (bfd_vma
, int);
63 static void OP_Skip_MODRM (int, int);
64 static void OP_REG (int, int);
65 static void OP_IMREG (int, int);
66 static void OP_I (int, int);
67 static void OP_I64 (int, int);
68 static void OP_sI (int, int);
69 static void OP_J (int, int);
70 static void OP_SEG (int, int);
71 static void OP_DIR (int, int);
72 static void OP_OFF (int, int);
73 static void OP_OFF64 (int, int);
74 static void ptr_reg (int, int);
75 static void OP_ESreg (int, int);
76 static void OP_DSreg (int, int);
77 static void OP_C (int, int);
78 static void OP_D (int, int);
79 static void OP_T (int, int);
80 static void OP_MMX (int, int);
81 static void OP_XMM (int, int);
82 static void OP_EM (int, int);
83 static void OP_EX (int, int);
84 static void OP_EMC (int,int);
85 static void OP_MXC (int,int);
86 static void OP_MS (int, int);
87 static void OP_XS (int, int);
88 static void OP_M (int, int);
89 static void OP_VEX (int, int);
90 static void OP_VexR (int, int);
91 static void OP_VexW (int, int);
92 static void OP_Rounding (int, int);
93 static void OP_REG_VexI4 (int, int);
94 static void OP_VexI4 (int, int);
95 static void PCLMUL_Fixup (int, int);
96 static void VPCMP_Fixup (int, int);
97 static void VPCOM_Fixup (int, int);
98 static void OP_0f07 (int, int);
99 static void OP_Monitor (int, int);
100 static void OP_Mwait (int, int);
101 static void NOP_Fixup1 (int, int);
102 static void NOP_Fixup2 (int, int);
103 static void OP_3DNowSuffix (int, int);
104 static void CMP_Fixup (int, int);
105 static void BadOp (void);
106 static void REP_Fixup (int, int);
107 static void SEP_Fixup (int, int);
108 static void BND_Fixup (int, int);
109 static void NOTRACK_Fixup (int, int);
110 static void HLE_Fixup1 (int, int);
111 static void HLE_Fixup2 (int, int);
112 static void HLE_Fixup3 (int, int);
113 static void CMPXCHG8B_Fixup (int, int);
114 static void XMM_Fixup (int, int);
115 static void FXSAVE_Fixup (int, int);
117 static void MOVSXD_Fixup (int, int);
120 /* Points to first byte not fetched. */
121 bfd_byte
*max_fetched
;
122 bfd_byte the_buffer
[MAX_MNEM_SIZE
];
125 OPCODES_SIGJMP_BUF bailout
;
135 enum address_mode address_mode
;
137 /* Flags for the prefixes for the current instruction. See below. */
140 /* REX prefix the current instruction. See below. */
142 /* Bits of REX we've already used. */
144 /* Mark parts used in the REX prefix. When we are testing for
145 empty prefix (for 8bit register REX extension), just mask it
146 out. Otherwise test for REX bit is excuse for existence of REX
147 only in case value is nonzero. */
148 #define USED_REX(value) \
153 rex_used |= (value) | REX_OPCODE; \
156 rex_used |= REX_OPCODE; \
159 /* Flags for prefixes which we somehow handled when printing the
160 current instruction. */
161 static int used_prefixes
;
163 /* Flags stored in PREFIXES. */
164 #define PREFIX_REPZ 1
165 #define PREFIX_REPNZ 2
166 #define PREFIX_LOCK 4
168 #define PREFIX_SS 0x10
169 #define PREFIX_DS 0x20
170 #define PREFIX_ES 0x40
171 #define PREFIX_FS 0x80
172 #define PREFIX_GS 0x100
173 #define PREFIX_DATA 0x200
174 #define PREFIX_ADDR 0x400
175 #define PREFIX_FWAIT 0x800
177 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
178 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
180 #define FETCH_DATA(info, addr) \
181 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
182 ? 1 : fetch_data ((info), (addr)))
185 fetch_data (struct disassemble_info
*info
, bfd_byte
*addr
)
188 struct dis_private
*priv
= (struct dis_private
*) info
->private_data
;
189 bfd_vma start
= priv
->insn_start
+ (priv
->max_fetched
- priv
->the_buffer
);
191 if (addr
<= priv
->the_buffer
+ MAX_MNEM_SIZE
)
192 status
= (*info
->read_memory_func
) (start
,
194 addr
- priv
->max_fetched
,
200 /* If we did manage to read at least one byte, then
201 print_insn_i386 will do something sensible. Otherwise, print
202 an error. We do that here because this is where we know
204 if (priv
->max_fetched
== priv
->the_buffer
)
205 (*info
->memory_error_func
) (status
, start
, info
);
206 OPCODES_SIGLONGJMP (priv
->bailout
, 1);
209 priv
->max_fetched
= addr
;
213 /* Possible values for prefix requirement. */
214 #define PREFIX_IGNORED_SHIFT 16
215 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
216 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
217 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
218 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
219 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
221 /* Opcode prefixes. */
222 #define PREFIX_OPCODE (PREFIX_REPZ \
226 /* Prefixes ignored. */
227 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
228 | PREFIX_IGNORED_REPNZ \
229 | PREFIX_IGNORED_DATA)
231 #define XX { NULL, 0 }
232 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
234 #define Eb { OP_E, b_mode }
235 #define Ebnd { OP_E, bnd_mode }
236 #define EbS { OP_E, b_swap_mode }
237 #define EbndS { OP_E, bnd_swap_mode }
238 #define Ev { OP_E, v_mode }
239 #define Eva { OP_E, va_mode }
240 #define Ev_bnd { OP_E, v_bnd_mode }
241 #define EvS { OP_E, v_swap_mode }
242 #define Ed { OP_E, d_mode }
243 #define Edq { OP_E, dq_mode }
244 #define Edqw { OP_E, dqw_mode }
245 #define Edqb { OP_E, dqb_mode }
246 #define Edb { OP_E, db_mode }
247 #define Edw { OP_E, dw_mode }
248 #define Edqd { OP_E, dqd_mode }
249 #define Eq { OP_E, q_mode }
250 #define indirEv { OP_indirE, indir_v_mode }
251 #define indirEp { OP_indirE, f_mode }
252 #define stackEv { OP_E, stack_v_mode }
253 #define Em { OP_E, m_mode }
254 #define Ew { OP_E, w_mode }
255 #define M { OP_M, 0 } /* lea, lgdt, etc. */
256 #define Ma { OP_M, a_mode }
257 #define Mb { OP_M, b_mode }
258 #define Md { OP_M, d_mode }
259 #define Mo { OP_M, o_mode }
260 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
261 #define Mq { OP_M, q_mode }
262 #define Mv { OP_M, v_mode }
263 #define Mv_bnd { OP_M, v_bndmk_mode }
264 #define Mx { OP_M, x_mode }
265 #define Mxmm { OP_M, xmm_mode }
266 #define Gb { OP_G, b_mode }
267 #define Gbnd { OP_G, bnd_mode }
268 #define Gv { OP_G, v_mode }
269 #define Gd { OP_G, d_mode }
270 #define Gdq { OP_G, dq_mode }
271 #define Gm { OP_G, m_mode }
272 #define Gva { OP_G, va_mode }
273 #define Gw { OP_G, w_mode }
274 #define Ib { OP_I, b_mode }
275 #define sIb { OP_sI, b_mode } /* sign extened byte */
276 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
277 #define Iv { OP_I, v_mode }
278 #define sIv { OP_sI, v_mode }
279 #define Iv64 { OP_I64, v_mode }
280 #define Id { OP_I, d_mode }
281 #define Iw { OP_I, w_mode }
282 #define I1 { OP_I, const_1_mode }
283 #define Jb { OP_J, b_mode }
284 #define Jv { OP_J, v_mode }
285 #define Jdqw { OP_J, dqw_mode }
286 #define Cm { OP_C, m_mode }
287 #define Dm { OP_D, m_mode }
288 #define Td { OP_T, d_mode }
289 #define Skip_MODRM { OP_Skip_MODRM, 0 }
291 #define RMeAX { OP_REG, eAX_reg }
292 #define RMeBX { OP_REG, eBX_reg }
293 #define RMeCX { OP_REG, eCX_reg }
294 #define RMeDX { OP_REG, eDX_reg }
295 #define RMeSP { OP_REG, eSP_reg }
296 #define RMeBP { OP_REG, eBP_reg }
297 #define RMeSI { OP_REG, eSI_reg }
298 #define RMeDI { OP_REG, eDI_reg }
299 #define RMrAX { OP_REG, rAX_reg }
300 #define RMrBX { OP_REG, rBX_reg }
301 #define RMrCX { OP_REG, rCX_reg }
302 #define RMrDX { OP_REG, rDX_reg }
303 #define RMrSP { OP_REG, rSP_reg }
304 #define RMrBP { OP_REG, rBP_reg }
305 #define RMrSI { OP_REG, rSI_reg }
306 #define RMrDI { OP_REG, rDI_reg }
307 #define RMAL { OP_REG, al_reg }
308 #define RMCL { OP_REG, cl_reg }
309 #define RMDL { OP_REG, dl_reg }
310 #define RMBL { OP_REG, bl_reg }
311 #define RMAH { OP_REG, ah_reg }
312 #define RMCH { OP_REG, ch_reg }
313 #define RMDH { OP_REG, dh_reg }
314 #define RMBH { OP_REG, bh_reg }
315 #define RMAX { OP_REG, ax_reg }
316 #define RMDX { OP_REG, dx_reg }
318 #define eAX { OP_IMREG, eAX_reg }
319 #define AL { OP_IMREG, al_reg }
320 #define CL { OP_IMREG, cl_reg }
321 #define zAX { OP_IMREG, z_mode_ax_reg }
322 #define indirDX { OP_IMREG, indir_dx_reg }
324 #define Sw { OP_SEG, w_mode }
325 #define Sv { OP_SEG, v_mode }
326 #define Ap { OP_DIR, 0 }
327 #define Ob { OP_OFF64, b_mode }
328 #define Ov { OP_OFF64, v_mode }
329 #define Xb { OP_DSreg, eSI_reg }
330 #define Xv { OP_DSreg, eSI_reg }
331 #define Xz { OP_DSreg, eSI_reg }
332 #define Yb { OP_ESreg, eDI_reg }
333 #define Yv { OP_ESreg, eDI_reg }
334 #define DSBX { OP_DSreg, eBX_reg }
336 #define es { OP_REG, es_reg }
337 #define ss { OP_REG, ss_reg }
338 #define cs { OP_REG, cs_reg }
339 #define ds { OP_REG, ds_reg }
340 #define fs { OP_REG, fs_reg }
341 #define gs { OP_REG, gs_reg }
343 #define MX { OP_MMX, 0 }
344 #define XM { OP_XMM, 0 }
345 #define XMScalar { OP_XMM, scalar_mode }
346 #define XMGatherD { OP_XMM, vex_vsib_d_w_dq_mode }
347 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
348 #define XMM { OP_XMM, xmm_mode }
349 #define TMM { OP_XMM, tmm_mode }
350 #define XMxmmq { OP_XMM, xmmq_mode }
351 #define EM { OP_EM, v_mode }
352 #define EMS { OP_EM, v_swap_mode }
353 #define EMd { OP_EM, d_mode }
354 #define EMx { OP_EM, x_mode }
355 #define EXbwUnit { OP_EX, bw_unit_mode }
356 #define EXw { OP_EX, w_mode }
357 #define EXd { OP_EX, d_mode }
358 #define EXdS { OP_EX, d_swap_mode }
359 #define EXq { OP_EX, q_mode }
360 #define EXqS { OP_EX, q_swap_mode }
361 #define EXx { OP_EX, x_mode }
362 #define EXxS { OP_EX, x_swap_mode }
363 #define EXxmm { OP_EX, xmm_mode }
364 #define EXymm { OP_EX, ymm_mode }
365 #define EXtmm { OP_EX, tmm_mode }
366 #define EXxmmq { OP_EX, xmmq_mode }
367 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
368 #define EXxmm_mb { OP_EX, xmm_mb_mode }
369 #define EXxmm_mw { OP_EX, xmm_mw_mode }
370 #define EXxmm_md { OP_EX, xmm_md_mode }
371 #define EXxmm_mq { OP_EX, xmm_mq_mode }
372 #define EXxmmdw { OP_EX, xmmdw_mode }
373 #define EXxmmqd { OP_EX, xmmqd_mode }
374 #define EXymmq { OP_EX, ymmq_mode }
375 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
376 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
377 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
378 #define MS { OP_MS, v_mode }
379 #define XS { OP_XS, v_mode }
380 #define EMCq { OP_EMC, q_mode }
381 #define MXC { OP_MXC, 0 }
382 #define OPSUF { OP_3DNowSuffix, 0 }
383 #define SEP { SEP_Fixup, 0 }
384 #define CMP { CMP_Fixup, 0 }
385 #define XMM0 { XMM_Fixup, 0 }
386 #define FXSAVE { FXSAVE_Fixup, 0 }
388 #define Vex { OP_VEX, vex_mode }
389 #define VexW { OP_VexW, vex_mode }
390 #define VexScalar { OP_VEX, vex_scalar_mode }
391 #define VexScalarR { OP_VexR, vex_scalar_mode }
392 #define VexGatherD { OP_VEX, vex_vsib_d_w_dq_mode }
393 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
394 #define VexGdq { OP_VEX, dq_mode }
395 #define VexTmm { OP_VEX, tmm_mode }
396 #define XMVexI4 { OP_REG_VexI4, x_mode }
397 #define XMVexScalarI4 { OP_REG_VexI4, scalar_mode }
398 #define VexI4 { OP_VexI4, 0 }
399 #define PCLMUL { PCLMUL_Fixup, 0 }
400 #define VPCMP { VPCMP_Fixup, 0 }
401 #define VPCOM { VPCOM_Fixup, 0 }
403 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
404 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
405 #define EXxEVexS { OP_Rounding, evex_sae_mode }
407 #define MaskG { OP_G, mask_mode }
408 #define MaskE { OP_E, mask_mode }
409 #define MaskBDE { OP_E, mask_bd_mode }
410 #define MaskVex { OP_VEX, mask_mode }
412 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
413 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
415 #define MVexSIBMEM { OP_M, vex_sibmem_mode }
417 /* Used handle "rep" prefix for string instructions. */
418 #define Xbr { REP_Fixup, eSI_reg }
419 #define Xvr { REP_Fixup, eSI_reg }
420 #define Ybr { REP_Fixup, eDI_reg }
421 #define Yvr { REP_Fixup, eDI_reg }
422 #define Yzr { REP_Fixup, eDI_reg }
423 #define indirDXr { REP_Fixup, indir_dx_reg }
424 #define ALr { REP_Fixup, al_reg }
425 #define eAXr { REP_Fixup, eAX_reg }
427 /* Used handle HLE prefix for lockable instructions. */
428 #define Ebh1 { HLE_Fixup1, b_mode }
429 #define Evh1 { HLE_Fixup1, v_mode }
430 #define Ebh2 { HLE_Fixup2, b_mode }
431 #define Evh2 { HLE_Fixup2, v_mode }
432 #define Ebh3 { HLE_Fixup3, b_mode }
433 #define Evh3 { HLE_Fixup3, v_mode }
435 #define BND { BND_Fixup, 0 }
436 #define NOTRACK { NOTRACK_Fixup, 0 }
438 #define cond_jump_flag { NULL, cond_jump_mode }
439 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
441 /* bits in sizeflag */
442 #define SUFFIX_ALWAYS 4
450 /* byte operand with operand swapped */
452 /* byte operand, sign extend like 'T' suffix */
454 /* operand size depends on prefixes */
456 /* operand size depends on prefixes with operand swapped */
458 /* operand size depends on address prefix */
462 /* double word operand */
464 /* double word operand with operand swapped */
466 /* quad word operand */
468 /* quad word operand with operand swapped */
470 /* ten-byte operand */
472 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
473 broadcast enabled. */
475 /* Similar to x_mode, but with different EVEX mem shifts. */
477 /* Similar to x_mode, but with yet different EVEX mem shifts. */
479 /* Similar to x_mode, but with disabled broadcast. */
481 /* Similar to x_mode, but with operands swapped and disabled broadcast
484 /* 16-byte XMM operand */
486 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
487 memory operand (depending on vector length). Broadcast isn't
490 /* Same as xmmq_mode, but broadcast is allowed. */
491 evex_half_bcst_xmmq_mode
,
492 /* XMM register or byte memory operand */
494 /* XMM register or word memory operand */
496 /* XMM register or double word memory operand */
498 /* XMM register or quad word memory operand */
500 /* 16-byte XMM, word, double word or quad word operand. */
502 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
504 /* 32-byte YMM operand */
506 /* quad word, ymmword or zmmword memory operand. */
508 /* 32-byte YMM or 16-byte word operand */
512 /* d_mode in 32bit, q_mode in 64bit mode. */
514 /* pair of v_mode operands */
520 /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */
522 /* operand size depends on REX prefixes. */
524 /* registers like dq_mode, memory like w_mode, displacements like
525 v_mode without considering Intel64 ISA. */
529 /* bounds operand with operand swapped */
531 /* 4- or 6-byte pointer operand */
534 /* v_mode for indirect branch opcodes. */
536 /* v_mode for stack-related opcodes. */
538 /* non-quad operand size depends on prefixes */
540 /* 16-byte operand */
542 /* registers like dq_mode, memory like b_mode. */
544 /* registers like d_mode, memory like b_mode. */
546 /* registers like d_mode, memory like w_mode. */
548 /* registers like dq_mode, memory like d_mode. */
550 /* normal vex mode */
553 /* Operand size depends on the VEX.W bit, with VSIB dword indices. */
554 vex_vsib_d_w_dq_mode
,
555 /* Operand size depends on the VEX.W bit, with VSIB qword indices. */
556 vex_vsib_q_w_dq_mode
,
557 /* mandatory non-vector SIB. */
560 /* scalar, ignore vector length. */
562 /* like vex_mode, ignore vector length. */
564 /* Operand size depends on the VEX.W bit, ignore vector length. */
565 vex_scalar_w_dq_mode
,
567 /* Static rounding. */
569 /* Static rounding, 64-bit mode only. */
570 evex_rounding_64_mode
,
571 /* Supress all exceptions. */
574 /* Mask register operand. */
576 /* Mask register operand. */
644 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
646 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
647 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
648 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
649 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
650 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
651 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
652 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
653 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
654 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
655 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
656 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
657 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
658 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
659 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
660 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
661 #define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I))
688 REG_0F3A0F_PREFIX_1_MOD_3
,
701 REG_VEX_0F3849_X86_64_P_0_W_0_M_1
,
706 REG_XOP_09_12_M_1_L_0
,
712 REG_EVEX_0F38C6_M_0_L_2
,
713 REG_EVEX_0F38C7_M_0_L_2
790 MOD_VEX_0F12_PREFIX_0
,
791 MOD_VEX_0F12_PREFIX_2
,
793 MOD_VEX_0F16_PREFIX_0
,
794 MOD_VEX_0F16_PREFIX_2
,
818 MOD_VEX_0FF0_PREFIX_3
,
825 MOD_VEX_0F3849_X86_64_P_0_W_0
,
826 MOD_VEX_0F3849_X86_64_P_2_W_0
,
827 MOD_VEX_0F3849_X86_64_P_3_W_0
,
828 MOD_VEX_0F384B_X86_64_P_1_W_0
,
829 MOD_VEX_0F384B_X86_64_P_2_W_0
,
830 MOD_VEX_0F384B_X86_64_P_3_W_0
,
832 MOD_VEX_0F385C_X86_64_P_1_W_0
,
833 MOD_VEX_0F385E_X86_64_P_0_W_0
,
834 MOD_VEX_0F385E_X86_64_P_1_W_0
,
835 MOD_VEX_0F385E_X86_64_P_2_W_0
,
836 MOD_VEX_0F385E_X86_64_P_3_W_0
,
846 MOD_EVEX_0F12_PREFIX_0
,
847 MOD_EVEX_0F12_PREFIX_2
,
849 MOD_EVEX_0F16_PREFIX_0
,
850 MOD_EVEX_0F16_PREFIX_2
,
856 MOD_EVEX_0F382A_P_1_W_1
,
858 MOD_EVEX_0F383A_P_1_W_0
,
878 RM_0F1E_P_1_MOD_3_REG_7
,
879 RM_0FAE_REG_6_MOD_3_P_0
,
881 RM_0F3A0F_P_1_MOD_3_REG_0
,
883 RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0
889 PREFIX_0F01_REG_1_RM_4
,
890 PREFIX_0F01_REG_1_RM_5
,
891 PREFIX_0F01_REG_1_RM_6
,
892 PREFIX_0F01_REG_1_RM_7
,
893 PREFIX_0F01_REG_3_RM_1
,
894 PREFIX_0F01_REG_5_MOD_0
,
895 PREFIX_0F01_REG_5_MOD_3_RM_0
,
896 PREFIX_0F01_REG_5_MOD_3_RM_1
,
897 PREFIX_0F01_REG_5_MOD_3_RM_2
,
898 PREFIX_0F01_REG_5_MOD_3_RM_4
,
899 PREFIX_0F01_REG_5_MOD_3_RM_5
,
900 PREFIX_0F01_REG_5_MOD_3_RM_6
,
901 PREFIX_0F01_REG_5_MOD_3_RM_7
,
902 PREFIX_0F01_REG_7_MOD_3_RM_2
,
903 PREFIX_0F01_REG_7_MOD_3_RM_6
,
904 PREFIX_0F01_REG_7_MOD_3_RM_7
,
942 PREFIX_0FAE_REG_0_MOD_3
,
943 PREFIX_0FAE_REG_1_MOD_3
,
944 PREFIX_0FAE_REG_2_MOD_3
,
945 PREFIX_0FAE_REG_3_MOD_3
,
946 PREFIX_0FAE_REG_4_MOD_0
,
947 PREFIX_0FAE_REG_4_MOD_3
,
948 PREFIX_0FAE_REG_5_MOD_3
,
949 PREFIX_0FAE_REG_6_MOD_0
,
950 PREFIX_0FAE_REG_6_MOD_3
,
951 PREFIX_0FAE_REG_7_MOD_0
,
956 PREFIX_0FC7_REG_6_MOD_0
,
957 PREFIX_0FC7_REG_6_MOD_3
,
958 PREFIX_0FC7_REG_7_MOD_3
,
986 PREFIX_VEX_0F41_L_1_M_1_W_0
,
987 PREFIX_VEX_0F41_L_1_M_1_W_1
,
988 PREFIX_VEX_0F42_L_1_M_1_W_0
,
989 PREFIX_VEX_0F42_L_1_M_1_W_1
,
990 PREFIX_VEX_0F44_L_0_M_1_W_0
,
991 PREFIX_VEX_0F44_L_0_M_1_W_1
,
992 PREFIX_VEX_0F45_L_1_M_1_W_0
,
993 PREFIX_VEX_0F45_L_1_M_1_W_1
,
994 PREFIX_VEX_0F46_L_1_M_1_W_0
,
995 PREFIX_VEX_0F46_L_1_M_1_W_1
,
996 PREFIX_VEX_0F47_L_1_M_1_W_0
,
997 PREFIX_VEX_0F47_L_1_M_1_W_1
,
998 PREFIX_VEX_0F4A_L_1_M_1_W_0
,
999 PREFIX_VEX_0F4A_L_1_M_1_W_1
,
1000 PREFIX_VEX_0F4B_L_1_M_1_W_0
,
1001 PREFIX_VEX_0F4B_L_1_M_1_W_1
,
1019 PREFIX_VEX_0F90_L_0_W_0
,
1020 PREFIX_VEX_0F90_L_0_W_1
,
1021 PREFIX_VEX_0F91_L_0_M_0_W_0
,
1022 PREFIX_VEX_0F91_L_0_M_0_W_1
,
1023 PREFIX_VEX_0F92_L_0_M_1_W_0
,
1024 PREFIX_VEX_0F92_L_0_M_1_W_1
,
1025 PREFIX_VEX_0F93_L_0_M_1_W_0
,
1026 PREFIX_VEX_0F93_L_0_M_1_W_1
,
1027 PREFIX_VEX_0F98_L_0_M_1_W_0
,
1028 PREFIX_VEX_0F98_L_0_M_1_W_1
,
1029 PREFIX_VEX_0F99_L_0_M_1_W_0
,
1030 PREFIX_VEX_0F99_L_0_M_1_W_1
,
1035 PREFIX_VEX_0F3849_X86_64
,
1036 PREFIX_VEX_0F384B_X86_64
,
1037 PREFIX_VEX_0F385C_X86_64
,
1038 PREFIX_VEX_0F385E_X86_64
,
1039 PREFIX_VEX_0F38F5_L_0
,
1040 PREFIX_VEX_0F38F6_L_0
,
1041 PREFIX_VEX_0F38F7_L_0
,
1042 PREFIX_VEX_0F3AF0_L_0
,
1137 X86_64_0F01_REG_1_RM_5_PREFIX_2
,
1138 X86_64_0F01_REG_1_RM_6_PREFIX_2
,
1139 X86_64_0F01_REG_1_RM_7_PREFIX_2
,
1142 X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1
,
1143 X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1
,
1144 X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1
,
1145 X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1
,
1146 X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1
,
1147 X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3
,
1148 X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1
,
1151 X86_64_0FC7_REG_6_MOD_3_PREFIX_1
,
1161 THREE_BYTE_0F38
= 0,
1188 VEX_LEN_0F12_P_0_M_0
= 0,
1189 VEX_LEN_0F12_P_0_M_1
,
1190 #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0
1192 VEX_LEN_0F16_P_0_M_0
,
1193 VEX_LEN_0F16_P_0_M_1
,
1194 #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0
1214 VEX_LEN_0FAE_R_2_M_0
,
1215 VEX_LEN_0FAE_R_3_M_0
,
1225 VEX_LEN_0F3849_X86_64_P_0_W_0_M_0
,
1226 VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0
,
1227 VEX_LEN_0F3849_X86_64_P_2_W_0_M_0
,
1228 VEX_LEN_0F3849_X86_64_P_3_W_0_M_0
,
1229 VEX_LEN_0F384B_X86_64_P_1_W_0_M_0
,
1230 VEX_LEN_0F384B_X86_64_P_2_W_0_M_0
,
1231 VEX_LEN_0F384B_X86_64_P_3_W_0_M_0
,
1233 VEX_LEN_0F385C_X86_64_P_1_W_0_M_0
,
1234 VEX_LEN_0F385E_X86_64_P_0_W_0_M_0
,
1235 VEX_LEN_0F385E_X86_64_P_1_W_0_M_0
,
1236 VEX_LEN_0F385E_X86_64_P_2_W_0_M_0
,
1237 VEX_LEN_0F385E_X86_64_P_3_W_0_M_0
,
1270 VEX_LEN_0FXOP_08_85
,
1271 VEX_LEN_0FXOP_08_86
,
1272 VEX_LEN_0FXOP_08_87
,
1273 VEX_LEN_0FXOP_08_8E
,
1274 VEX_LEN_0FXOP_08_8F
,
1275 VEX_LEN_0FXOP_08_95
,
1276 VEX_LEN_0FXOP_08_96
,
1277 VEX_LEN_0FXOP_08_97
,
1278 VEX_LEN_0FXOP_08_9E
,
1279 VEX_LEN_0FXOP_08_9F
,
1280 VEX_LEN_0FXOP_08_A3
,
1281 VEX_LEN_0FXOP_08_A6
,
1282 VEX_LEN_0FXOP_08_B6
,
1283 VEX_LEN_0FXOP_08_C0
,
1284 VEX_LEN_0FXOP_08_C1
,
1285 VEX_LEN_0FXOP_08_C2
,
1286 VEX_LEN_0FXOP_08_C3
,
1287 VEX_LEN_0FXOP_08_CC
,
1288 VEX_LEN_0FXOP_08_CD
,
1289 VEX_LEN_0FXOP_08_CE
,
1290 VEX_LEN_0FXOP_08_CF
,
1291 VEX_LEN_0FXOP_08_EC
,
1292 VEX_LEN_0FXOP_08_ED
,
1293 VEX_LEN_0FXOP_08_EE
,
1294 VEX_LEN_0FXOP_08_EF
,
1295 VEX_LEN_0FXOP_09_01
,
1296 VEX_LEN_0FXOP_09_02
,
1297 VEX_LEN_0FXOP_09_12_M_1
,
1298 VEX_LEN_0FXOP_09_82_W_0
,
1299 VEX_LEN_0FXOP_09_83_W_0
,
1300 VEX_LEN_0FXOP_09_90
,
1301 VEX_LEN_0FXOP_09_91
,
1302 VEX_LEN_0FXOP_09_92
,
1303 VEX_LEN_0FXOP_09_93
,
1304 VEX_LEN_0FXOP_09_94
,
1305 VEX_LEN_0FXOP_09_95
,
1306 VEX_LEN_0FXOP_09_96
,
1307 VEX_LEN_0FXOP_09_97
,
1308 VEX_LEN_0FXOP_09_98
,
1309 VEX_LEN_0FXOP_09_99
,
1310 VEX_LEN_0FXOP_09_9A
,
1311 VEX_LEN_0FXOP_09_9B
,
1312 VEX_LEN_0FXOP_09_C1
,
1313 VEX_LEN_0FXOP_09_C2
,
1314 VEX_LEN_0FXOP_09_C3
,
1315 VEX_LEN_0FXOP_09_C6
,
1316 VEX_LEN_0FXOP_09_C7
,
1317 VEX_LEN_0FXOP_09_CB
,
1318 VEX_LEN_0FXOP_09_D1
,
1319 VEX_LEN_0FXOP_09_D2
,
1320 VEX_LEN_0FXOP_09_D3
,
1321 VEX_LEN_0FXOP_09_D6
,
1322 VEX_LEN_0FXOP_09_D7
,
1323 VEX_LEN_0FXOP_09_DB
,
1324 VEX_LEN_0FXOP_09_E1
,
1325 VEX_LEN_0FXOP_09_E2
,
1326 VEX_LEN_0FXOP_09_E3
,
1327 VEX_LEN_0FXOP_0A_12
,
1332 EVEX_LEN_0F3816
= 0,
1334 EVEX_LEN_0F381A_M_0
,
1335 EVEX_LEN_0F381B_M_0
,
1337 EVEX_LEN_0F385A_M_0
,
1338 EVEX_LEN_0F385B_M_0
,
1339 EVEX_LEN_0F38C6_M_0
,
1340 EVEX_LEN_0F38C7_M_0
,
1357 VEX_W_0F41_L_1_M_1
= 0,
1379 VEX_W_0F381A_M_0_L_1
,
1386 VEX_W_0F3849_X86_64_P_0
,
1387 VEX_W_0F3849_X86_64_P_2
,
1388 VEX_W_0F3849_X86_64_P_3
,
1389 VEX_W_0F384B_X86_64_P_1
,
1390 VEX_W_0F384B_X86_64_P_2
,
1391 VEX_W_0F384B_X86_64_P_3
,
1398 VEX_W_0F385A_M_0_L_0
,
1399 VEX_W_0F385C_X86_64_P_1
,
1400 VEX_W_0F385E_X86_64_P_0
,
1401 VEX_W_0F385E_X86_64_P_1
,
1402 VEX_W_0F385E_X86_64_P_2
,
1403 VEX_W_0F385E_X86_64_P_3
,
1425 VEX_W_0FXOP_08_85_L_0
,
1426 VEX_W_0FXOP_08_86_L_0
,
1427 VEX_W_0FXOP_08_87_L_0
,
1428 VEX_W_0FXOP_08_8E_L_0
,
1429 VEX_W_0FXOP_08_8F_L_0
,
1430 VEX_W_0FXOP_08_95_L_0
,
1431 VEX_W_0FXOP_08_96_L_0
,
1432 VEX_W_0FXOP_08_97_L_0
,
1433 VEX_W_0FXOP_08_9E_L_0
,
1434 VEX_W_0FXOP_08_9F_L_0
,
1435 VEX_W_0FXOP_08_A6_L_0
,
1436 VEX_W_0FXOP_08_B6_L_0
,
1437 VEX_W_0FXOP_08_C0_L_0
,
1438 VEX_W_0FXOP_08_C1_L_0
,
1439 VEX_W_0FXOP_08_C2_L_0
,
1440 VEX_W_0FXOP_08_C3_L_0
,
1441 VEX_W_0FXOP_08_CC_L_0
,
1442 VEX_W_0FXOP_08_CD_L_0
,
1443 VEX_W_0FXOP_08_CE_L_0
,
1444 VEX_W_0FXOP_08_CF_L_0
,
1445 VEX_W_0FXOP_08_EC_L_0
,
1446 VEX_W_0FXOP_08_ED_L_0
,
1447 VEX_W_0FXOP_08_EE_L_0
,
1448 VEX_W_0FXOP_08_EF_L_0
,
1454 VEX_W_0FXOP_09_C1_L_0
,
1455 VEX_W_0FXOP_09_C2_L_0
,
1456 VEX_W_0FXOP_09_C3_L_0
,
1457 VEX_W_0FXOP_09_C6_L_0
,
1458 VEX_W_0FXOP_09_C7_L_0
,
1459 VEX_W_0FXOP_09_CB_L_0
,
1460 VEX_W_0FXOP_09_D1_L_0
,
1461 VEX_W_0FXOP_09_D2_L_0
,
1462 VEX_W_0FXOP_09_D3_L_0
,
1463 VEX_W_0FXOP_09_D6_L_0
,
1464 VEX_W_0FXOP_09_D7_L_0
,
1465 VEX_W_0FXOP_09_DB_L_0
,
1466 VEX_W_0FXOP_09_E1_L_0
,
1467 VEX_W_0FXOP_09_E2_L_0
,
1468 VEX_W_0FXOP_09_E3_L_0
,
1474 EVEX_W_0F12_P_0_M_1
,
1477 EVEX_W_0F16_P_0_M_1
,
1555 EVEX_W_0F381A_M_0_L_n
,
1556 EVEX_W_0F381B_M_0_L_2
,
1582 EVEX_W_0F385A_M_0_L_n
,
1583 EVEX_W_0F385B_M_0_L_2
,
1613 typedef void (*op_rtn
) (int bytemode
, int sizeflag
);
1622 unsigned int prefix_requirement
;
1625 /* Upper case letters in the instruction names here are macros.
1626 'A' => print 'b' if no register operands or suffix_always is true
1627 'B' => print 'b' if suffix_always is true
1628 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1630 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1631 suffix_always is true
1632 'E' => print 'e' if 32-bit form of jcxz
1633 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1634 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1635 'H' => print ",pt" or ",pn" branch hint
1638 'K' => print 'd' or 'q' if rex prefix is present.
1640 'M' => print 'r' if intel_mnemonic is false.
1641 'N' => print 'n' if instruction has no wait "prefix"
1642 'O' => print 'd' or 'o' (or 'q' in Intel mode)
1643 'P' => behave as 'T' except with register operand outside of suffix_always
1645 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1647 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1648 'S' => print 'w', 'l' or 'q' if suffix_always is true
1649 'T' => print 'w', 'l'/'d', or 'q' if instruction has an operand size
1650 prefix or if suffix_always is true.
1653 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1654 'X' => print 's', 'd' depending on data16 prefix (for XMM)
1656 'Z' => print 'q' in 64bit mode and 'l' otherwise, if suffix_always is true.
1657 '!' => change condition from true to false or from false to true.
1658 '%' => add 1 upper case letter to the macro.
1659 '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
1660 prefix or suffix_always is true (lcall/ljmp).
1661 '@' => in 64bit mode for Intel64 ISA or if instruction
1662 has no operand sizing prefix, print 'q' if suffix_always is true or
1663 nothing otherwise; behave as 'P' in all other cases
1665 2 upper case letter macros:
1666 "XY" => print 'x' or 'y' if suffix_always is true or no register
1667 operands and no broadcast.
1668 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
1669 register operands and no broadcast.
1670 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1671 "XV" => print "{vex3}" pseudo prefix
1672 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond
1673 being false, or no operand at all in 64bit mode, or if suffix_always
1675 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1676 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1677 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1678 "DQ" => print 'd' or 'q' depending on the VEX.W bit
1679 "BW" => print 'b' or 'w' depending on the VEX.W bit
1680 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
1681 an operand size prefix, or suffix_always is true. print
1682 'q' if rex prefix is present.
1684 Many of the above letters print nothing in Intel mode. See "putop"
1687 Braces '{' and '}', and vertical bars '|', indicate alternative
1688 mnemonic strings for AT&T and Intel. */
1690 static const struct dis386 dis386
[] = {
1692 { "addB", { Ebh1
, Gb
}, 0 },
1693 { "addS", { Evh1
, Gv
}, 0 },
1694 { "addB", { Gb
, EbS
}, 0 },
1695 { "addS", { Gv
, EvS
}, 0 },
1696 { "addB", { AL
, Ib
}, 0 },
1697 { "addS", { eAX
, Iv
}, 0 },
1698 { X86_64_TABLE (X86_64_06
) },
1699 { X86_64_TABLE (X86_64_07
) },
1701 { "orB", { Ebh1
, Gb
}, 0 },
1702 { "orS", { Evh1
, Gv
}, 0 },
1703 { "orB", { Gb
, EbS
}, 0 },
1704 { "orS", { Gv
, EvS
}, 0 },
1705 { "orB", { AL
, Ib
}, 0 },
1706 { "orS", { eAX
, Iv
}, 0 },
1707 { X86_64_TABLE (X86_64_0E
) },
1708 { Bad_Opcode
}, /* 0x0f extended opcode escape */
1710 { "adcB", { Ebh1
, Gb
}, 0 },
1711 { "adcS", { Evh1
, Gv
}, 0 },
1712 { "adcB", { Gb
, EbS
}, 0 },
1713 { "adcS", { Gv
, EvS
}, 0 },
1714 { "adcB", { AL
, Ib
}, 0 },
1715 { "adcS", { eAX
, Iv
}, 0 },
1716 { X86_64_TABLE (X86_64_16
) },
1717 { X86_64_TABLE (X86_64_17
) },
1719 { "sbbB", { Ebh1
, Gb
}, 0 },
1720 { "sbbS", { Evh1
, Gv
}, 0 },
1721 { "sbbB", { Gb
, EbS
}, 0 },
1722 { "sbbS", { Gv
, EvS
}, 0 },
1723 { "sbbB", { AL
, Ib
}, 0 },
1724 { "sbbS", { eAX
, Iv
}, 0 },
1725 { X86_64_TABLE (X86_64_1E
) },
1726 { X86_64_TABLE (X86_64_1F
) },
1728 { "andB", { Ebh1
, Gb
}, 0 },
1729 { "andS", { Evh1
, Gv
}, 0 },
1730 { "andB", { Gb
, EbS
}, 0 },
1731 { "andS", { Gv
, EvS
}, 0 },
1732 { "andB", { AL
, Ib
}, 0 },
1733 { "andS", { eAX
, Iv
}, 0 },
1734 { Bad_Opcode
}, /* SEG ES prefix */
1735 { X86_64_TABLE (X86_64_27
) },
1737 { "subB", { Ebh1
, Gb
}, 0 },
1738 { "subS", { Evh1
, Gv
}, 0 },
1739 { "subB", { Gb
, EbS
}, 0 },
1740 { "subS", { Gv
, EvS
}, 0 },
1741 { "subB", { AL
, Ib
}, 0 },
1742 { "subS", { eAX
, Iv
}, 0 },
1743 { Bad_Opcode
}, /* SEG CS prefix */
1744 { X86_64_TABLE (X86_64_2F
) },
1746 { "xorB", { Ebh1
, Gb
}, 0 },
1747 { "xorS", { Evh1
, Gv
}, 0 },
1748 { "xorB", { Gb
, EbS
}, 0 },
1749 { "xorS", { Gv
, EvS
}, 0 },
1750 { "xorB", { AL
, Ib
}, 0 },
1751 { "xorS", { eAX
, Iv
}, 0 },
1752 { Bad_Opcode
}, /* SEG SS prefix */
1753 { X86_64_TABLE (X86_64_37
) },
1755 { "cmpB", { Eb
, Gb
}, 0 },
1756 { "cmpS", { Ev
, Gv
}, 0 },
1757 { "cmpB", { Gb
, EbS
}, 0 },
1758 { "cmpS", { Gv
, EvS
}, 0 },
1759 { "cmpB", { AL
, Ib
}, 0 },
1760 { "cmpS", { eAX
, Iv
}, 0 },
1761 { Bad_Opcode
}, /* SEG DS prefix */
1762 { X86_64_TABLE (X86_64_3F
) },
1764 { "inc{S|}", { RMeAX
}, 0 },
1765 { "inc{S|}", { RMeCX
}, 0 },
1766 { "inc{S|}", { RMeDX
}, 0 },
1767 { "inc{S|}", { RMeBX
}, 0 },
1768 { "inc{S|}", { RMeSP
}, 0 },
1769 { "inc{S|}", { RMeBP
}, 0 },
1770 { "inc{S|}", { RMeSI
}, 0 },
1771 { "inc{S|}", { RMeDI
}, 0 },
1773 { "dec{S|}", { RMeAX
}, 0 },
1774 { "dec{S|}", { RMeCX
}, 0 },
1775 { "dec{S|}", { RMeDX
}, 0 },
1776 { "dec{S|}", { RMeBX
}, 0 },
1777 { "dec{S|}", { RMeSP
}, 0 },
1778 { "dec{S|}", { RMeBP
}, 0 },
1779 { "dec{S|}", { RMeSI
}, 0 },
1780 { "dec{S|}", { RMeDI
}, 0 },
1782 { "push{!P|}", { RMrAX
}, 0 },
1783 { "push{!P|}", { RMrCX
}, 0 },
1784 { "push{!P|}", { RMrDX
}, 0 },
1785 { "push{!P|}", { RMrBX
}, 0 },
1786 { "push{!P|}", { RMrSP
}, 0 },
1787 { "push{!P|}", { RMrBP
}, 0 },
1788 { "push{!P|}", { RMrSI
}, 0 },
1789 { "push{!P|}", { RMrDI
}, 0 },
1791 { "pop{!P|}", { RMrAX
}, 0 },
1792 { "pop{!P|}", { RMrCX
}, 0 },
1793 { "pop{!P|}", { RMrDX
}, 0 },
1794 { "pop{!P|}", { RMrBX
}, 0 },
1795 { "pop{!P|}", { RMrSP
}, 0 },
1796 { "pop{!P|}", { RMrBP
}, 0 },
1797 { "pop{!P|}", { RMrSI
}, 0 },
1798 { "pop{!P|}", { RMrDI
}, 0 },
1800 { X86_64_TABLE (X86_64_60
) },
1801 { X86_64_TABLE (X86_64_61
) },
1802 { X86_64_TABLE (X86_64_62
) },
1803 { X86_64_TABLE (X86_64_63
) },
1804 { Bad_Opcode
}, /* seg fs */
1805 { Bad_Opcode
}, /* seg gs */
1806 { Bad_Opcode
}, /* op size prefix */
1807 { Bad_Opcode
}, /* adr size prefix */
1809 { "pushP", { sIv
}, 0 },
1810 { "imulS", { Gv
, Ev
, Iv
}, 0 },
1811 { "pushP", { sIbT
}, 0 },
1812 { "imulS", { Gv
, Ev
, sIb
}, 0 },
1813 { "ins{b|}", { Ybr
, indirDX
}, 0 },
1814 { X86_64_TABLE (X86_64_6D
) },
1815 { "outs{b|}", { indirDXr
, Xb
}, 0 },
1816 { X86_64_TABLE (X86_64_6F
) },
1818 { "joH", { Jb
, BND
, cond_jump_flag
}, 0 },
1819 { "jnoH", { Jb
, BND
, cond_jump_flag
}, 0 },
1820 { "jbH", { Jb
, BND
, cond_jump_flag
}, 0 },
1821 { "jaeH", { Jb
, BND
, cond_jump_flag
}, 0 },
1822 { "jeH", { Jb
, BND
, cond_jump_flag
}, 0 },
1823 { "jneH", { Jb
, BND
, cond_jump_flag
}, 0 },
1824 { "jbeH", { Jb
, BND
, cond_jump_flag
}, 0 },
1825 { "jaH", { Jb
, BND
, cond_jump_flag
}, 0 },
1827 { "jsH", { Jb
, BND
, cond_jump_flag
}, 0 },
1828 { "jnsH", { Jb
, BND
, cond_jump_flag
}, 0 },
1829 { "jpH", { Jb
, BND
, cond_jump_flag
}, 0 },
1830 { "jnpH", { Jb
, BND
, cond_jump_flag
}, 0 },
1831 { "jlH", { Jb
, BND
, cond_jump_flag
}, 0 },
1832 { "jgeH", { Jb
, BND
, cond_jump_flag
}, 0 },
1833 { "jleH", { Jb
, BND
, cond_jump_flag
}, 0 },
1834 { "jgH", { Jb
, BND
, cond_jump_flag
}, 0 },
1836 { REG_TABLE (REG_80
) },
1837 { REG_TABLE (REG_81
) },
1838 { X86_64_TABLE (X86_64_82
) },
1839 { REG_TABLE (REG_83
) },
1840 { "testB", { Eb
, Gb
}, 0 },
1841 { "testS", { Ev
, Gv
}, 0 },
1842 { "xchgB", { Ebh2
, Gb
}, 0 },
1843 { "xchgS", { Evh2
, Gv
}, 0 },
1845 { "movB", { Ebh3
, Gb
}, 0 },
1846 { "movS", { Evh3
, Gv
}, 0 },
1847 { "movB", { Gb
, EbS
}, 0 },
1848 { "movS", { Gv
, EvS
}, 0 },
1849 { "movD", { Sv
, Sw
}, 0 },
1850 { MOD_TABLE (MOD_8D
) },
1851 { "movD", { Sw
, Sv
}, 0 },
1852 { REG_TABLE (REG_8F
) },
1854 { PREFIX_TABLE (PREFIX_90
) },
1855 { "xchgS", { RMeCX
, eAX
}, 0 },
1856 { "xchgS", { RMeDX
, eAX
}, 0 },
1857 { "xchgS", { RMeBX
, eAX
}, 0 },
1858 { "xchgS", { RMeSP
, eAX
}, 0 },
1859 { "xchgS", { RMeBP
, eAX
}, 0 },
1860 { "xchgS", { RMeSI
, eAX
}, 0 },
1861 { "xchgS", { RMeDI
, eAX
}, 0 },
1863 { "cW{t|}R", { XX
}, 0 },
1864 { "cR{t|}O", { XX
}, 0 },
1865 { X86_64_TABLE (X86_64_9A
) },
1866 { Bad_Opcode
}, /* fwait */
1867 { "pushfP", { XX
}, 0 },
1868 { "popfP", { XX
}, 0 },
1869 { "sahf", { XX
}, 0 },
1870 { "lahf", { XX
}, 0 },
1872 { "mov%LB", { AL
, Ob
}, 0 },
1873 { "mov%LS", { eAX
, Ov
}, 0 },
1874 { "mov%LB", { Ob
, AL
}, 0 },
1875 { "mov%LS", { Ov
, eAX
}, 0 },
1876 { "movs{b|}", { Ybr
, Xb
}, 0 },
1877 { "movs{R|}", { Yvr
, Xv
}, 0 },
1878 { "cmps{b|}", { Xb
, Yb
}, 0 },
1879 { "cmps{R|}", { Xv
, Yv
}, 0 },
1881 { "testB", { AL
, Ib
}, 0 },
1882 { "testS", { eAX
, Iv
}, 0 },
1883 { "stosB", { Ybr
, AL
}, 0 },
1884 { "stosS", { Yvr
, eAX
}, 0 },
1885 { "lodsB", { ALr
, Xb
}, 0 },
1886 { "lodsS", { eAXr
, Xv
}, 0 },
1887 { "scasB", { AL
, Yb
}, 0 },
1888 { "scasS", { eAX
, Yv
}, 0 },
1890 { "movB", { RMAL
, Ib
}, 0 },
1891 { "movB", { RMCL
, Ib
}, 0 },
1892 { "movB", { RMDL
, Ib
}, 0 },
1893 { "movB", { RMBL
, Ib
}, 0 },
1894 { "movB", { RMAH
, Ib
}, 0 },
1895 { "movB", { RMCH
, Ib
}, 0 },
1896 { "movB", { RMDH
, Ib
}, 0 },
1897 { "movB", { RMBH
, Ib
}, 0 },
1899 { "mov%LV", { RMeAX
, Iv64
}, 0 },
1900 { "mov%LV", { RMeCX
, Iv64
}, 0 },
1901 { "mov%LV", { RMeDX
, Iv64
}, 0 },
1902 { "mov%LV", { RMeBX
, Iv64
}, 0 },
1903 { "mov%LV", { RMeSP
, Iv64
}, 0 },
1904 { "mov%LV", { RMeBP
, Iv64
}, 0 },
1905 { "mov%LV", { RMeSI
, Iv64
}, 0 },
1906 { "mov%LV", { RMeDI
, Iv64
}, 0 },
1908 { REG_TABLE (REG_C0
) },
1909 { REG_TABLE (REG_C1
) },
1910 { X86_64_TABLE (X86_64_C2
) },
1911 { X86_64_TABLE (X86_64_C3
) },
1912 { X86_64_TABLE (X86_64_C4
) },
1913 { X86_64_TABLE (X86_64_C5
) },
1914 { REG_TABLE (REG_C6
) },
1915 { REG_TABLE (REG_C7
) },
1917 { "enterP", { Iw
, Ib
}, 0 },
1918 { "leaveP", { XX
}, 0 },
1919 { "{l|}ret{|f}%LP", { Iw
}, 0 },
1920 { "{l|}ret{|f}%LP", { XX
}, 0 },
1921 { "int3", { XX
}, 0 },
1922 { "int", { Ib
}, 0 },
1923 { X86_64_TABLE (X86_64_CE
) },
1924 { "iret%LP", { XX
}, 0 },
1926 { REG_TABLE (REG_D0
) },
1927 { REG_TABLE (REG_D1
) },
1928 { REG_TABLE (REG_D2
) },
1929 { REG_TABLE (REG_D3
) },
1930 { X86_64_TABLE (X86_64_D4
) },
1931 { X86_64_TABLE (X86_64_D5
) },
1933 { "xlat", { DSBX
}, 0 },
1944 { "loopneFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
1945 { "loopeFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
1946 { "loopFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
1947 { "jEcxzH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
1948 { "inB", { AL
, Ib
}, 0 },
1949 { "inG", { zAX
, Ib
}, 0 },
1950 { "outB", { Ib
, AL
}, 0 },
1951 { "outG", { Ib
, zAX
}, 0 },
1953 { X86_64_TABLE (X86_64_E8
) },
1954 { X86_64_TABLE (X86_64_E9
) },
1955 { X86_64_TABLE (X86_64_EA
) },
1956 { "jmp", { Jb
, BND
}, 0 },
1957 { "inB", { AL
, indirDX
}, 0 },
1958 { "inG", { zAX
, indirDX
}, 0 },
1959 { "outB", { indirDX
, AL
}, 0 },
1960 { "outG", { indirDX
, zAX
}, 0 },
1962 { Bad_Opcode
}, /* lock prefix */
1963 { "int1", { XX
}, 0 },
1964 { Bad_Opcode
}, /* repne */
1965 { Bad_Opcode
}, /* repz */
1966 { "hlt", { XX
}, 0 },
1967 { "cmc", { XX
}, 0 },
1968 { REG_TABLE (REG_F6
) },
1969 { REG_TABLE (REG_F7
) },
1971 { "clc", { XX
}, 0 },
1972 { "stc", { XX
}, 0 },
1973 { "cli", { XX
}, 0 },
1974 { "sti", { XX
}, 0 },
1975 { "cld", { XX
}, 0 },
1976 { "std", { XX
}, 0 },
1977 { REG_TABLE (REG_FE
) },
1978 { REG_TABLE (REG_FF
) },
1981 static const struct dis386 dis386_twobyte
[] = {
1983 { REG_TABLE (REG_0F00
) },
1984 { REG_TABLE (REG_0F01
) },
1985 { "larS", { Gv
, Ew
}, 0 },
1986 { "lslS", { Gv
, Ew
}, 0 },
1988 { "syscall", { XX
}, 0 },
1989 { "clts", { XX
}, 0 },
1990 { "sysret%LQ", { XX
}, 0 },
1992 { "invd", { XX
}, 0 },
1993 { PREFIX_TABLE (PREFIX_0F09
) },
1995 { "ud2", { XX
}, 0 },
1997 { REG_TABLE (REG_0F0D
) },
1998 { "femms", { XX
}, 0 },
1999 { "", { MX
, EM
, OPSUF
}, 0 }, /* See OP_3DNowSuffix. */
2001 { PREFIX_TABLE (PREFIX_0F10
) },
2002 { PREFIX_TABLE (PREFIX_0F11
) },
2003 { PREFIX_TABLE (PREFIX_0F12
) },
2004 { MOD_TABLE (MOD_0F13
) },
2005 { "unpcklpX", { XM
, EXx
}, PREFIX_OPCODE
},
2006 { "unpckhpX", { XM
, EXx
}, PREFIX_OPCODE
},
2007 { PREFIX_TABLE (PREFIX_0F16
) },
2008 { MOD_TABLE (MOD_0F17
) },
2010 { REG_TABLE (REG_0F18
) },
2011 { "nopQ", { Ev
}, 0 },
2012 { PREFIX_TABLE (PREFIX_0F1A
) },
2013 { PREFIX_TABLE (PREFIX_0F1B
) },
2014 { PREFIX_TABLE (PREFIX_0F1C
) },
2015 { "nopQ", { Ev
}, 0 },
2016 { PREFIX_TABLE (PREFIX_0F1E
) },
2017 { "nopQ", { Ev
}, 0 },
2019 { "movZ", { Em
, Cm
}, 0 },
2020 { "movZ", { Em
, Dm
}, 0 },
2021 { "movZ", { Cm
, Em
}, 0 },
2022 { "movZ", { Dm
, Em
}, 0 },
2023 { X86_64_TABLE (X86_64_0F24
) },
2025 { X86_64_TABLE (X86_64_0F26
) },
2028 { "movapX", { XM
, EXx
}, PREFIX_OPCODE
},
2029 { "movapX", { EXxS
, XM
}, PREFIX_OPCODE
},
2030 { PREFIX_TABLE (PREFIX_0F2A
) },
2031 { PREFIX_TABLE (PREFIX_0F2B
) },
2032 { PREFIX_TABLE (PREFIX_0F2C
) },
2033 { PREFIX_TABLE (PREFIX_0F2D
) },
2034 { PREFIX_TABLE (PREFIX_0F2E
) },
2035 { PREFIX_TABLE (PREFIX_0F2F
) },
2037 { "wrmsr", { XX
}, 0 },
2038 { "rdtsc", { XX
}, 0 },
2039 { "rdmsr", { XX
}, 0 },
2040 { "rdpmc", { XX
}, 0 },
2041 { "sysenter", { SEP
}, 0 },
2042 { "sysexit%LQ", { SEP
}, 0 },
2044 { "getsec", { XX
}, 0 },
2046 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38
, PREFIX_OPCODE
) },
2048 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A
, PREFIX_OPCODE
) },
2055 { "cmovoS", { Gv
, Ev
}, 0 },
2056 { "cmovnoS", { Gv
, Ev
}, 0 },
2057 { "cmovbS", { Gv
, Ev
}, 0 },
2058 { "cmovaeS", { Gv
, Ev
}, 0 },
2059 { "cmoveS", { Gv
, Ev
}, 0 },
2060 { "cmovneS", { Gv
, Ev
}, 0 },
2061 { "cmovbeS", { Gv
, Ev
}, 0 },
2062 { "cmovaS", { Gv
, Ev
}, 0 },
2064 { "cmovsS", { Gv
, Ev
}, 0 },
2065 { "cmovnsS", { Gv
, Ev
}, 0 },
2066 { "cmovpS", { Gv
, Ev
}, 0 },
2067 { "cmovnpS", { Gv
, Ev
}, 0 },
2068 { "cmovlS", { Gv
, Ev
}, 0 },
2069 { "cmovgeS", { Gv
, Ev
}, 0 },
2070 { "cmovleS", { Gv
, Ev
}, 0 },
2071 { "cmovgS", { Gv
, Ev
}, 0 },
2073 { MOD_TABLE (MOD_0F50
) },
2074 { PREFIX_TABLE (PREFIX_0F51
) },
2075 { PREFIX_TABLE (PREFIX_0F52
) },
2076 { PREFIX_TABLE (PREFIX_0F53
) },
2077 { "andpX", { XM
, EXx
}, PREFIX_OPCODE
},
2078 { "andnpX", { XM
, EXx
}, PREFIX_OPCODE
},
2079 { "orpX", { XM
, EXx
}, PREFIX_OPCODE
},
2080 { "xorpX", { XM
, EXx
}, PREFIX_OPCODE
},
2082 { PREFIX_TABLE (PREFIX_0F58
) },
2083 { PREFIX_TABLE (PREFIX_0F59
) },
2084 { PREFIX_TABLE (PREFIX_0F5A
) },
2085 { PREFIX_TABLE (PREFIX_0F5B
) },
2086 { PREFIX_TABLE (PREFIX_0F5C
) },
2087 { PREFIX_TABLE (PREFIX_0F5D
) },
2088 { PREFIX_TABLE (PREFIX_0F5E
) },
2089 { PREFIX_TABLE (PREFIX_0F5F
) },
2091 { PREFIX_TABLE (PREFIX_0F60
) },
2092 { PREFIX_TABLE (PREFIX_0F61
) },
2093 { PREFIX_TABLE (PREFIX_0F62
) },
2094 { "packsswb", { MX
, EM
}, PREFIX_OPCODE
},
2095 { "pcmpgtb", { MX
, EM
}, PREFIX_OPCODE
},
2096 { "pcmpgtw", { MX
, EM
}, PREFIX_OPCODE
},
2097 { "pcmpgtd", { MX
, EM
}, PREFIX_OPCODE
},
2098 { "packuswb", { MX
, EM
}, PREFIX_OPCODE
},
2100 { "punpckhbw", { MX
, EM
}, PREFIX_OPCODE
},
2101 { "punpckhwd", { MX
, EM
}, PREFIX_OPCODE
},
2102 { "punpckhdq", { MX
, EM
}, PREFIX_OPCODE
},
2103 { "packssdw", { MX
, EM
}, PREFIX_OPCODE
},
2104 { "punpcklqdq", { XM
, EXx
}, PREFIX_DATA
},
2105 { "punpckhqdq", { XM
, EXx
}, PREFIX_DATA
},
2106 { "movK", { MX
, Edq
}, PREFIX_OPCODE
},
2107 { PREFIX_TABLE (PREFIX_0F6F
) },
2109 { PREFIX_TABLE (PREFIX_0F70
) },
2110 { MOD_TABLE (MOD_0F71
) },
2111 { MOD_TABLE (MOD_0F72
) },
2112 { MOD_TABLE (MOD_0F73
) },
2113 { "pcmpeqb", { MX
, EM
}, PREFIX_OPCODE
},
2114 { "pcmpeqw", { MX
, EM
}, PREFIX_OPCODE
},
2115 { "pcmpeqd", { MX
, EM
}, PREFIX_OPCODE
},
2116 { "emms", { XX
}, PREFIX_OPCODE
},
2118 { PREFIX_TABLE (PREFIX_0F78
) },
2119 { PREFIX_TABLE (PREFIX_0F79
) },
2122 { PREFIX_TABLE (PREFIX_0F7C
) },
2123 { PREFIX_TABLE (PREFIX_0F7D
) },
2124 { PREFIX_TABLE (PREFIX_0F7E
) },
2125 { PREFIX_TABLE (PREFIX_0F7F
) },
2127 { "joH", { Jv
, BND
, cond_jump_flag
}, 0 },
2128 { "jnoH", { Jv
, BND
, cond_jump_flag
}, 0 },
2129 { "jbH", { Jv
, BND
, cond_jump_flag
}, 0 },
2130 { "jaeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2131 { "jeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2132 { "jneH", { Jv
, BND
, cond_jump_flag
}, 0 },
2133 { "jbeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2134 { "jaH", { Jv
, BND
, cond_jump_flag
}, 0 },
2136 { "jsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2137 { "jnsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2138 { "jpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2139 { "jnpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2140 { "jlH", { Jv
, BND
, cond_jump_flag
}, 0 },
2141 { "jgeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2142 { "jleH", { Jv
, BND
, cond_jump_flag
}, 0 },
2143 { "jgH", { Jv
, BND
, cond_jump_flag
}, 0 },
2145 { "seto", { Eb
}, 0 },
2146 { "setno", { Eb
}, 0 },
2147 { "setb", { Eb
}, 0 },
2148 { "setae", { Eb
}, 0 },
2149 { "sete", { Eb
}, 0 },
2150 { "setne", { Eb
}, 0 },
2151 { "setbe", { Eb
}, 0 },
2152 { "seta", { Eb
}, 0 },
2154 { "sets", { Eb
}, 0 },
2155 { "setns", { Eb
}, 0 },
2156 { "setp", { Eb
}, 0 },
2157 { "setnp", { Eb
}, 0 },
2158 { "setl", { Eb
}, 0 },
2159 { "setge", { Eb
}, 0 },
2160 { "setle", { Eb
}, 0 },
2161 { "setg", { Eb
}, 0 },
2163 { "pushP", { fs
}, 0 },
2164 { "popP", { fs
}, 0 },
2165 { "cpuid", { XX
}, 0 },
2166 { "btS", { Ev
, Gv
}, 0 },
2167 { "shldS", { Ev
, Gv
, Ib
}, 0 },
2168 { "shldS", { Ev
, Gv
, CL
}, 0 },
2169 { REG_TABLE (REG_0FA6
) },
2170 { REG_TABLE (REG_0FA7
) },
2172 { "pushP", { gs
}, 0 },
2173 { "popP", { gs
}, 0 },
2174 { "rsm", { XX
}, 0 },
2175 { "btsS", { Evh1
, Gv
}, 0 },
2176 { "shrdS", { Ev
, Gv
, Ib
}, 0 },
2177 { "shrdS", { Ev
, Gv
, CL
}, 0 },
2178 { REG_TABLE (REG_0FAE
) },
2179 { "imulS", { Gv
, Ev
}, 0 },
2181 { "cmpxchgB", { Ebh1
, Gb
}, 0 },
2182 { "cmpxchgS", { Evh1
, Gv
}, 0 },
2183 { MOD_TABLE (MOD_0FB2
) },
2184 { "btrS", { Evh1
, Gv
}, 0 },
2185 { MOD_TABLE (MOD_0FB4
) },
2186 { MOD_TABLE (MOD_0FB5
) },
2187 { "movz{bR|x}", { Gv
, Eb
}, 0 },
2188 { "movz{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movzww ! */
2190 { PREFIX_TABLE (PREFIX_0FB8
) },
2191 { "ud1S", { Gv
, Ev
}, 0 },
2192 { REG_TABLE (REG_0FBA
) },
2193 { "btcS", { Evh1
, Gv
}, 0 },
2194 { PREFIX_TABLE (PREFIX_0FBC
) },
2195 { PREFIX_TABLE (PREFIX_0FBD
) },
2196 { "movs{bR|x}", { Gv
, Eb
}, 0 },
2197 { "movs{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movsww ! */
2199 { "xaddB", { Ebh1
, Gb
}, 0 },
2200 { "xaddS", { Evh1
, Gv
}, 0 },
2201 { PREFIX_TABLE (PREFIX_0FC2
) },
2202 { MOD_TABLE (MOD_0FC3
) },
2203 { "pinsrw", { MX
, Edqw
, Ib
}, PREFIX_OPCODE
},
2204 { "pextrw", { Gdq
, MS
, Ib
}, PREFIX_OPCODE
},
2205 { "shufpX", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
2206 { REG_TABLE (REG_0FC7
) },
2208 { "bswap", { RMeAX
}, 0 },
2209 { "bswap", { RMeCX
}, 0 },
2210 { "bswap", { RMeDX
}, 0 },
2211 { "bswap", { RMeBX
}, 0 },
2212 { "bswap", { RMeSP
}, 0 },
2213 { "bswap", { RMeBP
}, 0 },
2214 { "bswap", { RMeSI
}, 0 },
2215 { "bswap", { RMeDI
}, 0 },
2217 { PREFIX_TABLE (PREFIX_0FD0
) },
2218 { "psrlw", { MX
, EM
}, PREFIX_OPCODE
},
2219 { "psrld", { MX
, EM
}, PREFIX_OPCODE
},
2220 { "psrlq", { MX
, EM
}, PREFIX_OPCODE
},
2221 { "paddq", { MX
, EM
}, PREFIX_OPCODE
},
2222 { "pmullw", { MX
, EM
}, PREFIX_OPCODE
},
2223 { PREFIX_TABLE (PREFIX_0FD6
) },
2224 { MOD_TABLE (MOD_0FD7
) },
2226 { "psubusb", { MX
, EM
}, PREFIX_OPCODE
},
2227 { "psubusw", { MX
, EM
}, PREFIX_OPCODE
},
2228 { "pminub", { MX
, EM
}, PREFIX_OPCODE
},
2229 { "pand", { MX
, EM
}, PREFIX_OPCODE
},
2230 { "paddusb", { MX
, EM
}, PREFIX_OPCODE
},
2231 { "paddusw", { MX
, EM
}, PREFIX_OPCODE
},
2232 { "pmaxub", { MX
, EM
}, PREFIX_OPCODE
},
2233 { "pandn", { MX
, EM
}, PREFIX_OPCODE
},
2235 { "pavgb", { MX
, EM
}, PREFIX_OPCODE
},
2236 { "psraw", { MX
, EM
}, PREFIX_OPCODE
},
2237 { "psrad", { MX
, EM
}, PREFIX_OPCODE
},
2238 { "pavgw", { MX
, EM
}, PREFIX_OPCODE
},
2239 { "pmulhuw", { MX
, EM
}, PREFIX_OPCODE
},
2240 { "pmulhw", { MX
, EM
}, PREFIX_OPCODE
},
2241 { PREFIX_TABLE (PREFIX_0FE6
) },
2242 { PREFIX_TABLE (PREFIX_0FE7
) },
2244 { "psubsb", { MX
, EM
}, PREFIX_OPCODE
},
2245 { "psubsw", { MX
, EM
}, PREFIX_OPCODE
},
2246 { "pminsw", { MX
, EM
}, PREFIX_OPCODE
},
2247 { "por", { MX
, EM
}, PREFIX_OPCODE
},
2248 { "paddsb", { MX
, EM
}, PREFIX_OPCODE
},
2249 { "paddsw", { MX
, EM
}, PREFIX_OPCODE
},
2250 { "pmaxsw", { MX
, EM
}, PREFIX_OPCODE
},
2251 { "pxor", { MX
, EM
}, PREFIX_OPCODE
},
2253 { PREFIX_TABLE (PREFIX_0FF0
) },
2254 { "psllw", { MX
, EM
}, PREFIX_OPCODE
},
2255 { "pslld", { MX
, EM
}, PREFIX_OPCODE
},
2256 { "psllq", { MX
, EM
}, PREFIX_OPCODE
},
2257 { "pmuludq", { MX
, EM
}, PREFIX_OPCODE
},
2258 { "pmaddwd", { MX
, EM
}, PREFIX_OPCODE
},
2259 { "psadbw", { MX
, EM
}, PREFIX_OPCODE
},
2260 { PREFIX_TABLE (PREFIX_0FF7
) },
2262 { "psubb", { MX
, EM
}, PREFIX_OPCODE
},
2263 { "psubw", { MX
, EM
}, PREFIX_OPCODE
},
2264 { "psubd", { MX
, EM
}, PREFIX_OPCODE
},
2265 { "psubq", { MX
, EM
}, PREFIX_OPCODE
},
2266 { "paddb", { MX
, EM
}, PREFIX_OPCODE
},
2267 { "paddw", { MX
, EM
}, PREFIX_OPCODE
},
2268 { "paddd", { MX
, EM
}, PREFIX_OPCODE
},
2269 { "ud0S", { Gv
, Ev
}, 0 },
2272 static const unsigned char onebyte_has_modrm
[256] = {
2273 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2274 /* ------------------------------- */
2275 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2276 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2277 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2278 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2279 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2280 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2281 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2282 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2283 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2284 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2285 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2286 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2287 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2288 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2289 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2290 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2291 /* ------------------------------- */
2292 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2295 static const unsigned char twobyte_has_modrm
[256] = {
2296 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2297 /* ------------------------------- */
2298 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2299 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2300 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2301 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2302 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2303 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2304 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2305 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2306 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2307 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2308 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2309 /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2310 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2311 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2312 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2313 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */
2314 /* ------------------------------- */
2315 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2318 static char obuf
[100];
2320 static char *mnemonicendp
;
2321 static char scratchbuf
[100];
2322 static unsigned char *start_codep
;
2323 static unsigned char *insn_codep
;
2324 static unsigned char *codep
;
2325 static unsigned char *end_codep
;
2326 static int last_lock_prefix
;
2327 static int last_repz_prefix
;
2328 static int last_repnz_prefix
;
2329 static int last_data_prefix
;
2330 static int last_addr_prefix
;
2331 static int last_rex_prefix
;
2332 static int last_seg_prefix
;
2333 static int fwait_prefix
;
2334 /* The active segment register prefix. */
2335 static int active_seg_prefix
;
2336 #define MAX_CODE_LENGTH 15
2337 /* We can up to 14 prefixes since the maximum instruction length is
2339 static int all_prefixes
[MAX_CODE_LENGTH
- 1];
2340 static disassemble_info
*the_info
;
2348 static unsigned char need_modrm
;
2358 int register_specifier
;
2365 int mask_register_specifier
;
2371 static unsigned char need_vex
;
2379 /* If we are accessing mod/rm/reg without need_modrm set, then the
2380 values are stale. Hitting this abort likely indicates that you
2381 need to update onebyte_has_modrm or twobyte_has_modrm. */
2382 #define MODRM_CHECK if (!need_modrm) abort ()
2384 static const char **names64
;
2385 static const char **names32
;
2386 static const char **names16
;
2387 static const char **names8
;
2388 static const char **names8rex
;
2389 static const char **names_seg
;
2390 static const char *index64
;
2391 static const char *index32
;
2392 static const char **index16
;
2393 static const char **names_bnd
;
2395 static const char *intel_names64
[] = {
2396 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2397 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2399 static const char *intel_names32
[] = {
2400 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2401 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2403 static const char *intel_names16
[] = {
2404 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2405 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2407 static const char *intel_names8
[] = {
2408 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2410 static const char *intel_names8rex
[] = {
2411 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2412 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2414 static const char *intel_names_seg
[] = {
2415 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2417 static const char *intel_index64
= "riz";
2418 static const char *intel_index32
= "eiz";
2419 static const char *intel_index16
[] = {
2420 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2423 static const char *att_names64
[] = {
2424 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2425 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2427 static const char *att_names32
[] = {
2428 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2429 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2431 static const char *att_names16
[] = {
2432 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2433 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2435 static const char *att_names8
[] = {
2436 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2438 static const char *att_names8rex
[] = {
2439 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2440 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2442 static const char *att_names_seg
[] = {
2443 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2445 static const char *att_index64
= "%riz";
2446 static const char *att_index32
= "%eiz";
2447 static const char *att_index16
[] = {
2448 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2451 static const char **names_mm
;
2452 static const char *intel_names_mm
[] = {
2453 "mm0", "mm1", "mm2", "mm3",
2454 "mm4", "mm5", "mm6", "mm7"
2456 static const char *att_names_mm
[] = {
2457 "%mm0", "%mm1", "%mm2", "%mm3",
2458 "%mm4", "%mm5", "%mm6", "%mm7"
2461 static const char *intel_names_bnd
[] = {
2462 "bnd0", "bnd1", "bnd2", "bnd3"
2465 static const char *att_names_bnd
[] = {
2466 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
2469 static const char **names_xmm
;
2470 static const char *intel_names_xmm
[] = {
2471 "xmm0", "xmm1", "xmm2", "xmm3",
2472 "xmm4", "xmm5", "xmm6", "xmm7",
2473 "xmm8", "xmm9", "xmm10", "xmm11",
2474 "xmm12", "xmm13", "xmm14", "xmm15",
2475 "xmm16", "xmm17", "xmm18", "xmm19",
2476 "xmm20", "xmm21", "xmm22", "xmm23",
2477 "xmm24", "xmm25", "xmm26", "xmm27",
2478 "xmm28", "xmm29", "xmm30", "xmm31"
2480 static const char *att_names_xmm
[] = {
2481 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2482 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2483 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2484 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
2485 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
2486 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
2487 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
2488 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
2491 static const char **names_ymm
;
2492 static const char *intel_names_ymm
[] = {
2493 "ymm0", "ymm1", "ymm2", "ymm3",
2494 "ymm4", "ymm5", "ymm6", "ymm7",
2495 "ymm8", "ymm9", "ymm10", "ymm11",
2496 "ymm12", "ymm13", "ymm14", "ymm15",
2497 "ymm16", "ymm17", "ymm18", "ymm19",
2498 "ymm20", "ymm21", "ymm22", "ymm23",
2499 "ymm24", "ymm25", "ymm26", "ymm27",
2500 "ymm28", "ymm29", "ymm30", "ymm31"
2502 static const char *att_names_ymm
[] = {
2503 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2504 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2505 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2506 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
2507 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
2508 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
2509 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
2510 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
2513 static const char **names_zmm
;
2514 static const char *intel_names_zmm
[] = {
2515 "zmm0", "zmm1", "zmm2", "zmm3",
2516 "zmm4", "zmm5", "zmm6", "zmm7",
2517 "zmm8", "zmm9", "zmm10", "zmm11",
2518 "zmm12", "zmm13", "zmm14", "zmm15",
2519 "zmm16", "zmm17", "zmm18", "zmm19",
2520 "zmm20", "zmm21", "zmm22", "zmm23",
2521 "zmm24", "zmm25", "zmm26", "zmm27",
2522 "zmm28", "zmm29", "zmm30", "zmm31"
2524 static const char *att_names_zmm
[] = {
2525 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
2526 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
2527 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
2528 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
2529 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
2530 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
2531 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
2532 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
2535 static const char **names_tmm
;
2536 static const char *intel_names_tmm
[] = {
2537 "tmm0", "tmm1", "tmm2", "tmm3",
2538 "tmm4", "tmm5", "tmm6", "tmm7"
2540 static const char *att_names_tmm
[] = {
2541 "%tmm0", "%tmm1", "%tmm2", "%tmm3",
2542 "%tmm4", "%tmm5", "%tmm6", "%tmm7"
2545 static const char **names_mask
;
2546 static const char *intel_names_mask
[] = {
2547 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
2549 static const char *att_names_mask
[] = {
2550 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
2553 static const char *names_rounding
[] =
2561 static const struct dis386 reg_table
[][8] = {
2564 { "addA", { Ebh1
, Ib
}, 0 },
2565 { "orA", { Ebh1
, Ib
}, 0 },
2566 { "adcA", { Ebh1
, Ib
}, 0 },
2567 { "sbbA", { Ebh1
, Ib
}, 0 },
2568 { "andA", { Ebh1
, Ib
}, 0 },
2569 { "subA", { Ebh1
, Ib
}, 0 },
2570 { "xorA", { Ebh1
, Ib
}, 0 },
2571 { "cmpA", { Eb
, Ib
}, 0 },
2575 { "addQ", { Evh1
, Iv
}, 0 },
2576 { "orQ", { Evh1
, Iv
}, 0 },
2577 { "adcQ", { Evh1
, Iv
}, 0 },
2578 { "sbbQ", { Evh1
, Iv
}, 0 },
2579 { "andQ", { Evh1
, Iv
}, 0 },
2580 { "subQ", { Evh1
, Iv
}, 0 },
2581 { "xorQ", { Evh1
, Iv
}, 0 },
2582 { "cmpQ", { Ev
, Iv
}, 0 },
2586 { "addQ", { Evh1
, sIb
}, 0 },
2587 { "orQ", { Evh1
, sIb
}, 0 },
2588 { "adcQ", { Evh1
, sIb
}, 0 },
2589 { "sbbQ", { Evh1
, sIb
}, 0 },
2590 { "andQ", { Evh1
, sIb
}, 0 },
2591 { "subQ", { Evh1
, sIb
}, 0 },
2592 { "xorQ", { Evh1
, sIb
}, 0 },
2593 { "cmpQ", { Ev
, sIb
}, 0 },
2597 { "pop{P|}", { stackEv
}, 0 },
2598 { XOP_8F_TABLE (XOP_09
) },
2602 { XOP_8F_TABLE (XOP_09
) },
2606 { "rolA", { Eb
, Ib
}, 0 },
2607 { "rorA", { Eb
, Ib
}, 0 },
2608 { "rclA", { Eb
, Ib
}, 0 },
2609 { "rcrA", { Eb
, Ib
}, 0 },
2610 { "shlA", { Eb
, Ib
}, 0 },
2611 { "shrA", { Eb
, Ib
}, 0 },
2612 { "shlA", { Eb
, Ib
}, 0 },
2613 { "sarA", { Eb
, Ib
}, 0 },
2617 { "rolQ", { Ev
, Ib
}, 0 },
2618 { "rorQ", { Ev
, Ib
}, 0 },
2619 { "rclQ", { Ev
, Ib
}, 0 },
2620 { "rcrQ", { Ev
, Ib
}, 0 },
2621 { "shlQ", { Ev
, Ib
}, 0 },
2622 { "shrQ", { Ev
, Ib
}, 0 },
2623 { "shlQ", { Ev
, Ib
}, 0 },
2624 { "sarQ", { Ev
, Ib
}, 0 },
2628 { "movA", { Ebh3
, Ib
}, 0 },
2635 { MOD_TABLE (MOD_C6_REG_7
) },
2639 { "movQ", { Evh3
, Iv
}, 0 },
2646 { MOD_TABLE (MOD_C7_REG_7
) },
2650 { "rolA", { Eb
, I1
}, 0 },
2651 { "rorA", { Eb
, I1
}, 0 },
2652 { "rclA", { Eb
, I1
}, 0 },
2653 { "rcrA", { Eb
, I1
}, 0 },
2654 { "shlA", { Eb
, I1
}, 0 },
2655 { "shrA", { Eb
, I1
}, 0 },
2656 { "shlA", { Eb
, I1
}, 0 },
2657 { "sarA", { Eb
, I1
}, 0 },
2661 { "rolQ", { Ev
, I1
}, 0 },
2662 { "rorQ", { Ev
, I1
}, 0 },
2663 { "rclQ", { Ev
, I1
}, 0 },
2664 { "rcrQ", { Ev
, I1
}, 0 },
2665 { "shlQ", { Ev
, I1
}, 0 },
2666 { "shrQ", { Ev
, I1
}, 0 },
2667 { "shlQ", { Ev
, I1
}, 0 },
2668 { "sarQ", { Ev
, I1
}, 0 },
2672 { "rolA", { Eb
, CL
}, 0 },
2673 { "rorA", { Eb
, CL
}, 0 },
2674 { "rclA", { Eb
, CL
}, 0 },
2675 { "rcrA", { Eb
, CL
}, 0 },
2676 { "shlA", { Eb
, CL
}, 0 },
2677 { "shrA", { Eb
, CL
}, 0 },
2678 { "shlA", { Eb
, CL
}, 0 },
2679 { "sarA", { Eb
, CL
}, 0 },
2683 { "rolQ", { Ev
, CL
}, 0 },
2684 { "rorQ", { Ev
, CL
}, 0 },
2685 { "rclQ", { Ev
, CL
}, 0 },
2686 { "rcrQ", { Ev
, CL
}, 0 },
2687 { "shlQ", { Ev
, CL
}, 0 },
2688 { "shrQ", { Ev
, CL
}, 0 },
2689 { "shlQ", { Ev
, CL
}, 0 },
2690 { "sarQ", { Ev
, CL
}, 0 },
2694 { "testA", { Eb
, Ib
}, 0 },
2695 { "testA", { Eb
, Ib
}, 0 },
2696 { "notA", { Ebh1
}, 0 },
2697 { "negA", { Ebh1
}, 0 },
2698 { "mulA", { Eb
}, 0 }, /* Don't print the implicit %al register, */
2699 { "imulA", { Eb
}, 0 }, /* to distinguish these opcodes from other */
2700 { "divA", { Eb
}, 0 }, /* mul/imul opcodes. Do the same for div */
2701 { "idivA", { Eb
}, 0 }, /* and idiv for consistency. */
2705 { "testQ", { Ev
, Iv
}, 0 },
2706 { "testQ", { Ev
, Iv
}, 0 },
2707 { "notQ", { Evh1
}, 0 },
2708 { "negQ", { Evh1
}, 0 },
2709 { "mulQ", { Ev
}, 0 }, /* Don't print the implicit register. */
2710 { "imulQ", { Ev
}, 0 },
2711 { "divQ", { Ev
}, 0 },
2712 { "idivQ", { Ev
}, 0 },
2716 { "incA", { Ebh1
}, 0 },
2717 { "decA", { Ebh1
}, 0 },
2721 { "incQ", { Evh1
}, 0 },
2722 { "decQ", { Evh1
}, 0 },
2723 { "call{@|}", { NOTRACK
, indirEv
, BND
}, 0 },
2724 { MOD_TABLE (MOD_FF_REG_3
) },
2725 { "jmp{@|}", { NOTRACK
, indirEv
, BND
}, 0 },
2726 { MOD_TABLE (MOD_FF_REG_5
) },
2727 { "push{P|}", { stackEv
}, 0 },
2732 { "sldtD", { Sv
}, 0 },
2733 { "strD", { Sv
}, 0 },
2734 { "lldt", { Ew
}, 0 },
2735 { "ltr", { Ew
}, 0 },
2736 { "verr", { Ew
}, 0 },
2737 { "verw", { Ew
}, 0 },
2743 { MOD_TABLE (MOD_0F01_REG_0
) },
2744 { MOD_TABLE (MOD_0F01_REG_1
) },
2745 { MOD_TABLE (MOD_0F01_REG_2
) },
2746 { MOD_TABLE (MOD_0F01_REG_3
) },
2747 { "smswD", { Sv
}, 0 },
2748 { MOD_TABLE (MOD_0F01_REG_5
) },
2749 { "lmsw", { Ew
}, 0 },
2750 { MOD_TABLE (MOD_0F01_REG_7
) },
2754 { "prefetch", { Mb
}, 0 },
2755 { "prefetchw", { Mb
}, 0 },
2756 { "prefetchwt1", { Mb
}, 0 },
2757 { "prefetch", { Mb
}, 0 },
2758 { "prefetch", { Mb
}, 0 },
2759 { "prefetch", { Mb
}, 0 },
2760 { "prefetch", { Mb
}, 0 },
2761 { "prefetch", { Mb
}, 0 },
2765 { MOD_TABLE (MOD_0F18_REG_0
) },
2766 { MOD_TABLE (MOD_0F18_REG_1
) },
2767 { MOD_TABLE (MOD_0F18_REG_2
) },
2768 { MOD_TABLE (MOD_0F18_REG_3
) },
2769 { "nopQ", { Ev
}, 0 },
2770 { "nopQ", { Ev
}, 0 },
2771 { "nopQ", { Ev
}, 0 },
2772 { "nopQ", { Ev
}, 0 },
2774 /* REG_0F1C_P_0_MOD_0 */
2776 { "cldemote", { Mb
}, 0 },
2777 { "nopQ", { Ev
}, 0 },
2778 { "nopQ", { Ev
}, 0 },
2779 { "nopQ", { Ev
}, 0 },
2780 { "nopQ", { Ev
}, 0 },
2781 { "nopQ", { Ev
}, 0 },
2782 { "nopQ", { Ev
}, 0 },
2783 { "nopQ", { Ev
}, 0 },
2785 /* REG_0F1E_P_1_MOD_3 */
2787 { "nopQ", { Ev
}, PREFIX_IGNORED
},
2788 { "rdsspK", { Edq
}, 0 },
2789 { "nopQ", { Ev
}, PREFIX_IGNORED
},
2790 { "nopQ", { Ev
}, PREFIX_IGNORED
},
2791 { "nopQ", { Ev
}, PREFIX_IGNORED
},
2792 { "nopQ", { Ev
}, PREFIX_IGNORED
},
2793 { "nopQ", { Ev
}, PREFIX_IGNORED
},
2794 { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7
) },
2796 /* REG_0F38D8_PREFIX_1 */
2798 { "aesencwide128kl", { M
}, 0 },
2799 { "aesdecwide128kl", { M
}, 0 },
2800 { "aesencwide256kl", { M
}, 0 },
2801 { "aesdecwide256kl", { M
}, 0 },
2803 /* REG_0F3A0F_PREFIX_1_MOD_3 */
2805 { RM_TABLE (RM_0F3A0F_P_1_MOD_3_REG_0
) },
2807 /* REG_0F71_MOD_0 */
2811 { "psrlw", { MS
, Ib
}, PREFIX_OPCODE
},
2813 { "psraw", { MS
, Ib
}, PREFIX_OPCODE
},
2815 { "psllw", { MS
, Ib
}, PREFIX_OPCODE
},
2817 /* REG_0F72_MOD_0 */
2821 { "psrld", { MS
, Ib
}, PREFIX_OPCODE
},
2823 { "psrad", { MS
, Ib
}, PREFIX_OPCODE
},
2825 { "pslld", { MS
, Ib
}, PREFIX_OPCODE
},
2827 /* REG_0F73_MOD_0 */
2831 { "psrlq", { MS
, Ib
}, PREFIX_OPCODE
},
2832 { "psrldq", { XS
, Ib
}, PREFIX_DATA
},
2835 { "psllq", { MS
, Ib
}, PREFIX_OPCODE
},
2836 { "pslldq", { XS
, Ib
}, PREFIX_DATA
},
2840 { "montmul", { { OP_0f07
, 0 } }, 0 },
2841 { "xsha1", { { OP_0f07
, 0 } }, 0 },
2842 { "xsha256", { { OP_0f07
, 0 } }, 0 },
2846 { "xstore-rng", { { OP_0f07
, 0 } }, 0 },
2847 { "xcrypt-ecb", { { OP_0f07
, 0 } }, 0 },
2848 { "xcrypt-cbc", { { OP_0f07
, 0 } }, 0 },
2849 { "xcrypt-ctr", { { OP_0f07
, 0 } }, 0 },
2850 { "xcrypt-cfb", { { OP_0f07
, 0 } }, 0 },
2851 { "xcrypt-ofb", { { OP_0f07
, 0 } }, 0 },
2855 { MOD_TABLE (MOD_0FAE_REG_0
) },
2856 { MOD_TABLE (MOD_0FAE_REG_1
) },
2857 { MOD_TABLE (MOD_0FAE_REG_2
) },
2858 { MOD_TABLE (MOD_0FAE_REG_3
) },
2859 { MOD_TABLE (MOD_0FAE_REG_4
) },
2860 { MOD_TABLE (MOD_0FAE_REG_5
) },
2861 { MOD_TABLE (MOD_0FAE_REG_6
) },
2862 { MOD_TABLE (MOD_0FAE_REG_7
) },
2870 { "btQ", { Ev
, Ib
}, 0 },
2871 { "btsQ", { Evh1
, Ib
}, 0 },
2872 { "btrQ", { Evh1
, Ib
}, 0 },
2873 { "btcQ", { Evh1
, Ib
}, 0 },
2878 { "cmpxchg8b", { { CMPXCHG8B_Fixup
, q_mode
} }, 0 },
2880 { MOD_TABLE (MOD_0FC7_REG_3
) },
2881 { MOD_TABLE (MOD_0FC7_REG_4
) },
2882 { MOD_TABLE (MOD_0FC7_REG_5
) },
2883 { MOD_TABLE (MOD_0FC7_REG_6
) },
2884 { MOD_TABLE (MOD_0FC7_REG_7
) },
2886 /* REG_VEX_0F71_M_0 */
2890 { "vpsrlw", { Vex
, XS
, Ib
}, PREFIX_DATA
},
2892 { "vpsraw", { Vex
, XS
, Ib
}, PREFIX_DATA
},
2894 { "vpsllw", { Vex
, XS
, Ib
}, PREFIX_DATA
},
2896 /* REG_VEX_0F72_M_0 */
2900 { "vpsrld", { Vex
, XS
, Ib
}, PREFIX_DATA
},
2902 { "vpsrad", { Vex
, XS
, Ib
}, PREFIX_DATA
},
2904 { "vpslld", { Vex
, XS
, Ib
}, PREFIX_DATA
},
2906 /* REG_VEX_0F73_M_0 */
2910 { "vpsrlq", { Vex
, XS
, Ib
}, PREFIX_DATA
},
2911 { "vpsrldq", { Vex
, XS
, Ib
}, PREFIX_DATA
},
2914 { "vpsllq", { Vex
, XS
, Ib
}, PREFIX_DATA
},
2915 { "vpslldq", { Vex
, XS
, Ib
}, PREFIX_DATA
},
2921 { MOD_TABLE (MOD_VEX_0FAE_REG_2
) },
2922 { MOD_TABLE (MOD_VEX_0FAE_REG_3
) },
2924 /* REG_VEX_0F3849_X86_64_P_0_W_0_M_1 */
2926 { RM_TABLE (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0
) },
2928 /* REG_VEX_0F38F3_L_0 */
2931 { "blsrS", { VexGdq
, Edq
}, PREFIX_OPCODE
},
2932 { "blsmskS", { VexGdq
, Edq
}, PREFIX_OPCODE
},
2933 { "blsiS", { VexGdq
, Edq
}, PREFIX_OPCODE
},
2935 /* REG_XOP_09_01_L_0 */
2938 { "blcfill", { VexGdq
, Edq
}, 0 },
2939 { "blsfill", { VexGdq
, Edq
}, 0 },
2940 { "blcs", { VexGdq
, Edq
}, 0 },
2941 { "tzmsk", { VexGdq
, Edq
}, 0 },
2942 { "blcic", { VexGdq
, Edq
}, 0 },
2943 { "blsic", { VexGdq
, Edq
}, 0 },
2944 { "t1mskc", { VexGdq
, Edq
}, 0 },
2946 /* REG_XOP_09_02_L_0 */
2949 { "blcmsk", { VexGdq
, Edq
}, 0 },
2954 { "blci", { VexGdq
, Edq
}, 0 },
2956 /* REG_XOP_09_12_M_1_L_0 */
2958 { "llwpcb", { Edq
}, 0 },
2959 { "slwpcb", { Edq
}, 0 },
2961 /* REG_XOP_0A_12_L_0 */
2963 { "lwpins", { VexGdq
, Ed
, Id
}, 0 },
2964 { "lwpval", { VexGdq
, Ed
, Id
}, 0 },
2967 #include "i386-dis-evex-reg.h"
2970 static const struct dis386 prefix_table
[][4] = {
2973 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
2974 { "pause", { XX
}, 0 },
2975 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
2976 { NULL
, { { NULL
, 0 } }, PREFIX_IGNORED
}
2979 /* PREFIX_0F01_REG_1_RM_4 */
2983 { "tdcall", { Skip_MODRM
}, 0 },
2987 /* PREFIX_0F01_REG_1_RM_5 */
2991 { X86_64_TABLE (X86_64_0F01_REG_1_RM_5_PREFIX_2
) },
2995 /* PREFIX_0F01_REG_1_RM_6 */
2999 { X86_64_TABLE (X86_64_0F01_REG_1_RM_6_PREFIX_2
) },
3003 /* PREFIX_0F01_REG_1_RM_7 */
3005 { "encls", { Skip_MODRM
}, 0 },
3007 { X86_64_TABLE (X86_64_0F01_REG_1_RM_7_PREFIX_2
) },
3011 /* PREFIX_0F01_REG_3_RM_1 */
3013 { "vmmcall", { Skip_MODRM
}, 0 },
3014 { "vmgexit", { Skip_MODRM
}, 0 },
3016 { "vmgexit", { Skip_MODRM
}, 0 },
3019 /* PREFIX_0F01_REG_5_MOD_0 */
3022 { "rstorssp", { Mq
}, PREFIX_OPCODE
},
3025 /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3027 { "serialize", { Skip_MODRM
}, PREFIX_OPCODE
},
3028 { "setssbsy", { Skip_MODRM
}, PREFIX_OPCODE
},
3030 { "xsusldtrk", { Skip_MODRM
}, PREFIX_OPCODE
},
3033 /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
3038 { "xresldtrk", { Skip_MODRM
}, PREFIX_OPCODE
},
3041 /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3044 { "saveprevssp", { Skip_MODRM
}, PREFIX_OPCODE
},
3047 /* PREFIX_0F01_REG_5_MOD_3_RM_4 */
3050 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1
) },
3053 /* PREFIX_0F01_REG_5_MOD_3_RM_5 */
3056 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1
) },
3059 /* PREFIX_0F01_REG_5_MOD_3_RM_6 */
3061 { "rdpkru", { Skip_MODRM
}, 0 },
3062 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1
) },
3065 /* PREFIX_0F01_REG_5_MOD_3_RM_7 */
3067 { "wrpkru", { Skip_MODRM
}, 0 },
3068 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1
) },
3071 /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3073 { "monitorx", { { OP_Monitor
, 0 } }, 0 },
3074 { "mcommit", { Skip_MODRM
}, 0 },
3077 /* PREFIX_0F01_REG_7_MOD_3_RM_6 */
3079 { "invlpgb", { Skip_MODRM
}, 0 },
3080 { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1
) },
3082 { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3
) },
3085 /* PREFIX_0F01_REG_7_MOD_3_RM_7 */
3087 { "tlbsync", { Skip_MODRM
}, 0 },
3088 { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1
) },
3090 { "pvalidate", { Skip_MODRM
}, 0 },
3095 { "wbinvd", { XX
}, 0 },
3096 { "wbnoinvd", { XX
}, 0 },
3101 { "movups", { XM
, EXx
}, PREFIX_OPCODE
},
3102 { "movss", { XM
, EXd
}, PREFIX_OPCODE
},
3103 { "movupd", { XM
, EXx
}, PREFIX_OPCODE
},
3104 { "movsd", { XM
, EXq
}, PREFIX_OPCODE
},
3109 { "movups", { EXxS
, XM
}, PREFIX_OPCODE
},
3110 { "movss", { EXdS
, XM
}, PREFIX_OPCODE
},
3111 { "movupd", { EXxS
, XM
}, PREFIX_OPCODE
},
3112 { "movsd", { EXqS
, XM
}, PREFIX_OPCODE
},
3117 { MOD_TABLE (MOD_0F12_PREFIX_0
) },
3118 { "movsldup", { XM
, EXx
}, PREFIX_OPCODE
},
3119 { MOD_TABLE (MOD_0F12_PREFIX_2
) },
3120 { "movddup", { XM
, EXq
}, PREFIX_OPCODE
},
3125 { MOD_TABLE (MOD_0F16_PREFIX_0
) },
3126 { "movshdup", { XM
, EXx
}, PREFIX_OPCODE
},
3127 { MOD_TABLE (MOD_0F16_PREFIX_2
) },
3132 { MOD_TABLE (MOD_0F1A_PREFIX_0
) },
3133 { "bndcl", { Gbnd
, Ev_bnd
}, 0 },
3134 { "bndmov", { Gbnd
, Ebnd
}, 0 },
3135 { "bndcu", { Gbnd
, Ev_bnd
}, 0 },
3140 { MOD_TABLE (MOD_0F1B_PREFIX_0
) },
3141 { MOD_TABLE (MOD_0F1B_PREFIX_1
) },
3142 { "bndmov", { EbndS
, Gbnd
}, 0 },
3143 { "bndcn", { Gbnd
, Ev_bnd
}, 0 },
3148 { MOD_TABLE (MOD_0F1C_PREFIX_0
) },
3149 { "nopQ", { Ev
}, PREFIX_IGNORED
},
3150 { "nopQ", { Ev
}, 0 },
3151 { "nopQ", { Ev
}, PREFIX_IGNORED
},
3156 { "nopQ", { Ev
}, 0 },
3157 { MOD_TABLE (MOD_0F1E_PREFIX_1
) },
3158 { "nopQ", { Ev
}, 0 },
3159 { NULL
, { XX
}, PREFIX_IGNORED
},
3164 { "cvtpi2ps", { XM
, EMCq
}, PREFIX_OPCODE
},
3165 { "cvtsi2ss{%LQ|}", { XM
, Edq
}, PREFIX_OPCODE
},
3166 { "cvtpi2pd", { XM
, EMCq
}, PREFIX_OPCODE
},
3167 { "cvtsi2sd{%LQ|}", { XM
, Edq
}, 0 },
3172 { MOD_TABLE (MOD_0F2B_PREFIX_0
) },
3173 { MOD_TABLE (MOD_0F2B_PREFIX_1
) },
3174 { MOD_TABLE (MOD_0F2B_PREFIX_2
) },
3175 { MOD_TABLE (MOD_0F2B_PREFIX_3
) },
3180 { "cvttps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3181 { "cvttss2si", { Gdq
, EXd
}, PREFIX_OPCODE
},
3182 { "cvttpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3183 { "cvttsd2si", { Gdq
, EXq
}, PREFIX_OPCODE
},
3188 { "cvtps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3189 { "cvtss2si", { Gdq
, EXd
}, PREFIX_OPCODE
},
3190 { "cvtpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3191 { "cvtsd2si", { Gdq
, EXq
}, PREFIX_OPCODE
},
3196 { "ucomiss",{ XM
, EXd
}, 0 },
3198 { "ucomisd",{ XM
, EXq
}, 0 },
3203 { "comiss", { XM
, EXd
}, 0 },
3205 { "comisd", { XM
, EXq
}, 0 },
3210 { "sqrtps", { XM
, EXx
}, PREFIX_OPCODE
},
3211 { "sqrtss", { XM
, EXd
}, PREFIX_OPCODE
},
3212 { "sqrtpd", { XM
, EXx
}, PREFIX_OPCODE
},
3213 { "sqrtsd", { XM
, EXq
}, PREFIX_OPCODE
},
3218 { "rsqrtps",{ XM
, EXx
}, PREFIX_OPCODE
},
3219 { "rsqrtss",{ XM
, EXd
}, PREFIX_OPCODE
},
3224 { "rcpps", { XM
, EXx
}, PREFIX_OPCODE
},
3225 { "rcpss", { XM
, EXd
}, PREFIX_OPCODE
},
3230 { "addps", { XM
, EXx
}, PREFIX_OPCODE
},
3231 { "addss", { XM
, EXd
}, PREFIX_OPCODE
},
3232 { "addpd", { XM
, EXx
}, PREFIX_OPCODE
},
3233 { "addsd", { XM
, EXq
}, PREFIX_OPCODE
},
3238 { "mulps", { XM
, EXx
}, PREFIX_OPCODE
},
3239 { "mulss", { XM
, EXd
}, PREFIX_OPCODE
},
3240 { "mulpd", { XM
, EXx
}, PREFIX_OPCODE
},
3241 { "mulsd", { XM
, EXq
}, PREFIX_OPCODE
},
3246 { "cvtps2pd", { XM
, EXq
}, PREFIX_OPCODE
},
3247 { "cvtss2sd", { XM
, EXd
}, PREFIX_OPCODE
},
3248 { "cvtpd2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3249 { "cvtsd2ss", { XM
, EXq
}, PREFIX_OPCODE
},
3254 { "cvtdq2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3255 { "cvttps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3256 { "cvtps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3261 { "subps", { XM
, EXx
}, PREFIX_OPCODE
},
3262 { "subss", { XM
, EXd
}, PREFIX_OPCODE
},
3263 { "subpd", { XM
, EXx
}, PREFIX_OPCODE
},
3264 { "subsd", { XM
, EXq
}, PREFIX_OPCODE
},
3269 { "minps", { XM
, EXx
}, PREFIX_OPCODE
},
3270 { "minss", { XM
, EXd
}, PREFIX_OPCODE
},
3271 { "minpd", { XM
, EXx
}, PREFIX_OPCODE
},
3272 { "minsd", { XM
, EXq
}, PREFIX_OPCODE
},
3277 { "divps", { XM
, EXx
}, PREFIX_OPCODE
},
3278 { "divss", { XM
, EXd
}, PREFIX_OPCODE
},
3279 { "divpd", { XM
, EXx
}, PREFIX_OPCODE
},
3280 { "divsd", { XM
, EXq
}, PREFIX_OPCODE
},
3285 { "maxps", { XM
, EXx
}, PREFIX_OPCODE
},
3286 { "maxss", { XM
, EXd
}, PREFIX_OPCODE
},
3287 { "maxpd", { XM
, EXx
}, PREFIX_OPCODE
},
3288 { "maxsd", { XM
, EXq
}, PREFIX_OPCODE
},
3293 { "punpcklbw",{ MX
, EMd
}, PREFIX_OPCODE
},
3295 { "punpcklbw",{ MX
, EMx
}, PREFIX_OPCODE
},
3300 { "punpcklwd",{ MX
, EMd
}, PREFIX_OPCODE
},
3302 { "punpcklwd",{ MX
, EMx
}, PREFIX_OPCODE
},
3307 { "punpckldq",{ MX
, EMd
}, PREFIX_OPCODE
},
3309 { "punpckldq",{ MX
, EMx
}, PREFIX_OPCODE
},
3314 { "movq", { MX
, EM
}, PREFIX_OPCODE
},
3315 { "movdqu", { XM
, EXx
}, PREFIX_OPCODE
},
3316 { "movdqa", { XM
, EXx
}, PREFIX_OPCODE
},
3321 { "pshufw", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
3322 { "pshufhw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3323 { "pshufd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3324 { "pshuflw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3329 {"vmread", { Em
, Gm
}, 0 },
3331 {"extrq", { XS
, Ib
, Ib
}, 0 },
3332 {"insertq", { XM
, XS
, Ib
, Ib
}, 0 },
3337 {"vmwrite", { Gm
, Em
}, 0 },
3339 {"extrq", { XM
, XS
}, 0 },
3340 {"insertq", { XM
, XS
}, 0 },
3347 { "haddpd", { XM
, EXx
}, PREFIX_OPCODE
},
3348 { "haddps", { XM
, EXx
}, PREFIX_OPCODE
},
3355 { "hsubpd", { XM
, EXx
}, PREFIX_OPCODE
},
3356 { "hsubps", { XM
, EXx
}, PREFIX_OPCODE
},
3361 { "movK", { Edq
, MX
}, PREFIX_OPCODE
},
3362 { "movq", { XM
, EXq
}, PREFIX_OPCODE
},
3363 { "movK", { Edq
, XM
}, PREFIX_OPCODE
},
3368 { "movq", { EMS
, MX
}, PREFIX_OPCODE
},
3369 { "movdqu", { EXxS
, XM
}, PREFIX_OPCODE
},
3370 { "movdqa", { EXxS
, XM
}, PREFIX_OPCODE
},
3373 /* PREFIX_0FAE_REG_0_MOD_3 */
3376 { "rdfsbase", { Ev
}, 0 },
3379 /* PREFIX_0FAE_REG_1_MOD_3 */
3382 { "rdgsbase", { Ev
}, 0 },
3385 /* PREFIX_0FAE_REG_2_MOD_3 */
3388 { "wrfsbase", { Ev
}, 0 },
3391 /* PREFIX_0FAE_REG_3_MOD_3 */
3394 { "wrgsbase", { Ev
}, 0 },
3397 /* PREFIX_0FAE_REG_4_MOD_0 */
3399 { "xsave", { FXSAVE
}, 0 },
3400 { "ptwrite{%LQ|}", { Edq
}, 0 },
3403 /* PREFIX_0FAE_REG_4_MOD_3 */
3406 { "ptwrite{%LQ|}", { Edq
}, 0 },
3409 /* PREFIX_0FAE_REG_5_MOD_3 */
3411 { "lfence", { Skip_MODRM
}, 0 },
3412 { "incsspK", { Edq
}, PREFIX_OPCODE
},
3415 /* PREFIX_0FAE_REG_6_MOD_0 */
3417 { "xsaveopt", { FXSAVE
}, PREFIX_OPCODE
},
3418 { "clrssbsy", { Mq
}, PREFIX_OPCODE
},
3419 { "clwb", { Mb
}, PREFIX_OPCODE
},
3422 /* PREFIX_0FAE_REG_6_MOD_3 */
3424 { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0
) },
3425 { "umonitor", { Eva
}, PREFIX_OPCODE
},
3426 { "tpause", { Edq
}, PREFIX_OPCODE
},
3427 { "umwait", { Edq
}, PREFIX_OPCODE
},
3430 /* PREFIX_0FAE_REG_7_MOD_0 */
3432 { "clflush", { Mb
}, 0 },
3434 { "clflushopt", { Mb
}, 0 },
3440 { "popcntS", { Gv
, Ev
}, 0 },
3445 { "bsfS", { Gv
, Ev
}, 0 },
3446 { "tzcntS", { Gv
, Ev
}, 0 },
3447 { "bsfS", { Gv
, Ev
}, 0 },
3452 { "bsrS", { Gv
, Ev
}, 0 },
3453 { "lzcntS", { Gv
, Ev
}, 0 },
3454 { "bsrS", { Gv
, Ev
}, 0 },
3459 { "cmpps", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
3460 { "cmpss", { XM
, EXd
, CMP
}, PREFIX_OPCODE
},
3461 { "cmppd", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
3462 { "cmpsd", { XM
, EXq
, CMP
}, PREFIX_OPCODE
},
3465 /* PREFIX_0FC7_REG_6_MOD_0 */
3467 { "vmptrld",{ Mq
}, 0 },
3468 { "vmxon", { Mq
}, 0 },
3469 { "vmclear",{ Mq
}, 0 },
3472 /* PREFIX_0FC7_REG_6_MOD_3 */
3474 { "rdrand", { Ev
}, 0 },
3475 { X86_64_TABLE (X86_64_0FC7_REG_6_MOD_3_PREFIX_1
) },
3476 { "rdrand", { Ev
}, 0 }
3479 /* PREFIX_0FC7_REG_7_MOD_3 */
3481 { "rdseed", { Ev
}, 0 },
3482 { "rdpid", { Em
}, 0 },
3483 { "rdseed", { Ev
}, 0 },
3490 { "addsubpd", { XM
, EXx
}, 0 },
3491 { "addsubps", { XM
, EXx
}, 0 },
3497 { "movq2dq",{ XM
, MS
}, 0 },
3498 { "movq", { EXqS
, XM
}, 0 },
3499 { "movdq2q",{ MX
, XS
}, 0 },
3505 { "cvtdq2pd", { XM
, EXq
}, PREFIX_OPCODE
},
3506 { "cvttpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3507 { "cvtpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3512 { "movntq", { Mq
, MX
}, PREFIX_OPCODE
},
3514 { MOD_TABLE (MOD_0FE7_PREFIX_2
) },
3522 { MOD_TABLE (MOD_0FF0_PREFIX_3
) },
3527 { "maskmovq", { MX
, MS
}, PREFIX_OPCODE
},
3529 { "maskmovdqu", { XM
, XS
}, PREFIX_OPCODE
},
3535 { REG_TABLE (REG_0F38D8_PREFIX_1
) },
3541 { MOD_TABLE (MOD_0F38DC_PREFIX_1
) },
3542 { "aesenc", { XM
, EXx
}, 0 },
3548 { MOD_TABLE (MOD_0F38DD_PREFIX_1
) },
3549 { "aesenclast", { XM
, EXx
}, 0 },
3555 { MOD_TABLE (MOD_0F38DE_PREFIX_1
) },
3556 { "aesdec", { XM
, EXx
}, 0 },
3562 { MOD_TABLE (MOD_0F38DF_PREFIX_1
) },
3563 { "aesdeclast", { XM
, EXx
}, 0 },
3568 { "movbeS", { Gv
, Mv
}, PREFIX_OPCODE
},
3570 { "movbeS", { Gv
, Mv
}, PREFIX_OPCODE
},
3571 { "crc32A", { Gdq
, Eb
}, PREFIX_OPCODE
},
3576 { "movbeS", { Mv
, Gv
}, PREFIX_OPCODE
},
3578 { "movbeS", { Mv
, Gv
}, PREFIX_OPCODE
},
3579 { "crc32Q", { Gdq
, Ev
}, PREFIX_OPCODE
},
3584 { MOD_TABLE (MOD_0F38F6_PREFIX_0
) },
3585 { "adoxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
3586 { "adcxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
3593 { MOD_TABLE (MOD_0F38F8_PREFIX_1
) },
3594 { MOD_TABLE (MOD_0F38F8_PREFIX_2
) },
3595 { MOD_TABLE (MOD_0F38F8_PREFIX_3
) },
3600 { MOD_TABLE (MOD_0F38FA_PREFIX_1
) },
3606 { MOD_TABLE (MOD_0F38FB_PREFIX_1
) },
3612 { MOD_TABLE (MOD_0F3A0F_PREFIX_1
)},
3615 /* PREFIX_VEX_0F10 */
3617 { "vmovups", { XM
, EXx
}, 0 },
3618 { "vmovss", { XMScalar
, VexScalarR
, EXxmm_md
}, 0 },
3619 { "vmovupd", { XM
, EXx
}, 0 },
3620 { "vmovsd", { XMScalar
, VexScalarR
, EXxmm_mq
}, 0 },
3623 /* PREFIX_VEX_0F11 */
3625 { "vmovups", { EXxS
, XM
}, 0 },
3626 { "vmovss", { EXdS
, VexScalarR
, XMScalar
}, 0 },
3627 { "vmovupd", { EXxS
, XM
}, 0 },
3628 { "vmovsd", { EXqS
, VexScalarR
, XMScalar
}, 0 },
3631 /* PREFIX_VEX_0F12 */
3633 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0
) },
3634 { "vmovsldup", { XM
, EXx
}, 0 },
3635 { MOD_TABLE (MOD_VEX_0F12_PREFIX_2
) },
3636 { "vmovddup", { XM
, EXymmq
}, 0 },
3639 /* PREFIX_VEX_0F16 */
3641 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0
) },
3642 { "vmovshdup", { XM
, EXx
}, 0 },
3643 { MOD_TABLE (MOD_VEX_0F16_PREFIX_2
) },
3646 /* PREFIX_VEX_0F2A */
3649 { "vcvtsi2ss{%LQ|}", { XMScalar
, VexScalar
, Edq
}, 0 },
3651 { "vcvtsi2sd{%LQ|}", { XMScalar
, VexScalar
, Edq
}, 0 },
3654 /* PREFIX_VEX_0F2C */
3657 { "vcvttss2si", { Gdq
, EXxmm_md
, EXxEVexS
}, 0 },
3659 { "vcvttsd2si", { Gdq
, EXxmm_mq
, EXxEVexS
}, 0 },
3662 /* PREFIX_VEX_0F2D */
3665 { "vcvtss2si", { Gdq
, EXxmm_md
, EXxEVexR
}, 0 },
3667 { "vcvtsd2si", { Gdq
, EXxmm_mq
, EXxEVexR
}, 0 },
3670 /* PREFIX_VEX_0F2E */
3672 { "vucomisX", { XMScalar
, EXxmm_md
, EXxEVexS
}, PREFIX_OPCODE
},
3674 { "vucomisX", { XMScalar
, EXxmm_mq
, EXxEVexS
}, PREFIX_OPCODE
},
3677 /* PREFIX_VEX_0F2F */
3679 { "vcomisX", { XMScalar
, EXxmm_md
, EXxEVexS
}, PREFIX_OPCODE
},
3681 { "vcomisX", { XMScalar
, EXxmm_mq
, EXxEVexS
}, PREFIX_OPCODE
},
3684 /* PREFIX_VEX_0F41_L_1_M_1_W_0 */
3686 { "kandw", { MaskG
, MaskVex
, MaskE
}, 0 },
3688 { "kandb", { MaskG
, MaskVex
, MaskE
}, 0 },
3691 /* PREFIX_VEX_0F41_L_1_M_1_W_1 */
3693 { "kandq", { MaskG
, MaskVex
, MaskE
}, 0 },
3695 { "kandd", { MaskG
, MaskVex
, MaskE
}, 0 },
3698 /* PREFIX_VEX_0F42_L_1_M_1_W_0 */
3700 { "kandnw", { MaskG
, MaskVex
, MaskE
}, 0 },
3702 { "kandnb", { MaskG
, MaskVex
, MaskE
}, 0 },
3705 /* PREFIX_VEX_0F42_L_1_M_1_W_1 */
3707 { "kandnq", { MaskG
, MaskVex
, MaskE
}, 0 },
3709 { "kandnd", { MaskG
, MaskVex
, MaskE
}, 0 },
3712 /* PREFIX_VEX_0F44_L_0_M_1_W_0 */
3714 { "knotw", { MaskG
, MaskE
}, 0 },
3716 { "knotb", { MaskG
, MaskE
}, 0 },
3719 /* PREFIX_VEX_0F44_L_0_M_1_W_1 */
3721 { "knotq", { MaskG
, MaskE
}, 0 },
3723 { "knotd", { MaskG
, MaskE
}, 0 },
3726 /* PREFIX_VEX_0F45_L_1_M_1_W_0 */
3728 { "korw", { MaskG
, MaskVex
, MaskE
}, 0 },
3730 { "korb", { MaskG
, MaskVex
, MaskE
}, 0 },
3733 /* PREFIX_VEX_0F45_L_1_M_1_W_1 */
3735 { "korq", { MaskG
, MaskVex
, MaskE
}, 0 },
3737 { "kord", { MaskG
, MaskVex
, MaskE
}, 0 },
3740 /* PREFIX_VEX_0F46_L_1_M_1_W_0 */
3742 { "kxnorw", { MaskG
, MaskVex
, MaskE
}, 0 },
3744 { "kxnorb", { MaskG
, MaskVex
, MaskE
}, 0 },
3747 /* PREFIX_VEX_0F46_L_1_M_1_W_1 */
3749 { "kxnorq", { MaskG
, MaskVex
, MaskE
}, 0 },
3751 { "kxnord", { MaskG
, MaskVex
, MaskE
}, 0 },
3754 /* PREFIX_VEX_0F47_L_1_M_1_W_0 */
3756 { "kxorw", { MaskG
, MaskVex
, MaskE
}, 0 },
3758 { "kxorb", { MaskG
, MaskVex
, MaskE
}, 0 },
3761 /* PREFIX_VEX_0F47_L_1_M_1_W_1 */
3763 { "kxorq", { MaskG
, MaskVex
, MaskE
}, 0 },
3765 { "kxord", { MaskG
, MaskVex
, MaskE
}, 0 },
3768 /* PREFIX_VEX_0F4A_L_1_M_1_W_0 */
3770 { "kaddw", { MaskG
, MaskVex
, MaskE
}, 0 },
3772 { "kaddb", { MaskG
, MaskVex
, MaskE
}, 0 },
3775 /* PREFIX_VEX_0F4A_L_1_M_1_W_1 */
3777 { "kaddq", { MaskG
, MaskVex
, MaskE
}, 0 },
3779 { "kaddd", { MaskG
, MaskVex
, MaskE
}, 0 },
3782 /* PREFIX_VEX_0F4B_L_1_M_1_W_0 */
3784 { "kunpckwd", { MaskG
, MaskVex
, MaskE
}, 0 },
3786 { "kunpckbw", { MaskG
, MaskVex
, MaskE
}, 0 },
3789 /* PREFIX_VEX_0F4B_L_1_M_1_W_1 */
3791 { "kunpckdq", { MaskG
, MaskVex
, MaskE
}, 0 },
3794 /* PREFIX_VEX_0F51 */
3796 { "vsqrtps", { XM
, EXx
}, 0 },
3797 { "vsqrtss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
3798 { "vsqrtpd", { XM
, EXx
}, 0 },
3799 { "vsqrtsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
3802 /* PREFIX_VEX_0F52 */
3804 { "vrsqrtps", { XM
, EXx
}, 0 },
3805 { "vrsqrtss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
3808 /* PREFIX_VEX_0F53 */
3810 { "vrcpps", { XM
, EXx
}, 0 },
3811 { "vrcpss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
3814 /* PREFIX_VEX_0F58 */
3816 { "vaddps", { XM
, Vex
, EXx
}, 0 },
3817 { "vaddss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
3818 { "vaddpd", { XM
, Vex
, EXx
}, 0 },
3819 { "vaddsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
3822 /* PREFIX_VEX_0F59 */
3824 { "vmulps", { XM
, Vex
, EXx
}, 0 },
3825 { "vmulss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
3826 { "vmulpd", { XM
, Vex
, EXx
}, 0 },
3827 { "vmulsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
3830 /* PREFIX_VEX_0F5A */
3832 { "vcvtps2pd", { XM
, EXxmmq
}, 0 },
3833 { "vcvtss2sd", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
3834 { "vcvtpd2ps%XY",{ XMM
, EXx
}, 0 },
3835 { "vcvtsd2ss", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
3838 /* PREFIX_VEX_0F5B */
3840 { "vcvtdq2ps", { XM
, EXx
}, 0 },
3841 { "vcvttps2dq", { XM
, EXx
}, 0 },
3842 { "vcvtps2dq", { XM
, EXx
}, 0 },
3845 /* PREFIX_VEX_0F5C */
3847 { "vsubps", { XM
, Vex
, EXx
}, 0 },
3848 { "vsubss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
3849 { "vsubpd", { XM
, Vex
, EXx
}, 0 },
3850 { "vsubsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
3853 /* PREFIX_VEX_0F5D */
3855 { "vminps", { XM
, Vex
, EXx
}, 0 },
3856 { "vminss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
3857 { "vminpd", { XM
, Vex
, EXx
}, 0 },
3858 { "vminsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
3861 /* PREFIX_VEX_0F5E */
3863 { "vdivps", { XM
, Vex
, EXx
}, 0 },
3864 { "vdivss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
3865 { "vdivpd", { XM
, Vex
, EXx
}, 0 },
3866 { "vdivsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
3869 /* PREFIX_VEX_0F5F */
3871 { "vmaxps", { XM
, Vex
, EXx
}, 0 },
3872 { "vmaxss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
3873 { "vmaxpd", { XM
, Vex
, EXx
}, 0 },
3874 { "vmaxsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
3877 /* PREFIX_VEX_0F6F */
3880 { "vmovdqu", { XM
, EXx
}, 0 },
3881 { "vmovdqa", { XM
, EXx
}, 0 },
3884 /* PREFIX_VEX_0F70 */
3887 { "vpshufhw", { XM
, EXx
, Ib
}, 0 },
3888 { "vpshufd", { XM
, EXx
, Ib
}, 0 },
3889 { "vpshuflw", { XM
, EXx
, Ib
}, 0 },
3892 /* PREFIX_VEX_0F7C */
3896 { "vhaddpd", { XM
, Vex
, EXx
}, 0 },
3897 { "vhaddps", { XM
, Vex
, EXx
}, 0 },
3900 /* PREFIX_VEX_0F7D */
3904 { "vhsubpd", { XM
, Vex
, EXx
}, 0 },
3905 { "vhsubps", { XM
, Vex
, EXx
}, 0 },
3908 /* PREFIX_VEX_0F7E */
3911 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1
) },
3912 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2
) },
3915 /* PREFIX_VEX_0F7F */
3918 { "vmovdqu", { EXxS
, XM
}, 0 },
3919 { "vmovdqa", { EXxS
, XM
}, 0 },
3922 /* PREFIX_VEX_0F90_L_0_W_0 */
3924 { "kmovw", { MaskG
, MaskE
}, 0 },
3926 { "kmovb", { MaskG
, MaskBDE
}, 0 },
3929 /* PREFIX_VEX_0F90_L_0_W_1 */
3931 { "kmovq", { MaskG
, MaskE
}, 0 },
3933 { "kmovd", { MaskG
, MaskBDE
}, 0 },
3936 /* PREFIX_VEX_0F91_L_0_M_0_W_0 */
3938 { "kmovw", { Ew
, MaskG
}, 0 },
3940 { "kmovb", { Eb
, MaskG
}, 0 },
3943 /* PREFIX_VEX_0F91_L_0_M_0_W_1 */
3945 { "kmovq", { Eq
, MaskG
}, 0 },
3947 { "kmovd", { Ed
, MaskG
}, 0 },
3950 /* PREFIX_VEX_0F92_L_0_M_1_W_0 */
3952 { "kmovw", { MaskG
, Edq
}, 0 },
3954 { "kmovb", { MaskG
, Edq
}, 0 },
3955 { "kmovd", { MaskG
, Edq
}, 0 },
3958 /* PREFIX_VEX_0F92_L_0_M_1_W_1 */
3963 { "kmovK", { MaskG
, Edq
}, 0 },
3966 /* PREFIX_VEX_0F93_L_0_M_1_W_0 */
3968 { "kmovw", { Gdq
, MaskE
}, 0 },
3970 { "kmovb", { Gdq
, MaskE
}, 0 },
3971 { "kmovd", { Gdq
, MaskE
}, 0 },
3974 /* PREFIX_VEX_0F93_L_0_M_1_W_1 */
3979 { "kmovK", { Gdq
, MaskE
}, 0 },
3982 /* PREFIX_VEX_0F98_L_0_M_1_W_0 */
3984 { "kortestw", { MaskG
, MaskE
}, 0 },
3986 { "kortestb", { MaskG
, MaskE
}, 0 },
3989 /* PREFIX_VEX_0F98_L_0_M_1_W_1 */
3991 { "kortestq", { MaskG
, MaskE
}, 0 },
3993 { "kortestd", { MaskG
, MaskE
}, 0 },
3996 /* PREFIX_VEX_0F99_L_0_M_1_W_0 */
3998 { "ktestw", { MaskG
, MaskE
}, 0 },
4000 { "ktestb", { MaskG
, MaskE
}, 0 },
4003 /* PREFIX_VEX_0F99_L_0_M_1_W_1 */
4005 { "ktestq", { MaskG
, MaskE
}, 0 },
4007 { "ktestd", { MaskG
, MaskE
}, 0 },
4010 /* PREFIX_VEX_0FC2 */
4012 { "vcmpps", { XM
, Vex
, EXx
, CMP
}, 0 },
4013 { "vcmpss", { XMScalar
, VexScalar
, EXxmm_md
, CMP
}, 0 },
4014 { "vcmppd", { XM
, Vex
, EXx
, CMP
}, 0 },
4015 { "vcmpsd", { XMScalar
, VexScalar
, EXxmm_mq
, CMP
}, 0 },
4018 /* PREFIX_VEX_0FD0 */
4022 { "vaddsubpd", { XM
, Vex
, EXx
}, 0 },
4023 { "vaddsubps", { XM
, Vex
, EXx
}, 0 },
4026 /* PREFIX_VEX_0FE6 */
4029 { "vcvtdq2pd", { XM
, EXxmmq
}, 0 },
4030 { "vcvttpd2dq%XY", { XMM
, EXx
}, 0 },
4031 { "vcvtpd2dq%XY", { XMM
, EXx
}, 0 },
4034 /* PREFIX_VEX_0FF0 */
4039 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3
) },
4042 /* PREFIX_VEX_0F3849_X86_64 */
4044 { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_0
) },
4046 { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_2
) },
4047 { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_3
) },
4050 /* PREFIX_VEX_0F384B_X86_64 */
4053 { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_1
) },
4054 { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_2
) },
4055 { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_3
) },
4058 /* PREFIX_VEX_0F385C_X86_64 */
4061 { VEX_W_TABLE (VEX_W_0F385C_X86_64_P_1
) },
4065 /* PREFIX_VEX_0F385E_X86_64 */
4067 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_0
) },
4068 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_1
) },
4069 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_2
) },
4070 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_3
) },
4073 /* PREFIX_VEX_0F38F5_L_0 */
4075 { "bzhiS", { Gdq
, Edq
, VexGdq
}, 0 },
4076 { "pextS", { Gdq
, VexGdq
, Edq
}, 0 },
4078 { "pdepS", { Gdq
, VexGdq
, Edq
}, 0 },
4081 /* PREFIX_VEX_0F38F6_L_0 */
4086 { "mulxS", { Gdq
, VexGdq
, Edq
}, 0 },
4089 /* PREFIX_VEX_0F38F7_L_0 */
4091 { "bextrS", { Gdq
, Edq
, VexGdq
}, 0 },
4092 { "sarxS", { Gdq
, Edq
, VexGdq
}, 0 },
4093 { "shlxS", { Gdq
, Edq
, VexGdq
}, 0 },
4094 { "shrxS", { Gdq
, Edq
, VexGdq
}, 0 },
4097 /* PREFIX_VEX_0F3AF0_L_0 */
4102 { "rorxS", { Gdq
, Edq
, Ib
}, 0 },
4105 #include "i386-dis-evex-prefix.h"
4108 static const struct dis386 x86_64_table
[][2] = {
4111 { "pushP", { es
}, 0 },
4116 { "popP", { es
}, 0 },
4121 { "pushP", { cs
}, 0 },
4126 { "pushP", { ss
}, 0 },
4131 { "popP", { ss
}, 0 },
4136 { "pushP", { ds
}, 0 },
4141 { "popP", { ds
}, 0 },
4146 { "daa", { XX
}, 0 },
4151 { "das", { XX
}, 0 },
4156 { "aaa", { XX
}, 0 },
4161 { "aas", { XX
}, 0 },
4166 { "pushaP", { XX
}, 0 },
4171 { "popaP", { XX
}, 0 },
4176 { MOD_TABLE (MOD_62_32BIT
) },
4177 { EVEX_TABLE (EVEX_0F
) },
4182 { "arpl", { Ew
, Gw
}, 0 },
4183 { "movs", { { OP_G
, movsxd_mode
}, { MOVSXD_Fixup
, movsxd_mode
} }, 0 },
4188 { "ins{R|}", { Yzr
, indirDX
}, 0 },
4189 { "ins{G|}", { Yzr
, indirDX
}, 0 },
4194 { "outs{R|}", { indirDXr
, Xz
}, 0 },
4195 { "outs{G|}", { indirDXr
, Xz
}, 0 },
4200 /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */
4201 { REG_TABLE (REG_80
) },
4206 { "{l|}call{P|}", { Ap
}, 0 },
4211 { "retP", { Iw
, BND
}, 0 },
4212 { "ret@", { Iw
, BND
}, 0 },
4217 { "retP", { BND
}, 0 },
4218 { "ret@", { BND
}, 0 },
4223 { MOD_TABLE (MOD_C4_32BIT
) },
4224 { VEX_C4_TABLE (VEX_0F
) },
4229 { MOD_TABLE (MOD_C5_32BIT
) },
4230 { VEX_C5_TABLE (VEX_0F
) },
4235 { "into", { XX
}, 0 },
4240 { "aam", { Ib
}, 0 },
4245 { "aad", { Ib
}, 0 },
4250 { "callP", { Jv
, BND
}, 0 },
4251 { "call@", { Jv
, BND
}, 0 }
4256 { "jmpP", { Jv
, BND
}, 0 },
4257 { "jmp@", { Jv
, BND
}, 0 }
4262 { "{l|}jmp{P|}", { Ap
}, 0 },
4265 /* X86_64_0F01_REG_0 */
4267 { "sgdt{Q|Q}", { M
}, 0 },
4268 { "sgdt", { M
}, 0 },
4271 /* X86_64_0F01_REG_1 */
4273 { "sidt{Q|Q}", { M
}, 0 },
4274 { "sidt", { M
}, 0 },
4277 /* X86_64_0F01_REG_1_RM_5_PREFIX_2 */
4280 { "seamret", { Skip_MODRM
}, 0 },
4283 /* X86_64_0F01_REG_1_RM_6_PREFIX_2 */
4286 { "seamops", { Skip_MODRM
}, 0 },
4289 /* X86_64_0F01_REG_1_RM_7_PREFIX_2 */
4292 { "seamcall", { Skip_MODRM
}, 0 },
4295 /* X86_64_0F01_REG_2 */
4297 { "lgdt{Q|Q}", { M
}, 0 },
4298 { "lgdt", { M
}, 0 },
4301 /* X86_64_0F01_REG_3 */
4303 { "lidt{Q|Q}", { M
}, 0 },
4304 { "lidt", { M
}, 0 },
4307 /* X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1 */
4310 { "uiret", { Skip_MODRM
}, 0 },
4313 /* X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1 */
4316 { "testui", { Skip_MODRM
}, 0 },
4319 /* X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1 */
4322 { "clui", { Skip_MODRM
}, 0 },
4325 /* X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1 */
4328 { "stui", { Skip_MODRM
}, 0 },
4331 /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1 */
4334 { "rmpadjust", { Skip_MODRM
}, 0 },
4337 /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3 */
4340 { "rmpupdate", { Skip_MODRM
}, 0 },
4343 /* X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1 */
4346 { "psmash", { Skip_MODRM
}, 0 },
4351 { "movZ", { Em
, Td
}, 0 },
4356 { "movZ", { Td
, Em
}, 0 },
4359 /* X86_64_0FC7_REG_6_MOD_3_PREFIX_1 */
4362 { "senduipi", { Eq
}, 0 },
4365 /* X86_64_VEX_0F3849 */
4368 { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64
) },
4371 /* X86_64_VEX_0F384B */
4374 { PREFIX_TABLE (PREFIX_VEX_0F384B_X86_64
) },
4377 /* X86_64_VEX_0F385C */
4380 { PREFIX_TABLE (PREFIX_VEX_0F385C_X86_64
) },
4383 /* X86_64_VEX_0F385E */
4386 { PREFIX_TABLE (PREFIX_VEX_0F385E_X86_64
) },
4390 static const struct dis386 three_byte_table
[][256] = {
4392 /* THREE_BYTE_0F38 */
4395 { "pshufb", { MX
, EM
}, PREFIX_OPCODE
},
4396 { "phaddw", { MX
, EM
}, PREFIX_OPCODE
},
4397 { "phaddd", { MX
, EM
}, PREFIX_OPCODE
},
4398 { "phaddsw", { MX
, EM
}, PREFIX_OPCODE
},
4399 { "pmaddubsw", { MX
, EM
}, PREFIX_OPCODE
},
4400 { "phsubw", { MX
, EM
}, PREFIX_OPCODE
},
4401 { "phsubd", { MX
, EM
}, PREFIX_OPCODE
},
4402 { "phsubsw", { MX
, EM
}, PREFIX_OPCODE
},
4404 { "psignb", { MX
, EM
}, PREFIX_OPCODE
},
4405 { "psignw", { MX
, EM
}, PREFIX_OPCODE
},
4406 { "psignd", { MX
, EM
}, PREFIX_OPCODE
},
4407 { "pmulhrsw", { MX
, EM
}, PREFIX_OPCODE
},
4413 { "pblendvb", { XM
, EXx
, XMM0
}, PREFIX_DATA
},
4417 { "blendvps", { XM
, EXx
, XMM0
}, PREFIX_DATA
},
4418 { "blendvpd", { XM
, EXx
, XMM0
}, PREFIX_DATA
},
4420 { "ptest", { XM
, EXx
}, PREFIX_DATA
},
4426 { "pabsb", { MX
, EM
}, PREFIX_OPCODE
},
4427 { "pabsw", { MX
, EM
}, PREFIX_OPCODE
},
4428 { "pabsd", { MX
, EM
}, PREFIX_OPCODE
},
4431 { "pmovsxbw", { XM
, EXq
}, PREFIX_DATA
},
4432 { "pmovsxbd", { XM
, EXd
}, PREFIX_DATA
},
4433 { "pmovsxbq", { XM
, EXw
}, PREFIX_DATA
},
4434 { "pmovsxwd", { XM
, EXq
}, PREFIX_DATA
},
4435 { "pmovsxwq", { XM
, EXd
}, PREFIX_DATA
},
4436 { "pmovsxdq", { XM
, EXq
}, PREFIX_DATA
},
4440 { "pmuldq", { XM
, EXx
}, PREFIX_DATA
},
4441 { "pcmpeqq", { XM
, EXx
}, PREFIX_DATA
},
4442 { MOD_TABLE (MOD_0F382A
) },
4443 { "packusdw", { XM
, EXx
}, PREFIX_DATA
},
4449 { "pmovzxbw", { XM
, EXq
}, PREFIX_DATA
},
4450 { "pmovzxbd", { XM
, EXd
}, PREFIX_DATA
},
4451 { "pmovzxbq", { XM
, EXw
}, PREFIX_DATA
},
4452 { "pmovzxwd", { XM
, EXq
}, PREFIX_DATA
},
4453 { "pmovzxwq", { XM
, EXd
}, PREFIX_DATA
},
4454 { "pmovzxdq", { XM
, EXq
}, PREFIX_DATA
},
4456 { "pcmpgtq", { XM
, EXx
}, PREFIX_DATA
},
4458 { "pminsb", { XM
, EXx
}, PREFIX_DATA
},
4459 { "pminsd", { XM
, EXx
}, PREFIX_DATA
},
4460 { "pminuw", { XM
, EXx
}, PREFIX_DATA
},
4461 { "pminud", { XM
, EXx
}, PREFIX_DATA
},
4462 { "pmaxsb", { XM
, EXx
}, PREFIX_DATA
},
4463 { "pmaxsd", { XM
, EXx
}, PREFIX_DATA
},
4464 { "pmaxuw", { XM
, EXx
}, PREFIX_DATA
},
4465 { "pmaxud", { XM
, EXx
}, PREFIX_DATA
},
4467 { "pmulld", { XM
, EXx
}, PREFIX_DATA
},
4468 { "phminposuw", { XM
, EXx
}, PREFIX_DATA
},
4539 { "invept", { Gm
, Mo
}, PREFIX_DATA
},
4540 { "invvpid", { Gm
, Mo
}, PREFIX_DATA
},
4541 { "invpcid", { Gm
, M
}, PREFIX_DATA
},
4620 { "sha1nexte", { XM
, EXxmm
}, PREFIX_OPCODE
},
4621 { "sha1msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4622 { "sha1msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4623 { "sha256rnds2", { XM
, EXxmm
, XMM0
}, PREFIX_OPCODE
},
4624 { "sha256msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4625 { "sha256msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4627 { "gf2p8mulb", { XM
, EXxmm
}, PREFIX_DATA
},
4638 { PREFIX_TABLE (PREFIX_0F38D8
) },
4641 { "aesimc", { XM
, EXx
}, PREFIX_DATA
},
4642 { PREFIX_TABLE (PREFIX_0F38DC
) },
4643 { PREFIX_TABLE (PREFIX_0F38DD
) },
4644 { PREFIX_TABLE (PREFIX_0F38DE
) },
4645 { PREFIX_TABLE (PREFIX_0F38DF
) },
4665 { PREFIX_TABLE (PREFIX_0F38F0
) },
4666 { PREFIX_TABLE (PREFIX_0F38F1
) },
4670 { MOD_TABLE (MOD_0F38F5
) },
4671 { PREFIX_TABLE (PREFIX_0F38F6
) },
4674 { PREFIX_TABLE (PREFIX_0F38F8
) },
4675 { MOD_TABLE (MOD_0F38F9
) },
4676 { PREFIX_TABLE (PREFIX_0F38FA
) },
4677 { PREFIX_TABLE (PREFIX_0F38FB
) },
4683 /* THREE_BYTE_0F3A */
4695 { "roundps", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4696 { "roundpd", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4697 { "roundss", { XM
, EXd
, Ib
}, PREFIX_DATA
},
4698 { "roundsd", { XM
, EXq
, Ib
}, PREFIX_DATA
},
4699 { "blendps", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4700 { "blendpd", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4701 { "pblendw", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4702 { "palignr", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
4708 { "pextrb", { Edqb
, XM
, Ib
}, PREFIX_DATA
},
4709 { "pextrw", { Edqw
, XM
, Ib
}, PREFIX_DATA
},
4710 { "pextrK", { Edq
, XM
, Ib
}, PREFIX_DATA
},
4711 { "extractps", { Edqd
, XM
, Ib
}, PREFIX_DATA
},
4722 { "pinsrb", { XM
, Edqb
, Ib
}, PREFIX_DATA
},
4723 { "insertps", { XM
, EXd
, Ib
}, PREFIX_DATA
},
4724 { "pinsrK", { XM
, Edq
, Ib
}, PREFIX_DATA
},
4758 { "dpps", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4759 { "dppd", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4760 { "mpsadbw", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4762 { "pclmulqdq", { XM
, EXx
, PCLMUL
}, PREFIX_DATA
},
4794 { "pcmpestrm!%LQ", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4795 { "pcmpestri!%LQ", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4796 { "pcmpistrm", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4797 { "pcmpistri", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4915 { "sha1rnds4", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4917 { "gf2p8affineqb", { XM
, EXxmm
, Ib
}, PREFIX_DATA
},
4918 { "gf2p8affineinvqb", { XM
, EXxmm
, Ib
}, PREFIX_DATA
},
4936 { "aeskeygenassist", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4956 { PREFIX_TABLE (PREFIX_0F3A0F
) },
4976 static const struct dis386 xop_table
[][256] = {
5129 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_85
) },
5130 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_86
) },
5131 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_87
) },
5139 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8E
) },
5140 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8F
) },
5147 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_95
) },
5148 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_96
) },
5149 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_97
) },
5157 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9E
) },
5158 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9F
) },
5162 { "vpcmov", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
5163 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A3
) },
5166 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A6
) },
5184 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_B6
) },
5196 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C0
) },
5197 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C1
) },
5198 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C2
) },
5199 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C3
) },
5209 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC
) },
5210 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD
) },
5211 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE
) },
5212 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF
) },
5245 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC
) },
5246 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED
) },
5247 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE
) },
5248 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF
) },
5272 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_01
) },
5273 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_02
) },
5291 { MOD_TABLE (MOD_XOP_09_12
) },
5415 { VEX_W_TABLE (VEX_W_0FXOP_09_80
) },
5416 { VEX_W_TABLE (VEX_W_0FXOP_09_81
) },
5417 { VEX_W_TABLE (VEX_W_0FXOP_09_82
) },
5418 { VEX_W_TABLE (VEX_W_0FXOP_09_83
) },
5433 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_90
) },
5434 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_91
) },
5435 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_92
) },
5436 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_93
) },
5437 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_94
) },
5438 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_95
) },
5439 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_96
) },
5440 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_97
) },
5442 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_98
) },
5443 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_99
) },
5444 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9A
) },
5445 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9B
) },
5488 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C1
) },
5489 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C2
) },
5490 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C3
) },
5493 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C6
) },
5494 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C7
) },
5499 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_CB
) },
5506 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D1
) },
5507 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D2
) },
5508 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D3
) },
5511 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D6
) },
5512 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D7
) },
5517 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_DB
) },
5524 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E1
) },
5525 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E2
) },
5526 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E3
) },
5580 { "bextrS", { Gdq
, Edq
, Id
}, 0 },
5582 { VEX_LEN_TABLE (VEX_LEN_0FXOP_0A_12
) },
5852 static const struct dis386 vex_table
[][256] = {
5874 { PREFIX_TABLE (PREFIX_VEX_0F10
) },
5875 { PREFIX_TABLE (PREFIX_VEX_0F11
) },
5876 { PREFIX_TABLE (PREFIX_VEX_0F12
) },
5877 { MOD_TABLE (MOD_VEX_0F13
) },
5878 { "vunpcklpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
5879 { "vunpckhpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
5880 { PREFIX_TABLE (PREFIX_VEX_0F16
) },
5881 { MOD_TABLE (MOD_VEX_0F17
) },
5901 { "vmovapX", { XM
, EXx
}, PREFIX_OPCODE
},
5902 { "vmovapX", { EXxS
, XM
}, PREFIX_OPCODE
},
5903 { PREFIX_TABLE (PREFIX_VEX_0F2A
) },
5904 { MOD_TABLE (MOD_VEX_0F2B
) },
5905 { PREFIX_TABLE (PREFIX_VEX_0F2C
) },
5906 { PREFIX_TABLE (PREFIX_VEX_0F2D
) },
5907 { PREFIX_TABLE (PREFIX_VEX_0F2E
) },
5908 { PREFIX_TABLE (PREFIX_VEX_0F2F
) },
5929 { VEX_LEN_TABLE (VEX_LEN_0F41
) },
5930 { VEX_LEN_TABLE (VEX_LEN_0F42
) },
5932 { VEX_LEN_TABLE (VEX_LEN_0F44
) },
5933 { VEX_LEN_TABLE (VEX_LEN_0F45
) },
5934 { VEX_LEN_TABLE (VEX_LEN_0F46
) },
5935 { VEX_LEN_TABLE (VEX_LEN_0F47
) },
5939 { VEX_LEN_TABLE (VEX_LEN_0F4A
) },
5940 { VEX_LEN_TABLE (VEX_LEN_0F4B
) },
5946 { MOD_TABLE (MOD_VEX_0F50
) },
5947 { PREFIX_TABLE (PREFIX_VEX_0F51
) },
5948 { PREFIX_TABLE (PREFIX_VEX_0F52
) },
5949 { PREFIX_TABLE (PREFIX_VEX_0F53
) },
5950 { "vandpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
5951 { "vandnpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
5952 { "vorpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
5953 { "vxorpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
5955 { PREFIX_TABLE (PREFIX_VEX_0F58
) },
5956 { PREFIX_TABLE (PREFIX_VEX_0F59
) },
5957 { PREFIX_TABLE (PREFIX_VEX_0F5A
) },
5958 { PREFIX_TABLE (PREFIX_VEX_0F5B
) },
5959 { PREFIX_TABLE (PREFIX_VEX_0F5C
) },
5960 { PREFIX_TABLE (PREFIX_VEX_0F5D
) },
5961 { PREFIX_TABLE (PREFIX_VEX_0F5E
) },
5962 { PREFIX_TABLE (PREFIX_VEX_0F5F
) },
5964 { "vpunpcklbw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5965 { "vpunpcklwd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5966 { "vpunpckldq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5967 { "vpacksswb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5968 { "vpcmpgtb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5969 { "vpcmpgtw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5970 { "vpcmpgtd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5971 { "vpackuswb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5973 { "vpunpckhbw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5974 { "vpunpckhwd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5975 { "vpunpckhdq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5976 { "vpackssdw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5977 { "vpunpcklqdq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5978 { "vpunpckhqdq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5979 { VEX_LEN_TABLE (VEX_LEN_0F6E
) },
5980 { PREFIX_TABLE (PREFIX_VEX_0F6F
) },
5982 { PREFIX_TABLE (PREFIX_VEX_0F70
) },
5983 { MOD_TABLE (MOD_VEX_0F71
) },
5984 { MOD_TABLE (MOD_VEX_0F72
) },
5985 { MOD_TABLE (MOD_VEX_0F73
) },
5986 { "vpcmpeqb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5987 { "vpcmpeqw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5988 { "vpcmpeqd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5989 { VEX_LEN_TABLE (VEX_LEN_0F77
) },
5995 { PREFIX_TABLE (PREFIX_VEX_0F7C
) },
5996 { PREFIX_TABLE (PREFIX_VEX_0F7D
) },
5997 { PREFIX_TABLE (PREFIX_VEX_0F7E
) },
5998 { PREFIX_TABLE (PREFIX_VEX_0F7F
) },
6018 { VEX_LEN_TABLE (VEX_LEN_0F90
) },
6019 { VEX_LEN_TABLE (VEX_LEN_0F91
) },
6020 { VEX_LEN_TABLE (VEX_LEN_0F92
) },
6021 { VEX_LEN_TABLE (VEX_LEN_0F93
) },
6027 { VEX_LEN_TABLE (VEX_LEN_0F98
) },
6028 { VEX_LEN_TABLE (VEX_LEN_0F99
) },
6051 { REG_TABLE (REG_VEX_0FAE
) },
6074 { PREFIX_TABLE (PREFIX_VEX_0FC2
) },
6076 { VEX_LEN_TABLE (VEX_LEN_0FC4
) },
6077 { VEX_LEN_TABLE (VEX_LEN_0FC5
) },
6078 { "vshufpX", { XM
, Vex
, EXx
, Ib
}, PREFIX_OPCODE
},
6090 { PREFIX_TABLE (PREFIX_VEX_0FD0
) },
6091 { "vpsrlw", { XM
, Vex
, EXxmm
}, PREFIX_DATA
},
6092 { "vpsrld", { XM
, Vex
, EXxmm
}, PREFIX_DATA
},
6093 { "vpsrlq", { XM
, Vex
, EXxmm
}, PREFIX_DATA
},
6094 { "vpaddq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6095 { "vpmullw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6096 { VEX_LEN_TABLE (VEX_LEN_0FD6
) },
6097 { MOD_TABLE (MOD_VEX_0FD7
) },
6099 { "vpsubusb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6100 { "vpsubusw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6101 { "vpminub", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6102 { "vpand", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6103 { "vpaddusb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6104 { "vpaddusw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6105 { "vpmaxub", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6106 { "vpandn", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6108 { "vpavgb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6109 { "vpsraw", { XM
, Vex
, EXxmm
}, PREFIX_DATA
},
6110 { "vpsrad", { XM
, Vex
, EXxmm
}, PREFIX_DATA
},
6111 { "vpavgw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6112 { "vpmulhuw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6113 { "vpmulhw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6114 { PREFIX_TABLE (PREFIX_VEX_0FE6
) },
6115 { MOD_TABLE (MOD_VEX_0FE7
) },
6117 { "vpsubsb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6118 { "vpsubsw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6119 { "vpminsw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6120 { "vpor", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6121 { "vpaddsb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6122 { "vpaddsw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6123 { "vpmaxsw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6124 { "vpxor", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6126 { PREFIX_TABLE (PREFIX_VEX_0FF0
) },
6127 { "vpsllw", { XM
, Vex
, EXxmm
}, PREFIX_DATA
},
6128 { "vpslld", { XM
, Vex
, EXxmm
}, PREFIX_DATA
},
6129 { "vpsllq", { XM
, Vex
, EXxmm
}, PREFIX_DATA
},
6130 { "vpmuludq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6131 { "vpmaddwd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6132 { "vpsadbw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6133 { VEX_LEN_TABLE (VEX_LEN_0FF7
) },
6135 { "vpsubb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6136 { "vpsubw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6137 { "vpsubd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6138 { "vpsubq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6139 { "vpaddb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6140 { "vpaddw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6141 { "vpaddd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6147 { "vpshufb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6148 { "vphaddw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6149 { "vphaddd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6150 { "vphaddsw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6151 { "vpmaddubsw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6152 { "vphsubw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6153 { "vphsubd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6154 { "vphsubsw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6156 { "vpsignb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6157 { "vpsignw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6158 { "vpsignd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6159 { "vpmulhrsw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6160 { VEX_W_TABLE (VEX_W_0F380C
) },
6161 { VEX_W_TABLE (VEX_W_0F380D
) },
6162 { VEX_W_TABLE (VEX_W_0F380E
) },
6163 { VEX_W_TABLE (VEX_W_0F380F
) },
6168 { VEX_W_TABLE (VEX_W_0F3813
) },
6171 { VEX_LEN_TABLE (VEX_LEN_0F3816
) },
6172 { "vptest", { XM
, EXx
}, PREFIX_DATA
},
6174 { VEX_W_TABLE (VEX_W_0F3818
) },
6175 { VEX_LEN_TABLE (VEX_LEN_0F3819
) },
6176 { MOD_TABLE (MOD_VEX_0F381A
) },
6178 { "vpabsb", { XM
, EXx
}, PREFIX_DATA
},
6179 { "vpabsw", { XM
, EXx
}, PREFIX_DATA
},
6180 { "vpabsd", { XM
, EXx
}, PREFIX_DATA
},
6183 { "vpmovsxbw", { XM
, EXxmmq
}, PREFIX_DATA
},
6184 { "vpmovsxbd", { XM
, EXxmmqd
}, PREFIX_DATA
},
6185 { "vpmovsxbq", { XM
, EXxmmdw
}, PREFIX_DATA
},
6186 { "vpmovsxwd", { XM
, EXxmmq
}, PREFIX_DATA
},
6187 { "vpmovsxwq", { XM
, EXxmmqd
}, PREFIX_DATA
},
6188 { "vpmovsxdq", { XM
, EXxmmq
}, PREFIX_DATA
},
6192 { "vpmuldq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6193 { "vpcmpeqq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6194 { MOD_TABLE (MOD_VEX_0F382A
) },
6195 { "vpackusdw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6196 { MOD_TABLE (MOD_VEX_0F382C
) },
6197 { MOD_TABLE (MOD_VEX_0F382D
) },
6198 { MOD_TABLE (MOD_VEX_0F382E
) },
6199 { MOD_TABLE (MOD_VEX_0F382F
) },
6201 { "vpmovzxbw", { XM
, EXxmmq
}, PREFIX_DATA
},
6202 { "vpmovzxbd", { XM
, EXxmmqd
}, PREFIX_DATA
},
6203 { "vpmovzxbq", { XM
, EXxmmdw
}, PREFIX_DATA
},
6204 { "vpmovzxwd", { XM
, EXxmmq
}, PREFIX_DATA
},
6205 { "vpmovzxwq", { XM
, EXxmmqd
}, PREFIX_DATA
},
6206 { "vpmovzxdq", { XM
, EXxmmq
}, PREFIX_DATA
},
6207 { VEX_LEN_TABLE (VEX_LEN_0F3836
) },
6208 { "vpcmpgtq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6210 { "vpminsb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6211 { "vpminsd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6212 { "vpminuw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6213 { "vpminud", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6214 { "vpmaxsb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6215 { "vpmaxsd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6216 { "vpmaxuw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6217 { "vpmaxud", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6219 { "vpmulld", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6220 { VEX_LEN_TABLE (VEX_LEN_0F3841
) },
6224 { "vpsrlv%DQ", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6225 { VEX_W_TABLE (VEX_W_0F3846
) },
6226 { "vpsllv%DQ", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6229 { X86_64_TABLE (X86_64_VEX_0F3849
) },
6231 { X86_64_TABLE (X86_64_VEX_0F384B
) },
6237 { VEX_W_TABLE (VEX_W_0F3850
) },
6238 { VEX_W_TABLE (VEX_W_0F3851
) },
6239 { VEX_W_TABLE (VEX_W_0F3852
) },
6240 { VEX_W_TABLE (VEX_W_0F3853
) },
6246 { VEX_W_TABLE (VEX_W_0F3858
) },
6247 { VEX_W_TABLE (VEX_W_0F3859
) },
6248 { MOD_TABLE (MOD_VEX_0F385A
) },
6250 { X86_64_TABLE (X86_64_VEX_0F385C
) },
6252 { X86_64_TABLE (X86_64_VEX_0F385E
) },
6282 { VEX_W_TABLE (VEX_W_0F3878
) },
6283 { VEX_W_TABLE (VEX_W_0F3879
) },
6304 { MOD_TABLE (MOD_VEX_0F388C
) },
6306 { MOD_TABLE (MOD_VEX_0F388E
) },
6309 { "vpgatherd%DQ", { XM
, MVexVSIBDWpX
, VexGatherD
}, PREFIX_DATA
},
6310 { "vpgatherq%DQ", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, PREFIX_DATA
},
6311 { "vgatherdp%XW", { XM
, MVexVSIBDWpX
, VexGatherD
}, PREFIX_DATA
},
6312 { "vgatherqp%XW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, PREFIX_DATA
},
6315 { "vfmaddsub132p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6316 { "vfmsubadd132p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6318 { "vfmadd132p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6319 { "vfmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6320 { "vfmsub132p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6321 { "vfmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6322 { "vfnmadd132p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6323 { "vfnmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6324 { "vfnmsub132p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6325 { "vfnmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6333 { "vfmaddsub213p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6334 { "vfmsubadd213p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6336 { "vfmadd213p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6337 { "vfmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6338 { "vfmsub213p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6339 { "vfmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6340 { "vfnmadd213p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6341 { "vfnmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6342 { "vfnmsub213p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6343 { "vfnmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6351 { "vfmaddsub231p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6352 { "vfmsubadd231p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6354 { "vfmadd231p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6355 { "vfmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6356 { "vfmsub231p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6357 { "vfmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6358 { "vfnmadd231p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6359 { "vfnmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6360 { "vfnmsub231p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6361 { "vfnmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6379 { VEX_W_TABLE (VEX_W_0F38CF
) },
6393 { VEX_LEN_TABLE (VEX_LEN_0F38DB
) },
6394 { "vaesenc", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6395 { "vaesenclast", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6396 { "vaesdec", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6397 { "vaesdeclast", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6419 { VEX_LEN_TABLE (VEX_LEN_0F38F2
) },
6420 { VEX_LEN_TABLE (VEX_LEN_0F38F3
) },
6422 { VEX_LEN_TABLE (VEX_LEN_0F38F5
) },
6423 { VEX_LEN_TABLE (VEX_LEN_0F38F6
) },
6424 { VEX_LEN_TABLE (VEX_LEN_0F38F7
) },
6438 { VEX_LEN_TABLE (VEX_LEN_0F3A00
) },
6439 { VEX_LEN_TABLE (VEX_LEN_0F3A01
) },
6440 { VEX_W_TABLE (VEX_W_0F3A02
) },
6442 { VEX_W_TABLE (VEX_W_0F3A04
) },
6443 { VEX_W_TABLE (VEX_W_0F3A05
) },
6444 { VEX_LEN_TABLE (VEX_LEN_0F3A06
) },
6447 { "vroundps", { XM
, EXx
, Ib
}, PREFIX_DATA
},
6448 { "vroundpd", { XM
, EXx
, Ib
}, PREFIX_DATA
},
6449 { "vroundss", { XMScalar
, VexScalar
, EXxmm_md
, Ib
}, PREFIX_DATA
},
6450 { "vroundsd", { XMScalar
, VexScalar
, EXxmm_mq
, Ib
}, PREFIX_DATA
},
6451 { "vblendps", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
6452 { "vblendpd", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
6453 { "vpblendw", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
6454 { "vpalignr", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
6460 { VEX_LEN_TABLE (VEX_LEN_0F3A14
) },
6461 { VEX_LEN_TABLE (VEX_LEN_0F3A15
) },
6462 { VEX_LEN_TABLE (VEX_LEN_0F3A16
) },
6463 { VEX_LEN_TABLE (VEX_LEN_0F3A17
) },
6465 { VEX_LEN_TABLE (VEX_LEN_0F3A18
) },
6466 { VEX_LEN_TABLE (VEX_LEN_0F3A19
) },
6470 { VEX_W_TABLE (VEX_W_0F3A1D
) },
6474 { VEX_LEN_TABLE (VEX_LEN_0F3A20
) },
6475 { VEX_LEN_TABLE (VEX_LEN_0F3A21
) },
6476 { VEX_LEN_TABLE (VEX_LEN_0F3A22
) },
6492 { VEX_LEN_TABLE (VEX_LEN_0F3A30
) },
6493 { VEX_LEN_TABLE (VEX_LEN_0F3A31
) },
6494 { VEX_LEN_TABLE (VEX_LEN_0F3A32
) },
6495 { VEX_LEN_TABLE (VEX_LEN_0F3A33
) },
6501 { VEX_LEN_TABLE (VEX_LEN_0F3A38
) },
6502 { VEX_LEN_TABLE (VEX_LEN_0F3A39
) },
6510 { "vdpps", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
6511 { VEX_LEN_TABLE (VEX_LEN_0F3A41
) },
6512 { "vmpsadbw", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
6514 { "vpclmulqdq", { XM
, Vex
, EXx
, PCLMUL
}, PREFIX_DATA
},
6516 { VEX_LEN_TABLE (VEX_LEN_0F3A46
) },
6519 { "vpermil2ps", { XM
, Vex
, EXx
, XMVexI4
, VexI4
}, PREFIX_DATA
},
6520 { "vpermil2pd", { XM
, Vex
, EXx
, XMVexI4
, VexI4
}, PREFIX_DATA
},
6521 { VEX_W_TABLE (VEX_W_0F3A4A
) },
6522 { VEX_W_TABLE (VEX_W_0F3A4B
) },
6523 { VEX_W_TABLE (VEX_W_0F3A4C
) },
6541 { "vfmaddsubps", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6542 { "vfmaddsubpd", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6543 { "vfmsubaddps", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6544 { "vfmsubaddpd", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6546 { VEX_LEN_TABLE (VEX_LEN_0F3A60
) },
6547 { VEX_LEN_TABLE (VEX_LEN_0F3A61
) },
6548 { VEX_LEN_TABLE (VEX_LEN_0F3A62
) },
6549 { VEX_LEN_TABLE (VEX_LEN_0F3A63
) },
6555 { "vfmaddps", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6556 { "vfmaddpd", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6557 { "vfmaddss", { XMScalar
, VexScalar
, EXxmm_md
, XMVexScalarI4
}, PREFIX_DATA
},
6558 { "vfmaddsd", { XMScalar
, VexScalar
, EXxmm_mq
, XMVexScalarI4
}, PREFIX_DATA
},
6559 { "vfmsubps", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6560 { "vfmsubpd", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6561 { "vfmsubss", { XMScalar
, VexScalar
, EXxmm_md
, XMVexScalarI4
}, PREFIX_DATA
},
6562 { "vfmsubsd", { XMScalar
, VexScalar
, EXxmm_mq
, XMVexScalarI4
}, PREFIX_DATA
},
6573 { "vfnmaddps", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6574 { "vfnmaddpd", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6575 { "vfnmaddss", { XMScalar
, VexScalar
, EXxmm_md
, XMVexScalarI4
}, PREFIX_DATA
},
6576 { "vfnmaddsd", { XMScalar
, VexScalar
, EXxmm_mq
, XMVexScalarI4
}, PREFIX_DATA
},
6577 { "vfnmsubps", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6578 { "vfnmsubpd", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6579 { "vfnmsubss", { XMScalar
, VexScalar
, EXxmm_md
, XMVexScalarI4
}, PREFIX_DATA
},
6580 { "vfnmsubsd", { XMScalar
, VexScalar
, EXxmm_mq
, XMVexScalarI4
}, PREFIX_DATA
},
6669 { VEX_W_TABLE (VEX_W_0F3ACE
) },
6670 { VEX_W_TABLE (VEX_W_0F3ACF
) },
6688 { VEX_LEN_TABLE (VEX_LEN_0F3ADF
) },
6708 { VEX_LEN_TABLE (VEX_LEN_0F3AF0
) },
6728 #include "i386-dis-evex.h"
6730 static const struct dis386 vex_len_table
[][2] = {
6731 /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */
6733 { "vmovlpX", { XM
, Vex
, EXq
}, 0 },
6736 /* VEX_LEN_0F12_P_0_M_1 */
6738 { "vmovhlps", { XM
, Vex
, EXq
}, 0 },
6741 /* VEX_LEN_0F13_M_0 */
6743 { "vmovlpX", { EXq
, XM
}, PREFIX_OPCODE
},
6746 /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */
6748 { "vmovhpX", { XM
, Vex
, EXq
}, 0 },
6751 /* VEX_LEN_0F16_P_0_M_1 */
6753 { "vmovlhps", { XM
, Vex
, EXq
}, 0 },
6756 /* VEX_LEN_0F17_M_0 */
6758 { "vmovhpX", { EXq
, XM
}, PREFIX_OPCODE
},
6764 { MOD_TABLE (MOD_VEX_0F41_L_1
) },
6770 { MOD_TABLE (MOD_VEX_0F42_L_1
) },
6775 { MOD_TABLE (MOD_VEX_0F44_L_0
) },
6781 { MOD_TABLE (MOD_VEX_0F45_L_1
) },
6787 { MOD_TABLE (MOD_VEX_0F46_L_1
) },
6793 { MOD_TABLE (MOD_VEX_0F47_L_1
) },
6799 { MOD_TABLE (MOD_VEX_0F4A_L_1
) },
6805 { MOD_TABLE (MOD_VEX_0F4B_L_1
) },
6810 { "vmovK", { XMScalar
, Edq
}, PREFIX_DATA
},
6815 { "vzeroupper", { XX
}, 0 },
6816 { "vzeroall", { XX
}, 0 },
6819 /* VEX_LEN_0F7E_P_1 */
6821 { "vmovq", { XMScalar
, EXxmm_mq
}, 0 },
6824 /* VEX_LEN_0F7E_P_2 */
6826 { "vmovK", { Edq
, XMScalar
}, 0 },
6831 { VEX_W_TABLE (VEX_W_0F90_L_0
) },
6836 { MOD_TABLE (MOD_VEX_0F91_L_0
) },
6841 { MOD_TABLE (MOD_VEX_0F92_L_0
) },
6846 { MOD_TABLE (MOD_VEX_0F93_L_0
) },
6851 { MOD_TABLE (MOD_VEX_0F98_L_0
) },
6856 { MOD_TABLE (MOD_VEX_0F99_L_0
) },
6859 /* VEX_LEN_0FAE_R_2_M_0 */
6861 { "vldmxcsr", { Md
}, 0 },
6864 /* VEX_LEN_0FAE_R_3_M_0 */
6866 { "vstmxcsr", { Md
}, 0 },
6871 { "vpinsrw", { XM
, Vex
, Edqw
, Ib
}, PREFIX_DATA
},
6876 { "vpextrw", { Gdq
, XS
, Ib
}, PREFIX_DATA
},
6881 { "vmovq", { EXqS
, XMScalar
}, PREFIX_DATA
},
6886 { "vmaskmovdqu", { XM
, XS
}, PREFIX_DATA
},
6889 /* VEX_LEN_0F3816 */
6892 { VEX_W_TABLE (VEX_W_0F3816_L_1
) },
6895 /* VEX_LEN_0F3819 */
6898 { VEX_W_TABLE (VEX_W_0F3819_L_1
) },
6901 /* VEX_LEN_0F381A_M_0 */
6904 { VEX_W_TABLE (VEX_W_0F381A_M_0_L_1
) },
6907 /* VEX_LEN_0F3836 */
6910 { VEX_W_TABLE (VEX_W_0F3836
) },
6913 /* VEX_LEN_0F3841 */
6915 { "vphminposuw", { XM
, EXx
}, PREFIX_DATA
},
6918 /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_0 */
6920 { "ldtilecfg", { M
}, 0 },
6923 /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0 */
6925 { "tilerelease", { Skip_MODRM
}, 0 },
6928 /* VEX_LEN_0F3849_X86_64_P_2_W_0_M_0 */
6930 { "sttilecfg", { M
}, 0 },
6933 /* VEX_LEN_0F3849_X86_64_P_3_W_0_M_0 */
6935 { "tilezero", { TMM
, Skip_MODRM
}, 0 },
6938 /* VEX_LEN_0F384B_X86_64_P_1_W_0_M_0 */
6940 { "tilestored", { MVexSIBMEM
, TMM
}, 0 },
6942 /* VEX_LEN_0F384B_X86_64_P_2_W_0_M_0 */
6944 { "tileloaddt1", { TMM
, MVexSIBMEM
}, 0 },
6947 /* VEX_LEN_0F384B_X86_64_P_3_W_0_M_0 */
6949 { "tileloadd", { TMM
, MVexSIBMEM
}, 0 },
6952 /* VEX_LEN_0F385A_M_0 */
6955 { VEX_W_TABLE (VEX_W_0F385A_M_0_L_0
) },
6958 /* VEX_LEN_0F385C_X86_64_P_1_W_0_M_0 */
6960 { "tdpbf16ps", { TMM
, EXtmm
, VexTmm
}, 0 },
6963 /* VEX_LEN_0F385E_X86_64_P_0_W_0_M_0 */
6965 { "tdpbuud", {TMM
, EXtmm
, VexTmm
}, 0 },
6968 /* VEX_LEN_0F385E_X86_64_P_1_W_0_M_0 */
6970 { "tdpbsud", {TMM
, EXtmm
, VexTmm
}, 0 },
6973 /* VEX_LEN_0F385E_X86_64_P_2_W_0_M_0 */
6975 { "tdpbusd", {TMM
, EXtmm
, VexTmm
}, 0 },
6978 /* VEX_LEN_0F385E_X86_64_P_3_W_0_M_0 */
6980 { "tdpbssd", {TMM
, EXtmm
, VexTmm
}, 0 },
6983 /* VEX_LEN_0F38DB */
6985 { "vaesimc", { XM
, EXx
}, PREFIX_DATA
},
6988 /* VEX_LEN_0F38F2 */
6990 { "andnS", { Gdq
, VexGdq
, Edq
}, PREFIX_OPCODE
},
6993 /* VEX_LEN_0F38F3 */
6995 { REG_TABLE(REG_VEX_0F38F3_L_0
) },
6998 /* VEX_LEN_0F38F5 */
7000 { PREFIX_TABLE(PREFIX_VEX_0F38F5_L_0
) },
7003 /* VEX_LEN_0F38F6 */
7005 { PREFIX_TABLE(PREFIX_VEX_0F38F6_L_0
) },
7008 /* VEX_LEN_0F38F7 */
7010 { PREFIX_TABLE(PREFIX_VEX_0F38F7_L_0
) },
7013 /* VEX_LEN_0F3A00 */
7016 { VEX_W_TABLE (VEX_W_0F3A00_L_1
) },
7019 /* VEX_LEN_0F3A01 */
7022 { VEX_W_TABLE (VEX_W_0F3A01_L_1
) },
7025 /* VEX_LEN_0F3A06 */
7028 { VEX_W_TABLE (VEX_W_0F3A06_L_1
) },
7031 /* VEX_LEN_0F3A14 */
7033 { "vpextrb", { Edqb
, XM
, Ib
}, PREFIX_DATA
},
7036 /* VEX_LEN_0F3A15 */
7038 { "vpextrw", { Edqw
, XM
, Ib
}, PREFIX_DATA
},
7041 /* VEX_LEN_0F3A16 */
7043 { "vpextrK", { Edq
, XM
, Ib
}, PREFIX_DATA
},
7046 /* VEX_LEN_0F3A17 */
7048 { "vextractps", { Edqd
, XM
, Ib
}, PREFIX_DATA
},
7051 /* VEX_LEN_0F3A18 */
7054 { VEX_W_TABLE (VEX_W_0F3A18_L_1
) },
7057 /* VEX_LEN_0F3A19 */
7060 { VEX_W_TABLE (VEX_W_0F3A19_L_1
) },
7063 /* VEX_LEN_0F3A20 */
7065 { "vpinsrb", { XM
, Vex
, Edqb
, Ib
}, PREFIX_DATA
},
7068 /* VEX_LEN_0F3A21 */
7070 { "vinsertps", { XM
, Vex
, EXd
, Ib
}, PREFIX_DATA
},
7073 /* VEX_LEN_0F3A22 */
7075 { "vpinsrK", { XM
, Vex
, Edq
, Ib
}, PREFIX_DATA
},
7078 /* VEX_LEN_0F3A30 */
7080 { MOD_TABLE (MOD_VEX_0F3A30_L_0
) },
7083 /* VEX_LEN_0F3A31 */
7085 { MOD_TABLE (MOD_VEX_0F3A31_L_0
) },
7088 /* VEX_LEN_0F3A32 */
7090 { MOD_TABLE (MOD_VEX_0F3A32_L_0
) },
7093 /* VEX_LEN_0F3A33 */
7095 { MOD_TABLE (MOD_VEX_0F3A33_L_0
) },
7098 /* VEX_LEN_0F3A38 */
7101 { VEX_W_TABLE (VEX_W_0F3A38_L_1
) },
7104 /* VEX_LEN_0F3A39 */
7107 { VEX_W_TABLE (VEX_W_0F3A39_L_1
) },
7110 /* VEX_LEN_0F3A41 */
7112 { "vdppd", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
7115 /* VEX_LEN_0F3A46 */
7118 { VEX_W_TABLE (VEX_W_0F3A46_L_1
) },
7121 /* VEX_LEN_0F3A60 */
7123 { "vpcmpestrm!%LQ", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7126 /* VEX_LEN_0F3A61 */
7128 { "vpcmpestri!%LQ", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7131 /* VEX_LEN_0F3A62 */
7133 { "vpcmpistrm", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7136 /* VEX_LEN_0F3A63 */
7138 { "vpcmpistri", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7141 /* VEX_LEN_0F3ADF */
7143 { "vaeskeygenassist", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7146 /* VEX_LEN_0F3AF0 */
7148 { PREFIX_TABLE (PREFIX_VEX_0F3AF0_L_0
) },
7151 /* VEX_LEN_0FXOP_08_85 */
7153 { VEX_W_TABLE (VEX_W_0FXOP_08_85_L_0
) },
7156 /* VEX_LEN_0FXOP_08_86 */
7158 { VEX_W_TABLE (VEX_W_0FXOP_08_86_L_0
) },
7161 /* VEX_LEN_0FXOP_08_87 */
7163 { VEX_W_TABLE (VEX_W_0FXOP_08_87_L_0
) },
7166 /* VEX_LEN_0FXOP_08_8E */
7168 { VEX_W_TABLE (VEX_W_0FXOP_08_8E_L_0
) },
7171 /* VEX_LEN_0FXOP_08_8F */
7173 { VEX_W_TABLE (VEX_W_0FXOP_08_8F_L_0
) },
7176 /* VEX_LEN_0FXOP_08_95 */
7178 { VEX_W_TABLE (VEX_W_0FXOP_08_95_L_0
) },
7181 /* VEX_LEN_0FXOP_08_96 */
7183 { VEX_W_TABLE (VEX_W_0FXOP_08_96_L_0
) },
7186 /* VEX_LEN_0FXOP_08_97 */
7188 { VEX_W_TABLE (VEX_W_0FXOP_08_97_L_0
) },
7191 /* VEX_LEN_0FXOP_08_9E */
7193 { VEX_W_TABLE (VEX_W_0FXOP_08_9E_L_0
) },
7196 /* VEX_LEN_0FXOP_08_9F */
7198 { VEX_W_TABLE (VEX_W_0FXOP_08_9F_L_0
) },
7201 /* VEX_LEN_0FXOP_08_A3 */
7203 { "vpperm", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7206 /* VEX_LEN_0FXOP_08_A6 */
7208 { VEX_W_TABLE (VEX_W_0FXOP_08_A6_L_0
) },
7211 /* VEX_LEN_0FXOP_08_B6 */
7213 { VEX_W_TABLE (VEX_W_0FXOP_08_B6_L_0
) },
7216 /* VEX_LEN_0FXOP_08_C0 */
7218 { VEX_W_TABLE (VEX_W_0FXOP_08_C0_L_0
) },
7221 /* VEX_LEN_0FXOP_08_C1 */
7223 { VEX_W_TABLE (VEX_W_0FXOP_08_C1_L_0
) },
7226 /* VEX_LEN_0FXOP_08_C2 */
7228 { VEX_W_TABLE (VEX_W_0FXOP_08_C2_L_0
) },
7231 /* VEX_LEN_0FXOP_08_C3 */
7233 { VEX_W_TABLE (VEX_W_0FXOP_08_C3_L_0
) },
7236 /* VEX_LEN_0FXOP_08_CC */
7238 { VEX_W_TABLE (VEX_W_0FXOP_08_CC_L_0
) },
7241 /* VEX_LEN_0FXOP_08_CD */
7243 { VEX_W_TABLE (VEX_W_0FXOP_08_CD_L_0
) },
7246 /* VEX_LEN_0FXOP_08_CE */
7248 { VEX_W_TABLE (VEX_W_0FXOP_08_CE_L_0
) },
7251 /* VEX_LEN_0FXOP_08_CF */
7253 { VEX_W_TABLE (VEX_W_0FXOP_08_CF_L_0
) },
7256 /* VEX_LEN_0FXOP_08_EC */
7258 { VEX_W_TABLE (VEX_W_0FXOP_08_EC_L_0
) },
7261 /* VEX_LEN_0FXOP_08_ED */
7263 { VEX_W_TABLE (VEX_W_0FXOP_08_ED_L_0
) },
7266 /* VEX_LEN_0FXOP_08_EE */
7268 { VEX_W_TABLE (VEX_W_0FXOP_08_EE_L_0
) },
7271 /* VEX_LEN_0FXOP_08_EF */
7273 { VEX_W_TABLE (VEX_W_0FXOP_08_EF_L_0
) },
7276 /* VEX_LEN_0FXOP_09_01 */
7278 { REG_TABLE (REG_XOP_09_01_L_0
) },
7281 /* VEX_LEN_0FXOP_09_02 */
7283 { REG_TABLE (REG_XOP_09_02_L_0
) },
7286 /* VEX_LEN_0FXOP_09_12_M_1 */
7288 { REG_TABLE (REG_XOP_09_12_M_1_L_0
) },
7291 /* VEX_LEN_0FXOP_09_82_W_0 */
7293 { "vfrczss", { XM
, EXd
}, 0 },
7296 /* VEX_LEN_0FXOP_09_83_W_0 */
7298 { "vfrczsd", { XM
, EXq
}, 0 },
7301 /* VEX_LEN_0FXOP_09_90 */
7303 { "vprotb", { XM
, EXx
, VexW
}, 0 },
7306 /* VEX_LEN_0FXOP_09_91 */
7308 { "vprotw", { XM
, EXx
, VexW
}, 0 },
7311 /* VEX_LEN_0FXOP_09_92 */
7313 { "vprotd", { XM
, EXx
, VexW
}, 0 },
7316 /* VEX_LEN_0FXOP_09_93 */
7318 { "vprotq", { XM
, EXx
, VexW
}, 0 },
7321 /* VEX_LEN_0FXOP_09_94 */
7323 { "vpshlb", { XM
, EXx
, VexW
}, 0 },
7326 /* VEX_LEN_0FXOP_09_95 */
7328 { "vpshlw", { XM
, EXx
, VexW
}, 0 },
7331 /* VEX_LEN_0FXOP_09_96 */
7333 { "vpshld", { XM
, EXx
, VexW
}, 0 },
7336 /* VEX_LEN_0FXOP_09_97 */
7338 { "vpshlq", { XM
, EXx
, VexW
}, 0 },
7341 /* VEX_LEN_0FXOP_09_98 */
7343 { "vpshab", { XM
, EXx
, VexW
}, 0 },
7346 /* VEX_LEN_0FXOP_09_99 */
7348 { "vpshaw", { XM
, EXx
, VexW
}, 0 },
7351 /* VEX_LEN_0FXOP_09_9A */
7353 { "vpshad", { XM
, EXx
, VexW
}, 0 },
7356 /* VEX_LEN_0FXOP_09_9B */
7358 { "vpshaq", { XM
, EXx
, VexW
}, 0 },
7361 /* VEX_LEN_0FXOP_09_C1 */
7363 { VEX_W_TABLE (VEX_W_0FXOP_09_C1_L_0
) },
7366 /* VEX_LEN_0FXOP_09_C2 */
7368 { VEX_W_TABLE (VEX_W_0FXOP_09_C2_L_0
) },
7371 /* VEX_LEN_0FXOP_09_C3 */
7373 { VEX_W_TABLE (VEX_W_0FXOP_09_C3_L_0
) },
7376 /* VEX_LEN_0FXOP_09_C6 */
7378 { VEX_W_TABLE (VEX_W_0FXOP_09_C6_L_0
) },
7381 /* VEX_LEN_0FXOP_09_C7 */
7383 { VEX_W_TABLE (VEX_W_0FXOP_09_C7_L_0
) },
7386 /* VEX_LEN_0FXOP_09_CB */
7388 { VEX_W_TABLE (VEX_W_0FXOP_09_CB_L_0
) },
7391 /* VEX_LEN_0FXOP_09_D1 */
7393 { VEX_W_TABLE (VEX_W_0FXOP_09_D1_L_0
) },
7396 /* VEX_LEN_0FXOP_09_D2 */
7398 { VEX_W_TABLE (VEX_W_0FXOP_09_D2_L_0
) },
7401 /* VEX_LEN_0FXOP_09_D3 */
7403 { VEX_W_TABLE (VEX_W_0FXOP_09_D3_L_0
) },
7406 /* VEX_LEN_0FXOP_09_D6 */
7408 { VEX_W_TABLE (VEX_W_0FXOP_09_D6_L_0
) },
7411 /* VEX_LEN_0FXOP_09_D7 */
7413 { VEX_W_TABLE (VEX_W_0FXOP_09_D7_L_0
) },
7416 /* VEX_LEN_0FXOP_09_DB */
7418 { VEX_W_TABLE (VEX_W_0FXOP_09_DB_L_0
) },
7421 /* VEX_LEN_0FXOP_09_E1 */
7423 { VEX_W_TABLE (VEX_W_0FXOP_09_E1_L_0
) },
7426 /* VEX_LEN_0FXOP_09_E2 */
7428 { VEX_W_TABLE (VEX_W_0FXOP_09_E2_L_0
) },
7431 /* VEX_LEN_0FXOP_09_E3 */
7433 { VEX_W_TABLE (VEX_W_0FXOP_09_E3_L_0
) },
7436 /* VEX_LEN_0FXOP_0A_12 */
7438 { REG_TABLE (REG_XOP_0A_12_L_0
) },
7442 #include "i386-dis-evex-len.h"
7444 static const struct dis386 vex_w_table
[][2] = {
7446 /* VEX_W_0F41_L_1_M_1 */
7447 { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_M_1_W_0
) },
7448 { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_M_1_W_1
) },
7451 /* VEX_W_0F42_L_1_M_1 */
7452 { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_M_1_W_0
) },
7453 { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_M_1_W_1
) },
7456 /* VEX_W_0F44_L_0_M_1 */
7457 { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_M_1_W_0
) },
7458 { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_M_1_W_1
) },
7461 /* VEX_W_0F45_L_1_M_1 */
7462 { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_M_1_W_0
) },
7463 { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_M_1_W_1
) },
7466 /* VEX_W_0F46_L_1_M_1 */
7467 { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_M_1_W_0
) },
7468 { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_M_1_W_1
) },
7471 /* VEX_W_0F47_L_1_M_1 */
7472 { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_M_1_W_0
) },
7473 { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_M_1_W_1
) },
7476 /* VEX_W_0F4A_L_1_M_1 */
7477 { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_M_1_W_0
) },
7478 { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_M_1_W_1
) },
7481 /* VEX_W_0F4B_L_1_M_1 */
7482 { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_M_1_W_0
) },
7483 { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_M_1_W_1
) },
7486 /* VEX_W_0F90_L_0 */
7487 { PREFIX_TABLE (PREFIX_VEX_0F90_L_0_W_0
) },
7488 { PREFIX_TABLE (PREFIX_VEX_0F90_L_0_W_1
) },
7491 /* VEX_W_0F91_L_0_M_0 */
7492 { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_M_0_W_0
) },
7493 { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_M_0_W_1
) },
7496 /* VEX_W_0F92_L_0_M_1 */
7497 { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_M_1_W_0
) },
7498 { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_M_1_W_1
) },
7501 /* VEX_W_0F93_L_0_M_1 */
7502 { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_M_1_W_0
) },
7503 { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_M_1_W_1
) },
7506 /* VEX_W_0F98_L_0_M_1 */
7507 { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_M_1_W_0
) },
7508 { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_M_1_W_1
) },
7511 /* VEX_W_0F99_L_0_M_1 */
7512 { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_M_1_W_0
) },
7513 { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_M_1_W_1
) },
7517 { "vpermilps", { XM
, Vex
, EXx
}, PREFIX_DATA
},
7521 { "vpermilpd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
7525 { "vtestps", { XM
, EXx
}, PREFIX_DATA
},
7529 { "vtestpd", { XM
, EXx
}, PREFIX_DATA
},
7533 { "vcvtph2ps", { XM
, EXxmmq
}, PREFIX_DATA
},
7536 /* VEX_W_0F3816_L_1 */
7537 { "vpermps", { XM
, Vex
, EXx
}, PREFIX_DATA
},
7541 { "vbroadcastss", { XM
, EXxmm_md
}, PREFIX_DATA
},
7544 /* VEX_W_0F3819_L_1 */
7545 { "vbroadcastsd", { XM
, EXxmm_mq
}, PREFIX_DATA
},
7548 /* VEX_W_0F381A_M_0_L_1 */
7549 { "vbroadcastf128", { XM
, Mxmm
}, PREFIX_DATA
},
7552 /* VEX_W_0F382C_M_0 */
7553 { "vmaskmovps", { XM
, Vex
, Mx
}, PREFIX_DATA
},
7556 /* VEX_W_0F382D_M_0 */
7557 { "vmaskmovpd", { XM
, Vex
, Mx
}, PREFIX_DATA
},
7560 /* VEX_W_0F382E_M_0 */
7561 { "vmaskmovps", { Mx
, Vex
, XM
}, PREFIX_DATA
},
7564 /* VEX_W_0F382F_M_0 */
7565 { "vmaskmovpd", { Mx
, Vex
, XM
}, PREFIX_DATA
},
7569 { "vpermd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
7573 { "vpsravd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
7576 /* VEX_W_0F3849_X86_64_P_0 */
7577 { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_0_W_0
) },
7580 /* VEX_W_0F3849_X86_64_P_2 */
7581 { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_2_W_0
) },
7584 /* VEX_W_0F3849_X86_64_P_3 */
7585 { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_3_W_0
) },
7588 /* VEX_W_0F384B_X86_64_P_1 */
7589 { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_1_W_0
) },
7592 /* VEX_W_0F384B_X86_64_P_2 */
7593 { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_2_W_0
) },
7596 /* VEX_W_0F384B_X86_64_P_3 */
7597 { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_3_W_0
) },
7601 { "%XV vpdpbusd", { XM
, Vex
, EXx
}, 0 },
7605 { "%XV vpdpbusds", { XM
, Vex
, EXx
}, 0 },
7609 { "%XV vpdpwssd", { XM
, Vex
, EXx
}, 0 },
7613 { "%XV vpdpwssds", { XM
, Vex
, EXx
}, 0 },
7617 { "vpbroadcastd", { XM
, EXxmm_md
}, PREFIX_DATA
},
7621 { "vpbroadcastq", { XM
, EXxmm_mq
}, PREFIX_DATA
},
7624 /* VEX_W_0F385A_M_0_L_0 */
7625 { "vbroadcasti128", { XM
, Mxmm
}, PREFIX_DATA
},
7628 /* VEX_W_0F385C_X86_64_P_1 */
7629 { MOD_TABLE (MOD_VEX_0F385C_X86_64_P_1_W_0
) },
7632 /* VEX_W_0F385E_X86_64_P_0 */
7633 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_0_W_0
) },
7636 /* VEX_W_0F385E_X86_64_P_1 */
7637 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_1_W_0
) },
7640 /* VEX_W_0F385E_X86_64_P_2 */
7641 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_2_W_0
) },
7644 /* VEX_W_0F385E_X86_64_P_3 */
7645 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_3_W_0
) },
7649 { "vpbroadcastb", { XM
, EXxmm_mb
}, PREFIX_DATA
},
7653 { "vpbroadcastw", { XM
, EXxmm_mw
}, PREFIX_DATA
},
7657 { "vgf2p8mulb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
7660 /* VEX_W_0F3A00_L_1 */
7662 { "vpermq", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7665 /* VEX_W_0F3A01_L_1 */
7667 { "vpermpd", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7671 { "vpblendd", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
7675 { "vpermilps", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7679 { "vpermilpd", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7682 /* VEX_W_0F3A06_L_1 */
7683 { "vperm2f128", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
7686 /* VEX_W_0F3A18_L_1 */
7687 { "vinsertf128", { XM
, Vex
, EXxmm
, Ib
}, PREFIX_DATA
},
7690 /* VEX_W_0F3A19_L_1 */
7691 { "vextractf128", { EXxmm
, XM
, Ib
}, PREFIX_DATA
},
7695 { "vcvtps2ph", { EXxmmq
, XM
, EXxEVexS
, Ib
}, PREFIX_DATA
},
7698 /* VEX_W_0F3A38_L_1 */
7699 { "vinserti128", { XM
, Vex
, EXxmm
, Ib
}, PREFIX_DATA
},
7702 /* VEX_W_0F3A39_L_1 */
7703 { "vextracti128", { EXxmm
, XM
, Ib
}, PREFIX_DATA
},
7706 /* VEX_W_0F3A46_L_1 */
7707 { "vperm2i128", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
7711 { "vblendvps", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
7715 { "vblendvpd", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
7719 { "vpblendvb", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
7724 { "vgf2p8affineqb", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
7729 { "vgf2p8affineinvqb", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
7731 /* VEX_W_0FXOP_08_85_L_0 */
7733 { "vpmacssww", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7735 /* VEX_W_0FXOP_08_86_L_0 */
7737 { "vpmacsswd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7739 /* VEX_W_0FXOP_08_87_L_0 */
7741 { "vpmacssdql", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7743 /* VEX_W_0FXOP_08_8E_L_0 */
7745 { "vpmacssdd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7747 /* VEX_W_0FXOP_08_8F_L_0 */
7749 { "vpmacssdqh", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7751 /* VEX_W_0FXOP_08_95_L_0 */
7753 { "vpmacsww", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7755 /* VEX_W_0FXOP_08_96_L_0 */
7757 { "vpmacswd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7759 /* VEX_W_0FXOP_08_97_L_0 */
7761 { "vpmacsdql", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7763 /* VEX_W_0FXOP_08_9E_L_0 */
7765 { "vpmacsdd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7767 /* VEX_W_0FXOP_08_9F_L_0 */
7769 { "vpmacsdqh", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7771 /* VEX_W_0FXOP_08_A6_L_0 */
7773 { "vpmadcsswd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7775 /* VEX_W_0FXOP_08_B6_L_0 */
7777 { "vpmadcswd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7779 /* VEX_W_0FXOP_08_C0_L_0 */
7781 { "vprotb", { XM
, EXx
, Ib
}, 0 },
7783 /* VEX_W_0FXOP_08_C1_L_0 */
7785 { "vprotw", { XM
, EXx
, Ib
}, 0 },
7787 /* VEX_W_0FXOP_08_C2_L_0 */
7789 { "vprotd", { XM
, EXx
, Ib
}, 0 },
7791 /* VEX_W_0FXOP_08_C3_L_0 */
7793 { "vprotq", { XM
, EXx
, Ib
}, 0 },
7795 /* VEX_W_0FXOP_08_CC_L_0 */
7797 { "vpcomb", { XM
, Vex
, EXx
, VPCOM
}, 0 },
7799 /* VEX_W_0FXOP_08_CD_L_0 */
7801 { "vpcomw", { XM
, Vex
, EXx
, VPCOM
}, 0 },
7803 /* VEX_W_0FXOP_08_CE_L_0 */
7805 { "vpcomd", { XM
, Vex
, EXx
, VPCOM
}, 0 },
7807 /* VEX_W_0FXOP_08_CF_L_0 */
7809 { "vpcomq", { XM
, Vex
, EXx
, VPCOM
}, 0 },
7811 /* VEX_W_0FXOP_08_EC_L_0 */
7813 { "vpcomub", { XM
, Vex
, EXx
, VPCOM
}, 0 },
7815 /* VEX_W_0FXOP_08_ED_L_0 */
7817 { "vpcomuw", { XM
, Vex
, EXx
, VPCOM
}, 0 },
7819 /* VEX_W_0FXOP_08_EE_L_0 */
7821 { "vpcomud", { XM
, Vex
, EXx
, VPCOM
}, 0 },
7823 /* VEX_W_0FXOP_08_EF_L_0 */
7825 { "vpcomuq", { XM
, Vex
, EXx
, VPCOM
}, 0 },
7827 /* VEX_W_0FXOP_09_80 */
7829 { "vfrczps", { XM
, EXx
}, 0 },
7831 /* VEX_W_0FXOP_09_81 */
7833 { "vfrczpd", { XM
, EXx
}, 0 },
7835 /* VEX_W_0FXOP_09_82 */
7837 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_82_W_0
) },
7839 /* VEX_W_0FXOP_09_83 */
7841 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_83_W_0
) },
7843 /* VEX_W_0FXOP_09_C1_L_0 */
7845 { "vphaddbw", { XM
, EXxmm
}, 0 },
7847 /* VEX_W_0FXOP_09_C2_L_0 */
7849 { "vphaddbd", { XM
, EXxmm
}, 0 },
7851 /* VEX_W_0FXOP_09_C3_L_0 */
7853 { "vphaddbq", { XM
, EXxmm
}, 0 },
7855 /* VEX_W_0FXOP_09_C6_L_0 */
7857 { "vphaddwd", { XM
, EXxmm
}, 0 },
7859 /* VEX_W_0FXOP_09_C7_L_0 */
7861 { "vphaddwq", { XM
, EXxmm
}, 0 },
7863 /* VEX_W_0FXOP_09_CB_L_0 */
7865 { "vphadddq", { XM
, EXxmm
}, 0 },
7867 /* VEX_W_0FXOP_09_D1_L_0 */
7869 { "vphaddubw", { XM
, EXxmm
}, 0 },
7871 /* VEX_W_0FXOP_09_D2_L_0 */
7873 { "vphaddubd", { XM
, EXxmm
}, 0 },
7875 /* VEX_W_0FXOP_09_D3_L_0 */
7877 { "vphaddubq", { XM
, EXxmm
}, 0 },
7879 /* VEX_W_0FXOP_09_D6_L_0 */
7881 { "vphadduwd", { XM
, EXxmm
}, 0 },
7883 /* VEX_W_0FXOP_09_D7_L_0 */
7885 { "vphadduwq", { XM
, EXxmm
}, 0 },
7887 /* VEX_W_0FXOP_09_DB_L_0 */
7889 { "vphaddudq", { XM
, EXxmm
}, 0 },
7891 /* VEX_W_0FXOP_09_E1_L_0 */
7893 { "vphsubbw", { XM
, EXxmm
}, 0 },
7895 /* VEX_W_0FXOP_09_E2_L_0 */
7897 { "vphsubwd", { XM
, EXxmm
}, 0 },
7899 /* VEX_W_0FXOP_09_E3_L_0 */
7901 { "vphsubdq", { XM
, EXxmm
}, 0 },
7904 #include "i386-dis-evex-w.h"
7907 static const struct dis386 mod_table
[][2] = {
7910 { "bound{S|}", { Gv
, Ma
}, 0 },
7911 { EVEX_TABLE (EVEX_0F
) },
7915 { "leaS", { Gv
, M
}, 0 },
7919 { "lesS", { Gv
, Mp
}, 0 },
7920 { VEX_C4_TABLE (VEX_0F
) },
7924 { "ldsS", { Gv
, Mp
}, 0 },
7925 { VEX_C5_TABLE (VEX_0F
) },
7930 { RM_TABLE (RM_C6_REG_7
) },
7935 { RM_TABLE (RM_C7_REG_7
) },
7939 { "{l|}call^", { indirEp
}, 0 },
7943 { "{l|}jmp^", { indirEp
}, 0 },
7946 /* MOD_0F01_REG_0 */
7947 { X86_64_TABLE (X86_64_0F01_REG_0
) },
7948 { RM_TABLE (RM_0F01_REG_0
) },
7951 /* MOD_0F01_REG_1 */
7952 { X86_64_TABLE (X86_64_0F01_REG_1
) },
7953 { RM_TABLE (RM_0F01_REG_1
) },
7956 /* MOD_0F01_REG_2 */
7957 { X86_64_TABLE (X86_64_0F01_REG_2
) },
7958 { RM_TABLE (RM_0F01_REG_2
) },
7961 /* MOD_0F01_REG_3 */
7962 { X86_64_TABLE (X86_64_0F01_REG_3
) },
7963 { RM_TABLE (RM_0F01_REG_3
) },
7966 /* MOD_0F01_REG_5 */
7967 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0
) },
7968 { RM_TABLE (RM_0F01_REG_5_MOD_3
) },
7971 /* MOD_0F01_REG_7 */
7972 { "invlpg", { Mb
}, 0 },
7973 { RM_TABLE (RM_0F01_REG_7_MOD_3
) },
7976 /* MOD_0F12_PREFIX_0 */
7977 { "movlpX", { XM
, EXq
}, 0 },
7978 { "movhlps", { XM
, EXq
}, 0 },
7981 /* MOD_0F12_PREFIX_2 */
7982 { "movlpX", { XM
, EXq
}, 0 },
7986 { "movlpX", { EXq
, XM
}, PREFIX_OPCODE
},
7989 /* MOD_0F16_PREFIX_0 */
7990 { "movhpX", { XM
, EXq
}, 0 },
7991 { "movlhps", { XM
, EXq
}, 0 },
7994 /* MOD_0F16_PREFIX_2 */
7995 { "movhpX", { XM
, EXq
}, 0 },
7999 { "movhpX", { EXq
, XM
}, PREFIX_OPCODE
},
8002 /* MOD_0F18_REG_0 */
8003 { "prefetchnta", { Mb
}, 0 },
8004 { "nopQ", { Ev
}, 0 },
8007 /* MOD_0F18_REG_1 */
8008 { "prefetcht0", { Mb
}, 0 },
8009 { "nopQ", { Ev
}, 0 },
8012 /* MOD_0F18_REG_2 */
8013 { "prefetcht1", { Mb
}, 0 },
8014 { "nopQ", { Ev
}, 0 },
8017 /* MOD_0F18_REG_3 */
8018 { "prefetcht2", { Mb
}, 0 },
8019 { "nopQ", { Ev
}, 0 },
8022 /* MOD_0F1A_PREFIX_0 */
8023 { "bndldx", { Gbnd
, Mv_bnd
}, 0 },
8024 { "nopQ", { Ev
}, 0 },
8027 /* MOD_0F1B_PREFIX_0 */
8028 { "bndstx", { Mv_bnd
, Gbnd
}, 0 },
8029 { "nopQ", { Ev
}, 0 },
8032 /* MOD_0F1B_PREFIX_1 */
8033 { "bndmk", { Gbnd
, Mv_bnd
}, 0 },
8034 { "nopQ", { Ev
}, PREFIX_IGNORED
},
8037 /* MOD_0F1C_PREFIX_0 */
8038 { REG_TABLE (REG_0F1C_P_0_MOD_0
) },
8039 { "nopQ", { Ev
}, 0 },
8042 /* MOD_0F1E_PREFIX_1 */
8043 { "nopQ", { Ev
}, PREFIX_IGNORED
},
8044 { REG_TABLE (REG_0F1E_P_1_MOD_3
) },
8047 /* MOD_0F2B_PREFIX_0 */
8048 {"movntps", { Mx
, XM
}, PREFIX_OPCODE
},
8051 /* MOD_0F2B_PREFIX_1 */
8052 {"movntss", { Md
, XM
}, PREFIX_OPCODE
},
8055 /* MOD_0F2B_PREFIX_2 */
8056 {"movntpd", { Mx
, XM
}, PREFIX_OPCODE
},
8059 /* MOD_0F2B_PREFIX_3 */
8060 {"movntsd", { Mq
, XM
}, PREFIX_OPCODE
},
8065 { "movmskpX", { Gdq
, XS
}, PREFIX_OPCODE
},
8070 { REG_TABLE (REG_0F71_MOD_0
) },
8075 { REG_TABLE (REG_0F72_MOD_0
) },
8080 { REG_TABLE (REG_0F73_MOD_0
) },
8083 /* MOD_0FAE_REG_0 */
8084 { "fxsave", { FXSAVE
}, 0 },
8085 { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3
) },
8088 /* MOD_0FAE_REG_1 */
8089 { "fxrstor", { FXSAVE
}, 0 },
8090 { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3
) },
8093 /* MOD_0FAE_REG_2 */
8094 { "ldmxcsr", { Md
}, 0 },
8095 { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3
) },
8098 /* MOD_0FAE_REG_3 */
8099 { "stmxcsr", { Md
}, 0 },
8100 { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3
) },
8103 /* MOD_0FAE_REG_4 */
8104 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0
) },
8105 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3
) },
8108 /* MOD_0FAE_REG_5 */
8109 { "xrstor", { FXSAVE
}, PREFIX_OPCODE
},
8110 { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3
) },
8113 /* MOD_0FAE_REG_6 */
8114 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0
) },
8115 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3
) },
8118 /* MOD_0FAE_REG_7 */
8119 { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0
) },
8120 { RM_TABLE (RM_0FAE_REG_7_MOD_3
) },
8124 { "lssS", { Gv
, Mp
}, 0 },
8128 { "lfsS", { Gv
, Mp
}, 0 },
8132 { "lgsS", { Gv
, Mp
}, 0 },
8136 { "movntiS", { Edq
, Gdq
}, PREFIX_OPCODE
},
8139 /* MOD_0FC7_REG_3 */
8140 { "xrstors", { FXSAVE
}, 0 },
8143 /* MOD_0FC7_REG_4 */
8144 { "xsavec", { FXSAVE
}, 0 },
8147 /* MOD_0FC7_REG_5 */
8148 { "xsaves", { FXSAVE
}, 0 },
8151 /* MOD_0FC7_REG_6 */
8152 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0
) },
8153 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3
) }
8156 /* MOD_0FC7_REG_7 */
8157 { "vmptrst", { Mq
}, 0 },
8158 { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3
) }
8163 { "pmovmskb", { Gdq
, MS
}, 0 },
8166 /* MOD_0FE7_PREFIX_2 */
8167 { "movntdq", { Mx
, XM
}, 0 },
8170 /* MOD_0FF0_PREFIX_3 */
8171 { "lddqu", { XM
, M
}, 0 },
8175 { "movntdqa", { XM
, Mx
}, PREFIX_DATA
},
8178 /* MOD_0F38DC_PREFIX_1 */
8179 { "aesenc128kl", { XM
, M
}, 0 },
8180 { "loadiwkey", { XM
, EXx
}, 0 },
8183 /* MOD_0F38DD_PREFIX_1 */
8184 { "aesdec128kl", { XM
, M
}, 0 },
8187 /* MOD_0F38DE_PREFIX_1 */
8188 { "aesenc256kl", { XM
, M
}, 0 },
8191 /* MOD_0F38DF_PREFIX_1 */
8192 { "aesdec256kl", { XM
, M
}, 0 },
8196 { "wrussK", { M
, Gdq
}, PREFIX_DATA
},
8199 /* MOD_0F38F6_PREFIX_0 */
8200 { "wrssK", { M
, Gdq
}, PREFIX_OPCODE
},
8203 /* MOD_0F38F8_PREFIX_1 */
8204 { "enqcmds", { Gva
, M
}, PREFIX_OPCODE
},
8207 /* MOD_0F38F8_PREFIX_2 */
8208 { "movdir64b", { Gva
, M
}, PREFIX_OPCODE
},
8211 /* MOD_0F38F8_PREFIX_3 */
8212 { "enqcmd", { Gva
, M
}, PREFIX_OPCODE
},
8216 { "movdiri", { Edq
, Gdq
}, PREFIX_OPCODE
},
8219 /* MOD_0F38FA_PREFIX_1 */
8221 { "encodekey128", { Gd
, Ed
}, 0 },
8224 /* MOD_0F38FB_PREFIX_1 */
8226 { "encodekey256", { Gd
, Ed
}, 0 },
8229 /* MOD_0F3A0F_PREFIX_1 */
8231 { REG_TABLE (REG_0F3A0F_PREFIX_1_MOD_3
) },
8234 /* MOD_VEX_0F12_PREFIX_0 */
8235 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0
) },
8236 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1
) },
8239 /* MOD_VEX_0F12_PREFIX_2 */
8240 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0
) },
8244 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0
) },
8247 /* MOD_VEX_0F16_PREFIX_0 */
8248 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0
) },
8249 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1
) },
8252 /* MOD_VEX_0F16_PREFIX_2 */
8253 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0
) },
8257 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0
) },
8261 { "vmovntpX", { Mx
, XM
}, PREFIX_OPCODE
},
8264 /* MOD_VEX_0F41_L_1 */
8266 { VEX_W_TABLE (VEX_W_0F41_L_1_M_1
) },
8269 /* MOD_VEX_0F42_L_1 */
8271 { VEX_W_TABLE (VEX_W_0F42_L_1_M_1
) },
8274 /* MOD_VEX_0F44_L_0 */
8276 { VEX_W_TABLE (VEX_W_0F44_L_0_M_1
) },
8279 /* MOD_VEX_0F45_L_1 */
8281 { VEX_W_TABLE (VEX_W_0F45_L_1_M_1
) },
8284 /* MOD_VEX_0F46_L_1 */
8286 { VEX_W_TABLE (VEX_W_0F46_L_1_M_1
) },
8289 /* MOD_VEX_0F47_L_1 */
8291 { VEX_W_TABLE (VEX_W_0F47_L_1_M_1
) },
8294 /* MOD_VEX_0F4A_L_1 */
8296 { VEX_W_TABLE (VEX_W_0F4A_L_1_M_1
) },
8299 /* MOD_VEX_0F4B_L_1 */
8301 { VEX_W_TABLE (VEX_W_0F4B_L_1_M_1
) },
8306 { "vmovmskpX", { Gdq
, XS
}, PREFIX_OPCODE
},
8311 { REG_TABLE (REG_VEX_0F71_M_0
) },
8316 { REG_TABLE (REG_VEX_0F72_M_0
) },
8321 { REG_TABLE (REG_VEX_0F73_M_0
) },
8324 /* MOD_VEX_0F91_L_0 */
8325 { VEX_W_TABLE (VEX_W_0F91_L_0_M_0
) },
8328 /* MOD_VEX_0F92_L_0 */
8330 { VEX_W_TABLE (VEX_W_0F92_L_0_M_1
) },
8333 /* MOD_VEX_0F93_L_0 */
8335 { VEX_W_TABLE (VEX_W_0F93_L_0_M_1
) },
8338 /* MOD_VEX_0F98_L_0 */
8340 { VEX_W_TABLE (VEX_W_0F98_L_0_M_1
) },
8343 /* MOD_VEX_0F99_L_0 */
8345 { VEX_W_TABLE (VEX_W_0F99_L_0_M_1
) },
8348 /* MOD_VEX_0FAE_REG_2 */
8349 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0
) },
8352 /* MOD_VEX_0FAE_REG_3 */
8353 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0
) },
8358 { "vpmovmskb", { Gdq
, XS
}, PREFIX_DATA
},
8362 { "vmovntdq", { Mx
, XM
}, PREFIX_DATA
},
8365 /* MOD_VEX_0FF0_PREFIX_3 */
8366 { "vlddqu", { XM
, M
}, 0 },
8369 /* MOD_VEX_0F381A */
8370 { VEX_LEN_TABLE (VEX_LEN_0F381A_M_0
) },
8373 /* MOD_VEX_0F382A */
8374 { "vmovntdqa", { XM
, Mx
}, PREFIX_DATA
},
8377 /* MOD_VEX_0F382C */
8378 { VEX_W_TABLE (VEX_W_0F382C_M_0
) },
8381 /* MOD_VEX_0F382D */
8382 { VEX_W_TABLE (VEX_W_0F382D_M_0
) },
8385 /* MOD_VEX_0F382E */
8386 { VEX_W_TABLE (VEX_W_0F382E_M_0
) },
8389 /* MOD_VEX_0F382F */
8390 { VEX_W_TABLE (VEX_W_0F382F_M_0
) },
8393 /* MOD_VEX_0F3849_X86_64_P_0_W_0 */
8394 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0
) },
8395 { REG_TABLE (REG_VEX_0F3849_X86_64_P_0_W_0_M_1
) },
8398 /* MOD_VEX_0F3849_X86_64_P_2_W_0 */
8399 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0
) },
8402 /* MOD_VEX_0F3849_X86_64_P_3_W_0 */
8404 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0
) },
8407 /* MOD_VEX_0F384B_X86_64_P_1_W_0 */
8408 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0
) },
8411 /* MOD_VEX_0F384B_X86_64_P_2_W_0 */
8412 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0
) },
8415 /* MOD_VEX_0F384B_X86_64_P_3_W_0 */
8416 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0
) },
8419 /* MOD_VEX_0F385A */
8420 { VEX_LEN_TABLE (VEX_LEN_0F385A_M_0
) },
8423 /* MOD_VEX_0F385C_X86_64_P_1_W_0 */
8425 { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0
) },
8428 /* MOD_VEX_0F385E_X86_64_P_0_W_0 */
8430 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0
) },
8433 /* MOD_VEX_0F385E_X86_64_P_1_W_0 */
8435 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0
) },
8438 /* MOD_VEX_0F385E_X86_64_P_2_W_0 */
8440 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0
) },
8443 /* MOD_VEX_0F385E_X86_64_P_3_W_0 */
8445 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0
) },
8448 /* MOD_VEX_0F388C */
8449 { "vpmaskmov%DQ", { XM
, Vex
, Mx
}, PREFIX_DATA
},
8452 /* MOD_VEX_0F388E */
8453 { "vpmaskmov%DQ", { Mx
, Vex
, XM
}, PREFIX_DATA
},
8456 /* MOD_VEX_0F3A30_L_0 */
8458 { "kshiftr%BW", { MaskG
, MaskE
, Ib
}, PREFIX_DATA
},
8461 /* MOD_VEX_0F3A31_L_0 */
8463 { "kshiftr%DQ", { MaskG
, MaskE
, Ib
}, PREFIX_DATA
},
8466 /* MOD_VEX_0F3A32_L_0 */
8468 { "kshiftl%BW", { MaskG
, MaskE
, Ib
}, PREFIX_DATA
},
8471 /* MOD_VEX_0F3A33_L_0 */
8473 { "kshiftl%DQ", { MaskG
, MaskE
, Ib
}, PREFIX_DATA
},
8478 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_12_M_1
) },
8481 #include "i386-dis-evex-mod.h"
8484 static const struct dis386 rm_table
[][8] = {
8487 { "xabort", { Skip_MODRM
, Ib
}, 0 },
8491 { "xbeginT", { Skip_MODRM
, Jdqw
}, 0 },
8495 { "enclv", { Skip_MODRM
}, 0 },
8496 { "vmcall", { Skip_MODRM
}, 0 },
8497 { "vmlaunch", { Skip_MODRM
}, 0 },
8498 { "vmresume", { Skip_MODRM
}, 0 },
8499 { "vmxoff", { Skip_MODRM
}, 0 },
8500 { "pconfig", { Skip_MODRM
}, 0 },
8504 { "monitor", { { OP_Monitor
, 0 } }, 0 },
8505 { "mwait", { { OP_Mwait
, 0 } }, 0 },
8506 { "clac", { Skip_MODRM
}, 0 },
8507 { "stac", { Skip_MODRM
}, 0 },
8508 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_4
) },
8509 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_5
) },
8510 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_6
) },
8511 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_7
) },
8515 { "xgetbv", { Skip_MODRM
}, 0 },
8516 { "xsetbv", { Skip_MODRM
}, 0 },
8519 { "vmfunc", { Skip_MODRM
}, 0 },
8520 { "xend", { Skip_MODRM
}, 0 },
8521 { "xtest", { Skip_MODRM
}, 0 },
8522 { "enclu", { Skip_MODRM
}, 0 },
8526 { "vmrun", { Skip_MODRM
}, 0 },
8527 { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1
) },
8528 { "vmload", { Skip_MODRM
}, 0 },
8529 { "vmsave", { Skip_MODRM
}, 0 },
8530 { "stgi", { Skip_MODRM
}, 0 },
8531 { "clgi", { Skip_MODRM
}, 0 },
8532 { "skinit", { Skip_MODRM
}, 0 },
8533 { "invlpga", { Skip_MODRM
}, 0 },
8536 /* RM_0F01_REG_5_MOD_3 */
8537 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0
) },
8538 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1
) },
8539 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2
) },
8541 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_4
) },
8542 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_5
) },
8543 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_6
) },
8544 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_7
) },
8547 /* RM_0F01_REG_7_MOD_3 */
8548 { "swapgs", { Skip_MODRM
}, 0 },
8549 { "rdtscp", { Skip_MODRM
}, 0 },
8550 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2
) },
8551 { "mwaitx", { { OP_Mwait
, eBX_reg
} }, PREFIX_OPCODE
},
8552 { "clzero", { Skip_MODRM
}, 0 },
8553 { "rdpru", { Skip_MODRM
}, 0 },
8554 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_6
) },
8555 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_7
) },
8558 /* RM_0F1E_P_1_MOD_3_REG_7 */
8559 { "nopQ", { Ev
}, PREFIX_IGNORED
},
8560 { "nopQ", { Ev
}, PREFIX_IGNORED
},
8561 { "endbr64", { Skip_MODRM
}, 0 },
8562 { "endbr32", { Skip_MODRM
}, 0 },
8563 { "nopQ", { Ev
}, PREFIX_IGNORED
},
8564 { "nopQ", { Ev
}, PREFIX_IGNORED
},
8565 { "nopQ", { Ev
}, PREFIX_IGNORED
},
8566 { "nopQ", { Ev
}, PREFIX_IGNORED
},
8569 /* RM_0FAE_REG_6_MOD_3 */
8570 { "mfence", { Skip_MODRM
}, 0 },
8573 /* RM_0FAE_REG_7_MOD_3 */
8574 { "sfence", { Skip_MODRM
}, 0 },
8577 /* RM_0F3A0F_P_1_MOD_3_REG_0 */
8578 { "hreset", { Skip_MODRM
, Ib
}, 0 },
8581 /* RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0 */
8582 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0
) },
8586 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
8588 /* We use the high bit to indicate different name for the same
8590 #define REP_PREFIX (0xf3 | 0x100)
8591 #define XACQUIRE_PREFIX (0xf2 | 0x200)
8592 #define XRELEASE_PREFIX (0xf3 | 0x400)
8593 #define BND_PREFIX (0xf2 | 0x400)
8594 #define NOTRACK_PREFIX (0x3e | 0x100)
8596 /* Remember if the current op is a jump instruction. */
8597 static bool op_is_jump
= false;
8602 int newrex
, i
, length
;
8607 last_lock_prefix
= -1;
8608 last_repz_prefix
= -1;
8609 last_repnz_prefix
= -1;
8610 last_data_prefix
= -1;
8611 last_addr_prefix
= -1;
8612 last_rex_prefix
= -1;
8613 last_seg_prefix
= -1;
8615 active_seg_prefix
= 0;
8616 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
8617 all_prefixes
[i
] = 0;
8620 /* The maximum instruction length is 15bytes. */
8621 while (length
< MAX_CODE_LENGTH
- 1)
8623 FETCH_DATA (the_info
, codep
+ 1);
8627 /* REX prefixes family. */
8644 if (address_mode
== mode_64bit
)
8648 last_rex_prefix
= i
;
8651 prefixes
|= PREFIX_REPZ
;
8652 last_repz_prefix
= i
;
8655 prefixes
|= PREFIX_REPNZ
;
8656 last_repnz_prefix
= i
;
8659 prefixes
|= PREFIX_LOCK
;
8660 last_lock_prefix
= i
;
8663 prefixes
|= PREFIX_CS
;
8664 last_seg_prefix
= i
;
8666 if (address_mode
!= mode_64bit
)
8667 active_seg_prefix
= PREFIX_CS
;
8671 prefixes
|= PREFIX_SS
;
8672 last_seg_prefix
= i
;
8674 if (address_mode
!= mode_64bit
)
8675 active_seg_prefix
= PREFIX_SS
;
8679 prefixes
|= PREFIX_DS
;
8680 last_seg_prefix
= i
;
8682 if (address_mode
!= mode_64bit
)
8683 active_seg_prefix
= PREFIX_DS
;
8687 prefixes
|= PREFIX_ES
;
8688 last_seg_prefix
= i
;
8690 if (address_mode
!= mode_64bit
)
8691 active_seg_prefix
= PREFIX_ES
;
8695 prefixes
|= PREFIX_FS
;
8696 last_seg_prefix
= i
;
8697 active_seg_prefix
= PREFIX_FS
;
8700 prefixes
|= PREFIX_GS
;
8701 last_seg_prefix
= i
;
8702 active_seg_prefix
= PREFIX_GS
;
8705 prefixes
|= PREFIX_DATA
;
8706 last_data_prefix
= i
;
8709 prefixes
|= PREFIX_ADDR
;
8710 last_addr_prefix
= i
;
8713 /* fwait is really an instruction. If there are prefixes
8714 before the fwait, they belong to the fwait, *not* to the
8715 following instruction. */
8717 if (prefixes
|| rex
)
8719 prefixes
|= PREFIX_FWAIT
;
8721 /* This ensures that the previous REX prefixes are noticed
8722 as unused prefixes, as in the return case below. */
8726 prefixes
= PREFIX_FWAIT
;
8731 /* Rex is ignored when followed by another prefix. */
8737 if (*codep
!= FWAIT_OPCODE
)
8738 all_prefixes
[i
++] = *codep
;
8746 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
8750 prefix_name (int pref
, int sizeflag
)
8752 static const char *rexes
[16] =
8757 "rex.XB", /* 0x43 */
8759 "rex.RB", /* 0x45 */
8760 "rex.RX", /* 0x46 */
8761 "rex.RXB", /* 0x47 */
8763 "rex.WB", /* 0x49 */
8764 "rex.WX", /* 0x4a */
8765 "rex.WXB", /* 0x4b */
8766 "rex.WR", /* 0x4c */
8767 "rex.WRB", /* 0x4d */
8768 "rex.WRX", /* 0x4e */
8769 "rex.WRXB", /* 0x4f */
8774 /* REX prefixes family. */
8791 return rexes
[pref
- 0x40];
8811 return (sizeflag
& DFLAG
) ? "data16" : "data32";
8813 if (address_mode
== mode_64bit
)
8814 return (sizeflag
& AFLAG
) ? "addr32" : "addr64";
8816 return (sizeflag
& AFLAG
) ? "addr16" : "addr32";
8821 case XACQUIRE_PREFIX
:
8823 case XRELEASE_PREFIX
:
8827 case NOTRACK_PREFIX
:
8834 static char op_out
[MAX_OPERANDS
][100];
8835 static int op_ad
, op_index
[MAX_OPERANDS
];
8836 static int two_source_ops
;
8837 static bfd_vma op_address
[MAX_OPERANDS
];
8838 static bfd_vma op_riprel
[MAX_OPERANDS
];
8839 static bfd_vma start_pc
;
8842 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
8843 * (see topic "Redundant prefixes" in the "Differences from 8086"
8844 * section of the "Virtual 8086 Mode" chapter.)
8845 * 'pc' should be the address of this instruction, it will
8846 * be used to print the target address if this is a relative jump or call
8847 * The function returns the length of this instruction in bytes.
8850 static char intel_syntax
;
8851 static char intel_mnemonic
= !SYSV386_COMPAT
;
8852 static char open_char
;
8853 static char close_char
;
8854 static char separator_char
;
8855 static char scale_char
;
8863 static enum x86_64_isa isa64
;
8865 /* Here for backwards compatibility. When gdb stops using
8866 print_insn_i386_att and print_insn_i386_intel these functions can
8867 disappear, and print_insn_i386 be merged into print_insn. */
8869 print_insn_i386_att (bfd_vma pc
, disassemble_info
*info
)
8873 return print_insn (pc
, info
);
8877 print_insn_i386_intel (bfd_vma pc
, disassemble_info
*info
)
8881 return print_insn (pc
, info
);
8885 print_insn_i386 (bfd_vma pc
, disassemble_info
*info
)
8889 return print_insn (pc
, info
);
8893 print_i386_disassembler_options (FILE *stream
)
8895 fprintf (stream
, _("\n\
8896 The following i386/x86-64 specific disassembler options are supported for use\n\
8897 with the -M switch (multiple options should be separated by commas):\n"));
8899 fprintf (stream
, _(" x86-64 Disassemble in 64bit mode\n"));
8900 fprintf (stream
, _(" i386 Disassemble in 32bit mode\n"));
8901 fprintf (stream
, _(" i8086 Disassemble in 16bit mode\n"));
8902 fprintf (stream
, _(" att Display instruction in AT&T syntax\n"));
8903 fprintf (stream
, _(" intel Display instruction in Intel syntax\n"));
8904 fprintf (stream
, _(" att-mnemonic\n"
8905 " Display instruction in AT&T mnemonic\n"));
8906 fprintf (stream
, _(" intel-mnemonic\n"
8907 " Display instruction in Intel mnemonic\n"));
8908 fprintf (stream
, _(" addr64 Assume 64bit address size\n"));
8909 fprintf (stream
, _(" addr32 Assume 32bit address size\n"));
8910 fprintf (stream
, _(" addr16 Assume 16bit address size\n"));
8911 fprintf (stream
, _(" data32 Assume 32bit data size\n"));
8912 fprintf (stream
, _(" data16 Assume 16bit data size\n"));
8913 fprintf (stream
, _(" suffix Always display instruction suffix in AT&T syntax\n"));
8914 fprintf (stream
, _(" amd64 Display instruction in AMD64 ISA\n"));
8915 fprintf (stream
, _(" intel64 Display instruction in Intel64 ISA\n"));
8919 static const struct dis386 bad_opcode
= { "(bad)", { XX
}, 0 };
8921 /* Get a pointer to struct dis386 with a valid name. */
8923 static const struct dis386
*
8924 get_valid_dis386 (const struct dis386
*dp
, disassemble_info
*info
)
8926 int vindex
, vex_table_index
;
8928 if (dp
->name
!= NULL
)
8931 switch (dp
->op
[0].bytemode
)
8934 dp
= ®_table
[dp
->op
[1].bytemode
][modrm
.reg
];
8938 vindex
= modrm
.mod
== 0x3 ? 1 : 0;
8939 dp
= &mod_table
[dp
->op
[1].bytemode
][vindex
];
8943 dp
= &rm_table
[dp
->op
[1].bytemode
][modrm
.rm
];
8946 case USE_PREFIX_TABLE
:
8949 /* The prefix in VEX is implicit. */
8955 case REPE_PREFIX_OPCODE
:
8958 case DATA_PREFIX_OPCODE
:
8961 case REPNE_PREFIX_OPCODE
:
8971 int last_prefix
= -1;
8974 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
8975 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
8977 if ((prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0)
8979 if (last_repz_prefix
> last_repnz_prefix
)
8982 prefix
= PREFIX_REPZ
;
8983 last_prefix
= last_repz_prefix
;
8988 prefix
= PREFIX_REPNZ
;
8989 last_prefix
= last_repnz_prefix
;
8992 /* Check if prefix should be ignored. */
8993 if ((((prefix_table
[dp
->op
[1].bytemode
][vindex
].prefix_requirement
8994 & PREFIX_IGNORED
) >> PREFIX_IGNORED_SHIFT
)
8996 && !prefix_table
[dp
->op
[1].bytemode
][vindex
].name
)
9000 if (vindex
== 0 && (prefixes
& PREFIX_DATA
) != 0)
9003 prefix
= PREFIX_DATA
;
9004 last_prefix
= last_data_prefix
;
9009 used_prefixes
|= prefix
;
9010 all_prefixes
[last_prefix
] = 0;
9013 dp
= &prefix_table
[dp
->op
[1].bytemode
][vindex
];
9016 case USE_X86_64_TABLE
:
9017 vindex
= address_mode
== mode_64bit
? 1 : 0;
9018 dp
= &x86_64_table
[dp
->op
[1].bytemode
][vindex
];
9021 case USE_3BYTE_TABLE
:
9022 FETCH_DATA (info
, codep
+ 2);
9024 dp
= &three_byte_table
[dp
->op
[1].bytemode
][vindex
];
9026 modrm
.mod
= (*codep
>> 6) & 3;
9027 modrm
.reg
= (*codep
>> 3) & 7;
9028 modrm
.rm
= *codep
& 7;
9031 case USE_VEX_LEN_TABLE
:
9041 /* This allows re-using in particular table entries where only
9042 128-bit operand size (VEX.L=0 / EVEX.L'L=0) are valid. */
9055 dp
= &vex_len_table
[dp
->op
[1].bytemode
][vindex
];
9058 case USE_EVEX_LEN_TABLE
:
9078 dp
= &evex_len_table
[dp
->op
[1].bytemode
][vindex
];
9081 case USE_XOP_8F_TABLE
:
9082 FETCH_DATA (info
, codep
+ 3);
9083 rex
= ~(*codep
>> 5) & 0x7;
9085 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
9086 switch ((*codep
& 0x1f))
9092 vex_table_index
= XOP_08
;
9095 vex_table_index
= XOP_09
;
9098 vex_table_index
= XOP_0A
;
9102 vex
.w
= *codep
& 0x80;
9103 if (vex
.w
&& address_mode
== mode_64bit
)
9106 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
9107 if (address_mode
!= mode_64bit
)
9109 /* In 16/32-bit mode REX_B is silently ignored. */
9113 vex
.length
= (*codep
& 0x4) ? 256 : 128;
9114 switch ((*codep
& 0x3))
9119 vex
.prefix
= DATA_PREFIX_OPCODE
;
9122 vex
.prefix
= REPE_PREFIX_OPCODE
;
9125 vex
.prefix
= REPNE_PREFIX_OPCODE
;
9131 dp
= &xop_table
[vex_table_index
][vindex
];
9134 FETCH_DATA (info
, codep
+ 1);
9135 modrm
.mod
= (*codep
>> 6) & 3;
9136 modrm
.reg
= (*codep
>> 3) & 7;
9137 modrm
.rm
= *codep
& 7;
9139 /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid
9140 having to decode the bits for every otherwise valid encoding. */
9145 case USE_VEX_C4_TABLE
:
9147 FETCH_DATA (info
, codep
+ 3);
9148 rex
= ~(*codep
>> 5) & 0x7;
9149 switch ((*codep
& 0x1f))
9155 vex_table_index
= VEX_0F
;
9158 vex_table_index
= VEX_0F38
;
9161 vex_table_index
= VEX_0F3A
;
9165 vex
.w
= *codep
& 0x80;
9166 if (address_mode
== mode_64bit
)
9173 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
9174 is ignored, other REX bits are 0 and the highest bit in
9175 VEX.vvvv is also ignored (but we mustn't clear it here). */
9178 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
9179 vex
.length
= (*codep
& 0x4) ? 256 : 128;
9180 switch ((*codep
& 0x3))
9185 vex
.prefix
= DATA_PREFIX_OPCODE
;
9188 vex
.prefix
= REPE_PREFIX_OPCODE
;
9191 vex
.prefix
= REPNE_PREFIX_OPCODE
;
9197 dp
= &vex_table
[vex_table_index
][vindex
];
9199 /* There is no MODRM byte for VEX0F 77. */
9200 if (vex_table_index
!= VEX_0F
|| vindex
!= 0x77)
9202 FETCH_DATA (info
, codep
+ 1);
9203 modrm
.mod
= (*codep
>> 6) & 3;
9204 modrm
.reg
= (*codep
>> 3) & 7;
9205 modrm
.rm
= *codep
& 7;
9209 case USE_VEX_C5_TABLE
:
9211 FETCH_DATA (info
, codep
+ 2);
9212 rex
= (*codep
& 0x80) ? 0 : REX_R
;
9214 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
9216 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
9217 vex
.length
= (*codep
& 0x4) ? 256 : 128;
9218 switch ((*codep
& 0x3))
9223 vex
.prefix
= DATA_PREFIX_OPCODE
;
9226 vex
.prefix
= REPE_PREFIX_OPCODE
;
9229 vex
.prefix
= REPNE_PREFIX_OPCODE
;
9235 dp
= &vex_table
[dp
->op
[1].bytemode
][vindex
];
9237 /* There is no MODRM byte for VEX 77. */
9240 FETCH_DATA (info
, codep
+ 1);
9241 modrm
.mod
= (*codep
>> 6) & 3;
9242 modrm
.reg
= (*codep
>> 3) & 7;
9243 modrm
.rm
= *codep
& 7;
9247 case USE_VEX_W_TABLE
:
9251 dp
= &vex_w_table
[dp
->op
[1].bytemode
][vex
.w
? 1 : 0];
9254 case USE_EVEX_TABLE
:
9258 FETCH_DATA (info
, codep
+ 4);
9259 /* The first byte after 0x62. */
9260 rex
= ~(*codep
>> 5) & 0x7;
9261 vex
.r
= *codep
& 0x10;
9262 switch ((*codep
& 0xf))
9267 vex_table_index
= EVEX_0F
;
9270 vex_table_index
= EVEX_0F38
;
9273 vex_table_index
= EVEX_0F3A
;
9277 /* The second byte after 0x62. */
9279 vex
.w
= *codep
& 0x80;
9280 if (vex
.w
&& address_mode
== mode_64bit
)
9283 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
9286 if (!(*codep
& 0x4))
9289 switch ((*codep
& 0x3))
9294 vex
.prefix
= DATA_PREFIX_OPCODE
;
9297 vex
.prefix
= REPE_PREFIX_OPCODE
;
9300 vex
.prefix
= REPNE_PREFIX_OPCODE
;
9304 /* The third byte after 0x62. */
9307 /* Remember the static rounding bits. */
9308 vex
.ll
= (*codep
>> 5) & 3;
9309 vex
.b
= (*codep
& 0x10) != 0;
9311 vex
.v
= *codep
& 0x8;
9312 vex
.mask_register_specifier
= *codep
& 0x7;
9313 vex
.zeroing
= *codep
& 0x80;
9315 if (address_mode
!= mode_64bit
)
9317 /* In 16/32-bit mode silently ignore following bits. */
9326 dp
= &evex_table
[vex_table_index
][vindex
];
9328 FETCH_DATA (info
, codep
+ 1);
9329 modrm
.mod
= (*codep
>> 6) & 3;
9330 modrm
.reg
= (*codep
>> 3) & 7;
9331 modrm
.rm
= *codep
& 7;
9333 /* Set vector length. */
9334 if (modrm
.mod
== 3 && vex
.b
)
9363 if (dp
->name
!= NULL
)
9366 return get_valid_dis386 (dp
, info
);
9370 get_sib (disassemble_info
*info
, int sizeflag
)
9372 /* If modrm.mod == 3, operand must be register. */
9374 && ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
9378 FETCH_DATA (info
, codep
+ 2);
9379 sib
.index
= (codep
[1] >> 3) & 7;
9380 sib
.scale
= (codep
[1] >> 6) & 3;
9381 sib
.base
= codep
[1] & 7;
9386 print_insn (bfd_vma pc
, disassemble_info
*info
)
9388 const struct dis386
*dp
;
9390 char *op_txt
[MAX_OPERANDS
];
9392 int sizeflag
, orig_sizeflag
;
9394 struct dis_private priv
;
9397 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
9398 if ((info
->mach
& bfd_mach_i386_i386
) != 0)
9399 address_mode
= mode_32bit
;
9400 else if (info
->mach
== bfd_mach_i386_i8086
)
9402 address_mode
= mode_16bit
;
9403 priv
.orig_sizeflag
= 0;
9406 address_mode
= mode_64bit
;
9408 if (intel_syntax
== (char) -1)
9409 intel_syntax
= (info
->mach
& bfd_mach_i386_intel_syntax
) != 0;
9411 for (p
= info
->disassembler_options
; p
!= NULL
; )
9413 if (startswith (p
, "amd64"))
9415 else if (startswith (p
, "intel64"))
9417 else if (startswith (p
, "x86-64"))
9419 address_mode
= mode_64bit
;
9420 priv
.orig_sizeflag
|= AFLAG
| DFLAG
;
9422 else if (startswith (p
, "i386"))
9424 address_mode
= mode_32bit
;
9425 priv
.orig_sizeflag
|= AFLAG
| DFLAG
;
9427 else if (startswith (p
, "i8086"))
9429 address_mode
= mode_16bit
;
9430 priv
.orig_sizeflag
&= ~(AFLAG
| DFLAG
);
9432 else if (startswith (p
, "intel"))
9435 if (startswith (p
+ 5, "-mnemonic"))
9438 else if (startswith (p
, "att"))
9441 if (startswith (p
+ 3, "-mnemonic"))
9444 else if (startswith (p
, "addr"))
9446 if (address_mode
== mode_64bit
)
9448 if (p
[4] == '3' && p
[5] == '2')
9449 priv
.orig_sizeflag
&= ~AFLAG
;
9450 else if (p
[4] == '6' && p
[5] == '4')
9451 priv
.orig_sizeflag
|= AFLAG
;
9455 if (p
[4] == '1' && p
[5] == '6')
9456 priv
.orig_sizeflag
&= ~AFLAG
;
9457 else if (p
[4] == '3' && p
[5] == '2')
9458 priv
.orig_sizeflag
|= AFLAG
;
9461 else if (startswith (p
, "data"))
9463 if (p
[4] == '1' && p
[5] == '6')
9464 priv
.orig_sizeflag
&= ~DFLAG
;
9465 else if (p
[4] == '3' && p
[5] == '2')
9466 priv
.orig_sizeflag
|= DFLAG
;
9468 else if (startswith (p
, "suffix"))
9469 priv
.orig_sizeflag
|= SUFFIX_ALWAYS
;
9471 p
= strchr (p
, ',');
9476 if (address_mode
== mode_64bit
&& sizeof (bfd_vma
) < 8)
9478 (*info
->fprintf_func
) (info
->stream
,
9479 _("64-bit address is disabled"));
9485 names64
= intel_names64
;
9486 names32
= intel_names32
;
9487 names16
= intel_names16
;
9488 names8
= intel_names8
;
9489 names8rex
= intel_names8rex
;
9490 names_seg
= intel_names_seg
;
9491 names_mm
= intel_names_mm
;
9492 names_bnd
= intel_names_bnd
;
9493 names_xmm
= intel_names_xmm
;
9494 names_ymm
= intel_names_ymm
;
9495 names_zmm
= intel_names_zmm
;
9496 names_tmm
= intel_names_tmm
;
9497 index64
= intel_index64
;
9498 index32
= intel_index32
;
9499 names_mask
= intel_names_mask
;
9500 index16
= intel_index16
;
9503 separator_char
= '+';
9508 names64
= att_names64
;
9509 names32
= att_names32
;
9510 names16
= att_names16
;
9511 names8
= att_names8
;
9512 names8rex
= att_names8rex
;
9513 names_seg
= att_names_seg
;
9514 names_mm
= att_names_mm
;
9515 names_bnd
= att_names_bnd
;
9516 names_xmm
= att_names_xmm
;
9517 names_ymm
= att_names_ymm
;
9518 names_zmm
= att_names_zmm
;
9519 names_tmm
= att_names_tmm
;
9520 index64
= att_index64
;
9521 index32
= att_index32
;
9522 names_mask
= att_names_mask
;
9523 index16
= att_index16
;
9526 separator_char
= ',';
9530 /* The output looks better if we put 7 bytes on a line, since that
9531 puts most long word instructions on a single line. Use 8 bytes
9533 if ((info
->mach
& bfd_mach_l1om
) != 0)
9534 info
->bytes_per_line
= 8;
9536 info
->bytes_per_line
= 7;
9538 info
->private_data
= &priv
;
9539 priv
.max_fetched
= priv
.the_buffer
;
9540 priv
.insn_start
= pc
;
9543 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
9551 start_codep
= priv
.the_buffer
;
9552 codep
= priv
.the_buffer
;
9554 if (OPCODES_SIGSETJMP (priv
.bailout
) != 0)
9558 /* Getting here means we tried for data but didn't get it. That
9559 means we have an incomplete instruction of some sort. Just
9560 print the first byte as a prefix or a .byte pseudo-op. */
9561 if (codep
> priv
.the_buffer
)
9563 name
= prefix_name (priv
.the_buffer
[0], priv
.orig_sizeflag
);
9565 (*info
->fprintf_func
) (info
->stream
, "%s", name
);
9568 /* Just print the first byte as a .byte instruction. */
9569 (*info
->fprintf_func
) (info
->stream
, ".byte 0x%x",
9570 (unsigned int) priv
.the_buffer
[0]);
9580 sizeflag
= priv
.orig_sizeflag
;
9582 if (!ckprefix () || rex_used
)
9584 /* Too many prefixes or unused REX prefixes. */
9586 i
< (int) ARRAY_SIZE (all_prefixes
) && all_prefixes
[i
];
9588 (*info
->fprintf_func
) (info
->stream
, "%s%s",
9590 prefix_name (all_prefixes
[i
], sizeflag
));
9596 FETCH_DATA (info
, codep
+ 1);
9597 two_source_ops
= (*codep
== 0x62) || (*codep
== 0xc8);
9599 if (((prefixes
& PREFIX_FWAIT
)
9600 && ((*codep
< 0xd8) || (*codep
> 0xdf))))
9602 /* Handle prefixes before fwait. */
9603 for (i
= 0; i
< fwait_prefix
&& all_prefixes
[i
];
9605 (*info
->fprintf_func
) (info
->stream
, "%s ",
9606 prefix_name (all_prefixes
[i
], sizeflag
));
9607 (*info
->fprintf_func
) (info
->stream
, "fwait");
9613 unsigned char threebyte
;
9616 FETCH_DATA (info
, codep
+ 1);
9618 dp
= &dis386_twobyte
[threebyte
];
9619 need_modrm
= twobyte_has_modrm
[threebyte
];
9624 dp
= &dis386
[*codep
];
9625 need_modrm
= onebyte_has_modrm
[*codep
];
9629 /* Save sizeflag for printing the extra prefixes later before updating
9630 it for mnemonic and operand processing. The prefix names depend
9631 only on the address mode. */
9632 orig_sizeflag
= sizeflag
;
9633 if (prefixes
& PREFIX_ADDR
)
9635 if ((prefixes
& PREFIX_DATA
))
9641 FETCH_DATA (info
, codep
+ 1);
9642 modrm
.mod
= (*codep
>> 6) & 3;
9643 modrm
.reg
= (*codep
>> 3) & 7;
9644 modrm
.rm
= *codep
& 7;
9647 memset (&modrm
, 0, sizeof (modrm
));
9650 memset (&vex
, 0, sizeof (vex
));
9652 if (dp
->name
== NULL
&& dp
->op
[0].bytemode
== FLOATCODE
)
9654 get_sib (info
, sizeflag
);
9659 dp
= get_valid_dis386 (dp
, info
);
9660 if (dp
!= NULL
&& putop (dp
->name
, sizeflag
) == 0)
9662 get_sib (info
, sizeflag
);
9663 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
9666 op_ad
= MAX_OPERANDS
- 1 - i
;
9668 (*dp
->op
[i
].rtn
) (dp
->op
[i
].bytemode
, sizeflag
);
9669 /* For EVEX instruction after the last operand masking
9670 should be printed. */
9671 if (i
== 0 && vex
.evex
)
9673 /* Don't print {%k0}. */
9674 if (vex
.mask_register_specifier
)
9677 oappend (names_mask
[vex
.mask_register_specifier
]);
9683 /* S/G insns require a mask and don't allow
9685 if ((dp
->op
[0].bytemode
== vex_vsib_d_w_dq_mode
9686 || dp
->op
[0].bytemode
== vex_vsib_q_w_dq_mode
)
9687 && (vex
.mask_register_specifier
== 0 || vex
.zeroing
))
9694 /* Clear instruction information. */
9697 the_info
->insn_info_valid
= 0;
9698 the_info
->branch_delay_insns
= 0;
9699 the_info
->data_size
= 0;
9700 the_info
->insn_type
= dis_noninsn
;
9701 the_info
->target
= 0;
9702 the_info
->target2
= 0;
9705 /* Reset jump operation indicator. */
9709 int jump_detection
= 0;
9711 /* Extract flags. */
9712 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
9714 if ((dp
->op
[i
].rtn
== OP_J
)
9715 || (dp
->op
[i
].rtn
== OP_indirE
))
9716 jump_detection
|= 1;
9717 else if ((dp
->op
[i
].rtn
== BND_Fixup
)
9718 || (!dp
->op
[i
].rtn
&& !dp
->op
[i
].bytemode
))
9719 jump_detection
|= 2;
9720 else if ((dp
->op
[i
].bytemode
== cond_jump_mode
)
9721 || (dp
->op
[i
].bytemode
== loop_jcxz_mode
))
9722 jump_detection
|= 4;
9725 /* Determine if this is a jump or branch. */
9726 if ((jump_detection
& 0x3) == 0x3)
9729 if (jump_detection
& 0x4)
9730 the_info
->insn_type
= dis_condbranch
;
9732 the_info
->insn_type
=
9733 (dp
->name
&& !strncmp(dp
->name
, "call", 4))
9734 ? dis_jsr
: dis_branch
;
9738 /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
9739 are all 0s in inverted form. */
9740 if (need_vex
&& vex
.register_specifier
!= 0)
9742 (*info
->fprintf_func
) (info
->stream
, "(bad)");
9743 return end_codep
- priv
.the_buffer
;
9746 /* If EVEX.z is set, there must be an actual mask register in use. */
9747 if (vex
.zeroing
&& vex
.mask_register_specifier
== 0)
9749 (*info
->fprintf_func
) (info
->stream
, "(bad)");
9750 return end_codep
- priv
.the_buffer
;
9753 switch (dp
->prefix_requirement
)
9756 /* If only the data prefix is marked as mandatory, its absence renders
9757 the encoding invalid. Most other PREFIX_OPCODE rules still apply. */
9758 if (need_vex
? !vex
.prefix
: !(prefixes
& PREFIX_DATA
))
9760 (*info
->fprintf_func
) (info
->stream
, "(bad)");
9761 return end_codep
- priv
.the_buffer
;
9763 used_prefixes
|= PREFIX_DATA
;
9766 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
9767 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
9768 used by putop and MMX/SSE operand and may be overridden by the
9769 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
9772 ? vex
.prefix
== REPE_PREFIX_OPCODE
9773 || vex
.prefix
== REPNE_PREFIX_OPCODE
9775 & (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0)
9777 & (PREFIX_REPZ
| PREFIX_REPNZ
)) == 0)
9779 ? vex
.prefix
== DATA_PREFIX_OPCODE
9781 & (PREFIX_REPZ
| PREFIX_REPNZ
| PREFIX_DATA
))
9783 && (used_prefixes
& PREFIX_DATA
) == 0))
9784 || (vex
.evex
&& dp
->prefix_requirement
!= PREFIX_DATA
9785 && !vex
.w
!= !(used_prefixes
& PREFIX_DATA
)))
9787 (*info
->fprintf_func
) (info
->stream
, "(bad)");
9788 return end_codep
- priv
.the_buffer
;
9792 case PREFIX_IGNORED
:
9793 /* Zap data size and rep prefixes from used_prefixes and reinstate their
9794 origins in all_prefixes. */
9795 used_prefixes
&= ~PREFIX_OPCODE
;
9796 if (last_data_prefix
>= 0)
9797 all_prefixes
[last_data_prefix
] = 0x66;
9798 if (last_repz_prefix
>= 0)
9799 all_prefixes
[last_repz_prefix
] = 0xf3;
9800 if (last_repnz_prefix
>= 0)
9801 all_prefixes
[last_repnz_prefix
] = 0xf2;
9805 /* Check if the REX prefix is used. */
9806 if ((rex
^ rex_used
) == 0 && !need_vex
&& last_rex_prefix
>= 0)
9807 all_prefixes
[last_rex_prefix
] = 0;
9809 /* Check if the SEG prefix is used. */
9810 if ((prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
| PREFIX_ES
9811 | PREFIX_FS
| PREFIX_GS
)) != 0
9812 && (used_prefixes
& active_seg_prefix
) != 0)
9813 all_prefixes
[last_seg_prefix
] = 0;
9815 /* Check if the ADDR prefix is used. */
9816 if ((prefixes
& PREFIX_ADDR
) != 0
9817 && (used_prefixes
& PREFIX_ADDR
) != 0)
9818 all_prefixes
[last_addr_prefix
] = 0;
9820 /* Check if the DATA prefix is used. */
9821 if ((prefixes
& PREFIX_DATA
) != 0
9822 && (used_prefixes
& PREFIX_DATA
) != 0
9824 all_prefixes
[last_data_prefix
] = 0;
9826 /* Print the extra prefixes. */
9828 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
9829 if (all_prefixes
[i
])
9832 name
= prefix_name (all_prefixes
[i
], orig_sizeflag
);
9835 prefix_length
+= strlen (name
) + 1;
9836 (*info
->fprintf_func
) (info
->stream
, "%s ", name
);
9839 /* Check maximum code length. */
9840 if ((codep
- start_codep
) > MAX_CODE_LENGTH
)
9842 (*info
->fprintf_func
) (info
->stream
, "(bad)");
9843 return MAX_CODE_LENGTH
;
9846 obufp
= mnemonicendp
;
9847 for (i
= strlen (obuf
) + prefix_length
; i
< 6; i
++)
9850 (*info
->fprintf_func
) (info
->stream
, "%s", obuf
);
9852 /* The enter and bound instructions are printed with operands in the same
9853 order as the intel book; everything else is printed in reverse order. */
9854 if (intel_syntax
|| two_source_ops
)
9858 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
9859 op_txt
[i
] = op_out
[i
];
9861 if (intel_syntax
&& dp
&& dp
->op
[2].rtn
== OP_Rounding
9862 && dp
->op
[3].rtn
== OP_E
&& dp
->op
[4].rtn
== NULL
)
9864 op_txt
[2] = op_out
[3];
9865 op_txt
[3] = op_out
[2];
9868 for (i
= 0; i
< (MAX_OPERANDS
>> 1); ++i
)
9870 op_ad
= op_index
[i
];
9871 op_index
[i
] = op_index
[MAX_OPERANDS
- 1 - i
];
9872 op_index
[MAX_OPERANDS
- 1 - i
] = op_ad
;
9873 riprel
= op_riprel
[i
];
9874 op_riprel
[i
] = op_riprel
[MAX_OPERANDS
- 1 - i
];
9875 op_riprel
[MAX_OPERANDS
- 1 - i
] = riprel
;
9880 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
9881 op_txt
[MAX_OPERANDS
- 1 - i
] = op_out
[i
];
9885 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
9889 (*info
->fprintf_func
) (info
->stream
, ",");
9890 if (op_index
[i
] != -1 && !op_riprel
[i
])
9892 bfd_vma target
= (bfd_vma
) op_address
[op_index
[i
]];
9894 if (the_info
&& op_is_jump
)
9896 the_info
->insn_info_valid
= 1;
9897 the_info
->branch_delay_insns
= 0;
9898 the_info
->data_size
= 0;
9899 the_info
->target
= target
;
9900 the_info
->target2
= 0;
9902 (*info
->print_address_func
) (target
, info
);
9905 (*info
->fprintf_func
) (info
->stream
, "%s", op_txt
[i
]);
9909 for (i
= 0; i
< MAX_OPERANDS
; i
++)
9910 if (op_index
[i
] != -1 && op_riprel
[i
])
9912 (*info
->fprintf_func
) (info
->stream
, " # ");
9913 (*info
->print_address_func
) ((bfd_vma
) (start_pc
+ (codep
- start_codep
)
9914 + op_address
[op_index
[i
]]), info
);
9917 return codep
- priv
.the_buffer
;
9920 static const char *float_mem
[] = {
9995 static const unsigned char float_mem_mode
[] = {
10070 #define ST { OP_ST, 0 }
10071 #define STi { OP_STi, 0 }
10073 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
10074 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
10075 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
10076 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
10077 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
10078 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
10079 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
10080 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
10081 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
10083 static const struct dis386 float_reg
[][8] = {
10086 { "fadd", { ST
, STi
}, 0 },
10087 { "fmul", { ST
, STi
}, 0 },
10088 { "fcom", { STi
}, 0 },
10089 { "fcomp", { STi
}, 0 },
10090 { "fsub", { ST
, STi
}, 0 },
10091 { "fsubr", { ST
, STi
}, 0 },
10092 { "fdiv", { ST
, STi
}, 0 },
10093 { "fdivr", { ST
, STi
}, 0 },
10097 { "fld", { STi
}, 0 },
10098 { "fxch", { STi
}, 0 },
10108 { "fcmovb", { ST
, STi
}, 0 },
10109 { "fcmove", { ST
, STi
}, 0 },
10110 { "fcmovbe",{ ST
, STi
}, 0 },
10111 { "fcmovu", { ST
, STi
}, 0 },
10119 { "fcmovnb",{ ST
, STi
}, 0 },
10120 { "fcmovne",{ ST
, STi
}, 0 },
10121 { "fcmovnbe",{ ST
, STi
}, 0 },
10122 { "fcmovnu",{ ST
, STi
}, 0 },
10124 { "fucomi", { ST
, STi
}, 0 },
10125 { "fcomi", { ST
, STi
}, 0 },
10130 { "fadd", { STi
, ST
}, 0 },
10131 { "fmul", { STi
, ST
}, 0 },
10134 { "fsub{!M|r}", { STi
, ST
}, 0 },
10135 { "fsub{M|}", { STi
, ST
}, 0 },
10136 { "fdiv{!M|r}", { STi
, ST
}, 0 },
10137 { "fdiv{M|}", { STi
, ST
}, 0 },
10141 { "ffree", { STi
}, 0 },
10143 { "fst", { STi
}, 0 },
10144 { "fstp", { STi
}, 0 },
10145 { "fucom", { STi
}, 0 },
10146 { "fucomp", { STi
}, 0 },
10152 { "faddp", { STi
, ST
}, 0 },
10153 { "fmulp", { STi
, ST
}, 0 },
10156 { "fsub{!M|r}p", { STi
, ST
}, 0 },
10157 { "fsub{M|}p", { STi
, ST
}, 0 },
10158 { "fdiv{!M|r}p", { STi
, ST
}, 0 },
10159 { "fdiv{M|}p", { STi
, ST
}, 0 },
10163 { "ffreep", { STi
}, 0 },
10168 { "fucomip", { ST
, STi
}, 0 },
10169 { "fcomip", { ST
, STi
}, 0 },
10174 static char *fgrps
[][8] = {
10177 "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10182 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10187 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
10192 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
10197 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
10202 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
10207 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10212 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
10213 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
10218 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10223 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10228 swap_operand (void)
10230 mnemonicendp
[0] = '.';
10231 mnemonicendp
[1] = 's';
10236 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED
,
10237 int sizeflag ATTRIBUTE_UNUSED
)
10239 /* Skip mod/rm byte. */
10245 dofloat (int sizeflag
)
10247 const struct dis386
*dp
;
10248 unsigned char floatop
;
10250 floatop
= codep
[-1];
10252 if (modrm
.mod
!= 3)
10254 int fp_indx
= (floatop
- 0xd8) * 8 + modrm
.reg
;
10256 putop (float_mem
[fp_indx
], sizeflag
);
10259 OP_E (float_mem_mode
[fp_indx
], sizeflag
);
10262 /* Skip mod/rm byte. */
10266 dp
= &float_reg
[floatop
- 0xd8][modrm
.reg
];
10267 if (dp
->name
== NULL
)
10269 putop (fgrps
[dp
->op
[0].bytemode
][modrm
.rm
], sizeflag
);
10271 /* Instruction fnstsw is only one with strange arg. */
10272 if (floatop
== 0xdf && codep
[-1] == 0xe0)
10273 strcpy (op_out
[0], names16
[0]);
10277 putop (dp
->name
, sizeflag
);
10282 (*dp
->op
[0].rtn
) (dp
->op
[0].bytemode
, sizeflag
);
10287 (*dp
->op
[1].rtn
) (dp
->op
[1].bytemode
, sizeflag
);
10291 /* Like oappend (below), but S is a string starting with '%'.
10292 In Intel syntax, the '%' is elided. */
10294 oappend_maybe_intel (const char *s
)
10296 oappend (s
+ intel_syntax
);
10300 OP_ST (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
10302 oappend_maybe_intel ("%st");
10306 OP_STi (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
10308 sprintf (scratchbuf
, "%%st(%d)", modrm
.rm
);
10309 oappend_maybe_intel (scratchbuf
);
10312 /* Capital letters in template are macros. */
10314 putop (const char *in_template
, int sizeflag
)
10319 unsigned int l
= 0, len
= 0;
10322 for (p
= in_template
; *p
; p
++)
10326 if (l
>= sizeof (last
) || !ISUPPER (*p
))
10345 while (*++p
!= '|')
10346 if (*p
== '}' || *p
== '\0')
10352 while (*++p
!= '}')
10364 if ((need_modrm
&& modrm
.mod
!= 3)
10365 || (sizeflag
& SUFFIX_ALWAYS
))
10374 if (sizeflag
& SUFFIX_ALWAYS
)
10377 else if (l
== 1 && last
[0] == 'L')
10379 if (address_mode
== mode_64bit
10380 && !(prefixes
& PREFIX_ADDR
))
10393 if (intel_syntax
&& !alt
)
10395 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
10397 if (sizeflag
& DFLAG
)
10398 *obufp
++ = intel_syntax
? 'd' : 'l';
10400 *obufp
++ = intel_syntax
? 'w' : 's';
10401 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10405 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
10408 if (modrm
.mod
== 3)
10414 if (sizeflag
& DFLAG
)
10415 *obufp
++ = intel_syntax
? 'd' : 'l';
10418 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10424 case 'E': /* For jcxz/jecxz */
10425 if (address_mode
== mode_64bit
)
10427 if (sizeflag
& AFLAG
)
10433 if (sizeflag
& AFLAG
)
10435 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
10440 if ((prefixes
& PREFIX_ADDR
) || (sizeflag
& SUFFIX_ALWAYS
))
10442 if (sizeflag
& AFLAG
)
10443 *obufp
++ = address_mode
== mode_64bit
? 'q' : 'l';
10445 *obufp
++ = address_mode
== mode_64bit
? 'l' : 'w';
10446 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
10450 if (intel_syntax
|| (obufp
[-1] != 's' && !(sizeflag
& SUFFIX_ALWAYS
)))
10452 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
10456 if (!(rex
& REX_W
))
10457 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10462 if ((prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_CS
10463 || (prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_DS
)
10465 used_prefixes
|= prefixes
& (PREFIX_CS
| PREFIX_DS
);
10469 /* Set active_seg_prefix even if not set in 64-bit mode
10470 because here it is a valid branch hint. */
10471 if (prefixes
& PREFIX_DS
)
10473 active_seg_prefix
= PREFIX_DS
;
10478 active_seg_prefix
= PREFIX_CS
;
10493 if (intel_mnemonic
!= cond
)
10497 if ((prefixes
& PREFIX_FWAIT
) == 0)
10500 used_prefixes
|= PREFIX_FWAIT
;
10506 else if (intel_syntax
&& (sizeflag
& DFLAG
))
10510 if (!(rex
& REX_W
))
10511 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10514 if (address_mode
== mode_64bit
10515 && (isa64
== intel64
|| (rex
& REX_W
)
10516 || !(prefixes
& PREFIX_DATA
)))
10518 if (sizeflag
& SUFFIX_ALWAYS
)
10522 /* Fall through. */
10526 if ((modrm
.mod
== 3 || !cond
)
10527 && !(sizeflag
& SUFFIX_ALWAYS
))
10529 /* Fall through. */
10531 if ((!(rex
& REX_W
) && (prefixes
& PREFIX_DATA
))
10532 || ((sizeflag
& SUFFIX_ALWAYS
)
10533 && address_mode
!= mode_64bit
))
10535 *obufp
++ = (sizeflag
& DFLAG
) ?
10536 intel_syntax
? 'd' : 'l' : 'w';
10537 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10539 else if (sizeflag
& SUFFIX_ALWAYS
)
10542 else if (l
== 1 && last
[0] == 'L')
10544 if ((prefixes
& PREFIX_DATA
)
10546 || (sizeflag
& SUFFIX_ALWAYS
))
10553 if (sizeflag
& DFLAG
)
10554 *obufp
++ = intel_syntax
? 'd' : 'l';
10557 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10567 if (intel_syntax
&& !alt
)
10570 if ((need_modrm
&& modrm
.mod
!= 3)
10571 || (sizeflag
& SUFFIX_ALWAYS
))
10577 if (sizeflag
& DFLAG
)
10578 *obufp
++ = intel_syntax
? 'd' : 'l';
10581 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10585 else if (l
== 1 && last
[0] == 'D')
10586 *obufp
++ = vex
.w
? 'q' : 'd';
10587 else if (l
== 1 && last
[0] == 'L')
10589 if (cond
? modrm
.mod
== 3 && !(sizeflag
& SUFFIX_ALWAYS
)
10590 : address_mode
!= mode_64bit
)
10597 else if((address_mode
== mode_64bit
&& cond
)
10598 || (sizeflag
& SUFFIX_ALWAYS
))
10599 *obufp
++ = intel_syntax
? 'd' : 'l';
10608 else if (sizeflag
& DFLAG
)
10617 if (intel_syntax
&& !p
[1]
10618 && ((rex
& REX_W
) || (sizeflag
& DFLAG
)))
10620 if (!(rex
& REX_W
))
10621 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10629 if (sizeflag
& SUFFIX_ALWAYS
)
10635 if (sizeflag
& DFLAG
)
10639 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10643 else if (l
== 1 && last
[0] == 'L')
10645 if (address_mode
== mode_64bit
10646 && !(prefixes
& PREFIX_ADDR
))
10662 && (last
[0] == 'L' || last
[0] == 'X'))
10664 if (last
[0] == 'X')
10672 else if (rex
& REX_W
)
10685 /* operand size flag for cwtl, cbtw */
10694 else if (sizeflag
& DFLAG
)
10698 if (!(rex
& REX_W
))
10699 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10705 if (last
[0] == 'X')
10706 *obufp
++ = vex
.w
? 'd': 's';
10707 else if (last
[0] == 'B')
10708 *obufp
++ = vex
.w
? 'w': 'b';
10719 ? vex
.prefix
== DATA_PREFIX_OPCODE
10720 : prefixes
& PREFIX_DATA
)
10723 used_prefixes
|= PREFIX_DATA
;
10729 if (l
== 1 && last
[0] == 'X')
10734 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
10736 switch (vex
.length
)
10756 /* These insns ignore ModR/M.mod: Force it to 3 for OP_E(). */
10758 if (!intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
10759 *obufp
++ = address_mode
== mode_64bit
? 'q' : 'l';
10761 else if (l
== 1 && last
[0] == 'X')
10766 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
10768 switch (vex
.length
)
10789 if (isa64
== intel64
&& (rex
& REX_W
))
10795 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
10797 if (sizeflag
& DFLAG
)
10801 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10810 mnemonicendp
= obufp
;
10815 oappend (const char *s
)
10817 obufp
= stpcpy (obufp
, s
);
10823 /* Only print the active segment register. */
10824 if (!active_seg_prefix
)
10827 used_prefixes
|= active_seg_prefix
;
10828 switch (active_seg_prefix
)
10831 oappend_maybe_intel ("%cs:");
10834 oappend_maybe_intel ("%ds:");
10837 oappend_maybe_intel ("%ss:");
10840 oappend_maybe_intel ("%es:");
10843 oappend_maybe_intel ("%fs:");
10846 oappend_maybe_intel ("%gs:");
10854 OP_indirE (int bytemode
, int sizeflag
)
10858 OP_E (bytemode
, sizeflag
);
10862 print_operand_value (char *buf
, int hex
, bfd_vma disp
)
10864 if (address_mode
== mode_64bit
)
10872 sprintf_vma (tmp
, disp
);
10873 for (i
= 0; tmp
[i
] == '0' && tmp
[i
+ 1]; i
++);
10874 strcpy (buf
+ 2, tmp
+ i
);
10878 bfd_signed_vma v
= disp
;
10885 /* Check for possible overflow on 0x8000000000000000. */
10888 strcpy (buf
, "9223372036854775808");
10902 tmp
[28 - i
] = (v
% 10) + '0';
10906 strcpy (buf
, tmp
+ 29 - i
);
10912 sprintf (buf
, "0x%x", (unsigned int) disp
);
10914 sprintf (buf
, "%d", (int) disp
);
10918 /* Put DISP in BUF as signed hex number. */
10921 print_displacement (char *buf
, bfd_vma disp
)
10923 bfd_signed_vma val
= disp
;
10932 /* Check for possible overflow. */
10935 switch (address_mode
)
10938 strcpy (buf
+ j
, "0x8000000000000000");
10941 strcpy (buf
+ j
, "0x80000000");
10944 strcpy (buf
+ j
, "0x8000");
10954 sprintf_vma (tmp
, (bfd_vma
) val
);
10955 for (i
= 0; tmp
[i
] == '0'; i
++)
10957 if (tmp
[i
] == '\0')
10959 strcpy (buf
+ j
, tmp
+ i
);
10963 intel_operand_size (int bytemode
, int sizeflag
)
10966 && (bytemode
== x_mode
10967 || bytemode
== evex_half_bcst_xmmq_mode
))
10970 oappend ("QWORD PTR ");
10972 oappend ("DWORD PTR ");
10981 oappend ("BYTE PTR ");
10986 oappend ("WORD PTR ");
10989 if (address_mode
== mode_64bit
&& isa64
== intel64
)
10991 oappend ("QWORD PTR ");
10994 /* Fall through. */
10996 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
10998 oappend ("QWORD PTR ");
11001 /* Fall through. */
11007 oappend ("QWORD PTR ");
11008 else if (bytemode
== dq_mode
)
11009 oappend ("DWORD PTR ");
11012 if (sizeflag
& DFLAG
)
11013 oappend ("DWORD PTR ");
11015 oappend ("WORD PTR ");
11016 used_prefixes
|= (prefixes
& PREFIX_DATA
);
11020 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
11022 oappend ("WORD PTR ");
11023 if (!(rex
& REX_W
))
11024 used_prefixes
|= (prefixes
& PREFIX_DATA
);
11027 if (sizeflag
& DFLAG
)
11028 oappend ("QWORD PTR ");
11030 oappend ("DWORD PTR ");
11031 used_prefixes
|= (prefixes
& PREFIX_DATA
);
11034 if (!(sizeflag
& DFLAG
) && isa64
== intel64
)
11035 oappend ("WORD PTR ");
11037 oappend ("DWORD PTR ");
11038 used_prefixes
|= (prefixes
& PREFIX_DATA
);
11043 oappend ("DWORD PTR ");
11047 oappend ("QWORD PTR ");
11050 if (address_mode
== mode_64bit
)
11051 oappend ("QWORD PTR ");
11053 oappend ("DWORD PTR ");
11056 if (sizeflag
& DFLAG
)
11057 oappend ("FWORD PTR ");
11059 oappend ("DWORD PTR ");
11060 used_prefixes
|= (prefixes
& PREFIX_DATA
);
11063 oappend ("TBYTE PTR ");
11067 case evex_x_gscat_mode
:
11068 case evex_x_nobcst_mode
:
11072 switch (vex
.length
)
11075 oappend ("XMMWORD PTR ");
11078 oappend ("YMMWORD PTR ");
11081 oappend ("ZMMWORD PTR ");
11088 oappend ("XMMWORD PTR ");
11091 oappend ("XMMWORD PTR ");
11094 oappend ("YMMWORD PTR ");
11097 case evex_half_bcst_xmmq_mode
:
11101 switch (vex
.length
)
11104 oappend ("QWORD PTR ");
11107 oappend ("XMMWORD PTR ");
11110 oappend ("YMMWORD PTR ");
11120 switch (vex
.length
)
11125 oappend ("BYTE PTR ");
11135 switch (vex
.length
)
11140 oappend ("WORD PTR ");
11150 switch (vex
.length
)
11155 oappend ("DWORD PTR ");
11165 switch (vex
.length
)
11170 oappend ("QWORD PTR ");
11180 switch (vex
.length
)
11183 oappend ("WORD PTR ");
11186 oappend ("DWORD PTR ");
11189 oappend ("QWORD PTR ");
11199 switch (vex
.length
)
11202 oappend ("DWORD PTR ");
11205 oappend ("QWORD PTR ");
11208 oappend ("XMMWORD PTR ");
11218 switch (vex
.length
)
11221 oappend ("QWORD PTR ");
11224 oappend ("YMMWORD PTR ");
11227 oappend ("ZMMWORD PTR ");
11237 switch (vex
.length
)
11241 oappend ("XMMWORD PTR ");
11248 oappend ("OWORD PTR ");
11250 case vex_scalar_w_dq_mode
:
11255 oappend ("QWORD PTR ");
11257 oappend ("DWORD PTR ");
11259 case vex_vsib_d_w_dq_mode
:
11260 case vex_vsib_q_w_dq_mode
:
11265 oappend ("QWORD PTR ");
11267 oappend ("DWORD PTR ");
11270 if (!need_vex
|| vex
.length
!= 128)
11273 oappend ("DWORD PTR ");
11275 oappend ("BYTE PTR ");
11281 oappend ("QWORD PTR ");
11283 oappend ("WORD PTR ");
11293 OP_E_register (int bytemode
, int sizeflag
)
11295 int reg
= modrm
.rm
;
11296 const char **names
;
11302 if ((sizeflag
& SUFFIX_ALWAYS
)
11303 && (bytemode
== b_swap_mode
11304 || bytemode
== bnd_swap_mode
11305 || bytemode
== v_swap_mode
))
11332 names
= address_mode
== mode_64bit
? names64
: names32
;
11335 case bnd_swap_mode
:
11344 if (address_mode
== mode_64bit
&& isa64
== intel64
)
11349 /* Fall through. */
11351 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
11357 /* Fall through. */
11367 else if (bytemode
!= v_mode
&& bytemode
!= v_swap_mode
)
11371 if (sizeflag
& DFLAG
)
11375 used_prefixes
|= (prefixes
& PREFIX_DATA
);
11379 if (!(sizeflag
& DFLAG
) && isa64
== intel64
)
11383 used_prefixes
|= (prefixes
& PREFIX_DATA
);
11386 names
= (address_mode
== mode_64bit
11387 ? names64
: names32
);
11388 if (!(prefixes
& PREFIX_ADDR
))
11389 names
= (address_mode
== mode_16bit
11390 ? names16
: names
);
11393 /* Remove "addr16/addr32". */
11394 all_prefixes
[last_addr_prefix
] = 0;
11395 names
= (address_mode
!= mode_32bit
11396 ? names32
: names16
);
11397 used_prefixes
|= PREFIX_ADDR
;
11407 names
= names_mask
;
11412 oappend (INTERNAL_DISASSEMBLER_ERROR
);
11415 oappend (names
[reg
]);
11419 OP_E_memory (int bytemode
, int sizeflag
)
11422 int add
= (rex
& REX_B
) ? 8 : 0;
11428 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
11430 && bytemode
!= x_mode
11431 && bytemode
!= evex_half_bcst_xmmq_mode
)
11449 if (address_mode
!= mode_64bit
)
11459 case vex_scalar_w_dq_mode
:
11460 case vex_vsib_d_w_dq_mode
:
11461 case vex_vsib_q_w_dq_mode
:
11462 case evex_x_gscat_mode
:
11463 shift
= vex
.w
? 3 : 2;
11466 case evex_half_bcst_xmmq_mode
:
11469 shift
= vex
.w
? 3 : 2;
11472 /* Fall through. */
11477 case evex_x_nobcst_mode
:
11479 switch (vex
.length
)
11493 /* Make necessary corrections to shift for modes that need it. */
11494 if (bytemode
== xmmq_mode
11495 || bytemode
== evex_half_bcst_xmmq_mode
11496 || (bytemode
== ymmq_mode
&& vex
.length
== 128))
11498 else if (bytemode
== xmmqd_mode
)
11500 else if (bytemode
== xmmdw_mode
)
11515 shift
= vex
.w
? 1 : 0;
11526 intel_operand_size (bytemode
, sizeflag
);
11529 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
11531 /* 32/64 bit address mode */
11541 int addr32flag
= !((sizeflag
& AFLAG
)
11542 || bytemode
== v_bnd_mode
11543 || bytemode
== v_bndmk_mode
11544 || bytemode
== bnd_mode
11545 || bytemode
== bnd_swap_mode
);
11546 bool check_gather
= false;
11547 const char **indexes64
= names64
;
11548 const char **indexes32
= names32
;
11558 vindex
= sib
.index
;
11564 case vex_vsib_d_w_dq_mode
:
11565 case vex_vsib_q_w_dq_mode
:
11572 check_gather
= obufp
== op_out
[1];
11576 switch (vex
.length
)
11579 indexes64
= indexes32
= names_xmm
;
11583 || bytemode
== vex_vsib_q_w_dq_mode
)
11584 indexes64
= indexes32
= names_ymm
;
11586 indexes64
= indexes32
= names_xmm
;
11590 || bytemode
== vex_vsib_q_w_dq_mode
)
11591 indexes64
= indexes32
= names_zmm
;
11593 indexes64
= indexes32
= names_ymm
;
11600 haveindex
= vindex
!= 4;
11609 /* Check for mandatory SIB. */
11610 if (bytemode
== vex_vsib_d_w_dq_mode
11611 || bytemode
== vex_vsib_q_w_dq_mode
11612 || bytemode
== vex_sibmem_mode
)
11618 rbase
= base
+ add
;
11626 if (address_mode
== mode_64bit
&& !havesib
)
11629 if (riprel
&& bytemode
== v_bndmk_mode
)
11637 FETCH_DATA (the_info
, codep
+ 1);
11639 if ((disp
& 0x80) != 0)
11641 if (vex
.evex
&& shift
> 0)
11654 && address_mode
!= mode_16bit
)
11656 if (address_mode
== mode_64bit
)
11660 /* Without base nor index registers, zero-extend the
11661 lower 32-bit displacement to 64 bits. */
11662 disp
= (unsigned int) disp
;
11669 /* In 32-bit mode, we need index register to tell [offset]
11670 from [eiz*1 + offset]. */
11675 havedisp
= (havebase
11677 || (havesib
&& (haveindex
|| scale
!= 0)));
11680 if (modrm
.mod
!= 0 || base
== 5)
11682 if (havedisp
|| riprel
)
11683 print_displacement (scratchbuf
, disp
);
11685 print_operand_value (scratchbuf
, 1, disp
);
11686 oappend (scratchbuf
);
11690 oappend (!addr32flag
? "(%rip)" : "(%eip)");
11694 if ((havebase
|| haveindex
|| needindex
|| needaddr32
|| riprel
)
11695 && (address_mode
!= mode_64bit
11696 || ((bytemode
!= v_bnd_mode
)
11697 && (bytemode
!= v_bndmk_mode
)
11698 && (bytemode
!= bnd_mode
)
11699 && (bytemode
!= bnd_swap_mode
))))
11700 used_prefixes
|= PREFIX_ADDR
;
11702 if (havedisp
|| (intel_syntax
&& riprel
))
11704 *obufp
++ = open_char
;
11705 if (intel_syntax
&& riprel
)
11708 oappend (!addr32flag
? "rip" : "eip");
11712 oappend (address_mode
== mode_64bit
&& !addr32flag
11713 ? names64
[rbase
] : names32
[rbase
]);
11716 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
11717 print index to tell base + index from base. */
11721 || (havebase
&& base
!= ESP_REG_NUM
))
11723 if (!intel_syntax
|| havebase
)
11725 *obufp
++ = separator_char
;
11729 oappend (address_mode
== mode_64bit
&& !addr32flag
11730 ? indexes64
[vindex
] : indexes32
[vindex
]);
11732 oappend (address_mode
== mode_64bit
&& !addr32flag
11733 ? index64
: index32
);
11735 *obufp
++ = scale_char
;
11737 sprintf (scratchbuf
, "%d", 1 << scale
);
11738 oappend (scratchbuf
);
11742 && (disp
|| modrm
.mod
!= 0 || base
== 5))
11744 if (!havedisp
|| (bfd_signed_vma
) disp
>= 0)
11749 else if (modrm
.mod
!= 1 && disp
!= -disp
)
11757 print_displacement (scratchbuf
, disp
);
11759 print_operand_value (scratchbuf
, 1, disp
);
11760 oappend (scratchbuf
);
11763 *obufp
++ = close_char
;
11768 /* Both XMM/YMM/ZMM registers must be distinct. */
11769 int modrm_reg
= modrm
.reg
;
11775 if (vindex
== modrm_reg
)
11776 oappend ("/(bad)");
11779 else if (intel_syntax
)
11781 if (modrm
.mod
!= 0 || base
== 5)
11783 if (!active_seg_prefix
)
11785 oappend (names_seg
[ds_reg
- es_reg
]);
11788 print_operand_value (scratchbuf
, 1, disp
);
11789 oappend (scratchbuf
);
11793 else if (bytemode
== v_bnd_mode
11794 || bytemode
== v_bndmk_mode
11795 || bytemode
== bnd_mode
11796 || bytemode
== bnd_swap_mode
11797 || bytemode
== vex_vsib_d_w_dq_mode
11798 || bytemode
== vex_vsib_q_w_dq_mode
)
11805 /* 16 bit address mode */
11806 used_prefixes
|= prefixes
& PREFIX_ADDR
;
11813 if ((disp
& 0x8000) != 0)
11818 FETCH_DATA (the_info
, codep
+ 1);
11820 if ((disp
& 0x80) != 0)
11822 if (vex
.evex
&& shift
> 0)
11827 if ((disp
& 0x8000) != 0)
11833 if (modrm
.mod
!= 0 || modrm
.rm
== 6)
11835 print_displacement (scratchbuf
, disp
);
11836 oappend (scratchbuf
);
11839 if (modrm
.mod
!= 0 || modrm
.rm
!= 6)
11841 *obufp
++ = open_char
;
11843 oappend (index16
[modrm
.rm
]);
11845 && (disp
|| modrm
.mod
!= 0 || modrm
.rm
== 6))
11847 if ((bfd_signed_vma
) disp
>= 0)
11852 else if (modrm
.mod
!= 1)
11859 print_displacement (scratchbuf
, disp
);
11860 oappend (scratchbuf
);
11863 *obufp
++ = close_char
;
11866 else if (intel_syntax
)
11868 if (!active_seg_prefix
)
11870 oappend (names_seg
[ds_reg
- es_reg
]);
11873 print_operand_value (scratchbuf
, 1, disp
& 0xffff);
11874 oappend (scratchbuf
);
11878 && (bytemode
== x_mode
11879 || bytemode
== evex_half_bcst_xmmq_mode
))
11882 || bytemode
== evex_half_bcst_xmmq_mode
)
11884 switch (vex
.length
)
11887 oappend ("{1to2}");
11890 oappend ("{1to4}");
11893 oappend ("{1to8}");
11901 switch (vex
.length
)
11904 oappend ("{1to4}");
11907 oappend ("{1to8}");
11910 oappend ("{1to16}");
11920 OP_E (int bytemode
, int sizeflag
)
11922 /* Skip mod/rm byte. */
11926 if (modrm
.mod
== 3)
11927 OP_E_register (bytemode
, sizeflag
);
11929 OP_E_memory (bytemode
, sizeflag
);
11933 OP_G (int bytemode
, int sizeflag
)
11936 const char **names
;
11946 oappend (names8rex
[modrm
.reg
+ add
]);
11948 oappend (names8
[modrm
.reg
+ add
]);
11951 oappend (names16
[modrm
.reg
+ add
]);
11956 oappend (names32
[modrm
.reg
+ add
]);
11959 oappend (names64
[modrm
.reg
+ add
]);
11962 if (modrm
.reg
> 0x3)
11967 oappend (names_bnd
[modrm
.reg
]);
11977 oappend (names64
[modrm
.reg
+ add
]);
11978 else if (bytemode
!= v_mode
&& bytemode
!= movsxd_mode
)
11979 oappend (names32
[modrm
.reg
+ add
]);
11982 if (sizeflag
& DFLAG
)
11983 oappend (names32
[modrm
.reg
+ add
]);
11985 oappend (names16
[modrm
.reg
+ add
]);
11986 used_prefixes
|= (prefixes
& PREFIX_DATA
);
11990 names
= (address_mode
== mode_64bit
11991 ? names64
: names32
);
11992 if (!(prefixes
& PREFIX_ADDR
))
11994 if (address_mode
== mode_16bit
)
11999 /* Remove "addr16/addr32". */
12000 all_prefixes
[last_addr_prefix
] = 0;
12001 names
= (address_mode
!= mode_32bit
12002 ? names32
: names16
);
12003 used_prefixes
|= PREFIX_ADDR
;
12005 oappend (names
[modrm
.reg
+ add
]);
12008 if (address_mode
== mode_64bit
)
12009 oappend (names64
[modrm
.reg
+ add
]);
12011 oappend (names32
[modrm
.reg
+ add
]);
12015 if (add
|| (vex
.evex
&& !vex
.r
))
12020 oappend (names_mask
[modrm
.reg
]);
12023 oappend (INTERNAL_DISASSEMBLER_ERROR
);
12036 FETCH_DATA (the_info
, codep
+ 8);
12037 a
= *codep
++ & 0xff;
12038 a
|= (*codep
++ & 0xff) << 8;
12039 a
|= (*codep
++ & 0xff) << 16;
12040 a
|= (*codep
++ & 0xffu
) << 24;
12041 b
= *codep
++ & 0xff;
12042 b
|= (*codep
++ & 0xff) << 8;
12043 b
|= (*codep
++ & 0xff) << 16;
12044 b
|= (*codep
++ & 0xffu
) << 24;
12045 x
= a
+ ((bfd_vma
) b
<< 32);
12053 static bfd_signed_vma
12058 FETCH_DATA (the_info
, codep
+ 4);
12059 x
= *codep
++ & (bfd_vma
) 0xff;
12060 x
|= (*codep
++ & (bfd_vma
) 0xff) << 8;
12061 x
|= (*codep
++ & (bfd_vma
) 0xff) << 16;
12062 x
|= (*codep
++ & (bfd_vma
) 0xff) << 24;
12066 static bfd_signed_vma
12071 FETCH_DATA (the_info
, codep
+ 4);
12072 x
= *codep
++ & (bfd_vma
) 0xff;
12073 x
|= (*codep
++ & (bfd_vma
) 0xff) << 8;
12074 x
|= (*codep
++ & (bfd_vma
) 0xff) << 16;
12075 x
|= (*codep
++ & (bfd_vma
) 0xff) << 24;
12077 x
= (x
^ ((bfd_vma
) 1 << 31)) - ((bfd_vma
) 1 << 31);
12087 FETCH_DATA (the_info
, codep
+ 2);
12088 x
= *codep
++ & 0xff;
12089 x
|= (*codep
++ & 0xff) << 8;
12094 set_op (bfd_vma op
, int riprel
)
12096 op_index
[op_ad
] = op_ad
;
12097 if (address_mode
== mode_64bit
)
12099 op_address
[op_ad
] = op
;
12100 op_riprel
[op_ad
] = riprel
;
12104 /* Mask to get a 32-bit address. */
12105 op_address
[op_ad
] = op
& 0xffffffff;
12106 op_riprel
[op_ad
] = riprel
& 0xffffffff;
12111 OP_REG (int code
, int sizeflag
)
12118 case es_reg
: case ss_reg
: case cs_reg
:
12119 case ds_reg
: case fs_reg
: case gs_reg
:
12120 oappend (names_seg
[code
- es_reg
]);
12132 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
12133 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
12134 s
= names16
[code
- ax_reg
+ add
];
12136 case ah_reg
: case ch_reg
: case dh_reg
: case bh_reg
:
12138 /* Fall through. */
12139 case al_reg
: case cl_reg
: case dl_reg
: case bl_reg
:
12141 s
= names8rex
[code
- al_reg
+ add
];
12143 s
= names8
[code
- al_reg
];
12145 case rAX_reg
: case rCX_reg
: case rDX_reg
: case rBX_reg
:
12146 case rSP_reg
: case rBP_reg
: case rSI_reg
: case rDI_reg
:
12147 if (address_mode
== mode_64bit
12148 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
12150 s
= names64
[code
- rAX_reg
+ add
];
12153 code
+= eAX_reg
- rAX_reg
;
12154 /* Fall through. */
12155 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
12156 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
12159 s
= names64
[code
- eAX_reg
+ add
];
12162 if (sizeflag
& DFLAG
)
12163 s
= names32
[code
- eAX_reg
+ add
];
12165 s
= names16
[code
- eAX_reg
+ add
];
12166 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12170 s
= INTERNAL_DISASSEMBLER_ERROR
;
12177 OP_IMREG (int code
, int sizeflag
)
12189 case al_reg
: case cl_reg
:
12190 s
= names8
[code
- al_reg
];
12199 /* Fall through. */
12200 case z_mode_ax_reg
:
12201 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
12205 if (!(rex
& REX_W
))
12206 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12209 s
= INTERNAL_DISASSEMBLER_ERROR
;
12216 OP_I (int bytemode
, int sizeflag
)
12219 bfd_signed_vma mask
= -1;
12224 FETCH_DATA (the_info
, codep
+ 1);
12234 if (sizeflag
& DFLAG
)
12244 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12260 oappend (INTERNAL_DISASSEMBLER_ERROR
);
12265 scratchbuf
[0] = '$';
12266 print_operand_value (scratchbuf
+ 1, 1, op
);
12267 oappend_maybe_intel (scratchbuf
);
12268 scratchbuf
[0] = '\0';
12272 OP_I64 (int bytemode
, int sizeflag
)
12274 if (bytemode
!= v_mode
|| address_mode
!= mode_64bit
|| !(rex
& REX_W
))
12276 OP_I (bytemode
, sizeflag
);
12282 scratchbuf
[0] = '$';
12283 print_operand_value (scratchbuf
+ 1, 1, get64 ());
12284 oappend_maybe_intel (scratchbuf
);
12285 scratchbuf
[0] = '\0';
12289 OP_sI (int bytemode
, int sizeflag
)
12297 FETCH_DATA (the_info
, codep
+ 1);
12299 if ((op
& 0x80) != 0)
12301 if (bytemode
== b_T_mode
)
12303 if (address_mode
!= mode_64bit
12304 || !((sizeflag
& DFLAG
) || (rex
& REX_W
)))
12306 /* The operand-size prefix is overridden by a REX prefix. */
12307 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
12315 if (!(rex
& REX_W
))
12317 if (sizeflag
& DFLAG
)
12325 /* The operand-size prefix is overridden by a REX prefix. */
12326 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
12332 oappend (INTERNAL_DISASSEMBLER_ERROR
);
12336 scratchbuf
[0] = '$';
12337 print_operand_value (scratchbuf
+ 1, 1, op
);
12338 oappend_maybe_intel (scratchbuf
);
12342 OP_J (int bytemode
, int sizeflag
)
12346 bfd_vma segment
= 0;
12351 FETCH_DATA (the_info
, codep
+ 1);
12353 if ((disp
& 0x80) != 0)
12358 if ((sizeflag
& DFLAG
)
12359 || (address_mode
== mode_64bit
12360 && ((isa64
== intel64
&& bytemode
!= dqw_mode
)
12361 || (rex
& REX_W
))))
12366 if ((disp
& 0x8000) != 0)
12368 /* In 16bit mode, address is wrapped around at 64k within
12369 the same segment. Otherwise, a data16 prefix on a jump
12370 instruction means that the pc is masked to 16 bits after
12371 the displacement is added! */
12373 if ((prefixes
& PREFIX_DATA
) == 0)
12374 segment
= ((start_pc
+ (codep
- start_codep
))
12375 & ~((bfd_vma
) 0xffff));
12377 if (address_mode
!= mode_64bit
12378 || (isa64
!= intel64
&& !(rex
& REX_W
)))
12379 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12382 oappend (INTERNAL_DISASSEMBLER_ERROR
);
12385 disp
= ((start_pc
+ (codep
- start_codep
) + disp
) & mask
) | segment
;
12387 print_operand_value (scratchbuf
, 1, disp
);
12388 oappend (scratchbuf
);
12392 OP_SEG (int bytemode
, int sizeflag
)
12394 if (bytemode
== w_mode
)
12395 oappend (names_seg
[modrm
.reg
]);
12397 OP_E (modrm
.mod
== 3 ? bytemode
: w_mode
, sizeflag
);
12401 OP_DIR (int dummy ATTRIBUTE_UNUSED
, int sizeflag
)
12405 if (sizeflag
& DFLAG
)
12415 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12417 sprintf (scratchbuf
, "0x%x:0x%x", seg
, offset
);
12419 sprintf (scratchbuf
, "$0x%x,$0x%x", seg
, offset
);
12420 oappend (scratchbuf
);
12424 OP_OFF (int bytemode
, int sizeflag
)
12428 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
12429 intel_operand_size (bytemode
, sizeflag
);
12432 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
12439 if (!active_seg_prefix
)
12441 oappend (names_seg
[ds_reg
- es_reg
]);
12445 print_operand_value (scratchbuf
, 1, off
);
12446 oappend (scratchbuf
);
12450 OP_OFF64 (int bytemode
, int sizeflag
)
12454 if (address_mode
!= mode_64bit
12455 || (prefixes
& PREFIX_ADDR
))
12457 OP_OFF (bytemode
, sizeflag
);
12461 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
12462 intel_operand_size (bytemode
, sizeflag
);
12469 if (!active_seg_prefix
)
12471 oappend (names_seg
[ds_reg
- es_reg
]);
12475 print_operand_value (scratchbuf
, 1, off
);
12476 oappend (scratchbuf
);
12480 ptr_reg (int code
, int sizeflag
)
12484 *obufp
++ = open_char
;
12485 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
12486 if (address_mode
== mode_64bit
)
12488 if (!(sizeflag
& AFLAG
))
12489 s
= names32
[code
- eAX_reg
];
12491 s
= names64
[code
- eAX_reg
];
12493 else if (sizeflag
& AFLAG
)
12494 s
= names32
[code
- eAX_reg
];
12496 s
= names16
[code
- eAX_reg
];
12498 *obufp
++ = close_char
;
12503 OP_ESreg (int code
, int sizeflag
)
12509 case 0x6d: /* insw/insl */
12510 intel_operand_size (z_mode
, sizeflag
);
12512 case 0xa5: /* movsw/movsl/movsq */
12513 case 0xa7: /* cmpsw/cmpsl/cmpsq */
12514 case 0xab: /* stosw/stosl */
12515 case 0xaf: /* scasw/scasl */
12516 intel_operand_size (v_mode
, sizeflag
);
12519 intel_operand_size (b_mode
, sizeflag
);
12522 oappend_maybe_intel ("%es:");
12523 ptr_reg (code
, sizeflag
);
12527 OP_DSreg (int code
, int sizeflag
)
12533 case 0x6f: /* outsw/outsl */
12534 intel_operand_size (z_mode
, sizeflag
);
12536 case 0xa5: /* movsw/movsl/movsq */
12537 case 0xa7: /* cmpsw/cmpsl/cmpsq */
12538 case 0xad: /* lodsw/lodsl/lodsq */
12539 intel_operand_size (v_mode
, sizeflag
);
12542 intel_operand_size (b_mode
, sizeflag
);
12545 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
12546 default segment register DS is printed. */
12547 if (!active_seg_prefix
)
12548 active_seg_prefix
= PREFIX_DS
;
12550 ptr_reg (code
, sizeflag
);
12554 OP_C (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12562 else if (address_mode
!= mode_64bit
&& (prefixes
& PREFIX_LOCK
))
12564 all_prefixes
[last_lock_prefix
] = 0;
12565 used_prefixes
|= PREFIX_LOCK
;
12570 sprintf (scratchbuf
, "%%cr%d", modrm
.reg
+ add
);
12571 oappend_maybe_intel (scratchbuf
);
12575 OP_D (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12584 sprintf (scratchbuf
, "dr%d", modrm
.reg
+ add
);
12586 sprintf (scratchbuf
, "%%db%d", modrm
.reg
+ add
);
12587 oappend (scratchbuf
);
12591 OP_T (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12593 sprintf (scratchbuf
, "%%tr%d", modrm
.reg
);
12594 oappend_maybe_intel (scratchbuf
);
12598 OP_MMX (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12600 int reg
= modrm
.reg
;
12601 const char **names
;
12603 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12604 if (prefixes
& PREFIX_DATA
)
12613 oappend (names
[reg
]);
12617 OP_XMM (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
12619 int reg
= modrm
.reg
;
12620 const char **names
;
12631 if (bytemode
== xmmq_mode
12632 || bytemode
== evex_half_bcst_xmmq_mode
)
12634 switch (vex
.length
)
12647 else if (bytemode
== ymm_mode
)
12649 else if (bytemode
== tmm_mode
)
12660 && bytemode
!= xmm_mode
12661 && bytemode
!= scalar_mode
)
12663 switch (vex
.length
)
12670 || bytemode
!= vex_vsib_q_w_dq_mode
)
12677 || bytemode
!= vex_vsib_q_w_dq_mode
)
12688 oappend (names
[reg
]);
12692 OP_EM (int bytemode
, int sizeflag
)
12695 const char **names
;
12697 if (modrm
.mod
!= 3)
12700 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
12702 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
12703 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12705 OP_E (bytemode
, sizeflag
);
12709 if ((sizeflag
& SUFFIX_ALWAYS
) && bytemode
== v_swap_mode
)
12712 /* Skip mod/rm byte. */
12715 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12717 if (prefixes
& PREFIX_DATA
)
12726 oappend (names
[reg
]);
12729 /* cvt* are the only instructions in sse2 which have
12730 both SSE and MMX operands and also have 0x66 prefix
12731 in their opcode. 0x66 was originally used to differentiate
12732 between SSE and MMX instruction(operands). So we have to handle the
12733 cvt* separately using OP_EMC and OP_MXC */
12735 OP_EMC (int bytemode
, int sizeflag
)
12737 if (modrm
.mod
!= 3)
12739 if (intel_syntax
&& bytemode
== v_mode
)
12741 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
12742 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12744 OP_E (bytemode
, sizeflag
);
12748 /* Skip mod/rm byte. */
12751 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12752 oappend (names_mm
[modrm
.rm
]);
12756 OP_MXC (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12758 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12759 oappend (names_mm
[modrm
.reg
]);
12763 OP_EX (int bytemode
, int sizeflag
)
12766 const char **names
;
12768 /* Skip mod/rm byte. */
12772 if (modrm
.mod
!= 3)
12774 OP_E_memory (bytemode
, sizeflag
);
12789 if ((sizeflag
& SUFFIX_ALWAYS
)
12790 && (bytemode
== x_swap_mode
12791 || bytemode
== d_swap_mode
12792 || bytemode
== q_swap_mode
))
12796 && bytemode
!= xmm_mode
12797 && bytemode
!= xmmdw_mode
12798 && bytemode
!= xmmqd_mode
12799 && bytemode
!= xmm_mb_mode
12800 && bytemode
!= xmm_mw_mode
12801 && bytemode
!= xmm_md_mode
12802 && bytemode
!= xmm_mq_mode
12803 && bytemode
!= xmmq_mode
12804 && bytemode
!= evex_half_bcst_xmmq_mode
12805 && bytemode
!= ymm_mode
12806 && bytemode
!= tmm_mode
12807 && bytemode
!= vex_scalar_w_dq_mode
)
12809 switch (vex
.length
)
12824 else if (bytemode
== xmmq_mode
12825 || bytemode
== evex_half_bcst_xmmq_mode
)
12827 switch (vex
.length
)
12840 else if (bytemode
== tmm_mode
)
12850 else if (bytemode
== ymm_mode
)
12854 oappend (names
[reg
]);
12858 OP_MS (int bytemode
, int sizeflag
)
12860 if (modrm
.mod
== 3)
12861 OP_EM (bytemode
, sizeflag
);
12867 OP_XS (int bytemode
, int sizeflag
)
12869 if (modrm
.mod
== 3)
12870 OP_EX (bytemode
, sizeflag
);
12876 OP_M (int bytemode
, int sizeflag
)
12878 if (modrm
.mod
== 3)
12879 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
12882 OP_E (bytemode
, sizeflag
);
12886 OP_0f07 (int bytemode
, int sizeflag
)
12888 if (modrm
.mod
!= 3 || modrm
.rm
!= 0)
12891 OP_E (bytemode
, sizeflag
);
12894 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
12895 32bit mode and "xchg %rax,%rax" in 64bit mode. */
12898 NOP_Fixup1 (int bytemode
, int sizeflag
)
12900 if ((prefixes
& PREFIX_DATA
) != 0
12903 && address_mode
== mode_64bit
))
12904 OP_REG (bytemode
, sizeflag
);
12906 strcpy (obuf
, "nop");
12910 NOP_Fixup2 (int bytemode
, int sizeflag
)
12912 if ((prefixes
& PREFIX_DATA
) != 0
12915 && address_mode
== mode_64bit
))
12916 OP_IMREG (bytemode
, sizeflag
);
12919 static const char *const Suffix3DNow
[] = {
12920 /* 00 */ NULL
, NULL
, NULL
, NULL
,
12921 /* 04 */ NULL
, NULL
, NULL
, NULL
,
12922 /* 08 */ NULL
, NULL
, NULL
, NULL
,
12923 /* 0C */ "pi2fw", "pi2fd", NULL
, NULL
,
12924 /* 10 */ NULL
, NULL
, NULL
, NULL
,
12925 /* 14 */ NULL
, NULL
, NULL
, NULL
,
12926 /* 18 */ NULL
, NULL
, NULL
, NULL
,
12927 /* 1C */ "pf2iw", "pf2id", NULL
, NULL
,
12928 /* 20 */ NULL
, NULL
, NULL
, NULL
,
12929 /* 24 */ NULL
, NULL
, NULL
, NULL
,
12930 /* 28 */ NULL
, NULL
, NULL
, NULL
,
12931 /* 2C */ NULL
, NULL
, NULL
, NULL
,
12932 /* 30 */ NULL
, NULL
, NULL
, NULL
,
12933 /* 34 */ NULL
, NULL
, NULL
, NULL
,
12934 /* 38 */ NULL
, NULL
, NULL
, NULL
,
12935 /* 3C */ NULL
, NULL
, NULL
, NULL
,
12936 /* 40 */ NULL
, NULL
, NULL
, NULL
,
12937 /* 44 */ NULL
, NULL
, NULL
, NULL
,
12938 /* 48 */ NULL
, NULL
, NULL
, NULL
,
12939 /* 4C */ NULL
, NULL
, NULL
, NULL
,
12940 /* 50 */ NULL
, NULL
, NULL
, NULL
,
12941 /* 54 */ NULL
, NULL
, NULL
, NULL
,
12942 /* 58 */ NULL
, NULL
, NULL
, NULL
,
12943 /* 5C */ NULL
, NULL
, NULL
, NULL
,
12944 /* 60 */ NULL
, NULL
, NULL
, NULL
,
12945 /* 64 */ NULL
, NULL
, NULL
, NULL
,
12946 /* 68 */ NULL
, NULL
, NULL
, NULL
,
12947 /* 6C */ NULL
, NULL
, NULL
, NULL
,
12948 /* 70 */ NULL
, NULL
, NULL
, NULL
,
12949 /* 74 */ NULL
, NULL
, NULL
, NULL
,
12950 /* 78 */ NULL
, NULL
, NULL
, NULL
,
12951 /* 7C */ NULL
, NULL
, NULL
, NULL
,
12952 /* 80 */ NULL
, NULL
, NULL
, NULL
,
12953 /* 84 */ NULL
, NULL
, NULL
, NULL
,
12954 /* 88 */ NULL
, NULL
, "pfnacc", NULL
,
12955 /* 8C */ NULL
, NULL
, "pfpnacc", NULL
,
12956 /* 90 */ "pfcmpge", NULL
, NULL
, NULL
,
12957 /* 94 */ "pfmin", NULL
, "pfrcp", "pfrsqrt",
12958 /* 98 */ NULL
, NULL
, "pfsub", NULL
,
12959 /* 9C */ NULL
, NULL
, "pfadd", NULL
,
12960 /* A0 */ "pfcmpgt", NULL
, NULL
, NULL
,
12961 /* A4 */ "pfmax", NULL
, "pfrcpit1", "pfrsqit1",
12962 /* A8 */ NULL
, NULL
, "pfsubr", NULL
,
12963 /* AC */ NULL
, NULL
, "pfacc", NULL
,
12964 /* B0 */ "pfcmpeq", NULL
, NULL
, NULL
,
12965 /* B4 */ "pfmul", NULL
, "pfrcpit2", "pmulhrw",
12966 /* B8 */ NULL
, NULL
, NULL
, "pswapd",
12967 /* BC */ NULL
, NULL
, NULL
, "pavgusb",
12968 /* C0 */ NULL
, NULL
, NULL
, NULL
,
12969 /* C4 */ NULL
, NULL
, NULL
, NULL
,
12970 /* C8 */ NULL
, NULL
, NULL
, NULL
,
12971 /* CC */ NULL
, NULL
, NULL
, NULL
,
12972 /* D0 */ NULL
, NULL
, NULL
, NULL
,
12973 /* D4 */ NULL
, NULL
, NULL
, NULL
,
12974 /* D8 */ NULL
, NULL
, NULL
, NULL
,
12975 /* DC */ NULL
, NULL
, NULL
, NULL
,
12976 /* E0 */ NULL
, NULL
, NULL
, NULL
,
12977 /* E4 */ NULL
, NULL
, NULL
, NULL
,
12978 /* E8 */ NULL
, NULL
, NULL
, NULL
,
12979 /* EC */ NULL
, NULL
, NULL
, NULL
,
12980 /* F0 */ NULL
, NULL
, NULL
, NULL
,
12981 /* F4 */ NULL
, NULL
, NULL
, NULL
,
12982 /* F8 */ NULL
, NULL
, NULL
, NULL
,
12983 /* FC */ NULL
, NULL
, NULL
, NULL
,
12987 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12989 const char *mnemonic
;
12991 FETCH_DATA (the_info
, codep
+ 1);
12992 /* AMD 3DNow! instructions are specified by an opcode suffix in the
12993 place where an 8-bit immediate would normally go. ie. the last
12994 byte of the instruction. */
12995 obufp
= mnemonicendp
;
12996 mnemonic
= Suffix3DNow
[*codep
++ & 0xff];
12998 oappend (mnemonic
);
13001 /* Since a variable sized modrm/sib chunk is between the start
13002 of the opcode (0x0f0f) and the opcode suffix, we need to do
13003 all the modrm processing first, and don't know until now that
13004 we have a bad opcode. This necessitates some cleaning up. */
13005 op_out
[0][0] = '\0';
13006 op_out
[1][0] = '\0';
13009 mnemonicendp
= obufp
;
13012 static const struct op simd_cmp_op
[] =
13014 { STRING_COMMA_LEN ("eq") },
13015 { STRING_COMMA_LEN ("lt") },
13016 { STRING_COMMA_LEN ("le") },
13017 { STRING_COMMA_LEN ("unord") },
13018 { STRING_COMMA_LEN ("neq") },
13019 { STRING_COMMA_LEN ("nlt") },
13020 { STRING_COMMA_LEN ("nle") },
13021 { STRING_COMMA_LEN ("ord") }
13024 static const struct op vex_cmp_op
[] =
13026 { STRING_COMMA_LEN ("eq_uq") },
13027 { STRING_COMMA_LEN ("nge") },
13028 { STRING_COMMA_LEN ("ngt") },
13029 { STRING_COMMA_LEN ("false") },
13030 { STRING_COMMA_LEN ("neq_oq") },
13031 { STRING_COMMA_LEN ("ge") },
13032 { STRING_COMMA_LEN ("gt") },
13033 { STRING_COMMA_LEN ("true") },
13034 { STRING_COMMA_LEN ("eq_os") },
13035 { STRING_COMMA_LEN ("lt_oq") },
13036 { STRING_COMMA_LEN ("le_oq") },
13037 { STRING_COMMA_LEN ("unord_s") },
13038 { STRING_COMMA_LEN ("neq_us") },
13039 { STRING_COMMA_LEN ("nlt_uq") },
13040 { STRING_COMMA_LEN ("nle_uq") },
13041 { STRING_COMMA_LEN ("ord_s") },
13042 { STRING_COMMA_LEN ("eq_us") },
13043 { STRING_COMMA_LEN ("nge_uq") },
13044 { STRING_COMMA_LEN ("ngt_uq") },
13045 { STRING_COMMA_LEN ("false_os") },
13046 { STRING_COMMA_LEN ("neq_os") },
13047 { STRING_COMMA_LEN ("ge_oq") },
13048 { STRING_COMMA_LEN ("gt_oq") },
13049 { STRING_COMMA_LEN ("true_us") },
13053 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13055 unsigned int cmp_type
;
13057 FETCH_DATA (the_info
, codep
+ 1);
13058 cmp_type
= *codep
++ & 0xff;
13059 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
))
13062 char *p
= mnemonicendp
- 2;
13066 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
13067 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
13070 && cmp_type
< ARRAY_SIZE (simd_cmp_op
) + ARRAY_SIZE (vex_cmp_op
))
13073 char *p
= mnemonicendp
- 2;
13077 cmp_type
-= ARRAY_SIZE (simd_cmp_op
);
13078 sprintf (p
, "%s%s", vex_cmp_op
[cmp_type
].name
, suffix
);
13079 mnemonicendp
+= vex_cmp_op
[cmp_type
].len
;
13083 /* We have a reserved extension byte. Output it directly. */
13084 scratchbuf
[0] = '$';
13085 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
13086 oappend_maybe_intel (scratchbuf
);
13087 scratchbuf
[0] = '\0';
13092 OP_Mwait (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
13094 /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx */
13097 strcpy (op_out
[0], names32
[0]);
13098 strcpy (op_out
[1], names32
[1]);
13099 if (bytemode
== eBX_reg
)
13100 strcpy (op_out
[2], names32
[3]);
13101 two_source_ops
= 1;
13103 /* Skip mod/rm byte. */
13109 OP_Monitor (int bytemode ATTRIBUTE_UNUSED
,
13110 int sizeflag ATTRIBUTE_UNUSED
)
13112 /* monitor %{e,r,}ax,%ecx,%edx" */
13115 const char **names
= (address_mode
== mode_64bit
13116 ? names64
: names32
);
13118 if (prefixes
& PREFIX_ADDR
)
13120 /* Remove "addr16/addr32". */
13121 all_prefixes
[last_addr_prefix
] = 0;
13122 names
= (address_mode
!= mode_32bit
13123 ? names32
: names16
);
13124 used_prefixes
|= PREFIX_ADDR
;
13126 else if (address_mode
== mode_16bit
)
13128 strcpy (op_out
[0], names
[0]);
13129 strcpy (op_out
[1], names32
[1]);
13130 strcpy (op_out
[2], names32
[2]);
13131 two_source_ops
= 1;
13133 /* Skip mod/rm byte. */
13141 /* Throw away prefixes and 1st. opcode byte. */
13142 codep
= insn_codep
+ 1;
13147 REP_Fixup (int bytemode
, int sizeflag
)
13149 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
13151 if (prefixes
& PREFIX_REPZ
)
13152 all_prefixes
[last_repz_prefix
] = REP_PREFIX
;
13159 OP_IMREG (bytemode
, sizeflag
);
13162 OP_ESreg (bytemode
, sizeflag
);
13165 OP_DSreg (bytemode
, sizeflag
);
13174 SEP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13176 if ( isa64
!= amd64
)
13181 mnemonicendp
= obufp
;
13185 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
13189 BND_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13191 if (prefixes
& PREFIX_REPNZ
)
13192 all_prefixes
[last_repnz_prefix
] = BND_PREFIX
;
13195 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
13199 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED
,
13200 int sizeflag ATTRIBUTE_UNUSED
)
13203 /* Since active_seg_prefix is not set in 64-bit mode, check whether
13204 we've seen a PREFIX_DS. */
13205 if ((prefixes
& PREFIX_DS
) != 0
13206 && (address_mode
!= mode_64bit
|| last_data_prefix
< 0))
13208 /* NOTRACK prefix is only valid on indirect branch instructions.
13209 NB: DATA prefix is unsupported for Intel64. */
13210 active_seg_prefix
= 0;
13211 all_prefixes
[last_seg_prefix
] = NOTRACK_PREFIX
;
13215 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
13216 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
13220 HLE_Fixup1 (int bytemode
, int sizeflag
)
13223 && (prefixes
& PREFIX_LOCK
) != 0)
13225 if (prefixes
& PREFIX_REPZ
)
13226 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
13227 if (prefixes
& PREFIX_REPNZ
)
13228 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
13231 OP_E (bytemode
, sizeflag
);
13234 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
13235 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
13239 HLE_Fixup2 (int bytemode
, int sizeflag
)
13241 if (modrm
.mod
!= 3)
13243 if (prefixes
& PREFIX_REPZ
)
13244 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
13245 if (prefixes
& PREFIX_REPNZ
)
13246 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
13249 OP_E (bytemode
, sizeflag
);
13252 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
13253 "xrelease" for memory operand. No check for LOCK prefix. */
13256 HLE_Fixup3 (int bytemode
, int sizeflag
)
13259 && last_repz_prefix
> last_repnz_prefix
13260 && (prefixes
& PREFIX_REPZ
) != 0)
13261 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
13263 OP_E (bytemode
, sizeflag
);
13267 CMPXCHG8B_Fixup (int bytemode
, int sizeflag
)
13272 /* Change cmpxchg8b to cmpxchg16b. */
13273 char *p
= mnemonicendp
- 2;
13274 mnemonicendp
= stpcpy (p
, "16b");
13277 else if ((prefixes
& PREFIX_LOCK
) != 0)
13279 if (prefixes
& PREFIX_REPZ
)
13280 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
13281 if (prefixes
& PREFIX_REPNZ
)
13282 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
13285 OP_M (bytemode
, sizeflag
);
13289 XMM_Fixup (int reg
, int sizeflag ATTRIBUTE_UNUSED
)
13291 const char **names
;
13295 switch (vex
.length
)
13309 oappend (names
[reg
]);
13313 FXSAVE_Fixup (int bytemode
, int sizeflag
)
13315 /* Add proper suffix to "fxsave" and "fxrstor". */
13319 char *p
= mnemonicendp
;
13325 OP_M (bytemode
, sizeflag
);
13328 /* Display the destination register operand for instructions with
13332 OP_VEX (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
13334 int reg
, modrm_reg
, sib_index
= -1;
13335 const char **names
;
13340 reg
= vex
.register_specifier
;
13341 vex
.register_specifier
= 0;
13342 if (address_mode
!= mode_64bit
)
13344 else if (vex
.evex
&& !vex
.v
)
13349 case vex_scalar_mode
:
13350 oappend (names_xmm
[reg
]);
13353 case vex_vsib_d_w_dq_mode
:
13354 case vex_vsib_q_w_dq_mode
:
13355 /* This must be the 3rd operand. */
13356 if (obufp
!= op_out
[2])
13358 if (vex
.length
== 128
13359 || (bytemode
!= vex_vsib_d_w_dq_mode
13361 oappend (names_xmm
[reg
]);
13363 oappend (names_ymm
[reg
]);
13365 /* All 3 XMM/YMM registers must be distinct. */
13366 modrm_reg
= modrm
.reg
;
13372 sib_index
= sib
.index
;
13377 if (reg
== modrm_reg
|| reg
== sib_index
)
13378 strcpy (obufp
, "/(bad)");
13379 if (modrm_reg
== sib_index
|| modrm_reg
== reg
)
13380 strcat (op_out
[0], "/(bad)");
13381 if (sib_index
== modrm_reg
|| sib_index
== reg
)
13382 strcat (op_out
[1], "/(bad)");
13387 /* All 3 TMM registers must be distinct. */
13392 /* This must be the 3rd operand. */
13393 if (obufp
!= op_out
[2])
13395 oappend (names_tmm
[reg
]);
13396 if (reg
== modrm
.reg
|| reg
== modrm
.rm
)
13397 strcpy (obufp
, "/(bad)");
13400 if (modrm
.reg
== modrm
.rm
|| modrm
.reg
== reg
|| modrm
.rm
== reg
)
13403 && (modrm
.reg
== modrm
.rm
|| modrm
.reg
== reg
))
13404 strcat (op_out
[0], "/(bad)");
13406 && (modrm
.rm
== modrm
.reg
|| modrm
.rm
== reg
))
13407 strcat (op_out
[1], "/(bad)");
13413 switch (vex
.length
)
13434 names
= names_mask
;
13454 names
= names_mask
;
13457 /* See PR binutils/20893 for a reproducer. */
13469 oappend (names
[reg
]);
13473 OP_VexR (int bytemode
, int sizeflag
)
13475 if (modrm
.mod
== 3)
13476 OP_VEX (bytemode
, sizeflag
);
13480 OP_VexW (int bytemode
, int sizeflag
)
13482 OP_VEX (bytemode
, sizeflag
);
13486 /* Swap 2nd and 3rd operands. */
13487 strcpy (scratchbuf
, op_out
[2]);
13488 strcpy (op_out
[2], op_out
[1]);
13489 strcpy (op_out
[1], scratchbuf
);
13494 OP_REG_VexI4 (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
13497 const char **names
= names_xmm
;
13499 FETCH_DATA (the_info
, codep
+ 1);
13502 if (bytemode
!= x_mode
&& bytemode
!= scalar_mode
)
13506 if (address_mode
!= mode_64bit
)
13509 if (bytemode
== x_mode
&& vex
.length
== 256)
13512 oappend (names
[reg
]);
13516 /* Swap 3rd and 4th operands. */
13517 strcpy (scratchbuf
, op_out
[3]);
13518 strcpy (op_out
[3], op_out
[2]);
13519 strcpy (op_out
[2], scratchbuf
);
13524 OP_VexI4 (int bytemode ATTRIBUTE_UNUSED
,
13525 int sizeflag ATTRIBUTE_UNUSED
)
13527 scratchbuf
[0] = '$';
13528 print_operand_value (scratchbuf
+ 1, 1, codep
[-1] & 0xf);
13529 oappend_maybe_intel (scratchbuf
);
13533 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
,
13534 int sizeflag ATTRIBUTE_UNUSED
)
13536 unsigned int cmp_type
;
13541 FETCH_DATA (the_info
, codep
+ 1);
13542 cmp_type
= *codep
++ & 0xff;
13543 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
13544 If it's the case, print suffix, otherwise - print the immediate. */
13545 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
)
13550 char *p
= mnemonicendp
- 2;
13552 /* vpcmp* can have both one- and two-lettered suffix. */
13566 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
13567 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
13571 /* We have a reserved extension byte. Output it directly. */
13572 scratchbuf
[0] = '$';
13573 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
13574 oappend_maybe_intel (scratchbuf
);
13575 scratchbuf
[0] = '\0';
13579 static const struct op xop_cmp_op
[] =
13581 { STRING_COMMA_LEN ("lt") },
13582 { STRING_COMMA_LEN ("le") },
13583 { STRING_COMMA_LEN ("gt") },
13584 { STRING_COMMA_LEN ("ge") },
13585 { STRING_COMMA_LEN ("eq") },
13586 { STRING_COMMA_LEN ("neq") },
13587 { STRING_COMMA_LEN ("false") },
13588 { STRING_COMMA_LEN ("true") }
13592 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED
,
13593 int sizeflag ATTRIBUTE_UNUSED
)
13595 unsigned int cmp_type
;
13597 FETCH_DATA (the_info
, codep
+ 1);
13598 cmp_type
= *codep
++ & 0xff;
13599 if (cmp_type
< ARRAY_SIZE (xop_cmp_op
))
13602 char *p
= mnemonicendp
- 2;
13604 /* vpcom* can have both one- and two-lettered suffix. */
13618 sprintf (p
, "%s%s", xop_cmp_op
[cmp_type
].name
, suffix
);
13619 mnemonicendp
+= xop_cmp_op
[cmp_type
].len
;
13623 /* We have a reserved extension byte. Output it directly. */
13624 scratchbuf
[0] = '$';
13625 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
13626 oappend_maybe_intel (scratchbuf
);
13627 scratchbuf
[0] = '\0';
13631 static const struct op pclmul_op
[] =
13633 { STRING_COMMA_LEN ("lql") },
13634 { STRING_COMMA_LEN ("hql") },
13635 { STRING_COMMA_LEN ("lqh") },
13636 { STRING_COMMA_LEN ("hqh") }
13640 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED
,
13641 int sizeflag ATTRIBUTE_UNUSED
)
13643 unsigned int pclmul_type
;
13645 FETCH_DATA (the_info
, codep
+ 1);
13646 pclmul_type
= *codep
++ & 0xff;
13647 switch (pclmul_type
)
13658 if (pclmul_type
< ARRAY_SIZE (pclmul_op
))
13661 char *p
= mnemonicendp
- 3;
13666 sprintf (p
, "%s%s", pclmul_op
[pclmul_type
].name
, suffix
);
13667 mnemonicendp
+= pclmul_op
[pclmul_type
].len
;
13671 /* We have a reserved extension byte. Output it directly. */
13672 scratchbuf
[0] = '$';
13673 print_operand_value (scratchbuf
+ 1, 1, pclmul_type
);
13674 oappend_maybe_intel (scratchbuf
);
13675 scratchbuf
[0] = '\0';
13680 MOVSXD_Fixup (int bytemode
, int sizeflag
)
13682 /* Add proper suffix to "movsxd". */
13683 char *p
= mnemonicendp
;
13708 oappend (INTERNAL_DISASSEMBLER_ERROR
);
13715 OP_E (bytemode
, sizeflag
);
13719 OP_Rounding (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
13721 if (modrm
.mod
== 3 && vex
.b
)
13724 case evex_rounding_64_mode
:
13725 if (address_mode
!= mode_64bit
|| !vex
.w
)
13730 /* Fall through. */
13731 case evex_rounding_mode
:
13732 oappend (names_rounding
[vex
.ll
]);
13734 case evex_sae_mode
: