1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2015 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
38 #include "opcode/i386.h"
39 #include "libiberty.h"
43 static int print_insn (bfd_vma
, disassemble_info
*);
44 static void dofloat (int);
45 static void OP_ST (int, int);
46 static void OP_STi (int, int);
47 static int putop (const char *, int);
48 static void oappend (const char *);
49 static void append_seg (void);
50 static void OP_indirE (int, int);
51 static void print_operand_value (char *, int, bfd_vma
);
52 static void OP_E_register (int, int);
53 static void OP_E_memory (int, int);
54 static void print_displacement (char *, bfd_vma
);
55 static void OP_E (int, int);
56 static void OP_G (int, int);
57 static bfd_vma
get64 (void);
58 static bfd_signed_vma
get32 (void);
59 static bfd_signed_vma
get32s (void);
60 static int get16 (void);
61 static void set_op (bfd_vma
, int);
62 static void OP_Skip_MODRM (int, int);
63 static void OP_REG (int, int);
64 static void OP_IMREG (int, int);
65 static void OP_I (int, int);
66 static void OP_I64 (int, int);
67 static void OP_sI (int, int);
68 static void OP_J (int, int);
69 static void OP_SEG (int, int);
70 static void OP_DIR (int, int);
71 static void OP_OFF (int, int);
72 static void OP_OFF64 (int, int);
73 static void ptr_reg (int, int);
74 static void OP_ESreg (int, int);
75 static void OP_DSreg (int, int);
76 static void OP_C (int, int);
77 static void OP_D (int, int);
78 static void OP_T (int, int);
79 static void OP_R (int, int);
80 static void OP_MMX (int, int);
81 static void OP_XMM (int, int);
82 static void OP_EM (int, int);
83 static void OP_EX (int, int);
84 static void OP_EMC (int,int);
85 static void OP_MXC (int,int);
86 static void OP_MS (int, int);
87 static void OP_XS (int, int);
88 static void OP_M (int, int);
89 static void OP_VEX (int, int);
90 static void OP_EX_Vex (int, int);
91 static void OP_EX_VexW (int, int);
92 static void OP_EX_VexImmW (int, int);
93 static void OP_XMM_Vex (int, int);
94 static void OP_XMM_VexW (int, int);
95 static void OP_Rounding (int, int);
96 static void OP_REG_VexI4 (int, int);
97 static void PCLMUL_Fixup (int, int);
98 static void VEXI4_Fixup (int, int);
99 static void VZERO_Fixup (int, int);
100 static void VCMP_Fixup (int, int);
101 static void VPCMP_Fixup (int, int);
102 static void OP_0f07 (int, int);
103 static void OP_Monitor (int, int);
104 static void OP_Mwait (int, int);
105 static void OP_Mwaitx (int, int);
106 static void NOP_Fixup1 (int, int);
107 static void NOP_Fixup2 (int, int);
108 static void OP_3DNowSuffix (int, int);
109 static void CMP_Fixup (int, int);
110 static void BadOp (void);
111 static void REP_Fixup (int, int);
112 static void BND_Fixup (int, int);
113 static void HLE_Fixup1 (int, int);
114 static void HLE_Fixup2 (int, int);
115 static void HLE_Fixup3 (int, int);
116 static void CMPXCHG8B_Fixup (int, int);
117 static void XMM_Fixup (int, int);
118 static void CRC32_Fixup (int, int);
119 static void FXSAVE_Fixup (int, int);
120 static void OP_LWPCB_E (int, int);
121 static void OP_LWP_E (int, int);
122 static void OP_Vex_2src_1 (int, int);
123 static void OP_Vex_2src_2 (int, int);
125 static void MOVBE_Fixup (int, int);
127 static void OP_Mask (int, int);
130 /* Points to first byte not fetched. */
131 bfd_byte
*max_fetched
;
132 bfd_byte the_buffer
[MAX_MNEM_SIZE
];
135 OPCODES_SIGJMP_BUF bailout
;
145 enum address_mode address_mode
;
147 /* Flags for the prefixes for the current instruction. See below. */
150 /* REX prefix the current instruction. See below. */
152 /* Bits of REX we've already used. */
154 /* REX bits in original REX prefix ignored. */
155 static int rex_ignored
;
156 /* Mark parts used in the REX prefix. When we are testing for
157 empty prefix (for 8bit register REX extension), just mask it
158 out. Otherwise test for REX bit is excuse for existence of REX
159 only in case value is nonzero. */
160 #define USED_REX(value) \
165 rex_used |= (value) | REX_OPCODE; \
168 rex_used |= REX_OPCODE; \
171 /* Flags for prefixes which we somehow handled when printing the
172 current instruction. */
173 static int used_prefixes
;
175 /* Flags stored in PREFIXES. */
176 #define PREFIX_REPZ 1
177 #define PREFIX_REPNZ 2
178 #define PREFIX_LOCK 4
180 #define PREFIX_SS 0x10
181 #define PREFIX_DS 0x20
182 #define PREFIX_ES 0x40
183 #define PREFIX_FS 0x80
184 #define PREFIX_GS 0x100
185 #define PREFIX_DATA 0x200
186 #define PREFIX_ADDR 0x400
187 #define PREFIX_FWAIT 0x800
189 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
190 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
192 #define FETCH_DATA(info, addr) \
193 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
194 ? 1 : fetch_data ((info), (addr)))
197 fetch_data (struct disassemble_info
*info
, bfd_byte
*addr
)
200 struct dis_private
*priv
= (struct dis_private
*) info
->private_data
;
201 bfd_vma start
= priv
->insn_start
+ (priv
->max_fetched
- priv
->the_buffer
);
203 if (addr
<= priv
->the_buffer
+ MAX_MNEM_SIZE
)
204 status
= (*info
->read_memory_func
) (start
,
206 addr
- priv
->max_fetched
,
212 /* If we did manage to read at least one byte, then
213 print_insn_i386 will do something sensible. Otherwise, print
214 an error. We do that here because this is where we know
216 if (priv
->max_fetched
== priv
->the_buffer
)
217 (*info
->memory_error_func
) (status
, start
, info
);
218 OPCODES_SIGLONGJMP (priv
->bailout
, 1);
221 priv
->max_fetched
= addr
;
225 /* Possible values for prefix requirement. */
226 #define PREFIX_IGNORED_SHIFT 16
227 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
228 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
229 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
230 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
231 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
233 /* Opcode prefixes. */
234 #define PREFIX_OPCODE (PREFIX_REPZ \
238 /* Prefixes ignored. */
239 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
240 | PREFIX_IGNORED_REPNZ \
241 | PREFIX_IGNORED_DATA)
243 #define XX { NULL, 0 }
244 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
246 #define Eb { OP_E, b_mode }
247 #define Ebnd { OP_E, bnd_mode }
248 #define EbS { OP_E, b_swap_mode }
249 #define Ev { OP_E, v_mode }
250 #define Ev_bnd { OP_E, v_bnd_mode }
251 #define EvS { OP_E, v_swap_mode }
252 #define Ed { OP_E, d_mode }
253 #define Edq { OP_E, dq_mode }
254 #define Edqw { OP_E, dqw_mode }
255 #define EdqwS { OP_E, dqw_swap_mode }
256 #define Edqb { OP_E, dqb_mode }
257 #define Edb { OP_E, db_mode }
258 #define Edw { OP_E, dw_mode }
259 #define Edqd { OP_E, dqd_mode }
260 #define Eq { OP_E, q_mode }
261 #define indirEv { OP_indirE, stack_v_mode }
262 #define indirEp { OP_indirE, f_mode }
263 #define stackEv { OP_E, stack_v_mode }
264 #define Em { OP_E, m_mode }
265 #define Ew { OP_E, w_mode }
266 #define M { OP_M, 0 } /* lea, lgdt, etc. */
267 #define Ma { OP_M, a_mode }
268 #define Mb { OP_M, b_mode }
269 #define Md { OP_M, d_mode }
270 #define Mo { OP_M, o_mode }
271 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
272 #define Mq { OP_M, q_mode }
273 #define Mx { OP_M, x_mode }
274 #define Mxmm { OP_M, xmm_mode }
275 #define Gb { OP_G, b_mode }
276 #define Gbnd { OP_G, bnd_mode }
277 #define Gv { OP_G, v_mode }
278 #define Gd { OP_G, d_mode }
279 #define Gdq { OP_G, dq_mode }
280 #define Gm { OP_G, m_mode }
281 #define Gw { OP_G, w_mode }
282 #define Rd { OP_R, d_mode }
283 #define Rdq { OP_R, dq_mode }
284 #define Rm { OP_R, m_mode }
285 #define Ib { OP_I, b_mode }
286 #define sIb { OP_sI, b_mode } /* sign extened byte */
287 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
288 #define Iv { OP_I, v_mode }
289 #define sIv { OP_sI, v_mode }
290 #define Iq { OP_I, q_mode }
291 #define Iv64 { OP_I64, v_mode }
292 #define Iw { OP_I, w_mode }
293 #define I1 { OP_I, const_1_mode }
294 #define Jb { OP_J, b_mode }
295 #define Jv { OP_J, v_mode }
296 #define Cm { OP_C, m_mode }
297 #define Dm { OP_D, m_mode }
298 #define Td { OP_T, d_mode }
299 #define Skip_MODRM { OP_Skip_MODRM, 0 }
301 #define RMeAX { OP_REG, eAX_reg }
302 #define RMeBX { OP_REG, eBX_reg }
303 #define RMeCX { OP_REG, eCX_reg }
304 #define RMeDX { OP_REG, eDX_reg }
305 #define RMeSP { OP_REG, eSP_reg }
306 #define RMeBP { OP_REG, eBP_reg }
307 #define RMeSI { OP_REG, eSI_reg }
308 #define RMeDI { OP_REG, eDI_reg }
309 #define RMrAX { OP_REG, rAX_reg }
310 #define RMrBX { OP_REG, rBX_reg }
311 #define RMrCX { OP_REG, rCX_reg }
312 #define RMrDX { OP_REG, rDX_reg }
313 #define RMrSP { OP_REG, rSP_reg }
314 #define RMrBP { OP_REG, rBP_reg }
315 #define RMrSI { OP_REG, rSI_reg }
316 #define RMrDI { OP_REG, rDI_reg }
317 #define RMAL { OP_REG, al_reg }
318 #define RMCL { OP_REG, cl_reg }
319 #define RMDL { OP_REG, dl_reg }
320 #define RMBL { OP_REG, bl_reg }
321 #define RMAH { OP_REG, ah_reg }
322 #define RMCH { OP_REG, ch_reg }
323 #define RMDH { OP_REG, dh_reg }
324 #define RMBH { OP_REG, bh_reg }
325 #define RMAX { OP_REG, ax_reg }
326 #define RMDX { OP_REG, dx_reg }
328 #define eAX { OP_IMREG, eAX_reg }
329 #define eBX { OP_IMREG, eBX_reg }
330 #define eCX { OP_IMREG, eCX_reg }
331 #define eDX { OP_IMREG, eDX_reg }
332 #define eSP { OP_IMREG, eSP_reg }
333 #define eBP { OP_IMREG, eBP_reg }
334 #define eSI { OP_IMREG, eSI_reg }
335 #define eDI { OP_IMREG, eDI_reg }
336 #define AL { OP_IMREG, al_reg }
337 #define CL { OP_IMREG, cl_reg }
338 #define DL { OP_IMREG, dl_reg }
339 #define BL { OP_IMREG, bl_reg }
340 #define AH { OP_IMREG, ah_reg }
341 #define CH { OP_IMREG, ch_reg }
342 #define DH { OP_IMREG, dh_reg }
343 #define BH { OP_IMREG, bh_reg }
344 #define AX { OP_IMREG, ax_reg }
345 #define DX { OP_IMREG, dx_reg }
346 #define zAX { OP_IMREG, z_mode_ax_reg }
347 #define indirDX { OP_IMREG, indir_dx_reg }
349 #define Sw { OP_SEG, w_mode }
350 #define Sv { OP_SEG, v_mode }
351 #define Ap { OP_DIR, 0 }
352 #define Ob { OP_OFF64, b_mode }
353 #define Ov { OP_OFF64, v_mode }
354 #define Xb { OP_DSreg, eSI_reg }
355 #define Xv { OP_DSreg, eSI_reg }
356 #define Xz { OP_DSreg, eSI_reg }
357 #define Yb { OP_ESreg, eDI_reg }
358 #define Yv { OP_ESreg, eDI_reg }
359 #define DSBX { OP_DSreg, eBX_reg }
361 #define es { OP_REG, es_reg }
362 #define ss { OP_REG, ss_reg }
363 #define cs { OP_REG, cs_reg }
364 #define ds { OP_REG, ds_reg }
365 #define fs { OP_REG, fs_reg }
366 #define gs { OP_REG, gs_reg }
368 #define MX { OP_MMX, 0 }
369 #define XM { OP_XMM, 0 }
370 #define XMScalar { OP_XMM, scalar_mode }
371 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
372 #define XMM { OP_XMM, xmm_mode }
373 #define XMxmmq { OP_XMM, xmmq_mode }
374 #define EM { OP_EM, v_mode }
375 #define EMS { OP_EM, v_swap_mode }
376 #define EMd { OP_EM, d_mode }
377 #define EMx { OP_EM, x_mode }
378 #define EXw { OP_EX, w_mode }
379 #define EXd { OP_EX, d_mode }
380 #define EXdScalar { OP_EX, d_scalar_mode }
381 #define EXdS { OP_EX, d_swap_mode }
382 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
383 #define EXq { OP_EX, q_mode }
384 #define EXqScalar { OP_EX, q_scalar_mode }
385 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
386 #define EXqS { OP_EX, q_swap_mode }
387 #define EXx { OP_EX, x_mode }
388 #define EXxS { OP_EX, x_swap_mode }
389 #define EXxmm { OP_EX, xmm_mode }
390 #define EXymm { OP_EX, ymm_mode }
391 #define EXxmmq { OP_EX, xmmq_mode }
392 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
393 #define EXxmm_mb { OP_EX, xmm_mb_mode }
394 #define EXxmm_mw { OP_EX, xmm_mw_mode }
395 #define EXxmm_md { OP_EX, xmm_md_mode }
396 #define EXxmm_mq { OP_EX, xmm_mq_mode }
397 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
398 #define EXxmmdw { OP_EX, xmmdw_mode }
399 #define EXxmmqd { OP_EX, xmmqd_mode }
400 #define EXymmq { OP_EX, ymmq_mode }
401 #define EXVexWdq { OP_EX, vex_w_dq_mode }
402 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
403 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
404 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
405 #define MS { OP_MS, v_mode }
406 #define XS { OP_XS, v_mode }
407 #define EMCq { OP_EMC, q_mode }
408 #define MXC { OP_MXC, 0 }
409 #define OPSUF { OP_3DNowSuffix, 0 }
410 #define CMP { CMP_Fixup, 0 }
411 #define XMM0 { XMM_Fixup, 0 }
412 #define FXSAVE { FXSAVE_Fixup, 0 }
413 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
414 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
416 #define Vex { OP_VEX, vex_mode }
417 #define VexScalar { OP_VEX, vex_scalar_mode }
418 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
419 #define Vex128 { OP_VEX, vex128_mode }
420 #define Vex256 { OP_VEX, vex256_mode }
421 #define VexGdq { OP_VEX, dq_mode }
422 #define VexI4 { VEXI4_Fixup, 0}
423 #define EXdVex { OP_EX_Vex, d_mode }
424 #define EXdVexS { OP_EX_Vex, d_swap_mode }
425 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
426 #define EXqVex { OP_EX_Vex, q_mode }
427 #define EXqVexS { OP_EX_Vex, q_swap_mode }
428 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
429 #define EXVexW { OP_EX_VexW, x_mode }
430 #define EXdVexW { OP_EX_VexW, d_mode }
431 #define EXqVexW { OP_EX_VexW, q_mode }
432 #define EXVexImmW { OP_EX_VexImmW, x_mode }
433 #define XMVex { OP_XMM_Vex, 0 }
434 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
435 #define XMVexW { OP_XMM_VexW, 0 }
436 #define XMVexI4 { OP_REG_VexI4, x_mode }
437 #define PCLMUL { PCLMUL_Fixup, 0 }
438 #define VZERO { VZERO_Fixup, 0 }
439 #define VCMP { VCMP_Fixup, 0 }
440 #define VPCMP { VPCMP_Fixup, 0 }
442 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
443 #define EXxEVexS { OP_Rounding, evex_sae_mode }
445 #define XMask { OP_Mask, mask_mode }
446 #define MaskG { OP_G, mask_mode }
447 #define MaskE { OP_E, mask_mode }
448 #define MaskBDE { OP_E, mask_bd_mode }
449 #define MaskR { OP_R, mask_mode }
450 #define MaskVex { OP_VEX, mask_mode }
452 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
453 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
454 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
455 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
457 /* Used handle "rep" prefix for string instructions. */
458 #define Xbr { REP_Fixup, eSI_reg }
459 #define Xvr { REP_Fixup, eSI_reg }
460 #define Ybr { REP_Fixup, eDI_reg }
461 #define Yvr { REP_Fixup, eDI_reg }
462 #define Yzr { REP_Fixup, eDI_reg }
463 #define indirDXr { REP_Fixup, indir_dx_reg }
464 #define ALr { REP_Fixup, al_reg }
465 #define eAXr { REP_Fixup, eAX_reg }
467 /* Used handle HLE prefix for lockable instructions. */
468 #define Ebh1 { HLE_Fixup1, b_mode }
469 #define Evh1 { HLE_Fixup1, v_mode }
470 #define Ebh2 { HLE_Fixup2, b_mode }
471 #define Evh2 { HLE_Fixup2, v_mode }
472 #define Ebh3 { HLE_Fixup3, b_mode }
473 #define Evh3 { HLE_Fixup3, v_mode }
475 #define BND { BND_Fixup, 0 }
477 #define cond_jump_flag { NULL, cond_jump_mode }
478 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
480 /* bits in sizeflag */
481 #define SUFFIX_ALWAYS 4
489 /* byte operand with operand swapped */
491 /* byte operand, sign extend like 'T' suffix */
493 /* operand size depends on prefixes */
495 /* operand size depends on prefixes with operand swapped */
499 /* double word operand */
501 /* double word operand with operand swapped */
503 /* quad word operand */
505 /* quad word operand with operand swapped */
507 /* ten-byte operand */
509 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
510 broadcast enabled. */
512 /* Similar to x_mode, but with different EVEX mem shifts. */
514 /* Similar to x_mode, but with disabled broadcast. */
516 /* Similar to x_mode, but with operands swapped and disabled broadcast
519 /* 16-byte XMM operand */
521 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
522 memory operand (depending on vector length). Broadcast isn't
525 /* Same as xmmq_mode, but broadcast is allowed. */
526 evex_half_bcst_xmmq_mode
,
527 /* XMM register or byte memory operand */
529 /* XMM register or word memory operand */
531 /* XMM register or double word memory operand */
533 /* XMM register or quad word memory operand */
535 /* XMM register or double/quad word memory operand, depending on
538 /* 16-byte XMM, word, double word or quad word operand. */
540 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
542 /* 32-byte YMM operand */
544 /* quad word, ymmword or zmmword memory operand. */
546 /* 32-byte YMM or 16-byte word operand */
548 /* d_mode in 32bit, q_mode in 64bit mode. */
550 /* pair of v_mode operands */
555 /* operand size depends on REX prefixes. */
557 /* registers like dq_mode, memory like w_mode. */
561 /* 4- or 6-byte pointer operand */
564 /* v_mode for stack-related opcodes. */
566 /* non-quad operand size depends on prefixes */
568 /* 16-byte operand */
570 /* registers like dq_mode, memory like b_mode. */
572 /* registers like d_mode, memory like b_mode. */
574 /* registers like d_mode, memory like w_mode. */
576 /* registers like dq_mode, memory like d_mode. */
578 /* normal vex mode */
580 /* 128bit vex mode */
582 /* 256bit vex mode */
584 /* operand size depends on the VEX.W bit. */
587 /* Similar to vex_w_dq_mode, with VSIB dword indices. */
588 vex_vsib_d_w_dq_mode
,
589 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
591 /* Similar to vex_w_dq_mode, with VSIB qword indices. */
592 vex_vsib_q_w_dq_mode
,
593 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
596 /* scalar, ignore vector length. */
598 /* like d_mode, ignore vector length. */
600 /* like d_swap_mode, ignore vector length. */
602 /* like q_mode, ignore vector length. */
604 /* like q_swap_mode, ignore vector length. */
606 /* like vex_mode, ignore vector length. */
608 /* like vex_w_dq_mode, ignore vector length. */
609 vex_scalar_w_dq_mode
,
611 /* Static rounding. */
613 /* Supress all exceptions. */
616 /* Mask register operand. */
618 /* Mask register operand. */
685 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
687 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
688 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
689 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
690 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
691 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
692 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
693 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
694 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
695 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
696 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
697 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
698 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
699 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
700 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
701 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
818 MOD_VEX_0F12_PREFIX_0
,
820 MOD_VEX_0F16_PREFIX_0
,
836 MOD_VEX_0FD7_PREFIX_2
,
837 MOD_VEX_0FE7_PREFIX_2
,
838 MOD_VEX_0FF0_PREFIX_3
,
839 MOD_VEX_0F381A_PREFIX_2
,
840 MOD_VEX_0F382A_PREFIX_2
,
841 MOD_VEX_0F382C_PREFIX_2
,
842 MOD_VEX_0F382D_PREFIX_2
,
843 MOD_VEX_0F382E_PREFIX_2
,
844 MOD_VEX_0F382F_PREFIX_2
,
845 MOD_VEX_0F385A_PREFIX_2
,
846 MOD_VEX_0F388C_PREFIX_2
,
847 MOD_VEX_0F388E_PREFIX_2
,
849 MOD_EVEX_0F10_PREFIX_1
,
850 MOD_EVEX_0F10_PREFIX_3
,
851 MOD_EVEX_0F11_PREFIX_1
,
852 MOD_EVEX_0F11_PREFIX_3
,
853 MOD_EVEX_0F12_PREFIX_0
,
854 MOD_EVEX_0F16_PREFIX_0
,
855 MOD_EVEX_0F38C6_REG_1
,
856 MOD_EVEX_0F38C6_REG_2
,
857 MOD_EVEX_0F38C6_REG_5
,
858 MOD_EVEX_0F38C6_REG_6
,
859 MOD_EVEX_0F38C7_REG_1
,
860 MOD_EVEX_0F38C7_REG_2
,
861 MOD_EVEX_0F38C7_REG_5
,
862 MOD_EVEX_0F38C7_REG_6
926 PREFIX_RM_0_0FAE_REG_7
,
932 PREFIX_MOD_0_0FC7_REG_6
,
933 PREFIX_MOD_3_0FC7_REG_6
,
934 PREFIX_MOD_3_0FC7_REG_7
,
1058 PREFIX_VEX_0F71_REG_2
,
1059 PREFIX_VEX_0F71_REG_4
,
1060 PREFIX_VEX_0F71_REG_6
,
1061 PREFIX_VEX_0F72_REG_2
,
1062 PREFIX_VEX_0F72_REG_4
,
1063 PREFIX_VEX_0F72_REG_6
,
1064 PREFIX_VEX_0F73_REG_2
,
1065 PREFIX_VEX_0F73_REG_3
,
1066 PREFIX_VEX_0F73_REG_6
,
1067 PREFIX_VEX_0F73_REG_7
,
1239 PREFIX_VEX_0F38F3_REG_1
,
1240 PREFIX_VEX_0F38F3_REG_2
,
1241 PREFIX_VEX_0F38F3_REG_3
,
1358 PREFIX_EVEX_0F71_REG_2
,
1359 PREFIX_EVEX_0F71_REG_4
,
1360 PREFIX_EVEX_0F71_REG_6
,
1361 PREFIX_EVEX_0F72_REG_0
,
1362 PREFIX_EVEX_0F72_REG_1
,
1363 PREFIX_EVEX_0F72_REG_2
,
1364 PREFIX_EVEX_0F72_REG_4
,
1365 PREFIX_EVEX_0F72_REG_6
,
1366 PREFIX_EVEX_0F73_REG_2
,
1367 PREFIX_EVEX_0F73_REG_3
,
1368 PREFIX_EVEX_0F73_REG_6
,
1369 PREFIX_EVEX_0F73_REG_7
,
1552 PREFIX_EVEX_0F38C6_REG_1
,
1553 PREFIX_EVEX_0F38C6_REG_2
,
1554 PREFIX_EVEX_0F38C6_REG_5
,
1555 PREFIX_EVEX_0F38C6_REG_6
,
1556 PREFIX_EVEX_0F38C7_REG_1
,
1557 PREFIX_EVEX_0F38C7_REG_2
,
1558 PREFIX_EVEX_0F38C7_REG_5
,
1559 PREFIX_EVEX_0F38C7_REG_6
,
1648 THREE_BYTE_0F38
= 0,
1676 VEX_LEN_0F10_P_1
= 0,
1680 VEX_LEN_0F12_P_0_M_0
,
1681 VEX_LEN_0F12_P_0_M_1
,
1684 VEX_LEN_0F16_P_0_M_0
,
1685 VEX_LEN_0F16_P_0_M_1
,
1749 VEX_LEN_0FAE_R_2_M_0
,
1750 VEX_LEN_0FAE_R_3_M_0
,
1759 VEX_LEN_0F381A_P_2_M_0
,
1762 VEX_LEN_0F385A_P_2_M_0
,
1769 VEX_LEN_0F38F3_R_1_P_0
,
1770 VEX_LEN_0F38F3_R_2_P_0
,
1771 VEX_LEN_0F38F3_R_3_P_0
,
1817 VEX_LEN_0FXOP_08_CC
,
1818 VEX_LEN_0FXOP_08_CD
,
1819 VEX_LEN_0FXOP_08_CE
,
1820 VEX_LEN_0FXOP_08_CF
,
1821 VEX_LEN_0FXOP_08_EC
,
1822 VEX_LEN_0FXOP_08_ED
,
1823 VEX_LEN_0FXOP_08_EE
,
1824 VEX_LEN_0FXOP_08_EF
,
1825 VEX_LEN_0FXOP_09_80
,
1859 VEX_W_0F41_P_0_LEN_1
,
1860 VEX_W_0F41_P_2_LEN_1
,
1861 VEX_W_0F42_P_0_LEN_1
,
1862 VEX_W_0F42_P_2_LEN_1
,
1863 VEX_W_0F44_P_0_LEN_0
,
1864 VEX_W_0F44_P_2_LEN_0
,
1865 VEX_W_0F45_P_0_LEN_1
,
1866 VEX_W_0F45_P_2_LEN_1
,
1867 VEX_W_0F46_P_0_LEN_1
,
1868 VEX_W_0F46_P_2_LEN_1
,
1869 VEX_W_0F47_P_0_LEN_1
,
1870 VEX_W_0F47_P_2_LEN_1
,
1871 VEX_W_0F4A_P_0_LEN_1
,
1872 VEX_W_0F4A_P_2_LEN_1
,
1873 VEX_W_0F4B_P_0_LEN_1
,
1874 VEX_W_0F4B_P_2_LEN_1
,
1954 VEX_W_0F90_P_0_LEN_0
,
1955 VEX_W_0F90_P_2_LEN_0
,
1956 VEX_W_0F91_P_0_LEN_0
,
1957 VEX_W_0F91_P_2_LEN_0
,
1958 VEX_W_0F92_P_0_LEN_0
,
1959 VEX_W_0F92_P_2_LEN_0
,
1960 VEX_W_0F92_P_3_LEN_0
,
1961 VEX_W_0F93_P_0_LEN_0
,
1962 VEX_W_0F93_P_2_LEN_0
,
1963 VEX_W_0F93_P_3_LEN_0
,
1964 VEX_W_0F98_P_0_LEN_0
,
1965 VEX_W_0F98_P_2_LEN_0
,
1966 VEX_W_0F99_P_0_LEN_0
,
1967 VEX_W_0F99_P_2_LEN_0
,
2046 VEX_W_0F381A_P_2_M_0
,
2058 VEX_W_0F382A_P_2_M_0
,
2060 VEX_W_0F382C_P_2_M_0
,
2061 VEX_W_0F382D_P_2_M_0
,
2062 VEX_W_0F382E_P_2_M_0
,
2063 VEX_W_0F382F_P_2_M_0
,
2085 VEX_W_0F385A_P_2_M_0
,
2113 VEX_W_0F3A30_P_2_LEN_0
,
2114 VEX_W_0F3A31_P_2_LEN_0
,
2115 VEX_W_0F3A32_P_2_LEN_0
,
2116 VEX_W_0F3A33_P_2_LEN_0
,
2136 EVEX_W_0F10_P_1_M_0
,
2137 EVEX_W_0F10_P_1_M_1
,
2139 EVEX_W_0F10_P_3_M_0
,
2140 EVEX_W_0F10_P_3_M_1
,
2142 EVEX_W_0F11_P_1_M_0
,
2143 EVEX_W_0F11_P_1_M_1
,
2145 EVEX_W_0F11_P_3_M_0
,
2146 EVEX_W_0F11_P_3_M_1
,
2147 EVEX_W_0F12_P_0_M_0
,
2148 EVEX_W_0F12_P_0_M_1
,
2158 EVEX_W_0F16_P_0_M_0
,
2159 EVEX_W_0F16_P_0_M_1
,
2230 EVEX_W_0F72_R_2_P_2
,
2231 EVEX_W_0F72_R_6_P_2
,
2232 EVEX_W_0F73_R_2_P_2
,
2233 EVEX_W_0F73_R_6_P_2
,
2333 EVEX_W_0F38C7_R_1_P_2
,
2334 EVEX_W_0F38C7_R_2_P_2
,
2335 EVEX_W_0F38C7_R_5_P_2
,
2336 EVEX_W_0F38C7_R_6_P_2
,
2371 typedef void (*op_rtn
) (int bytemode
, int sizeflag
);
2380 unsigned int prefix_requirement
;
2383 /* Upper case letters in the instruction names here are macros.
2384 'A' => print 'b' if no register operands or suffix_always is true
2385 'B' => print 'b' if suffix_always is true
2386 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2388 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2389 suffix_always is true
2390 'E' => print 'e' if 32-bit form of jcxz
2391 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2392 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2393 'H' => print ",pt" or ",pn" branch hint
2394 'I' => honor following macro letter even in Intel mode (implemented only
2395 for some of the macro letters)
2397 'K' => print 'd' or 'q' if rex prefix is present.
2398 'L' => print 'l' if suffix_always is true
2399 'M' => print 'r' if intel_mnemonic is false.
2400 'N' => print 'n' if instruction has no wait "prefix"
2401 'O' => print 'd' or 'o' (or 'q' in Intel mode)
2402 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2403 or suffix_always is true. print 'q' if rex prefix is present.
2404 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2406 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2407 'S' => print 'w', 'l' or 'q' if suffix_always is true
2408 'T' => print 'q' in 64bit mode if instruction has no operand size
2409 prefix and behave as 'P' otherwise
2410 'U' => print 'q' in 64bit mode if instruction has no operand size
2411 prefix and behave as 'Q' otherwise
2412 'V' => print 'q' in 64bit mode if instruction has no operand size
2413 prefix and behave as 'S' otherwise
2414 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2415 'X' => print 's', 'd' depending on data16 prefix (for XMM)
2416 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2417 suffix_always is true.
2418 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2419 '!' => change condition from true to false or from false to true.
2420 '%' => add 1 upper case letter to the macro.
2421 '^' => print 'w' or 'l' depending on operand size prefix or
2422 suffix_always is true (lcall/ljmp).
2423 '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2424 on operand size prefix.
2426 2 upper case letter macros:
2427 "XY" => print 'x' or 'y' if suffix_always is true or no register
2428 operands and no broadcast.
2429 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2430 register operands and no broadcast.
2431 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2432 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2433 or suffix_always is true
2434 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2435 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2436 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2437 "LW" => print 'd', 'q' depending on the VEX.W bit
2438 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2439 an operand size prefix, or suffix_always is true. print
2440 'q' if rex prefix is present.
2442 Many of the above letters print nothing in Intel mode. See "putop"
2445 Braces '{' and '}', and vertical bars '|', indicate alternative
2446 mnemonic strings for AT&T and Intel. */
2448 static const struct dis386 dis386
[] = {
2450 { "addB", { Ebh1
, Gb
}, 0 },
2451 { "addS", { Evh1
, Gv
}, 0 },
2452 { "addB", { Gb
, EbS
}, 0 },
2453 { "addS", { Gv
, EvS
}, 0 },
2454 { "addB", { AL
, Ib
}, 0 },
2455 { "addS", { eAX
, Iv
}, 0 },
2456 { X86_64_TABLE (X86_64_06
) },
2457 { X86_64_TABLE (X86_64_07
) },
2459 { "orB", { Ebh1
, Gb
}, 0 },
2460 { "orS", { Evh1
, Gv
}, 0 },
2461 { "orB", { Gb
, EbS
}, 0 },
2462 { "orS", { Gv
, EvS
}, 0 },
2463 { "orB", { AL
, Ib
}, 0 },
2464 { "orS", { eAX
, Iv
}, 0 },
2465 { X86_64_TABLE (X86_64_0D
) },
2466 { Bad_Opcode
}, /* 0x0f extended opcode escape */
2468 { "adcB", { Ebh1
, Gb
}, 0 },
2469 { "adcS", { Evh1
, Gv
}, 0 },
2470 { "adcB", { Gb
, EbS
}, 0 },
2471 { "adcS", { Gv
, EvS
}, 0 },
2472 { "adcB", { AL
, Ib
}, 0 },
2473 { "adcS", { eAX
, Iv
}, 0 },
2474 { X86_64_TABLE (X86_64_16
) },
2475 { X86_64_TABLE (X86_64_17
) },
2477 { "sbbB", { Ebh1
, Gb
}, 0 },
2478 { "sbbS", { Evh1
, Gv
}, 0 },
2479 { "sbbB", { Gb
, EbS
}, 0 },
2480 { "sbbS", { Gv
, EvS
}, 0 },
2481 { "sbbB", { AL
, Ib
}, 0 },
2482 { "sbbS", { eAX
, Iv
}, 0 },
2483 { X86_64_TABLE (X86_64_1E
) },
2484 { X86_64_TABLE (X86_64_1F
) },
2486 { "andB", { Ebh1
, Gb
}, 0 },
2487 { "andS", { Evh1
, Gv
}, 0 },
2488 { "andB", { Gb
, EbS
}, 0 },
2489 { "andS", { Gv
, EvS
}, 0 },
2490 { "andB", { AL
, Ib
}, 0 },
2491 { "andS", { eAX
, Iv
}, 0 },
2492 { Bad_Opcode
}, /* SEG ES prefix */
2493 { X86_64_TABLE (X86_64_27
) },
2495 { "subB", { Ebh1
, Gb
}, 0 },
2496 { "subS", { Evh1
, Gv
}, 0 },
2497 { "subB", { Gb
, EbS
}, 0 },
2498 { "subS", { Gv
, EvS
}, 0 },
2499 { "subB", { AL
, Ib
}, 0 },
2500 { "subS", { eAX
, Iv
}, 0 },
2501 { Bad_Opcode
}, /* SEG CS prefix */
2502 { X86_64_TABLE (X86_64_2F
) },
2504 { "xorB", { Ebh1
, Gb
}, 0 },
2505 { "xorS", { Evh1
, Gv
}, 0 },
2506 { "xorB", { Gb
, EbS
}, 0 },
2507 { "xorS", { Gv
, EvS
}, 0 },
2508 { "xorB", { AL
, Ib
}, 0 },
2509 { "xorS", { eAX
, Iv
}, 0 },
2510 { Bad_Opcode
}, /* SEG SS prefix */
2511 { X86_64_TABLE (X86_64_37
) },
2513 { "cmpB", { Eb
, Gb
}, 0 },
2514 { "cmpS", { Ev
, Gv
}, 0 },
2515 { "cmpB", { Gb
, EbS
}, 0 },
2516 { "cmpS", { Gv
, EvS
}, 0 },
2517 { "cmpB", { AL
, Ib
}, 0 },
2518 { "cmpS", { eAX
, Iv
}, 0 },
2519 { Bad_Opcode
}, /* SEG DS prefix */
2520 { X86_64_TABLE (X86_64_3F
) },
2522 { "inc{S|}", { RMeAX
}, 0 },
2523 { "inc{S|}", { RMeCX
}, 0 },
2524 { "inc{S|}", { RMeDX
}, 0 },
2525 { "inc{S|}", { RMeBX
}, 0 },
2526 { "inc{S|}", { RMeSP
}, 0 },
2527 { "inc{S|}", { RMeBP
}, 0 },
2528 { "inc{S|}", { RMeSI
}, 0 },
2529 { "inc{S|}", { RMeDI
}, 0 },
2531 { "dec{S|}", { RMeAX
}, 0 },
2532 { "dec{S|}", { RMeCX
}, 0 },
2533 { "dec{S|}", { RMeDX
}, 0 },
2534 { "dec{S|}", { RMeBX
}, 0 },
2535 { "dec{S|}", { RMeSP
}, 0 },
2536 { "dec{S|}", { RMeBP
}, 0 },
2537 { "dec{S|}", { RMeSI
}, 0 },
2538 { "dec{S|}", { RMeDI
}, 0 },
2540 { "pushV", { RMrAX
}, 0 },
2541 { "pushV", { RMrCX
}, 0 },
2542 { "pushV", { RMrDX
}, 0 },
2543 { "pushV", { RMrBX
}, 0 },
2544 { "pushV", { RMrSP
}, 0 },
2545 { "pushV", { RMrBP
}, 0 },
2546 { "pushV", { RMrSI
}, 0 },
2547 { "pushV", { RMrDI
}, 0 },
2549 { "popV", { RMrAX
}, 0 },
2550 { "popV", { RMrCX
}, 0 },
2551 { "popV", { RMrDX
}, 0 },
2552 { "popV", { RMrBX
}, 0 },
2553 { "popV", { RMrSP
}, 0 },
2554 { "popV", { RMrBP
}, 0 },
2555 { "popV", { RMrSI
}, 0 },
2556 { "popV", { RMrDI
}, 0 },
2558 { X86_64_TABLE (X86_64_60
) },
2559 { X86_64_TABLE (X86_64_61
) },
2560 { X86_64_TABLE (X86_64_62
) },
2561 { X86_64_TABLE (X86_64_63
) },
2562 { Bad_Opcode
}, /* seg fs */
2563 { Bad_Opcode
}, /* seg gs */
2564 { Bad_Opcode
}, /* op size prefix */
2565 { Bad_Opcode
}, /* adr size prefix */
2567 { "pushT", { sIv
}, 0 },
2568 { "imulS", { Gv
, Ev
, Iv
}, 0 },
2569 { "pushT", { sIbT
}, 0 },
2570 { "imulS", { Gv
, Ev
, sIb
}, 0 },
2571 { "ins{b|}", { Ybr
, indirDX
}, 0 },
2572 { X86_64_TABLE (X86_64_6D
) },
2573 { "outs{b|}", { indirDXr
, Xb
}, 0 },
2574 { X86_64_TABLE (X86_64_6F
) },
2576 { "joH", { Jb
, BND
, cond_jump_flag
}, 0 },
2577 { "jnoH", { Jb
, BND
, cond_jump_flag
}, 0 },
2578 { "jbH", { Jb
, BND
, cond_jump_flag
}, 0 },
2579 { "jaeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2580 { "jeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2581 { "jneH", { Jb
, BND
, cond_jump_flag
}, 0 },
2582 { "jbeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2583 { "jaH", { Jb
, BND
, cond_jump_flag
}, 0 },
2585 { "jsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2586 { "jnsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2587 { "jpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2588 { "jnpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2589 { "jlH", { Jb
, BND
, cond_jump_flag
}, 0 },
2590 { "jgeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2591 { "jleH", { Jb
, BND
, cond_jump_flag
}, 0 },
2592 { "jgH", { Jb
, BND
, cond_jump_flag
}, 0 },
2594 { REG_TABLE (REG_80
) },
2595 { REG_TABLE (REG_81
) },
2597 { REG_TABLE (REG_82
) },
2598 { "testB", { Eb
, Gb
}, 0 },
2599 { "testS", { Ev
, Gv
}, 0 },
2600 { "xchgB", { Ebh2
, Gb
}, 0 },
2601 { "xchgS", { Evh2
, Gv
}, 0 },
2603 { "movB", { Ebh3
, Gb
}, 0 },
2604 { "movS", { Evh3
, Gv
}, 0 },
2605 { "movB", { Gb
, EbS
}, 0 },
2606 { "movS", { Gv
, EvS
}, 0 },
2607 { "movD", { Sv
, Sw
}, 0 },
2608 { MOD_TABLE (MOD_8D
) },
2609 { "movD", { Sw
, Sv
}, 0 },
2610 { REG_TABLE (REG_8F
) },
2612 { PREFIX_TABLE (PREFIX_90
) },
2613 { "xchgS", { RMeCX
, eAX
}, 0 },
2614 { "xchgS", { RMeDX
, eAX
}, 0 },
2615 { "xchgS", { RMeBX
, eAX
}, 0 },
2616 { "xchgS", { RMeSP
, eAX
}, 0 },
2617 { "xchgS", { RMeBP
, eAX
}, 0 },
2618 { "xchgS", { RMeSI
, eAX
}, 0 },
2619 { "xchgS", { RMeDI
, eAX
}, 0 },
2621 { "cW{t|}R", { XX
}, 0 },
2622 { "cR{t|}O", { XX
}, 0 },
2623 { X86_64_TABLE (X86_64_9A
) },
2624 { Bad_Opcode
}, /* fwait */
2625 { "pushfT", { XX
}, 0 },
2626 { "popfT", { XX
}, 0 },
2627 { "sahf", { XX
}, 0 },
2628 { "lahf", { XX
}, 0 },
2630 { "mov%LB", { AL
, Ob
}, 0 },
2631 { "mov%LS", { eAX
, Ov
}, 0 },
2632 { "mov%LB", { Ob
, AL
}, 0 },
2633 { "mov%LS", { Ov
, eAX
}, 0 },
2634 { "movs{b|}", { Ybr
, Xb
}, 0 },
2635 { "movs{R|}", { Yvr
, Xv
}, 0 },
2636 { "cmps{b|}", { Xb
, Yb
}, 0 },
2637 { "cmps{R|}", { Xv
, Yv
}, 0 },
2639 { "testB", { AL
, Ib
}, 0 },
2640 { "testS", { eAX
, Iv
}, 0 },
2641 { "stosB", { Ybr
, AL
}, 0 },
2642 { "stosS", { Yvr
, eAX
}, 0 },
2643 { "lodsB", { ALr
, Xb
}, 0 },
2644 { "lodsS", { eAXr
, Xv
}, 0 },
2645 { "scasB", { AL
, Yb
}, 0 },
2646 { "scasS", { eAX
, Yv
}, 0 },
2648 { "movB", { RMAL
, Ib
}, 0 },
2649 { "movB", { RMCL
, Ib
}, 0 },
2650 { "movB", { RMDL
, Ib
}, 0 },
2651 { "movB", { RMBL
, Ib
}, 0 },
2652 { "movB", { RMAH
, Ib
}, 0 },
2653 { "movB", { RMCH
, Ib
}, 0 },
2654 { "movB", { RMDH
, Ib
}, 0 },
2655 { "movB", { RMBH
, Ib
}, 0 },
2657 { "mov%LV", { RMeAX
, Iv64
}, 0 },
2658 { "mov%LV", { RMeCX
, Iv64
}, 0 },
2659 { "mov%LV", { RMeDX
, Iv64
}, 0 },
2660 { "mov%LV", { RMeBX
, Iv64
}, 0 },
2661 { "mov%LV", { RMeSP
, Iv64
}, 0 },
2662 { "mov%LV", { RMeBP
, Iv64
}, 0 },
2663 { "mov%LV", { RMeSI
, Iv64
}, 0 },
2664 { "mov%LV", { RMeDI
, Iv64
}, 0 },
2666 { REG_TABLE (REG_C0
) },
2667 { REG_TABLE (REG_C1
) },
2668 { "retT", { Iw
, BND
}, 0 },
2669 { "retT", { BND
}, 0 },
2670 { X86_64_TABLE (X86_64_C4
) },
2671 { X86_64_TABLE (X86_64_C5
) },
2672 { REG_TABLE (REG_C6
) },
2673 { REG_TABLE (REG_C7
) },
2675 { "enterT", { Iw
, Ib
}, 0 },
2676 { "leaveT", { XX
}, 0 },
2677 { "Jret{|f}P", { Iw
}, 0 },
2678 { "Jret{|f}P", { XX
}, 0 },
2679 { "int3", { XX
}, 0 },
2680 { "int", { Ib
}, 0 },
2681 { X86_64_TABLE (X86_64_CE
) },
2682 { "iret%LP", { XX
}, 0 },
2684 { REG_TABLE (REG_D0
) },
2685 { REG_TABLE (REG_D1
) },
2686 { REG_TABLE (REG_D2
) },
2687 { REG_TABLE (REG_D3
) },
2688 { X86_64_TABLE (X86_64_D4
) },
2689 { X86_64_TABLE (X86_64_D5
) },
2691 { "xlat", { DSBX
}, 0 },
2702 { "loopneFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2703 { "loopeFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2704 { "loopFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2705 { "jEcxzH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2706 { "inB", { AL
, Ib
}, 0 },
2707 { "inG", { zAX
, Ib
}, 0 },
2708 { "outB", { Ib
, AL
}, 0 },
2709 { "outG", { Ib
, zAX
}, 0 },
2711 { X86_64_TABLE (X86_64_E8
) },
2712 { X86_64_TABLE (X86_64_E9
) },
2713 { X86_64_TABLE (X86_64_EA
) },
2714 { "jmp", { Jb
, BND
}, 0 },
2715 { "inB", { AL
, indirDX
}, 0 },
2716 { "inG", { zAX
, indirDX
}, 0 },
2717 { "outB", { indirDX
, AL
}, 0 },
2718 { "outG", { indirDX
, zAX
}, 0 },
2720 { Bad_Opcode
}, /* lock prefix */
2721 { "icebp", { XX
}, 0 },
2722 { Bad_Opcode
}, /* repne */
2723 { Bad_Opcode
}, /* repz */
2724 { "hlt", { XX
}, 0 },
2725 { "cmc", { XX
}, 0 },
2726 { REG_TABLE (REG_F6
) },
2727 { REG_TABLE (REG_F7
) },
2729 { "clc", { XX
}, 0 },
2730 { "stc", { XX
}, 0 },
2731 { "cli", { XX
}, 0 },
2732 { "sti", { XX
}, 0 },
2733 { "cld", { XX
}, 0 },
2734 { "std", { XX
}, 0 },
2735 { REG_TABLE (REG_FE
) },
2736 { REG_TABLE (REG_FF
) },
2739 static const struct dis386 dis386_twobyte
[] = {
2741 { REG_TABLE (REG_0F00
) },
2742 { REG_TABLE (REG_0F01
) },
2743 { "larS", { Gv
, Ew
}, 0 },
2744 { "lslS", { Gv
, Ew
}, 0 },
2746 { "syscall", { XX
}, 0 },
2747 { "clts", { XX
}, 0 },
2748 { "sysret%LP", { XX
}, 0 },
2750 { "invd", { XX
}, 0 },
2751 { "wbinvd", { XX
}, 0 },
2753 { "ud2", { XX
}, 0 },
2755 { REG_TABLE (REG_0F0D
) },
2756 { "femms", { XX
}, 0 },
2757 { "", { MX
, EM
, OPSUF
}, 0 }, /* See OP_3DNowSuffix. */
2759 { PREFIX_TABLE (PREFIX_0F10
) },
2760 { PREFIX_TABLE (PREFIX_0F11
) },
2761 { PREFIX_TABLE (PREFIX_0F12
) },
2762 { MOD_TABLE (MOD_0F13
) },
2763 { "unpcklpX", { XM
, EXx
}, PREFIX_OPCODE
},
2764 { "unpckhpX", { XM
, EXx
}, PREFIX_OPCODE
},
2765 { PREFIX_TABLE (PREFIX_0F16
) },
2766 { MOD_TABLE (MOD_0F17
) },
2768 { REG_TABLE (REG_0F18
) },
2769 { "nopQ", { Ev
}, 0 },
2770 { PREFIX_TABLE (PREFIX_0F1A
) },
2771 { PREFIX_TABLE (PREFIX_0F1B
) },
2772 { "nopQ", { Ev
}, 0 },
2773 { "nopQ", { Ev
}, 0 },
2774 { "nopQ", { Ev
}, 0 },
2775 { "nopQ", { Ev
}, 0 },
2777 { "movZ", { Rm
, Cm
}, 0 },
2778 { "movZ", { Rm
, Dm
}, 0 },
2779 { "movZ", { Cm
, Rm
}, 0 },
2780 { "movZ", { Dm
, Rm
}, 0 },
2781 { MOD_TABLE (MOD_0F24
) },
2783 { MOD_TABLE (MOD_0F26
) },
2786 { "movapX", { XM
, EXx
}, PREFIX_OPCODE
},
2787 { "movapX", { EXxS
, XM
}, PREFIX_OPCODE
},
2788 { PREFIX_TABLE (PREFIX_0F2A
) },
2789 { PREFIX_TABLE (PREFIX_0F2B
) },
2790 { PREFIX_TABLE (PREFIX_0F2C
) },
2791 { PREFIX_TABLE (PREFIX_0F2D
) },
2792 { PREFIX_TABLE (PREFIX_0F2E
) },
2793 { PREFIX_TABLE (PREFIX_0F2F
) },
2795 { "wrmsr", { XX
}, 0 },
2796 { "rdtsc", { XX
}, 0 },
2797 { "rdmsr", { XX
}, 0 },
2798 { "rdpmc", { XX
}, 0 },
2799 { "sysenter", { XX
}, 0 },
2800 { "sysexit", { XX
}, 0 },
2802 { "getsec", { XX
}, 0 },
2804 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38
, PREFIX_OPCODE
) },
2806 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A
, PREFIX_OPCODE
) },
2813 { "cmovoS", { Gv
, Ev
}, 0 },
2814 { "cmovnoS", { Gv
, Ev
}, 0 },
2815 { "cmovbS", { Gv
, Ev
}, 0 },
2816 { "cmovaeS", { Gv
, Ev
}, 0 },
2817 { "cmoveS", { Gv
, Ev
}, 0 },
2818 { "cmovneS", { Gv
, Ev
}, 0 },
2819 { "cmovbeS", { Gv
, Ev
}, 0 },
2820 { "cmovaS", { Gv
, Ev
}, 0 },
2822 { "cmovsS", { Gv
, Ev
}, 0 },
2823 { "cmovnsS", { Gv
, Ev
}, 0 },
2824 { "cmovpS", { Gv
, Ev
}, 0 },
2825 { "cmovnpS", { Gv
, Ev
}, 0 },
2826 { "cmovlS", { Gv
, Ev
}, 0 },
2827 { "cmovgeS", { Gv
, Ev
}, 0 },
2828 { "cmovleS", { Gv
, Ev
}, 0 },
2829 { "cmovgS", { Gv
, Ev
}, 0 },
2831 { MOD_TABLE (MOD_0F51
) },
2832 { PREFIX_TABLE (PREFIX_0F51
) },
2833 { PREFIX_TABLE (PREFIX_0F52
) },
2834 { PREFIX_TABLE (PREFIX_0F53
) },
2835 { "andpX", { XM
, EXx
}, PREFIX_OPCODE
},
2836 { "andnpX", { XM
, EXx
}, PREFIX_OPCODE
},
2837 { "orpX", { XM
, EXx
}, PREFIX_OPCODE
},
2838 { "xorpX", { XM
, EXx
}, PREFIX_OPCODE
},
2840 { PREFIX_TABLE (PREFIX_0F58
) },
2841 { PREFIX_TABLE (PREFIX_0F59
) },
2842 { PREFIX_TABLE (PREFIX_0F5A
) },
2843 { PREFIX_TABLE (PREFIX_0F5B
) },
2844 { PREFIX_TABLE (PREFIX_0F5C
) },
2845 { PREFIX_TABLE (PREFIX_0F5D
) },
2846 { PREFIX_TABLE (PREFIX_0F5E
) },
2847 { PREFIX_TABLE (PREFIX_0F5F
) },
2849 { PREFIX_TABLE (PREFIX_0F60
) },
2850 { PREFIX_TABLE (PREFIX_0F61
) },
2851 { PREFIX_TABLE (PREFIX_0F62
) },
2852 { "packsswb", { MX
, EM
}, PREFIX_OPCODE
},
2853 { "pcmpgtb", { MX
, EM
}, PREFIX_OPCODE
},
2854 { "pcmpgtw", { MX
, EM
}, PREFIX_OPCODE
},
2855 { "pcmpgtd", { MX
, EM
}, PREFIX_OPCODE
},
2856 { "packuswb", { MX
, EM
}, PREFIX_OPCODE
},
2858 { "punpckhbw", { MX
, EM
}, PREFIX_OPCODE
},
2859 { "punpckhwd", { MX
, EM
}, PREFIX_OPCODE
},
2860 { "punpckhdq", { MX
, EM
}, PREFIX_OPCODE
},
2861 { "packssdw", { MX
, EM
}, PREFIX_OPCODE
},
2862 { PREFIX_TABLE (PREFIX_0F6C
) },
2863 { PREFIX_TABLE (PREFIX_0F6D
) },
2864 { "movK", { MX
, Edq
}, PREFIX_OPCODE
},
2865 { PREFIX_TABLE (PREFIX_0F6F
) },
2867 { PREFIX_TABLE (PREFIX_0F70
) },
2868 { REG_TABLE (REG_0F71
) },
2869 { REG_TABLE (REG_0F72
) },
2870 { REG_TABLE (REG_0F73
) },
2871 { "pcmpeqb", { MX
, EM
}, PREFIX_OPCODE
},
2872 { "pcmpeqw", { MX
, EM
}, PREFIX_OPCODE
},
2873 { "pcmpeqd", { MX
, EM
}, PREFIX_OPCODE
},
2874 { "emms", { XX
}, PREFIX_OPCODE
},
2876 { PREFIX_TABLE (PREFIX_0F78
) },
2877 { PREFIX_TABLE (PREFIX_0F79
) },
2878 { THREE_BYTE_TABLE (THREE_BYTE_0F7A
) },
2880 { PREFIX_TABLE (PREFIX_0F7C
) },
2881 { PREFIX_TABLE (PREFIX_0F7D
) },
2882 { PREFIX_TABLE (PREFIX_0F7E
) },
2883 { PREFIX_TABLE (PREFIX_0F7F
) },
2885 { "joH", { Jv
, BND
, cond_jump_flag
}, 0 },
2886 { "jnoH", { Jv
, BND
, cond_jump_flag
}, 0 },
2887 { "jbH", { Jv
, BND
, cond_jump_flag
}, 0 },
2888 { "jaeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2889 { "jeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2890 { "jneH", { Jv
, BND
, cond_jump_flag
}, 0 },
2891 { "jbeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2892 { "jaH", { Jv
, BND
, cond_jump_flag
}, 0 },
2894 { "jsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2895 { "jnsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2896 { "jpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2897 { "jnpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2898 { "jlH", { Jv
, BND
, cond_jump_flag
}, 0 },
2899 { "jgeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2900 { "jleH", { Jv
, BND
, cond_jump_flag
}, 0 },
2901 { "jgH", { Jv
, BND
, cond_jump_flag
}, 0 },
2903 { "seto", { Eb
}, 0 },
2904 { "setno", { Eb
}, 0 },
2905 { "setb", { Eb
}, 0 },
2906 { "setae", { Eb
}, 0 },
2907 { "sete", { Eb
}, 0 },
2908 { "setne", { Eb
}, 0 },
2909 { "setbe", { Eb
}, 0 },
2910 { "seta", { Eb
}, 0 },
2912 { "sets", { Eb
}, 0 },
2913 { "setns", { Eb
}, 0 },
2914 { "setp", { Eb
}, 0 },
2915 { "setnp", { Eb
}, 0 },
2916 { "setl", { Eb
}, 0 },
2917 { "setge", { Eb
}, 0 },
2918 { "setle", { Eb
}, 0 },
2919 { "setg", { Eb
}, 0 },
2921 { "pushT", { fs
}, 0 },
2922 { "popT", { fs
}, 0 },
2923 { "cpuid", { XX
}, 0 },
2924 { "btS", { Ev
, Gv
}, 0 },
2925 { "shldS", { Ev
, Gv
, Ib
}, 0 },
2926 { "shldS", { Ev
, Gv
, CL
}, 0 },
2927 { REG_TABLE (REG_0FA6
) },
2928 { REG_TABLE (REG_0FA7
) },
2930 { "pushT", { gs
}, 0 },
2931 { "popT", { gs
}, 0 },
2932 { "rsm", { XX
}, 0 },
2933 { "btsS", { Evh1
, Gv
}, 0 },
2934 { "shrdS", { Ev
, Gv
, Ib
}, 0 },
2935 { "shrdS", { Ev
, Gv
, CL
}, 0 },
2936 { REG_TABLE (REG_0FAE
) },
2937 { "imulS", { Gv
, Ev
}, 0 },
2939 { "cmpxchgB", { Ebh1
, Gb
}, 0 },
2940 { "cmpxchgS", { Evh1
, Gv
}, 0 },
2941 { MOD_TABLE (MOD_0FB2
) },
2942 { "btrS", { Evh1
, Gv
}, 0 },
2943 { MOD_TABLE (MOD_0FB4
) },
2944 { MOD_TABLE (MOD_0FB5
) },
2945 { "movz{bR|x}", { Gv
, Eb
}, 0 },
2946 { "movz{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movzww ! */
2948 { PREFIX_TABLE (PREFIX_0FB8
) },
2949 { "ud1", { XX
}, 0 },
2950 { REG_TABLE (REG_0FBA
) },
2951 { "btcS", { Evh1
, Gv
}, 0 },
2952 { PREFIX_TABLE (PREFIX_0FBC
) },
2953 { PREFIX_TABLE (PREFIX_0FBD
) },
2954 { "movs{bR|x}", { Gv
, Eb
}, 0 },
2955 { "movs{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movsww ! */
2957 { "xaddB", { Ebh1
, Gb
}, 0 },
2958 { "xaddS", { Evh1
, Gv
}, 0 },
2959 { PREFIX_TABLE (PREFIX_0FC2
) },
2960 { MOD_TABLE (MOD_0FC3
) },
2961 { "pinsrw", { MX
, Edqw
, Ib
}, PREFIX_OPCODE
},
2962 { "pextrw", { Gdq
, MS
, Ib
}, PREFIX_OPCODE
},
2963 { "shufpX", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
2964 { REG_TABLE (REG_0FC7
) },
2966 { "bswap", { RMeAX
}, 0 },
2967 { "bswap", { RMeCX
}, 0 },
2968 { "bswap", { RMeDX
}, 0 },
2969 { "bswap", { RMeBX
}, 0 },
2970 { "bswap", { RMeSP
}, 0 },
2971 { "bswap", { RMeBP
}, 0 },
2972 { "bswap", { RMeSI
}, 0 },
2973 { "bswap", { RMeDI
}, 0 },
2975 { PREFIX_TABLE (PREFIX_0FD0
) },
2976 { "psrlw", { MX
, EM
}, PREFIX_OPCODE
},
2977 { "psrld", { MX
, EM
}, PREFIX_OPCODE
},
2978 { "psrlq", { MX
, EM
}, PREFIX_OPCODE
},
2979 { "paddq", { MX
, EM
}, PREFIX_OPCODE
},
2980 { "pmullw", { MX
, EM
}, PREFIX_OPCODE
},
2981 { PREFIX_TABLE (PREFIX_0FD6
) },
2982 { MOD_TABLE (MOD_0FD7
) },
2984 { "psubusb", { MX
, EM
}, PREFIX_OPCODE
},
2985 { "psubusw", { MX
, EM
}, PREFIX_OPCODE
},
2986 { "pminub", { MX
, EM
}, PREFIX_OPCODE
},
2987 { "pand", { MX
, EM
}, PREFIX_OPCODE
},
2988 { "paddusb", { MX
, EM
}, PREFIX_OPCODE
},
2989 { "paddusw", { MX
, EM
}, PREFIX_OPCODE
},
2990 { "pmaxub", { MX
, EM
}, PREFIX_OPCODE
},
2991 { "pandn", { MX
, EM
}, PREFIX_OPCODE
},
2993 { "pavgb", { MX
, EM
}, PREFIX_OPCODE
},
2994 { "psraw", { MX
, EM
}, PREFIX_OPCODE
},
2995 { "psrad", { MX
, EM
}, PREFIX_OPCODE
},
2996 { "pavgw", { MX
, EM
}, PREFIX_OPCODE
},
2997 { "pmulhuw", { MX
, EM
}, PREFIX_OPCODE
},
2998 { "pmulhw", { MX
, EM
}, PREFIX_OPCODE
},
2999 { PREFIX_TABLE (PREFIX_0FE6
) },
3000 { PREFIX_TABLE (PREFIX_0FE7
) },
3002 { "psubsb", { MX
, EM
}, PREFIX_OPCODE
},
3003 { "psubsw", { MX
, EM
}, PREFIX_OPCODE
},
3004 { "pminsw", { MX
, EM
}, PREFIX_OPCODE
},
3005 { "por", { MX
, EM
}, PREFIX_OPCODE
},
3006 { "paddsb", { MX
, EM
}, PREFIX_OPCODE
},
3007 { "paddsw", { MX
, EM
}, PREFIX_OPCODE
},
3008 { "pmaxsw", { MX
, EM
}, PREFIX_OPCODE
},
3009 { "pxor", { MX
, EM
}, PREFIX_OPCODE
},
3011 { PREFIX_TABLE (PREFIX_0FF0
) },
3012 { "psllw", { MX
, EM
}, PREFIX_OPCODE
},
3013 { "pslld", { MX
, EM
}, PREFIX_OPCODE
},
3014 { "psllq", { MX
, EM
}, PREFIX_OPCODE
},
3015 { "pmuludq", { MX
, EM
}, PREFIX_OPCODE
},
3016 { "pmaddwd", { MX
, EM
}, PREFIX_OPCODE
},
3017 { "psadbw", { MX
, EM
}, PREFIX_OPCODE
},
3018 { PREFIX_TABLE (PREFIX_0FF7
) },
3020 { "psubb", { MX
, EM
}, PREFIX_OPCODE
},
3021 { "psubw", { MX
, EM
}, PREFIX_OPCODE
},
3022 { "psubd", { MX
, EM
}, PREFIX_OPCODE
},
3023 { "psubq", { MX
, EM
}, PREFIX_OPCODE
},
3024 { "paddb", { MX
, EM
}, PREFIX_OPCODE
},
3025 { "paddw", { MX
, EM
}, PREFIX_OPCODE
},
3026 { "paddd", { MX
, EM
}, PREFIX_OPCODE
},
3030 static const unsigned char onebyte_has_modrm
[256] = {
3031 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3032 /* ------------------------------- */
3033 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
3034 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
3035 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
3036 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
3037 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
3038 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
3039 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
3040 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
3041 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
3042 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
3043 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
3044 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
3045 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
3046 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
3047 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
3048 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
3049 /* ------------------------------- */
3050 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3053 static const unsigned char twobyte_has_modrm
[256] = {
3054 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3055 /* ------------------------------- */
3056 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
3057 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
3058 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
3059 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3060 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
3061 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3062 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3063 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
3064 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3065 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
3066 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
3067 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
3068 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
3069 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3070 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3071 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
3072 /* ------------------------------- */
3073 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3076 static char obuf
[100];
3078 static char *mnemonicendp
;
3079 static char scratchbuf
[100];
3080 static unsigned char *start_codep
;
3081 static unsigned char *insn_codep
;
3082 static unsigned char *codep
;
3083 static unsigned char *end_codep
;
3084 static int last_lock_prefix
;
3085 static int last_repz_prefix
;
3086 static int last_repnz_prefix
;
3087 static int last_data_prefix
;
3088 static int last_addr_prefix
;
3089 static int last_rex_prefix
;
3090 static int last_seg_prefix
;
3091 static int fwait_prefix
;
3092 /* The active segment register prefix. */
3093 static int active_seg_prefix
;
3094 #define MAX_CODE_LENGTH 15
3095 /* We can up to 14 prefixes since the maximum instruction length is
3097 static int all_prefixes
[MAX_CODE_LENGTH
- 1];
3098 static disassemble_info
*the_info
;
3106 static unsigned char need_modrm
;
3116 int register_specifier
;
3123 int mask_register_specifier
;
3129 static unsigned char need_vex
;
3130 static unsigned char need_vex_reg
;
3131 static unsigned char vex_w_done
;
3139 /* If we are accessing mod/rm/reg without need_modrm set, then the
3140 values are stale. Hitting this abort likely indicates that you
3141 need to update onebyte_has_modrm or twobyte_has_modrm. */
3142 #define MODRM_CHECK if (!need_modrm) abort ()
3144 static const char **names64
;
3145 static const char **names32
;
3146 static const char **names16
;
3147 static const char **names8
;
3148 static const char **names8rex
;
3149 static const char **names_seg
;
3150 static const char *index64
;
3151 static const char *index32
;
3152 static const char **index16
;
3153 static const char **names_bnd
;
3155 static const char *intel_names64
[] = {
3156 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3157 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3159 static const char *intel_names32
[] = {
3160 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3161 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3163 static const char *intel_names16
[] = {
3164 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3165 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3167 static const char *intel_names8
[] = {
3168 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3170 static const char *intel_names8rex
[] = {
3171 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3172 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3174 static const char *intel_names_seg
[] = {
3175 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3177 static const char *intel_index64
= "riz";
3178 static const char *intel_index32
= "eiz";
3179 static const char *intel_index16
[] = {
3180 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3183 static const char *att_names64
[] = {
3184 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3185 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3187 static const char *att_names32
[] = {
3188 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3189 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3191 static const char *att_names16
[] = {
3192 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3193 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3195 static const char *att_names8
[] = {
3196 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3198 static const char *att_names8rex
[] = {
3199 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3200 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3202 static const char *att_names_seg
[] = {
3203 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3205 static const char *att_index64
= "%riz";
3206 static const char *att_index32
= "%eiz";
3207 static const char *att_index16
[] = {
3208 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3211 static const char **names_mm
;
3212 static const char *intel_names_mm
[] = {
3213 "mm0", "mm1", "mm2", "mm3",
3214 "mm4", "mm5", "mm6", "mm7"
3216 static const char *att_names_mm
[] = {
3217 "%mm0", "%mm1", "%mm2", "%mm3",
3218 "%mm4", "%mm5", "%mm6", "%mm7"
3221 static const char *intel_names_bnd
[] = {
3222 "bnd0", "bnd1", "bnd2", "bnd3"
3225 static const char *att_names_bnd
[] = {
3226 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3229 static const char **names_xmm
;
3230 static const char *intel_names_xmm
[] = {
3231 "xmm0", "xmm1", "xmm2", "xmm3",
3232 "xmm4", "xmm5", "xmm6", "xmm7",
3233 "xmm8", "xmm9", "xmm10", "xmm11",
3234 "xmm12", "xmm13", "xmm14", "xmm15",
3235 "xmm16", "xmm17", "xmm18", "xmm19",
3236 "xmm20", "xmm21", "xmm22", "xmm23",
3237 "xmm24", "xmm25", "xmm26", "xmm27",
3238 "xmm28", "xmm29", "xmm30", "xmm31"
3240 static const char *att_names_xmm
[] = {
3241 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3242 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3243 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3244 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3245 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3246 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3247 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3248 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3251 static const char **names_ymm
;
3252 static const char *intel_names_ymm
[] = {
3253 "ymm0", "ymm1", "ymm2", "ymm3",
3254 "ymm4", "ymm5", "ymm6", "ymm7",
3255 "ymm8", "ymm9", "ymm10", "ymm11",
3256 "ymm12", "ymm13", "ymm14", "ymm15",
3257 "ymm16", "ymm17", "ymm18", "ymm19",
3258 "ymm20", "ymm21", "ymm22", "ymm23",
3259 "ymm24", "ymm25", "ymm26", "ymm27",
3260 "ymm28", "ymm29", "ymm30", "ymm31"
3262 static const char *att_names_ymm
[] = {
3263 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3264 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3265 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3266 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3267 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3268 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3269 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3270 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3273 static const char **names_zmm
;
3274 static const char *intel_names_zmm
[] = {
3275 "zmm0", "zmm1", "zmm2", "zmm3",
3276 "zmm4", "zmm5", "zmm6", "zmm7",
3277 "zmm8", "zmm9", "zmm10", "zmm11",
3278 "zmm12", "zmm13", "zmm14", "zmm15",
3279 "zmm16", "zmm17", "zmm18", "zmm19",
3280 "zmm20", "zmm21", "zmm22", "zmm23",
3281 "zmm24", "zmm25", "zmm26", "zmm27",
3282 "zmm28", "zmm29", "zmm30", "zmm31"
3284 static const char *att_names_zmm
[] = {
3285 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3286 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3287 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3288 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3289 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3290 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3291 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3292 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3295 static const char **names_mask
;
3296 static const char *intel_names_mask
[] = {
3297 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3299 static const char *att_names_mask
[] = {
3300 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3303 static const char *names_rounding
[] =
3311 static const struct dis386 reg_table
[][8] = {
3314 { "addA", { Ebh1
, Ib
}, 0 },
3315 { "orA", { Ebh1
, Ib
}, 0 },
3316 { "adcA", { Ebh1
, Ib
}, 0 },
3317 { "sbbA", { Ebh1
, Ib
}, 0 },
3318 { "andA", { Ebh1
, Ib
}, 0 },
3319 { "subA", { Ebh1
, Ib
}, 0 },
3320 { "xorA", { Ebh1
, Ib
}, 0 },
3321 { "cmpA", { Eb
, Ib
}, 0 },
3325 { "addQ", { Evh1
, Iv
}, 0 },
3326 { "orQ", { Evh1
, Iv
}, 0 },
3327 { "adcQ", { Evh1
, Iv
}, 0 },
3328 { "sbbQ", { Evh1
, Iv
}, 0 },
3329 { "andQ", { Evh1
, Iv
}, 0 },
3330 { "subQ", { Evh1
, Iv
}, 0 },
3331 { "xorQ", { Evh1
, Iv
}, 0 },
3332 { "cmpQ", { Ev
, Iv
}, 0 },
3336 { "addQ", { Evh1
, sIb
}, 0 },
3337 { "orQ", { Evh1
, sIb
}, 0 },
3338 { "adcQ", { Evh1
, sIb
}, 0 },
3339 { "sbbQ", { Evh1
, sIb
}, 0 },
3340 { "andQ", { Evh1
, sIb
}, 0 },
3341 { "subQ", { Evh1
, sIb
}, 0 },
3342 { "xorQ", { Evh1
, sIb
}, 0 },
3343 { "cmpQ", { Ev
, sIb
}, 0 },
3347 { "popU", { stackEv
}, 0 },
3348 { XOP_8F_TABLE (XOP_09
) },
3352 { XOP_8F_TABLE (XOP_09
) },
3356 { "rolA", { Eb
, Ib
}, 0 },
3357 { "rorA", { Eb
, Ib
}, 0 },
3358 { "rclA", { Eb
, Ib
}, 0 },
3359 { "rcrA", { Eb
, Ib
}, 0 },
3360 { "shlA", { Eb
, Ib
}, 0 },
3361 { "shrA", { Eb
, Ib
}, 0 },
3363 { "sarA", { Eb
, Ib
}, 0 },
3367 { "rolQ", { Ev
, Ib
}, 0 },
3368 { "rorQ", { Ev
, Ib
}, 0 },
3369 { "rclQ", { Ev
, Ib
}, 0 },
3370 { "rcrQ", { Ev
, Ib
}, 0 },
3371 { "shlQ", { Ev
, Ib
}, 0 },
3372 { "shrQ", { Ev
, Ib
}, 0 },
3374 { "sarQ", { Ev
, Ib
}, 0 },
3378 { "movA", { Ebh3
, Ib
}, 0 },
3385 { MOD_TABLE (MOD_C6_REG_7
) },
3389 { "movQ", { Evh3
, Iv
}, 0 },
3396 { MOD_TABLE (MOD_C7_REG_7
) },
3400 { "rolA", { Eb
, I1
}, 0 },
3401 { "rorA", { Eb
, I1
}, 0 },
3402 { "rclA", { Eb
, I1
}, 0 },
3403 { "rcrA", { Eb
, I1
}, 0 },
3404 { "shlA", { Eb
, I1
}, 0 },
3405 { "shrA", { Eb
, I1
}, 0 },
3407 { "sarA", { Eb
, I1
}, 0 },
3411 { "rolQ", { Ev
, I1
}, 0 },
3412 { "rorQ", { Ev
, I1
}, 0 },
3413 { "rclQ", { Ev
, I1
}, 0 },
3414 { "rcrQ", { Ev
, I1
}, 0 },
3415 { "shlQ", { Ev
, I1
}, 0 },
3416 { "shrQ", { Ev
, I1
}, 0 },
3418 { "sarQ", { Ev
, I1
}, 0 },
3422 { "rolA", { Eb
, CL
}, 0 },
3423 { "rorA", { Eb
, CL
}, 0 },
3424 { "rclA", { Eb
, CL
}, 0 },
3425 { "rcrA", { Eb
, CL
}, 0 },
3426 { "shlA", { Eb
, CL
}, 0 },
3427 { "shrA", { Eb
, CL
}, 0 },
3429 { "sarA", { Eb
, CL
}, 0 },
3433 { "rolQ", { Ev
, CL
}, 0 },
3434 { "rorQ", { Ev
, CL
}, 0 },
3435 { "rclQ", { Ev
, CL
}, 0 },
3436 { "rcrQ", { Ev
, CL
}, 0 },
3437 { "shlQ", { Ev
, CL
}, 0 },
3438 { "shrQ", { Ev
, CL
}, 0 },
3440 { "sarQ", { Ev
, CL
}, 0 },
3444 { "testA", { Eb
, Ib
}, 0 },
3446 { "notA", { Ebh1
}, 0 },
3447 { "negA", { Ebh1
}, 0 },
3448 { "mulA", { Eb
}, 0 }, /* Don't print the implicit %al register, */
3449 { "imulA", { Eb
}, 0 }, /* to distinguish these opcodes from other */
3450 { "divA", { Eb
}, 0 }, /* mul/imul opcodes. Do the same for div */
3451 { "idivA", { Eb
}, 0 }, /* and idiv for consistency. */
3455 { "testQ", { Ev
, Iv
}, 0 },
3457 { "notQ", { Evh1
}, 0 },
3458 { "negQ", { Evh1
}, 0 },
3459 { "mulQ", { Ev
}, 0 }, /* Don't print the implicit register. */
3460 { "imulQ", { Ev
}, 0 },
3461 { "divQ", { Ev
}, 0 },
3462 { "idivQ", { Ev
}, 0 },
3466 { "incA", { Ebh1
}, 0 },
3467 { "decA", { Ebh1
}, 0 },
3471 { "incQ", { Evh1
}, 0 },
3472 { "decQ", { Evh1
}, 0 },
3473 { "call{T|}", { indirEv
, BND
}, 0 },
3474 { MOD_TABLE (MOD_FF_REG_3
) },
3475 { "jmp{T|}", { indirEv
, BND
}, 0 },
3476 { MOD_TABLE (MOD_FF_REG_5
) },
3477 { "pushU", { stackEv
}, 0 },
3482 { "sldtD", { Sv
}, 0 },
3483 { "strD", { Sv
}, 0 },
3484 { "lldt", { Ew
}, 0 },
3485 { "ltr", { Ew
}, 0 },
3486 { "verr", { Ew
}, 0 },
3487 { "verw", { Ew
}, 0 },
3493 { MOD_TABLE (MOD_0F01_REG_0
) },
3494 { MOD_TABLE (MOD_0F01_REG_1
) },
3495 { MOD_TABLE (MOD_0F01_REG_2
) },
3496 { MOD_TABLE (MOD_0F01_REG_3
) },
3497 { "smswD", { Sv
}, 0 },
3499 { "lmsw", { Ew
}, 0 },
3500 { MOD_TABLE (MOD_0F01_REG_7
) },
3504 { "prefetch", { Mb
}, 0 },
3505 { "prefetchw", { Mb
}, 0 },
3506 { "prefetchwt1", { Mb
}, 0 },
3507 { "prefetch", { Mb
}, 0 },
3508 { "prefetch", { Mb
}, 0 },
3509 { "prefetch", { Mb
}, 0 },
3510 { "prefetch", { Mb
}, 0 },
3511 { "prefetch", { Mb
}, 0 },
3515 { MOD_TABLE (MOD_0F18_REG_0
) },
3516 { MOD_TABLE (MOD_0F18_REG_1
) },
3517 { MOD_TABLE (MOD_0F18_REG_2
) },
3518 { MOD_TABLE (MOD_0F18_REG_3
) },
3519 { MOD_TABLE (MOD_0F18_REG_4
) },
3520 { MOD_TABLE (MOD_0F18_REG_5
) },
3521 { MOD_TABLE (MOD_0F18_REG_6
) },
3522 { MOD_TABLE (MOD_0F18_REG_7
) },
3528 { MOD_TABLE (MOD_0F71_REG_2
) },
3530 { MOD_TABLE (MOD_0F71_REG_4
) },
3532 { MOD_TABLE (MOD_0F71_REG_6
) },
3538 { MOD_TABLE (MOD_0F72_REG_2
) },
3540 { MOD_TABLE (MOD_0F72_REG_4
) },
3542 { MOD_TABLE (MOD_0F72_REG_6
) },
3548 { MOD_TABLE (MOD_0F73_REG_2
) },
3549 { MOD_TABLE (MOD_0F73_REG_3
) },
3552 { MOD_TABLE (MOD_0F73_REG_6
) },
3553 { MOD_TABLE (MOD_0F73_REG_7
) },
3557 { "montmul", { { OP_0f07
, 0 } }, 0 },
3558 { "xsha1", { { OP_0f07
, 0 } }, 0 },
3559 { "xsha256", { { OP_0f07
, 0 } }, 0 },
3563 { "xstore-rng", { { OP_0f07
, 0 } }, 0 },
3564 { "xcrypt-ecb", { { OP_0f07
, 0 } }, 0 },
3565 { "xcrypt-cbc", { { OP_0f07
, 0 } }, 0 },
3566 { "xcrypt-ctr", { { OP_0f07
, 0 } }, 0 },
3567 { "xcrypt-cfb", { { OP_0f07
, 0 } }, 0 },
3568 { "xcrypt-ofb", { { OP_0f07
, 0 } }, 0 },
3572 { MOD_TABLE (MOD_0FAE_REG_0
) },
3573 { MOD_TABLE (MOD_0FAE_REG_1
) },
3574 { MOD_TABLE (MOD_0FAE_REG_2
) },
3575 { MOD_TABLE (MOD_0FAE_REG_3
) },
3576 { MOD_TABLE (MOD_0FAE_REG_4
) },
3577 { MOD_TABLE (MOD_0FAE_REG_5
) },
3578 { MOD_TABLE (MOD_0FAE_REG_6
) },
3579 { MOD_TABLE (MOD_0FAE_REG_7
) },
3587 { "btQ", { Ev
, Ib
}, 0 },
3588 { "btsQ", { Evh1
, Ib
}, 0 },
3589 { "btrQ", { Evh1
, Ib
}, 0 },
3590 { "btcQ", { Evh1
, Ib
}, 0 },
3595 { "cmpxchg8b", { { CMPXCHG8B_Fixup
, q_mode
} }, 0 },
3597 { MOD_TABLE (MOD_0FC7_REG_3
) },
3598 { MOD_TABLE (MOD_0FC7_REG_4
) },
3599 { MOD_TABLE (MOD_0FC7_REG_5
) },
3600 { MOD_TABLE (MOD_0FC7_REG_6
) },
3601 { MOD_TABLE (MOD_0FC7_REG_7
) },
3607 { MOD_TABLE (MOD_VEX_0F71_REG_2
) },
3609 { MOD_TABLE (MOD_VEX_0F71_REG_4
) },
3611 { MOD_TABLE (MOD_VEX_0F71_REG_6
) },
3617 { MOD_TABLE (MOD_VEX_0F72_REG_2
) },
3619 { MOD_TABLE (MOD_VEX_0F72_REG_4
) },
3621 { MOD_TABLE (MOD_VEX_0F72_REG_6
) },
3627 { MOD_TABLE (MOD_VEX_0F73_REG_2
) },
3628 { MOD_TABLE (MOD_VEX_0F73_REG_3
) },
3631 { MOD_TABLE (MOD_VEX_0F73_REG_6
) },
3632 { MOD_TABLE (MOD_VEX_0F73_REG_7
) },
3638 { MOD_TABLE (MOD_VEX_0FAE_REG_2
) },
3639 { MOD_TABLE (MOD_VEX_0FAE_REG_3
) },
3641 /* REG_VEX_0F38F3 */
3644 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1
) },
3645 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2
) },
3646 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3
) },
3650 { "llwpcb", { { OP_LWPCB_E
, 0 } }, 0 },
3651 { "slwpcb", { { OP_LWPCB_E
, 0 } }, 0 },
3655 { "lwpins", { { OP_LWP_E
, 0 }, Ed
, Iq
}, 0 },
3656 { "lwpval", { { OP_LWP_E
, 0 }, Ed
, Iq
}, 0 },
3658 /* REG_XOP_TBM_01 */
3661 { "blcfill", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3662 { "blsfill", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3663 { "blcs", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3664 { "tzmsk", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3665 { "blcic", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3666 { "blsic", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3667 { "t1mskc", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3669 /* REG_XOP_TBM_02 */
3672 { "blcmsk", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3677 { "blci", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3679 #define NEED_REG_TABLE
3680 #include "i386-dis-evex.h"
3681 #undef NEED_REG_TABLE
3684 static const struct dis386 prefix_table
[][4] = {
3687 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3688 { "pause", { XX
}, 0 },
3689 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3690 { NULL
, { { NULL
, 0 } }, PREFIX_IGNORED
}
3695 { "movups", { XM
, EXx
}, PREFIX_OPCODE
},
3696 { "movss", { XM
, EXd
}, PREFIX_OPCODE
},
3697 { "movupd", { XM
, EXx
}, PREFIX_OPCODE
},
3698 { "movsd", { XM
, EXq
}, PREFIX_OPCODE
},
3703 { "movups", { EXxS
, XM
}, PREFIX_OPCODE
},
3704 { "movss", { EXdS
, XM
}, PREFIX_OPCODE
},
3705 { "movupd", { EXxS
, XM
}, PREFIX_OPCODE
},
3706 { "movsd", { EXqS
, XM
}, PREFIX_OPCODE
},
3711 { MOD_TABLE (MOD_0F12_PREFIX_0
) },
3712 { "movsldup", { XM
, EXx
}, PREFIX_OPCODE
},
3713 { "movlpd", { XM
, EXq
}, PREFIX_OPCODE
},
3714 { "movddup", { XM
, EXq
}, PREFIX_OPCODE
},
3719 { MOD_TABLE (MOD_0F16_PREFIX_0
) },
3720 { "movshdup", { XM
, EXx
}, PREFIX_OPCODE
},
3721 { "movhpd", { XM
, EXq
}, PREFIX_OPCODE
},
3726 { MOD_TABLE (MOD_0F1A_PREFIX_0
) },
3727 { "bndcl", { Gbnd
, Ev_bnd
}, 0 },
3728 { "bndmov", { Gbnd
, Ebnd
}, 0 },
3729 { "bndcu", { Gbnd
, Ev_bnd
}, 0 },
3734 { MOD_TABLE (MOD_0F1B_PREFIX_0
) },
3735 { MOD_TABLE (MOD_0F1B_PREFIX_1
) },
3736 { "bndmov", { Ebnd
, Gbnd
}, 0 },
3737 { "bndcn", { Gbnd
, Ev_bnd
}, 0 },
3742 { "cvtpi2ps", { XM
, EMCq
}, PREFIX_OPCODE
},
3743 { "cvtsi2ss%LQ", { XM
, Ev
}, PREFIX_OPCODE
},
3744 { "cvtpi2pd", { XM
, EMCq
}, PREFIX_OPCODE
},
3745 { "cvtsi2sd%LQ", { XM
, Ev
}, 0 },
3750 { MOD_TABLE (MOD_0F2B_PREFIX_0
) },
3751 { MOD_TABLE (MOD_0F2B_PREFIX_1
) },
3752 { MOD_TABLE (MOD_0F2B_PREFIX_2
) },
3753 { MOD_TABLE (MOD_0F2B_PREFIX_3
) },
3758 { "cvttps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3759 { "cvttss2siY", { Gv
, EXd
}, PREFIX_OPCODE
},
3760 { "cvttpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3761 { "cvttsd2siY", { Gv
, EXq
}, PREFIX_OPCODE
},
3766 { "cvtps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3767 { "cvtss2siY", { Gv
, EXd
}, PREFIX_OPCODE
},
3768 { "cvtpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3769 { "cvtsd2siY", { Gv
, EXq
}, PREFIX_OPCODE
},
3774 { "ucomiss",{ XM
, EXd
}, 0 },
3776 { "ucomisd",{ XM
, EXq
}, 0 },
3781 { "comiss", { XM
, EXd
}, 0 },
3783 { "comisd", { XM
, EXq
}, 0 },
3788 { "sqrtps", { XM
, EXx
}, PREFIX_OPCODE
},
3789 { "sqrtss", { XM
, EXd
}, PREFIX_OPCODE
},
3790 { "sqrtpd", { XM
, EXx
}, PREFIX_OPCODE
},
3791 { "sqrtsd", { XM
, EXq
}, PREFIX_OPCODE
},
3796 { "rsqrtps",{ XM
, EXx
}, PREFIX_OPCODE
},
3797 { "rsqrtss",{ XM
, EXd
}, PREFIX_OPCODE
},
3802 { "rcpps", { XM
, EXx
}, PREFIX_OPCODE
},
3803 { "rcpss", { XM
, EXd
}, PREFIX_OPCODE
},
3808 { "addps", { XM
, EXx
}, PREFIX_OPCODE
},
3809 { "addss", { XM
, EXd
}, PREFIX_OPCODE
},
3810 { "addpd", { XM
, EXx
}, PREFIX_OPCODE
},
3811 { "addsd", { XM
, EXq
}, PREFIX_OPCODE
},
3816 { "mulps", { XM
, EXx
}, PREFIX_OPCODE
},
3817 { "mulss", { XM
, EXd
}, PREFIX_OPCODE
},
3818 { "mulpd", { XM
, EXx
}, PREFIX_OPCODE
},
3819 { "mulsd", { XM
, EXq
}, PREFIX_OPCODE
},
3824 { "cvtps2pd", { XM
, EXq
}, PREFIX_OPCODE
},
3825 { "cvtss2sd", { XM
, EXd
}, PREFIX_OPCODE
},
3826 { "cvtpd2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3827 { "cvtsd2ss", { XM
, EXq
}, PREFIX_OPCODE
},
3832 { "cvtdq2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3833 { "cvttps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3834 { "cvtps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3839 { "subps", { XM
, EXx
}, PREFIX_OPCODE
},
3840 { "subss", { XM
, EXd
}, PREFIX_OPCODE
},
3841 { "subpd", { XM
, EXx
}, PREFIX_OPCODE
},
3842 { "subsd", { XM
, EXq
}, PREFIX_OPCODE
},
3847 { "minps", { XM
, EXx
}, PREFIX_OPCODE
},
3848 { "minss", { XM
, EXd
}, PREFIX_OPCODE
},
3849 { "minpd", { XM
, EXx
}, PREFIX_OPCODE
},
3850 { "minsd", { XM
, EXq
}, PREFIX_OPCODE
},
3855 { "divps", { XM
, EXx
}, PREFIX_OPCODE
},
3856 { "divss", { XM
, EXd
}, PREFIX_OPCODE
},
3857 { "divpd", { XM
, EXx
}, PREFIX_OPCODE
},
3858 { "divsd", { XM
, EXq
}, PREFIX_OPCODE
},
3863 { "maxps", { XM
, EXx
}, PREFIX_OPCODE
},
3864 { "maxss", { XM
, EXd
}, PREFIX_OPCODE
},
3865 { "maxpd", { XM
, EXx
}, PREFIX_OPCODE
},
3866 { "maxsd", { XM
, EXq
}, PREFIX_OPCODE
},
3871 { "punpcklbw",{ MX
, EMd
}, PREFIX_OPCODE
},
3873 { "punpcklbw",{ MX
, EMx
}, PREFIX_OPCODE
},
3878 { "punpcklwd",{ MX
, EMd
}, PREFIX_OPCODE
},
3880 { "punpcklwd",{ MX
, EMx
}, PREFIX_OPCODE
},
3885 { "punpckldq",{ MX
, EMd
}, PREFIX_OPCODE
},
3887 { "punpckldq",{ MX
, EMx
}, PREFIX_OPCODE
},
3894 { "punpcklqdq", { XM
, EXx
}, PREFIX_OPCODE
},
3901 { "punpckhqdq", { XM
, EXx
}, PREFIX_OPCODE
},
3906 { "movq", { MX
, EM
}, PREFIX_OPCODE
},
3907 { "movdqu", { XM
, EXx
}, PREFIX_OPCODE
},
3908 { "movdqa", { XM
, EXx
}, PREFIX_OPCODE
},
3913 { "pshufw", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
3914 { "pshufhw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3915 { "pshufd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3916 { "pshuflw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3919 /* PREFIX_0F73_REG_3 */
3923 { "psrldq", { XS
, Ib
}, 0 },
3926 /* PREFIX_0F73_REG_7 */
3930 { "pslldq", { XS
, Ib
}, 0 },
3935 {"vmread", { Em
, Gm
}, 0 },
3937 {"extrq", { XS
, Ib
, Ib
}, 0 },
3938 {"insertq", { XM
, XS
, Ib
, Ib
}, 0 },
3943 {"vmwrite", { Gm
, Em
}, 0 },
3945 {"extrq", { XM
, XS
}, 0 },
3946 {"insertq", { XM
, XS
}, 0 },
3953 { "haddpd", { XM
, EXx
}, PREFIX_OPCODE
},
3954 { "haddps", { XM
, EXx
}, PREFIX_OPCODE
},
3961 { "hsubpd", { XM
, EXx
}, PREFIX_OPCODE
},
3962 { "hsubps", { XM
, EXx
}, PREFIX_OPCODE
},
3967 { "movK", { Edq
, MX
}, PREFIX_OPCODE
},
3968 { "movq", { XM
, EXq
}, PREFIX_OPCODE
},
3969 { "movK", { Edq
, XM
}, PREFIX_OPCODE
},
3974 { "movq", { EMS
, MX
}, PREFIX_OPCODE
},
3975 { "movdqu", { EXxS
, XM
}, PREFIX_OPCODE
},
3976 { "movdqa", { EXxS
, XM
}, PREFIX_OPCODE
},
3979 /* PREFIX_0FAE_REG_0 */
3982 { "rdfsbase", { Ev
}, 0 },
3985 /* PREFIX_0FAE_REG_1 */
3988 { "rdgsbase", { Ev
}, 0 },
3991 /* PREFIX_0FAE_REG_2 */
3994 { "wrfsbase", { Ev
}, 0 },
3997 /* PREFIX_0FAE_REG_3 */
4000 { "wrgsbase", { Ev
}, 0 },
4003 /* PREFIX_0FAE_REG_6 */
4005 { "xsaveopt", { FXSAVE
}, 0 },
4007 { "clwb", { Mb
}, 0 },
4010 /* PREFIX_0FAE_REG_7 */
4012 { "clflush", { Mb
}, 0 },
4014 { "clflushopt", { Mb
}, 0 },
4017 /* PREFIX_RM_0_0FAE_REG_7 */
4019 { "sfence", { Skip_MODRM
}, 0 },
4021 { "pcommit", { Skip_MODRM
}, 0 },
4027 { "popcntS", { Gv
, Ev
}, 0 },
4032 { "bsfS", { Gv
, Ev
}, 0 },
4033 { "tzcntS", { Gv
, Ev
}, 0 },
4034 { "bsfS", { Gv
, Ev
}, 0 },
4039 { "bsrS", { Gv
, Ev
}, 0 },
4040 { "lzcntS", { Gv
, Ev
}, 0 },
4041 { "bsrS", { Gv
, Ev
}, 0 },
4046 { "cmpps", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
4047 { "cmpss", { XM
, EXd
, CMP
}, PREFIX_OPCODE
},
4048 { "cmppd", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
4049 { "cmpsd", { XM
, EXq
, CMP
}, PREFIX_OPCODE
},
4052 /* PREFIX_MOD_0_0FC3 */
4054 { "movntiS", { Ev
, Gv
}, PREFIX_OPCODE
},
4057 /* PREFIX_MOD_0_0FC7_REG_6 */
4059 { "vmptrld",{ Mq
}, 0 },
4060 { "vmxon", { Mq
}, 0 },
4061 { "vmclear",{ Mq
}, 0 },
4064 /* PREFIX_MOD_3_0FC7_REG_6 */
4066 { "rdrand", { Ev
}, 0 },
4068 { "rdrand", { Ev
}, 0 }
4071 /* PREFIX_MOD_3_0FC7_REG_7 */
4073 { "rdseed", { Ev
}, 0 },
4075 { "rdseed", { Ev
}, 0 },
4082 { "addsubpd", { XM
, EXx
}, 0 },
4083 { "addsubps", { XM
, EXx
}, 0 },
4089 { "movq2dq",{ XM
, MS
}, 0 },
4090 { "movq", { EXqS
, XM
}, 0 },
4091 { "movdq2q",{ MX
, XS
}, 0 },
4097 { "cvtdq2pd", { XM
, EXq
}, PREFIX_OPCODE
},
4098 { "cvttpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
4099 { "cvtpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
4104 { "movntq", { Mq
, MX
}, PREFIX_OPCODE
},
4106 { MOD_TABLE (MOD_0FE7_PREFIX_2
) },
4114 { MOD_TABLE (MOD_0FF0_PREFIX_3
) },
4119 { "maskmovq", { MX
, MS
}, PREFIX_OPCODE
},
4121 { "maskmovdqu", { XM
, XS
}, PREFIX_OPCODE
},
4128 { "pblendvb", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4135 { "blendvps", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4142 { "blendvpd", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4149 { "ptest", { XM
, EXx
}, PREFIX_OPCODE
},
4156 { "pmovsxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4163 { "pmovsxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4170 { "pmovsxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4177 { "pmovsxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4184 { "pmovsxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4191 { "pmovsxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4198 { "pmuldq", { XM
, EXx
}, PREFIX_OPCODE
},
4205 { "pcmpeqq", { XM
, EXx
}, PREFIX_OPCODE
},
4212 { MOD_TABLE (MOD_0F382A_PREFIX_2
) },
4219 { "packusdw", { XM
, EXx
}, PREFIX_OPCODE
},
4226 { "pmovzxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4233 { "pmovzxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4240 { "pmovzxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4247 { "pmovzxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4254 { "pmovzxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4261 { "pmovzxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4268 { "pcmpgtq", { XM
, EXx
}, PREFIX_OPCODE
},
4275 { "pminsb", { XM
, EXx
}, PREFIX_OPCODE
},
4282 { "pminsd", { XM
, EXx
}, PREFIX_OPCODE
},
4289 { "pminuw", { XM
, EXx
}, PREFIX_OPCODE
},
4296 { "pminud", { XM
, EXx
}, PREFIX_OPCODE
},
4303 { "pmaxsb", { XM
, EXx
}, PREFIX_OPCODE
},
4310 { "pmaxsd", { XM
, EXx
}, PREFIX_OPCODE
},
4317 { "pmaxuw", { XM
, EXx
}, PREFIX_OPCODE
},
4324 { "pmaxud", { XM
, EXx
}, PREFIX_OPCODE
},
4331 { "pmulld", { XM
, EXx
}, PREFIX_OPCODE
},
4338 { "phminposuw", { XM
, EXx
}, PREFIX_OPCODE
},
4345 { "invept", { Gm
, Mo
}, PREFIX_OPCODE
},
4352 { "invvpid", { Gm
, Mo
}, PREFIX_OPCODE
},
4359 { "invpcid", { Gm
, M
}, PREFIX_OPCODE
},
4364 { "sha1nexte", { XM
, EXxmm
}, PREFIX_OPCODE
},
4369 { "sha1msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4374 { "sha1msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4379 { "sha256rnds2", { XM
, EXxmm
, XMM0
}, PREFIX_OPCODE
},
4384 { "sha256msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4389 { "sha256msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4396 { "aesimc", { XM
, EXx
}, PREFIX_OPCODE
},
4403 { "aesenc", { XM
, EXx
}, PREFIX_OPCODE
},
4410 { "aesenclast", { XM
, EXx
}, PREFIX_OPCODE
},
4417 { "aesdec", { XM
, EXx
}, PREFIX_OPCODE
},
4424 { "aesdeclast", { XM
, EXx
}, PREFIX_OPCODE
},
4429 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4431 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4432 { "crc32", { Gdq
, { CRC32_Fixup
, b_mode
} }, PREFIX_OPCODE
},
4437 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
}, PREFIX_OPCODE
},
4439 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
}, PREFIX_OPCODE
},
4440 { "crc32", { Gdq
, { CRC32_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4446 { "adoxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4447 { "adcxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4455 { "roundps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4462 { "roundpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4469 { "roundss", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4476 { "roundsd", { XM
, EXq
, Ib
}, PREFIX_OPCODE
},
4483 { "blendps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4490 { "blendpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4497 { "pblendw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4504 { "pextrb", { Edqb
, XM
, Ib
}, PREFIX_OPCODE
},
4511 { "pextrw", { Edqw
, XM
, Ib
}, PREFIX_OPCODE
},
4518 { "pextrK", { Edq
, XM
, Ib
}, PREFIX_OPCODE
},
4525 { "extractps", { Edqd
, XM
, Ib
}, PREFIX_OPCODE
},
4532 { "pinsrb", { XM
, Edqb
, Ib
}, PREFIX_OPCODE
},
4539 { "insertps", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4546 { "pinsrK", { XM
, Edq
, Ib
}, PREFIX_OPCODE
},
4553 { "dpps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4560 { "dppd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4567 { "mpsadbw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4574 { "pclmulqdq", { XM
, EXx
, PCLMUL
}, PREFIX_OPCODE
},
4581 { "pcmpestrm", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4588 { "pcmpestri", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4595 { "pcmpistrm", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4602 { "pcmpistri", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4607 { "sha1rnds4", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4614 { "aeskeygenassist", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4617 /* PREFIX_VEX_0F10 */
4619 { VEX_W_TABLE (VEX_W_0F10_P_0
) },
4620 { VEX_LEN_TABLE (VEX_LEN_0F10_P_1
) },
4621 { VEX_W_TABLE (VEX_W_0F10_P_2
) },
4622 { VEX_LEN_TABLE (VEX_LEN_0F10_P_3
) },
4625 /* PREFIX_VEX_0F11 */
4627 { VEX_W_TABLE (VEX_W_0F11_P_0
) },
4628 { VEX_LEN_TABLE (VEX_LEN_0F11_P_1
) },
4629 { VEX_W_TABLE (VEX_W_0F11_P_2
) },
4630 { VEX_LEN_TABLE (VEX_LEN_0F11_P_3
) },
4633 /* PREFIX_VEX_0F12 */
4635 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0
) },
4636 { VEX_W_TABLE (VEX_W_0F12_P_1
) },
4637 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2
) },
4638 { VEX_W_TABLE (VEX_W_0F12_P_3
) },
4641 /* PREFIX_VEX_0F16 */
4643 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0
) },
4644 { VEX_W_TABLE (VEX_W_0F16_P_1
) },
4645 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2
) },
4648 /* PREFIX_VEX_0F2A */
4651 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1
) },
4653 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3
) },
4656 /* PREFIX_VEX_0F2C */
4659 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1
) },
4661 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3
) },
4664 /* PREFIX_VEX_0F2D */
4667 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1
) },
4669 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3
) },
4672 /* PREFIX_VEX_0F2E */
4674 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0
) },
4676 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2
) },
4679 /* PREFIX_VEX_0F2F */
4681 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0
) },
4683 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2
) },
4686 /* PREFIX_VEX_0F41 */
4688 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0
) },
4690 { VEX_LEN_TABLE (VEX_LEN_0F41_P_2
) },
4693 /* PREFIX_VEX_0F42 */
4695 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0
) },
4697 { VEX_LEN_TABLE (VEX_LEN_0F42_P_2
) },
4700 /* PREFIX_VEX_0F44 */
4702 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0
) },
4704 { VEX_LEN_TABLE (VEX_LEN_0F44_P_2
) },
4707 /* PREFIX_VEX_0F45 */
4709 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0
) },
4711 { VEX_LEN_TABLE (VEX_LEN_0F45_P_2
) },
4714 /* PREFIX_VEX_0F46 */
4716 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0
) },
4718 { VEX_LEN_TABLE (VEX_LEN_0F46_P_2
) },
4721 /* PREFIX_VEX_0F47 */
4723 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0
) },
4725 { VEX_LEN_TABLE (VEX_LEN_0F47_P_2
) },
4728 /* PREFIX_VEX_0F4A */
4730 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0
) },
4732 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2
) },
4735 /* PREFIX_VEX_0F4B */
4737 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0
) },
4739 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2
) },
4742 /* PREFIX_VEX_0F51 */
4744 { VEX_W_TABLE (VEX_W_0F51_P_0
) },
4745 { VEX_LEN_TABLE (VEX_LEN_0F51_P_1
) },
4746 { VEX_W_TABLE (VEX_W_0F51_P_2
) },
4747 { VEX_LEN_TABLE (VEX_LEN_0F51_P_3
) },
4750 /* PREFIX_VEX_0F52 */
4752 { VEX_W_TABLE (VEX_W_0F52_P_0
) },
4753 { VEX_LEN_TABLE (VEX_LEN_0F52_P_1
) },
4756 /* PREFIX_VEX_0F53 */
4758 { VEX_W_TABLE (VEX_W_0F53_P_0
) },
4759 { VEX_LEN_TABLE (VEX_LEN_0F53_P_1
) },
4762 /* PREFIX_VEX_0F58 */
4764 { VEX_W_TABLE (VEX_W_0F58_P_0
) },
4765 { VEX_LEN_TABLE (VEX_LEN_0F58_P_1
) },
4766 { VEX_W_TABLE (VEX_W_0F58_P_2
) },
4767 { VEX_LEN_TABLE (VEX_LEN_0F58_P_3
) },
4770 /* PREFIX_VEX_0F59 */
4772 { VEX_W_TABLE (VEX_W_0F59_P_0
) },
4773 { VEX_LEN_TABLE (VEX_LEN_0F59_P_1
) },
4774 { VEX_W_TABLE (VEX_W_0F59_P_2
) },
4775 { VEX_LEN_TABLE (VEX_LEN_0F59_P_3
) },
4778 /* PREFIX_VEX_0F5A */
4780 { VEX_W_TABLE (VEX_W_0F5A_P_0
) },
4781 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1
) },
4782 { "vcvtpd2ps%XY", { XMM
, EXx
}, 0 },
4783 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3
) },
4786 /* PREFIX_VEX_0F5B */
4788 { VEX_W_TABLE (VEX_W_0F5B_P_0
) },
4789 { VEX_W_TABLE (VEX_W_0F5B_P_1
) },
4790 { VEX_W_TABLE (VEX_W_0F5B_P_2
) },
4793 /* PREFIX_VEX_0F5C */
4795 { VEX_W_TABLE (VEX_W_0F5C_P_0
) },
4796 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1
) },
4797 { VEX_W_TABLE (VEX_W_0F5C_P_2
) },
4798 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3
) },
4801 /* PREFIX_VEX_0F5D */
4803 { VEX_W_TABLE (VEX_W_0F5D_P_0
) },
4804 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1
) },
4805 { VEX_W_TABLE (VEX_W_0F5D_P_2
) },
4806 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3
) },
4809 /* PREFIX_VEX_0F5E */
4811 { VEX_W_TABLE (VEX_W_0F5E_P_0
) },
4812 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1
) },
4813 { VEX_W_TABLE (VEX_W_0F5E_P_2
) },
4814 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3
) },
4817 /* PREFIX_VEX_0F5F */
4819 { VEX_W_TABLE (VEX_W_0F5F_P_0
) },
4820 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1
) },
4821 { VEX_W_TABLE (VEX_W_0F5F_P_2
) },
4822 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3
) },
4825 /* PREFIX_VEX_0F60 */
4829 { VEX_W_TABLE (VEX_W_0F60_P_2
) },
4832 /* PREFIX_VEX_0F61 */
4836 { VEX_W_TABLE (VEX_W_0F61_P_2
) },
4839 /* PREFIX_VEX_0F62 */
4843 { VEX_W_TABLE (VEX_W_0F62_P_2
) },
4846 /* PREFIX_VEX_0F63 */
4850 { VEX_W_TABLE (VEX_W_0F63_P_2
) },
4853 /* PREFIX_VEX_0F64 */
4857 { VEX_W_TABLE (VEX_W_0F64_P_2
) },
4860 /* PREFIX_VEX_0F65 */
4864 { VEX_W_TABLE (VEX_W_0F65_P_2
) },
4867 /* PREFIX_VEX_0F66 */
4871 { VEX_W_TABLE (VEX_W_0F66_P_2
) },
4874 /* PREFIX_VEX_0F67 */
4878 { VEX_W_TABLE (VEX_W_0F67_P_2
) },
4881 /* PREFIX_VEX_0F68 */
4885 { VEX_W_TABLE (VEX_W_0F68_P_2
) },
4888 /* PREFIX_VEX_0F69 */
4892 { VEX_W_TABLE (VEX_W_0F69_P_2
) },
4895 /* PREFIX_VEX_0F6A */
4899 { VEX_W_TABLE (VEX_W_0F6A_P_2
) },
4902 /* PREFIX_VEX_0F6B */
4906 { VEX_W_TABLE (VEX_W_0F6B_P_2
) },
4909 /* PREFIX_VEX_0F6C */
4913 { VEX_W_TABLE (VEX_W_0F6C_P_2
) },
4916 /* PREFIX_VEX_0F6D */
4920 { VEX_W_TABLE (VEX_W_0F6D_P_2
) },
4923 /* PREFIX_VEX_0F6E */
4927 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2
) },
4930 /* PREFIX_VEX_0F6F */
4933 { VEX_W_TABLE (VEX_W_0F6F_P_1
) },
4934 { VEX_W_TABLE (VEX_W_0F6F_P_2
) },
4937 /* PREFIX_VEX_0F70 */
4940 { VEX_W_TABLE (VEX_W_0F70_P_1
) },
4941 { VEX_W_TABLE (VEX_W_0F70_P_2
) },
4942 { VEX_W_TABLE (VEX_W_0F70_P_3
) },
4945 /* PREFIX_VEX_0F71_REG_2 */
4949 { VEX_W_TABLE (VEX_W_0F71_R_2_P_2
) },
4952 /* PREFIX_VEX_0F71_REG_4 */
4956 { VEX_W_TABLE (VEX_W_0F71_R_4_P_2
) },
4959 /* PREFIX_VEX_0F71_REG_6 */
4963 { VEX_W_TABLE (VEX_W_0F71_R_6_P_2
) },
4966 /* PREFIX_VEX_0F72_REG_2 */
4970 { VEX_W_TABLE (VEX_W_0F72_R_2_P_2
) },
4973 /* PREFIX_VEX_0F72_REG_4 */
4977 { VEX_W_TABLE (VEX_W_0F72_R_4_P_2
) },
4980 /* PREFIX_VEX_0F72_REG_6 */
4984 { VEX_W_TABLE (VEX_W_0F72_R_6_P_2
) },
4987 /* PREFIX_VEX_0F73_REG_2 */
4991 { VEX_W_TABLE (VEX_W_0F73_R_2_P_2
) },
4994 /* PREFIX_VEX_0F73_REG_3 */
4998 { VEX_W_TABLE (VEX_W_0F73_R_3_P_2
) },
5001 /* PREFIX_VEX_0F73_REG_6 */
5005 { VEX_W_TABLE (VEX_W_0F73_R_6_P_2
) },
5008 /* PREFIX_VEX_0F73_REG_7 */
5012 { VEX_W_TABLE (VEX_W_0F73_R_7_P_2
) },
5015 /* PREFIX_VEX_0F74 */
5019 { VEX_W_TABLE (VEX_W_0F74_P_2
) },
5022 /* PREFIX_VEX_0F75 */
5026 { VEX_W_TABLE (VEX_W_0F75_P_2
) },
5029 /* PREFIX_VEX_0F76 */
5033 { VEX_W_TABLE (VEX_W_0F76_P_2
) },
5036 /* PREFIX_VEX_0F77 */
5038 { VEX_W_TABLE (VEX_W_0F77_P_0
) },
5041 /* PREFIX_VEX_0F7C */
5045 { VEX_W_TABLE (VEX_W_0F7C_P_2
) },
5046 { VEX_W_TABLE (VEX_W_0F7C_P_3
) },
5049 /* PREFIX_VEX_0F7D */
5053 { VEX_W_TABLE (VEX_W_0F7D_P_2
) },
5054 { VEX_W_TABLE (VEX_W_0F7D_P_3
) },
5057 /* PREFIX_VEX_0F7E */
5060 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1
) },
5061 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2
) },
5064 /* PREFIX_VEX_0F7F */
5067 { VEX_W_TABLE (VEX_W_0F7F_P_1
) },
5068 { VEX_W_TABLE (VEX_W_0F7F_P_2
) },
5071 /* PREFIX_VEX_0F90 */
5073 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0
) },
5075 { VEX_LEN_TABLE (VEX_LEN_0F90_P_2
) },
5078 /* PREFIX_VEX_0F91 */
5080 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0
) },
5082 { VEX_LEN_TABLE (VEX_LEN_0F91_P_2
) },
5085 /* PREFIX_VEX_0F92 */
5087 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0
) },
5089 { VEX_LEN_TABLE (VEX_LEN_0F92_P_2
) },
5090 { VEX_LEN_TABLE (VEX_LEN_0F92_P_3
) },
5093 /* PREFIX_VEX_0F93 */
5095 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0
) },
5097 { VEX_LEN_TABLE (VEX_LEN_0F93_P_2
) },
5098 { VEX_LEN_TABLE (VEX_LEN_0F93_P_3
) },
5101 /* PREFIX_VEX_0F98 */
5103 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0
) },
5105 { VEX_LEN_TABLE (VEX_LEN_0F98_P_2
) },
5108 /* PREFIX_VEX_0F99 */
5110 { VEX_LEN_TABLE (VEX_LEN_0F99_P_0
) },
5112 { VEX_LEN_TABLE (VEX_LEN_0F99_P_2
) },
5115 /* PREFIX_VEX_0FC2 */
5117 { VEX_W_TABLE (VEX_W_0FC2_P_0
) },
5118 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1
) },
5119 { VEX_W_TABLE (VEX_W_0FC2_P_2
) },
5120 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3
) },
5123 /* PREFIX_VEX_0FC4 */
5127 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2
) },
5130 /* PREFIX_VEX_0FC5 */
5134 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2
) },
5137 /* PREFIX_VEX_0FD0 */
5141 { VEX_W_TABLE (VEX_W_0FD0_P_2
) },
5142 { VEX_W_TABLE (VEX_W_0FD0_P_3
) },
5145 /* PREFIX_VEX_0FD1 */
5149 { VEX_W_TABLE (VEX_W_0FD1_P_2
) },
5152 /* PREFIX_VEX_0FD2 */
5156 { VEX_W_TABLE (VEX_W_0FD2_P_2
) },
5159 /* PREFIX_VEX_0FD3 */
5163 { VEX_W_TABLE (VEX_W_0FD3_P_2
) },
5166 /* PREFIX_VEX_0FD4 */
5170 { VEX_W_TABLE (VEX_W_0FD4_P_2
) },
5173 /* PREFIX_VEX_0FD5 */
5177 { VEX_W_TABLE (VEX_W_0FD5_P_2
) },
5180 /* PREFIX_VEX_0FD6 */
5184 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2
) },
5187 /* PREFIX_VEX_0FD7 */
5191 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2
) },
5194 /* PREFIX_VEX_0FD8 */
5198 { VEX_W_TABLE (VEX_W_0FD8_P_2
) },
5201 /* PREFIX_VEX_0FD9 */
5205 { VEX_W_TABLE (VEX_W_0FD9_P_2
) },
5208 /* PREFIX_VEX_0FDA */
5212 { VEX_W_TABLE (VEX_W_0FDA_P_2
) },
5215 /* PREFIX_VEX_0FDB */
5219 { VEX_W_TABLE (VEX_W_0FDB_P_2
) },
5222 /* PREFIX_VEX_0FDC */
5226 { VEX_W_TABLE (VEX_W_0FDC_P_2
) },
5229 /* PREFIX_VEX_0FDD */
5233 { VEX_W_TABLE (VEX_W_0FDD_P_2
) },
5236 /* PREFIX_VEX_0FDE */
5240 { VEX_W_TABLE (VEX_W_0FDE_P_2
) },
5243 /* PREFIX_VEX_0FDF */
5247 { VEX_W_TABLE (VEX_W_0FDF_P_2
) },
5250 /* PREFIX_VEX_0FE0 */
5254 { VEX_W_TABLE (VEX_W_0FE0_P_2
) },
5257 /* PREFIX_VEX_0FE1 */
5261 { VEX_W_TABLE (VEX_W_0FE1_P_2
) },
5264 /* PREFIX_VEX_0FE2 */
5268 { VEX_W_TABLE (VEX_W_0FE2_P_2
) },
5271 /* PREFIX_VEX_0FE3 */
5275 { VEX_W_TABLE (VEX_W_0FE3_P_2
) },
5278 /* PREFIX_VEX_0FE4 */
5282 { VEX_W_TABLE (VEX_W_0FE4_P_2
) },
5285 /* PREFIX_VEX_0FE5 */
5289 { VEX_W_TABLE (VEX_W_0FE5_P_2
) },
5292 /* PREFIX_VEX_0FE6 */
5295 { VEX_W_TABLE (VEX_W_0FE6_P_1
) },
5296 { VEX_W_TABLE (VEX_W_0FE6_P_2
) },
5297 { VEX_W_TABLE (VEX_W_0FE6_P_3
) },
5300 /* PREFIX_VEX_0FE7 */
5304 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2
) },
5307 /* PREFIX_VEX_0FE8 */
5311 { VEX_W_TABLE (VEX_W_0FE8_P_2
) },
5314 /* PREFIX_VEX_0FE9 */
5318 { VEX_W_TABLE (VEX_W_0FE9_P_2
) },
5321 /* PREFIX_VEX_0FEA */
5325 { VEX_W_TABLE (VEX_W_0FEA_P_2
) },
5328 /* PREFIX_VEX_0FEB */
5332 { VEX_W_TABLE (VEX_W_0FEB_P_2
) },
5335 /* PREFIX_VEX_0FEC */
5339 { VEX_W_TABLE (VEX_W_0FEC_P_2
) },
5342 /* PREFIX_VEX_0FED */
5346 { VEX_W_TABLE (VEX_W_0FED_P_2
) },
5349 /* PREFIX_VEX_0FEE */
5353 { VEX_W_TABLE (VEX_W_0FEE_P_2
) },
5356 /* PREFIX_VEX_0FEF */
5360 { VEX_W_TABLE (VEX_W_0FEF_P_2
) },
5363 /* PREFIX_VEX_0FF0 */
5368 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3
) },
5371 /* PREFIX_VEX_0FF1 */
5375 { VEX_W_TABLE (VEX_W_0FF1_P_2
) },
5378 /* PREFIX_VEX_0FF2 */
5382 { VEX_W_TABLE (VEX_W_0FF2_P_2
) },
5385 /* PREFIX_VEX_0FF3 */
5389 { VEX_W_TABLE (VEX_W_0FF3_P_2
) },
5392 /* PREFIX_VEX_0FF4 */
5396 { VEX_W_TABLE (VEX_W_0FF4_P_2
) },
5399 /* PREFIX_VEX_0FF5 */
5403 { VEX_W_TABLE (VEX_W_0FF5_P_2
) },
5406 /* PREFIX_VEX_0FF6 */
5410 { VEX_W_TABLE (VEX_W_0FF6_P_2
) },
5413 /* PREFIX_VEX_0FF7 */
5417 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2
) },
5420 /* PREFIX_VEX_0FF8 */
5424 { VEX_W_TABLE (VEX_W_0FF8_P_2
) },
5427 /* PREFIX_VEX_0FF9 */
5431 { VEX_W_TABLE (VEX_W_0FF9_P_2
) },
5434 /* PREFIX_VEX_0FFA */
5438 { VEX_W_TABLE (VEX_W_0FFA_P_2
) },
5441 /* PREFIX_VEX_0FFB */
5445 { VEX_W_TABLE (VEX_W_0FFB_P_2
) },
5448 /* PREFIX_VEX_0FFC */
5452 { VEX_W_TABLE (VEX_W_0FFC_P_2
) },
5455 /* PREFIX_VEX_0FFD */
5459 { VEX_W_TABLE (VEX_W_0FFD_P_2
) },
5462 /* PREFIX_VEX_0FFE */
5466 { VEX_W_TABLE (VEX_W_0FFE_P_2
) },
5469 /* PREFIX_VEX_0F3800 */
5473 { VEX_W_TABLE (VEX_W_0F3800_P_2
) },
5476 /* PREFIX_VEX_0F3801 */
5480 { VEX_W_TABLE (VEX_W_0F3801_P_2
) },
5483 /* PREFIX_VEX_0F3802 */
5487 { VEX_W_TABLE (VEX_W_0F3802_P_2
) },
5490 /* PREFIX_VEX_0F3803 */
5494 { VEX_W_TABLE (VEX_W_0F3803_P_2
) },
5497 /* PREFIX_VEX_0F3804 */
5501 { VEX_W_TABLE (VEX_W_0F3804_P_2
) },
5504 /* PREFIX_VEX_0F3805 */
5508 { VEX_W_TABLE (VEX_W_0F3805_P_2
) },
5511 /* PREFIX_VEX_0F3806 */
5515 { VEX_W_TABLE (VEX_W_0F3806_P_2
) },
5518 /* PREFIX_VEX_0F3807 */
5522 { VEX_W_TABLE (VEX_W_0F3807_P_2
) },
5525 /* PREFIX_VEX_0F3808 */
5529 { VEX_W_TABLE (VEX_W_0F3808_P_2
) },
5532 /* PREFIX_VEX_0F3809 */
5536 { VEX_W_TABLE (VEX_W_0F3809_P_2
) },
5539 /* PREFIX_VEX_0F380A */
5543 { VEX_W_TABLE (VEX_W_0F380A_P_2
) },
5546 /* PREFIX_VEX_0F380B */
5550 { VEX_W_TABLE (VEX_W_0F380B_P_2
) },
5553 /* PREFIX_VEX_0F380C */
5557 { VEX_W_TABLE (VEX_W_0F380C_P_2
) },
5560 /* PREFIX_VEX_0F380D */
5564 { VEX_W_TABLE (VEX_W_0F380D_P_2
) },
5567 /* PREFIX_VEX_0F380E */
5571 { VEX_W_TABLE (VEX_W_0F380E_P_2
) },
5574 /* PREFIX_VEX_0F380F */
5578 { VEX_W_TABLE (VEX_W_0F380F_P_2
) },
5581 /* PREFIX_VEX_0F3813 */
5585 { "vcvtph2ps", { XM
, EXxmmq
}, 0 },
5588 /* PREFIX_VEX_0F3816 */
5592 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2
) },
5595 /* PREFIX_VEX_0F3817 */
5599 { VEX_W_TABLE (VEX_W_0F3817_P_2
) },
5602 /* PREFIX_VEX_0F3818 */
5606 { VEX_W_TABLE (VEX_W_0F3818_P_2
) },
5609 /* PREFIX_VEX_0F3819 */
5613 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2
) },
5616 /* PREFIX_VEX_0F381A */
5620 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2
) },
5623 /* PREFIX_VEX_0F381C */
5627 { VEX_W_TABLE (VEX_W_0F381C_P_2
) },
5630 /* PREFIX_VEX_0F381D */
5634 { VEX_W_TABLE (VEX_W_0F381D_P_2
) },
5637 /* PREFIX_VEX_0F381E */
5641 { VEX_W_TABLE (VEX_W_0F381E_P_2
) },
5644 /* PREFIX_VEX_0F3820 */
5648 { VEX_W_TABLE (VEX_W_0F3820_P_2
) },
5651 /* PREFIX_VEX_0F3821 */
5655 { VEX_W_TABLE (VEX_W_0F3821_P_2
) },
5658 /* PREFIX_VEX_0F3822 */
5662 { VEX_W_TABLE (VEX_W_0F3822_P_2
) },
5665 /* PREFIX_VEX_0F3823 */
5669 { VEX_W_TABLE (VEX_W_0F3823_P_2
) },
5672 /* PREFIX_VEX_0F3824 */
5676 { VEX_W_TABLE (VEX_W_0F3824_P_2
) },
5679 /* PREFIX_VEX_0F3825 */
5683 { VEX_W_TABLE (VEX_W_0F3825_P_2
) },
5686 /* PREFIX_VEX_0F3828 */
5690 { VEX_W_TABLE (VEX_W_0F3828_P_2
) },
5693 /* PREFIX_VEX_0F3829 */
5697 { VEX_W_TABLE (VEX_W_0F3829_P_2
) },
5700 /* PREFIX_VEX_0F382A */
5704 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2
) },
5707 /* PREFIX_VEX_0F382B */
5711 { VEX_W_TABLE (VEX_W_0F382B_P_2
) },
5714 /* PREFIX_VEX_0F382C */
5718 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2
) },
5721 /* PREFIX_VEX_0F382D */
5725 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2
) },
5728 /* PREFIX_VEX_0F382E */
5732 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2
) },
5735 /* PREFIX_VEX_0F382F */
5739 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2
) },
5742 /* PREFIX_VEX_0F3830 */
5746 { VEX_W_TABLE (VEX_W_0F3830_P_2
) },
5749 /* PREFIX_VEX_0F3831 */
5753 { VEX_W_TABLE (VEX_W_0F3831_P_2
) },
5756 /* PREFIX_VEX_0F3832 */
5760 { VEX_W_TABLE (VEX_W_0F3832_P_2
) },
5763 /* PREFIX_VEX_0F3833 */
5767 { VEX_W_TABLE (VEX_W_0F3833_P_2
) },
5770 /* PREFIX_VEX_0F3834 */
5774 { VEX_W_TABLE (VEX_W_0F3834_P_2
) },
5777 /* PREFIX_VEX_0F3835 */
5781 { VEX_W_TABLE (VEX_W_0F3835_P_2
) },
5784 /* PREFIX_VEX_0F3836 */
5788 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2
) },
5791 /* PREFIX_VEX_0F3837 */
5795 { VEX_W_TABLE (VEX_W_0F3837_P_2
) },
5798 /* PREFIX_VEX_0F3838 */
5802 { VEX_W_TABLE (VEX_W_0F3838_P_2
) },
5805 /* PREFIX_VEX_0F3839 */
5809 { VEX_W_TABLE (VEX_W_0F3839_P_2
) },
5812 /* PREFIX_VEX_0F383A */
5816 { VEX_W_TABLE (VEX_W_0F383A_P_2
) },
5819 /* PREFIX_VEX_0F383B */
5823 { VEX_W_TABLE (VEX_W_0F383B_P_2
) },
5826 /* PREFIX_VEX_0F383C */
5830 { VEX_W_TABLE (VEX_W_0F383C_P_2
) },
5833 /* PREFIX_VEX_0F383D */
5837 { VEX_W_TABLE (VEX_W_0F383D_P_2
) },
5840 /* PREFIX_VEX_0F383E */
5844 { VEX_W_TABLE (VEX_W_0F383E_P_2
) },
5847 /* PREFIX_VEX_0F383F */
5851 { VEX_W_TABLE (VEX_W_0F383F_P_2
) },
5854 /* PREFIX_VEX_0F3840 */
5858 { VEX_W_TABLE (VEX_W_0F3840_P_2
) },
5861 /* PREFIX_VEX_0F3841 */
5865 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2
) },
5868 /* PREFIX_VEX_0F3845 */
5872 { "vpsrlv%LW", { XM
, Vex
, EXx
}, 0 },
5875 /* PREFIX_VEX_0F3846 */
5879 { VEX_W_TABLE (VEX_W_0F3846_P_2
) },
5882 /* PREFIX_VEX_0F3847 */
5886 { "vpsllv%LW", { XM
, Vex
, EXx
}, 0 },
5889 /* PREFIX_VEX_0F3858 */
5893 { VEX_W_TABLE (VEX_W_0F3858_P_2
) },
5896 /* PREFIX_VEX_0F3859 */
5900 { VEX_W_TABLE (VEX_W_0F3859_P_2
) },
5903 /* PREFIX_VEX_0F385A */
5907 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2
) },
5910 /* PREFIX_VEX_0F3878 */
5914 { VEX_W_TABLE (VEX_W_0F3878_P_2
) },
5917 /* PREFIX_VEX_0F3879 */
5921 { VEX_W_TABLE (VEX_W_0F3879_P_2
) },
5924 /* PREFIX_VEX_0F388C */
5928 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2
) },
5931 /* PREFIX_VEX_0F388E */
5935 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2
) },
5938 /* PREFIX_VEX_0F3890 */
5942 { "vpgatherd%LW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
5945 /* PREFIX_VEX_0F3891 */
5949 { "vpgatherq%LW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
5952 /* PREFIX_VEX_0F3892 */
5956 { "vgatherdp%XW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
5959 /* PREFIX_VEX_0F3893 */
5963 { "vgatherqp%XW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
5966 /* PREFIX_VEX_0F3896 */
5970 { "vfmaddsub132p%XW", { XM
, Vex
, EXx
}, 0 },
5973 /* PREFIX_VEX_0F3897 */
5977 { "vfmsubadd132p%XW", { XM
, Vex
, EXx
}, 0 },
5980 /* PREFIX_VEX_0F3898 */
5984 { "vfmadd132p%XW", { XM
, Vex
, EXx
}, 0 },
5987 /* PREFIX_VEX_0F3899 */
5991 { "vfmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
5994 /* PREFIX_VEX_0F389A */
5998 { "vfmsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6001 /* PREFIX_VEX_0F389B */
6005 { "vfmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6008 /* PREFIX_VEX_0F389C */
6012 { "vfnmadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6015 /* PREFIX_VEX_0F389D */
6019 { "vfnmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6022 /* PREFIX_VEX_0F389E */
6026 { "vfnmsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6029 /* PREFIX_VEX_0F389F */
6033 { "vfnmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6036 /* PREFIX_VEX_0F38A6 */
6040 { "vfmaddsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6044 /* PREFIX_VEX_0F38A7 */
6048 { "vfmsubadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6051 /* PREFIX_VEX_0F38A8 */
6055 { "vfmadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6058 /* PREFIX_VEX_0F38A9 */
6062 { "vfmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6065 /* PREFIX_VEX_0F38AA */
6069 { "vfmsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6072 /* PREFIX_VEX_0F38AB */
6076 { "vfmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6079 /* PREFIX_VEX_0F38AC */
6083 { "vfnmadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6086 /* PREFIX_VEX_0F38AD */
6090 { "vfnmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6093 /* PREFIX_VEX_0F38AE */
6097 { "vfnmsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6100 /* PREFIX_VEX_0F38AF */
6104 { "vfnmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6107 /* PREFIX_VEX_0F38B6 */
6111 { "vfmaddsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6114 /* PREFIX_VEX_0F38B7 */
6118 { "vfmsubadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6121 /* PREFIX_VEX_0F38B8 */
6125 { "vfmadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6128 /* PREFIX_VEX_0F38B9 */
6132 { "vfmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6135 /* PREFIX_VEX_0F38BA */
6139 { "vfmsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6142 /* PREFIX_VEX_0F38BB */
6146 { "vfmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6149 /* PREFIX_VEX_0F38BC */
6153 { "vfnmadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6156 /* PREFIX_VEX_0F38BD */
6160 { "vfnmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6163 /* PREFIX_VEX_0F38BE */
6167 { "vfnmsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6170 /* PREFIX_VEX_0F38BF */
6174 { "vfnmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6177 /* PREFIX_VEX_0F38DB */
6181 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2
) },
6184 /* PREFIX_VEX_0F38DC */
6188 { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2
) },
6191 /* PREFIX_VEX_0F38DD */
6195 { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2
) },
6198 /* PREFIX_VEX_0F38DE */
6202 { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2
) },
6205 /* PREFIX_VEX_0F38DF */
6209 { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2
) },
6212 /* PREFIX_VEX_0F38F2 */
6214 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0
) },
6217 /* PREFIX_VEX_0F38F3_REG_1 */
6219 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0
) },
6222 /* PREFIX_VEX_0F38F3_REG_2 */
6224 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0
) },
6227 /* PREFIX_VEX_0F38F3_REG_3 */
6229 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0
) },
6232 /* PREFIX_VEX_0F38F5 */
6234 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0
) },
6235 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1
) },
6237 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3
) },
6240 /* PREFIX_VEX_0F38F6 */
6245 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3
) },
6248 /* PREFIX_VEX_0F38F7 */
6250 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0
) },
6251 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1
) },
6252 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2
) },
6253 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3
) },
6256 /* PREFIX_VEX_0F3A00 */
6260 { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2
) },
6263 /* PREFIX_VEX_0F3A01 */
6267 { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2
) },
6270 /* PREFIX_VEX_0F3A02 */
6274 { VEX_W_TABLE (VEX_W_0F3A02_P_2
) },
6277 /* PREFIX_VEX_0F3A04 */
6281 { VEX_W_TABLE (VEX_W_0F3A04_P_2
) },
6284 /* PREFIX_VEX_0F3A05 */
6288 { VEX_W_TABLE (VEX_W_0F3A05_P_2
) },
6291 /* PREFIX_VEX_0F3A06 */
6295 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2
) },
6298 /* PREFIX_VEX_0F3A08 */
6302 { VEX_W_TABLE (VEX_W_0F3A08_P_2
) },
6305 /* PREFIX_VEX_0F3A09 */
6309 { VEX_W_TABLE (VEX_W_0F3A09_P_2
) },
6312 /* PREFIX_VEX_0F3A0A */
6316 { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2
) },
6319 /* PREFIX_VEX_0F3A0B */
6323 { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2
) },
6326 /* PREFIX_VEX_0F3A0C */
6330 { VEX_W_TABLE (VEX_W_0F3A0C_P_2
) },
6333 /* PREFIX_VEX_0F3A0D */
6337 { VEX_W_TABLE (VEX_W_0F3A0D_P_2
) },
6340 /* PREFIX_VEX_0F3A0E */
6344 { VEX_W_TABLE (VEX_W_0F3A0E_P_2
) },
6347 /* PREFIX_VEX_0F3A0F */
6351 { VEX_W_TABLE (VEX_W_0F3A0F_P_2
) },
6354 /* PREFIX_VEX_0F3A14 */
6358 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2
) },
6361 /* PREFIX_VEX_0F3A15 */
6365 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2
) },
6368 /* PREFIX_VEX_0F3A16 */
6372 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2
) },
6375 /* PREFIX_VEX_0F3A17 */
6379 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2
) },
6382 /* PREFIX_VEX_0F3A18 */
6386 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2
) },
6389 /* PREFIX_VEX_0F3A19 */
6393 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2
) },
6396 /* PREFIX_VEX_0F3A1D */
6400 { "vcvtps2ph", { EXxmmq
, XM
, Ib
}, 0 },
6403 /* PREFIX_VEX_0F3A20 */
6407 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2
) },
6410 /* PREFIX_VEX_0F3A21 */
6414 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2
) },
6417 /* PREFIX_VEX_0F3A22 */
6421 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2
) },
6424 /* PREFIX_VEX_0F3A30 */
6428 { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2
) },
6431 /* PREFIX_VEX_0F3A31 */
6435 { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2
) },
6438 /* PREFIX_VEX_0F3A32 */
6442 { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2
) },
6445 /* PREFIX_VEX_0F3A33 */
6449 { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2
) },
6452 /* PREFIX_VEX_0F3A38 */
6456 { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2
) },
6459 /* PREFIX_VEX_0F3A39 */
6463 { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2
) },
6466 /* PREFIX_VEX_0F3A40 */
6470 { VEX_W_TABLE (VEX_W_0F3A40_P_2
) },
6473 /* PREFIX_VEX_0F3A41 */
6477 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2
) },
6480 /* PREFIX_VEX_0F3A42 */
6484 { VEX_W_TABLE (VEX_W_0F3A42_P_2
) },
6487 /* PREFIX_VEX_0F3A44 */
6491 { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2
) },
6494 /* PREFIX_VEX_0F3A46 */
6498 { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2
) },
6501 /* PREFIX_VEX_0F3A48 */
6505 { VEX_W_TABLE (VEX_W_0F3A48_P_2
) },
6508 /* PREFIX_VEX_0F3A49 */
6512 { VEX_W_TABLE (VEX_W_0F3A49_P_2
) },
6515 /* PREFIX_VEX_0F3A4A */
6519 { VEX_W_TABLE (VEX_W_0F3A4A_P_2
) },
6522 /* PREFIX_VEX_0F3A4B */
6526 { VEX_W_TABLE (VEX_W_0F3A4B_P_2
) },
6529 /* PREFIX_VEX_0F3A4C */
6533 { VEX_W_TABLE (VEX_W_0F3A4C_P_2
) },
6536 /* PREFIX_VEX_0F3A5C */
6540 { "vfmaddsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6543 /* PREFIX_VEX_0F3A5D */
6547 { "vfmaddsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6550 /* PREFIX_VEX_0F3A5E */
6554 { "vfmsubaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6557 /* PREFIX_VEX_0F3A5F */
6561 { "vfmsubaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6564 /* PREFIX_VEX_0F3A60 */
6568 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2
) },
6572 /* PREFIX_VEX_0F3A61 */
6576 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2
) },
6579 /* PREFIX_VEX_0F3A62 */
6583 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2
) },
6586 /* PREFIX_VEX_0F3A63 */
6590 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2
) },
6593 /* PREFIX_VEX_0F3A68 */
6597 { "vfmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6600 /* PREFIX_VEX_0F3A69 */
6604 { "vfmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6607 /* PREFIX_VEX_0F3A6A */
6611 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2
) },
6614 /* PREFIX_VEX_0F3A6B */
6618 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2
) },
6621 /* PREFIX_VEX_0F3A6C */
6625 { "vfmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6628 /* PREFIX_VEX_0F3A6D */
6632 { "vfmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6635 /* PREFIX_VEX_0F3A6E */
6639 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2
) },
6642 /* PREFIX_VEX_0F3A6F */
6646 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2
) },
6649 /* PREFIX_VEX_0F3A78 */
6653 { "vfnmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6656 /* PREFIX_VEX_0F3A79 */
6660 { "vfnmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6663 /* PREFIX_VEX_0F3A7A */
6667 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2
) },
6670 /* PREFIX_VEX_0F3A7B */
6674 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2
) },
6677 /* PREFIX_VEX_0F3A7C */
6681 { "vfnmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6685 /* PREFIX_VEX_0F3A7D */
6689 { "vfnmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6692 /* PREFIX_VEX_0F3A7E */
6696 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2
) },
6699 /* PREFIX_VEX_0F3A7F */
6703 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2
) },
6706 /* PREFIX_VEX_0F3ADF */
6710 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2
) },
6713 /* PREFIX_VEX_0F3AF0 */
6718 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3
) },
6721 #define NEED_PREFIX_TABLE
6722 #include "i386-dis-evex.h"
6723 #undef NEED_PREFIX_TABLE
6726 static const struct dis386 x86_64_table
[][2] = {
6729 { "pushP", { es
}, 0 },
6734 { "popP", { es
}, 0 },
6739 { "pushP", { cs
}, 0 },
6744 { "pushP", { ss
}, 0 },
6749 { "popP", { ss
}, 0 },
6754 { "pushP", { ds
}, 0 },
6759 { "popP", { ds
}, 0 },
6764 { "daa", { XX
}, 0 },
6769 { "das", { XX
}, 0 },
6774 { "aaa", { XX
}, 0 },
6779 { "aas", { XX
}, 0 },
6784 { "pushaP", { XX
}, 0 },
6789 { "popaP", { XX
}, 0 },
6794 { MOD_TABLE (MOD_62_32BIT
) },
6795 { EVEX_TABLE (EVEX_0F
) },
6800 { "arpl", { Ew
, Gw
}, 0 },
6801 { "movs{lq|xd}", { Gv
, Ed
}, 0 },
6806 { "ins{R|}", { Yzr
, indirDX
}, 0 },
6807 { "ins{G|}", { Yzr
, indirDX
}, 0 },
6812 { "outs{R|}", { indirDXr
, Xz
}, 0 },
6813 { "outs{G|}", { indirDXr
, Xz
}, 0 },
6818 { "Jcall{T|}", { Ap
}, 0 },
6823 { MOD_TABLE (MOD_C4_32BIT
) },
6824 { VEX_C4_TABLE (VEX_0F
) },
6829 { MOD_TABLE (MOD_C5_32BIT
) },
6830 { VEX_C5_TABLE (VEX_0F
) },
6835 { "into", { XX
}, 0 },
6840 { "aam", { Ib
}, 0 },
6845 { "aad", { Ib
}, 0 },
6850 { "callP", { Jv
, BND
}, 0 },
6851 { "call@", { Jv
, BND
}, 0 }
6856 { "jmpP", { Jv
, BND
}, 0 },
6857 { "jmp@", { Jv
, BND
}, 0 }
6862 { "Jjmp{T|}", { Ap
}, 0 },
6865 /* X86_64_0F01_REG_0 */
6867 { "sgdt{Q|IQ}", { M
}, 0 },
6868 { "sgdt", { M
}, 0 },
6871 /* X86_64_0F01_REG_1 */
6873 { "sidt{Q|IQ}", { M
}, 0 },
6874 { "sidt", { M
}, 0 },
6877 /* X86_64_0F01_REG_2 */
6879 { "lgdt{Q|Q}", { M
}, 0 },
6880 { "lgdt", { M
}, 0 },
6883 /* X86_64_0F01_REG_3 */
6885 { "lidt{Q|Q}", { M
}, 0 },
6886 { "lidt", { M
}, 0 },
6890 static const struct dis386 three_byte_table
[][256] = {
6892 /* THREE_BYTE_0F38 */
6895 { "pshufb", { MX
, EM
}, PREFIX_OPCODE
},
6896 { "phaddw", { MX
, EM
}, PREFIX_OPCODE
},
6897 { "phaddd", { MX
, EM
}, PREFIX_OPCODE
},
6898 { "phaddsw", { MX
, EM
}, PREFIX_OPCODE
},
6899 { "pmaddubsw", { MX
, EM
}, PREFIX_OPCODE
},
6900 { "phsubw", { MX
, EM
}, PREFIX_OPCODE
},
6901 { "phsubd", { MX
, EM
}, PREFIX_OPCODE
},
6902 { "phsubsw", { MX
, EM
}, PREFIX_OPCODE
},
6904 { "psignb", { MX
, EM
}, PREFIX_OPCODE
},
6905 { "psignw", { MX
, EM
}, PREFIX_OPCODE
},
6906 { "psignd", { MX
, EM
}, PREFIX_OPCODE
},
6907 { "pmulhrsw", { MX
, EM
}, PREFIX_OPCODE
},
6913 { PREFIX_TABLE (PREFIX_0F3810
) },
6917 { PREFIX_TABLE (PREFIX_0F3814
) },
6918 { PREFIX_TABLE (PREFIX_0F3815
) },
6920 { PREFIX_TABLE (PREFIX_0F3817
) },
6926 { "pabsb", { MX
, EM
}, PREFIX_OPCODE
},
6927 { "pabsw", { MX
, EM
}, PREFIX_OPCODE
},
6928 { "pabsd", { MX
, EM
}, PREFIX_OPCODE
},
6931 { PREFIX_TABLE (PREFIX_0F3820
) },
6932 { PREFIX_TABLE (PREFIX_0F3821
) },
6933 { PREFIX_TABLE (PREFIX_0F3822
) },
6934 { PREFIX_TABLE (PREFIX_0F3823
) },
6935 { PREFIX_TABLE (PREFIX_0F3824
) },
6936 { PREFIX_TABLE (PREFIX_0F3825
) },
6940 { PREFIX_TABLE (PREFIX_0F3828
) },
6941 { PREFIX_TABLE (PREFIX_0F3829
) },
6942 { PREFIX_TABLE (PREFIX_0F382A
) },
6943 { PREFIX_TABLE (PREFIX_0F382B
) },
6949 { PREFIX_TABLE (PREFIX_0F3830
) },
6950 { PREFIX_TABLE (PREFIX_0F3831
) },
6951 { PREFIX_TABLE (PREFIX_0F3832
) },
6952 { PREFIX_TABLE (PREFIX_0F3833
) },
6953 { PREFIX_TABLE (PREFIX_0F3834
) },
6954 { PREFIX_TABLE (PREFIX_0F3835
) },
6956 { PREFIX_TABLE (PREFIX_0F3837
) },
6958 { PREFIX_TABLE (PREFIX_0F3838
) },
6959 { PREFIX_TABLE (PREFIX_0F3839
) },
6960 { PREFIX_TABLE (PREFIX_0F383A
) },
6961 { PREFIX_TABLE (PREFIX_0F383B
) },
6962 { PREFIX_TABLE (PREFIX_0F383C
) },
6963 { PREFIX_TABLE (PREFIX_0F383D
) },
6964 { PREFIX_TABLE (PREFIX_0F383E
) },
6965 { PREFIX_TABLE (PREFIX_0F383F
) },
6967 { PREFIX_TABLE (PREFIX_0F3840
) },
6968 { PREFIX_TABLE (PREFIX_0F3841
) },
7039 { PREFIX_TABLE (PREFIX_0F3880
) },
7040 { PREFIX_TABLE (PREFIX_0F3881
) },
7041 { PREFIX_TABLE (PREFIX_0F3882
) },
7120 { PREFIX_TABLE (PREFIX_0F38C8
) },
7121 { PREFIX_TABLE (PREFIX_0F38C9
) },
7122 { PREFIX_TABLE (PREFIX_0F38CA
) },
7123 { PREFIX_TABLE (PREFIX_0F38CB
) },
7124 { PREFIX_TABLE (PREFIX_0F38CC
) },
7125 { PREFIX_TABLE (PREFIX_0F38CD
) },
7141 { PREFIX_TABLE (PREFIX_0F38DB
) },
7142 { PREFIX_TABLE (PREFIX_0F38DC
) },
7143 { PREFIX_TABLE (PREFIX_0F38DD
) },
7144 { PREFIX_TABLE (PREFIX_0F38DE
) },
7145 { PREFIX_TABLE (PREFIX_0F38DF
) },
7165 { PREFIX_TABLE (PREFIX_0F38F0
) },
7166 { PREFIX_TABLE (PREFIX_0F38F1
) },
7171 { PREFIX_TABLE (PREFIX_0F38F6
) },
7183 /* THREE_BYTE_0F3A */
7195 { PREFIX_TABLE (PREFIX_0F3A08
) },
7196 { PREFIX_TABLE (PREFIX_0F3A09
) },
7197 { PREFIX_TABLE (PREFIX_0F3A0A
) },
7198 { PREFIX_TABLE (PREFIX_0F3A0B
) },
7199 { PREFIX_TABLE (PREFIX_0F3A0C
) },
7200 { PREFIX_TABLE (PREFIX_0F3A0D
) },
7201 { PREFIX_TABLE (PREFIX_0F3A0E
) },
7202 { "palignr", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
7208 { PREFIX_TABLE (PREFIX_0F3A14
) },
7209 { PREFIX_TABLE (PREFIX_0F3A15
) },
7210 { PREFIX_TABLE (PREFIX_0F3A16
) },
7211 { PREFIX_TABLE (PREFIX_0F3A17
) },
7222 { PREFIX_TABLE (PREFIX_0F3A20
) },
7223 { PREFIX_TABLE (PREFIX_0F3A21
) },
7224 { PREFIX_TABLE (PREFIX_0F3A22
) },
7258 { PREFIX_TABLE (PREFIX_0F3A40
) },
7259 { PREFIX_TABLE (PREFIX_0F3A41
) },
7260 { PREFIX_TABLE (PREFIX_0F3A42
) },
7262 { PREFIX_TABLE (PREFIX_0F3A44
) },
7294 { PREFIX_TABLE (PREFIX_0F3A60
) },
7295 { PREFIX_TABLE (PREFIX_0F3A61
) },
7296 { PREFIX_TABLE (PREFIX_0F3A62
) },
7297 { PREFIX_TABLE (PREFIX_0F3A63
) },
7415 { PREFIX_TABLE (PREFIX_0F3ACC
) },
7436 { PREFIX_TABLE (PREFIX_0F3ADF
) },
7475 /* THREE_BYTE_0F7A */
7514 { "ptest", { XX
}, PREFIX_OPCODE
},
7551 { "phaddbw", { XM
, EXq
}, PREFIX_OPCODE
},
7552 { "phaddbd", { XM
, EXq
}, PREFIX_OPCODE
},
7553 { "phaddbq", { XM
, EXq
}, PREFIX_OPCODE
},
7556 { "phaddwd", { XM
, EXq
}, PREFIX_OPCODE
},
7557 { "phaddwq", { XM
, EXq
}, PREFIX_OPCODE
},
7562 { "phadddq", { XM
, EXq
}, PREFIX_OPCODE
},
7569 { "phaddubw", { XM
, EXq
}, PREFIX_OPCODE
},
7570 { "phaddubd", { XM
, EXq
}, PREFIX_OPCODE
},
7571 { "phaddubq", { XM
, EXq
}, PREFIX_OPCODE
},
7574 { "phadduwd", { XM
, EXq
}, PREFIX_OPCODE
},
7575 { "phadduwq", { XM
, EXq
}, PREFIX_OPCODE
},
7580 { "phaddudq", { XM
, EXq
}, PREFIX_OPCODE
},
7587 { "phsubbw", { XM
, EXq
}, PREFIX_OPCODE
},
7588 { "phsubbd", { XM
, EXq
}, PREFIX_OPCODE
},
7589 { "phsubbq", { XM
, EXq
}, PREFIX_OPCODE
},
7768 static const struct dis386 xop_table
[][256] = {
7921 { "vpmacssww", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7922 { "vpmacsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7923 { "vpmacssdql", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7931 { "vpmacssdd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7932 { "vpmacssdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7939 { "vpmacsww", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7940 { "vpmacswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7941 { "vpmacsdql", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7949 { "vpmacsdd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7950 { "vpmacsdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7954 { "vpcmov", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7955 { "vpperm", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7958 { "vpmadcsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7976 { "vpmadcswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7988 { "vprotb", { XM
, Vex_2src_1
, Ib
}, 0 },
7989 { "vprotw", { XM
, Vex_2src_1
, Ib
}, 0 },
7990 { "vprotd", { XM
, Vex_2src_1
, Ib
}, 0 },
7991 { "vprotq", { XM
, Vex_2src_1
, Ib
}, 0 },
8001 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC
) },
8002 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD
) },
8003 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE
) },
8004 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF
) },
8037 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC
) },
8038 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED
) },
8039 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE
) },
8040 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF
) },
8064 { REG_TABLE (REG_XOP_TBM_01
) },
8065 { REG_TABLE (REG_XOP_TBM_02
) },
8083 { REG_TABLE (REG_XOP_LWPCB
) },
8207 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80
) },
8208 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81
) },
8209 { "vfrczss", { XM
, EXd
}, 0 },
8210 { "vfrczsd", { XM
, EXq
}, 0 },
8225 { "vprotb", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8226 { "vprotw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8227 { "vprotd", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8228 { "vprotq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8229 { "vpshlb", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8230 { "vpshlw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8231 { "vpshld", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8232 { "vpshlq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8234 { "vpshab", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8235 { "vpshaw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8236 { "vpshad", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8237 { "vpshaq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8280 { "vphaddbw", { XM
, EXxmm
}, 0 },
8281 { "vphaddbd", { XM
, EXxmm
}, 0 },
8282 { "vphaddbq", { XM
, EXxmm
}, 0 },
8285 { "vphaddwd", { XM
, EXxmm
}, 0 },
8286 { "vphaddwq", { XM
, EXxmm
}, 0 },
8291 { "vphadddq", { XM
, EXxmm
}, 0 },
8298 { "vphaddubw", { XM
, EXxmm
}, 0 },
8299 { "vphaddubd", { XM
, EXxmm
}, 0 },
8300 { "vphaddubq", { XM
, EXxmm
}, 0 },
8303 { "vphadduwd", { XM
, EXxmm
}, 0 },
8304 { "vphadduwq", { XM
, EXxmm
}, 0 },
8309 { "vphaddudq", { XM
, EXxmm
}, 0 },
8316 { "vphsubbw", { XM
, EXxmm
}, 0 },
8317 { "vphsubwd", { XM
, EXxmm
}, 0 },
8318 { "vphsubdq", { XM
, EXxmm
}, 0 },
8372 { "bextr", { Gv
, Ev
, Iq
}, 0 },
8374 { REG_TABLE (REG_XOP_LWP
) },
8644 static const struct dis386 vex_table
[][256] = {
8666 { PREFIX_TABLE (PREFIX_VEX_0F10
) },
8667 { PREFIX_TABLE (PREFIX_VEX_0F11
) },
8668 { PREFIX_TABLE (PREFIX_VEX_0F12
) },
8669 { MOD_TABLE (MOD_VEX_0F13
) },
8670 { VEX_W_TABLE (VEX_W_0F14
) },
8671 { VEX_W_TABLE (VEX_W_0F15
) },
8672 { PREFIX_TABLE (PREFIX_VEX_0F16
) },
8673 { MOD_TABLE (MOD_VEX_0F17
) },
8693 { VEX_W_TABLE (VEX_W_0F28
) },
8694 { VEX_W_TABLE (VEX_W_0F29
) },
8695 { PREFIX_TABLE (PREFIX_VEX_0F2A
) },
8696 { MOD_TABLE (MOD_VEX_0F2B
) },
8697 { PREFIX_TABLE (PREFIX_VEX_0F2C
) },
8698 { PREFIX_TABLE (PREFIX_VEX_0F2D
) },
8699 { PREFIX_TABLE (PREFIX_VEX_0F2E
) },
8700 { PREFIX_TABLE (PREFIX_VEX_0F2F
) },
8721 { PREFIX_TABLE (PREFIX_VEX_0F41
) },
8722 { PREFIX_TABLE (PREFIX_VEX_0F42
) },
8724 { PREFIX_TABLE (PREFIX_VEX_0F44
) },
8725 { PREFIX_TABLE (PREFIX_VEX_0F45
) },
8726 { PREFIX_TABLE (PREFIX_VEX_0F46
) },
8727 { PREFIX_TABLE (PREFIX_VEX_0F47
) },
8731 { PREFIX_TABLE (PREFIX_VEX_0F4A
) },
8732 { PREFIX_TABLE (PREFIX_VEX_0F4B
) },
8738 { MOD_TABLE (MOD_VEX_0F50
) },
8739 { PREFIX_TABLE (PREFIX_VEX_0F51
) },
8740 { PREFIX_TABLE (PREFIX_VEX_0F52
) },
8741 { PREFIX_TABLE (PREFIX_VEX_0F53
) },
8742 { "vandpX", { XM
, Vex
, EXx
}, 0 },
8743 { "vandnpX", { XM
, Vex
, EXx
}, 0 },
8744 { "vorpX", { XM
, Vex
, EXx
}, 0 },
8745 { "vxorpX", { XM
, Vex
, EXx
}, 0 },
8747 { PREFIX_TABLE (PREFIX_VEX_0F58
) },
8748 { PREFIX_TABLE (PREFIX_VEX_0F59
) },
8749 { PREFIX_TABLE (PREFIX_VEX_0F5A
) },
8750 { PREFIX_TABLE (PREFIX_VEX_0F5B
) },
8751 { PREFIX_TABLE (PREFIX_VEX_0F5C
) },
8752 { PREFIX_TABLE (PREFIX_VEX_0F5D
) },
8753 { PREFIX_TABLE (PREFIX_VEX_0F5E
) },
8754 { PREFIX_TABLE (PREFIX_VEX_0F5F
) },
8756 { PREFIX_TABLE (PREFIX_VEX_0F60
) },
8757 { PREFIX_TABLE (PREFIX_VEX_0F61
) },
8758 { PREFIX_TABLE (PREFIX_VEX_0F62
) },
8759 { PREFIX_TABLE (PREFIX_VEX_0F63
) },
8760 { PREFIX_TABLE (PREFIX_VEX_0F64
) },
8761 { PREFIX_TABLE (PREFIX_VEX_0F65
) },
8762 { PREFIX_TABLE (PREFIX_VEX_0F66
) },
8763 { PREFIX_TABLE (PREFIX_VEX_0F67
) },
8765 { PREFIX_TABLE (PREFIX_VEX_0F68
) },
8766 { PREFIX_TABLE (PREFIX_VEX_0F69
) },
8767 { PREFIX_TABLE (PREFIX_VEX_0F6A
) },
8768 { PREFIX_TABLE (PREFIX_VEX_0F6B
) },
8769 { PREFIX_TABLE (PREFIX_VEX_0F6C
) },
8770 { PREFIX_TABLE (PREFIX_VEX_0F6D
) },
8771 { PREFIX_TABLE (PREFIX_VEX_0F6E
) },
8772 { PREFIX_TABLE (PREFIX_VEX_0F6F
) },
8774 { PREFIX_TABLE (PREFIX_VEX_0F70
) },
8775 { REG_TABLE (REG_VEX_0F71
) },
8776 { REG_TABLE (REG_VEX_0F72
) },
8777 { REG_TABLE (REG_VEX_0F73
) },
8778 { PREFIX_TABLE (PREFIX_VEX_0F74
) },
8779 { PREFIX_TABLE (PREFIX_VEX_0F75
) },
8780 { PREFIX_TABLE (PREFIX_VEX_0F76
) },
8781 { PREFIX_TABLE (PREFIX_VEX_0F77
) },
8787 { PREFIX_TABLE (PREFIX_VEX_0F7C
) },
8788 { PREFIX_TABLE (PREFIX_VEX_0F7D
) },
8789 { PREFIX_TABLE (PREFIX_VEX_0F7E
) },
8790 { PREFIX_TABLE (PREFIX_VEX_0F7F
) },
8810 { PREFIX_TABLE (PREFIX_VEX_0F90
) },
8811 { PREFIX_TABLE (PREFIX_VEX_0F91
) },
8812 { PREFIX_TABLE (PREFIX_VEX_0F92
) },
8813 { PREFIX_TABLE (PREFIX_VEX_0F93
) },
8819 { PREFIX_TABLE (PREFIX_VEX_0F98
) },
8820 { PREFIX_TABLE (PREFIX_VEX_0F99
) },
8843 { REG_TABLE (REG_VEX_0FAE
) },
8866 { PREFIX_TABLE (PREFIX_VEX_0FC2
) },
8868 { PREFIX_TABLE (PREFIX_VEX_0FC4
) },
8869 { PREFIX_TABLE (PREFIX_VEX_0FC5
) },
8870 { "vshufpX", { XM
, Vex
, EXx
, Ib
}, 0 },
8882 { PREFIX_TABLE (PREFIX_VEX_0FD0
) },
8883 { PREFIX_TABLE (PREFIX_VEX_0FD1
) },
8884 { PREFIX_TABLE (PREFIX_VEX_0FD2
) },
8885 { PREFIX_TABLE (PREFIX_VEX_0FD3
) },
8886 { PREFIX_TABLE (PREFIX_VEX_0FD4
) },
8887 { PREFIX_TABLE (PREFIX_VEX_0FD5
) },
8888 { PREFIX_TABLE (PREFIX_VEX_0FD6
) },
8889 { PREFIX_TABLE (PREFIX_VEX_0FD7
) },
8891 { PREFIX_TABLE (PREFIX_VEX_0FD8
) },
8892 { PREFIX_TABLE (PREFIX_VEX_0FD9
) },
8893 { PREFIX_TABLE (PREFIX_VEX_0FDA
) },
8894 { PREFIX_TABLE (PREFIX_VEX_0FDB
) },
8895 { PREFIX_TABLE (PREFIX_VEX_0FDC
) },
8896 { PREFIX_TABLE (PREFIX_VEX_0FDD
) },
8897 { PREFIX_TABLE (PREFIX_VEX_0FDE
) },
8898 { PREFIX_TABLE (PREFIX_VEX_0FDF
) },
8900 { PREFIX_TABLE (PREFIX_VEX_0FE0
) },
8901 { PREFIX_TABLE (PREFIX_VEX_0FE1
) },
8902 { PREFIX_TABLE (PREFIX_VEX_0FE2
) },
8903 { PREFIX_TABLE (PREFIX_VEX_0FE3
) },
8904 { PREFIX_TABLE (PREFIX_VEX_0FE4
) },
8905 { PREFIX_TABLE (PREFIX_VEX_0FE5
) },
8906 { PREFIX_TABLE (PREFIX_VEX_0FE6
) },
8907 { PREFIX_TABLE (PREFIX_VEX_0FE7
) },
8909 { PREFIX_TABLE (PREFIX_VEX_0FE8
) },
8910 { PREFIX_TABLE (PREFIX_VEX_0FE9
) },
8911 { PREFIX_TABLE (PREFIX_VEX_0FEA
) },
8912 { PREFIX_TABLE (PREFIX_VEX_0FEB
) },
8913 { PREFIX_TABLE (PREFIX_VEX_0FEC
) },
8914 { PREFIX_TABLE (PREFIX_VEX_0FED
) },
8915 { PREFIX_TABLE (PREFIX_VEX_0FEE
) },
8916 { PREFIX_TABLE (PREFIX_VEX_0FEF
) },
8918 { PREFIX_TABLE (PREFIX_VEX_0FF0
) },
8919 { PREFIX_TABLE (PREFIX_VEX_0FF1
) },
8920 { PREFIX_TABLE (PREFIX_VEX_0FF2
) },
8921 { PREFIX_TABLE (PREFIX_VEX_0FF3
) },
8922 { PREFIX_TABLE (PREFIX_VEX_0FF4
) },
8923 { PREFIX_TABLE (PREFIX_VEX_0FF5
) },
8924 { PREFIX_TABLE (PREFIX_VEX_0FF6
) },
8925 { PREFIX_TABLE (PREFIX_VEX_0FF7
) },
8927 { PREFIX_TABLE (PREFIX_VEX_0FF8
) },
8928 { PREFIX_TABLE (PREFIX_VEX_0FF9
) },
8929 { PREFIX_TABLE (PREFIX_VEX_0FFA
) },
8930 { PREFIX_TABLE (PREFIX_VEX_0FFB
) },
8931 { PREFIX_TABLE (PREFIX_VEX_0FFC
) },
8932 { PREFIX_TABLE (PREFIX_VEX_0FFD
) },
8933 { PREFIX_TABLE (PREFIX_VEX_0FFE
) },
8939 { PREFIX_TABLE (PREFIX_VEX_0F3800
) },
8940 { PREFIX_TABLE (PREFIX_VEX_0F3801
) },
8941 { PREFIX_TABLE (PREFIX_VEX_0F3802
) },
8942 { PREFIX_TABLE (PREFIX_VEX_0F3803
) },
8943 { PREFIX_TABLE (PREFIX_VEX_0F3804
) },
8944 { PREFIX_TABLE (PREFIX_VEX_0F3805
) },
8945 { PREFIX_TABLE (PREFIX_VEX_0F3806
) },
8946 { PREFIX_TABLE (PREFIX_VEX_0F3807
) },
8948 { PREFIX_TABLE (PREFIX_VEX_0F3808
) },
8949 { PREFIX_TABLE (PREFIX_VEX_0F3809
) },
8950 { PREFIX_TABLE (PREFIX_VEX_0F380A
) },
8951 { PREFIX_TABLE (PREFIX_VEX_0F380B
) },
8952 { PREFIX_TABLE (PREFIX_VEX_0F380C
) },
8953 { PREFIX_TABLE (PREFIX_VEX_0F380D
) },
8954 { PREFIX_TABLE (PREFIX_VEX_0F380E
) },
8955 { PREFIX_TABLE (PREFIX_VEX_0F380F
) },
8960 { PREFIX_TABLE (PREFIX_VEX_0F3813
) },
8963 { PREFIX_TABLE (PREFIX_VEX_0F3816
) },
8964 { PREFIX_TABLE (PREFIX_VEX_0F3817
) },
8966 { PREFIX_TABLE (PREFIX_VEX_0F3818
) },
8967 { PREFIX_TABLE (PREFIX_VEX_0F3819
) },
8968 { PREFIX_TABLE (PREFIX_VEX_0F381A
) },
8970 { PREFIX_TABLE (PREFIX_VEX_0F381C
) },
8971 { PREFIX_TABLE (PREFIX_VEX_0F381D
) },
8972 { PREFIX_TABLE (PREFIX_VEX_0F381E
) },
8975 { PREFIX_TABLE (PREFIX_VEX_0F3820
) },
8976 { PREFIX_TABLE (PREFIX_VEX_0F3821
) },
8977 { PREFIX_TABLE (PREFIX_VEX_0F3822
) },
8978 { PREFIX_TABLE (PREFIX_VEX_0F3823
) },
8979 { PREFIX_TABLE (PREFIX_VEX_0F3824
) },
8980 { PREFIX_TABLE (PREFIX_VEX_0F3825
) },
8984 { PREFIX_TABLE (PREFIX_VEX_0F3828
) },
8985 { PREFIX_TABLE (PREFIX_VEX_0F3829
) },
8986 { PREFIX_TABLE (PREFIX_VEX_0F382A
) },
8987 { PREFIX_TABLE (PREFIX_VEX_0F382B
) },
8988 { PREFIX_TABLE (PREFIX_VEX_0F382C
) },
8989 { PREFIX_TABLE (PREFIX_VEX_0F382D
) },
8990 { PREFIX_TABLE (PREFIX_VEX_0F382E
) },
8991 { PREFIX_TABLE (PREFIX_VEX_0F382F
) },
8993 { PREFIX_TABLE (PREFIX_VEX_0F3830
) },
8994 { PREFIX_TABLE (PREFIX_VEX_0F3831
) },
8995 { PREFIX_TABLE (PREFIX_VEX_0F3832
) },
8996 { PREFIX_TABLE (PREFIX_VEX_0F3833
) },
8997 { PREFIX_TABLE (PREFIX_VEX_0F3834
) },
8998 { PREFIX_TABLE (PREFIX_VEX_0F3835
) },
8999 { PREFIX_TABLE (PREFIX_VEX_0F3836
) },
9000 { PREFIX_TABLE (PREFIX_VEX_0F3837
) },
9002 { PREFIX_TABLE (PREFIX_VEX_0F3838
) },
9003 { PREFIX_TABLE (PREFIX_VEX_0F3839
) },
9004 { PREFIX_TABLE (PREFIX_VEX_0F383A
) },
9005 { PREFIX_TABLE (PREFIX_VEX_0F383B
) },
9006 { PREFIX_TABLE (PREFIX_VEX_0F383C
) },
9007 { PREFIX_TABLE (PREFIX_VEX_0F383D
) },
9008 { PREFIX_TABLE (PREFIX_VEX_0F383E
) },
9009 { PREFIX_TABLE (PREFIX_VEX_0F383F
) },
9011 { PREFIX_TABLE (PREFIX_VEX_0F3840
) },
9012 { PREFIX_TABLE (PREFIX_VEX_0F3841
) },
9016 { PREFIX_TABLE (PREFIX_VEX_0F3845
) },
9017 { PREFIX_TABLE (PREFIX_VEX_0F3846
) },
9018 { PREFIX_TABLE (PREFIX_VEX_0F3847
) },
9038 { PREFIX_TABLE (PREFIX_VEX_0F3858
) },
9039 { PREFIX_TABLE (PREFIX_VEX_0F3859
) },
9040 { PREFIX_TABLE (PREFIX_VEX_0F385A
) },
9074 { PREFIX_TABLE (PREFIX_VEX_0F3878
) },
9075 { PREFIX_TABLE (PREFIX_VEX_0F3879
) },
9096 { PREFIX_TABLE (PREFIX_VEX_0F388C
) },
9098 { PREFIX_TABLE (PREFIX_VEX_0F388E
) },
9101 { PREFIX_TABLE (PREFIX_VEX_0F3890
) },
9102 { PREFIX_TABLE (PREFIX_VEX_0F3891
) },
9103 { PREFIX_TABLE (PREFIX_VEX_0F3892
) },
9104 { PREFIX_TABLE (PREFIX_VEX_0F3893
) },
9107 { PREFIX_TABLE (PREFIX_VEX_0F3896
) },
9108 { PREFIX_TABLE (PREFIX_VEX_0F3897
) },
9110 { PREFIX_TABLE (PREFIX_VEX_0F3898
) },
9111 { PREFIX_TABLE (PREFIX_VEX_0F3899
) },
9112 { PREFIX_TABLE (PREFIX_VEX_0F389A
) },
9113 { PREFIX_TABLE (PREFIX_VEX_0F389B
) },
9114 { PREFIX_TABLE (PREFIX_VEX_0F389C
) },
9115 { PREFIX_TABLE (PREFIX_VEX_0F389D
) },
9116 { PREFIX_TABLE (PREFIX_VEX_0F389E
) },
9117 { PREFIX_TABLE (PREFIX_VEX_0F389F
) },
9125 { PREFIX_TABLE (PREFIX_VEX_0F38A6
) },
9126 { PREFIX_TABLE (PREFIX_VEX_0F38A7
) },
9128 { PREFIX_TABLE (PREFIX_VEX_0F38A8
) },
9129 { PREFIX_TABLE (PREFIX_VEX_0F38A9
) },
9130 { PREFIX_TABLE (PREFIX_VEX_0F38AA
) },
9131 { PREFIX_TABLE (PREFIX_VEX_0F38AB
) },
9132 { PREFIX_TABLE (PREFIX_VEX_0F38AC
) },
9133 { PREFIX_TABLE (PREFIX_VEX_0F38AD
) },
9134 { PREFIX_TABLE (PREFIX_VEX_0F38AE
) },
9135 { PREFIX_TABLE (PREFIX_VEX_0F38AF
) },
9143 { PREFIX_TABLE (PREFIX_VEX_0F38B6
) },
9144 { PREFIX_TABLE (PREFIX_VEX_0F38B7
) },
9146 { PREFIX_TABLE (PREFIX_VEX_0F38B8
) },
9147 { PREFIX_TABLE (PREFIX_VEX_0F38B9
) },
9148 { PREFIX_TABLE (PREFIX_VEX_0F38BA
) },
9149 { PREFIX_TABLE (PREFIX_VEX_0F38BB
) },
9150 { PREFIX_TABLE (PREFIX_VEX_0F38BC
) },
9151 { PREFIX_TABLE (PREFIX_VEX_0F38BD
) },
9152 { PREFIX_TABLE (PREFIX_VEX_0F38BE
) },
9153 { PREFIX_TABLE (PREFIX_VEX_0F38BF
) },
9185 { PREFIX_TABLE (PREFIX_VEX_0F38DB
) },
9186 { PREFIX_TABLE (PREFIX_VEX_0F38DC
) },
9187 { PREFIX_TABLE (PREFIX_VEX_0F38DD
) },
9188 { PREFIX_TABLE (PREFIX_VEX_0F38DE
) },
9189 { PREFIX_TABLE (PREFIX_VEX_0F38DF
) },
9211 { PREFIX_TABLE (PREFIX_VEX_0F38F2
) },
9212 { REG_TABLE (REG_VEX_0F38F3
) },
9214 { PREFIX_TABLE (PREFIX_VEX_0F38F5
) },
9215 { PREFIX_TABLE (PREFIX_VEX_0F38F6
) },
9216 { PREFIX_TABLE (PREFIX_VEX_0F38F7
) },
9230 { PREFIX_TABLE (PREFIX_VEX_0F3A00
) },
9231 { PREFIX_TABLE (PREFIX_VEX_0F3A01
) },
9232 { PREFIX_TABLE (PREFIX_VEX_0F3A02
) },
9234 { PREFIX_TABLE (PREFIX_VEX_0F3A04
) },
9235 { PREFIX_TABLE (PREFIX_VEX_0F3A05
) },
9236 { PREFIX_TABLE (PREFIX_VEX_0F3A06
) },
9239 { PREFIX_TABLE (PREFIX_VEX_0F3A08
) },
9240 { PREFIX_TABLE (PREFIX_VEX_0F3A09
) },
9241 { PREFIX_TABLE (PREFIX_VEX_0F3A0A
) },
9242 { PREFIX_TABLE (PREFIX_VEX_0F3A0B
) },
9243 { PREFIX_TABLE (PREFIX_VEX_0F3A0C
) },
9244 { PREFIX_TABLE (PREFIX_VEX_0F3A0D
) },
9245 { PREFIX_TABLE (PREFIX_VEX_0F3A0E
) },
9246 { PREFIX_TABLE (PREFIX_VEX_0F3A0F
) },
9252 { PREFIX_TABLE (PREFIX_VEX_0F3A14
) },
9253 { PREFIX_TABLE (PREFIX_VEX_0F3A15
) },
9254 { PREFIX_TABLE (PREFIX_VEX_0F3A16
) },
9255 { PREFIX_TABLE (PREFIX_VEX_0F3A17
) },
9257 { PREFIX_TABLE (PREFIX_VEX_0F3A18
) },
9258 { PREFIX_TABLE (PREFIX_VEX_0F3A19
) },
9262 { PREFIX_TABLE (PREFIX_VEX_0F3A1D
) },
9266 { PREFIX_TABLE (PREFIX_VEX_0F3A20
) },
9267 { PREFIX_TABLE (PREFIX_VEX_0F3A21
) },
9268 { PREFIX_TABLE (PREFIX_VEX_0F3A22
) },
9284 { PREFIX_TABLE (PREFIX_VEX_0F3A30
) },
9285 { PREFIX_TABLE (PREFIX_VEX_0F3A31
) },
9286 { PREFIX_TABLE (PREFIX_VEX_0F3A32
) },
9287 { PREFIX_TABLE (PREFIX_VEX_0F3A33
) },
9293 { PREFIX_TABLE (PREFIX_VEX_0F3A38
) },
9294 { PREFIX_TABLE (PREFIX_VEX_0F3A39
) },
9302 { PREFIX_TABLE (PREFIX_VEX_0F3A40
) },
9303 { PREFIX_TABLE (PREFIX_VEX_0F3A41
) },
9304 { PREFIX_TABLE (PREFIX_VEX_0F3A42
) },
9306 { PREFIX_TABLE (PREFIX_VEX_0F3A44
) },
9308 { PREFIX_TABLE (PREFIX_VEX_0F3A46
) },
9311 { PREFIX_TABLE (PREFIX_VEX_0F3A48
) },
9312 { PREFIX_TABLE (PREFIX_VEX_0F3A49
) },
9313 { PREFIX_TABLE (PREFIX_VEX_0F3A4A
) },
9314 { PREFIX_TABLE (PREFIX_VEX_0F3A4B
) },
9315 { PREFIX_TABLE (PREFIX_VEX_0F3A4C
) },
9333 { PREFIX_TABLE (PREFIX_VEX_0F3A5C
) },
9334 { PREFIX_TABLE (PREFIX_VEX_0F3A5D
) },
9335 { PREFIX_TABLE (PREFIX_VEX_0F3A5E
) },
9336 { PREFIX_TABLE (PREFIX_VEX_0F3A5F
) },
9338 { PREFIX_TABLE (PREFIX_VEX_0F3A60
) },
9339 { PREFIX_TABLE (PREFIX_VEX_0F3A61
) },
9340 { PREFIX_TABLE (PREFIX_VEX_0F3A62
) },
9341 { PREFIX_TABLE (PREFIX_VEX_0F3A63
) },
9347 { PREFIX_TABLE (PREFIX_VEX_0F3A68
) },
9348 { PREFIX_TABLE (PREFIX_VEX_0F3A69
) },
9349 { PREFIX_TABLE (PREFIX_VEX_0F3A6A
) },
9350 { PREFIX_TABLE (PREFIX_VEX_0F3A6B
) },
9351 { PREFIX_TABLE (PREFIX_VEX_0F3A6C
) },
9352 { PREFIX_TABLE (PREFIX_VEX_0F3A6D
) },
9353 { PREFIX_TABLE (PREFIX_VEX_0F3A6E
) },
9354 { PREFIX_TABLE (PREFIX_VEX_0F3A6F
) },
9365 { PREFIX_TABLE (PREFIX_VEX_0F3A78
) },
9366 { PREFIX_TABLE (PREFIX_VEX_0F3A79
) },
9367 { PREFIX_TABLE (PREFIX_VEX_0F3A7A
) },
9368 { PREFIX_TABLE (PREFIX_VEX_0F3A7B
) },
9369 { PREFIX_TABLE (PREFIX_VEX_0F3A7C
) },
9370 { PREFIX_TABLE (PREFIX_VEX_0F3A7D
) },
9371 { PREFIX_TABLE (PREFIX_VEX_0F3A7E
) },
9372 { PREFIX_TABLE (PREFIX_VEX_0F3A7F
) },
9480 { PREFIX_TABLE (PREFIX_VEX_0F3ADF
) },
9500 { PREFIX_TABLE (PREFIX_VEX_0F3AF0
) },
9520 #define NEED_OPCODE_TABLE
9521 #include "i386-dis-evex.h"
9522 #undef NEED_OPCODE_TABLE
9523 static const struct dis386 vex_len_table
[][2] = {
9524 /* VEX_LEN_0F10_P_1 */
9526 { VEX_W_TABLE (VEX_W_0F10_P_1
) },
9527 { VEX_W_TABLE (VEX_W_0F10_P_1
) },
9530 /* VEX_LEN_0F10_P_3 */
9532 { VEX_W_TABLE (VEX_W_0F10_P_3
) },
9533 { VEX_W_TABLE (VEX_W_0F10_P_3
) },
9536 /* VEX_LEN_0F11_P_1 */
9538 { VEX_W_TABLE (VEX_W_0F11_P_1
) },
9539 { VEX_W_TABLE (VEX_W_0F11_P_1
) },
9542 /* VEX_LEN_0F11_P_3 */
9544 { VEX_W_TABLE (VEX_W_0F11_P_3
) },
9545 { VEX_W_TABLE (VEX_W_0F11_P_3
) },
9548 /* VEX_LEN_0F12_P_0_M_0 */
9550 { VEX_W_TABLE (VEX_W_0F12_P_0_M_0
) },
9553 /* VEX_LEN_0F12_P_0_M_1 */
9555 { VEX_W_TABLE (VEX_W_0F12_P_0_M_1
) },
9558 /* VEX_LEN_0F12_P_2 */
9560 { VEX_W_TABLE (VEX_W_0F12_P_2
) },
9563 /* VEX_LEN_0F13_M_0 */
9565 { VEX_W_TABLE (VEX_W_0F13_M_0
) },
9568 /* VEX_LEN_0F16_P_0_M_0 */
9570 { VEX_W_TABLE (VEX_W_0F16_P_0_M_0
) },
9573 /* VEX_LEN_0F16_P_0_M_1 */
9575 { VEX_W_TABLE (VEX_W_0F16_P_0_M_1
) },
9578 /* VEX_LEN_0F16_P_2 */
9580 { VEX_W_TABLE (VEX_W_0F16_P_2
) },
9583 /* VEX_LEN_0F17_M_0 */
9585 { VEX_W_TABLE (VEX_W_0F17_M_0
) },
9588 /* VEX_LEN_0F2A_P_1 */
9590 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9591 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9594 /* VEX_LEN_0F2A_P_3 */
9596 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9597 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9600 /* VEX_LEN_0F2C_P_1 */
9602 { "vcvttss2siY", { Gv
, EXdScalar
}, 0 },
9603 { "vcvttss2siY", { Gv
, EXdScalar
}, 0 },
9606 /* VEX_LEN_0F2C_P_3 */
9608 { "vcvttsd2siY", { Gv
, EXqScalar
}, 0 },
9609 { "vcvttsd2siY", { Gv
, EXqScalar
}, 0 },
9612 /* VEX_LEN_0F2D_P_1 */
9614 { "vcvtss2siY", { Gv
, EXdScalar
}, 0 },
9615 { "vcvtss2siY", { Gv
, EXdScalar
}, 0 },
9618 /* VEX_LEN_0F2D_P_3 */
9620 { "vcvtsd2siY", { Gv
, EXqScalar
}, 0 },
9621 { "vcvtsd2siY", { Gv
, EXqScalar
}, 0 },
9624 /* VEX_LEN_0F2E_P_0 */
9626 { VEX_W_TABLE (VEX_W_0F2E_P_0
) },
9627 { VEX_W_TABLE (VEX_W_0F2E_P_0
) },
9630 /* VEX_LEN_0F2E_P_2 */
9632 { VEX_W_TABLE (VEX_W_0F2E_P_2
) },
9633 { VEX_W_TABLE (VEX_W_0F2E_P_2
) },
9636 /* VEX_LEN_0F2F_P_0 */
9638 { VEX_W_TABLE (VEX_W_0F2F_P_0
) },
9639 { VEX_W_TABLE (VEX_W_0F2F_P_0
) },
9642 /* VEX_LEN_0F2F_P_2 */
9644 { VEX_W_TABLE (VEX_W_0F2F_P_2
) },
9645 { VEX_W_TABLE (VEX_W_0F2F_P_2
) },
9648 /* VEX_LEN_0F41_P_0 */
9651 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1
) },
9653 /* VEX_LEN_0F41_P_2 */
9656 { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1
) },
9658 /* VEX_LEN_0F42_P_0 */
9661 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1
) },
9663 /* VEX_LEN_0F42_P_2 */
9666 { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1
) },
9668 /* VEX_LEN_0F44_P_0 */
9670 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0
) },
9672 /* VEX_LEN_0F44_P_2 */
9674 { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0
) },
9676 /* VEX_LEN_0F45_P_0 */
9679 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1
) },
9681 /* VEX_LEN_0F45_P_2 */
9684 { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1
) },
9686 /* VEX_LEN_0F46_P_0 */
9689 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1
) },
9691 /* VEX_LEN_0F46_P_2 */
9694 { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1
) },
9696 /* VEX_LEN_0F47_P_0 */
9699 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1
) },
9701 /* VEX_LEN_0F47_P_2 */
9704 { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1
) },
9706 /* VEX_LEN_0F4A_P_0 */
9709 { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1
) },
9711 /* VEX_LEN_0F4A_P_2 */
9714 { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1
) },
9716 /* VEX_LEN_0F4B_P_0 */
9719 { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1
) },
9721 /* VEX_LEN_0F4B_P_2 */
9724 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1
) },
9727 /* VEX_LEN_0F51_P_1 */
9729 { VEX_W_TABLE (VEX_W_0F51_P_1
) },
9730 { VEX_W_TABLE (VEX_W_0F51_P_1
) },
9733 /* VEX_LEN_0F51_P_3 */
9735 { VEX_W_TABLE (VEX_W_0F51_P_3
) },
9736 { VEX_W_TABLE (VEX_W_0F51_P_3
) },
9739 /* VEX_LEN_0F52_P_1 */
9741 { VEX_W_TABLE (VEX_W_0F52_P_1
) },
9742 { VEX_W_TABLE (VEX_W_0F52_P_1
) },
9745 /* VEX_LEN_0F53_P_1 */
9747 { VEX_W_TABLE (VEX_W_0F53_P_1
) },
9748 { VEX_W_TABLE (VEX_W_0F53_P_1
) },
9751 /* VEX_LEN_0F58_P_1 */
9753 { VEX_W_TABLE (VEX_W_0F58_P_1
) },
9754 { VEX_W_TABLE (VEX_W_0F58_P_1
) },
9757 /* VEX_LEN_0F58_P_3 */
9759 { VEX_W_TABLE (VEX_W_0F58_P_3
) },
9760 { VEX_W_TABLE (VEX_W_0F58_P_3
) },
9763 /* VEX_LEN_0F59_P_1 */
9765 { VEX_W_TABLE (VEX_W_0F59_P_1
) },
9766 { VEX_W_TABLE (VEX_W_0F59_P_1
) },
9769 /* VEX_LEN_0F59_P_3 */
9771 { VEX_W_TABLE (VEX_W_0F59_P_3
) },
9772 { VEX_W_TABLE (VEX_W_0F59_P_3
) },
9775 /* VEX_LEN_0F5A_P_1 */
9777 { VEX_W_TABLE (VEX_W_0F5A_P_1
) },
9778 { VEX_W_TABLE (VEX_W_0F5A_P_1
) },
9781 /* VEX_LEN_0F5A_P_3 */
9783 { VEX_W_TABLE (VEX_W_0F5A_P_3
) },
9784 { VEX_W_TABLE (VEX_W_0F5A_P_3
) },
9787 /* VEX_LEN_0F5C_P_1 */
9789 { VEX_W_TABLE (VEX_W_0F5C_P_1
) },
9790 { VEX_W_TABLE (VEX_W_0F5C_P_1
) },
9793 /* VEX_LEN_0F5C_P_3 */
9795 { VEX_W_TABLE (VEX_W_0F5C_P_3
) },
9796 { VEX_W_TABLE (VEX_W_0F5C_P_3
) },
9799 /* VEX_LEN_0F5D_P_1 */
9801 { VEX_W_TABLE (VEX_W_0F5D_P_1
) },
9802 { VEX_W_TABLE (VEX_W_0F5D_P_1
) },
9805 /* VEX_LEN_0F5D_P_3 */
9807 { VEX_W_TABLE (VEX_W_0F5D_P_3
) },
9808 { VEX_W_TABLE (VEX_W_0F5D_P_3
) },
9811 /* VEX_LEN_0F5E_P_1 */
9813 { VEX_W_TABLE (VEX_W_0F5E_P_1
) },
9814 { VEX_W_TABLE (VEX_W_0F5E_P_1
) },
9817 /* VEX_LEN_0F5E_P_3 */
9819 { VEX_W_TABLE (VEX_W_0F5E_P_3
) },
9820 { VEX_W_TABLE (VEX_W_0F5E_P_3
) },
9823 /* VEX_LEN_0F5F_P_1 */
9825 { VEX_W_TABLE (VEX_W_0F5F_P_1
) },
9826 { VEX_W_TABLE (VEX_W_0F5F_P_1
) },
9829 /* VEX_LEN_0F5F_P_3 */
9831 { VEX_W_TABLE (VEX_W_0F5F_P_3
) },
9832 { VEX_W_TABLE (VEX_W_0F5F_P_3
) },
9835 /* VEX_LEN_0F6E_P_2 */
9837 { "vmovK", { XMScalar
, Edq
}, 0 },
9838 { "vmovK", { XMScalar
, Edq
}, 0 },
9841 /* VEX_LEN_0F7E_P_1 */
9843 { VEX_W_TABLE (VEX_W_0F7E_P_1
) },
9844 { VEX_W_TABLE (VEX_W_0F7E_P_1
) },
9847 /* VEX_LEN_0F7E_P_2 */
9849 { "vmovK", { Edq
, XMScalar
}, 0 },
9850 { "vmovK", { Edq
, XMScalar
}, 0 },
9853 /* VEX_LEN_0F90_P_0 */
9855 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0
) },
9858 /* VEX_LEN_0F90_P_2 */
9860 { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0
) },
9863 /* VEX_LEN_0F91_P_0 */
9865 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0
) },
9868 /* VEX_LEN_0F91_P_2 */
9870 { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0
) },
9873 /* VEX_LEN_0F92_P_0 */
9875 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0
) },
9878 /* VEX_LEN_0F92_P_2 */
9880 { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0
) },
9883 /* VEX_LEN_0F92_P_3 */
9885 { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0
) },
9888 /* VEX_LEN_0F93_P_0 */
9890 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0
) },
9893 /* VEX_LEN_0F93_P_2 */
9895 { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0
) },
9898 /* VEX_LEN_0F93_P_3 */
9900 { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0
) },
9903 /* VEX_LEN_0F98_P_0 */
9905 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0
) },
9908 /* VEX_LEN_0F98_P_2 */
9910 { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0
) },
9913 /* VEX_LEN_0F99_P_0 */
9915 { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0
) },
9918 /* VEX_LEN_0F99_P_2 */
9920 { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0
) },
9923 /* VEX_LEN_0FAE_R_2_M_0 */
9925 { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0
) },
9928 /* VEX_LEN_0FAE_R_3_M_0 */
9930 { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0
) },
9933 /* VEX_LEN_0FC2_P_1 */
9935 { VEX_W_TABLE (VEX_W_0FC2_P_1
) },
9936 { VEX_W_TABLE (VEX_W_0FC2_P_1
) },
9939 /* VEX_LEN_0FC2_P_3 */
9941 { VEX_W_TABLE (VEX_W_0FC2_P_3
) },
9942 { VEX_W_TABLE (VEX_W_0FC2_P_3
) },
9945 /* VEX_LEN_0FC4_P_2 */
9947 { VEX_W_TABLE (VEX_W_0FC4_P_2
) },
9950 /* VEX_LEN_0FC5_P_2 */
9952 { VEX_W_TABLE (VEX_W_0FC5_P_2
) },
9955 /* VEX_LEN_0FD6_P_2 */
9957 { VEX_W_TABLE (VEX_W_0FD6_P_2
) },
9958 { VEX_W_TABLE (VEX_W_0FD6_P_2
) },
9961 /* VEX_LEN_0FF7_P_2 */
9963 { VEX_W_TABLE (VEX_W_0FF7_P_2
) },
9966 /* VEX_LEN_0F3816_P_2 */
9969 { VEX_W_TABLE (VEX_W_0F3816_P_2
) },
9972 /* VEX_LEN_0F3819_P_2 */
9975 { VEX_W_TABLE (VEX_W_0F3819_P_2
) },
9978 /* VEX_LEN_0F381A_P_2_M_0 */
9981 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0
) },
9984 /* VEX_LEN_0F3836_P_2 */
9987 { VEX_W_TABLE (VEX_W_0F3836_P_2
) },
9990 /* VEX_LEN_0F3841_P_2 */
9992 { VEX_W_TABLE (VEX_W_0F3841_P_2
) },
9995 /* VEX_LEN_0F385A_P_2_M_0 */
9998 { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0
) },
10001 /* VEX_LEN_0F38DB_P_2 */
10003 { VEX_W_TABLE (VEX_W_0F38DB_P_2
) },
10006 /* VEX_LEN_0F38DC_P_2 */
10008 { VEX_W_TABLE (VEX_W_0F38DC_P_2
) },
10011 /* VEX_LEN_0F38DD_P_2 */
10013 { VEX_W_TABLE (VEX_W_0F38DD_P_2
) },
10016 /* VEX_LEN_0F38DE_P_2 */
10018 { VEX_W_TABLE (VEX_W_0F38DE_P_2
) },
10021 /* VEX_LEN_0F38DF_P_2 */
10023 { VEX_W_TABLE (VEX_W_0F38DF_P_2
) },
10026 /* VEX_LEN_0F38F2_P_0 */
10028 { "andnS", { Gdq
, VexGdq
, Edq
}, 0 },
10031 /* VEX_LEN_0F38F3_R_1_P_0 */
10033 { "blsrS", { VexGdq
, Edq
}, 0 },
10036 /* VEX_LEN_0F38F3_R_2_P_0 */
10038 { "blsmskS", { VexGdq
, Edq
}, 0 },
10041 /* VEX_LEN_0F38F3_R_3_P_0 */
10043 { "blsiS", { VexGdq
, Edq
}, 0 },
10046 /* VEX_LEN_0F38F5_P_0 */
10048 { "bzhiS", { Gdq
, Edq
, VexGdq
}, 0 },
10051 /* VEX_LEN_0F38F5_P_1 */
10053 { "pextS", { Gdq
, VexGdq
, Edq
}, 0 },
10056 /* VEX_LEN_0F38F5_P_3 */
10058 { "pdepS", { Gdq
, VexGdq
, Edq
}, 0 },
10061 /* VEX_LEN_0F38F6_P_3 */
10063 { "mulxS", { Gdq
, VexGdq
, Edq
}, 0 },
10066 /* VEX_LEN_0F38F7_P_0 */
10068 { "bextrS", { Gdq
, Edq
, VexGdq
}, 0 },
10071 /* VEX_LEN_0F38F7_P_1 */
10073 { "sarxS", { Gdq
, Edq
, VexGdq
}, 0 },
10076 /* VEX_LEN_0F38F7_P_2 */
10078 { "shlxS", { Gdq
, Edq
, VexGdq
}, 0 },
10081 /* VEX_LEN_0F38F7_P_3 */
10083 { "shrxS", { Gdq
, Edq
, VexGdq
}, 0 },
10086 /* VEX_LEN_0F3A00_P_2 */
10089 { VEX_W_TABLE (VEX_W_0F3A00_P_2
) },
10092 /* VEX_LEN_0F3A01_P_2 */
10095 { VEX_W_TABLE (VEX_W_0F3A01_P_2
) },
10098 /* VEX_LEN_0F3A06_P_2 */
10101 { VEX_W_TABLE (VEX_W_0F3A06_P_2
) },
10104 /* VEX_LEN_0F3A0A_P_2 */
10106 { VEX_W_TABLE (VEX_W_0F3A0A_P_2
) },
10107 { VEX_W_TABLE (VEX_W_0F3A0A_P_2
) },
10110 /* VEX_LEN_0F3A0B_P_2 */
10112 { VEX_W_TABLE (VEX_W_0F3A0B_P_2
) },
10113 { VEX_W_TABLE (VEX_W_0F3A0B_P_2
) },
10116 /* VEX_LEN_0F3A14_P_2 */
10118 { VEX_W_TABLE (VEX_W_0F3A14_P_2
) },
10121 /* VEX_LEN_0F3A15_P_2 */
10123 { VEX_W_TABLE (VEX_W_0F3A15_P_2
) },
10126 /* VEX_LEN_0F3A16_P_2 */
10128 { "vpextrK", { Edq
, XM
, Ib
}, 0 },
10131 /* VEX_LEN_0F3A17_P_2 */
10133 { "vextractps", { Edqd
, XM
, Ib
}, 0 },
10136 /* VEX_LEN_0F3A18_P_2 */
10139 { VEX_W_TABLE (VEX_W_0F3A18_P_2
) },
10142 /* VEX_LEN_0F3A19_P_2 */
10145 { VEX_W_TABLE (VEX_W_0F3A19_P_2
) },
10148 /* VEX_LEN_0F3A20_P_2 */
10150 { VEX_W_TABLE (VEX_W_0F3A20_P_2
) },
10153 /* VEX_LEN_0F3A21_P_2 */
10155 { VEX_W_TABLE (VEX_W_0F3A21_P_2
) },
10158 /* VEX_LEN_0F3A22_P_2 */
10160 { "vpinsrK", { XM
, Vex128
, Edq
, Ib
}, 0 },
10163 /* VEX_LEN_0F3A30_P_2 */
10165 { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0
) },
10168 /* VEX_LEN_0F3A31_P_2 */
10170 { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0
) },
10173 /* VEX_LEN_0F3A32_P_2 */
10175 { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0
) },
10178 /* VEX_LEN_0F3A33_P_2 */
10180 { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0
) },
10183 /* VEX_LEN_0F3A38_P_2 */
10186 { VEX_W_TABLE (VEX_W_0F3A38_P_2
) },
10189 /* VEX_LEN_0F3A39_P_2 */
10192 { VEX_W_TABLE (VEX_W_0F3A39_P_2
) },
10195 /* VEX_LEN_0F3A41_P_2 */
10197 { VEX_W_TABLE (VEX_W_0F3A41_P_2
) },
10200 /* VEX_LEN_0F3A44_P_2 */
10202 { VEX_W_TABLE (VEX_W_0F3A44_P_2
) },
10205 /* VEX_LEN_0F3A46_P_2 */
10208 { VEX_W_TABLE (VEX_W_0F3A46_P_2
) },
10211 /* VEX_LEN_0F3A60_P_2 */
10213 { VEX_W_TABLE (VEX_W_0F3A60_P_2
) },
10216 /* VEX_LEN_0F3A61_P_2 */
10218 { VEX_W_TABLE (VEX_W_0F3A61_P_2
) },
10221 /* VEX_LEN_0F3A62_P_2 */
10223 { VEX_W_TABLE (VEX_W_0F3A62_P_2
) },
10226 /* VEX_LEN_0F3A63_P_2 */
10228 { VEX_W_TABLE (VEX_W_0F3A63_P_2
) },
10231 /* VEX_LEN_0F3A6A_P_2 */
10233 { "vfmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
}, 0 },
10236 /* VEX_LEN_0F3A6B_P_2 */
10238 { "vfmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
}, 0 },
10241 /* VEX_LEN_0F3A6E_P_2 */
10243 { "vfmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
}, 0 },
10246 /* VEX_LEN_0F3A6F_P_2 */
10248 { "vfmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
}, 0 },
10251 /* VEX_LEN_0F3A7A_P_2 */
10253 { "vfnmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
}, 0 },
10256 /* VEX_LEN_0F3A7B_P_2 */
10258 { "vfnmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
}, 0 },
10261 /* VEX_LEN_0F3A7E_P_2 */
10263 { "vfnmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
}, 0 },
10266 /* VEX_LEN_0F3A7F_P_2 */
10268 { "vfnmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
}, 0 },
10271 /* VEX_LEN_0F3ADF_P_2 */
10273 { VEX_W_TABLE (VEX_W_0F3ADF_P_2
) },
10276 /* VEX_LEN_0F3AF0_P_3 */
10278 { "rorxS", { Gdq
, Edq
, Ib
}, 0 },
10281 /* VEX_LEN_0FXOP_08_CC */
10283 { "vpcomb", { XM
, Vex128
, EXx
, Ib
}, 0 },
10286 /* VEX_LEN_0FXOP_08_CD */
10288 { "vpcomw", { XM
, Vex128
, EXx
, Ib
}, 0 },
10291 /* VEX_LEN_0FXOP_08_CE */
10293 { "vpcomd", { XM
, Vex128
, EXx
, Ib
}, 0 },
10296 /* VEX_LEN_0FXOP_08_CF */
10298 { "vpcomq", { XM
, Vex128
, EXx
, Ib
}, 0 },
10301 /* VEX_LEN_0FXOP_08_EC */
10303 { "vpcomub", { XM
, Vex128
, EXx
, Ib
}, 0 },
10306 /* VEX_LEN_0FXOP_08_ED */
10308 { "vpcomuw", { XM
, Vex128
, EXx
, Ib
}, 0 },
10311 /* VEX_LEN_0FXOP_08_EE */
10313 { "vpcomud", { XM
, Vex128
, EXx
, Ib
}, 0 },
10316 /* VEX_LEN_0FXOP_08_EF */
10318 { "vpcomuq", { XM
, Vex128
, EXx
, Ib
}, 0 },
10321 /* VEX_LEN_0FXOP_09_80 */
10323 { "vfrczps", { XM
, EXxmm
}, 0 },
10324 { "vfrczps", { XM
, EXymmq
}, 0 },
10327 /* VEX_LEN_0FXOP_09_81 */
10329 { "vfrczpd", { XM
, EXxmm
}, 0 },
10330 { "vfrczpd", { XM
, EXymmq
}, 0 },
10334 static const struct dis386 vex_w_table
[][2] = {
10336 /* VEX_W_0F10_P_0 */
10337 { "vmovups", { XM
, EXx
}, 0 },
10340 /* VEX_W_0F10_P_1 */
10341 { "vmovss", { XMVexScalar
, VexScalar
, EXdScalar
}, 0 },
10344 /* VEX_W_0F10_P_2 */
10345 { "vmovupd", { XM
, EXx
}, 0 },
10348 /* VEX_W_0F10_P_3 */
10349 { "vmovsd", { XMVexScalar
, VexScalar
, EXqScalar
}, 0 },
10352 /* VEX_W_0F11_P_0 */
10353 { "vmovups", { EXxS
, XM
}, 0 },
10356 /* VEX_W_0F11_P_1 */
10357 { "vmovss", { EXdVexScalarS
, VexScalar
, XMScalar
}, 0 },
10360 /* VEX_W_0F11_P_2 */
10361 { "vmovupd", { EXxS
, XM
}, 0 },
10364 /* VEX_W_0F11_P_3 */
10365 { "vmovsd", { EXqVexScalarS
, VexScalar
, XMScalar
}, 0 },
10368 /* VEX_W_0F12_P_0_M_0 */
10369 { "vmovlps", { XM
, Vex128
, EXq
}, 0 },
10372 /* VEX_W_0F12_P_0_M_1 */
10373 { "vmovhlps", { XM
, Vex128
, EXq
}, 0 },
10376 /* VEX_W_0F12_P_1 */
10377 { "vmovsldup", { XM
, EXx
}, 0 },
10380 /* VEX_W_0F12_P_2 */
10381 { "vmovlpd", { XM
, Vex128
, EXq
}, 0 },
10384 /* VEX_W_0F12_P_3 */
10385 { "vmovddup", { XM
, EXymmq
}, 0 },
10388 /* VEX_W_0F13_M_0 */
10389 { "vmovlpX", { EXq
, XM
}, 0 },
10393 { "vunpcklpX", { XM
, Vex
, EXx
}, 0 },
10397 { "vunpckhpX", { XM
, Vex
, EXx
}, 0 },
10400 /* VEX_W_0F16_P_0_M_0 */
10401 { "vmovhps", { XM
, Vex128
, EXq
}, 0 },
10404 /* VEX_W_0F16_P_0_M_1 */
10405 { "vmovlhps", { XM
, Vex128
, EXq
}, 0 },
10408 /* VEX_W_0F16_P_1 */
10409 { "vmovshdup", { XM
, EXx
}, 0 },
10412 /* VEX_W_0F16_P_2 */
10413 { "vmovhpd", { XM
, Vex128
, EXq
}, 0 },
10416 /* VEX_W_0F17_M_0 */
10417 { "vmovhpX", { EXq
, XM
}, 0 },
10421 { "vmovapX", { XM
, EXx
}, 0 },
10425 { "vmovapX", { EXxS
, XM
}, 0 },
10428 /* VEX_W_0F2B_M_0 */
10429 { "vmovntpX", { Mx
, XM
}, 0 },
10432 /* VEX_W_0F2E_P_0 */
10433 { "vucomiss", { XMScalar
, EXdScalar
}, 0 },
10436 /* VEX_W_0F2E_P_2 */
10437 { "vucomisd", { XMScalar
, EXqScalar
}, 0 },
10440 /* VEX_W_0F2F_P_0 */
10441 { "vcomiss", { XMScalar
, EXdScalar
}, 0 },
10444 /* VEX_W_0F2F_P_2 */
10445 { "vcomisd", { XMScalar
, EXqScalar
}, 0 },
10448 /* VEX_W_0F41_P_0_LEN_1 */
10449 { "kandw", { MaskG
, MaskVex
, MaskR
}, 0 },
10450 { "kandq", { MaskG
, MaskVex
, MaskR
}, 0 },
10453 /* VEX_W_0F41_P_2_LEN_1 */
10454 { "kandb", { MaskG
, MaskVex
, MaskR
}, 0 },
10455 { "kandd", { MaskG
, MaskVex
, MaskR
}, 0 },
10458 /* VEX_W_0F42_P_0_LEN_1 */
10459 { "kandnw", { MaskG
, MaskVex
, MaskR
}, 0 },
10460 { "kandnq", { MaskG
, MaskVex
, MaskR
}, 0 },
10463 /* VEX_W_0F42_P_2_LEN_1 */
10464 { "kandnb", { MaskG
, MaskVex
, MaskR
}, 0 },
10465 { "kandnd", { MaskG
, MaskVex
, MaskR
}, 0 },
10468 /* VEX_W_0F44_P_0_LEN_0 */
10469 { "knotw", { MaskG
, MaskR
}, 0 },
10470 { "knotq", { MaskG
, MaskR
}, 0 },
10473 /* VEX_W_0F44_P_2_LEN_0 */
10474 { "knotb", { MaskG
, MaskR
}, 0 },
10475 { "knotd", { MaskG
, MaskR
}, 0 },
10478 /* VEX_W_0F45_P_0_LEN_1 */
10479 { "korw", { MaskG
, MaskVex
, MaskR
}, 0 },
10480 { "korq", { MaskG
, MaskVex
, MaskR
}, 0 },
10483 /* VEX_W_0F45_P_2_LEN_1 */
10484 { "korb", { MaskG
, MaskVex
, MaskR
}, 0 },
10485 { "kord", { MaskG
, MaskVex
, MaskR
}, 0 },
10488 /* VEX_W_0F46_P_0_LEN_1 */
10489 { "kxnorw", { MaskG
, MaskVex
, MaskR
}, 0 },
10490 { "kxnorq", { MaskG
, MaskVex
, MaskR
}, 0 },
10493 /* VEX_W_0F46_P_2_LEN_1 */
10494 { "kxnorb", { MaskG
, MaskVex
, MaskR
}, 0 },
10495 { "kxnord", { MaskG
, MaskVex
, MaskR
}, 0 },
10498 /* VEX_W_0F47_P_0_LEN_1 */
10499 { "kxorw", { MaskG
, MaskVex
, MaskR
}, 0 },
10500 { "kxorq", { MaskG
, MaskVex
, MaskR
}, 0 },
10503 /* VEX_W_0F47_P_2_LEN_1 */
10504 { "kxorb", { MaskG
, MaskVex
, MaskR
}, 0 },
10505 { "kxord", { MaskG
, MaskVex
, MaskR
}, 0 },
10508 /* VEX_W_0F4A_P_0_LEN_1 */
10509 { "kaddw", { MaskG
, MaskVex
, MaskR
}, 0 },
10510 { "kaddq", { MaskG
, MaskVex
, MaskR
}, 0 },
10513 /* VEX_W_0F4A_P_2_LEN_1 */
10514 { "kaddb", { MaskG
, MaskVex
, MaskR
}, 0 },
10515 { "kaddd", { MaskG
, MaskVex
, MaskR
}, 0 },
10518 /* VEX_W_0F4B_P_0_LEN_1 */
10519 { "kunpckwd", { MaskG
, MaskVex
, MaskR
}, 0 },
10520 { "kunpckdq", { MaskG
, MaskVex
, MaskR
}, 0 },
10523 /* VEX_W_0F4B_P_2_LEN_1 */
10524 { "kunpckbw", { MaskG
, MaskVex
, MaskR
}, 0 },
10527 /* VEX_W_0F50_M_0 */
10528 { "vmovmskpX", { Gdq
, XS
}, 0 },
10531 /* VEX_W_0F51_P_0 */
10532 { "vsqrtps", { XM
, EXx
}, 0 },
10535 /* VEX_W_0F51_P_1 */
10536 { "vsqrtss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10539 /* VEX_W_0F51_P_2 */
10540 { "vsqrtpd", { XM
, EXx
}, 0 },
10543 /* VEX_W_0F51_P_3 */
10544 { "vsqrtsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10547 /* VEX_W_0F52_P_0 */
10548 { "vrsqrtps", { XM
, EXx
}, 0 },
10551 /* VEX_W_0F52_P_1 */
10552 { "vrsqrtss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10555 /* VEX_W_0F53_P_0 */
10556 { "vrcpps", { XM
, EXx
}, 0 },
10559 /* VEX_W_0F53_P_1 */
10560 { "vrcpss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10563 /* VEX_W_0F58_P_0 */
10564 { "vaddps", { XM
, Vex
, EXx
}, 0 },
10567 /* VEX_W_0F58_P_1 */
10568 { "vaddss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10571 /* VEX_W_0F58_P_2 */
10572 { "vaddpd", { XM
, Vex
, EXx
}, 0 },
10575 /* VEX_W_0F58_P_3 */
10576 { "vaddsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10579 /* VEX_W_0F59_P_0 */
10580 { "vmulps", { XM
, Vex
, EXx
}, 0 },
10583 /* VEX_W_0F59_P_1 */
10584 { "vmulss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10587 /* VEX_W_0F59_P_2 */
10588 { "vmulpd", { XM
, Vex
, EXx
}, 0 },
10591 /* VEX_W_0F59_P_3 */
10592 { "vmulsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10595 /* VEX_W_0F5A_P_0 */
10596 { "vcvtps2pd", { XM
, EXxmmq
}, 0 },
10599 /* VEX_W_0F5A_P_1 */
10600 { "vcvtss2sd", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10603 /* VEX_W_0F5A_P_3 */
10604 { "vcvtsd2ss", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10607 /* VEX_W_0F5B_P_0 */
10608 { "vcvtdq2ps", { XM
, EXx
}, 0 },
10611 /* VEX_W_0F5B_P_1 */
10612 { "vcvttps2dq", { XM
, EXx
}, 0 },
10615 /* VEX_W_0F5B_P_2 */
10616 { "vcvtps2dq", { XM
, EXx
}, 0 },
10619 /* VEX_W_0F5C_P_0 */
10620 { "vsubps", { XM
, Vex
, EXx
}, 0 },
10623 /* VEX_W_0F5C_P_1 */
10624 { "vsubss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10627 /* VEX_W_0F5C_P_2 */
10628 { "vsubpd", { XM
, Vex
, EXx
}, 0 },
10631 /* VEX_W_0F5C_P_3 */
10632 { "vsubsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10635 /* VEX_W_0F5D_P_0 */
10636 { "vminps", { XM
, Vex
, EXx
}, 0 },
10639 /* VEX_W_0F5D_P_1 */
10640 { "vminss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10643 /* VEX_W_0F5D_P_2 */
10644 { "vminpd", { XM
, Vex
, EXx
}, 0 },
10647 /* VEX_W_0F5D_P_3 */
10648 { "vminsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10651 /* VEX_W_0F5E_P_0 */
10652 { "vdivps", { XM
, Vex
, EXx
}, 0 },
10655 /* VEX_W_0F5E_P_1 */
10656 { "vdivss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10659 /* VEX_W_0F5E_P_2 */
10660 { "vdivpd", { XM
, Vex
, EXx
}, 0 },
10663 /* VEX_W_0F5E_P_3 */
10664 { "vdivsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10667 /* VEX_W_0F5F_P_0 */
10668 { "vmaxps", { XM
, Vex
, EXx
}, 0 },
10671 /* VEX_W_0F5F_P_1 */
10672 { "vmaxss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10675 /* VEX_W_0F5F_P_2 */
10676 { "vmaxpd", { XM
, Vex
, EXx
}, 0 },
10679 /* VEX_W_0F5F_P_3 */
10680 { "vmaxsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10683 /* VEX_W_0F60_P_2 */
10684 { "vpunpcklbw", { XM
, Vex
, EXx
}, 0 },
10687 /* VEX_W_0F61_P_2 */
10688 { "vpunpcklwd", { XM
, Vex
, EXx
}, 0 },
10691 /* VEX_W_0F62_P_2 */
10692 { "vpunpckldq", { XM
, Vex
, EXx
}, 0 },
10695 /* VEX_W_0F63_P_2 */
10696 { "vpacksswb", { XM
, Vex
, EXx
}, 0 },
10699 /* VEX_W_0F64_P_2 */
10700 { "vpcmpgtb", { XM
, Vex
, EXx
}, 0 },
10703 /* VEX_W_0F65_P_2 */
10704 { "vpcmpgtw", { XM
, Vex
, EXx
}, 0 },
10707 /* VEX_W_0F66_P_2 */
10708 { "vpcmpgtd", { XM
, Vex
, EXx
}, 0 },
10711 /* VEX_W_0F67_P_2 */
10712 { "vpackuswb", { XM
, Vex
, EXx
}, 0 },
10715 /* VEX_W_0F68_P_2 */
10716 { "vpunpckhbw", { XM
, Vex
, EXx
}, 0 },
10719 /* VEX_W_0F69_P_2 */
10720 { "vpunpckhwd", { XM
, Vex
, EXx
}, 0 },
10723 /* VEX_W_0F6A_P_2 */
10724 { "vpunpckhdq", { XM
, Vex
, EXx
}, 0 },
10727 /* VEX_W_0F6B_P_2 */
10728 { "vpackssdw", { XM
, Vex
, EXx
}, 0 },
10731 /* VEX_W_0F6C_P_2 */
10732 { "vpunpcklqdq", { XM
, Vex
, EXx
}, 0 },
10735 /* VEX_W_0F6D_P_2 */
10736 { "vpunpckhqdq", { XM
, Vex
, EXx
}, 0 },
10739 /* VEX_W_0F6F_P_1 */
10740 { "vmovdqu", { XM
, EXx
}, 0 },
10743 /* VEX_W_0F6F_P_2 */
10744 { "vmovdqa", { XM
, EXx
}, 0 },
10747 /* VEX_W_0F70_P_1 */
10748 { "vpshufhw", { XM
, EXx
, Ib
}, 0 },
10751 /* VEX_W_0F70_P_2 */
10752 { "vpshufd", { XM
, EXx
, Ib
}, 0 },
10755 /* VEX_W_0F70_P_3 */
10756 { "vpshuflw", { XM
, EXx
, Ib
}, 0 },
10759 /* VEX_W_0F71_R_2_P_2 */
10760 { "vpsrlw", { Vex
, XS
, Ib
}, 0 },
10763 /* VEX_W_0F71_R_4_P_2 */
10764 { "vpsraw", { Vex
, XS
, Ib
}, 0 },
10767 /* VEX_W_0F71_R_6_P_2 */
10768 { "vpsllw", { Vex
, XS
, Ib
}, 0 },
10771 /* VEX_W_0F72_R_2_P_2 */
10772 { "vpsrld", { Vex
, XS
, Ib
}, 0 },
10775 /* VEX_W_0F72_R_4_P_2 */
10776 { "vpsrad", { Vex
, XS
, Ib
}, 0 },
10779 /* VEX_W_0F72_R_6_P_2 */
10780 { "vpslld", { Vex
, XS
, Ib
}, 0 },
10783 /* VEX_W_0F73_R_2_P_2 */
10784 { "vpsrlq", { Vex
, XS
, Ib
}, 0 },
10787 /* VEX_W_0F73_R_3_P_2 */
10788 { "vpsrldq", { Vex
, XS
, Ib
}, 0 },
10791 /* VEX_W_0F73_R_6_P_2 */
10792 { "vpsllq", { Vex
, XS
, Ib
}, 0 },
10795 /* VEX_W_0F73_R_7_P_2 */
10796 { "vpslldq", { Vex
, XS
, Ib
}, 0 },
10799 /* VEX_W_0F74_P_2 */
10800 { "vpcmpeqb", { XM
, Vex
, EXx
}, 0 },
10803 /* VEX_W_0F75_P_2 */
10804 { "vpcmpeqw", { XM
, Vex
, EXx
}, 0 },
10807 /* VEX_W_0F76_P_2 */
10808 { "vpcmpeqd", { XM
, Vex
, EXx
}, 0 },
10811 /* VEX_W_0F77_P_0 */
10812 { "", { VZERO
}, 0 },
10815 /* VEX_W_0F7C_P_2 */
10816 { "vhaddpd", { XM
, Vex
, EXx
}, 0 },
10819 /* VEX_W_0F7C_P_3 */
10820 { "vhaddps", { XM
, Vex
, EXx
}, 0 },
10823 /* VEX_W_0F7D_P_2 */
10824 { "vhsubpd", { XM
, Vex
, EXx
}, 0 },
10827 /* VEX_W_0F7D_P_3 */
10828 { "vhsubps", { XM
, Vex
, EXx
}, 0 },
10831 /* VEX_W_0F7E_P_1 */
10832 { "vmovq", { XMScalar
, EXqScalar
}, 0 },
10835 /* VEX_W_0F7F_P_1 */
10836 { "vmovdqu", { EXxS
, XM
}, 0 },
10839 /* VEX_W_0F7F_P_2 */
10840 { "vmovdqa", { EXxS
, XM
}, 0 },
10843 /* VEX_W_0F90_P_0_LEN_0 */
10844 { "kmovw", { MaskG
, MaskE
}, 0 },
10845 { "kmovq", { MaskG
, MaskE
}, 0 },
10848 /* VEX_W_0F90_P_2_LEN_0 */
10849 { "kmovb", { MaskG
, MaskBDE
}, 0 },
10850 { "kmovd", { MaskG
, MaskBDE
}, 0 },
10853 /* VEX_W_0F91_P_0_LEN_0 */
10854 { "kmovw", { Ew
, MaskG
}, 0 },
10855 { "kmovq", { Eq
, MaskG
}, 0 },
10858 /* VEX_W_0F91_P_2_LEN_0 */
10859 { "kmovb", { Eb
, MaskG
}, 0 },
10860 { "kmovd", { Ed
, MaskG
}, 0 },
10863 /* VEX_W_0F92_P_0_LEN_0 */
10864 { "kmovw", { MaskG
, Rdq
}, 0 },
10867 /* VEX_W_0F92_P_2_LEN_0 */
10868 { "kmovb", { MaskG
, Rdq
}, 0 },
10871 /* VEX_W_0F92_P_3_LEN_0 */
10872 { "kmovd", { MaskG
, Rdq
}, 0 },
10873 { "kmovq", { MaskG
, Rdq
}, 0 },
10876 /* VEX_W_0F93_P_0_LEN_0 */
10877 { "kmovw", { Gdq
, MaskR
}, 0 },
10880 /* VEX_W_0F93_P_2_LEN_0 */
10881 { "kmovb", { Gdq
, MaskR
}, 0 },
10884 /* VEX_W_0F93_P_3_LEN_0 */
10885 { "kmovd", { Gdq
, MaskR
}, 0 },
10886 { "kmovq", { Gdq
, MaskR
}, 0 },
10889 /* VEX_W_0F98_P_0_LEN_0 */
10890 { "kortestw", { MaskG
, MaskR
}, 0 },
10891 { "kortestq", { MaskG
, MaskR
}, 0 },
10894 /* VEX_W_0F98_P_2_LEN_0 */
10895 { "kortestb", { MaskG
, MaskR
}, 0 },
10896 { "kortestd", { MaskG
, MaskR
}, 0 },
10899 /* VEX_W_0F99_P_0_LEN_0 */
10900 { "ktestw", { MaskG
, MaskR
}, 0 },
10901 { "ktestq", { MaskG
, MaskR
}, 0 },
10904 /* VEX_W_0F99_P_2_LEN_0 */
10905 { "ktestb", { MaskG
, MaskR
}, 0 },
10906 { "ktestd", { MaskG
, MaskR
}, 0 },
10909 /* VEX_W_0FAE_R_2_M_0 */
10910 { "vldmxcsr", { Md
}, 0 },
10913 /* VEX_W_0FAE_R_3_M_0 */
10914 { "vstmxcsr", { Md
}, 0 },
10917 /* VEX_W_0FC2_P_0 */
10918 { "vcmpps", { XM
, Vex
, EXx
, VCMP
}, 0 },
10921 /* VEX_W_0FC2_P_1 */
10922 { "vcmpss", { XMScalar
, VexScalar
, EXdScalar
, VCMP
}, 0 },
10925 /* VEX_W_0FC2_P_2 */
10926 { "vcmppd", { XM
, Vex
, EXx
, VCMP
}, 0 },
10929 /* VEX_W_0FC2_P_3 */
10930 { "vcmpsd", { XMScalar
, VexScalar
, EXqScalar
, VCMP
}, 0 },
10933 /* VEX_W_0FC4_P_2 */
10934 { "vpinsrw", { XM
, Vex128
, Edqw
, Ib
}, 0 },
10937 /* VEX_W_0FC5_P_2 */
10938 { "vpextrw", { Gdq
, XS
, Ib
}, 0 },
10941 /* VEX_W_0FD0_P_2 */
10942 { "vaddsubpd", { XM
, Vex
, EXx
}, 0 },
10945 /* VEX_W_0FD0_P_3 */
10946 { "vaddsubps", { XM
, Vex
, EXx
}, 0 },
10949 /* VEX_W_0FD1_P_2 */
10950 { "vpsrlw", { XM
, Vex
, EXxmm
}, 0 },
10953 /* VEX_W_0FD2_P_2 */
10954 { "vpsrld", { XM
, Vex
, EXxmm
}, 0 },
10957 /* VEX_W_0FD3_P_2 */
10958 { "vpsrlq", { XM
, Vex
, EXxmm
}, 0 },
10961 /* VEX_W_0FD4_P_2 */
10962 { "vpaddq", { XM
, Vex
, EXx
}, 0 },
10965 /* VEX_W_0FD5_P_2 */
10966 { "vpmullw", { XM
, Vex
, EXx
}, 0 },
10969 /* VEX_W_0FD6_P_2 */
10970 { "vmovq", { EXqScalarS
, XMScalar
}, 0 },
10973 /* VEX_W_0FD7_P_2_M_1 */
10974 { "vpmovmskb", { Gdq
, XS
}, 0 },
10977 /* VEX_W_0FD8_P_2 */
10978 { "vpsubusb", { XM
, Vex
, EXx
}, 0 },
10981 /* VEX_W_0FD9_P_2 */
10982 { "vpsubusw", { XM
, Vex
, EXx
}, 0 },
10985 /* VEX_W_0FDA_P_2 */
10986 { "vpminub", { XM
, Vex
, EXx
}, 0 },
10989 /* VEX_W_0FDB_P_2 */
10990 { "vpand", { XM
, Vex
, EXx
}, 0 },
10993 /* VEX_W_0FDC_P_2 */
10994 { "vpaddusb", { XM
, Vex
, EXx
}, 0 },
10997 /* VEX_W_0FDD_P_2 */
10998 { "vpaddusw", { XM
, Vex
, EXx
}, 0 },
11001 /* VEX_W_0FDE_P_2 */
11002 { "vpmaxub", { XM
, Vex
, EXx
}, 0 },
11005 /* VEX_W_0FDF_P_2 */
11006 { "vpandn", { XM
, Vex
, EXx
}, 0 },
11009 /* VEX_W_0FE0_P_2 */
11010 { "vpavgb", { XM
, Vex
, EXx
}, 0 },
11013 /* VEX_W_0FE1_P_2 */
11014 { "vpsraw", { XM
, Vex
, EXxmm
}, 0 },
11017 /* VEX_W_0FE2_P_2 */
11018 { "vpsrad", { XM
, Vex
, EXxmm
}, 0 },
11021 /* VEX_W_0FE3_P_2 */
11022 { "vpavgw", { XM
, Vex
, EXx
}, 0 },
11025 /* VEX_W_0FE4_P_2 */
11026 { "vpmulhuw", { XM
, Vex
, EXx
}, 0 },
11029 /* VEX_W_0FE5_P_2 */
11030 { "vpmulhw", { XM
, Vex
, EXx
}, 0 },
11033 /* VEX_W_0FE6_P_1 */
11034 { "vcvtdq2pd", { XM
, EXxmmq
}, 0 },
11037 /* VEX_W_0FE6_P_2 */
11038 { "vcvttpd2dq%XY", { XMM
, EXx
}, 0 },
11041 /* VEX_W_0FE6_P_3 */
11042 { "vcvtpd2dq%XY", { XMM
, EXx
}, 0 },
11045 /* VEX_W_0FE7_P_2_M_0 */
11046 { "vmovntdq", { Mx
, XM
}, 0 },
11049 /* VEX_W_0FE8_P_2 */
11050 { "vpsubsb", { XM
, Vex
, EXx
}, 0 },
11053 /* VEX_W_0FE9_P_2 */
11054 { "vpsubsw", { XM
, Vex
, EXx
}, 0 },
11057 /* VEX_W_0FEA_P_2 */
11058 { "vpminsw", { XM
, Vex
, EXx
}, 0 },
11061 /* VEX_W_0FEB_P_2 */
11062 { "vpor", { XM
, Vex
, EXx
}, 0 },
11065 /* VEX_W_0FEC_P_2 */
11066 { "vpaddsb", { XM
, Vex
, EXx
}, 0 },
11069 /* VEX_W_0FED_P_2 */
11070 { "vpaddsw", { XM
, Vex
, EXx
}, 0 },
11073 /* VEX_W_0FEE_P_2 */
11074 { "vpmaxsw", { XM
, Vex
, EXx
}, 0 },
11077 /* VEX_W_0FEF_P_2 */
11078 { "vpxor", { XM
, Vex
, EXx
}, 0 },
11081 /* VEX_W_0FF0_P_3_M_0 */
11082 { "vlddqu", { XM
, M
}, 0 },
11085 /* VEX_W_0FF1_P_2 */
11086 { "vpsllw", { XM
, Vex
, EXxmm
}, 0 },
11089 /* VEX_W_0FF2_P_2 */
11090 { "vpslld", { XM
, Vex
, EXxmm
}, 0 },
11093 /* VEX_W_0FF3_P_2 */
11094 { "vpsllq", { XM
, Vex
, EXxmm
}, 0 },
11097 /* VEX_W_0FF4_P_2 */
11098 { "vpmuludq", { XM
, Vex
, EXx
}, 0 },
11101 /* VEX_W_0FF5_P_2 */
11102 { "vpmaddwd", { XM
, Vex
, EXx
}, 0 },
11105 /* VEX_W_0FF6_P_2 */
11106 { "vpsadbw", { XM
, Vex
, EXx
}, 0 },
11109 /* VEX_W_0FF7_P_2 */
11110 { "vmaskmovdqu", { XM
, XS
}, 0 },
11113 /* VEX_W_0FF8_P_2 */
11114 { "vpsubb", { XM
, Vex
, EXx
}, 0 },
11117 /* VEX_W_0FF9_P_2 */
11118 { "vpsubw", { XM
, Vex
, EXx
}, 0 },
11121 /* VEX_W_0FFA_P_2 */
11122 { "vpsubd", { XM
, Vex
, EXx
}, 0 },
11125 /* VEX_W_0FFB_P_2 */
11126 { "vpsubq", { XM
, Vex
, EXx
}, 0 },
11129 /* VEX_W_0FFC_P_2 */
11130 { "vpaddb", { XM
, Vex
, EXx
}, 0 },
11133 /* VEX_W_0FFD_P_2 */
11134 { "vpaddw", { XM
, Vex
, EXx
}, 0 },
11137 /* VEX_W_0FFE_P_2 */
11138 { "vpaddd", { XM
, Vex
, EXx
}, 0 },
11141 /* VEX_W_0F3800_P_2 */
11142 { "vpshufb", { XM
, Vex
, EXx
}, 0 },
11145 /* VEX_W_0F3801_P_2 */
11146 { "vphaddw", { XM
, Vex
, EXx
}, 0 },
11149 /* VEX_W_0F3802_P_2 */
11150 { "vphaddd", { XM
, Vex
, EXx
}, 0 },
11153 /* VEX_W_0F3803_P_2 */
11154 { "vphaddsw", { XM
, Vex
, EXx
}, 0 },
11157 /* VEX_W_0F3804_P_2 */
11158 { "vpmaddubsw", { XM
, Vex
, EXx
}, 0 },
11161 /* VEX_W_0F3805_P_2 */
11162 { "vphsubw", { XM
, Vex
, EXx
}, 0 },
11165 /* VEX_W_0F3806_P_2 */
11166 { "vphsubd", { XM
, Vex
, EXx
}, 0 },
11169 /* VEX_W_0F3807_P_2 */
11170 { "vphsubsw", { XM
, Vex
, EXx
}, 0 },
11173 /* VEX_W_0F3808_P_2 */
11174 { "vpsignb", { XM
, Vex
, EXx
}, 0 },
11177 /* VEX_W_0F3809_P_2 */
11178 { "vpsignw", { XM
, Vex
, EXx
}, 0 },
11181 /* VEX_W_0F380A_P_2 */
11182 { "vpsignd", { XM
, Vex
, EXx
}, 0 },
11185 /* VEX_W_0F380B_P_2 */
11186 { "vpmulhrsw", { XM
, Vex
, EXx
}, 0 },
11189 /* VEX_W_0F380C_P_2 */
11190 { "vpermilps", { XM
, Vex
, EXx
}, 0 },
11193 /* VEX_W_0F380D_P_2 */
11194 { "vpermilpd", { XM
, Vex
, EXx
}, 0 },
11197 /* VEX_W_0F380E_P_2 */
11198 { "vtestps", { XM
, EXx
}, 0 },
11201 /* VEX_W_0F380F_P_2 */
11202 { "vtestpd", { XM
, EXx
}, 0 },
11205 /* VEX_W_0F3816_P_2 */
11206 { "vpermps", { XM
, Vex
, EXx
}, 0 },
11209 /* VEX_W_0F3817_P_2 */
11210 { "vptest", { XM
, EXx
}, 0 },
11213 /* VEX_W_0F3818_P_2 */
11214 { "vbroadcastss", { XM
, EXxmm_md
}, 0 },
11217 /* VEX_W_0F3819_P_2 */
11218 { "vbroadcastsd", { XM
, EXxmm_mq
}, 0 },
11221 /* VEX_W_0F381A_P_2_M_0 */
11222 { "vbroadcastf128", { XM
, Mxmm
}, 0 },
11225 /* VEX_W_0F381C_P_2 */
11226 { "vpabsb", { XM
, EXx
}, 0 },
11229 /* VEX_W_0F381D_P_2 */
11230 { "vpabsw", { XM
, EXx
}, 0 },
11233 /* VEX_W_0F381E_P_2 */
11234 { "vpabsd", { XM
, EXx
}, 0 },
11237 /* VEX_W_0F3820_P_2 */
11238 { "vpmovsxbw", { XM
, EXxmmq
}, 0 },
11241 /* VEX_W_0F3821_P_2 */
11242 { "vpmovsxbd", { XM
, EXxmmqd
}, 0 },
11245 /* VEX_W_0F3822_P_2 */
11246 { "vpmovsxbq", { XM
, EXxmmdw
}, 0 },
11249 /* VEX_W_0F3823_P_2 */
11250 { "vpmovsxwd", { XM
, EXxmmq
}, 0 },
11253 /* VEX_W_0F3824_P_2 */
11254 { "vpmovsxwq", { XM
, EXxmmqd
}, 0 },
11257 /* VEX_W_0F3825_P_2 */
11258 { "vpmovsxdq", { XM
, EXxmmq
}, 0 },
11261 /* VEX_W_0F3828_P_2 */
11262 { "vpmuldq", { XM
, Vex
, EXx
}, 0 },
11265 /* VEX_W_0F3829_P_2 */
11266 { "vpcmpeqq", { XM
, Vex
, EXx
}, 0 },
11269 /* VEX_W_0F382A_P_2_M_0 */
11270 { "vmovntdqa", { XM
, Mx
}, 0 },
11273 /* VEX_W_0F382B_P_2 */
11274 { "vpackusdw", { XM
, Vex
, EXx
}, 0 },
11277 /* VEX_W_0F382C_P_2_M_0 */
11278 { "vmaskmovps", { XM
, Vex
, Mx
}, 0 },
11281 /* VEX_W_0F382D_P_2_M_0 */
11282 { "vmaskmovpd", { XM
, Vex
, Mx
}, 0 },
11285 /* VEX_W_0F382E_P_2_M_0 */
11286 { "vmaskmovps", { Mx
, Vex
, XM
}, 0 },
11289 /* VEX_W_0F382F_P_2_M_0 */
11290 { "vmaskmovpd", { Mx
, Vex
, XM
}, 0 },
11293 /* VEX_W_0F3830_P_2 */
11294 { "vpmovzxbw", { XM
, EXxmmq
}, 0 },
11297 /* VEX_W_0F3831_P_2 */
11298 { "vpmovzxbd", { XM
, EXxmmqd
}, 0 },
11301 /* VEX_W_0F3832_P_2 */
11302 { "vpmovzxbq", { XM
, EXxmmdw
}, 0 },
11305 /* VEX_W_0F3833_P_2 */
11306 { "vpmovzxwd", { XM
, EXxmmq
}, 0 },
11309 /* VEX_W_0F3834_P_2 */
11310 { "vpmovzxwq", { XM
, EXxmmqd
}, 0 },
11313 /* VEX_W_0F3835_P_2 */
11314 { "vpmovzxdq", { XM
, EXxmmq
}, 0 },
11317 /* VEX_W_0F3836_P_2 */
11318 { "vpermd", { XM
, Vex
, EXx
}, 0 },
11321 /* VEX_W_0F3837_P_2 */
11322 { "vpcmpgtq", { XM
, Vex
, EXx
}, 0 },
11325 /* VEX_W_0F3838_P_2 */
11326 { "vpminsb", { XM
, Vex
, EXx
}, 0 },
11329 /* VEX_W_0F3839_P_2 */
11330 { "vpminsd", { XM
, Vex
, EXx
}, 0 },
11333 /* VEX_W_0F383A_P_2 */
11334 { "vpminuw", { XM
, Vex
, EXx
}, 0 },
11337 /* VEX_W_0F383B_P_2 */
11338 { "vpminud", { XM
, Vex
, EXx
}, 0 },
11341 /* VEX_W_0F383C_P_2 */
11342 { "vpmaxsb", { XM
, Vex
, EXx
}, 0 },
11345 /* VEX_W_0F383D_P_2 */
11346 { "vpmaxsd", { XM
, Vex
, EXx
}, 0 },
11349 /* VEX_W_0F383E_P_2 */
11350 { "vpmaxuw", { XM
, Vex
, EXx
}, 0 },
11353 /* VEX_W_0F383F_P_2 */
11354 { "vpmaxud", { XM
, Vex
, EXx
}, 0 },
11357 /* VEX_W_0F3840_P_2 */
11358 { "vpmulld", { XM
, Vex
, EXx
}, 0 },
11361 /* VEX_W_0F3841_P_2 */
11362 { "vphminposuw", { XM
, EXx
}, 0 },
11365 /* VEX_W_0F3846_P_2 */
11366 { "vpsravd", { XM
, Vex
, EXx
}, 0 },
11369 /* VEX_W_0F3858_P_2 */
11370 { "vpbroadcastd", { XM
, EXxmm_md
}, 0 },
11373 /* VEX_W_0F3859_P_2 */
11374 { "vpbroadcastq", { XM
, EXxmm_mq
}, 0 },
11377 /* VEX_W_0F385A_P_2_M_0 */
11378 { "vbroadcasti128", { XM
, Mxmm
}, 0 },
11381 /* VEX_W_0F3878_P_2 */
11382 { "vpbroadcastb", { XM
, EXxmm_mb
}, 0 },
11385 /* VEX_W_0F3879_P_2 */
11386 { "vpbroadcastw", { XM
, EXxmm_mw
}, 0 },
11389 /* VEX_W_0F38DB_P_2 */
11390 { "vaesimc", { XM
, EXx
}, 0 },
11393 /* VEX_W_0F38DC_P_2 */
11394 { "vaesenc", { XM
, Vex128
, EXx
}, 0 },
11397 /* VEX_W_0F38DD_P_2 */
11398 { "vaesenclast", { XM
, Vex128
, EXx
}, 0 },
11401 /* VEX_W_0F38DE_P_2 */
11402 { "vaesdec", { XM
, Vex128
, EXx
}, 0 },
11405 /* VEX_W_0F38DF_P_2 */
11406 { "vaesdeclast", { XM
, Vex128
, EXx
}, 0 },
11409 /* VEX_W_0F3A00_P_2 */
11411 { "vpermq", { XM
, EXx
, Ib
}, 0 },
11414 /* VEX_W_0F3A01_P_2 */
11416 { "vpermpd", { XM
, EXx
, Ib
}, 0 },
11419 /* VEX_W_0F3A02_P_2 */
11420 { "vpblendd", { XM
, Vex
, EXx
, Ib
}, 0 },
11423 /* VEX_W_0F3A04_P_2 */
11424 { "vpermilps", { XM
, EXx
, Ib
}, 0 },
11427 /* VEX_W_0F3A05_P_2 */
11428 { "vpermilpd", { XM
, EXx
, Ib
}, 0 },
11431 /* VEX_W_0F3A06_P_2 */
11432 { "vperm2f128", { XM
, Vex256
, EXx
, Ib
}, 0 },
11435 /* VEX_W_0F3A08_P_2 */
11436 { "vroundps", { XM
, EXx
, Ib
}, 0 },
11439 /* VEX_W_0F3A09_P_2 */
11440 { "vroundpd", { XM
, EXx
, Ib
}, 0 },
11443 /* VEX_W_0F3A0A_P_2 */
11444 { "vroundss", { XMScalar
, VexScalar
, EXdScalar
, Ib
}, 0 },
11447 /* VEX_W_0F3A0B_P_2 */
11448 { "vroundsd", { XMScalar
, VexScalar
, EXqScalar
, Ib
}, 0 },
11451 /* VEX_W_0F3A0C_P_2 */
11452 { "vblendps", { XM
, Vex
, EXx
, Ib
}, 0 },
11455 /* VEX_W_0F3A0D_P_2 */
11456 { "vblendpd", { XM
, Vex
, EXx
, Ib
}, 0 },
11459 /* VEX_W_0F3A0E_P_2 */
11460 { "vpblendw", { XM
, Vex
, EXx
, Ib
}, 0 },
11463 /* VEX_W_0F3A0F_P_2 */
11464 { "vpalignr", { XM
, Vex
, EXx
, Ib
}, 0 },
11467 /* VEX_W_0F3A14_P_2 */
11468 { "vpextrb", { Edqb
, XM
, Ib
}, 0 },
11471 /* VEX_W_0F3A15_P_2 */
11472 { "vpextrw", { Edqw
, XM
, Ib
}, 0 },
11475 /* VEX_W_0F3A18_P_2 */
11476 { "vinsertf128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
11479 /* VEX_W_0F3A19_P_2 */
11480 { "vextractf128", { EXxmm
, XM
, Ib
}, 0 },
11483 /* VEX_W_0F3A20_P_2 */
11484 { "vpinsrb", { XM
, Vex128
, Edqb
, Ib
}, 0 },
11487 /* VEX_W_0F3A21_P_2 */
11488 { "vinsertps", { XM
, Vex128
, EXd
, Ib
}, 0 },
11491 /* VEX_W_0F3A30_P_2_LEN_0 */
11492 { "kshiftrb", { MaskG
, MaskR
, Ib
}, 0 },
11493 { "kshiftrw", { MaskG
, MaskR
, Ib
}, 0 },
11496 /* VEX_W_0F3A31_P_2_LEN_0 */
11497 { "kshiftrd", { MaskG
, MaskR
, Ib
}, 0 },
11498 { "kshiftrq", { MaskG
, MaskR
, Ib
}, 0 },
11501 /* VEX_W_0F3A32_P_2_LEN_0 */
11502 { "kshiftlb", { MaskG
, MaskR
, Ib
}, 0 },
11503 { "kshiftlw", { MaskG
, MaskR
, Ib
}, 0 },
11506 /* VEX_W_0F3A33_P_2_LEN_0 */
11507 { "kshiftld", { MaskG
, MaskR
, Ib
}, 0 },
11508 { "kshiftlq", { MaskG
, MaskR
, Ib
}, 0 },
11511 /* VEX_W_0F3A38_P_2 */
11512 { "vinserti128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
11515 /* VEX_W_0F3A39_P_2 */
11516 { "vextracti128", { EXxmm
, XM
, Ib
}, 0 },
11519 /* VEX_W_0F3A40_P_2 */
11520 { "vdpps", { XM
, Vex
, EXx
, Ib
}, 0 },
11523 /* VEX_W_0F3A41_P_2 */
11524 { "vdppd", { XM
, Vex128
, EXx
, Ib
}, 0 },
11527 /* VEX_W_0F3A42_P_2 */
11528 { "vmpsadbw", { XM
, Vex
, EXx
, Ib
}, 0 },
11531 /* VEX_W_0F3A44_P_2 */
11532 { "vpclmulqdq", { XM
, Vex128
, EXx
, PCLMUL
}, 0 },
11535 /* VEX_W_0F3A46_P_2 */
11536 { "vperm2i128", { XM
, Vex256
, EXx
, Ib
}, 0 },
11539 /* VEX_W_0F3A48_P_2 */
11540 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
11541 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
11544 /* VEX_W_0F3A49_P_2 */
11545 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
11546 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
11549 /* VEX_W_0F3A4A_P_2 */
11550 { "vblendvps", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
11553 /* VEX_W_0F3A4B_P_2 */
11554 { "vblendvpd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
11557 /* VEX_W_0F3A4C_P_2 */
11558 { "vpblendvb", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
11561 /* VEX_W_0F3A60_P_2 */
11562 { "vpcmpestrm", { XM
, EXx
, Ib
}, 0 },
11565 /* VEX_W_0F3A61_P_2 */
11566 { "vpcmpestri", { XM
, EXx
, Ib
}, 0 },
11569 /* VEX_W_0F3A62_P_2 */
11570 { "vpcmpistrm", { XM
, EXx
, Ib
}, 0 },
11573 /* VEX_W_0F3A63_P_2 */
11574 { "vpcmpistri", { XM
, EXx
, Ib
}, 0 },
11577 /* VEX_W_0F3ADF_P_2 */
11578 { "vaeskeygenassist", { XM
, EXx
, Ib
}, 0 },
11580 #define NEED_VEX_W_TABLE
11581 #include "i386-dis-evex.h"
11582 #undef NEED_VEX_W_TABLE
11585 static const struct dis386 mod_table
[][2] = {
11588 { "leaS", { Gv
, M
}, 0 },
11593 { RM_TABLE (RM_C6_REG_7
) },
11598 { RM_TABLE (RM_C7_REG_7
) },
11602 { "Jcall^", { indirEp
}, 0 },
11606 { "Jjmp^", { indirEp
}, 0 },
11609 /* MOD_0F01_REG_0 */
11610 { X86_64_TABLE (X86_64_0F01_REG_0
) },
11611 { RM_TABLE (RM_0F01_REG_0
) },
11614 /* MOD_0F01_REG_1 */
11615 { X86_64_TABLE (X86_64_0F01_REG_1
) },
11616 { RM_TABLE (RM_0F01_REG_1
) },
11619 /* MOD_0F01_REG_2 */
11620 { X86_64_TABLE (X86_64_0F01_REG_2
) },
11621 { RM_TABLE (RM_0F01_REG_2
) },
11624 /* MOD_0F01_REG_3 */
11625 { X86_64_TABLE (X86_64_0F01_REG_3
) },
11626 { RM_TABLE (RM_0F01_REG_3
) },
11629 /* MOD_0F01_REG_7 */
11630 { "invlpg", { Mb
}, 0 },
11631 { RM_TABLE (RM_0F01_REG_7
) },
11634 /* MOD_0F12_PREFIX_0 */
11635 { "movlps", { XM
, EXq
}, PREFIX_OPCODE
},
11636 { "movhlps", { XM
, EXq
}, PREFIX_OPCODE
},
11640 { "movlpX", { EXq
, XM
}, PREFIX_OPCODE
},
11643 /* MOD_0F16_PREFIX_0 */
11644 { "movhps", { XM
, EXq
}, 0 },
11645 { "movlhps", { XM
, EXq
}, 0 },
11649 { "movhpX", { EXq
, XM
}, PREFIX_OPCODE
},
11652 /* MOD_0F18_REG_0 */
11653 { "prefetchnta", { Mb
}, 0 },
11656 /* MOD_0F18_REG_1 */
11657 { "prefetcht0", { Mb
}, 0 },
11660 /* MOD_0F18_REG_2 */
11661 { "prefetcht1", { Mb
}, 0 },
11664 /* MOD_0F18_REG_3 */
11665 { "prefetcht2", { Mb
}, 0 },
11668 /* MOD_0F18_REG_4 */
11669 { "nop/reserved", { Mb
}, 0 },
11672 /* MOD_0F18_REG_5 */
11673 { "nop/reserved", { Mb
}, 0 },
11676 /* MOD_0F18_REG_6 */
11677 { "nop/reserved", { Mb
}, 0 },
11680 /* MOD_0F18_REG_7 */
11681 { "nop/reserved", { Mb
}, 0 },
11684 /* MOD_0F1A_PREFIX_0 */
11685 { "bndldx", { Gbnd
, Ev_bnd
}, 0 },
11686 { "nopQ", { Ev
}, 0 },
11689 /* MOD_0F1B_PREFIX_0 */
11690 { "bndstx", { Ev_bnd
, Gbnd
}, 0 },
11691 { "nopQ", { Ev
}, 0 },
11694 /* MOD_0F1B_PREFIX_1 */
11695 { "bndmk", { Gbnd
, Ev_bnd
}, 0 },
11696 { "nopQ", { Ev
}, 0 },
11701 { "movL", { Rd
, Td
}, 0 },
11706 { "movL", { Td
, Rd
}, 0 },
11709 /* MOD_0F2B_PREFIX_0 */
11710 {"movntps", { Mx
, XM
}, PREFIX_OPCODE
},
11713 /* MOD_0F2B_PREFIX_1 */
11714 {"movntss", { Md
, XM
}, PREFIX_OPCODE
},
11717 /* MOD_0F2B_PREFIX_2 */
11718 {"movntpd", { Mx
, XM
}, PREFIX_OPCODE
},
11721 /* MOD_0F2B_PREFIX_3 */
11722 {"movntsd", { Mq
, XM
}, PREFIX_OPCODE
},
11727 { "movmskpX", { Gdq
, XS
}, PREFIX_OPCODE
},
11730 /* MOD_0F71_REG_2 */
11732 { "psrlw", { MS
, Ib
}, 0 },
11735 /* MOD_0F71_REG_4 */
11737 { "psraw", { MS
, Ib
}, 0 },
11740 /* MOD_0F71_REG_6 */
11742 { "psllw", { MS
, Ib
}, 0 },
11745 /* MOD_0F72_REG_2 */
11747 { "psrld", { MS
, Ib
}, 0 },
11750 /* MOD_0F72_REG_4 */
11752 { "psrad", { MS
, Ib
}, 0 },
11755 /* MOD_0F72_REG_6 */
11757 { "pslld", { MS
, Ib
}, 0 },
11760 /* MOD_0F73_REG_2 */
11762 { "psrlq", { MS
, Ib
}, 0 },
11765 /* MOD_0F73_REG_3 */
11767 { PREFIX_TABLE (PREFIX_0F73_REG_3
) },
11770 /* MOD_0F73_REG_6 */
11772 { "psllq", { MS
, Ib
}, 0 },
11775 /* MOD_0F73_REG_7 */
11777 { PREFIX_TABLE (PREFIX_0F73_REG_7
) },
11780 /* MOD_0FAE_REG_0 */
11781 { "fxsave", { FXSAVE
}, 0 },
11782 { PREFIX_TABLE (PREFIX_0FAE_REG_0
) },
11785 /* MOD_0FAE_REG_1 */
11786 { "fxrstor", { FXSAVE
}, 0 },
11787 { PREFIX_TABLE (PREFIX_0FAE_REG_1
) },
11790 /* MOD_0FAE_REG_2 */
11791 { "ldmxcsr", { Md
}, 0 },
11792 { PREFIX_TABLE (PREFIX_0FAE_REG_2
) },
11795 /* MOD_0FAE_REG_3 */
11796 { "stmxcsr", { Md
}, 0 },
11797 { PREFIX_TABLE (PREFIX_0FAE_REG_3
) },
11800 /* MOD_0FAE_REG_4 */
11801 { "xsave", { FXSAVE
}, 0 },
11804 /* MOD_0FAE_REG_5 */
11805 { "xrstor", { FXSAVE
}, 0 },
11806 { RM_TABLE (RM_0FAE_REG_5
) },
11809 /* MOD_0FAE_REG_6 */
11810 { PREFIX_TABLE (PREFIX_0FAE_REG_6
) },
11811 { RM_TABLE (RM_0FAE_REG_6
) },
11814 /* MOD_0FAE_REG_7 */
11815 { PREFIX_TABLE (PREFIX_0FAE_REG_7
) },
11816 { RM_TABLE (RM_0FAE_REG_7
) },
11820 { "lssS", { Gv
, Mp
}, 0 },
11824 { "lfsS", { Gv
, Mp
}, 0 },
11828 { "lgsS", { Gv
, Mp
}, 0 },
11832 { PREFIX_TABLE (PREFIX_MOD_0_0FC3
) },
11835 /* MOD_0FC7_REG_3 */
11836 { "xrstors", { FXSAVE
}, 0 },
11839 /* MOD_0FC7_REG_4 */
11840 { "xsavec", { FXSAVE
}, 0 },
11843 /* MOD_0FC7_REG_5 */
11844 { "xsaves", { FXSAVE
}, 0 },
11847 /* MOD_0FC7_REG_6 */
11848 { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6
) },
11849 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6
) }
11852 /* MOD_0FC7_REG_7 */
11853 { "vmptrst", { Mq
}, 0 },
11854 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7
) }
11859 { "pmovmskb", { Gdq
, MS
}, 0 },
11862 /* MOD_0FE7_PREFIX_2 */
11863 { "movntdq", { Mx
, XM
}, 0 },
11866 /* MOD_0FF0_PREFIX_3 */
11867 { "lddqu", { XM
, M
}, 0 },
11870 /* MOD_0F382A_PREFIX_2 */
11871 { "movntdqa", { XM
, Mx
}, 0 },
11875 { "bound{S|}", { Gv
, Ma
}, 0 },
11876 { EVEX_TABLE (EVEX_0F
) },
11880 { "lesS", { Gv
, Mp
}, 0 },
11881 { VEX_C4_TABLE (VEX_0F
) },
11885 { "ldsS", { Gv
, Mp
}, 0 },
11886 { VEX_C5_TABLE (VEX_0F
) },
11889 /* MOD_VEX_0F12_PREFIX_0 */
11890 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0
) },
11891 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1
) },
11895 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0
) },
11898 /* MOD_VEX_0F16_PREFIX_0 */
11899 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0
) },
11900 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1
) },
11904 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0
) },
11908 { VEX_W_TABLE (VEX_W_0F2B_M_0
) },
11913 { VEX_W_TABLE (VEX_W_0F50_M_0
) },
11916 /* MOD_VEX_0F71_REG_2 */
11918 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2
) },
11921 /* MOD_VEX_0F71_REG_4 */
11923 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4
) },
11926 /* MOD_VEX_0F71_REG_6 */
11928 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6
) },
11931 /* MOD_VEX_0F72_REG_2 */
11933 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2
) },
11936 /* MOD_VEX_0F72_REG_4 */
11938 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4
) },
11941 /* MOD_VEX_0F72_REG_6 */
11943 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6
) },
11946 /* MOD_VEX_0F73_REG_2 */
11948 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2
) },
11951 /* MOD_VEX_0F73_REG_3 */
11953 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3
) },
11956 /* MOD_VEX_0F73_REG_6 */
11958 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6
) },
11961 /* MOD_VEX_0F73_REG_7 */
11963 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7
) },
11966 /* MOD_VEX_0FAE_REG_2 */
11967 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0
) },
11970 /* MOD_VEX_0FAE_REG_3 */
11971 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0
) },
11974 /* MOD_VEX_0FD7_PREFIX_2 */
11976 { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1
) },
11979 /* MOD_VEX_0FE7_PREFIX_2 */
11980 { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0
) },
11983 /* MOD_VEX_0FF0_PREFIX_3 */
11984 { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0
) },
11987 /* MOD_VEX_0F381A_PREFIX_2 */
11988 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0
) },
11991 /* MOD_VEX_0F382A_PREFIX_2 */
11992 { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0
) },
11995 /* MOD_VEX_0F382C_PREFIX_2 */
11996 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0
) },
11999 /* MOD_VEX_0F382D_PREFIX_2 */
12000 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0
) },
12003 /* MOD_VEX_0F382E_PREFIX_2 */
12004 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0
) },
12007 /* MOD_VEX_0F382F_PREFIX_2 */
12008 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0
) },
12011 /* MOD_VEX_0F385A_PREFIX_2 */
12012 { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0
) },
12015 /* MOD_VEX_0F388C_PREFIX_2 */
12016 { "vpmaskmov%LW", { XM
, Vex
, Mx
}, 0 },
12019 /* MOD_VEX_0F388E_PREFIX_2 */
12020 { "vpmaskmov%LW", { Mx
, Vex
, XM
}, 0 },
12022 #define NEED_MOD_TABLE
12023 #include "i386-dis-evex.h"
12024 #undef NEED_MOD_TABLE
12027 static const struct dis386 rm_table
[][8] = {
12030 { "xabort", { Skip_MODRM
, Ib
}, 0 },
12034 { "xbeginT", { Skip_MODRM
, Jv
}, 0 },
12037 /* RM_0F01_REG_0 */
12039 { "vmcall", { Skip_MODRM
}, 0 },
12040 { "vmlaunch", { Skip_MODRM
}, 0 },
12041 { "vmresume", { Skip_MODRM
}, 0 },
12042 { "vmxoff", { Skip_MODRM
}, 0 },
12045 /* RM_0F01_REG_1 */
12046 { "monitor", { { OP_Monitor
, 0 } }, 0 },
12047 { "mwait", { { OP_Mwait
, 0 } }, 0 },
12048 { "clac", { Skip_MODRM
}, 0 },
12049 { "stac", { Skip_MODRM
}, 0 },
12053 { "encls", { Skip_MODRM
}, 0 },
12056 /* RM_0F01_REG_2 */
12057 { "xgetbv", { Skip_MODRM
}, 0 },
12058 { "xsetbv", { Skip_MODRM
}, 0 },
12061 { "vmfunc", { Skip_MODRM
}, 0 },
12062 { "xend", { Skip_MODRM
}, 0 },
12063 { "xtest", { Skip_MODRM
}, 0 },
12064 { "enclu", { Skip_MODRM
}, 0 },
12067 /* RM_0F01_REG_3 */
12068 { "vmrun", { Skip_MODRM
}, 0 },
12069 { "vmmcall", { Skip_MODRM
}, 0 },
12070 { "vmload", { Skip_MODRM
}, 0 },
12071 { "vmsave", { Skip_MODRM
}, 0 },
12072 { "stgi", { Skip_MODRM
}, 0 },
12073 { "clgi", { Skip_MODRM
}, 0 },
12074 { "skinit", { Skip_MODRM
}, 0 },
12075 { "invlpga", { Skip_MODRM
}, 0 },
12078 /* RM_0F01_REG_7 */
12079 { "swapgs", { Skip_MODRM
}, 0 },
12080 { "rdtscp", { Skip_MODRM
}, 0 },
12081 { "monitorx", { { OP_Monitor
, 0 } }, 0 },
12082 { "mwaitx", { { OP_Mwaitx
, 0 } }, 0 },
12083 { "clzero", { Skip_MODRM
}, 0 },
12086 /* RM_0FAE_REG_5 */
12087 { "lfence", { Skip_MODRM
}, 0 },
12090 /* RM_0FAE_REG_6 */
12091 { "mfence", { Skip_MODRM
}, 0 },
12094 /* RM_0FAE_REG_7 */
12095 { PREFIX_TABLE (PREFIX_RM_0_0FAE_REG_7
) },
12099 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
12101 /* We use the high bit to indicate different name for the same
12103 #define REP_PREFIX (0xf3 | 0x100)
12104 #define XACQUIRE_PREFIX (0xf2 | 0x200)
12105 #define XRELEASE_PREFIX (0xf3 | 0x400)
12106 #define BND_PREFIX (0xf2 | 0x400)
12111 int newrex
, i
, length
;
12117 last_lock_prefix
= -1;
12118 last_repz_prefix
= -1;
12119 last_repnz_prefix
= -1;
12120 last_data_prefix
= -1;
12121 last_addr_prefix
= -1;
12122 last_rex_prefix
= -1;
12123 last_seg_prefix
= -1;
12125 active_seg_prefix
= 0;
12126 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
12127 all_prefixes
[i
] = 0;
12130 /* The maximum instruction length is 15bytes. */
12131 while (length
< MAX_CODE_LENGTH
- 1)
12133 FETCH_DATA (the_info
, codep
+ 1);
12137 /* REX prefixes family. */
12154 if (address_mode
== mode_64bit
)
12158 last_rex_prefix
= i
;
12161 prefixes
|= PREFIX_REPZ
;
12162 last_repz_prefix
= i
;
12165 prefixes
|= PREFIX_REPNZ
;
12166 last_repnz_prefix
= i
;
12169 prefixes
|= PREFIX_LOCK
;
12170 last_lock_prefix
= i
;
12173 prefixes
|= PREFIX_CS
;
12174 last_seg_prefix
= i
;
12175 active_seg_prefix
= PREFIX_CS
;
12178 prefixes
|= PREFIX_SS
;
12179 last_seg_prefix
= i
;
12180 active_seg_prefix
= PREFIX_SS
;
12183 prefixes
|= PREFIX_DS
;
12184 last_seg_prefix
= i
;
12185 active_seg_prefix
= PREFIX_DS
;
12188 prefixes
|= PREFIX_ES
;
12189 last_seg_prefix
= i
;
12190 active_seg_prefix
= PREFIX_ES
;
12193 prefixes
|= PREFIX_FS
;
12194 last_seg_prefix
= i
;
12195 active_seg_prefix
= PREFIX_FS
;
12198 prefixes
|= PREFIX_GS
;
12199 last_seg_prefix
= i
;
12200 active_seg_prefix
= PREFIX_GS
;
12203 prefixes
|= PREFIX_DATA
;
12204 last_data_prefix
= i
;
12207 prefixes
|= PREFIX_ADDR
;
12208 last_addr_prefix
= i
;
12211 /* fwait is really an instruction. If there are prefixes
12212 before the fwait, they belong to the fwait, *not* to the
12213 following instruction. */
12215 if (prefixes
|| rex
)
12217 prefixes
|= PREFIX_FWAIT
;
12219 /* This ensures that the previous REX prefixes are noticed
12220 as unused prefixes, as in the return case below. */
12224 prefixes
= PREFIX_FWAIT
;
12229 /* Rex is ignored when followed by another prefix. */
12235 if (*codep
!= FWAIT_OPCODE
)
12236 all_prefixes
[i
++] = *codep
;
12244 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
12247 static const char *
12248 prefix_name (int pref
, int sizeflag
)
12250 static const char *rexes
[16] =
12253 "rex.B", /* 0x41 */
12254 "rex.X", /* 0x42 */
12255 "rex.XB", /* 0x43 */
12256 "rex.R", /* 0x44 */
12257 "rex.RB", /* 0x45 */
12258 "rex.RX", /* 0x46 */
12259 "rex.RXB", /* 0x47 */
12260 "rex.W", /* 0x48 */
12261 "rex.WB", /* 0x49 */
12262 "rex.WX", /* 0x4a */
12263 "rex.WXB", /* 0x4b */
12264 "rex.WR", /* 0x4c */
12265 "rex.WRB", /* 0x4d */
12266 "rex.WRX", /* 0x4e */
12267 "rex.WRXB", /* 0x4f */
12272 /* REX prefixes family. */
12289 return rexes
[pref
- 0x40];
12309 return (sizeflag
& DFLAG
) ? "data16" : "data32";
12311 if (address_mode
== mode_64bit
)
12312 return (sizeflag
& AFLAG
) ? "addr32" : "addr64";
12314 return (sizeflag
& AFLAG
) ? "addr16" : "addr32";
12319 case XACQUIRE_PREFIX
:
12321 case XRELEASE_PREFIX
:
12330 static char op_out
[MAX_OPERANDS
][100];
12331 static int op_ad
, op_index
[MAX_OPERANDS
];
12332 static int two_source_ops
;
12333 static bfd_vma op_address
[MAX_OPERANDS
];
12334 static bfd_vma op_riprel
[MAX_OPERANDS
];
12335 static bfd_vma start_pc
;
12338 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
12339 * (see topic "Redundant prefixes" in the "Differences from 8086"
12340 * section of the "Virtual 8086 Mode" chapter.)
12341 * 'pc' should be the address of this instruction, it will
12342 * be used to print the target address if this is a relative jump or call
12343 * The function returns the length of this instruction in bytes.
12346 static char intel_syntax
;
12347 static char intel_mnemonic
= !SYSV386_COMPAT
;
12348 static char open_char
;
12349 static char close_char
;
12350 static char separator_char
;
12351 static char scale_char
;
12359 static enum x86_64_isa isa64
;
12361 /* Here for backwards compatibility. When gdb stops using
12362 print_insn_i386_att and print_insn_i386_intel these functions can
12363 disappear, and print_insn_i386 be merged into print_insn. */
12365 print_insn_i386_att (bfd_vma pc
, disassemble_info
*info
)
12369 return print_insn (pc
, info
);
12373 print_insn_i386_intel (bfd_vma pc
, disassemble_info
*info
)
12377 return print_insn (pc
, info
);
12381 print_insn_i386 (bfd_vma pc
, disassemble_info
*info
)
12385 return print_insn (pc
, info
);
12389 print_i386_disassembler_options (FILE *stream
)
12391 fprintf (stream
, _("\n\
12392 The following i386/x86-64 specific disassembler options are supported for use\n\
12393 with the -M switch (multiple options should be separated by commas):\n"));
12395 fprintf (stream
, _(" x86-64 Disassemble in 64bit mode\n"));
12396 fprintf (stream
, _(" i386 Disassemble in 32bit mode\n"));
12397 fprintf (stream
, _(" i8086 Disassemble in 16bit mode\n"));
12398 fprintf (stream
, _(" att Display instruction in AT&T syntax\n"));
12399 fprintf (stream
, _(" intel Display instruction in Intel syntax\n"));
12400 fprintf (stream
, _(" att-mnemonic\n"
12401 " Display instruction in AT&T mnemonic\n"));
12402 fprintf (stream
, _(" intel-mnemonic\n"
12403 " Display instruction in Intel mnemonic\n"));
12404 fprintf (stream
, _(" addr64 Assume 64bit address size\n"));
12405 fprintf (stream
, _(" addr32 Assume 32bit address size\n"));
12406 fprintf (stream
, _(" addr16 Assume 16bit address size\n"));
12407 fprintf (stream
, _(" data32 Assume 32bit data size\n"));
12408 fprintf (stream
, _(" data16 Assume 16bit data size\n"));
12409 fprintf (stream
, _(" suffix Always display instruction suffix in AT&T syntax\n"));
12410 fprintf (stream
, _(" amd64 Display instruction in AMD64 ISA\n"));
12411 fprintf (stream
, _(" intel64 Display instruction in Intel64 ISA\n"));
12415 static const struct dis386 bad_opcode
= { "(bad)", { XX
}, 0 };
12417 /* Get a pointer to struct dis386 with a valid name. */
12419 static const struct dis386
*
12420 get_valid_dis386 (const struct dis386
*dp
, disassemble_info
*info
)
12422 int vindex
, vex_table_index
;
12424 if (dp
->name
!= NULL
)
12427 switch (dp
->op
[0].bytemode
)
12429 case USE_REG_TABLE
:
12430 dp
= ®_table
[dp
->op
[1].bytemode
][modrm
.reg
];
12433 case USE_MOD_TABLE
:
12434 vindex
= modrm
.mod
== 0x3 ? 1 : 0;
12435 dp
= &mod_table
[dp
->op
[1].bytemode
][vindex
];
12439 dp
= &rm_table
[dp
->op
[1].bytemode
][modrm
.rm
];
12442 case USE_PREFIX_TABLE
:
12445 /* The prefix in VEX is implicit. */
12446 switch (vex
.prefix
)
12451 case REPE_PREFIX_OPCODE
:
12454 case DATA_PREFIX_OPCODE
:
12457 case REPNE_PREFIX_OPCODE
:
12467 int last_prefix
= -1;
12470 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12471 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12473 if ((prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0)
12475 if (last_repz_prefix
> last_repnz_prefix
)
12478 prefix
= PREFIX_REPZ
;
12479 last_prefix
= last_repz_prefix
;
12484 prefix
= PREFIX_REPNZ
;
12485 last_prefix
= last_repnz_prefix
;
12488 /* Check if prefix should be ignored. */
12489 if ((((prefix_table
[dp
->op
[1].bytemode
][vindex
].prefix_requirement
12490 & PREFIX_IGNORED
) >> PREFIX_IGNORED_SHIFT
)
12495 if (vindex
== 0 && (prefixes
& PREFIX_DATA
) != 0)
12498 prefix
= PREFIX_DATA
;
12499 last_prefix
= last_data_prefix
;
12504 used_prefixes
|= prefix
;
12505 all_prefixes
[last_prefix
] = 0;
12508 dp
= &prefix_table
[dp
->op
[1].bytemode
][vindex
];
12511 case USE_X86_64_TABLE
:
12512 vindex
= address_mode
== mode_64bit
? 1 : 0;
12513 dp
= &x86_64_table
[dp
->op
[1].bytemode
][vindex
];
12516 case USE_3BYTE_TABLE
:
12517 FETCH_DATA (info
, codep
+ 2);
12519 dp
= &three_byte_table
[dp
->op
[1].bytemode
][vindex
];
12521 modrm
.mod
= (*codep
>> 6) & 3;
12522 modrm
.reg
= (*codep
>> 3) & 7;
12523 modrm
.rm
= *codep
& 7;
12526 case USE_VEX_LEN_TABLE
:
12530 switch (vex
.length
)
12543 dp
= &vex_len_table
[dp
->op
[1].bytemode
][vindex
];
12546 case USE_XOP_8F_TABLE
:
12547 FETCH_DATA (info
, codep
+ 3);
12548 /* All bits in the REX prefix are ignored. */
12550 rex
= ~(*codep
>> 5) & 0x7;
12552 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
12553 switch ((*codep
& 0x1f))
12559 vex_table_index
= XOP_08
;
12562 vex_table_index
= XOP_09
;
12565 vex_table_index
= XOP_0A
;
12569 vex
.w
= *codep
& 0x80;
12570 if (vex
.w
&& address_mode
== mode_64bit
)
12573 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12574 if (address_mode
!= mode_64bit
12575 && vex
.register_specifier
> 0x7)
12581 vex
.length
= (*codep
& 0x4) ? 256 : 128;
12582 switch ((*codep
& 0x3))
12588 vex
.prefix
= DATA_PREFIX_OPCODE
;
12591 vex
.prefix
= REPE_PREFIX_OPCODE
;
12594 vex
.prefix
= REPNE_PREFIX_OPCODE
;
12601 dp
= &xop_table
[vex_table_index
][vindex
];
12604 FETCH_DATA (info
, codep
+ 1);
12605 modrm
.mod
= (*codep
>> 6) & 3;
12606 modrm
.reg
= (*codep
>> 3) & 7;
12607 modrm
.rm
= *codep
& 7;
12610 case USE_VEX_C4_TABLE
:
12612 FETCH_DATA (info
, codep
+ 3);
12613 /* All bits in the REX prefix are ignored. */
12615 rex
= ~(*codep
>> 5) & 0x7;
12616 switch ((*codep
& 0x1f))
12622 vex_table_index
= VEX_0F
;
12625 vex_table_index
= VEX_0F38
;
12628 vex_table_index
= VEX_0F3A
;
12632 vex
.w
= *codep
& 0x80;
12633 if (vex
.w
&& address_mode
== mode_64bit
)
12636 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12637 if (address_mode
!= mode_64bit
12638 && vex
.register_specifier
> 0x7)
12644 vex
.length
= (*codep
& 0x4) ? 256 : 128;
12645 switch ((*codep
& 0x3))
12651 vex
.prefix
= DATA_PREFIX_OPCODE
;
12654 vex
.prefix
= REPE_PREFIX_OPCODE
;
12657 vex
.prefix
= REPNE_PREFIX_OPCODE
;
12664 dp
= &vex_table
[vex_table_index
][vindex
];
12666 /* There is no MODRM byte for VEX [82|77]. */
12667 if (vindex
!= 0x77 && vindex
!= 0x82)
12669 FETCH_DATA (info
, codep
+ 1);
12670 modrm
.mod
= (*codep
>> 6) & 3;
12671 modrm
.reg
= (*codep
>> 3) & 7;
12672 modrm
.rm
= *codep
& 7;
12676 case USE_VEX_C5_TABLE
:
12678 FETCH_DATA (info
, codep
+ 2);
12679 /* All bits in the REX prefix are ignored. */
12681 rex
= (*codep
& 0x80) ? 0 : REX_R
;
12683 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12684 if (address_mode
!= mode_64bit
12685 && vex
.register_specifier
> 0x7)
12693 vex
.length
= (*codep
& 0x4) ? 256 : 128;
12694 switch ((*codep
& 0x3))
12700 vex
.prefix
= DATA_PREFIX_OPCODE
;
12703 vex
.prefix
= REPE_PREFIX_OPCODE
;
12706 vex
.prefix
= REPNE_PREFIX_OPCODE
;
12713 dp
= &vex_table
[dp
->op
[1].bytemode
][vindex
];
12715 /* There is no MODRM byte for VEX [82|77]. */
12716 if (vindex
!= 0x77 && vindex
!= 0x82)
12718 FETCH_DATA (info
, codep
+ 1);
12719 modrm
.mod
= (*codep
>> 6) & 3;
12720 modrm
.reg
= (*codep
>> 3) & 7;
12721 modrm
.rm
= *codep
& 7;
12725 case USE_VEX_W_TABLE
:
12729 dp
= &vex_w_table
[dp
->op
[1].bytemode
][vex
.w
? 1 : 0];
12732 case USE_EVEX_TABLE
:
12733 two_source_ops
= 0;
12736 FETCH_DATA (info
, codep
+ 4);
12737 /* All bits in the REX prefix are ignored. */
12739 /* The first byte after 0x62. */
12740 rex
= ~(*codep
>> 5) & 0x7;
12741 vex
.r
= *codep
& 0x10;
12742 switch ((*codep
& 0xf))
12745 return &bad_opcode
;
12747 vex_table_index
= EVEX_0F
;
12750 vex_table_index
= EVEX_0F38
;
12753 vex_table_index
= EVEX_0F3A
;
12757 /* The second byte after 0x62. */
12759 vex
.w
= *codep
& 0x80;
12760 if (vex
.w
&& address_mode
== mode_64bit
)
12763 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12764 if (address_mode
!= mode_64bit
)
12766 /* In 16/32-bit mode silently ignore following bits. */
12770 vex
.register_specifier
&= 0x7;
12774 if (!(*codep
& 0x4))
12775 return &bad_opcode
;
12777 switch ((*codep
& 0x3))
12783 vex
.prefix
= DATA_PREFIX_OPCODE
;
12786 vex
.prefix
= REPE_PREFIX_OPCODE
;
12789 vex
.prefix
= REPNE_PREFIX_OPCODE
;
12793 /* The third byte after 0x62. */
12796 /* Remember the static rounding bits. */
12797 vex
.ll
= (*codep
>> 5) & 3;
12798 vex
.b
= (*codep
& 0x10) != 0;
12800 vex
.v
= *codep
& 0x8;
12801 vex
.mask_register_specifier
= *codep
& 0x7;
12802 vex
.zeroing
= *codep
& 0x80;
12808 dp
= &evex_table
[vex_table_index
][vindex
];
12810 FETCH_DATA (info
, codep
+ 1);
12811 modrm
.mod
= (*codep
>> 6) & 3;
12812 modrm
.reg
= (*codep
>> 3) & 7;
12813 modrm
.rm
= *codep
& 7;
12815 /* Set vector length. */
12816 if (modrm
.mod
== 3 && vex
.b
)
12832 return &bad_opcode
;
12845 if (dp
->name
!= NULL
)
12848 return get_valid_dis386 (dp
, info
);
12852 get_sib (disassemble_info
*info
, int sizeflag
)
12854 /* If modrm.mod == 3, operand must be register. */
12856 && ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
12860 FETCH_DATA (info
, codep
+ 2);
12861 sib
.index
= (codep
[1] >> 3) & 7;
12862 sib
.scale
= (codep
[1] >> 6) & 3;
12863 sib
.base
= codep
[1] & 7;
12868 print_insn (bfd_vma pc
, disassemble_info
*info
)
12870 const struct dis386
*dp
;
12872 char *op_txt
[MAX_OPERANDS
];
12874 int sizeflag
, orig_sizeflag
;
12876 struct dis_private priv
;
12879 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
12880 if ((info
->mach
& bfd_mach_i386_i386
) != 0)
12881 address_mode
= mode_32bit
;
12882 else if (info
->mach
== bfd_mach_i386_i8086
)
12884 address_mode
= mode_16bit
;
12885 priv
.orig_sizeflag
= 0;
12888 address_mode
= mode_64bit
;
12890 if (intel_syntax
== (char) -1)
12891 intel_syntax
= (info
->mach
& bfd_mach_i386_intel_syntax
) != 0;
12893 for (p
= info
->disassembler_options
; p
!= NULL
; )
12895 if (CONST_STRNEQ (p
, "amd64"))
12897 else if (CONST_STRNEQ (p
, "intel64"))
12899 else if (CONST_STRNEQ (p
, "x86-64"))
12901 address_mode
= mode_64bit
;
12902 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
12904 else if (CONST_STRNEQ (p
, "i386"))
12906 address_mode
= mode_32bit
;
12907 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
12909 else if (CONST_STRNEQ (p
, "i8086"))
12911 address_mode
= mode_16bit
;
12912 priv
.orig_sizeflag
= 0;
12914 else if (CONST_STRNEQ (p
, "intel"))
12917 if (CONST_STRNEQ (p
+ 5, "-mnemonic"))
12918 intel_mnemonic
= 1;
12920 else if (CONST_STRNEQ (p
, "att"))
12923 if (CONST_STRNEQ (p
+ 3, "-mnemonic"))
12924 intel_mnemonic
= 0;
12926 else if (CONST_STRNEQ (p
, "addr"))
12928 if (address_mode
== mode_64bit
)
12930 if (p
[4] == '3' && p
[5] == '2')
12931 priv
.orig_sizeflag
&= ~AFLAG
;
12932 else if (p
[4] == '6' && p
[5] == '4')
12933 priv
.orig_sizeflag
|= AFLAG
;
12937 if (p
[4] == '1' && p
[5] == '6')
12938 priv
.orig_sizeflag
&= ~AFLAG
;
12939 else if (p
[4] == '3' && p
[5] == '2')
12940 priv
.orig_sizeflag
|= AFLAG
;
12943 else if (CONST_STRNEQ (p
, "data"))
12945 if (p
[4] == '1' && p
[5] == '6')
12946 priv
.orig_sizeflag
&= ~DFLAG
;
12947 else if (p
[4] == '3' && p
[5] == '2')
12948 priv
.orig_sizeflag
|= DFLAG
;
12950 else if (CONST_STRNEQ (p
, "suffix"))
12951 priv
.orig_sizeflag
|= SUFFIX_ALWAYS
;
12953 p
= strchr (p
, ',');
12960 names64
= intel_names64
;
12961 names32
= intel_names32
;
12962 names16
= intel_names16
;
12963 names8
= intel_names8
;
12964 names8rex
= intel_names8rex
;
12965 names_seg
= intel_names_seg
;
12966 names_mm
= intel_names_mm
;
12967 names_bnd
= intel_names_bnd
;
12968 names_xmm
= intel_names_xmm
;
12969 names_ymm
= intel_names_ymm
;
12970 names_zmm
= intel_names_zmm
;
12971 index64
= intel_index64
;
12972 index32
= intel_index32
;
12973 names_mask
= intel_names_mask
;
12974 index16
= intel_index16
;
12977 separator_char
= '+';
12982 names64
= att_names64
;
12983 names32
= att_names32
;
12984 names16
= att_names16
;
12985 names8
= att_names8
;
12986 names8rex
= att_names8rex
;
12987 names_seg
= att_names_seg
;
12988 names_mm
= att_names_mm
;
12989 names_bnd
= att_names_bnd
;
12990 names_xmm
= att_names_xmm
;
12991 names_ymm
= att_names_ymm
;
12992 names_zmm
= att_names_zmm
;
12993 index64
= att_index64
;
12994 index32
= att_index32
;
12995 names_mask
= att_names_mask
;
12996 index16
= att_index16
;
12999 separator_char
= ',';
13003 /* The output looks better if we put 7 bytes on a line, since that
13004 puts most long word instructions on a single line. Use 8 bytes
13006 if ((info
->mach
& bfd_mach_l1om
) != 0)
13007 info
->bytes_per_line
= 8;
13009 info
->bytes_per_line
= 7;
13011 info
->private_data
= &priv
;
13012 priv
.max_fetched
= priv
.the_buffer
;
13013 priv
.insn_start
= pc
;
13016 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13024 start_codep
= priv
.the_buffer
;
13025 codep
= priv
.the_buffer
;
13027 if (OPCODES_SIGSETJMP (priv
.bailout
) != 0)
13031 /* Getting here means we tried for data but didn't get it. That
13032 means we have an incomplete instruction of some sort. Just
13033 print the first byte as a prefix or a .byte pseudo-op. */
13034 if (codep
> priv
.the_buffer
)
13036 name
= prefix_name (priv
.the_buffer
[0], priv
.orig_sizeflag
);
13038 (*info
->fprintf_func
) (info
->stream
, "%s", name
);
13041 /* Just print the first byte as a .byte instruction. */
13042 (*info
->fprintf_func
) (info
->stream
, ".byte 0x%x",
13043 (unsigned int) priv
.the_buffer
[0]);
13053 sizeflag
= priv
.orig_sizeflag
;
13055 if (!ckprefix () || rex_used
)
13057 /* Too many prefixes or unused REX prefixes. */
13059 i
< (int) ARRAY_SIZE (all_prefixes
) && all_prefixes
[i
];
13061 (*info
->fprintf_func
) (info
->stream
, "%s%s",
13063 prefix_name (all_prefixes
[i
], sizeflag
));
13067 insn_codep
= codep
;
13069 FETCH_DATA (info
, codep
+ 1);
13070 two_source_ops
= (*codep
== 0x62) || (*codep
== 0xc8);
13072 if (((prefixes
& PREFIX_FWAIT
)
13073 && ((*codep
< 0xd8) || (*codep
> 0xdf))))
13075 /* Handle prefixes before fwait. */
13076 for (i
= 0; i
< fwait_prefix
&& all_prefixes
[i
];
13078 (*info
->fprintf_func
) (info
->stream
, "%s ",
13079 prefix_name (all_prefixes
[i
], sizeflag
));
13080 (*info
->fprintf_func
) (info
->stream
, "fwait");
13084 if (*codep
== 0x0f)
13086 unsigned char threebyte
;
13087 FETCH_DATA (info
, codep
+ 2);
13088 threebyte
= *++codep
;
13089 dp
= &dis386_twobyte
[threebyte
];
13090 need_modrm
= twobyte_has_modrm
[*codep
];
13095 dp
= &dis386
[*codep
];
13096 need_modrm
= onebyte_has_modrm
[*codep
];
13100 /* Save sizeflag for printing the extra prefixes later before updating
13101 it for mnemonic and operand processing. The prefix names depend
13102 only on the address mode. */
13103 orig_sizeflag
= sizeflag
;
13104 if (prefixes
& PREFIX_ADDR
)
13106 if ((prefixes
& PREFIX_DATA
))
13112 FETCH_DATA (info
, codep
+ 1);
13113 modrm
.mod
= (*codep
>> 6) & 3;
13114 modrm
.reg
= (*codep
>> 3) & 7;
13115 modrm
.rm
= *codep
& 7;
13123 if (dp
->name
== NULL
&& dp
->op
[0].bytemode
== FLOATCODE
)
13125 get_sib (info
, sizeflag
);
13126 dofloat (sizeflag
);
13130 dp
= get_valid_dis386 (dp
, info
);
13131 if (dp
!= NULL
&& putop (dp
->name
, sizeflag
) == 0)
13133 get_sib (info
, sizeflag
);
13134 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13137 op_ad
= MAX_OPERANDS
- 1 - i
;
13139 (*dp
->op
[i
].rtn
) (dp
->op
[i
].bytemode
, sizeflag
);
13140 /* For EVEX instruction after the last operand masking
13141 should be printed. */
13142 if (i
== 0 && vex
.evex
)
13144 /* Don't print {%k0}. */
13145 if (vex
.mask_register_specifier
)
13148 oappend (names_mask
[vex
.mask_register_specifier
]);
13158 /* Check if the REX prefix is used. */
13159 if (rex_ignored
== 0 && (rex
^ rex_used
) == 0 && last_rex_prefix
>= 0)
13160 all_prefixes
[last_rex_prefix
] = 0;
13162 /* Check if the SEG prefix is used. */
13163 if ((prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
| PREFIX_ES
13164 | PREFIX_FS
| PREFIX_GS
)) != 0
13165 && (used_prefixes
& active_seg_prefix
) != 0)
13166 all_prefixes
[last_seg_prefix
] = 0;
13168 /* Check if the ADDR prefix is used. */
13169 if ((prefixes
& PREFIX_ADDR
) != 0
13170 && (used_prefixes
& PREFIX_ADDR
) != 0)
13171 all_prefixes
[last_addr_prefix
] = 0;
13173 /* Check if the DATA prefix is used. */
13174 if ((prefixes
& PREFIX_DATA
) != 0
13175 && (used_prefixes
& PREFIX_DATA
) != 0)
13176 all_prefixes
[last_data_prefix
] = 0;
13178 /* Print the extra prefixes. */
13180 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
13181 if (all_prefixes
[i
])
13184 name
= prefix_name (all_prefixes
[i
], orig_sizeflag
);
13187 prefix_length
+= strlen (name
) + 1;
13188 (*info
->fprintf_func
) (info
->stream
, "%s ", name
);
13191 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
13192 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
13193 used by putop and MMX/SSE operand and may be overriden by the
13194 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
13196 if (dp
->prefix_requirement
== PREFIX_OPCODE
13197 && dp
!= &bad_opcode
13199 & (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0
13201 & (PREFIX_REPZ
| PREFIX_REPNZ
)) == 0)
13203 & (PREFIX_REPZ
| PREFIX_REPNZ
| PREFIX_DATA
))
13205 && (used_prefixes
& PREFIX_DATA
) == 0))))
13207 (*info
->fprintf_func
) (info
->stream
, "(bad)");
13208 return end_codep
- priv
.the_buffer
;
13211 /* Check maximum code length. */
13212 if ((codep
- start_codep
) > MAX_CODE_LENGTH
)
13214 (*info
->fprintf_func
) (info
->stream
, "(bad)");
13215 return MAX_CODE_LENGTH
;
13218 obufp
= mnemonicendp
;
13219 for (i
= strlen (obuf
) + prefix_length
; i
< 6; i
++)
13222 (*info
->fprintf_func
) (info
->stream
, "%s", obuf
);
13224 /* The enter and bound instructions are printed with operands in the same
13225 order as the intel book; everything else is printed in reverse order. */
13226 if (intel_syntax
|| two_source_ops
)
13230 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13231 op_txt
[i
] = op_out
[i
];
13233 if (intel_syntax
&& dp
&& dp
->op
[2].rtn
== OP_Rounding
13234 && dp
->op
[3].rtn
== OP_E
&& dp
->op
[4].rtn
== NULL
)
13236 op_txt
[2] = op_out
[3];
13237 op_txt
[3] = op_out
[2];
13240 for (i
= 0; i
< (MAX_OPERANDS
>> 1); ++i
)
13242 op_ad
= op_index
[i
];
13243 op_index
[i
] = op_index
[MAX_OPERANDS
- 1 - i
];
13244 op_index
[MAX_OPERANDS
- 1 - i
] = op_ad
;
13245 riprel
= op_riprel
[i
];
13246 op_riprel
[i
] = op_riprel
[MAX_OPERANDS
- 1 - i
];
13247 op_riprel
[MAX_OPERANDS
- 1 - i
] = riprel
;
13252 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13253 op_txt
[MAX_OPERANDS
- 1 - i
] = op_out
[i
];
13257 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13261 (*info
->fprintf_func
) (info
->stream
, ",");
13262 if (op_index
[i
] != -1 && !op_riprel
[i
])
13263 (*info
->print_address_func
) ((bfd_vma
) op_address
[op_index
[i
]], info
);
13265 (*info
->fprintf_func
) (info
->stream
, "%s", op_txt
[i
]);
13269 for (i
= 0; i
< MAX_OPERANDS
; i
++)
13270 if (op_index
[i
] != -1 && op_riprel
[i
])
13272 (*info
->fprintf_func
) (info
->stream
, " # ");
13273 (*info
->print_address_func
) ((bfd_vma
) (start_pc
+ codep
- start_codep
13274 + op_address
[op_index
[i
]]), info
);
13277 return codep
- priv
.the_buffer
;
13280 static const char *float_mem
[] = {
13355 static const unsigned char float_mem_mode
[] = {
13430 #define ST { OP_ST, 0 }
13431 #define STi { OP_STi, 0 }
13433 #define FGRPd9_2 NULL, { { NULL, 0 } }, 0
13434 #define FGRPd9_4 NULL, { { NULL, 1 } }, 0
13435 #define FGRPd9_5 NULL, { { NULL, 2 } }, 0
13436 #define FGRPd9_6 NULL, { { NULL, 3 } }, 0
13437 #define FGRPd9_7 NULL, { { NULL, 4 } }, 0
13438 #define FGRPda_5 NULL, { { NULL, 5 } }, 0
13439 #define FGRPdb_4 NULL, { { NULL, 6 } }, 0
13440 #define FGRPde_3 NULL, { { NULL, 7 } }, 0
13441 #define FGRPdf_4 NULL, { { NULL, 8 } }, 0
13443 static const struct dis386 float_reg
[][8] = {
13446 { "fadd", { ST
, STi
}, 0 },
13447 { "fmul", { ST
, STi
}, 0 },
13448 { "fcom", { STi
}, 0 },
13449 { "fcomp", { STi
}, 0 },
13450 { "fsub", { ST
, STi
}, 0 },
13451 { "fsubr", { ST
, STi
}, 0 },
13452 { "fdiv", { ST
, STi
}, 0 },
13453 { "fdivr", { ST
, STi
}, 0 },
13457 { "fld", { STi
}, 0 },
13458 { "fxch", { STi
}, 0 },
13468 { "fcmovb", { ST
, STi
}, 0 },
13469 { "fcmove", { ST
, STi
}, 0 },
13470 { "fcmovbe",{ ST
, STi
}, 0 },
13471 { "fcmovu", { ST
, STi
}, 0 },
13479 { "fcmovnb",{ ST
, STi
}, 0 },
13480 { "fcmovne",{ ST
, STi
}, 0 },
13481 { "fcmovnbe",{ ST
, STi
}, 0 },
13482 { "fcmovnu",{ ST
, STi
}, 0 },
13484 { "fucomi", { ST
, STi
}, 0 },
13485 { "fcomi", { ST
, STi
}, 0 },
13490 { "fadd", { STi
, ST
}, 0 },
13491 { "fmul", { STi
, ST
}, 0 },
13494 { "fsub!M", { STi
, ST
}, 0 },
13495 { "fsubM", { STi
, ST
}, 0 },
13496 { "fdiv!M", { STi
, ST
}, 0 },
13497 { "fdivM", { STi
, ST
}, 0 },
13501 { "ffree", { STi
}, 0 },
13503 { "fst", { STi
}, 0 },
13504 { "fstp", { STi
}, 0 },
13505 { "fucom", { STi
}, 0 },
13506 { "fucomp", { STi
}, 0 },
13512 { "faddp", { STi
, ST
}, 0 },
13513 { "fmulp", { STi
, ST
}, 0 },
13516 { "fsub!Mp", { STi
, ST
}, 0 },
13517 { "fsubMp", { STi
, ST
}, 0 },
13518 { "fdiv!Mp", { STi
, ST
}, 0 },
13519 { "fdivMp", { STi
, ST
}, 0 },
13523 { "ffreep", { STi
}, 0 },
13528 { "fucomip", { ST
, STi
}, 0 },
13529 { "fcomip", { ST
, STi
}, 0 },
13534 static char *fgrps
[][8] = {
13537 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13542 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13547 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13552 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13557 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13562 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13567 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13568 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13573 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13578 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13583 swap_operand (void)
13585 mnemonicendp
[0] = '.';
13586 mnemonicendp
[1] = 's';
13591 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED
,
13592 int sizeflag ATTRIBUTE_UNUSED
)
13594 /* Skip mod/rm byte. */
13600 dofloat (int sizeflag
)
13602 const struct dis386
*dp
;
13603 unsigned char floatop
;
13605 floatop
= codep
[-1];
13607 if (modrm
.mod
!= 3)
13609 int fp_indx
= (floatop
- 0xd8) * 8 + modrm
.reg
;
13611 putop (float_mem
[fp_indx
], sizeflag
);
13614 OP_E (float_mem_mode
[fp_indx
], sizeflag
);
13617 /* Skip mod/rm byte. */
13621 dp
= &float_reg
[floatop
- 0xd8][modrm
.reg
];
13622 if (dp
->name
== NULL
)
13624 putop (fgrps
[dp
->op
[0].bytemode
][modrm
.rm
], sizeflag
);
13626 /* Instruction fnstsw is only one with strange arg. */
13627 if (floatop
== 0xdf && codep
[-1] == 0xe0)
13628 strcpy (op_out
[0], names16
[0]);
13632 putop (dp
->name
, sizeflag
);
13637 (*dp
->op
[0].rtn
) (dp
->op
[0].bytemode
, sizeflag
);
13642 (*dp
->op
[1].rtn
) (dp
->op
[1].bytemode
, sizeflag
);
13646 /* Like oappend (below), but S is a string starting with '%'.
13647 In Intel syntax, the '%' is elided. */
13649 oappend_maybe_intel (const char *s
)
13651 oappend (s
+ intel_syntax
);
13655 OP_ST (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13657 oappend_maybe_intel ("%st");
13661 OP_STi (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13663 sprintf (scratchbuf
, "%%st(%d)", modrm
.rm
);
13664 oappend_maybe_intel (scratchbuf
);
13667 /* Capital letters in template are macros. */
13669 putop (const char *in_template
, int sizeflag
)
13674 unsigned int l
= 0, len
= 1;
13677 #define SAVE_LAST(c) \
13678 if (l < len && l < sizeof (last)) \
13683 for (p
= in_template
; *p
; p
++)
13700 while (*++p
!= '|')
13701 if (*p
== '}' || *p
== '\0')
13704 /* Fall through. */
13709 while (*++p
!= '}')
13720 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
13724 if (l
== 0 && len
== 1)
13729 if (sizeflag
& SUFFIX_ALWAYS
)
13742 if (address_mode
== mode_64bit
13743 && !(prefixes
& PREFIX_ADDR
))
13754 if (intel_syntax
&& !alt
)
13756 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
13758 if (sizeflag
& DFLAG
)
13759 *obufp
++ = intel_syntax
? 'd' : 'l';
13761 *obufp
++ = intel_syntax
? 'w' : 's';
13762 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13766 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
13769 if (modrm
.mod
== 3)
13775 if (sizeflag
& DFLAG
)
13776 *obufp
++ = intel_syntax
? 'd' : 'l';
13779 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13785 case 'E': /* For jcxz/jecxz */
13786 if (address_mode
== mode_64bit
)
13788 if (sizeflag
& AFLAG
)
13794 if (sizeflag
& AFLAG
)
13796 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
13801 if ((prefixes
& PREFIX_ADDR
) || (sizeflag
& SUFFIX_ALWAYS
))
13803 if (sizeflag
& AFLAG
)
13804 *obufp
++ = address_mode
== mode_64bit
? 'q' : 'l';
13806 *obufp
++ = address_mode
== mode_64bit
? 'l' : 'w';
13807 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
13811 if (intel_syntax
|| (obufp
[-1] != 's' && !(sizeflag
& SUFFIX_ALWAYS
)))
13813 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
13817 if (!(rex
& REX_W
))
13818 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13823 if ((prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_CS
13824 || (prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_DS
)
13826 used_prefixes
|= prefixes
& (PREFIX_CS
| PREFIX_DS
);
13829 if (prefixes
& PREFIX_DS
)
13848 if (l
!= 0 || len
!= 1)
13850 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
13855 if (!need_vex
|| !vex
.evex
)
13858 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
13860 switch (vex
.length
)
13878 if (address_mode
== mode_64bit
&& (sizeflag
& SUFFIX_ALWAYS
))
13883 /* Fall through. */
13886 if (l
!= 0 || len
!= 1)
13894 if (sizeflag
& SUFFIX_ALWAYS
)
13898 if (intel_mnemonic
!= cond
)
13902 if ((prefixes
& PREFIX_FWAIT
) == 0)
13905 used_prefixes
|= PREFIX_FWAIT
;
13911 else if (intel_syntax
&& (sizeflag
& DFLAG
))
13915 if (!(rex
& REX_W
))
13916 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13920 && address_mode
== mode_64bit
13921 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13926 /* Fall through. */
13929 if (l
== 0 && len
== 1)
13934 if ((rex
& REX_W
) == 0
13935 && (prefixes
& PREFIX_DATA
))
13937 if ((sizeflag
& DFLAG
) == 0)
13939 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13943 if ((prefixes
& PREFIX_DATA
)
13945 || (sizeflag
& SUFFIX_ALWAYS
))
13952 if (sizeflag
& DFLAG
)
13956 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13962 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
13968 if ((prefixes
& PREFIX_DATA
)
13970 || (sizeflag
& SUFFIX_ALWAYS
))
13977 if (sizeflag
& DFLAG
)
13978 *obufp
++ = intel_syntax
? 'd' : 'l';
13981 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13989 if (address_mode
== mode_64bit
13990 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13992 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
13996 /* Fall through. */
13999 if (l
== 0 && len
== 1)
14002 if (intel_syntax
&& !alt
)
14005 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
14011 if (sizeflag
& DFLAG
)
14012 *obufp
++ = intel_syntax
? 'd' : 'l';
14015 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14021 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
14027 || (modrm
.mod
== 3 && !(sizeflag
& SUFFIX_ALWAYS
)))
14042 else if (sizeflag
& DFLAG
)
14051 if (intel_syntax
&& !p
[1]
14052 && ((rex
& REX_W
) || (sizeflag
& DFLAG
)))
14054 if (!(rex
& REX_W
))
14055 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14058 if (l
== 0 && len
== 1)
14062 if (address_mode
== mode_64bit
14063 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14065 if (sizeflag
& SUFFIX_ALWAYS
)
14087 /* Fall through. */
14090 if (l
== 0 && len
== 1)
14095 if (sizeflag
& SUFFIX_ALWAYS
)
14101 if (sizeflag
& DFLAG
)
14105 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14119 if (address_mode
== mode_64bit
14120 && !(prefixes
& PREFIX_ADDR
))
14131 if (l
!= 0 || len
!= 1)
14136 if (need_vex
&& vex
.prefix
)
14138 if (vex
.prefix
== DATA_PREFIX_OPCODE
)
14145 if (prefixes
& PREFIX_DATA
)
14149 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14153 if (l
== 0 && len
== 1)
14155 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
14166 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
14174 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
14176 switch (vex
.length
)
14192 if (l
== 0 && len
== 1)
14194 /* operand size flag for cwtl, cbtw */
14203 else if (sizeflag
& DFLAG
)
14207 if (!(rex
& REX_W
))
14208 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14215 && last
[0] != 'L'))
14222 if (last
[0] == 'X')
14223 *obufp
++ = vex
.w
? 'd': 's';
14225 *obufp
++ = vex
.w
? 'q': 'd';
14231 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
14233 if (sizeflag
& DFLAG
)
14237 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14243 if (address_mode
== mode_64bit
14244 && (isa64
== intel64
14245 || ((sizeflag
& DFLAG
) || (rex
& REX_W
))))
14247 else if ((prefixes
& PREFIX_DATA
))
14249 if (!(sizeflag
& DFLAG
))
14251 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14258 mnemonicendp
= obufp
;
14263 oappend (const char *s
)
14265 obufp
= stpcpy (obufp
, s
);
14271 /* Only print the active segment register. */
14272 if (!active_seg_prefix
)
14275 used_prefixes
|= active_seg_prefix
;
14276 switch (active_seg_prefix
)
14279 oappend_maybe_intel ("%cs:");
14282 oappend_maybe_intel ("%ds:");
14285 oappend_maybe_intel ("%ss:");
14288 oappend_maybe_intel ("%es:");
14291 oappend_maybe_intel ("%fs:");
14294 oappend_maybe_intel ("%gs:");
14302 OP_indirE (int bytemode
, int sizeflag
)
14306 OP_E (bytemode
, sizeflag
);
14310 print_operand_value (char *buf
, int hex
, bfd_vma disp
)
14312 if (address_mode
== mode_64bit
)
14320 sprintf_vma (tmp
, disp
);
14321 for (i
= 0; tmp
[i
] == '0' && tmp
[i
+ 1]; i
++);
14322 strcpy (buf
+ 2, tmp
+ i
);
14326 bfd_signed_vma v
= disp
;
14333 /* Check for possible overflow on 0x8000000000000000. */
14336 strcpy (buf
, "9223372036854775808");
14350 tmp
[28 - i
] = (v
% 10) + '0';
14354 strcpy (buf
, tmp
+ 29 - i
);
14360 sprintf (buf
, "0x%x", (unsigned int) disp
);
14362 sprintf (buf
, "%d", (int) disp
);
14366 /* Put DISP in BUF as signed hex number. */
14369 print_displacement (char *buf
, bfd_vma disp
)
14371 bfd_signed_vma val
= disp
;
14380 /* Check for possible overflow. */
14383 switch (address_mode
)
14386 strcpy (buf
+ j
, "0x8000000000000000");
14389 strcpy (buf
+ j
, "0x80000000");
14392 strcpy (buf
+ j
, "0x8000");
14402 sprintf_vma (tmp
, (bfd_vma
) val
);
14403 for (i
= 0; tmp
[i
] == '0'; i
++)
14405 if (tmp
[i
] == '\0')
14407 strcpy (buf
+ j
, tmp
+ i
);
14411 intel_operand_size (int bytemode
, int sizeflag
)
14415 && (bytemode
== x_mode
14416 || bytemode
== evex_half_bcst_xmmq_mode
))
14419 oappend ("QWORD PTR ");
14421 oappend ("DWORD PTR ");
14430 oappend ("BYTE PTR ");
14435 case dqw_swap_mode
:
14436 oappend ("WORD PTR ");
14439 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14441 oappend ("QWORD PTR ");
14450 oappend ("QWORD PTR ");
14453 if ((sizeflag
& DFLAG
) || bytemode
== dq_mode
)
14454 oappend ("DWORD PTR ");
14456 oappend ("WORD PTR ");
14457 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14461 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
14463 oappend ("WORD PTR ");
14464 if (!(rex
& REX_W
))
14465 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14468 if (sizeflag
& DFLAG
)
14469 oappend ("QWORD PTR ");
14471 oappend ("DWORD PTR ");
14472 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14475 case d_scalar_mode
:
14476 case d_scalar_swap_mode
:
14479 oappend ("DWORD PTR ");
14482 case q_scalar_mode
:
14483 case q_scalar_swap_mode
:
14485 oappend ("QWORD PTR ");
14488 if (address_mode
== mode_64bit
)
14489 oappend ("QWORD PTR ");
14491 oappend ("DWORD PTR ");
14494 if (sizeflag
& DFLAG
)
14495 oappend ("FWORD PTR ");
14497 oappend ("DWORD PTR ");
14498 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14501 oappend ("TBYTE PTR ");
14505 case evex_x_gscat_mode
:
14506 case evex_x_nobcst_mode
:
14509 switch (vex
.length
)
14512 oappend ("XMMWORD PTR ");
14515 oappend ("YMMWORD PTR ");
14518 oappend ("ZMMWORD PTR ");
14525 oappend ("XMMWORD PTR ");
14528 oappend ("XMMWORD PTR ");
14531 oappend ("YMMWORD PTR ");
14534 case evex_half_bcst_xmmq_mode
:
14538 switch (vex
.length
)
14541 oappend ("QWORD PTR ");
14544 oappend ("XMMWORD PTR ");
14547 oappend ("YMMWORD PTR ");
14557 switch (vex
.length
)
14562 oappend ("BYTE PTR ");
14572 switch (vex
.length
)
14577 oappend ("WORD PTR ");
14587 switch (vex
.length
)
14592 oappend ("DWORD PTR ");
14602 switch (vex
.length
)
14607 oappend ("QWORD PTR ");
14617 switch (vex
.length
)
14620 oappend ("WORD PTR ");
14623 oappend ("DWORD PTR ");
14626 oappend ("QWORD PTR ");
14636 switch (vex
.length
)
14639 oappend ("DWORD PTR ");
14642 oappend ("QWORD PTR ");
14645 oappend ("XMMWORD PTR ");
14655 switch (vex
.length
)
14658 oappend ("QWORD PTR ");
14661 oappend ("YMMWORD PTR ");
14664 oappend ("ZMMWORD PTR ");
14674 switch (vex
.length
)
14678 oappend ("XMMWORD PTR ");
14685 oappend ("OWORD PTR ");
14688 case vex_w_dq_mode
:
14689 case vex_scalar_w_dq_mode
:
14694 oappend ("QWORD PTR ");
14696 oappend ("DWORD PTR ");
14698 case vex_vsib_d_w_dq_mode
:
14699 case vex_vsib_q_w_dq_mode
:
14706 oappend ("QWORD PTR ");
14708 oappend ("DWORD PTR ");
14712 switch (vex
.length
)
14715 oappend ("XMMWORD PTR ");
14718 oappend ("YMMWORD PTR ");
14721 oappend ("ZMMWORD PTR ");
14728 case vex_vsib_q_w_d_mode
:
14729 case vex_vsib_d_w_d_mode
:
14730 if (!need_vex
|| !vex
.evex
)
14733 switch (vex
.length
)
14736 oappend ("QWORD PTR ");
14739 oappend ("XMMWORD PTR ");
14742 oappend ("YMMWORD PTR ");
14750 if (!need_vex
|| vex
.length
!= 128)
14753 oappend ("DWORD PTR ");
14755 oappend ("BYTE PTR ");
14761 oappend ("QWORD PTR ");
14763 oappend ("WORD PTR ");
14772 OP_E_register (int bytemode
, int sizeflag
)
14774 int reg
= modrm
.rm
;
14775 const char **names
;
14781 if ((sizeflag
& SUFFIX_ALWAYS
)
14782 && (bytemode
== b_swap_mode
14783 || bytemode
== v_swap_mode
14784 || bytemode
== dqw_swap_mode
))
14810 names
= address_mode
== mode_64bit
? names64
: names32
;
14816 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14829 case dqw_swap_mode
:
14835 if ((sizeflag
& DFLAG
)
14836 || (bytemode
!= v_mode
14837 && bytemode
!= v_swap_mode
))
14841 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14846 names
= names_mask
;
14851 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14854 oappend (names
[reg
]);
14858 OP_E_memory (int bytemode
, int sizeflag
)
14861 int add
= (rex
& REX_B
) ? 8 : 0;
14867 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
14869 && bytemode
!= x_mode
14870 && bytemode
!= xmmq_mode
14871 && bytemode
!= evex_half_bcst_xmmq_mode
)
14880 case dqw_swap_mode
:
14887 case vex_vsib_d_w_dq_mode
:
14888 case vex_vsib_d_w_d_mode
:
14889 case vex_vsib_q_w_dq_mode
:
14890 case vex_vsib_q_w_d_mode
:
14891 case evex_x_gscat_mode
:
14893 shift
= vex
.w
? 3 : 2;
14896 case evex_half_bcst_xmmq_mode
:
14900 shift
= vex
.w
? 3 : 2;
14903 /* Fall through if vex.b == 0. */
14907 case evex_x_nobcst_mode
:
14909 switch (vex
.length
)
14932 case q_scalar_mode
:
14934 case q_scalar_swap_mode
:
14940 case d_scalar_mode
:
14942 case d_scalar_swap_mode
:
14954 /* Make necessary corrections to shift for modes that need it.
14955 For these modes we currently have shift 4, 5 or 6 depending on
14956 vex.length (it corresponds to xmmword, ymmword or zmmword
14957 operand). We might want to make it 3, 4 or 5 (e.g. for
14958 xmmq_mode). In case of broadcast enabled the corrections
14959 aren't needed, as element size is always 32 or 64 bits. */
14961 && (bytemode
== xmmq_mode
14962 || bytemode
== evex_half_bcst_xmmq_mode
))
14964 else if (bytemode
== xmmqd_mode
)
14966 else if (bytemode
== xmmdw_mode
)
14968 else if (bytemode
== ymmq_mode
&& vex
.length
== 128)
14976 intel_operand_size (bytemode
, sizeflag
);
14979 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
14981 /* 32/64 bit address mode */
14990 int addr32flag
= !((sizeflag
& AFLAG
)
14991 || bytemode
== v_bnd_mode
14992 || bytemode
== bnd_mode
);
14993 const char **indexes64
= names64
;
14994 const char **indexes32
= names32
;
15004 vindex
= sib
.index
;
15010 case vex_vsib_d_w_dq_mode
:
15011 case vex_vsib_d_w_d_mode
:
15012 case vex_vsib_q_w_dq_mode
:
15013 case vex_vsib_q_w_d_mode
:
15023 switch (vex
.length
)
15026 indexes64
= indexes32
= names_xmm
;
15030 || bytemode
== vex_vsib_q_w_dq_mode
15031 || bytemode
== vex_vsib_q_w_d_mode
)
15032 indexes64
= indexes32
= names_ymm
;
15034 indexes64
= indexes32
= names_xmm
;
15038 || bytemode
== vex_vsib_q_w_dq_mode
15039 || bytemode
== vex_vsib_q_w_d_mode
)
15040 indexes64
= indexes32
= names_zmm
;
15042 indexes64
= indexes32
= names_ymm
;
15049 haveindex
= vindex
!= 4;
15056 rbase
= base
+ add
;
15064 if (address_mode
== mode_64bit
&& !havesib
)
15070 FETCH_DATA (the_info
, codep
+ 1);
15072 if ((disp
& 0x80) != 0)
15074 if (vex
.evex
&& shift
> 0)
15082 /* In 32bit mode, we need index register to tell [offset] from
15083 [eiz*1 + offset]. */
15084 needindex
= (havesib
15087 && address_mode
== mode_32bit
);
15088 havedisp
= (havebase
15090 || (havesib
&& (haveindex
|| scale
!= 0)));
15093 if (modrm
.mod
!= 0 || base
== 5)
15095 if (havedisp
|| riprel
)
15096 print_displacement (scratchbuf
, disp
);
15098 print_operand_value (scratchbuf
, 1, disp
);
15099 oappend (scratchbuf
);
15103 oappend (sizeflag
& AFLAG
? "(%rip)" : "(%eip)");
15107 if ((havebase
|| haveindex
|| riprel
)
15108 && (bytemode
!= v_bnd_mode
)
15109 && (bytemode
!= bnd_mode
))
15110 used_prefixes
|= PREFIX_ADDR
;
15112 if (havedisp
|| (intel_syntax
&& riprel
))
15114 *obufp
++ = open_char
;
15115 if (intel_syntax
&& riprel
)
15118 oappend (sizeflag
& AFLAG
? "rip" : "eip");
15122 oappend (address_mode
== mode_64bit
&& !addr32flag
15123 ? names64
[rbase
] : names32
[rbase
]);
15126 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
15127 print index to tell base + index from base. */
15131 || (havebase
&& base
!= ESP_REG_NUM
))
15133 if (!intel_syntax
|| havebase
)
15135 *obufp
++ = separator_char
;
15139 oappend (address_mode
== mode_64bit
&& !addr32flag
15140 ? indexes64
[vindex
] : indexes32
[vindex
]);
15142 oappend (address_mode
== mode_64bit
&& !addr32flag
15143 ? index64
: index32
);
15145 *obufp
++ = scale_char
;
15147 sprintf (scratchbuf
, "%d", 1 << scale
);
15148 oappend (scratchbuf
);
15152 && (disp
|| modrm
.mod
!= 0 || base
== 5))
15154 if (!havedisp
|| (bfd_signed_vma
) disp
>= 0)
15159 else if (modrm
.mod
!= 1 && disp
!= -disp
)
15163 disp
= - (bfd_signed_vma
) disp
;
15167 print_displacement (scratchbuf
, disp
);
15169 print_operand_value (scratchbuf
, 1, disp
);
15170 oappend (scratchbuf
);
15173 *obufp
++ = close_char
;
15176 else if (intel_syntax
)
15178 if (modrm
.mod
!= 0 || base
== 5)
15180 if (!active_seg_prefix
)
15182 oappend (names_seg
[ds_reg
- es_reg
]);
15185 print_operand_value (scratchbuf
, 1, disp
);
15186 oappend (scratchbuf
);
15192 /* 16 bit address mode */
15193 used_prefixes
|= prefixes
& PREFIX_ADDR
;
15200 if ((disp
& 0x8000) != 0)
15205 FETCH_DATA (the_info
, codep
+ 1);
15207 if ((disp
& 0x80) != 0)
15212 if ((disp
& 0x8000) != 0)
15218 if (modrm
.mod
!= 0 || modrm
.rm
== 6)
15220 print_displacement (scratchbuf
, disp
);
15221 oappend (scratchbuf
);
15224 if (modrm
.mod
!= 0 || modrm
.rm
!= 6)
15226 *obufp
++ = open_char
;
15228 oappend (index16
[modrm
.rm
]);
15230 && (disp
|| modrm
.mod
!= 0 || modrm
.rm
== 6))
15232 if ((bfd_signed_vma
) disp
>= 0)
15237 else if (modrm
.mod
!= 1)
15241 disp
= - (bfd_signed_vma
) disp
;
15244 print_displacement (scratchbuf
, disp
);
15245 oappend (scratchbuf
);
15248 *obufp
++ = close_char
;
15251 else if (intel_syntax
)
15253 if (!active_seg_prefix
)
15255 oappend (names_seg
[ds_reg
- es_reg
]);
15258 print_operand_value (scratchbuf
, 1, disp
& 0xffff);
15259 oappend (scratchbuf
);
15262 if (vex
.evex
&& vex
.b
15263 && (bytemode
== x_mode
15264 || bytemode
== xmmq_mode
15265 || bytemode
== evex_half_bcst_xmmq_mode
))
15268 || bytemode
== xmmq_mode
15269 || bytemode
== evex_half_bcst_xmmq_mode
)
15271 switch (vex
.length
)
15274 oappend ("{1to2}");
15277 oappend ("{1to4}");
15280 oappend ("{1to8}");
15288 switch (vex
.length
)
15291 oappend ("{1to4}");
15294 oappend ("{1to8}");
15297 oappend ("{1to16}");
15307 OP_E (int bytemode
, int sizeflag
)
15309 /* Skip mod/rm byte. */
15313 if (modrm
.mod
== 3)
15314 OP_E_register (bytemode
, sizeflag
);
15316 OP_E_memory (bytemode
, sizeflag
);
15320 OP_G (int bytemode
, int sizeflag
)
15331 oappend (names8rex
[modrm
.reg
+ add
]);
15333 oappend (names8
[modrm
.reg
+ add
]);
15336 oappend (names16
[modrm
.reg
+ add
]);
15341 oappend (names32
[modrm
.reg
+ add
]);
15344 oappend (names64
[modrm
.reg
+ add
]);
15347 oappend (names_bnd
[modrm
.reg
]);
15354 case dqw_swap_mode
:
15357 oappend (names64
[modrm
.reg
+ add
]);
15360 if ((sizeflag
& DFLAG
) || bytemode
!= v_mode
)
15361 oappend (names32
[modrm
.reg
+ add
]);
15363 oappend (names16
[modrm
.reg
+ add
]);
15364 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15368 if (address_mode
== mode_64bit
)
15369 oappend (names64
[modrm
.reg
+ add
]);
15371 oappend (names32
[modrm
.reg
+ add
]);
15375 oappend (names_mask
[modrm
.reg
+ add
]);
15378 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15391 FETCH_DATA (the_info
, codep
+ 8);
15392 a
= *codep
++ & 0xff;
15393 a
|= (*codep
++ & 0xff) << 8;
15394 a
|= (*codep
++ & 0xff) << 16;
15395 a
|= (*codep
++ & 0xffu
) << 24;
15396 b
= *codep
++ & 0xff;
15397 b
|= (*codep
++ & 0xff) << 8;
15398 b
|= (*codep
++ & 0xff) << 16;
15399 b
|= (*codep
++ & 0xffu
) << 24;
15400 x
= a
+ ((bfd_vma
) b
<< 32);
15408 static bfd_signed_vma
15411 bfd_signed_vma x
= 0;
15413 FETCH_DATA (the_info
, codep
+ 4);
15414 x
= *codep
++ & (bfd_signed_vma
) 0xff;
15415 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
15416 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
15417 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
15421 static bfd_signed_vma
15424 bfd_signed_vma x
= 0;
15426 FETCH_DATA (the_info
, codep
+ 4);
15427 x
= *codep
++ & (bfd_signed_vma
) 0xff;
15428 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
15429 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
15430 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
15432 x
= (x
^ ((bfd_signed_vma
) 1 << 31)) - ((bfd_signed_vma
) 1 << 31);
15442 FETCH_DATA (the_info
, codep
+ 2);
15443 x
= *codep
++ & 0xff;
15444 x
|= (*codep
++ & 0xff) << 8;
15449 set_op (bfd_vma op
, int riprel
)
15451 op_index
[op_ad
] = op_ad
;
15452 if (address_mode
== mode_64bit
)
15454 op_address
[op_ad
] = op
;
15455 op_riprel
[op_ad
] = riprel
;
15459 /* Mask to get a 32-bit address. */
15460 op_address
[op_ad
] = op
& 0xffffffff;
15461 op_riprel
[op_ad
] = riprel
& 0xffffffff;
15466 OP_REG (int code
, int sizeflag
)
15473 case es_reg
: case ss_reg
: case cs_reg
:
15474 case ds_reg
: case fs_reg
: case gs_reg
:
15475 oappend (names_seg
[code
- es_reg
]);
15487 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
15488 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
15489 s
= names16
[code
- ax_reg
+ add
];
15491 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
15492 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
15495 s
= names8rex
[code
- al_reg
+ add
];
15497 s
= names8
[code
- al_reg
];
15499 case rAX_reg
: case rCX_reg
: case rDX_reg
: case rBX_reg
:
15500 case rSP_reg
: case rBP_reg
: case rSI_reg
: case rDI_reg
:
15501 if (address_mode
== mode_64bit
15502 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
15504 s
= names64
[code
- rAX_reg
+ add
];
15507 code
+= eAX_reg
- rAX_reg
;
15508 /* Fall through. */
15509 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
15510 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
15513 s
= names64
[code
- eAX_reg
+ add
];
15516 if (sizeflag
& DFLAG
)
15517 s
= names32
[code
- eAX_reg
+ add
];
15519 s
= names16
[code
- eAX_reg
+ add
];
15520 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15524 s
= INTERNAL_DISASSEMBLER_ERROR
;
15531 OP_IMREG (int code
, int sizeflag
)
15543 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
15544 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
15545 s
= names16
[code
- ax_reg
];
15547 case es_reg
: case ss_reg
: case cs_reg
:
15548 case ds_reg
: case fs_reg
: case gs_reg
:
15549 s
= names_seg
[code
- es_reg
];
15551 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
15552 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
15555 s
= names8rex
[code
- al_reg
];
15557 s
= names8
[code
- al_reg
];
15559 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
15560 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
15563 s
= names64
[code
- eAX_reg
];
15566 if (sizeflag
& DFLAG
)
15567 s
= names32
[code
- eAX_reg
];
15569 s
= names16
[code
- eAX_reg
];
15570 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15573 case z_mode_ax_reg
:
15574 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
15578 if (!(rex
& REX_W
))
15579 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15582 s
= INTERNAL_DISASSEMBLER_ERROR
;
15589 OP_I (int bytemode
, int sizeflag
)
15592 bfd_signed_vma mask
= -1;
15597 FETCH_DATA (the_info
, codep
+ 1);
15602 if (address_mode
== mode_64bit
)
15607 /* Fall through. */
15614 if (sizeflag
& DFLAG
)
15624 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15636 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15641 scratchbuf
[0] = '$';
15642 print_operand_value (scratchbuf
+ 1, 1, op
);
15643 oappend_maybe_intel (scratchbuf
);
15644 scratchbuf
[0] = '\0';
15648 OP_I64 (int bytemode
, int sizeflag
)
15651 bfd_signed_vma mask
= -1;
15653 if (address_mode
!= mode_64bit
)
15655 OP_I (bytemode
, sizeflag
);
15662 FETCH_DATA (the_info
, codep
+ 1);
15672 if (sizeflag
& DFLAG
)
15682 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15690 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15695 scratchbuf
[0] = '$';
15696 print_operand_value (scratchbuf
+ 1, 1, op
);
15697 oappend_maybe_intel (scratchbuf
);
15698 scratchbuf
[0] = '\0';
15702 OP_sI (int bytemode
, int sizeflag
)
15710 FETCH_DATA (the_info
, codep
+ 1);
15712 if ((op
& 0x80) != 0)
15714 if (bytemode
== b_T_mode
)
15716 if (address_mode
!= mode_64bit
15717 || !((sizeflag
& DFLAG
) || (rex
& REX_W
)))
15719 /* The operand-size prefix is overridden by a REX prefix. */
15720 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
15728 if (!(rex
& REX_W
))
15730 if (sizeflag
& DFLAG
)
15738 /* The operand-size prefix is overridden by a REX prefix. */
15739 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
15745 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15749 scratchbuf
[0] = '$';
15750 print_operand_value (scratchbuf
+ 1, 1, op
);
15751 oappend_maybe_intel (scratchbuf
);
15755 OP_J (int bytemode
, int sizeflag
)
15759 bfd_vma segment
= 0;
15764 FETCH_DATA (the_info
, codep
+ 1);
15766 if ((disp
& 0x80) != 0)
15770 if (isa64
== amd64
)
15772 if ((sizeflag
& DFLAG
)
15773 || (address_mode
== mode_64bit
15774 && (isa64
!= amd64
|| (rex
& REX_W
))))
15779 if ((disp
& 0x8000) != 0)
15781 /* In 16bit mode, address is wrapped around at 64k within
15782 the same segment. Otherwise, a data16 prefix on a jump
15783 instruction means that the pc is masked to 16 bits after
15784 the displacement is added! */
15786 if ((prefixes
& PREFIX_DATA
) == 0)
15787 segment
= ((start_pc
+ codep
- start_codep
)
15788 & ~((bfd_vma
) 0xffff));
15790 if (address_mode
!= mode_64bit
15791 || (isa64
== amd64
&& !(rex
& REX_W
)))
15792 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15795 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15798 disp
= ((start_pc
+ (codep
- start_codep
) + disp
) & mask
) | segment
;
15800 print_operand_value (scratchbuf
, 1, disp
);
15801 oappend (scratchbuf
);
15805 OP_SEG (int bytemode
, int sizeflag
)
15807 if (bytemode
== w_mode
)
15808 oappend (names_seg
[modrm
.reg
]);
15810 OP_E (modrm
.mod
== 3 ? bytemode
: w_mode
, sizeflag
);
15814 OP_DIR (int dummy ATTRIBUTE_UNUSED
, int sizeflag
)
15818 if (sizeflag
& DFLAG
)
15828 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15830 sprintf (scratchbuf
, "0x%x:0x%x", seg
, offset
);
15832 sprintf (scratchbuf
, "$0x%x,$0x%x", seg
, offset
);
15833 oappend (scratchbuf
);
15837 OP_OFF (int bytemode
, int sizeflag
)
15841 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
15842 intel_operand_size (bytemode
, sizeflag
);
15845 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
15852 if (!active_seg_prefix
)
15854 oappend (names_seg
[ds_reg
- es_reg
]);
15858 print_operand_value (scratchbuf
, 1, off
);
15859 oappend (scratchbuf
);
15863 OP_OFF64 (int bytemode
, int sizeflag
)
15867 if (address_mode
!= mode_64bit
15868 || (prefixes
& PREFIX_ADDR
))
15870 OP_OFF (bytemode
, sizeflag
);
15874 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
15875 intel_operand_size (bytemode
, sizeflag
);
15882 if (!active_seg_prefix
)
15884 oappend (names_seg
[ds_reg
- es_reg
]);
15888 print_operand_value (scratchbuf
, 1, off
);
15889 oappend (scratchbuf
);
15893 ptr_reg (int code
, int sizeflag
)
15897 *obufp
++ = open_char
;
15898 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
15899 if (address_mode
== mode_64bit
)
15901 if (!(sizeflag
& AFLAG
))
15902 s
= names32
[code
- eAX_reg
];
15904 s
= names64
[code
- eAX_reg
];
15906 else if (sizeflag
& AFLAG
)
15907 s
= names32
[code
- eAX_reg
];
15909 s
= names16
[code
- eAX_reg
];
15911 *obufp
++ = close_char
;
15916 OP_ESreg (int code
, int sizeflag
)
15922 case 0x6d: /* insw/insl */
15923 intel_operand_size (z_mode
, sizeflag
);
15925 case 0xa5: /* movsw/movsl/movsq */
15926 case 0xa7: /* cmpsw/cmpsl/cmpsq */
15927 case 0xab: /* stosw/stosl */
15928 case 0xaf: /* scasw/scasl */
15929 intel_operand_size (v_mode
, sizeflag
);
15932 intel_operand_size (b_mode
, sizeflag
);
15935 oappend_maybe_intel ("%es:");
15936 ptr_reg (code
, sizeflag
);
15940 OP_DSreg (int code
, int sizeflag
)
15946 case 0x6f: /* outsw/outsl */
15947 intel_operand_size (z_mode
, sizeflag
);
15949 case 0xa5: /* movsw/movsl/movsq */
15950 case 0xa7: /* cmpsw/cmpsl/cmpsq */
15951 case 0xad: /* lodsw/lodsl/lodsq */
15952 intel_operand_size (v_mode
, sizeflag
);
15955 intel_operand_size (b_mode
, sizeflag
);
15958 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15959 default segment register DS is printed. */
15960 if (!active_seg_prefix
)
15961 active_seg_prefix
= PREFIX_DS
;
15963 ptr_reg (code
, sizeflag
);
15967 OP_C (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15975 else if (address_mode
!= mode_64bit
&& (prefixes
& PREFIX_LOCK
))
15977 all_prefixes
[last_lock_prefix
] = 0;
15978 used_prefixes
|= PREFIX_LOCK
;
15983 sprintf (scratchbuf
, "%%cr%d", modrm
.reg
+ add
);
15984 oappend_maybe_intel (scratchbuf
);
15988 OP_D (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15997 sprintf (scratchbuf
, "db%d", modrm
.reg
+ add
);
15999 sprintf (scratchbuf
, "%%db%d", modrm
.reg
+ add
);
16000 oappend (scratchbuf
);
16004 OP_T (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16006 sprintf (scratchbuf
, "%%tr%d", modrm
.reg
);
16007 oappend_maybe_intel (scratchbuf
);
16011 OP_R (int bytemode
, int sizeflag
)
16013 /* Skip mod/rm byte. */
16016 OP_E_register (bytemode
, sizeflag
);
16020 OP_MMX (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16022 int reg
= modrm
.reg
;
16023 const char **names
;
16025 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16026 if (prefixes
& PREFIX_DATA
)
16035 oappend (names
[reg
]);
16039 OP_XMM (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16041 int reg
= modrm
.reg
;
16042 const char **names
;
16054 && bytemode
!= xmm_mode
16055 && bytemode
!= xmmq_mode
16056 && bytemode
!= evex_half_bcst_xmmq_mode
16057 && bytemode
!= ymm_mode
16058 && bytemode
!= scalar_mode
)
16060 switch (vex
.length
)
16067 || (bytemode
!= vex_vsib_q_w_dq_mode
16068 && bytemode
!= vex_vsib_q_w_d_mode
))
16080 else if (bytemode
== xmmq_mode
16081 || bytemode
== evex_half_bcst_xmmq_mode
)
16083 switch (vex
.length
)
16096 else if (bytemode
== ymm_mode
)
16100 oappend (names
[reg
]);
16104 OP_EM (int bytemode
, int sizeflag
)
16107 const char **names
;
16109 if (modrm
.mod
!= 3)
16112 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
16114 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
16115 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16117 OP_E (bytemode
, sizeflag
);
16121 if ((sizeflag
& SUFFIX_ALWAYS
) && bytemode
== v_swap_mode
)
16124 /* Skip mod/rm byte. */
16127 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16129 if (prefixes
& PREFIX_DATA
)
16138 oappend (names
[reg
]);
16141 /* cvt* are the only instructions in sse2 which have
16142 both SSE and MMX operands and also have 0x66 prefix
16143 in their opcode. 0x66 was originally used to differentiate
16144 between SSE and MMX instruction(operands). So we have to handle the
16145 cvt* separately using OP_EMC and OP_MXC */
16147 OP_EMC (int bytemode
, int sizeflag
)
16149 if (modrm
.mod
!= 3)
16151 if (intel_syntax
&& bytemode
== v_mode
)
16153 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
16154 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16156 OP_E (bytemode
, sizeflag
);
16160 /* Skip mod/rm byte. */
16163 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16164 oappend (names_mm
[modrm
.rm
]);
16168 OP_MXC (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16170 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16171 oappend (names_mm
[modrm
.reg
]);
16175 OP_EX (int bytemode
, int sizeflag
)
16178 const char **names
;
16180 /* Skip mod/rm byte. */
16184 if (modrm
.mod
!= 3)
16186 OP_E_memory (bytemode
, sizeflag
);
16201 if ((sizeflag
& SUFFIX_ALWAYS
)
16202 && (bytemode
== x_swap_mode
16203 || bytemode
== d_swap_mode
16204 || bytemode
== dqw_swap_mode
16205 || bytemode
== d_scalar_swap_mode
16206 || bytemode
== q_swap_mode
16207 || bytemode
== q_scalar_swap_mode
))
16211 && bytemode
!= xmm_mode
16212 && bytemode
!= xmmdw_mode
16213 && bytemode
!= xmmqd_mode
16214 && bytemode
!= xmm_mb_mode
16215 && bytemode
!= xmm_mw_mode
16216 && bytemode
!= xmm_md_mode
16217 && bytemode
!= xmm_mq_mode
16218 && bytemode
!= xmm_mdq_mode
16219 && bytemode
!= xmmq_mode
16220 && bytemode
!= evex_half_bcst_xmmq_mode
16221 && bytemode
!= ymm_mode
16222 && bytemode
!= d_scalar_mode
16223 && bytemode
!= d_scalar_swap_mode
16224 && bytemode
!= q_scalar_mode
16225 && bytemode
!= q_scalar_swap_mode
16226 && bytemode
!= vex_scalar_w_dq_mode
)
16228 switch (vex
.length
)
16243 else if (bytemode
== xmmq_mode
16244 || bytemode
== evex_half_bcst_xmmq_mode
)
16246 switch (vex
.length
)
16259 else if (bytemode
== ymm_mode
)
16263 oappend (names
[reg
]);
16267 OP_MS (int bytemode
, int sizeflag
)
16269 if (modrm
.mod
== 3)
16270 OP_EM (bytemode
, sizeflag
);
16276 OP_XS (int bytemode
, int sizeflag
)
16278 if (modrm
.mod
== 3)
16279 OP_EX (bytemode
, sizeflag
);
16285 OP_M (int bytemode
, int sizeflag
)
16287 if (modrm
.mod
== 3)
16288 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
16291 OP_E (bytemode
, sizeflag
);
16295 OP_0f07 (int bytemode
, int sizeflag
)
16297 if (modrm
.mod
!= 3 || modrm
.rm
!= 0)
16300 OP_E (bytemode
, sizeflag
);
16303 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
16304 32bit mode and "xchg %rax,%rax" in 64bit mode. */
16307 NOP_Fixup1 (int bytemode
, int sizeflag
)
16309 if ((prefixes
& PREFIX_DATA
) != 0
16312 && address_mode
== mode_64bit
))
16313 OP_REG (bytemode
, sizeflag
);
16315 strcpy (obuf
, "nop");
16319 NOP_Fixup2 (int bytemode
, int sizeflag
)
16321 if ((prefixes
& PREFIX_DATA
) != 0
16324 && address_mode
== mode_64bit
))
16325 OP_IMREG (bytemode
, sizeflag
);
16328 static const char *const Suffix3DNow
[] = {
16329 /* 00 */ NULL
, NULL
, NULL
, NULL
,
16330 /* 04 */ NULL
, NULL
, NULL
, NULL
,
16331 /* 08 */ NULL
, NULL
, NULL
, NULL
,
16332 /* 0C */ "pi2fw", "pi2fd", NULL
, NULL
,
16333 /* 10 */ NULL
, NULL
, NULL
, NULL
,
16334 /* 14 */ NULL
, NULL
, NULL
, NULL
,
16335 /* 18 */ NULL
, NULL
, NULL
, NULL
,
16336 /* 1C */ "pf2iw", "pf2id", NULL
, NULL
,
16337 /* 20 */ NULL
, NULL
, NULL
, NULL
,
16338 /* 24 */ NULL
, NULL
, NULL
, NULL
,
16339 /* 28 */ NULL
, NULL
, NULL
, NULL
,
16340 /* 2C */ NULL
, NULL
, NULL
, NULL
,
16341 /* 30 */ NULL
, NULL
, NULL
, NULL
,
16342 /* 34 */ NULL
, NULL
, NULL
, NULL
,
16343 /* 38 */ NULL
, NULL
, NULL
, NULL
,
16344 /* 3C */ NULL
, NULL
, NULL
, NULL
,
16345 /* 40 */ NULL
, NULL
, NULL
, NULL
,
16346 /* 44 */ NULL
, NULL
, NULL
, NULL
,
16347 /* 48 */ NULL
, NULL
, NULL
, NULL
,
16348 /* 4C */ NULL
, NULL
, NULL
, NULL
,
16349 /* 50 */ NULL
, NULL
, NULL
, NULL
,
16350 /* 54 */ NULL
, NULL
, NULL
, NULL
,
16351 /* 58 */ NULL
, NULL
, NULL
, NULL
,
16352 /* 5C */ NULL
, NULL
, NULL
, NULL
,
16353 /* 60 */ NULL
, NULL
, NULL
, NULL
,
16354 /* 64 */ NULL
, NULL
, NULL
, NULL
,
16355 /* 68 */ NULL
, NULL
, NULL
, NULL
,
16356 /* 6C */ NULL
, NULL
, NULL
, NULL
,
16357 /* 70 */ NULL
, NULL
, NULL
, NULL
,
16358 /* 74 */ NULL
, NULL
, NULL
, NULL
,
16359 /* 78 */ NULL
, NULL
, NULL
, NULL
,
16360 /* 7C */ NULL
, NULL
, NULL
, NULL
,
16361 /* 80 */ NULL
, NULL
, NULL
, NULL
,
16362 /* 84 */ NULL
, NULL
, NULL
, NULL
,
16363 /* 88 */ NULL
, NULL
, "pfnacc", NULL
,
16364 /* 8C */ NULL
, NULL
, "pfpnacc", NULL
,
16365 /* 90 */ "pfcmpge", NULL
, NULL
, NULL
,
16366 /* 94 */ "pfmin", NULL
, "pfrcp", "pfrsqrt",
16367 /* 98 */ NULL
, NULL
, "pfsub", NULL
,
16368 /* 9C */ NULL
, NULL
, "pfadd", NULL
,
16369 /* A0 */ "pfcmpgt", NULL
, NULL
, NULL
,
16370 /* A4 */ "pfmax", NULL
, "pfrcpit1", "pfrsqit1",
16371 /* A8 */ NULL
, NULL
, "pfsubr", NULL
,
16372 /* AC */ NULL
, NULL
, "pfacc", NULL
,
16373 /* B0 */ "pfcmpeq", NULL
, NULL
, NULL
,
16374 /* B4 */ "pfmul", NULL
, "pfrcpit2", "pmulhrw",
16375 /* B8 */ NULL
, NULL
, NULL
, "pswapd",
16376 /* BC */ NULL
, NULL
, NULL
, "pavgusb",
16377 /* C0 */ NULL
, NULL
, NULL
, NULL
,
16378 /* C4 */ NULL
, NULL
, NULL
, NULL
,
16379 /* C8 */ NULL
, NULL
, NULL
, NULL
,
16380 /* CC */ NULL
, NULL
, NULL
, NULL
,
16381 /* D0 */ NULL
, NULL
, NULL
, NULL
,
16382 /* D4 */ NULL
, NULL
, NULL
, NULL
,
16383 /* D8 */ NULL
, NULL
, NULL
, NULL
,
16384 /* DC */ NULL
, NULL
, NULL
, NULL
,
16385 /* E0 */ NULL
, NULL
, NULL
, NULL
,
16386 /* E4 */ NULL
, NULL
, NULL
, NULL
,
16387 /* E8 */ NULL
, NULL
, NULL
, NULL
,
16388 /* EC */ NULL
, NULL
, NULL
, NULL
,
16389 /* F0 */ NULL
, NULL
, NULL
, NULL
,
16390 /* F4 */ NULL
, NULL
, NULL
, NULL
,
16391 /* F8 */ NULL
, NULL
, NULL
, NULL
,
16392 /* FC */ NULL
, NULL
, NULL
, NULL
,
16396 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16398 const char *mnemonic
;
16400 FETCH_DATA (the_info
, codep
+ 1);
16401 /* AMD 3DNow! instructions are specified by an opcode suffix in the
16402 place where an 8-bit immediate would normally go. ie. the last
16403 byte of the instruction. */
16404 obufp
= mnemonicendp
;
16405 mnemonic
= Suffix3DNow
[*codep
++ & 0xff];
16407 oappend (mnemonic
);
16410 /* Since a variable sized modrm/sib chunk is between the start
16411 of the opcode (0x0f0f) and the opcode suffix, we need to do
16412 all the modrm processing first, and don't know until now that
16413 we have a bad opcode. This necessitates some cleaning up. */
16414 op_out
[0][0] = '\0';
16415 op_out
[1][0] = '\0';
16418 mnemonicendp
= obufp
;
16421 static struct op simd_cmp_op
[] =
16423 { STRING_COMMA_LEN ("eq") },
16424 { STRING_COMMA_LEN ("lt") },
16425 { STRING_COMMA_LEN ("le") },
16426 { STRING_COMMA_LEN ("unord") },
16427 { STRING_COMMA_LEN ("neq") },
16428 { STRING_COMMA_LEN ("nlt") },
16429 { STRING_COMMA_LEN ("nle") },
16430 { STRING_COMMA_LEN ("ord") }
16434 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16436 unsigned int cmp_type
;
16438 FETCH_DATA (the_info
, codep
+ 1);
16439 cmp_type
= *codep
++ & 0xff;
16440 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
))
16443 char *p
= mnemonicendp
- 2;
16447 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
16448 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
16452 /* We have a reserved extension byte. Output it directly. */
16453 scratchbuf
[0] = '$';
16454 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16455 oappend_maybe_intel (scratchbuf
);
16456 scratchbuf
[0] = '\0';
16461 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED
,
16462 int sizeflag ATTRIBUTE_UNUSED
)
16464 /* mwaitx %eax,%ecx,%ebx */
16467 const char **names
= (address_mode
== mode_64bit
16468 ? names64
: names32
);
16469 strcpy (op_out
[0], names
[0]);
16470 strcpy (op_out
[1], names
[1]);
16471 strcpy (op_out
[2], names
[3]);
16472 two_source_ops
= 1;
16474 /* Skip mod/rm byte. */
16480 OP_Mwait (int bytemode ATTRIBUTE_UNUSED
,
16481 int sizeflag ATTRIBUTE_UNUSED
)
16483 /* mwait %eax,%ecx */
16486 const char **names
= (address_mode
== mode_64bit
16487 ? names64
: names32
);
16488 strcpy (op_out
[0], names
[0]);
16489 strcpy (op_out
[1], names
[1]);
16490 two_source_ops
= 1;
16492 /* Skip mod/rm byte. */
16498 OP_Monitor (int bytemode ATTRIBUTE_UNUSED
,
16499 int sizeflag ATTRIBUTE_UNUSED
)
16501 /* monitor %eax,%ecx,%edx" */
16504 const char **op1_names
;
16505 const char **names
= (address_mode
== mode_64bit
16506 ? names64
: names32
);
16508 if (!(prefixes
& PREFIX_ADDR
))
16509 op1_names
= (address_mode
== mode_16bit
16510 ? names16
: names
);
16513 /* Remove "addr16/addr32". */
16514 all_prefixes
[last_addr_prefix
] = 0;
16515 op1_names
= (address_mode
!= mode_32bit
16516 ? names32
: names16
);
16517 used_prefixes
|= PREFIX_ADDR
;
16519 strcpy (op_out
[0], op1_names
[0]);
16520 strcpy (op_out
[1], names
[1]);
16521 strcpy (op_out
[2], names
[2]);
16522 two_source_ops
= 1;
16524 /* Skip mod/rm byte. */
16532 /* Throw away prefixes and 1st. opcode byte. */
16533 codep
= insn_codep
+ 1;
16538 REP_Fixup (int bytemode
, int sizeflag
)
16540 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16542 if (prefixes
& PREFIX_REPZ
)
16543 all_prefixes
[last_repz_prefix
] = REP_PREFIX
;
16550 OP_IMREG (bytemode
, sizeflag
);
16553 OP_ESreg (bytemode
, sizeflag
);
16556 OP_DSreg (bytemode
, sizeflag
);
16564 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16568 BND_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16570 if (prefixes
& PREFIX_REPNZ
)
16571 all_prefixes
[last_repnz_prefix
] = BND_PREFIX
;
16574 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
16575 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
16579 HLE_Fixup1 (int bytemode
, int sizeflag
)
16582 && (prefixes
& PREFIX_LOCK
) != 0)
16584 if (prefixes
& PREFIX_REPZ
)
16585 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
16586 if (prefixes
& PREFIX_REPNZ
)
16587 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
16590 OP_E (bytemode
, sizeflag
);
16593 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
16594 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
16598 HLE_Fixup2 (int bytemode
, int sizeflag
)
16600 if (modrm
.mod
!= 3)
16602 if (prefixes
& PREFIX_REPZ
)
16603 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
16604 if (prefixes
& PREFIX_REPNZ
)
16605 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
16608 OP_E (bytemode
, sizeflag
);
16611 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
16612 "xrelease" for memory operand. No check for LOCK prefix. */
16615 HLE_Fixup3 (int bytemode
, int sizeflag
)
16618 && last_repz_prefix
> last_repnz_prefix
16619 && (prefixes
& PREFIX_REPZ
) != 0)
16620 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
16622 OP_E (bytemode
, sizeflag
);
16626 CMPXCHG8B_Fixup (int bytemode
, int sizeflag
)
16631 /* Change cmpxchg8b to cmpxchg16b. */
16632 char *p
= mnemonicendp
- 2;
16633 mnemonicendp
= stpcpy (p
, "16b");
16636 else if ((prefixes
& PREFIX_LOCK
) != 0)
16638 if (prefixes
& PREFIX_REPZ
)
16639 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
16640 if (prefixes
& PREFIX_REPNZ
)
16641 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
16644 OP_M (bytemode
, sizeflag
);
16648 XMM_Fixup (int reg
, int sizeflag ATTRIBUTE_UNUSED
)
16650 const char **names
;
16654 switch (vex
.length
)
16668 oappend (names
[reg
]);
16672 CRC32_Fixup (int bytemode
, int sizeflag
)
16674 /* Add proper suffix to "crc32". */
16675 char *p
= mnemonicendp
;
16694 if (sizeflag
& DFLAG
)
16698 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16702 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16709 if (modrm
.mod
== 3)
16713 /* Skip mod/rm byte. */
16718 add
= (rex
& REX_B
) ? 8 : 0;
16719 if (bytemode
== b_mode
)
16723 oappend (names8rex
[modrm
.rm
+ add
]);
16725 oappend (names8
[modrm
.rm
+ add
]);
16731 oappend (names64
[modrm
.rm
+ add
]);
16732 else if ((prefixes
& PREFIX_DATA
))
16733 oappend (names16
[modrm
.rm
+ add
]);
16735 oappend (names32
[modrm
.rm
+ add
]);
16739 OP_E (bytemode
, sizeflag
);
16743 FXSAVE_Fixup (int bytemode
, int sizeflag
)
16745 /* Add proper suffix to "fxsave" and "fxrstor". */
16749 char *p
= mnemonicendp
;
16755 OP_M (bytemode
, sizeflag
);
16758 /* Display the destination register operand for instructions with
16762 OP_VEX (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16765 const char **names
;
16773 reg
= vex
.register_specifier
;
16780 if (bytemode
== vex_scalar_mode
)
16782 oappend (names_xmm
[reg
]);
16786 switch (vex
.length
)
16793 case vex_vsib_q_w_dq_mode
:
16794 case vex_vsib_q_w_d_mode
:
16805 names
= names_mask
;
16819 case vex_vsib_q_w_dq_mode
:
16820 case vex_vsib_q_w_d_mode
:
16821 names
= vex
.w
? names_ymm
: names_xmm
;
16825 names
= names_mask
;
16839 oappend (names
[reg
]);
16842 /* Get the VEX immediate byte without moving codep. */
16844 static unsigned char
16845 get_vex_imm8 (int sizeflag
, int opnum
)
16847 int bytes_before_imm
= 0;
16849 if (modrm
.mod
!= 3)
16851 /* There are SIB/displacement bytes. */
16852 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
16854 /* 32/64 bit address mode */
16855 int base
= modrm
.rm
;
16857 /* Check SIB byte. */
16860 FETCH_DATA (the_info
, codep
+ 1);
16862 /* When decoding the third source, don't increase
16863 bytes_before_imm as this has already been incremented
16864 by one in OP_E_memory while decoding the second
16867 bytes_before_imm
++;
16870 /* Don't increase bytes_before_imm when decoding the third source,
16871 it has already been incremented by OP_E_memory while decoding
16872 the second source operand. */
16878 /* When modrm.rm == 5 or modrm.rm == 4 and base in
16879 SIB == 5, there is a 4 byte displacement. */
16881 /* No displacement. */
16884 /* 4 byte displacement. */
16885 bytes_before_imm
+= 4;
16888 /* 1 byte displacement. */
16889 bytes_before_imm
++;
16896 /* 16 bit address mode */
16897 /* Don't increase bytes_before_imm when decoding the third source,
16898 it has already been incremented by OP_E_memory while decoding
16899 the second source operand. */
16905 /* When modrm.rm == 6, there is a 2 byte displacement. */
16907 /* No displacement. */
16910 /* 2 byte displacement. */
16911 bytes_before_imm
+= 2;
16914 /* 1 byte displacement: when decoding the third source,
16915 don't increase bytes_before_imm as this has already
16916 been incremented by one in OP_E_memory while decoding
16917 the second source operand. */
16919 bytes_before_imm
++;
16927 FETCH_DATA (the_info
, codep
+ bytes_before_imm
+ 1);
16928 return codep
[bytes_before_imm
];
16932 OP_EX_VexReg (int bytemode
, int sizeflag
, int reg
)
16934 const char **names
;
16936 if (reg
== -1 && modrm
.mod
!= 3)
16938 OP_E_memory (bytemode
, sizeflag
);
16950 else if (reg
> 7 && address_mode
!= mode_64bit
)
16954 switch (vex
.length
)
16965 oappend (names
[reg
]);
16969 OP_EX_VexImmW (int bytemode
, int sizeflag
)
16972 static unsigned char vex_imm8
;
16974 if (vex_w_done
== 0)
16978 /* Skip mod/rm byte. */
16982 vex_imm8
= get_vex_imm8 (sizeflag
, 0);
16985 reg
= vex_imm8
>> 4;
16987 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16989 else if (vex_w_done
== 1)
16994 reg
= vex_imm8
>> 4;
16996 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
17000 /* Output the imm8 directly. */
17001 scratchbuf
[0] = '$';
17002 print_operand_value (scratchbuf
+ 1, 1, vex_imm8
& 0xf);
17003 oappend_maybe_intel (scratchbuf
);
17004 scratchbuf
[0] = '\0';
17010 OP_Vex_2src (int bytemode
, int sizeflag
)
17012 if (modrm
.mod
== 3)
17014 int reg
= modrm
.rm
;
17018 oappend (names_xmm
[reg
]);
17023 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
17025 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
17026 used_prefixes
|= (prefixes
& PREFIX_DATA
);
17028 OP_E (bytemode
, sizeflag
);
17033 OP_Vex_2src_1 (int bytemode
, int sizeflag
)
17035 if (modrm
.mod
== 3)
17037 /* Skip mod/rm byte. */
17043 oappend (names_xmm
[vex
.register_specifier
]);
17045 OP_Vex_2src (bytemode
, sizeflag
);
17049 OP_Vex_2src_2 (int bytemode
, int sizeflag
)
17052 OP_Vex_2src (bytemode
, sizeflag
);
17054 oappend (names_xmm
[vex
.register_specifier
]);
17058 OP_EX_VexW (int bytemode
, int sizeflag
)
17066 /* Skip mod/rm byte. */
17071 reg
= get_vex_imm8 (sizeflag
, 0) >> 4;
17076 reg
= get_vex_imm8 (sizeflag
, 1) >> 4;
17079 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
17083 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED
,
17084 int sizeflag ATTRIBUTE_UNUSED
)
17086 /* Skip the immediate byte and check for invalid bits. */
17087 FETCH_DATA (the_info
, codep
+ 1);
17088 if (*codep
++ & 0xf)
17093 OP_REG_VexI4 (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
17096 const char **names
;
17098 FETCH_DATA (the_info
, codep
+ 1);
17101 if (bytemode
!= x_mode
)
17108 if (reg
> 7 && address_mode
!= mode_64bit
)
17111 switch (vex
.length
)
17122 oappend (names
[reg
]);
17126 OP_XMM_VexW (int bytemode
, int sizeflag
)
17128 /* Turn off the REX.W bit since it is used for swapping operands
17131 OP_XMM (bytemode
, sizeflag
);
17135 OP_EX_Vex (int bytemode
, int sizeflag
)
17137 if (modrm
.mod
!= 3)
17139 if (vex
.register_specifier
!= 0)
17143 OP_EX (bytemode
, sizeflag
);
17147 OP_XMM_Vex (int bytemode
, int sizeflag
)
17149 if (modrm
.mod
!= 3)
17151 if (vex
.register_specifier
!= 0)
17155 OP_XMM (bytemode
, sizeflag
);
17159 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
17161 switch (vex
.length
)
17164 mnemonicendp
= stpcpy (obuf
, "vzeroupper");
17167 mnemonicendp
= stpcpy (obuf
, "vzeroall");
17174 static struct op vex_cmp_op
[] =
17176 { STRING_COMMA_LEN ("eq") },
17177 { STRING_COMMA_LEN ("lt") },
17178 { STRING_COMMA_LEN ("le") },
17179 { STRING_COMMA_LEN ("unord") },
17180 { STRING_COMMA_LEN ("neq") },
17181 { STRING_COMMA_LEN ("nlt") },
17182 { STRING_COMMA_LEN ("nle") },
17183 { STRING_COMMA_LEN ("ord") },
17184 { STRING_COMMA_LEN ("eq_uq") },
17185 { STRING_COMMA_LEN ("nge") },
17186 { STRING_COMMA_LEN ("ngt") },
17187 { STRING_COMMA_LEN ("false") },
17188 { STRING_COMMA_LEN ("neq_oq") },
17189 { STRING_COMMA_LEN ("ge") },
17190 { STRING_COMMA_LEN ("gt") },
17191 { STRING_COMMA_LEN ("true") },
17192 { STRING_COMMA_LEN ("eq_os") },
17193 { STRING_COMMA_LEN ("lt_oq") },
17194 { STRING_COMMA_LEN ("le_oq") },
17195 { STRING_COMMA_LEN ("unord_s") },
17196 { STRING_COMMA_LEN ("neq_us") },
17197 { STRING_COMMA_LEN ("nlt_uq") },
17198 { STRING_COMMA_LEN ("nle_uq") },
17199 { STRING_COMMA_LEN ("ord_s") },
17200 { STRING_COMMA_LEN ("eq_us") },
17201 { STRING_COMMA_LEN ("nge_uq") },
17202 { STRING_COMMA_LEN ("ngt_uq") },
17203 { STRING_COMMA_LEN ("false_os") },
17204 { STRING_COMMA_LEN ("neq_os") },
17205 { STRING_COMMA_LEN ("ge_oq") },
17206 { STRING_COMMA_LEN ("gt_oq") },
17207 { STRING_COMMA_LEN ("true_us") },
17211 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
17213 unsigned int cmp_type
;
17215 FETCH_DATA (the_info
, codep
+ 1);
17216 cmp_type
= *codep
++ & 0xff;
17217 if (cmp_type
< ARRAY_SIZE (vex_cmp_op
))
17220 char *p
= mnemonicendp
- 2;
17224 sprintf (p
, "%s%s", vex_cmp_op
[cmp_type
].name
, suffix
);
17225 mnemonicendp
+= vex_cmp_op
[cmp_type
].len
;
17229 /* We have a reserved extension byte. Output it directly. */
17230 scratchbuf
[0] = '$';
17231 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
17232 oappend_maybe_intel (scratchbuf
);
17233 scratchbuf
[0] = '\0';
17238 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
,
17239 int sizeflag ATTRIBUTE_UNUSED
)
17241 unsigned int cmp_type
;
17246 FETCH_DATA (the_info
, codep
+ 1);
17247 cmp_type
= *codep
++ & 0xff;
17248 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
17249 If it's the case, print suffix, otherwise - print the immediate. */
17250 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
)
17255 char *p
= mnemonicendp
- 2;
17257 /* vpcmp* can have both one- and two-lettered suffix. */
17271 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
17272 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
17276 /* We have a reserved extension byte. Output it directly. */
17277 scratchbuf
[0] = '$';
17278 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
17279 oappend_maybe_intel (scratchbuf
);
17280 scratchbuf
[0] = '\0';
17284 static const struct op pclmul_op
[] =
17286 { STRING_COMMA_LEN ("lql") },
17287 { STRING_COMMA_LEN ("hql") },
17288 { STRING_COMMA_LEN ("lqh") },
17289 { STRING_COMMA_LEN ("hqh") }
17293 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED
,
17294 int sizeflag ATTRIBUTE_UNUSED
)
17296 unsigned int pclmul_type
;
17298 FETCH_DATA (the_info
, codep
+ 1);
17299 pclmul_type
= *codep
++ & 0xff;
17300 switch (pclmul_type
)
17311 if (pclmul_type
< ARRAY_SIZE (pclmul_op
))
17314 char *p
= mnemonicendp
- 3;
17319 sprintf (p
, "%s%s", pclmul_op
[pclmul_type
].name
, suffix
);
17320 mnemonicendp
+= pclmul_op
[pclmul_type
].len
;
17324 /* We have a reserved extension byte. Output it directly. */
17325 scratchbuf
[0] = '$';
17326 print_operand_value (scratchbuf
+ 1, 1, pclmul_type
);
17327 oappend_maybe_intel (scratchbuf
);
17328 scratchbuf
[0] = '\0';
17333 MOVBE_Fixup (int bytemode
, int sizeflag
)
17335 /* Add proper suffix to "movbe". */
17336 char *p
= mnemonicendp
;
17345 if (sizeflag
& SUFFIX_ALWAYS
)
17351 if (sizeflag
& DFLAG
)
17355 used_prefixes
|= (prefixes
& PREFIX_DATA
);
17360 oappend (INTERNAL_DISASSEMBLER_ERROR
);
17367 OP_M (bytemode
, sizeflag
);
17371 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
17374 const char **names
;
17376 /* Skip mod/rm byte. */
17390 oappend (names
[reg
]);
17394 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
17396 const char **names
;
17403 oappend (names
[vex
.register_specifier
]);
17407 OP_Mask (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
17410 || (bytemode
!= mask_mode
&& bytemode
!= mask_bd_mode
))
17414 if ((rex
& REX_R
) != 0 || !vex
.r
)
17420 oappend (names_mask
[modrm
.reg
]);
17424 OP_Rounding (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
17427 || (bytemode
!= evex_rounding_mode
17428 && bytemode
!= evex_sae_mode
))
17430 if (modrm
.mod
== 3 && vex
.b
)
17433 case evex_rounding_mode
:
17434 oappend (names_rounding
[vex
.ll
]);
17436 case evex_sae_mode
: