1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2020 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
36 #include "disassemble.h"
38 #include "opcode/i386.h"
39 #include "libiberty.h"
40 #include "safe-ctype.h"
44 static int print_insn (bfd_vma
, disassemble_info
*);
45 static void dofloat (int);
46 static void OP_ST (int, int);
47 static void OP_STi (int, int);
48 static int putop (const char *, int);
49 static void oappend (const char *);
50 static void append_seg (void);
51 static void OP_indirE (int, int);
52 static void print_operand_value (char *, int, bfd_vma
);
53 static void OP_E_register (int, int);
54 static void OP_E_memory (int, int);
55 static void print_displacement (char *, bfd_vma
);
56 static void OP_E (int, int);
57 static void OP_G (int, int);
58 static bfd_vma
get64 (void);
59 static bfd_signed_vma
get32 (void);
60 static bfd_signed_vma
get32s (void);
61 static int get16 (void);
62 static void set_op (bfd_vma
, int);
63 static void OP_Skip_MODRM (int, int);
64 static void OP_REG (int, int);
65 static void OP_IMREG (int, int);
66 static void OP_I (int, int);
67 static void OP_I64 (int, int);
68 static void OP_sI (int, int);
69 static void OP_J (int, int);
70 static void OP_SEG (int, int);
71 static void OP_DIR (int, int);
72 static void OP_OFF (int, int);
73 static void OP_OFF64 (int, int);
74 static void ptr_reg (int, int);
75 static void OP_ESreg (int, int);
76 static void OP_DSreg (int, int);
77 static void OP_C (int, int);
78 static void OP_D (int, int);
79 static void OP_T (int, int);
80 static void OP_MMX (int, int);
81 static void OP_XMM (int, int);
82 static void OP_EM (int, int);
83 static void OP_EX (int, int);
84 static void OP_EMC (int,int);
85 static void OP_MXC (int,int);
86 static void OP_MS (int, int);
87 static void OP_XS (int, int);
88 static void OP_M (int, int);
89 static void OP_VEX (int, int);
90 static void OP_VexR (int, int);
91 static void OP_VexW (int, int);
92 static void OP_Rounding (int, int);
93 static void OP_REG_VexI4 (int, int);
94 static void OP_VexI4 (int, int);
95 static void PCLMUL_Fixup (int, int);
96 static void VPCMP_Fixup (int, int);
97 static void VPCOM_Fixup (int, int);
98 static void OP_0f07 (int, int);
99 static void OP_Monitor (int, int);
100 static void OP_Mwait (int, int);
101 static void NOP_Fixup1 (int, int);
102 static void NOP_Fixup2 (int, int);
103 static void OP_3DNowSuffix (int, int);
104 static void CMP_Fixup (int, int);
105 static void BadOp (void);
106 static void REP_Fixup (int, int);
107 static void SEP_Fixup (int, int);
108 static void BND_Fixup (int, int);
109 static void NOTRACK_Fixup (int, int);
110 static void HLE_Fixup1 (int, int);
111 static void HLE_Fixup2 (int, int);
112 static void HLE_Fixup3 (int, int);
113 static void CMPXCHG8B_Fixup (int, int);
114 static void XMM_Fixup (int, int);
115 static void FXSAVE_Fixup (int, int);
117 static void MOVSXD_Fixup (int, int);
119 static void OP_Mask (int, int);
122 /* Points to first byte not fetched. */
123 bfd_byte
*max_fetched
;
124 bfd_byte the_buffer
[MAX_MNEM_SIZE
];
127 OPCODES_SIGJMP_BUF bailout
;
137 enum address_mode address_mode
;
139 /* Flags for the prefixes for the current instruction. See below. */
142 /* REX prefix the current instruction. See below. */
144 /* Bits of REX we've already used. */
146 /* Mark parts used in the REX prefix. When we are testing for
147 empty prefix (for 8bit register REX extension), just mask it
148 out. Otherwise test for REX bit is excuse for existence of REX
149 only in case value is nonzero. */
150 #define USED_REX(value) \
155 rex_used |= (value) | REX_OPCODE; \
158 rex_used |= REX_OPCODE; \
161 /* Flags for prefixes which we somehow handled when printing the
162 current instruction. */
163 static int used_prefixes
;
165 /* Flags stored in PREFIXES. */
166 #define PREFIX_REPZ 1
167 #define PREFIX_REPNZ 2
168 #define PREFIX_LOCK 4
170 #define PREFIX_SS 0x10
171 #define PREFIX_DS 0x20
172 #define PREFIX_ES 0x40
173 #define PREFIX_FS 0x80
174 #define PREFIX_GS 0x100
175 #define PREFIX_DATA 0x200
176 #define PREFIX_ADDR 0x400
177 #define PREFIX_FWAIT 0x800
179 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
180 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
182 #define FETCH_DATA(info, addr) \
183 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
184 ? 1 : fetch_data ((info), (addr)))
187 fetch_data (struct disassemble_info
*info
, bfd_byte
*addr
)
190 struct dis_private
*priv
= (struct dis_private
*) info
->private_data
;
191 bfd_vma start
= priv
->insn_start
+ (priv
->max_fetched
- priv
->the_buffer
);
193 if (addr
<= priv
->the_buffer
+ MAX_MNEM_SIZE
)
194 status
= (*info
->read_memory_func
) (start
,
196 addr
- priv
->max_fetched
,
202 /* If we did manage to read at least one byte, then
203 print_insn_i386 will do something sensible. Otherwise, print
204 an error. We do that here because this is where we know
206 if (priv
->max_fetched
== priv
->the_buffer
)
207 (*info
->memory_error_func
) (status
, start
, info
);
208 OPCODES_SIGLONGJMP (priv
->bailout
, 1);
211 priv
->max_fetched
= addr
;
215 /* Possible values for prefix requirement. */
216 #define PREFIX_IGNORED_SHIFT 16
217 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
218 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
219 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
220 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
221 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
223 /* Opcode prefixes. */
224 #define PREFIX_OPCODE (PREFIX_REPZ \
228 /* Prefixes ignored. */
229 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
230 | PREFIX_IGNORED_REPNZ \
231 | PREFIX_IGNORED_DATA)
233 #define XX { NULL, 0 }
234 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
236 #define Eb { OP_E, b_mode }
237 #define Ebnd { OP_E, bnd_mode }
238 #define EbS { OP_E, b_swap_mode }
239 #define EbndS { OP_E, bnd_swap_mode }
240 #define Ev { OP_E, v_mode }
241 #define Eva { OP_E, va_mode }
242 #define Ev_bnd { OP_E, v_bnd_mode }
243 #define EvS { OP_E, v_swap_mode }
244 #define Ed { OP_E, d_mode }
245 #define Edq { OP_E, dq_mode }
246 #define Edqw { OP_E, dqw_mode }
247 #define Edqb { OP_E, dqb_mode }
248 #define Edb { OP_E, db_mode }
249 #define Edw { OP_E, dw_mode }
250 #define Edqd { OP_E, dqd_mode }
251 #define Eq { OP_E, q_mode }
252 #define indirEv { OP_indirE, indir_v_mode }
253 #define indirEp { OP_indirE, f_mode }
254 #define stackEv { OP_E, stack_v_mode }
255 #define Em { OP_E, m_mode }
256 #define Ew { OP_E, w_mode }
257 #define M { OP_M, 0 } /* lea, lgdt, etc. */
258 #define Ma { OP_M, a_mode }
259 #define Mb { OP_M, b_mode }
260 #define Md { OP_M, d_mode }
261 #define Mo { OP_M, o_mode }
262 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
263 #define Mq { OP_M, q_mode }
264 #define Mv { OP_M, v_mode }
265 #define Mv_bnd { OP_M, v_bndmk_mode }
266 #define Mx { OP_M, x_mode }
267 #define Mxmm { OP_M, xmm_mode }
268 #define Gb { OP_G, b_mode }
269 #define Gbnd { OP_G, bnd_mode }
270 #define Gv { OP_G, v_mode }
271 #define Gd { OP_G, d_mode }
272 #define Gdq { OP_G, dq_mode }
273 #define Gm { OP_G, m_mode }
274 #define Gva { OP_G, va_mode }
275 #define Gw { OP_G, w_mode }
276 #define Ib { OP_I, b_mode }
277 #define sIb { OP_sI, b_mode } /* sign extened byte */
278 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
279 #define Iv { OP_I, v_mode }
280 #define sIv { OP_sI, v_mode }
281 #define Iv64 { OP_I64, v_mode }
282 #define Id { OP_I, d_mode }
283 #define Iw { OP_I, w_mode }
284 #define I1 { OP_I, const_1_mode }
285 #define Jb { OP_J, b_mode }
286 #define Jv { OP_J, v_mode }
287 #define Jdqw { OP_J, dqw_mode }
288 #define Cm { OP_C, m_mode }
289 #define Dm { OP_D, m_mode }
290 #define Td { OP_T, d_mode }
291 #define Skip_MODRM { OP_Skip_MODRM, 0 }
293 #define RMeAX { OP_REG, eAX_reg }
294 #define RMeBX { OP_REG, eBX_reg }
295 #define RMeCX { OP_REG, eCX_reg }
296 #define RMeDX { OP_REG, eDX_reg }
297 #define RMeSP { OP_REG, eSP_reg }
298 #define RMeBP { OP_REG, eBP_reg }
299 #define RMeSI { OP_REG, eSI_reg }
300 #define RMeDI { OP_REG, eDI_reg }
301 #define RMrAX { OP_REG, rAX_reg }
302 #define RMrBX { OP_REG, rBX_reg }
303 #define RMrCX { OP_REG, rCX_reg }
304 #define RMrDX { OP_REG, rDX_reg }
305 #define RMrSP { OP_REG, rSP_reg }
306 #define RMrBP { OP_REG, rBP_reg }
307 #define RMrSI { OP_REG, rSI_reg }
308 #define RMrDI { OP_REG, rDI_reg }
309 #define RMAL { OP_REG, al_reg }
310 #define RMCL { OP_REG, cl_reg }
311 #define RMDL { OP_REG, dl_reg }
312 #define RMBL { OP_REG, bl_reg }
313 #define RMAH { OP_REG, ah_reg }
314 #define RMCH { OP_REG, ch_reg }
315 #define RMDH { OP_REG, dh_reg }
316 #define RMBH { OP_REG, bh_reg }
317 #define RMAX { OP_REG, ax_reg }
318 #define RMDX { OP_REG, dx_reg }
320 #define eAX { OP_IMREG, eAX_reg }
321 #define AL { OP_IMREG, al_reg }
322 #define CL { OP_IMREG, cl_reg }
323 #define zAX { OP_IMREG, z_mode_ax_reg }
324 #define indirDX { OP_IMREG, indir_dx_reg }
326 #define Sw { OP_SEG, w_mode }
327 #define Sv { OP_SEG, v_mode }
328 #define Ap { OP_DIR, 0 }
329 #define Ob { OP_OFF64, b_mode }
330 #define Ov { OP_OFF64, v_mode }
331 #define Xb { OP_DSreg, eSI_reg }
332 #define Xv { OP_DSreg, eSI_reg }
333 #define Xz { OP_DSreg, eSI_reg }
334 #define Yb { OP_ESreg, eDI_reg }
335 #define Yv { OP_ESreg, eDI_reg }
336 #define DSBX { OP_DSreg, eBX_reg }
338 #define es { OP_REG, es_reg }
339 #define ss { OP_REG, ss_reg }
340 #define cs { OP_REG, cs_reg }
341 #define ds { OP_REG, ds_reg }
342 #define fs { OP_REG, fs_reg }
343 #define gs { OP_REG, gs_reg }
345 #define MX { OP_MMX, 0 }
346 #define XM { OP_XMM, 0 }
347 #define XMScalar { OP_XMM, scalar_mode }
348 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
349 #define XMM { OP_XMM, xmm_mode }
350 #define TMM { OP_XMM, tmm_mode }
351 #define XMxmmq { OP_XMM, xmmq_mode }
352 #define EM { OP_EM, v_mode }
353 #define EMS { OP_EM, v_swap_mode }
354 #define EMd { OP_EM, d_mode }
355 #define EMx { OP_EM, x_mode }
356 #define EXbwUnit { OP_EX, bw_unit_mode }
357 #define EXw { OP_EX, w_mode }
358 #define EXd { OP_EX, d_mode }
359 #define EXdS { OP_EX, d_swap_mode }
360 #define EXq { OP_EX, q_mode }
361 #define EXqS { OP_EX, q_swap_mode }
362 #define EXx { OP_EX, x_mode }
363 #define EXxS { OP_EX, x_swap_mode }
364 #define EXxmm { OP_EX, xmm_mode }
365 #define EXymm { OP_EX, ymm_mode }
366 #define EXtmm { OP_EX, tmm_mode }
367 #define EXxmmq { OP_EX, xmmq_mode }
368 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
369 #define EXxmm_mb { OP_EX, xmm_mb_mode }
370 #define EXxmm_mw { OP_EX, xmm_mw_mode }
371 #define EXxmm_md { OP_EX, xmm_md_mode }
372 #define EXxmm_mq { OP_EX, xmm_mq_mode }
373 #define EXxmmdw { OP_EX, xmmdw_mode }
374 #define EXxmmqd { OP_EX, xmmqd_mode }
375 #define EXymmq { OP_EX, ymmq_mode }
376 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
377 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
378 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
379 #define MS { OP_MS, v_mode }
380 #define XS { OP_XS, v_mode }
381 #define EMCq { OP_EMC, q_mode }
382 #define MXC { OP_MXC, 0 }
383 #define OPSUF { OP_3DNowSuffix, 0 }
384 #define SEP { SEP_Fixup, 0 }
385 #define CMP { CMP_Fixup, 0 }
386 #define XMM0 { XMM_Fixup, 0 }
387 #define FXSAVE { FXSAVE_Fixup, 0 }
389 #define Vex { OP_VEX, vex_mode }
390 #define VexW { OP_VexW, vex_mode }
391 #define VexScalar { OP_VEX, vex_scalar_mode }
392 #define VexScalarR { OP_VexR, vex_scalar_mode }
393 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
394 #define VexGdq { OP_VEX, dq_mode }
395 #define VexTmm { OP_VEX, tmm_mode }
396 #define XMVexI4 { OP_REG_VexI4, x_mode }
397 #define XMVexScalarI4 { OP_REG_VexI4, scalar_mode }
398 #define VexI4 { OP_VexI4, 0 }
399 #define PCLMUL { PCLMUL_Fixup, 0 }
400 #define VPCMP { VPCMP_Fixup, 0 }
401 #define VPCOM { VPCOM_Fixup, 0 }
403 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
404 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
405 #define EXxEVexS { OP_Rounding, evex_sae_mode }
407 #define XMask { OP_Mask, mask_mode }
408 #define MaskG { OP_G, mask_mode }
409 #define MaskE { OP_E, mask_mode }
410 #define MaskBDE { OP_E, mask_bd_mode }
411 #define MaskVex { OP_VEX, mask_mode }
413 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
414 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
415 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
416 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
418 #define MVexSIBMEM { OP_M, vex_sibmem_mode }
420 /* Used handle "rep" prefix for string instructions. */
421 #define Xbr { REP_Fixup, eSI_reg }
422 #define Xvr { REP_Fixup, eSI_reg }
423 #define Ybr { REP_Fixup, eDI_reg }
424 #define Yvr { REP_Fixup, eDI_reg }
425 #define Yzr { REP_Fixup, eDI_reg }
426 #define indirDXr { REP_Fixup, indir_dx_reg }
427 #define ALr { REP_Fixup, al_reg }
428 #define eAXr { REP_Fixup, eAX_reg }
430 /* Used handle HLE prefix for lockable instructions. */
431 #define Ebh1 { HLE_Fixup1, b_mode }
432 #define Evh1 { HLE_Fixup1, v_mode }
433 #define Ebh2 { HLE_Fixup2, b_mode }
434 #define Evh2 { HLE_Fixup2, v_mode }
435 #define Ebh3 { HLE_Fixup3, b_mode }
436 #define Evh3 { HLE_Fixup3, v_mode }
438 #define BND { BND_Fixup, 0 }
439 #define NOTRACK { NOTRACK_Fixup, 0 }
441 #define cond_jump_flag { NULL, cond_jump_mode }
442 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
444 /* bits in sizeflag */
445 #define SUFFIX_ALWAYS 4
453 /* byte operand with operand swapped */
455 /* byte operand, sign extend like 'T' suffix */
457 /* operand size depends on prefixes */
459 /* operand size depends on prefixes with operand swapped */
461 /* operand size depends on address prefix */
465 /* double word operand */
467 /* double word operand with operand swapped */
469 /* quad word operand */
471 /* quad word operand with operand swapped */
473 /* ten-byte operand */
475 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
476 broadcast enabled. */
478 /* Similar to x_mode, but with different EVEX mem shifts. */
480 /* Similar to x_mode, but with yet different EVEX mem shifts. */
482 /* Similar to x_mode, but with disabled broadcast. */
484 /* Similar to x_mode, but with operands swapped and disabled broadcast
487 /* 16-byte XMM operand */
489 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
490 memory operand (depending on vector length). Broadcast isn't
493 /* Same as xmmq_mode, but broadcast is allowed. */
494 evex_half_bcst_xmmq_mode
,
495 /* XMM register or byte memory operand */
497 /* XMM register or word memory operand */
499 /* XMM register or double word memory operand */
501 /* XMM register or quad word memory operand */
503 /* 16-byte XMM, word, double word or quad word operand. */
505 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
507 /* 32-byte YMM operand */
509 /* quad word, ymmword or zmmword memory operand. */
511 /* 32-byte YMM or 16-byte word operand */
515 /* d_mode in 32bit, q_mode in 64bit mode. */
517 /* pair of v_mode operands */
523 /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */
525 /* operand size depends on REX prefixes. */
527 /* registers like dq_mode, memory like w_mode, displacements like
528 v_mode without considering Intel64 ISA. */
532 /* bounds operand with operand swapped */
534 /* 4- or 6-byte pointer operand */
537 /* v_mode for indirect branch opcodes. */
539 /* v_mode for stack-related opcodes. */
541 /* non-quad operand size depends on prefixes */
543 /* 16-byte operand */
545 /* registers like dq_mode, memory like b_mode. */
547 /* registers like d_mode, memory like b_mode. */
549 /* registers like d_mode, memory like w_mode. */
551 /* registers like dq_mode, memory like d_mode. */
553 /* normal vex mode */
556 /* Operand size depends on the VEX.W bit, with VSIB dword indices. */
557 vex_vsib_d_w_dq_mode
,
558 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
560 /* Operand size depends on the VEX.W bit, with VSIB qword indices. */
561 vex_vsib_q_w_dq_mode
,
562 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
564 /* mandatory non-vector SIB. */
567 /* scalar, ignore vector length. */
569 /* like vex_mode, ignore vector length. */
571 /* Operand size depends on the VEX.W bit, ignore vector length. */
572 vex_scalar_w_dq_mode
,
574 /* Static rounding. */
576 /* Static rounding, 64-bit mode only. */
577 evex_rounding_64_mode
,
578 /* Supress all exceptions. */
581 /* Mask register operand. */
583 /* Mask register operand. */
651 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
653 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
654 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
655 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
656 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
657 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
658 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
659 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
660 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
661 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
662 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
663 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
664 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
665 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
666 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
667 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
668 #define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I))
706 REG_VEX_0F3849_X86_64_P_0_W_0_M_1
,
711 REG_0FXOP_09_12_M_1_L_0
,
789 MOD_VEX_0F3849_X86_64_P_0_W_0
,
790 MOD_VEX_0F3849_X86_64_P_2_W_0
,
791 MOD_VEX_0F3849_X86_64_P_3_W_0
,
792 MOD_VEX_0F384B_X86_64_P_1_W_0
,
793 MOD_VEX_0F384B_X86_64_P_2_W_0
,
794 MOD_VEX_0F384B_X86_64_P_3_W_0
,
795 MOD_VEX_0F385C_X86_64_P_1_W_0
,
796 MOD_VEX_0F385E_X86_64_P_0_W_0
,
797 MOD_VEX_0F385E_X86_64_P_1_W_0
,
798 MOD_VEX_0F385E_X86_64_P_2_W_0
,
799 MOD_VEX_0F385E_X86_64_P_3_W_0
,
809 MOD_VEX_0F12_PREFIX_0
,
810 MOD_VEX_0F12_PREFIX_2
,
812 MOD_VEX_0F16_PREFIX_0
,
813 MOD_VEX_0F16_PREFIX_2
,
816 MOD_VEX_W_0_0F41_P_0_LEN_1
,
817 MOD_VEX_W_1_0F41_P_0_LEN_1
,
818 MOD_VEX_W_0_0F41_P_2_LEN_1
,
819 MOD_VEX_W_1_0F41_P_2_LEN_1
,
820 MOD_VEX_W_0_0F42_P_0_LEN_1
,
821 MOD_VEX_W_1_0F42_P_0_LEN_1
,
822 MOD_VEX_W_0_0F42_P_2_LEN_1
,
823 MOD_VEX_W_1_0F42_P_2_LEN_1
,
824 MOD_VEX_W_0_0F44_P_0_LEN_1
,
825 MOD_VEX_W_1_0F44_P_0_LEN_1
,
826 MOD_VEX_W_0_0F44_P_2_LEN_1
,
827 MOD_VEX_W_1_0F44_P_2_LEN_1
,
828 MOD_VEX_W_0_0F45_P_0_LEN_1
,
829 MOD_VEX_W_1_0F45_P_0_LEN_1
,
830 MOD_VEX_W_0_0F45_P_2_LEN_1
,
831 MOD_VEX_W_1_0F45_P_2_LEN_1
,
832 MOD_VEX_W_0_0F46_P_0_LEN_1
,
833 MOD_VEX_W_1_0F46_P_0_LEN_1
,
834 MOD_VEX_W_0_0F46_P_2_LEN_1
,
835 MOD_VEX_W_1_0F46_P_2_LEN_1
,
836 MOD_VEX_W_0_0F47_P_0_LEN_1
,
837 MOD_VEX_W_1_0F47_P_0_LEN_1
,
838 MOD_VEX_W_0_0F47_P_2_LEN_1
,
839 MOD_VEX_W_1_0F47_P_2_LEN_1
,
840 MOD_VEX_W_0_0F4A_P_0_LEN_1
,
841 MOD_VEX_W_1_0F4A_P_0_LEN_1
,
842 MOD_VEX_W_0_0F4A_P_2_LEN_1
,
843 MOD_VEX_W_1_0F4A_P_2_LEN_1
,
844 MOD_VEX_W_0_0F4B_P_0_LEN_1
,
845 MOD_VEX_W_1_0F4B_P_0_LEN_1
,
846 MOD_VEX_W_0_0F4B_P_2_LEN_1
,
858 MOD_VEX_W_0_0F91_P_0_LEN_0
,
859 MOD_VEX_W_1_0F91_P_0_LEN_0
,
860 MOD_VEX_W_0_0F91_P_2_LEN_0
,
861 MOD_VEX_W_1_0F91_P_2_LEN_0
,
862 MOD_VEX_W_0_0F92_P_0_LEN_0
,
863 MOD_VEX_W_0_0F92_P_2_LEN_0
,
864 MOD_VEX_0F92_P_3_LEN_0
,
865 MOD_VEX_W_0_0F93_P_0_LEN_0
,
866 MOD_VEX_W_0_0F93_P_2_LEN_0
,
867 MOD_VEX_0F93_P_3_LEN_0
,
868 MOD_VEX_W_0_0F98_P_0_LEN_0
,
869 MOD_VEX_W_1_0F98_P_0_LEN_0
,
870 MOD_VEX_W_0_0F98_P_2_LEN_0
,
871 MOD_VEX_W_1_0F98_P_2_LEN_0
,
872 MOD_VEX_W_0_0F99_P_0_LEN_0
,
873 MOD_VEX_W_1_0F99_P_0_LEN_0
,
874 MOD_VEX_W_0_0F99_P_2_LEN_0
,
875 MOD_VEX_W_1_0F99_P_2_LEN_0
,
880 MOD_VEX_0FF0_PREFIX_3
,
897 MOD_EVEX_0F12_PREFIX_0
,
898 MOD_EVEX_0F12_PREFIX_2
,
900 MOD_EVEX_0F16_PREFIX_0
,
901 MOD_EVEX_0F16_PREFIX_2
,
909 MOD_EVEX_0F382A_P_1_W_1
,
911 MOD_EVEX_0F383A_P_1_W_0
,
919 MOD_EVEX_0F38C6_REG_1
,
920 MOD_EVEX_0F38C6_REG_2
,
921 MOD_EVEX_0F38C6_REG_5
,
922 MOD_EVEX_0F38C6_REG_6
,
923 MOD_EVEX_0F38C7_REG_1
,
924 MOD_EVEX_0F38C7_REG_2
,
925 MOD_EVEX_0F38C7_REG_5
,
926 MOD_EVEX_0F38C7_REG_6
939 RM_0F1E_P_1_MOD_3_REG_7
,
940 RM_0FAE_REG_6_MOD_3_P_0
,
942 RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0
948 PREFIX_0F01_REG_3_RM_1
,
949 PREFIX_0F01_REG_5_MOD_0
,
950 PREFIX_0F01_REG_5_MOD_3_RM_0
,
951 PREFIX_0F01_REG_5_MOD_3_RM_1
,
952 PREFIX_0F01_REG_5_MOD_3_RM_2
,
953 PREFIX_0F01_REG_7_MOD_3_RM_2
,
991 PREFIX_0FAE_REG_0_MOD_3
,
992 PREFIX_0FAE_REG_1_MOD_3
,
993 PREFIX_0FAE_REG_2_MOD_3
,
994 PREFIX_0FAE_REG_3_MOD_3
,
995 PREFIX_0FAE_REG_4_MOD_0
,
996 PREFIX_0FAE_REG_4_MOD_3
,
997 PREFIX_0FAE_REG_5_MOD_3
,
998 PREFIX_0FAE_REG_6_MOD_0
,
999 PREFIX_0FAE_REG_6_MOD_3
,
1000 PREFIX_0FAE_REG_7_MOD_0
,
1005 PREFIX_0FC7_REG_6_MOD_0
,
1006 PREFIX_0FC7_REG_6_MOD_3
,
1007 PREFIX_0FC7_REG_7_MOD_3
,
1062 PREFIX_VEX_0F3849_X86_64
,
1063 PREFIX_VEX_0F384B_X86_64
,
1064 PREFIX_VEX_0F385C_X86_64
,
1065 PREFIX_VEX_0F385E_X86_64
,
1176 THREE_BYTE_0F38
= 0,
1203 VEX_LEN_0F12_P_0_M_0
= 0,
1204 VEX_LEN_0F12_P_0_M_1
,
1205 #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0
1207 VEX_LEN_0F16_P_0_M_0
,
1208 VEX_LEN_0F16_P_0_M_1
,
1209 #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0
1245 VEX_LEN_0FAE_R_2_M_0
,
1246 VEX_LEN_0FAE_R_3_M_0
,
1256 VEX_LEN_0F3849_X86_64_P_0_W_0_M_0
,
1257 VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0
,
1258 VEX_LEN_0F3849_X86_64_P_2_W_0_M_0
,
1259 VEX_LEN_0F3849_X86_64_P_3_W_0_M_0
,
1260 VEX_LEN_0F384B_X86_64_P_1_W_0_M_0
,
1261 VEX_LEN_0F384B_X86_64_P_2_W_0_M_0
,
1262 VEX_LEN_0F384B_X86_64_P_3_W_0_M_0
,
1264 VEX_LEN_0F385C_X86_64_P_1_W_0_M_0
,
1265 VEX_LEN_0F385E_X86_64_P_0_W_0_M_0
,
1266 VEX_LEN_0F385E_X86_64_P_1_W_0_M_0
,
1267 VEX_LEN_0F385E_X86_64_P_2_W_0_M_0
,
1268 VEX_LEN_0F385E_X86_64_P_3_W_0_M_0
,
1308 VEX_LEN_0FXOP_08_85
,
1309 VEX_LEN_0FXOP_08_86
,
1310 VEX_LEN_0FXOP_08_87
,
1311 VEX_LEN_0FXOP_08_8E
,
1312 VEX_LEN_0FXOP_08_8F
,
1313 VEX_LEN_0FXOP_08_95
,
1314 VEX_LEN_0FXOP_08_96
,
1315 VEX_LEN_0FXOP_08_97
,
1316 VEX_LEN_0FXOP_08_9E
,
1317 VEX_LEN_0FXOP_08_9F
,
1318 VEX_LEN_0FXOP_08_A3
,
1319 VEX_LEN_0FXOP_08_A6
,
1320 VEX_LEN_0FXOP_08_B6
,
1321 VEX_LEN_0FXOP_08_C0
,
1322 VEX_LEN_0FXOP_08_C1
,
1323 VEX_LEN_0FXOP_08_C2
,
1324 VEX_LEN_0FXOP_08_C3
,
1325 VEX_LEN_0FXOP_08_CC
,
1326 VEX_LEN_0FXOP_08_CD
,
1327 VEX_LEN_0FXOP_08_CE
,
1328 VEX_LEN_0FXOP_08_CF
,
1329 VEX_LEN_0FXOP_08_EC
,
1330 VEX_LEN_0FXOP_08_ED
,
1331 VEX_LEN_0FXOP_08_EE
,
1332 VEX_LEN_0FXOP_08_EF
,
1333 VEX_LEN_0FXOP_09_01
,
1334 VEX_LEN_0FXOP_09_02
,
1335 VEX_LEN_0FXOP_09_12_M_1
,
1336 VEX_LEN_0FXOP_09_82_W_0
,
1337 VEX_LEN_0FXOP_09_83_W_0
,
1338 VEX_LEN_0FXOP_09_90
,
1339 VEX_LEN_0FXOP_09_91
,
1340 VEX_LEN_0FXOP_09_92
,
1341 VEX_LEN_0FXOP_09_93
,
1342 VEX_LEN_0FXOP_09_94
,
1343 VEX_LEN_0FXOP_09_95
,
1344 VEX_LEN_0FXOP_09_96
,
1345 VEX_LEN_0FXOP_09_97
,
1346 VEX_LEN_0FXOP_09_98
,
1347 VEX_LEN_0FXOP_09_99
,
1348 VEX_LEN_0FXOP_09_9A
,
1349 VEX_LEN_0FXOP_09_9B
,
1350 VEX_LEN_0FXOP_09_C1
,
1351 VEX_LEN_0FXOP_09_C2
,
1352 VEX_LEN_0FXOP_09_C3
,
1353 VEX_LEN_0FXOP_09_C6
,
1354 VEX_LEN_0FXOP_09_C7
,
1355 VEX_LEN_0FXOP_09_CB
,
1356 VEX_LEN_0FXOP_09_D1
,
1357 VEX_LEN_0FXOP_09_D2
,
1358 VEX_LEN_0FXOP_09_D3
,
1359 VEX_LEN_0FXOP_09_D6
,
1360 VEX_LEN_0FXOP_09_D7
,
1361 VEX_LEN_0FXOP_09_DB
,
1362 VEX_LEN_0FXOP_09_E1
,
1363 VEX_LEN_0FXOP_09_E2
,
1364 VEX_LEN_0FXOP_09_E3
,
1365 VEX_LEN_0FXOP_0A_12
,
1377 EVEX_LEN_0F3819_W_0
,
1378 EVEX_LEN_0F3819_W_1
,
1379 EVEX_LEN_0F381A_W_0_M_0
,
1380 EVEX_LEN_0F381A_W_1_M_0
,
1381 EVEX_LEN_0F381B_W_0_M_0
,
1382 EVEX_LEN_0F381B_W_1_M_0
,
1384 EVEX_LEN_0F385A_W_0_M_0
,
1385 EVEX_LEN_0F385A_W_1_M_0
,
1386 EVEX_LEN_0F385B_W_0_M_0
,
1387 EVEX_LEN_0F385B_W_1_M_0
,
1388 EVEX_LEN_0F38C6_R_1_M_0
,
1389 EVEX_LEN_0F38C6_R_2_M_0
,
1390 EVEX_LEN_0F38C6_R_5_M_0
,
1391 EVEX_LEN_0F38C6_R_6_M_0
,
1392 EVEX_LEN_0F38C7_R_1_M_0_W_0
,
1393 EVEX_LEN_0F38C7_R_1_M_0_W_1
,
1394 EVEX_LEN_0F38C7_R_2_M_0_W_0
,
1395 EVEX_LEN_0F38C7_R_2_M_0_W_1
,
1396 EVEX_LEN_0F38C7_R_5_M_0_W_0
,
1397 EVEX_LEN_0F38C7_R_5_M_0_W_1
,
1398 EVEX_LEN_0F38C7_R_6_M_0_W_0
,
1399 EVEX_LEN_0F38C7_R_6_M_0_W_1
,
1400 EVEX_LEN_0F3A00_W_1
,
1401 EVEX_LEN_0F3A01_W_1
,
1406 EVEX_LEN_0F3A18_W_0
,
1407 EVEX_LEN_0F3A18_W_1
,
1408 EVEX_LEN_0F3A19_W_0
,
1409 EVEX_LEN_0F3A19_W_1
,
1410 EVEX_LEN_0F3A1A_W_0
,
1411 EVEX_LEN_0F3A1A_W_1
,
1412 EVEX_LEN_0F3A1B_W_0
,
1413 EVEX_LEN_0F3A1B_W_1
,
1415 EVEX_LEN_0F3A21_W_0
,
1417 EVEX_LEN_0F3A23_W_0
,
1418 EVEX_LEN_0F3A23_W_1
,
1419 EVEX_LEN_0F3A38_W_0
,
1420 EVEX_LEN_0F3A38_W_1
,
1421 EVEX_LEN_0F3A39_W_0
,
1422 EVEX_LEN_0F3A39_W_1
,
1423 EVEX_LEN_0F3A3A_W_0
,
1424 EVEX_LEN_0F3A3A_W_1
,
1425 EVEX_LEN_0F3A3B_W_0
,
1426 EVEX_LEN_0F3A3B_W_1
,
1427 EVEX_LEN_0F3A43_W_0
,
1433 VEX_W_0F41_P_0_LEN_1
= 0,
1434 VEX_W_0F41_P_2_LEN_1
,
1435 VEX_W_0F42_P_0_LEN_1
,
1436 VEX_W_0F42_P_2_LEN_1
,
1437 VEX_W_0F44_P_0_LEN_0
,
1438 VEX_W_0F44_P_2_LEN_0
,
1439 VEX_W_0F45_P_0_LEN_1
,
1440 VEX_W_0F45_P_2_LEN_1
,
1441 VEX_W_0F46_P_0_LEN_1
,
1442 VEX_W_0F46_P_2_LEN_1
,
1443 VEX_W_0F47_P_0_LEN_1
,
1444 VEX_W_0F47_P_2_LEN_1
,
1445 VEX_W_0F4A_P_0_LEN_1
,
1446 VEX_W_0F4A_P_2_LEN_1
,
1447 VEX_W_0F4B_P_0_LEN_1
,
1448 VEX_W_0F4B_P_2_LEN_1
,
1449 VEX_W_0F90_P_0_LEN_0
,
1450 VEX_W_0F90_P_2_LEN_0
,
1451 VEX_W_0F91_P_0_LEN_0
,
1452 VEX_W_0F91_P_2_LEN_0
,
1453 VEX_W_0F92_P_0_LEN_0
,
1454 VEX_W_0F92_P_2_LEN_0
,
1455 VEX_W_0F93_P_0_LEN_0
,
1456 VEX_W_0F93_P_2_LEN_0
,
1457 VEX_W_0F98_P_0_LEN_0
,
1458 VEX_W_0F98_P_2_LEN_0
,
1459 VEX_W_0F99_P_0_LEN_0
,
1460 VEX_W_0F99_P_2_LEN_0
,
1469 VEX_W_0F381A_M_0_L_1
,
1476 VEX_W_0F3849_X86_64_P_0
,
1477 VEX_W_0F3849_X86_64_P_2
,
1478 VEX_W_0F3849_X86_64_P_3
,
1479 VEX_W_0F384B_X86_64_P_1
,
1480 VEX_W_0F384B_X86_64_P_2
,
1481 VEX_W_0F384B_X86_64_P_3
,
1484 VEX_W_0F385A_M_0_L_0
,
1485 VEX_W_0F385C_X86_64_P_1
,
1486 VEX_W_0F385E_X86_64_P_0
,
1487 VEX_W_0F385E_X86_64_P_1
,
1488 VEX_W_0F385E_X86_64_P_2
,
1489 VEX_W_0F385E_X86_64_P_3
,
1511 VEX_W_0FXOP_08_85_L_0
,
1512 VEX_W_0FXOP_08_86_L_0
,
1513 VEX_W_0FXOP_08_87_L_0
,
1514 VEX_W_0FXOP_08_8E_L_0
,
1515 VEX_W_0FXOP_08_8F_L_0
,
1516 VEX_W_0FXOP_08_95_L_0
,
1517 VEX_W_0FXOP_08_96_L_0
,
1518 VEX_W_0FXOP_08_97_L_0
,
1519 VEX_W_0FXOP_08_9E_L_0
,
1520 VEX_W_0FXOP_08_9F_L_0
,
1521 VEX_W_0FXOP_08_A6_L_0
,
1522 VEX_W_0FXOP_08_B6_L_0
,
1523 VEX_W_0FXOP_08_C0_L_0
,
1524 VEX_W_0FXOP_08_C1_L_0
,
1525 VEX_W_0FXOP_08_C2_L_0
,
1526 VEX_W_0FXOP_08_C3_L_0
,
1527 VEX_W_0FXOP_08_CC_L_0
,
1528 VEX_W_0FXOP_08_CD_L_0
,
1529 VEX_W_0FXOP_08_CE_L_0
,
1530 VEX_W_0FXOP_08_CF_L_0
,
1531 VEX_W_0FXOP_08_EC_L_0
,
1532 VEX_W_0FXOP_08_ED_L_0
,
1533 VEX_W_0FXOP_08_EE_L_0
,
1534 VEX_W_0FXOP_08_EF_L_0
,
1540 VEX_W_0FXOP_09_C1_L_0
,
1541 VEX_W_0FXOP_09_C2_L_0
,
1542 VEX_W_0FXOP_09_C3_L_0
,
1543 VEX_W_0FXOP_09_C6_L_0
,
1544 VEX_W_0FXOP_09_C7_L_0
,
1545 VEX_W_0FXOP_09_CB_L_0
,
1546 VEX_W_0FXOP_09_D1_L_0
,
1547 VEX_W_0FXOP_09_D2_L_0
,
1548 VEX_W_0FXOP_09_D3_L_0
,
1549 VEX_W_0FXOP_09_D6_L_0
,
1550 VEX_W_0FXOP_09_D7_L_0
,
1551 VEX_W_0FXOP_09_DB_L_0
,
1552 VEX_W_0FXOP_09_E1_L_0
,
1553 VEX_W_0FXOP_09_E2_L_0
,
1554 VEX_W_0FXOP_09_E3_L_0
,
1560 EVEX_W_0F12_P_0_M_1
,
1563 EVEX_W_0F16_P_0_M_1
,
1683 EVEX_W_0F38C7_R_1_M_0
,
1684 EVEX_W_0F38C7_R_2_M_0
,
1685 EVEX_W_0F38C7_R_5_M_0
,
1686 EVEX_W_0F38C7_R_6_M_0
,
1711 typedef void (*op_rtn
) (int bytemode
, int sizeflag
);
1720 unsigned int prefix_requirement
;
1723 /* Upper case letters in the instruction names here are macros.
1724 'A' => print 'b' if no register operands or suffix_always is true
1725 'B' => print 'b' if suffix_always is true
1726 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1728 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1729 suffix_always is true
1730 'E' => print 'e' if 32-bit form of jcxz
1731 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1732 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1733 'H' => print ",pt" or ",pn" branch hint
1736 'K' => print 'd' or 'q' if rex prefix is present.
1738 'M' => print 'r' if intel_mnemonic is false.
1739 'N' => print 'n' if instruction has no wait "prefix"
1740 'O' => print 'd' or 'o' (or 'q' in Intel mode)
1741 'P' => behave as 'T' except with register operand outside of suffix_always
1743 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1745 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1746 'S' => print 'w', 'l' or 'q' if suffix_always is true
1747 'T' => print 'w', 'l'/'d', or 'q' if instruction has an operand size
1748 prefix or if suffix_always is true.
1750 'V' => print 'q' in 64bit mode if instruction has no operand size
1751 prefix and behave as 'S' otherwise
1752 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1753 'X' => print 's', 'd' depending on data16 prefix (for XMM)
1755 'Z' => print 'q' in 64bit mode and 'l' otherwise, if suffix_always is true.
1756 '!' => change condition from true to false or from false to true.
1757 '%' => add 1 upper case letter to the macro.
1758 '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
1759 prefix or suffix_always is true (lcall/ljmp).
1760 '@' => in 64bit mode for Intel64 ISA or if instruction
1761 has no operand sizing prefix, print 'q' if suffix_always is true or
1762 nothing otherwise; behave as 'P' in all other cases
1764 2 upper case letter macros:
1765 "XY" => print 'x' or 'y' if suffix_always is true or no register
1766 operands and no broadcast.
1767 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
1768 register operands and no broadcast.
1769 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1770 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond
1771 being false, or no operand at all in 64bit mode, or if suffix_always
1773 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1774 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1775 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1776 "DQ" => print 'd' or 'q' depending on the VEX.W bit
1777 "BW" => print 'b' or 'w' depending on the VEX.W bit
1778 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
1779 an operand size prefix, or suffix_always is true. print
1780 'q' if rex prefix is present.
1782 Many of the above letters print nothing in Intel mode. See "putop"
1785 Braces '{' and '}', and vertical bars '|', indicate alternative
1786 mnemonic strings for AT&T and Intel. */
1788 static const struct dis386 dis386
[] = {
1790 { "addB", { Ebh1
, Gb
}, 0 },
1791 { "addS", { Evh1
, Gv
}, 0 },
1792 { "addB", { Gb
, EbS
}, 0 },
1793 { "addS", { Gv
, EvS
}, 0 },
1794 { "addB", { AL
, Ib
}, 0 },
1795 { "addS", { eAX
, Iv
}, 0 },
1796 { X86_64_TABLE (X86_64_06
) },
1797 { X86_64_TABLE (X86_64_07
) },
1799 { "orB", { Ebh1
, Gb
}, 0 },
1800 { "orS", { Evh1
, Gv
}, 0 },
1801 { "orB", { Gb
, EbS
}, 0 },
1802 { "orS", { Gv
, EvS
}, 0 },
1803 { "orB", { AL
, Ib
}, 0 },
1804 { "orS", { eAX
, Iv
}, 0 },
1805 { X86_64_TABLE (X86_64_0E
) },
1806 { Bad_Opcode
}, /* 0x0f extended opcode escape */
1808 { "adcB", { Ebh1
, Gb
}, 0 },
1809 { "adcS", { Evh1
, Gv
}, 0 },
1810 { "adcB", { Gb
, EbS
}, 0 },
1811 { "adcS", { Gv
, EvS
}, 0 },
1812 { "adcB", { AL
, Ib
}, 0 },
1813 { "adcS", { eAX
, Iv
}, 0 },
1814 { X86_64_TABLE (X86_64_16
) },
1815 { X86_64_TABLE (X86_64_17
) },
1817 { "sbbB", { Ebh1
, Gb
}, 0 },
1818 { "sbbS", { Evh1
, Gv
}, 0 },
1819 { "sbbB", { Gb
, EbS
}, 0 },
1820 { "sbbS", { Gv
, EvS
}, 0 },
1821 { "sbbB", { AL
, Ib
}, 0 },
1822 { "sbbS", { eAX
, Iv
}, 0 },
1823 { X86_64_TABLE (X86_64_1E
) },
1824 { X86_64_TABLE (X86_64_1F
) },
1826 { "andB", { Ebh1
, Gb
}, 0 },
1827 { "andS", { Evh1
, Gv
}, 0 },
1828 { "andB", { Gb
, EbS
}, 0 },
1829 { "andS", { Gv
, EvS
}, 0 },
1830 { "andB", { AL
, Ib
}, 0 },
1831 { "andS", { eAX
, Iv
}, 0 },
1832 { Bad_Opcode
}, /* SEG ES prefix */
1833 { X86_64_TABLE (X86_64_27
) },
1835 { "subB", { Ebh1
, Gb
}, 0 },
1836 { "subS", { Evh1
, Gv
}, 0 },
1837 { "subB", { Gb
, EbS
}, 0 },
1838 { "subS", { Gv
, EvS
}, 0 },
1839 { "subB", { AL
, Ib
}, 0 },
1840 { "subS", { eAX
, Iv
}, 0 },
1841 { Bad_Opcode
}, /* SEG CS prefix */
1842 { X86_64_TABLE (X86_64_2F
) },
1844 { "xorB", { Ebh1
, Gb
}, 0 },
1845 { "xorS", { Evh1
, Gv
}, 0 },
1846 { "xorB", { Gb
, EbS
}, 0 },
1847 { "xorS", { Gv
, EvS
}, 0 },
1848 { "xorB", { AL
, Ib
}, 0 },
1849 { "xorS", { eAX
, Iv
}, 0 },
1850 { Bad_Opcode
}, /* SEG SS prefix */
1851 { X86_64_TABLE (X86_64_37
) },
1853 { "cmpB", { Eb
, Gb
}, 0 },
1854 { "cmpS", { Ev
, Gv
}, 0 },
1855 { "cmpB", { Gb
, EbS
}, 0 },
1856 { "cmpS", { Gv
, EvS
}, 0 },
1857 { "cmpB", { AL
, Ib
}, 0 },
1858 { "cmpS", { eAX
, Iv
}, 0 },
1859 { Bad_Opcode
}, /* SEG DS prefix */
1860 { X86_64_TABLE (X86_64_3F
) },
1862 { "inc{S|}", { RMeAX
}, 0 },
1863 { "inc{S|}", { RMeCX
}, 0 },
1864 { "inc{S|}", { RMeDX
}, 0 },
1865 { "inc{S|}", { RMeBX
}, 0 },
1866 { "inc{S|}", { RMeSP
}, 0 },
1867 { "inc{S|}", { RMeBP
}, 0 },
1868 { "inc{S|}", { RMeSI
}, 0 },
1869 { "inc{S|}", { RMeDI
}, 0 },
1871 { "dec{S|}", { RMeAX
}, 0 },
1872 { "dec{S|}", { RMeCX
}, 0 },
1873 { "dec{S|}", { RMeDX
}, 0 },
1874 { "dec{S|}", { RMeBX
}, 0 },
1875 { "dec{S|}", { RMeSP
}, 0 },
1876 { "dec{S|}", { RMeBP
}, 0 },
1877 { "dec{S|}", { RMeSI
}, 0 },
1878 { "dec{S|}", { RMeDI
}, 0 },
1880 { "pushV", { RMrAX
}, 0 },
1881 { "pushV", { RMrCX
}, 0 },
1882 { "pushV", { RMrDX
}, 0 },
1883 { "pushV", { RMrBX
}, 0 },
1884 { "pushV", { RMrSP
}, 0 },
1885 { "pushV", { RMrBP
}, 0 },
1886 { "pushV", { RMrSI
}, 0 },
1887 { "pushV", { RMrDI
}, 0 },
1889 { "popV", { RMrAX
}, 0 },
1890 { "popV", { RMrCX
}, 0 },
1891 { "popV", { RMrDX
}, 0 },
1892 { "popV", { RMrBX
}, 0 },
1893 { "popV", { RMrSP
}, 0 },
1894 { "popV", { RMrBP
}, 0 },
1895 { "popV", { RMrSI
}, 0 },
1896 { "popV", { RMrDI
}, 0 },
1898 { X86_64_TABLE (X86_64_60
) },
1899 { X86_64_TABLE (X86_64_61
) },
1900 { X86_64_TABLE (X86_64_62
) },
1901 { X86_64_TABLE (X86_64_63
) },
1902 { Bad_Opcode
}, /* seg fs */
1903 { Bad_Opcode
}, /* seg gs */
1904 { Bad_Opcode
}, /* op size prefix */
1905 { Bad_Opcode
}, /* adr size prefix */
1907 { "pushP", { sIv
}, 0 },
1908 { "imulS", { Gv
, Ev
, Iv
}, 0 },
1909 { "pushP", { sIbT
}, 0 },
1910 { "imulS", { Gv
, Ev
, sIb
}, 0 },
1911 { "ins{b|}", { Ybr
, indirDX
}, 0 },
1912 { X86_64_TABLE (X86_64_6D
) },
1913 { "outs{b|}", { indirDXr
, Xb
}, 0 },
1914 { X86_64_TABLE (X86_64_6F
) },
1916 { "joH", { Jb
, BND
, cond_jump_flag
}, 0 },
1917 { "jnoH", { Jb
, BND
, cond_jump_flag
}, 0 },
1918 { "jbH", { Jb
, BND
, cond_jump_flag
}, 0 },
1919 { "jaeH", { Jb
, BND
, cond_jump_flag
}, 0 },
1920 { "jeH", { Jb
, BND
, cond_jump_flag
}, 0 },
1921 { "jneH", { Jb
, BND
, cond_jump_flag
}, 0 },
1922 { "jbeH", { Jb
, BND
, cond_jump_flag
}, 0 },
1923 { "jaH", { Jb
, BND
, cond_jump_flag
}, 0 },
1925 { "jsH", { Jb
, BND
, cond_jump_flag
}, 0 },
1926 { "jnsH", { Jb
, BND
, cond_jump_flag
}, 0 },
1927 { "jpH", { Jb
, BND
, cond_jump_flag
}, 0 },
1928 { "jnpH", { Jb
, BND
, cond_jump_flag
}, 0 },
1929 { "jlH", { Jb
, BND
, cond_jump_flag
}, 0 },
1930 { "jgeH", { Jb
, BND
, cond_jump_flag
}, 0 },
1931 { "jleH", { Jb
, BND
, cond_jump_flag
}, 0 },
1932 { "jgH", { Jb
, BND
, cond_jump_flag
}, 0 },
1934 { REG_TABLE (REG_80
) },
1935 { REG_TABLE (REG_81
) },
1936 { X86_64_TABLE (X86_64_82
) },
1937 { REG_TABLE (REG_83
) },
1938 { "testB", { Eb
, Gb
}, 0 },
1939 { "testS", { Ev
, Gv
}, 0 },
1940 { "xchgB", { Ebh2
, Gb
}, 0 },
1941 { "xchgS", { Evh2
, Gv
}, 0 },
1943 { "movB", { Ebh3
, Gb
}, 0 },
1944 { "movS", { Evh3
, Gv
}, 0 },
1945 { "movB", { Gb
, EbS
}, 0 },
1946 { "movS", { Gv
, EvS
}, 0 },
1947 { "movD", { Sv
, Sw
}, 0 },
1948 { MOD_TABLE (MOD_8D
) },
1949 { "movD", { Sw
, Sv
}, 0 },
1950 { REG_TABLE (REG_8F
) },
1952 { PREFIX_TABLE (PREFIX_90
) },
1953 { "xchgS", { RMeCX
, eAX
}, 0 },
1954 { "xchgS", { RMeDX
, eAX
}, 0 },
1955 { "xchgS", { RMeBX
, eAX
}, 0 },
1956 { "xchgS", { RMeSP
, eAX
}, 0 },
1957 { "xchgS", { RMeBP
, eAX
}, 0 },
1958 { "xchgS", { RMeSI
, eAX
}, 0 },
1959 { "xchgS", { RMeDI
, eAX
}, 0 },
1961 { "cW{t|}R", { XX
}, 0 },
1962 { "cR{t|}O", { XX
}, 0 },
1963 { X86_64_TABLE (X86_64_9A
) },
1964 { Bad_Opcode
}, /* fwait */
1965 { "pushfP", { XX
}, 0 },
1966 { "popfP", { XX
}, 0 },
1967 { "sahf", { XX
}, 0 },
1968 { "lahf", { XX
}, 0 },
1970 { "mov%LB", { AL
, Ob
}, 0 },
1971 { "mov%LS", { eAX
, Ov
}, 0 },
1972 { "mov%LB", { Ob
, AL
}, 0 },
1973 { "mov%LS", { Ov
, eAX
}, 0 },
1974 { "movs{b|}", { Ybr
, Xb
}, 0 },
1975 { "movs{R|}", { Yvr
, Xv
}, 0 },
1976 { "cmps{b|}", { Xb
, Yb
}, 0 },
1977 { "cmps{R|}", { Xv
, Yv
}, 0 },
1979 { "testB", { AL
, Ib
}, 0 },
1980 { "testS", { eAX
, Iv
}, 0 },
1981 { "stosB", { Ybr
, AL
}, 0 },
1982 { "stosS", { Yvr
, eAX
}, 0 },
1983 { "lodsB", { ALr
, Xb
}, 0 },
1984 { "lodsS", { eAXr
, Xv
}, 0 },
1985 { "scasB", { AL
, Yb
}, 0 },
1986 { "scasS", { eAX
, Yv
}, 0 },
1988 { "movB", { RMAL
, Ib
}, 0 },
1989 { "movB", { RMCL
, Ib
}, 0 },
1990 { "movB", { RMDL
, Ib
}, 0 },
1991 { "movB", { RMBL
, Ib
}, 0 },
1992 { "movB", { RMAH
, Ib
}, 0 },
1993 { "movB", { RMCH
, Ib
}, 0 },
1994 { "movB", { RMDH
, Ib
}, 0 },
1995 { "movB", { RMBH
, Ib
}, 0 },
1997 { "mov%LV", { RMeAX
, Iv64
}, 0 },
1998 { "mov%LV", { RMeCX
, Iv64
}, 0 },
1999 { "mov%LV", { RMeDX
, Iv64
}, 0 },
2000 { "mov%LV", { RMeBX
, Iv64
}, 0 },
2001 { "mov%LV", { RMeSP
, Iv64
}, 0 },
2002 { "mov%LV", { RMeBP
, Iv64
}, 0 },
2003 { "mov%LV", { RMeSI
, Iv64
}, 0 },
2004 { "mov%LV", { RMeDI
, Iv64
}, 0 },
2006 { REG_TABLE (REG_C0
) },
2007 { REG_TABLE (REG_C1
) },
2008 { X86_64_TABLE (X86_64_C2
) },
2009 { X86_64_TABLE (X86_64_C3
) },
2010 { X86_64_TABLE (X86_64_C4
) },
2011 { X86_64_TABLE (X86_64_C5
) },
2012 { REG_TABLE (REG_C6
) },
2013 { REG_TABLE (REG_C7
) },
2015 { "enterP", { Iw
, Ib
}, 0 },
2016 { "leaveP", { XX
}, 0 },
2017 { "{l|}ret{|f}%LP", { Iw
}, 0 },
2018 { "{l|}ret{|f}%LP", { XX
}, 0 },
2019 { "int3", { XX
}, 0 },
2020 { "int", { Ib
}, 0 },
2021 { X86_64_TABLE (X86_64_CE
) },
2022 { "iret%LP", { XX
}, 0 },
2024 { REG_TABLE (REG_D0
) },
2025 { REG_TABLE (REG_D1
) },
2026 { REG_TABLE (REG_D2
) },
2027 { REG_TABLE (REG_D3
) },
2028 { X86_64_TABLE (X86_64_D4
) },
2029 { X86_64_TABLE (X86_64_D5
) },
2031 { "xlat", { DSBX
}, 0 },
2042 { "loopneFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2043 { "loopeFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2044 { "loopFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2045 { "jEcxzH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2046 { "inB", { AL
, Ib
}, 0 },
2047 { "inG", { zAX
, Ib
}, 0 },
2048 { "outB", { Ib
, AL
}, 0 },
2049 { "outG", { Ib
, zAX
}, 0 },
2051 { X86_64_TABLE (X86_64_E8
) },
2052 { X86_64_TABLE (X86_64_E9
) },
2053 { X86_64_TABLE (X86_64_EA
) },
2054 { "jmp", { Jb
, BND
}, 0 },
2055 { "inB", { AL
, indirDX
}, 0 },
2056 { "inG", { zAX
, indirDX
}, 0 },
2057 { "outB", { indirDX
, AL
}, 0 },
2058 { "outG", { indirDX
, zAX
}, 0 },
2060 { Bad_Opcode
}, /* lock prefix */
2061 { "icebp", { XX
}, 0 },
2062 { Bad_Opcode
}, /* repne */
2063 { Bad_Opcode
}, /* repz */
2064 { "hlt", { XX
}, 0 },
2065 { "cmc", { XX
}, 0 },
2066 { REG_TABLE (REG_F6
) },
2067 { REG_TABLE (REG_F7
) },
2069 { "clc", { XX
}, 0 },
2070 { "stc", { XX
}, 0 },
2071 { "cli", { XX
}, 0 },
2072 { "sti", { XX
}, 0 },
2073 { "cld", { XX
}, 0 },
2074 { "std", { XX
}, 0 },
2075 { REG_TABLE (REG_FE
) },
2076 { REG_TABLE (REG_FF
) },
2079 static const struct dis386 dis386_twobyte
[] = {
2081 { REG_TABLE (REG_0F00
) },
2082 { REG_TABLE (REG_0F01
) },
2083 { "larS", { Gv
, Ew
}, 0 },
2084 { "lslS", { Gv
, Ew
}, 0 },
2086 { "syscall", { XX
}, 0 },
2087 { "clts", { XX
}, 0 },
2088 { "sysret%LQ", { XX
}, 0 },
2090 { "invd", { XX
}, 0 },
2091 { PREFIX_TABLE (PREFIX_0F09
) },
2093 { "ud2", { XX
}, 0 },
2095 { REG_TABLE (REG_0F0D
) },
2096 { "femms", { XX
}, 0 },
2097 { "", { MX
, EM
, OPSUF
}, 0 }, /* See OP_3DNowSuffix. */
2099 { PREFIX_TABLE (PREFIX_0F10
) },
2100 { PREFIX_TABLE (PREFIX_0F11
) },
2101 { PREFIX_TABLE (PREFIX_0F12
) },
2102 { MOD_TABLE (MOD_0F13
) },
2103 { "unpcklpX", { XM
, EXx
}, PREFIX_OPCODE
},
2104 { "unpckhpX", { XM
, EXx
}, PREFIX_OPCODE
},
2105 { PREFIX_TABLE (PREFIX_0F16
) },
2106 { MOD_TABLE (MOD_0F17
) },
2108 { REG_TABLE (REG_0F18
) },
2109 { "nopQ", { Ev
}, 0 },
2110 { PREFIX_TABLE (PREFIX_0F1A
) },
2111 { PREFIX_TABLE (PREFIX_0F1B
) },
2112 { PREFIX_TABLE (PREFIX_0F1C
) },
2113 { "nopQ", { Ev
}, 0 },
2114 { PREFIX_TABLE (PREFIX_0F1E
) },
2115 { "nopQ", { Ev
}, 0 },
2117 { "movZ", { Em
, Cm
}, 0 },
2118 { "movZ", { Em
, Dm
}, 0 },
2119 { "movZ", { Cm
, Em
}, 0 },
2120 { "movZ", { Dm
, Em
}, 0 },
2121 { X86_64_TABLE (X86_64_0F24
) },
2123 { X86_64_TABLE (X86_64_0F26
) },
2126 { "movapX", { XM
, EXx
}, PREFIX_OPCODE
},
2127 { "movapX", { EXxS
, XM
}, PREFIX_OPCODE
},
2128 { PREFIX_TABLE (PREFIX_0F2A
) },
2129 { PREFIX_TABLE (PREFIX_0F2B
) },
2130 { PREFIX_TABLE (PREFIX_0F2C
) },
2131 { PREFIX_TABLE (PREFIX_0F2D
) },
2132 { PREFIX_TABLE (PREFIX_0F2E
) },
2133 { PREFIX_TABLE (PREFIX_0F2F
) },
2135 { "wrmsr", { XX
}, 0 },
2136 { "rdtsc", { XX
}, 0 },
2137 { "rdmsr", { XX
}, 0 },
2138 { "rdpmc", { XX
}, 0 },
2139 { "sysenter", { SEP
}, 0 },
2140 { "sysexit", { SEP
}, 0 },
2142 { "getsec", { XX
}, 0 },
2144 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38
, PREFIX_OPCODE
) },
2146 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A
, PREFIX_OPCODE
) },
2153 { "cmovoS", { Gv
, Ev
}, 0 },
2154 { "cmovnoS", { Gv
, Ev
}, 0 },
2155 { "cmovbS", { Gv
, Ev
}, 0 },
2156 { "cmovaeS", { Gv
, Ev
}, 0 },
2157 { "cmoveS", { Gv
, Ev
}, 0 },
2158 { "cmovneS", { Gv
, Ev
}, 0 },
2159 { "cmovbeS", { Gv
, Ev
}, 0 },
2160 { "cmovaS", { Gv
, Ev
}, 0 },
2162 { "cmovsS", { Gv
, Ev
}, 0 },
2163 { "cmovnsS", { Gv
, Ev
}, 0 },
2164 { "cmovpS", { Gv
, Ev
}, 0 },
2165 { "cmovnpS", { Gv
, Ev
}, 0 },
2166 { "cmovlS", { Gv
, Ev
}, 0 },
2167 { "cmovgeS", { Gv
, Ev
}, 0 },
2168 { "cmovleS", { Gv
, Ev
}, 0 },
2169 { "cmovgS", { Gv
, Ev
}, 0 },
2171 { MOD_TABLE (MOD_0F50
) },
2172 { PREFIX_TABLE (PREFIX_0F51
) },
2173 { PREFIX_TABLE (PREFIX_0F52
) },
2174 { PREFIX_TABLE (PREFIX_0F53
) },
2175 { "andpX", { XM
, EXx
}, PREFIX_OPCODE
},
2176 { "andnpX", { XM
, EXx
}, PREFIX_OPCODE
},
2177 { "orpX", { XM
, EXx
}, PREFIX_OPCODE
},
2178 { "xorpX", { XM
, EXx
}, PREFIX_OPCODE
},
2180 { PREFIX_TABLE (PREFIX_0F58
) },
2181 { PREFIX_TABLE (PREFIX_0F59
) },
2182 { PREFIX_TABLE (PREFIX_0F5A
) },
2183 { PREFIX_TABLE (PREFIX_0F5B
) },
2184 { PREFIX_TABLE (PREFIX_0F5C
) },
2185 { PREFIX_TABLE (PREFIX_0F5D
) },
2186 { PREFIX_TABLE (PREFIX_0F5E
) },
2187 { PREFIX_TABLE (PREFIX_0F5F
) },
2189 { PREFIX_TABLE (PREFIX_0F60
) },
2190 { PREFIX_TABLE (PREFIX_0F61
) },
2191 { PREFIX_TABLE (PREFIX_0F62
) },
2192 { "packsswb", { MX
, EM
}, PREFIX_OPCODE
},
2193 { "pcmpgtb", { MX
, EM
}, PREFIX_OPCODE
},
2194 { "pcmpgtw", { MX
, EM
}, PREFIX_OPCODE
},
2195 { "pcmpgtd", { MX
, EM
}, PREFIX_OPCODE
},
2196 { "packuswb", { MX
, EM
}, PREFIX_OPCODE
},
2198 { "punpckhbw", { MX
, EM
}, PREFIX_OPCODE
},
2199 { "punpckhwd", { MX
, EM
}, PREFIX_OPCODE
},
2200 { "punpckhdq", { MX
, EM
}, PREFIX_OPCODE
},
2201 { "packssdw", { MX
, EM
}, PREFIX_OPCODE
},
2202 { "punpcklqdq", { XM
, EXx
}, PREFIX_DATA
},
2203 { "punpckhqdq", { XM
, EXx
}, PREFIX_DATA
},
2204 { "movK", { MX
, Edq
}, PREFIX_OPCODE
},
2205 { PREFIX_TABLE (PREFIX_0F6F
) },
2207 { PREFIX_TABLE (PREFIX_0F70
) },
2208 { REG_TABLE (REG_0F71
) },
2209 { REG_TABLE (REG_0F72
) },
2210 { REG_TABLE (REG_0F73
) },
2211 { "pcmpeqb", { MX
, EM
}, PREFIX_OPCODE
},
2212 { "pcmpeqw", { MX
, EM
}, PREFIX_OPCODE
},
2213 { "pcmpeqd", { MX
, EM
}, PREFIX_OPCODE
},
2214 { "emms", { XX
}, PREFIX_OPCODE
},
2216 { PREFIX_TABLE (PREFIX_0F78
) },
2217 { PREFIX_TABLE (PREFIX_0F79
) },
2220 { PREFIX_TABLE (PREFIX_0F7C
) },
2221 { PREFIX_TABLE (PREFIX_0F7D
) },
2222 { PREFIX_TABLE (PREFIX_0F7E
) },
2223 { PREFIX_TABLE (PREFIX_0F7F
) },
2225 { "joH", { Jv
, BND
, cond_jump_flag
}, 0 },
2226 { "jnoH", { Jv
, BND
, cond_jump_flag
}, 0 },
2227 { "jbH", { Jv
, BND
, cond_jump_flag
}, 0 },
2228 { "jaeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2229 { "jeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2230 { "jneH", { Jv
, BND
, cond_jump_flag
}, 0 },
2231 { "jbeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2232 { "jaH", { Jv
, BND
, cond_jump_flag
}, 0 },
2234 { "jsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2235 { "jnsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2236 { "jpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2237 { "jnpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2238 { "jlH", { Jv
, BND
, cond_jump_flag
}, 0 },
2239 { "jgeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2240 { "jleH", { Jv
, BND
, cond_jump_flag
}, 0 },
2241 { "jgH", { Jv
, BND
, cond_jump_flag
}, 0 },
2243 { "seto", { Eb
}, 0 },
2244 { "setno", { Eb
}, 0 },
2245 { "setb", { Eb
}, 0 },
2246 { "setae", { Eb
}, 0 },
2247 { "sete", { Eb
}, 0 },
2248 { "setne", { Eb
}, 0 },
2249 { "setbe", { Eb
}, 0 },
2250 { "seta", { Eb
}, 0 },
2252 { "sets", { Eb
}, 0 },
2253 { "setns", { Eb
}, 0 },
2254 { "setp", { Eb
}, 0 },
2255 { "setnp", { Eb
}, 0 },
2256 { "setl", { Eb
}, 0 },
2257 { "setge", { Eb
}, 0 },
2258 { "setle", { Eb
}, 0 },
2259 { "setg", { Eb
}, 0 },
2261 { "pushP", { fs
}, 0 },
2262 { "popP", { fs
}, 0 },
2263 { "cpuid", { XX
}, 0 },
2264 { "btS", { Ev
, Gv
}, 0 },
2265 { "shldS", { Ev
, Gv
, Ib
}, 0 },
2266 { "shldS", { Ev
, Gv
, CL
}, 0 },
2267 { REG_TABLE (REG_0FA6
) },
2268 { REG_TABLE (REG_0FA7
) },
2270 { "pushP", { gs
}, 0 },
2271 { "popP", { gs
}, 0 },
2272 { "rsm", { XX
}, 0 },
2273 { "btsS", { Evh1
, Gv
}, 0 },
2274 { "shrdS", { Ev
, Gv
, Ib
}, 0 },
2275 { "shrdS", { Ev
, Gv
, CL
}, 0 },
2276 { REG_TABLE (REG_0FAE
) },
2277 { "imulS", { Gv
, Ev
}, 0 },
2279 { "cmpxchgB", { Ebh1
, Gb
}, 0 },
2280 { "cmpxchgS", { Evh1
, Gv
}, 0 },
2281 { MOD_TABLE (MOD_0FB2
) },
2282 { "btrS", { Evh1
, Gv
}, 0 },
2283 { MOD_TABLE (MOD_0FB4
) },
2284 { MOD_TABLE (MOD_0FB5
) },
2285 { "movz{bR|x}", { Gv
, Eb
}, 0 },
2286 { "movz{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movzww ! */
2288 { PREFIX_TABLE (PREFIX_0FB8
) },
2289 { "ud1S", { Gv
, Ev
}, 0 },
2290 { REG_TABLE (REG_0FBA
) },
2291 { "btcS", { Evh1
, Gv
}, 0 },
2292 { PREFIX_TABLE (PREFIX_0FBC
) },
2293 { PREFIX_TABLE (PREFIX_0FBD
) },
2294 { "movs{bR|x}", { Gv
, Eb
}, 0 },
2295 { "movs{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movsww ! */
2297 { "xaddB", { Ebh1
, Gb
}, 0 },
2298 { "xaddS", { Evh1
, Gv
}, 0 },
2299 { PREFIX_TABLE (PREFIX_0FC2
) },
2300 { MOD_TABLE (MOD_0FC3
) },
2301 { "pinsrw", { MX
, Edqw
, Ib
}, PREFIX_OPCODE
},
2302 { "pextrw", { Gdq
, MS
, Ib
}, PREFIX_OPCODE
},
2303 { "shufpX", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
2304 { REG_TABLE (REG_0FC7
) },
2306 { "bswap", { RMeAX
}, 0 },
2307 { "bswap", { RMeCX
}, 0 },
2308 { "bswap", { RMeDX
}, 0 },
2309 { "bswap", { RMeBX
}, 0 },
2310 { "bswap", { RMeSP
}, 0 },
2311 { "bswap", { RMeBP
}, 0 },
2312 { "bswap", { RMeSI
}, 0 },
2313 { "bswap", { RMeDI
}, 0 },
2315 { PREFIX_TABLE (PREFIX_0FD0
) },
2316 { "psrlw", { MX
, EM
}, PREFIX_OPCODE
},
2317 { "psrld", { MX
, EM
}, PREFIX_OPCODE
},
2318 { "psrlq", { MX
, EM
}, PREFIX_OPCODE
},
2319 { "paddq", { MX
, EM
}, PREFIX_OPCODE
},
2320 { "pmullw", { MX
, EM
}, PREFIX_OPCODE
},
2321 { PREFIX_TABLE (PREFIX_0FD6
) },
2322 { MOD_TABLE (MOD_0FD7
) },
2324 { "psubusb", { MX
, EM
}, PREFIX_OPCODE
},
2325 { "psubusw", { MX
, EM
}, PREFIX_OPCODE
},
2326 { "pminub", { MX
, EM
}, PREFIX_OPCODE
},
2327 { "pand", { MX
, EM
}, PREFIX_OPCODE
},
2328 { "paddusb", { MX
, EM
}, PREFIX_OPCODE
},
2329 { "paddusw", { MX
, EM
}, PREFIX_OPCODE
},
2330 { "pmaxub", { MX
, EM
}, PREFIX_OPCODE
},
2331 { "pandn", { MX
, EM
}, PREFIX_OPCODE
},
2333 { "pavgb", { MX
, EM
}, PREFIX_OPCODE
},
2334 { "psraw", { MX
, EM
}, PREFIX_OPCODE
},
2335 { "psrad", { MX
, EM
}, PREFIX_OPCODE
},
2336 { "pavgw", { MX
, EM
}, PREFIX_OPCODE
},
2337 { "pmulhuw", { MX
, EM
}, PREFIX_OPCODE
},
2338 { "pmulhw", { MX
, EM
}, PREFIX_OPCODE
},
2339 { PREFIX_TABLE (PREFIX_0FE6
) },
2340 { PREFIX_TABLE (PREFIX_0FE7
) },
2342 { "psubsb", { MX
, EM
}, PREFIX_OPCODE
},
2343 { "psubsw", { MX
, EM
}, PREFIX_OPCODE
},
2344 { "pminsw", { MX
, EM
}, PREFIX_OPCODE
},
2345 { "por", { MX
, EM
}, PREFIX_OPCODE
},
2346 { "paddsb", { MX
, EM
}, PREFIX_OPCODE
},
2347 { "paddsw", { MX
, EM
}, PREFIX_OPCODE
},
2348 { "pmaxsw", { MX
, EM
}, PREFIX_OPCODE
},
2349 { "pxor", { MX
, EM
}, PREFIX_OPCODE
},
2351 { PREFIX_TABLE (PREFIX_0FF0
) },
2352 { "psllw", { MX
, EM
}, PREFIX_OPCODE
},
2353 { "pslld", { MX
, EM
}, PREFIX_OPCODE
},
2354 { "psllq", { MX
, EM
}, PREFIX_OPCODE
},
2355 { "pmuludq", { MX
, EM
}, PREFIX_OPCODE
},
2356 { "pmaddwd", { MX
, EM
}, PREFIX_OPCODE
},
2357 { "psadbw", { MX
, EM
}, PREFIX_OPCODE
},
2358 { PREFIX_TABLE (PREFIX_0FF7
) },
2360 { "psubb", { MX
, EM
}, PREFIX_OPCODE
},
2361 { "psubw", { MX
, EM
}, PREFIX_OPCODE
},
2362 { "psubd", { MX
, EM
}, PREFIX_OPCODE
},
2363 { "psubq", { MX
, EM
}, PREFIX_OPCODE
},
2364 { "paddb", { MX
, EM
}, PREFIX_OPCODE
},
2365 { "paddw", { MX
, EM
}, PREFIX_OPCODE
},
2366 { "paddd", { MX
, EM
}, PREFIX_OPCODE
},
2367 { "ud0S", { Gv
, Ev
}, 0 },
2370 static const unsigned char onebyte_has_modrm
[256] = {
2371 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2372 /* ------------------------------- */
2373 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2374 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2375 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2376 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2377 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2378 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2379 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2380 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2381 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2382 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2383 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2384 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2385 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2386 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2387 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2388 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2389 /* ------------------------------- */
2390 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2393 static const unsigned char twobyte_has_modrm
[256] = {
2394 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2395 /* ------------------------------- */
2396 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2397 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2398 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2399 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2400 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2401 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2402 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2403 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2404 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2405 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2406 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2407 /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2408 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2409 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2410 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2411 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */
2412 /* ------------------------------- */
2413 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2416 static char obuf
[100];
2418 static char *mnemonicendp
;
2419 static char scratchbuf
[100];
2420 static unsigned char *start_codep
;
2421 static unsigned char *insn_codep
;
2422 static unsigned char *codep
;
2423 static unsigned char *end_codep
;
2424 static int last_lock_prefix
;
2425 static int last_repz_prefix
;
2426 static int last_repnz_prefix
;
2427 static int last_data_prefix
;
2428 static int last_addr_prefix
;
2429 static int last_rex_prefix
;
2430 static int last_seg_prefix
;
2431 static int fwait_prefix
;
2432 /* The active segment register prefix. */
2433 static int active_seg_prefix
;
2434 #define MAX_CODE_LENGTH 15
2435 /* We can up to 14 prefixes since the maximum instruction length is
2437 static int all_prefixes
[MAX_CODE_LENGTH
- 1];
2438 static disassemble_info
*the_info
;
2446 static unsigned char need_modrm
;
2456 int register_specifier
;
2463 int mask_register_specifier
;
2469 static unsigned char need_vex
;
2477 /* If we are accessing mod/rm/reg without need_modrm set, then the
2478 values are stale. Hitting this abort likely indicates that you
2479 need to update onebyte_has_modrm or twobyte_has_modrm. */
2480 #define MODRM_CHECK if (!need_modrm) abort ()
2482 static const char **names64
;
2483 static const char **names32
;
2484 static const char **names16
;
2485 static const char **names8
;
2486 static const char **names8rex
;
2487 static const char **names_seg
;
2488 static const char *index64
;
2489 static const char *index32
;
2490 static const char **index16
;
2491 static const char **names_bnd
;
2493 static const char *intel_names64
[] = {
2494 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2495 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2497 static const char *intel_names32
[] = {
2498 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2499 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2501 static const char *intel_names16
[] = {
2502 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2503 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2505 static const char *intel_names8
[] = {
2506 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2508 static const char *intel_names8rex
[] = {
2509 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2510 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2512 static const char *intel_names_seg
[] = {
2513 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2515 static const char *intel_index64
= "riz";
2516 static const char *intel_index32
= "eiz";
2517 static const char *intel_index16
[] = {
2518 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2521 static const char *att_names64
[] = {
2522 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2523 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2525 static const char *att_names32
[] = {
2526 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2527 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2529 static const char *att_names16
[] = {
2530 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2531 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2533 static const char *att_names8
[] = {
2534 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2536 static const char *att_names8rex
[] = {
2537 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2538 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2540 static const char *att_names_seg
[] = {
2541 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2543 static const char *att_index64
= "%riz";
2544 static const char *att_index32
= "%eiz";
2545 static const char *att_index16
[] = {
2546 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2549 static const char **names_mm
;
2550 static const char *intel_names_mm
[] = {
2551 "mm0", "mm1", "mm2", "mm3",
2552 "mm4", "mm5", "mm6", "mm7"
2554 static const char *att_names_mm
[] = {
2555 "%mm0", "%mm1", "%mm2", "%mm3",
2556 "%mm4", "%mm5", "%mm6", "%mm7"
2559 static const char *intel_names_bnd
[] = {
2560 "bnd0", "bnd1", "bnd2", "bnd3"
2563 static const char *att_names_bnd
[] = {
2564 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
2567 static const char **names_xmm
;
2568 static const char *intel_names_xmm
[] = {
2569 "xmm0", "xmm1", "xmm2", "xmm3",
2570 "xmm4", "xmm5", "xmm6", "xmm7",
2571 "xmm8", "xmm9", "xmm10", "xmm11",
2572 "xmm12", "xmm13", "xmm14", "xmm15",
2573 "xmm16", "xmm17", "xmm18", "xmm19",
2574 "xmm20", "xmm21", "xmm22", "xmm23",
2575 "xmm24", "xmm25", "xmm26", "xmm27",
2576 "xmm28", "xmm29", "xmm30", "xmm31"
2578 static const char *att_names_xmm
[] = {
2579 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2580 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2581 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2582 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
2583 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
2584 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
2585 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
2586 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
2589 static const char **names_ymm
;
2590 static const char *intel_names_ymm
[] = {
2591 "ymm0", "ymm1", "ymm2", "ymm3",
2592 "ymm4", "ymm5", "ymm6", "ymm7",
2593 "ymm8", "ymm9", "ymm10", "ymm11",
2594 "ymm12", "ymm13", "ymm14", "ymm15",
2595 "ymm16", "ymm17", "ymm18", "ymm19",
2596 "ymm20", "ymm21", "ymm22", "ymm23",
2597 "ymm24", "ymm25", "ymm26", "ymm27",
2598 "ymm28", "ymm29", "ymm30", "ymm31"
2600 static const char *att_names_ymm
[] = {
2601 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2602 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2603 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2604 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
2605 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
2606 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
2607 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
2608 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
2611 static const char **names_zmm
;
2612 static const char *intel_names_zmm
[] = {
2613 "zmm0", "zmm1", "zmm2", "zmm3",
2614 "zmm4", "zmm5", "zmm6", "zmm7",
2615 "zmm8", "zmm9", "zmm10", "zmm11",
2616 "zmm12", "zmm13", "zmm14", "zmm15",
2617 "zmm16", "zmm17", "zmm18", "zmm19",
2618 "zmm20", "zmm21", "zmm22", "zmm23",
2619 "zmm24", "zmm25", "zmm26", "zmm27",
2620 "zmm28", "zmm29", "zmm30", "zmm31"
2622 static const char *att_names_zmm
[] = {
2623 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
2624 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
2625 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
2626 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
2627 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
2628 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
2629 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
2630 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
2633 static const char **names_tmm
;
2634 static const char *intel_names_tmm
[] = {
2635 "tmm0", "tmm1", "tmm2", "tmm3",
2636 "tmm4", "tmm5", "tmm6", "tmm7"
2638 static const char *att_names_tmm
[] = {
2639 "%tmm0", "%tmm1", "%tmm2", "%tmm3",
2640 "%tmm4", "%tmm5", "%tmm6", "%tmm7"
2643 static const char **names_mask
;
2644 static const char *intel_names_mask
[] = {
2645 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
2647 static const char *att_names_mask
[] = {
2648 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
2651 static const char *names_rounding
[] =
2659 static const struct dis386 reg_table
[][8] = {
2662 { "addA", { Ebh1
, Ib
}, 0 },
2663 { "orA", { Ebh1
, Ib
}, 0 },
2664 { "adcA", { Ebh1
, Ib
}, 0 },
2665 { "sbbA", { Ebh1
, Ib
}, 0 },
2666 { "andA", { Ebh1
, Ib
}, 0 },
2667 { "subA", { Ebh1
, Ib
}, 0 },
2668 { "xorA", { Ebh1
, Ib
}, 0 },
2669 { "cmpA", { Eb
, Ib
}, 0 },
2673 { "addQ", { Evh1
, Iv
}, 0 },
2674 { "orQ", { Evh1
, Iv
}, 0 },
2675 { "adcQ", { Evh1
, Iv
}, 0 },
2676 { "sbbQ", { Evh1
, Iv
}, 0 },
2677 { "andQ", { Evh1
, Iv
}, 0 },
2678 { "subQ", { Evh1
, Iv
}, 0 },
2679 { "xorQ", { Evh1
, Iv
}, 0 },
2680 { "cmpQ", { Ev
, Iv
}, 0 },
2684 { "addQ", { Evh1
, sIb
}, 0 },
2685 { "orQ", { Evh1
, sIb
}, 0 },
2686 { "adcQ", { Evh1
, sIb
}, 0 },
2687 { "sbbQ", { Evh1
, sIb
}, 0 },
2688 { "andQ", { Evh1
, sIb
}, 0 },
2689 { "subQ", { Evh1
, sIb
}, 0 },
2690 { "xorQ", { Evh1
, sIb
}, 0 },
2691 { "cmpQ", { Ev
, sIb
}, 0 },
2695 { "pop{P|}", { stackEv
}, 0 },
2696 { XOP_8F_TABLE (XOP_09
) },
2700 { XOP_8F_TABLE (XOP_09
) },
2704 { "rolA", { Eb
, Ib
}, 0 },
2705 { "rorA", { Eb
, Ib
}, 0 },
2706 { "rclA", { Eb
, Ib
}, 0 },
2707 { "rcrA", { Eb
, Ib
}, 0 },
2708 { "shlA", { Eb
, Ib
}, 0 },
2709 { "shrA", { Eb
, Ib
}, 0 },
2710 { "shlA", { Eb
, Ib
}, 0 },
2711 { "sarA", { Eb
, Ib
}, 0 },
2715 { "rolQ", { Ev
, Ib
}, 0 },
2716 { "rorQ", { Ev
, Ib
}, 0 },
2717 { "rclQ", { Ev
, Ib
}, 0 },
2718 { "rcrQ", { Ev
, Ib
}, 0 },
2719 { "shlQ", { Ev
, Ib
}, 0 },
2720 { "shrQ", { Ev
, Ib
}, 0 },
2721 { "shlQ", { Ev
, Ib
}, 0 },
2722 { "sarQ", { Ev
, Ib
}, 0 },
2726 { "movA", { Ebh3
, Ib
}, 0 },
2733 { MOD_TABLE (MOD_C6_REG_7
) },
2737 { "movQ", { Evh3
, Iv
}, 0 },
2744 { MOD_TABLE (MOD_C7_REG_7
) },
2748 { "rolA", { Eb
, I1
}, 0 },
2749 { "rorA", { Eb
, I1
}, 0 },
2750 { "rclA", { Eb
, I1
}, 0 },
2751 { "rcrA", { Eb
, I1
}, 0 },
2752 { "shlA", { Eb
, I1
}, 0 },
2753 { "shrA", { Eb
, I1
}, 0 },
2754 { "shlA", { Eb
, I1
}, 0 },
2755 { "sarA", { Eb
, I1
}, 0 },
2759 { "rolQ", { Ev
, I1
}, 0 },
2760 { "rorQ", { Ev
, I1
}, 0 },
2761 { "rclQ", { Ev
, I1
}, 0 },
2762 { "rcrQ", { Ev
, I1
}, 0 },
2763 { "shlQ", { Ev
, I1
}, 0 },
2764 { "shrQ", { Ev
, I1
}, 0 },
2765 { "shlQ", { Ev
, I1
}, 0 },
2766 { "sarQ", { Ev
, I1
}, 0 },
2770 { "rolA", { Eb
, CL
}, 0 },
2771 { "rorA", { Eb
, CL
}, 0 },
2772 { "rclA", { Eb
, CL
}, 0 },
2773 { "rcrA", { Eb
, CL
}, 0 },
2774 { "shlA", { Eb
, CL
}, 0 },
2775 { "shrA", { Eb
, CL
}, 0 },
2776 { "shlA", { Eb
, CL
}, 0 },
2777 { "sarA", { Eb
, CL
}, 0 },
2781 { "rolQ", { Ev
, CL
}, 0 },
2782 { "rorQ", { Ev
, CL
}, 0 },
2783 { "rclQ", { Ev
, CL
}, 0 },
2784 { "rcrQ", { Ev
, CL
}, 0 },
2785 { "shlQ", { Ev
, CL
}, 0 },
2786 { "shrQ", { Ev
, CL
}, 0 },
2787 { "shlQ", { Ev
, CL
}, 0 },
2788 { "sarQ", { Ev
, CL
}, 0 },
2792 { "testA", { Eb
, Ib
}, 0 },
2793 { "testA", { Eb
, Ib
}, 0 },
2794 { "notA", { Ebh1
}, 0 },
2795 { "negA", { Ebh1
}, 0 },
2796 { "mulA", { Eb
}, 0 }, /* Don't print the implicit %al register, */
2797 { "imulA", { Eb
}, 0 }, /* to distinguish these opcodes from other */
2798 { "divA", { Eb
}, 0 }, /* mul/imul opcodes. Do the same for div */
2799 { "idivA", { Eb
}, 0 }, /* and idiv for consistency. */
2803 { "testQ", { Ev
, Iv
}, 0 },
2804 { "testQ", { Ev
, Iv
}, 0 },
2805 { "notQ", { Evh1
}, 0 },
2806 { "negQ", { Evh1
}, 0 },
2807 { "mulQ", { Ev
}, 0 }, /* Don't print the implicit register. */
2808 { "imulQ", { Ev
}, 0 },
2809 { "divQ", { Ev
}, 0 },
2810 { "idivQ", { Ev
}, 0 },
2814 { "incA", { Ebh1
}, 0 },
2815 { "decA", { Ebh1
}, 0 },
2819 { "incQ", { Evh1
}, 0 },
2820 { "decQ", { Evh1
}, 0 },
2821 { "call{@|}", { NOTRACK
, indirEv
, BND
}, 0 },
2822 { MOD_TABLE (MOD_FF_REG_3
) },
2823 { "jmp{@|}", { NOTRACK
, indirEv
, BND
}, 0 },
2824 { MOD_TABLE (MOD_FF_REG_5
) },
2825 { "push{P|}", { stackEv
}, 0 },
2830 { "sldtD", { Sv
}, 0 },
2831 { "strD", { Sv
}, 0 },
2832 { "lldt", { Ew
}, 0 },
2833 { "ltr", { Ew
}, 0 },
2834 { "verr", { Ew
}, 0 },
2835 { "verw", { Ew
}, 0 },
2841 { MOD_TABLE (MOD_0F01_REG_0
) },
2842 { MOD_TABLE (MOD_0F01_REG_1
) },
2843 { MOD_TABLE (MOD_0F01_REG_2
) },
2844 { MOD_TABLE (MOD_0F01_REG_3
) },
2845 { "smswD", { Sv
}, 0 },
2846 { MOD_TABLE (MOD_0F01_REG_5
) },
2847 { "lmsw", { Ew
}, 0 },
2848 { MOD_TABLE (MOD_0F01_REG_7
) },
2852 { "prefetch", { Mb
}, 0 },
2853 { "prefetchw", { Mb
}, 0 },
2854 { "prefetchwt1", { Mb
}, 0 },
2855 { "prefetch", { Mb
}, 0 },
2856 { "prefetch", { Mb
}, 0 },
2857 { "prefetch", { Mb
}, 0 },
2858 { "prefetch", { Mb
}, 0 },
2859 { "prefetch", { Mb
}, 0 },
2863 { MOD_TABLE (MOD_0F18_REG_0
) },
2864 { MOD_TABLE (MOD_0F18_REG_1
) },
2865 { MOD_TABLE (MOD_0F18_REG_2
) },
2866 { MOD_TABLE (MOD_0F18_REG_3
) },
2867 { MOD_TABLE (MOD_0F18_REG_4
) },
2868 { MOD_TABLE (MOD_0F18_REG_5
) },
2869 { MOD_TABLE (MOD_0F18_REG_6
) },
2870 { MOD_TABLE (MOD_0F18_REG_7
) },
2872 /* REG_0F1C_P_0_MOD_0 */
2874 { "cldemote", { Mb
}, 0 },
2875 { "nopQ", { Ev
}, 0 },
2876 { "nopQ", { Ev
}, 0 },
2877 { "nopQ", { Ev
}, 0 },
2878 { "nopQ", { Ev
}, 0 },
2879 { "nopQ", { Ev
}, 0 },
2880 { "nopQ", { Ev
}, 0 },
2881 { "nopQ", { Ev
}, 0 },
2883 /* REG_0F1E_P_1_MOD_3 */
2885 { "nopQ", { Ev
}, 0 },
2886 { "rdsspK", { Edq
}, PREFIX_OPCODE
},
2887 { "nopQ", { Ev
}, 0 },
2888 { "nopQ", { Ev
}, 0 },
2889 { "nopQ", { Ev
}, 0 },
2890 { "nopQ", { Ev
}, 0 },
2891 { "nopQ", { Ev
}, 0 },
2892 { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7
) },
2898 { MOD_TABLE (MOD_0F71_REG_2
) },
2900 { MOD_TABLE (MOD_0F71_REG_4
) },
2902 { MOD_TABLE (MOD_0F71_REG_6
) },
2908 { MOD_TABLE (MOD_0F72_REG_2
) },
2910 { MOD_TABLE (MOD_0F72_REG_4
) },
2912 { MOD_TABLE (MOD_0F72_REG_6
) },
2918 { MOD_TABLE (MOD_0F73_REG_2
) },
2919 { MOD_TABLE (MOD_0F73_REG_3
) },
2922 { MOD_TABLE (MOD_0F73_REG_6
) },
2923 { MOD_TABLE (MOD_0F73_REG_7
) },
2927 { "montmul", { { OP_0f07
, 0 } }, 0 },
2928 { "xsha1", { { OP_0f07
, 0 } }, 0 },
2929 { "xsha256", { { OP_0f07
, 0 } }, 0 },
2933 { "xstore-rng", { { OP_0f07
, 0 } }, 0 },
2934 { "xcrypt-ecb", { { OP_0f07
, 0 } }, 0 },
2935 { "xcrypt-cbc", { { OP_0f07
, 0 } }, 0 },
2936 { "xcrypt-ctr", { { OP_0f07
, 0 } }, 0 },
2937 { "xcrypt-cfb", { { OP_0f07
, 0 } }, 0 },
2938 { "xcrypt-ofb", { { OP_0f07
, 0 } }, 0 },
2942 { MOD_TABLE (MOD_0FAE_REG_0
) },
2943 { MOD_TABLE (MOD_0FAE_REG_1
) },
2944 { MOD_TABLE (MOD_0FAE_REG_2
) },
2945 { MOD_TABLE (MOD_0FAE_REG_3
) },
2946 { MOD_TABLE (MOD_0FAE_REG_4
) },
2947 { MOD_TABLE (MOD_0FAE_REG_5
) },
2948 { MOD_TABLE (MOD_0FAE_REG_6
) },
2949 { MOD_TABLE (MOD_0FAE_REG_7
) },
2957 { "btQ", { Ev
, Ib
}, 0 },
2958 { "btsQ", { Evh1
, Ib
}, 0 },
2959 { "btrQ", { Evh1
, Ib
}, 0 },
2960 { "btcQ", { Evh1
, Ib
}, 0 },
2965 { "cmpxchg8b", { { CMPXCHG8B_Fixup
, q_mode
} }, 0 },
2967 { MOD_TABLE (MOD_0FC7_REG_3
) },
2968 { MOD_TABLE (MOD_0FC7_REG_4
) },
2969 { MOD_TABLE (MOD_0FC7_REG_5
) },
2970 { MOD_TABLE (MOD_0FC7_REG_6
) },
2971 { MOD_TABLE (MOD_0FC7_REG_7
) },
2977 { MOD_TABLE (MOD_VEX_0F71_REG_2
) },
2979 { MOD_TABLE (MOD_VEX_0F71_REG_4
) },
2981 { MOD_TABLE (MOD_VEX_0F71_REG_6
) },
2987 { MOD_TABLE (MOD_VEX_0F72_REG_2
) },
2989 { MOD_TABLE (MOD_VEX_0F72_REG_4
) },
2991 { MOD_TABLE (MOD_VEX_0F72_REG_6
) },
2997 { MOD_TABLE (MOD_VEX_0F73_REG_2
) },
2998 { MOD_TABLE (MOD_VEX_0F73_REG_3
) },
3001 { MOD_TABLE (MOD_VEX_0F73_REG_6
) },
3002 { MOD_TABLE (MOD_VEX_0F73_REG_7
) },
3008 { MOD_TABLE (MOD_VEX_0FAE_REG_2
) },
3009 { MOD_TABLE (MOD_VEX_0FAE_REG_3
) },
3011 /* REG_VEX_0F3849_X86_64_P_0_W_0_M_1 */
3013 { RM_TABLE (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0
) },
3015 /* REG_VEX_0F38F3 */
3018 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1
) },
3019 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2
) },
3020 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3
) },
3022 /* REG_0FXOP_09_01_L_0 */
3025 { "blcfill", { VexGdq
, Edq
}, 0 },
3026 { "blsfill", { VexGdq
, Edq
}, 0 },
3027 { "blcs", { VexGdq
, Edq
}, 0 },
3028 { "tzmsk", { VexGdq
, Edq
}, 0 },
3029 { "blcic", { VexGdq
, Edq
}, 0 },
3030 { "blsic", { VexGdq
, Edq
}, 0 },
3031 { "t1mskc", { VexGdq
, Edq
}, 0 },
3033 /* REG_0FXOP_09_02_L_0 */
3036 { "blcmsk", { VexGdq
, Edq
}, 0 },
3041 { "blci", { VexGdq
, Edq
}, 0 },
3043 /* REG_0FXOP_09_12_M_1_L_0 */
3045 { "llwpcb", { Edq
}, 0 },
3046 { "slwpcb", { Edq
}, 0 },
3048 /* REG_0FXOP_0A_12_L_0 */
3050 { "lwpins", { VexGdq
, Ed
, Id
}, 0 },
3051 { "lwpval", { VexGdq
, Ed
, Id
}, 0 },
3054 #include "i386-dis-evex-reg.h"
3057 static const struct dis386 prefix_table
[][4] = {
3060 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3061 { "pause", { XX
}, 0 },
3062 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3063 { NULL
, { { NULL
, 0 } }, PREFIX_IGNORED
}
3066 /* PREFIX_0F01_REG_3_RM_1 */
3068 { "vmmcall", { Skip_MODRM
}, 0 },
3069 { "vmgexit", { Skip_MODRM
}, 0 },
3071 { "vmgexit", { Skip_MODRM
}, 0 },
3074 /* PREFIX_0F01_REG_5_MOD_0 */
3077 { "rstorssp", { Mq
}, PREFIX_OPCODE
},
3080 /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3082 { "serialize", { Skip_MODRM
}, PREFIX_OPCODE
},
3083 { "setssbsy", { Skip_MODRM
}, PREFIX_OPCODE
},
3085 { "xsusldtrk", { Skip_MODRM
}, PREFIX_OPCODE
},
3088 /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
3093 { "xresldtrk", { Skip_MODRM
}, PREFIX_OPCODE
},
3096 /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3099 { "saveprevssp", { Skip_MODRM
}, PREFIX_OPCODE
},
3102 /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3104 { "monitorx", { { OP_Monitor
, 0 } }, 0 },
3105 { "mcommit", { Skip_MODRM
}, 0 },
3110 { "wbinvd", { XX
}, 0 },
3111 { "wbnoinvd", { XX
}, 0 },
3116 { "movups", { XM
, EXx
}, PREFIX_OPCODE
},
3117 { "movss", { XM
, EXd
}, PREFIX_OPCODE
},
3118 { "movupd", { XM
, EXx
}, PREFIX_OPCODE
},
3119 { "movsd", { XM
, EXq
}, PREFIX_OPCODE
},
3124 { "movups", { EXxS
, XM
}, PREFIX_OPCODE
},
3125 { "movss", { EXdS
, XM
}, PREFIX_OPCODE
},
3126 { "movupd", { EXxS
, XM
}, PREFIX_OPCODE
},
3127 { "movsd", { EXqS
, XM
}, PREFIX_OPCODE
},
3132 { MOD_TABLE (MOD_0F12_PREFIX_0
) },
3133 { "movsldup", { XM
, EXx
}, PREFIX_OPCODE
},
3134 { MOD_TABLE (MOD_0F12_PREFIX_2
) },
3135 { "movddup", { XM
, EXq
}, PREFIX_OPCODE
},
3140 { MOD_TABLE (MOD_0F16_PREFIX_0
) },
3141 { "movshdup", { XM
, EXx
}, PREFIX_OPCODE
},
3142 { MOD_TABLE (MOD_0F16_PREFIX_2
) },
3147 { MOD_TABLE (MOD_0F1A_PREFIX_0
) },
3148 { "bndcl", { Gbnd
, Ev_bnd
}, 0 },
3149 { "bndmov", { Gbnd
, Ebnd
}, 0 },
3150 { "bndcu", { Gbnd
, Ev_bnd
}, 0 },
3155 { MOD_TABLE (MOD_0F1B_PREFIX_0
) },
3156 { MOD_TABLE (MOD_0F1B_PREFIX_1
) },
3157 { "bndmov", { EbndS
, Gbnd
}, 0 },
3158 { "bndcn", { Gbnd
, Ev_bnd
}, 0 },
3163 { MOD_TABLE (MOD_0F1C_PREFIX_0
) },
3164 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3165 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3166 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3171 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3172 { MOD_TABLE (MOD_0F1E_PREFIX_1
) },
3173 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3174 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3179 { "cvtpi2ps", { XM
, EMCq
}, PREFIX_OPCODE
},
3180 { "cvtsi2ss{%LQ|}", { XM
, Edq
}, PREFIX_OPCODE
},
3181 { "cvtpi2pd", { XM
, EMCq
}, PREFIX_OPCODE
},
3182 { "cvtsi2sd{%LQ|}", { XM
, Edq
}, 0 },
3187 { MOD_TABLE (MOD_0F2B_PREFIX_0
) },
3188 { MOD_TABLE (MOD_0F2B_PREFIX_1
) },
3189 { MOD_TABLE (MOD_0F2B_PREFIX_2
) },
3190 { MOD_TABLE (MOD_0F2B_PREFIX_3
) },
3195 { "cvttps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3196 { "cvttss2si", { Gdq
, EXd
}, PREFIX_OPCODE
},
3197 { "cvttpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3198 { "cvttsd2si", { Gdq
, EXq
}, PREFIX_OPCODE
},
3203 { "cvtps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3204 { "cvtss2si", { Gdq
, EXd
}, PREFIX_OPCODE
},
3205 { "cvtpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3206 { "cvtsd2si", { Gdq
, EXq
}, PREFIX_OPCODE
},
3211 { "ucomiss",{ XM
, EXd
}, 0 },
3213 { "ucomisd",{ XM
, EXq
}, 0 },
3218 { "comiss", { XM
, EXd
}, 0 },
3220 { "comisd", { XM
, EXq
}, 0 },
3225 { "sqrtps", { XM
, EXx
}, PREFIX_OPCODE
},
3226 { "sqrtss", { XM
, EXd
}, PREFIX_OPCODE
},
3227 { "sqrtpd", { XM
, EXx
}, PREFIX_OPCODE
},
3228 { "sqrtsd", { XM
, EXq
}, PREFIX_OPCODE
},
3233 { "rsqrtps",{ XM
, EXx
}, PREFIX_OPCODE
},
3234 { "rsqrtss",{ XM
, EXd
}, PREFIX_OPCODE
},
3239 { "rcpps", { XM
, EXx
}, PREFIX_OPCODE
},
3240 { "rcpss", { XM
, EXd
}, PREFIX_OPCODE
},
3245 { "addps", { XM
, EXx
}, PREFIX_OPCODE
},
3246 { "addss", { XM
, EXd
}, PREFIX_OPCODE
},
3247 { "addpd", { XM
, EXx
}, PREFIX_OPCODE
},
3248 { "addsd", { XM
, EXq
}, PREFIX_OPCODE
},
3253 { "mulps", { XM
, EXx
}, PREFIX_OPCODE
},
3254 { "mulss", { XM
, EXd
}, PREFIX_OPCODE
},
3255 { "mulpd", { XM
, EXx
}, PREFIX_OPCODE
},
3256 { "mulsd", { XM
, EXq
}, PREFIX_OPCODE
},
3261 { "cvtps2pd", { XM
, EXq
}, PREFIX_OPCODE
},
3262 { "cvtss2sd", { XM
, EXd
}, PREFIX_OPCODE
},
3263 { "cvtpd2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3264 { "cvtsd2ss", { XM
, EXq
}, PREFIX_OPCODE
},
3269 { "cvtdq2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3270 { "cvttps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3271 { "cvtps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3276 { "subps", { XM
, EXx
}, PREFIX_OPCODE
},
3277 { "subss", { XM
, EXd
}, PREFIX_OPCODE
},
3278 { "subpd", { XM
, EXx
}, PREFIX_OPCODE
},
3279 { "subsd", { XM
, EXq
}, PREFIX_OPCODE
},
3284 { "minps", { XM
, EXx
}, PREFIX_OPCODE
},
3285 { "minss", { XM
, EXd
}, PREFIX_OPCODE
},
3286 { "minpd", { XM
, EXx
}, PREFIX_OPCODE
},
3287 { "minsd", { XM
, EXq
}, PREFIX_OPCODE
},
3292 { "divps", { XM
, EXx
}, PREFIX_OPCODE
},
3293 { "divss", { XM
, EXd
}, PREFIX_OPCODE
},
3294 { "divpd", { XM
, EXx
}, PREFIX_OPCODE
},
3295 { "divsd", { XM
, EXq
}, PREFIX_OPCODE
},
3300 { "maxps", { XM
, EXx
}, PREFIX_OPCODE
},
3301 { "maxss", { XM
, EXd
}, PREFIX_OPCODE
},
3302 { "maxpd", { XM
, EXx
}, PREFIX_OPCODE
},
3303 { "maxsd", { XM
, EXq
}, PREFIX_OPCODE
},
3308 { "punpcklbw",{ MX
, EMd
}, PREFIX_OPCODE
},
3310 { "punpcklbw",{ MX
, EMx
}, PREFIX_OPCODE
},
3315 { "punpcklwd",{ MX
, EMd
}, PREFIX_OPCODE
},
3317 { "punpcklwd",{ MX
, EMx
}, PREFIX_OPCODE
},
3322 { "punpckldq",{ MX
, EMd
}, PREFIX_OPCODE
},
3324 { "punpckldq",{ MX
, EMx
}, PREFIX_OPCODE
},
3329 { "movq", { MX
, EM
}, PREFIX_OPCODE
},
3330 { "movdqu", { XM
, EXx
}, PREFIX_OPCODE
},
3331 { "movdqa", { XM
, EXx
}, PREFIX_OPCODE
},
3336 { "pshufw", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
3337 { "pshufhw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3338 { "pshufd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3339 { "pshuflw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3344 {"vmread", { Em
, Gm
}, 0 },
3346 {"extrq", { XS
, Ib
, Ib
}, 0 },
3347 {"insertq", { XM
, XS
, Ib
, Ib
}, 0 },
3352 {"vmwrite", { Gm
, Em
}, 0 },
3354 {"extrq", { XM
, XS
}, 0 },
3355 {"insertq", { XM
, XS
}, 0 },
3362 { "haddpd", { XM
, EXx
}, PREFIX_OPCODE
},
3363 { "haddps", { XM
, EXx
}, PREFIX_OPCODE
},
3370 { "hsubpd", { XM
, EXx
}, PREFIX_OPCODE
},
3371 { "hsubps", { XM
, EXx
}, PREFIX_OPCODE
},
3376 { "movK", { Edq
, MX
}, PREFIX_OPCODE
},
3377 { "movq", { XM
, EXq
}, PREFIX_OPCODE
},
3378 { "movK", { Edq
, XM
}, PREFIX_OPCODE
},
3383 { "movq", { EMS
, MX
}, PREFIX_OPCODE
},
3384 { "movdqu", { EXxS
, XM
}, PREFIX_OPCODE
},
3385 { "movdqa", { EXxS
, XM
}, PREFIX_OPCODE
},
3388 /* PREFIX_0FAE_REG_0_MOD_3 */
3391 { "rdfsbase", { Ev
}, 0 },
3394 /* PREFIX_0FAE_REG_1_MOD_3 */
3397 { "rdgsbase", { Ev
}, 0 },
3400 /* PREFIX_0FAE_REG_2_MOD_3 */
3403 { "wrfsbase", { Ev
}, 0 },
3406 /* PREFIX_0FAE_REG_3_MOD_3 */
3409 { "wrgsbase", { Ev
}, 0 },
3412 /* PREFIX_0FAE_REG_4_MOD_0 */
3414 { "xsave", { FXSAVE
}, 0 },
3415 { "ptwrite{%LQ|}", { Edq
}, 0 },
3418 /* PREFIX_0FAE_REG_4_MOD_3 */
3421 { "ptwrite{%LQ|}", { Edq
}, 0 },
3424 /* PREFIX_0FAE_REG_5_MOD_3 */
3426 { "lfence", { Skip_MODRM
}, 0 },
3427 { "incsspK", { Edq
}, PREFIX_OPCODE
},
3430 /* PREFIX_0FAE_REG_6_MOD_0 */
3432 { "xsaveopt", { FXSAVE
}, PREFIX_OPCODE
},
3433 { "clrssbsy", { Mq
}, PREFIX_OPCODE
},
3434 { "clwb", { Mb
}, PREFIX_OPCODE
},
3437 /* PREFIX_0FAE_REG_6_MOD_3 */
3439 { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0
) },
3440 { "umonitor", { Eva
}, PREFIX_OPCODE
},
3441 { "tpause", { Edq
}, PREFIX_OPCODE
},
3442 { "umwait", { Edq
}, PREFIX_OPCODE
},
3445 /* PREFIX_0FAE_REG_7_MOD_0 */
3447 { "clflush", { Mb
}, 0 },
3449 { "clflushopt", { Mb
}, 0 },
3455 { "popcntS", { Gv
, Ev
}, 0 },
3460 { "bsfS", { Gv
, Ev
}, 0 },
3461 { "tzcntS", { Gv
, Ev
}, 0 },
3462 { "bsfS", { Gv
, Ev
}, 0 },
3467 { "bsrS", { Gv
, Ev
}, 0 },
3468 { "lzcntS", { Gv
, Ev
}, 0 },
3469 { "bsrS", { Gv
, Ev
}, 0 },
3474 { "cmpps", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
3475 { "cmpss", { XM
, EXd
, CMP
}, PREFIX_OPCODE
},
3476 { "cmppd", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
3477 { "cmpsd", { XM
, EXq
, CMP
}, PREFIX_OPCODE
},
3480 /* PREFIX_0FC7_REG_6_MOD_0 */
3482 { "vmptrld",{ Mq
}, 0 },
3483 { "vmxon", { Mq
}, 0 },
3484 { "vmclear",{ Mq
}, 0 },
3487 /* PREFIX_0FC7_REG_6_MOD_3 */
3489 { "rdrand", { Ev
}, 0 },
3491 { "rdrand", { Ev
}, 0 }
3494 /* PREFIX_0FC7_REG_7_MOD_3 */
3496 { "rdseed", { Ev
}, 0 },
3497 { "rdpid", { Em
}, 0 },
3498 { "rdseed", { Ev
}, 0 },
3505 { "addsubpd", { XM
, EXx
}, 0 },
3506 { "addsubps", { XM
, EXx
}, 0 },
3512 { "movq2dq",{ XM
, MS
}, 0 },
3513 { "movq", { EXqS
, XM
}, 0 },
3514 { "movdq2q",{ MX
, XS
}, 0 },
3520 { "cvtdq2pd", { XM
, EXq
}, PREFIX_OPCODE
},
3521 { "cvttpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3522 { "cvtpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3527 { "movntq", { Mq
, MX
}, PREFIX_OPCODE
},
3529 { MOD_TABLE (MOD_0FE7_PREFIX_2
) },
3537 { MOD_TABLE (MOD_0FF0_PREFIX_3
) },
3542 { "maskmovq", { MX
, MS
}, PREFIX_OPCODE
},
3544 { "maskmovdqu", { XM
, XS
}, PREFIX_OPCODE
},
3549 { "movbeS", { Gv
, Mv
}, PREFIX_OPCODE
},
3551 { "movbeS", { Gv
, Mv
}, PREFIX_OPCODE
},
3552 { "crc32A", { Gdq
, Eb
}, PREFIX_OPCODE
},
3557 { "movbeS", { Mv
, Gv
}, PREFIX_OPCODE
},
3559 { "movbeS", { Mv
, Gv
}, PREFIX_OPCODE
},
3560 { "crc32Q", { Gdq
, Ev
}, PREFIX_OPCODE
},
3565 { MOD_TABLE (MOD_0F38F6_PREFIX_0
) },
3566 { "adoxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
3567 { "adcxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
3574 { MOD_TABLE (MOD_0F38F8_PREFIX_1
) },
3575 { MOD_TABLE (MOD_0F38F8_PREFIX_2
) },
3576 { MOD_TABLE (MOD_0F38F8_PREFIX_3
) },
3579 /* PREFIX_VEX_0F10 */
3581 { "vmovups", { XM
, EXx
}, 0 },
3582 { "vmovss", { XMScalar
, VexScalarR
, EXxmm_md
}, 0 },
3583 { "vmovupd", { XM
, EXx
}, 0 },
3584 { "vmovsd", { XMScalar
, VexScalarR
, EXxmm_mq
}, 0 },
3587 /* PREFIX_VEX_0F11 */
3589 { "vmovups", { EXxS
, XM
}, 0 },
3590 { "vmovss", { EXdS
, VexScalarR
, XMScalar
}, 0 },
3591 { "vmovupd", { EXxS
, XM
}, 0 },
3592 { "vmovsd", { EXqS
, VexScalarR
, XMScalar
}, 0 },
3595 /* PREFIX_VEX_0F12 */
3597 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0
) },
3598 { "vmovsldup", { XM
, EXx
}, 0 },
3599 { MOD_TABLE (MOD_VEX_0F12_PREFIX_2
) },
3600 { "vmovddup", { XM
, EXymmq
}, 0 },
3603 /* PREFIX_VEX_0F16 */
3605 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0
) },
3606 { "vmovshdup", { XM
, EXx
}, 0 },
3607 { MOD_TABLE (MOD_VEX_0F16_PREFIX_2
) },
3610 /* PREFIX_VEX_0F2A */
3613 { "vcvtsi2ss{%LQ|}", { XMScalar
, VexScalar
, Edq
}, 0 },
3615 { "vcvtsi2sd{%LQ|}", { XMScalar
, VexScalar
, Edq
}, 0 },
3618 /* PREFIX_VEX_0F2C */
3621 { "vcvttss2si", { Gdq
, EXxmm_md
, EXxEVexS
}, 0 },
3623 { "vcvttsd2si", { Gdq
, EXxmm_mq
, EXxEVexS
}, 0 },
3626 /* PREFIX_VEX_0F2D */
3629 { "vcvtss2si", { Gdq
, EXxmm_md
, EXxEVexR
}, 0 },
3631 { "vcvtsd2si", { Gdq
, EXxmm_mq
, EXxEVexR
}, 0 },
3634 /* PREFIX_VEX_0F2E */
3636 { "vucomisX", { XMScalar
, EXxmm_md
, EXxEVexS
}, PREFIX_OPCODE
},
3638 { "vucomisX", { XMScalar
, EXxmm_mq
, EXxEVexS
}, PREFIX_OPCODE
},
3641 /* PREFIX_VEX_0F2F */
3643 { "vcomisX", { XMScalar
, EXxmm_md
, EXxEVexS
}, PREFIX_OPCODE
},
3645 { "vcomisX", { XMScalar
, EXxmm_mq
, EXxEVexS
}, PREFIX_OPCODE
},
3648 /* PREFIX_VEX_0F41 */
3650 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0
) },
3652 { VEX_LEN_TABLE (VEX_LEN_0F41_P_2
) },
3655 /* PREFIX_VEX_0F42 */
3657 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0
) },
3659 { VEX_LEN_TABLE (VEX_LEN_0F42_P_2
) },
3662 /* PREFIX_VEX_0F44 */
3664 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0
) },
3666 { VEX_LEN_TABLE (VEX_LEN_0F44_P_2
) },
3669 /* PREFIX_VEX_0F45 */
3671 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0
) },
3673 { VEX_LEN_TABLE (VEX_LEN_0F45_P_2
) },
3676 /* PREFIX_VEX_0F46 */
3678 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0
) },
3680 { VEX_LEN_TABLE (VEX_LEN_0F46_P_2
) },
3683 /* PREFIX_VEX_0F47 */
3685 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0
) },
3687 { VEX_LEN_TABLE (VEX_LEN_0F47_P_2
) },
3690 /* PREFIX_VEX_0F4A */
3692 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0
) },
3694 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2
) },
3697 /* PREFIX_VEX_0F4B */
3699 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0
) },
3701 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2
) },
3704 /* PREFIX_VEX_0F51 */
3706 { "vsqrtps", { XM
, EXx
}, 0 },
3707 { "vsqrtss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
3708 { "vsqrtpd", { XM
, EXx
}, 0 },
3709 { "vsqrtsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
3712 /* PREFIX_VEX_0F52 */
3714 { "vrsqrtps", { XM
, EXx
}, 0 },
3715 { "vrsqrtss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
3718 /* PREFIX_VEX_0F53 */
3720 { "vrcpps", { XM
, EXx
}, 0 },
3721 { "vrcpss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
3724 /* PREFIX_VEX_0F58 */
3726 { "vaddps", { XM
, Vex
, EXx
}, 0 },
3727 { "vaddss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
3728 { "vaddpd", { XM
, Vex
, EXx
}, 0 },
3729 { "vaddsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
3732 /* PREFIX_VEX_0F59 */
3734 { "vmulps", { XM
, Vex
, EXx
}, 0 },
3735 { "vmulss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
3736 { "vmulpd", { XM
, Vex
, EXx
}, 0 },
3737 { "vmulsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
3740 /* PREFIX_VEX_0F5A */
3742 { "vcvtps2pd", { XM
, EXxmmq
}, 0 },
3743 { "vcvtss2sd", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
3744 { "vcvtpd2ps%XY",{ XMM
, EXx
}, 0 },
3745 { "vcvtsd2ss", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
3748 /* PREFIX_VEX_0F5B */
3750 { "vcvtdq2ps", { XM
, EXx
}, 0 },
3751 { "vcvttps2dq", { XM
, EXx
}, 0 },
3752 { "vcvtps2dq", { XM
, EXx
}, 0 },
3755 /* PREFIX_VEX_0F5C */
3757 { "vsubps", { XM
, Vex
, EXx
}, 0 },
3758 { "vsubss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
3759 { "vsubpd", { XM
, Vex
, EXx
}, 0 },
3760 { "vsubsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
3763 /* PREFIX_VEX_0F5D */
3765 { "vminps", { XM
, Vex
, EXx
}, 0 },
3766 { "vminss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
3767 { "vminpd", { XM
, Vex
, EXx
}, 0 },
3768 { "vminsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
3771 /* PREFIX_VEX_0F5E */
3773 { "vdivps", { XM
, Vex
, EXx
}, 0 },
3774 { "vdivss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
3775 { "vdivpd", { XM
, Vex
, EXx
}, 0 },
3776 { "vdivsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
3779 /* PREFIX_VEX_0F5F */
3781 { "vmaxps", { XM
, Vex
, EXx
}, 0 },
3782 { "vmaxss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
3783 { "vmaxpd", { XM
, Vex
, EXx
}, 0 },
3784 { "vmaxsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
3787 /* PREFIX_VEX_0F6F */
3790 { "vmovdqu", { XM
, EXx
}, 0 },
3791 { "vmovdqa", { XM
, EXx
}, 0 },
3794 /* PREFIX_VEX_0F70 */
3797 { "vpshufhw", { XM
, EXx
, Ib
}, 0 },
3798 { "vpshufd", { XM
, EXx
, Ib
}, 0 },
3799 { "vpshuflw", { XM
, EXx
, Ib
}, 0 },
3802 /* PREFIX_VEX_0F7C */
3806 { "vhaddpd", { XM
, Vex
, EXx
}, 0 },
3807 { "vhaddps", { XM
, Vex
, EXx
}, 0 },
3810 /* PREFIX_VEX_0F7D */
3814 { "vhsubpd", { XM
, Vex
, EXx
}, 0 },
3815 { "vhsubps", { XM
, Vex
, EXx
}, 0 },
3818 /* PREFIX_VEX_0F7E */
3821 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1
) },
3822 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2
) },
3825 /* PREFIX_VEX_0F7F */
3828 { "vmovdqu", { EXxS
, XM
}, 0 },
3829 { "vmovdqa", { EXxS
, XM
}, 0 },
3832 /* PREFIX_VEX_0F90 */
3834 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0
) },
3836 { VEX_LEN_TABLE (VEX_LEN_0F90_P_2
) },
3839 /* PREFIX_VEX_0F91 */
3841 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0
) },
3843 { VEX_LEN_TABLE (VEX_LEN_0F91_P_2
) },
3846 /* PREFIX_VEX_0F92 */
3848 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0
) },
3850 { VEX_LEN_TABLE (VEX_LEN_0F92_P_2
) },
3851 { VEX_LEN_TABLE (VEX_LEN_0F92_P_3
) },
3854 /* PREFIX_VEX_0F93 */
3856 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0
) },
3858 { VEX_LEN_TABLE (VEX_LEN_0F93_P_2
) },
3859 { VEX_LEN_TABLE (VEX_LEN_0F93_P_3
) },
3862 /* PREFIX_VEX_0F98 */
3864 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0
) },
3866 { VEX_LEN_TABLE (VEX_LEN_0F98_P_2
) },
3869 /* PREFIX_VEX_0F99 */
3871 { VEX_LEN_TABLE (VEX_LEN_0F99_P_0
) },
3873 { VEX_LEN_TABLE (VEX_LEN_0F99_P_2
) },
3876 /* PREFIX_VEX_0FC2 */
3878 { "vcmpps", { XM
, Vex
, EXx
, CMP
}, 0 },
3879 { "vcmpss", { XMScalar
, VexScalar
, EXxmm_md
, CMP
}, 0 },
3880 { "vcmppd", { XM
, Vex
, EXx
, CMP
}, 0 },
3881 { "vcmpsd", { XMScalar
, VexScalar
, EXxmm_mq
, CMP
}, 0 },
3884 /* PREFIX_VEX_0FD0 */
3888 { "vaddsubpd", { XM
, Vex
, EXx
}, 0 },
3889 { "vaddsubps", { XM
, Vex
, EXx
}, 0 },
3892 /* PREFIX_VEX_0FE6 */
3895 { "vcvtdq2pd", { XM
, EXxmmq
}, 0 },
3896 { "vcvttpd2dq%XY", { XMM
, EXx
}, 0 },
3897 { "vcvtpd2dq%XY", { XMM
, EXx
}, 0 },
3900 /* PREFIX_VEX_0FF0 */
3905 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3
) },
3908 /* PREFIX_VEX_0F3849_X86_64 */
3910 { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_0
) },
3912 { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_2
) },
3913 { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_3
) },
3916 /* PREFIX_VEX_0F384B_X86_64 */
3919 { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_1
) },
3920 { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_2
) },
3921 { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_3
) },
3924 /* PREFIX_VEX_0F385C_X86_64 */
3927 { VEX_W_TABLE (VEX_W_0F385C_X86_64_P_1
) },
3931 /* PREFIX_VEX_0F385E_X86_64 */
3933 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_0
) },
3934 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_1
) },
3935 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_2
) },
3936 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_3
) },
3939 /* PREFIX_VEX_0F38F5 */
3941 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0
) },
3942 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1
) },
3944 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3
) },
3947 /* PREFIX_VEX_0F38F6 */
3952 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3
) },
3955 /* PREFIX_VEX_0F38F7 */
3957 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0
) },
3958 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1
) },
3959 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2
) },
3960 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3
) },
3963 /* PREFIX_VEX_0F3AF0 */
3968 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3
) },
3971 #include "i386-dis-evex-prefix.h"
3974 static const struct dis386 x86_64_table
[][2] = {
3977 { "pushP", { es
}, 0 },
3982 { "popP", { es
}, 0 },
3987 { "pushP", { cs
}, 0 },
3992 { "pushP", { ss
}, 0 },
3997 { "popP", { ss
}, 0 },
4002 { "pushP", { ds
}, 0 },
4007 { "popP", { ds
}, 0 },
4012 { "daa", { XX
}, 0 },
4017 { "das", { XX
}, 0 },
4022 { "aaa", { XX
}, 0 },
4027 { "aas", { XX
}, 0 },
4032 { "pushaP", { XX
}, 0 },
4037 { "popaP", { XX
}, 0 },
4042 { MOD_TABLE (MOD_62_32BIT
) },
4043 { EVEX_TABLE (EVEX_0F
) },
4048 { "arpl", { Ew
, Gw
}, 0 },
4049 { "movs", { { OP_G
, movsxd_mode
}, { MOVSXD_Fixup
, movsxd_mode
} }, 0 },
4054 { "ins{R|}", { Yzr
, indirDX
}, 0 },
4055 { "ins{G|}", { Yzr
, indirDX
}, 0 },
4060 { "outs{R|}", { indirDXr
, Xz
}, 0 },
4061 { "outs{G|}", { indirDXr
, Xz
}, 0 },
4066 /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */
4067 { REG_TABLE (REG_80
) },
4072 { "{l|}call{P|}", { Ap
}, 0 },
4077 { "retP", { Iw
, BND
}, 0 },
4078 { "ret@", { Iw
, BND
}, 0 },
4083 { "retP", { BND
}, 0 },
4084 { "ret@", { BND
}, 0 },
4089 { MOD_TABLE (MOD_C4_32BIT
) },
4090 { VEX_C4_TABLE (VEX_0F
) },
4095 { MOD_TABLE (MOD_C5_32BIT
) },
4096 { VEX_C5_TABLE (VEX_0F
) },
4101 { "into", { XX
}, 0 },
4106 { "aam", { Ib
}, 0 },
4111 { "aad", { Ib
}, 0 },
4116 { "callP", { Jv
, BND
}, 0 },
4117 { "call@", { Jv
, BND
}, 0 }
4122 { "jmpP", { Jv
, BND
}, 0 },
4123 { "jmp@", { Jv
, BND
}, 0 }
4128 { "{l|}jmp{P|}", { Ap
}, 0 },
4131 /* X86_64_0F01_REG_0 */
4133 { "sgdt{Q|Q}", { M
}, 0 },
4134 { "sgdt", { M
}, 0 },
4137 /* X86_64_0F01_REG_1 */
4139 { "sidt{Q|Q}", { M
}, 0 },
4140 { "sidt", { M
}, 0 },
4143 /* X86_64_0F01_REG_2 */
4145 { "lgdt{Q|Q}", { M
}, 0 },
4146 { "lgdt", { M
}, 0 },
4149 /* X86_64_0F01_REG_3 */
4151 { "lidt{Q|Q}", { M
}, 0 },
4152 { "lidt", { M
}, 0 },
4157 { "movZ", { Em
, Td
}, 0 },
4162 { "movZ", { Td
, Em
}, 0 },
4165 /* X86_64_VEX_0F3849 */
4168 { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64
) },
4171 /* X86_64_VEX_0F384B */
4174 { PREFIX_TABLE (PREFIX_VEX_0F384B_X86_64
) },
4177 /* X86_64_VEX_0F385C */
4180 { PREFIX_TABLE (PREFIX_VEX_0F385C_X86_64
) },
4183 /* X86_64_VEX_0F385E */
4186 { PREFIX_TABLE (PREFIX_VEX_0F385E_X86_64
) },
4190 static const struct dis386 three_byte_table
[][256] = {
4192 /* THREE_BYTE_0F38 */
4195 { "pshufb", { MX
, EM
}, PREFIX_OPCODE
},
4196 { "phaddw", { MX
, EM
}, PREFIX_OPCODE
},
4197 { "phaddd", { MX
, EM
}, PREFIX_OPCODE
},
4198 { "phaddsw", { MX
, EM
}, PREFIX_OPCODE
},
4199 { "pmaddubsw", { MX
, EM
}, PREFIX_OPCODE
},
4200 { "phsubw", { MX
, EM
}, PREFIX_OPCODE
},
4201 { "phsubd", { MX
, EM
}, PREFIX_OPCODE
},
4202 { "phsubsw", { MX
, EM
}, PREFIX_OPCODE
},
4204 { "psignb", { MX
, EM
}, PREFIX_OPCODE
},
4205 { "psignw", { MX
, EM
}, PREFIX_OPCODE
},
4206 { "psignd", { MX
, EM
}, PREFIX_OPCODE
},
4207 { "pmulhrsw", { MX
, EM
}, PREFIX_OPCODE
},
4213 { "pblendvb", { XM
, EXx
, XMM0
}, PREFIX_DATA
},
4217 { "blendvps", { XM
, EXx
, XMM0
}, PREFIX_DATA
},
4218 { "blendvpd", { XM
, EXx
, XMM0
}, PREFIX_DATA
},
4220 { "ptest", { XM
, EXx
}, PREFIX_DATA
},
4226 { "pabsb", { MX
, EM
}, PREFIX_OPCODE
},
4227 { "pabsw", { MX
, EM
}, PREFIX_OPCODE
},
4228 { "pabsd", { MX
, EM
}, PREFIX_OPCODE
},
4231 { "pmovsxbw", { XM
, EXq
}, PREFIX_DATA
},
4232 { "pmovsxbd", { XM
, EXd
}, PREFIX_DATA
},
4233 { "pmovsxbq", { XM
, EXw
}, PREFIX_DATA
},
4234 { "pmovsxwd", { XM
, EXq
}, PREFIX_DATA
},
4235 { "pmovsxwq", { XM
, EXd
}, PREFIX_DATA
},
4236 { "pmovsxdq", { XM
, EXq
}, PREFIX_DATA
},
4240 { "pmuldq", { XM
, EXx
}, PREFIX_DATA
},
4241 { "pcmpeqq", { XM
, EXx
}, PREFIX_DATA
},
4242 { MOD_TABLE (MOD_0F382A
) },
4243 { "packusdw", { XM
, EXx
}, PREFIX_DATA
},
4249 { "pmovzxbw", { XM
, EXq
}, PREFIX_DATA
},
4250 { "pmovzxbd", { XM
, EXd
}, PREFIX_DATA
},
4251 { "pmovzxbq", { XM
, EXw
}, PREFIX_DATA
},
4252 { "pmovzxwd", { XM
, EXq
}, PREFIX_DATA
},
4253 { "pmovzxwq", { XM
, EXd
}, PREFIX_DATA
},
4254 { "pmovzxdq", { XM
, EXq
}, PREFIX_DATA
},
4256 { "pcmpgtq", { XM
, EXx
}, PREFIX_DATA
},
4258 { "pminsb", { XM
, EXx
}, PREFIX_DATA
},
4259 { "pminsd", { XM
, EXx
}, PREFIX_DATA
},
4260 { "pminuw", { XM
, EXx
}, PREFIX_DATA
},
4261 { "pminud", { XM
, EXx
}, PREFIX_DATA
},
4262 { "pmaxsb", { XM
, EXx
}, PREFIX_DATA
},
4263 { "pmaxsd", { XM
, EXx
}, PREFIX_DATA
},
4264 { "pmaxuw", { XM
, EXx
}, PREFIX_DATA
},
4265 { "pmaxud", { XM
, EXx
}, PREFIX_DATA
},
4267 { "pmulld", { XM
, EXx
}, PREFIX_DATA
},
4268 { "phminposuw", { XM
, EXx
}, PREFIX_DATA
},
4339 { "invept", { Gm
, Mo
}, PREFIX_DATA
},
4340 { "invvpid", { Gm
, Mo
}, PREFIX_DATA
},
4341 { "invpcid", { Gm
, M
}, PREFIX_DATA
},
4420 { "sha1nexte", { XM
, EXxmm
}, PREFIX_OPCODE
},
4421 { "sha1msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4422 { "sha1msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4423 { "sha256rnds2", { XM
, EXxmm
, XMM0
}, PREFIX_OPCODE
},
4424 { "sha256msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4425 { "sha256msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4427 { "gf2p8mulb", { XM
, EXxmm
}, PREFIX_DATA
},
4441 { "aesimc", { XM
, EXx
}, PREFIX_DATA
},
4442 { "aesenc", { XM
, EXx
}, PREFIX_DATA
},
4443 { "aesenclast", { XM
, EXx
}, PREFIX_DATA
},
4444 { "aesdec", { XM
, EXx
}, PREFIX_DATA
},
4445 { "aesdeclast", { XM
, EXx
}, PREFIX_DATA
},
4465 { PREFIX_TABLE (PREFIX_0F38F0
) },
4466 { PREFIX_TABLE (PREFIX_0F38F1
) },
4470 { MOD_TABLE (MOD_0F38F5
) },
4471 { PREFIX_TABLE (PREFIX_0F38F6
) },
4474 { PREFIX_TABLE (PREFIX_0F38F8
) },
4475 { MOD_TABLE (MOD_0F38F9
) },
4483 /* THREE_BYTE_0F3A */
4495 { "roundps", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4496 { "roundpd", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4497 { "roundss", { XM
, EXd
, Ib
}, PREFIX_DATA
},
4498 { "roundsd", { XM
, EXq
, Ib
}, PREFIX_DATA
},
4499 { "blendps", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4500 { "blendpd", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4501 { "pblendw", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4502 { "palignr", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
4508 { "pextrb", { Edqb
, XM
, Ib
}, PREFIX_DATA
},
4509 { "pextrw", { Edqw
, XM
, Ib
}, PREFIX_DATA
},
4510 { "pextrK", { Edq
, XM
, Ib
}, PREFIX_DATA
},
4511 { "extractps", { Edqd
, XM
, Ib
}, PREFIX_DATA
},
4522 { "pinsrb", { XM
, Edqb
, Ib
}, PREFIX_DATA
},
4523 { "insertps", { XM
, EXd
, Ib
}, PREFIX_DATA
},
4524 { "pinsrK", { XM
, Edq
, Ib
}, PREFIX_DATA
},
4558 { "dpps", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4559 { "dppd", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4560 { "mpsadbw", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4562 { "pclmulqdq", { XM
, EXx
, PCLMUL
}, PREFIX_DATA
},
4594 { "pcmpestrm!%LQ", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4595 { "pcmpestri!%LQ", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4596 { "pcmpistrm", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4597 { "pcmpistri", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4715 { "sha1rnds4", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4717 { "gf2p8affineqb", { XM
, EXxmm
, Ib
}, PREFIX_DATA
},
4718 { "gf2p8affineinvqb", { XM
, EXxmm
, Ib
}, PREFIX_DATA
},
4736 { "aeskeygenassist", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4776 static const struct dis386 xop_table
[][256] = {
4929 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_85
) },
4930 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_86
) },
4931 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_87
) },
4939 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8E
) },
4940 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8F
) },
4947 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_95
) },
4948 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_96
) },
4949 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_97
) },
4957 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9E
) },
4958 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9F
) },
4962 { "vpcmov", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
4963 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A3
) },
4966 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A6
) },
4984 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_B6
) },
4996 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C0
) },
4997 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C1
) },
4998 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C2
) },
4999 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C3
) },
5009 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC
) },
5010 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD
) },
5011 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE
) },
5012 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF
) },
5045 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC
) },
5046 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED
) },
5047 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE
) },
5048 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF
) },
5072 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_01
) },
5073 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_02
) },
5091 { MOD_TABLE (MOD_VEX_0FXOP_09_12
) },
5215 { VEX_W_TABLE (VEX_W_0FXOP_09_80
) },
5216 { VEX_W_TABLE (VEX_W_0FXOP_09_81
) },
5217 { VEX_W_TABLE (VEX_W_0FXOP_09_82
) },
5218 { VEX_W_TABLE (VEX_W_0FXOP_09_83
) },
5233 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_90
) },
5234 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_91
) },
5235 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_92
) },
5236 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_93
) },
5237 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_94
) },
5238 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_95
) },
5239 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_96
) },
5240 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_97
) },
5242 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_98
) },
5243 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_99
) },
5244 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9A
) },
5245 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9B
) },
5288 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C1
) },
5289 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C2
) },
5290 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C3
) },
5293 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C6
) },
5294 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C7
) },
5299 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_CB
) },
5306 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D1
) },
5307 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D2
) },
5308 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D3
) },
5311 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D6
) },
5312 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D7
) },
5317 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_DB
) },
5324 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E1
) },
5325 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E2
) },
5326 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E3
) },
5380 { "bextrS", { Gdq
, Edq
, Id
}, 0 },
5382 { VEX_LEN_TABLE (VEX_LEN_0FXOP_0A_12
) },
5652 static const struct dis386 vex_table
[][256] = {
5674 { PREFIX_TABLE (PREFIX_VEX_0F10
) },
5675 { PREFIX_TABLE (PREFIX_VEX_0F11
) },
5676 { PREFIX_TABLE (PREFIX_VEX_0F12
) },
5677 { MOD_TABLE (MOD_VEX_0F13
) },
5678 { "vunpcklpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
5679 { "vunpckhpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
5680 { PREFIX_TABLE (PREFIX_VEX_0F16
) },
5681 { MOD_TABLE (MOD_VEX_0F17
) },
5701 { "vmovapX", { XM
, EXx
}, PREFIX_OPCODE
},
5702 { "vmovapX", { EXxS
, XM
}, PREFIX_OPCODE
},
5703 { PREFIX_TABLE (PREFIX_VEX_0F2A
) },
5704 { MOD_TABLE (MOD_VEX_0F2B
) },
5705 { PREFIX_TABLE (PREFIX_VEX_0F2C
) },
5706 { PREFIX_TABLE (PREFIX_VEX_0F2D
) },
5707 { PREFIX_TABLE (PREFIX_VEX_0F2E
) },
5708 { PREFIX_TABLE (PREFIX_VEX_0F2F
) },
5729 { PREFIX_TABLE (PREFIX_VEX_0F41
) },
5730 { PREFIX_TABLE (PREFIX_VEX_0F42
) },
5732 { PREFIX_TABLE (PREFIX_VEX_0F44
) },
5733 { PREFIX_TABLE (PREFIX_VEX_0F45
) },
5734 { PREFIX_TABLE (PREFIX_VEX_0F46
) },
5735 { PREFIX_TABLE (PREFIX_VEX_0F47
) },
5739 { PREFIX_TABLE (PREFIX_VEX_0F4A
) },
5740 { PREFIX_TABLE (PREFIX_VEX_0F4B
) },
5746 { MOD_TABLE (MOD_VEX_0F50
) },
5747 { PREFIX_TABLE (PREFIX_VEX_0F51
) },
5748 { PREFIX_TABLE (PREFIX_VEX_0F52
) },
5749 { PREFIX_TABLE (PREFIX_VEX_0F53
) },
5750 { "vandpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
5751 { "vandnpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
5752 { "vorpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
5753 { "vxorpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
5755 { PREFIX_TABLE (PREFIX_VEX_0F58
) },
5756 { PREFIX_TABLE (PREFIX_VEX_0F59
) },
5757 { PREFIX_TABLE (PREFIX_VEX_0F5A
) },
5758 { PREFIX_TABLE (PREFIX_VEX_0F5B
) },
5759 { PREFIX_TABLE (PREFIX_VEX_0F5C
) },
5760 { PREFIX_TABLE (PREFIX_VEX_0F5D
) },
5761 { PREFIX_TABLE (PREFIX_VEX_0F5E
) },
5762 { PREFIX_TABLE (PREFIX_VEX_0F5F
) },
5764 { "vpunpcklbw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5765 { "vpunpcklwd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5766 { "vpunpckldq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5767 { "vpacksswb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5768 { "vpcmpgtb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5769 { "vpcmpgtw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5770 { "vpcmpgtd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5771 { "vpackuswb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5773 { "vpunpckhbw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5774 { "vpunpckhwd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5775 { "vpunpckhdq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5776 { "vpackssdw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5777 { "vpunpcklqdq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5778 { "vpunpckhqdq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5779 { VEX_LEN_TABLE (VEX_LEN_0F6E
) },
5780 { PREFIX_TABLE (PREFIX_VEX_0F6F
) },
5782 { PREFIX_TABLE (PREFIX_VEX_0F70
) },
5783 { REG_TABLE (REG_VEX_0F71
) },
5784 { REG_TABLE (REG_VEX_0F72
) },
5785 { REG_TABLE (REG_VEX_0F73
) },
5786 { "vpcmpeqb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5787 { "vpcmpeqw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5788 { "vpcmpeqd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5789 { VEX_LEN_TABLE (VEX_LEN_0F77
) },
5795 { PREFIX_TABLE (PREFIX_VEX_0F7C
) },
5796 { PREFIX_TABLE (PREFIX_VEX_0F7D
) },
5797 { PREFIX_TABLE (PREFIX_VEX_0F7E
) },
5798 { PREFIX_TABLE (PREFIX_VEX_0F7F
) },
5818 { PREFIX_TABLE (PREFIX_VEX_0F90
) },
5819 { PREFIX_TABLE (PREFIX_VEX_0F91
) },
5820 { PREFIX_TABLE (PREFIX_VEX_0F92
) },
5821 { PREFIX_TABLE (PREFIX_VEX_0F93
) },
5827 { PREFIX_TABLE (PREFIX_VEX_0F98
) },
5828 { PREFIX_TABLE (PREFIX_VEX_0F99
) },
5851 { REG_TABLE (REG_VEX_0FAE
) },
5874 { PREFIX_TABLE (PREFIX_VEX_0FC2
) },
5876 { VEX_LEN_TABLE (VEX_LEN_0FC4
) },
5877 { VEX_LEN_TABLE (VEX_LEN_0FC5
) },
5878 { "vshufpX", { XM
, Vex
, EXx
, Ib
}, PREFIX_OPCODE
},
5890 { PREFIX_TABLE (PREFIX_VEX_0FD0
) },
5891 { "vpsrlw", { XM
, Vex
, EXxmm
}, PREFIX_DATA
},
5892 { "vpsrld", { XM
, Vex
, EXxmm
}, PREFIX_DATA
},
5893 { "vpsrlq", { XM
, Vex
, EXxmm
}, PREFIX_DATA
},
5894 { "vpaddq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5895 { "vpmullw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5896 { VEX_LEN_TABLE (VEX_LEN_0FD6
) },
5897 { MOD_TABLE (MOD_VEX_0FD7
) },
5899 { "vpsubusb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5900 { "vpsubusw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5901 { "vpminub", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5902 { "vpand", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5903 { "vpaddusb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5904 { "vpaddusw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5905 { "vpmaxub", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5906 { "vpandn", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5908 { "vpavgb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5909 { "vpsraw", { XM
, Vex
, EXxmm
}, PREFIX_DATA
},
5910 { "vpsrad", { XM
, Vex
, EXxmm
}, PREFIX_DATA
},
5911 { "vpavgw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5912 { "vpmulhuw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5913 { "vpmulhw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5914 { PREFIX_TABLE (PREFIX_VEX_0FE6
) },
5915 { MOD_TABLE (MOD_VEX_0FE7
) },
5917 { "vpsubsb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5918 { "vpsubsw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5919 { "vpminsw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5920 { "vpor", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5921 { "vpaddsb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5922 { "vpaddsw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5923 { "vpmaxsw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5924 { "vpxor", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5926 { PREFIX_TABLE (PREFIX_VEX_0FF0
) },
5927 { "vpsllw", { XM
, Vex
, EXxmm
}, PREFIX_DATA
},
5928 { "vpslld", { XM
, Vex
, EXxmm
}, PREFIX_DATA
},
5929 { "vpsllq", { XM
, Vex
, EXxmm
}, PREFIX_DATA
},
5930 { "vpmuludq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5931 { "vpmaddwd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5932 { "vpsadbw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5933 { VEX_LEN_TABLE (VEX_LEN_0FF7
) },
5935 { "vpsubb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5936 { "vpsubw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5937 { "vpsubd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5938 { "vpsubq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5939 { "vpaddb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5940 { "vpaddw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5941 { "vpaddd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5947 { "vpshufb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5948 { "vphaddw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5949 { "vphaddd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5950 { "vphaddsw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5951 { "vpmaddubsw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5952 { "vphsubw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5953 { "vphsubd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5954 { "vphsubsw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5956 { "vpsignb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5957 { "vpsignw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5958 { "vpsignd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5959 { "vpmulhrsw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5960 { VEX_W_TABLE (VEX_W_0F380C
) },
5961 { VEX_W_TABLE (VEX_W_0F380D
) },
5962 { VEX_W_TABLE (VEX_W_0F380E
) },
5963 { VEX_W_TABLE (VEX_W_0F380F
) },
5968 { VEX_W_TABLE (VEX_W_0F3813
) },
5971 { VEX_LEN_TABLE (VEX_LEN_0F3816
) },
5972 { "vptest", { XM
, EXx
}, PREFIX_DATA
},
5974 { VEX_W_TABLE (VEX_W_0F3818
) },
5975 { VEX_LEN_TABLE (VEX_LEN_0F3819
) },
5976 { MOD_TABLE (MOD_VEX_0F381A
) },
5978 { "vpabsb", { XM
, EXx
}, PREFIX_DATA
},
5979 { "vpabsw", { XM
, EXx
}, PREFIX_DATA
},
5980 { "vpabsd", { XM
, EXx
}, PREFIX_DATA
},
5983 { "vpmovsxbw", { XM
, EXxmmq
}, PREFIX_DATA
},
5984 { "vpmovsxbd", { XM
, EXxmmqd
}, PREFIX_DATA
},
5985 { "vpmovsxbq", { XM
, EXxmmdw
}, PREFIX_DATA
},
5986 { "vpmovsxwd", { XM
, EXxmmq
}, PREFIX_DATA
},
5987 { "vpmovsxwq", { XM
, EXxmmqd
}, PREFIX_DATA
},
5988 { "vpmovsxdq", { XM
, EXxmmq
}, PREFIX_DATA
},
5992 { "vpmuldq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5993 { "vpcmpeqq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5994 { MOD_TABLE (MOD_VEX_0F382A
) },
5995 { "vpackusdw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5996 { MOD_TABLE (MOD_VEX_0F382C
) },
5997 { MOD_TABLE (MOD_VEX_0F382D
) },
5998 { MOD_TABLE (MOD_VEX_0F382E
) },
5999 { MOD_TABLE (MOD_VEX_0F382F
) },
6001 { "vpmovzxbw", { XM
, EXxmmq
}, PREFIX_DATA
},
6002 { "vpmovzxbd", { XM
, EXxmmqd
}, PREFIX_DATA
},
6003 { "vpmovzxbq", { XM
, EXxmmdw
}, PREFIX_DATA
},
6004 { "vpmovzxwd", { XM
, EXxmmq
}, PREFIX_DATA
},
6005 { "vpmovzxwq", { XM
, EXxmmqd
}, PREFIX_DATA
},
6006 { "vpmovzxdq", { XM
, EXxmmq
}, PREFIX_DATA
},
6007 { VEX_LEN_TABLE (VEX_LEN_0F3836
) },
6008 { "vpcmpgtq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6010 { "vpminsb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6011 { "vpminsd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6012 { "vpminuw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6013 { "vpminud", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6014 { "vpmaxsb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6015 { "vpmaxsd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6016 { "vpmaxuw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6017 { "vpmaxud", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6019 { "vpmulld", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6020 { VEX_LEN_TABLE (VEX_LEN_0F3841
) },
6024 { "vpsrlv%DQ", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6025 { VEX_W_TABLE (VEX_W_0F3846
) },
6026 { "vpsllv%DQ", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6029 { X86_64_TABLE (X86_64_VEX_0F3849
) },
6031 { X86_64_TABLE (X86_64_VEX_0F384B
) },
6046 { VEX_W_TABLE (VEX_W_0F3858
) },
6047 { VEX_W_TABLE (VEX_W_0F3859
) },
6048 { MOD_TABLE (MOD_VEX_0F385A
) },
6050 { X86_64_TABLE (X86_64_VEX_0F385C
) },
6052 { X86_64_TABLE (X86_64_VEX_0F385E
) },
6082 { VEX_W_TABLE (VEX_W_0F3878
) },
6083 { VEX_W_TABLE (VEX_W_0F3879
) },
6104 { MOD_TABLE (MOD_VEX_0F388C
) },
6106 { MOD_TABLE (MOD_VEX_0F388E
) },
6109 { "vpgatherd%DQ", { XM
, MVexVSIBDWpX
, Vex
}, PREFIX_DATA
},
6110 { "vpgatherq%DQ", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, PREFIX_DATA
},
6111 { "vgatherdp%XW", { XM
, MVexVSIBDWpX
, Vex
}, PREFIX_DATA
},
6112 { "vgatherqp%XW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, PREFIX_DATA
},
6115 { "vfmaddsub132p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6116 { "vfmsubadd132p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6118 { "vfmadd132p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6119 { "vfmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6120 { "vfmsub132p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6121 { "vfmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6122 { "vfnmadd132p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6123 { "vfnmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6124 { "vfnmsub132p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6125 { "vfnmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6133 { "vfmaddsub213p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6134 { "vfmsubadd213p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6136 { "vfmadd213p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6137 { "vfmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6138 { "vfmsub213p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6139 { "vfmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6140 { "vfnmadd213p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6141 { "vfnmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6142 { "vfnmsub213p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6143 { "vfnmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6151 { "vfmaddsub231p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6152 { "vfmsubadd231p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6154 { "vfmadd231p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6155 { "vfmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6156 { "vfmsub231p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6157 { "vfmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6158 { "vfnmadd231p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6159 { "vfnmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6160 { "vfnmsub231p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6161 { "vfnmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6179 { VEX_W_TABLE (VEX_W_0F38CF
) },
6193 { VEX_LEN_TABLE (VEX_LEN_0F38DB
) },
6194 { "vaesenc", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6195 { "vaesenclast", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6196 { "vaesdec", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6197 { "vaesdeclast", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6219 { VEX_LEN_TABLE (VEX_LEN_0F38F2
) },
6220 { REG_TABLE (REG_VEX_0F38F3
) },
6222 { PREFIX_TABLE (PREFIX_VEX_0F38F5
) },
6223 { PREFIX_TABLE (PREFIX_VEX_0F38F6
) },
6224 { PREFIX_TABLE (PREFIX_VEX_0F38F7
) },
6238 { VEX_LEN_TABLE (VEX_LEN_0F3A00
) },
6239 { VEX_LEN_TABLE (VEX_LEN_0F3A01
) },
6240 { VEX_W_TABLE (VEX_W_0F3A02
) },
6242 { VEX_W_TABLE (VEX_W_0F3A04
) },
6243 { VEX_W_TABLE (VEX_W_0F3A05
) },
6244 { VEX_LEN_TABLE (VEX_LEN_0F3A06
) },
6247 { "vroundps", { XM
, EXx
, Ib
}, PREFIX_DATA
},
6248 { "vroundpd", { XM
, EXx
, Ib
}, PREFIX_DATA
},
6249 { "vroundss", { XMScalar
, VexScalar
, EXxmm_md
, Ib
}, PREFIX_DATA
},
6250 { "vroundsd", { XMScalar
, VexScalar
, EXxmm_mq
, Ib
}, PREFIX_DATA
},
6251 { "vblendps", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
6252 { "vblendpd", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
6253 { "vpblendw", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
6254 { "vpalignr", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
6260 { VEX_LEN_TABLE (VEX_LEN_0F3A14
) },
6261 { VEX_LEN_TABLE (VEX_LEN_0F3A15
) },
6262 { VEX_LEN_TABLE (VEX_LEN_0F3A16
) },
6263 { VEX_LEN_TABLE (VEX_LEN_0F3A17
) },
6265 { VEX_LEN_TABLE (VEX_LEN_0F3A18
) },
6266 { VEX_LEN_TABLE (VEX_LEN_0F3A19
) },
6270 { VEX_W_TABLE (VEX_W_0F3A1D
) },
6274 { VEX_LEN_TABLE (VEX_LEN_0F3A20
) },
6275 { VEX_LEN_TABLE (VEX_LEN_0F3A21
) },
6276 { VEX_LEN_TABLE (VEX_LEN_0F3A22
) },
6292 { VEX_LEN_TABLE (VEX_LEN_0F3A30
) },
6293 { VEX_LEN_TABLE (VEX_LEN_0F3A31
) },
6294 { VEX_LEN_TABLE (VEX_LEN_0F3A32
) },
6295 { VEX_LEN_TABLE (VEX_LEN_0F3A33
) },
6301 { VEX_LEN_TABLE (VEX_LEN_0F3A38
) },
6302 { VEX_LEN_TABLE (VEX_LEN_0F3A39
) },
6310 { "vdpps", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
6311 { VEX_LEN_TABLE (VEX_LEN_0F3A41
) },
6312 { "vmpsadbw", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
6314 { "vpclmulqdq", { XM
, Vex
, EXx
, PCLMUL
}, PREFIX_DATA
},
6316 { VEX_LEN_TABLE (VEX_LEN_0F3A46
) },
6319 { "vpermil2ps", { XM
, Vex
, EXx
, XMVexI4
, VexI4
}, PREFIX_DATA
},
6320 { "vpermil2pd", { XM
, Vex
, EXx
, XMVexI4
, VexI4
}, PREFIX_DATA
},
6321 { VEX_W_TABLE (VEX_W_0F3A4A
) },
6322 { VEX_W_TABLE (VEX_W_0F3A4B
) },
6323 { VEX_W_TABLE (VEX_W_0F3A4C
) },
6341 { "vfmaddsubps", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6342 { "vfmaddsubpd", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6343 { "vfmsubaddps", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6344 { "vfmsubaddpd", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6346 { VEX_LEN_TABLE (VEX_LEN_0F3A60
) },
6347 { VEX_LEN_TABLE (VEX_LEN_0F3A61
) },
6348 { VEX_LEN_TABLE (VEX_LEN_0F3A62
) },
6349 { VEX_LEN_TABLE (VEX_LEN_0F3A63
) },
6355 { "vfmaddps", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6356 { "vfmaddpd", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6357 { "vfmaddss", { XMScalar
, VexScalar
, EXxmm_md
, XMVexScalarI4
}, PREFIX_DATA
},
6358 { "vfmaddsd", { XMScalar
, VexScalar
, EXxmm_mq
, XMVexScalarI4
}, PREFIX_DATA
},
6359 { "vfmsubps", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6360 { "vfmsubpd", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6361 { "vfmsubss", { XMScalar
, VexScalar
, EXxmm_md
, XMVexScalarI4
}, PREFIX_DATA
},
6362 { "vfmsubsd", { XMScalar
, VexScalar
, EXxmm_mq
, XMVexScalarI4
}, PREFIX_DATA
},
6373 { "vfnmaddps", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6374 { "vfnmaddpd", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6375 { "vfnmaddss", { XMScalar
, VexScalar
, EXxmm_md
, XMVexScalarI4
}, PREFIX_DATA
},
6376 { "vfnmaddsd", { XMScalar
, VexScalar
, EXxmm_mq
, XMVexScalarI4
}, PREFIX_DATA
},
6377 { "vfnmsubps", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6378 { "vfnmsubpd", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6379 { "vfnmsubss", { XMScalar
, VexScalar
, EXxmm_md
, XMVexScalarI4
}, PREFIX_DATA
},
6380 { "vfnmsubsd", { XMScalar
, VexScalar
, EXxmm_mq
, XMVexScalarI4
}, PREFIX_DATA
},
6469 { VEX_W_TABLE (VEX_W_0F3ACE
) },
6470 { VEX_W_TABLE (VEX_W_0F3ACF
) },
6488 { VEX_LEN_TABLE (VEX_LEN_0F3ADF
) },
6508 { PREFIX_TABLE (PREFIX_VEX_0F3AF0
) },
6528 #include "i386-dis-evex.h"
6530 static const struct dis386 vex_len_table
[][2] = {
6531 /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */
6533 { "vmovlpX", { XM
, Vex
, EXq
}, 0 },
6536 /* VEX_LEN_0F12_P_0_M_1 */
6538 { "vmovhlps", { XM
, Vex
, EXq
}, 0 },
6541 /* VEX_LEN_0F13_M_0 */
6543 { "vmovlpX", { EXq
, XM
}, PREFIX_OPCODE
},
6546 /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */
6548 { "vmovhpX", { XM
, Vex
, EXq
}, 0 },
6551 /* VEX_LEN_0F16_P_0_M_1 */
6553 { "vmovlhps", { XM
, Vex
, EXq
}, 0 },
6556 /* VEX_LEN_0F17_M_0 */
6558 { "vmovhpX", { EXq
, XM
}, PREFIX_OPCODE
},
6561 /* VEX_LEN_0F41_P_0 */
6564 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1
) },
6566 /* VEX_LEN_0F41_P_2 */
6569 { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1
) },
6571 /* VEX_LEN_0F42_P_0 */
6574 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1
) },
6576 /* VEX_LEN_0F42_P_2 */
6579 { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1
) },
6581 /* VEX_LEN_0F44_P_0 */
6583 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0
) },
6585 /* VEX_LEN_0F44_P_2 */
6587 { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0
) },
6589 /* VEX_LEN_0F45_P_0 */
6592 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1
) },
6594 /* VEX_LEN_0F45_P_2 */
6597 { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1
) },
6599 /* VEX_LEN_0F46_P_0 */
6602 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1
) },
6604 /* VEX_LEN_0F46_P_2 */
6607 { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1
) },
6609 /* VEX_LEN_0F47_P_0 */
6612 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1
) },
6614 /* VEX_LEN_0F47_P_2 */
6617 { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1
) },
6619 /* VEX_LEN_0F4A_P_0 */
6622 { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1
) },
6624 /* VEX_LEN_0F4A_P_2 */
6627 { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1
) },
6629 /* VEX_LEN_0F4B_P_0 */
6632 { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1
) },
6634 /* VEX_LEN_0F4B_P_2 */
6637 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1
) },
6642 { "vmovK", { XMScalar
, Edq
}, PREFIX_DATA
},
6647 { "vzeroupper", { XX
}, 0 },
6648 { "vzeroall", { XX
}, 0 },
6651 /* VEX_LEN_0F7E_P_1 */
6653 { "vmovq", { XMScalar
, EXxmm_mq
}, 0 },
6656 /* VEX_LEN_0F7E_P_2 */
6658 { "vmovK", { Edq
, XMScalar
}, 0 },
6661 /* VEX_LEN_0F90_P_0 */
6663 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0
) },
6666 /* VEX_LEN_0F90_P_2 */
6668 { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0
) },
6671 /* VEX_LEN_0F91_P_0 */
6673 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0
) },
6676 /* VEX_LEN_0F91_P_2 */
6678 { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0
) },
6681 /* VEX_LEN_0F92_P_0 */
6683 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0
) },
6686 /* VEX_LEN_0F92_P_2 */
6688 { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0
) },
6691 /* VEX_LEN_0F92_P_3 */
6693 { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0
) },
6696 /* VEX_LEN_0F93_P_0 */
6698 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0
) },
6701 /* VEX_LEN_0F93_P_2 */
6703 { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0
) },
6706 /* VEX_LEN_0F93_P_3 */
6708 { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0
) },
6711 /* VEX_LEN_0F98_P_0 */
6713 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0
) },
6716 /* VEX_LEN_0F98_P_2 */
6718 { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0
) },
6721 /* VEX_LEN_0F99_P_0 */
6723 { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0
) },
6726 /* VEX_LEN_0F99_P_2 */
6728 { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0
) },
6731 /* VEX_LEN_0FAE_R_2_M_0 */
6733 { "vldmxcsr", { Md
}, 0 },
6736 /* VEX_LEN_0FAE_R_3_M_0 */
6738 { "vstmxcsr", { Md
}, 0 },
6743 { "vpinsrw", { XM
, Vex
, Edqw
, Ib
}, PREFIX_DATA
},
6748 { "vpextrw", { Gdq
, XS
, Ib
}, PREFIX_DATA
},
6753 { "vmovq", { EXqS
, XMScalar
}, PREFIX_DATA
},
6758 { "vmaskmovdqu", { XM
, XS
}, PREFIX_DATA
},
6761 /* VEX_LEN_0F3816 */
6764 { VEX_W_TABLE (VEX_W_0F3816_L_1
) },
6767 /* VEX_LEN_0F3819 */
6770 { VEX_W_TABLE (VEX_W_0F3819_L_1
) },
6773 /* VEX_LEN_0F381A_M_0 */
6776 { VEX_W_TABLE (VEX_W_0F381A_M_0_L_1
) },
6779 /* VEX_LEN_0F3836 */
6782 { VEX_W_TABLE (VEX_W_0F3836
) },
6785 /* VEX_LEN_0F3841 */
6787 { "vphminposuw", { XM
, EXx
}, PREFIX_DATA
},
6790 /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_0 */
6792 { "ldtilecfg", { M
}, 0 },
6795 /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0 */
6797 { "tilerelease", { Skip_MODRM
}, 0 },
6800 /* VEX_LEN_0F3849_X86_64_P_2_W_0_M_0 */
6802 { "sttilecfg", { M
}, 0 },
6805 /* VEX_LEN_0F3849_X86_64_P_3_W_0_M_0 */
6807 { "tilezero", { TMM
, Skip_MODRM
}, 0 },
6810 /* VEX_LEN_0F384B_X86_64_P_1_W_0_M_0 */
6812 { "tilestored", { MVexSIBMEM
, TMM
}, 0 },
6814 /* VEX_LEN_0F384B_X86_64_P_2_W_0_M_0 */
6816 { "tileloaddt1", { TMM
, MVexSIBMEM
}, 0 },
6819 /* VEX_LEN_0F384B_X86_64_P_3_W_0_M_0 */
6821 { "tileloadd", { TMM
, MVexSIBMEM
}, 0 },
6824 /* VEX_LEN_0F385A_M_0 */
6827 { VEX_W_TABLE (VEX_W_0F385A_M_0_L_0
) },
6830 /* VEX_LEN_0F385C_X86_64_P_1_W_0_M_0 */
6832 { "tdpbf16ps", { TMM
, EXtmm
, VexTmm
}, 0 },
6835 /* VEX_LEN_0F385E_X86_64_P_0_W_0_M_0 */
6837 { "tdpbuud", {TMM
, EXtmm
, VexTmm
}, 0 },
6840 /* VEX_LEN_0F385E_X86_64_P_1_W_0_M_0 */
6842 { "tdpbsud", {TMM
, EXtmm
, VexTmm
}, 0 },
6845 /* VEX_LEN_0F385E_X86_64_P_2_W_0_M_0 */
6847 { "tdpbusd", {TMM
, EXtmm
, VexTmm
}, 0 },
6850 /* VEX_LEN_0F385E_X86_64_P_3_W_0_M_0 */
6852 { "tdpbssd", {TMM
, EXtmm
, VexTmm
}, 0 },
6855 /* VEX_LEN_0F38DB */
6857 { "vaesimc", { XM
, EXx
}, PREFIX_DATA
},
6860 /* VEX_LEN_0F38F2 */
6862 { "andnS", { Gdq
, VexGdq
, Edq
}, PREFIX_OPCODE
},
6865 /* VEX_LEN_0F38F3_R_1 */
6867 { "blsrS", { VexGdq
, Edq
}, PREFIX_OPCODE
},
6870 /* VEX_LEN_0F38F3_R_2 */
6872 { "blsmskS", { VexGdq
, Edq
}, PREFIX_OPCODE
},
6875 /* VEX_LEN_0F38F3_R_3 */
6877 { "blsiS", { VexGdq
, Edq
}, PREFIX_OPCODE
},
6880 /* VEX_LEN_0F38F5_P_0 */
6882 { "bzhiS", { Gdq
, Edq
, VexGdq
}, 0 },
6885 /* VEX_LEN_0F38F5_P_1 */
6887 { "pextS", { Gdq
, VexGdq
, Edq
}, 0 },
6890 /* VEX_LEN_0F38F5_P_3 */
6892 { "pdepS", { Gdq
, VexGdq
, Edq
}, 0 },
6895 /* VEX_LEN_0F38F6_P_3 */
6897 { "mulxS", { Gdq
, VexGdq
, Edq
}, 0 },
6900 /* VEX_LEN_0F38F7_P_0 */
6902 { "bextrS", { Gdq
, Edq
, VexGdq
}, 0 },
6905 /* VEX_LEN_0F38F7_P_1 */
6907 { "sarxS", { Gdq
, Edq
, VexGdq
}, 0 },
6910 /* VEX_LEN_0F38F7_P_2 */
6912 { "shlxS", { Gdq
, Edq
, VexGdq
}, 0 },
6915 /* VEX_LEN_0F38F7_P_3 */
6917 { "shrxS", { Gdq
, Edq
, VexGdq
}, 0 },
6920 /* VEX_LEN_0F3A00 */
6923 { VEX_W_TABLE (VEX_W_0F3A00_L_1
) },
6926 /* VEX_LEN_0F3A01 */
6929 { VEX_W_TABLE (VEX_W_0F3A01_L_1
) },
6932 /* VEX_LEN_0F3A06 */
6935 { VEX_W_TABLE (VEX_W_0F3A06_L_1
) },
6938 /* VEX_LEN_0F3A14 */
6940 { "vpextrb", { Edqb
, XM
, Ib
}, PREFIX_DATA
},
6943 /* VEX_LEN_0F3A15 */
6945 { "vpextrw", { Edqw
, XM
, Ib
}, PREFIX_DATA
},
6948 /* VEX_LEN_0F3A16 */
6950 { "vpextrK", { Edq
, XM
, Ib
}, PREFIX_DATA
},
6953 /* VEX_LEN_0F3A17 */
6955 { "vextractps", { Edqd
, XM
, Ib
}, PREFIX_DATA
},
6958 /* VEX_LEN_0F3A18 */
6961 { VEX_W_TABLE (VEX_W_0F3A18_L_1
) },
6964 /* VEX_LEN_0F3A19 */
6967 { VEX_W_TABLE (VEX_W_0F3A19_L_1
) },
6970 /* VEX_LEN_0F3A20 */
6972 { "vpinsrb", { XM
, Vex
, Edqb
, Ib
}, PREFIX_DATA
},
6975 /* VEX_LEN_0F3A21 */
6977 { "vinsertps", { XM
, Vex
, EXd
, Ib
}, PREFIX_DATA
},
6980 /* VEX_LEN_0F3A22 */
6982 { "vpinsrK", { XM
, Vex
, Edq
, Ib
}, PREFIX_DATA
},
6985 /* VEX_LEN_0F3A30 */
6987 { MOD_TABLE (MOD_VEX_0F3A30_L_0
) },
6990 /* VEX_LEN_0F3A31 */
6992 { MOD_TABLE (MOD_VEX_0F3A31_L_0
) },
6995 /* VEX_LEN_0F3A32 */
6997 { MOD_TABLE (MOD_VEX_0F3A32_L_0
) },
7000 /* VEX_LEN_0F3A33 */
7002 { MOD_TABLE (MOD_VEX_0F3A33_L_0
) },
7005 /* VEX_LEN_0F3A38 */
7008 { VEX_W_TABLE (VEX_W_0F3A38_L_1
) },
7011 /* VEX_LEN_0F3A39 */
7014 { VEX_W_TABLE (VEX_W_0F3A39_L_1
) },
7017 /* VEX_LEN_0F3A41 */
7019 { "vdppd", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
7022 /* VEX_LEN_0F3A46 */
7025 { VEX_W_TABLE (VEX_W_0F3A46_L_1
) },
7028 /* VEX_LEN_0F3A60 */
7030 { "vpcmpestrm!%LQ", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7033 /* VEX_LEN_0F3A61 */
7035 { "vpcmpestri!%LQ", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7038 /* VEX_LEN_0F3A62 */
7040 { "vpcmpistrm", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7043 /* VEX_LEN_0F3A63 */
7045 { "vpcmpistri", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7048 /* VEX_LEN_0F3ADF */
7050 { "vaeskeygenassist", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7053 /* VEX_LEN_0F3AF0_P_3 */
7055 { "rorxS", { Gdq
, Edq
, Ib
}, 0 },
7058 /* VEX_LEN_0FXOP_08_85 */
7060 { VEX_W_TABLE (VEX_W_0FXOP_08_85_L_0
) },
7063 /* VEX_LEN_0FXOP_08_86 */
7065 { VEX_W_TABLE (VEX_W_0FXOP_08_86_L_0
) },
7068 /* VEX_LEN_0FXOP_08_87 */
7070 { VEX_W_TABLE (VEX_W_0FXOP_08_87_L_0
) },
7073 /* VEX_LEN_0FXOP_08_8E */
7075 { VEX_W_TABLE (VEX_W_0FXOP_08_8E_L_0
) },
7078 /* VEX_LEN_0FXOP_08_8F */
7080 { VEX_W_TABLE (VEX_W_0FXOP_08_8F_L_0
) },
7083 /* VEX_LEN_0FXOP_08_95 */
7085 { VEX_W_TABLE (VEX_W_0FXOP_08_95_L_0
) },
7088 /* VEX_LEN_0FXOP_08_96 */
7090 { VEX_W_TABLE (VEX_W_0FXOP_08_96_L_0
) },
7093 /* VEX_LEN_0FXOP_08_97 */
7095 { VEX_W_TABLE (VEX_W_0FXOP_08_97_L_0
) },
7098 /* VEX_LEN_0FXOP_08_9E */
7100 { VEX_W_TABLE (VEX_W_0FXOP_08_9E_L_0
) },
7103 /* VEX_LEN_0FXOP_08_9F */
7105 { VEX_W_TABLE (VEX_W_0FXOP_08_9F_L_0
) },
7108 /* VEX_LEN_0FXOP_08_A3 */
7110 { "vpperm", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7113 /* VEX_LEN_0FXOP_08_A6 */
7115 { VEX_W_TABLE (VEX_W_0FXOP_08_A6_L_0
) },
7118 /* VEX_LEN_0FXOP_08_B6 */
7120 { VEX_W_TABLE (VEX_W_0FXOP_08_B6_L_0
) },
7123 /* VEX_LEN_0FXOP_08_C0 */
7125 { VEX_W_TABLE (VEX_W_0FXOP_08_C0_L_0
) },
7128 /* VEX_LEN_0FXOP_08_C1 */
7130 { VEX_W_TABLE (VEX_W_0FXOP_08_C1_L_0
) },
7133 /* VEX_LEN_0FXOP_08_C2 */
7135 { VEX_W_TABLE (VEX_W_0FXOP_08_C2_L_0
) },
7138 /* VEX_LEN_0FXOP_08_C3 */
7140 { VEX_W_TABLE (VEX_W_0FXOP_08_C3_L_0
) },
7143 /* VEX_LEN_0FXOP_08_CC */
7145 { VEX_W_TABLE (VEX_W_0FXOP_08_CC_L_0
) },
7148 /* VEX_LEN_0FXOP_08_CD */
7150 { VEX_W_TABLE (VEX_W_0FXOP_08_CD_L_0
) },
7153 /* VEX_LEN_0FXOP_08_CE */
7155 { VEX_W_TABLE (VEX_W_0FXOP_08_CE_L_0
) },
7158 /* VEX_LEN_0FXOP_08_CF */
7160 { VEX_W_TABLE (VEX_W_0FXOP_08_CF_L_0
) },
7163 /* VEX_LEN_0FXOP_08_EC */
7165 { VEX_W_TABLE (VEX_W_0FXOP_08_EC_L_0
) },
7168 /* VEX_LEN_0FXOP_08_ED */
7170 { VEX_W_TABLE (VEX_W_0FXOP_08_ED_L_0
) },
7173 /* VEX_LEN_0FXOP_08_EE */
7175 { VEX_W_TABLE (VEX_W_0FXOP_08_EE_L_0
) },
7178 /* VEX_LEN_0FXOP_08_EF */
7180 { VEX_W_TABLE (VEX_W_0FXOP_08_EF_L_0
) },
7183 /* VEX_LEN_0FXOP_09_01 */
7185 { REG_TABLE (REG_0FXOP_09_01_L_0
) },
7188 /* VEX_LEN_0FXOP_09_02 */
7190 { REG_TABLE (REG_0FXOP_09_02_L_0
) },
7193 /* VEX_LEN_0FXOP_09_12_M_1 */
7195 { REG_TABLE (REG_0FXOP_09_12_M_1_L_0
) },
7198 /* VEX_LEN_0FXOP_09_82_W_0 */
7200 { "vfrczss", { XM
, EXd
}, 0 },
7203 /* VEX_LEN_0FXOP_09_83_W_0 */
7205 { "vfrczsd", { XM
, EXq
}, 0 },
7208 /* VEX_LEN_0FXOP_09_90 */
7210 { "vprotb", { XM
, EXx
, VexW
}, 0 },
7213 /* VEX_LEN_0FXOP_09_91 */
7215 { "vprotw", { XM
, EXx
, VexW
}, 0 },
7218 /* VEX_LEN_0FXOP_09_92 */
7220 { "vprotd", { XM
, EXx
, VexW
}, 0 },
7223 /* VEX_LEN_0FXOP_09_93 */
7225 { "vprotq", { XM
, EXx
, VexW
}, 0 },
7228 /* VEX_LEN_0FXOP_09_94 */
7230 { "vpshlb", { XM
, EXx
, VexW
}, 0 },
7233 /* VEX_LEN_0FXOP_09_95 */
7235 { "vpshlw", { XM
, EXx
, VexW
}, 0 },
7238 /* VEX_LEN_0FXOP_09_96 */
7240 { "vpshld", { XM
, EXx
, VexW
}, 0 },
7243 /* VEX_LEN_0FXOP_09_97 */
7245 { "vpshlq", { XM
, EXx
, VexW
}, 0 },
7248 /* VEX_LEN_0FXOP_09_98 */
7250 { "vpshab", { XM
, EXx
, VexW
}, 0 },
7253 /* VEX_LEN_0FXOP_09_99 */
7255 { "vpshaw", { XM
, EXx
, VexW
}, 0 },
7258 /* VEX_LEN_0FXOP_09_9A */
7260 { "vpshad", { XM
, EXx
, VexW
}, 0 },
7263 /* VEX_LEN_0FXOP_09_9B */
7265 { "vpshaq", { XM
, EXx
, VexW
}, 0 },
7268 /* VEX_LEN_0FXOP_09_C1 */
7270 { VEX_W_TABLE (VEX_W_0FXOP_09_C1_L_0
) },
7273 /* VEX_LEN_0FXOP_09_C2 */
7275 { VEX_W_TABLE (VEX_W_0FXOP_09_C2_L_0
) },
7278 /* VEX_LEN_0FXOP_09_C3 */
7280 { VEX_W_TABLE (VEX_W_0FXOP_09_C3_L_0
) },
7283 /* VEX_LEN_0FXOP_09_C6 */
7285 { VEX_W_TABLE (VEX_W_0FXOP_09_C6_L_0
) },
7288 /* VEX_LEN_0FXOP_09_C7 */
7290 { VEX_W_TABLE (VEX_W_0FXOP_09_C7_L_0
) },
7293 /* VEX_LEN_0FXOP_09_CB */
7295 { VEX_W_TABLE (VEX_W_0FXOP_09_CB_L_0
) },
7298 /* VEX_LEN_0FXOP_09_D1 */
7300 { VEX_W_TABLE (VEX_W_0FXOP_09_D1_L_0
) },
7303 /* VEX_LEN_0FXOP_09_D2 */
7305 { VEX_W_TABLE (VEX_W_0FXOP_09_D2_L_0
) },
7308 /* VEX_LEN_0FXOP_09_D3 */
7310 { VEX_W_TABLE (VEX_W_0FXOP_09_D3_L_0
) },
7313 /* VEX_LEN_0FXOP_09_D6 */
7315 { VEX_W_TABLE (VEX_W_0FXOP_09_D6_L_0
) },
7318 /* VEX_LEN_0FXOP_09_D7 */
7320 { VEX_W_TABLE (VEX_W_0FXOP_09_D7_L_0
) },
7323 /* VEX_LEN_0FXOP_09_DB */
7325 { VEX_W_TABLE (VEX_W_0FXOP_09_DB_L_0
) },
7328 /* VEX_LEN_0FXOP_09_E1 */
7330 { VEX_W_TABLE (VEX_W_0FXOP_09_E1_L_0
) },
7333 /* VEX_LEN_0FXOP_09_E2 */
7335 { VEX_W_TABLE (VEX_W_0FXOP_09_E2_L_0
) },
7338 /* VEX_LEN_0FXOP_09_E3 */
7340 { VEX_W_TABLE (VEX_W_0FXOP_09_E3_L_0
) },
7343 /* VEX_LEN_0FXOP_0A_12 */
7345 { REG_TABLE (REG_0FXOP_0A_12_L_0
) },
7349 #include "i386-dis-evex-len.h"
7351 static const struct dis386 vex_w_table
[][2] = {
7353 /* VEX_W_0F41_P_0_LEN_1 */
7354 { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1
) },
7355 { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1
) },
7358 /* VEX_W_0F41_P_2_LEN_1 */
7359 { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1
) },
7360 { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1
) }
7363 /* VEX_W_0F42_P_0_LEN_1 */
7364 { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1
) },
7365 { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1
) },
7368 /* VEX_W_0F42_P_2_LEN_1 */
7369 { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1
) },
7370 { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1
) },
7373 /* VEX_W_0F44_P_0_LEN_0 */
7374 { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1
) },
7375 { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1
) },
7378 /* VEX_W_0F44_P_2_LEN_0 */
7379 { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1
) },
7380 { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1
) },
7383 /* VEX_W_0F45_P_0_LEN_1 */
7384 { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1
) },
7385 { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1
) },
7388 /* VEX_W_0F45_P_2_LEN_1 */
7389 { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1
) },
7390 { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1
) },
7393 /* VEX_W_0F46_P_0_LEN_1 */
7394 { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1
) },
7395 { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1
) },
7398 /* VEX_W_0F46_P_2_LEN_1 */
7399 { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1
) },
7400 { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1
) },
7403 /* VEX_W_0F47_P_0_LEN_1 */
7404 { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1
) },
7405 { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1
) },
7408 /* VEX_W_0F47_P_2_LEN_1 */
7409 { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1
) },
7410 { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1
) },
7413 /* VEX_W_0F4A_P_0_LEN_1 */
7414 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1
) },
7415 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1
) },
7418 /* VEX_W_0F4A_P_2_LEN_1 */
7419 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1
) },
7420 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1
) },
7423 /* VEX_W_0F4B_P_0_LEN_1 */
7424 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1
) },
7425 { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1
) },
7428 /* VEX_W_0F4B_P_2_LEN_1 */
7429 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1
) },
7432 /* VEX_W_0F90_P_0_LEN_0 */
7433 { "kmovw", { MaskG
, MaskE
}, 0 },
7434 { "kmovq", { MaskG
, MaskE
}, 0 },
7437 /* VEX_W_0F90_P_2_LEN_0 */
7438 { "kmovb", { MaskG
, MaskBDE
}, 0 },
7439 { "kmovd", { MaskG
, MaskBDE
}, 0 },
7442 /* VEX_W_0F91_P_0_LEN_0 */
7443 { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0
) },
7444 { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0
) },
7447 /* VEX_W_0F91_P_2_LEN_0 */
7448 { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0
) },
7449 { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0
) },
7452 /* VEX_W_0F92_P_0_LEN_0 */
7453 { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0
) },
7456 /* VEX_W_0F92_P_2_LEN_0 */
7457 { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0
) },
7460 /* VEX_W_0F93_P_0_LEN_0 */
7461 { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0
) },
7464 /* VEX_W_0F93_P_2_LEN_0 */
7465 { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0
) },
7468 /* VEX_W_0F98_P_0_LEN_0 */
7469 { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0
) },
7470 { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0
) },
7473 /* VEX_W_0F98_P_2_LEN_0 */
7474 { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0
) },
7475 { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0
) },
7478 /* VEX_W_0F99_P_0_LEN_0 */
7479 { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0
) },
7480 { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0
) },
7483 /* VEX_W_0F99_P_2_LEN_0 */
7484 { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0
) },
7485 { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0
) },
7489 { "vpermilps", { XM
, Vex
, EXx
}, PREFIX_DATA
},
7493 { "vpermilpd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
7497 { "vtestps", { XM
, EXx
}, PREFIX_DATA
},
7501 { "vtestpd", { XM
, EXx
}, PREFIX_DATA
},
7505 { "vcvtph2ps", { XM
, EXxmmq
}, PREFIX_DATA
},
7508 /* VEX_W_0F3816_L_1 */
7509 { "vpermps", { XM
, Vex
, EXx
}, PREFIX_DATA
},
7513 { "vbroadcastss", { XM
, EXxmm_md
}, PREFIX_DATA
},
7516 /* VEX_W_0F3819_L_1 */
7517 { "vbroadcastsd", { XM
, EXxmm_mq
}, PREFIX_DATA
},
7520 /* VEX_W_0F381A_M_0_L_1 */
7521 { "vbroadcastf128", { XM
, Mxmm
}, PREFIX_DATA
},
7524 /* VEX_W_0F382C_M_0 */
7525 { "vmaskmovps", { XM
, Vex
, Mx
}, PREFIX_DATA
},
7528 /* VEX_W_0F382D_M_0 */
7529 { "vmaskmovpd", { XM
, Vex
, Mx
}, PREFIX_DATA
},
7532 /* VEX_W_0F382E_M_0 */
7533 { "vmaskmovps", { Mx
, Vex
, XM
}, PREFIX_DATA
},
7536 /* VEX_W_0F382F_M_0 */
7537 { "vmaskmovpd", { Mx
, Vex
, XM
}, PREFIX_DATA
},
7541 { "vpermd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
7545 { "vpsravd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
7548 /* VEX_W_0F3849_X86_64_P_0 */
7549 { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_0_W_0
) },
7552 /* VEX_W_0F3849_X86_64_P_2 */
7553 { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_2_W_0
) },
7556 /* VEX_W_0F3849_X86_64_P_3 */
7557 { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_3_W_0
) },
7560 /* VEX_W_0F384B_X86_64_P_1 */
7561 { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_1_W_0
) },
7564 /* VEX_W_0F384B_X86_64_P_2 */
7565 { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_2_W_0
) },
7568 /* VEX_W_0F384B_X86_64_P_3 */
7569 { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_3_W_0
) },
7573 { "vpbroadcastd", { XM
, EXxmm_md
}, PREFIX_DATA
},
7577 { "vpbroadcastq", { XM
, EXxmm_mq
}, PREFIX_DATA
},
7580 /* VEX_W_0F385A_M_0_L_0 */
7581 { "vbroadcasti128", { XM
, Mxmm
}, PREFIX_DATA
},
7584 /* VEX_W_0F385C_X86_64_P_1 */
7585 { MOD_TABLE (MOD_VEX_0F385C_X86_64_P_1_W_0
) },
7588 /* VEX_W_0F385E_X86_64_P_0 */
7589 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_0_W_0
) },
7592 /* VEX_W_0F385E_X86_64_P_1 */
7593 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_1_W_0
) },
7596 /* VEX_W_0F385E_X86_64_P_2 */
7597 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_2_W_0
) },
7600 /* VEX_W_0F385E_X86_64_P_3 */
7601 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_3_W_0
) },
7605 { "vpbroadcastb", { XM
, EXxmm_mb
}, PREFIX_DATA
},
7609 { "vpbroadcastw", { XM
, EXxmm_mw
}, PREFIX_DATA
},
7613 { "vgf2p8mulb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
7616 /* VEX_W_0F3A00_L_1 */
7618 { "vpermq", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7621 /* VEX_W_0F3A01_L_1 */
7623 { "vpermpd", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7627 { "vpblendd", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
7631 { "vpermilps", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7635 { "vpermilpd", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7638 /* VEX_W_0F3A06_L_1 */
7639 { "vperm2f128", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
7642 /* VEX_W_0F3A18_L_1 */
7643 { "vinsertf128", { XM
, Vex
, EXxmm
, Ib
}, PREFIX_DATA
},
7646 /* VEX_W_0F3A19_L_1 */
7647 { "vextractf128", { EXxmm
, XM
, Ib
}, PREFIX_DATA
},
7651 { "vcvtps2ph", { EXxmmq
, XM
, EXxEVexS
, Ib
}, PREFIX_DATA
},
7654 /* VEX_W_0F3A38_L_1 */
7655 { "vinserti128", { XM
, Vex
, EXxmm
, Ib
}, PREFIX_DATA
},
7658 /* VEX_W_0F3A39_L_1 */
7659 { "vextracti128", { EXxmm
, XM
, Ib
}, PREFIX_DATA
},
7662 /* VEX_W_0F3A46_L_1 */
7663 { "vperm2i128", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
7667 { "vblendvps", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
7671 { "vblendvpd", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
7675 { "vpblendvb", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
7680 { "vgf2p8affineqb", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
7685 { "vgf2p8affineinvqb", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
7687 /* VEX_W_0FXOP_08_85_L_0 */
7689 { "vpmacssww", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7691 /* VEX_W_0FXOP_08_86_L_0 */
7693 { "vpmacsswd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7695 /* VEX_W_0FXOP_08_87_L_0 */
7697 { "vpmacssdql", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7699 /* VEX_W_0FXOP_08_8E_L_0 */
7701 { "vpmacssdd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7703 /* VEX_W_0FXOP_08_8F_L_0 */
7705 { "vpmacssdqh", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7707 /* VEX_W_0FXOP_08_95_L_0 */
7709 { "vpmacsww", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7711 /* VEX_W_0FXOP_08_96_L_0 */
7713 { "vpmacswd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7715 /* VEX_W_0FXOP_08_97_L_0 */
7717 { "vpmacsdql", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7719 /* VEX_W_0FXOP_08_9E_L_0 */
7721 { "vpmacsdd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7723 /* VEX_W_0FXOP_08_9F_L_0 */
7725 { "vpmacsdqh", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7727 /* VEX_W_0FXOP_08_A6_L_0 */
7729 { "vpmadcsswd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7731 /* VEX_W_0FXOP_08_B6_L_0 */
7733 { "vpmadcswd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7735 /* VEX_W_0FXOP_08_C0_L_0 */
7737 { "vprotb", { XM
, EXx
, Ib
}, 0 },
7739 /* VEX_W_0FXOP_08_C1_L_0 */
7741 { "vprotw", { XM
, EXx
, Ib
}, 0 },
7743 /* VEX_W_0FXOP_08_C2_L_0 */
7745 { "vprotd", { XM
, EXx
, Ib
}, 0 },
7747 /* VEX_W_0FXOP_08_C3_L_0 */
7749 { "vprotq", { XM
, EXx
, Ib
}, 0 },
7751 /* VEX_W_0FXOP_08_CC_L_0 */
7753 { "vpcomb", { XM
, Vex
, EXx
, VPCOM
}, 0 },
7755 /* VEX_W_0FXOP_08_CD_L_0 */
7757 { "vpcomw", { XM
, Vex
, EXx
, VPCOM
}, 0 },
7759 /* VEX_W_0FXOP_08_CE_L_0 */
7761 { "vpcomd", { XM
, Vex
, EXx
, VPCOM
}, 0 },
7763 /* VEX_W_0FXOP_08_CF_L_0 */
7765 { "vpcomq", { XM
, Vex
, EXx
, VPCOM
}, 0 },
7767 /* VEX_W_0FXOP_08_EC_L_0 */
7769 { "vpcomub", { XM
, Vex
, EXx
, VPCOM
}, 0 },
7771 /* VEX_W_0FXOP_08_ED_L_0 */
7773 { "vpcomuw", { XM
, Vex
, EXx
, VPCOM
}, 0 },
7775 /* VEX_W_0FXOP_08_EE_L_0 */
7777 { "vpcomud", { XM
, Vex
, EXx
, VPCOM
}, 0 },
7779 /* VEX_W_0FXOP_08_EF_L_0 */
7781 { "vpcomuq", { XM
, Vex
, EXx
, VPCOM
}, 0 },
7783 /* VEX_W_0FXOP_09_80 */
7785 { "vfrczps", { XM
, EXx
}, 0 },
7787 /* VEX_W_0FXOP_09_81 */
7789 { "vfrczpd", { XM
, EXx
}, 0 },
7791 /* VEX_W_0FXOP_09_82 */
7793 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_82_W_0
) },
7795 /* VEX_W_0FXOP_09_83 */
7797 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_83_W_0
) },
7799 /* VEX_W_0FXOP_09_C1_L_0 */
7801 { "vphaddbw", { XM
, EXxmm
}, 0 },
7803 /* VEX_W_0FXOP_09_C2_L_0 */
7805 { "vphaddbd", { XM
, EXxmm
}, 0 },
7807 /* VEX_W_0FXOP_09_C3_L_0 */
7809 { "vphaddbq", { XM
, EXxmm
}, 0 },
7811 /* VEX_W_0FXOP_09_C6_L_0 */
7813 { "vphaddwd", { XM
, EXxmm
}, 0 },
7815 /* VEX_W_0FXOP_09_C7_L_0 */
7817 { "vphaddwq", { XM
, EXxmm
}, 0 },
7819 /* VEX_W_0FXOP_09_CB_L_0 */
7821 { "vphadddq", { XM
, EXxmm
}, 0 },
7823 /* VEX_W_0FXOP_09_D1_L_0 */
7825 { "vphaddubw", { XM
, EXxmm
}, 0 },
7827 /* VEX_W_0FXOP_09_D2_L_0 */
7829 { "vphaddubd", { XM
, EXxmm
}, 0 },
7831 /* VEX_W_0FXOP_09_D3_L_0 */
7833 { "vphaddubq", { XM
, EXxmm
}, 0 },
7835 /* VEX_W_0FXOP_09_D6_L_0 */
7837 { "vphadduwd", { XM
, EXxmm
}, 0 },
7839 /* VEX_W_0FXOP_09_D7_L_0 */
7841 { "vphadduwq", { XM
, EXxmm
}, 0 },
7843 /* VEX_W_0FXOP_09_DB_L_0 */
7845 { "vphaddudq", { XM
, EXxmm
}, 0 },
7847 /* VEX_W_0FXOP_09_E1_L_0 */
7849 { "vphsubbw", { XM
, EXxmm
}, 0 },
7851 /* VEX_W_0FXOP_09_E2_L_0 */
7853 { "vphsubwd", { XM
, EXxmm
}, 0 },
7855 /* VEX_W_0FXOP_09_E3_L_0 */
7857 { "vphsubdq", { XM
, EXxmm
}, 0 },
7860 #include "i386-dis-evex-w.h"
7863 static const struct dis386 mod_table
[][2] = {
7866 { "leaS", { Gv
, M
}, 0 },
7871 { RM_TABLE (RM_C6_REG_7
) },
7876 { RM_TABLE (RM_C7_REG_7
) },
7880 { "{l|}call^", { indirEp
}, 0 },
7884 { "{l|}jmp^", { indirEp
}, 0 },
7887 /* MOD_0F01_REG_0 */
7888 { X86_64_TABLE (X86_64_0F01_REG_0
) },
7889 { RM_TABLE (RM_0F01_REG_0
) },
7892 /* MOD_0F01_REG_1 */
7893 { X86_64_TABLE (X86_64_0F01_REG_1
) },
7894 { RM_TABLE (RM_0F01_REG_1
) },
7897 /* MOD_0F01_REG_2 */
7898 { X86_64_TABLE (X86_64_0F01_REG_2
) },
7899 { RM_TABLE (RM_0F01_REG_2
) },
7902 /* MOD_0F01_REG_3 */
7903 { X86_64_TABLE (X86_64_0F01_REG_3
) },
7904 { RM_TABLE (RM_0F01_REG_3
) },
7907 /* MOD_0F01_REG_5 */
7908 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0
) },
7909 { RM_TABLE (RM_0F01_REG_5_MOD_3
) },
7912 /* MOD_0F01_REG_7 */
7913 { "invlpg", { Mb
}, 0 },
7914 { RM_TABLE (RM_0F01_REG_7_MOD_3
) },
7917 /* MOD_0F12_PREFIX_0 */
7918 { "movlpX", { XM
, EXq
}, 0 },
7919 { "movhlps", { XM
, EXq
}, 0 },
7922 /* MOD_0F12_PREFIX_2 */
7923 { "movlpX", { XM
, EXq
}, 0 },
7927 { "movlpX", { EXq
, XM
}, PREFIX_OPCODE
},
7930 /* MOD_0F16_PREFIX_0 */
7931 { "movhpX", { XM
, EXq
}, 0 },
7932 { "movlhps", { XM
, EXq
}, 0 },
7935 /* MOD_0F16_PREFIX_2 */
7936 { "movhpX", { XM
, EXq
}, 0 },
7940 { "movhpX", { EXq
, XM
}, PREFIX_OPCODE
},
7943 /* MOD_0F18_REG_0 */
7944 { "prefetchnta", { Mb
}, 0 },
7947 /* MOD_0F18_REG_1 */
7948 { "prefetcht0", { Mb
}, 0 },
7951 /* MOD_0F18_REG_2 */
7952 { "prefetcht1", { Mb
}, 0 },
7955 /* MOD_0F18_REG_3 */
7956 { "prefetcht2", { Mb
}, 0 },
7959 /* MOD_0F18_REG_4 */
7960 { "nop/reserved", { Mb
}, 0 },
7963 /* MOD_0F18_REG_5 */
7964 { "nop/reserved", { Mb
}, 0 },
7967 /* MOD_0F18_REG_6 */
7968 { "nop/reserved", { Mb
}, 0 },
7971 /* MOD_0F18_REG_7 */
7972 { "nop/reserved", { Mb
}, 0 },
7975 /* MOD_0F1A_PREFIX_0 */
7976 { "bndldx", { Gbnd
, Mv_bnd
}, 0 },
7977 { "nopQ", { Ev
}, 0 },
7980 /* MOD_0F1B_PREFIX_0 */
7981 { "bndstx", { Mv_bnd
, Gbnd
}, 0 },
7982 { "nopQ", { Ev
}, 0 },
7985 /* MOD_0F1B_PREFIX_1 */
7986 { "bndmk", { Gbnd
, Mv_bnd
}, 0 },
7987 { "nopQ", { Ev
}, 0 },
7990 /* MOD_0F1C_PREFIX_0 */
7991 { REG_TABLE (REG_0F1C_P_0_MOD_0
) },
7992 { "nopQ", { Ev
}, 0 },
7995 /* MOD_0F1E_PREFIX_1 */
7996 { "nopQ", { Ev
}, 0 },
7997 { REG_TABLE (REG_0F1E_P_1_MOD_3
) },
8000 /* MOD_0F2B_PREFIX_0 */
8001 {"movntps", { Mx
, XM
}, PREFIX_OPCODE
},
8004 /* MOD_0F2B_PREFIX_1 */
8005 {"movntss", { Md
, XM
}, PREFIX_OPCODE
},
8008 /* MOD_0F2B_PREFIX_2 */
8009 {"movntpd", { Mx
, XM
}, PREFIX_OPCODE
},
8012 /* MOD_0F2B_PREFIX_3 */
8013 {"movntsd", { Mq
, XM
}, PREFIX_OPCODE
},
8018 { "movmskpX", { Gdq
, XS
}, PREFIX_OPCODE
},
8021 /* MOD_0F71_REG_2 */
8023 { "psrlw", { MS
, Ib
}, PREFIX_OPCODE
},
8026 /* MOD_0F71_REG_4 */
8028 { "psraw", { MS
, Ib
}, PREFIX_OPCODE
},
8031 /* MOD_0F71_REG_6 */
8033 { "psllw", { MS
, Ib
}, PREFIX_OPCODE
},
8036 /* MOD_0F72_REG_2 */
8038 { "psrld", { MS
, Ib
}, PREFIX_OPCODE
},
8041 /* MOD_0F72_REG_4 */
8043 { "psrad", { MS
, Ib
}, PREFIX_OPCODE
},
8046 /* MOD_0F72_REG_6 */
8048 { "pslld", { MS
, Ib
}, PREFIX_OPCODE
},
8051 /* MOD_0F73_REG_2 */
8053 { "psrlq", { MS
, Ib
}, PREFIX_OPCODE
},
8056 /* MOD_0F73_REG_3 */
8058 { "psrldq", { XS
, Ib
}, PREFIX_DATA
},
8061 /* MOD_0F73_REG_6 */
8063 { "psllq", { MS
, Ib
}, PREFIX_OPCODE
},
8066 /* MOD_0F73_REG_7 */
8068 { "pslldq", { XS
, Ib
}, PREFIX_DATA
},
8071 /* MOD_0FAE_REG_0 */
8072 { "fxsave", { FXSAVE
}, 0 },
8073 { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3
) },
8076 /* MOD_0FAE_REG_1 */
8077 { "fxrstor", { FXSAVE
}, 0 },
8078 { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3
) },
8081 /* MOD_0FAE_REG_2 */
8082 { "ldmxcsr", { Md
}, 0 },
8083 { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3
) },
8086 /* MOD_0FAE_REG_3 */
8087 { "stmxcsr", { Md
}, 0 },
8088 { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3
) },
8091 /* MOD_0FAE_REG_4 */
8092 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0
) },
8093 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3
) },
8096 /* MOD_0FAE_REG_5 */
8097 { "xrstor", { FXSAVE
}, PREFIX_OPCODE
},
8098 { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3
) },
8101 /* MOD_0FAE_REG_6 */
8102 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0
) },
8103 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3
) },
8106 /* MOD_0FAE_REG_7 */
8107 { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0
) },
8108 { RM_TABLE (RM_0FAE_REG_7_MOD_3
) },
8112 { "lssS", { Gv
, Mp
}, 0 },
8116 { "lfsS", { Gv
, Mp
}, 0 },
8120 { "lgsS", { Gv
, Mp
}, 0 },
8124 { "movntiS", { Edq
, Gdq
}, PREFIX_OPCODE
},
8127 /* MOD_0FC7_REG_3 */
8128 { "xrstors", { FXSAVE
}, 0 },
8131 /* MOD_0FC7_REG_4 */
8132 { "xsavec", { FXSAVE
}, 0 },
8135 /* MOD_0FC7_REG_5 */
8136 { "xsaves", { FXSAVE
}, 0 },
8139 /* MOD_0FC7_REG_6 */
8140 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0
) },
8141 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3
) }
8144 /* MOD_0FC7_REG_7 */
8145 { "vmptrst", { Mq
}, 0 },
8146 { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3
) }
8151 { "pmovmskb", { Gdq
, MS
}, 0 },
8154 /* MOD_0FE7_PREFIX_2 */
8155 { "movntdq", { Mx
, XM
}, 0 },
8158 /* MOD_0FF0_PREFIX_3 */
8159 { "lddqu", { XM
, M
}, 0 },
8163 { "movntdqa", { XM
, Mx
}, PREFIX_DATA
},
8166 /* MOD_VEX_0F3849_X86_64_P_0_W_0 */
8167 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0
) },
8168 { REG_TABLE (REG_VEX_0F3849_X86_64_P_0_W_0_M_1
) },
8171 /* MOD_VEX_0F3849_X86_64_P_2_W_0 */
8172 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0
) },
8175 /* MOD_VEX_0F3849_X86_64_P_3_W_0 */
8177 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0
) },
8180 /* MOD_VEX_0F384B_X86_64_P_1_W_0 */
8181 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0
) },
8184 /* MOD_VEX_0F384B_X86_64_P_2_W_0 */
8185 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0
) },
8188 /* MOD_VEX_0F384B_X86_64_P_3_W_0 */
8189 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0
) },
8192 /* MOD_VEX_0F385C_X86_64_P_1_W_0 */
8194 { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0
) },
8197 /* MOD_VEX_0F385E_X86_64_P_0_W_0 */
8199 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0
) },
8202 /* MOD_VEX_0F385E_X86_64_P_1_W_0 */
8204 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0
) },
8207 /* MOD_VEX_0F385E_X86_64_P_2_W_0 */
8209 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0
) },
8212 /* MOD_VEX_0F385E_X86_64_P_3_W_0 */
8214 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0
) },
8218 { "wrussK", { M
, Gdq
}, PREFIX_DATA
},
8221 /* MOD_0F38F6_PREFIX_0 */
8222 { "wrssK", { M
, Gdq
}, PREFIX_OPCODE
},
8225 /* MOD_0F38F8_PREFIX_1 */
8226 { "enqcmds", { Gva
, M
}, PREFIX_OPCODE
},
8229 /* MOD_0F38F8_PREFIX_2 */
8230 { "movdir64b", { Gva
, M
}, PREFIX_OPCODE
},
8233 /* MOD_0F38F8_PREFIX_3 */
8234 { "enqcmd", { Gva
, M
}, PREFIX_OPCODE
},
8238 { "movdiri", { Edq
, Gdq
}, PREFIX_OPCODE
},
8242 { "bound{S|}", { Gv
, Ma
}, 0 },
8243 { EVEX_TABLE (EVEX_0F
) },
8247 { "lesS", { Gv
, Mp
}, 0 },
8248 { VEX_C4_TABLE (VEX_0F
) },
8252 { "ldsS", { Gv
, Mp
}, 0 },
8253 { VEX_C5_TABLE (VEX_0F
) },
8256 /* MOD_VEX_0F12_PREFIX_0 */
8257 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0
) },
8258 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1
) },
8261 /* MOD_VEX_0F12_PREFIX_2 */
8262 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0
) },
8266 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0
) },
8269 /* MOD_VEX_0F16_PREFIX_0 */
8270 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0
) },
8271 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1
) },
8274 /* MOD_VEX_0F16_PREFIX_2 */
8275 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0
) },
8279 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0
) },
8283 { "vmovntpX", { Mx
, XM
}, PREFIX_OPCODE
},
8286 /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
8288 { "kandw", { MaskG
, MaskVex
, MaskE
}, 0 },
8291 /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
8293 { "kandq", { MaskG
, MaskVex
, MaskE
}, 0 },
8296 /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
8298 { "kandb", { MaskG
, MaskVex
, MaskE
}, 0 },
8301 /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
8303 { "kandd", { MaskG
, MaskVex
, MaskE
}, 0 },
8306 /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
8308 { "kandnw", { MaskG
, MaskVex
, MaskE
}, 0 },
8311 /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
8313 { "kandnq", { MaskG
, MaskVex
, MaskE
}, 0 },
8316 /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
8318 { "kandnb", { MaskG
, MaskVex
, MaskE
}, 0 },
8321 /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
8323 { "kandnd", { MaskG
, MaskVex
, MaskE
}, 0 },
8326 /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
8328 { "knotw", { MaskG
, MaskE
}, 0 },
8331 /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
8333 { "knotq", { MaskG
, MaskE
}, 0 },
8336 /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
8338 { "knotb", { MaskG
, MaskE
}, 0 },
8341 /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
8343 { "knotd", { MaskG
, MaskE
}, 0 },
8346 /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
8348 { "korw", { MaskG
, MaskVex
, MaskE
}, 0 },
8351 /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
8353 { "korq", { MaskG
, MaskVex
, MaskE
}, 0 },
8356 /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
8358 { "korb", { MaskG
, MaskVex
, MaskE
}, 0 },
8361 /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
8363 { "kord", { MaskG
, MaskVex
, MaskE
}, 0 },
8366 /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
8368 { "kxnorw", { MaskG
, MaskVex
, MaskE
}, 0 },
8371 /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
8373 { "kxnorq", { MaskG
, MaskVex
, MaskE
}, 0 },
8376 /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
8378 { "kxnorb", { MaskG
, MaskVex
, MaskE
}, 0 },
8381 /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
8383 { "kxnord", { MaskG
, MaskVex
, MaskE
}, 0 },
8386 /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
8388 { "kxorw", { MaskG
, MaskVex
, MaskE
}, 0 },
8391 /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
8393 { "kxorq", { MaskG
, MaskVex
, MaskE
}, 0 },
8396 /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
8398 { "kxorb", { MaskG
, MaskVex
, MaskE
}, 0 },
8401 /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
8403 { "kxord", { MaskG
, MaskVex
, MaskE
}, 0 },
8406 /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
8408 { "kaddw", { MaskG
, MaskVex
, MaskE
}, 0 },
8411 /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
8413 { "kaddq", { MaskG
, MaskVex
, MaskE
}, 0 },
8416 /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
8418 { "kaddb", { MaskG
, MaskVex
, MaskE
}, 0 },
8421 /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
8423 { "kaddd", { MaskG
, MaskVex
, MaskE
}, 0 },
8426 /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
8428 { "kunpckwd", { MaskG
, MaskVex
, MaskE
}, 0 },
8431 /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
8433 { "kunpckdq", { MaskG
, MaskVex
, MaskE
}, 0 },
8436 /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
8438 { "kunpckbw", { MaskG
, MaskVex
, MaskE
}, 0 },
8443 { "vmovmskpX", { Gdq
, XS
}, PREFIX_OPCODE
},
8446 /* MOD_VEX_0F71_REG_2 */
8448 { "vpsrlw", { Vex
, XS
, Ib
}, PREFIX_DATA
},
8451 /* MOD_VEX_0F71_REG_4 */
8453 { "vpsraw", { Vex
, XS
, Ib
}, PREFIX_DATA
},
8456 /* MOD_VEX_0F71_REG_6 */
8458 { "vpsllw", { Vex
, XS
, Ib
}, PREFIX_DATA
},
8461 /* MOD_VEX_0F72_REG_2 */
8463 { "vpsrld", { Vex
, XS
, Ib
}, PREFIX_DATA
},
8466 /* MOD_VEX_0F72_REG_4 */
8468 { "vpsrad", { Vex
, XS
, Ib
}, PREFIX_DATA
},
8471 /* MOD_VEX_0F72_REG_6 */
8473 { "vpslld", { Vex
, XS
, Ib
}, PREFIX_DATA
},
8476 /* MOD_VEX_0F73_REG_2 */
8478 { "vpsrlq", { Vex
, XS
, Ib
}, PREFIX_DATA
},
8481 /* MOD_VEX_0F73_REG_3 */
8483 { "vpsrldq", { Vex
, XS
, Ib
}, PREFIX_DATA
},
8486 /* MOD_VEX_0F73_REG_6 */
8488 { "vpsllq", { Vex
, XS
, Ib
}, PREFIX_DATA
},
8491 /* MOD_VEX_0F73_REG_7 */
8493 { "vpslldq", { Vex
, XS
, Ib
}, PREFIX_DATA
},
8496 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
8497 { "kmovw", { Ew
, MaskG
}, 0 },
8501 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
8502 { "kmovq", { Eq
, MaskG
}, 0 },
8506 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
8507 { "kmovb", { Eb
, MaskG
}, 0 },
8511 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
8512 { "kmovd", { Ed
, MaskG
}, 0 },
8516 /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
8518 { "kmovw", { MaskG
, Edq
}, 0 },
8521 /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
8523 { "kmovb", { MaskG
, Edq
}, 0 },
8526 /* MOD_VEX_0F92_P_3_LEN_0 */
8528 { "kmovK", { MaskG
, Edq
}, 0 },
8531 /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
8533 { "kmovw", { Gdq
, MaskE
}, 0 },
8536 /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
8538 { "kmovb", { Gdq
, MaskE
}, 0 },
8541 /* MOD_VEX_0F93_P_3_LEN_0 */
8543 { "kmovK", { Gdq
, MaskE
}, 0 },
8546 /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
8548 { "kortestw", { MaskG
, MaskE
}, 0 },
8551 /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
8553 { "kortestq", { MaskG
, MaskE
}, 0 },
8556 /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
8558 { "kortestb", { MaskG
, MaskE
}, 0 },
8561 /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
8563 { "kortestd", { MaskG
, MaskE
}, 0 },
8566 /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
8568 { "ktestw", { MaskG
, MaskE
}, 0 },
8571 /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
8573 { "ktestq", { MaskG
, MaskE
}, 0 },
8576 /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
8578 { "ktestb", { MaskG
, MaskE
}, 0 },
8581 /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
8583 { "ktestd", { MaskG
, MaskE
}, 0 },
8586 /* MOD_VEX_0FAE_REG_2 */
8587 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0
) },
8590 /* MOD_VEX_0FAE_REG_3 */
8591 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0
) },
8596 { "vpmovmskb", { Gdq
, XS
}, PREFIX_DATA
},
8600 { "vmovntdq", { Mx
, XM
}, PREFIX_DATA
},
8603 /* MOD_VEX_0FF0_PREFIX_3 */
8604 { "vlddqu", { XM
, M
}, 0 },
8607 /* MOD_VEX_0F381A */
8608 { VEX_LEN_TABLE (VEX_LEN_0F381A_M_0
) },
8611 /* MOD_VEX_0F382A */
8612 { "vmovntdqa", { XM
, Mx
}, PREFIX_DATA
},
8615 /* MOD_VEX_0F382C */
8616 { VEX_W_TABLE (VEX_W_0F382C_M_0
) },
8619 /* MOD_VEX_0F382D */
8620 { VEX_W_TABLE (VEX_W_0F382D_M_0
) },
8623 /* MOD_VEX_0F382E */
8624 { VEX_W_TABLE (VEX_W_0F382E_M_0
) },
8627 /* MOD_VEX_0F382F */
8628 { VEX_W_TABLE (VEX_W_0F382F_M_0
) },
8631 /* MOD_VEX_0F385A */
8632 { VEX_LEN_TABLE (VEX_LEN_0F385A_M_0
) },
8635 /* MOD_VEX_0F388C */
8636 { "vpmaskmov%DQ", { XM
, Vex
, Mx
}, PREFIX_DATA
},
8639 /* MOD_VEX_0F388E */
8640 { "vpmaskmov%DQ", { Mx
, Vex
, XM
}, PREFIX_DATA
},
8643 /* MOD_VEX_0F3A30_L_0 */
8645 { "kshiftr%BW", { MaskG
, MaskE
, Ib
}, PREFIX_DATA
},
8648 /* MOD_VEX_0F3A31_L_0 */
8650 { "kshiftr%DQ", { MaskG
, MaskE
, Ib
}, PREFIX_DATA
},
8653 /* MOD_VEX_0F3A32_L_0 */
8655 { "kshiftl%BW", { MaskG
, MaskE
, Ib
}, PREFIX_DATA
},
8658 /* MOD_VEX_0F3A33_L_0 */
8660 { "kshiftl%DQ", { MaskG
, MaskE
, Ib
}, PREFIX_DATA
},
8663 /* MOD_VEX_0FXOP_09_12 */
8665 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_12_M_1
) },
8668 #include "i386-dis-evex-mod.h"
8671 static const struct dis386 rm_table
[][8] = {
8674 { "xabort", { Skip_MODRM
, Ib
}, 0 },
8678 { "xbeginT", { Skip_MODRM
, Jdqw
}, 0 },
8682 { "enclv", { Skip_MODRM
}, 0 },
8683 { "vmcall", { Skip_MODRM
}, 0 },
8684 { "vmlaunch", { Skip_MODRM
}, 0 },
8685 { "vmresume", { Skip_MODRM
}, 0 },
8686 { "vmxoff", { Skip_MODRM
}, 0 },
8687 { "pconfig", { Skip_MODRM
}, 0 },
8691 { "monitor", { { OP_Monitor
, 0 } }, 0 },
8692 { "mwait", { { OP_Mwait
, 0 } }, 0 },
8693 { "clac", { Skip_MODRM
}, 0 },
8694 { "stac", { Skip_MODRM
}, 0 },
8698 { "encls", { Skip_MODRM
}, 0 },
8702 { "xgetbv", { Skip_MODRM
}, 0 },
8703 { "xsetbv", { Skip_MODRM
}, 0 },
8706 { "vmfunc", { Skip_MODRM
}, 0 },
8707 { "xend", { Skip_MODRM
}, 0 },
8708 { "xtest", { Skip_MODRM
}, 0 },
8709 { "enclu", { Skip_MODRM
}, 0 },
8713 { "vmrun", { Skip_MODRM
}, 0 },
8714 { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1
) },
8715 { "vmload", { Skip_MODRM
}, 0 },
8716 { "vmsave", { Skip_MODRM
}, 0 },
8717 { "stgi", { Skip_MODRM
}, 0 },
8718 { "clgi", { Skip_MODRM
}, 0 },
8719 { "skinit", { Skip_MODRM
}, 0 },
8720 { "invlpga", { Skip_MODRM
}, 0 },
8723 /* RM_0F01_REG_5_MOD_3 */
8724 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0
) },
8725 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1
) },
8726 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2
) },
8730 { "rdpkru", { Skip_MODRM
}, 0 },
8731 { "wrpkru", { Skip_MODRM
}, 0 },
8734 /* RM_0F01_REG_7_MOD_3 */
8735 { "swapgs", { Skip_MODRM
}, 0 },
8736 { "rdtscp", { Skip_MODRM
}, 0 },
8737 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2
) },
8738 { "mwaitx", { { OP_Mwait
, eBX_reg
} }, PREFIX_OPCODE
},
8739 { "clzero", { Skip_MODRM
}, 0 },
8740 { "rdpru", { Skip_MODRM
}, 0 },
8743 /* RM_0F1E_P_1_MOD_3_REG_7 */
8744 { "nopQ", { Ev
}, 0 },
8745 { "nopQ", { Ev
}, 0 },
8746 { "endbr64", { Skip_MODRM
}, PREFIX_OPCODE
},
8747 { "endbr32", { Skip_MODRM
}, PREFIX_OPCODE
},
8748 { "nopQ", { Ev
}, 0 },
8749 { "nopQ", { Ev
}, 0 },
8750 { "nopQ", { Ev
}, 0 },
8751 { "nopQ", { Ev
}, 0 },
8754 /* RM_0FAE_REG_6_MOD_3 */
8755 { "mfence", { Skip_MODRM
}, 0 },
8758 /* RM_0FAE_REG_7_MOD_3 */
8759 { "sfence", { Skip_MODRM
}, 0 },
8763 /* RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0 */
8764 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0
) },
8768 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
8770 /* We use the high bit to indicate different name for the same
8772 #define REP_PREFIX (0xf3 | 0x100)
8773 #define XACQUIRE_PREFIX (0xf2 | 0x200)
8774 #define XRELEASE_PREFIX (0xf3 | 0x400)
8775 #define BND_PREFIX (0xf2 | 0x400)
8776 #define NOTRACK_PREFIX (0x3e | 0x100)
8778 /* Remember if the current op is a jump instruction. */
8779 static bfd_boolean op_is_jump
= FALSE
;
8784 int newrex
, i
, length
;
8789 last_lock_prefix
= -1;
8790 last_repz_prefix
= -1;
8791 last_repnz_prefix
= -1;
8792 last_data_prefix
= -1;
8793 last_addr_prefix
= -1;
8794 last_rex_prefix
= -1;
8795 last_seg_prefix
= -1;
8797 active_seg_prefix
= 0;
8798 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
8799 all_prefixes
[i
] = 0;
8802 /* The maximum instruction length is 15bytes. */
8803 while (length
< MAX_CODE_LENGTH
- 1)
8805 FETCH_DATA (the_info
, codep
+ 1);
8809 /* REX prefixes family. */
8826 if (address_mode
== mode_64bit
)
8830 last_rex_prefix
= i
;
8833 prefixes
|= PREFIX_REPZ
;
8834 last_repz_prefix
= i
;
8837 prefixes
|= PREFIX_REPNZ
;
8838 last_repnz_prefix
= i
;
8841 prefixes
|= PREFIX_LOCK
;
8842 last_lock_prefix
= i
;
8845 prefixes
|= PREFIX_CS
;
8846 last_seg_prefix
= i
;
8847 active_seg_prefix
= PREFIX_CS
;
8850 prefixes
|= PREFIX_SS
;
8851 last_seg_prefix
= i
;
8852 active_seg_prefix
= PREFIX_SS
;
8855 prefixes
|= PREFIX_DS
;
8856 last_seg_prefix
= i
;
8857 active_seg_prefix
= PREFIX_DS
;
8860 prefixes
|= PREFIX_ES
;
8861 last_seg_prefix
= i
;
8862 active_seg_prefix
= PREFIX_ES
;
8865 prefixes
|= PREFIX_FS
;
8866 last_seg_prefix
= i
;
8867 active_seg_prefix
= PREFIX_FS
;
8870 prefixes
|= PREFIX_GS
;
8871 last_seg_prefix
= i
;
8872 active_seg_prefix
= PREFIX_GS
;
8875 prefixes
|= PREFIX_DATA
;
8876 last_data_prefix
= i
;
8879 prefixes
|= PREFIX_ADDR
;
8880 last_addr_prefix
= i
;
8883 /* fwait is really an instruction. If there are prefixes
8884 before the fwait, they belong to the fwait, *not* to the
8885 following instruction. */
8887 if (prefixes
|| rex
)
8889 prefixes
|= PREFIX_FWAIT
;
8891 /* This ensures that the previous REX prefixes are noticed
8892 as unused prefixes, as in the return case below. */
8896 prefixes
= PREFIX_FWAIT
;
8901 /* Rex is ignored when followed by another prefix. */
8907 if (*codep
!= FWAIT_OPCODE
)
8908 all_prefixes
[i
++] = *codep
;
8916 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
8920 prefix_name (int pref
, int sizeflag
)
8922 static const char *rexes
[16] =
8927 "rex.XB", /* 0x43 */
8929 "rex.RB", /* 0x45 */
8930 "rex.RX", /* 0x46 */
8931 "rex.RXB", /* 0x47 */
8933 "rex.WB", /* 0x49 */
8934 "rex.WX", /* 0x4a */
8935 "rex.WXB", /* 0x4b */
8936 "rex.WR", /* 0x4c */
8937 "rex.WRB", /* 0x4d */
8938 "rex.WRX", /* 0x4e */
8939 "rex.WRXB", /* 0x4f */
8944 /* REX prefixes family. */
8961 return rexes
[pref
- 0x40];
8981 return (sizeflag
& DFLAG
) ? "data16" : "data32";
8983 if (address_mode
== mode_64bit
)
8984 return (sizeflag
& AFLAG
) ? "addr32" : "addr64";
8986 return (sizeflag
& AFLAG
) ? "addr16" : "addr32";
8991 case XACQUIRE_PREFIX
:
8993 case XRELEASE_PREFIX
:
8997 case NOTRACK_PREFIX
:
9004 static char op_out
[MAX_OPERANDS
][100];
9005 static int op_ad
, op_index
[MAX_OPERANDS
];
9006 static int two_source_ops
;
9007 static bfd_vma op_address
[MAX_OPERANDS
];
9008 static bfd_vma op_riprel
[MAX_OPERANDS
];
9009 static bfd_vma start_pc
;
9012 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
9013 * (see topic "Redundant prefixes" in the "Differences from 8086"
9014 * section of the "Virtual 8086 Mode" chapter.)
9015 * 'pc' should be the address of this instruction, it will
9016 * be used to print the target address if this is a relative jump or call
9017 * The function returns the length of this instruction in bytes.
9020 static char intel_syntax
;
9021 static char intel_mnemonic
= !SYSV386_COMPAT
;
9022 static char open_char
;
9023 static char close_char
;
9024 static char separator_char
;
9025 static char scale_char
;
9033 static enum x86_64_isa isa64
;
9035 /* Here for backwards compatibility. When gdb stops using
9036 print_insn_i386_att and print_insn_i386_intel these functions can
9037 disappear, and print_insn_i386 be merged into print_insn. */
9039 print_insn_i386_att (bfd_vma pc
, disassemble_info
*info
)
9043 return print_insn (pc
, info
);
9047 print_insn_i386_intel (bfd_vma pc
, disassemble_info
*info
)
9051 return print_insn (pc
, info
);
9055 print_insn_i386 (bfd_vma pc
, disassemble_info
*info
)
9059 return print_insn (pc
, info
);
9063 print_i386_disassembler_options (FILE *stream
)
9065 fprintf (stream
, _("\n\
9066 The following i386/x86-64 specific disassembler options are supported for use\n\
9067 with the -M switch (multiple options should be separated by commas):\n"));
9069 fprintf (stream
, _(" x86-64 Disassemble in 64bit mode\n"));
9070 fprintf (stream
, _(" i386 Disassemble in 32bit mode\n"));
9071 fprintf (stream
, _(" i8086 Disassemble in 16bit mode\n"));
9072 fprintf (stream
, _(" att Display instruction in AT&T syntax\n"));
9073 fprintf (stream
, _(" intel Display instruction in Intel syntax\n"));
9074 fprintf (stream
, _(" att-mnemonic\n"
9075 " Display instruction in AT&T mnemonic\n"));
9076 fprintf (stream
, _(" intel-mnemonic\n"
9077 " Display instruction in Intel mnemonic\n"));
9078 fprintf (stream
, _(" addr64 Assume 64bit address size\n"));
9079 fprintf (stream
, _(" addr32 Assume 32bit address size\n"));
9080 fprintf (stream
, _(" addr16 Assume 16bit address size\n"));
9081 fprintf (stream
, _(" data32 Assume 32bit data size\n"));
9082 fprintf (stream
, _(" data16 Assume 16bit data size\n"));
9083 fprintf (stream
, _(" suffix Always display instruction suffix in AT&T syntax\n"));
9084 fprintf (stream
, _(" amd64 Display instruction in AMD64 ISA\n"));
9085 fprintf (stream
, _(" intel64 Display instruction in Intel64 ISA\n"));
9089 static const struct dis386 bad_opcode
= { "(bad)", { XX
}, 0 };
9091 /* Get a pointer to struct dis386 with a valid name. */
9093 static const struct dis386
*
9094 get_valid_dis386 (const struct dis386
*dp
, disassemble_info
*info
)
9096 int vindex
, vex_table_index
;
9098 if (dp
->name
!= NULL
)
9101 switch (dp
->op
[0].bytemode
)
9104 dp
= ®_table
[dp
->op
[1].bytemode
][modrm
.reg
];
9108 vindex
= modrm
.mod
== 0x3 ? 1 : 0;
9109 dp
= &mod_table
[dp
->op
[1].bytemode
][vindex
];
9113 dp
= &rm_table
[dp
->op
[1].bytemode
][modrm
.rm
];
9116 case USE_PREFIX_TABLE
:
9119 /* The prefix in VEX is implicit. */
9125 case REPE_PREFIX_OPCODE
:
9128 case DATA_PREFIX_OPCODE
:
9131 case REPNE_PREFIX_OPCODE
:
9141 int last_prefix
= -1;
9144 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
9145 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
9147 if ((prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0)
9149 if (last_repz_prefix
> last_repnz_prefix
)
9152 prefix
= PREFIX_REPZ
;
9153 last_prefix
= last_repz_prefix
;
9158 prefix
= PREFIX_REPNZ
;
9159 last_prefix
= last_repnz_prefix
;
9162 /* Check if prefix should be ignored. */
9163 if ((((prefix_table
[dp
->op
[1].bytemode
][vindex
].prefix_requirement
9164 & PREFIX_IGNORED
) >> PREFIX_IGNORED_SHIFT
)
9169 if (vindex
== 0 && (prefixes
& PREFIX_DATA
) != 0)
9172 prefix
= PREFIX_DATA
;
9173 last_prefix
= last_data_prefix
;
9178 used_prefixes
|= prefix
;
9179 all_prefixes
[last_prefix
] = 0;
9182 dp
= &prefix_table
[dp
->op
[1].bytemode
][vindex
];
9185 case USE_X86_64_TABLE
:
9186 vindex
= address_mode
== mode_64bit
? 1 : 0;
9187 dp
= &x86_64_table
[dp
->op
[1].bytemode
][vindex
];
9190 case USE_3BYTE_TABLE
:
9191 FETCH_DATA (info
, codep
+ 2);
9193 dp
= &three_byte_table
[dp
->op
[1].bytemode
][vindex
];
9195 modrm
.mod
= (*codep
>> 6) & 3;
9196 modrm
.reg
= (*codep
>> 3) & 7;
9197 modrm
.rm
= *codep
& 7;
9200 case USE_VEX_LEN_TABLE
:
9217 dp
= &vex_len_table
[dp
->op
[1].bytemode
][vindex
];
9220 case USE_EVEX_LEN_TABLE
:
9240 dp
= &evex_len_table
[dp
->op
[1].bytemode
][vindex
];
9243 case USE_XOP_8F_TABLE
:
9244 FETCH_DATA (info
, codep
+ 3);
9245 rex
= ~(*codep
>> 5) & 0x7;
9247 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
9248 switch ((*codep
& 0x1f))
9254 vex_table_index
= XOP_08
;
9257 vex_table_index
= XOP_09
;
9260 vex_table_index
= XOP_0A
;
9264 vex
.w
= *codep
& 0x80;
9265 if (vex
.w
&& address_mode
== mode_64bit
)
9268 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
9269 if (address_mode
!= mode_64bit
)
9271 /* In 16/32-bit mode REX_B is silently ignored. */
9275 vex
.length
= (*codep
& 0x4) ? 256 : 128;
9276 switch ((*codep
& 0x3))
9281 vex
.prefix
= DATA_PREFIX_OPCODE
;
9284 vex
.prefix
= REPE_PREFIX_OPCODE
;
9287 vex
.prefix
= REPNE_PREFIX_OPCODE
;
9293 dp
= &xop_table
[vex_table_index
][vindex
];
9296 FETCH_DATA (info
, codep
+ 1);
9297 modrm
.mod
= (*codep
>> 6) & 3;
9298 modrm
.reg
= (*codep
>> 3) & 7;
9299 modrm
.rm
= *codep
& 7;
9301 /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid
9302 having to decode the bits for every otherwise valid encoding. */
9307 case USE_VEX_C4_TABLE
:
9309 FETCH_DATA (info
, codep
+ 3);
9310 rex
= ~(*codep
>> 5) & 0x7;
9311 switch ((*codep
& 0x1f))
9317 vex_table_index
= VEX_0F
;
9320 vex_table_index
= VEX_0F38
;
9323 vex_table_index
= VEX_0F3A
;
9327 vex
.w
= *codep
& 0x80;
9328 if (address_mode
== mode_64bit
)
9335 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
9336 is ignored, other REX bits are 0 and the highest bit in
9337 VEX.vvvv is also ignored (but we mustn't clear it here). */
9340 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
9341 vex
.length
= (*codep
& 0x4) ? 256 : 128;
9342 switch ((*codep
& 0x3))
9347 vex
.prefix
= DATA_PREFIX_OPCODE
;
9350 vex
.prefix
= REPE_PREFIX_OPCODE
;
9353 vex
.prefix
= REPNE_PREFIX_OPCODE
;
9359 dp
= &vex_table
[vex_table_index
][vindex
];
9361 /* There is no MODRM byte for VEX0F 77. */
9362 if (vex_table_index
!= VEX_0F
|| vindex
!= 0x77)
9364 FETCH_DATA (info
, codep
+ 1);
9365 modrm
.mod
= (*codep
>> 6) & 3;
9366 modrm
.reg
= (*codep
>> 3) & 7;
9367 modrm
.rm
= *codep
& 7;
9371 case USE_VEX_C5_TABLE
:
9373 FETCH_DATA (info
, codep
+ 2);
9374 rex
= (*codep
& 0x80) ? 0 : REX_R
;
9376 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
9378 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
9379 vex
.length
= (*codep
& 0x4) ? 256 : 128;
9380 switch ((*codep
& 0x3))
9385 vex
.prefix
= DATA_PREFIX_OPCODE
;
9388 vex
.prefix
= REPE_PREFIX_OPCODE
;
9391 vex
.prefix
= REPNE_PREFIX_OPCODE
;
9397 dp
= &vex_table
[dp
->op
[1].bytemode
][vindex
];
9399 /* There is no MODRM byte for VEX 77. */
9402 FETCH_DATA (info
, codep
+ 1);
9403 modrm
.mod
= (*codep
>> 6) & 3;
9404 modrm
.reg
= (*codep
>> 3) & 7;
9405 modrm
.rm
= *codep
& 7;
9409 case USE_VEX_W_TABLE
:
9413 dp
= &vex_w_table
[dp
->op
[1].bytemode
][vex
.w
? 1 : 0];
9416 case USE_EVEX_TABLE
:
9420 FETCH_DATA (info
, codep
+ 4);
9421 /* The first byte after 0x62. */
9422 rex
= ~(*codep
>> 5) & 0x7;
9423 vex
.r
= *codep
& 0x10;
9424 switch ((*codep
& 0xf))
9429 vex_table_index
= EVEX_0F
;
9432 vex_table_index
= EVEX_0F38
;
9435 vex_table_index
= EVEX_0F3A
;
9439 /* The second byte after 0x62. */
9441 vex
.w
= *codep
& 0x80;
9442 if (vex
.w
&& address_mode
== mode_64bit
)
9445 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
9448 if (!(*codep
& 0x4))
9451 switch ((*codep
& 0x3))
9456 vex
.prefix
= DATA_PREFIX_OPCODE
;
9459 vex
.prefix
= REPE_PREFIX_OPCODE
;
9462 vex
.prefix
= REPNE_PREFIX_OPCODE
;
9466 /* The third byte after 0x62. */
9469 /* Remember the static rounding bits. */
9470 vex
.ll
= (*codep
>> 5) & 3;
9471 vex
.b
= (*codep
& 0x10) != 0;
9473 vex
.v
= *codep
& 0x8;
9474 vex
.mask_register_specifier
= *codep
& 0x7;
9475 vex
.zeroing
= *codep
& 0x80;
9477 if (address_mode
!= mode_64bit
)
9479 /* In 16/32-bit mode silently ignore following bits. */
9488 dp
= &evex_table
[vex_table_index
][vindex
];
9490 FETCH_DATA (info
, codep
+ 1);
9491 modrm
.mod
= (*codep
>> 6) & 3;
9492 modrm
.reg
= (*codep
>> 3) & 7;
9493 modrm
.rm
= *codep
& 7;
9495 /* Set vector length. */
9496 if (modrm
.mod
== 3 && vex
.b
)
9525 if (dp
->name
!= NULL
)
9528 return get_valid_dis386 (dp
, info
);
9532 get_sib (disassemble_info
*info
, int sizeflag
)
9534 /* If modrm.mod == 3, operand must be register. */
9536 && ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
9540 FETCH_DATA (info
, codep
+ 2);
9541 sib
.index
= (codep
[1] >> 3) & 7;
9542 sib
.scale
= (codep
[1] >> 6) & 3;
9543 sib
.base
= codep
[1] & 7;
9548 print_insn (bfd_vma pc
, disassemble_info
*info
)
9550 const struct dis386
*dp
;
9552 char *op_txt
[MAX_OPERANDS
];
9554 int sizeflag
, orig_sizeflag
;
9556 struct dis_private priv
;
9559 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
9560 if ((info
->mach
& bfd_mach_i386_i386
) != 0)
9561 address_mode
= mode_32bit
;
9562 else if (info
->mach
== bfd_mach_i386_i8086
)
9564 address_mode
= mode_16bit
;
9565 priv
.orig_sizeflag
= 0;
9568 address_mode
= mode_64bit
;
9570 if (intel_syntax
== (char) -1)
9571 intel_syntax
= (info
->mach
& bfd_mach_i386_intel_syntax
) != 0;
9573 for (p
= info
->disassembler_options
; p
!= NULL
; )
9575 if (CONST_STRNEQ (p
, "amd64"))
9577 else if (CONST_STRNEQ (p
, "intel64"))
9579 else if (CONST_STRNEQ (p
, "x86-64"))
9581 address_mode
= mode_64bit
;
9582 priv
.orig_sizeflag
|= AFLAG
| DFLAG
;
9584 else if (CONST_STRNEQ (p
, "i386"))
9586 address_mode
= mode_32bit
;
9587 priv
.orig_sizeflag
|= AFLAG
| DFLAG
;
9589 else if (CONST_STRNEQ (p
, "i8086"))
9591 address_mode
= mode_16bit
;
9592 priv
.orig_sizeflag
&= ~(AFLAG
| DFLAG
);
9594 else if (CONST_STRNEQ (p
, "intel"))
9597 if (CONST_STRNEQ (p
+ 5, "-mnemonic"))
9600 else if (CONST_STRNEQ (p
, "att"))
9603 if (CONST_STRNEQ (p
+ 3, "-mnemonic"))
9606 else if (CONST_STRNEQ (p
, "addr"))
9608 if (address_mode
== mode_64bit
)
9610 if (p
[4] == '3' && p
[5] == '2')
9611 priv
.orig_sizeflag
&= ~AFLAG
;
9612 else if (p
[4] == '6' && p
[5] == '4')
9613 priv
.orig_sizeflag
|= AFLAG
;
9617 if (p
[4] == '1' && p
[5] == '6')
9618 priv
.orig_sizeflag
&= ~AFLAG
;
9619 else if (p
[4] == '3' && p
[5] == '2')
9620 priv
.orig_sizeflag
|= AFLAG
;
9623 else if (CONST_STRNEQ (p
, "data"))
9625 if (p
[4] == '1' && p
[5] == '6')
9626 priv
.orig_sizeflag
&= ~DFLAG
;
9627 else if (p
[4] == '3' && p
[5] == '2')
9628 priv
.orig_sizeflag
|= DFLAG
;
9630 else if (CONST_STRNEQ (p
, "suffix"))
9631 priv
.orig_sizeflag
|= SUFFIX_ALWAYS
;
9633 p
= strchr (p
, ',');
9638 if (address_mode
== mode_64bit
&& sizeof (bfd_vma
) < 8)
9640 (*info
->fprintf_func
) (info
->stream
,
9641 _("64-bit address is disabled"));
9647 names64
= intel_names64
;
9648 names32
= intel_names32
;
9649 names16
= intel_names16
;
9650 names8
= intel_names8
;
9651 names8rex
= intel_names8rex
;
9652 names_seg
= intel_names_seg
;
9653 names_mm
= intel_names_mm
;
9654 names_bnd
= intel_names_bnd
;
9655 names_xmm
= intel_names_xmm
;
9656 names_ymm
= intel_names_ymm
;
9657 names_zmm
= intel_names_zmm
;
9658 names_tmm
= intel_names_tmm
;
9659 index64
= intel_index64
;
9660 index32
= intel_index32
;
9661 names_mask
= intel_names_mask
;
9662 index16
= intel_index16
;
9665 separator_char
= '+';
9670 names64
= att_names64
;
9671 names32
= att_names32
;
9672 names16
= att_names16
;
9673 names8
= att_names8
;
9674 names8rex
= att_names8rex
;
9675 names_seg
= att_names_seg
;
9676 names_mm
= att_names_mm
;
9677 names_bnd
= att_names_bnd
;
9678 names_xmm
= att_names_xmm
;
9679 names_ymm
= att_names_ymm
;
9680 names_zmm
= att_names_zmm
;
9681 names_tmm
= att_names_tmm
;
9682 index64
= att_index64
;
9683 index32
= att_index32
;
9684 names_mask
= att_names_mask
;
9685 index16
= att_index16
;
9688 separator_char
= ',';
9692 /* The output looks better if we put 7 bytes on a line, since that
9693 puts most long word instructions on a single line. Use 8 bytes
9695 if ((info
->mach
& bfd_mach_l1om
) != 0)
9696 info
->bytes_per_line
= 8;
9698 info
->bytes_per_line
= 7;
9700 info
->private_data
= &priv
;
9701 priv
.max_fetched
= priv
.the_buffer
;
9702 priv
.insn_start
= pc
;
9705 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
9713 start_codep
= priv
.the_buffer
;
9714 codep
= priv
.the_buffer
;
9716 if (OPCODES_SIGSETJMP (priv
.bailout
) != 0)
9720 /* Getting here means we tried for data but didn't get it. That
9721 means we have an incomplete instruction of some sort. Just
9722 print the first byte as a prefix or a .byte pseudo-op. */
9723 if (codep
> priv
.the_buffer
)
9725 name
= prefix_name (priv
.the_buffer
[0], priv
.orig_sizeflag
);
9727 (*info
->fprintf_func
) (info
->stream
, "%s", name
);
9730 /* Just print the first byte as a .byte instruction. */
9731 (*info
->fprintf_func
) (info
->stream
, ".byte 0x%x",
9732 (unsigned int) priv
.the_buffer
[0]);
9742 sizeflag
= priv
.orig_sizeflag
;
9744 if (!ckprefix () || rex_used
)
9746 /* Too many prefixes or unused REX prefixes. */
9748 i
< (int) ARRAY_SIZE (all_prefixes
) && all_prefixes
[i
];
9750 (*info
->fprintf_func
) (info
->stream
, "%s%s",
9752 prefix_name (all_prefixes
[i
], sizeflag
));
9758 FETCH_DATA (info
, codep
+ 1);
9759 two_source_ops
= (*codep
== 0x62) || (*codep
== 0xc8);
9761 if (((prefixes
& PREFIX_FWAIT
)
9762 && ((*codep
< 0xd8) || (*codep
> 0xdf))))
9764 /* Handle prefixes before fwait. */
9765 for (i
= 0; i
< fwait_prefix
&& all_prefixes
[i
];
9767 (*info
->fprintf_func
) (info
->stream
, "%s ",
9768 prefix_name (all_prefixes
[i
], sizeflag
));
9769 (*info
->fprintf_func
) (info
->stream
, "fwait");
9775 unsigned char threebyte
;
9778 FETCH_DATA (info
, codep
+ 1);
9780 dp
= &dis386_twobyte
[threebyte
];
9781 need_modrm
= twobyte_has_modrm
[*codep
];
9786 dp
= &dis386
[*codep
];
9787 need_modrm
= onebyte_has_modrm
[*codep
];
9791 /* Save sizeflag for printing the extra prefixes later before updating
9792 it for mnemonic and operand processing. The prefix names depend
9793 only on the address mode. */
9794 orig_sizeflag
= sizeflag
;
9795 if (prefixes
& PREFIX_ADDR
)
9797 if ((prefixes
& PREFIX_DATA
))
9803 FETCH_DATA (info
, codep
+ 1);
9804 modrm
.mod
= (*codep
>> 6) & 3;
9805 modrm
.reg
= (*codep
>> 3) & 7;
9806 modrm
.rm
= *codep
& 7;
9810 memset (&vex
, 0, sizeof (vex
));
9812 if (dp
->name
== NULL
&& dp
->op
[0].bytemode
== FLOATCODE
)
9814 get_sib (info
, sizeflag
);
9819 dp
= get_valid_dis386 (dp
, info
);
9820 if (dp
!= NULL
&& putop (dp
->name
, sizeflag
) == 0)
9822 get_sib (info
, sizeflag
);
9823 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
9826 op_ad
= MAX_OPERANDS
- 1 - i
;
9828 (*dp
->op
[i
].rtn
) (dp
->op
[i
].bytemode
, sizeflag
);
9829 /* For EVEX instruction after the last operand masking
9830 should be printed. */
9831 if (i
== 0 && vex
.evex
)
9833 /* Don't print {%k0}. */
9834 if (vex
.mask_register_specifier
)
9837 oappend (names_mask
[vex
.mask_register_specifier
]);
9847 /* Clear instruction information. */
9850 the_info
->insn_info_valid
= 0;
9851 the_info
->branch_delay_insns
= 0;
9852 the_info
->data_size
= 0;
9853 the_info
->insn_type
= dis_noninsn
;
9854 the_info
->target
= 0;
9855 the_info
->target2
= 0;
9858 /* Reset jump operation indicator. */
9862 int jump_detection
= 0;
9864 /* Extract flags. */
9865 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
9867 if ((dp
->op
[i
].rtn
== OP_J
)
9868 || (dp
->op
[i
].rtn
== OP_indirE
))
9869 jump_detection
|= 1;
9870 else if ((dp
->op
[i
].rtn
== BND_Fixup
)
9871 || (!dp
->op
[i
].rtn
&& !dp
->op
[i
].bytemode
))
9872 jump_detection
|= 2;
9873 else if ((dp
->op
[i
].bytemode
== cond_jump_mode
)
9874 || (dp
->op
[i
].bytemode
== loop_jcxz_mode
))
9875 jump_detection
|= 4;
9878 /* Determine if this is a jump or branch. */
9879 if ((jump_detection
& 0x3) == 0x3)
9882 if (jump_detection
& 0x4)
9883 the_info
->insn_type
= dis_condbranch
;
9885 the_info
->insn_type
=
9886 (dp
->name
&& !strncmp(dp
->name
, "call", 4))
9887 ? dis_jsr
: dis_branch
;
9891 /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
9892 are all 0s in inverted form. */
9893 if (need_vex
&& vex
.register_specifier
!= 0)
9895 (*info
->fprintf_func
) (info
->stream
, "(bad)");
9896 return end_codep
- priv
.the_buffer
;
9899 switch (dp
->prefix_requirement
)
9902 /* If only the data prefix is marked as mandatory, its absence renders
9903 the encoding invalid. Most other PREFIX_OPCODE rules still apply. */
9904 if (need_vex
? !vex
.prefix
: !(prefixes
& PREFIX_DATA
))
9906 (*info
->fprintf_func
) (info
->stream
, "(bad)");
9907 return end_codep
- priv
.the_buffer
;
9909 used_prefixes
|= PREFIX_DATA
;
9912 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
9913 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
9914 used by putop and MMX/SSE operand and may be overridden by the
9915 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
9918 ? vex
.prefix
== REPE_PREFIX_OPCODE
9919 || vex
.prefix
== REPNE_PREFIX_OPCODE
9921 & (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0)
9923 & (PREFIX_REPZ
| PREFIX_REPNZ
)) == 0)
9925 ? vex
.prefix
== DATA_PREFIX_OPCODE
9927 & (PREFIX_REPZ
| PREFIX_REPNZ
| PREFIX_DATA
))
9929 && (used_prefixes
& PREFIX_DATA
) == 0))
9930 || (vex
.evex
&& dp
->prefix_requirement
!= PREFIX_DATA
9931 && !vex
.w
!= !(used_prefixes
& PREFIX_DATA
)))
9933 (*info
->fprintf_func
) (info
->stream
, "(bad)");
9934 return end_codep
- priv
.the_buffer
;
9939 /* Check if the REX prefix is used. */
9940 if ((rex
^ rex_used
) == 0 && !need_vex
&& last_rex_prefix
>= 0)
9941 all_prefixes
[last_rex_prefix
] = 0;
9943 /* Check if the SEG prefix is used. */
9944 if ((prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
| PREFIX_ES
9945 | PREFIX_FS
| PREFIX_GS
)) != 0
9946 && (used_prefixes
& active_seg_prefix
) != 0)
9947 all_prefixes
[last_seg_prefix
] = 0;
9949 /* Check if the ADDR prefix is used. */
9950 if ((prefixes
& PREFIX_ADDR
) != 0
9951 && (used_prefixes
& PREFIX_ADDR
) != 0)
9952 all_prefixes
[last_addr_prefix
] = 0;
9954 /* Check if the DATA prefix is used. */
9955 if ((prefixes
& PREFIX_DATA
) != 0
9956 && (used_prefixes
& PREFIX_DATA
) != 0
9958 all_prefixes
[last_data_prefix
] = 0;
9960 /* Print the extra prefixes. */
9962 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
9963 if (all_prefixes
[i
])
9966 name
= prefix_name (all_prefixes
[i
], orig_sizeflag
);
9969 prefix_length
+= strlen (name
) + 1;
9970 (*info
->fprintf_func
) (info
->stream
, "%s ", name
);
9973 /* Check maximum code length. */
9974 if ((codep
- start_codep
) > MAX_CODE_LENGTH
)
9976 (*info
->fprintf_func
) (info
->stream
, "(bad)");
9977 return MAX_CODE_LENGTH
;
9980 obufp
= mnemonicendp
;
9981 for (i
= strlen (obuf
) + prefix_length
; i
< 6; i
++)
9984 (*info
->fprintf_func
) (info
->stream
, "%s", obuf
);
9986 /* The enter and bound instructions are printed with operands in the same
9987 order as the intel book; everything else is printed in reverse order. */
9988 if (intel_syntax
|| two_source_ops
)
9992 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
9993 op_txt
[i
] = op_out
[i
];
9995 if (intel_syntax
&& dp
&& dp
->op
[2].rtn
== OP_Rounding
9996 && dp
->op
[3].rtn
== OP_E
&& dp
->op
[4].rtn
== NULL
)
9998 op_txt
[2] = op_out
[3];
9999 op_txt
[3] = op_out
[2];
10002 for (i
= 0; i
< (MAX_OPERANDS
>> 1); ++i
)
10004 op_ad
= op_index
[i
];
10005 op_index
[i
] = op_index
[MAX_OPERANDS
- 1 - i
];
10006 op_index
[MAX_OPERANDS
- 1 - i
] = op_ad
;
10007 riprel
= op_riprel
[i
];
10008 op_riprel
[i
] = op_riprel
[MAX_OPERANDS
- 1 - i
];
10009 op_riprel
[MAX_OPERANDS
- 1 - i
] = riprel
;
10014 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
10015 op_txt
[MAX_OPERANDS
- 1 - i
] = op_out
[i
];
10019 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
10023 (*info
->fprintf_func
) (info
->stream
, ",");
10024 if (op_index
[i
] != -1 && !op_riprel
[i
])
10026 bfd_vma target
= (bfd_vma
) op_address
[op_index
[i
]];
10028 if (the_info
&& op_is_jump
)
10030 the_info
->insn_info_valid
= 1;
10031 the_info
->branch_delay_insns
= 0;
10032 the_info
->data_size
= 0;
10033 the_info
->target
= target
;
10034 the_info
->target2
= 0;
10036 (*info
->print_address_func
) (target
, info
);
10039 (*info
->fprintf_func
) (info
->stream
, "%s", op_txt
[i
]);
10043 for (i
= 0; i
< MAX_OPERANDS
; i
++)
10044 if (op_index
[i
] != -1 && op_riprel
[i
])
10046 (*info
->fprintf_func
) (info
->stream
, " # ");
10047 (*info
->print_address_func
) ((bfd_vma
) (start_pc
+ (codep
- start_codep
)
10048 + op_address
[op_index
[i
]]), info
);
10051 return codep
- priv
.the_buffer
;
10054 static const char *float_mem
[] = {
10129 static const unsigned char float_mem_mode
[] = {
10204 #define ST { OP_ST, 0 }
10205 #define STi { OP_STi, 0 }
10207 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
10208 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
10209 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
10210 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
10211 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
10212 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
10213 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
10214 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
10215 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
10217 static const struct dis386 float_reg
[][8] = {
10220 { "fadd", { ST
, STi
}, 0 },
10221 { "fmul", { ST
, STi
}, 0 },
10222 { "fcom", { STi
}, 0 },
10223 { "fcomp", { STi
}, 0 },
10224 { "fsub", { ST
, STi
}, 0 },
10225 { "fsubr", { ST
, STi
}, 0 },
10226 { "fdiv", { ST
, STi
}, 0 },
10227 { "fdivr", { ST
, STi
}, 0 },
10231 { "fld", { STi
}, 0 },
10232 { "fxch", { STi
}, 0 },
10242 { "fcmovb", { ST
, STi
}, 0 },
10243 { "fcmove", { ST
, STi
}, 0 },
10244 { "fcmovbe",{ ST
, STi
}, 0 },
10245 { "fcmovu", { ST
, STi
}, 0 },
10253 { "fcmovnb",{ ST
, STi
}, 0 },
10254 { "fcmovne",{ ST
, STi
}, 0 },
10255 { "fcmovnbe",{ ST
, STi
}, 0 },
10256 { "fcmovnu",{ ST
, STi
}, 0 },
10258 { "fucomi", { ST
, STi
}, 0 },
10259 { "fcomi", { ST
, STi
}, 0 },
10264 { "fadd", { STi
, ST
}, 0 },
10265 { "fmul", { STi
, ST
}, 0 },
10268 { "fsub{!M|r}", { STi
, ST
}, 0 },
10269 { "fsub{M|}", { STi
, ST
}, 0 },
10270 { "fdiv{!M|r}", { STi
, ST
}, 0 },
10271 { "fdiv{M|}", { STi
, ST
}, 0 },
10275 { "ffree", { STi
}, 0 },
10277 { "fst", { STi
}, 0 },
10278 { "fstp", { STi
}, 0 },
10279 { "fucom", { STi
}, 0 },
10280 { "fucomp", { STi
}, 0 },
10286 { "faddp", { STi
, ST
}, 0 },
10287 { "fmulp", { STi
, ST
}, 0 },
10290 { "fsub{!M|r}p", { STi
, ST
}, 0 },
10291 { "fsub{M|}p", { STi
, ST
}, 0 },
10292 { "fdiv{!M|r}p", { STi
, ST
}, 0 },
10293 { "fdiv{M|}p", { STi
, ST
}, 0 },
10297 { "ffreep", { STi
}, 0 },
10302 { "fucomip", { ST
, STi
}, 0 },
10303 { "fcomip", { ST
, STi
}, 0 },
10308 static char *fgrps
[][8] = {
10311 "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10316 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10321 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
10326 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
10331 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
10336 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
10341 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10346 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
10347 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
10352 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10357 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10362 swap_operand (void)
10364 mnemonicendp
[0] = '.';
10365 mnemonicendp
[1] = 's';
10370 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED
,
10371 int sizeflag ATTRIBUTE_UNUSED
)
10373 /* Skip mod/rm byte. */
10379 dofloat (int sizeflag
)
10381 const struct dis386
*dp
;
10382 unsigned char floatop
;
10384 floatop
= codep
[-1];
10386 if (modrm
.mod
!= 3)
10388 int fp_indx
= (floatop
- 0xd8) * 8 + modrm
.reg
;
10390 putop (float_mem
[fp_indx
], sizeflag
);
10393 OP_E (float_mem_mode
[fp_indx
], sizeflag
);
10396 /* Skip mod/rm byte. */
10400 dp
= &float_reg
[floatop
- 0xd8][modrm
.reg
];
10401 if (dp
->name
== NULL
)
10403 putop (fgrps
[dp
->op
[0].bytemode
][modrm
.rm
], sizeflag
);
10405 /* Instruction fnstsw is only one with strange arg. */
10406 if (floatop
== 0xdf && codep
[-1] == 0xe0)
10407 strcpy (op_out
[0], names16
[0]);
10411 putop (dp
->name
, sizeflag
);
10416 (*dp
->op
[0].rtn
) (dp
->op
[0].bytemode
, sizeflag
);
10421 (*dp
->op
[1].rtn
) (dp
->op
[1].bytemode
, sizeflag
);
10425 /* Like oappend (below), but S is a string starting with '%'.
10426 In Intel syntax, the '%' is elided. */
10428 oappend_maybe_intel (const char *s
)
10430 oappend (s
+ intel_syntax
);
10434 OP_ST (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
10436 oappend_maybe_intel ("%st");
10440 OP_STi (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
10442 sprintf (scratchbuf
, "%%st(%d)", modrm
.rm
);
10443 oappend_maybe_intel (scratchbuf
);
10446 /* Capital letters in template are macros. */
10448 putop (const char *in_template
, int sizeflag
)
10453 unsigned int l
= 0, len
= 0;
10456 for (p
= in_template
; *p
; p
++)
10460 if (l
>= sizeof (last
) || !ISUPPER (*p
))
10479 while (*++p
!= '|')
10480 if (*p
== '}' || *p
== '\0')
10486 while (*++p
!= '}')
10498 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
10507 if (sizeflag
& SUFFIX_ALWAYS
)
10510 else if (l
== 1 && last
[0] == 'L')
10512 if (address_mode
== mode_64bit
10513 && !(prefixes
& PREFIX_ADDR
))
10526 if (intel_syntax
&& !alt
)
10528 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
10530 if (sizeflag
& DFLAG
)
10531 *obufp
++ = intel_syntax
? 'd' : 'l';
10533 *obufp
++ = intel_syntax
? 'w' : 's';
10534 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10538 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
10541 if (modrm
.mod
== 3)
10547 if (sizeflag
& DFLAG
)
10548 *obufp
++ = intel_syntax
? 'd' : 'l';
10551 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10557 case 'E': /* For jcxz/jecxz */
10558 if (address_mode
== mode_64bit
)
10560 if (sizeflag
& AFLAG
)
10566 if (sizeflag
& AFLAG
)
10568 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
10573 if ((prefixes
& PREFIX_ADDR
) || (sizeflag
& SUFFIX_ALWAYS
))
10575 if (sizeflag
& AFLAG
)
10576 *obufp
++ = address_mode
== mode_64bit
? 'q' : 'l';
10578 *obufp
++ = address_mode
== mode_64bit
? 'l' : 'w';
10579 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
10583 if (intel_syntax
|| (obufp
[-1] != 's' && !(sizeflag
& SUFFIX_ALWAYS
)))
10585 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
10589 if (!(rex
& REX_W
))
10590 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10595 if ((prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_CS
10596 || (prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_DS
)
10598 used_prefixes
|= prefixes
& (PREFIX_CS
| PREFIX_DS
);
10601 if (prefixes
& PREFIX_DS
)
10617 if (intel_mnemonic
!= cond
)
10621 if ((prefixes
& PREFIX_FWAIT
) == 0)
10624 used_prefixes
|= PREFIX_FWAIT
;
10630 else if (intel_syntax
&& (sizeflag
& DFLAG
))
10634 if (!(rex
& REX_W
))
10635 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10638 if (address_mode
== mode_64bit
10639 && (isa64
== intel64
|| (rex
& REX_W
)
10640 || !(prefixes
& PREFIX_DATA
)))
10642 if (sizeflag
& SUFFIX_ALWAYS
)
10646 /* Fall through. */
10650 if (need_modrm
&& modrm
.mod
== 3 && !(sizeflag
& SUFFIX_ALWAYS
))
10652 /* Fall through. */
10654 if ((!(rex
& REX_W
) && (prefixes
& PREFIX_DATA
))
10655 || ((sizeflag
& SUFFIX_ALWAYS
)
10656 && address_mode
!= mode_64bit
))
10658 *obufp
++ = (sizeflag
& DFLAG
) ?
10659 intel_syntax
? 'd' : 'l' : 'w';
10660 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10662 else if (sizeflag
& SUFFIX_ALWAYS
)
10665 else if (l
== 1 && last
[0] == 'L')
10667 if ((prefixes
& PREFIX_DATA
)
10669 || (sizeflag
& SUFFIX_ALWAYS
))
10676 if (sizeflag
& DFLAG
)
10677 *obufp
++ = intel_syntax
? 'd' : 'l';
10680 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10690 if (intel_syntax
&& !alt
)
10693 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
10699 if (sizeflag
& DFLAG
)
10700 *obufp
++ = intel_syntax
? 'd' : 'l';
10703 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10707 else if (l
== 1 && last
[0] == 'D')
10708 *obufp
++ = vex
.w
? 'q' : 'd';
10709 else if (l
== 1 && last
[0] == 'L')
10711 if (cond
? modrm
.mod
== 3 && !(sizeflag
& SUFFIX_ALWAYS
)
10712 : address_mode
!= mode_64bit
)
10719 else if((address_mode
== mode_64bit
&& need_modrm
&& cond
)
10720 || (sizeflag
& SUFFIX_ALWAYS
))
10721 *obufp
++ = intel_syntax
? 'd' : 'l';
10730 else if (sizeflag
& DFLAG
)
10739 if (intel_syntax
&& !p
[1]
10740 && ((rex
& REX_W
) || (sizeflag
& DFLAG
)))
10742 if (!(rex
& REX_W
))
10743 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10750 if (address_mode
== mode_64bit
10751 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
10753 if (sizeflag
& SUFFIX_ALWAYS
)
10758 else if (l
== 1 && last
[0] == 'L')
10769 /* Fall through. */
10777 if (sizeflag
& SUFFIX_ALWAYS
)
10783 if (sizeflag
& DFLAG
)
10787 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10791 else if (l
== 1 && last
[0] == 'L')
10793 if (address_mode
== mode_64bit
10794 && !(prefixes
& PREFIX_ADDR
))
10810 ? vex
.prefix
== DATA_PREFIX_OPCODE
10811 : prefixes
& PREFIX_DATA
)
10814 used_prefixes
|= PREFIX_DATA
;
10820 if (l
== 1 && last
[0] == 'X')
10825 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
10827 switch (vex
.length
)
10847 /* These insns ignore ModR/M.mod: Force it to 3 for OP_E(). */
10849 if (!intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
10850 *obufp
++ = address_mode
== mode_64bit
? 'q' : 'l';
10852 else if (l
== 1 && last
[0] == 'X')
10854 if (!need_vex
|| !vex
.evex
)
10857 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
10859 switch (vex
.length
)
10880 /* operand size flag for cwtl, cbtw */
10889 else if (sizeflag
& DFLAG
)
10893 if (!(rex
& REX_W
))
10894 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10900 if (last
[0] == 'X')
10901 *obufp
++ = vex
.w
? 'd': 's';
10902 else if (last
[0] == 'B')
10903 *obufp
++ = vex
.w
? 'w': 'b';
10913 if (isa64
== intel64
&& (rex
& REX_W
))
10919 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
10921 if (sizeflag
& DFLAG
)
10925 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10934 mnemonicendp
= obufp
;
10939 oappend (const char *s
)
10941 obufp
= stpcpy (obufp
, s
);
10947 /* Only print the active segment register. */
10948 if (!active_seg_prefix
)
10951 used_prefixes
|= active_seg_prefix
;
10952 switch (active_seg_prefix
)
10955 oappend_maybe_intel ("%cs:");
10958 oappend_maybe_intel ("%ds:");
10961 oappend_maybe_intel ("%ss:");
10964 oappend_maybe_intel ("%es:");
10967 oappend_maybe_intel ("%fs:");
10970 oappend_maybe_intel ("%gs:");
10978 OP_indirE (int bytemode
, int sizeflag
)
10982 OP_E (bytemode
, sizeflag
);
10986 print_operand_value (char *buf
, int hex
, bfd_vma disp
)
10988 if (address_mode
== mode_64bit
)
10996 sprintf_vma (tmp
, disp
);
10997 for (i
= 0; tmp
[i
] == '0' && tmp
[i
+ 1]; i
++);
10998 strcpy (buf
+ 2, tmp
+ i
);
11002 bfd_signed_vma v
= disp
;
11009 /* Check for possible overflow on 0x8000000000000000. */
11012 strcpy (buf
, "9223372036854775808");
11026 tmp
[28 - i
] = (v
% 10) + '0';
11030 strcpy (buf
, tmp
+ 29 - i
);
11036 sprintf (buf
, "0x%x", (unsigned int) disp
);
11038 sprintf (buf
, "%d", (int) disp
);
11042 /* Put DISP in BUF as signed hex number. */
11045 print_displacement (char *buf
, bfd_vma disp
)
11047 bfd_signed_vma val
= disp
;
11056 /* Check for possible overflow. */
11059 switch (address_mode
)
11062 strcpy (buf
+ j
, "0x8000000000000000");
11065 strcpy (buf
+ j
, "0x80000000");
11068 strcpy (buf
+ j
, "0x8000");
11078 sprintf_vma (tmp
, (bfd_vma
) val
);
11079 for (i
= 0; tmp
[i
] == '0'; i
++)
11081 if (tmp
[i
] == '\0')
11083 strcpy (buf
+ j
, tmp
+ i
);
11087 intel_operand_size (int bytemode
, int sizeflag
)
11091 && (bytemode
== x_mode
11092 || bytemode
== evex_half_bcst_xmmq_mode
))
11095 oappend ("QWORD PTR ");
11097 oappend ("DWORD PTR ");
11106 oappend ("BYTE PTR ");
11111 oappend ("WORD PTR ");
11114 if (address_mode
== mode_64bit
&& isa64
== intel64
)
11116 oappend ("QWORD PTR ");
11119 /* Fall through. */
11121 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
11123 oappend ("QWORD PTR ");
11126 /* Fall through. */
11132 oappend ("QWORD PTR ");
11133 else if (bytemode
== dq_mode
)
11134 oappend ("DWORD PTR ");
11137 if (sizeflag
& DFLAG
)
11138 oappend ("DWORD PTR ");
11140 oappend ("WORD PTR ");
11141 used_prefixes
|= (prefixes
& PREFIX_DATA
);
11145 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
11147 oappend ("WORD PTR ");
11148 if (!(rex
& REX_W
))
11149 used_prefixes
|= (prefixes
& PREFIX_DATA
);
11152 if (sizeflag
& DFLAG
)
11153 oappend ("QWORD PTR ");
11155 oappend ("DWORD PTR ");
11156 used_prefixes
|= (prefixes
& PREFIX_DATA
);
11159 if (!(sizeflag
& DFLAG
) && isa64
== intel64
)
11160 oappend ("WORD PTR ");
11162 oappend ("DWORD PTR ");
11163 used_prefixes
|= (prefixes
& PREFIX_DATA
);
11168 oappend ("DWORD PTR ");
11172 oappend ("QWORD PTR ");
11175 if (address_mode
== mode_64bit
)
11176 oappend ("QWORD PTR ");
11178 oappend ("DWORD PTR ");
11181 if (sizeflag
& DFLAG
)
11182 oappend ("FWORD PTR ");
11184 oappend ("DWORD PTR ");
11185 used_prefixes
|= (prefixes
& PREFIX_DATA
);
11188 oappend ("TBYTE PTR ");
11192 case evex_x_gscat_mode
:
11193 case evex_x_nobcst_mode
:
11197 switch (vex
.length
)
11200 oappend ("XMMWORD PTR ");
11203 oappend ("YMMWORD PTR ");
11206 oappend ("ZMMWORD PTR ");
11213 oappend ("XMMWORD PTR ");
11216 oappend ("XMMWORD PTR ");
11219 oappend ("YMMWORD PTR ");
11222 case evex_half_bcst_xmmq_mode
:
11226 switch (vex
.length
)
11229 oappend ("QWORD PTR ");
11232 oappend ("XMMWORD PTR ");
11235 oappend ("YMMWORD PTR ");
11245 switch (vex
.length
)
11250 oappend ("BYTE PTR ");
11260 switch (vex
.length
)
11265 oappend ("WORD PTR ");
11275 switch (vex
.length
)
11280 oappend ("DWORD PTR ");
11290 switch (vex
.length
)
11295 oappend ("QWORD PTR ");
11305 switch (vex
.length
)
11308 oappend ("WORD PTR ");
11311 oappend ("DWORD PTR ");
11314 oappend ("QWORD PTR ");
11324 switch (vex
.length
)
11327 oappend ("DWORD PTR ");
11330 oappend ("QWORD PTR ");
11333 oappend ("XMMWORD PTR ");
11343 switch (vex
.length
)
11346 oappend ("QWORD PTR ");
11349 oappend ("YMMWORD PTR ");
11352 oappend ("ZMMWORD PTR ");
11362 switch (vex
.length
)
11366 oappend ("XMMWORD PTR ");
11373 oappend ("OWORD PTR ");
11375 case vex_scalar_w_dq_mode
:
11380 oappend ("QWORD PTR ");
11382 oappend ("DWORD PTR ");
11384 case vex_vsib_d_w_dq_mode
:
11385 case vex_vsib_q_w_dq_mode
:
11392 oappend ("QWORD PTR ");
11394 oappend ("DWORD PTR ");
11398 switch (vex
.length
)
11401 oappend ("XMMWORD PTR ");
11404 oappend ("YMMWORD PTR ");
11407 oappend ("ZMMWORD PTR ");
11414 case vex_vsib_q_w_d_mode
:
11415 case vex_vsib_d_w_d_mode
:
11416 if (!need_vex
|| !vex
.evex
)
11419 switch (vex
.length
)
11422 oappend ("QWORD PTR ");
11425 oappend ("XMMWORD PTR ");
11428 oappend ("YMMWORD PTR ");
11436 if (!need_vex
|| vex
.length
!= 128)
11439 oappend ("DWORD PTR ");
11441 oappend ("BYTE PTR ");
11447 oappend ("QWORD PTR ");
11449 oappend ("WORD PTR ");
11459 OP_E_register (int bytemode
, int sizeflag
)
11461 int reg
= modrm
.rm
;
11462 const char **names
;
11468 if ((sizeflag
& SUFFIX_ALWAYS
)
11469 && (bytemode
== b_swap_mode
11470 || bytemode
== bnd_swap_mode
11471 || bytemode
== v_swap_mode
))
11498 names
= address_mode
== mode_64bit
? names64
: names32
;
11501 case bnd_swap_mode
:
11510 if (address_mode
== mode_64bit
&& isa64
== intel64
)
11515 /* Fall through. */
11517 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
11523 /* Fall through. */
11533 else if (bytemode
!= v_mode
&& bytemode
!= v_swap_mode
)
11537 if (sizeflag
& DFLAG
)
11541 used_prefixes
|= (prefixes
& PREFIX_DATA
);
11545 if (!(sizeflag
& DFLAG
) && isa64
== intel64
)
11549 used_prefixes
|= (prefixes
& PREFIX_DATA
);
11552 names
= (address_mode
== mode_64bit
11553 ? names64
: names32
);
11554 if (!(prefixes
& PREFIX_ADDR
))
11555 names
= (address_mode
== mode_16bit
11556 ? names16
: names
);
11559 /* Remove "addr16/addr32". */
11560 all_prefixes
[last_addr_prefix
] = 0;
11561 names
= (address_mode
!= mode_32bit
11562 ? names32
: names16
);
11563 used_prefixes
|= PREFIX_ADDR
;
11573 names
= names_mask
;
11578 oappend (INTERNAL_DISASSEMBLER_ERROR
);
11581 oappend (names
[reg
]);
11585 OP_E_memory (int bytemode
, int sizeflag
)
11588 int add
= (rex
& REX_B
) ? 8 : 0;
11594 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
11596 && bytemode
!= x_mode
11597 && bytemode
!= xmmq_mode
11598 && bytemode
!= evex_half_bcst_xmmq_mode
)
11616 if (address_mode
!= mode_64bit
)
11626 case vex_scalar_w_dq_mode
:
11627 case vex_vsib_d_w_dq_mode
:
11628 case vex_vsib_d_w_d_mode
:
11629 case vex_vsib_q_w_dq_mode
:
11630 case vex_vsib_q_w_d_mode
:
11631 case evex_x_gscat_mode
:
11632 shift
= vex
.w
? 3 : 2;
11635 case evex_half_bcst_xmmq_mode
:
11639 shift
= vex
.w
? 3 : 2;
11642 /* Fall through. */
11646 case evex_x_nobcst_mode
:
11648 switch (vex
.length
)
11662 /* Make necessary corrections to shift for modes that need it. */
11663 if (bytemode
== xmmq_mode
11664 || bytemode
== evex_half_bcst_xmmq_mode
11665 || (bytemode
== ymmq_mode
&& vex
.length
== 128))
11667 else if (bytemode
== xmmqd_mode
)
11669 else if (bytemode
== xmmdw_mode
)
11684 shift
= vex
.w
? 1 : 0;
11695 intel_operand_size (bytemode
, sizeflag
);
11698 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
11700 /* 32/64 bit address mode */
11710 int addr32flag
= !((sizeflag
& AFLAG
)
11711 || bytemode
== v_bnd_mode
11712 || bytemode
== v_bndmk_mode
11713 || bytemode
== bnd_mode
11714 || bytemode
== bnd_swap_mode
);
11715 const char **indexes64
= names64
;
11716 const char **indexes32
= names32
;
11726 vindex
= sib
.index
;
11732 case vex_vsib_d_w_dq_mode
:
11733 case vex_vsib_d_w_d_mode
:
11734 case vex_vsib_q_w_dq_mode
:
11735 case vex_vsib_q_w_d_mode
:
11745 switch (vex
.length
)
11748 indexes64
= indexes32
= names_xmm
;
11752 || bytemode
== vex_vsib_q_w_dq_mode
11753 || bytemode
== vex_vsib_q_w_d_mode
)
11754 indexes64
= indexes32
= names_ymm
;
11756 indexes64
= indexes32
= names_xmm
;
11760 || bytemode
== vex_vsib_q_w_dq_mode
11761 || bytemode
== vex_vsib_q_w_d_mode
)
11762 indexes64
= indexes32
= names_zmm
;
11764 indexes64
= indexes32
= names_ymm
;
11771 haveindex
= vindex
!= 4;
11780 /* mandatory non-vector SIB must have sib */
11781 if (bytemode
== vex_sibmem_mode
)
11787 rbase
= base
+ add
;
11795 if (address_mode
== mode_64bit
&& !havesib
)
11798 if (riprel
&& bytemode
== v_bndmk_mode
)
11806 FETCH_DATA (the_info
, codep
+ 1);
11808 if ((disp
& 0x80) != 0)
11810 if (vex
.evex
&& shift
> 0)
11823 && address_mode
!= mode_16bit
)
11825 if (address_mode
== mode_64bit
)
11829 /* Without base nor index registers, zero-extend the
11830 lower 32-bit displacement to 64 bits. */
11831 disp
= (unsigned int) disp
;
11838 /* In 32-bit mode, we need index register to tell [offset]
11839 from [eiz*1 + offset]. */
11844 havedisp
= (havebase
11846 || (havesib
&& (haveindex
|| scale
!= 0)));
11849 if (modrm
.mod
!= 0 || base
== 5)
11851 if (havedisp
|| riprel
)
11852 print_displacement (scratchbuf
, disp
);
11854 print_operand_value (scratchbuf
, 1, disp
);
11855 oappend (scratchbuf
);
11859 oappend (!addr32flag
? "(%rip)" : "(%eip)");
11863 if ((havebase
|| haveindex
|| needindex
|| needaddr32
|| riprel
)
11864 && (address_mode
!= mode_64bit
11865 || ((bytemode
!= v_bnd_mode
)
11866 && (bytemode
!= v_bndmk_mode
)
11867 && (bytemode
!= bnd_mode
)
11868 && (bytemode
!= bnd_swap_mode
))))
11869 used_prefixes
|= PREFIX_ADDR
;
11871 if (havedisp
|| (intel_syntax
&& riprel
))
11873 *obufp
++ = open_char
;
11874 if (intel_syntax
&& riprel
)
11877 oappend (!addr32flag
? "rip" : "eip");
11881 oappend (address_mode
== mode_64bit
&& !addr32flag
11882 ? names64
[rbase
] : names32
[rbase
]);
11885 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
11886 print index to tell base + index from base. */
11890 || (havebase
&& base
!= ESP_REG_NUM
))
11892 if (!intel_syntax
|| havebase
)
11894 *obufp
++ = separator_char
;
11898 oappend (address_mode
== mode_64bit
&& !addr32flag
11899 ? indexes64
[vindex
] : indexes32
[vindex
]);
11901 oappend (address_mode
== mode_64bit
&& !addr32flag
11902 ? index64
: index32
);
11904 *obufp
++ = scale_char
;
11906 sprintf (scratchbuf
, "%d", 1 << scale
);
11907 oappend (scratchbuf
);
11911 && (disp
|| modrm
.mod
!= 0 || base
== 5))
11913 if (!havedisp
|| (bfd_signed_vma
) disp
>= 0)
11918 else if (modrm
.mod
!= 1 && disp
!= -disp
)
11922 disp
= - (bfd_signed_vma
) disp
;
11926 print_displacement (scratchbuf
, disp
);
11928 print_operand_value (scratchbuf
, 1, disp
);
11929 oappend (scratchbuf
);
11932 *obufp
++ = close_char
;
11935 else if (intel_syntax
)
11937 if (modrm
.mod
!= 0 || base
== 5)
11939 if (!active_seg_prefix
)
11941 oappend (names_seg
[ds_reg
- es_reg
]);
11944 print_operand_value (scratchbuf
, 1, disp
);
11945 oappend (scratchbuf
);
11949 else if (bytemode
== v_bnd_mode
11950 || bytemode
== v_bndmk_mode
11951 || bytemode
== bnd_mode
11952 || bytemode
== bnd_swap_mode
)
11959 /* 16 bit address mode */
11960 used_prefixes
|= prefixes
& PREFIX_ADDR
;
11967 if ((disp
& 0x8000) != 0)
11972 FETCH_DATA (the_info
, codep
+ 1);
11974 if ((disp
& 0x80) != 0)
11976 if (vex
.evex
&& shift
> 0)
11981 if ((disp
& 0x8000) != 0)
11987 if (modrm
.mod
!= 0 || modrm
.rm
== 6)
11989 print_displacement (scratchbuf
, disp
);
11990 oappend (scratchbuf
);
11993 if (modrm
.mod
!= 0 || modrm
.rm
!= 6)
11995 *obufp
++ = open_char
;
11997 oappend (index16
[modrm
.rm
]);
11999 && (disp
|| modrm
.mod
!= 0 || modrm
.rm
== 6))
12001 if ((bfd_signed_vma
) disp
>= 0)
12006 else if (modrm
.mod
!= 1)
12010 disp
= - (bfd_signed_vma
) disp
;
12013 print_displacement (scratchbuf
, disp
);
12014 oappend (scratchbuf
);
12017 *obufp
++ = close_char
;
12020 else if (intel_syntax
)
12022 if (!active_seg_prefix
)
12024 oappend (names_seg
[ds_reg
- es_reg
]);
12027 print_operand_value (scratchbuf
, 1, disp
& 0xffff);
12028 oappend (scratchbuf
);
12031 if (vex
.evex
&& vex
.b
12032 && (bytemode
== x_mode
12033 || bytemode
== xmmq_mode
12034 || bytemode
== evex_half_bcst_xmmq_mode
))
12037 || bytemode
== xmmq_mode
12038 || bytemode
== evex_half_bcst_xmmq_mode
)
12040 switch (vex
.length
)
12043 oappend ("{1to2}");
12046 oappend ("{1to4}");
12049 oappend ("{1to8}");
12057 switch (vex
.length
)
12060 oappend ("{1to4}");
12063 oappend ("{1to8}");
12066 oappend ("{1to16}");
12076 OP_E (int bytemode
, int sizeflag
)
12078 /* Skip mod/rm byte. */
12082 if (modrm
.mod
== 3)
12083 OP_E_register (bytemode
, sizeflag
);
12085 OP_E_memory (bytemode
, sizeflag
);
12089 OP_G (int bytemode
, int sizeflag
)
12092 const char **names
;
12102 oappend (names8rex
[modrm
.reg
+ add
]);
12104 oappend (names8
[modrm
.reg
+ add
]);
12107 oappend (names16
[modrm
.reg
+ add
]);
12112 oappend (names32
[modrm
.reg
+ add
]);
12115 oappend (names64
[modrm
.reg
+ add
]);
12118 if (modrm
.reg
> 0x3)
12123 oappend (names_bnd
[modrm
.reg
]);
12133 oappend (names64
[modrm
.reg
+ add
]);
12134 else if (bytemode
!= v_mode
&& bytemode
!= movsxd_mode
)
12135 oappend (names32
[modrm
.reg
+ add
]);
12138 if (sizeflag
& DFLAG
)
12139 oappend (names32
[modrm
.reg
+ add
]);
12141 oappend (names16
[modrm
.reg
+ add
]);
12142 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12146 names
= (address_mode
== mode_64bit
12147 ? names64
: names32
);
12148 if (!(prefixes
& PREFIX_ADDR
))
12150 if (address_mode
== mode_16bit
)
12155 /* Remove "addr16/addr32". */
12156 all_prefixes
[last_addr_prefix
] = 0;
12157 names
= (address_mode
!= mode_32bit
12158 ? names32
: names16
);
12159 used_prefixes
|= PREFIX_ADDR
;
12161 oappend (names
[modrm
.reg
+ add
]);
12164 if (address_mode
== mode_64bit
)
12165 oappend (names64
[modrm
.reg
+ add
]);
12167 oappend (names32
[modrm
.reg
+ add
]);
12171 if ((modrm
.reg
+ add
) > 0x7)
12176 oappend (names_mask
[modrm
.reg
+ add
]);
12179 oappend (INTERNAL_DISASSEMBLER_ERROR
);
12192 FETCH_DATA (the_info
, codep
+ 8);
12193 a
= *codep
++ & 0xff;
12194 a
|= (*codep
++ & 0xff) << 8;
12195 a
|= (*codep
++ & 0xff) << 16;
12196 a
|= (*codep
++ & 0xffu
) << 24;
12197 b
= *codep
++ & 0xff;
12198 b
|= (*codep
++ & 0xff) << 8;
12199 b
|= (*codep
++ & 0xff) << 16;
12200 b
|= (*codep
++ & 0xffu
) << 24;
12201 x
= a
+ ((bfd_vma
) b
<< 32);
12209 static bfd_signed_vma
12212 bfd_signed_vma x
= 0;
12214 FETCH_DATA (the_info
, codep
+ 4);
12215 x
= *codep
++ & (bfd_signed_vma
) 0xff;
12216 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
12217 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
12218 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
12222 static bfd_signed_vma
12225 bfd_signed_vma x
= 0;
12227 FETCH_DATA (the_info
, codep
+ 4);
12228 x
= *codep
++ & (bfd_signed_vma
) 0xff;
12229 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
12230 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
12231 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
12233 x
= (x
^ ((bfd_signed_vma
) 1 << 31)) - ((bfd_signed_vma
) 1 << 31);
12243 FETCH_DATA (the_info
, codep
+ 2);
12244 x
= *codep
++ & 0xff;
12245 x
|= (*codep
++ & 0xff) << 8;
12250 set_op (bfd_vma op
, int riprel
)
12252 op_index
[op_ad
] = op_ad
;
12253 if (address_mode
== mode_64bit
)
12255 op_address
[op_ad
] = op
;
12256 op_riprel
[op_ad
] = riprel
;
12260 /* Mask to get a 32-bit address. */
12261 op_address
[op_ad
] = op
& 0xffffffff;
12262 op_riprel
[op_ad
] = riprel
& 0xffffffff;
12267 OP_REG (int code
, int sizeflag
)
12274 case es_reg
: case ss_reg
: case cs_reg
:
12275 case ds_reg
: case fs_reg
: case gs_reg
:
12276 oappend (names_seg
[code
- es_reg
]);
12288 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
12289 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
12290 s
= names16
[code
- ax_reg
+ add
];
12292 case ah_reg
: case ch_reg
: case dh_reg
: case bh_reg
:
12294 /* Fall through. */
12295 case al_reg
: case cl_reg
: case dl_reg
: case bl_reg
:
12297 s
= names8rex
[code
- al_reg
+ add
];
12299 s
= names8
[code
- al_reg
];
12301 case rAX_reg
: case rCX_reg
: case rDX_reg
: case rBX_reg
:
12302 case rSP_reg
: case rBP_reg
: case rSI_reg
: case rDI_reg
:
12303 if (address_mode
== mode_64bit
12304 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
12306 s
= names64
[code
- rAX_reg
+ add
];
12309 code
+= eAX_reg
- rAX_reg
;
12310 /* Fall through. */
12311 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
12312 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
12315 s
= names64
[code
- eAX_reg
+ add
];
12318 if (sizeflag
& DFLAG
)
12319 s
= names32
[code
- eAX_reg
+ add
];
12321 s
= names16
[code
- eAX_reg
+ add
];
12322 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12326 s
= INTERNAL_DISASSEMBLER_ERROR
;
12333 OP_IMREG (int code
, int sizeflag
)
12345 case al_reg
: case cl_reg
:
12346 s
= names8
[code
- al_reg
];
12355 /* Fall through. */
12356 case z_mode_ax_reg
:
12357 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
12361 if (!(rex
& REX_W
))
12362 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12365 s
= INTERNAL_DISASSEMBLER_ERROR
;
12372 OP_I (int bytemode
, int sizeflag
)
12375 bfd_signed_vma mask
= -1;
12380 FETCH_DATA (the_info
, codep
+ 1);
12390 if (sizeflag
& DFLAG
)
12400 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12416 oappend (INTERNAL_DISASSEMBLER_ERROR
);
12421 scratchbuf
[0] = '$';
12422 print_operand_value (scratchbuf
+ 1, 1, op
);
12423 oappend_maybe_intel (scratchbuf
);
12424 scratchbuf
[0] = '\0';
12428 OP_I64 (int bytemode
, int sizeflag
)
12430 if (bytemode
!= v_mode
|| address_mode
!= mode_64bit
|| !(rex
& REX_W
))
12432 OP_I (bytemode
, sizeflag
);
12438 scratchbuf
[0] = '$';
12439 print_operand_value (scratchbuf
+ 1, 1, get64 ());
12440 oappend_maybe_intel (scratchbuf
);
12441 scratchbuf
[0] = '\0';
12445 OP_sI (int bytemode
, int sizeflag
)
12453 FETCH_DATA (the_info
, codep
+ 1);
12455 if ((op
& 0x80) != 0)
12457 if (bytemode
== b_T_mode
)
12459 if (address_mode
!= mode_64bit
12460 || !((sizeflag
& DFLAG
) || (rex
& REX_W
)))
12462 /* The operand-size prefix is overridden by a REX prefix. */
12463 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
12471 if (!(rex
& REX_W
))
12473 if (sizeflag
& DFLAG
)
12481 /* The operand-size prefix is overridden by a REX prefix. */
12482 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
12488 oappend (INTERNAL_DISASSEMBLER_ERROR
);
12492 scratchbuf
[0] = '$';
12493 print_operand_value (scratchbuf
+ 1, 1, op
);
12494 oappend_maybe_intel (scratchbuf
);
12498 OP_J (int bytemode
, int sizeflag
)
12502 bfd_vma segment
= 0;
12507 FETCH_DATA (the_info
, codep
+ 1);
12509 if ((disp
& 0x80) != 0)
12514 if ((sizeflag
& DFLAG
)
12515 || (address_mode
== mode_64bit
12516 && ((isa64
== intel64
&& bytemode
!= dqw_mode
)
12517 || (rex
& REX_W
))))
12522 if ((disp
& 0x8000) != 0)
12524 /* In 16bit mode, address is wrapped around at 64k within
12525 the same segment. Otherwise, a data16 prefix on a jump
12526 instruction means that the pc is masked to 16 bits after
12527 the displacement is added! */
12529 if ((prefixes
& PREFIX_DATA
) == 0)
12530 segment
= ((start_pc
+ (codep
- start_codep
))
12531 & ~((bfd_vma
) 0xffff));
12533 if (address_mode
!= mode_64bit
12534 || (isa64
!= intel64
&& !(rex
& REX_W
)))
12535 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12538 oappend (INTERNAL_DISASSEMBLER_ERROR
);
12541 disp
= ((start_pc
+ (codep
- start_codep
) + disp
) & mask
) | segment
;
12543 print_operand_value (scratchbuf
, 1, disp
);
12544 oappend (scratchbuf
);
12548 OP_SEG (int bytemode
, int sizeflag
)
12550 if (bytemode
== w_mode
)
12551 oappend (names_seg
[modrm
.reg
]);
12553 OP_E (modrm
.mod
== 3 ? bytemode
: w_mode
, sizeflag
);
12557 OP_DIR (int dummy ATTRIBUTE_UNUSED
, int sizeflag
)
12561 if (sizeflag
& DFLAG
)
12571 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12573 sprintf (scratchbuf
, "0x%x:0x%x", seg
, offset
);
12575 sprintf (scratchbuf
, "$0x%x,$0x%x", seg
, offset
);
12576 oappend (scratchbuf
);
12580 OP_OFF (int bytemode
, int sizeflag
)
12584 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
12585 intel_operand_size (bytemode
, sizeflag
);
12588 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
12595 if (!active_seg_prefix
)
12597 oappend (names_seg
[ds_reg
- es_reg
]);
12601 print_operand_value (scratchbuf
, 1, off
);
12602 oappend (scratchbuf
);
12606 OP_OFF64 (int bytemode
, int sizeflag
)
12610 if (address_mode
!= mode_64bit
12611 || (prefixes
& PREFIX_ADDR
))
12613 OP_OFF (bytemode
, sizeflag
);
12617 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
12618 intel_operand_size (bytemode
, sizeflag
);
12625 if (!active_seg_prefix
)
12627 oappend (names_seg
[ds_reg
- es_reg
]);
12631 print_operand_value (scratchbuf
, 1, off
);
12632 oappend (scratchbuf
);
12636 ptr_reg (int code
, int sizeflag
)
12640 *obufp
++ = open_char
;
12641 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
12642 if (address_mode
== mode_64bit
)
12644 if (!(sizeflag
& AFLAG
))
12645 s
= names32
[code
- eAX_reg
];
12647 s
= names64
[code
- eAX_reg
];
12649 else if (sizeflag
& AFLAG
)
12650 s
= names32
[code
- eAX_reg
];
12652 s
= names16
[code
- eAX_reg
];
12654 *obufp
++ = close_char
;
12659 OP_ESreg (int code
, int sizeflag
)
12665 case 0x6d: /* insw/insl */
12666 intel_operand_size (z_mode
, sizeflag
);
12668 case 0xa5: /* movsw/movsl/movsq */
12669 case 0xa7: /* cmpsw/cmpsl/cmpsq */
12670 case 0xab: /* stosw/stosl */
12671 case 0xaf: /* scasw/scasl */
12672 intel_operand_size (v_mode
, sizeflag
);
12675 intel_operand_size (b_mode
, sizeflag
);
12678 oappend_maybe_intel ("%es:");
12679 ptr_reg (code
, sizeflag
);
12683 OP_DSreg (int code
, int sizeflag
)
12689 case 0x6f: /* outsw/outsl */
12690 intel_operand_size (z_mode
, sizeflag
);
12692 case 0xa5: /* movsw/movsl/movsq */
12693 case 0xa7: /* cmpsw/cmpsl/cmpsq */
12694 case 0xad: /* lodsw/lodsl/lodsq */
12695 intel_operand_size (v_mode
, sizeflag
);
12698 intel_operand_size (b_mode
, sizeflag
);
12701 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
12702 default segment register DS is printed. */
12703 if (!active_seg_prefix
)
12704 active_seg_prefix
= PREFIX_DS
;
12706 ptr_reg (code
, sizeflag
);
12710 OP_C (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12718 else if (address_mode
!= mode_64bit
&& (prefixes
& PREFIX_LOCK
))
12720 all_prefixes
[last_lock_prefix
] = 0;
12721 used_prefixes
|= PREFIX_LOCK
;
12726 sprintf (scratchbuf
, "%%cr%d", modrm
.reg
+ add
);
12727 oappend_maybe_intel (scratchbuf
);
12731 OP_D (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12740 sprintf (scratchbuf
, "dr%d", modrm
.reg
+ add
);
12742 sprintf (scratchbuf
, "%%db%d", modrm
.reg
+ add
);
12743 oappend (scratchbuf
);
12747 OP_T (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12749 sprintf (scratchbuf
, "%%tr%d", modrm
.reg
);
12750 oappend_maybe_intel (scratchbuf
);
12754 OP_MMX (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12756 int reg
= modrm
.reg
;
12757 const char **names
;
12759 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12760 if (prefixes
& PREFIX_DATA
)
12769 oappend (names
[reg
]);
12773 OP_XMM (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
12775 int reg
= modrm
.reg
;
12776 const char **names
;
12788 && bytemode
!= xmm_mode
12789 && bytemode
!= xmmq_mode
12790 && bytemode
!= evex_half_bcst_xmmq_mode
12791 && bytemode
!= ymm_mode
12792 && bytemode
!= tmm_mode
12793 && bytemode
!= scalar_mode
)
12795 switch (vex
.length
)
12802 || (bytemode
!= vex_vsib_q_w_dq_mode
12803 && bytemode
!= vex_vsib_q_w_d_mode
))
12815 else if (bytemode
== xmmq_mode
12816 || bytemode
== evex_half_bcst_xmmq_mode
)
12818 switch (vex
.length
)
12831 else if (bytemode
== tmm_mode
)
12841 else if (bytemode
== ymm_mode
)
12845 oappend (names
[reg
]);
12849 OP_EM (int bytemode
, int sizeflag
)
12852 const char **names
;
12854 if (modrm
.mod
!= 3)
12857 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
12859 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
12860 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12862 OP_E (bytemode
, sizeflag
);
12866 if ((sizeflag
& SUFFIX_ALWAYS
) && bytemode
== v_swap_mode
)
12869 /* Skip mod/rm byte. */
12872 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12874 if (prefixes
& PREFIX_DATA
)
12883 oappend (names
[reg
]);
12886 /* cvt* are the only instructions in sse2 which have
12887 both SSE and MMX operands and also have 0x66 prefix
12888 in their opcode. 0x66 was originally used to differentiate
12889 between SSE and MMX instruction(operands). So we have to handle the
12890 cvt* separately using OP_EMC and OP_MXC */
12892 OP_EMC (int bytemode
, int sizeflag
)
12894 if (modrm
.mod
!= 3)
12896 if (intel_syntax
&& bytemode
== v_mode
)
12898 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
12899 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12901 OP_E (bytemode
, sizeflag
);
12905 /* Skip mod/rm byte. */
12908 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12909 oappend (names_mm
[modrm
.rm
]);
12913 OP_MXC (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12915 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12916 oappend (names_mm
[modrm
.reg
]);
12920 OP_EX (int bytemode
, int sizeflag
)
12923 const char **names
;
12925 /* Skip mod/rm byte. */
12929 if (modrm
.mod
!= 3)
12931 OP_E_memory (bytemode
, sizeflag
);
12946 if ((sizeflag
& SUFFIX_ALWAYS
)
12947 && (bytemode
== x_swap_mode
12948 || bytemode
== d_swap_mode
12949 || bytemode
== q_swap_mode
))
12953 && bytemode
!= xmm_mode
12954 && bytemode
!= xmmdw_mode
12955 && bytemode
!= xmmqd_mode
12956 && bytemode
!= xmm_mb_mode
12957 && bytemode
!= xmm_mw_mode
12958 && bytemode
!= xmm_md_mode
12959 && bytemode
!= xmm_mq_mode
12960 && bytemode
!= xmmq_mode
12961 && bytemode
!= evex_half_bcst_xmmq_mode
12962 && bytemode
!= ymm_mode
12963 && bytemode
!= tmm_mode
12964 && bytemode
!= vex_scalar_w_dq_mode
)
12966 switch (vex
.length
)
12981 else if (bytemode
== xmmq_mode
12982 || bytemode
== evex_half_bcst_xmmq_mode
)
12984 switch (vex
.length
)
12997 else if (bytemode
== tmm_mode
)
13007 else if (bytemode
== ymm_mode
)
13011 oappend (names
[reg
]);
13015 OP_MS (int bytemode
, int sizeflag
)
13017 if (modrm
.mod
== 3)
13018 OP_EM (bytemode
, sizeflag
);
13024 OP_XS (int bytemode
, int sizeflag
)
13026 if (modrm
.mod
== 3)
13027 OP_EX (bytemode
, sizeflag
);
13033 OP_M (int bytemode
, int sizeflag
)
13035 if (modrm
.mod
== 3)
13036 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
13039 OP_E (bytemode
, sizeflag
);
13043 OP_0f07 (int bytemode
, int sizeflag
)
13045 if (modrm
.mod
!= 3 || modrm
.rm
!= 0)
13048 OP_E (bytemode
, sizeflag
);
13051 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
13052 32bit mode and "xchg %rax,%rax" in 64bit mode. */
13055 NOP_Fixup1 (int bytemode
, int sizeflag
)
13057 if ((prefixes
& PREFIX_DATA
) != 0
13060 && address_mode
== mode_64bit
))
13061 OP_REG (bytemode
, sizeflag
);
13063 strcpy (obuf
, "nop");
13067 NOP_Fixup2 (int bytemode
, int sizeflag
)
13069 if ((prefixes
& PREFIX_DATA
) != 0
13072 && address_mode
== mode_64bit
))
13073 OP_IMREG (bytemode
, sizeflag
);
13076 static const char *const Suffix3DNow
[] = {
13077 /* 00 */ NULL
, NULL
, NULL
, NULL
,
13078 /* 04 */ NULL
, NULL
, NULL
, NULL
,
13079 /* 08 */ NULL
, NULL
, NULL
, NULL
,
13080 /* 0C */ "pi2fw", "pi2fd", NULL
, NULL
,
13081 /* 10 */ NULL
, NULL
, NULL
, NULL
,
13082 /* 14 */ NULL
, NULL
, NULL
, NULL
,
13083 /* 18 */ NULL
, NULL
, NULL
, NULL
,
13084 /* 1C */ "pf2iw", "pf2id", NULL
, NULL
,
13085 /* 20 */ NULL
, NULL
, NULL
, NULL
,
13086 /* 24 */ NULL
, NULL
, NULL
, NULL
,
13087 /* 28 */ NULL
, NULL
, NULL
, NULL
,
13088 /* 2C */ NULL
, NULL
, NULL
, NULL
,
13089 /* 30 */ NULL
, NULL
, NULL
, NULL
,
13090 /* 34 */ NULL
, NULL
, NULL
, NULL
,
13091 /* 38 */ NULL
, NULL
, NULL
, NULL
,
13092 /* 3C */ NULL
, NULL
, NULL
, NULL
,
13093 /* 40 */ NULL
, NULL
, NULL
, NULL
,
13094 /* 44 */ NULL
, NULL
, NULL
, NULL
,
13095 /* 48 */ NULL
, NULL
, NULL
, NULL
,
13096 /* 4C */ NULL
, NULL
, NULL
, NULL
,
13097 /* 50 */ NULL
, NULL
, NULL
, NULL
,
13098 /* 54 */ NULL
, NULL
, NULL
, NULL
,
13099 /* 58 */ NULL
, NULL
, NULL
, NULL
,
13100 /* 5C */ NULL
, NULL
, NULL
, NULL
,
13101 /* 60 */ NULL
, NULL
, NULL
, NULL
,
13102 /* 64 */ NULL
, NULL
, NULL
, NULL
,
13103 /* 68 */ NULL
, NULL
, NULL
, NULL
,
13104 /* 6C */ NULL
, NULL
, NULL
, NULL
,
13105 /* 70 */ NULL
, NULL
, NULL
, NULL
,
13106 /* 74 */ NULL
, NULL
, NULL
, NULL
,
13107 /* 78 */ NULL
, NULL
, NULL
, NULL
,
13108 /* 7C */ NULL
, NULL
, NULL
, NULL
,
13109 /* 80 */ NULL
, NULL
, NULL
, NULL
,
13110 /* 84 */ NULL
, NULL
, NULL
, NULL
,
13111 /* 88 */ NULL
, NULL
, "pfnacc", NULL
,
13112 /* 8C */ NULL
, NULL
, "pfpnacc", NULL
,
13113 /* 90 */ "pfcmpge", NULL
, NULL
, NULL
,
13114 /* 94 */ "pfmin", NULL
, "pfrcp", "pfrsqrt",
13115 /* 98 */ NULL
, NULL
, "pfsub", NULL
,
13116 /* 9C */ NULL
, NULL
, "pfadd", NULL
,
13117 /* A0 */ "pfcmpgt", NULL
, NULL
, NULL
,
13118 /* A4 */ "pfmax", NULL
, "pfrcpit1", "pfrsqit1",
13119 /* A8 */ NULL
, NULL
, "pfsubr", NULL
,
13120 /* AC */ NULL
, NULL
, "pfacc", NULL
,
13121 /* B0 */ "pfcmpeq", NULL
, NULL
, NULL
,
13122 /* B4 */ "pfmul", NULL
, "pfrcpit2", "pmulhrw",
13123 /* B8 */ NULL
, NULL
, NULL
, "pswapd",
13124 /* BC */ NULL
, NULL
, NULL
, "pavgusb",
13125 /* C0 */ NULL
, NULL
, NULL
, NULL
,
13126 /* C4 */ NULL
, NULL
, NULL
, NULL
,
13127 /* C8 */ NULL
, NULL
, NULL
, NULL
,
13128 /* CC */ NULL
, NULL
, NULL
, NULL
,
13129 /* D0 */ NULL
, NULL
, NULL
, NULL
,
13130 /* D4 */ NULL
, NULL
, NULL
, NULL
,
13131 /* D8 */ NULL
, NULL
, NULL
, NULL
,
13132 /* DC */ NULL
, NULL
, NULL
, NULL
,
13133 /* E0 */ NULL
, NULL
, NULL
, NULL
,
13134 /* E4 */ NULL
, NULL
, NULL
, NULL
,
13135 /* E8 */ NULL
, NULL
, NULL
, NULL
,
13136 /* EC */ NULL
, NULL
, NULL
, NULL
,
13137 /* F0 */ NULL
, NULL
, NULL
, NULL
,
13138 /* F4 */ NULL
, NULL
, NULL
, NULL
,
13139 /* F8 */ NULL
, NULL
, NULL
, NULL
,
13140 /* FC */ NULL
, NULL
, NULL
, NULL
,
13144 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13146 const char *mnemonic
;
13148 FETCH_DATA (the_info
, codep
+ 1);
13149 /* AMD 3DNow! instructions are specified by an opcode suffix in the
13150 place where an 8-bit immediate would normally go. ie. the last
13151 byte of the instruction. */
13152 obufp
= mnemonicendp
;
13153 mnemonic
= Suffix3DNow
[*codep
++ & 0xff];
13155 oappend (mnemonic
);
13158 /* Since a variable sized modrm/sib chunk is between the start
13159 of the opcode (0x0f0f) and the opcode suffix, we need to do
13160 all the modrm processing first, and don't know until now that
13161 we have a bad opcode. This necessitates some cleaning up. */
13162 op_out
[0][0] = '\0';
13163 op_out
[1][0] = '\0';
13166 mnemonicendp
= obufp
;
13169 static const struct op simd_cmp_op
[] =
13171 { STRING_COMMA_LEN ("eq") },
13172 { STRING_COMMA_LEN ("lt") },
13173 { STRING_COMMA_LEN ("le") },
13174 { STRING_COMMA_LEN ("unord") },
13175 { STRING_COMMA_LEN ("neq") },
13176 { STRING_COMMA_LEN ("nlt") },
13177 { STRING_COMMA_LEN ("nle") },
13178 { STRING_COMMA_LEN ("ord") }
13181 static const struct op vex_cmp_op
[] =
13183 { STRING_COMMA_LEN ("eq_uq") },
13184 { STRING_COMMA_LEN ("nge") },
13185 { STRING_COMMA_LEN ("ngt") },
13186 { STRING_COMMA_LEN ("false") },
13187 { STRING_COMMA_LEN ("neq_oq") },
13188 { STRING_COMMA_LEN ("ge") },
13189 { STRING_COMMA_LEN ("gt") },
13190 { STRING_COMMA_LEN ("true") },
13191 { STRING_COMMA_LEN ("eq_os") },
13192 { STRING_COMMA_LEN ("lt_oq") },
13193 { STRING_COMMA_LEN ("le_oq") },
13194 { STRING_COMMA_LEN ("unord_s") },
13195 { STRING_COMMA_LEN ("neq_us") },
13196 { STRING_COMMA_LEN ("nlt_uq") },
13197 { STRING_COMMA_LEN ("nle_uq") },
13198 { STRING_COMMA_LEN ("ord_s") },
13199 { STRING_COMMA_LEN ("eq_us") },
13200 { STRING_COMMA_LEN ("nge_uq") },
13201 { STRING_COMMA_LEN ("ngt_uq") },
13202 { STRING_COMMA_LEN ("false_os") },
13203 { STRING_COMMA_LEN ("neq_os") },
13204 { STRING_COMMA_LEN ("ge_oq") },
13205 { STRING_COMMA_LEN ("gt_oq") },
13206 { STRING_COMMA_LEN ("true_us") },
13210 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13212 unsigned int cmp_type
;
13214 FETCH_DATA (the_info
, codep
+ 1);
13215 cmp_type
= *codep
++ & 0xff;
13216 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
))
13219 char *p
= mnemonicendp
- 2;
13223 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
13224 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
13227 && cmp_type
< ARRAY_SIZE (simd_cmp_op
) + ARRAY_SIZE (vex_cmp_op
))
13230 char *p
= mnemonicendp
- 2;
13234 cmp_type
-= ARRAY_SIZE (simd_cmp_op
);
13235 sprintf (p
, "%s%s", vex_cmp_op
[cmp_type
].name
, suffix
);
13236 mnemonicendp
+= vex_cmp_op
[cmp_type
].len
;
13240 /* We have a reserved extension byte. Output it directly. */
13241 scratchbuf
[0] = '$';
13242 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
13243 oappend_maybe_intel (scratchbuf
);
13244 scratchbuf
[0] = '\0';
13249 OP_Mwait (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
13251 /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx */
13254 strcpy (op_out
[0], names32
[0]);
13255 strcpy (op_out
[1], names32
[1]);
13256 if (bytemode
== eBX_reg
)
13257 strcpy (op_out
[2], names32
[3]);
13258 two_source_ops
= 1;
13260 /* Skip mod/rm byte. */
13266 OP_Monitor (int bytemode ATTRIBUTE_UNUSED
,
13267 int sizeflag ATTRIBUTE_UNUSED
)
13269 /* monitor %{e,r,}ax,%ecx,%edx" */
13272 const char **names
= (address_mode
== mode_64bit
13273 ? names64
: names32
);
13275 if (prefixes
& PREFIX_ADDR
)
13277 /* Remove "addr16/addr32". */
13278 all_prefixes
[last_addr_prefix
] = 0;
13279 names
= (address_mode
!= mode_32bit
13280 ? names32
: names16
);
13281 used_prefixes
|= PREFIX_ADDR
;
13283 else if (address_mode
== mode_16bit
)
13285 strcpy (op_out
[0], names
[0]);
13286 strcpy (op_out
[1], names32
[1]);
13287 strcpy (op_out
[2], names32
[2]);
13288 two_source_ops
= 1;
13290 /* Skip mod/rm byte. */
13298 /* Throw away prefixes and 1st. opcode byte. */
13299 codep
= insn_codep
+ 1;
13304 REP_Fixup (int bytemode
, int sizeflag
)
13306 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
13308 if (prefixes
& PREFIX_REPZ
)
13309 all_prefixes
[last_repz_prefix
] = REP_PREFIX
;
13316 OP_IMREG (bytemode
, sizeflag
);
13319 OP_ESreg (bytemode
, sizeflag
);
13322 OP_DSreg (bytemode
, sizeflag
);
13331 SEP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13333 if ( isa64
!= amd64
)
13338 mnemonicendp
= obufp
;
13342 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
13346 BND_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13348 if (prefixes
& PREFIX_REPNZ
)
13349 all_prefixes
[last_repnz_prefix
] = BND_PREFIX
;
13352 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
13356 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED
,
13357 int sizeflag ATTRIBUTE_UNUSED
)
13359 if (active_seg_prefix
== PREFIX_DS
13360 && (address_mode
!= mode_64bit
|| last_data_prefix
< 0))
13362 /* NOTRACK prefix is only valid on indirect branch instructions.
13363 NB: DATA prefix is unsupported for Intel64. */
13364 active_seg_prefix
= 0;
13365 all_prefixes
[last_seg_prefix
] = NOTRACK_PREFIX
;
13369 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
13370 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
13374 HLE_Fixup1 (int bytemode
, int sizeflag
)
13377 && (prefixes
& PREFIX_LOCK
) != 0)
13379 if (prefixes
& PREFIX_REPZ
)
13380 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
13381 if (prefixes
& PREFIX_REPNZ
)
13382 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
13385 OP_E (bytemode
, sizeflag
);
13388 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
13389 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
13393 HLE_Fixup2 (int bytemode
, int sizeflag
)
13395 if (modrm
.mod
!= 3)
13397 if (prefixes
& PREFIX_REPZ
)
13398 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
13399 if (prefixes
& PREFIX_REPNZ
)
13400 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
13403 OP_E (bytemode
, sizeflag
);
13406 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
13407 "xrelease" for memory operand. No check for LOCK prefix. */
13410 HLE_Fixup3 (int bytemode
, int sizeflag
)
13413 && last_repz_prefix
> last_repnz_prefix
13414 && (prefixes
& PREFIX_REPZ
) != 0)
13415 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
13417 OP_E (bytemode
, sizeflag
);
13421 CMPXCHG8B_Fixup (int bytemode
, int sizeflag
)
13426 /* Change cmpxchg8b to cmpxchg16b. */
13427 char *p
= mnemonicendp
- 2;
13428 mnemonicendp
= stpcpy (p
, "16b");
13431 else if ((prefixes
& PREFIX_LOCK
) != 0)
13433 if (prefixes
& PREFIX_REPZ
)
13434 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
13435 if (prefixes
& PREFIX_REPNZ
)
13436 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
13439 OP_M (bytemode
, sizeflag
);
13443 XMM_Fixup (int reg
, int sizeflag ATTRIBUTE_UNUSED
)
13445 const char **names
;
13449 switch (vex
.length
)
13463 oappend (names
[reg
]);
13467 FXSAVE_Fixup (int bytemode
, int sizeflag
)
13469 /* Add proper suffix to "fxsave" and "fxrstor". */
13473 char *p
= mnemonicendp
;
13479 OP_M (bytemode
, sizeflag
);
13482 /* Display the destination register operand for instructions with
13486 OP_VEX (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
13489 const char **names
;
13494 reg
= vex
.register_specifier
;
13495 vex
.register_specifier
= 0;
13496 if (address_mode
!= mode_64bit
)
13498 else if (vex
.evex
&& !vex
.v
)
13501 if (bytemode
== vex_scalar_mode
)
13503 oappend (names_xmm
[reg
]);
13507 if (bytemode
== tmm_mode
)
13509 /* All 3 TMM registers must be distinct. */
13514 /* This must be the 3rd operand. */
13515 if (obufp
!= op_out
[2])
13517 oappend (names_tmm
[reg
]);
13518 if (reg
== modrm
.reg
|| reg
== modrm
.rm
)
13519 strcpy (obufp
, "/(bad)");
13522 if (modrm
.reg
== modrm
.rm
|| modrm
.reg
== reg
|| modrm
.rm
== reg
)
13525 && (modrm
.reg
== modrm
.rm
|| modrm
.reg
== reg
))
13526 strcat (op_out
[0], "/(bad)");
13528 && (modrm
.rm
== modrm
.reg
|| modrm
.rm
== reg
))
13529 strcat (op_out
[1], "/(bad)");
13535 switch (vex
.length
)
13541 case vex_vsib_q_w_dq_mode
:
13542 case vex_vsib_q_w_d_mode
:
13558 names
= names_mask
;
13571 case vex_vsib_q_w_dq_mode
:
13572 case vex_vsib_q_w_d_mode
:
13573 names
= vex
.w
? names_ymm
: names_xmm
;
13582 names
= names_mask
;
13585 /* See PR binutils/20893 for a reproducer. */
13597 oappend (names
[reg
]);
13601 OP_VexR (int bytemode
, int sizeflag
)
13603 if (modrm
.mod
== 3)
13604 OP_VEX (bytemode
, sizeflag
);
13608 OP_VexW (int bytemode
, int sizeflag
)
13610 OP_VEX (bytemode
, sizeflag
);
13614 /* Swap 2nd and 3rd operands. */
13615 strcpy (scratchbuf
, op_out
[2]);
13616 strcpy (op_out
[2], op_out
[1]);
13617 strcpy (op_out
[1], scratchbuf
);
13622 OP_REG_VexI4 (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
13625 const char **names
= names_xmm
;
13627 FETCH_DATA (the_info
, codep
+ 1);
13630 if (bytemode
!= x_mode
&& bytemode
!= scalar_mode
)
13634 if (address_mode
!= mode_64bit
)
13637 if (bytemode
== x_mode
&& vex
.length
== 256)
13640 oappend (names
[reg
]);
13644 /* Swap 3rd and 4th operands. */
13645 strcpy (scratchbuf
, op_out
[3]);
13646 strcpy (op_out
[3], op_out
[2]);
13647 strcpy (op_out
[2], scratchbuf
);
13652 OP_VexI4 (int bytemode ATTRIBUTE_UNUSED
,
13653 int sizeflag ATTRIBUTE_UNUSED
)
13655 scratchbuf
[0] = '$';
13656 print_operand_value (scratchbuf
+ 1, 1, codep
[-1] & 0xf);
13657 oappend_maybe_intel (scratchbuf
);
13661 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
,
13662 int sizeflag ATTRIBUTE_UNUSED
)
13664 unsigned int cmp_type
;
13669 FETCH_DATA (the_info
, codep
+ 1);
13670 cmp_type
= *codep
++ & 0xff;
13671 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
13672 If it's the case, print suffix, otherwise - print the immediate. */
13673 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
)
13678 char *p
= mnemonicendp
- 2;
13680 /* vpcmp* can have both one- and two-lettered suffix. */
13694 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
13695 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
13699 /* We have a reserved extension byte. Output it directly. */
13700 scratchbuf
[0] = '$';
13701 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
13702 oappend_maybe_intel (scratchbuf
);
13703 scratchbuf
[0] = '\0';
13707 static const struct op xop_cmp_op
[] =
13709 { STRING_COMMA_LEN ("lt") },
13710 { STRING_COMMA_LEN ("le") },
13711 { STRING_COMMA_LEN ("gt") },
13712 { STRING_COMMA_LEN ("ge") },
13713 { STRING_COMMA_LEN ("eq") },
13714 { STRING_COMMA_LEN ("neq") },
13715 { STRING_COMMA_LEN ("false") },
13716 { STRING_COMMA_LEN ("true") }
13720 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED
,
13721 int sizeflag ATTRIBUTE_UNUSED
)
13723 unsigned int cmp_type
;
13725 FETCH_DATA (the_info
, codep
+ 1);
13726 cmp_type
= *codep
++ & 0xff;
13727 if (cmp_type
< ARRAY_SIZE (xop_cmp_op
))
13730 char *p
= mnemonicendp
- 2;
13732 /* vpcom* can have both one- and two-lettered suffix. */
13746 sprintf (p
, "%s%s", xop_cmp_op
[cmp_type
].name
, suffix
);
13747 mnemonicendp
+= xop_cmp_op
[cmp_type
].len
;
13751 /* We have a reserved extension byte. Output it directly. */
13752 scratchbuf
[0] = '$';
13753 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
13754 oappend_maybe_intel (scratchbuf
);
13755 scratchbuf
[0] = '\0';
13759 static const struct op pclmul_op
[] =
13761 { STRING_COMMA_LEN ("lql") },
13762 { STRING_COMMA_LEN ("hql") },
13763 { STRING_COMMA_LEN ("lqh") },
13764 { STRING_COMMA_LEN ("hqh") }
13768 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED
,
13769 int sizeflag ATTRIBUTE_UNUSED
)
13771 unsigned int pclmul_type
;
13773 FETCH_DATA (the_info
, codep
+ 1);
13774 pclmul_type
= *codep
++ & 0xff;
13775 switch (pclmul_type
)
13786 if (pclmul_type
< ARRAY_SIZE (pclmul_op
))
13789 char *p
= mnemonicendp
- 3;
13794 sprintf (p
, "%s%s", pclmul_op
[pclmul_type
].name
, suffix
);
13795 mnemonicendp
+= pclmul_op
[pclmul_type
].len
;
13799 /* We have a reserved extension byte. Output it directly. */
13800 scratchbuf
[0] = '$';
13801 print_operand_value (scratchbuf
+ 1, 1, pclmul_type
);
13802 oappend_maybe_intel (scratchbuf
);
13803 scratchbuf
[0] = '\0';
13808 MOVSXD_Fixup (int bytemode
, int sizeflag
)
13810 /* Add proper suffix to "movsxd". */
13811 char *p
= mnemonicendp
;
13836 oappend (INTERNAL_DISASSEMBLER_ERROR
);
13843 OP_E (bytemode
, sizeflag
);
13847 OP_Mask (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
13850 || (bytemode
!= mask_mode
&& bytemode
!= mask_bd_mode
))
13854 if ((rex
& REX_R
) != 0 || !vex
.r
)
13860 oappend (names_mask
[modrm
.reg
]);
13864 OP_Rounding (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
13866 if (modrm
.mod
== 3 && vex
.b
)
13869 case evex_rounding_64_mode
:
13870 if (address_mode
!= mode_64bit
)
13875 /* Fall through. */
13876 case evex_rounding_mode
:
13877 oappend (names_rounding
[vex
.ll
]);
13879 case evex_sae_mode
: