1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
6 This file is part of the GNU opcodes library.
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
24 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
26 modified by John Hassey (hassey@dg-rtp.dg.com)
27 x86-64 support added by Jan Hubicka (jh@suse.cz)
28 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
30 /* The main tables describing the instructions is essentially a copy
31 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
32 Programmers Manual. Usually, there is a capital letter, followed
33 by a small letter. The capital letter tell the addressing mode,
34 and the small letter tells about the operand size. Refer to
35 the Intel manual for details. */
40 #include "opcode/i386.h"
41 #include "libiberty.h"
45 static int print_insn (bfd_vma
, disassemble_info
*);
46 static void dofloat (int);
47 static void OP_ST (int, int);
48 static void OP_STi (int, int);
49 static int putop (const char *, int);
50 static void oappend (const char *);
51 static void append_seg (void);
52 static void OP_indirE (int, int);
53 static void print_operand_value (char *, int, bfd_vma
);
54 static void OP_E_register (int, int);
55 static void OP_E_memory (int, int);
56 static void print_displacement (char *, bfd_vma
);
57 static void OP_E (int, int);
58 static void OP_G (int, int);
59 static bfd_vma
get64 (void);
60 static bfd_signed_vma
get32 (void);
61 static bfd_signed_vma
get32s (void);
62 static int get16 (void);
63 static void set_op (bfd_vma
, int);
64 static void OP_Skip_MODRM (int, int);
65 static void OP_REG (int, int);
66 static void OP_IMREG (int, int);
67 static void OP_I (int, int);
68 static void OP_I64 (int, int);
69 static void OP_sI (int, int);
70 static void OP_J (int, int);
71 static void OP_SEG (int, int);
72 static void OP_DIR (int, int);
73 static void OP_OFF (int, int);
74 static void OP_OFF64 (int, int);
75 static void ptr_reg (int, int);
76 static void OP_ESreg (int, int);
77 static void OP_DSreg (int, int);
78 static void OP_C (int, int);
79 static void OP_D (int, int);
80 static void OP_T (int, int);
81 static void OP_R (int, int);
82 static void OP_MMX (int, int);
83 static void OP_XMM (int, int);
84 static void OP_EM (int, int);
85 static void OP_EX (int, int);
86 static void OP_EMC (int,int);
87 static void OP_MXC (int,int);
88 static void OP_MS (int, int);
89 static void OP_XS (int, int);
90 static void OP_M (int, int);
91 static void OP_VEX (int, int);
92 static void OP_EX_Vex (int, int);
93 static void OP_EX_VexW (int, int);
94 static void OP_EX_VexImmW (int, int);
95 static void OP_XMM_Vex (int, int);
96 static void OP_XMM_VexW (int, int);
97 static void OP_REG_VexI4 (int, int);
98 static void PCLMUL_Fixup (int, int);
99 static void VEXI4_Fixup (int, int);
100 static void VZERO_Fixup (int, int);
101 static void VCMP_Fixup (int, int);
102 static void OP_0f07 (int, int);
103 static void OP_Monitor (int, int);
104 static void OP_Mwait (int, int);
105 static void NOP_Fixup1 (int, int);
106 static void NOP_Fixup2 (int, int);
107 static void OP_3DNowSuffix (int, int);
108 static void CMP_Fixup (int, int);
109 static void BadOp (void);
110 static void REP_Fixup (int, int);
111 static void CMPXCHG8B_Fixup (int, int);
112 static void XMM_Fixup (int, int);
113 static void CRC32_Fixup (int, int);
114 static void FXSAVE_Fixup (int, int);
115 static void OP_LWPCB_E (int, int);
116 static void OP_LWP_E (int, int);
117 static void OP_Vex_2src_1 (int, int);
118 static void OP_Vex_2src_2 (int, int);
120 static void MOVBE_Fixup (int, int);
123 /* Points to first byte not fetched. */
124 bfd_byte
*max_fetched
;
125 bfd_byte the_buffer
[MAX_MNEM_SIZE
];
138 enum address_mode address_mode
;
140 /* Flags for the prefixes for the current instruction. See below. */
143 /* REX prefix the current instruction. See below. */
145 /* Bits of REX we've already used. */
147 /* REX bits in original REX prefix ignored. */
148 static int rex_ignored
;
149 /* Mark parts used in the REX prefix. When we are testing for
150 empty prefix (for 8bit register REX extension), just mask it
151 out. Otherwise test for REX bit is excuse for existence of REX
152 only in case value is nonzero. */
153 #define USED_REX(value) \
158 rex_used |= (value) | REX_OPCODE; \
161 rex_used |= REX_OPCODE; \
164 /* Flags for prefixes which we somehow handled when printing the
165 current instruction. */
166 static int used_prefixes
;
168 /* Flags stored in PREFIXES. */
169 #define PREFIX_REPZ 1
170 #define PREFIX_REPNZ 2
171 #define PREFIX_LOCK 4
173 #define PREFIX_SS 0x10
174 #define PREFIX_DS 0x20
175 #define PREFIX_ES 0x40
176 #define PREFIX_FS 0x80
177 #define PREFIX_GS 0x100
178 #define PREFIX_DATA 0x200
179 #define PREFIX_ADDR 0x400
180 #define PREFIX_FWAIT 0x800
182 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
183 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
185 #define FETCH_DATA(info, addr) \
186 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
187 ? 1 : fetch_data ((info), (addr)))
190 fetch_data (struct disassemble_info
*info
, bfd_byte
*addr
)
193 struct dis_private
*priv
= (struct dis_private
*) info
->private_data
;
194 bfd_vma start
= priv
->insn_start
+ (priv
->max_fetched
- priv
->the_buffer
);
196 if (addr
<= priv
->the_buffer
+ MAX_MNEM_SIZE
)
197 status
= (*info
->read_memory_func
) (start
,
199 addr
- priv
->max_fetched
,
205 /* If we did manage to read at least one byte, then
206 print_insn_i386 will do something sensible. Otherwise, print
207 an error. We do that here because this is where we know
209 if (priv
->max_fetched
== priv
->the_buffer
)
210 (*info
->memory_error_func
) (status
, start
, info
);
211 longjmp (priv
->bailout
, 1);
214 priv
->max_fetched
= addr
;
218 #define XX { NULL, 0 }
219 #define Bad_Opcode NULL, { { NULL, 0 } }
221 #define Eb { OP_E, b_mode }
222 #define EbS { OP_E, b_swap_mode }
223 #define Ev { OP_E, v_mode }
224 #define EvS { OP_E, v_swap_mode }
225 #define Ed { OP_E, d_mode }
226 #define Edq { OP_E, dq_mode }
227 #define Edqw { OP_E, dqw_mode }
228 #define Edqb { OP_E, dqb_mode }
229 #define Edqd { OP_E, dqd_mode }
230 #define Eq { OP_E, q_mode }
231 #define indirEv { OP_indirE, stack_v_mode }
232 #define indirEp { OP_indirE, f_mode }
233 #define stackEv { OP_E, stack_v_mode }
234 #define Em { OP_E, m_mode }
235 #define Ew { OP_E, w_mode }
236 #define M { OP_M, 0 } /* lea, lgdt, etc. */
237 #define Ma { OP_M, a_mode }
238 #define Mb { OP_M, b_mode }
239 #define Md { OP_M, d_mode }
240 #define Mo { OP_M, o_mode }
241 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
242 #define Mq { OP_M, q_mode }
243 #define Mx { OP_M, x_mode }
244 #define Mxmm { OP_M, xmm_mode }
245 #define Gb { OP_G, b_mode }
246 #define Gv { OP_G, v_mode }
247 #define Gd { OP_G, d_mode }
248 #define Gdq { OP_G, dq_mode }
249 #define Gm { OP_G, m_mode }
250 #define Gw { OP_G, w_mode }
251 #define Rd { OP_R, d_mode }
252 #define Rm { OP_R, m_mode }
253 #define Ib { OP_I, b_mode }
254 #define sIb { OP_sI, b_mode } /* sign extened byte */
255 #define Iv { OP_I, v_mode }
256 #define sIv { OP_sI, v_mode }
257 #define Iq { OP_I, q_mode }
258 #define Iv64 { OP_I64, v_mode }
259 #define Iw { OP_I, w_mode }
260 #define I1 { OP_I, const_1_mode }
261 #define Jb { OP_J, b_mode }
262 #define Jv { OP_J, v_mode }
263 #define Cm { OP_C, m_mode }
264 #define Dm { OP_D, m_mode }
265 #define Td { OP_T, d_mode }
266 #define Skip_MODRM { OP_Skip_MODRM, 0 }
268 #define RMeAX { OP_REG, eAX_reg }
269 #define RMeBX { OP_REG, eBX_reg }
270 #define RMeCX { OP_REG, eCX_reg }
271 #define RMeDX { OP_REG, eDX_reg }
272 #define RMeSP { OP_REG, eSP_reg }
273 #define RMeBP { OP_REG, eBP_reg }
274 #define RMeSI { OP_REG, eSI_reg }
275 #define RMeDI { OP_REG, eDI_reg }
276 #define RMrAX { OP_REG, rAX_reg }
277 #define RMrBX { OP_REG, rBX_reg }
278 #define RMrCX { OP_REG, rCX_reg }
279 #define RMrDX { OP_REG, rDX_reg }
280 #define RMrSP { OP_REG, rSP_reg }
281 #define RMrBP { OP_REG, rBP_reg }
282 #define RMrSI { OP_REG, rSI_reg }
283 #define RMrDI { OP_REG, rDI_reg }
284 #define RMAL { OP_REG, al_reg }
285 #define RMAL { OP_REG, al_reg }
286 #define RMCL { OP_REG, cl_reg }
287 #define RMDL { OP_REG, dl_reg }
288 #define RMBL { OP_REG, bl_reg }
289 #define RMAH { OP_REG, ah_reg }
290 #define RMCH { OP_REG, ch_reg }
291 #define RMDH { OP_REG, dh_reg }
292 #define RMBH { OP_REG, bh_reg }
293 #define RMAX { OP_REG, ax_reg }
294 #define RMDX { OP_REG, dx_reg }
296 #define eAX { OP_IMREG, eAX_reg }
297 #define eBX { OP_IMREG, eBX_reg }
298 #define eCX { OP_IMREG, eCX_reg }
299 #define eDX { OP_IMREG, eDX_reg }
300 #define eSP { OP_IMREG, eSP_reg }
301 #define eBP { OP_IMREG, eBP_reg }
302 #define eSI { OP_IMREG, eSI_reg }
303 #define eDI { OP_IMREG, eDI_reg }
304 #define AL { OP_IMREG, al_reg }
305 #define CL { OP_IMREG, cl_reg }
306 #define DL { OP_IMREG, dl_reg }
307 #define BL { OP_IMREG, bl_reg }
308 #define AH { OP_IMREG, ah_reg }
309 #define CH { OP_IMREG, ch_reg }
310 #define DH { OP_IMREG, dh_reg }
311 #define BH { OP_IMREG, bh_reg }
312 #define AX { OP_IMREG, ax_reg }
313 #define DX { OP_IMREG, dx_reg }
314 #define zAX { OP_IMREG, z_mode_ax_reg }
315 #define indirDX { OP_IMREG, indir_dx_reg }
317 #define Sw { OP_SEG, w_mode }
318 #define Sv { OP_SEG, v_mode }
319 #define Ap { OP_DIR, 0 }
320 #define Ob { OP_OFF64, b_mode }
321 #define Ov { OP_OFF64, v_mode }
322 #define Xb { OP_DSreg, eSI_reg }
323 #define Xv { OP_DSreg, eSI_reg }
324 #define Xz { OP_DSreg, eSI_reg }
325 #define Yb { OP_ESreg, eDI_reg }
326 #define Yv { OP_ESreg, eDI_reg }
327 #define DSBX { OP_DSreg, eBX_reg }
329 #define es { OP_REG, es_reg }
330 #define ss { OP_REG, ss_reg }
331 #define cs { OP_REG, cs_reg }
332 #define ds { OP_REG, ds_reg }
333 #define fs { OP_REG, fs_reg }
334 #define gs { OP_REG, gs_reg }
336 #define MX { OP_MMX, 0 }
337 #define XM { OP_XMM, 0 }
338 #define XMScalar { OP_XMM, scalar_mode }
339 #define XMM { OP_XMM, xmm_mode }
340 #define EM { OP_EM, v_mode }
341 #define EMS { OP_EM, v_swap_mode }
342 #define EMd { OP_EM, d_mode }
343 #define EMx { OP_EM, x_mode }
344 #define EXw { OP_EX, w_mode }
345 #define EXd { OP_EX, d_mode }
346 #define EXdScalar { OP_EX, d_scalar_mode }
347 #define EXdS { OP_EX, d_swap_mode }
348 #define EXq { OP_EX, q_mode }
349 #define EXqScalar { OP_EX, q_scalar_mode }
350 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
351 #define EXqS { OP_EX, q_swap_mode }
352 #define EXx { OP_EX, x_mode }
353 #define EXxS { OP_EX, x_swap_mode }
354 #define EXxmm { OP_EX, xmm_mode }
355 #define EXxmmq { OP_EX, xmmq_mode }
356 #define EXymmq { OP_EX, ymmq_mode }
357 #define EXVexWdq { OP_EX, vex_w_dq_mode }
358 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
359 #define MS { OP_MS, v_mode }
360 #define XS { OP_XS, v_mode }
361 #define EMCq { OP_EMC, q_mode }
362 #define MXC { OP_MXC, 0 }
363 #define OPSUF { OP_3DNowSuffix, 0 }
364 #define CMP { CMP_Fixup, 0 }
365 #define XMM0 { XMM_Fixup, 0 }
366 #define FXSAVE { FXSAVE_Fixup, 0 }
367 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
368 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
370 #define Vex { OP_VEX, vex_mode }
371 #define VexScalar { OP_VEX, vex_scalar_mode }
372 #define Vex128 { OP_VEX, vex128_mode }
373 #define Vex256 { OP_VEX, vex256_mode }
374 #define VexI4 { VEXI4_Fixup, 0}
375 #define EXdVex { OP_EX_Vex, d_mode }
376 #define EXdVexS { OP_EX_Vex, d_swap_mode }
377 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
378 #define EXqVex { OP_EX_Vex, q_mode }
379 #define EXqVexS { OP_EX_Vex, q_swap_mode }
380 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
381 #define EXVexW { OP_EX_VexW, x_mode }
382 #define EXdVexW { OP_EX_VexW, d_mode }
383 #define EXqVexW { OP_EX_VexW, q_mode }
384 #define EXVexImmW { OP_EX_VexImmW, x_mode }
385 #define XMVex { OP_XMM_Vex, 0 }
386 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
387 #define XMVexW { OP_XMM_VexW, 0 }
388 #define XMVexI4 { OP_REG_VexI4, x_mode }
389 #define PCLMUL { PCLMUL_Fixup, 0 }
390 #define VZERO { VZERO_Fixup, 0 }
391 #define VCMP { VCMP_Fixup, 0 }
393 /* Used handle "rep" prefix for string instructions. */
394 #define Xbr { REP_Fixup, eSI_reg }
395 #define Xvr { REP_Fixup, eSI_reg }
396 #define Ybr { REP_Fixup, eDI_reg }
397 #define Yvr { REP_Fixup, eDI_reg }
398 #define Yzr { REP_Fixup, eDI_reg }
399 #define indirDXr { REP_Fixup, indir_dx_reg }
400 #define ALr { REP_Fixup, al_reg }
401 #define eAXr { REP_Fixup, eAX_reg }
403 #define cond_jump_flag { NULL, cond_jump_mode }
404 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
406 /* bits in sizeflag */
407 #define SUFFIX_ALWAYS 4
415 /* byte operand with operand swapped */
417 /* operand size depends on prefixes */
419 /* operand size depends on prefixes with operand swapped */
423 /* double word operand */
425 /* double word operand with operand swapped */
427 /* quad word operand */
429 /* quad word operand with operand swapped */
431 /* ten-byte operand */
433 /* 16-byte XMM or 32-byte YMM operand */
435 /* 16-byte XMM or 32-byte YMM operand with operand swapped */
437 /* 16-byte XMM operand */
439 /* 16-byte XMM or quad word operand */
441 /* 32-byte YMM or quad word operand */
443 /* d_mode in 32bit, q_mode in 64bit mode. */
445 /* pair of v_mode operands */
449 /* operand size depends on REX prefixes. */
451 /* registers like dq_mode, memory like w_mode. */
453 /* 4- or 6-byte pointer operand */
456 /* v_mode for stack-related opcodes. */
458 /* non-quad operand size depends on prefixes */
460 /* 16-byte operand */
462 /* registers like dq_mode, memory like b_mode. */
464 /* registers like dq_mode, memory like d_mode. */
466 /* normal vex mode */
468 /* 128bit vex mode */
470 /* 256bit vex mode */
472 /* operand size depends on the VEX.W bit. */
475 /* scalar, ignore vector length. */
477 /* like d_mode, ignore vector length. */
479 /* like d_swap_mode, ignore vector length. */
481 /* like q_mode, ignore vector length. */
483 /* like q_swap_mode, ignore vector length. */
485 /* like vex_mode, ignore vector length. */
487 /* like vex_w_dq_mode, ignore vector length. */
488 vex_scalar_w_dq_mode
,
553 #define FLOAT NULL, { { NULL, FLOATCODE } }
555 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }
556 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
557 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
558 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
559 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
560 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
561 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
562 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
563 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
564 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
565 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
566 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
663 MOD_VEX_0F12_PREFIX_0
,
665 MOD_VEX_0F16_PREFIX_0
,
681 MOD_VEX_0FD7_PREFIX_2
,
682 MOD_VEX_0FE7_PREFIX_2
,
683 MOD_VEX_0FF0_PREFIX_3
,
684 MOD_VEX_0F3818_PREFIX_2
,
685 MOD_VEX_0F3819_PREFIX_2
,
686 MOD_VEX_0F381A_PREFIX_2
,
687 MOD_VEX_0F382A_PREFIX_2
,
688 MOD_VEX_0F382C_PREFIX_2
,
689 MOD_VEX_0F382D_PREFIX_2
,
690 MOD_VEX_0F382E_PREFIX_2
,
691 MOD_VEX_0F382F_PREFIX_2
860 PREFIX_VEX_0F71_REG_2
,
861 PREFIX_VEX_0F71_REG_4
,
862 PREFIX_VEX_0F71_REG_6
,
863 PREFIX_VEX_0F72_REG_2
,
864 PREFIX_VEX_0F72_REG_4
,
865 PREFIX_VEX_0F72_REG_6
,
866 PREFIX_VEX_0F73_REG_2
,
867 PREFIX_VEX_0F73_REG_3
,
868 PREFIX_VEX_0F73_REG_6
,
869 PREFIX_VEX_0F73_REG_7
,
1109 THREE_BYTE_0F38
= 0,
1130 VEX_LEN_0F10_P_1
= 0,
1134 VEX_LEN_0F12_P_0_M_0
,
1135 VEX_LEN_0F12_P_0_M_1
,
1138 VEX_LEN_0F16_P_0_M_0
,
1139 VEX_LEN_0F16_P_0_M_1
,
1188 VEX_LEN_0F71_R_2_P_2
,
1189 VEX_LEN_0F71_R_4_P_2
,
1190 VEX_LEN_0F71_R_6_P_2
,
1191 VEX_LEN_0F72_R_2_P_2
,
1192 VEX_LEN_0F72_R_4_P_2
,
1193 VEX_LEN_0F72_R_6_P_2
,
1194 VEX_LEN_0F73_R_2_P_2
,
1195 VEX_LEN_0F73_R_3_P_2
,
1196 VEX_LEN_0F73_R_6_P_2
,
1197 VEX_LEN_0F73_R_7_P_2
,
1203 VEX_LEN_0FAE_R_2_M_0
,
1204 VEX_LEN_0FAE_R_3_M_0
,
1215 VEX_LEN_0FD7_P_2_M_1
,
1264 VEX_LEN_0F3819_P_2_M_0
,
1265 VEX_LEN_0F381A_P_2_M_0
,
1277 VEX_LEN_0F382A_P_2_M_0
,
1332 VEX_LEN_0FXOP_09_80
,
1520 VEX_W_0F3818_P_2_M_0
,
1521 VEX_W_0F3819_P_2_M_0
,
1522 VEX_W_0F381A_P_2_M_0
,
1534 VEX_W_0F382A_P_2_M_0
,
1536 VEX_W_0F382C_P_2_M_0
,
1537 VEX_W_0F382D_P_2_M_0
,
1538 VEX_W_0F382E_P_2_M_0
,
1539 VEX_W_0F382F_P_2_M_0
,
1595 typedef void (*op_rtn
) (int bytemode
, int sizeflag
);
1606 /* Upper case letters in the instruction names here are macros.
1607 'A' => print 'b' if no register operands or suffix_always is true
1608 'B' => print 'b' if suffix_always is true
1609 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1611 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1612 suffix_always is true
1613 'E' => print 'e' if 32-bit form of jcxz
1614 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1615 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1616 'H' => print ",pt" or ",pn" branch hint
1617 'I' => honor following macro letter even in Intel mode (implemented only
1618 for some of the macro letters)
1620 'K' => print 'd' or 'q' if rex prefix is present.
1621 'L' => print 'l' if suffix_always is true
1622 'M' => print 'r' if intel_mnemonic is false.
1623 'N' => print 'n' if instruction has no wait "prefix"
1624 'O' => print 'd' or 'o' (or 'q' in Intel mode)
1625 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
1626 or suffix_always is true. print 'q' if rex prefix is present.
1627 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1629 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1630 'S' => print 'w', 'l' or 'q' if suffix_always is true
1631 'T' => print 'q' in 64bit mode and behave as 'P' otherwise
1632 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
1633 'V' => print 'q' in 64bit mode and behave as 'S' otherwise
1634 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1635 'X' => print 's', 'd' depending on data16 prefix (for XMM)
1636 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
1637 suffix_always is true.
1638 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
1639 '!' => change condition from true to false or from false to true.
1640 '%' => add 1 upper case letter to the macro.
1642 2 upper case letter macros:
1643 "XY" => print 'x' or 'y' if no register operands or suffix_always
1645 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1646 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
1647 or suffix_always is true
1648 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1649 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1650 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1652 Many of the above letters print nothing in Intel mode. See "putop"
1655 Braces '{' and '}', and vertical bars '|', indicate alternative
1656 mnemonic strings for AT&T and Intel. */
1658 static const struct dis386 dis386
[] = {
1660 { "addB", { Eb
, Gb
} },
1661 { "addS", { Ev
, Gv
} },
1662 { "addB", { Gb
, EbS
} },
1663 { "addS", { Gv
, EvS
} },
1664 { "addB", { AL
, Ib
} },
1665 { "addS", { eAX
, Iv
} },
1666 { X86_64_TABLE (X86_64_06
) },
1667 { X86_64_TABLE (X86_64_07
) },
1669 { "orB", { Eb
, Gb
} },
1670 { "orS", { Ev
, Gv
} },
1671 { "orB", { Gb
, EbS
} },
1672 { "orS", { Gv
, EvS
} },
1673 { "orB", { AL
, Ib
} },
1674 { "orS", { eAX
, Iv
} },
1675 { X86_64_TABLE (X86_64_0D
) },
1676 { Bad_Opcode
}, /* 0x0f extended opcode escape */
1678 { "adcB", { Eb
, Gb
} },
1679 { "adcS", { Ev
, Gv
} },
1680 { "adcB", { Gb
, EbS
} },
1681 { "adcS", { Gv
, EvS
} },
1682 { "adcB", { AL
, Ib
} },
1683 { "adcS", { eAX
, Iv
} },
1684 { X86_64_TABLE (X86_64_16
) },
1685 { X86_64_TABLE (X86_64_17
) },
1687 { "sbbB", { Eb
, Gb
} },
1688 { "sbbS", { Ev
, Gv
} },
1689 { "sbbB", { Gb
, EbS
} },
1690 { "sbbS", { Gv
, EvS
} },
1691 { "sbbB", { AL
, Ib
} },
1692 { "sbbS", { eAX
, Iv
} },
1693 { X86_64_TABLE (X86_64_1E
) },
1694 { X86_64_TABLE (X86_64_1F
) },
1696 { "andB", { Eb
, Gb
} },
1697 { "andS", { Ev
, Gv
} },
1698 { "andB", { Gb
, EbS
} },
1699 { "andS", { Gv
, EvS
} },
1700 { "andB", { AL
, Ib
} },
1701 { "andS", { eAX
, Iv
} },
1702 { Bad_Opcode
}, /* SEG ES prefix */
1703 { X86_64_TABLE (X86_64_27
) },
1705 { "subB", { Eb
, Gb
} },
1706 { "subS", { Ev
, Gv
} },
1707 { "subB", { Gb
, EbS
} },
1708 { "subS", { Gv
, EvS
} },
1709 { "subB", { AL
, Ib
} },
1710 { "subS", { eAX
, Iv
} },
1711 { Bad_Opcode
}, /* SEG CS prefix */
1712 { X86_64_TABLE (X86_64_2F
) },
1714 { "xorB", { Eb
, Gb
} },
1715 { "xorS", { Ev
, Gv
} },
1716 { "xorB", { Gb
, EbS
} },
1717 { "xorS", { Gv
, EvS
} },
1718 { "xorB", { AL
, Ib
} },
1719 { "xorS", { eAX
, Iv
} },
1720 { Bad_Opcode
}, /* SEG SS prefix */
1721 { X86_64_TABLE (X86_64_37
) },
1723 { "cmpB", { Eb
, Gb
} },
1724 { "cmpS", { Ev
, Gv
} },
1725 { "cmpB", { Gb
, EbS
} },
1726 { "cmpS", { Gv
, EvS
} },
1727 { "cmpB", { AL
, Ib
} },
1728 { "cmpS", { eAX
, Iv
} },
1729 { Bad_Opcode
}, /* SEG DS prefix */
1730 { X86_64_TABLE (X86_64_3F
) },
1732 { "inc{S|}", { RMeAX
} },
1733 { "inc{S|}", { RMeCX
} },
1734 { "inc{S|}", { RMeDX
} },
1735 { "inc{S|}", { RMeBX
} },
1736 { "inc{S|}", { RMeSP
} },
1737 { "inc{S|}", { RMeBP
} },
1738 { "inc{S|}", { RMeSI
} },
1739 { "inc{S|}", { RMeDI
} },
1741 { "dec{S|}", { RMeAX
} },
1742 { "dec{S|}", { RMeCX
} },
1743 { "dec{S|}", { RMeDX
} },
1744 { "dec{S|}", { RMeBX
} },
1745 { "dec{S|}", { RMeSP
} },
1746 { "dec{S|}", { RMeBP
} },
1747 { "dec{S|}", { RMeSI
} },
1748 { "dec{S|}", { RMeDI
} },
1750 { "pushV", { RMrAX
} },
1751 { "pushV", { RMrCX
} },
1752 { "pushV", { RMrDX
} },
1753 { "pushV", { RMrBX
} },
1754 { "pushV", { RMrSP
} },
1755 { "pushV", { RMrBP
} },
1756 { "pushV", { RMrSI
} },
1757 { "pushV", { RMrDI
} },
1759 { "popV", { RMrAX
} },
1760 { "popV", { RMrCX
} },
1761 { "popV", { RMrDX
} },
1762 { "popV", { RMrBX
} },
1763 { "popV", { RMrSP
} },
1764 { "popV", { RMrBP
} },
1765 { "popV", { RMrSI
} },
1766 { "popV", { RMrDI
} },
1768 { X86_64_TABLE (X86_64_60
) },
1769 { X86_64_TABLE (X86_64_61
) },
1770 { X86_64_TABLE (X86_64_62
) },
1771 { X86_64_TABLE (X86_64_63
) },
1772 { Bad_Opcode
}, /* seg fs */
1773 { Bad_Opcode
}, /* seg gs */
1774 { Bad_Opcode
}, /* op size prefix */
1775 { Bad_Opcode
}, /* adr size prefix */
1777 { "pushT", { sIv
} },
1778 { "imulS", { Gv
, Ev
, Iv
} },
1779 { "pushT", { sIb
} },
1780 { "imulS", { Gv
, Ev
, sIb
} },
1781 { "ins{b|}", { Ybr
, indirDX
} },
1782 { X86_64_TABLE (X86_64_6D
) },
1783 { "outs{b|}", { indirDXr
, Xb
} },
1784 { X86_64_TABLE (X86_64_6F
) },
1786 { "joH", { Jb
, XX
, cond_jump_flag
} },
1787 { "jnoH", { Jb
, XX
, cond_jump_flag
} },
1788 { "jbH", { Jb
, XX
, cond_jump_flag
} },
1789 { "jaeH", { Jb
, XX
, cond_jump_flag
} },
1790 { "jeH", { Jb
, XX
, cond_jump_flag
} },
1791 { "jneH", { Jb
, XX
, cond_jump_flag
} },
1792 { "jbeH", { Jb
, XX
, cond_jump_flag
} },
1793 { "jaH", { Jb
, XX
, cond_jump_flag
} },
1795 { "jsH", { Jb
, XX
, cond_jump_flag
} },
1796 { "jnsH", { Jb
, XX
, cond_jump_flag
} },
1797 { "jpH", { Jb
, XX
, cond_jump_flag
} },
1798 { "jnpH", { Jb
, XX
, cond_jump_flag
} },
1799 { "jlH", { Jb
, XX
, cond_jump_flag
} },
1800 { "jgeH", { Jb
, XX
, cond_jump_flag
} },
1801 { "jleH", { Jb
, XX
, cond_jump_flag
} },
1802 { "jgH", { Jb
, XX
, cond_jump_flag
} },
1804 { REG_TABLE (REG_80
) },
1805 { REG_TABLE (REG_81
) },
1807 { REG_TABLE (REG_82
) },
1808 { "testB", { Eb
, Gb
} },
1809 { "testS", { Ev
, Gv
} },
1810 { "xchgB", { Eb
, Gb
} },
1811 { "xchgS", { Ev
, Gv
} },
1813 { "movB", { Eb
, Gb
} },
1814 { "movS", { Ev
, Gv
} },
1815 { "movB", { Gb
, EbS
} },
1816 { "movS", { Gv
, EvS
} },
1817 { "movD", { Sv
, Sw
} },
1818 { MOD_TABLE (MOD_8D
) },
1819 { "movD", { Sw
, Sv
} },
1820 { REG_TABLE (REG_8F
) },
1822 { PREFIX_TABLE (PREFIX_90
) },
1823 { "xchgS", { RMeCX
, eAX
} },
1824 { "xchgS", { RMeDX
, eAX
} },
1825 { "xchgS", { RMeBX
, eAX
} },
1826 { "xchgS", { RMeSP
, eAX
} },
1827 { "xchgS", { RMeBP
, eAX
} },
1828 { "xchgS", { RMeSI
, eAX
} },
1829 { "xchgS", { RMeDI
, eAX
} },
1831 { "cW{t|}R", { XX
} },
1832 { "cR{t|}O", { XX
} },
1833 { X86_64_TABLE (X86_64_9A
) },
1834 { Bad_Opcode
}, /* fwait */
1835 { "pushfT", { XX
} },
1836 { "popfT", { XX
} },
1840 { "mov%LB", { AL
, Ob
} },
1841 { "mov%LS", { eAX
, Ov
} },
1842 { "mov%LB", { Ob
, AL
} },
1843 { "mov%LS", { Ov
, eAX
} },
1844 { "movs{b|}", { Ybr
, Xb
} },
1845 { "movs{R|}", { Yvr
, Xv
} },
1846 { "cmps{b|}", { Xb
, Yb
} },
1847 { "cmps{R|}", { Xv
, Yv
} },
1849 { "testB", { AL
, Ib
} },
1850 { "testS", { eAX
, Iv
} },
1851 { "stosB", { Ybr
, AL
} },
1852 { "stosS", { Yvr
, eAX
} },
1853 { "lodsB", { ALr
, Xb
} },
1854 { "lodsS", { eAXr
, Xv
} },
1855 { "scasB", { AL
, Yb
} },
1856 { "scasS", { eAX
, Yv
} },
1858 { "movB", { RMAL
, Ib
} },
1859 { "movB", { RMCL
, Ib
} },
1860 { "movB", { RMDL
, Ib
} },
1861 { "movB", { RMBL
, Ib
} },
1862 { "movB", { RMAH
, Ib
} },
1863 { "movB", { RMCH
, Ib
} },
1864 { "movB", { RMDH
, Ib
} },
1865 { "movB", { RMBH
, Ib
} },
1867 { "mov%LV", { RMeAX
, Iv64
} },
1868 { "mov%LV", { RMeCX
, Iv64
} },
1869 { "mov%LV", { RMeDX
, Iv64
} },
1870 { "mov%LV", { RMeBX
, Iv64
} },
1871 { "mov%LV", { RMeSP
, Iv64
} },
1872 { "mov%LV", { RMeBP
, Iv64
} },
1873 { "mov%LV", { RMeSI
, Iv64
} },
1874 { "mov%LV", { RMeDI
, Iv64
} },
1876 { REG_TABLE (REG_C0
) },
1877 { REG_TABLE (REG_C1
) },
1880 { X86_64_TABLE (X86_64_C4
) },
1881 { X86_64_TABLE (X86_64_C5
) },
1882 { REG_TABLE (REG_C6
) },
1883 { REG_TABLE (REG_C7
) },
1885 { "enterT", { Iw
, Ib
} },
1886 { "leaveT", { XX
} },
1887 { "Jret{|f}P", { Iw
} },
1888 { "Jret{|f}P", { XX
} },
1891 { X86_64_TABLE (X86_64_CE
) },
1892 { "iretP", { XX
} },
1894 { REG_TABLE (REG_D0
) },
1895 { REG_TABLE (REG_D1
) },
1896 { REG_TABLE (REG_D2
) },
1897 { REG_TABLE (REG_D3
) },
1898 { X86_64_TABLE (X86_64_D4
) },
1899 { X86_64_TABLE (X86_64_D5
) },
1901 { "xlat", { DSBX
} },
1912 { "loopneFH", { Jb
, XX
, loop_jcxz_flag
} },
1913 { "loopeFH", { Jb
, XX
, loop_jcxz_flag
} },
1914 { "loopFH", { Jb
, XX
, loop_jcxz_flag
} },
1915 { "jEcxzH", { Jb
, XX
, loop_jcxz_flag
} },
1916 { "inB", { AL
, Ib
} },
1917 { "inG", { zAX
, Ib
} },
1918 { "outB", { Ib
, AL
} },
1919 { "outG", { Ib
, zAX
} },
1921 { "callT", { Jv
} },
1923 { X86_64_TABLE (X86_64_EA
) },
1925 { "inB", { AL
, indirDX
} },
1926 { "inG", { zAX
, indirDX
} },
1927 { "outB", { indirDX
, AL
} },
1928 { "outG", { indirDX
, zAX
} },
1930 { Bad_Opcode
}, /* lock prefix */
1931 { "icebp", { XX
} },
1932 { Bad_Opcode
}, /* repne */
1933 { Bad_Opcode
}, /* repz */
1936 { REG_TABLE (REG_F6
) },
1937 { REG_TABLE (REG_F7
) },
1945 { REG_TABLE (REG_FE
) },
1946 { REG_TABLE (REG_FF
) },
1949 static const struct dis386 dis386_twobyte
[] = {
1951 { REG_TABLE (REG_0F00
) },
1952 { REG_TABLE (REG_0F01
) },
1953 { "larS", { Gv
, Ew
} },
1954 { "lslS", { Gv
, Ew
} },
1956 { "syscall", { XX
} },
1958 { "sysretP", { XX
} },
1961 { "wbinvd", { XX
} },
1965 { REG_TABLE (REG_0F0D
) },
1966 { "femms", { XX
} },
1967 { "", { MX
, EM
, OPSUF
} }, /* See OP_3DNowSuffix. */
1969 { PREFIX_TABLE (PREFIX_0F10
) },
1970 { PREFIX_TABLE (PREFIX_0F11
) },
1971 { PREFIX_TABLE (PREFIX_0F12
) },
1972 { MOD_TABLE (MOD_0F13
) },
1973 { "unpcklpX", { XM
, EXx
} },
1974 { "unpckhpX", { XM
, EXx
} },
1975 { PREFIX_TABLE (PREFIX_0F16
) },
1976 { MOD_TABLE (MOD_0F17
) },
1978 { REG_TABLE (REG_0F18
) },
1987 { MOD_TABLE (MOD_0F20
) },
1988 { MOD_TABLE (MOD_0F21
) },
1989 { MOD_TABLE (MOD_0F22
) },
1990 { MOD_TABLE (MOD_0F23
) },
1991 { MOD_TABLE (MOD_0F24
) },
1993 { MOD_TABLE (MOD_0F26
) },
1996 { "movapX", { XM
, EXx
} },
1997 { "movapX", { EXxS
, XM
} },
1998 { PREFIX_TABLE (PREFIX_0F2A
) },
1999 { PREFIX_TABLE (PREFIX_0F2B
) },
2000 { PREFIX_TABLE (PREFIX_0F2C
) },
2001 { PREFIX_TABLE (PREFIX_0F2D
) },
2002 { PREFIX_TABLE (PREFIX_0F2E
) },
2003 { PREFIX_TABLE (PREFIX_0F2F
) },
2005 { "wrmsr", { XX
} },
2006 { "rdtsc", { XX
} },
2007 { "rdmsr", { XX
} },
2008 { "rdpmc", { XX
} },
2009 { "sysenter", { XX
} },
2010 { "sysexit", { XX
} },
2012 { "getsec", { XX
} },
2014 { THREE_BYTE_TABLE (THREE_BYTE_0F38
) },
2016 { THREE_BYTE_TABLE (THREE_BYTE_0F3A
) },
2023 { "cmovoS", { Gv
, Ev
} },
2024 { "cmovnoS", { Gv
, Ev
} },
2025 { "cmovbS", { Gv
, Ev
} },
2026 { "cmovaeS", { Gv
, Ev
} },
2027 { "cmoveS", { Gv
, Ev
} },
2028 { "cmovneS", { Gv
, Ev
} },
2029 { "cmovbeS", { Gv
, Ev
} },
2030 { "cmovaS", { Gv
, Ev
} },
2032 { "cmovsS", { Gv
, Ev
} },
2033 { "cmovnsS", { Gv
, Ev
} },
2034 { "cmovpS", { Gv
, Ev
} },
2035 { "cmovnpS", { Gv
, Ev
} },
2036 { "cmovlS", { Gv
, Ev
} },
2037 { "cmovgeS", { Gv
, Ev
} },
2038 { "cmovleS", { Gv
, Ev
} },
2039 { "cmovgS", { Gv
, Ev
} },
2041 { MOD_TABLE (MOD_0F51
) },
2042 { PREFIX_TABLE (PREFIX_0F51
) },
2043 { PREFIX_TABLE (PREFIX_0F52
) },
2044 { PREFIX_TABLE (PREFIX_0F53
) },
2045 { "andpX", { XM
, EXx
} },
2046 { "andnpX", { XM
, EXx
} },
2047 { "orpX", { XM
, EXx
} },
2048 { "xorpX", { XM
, EXx
} },
2050 { PREFIX_TABLE (PREFIX_0F58
) },
2051 { PREFIX_TABLE (PREFIX_0F59
) },
2052 { PREFIX_TABLE (PREFIX_0F5A
) },
2053 { PREFIX_TABLE (PREFIX_0F5B
) },
2054 { PREFIX_TABLE (PREFIX_0F5C
) },
2055 { PREFIX_TABLE (PREFIX_0F5D
) },
2056 { PREFIX_TABLE (PREFIX_0F5E
) },
2057 { PREFIX_TABLE (PREFIX_0F5F
) },
2059 { PREFIX_TABLE (PREFIX_0F60
) },
2060 { PREFIX_TABLE (PREFIX_0F61
) },
2061 { PREFIX_TABLE (PREFIX_0F62
) },
2062 { "packsswb", { MX
, EM
} },
2063 { "pcmpgtb", { MX
, EM
} },
2064 { "pcmpgtw", { MX
, EM
} },
2065 { "pcmpgtd", { MX
, EM
} },
2066 { "packuswb", { MX
, EM
} },
2068 { "punpckhbw", { MX
, EM
} },
2069 { "punpckhwd", { MX
, EM
} },
2070 { "punpckhdq", { MX
, EM
} },
2071 { "packssdw", { MX
, EM
} },
2072 { PREFIX_TABLE (PREFIX_0F6C
) },
2073 { PREFIX_TABLE (PREFIX_0F6D
) },
2074 { "movK", { MX
, Edq
} },
2075 { PREFIX_TABLE (PREFIX_0F6F
) },
2077 { PREFIX_TABLE (PREFIX_0F70
) },
2078 { REG_TABLE (REG_0F71
) },
2079 { REG_TABLE (REG_0F72
) },
2080 { REG_TABLE (REG_0F73
) },
2081 { "pcmpeqb", { MX
, EM
} },
2082 { "pcmpeqw", { MX
, EM
} },
2083 { "pcmpeqd", { MX
, EM
} },
2086 { PREFIX_TABLE (PREFIX_0F78
) },
2087 { PREFIX_TABLE (PREFIX_0F79
) },
2088 { THREE_BYTE_TABLE (THREE_BYTE_0F7A
) },
2090 { PREFIX_TABLE (PREFIX_0F7C
) },
2091 { PREFIX_TABLE (PREFIX_0F7D
) },
2092 { PREFIX_TABLE (PREFIX_0F7E
) },
2093 { PREFIX_TABLE (PREFIX_0F7F
) },
2095 { "joH", { Jv
, XX
, cond_jump_flag
} },
2096 { "jnoH", { Jv
, XX
, cond_jump_flag
} },
2097 { "jbH", { Jv
, XX
, cond_jump_flag
} },
2098 { "jaeH", { Jv
, XX
, cond_jump_flag
} },
2099 { "jeH", { Jv
, XX
, cond_jump_flag
} },
2100 { "jneH", { Jv
, XX
, cond_jump_flag
} },
2101 { "jbeH", { Jv
, XX
, cond_jump_flag
} },
2102 { "jaH", { Jv
, XX
, cond_jump_flag
} },
2104 { "jsH", { Jv
, XX
, cond_jump_flag
} },
2105 { "jnsH", { Jv
, XX
, cond_jump_flag
} },
2106 { "jpH", { Jv
, XX
, cond_jump_flag
} },
2107 { "jnpH", { Jv
, XX
, cond_jump_flag
} },
2108 { "jlH", { Jv
, XX
, cond_jump_flag
} },
2109 { "jgeH", { Jv
, XX
, cond_jump_flag
} },
2110 { "jleH", { Jv
, XX
, cond_jump_flag
} },
2111 { "jgH", { Jv
, XX
, cond_jump_flag
} },
2114 { "setno", { Eb
} },
2116 { "setae", { Eb
} },
2118 { "setne", { Eb
} },
2119 { "setbe", { Eb
} },
2123 { "setns", { Eb
} },
2125 { "setnp", { Eb
} },
2127 { "setge", { Eb
} },
2128 { "setle", { Eb
} },
2131 { "pushT", { fs
} },
2133 { "cpuid", { XX
} },
2134 { "btS", { Ev
, Gv
} },
2135 { "shldS", { Ev
, Gv
, Ib
} },
2136 { "shldS", { Ev
, Gv
, CL
} },
2137 { REG_TABLE (REG_0FA6
) },
2138 { REG_TABLE (REG_0FA7
) },
2140 { "pushT", { gs
} },
2143 { "btsS", { Ev
, Gv
} },
2144 { "shrdS", { Ev
, Gv
, Ib
} },
2145 { "shrdS", { Ev
, Gv
, CL
} },
2146 { REG_TABLE (REG_0FAE
) },
2147 { "imulS", { Gv
, Ev
} },
2149 { "cmpxchgB", { Eb
, Gb
} },
2150 { "cmpxchgS", { Ev
, Gv
} },
2151 { MOD_TABLE (MOD_0FB2
) },
2152 { "btrS", { Ev
, Gv
} },
2153 { MOD_TABLE (MOD_0FB4
) },
2154 { MOD_TABLE (MOD_0FB5
) },
2155 { "movz{bR|x}", { Gv
, Eb
} },
2156 { "movz{wR|x}", { Gv
, Ew
} }, /* yes, there really is movzww ! */
2158 { PREFIX_TABLE (PREFIX_0FB8
) },
2160 { REG_TABLE (REG_0FBA
) },
2161 { "btcS", { Ev
, Gv
} },
2162 { "bsfS", { Gv
, Ev
} },
2163 { PREFIX_TABLE (PREFIX_0FBD
) },
2164 { "movs{bR|x}", { Gv
, Eb
} },
2165 { "movs{wR|x}", { Gv
, Ew
} }, /* yes, there really is movsww ! */
2167 { "xaddB", { Eb
, Gb
} },
2168 { "xaddS", { Ev
, Gv
} },
2169 { PREFIX_TABLE (PREFIX_0FC2
) },
2170 { PREFIX_TABLE (PREFIX_0FC3
) },
2171 { "pinsrw", { MX
, Edqw
, Ib
} },
2172 { "pextrw", { Gdq
, MS
, Ib
} },
2173 { "shufpX", { XM
, EXx
, Ib
} },
2174 { REG_TABLE (REG_0FC7
) },
2176 { "bswap", { RMeAX
} },
2177 { "bswap", { RMeCX
} },
2178 { "bswap", { RMeDX
} },
2179 { "bswap", { RMeBX
} },
2180 { "bswap", { RMeSP
} },
2181 { "bswap", { RMeBP
} },
2182 { "bswap", { RMeSI
} },
2183 { "bswap", { RMeDI
} },
2185 { PREFIX_TABLE (PREFIX_0FD0
) },
2186 { "psrlw", { MX
, EM
} },
2187 { "psrld", { MX
, EM
} },
2188 { "psrlq", { MX
, EM
} },
2189 { "paddq", { MX
, EM
} },
2190 { "pmullw", { MX
, EM
} },
2191 { PREFIX_TABLE (PREFIX_0FD6
) },
2192 { MOD_TABLE (MOD_0FD7
) },
2194 { "psubusb", { MX
, EM
} },
2195 { "psubusw", { MX
, EM
} },
2196 { "pminub", { MX
, EM
} },
2197 { "pand", { MX
, EM
} },
2198 { "paddusb", { MX
, EM
} },
2199 { "paddusw", { MX
, EM
} },
2200 { "pmaxub", { MX
, EM
} },
2201 { "pandn", { MX
, EM
} },
2203 { "pavgb", { MX
, EM
} },
2204 { "psraw", { MX
, EM
} },
2205 { "psrad", { MX
, EM
} },
2206 { "pavgw", { MX
, EM
} },
2207 { "pmulhuw", { MX
, EM
} },
2208 { "pmulhw", { MX
, EM
} },
2209 { PREFIX_TABLE (PREFIX_0FE6
) },
2210 { PREFIX_TABLE (PREFIX_0FE7
) },
2212 { "psubsb", { MX
, EM
} },
2213 { "psubsw", { MX
, EM
} },
2214 { "pminsw", { MX
, EM
} },
2215 { "por", { MX
, EM
} },
2216 { "paddsb", { MX
, EM
} },
2217 { "paddsw", { MX
, EM
} },
2218 { "pmaxsw", { MX
, EM
} },
2219 { "pxor", { MX
, EM
} },
2221 { PREFIX_TABLE (PREFIX_0FF0
) },
2222 { "psllw", { MX
, EM
} },
2223 { "pslld", { MX
, EM
} },
2224 { "psllq", { MX
, EM
} },
2225 { "pmuludq", { MX
, EM
} },
2226 { "pmaddwd", { MX
, EM
} },
2227 { "psadbw", { MX
, EM
} },
2228 { PREFIX_TABLE (PREFIX_0FF7
) },
2230 { "psubb", { MX
, EM
} },
2231 { "psubw", { MX
, EM
} },
2232 { "psubd", { MX
, EM
} },
2233 { "psubq", { MX
, EM
} },
2234 { "paddb", { MX
, EM
} },
2235 { "paddw", { MX
, EM
} },
2236 { "paddd", { MX
, EM
} },
2240 static const unsigned char onebyte_has_modrm
[256] = {
2241 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2242 /* ------------------------------- */
2243 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2244 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2245 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2246 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2247 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2248 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2249 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2250 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2251 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2252 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2253 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2254 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2255 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2256 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2257 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2258 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2259 /* ------------------------------- */
2260 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2263 static const unsigned char twobyte_has_modrm
[256] = {
2264 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2265 /* ------------------------------- */
2266 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2267 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2268 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2269 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2270 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2271 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2272 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2273 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2274 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2275 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2276 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2277 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
2278 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2279 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2280 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2281 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
2282 /* ------------------------------- */
2283 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2286 static char obuf
[100];
2288 static char *mnemonicendp
;
2289 static char scratchbuf
[100];
2290 static unsigned char *start_codep
;
2291 static unsigned char *insn_codep
;
2292 static unsigned char *codep
;
2293 static int last_lock_prefix
;
2294 static int last_repz_prefix
;
2295 static int last_repnz_prefix
;
2296 static int last_data_prefix
;
2297 static int last_addr_prefix
;
2298 static int last_rex_prefix
;
2299 static int last_seg_prefix
;
2300 #define MAX_CODE_LENGTH 15
2301 /* We can up to 14 prefixes since the maximum instruction length is
2303 static int all_prefixes
[MAX_CODE_LENGTH
- 1];
2304 static disassemble_info
*the_info
;
2312 static unsigned char need_modrm
;
2322 int register_specifier
;
2328 static unsigned char need_vex
;
2329 static unsigned char need_vex_reg
;
2330 static unsigned char vex_w_done
;
2338 /* If we are accessing mod/rm/reg without need_modrm set, then the
2339 values are stale. Hitting this abort likely indicates that you
2340 need to update onebyte_has_modrm or twobyte_has_modrm. */
2341 #define MODRM_CHECK if (!need_modrm) abort ()
2343 static const char **names64
;
2344 static const char **names32
;
2345 static const char **names16
;
2346 static const char **names8
;
2347 static const char **names8rex
;
2348 static const char **names_seg
;
2349 static const char *index64
;
2350 static const char *index32
;
2351 static const char **index16
;
2353 static const char *intel_names64
[] = {
2354 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2355 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2357 static const char *intel_names32
[] = {
2358 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2359 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2361 static const char *intel_names16
[] = {
2362 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2363 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2365 static const char *intel_names8
[] = {
2366 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2368 static const char *intel_names8rex
[] = {
2369 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2370 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2372 static const char *intel_names_seg
[] = {
2373 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2375 static const char *intel_index64
= "riz";
2376 static const char *intel_index32
= "eiz";
2377 static const char *intel_index16
[] = {
2378 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2381 static const char *att_names64
[] = {
2382 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2383 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2385 static const char *att_names32
[] = {
2386 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2387 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2389 static const char *att_names16
[] = {
2390 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2391 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2393 static const char *att_names8
[] = {
2394 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2396 static const char *att_names8rex
[] = {
2397 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2398 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2400 static const char *att_names_seg
[] = {
2401 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2403 static const char *att_index64
= "%riz";
2404 static const char *att_index32
= "%eiz";
2405 static const char *att_index16
[] = {
2406 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2409 static const char **names_mm
;
2410 static const char *intel_names_mm
[] = {
2411 "mm0", "mm1", "mm2", "mm3",
2412 "mm4", "mm5", "mm6", "mm7"
2414 static const char *att_names_mm
[] = {
2415 "%mm0", "%mm1", "%mm2", "%mm3",
2416 "%mm4", "%mm5", "%mm6", "%mm7"
2419 static const char **names_xmm
;
2420 static const char *intel_names_xmm
[] = {
2421 "xmm0", "xmm1", "xmm2", "xmm3",
2422 "xmm4", "xmm5", "xmm6", "xmm7",
2423 "xmm8", "xmm9", "xmm10", "xmm11",
2424 "xmm12", "xmm13", "xmm14", "xmm15"
2426 static const char *att_names_xmm
[] = {
2427 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2428 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2429 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2430 "%xmm12", "%xmm13", "%xmm14", "%xmm15"
2433 static const char **names_ymm
;
2434 static const char *intel_names_ymm
[] = {
2435 "ymm0", "ymm1", "ymm2", "ymm3",
2436 "ymm4", "ymm5", "ymm6", "ymm7",
2437 "ymm8", "ymm9", "ymm10", "ymm11",
2438 "ymm12", "ymm13", "ymm14", "ymm15"
2440 static const char *att_names_ymm
[] = {
2441 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2442 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2443 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2444 "%ymm12", "%ymm13", "%ymm14", "%ymm15"
2447 static const struct dis386 reg_table
[][8] = {
2450 { "addA", { Eb
, Ib
} },
2451 { "orA", { Eb
, Ib
} },
2452 { "adcA", { Eb
, Ib
} },
2453 { "sbbA", { Eb
, Ib
} },
2454 { "andA", { Eb
, Ib
} },
2455 { "subA", { Eb
, Ib
} },
2456 { "xorA", { Eb
, Ib
} },
2457 { "cmpA", { Eb
, Ib
} },
2461 { "addQ", { Ev
, Iv
} },
2462 { "orQ", { Ev
, Iv
} },
2463 { "adcQ", { Ev
, Iv
} },
2464 { "sbbQ", { Ev
, Iv
} },
2465 { "andQ", { Ev
, Iv
} },
2466 { "subQ", { Ev
, Iv
} },
2467 { "xorQ", { Ev
, Iv
} },
2468 { "cmpQ", { Ev
, Iv
} },
2472 { "addQ", { Ev
, sIb
} },
2473 { "orQ", { Ev
, sIb
} },
2474 { "adcQ", { Ev
, sIb
} },
2475 { "sbbQ", { Ev
, sIb
} },
2476 { "andQ", { Ev
, sIb
} },
2477 { "subQ", { Ev
, sIb
} },
2478 { "xorQ", { Ev
, sIb
} },
2479 { "cmpQ", { Ev
, sIb
} },
2483 { "popU", { stackEv
} },
2484 { XOP_8F_TABLE (XOP_09
) },
2488 { XOP_8F_TABLE (XOP_09
) },
2492 { "rolA", { Eb
, Ib
} },
2493 { "rorA", { Eb
, Ib
} },
2494 { "rclA", { Eb
, Ib
} },
2495 { "rcrA", { Eb
, Ib
} },
2496 { "shlA", { Eb
, Ib
} },
2497 { "shrA", { Eb
, Ib
} },
2499 { "sarA", { Eb
, Ib
} },
2503 { "rolQ", { Ev
, Ib
} },
2504 { "rorQ", { Ev
, Ib
} },
2505 { "rclQ", { Ev
, Ib
} },
2506 { "rcrQ", { Ev
, Ib
} },
2507 { "shlQ", { Ev
, Ib
} },
2508 { "shrQ", { Ev
, Ib
} },
2510 { "sarQ", { Ev
, Ib
} },
2514 { "movA", { Eb
, Ib
} },
2518 { "movQ", { Ev
, Iv
} },
2522 { "rolA", { Eb
, I1
} },
2523 { "rorA", { Eb
, I1
} },
2524 { "rclA", { Eb
, I1
} },
2525 { "rcrA", { Eb
, I1
} },
2526 { "shlA", { Eb
, I1
} },
2527 { "shrA", { Eb
, I1
} },
2529 { "sarA", { Eb
, I1
} },
2533 { "rolQ", { Ev
, I1
} },
2534 { "rorQ", { Ev
, I1
} },
2535 { "rclQ", { Ev
, I1
} },
2536 { "rcrQ", { Ev
, I1
} },
2537 { "shlQ", { Ev
, I1
} },
2538 { "shrQ", { Ev
, I1
} },
2540 { "sarQ", { Ev
, I1
} },
2544 { "rolA", { Eb
, CL
} },
2545 { "rorA", { Eb
, CL
} },
2546 { "rclA", { Eb
, CL
} },
2547 { "rcrA", { Eb
, CL
} },
2548 { "shlA", { Eb
, CL
} },
2549 { "shrA", { Eb
, CL
} },
2551 { "sarA", { Eb
, CL
} },
2555 { "rolQ", { Ev
, CL
} },
2556 { "rorQ", { Ev
, CL
} },
2557 { "rclQ", { Ev
, CL
} },
2558 { "rcrQ", { Ev
, CL
} },
2559 { "shlQ", { Ev
, CL
} },
2560 { "shrQ", { Ev
, CL
} },
2562 { "sarQ", { Ev
, CL
} },
2566 { "testA", { Eb
, Ib
} },
2570 { "mulA", { Eb
} }, /* Don't print the implicit %al register, */
2571 { "imulA", { Eb
} }, /* to distinguish these opcodes from other */
2572 { "divA", { Eb
} }, /* mul/imul opcodes. Do the same for div */
2573 { "idivA", { Eb
} }, /* and idiv for consistency. */
2577 { "testQ", { Ev
, Iv
} },
2581 { "mulQ", { Ev
} }, /* Don't print the implicit register. */
2582 { "imulQ", { Ev
} },
2584 { "idivQ", { Ev
} },
2595 { "call{T|}", { indirEv
} },
2596 { "Jcall{T|}", { indirEp
} },
2597 { "jmp{T|}", { indirEv
} },
2598 { "Jjmp{T|}", { indirEp
} },
2599 { "pushU", { stackEv
} },
2604 { "sldtD", { Sv
} },
2615 { MOD_TABLE (MOD_0F01_REG_0
) },
2616 { MOD_TABLE (MOD_0F01_REG_1
) },
2617 { MOD_TABLE (MOD_0F01_REG_2
) },
2618 { MOD_TABLE (MOD_0F01_REG_3
) },
2619 { "smswD", { Sv
} },
2622 { MOD_TABLE (MOD_0F01_REG_7
) },
2626 { "prefetch", { Mb
} },
2627 { "prefetchw", { Mb
} },
2631 { MOD_TABLE (MOD_0F18_REG_0
) },
2632 { MOD_TABLE (MOD_0F18_REG_1
) },
2633 { MOD_TABLE (MOD_0F18_REG_2
) },
2634 { MOD_TABLE (MOD_0F18_REG_3
) },
2640 { MOD_TABLE (MOD_0F71_REG_2
) },
2642 { MOD_TABLE (MOD_0F71_REG_4
) },
2644 { MOD_TABLE (MOD_0F71_REG_6
) },
2650 { MOD_TABLE (MOD_0F72_REG_2
) },
2652 { MOD_TABLE (MOD_0F72_REG_4
) },
2654 { MOD_TABLE (MOD_0F72_REG_6
) },
2660 { MOD_TABLE (MOD_0F73_REG_2
) },
2661 { MOD_TABLE (MOD_0F73_REG_3
) },
2664 { MOD_TABLE (MOD_0F73_REG_6
) },
2665 { MOD_TABLE (MOD_0F73_REG_7
) },
2669 { "montmul", { { OP_0f07
, 0 } } },
2670 { "xsha1", { { OP_0f07
, 0 } } },
2671 { "xsha256", { { OP_0f07
, 0 } } },
2675 { "xstore-rng", { { OP_0f07
, 0 } } },
2676 { "xcrypt-ecb", { { OP_0f07
, 0 } } },
2677 { "xcrypt-cbc", { { OP_0f07
, 0 } } },
2678 { "xcrypt-ctr", { { OP_0f07
, 0 } } },
2679 { "xcrypt-cfb", { { OP_0f07
, 0 } } },
2680 { "xcrypt-ofb", { { OP_0f07
, 0 } } },
2684 { MOD_TABLE (MOD_0FAE_REG_0
) },
2685 { MOD_TABLE (MOD_0FAE_REG_1
) },
2686 { MOD_TABLE (MOD_0FAE_REG_2
) },
2687 { MOD_TABLE (MOD_0FAE_REG_3
) },
2688 { MOD_TABLE (MOD_0FAE_REG_4
) },
2689 { MOD_TABLE (MOD_0FAE_REG_5
) },
2690 { MOD_TABLE (MOD_0FAE_REG_6
) },
2691 { MOD_TABLE (MOD_0FAE_REG_7
) },
2699 { "btQ", { Ev
, Ib
} },
2700 { "btsQ", { Ev
, Ib
} },
2701 { "btrQ", { Ev
, Ib
} },
2702 { "btcQ", { Ev
, Ib
} },
2707 { "cmpxchg8b", { { CMPXCHG8B_Fixup
, q_mode
} } },
2712 { MOD_TABLE (MOD_0FC7_REG_6
) },
2713 { MOD_TABLE (MOD_0FC7_REG_7
) },
2719 { MOD_TABLE (MOD_VEX_0F71_REG_2
) },
2721 { MOD_TABLE (MOD_VEX_0F71_REG_4
) },
2723 { MOD_TABLE (MOD_VEX_0F71_REG_6
) },
2729 { MOD_TABLE (MOD_VEX_0F72_REG_2
) },
2731 { MOD_TABLE (MOD_VEX_0F72_REG_4
) },
2733 { MOD_TABLE (MOD_VEX_0F72_REG_6
) },
2739 { MOD_TABLE (MOD_VEX_0F73_REG_2
) },
2740 { MOD_TABLE (MOD_VEX_0F73_REG_3
) },
2743 { MOD_TABLE (MOD_VEX_0F73_REG_6
) },
2744 { MOD_TABLE (MOD_VEX_0F73_REG_7
) },
2750 { MOD_TABLE (MOD_VEX_0FAE_REG_2
) },
2751 { MOD_TABLE (MOD_VEX_0FAE_REG_3
) },
2755 { "llwpcb", { { OP_LWPCB_E
, 0 } } },
2756 { "slwpcb", { { OP_LWPCB_E
, 0 } } },
2760 { "lwpins", { { OP_LWP_E
, 0 }, Ed
, Iq
} },
2761 { "lwpval", { { OP_LWP_E
, 0 }, Ed
, Iq
} },
2765 static const struct dis386 prefix_table
[][4] = {
2768 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} } },
2769 { "pause", { XX
} },
2770 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} } },
2775 { "movups", { XM
, EXx
} },
2776 { "movss", { XM
, EXd
} },
2777 { "movupd", { XM
, EXx
} },
2778 { "movsd", { XM
, EXq
} },
2783 { "movups", { EXxS
, XM
} },
2784 { "movss", { EXdS
, XM
} },
2785 { "movupd", { EXxS
, XM
} },
2786 { "movsd", { EXqS
, XM
} },
2791 { MOD_TABLE (MOD_0F12_PREFIX_0
) },
2792 { "movsldup", { XM
, EXx
} },
2793 { "movlpd", { XM
, EXq
} },
2794 { "movddup", { XM
, EXq
} },
2799 { MOD_TABLE (MOD_0F16_PREFIX_0
) },
2800 { "movshdup", { XM
, EXx
} },
2801 { "movhpd", { XM
, EXq
} },
2806 { "cvtpi2ps", { XM
, EMCq
} },
2807 { "cvtsi2ss%LQ", { XM
, Ev
} },
2808 { "cvtpi2pd", { XM
, EMCq
} },
2809 { "cvtsi2sd%LQ", { XM
, Ev
} },
2814 { MOD_TABLE (MOD_0F2B_PREFIX_0
) },
2815 { MOD_TABLE (MOD_0F2B_PREFIX_1
) },
2816 { MOD_TABLE (MOD_0F2B_PREFIX_2
) },
2817 { MOD_TABLE (MOD_0F2B_PREFIX_3
) },
2822 { "cvttps2pi", { MXC
, EXq
} },
2823 { "cvttss2siY", { Gv
, EXd
} },
2824 { "cvttpd2pi", { MXC
, EXx
} },
2825 { "cvttsd2siY", { Gv
, EXq
} },
2830 { "cvtps2pi", { MXC
, EXq
} },
2831 { "cvtss2siY", { Gv
, EXd
} },
2832 { "cvtpd2pi", { MXC
, EXx
} },
2833 { "cvtsd2siY", { Gv
, EXq
} },
2838 { "ucomiss",{ XM
, EXd
} },
2840 { "ucomisd",{ XM
, EXq
} },
2845 { "comiss", { XM
, EXd
} },
2847 { "comisd", { XM
, EXq
} },
2852 { "sqrtps", { XM
, EXx
} },
2853 { "sqrtss", { XM
, EXd
} },
2854 { "sqrtpd", { XM
, EXx
} },
2855 { "sqrtsd", { XM
, EXq
} },
2860 { "rsqrtps",{ XM
, EXx
} },
2861 { "rsqrtss",{ XM
, EXd
} },
2866 { "rcpps", { XM
, EXx
} },
2867 { "rcpss", { XM
, EXd
} },
2872 { "addps", { XM
, EXx
} },
2873 { "addss", { XM
, EXd
} },
2874 { "addpd", { XM
, EXx
} },
2875 { "addsd", { XM
, EXq
} },
2880 { "mulps", { XM
, EXx
} },
2881 { "mulss", { XM
, EXd
} },
2882 { "mulpd", { XM
, EXx
} },
2883 { "mulsd", { XM
, EXq
} },
2888 { "cvtps2pd", { XM
, EXq
} },
2889 { "cvtss2sd", { XM
, EXd
} },
2890 { "cvtpd2ps", { XM
, EXx
} },
2891 { "cvtsd2ss", { XM
, EXq
} },
2896 { "cvtdq2ps", { XM
, EXx
} },
2897 { "cvttps2dq", { XM
, EXx
} },
2898 { "cvtps2dq", { XM
, EXx
} },
2903 { "subps", { XM
, EXx
} },
2904 { "subss", { XM
, EXd
} },
2905 { "subpd", { XM
, EXx
} },
2906 { "subsd", { XM
, EXq
} },
2911 { "minps", { XM
, EXx
} },
2912 { "minss", { XM
, EXd
} },
2913 { "minpd", { XM
, EXx
} },
2914 { "minsd", { XM
, EXq
} },
2919 { "divps", { XM
, EXx
} },
2920 { "divss", { XM
, EXd
} },
2921 { "divpd", { XM
, EXx
} },
2922 { "divsd", { XM
, EXq
} },
2927 { "maxps", { XM
, EXx
} },
2928 { "maxss", { XM
, EXd
} },
2929 { "maxpd", { XM
, EXx
} },
2930 { "maxsd", { XM
, EXq
} },
2935 { "punpcklbw",{ MX
, EMd
} },
2937 { "punpcklbw",{ MX
, EMx
} },
2942 { "punpcklwd",{ MX
, EMd
} },
2944 { "punpcklwd",{ MX
, EMx
} },
2949 { "punpckldq",{ MX
, EMd
} },
2951 { "punpckldq",{ MX
, EMx
} },
2958 { "punpcklqdq", { XM
, EXx
} },
2965 { "punpckhqdq", { XM
, EXx
} },
2970 { "movq", { MX
, EM
} },
2971 { "movdqu", { XM
, EXx
} },
2972 { "movdqa", { XM
, EXx
} },
2977 { "pshufw", { MX
, EM
, Ib
} },
2978 { "pshufhw",{ XM
, EXx
, Ib
} },
2979 { "pshufd", { XM
, EXx
, Ib
} },
2980 { "pshuflw",{ XM
, EXx
, Ib
} },
2983 /* PREFIX_0F73_REG_3 */
2987 { "psrldq", { XS
, Ib
} },
2990 /* PREFIX_0F73_REG_7 */
2994 { "pslldq", { XS
, Ib
} },
2999 {"vmread", { Em
, Gm
} },
3001 {"extrq", { XS
, Ib
, Ib
} },
3002 {"insertq", { XM
, XS
, Ib
, Ib
} },
3007 {"vmwrite", { Gm
, Em
} },
3009 {"extrq", { XM
, XS
} },
3010 {"insertq", { XM
, XS
} },
3017 { "haddpd", { XM
, EXx
} },
3018 { "haddps", { XM
, EXx
} },
3025 { "hsubpd", { XM
, EXx
} },
3026 { "hsubps", { XM
, EXx
} },
3031 { "movK", { Edq
, MX
} },
3032 { "movq", { XM
, EXq
} },
3033 { "movK", { Edq
, XM
} },
3038 { "movq", { EMS
, MX
} },
3039 { "movdqu", { EXxS
, XM
} },
3040 { "movdqa", { EXxS
, XM
} },
3043 /* PREFIX_0FAE_REG_0 */
3046 { "rdfsbase", { Ev
} },
3049 /* PREFIX_0FAE_REG_1 */
3052 { "rdgsbase", { Ev
} },
3055 /* PREFIX_0FAE_REG_2 */
3058 { "wrfsbase", { Ev
} },
3061 /* PREFIX_0FAE_REG_3 */
3064 { "wrgsbase", { Ev
} },
3070 { "popcntS", { Gv
, Ev
} },
3075 { "bsrS", { Gv
, Ev
} },
3076 { "lzcntS", { Gv
, Ev
} },
3077 { "bsrS", { Gv
, Ev
} },
3082 { "cmpps", { XM
, EXx
, CMP
} },
3083 { "cmpss", { XM
, EXd
, CMP
} },
3084 { "cmppd", { XM
, EXx
, CMP
} },
3085 { "cmpsd", { XM
, EXq
, CMP
} },
3090 { "movntiS", { Ma
, Gv
} },
3093 /* PREFIX_0FC7_REG_6 */
3095 { "vmptrld",{ Mq
} },
3096 { "vmxon", { Mq
} },
3097 { "vmclear",{ Mq
} },
3104 { "addsubpd", { XM
, EXx
} },
3105 { "addsubps", { XM
, EXx
} },
3111 { "movq2dq",{ XM
, MS
} },
3112 { "movq", { EXqS
, XM
} },
3113 { "movdq2q",{ MX
, XS
} },
3119 { "cvtdq2pd", { XM
, EXq
} },
3120 { "cvttpd2dq", { XM
, EXx
} },
3121 { "cvtpd2dq", { XM
, EXx
} },
3126 { "movntq", { Mq
, MX
} },
3128 { MOD_TABLE (MOD_0FE7_PREFIX_2
) },
3136 { MOD_TABLE (MOD_0FF0_PREFIX_3
) },
3141 { "maskmovq", { MX
, MS
} },
3143 { "maskmovdqu", { XM
, XS
} },
3150 { "pblendvb", { XM
, EXx
, XMM0
} },
3157 { "blendvps", { XM
, EXx
, XMM0
} },
3164 { "blendvpd", { XM
, EXx
, XMM0
} },
3171 { "ptest", { XM
, EXx
} },
3178 { "pmovsxbw", { XM
, EXq
} },
3185 { "pmovsxbd", { XM
, EXd
} },
3192 { "pmovsxbq", { XM
, EXw
} },
3199 { "pmovsxwd", { XM
, EXq
} },
3206 { "pmovsxwq", { XM
, EXd
} },
3213 { "pmovsxdq", { XM
, EXq
} },
3220 { "pmuldq", { XM
, EXx
} },
3227 { "pcmpeqq", { XM
, EXx
} },
3234 { MOD_TABLE (MOD_0F382A_PREFIX_2
) },
3241 { "packusdw", { XM
, EXx
} },
3248 { "pmovzxbw", { XM
, EXq
} },
3255 { "pmovzxbd", { XM
, EXd
} },
3262 { "pmovzxbq", { XM
, EXw
} },
3269 { "pmovzxwd", { XM
, EXq
} },
3276 { "pmovzxwq", { XM
, EXd
} },
3283 { "pmovzxdq", { XM
, EXq
} },
3290 { "pcmpgtq", { XM
, EXx
} },
3297 { "pminsb", { XM
, EXx
} },
3304 { "pminsd", { XM
, EXx
} },
3311 { "pminuw", { XM
, EXx
} },
3318 { "pminud", { XM
, EXx
} },
3325 { "pmaxsb", { XM
, EXx
} },
3332 { "pmaxsd", { XM
, EXx
} },
3339 { "pmaxuw", { XM
, EXx
} },
3346 { "pmaxud", { XM
, EXx
} },
3353 { "pmulld", { XM
, EXx
} },
3360 { "phminposuw", { XM
, EXx
} },
3367 { "invept", { Gm
, Mo
} },
3374 { "invvpid", { Gm
, Mo
} },
3381 { "aesimc", { XM
, EXx
} },
3388 { "aesenc", { XM
, EXx
} },
3395 { "aesenclast", { XM
, EXx
} },
3402 { "aesdec", { XM
, EXx
} },
3409 { "aesdeclast", { XM
, EXx
} },
3414 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} } },
3416 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} } },
3417 { "crc32", { Gdq
, { CRC32_Fixup
, b_mode
} } },
3422 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
} },
3424 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
} },
3425 { "crc32", { Gdq
, { CRC32_Fixup
, v_mode
} } },
3432 { "roundps", { XM
, EXx
, Ib
} },
3439 { "roundpd", { XM
, EXx
, Ib
} },
3446 { "roundss", { XM
, EXd
, Ib
} },
3453 { "roundsd", { XM
, EXq
, Ib
} },
3460 { "blendps", { XM
, EXx
, Ib
} },
3467 { "blendpd", { XM
, EXx
, Ib
} },
3474 { "pblendw", { XM
, EXx
, Ib
} },
3481 { "pextrb", { Edqb
, XM
, Ib
} },
3488 { "pextrw", { Edqw
, XM
, Ib
} },
3495 { "pextrK", { Edq
, XM
, Ib
} },
3502 { "extractps", { Edqd
, XM
, Ib
} },
3509 { "pinsrb", { XM
, Edqb
, Ib
} },
3516 { "insertps", { XM
, EXd
, Ib
} },
3523 { "pinsrK", { XM
, Edq
, Ib
} },
3530 { "dpps", { XM
, EXx
, Ib
} },
3537 { "dppd", { XM
, EXx
, Ib
} },
3544 { "mpsadbw", { XM
, EXx
, Ib
} },
3551 { "pclmulqdq", { XM
, EXx
, PCLMUL
} },
3558 { "pcmpestrm", { XM
, EXx
, Ib
} },
3565 { "pcmpestri", { XM
, EXx
, Ib
} },
3572 { "pcmpistrm", { XM
, EXx
, Ib
} },
3579 { "pcmpistri", { XM
, EXx
, Ib
} },
3586 { "aeskeygenassist", { XM
, EXx
, Ib
} },
3589 /* PREFIX_VEX_0F10 */
3591 { VEX_W_TABLE (VEX_W_0F10_P_0
) },
3592 { VEX_LEN_TABLE (VEX_LEN_0F10_P_1
) },
3593 { VEX_W_TABLE (VEX_W_0F10_P_2
) },
3594 { VEX_LEN_TABLE (VEX_LEN_0F10_P_3
) },
3597 /* PREFIX_VEX_0F11 */
3599 { VEX_W_TABLE (VEX_W_0F11_P_0
) },
3600 { VEX_LEN_TABLE (VEX_LEN_0F11_P_1
) },
3601 { VEX_W_TABLE (VEX_W_0F11_P_2
) },
3602 { VEX_LEN_TABLE (VEX_LEN_0F11_P_3
) },
3605 /* PREFIX_VEX_0F12 */
3607 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0
) },
3608 { VEX_W_TABLE (VEX_W_0F12_P_1
) },
3609 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2
) },
3610 { VEX_W_TABLE (VEX_W_0F12_P_3
) },
3613 /* PREFIX_VEX_0F16 */
3615 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0
) },
3616 { VEX_W_TABLE (VEX_W_0F16_P_1
) },
3617 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2
) },
3620 /* PREFIX_VEX_0F2A */
3623 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1
) },
3625 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3
) },
3628 /* PREFIX_VEX_0F2C */
3631 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1
) },
3633 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3
) },
3636 /* PREFIX_VEX_0F2D */
3639 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1
) },
3641 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3
) },
3644 /* PREFIX_VEX_0F2E */
3646 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0
) },
3648 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2
) },
3651 /* PREFIX_VEX_0F2F */
3653 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0
) },
3655 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2
) },
3658 /* PREFIX_VEX_0F51 */
3660 { VEX_W_TABLE (VEX_W_0F51_P_0
) },
3661 { VEX_LEN_TABLE (VEX_LEN_0F51_P_1
) },
3662 { VEX_W_TABLE (VEX_W_0F51_P_2
) },
3663 { VEX_LEN_TABLE (VEX_LEN_0F51_P_3
) },
3666 /* PREFIX_VEX_0F52 */
3668 { VEX_W_TABLE (VEX_W_0F52_P_0
) },
3669 { VEX_LEN_TABLE (VEX_LEN_0F52_P_1
) },
3672 /* PREFIX_VEX_0F53 */
3674 { VEX_W_TABLE (VEX_W_0F53_P_0
) },
3675 { VEX_LEN_TABLE (VEX_LEN_0F53_P_1
) },
3678 /* PREFIX_VEX_0F58 */
3680 { VEX_W_TABLE (VEX_W_0F58_P_0
) },
3681 { VEX_LEN_TABLE (VEX_LEN_0F58_P_1
) },
3682 { VEX_W_TABLE (VEX_W_0F58_P_2
) },
3683 { VEX_LEN_TABLE (VEX_LEN_0F58_P_3
) },
3686 /* PREFIX_VEX_0F59 */
3688 { VEX_W_TABLE (VEX_W_0F59_P_0
) },
3689 { VEX_LEN_TABLE (VEX_LEN_0F59_P_1
) },
3690 { VEX_W_TABLE (VEX_W_0F59_P_2
) },
3691 { VEX_LEN_TABLE (VEX_LEN_0F59_P_3
) },
3694 /* PREFIX_VEX_0F5A */
3696 { VEX_W_TABLE (VEX_W_0F5A_P_0
) },
3697 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1
) },
3698 { "vcvtpd2ps%XY", { XMM
, EXx
} },
3699 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3
) },
3702 /* PREFIX_VEX_0F5B */
3704 { VEX_W_TABLE (VEX_W_0F5B_P_0
) },
3705 { VEX_W_TABLE (VEX_W_0F5B_P_1
) },
3706 { VEX_W_TABLE (VEX_W_0F5B_P_2
) },
3709 /* PREFIX_VEX_0F5C */
3711 { VEX_W_TABLE (VEX_W_0F5C_P_0
) },
3712 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1
) },
3713 { VEX_W_TABLE (VEX_W_0F5C_P_2
) },
3714 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3
) },
3717 /* PREFIX_VEX_0F5D */
3719 { VEX_W_TABLE (VEX_W_0F5D_P_0
) },
3720 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1
) },
3721 { VEX_W_TABLE (VEX_W_0F5D_P_2
) },
3722 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3
) },
3725 /* PREFIX_VEX_0F5E */
3727 { VEX_W_TABLE (VEX_W_0F5E_P_0
) },
3728 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1
) },
3729 { VEX_W_TABLE (VEX_W_0F5E_P_2
) },
3730 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3
) },
3733 /* PREFIX_VEX_0F5F */
3735 { VEX_W_TABLE (VEX_W_0F5F_P_0
) },
3736 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1
) },
3737 { VEX_W_TABLE (VEX_W_0F5F_P_2
) },
3738 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3
) },
3741 /* PREFIX_VEX_0F60 */
3745 { VEX_LEN_TABLE (VEX_LEN_0F60_P_2
) },
3748 /* PREFIX_VEX_0F61 */
3752 { VEX_LEN_TABLE (VEX_LEN_0F61_P_2
) },
3755 /* PREFIX_VEX_0F62 */
3759 { VEX_LEN_TABLE (VEX_LEN_0F62_P_2
) },
3762 /* PREFIX_VEX_0F63 */
3766 { VEX_LEN_TABLE (VEX_LEN_0F63_P_2
) },
3769 /* PREFIX_VEX_0F64 */
3773 { VEX_LEN_TABLE (VEX_LEN_0F64_P_2
) },
3776 /* PREFIX_VEX_0F65 */
3780 { VEX_LEN_TABLE (VEX_LEN_0F65_P_2
) },
3783 /* PREFIX_VEX_0F66 */
3787 { VEX_LEN_TABLE (VEX_LEN_0F66_P_2
) },
3790 /* PREFIX_VEX_0F67 */
3794 { VEX_LEN_TABLE (VEX_LEN_0F67_P_2
) },
3797 /* PREFIX_VEX_0F68 */
3801 { VEX_LEN_TABLE (VEX_LEN_0F68_P_2
) },
3804 /* PREFIX_VEX_0F69 */
3808 { VEX_LEN_TABLE (VEX_LEN_0F69_P_2
) },
3811 /* PREFIX_VEX_0F6A */
3815 { VEX_LEN_TABLE (VEX_LEN_0F6A_P_2
) },
3818 /* PREFIX_VEX_0F6B */
3822 { VEX_LEN_TABLE (VEX_LEN_0F6B_P_2
) },
3825 /* PREFIX_VEX_0F6C */
3829 { VEX_LEN_TABLE (VEX_LEN_0F6C_P_2
) },
3832 /* PREFIX_VEX_0F6D */
3836 { VEX_LEN_TABLE (VEX_LEN_0F6D_P_2
) },
3839 /* PREFIX_VEX_0F6E */
3843 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2
) },
3846 /* PREFIX_VEX_0F6F */
3849 { VEX_W_TABLE (VEX_W_0F6F_P_1
) },
3850 { VEX_W_TABLE (VEX_W_0F6F_P_2
) },
3853 /* PREFIX_VEX_0F70 */
3856 { VEX_LEN_TABLE (VEX_LEN_0F70_P_1
) },
3857 { VEX_LEN_TABLE (VEX_LEN_0F70_P_2
) },
3858 { VEX_LEN_TABLE (VEX_LEN_0F70_P_3
) },
3861 /* PREFIX_VEX_0F71_REG_2 */
3865 { VEX_LEN_TABLE (VEX_LEN_0F71_R_2_P_2
) },
3868 /* PREFIX_VEX_0F71_REG_4 */
3872 { VEX_LEN_TABLE (VEX_LEN_0F71_R_4_P_2
) },
3875 /* PREFIX_VEX_0F71_REG_6 */
3879 { VEX_LEN_TABLE (VEX_LEN_0F71_R_6_P_2
) },
3882 /* PREFIX_VEX_0F72_REG_2 */
3886 { VEX_LEN_TABLE (VEX_LEN_0F72_R_2_P_2
) },
3889 /* PREFIX_VEX_0F72_REG_4 */
3893 { VEX_LEN_TABLE (VEX_LEN_0F72_R_4_P_2
) },
3896 /* PREFIX_VEX_0F72_REG_6 */
3900 { VEX_LEN_TABLE (VEX_LEN_0F72_R_6_P_2
) },
3903 /* PREFIX_VEX_0F73_REG_2 */
3907 { VEX_LEN_TABLE (VEX_LEN_0F73_R_2_P_2
) },
3910 /* PREFIX_VEX_0F73_REG_3 */
3914 { VEX_LEN_TABLE (VEX_LEN_0F73_R_3_P_2
) },
3917 /* PREFIX_VEX_0F73_REG_6 */
3921 { VEX_LEN_TABLE (VEX_LEN_0F73_R_6_P_2
) },
3924 /* PREFIX_VEX_0F73_REG_7 */
3928 { VEX_LEN_TABLE (VEX_LEN_0F73_R_7_P_2
) },
3931 /* PREFIX_VEX_0F74 */
3935 { VEX_LEN_TABLE (VEX_LEN_0F74_P_2
) },
3938 /* PREFIX_VEX_0F75 */
3942 { VEX_LEN_TABLE (VEX_LEN_0F75_P_2
) },
3945 /* PREFIX_VEX_0F76 */
3949 { VEX_LEN_TABLE (VEX_LEN_0F76_P_2
) },
3952 /* PREFIX_VEX_0F77 */
3954 { VEX_W_TABLE (VEX_W_0F77_P_0
) },
3957 /* PREFIX_VEX_0F7C */
3961 { VEX_W_TABLE (VEX_W_0F7C_P_2
) },
3962 { VEX_W_TABLE (VEX_W_0F7C_P_3
) },
3965 /* PREFIX_VEX_0F7D */
3969 { VEX_W_TABLE (VEX_W_0F7D_P_2
) },
3970 { VEX_W_TABLE (VEX_W_0F7D_P_3
) },
3973 /* PREFIX_VEX_0F7E */
3976 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1
) },
3977 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2
) },
3980 /* PREFIX_VEX_0F7F */
3983 { VEX_W_TABLE (VEX_W_0F7F_P_1
) },
3984 { VEX_W_TABLE (VEX_W_0F7F_P_2
) },
3987 /* PREFIX_VEX_0FC2 */
3989 { VEX_W_TABLE (VEX_W_0FC2_P_0
) },
3990 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1
) },
3991 { VEX_W_TABLE (VEX_W_0FC2_P_2
) },
3992 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3
) },
3995 /* PREFIX_VEX_0FC4 */
3999 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2
) },
4002 /* PREFIX_VEX_0FC5 */
4006 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2
) },
4009 /* PREFIX_VEX_0FD0 */
4013 { VEX_W_TABLE (VEX_W_0FD0_P_2
) },
4014 { VEX_W_TABLE (VEX_W_0FD0_P_3
) },
4017 /* PREFIX_VEX_0FD1 */
4021 { VEX_LEN_TABLE (VEX_LEN_0FD1_P_2
) },
4024 /* PREFIX_VEX_0FD2 */
4028 { VEX_LEN_TABLE (VEX_LEN_0FD2_P_2
) },
4031 /* PREFIX_VEX_0FD3 */
4035 { VEX_LEN_TABLE (VEX_LEN_0FD3_P_2
) },
4038 /* PREFIX_VEX_0FD4 */
4042 { VEX_LEN_TABLE (VEX_LEN_0FD4_P_2
) },
4045 /* PREFIX_VEX_0FD5 */
4049 { VEX_LEN_TABLE (VEX_LEN_0FD5_P_2
) },
4052 /* PREFIX_VEX_0FD6 */
4056 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2
) },
4059 /* PREFIX_VEX_0FD7 */
4063 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2
) },
4066 /* PREFIX_VEX_0FD8 */
4070 { VEX_LEN_TABLE (VEX_LEN_0FD8_P_2
) },
4073 /* PREFIX_VEX_0FD9 */
4077 { VEX_LEN_TABLE (VEX_LEN_0FD9_P_2
) },
4080 /* PREFIX_VEX_0FDA */
4084 { VEX_LEN_TABLE (VEX_LEN_0FDA_P_2
) },
4087 /* PREFIX_VEX_0FDB */
4091 { VEX_LEN_TABLE (VEX_LEN_0FDB_P_2
) },
4094 /* PREFIX_VEX_0FDC */
4098 { VEX_LEN_TABLE (VEX_LEN_0FDC_P_2
) },
4101 /* PREFIX_VEX_0FDD */
4105 { VEX_LEN_TABLE (VEX_LEN_0FDD_P_2
) },
4108 /* PREFIX_VEX_0FDE */
4112 { VEX_LEN_TABLE (VEX_LEN_0FDE_P_2
) },
4115 /* PREFIX_VEX_0FDF */
4119 { VEX_LEN_TABLE (VEX_LEN_0FDF_P_2
) },
4122 /* PREFIX_VEX_0FE0 */
4126 { VEX_LEN_TABLE (VEX_LEN_0FE0_P_2
) },
4129 /* PREFIX_VEX_0FE1 */
4133 { VEX_LEN_TABLE (VEX_LEN_0FE1_P_2
) },
4136 /* PREFIX_VEX_0FE2 */
4140 { VEX_LEN_TABLE (VEX_LEN_0FE2_P_2
) },
4143 /* PREFIX_VEX_0FE3 */
4147 { VEX_LEN_TABLE (VEX_LEN_0FE3_P_2
) },
4150 /* PREFIX_VEX_0FE4 */
4154 { VEX_LEN_TABLE (VEX_LEN_0FE4_P_2
) },
4157 /* PREFIX_VEX_0FE5 */
4161 { VEX_LEN_TABLE (VEX_LEN_0FE5_P_2
) },
4164 /* PREFIX_VEX_0FE6 */
4167 { VEX_W_TABLE (VEX_W_0FE6_P_1
) },
4168 { VEX_W_TABLE (VEX_W_0FE6_P_2
) },
4169 { VEX_W_TABLE (VEX_W_0FE6_P_3
) },
4172 /* PREFIX_VEX_0FE7 */
4176 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2
) },
4179 /* PREFIX_VEX_0FE8 */
4183 { VEX_LEN_TABLE (VEX_LEN_0FE8_P_2
) },
4186 /* PREFIX_VEX_0FE9 */
4190 { VEX_LEN_TABLE (VEX_LEN_0FE9_P_2
) },
4193 /* PREFIX_VEX_0FEA */
4197 { VEX_LEN_TABLE (VEX_LEN_0FEA_P_2
) },
4200 /* PREFIX_VEX_0FEB */
4204 { VEX_LEN_TABLE (VEX_LEN_0FEB_P_2
) },
4207 /* PREFIX_VEX_0FEC */
4211 { VEX_LEN_TABLE (VEX_LEN_0FEC_P_2
) },
4214 /* PREFIX_VEX_0FED */
4218 { VEX_LEN_TABLE (VEX_LEN_0FED_P_2
) },
4221 /* PREFIX_VEX_0FEE */
4225 { VEX_LEN_TABLE (VEX_LEN_0FEE_P_2
) },
4228 /* PREFIX_VEX_0FEF */
4232 { VEX_LEN_TABLE (VEX_LEN_0FEF_P_2
) },
4235 /* PREFIX_VEX_0FF0 */
4240 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3
) },
4243 /* PREFIX_VEX_0FF1 */
4247 { VEX_LEN_TABLE (VEX_LEN_0FF1_P_2
) },
4250 /* PREFIX_VEX_0FF2 */
4254 { VEX_LEN_TABLE (VEX_LEN_0FF2_P_2
) },
4257 /* PREFIX_VEX_0FF3 */
4261 { VEX_LEN_TABLE (VEX_LEN_0FF3_P_2
) },
4264 /* PREFIX_VEX_0FF4 */
4268 { VEX_LEN_TABLE (VEX_LEN_0FF4_P_2
) },
4271 /* PREFIX_VEX_0FF5 */
4275 { VEX_LEN_TABLE (VEX_LEN_0FF5_P_2
) },
4278 /* PREFIX_VEX_0FF6 */
4282 { VEX_LEN_TABLE (VEX_LEN_0FF6_P_2
) },
4285 /* PREFIX_VEX_0FF7 */
4289 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2
) },
4292 /* PREFIX_VEX_0FF8 */
4296 { VEX_LEN_TABLE (VEX_LEN_0FF8_P_2
) },
4299 /* PREFIX_VEX_0FF9 */
4303 { VEX_LEN_TABLE (VEX_LEN_0FF9_P_2
) },
4306 /* PREFIX_VEX_0FFA */
4310 { VEX_LEN_TABLE (VEX_LEN_0FFA_P_2
) },
4313 /* PREFIX_VEX_0FFB */
4317 { VEX_LEN_TABLE (VEX_LEN_0FFB_P_2
) },
4320 /* PREFIX_VEX_0FFC */
4324 { VEX_LEN_TABLE (VEX_LEN_0FFC_P_2
) },
4327 /* PREFIX_VEX_0FFD */
4331 { VEX_LEN_TABLE (VEX_LEN_0FFD_P_2
) },
4334 /* PREFIX_VEX_0FFE */
4338 { VEX_LEN_TABLE (VEX_LEN_0FFE_P_2
) },
4341 /* PREFIX_VEX_0F3800 */
4345 { VEX_LEN_TABLE (VEX_LEN_0F3800_P_2
) },
4348 /* PREFIX_VEX_0F3801 */
4352 { VEX_LEN_TABLE (VEX_LEN_0F3801_P_2
) },
4355 /* PREFIX_VEX_0F3802 */
4359 { VEX_LEN_TABLE (VEX_LEN_0F3802_P_2
) },
4362 /* PREFIX_VEX_0F3803 */
4366 { VEX_LEN_TABLE (VEX_LEN_0F3803_P_2
) },
4369 /* PREFIX_VEX_0F3804 */
4373 { VEX_LEN_TABLE (VEX_LEN_0F3804_P_2
) },
4376 /* PREFIX_VEX_0F3805 */
4380 { VEX_LEN_TABLE (VEX_LEN_0F3805_P_2
) },
4383 /* PREFIX_VEX_0F3806 */
4387 { VEX_LEN_TABLE (VEX_LEN_0F3806_P_2
) },
4390 /* PREFIX_VEX_0F3807 */
4394 { VEX_LEN_TABLE (VEX_LEN_0F3807_P_2
) },
4397 /* PREFIX_VEX_0F3808 */
4401 { VEX_LEN_TABLE (VEX_LEN_0F3808_P_2
) },
4404 /* PREFIX_VEX_0F3809 */
4408 { VEX_LEN_TABLE (VEX_LEN_0F3809_P_2
) },
4411 /* PREFIX_VEX_0F380A */
4415 { VEX_LEN_TABLE (VEX_LEN_0F380A_P_2
) },
4418 /* PREFIX_VEX_0F380B */
4422 { VEX_LEN_TABLE (VEX_LEN_0F380B_P_2
) },
4425 /* PREFIX_VEX_0F380C */
4429 { VEX_W_TABLE (VEX_W_0F380C_P_2
) },
4432 /* PREFIX_VEX_0F380D */
4436 { VEX_W_TABLE (VEX_W_0F380D_P_2
) },
4439 /* PREFIX_VEX_0F380E */
4443 { VEX_W_TABLE (VEX_W_0F380E_P_2
) },
4446 /* PREFIX_VEX_0F380F */
4450 { VEX_W_TABLE (VEX_W_0F380F_P_2
) },
4453 /* PREFIX_VEX_0F3813 */
4457 { "vcvtph2ps", { XM
, EXxmmq
} },
4460 /* PREFIX_VEX_0F3817 */
4464 { VEX_W_TABLE (VEX_W_0F3817_P_2
) },
4467 /* PREFIX_VEX_0F3818 */
4471 { MOD_TABLE (MOD_VEX_0F3818_PREFIX_2
) },
4474 /* PREFIX_VEX_0F3819 */
4478 { MOD_TABLE (MOD_VEX_0F3819_PREFIX_2
) },
4481 /* PREFIX_VEX_0F381A */
4485 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2
) },
4488 /* PREFIX_VEX_0F381C */
4492 { VEX_LEN_TABLE (VEX_LEN_0F381C_P_2
) },
4495 /* PREFIX_VEX_0F381D */
4499 { VEX_LEN_TABLE (VEX_LEN_0F381D_P_2
) },
4502 /* PREFIX_VEX_0F381E */
4506 { VEX_LEN_TABLE (VEX_LEN_0F381E_P_2
) },
4509 /* PREFIX_VEX_0F3820 */
4513 { VEX_LEN_TABLE (VEX_LEN_0F3820_P_2
) },
4516 /* PREFIX_VEX_0F3821 */
4520 { VEX_LEN_TABLE (VEX_LEN_0F3821_P_2
) },
4523 /* PREFIX_VEX_0F3822 */
4527 { VEX_LEN_TABLE (VEX_LEN_0F3822_P_2
) },
4530 /* PREFIX_VEX_0F3823 */
4534 { VEX_LEN_TABLE (VEX_LEN_0F3823_P_2
) },
4537 /* PREFIX_VEX_0F3824 */
4541 { VEX_LEN_TABLE (VEX_LEN_0F3824_P_2
) },
4544 /* PREFIX_VEX_0F3825 */
4548 { VEX_LEN_TABLE (VEX_LEN_0F3825_P_2
) },
4551 /* PREFIX_VEX_0F3828 */
4555 { VEX_LEN_TABLE (VEX_LEN_0F3828_P_2
) },
4558 /* PREFIX_VEX_0F3829 */
4562 { VEX_LEN_TABLE (VEX_LEN_0F3829_P_2
) },
4565 /* PREFIX_VEX_0F382A */
4569 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2
) },
4572 /* PREFIX_VEX_0F382B */
4576 { VEX_LEN_TABLE (VEX_LEN_0F382B_P_2
) },
4579 /* PREFIX_VEX_0F382C */
4583 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2
) },
4586 /* PREFIX_VEX_0F382D */
4590 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2
) },
4593 /* PREFIX_VEX_0F382E */
4597 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2
) },
4600 /* PREFIX_VEX_0F382F */
4604 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2
) },
4607 /* PREFIX_VEX_0F3830 */
4611 { VEX_LEN_TABLE (VEX_LEN_0F3830_P_2
) },
4614 /* PREFIX_VEX_0F3831 */
4618 { VEX_LEN_TABLE (VEX_LEN_0F3831_P_2
) },
4621 /* PREFIX_VEX_0F3832 */
4625 { VEX_LEN_TABLE (VEX_LEN_0F3832_P_2
) },
4628 /* PREFIX_VEX_0F3833 */
4632 { VEX_LEN_TABLE (VEX_LEN_0F3833_P_2
) },
4635 /* PREFIX_VEX_0F3834 */
4639 { VEX_LEN_TABLE (VEX_LEN_0F3834_P_2
) },
4642 /* PREFIX_VEX_0F3835 */
4646 { VEX_LEN_TABLE (VEX_LEN_0F3835_P_2
) },
4649 /* PREFIX_VEX_0F3837 */
4653 { VEX_LEN_TABLE (VEX_LEN_0F3837_P_2
) },
4656 /* PREFIX_VEX_0F3838 */
4660 { VEX_LEN_TABLE (VEX_LEN_0F3838_P_2
) },
4663 /* PREFIX_VEX_0F3839 */
4667 { VEX_LEN_TABLE (VEX_LEN_0F3839_P_2
) },
4670 /* PREFIX_VEX_0F383A */
4674 { VEX_LEN_TABLE (VEX_LEN_0F383A_P_2
) },
4677 /* PREFIX_VEX_0F383B */
4681 { VEX_LEN_TABLE (VEX_LEN_0F383B_P_2
) },
4684 /* PREFIX_VEX_0F383C */
4688 { VEX_LEN_TABLE (VEX_LEN_0F383C_P_2
) },
4691 /* PREFIX_VEX_0F383D */
4695 { VEX_LEN_TABLE (VEX_LEN_0F383D_P_2
) },
4698 /* PREFIX_VEX_0F383E */
4702 { VEX_LEN_TABLE (VEX_LEN_0F383E_P_2
) },
4705 /* PREFIX_VEX_0F383F */
4709 { VEX_LEN_TABLE (VEX_LEN_0F383F_P_2
) },
4712 /* PREFIX_VEX_0F3840 */
4716 { VEX_LEN_TABLE (VEX_LEN_0F3840_P_2
) },
4719 /* PREFIX_VEX_0F3841 */
4723 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2
) },
4726 /* PREFIX_VEX_0F3896 */
4730 { "vfmaddsub132p%XW", { XM
, Vex
, EXx
} },
4733 /* PREFIX_VEX_0F3897 */
4737 { "vfmsubadd132p%XW", { XM
, Vex
, EXx
} },
4740 /* PREFIX_VEX_0F3898 */
4744 { "vfmadd132p%XW", { XM
, Vex
, EXx
} },
4747 /* PREFIX_VEX_0F3899 */
4751 { "vfmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
4754 /* PREFIX_VEX_0F389A */
4758 { "vfmsub132p%XW", { XM
, Vex
, EXx
} },
4761 /* PREFIX_VEX_0F389B */
4765 { "vfmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
4768 /* PREFIX_VEX_0F389C */
4772 { "vfnmadd132p%XW", { XM
, Vex
, EXx
} },
4775 /* PREFIX_VEX_0F389D */
4779 { "vfnmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
4782 /* PREFIX_VEX_0F389E */
4786 { "vfnmsub132p%XW", { XM
, Vex
, EXx
} },
4789 /* PREFIX_VEX_0F389F */
4793 { "vfnmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
4796 /* PREFIX_VEX_0F38A6 */
4800 { "vfmaddsub213p%XW", { XM
, Vex
, EXx
} },
4804 /* PREFIX_VEX_0F38A7 */
4808 { "vfmsubadd213p%XW", { XM
, Vex
, EXx
} },
4811 /* PREFIX_VEX_0F38A8 */
4815 { "vfmadd213p%XW", { XM
, Vex
, EXx
} },
4818 /* PREFIX_VEX_0F38A9 */
4822 { "vfmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
4825 /* PREFIX_VEX_0F38AA */
4829 { "vfmsub213p%XW", { XM
, Vex
, EXx
} },
4832 /* PREFIX_VEX_0F38AB */
4836 { "vfmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
4839 /* PREFIX_VEX_0F38AC */
4843 { "vfnmadd213p%XW", { XM
, Vex
, EXx
} },
4846 /* PREFIX_VEX_0F38AD */
4850 { "vfnmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
4853 /* PREFIX_VEX_0F38AE */
4857 { "vfnmsub213p%XW", { XM
, Vex
, EXx
} },
4860 /* PREFIX_VEX_0F38AF */
4864 { "vfnmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
4867 /* PREFIX_VEX_0F38B6 */
4871 { "vfmaddsub231p%XW", { XM
, Vex
, EXx
} },
4874 /* PREFIX_VEX_0F38B7 */
4878 { "vfmsubadd231p%XW", { XM
, Vex
, EXx
} },
4881 /* PREFIX_VEX_0F38B8 */
4885 { "vfmadd231p%XW", { XM
, Vex
, EXx
} },
4888 /* PREFIX_VEX_0F38B9 */
4892 { "vfmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
4895 /* PREFIX_VEX_0F38BA */
4899 { "vfmsub231p%XW", { XM
, Vex
, EXx
} },
4902 /* PREFIX_VEX_0F38BB */
4906 { "vfmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
4909 /* PREFIX_VEX_0F38BC */
4913 { "vfnmadd231p%XW", { XM
, Vex
, EXx
} },
4916 /* PREFIX_VEX_0F38BD */
4920 { "vfnmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
4923 /* PREFIX_VEX_0F38BE */
4927 { "vfnmsub231p%XW", { XM
, Vex
, EXx
} },
4930 /* PREFIX_VEX_0F38BF */
4934 { "vfnmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
4937 /* PREFIX_VEX_0F38DB */
4941 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2
) },
4944 /* PREFIX_VEX_0F38DC */
4948 { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2
) },
4951 /* PREFIX_VEX_0F38DD */
4955 { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2
) },
4958 /* PREFIX_VEX_0F38DE */
4962 { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2
) },
4965 /* PREFIX_VEX_0F38DF */
4969 { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2
) },
4972 /* PREFIX_VEX_0F3A04 */
4976 { VEX_W_TABLE (VEX_W_0F3A04_P_2
) },
4979 /* PREFIX_VEX_0F3A05 */
4983 { VEX_W_TABLE (VEX_W_0F3A05_P_2
) },
4986 /* PREFIX_VEX_0F3A06 */
4990 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2
) },
4993 /* PREFIX_VEX_0F3A08 */
4997 { VEX_W_TABLE (VEX_W_0F3A08_P_2
) },
5000 /* PREFIX_VEX_0F3A09 */
5004 { VEX_W_TABLE (VEX_W_0F3A09_P_2
) },
5007 /* PREFIX_VEX_0F3A0A */
5011 { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2
) },
5014 /* PREFIX_VEX_0F3A0B */
5018 { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2
) },
5021 /* PREFIX_VEX_0F3A0C */
5025 { VEX_W_TABLE (VEX_W_0F3A0C_P_2
) },
5028 /* PREFIX_VEX_0F3A0D */
5032 { VEX_W_TABLE (VEX_W_0F3A0D_P_2
) },
5035 /* PREFIX_VEX_0F3A0E */
5039 { VEX_LEN_TABLE (VEX_LEN_0F3A0E_P_2
) },
5042 /* PREFIX_VEX_0F3A0F */
5046 { VEX_LEN_TABLE (VEX_LEN_0F3A0F_P_2
) },
5049 /* PREFIX_VEX_0F3A14 */
5053 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2
) },
5056 /* PREFIX_VEX_0F3A15 */
5060 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2
) },
5063 /* PREFIX_VEX_0F3A16 */
5067 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2
) },
5070 /* PREFIX_VEX_0F3A17 */
5074 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2
) },
5077 /* PREFIX_VEX_0F3A18 */
5081 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2
) },
5084 /* PREFIX_VEX_0F3A19 */
5088 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2
) },
5091 /* PREFIX_VEX_0F3A1D */
5095 { "vcvtps2ph", { EXxmmq
, XM
, Ib
} },
5098 /* PREFIX_VEX_0F3A20 */
5102 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2
) },
5105 /* PREFIX_VEX_0F3A21 */
5109 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2
) },
5112 /* PREFIX_VEX_0F3A22 */
5116 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2
) },
5119 /* PREFIX_VEX_0F3A40 */
5123 { VEX_W_TABLE (VEX_W_0F3A40_P_2
) },
5126 /* PREFIX_VEX_0F3A41 */
5130 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2
) },
5133 /* PREFIX_VEX_0F3A42 */
5137 { VEX_LEN_TABLE (VEX_LEN_0F3A42_P_2
) },
5140 /* PREFIX_VEX_0F3A44 */
5144 { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2
) },
5147 /* PREFIX_VEX_0F3A48 */
5151 { VEX_W_TABLE (VEX_W_0F3A48_P_2
) },
5154 /* PREFIX_VEX_0F3A49 */
5158 { VEX_W_TABLE (VEX_W_0F3A49_P_2
) },
5161 /* PREFIX_VEX_0F3A4A */
5165 { VEX_W_TABLE (VEX_W_0F3A4A_P_2
) },
5168 /* PREFIX_VEX_0F3A4B */
5172 { VEX_W_TABLE (VEX_W_0F3A4B_P_2
) },
5175 /* PREFIX_VEX_0F3A4C */
5179 { VEX_LEN_TABLE (VEX_LEN_0F3A4C_P_2
) },
5182 /* PREFIX_VEX_0F3A5C */
5186 { "vfmaddsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5189 /* PREFIX_VEX_0F3A5D */
5193 { "vfmaddsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5196 /* PREFIX_VEX_0F3A5E */
5200 { "vfmsubaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5203 /* PREFIX_VEX_0F3A5F */
5207 { "vfmsubaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5210 /* PREFIX_VEX_0F3A60 */
5214 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2
) },
5218 /* PREFIX_VEX_0F3A61 */
5222 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2
) },
5225 /* PREFIX_VEX_0F3A62 */
5229 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2
) },
5232 /* PREFIX_VEX_0F3A63 */
5236 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2
) },
5239 /* PREFIX_VEX_0F3A68 */
5243 { "vfmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5246 /* PREFIX_VEX_0F3A69 */
5250 { "vfmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5253 /* PREFIX_VEX_0F3A6A */
5257 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2
) },
5260 /* PREFIX_VEX_0F3A6B */
5264 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2
) },
5267 /* PREFIX_VEX_0F3A6C */
5271 { "vfmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5274 /* PREFIX_VEX_0F3A6D */
5278 { "vfmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5281 /* PREFIX_VEX_0F3A6E */
5285 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2
) },
5288 /* PREFIX_VEX_0F3A6F */
5292 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2
) },
5295 /* PREFIX_VEX_0F3A78 */
5299 { "vfnmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5302 /* PREFIX_VEX_0F3A79 */
5306 { "vfnmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5309 /* PREFIX_VEX_0F3A7A */
5313 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2
) },
5316 /* PREFIX_VEX_0F3A7B */
5320 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2
) },
5323 /* PREFIX_VEX_0F3A7C */
5327 { "vfnmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5331 /* PREFIX_VEX_0F3A7D */
5335 { "vfnmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5338 /* PREFIX_VEX_0F3A7E */
5342 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2
) },
5345 /* PREFIX_VEX_0F3A7F */
5349 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2
) },
5352 /* PREFIX_VEX_0F3ADF */
5356 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2
) },
5360 static const struct dis386 x86_64_table
[][2] = {
5363 { "pushP", { es
} },
5373 { "pushP", { cs
} },
5378 { "pushP", { ss
} },
5388 { "pushP", { ds
} },
5418 { "pushaP", { XX
} },
5423 { "popaP", { XX
} },
5428 { MOD_TABLE (MOD_62_32BIT
) },
5433 { "arpl", { Ew
, Gw
} },
5434 { "movs{lq|xd}", { Gv
, Ed
} },
5439 { "ins{R|}", { Yzr
, indirDX
} },
5440 { "ins{G|}", { Yzr
, indirDX
} },
5445 { "outs{R|}", { indirDXr
, Xz
} },
5446 { "outs{G|}", { indirDXr
, Xz
} },
5451 { "Jcall{T|}", { Ap
} },
5456 { MOD_TABLE (MOD_C4_32BIT
) },
5457 { VEX_C4_TABLE (VEX_0F
) },
5462 { MOD_TABLE (MOD_C5_32BIT
) },
5463 { VEX_C5_TABLE (VEX_0F
) },
5483 { "Jjmp{T|}", { Ap
} },
5486 /* X86_64_0F01_REG_0 */
5488 { "sgdt{Q|IQ}", { M
} },
5492 /* X86_64_0F01_REG_1 */
5494 { "sidt{Q|IQ}", { M
} },
5498 /* X86_64_0F01_REG_2 */
5500 { "lgdt{Q|Q}", { M
} },
5504 /* X86_64_0F01_REG_3 */
5506 { "lidt{Q|Q}", { M
} },
5511 static const struct dis386 three_byte_table
[][256] = {
5513 /* THREE_BYTE_0F38 */
5516 { "pshufb", { MX
, EM
} },
5517 { "phaddw", { MX
, EM
} },
5518 { "phaddd", { MX
, EM
} },
5519 { "phaddsw", { MX
, EM
} },
5520 { "pmaddubsw", { MX
, EM
} },
5521 { "phsubw", { MX
, EM
} },
5522 { "phsubd", { MX
, EM
} },
5523 { "phsubsw", { MX
, EM
} },
5525 { "psignb", { MX
, EM
} },
5526 { "psignw", { MX
, EM
} },
5527 { "psignd", { MX
, EM
} },
5528 { "pmulhrsw", { MX
, EM
} },
5534 { PREFIX_TABLE (PREFIX_0F3810
) },
5538 { PREFIX_TABLE (PREFIX_0F3814
) },
5539 { PREFIX_TABLE (PREFIX_0F3815
) },
5541 { PREFIX_TABLE (PREFIX_0F3817
) },
5547 { "pabsb", { MX
, EM
} },
5548 { "pabsw", { MX
, EM
} },
5549 { "pabsd", { MX
, EM
} },
5552 { PREFIX_TABLE (PREFIX_0F3820
) },
5553 { PREFIX_TABLE (PREFIX_0F3821
) },
5554 { PREFIX_TABLE (PREFIX_0F3822
) },
5555 { PREFIX_TABLE (PREFIX_0F3823
) },
5556 { PREFIX_TABLE (PREFIX_0F3824
) },
5557 { PREFIX_TABLE (PREFIX_0F3825
) },
5561 { PREFIX_TABLE (PREFIX_0F3828
) },
5562 { PREFIX_TABLE (PREFIX_0F3829
) },
5563 { PREFIX_TABLE (PREFIX_0F382A
) },
5564 { PREFIX_TABLE (PREFIX_0F382B
) },
5570 { PREFIX_TABLE (PREFIX_0F3830
) },
5571 { PREFIX_TABLE (PREFIX_0F3831
) },
5572 { PREFIX_TABLE (PREFIX_0F3832
) },
5573 { PREFIX_TABLE (PREFIX_0F3833
) },
5574 { PREFIX_TABLE (PREFIX_0F3834
) },
5575 { PREFIX_TABLE (PREFIX_0F3835
) },
5577 { PREFIX_TABLE (PREFIX_0F3837
) },
5579 { PREFIX_TABLE (PREFIX_0F3838
) },
5580 { PREFIX_TABLE (PREFIX_0F3839
) },
5581 { PREFIX_TABLE (PREFIX_0F383A
) },
5582 { PREFIX_TABLE (PREFIX_0F383B
) },
5583 { PREFIX_TABLE (PREFIX_0F383C
) },
5584 { PREFIX_TABLE (PREFIX_0F383D
) },
5585 { PREFIX_TABLE (PREFIX_0F383E
) },
5586 { PREFIX_TABLE (PREFIX_0F383F
) },
5588 { PREFIX_TABLE (PREFIX_0F3840
) },
5589 { PREFIX_TABLE (PREFIX_0F3841
) },
5660 { PREFIX_TABLE (PREFIX_0F3880
) },
5661 { PREFIX_TABLE (PREFIX_0F3881
) },
5762 { PREFIX_TABLE (PREFIX_0F38DB
) },
5763 { PREFIX_TABLE (PREFIX_0F38DC
) },
5764 { PREFIX_TABLE (PREFIX_0F38DD
) },
5765 { PREFIX_TABLE (PREFIX_0F38DE
) },
5766 { PREFIX_TABLE (PREFIX_0F38DF
) },
5786 { PREFIX_TABLE (PREFIX_0F38F0
) },
5787 { PREFIX_TABLE (PREFIX_0F38F1
) },
5804 /* THREE_BYTE_0F3A */
5816 { PREFIX_TABLE (PREFIX_0F3A08
) },
5817 { PREFIX_TABLE (PREFIX_0F3A09
) },
5818 { PREFIX_TABLE (PREFIX_0F3A0A
) },
5819 { PREFIX_TABLE (PREFIX_0F3A0B
) },
5820 { PREFIX_TABLE (PREFIX_0F3A0C
) },
5821 { PREFIX_TABLE (PREFIX_0F3A0D
) },
5822 { PREFIX_TABLE (PREFIX_0F3A0E
) },
5823 { "palignr", { MX
, EM
, Ib
} },
5829 { PREFIX_TABLE (PREFIX_0F3A14
) },
5830 { PREFIX_TABLE (PREFIX_0F3A15
) },
5831 { PREFIX_TABLE (PREFIX_0F3A16
) },
5832 { PREFIX_TABLE (PREFIX_0F3A17
) },
5843 { PREFIX_TABLE (PREFIX_0F3A20
) },
5844 { PREFIX_TABLE (PREFIX_0F3A21
) },
5845 { PREFIX_TABLE (PREFIX_0F3A22
) },
5879 { PREFIX_TABLE (PREFIX_0F3A40
) },
5880 { PREFIX_TABLE (PREFIX_0F3A41
) },
5881 { PREFIX_TABLE (PREFIX_0F3A42
) },
5883 { PREFIX_TABLE (PREFIX_0F3A44
) },
5915 { PREFIX_TABLE (PREFIX_0F3A60
) },
5916 { PREFIX_TABLE (PREFIX_0F3A61
) },
5917 { PREFIX_TABLE (PREFIX_0F3A62
) },
5918 { PREFIX_TABLE (PREFIX_0F3A63
) },
6057 { PREFIX_TABLE (PREFIX_0F3ADF
) },
6096 /* THREE_BYTE_0F7A */
6135 { "ptest", { XX
} },
6172 { "phaddbw", { XM
, EXq
} },
6173 { "phaddbd", { XM
, EXq
} },
6174 { "phaddbq", { XM
, EXq
} },
6177 { "phaddwd", { XM
, EXq
} },
6178 { "phaddwq", { XM
, EXq
} },
6183 { "phadddq", { XM
, EXq
} },
6190 { "phaddubw", { XM
, EXq
} },
6191 { "phaddubd", { XM
, EXq
} },
6192 { "phaddubq", { XM
, EXq
} },
6195 { "phadduwd", { XM
, EXq
} },
6196 { "phadduwq", { XM
, EXq
} },
6201 { "phaddudq", { XM
, EXq
} },
6208 { "phsubbw", { XM
, EXq
} },
6209 { "phsubbd", { XM
, EXq
} },
6210 { "phsubbq", { XM
, EXq
} },
6389 static const struct dis386 xop_table
[][256] = {
6542 { "vpmacssww", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6543 { "vpmacsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6544 { "vpmacssdql", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6552 { "vpmacssdd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6553 { "vpmacssdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6560 { "vpmacsww", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6561 { "vpmacswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6562 { "vpmacsdql", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6570 { "vpmacsdd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6571 { "vpmacsdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6575 { "vpcmov", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6576 { "vpperm", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6579 { "vpmadcsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6597 { "vpmadcswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6609 { "vprotb", { XM
, Vex_2src_1
, Ib
} },
6610 { "vprotw", { XM
, Vex_2src_1
, Ib
} },
6611 { "vprotd", { XM
, Vex_2src_1
, Ib
} },
6612 { "vprotq", { XM
, Vex_2src_1
, Ib
} },
6622 { "vpcomb", { XM
, Vex128
, EXx
, Ib
} },
6623 { "vpcomw", { XM
, Vex128
, EXx
, Ib
} },
6624 { "vpcomd", { XM
, Vex128
, EXx
, Ib
} },
6625 { "vpcomq", { XM
, Vex128
, EXx
, Ib
} },
6658 { "vpcomub", { XM
, Vex128
, EXx
, Ib
} },
6659 { "vpcomuw", { XM
, Vex128
, EXx
, Ib
} },
6660 { "vpcomud", { XM
, Vex128
, EXx
, Ib
} },
6661 { "vpcomuq", { XM
, Vex128
, EXx
, Ib
} },
6704 { REG_TABLE (REG_XOP_LWPCB
) },
6828 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80
) },
6829 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81
) },
6830 { "vfrczss", { XM
, EXd
} },
6831 { "vfrczsd", { XM
, EXq
} },
6846 { "vprotb", { XM
, Vex_2src_1
, Vex_2src_2
} },
6847 { "vprotw", { XM
, Vex_2src_1
, Vex_2src_2
} },
6848 { "vprotd", { XM
, Vex_2src_1
, Vex_2src_2
} },
6849 { "vprotq", { XM
, Vex_2src_1
, Vex_2src_2
} },
6850 { "vpshlb", { XM
, Vex_2src_1
, Vex_2src_2
} },
6851 { "vpshlw", { XM
, Vex_2src_1
, Vex_2src_2
} },
6852 { "vpshld", { XM
, Vex_2src_1
, Vex_2src_2
} },
6853 { "vpshlq", { XM
, Vex_2src_1
, Vex_2src_2
} },
6855 { "vpshab", { XM
, Vex_2src_1
, Vex_2src_2
} },
6856 { "vpshaw", { XM
, Vex_2src_1
, Vex_2src_2
} },
6857 { "vpshad", { XM
, Vex_2src_1
, Vex_2src_2
} },
6858 { "vpshaq", { XM
, Vex_2src_1
, Vex_2src_2
} },
6901 { "vphaddbw", { XM
, EXxmm
} },
6902 { "vphaddbd", { XM
, EXxmm
} },
6903 { "vphaddbq", { XM
, EXxmm
} },
6906 { "vphaddwd", { XM
, EXxmm
} },
6907 { "vphaddwq", { XM
, EXxmm
} },
6912 { "vphadddq", { XM
, EXxmm
} },
6919 { "vphaddubw", { XM
, EXxmm
} },
6920 { "vphaddubd", { XM
, EXxmm
} },
6921 { "vphaddubq", { XM
, EXxmm
} },
6924 { "vphadduwd", { XM
, EXxmm
} },
6925 { "vphadduwq", { XM
, EXxmm
} },
6930 { "vphaddudq", { XM
, EXxmm
} },
6937 { "vphsubbw", { XM
, EXxmm
} },
6938 { "vphsubwd", { XM
, EXxmm
} },
6939 { "vphsubdq", { XM
, EXxmm
} },
6995 { REG_TABLE (REG_XOP_LWP
) },
7265 static const struct dis386 vex_table
[][256] = {
7287 { PREFIX_TABLE (PREFIX_VEX_0F10
) },
7288 { PREFIX_TABLE (PREFIX_VEX_0F11
) },
7289 { PREFIX_TABLE (PREFIX_VEX_0F12
) },
7290 { MOD_TABLE (MOD_VEX_0F13
) },
7291 { VEX_W_TABLE (VEX_W_0F14
) },
7292 { VEX_W_TABLE (VEX_W_0F15
) },
7293 { PREFIX_TABLE (PREFIX_VEX_0F16
) },
7294 { MOD_TABLE (MOD_VEX_0F17
) },
7314 { VEX_W_TABLE (VEX_W_0F28
) },
7315 { VEX_W_TABLE (VEX_W_0F29
) },
7316 { PREFIX_TABLE (PREFIX_VEX_0F2A
) },
7317 { MOD_TABLE (MOD_VEX_0F2B
) },
7318 { PREFIX_TABLE (PREFIX_VEX_0F2C
) },
7319 { PREFIX_TABLE (PREFIX_VEX_0F2D
) },
7320 { PREFIX_TABLE (PREFIX_VEX_0F2E
) },
7321 { PREFIX_TABLE (PREFIX_VEX_0F2F
) },
7359 { MOD_TABLE (MOD_VEX_0F50
) },
7360 { PREFIX_TABLE (PREFIX_VEX_0F51
) },
7361 { PREFIX_TABLE (PREFIX_VEX_0F52
) },
7362 { PREFIX_TABLE (PREFIX_VEX_0F53
) },
7363 { "vandpX", { XM
, Vex
, EXx
} },
7364 { "vandnpX", { XM
, Vex
, EXx
} },
7365 { "vorpX", { XM
, Vex
, EXx
} },
7366 { "vxorpX", { XM
, Vex
, EXx
} },
7368 { PREFIX_TABLE (PREFIX_VEX_0F58
) },
7369 { PREFIX_TABLE (PREFIX_VEX_0F59
) },
7370 { PREFIX_TABLE (PREFIX_VEX_0F5A
) },
7371 { PREFIX_TABLE (PREFIX_VEX_0F5B
) },
7372 { PREFIX_TABLE (PREFIX_VEX_0F5C
) },
7373 { PREFIX_TABLE (PREFIX_VEX_0F5D
) },
7374 { PREFIX_TABLE (PREFIX_VEX_0F5E
) },
7375 { PREFIX_TABLE (PREFIX_VEX_0F5F
) },
7377 { PREFIX_TABLE (PREFIX_VEX_0F60
) },
7378 { PREFIX_TABLE (PREFIX_VEX_0F61
) },
7379 { PREFIX_TABLE (PREFIX_VEX_0F62
) },
7380 { PREFIX_TABLE (PREFIX_VEX_0F63
) },
7381 { PREFIX_TABLE (PREFIX_VEX_0F64
) },
7382 { PREFIX_TABLE (PREFIX_VEX_0F65
) },
7383 { PREFIX_TABLE (PREFIX_VEX_0F66
) },
7384 { PREFIX_TABLE (PREFIX_VEX_0F67
) },
7386 { PREFIX_TABLE (PREFIX_VEX_0F68
) },
7387 { PREFIX_TABLE (PREFIX_VEX_0F69
) },
7388 { PREFIX_TABLE (PREFIX_VEX_0F6A
) },
7389 { PREFIX_TABLE (PREFIX_VEX_0F6B
) },
7390 { PREFIX_TABLE (PREFIX_VEX_0F6C
) },
7391 { PREFIX_TABLE (PREFIX_VEX_0F6D
) },
7392 { PREFIX_TABLE (PREFIX_VEX_0F6E
) },
7393 { PREFIX_TABLE (PREFIX_VEX_0F6F
) },
7395 { PREFIX_TABLE (PREFIX_VEX_0F70
) },
7396 { REG_TABLE (REG_VEX_0F71
) },
7397 { REG_TABLE (REG_VEX_0F72
) },
7398 { REG_TABLE (REG_VEX_0F73
) },
7399 { PREFIX_TABLE (PREFIX_VEX_0F74
) },
7400 { PREFIX_TABLE (PREFIX_VEX_0F75
) },
7401 { PREFIX_TABLE (PREFIX_VEX_0F76
) },
7402 { PREFIX_TABLE (PREFIX_VEX_0F77
) },
7408 { PREFIX_TABLE (PREFIX_VEX_0F7C
) },
7409 { PREFIX_TABLE (PREFIX_VEX_0F7D
) },
7410 { PREFIX_TABLE (PREFIX_VEX_0F7E
) },
7411 { PREFIX_TABLE (PREFIX_VEX_0F7F
) },
7464 { REG_TABLE (REG_VEX_0FAE
) },
7487 { PREFIX_TABLE (PREFIX_VEX_0FC2
) },
7489 { PREFIX_TABLE (PREFIX_VEX_0FC4
) },
7490 { PREFIX_TABLE (PREFIX_VEX_0FC5
) },
7491 { "vshufpX", { XM
, Vex
, EXx
, Ib
} },
7503 { PREFIX_TABLE (PREFIX_VEX_0FD0
) },
7504 { PREFIX_TABLE (PREFIX_VEX_0FD1
) },
7505 { PREFIX_TABLE (PREFIX_VEX_0FD2
) },
7506 { PREFIX_TABLE (PREFIX_VEX_0FD3
) },
7507 { PREFIX_TABLE (PREFIX_VEX_0FD4
) },
7508 { PREFIX_TABLE (PREFIX_VEX_0FD5
) },
7509 { PREFIX_TABLE (PREFIX_VEX_0FD6
) },
7510 { PREFIX_TABLE (PREFIX_VEX_0FD7
) },
7512 { PREFIX_TABLE (PREFIX_VEX_0FD8
) },
7513 { PREFIX_TABLE (PREFIX_VEX_0FD9
) },
7514 { PREFIX_TABLE (PREFIX_VEX_0FDA
) },
7515 { PREFIX_TABLE (PREFIX_VEX_0FDB
) },
7516 { PREFIX_TABLE (PREFIX_VEX_0FDC
) },
7517 { PREFIX_TABLE (PREFIX_VEX_0FDD
) },
7518 { PREFIX_TABLE (PREFIX_VEX_0FDE
) },
7519 { PREFIX_TABLE (PREFIX_VEX_0FDF
) },
7521 { PREFIX_TABLE (PREFIX_VEX_0FE0
) },
7522 { PREFIX_TABLE (PREFIX_VEX_0FE1
) },
7523 { PREFIX_TABLE (PREFIX_VEX_0FE2
) },
7524 { PREFIX_TABLE (PREFIX_VEX_0FE3
) },
7525 { PREFIX_TABLE (PREFIX_VEX_0FE4
) },
7526 { PREFIX_TABLE (PREFIX_VEX_0FE5
) },
7527 { PREFIX_TABLE (PREFIX_VEX_0FE6
) },
7528 { PREFIX_TABLE (PREFIX_VEX_0FE7
) },
7530 { PREFIX_TABLE (PREFIX_VEX_0FE8
) },
7531 { PREFIX_TABLE (PREFIX_VEX_0FE9
) },
7532 { PREFIX_TABLE (PREFIX_VEX_0FEA
) },
7533 { PREFIX_TABLE (PREFIX_VEX_0FEB
) },
7534 { PREFIX_TABLE (PREFIX_VEX_0FEC
) },
7535 { PREFIX_TABLE (PREFIX_VEX_0FED
) },
7536 { PREFIX_TABLE (PREFIX_VEX_0FEE
) },
7537 { PREFIX_TABLE (PREFIX_VEX_0FEF
) },
7539 { PREFIX_TABLE (PREFIX_VEX_0FF0
) },
7540 { PREFIX_TABLE (PREFIX_VEX_0FF1
) },
7541 { PREFIX_TABLE (PREFIX_VEX_0FF2
) },
7542 { PREFIX_TABLE (PREFIX_VEX_0FF3
) },
7543 { PREFIX_TABLE (PREFIX_VEX_0FF4
) },
7544 { PREFIX_TABLE (PREFIX_VEX_0FF5
) },
7545 { PREFIX_TABLE (PREFIX_VEX_0FF6
) },
7546 { PREFIX_TABLE (PREFIX_VEX_0FF7
) },
7548 { PREFIX_TABLE (PREFIX_VEX_0FF8
) },
7549 { PREFIX_TABLE (PREFIX_VEX_0FF9
) },
7550 { PREFIX_TABLE (PREFIX_VEX_0FFA
) },
7551 { PREFIX_TABLE (PREFIX_VEX_0FFB
) },
7552 { PREFIX_TABLE (PREFIX_VEX_0FFC
) },
7553 { PREFIX_TABLE (PREFIX_VEX_0FFD
) },
7554 { PREFIX_TABLE (PREFIX_VEX_0FFE
) },
7560 { PREFIX_TABLE (PREFIX_VEX_0F3800
) },
7561 { PREFIX_TABLE (PREFIX_VEX_0F3801
) },
7562 { PREFIX_TABLE (PREFIX_VEX_0F3802
) },
7563 { PREFIX_TABLE (PREFIX_VEX_0F3803
) },
7564 { PREFIX_TABLE (PREFIX_VEX_0F3804
) },
7565 { PREFIX_TABLE (PREFIX_VEX_0F3805
) },
7566 { PREFIX_TABLE (PREFIX_VEX_0F3806
) },
7567 { PREFIX_TABLE (PREFIX_VEX_0F3807
) },
7569 { PREFIX_TABLE (PREFIX_VEX_0F3808
) },
7570 { PREFIX_TABLE (PREFIX_VEX_0F3809
) },
7571 { PREFIX_TABLE (PREFIX_VEX_0F380A
) },
7572 { PREFIX_TABLE (PREFIX_VEX_0F380B
) },
7573 { PREFIX_TABLE (PREFIX_VEX_0F380C
) },
7574 { PREFIX_TABLE (PREFIX_VEX_0F380D
) },
7575 { PREFIX_TABLE (PREFIX_VEX_0F380E
) },
7576 { PREFIX_TABLE (PREFIX_VEX_0F380F
) },
7581 { PREFIX_TABLE (PREFIX_VEX_0F3813
) },
7585 { PREFIX_TABLE (PREFIX_VEX_0F3817
) },
7587 { PREFIX_TABLE (PREFIX_VEX_0F3818
) },
7588 { PREFIX_TABLE (PREFIX_VEX_0F3819
) },
7589 { PREFIX_TABLE (PREFIX_VEX_0F381A
) },
7591 { PREFIX_TABLE (PREFIX_VEX_0F381C
) },
7592 { PREFIX_TABLE (PREFIX_VEX_0F381D
) },
7593 { PREFIX_TABLE (PREFIX_VEX_0F381E
) },
7596 { PREFIX_TABLE (PREFIX_VEX_0F3820
) },
7597 { PREFIX_TABLE (PREFIX_VEX_0F3821
) },
7598 { PREFIX_TABLE (PREFIX_VEX_0F3822
) },
7599 { PREFIX_TABLE (PREFIX_VEX_0F3823
) },
7600 { PREFIX_TABLE (PREFIX_VEX_0F3824
) },
7601 { PREFIX_TABLE (PREFIX_VEX_0F3825
) },
7605 { PREFIX_TABLE (PREFIX_VEX_0F3828
) },
7606 { PREFIX_TABLE (PREFIX_VEX_0F3829
) },
7607 { PREFIX_TABLE (PREFIX_VEX_0F382A
) },
7608 { PREFIX_TABLE (PREFIX_VEX_0F382B
) },
7609 { PREFIX_TABLE (PREFIX_VEX_0F382C
) },
7610 { PREFIX_TABLE (PREFIX_VEX_0F382D
) },
7611 { PREFIX_TABLE (PREFIX_VEX_0F382E
) },
7612 { PREFIX_TABLE (PREFIX_VEX_0F382F
) },
7614 { PREFIX_TABLE (PREFIX_VEX_0F3830
) },
7615 { PREFIX_TABLE (PREFIX_VEX_0F3831
) },
7616 { PREFIX_TABLE (PREFIX_VEX_0F3832
) },
7617 { PREFIX_TABLE (PREFIX_VEX_0F3833
) },
7618 { PREFIX_TABLE (PREFIX_VEX_0F3834
) },
7619 { PREFIX_TABLE (PREFIX_VEX_0F3835
) },
7621 { PREFIX_TABLE (PREFIX_VEX_0F3837
) },
7623 { PREFIX_TABLE (PREFIX_VEX_0F3838
) },
7624 { PREFIX_TABLE (PREFIX_VEX_0F3839
) },
7625 { PREFIX_TABLE (PREFIX_VEX_0F383A
) },
7626 { PREFIX_TABLE (PREFIX_VEX_0F383B
) },
7627 { PREFIX_TABLE (PREFIX_VEX_0F383C
) },
7628 { PREFIX_TABLE (PREFIX_VEX_0F383D
) },
7629 { PREFIX_TABLE (PREFIX_VEX_0F383E
) },
7630 { PREFIX_TABLE (PREFIX_VEX_0F383F
) },
7632 { PREFIX_TABLE (PREFIX_VEX_0F3840
) },
7633 { PREFIX_TABLE (PREFIX_VEX_0F3841
) },
7728 { PREFIX_TABLE (PREFIX_VEX_0F3896
) },
7729 { PREFIX_TABLE (PREFIX_VEX_0F3897
) },
7731 { PREFIX_TABLE (PREFIX_VEX_0F3898
) },
7732 { PREFIX_TABLE (PREFIX_VEX_0F3899
) },
7733 { PREFIX_TABLE (PREFIX_VEX_0F389A
) },
7734 { PREFIX_TABLE (PREFIX_VEX_0F389B
) },
7735 { PREFIX_TABLE (PREFIX_VEX_0F389C
) },
7736 { PREFIX_TABLE (PREFIX_VEX_0F389D
) },
7737 { PREFIX_TABLE (PREFIX_VEX_0F389E
) },
7738 { PREFIX_TABLE (PREFIX_VEX_0F389F
) },
7746 { PREFIX_TABLE (PREFIX_VEX_0F38A6
) },
7747 { PREFIX_TABLE (PREFIX_VEX_0F38A7
) },
7749 { PREFIX_TABLE (PREFIX_VEX_0F38A8
) },
7750 { PREFIX_TABLE (PREFIX_VEX_0F38A9
) },
7751 { PREFIX_TABLE (PREFIX_VEX_0F38AA
) },
7752 { PREFIX_TABLE (PREFIX_VEX_0F38AB
) },
7753 { PREFIX_TABLE (PREFIX_VEX_0F38AC
) },
7754 { PREFIX_TABLE (PREFIX_VEX_0F38AD
) },
7755 { PREFIX_TABLE (PREFIX_VEX_0F38AE
) },
7756 { PREFIX_TABLE (PREFIX_VEX_0F38AF
) },
7764 { PREFIX_TABLE (PREFIX_VEX_0F38B6
) },
7765 { PREFIX_TABLE (PREFIX_VEX_0F38B7
) },
7767 { PREFIX_TABLE (PREFIX_VEX_0F38B8
) },
7768 { PREFIX_TABLE (PREFIX_VEX_0F38B9
) },
7769 { PREFIX_TABLE (PREFIX_VEX_0F38BA
) },
7770 { PREFIX_TABLE (PREFIX_VEX_0F38BB
) },
7771 { PREFIX_TABLE (PREFIX_VEX_0F38BC
) },
7772 { PREFIX_TABLE (PREFIX_VEX_0F38BD
) },
7773 { PREFIX_TABLE (PREFIX_VEX_0F38BE
) },
7774 { PREFIX_TABLE (PREFIX_VEX_0F38BF
) },
7806 { PREFIX_TABLE (PREFIX_VEX_0F38DB
) },
7807 { PREFIX_TABLE (PREFIX_VEX_0F38DC
) },
7808 { PREFIX_TABLE (PREFIX_VEX_0F38DD
) },
7809 { PREFIX_TABLE (PREFIX_VEX_0F38DE
) },
7810 { PREFIX_TABLE (PREFIX_VEX_0F38DF
) },
7855 { PREFIX_TABLE (PREFIX_VEX_0F3A04
) },
7856 { PREFIX_TABLE (PREFIX_VEX_0F3A05
) },
7857 { PREFIX_TABLE (PREFIX_VEX_0F3A06
) },
7860 { PREFIX_TABLE (PREFIX_VEX_0F3A08
) },
7861 { PREFIX_TABLE (PREFIX_VEX_0F3A09
) },
7862 { PREFIX_TABLE (PREFIX_VEX_0F3A0A
) },
7863 { PREFIX_TABLE (PREFIX_VEX_0F3A0B
) },
7864 { PREFIX_TABLE (PREFIX_VEX_0F3A0C
) },
7865 { PREFIX_TABLE (PREFIX_VEX_0F3A0D
) },
7866 { PREFIX_TABLE (PREFIX_VEX_0F3A0E
) },
7867 { PREFIX_TABLE (PREFIX_VEX_0F3A0F
) },
7873 { PREFIX_TABLE (PREFIX_VEX_0F3A14
) },
7874 { PREFIX_TABLE (PREFIX_VEX_0F3A15
) },
7875 { PREFIX_TABLE (PREFIX_VEX_0F3A16
) },
7876 { PREFIX_TABLE (PREFIX_VEX_0F3A17
) },
7878 { PREFIX_TABLE (PREFIX_VEX_0F3A18
) },
7879 { PREFIX_TABLE (PREFIX_VEX_0F3A19
) },
7883 { PREFIX_TABLE (PREFIX_VEX_0F3A1D
) },
7887 { PREFIX_TABLE (PREFIX_VEX_0F3A20
) },
7888 { PREFIX_TABLE (PREFIX_VEX_0F3A21
) },
7889 { PREFIX_TABLE (PREFIX_VEX_0F3A22
) },
7923 { PREFIX_TABLE (PREFIX_VEX_0F3A40
) },
7924 { PREFIX_TABLE (PREFIX_VEX_0F3A41
) },
7925 { PREFIX_TABLE (PREFIX_VEX_0F3A42
) },
7927 { PREFIX_TABLE (PREFIX_VEX_0F3A44
) },
7932 { PREFIX_TABLE (PREFIX_VEX_0F3A48
) },
7933 { PREFIX_TABLE (PREFIX_VEX_0F3A49
) },
7934 { PREFIX_TABLE (PREFIX_VEX_0F3A4A
) },
7935 { PREFIX_TABLE (PREFIX_VEX_0F3A4B
) },
7936 { PREFIX_TABLE (PREFIX_VEX_0F3A4C
) },
7954 { PREFIX_TABLE (PREFIX_VEX_0F3A5C
) },
7955 { PREFIX_TABLE (PREFIX_VEX_0F3A5D
) },
7956 { PREFIX_TABLE (PREFIX_VEX_0F3A5E
) },
7957 { PREFIX_TABLE (PREFIX_VEX_0F3A5F
) },
7959 { PREFIX_TABLE (PREFIX_VEX_0F3A60
) },
7960 { PREFIX_TABLE (PREFIX_VEX_0F3A61
) },
7961 { PREFIX_TABLE (PREFIX_VEX_0F3A62
) },
7962 { PREFIX_TABLE (PREFIX_VEX_0F3A63
) },
7968 { PREFIX_TABLE (PREFIX_VEX_0F3A68
) },
7969 { PREFIX_TABLE (PREFIX_VEX_0F3A69
) },
7970 { PREFIX_TABLE (PREFIX_VEX_0F3A6A
) },
7971 { PREFIX_TABLE (PREFIX_VEX_0F3A6B
) },
7972 { PREFIX_TABLE (PREFIX_VEX_0F3A6C
) },
7973 { PREFIX_TABLE (PREFIX_VEX_0F3A6D
) },
7974 { PREFIX_TABLE (PREFIX_VEX_0F3A6E
) },
7975 { PREFIX_TABLE (PREFIX_VEX_0F3A6F
) },
7986 { PREFIX_TABLE (PREFIX_VEX_0F3A78
) },
7987 { PREFIX_TABLE (PREFIX_VEX_0F3A79
) },
7988 { PREFIX_TABLE (PREFIX_VEX_0F3A7A
) },
7989 { PREFIX_TABLE (PREFIX_VEX_0F3A7B
) },
7990 { PREFIX_TABLE (PREFIX_VEX_0F3A7C
) },
7991 { PREFIX_TABLE (PREFIX_VEX_0F3A7D
) },
7992 { PREFIX_TABLE (PREFIX_VEX_0F3A7E
) },
7993 { PREFIX_TABLE (PREFIX_VEX_0F3A7F
) },
8101 { PREFIX_TABLE (PREFIX_VEX_0F3ADF
) },
8141 static const struct dis386 vex_len_table
[][2] = {
8142 /* VEX_LEN_0F10_P_1 */
8144 { VEX_W_TABLE (VEX_W_0F10_P_1
) },
8145 { VEX_W_TABLE (VEX_W_0F10_P_1
) },
8148 /* VEX_LEN_0F10_P_3 */
8150 { VEX_W_TABLE (VEX_W_0F10_P_3
) },
8151 { VEX_W_TABLE (VEX_W_0F10_P_3
) },
8154 /* VEX_LEN_0F11_P_1 */
8156 { VEX_W_TABLE (VEX_W_0F11_P_1
) },
8157 { VEX_W_TABLE (VEX_W_0F11_P_1
) },
8160 /* VEX_LEN_0F11_P_3 */
8162 { VEX_W_TABLE (VEX_W_0F11_P_3
) },
8163 { VEX_W_TABLE (VEX_W_0F11_P_3
) },
8166 /* VEX_LEN_0F12_P_0_M_0 */
8168 { VEX_W_TABLE (VEX_W_0F12_P_0_M_0
) },
8171 /* VEX_LEN_0F12_P_0_M_1 */
8173 { VEX_W_TABLE (VEX_W_0F12_P_0_M_1
) },
8176 /* VEX_LEN_0F12_P_2 */
8178 { VEX_W_TABLE (VEX_W_0F12_P_2
) },
8181 /* VEX_LEN_0F13_M_0 */
8183 { VEX_W_TABLE (VEX_W_0F13_M_0
) },
8186 /* VEX_LEN_0F16_P_0_M_0 */
8188 { VEX_W_TABLE (VEX_W_0F16_P_0_M_0
) },
8191 /* VEX_LEN_0F16_P_0_M_1 */
8193 { VEX_W_TABLE (VEX_W_0F16_P_0_M_1
) },
8196 /* VEX_LEN_0F16_P_2 */
8198 { VEX_W_TABLE (VEX_W_0F16_P_2
) },
8201 /* VEX_LEN_0F17_M_0 */
8203 { VEX_W_TABLE (VEX_W_0F17_M_0
) },
8206 /* VEX_LEN_0F2A_P_1 */
8208 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Ev
} },
8209 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Ev
} },
8212 /* VEX_LEN_0F2A_P_3 */
8214 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Ev
} },
8215 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Ev
} },
8218 /* VEX_LEN_0F2C_P_1 */
8220 { "vcvttss2siY", { Gv
, EXdScalar
} },
8221 { "vcvttss2siY", { Gv
, EXdScalar
} },
8224 /* VEX_LEN_0F2C_P_3 */
8226 { "vcvttsd2siY", { Gv
, EXqScalar
} },
8227 { "vcvttsd2siY", { Gv
, EXqScalar
} },
8230 /* VEX_LEN_0F2D_P_1 */
8232 { "vcvtss2siY", { Gv
, EXdScalar
} },
8233 { "vcvtss2siY", { Gv
, EXdScalar
} },
8236 /* VEX_LEN_0F2D_P_3 */
8238 { "vcvtsd2siY", { Gv
, EXqScalar
} },
8239 { "vcvtsd2siY", { Gv
, EXqScalar
} },
8242 /* VEX_LEN_0F2E_P_0 */
8244 { VEX_W_TABLE (VEX_W_0F2E_P_0
) },
8245 { VEX_W_TABLE (VEX_W_0F2E_P_0
) },
8248 /* VEX_LEN_0F2E_P_2 */
8250 { VEX_W_TABLE (VEX_W_0F2E_P_2
) },
8251 { VEX_W_TABLE (VEX_W_0F2E_P_2
) },
8254 /* VEX_LEN_0F2F_P_0 */
8256 { VEX_W_TABLE (VEX_W_0F2F_P_0
) },
8257 { VEX_W_TABLE (VEX_W_0F2F_P_0
) },
8260 /* VEX_LEN_0F2F_P_2 */
8262 { VEX_W_TABLE (VEX_W_0F2F_P_2
) },
8263 { VEX_W_TABLE (VEX_W_0F2F_P_2
) },
8266 /* VEX_LEN_0F51_P_1 */
8268 { VEX_W_TABLE (VEX_W_0F51_P_1
) },
8269 { VEX_W_TABLE (VEX_W_0F51_P_1
) },
8272 /* VEX_LEN_0F51_P_3 */
8274 { VEX_W_TABLE (VEX_W_0F51_P_3
) },
8275 { VEX_W_TABLE (VEX_W_0F51_P_3
) },
8278 /* VEX_LEN_0F52_P_1 */
8280 { VEX_W_TABLE (VEX_W_0F52_P_1
) },
8281 { VEX_W_TABLE (VEX_W_0F52_P_1
) },
8284 /* VEX_LEN_0F53_P_1 */
8286 { VEX_W_TABLE (VEX_W_0F53_P_1
) },
8287 { VEX_W_TABLE (VEX_W_0F53_P_1
) },
8290 /* VEX_LEN_0F58_P_1 */
8292 { VEX_W_TABLE (VEX_W_0F58_P_1
) },
8293 { VEX_W_TABLE (VEX_W_0F58_P_1
) },
8296 /* VEX_LEN_0F58_P_3 */
8298 { VEX_W_TABLE (VEX_W_0F58_P_3
) },
8299 { VEX_W_TABLE (VEX_W_0F58_P_3
) },
8302 /* VEX_LEN_0F59_P_1 */
8304 { VEX_W_TABLE (VEX_W_0F59_P_1
) },
8305 { VEX_W_TABLE (VEX_W_0F59_P_1
) },
8308 /* VEX_LEN_0F59_P_3 */
8310 { VEX_W_TABLE (VEX_W_0F59_P_3
) },
8311 { VEX_W_TABLE (VEX_W_0F59_P_3
) },
8314 /* VEX_LEN_0F5A_P_1 */
8316 { VEX_W_TABLE (VEX_W_0F5A_P_1
) },
8317 { VEX_W_TABLE (VEX_W_0F5A_P_1
) },
8320 /* VEX_LEN_0F5A_P_3 */
8322 { VEX_W_TABLE (VEX_W_0F5A_P_3
) },
8323 { VEX_W_TABLE (VEX_W_0F5A_P_3
) },
8326 /* VEX_LEN_0F5C_P_1 */
8328 { VEX_W_TABLE (VEX_W_0F5C_P_1
) },
8329 { VEX_W_TABLE (VEX_W_0F5C_P_1
) },
8332 /* VEX_LEN_0F5C_P_3 */
8334 { VEX_W_TABLE (VEX_W_0F5C_P_3
) },
8335 { VEX_W_TABLE (VEX_W_0F5C_P_3
) },
8338 /* VEX_LEN_0F5D_P_1 */
8340 { VEX_W_TABLE (VEX_W_0F5D_P_1
) },
8341 { VEX_W_TABLE (VEX_W_0F5D_P_1
) },
8344 /* VEX_LEN_0F5D_P_3 */
8346 { VEX_W_TABLE (VEX_W_0F5D_P_3
) },
8347 { VEX_W_TABLE (VEX_W_0F5D_P_3
) },
8350 /* VEX_LEN_0F5E_P_1 */
8352 { VEX_W_TABLE (VEX_W_0F5E_P_1
) },
8353 { VEX_W_TABLE (VEX_W_0F5E_P_1
) },
8356 /* VEX_LEN_0F5E_P_3 */
8358 { VEX_W_TABLE (VEX_W_0F5E_P_3
) },
8359 { VEX_W_TABLE (VEX_W_0F5E_P_3
) },
8362 /* VEX_LEN_0F5F_P_1 */
8364 { VEX_W_TABLE (VEX_W_0F5F_P_1
) },
8365 { VEX_W_TABLE (VEX_W_0F5F_P_1
) },
8368 /* VEX_LEN_0F5F_P_3 */
8370 { VEX_W_TABLE (VEX_W_0F5F_P_3
) },
8371 { VEX_W_TABLE (VEX_W_0F5F_P_3
) },
8374 /* VEX_LEN_0F60_P_2 */
8376 { VEX_W_TABLE (VEX_W_0F60_P_2
) },
8379 /* VEX_LEN_0F61_P_2 */
8381 { VEX_W_TABLE (VEX_W_0F61_P_2
) },
8384 /* VEX_LEN_0F62_P_2 */
8386 { VEX_W_TABLE (VEX_W_0F62_P_2
) },
8389 /* VEX_LEN_0F63_P_2 */
8391 { VEX_W_TABLE (VEX_W_0F63_P_2
) },
8394 /* VEX_LEN_0F64_P_2 */
8396 { VEX_W_TABLE (VEX_W_0F64_P_2
) },
8399 /* VEX_LEN_0F65_P_2 */
8401 { VEX_W_TABLE (VEX_W_0F65_P_2
) },
8404 /* VEX_LEN_0F66_P_2 */
8406 { VEX_W_TABLE (VEX_W_0F66_P_2
) },
8409 /* VEX_LEN_0F67_P_2 */
8411 { VEX_W_TABLE (VEX_W_0F67_P_2
) },
8414 /* VEX_LEN_0F68_P_2 */
8416 { VEX_W_TABLE (VEX_W_0F68_P_2
) },
8419 /* VEX_LEN_0F69_P_2 */
8421 { VEX_W_TABLE (VEX_W_0F69_P_2
) },
8424 /* VEX_LEN_0F6A_P_2 */
8426 { VEX_W_TABLE (VEX_W_0F6A_P_2
) },
8429 /* VEX_LEN_0F6B_P_2 */
8431 { VEX_W_TABLE (VEX_W_0F6B_P_2
) },
8434 /* VEX_LEN_0F6C_P_2 */
8436 { VEX_W_TABLE (VEX_W_0F6C_P_2
) },
8439 /* VEX_LEN_0F6D_P_2 */
8441 { VEX_W_TABLE (VEX_W_0F6D_P_2
) },
8444 /* VEX_LEN_0F6E_P_2 */
8446 { "vmovK", { XMScalar
, Edq
} },
8447 { "vmovK", { XMScalar
, Edq
} },
8450 /* VEX_LEN_0F70_P_1 */
8452 { VEX_W_TABLE (VEX_W_0F70_P_1
) },
8455 /* VEX_LEN_0F70_P_2 */
8457 { VEX_W_TABLE (VEX_W_0F70_P_2
) },
8460 /* VEX_LEN_0F70_P_3 */
8462 { VEX_W_TABLE (VEX_W_0F70_P_3
) },
8465 /* VEX_LEN_0F71_R_2_P_2 */
8467 { VEX_W_TABLE (VEX_W_0F71_R_2_P_2
) },
8470 /* VEX_LEN_0F71_R_4_P_2 */
8472 { VEX_W_TABLE (VEX_W_0F71_R_4_P_2
) },
8475 /* VEX_LEN_0F71_R_6_P_2 */
8477 { VEX_W_TABLE (VEX_W_0F71_R_6_P_2
) },
8480 /* VEX_LEN_0F72_R_2_P_2 */
8482 { VEX_W_TABLE (VEX_W_0F72_R_2_P_2
) },
8485 /* VEX_LEN_0F72_R_4_P_2 */
8487 { VEX_W_TABLE (VEX_W_0F72_R_4_P_2
) },
8490 /* VEX_LEN_0F72_R_6_P_2 */
8492 { VEX_W_TABLE (VEX_W_0F72_R_6_P_2
) },
8495 /* VEX_LEN_0F73_R_2_P_2 */
8497 { VEX_W_TABLE (VEX_W_0F73_R_2_P_2
) },
8500 /* VEX_LEN_0F73_R_3_P_2 */
8502 { VEX_W_TABLE (VEX_W_0F73_R_3_P_2
) },
8505 /* VEX_LEN_0F73_R_6_P_2 */
8507 { VEX_W_TABLE (VEX_W_0F73_R_6_P_2
) },
8510 /* VEX_LEN_0F73_R_7_P_2 */
8512 { VEX_W_TABLE (VEX_W_0F73_R_7_P_2
) },
8515 /* VEX_LEN_0F74_P_2 */
8517 { VEX_W_TABLE (VEX_W_0F74_P_2
) },
8520 /* VEX_LEN_0F75_P_2 */
8522 { VEX_W_TABLE (VEX_W_0F75_P_2
) },
8525 /* VEX_LEN_0F76_P_2 */
8527 { VEX_W_TABLE (VEX_W_0F76_P_2
) },
8530 /* VEX_LEN_0F7E_P_1 */
8532 { VEX_W_TABLE (VEX_W_0F7E_P_1
) },
8533 { VEX_W_TABLE (VEX_W_0F7E_P_1
) },
8536 /* VEX_LEN_0F7E_P_2 */
8538 { "vmovK", { Edq
, XMScalar
} },
8539 { "vmovK", { Edq
, XMScalar
} },
8542 /* VEX_LEN_0FAE_R_2_M_0 */
8544 { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0
) },
8547 /* VEX_LEN_0FAE_R_3_M_0 */
8549 { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0
) },
8552 /* VEX_LEN_0FC2_P_1 */
8554 { VEX_W_TABLE (VEX_W_0FC2_P_1
) },
8555 { VEX_W_TABLE (VEX_W_0FC2_P_1
) },
8558 /* VEX_LEN_0FC2_P_3 */
8560 { VEX_W_TABLE (VEX_W_0FC2_P_3
) },
8561 { VEX_W_TABLE (VEX_W_0FC2_P_3
) },
8564 /* VEX_LEN_0FC4_P_2 */
8566 { VEX_W_TABLE (VEX_W_0FC4_P_2
) },
8569 /* VEX_LEN_0FC5_P_2 */
8571 { VEX_W_TABLE (VEX_W_0FC5_P_2
) },
8574 /* VEX_LEN_0FD1_P_2 */
8576 { VEX_W_TABLE (VEX_W_0FD1_P_2
) },
8579 /* VEX_LEN_0FD2_P_2 */
8581 { VEX_W_TABLE (VEX_W_0FD2_P_2
) },
8584 /* VEX_LEN_0FD3_P_2 */
8586 { VEX_W_TABLE (VEX_W_0FD3_P_2
) },
8589 /* VEX_LEN_0FD4_P_2 */
8591 { VEX_W_TABLE (VEX_W_0FD4_P_2
) },
8594 /* VEX_LEN_0FD5_P_2 */
8596 { VEX_W_TABLE (VEX_W_0FD5_P_2
) },
8599 /* VEX_LEN_0FD6_P_2 */
8601 { VEX_W_TABLE (VEX_W_0FD6_P_2
) },
8602 { VEX_W_TABLE (VEX_W_0FD6_P_2
) },
8605 /* VEX_LEN_0FD7_P_2_M_1 */
8607 { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1
) },
8610 /* VEX_LEN_0FD8_P_2 */
8612 { VEX_W_TABLE (VEX_W_0FD8_P_2
) },
8615 /* VEX_LEN_0FD9_P_2 */
8617 { VEX_W_TABLE (VEX_W_0FD9_P_2
) },
8620 /* VEX_LEN_0FDA_P_2 */
8622 { VEX_W_TABLE (VEX_W_0FDA_P_2
) },
8625 /* VEX_LEN_0FDB_P_2 */
8627 { VEX_W_TABLE (VEX_W_0FDB_P_2
) },
8630 /* VEX_LEN_0FDC_P_2 */
8632 { VEX_W_TABLE (VEX_W_0FDC_P_2
) },
8635 /* VEX_LEN_0FDD_P_2 */
8637 { VEX_W_TABLE (VEX_W_0FDD_P_2
) },
8640 /* VEX_LEN_0FDE_P_2 */
8642 { VEX_W_TABLE (VEX_W_0FDE_P_2
) },
8645 /* VEX_LEN_0FDF_P_2 */
8647 { VEX_W_TABLE (VEX_W_0FDF_P_2
) },
8650 /* VEX_LEN_0FE0_P_2 */
8652 { VEX_W_TABLE (VEX_W_0FE0_P_2
) },
8655 /* VEX_LEN_0FE1_P_2 */
8657 { VEX_W_TABLE (VEX_W_0FE1_P_2
) },
8660 /* VEX_LEN_0FE2_P_2 */
8662 { VEX_W_TABLE (VEX_W_0FE2_P_2
) },
8665 /* VEX_LEN_0FE3_P_2 */
8667 { VEX_W_TABLE (VEX_W_0FE3_P_2
) },
8670 /* VEX_LEN_0FE4_P_2 */
8672 { VEX_W_TABLE (VEX_W_0FE4_P_2
) },
8675 /* VEX_LEN_0FE5_P_2 */
8677 { VEX_W_TABLE (VEX_W_0FE5_P_2
) },
8680 /* VEX_LEN_0FE8_P_2 */
8682 { VEX_W_TABLE (VEX_W_0FE8_P_2
) },
8685 /* VEX_LEN_0FE9_P_2 */
8687 { VEX_W_TABLE (VEX_W_0FE9_P_2
) },
8690 /* VEX_LEN_0FEA_P_2 */
8692 { VEX_W_TABLE (VEX_W_0FEA_P_2
) },
8695 /* VEX_LEN_0FEB_P_2 */
8697 { VEX_W_TABLE (VEX_W_0FEB_P_2
) },
8700 /* VEX_LEN_0FEC_P_2 */
8702 { VEX_W_TABLE (VEX_W_0FEC_P_2
) },
8705 /* VEX_LEN_0FED_P_2 */
8707 { VEX_W_TABLE (VEX_W_0FED_P_2
) },
8710 /* VEX_LEN_0FEE_P_2 */
8712 { VEX_W_TABLE (VEX_W_0FEE_P_2
) },
8715 /* VEX_LEN_0FEF_P_2 */
8717 { VEX_W_TABLE (VEX_W_0FEF_P_2
) },
8720 /* VEX_LEN_0FF1_P_2 */
8722 { VEX_W_TABLE (VEX_W_0FF1_P_2
) },
8725 /* VEX_LEN_0FF2_P_2 */
8727 { VEX_W_TABLE (VEX_W_0FF2_P_2
) },
8730 /* VEX_LEN_0FF3_P_2 */
8732 { VEX_W_TABLE (VEX_W_0FF3_P_2
) },
8735 /* VEX_LEN_0FF4_P_2 */
8737 { VEX_W_TABLE (VEX_W_0FF4_P_2
) },
8740 /* VEX_LEN_0FF5_P_2 */
8742 { VEX_W_TABLE (VEX_W_0FF5_P_2
) },
8745 /* VEX_LEN_0FF6_P_2 */
8747 { VEX_W_TABLE (VEX_W_0FF6_P_2
) },
8750 /* VEX_LEN_0FF7_P_2 */
8752 { VEX_W_TABLE (VEX_W_0FF7_P_2
) },
8755 /* VEX_LEN_0FF8_P_2 */
8757 { VEX_W_TABLE (VEX_W_0FF8_P_2
) },
8760 /* VEX_LEN_0FF9_P_2 */
8762 { VEX_W_TABLE (VEX_W_0FF9_P_2
) },
8765 /* VEX_LEN_0FFA_P_2 */
8767 { VEX_W_TABLE (VEX_W_0FFA_P_2
) },
8770 /* VEX_LEN_0FFB_P_2 */
8772 { VEX_W_TABLE (VEX_W_0FFB_P_2
) },
8775 /* VEX_LEN_0FFC_P_2 */
8777 { VEX_W_TABLE (VEX_W_0FFC_P_2
) },
8780 /* VEX_LEN_0FFD_P_2 */
8782 { VEX_W_TABLE (VEX_W_0FFD_P_2
) },
8785 /* VEX_LEN_0FFE_P_2 */
8787 { VEX_W_TABLE (VEX_W_0FFE_P_2
) },
8790 /* VEX_LEN_0F3800_P_2 */
8792 { VEX_W_TABLE (VEX_W_0F3800_P_2
) },
8795 /* VEX_LEN_0F3801_P_2 */
8797 { VEX_W_TABLE (VEX_W_0F3801_P_2
) },
8800 /* VEX_LEN_0F3802_P_2 */
8802 { VEX_W_TABLE (VEX_W_0F3802_P_2
) },
8805 /* VEX_LEN_0F3803_P_2 */
8807 { VEX_W_TABLE (VEX_W_0F3803_P_2
) },
8810 /* VEX_LEN_0F3804_P_2 */
8812 { VEX_W_TABLE (VEX_W_0F3804_P_2
) },
8815 /* VEX_LEN_0F3805_P_2 */
8817 { VEX_W_TABLE (VEX_W_0F3805_P_2
) },
8820 /* VEX_LEN_0F3806_P_2 */
8822 { VEX_W_TABLE (VEX_W_0F3806_P_2
) },
8825 /* VEX_LEN_0F3807_P_2 */
8827 { VEX_W_TABLE (VEX_W_0F3807_P_2
) },
8830 /* VEX_LEN_0F3808_P_2 */
8832 { VEX_W_TABLE (VEX_W_0F3808_P_2
) },
8835 /* VEX_LEN_0F3809_P_2 */
8837 { VEX_W_TABLE (VEX_W_0F3809_P_2
) },
8840 /* VEX_LEN_0F380A_P_2 */
8842 { VEX_W_TABLE (VEX_W_0F380A_P_2
) },
8845 /* VEX_LEN_0F380B_P_2 */
8847 { VEX_W_TABLE (VEX_W_0F380B_P_2
) },
8850 /* VEX_LEN_0F3819_P_2_M_0 */
8853 { VEX_W_TABLE (VEX_W_0F3819_P_2_M_0
) },
8856 /* VEX_LEN_0F381A_P_2_M_0 */
8859 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0
) },
8862 /* VEX_LEN_0F381C_P_2 */
8864 { VEX_W_TABLE (VEX_W_0F381C_P_2
) },
8867 /* VEX_LEN_0F381D_P_2 */
8869 { VEX_W_TABLE (VEX_W_0F381D_P_2
) },
8872 /* VEX_LEN_0F381E_P_2 */
8874 { VEX_W_TABLE (VEX_W_0F381E_P_2
) },
8877 /* VEX_LEN_0F3820_P_2 */
8879 { VEX_W_TABLE (VEX_W_0F3820_P_2
) },
8882 /* VEX_LEN_0F3821_P_2 */
8884 { VEX_W_TABLE (VEX_W_0F3821_P_2
) },
8887 /* VEX_LEN_0F3822_P_2 */
8889 { VEX_W_TABLE (VEX_W_0F3822_P_2
) },
8892 /* VEX_LEN_0F3823_P_2 */
8894 { VEX_W_TABLE (VEX_W_0F3823_P_2
) },
8897 /* VEX_LEN_0F3824_P_2 */
8899 { VEX_W_TABLE (VEX_W_0F3824_P_2
) },
8902 /* VEX_LEN_0F3825_P_2 */
8904 { VEX_W_TABLE (VEX_W_0F3825_P_2
) },
8907 /* VEX_LEN_0F3828_P_2 */
8909 { VEX_W_TABLE (VEX_W_0F3828_P_2
) },
8912 /* VEX_LEN_0F3829_P_2 */
8914 { VEX_W_TABLE (VEX_W_0F3829_P_2
) },
8917 /* VEX_LEN_0F382A_P_2_M_0 */
8919 { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0
) },
8922 /* VEX_LEN_0F382B_P_2 */
8924 { VEX_W_TABLE (VEX_W_0F382B_P_2
) },
8927 /* VEX_LEN_0F3830_P_2 */
8929 { VEX_W_TABLE (VEX_W_0F3830_P_2
) },
8932 /* VEX_LEN_0F3831_P_2 */
8934 { VEX_W_TABLE (VEX_W_0F3831_P_2
) },
8937 /* VEX_LEN_0F3832_P_2 */
8939 { VEX_W_TABLE (VEX_W_0F3832_P_2
) },
8942 /* VEX_LEN_0F3833_P_2 */
8944 { VEX_W_TABLE (VEX_W_0F3833_P_2
) },
8947 /* VEX_LEN_0F3834_P_2 */
8949 { VEX_W_TABLE (VEX_W_0F3834_P_2
) },
8952 /* VEX_LEN_0F3835_P_2 */
8954 { VEX_W_TABLE (VEX_W_0F3835_P_2
) },
8957 /* VEX_LEN_0F3837_P_2 */
8959 { VEX_W_TABLE (VEX_W_0F3837_P_2
) },
8962 /* VEX_LEN_0F3838_P_2 */
8964 { VEX_W_TABLE (VEX_W_0F3838_P_2
) },
8967 /* VEX_LEN_0F3839_P_2 */
8969 { VEX_W_TABLE (VEX_W_0F3839_P_2
) },
8972 /* VEX_LEN_0F383A_P_2 */
8974 { VEX_W_TABLE (VEX_W_0F383A_P_2
) },
8977 /* VEX_LEN_0F383B_P_2 */
8979 { VEX_W_TABLE (VEX_W_0F383B_P_2
) },
8982 /* VEX_LEN_0F383C_P_2 */
8984 { VEX_W_TABLE (VEX_W_0F383C_P_2
) },
8987 /* VEX_LEN_0F383D_P_2 */
8989 { VEX_W_TABLE (VEX_W_0F383D_P_2
) },
8992 /* VEX_LEN_0F383E_P_2 */
8994 { VEX_W_TABLE (VEX_W_0F383E_P_2
) },
8997 /* VEX_LEN_0F383F_P_2 */
8999 { VEX_W_TABLE (VEX_W_0F383F_P_2
) },
9002 /* VEX_LEN_0F3840_P_2 */
9004 { VEX_W_TABLE (VEX_W_0F3840_P_2
) },
9007 /* VEX_LEN_0F3841_P_2 */
9009 { VEX_W_TABLE (VEX_W_0F3841_P_2
) },
9012 /* VEX_LEN_0F38DB_P_2 */
9014 { VEX_W_TABLE (VEX_W_0F38DB_P_2
) },
9017 /* VEX_LEN_0F38DC_P_2 */
9019 { VEX_W_TABLE (VEX_W_0F38DC_P_2
) },
9022 /* VEX_LEN_0F38DD_P_2 */
9024 { VEX_W_TABLE (VEX_W_0F38DD_P_2
) },
9027 /* VEX_LEN_0F38DE_P_2 */
9029 { VEX_W_TABLE (VEX_W_0F38DE_P_2
) },
9032 /* VEX_LEN_0F38DF_P_2 */
9034 { VEX_W_TABLE (VEX_W_0F38DF_P_2
) },
9037 /* VEX_LEN_0F3A06_P_2 */
9040 { VEX_W_TABLE (VEX_W_0F3A06_P_2
) },
9043 /* VEX_LEN_0F3A0A_P_2 */
9045 { VEX_W_TABLE (VEX_W_0F3A0A_P_2
) },
9046 { VEX_W_TABLE (VEX_W_0F3A0A_P_2
) },
9049 /* VEX_LEN_0F3A0B_P_2 */
9051 { VEX_W_TABLE (VEX_W_0F3A0B_P_2
) },
9052 { VEX_W_TABLE (VEX_W_0F3A0B_P_2
) },
9055 /* VEX_LEN_0F3A0E_P_2 */
9057 { VEX_W_TABLE (VEX_W_0F3A0E_P_2
) },
9060 /* VEX_LEN_0F3A0F_P_2 */
9062 { VEX_W_TABLE (VEX_W_0F3A0F_P_2
) },
9065 /* VEX_LEN_0F3A14_P_2 */
9067 { VEX_W_TABLE (VEX_W_0F3A14_P_2
) },
9070 /* VEX_LEN_0F3A15_P_2 */
9072 { VEX_W_TABLE (VEX_W_0F3A15_P_2
) },
9075 /* VEX_LEN_0F3A16_P_2 */
9077 { "vpextrK", { Edq
, XM
, Ib
} },
9080 /* VEX_LEN_0F3A17_P_2 */
9082 { "vextractps", { Edqd
, XM
, Ib
} },
9085 /* VEX_LEN_0F3A18_P_2 */
9088 { VEX_W_TABLE (VEX_W_0F3A18_P_2
) },
9091 /* VEX_LEN_0F3A19_P_2 */
9094 { VEX_W_TABLE (VEX_W_0F3A19_P_2
) },
9097 /* VEX_LEN_0F3A20_P_2 */
9099 { VEX_W_TABLE (VEX_W_0F3A20_P_2
) },
9102 /* VEX_LEN_0F3A21_P_2 */
9104 { VEX_W_TABLE (VEX_W_0F3A21_P_2
) },
9107 /* VEX_LEN_0F3A22_P_2 */
9109 { "vpinsrK", { XM
, Vex128
, Edq
, Ib
} },
9112 /* VEX_LEN_0F3A41_P_2 */
9114 { VEX_W_TABLE (VEX_W_0F3A41_P_2
) },
9117 /* VEX_LEN_0F3A42_P_2 */
9119 { VEX_W_TABLE (VEX_W_0F3A42_P_2
) },
9122 /* VEX_LEN_0F3A44_P_2 */
9124 { VEX_W_TABLE (VEX_W_0F3A44_P_2
) },
9127 /* VEX_LEN_0F3A4C_P_2 */
9129 { VEX_W_TABLE (VEX_W_0F3A4C_P_2
) },
9132 /* VEX_LEN_0F3A60_P_2 */
9134 { VEX_W_TABLE (VEX_W_0F3A60_P_2
) },
9137 /* VEX_LEN_0F3A61_P_2 */
9139 { VEX_W_TABLE (VEX_W_0F3A61_P_2
) },
9142 /* VEX_LEN_0F3A62_P_2 */
9144 { VEX_W_TABLE (VEX_W_0F3A62_P_2
) },
9147 /* VEX_LEN_0F3A63_P_2 */
9149 { VEX_W_TABLE (VEX_W_0F3A63_P_2
) },
9152 /* VEX_LEN_0F3A6A_P_2 */
9154 { "vfmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
} },
9157 /* VEX_LEN_0F3A6B_P_2 */
9159 { "vfmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
} },
9162 /* VEX_LEN_0F3A6E_P_2 */
9164 { "vfmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
} },
9167 /* VEX_LEN_0F3A6F_P_2 */
9169 { "vfmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
} },
9172 /* VEX_LEN_0F3A7A_P_2 */
9174 { "vfnmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
} },
9177 /* VEX_LEN_0F3A7B_P_2 */
9179 { "vfnmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
} },
9182 /* VEX_LEN_0F3A7E_P_2 */
9184 { "vfnmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
} },
9187 /* VEX_LEN_0F3A7F_P_2 */
9189 { "vfnmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
} },
9192 /* VEX_LEN_0F3ADF_P_2 */
9194 { VEX_W_TABLE (VEX_W_0F3ADF_P_2
) },
9197 /* VEX_LEN_0FXOP_09_80 */
9199 { "vfrczps", { XM
, EXxmm
} },
9200 { "vfrczps", { XM
, EXymmq
} },
9203 /* VEX_LEN_0FXOP_09_81 */
9205 { "vfrczpd", { XM
, EXxmm
} },
9206 { "vfrczpd", { XM
, EXymmq
} },
9210 static const struct dis386 vex_w_table
[][2] = {
9212 /* VEX_W_0F10_P_0 */
9213 { "vmovups", { XM
, EXx
} },
9216 /* VEX_W_0F10_P_1 */
9217 { "vmovss", { XMVexScalar
, VexScalar
, EXdScalar
} },
9220 /* VEX_W_0F10_P_2 */
9221 { "vmovupd", { XM
, EXx
} },
9224 /* VEX_W_0F10_P_3 */
9225 { "vmovsd", { XMVexScalar
, VexScalar
, EXqScalar
} },
9228 /* VEX_W_0F11_P_0 */
9229 { "vmovups", { EXxS
, XM
} },
9232 /* VEX_W_0F11_P_1 */
9233 { "vmovss", { EXdVexScalarS
, VexScalar
, XMScalar
} },
9236 /* VEX_W_0F11_P_2 */
9237 { "vmovupd", { EXxS
, XM
} },
9240 /* VEX_W_0F11_P_3 */
9241 { "vmovsd", { EXqVexScalarS
, VexScalar
, XMScalar
} },
9244 /* VEX_W_0F12_P_0_M_0 */
9245 { "vmovlps", { XM
, Vex128
, EXq
} },
9248 /* VEX_W_0F12_P_0_M_1 */
9249 { "vmovhlps", { XM
, Vex128
, EXq
} },
9252 /* VEX_W_0F12_P_1 */
9253 { "vmovsldup", { XM
, EXx
} },
9256 /* VEX_W_0F12_P_2 */
9257 { "vmovlpd", { XM
, Vex128
, EXq
} },
9260 /* VEX_W_0F12_P_3 */
9261 { "vmovddup", { XM
, EXymmq
} },
9264 /* VEX_W_0F13_M_0 */
9265 { "vmovlpX", { EXq
, XM
} },
9269 { "vunpcklpX", { XM
, Vex
, EXx
} },
9273 { "vunpckhpX", { XM
, Vex
, EXx
} },
9276 /* VEX_W_0F16_P_0_M_0 */
9277 { "vmovhps", { XM
, Vex128
, EXq
} },
9280 /* VEX_W_0F16_P_0_M_1 */
9281 { "vmovlhps", { XM
, Vex128
, EXq
} },
9284 /* VEX_W_0F16_P_1 */
9285 { "vmovshdup", { XM
, EXx
} },
9288 /* VEX_W_0F16_P_2 */
9289 { "vmovhpd", { XM
, Vex128
, EXq
} },
9292 /* VEX_W_0F17_M_0 */
9293 { "vmovhpX", { EXq
, XM
} },
9297 { "vmovapX", { XM
, EXx
} },
9301 { "vmovapX", { EXxS
, XM
} },
9304 /* VEX_W_0F2B_M_0 */
9305 { "vmovntpX", { Mx
, XM
} },
9308 /* VEX_W_0F2E_P_0 */
9309 { "vucomiss", { XMScalar
, EXdScalar
} },
9312 /* VEX_W_0F2E_P_2 */
9313 { "vucomisd", { XMScalar
, EXqScalar
} },
9316 /* VEX_W_0F2F_P_0 */
9317 { "vcomiss", { XMScalar
, EXdScalar
} },
9320 /* VEX_W_0F2F_P_2 */
9321 { "vcomisd", { XMScalar
, EXqScalar
} },
9324 /* VEX_W_0F50_M_0 */
9325 { "vmovmskpX", { Gdq
, XS
} },
9328 /* VEX_W_0F51_P_0 */
9329 { "vsqrtps", { XM
, EXx
} },
9332 /* VEX_W_0F51_P_1 */
9333 { "vsqrtss", { XMScalar
, VexScalar
, EXdScalar
} },
9336 /* VEX_W_0F51_P_2 */
9337 { "vsqrtpd", { XM
, EXx
} },
9340 /* VEX_W_0F51_P_3 */
9341 { "vsqrtsd", { XMScalar
, VexScalar
, EXqScalar
} },
9344 /* VEX_W_0F52_P_0 */
9345 { "vrsqrtps", { XM
, EXx
} },
9348 /* VEX_W_0F52_P_1 */
9349 { "vrsqrtss", { XMScalar
, VexScalar
, EXdScalar
} },
9352 /* VEX_W_0F53_P_0 */
9353 { "vrcpps", { XM
, EXx
} },
9356 /* VEX_W_0F53_P_1 */
9357 { "vrcpss", { XMScalar
, VexScalar
, EXdScalar
} },
9360 /* VEX_W_0F58_P_0 */
9361 { "vaddps", { XM
, Vex
, EXx
} },
9364 /* VEX_W_0F58_P_1 */
9365 { "vaddss", { XMScalar
, VexScalar
, EXdScalar
} },
9368 /* VEX_W_0F58_P_2 */
9369 { "vaddpd", { XM
, Vex
, EXx
} },
9372 /* VEX_W_0F58_P_3 */
9373 { "vaddsd", { XMScalar
, VexScalar
, EXqScalar
} },
9376 /* VEX_W_0F59_P_0 */
9377 { "vmulps", { XM
, Vex
, EXx
} },
9380 /* VEX_W_0F59_P_1 */
9381 { "vmulss", { XMScalar
, VexScalar
, EXdScalar
} },
9384 /* VEX_W_0F59_P_2 */
9385 { "vmulpd", { XM
, Vex
, EXx
} },
9388 /* VEX_W_0F59_P_3 */
9389 { "vmulsd", { XMScalar
, VexScalar
, EXqScalar
} },
9392 /* VEX_W_0F5A_P_0 */
9393 { "vcvtps2pd", { XM
, EXxmmq
} },
9396 /* VEX_W_0F5A_P_1 */
9397 { "vcvtss2sd", { XMScalar
, VexScalar
, EXdScalar
} },
9400 /* VEX_W_0F5A_P_3 */
9401 { "vcvtsd2ss", { XMScalar
, VexScalar
, EXqScalar
} },
9404 /* VEX_W_0F5B_P_0 */
9405 { "vcvtdq2ps", { XM
, EXx
} },
9408 /* VEX_W_0F5B_P_1 */
9409 { "vcvttps2dq", { XM
, EXx
} },
9412 /* VEX_W_0F5B_P_2 */
9413 { "vcvtps2dq", { XM
, EXx
} },
9416 /* VEX_W_0F5C_P_0 */
9417 { "vsubps", { XM
, Vex
, EXx
} },
9420 /* VEX_W_0F5C_P_1 */
9421 { "vsubss", { XMScalar
, VexScalar
, EXdScalar
} },
9424 /* VEX_W_0F5C_P_2 */
9425 { "vsubpd", { XM
, Vex
, EXx
} },
9428 /* VEX_W_0F5C_P_3 */
9429 { "vsubsd", { XMScalar
, VexScalar
, EXqScalar
} },
9432 /* VEX_W_0F5D_P_0 */
9433 { "vminps", { XM
, Vex
, EXx
} },
9436 /* VEX_W_0F5D_P_1 */
9437 { "vminss", { XMScalar
, VexScalar
, EXdScalar
} },
9440 /* VEX_W_0F5D_P_2 */
9441 { "vminpd", { XM
, Vex
, EXx
} },
9444 /* VEX_W_0F5D_P_3 */
9445 { "vminsd", { XMScalar
, VexScalar
, EXqScalar
} },
9448 /* VEX_W_0F5E_P_0 */
9449 { "vdivps", { XM
, Vex
, EXx
} },
9452 /* VEX_W_0F5E_P_1 */
9453 { "vdivss", { XMScalar
, VexScalar
, EXdScalar
} },
9456 /* VEX_W_0F5E_P_2 */
9457 { "vdivpd", { XM
, Vex
, EXx
} },
9460 /* VEX_W_0F5E_P_3 */
9461 { "vdivsd", { XMScalar
, VexScalar
, EXqScalar
} },
9464 /* VEX_W_0F5F_P_0 */
9465 { "vmaxps", { XM
, Vex
, EXx
} },
9468 /* VEX_W_0F5F_P_1 */
9469 { "vmaxss", { XMScalar
, VexScalar
, EXdScalar
} },
9472 /* VEX_W_0F5F_P_2 */
9473 { "vmaxpd", { XM
, Vex
, EXx
} },
9476 /* VEX_W_0F5F_P_3 */
9477 { "vmaxsd", { XMScalar
, VexScalar
, EXqScalar
} },
9480 /* VEX_W_0F60_P_2 */
9481 { "vpunpcklbw", { XM
, Vex128
, EXx
} },
9484 /* VEX_W_0F61_P_2 */
9485 { "vpunpcklwd", { XM
, Vex128
, EXx
} },
9488 /* VEX_W_0F62_P_2 */
9489 { "vpunpckldq", { XM
, Vex128
, EXx
} },
9492 /* VEX_W_0F63_P_2 */
9493 { "vpacksswb", { XM
, Vex128
, EXx
} },
9496 /* VEX_W_0F64_P_2 */
9497 { "vpcmpgtb", { XM
, Vex128
, EXx
} },
9500 /* VEX_W_0F65_P_2 */
9501 { "vpcmpgtw", { XM
, Vex128
, EXx
} },
9504 /* VEX_W_0F66_P_2 */
9505 { "vpcmpgtd", { XM
, Vex128
, EXx
} },
9508 /* VEX_W_0F67_P_2 */
9509 { "vpackuswb", { XM
, Vex128
, EXx
} },
9512 /* VEX_W_0F68_P_2 */
9513 { "vpunpckhbw", { XM
, Vex128
, EXx
} },
9516 /* VEX_W_0F69_P_2 */
9517 { "vpunpckhwd", { XM
, Vex128
, EXx
} },
9520 /* VEX_W_0F6A_P_2 */
9521 { "vpunpckhdq", { XM
, Vex128
, EXx
} },
9524 /* VEX_W_0F6B_P_2 */
9525 { "vpackssdw", { XM
, Vex128
, EXx
} },
9528 /* VEX_W_0F6C_P_2 */
9529 { "vpunpcklqdq", { XM
, Vex128
, EXx
} },
9532 /* VEX_W_0F6D_P_2 */
9533 { "vpunpckhqdq", { XM
, Vex128
, EXx
} },
9536 /* VEX_W_0F6F_P_1 */
9537 { "vmovdqu", { XM
, EXx
} },
9540 /* VEX_W_0F6F_P_2 */
9541 { "vmovdqa", { XM
, EXx
} },
9544 /* VEX_W_0F70_P_1 */
9545 { "vpshufhw", { XM
, EXx
, Ib
} },
9548 /* VEX_W_0F70_P_2 */
9549 { "vpshufd", { XM
, EXx
, Ib
} },
9552 /* VEX_W_0F70_P_3 */
9553 { "vpshuflw", { XM
, EXx
, Ib
} },
9556 /* VEX_W_0F71_R_2_P_2 */
9557 { "vpsrlw", { Vex128
, XS
, Ib
} },
9560 /* VEX_W_0F71_R_4_P_2 */
9561 { "vpsraw", { Vex128
, XS
, Ib
} },
9564 /* VEX_W_0F71_R_6_P_2 */
9565 { "vpsllw", { Vex128
, XS
, Ib
} },
9568 /* VEX_W_0F72_R_2_P_2 */
9569 { "vpsrld", { Vex128
, XS
, Ib
} },
9572 /* VEX_W_0F72_R_4_P_2 */
9573 { "vpsrad", { Vex128
, XS
, Ib
} },
9576 /* VEX_W_0F72_R_6_P_2 */
9577 { "vpslld", { Vex128
, XS
, Ib
} },
9580 /* VEX_W_0F73_R_2_P_2 */
9581 { "vpsrlq", { Vex128
, XS
, Ib
} },
9584 /* VEX_W_0F73_R_3_P_2 */
9585 { "vpsrldq", { Vex128
, XS
, Ib
} },
9588 /* VEX_W_0F73_R_6_P_2 */
9589 { "vpsllq", { Vex128
, XS
, Ib
} },
9592 /* VEX_W_0F73_R_7_P_2 */
9593 { "vpslldq", { Vex128
, XS
, Ib
} },
9596 /* VEX_W_0F74_P_2 */
9597 { "vpcmpeqb", { XM
, Vex128
, EXx
} },
9600 /* VEX_W_0F75_P_2 */
9601 { "vpcmpeqw", { XM
, Vex128
, EXx
} },
9604 /* VEX_W_0F76_P_2 */
9605 { "vpcmpeqd", { XM
, Vex128
, EXx
} },
9608 /* VEX_W_0F77_P_0 */
9612 /* VEX_W_0F7C_P_2 */
9613 { "vhaddpd", { XM
, Vex
, EXx
} },
9616 /* VEX_W_0F7C_P_3 */
9617 { "vhaddps", { XM
, Vex
, EXx
} },
9620 /* VEX_W_0F7D_P_2 */
9621 { "vhsubpd", { XM
, Vex
, EXx
} },
9624 /* VEX_W_0F7D_P_3 */
9625 { "vhsubps", { XM
, Vex
, EXx
} },
9628 /* VEX_W_0F7E_P_1 */
9629 { "vmovq", { XMScalar
, EXqScalar
} },
9632 /* VEX_W_0F7F_P_1 */
9633 { "vmovdqu", { EXxS
, XM
} },
9636 /* VEX_W_0F7F_P_2 */
9637 { "vmovdqa", { EXxS
, XM
} },
9640 /* VEX_W_0FAE_R_2_M_0 */
9641 { "vldmxcsr", { Md
} },
9644 /* VEX_W_0FAE_R_3_M_0 */
9645 { "vstmxcsr", { Md
} },
9648 /* VEX_W_0FC2_P_0 */
9649 { "vcmpps", { XM
, Vex
, EXx
, VCMP
} },
9652 /* VEX_W_0FC2_P_1 */
9653 { "vcmpss", { XMScalar
, VexScalar
, EXdScalar
, VCMP
} },
9656 /* VEX_W_0FC2_P_2 */
9657 { "vcmppd", { XM
, Vex
, EXx
, VCMP
} },
9660 /* VEX_W_0FC2_P_3 */
9661 { "vcmpsd", { XMScalar
, VexScalar
, EXqScalar
, VCMP
} },
9664 /* VEX_W_0FC4_P_2 */
9665 { "vpinsrw", { XM
, Vex128
, Edqw
, Ib
} },
9668 /* VEX_W_0FC5_P_2 */
9669 { "vpextrw", { Gdq
, XS
, Ib
} },
9672 /* VEX_W_0FD0_P_2 */
9673 { "vaddsubpd", { XM
, Vex
, EXx
} },
9676 /* VEX_W_0FD0_P_3 */
9677 { "vaddsubps", { XM
, Vex
, EXx
} },
9680 /* VEX_W_0FD1_P_2 */
9681 { "vpsrlw", { XM
, Vex128
, EXx
} },
9684 /* VEX_W_0FD2_P_2 */
9685 { "vpsrld", { XM
, Vex128
, EXx
} },
9688 /* VEX_W_0FD3_P_2 */
9689 { "vpsrlq", { XM
, Vex128
, EXx
} },
9692 /* VEX_W_0FD4_P_2 */
9693 { "vpaddq", { XM
, Vex128
, EXx
} },
9696 /* VEX_W_0FD5_P_2 */
9697 { "vpmullw", { XM
, Vex128
, EXx
} },
9700 /* VEX_W_0FD6_P_2 */
9701 { "vmovq", { EXqScalarS
, XMScalar
} },
9704 /* VEX_W_0FD7_P_2_M_1 */
9705 { "vpmovmskb", { Gdq
, XS
} },
9708 /* VEX_W_0FD8_P_2 */
9709 { "vpsubusb", { XM
, Vex128
, EXx
} },
9712 /* VEX_W_0FD9_P_2 */
9713 { "vpsubusw", { XM
, Vex128
, EXx
} },
9716 /* VEX_W_0FDA_P_2 */
9717 { "vpminub", { XM
, Vex128
, EXx
} },
9720 /* VEX_W_0FDB_P_2 */
9721 { "vpand", { XM
, Vex128
, EXx
} },
9724 /* VEX_W_0FDC_P_2 */
9725 { "vpaddusb", { XM
, Vex128
, EXx
} },
9728 /* VEX_W_0FDD_P_2 */
9729 { "vpaddusw", { XM
, Vex128
, EXx
} },
9732 /* VEX_W_0FDE_P_2 */
9733 { "vpmaxub", { XM
, Vex128
, EXx
} },
9736 /* VEX_W_0FDF_P_2 */
9737 { "vpandn", { XM
, Vex128
, EXx
} },
9740 /* VEX_W_0FE0_P_2 */
9741 { "vpavgb", { XM
, Vex128
, EXx
} },
9744 /* VEX_W_0FE1_P_2 */
9745 { "vpsraw", { XM
, Vex128
, EXx
} },
9748 /* VEX_W_0FE2_P_2 */
9749 { "vpsrad", { XM
, Vex128
, EXx
} },
9752 /* VEX_W_0FE3_P_2 */
9753 { "vpavgw", { XM
, Vex128
, EXx
} },
9756 /* VEX_W_0FE4_P_2 */
9757 { "vpmulhuw", { XM
, Vex128
, EXx
} },
9760 /* VEX_W_0FE5_P_2 */
9761 { "vpmulhw", { XM
, Vex128
, EXx
} },
9764 /* VEX_W_0FE6_P_1 */
9765 { "vcvtdq2pd", { XM
, EXxmmq
} },
9768 /* VEX_W_0FE6_P_2 */
9769 { "vcvttpd2dq%XY", { XMM
, EXx
} },
9772 /* VEX_W_0FE6_P_3 */
9773 { "vcvtpd2dq%XY", { XMM
, EXx
} },
9776 /* VEX_W_0FE7_P_2_M_0 */
9777 { "vmovntdq", { Mx
, XM
} },
9780 /* VEX_W_0FE8_P_2 */
9781 { "vpsubsb", { XM
, Vex128
, EXx
} },
9784 /* VEX_W_0FE9_P_2 */
9785 { "vpsubsw", { XM
, Vex128
, EXx
} },
9788 /* VEX_W_0FEA_P_2 */
9789 { "vpminsw", { XM
, Vex128
, EXx
} },
9792 /* VEX_W_0FEB_P_2 */
9793 { "vpor", { XM
, Vex128
, EXx
} },
9796 /* VEX_W_0FEC_P_2 */
9797 { "vpaddsb", { XM
, Vex128
, EXx
} },
9800 /* VEX_W_0FED_P_2 */
9801 { "vpaddsw", { XM
, Vex128
, EXx
} },
9804 /* VEX_W_0FEE_P_2 */
9805 { "vpmaxsw", { XM
, Vex128
, EXx
} },
9808 /* VEX_W_0FEF_P_2 */
9809 { "vpxor", { XM
, Vex128
, EXx
} },
9812 /* VEX_W_0FF0_P_3_M_0 */
9813 { "vlddqu", { XM
, M
} },
9816 /* VEX_W_0FF1_P_2 */
9817 { "vpsllw", { XM
, Vex128
, EXx
} },
9820 /* VEX_W_0FF2_P_2 */
9821 { "vpslld", { XM
, Vex128
, EXx
} },
9824 /* VEX_W_0FF3_P_2 */
9825 { "vpsllq", { XM
, Vex128
, EXx
} },
9828 /* VEX_W_0FF4_P_2 */
9829 { "vpmuludq", { XM
, Vex128
, EXx
} },
9832 /* VEX_W_0FF5_P_2 */
9833 { "vpmaddwd", { XM
, Vex128
, EXx
} },
9836 /* VEX_W_0FF6_P_2 */
9837 { "vpsadbw", { XM
, Vex128
, EXx
} },
9840 /* VEX_W_0FF7_P_2 */
9841 { "vmaskmovdqu", { XM
, XS
} },
9844 /* VEX_W_0FF8_P_2 */
9845 { "vpsubb", { XM
, Vex128
, EXx
} },
9848 /* VEX_W_0FF9_P_2 */
9849 { "vpsubw", { XM
, Vex128
, EXx
} },
9852 /* VEX_W_0FFA_P_2 */
9853 { "vpsubd", { XM
, Vex128
, EXx
} },
9856 /* VEX_W_0FFB_P_2 */
9857 { "vpsubq", { XM
, Vex128
, EXx
} },
9860 /* VEX_W_0FFC_P_2 */
9861 { "vpaddb", { XM
, Vex128
, EXx
} },
9864 /* VEX_W_0FFD_P_2 */
9865 { "vpaddw", { XM
, Vex128
, EXx
} },
9868 /* VEX_W_0FFE_P_2 */
9869 { "vpaddd", { XM
, Vex128
, EXx
} },
9872 /* VEX_W_0F3800_P_2 */
9873 { "vpshufb", { XM
, Vex128
, EXx
} },
9876 /* VEX_W_0F3801_P_2 */
9877 { "vphaddw", { XM
, Vex128
, EXx
} },
9880 /* VEX_W_0F3802_P_2 */
9881 { "vphaddd", { XM
, Vex128
, EXx
} },
9884 /* VEX_W_0F3803_P_2 */
9885 { "vphaddsw", { XM
, Vex128
, EXx
} },
9888 /* VEX_W_0F3804_P_2 */
9889 { "vpmaddubsw", { XM
, Vex128
, EXx
} },
9892 /* VEX_W_0F3805_P_2 */
9893 { "vphsubw", { XM
, Vex128
, EXx
} },
9896 /* VEX_W_0F3806_P_2 */
9897 { "vphsubd", { XM
, Vex128
, EXx
} },
9900 /* VEX_W_0F3807_P_2 */
9901 { "vphsubsw", { XM
, Vex128
, EXx
} },
9904 /* VEX_W_0F3808_P_2 */
9905 { "vpsignb", { XM
, Vex128
, EXx
} },
9908 /* VEX_W_0F3809_P_2 */
9909 { "vpsignw", { XM
, Vex128
, EXx
} },
9912 /* VEX_W_0F380A_P_2 */
9913 { "vpsignd", { XM
, Vex128
, EXx
} },
9916 /* VEX_W_0F380B_P_2 */
9917 { "vpmulhrsw", { XM
, Vex128
, EXx
} },
9920 /* VEX_W_0F380C_P_2 */
9921 { "vpermilps", { XM
, Vex
, EXx
} },
9924 /* VEX_W_0F380D_P_2 */
9925 { "vpermilpd", { XM
, Vex
, EXx
} },
9928 /* VEX_W_0F380E_P_2 */
9929 { "vtestps", { XM
, EXx
} },
9932 /* VEX_W_0F380F_P_2 */
9933 { "vtestpd", { XM
, EXx
} },
9936 /* VEX_W_0F3817_P_2 */
9937 { "vptest", { XM
, EXx
} },
9940 /* VEX_W_0F3818_P_2_M_0 */
9941 { "vbroadcastss", { XM
, Md
} },
9944 /* VEX_W_0F3819_P_2_M_0 */
9945 { "vbroadcastsd", { XM
, Mq
} },
9948 /* VEX_W_0F381A_P_2_M_0 */
9949 { "vbroadcastf128", { XM
, Mxmm
} },
9952 /* VEX_W_0F381C_P_2 */
9953 { "vpabsb", { XM
, EXx
} },
9956 /* VEX_W_0F381D_P_2 */
9957 { "vpabsw", { XM
, EXx
} },
9960 /* VEX_W_0F381E_P_2 */
9961 { "vpabsd", { XM
, EXx
} },
9964 /* VEX_W_0F3820_P_2 */
9965 { "vpmovsxbw", { XM
, EXq
} },
9968 /* VEX_W_0F3821_P_2 */
9969 { "vpmovsxbd", { XM
, EXd
} },
9972 /* VEX_W_0F3822_P_2 */
9973 { "vpmovsxbq", { XM
, EXw
} },
9976 /* VEX_W_0F3823_P_2 */
9977 { "vpmovsxwd", { XM
, EXq
} },
9980 /* VEX_W_0F3824_P_2 */
9981 { "vpmovsxwq", { XM
, EXd
} },
9984 /* VEX_W_0F3825_P_2 */
9985 { "vpmovsxdq", { XM
, EXq
} },
9988 /* VEX_W_0F3828_P_2 */
9989 { "vpmuldq", { XM
, Vex128
, EXx
} },
9992 /* VEX_W_0F3829_P_2 */
9993 { "vpcmpeqq", { XM
, Vex128
, EXx
} },
9996 /* VEX_W_0F382A_P_2_M_0 */
9997 { "vmovntdqa", { XM
, Mx
} },
10000 /* VEX_W_0F382B_P_2 */
10001 { "vpackusdw", { XM
, Vex128
, EXx
} },
10004 /* VEX_W_0F382C_P_2_M_0 */
10005 { "vmaskmovps", { XM
, Vex
, Mx
} },
10008 /* VEX_W_0F382D_P_2_M_0 */
10009 { "vmaskmovpd", { XM
, Vex
, Mx
} },
10012 /* VEX_W_0F382E_P_2_M_0 */
10013 { "vmaskmovps", { Mx
, Vex
, XM
} },
10016 /* VEX_W_0F382F_P_2_M_0 */
10017 { "vmaskmovpd", { Mx
, Vex
, XM
} },
10020 /* VEX_W_0F3830_P_2 */
10021 { "vpmovzxbw", { XM
, EXq
} },
10024 /* VEX_W_0F3831_P_2 */
10025 { "vpmovzxbd", { XM
, EXd
} },
10028 /* VEX_W_0F3832_P_2 */
10029 { "vpmovzxbq", { XM
, EXw
} },
10032 /* VEX_W_0F3833_P_2 */
10033 { "vpmovzxwd", { XM
, EXq
} },
10036 /* VEX_W_0F3834_P_2 */
10037 { "vpmovzxwq", { XM
, EXd
} },
10040 /* VEX_W_0F3835_P_2 */
10041 { "vpmovzxdq", { XM
, EXq
} },
10044 /* VEX_W_0F3837_P_2 */
10045 { "vpcmpgtq", { XM
, Vex128
, EXx
} },
10048 /* VEX_W_0F3838_P_2 */
10049 { "vpminsb", { XM
, Vex128
, EXx
} },
10052 /* VEX_W_0F3839_P_2 */
10053 { "vpminsd", { XM
, Vex128
, EXx
} },
10056 /* VEX_W_0F383A_P_2 */
10057 { "vpminuw", { XM
, Vex128
, EXx
} },
10060 /* VEX_W_0F383B_P_2 */
10061 { "vpminud", { XM
, Vex128
, EXx
} },
10064 /* VEX_W_0F383C_P_2 */
10065 { "vpmaxsb", { XM
, Vex128
, EXx
} },
10068 /* VEX_W_0F383D_P_2 */
10069 { "vpmaxsd", { XM
, Vex128
, EXx
} },
10072 /* VEX_W_0F383E_P_2 */
10073 { "vpmaxuw", { XM
, Vex128
, EXx
} },
10076 /* VEX_W_0F383F_P_2 */
10077 { "vpmaxud", { XM
, Vex128
, EXx
} },
10080 /* VEX_W_0F3840_P_2 */
10081 { "vpmulld", { XM
, Vex128
, EXx
} },
10084 /* VEX_W_0F3841_P_2 */
10085 { "vphminposuw", { XM
, EXx
} },
10088 /* VEX_W_0F38DB_P_2 */
10089 { "vaesimc", { XM
, EXx
} },
10092 /* VEX_W_0F38DC_P_2 */
10093 { "vaesenc", { XM
, Vex128
, EXx
} },
10096 /* VEX_W_0F38DD_P_2 */
10097 { "vaesenclast", { XM
, Vex128
, EXx
} },
10100 /* VEX_W_0F38DE_P_2 */
10101 { "vaesdec", { XM
, Vex128
, EXx
} },
10104 /* VEX_W_0F38DF_P_2 */
10105 { "vaesdeclast", { XM
, Vex128
, EXx
} },
10108 /* VEX_W_0F3A04_P_2 */
10109 { "vpermilps", { XM
, EXx
, Ib
} },
10112 /* VEX_W_0F3A05_P_2 */
10113 { "vpermilpd", { XM
, EXx
, Ib
} },
10116 /* VEX_W_0F3A06_P_2 */
10117 { "vperm2f128", { XM
, Vex256
, EXx
, Ib
} },
10120 /* VEX_W_0F3A08_P_2 */
10121 { "vroundps", { XM
, EXx
, Ib
} },
10124 /* VEX_W_0F3A09_P_2 */
10125 { "vroundpd", { XM
, EXx
, Ib
} },
10128 /* VEX_W_0F3A0A_P_2 */
10129 { "vroundss", { XMScalar
, VexScalar
, EXdScalar
, Ib
} },
10132 /* VEX_W_0F3A0B_P_2 */
10133 { "vroundsd", { XMScalar
, VexScalar
, EXqScalar
, Ib
} },
10136 /* VEX_W_0F3A0C_P_2 */
10137 { "vblendps", { XM
, Vex
, EXx
, Ib
} },
10140 /* VEX_W_0F3A0D_P_2 */
10141 { "vblendpd", { XM
, Vex
, EXx
, Ib
} },
10144 /* VEX_W_0F3A0E_P_2 */
10145 { "vpblendw", { XM
, Vex128
, EXx
, Ib
} },
10148 /* VEX_W_0F3A0F_P_2 */
10149 { "vpalignr", { XM
, Vex128
, EXx
, Ib
} },
10152 /* VEX_W_0F3A14_P_2 */
10153 { "vpextrb", { Edqb
, XM
, Ib
} },
10156 /* VEX_W_0F3A15_P_2 */
10157 { "vpextrw", { Edqw
, XM
, Ib
} },
10160 /* VEX_W_0F3A18_P_2 */
10161 { "vinsertf128", { XM
, Vex256
, EXxmm
, Ib
} },
10164 /* VEX_W_0F3A19_P_2 */
10165 { "vextractf128", { EXxmm
, XM
, Ib
} },
10168 /* VEX_W_0F3A20_P_2 */
10169 { "vpinsrb", { XM
, Vex128
, Edqb
, Ib
} },
10172 /* VEX_W_0F3A21_P_2 */
10173 { "vinsertps", { XM
, Vex128
, EXd
, Ib
} },
10176 /* VEX_W_0F3A40_P_2 */
10177 { "vdpps", { XM
, Vex
, EXx
, Ib
} },
10180 /* VEX_W_0F3A41_P_2 */
10181 { "vdppd", { XM
, Vex128
, EXx
, Ib
} },
10184 /* VEX_W_0F3A42_P_2 */
10185 { "vmpsadbw", { XM
, Vex128
, EXx
, Ib
} },
10188 /* VEX_W_0F3A44_P_2 */
10189 { "vpclmulqdq", { XM
, Vex128
, EXx
, PCLMUL
} },
10192 /* VEX_W_0F3A48_P_2 */
10193 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
} },
10194 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
} },
10197 /* VEX_W_0F3A49_P_2 */
10198 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
} },
10199 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
} },
10202 /* VEX_W_0F3A4A_P_2 */
10203 { "vblendvps", { XM
, Vex
, EXx
, XMVexI4
} },
10206 /* VEX_W_0F3A4B_P_2 */
10207 { "vblendvpd", { XM
, Vex
, EXx
, XMVexI4
} },
10210 /* VEX_W_0F3A4C_P_2 */
10211 { "vpblendvb", { XM
, Vex128
, EXx
, XMVexI4
} },
10214 /* VEX_W_0F3A60_P_2 */
10215 { "vpcmpestrm", { XM
, EXx
, Ib
} },
10218 /* VEX_W_0F3A61_P_2 */
10219 { "vpcmpestri", { XM
, EXx
, Ib
} },
10222 /* VEX_W_0F3A62_P_2 */
10223 { "vpcmpistrm", { XM
, EXx
, Ib
} },
10226 /* VEX_W_0F3A63_P_2 */
10227 { "vpcmpistri", { XM
, EXx
, Ib
} },
10230 /* VEX_W_0F3ADF_P_2 */
10231 { "vaeskeygenassist", { XM
, EXx
, Ib
} },
10235 static const struct dis386 mod_table
[][2] = {
10238 { "leaS", { Gv
, M
} },
10241 /* MOD_0F01_REG_0 */
10242 { X86_64_TABLE (X86_64_0F01_REG_0
) },
10243 { RM_TABLE (RM_0F01_REG_0
) },
10246 /* MOD_0F01_REG_1 */
10247 { X86_64_TABLE (X86_64_0F01_REG_1
) },
10248 { RM_TABLE (RM_0F01_REG_1
) },
10251 /* MOD_0F01_REG_2 */
10252 { X86_64_TABLE (X86_64_0F01_REG_2
) },
10253 { RM_TABLE (RM_0F01_REG_2
) },
10256 /* MOD_0F01_REG_3 */
10257 { X86_64_TABLE (X86_64_0F01_REG_3
) },
10258 { RM_TABLE (RM_0F01_REG_3
) },
10261 /* MOD_0F01_REG_7 */
10262 { "invlpg", { Mb
} },
10263 { RM_TABLE (RM_0F01_REG_7
) },
10266 /* MOD_0F12_PREFIX_0 */
10267 { "movlps", { XM
, EXq
} },
10268 { "movhlps", { XM
, EXq
} },
10272 { "movlpX", { EXq
, XM
} },
10275 /* MOD_0F16_PREFIX_0 */
10276 { "movhps", { XM
, EXq
} },
10277 { "movlhps", { XM
, EXq
} },
10281 { "movhpX", { EXq
, XM
} },
10284 /* MOD_0F18_REG_0 */
10285 { "prefetchnta", { Mb
} },
10288 /* MOD_0F18_REG_1 */
10289 { "prefetcht0", { Mb
} },
10292 /* MOD_0F18_REG_2 */
10293 { "prefetcht1", { Mb
} },
10296 /* MOD_0F18_REG_3 */
10297 { "prefetcht2", { Mb
} },
10302 { "movZ", { Rm
, Cm
} },
10307 { "movZ", { Rm
, Dm
} },
10312 { "movZ", { Cm
, Rm
} },
10317 { "movZ", { Dm
, Rm
} },
10322 { "movL", { Rd
, Td
} },
10327 { "movL", { Td
, Rd
} },
10330 /* MOD_0F2B_PREFIX_0 */
10331 {"movntps", { Mx
, XM
} },
10334 /* MOD_0F2B_PREFIX_1 */
10335 {"movntss", { Md
, XM
} },
10338 /* MOD_0F2B_PREFIX_2 */
10339 {"movntpd", { Mx
, XM
} },
10342 /* MOD_0F2B_PREFIX_3 */
10343 {"movntsd", { Mq
, XM
} },
10348 { "movmskpX", { Gdq
, XS
} },
10351 /* MOD_0F71_REG_2 */
10353 { "psrlw", { MS
, Ib
} },
10356 /* MOD_0F71_REG_4 */
10358 { "psraw", { MS
, Ib
} },
10361 /* MOD_0F71_REG_6 */
10363 { "psllw", { MS
, Ib
} },
10366 /* MOD_0F72_REG_2 */
10368 { "psrld", { MS
, Ib
} },
10371 /* MOD_0F72_REG_4 */
10373 { "psrad", { MS
, Ib
} },
10376 /* MOD_0F72_REG_6 */
10378 { "pslld", { MS
, Ib
} },
10381 /* MOD_0F73_REG_2 */
10383 { "psrlq", { MS
, Ib
} },
10386 /* MOD_0F73_REG_3 */
10388 { PREFIX_TABLE (PREFIX_0F73_REG_3
) },
10391 /* MOD_0F73_REG_6 */
10393 { "psllq", { MS
, Ib
} },
10396 /* MOD_0F73_REG_7 */
10398 { PREFIX_TABLE (PREFIX_0F73_REG_7
) },
10401 /* MOD_0FAE_REG_0 */
10402 { "fxsave", { FXSAVE
} },
10403 { PREFIX_TABLE (PREFIX_0FAE_REG_0
) },
10406 /* MOD_0FAE_REG_1 */
10407 { "fxrstor", { FXSAVE
} },
10408 { PREFIX_TABLE (PREFIX_0FAE_REG_1
) },
10411 /* MOD_0FAE_REG_2 */
10412 { "ldmxcsr", { Md
} },
10413 { PREFIX_TABLE (PREFIX_0FAE_REG_2
) },
10416 /* MOD_0FAE_REG_3 */
10417 { "stmxcsr", { Md
} },
10418 { PREFIX_TABLE (PREFIX_0FAE_REG_3
) },
10421 /* MOD_0FAE_REG_4 */
10422 { "xsave", { FXSAVE
} },
10425 /* MOD_0FAE_REG_5 */
10426 { "xrstor", { FXSAVE
} },
10427 { RM_TABLE (RM_0FAE_REG_5
) },
10430 /* MOD_0FAE_REG_6 */
10431 { "xsaveopt", { FXSAVE
} },
10432 { RM_TABLE (RM_0FAE_REG_6
) },
10435 /* MOD_0FAE_REG_7 */
10436 { "clflush", { Mb
} },
10437 { RM_TABLE (RM_0FAE_REG_7
) },
10441 { "lssS", { Gv
, Mp
} },
10445 { "lfsS", { Gv
, Mp
} },
10449 { "lgsS", { Gv
, Mp
} },
10452 /* MOD_0FC7_REG_6 */
10453 { PREFIX_TABLE (PREFIX_0FC7_REG_6
) },
10454 { "rdrand", { Ev
} },
10457 /* MOD_0FC7_REG_7 */
10458 { "vmptrst", { Mq
} },
10463 { "pmovmskb", { Gdq
, MS
} },
10466 /* MOD_0FE7_PREFIX_2 */
10467 { "movntdq", { Mx
, XM
} },
10470 /* MOD_0FF0_PREFIX_3 */
10471 { "lddqu", { XM
, M
} },
10474 /* MOD_0F382A_PREFIX_2 */
10475 { "movntdqa", { XM
, Mx
} },
10479 { "bound{S|}", { Gv
, Ma
} },
10483 { "lesS", { Gv
, Mp
} },
10484 { VEX_C4_TABLE (VEX_0F
) },
10488 { "ldsS", { Gv
, Mp
} },
10489 { VEX_C5_TABLE (VEX_0F
) },
10492 /* MOD_VEX_0F12_PREFIX_0 */
10493 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0
) },
10494 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1
) },
10498 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0
) },
10501 /* MOD_VEX_0F16_PREFIX_0 */
10502 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0
) },
10503 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1
) },
10507 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0
) },
10511 { VEX_W_TABLE (VEX_W_0F2B_M_0
) },
10516 { VEX_W_TABLE (VEX_W_0F50_M_0
) },
10519 /* MOD_VEX_0F71_REG_2 */
10521 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2
) },
10524 /* MOD_VEX_0F71_REG_4 */
10526 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4
) },
10529 /* MOD_VEX_0F71_REG_6 */
10531 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6
) },
10534 /* MOD_VEX_0F72_REG_2 */
10536 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2
) },
10539 /* MOD_VEX_0F72_REG_4 */
10541 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4
) },
10544 /* MOD_VEX_0F72_REG_6 */
10546 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6
) },
10549 /* MOD_VEX_0F73_REG_2 */
10551 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2
) },
10554 /* MOD_VEX_0F73_REG_3 */
10556 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3
) },
10559 /* MOD_VEX_0F73_REG_6 */
10561 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6
) },
10564 /* MOD_VEX_0F73_REG_7 */
10566 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7
) },
10569 /* MOD_VEX_0FAE_REG_2 */
10570 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0
) },
10573 /* MOD_VEX_0FAE_REG_3 */
10574 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0
) },
10577 /* MOD_VEX_0FD7_PREFIX_2 */
10579 { VEX_LEN_TABLE (VEX_LEN_0FD7_P_2_M_1
) },
10582 /* MOD_VEX_0FE7_PREFIX_2 */
10583 { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0
) },
10586 /* MOD_VEX_0FF0_PREFIX_3 */
10587 { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0
) },
10590 /* MOD_VEX_0F3818_PREFIX_2 */
10591 { VEX_W_TABLE (VEX_W_0F3818_P_2_M_0
) },
10594 /* MOD_VEX_0F3819_PREFIX_2 */
10595 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2_M_0
) },
10598 /* MOD_VEX_0F381A_PREFIX_2 */
10599 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0
) },
10602 /* MOD_VEX_0F382A_PREFIX_2 */
10603 { VEX_LEN_TABLE (VEX_LEN_0F382A_P_2_M_0
) },
10606 /* MOD_VEX_0F382C_PREFIX_2 */
10607 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0
) },
10610 /* MOD_VEX_0F382D_PREFIX_2 */
10611 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0
) },
10614 /* MOD_VEX_0F382E_PREFIX_2 */
10615 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0
) },
10618 /* MOD_VEX_0F382F_PREFIX_2 */
10619 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0
) },
10623 static const struct dis386 rm_table
[][8] = {
10625 /* RM_0F01_REG_0 */
10627 { "vmcall", { Skip_MODRM
} },
10628 { "vmlaunch", { Skip_MODRM
} },
10629 { "vmresume", { Skip_MODRM
} },
10630 { "vmxoff", { Skip_MODRM
} },
10633 /* RM_0F01_REG_1 */
10634 { "monitor", { { OP_Monitor
, 0 } } },
10635 { "mwait", { { OP_Mwait
, 0 } } },
10638 /* RM_0F01_REG_2 */
10639 { "xgetbv", { Skip_MODRM
} },
10640 { "xsetbv", { Skip_MODRM
} },
10643 /* RM_0F01_REG_3 */
10644 { "vmrun", { Skip_MODRM
} },
10645 { "vmmcall", { Skip_MODRM
} },
10646 { "vmload", { Skip_MODRM
} },
10647 { "vmsave", { Skip_MODRM
} },
10648 { "stgi", { Skip_MODRM
} },
10649 { "clgi", { Skip_MODRM
} },
10650 { "skinit", { Skip_MODRM
} },
10651 { "invlpga", { Skip_MODRM
} },
10654 /* RM_0F01_REG_7 */
10655 { "swapgs", { Skip_MODRM
} },
10656 { "rdtscp", { Skip_MODRM
} },
10659 /* RM_0FAE_REG_5 */
10660 { "lfence", { Skip_MODRM
} },
10663 /* RM_0FAE_REG_6 */
10664 { "mfence", { Skip_MODRM
} },
10667 /* RM_0FAE_REG_7 */
10668 { "sfence", { Skip_MODRM
} },
10672 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
10674 /* We use the high bit to indicate different name for the same
10676 #define ADDR16_PREFIX (0x67 | 0x100)
10677 #define ADDR32_PREFIX (0x67 | 0x200)
10678 #define DATA16_PREFIX (0x66 | 0x100)
10679 #define DATA32_PREFIX (0x66 | 0x200)
10680 #define REP_PREFIX (0xf3 | 0x100)
10685 int newrex
, i
, length
;
10691 last_lock_prefix
= -1;
10692 last_repz_prefix
= -1;
10693 last_repnz_prefix
= -1;
10694 last_data_prefix
= -1;
10695 last_addr_prefix
= -1;
10696 last_rex_prefix
= -1;
10697 last_seg_prefix
= -1;
10698 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
10699 all_prefixes
[i
] = 0;
10702 /* The maximum instruction length is 15bytes. */
10703 while (length
< MAX_CODE_LENGTH
- 1)
10705 FETCH_DATA (the_info
, codep
+ 1);
10709 /* REX prefixes family. */
10726 if (address_mode
== mode_64bit
)
10730 last_rex_prefix
= i
;
10733 prefixes
|= PREFIX_REPZ
;
10734 last_repz_prefix
= i
;
10737 prefixes
|= PREFIX_REPNZ
;
10738 last_repnz_prefix
= i
;
10741 prefixes
|= PREFIX_LOCK
;
10742 last_lock_prefix
= i
;
10745 prefixes
|= PREFIX_CS
;
10746 last_seg_prefix
= i
;
10749 prefixes
|= PREFIX_SS
;
10750 last_seg_prefix
= i
;
10753 prefixes
|= PREFIX_DS
;
10754 last_seg_prefix
= i
;
10757 prefixes
|= PREFIX_ES
;
10758 last_seg_prefix
= i
;
10761 prefixes
|= PREFIX_FS
;
10762 last_seg_prefix
= i
;
10765 prefixes
|= PREFIX_GS
;
10766 last_seg_prefix
= i
;
10769 prefixes
|= PREFIX_DATA
;
10770 last_data_prefix
= i
;
10773 prefixes
|= PREFIX_ADDR
;
10774 last_addr_prefix
= i
;
10777 /* fwait is really an instruction. If there are prefixes
10778 before the fwait, they belong to the fwait, *not* to the
10779 following instruction. */
10780 if (prefixes
|| rex
)
10782 prefixes
|= PREFIX_FWAIT
;
10786 prefixes
= PREFIX_FWAIT
;
10791 /* Rex is ignored when followed by another prefix. */
10797 if (*codep
!= FWAIT_OPCODE
)
10798 all_prefixes
[i
++] = *codep
;
10807 seg_prefix (int pref
)
10828 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
10831 static const char *
10832 prefix_name (int pref
, int sizeflag
)
10834 static const char *rexes
[16] =
10837 "rex.B", /* 0x41 */
10838 "rex.X", /* 0x42 */
10839 "rex.XB", /* 0x43 */
10840 "rex.R", /* 0x44 */
10841 "rex.RB", /* 0x45 */
10842 "rex.RX", /* 0x46 */
10843 "rex.RXB", /* 0x47 */
10844 "rex.W", /* 0x48 */
10845 "rex.WB", /* 0x49 */
10846 "rex.WX", /* 0x4a */
10847 "rex.WXB", /* 0x4b */
10848 "rex.WR", /* 0x4c */
10849 "rex.WRB", /* 0x4d */
10850 "rex.WRX", /* 0x4e */
10851 "rex.WRXB", /* 0x4f */
10856 /* REX prefixes family. */
10873 return rexes
[pref
- 0x40];
10893 return (sizeflag
& DFLAG
) ? "data16" : "data32";
10895 if (address_mode
== mode_64bit
)
10896 return (sizeflag
& AFLAG
) ? "addr32" : "addr64";
10898 return (sizeflag
& AFLAG
) ? "addr16" : "addr32";
10901 case ADDR16_PREFIX
:
10903 case ADDR32_PREFIX
:
10905 case DATA16_PREFIX
:
10907 case DATA32_PREFIX
:
10916 static char op_out
[MAX_OPERANDS
][100];
10917 static int op_ad
, op_index
[MAX_OPERANDS
];
10918 static int two_source_ops
;
10919 static bfd_vma op_address
[MAX_OPERANDS
];
10920 static bfd_vma op_riprel
[MAX_OPERANDS
];
10921 static bfd_vma start_pc
;
10924 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
10925 * (see topic "Redundant prefixes" in the "Differences from 8086"
10926 * section of the "Virtual 8086 Mode" chapter.)
10927 * 'pc' should be the address of this instruction, it will
10928 * be used to print the target address if this is a relative jump or call
10929 * The function returns the length of this instruction in bytes.
10932 static char intel_syntax
;
10933 static char intel_mnemonic
= !SYSV386_COMPAT
;
10934 static char open_char
;
10935 static char close_char
;
10936 static char separator_char
;
10937 static char scale_char
;
10939 /* Here for backwards compatibility. When gdb stops using
10940 print_insn_i386_att and print_insn_i386_intel these functions can
10941 disappear, and print_insn_i386 be merged into print_insn. */
10943 print_insn_i386_att (bfd_vma pc
, disassemble_info
*info
)
10947 return print_insn (pc
, info
);
10951 print_insn_i386_intel (bfd_vma pc
, disassemble_info
*info
)
10955 return print_insn (pc
, info
);
10959 print_insn_i386 (bfd_vma pc
, disassemble_info
*info
)
10963 return print_insn (pc
, info
);
10967 print_i386_disassembler_options (FILE *stream
)
10969 fprintf (stream
, _("\n\
10970 The following i386/x86-64 specific disassembler options are supported for use\n\
10971 with the -M switch (multiple options should be separated by commas):\n"));
10973 fprintf (stream
, _(" x86-64 Disassemble in 64bit mode\n"));
10974 fprintf (stream
, _(" i386 Disassemble in 32bit mode\n"));
10975 fprintf (stream
, _(" i8086 Disassemble in 16bit mode\n"));
10976 fprintf (stream
, _(" att Display instruction in AT&T syntax\n"));
10977 fprintf (stream
, _(" intel Display instruction in Intel syntax\n"));
10978 fprintf (stream
, _(" att-mnemonic\n"
10979 " Display instruction in AT&T mnemonic\n"));
10980 fprintf (stream
, _(" intel-mnemonic\n"
10981 " Display instruction in Intel mnemonic\n"));
10982 fprintf (stream
, _(" addr64 Assume 64bit address size\n"));
10983 fprintf (stream
, _(" addr32 Assume 32bit address size\n"));
10984 fprintf (stream
, _(" addr16 Assume 16bit address size\n"));
10985 fprintf (stream
, _(" data32 Assume 32bit data size\n"));
10986 fprintf (stream
, _(" data16 Assume 16bit data size\n"));
10987 fprintf (stream
, _(" suffix Always display instruction suffix in AT&T syntax\n"));
10991 static const struct dis386 bad_opcode
= { "(bad)", { XX
} };
10993 /* Get a pointer to struct dis386 with a valid name. */
10995 static const struct dis386
*
10996 get_valid_dis386 (const struct dis386
*dp
, disassemble_info
*info
)
10998 int vindex
, vex_table_index
;
11000 if (dp
->name
!= NULL
)
11003 switch (dp
->op
[0].bytemode
)
11005 case USE_REG_TABLE
:
11006 dp
= ®_table
[dp
->op
[1].bytemode
][modrm
.reg
];
11009 case USE_MOD_TABLE
:
11010 vindex
= modrm
.mod
== 0x3 ? 1 : 0;
11011 dp
= &mod_table
[dp
->op
[1].bytemode
][vindex
];
11015 dp
= &rm_table
[dp
->op
[1].bytemode
][modrm
.rm
];
11018 case USE_PREFIX_TABLE
:
11021 /* The prefix in VEX is implicit. */
11022 switch (vex
.prefix
)
11027 case REPE_PREFIX_OPCODE
:
11030 case DATA_PREFIX_OPCODE
:
11033 case REPNE_PREFIX_OPCODE
:
11044 used_prefixes
|= (prefixes
& PREFIX_REPZ
);
11045 if (prefixes
& PREFIX_REPZ
)
11048 all_prefixes
[last_repz_prefix
] = 0;
11052 /* We should check PREFIX_REPNZ and PREFIX_REPZ before
11054 used_prefixes
|= (prefixes
& PREFIX_REPNZ
);
11055 if (prefixes
& PREFIX_REPNZ
)
11058 all_prefixes
[last_repnz_prefix
] = 0;
11062 used_prefixes
|= (prefixes
& PREFIX_DATA
);
11063 if (prefixes
& PREFIX_DATA
)
11066 all_prefixes
[last_data_prefix
] = 0;
11071 dp
= &prefix_table
[dp
->op
[1].bytemode
][vindex
];
11074 case USE_X86_64_TABLE
:
11075 vindex
= address_mode
== mode_64bit
? 1 : 0;
11076 dp
= &x86_64_table
[dp
->op
[1].bytemode
][vindex
];
11079 case USE_3BYTE_TABLE
:
11080 FETCH_DATA (info
, codep
+ 2);
11082 dp
= &three_byte_table
[dp
->op
[1].bytemode
][vindex
];
11083 modrm
.mod
= (*codep
>> 6) & 3;
11084 modrm
.reg
= (*codep
>> 3) & 7;
11085 modrm
.rm
= *codep
& 7;
11088 case USE_VEX_LEN_TABLE
:
11092 switch (vex
.length
)
11105 dp
= &vex_len_table
[dp
->op
[1].bytemode
][vindex
];
11108 case USE_XOP_8F_TABLE
:
11109 FETCH_DATA (info
, codep
+ 3);
11110 /* All bits in the REX prefix are ignored. */
11112 rex
= ~(*codep
>> 5) & 0x7;
11114 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
11115 switch ((*codep
& 0x1f))
11121 vex_table_index
= XOP_08
;
11124 vex_table_index
= XOP_09
;
11127 vex_table_index
= XOP_0A
;
11131 vex
.w
= *codep
& 0x80;
11132 if (vex
.w
&& address_mode
== mode_64bit
)
11135 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11136 if (address_mode
!= mode_64bit
11137 && vex
.register_specifier
> 0x7)
11143 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11144 switch ((*codep
& 0x3))
11150 vex
.prefix
= DATA_PREFIX_OPCODE
;
11153 vex
.prefix
= REPE_PREFIX_OPCODE
;
11156 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11163 dp
= &xop_table
[vex_table_index
][vindex
];
11165 FETCH_DATA (info
, codep
+ 1);
11166 modrm
.mod
= (*codep
>> 6) & 3;
11167 modrm
.reg
= (*codep
>> 3) & 7;
11168 modrm
.rm
= *codep
& 7;
11171 case USE_VEX_C4_TABLE
:
11172 FETCH_DATA (info
, codep
+ 3);
11173 /* All bits in the REX prefix are ignored. */
11175 rex
= ~(*codep
>> 5) & 0x7;
11176 switch ((*codep
& 0x1f))
11182 vex_table_index
= VEX_0F
;
11185 vex_table_index
= VEX_0F38
;
11188 vex_table_index
= VEX_0F3A
;
11192 vex
.w
= *codep
& 0x80;
11193 if (vex
.w
&& address_mode
== mode_64bit
)
11196 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11197 if (address_mode
!= mode_64bit
11198 && vex
.register_specifier
> 0x7)
11204 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11205 switch ((*codep
& 0x3))
11211 vex
.prefix
= DATA_PREFIX_OPCODE
;
11214 vex
.prefix
= REPE_PREFIX_OPCODE
;
11217 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11224 dp
= &vex_table
[vex_table_index
][vindex
];
11225 /* There is no MODRM byte for VEX [82|77]. */
11226 if (vindex
!= 0x77 && vindex
!= 0x82)
11228 FETCH_DATA (info
, codep
+ 1);
11229 modrm
.mod
= (*codep
>> 6) & 3;
11230 modrm
.reg
= (*codep
>> 3) & 7;
11231 modrm
.rm
= *codep
& 7;
11235 case USE_VEX_C5_TABLE
:
11236 FETCH_DATA (info
, codep
+ 2);
11237 /* All bits in the REX prefix are ignored. */
11239 rex
= (*codep
& 0x80) ? 0 : REX_R
;
11241 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11242 if (address_mode
!= mode_64bit
11243 && vex
.register_specifier
> 0x7)
11251 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11252 switch ((*codep
& 0x3))
11258 vex
.prefix
= DATA_PREFIX_OPCODE
;
11261 vex
.prefix
= REPE_PREFIX_OPCODE
;
11264 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11271 dp
= &vex_table
[dp
->op
[1].bytemode
][vindex
];
11272 /* There is no MODRM byte for VEX [82|77]. */
11273 if (vindex
!= 0x77 && vindex
!= 0x82)
11275 FETCH_DATA (info
, codep
+ 1);
11276 modrm
.mod
= (*codep
>> 6) & 3;
11277 modrm
.reg
= (*codep
>> 3) & 7;
11278 modrm
.rm
= *codep
& 7;
11282 case USE_VEX_W_TABLE
:
11286 dp
= &vex_w_table
[dp
->op
[1].bytemode
][vex
.w
? 1 : 0];
11297 if (dp
->name
!= NULL
)
11300 return get_valid_dis386 (dp
, info
);
11304 get_sib (disassemble_info
*info
)
11306 /* If modrm.mod == 3, operand must be register. */
11308 && address_mode
!= mode_16bit
11312 FETCH_DATA (info
, codep
+ 2);
11313 sib
.index
= (codep
[1] >> 3) & 7;
11314 sib
.scale
= (codep
[1] >> 6) & 3;
11315 sib
.base
= codep
[1] & 7;
11320 print_insn (bfd_vma pc
, disassemble_info
*info
)
11322 const struct dis386
*dp
;
11324 char *op_txt
[MAX_OPERANDS
];
11328 struct dis_private priv
;
11330 int default_prefixes
;
11332 if (info
->mach
== bfd_mach_x86_64_intel_syntax
11333 || info
->mach
== bfd_mach_x86_64
11334 || info
->mach
== bfd_mach_l1om
11335 || info
->mach
== bfd_mach_l1om_intel_syntax
)
11336 address_mode
= mode_64bit
;
11338 address_mode
= mode_32bit
;
11340 if (intel_syntax
== (char) -1)
11341 intel_syntax
= (info
->mach
== bfd_mach_i386_i386_intel_syntax
11342 || info
->mach
== bfd_mach_x86_64_intel_syntax
11343 || info
->mach
== bfd_mach_l1om_intel_syntax
);
11345 if (info
->mach
== bfd_mach_i386_i386
11346 || info
->mach
== bfd_mach_x86_64
11347 || info
->mach
== bfd_mach_l1om
11348 || info
->mach
== bfd_mach_i386_i386_intel_syntax
11349 || info
->mach
== bfd_mach_x86_64_intel_syntax
11350 || info
->mach
== bfd_mach_l1om_intel_syntax
)
11351 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
11352 else if (info
->mach
== bfd_mach_i386_i8086
)
11353 priv
.orig_sizeflag
= 0;
11357 for (p
= info
->disassembler_options
; p
!= NULL
; )
11359 if (CONST_STRNEQ (p
, "x86-64"))
11361 address_mode
= mode_64bit
;
11362 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
11364 else if (CONST_STRNEQ (p
, "i386"))
11366 address_mode
= mode_32bit
;
11367 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
11369 else if (CONST_STRNEQ (p
, "i8086"))
11371 address_mode
= mode_16bit
;
11372 priv
.orig_sizeflag
= 0;
11374 else if (CONST_STRNEQ (p
, "intel"))
11377 if (CONST_STRNEQ (p
+ 5, "-mnemonic"))
11378 intel_mnemonic
= 1;
11380 else if (CONST_STRNEQ (p
, "att"))
11383 if (CONST_STRNEQ (p
+ 3, "-mnemonic"))
11384 intel_mnemonic
= 0;
11386 else if (CONST_STRNEQ (p
, "addr"))
11388 if (address_mode
== mode_64bit
)
11390 if (p
[4] == '3' && p
[5] == '2')
11391 priv
.orig_sizeflag
&= ~AFLAG
;
11392 else if (p
[4] == '6' && p
[5] == '4')
11393 priv
.orig_sizeflag
|= AFLAG
;
11397 if (p
[4] == '1' && p
[5] == '6')
11398 priv
.orig_sizeflag
&= ~AFLAG
;
11399 else if (p
[4] == '3' && p
[5] == '2')
11400 priv
.orig_sizeflag
|= AFLAG
;
11403 else if (CONST_STRNEQ (p
, "data"))
11405 if (p
[4] == '1' && p
[5] == '6')
11406 priv
.orig_sizeflag
&= ~DFLAG
;
11407 else if (p
[4] == '3' && p
[5] == '2')
11408 priv
.orig_sizeflag
|= DFLAG
;
11410 else if (CONST_STRNEQ (p
, "suffix"))
11411 priv
.orig_sizeflag
|= SUFFIX_ALWAYS
;
11413 p
= strchr (p
, ',');
11420 names64
= intel_names64
;
11421 names32
= intel_names32
;
11422 names16
= intel_names16
;
11423 names8
= intel_names8
;
11424 names8rex
= intel_names8rex
;
11425 names_seg
= intel_names_seg
;
11426 names_mm
= intel_names_mm
;
11427 names_xmm
= intel_names_xmm
;
11428 names_ymm
= intel_names_ymm
;
11429 index64
= intel_index64
;
11430 index32
= intel_index32
;
11431 index16
= intel_index16
;
11434 separator_char
= '+';
11439 names64
= att_names64
;
11440 names32
= att_names32
;
11441 names16
= att_names16
;
11442 names8
= att_names8
;
11443 names8rex
= att_names8rex
;
11444 names_seg
= att_names_seg
;
11445 names_mm
= att_names_mm
;
11446 names_xmm
= att_names_xmm
;
11447 names_ymm
= att_names_ymm
;
11448 index64
= att_index64
;
11449 index32
= att_index32
;
11450 index16
= att_index16
;
11453 separator_char
= ',';
11457 /* The output looks better if we put 7 bytes on a line, since that
11458 puts most long word instructions on a single line. Use 8 bytes
11460 if (info
->mach
== bfd_mach_l1om
11461 || info
->mach
== bfd_mach_l1om_intel_syntax
)
11462 info
->bytes_per_line
= 8;
11464 info
->bytes_per_line
= 7;
11466 info
->private_data
= &priv
;
11467 priv
.max_fetched
= priv
.the_buffer
;
11468 priv
.insn_start
= pc
;
11471 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
11479 start_codep
= priv
.the_buffer
;
11480 codep
= priv
.the_buffer
;
11482 if (setjmp (priv
.bailout
) != 0)
11486 /* Getting here means we tried for data but didn't get it. That
11487 means we have an incomplete instruction of some sort. Just
11488 print the first byte as a prefix or a .byte pseudo-op. */
11489 if (codep
> priv
.the_buffer
)
11491 name
= prefix_name (priv
.the_buffer
[0], priv
.orig_sizeflag
);
11493 (*info
->fprintf_func
) (info
->stream
, "%s", name
);
11496 /* Just print the first byte as a .byte instruction. */
11497 (*info
->fprintf_func
) (info
->stream
, ".byte 0x%x",
11498 (unsigned int) priv
.the_buffer
[0]);
11508 sizeflag
= priv
.orig_sizeflag
;
11510 if (!ckprefix () || rex_used
)
11512 /* Too many prefixes or unused REX prefixes. */
11514 all_prefixes
[i
] && i
< (int) ARRAY_SIZE (all_prefixes
);
11516 (*info
->fprintf_func
) (info
->stream
, "%s",
11517 prefix_name (all_prefixes
[i
], sizeflag
));
11521 insn_codep
= codep
;
11523 FETCH_DATA (info
, codep
+ 1);
11524 two_source_ops
= (*codep
== 0x62) || (*codep
== 0xc8);
11526 if (((prefixes
& PREFIX_FWAIT
)
11527 && ((*codep
< 0xd8) || (*codep
> 0xdf))))
11529 (*info
->fprintf_func
) (info
->stream
, "fwait");
11533 if (*codep
== 0x0f)
11535 unsigned char threebyte
;
11536 FETCH_DATA (info
, codep
+ 2);
11537 threebyte
= *++codep
;
11538 dp
= &dis386_twobyte
[threebyte
];
11539 need_modrm
= twobyte_has_modrm
[*codep
];
11544 dp
= &dis386
[*codep
];
11545 need_modrm
= onebyte_has_modrm
[*codep
];
11549 if ((prefixes
& PREFIX_REPZ
))
11550 used_prefixes
|= PREFIX_REPZ
;
11551 if ((prefixes
& PREFIX_REPNZ
))
11552 used_prefixes
|= PREFIX_REPNZ
;
11553 if ((prefixes
& PREFIX_LOCK
))
11554 used_prefixes
|= PREFIX_LOCK
;
11556 default_prefixes
= 0;
11557 if (prefixes
& PREFIX_ADDR
)
11560 if (dp
->op
[2].bytemode
!= loop_jcxz_mode
|| intel_syntax
)
11562 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
11563 all_prefixes
[last_addr_prefix
] = ADDR32_PREFIX
;
11565 all_prefixes
[last_addr_prefix
] = ADDR16_PREFIX
;
11566 default_prefixes
|= PREFIX_ADDR
;
11570 if ((prefixes
& PREFIX_DATA
))
11573 if (dp
->op
[2].bytemode
== cond_jump_mode
11574 && dp
->op
[0].bytemode
== v_mode
11577 if (sizeflag
& DFLAG
)
11578 all_prefixes
[last_data_prefix
] = DATA32_PREFIX
;
11580 all_prefixes
[last_data_prefix
] = DATA16_PREFIX
;
11581 default_prefixes
|= PREFIX_DATA
;
11583 else if (rex
& REX_W
)
11585 /* REX_W will override PREFIX_DATA. */
11586 default_prefixes
|= PREFIX_DATA
;
11592 FETCH_DATA (info
, codep
+ 1);
11593 modrm
.mod
= (*codep
>> 6) & 3;
11594 modrm
.reg
= (*codep
>> 3) & 7;
11595 modrm
.rm
= *codep
& 7;
11602 if (dp
->name
== NULL
&& dp
->op
[0].bytemode
== FLOATCODE
)
11605 dofloat (sizeflag
);
11609 dp
= get_valid_dis386 (dp
, info
);
11610 if (dp
!= NULL
&& putop (dp
->name
, sizeflag
) == 0)
11613 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
11616 op_ad
= MAX_OPERANDS
- 1 - i
;
11618 (*dp
->op
[i
].rtn
) (dp
->op
[i
].bytemode
, sizeflag
);
11623 /* See if any prefixes were not used. If so, print the first one
11624 separately. If we don't do this, we'll wind up printing an
11625 instruction stream which does not precisely correspond to the
11626 bytes we are disassembling. */
11627 if ((prefixes
& ~(used_prefixes
| default_prefixes
)) != 0)
11629 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
11630 if (all_prefixes
[i
])
11633 name
= prefix_name (all_prefixes
[i
], priv
.orig_sizeflag
);
11635 name
= INTERNAL_DISASSEMBLER_ERROR
;
11636 (*info
->fprintf_func
) (info
->stream
, "%s", name
);
11641 /* Check if the REX prefix is used. */
11642 if (rex_ignored
== 0 && (rex
^ rex_used
) == 0)
11643 all_prefixes
[last_rex_prefix
] = 0;
11645 /* Check if the SEG prefix is used. */
11646 if ((prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
| PREFIX_ES
11647 | PREFIX_FS
| PREFIX_GS
)) != 0
11649 & seg_prefix (all_prefixes
[last_seg_prefix
])) != 0)
11650 all_prefixes
[last_seg_prefix
] = 0;
11652 /* Check if the ADDR prefix is used. */
11653 if ((prefixes
& PREFIX_ADDR
) != 0
11654 && (used_prefixes
& PREFIX_ADDR
) != 0)
11655 all_prefixes
[last_addr_prefix
] = 0;
11657 /* Check if the DATA prefix is used. */
11658 if ((prefixes
& PREFIX_DATA
) != 0
11659 && (used_prefixes
& PREFIX_DATA
) != 0)
11660 all_prefixes
[last_data_prefix
] = 0;
11663 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
11664 if (all_prefixes
[i
])
11667 name
= prefix_name (all_prefixes
[i
], sizeflag
);
11670 prefix_length
+= strlen (name
) + 1;
11671 (*info
->fprintf_func
) (info
->stream
, "%s ", name
);
11674 /* Check maximum code length. */
11675 if ((codep
- start_codep
) > MAX_CODE_LENGTH
)
11677 (*info
->fprintf_func
) (info
->stream
, "(bad)");
11678 return MAX_CODE_LENGTH
;
11681 obufp
= mnemonicendp
;
11682 for (i
= strlen (obuf
) + prefix_length
; i
< 6; i
++)
11685 (*info
->fprintf_func
) (info
->stream
, "%s", obuf
);
11687 /* The enter and bound instructions are printed with operands in the same
11688 order as the intel book; everything else is printed in reverse order. */
11689 if (intel_syntax
|| two_source_ops
)
11693 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
11694 op_txt
[i
] = op_out
[i
];
11696 for (i
= 0; i
< (MAX_OPERANDS
>> 1); ++i
)
11698 op_ad
= op_index
[i
];
11699 op_index
[i
] = op_index
[MAX_OPERANDS
- 1 - i
];
11700 op_index
[MAX_OPERANDS
- 1 - i
] = op_ad
;
11701 riprel
= op_riprel
[i
];
11702 op_riprel
[i
] = op_riprel
[MAX_OPERANDS
- 1 - i
];
11703 op_riprel
[MAX_OPERANDS
- 1 - i
] = riprel
;
11708 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
11709 op_txt
[MAX_OPERANDS
- 1 - i
] = op_out
[i
];
11713 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
11717 (*info
->fprintf_func
) (info
->stream
, ",");
11718 if (op_index
[i
] != -1 && !op_riprel
[i
])
11719 (*info
->print_address_func
) ((bfd_vma
) op_address
[op_index
[i
]], info
);
11721 (*info
->fprintf_func
) (info
->stream
, "%s", op_txt
[i
]);
11725 for (i
= 0; i
< MAX_OPERANDS
; i
++)
11726 if (op_index
[i
] != -1 && op_riprel
[i
])
11728 (*info
->fprintf_func
) (info
->stream
, " # ");
11729 (*info
->print_address_func
) ((bfd_vma
) (start_pc
+ codep
- start_codep
11730 + op_address
[op_index
[i
]]), info
);
11733 return codep
- priv
.the_buffer
;
11736 static const char *float_mem
[] = {
11811 static const unsigned char float_mem_mode
[] = {
11886 #define ST { OP_ST, 0 }
11887 #define STi { OP_STi, 0 }
11889 #define FGRPd9_2 NULL, { { NULL, 0 } }
11890 #define FGRPd9_4 NULL, { { NULL, 1 } }
11891 #define FGRPd9_5 NULL, { { NULL, 2 } }
11892 #define FGRPd9_6 NULL, { { NULL, 3 } }
11893 #define FGRPd9_7 NULL, { { NULL, 4 } }
11894 #define FGRPda_5 NULL, { { NULL, 5 } }
11895 #define FGRPdb_4 NULL, { { NULL, 6 } }
11896 #define FGRPde_3 NULL, { { NULL, 7 } }
11897 #define FGRPdf_4 NULL, { { NULL, 8 } }
11899 static const struct dis386 float_reg
[][8] = {
11902 { "fadd", { ST
, STi
} },
11903 { "fmul", { ST
, STi
} },
11904 { "fcom", { STi
} },
11905 { "fcomp", { STi
} },
11906 { "fsub", { ST
, STi
} },
11907 { "fsubr", { ST
, STi
} },
11908 { "fdiv", { ST
, STi
} },
11909 { "fdivr", { ST
, STi
} },
11913 { "fld", { STi
} },
11914 { "fxch", { STi
} },
11924 { "fcmovb", { ST
, STi
} },
11925 { "fcmove", { ST
, STi
} },
11926 { "fcmovbe",{ ST
, STi
} },
11927 { "fcmovu", { ST
, STi
} },
11935 { "fcmovnb",{ ST
, STi
} },
11936 { "fcmovne",{ ST
, STi
} },
11937 { "fcmovnbe",{ ST
, STi
} },
11938 { "fcmovnu",{ ST
, STi
} },
11940 { "fucomi", { ST
, STi
} },
11941 { "fcomi", { ST
, STi
} },
11946 { "fadd", { STi
, ST
} },
11947 { "fmul", { STi
, ST
} },
11950 { "fsub!M", { STi
, ST
} },
11951 { "fsubM", { STi
, ST
} },
11952 { "fdiv!M", { STi
, ST
} },
11953 { "fdivM", { STi
, ST
} },
11957 { "ffree", { STi
} },
11959 { "fst", { STi
} },
11960 { "fstp", { STi
} },
11961 { "fucom", { STi
} },
11962 { "fucomp", { STi
} },
11968 { "faddp", { STi
, ST
} },
11969 { "fmulp", { STi
, ST
} },
11972 { "fsub!Mp", { STi
, ST
} },
11973 { "fsubMp", { STi
, ST
} },
11974 { "fdiv!Mp", { STi
, ST
} },
11975 { "fdivMp", { STi
, ST
} },
11979 { "ffreep", { STi
} },
11984 { "fucomip", { ST
, STi
} },
11985 { "fcomip", { ST
, STi
} },
11990 static char *fgrps
[][8] = {
11993 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11998 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
12003 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
12008 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
12013 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
12018 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12023 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
12024 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
12029 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12034 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12039 swap_operand (void)
12041 mnemonicendp
[0] = '.';
12042 mnemonicendp
[1] = 's';
12047 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED
,
12048 int sizeflag ATTRIBUTE_UNUSED
)
12050 /* Skip mod/rm byte. */
12056 dofloat (int sizeflag
)
12058 const struct dis386
*dp
;
12059 unsigned char floatop
;
12061 floatop
= codep
[-1];
12063 if (modrm
.mod
!= 3)
12065 int fp_indx
= (floatop
- 0xd8) * 8 + modrm
.reg
;
12067 putop (float_mem
[fp_indx
], sizeflag
);
12070 OP_E (float_mem_mode
[fp_indx
], sizeflag
);
12073 /* Skip mod/rm byte. */
12077 dp
= &float_reg
[floatop
- 0xd8][modrm
.reg
];
12078 if (dp
->name
== NULL
)
12080 putop (fgrps
[dp
->op
[0].bytemode
][modrm
.rm
], sizeflag
);
12082 /* Instruction fnstsw is only one with strange arg. */
12083 if (floatop
== 0xdf && codep
[-1] == 0xe0)
12084 strcpy (op_out
[0], names16
[0]);
12088 putop (dp
->name
, sizeflag
);
12093 (*dp
->op
[0].rtn
) (dp
->op
[0].bytemode
, sizeflag
);
12098 (*dp
->op
[1].rtn
) (dp
->op
[1].bytemode
, sizeflag
);
12103 OP_ST (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12105 oappend ("%st" + intel_syntax
);
12109 OP_STi (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12111 sprintf (scratchbuf
, "%%st(%d)", modrm
.rm
);
12112 oappend (scratchbuf
+ intel_syntax
);
12115 /* Capital letters in template are macros. */
12117 putop (const char *in_template
, int sizeflag
)
12122 unsigned int l
= 0, len
= 1;
12125 #define SAVE_LAST(c) \
12126 if (l < len && l < sizeof (last)) \
12131 for (p
= in_template
; *p
; p
++)
12148 while (*++p
!= '|')
12149 if (*p
== '}' || *p
== '\0')
12152 /* Fall through. */
12157 while (*++p
!= '}')
12168 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
12172 if (l
== 0 && len
== 1)
12177 if (sizeflag
& SUFFIX_ALWAYS
)
12190 if (address_mode
== mode_64bit
12191 && !(prefixes
& PREFIX_ADDR
))
12202 if (intel_syntax
&& !alt
)
12204 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
12206 if (sizeflag
& DFLAG
)
12207 *obufp
++ = intel_syntax
? 'd' : 'l';
12209 *obufp
++ = intel_syntax
? 'w' : 's';
12210 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12214 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
12217 if (modrm
.mod
== 3)
12223 if (sizeflag
& DFLAG
)
12224 *obufp
++ = intel_syntax
? 'd' : 'l';
12227 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12233 case 'E': /* For jcxz/jecxz */
12234 if (address_mode
== mode_64bit
)
12236 if (sizeflag
& AFLAG
)
12242 if (sizeflag
& AFLAG
)
12244 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
12249 if ((prefixes
& PREFIX_ADDR
) || (sizeflag
& SUFFIX_ALWAYS
))
12251 if (sizeflag
& AFLAG
)
12252 *obufp
++ = address_mode
== mode_64bit
? 'q' : 'l';
12254 *obufp
++ = address_mode
== mode_64bit
? 'l' : 'w';
12255 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
12259 if (intel_syntax
|| (obufp
[-1] != 's' && !(sizeflag
& SUFFIX_ALWAYS
)))
12261 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
12265 if (!(rex
& REX_W
))
12266 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12271 if ((prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_CS
12272 || (prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_DS
)
12274 used_prefixes
|= prefixes
& (PREFIX_CS
| PREFIX_DS
);
12277 if (prefixes
& PREFIX_DS
)
12298 if (address_mode
== mode_64bit
&& (sizeflag
& SUFFIX_ALWAYS
))
12303 /* Fall through. */
12306 if (l
!= 0 || len
!= 1)
12314 if (sizeflag
& SUFFIX_ALWAYS
)
12318 if (intel_mnemonic
!= cond
)
12322 if ((prefixes
& PREFIX_FWAIT
) == 0)
12325 used_prefixes
|= PREFIX_FWAIT
;
12331 else if (intel_syntax
&& (sizeflag
& DFLAG
))
12335 if (!(rex
& REX_W
))
12336 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12340 && address_mode
== mode_64bit
12341 && (sizeflag
& DFLAG
))
12346 /* Fall through. */
12350 if ((rex
& REX_W
) == 0
12351 && (prefixes
& PREFIX_DATA
))
12353 if ((sizeflag
& DFLAG
) == 0)
12355 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12359 if ((prefixes
& PREFIX_DATA
)
12361 || (sizeflag
& SUFFIX_ALWAYS
))
12368 if (sizeflag
& DFLAG
)
12372 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12379 if (address_mode
== mode_64bit
&& (sizeflag
& DFLAG
))
12381 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
12385 /* Fall through. */
12388 if (l
== 0 && len
== 1)
12391 if (intel_syntax
&& !alt
)
12394 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
12400 if (sizeflag
& DFLAG
)
12401 *obufp
++ = intel_syntax
? 'd' : 'l';
12404 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12410 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
12416 || (modrm
.mod
== 3 && !(sizeflag
& SUFFIX_ALWAYS
)))
12431 else if (sizeflag
& DFLAG
)
12440 if (intel_syntax
&& !p
[1]
12441 && ((rex
& REX_W
) || (sizeflag
& DFLAG
)))
12443 if (!(rex
& REX_W
))
12444 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12447 if (l
== 0 && len
== 1)
12451 if (address_mode
== mode_64bit
&& (sizeflag
& DFLAG
))
12453 if (sizeflag
& SUFFIX_ALWAYS
)
12475 /* Fall through. */
12478 if (l
== 0 && len
== 1)
12483 if (sizeflag
& SUFFIX_ALWAYS
)
12489 if (sizeflag
& DFLAG
)
12493 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12507 if (address_mode
== mode_64bit
12508 && !(prefixes
& PREFIX_ADDR
))
12519 if (l
!= 0 || len
!= 1)
12524 if (need_vex
&& vex
.prefix
)
12526 if (vex
.prefix
== DATA_PREFIX_OPCODE
)
12533 if (prefixes
& PREFIX_DATA
)
12537 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12541 if (l
== 0 && len
== 1)
12543 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
12554 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
12562 || (modrm
.mod
== 3 && !(sizeflag
& SUFFIX_ALWAYS
)))
12564 switch (vex
.length
)
12578 if (l
== 0 && len
== 1)
12580 /* operand size flag for cwtl, cbtw */
12589 else if (sizeflag
& DFLAG
)
12593 if (!(rex
& REX_W
))
12594 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12598 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
12605 *obufp
++ = vex
.w
? 'd': 's';
12612 mnemonicendp
= obufp
;
12617 oappend (const char *s
)
12619 obufp
= stpcpy (obufp
, s
);
12625 if (prefixes
& PREFIX_CS
)
12627 used_prefixes
|= PREFIX_CS
;
12628 oappend ("%cs:" + intel_syntax
);
12630 if (prefixes
& PREFIX_DS
)
12632 used_prefixes
|= PREFIX_DS
;
12633 oappend ("%ds:" + intel_syntax
);
12635 if (prefixes
& PREFIX_SS
)
12637 used_prefixes
|= PREFIX_SS
;
12638 oappend ("%ss:" + intel_syntax
);
12640 if (prefixes
& PREFIX_ES
)
12642 used_prefixes
|= PREFIX_ES
;
12643 oappend ("%es:" + intel_syntax
);
12645 if (prefixes
& PREFIX_FS
)
12647 used_prefixes
|= PREFIX_FS
;
12648 oappend ("%fs:" + intel_syntax
);
12650 if (prefixes
& PREFIX_GS
)
12652 used_prefixes
|= PREFIX_GS
;
12653 oappend ("%gs:" + intel_syntax
);
12658 OP_indirE (int bytemode
, int sizeflag
)
12662 OP_E (bytemode
, sizeflag
);
12666 print_operand_value (char *buf
, int hex
, bfd_vma disp
)
12668 if (address_mode
== mode_64bit
)
12676 sprintf_vma (tmp
, disp
);
12677 for (i
= 0; tmp
[i
] == '0' && tmp
[i
+ 1]; i
++);
12678 strcpy (buf
+ 2, tmp
+ i
);
12682 bfd_signed_vma v
= disp
;
12689 /* Check for possible overflow on 0x8000000000000000. */
12692 strcpy (buf
, "9223372036854775808");
12706 tmp
[28 - i
] = (v
% 10) + '0';
12710 strcpy (buf
, tmp
+ 29 - i
);
12716 sprintf (buf
, "0x%x", (unsigned int) disp
);
12718 sprintf (buf
, "%d", (int) disp
);
12722 /* Put DISP in BUF as signed hex number. */
12725 print_displacement (char *buf
, bfd_vma disp
)
12727 bfd_signed_vma val
= disp
;
12736 /* Check for possible overflow. */
12739 switch (address_mode
)
12742 strcpy (buf
+ j
, "0x8000000000000000");
12745 strcpy (buf
+ j
, "0x80000000");
12748 strcpy (buf
+ j
, "0x8000");
12758 sprintf_vma (tmp
, (bfd_vma
) val
);
12759 for (i
= 0; tmp
[i
] == '0'; i
++)
12761 if (tmp
[i
] == '\0')
12763 strcpy (buf
+ j
, tmp
+ i
);
12767 intel_operand_size (int bytemode
, int sizeflag
)
12774 oappend ("BYTE PTR ");
12778 oappend ("WORD PTR ");
12781 if (address_mode
== mode_64bit
&& (sizeflag
& DFLAG
))
12783 oappend ("QWORD PTR ");
12792 oappend ("QWORD PTR ");
12795 if ((sizeflag
& DFLAG
) || bytemode
== dq_mode
)
12796 oappend ("DWORD PTR ");
12798 oappend ("WORD PTR ");
12799 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12803 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
12805 oappend ("WORD PTR ");
12806 if (!(rex
& REX_W
))
12807 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12810 if (sizeflag
& DFLAG
)
12811 oappend ("QWORD PTR ");
12813 oappend ("DWORD PTR ");
12814 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12817 case d_scalar_mode
:
12818 case d_scalar_swap_mode
:
12821 oappend ("DWORD PTR ");
12824 case q_scalar_mode
:
12825 case q_scalar_swap_mode
:
12827 oappend ("QWORD PTR ");
12830 if (address_mode
== mode_64bit
)
12831 oappend ("QWORD PTR ");
12833 oappend ("DWORD PTR ");
12836 if (sizeflag
& DFLAG
)
12837 oappend ("FWORD PTR ");
12839 oappend ("DWORD PTR ");
12840 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12843 oappend ("TBYTE PTR ");
12849 switch (vex
.length
)
12852 oappend ("XMMWORD PTR ");
12855 oappend ("YMMWORD PTR ");
12862 oappend ("XMMWORD PTR ");
12865 oappend ("XMMWORD PTR ");
12871 switch (vex
.length
)
12874 oappend ("QWORD PTR ");
12877 oappend ("XMMWORD PTR ");
12887 switch (vex
.length
)
12890 oappend ("QWORD PTR ");
12893 oappend ("YMMWORD PTR ");
12900 oappend ("OWORD PTR ");
12902 case vex_w_dq_mode
:
12903 case vex_scalar_w_dq_mode
:
12908 oappend ("QWORD PTR ");
12910 oappend ("DWORD PTR ");
12918 OP_E_register (int bytemode
, int sizeflag
)
12920 int reg
= modrm
.rm
;
12921 const char **names
;
12927 if ((sizeflag
& SUFFIX_ALWAYS
)
12928 && (bytemode
== b_swap_mode
|| bytemode
== v_swap_mode
))
12951 names
= address_mode
== mode_64bit
? names64
: names32
;
12954 if (address_mode
== mode_64bit
&& (sizeflag
& DFLAG
))
12972 if ((sizeflag
& DFLAG
)
12973 || (bytemode
!= v_mode
12974 && bytemode
!= v_swap_mode
))
12978 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12984 oappend (INTERNAL_DISASSEMBLER_ERROR
);
12987 oappend (names
[reg
]);
12991 OP_E_memory (int bytemode
, int sizeflag
)
12994 int add
= (rex
& REX_B
) ? 8 : 0;
12999 intel_operand_size (bytemode
, sizeflag
);
13002 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
13004 /* 32/64 bit address mode */
13022 vindex
= sib
.index
;
13028 haveindex
= vindex
!= 4;
13031 rbase
= base
+ add
;
13039 if (address_mode
== mode_64bit
&& !havesib
)
13045 FETCH_DATA (the_info
, codep
+ 1);
13047 if ((disp
& 0x80) != 0)
13055 /* In 32bit mode, we need index register to tell [offset] from
13056 [eiz*1 + offset]. */
13057 needindex
= (havesib
13060 && address_mode
== mode_32bit
);
13061 havedisp
= (havebase
13063 || (havesib
&& (haveindex
|| scale
!= 0)));
13066 if (modrm
.mod
!= 0 || base
== 5)
13068 if (havedisp
|| riprel
)
13069 print_displacement (scratchbuf
, disp
);
13071 print_operand_value (scratchbuf
, 1, disp
);
13072 oappend (scratchbuf
);
13076 oappend (sizeflag
& AFLAG
? "(%rip)" : "(%eip)");
13080 if (havebase
|| haveindex
|| riprel
)
13081 used_prefixes
|= PREFIX_ADDR
;
13083 if (havedisp
|| (intel_syntax
&& riprel
))
13085 *obufp
++ = open_char
;
13086 if (intel_syntax
&& riprel
)
13089 oappend (sizeflag
& AFLAG
? "rip" : "eip");
13093 oappend (address_mode
== mode_64bit
&& (sizeflag
& AFLAG
)
13094 ? names64
[rbase
] : names32
[rbase
]);
13097 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
13098 print index to tell base + index from base. */
13102 || (havebase
&& base
!= ESP_REG_NUM
))
13104 if (!intel_syntax
|| havebase
)
13106 *obufp
++ = separator_char
;
13110 oappend (address_mode
== mode_64bit
13111 && (sizeflag
& AFLAG
)
13112 ? names64
[vindex
] : names32
[vindex
]);
13114 oappend (address_mode
== mode_64bit
13115 && (sizeflag
& AFLAG
)
13116 ? index64
: index32
);
13118 *obufp
++ = scale_char
;
13120 sprintf (scratchbuf
, "%d", 1 << scale
);
13121 oappend (scratchbuf
);
13125 && (disp
|| modrm
.mod
!= 0 || base
== 5))
13127 if (!havedisp
|| (bfd_signed_vma
) disp
>= 0)
13132 else if (modrm
.mod
!= 1 && disp
!= -disp
)
13136 disp
= - (bfd_signed_vma
) disp
;
13140 print_displacement (scratchbuf
, disp
);
13142 print_operand_value (scratchbuf
, 1, disp
);
13143 oappend (scratchbuf
);
13146 *obufp
++ = close_char
;
13149 else if (intel_syntax
)
13151 if (modrm
.mod
!= 0 || base
== 5)
13153 if (prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
13154 | PREFIX_ES
| PREFIX_FS
| PREFIX_GS
))
13158 oappend (names_seg
[ds_reg
- es_reg
]);
13161 print_operand_value (scratchbuf
, 1, disp
);
13162 oappend (scratchbuf
);
13168 /* 16 bit address mode */
13169 used_prefixes
|= prefixes
& PREFIX_ADDR
;
13176 if ((disp
& 0x8000) != 0)
13181 FETCH_DATA (the_info
, codep
+ 1);
13183 if ((disp
& 0x80) != 0)
13188 if ((disp
& 0x8000) != 0)
13194 if (modrm
.mod
!= 0 || modrm
.rm
== 6)
13196 print_displacement (scratchbuf
, disp
);
13197 oappend (scratchbuf
);
13200 if (modrm
.mod
!= 0 || modrm
.rm
!= 6)
13202 *obufp
++ = open_char
;
13204 oappend (index16
[modrm
.rm
]);
13206 && (disp
|| modrm
.mod
!= 0 || modrm
.rm
== 6))
13208 if ((bfd_signed_vma
) disp
>= 0)
13213 else if (modrm
.mod
!= 1)
13217 disp
= - (bfd_signed_vma
) disp
;
13220 print_displacement (scratchbuf
, disp
);
13221 oappend (scratchbuf
);
13224 *obufp
++ = close_char
;
13227 else if (intel_syntax
)
13229 if (prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
13230 | PREFIX_ES
| PREFIX_FS
| PREFIX_GS
))
13234 oappend (names_seg
[ds_reg
- es_reg
]);
13237 print_operand_value (scratchbuf
, 1, disp
& 0xffff);
13238 oappend (scratchbuf
);
13244 OP_E (int bytemode
, int sizeflag
)
13246 /* Skip mod/rm byte. */
13250 if (modrm
.mod
== 3)
13251 OP_E_register (bytemode
, sizeflag
);
13253 OP_E_memory (bytemode
, sizeflag
);
13257 OP_G (int bytemode
, int sizeflag
)
13268 oappend (names8rex
[modrm
.reg
+ add
]);
13270 oappend (names8
[modrm
.reg
+ add
]);
13273 oappend (names16
[modrm
.reg
+ add
]);
13276 oappend (names32
[modrm
.reg
+ add
]);
13279 oappend (names64
[modrm
.reg
+ add
]);
13288 oappend (names64
[modrm
.reg
+ add
]);
13291 if ((sizeflag
& DFLAG
) || bytemode
!= v_mode
)
13292 oappend (names32
[modrm
.reg
+ add
]);
13294 oappend (names16
[modrm
.reg
+ add
]);
13295 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13299 if (address_mode
== mode_64bit
)
13300 oappend (names64
[modrm
.reg
+ add
]);
13302 oappend (names32
[modrm
.reg
+ add
]);
13305 oappend (INTERNAL_DISASSEMBLER_ERROR
);
13318 FETCH_DATA (the_info
, codep
+ 8);
13319 a
= *codep
++ & 0xff;
13320 a
|= (*codep
++ & 0xff) << 8;
13321 a
|= (*codep
++ & 0xff) << 16;
13322 a
|= (*codep
++ & 0xff) << 24;
13323 b
= *codep
++ & 0xff;
13324 b
|= (*codep
++ & 0xff) << 8;
13325 b
|= (*codep
++ & 0xff) << 16;
13326 b
|= (*codep
++ & 0xff) << 24;
13327 x
= a
+ ((bfd_vma
) b
<< 32);
13335 static bfd_signed_vma
13338 bfd_signed_vma x
= 0;
13340 FETCH_DATA (the_info
, codep
+ 4);
13341 x
= *codep
++ & (bfd_signed_vma
) 0xff;
13342 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
13343 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
13344 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
13348 static bfd_signed_vma
13351 bfd_signed_vma x
= 0;
13353 FETCH_DATA (the_info
, codep
+ 4);
13354 x
= *codep
++ & (bfd_signed_vma
) 0xff;
13355 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
13356 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
13357 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
13359 x
= (x
^ ((bfd_signed_vma
) 1 << 31)) - ((bfd_signed_vma
) 1 << 31);
13369 FETCH_DATA (the_info
, codep
+ 2);
13370 x
= *codep
++ & 0xff;
13371 x
|= (*codep
++ & 0xff) << 8;
13376 set_op (bfd_vma op
, int riprel
)
13378 op_index
[op_ad
] = op_ad
;
13379 if (address_mode
== mode_64bit
)
13381 op_address
[op_ad
] = op
;
13382 op_riprel
[op_ad
] = riprel
;
13386 /* Mask to get a 32-bit address. */
13387 op_address
[op_ad
] = op
& 0xffffffff;
13388 op_riprel
[op_ad
] = riprel
& 0xffffffff;
13393 OP_REG (int code
, int sizeflag
)
13405 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
13406 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
13407 s
= names16
[code
- ax_reg
+ add
];
13409 case es_reg
: case ss_reg
: case cs_reg
:
13410 case ds_reg
: case fs_reg
: case gs_reg
:
13411 s
= names_seg
[code
- es_reg
+ add
];
13413 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
13414 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
13417 s
= names8rex
[code
- al_reg
+ add
];
13419 s
= names8
[code
- al_reg
];
13421 case rAX_reg
: case rCX_reg
: case rDX_reg
: case rBX_reg
:
13422 case rSP_reg
: case rBP_reg
: case rSI_reg
: case rDI_reg
:
13423 if (address_mode
== mode_64bit
&& (sizeflag
& DFLAG
))
13425 s
= names64
[code
- rAX_reg
+ add
];
13428 code
+= eAX_reg
- rAX_reg
;
13429 /* Fall through. */
13430 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
13431 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
13434 s
= names64
[code
- eAX_reg
+ add
];
13437 if (sizeflag
& DFLAG
)
13438 s
= names32
[code
- eAX_reg
+ add
];
13440 s
= names16
[code
- eAX_reg
+ add
];
13441 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13445 s
= INTERNAL_DISASSEMBLER_ERROR
;
13452 OP_IMREG (int code
, int sizeflag
)
13464 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
13465 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
13466 s
= names16
[code
- ax_reg
];
13468 case es_reg
: case ss_reg
: case cs_reg
:
13469 case ds_reg
: case fs_reg
: case gs_reg
:
13470 s
= names_seg
[code
- es_reg
];
13472 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
13473 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
13476 s
= names8rex
[code
- al_reg
];
13478 s
= names8
[code
- al_reg
];
13480 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
13481 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
13484 s
= names64
[code
- eAX_reg
];
13487 if (sizeflag
& DFLAG
)
13488 s
= names32
[code
- eAX_reg
];
13490 s
= names16
[code
- eAX_reg
];
13491 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13494 case z_mode_ax_reg
:
13495 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
13499 if (!(rex
& REX_W
))
13500 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13503 s
= INTERNAL_DISASSEMBLER_ERROR
;
13510 OP_I (int bytemode
, int sizeflag
)
13513 bfd_signed_vma mask
= -1;
13518 FETCH_DATA (the_info
, codep
+ 1);
13523 if (address_mode
== mode_64bit
)
13528 /* Fall through. */
13535 if (sizeflag
& DFLAG
)
13545 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13557 oappend (INTERNAL_DISASSEMBLER_ERROR
);
13562 scratchbuf
[0] = '$';
13563 print_operand_value (scratchbuf
+ 1, 1, op
);
13564 oappend (scratchbuf
+ intel_syntax
);
13565 scratchbuf
[0] = '\0';
13569 OP_I64 (int bytemode
, int sizeflag
)
13572 bfd_signed_vma mask
= -1;
13574 if (address_mode
!= mode_64bit
)
13576 OP_I (bytemode
, sizeflag
);
13583 FETCH_DATA (the_info
, codep
+ 1);
13593 if (sizeflag
& DFLAG
)
13603 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13611 oappend (INTERNAL_DISASSEMBLER_ERROR
);
13616 scratchbuf
[0] = '$';
13617 print_operand_value (scratchbuf
+ 1, 1, op
);
13618 oappend (scratchbuf
+ intel_syntax
);
13619 scratchbuf
[0] = '\0';
13623 OP_sI (int bytemode
, int sizeflag
)
13630 FETCH_DATA (the_info
, codep
+ 1);
13632 if ((op
& 0x80) != 0)
13636 if (sizeflag
& DFLAG
)
13642 oappend (INTERNAL_DISASSEMBLER_ERROR
);
13646 scratchbuf
[0] = '$';
13647 print_operand_value (scratchbuf
+ 1, 1, op
);
13648 oappend (scratchbuf
+ intel_syntax
);
13652 OP_J (int bytemode
, int sizeflag
)
13656 bfd_vma segment
= 0;
13661 FETCH_DATA (the_info
, codep
+ 1);
13663 if ((disp
& 0x80) != 0)
13668 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
13673 if ((disp
& 0x8000) != 0)
13675 /* In 16bit mode, address is wrapped around at 64k within
13676 the same segment. Otherwise, a data16 prefix on a jump
13677 instruction means that the pc is masked to 16 bits after
13678 the displacement is added! */
13680 if ((prefixes
& PREFIX_DATA
) == 0)
13681 segment
= ((start_pc
+ codep
- start_codep
)
13682 & ~((bfd_vma
) 0xffff));
13684 if (!(rex
& REX_W
))
13685 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13688 oappend (INTERNAL_DISASSEMBLER_ERROR
);
13691 disp
= ((start_pc
+ codep
- start_codep
+ disp
) & mask
) | segment
;
13693 print_operand_value (scratchbuf
, 1, disp
);
13694 oappend (scratchbuf
);
13698 OP_SEG (int bytemode
, int sizeflag
)
13700 if (bytemode
== w_mode
)
13701 oappend (names_seg
[modrm
.reg
]);
13703 OP_E (modrm
.mod
== 3 ? bytemode
: w_mode
, sizeflag
);
13707 OP_DIR (int dummy ATTRIBUTE_UNUSED
, int sizeflag
)
13711 if (sizeflag
& DFLAG
)
13721 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13723 sprintf (scratchbuf
, "0x%x:0x%x", seg
, offset
);
13725 sprintf (scratchbuf
, "$0x%x,$0x%x", seg
, offset
);
13726 oappend (scratchbuf
);
13730 OP_OFF (int bytemode
, int sizeflag
)
13734 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
13735 intel_operand_size (bytemode
, sizeflag
);
13738 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
13745 if (!(prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
13746 | PREFIX_ES
| PREFIX_FS
| PREFIX_GS
)))
13748 oappend (names_seg
[ds_reg
- es_reg
]);
13752 print_operand_value (scratchbuf
, 1, off
);
13753 oappend (scratchbuf
);
13757 OP_OFF64 (int bytemode
, int sizeflag
)
13761 if (address_mode
!= mode_64bit
13762 || (prefixes
& PREFIX_ADDR
))
13764 OP_OFF (bytemode
, sizeflag
);
13768 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
13769 intel_operand_size (bytemode
, sizeflag
);
13776 if (!(prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
13777 | PREFIX_ES
| PREFIX_FS
| PREFIX_GS
)))
13779 oappend (names_seg
[ds_reg
- es_reg
]);
13783 print_operand_value (scratchbuf
, 1, off
);
13784 oappend (scratchbuf
);
13788 ptr_reg (int code
, int sizeflag
)
13792 *obufp
++ = open_char
;
13793 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
13794 if (address_mode
== mode_64bit
)
13796 if (!(sizeflag
& AFLAG
))
13797 s
= names32
[code
- eAX_reg
];
13799 s
= names64
[code
- eAX_reg
];
13801 else if (sizeflag
& AFLAG
)
13802 s
= names32
[code
- eAX_reg
];
13804 s
= names16
[code
- eAX_reg
];
13806 *obufp
++ = close_char
;
13811 OP_ESreg (int code
, int sizeflag
)
13817 case 0x6d: /* insw/insl */
13818 intel_operand_size (z_mode
, sizeflag
);
13820 case 0xa5: /* movsw/movsl/movsq */
13821 case 0xa7: /* cmpsw/cmpsl/cmpsq */
13822 case 0xab: /* stosw/stosl */
13823 case 0xaf: /* scasw/scasl */
13824 intel_operand_size (v_mode
, sizeflag
);
13827 intel_operand_size (b_mode
, sizeflag
);
13830 oappend ("%es:" + intel_syntax
);
13831 ptr_reg (code
, sizeflag
);
13835 OP_DSreg (int code
, int sizeflag
)
13841 case 0x6f: /* outsw/outsl */
13842 intel_operand_size (z_mode
, sizeflag
);
13844 case 0xa5: /* movsw/movsl/movsq */
13845 case 0xa7: /* cmpsw/cmpsl/cmpsq */
13846 case 0xad: /* lodsw/lodsl/lodsq */
13847 intel_operand_size (v_mode
, sizeflag
);
13850 intel_operand_size (b_mode
, sizeflag
);
13859 | PREFIX_GS
)) == 0)
13860 prefixes
|= PREFIX_DS
;
13862 ptr_reg (code
, sizeflag
);
13866 OP_C (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13874 else if (address_mode
!= mode_64bit
&& (prefixes
& PREFIX_LOCK
))
13876 all_prefixes
[last_lock_prefix
] = 0;
13877 used_prefixes
|= PREFIX_LOCK
;
13882 sprintf (scratchbuf
, "%%cr%d", modrm
.reg
+ add
);
13883 oappend (scratchbuf
+ intel_syntax
);
13887 OP_D (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13896 sprintf (scratchbuf
, "db%d", modrm
.reg
+ add
);
13898 sprintf (scratchbuf
, "%%db%d", modrm
.reg
+ add
);
13899 oappend (scratchbuf
);
13903 OP_T (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13905 sprintf (scratchbuf
, "%%tr%d", modrm
.reg
);
13906 oappend (scratchbuf
+ intel_syntax
);
13910 OP_R (int bytemode
, int sizeflag
)
13912 if (modrm
.mod
== 3)
13913 OP_E (bytemode
, sizeflag
);
13919 OP_MMX (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13921 int reg
= modrm
.reg
;
13922 const char **names
;
13924 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13925 if (prefixes
& PREFIX_DATA
)
13934 oappend (names
[reg
]);
13938 OP_XMM (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
13940 int reg
= modrm
.reg
;
13941 const char **names
;
13947 && bytemode
!= xmm_mode
13948 && bytemode
!= scalar_mode
)
13950 switch (vex
.length
)
13964 oappend (names
[reg
]);
13968 OP_EM (int bytemode
, int sizeflag
)
13971 const char **names
;
13973 if (modrm
.mod
!= 3)
13976 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
13978 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
13979 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13981 OP_E (bytemode
, sizeflag
);
13985 if ((sizeflag
& SUFFIX_ALWAYS
) && bytemode
== v_swap_mode
)
13988 /* Skip mod/rm byte. */
13991 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13993 if (prefixes
& PREFIX_DATA
)
14002 oappend (names
[reg
]);
14005 /* cvt* are the only instructions in sse2 which have
14006 both SSE and MMX operands and also have 0x66 prefix
14007 in their opcode. 0x66 was originally used to differentiate
14008 between SSE and MMX instruction(operands). So we have to handle the
14009 cvt* separately using OP_EMC and OP_MXC */
14011 OP_EMC (int bytemode
, int sizeflag
)
14013 if (modrm
.mod
!= 3)
14015 if (intel_syntax
&& bytemode
== v_mode
)
14017 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
14018 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14020 OP_E (bytemode
, sizeflag
);
14024 /* Skip mod/rm byte. */
14027 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14028 oappend (names_mm
[modrm
.rm
]);
14032 OP_MXC (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
14034 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14035 oappend (names_mm
[modrm
.reg
]);
14039 OP_EX (int bytemode
, int sizeflag
)
14042 const char **names
;
14044 /* Skip mod/rm byte. */
14048 if (modrm
.mod
!= 3)
14050 OP_E_memory (bytemode
, sizeflag
);
14059 if ((sizeflag
& SUFFIX_ALWAYS
)
14060 && (bytemode
== x_swap_mode
14061 || bytemode
== d_swap_mode
14062 || bytemode
== d_scalar_swap_mode
14063 || bytemode
== q_swap_mode
14064 || bytemode
== q_scalar_swap_mode
))
14068 && bytemode
!= xmm_mode
14069 && bytemode
!= xmmq_mode
14070 && bytemode
!= d_scalar_mode
14071 && bytemode
!= d_scalar_swap_mode
14072 && bytemode
!= q_scalar_mode
14073 && bytemode
!= q_scalar_swap_mode
14074 && bytemode
!= vex_scalar_w_dq_mode
)
14076 switch (vex
.length
)
14090 oappend (names
[reg
]);
14094 OP_MS (int bytemode
, int sizeflag
)
14096 if (modrm
.mod
== 3)
14097 OP_EM (bytemode
, sizeflag
);
14103 OP_XS (int bytemode
, int sizeflag
)
14105 if (modrm
.mod
== 3)
14106 OP_EX (bytemode
, sizeflag
);
14112 OP_M (int bytemode
, int sizeflag
)
14114 if (modrm
.mod
== 3)
14115 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
14118 OP_E (bytemode
, sizeflag
);
14122 OP_0f07 (int bytemode
, int sizeflag
)
14124 if (modrm
.mod
!= 3 || modrm
.rm
!= 0)
14127 OP_E (bytemode
, sizeflag
);
14130 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
14131 32bit mode and "xchg %rax,%rax" in 64bit mode. */
14134 NOP_Fixup1 (int bytemode
, int sizeflag
)
14136 if ((prefixes
& PREFIX_DATA
) != 0
14139 && address_mode
== mode_64bit
))
14140 OP_REG (bytemode
, sizeflag
);
14142 strcpy (obuf
, "nop");
14146 NOP_Fixup2 (int bytemode
, int sizeflag
)
14148 if ((prefixes
& PREFIX_DATA
) != 0
14151 && address_mode
== mode_64bit
))
14152 OP_IMREG (bytemode
, sizeflag
);
14155 static const char *const Suffix3DNow
[] = {
14156 /* 00 */ NULL
, NULL
, NULL
, NULL
,
14157 /* 04 */ NULL
, NULL
, NULL
, NULL
,
14158 /* 08 */ NULL
, NULL
, NULL
, NULL
,
14159 /* 0C */ "pi2fw", "pi2fd", NULL
, NULL
,
14160 /* 10 */ NULL
, NULL
, NULL
, NULL
,
14161 /* 14 */ NULL
, NULL
, NULL
, NULL
,
14162 /* 18 */ NULL
, NULL
, NULL
, NULL
,
14163 /* 1C */ "pf2iw", "pf2id", NULL
, NULL
,
14164 /* 20 */ NULL
, NULL
, NULL
, NULL
,
14165 /* 24 */ NULL
, NULL
, NULL
, NULL
,
14166 /* 28 */ NULL
, NULL
, NULL
, NULL
,
14167 /* 2C */ NULL
, NULL
, NULL
, NULL
,
14168 /* 30 */ NULL
, NULL
, NULL
, NULL
,
14169 /* 34 */ NULL
, NULL
, NULL
, NULL
,
14170 /* 38 */ NULL
, NULL
, NULL
, NULL
,
14171 /* 3C */ NULL
, NULL
, NULL
, NULL
,
14172 /* 40 */ NULL
, NULL
, NULL
, NULL
,
14173 /* 44 */ NULL
, NULL
, NULL
, NULL
,
14174 /* 48 */ NULL
, NULL
, NULL
, NULL
,
14175 /* 4C */ NULL
, NULL
, NULL
, NULL
,
14176 /* 50 */ NULL
, NULL
, NULL
, NULL
,
14177 /* 54 */ NULL
, NULL
, NULL
, NULL
,
14178 /* 58 */ NULL
, NULL
, NULL
, NULL
,
14179 /* 5C */ NULL
, NULL
, NULL
, NULL
,
14180 /* 60 */ NULL
, NULL
, NULL
, NULL
,
14181 /* 64 */ NULL
, NULL
, NULL
, NULL
,
14182 /* 68 */ NULL
, NULL
, NULL
, NULL
,
14183 /* 6C */ NULL
, NULL
, NULL
, NULL
,
14184 /* 70 */ NULL
, NULL
, NULL
, NULL
,
14185 /* 74 */ NULL
, NULL
, NULL
, NULL
,
14186 /* 78 */ NULL
, NULL
, NULL
, NULL
,
14187 /* 7C */ NULL
, NULL
, NULL
, NULL
,
14188 /* 80 */ NULL
, NULL
, NULL
, NULL
,
14189 /* 84 */ NULL
, NULL
, NULL
, NULL
,
14190 /* 88 */ NULL
, NULL
, "pfnacc", NULL
,
14191 /* 8C */ NULL
, NULL
, "pfpnacc", NULL
,
14192 /* 90 */ "pfcmpge", NULL
, NULL
, NULL
,
14193 /* 94 */ "pfmin", NULL
, "pfrcp", "pfrsqrt",
14194 /* 98 */ NULL
, NULL
, "pfsub", NULL
,
14195 /* 9C */ NULL
, NULL
, "pfadd", NULL
,
14196 /* A0 */ "pfcmpgt", NULL
, NULL
, NULL
,
14197 /* A4 */ "pfmax", NULL
, "pfrcpit1", "pfrsqit1",
14198 /* A8 */ NULL
, NULL
, "pfsubr", NULL
,
14199 /* AC */ NULL
, NULL
, "pfacc", NULL
,
14200 /* B0 */ "pfcmpeq", NULL
, NULL
, NULL
,
14201 /* B4 */ "pfmul", NULL
, "pfrcpit2", "pmulhrw",
14202 /* B8 */ NULL
, NULL
, NULL
, "pswapd",
14203 /* BC */ NULL
, NULL
, NULL
, "pavgusb",
14204 /* C0 */ NULL
, NULL
, NULL
, NULL
,
14205 /* C4 */ NULL
, NULL
, NULL
, NULL
,
14206 /* C8 */ NULL
, NULL
, NULL
, NULL
,
14207 /* CC */ NULL
, NULL
, NULL
, NULL
,
14208 /* D0 */ NULL
, NULL
, NULL
, NULL
,
14209 /* D4 */ NULL
, NULL
, NULL
, NULL
,
14210 /* D8 */ NULL
, NULL
, NULL
, NULL
,
14211 /* DC */ NULL
, NULL
, NULL
, NULL
,
14212 /* E0 */ NULL
, NULL
, NULL
, NULL
,
14213 /* E4 */ NULL
, NULL
, NULL
, NULL
,
14214 /* E8 */ NULL
, NULL
, NULL
, NULL
,
14215 /* EC */ NULL
, NULL
, NULL
, NULL
,
14216 /* F0 */ NULL
, NULL
, NULL
, NULL
,
14217 /* F4 */ NULL
, NULL
, NULL
, NULL
,
14218 /* F8 */ NULL
, NULL
, NULL
, NULL
,
14219 /* FC */ NULL
, NULL
, NULL
, NULL
,
14223 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
14225 const char *mnemonic
;
14227 FETCH_DATA (the_info
, codep
+ 1);
14228 /* AMD 3DNow! instructions are specified by an opcode suffix in the
14229 place where an 8-bit immediate would normally go. ie. the last
14230 byte of the instruction. */
14231 obufp
= mnemonicendp
;
14232 mnemonic
= Suffix3DNow
[*codep
++ & 0xff];
14234 oappend (mnemonic
);
14237 /* Since a variable sized modrm/sib chunk is between the start
14238 of the opcode (0x0f0f) and the opcode suffix, we need to do
14239 all the modrm processing first, and don't know until now that
14240 we have a bad opcode. This necessitates some cleaning up. */
14241 op_out
[0][0] = '\0';
14242 op_out
[1][0] = '\0';
14245 mnemonicendp
= obufp
;
14248 static struct op simd_cmp_op
[] =
14250 { STRING_COMMA_LEN ("eq") },
14251 { STRING_COMMA_LEN ("lt") },
14252 { STRING_COMMA_LEN ("le") },
14253 { STRING_COMMA_LEN ("unord") },
14254 { STRING_COMMA_LEN ("neq") },
14255 { STRING_COMMA_LEN ("nlt") },
14256 { STRING_COMMA_LEN ("nle") },
14257 { STRING_COMMA_LEN ("ord") }
14261 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
14263 unsigned int cmp_type
;
14265 FETCH_DATA (the_info
, codep
+ 1);
14266 cmp_type
= *codep
++ & 0xff;
14267 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
))
14270 char *p
= mnemonicendp
- 2;
14274 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
14275 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
14279 /* We have a reserved extension byte. Output it directly. */
14280 scratchbuf
[0] = '$';
14281 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
14282 oappend (scratchbuf
+ intel_syntax
);
14283 scratchbuf
[0] = '\0';
14288 OP_Mwait (int bytemode ATTRIBUTE_UNUSED
,
14289 int sizeflag ATTRIBUTE_UNUSED
)
14291 /* mwait %eax,%ecx */
14294 const char **names
= (address_mode
== mode_64bit
14295 ? names64
: names32
);
14296 strcpy (op_out
[0], names
[0]);
14297 strcpy (op_out
[1], names
[1]);
14298 two_source_ops
= 1;
14300 /* Skip mod/rm byte. */
14306 OP_Monitor (int bytemode ATTRIBUTE_UNUSED
,
14307 int sizeflag ATTRIBUTE_UNUSED
)
14309 /* monitor %eax,%ecx,%edx" */
14312 const char **op1_names
;
14313 const char **names
= (address_mode
== mode_64bit
14314 ? names64
: names32
);
14316 if (!(prefixes
& PREFIX_ADDR
))
14317 op1_names
= (address_mode
== mode_16bit
14318 ? names16
: names
);
14321 /* Remove "addr16/addr32". */
14322 all_prefixes
[last_addr_prefix
] = 0;
14323 op1_names
= (address_mode
!= mode_32bit
14324 ? names32
: names16
);
14325 used_prefixes
|= PREFIX_ADDR
;
14327 strcpy (op_out
[0], op1_names
[0]);
14328 strcpy (op_out
[1], names
[1]);
14329 strcpy (op_out
[2], names
[2]);
14330 two_source_ops
= 1;
14332 /* Skip mod/rm byte. */
14340 /* Throw away prefixes and 1st. opcode byte. */
14341 codep
= insn_codep
+ 1;
14346 REP_Fixup (int bytemode
, int sizeflag
)
14348 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
14350 if (prefixes
& PREFIX_REPZ
)
14351 all_prefixes
[last_repz_prefix
] = REP_PREFIX
;
14358 OP_IMREG (bytemode
, sizeflag
);
14361 OP_ESreg (bytemode
, sizeflag
);
14364 OP_DSreg (bytemode
, sizeflag
);
14373 CMPXCHG8B_Fixup (int bytemode
, int sizeflag
)
14378 /* Change cmpxchg8b to cmpxchg16b. */
14379 char *p
= mnemonicendp
- 2;
14380 mnemonicendp
= stpcpy (p
, "16b");
14383 OP_M (bytemode
, sizeflag
);
14387 XMM_Fixup (int reg
, int sizeflag ATTRIBUTE_UNUSED
)
14389 const char **names
;
14393 switch (vex
.length
)
14407 oappend (names
[reg
]);
14411 CRC32_Fixup (int bytemode
, int sizeflag
)
14413 /* Add proper suffix to "crc32". */
14414 char *p
= mnemonicendp
;
14433 if (sizeflag
& DFLAG
)
14437 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14441 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14448 if (modrm
.mod
== 3)
14452 /* Skip mod/rm byte. */
14457 add
= (rex
& REX_B
) ? 8 : 0;
14458 if (bytemode
== b_mode
)
14462 oappend (names8rex
[modrm
.rm
+ add
]);
14464 oappend (names8
[modrm
.rm
+ add
]);
14470 oappend (names64
[modrm
.rm
+ add
]);
14471 else if ((prefixes
& PREFIX_DATA
))
14472 oappend (names16
[modrm
.rm
+ add
]);
14474 oappend (names32
[modrm
.rm
+ add
]);
14478 OP_E (bytemode
, sizeflag
);
14482 FXSAVE_Fixup (int bytemode
, int sizeflag
)
14484 /* Add proper suffix to "fxsave" and "fxrstor". */
14488 char *p
= mnemonicendp
;
14494 OP_M (bytemode
, sizeflag
);
14497 /* Display the destination register operand for instructions with
14501 OP_VEX (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
14504 const char **names
;
14512 reg
= vex
.register_specifier
;
14513 if (bytemode
== vex_scalar_mode
)
14515 oappend (names_xmm
[reg
]);
14519 switch (vex
.length
)
14551 oappend (names
[reg
]);
14554 /* Get the VEX immediate byte without moving codep. */
14556 static unsigned char
14557 get_vex_imm8 (int sizeflag
, int opnum
)
14559 int bytes_before_imm
= 0;
14561 if (modrm
.mod
!= 3)
14563 /* There are SIB/displacement bytes. */
14564 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
14566 /* 32/64 bit address mode */
14567 int base
= modrm
.rm
;
14569 /* Check SIB byte. */
14572 FETCH_DATA (the_info
, codep
+ 1);
14574 /* When decoding the third source, don't increase
14575 bytes_before_imm as this has already been incremented
14576 by one in OP_E_memory while decoding the second
14579 bytes_before_imm
++;
14582 /* Don't increase bytes_before_imm when decoding the third source,
14583 it has already been incremented by OP_E_memory while decoding
14584 the second source operand. */
14590 /* When modrm.rm == 5 or modrm.rm == 4 and base in
14591 SIB == 5, there is a 4 byte displacement. */
14593 /* No displacement. */
14596 /* 4 byte displacement. */
14597 bytes_before_imm
+= 4;
14600 /* 1 byte displacement. */
14601 bytes_before_imm
++;
14608 /* 16 bit address mode */
14609 /* Don't increase bytes_before_imm when decoding the third source,
14610 it has already been incremented by OP_E_memory while decoding
14611 the second source operand. */
14617 /* When modrm.rm == 6, there is a 2 byte displacement. */
14619 /* No displacement. */
14622 /* 2 byte displacement. */
14623 bytes_before_imm
+= 2;
14626 /* 1 byte displacement: when decoding the third source,
14627 don't increase bytes_before_imm as this has already
14628 been incremented by one in OP_E_memory while decoding
14629 the second source operand. */
14631 bytes_before_imm
++;
14639 FETCH_DATA (the_info
, codep
+ bytes_before_imm
+ 1);
14640 return codep
[bytes_before_imm
];
14644 OP_EX_VexReg (int bytemode
, int sizeflag
, int reg
)
14646 const char **names
;
14648 if (reg
== -1 && modrm
.mod
!= 3)
14650 OP_E_memory (bytemode
, sizeflag
);
14662 else if (reg
> 7 && address_mode
!= mode_64bit
)
14666 switch (vex
.length
)
14677 oappend (names
[reg
]);
14681 OP_EX_VexImmW (int bytemode
, int sizeflag
)
14684 static unsigned char vex_imm8
;
14686 if (vex_w_done
== 0)
14690 /* Skip mod/rm byte. */
14694 vex_imm8
= get_vex_imm8 (sizeflag
, 0);
14697 reg
= vex_imm8
>> 4;
14699 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
14701 else if (vex_w_done
== 1)
14706 reg
= vex_imm8
>> 4;
14708 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
14712 /* Output the imm8 directly. */
14713 scratchbuf
[0] = '$';
14714 print_operand_value (scratchbuf
+ 1, 1, vex_imm8
& 0xf);
14715 oappend (scratchbuf
+ intel_syntax
);
14716 scratchbuf
[0] = '\0';
14722 OP_Vex_2src (int bytemode
, int sizeflag
)
14724 if (modrm
.mod
== 3)
14726 int reg
= modrm
.rm
;
14730 oappend (names_xmm
[reg
]);
14735 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
14737 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
14738 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14740 OP_E (bytemode
, sizeflag
);
14745 OP_Vex_2src_1 (int bytemode
, int sizeflag
)
14747 if (modrm
.mod
== 3)
14749 /* Skip mod/rm byte. */
14755 oappend (names_xmm
[vex
.register_specifier
]);
14757 OP_Vex_2src (bytemode
, sizeflag
);
14761 OP_Vex_2src_2 (int bytemode
, int sizeflag
)
14764 OP_Vex_2src (bytemode
, sizeflag
);
14766 oappend (names_xmm
[vex
.register_specifier
]);
14770 OP_EX_VexW (int bytemode
, int sizeflag
)
14778 /* Skip mod/rm byte. */
14783 reg
= get_vex_imm8 (sizeflag
, 0) >> 4;
14788 reg
= get_vex_imm8 (sizeflag
, 1) >> 4;
14791 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
14795 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED
,
14796 int sizeflag ATTRIBUTE_UNUSED
)
14798 /* Skip the immediate byte and check for invalid bits. */
14799 FETCH_DATA (the_info
, codep
+ 1);
14800 if (*codep
++ & 0xf)
14805 OP_REG_VexI4 (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
14808 const char **names
;
14810 FETCH_DATA (the_info
, codep
+ 1);
14813 if (bytemode
!= x_mode
)
14820 if (reg
> 7 && address_mode
!= mode_64bit
)
14823 switch (vex
.length
)
14834 oappend (names
[reg
]);
14838 OP_XMM_VexW (int bytemode
, int sizeflag
)
14840 /* Turn off the REX.W bit since it is used for swapping operands
14843 OP_XMM (bytemode
, sizeflag
);
14847 OP_EX_Vex (int bytemode
, int sizeflag
)
14849 if (modrm
.mod
!= 3)
14851 if (vex
.register_specifier
!= 0)
14855 OP_EX (bytemode
, sizeflag
);
14859 OP_XMM_Vex (int bytemode
, int sizeflag
)
14861 if (modrm
.mod
!= 3)
14863 if (vex
.register_specifier
!= 0)
14867 OP_XMM (bytemode
, sizeflag
);
14871 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
14873 switch (vex
.length
)
14876 mnemonicendp
= stpcpy (obuf
, "vzeroupper");
14879 mnemonicendp
= stpcpy (obuf
, "vzeroall");
14886 static struct op vex_cmp_op
[] =
14888 { STRING_COMMA_LEN ("eq") },
14889 { STRING_COMMA_LEN ("lt") },
14890 { STRING_COMMA_LEN ("le") },
14891 { STRING_COMMA_LEN ("unord") },
14892 { STRING_COMMA_LEN ("neq") },
14893 { STRING_COMMA_LEN ("nlt") },
14894 { STRING_COMMA_LEN ("nle") },
14895 { STRING_COMMA_LEN ("ord") },
14896 { STRING_COMMA_LEN ("eq_uq") },
14897 { STRING_COMMA_LEN ("nge") },
14898 { STRING_COMMA_LEN ("ngt") },
14899 { STRING_COMMA_LEN ("false") },
14900 { STRING_COMMA_LEN ("neq_oq") },
14901 { STRING_COMMA_LEN ("ge") },
14902 { STRING_COMMA_LEN ("gt") },
14903 { STRING_COMMA_LEN ("true") },
14904 { STRING_COMMA_LEN ("eq_os") },
14905 { STRING_COMMA_LEN ("lt_oq") },
14906 { STRING_COMMA_LEN ("le_oq") },
14907 { STRING_COMMA_LEN ("unord_s") },
14908 { STRING_COMMA_LEN ("neq_us") },
14909 { STRING_COMMA_LEN ("nlt_uq") },
14910 { STRING_COMMA_LEN ("nle_uq") },
14911 { STRING_COMMA_LEN ("ord_s") },
14912 { STRING_COMMA_LEN ("eq_us") },
14913 { STRING_COMMA_LEN ("nge_uq") },
14914 { STRING_COMMA_LEN ("ngt_uq") },
14915 { STRING_COMMA_LEN ("false_os") },
14916 { STRING_COMMA_LEN ("neq_os") },
14917 { STRING_COMMA_LEN ("ge_oq") },
14918 { STRING_COMMA_LEN ("gt_oq") },
14919 { STRING_COMMA_LEN ("true_us") },
14923 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
14925 unsigned int cmp_type
;
14927 FETCH_DATA (the_info
, codep
+ 1);
14928 cmp_type
= *codep
++ & 0xff;
14929 if (cmp_type
< ARRAY_SIZE (vex_cmp_op
))
14932 char *p
= mnemonicendp
- 2;
14936 sprintf (p
, "%s%s", vex_cmp_op
[cmp_type
].name
, suffix
);
14937 mnemonicendp
+= vex_cmp_op
[cmp_type
].len
;
14941 /* We have a reserved extension byte. Output it directly. */
14942 scratchbuf
[0] = '$';
14943 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
14944 oappend (scratchbuf
+ intel_syntax
);
14945 scratchbuf
[0] = '\0';
14949 static const struct op pclmul_op
[] =
14951 { STRING_COMMA_LEN ("lql") },
14952 { STRING_COMMA_LEN ("hql") },
14953 { STRING_COMMA_LEN ("lqh") },
14954 { STRING_COMMA_LEN ("hqh") }
14958 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED
,
14959 int sizeflag ATTRIBUTE_UNUSED
)
14961 unsigned int pclmul_type
;
14963 FETCH_DATA (the_info
, codep
+ 1);
14964 pclmul_type
= *codep
++ & 0xff;
14965 switch (pclmul_type
)
14976 if (pclmul_type
< ARRAY_SIZE (pclmul_op
))
14979 char *p
= mnemonicendp
- 3;
14984 sprintf (p
, "%s%s", pclmul_op
[pclmul_type
].name
, suffix
);
14985 mnemonicendp
+= pclmul_op
[pclmul_type
].len
;
14989 /* We have a reserved extension byte. Output it directly. */
14990 scratchbuf
[0] = '$';
14991 print_operand_value (scratchbuf
+ 1, 1, pclmul_type
);
14992 oappend (scratchbuf
+ intel_syntax
);
14993 scratchbuf
[0] = '\0';
14998 MOVBE_Fixup (int bytemode
, int sizeflag
)
15000 /* Add proper suffix to "movbe". */
15001 char *p
= mnemonicendp
;
15010 if (sizeflag
& SUFFIX_ALWAYS
)
15016 if (sizeflag
& DFLAG
)
15020 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15025 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15032 OP_M (bytemode
, sizeflag
);
15036 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15039 const char **names
;
15041 /* Skip mod/rm byte. */
15055 oappend (names
[reg
]);
15059 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15061 const char **names
;
15068 oappend (names
[vex
.register_specifier
]);