opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
   3    2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
   4    Free Software Foundation, Inc.
   5
   6    This file is part of the GNU opcodes library.
   7
   8    This library is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3, or (at your option)
  11    any later version.
  12
  13    It is distributed in the hope that it will be useful, but WITHOUT
  14    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16    License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; if not, write to the Free Software
  20    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  21    MA 02110-1301, USA.  */
  22
  23
  24 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  25    July 1988
  26     modified by John Hassey (hassey@dg-rtp.dg.com)
  27     x86-64 support added by Jan Hubicka (jh@suse.cz)
  28     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  29
  30 /* The main tables describing the instructions is essentially a copy
  31    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  32    Programmers Manual.  Usually, there is a capital letter, followed
  33    by a small letter.  The capital letter tell the addressing mode,
  34    and the small letter tells about the operand size.  Refer to
  35    the Intel manual for details.  */
  36
  37 #include "sysdep.h"
  38 #include "dis-asm.h"
  39 #include "opintl.h"
  40 #include "opcode/i386.h"
  41 #include "libiberty.h"
  42
  43 #include <setjmp.h>
  44
  45 static int print_insn (bfd_vma, disassemble_info *);
  46 static void dofloat (int);
  47 static void OP_ST (int, int);
  48 static void OP_STi (int, int);
  49 static int putop (const char *, int);
  50 static void oappend (const char *);
  51 static void append_seg (void);
  52 static void OP_indirE (int, int);
  53 static void print_operand_value (char *, int, bfd_vma);
  54 static void OP_E_register (int, int);
  55 static void OP_E_memory (int, int);
  56 static void print_displacement (char *, bfd_vma);
  57 static void OP_E (int, int);
  58 static void OP_G (int, int);
  59 static bfd_vma get64 (void);
  60 static bfd_signed_vma get32 (void);
  61 static bfd_signed_vma get32s (void);
  62 static int get16 (void);
  63 static void set_op (bfd_vma, int);
  64 static void OP_Skip_MODRM (int, int);
  65 static void OP_REG (int, int);
  66 static void OP_IMREG (int, int);
  67 static void OP_I (int, int);
  68 static void OP_I64 (int, int);
  69 static void OP_sI (int, int);
  70 static void OP_J (int, int);
  71 static void OP_SEG (int, int);
  72 static void OP_DIR (int, int);
  73 static void OP_OFF (int, int);
  74 static void OP_OFF64 (int, int);
  75 static void ptr_reg (int, int);
  76 static void OP_ESreg (int, int);
  77 static void OP_DSreg (int, int);
  78 static void OP_C (int, int);
  79 static void OP_D (int, int);
  80 static void OP_T (int, int);
  81 static void OP_R (int, int);
  82 static void OP_MMX (int, int);
  83 static void OP_XMM (int, int);
  84 static void OP_EM (int, int);
  85 static void OP_EX (int, int);
  86 static void OP_EMC (int,int);
  87 static void OP_MXC (int,int);
  88 static void OP_MS (int, int);
  89 static void OP_XS (int, int);
  90 static void OP_M (int, int);
  91 static void OP_VEX (int, int);
  92 static void OP_EX_Vex (int, int);
  93 static void OP_EX_VexW (int, int);
  94 static void OP_EX_VexImmW (int, int);
  95 static void OP_XMM_Vex (int, int);
  96 static void OP_XMM_VexW (int, int);
  97 static void OP_REG_VexI4 (int, int);
  98 static void PCLMUL_Fixup (int, int);
  99 static void VEXI4_Fixup (int, int);
 100 static void VZERO_Fixup (int, int);
 101 static void VCMP_Fixup (int, int);
 102 static void OP_0f07 (int, int);
 103 static void OP_Monitor (int, int);
 104 static void OP_Mwait (int, int);
 105 static void NOP_Fixup1 (int, int);
 106 static void NOP_Fixup2 (int, int);
 107 static void OP_3DNowSuffix (int, int);
 108 static void CMP_Fixup (int, int);
 109 static void BadOp (void);
 110 static void REP_Fixup (int, int);
 111 static void CMPXCHG8B_Fixup (int, int);
 112 static void XMM_Fixup (int, int);
 113 static void CRC32_Fixup (int, int);
 114 static void FXSAVE_Fixup (int, int);
 115 static void OP_LWPCB_E (int, int);
 116 static void OP_LWP_E (int, int);
 117 static void OP_Vex_2src_1 (int, int);
 118 static void OP_Vex_2src_2 (int, int);
 119
 120 static void MOVBE_Fixup (int, int);
 121
 122 struct dis_private {
 123   /* Points to first byte not fetched.  */
 124   bfd_byte *max_fetched;
 125   bfd_byte the_buffer[MAX_MNEM_SIZE];
 126   bfd_vma insn_start;
 127   int orig_sizeflag;
 128   jmp_buf bailout;
 129 };
 130
 131 enum address_mode
 132 {
 133   mode_16bit,
 134   mode_32bit,
 135   mode_64bit
 136 };
 137
 138 enum address_mode address_mode;
 139
 140 /* Flags for the prefixes for the current instruction.  See below.  */
 141 static int prefixes;
 142
 143 /* REX prefix the current instruction.  See below.  */
 144 static int rex;
 145 /* Bits of REX we've already used.  */
 146 static int rex_used;
 147 /* REX bits in original REX prefix ignored.  */
 148 static int rex_ignored;
 149 /* Mark parts used in the REX prefix.  When we are testing for
 150    empty prefix (for 8bit register REX extension), just mask it
 151    out.  Otherwise test for REX bit is excuse for existence of REX
 152    only in case value is nonzero.  */
 153 #define USED_REX(value)                                 \
 154   {                                                     \
 155     if (value)                                          \
 156       {                                                 \
 157         if ((rex & value))                              \
 158           rex_used |= (value) | REX_OPCODE;             \
 159       }                                                 \
 160     else                                                \
 161       rex_used |= REX_OPCODE;                           \
 162   }
 163
 164 /* Flags for prefixes which we somehow handled when printing the
 165    current instruction.  */
 166 static int used_prefixes;
 167
 168 /* Flags stored in PREFIXES.  */
 169 #define PREFIX_REPZ 1
 170 #define PREFIX_REPNZ 2
 171 #define PREFIX_LOCK 4
 172 #define PREFIX_CS 8
 173 #define PREFIX_SS 0x10
 174 #define PREFIX_DS 0x20
 175 #define PREFIX_ES 0x40
 176 #define PREFIX_FS 0x80
 177 #define PREFIX_GS 0x100
 178 #define PREFIX_DATA 0x200
 179 #define PREFIX_ADDR 0x400
 180 #define PREFIX_FWAIT 0x800
 181
 182 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 183    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 184    on error.  */
 185 #define FETCH_DATA(info, addr) \
 186   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 187    ? 1 : fetch_data ((info), (addr)))
 188
 189 static int
 190 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 191 {
 192   int status;
 193   struct dis_private *priv = (struct dis_private *) info->private_data;
 194   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 195
 196   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 197     status = (*info->read_memory_func) (start,
 198                                         priv->max_fetched,
 199                                         addr - priv->max_fetched,
 200                                         info);
 201   else
 202     status = -1;
 203   if (status != 0)
 204     {
 205       /* If we did manage to read at least one byte, then
 206          print_insn_i386 will do something sensible.  Otherwise, print
 207          an error.  We do that here because this is where we know
 208          STATUS.  */
 209       if (priv->max_fetched == priv->the_buffer)
 210         (*info->memory_error_func) (status, start, info);
 211       longjmp (priv->bailout, 1);
 212     }
 213   else
 214     priv->max_fetched = addr;
 215   return 1;
 216 }
 217
 218 #define XX { NULL, 0 }
 219 #define Bad_Opcode NULL, { { NULL, 0 } }
 220
 221 #define Eb { OP_E, b_mode }
 222 #define EbS { OP_E, b_swap_mode }
 223 #define Ev { OP_E, v_mode }
 224 #define EvS { OP_E, v_swap_mode }
 225 #define Ed { OP_E, d_mode }
 226 #define Edq { OP_E, dq_mode }
 227 #define Edqw { OP_E, dqw_mode }
 228 #define Edqb { OP_E, dqb_mode }
 229 #define Edqd { OP_E, dqd_mode }
 230 #define Eq { OP_E, q_mode }
 231 #define indirEv { OP_indirE, stack_v_mode }
 232 #define indirEp { OP_indirE, f_mode }
 233 #define stackEv { OP_E, stack_v_mode }
 234 #define Em { OP_E, m_mode }
 235 #define Ew { OP_E, w_mode }
 236 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 237 #define Ma { OP_M, a_mode }
 238 #define Mb { OP_M, b_mode }
 239 #define Md { OP_M, d_mode }
 240 #define Mo { OP_M, o_mode }
 241 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 242 #define Mq { OP_M, q_mode }
 243 #define Mx { OP_M, x_mode }
 244 #define Mxmm { OP_M, xmm_mode }
 245 #define Gb { OP_G, b_mode }
 246 #define Gv { OP_G, v_mode }
 247 #define Gd { OP_G, d_mode }
 248 #define Gdq { OP_G, dq_mode }
 249 #define Gm { OP_G, m_mode }
 250 #define Gw { OP_G, w_mode }
 251 #define Rd { OP_R, d_mode }
 252 #define Rm { OP_R, m_mode }
 253 #define Ib { OP_I, b_mode }
 254 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 255 #define Iv { OP_I, v_mode }
 256 #define sIv { OP_sI, v_mode }
 257 #define Iq { OP_I, q_mode }
 258 #define Iv64 { OP_I64, v_mode }
 259 #define Iw { OP_I, w_mode }
 260 #define I1 { OP_I, const_1_mode }
 261 #define Jb { OP_J, b_mode }
 262 #define Jv { OP_J, v_mode }
 263 #define Cm { OP_C, m_mode }
 264 #define Dm { OP_D, m_mode }
 265 #define Td { OP_T, d_mode }
 266 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 267
 268 #define RMeAX { OP_REG, eAX_reg }
 269 #define RMeBX { OP_REG, eBX_reg }
 270 #define RMeCX { OP_REG, eCX_reg }
 271 #define RMeDX { OP_REG, eDX_reg }
 272 #define RMeSP { OP_REG, eSP_reg }
 273 #define RMeBP { OP_REG, eBP_reg }
 274 #define RMeSI { OP_REG, eSI_reg }
 275 #define RMeDI { OP_REG, eDI_reg }
 276 #define RMrAX { OP_REG, rAX_reg }
 277 #define RMrBX { OP_REG, rBX_reg }
 278 #define RMrCX { OP_REG, rCX_reg }
 279 #define RMrDX { OP_REG, rDX_reg }
 280 #define RMrSP { OP_REG, rSP_reg }
 281 #define RMrBP { OP_REG, rBP_reg }
 282 #define RMrSI { OP_REG, rSI_reg }
 283 #define RMrDI { OP_REG, rDI_reg }
 284 #define RMAL { OP_REG, al_reg }
 285 #define RMAL { OP_REG, al_reg }
 286 #define RMCL { OP_REG, cl_reg }
 287 #define RMDL { OP_REG, dl_reg }
 288 #define RMBL { OP_REG, bl_reg }
 289 #define RMAH { OP_REG, ah_reg }
 290 #define RMCH { OP_REG, ch_reg }
 291 #define RMDH { OP_REG, dh_reg }
 292 #define RMBH { OP_REG, bh_reg }
 293 #define RMAX { OP_REG, ax_reg }
 294 #define RMDX { OP_REG, dx_reg }
 295
 296 #define eAX { OP_IMREG, eAX_reg }
 297 #define eBX { OP_IMREG, eBX_reg }
 298 #define eCX { OP_IMREG, eCX_reg }
 299 #define eDX { OP_IMREG, eDX_reg }
 300 #define eSP { OP_IMREG, eSP_reg }
 301 #define eBP { OP_IMREG, eBP_reg }
 302 #define eSI { OP_IMREG, eSI_reg }
 303 #define eDI { OP_IMREG, eDI_reg }
 304 #define AL { OP_IMREG, al_reg }
 305 #define CL { OP_IMREG, cl_reg }
 306 #define DL { OP_IMREG, dl_reg }
 307 #define BL { OP_IMREG, bl_reg }
 308 #define AH { OP_IMREG, ah_reg }
 309 #define CH { OP_IMREG, ch_reg }
 310 #define DH { OP_IMREG, dh_reg }
 311 #define BH { OP_IMREG, bh_reg }
 312 #define AX { OP_IMREG, ax_reg }
 313 #define DX { OP_IMREG, dx_reg }
 314 #define zAX { OP_IMREG, z_mode_ax_reg }
 315 #define indirDX { OP_IMREG, indir_dx_reg }
 316
 317 #define Sw { OP_SEG, w_mode }
 318 #define Sv { OP_SEG, v_mode }
 319 #define Ap { OP_DIR, 0 }
 320 #define Ob { OP_OFF64, b_mode }
 321 #define Ov { OP_OFF64, v_mode }
 322 #define Xb { OP_DSreg, eSI_reg }
 323 #define Xv { OP_DSreg, eSI_reg }
 324 #define Xz { OP_DSreg, eSI_reg }
 325 #define Yb { OP_ESreg, eDI_reg }
 326 #define Yv { OP_ESreg, eDI_reg }
 327 #define DSBX { OP_DSreg, eBX_reg }
 328
 329 #define es { OP_REG, es_reg }
 330 #define ss { OP_REG, ss_reg }
 331 #define cs { OP_REG, cs_reg }
 332 #define ds { OP_REG, ds_reg }
 333 #define fs { OP_REG, fs_reg }
 334 #define gs { OP_REG, gs_reg }
 335
 336 #define MX { OP_MMX, 0 }
 337 #define XM { OP_XMM, 0 }
 338 #define XMScalar { OP_XMM, scalar_mode }
 339 #define XMM { OP_XMM, xmm_mode }
 340 #define EM { OP_EM, v_mode }
 341 #define EMS { OP_EM, v_swap_mode }
 342 #define EMd { OP_EM, d_mode }
 343 #define EMx { OP_EM, x_mode }
 344 #define EXw { OP_EX, w_mode }
 345 #define EXd { OP_EX, d_mode }
 346 #define EXdScalar { OP_EX, d_scalar_mode }
 347 #define EXdS { OP_EX, d_swap_mode }
 348 #define EXq { OP_EX, q_mode }
 349 #define EXqScalar { OP_EX, q_scalar_mode }
 350 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 351 #define EXqS { OP_EX, q_swap_mode }
 352 #define EXx { OP_EX, x_mode }
 353 #define EXxS { OP_EX, x_swap_mode }
 354 #define EXxmm { OP_EX, xmm_mode }
 355 #define EXxmmq { OP_EX, xmmq_mode }
 356 #define EXymmq { OP_EX, ymmq_mode }
 357 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 358 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 359 #define MS { OP_MS, v_mode }
 360 #define XS { OP_XS, v_mode }
 361 #define EMCq { OP_EMC, q_mode }
 362 #define MXC { OP_MXC, 0 }
 363 #define OPSUF { OP_3DNowSuffix, 0 }
 364 #define CMP { CMP_Fixup, 0 }
 365 #define XMM0 { XMM_Fixup, 0 }
 366 #define FXSAVE { FXSAVE_Fixup, 0 }
 367 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 368 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 369
 370 #define Vex { OP_VEX, vex_mode }
 371 #define VexScalar { OP_VEX, vex_scalar_mode }
 372 #define Vex128 { OP_VEX, vex128_mode }
 373 #define Vex256 { OP_VEX, vex256_mode }
 374 #define VexI4 { VEXI4_Fixup, 0}
 375 #define EXdVex { OP_EX_Vex, d_mode }
 376 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 377 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 378 #define EXqVex { OP_EX_Vex, q_mode }
 379 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 380 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 381 #define EXVexW { OP_EX_VexW, x_mode }
 382 #define EXdVexW { OP_EX_VexW, d_mode }
 383 #define EXqVexW { OP_EX_VexW, q_mode }
 384 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 385 #define XMVex { OP_XMM_Vex, 0 }
 386 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 387 #define XMVexW { OP_XMM_VexW, 0 }
 388 #define XMVexI4 { OP_REG_VexI4, x_mode }
 389 #define PCLMUL { PCLMUL_Fixup, 0 }
 390 #define VZERO { VZERO_Fixup, 0 }
 391 #define VCMP { VCMP_Fixup, 0 }
 392
 393 /* Used handle "rep" prefix for string instructions.  */
 394 #define Xbr { REP_Fixup, eSI_reg }
 395 #define Xvr { REP_Fixup, eSI_reg }
 396 #define Ybr { REP_Fixup, eDI_reg }
 397 #define Yvr { REP_Fixup, eDI_reg }
 398 #define Yzr { REP_Fixup, eDI_reg }
 399 #define indirDXr { REP_Fixup, indir_dx_reg }
 400 #define ALr { REP_Fixup, al_reg }
 401 #define eAXr { REP_Fixup, eAX_reg }
 402
 403 #define cond_jump_flag { NULL, cond_jump_mode }
 404 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 405
 406 /* bits in sizeflag */
 407 #define SUFFIX_ALWAYS 4
 408 #define AFLAG 2
 409 #define DFLAG 1
 410
 411 enum
 412 {
 413   /* byte operand */
 414   b_mode = 1,
 415   /* byte operand with operand swapped */
 416   b_swap_mode,
 417   /* operand size depends on prefixes */
 418   v_mode,
 419   /* operand size depends on prefixes with operand swapped */
 420   v_swap_mode,
 421   /* word operand */
 422   w_mode,
 423   /* double word operand  */
 424   d_mode,
 425   /* double word operand with operand swapped */
 426   d_swap_mode,
 427   /* quad word operand */
 428   q_mode,
 429   /* quad word operand with operand swapped */
 430   q_swap_mode,
 431   /* ten-byte operand */
 432   t_mode,
 433   /* 16-byte XMM or 32-byte YMM operand */
 434   x_mode,
 435   /* 16-byte XMM or 32-byte YMM operand with operand swapped */
 436   x_swap_mode,
 437   /* 16-byte XMM operand */
 438   xmm_mode,
 439   /* 16-byte XMM or quad word operand */
 440   xmmq_mode,
 441   /* 32-byte YMM or quad word operand */
 442   ymmq_mode,
 443   /* d_mode in 32bit, q_mode in 64bit mode.  */
 444   m_mode,
 445   /* pair of v_mode operands */
 446   a_mode,
 447   cond_jump_mode,
 448   loop_jcxz_mode,
 449   /* operand size depends on REX prefixes.  */
 450   dq_mode,
 451   /* registers like dq_mode, memory like w_mode.  */
 452   dqw_mode,
 453   /* 4- or 6-byte pointer operand */
 454   f_mode,
 455   const_1_mode,
 456   /* v_mode for stack-related opcodes.  */
 457   stack_v_mode,
 458   /* non-quad operand size depends on prefixes */
 459   z_mode,
 460   /* 16-byte operand */
 461   o_mode,
 462   /* registers like dq_mode, memory like b_mode.  */
 463   dqb_mode,
 464   /* registers like dq_mode, memory like d_mode.  */
 465   dqd_mode,
 466   /* normal vex mode */
 467   vex_mode,
 468   /* 128bit vex mode */
 469   vex128_mode,
 470   /* 256bit vex mode */
 471   vex256_mode,
 472   /* operand size depends on the VEX.W bit.  */
 473   vex_w_dq_mode,
 474
 475   /* scalar, ignore vector length.  */
 476   scalar_mode,
 477   /* like d_mode, ignore vector length.  */
 478   d_scalar_mode,
 479   /* like d_swap_mode, ignore vector length.  */
 480   d_scalar_swap_mode,
 481   /* like q_mode, ignore vector length.  */
 482   q_scalar_mode,
 483   /* like q_swap_mode, ignore vector length.  */
 484   q_scalar_swap_mode,
 485   /* like vex_mode, ignore vector length.  */
 486   vex_scalar_mode,
 487   /* like vex_w_dq_mode, ignore vector length.  */
 488   vex_scalar_w_dq_mode,
 489
 490   es_reg,
 491   cs_reg,
 492   ss_reg,
 493   ds_reg,
 494   fs_reg,
 495   gs_reg,
 496
 497   eAX_reg,
 498   eCX_reg,
 499   eDX_reg,
 500   eBX_reg,
 501   eSP_reg,
 502   eBP_reg,
 503   eSI_reg,
 504   eDI_reg,
 505
 506   al_reg,
 507   cl_reg,
 508   dl_reg,
 509   bl_reg,
 510   ah_reg,
 511   ch_reg,
 512   dh_reg,
 513   bh_reg,
 514
 515   ax_reg,
 516   cx_reg,
 517   dx_reg,
 518   bx_reg,
 519   sp_reg,
 520   bp_reg,
 521   si_reg,
 522   di_reg,
 523
 524   rAX_reg,
 525   rCX_reg,
 526   rDX_reg,
 527   rBX_reg,
 528   rSP_reg,
 529   rBP_reg,
 530   rSI_reg,
 531   rDI_reg,
 532
 533   z_mode_ax_reg,
 534   indir_dx_reg
 535 };
 536
 537 enum
 538 {
 539   FLOATCODE = 1,
 540   USE_REG_TABLE,
 541   USE_MOD_TABLE,
 542   USE_RM_TABLE,
 543   USE_PREFIX_TABLE,
 544   USE_X86_64_TABLE,
 545   USE_3BYTE_TABLE,
 546   USE_XOP_8F_TABLE,
 547   USE_VEX_C4_TABLE,
 548   USE_VEX_C5_TABLE,
 549   USE_VEX_LEN_TABLE,
 550   USE_VEX_W_TABLE
 551 };
 552
 553 #define FLOAT                   NULL, { { NULL, FLOATCODE } }
 554
 555 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }
 556 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 557 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 558 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 559 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 560 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 561 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 562 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 563 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 564 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 565 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 566 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 567
 568 enum
 569 {
 570   REG_80 = 0,
 571   REG_81,
 572   REG_82,
 573   REG_8F,
 574   REG_C0,
 575   REG_C1,
 576   REG_C6,
 577   REG_C7,
 578   REG_D0,
 579   REG_D1,
 580   REG_D2,
 581   REG_D3,
 582   REG_F6,
 583   REG_F7,
 584   REG_FE,
 585   REG_FF,
 586   REG_0F00,
 587   REG_0F01,
 588   REG_0F0D,
 589   REG_0F18,
 590   REG_0F71,
 591   REG_0F72,
 592   REG_0F73,
 593   REG_0FA6,
 594   REG_0FA7,
 595   REG_0FAE,
 596   REG_0FBA,
 597   REG_0FC7,
 598   REG_VEX_0F71,
 599   REG_VEX_0F72,
 600   REG_VEX_0F73,
 601   REG_VEX_0FAE,
 602   REG_XOP_LWPCB,
 603   REG_XOP_LWP
 604 };
 605
 606 enum
 607 {
 608   MOD_8D = 0,
 609   MOD_0F01_REG_0,
 610   MOD_0F01_REG_1,
 611   MOD_0F01_REG_2,
 612   MOD_0F01_REG_3,
 613   MOD_0F01_REG_7,
 614   MOD_0F12_PREFIX_0,
 615   MOD_0F13,
 616   MOD_0F16_PREFIX_0,
 617   MOD_0F17,
 618   MOD_0F18_REG_0,
 619   MOD_0F18_REG_1,
 620   MOD_0F18_REG_2,
 621   MOD_0F18_REG_3,
 622   MOD_0F20,
 623   MOD_0F21,
 624   MOD_0F22,
 625   MOD_0F23,
 626   MOD_0F24,
 627   MOD_0F26,
 628   MOD_0F2B_PREFIX_0,
 629   MOD_0F2B_PREFIX_1,
 630   MOD_0F2B_PREFIX_2,
 631   MOD_0F2B_PREFIX_3,
 632   MOD_0F51,
 633   MOD_0F71_REG_2,
 634   MOD_0F71_REG_4,
 635   MOD_0F71_REG_6,
 636   MOD_0F72_REG_2,
 637   MOD_0F72_REG_4,
 638   MOD_0F72_REG_6,
 639   MOD_0F73_REG_2,
 640   MOD_0F73_REG_3,
 641   MOD_0F73_REG_6,
 642   MOD_0F73_REG_7,
 643   MOD_0FAE_REG_0,
 644   MOD_0FAE_REG_1,
 645   MOD_0FAE_REG_2,
 646   MOD_0FAE_REG_3,
 647   MOD_0FAE_REG_4,
 648   MOD_0FAE_REG_5,
 649   MOD_0FAE_REG_6,
 650   MOD_0FAE_REG_7,
 651   MOD_0FB2,
 652   MOD_0FB4,
 653   MOD_0FB5,
 654   MOD_0FC7_REG_6,
 655   MOD_0FC7_REG_7,
 656   MOD_0FD7,
 657   MOD_0FE7_PREFIX_2,
 658   MOD_0FF0_PREFIX_3,
 659   MOD_0F382A_PREFIX_2,
 660   MOD_62_32BIT,
 661   MOD_C4_32BIT,
 662   MOD_C5_32BIT,
 663   MOD_VEX_0F12_PREFIX_0,
 664   MOD_VEX_0F13,
 665   MOD_VEX_0F16_PREFIX_0,
 666   MOD_VEX_0F17,
 667   MOD_VEX_0F2B,
 668   MOD_VEX_0F50,
 669   MOD_VEX_0F71_REG_2,
 670   MOD_VEX_0F71_REG_4,
 671   MOD_VEX_0F71_REG_6,
 672   MOD_VEX_0F72_REG_2,
 673   MOD_VEX_0F72_REG_4,
 674   MOD_VEX_0F72_REG_6,
 675   MOD_VEX_0F73_REG_2,
 676   MOD_VEX_0F73_REG_3,
 677   MOD_VEX_0F73_REG_6,
 678   MOD_VEX_0F73_REG_7,
 679   MOD_VEX_0FAE_REG_2,
 680   MOD_VEX_0FAE_REG_3,
 681   MOD_VEX_0FD7_PREFIX_2,
 682   MOD_VEX_0FE7_PREFIX_2,
 683   MOD_VEX_0FF0_PREFIX_3,
 684   MOD_VEX_0F3818_PREFIX_2,
 685   MOD_VEX_0F3819_PREFIX_2,
 686   MOD_VEX_0F381A_PREFIX_2,
 687   MOD_VEX_0F382A_PREFIX_2,
 688   MOD_VEX_0F382C_PREFIX_2,
 689   MOD_VEX_0F382D_PREFIX_2,
 690   MOD_VEX_0F382E_PREFIX_2,
 691   MOD_VEX_0F382F_PREFIX_2
 692 };
 693
 694 enum
 695 {
 696   RM_0F01_REG_0 = 0,
 697   RM_0F01_REG_1,
 698   RM_0F01_REG_2,
 699   RM_0F01_REG_3,
 700   RM_0F01_REG_7,
 701   RM_0FAE_REG_5,
 702   RM_0FAE_REG_6,
 703   RM_0FAE_REG_7
 704 };
 705
 706 enum
 707 {
 708   PREFIX_90 = 0,
 709   PREFIX_0F10,
 710   PREFIX_0F11,
 711   PREFIX_0F12,
 712   PREFIX_0F16,
 713   PREFIX_0F2A,
 714   PREFIX_0F2B,
 715   PREFIX_0F2C,
 716   PREFIX_0F2D,
 717   PREFIX_0F2E,
 718   PREFIX_0F2F,
 719   PREFIX_0F51,
 720   PREFIX_0F52,
 721   PREFIX_0F53,
 722   PREFIX_0F58,
 723   PREFIX_0F59,
 724   PREFIX_0F5A,
 725   PREFIX_0F5B,
 726   PREFIX_0F5C,
 727   PREFIX_0F5D,
 728   PREFIX_0F5E,
 729   PREFIX_0F5F,
 730   PREFIX_0F60,
 731   PREFIX_0F61,
 732   PREFIX_0F62,
 733   PREFIX_0F6C,
 734   PREFIX_0F6D,
 735   PREFIX_0F6F,
 736   PREFIX_0F70,
 737   PREFIX_0F73_REG_3,
 738   PREFIX_0F73_REG_7,
 739   PREFIX_0F78,
 740   PREFIX_0F79,
 741   PREFIX_0F7C,
 742   PREFIX_0F7D,
 743   PREFIX_0F7E,
 744   PREFIX_0F7F,
 745   PREFIX_0FAE_REG_0,
 746   PREFIX_0FAE_REG_1,
 747   PREFIX_0FAE_REG_2,
 748   PREFIX_0FAE_REG_3,
 749   PREFIX_0FB8,
 750   PREFIX_0FBD,
 751   PREFIX_0FC2,
 752   PREFIX_0FC3,
 753   PREFIX_0FC7_REG_6,
 754   PREFIX_0FD0,
 755   PREFIX_0FD6,
 756   PREFIX_0FE6,
 757   PREFIX_0FE7,
 758   PREFIX_0FF0,
 759   PREFIX_0FF7,
 760   PREFIX_0F3810,
 761   PREFIX_0F3814,
 762   PREFIX_0F3815,
 763   PREFIX_0F3817,
 764   PREFIX_0F3820,
 765   PREFIX_0F3821,
 766   PREFIX_0F3822,
 767   PREFIX_0F3823,
 768   PREFIX_0F3824,
 769   PREFIX_0F3825,
 770   PREFIX_0F3828,
 771   PREFIX_0F3829,
 772   PREFIX_0F382A,
 773   PREFIX_0F382B,
 774   PREFIX_0F3830,
 775   PREFIX_0F3831,
 776   PREFIX_0F3832,
 777   PREFIX_0F3833,
 778   PREFIX_0F3834,
 779   PREFIX_0F3835,
 780   PREFIX_0F3837,
 781   PREFIX_0F3838,
 782   PREFIX_0F3839,
 783   PREFIX_0F383A,
 784   PREFIX_0F383B,
 785   PREFIX_0F383C,
 786   PREFIX_0F383D,
 787   PREFIX_0F383E,
 788   PREFIX_0F383F,
 789   PREFIX_0F3840,
 790   PREFIX_0F3841,
 791   PREFIX_0F3880,
 792   PREFIX_0F3881,
 793   PREFIX_0F38DB,
 794   PREFIX_0F38DC,
 795   PREFIX_0F38DD,
 796   PREFIX_0F38DE,
 797   PREFIX_0F38DF,
 798   PREFIX_0F38F0,
 799   PREFIX_0F38F1,
 800   PREFIX_0F3A08,
 801   PREFIX_0F3A09,
 802   PREFIX_0F3A0A,
 803   PREFIX_0F3A0B,
 804   PREFIX_0F3A0C,
 805   PREFIX_0F3A0D,
 806   PREFIX_0F3A0E,
 807   PREFIX_0F3A14,
 808   PREFIX_0F3A15,
 809   PREFIX_0F3A16,
 810   PREFIX_0F3A17,
 811   PREFIX_0F3A20,
 812   PREFIX_0F3A21,
 813   PREFIX_0F3A22,
 814   PREFIX_0F3A40,
 815   PREFIX_0F3A41,
 816   PREFIX_0F3A42,
 817   PREFIX_0F3A44,
 818   PREFIX_0F3A60,
 819   PREFIX_0F3A61,
 820   PREFIX_0F3A62,
 821   PREFIX_0F3A63,
 822   PREFIX_0F3ADF,
 823   PREFIX_VEX_0F10,
 824   PREFIX_VEX_0F11,
 825   PREFIX_VEX_0F12,
 826   PREFIX_VEX_0F16,
 827   PREFIX_VEX_0F2A,
 828   PREFIX_VEX_0F2C,
 829   PREFIX_VEX_0F2D,
 830   PREFIX_VEX_0F2E,
 831   PREFIX_VEX_0F2F,
 832   PREFIX_VEX_0F51,
 833   PREFIX_VEX_0F52,
 834   PREFIX_VEX_0F53,
 835   PREFIX_VEX_0F58,
 836   PREFIX_VEX_0F59,
 837   PREFIX_VEX_0F5A,
 838   PREFIX_VEX_0F5B,
 839   PREFIX_VEX_0F5C,
 840   PREFIX_VEX_0F5D,
 841   PREFIX_VEX_0F5E,
 842   PREFIX_VEX_0F5F,
 843   PREFIX_VEX_0F60,
 844   PREFIX_VEX_0F61,
 845   PREFIX_VEX_0F62,
 846   PREFIX_VEX_0F63,
 847   PREFIX_VEX_0F64,
 848   PREFIX_VEX_0F65,
 849   PREFIX_VEX_0F66,
 850   PREFIX_VEX_0F67,
 851   PREFIX_VEX_0F68,
 852   PREFIX_VEX_0F69,
 853   PREFIX_VEX_0F6A,
 854   PREFIX_VEX_0F6B,
 855   PREFIX_VEX_0F6C,
 856   PREFIX_VEX_0F6D,
 857   PREFIX_VEX_0F6E,
 858   PREFIX_VEX_0F6F,
 859   PREFIX_VEX_0F70,
 860   PREFIX_VEX_0F71_REG_2,
 861   PREFIX_VEX_0F71_REG_4,
 862   PREFIX_VEX_0F71_REG_6,
 863   PREFIX_VEX_0F72_REG_2,
 864   PREFIX_VEX_0F72_REG_4,
 865   PREFIX_VEX_0F72_REG_6,
 866   PREFIX_VEX_0F73_REG_2,
 867   PREFIX_VEX_0F73_REG_3,
 868   PREFIX_VEX_0F73_REG_6,
 869   PREFIX_VEX_0F73_REG_7,
 870   PREFIX_VEX_0F74,
 871   PREFIX_VEX_0F75,
 872   PREFIX_VEX_0F76,
 873   PREFIX_VEX_0F77,
 874   PREFIX_VEX_0F7C,
 875   PREFIX_VEX_0F7D,
 876   PREFIX_VEX_0F7E,
 877   PREFIX_VEX_0F7F,
 878   PREFIX_VEX_0FC2,
 879   PREFIX_VEX_0FC4,
 880   PREFIX_VEX_0FC5,
 881   PREFIX_VEX_0FD0,
 882   PREFIX_VEX_0FD1,
 883   PREFIX_VEX_0FD2,
 884   PREFIX_VEX_0FD3,
 885   PREFIX_VEX_0FD4,
 886   PREFIX_VEX_0FD5,
 887   PREFIX_VEX_0FD6,
 888   PREFIX_VEX_0FD7,
 889   PREFIX_VEX_0FD8,
 890   PREFIX_VEX_0FD9,
 891   PREFIX_VEX_0FDA,
 892   PREFIX_VEX_0FDB,
 893   PREFIX_VEX_0FDC,
 894   PREFIX_VEX_0FDD,
 895   PREFIX_VEX_0FDE,
 896   PREFIX_VEX_0FDF,
 897   PREFIX_VEX_0FE0,
 898   PREFIX_VEX_0FE1,
 899   PREFIX_VEX_0FE2,
 900   PREFIX_VEX_0FE3,
 901   PREFIX_VEX_0FE4,
 902   PREFIX_VEX_0FE5,
 903   PREFIX_VEX_0FE6,
 904   PREFIX_VEX_0FE7,
 905   PREFIX_VEX_0FE8,
 906   PREFIX_VEX_0FE9,
 907   PREFIX_VEX_0FEA,
 908   PREFIX_VEX_0FEB,
 909   PREFIX_VEX_0FEC,
 910   PREFIX_VEX_0FED,
 911   PREFIX_VEX_0FEE,
 912   PREFIX_VEX_0FEF,
 913   PREFIX_VEX_0FF0,
 914   PREFIX_VEX_0FF1,
 915   PREFIX_VEX_0FF2,
 916   PREFIX_VEX_0FF3,
 917   PREFIX_VEX_0FF4,
 918   PREFIX_VEX_0FF5,
 919   PREFIX_VEX_0FF6,
 920   PREFIX_VEX_0FF7,
 921   PREFIX_VEX_0FF8,
 922   PREFIX_VEX_0FF9,
 923   PREFIX_VEX_0FFA,
 924   PREFIX_VEX_0FFB,
 925   PREFIX_VEX_0FFC,
 926   PREFIX_VEX_0FFD,
 927   PREFIX_VEX_0FFE,
 928   PREFIX_VEX_0F3800,
 929   PREFIX_VEX_0F3801,
 930   PREFIX_VEX_0F3802,
 931   PREFIX_VEX_0F3803,
 932   PREFIX_VEX_0F3804,
 933   PREFIX_VEX_0F3805,
 934   PREFIX_VEX_0F3806,
 935   PREFIX_VEX_0F3807,
 936   PREFIX_VEX_0F3808,
 937   PREFIX_VEX_0F3809,
 938   PREFIX_VEX_0F380A,
 939   PREFIX_VEX_0F380B,
 940   PREFIX_VEX_0F380C,
 941   PREFIX_VEX_0F380D,
 942   PREFIX_VEX_0F380E,
 943   PREFIX_VEX_0F380F,
 944   PREFIX_VEX_0F3813,
 945   PREFIX_VEX_0F3817,
 946   PREFIX_VEX_0F3818,
 947   PREFIX_VEX_0F3819,
 948   PREFIX_VEX_0F381A,
 949   PREFIX_VEX_0F381C,
 950   PREFIX_VEX_0F381D,
 951   PREFIX_VEX_0F381E,
 952   PREFIX_VEX_0F3820,
 953   PREFIX_VEX_0F3821,
 954   PREFIX_VEX_0F3822,
 955   PREFIX_VEX_0F3823,
 956   PREFIX_VEX_0F3824,
 957   PREFIX_VEX_0F3825,
 958   PREFIX_VEX_0F3828,
 959   PREFIX_VEX_0F3829,
 960   PREFIX_VEX_0F382A,
 961   PREFIX_VEX_0F382B,
 962   PREFIX_VEX_0F382C,
 963   PREFIX_VEX_0F382D,
 964   PREFIX_VEX_0F382E,
 965   PREFIX_VEX_0F382F,
 966   PREFIX_VEX_0F3830,
 967   PREFIX_VEX_0F3831,
 968   PREFIX_VEX_0F3832,
 969   PREFIX_VEX_0F3833,
 970   PREFIX_VEX_0F3834,
 971   PREFIX_VEX_0F3835,
 972   PREFIX_VEX_0F3837,
 973   PREFIX_VEX_0F3838,
 974   PREFIX_VEX_0F3839,
 975   PREFIX_VEX_0F383A,
 976   PREFIX_VEX_0F383B,
 977   PREFIX_VEX_0F383C,
 978   PREFIX_VEX_0F383D,
 979   PREFIX_VEX_0F383E,
 980   PREFIX_VEX_0F383F,
 981   PREFIX_VEX_0F3840,
 982   PREFIX_VEX_0F3841,
 983   PREFIX_VEX_0F3896,
 984   PREFIX_VEX_0F3897,
 985   PREFIX_VEX_0F3898,
 986   PREFIX_VEX_0F3899,
 987   PREFIX_VEX_0F389A,
 988   PREFIX_VEX_0F389B,
 989   PREFIX_VEX_0F389C,
 990   PREFIX_VEX_0F389D,
 991   PREFIX_VEX_0F389E,
 992   PREFIX_VEX_0F389F,
 993   PREFIX_VEX_0F38A6,
 994   PREFIX_VEX_0F38A7,
 995   PREFIX_VEX_0F38A8,
 996   PREFIX_VEX_0F38A9,
 997   PREFIX_VEX_0F38AA,
 998   PREFIX_VEX_0F38AB,
 999   PREFIX_VEX_0F38AC,
1000   PREFIX_VEX_0F38AD,
1001   PREFIX_VEX_0F38AE,
1002   PREFIX_VEX_0F38AF,
1003   PREFIX_VEX_0F38B6,
1004   PREFIX_VEX_0F38B7,
1005   PREFIX_VEX_0F38B8,
1006   PREFIX_VEX_0F38B9,
1007   PREFIX_VEX_0F38BA,
1008   PREFIX_VEX_0F38BB,
1009   PREFIX_VEX_0F38BC,
1010   PREFIX_VEX_0F38BD,
1011   PREFIX_VEX_0F38BE,
1012   PREFIX_VEX_0F38BF,
1013   PREFIX_VEX_0F38DB,
1014   PREFIX_VEX_0F38DC,
1015   PREFIX_VEX_0F38DD,
1016   PREFIX_VEX_0F38DE,
1017   PREFIX_VEX_0F38DF,
1018   PREFIX_VEX_0F3A04,
1019   PREFIX_VEX_0F3A05,
1020   PREFIX_VEX_0F3A06,
1021   PREFIX_VEX_0F3A08,
1022   PREFIX_VEX_0F3A09,
1023   PREFIX_VEX_0F3A0A,
1024   PREFIX_VEX_0F3A0B,
1025   PREFIX_VEX_0F3A0C,
1026   PREFIX_VEX_0F3A0D,
1027   PREFIX_VEX_0F3A0E,
1028   PREFIX_VEX_0F3A0F,
1029   PREFIX_VEX_0F3A14,
1030   PREFIX_VEX_0F3A15,
1031   PREFIX_VEX_0F3A16,
1032   PREFIX_VEX_0F3A17,
1033   PREFIX_VEX_0F3A18,
1034   PREFIX_VEX_0F3A19,
1035   PREFIX_VEX_0F3A1D,
1036   PREFIX_VEX_0F3A20,
1037   PREFIX_VEX_0F3A21,
1038   PREFIX_VEX_0F3A22,
1039   PREFIX_VEX_0F3A40,
1040   PREFIX_VEX_0F3A41,
1041   PREFIX_VEX_0F3A42,
1042   PREFIX_VEX_0F3A44,
1043   PREFIX_VEX_0F3A48,
1044   PREFIX_VEX_0F3A49,
1045   PREFIX_VEX_0F3A4A,
1046   PREFIX_VEX_0F3A4B,
1047   PREFIX_VEX_0F3A4C,
1048   PREFIX_VEX_0F3A5C,
1049   PREFIX_VEX_0F3A5D,
1050   PREFIX_VEX_0F3A5E,
1051   PREFIX_VEX_0F3A5F,
1052   PREFIX_VEX_0F3A60,
1053   PREFIX_VEX_0F3A61,
1054   PREFIX_VEX_0F3A62,
1055   PREFIX_VEX_0F3A63,
1056   PREFIX_VEX_0F3A68,
1057   PREFIX_VEX_0F3A69,
1058   PREFIX_VEX_0F3A6A,
1059   PREFIX_VEX_0F3A6B,
1060   PREFIX_VEX_0F3A6C,
1061   PREFIX_VEX_0F3A6D,
1062   PREFIX_VEX_0F3A6E,
1063   PREFIX_VEX_0F3A6F,
1064   PREFIX_VEX_0F3A78,
1065   PREFIX_VEX_0F3A79,
1066   PREFIX_VEX_0F3A7A,
1067   PREFIX_VEX_0F3A7B,
1068   PREFIX_VEX_0F3A7C,
1069   PREFIX_VEX_0F3A7D,
1070   PREFIX_VEX_0F3A7E,
1071   PREFIX_VEX_0F3A7F,
1072   PREFIX_VEX_0F3ADF
1073 };
1074
1075 enum
1076 {
1077   X86_64_06 = 0,
1078   X86_64_07,
1079   X86_64_0D,
1080   X86_64_16,
1081   X86_64_17,
1082   X86_64_1E,
1083   X86_64_1F,
1084   X86_64_27,
1085   X86_64_2F,
1086   X86_64_37,
1087   X86_64_3F,
1088   X86_64_60,
1089   X86_64_61,
1090   X86_64_62,
1091   X86_64_63,
1092   X86_64_6D,
1093   X86_64_6F,
1094   X86_64_9A,
1095   X86_64_C4,
1096   X86_64_C5,
1097   X86_64_CE,
1098   X86_64_D4,
1099   X86_64_D5,
1100   X86_64_EA,
1101   X86_64_0F01_REG_0,
1102   X86_64_0F01_REG_1,
1103   X86_64_0F01_REG_2,
1104   X86_64_0F01_REG_3
1105 };
1106
1107 enum
1108 {
1109   THREE_BYTE_0F38 = 0,
1110   THREE_BYTE_0F3A,
1111   THREE_BYTE_0F7A
1112 };
1113
1114 enum
1115 {
1116   XOP_08 = 0,
1117   XOP_09,
1118   XOP_0A
1119 };
1120
1121 enum
1122 {
1123   VEX_0F = 0,
1124   VEX_0F38,
1125   VEX_0F3A
1126 };
1127
1128 enum
1129 {
1130   VEX_LEN_0F10_P_1 = 0,
1131   VEX_LEN_0F10_P_3,
1132   VEX_LEN_0F11_P_1,
1133   VEX_LEN_0F11_P_3,
1134   VEX_LEN_0F12_P_0_M_0,
1135   VEX_LEN_0F12_P_0_M_1,
1136   VEX_LEN_0F12_P_2,
1137   VEX_LEN_0F13_M_0,
1138   VEX_LEN_0F16_P_0_M_0,
1139   VEX_LEN_0F16_P_0_M_1,
1140   VEX_LEN_0F16_P_2,
1141   VEX_LEN_0F17_M_0,
1142   VEX_LEN_0F2A_P_1,
1143   VEX_LEN_0F2A_P_3,
1144   VEX_LEN_0F2C_P_1,
1145   VEX_LEN_0F2C_P_3,
1146   VEX_LEN_0F2D_P_1,
1147   VEX_LEN_0F2D_P_3,
1148   VEX_LEN_0F2E_P_0,
1149   VEX_LEN_0F2E_P_2,
1150   VEX_LEN_0F2F_P_0,
1151   VEX_LEN_0F2F_P_2,
1152   VEX_LEN_0F51_P_1,
1153   VEX_LEN_0F51_P_3,
1154   VEX_LEN_0F52_P_1,
1155   VEX_LEN_0F53_P_1,
1156   VEX_LEN_0F58_P_1,
1157   VEX_LEN_0F58_P_3,
1158   VEX_LEN_0F59_P_1,
1159   VEX_LEN_0F59_P_3,
1160   VEX_LEN_0F5A_P_1,
1161   VEX_LEN_0F5A_P_3,
1162   VEX_LEN_0F5C_P_1,
1163   VEX_LEN_0F5C_P_3,
1164   VEX_LEN_0F5D_P_1,
1165   VEX_LEN_0F5D_P_3,
1166   VEX_LEN_0F5E_P_1,
1167   VEX_LEN_0F5E_P_3,
1168   VEX_LEN_0F5F_P_1,
1169   VEX_LEN_0F5F_P_3,
1170   VEX_LEN_0F60_P_2,
1171   VEX_LEN_0F61_P_2,
1172   VEX_LEN_0F62_P_2,
1173   VEX_LEN_0F63_P_2,
1174   VEX_LEN_0F64_P_2,
1175   VEX_LEN_0F65_P_2,
1176   VEX_LEN_0F66_P_2,
1177   VEX_LEN_0F67_P_2,
1178   VEX_LEN_0F68_P_2,
1179   VEX_LEN_0F69_P_2,
1180   VEX_LEN_0F6A_P_2,
1181   VEX_LEN_0F6B_P_2,
1182   VEX_LEN_0F6C_P_2,
1183   VEX_LEN_0F6D_P_2,
1184   VEX_LEN_0F6E_P_2,
1185   VEX_LEN_0F70_P_1,
1186   VEX_LEN_0F70_P_2,
1187   VEX_LEN_0F70_P_3,
1188   VEX_LEN_0F71_R_2_P_2,
1189   VEX_LEN_0F71_R_4_P_2,
1190   VEX_LEN_0F71_R_6_P_2,
1191   VEX_LEN_0F72_R_2_P_2,
1192   VEX_LEN_0F72_R_4_P_2,
1193   VEX_LEN_0F72_R_6_P_2,
1194   VEX_LEN_0F73_R_2_P_2,
1195   VEX_LEN_0F73_R_3_P_2,
1196   VEX_LEN_0F73_R_6_P_2,
1197   VEX_LEN_0F73_R_7_P_2,
1198   VEX_LEN_0F74_P_2,
1199   VEX_LEN_0F75_P_2,
1200   VEX_LEN_0F76_P_2,
1201   VEX_LEN_0F7E_P_1,
1202   VEX_LEN_0F7E_P_2,
1203   VEX_LEN_0FAE_R_2_M_0,
1204   VEX_LEN_0FAE_R_3_M_0,
1205   VEX_LEN_0FC2_P_1,
1206   VEX_LEN_0FC2_P_3,
1207   VEX_LEN_0FC4_P_2,
1208   VEX_LEN_0FC5_P_2,
1209   VEX_LEN_0FD1_P_2,
1210   VEX_LEN_0FD2_P_2,
1211   VEX_LEN_0FD3_P_2,
1212   VEX_LEN_0FD4_P_2,
1213   VEX_LEN_0FD5_P_2,
1214   VEX_LEN_0FD6_P_2,
1215   VEX_LEN_0FD7_P_2_M_1,
1216   VEX_LEN_0FD8_P_2,
1217   VEX_LEN_0FD9_P_2,
1218   VEX_LEN_0FDA_P_2,
1219   VEX_LEN_0FDB_P_2,
1220   VEX_LEN_0FDC_P_2,
1221   VEX_LEN_0FDD_P_2,
1222   VEX_LEN_0FDE_P_2,
1223   VEX_LEN_0FDF_P_2,
1224   VEX_LEN_0FE0_P_2,
1225   VEX_LEN_0FE1_P_2,
1226   VEX_LEN_0FE2_P_2,
1227   VEX_LEN_0FE3_P_2,
1228   VEX_LEN_0FE4_P_2,
1229   VEX_LEN_0FE5_P_2,
1230   VEX_LEN_0FE8_P_2,
1231   VEX_LEN_0FE9_P_2,
1232   VEX_LEN_0FEA_P_2,
1233   VEX_LEN_0FEB_P_2,
1234   VEX_LEN_0FEC_P_2,
1235   VEX_LEN_0FED_P_2,
1236   VEX_LEN_0FEE_P_2,
1237   VEX_LEN_0FEF_P_2,
1238   VEX_LEN_0FF1_P_2,
1239   VEX_LEN_0FF2_P_2,
1240   VEX_LEN_0FF3_P_2,
1241   VEX_LEN_0FF4_P_2,
1242   VEX_LEN_0FF5_P_2,
1243   VEX_LEN_0FF6_P_2,
1244   VEX_LEN_0FF7_P_2,
1245   VEX_LEN_0FF8_P_2,
1246   VEX_LEN_0FF9_P_2,
1247   VEX_LEN_0FFA_P_2,
1248   VEX_LEN_0FFB_P_2,
1249   VEX_LEN_0FFC_P_2,
1250   VEX_LEN_0FFD_P_2,
1251   VEX_LEN_0FFE_P_2,
1252   VEX_LEN_0F3800_P_2,
1253   VEX_LEN_0F3801_P_2,
1254   VEX_LEN_0F3802_P_2,
1255   VEX_LEN_0F3803_P_2,
1256   VEX_LEN_0F3804_P_2,
1257   VEX_LEN_0F3805_P_2,
1258   VEX_LEN_0F3806_P_2,
1259   VEX_LEN_0F3807_P_2,
1260   VEX_LEN_0F3808_P_2,
1261   VEX_LEN_0F3809_P_2,
1262   VEX_LEN_0F380A_P_2,
1263   VEX_LEN_0F380B_P_2,
1264   VEX_LEN_0F3819_P_2_M_0,
1265   VEX_LEN_0F381A_P_2_M_0,
1266   VEX_LEN_0F381C_P_2,
1267   VEX_LEN_0F381D_P_2,
1268   VEX_LEN_0F381E_P_2,
1269   VEX_LEN_0F3820_P_2,
1270   VEX_LEN_0F3821_P_2,
1271   VEX_LEN_0F3822_P_2,
1272   VEX_LEN_0F3823_P_2,
1273   VEX_LEN_0F3824_P_2,
1274   VEX_LEN_0F3825_P_2,
1275   VEX_LEN_0F3828_P_2,
1276   VEX_LEN_0F3829_P_2,
1277   VEX_LEN_0F382A_P_2_M_0,
1278   VEX_LEN_0F382B_P_2,
1279   VEX_LEN_0F3830_P_2,
1280   VEX_LEN_0F3831_P_2,
1281   VEX_LEN_0F3832_P_2,
1282   VEX_LEN_0F3833_P_2,
1283   VEX_LEN_0F3834_P_2,
1284   VEX_LEN_0F3835_P_2,
1285   VEX_LEN_0F3837_P_2,
1286   VEX_LEN_0F3838_P_2,
1287   VEX_LEN_0F3839_P_2,
1288   VEX_LEN_0F383A_P_2,
1289   VEX_LEN_0F383B_P_2,
1290   VEX_LEN_0F383C_P_2,
1291   VEX_LEN_0F383D_P_2,
1292   VEX_LEN_0F383E_P_2,
1293   VEX_LEN_0F383F_P_2,
1294   VEX_LEN_0F3840_P_2,
1295   VEX_LEN_0F3841_P_2,
1296   VEX_LEN_0F38DB_P_2,
1297   VEX_LEN_0F38DC_P_2,
1298   VEX_LEN_0F38DD_P_2,
1299   VEX_LEN_0F38DE_P_2,
1300   VEX_LEN_0F38DF_P_2,
1301   VEX_LEN_0F3A06_P_2,
1302   VEX_LEN_0F3A0A_P_2,
1303   VEX_LEN_0F3A0B_P_2,
1304   VEX_LEN_0F3A0E_P_2,
1305   VEX_LEN_0F3A0F_P_2,
1306   VEX_LEN_0F3A14_P_2,
1307   VEX_LEN_0F3A15_P_2,
1308   VEX_LEN_0F3A16_P_2,
1309   VEX_LEN_0F3A17_P_2,
1310   VEX_LEN_0F3A18_P_2,
1311   VEX_LEN_0F3A19_P_2,
1312   VEX_LEN_0F3A20_P_2,
1313   VEX_LEN_0F3A21_P_2,
1314   VEX_LEN_0F3A22_P_2,
1315   VEX_LEN_0F3A41_P_2,
1316   VEX_LEN_0F3A42_P_2,
1317   VEX_LEN_0F3A44_P_2,
1318   VEX_LEN_0F3A4C_P_2,
1319   VEX_LEN_0F3A60_P_2,
1320   VEX_LEN_0F3A61_P_2,
1321   VEX_LEN_0F3A62_P_2,
1322   VEX_LEN_0F3A63_P_2,
1323   VEX_LEN_0F3A6A_P_2,
1324   VEX_LEN_0F3A6B_P_2,
1325   VEX_LEN_0F3A6E_P_2,
1326   VEX_LEN_0F3A6F_P_2,
1327   VEX_LEN_0F3A7A_P_2,
1328   VEX_LEN_0F3A7B_P_2,
1329   VEX_LEN_0F3A7E_P_2,
1330   VEX_LEN_0F3A7F_P_2,
1331   VEX_LEN_0F3ADF_P_2,
1332   VEX_LEN_0FXOP_09_80,
1333   VEX_LEN_0FXOP_09_81
1334 };
1335
1336 enum
1337 {
1338   VEX_W_0F10_P_0 = 0,
1339   VEX_W_0F10_P_1,
1340   VEX_W_0F10_P_2,
1341   VEX_W_0F10_P_3,
1342   VEX_W_0F11_P_0,
1343   VEX_W_0F11_P_1,
1344   VEX_W_0F11_P_2,
1345   VEX_W_0F11_P_3,
1346   VEX_W_0F12_P_0_M_0,
1347   VEX_W_0F12_P_0_M_1,
1348   VEX_W_0F12_P_1,
1349   VEX_W_0F12_P_2,
1350   VEX_W_0F12_P_3,
1351   VEX_W_0F13_M_0,
1352   VEX_W_0F14,
1353   VEX_W_0F15,
1354   VEX_W_0F16_P_0_M_0,
1355   VEX_W_0F16_P_0_M_1,
1356   VEX_W_0F16_P_1,
1357   VEX_W_0F16_P_2,
1358   VEX_W_0F17_M_0,
1359   VEX_W_0F28,
1360   VEX_W_0F29,
1361   VEX_W_0F2B_M_0,
1362   VEX_W_0F2E_P_0,
1363   VEX_W_0F2E_P_2,
1364   VEX_W_0F2F_P_0,
1365   VEX_W_0F2F_P_2,
1366   VEX_W_0F50_M_0,
1367   VEX_W_0F51_P_0,
1368   VEX_W_0F51_P_1,
1369   VEX_W_0F51_P_2,
1370   VEX_W_0F51_P_3,
1371   VEX_W_0F52_P_0,
1372   VEX_W_0F52_P_1,
1373   VEX_W_0F53_P_0,
1374   VEX_W_0F53_P_1,
1375   VEX_W_0F58_P_0,
1376   VEX_W_0F58_P_1,
1377   VEX_W_0F58_P_2,
1378   VEX_W_0F58_P_3,
1379   VEX_W_0F59_P_0,
1380   VEX_W_0F59_P_1,
1381   VEX_W_0F59_P_2,
1382   VEX_W_0F59_P_3,
1383   VEX_W_0F5A_P_0,
1384   VEX_W_0F5A_P_1,
1385   VEX_W_0F5A_P_3,
1386   VEX_W_0F5B_P_0,
1387   VEX_W_0F5B_P_1,
1388   VEX_W_0F5B_P_2,
1389   VEX_W_0F5C_P_0,
1390   VEX_W_0F5C_P_1,
1391   VEX_W_0F5C_P_2,
1392   VEX_W_0F5C_P_3,
1393   VEX_W_0F5D_P_0,
1394   VEX_W_0F5D_P_1,
1395   VEX_W_0F5D_P_2,
1396   VEX_W_0F5D_P_3,
1397   VEX_W_0F5E_P_0,
1398   VEX_W_0F5E_P_1,
1399   VEX_W_0F5E_P_2,
1400   VEX_W_0F5E_P_3,
1401   VEX_W_0F5F_P_0,
1402   VEX_W_0F5F_P_1,
1403   VEX_W_0F5F_P_2,
1404   VEX_W_0F5F_P_3,
1405   VEX_W_0F60_P_2,
1406   VEX_W_0F61_P_2,
1407   VEX_W_0F62_P_2,
1408   VEX_W_0F63_P_2,
1409   VEX_W_0F64_P_2,
1410   VEX_W_0F65_P_2,
1411   VEX_W_0F66_P_2,
1412   VEX_W_0F67_P_2,
1413   VEX_W_0F68_P_2,
1414   VEX_W_0F69_P_2,
1415   VEX_W_0F6A_P_2,
1416   VEX_W_0F6B_P_2,
1417   VEX_W_0F6C_P_2,
1418   VEX_W_0F6D_P_2,
1419   VEX_W_0F6F_P_1,
1420   VEX_W_0F6F_P_2,
1421   VEX_W_0F70_P_1,
1422   VEX_W_0F70_P_2,
1423   VEX_W_0F70_P_3,
1424   VEX_W_0F71_R_2_P_2,
1425   VEX_W_0F71_R_4_P_2,
1426   VEX_W_0F71_R_6_P_2,
1427   VEX_W_0F72_R_2_P_2,
1428   VEX_W_0F72_R_4_P_2,
1429   VEX_W_0F72_R_6_P_2,
1430   VEX_W_0F73_R_2_P_2,
1431   VEX_W_0F73_R_3_P_2,
1432   VEX_W_0F73_R_6_P_2,
1433   VEX_W_0F73_R_7_P_2,
1434   VEX_W_0F74_P_2,
1435   VEX_W_0F75_P_2,
1436   VEX_W_0F76_P_2,
1437   VEX_W_0F77_P_0,
1438   VEX_W_0F7C_P_2,
1439   VEX_W_0F7C_P_3,
1440   VEX_W_0F7D_P_2,
1441   VEX_W_0F7D_P_3,
1442   VEX_W_0F7E_P_1,
1443   VEX_W_0F7F_P_1,
1444   VEX_W_0F7F_P_2,
1445   VEX_W_0FAE_R_2_M_0,
1446   VEX_W_0FAE_R_3_M_0,
1447   VEX_W_0FC2_P_0,
1448   VEX_W_0FC2_P_1,
1449   VEX_W_0FC2_P_2,
1450   VEX_W_0FC2_P_3,
1451   VEX_W_0FC4_P_2,
1452   VEX_W_0FC5_P_2,
1453   VEX_W_0FD0_P_2,
1454   VEX_W_0FD0_P_3,
1455   VEX_W_0FD1_P_2,
1456   VEX_W_0FD2_P_2,
1457   VEX_W_0FD3_P_2,
1458   VEX_W_0FD4_P_2,
1459   VEX_W_0FD5_P_2,
1460   VEX_W_0FD6_P_2,
1461   VEX_W_0FD7_P_2_M_1,
1462   VEX_W_0FD8_P_2,
1463   VEX_W_0FD9_P_2,
1464   VEX_W_0FDA_P_2,
1465   VEX_W_0FDB_P_2,
1466   VEX_W_0FDC_P_2,
1467   VEX_W_0FDD_P_2,
1468   VEX_W_0FDE_P_2,
1469   VEX_W_0FDF_P_2,
1470   VEX_W_0FE0_P_2,
1471   VEX_W_0FE1_P_2,
1472   VEX_W_0FE2_P_2,
1473   VEX_W_0FE3_P_2,
1474   VEX_W_0FE4_P_2,
1475   VEX_W_0FE5_P_2,
1476   VEX_W_0FE6_P_1,
1477   VEX_W_0FE6_P_2,
1478   VEX_W_0FE6_P_3,
1479   VEX_W_0FE7_P_2_M_0,
1480   VEX_W_0FE8_P_2,
1481   VEX_W_0FE9_P_2,
1482   VEX_W_0FEA_P_2,
1483   VEX_W_0FEB_P_2,
1484   VEX_W_0FEC_P_2,
1485   VEX_W_0FED_P_2,
1486   VEX_W_0FEE_P_2,
1487   VEX_W_0FEF_P_2,
1488   VEX_W_0FF0_P_3_M_0,
1489   VEX_W_0FF1_P_2,
1490   VEX_W_0FF2_P_2,
1491   VEX_W_0FF3_P_2,
1492   VEX_W_0FF4_P_2,
1493   VEX_W_0FF5_P_2,
1494   VEX_W_0FF6_P_2,
1495   VEX_W_0FF7_P_2,
1496   VEX_W_0FF8_P_2,
1497   VEX_W_0FF9_P_2,
1498   VEX_W_0FFA_P_2,
1499   VEX_W_0FFB_P_2,
1500   VEX_W_0FFC_P_2,
1501   VEX_W_0FFD_P_2,
1502   VEX_W_0FFE_P_2,
1503   VEX_W_0F3800_P_2,
1504   VEX_W_0F3801_P_2,
1505   VEX_W_0F3802_P_2,
1506   VEX_W_0F3803_P_2,
1507   VEX_W_0F3804_P_2,
1508   VEX_W_0F3805_P_2,
1509   VEX_W_0F3806_P_2,
1510   VEX_W_0F3807_P_2,
1511   VEX_W_0F3808_P_2,
1512   VEX_W_0F3809_P_2,
1513   VEX_W_0F380A_P_2,
1514   VEX_W_0F380B_P_2,
1515   VEX_W_0F380C_P_2,
1516   VEX_W_0F380D_P_2,
1517   VEX_W_0F380E_P_2,
1518   VEX_W_0F380F_P_2,
1519   VEX_W_0F3817_P_2,
1520   VEX_W_0F3818_P_2_M_0,
1521   VEX_W_0F3819_P_2_M_0,
1522   VEX_W_0F381A_P_2_M_0,
1523   VEX_W_0F381C_P_2,
1524   VEX_W_0F381D_P_2,
1525   VEX_W_0F381E_P_2,
1526   VEX_W_0F3820_P_2,
1527   VEX_W_0F3821_P_2,
1528   VEX_W_0F3822_P_2,
1529   VEX_W_0F3823_P_2,
1530   VEX_W_0F3824_P_2,
1531   VEX_W_0F3825_P_2,
1532   VEX_W_0F3828_P_2,
1533   VEX_W_0F3829_P_2,
1534   VEX_W_0F382A_P_2_M_0,
1535   VEX_W_0F382B_P_2,
1536   VEX_W_0F382C_P_2_M_0,
1537   VEX_W_0F382D_P_2_M_0,
1538   VEX_W_0F382E_P_2_M_0,
1539   VEX_W_0F382F_P_2_M_0,
1540   VEX_W_0F3830_P_2,
1541   VEX_W_0F3831_P_2,
1542   VEX_W_0F3832_P_2,
1543   VEX_W_0F3833_P_2,
1544   VEX_W_0F3834_P_2,
1545   VEX_W_0F3835_P_2,
1546   VEX_W_0F3837_P_2,
1547   VEX_W_0F3838_P_2,
1548   VEX_W_0F3839_P_2,
1549   VEX_W_0F383A_P_2,
1550   VEX_W_0F383B_P_2,
1551   VEX_W_0F383C_P_2,
1552   VEX_W_0F383D_P_2,
1553   VEX_W_0F383E_P_2,
1554   VEX_W_0F383F_P_2,
1555   VEX_W_0F3840_P_2,
1556   VEX_W_0F3841_P_2,
1557   VEX_W_0F38DB_P_2,
1558   VEX_W_0F38DC_P_2,
1559   VEX_W_0F38DD_P_2,
1560   VEX_W_0F38DE_P_2,
1561   VEX_W_0F38DF_P_2,
1562   VEX_W_0F3A04_P_2,
1563   VEX_W_0F3A05_P_2,
1564   VEX_W_0F3A06_P_2,
1565   VEX_W_0F3A08_P_2,
1566   VEX_W_0F3A09_P_2,
1567   VEX_W_0F3A0A_P_2,
1568   VEX_W_0F3A0B_P_2,
1569   VEX_W_0F3A0C_P_2,
1570   VEX_W_0F3A0D_P_2,
1571   VEX_W_0F3A0E_P_2,
1572   VEX_W_0F3A0F_P_2,
1573   VEX_W_0F3A14_P_2,
1574   VEX_W_0F3A15_P_2,
1575   VEX_W_0F3A18_P_2,
1576   VEX_W_0F3A19_P_2,
1577   VEX_W_0F3A20_P_2,
1578   VEX_W_0F3A21_P_2,
1579   VEX_W_0F3A40_P_2,
1580   VEX_W_0F3A41_P_2,
1581   VEX_W_0F3A42_P_2,
1582   VEX_W_0F3A44_P_2,
1583   VEX_W_0F3A48_P_2,
1584   VEX_W_0F3A49_P_2,
1585   VEX_W_0F3A4A_P_2,
1586   VEX_W_0F3A4B_P_2,
1587   VEX_W_0F3A4C_P_2,
1588   VEX_W_0F3A60_P_2,
1589   VEX_W_0F3A61_P_2,
1590   VEX_W_0F3A62_P_2,
1591   VEX_W_0F3A63_P_2,
1592   VEX_W_0F3ADF_P_2
1593 };
1594
1595 typedef void (*op_rtn) (int bytemode, int sizeflag);
1596
1597 struct dis386 {
1598   const char *name;
1599   struct
1600     {
1601       op_rtn rtn;
1602       int bytemode;
1603     } op[MAX_OPERANDS];
1604 };
1605
1606 /* Upper case letters in the instruction names here are macros.
1607    'A' => print 'b' if no register operands or suffix_always is true
1608    'B' => print 'b' if suffix_always is true
1609    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1610           size prefix
1611    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1612           suffix_always is true
1613    'E' => print 'e' if 32-bit form of jcxz
1614    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1615    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1616    'H' => print ",pt" or ",pn" branch hint
1617    'I' => honor following macro letter even in Intel mode (implemented only
1618           for some of the macro letters)
1619    'J' => print 'l'
1620    'K' => print 'd' or 'q' if rex prefix is present.
1621    'L' => print 'l' if suffix_always is true
1622    'M' => print 'r' if intel_mnemonic is false.
1623    'N' => print 'n' if instruction has no wait "prefix"
1624    'O' => print 'd' or 'o' (or 'q' in Intel mode)
1625    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
1626           or suffix_always is true.  print 'q' if rex prefix is present.
1627    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1628           is true
1629    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1630    'S' => print 'w', 'l' or 'q' if suffix_always is true
1631    'T' => print 'q' in 64bit mode and behave as 'P' otherwise
1632    'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
1633    'V' => print 'q' in 64bit mode and behave as 'S' otherwise
1634    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1635    'X' => print 's', 'd' depending on data16 prefix (for XMM)
1636    'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
1637           suffix_always is true.
1638    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
1639    '!' => change condition from true to false or from false to true.
1640    '%' => add 1 upper case letter to the macro.
1641
1642    2 upper case letter macros:
1643    "XY" => print 'x' or 'y' if no register operands or suffix_always
1644            is true.
1645    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1646    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
1647            or suffix_always is true
1648    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1649    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1650    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1651
1652    Many of the above letters print nothing in Intel mode.  See "putop"
1653    for the details.
1654
1655    Braces '{' and '}', and vertical bars '|', indicate alternative
1656    mnemonic strings for AT&T and Intel.  */
1657
1658 static const struct dis386 dis386[] = {
1659   /* 00 */
1660   { "addB",             { Eb, Gb } },
1661   { "addS",             { Ev, Gv } },
1662   { "addB",             { Gb, EbS } },
1663   { "addS",             { Gv, EvS } },
1664   { "addB",             { AL, Ib } },
1665   { "addS",             { eAX, Iv } },
1666   { X86_64_TABLE (X86_64_06) },
1667   { X86_64_TABLE (X86_64_07) },
1668   /* 08 */
1669   { "orB",              { Eb, Gb } },
1670   { "orS",              { Ev, Gv } },
1671   { "orB",              { Gb, EbS } },
1672   { "orS",              { Gv, EvS } },
1673   { "orB",              { AL, Ib } },
1674   { "orS",              { eAX, Iv } },
1675   { X86_64_TABLE (X86_64_0D) },
1676   { Bad_Opcode },       /* 0x0f extended opcode escape */
1677   /* 10 */
1678   { "adcB",             { Eb, Gb } },
1679   { "adcS",             { Ev, Gv } },
1680   { "adcB",             { Gb, EbS } },
1681   { "adcS",             { Gv, EvS } },
1682   { "adcB",             { AL, Ib } },
1683   { "adcS",             { eAX, Iv } },
1684   { X86_64_TABLE (X86_64_16) },
1685   { X86_64_TABLE (X86_64_17) },
1686   /* 18 */
1687   { "sbbB",             { Eb, Gb } },
1688   { "sbbS",             { Ev, Gv } },
1689   { "sbbB",             { Gb, EbS } },
1690   { "sbbS",             { Gv, EvS } },
1691   { "sbbB",             { AL, Ib } },
1692   { "sbbS",             { eAX, Iv } },
1693   { X86_64_TABLE (X86_64_1E) },
1694   { X86_64_TABLE (X86_64_1F) },
1695   /* 20 */
1696   { "andB",             { Eb, Gb } },
1697   { "andS",             { Ev, Gv } },
1698   { "andB",             { Gb, EbS } },
1699   { "andS",             { Gv, EvS } },
1700   { "andB",             { AL, Ib } },
1701   { "andS",             { eAX, Iv } },
1702   { Bad_Opcode },       /* SEG ES prefix */
1703   { X86_64_TABLE (X86_64_27) },
1704   /* 28 */
1705   { "subB",             { Eb, Gb } },
1706   { "subS",             { Ev, Gv } },
1707   { "subB",             { Gb, EbS } },
1708   { "subS",             { Gv, EvS } },
1709   { "subB",             { AL, Ib } },
1710   { "subS",             { eAX, Iv } },
1711   { Bad_Opcode },       /* SEG CS prefix */
1712   { X86_64_TABLE (X86_64_2F) },
1713   /* 30 */
1714   { "xorB",             { Eb, Gb } },
1715   { "xorS",             { Ev, Gv } },
1716   { "xorB",             { Gb, EbS } },
1717   { "xorS",             { Gv, EvS } },
1718   { "xorB",             { AL, Ib } },
1719   { "xorS",             { eAX, Iv } },
1720   { Bad_Opcode },       /* SEG SS prefix */
1721   { X86_64_TABLE (X86_64_37) },
1722   /* 38 */
1723   { "cmpB",             { Eb, Gb } },
1724   { "cmpS",             { Ev, Gv } },
1725   { "cmpB",             { Gb, EbS } },
1726   { "cmpS",             { Gv, EvS } },
1727   { "cmpB",             { AL, Ib } },
1728   { "cmpS",             { eAX, Iv } },
1729   { Bad_Opcode },       /* SEG DS prefix */
1730   { X86_64_TABLE (X86_64_3F) },
1731   /* 40 */
1732   { "inc{S|}",          { RMeAX } },
1733   { "inc{S|}",          { RMeCX } },
1734   { "inc{S|}",          { RMeDX } },
1735   { "inc{S|}",          { RMeBX } },
1736   { "inc{S|}",          { RMeSP } },
1737   { "inc{S|}",          { RMeBP } },
1738   { "inc{S|}",          { RMeSI } },
1739   { "inc{S|}",          { RMeDI } },
1740   /* 48 */
1741   { "dec{S|}",          { RMeAX } },
1742   { "dec{S|}",          { RMeCX } },
1743   { "dec{S|}",          { RMeDX } },
1744   { "dec{S|}",          { RMeBX } },
1745   { "dec{S|}",          { RMeSP } },
1746   { "dec{S|}",          { RMeBP } },
1747   { "dec{S|}",          { RMeSI } },
1748   { "dec{S|}",          { RMeDI } },
1749   /* 50 */
1750   { "pushV",            { RMrAX } },
1751   { "pushV",            { RMrCX } },
1752   { "pushV",            { RMrDX } },
1753   { "pushV",            { RMrBX } },
1754   { "pushV",            { RMrSP } },
1755   { "pushV",            { RMrBP } },
1756   { "pushV",            { RMrSI } },
1757   { "pushV",            { RMrDI } },
1758   /* 58 */
1759   { "popV",             { RMrAX } },
1760   { "popV",             { RMrCX } },
1761   { "popV",             { RMrDX } },
1762   { "popV",             { RMrBX } },
1763   { "popV",             { RMrSP } },
1764   { "popV",             { RMrBP } },
1765   { "popV",             { RMrSI } },
1766   { "popV",             { RMrDI } },
1767   /* 60 */
1768   { X86_64_TABLE (X86_64_60) },
1769   { X86_64_TABLE (X86_64_61) },
1770   { X86_64_TABLE (X86_64_62) },
1771   { X86_64_TABLE (X86_64_63) },
1772   { Bad_Opcode },       /* seg fs */
1773   { Bad_Opcode },       /* seg gs */
1774   { Bad_Opcode },       /* op size prefix */
1775   { Bad_Opcode },       /* adr size prefix */
1776   /* 68 */
1777   { "pushT",            { sIv } },
1778   { "imulS",            { Gv, Ev, Iv } },
1779   { "pushT",            { sIb } },
1780   { "imulS",            { Gv, Ev, sIb } },
1781   { "ins{b|}",          { Ybr, indirDX } },
1782   { X86_64_TABLE (X86_64_6D) },
1783   { "outs{b|}",         { indirDXr, Xb } },
1784   { X86_64_TABLE (X86_64_6F) },
1785   /* 70 */
1786   { "joH",              { Jb, XX, cond_jump_flag } },
1787   { "jnoH",             { Jb, XX, cond_jump_flag } },
1788   { "jbH",              { Jb, XX, cond_jump_flag } },
1789   { "jaeH",             { Jb, XX, cond_jump_flag } },
1790   { "jeH",              { Jb, XX, cond_jump_flag } },
1791   { "jneH",             { Jb, XX, cond_jump_flag } },
1792   { "jbeH",             { Jb, XX, cond_jump_flag } },
1793   { "jaH",              { Jb, XX, cond_jump_flag } },
1794   /* 78 */
1795   { "jsH",              { Jb, XX, cond_jump_flag } },
1796   { "jnsH",             { Jb, XX, cond_jump_flag } },
1797   { "jpH",              { Jb, XX, cond_jump_flag } },
1798   { "jnpH",             { Jb, XX, cond_jump_flag } },
1799   { "jlH",              { Jb, XX, cond_jump_flag } },
1800   { "jgeH",             { Jb, XX, cond_jump_flag } },
1801   { "jleH",             { Jb, XX, cond_jump_flag } },
1802   { "jgH",              { Jb, XX, cond_jump_flag } },
1803   /* 80 */
1804   { REG_TABLE (REG_80) },
1805   { REG_TABLE (REG_81) },
1806   { Bad_Opcode },
1807   { REG_TABLE (REG_82) },
1808   { "testB",            { Eb, Gb } },
1809   { "testS",            { Ev, Gv } },
1810   { "xchgB",            { Eb, Gb } },
1811   { "xchgS",            { Ev, Gv } },
1812   /* 88 */
1813   { "movB",             { Eb, Gb } },
1814   { "movS",             { Ev, Gv } },
1815   { "movB",             { Gb, EbS } },
1816   { "movS",             { Gv, EvS } },
1817   { "movD",             { Sv, Sw } },
1818   { MOD_TABLE (MOD_8D) },
1819   { "movD",             { Sw, Sv } },
1820   { REG_TABLE (REG_8F) },
1821   /* 90 */
1822   { PREFIX_TABLE (PREFIX_90) },
1823   { "xchgS",            { RMeCX, eAX } },
1824   { "xchgS",            { RMeDX, eAX } },
1825   { "xchgS",            { RMeBX, eAX } },
1826   { "xchgS",            { RMeSP, eAX } },
1827   { "xchgS",            { RMeBP, eAX } },
1828   { "xchgS",            { RMeSI, eAX } },
1829   { "xchgS",            { RMeDI, eAX } },
1830   /* 98 */
1831   { "cW{t|}R",          { XX } },
1832   { "cR{t|}O",          { XX } },
1833   { X86_64_TABLE (X86_64_9A) },
1834   { Bad_Opcode },       /* fwait */
1835   { "pushfT",           { XX } },
1836   { "popfT",            { XX } },
1837   { "sahf",             { XX } },
1838   { "lahf",             { XX } },
1839   /* a0 */
1840   { "mov%LB",           { AL, Ob } },
1841   { "mov%LS",           { eAX, Ov } },
1842   { "mov%LB",           { Ob, AL } },
1843   { "mov%LS",           { Ov, eAX } },
1844   { "movs{b|}",         { Ybr, Xb } },
1845   { "movs{R|}",         { Yvr, Xv } },
1846   { "cmps{b|}",         { Xb, Yb } },
1847   { "cmps{R|}",         { Xv, Yv } },
1848   /* a8 */
1849   { "testB",            { AL, Ib } },
1850   { "testS",            { eAX, Iv } },
1851   { "stosB",            { Ybr, AL } },
1852   { "stosS",            { Yvr, eAX } },
1853   { "lodsB",            { ALr, Xb } },
1854   { "lodsS",            { eAXr, Xv } },
1855   { "scasB",            { AL, Yb } },
1856   { "scasS",            { eAX, Yv } },
1857   /* b0 */
1858   { "movB",             { RMAL, Ib } },
1859   { "movB",             { RMCL, Ib } },
1860   { "movB",             { RMDL, Ib } },
1861   { "movB",             { RMBL, Ib } },
1862   { "movB",             { RMAH, Ib } },
1863   { "movB",             { RMCH, Ib } },
1864   { "movB",             { RMDH, Ib } },
1865   { "movB",             { RMBH, Ib } },
1866   /* b8 */
1867   { "mov%LV",           { RMeAX, Iv64 } },
1868   { "mov%LV",           { RMeCX, Iv64 } },
1869   { "mov%LV",           { RMeDX, Iv64 } },
1870   { "mov%LV",           { RMeBX, Iv64 } },
1871   { "mov%LV",           { RMeSP, Iv64 } },
1872   { "mov%LV",           { RMeBP, Iv64 } },
1873   { "mov%LV",           { RMeSI, Iv64 } },
1874   { "mov%LV",           { RMeDI, Iv64 } },
1875   /* c0 */
1876   { REG_TABLE (REG_C0) },
1877   { REG_TABLE (REG_C1) },
1878   { "retT",             { Iw } },
1879   { "retT",             { XX } },
1880   { X86_64_TABLE (X86_64_C4) },
1881   { X86_64_TABLE (X86_64_C5) },
1882   { REG_TABLE (REG_C6) },
1883   { REG_TABLE (REG_C7) },
1884   /* c8 */
1885   { "enterT",           { Iw, Ib } },
1886   { "leaveT",           { XX } },
1887   { "Jret{|f}P",        { Iw } },
1888   { "Jret{|f}P",        { XX } },
1889   { "int3",             { XX } },
1890   { "int",              { Ib } },
1891   { X86_64_TABLE (X86_64_CE) },
1892   { "iretP",            { XX } },
1893   /* d0 */
1894   { REG_TABLE (REG_D0) },
1895   { REG_TABLE (REG_D1) },
1896   { REG_TABLE (REG_D2) },
1897   { REG_TABLE (REG_D3) },
1898   { X86_64_TABLE (X86_64_D4) },
1899   { X86_64_TABLE (X86_64_D5) },
1900   { Bad_Opcode },
1901   { "xlat",             { DSBX } },
1902   /* d8 */
1903   { FLOAT },
1904   { FLOAT },
1905   { FLOAT },
1906   { FLOAT },
1907   { FLOAT },
1908   { FLOAT },
1909   { FLOAT },
1910   { FLOAT },
1911   /* e0 */
1912   { "loopneFH",         { Jb, XX, loop_jcxz_flag } },
1913   { "loopeFH",          { Jb, XX, loop_jcxz_flag } },
1914   { "loopFH",           { Jb, XX, loop_jcxz_flag } },
1915   { "jEcxzH",           { Jb, XX, loop_jcxz_flag } },
1916   { "inB",              { AL, Ib } },
1917   { "inG",              { zAX, Ib } },
1918   { "outB",             { Ib, AL } },
1919   { "outG",             { Ib, zAX } },
1920   /* e8 */
1921   { "callT",            { Jv } },
1922   { "jmpT",             { Jv } },
1923   { X86_64_TABLE (X86_64_EA) },
1924   { "jmp",              { Jb } },
1925   { "inB",              { AL, indirDX } },
1926   { "inG",              { zAX, indirDX } },
1927   { "outB",             { indirDX, AL } },
1928   { "outG",             { indirDX, zAX } },
1929   /* f0 */
1930   { Bad_Opcode },       /* lock prefix */
1931   { "icebp",            { XX } },
1932   { Bad_Opcode },       /* repne */
1933   { Bad_Opcode },       /* repz */
1934   { "hlt",              { XX } },
1935   { "cmc",              { XX } },
1936   { REG_TABLE (REG_F6) },
1937   { REG_TABLE (REG_F7) },
1938   /* f8 */
1939   { "clc",              { XX } },
1940   { "stc",              { XX } },
1941   { "cli",              { XX } },
1942   { "sti",              { XX } },
1943   { "cld",              { XX } },
1944   { "std",              { XX } },
1945   { REG_TABLE (REG_FE) },
1946   { REG_TABLE (REG_FF) },
1947 };
1948
1949 static const struct dis386 dis386_twobyte[] = {
1950   /* 00 */
1951   { REG_TABLE (REG_0F00 ) },
1952   { REG_TABLE (REG_0F01 ) },
1953   { "larS",             { Gv, Ew } },
1954   { "lslS",             { Gv, Ew } },
1955   { Bad_Opcode },
1956   { "syscall",          { XX } },
1957   { "clts",             { XX } },
1958   { "sysretP",          { XX } },
1959   /* 08 */
1960   { "invd",             { XX } },
1961   { "wbinvd",           { XX } },
1962   { Bad_Opcode },
1963   { "ud2",              { XX } },
1964   { Bad_Opcode },
1965   { REG_TABLE (REG_0F0D) },
1966   { "femms",            { XX } },
1967   { "",                 { MX, EM, OPSUF } }, /* See OP_3DNowSuffix.  */
1968   /* 10 */
1969   { PREFIX_TABLE (PREFIX_0F10) },
1970   { PREFIX_TABLE (PREFIX_0F11) },
1971   { PREFIX_TABLE (PREFIX_0F12) },
1972   { MOD_TABLE (MOD_0F13) },
1973   { "unpcklpX",         { XM, EXx } },
1974   { "unpckhpX",         { XM, EXx } },
1975   { PREFIX_TABLE (PREFIX_0F16) },
1976   { MOD_TABLE (MOD_0F17) },
1977   /* 18 */
1978   { REG_TABLE (REG_0F18) },
1979   { "nopQ",             { Ev } },
1980   { "nopQ",             { Ev } },
1981   { "nopQ",             { Ev } },
1982   { "nopQ",             { Ev } },
1983   { "nopQ",             { Ev } },
1984   { "nopQ",             { Ev } },
1985   { "nopQ",             { Ev } },
1986   /* 20 */
1987   { MOD_TABLE (MOD_0F20) },
1988   { MOD_TABLE (MOD_0F21) },
1989   { MOD_TABLE (MOD_0F22) },
1990   { MOD_TABLE (MOD_0F23) },
1991   { MOD_TABLE (MOD_0F24) },
1992   { Bad_Opcode },
1993   { MOD_TABLE (MOD_0F26) },
1994   { Bad_Opcode },
1995   /* 28 */
1996   { "movapX",           { XM, EXx } },
1997   { "movapX",           { EXxS, XM } },
1998   { PREFIX_TABLE (PREFIX_0F2A) },
1999   { PREFIX_TABLE (PREFIX_0F2B) },
2000   { PREFIX_TABLE (PREFIX_0F2C) },
2001   { PREFIX_TABLE (PREFIX_0F2D) },
2002   { PREFIX_TABLE (PREFIX_0F2E) },
2003   { PREFIX_TABLE (PREFIX_0F2F) },
2004   /* 30 */
2005   { "wrmsr",            { XX } },
2006   { "rdtsc",            { XX } },
2007   { "rdmsr",            { XX } },
2008   { "rdpmc",            { XX } },
2009   { "sysenter",         { XX } },
2010   { "sysexit",          { XX } },
2011   { Bad_Opcode },
2012   { "getsec",           { XX } },
2013   /* 38 */
2014   { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
2015   { Bad_Opcode },
2016   { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
2017   { Bad_Opcode },
2018   { Bad_Opcode },
2019   { Bad_Opcode },
2020   { Bad_Opcode },
2021   { Bad_Opcode },
2022   /* 40 */
2023   { "cmovoS",           { Gv, Ev } },
2024   { "cmovnoS",          { Gv, Ev } },
2025   { "cmovbS",           { Gv, Ev } },
2026   { "cmovaeS",          { Gv, Ev } },
2027   { "cmoveS",           { Gv, Ev } },
2028   { "cmovneS",          { Gv, Ev } },
2029   { "cmovbeS",          { Gv, Ev } },
2030   { "cmovaS",           { Gv, Ev } },
2031   /* 48 */
2032   { "cmovsS",           { Gv, Ev } },
2033   { "cmovnsS",          { Gv, Ev } },
2034   { "cmovpS",           { Gv, Ev } },
2035   { "cmovnpS",          { Gv, Ev } },
2036   { "cmovlS",           { Gv, Ev } },
2037   { "cmovgeS",          { Gv, Ev } },
2038   { "cmovleS",          { Gv, Ev } },
2039   { "cmovgS",           { Gv, Ev } },
2040   /* 50 */
2041   { MOD_TABLE (MOD_0F51) },
2042   { PREFIX_TABLE (PREFIX_0F51) },
2043   { PREFIX_TABLE (PREFIX_0F52) },
2044   { PREFIX_TABLE (PREFIX_0F53) },
2045   { "andpX",            { XM, EXx } },
2046   { "andnpX",           { XM, EXx } },
2047   { "orpX",             { XM, EXx } },
2048   { "xorpX",            { XM, EXx } },
2049   /* 58 */
2050   { PREFIX_TABLE (PREFIX_0F58) },
2051   { PREFIX_TABLE (PREFIX_0F59) },
2052   { PREFIX_TABLE (PREFIX_0F5A) },
2053   { PREFIX_TABLE (PREFIX_0F5B) },
2054   { PREFIX_TABLE (PREFIX_0F5C) },
2055   { PREFIX_TABLE (PREFIX_0F5D) },
2056   { PREFIX_TABLE (PREFIX_0F5E) },
2057   { PREFIX_TABLE (PREFIX_0F5F) },
2058   /* 60 */
2059   { PREFIX_TABLE (PREFIX_0F60) },
2060   { PREFIX_TABLE (PREFIX_0F61) },
2061   { PREFIX_TABLE (PREFIX_0F62) },
2062   { "packsswb",         { MX, EM } },
2063   { "pcmpgtb",          { MX, EM } },
2064   { "pcmpgtw",          { MX, EM } },
2065   { "pcmpgtd",          { MX, EM } },
2066   { "packuswb",         { MX, EM } },
2067   /* 68 */
2068   { "punpckhbw",        { MX, EM } },
2069   { "punpckhwd",        { MX, EM } },
2070   { "punpckhdq",        { MX, EM } },
2071   { "packssdw",         { MX, EM } },
2072   { PREFIX_TABLE (PREFIX_0F6C) },
2073   { PREFIX_TABLE (PREFIX_0F6D) },
2074   { "movK",             { MX, Edq } },
2075   { PREFIX_TABLE (PREFIX_0F6F) },
2076   /* 70 */
2077   { PREFIX_TABLE (PREFIX_0F70) },
2078   { REG_TABLE (REG_0F71) },
2079   { REG_TABLE (REG_0F72) },
2080   { REG_TABLE (REG_0F73) },
2081   { "pcmpeqb",          { MX, EM } },
2082   { "pcmpeqw",          { MX, EM } },
2083   { "pcmpeqd",          { MX, EM } },
2084   { "emms",             { XX } },
2085   /* 78 */
2086   { PREFIX_TABLE (PREFIX_0F78) },
2087   { PREFIX_TABLE (PREFIX_0F79) },
2088   { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
2089   { Bad_Opcode },
2090   { PREFIX_TABLE (PREFIX_0F7C) },
2091   { PREFIX_TABLE (PREFIX_0F7D) },
2092   { PREFIX_TABLE (PREFIX_0F7E) },
2093   { PREFIX_TABLE (PREFIX_0F7F) },
2094   /* 80 */
2095   { "joH",              { Jv, XX, cond_jump_flag } },
2096   { "jnoH",             { Jv, XX, cond_jump_flag } },
2097   { "jbH",              { Jv, XX, cond_jump_flag } },
2098   { "jaeH",             { Jv, XX, cond_jump_flag } },
2099   { "jeH",              { Jv, XX, cond_jump_flag } },
2100   { "jneH",             { Jv, XX, cond_jump_flag } },
2101   { "jbeH",             { Jv, XX, cond_jump_flag } },
2102   { "jaH",              { Jv, XX, cond_jump_flag } },
2103   /* 88 */
2104   { "jsH",              { Jv, XX, cond_jump_flag } },
2105   { "jnsH",             { Jv, XX, cond_jump_flag } },
2106   { "jpH",              { Jv, XX, cond_jump_flag } },
2107   { "jnpH",             { Jv, XX, cond_jump_flag } },
2108   { "jlH",              { Jv, XX, cond_jump_flag } },
2109   { "jgeH",             { Jv, XX, cond_jump_flag } },
2110   { "jleH",             { Jv, XX, cond_jump_flag } },
2111   { "jgH",              { Jv, XX, cond_jump_flag } },
2112   /* 90 */
2113   { "seto",             { Eb } },
2114   { "setno",            { Eb } },
2115   { "setb",             { Eb } },
2116   { "setae",            { Eb } },
2117   { "sete",             { Eb } },
2118   { "setne",            { Eb } },
2119   { "setbe",            { Eb } },
2120   { "seta",             { Eb } },
2121   /* 98 */
2122   { "sets",             { Eb } },
2123   { "setns",            { Eb } },
2124   { "setp",             { Eb } },
2125   { "setnp",            { Eb } },
2126   { "setl",             { Eb } },
2127   { "setge",            { Eb } },
2128   { "setle",            { Eb } },
2129   { "setg",             { Eb } },
2130   /* a0 */
2131   { "pushT",            { fs } },
2132   { "popT",             { fs } },
2133   { "cpuid",            { XX } },
2134   { "btS",              { Ev, Gv } },
2135   { "shldS",            { Ev, Gv, Ib } },
2136   { "shldS",            { Ev, Gv, CL } },
2137   { REG_TABLE (REG_0FA6) },
2138   { REG_TABLE (REG_0FA7) },
2139   /* a8 */
2140   { "pushT",            { gs } },
2141   { "popT",             { gs } },
2142   { "rsm",              { XX } },
2143   { "btsS",             { Ev, Gv } },
2144   { "shrdS",            { Ev, Gv, Ib } },
2145   { "shrdS",            { Ev, Gv, CL } },
2146   { REG_TABLE (REG_0FAE) },
2147   { "imulS",            { Gv, Ev } },
2148   /* b0 */
2149   { "cmpxchgB",         { Eb, Gb } },
2150   { "cmpxchgS",         { Ev, Gv } },
2151   { MOD_TABLE (MOD_0FB2) },
2152   { "btrS",             { Ev, Gv } },
2153   { MOD_TABLE (MOD_0FB4) },
2154   { MOD_TABLE (MOD_0FB5) },
2155   { "movz{bR|x}",       { Gv, Eb } },
2156   { "movz{wR|x}",       { Gv, Ew } }, /* yes, there really is movzww ! */
2157   /* b8 */
2158   { PREFIX_TABLE (PREFIX_0FB8) },
2159   { "ud1",              { XX } },
2160   { REG_TABLE (REG_0FBA) },
2161   { "btcS",             { Ev, Gv } },
2162   { "bsfS",             { Gv, Ev } },
2163   { PREFIX_TABLE (PREFIX_0FBD) },
2164   { "movs{bR|x}",       { Gv, Eb } },
2165   { "movs{wR|x}",       { Gv, Ew } }, /* yes, there really is movsww ! */
2166   /* c0 */
2167   { "xaddB",            { Eb, Gb } },
2168   { "xaddS",            { Ev, Gv } },
2169   { PREFIX_TABLE (PREFIX_0FC2) },
2170   { PREFIX_TABLE (PREFIX_0FC3) },
2171   { "pinsrw",           { MX, Edqw, Ib } },
2172   { "pextrw",           { Gdq, MS, Ib } },
2173   { "shufpX",           { XM, EXx, Ib } },
2174   { REG_TABLE (REG_0FC7) },
2175   /* c8 */
2176   { "bswap",            { RMeAX } },
2177   { "bswap",            { RMeCX } },
2178   { "bswap",            { RMeDX } },
2179   { "bswap",            { RMeBX } },
2180   { "bswap",            { RMeSP } },
2181   { "bswap",            { RMeBP } },
2182   { "bswap",            { RMeSI } },
2183   { "bswap",            { RMeDI } },
2184   /* d0 */
2185   { PREFIX_TABLE (PREFIX_0FD0) },
2186   { "psrlw",            { MX, EM } },
2187   { "psrld",            { MX, EM } },
2188   { "psrlq",            { MX, EM } },
2189   { "paddq",            { MX, EM } },
2190   { "pmullw",           { MX, EM } },
2191   { PREFIX_TABLE (PREFIX_0FD6) },
2192   { MOD_TABLE (MOD_0FD7) },
2193   /* d8 */
2194   { "psubusb",          { MX, EM } },
2195   { "psubusw",          { MX, EM } },
2196   { "pminub",           { MX, EM } },
2197   { "pand",             { MX, EM } },
2198   { "paddusb",          { MX, EM } },
2199   { "paddusw",          { MX, EM } },
2200   { "pmaxub",           { MX, EM } },
2201   { "pandn",            { MX, EM } },
2202   /* e0 */
2203   { "pavgb",            { MX, EM } },
2204   { "psraw",            { MX, EM } },
2205   { "psrad",            { MX, EM } },
2206   { "pavgw",            { MX, EM } },
2207   { "pmulhuw",          { MX, EM } },
2208   { "pmulhw",           { MX, EM } },
2209   { PREFIX_TABLE (PREFIX_0FE6) },
2210   { PREFIX_TABLE (PREFIX_0FE7) },
2211   /* e8 */
2212   { "psubsb",           { MX, EM } },
2213   { "psubsw",           { MX, EM } },
2214   { "pminsw",           { MX, EM } },
2215   { "por",              { MX, EM } },
2216   { "paddsb",           { MX, EM } },
2217   { "paddsw",           { MX, EM } },
2218   { "pmaxsw",           { MX, EM } },
2219   { "pxor",             { MX, EM } },
2220   /* f0 */
2221   { PREFIX_TABLE (PREFIX_0FF0) },
2222   { "psllw",            { MX, EM } },
2223   { "pslld",            { MX, EM } },
2224   { "psllq",            { MX, EM } },
2225   { "pmuludq",          { MX, EM } },
2226   { "pmaddwd",          { MX, EM } },
2227   { "psadbw",           { MX, EM } },
2228   { PREFIX_TABLE (PREFIX_0FF7) },
2229   /* f8 */
2230   { "psubb",            { MX, EM } },
2231   { "psubw",            { MX, EM } },
2232   { "psubd",            { MX, EM } },
2233   { "psubq",            { MX, EM } },
2234   { "paddb",            { MX, EM } },
2235   { "paddw",            { MX, EM } },
2236   { "paddd",            { MX, EM } },
2237   { Bad_Opcode },
2238 };
2239
2240 static const unsigned char onebyte_has_modrm[256] = {
2241   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2242   /*       -------------------------------        */
2243   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2244   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2245   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2246   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2247   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2248   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2249   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2250   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2251   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2252   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2253   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2254   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2255   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2256   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2257   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2258   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2259   /*       -------------------------------        */
2260   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2261 };
2262
2263 static const unsigned char twobyte_has_modrm[256] = {
2264   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2265   /*       -------------------------------        */
2266   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2267   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2268   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2269   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2270   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2271   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2272   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2273   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2274   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2275   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2276   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2277   /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
2278   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2279   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2280   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2281   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
2282   /*       -------------------------------        */
2283   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2284 };
2285
2286 static char obuf[100];
2287 static char *obufp;
2288 static char *mnemonicendp;
2289 static char scratchbuf[100];
2290 static unsigned char *start_codep;
2291 static unsigned char *insn_codep;
2292 static unsigned char *codep;
2293 static int last_lock_prefix;
2294 static int last_repz_prefix;
2295 static int last_repnz_prefix;
2296 static int last_data_prefix;
2297 static int last_addr_prefix;
2298 static int last_rex_prefix;
2299 static int last_seg_prefix;
2300 #define MAX_CODE_LENGTH 15
2301 /* We can up to 14 prefixes since the maximum instruction length is
2302    15bytes.  */
2303 static int all_prefixes[MAX_CODE_LENGTH - 1];
2304 static disassemble_info *the_info;
2305 static struct
2306   {
2307     int mod;
2308     int reg;
2309     int rm;
2310   }
2311 modrm;
2312 static unsigned char need_modrm;
2313 static struct
2314   {
2315     int scale;
2316     int index;
2317     int base;
2318   }
2319 sib;
2320 static struct
2321   {
2322     int register_specifier;
2323     int length;
2324     int prefix;
2325     int w;
2326   }
2327 vex;
2328 static unsigned char need_vex;
2329 static unsigned char need_vex_reg;
2330 static unsigned char vex_w_done;
2331
2332 struct op
2333   {
2334     const char *name;
2335     unsigned int len;
2336   };
2337
2338 /* If we are accessing mod/rm/reg without need_modrm set, then the
2339    values are stale.  Hitting this abort likely indicates that you
2340    need to update onebyte_has_modrm or twobyte_has_modrm.  */
2341 #define MODRM_CHECK  if (!need_modrm) abort ()
2342
2343 static const char **names64;
2344 static const char **names32;
2345 static const char **names16;
2346 static const char **names8;
2347 static const char **names8rex;
2348 static const char **names_seg;
2349 static const char *index64;
2350 static const char *index32;
2351 static const char **index16;
2352
2353 static const char *intel_names64[] = {
2354   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2355   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2356 };
2357 static const char *intel_names32[] = {
2358   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2359   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2360 };
2361 static const char *intel_names16[] = {
2362   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2363   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2364 };
2365 static const char *intel_names8[] = {
2366   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2367 };
2368 static const char *intel_names8rex[] = {
2369   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2370   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2371 };
2372 static const char *intel_names_seg[] = {
2373   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2374 };
2375 static const char *intel_index64 = "riz";
2376 static const char *intel_index32 = "eiz";
2377 static const char *intel_index16[] = {
2378   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2379 };
2380
2381 static const char *att_names64[] = {
2382   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2383   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2384 };
2385 static const char *att_names32[] = {
2386   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2387   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2388 };
2389 static const char *att_names16[] = {
2390   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2391   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2392 };
2393 static const char *att_names8[] = {
2394   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2395 };
2396 static const char *att_names8rex[] = {
2397   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2398   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2399 };
2400 static const char *att_names_seg[] = {
2401   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2402 };
2403 static const char *att_index64 = "%riz";
2404 static const char *att_index32 = "%eiz";
2405 static const char *att_index16[] = {
2406   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2407 };
2408
2409 static const char **names_mm;
2410 static const char *intel_names_mm[] = {
2411   "mm0", "mm1", "mm2", "mm3",
2412   "mm4", "mm5", "mm6", "mm7"
2413 };
2414 static const char *att_names_mm[] = {
2415   "%mm0", "%mm1", "%mm2", "%mm3",
2416   "%mm4", "%mm5", "%mm6", "%mm7"
2417 };
2418
2419 static const char **names_xmm;
2420 static const char *intel_names_xmm[] = {
2421   "xmm0", "xmm1", "xmm2", "xmm3",
2422   "xmm4", "xmm5", "xmm6", "xmm7",
2423   "xmm8", "xmm9", "xmm10", "xmm11",
2424   "xmm12", "xmm13", "xmm14", "xmm15"
2425 };
2426 static const char *att_names_xmm[] = {
2427   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2428   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2429   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2430   "%xmm12", "%xmm13", "%xmm14", "%xmm15"
2431 };
2432
2433 static const char **names_ymm;
2434 static const char *intel_names_ymm[] = {
2435   "ymm0", "ymm1", "ymm2", "ymm3",
2436   "ymm4", "ymm5", "ymm6", "ymm7",
2437   "ymm8", "ymm9", "ymm10", "ymm11",
2438   "ymm12", "ymm13", "ymm14", "ymm15"
2439 };
2440 static const char *att_names_ymm[] = {
2441   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2442   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2443   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2444   "%ymm12", "%ymm13", "%ymm14", "%ymm15"
2445 };
2446
2447 static const struct dis386 reg_table[][8] = {
2448   /* REG_80 */
2449   {
2450     { "addA",   { Eb, Ib } },
2451     { "orA",    { Eb, Ib } },
2452     { "adcA",   { Eb, Ib } },
2453     { "sbbA",   { Eb, Ib } },
2454     { "andA",   { Eb, Ib } },
2455     { "subA",   { Eb, Ib } },
2456     { "xorA",   { Eb, Ib } },
2457     { "cmpA",   { Eb, Ib } },
2458   },
2459   /* REG_81 */
2460   {
2461     { "addQ",   { Ev, Iv } },
2462     { "orQ",    { Ev, Iv } },
2463     { "adcQ",   { Ev, Iv } },
2464     { "sbbQ",   { Ev, Iv } },
2465     { "andQ",   { Ev, Iv } },
2466     { "subQ",   { Ev, Iv } },
2467     { "xorQ",   { Ev, Iv } },
2468     { "cmpQ",   { Ev, Iv } },
2469   },
2470   /* REG_82 */
2471   {
2472     { "addQ",   { Ev, sIb } },
2473     { "orQ",    { Ev, sIb } },
2474     { "adcQ",   { Ev, sIb } },
2475     { "sbbQ",   { Ev, sIb } },
2476     { "andQ",   { Ev, sIb } },
2477     { "subQ",   { Ev, sIb } },
2478     { "xorQ",   { Ev, sIb } },
2479     { "cmpQ",   { Ev, sIb } },
2480   },
2481   /* REG_8F */
2482   {
2483     { "popU",   { stackEv } },
2484     { XOP_8F_TABLE (XOP_09) },
2485     { Bad_Opcode },
2486     { Bad_Opcode },
2487     { Bad_Opcode },
2488     { XOP_8F_TABLE (XOP_09) },
2489   },
2490   /* REG_C0 */
2491   {
2492     { "rolA",   { Eb, Ib } },
2493     { "rorA",   { Eb, Ib } },
2494     { "rclA",   { Eb, Ib } },
2495     { "rcrA",   { Eb, Ib } },
2496     { "shlA",   { Eb, Ib } },
2497     { "shrA",   { Eb, Ib } },
2498     { Bad_Opcode },
2499     { "sarA",   { Eb, Ib } },
2500   },
2501   /* REG_C1 */
2502   {
2503     { "rolQ",   { Ev, Ib } },
2504     { "rorQ",   { Ev, Ib } },
2505     { "rclQ",   { Ev, Ib } },
2506     { "rcrQ",   { Ev, Ib } },
2507     { "shlQ",   { Ev, Ib } },
2508     { "shrQ",   { Ev, Ib } },
2509     { Bad_Opcode },
2510     { "sarQ",   { Ev, Ib } },
2511   },
2512   /* REG_C6 */
2513   {
2514     { "movA",   { Eb, Ib } },
2515   },
2516   /* REG_C7 */
2517   {
2518     { "movQ",   { Ev, Iv } },
2519   },
2520   /* REG_D0 */
2521   {
2522     { "rolA",   { Eb, I1 } },
2523     { "rorA",   { Eb, I1 } },
2524     { "rclA",   { Eb, I1 } },
2525     { "rcrA",   { Eb, I1 } },
2526     { "shlA",   { Eb, I1 } },
2527     { "shrA",   { Eb, I1 } },
2528     { Bad_Opcode },
2529     { "sarA",   { Eb, I1 } },
2530   },
2531   /* REG_D1 */
2532   {
2533     { "rolQ",   { Ev, I1 } },
2534     { "rorQ",   { Ev, I1 } },
2535     { "rclQ",   { Ev, I1 } },
2536     { "rcrQ",   { Ev, I1 } },
2537     { "shlQ",   { Ev, I1 } },
2538     { "shrQ",   { Ev, I1 } },
2539     { Bad_Opcode },
2540     { "sarQ",   { Ev, I1 } },
2541   },
2542   /* REG_D2 */
2543   {
2544     { "rolA",   { Eb, CL } },
2545     { "rorA",   { Eb, CL } },
2546     { "rclA",   { Eb, CL } },
2547     { "rcrA",   { Eb, CL } },
2548     { "shlA",   { Eb, CL } },
2549     { "shrA",   { Eb, CL } },
2550     { Bad_Opcode },
2551     { "sarA",   { Eb, CL } },
2552   },
2553   /* REG_D3 */
2554   {
2555     { "rolQ",   { Ev, CL } },
2556     { "rorQ",   { Ev, CL } },
2557     { "rclQ",   { Ev, CL } },
2558     { "rcrQ",   { Ev, CL } },
2559     { "shlQ",   { Ev, CL } },
2560     { "shrQ",   { Ev, CL } },
2561     { Bad_Opcode },
2562     { "sarQ",   { Ev, CL } },
2563   },
2564   /* REG_F6 */
2565   {
2566     { "testA",  { Eb, Ib } },
2567     { Bad_Opcode },
2568     { "notA",   { Eb } },
2569     { "negA",   { Eb } },
2570     { "mulA",   { Eb } },       /* Don't print the implicit %al register,  */
2571     { "imulA",  { Eb } },       /* to distinguish these opcodes from other */
2572     { "divA",   { Eb } },       /* mul/imul opcodes.  Do the same for div  */
2573     { "idivA",  { Eb } },       /* and idiv for consistency.               */
2574   },
2575   /* REG_F7 */
2576   {
2577     { "testQ",  { Ev, Iv } },
2578     { Bad_Opcode },
2579     { "notQ",   { Ev } },
2580     { "negQ",   { Ev } },
2581     { "mulQ",   { Ev } },       /* Don't print the implicit register.  */
2582     { "imulQ",  { Ev } },
2583     { "divQ",   { Ev } },
2584     { "idivQ",  { Ev } },
2585   },
2586   /* REG_FE */
2587   {
2588     { "incA",   { Eb } },
2589     { "decA",   { Eb } },
2590   },
2591   /* REG_FF */
2592   {
2593     { "incQ",   { Ev } },
2594     { "decQ",   { Ev } },
2595     { "call{T|}", { indirEv } },
2596     { "Jcall{T|}", { indirEp } },
2597     { "jmp{T|}", { indirEv } },
2598     { "Jjmp{T|}", { indirEp } },
2599     { "pushU",  { stackEv } },
2600     { Bad_Opcode },
2601   },
2602   /* REG_0F00 */
2603   {
2604     { "sldtD",  { Sv } },
2605     { "strD",   { Sv } },
2606     { "lldt",   { Ew } },
2607     { "ltr",    { Ew } },
2608     { "verr",   { Ew } },
2609     { "verw",   { Ew } },
2610     { Bad_Opcode },
2611     { Bad_Opcode },
2612   },
2613   /* REG_0F01 */
2614   {
2615     { MOD_TABLE (MOD_0F01_REG_0) },
2616     { MOD_TABLE (MOD_0F01_REG_1) },
2617     { MOD_TABLE (MOD_0F01_REG_2) },
2618     { MOD_TABLE (MOD_0F01_REG_3) },
2619     { "smswD",  { Sv } },
2620     { Bad_Opcode },
2621     { "lmsw",   { Ew } },
2622     { MOD_TABLE (MOD_0F01_REG_7) },
2623   },
2624   /* REG_0F0D */
2625   {
2626     { "prefetch",       { Mb } },
2627     { "prefetchw",      { Mb } },
2628   },
2629   /* REG_0F18 */
2630   {
2631     { MOD_TABLE (MOD_0F18_REG_0) },
2632     { MOD_TABLE (MOD_0F18_REG_1) },
2633     { MOD_TABLE (MOD_0F18_REG_2) },
2634     { MOD_TABLE (MOD_0F18_REG_3) },
2635   },
2636   /* REG_0F71 */
2637   {
2638     { Bad_Opcode },
2639     { Bad_Opcode },
2640     { MOD_TABLE (MOD_0F71_REG_2) },
2641     { Bad_Opcode },
2642     { MOD_TABLE (MOD_0F71_REG_4) },
2643     { Bad_Opcode },
2644     { MOD_TABLE (MOD_0F71_REG_6) },
2645   },
2646   /* REG_0F72 */
2647   {
2648     { Bad_Opcode },
2649     { Bad_Opcode },
2650     { MOD_TABLE (MOD_0F72_REG_2) },
2651     { Bad_Opcode },
2652     { MOD_TABLE (MOD_0F72_REG_4) },
2653     { Bad_Opcode },
2654     { MOD_TABLE (MOD_0F72_REG_6) },
2655   },
2656   /* REG_0F73 */
2657   {
2658     { Bad_Opcode },
2659     { Bad_Opcode },
2660     { MOD_TABLE (MOD_0F73_REG_2) },
2661     { MOD_TABLE (MOD_0F73_REG_3) },
2662     { Bad_Opcode },
2663     { Bad_Opcode },
2664     { MOD_TABLE (MOD_0F73_REG_6) },
2665     { MOD_TABLE (MOD_0F73_REG_7) },
2666   },
2667   /* REG_0FA6 */
2668   {
2669     { "montmul",        { { OP_0f07, 0 } } },
2670     { "xsha1",          { { OP_0f07, 0 } } },
2671     { "xsha256",        { { OP_0f07, 0 } } },
2672   },
2673   /* REG_0FA7 */
2674   {
2675     { "xstore-rng",     { { OP_0f07, 0 } } },
2676     { "xcrypt-ecb",     { { OP_0f07, 0 } } },
2677     { "xcrypt-cbc",     { { OP_0f07, 0 } } },
2678     { "xcrypt-ctr",     { { OP_0f07, 0 } } },
2679     { "xcrypt-cfb",     { { OP_0f07, 0 } } },
2680     { "xcrypt-ofb",     { { OP_0f07, 0 } } },
2681   },
2682   /* REG_0FAE */
2683   {
2684     { MOD_TABLE (MOD_0FAE_REG_0) },
2685     { MOD_TABLE (MOD_0FAE_REG_1) },
2686     { MOD_TABLE (MOD_0FAE_REG_2) },
2687     { MOD_TABLE (MOD_0FAE_REG_3) },
2688     { MOD_TABLE (MOD_0FAE_REG_4) },
2689     { MOD_TABLE (MOD_0FAE_REG_5) },
2690     { MOD_TABLE (MOD_0FAE_REG_6) },
2691     { MOD_TABLE (MOD_0FAE_REG_7) },
2692   },
2693   /* REG_0FBA */
2694   {
2695     { Bad_Opcode },
2696     { Bad_Opcode },
2697     { Bad_Opcode },
2698     { Bad_Opcode },
2699     { "btQ",    { Ev, Ib } },
2700     { "btsQ",   { Ev, Ib } },
2701     { "btrQ",   { Ev, Ib } },
2702     { "btcQ",   { Ev, Ib } },
2703   },
2704   /* REG_0FC7 */
2705   {
2706     { Bad_Opcode },
2707     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
2708     { Bad_Opcode },
2709     { Bad_Opcode },
2710     { Bad_Opcode },
2711     { Bad_Opcode },
2712     { MOD_TABLE (MOD_0FC7_REG_6) },
2713     { MOD_TABLE (MOD_0FC7_REG_7) },
2714   },
2715   /* REG_VEX_0F71 */
2716   {
2717     { Bad_Opcode },
2718     { Bad_Opcode },
2719     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
2720     { Bad_Opcode },
2721     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
2722     { Bad_Opcode },
2723     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
2724   },
2725   /* REG_VEX_0F72 */
2726   {
2727     { Bad_Opcode },
2728     { Bad_Opcode },
2729     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
2730     { Bad_Opcode },
2731     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
2732     { Bad_Opcode },
2733     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
2734   },
2735   /* REG_VEX_0F73 */
2736   {
2737     { Bad_Opcode },
2738     { Bad_Opcode },
2739     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
2740     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
2741     { Bad_Opcode },
2742     { Bad_Opcode },
2743     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
2744     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
2745   },
2746   /* REG_VEX_0FAE */
2747   {
2748     { Bad_Opcode },
2749     { Bad_Opcode },
2750     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
2751     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
2752   },
2753   /* REG_XOP_LWPCB */
2754   {
2755     { "llwpcb", { { OP_LWPCB_E, 0 } } },
2756     { "slwpcb", { { OP_LWPCB_E, 0 } } },
2757   },
2758   /* REG_XOP_LWP */
2759   {
2760     { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq } },
2761     { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq } },
2762   },
2763 };
2764
2765 static const struct dis386 prefix_table[][4] = {
2766   /* PREFIX_90 */
2767   {
2768     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2769     { "pause", { XX } },
2770     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2771   },
2772
2773   /* PREFIX_0F10 */
2774   {
2775     { "movups", { XM, EXx } },
2776     { "movss",  { XM, EXd } },
2777     { "movupd", { XM, EXx } },
2778     { "movsd",  { XM, EXq } },
2779   },
2780
2781   /* PREFIX_0F11 */
2782   {
2783     { "movups", { EXxS, XM } },
2784     { "movss",  { EXdS, XM } },
2785     { "movupd", { EXxS, XM } },
2786     { "movsd",  { EXqS, XM } },
2787   },
2788
2789   /* PREFIX_0F12 */
2790   {
2791     { MOD_TABLE (MOD_0F12_PREFIX_0) },
2792     { "movsldup", { XM, EXx } },
2793     { "movlpd", { XM, EXq } },
2794     { "movddup", { XM, EXq } },
2795   },
2796
2797   /* PREFIX_0F16 */
2798   {
2799     { MOD_TABLE (MOD_0F16_PREFIX_0) },
2800     { "movshdup", { XM, EXx } },
2801     { "movhpd", { XM, EXq } },
2802   },
2803
2804   /* PREFIX_0F2A */
2805   {
2806     { "cvtpi2ps", { XM, EMCq } },
2807     { "cvtsi2ss%LQ", { XM, Ev } },
2808     { "cvtpi2pd", { XM, EMCq } },
2809     { "cvtsi2sd%LQ", { XM, Ev } },
2810   },
2811
2812   /* PREFIX_0F2B */
2813   {
2814     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
2815     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
2816     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
2817     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
2818   },
2819
2820   /* PREFIX_0F2C */
2821   {
2822     { "cvttps2pi", { MXC, EXq } },
2823     { "cvttss2siY", { Gv, EXd } },
2824     { "cvttpd2pi", { MXC, EXx } },
2825     { "cvttsd2siY", { Gv, EXq } },
2826   },
2827
2828   /* PREFIX_0F2D */
2829   {
2830     { "cvtps2pi", { MXC, EXq } },
2831     { "cvtss2siY", { Gv, EXd } },
2832     { "cvtpd2pi", { MXC, EXx } },
2833     { "cvtsd2siY", { Gv, EXq } },
2834   },
2835
2836   /* PREFIX_0F2E */
2837   {
2838     { "ucomiss",{ XM, EXd } },
2839     { Bad_Opcode },
2840     { "ucomisd",{ XM, EXq } },
2841   },
2842
2843   /* PREFIX_0F2F */
2844   {
2845     { "comiss", { XM, EXd } },
2846     { Bad_Opcode },
2847     { "comisd", { XM, EXq } },
2848   },
2849
2850   /* PREFIX_0F51 */
2851   {
2852     { "sqrtps", { XM, EXx } },
2853     { "sqrtss", { XM, EXd } },
2854     { "sqrtpd", { XM, EXx } },
2855     { "sqrtsd", { XM, EXq } },
2856   },
2857
2858   /* PREFIX_0F52 */
2859   {
2860     { "rsqrtps",{ XM, EXx } },
2861     { "rsqrtss",{ XM, EXd } },
2862   },
2863
2864   /* PREFIX_0F53 */
2865   {
2866     { "rcpps",  { XM, EXx } },
2867     { "rcpss",  { XM, EXd } },
2868   },
2869
2870   /* PREFIX_0F58 */
2871   {
2872     { "addps", { XM, EXx } },
2873     { "addss", { XM, EXd } },
2874     { "addpd", { XM, EXx } },
2875     { "addsd", { XM, EXq } },
2876   },
2877
2878   /* PREFIX_0F59 */
2879   {
2880     { "mulps",  { XM, EXx } },
2881     { "mulss",  { XM, EXd } },
2882     { "mulpd",  { XM, EXx } },
2883     { "mulsd",  { XM, EXq } },
2884   },
2885
2886   /* PREFIX_0F5A */
2887   {
2888     { "cvtps2pd", { XM, EXq } },
2889     { "cvtss2sd", { XM, EXd } },
2890     { "cvtpd2ps", { XM, EXx } },
2891     { "cvtsd2ss", { XM, EXq } },
2892   },
2893
2894   /* PREFIX_0F5B */
2895   {
2896     { "cvtdq2ps", { XM, EXx } },
2897     { "cvttps2dq", { XM, EXx } },
2898     { "cvtps2dq", { XM, EXx } },
2899   },
2900
2901   /* PREFIX_0F5C */
2902   {
2903     { "subps",  { XM, EXx } },
2904     { "subss",  { XM, EXd } },
2905     { "subpd",  { XM, EXx } },
2906     { "subsd",  { XM, EXq } },
2907   },
2908
2909   /* PREFIX_0F5D */
2910   {
2911     { "minps",  { XM, EXx } },
2912     { "minss",  { XM, EXd } },
2913     { "minpd",  { XM, EXx } },
2914     { "minsd",  { XM, EXq } },
2915   },
2916
2917   /* PREFIX_0F5E */
2918   {
2919     { "divps",  { XM, EXx } },
2920     { "divss",  { XM, EXd } },
2921     { "divpd",  { XM, EXx } },
2922     { "divsd",  { XM, EXq } },
2923   },
2924
2925   /* PREFIX_0F5F */
2926   {
2927     { "maxps",  { XM, EXx } },
2928     { "maxss",  { XM, EXd } },
2929     { "maxpd",  { XM, EXx } },
2930     { "maxsd",  { XM, EXq } },
2931   },
2932
2933   /* PREFIX_0F60 */
2934   {
2935     { "punpcklbw",{ MX, EMd } },
2936     { Bad_Opcode },
2937     { "punpcklbw",{ MX, EMx } },
2938   },
2939
2940   /* PREFIX_0F61 */
2941   {
2942     { "punpcklwd",{ MX, EMd } },
2943     { Bad_Opcode },
2944     { "punpcklwd",{ MX, EMx } },
2945   },
2946
2947   /* PREFIX_0F62 */
2948   {
2949     { "punpckldq",{ MX, EMd } },
2950     { Bad_Opcode },
2951     { "punpckldq",{ MX, EMx } },
2952   },
2953
2954   /* PREFIX_0F6C */
2955   {
2956     { Bad_Opcode },
2957     { Bad_Opcode },
2958     { "punpcklqdq", { XM, EXx } },
2959   },
2960
2961   /* PREFIX_0F6D */
2962   {
2963     { Bad_Opcode },
2964     { Bad_Opcode },
2965     { "punpckhqdq", { XM, EXx } },
2966   },
2967
2968   /* PREFIX_0F6F */
2969   {
2970     { "movq",   { MX, EM } },
2971     { "movdqu", { XM, EXx } },
2972     { "movdqa", { XM, EXx } },
2973   },
2974
2975   /* PREFIX_0F70 */
2976   {
2977     { "pshufw", { MX, EM, Ib } },
2978     { "pshufhw",{ XM, EXx, Ib } },
2979     { "pshufd", { XM, EXx, Ib } },
2980     { "pshuflw",{ XM, EXx, Ib } },
2981   },
2982
2983   /* PREFIX_0F73_REG_3 */
2984   {
2985     { Bad_Opcode },
2986     { Bad_Opcode },
2987     { "psrldq", { XS, Ib } },
2988   },
2989
2990   /* PREFIX_0F73_REG_7 */
2991   {
2992     { Bad_Opcode },
2993     { Bad_Opcode },
2994     { "pslldq", { XS, Ib } },
2995   },
2996
2997   /* PREFIX_0F78 */
2998   {
2999     {"vmread",  { Em, Gm } },
3000     { Bad_Opcode },
3001     {"extrq",   { XS, Ib, Ib } },
3002     {"insertq", { XM, XS, Ib, Ib } },
3003   },
3004
3005   /* PREFIX_0F79 */
3006   {
3007     {"vmwrite", { Gm, Em } },
3008     { Bad_Opcode },
3009     {"extrq",   { XM, XS } },
3010     {"insertq", { XM, XS } },
3011   },
3012
3013   /* PREFIX_0F7C */
3014   {
3015     { Bad_Opcode },
3016     { Bad_Opcode },
3017     { "haddpd", { XM, EXx } },
3018     { "haddps", { XM, EXx } },
3019   },
3020
3021   /* PREFIX_0F7D */
3022   {
3023     { Bad_Opcode },
3024     { Bad_Opcode },
3025     { "hsubpd", { XM, EXx } },
3026     { "hsubps", { XM, EXx } },
3027   },
3028
3029   /* PREFIX_0F7E */
3030   {
3031     { "movK",   { Edq, MX } },
3032     { "movq",   { XM, EXq } },
3033     { "movK",   { Edq, XM } },
3034   },
3035
3036   /* PREFIX_0F7F */
3037   {
3038     { "movq",   { EMS, MX } },
3039     { "movdqu", { EXxS, XM } },
3040     { "movdqa", { EXxS, XM } },
3041   },
3042
3043   /* PREFIX_0FAE_REG_0 */
3044   {
3045     { Bad_Opcode },
3046     { "rdfsbase", { Ev } },
3047   },
3048
3049   /* PREFIX_0FAE_REG_1 */
3050   {
3051     { Bad_Opcode },
3052     { "rdgsbase", { Ev } },
3053   },
3054
3055   /* PREFIX_0FAE_REG_2 */
3056   {
3057     { Bad_Opcode },
3058     { "wrfsbase", { Ev } },
3059   },
3060
3061   /* PREFIX_0FAE_REG_3 */
3062   {
3063     { Bad_Opcode },
3064     { "wrgsbase", { Ev } },
3065   },
3066
3067   /* PREFIX_0FB8 */
3068   {
3069     { Bad_Opcode },
3070     { "popcntS", { Gv, Ev } },
3071   },
3072
3073   /* PREFIX_0FBD */
3074   {
3075     { "bsrS",   { Gv, Ev } },
3076     { "lzcntS", { Gv, Ev } },
3077     { "bsrS",   { Gv, Ev } },
3078   },
3079
3080   /* PREFIX_0FC2 */
3081   {
3082     { "cmpps",  { XM, EXx, CMP } },
3083     { "cmpss",  { XM, EXd, CMP } },
3084     { "cmppd",  { XM, EXx, CMP } },
3085     { "cmpsd",  { XM, EXq, CMP } },
3086   },
3087
3088   /* PREFIX_0FC3 */
3089   {
3090     { "movntiS", { Ma, Gv } },
3091   },
3092
3093   /* PREFIX_0FC7_REG_6 */
3094   {
3095     { "vmptrld",{ Mq } },
3096     { "vmxon",  { Mq } },
3097     { "vmclear",{ Mq } },
3098   },
3099
3100   /* PREFIX_0FD0 */
3101   {
3102     { Bad_Opcode },
3103     { Bad_Opcode },
3104     { "addsubpd", { XM, EXx } },
3105     { "addsubps", { XM, EXx } },
3106   },
3107
3108   /* PREFIX_0FD6 */
3109   {
3110     { Bad_Opcode },
3111     { "movq2dq",{ XM, MS } },
3112     { "movq",   { EXqS, XM } },
3113     { "movdq2q",{ MX, XS } },
3114   },
3115
3116   /* PREFIX_0FE6 */
3117   {
3118     { Bad_Opcode },
3119     { "cvtdq2pd", { XM, EXq } },
3120     { "cvttpd2dq", { XM, EXx } },
3121     { "cvtpd2dq", { XM, EXx } },
3122   },
3123
3124   /* PREFIX_0FE7 */
3125   {
3126     { "movntq", { Mq, MX } },
3127     { Bad_Opcode },
3128     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
3129   },
3130
3131   /* PREFIX_0FF0 */
3132   {
3133     { Bad_Opcode },
3134     { Bad_Opcode },
3135     { Bad_Opcode },
3136     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
3137   },
3138
3139   /* PREFIX_0FF7 */
3140   {
3141     { "maskmovq", { MX, MS } },
3142     { Bad_Opcode },
3143     { "maskmovdqu", { XM, XS } },
3144   },
3145
3146   /* PREFIX_0F3810 */
3147   {
3148     { Bad_Opcode },
3149     { Bad_Opcode },
3150     { "pblendvb", { XM, EXx, XMM0 } },
3151   },
3152
3153   /* PREFIX_0F3814 */
3154   {
3155     { Bad_Opcode },
3156     { Bad_Opcode },
3157     { "blendvps", { XM, EXx, XMM0 } },
3158   },
3159
3160   /* PREFIX_0F3815 */
3161   {
3162     { Bad_Opcode },
3163     { Bad_Opcode },
3164     { "blendvpd", { XM, EXx, XMM0 } },
3165   },
3166
3167   /* PREFIX_0F3817 */
3168   {
3169     { Bad_Opcode },
3170     { Bad_Opcode },
3171     { "ptest",  { XM, EXx } },
3172   },
3173
3174   /* PREFIX_0F3820 */
3175   {
3176     { Bad_Opcode },
3177     { Bad_Opcode },
3178     { "pmovsxbw", { XM, EXq } },
3179   },
3180
3181   /* PREFIX_0F3821 */
3182   {
3183     { Bad_Opcode },
3184     { Bad_Opcode },
3185     { "pmovsxbd", { XM, EXd } },
3186   },
3187
3188   /* PREFIX_0F3822 */
3189   {
3190     { Bad_Opcode },
3191     { Bad_Opcode },
3192     { "pmovsxbq", { XM, EXw } },
3193   },
3194
3195   /* PREFIX_0F3823 */
3196   {
3197     { Bad_Opcode },
3198     { Bad_Opcode },
3199     { "pmovsxwd", { XM, EXq } },
3200   },
3201
3202   /* PREFIX_0F3824 */
3203   {
3204     { Bad_Opcode },
3205     { Bad_Opcode },
3206     { "pmovsxwq", { XM, EXd } },
3207   },
3208
3209   /* PREFIX_0F3825 */
3210   {
3211     { Bad_Opcode },
3212     { Bad_Opcode },
3213     { "pmovsxdq", { XM, EXq } },
3214   },
3215
3216   /* PREFIX_0F3828 */
3217   {
3218     { Bad_Opcode },
3219     { Bad_Opcode },
3220     { "pmuldq", { XM, EXx } },
3221   },
3222
3223   /* PREFIX_0F3829 */
3224   {
3225     { Bad_Opcode },
3226     { Bad_Opcode },
3227     { "pcmpeqq", { XM, EXx } },
3228   },
3229
3230   /* PREFIX_0F382A */
3231   {
3232     { Bad_Opcode },
3233     { Bad_Opcode },
3234     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
3235   },
3236
3237   /* PREFIX_0F382B */
3238   {
3239     { Bad_Opcode },
3240     { Bad_Opcode },
3241     { "packusdw", { XM, EXx } },
3242   },
3243
3244   /* PREFIX_0F3830 */
3245   {
3246     { Bad_Opcode },
3247     { Bad_Opcode },
3248     { "pmovzxbw", { XM, EXq } },
3249   },
3250
3251   /* PREFIX_0F3831 */
3252   {
3253     { Bad_Opcode },
3254     { Bad_Opcode },
3255     { "pmovzxbd", { XM, EXd } },
3256   },
3257
3258   /* PREFIX_0F3832 */
3259   {
3260     { Bad_Opcode },
3261     { Bad_Opcode },
3262     { "pmovzxbq", { XM, EXw } },
3263   },
3264
3265   /* PREFIX_0F3833 */
3266   {
3267     { Bad_Opcode },
3268     { Bad_Opcode },
3269     { "pmovzxwd", { XM, EXq } },
3270   },
3271
3272   /* PREFIX_0F3834 */
3273   {
3274     { Bad_Opcode },
3275     { Bad_Opcode },
3276     { "pmovzxwq", { XM, EXd } },
3277   },
3278
3279   /* PREFIX_0F3835 */
3280   {
3281     { Bad_Opcode },
3282     { Bad_Opcode },
3283     { "pmovzxdq", { XM, EXq } },
3284   },
3285
3286   /* PREFIX_0F3837 */
3287   {
3288     { Bad_Opcode },
3289     { Bad_Opcode },
3290     { "pcmpgtq", { XM, EXx } },
3291   },
3292
3293   /* PREFIX_0F3838 */
3294   {
3295     { Bad_Opcode },
3296     { Bad_Opcode },
3297     { "pminsb", { XM, EXx } },
3298   },
3299
3300   /* PREFIX_0F3839 */
3301   {
3302     { Bad_Opcode },
3303     { Bad_Opcode },
3304     { "pminsd", { XM, EXx } },
3305   },
3306
3307   /* PREFIX_0F383A */
3308   {
3309     { Bad_Opcode },
3310     { Bad_Opcode },
3311     { "pminuw", { XM, EXx } },
3312   },
3313
3314   /* PREFIX_0F383B */
3315   {
3316     { Bad_Opcode },
3317     { Bad_Opcode },
3318     { "pminud", { XM, EXx } },
3319   },
3320
3321   /* PREFIX_0F383C */
3322   {
3323     { Bad_Opcode },
3324     { Bad_Opcode },
3325     { "pmaxsb", { XM, EXx } },
3326   },
3327
3328   /* PREFIX_0F383D */
3329   {
3330     { Bad_Opcode },
3331     { Bad_Opcode },
3332     { "pmaxsd", { XM, EXx } },
3333   },
3334
3335   /* PREFIX_0F383E */
3336   {
3337     { Bad_Opcode },
3338     { Bad_Opcode },
3339     { "pmaxuw", { XM, EXx } },
3340   },
3341
3342   /* PREFIX_0F383F */
3343   {
3344     { Bad_Opcode },
3345     { Bad_Opcode },
3346     { "pmaxud", { XM, EXx } },
3347   },
3348
3349   /* PREFIX_0F3840 */
3350   {
3351     { Bad_Opcode },
3352     { Bad_Opcode },
3353     { "pmulld", { XM, EXx } },
3354   },
3355
3356   /* PREFIX_0F3841 */
3357   {
3358     { Bad_Opcode },
3359     { Bad_Opcode },
3360     { "phminposuw", { XM, EXx } },
3361   },
3362
3363   /* PREFIX_0F3880 */
3364   {
3365     { Bad_Opcode },
3366     { Bad_Opcode },
3367     { "invept", { Gm, Mo } },
3368   },
3369
3370   /* PREFIX_0F3881 */
3371   {
3372     { Bad_Opcode },
3373     { Bad_Opcode },
3374     { "invvpid", { Gm, Mo } },
3375   },
3376
3377   /* PREFIX_0F38DB */
3378   {
3379     { Bad_Opcode },
3380     { Bad_Opcode },
3381     { "aesimc", { XM, EXx } },
3382   },
3383
3384   /* PREFIX_0F38DC */
3385   {
3386     { Bad_Opcode },
3387     { Bad_Opcode },
3388     { "aesenc", { XM, EXx } },
3389   },
3390
3391   /* PREFIX_0F38DD */
3392   {
3393     { Bad_Opcode },
3394     { Bad_Opcode },
3395     { "aesenclast", { XM, EXx } },
3396   },
3397
3398   /* PREFIX_0F38DE */
3399   {
3400     { Bad_Opcode },
3401     { Bad_Opcode },
3402     { "aesdec", { XM, EXx } },
3403   },
3404
3405   /* PREFIX_0F38DF */
3406   {
3407     { Bad_Opcode },
3408     { Bad_Opcode },
3409     { "aesdeclast", { XM, EXx } },
3410   },
3411
3412   /* PREFIX_0F38F0 */
3413   {
3414     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
3415     { Bad_Opcode },
3416     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
3417     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } } },
3418   },
3419
3420   /* PREFIX_0F38F1 */
3421   {
3422     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
3423     { Bad_Opcode },
3424     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
3425     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } } },
3426   },
3427
3428   /* PREFIX_0F3A08 */
3429   {
3430     { Bad_Opcode },
3431     { Bad_Opcode },
3432     { "roundps", { XM, EXx, Ib } },
3433   },
3434
3435   /* PREFIX_0F3A09 */
3436   {
3437     { Bad_Opcode },
3438     { Bad_Opcode },
3439     { "roundpd", { XM, EXx, Ib } },
3440   },
3441
3442   /* PREFIX_0F3A0A */
3443   {
3444     { Bad_Opcode },
3445     { Bad_Opcode },
3446     { "roundss", { XM, EXd, Ib } },
3447   },
3448
3449   /* PREFIX_0F3A0B */
3450   {
3451     { Bad_Opcode },
3452     { Bad_Opcode },
3453     { "roundsd", { XM, EXq, Ib } },
3454   },
3455
3456   /* PREFIX_0F3A0C */
3457   {
3458     { Bad_Opcode },
3459     { Bad_Opcode },
3460     { "blendps", { XM, EXx, Ib } },
3461   },
3462
3463   /* PREFIX_0F3A0D */
3464   {
3465     { Bad_Opcode },
3466     { Bad_Opcode },
3467     { "blendpd", { XM, EXx, Ib } },
3468   },
3469
3470   /* PREFIX_0F3A0E */
3471   {
3472     { Bad_Opcode },
3473     { Bad_Opcode },
3474     { "pblendw", { XM, EXx, Ib } },
3475   },
3476
3477   /* PREFIX_0F3A14 */
3478   {
3479     { Bad_Opcode },
3480     { Bad_Opcode },
3481     { "pextrb", { Edqb, XM, Ib } },
3482   },
3483
3484   /* PREFIX_0F3A15 */
3485   {
3486     { Bad_Opcode },
3487     { Bad_Opcode },
3488     { "pextrw", { Edqw, XM, Ib } },
3489   },
3490
3491   /* PREFIX_0F3A16 */
3492   {
3493     { Bad_Opcode },
3494     { Bad_Opcode },
3495     { "pextrK", { Edq, XM, Ib } },
3496   },
3497
3498   /* PREFIX_0F3A17 */
3499   {
3500     { Bad_Opcode },
3501     { Bad_Opcode },
3502     { "extractps", { Edqd, XM, Ib } },
3503   },
3504
3505   /* PREFIX_0F3A20 */
3506   {
3507     { Bad_Opcode },
3508     { Bad_Opcode },
3509     { "pinsrb", { XM, Edqb, Ib } },
3510   },
3511
3512   /* PREFIX_0F3A21 */
3513   {
3514     { Bad_Opcode },
3515     { Bad_Opcode },
3516     { "insertps", { XM, EXd, Ib } },
3517   },
3518
3519   /* PREFIX_0F3A22 */
3520   {
3521     { Bad_Opcode },
3522     { Bad_Opcode },
3523     { "pinsrK", { XM, Edq, Ib } },
3524   },
3525
3526   /* PREFIX_0F3A40 */
3527   {
3528     { Bad_Opcode },
3529     { Bad_Opcode },
3530     { "dpps",   { XM, EXx, Ib } },
3531   },
3532
3533   /* PREFIX_0F3A41 */
3534   {
3535     { Bad_Opcode },
3536     { Bad_Opcode },
3537     { "dppd",   { XM, EXx, Ib } },
3538   },
3539
3540   /* PREFIX_0F3A42 */
3541   {
3542     { Bad_Opcode },
3543     { Bad_Opcode },
3544     { "mpsadbw", { XM, EXx, Ib } },
3545   },
3546
3547   /* PREFIX_0F3A44 */
3548   {
3549     { Bad_Opcode },
3550     { Bad_Opcode },
3551     { "pclmulqdq", { XM, EXx, PCLMUL } },
3552   },
3553
3554   /* PREFIX_0F3A60 */
3555   {
3556     { Bad_Opcode },
3557     { Bad_Opcode },
3558     { "pcmpestrm", { XM, EXx, Ib } },
3559   },
3560
3561   /* PREFIX_0F3A61 */
3562   {
3563     { Bad_Opcode },
3564     { Bad_Opcode },
3565     { "pcmpestri", { XM, EXx, Ib } },
3566   },
3567
3568   /* PREFIX_0F3A62 */
3569   {
3570     { Bad_Opcode },
3571     { Bad_Opcode },
3572     { "pcmpistrm", { XM, EXx, Ib } },
3573   },
3574
3575   /* PREFIX_0F3A63 */
3576   {
3577     { Bad_Opcode },
3578     { Bad_Opcode },
3579     { "pcmpistri", { XM, EXx, Ib } },
3580   },
3581
3582   /* PREFIX_0F3ADF */
3583   {
3584     { Bad_Opcode },
3585     { Bad_Opcode },
3586     { "aeskeygenassist", { XM, EXx, Ib } },
3587   },
3588
3589   /* PREFIX_VEX_0F10 */
3590   {
3591     { VEX_W_TABLE (VEX_W_0F10_P_0) },
3592     { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
3593     { VEX_W_TABLE (VEX_W_0F10_P_2) },
3594     { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
3595   },
3596
3597   /* PREFIX_VEX_0F11 */
3598   {
3599     { VEX_W_TABLE (VEX_W_0F11_P_0) },
3600     { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
3601     { VEX_W_TABLE (VEX_W_0F11_P_2) },
3602     { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
3603   },
3604
3605   /* PREFIX_VEX_0F12 */
3606   {
3607     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
3608     { VEX_W_TABLE (VEX_W_0F12_P_1) },
3609     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
3610     { VEX_W_TABLE (VEX_W_0F12_P_3) },
3611   },
3612
3613   /* PREFIX_VEX_0F16 */
3614   {
3615     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
3616     { VEX_W_TABLE (VEX_W_0F16_P_1) },
3617     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
3618   },
3619
3620   /* PREFIX_VEX_0F2A */
3621   {
3622     { Bad_Opcode },
3623     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
3624     { Bad_Opcode },
3625     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
3626   },
3627
3628   /* PREFIX_VEX_0F2C */
3629   {
3630     { Bad_Opcode },
3631     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
3632     { Bad_Opcode },
3633     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
3634   },
3635
3636   /* PREFIX_VEX_0F2D */
3637   {
3638     { Bad_Opcode },
3639     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
3640     { Bad_Opcode },
3641     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
3642   },
3643
3644   /* PREFIX_VEX_0F2E */
3645   {
3646     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
3647     { Bad_Opcode },
3648     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
3649   },
3650
3651   /* PREFIX_VEX_0F2F */
3652   {
3653     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
3654     { Bad_Opcode },
3655     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
3656   },
3657
3658   /* PREFIX_VEX_0F51 */
3659   {
3660     { VEX_W_TABLE (VEX_W_0F51_P_0) },
3661     { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
3662     { VEX_W_TABLE (VEX_W_0F51_P_2) },
3663     { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
3664   },
3665
3666   /* PREFIX_VEX_0F52 */
3667   {
3668     { VEX_W_TABLE (VEX_W_0F52_P_0) },
3669     { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
3670   },
3671
3672   /* PREFIX_VEX_0F53 */
3673   {
3674     { VEX_W_TABLE (VEX_W_0F53_P_0) },
3675     { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
3676   },
3677
3678   /* PREFIX_VEX_0F58 */
3679   {
3680     { VEX_W_TABLE (VEX_W_0F58_P_0) },
3681     { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
3682     { VEX_W_TABLE (VEX_W_0F58_P_2) },
3683     { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
3684   },
3685
3686   /* PREFIX_VEX_0F59 */
3687   {
3688     { VEX_W_TABLE (VEX_W_0F59_P_0) },
3689     { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
3690     { VEX_W_TABLE (VEX_W_0F59_P_2) },
3691     { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
3692   },
3693
3694   /* PREFIX_VEX_0F5A */
3695   {
3696     { VEX_W_TABLE (VEX_W_0F5A_P_0) },
3697     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
3698     { "vcvtpd2ps%XY", { XMM, EXx } },
3699     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
3700   },
3701
3702   /* PREFIX_VEX_0F5B */
3703   {
3704     { VEX_W_TABLE (VEX_W_0F5B_P_0) },
3705     { VEX_W_TABLE (VEX_W_0F5B_P_1) },
3706     { VEX_W_TABLE (VEX_W_0F5B_P_2) },
3707   },
3708
3709   /* PREFIX_VEX_0F5C */
3710   {
3711     { VEX_W_TABLE (VEX_W_0F5C_P_0) },
3712     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
3713     { VEX_W_TABLE (VEX_W_0F5C_P_2) },
3714     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
3715   },
3716
3717   /* PREFIX_VEX_0F5D */
3718   {
3719     { VEX_W_TABLE (VEX_W_0F5D_P_0) },
3720     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
3721     { VEX_W_TABLE (VEX_W_0F5D_P_2) },
3722     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
3723   },
3724
3725   /* PREFIX_VEX_0F5E */
3726   {
3727     { VEX_W_TABLE (VEX_W_0F5E_P_0) },
3728     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
3729     { VEX_W_TABLE (VEX_W_0F5E_P_2) },
3730     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
3731   },
3732
3733   /* PREFIX_VEX_0F5F */
3734   {
3735     { VEX_W_TABLE (VEX_W_0F5F_P_0) },
3736     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
3737     { VEX_W_TABLE (VEX_W_0F5F_P_2) },
3738     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
3739   },
3740
3741   /* PREFIX_VEX_0F60 */
3742   {
3743     { Bad_Opcode },
3744     { Bad_Opcode },
3745     { VEX_LEN_TABLE (VEX_LEN_0F60_P_2) },
3746   },
3747
3748   /* PREFIX_VEX_0F61 */
3749   {
3750     { Bad_Opcode },
3751     { Bad_Opcode },
3752     { VEX_LEN_TABLE (VEX_LEN_0F61_P_2) },
3753   },
3754
3755   /* PREFIX_VEX_0F62 */
3756   {
3757     { Bad_Opcode },
3758     { Bad_Opcode },
3759     { VEX_LEN_TABLE (VEX_LEN_0F62_P_2) },
3760   },
3761
3762   /* PREFIX_VEX_0F63 */
3763   {
3764     { Bad_Opcode },
3765     { Bad_Opcode },
3766     { VEX_LEN_TABLE (VEX_LEN_0F63_P_2) },
3767   },
3768
3769   /* PREFIX_VEX_0F64 */
3770   {
3771     { Bad_Opcode },
3772     { Bad_Opcode },
3773     { VEX_LEN_TABLE (VEX_LEN_0F64_P_2) },
3774   },
3775
3776   /* PREFIX_VEX_0F65 */
3777   {
3778     { Bad_Opcode },
3779     { Bad_Opcode },
3780     { VEX_LEN_TABLE (VEX_LEN_0F65_P_2) },
3781   },
3782
3783   /* PREFIX_VEX_0F66 */
3784   {
3785     { Bad_Opcode },
3786     { Bad_Opcode },
3787     { VEX_LEN_TABLE (VEX_LEN_0F66_P_2) },
3788   },
3789
3790   /* PREFIX_VEX_0F67 */
3791   {
3792     { Bad_Opcode },
3793     { Bad_Opcode },
3794     { VEX_LEN_TABLE (VEX_LEN_0F67_P_2) },
3795   },
3796
3797   /* PREFIX_VEX_0F68 */
3798   {
3799     { Bad_Opcode },
3800     { Bad_Opcode },
3801     { VEX_LEN_TABLE (VEX_LEN_0F68_P_2) },
3802   },
3803
3804   /* PREFIX_VEX_0F69 */
3805   {
3806     { Bad_Opcode },
3807     { Bad_Opcode },
3808     { VEX_LEN_TABLE (VEX_LEN_0F69_P_2) },
3809   },
3810
3811   /* PREFIX_VEX_0F6A */
3812   {
3813     { Bad_Opcode },
3814     { Bad_Opcode },
3815     { VEX_LEN_TABLE (VEX_LEN_0F6A_P_2) },
3816   },
3817
3818   /* PREFIX_VEX_0F6B */
3819   {
3820     { Bad_Opcode },
3821     { Bad_Opcode },
3822     { VEX_LEN_TABLE (VEX_LEN_0F6B_P_2) },
3823   },
3824
3825   /* PREFIX_VEX_0F6C */
3826   {
3827     { Bad_Opcode },
3828     { Bad_Opcode },
3829     { VEX_LEN_TABLE (VEX_LEN_0F6C_P_2) },
3830   },
3831
3832   /* PREFIX_VEX_0F6D */
3833   {
3834     { Bad_Opcode },
3835     { Bad_Opcode },
3836     { VEX_LEN_TABLE (VEX_LEN_0F6D_P_2) },
3837   },
3838
3839   /* PREFIX_VEX_0F6E */
3840   {
3841     { Bad_Opcode },
3842     { Bad_Opcode },
3843     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
3844   },
3845
3846   /* PREFIX_VEX_0F6F */
3847   {
3848     { Bad_Opcode },
3849     { VEX_W_TABLE (VEX_W_0F6F_P_1) },
3850     { VEX_W_TABLE (VEX_W_0F6F_P_2) },
3851   },
3852
3853   /* PREFIX_VEX_0F70 */
3854   {
3855     { Bad_Opcode },
3856     { VEX_LEN_TABLE (VEX_LEN_0F70_P_1) },
3857     { VEX_LEN_TABLE (VEX_LEN_0F70_P_2) },
3858     { VEX_LEN_TABLE (VEX_LEN_0F70_P_3) },
3859   },
3860
3861   /* PREFIX_VEX_0F71_REG_2 */
3862   {
3863     { Bad_Opcode },
3864     { Bad_Opcode },
3865     { VEX_LEN_TABLE (VEX_LEN_0F71_R_2_P_2) },
3866   },
3867
3868   /* PREFIX_VEX_0F71_REG_4 */
3869   {
3870     { Bad_Opcode },
3871     { Bad_Opcode },
3872     { VEX_LEN_TABLE (VEX_LEN_0F71_R_4_P_2) },
3873   },
3874
3875   /* PREFIX_VEX_0F71_REG_6 */
3876   {
3877     { Bad_Opcode },
3878     { Bad_Opcode },
3879     { VEX_LEN_TABLE (VEX_LEN_0F71_R_6_P_2) },
3880   },
3881
3882   /* PREFIX_VEX_0F72_REG_2 */
3883   {
3884     { Bad_Opcode },
3885     { Bad_Opcode },
3886     { VEX_LEN_TABLE (VEX_LEN_0F72_R_2_P_2) },
3887   },
3888
3889   /* PREFIX_VEX_0F72_REG_4 */
3890   {
3891     { Bad_Opcode },
3892     { Bad_Opcode },
3893     { VEX_LEN_TABLE (VEX_LEN_0F72_R_4_P_2) },
3894   },
3895
3896   /* PREFIX_VEX_0F72_REG_6 */
3897   {
3898     { Bad_Opcode },
3899     { Bad_Opcode },
3900     { VEX_LEN_TABLE (VEX_LEN_0F72_R_6_P_2) },
3901   },
3902
3903   /* PREFIX_VEX_0F73_REG_2 */
3904   {
3905     { Bad_Opcode },
3906     { Bad_Opcode },
3907     { VEX_LEN_TABLE (VEX_LEN_0F73_R_2_P_2) },
3908   },
3909
3910   /* PREFIX_VEX_0F73_REG_3 */
3911   {
3912     { Bad_Opcode },
3913     { Bad_Opcode },
3914     { VEX_LEN_TABLE (VEX_LEN_0F73_R_3_P_2) },
3915   },
3916
3917   /* PREFIX_VEX_0F73_REG_6 */
3918   {
3919     { Bad_Opcode },
3920     { Bad_Opcode },
3921     { VEX_LEN_TABLE (VEX_LEN_0F73_R_6_P_2) },
3922   },
3923
3924   /* PREFIX_VEX_0F73_REG_7 */
3925   {
3926     { Bad_Opcode },
3927     { Bad_Opcode },
3928     { VEX_LEN_TABLE (VEX_LEN_0F73_R_7_P_2) },
3929   },
3930
3931   /* PREFIX_VEX_0F74 */
3932   {
3933     { Bad_Opcode },
3934     { Bad_Opcode },
3935     { VEX_LEN_TABLE (VEX_LEN_0F74_P_2) },
3936   },
3937
3938   /* PREFIX_VEX_0F75 */
3939   {
3940     { Bad_Opcode },
3941     { Bad_Opcode },
3942     { VEX_LEN_TABLE (VEX_LEN_0F75_P_2) },
3943   },
3944
3945   /* PREFIX_VEX_0F76 */
3946   {
3947     { Bad_Opcode },
3948     { Bad_Opcode },
3949     { VEX_LEN_TABLE (VEX_LEN_0F76_P_2) },
3950   },
3951
3952   /* PREFIX_VEX_0F77 */
3953   {
3954     { VEX_W_TABLE (VEX_W_0F77_P_0) },
3955   },
3956
3957   /* PREFIX_VEX_0F7C */
3958   {
3959     { Bad_Opcode },
3960     { Bad_Opcode },
3961     { VEX_W_TABLE (VEX_W_0F7C_P_2) },
3962     { VEX_W_TABLE (VEX_W_0F7C_P_3) },
3963   },
3964
3965   /* PREFIX_VEX_0F7D */
3966   {
3967     { Bad_Opcode },
3968     { Bad_Opcode },
3969     { VEX_W_TABLE (VEX_W_0F7D_P_2) },
3970     { VEX_W_TABLE (VEX_W_0F7D_P_3) },
3971   },
3972
3973   /* PREFIX_VEX_0F7E */
3974   {
3975     { Bad_Opcode },
3976     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
3977     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
3978   },
3979
3980   /* PREFIX_VEX_0F7F */
3981   {
3982     { Bad_Opcode },
3983     { VEX_W_TABLE (VEX_W_0F7F_P_1) },
3984     { VEX_W_TABLE (VEX_W_0F7F_P_2) },
3985   },
3986
3987   /* PREFIX_VEX_0FC2 */
3988   {
3989     { VEX_W_TABLE (VEX_W_0FC2_P_0) },
3990     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
3991     { VEX_W_TABLE (VEX_W_0FC2_P_2) },
3992     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
3993   },
3994
3995   /* PREFIX_VEX_0FC4 */
3996   {
3997     { Bad_Opcode },
3998     { Bad_Opcode },
3999     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
4000   },
4001
4002   /* PREFIX_VEX_0FC5 */
4003   {
4004     { Bad_Opcode },
4005     { Bad_Opcode },
4006     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
4007   },
4008
4009   /* PREFIX_VEX_0FD0 */
4010   {
4011     { Bad_Opcode },
4012     { Bad_Opcode },
4013     { VEX_W_TABLE (VEX_W_0FD0_P_2) },
4014     { VEX_W_TABLE (VEX_W_0FD0_P_3) },
4015   },
4016
4017   /* PREFIX_VEX_0FD1 */
4018   {
4019     { Bad_Opcode },
4020     { Bad_Opcode },
4021     { VEX_LEN_TABLE (VEX_LEN_0FD1_P_2) },
4022   },
4023
4024   /* PREFIX_VEX_0FD2 */
4025   {
4026     { Bad_Opcode },
4027     { Bad_Opcode },
4028     { VEX_LEN_TABLE (VEX_LEN_0FD2_P_2) },
4029   },
4030
4031   /* PREFIX_VEX_0FD3 */
4032   {
4033     { Bad_Opcode },
4034     { Bad_Opcode },
4035     { VEX_LEN_TABLE (VEX_LEN_0FD3_P_2) },
4036   },
4037
4038   /* PREFIX_VEX_0FD4 */
4039   {
4040     { Bad_Opcode },
4041     { Bad_Opcode },
4042     { VEX_LEN_TABLE (VEX_LEN_0FD4_P_2) },
4043   },
4044
4045   /* PREFIX_VEX_0FD5 */
4046   {
4047     { Bad_Opcode },
4048     { Bad_Opcode },
4049     { VEX_LEN_TABLE (VEX_LEN_0FD5_P_2) },
4050   },
4051
4052   /* PREFIX_VEX_0FD6 */
4053   {
4054     { Bad_Opcode },
4055     { Bad_Opcode },
4056     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
4057   },
4058
4059   /* PREFIX_VEX_0FD7 */
4060   {
4061     { Bad_Opcode },
4062     { Bad_Opcode },
4063     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
4064   },
4065
4066   /* PREFIX_VEX_0FD8 */
4067   {
4068     { Bad_Opcode },
4069     { Bad_Opcode },
4070     { VEX_LEN_TABLE (VEX_LEN_0FD8_P_2) },
4071   },
4072
4073   /* PREFIX_VEX_0FD9 */
4074   {
4075     { Bad_Opcode },
4076     { Bad_Opcode },
4077     { VEX_LEN_TABLE (VEX_LEN_0FD9_P_2) },
4078   },
4079
4080   /* PREFIX_VEX_0FDA */
4081   {
4082     { Bad_Opcode },
4083     { Bad_Opcode },
4084     { VEX_LEN_TABLE (VEX_LEN_0FDA_P_2) },
4085   },
4086
4087   /* PREFIX_VEX_0FDB */
4088   {
4089     { Bad_Opcode },
4090     { Bad_Opcode },
4091     { VEX_LEN_TABLE (VEX_LEN_0FDB_P_2) },
4092   },
4093
4094   /* PREFIX_VEX_0FDC */
4095   {
4096     { Bad_Opcode },
4097     { Bad_Opcode },
4098     { VEX_LEN_TABLE (VEX_LEN_0FDC_P_2) },
4099   },
4100
4101   /* PREFIX_VEX_0FDD */
4102   {
4103     { Bad_Opcode },
4104     { Bad_Opcode },
4105     { VEX_LEN_TABLE (VEX_LEN_0FDD_P_2) },
4106   },
4107
4108   /* PREFIX_VEX_0FDE */
4109   {
4110     { Bad_Opcode },
4111     { Bad_Opcode },
4112     { VEX_LEN_TABLE (VEX_LEN_0FDE_P_2) },
4113   },
4114
4115   /* PREFIX_VEX_0FDF */
4116   {
4117     { Bad_Opcode },
4118     { Bad_Opcode },
4119     { VEX_LEN_TABLE (VEX_LEN_0FDF_P_2) },
4120   },
4121
4122   /* PREFIX_VEX_0FE0 */
4123   {
4124     { Bad_Opcode },
4125     { Bad_Opcode },
4126     { VEX_LEN_TABLE (VEX_LEN_0FE0_P_2) },
4127   },
4128
4129   /* PREFIX_VEX_0FE1 */
4130   {
4131     { Bad_Opcode },
4132     { Bad_Opcode },
4133     { VEX_LEN_TABLE (VEX_LEN_0FE1_P_2) },
4134   },
4135
4136   /* PREFIX_VEX_0FE2 */
4137   {
4138     { Bad_Opcode },
4139     { Bad_Opcode },
4140     { VEX_LEN_TABLE (VEX_LEN_0FE2_P_2) },
4141   },
4142
4143   /* PREFIX_VEX_0FE3 */
4144   {
4145     { Bad_Opcode },
4146     { Bad_Opcode },
4147     { VEX_LEN_TABLE (VEX_LEN_0FE3_P_2) },
4148   },
4149
4150   /* PREFIX_VEX_0FE4 */
4151   {
4152     { Bad_Opcode },
4153     { Bad_Opcode },
4154     { VEX_LEN_TABLE (VEX_LEN_0FE4_P_2) },
4155   },
4156
4157   /* PREFIX_VEX_0FE5 */
4158   {
4159     { Bad_Opcode },
4160     { Bad_Opcode },
4161     { VEX_LEN_TABLE (VEX_LEN_0FE5_P_2) },
4162   },
4163
4164   /* PREFIX_VEX_0FE6 */
4165   {
4166     { Bad_Opcode },
4167     { VEX_W_TABLE (VEX_W_0FE6_P_1) },
4168     { VEX_W_TABLE (VEX_W_0FE6_P_2) },
4169     { VEX_W_TABLE (VEX_W_0FE6_P_3) },
4170   },
4171
4172   /* PREFIX_VEX_0FE7 */
4173   {
4174     { Bad_Opcode },
4175     { Bad_Opcode },
4176     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
4177   },
4178
4179   /* PREFIX_VEX_0FE8 */
4180   {
4181     { Bad_Opcode },
4182     { Bad_Opcode },
4183     { VEX_LEN_TABLE (VEX_LEN_0FE8_P_2) },
4184   },
4185
4186   /* PREFIX_VEX_0FE9 */
4187   {
4188     { Bad_Opcode },
4189     { Bad_Opcode },
4190     { VEX_LEN_TABLE (VEX_LEN_0FE9_P_2) },
4191   },
4192
4193   /* PREFIX_VEX_0FEA */
4194   {
4195     { Bad_Opcode },
4196     { Bad_Opcode },
4197     { VEX_LEN_TABLE (VEX_LEN_0FEA_P_2) },
4198   },
4199
4200   /* PREFIX_VEX_0FEB */
4201   {
4202     { Bad_Opcode },
4203     { Bad_Opcode },
4204     { VEX_LEN_TABLE (VEX_LEN_0FEB_P_2) },
4205   },
4206
4207   /* PREFIX_VEX_0FEC */
4208   {
4209     { Bad_Opcode },
4210     { Bad_Opcode },
4211     { VEX_LEN_TABLE (VEX_LEN_0FEC_P_2) },
4212   },
4213
4214   /* PREFIX_VEX_0FED */
4215   {
4216     { Bad_Opcode },
4217     { Bad_Opcode },
4218     { VEX_LEN_TABLE (VEX_LEN_0FED_P_2) },
4219   },
4220
4221   /* PREFIX_VEX_0FEE */
4222   {
4223     { Bad_Opcode },
4224     { Bad_Opcode },
4225     { VEX_LEN_TABLE (VEX_LEN_0FEE_P_2) },
4226   },
4227
4228   /* PREFIX_VEX_0FEF */
4229   {
4230     { Bad_Opcode },
4231     { Bad_Opcode },
4232     { VEX_LEN_TABLE (VEX_LEN_0FEF_P_2) },
4233   },
4234
4235   /* PREFIX_VEX_0FF0 */
4236   {
4237     { Bad_Opcode },
4238     { Bad_Opcode },
4239     { Bad_Opcode },
4240     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
4241   },
4242
4243   /* PREFIX_VEX_0FF1 */
4244   {
4245     { Bad_Opcode },
4246     { Bad_Opcode },
4247     { VEX_LEN_TABLE (VEX_LEN_0FF1_P_2) },
4248   },
4249
4250   /* PREFIX_VEX_0FF2 */
4251   {
4252     { Bad_Opcode },
4253     { Bad_Opcode },
4254     { VEX_LEN_TABLE (VEX_LEN_0FF2_P_2) },
4255   },
4256
4257   /* PREFIX_VEX_0FF3 */
4258   {
4259     { Bad_Opcode },
4260     { Bad_Opcode },
4261     { VEX_LEN_TABLE (VEX_LEN_0FF3_P_2) },
4262   },
4263
4264   /* PREFIX_VEX_0FF4 */
4265   {
4266     { Bad_Opcode },
4267     { Bad_Opcode },
4268     { VEX_LEN_TABLE (VEX_LEN_0FF4_P_2) },
4269   },
4270
4271   /* PREFIX_VEX_0FF5 */
4272   {
4273     { Bad_Opcode },
4274     { Bad_Opcode },
4275     { VEX_LEN_TABLE (VEX_LEN_0FF5_P_2) },
4276   },
4277
4278   /* PREFIX_VEX_0FF6 */
4279   {
4280     { Bad_Opcode },
4281     { Bad_Opcode },
4282     { VEX_LEN_TABLE (VEX_LEN_0FF6_P_2) },
4283   },
4284
4285   /* PREFIX_VEX_0FF7 */
4286   {
4287     { Bad_Opcode },
4288     { Bad_Opcode },
4289     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
4290   },
4291
4292   /* PREFIX_VEX_0FF8 */
4293   {
4294     { Bad_Opcode },
4295     { Bad_Opcode },
4296     { VEX_LEN_TABLE (VEX_LEN_0FF8_P_2) },
4297   },
4298
4299   /* PREFIX_VEX_0FF9 */
4300   {
4301     { Bad_Opcode },
4302     { Bad_Opcode },
4303     { VEX_LEN_TABLE (VEX_LEN_0FF9_P_2) },
4304   },
4305
4306   /* PREFIX_VEX_0FFA */
4307   {
4308     { Bad_Opcode },
4309     { Bad_Opcode },
4310     { VEX_LEN_TABLE (VEX_LEN_0FFA_P_2) },
4311   },
4312
4313   /* PREFIX_VEX_0FFB */
4314   {
4315     { Bad_Opcode },
4316     { Bad_Opcode },
4317     { VEX_LEN_TABLE (VEX_LEN_0FFB_P_2) },
4318   },
4319
4320   /* PREFIX_VEX_0FFC */
4321   {
4322     { Bad_Opcode },
4323     { Bad_Opcode },
4324     { VEX_LEN_TABLE (VEX_LEN_0FFC_P_2) },
4325   },
4326
4327   /* PREFIX_VEX_0FFD */
4328   {
4329     { Bad_Opcode },
4330     { Bad_Opcode },
4331     { VEX_LEN_TABLE (VEX_LEN_0FFD_P_2) },
4332   },
4333
4334   /* PREFIX_VEX_0FFE */
4335   {
4336     { Bad_Opcode },
4337     { Bad_Opcode },
4338     { VEX_LEN_TABLE (VEX_LEN_0FFE_P_2) },
4339   },
4340
4341   /* PREFIX_VEX_0F3800 */
4342   {
4343     { Bad_Opcode },
4344     { Bad_Opcode },
4345     { VEX_LEN_TABLE (VEX_LEN_0F3800_P_2) },
4346   },
4347
4348   /* PREFIX_VEX_0F3801 */
4349   {
4350     { Bad_Opcode },
4351     { Bad_Opcode },
4352     { VEX_LEN_TABLE (VEX_LEN_0F3801_P_2) },
4353   },
4354
4355   /* PREFIX_VEX_0F3802 */
4356   {
4357     { Bad_Opcode },
4358     { Bad_Opcode },
4359     { VEX_LEN_TABLE (VEX_LEN_0F3802_P_2) },
4360   },
4361
4362   /* PREFIX_VEX_0F3803 */
4363   {
4364     { Bad_Opcode },
4365     { Bad_Opcode },
4366     { VEX_LEN_TABLE (VEX_LEN_0F3803_P_2) },
4367   },
4368
4369   /* PREFIX_VEX_0F3804 */
4370   {
4371     { Bad_Opcode },
4372     { Bad_Opcode },
4373     { VEX_LEN_TABLE (VEX_LEN_0F3804_P_2) },
4374   },
4375
4376   /* PREFIX_VEX_0F3805 */
4377   {
4378     { Bad_Opcode },
4379     { Bad_Opcode },
4380     { VEX_LEN_TABLE (VEX_LEN_0F3805_P_2) },
4381   },
4382
4383   /* PREFIX_VEX_0F3806 */
4384   {
4385     { Bad_Opcode },
4386     { Bad_Opcode },
4387     { VEX_LEN_TABLE (VEX_LEN_0F3806_P_2) },
4388   },
4389
4390   /* PREFIX_VEX_0F3807 */
4391   {
4392     { Bad_Opcode },
4393     { Bad_Opcode },
4394     { VEX_LEN_TABLE (VEX_LEN_0F3807_P_2) },
4395   },
4396
4397   /* PREFIX_VEX_0F3808 */
4398   {
4399     { Bad_Opcode },
4400     { Bad_Opcode },
4401     { VEX_LEN_TABLE (VEX_LEN_0F3808_P_2) },
4402   },
4403
4404   /* PREFIX_VEX_0F3809 */
4405   {
4406     { Bad_Opcode },
4407     { Bad_Opcode },
4408     { VEX_LEN_TABLE (VEX_LEN_0F3809_P_2) },
4409   },
4410
4411   /* PREFIX_VEX_0F380A */
4412   {
4413     { Bad_Opcode },
4414     { Bad_Opcode },
4415     { VEX_LEN_TABLE (VEX_LEN_0F380A_P_2) },
4416   },
4417
4418   /* PREFIX_VEX_0F380B */
4419   {
4420     { Bad_Opcode },
4421     { Bad_Opcode },
4422     { VEX_LEN_TABLE (VEX_LEN_0F380B_P_2) },
4423   },
4424
4425   /* PREFIX_VEX_0F380C */
4426   {
4427     { Bad_Opcode },
4428     { Bad_Opcode },
4429     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
4430   },
4431
4432   /* PREFIX_VEX_0F380D */
4433   {
4434     { Bad_Opcode },
4435     { Bad_Opcode },
4436     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
4437   },
4438
4439   /* PREFIX_VEX_0F380E */
4440   {
4441     { Bad_Opcode },
4442     { Bad_Opcode },
4443     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
4444   },
4445
4446   /* PREFIX_VEX_0F380F */
4447   {
4448     { Bad_Opcode },
4449     { Bad_Opcode },
4450     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
4451   },
4452
4453   /* PREFIX_VEX_0F3813 */
4454   {
4455     { Bad_Opcode },
4456     { Bad_Opcode },
4457     { "vcvtph2ps", { XM, EXxmmq } },
4458   },
4459
4460   /* PREFIX_VEX_0F3817 */
4461   {
4462     { Bad_Opcode },
4463     { Bad_Opcode },
4464     { VEX_W_TABLE (VEX_W_0F3817_P_2) },
4465   },
4466
4467   /* PREFIX_VEX_0F3818 */
4468   {
4469     { Bad_Opcode },
4470     { Bad_Opcode },
4471     { MOD_TABLE (MOD_VEX_0F3818_PREFIX_2) },
4472   },
4473
4474   /* PREFIX_VEX_0F3819 */
4475   {
4476     { Bad_Opcode },
4477     { Bad_Opcode },
4478     { MOD_TABLE (MOD_VEX_0F3819_PREFIX_2) },
4479   },
4480
4481   /* PREFIX_VEX_0F381A */
4482   {
4483     { Bad_Opcode },
4484     { Bad_Opcode },
4485     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
4486   },
4487
4488   /* PREFIX_VEX_0F381C */
4489   {
4490     { Bad_Opcode },
4491     { Bad_Opcode },
4492     { VEX_LEN_TABLE (VEX_LEN_0F381C_P_2) },
4493   },
4494
4495   /* PREFIX_VEX_0F381D */
4496   {
4497     { Bad_Opcode },
4498     { Bad_Opcode },
4499     { VEX_LEN_TABLE (VEX_LEN_0F381D_P_2) },
4500   },
4501
4502   /* PREFIX_VEX_0F381E */
4503   {
4504     { Bad_Opcode },
4505     { Bad_Opcode },
4506     { VEX_LEN_TABLE (VEX_LEN_0F381E_P_2) },
4507   },
4508
4509   /* PREFIX_VEX_0F3820 */
4510   {
4511     { Bad_Opcode },
4512     { Bad_Opcode },
4513     { VEX_LEN_TABLE (VEX_LEN_0F3820_P_2) },
4514   },
4515
4516   /* PREFIX_VEX_0F3821 */
4517   {
4518     { Bad_Opcode },
4519     { Bad_Opcode },
4520     { VEX_LEN_TABLE (VEX_LEN_0F3821_P_2) },
4521   },
4522
4523   /* PREFIX_VEX_0F3822 */
4524   {
4525     { Bad_Opcode },
4526     { Bad_Opcode },
4527     { VEX_LEN_TABLE (VEX_LEN_0F3822_P_2) },
4528   },
4529
4530   /* PREFIX_VEX_0F3823 */
4531   {
4532     { Bad_Opcode },
4533     { Bad_Opcode },
4534     { VEX_LEN_TABLE (VEX_LEN_0F3823_P_2) },
4535   },
4536
4537   /* PREFIX_VEX_0F3824 */
4538   {
4539     { Bad_Opcode },
4540     { Bad_Opcode },
4541     { VEX_LEN_TABLE (VEX_LEN_0F3824_P_2) },
4542   },
4543
4544   /* PREFIX_VEX_0F3825 */
4545   {
4546     { Bad_Opcode },
4547     { Bad_Opcode },
4548     { VEX_LEN_TABLE (VEX_LEN_0F3825_P_2) },
4549   },
4550
4551   /* PREFIX_VEX_0F3828 */
4552   {
4553     { Bad_Opcode },
4554     { Bad_Opcode },
4555     { VEX_LEN_TABLE (VEX_LEN_0F3828_P_2) },
4556   },
4557
4558   /* PREFIX_VEX_0F3829 */
4559   {
4560     { Bad_Opcode },
4561     { Bad_Opcode },
4562     { VEX_LEN_TABLE (VEX_LEN_0F3829_P_2) },
4563   },
4564
4565   /* PREFIX_VEX_0F382A */
4566   {
4567     { Bad_Opcode },
4568     { Bad_Opcode },
4569     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
4570   },
4571
4572   /* PREFIX_VEX_0F382B */
4573   {
4574     { Bad_Opcode },
4575     { Bad_Opcode },
4576     { VEX_LEN_TABLE (VEX_LEN_0F382B_P_2) },
4577   },
4578
4579   /* PREFIX_VEX_0F382C */
4580   {
4581     { Bad_Opcode },
4582     { Bad_Opcode },
4583      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
4584   },
4585
4586   /* PREFIX_VEX_0F382D */
4587   {
4588     { Bad_Opcode },
4589     { Bad_Opcode },
4590      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
4591   },
4592
4593   /* PREFIX_VEX_0F382E */
4594   {
4595     { Bad_Opcode },
4596     { Bad_Opcode },
4597      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
4598   },
4599
4600   /* PREFIX_VEX_0F382F */
4601   {
4602     { Bad_Opcode },
4603     { Bad_Opcode },
4604      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
4605   },
4606
4607   /* PREFIX_VEX_0F3830 */
4608   {
4609     { Bad_Opcode },
4610     { Bad_Opcode },
4611     { VEX_LEN_TABLE (VEX_LEN_0F3830_P_2) },
4612   },
4613
4614   /* PREFIX_VEX_0F3831 */
4615   {
4616     { Bad_Opcode },
4617     { Bad_Opcode },
4618     { VEX_LEN_TABLE (VEX_LEN_0F3831_P_2) },
4619   },
4620
4621   /* PREFIX_VEX_0F3832 */
4622   {
4623     { Bad_Opcode },
4624     { Bad_Opcode },
4625     { VEX_LEN_TABLE (VEX_LEN_0F3832_P_2) },
4626   },
4627
4628   /* PREFIX_VEX_0F3833 */
4629   {
4630     { Bad_Opcode },
4631     { Bad_Opcode },
4632     { VEX_LEN_TABLE (VEX_LEN_0F3833_P_2) },
4633   },
4634
4635   /* PREFIX_VEX_0F3834 */
4636   {
4637     { Bad_Opcode },
4638     { Bad_Opcode },
4639     { VEX_LEN_TABLE (VEX_LEN_0F3834_P_2) },
4640   },
4641
4642   /* PREFIX_VEX_0F3835 */
4643   {
4644     { Bad_Opcode },
4645     { Bad_Opcode },
4646     { VEX_LEN_TABLE (VEX_LEN_0F3835_P_2) },
4647   },
4648
4649   /* PREFIX_VEX_0F3837 */
4650   {
4651     { Bad_Opcode },
4652     { Bad_Opcode },
4653     { VEX_LEN_TABLE (VEX_LEN_0F3837_P_2) },
4654   },
4655
4656   /* PREFIX_VEX_0F3838 */
4657   {
4658     { Bad_Opcode },
4659     { Bad_Opcode },
4660     { VEX_LEN_TABLE (VEX_LEN_0F3838_P_2) },
4661   },
4662
4663   /* PREFIX_VEX_0F3839 */
4664   {
4665     { Bad_Opcode },
4666     { Bad_Opcode },
4667     { VEX_LEN_TABLE (VEX_LEN_0F3839_P_2) },
4668   },
4669
4670   /* PREFIX_VEX_0F383A */
4671   {
4672     { Bad_Opcode },
4673     { Bad_Opcode },
4674     { VEX_LEN_TABLE (VEX_LEN_0F383A_P_2) },
4675   },
4676
4677   /* PREFIX_VEX_0F383B */
4678   {
4679     { Bad_Opcode },
4680     { Bad_Opcode },
4681     { VEX_LEN_TABLE (VEX_LEN_0F383B_P_2) },
4682   },
4683
4684   /* PREFIX_VEX_0F383C */
4685   {
4686     { Bad_Opcode },
4687     { Bad_Opcode },
4688     { VEX_LEN_TABLE (VEX_LEN_0F383C_P_2) },
4689   },
4690
4691   /* PREFIX_VEX_0F383D */
4692   {
4693     { Bad_Opcode },
4694     { Bad_Opcode },
4695     { VEX_LEN_TABLE (VEX_LEN_0F383D_P_2) },
4696   },
4697
4698   /* PREFIX_VEX_0F383E */
4699   {
4700     { Bad_Opcode },
4701     { Bad_Opcode },
4702     { VEX_LEN_TABLE (VEX_LEN_0F383E_P_2) },
4703   },
4704
4705   /* PREFIX_VEX_0F383F */
4706   {
4707     { Bad_Opcode },
4708     { Bad_Opcode },
4709     { VEX_LEN_TABLE (VEX_LEN_0F383F_P_2) },
4710   },
4711
4712   /* PREFIX_VEX_0F3840 */
4713   {
4714     { Bad_Opcode },
4715     { Bad_Opcode },
4716     { VEX_LEN_TABLE (VEX_LEN_0F3840_P_2) },
4717   },
4718
4719   /* PREFIX_VEX_0F3841 */
4720   {
4721     { Bad_Opcode },
4722     { Bad_Opcode },
4723     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
4724   },
4725
4726   /* PREFIX_VEX_0F3896 */
4727   {
4728     { Bad_Opcode },
4729     { Bad_Opcode },
4730     { "vfmaddsub132p%XW", { XM, Vex, EXx } },
4731   },
4732
4733   /* PREFIX_VEX_0F3897 */
4734   {
4735     { Bad_Opcode },
4736     { Bad_Opcode },
4737     { "vfmsubadd132p%XW", { XM, Vex, EXx } },
4738   },
4739
4740   /* PREFIX_VEX_0F3898 */
4741   {
4742     { Bad_Opcode },
4743     { Bad_Opcode },
4744     { "vfmadd132p%XW", { XM, Vex, EXx } },
4745   },
4746
4747   /* PREFIX_VEX_0F3899 */
4748   {
4749     { Bad_Opcode },
4750     { Bad_Opcode },
4751     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4752   },
4753
4754   /* PREFIX_VEX_0F389A */
4755   {
4756     { Bad_Opcode },
4757     { Bad_Opcode },
4758     { "vfmsub132p%XW", { XM, Vex, EXx } },
4759   },
4760
4761   /* PREFIX_VEX_0F389B */
4762   {
4763     { Bad_Opcode },
4764     { Bad_Opcode },
4765     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4766   },
4767
4768   /* PREFIX_VEX_0F389C */
4769   {
4770     { Bad_Opcode },
4771     { Bad_Opcode },
4772     { "vfnmadd132p%XW", { XM, Vex, EXx } },
4773   },
4774
4775   /* PREFIX_VEX_0F389D */
4776   {
4777     { Bad_Opcode },
4778     { Bad_Opcode },
4779     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4780   },
4781
4782   /* PREFIX_VEX_0F389E */
4783   {
4784     { Bad_Opcode },
4785     { Bad_Opcode },
4786     { "vfnmsub132p%XW", { XM, Vex, EXx } },
4787   },
4788
4789   /* PREFIX_VEX_0F389F */
4790   {
4791     { Bad_Opcode },
4792     { Bad_Opcode },
4793     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4794   },
4795
4796   /* PREFIX_VEX_0F38A6 */
4797   {
4798     { Bad_Opcode },
4799     { Bad_Opcode },
4800     { "vfmaddsub213p%XW", { XM, Vex, EXx } },
4801     { Bad_Opcode },
4802   },
4803
4804   /* PREFIX_VEX_0F38A7 */
4805   {
4806     { Bad_Opcode },
4807     { Bad_Opcode },
4808     { "vfmsubadd213p%XW", { XM, Vex, EXx } },
4809   },
4810
4811   /* PREFIX_VEX_0F38A8 */
4812   {
4813     { Bad_Opcode },
4814     { Bad_Opcode },
4815     { "vfmadd213p%XW", { XM, Vex, EXx } },
4816   },
4817
4818   /* PREFIX_VEX_0F38A9 */
4819   {
4820     { Bad_Opcode },
4821     { Bad_Opcode },
4822     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4823   },
4824
4825   /* PREFIX_VEX_0F38AA */
4826   {
4827     { Bad_Opcode },
4828     { Bad_Opcode },
4829     { "vfmsub213p%XW", { XM, Vex, EXx } },
4830   },
4831
4832   /* PREFIX_VEX_0F38AB */
4833   {
4834     { Bad_Opcode },
4835     { Bad_Opcode },
4836     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4837   },
4838
4839   /* PREFIX_VEX_0F38AC */
4840   {
4841     { Bad_Opcode },
4842     { Bad_Opcode },
4843     { "vfnmadd213p%XW", { XM, Vex, EXx } },
4844   },
4845
4846   /* PREFIX_VEX_0F38AD */
4847   {
4848     { Bad_Opcode },
4849     { Bad_Opcode },
4850     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4851   },
4852
4853   /* PREFIX_VEX_0F38AE */
4854   {
4855     { Bad_Opcode },
4856     { Bad_Opcode },
4857     { "vfnmsub213p%XW", { XM, Vex, EXx } },
4858   },
4859
4860   /* PREFIX_VEX_0F38AF */
4861   {
4862     { Bad_Opcode },
4863     { Bad_Opcode },
4864     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4865   },
4866
4867   /* PREFIX_VEX_0F38B6 */
4868   {
4869     { Bad_Opcode },
4870     { Bad_Opcode },
4871     { "vfmaddsub231p%XW", { XM, Vex, EXx } },
4872   },
4873
4874   /* PREFIX_VEX_0F38B7 */
4875   {
4876     { Bad_Opcode },
4877     { Bad_Opcode },
4878     { "vfmsubadd231p%XW", { XM, Vex, EXx } },
4879   },
4880
4881   /* PREFIX_VEX_0F38B8 */
4882   {
4883     { Bad_Opcode },
4884     { Bad_Opcode },
4885     { "vfmadd231p%XW", { XM, Vex, EXx } },
4886   },
4887
4888   /* PREFIX_VEX_0F38B9 */
4889   {
4890     { Bad_Opcode },
4891     { Bad_Opcode },
4892     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4893   },
4894
4895   /* PREFIX_VEX_0F38BA */
4896   {
4897     { Bad_Opcode },
4898     { Bad_Opcode },
4899     { "vfmsub231p%XW", { XM, Vex, EXx } },
4900   },
4901
4902   /* PREFIX_VEX_0F38BB */
4903   {
4904     { Bad_Opcode },
4905     { Bad_Opcode },
4906     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4907   },
4908
4909   /* PREFIX_VEX_0F38BC */
4910   {
4911     { Bad_Opcode },
4912     { Bad_Opcode },
4913     { "vfnmadd231p%XW", { XM, Vex, EXx } },
4914   },
4915
4916   /* PREFIX_VEX_0F38BD */
4917   {
4918     { Bad_Opcode },
4919     { Bad_Opcode },
4920     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4921   },
4922
4923   /* PREFIX_VEX_0F38BE */
4924   {
4925     { Bad_Opcode },
4926     { Bad_Opcode },
4927     { "vfnmsub231p%XW", { XM, Vex, EXx } },
4928   },
4929
4930   /* PREFIX_VEX_0F38BF */
4931   {
4932     { Bad_Opcode },
4933     { Bad_Opcode },
4934     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4935   },
4936
4937   /* PREFIX_VEX_0F38DB */
4938   {
4939     { Bad_Opcode },
4940     { Bad_Opcode },
4941     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
4942   },
4943
4944   /* PREFIX_VEX_0F38DC */
4945   {
4946     { Bad_Opcode },
4947     { Bad_Opcode },
4948     { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) },
4949   },
4950
4951   /* PREFIX_VEX_0F38DD */
4952   {
4953     { Bad_Opcode },
4954     { Bad_Opcode },
4955     { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) },
4956   },
4957
4958   /* PREFIX_VEX_0F38DE */
4959   {
4960     { Bad_Opcode },
4961     { Bad_Opcode },
4962     { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) },
4963   },
4964
4965   /* PREFIX_VEX_0F38DF */
4966   {
4967     { Bad_Opcode },
4968     { Bad_Opcode },
4969     { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) },
4970   },
4971
4972   /* PREFIX_VEX_0F3A04 */
4973   {
4974     { Bad_Opcode },
4975     { Bad_Opcode },
4976     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
4977   },
4978
4979   /* PREFIX_VEX_0F3A05 */
4980   {
4981     { Bad_Opcode },
4982     { Bad_Opcode },
4983     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
4984   },
4985
4986   /* PREFIX_VEX_0F3A06 */
4987   {
4988     { Bad_Opcode },
4989     { Bad_Opcode },
4990     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
4991   },
4992
4993   /* PREFIX_VEX_0F3A08 */
4994   {
4995     { Bad_Opcode },
4996     { Bad_Opcode },
4997     { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
4998   },
4999
5000   /* PREFIX_VEX_0F3A09 */
5001   {
5002     { Bad_Opcode },
5003     { Bad_Opcode },
5004     { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
5005   },
5006
5007   /* PREFIX_VEX_0F3A0A */
5008   {
5009     { Bad_Opcode },
5010     { Bad_Opcode },
5011     { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
5012   },
5013
5014   /* PREFIX_VEX_0F3A0B */
5015   {
5016     { Bad_Opcode },
5017     { Bad_Opcode },
5018     { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
5019   },
5020
5021   /* PREFIX_VEX_0F3A0C */
5022   {
5023     { Bad_Opcode },
5024     { Bad_Opcode },
5025     { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
5026   },
5027
5028   /* PREFIX_VEX_0F3A0D */
5029   {
5030     { Bad_Opcode },
5031     { Bad_Opcode },
5032     { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
5033   },
5034
5035   /* PREFIX_VEX_0F3A0E */
5036   {
5037     { Bad_Opcode },
5038     { Bad_Opcode },
5039     { VEX_LEN_TABLE (VEX_LEN_0F3A0E_P_2) },
5040   },
5041
5042   /* PREFIX_VEX_0F3A0F */
5043   {
5044     { Bad_Opcode },
5045     { Bad_Opcode },
5046     { VEX_LEN_TABLE (VEX_LEN_0F3A0F_P_2) },
5047   },
5048
5049   /* PREFIX_VEX_0F3A14 */
5050   {
5051     { Bad_Opcode },
5052     { Bad_Opcode },
5053     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
5054   },
5055
5056   /* PREFIX_VEX_0F3A15 */
5057   {
5058     { Bad_Opcode },
5059     { Bad_Opcode },
5060     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
5061   },
5062
5063   /* PREFIX_VEX_0F3A16 */
5064   {
5065     { Bad_Opcode },
5066     { Bad_Opcode },
5067     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
5068   },
5069
5070   /* PREFIX_VEX_0F3A17 */
5071   {
5072     { Bad_Opcode },
5073     { Bad_Opcode },
5074     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
5075   },
5076
5077   /* PREFIX_VEX_0F3A18 */
5078   {
5079     { Bad_Opcode },
5080     { Bad_Opcode },
5081     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
5082   },
5083
5084   /* PREFIX_VEX_0F3A19 */
5085   {
5086     { Bad_Opcode },
5087     { Bad_Opcode },
5088     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
5089   },
5090
5091   /* PREFIX_VEX_0F3A1D */
5092   {
5093     { Bad_Opcode },
5094     { Bad_Opcode },
5095     { "vcvtps2ph", { EXxmmq, XM, Ib } },
5096   },
5097
5098   /* PREFIX_VEX_0F3A20 */
5099   {
5100     { Bad_Opcode },
5101     { Bad_Opcode },
5102     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
5103   },
5104
5105   /* PREFIX_VEX_0F3A21 */
5106   {
5107     { Bad_Opcode },
5108     { Bad_Opcode },
5109     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
5110   },
5111
5112   /* PREFIX_VEX_0F3A22 */
5113   {
5114     { Bad_Opcode },
5115     { Bad_Opcode },
5116     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
5117   },
5118
5119   /* PREFIX_VEX_0F3A40 */
5120   {
5121     { Bad_Opcode },
5122     { Bad_Opcode },
5123     { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
5124   },
5125
5126   /* PREFIX_VEX_0F3A41 */
5127   {
5128     { Bad_Opcode },
5129     { Bad_Opcode },
5130     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
5131   },
5132
5133   /* PREFIX_VEX_0F3A42 */
5134   {
5135     { Bad_Opcode },
5136     { Bad_Opcode },
5137     { VEX_LEN_TABLE (VEX_LEN_0F3A42_P_2) },
5138   },
5139
5140   /* PREFIX_VEX_0F3A44 */
5141   {
5142     { Bad_Opcode },
5143     { Bad_Opcode },
5144     { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) },
5145   },
5146
5147   /* PREFIX_VEX_0F3A48 */
5148   {
5149     { Bad_Opcode },
5150     { Bad_Opcode },
5151     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
5152   },
5153
5154   /* PREFIX_VEX_0F3A49 */
5155   {
5156     { Bad_Opcode },
5157     { Bad_Opcode },
5158     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
5159   },
5160
5161   /* PREFIX_VEX_0F3A4A */
5162   {
5163     { Bad_Opcode },
5164     { Bad_Opcode },
5165     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
5166   },
5167
5168   /* PREFIX_VEX_0F3A4B */
5169   {
5170     { Bad_Opcode },
5171     { Bad_Opcode },
5172     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
5173   },
5174
5175   /* PREFIX_VEX_0F3A4C */
5176   {
5177     { Bad_Opcode },
5178     { Bad_Opcode },
5179     { VEX_LEN_TABLE (VEX_LEN_0F3A4C_P_2) },
5180   },
5181
5182   /* PREFIX_VEX_0F3A5C */
5183   {
5184     { Bad_Opcode },
5185     { Bad_Opcode },
5186     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5187   },
5188
5189   /* PREFIX_VEX_0F3A5D */
5190   {
5191     { Bad_Opcode },
5192     { Bad_Opcode },
5193     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5194   },
5195
5196   /* PREFIX_VEX_0F3A5E */
5197   {
5198     { Bad_Opcode },
5199     { Bad_Opcode },
5200     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5201   },
5202
5203   /* PREFIX_VEX_0F3A5F */
5204   {
5205     { Bad_Opcode },
5206     { Bad_Opcode },
5207     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5208   },
5209
5210   /* PREFIX_VEX_0F3A60 */
5211   {
5212     { Bad_Opcode },
5213     { Bad_Opcode },
5214     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
5215     { Bad_Opcode },
5216   },
5217
5218   /* PREFIX_VEX_0F3A61 */
5219   {
5220     { Bad_Opcode },
5221     { Bad_Opcode },
5222     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
5223   },
5224
5225   /* PREFIX_VEX_0F3A62 */
5226   {
5227     { Bad_Opcode },
5228     { Bad_Opcode },
5229     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
5230   },
5231
5232   /* PREFIX_VEX_0F3A63 */
5233   {
5234     { Bad_Opcode },
5235     { Bad_Opcode },
5236     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
5237   },
5238
5239   /* PREFIX_VEX_0F3A68 */
5240   {
5241     { Bad_Opcode },
5242     { Bad_Opcode },
5243     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5244   },
5245
5246   /* PREFIX_VEX_0F3A69 */
5247   {
5248     { Bad_Opcode },
5249     { Bad_Opcode },
5250     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5251   },
5252
5253   /* PREFIX_VEX_0F3A6A */
5254   {
5255     { Bad_Opcode },
5256     { Bad_Opcode },
5257     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
5258   },
5259
5260   /* PREFIX_VEX_0F3A6B */
5261   {
5262     { Bad_Opcode },
5263     { Bad_Opcode },
5264     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
5265   },
5266
5267   /* PREFIX_VEX_0F3A6C */
5268   {
5269     { Bad_Opcode },
5270     { Bad_Opcode },
5271     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5272   },
5273
5274   /* PREFIX_VEX_0F3A6D */
5275   {
5276     { Bad_Opcode },
5277     { Bad_Opcode },
5278     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5279   },
5280
5281   /* PREFIX_VEX_0F3A6E */
5282   {
5283     { Bad_Opcode },
5284     { Bad_Opcode },
5285     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
5286   },
5287
5288   /* PREFIX_VEX_0F3A6F */
5289   {
5290     { Bad_Opcode },
5291     { Bad_Opcode },
5292     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
5293   },
5294
5295   /* PREFIX_VEX_0F3A78 */
5296   {
5297     { Bad_Opcode },
5298     { Bad_Opcode },
5299     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5300   },
5301
5302   /* PREFIX_VEX_0F3A79 */
5303   {
5304     { Bad_Opcode },
5305     { Bad_Opcode },
5306     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5307   },
5308
5309   /* PREFIX_VEX_0F3A7A */
5310   {
5311     { Bad_Opcode },
5312     { Bad_Opcode },
5313     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
5314   },
5315
5316   /* PREFIX_VEX_0F3A7B */
5317   {
5318     { Bad_Opcode },
5319     { Bad_Opcode },
5320     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
5321   },
5322
5323   /* PREFIX_VEX_0F3A7C */
5324   {
5325     { Bad_Opcode },
5326     { Bad_Opcode },
5327     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5328     { Bad_Opcode },
5329   },
5330
5331   /* PREFIX_VEX_0F3A7D */
5332   {
5333     { Bad_Opcode },
5334     { Bad_Opcode },
5335     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5336   },
5337
5338   /* PREFIX_VEX_0F3A7E */
5339   {
5340     { Bad_Opcode },
5341     { Bad_Opcode },
5342     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
5343   },
5344
5345   /* PREFIX_VEX_0F3A7F */
5346   {
5347     { Bad_Opcode },
5348     { Bad_Opcode },
5349     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
5350   },
5351
5352   /* PREFIX_VEX_0F3ADF */
5353   {
5354     { Bad_Opcode },
5355     { Bad_Opcode },
5356     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
5357   },
5358 };
5359
5360 static const struct dis386 x86_64_table[][2] = {
5361   /* X86_64_06 */
5362   {
5363     { "pushP", { es } },
5364   },
5365
5366   /* X86_64_07 */
5367   {
5368     { "popP", { es } },
5369   },
5370
5371   /* X86_64_0D */
5372   {
5373     { "pushP", { cs } },
5374   },
5375
5376   /* X86_64_16 */
5377   {
5378     { "pushP", { ss } },
5379   },
5380
5381   /* X86_64_17 */
5382   {
5383     { "popP", { ss } },
5384   },
5385
5386   /* X86_64_1E */
5387   {
5388     { "pushP", { ds } },
5389   },
5390
5391   /* X86_64_1F */
5392   {
5393     { "popP", { ds } },
5394   },
5395
5396   /* X86_64_27 */
5397   {
5398     { "daa", { XX } },
5399   },
5400
5401   /* X86_64_2F */
5402   {
5403     { "das", { XX } },
5404   },
5405
5406   /* X86_64_37 */
5407   {
5408     { "aaa", { XX } },
5409   },
5410
5411   /* X86_64_3F */
5412   {
5413     { "aas", { XX } },
5414   },
5415
5416   /* X86_64_60 */
5417   {
5418     { "pushaP", { XX } },
5419   },
5420
5421   /* X86_64_61 */
5422   {
5423     { "popaP", { XX } },
5424   },
5425
5426   /* X86_64_62 */
5427   {
5428     { MOD_TABLE (MOD_62_32BIT) },
5429   },
5430
5431   /* X86_64_63 */
5432   {
5433     { "arpl", { Ew, Gw } },
5434     { "movs{lq|xd}", { Gv, Ed } },
5435   },
5436
5437   /* X86_64_6D */
5438   {
5439     { "ins{R|}", { Yzr, indirDX } },
5440     { "ins{G|}", { Yzr, indirDX } },
5441   },
5442
5443   /* X86_64_6F */
5444   {
5445     { "outs{R|}", { indirDXr, Xz } },
5446     { "outs{G|}", { indirDXr, Xz } },
5447   },
5448
5449   /* X86_64_9A */
5450   {
5451     { "Jcall{T|}", { Ap } },
5452   },
5453
5454   /* X86_64_C4 */
5455   {
5456     { MOD_TABLE (MOD_C4_32BIT) },
5457     { VEX_C4_TABLE (VEX_0F) },
5458   },
5459
5460   /* X86_64_C5 */
5461   {
5462     { MOD_TABLE (MOD_C5_32BIT) },
5463     { VEX_C5_TABLE (VEX_0F) },
5464   },
5465
5466   /* X86_64_CE */
5467   {
5468     { "into", { XX } },
5469   },
5470
5471   /* X86_64_D4 */
5472   {
5473     { "aam", { sIb } },
5474   },
5475
5476   /* X86_64_D5 */
5477   {
5478     { "aad", { sIb } },
5479   },
5480
5481   /* X86_64_EA */
5482   {
5483     { "Jjmp{T|}", { Ap } },
5484   },
5485
5486   /* X86_64_0F01_REG_0 */
5487   {
5488     { "sgdt{Q|IQ}", { M } },
5489     { "sgdt", { M } },
5490   },
5491
5492   /* X86_64_0F01_REG_1 */
5493   {
5494     { "sidt{Q|IQ}", { M } },
5495     { "sidt", { M } },
5496   },
5497
5498   /* X86_64_0F01_REG_2 */
5499   {
5500     { "lgdt{Q|Q}", { M } },
5501     { "lgdt", { M } },
5502   },
5503
5504   /* X86_64_0F01_REG_3 */
5505   {
5506     { "lidt{Q|Q}", { M } },
5507     { "lidt", { M } },
5508   },
5509 };
5510
5511 static const struct dis386 three_byte_table[][256] = {
5512
5513   /* THREE_BYTE_0F38 */
5514   {
5515     /* 00 */
5516     { "pshufb",         { MX, EM } },
5517     { "phaddw",         { MX, EM } },
5518     { "phaddd",         { MX, EM } },
5519     { "phaddsw",        { MX, EM } },
5520     { "pmaddubsw",      { MX, EM } },
5521     { "phsubw",         { MX, EM } },
5522     { "phsubd",         { MX, EM } },
5523     { "phsubsw",        { MX, EM } },
5524     /* 08 */
5525     { "psignb",         { MX, EM } },
5526     { "psignw",         { MX, EM } },
5527     { "psignd",         { MX, EM } },
5528     { "pmulhrsw",       { MX, EM } },
5529     { Bad_Opcode },
5530     { Bad_Opcode },
5531     { Bad_Opcode },
5532     { Bad_Opcode },
5533     /* 10 */
5534     { PREFIX_TABLE (PREFIX_0F3810) },
5535     { Bad_Opcode },
5536     { Bad_Opcode },
5537     { Bad_Opcode },
5538     { PREFIX_TABLE (PREFIX_0F3814) },
5539     { PREFIX_TABLE (PREFIX_0F3815) },
5540     { Bad_Opcode },
5541     { PREFIX_TABLE (PREFIX_0F3817) },
5542     /* 18 */
5543     { Bad_Opcode },
5544     { Bad_Opcode },
5545     { Bad_Opcode },
5546     { Bad_Opcode },
5547     { "pabsb",          { MX, EM } },
5548     { "pabsw",          { MX, EM } },
5549     { "pabsd",          { MX, EM } },
5550     { Bad_Opcode },
5551     /* 20 */
5552     { PREFIX_TABLE (PREFIX_0F3820) },
5553     { PREFIX_TABLE (PREFIX_0F3821) },
5554     { PREFIX_TABLE (PREFIX_0F3822) },
5555     { PREFIX_TABLE (PREFIX_0F3823) },
5556     { PREFIX_TABLE (PREFIX_0F3824) },
5557     { PREFIX_TABLE (PREFIX_0F3825) },
5558     { Bad_Opcode },
5559     { Bad_Opcode },
5560     /* 28 */
5561     { PREFIX_TABLE (PREFIX_0F3828) },
5562     { PREFIX_TABLE (PREFIX_0F3829) },
5563     { PREFIX_TABLE (PREFIX_0F382A) },
5564     { PREFIX_TABLE (PREFIX_0F382B) },
5565     { Bad_Opcode },
5566     { Bad_Opcode },
5567     { Bad_Opcode },
5568     { Bad_Opcode },
5569     /* 30 */
5570     { PREFIX_TABLE (PREFIX_0F3830) },
5571     { PREFIX_TABLE (PREFIX_0F3831) },
5572     { PREFIX_TABLE (PREFIX_0F3832) },
5573     { PREFIX_TABLE (PREFIX_0F3833) },
5574     { PREFIX_TABLE (PREFIX_0F3834) },
5575     { PREFIX_TABLE (PREFIX_0F3835) },
5576     { Bad_Opcode },
5577     { PREFIX_TABLE (PREFIX_0F3837) },
5578     /* 38 */
5579     { PREFIX_TABLE (PREFIX_0F3838) },
5580     { PREFIX_TABLE (PREFIX_0F3839) },
5581     { PREFIX_TABLE (PREFIX_0F383A) },
5582     { PREFIX_TABLE (PREFIX_0F383B) },
5583     { PREFIX_TABLE (PREFIX_0F383C) },
5584     { PREFIX_TABLE (PREFIX_0F383D) },
5585     { PREFIX_TABLE (PREFIX_0F383E) },
5586     { PREFIX_TABLE (PREFIX_0F383F) },
5587     /* 40 */
5588     { PREFIX_TABLE (PREFIX_0F3840) },
5589     { PREFIX_TABLE (PREFIX_0F3841) },
5590     { Bad_Opcode },
5591     { Bad_Opcode },
5592     { Bad_Opcode },
5593     { Bad_Opcode },
5594     { Bad_Opcode },
5595     { Bad_Opcode },
5596     /* 48 */
5597     { Bad_Opcode },
5598     { Bad_Opcode },
5599     { Bad_Opcode },
5600     { Bad_Opcode },
5601     { Bad_Opcode },
5602     { Bad_Opcode },
5603     { Bad_Opcode },
5604     { Bad_Opcode },
5605     /* 50 */
5606     { Bad_Opcode },
5607     { Bad_Opcode },
5608     { Bad_Opcode },
5609     { Bad_Opcode },
5610     { Bad_Opcode },
5611     { Bad_Opcode },
5612     { Bad_Opcode },
5613     { Bad_Opcode },
5614     /* 58 */
5615     { Bad_Opcode },
5616     { Bad_Opcode },
5617     { Bad_Opcode },
5618     { Bad_Opcode },
5619     { Bad_Opcode },
5620     { Bad_Opcode },
5621     { Bad_Opcode },
5622     { Bad_Opcode },
5623     /* 60 */
5624     { Bad_Opcode },
5625     { Bad_Opcode },
5626     { Bad_Opcode },
5627     { Bad_Opcode },
5628     { Bad_Opcode },
5629     { Bad_Opcode },
5630     { Bad_Opcode },
5631     { Bad_Opcode },
5632     /* 68 */
5633     { Bad_Opcode },
5634     { Bad_Opcode },
5635     { Bad_Opcode },
5636     { Bad_Opcode },
5637     { Bad_Opcode },
5638     { Bad_Opcode },
5639     { Bad_Opcode },
5640     { Bad_Opcode },
5641     /* 70 */
5642     { Bad_Opcode },
5643     { Bad_Opcode },
5644     { Bad_Opcode },
5645     { Bad_Opcode },
5646     { Bad_Opcode },
5647     { Bad_Opcode },
5648     { Bad_Opcode },
5649     { Bad_Opcode },
5650     /* 78 */
5651     { Bad_Opcode },
5652     { Bad_Opcode },
5653     { Bad_Opcode },
5654     { Bad_Opcode },
5655     { Bad_Opcode },
5656     { Bad_Opcode },
5657     { Bad_Opcode },
5658     { Bad_Opcode },
5659     /* 80 */
5660     { PREFIX_TABLE (PREFIX_0F3880) },
5661     { PREFIX_TABLE (PREFIX_0F3881) },
5662     { Bad_Opcode },
5663     { Bad_Opcode },
5664     { Bad_Opcode },
5665     { Bad_Opcode },
5666     { Bad_Opcode },
5667     { Bad_Opcode },
5668     /* 88 */
5669     { Bad_Opcode },
5670     { Bad_Opcode },
5671     { Bad_Opcode },
5672     { Bad_Opcode },
5673     { Bad_Opcode },
5674     { Bad_Opcode },
5675     { Bad_Opcode },
5676     { Bad_Opcode },
5677     /* 90 */
5678     { Bad_Opcode },
5679     { Bad_Opcode },
5680     { Bad_Opcode },
5681     { Bad_Opcode },
5682     { Bad_Opcode },
5683     { Bad_Opcode },
5684     { Bad_Opcode },
5685     { Bad_Opcode },
5686     /* 98 */
5687     { Bad_Opcode },
5688     { Bad_Opcode },
5689     { Bad_Opcode },
5690     { Bad_Opcode },
5691     { Bad_Opcode },
5692     { Bad_Opcode },
5693     { Bad_Opcode },
5694     { Bad_Opcode },
5695     /* a0 */
5696     { Bad_Opcode },
5697     { Bad_Opcode },
5698     { Bad_Opcode },
5699     { Bad_Opcode },
5700     { Bad_Opcode },
5701     { Bad_Opcode },
5702     { Bad_Opcode },
5703     { Bad_Opcode },
5704     /* a8 */
5705     { Bad_Opcode },
5706     { Bad_Opcode },
5707     { Bad_Opcode },
5708     { Bad_Opcode },
5709     { Bad_Opcode },
5710     { Bad_Opcode },
5711     { Bad_Opcode },
5712     { Bad_Opcode },
5713     /* b0 */
5714     { Bad_Opcode },
5715     { Bad_Opcode },
5716     { Bad_Opcode },
5717     { Bad_Opcode },
5718     { Bad_Opcode },
5719     { Bad_Opcode },
5720     { Bad_Opcode },
5721     { Bad_Opcode },
5722     /* b8 */
5723     { Bad_Opcode },
5724     { Bad_Opcode },
5725     { Bad_Opcode },
5726     { Bad_Opcode },
5727     { Bad_Opcode },
5728     { Bad_Opcode },
5729     { Bad_Opcode },
5730     { Bad_Opcode },
5731     /* c0 */
5732     { Bad_Opcode },
5733     { Bad_Opcode },
5734     { Bad_Opcode },
5735     { Bad_Opcode },
5736     { Bad_Opcode },
5737     { Bad_Opcode },
5738     { Bad_Opcode },
5739     { Bad_Opcode },
5740     /* c8 */
5741     { Bad_Opcode },
5742     { Bad_Opcode },
5743     { Bad_Opcode },
5744     { Bad_Opcode },
5745     { Bad_Opcode },
5746     { Bad_Opcode },
5747     { Bad_Opcode },
5748     { Bad_Opcode },
5749     /* d0 */
5750     { Bad_Opcode },
5751     { Bad_Opcode },
5752     { Bad_Opcode },
5753     { Bad_Opcode },
5754     { Bad_Opcode },
5755     { Bad_Opcode },
5756     { Bad_Opcode },
5757     { Bad_Opcode },
5758     /* d8 */
5759     { Bad_Opcode },
5760     { Bad_Opcode },
5761     { Bad_Opcode },
5762     { PREFIX_TABLE (PREFIX_0F38DB) },
5763     { PREFIX_TABLE (PREFIX_0F38DC) },
5764     { PREFIX_TABLE (PREFIX_0F38DD) },
5765     { PREFIX_TABLE (PREFIX_0F38DE) },
5766     { PREFIX_TABLE (PREFIX_0F38DF) },
5767     /* e0 */
5768     { Bad_Opcode },
5769     { Bad_Opcode },
5770     { Bad_Opcode },
5771     { Bad_Opcode },
5772     { Bad_Opcode },
5773     { Bad_Opcode },
5774     { Bad_Opcode },
5775     { Bad_Opcode },
5776     /* e8 */
5777     { Bad_Opcode },
5778     { Bad_Opcode },
5779     { Bad_Opcode },
5780     { Bad_Opcode },
5781     { Bad_Opcode },
5782     { Bad_Opcode },
5783     { Bad_Opcode },
5784     { Bad_Opcode },
5785     /* f0 */
5786     { PREFIX_TABLE (PREFIX_0F38F0) },
5787     { PREFIX_TABLE (PREFIX_0F38F1) },
5788     { Bad_Opcode },
5789     { Bad_Opcode },
5790     { Bad_Opcode },
5791     { Bad_Opcode },
5792     { Bad_Opcode },
5793     { Bad_Opcode },
5794     /* f8 */
5795     { Bad_Opcode },
5796     { Bad_Opcode },
5797     { Bad_Opcode },
5798     { Bad_Opcode },
5799     { Bad_Opcode },
5800     { Bad_Opcode },
5801     { Bad_Opcode },
5802     { Bad_Opcode },
5803   },
5804   /* THREE_BYTE_0F3A */
5805   {
5806     /* 00 */
5807     { Bad_Opcode },
5808     { Bad_Opcode },
5809     { Bad_Opcode },
5810     { Bad_Opcode },
5811     { Bad_Opcode },
5812     { Bad_Opcode },
5813     { Bad_Opcode },
5814     { Bad_Opcode },
5815     /* 08 */
5816     { PREFIX_TABLE (PREFIX_0F3A08) },
5817     { PREFIX_TABLE (PREFIX_0F3A09) },
5818     { PREFIX_TABLE (PREFIX_0F3A0A) },
5819     { PREFIX_TABLE (PREFIX_0F3A0B) },
5820     { PREFIX_TABLE (PREFIX_0F3A0C) },
5821     { PREFIX_TABLE (PREFIX_0F3A0D) },
5822     { PREFIX_TABLE (PREFIX_0F3A0E) },
5823     { "palignr",        { MX, EM, Ib } },
5824     /* 10 */
5825     { Bad_Opcode },
5826     { Bad_Opcode },
5827     { Bad_Opcode },
5828     { Bad_Opcode },
5829     { PREFIX_TABLE (PREFIX_0F3A14) },
5830     { PREFIX_TABLE (PREFIX_0F3A15) },
5831     { PREFIX_TABLE (PREFIX_0F3A16) },
5832     { PREFIX_TABLE (PREFIX_0F3A17) },
5833     /* 18 */
5834     { Bad_Opcode },
5835     { Bad_Opcode },
5836     { Bad_Opcode },
5837     { Bad_Opcode },
5838     { Bad_Opcode },
5839     { Bad_Opcode },
5840     { Bad_Opcode },
5841     { Bad_Opcode },
5842     /* 20 */
5843     { PREFIX_TABLE (PREFIX_0F3A20) },
5844     { PREFIX_TABLE (PREFIX_0F3A21) },
5845     { PREFIX_TABLE (PREFIX_0F3A22) },
5846     { Bad_Opcode },
5847     { Bad_Opcode },
5848     { Bad_Opcode },
5849     { Bad_Opcode },
5850     { Bad_Opcode },
5851     /* 28 */
5852     { Bad_Opcode },
5853     { Bad_Opcode },
5854     { Bad_Opcode },
5855     { Bad_Opcode },
5856     { Bad_Opcode },
5857     { Bad_Opcode },
5858     { Bad_Opcode },
5859     { Bad_Opcode },
5860     /* 30 */
5861     { Bad_Opcode },
5862     { Bad_Opcode },
5863     { Bad_Opcode },
5864     { Bad_Opcode },
5865     { Bad_Opcode },
5866     { Bad_Opcode },
5867     { Bad_Opcode },
5868     { Bad_Opcode },
5869     /* 38 */
5870     { Bad_Opcode },
5871     { Bad_Opcode },
5872     { Bad_Opcode },
5873     { Bad_Opcode },
5874     { Bad_Opcode },
5875     { Bad_Opcode },
5876     { Bad_Opcode },
5877     { Bad_Opcode },
5878     /* 40 */
5879     { PREFIX_TABLE (PREFIX_0F3A40) },
5880     { PREFIX_TABLE (PREFIX_0F3A41) },
5881     { PREFIX_TABLE (PREFIX_0F3A42) },
5882     { Bad_Opcode },
5883     { PREFIX_TABLE (PREFIX_0F3A44) },
5884     { Bad_Opcode },
5885     { Bad_Opcode },
5886     { Bad_Opcode },
5887     /* 48 */
5888     { Bad_Opcode },
5889     { Bad_Opcode },
5890     { Bad_Opcode },
5891     { Bad_Opcode },
5892     { Bad_Opcode },
5893     { Bad_Opcode },
5894     { Bad_Opcode },
5895     { Bad_Opcode },
5896     /* 50 */
5897     { Bad_Opcode },
5898     { Bad_Opcode },
5899     { Bad_Opcode },
5900     { Bad_Opcode },
5901     { Bad_Opcode },
5902     { Bad_Opcode },
5903     { Bad_Opcode },
5904     { Bad_Opcode },
5905     /* 58 */
5906     { Bad_Opcode },
5907     { Bad_Opcode },
5908     { Bad_Opcode },
5909     { Bad_Opcode },
5910     { Bad_Opcode },
5911     { Bad_Opcode },
5912     { Bad_Opcode },
5913     { Bad_Opcode },
5914     /* 60 */
5915     { PREFIX_TABLE (PREFIX_0F3A60) },
5916     { PREFIX_TABLE (PREFIX_0F3A61) },
5917     { PREFIX_TABLE (PREFIX_0F3A62) },
5918     { PREFIX_TABLE (PREFIX_0F3A63) },
5919     { Bad_Opcode },
5920     { Bad_Opcode },
5921     { Bad_Opcode },
5922     { Bad_Opcode },
5923     /* 68 */
5924     { Bad_Opcode },
5925     { Bad_Opcode },
5926     { Bad_Opcode },
5927     { Bad_Opcode },
5928     { Bad_Opcode },
5929     { Bad_Opcode },
5930     { Bad_Opcode },
5931     { Bad_Opcode },
5932     /* 70 */
5933     { Bad_Opcode },
5934     { Bad_Opcode },
5935     { Bad_Opcode },
5936     { Bad_Opcode },
5937     { Bad_Opcode },
5938     { Bad_Opcode },
5939     { Bad_Opcode },
5940     { Bad_Opcode },
5941     /* 78 */
5942     { Bad_Opcode },
5943     { Bad_Opcode },
5944     { Bad_Opcode },
5945     { Bad_Opcode },
5946     { Bad_Opcode },
5947     { Bad_Opcode },
5948     { Bad_Opcode },
5949     { Bad_Opcode },
5950     /* 80 */
5951     { Bad_Opcode },
5952     { Bad_Opcode },
5953     { Bad_Opcode },
5954     { Bad_Opcode },
5955     { Bad_Opcode },
5956     { Bad_Opcode },
5957     { Bad_Opcode },
5958     { Bad_Opcode },
5959     /* 88 */
5960     { Bad_Opcode },
5961     { Bad_Opcode },
5962     { Bad_Opcode },
5963     { Bad_Opcode },
5964     { Bad_Opcode },
5965     { Bad_Opcode },
5966     { Bad_Opcode },
5967     { Bad_Opcode },
5968     /* 90 */
5969     { Bad_Opcode },
5970     { Bad_Opcode },
5971     { Bad_Opcode },
5972     { Bad_Opcode },
5973     { Bad_Opcode },
5974     { Bad_Opcode },
5975     { Bad_Opcode },
5976     { Bad_Opcode },
5977     /* 98 */
5978     { Bad_Opcode },
5979     { Bad_Opcode },
5980     { Bad_Opcode },
5981     { Bad_Opcode },
5982     { Bad_Opcode },
5983     { Bad_Opcode },
5984     { Bad_Opcode },
5985     { Bad_Opcode },
5986     /* a0 */
5987     { Bad_Opcode },
5988     { Bad_Opcode },
5989     { Bad_Opcode },
5990     { Bad_Opcode },
5991     { Bad_Opcode },
5992     { Bad_Opcode },
5993     { Bad_Opcode },
5994     { Bad_Opcode },
5995     /* a8 */
5996     { Bad_Opcode },
5997     { Bad_Opcode },
5998     { Bad_Opcode },
5999     { Bad_Opcode },
6000     { Bad_Opcode },
6001     { Bad_Opcode },
6002     { Bad_Opcode },
6003     { Bad_Opcode },
6004     /* b0 */
6005     { Bad_Opcode },
6006     { Bad_Opcode },
6007     { Bad_Opcode },
6008     { Bad_Opcode },
6009     { Bad_Opcode },
6010     { Bad_Opcode },
6011     { Bad_Opcode },
6012     { Bad_Opcode },
6013     /* b8 */
6014     { Bad_Opcode },
6015     { Bad_Opcode },
6016     { Bad_Opcode },
6017     { Bad_Opcode },
6018     { Bad_Opcode },
6019     { Bad_Opcode },
6020     { Bad_Opcode },
6021     { Bad_Opcode },
6022     /* c0 */
6023     { Bad_Opcode },
6024     { Bad_Opcode },
6025     { Bad_Opcode },
6026     { Bad_Opcode },
6027     { Bad_Opcode },
6028     { Bad_Opcode },
6029     { Bad_Opcode },
6030     { Bad_Opcode },
6031     /* c8 */
6032     { Bad_Opcode },
6033     { Bad_Opcode },
6034     { Bad_Opcode },
6035     { Bad_Opcode },
6036     { Bad_Opcode },
6037     { Bad_Opcode },
6038     { Bad_Opcode },
6039     { Bad_Opcode },
6040     /* d0 */
6041     { Bad_Opcode },
6042     { Bad_Opcode },
6043     { Bad_Opcode },
6044     { Bad_Opcode },
6045     { Bad_Opcode },
6046     { Bad_Opcode },
6047     { Bad_Opcode },
6048     { Bad_Opcode },
6049     /* d8 */
6050     { Bad_Opcode },
6051     { Bad_Opcode },
6052     { Bad_Opcode },
6053     { Bad_Opcode },
6054     { Bad_Opcode },
6055     { Bad_Opcode },
6056     { Bad_Opcode },
6057     { PREFIX_TABLE (PREFIX_0F3ADF) },
6058     /* e0 */
6059     { Bad_Opcode },
6060     { Bad_Opcode },
6061     { Bad_Opcode },
6062     { Bad_Opcode },
6063     { Bad_Opcode },
6064     { Bad_Opcode },
6065     { Bad_Opcode },
6066     { Bad_Opcode },
6067     /* e8 */
6068     { Bad_Opcode },
6069     { Bad_Opcode },
6070     { Bad_Opcode },
6071     { Bad_Opcode },
6072     { Bad_Opcode },
6073     { Bad_Opcode },
6074     { Bad_Opcode },
6075     { Bad_Opcode },
6076     /* f0 */
6077     { Bad_Opcode },
6078     { Bad_Opcode },
6079     { Bad_Opcode },
6080     { Bad_Opcode },
6081     { Bad_Opcode },
6082     { Bad_Opcode },
6083     { Bad_Opcode },
6084     { Bad_Opcode },
6085     /* f8 */
6086     { Bad_Opcode },
6087     { Bad_Opcode },
6088     { Bad_Opcode },
6089     { Bad_Opcode },
6090     { Bad_Opcode },
6091     { Bad_Opcode },
6092     { Bad_Opcode },
6093     { Bad_Opcode },
6094   },
6095
6096   /* THREE_BYTE_0F7A */
6097   {
6098     /* 00 */
6099     { Bad_Opcode },
6100     { Bad_Opcode },
6101     { Bad_Opcode },
6102     { Bad_Opcode },
6103     { Bad_Opcode },
6104     { Bad_Opcode },
6105     { Bad_Opcode },
6106     { Bad_Opcode },
6107     /* 08 */
6108     { Bad_Opcode },
6109     { Bad_Opcode },
6110     { Bad_Opcode },
6111     { Bad_Opcode },
6112     { Bad_Opcode },
6113     { Bad_Opcode },
6114     { Bad_Opcode },
6115     { Bad_Opcode },
6116     /* 10 */
6117     { Bad_Opcode },
6118     { Bad_Opcode },
6119     { Bad_Opcode },
6120     { Bad_Opcode },
6121     { Bad_Opcode },
6122     { Bad_Opcode },
6123     { Bad_Opcode },
6124     { Bad_Opcode },
6125     /* 18 */
6126     { Bad_Opcode },
6127     { Bad_Opcode },
6128     { Bad_Opcode },
6129     { Bad_Opcode },
6130     { Bad_Opcode },
6131     { Bad_Opcode },
6132     { Bad_Opcode },
6133     { Bad_Opcode },
6134     /* 20 */
6135     { "ptest",          { XX } },
6136     { Bad_Opcode },
6137     { Bad_Opcode },
6138     { Bad_Opcode },
6139     { Bad_Opcode },
6140     { Bad_Opcode },
6141     { Bad_Opcode },
6142     { Bad_Opcode },
6143     /* 28 */
6144     { Bad_Opcode },
6145     { Bad_Opcode },
6146     { Bad_Opcode },
6147     { Bad_Opcode },
6148     { Bad_Opcode },
6149     { Bad_Opcode },
6150     { Bad_Opcode },
6151     { Bad_Opcode },
6152     /* 30 */
6153     { Bad_Opcode },
6154     { Bad_Opcode },
6155     { Bad_Opcode },
6156     { Bad_Opcode },
6157     { Bad_Opcode },
6158     { Bad_Opcode },
6159     { Bad_Opcode },
6160     { Bad_Opcode },
6161     /* 38 */
6162     { Bad_Opcode },
6163     { Bad_Opcode },
6164     { Bad_Opcode },
6165     { Bad_Opcode },
6166     { Bad_Opcode },
6167     { Bad_Opcode },
6168     { Bad_Opcode },
6169     { Bad_Opcode },
6170     /* 40 */
6171     { Bad_Opcode },
6172     { "phaddbw",        { XM, EXq } },
6173     { "phaddbd",        { XM, EXq } },
6174     { "phaddbq",        { XM, EXq } },
6175     { Bad_Opcode },
6176     { Bad_Opcode },
6177     { "phaddwd",        { XM, EXq } },
6178     { "phaddwq",        { XM, EXq } },
6179     /* 48 */
6180     { Bad_Opcode },
6181     { Bad_Opcode },
6182     { Bad_Opcode },
6183     { "phadddq",        { XM, EXq } },
6184     { Bad_Opcode },
6185     { Bad_Opcode },
6186     { Bad_Opcode },
6187     { Bad_Opcode },
6188     /* 50 */
6189     { Bad_Opcode },
6190     { "phaddubw",       { XM, EXq } },
6191     { "phaddubd",       { XM, EXq } },
6192     { "phaddubq",       { XM, EXq } },
6193     { Bad_Opcode },
6194     { Bad_Opcode },
6195     { "phadduwd",       { XM, EXq } },
6196     { "phadduwq",       { XM, EXq } },
6197     /* 58 */
6198     { Bad_Opcode },
6199     { Bad_Opcode },
6200     { Bad_Opcode },
6201     { "phaddudq",       { XM, EXq } },
6202     { Bad_Opcode },
6203     { Bad_Opcode },
6204     { Bad_Opcode },
6205     { Bad_Opcode },
6206     /* 60 */
6207     { Bad_Opcode },
6208     { "phsubbw",        { XM, EXq } },
6209     { "phsubbd",        { XM, EXq } },
6210     { "phsubbq",        { XM, EXq } },
6211     { Bad_Opcode },
6212     { Bad_Opcode },
6213     { Bad_Opcode },
6214     { Bad_Opcode },
6215     /* 68 */
6216     { Bad_Opcode },
6217     { Bad_Opcode },
6218     { Bad_Opcode },
6219     { Bad_Opcode },
6220     { Bad_Opcode },
6221     { Bad_Opcode },
6222     { Bad_Opcode },
6223     { Bad_Opcode },
6224     /* 70 */
6225     { Bad_Opcode },
6226     { Bad_Opcode },
6227     { Bad_Opcode },
6228     { Bad_Opcode },
6229     { Bad_Opcode },
6230     { Bad_Opcode },
6231     { Bad_Opcode },
6232     { Bad_Opcode },
6233     /* 78 */
6234     { Bad_Opcode },
6235     { Bad_Opcode },
6236     { Bad_Opcode },
6237     { Bad_Opcode },
6238     { Bad_Opcode },
6239     { Bad_Opcode },
6240     { Bad_Opcode },
6241     { Bad_Opcode },
6242     /* 80 */
6243     { Bad_Opcode },
6244     { Bad_Opcode },
6245     { Bad_Opcode },
6246     { Bad_Opcode },
6247     { Bad_Opcode },
6248     { Bad_Opcode },
6249     { Bad_Opcode },
6250     { Bad_Opcode },
6251     /* 88 */
6252     { Bad_Opcode },
6253     { Bad_Opcode },
6254     { Bad_Opcode },
6255     { Bad_Opcode },
6256     { Bad_Opcode },
6257     { Bad_Opcode },
6258     { Bad_Opcode },
6259     { Bad_Opcode },
6260     /* 90 */
6261     { Bad_Opcode },
6262     { Bad_Opcode },
6263     { Bad_Opcode },
6264     { Bad_Opcode },
6265     { Bad_Opcode },
6266     { Bad_Opcode },
6267     { Bad_Opcode },
6268     { Bad_Opcode },
6269     /* 98 */
6270     { Bad_Opcode },
6271     { Bad_Opcode },
6272     { Bad_Opcode },
6273     { Bad_Opcode },
6274     { Bad_Opcode },
6275     { Bad_Opcode },
6276     { Bad_Opcode },
6277     { Bad_Opcode },
6278     /* a0 */
6279     { Bad_Opcode },
6280     { Bad_Opcode },
6281     { Bad_Opcode },
6282     { Bad_Opcode },
6283     { Bad_Opcode },
6284     { Bad_Opcode },
6285     { Bad_Opcode },
6286     { Bad_Opcode },
6287     /* a8 */
6288     { Bad_Opcode },
6289     { Bad_Opcode },
6290     { Bad_Opcode },
6291     { Bad_Opcode },
6292     { Bad_Opcode },
6293     { Bad_Opcode },
6294     { Bad_Opcode },
6295     { Bad_Opcode },
6296     /* b0 */
6297     { Bad_Opcode },
6298     { Bad_Opcode },
6299     { Bad_Opcode },
6300     { Bad_Opcode },
6301     { Bad_Opcode },
6302     { Bad_Opcode },
6303     { Bad_Opcode },
6304     { Bad_Opcode },
6305     /* b8 */
6306     { Bad_Opcode },
6307     { Bad_Opcode },
6308     { Bad_Opcode },
6309     { Bad_Opcode },
6310     { Bad_Opcode },
6311     { Bad_Opcode },
6312     { Bad_Opcode },
6313     { Bad_Opcode },
6314     /* c0 */
6315     { Bad_Opcode },
6316     { Bad_Opcode },
6317     { Bad_Opcode },
6318     { Bad_Opcode },
6319     { Bad_Opcode },
6320     { Bad_Opcode },
6321     { Bad_Opcode },
6322     { Bad_Opcode },
6323     /* c8 */
6324     { Bad_Opcode },
6325     { Bad_Opcode },
6326     { Bad_Opcode },
6327     { Bad_Opcode },
6328     { Bad_Opcode },
6329     { Bad_Opcode },
6330     { Bad_Opcode },
6331     { Bad_Opcode },
6332     /* d0 */
6333     { Bad_Opcode },
6334     { Bad_Opcode },
6335     { Bad_Opcode },
6336     { Bad_Opcode },
6337     { Bad_Opcode },
6338     { Bad_Opcode },
6339     { Bad_Opcode },
6340     { Bad_Opcode },
6341     /* d8 */
6342     { Bad_Opcode },
6343     { Bad_Opcode },
6344     { Bad_Opcode },
6345     { Bad_Opcode },
6346     { Bad_Opcode },
6347     { Bad_Opcode },
6348     { Bad_Opcode },
6349     { Bad_Opcode },
6350     /* e0 */
6351     { Bad_Opcode },
6352     { Bad_Opcode },
6353     { Bad_Opcode },
6354     { Bad_Opcode },
6355     { Bad_Opcode },
6356     { Bad_Opcode },
6357     { Bad_Opcode },
6358     { Bad_Opcode },
6359     /* e8 */
6360     { Bad_Opcode },
6361     { Bad_Opcode },
6362     { Bad_Opcode },
6363     { Bad_Opcode },
6364     { Bad_Opcode },
6365     { Bad_Opcode },
6366     { Bad_Opcode },
6367     { Bad_Opcode },
6368     /* f0 */
6369     { Bad_Opcode },
6370     { Bad_Opcode },
6371     { Bad_Opcode },
6372     { Bad_Opcode },
6373     { Bad_Opcode },
6374     { Bad_Opcode },
6375     { Bad_Opcode },
6376     { Bad_Opcode },
6377     /* f8 */
6378     { Bad_Opcode },
6379     { Bad_Opcode },
6380     { Bad_Opcode },
6381     { Bad_Opcode },
6382     { Bad_Opcode },
6383     { Bad_Opcode },
6384     { Bad_Opcode },
6385     { Bad_Opcode },
6386   },
6387 };
6388
6389 static const struct dis386 xop_table[][256] = {
6390   /* XOP_08 */
6391   {
6392     /* 00 */
6393     { Bad_Opcode },
6394     { Bad_Opcode },
6395     { Bad_Opcode },
6396     { Bad_Opcode },
6397     { Bad_Opcode },
6398     { Bad_Opcode },
6399     { Bad_Opcode },
6400     { Bad_Opcode },
6401     /* 08 */
6402     { Bad_Opcode },
6403     { Bad_Opcode },
6404     { Bad_Opcode },
6405     { Bad_Opcode },
6406     { Bad_Opcode },
6407     { Bad_Opcode },
6408     { Bad_Opcode },
6409     { Bad_Opcode },
6410     /* 10 */
6411     { Bad_Opcode },
6412     { Bad_Opcode },
6413     { Bad_Opcode },
6414     { Bad_Opcode },
6415     { Bad_Opcode },
6416     { Bad_Opcode },
6417     { Bad_Opcode },
6418     { Bad_Opcode },
6419     /* 18 */
6420     { Bad_Opcode },
6421     { Bad_Opcode },
6422     { Bad_Opcode },
6423     { Bad_Opcode },
6424     { Bad_Opcode },
6425     { Bad_Opcode },
6426     { Bad_Opcode },
6427     { Bad_Opcode },
6428     /* 20 */
6429     { Bad_Opcode },
6430     { Bad_Opcode },
6431     { Bad_Opcode },
6432     { Bad_Opcode },
6433     { Bad_Opcode },
6434     { Bad_Opcode },
6435     { Bad_Opcode },
6436     { Bad_Opcode },
6437     /* 28 */
6438     { Bad_Opcode },
6439     { Bad_Opcode },
6440     { Bad_Opcode },
6441     { Bad_Opcode },
6442     { Bad_Opcode },
6443     { Bad_Opcode },
6444     { Bad_Opcode },
6445     { Bad_Opcode },
6446     /* 30 */
6447     { Bad_Opcode },
6448     { Bad_Opcode },
6449     { Bad_Opcode },
6450     { Bad_Opcode },
6451     { Bad_Opcode },
6452     { Bad_Opcode },
6453     { Bad_Opcode },
6454     { Bad_Opcode },
6455     /* 38 */
6456     { Bad_Opcode },
6457     { Bad_Opcode },
6458     { Bad_Opcode },
6459     { Bad_Opcode },
6460     { Bad_Opcode },
6461     { Bad_Opcode },
6462     { Bad_Opcode },
6463     { Bad_Opcode },
6464     /* 40 */
6465     { Bad_Opcode },
6466     { Bad_Opcode },
6467     { Bad_Opcode },
6468     { Bad_Opcode },
6469     { Bad_Opcode },
6470     { Bad_Opcode },
6471     { Bad_Opcode },
6472     { Bad_Opcode },
6473     /* 48 */
6474     { Bad_Opcode },
6475     { Bad_Opcode },
6476     { Bad_Opcode },
6477     { Bad_Opcode },
6478     { Bad_Opcode },
6479     { Bad_Opcode },
6480     { Bad_Opcode },
6481     { Bad_Opcode },
6482     /* 50 */
6483     { Bad_Opcode },
6484     { Bad_Opcode },
6485     { Bad_Opcode },
6486     { Bad_Opcode },
6487     { Bad_Opcode },
6488     { Bad_Opcode },
6489     { Bad_Opcode },
6490     { Bad_Opcode },
6491     /* 58 */
6492     { Bad_Opcode },
6493     { Bad_Opcode },
6494     { Bad_Opcode },
6495     { Bad_Opcode },
6496     { Bad_Opcode },
6497     { Bad_Opcode },
6498     { Bad_Opcode },
6499     { Bad_Opcode },
6500     /* 60 */
6501     { Bad_Opcode },
6502     { Bad_Opcode },
6503     { Bad_Opcode },
6504     { Bad_Opcode },
6505     { Bad_Opcode },
6506     { Bad_Opcode },
6507     { Bad_Opcode },
6508     { Bad_Opcode },
6509     /* 68 */
6510     { Bad_Opcode },
6511     { Bad_Opcode },
6512     { Bad_Opcode },
6513     { Bad_Opcode },
6514     { Bad_Opcode },
6515     { Bad_Opcode },
6516     { Bad_Opcode },
6517     { Bad_Opcode },
6518     /* 70 */
6519     { Bad_Opcode },
6520     { Bad_Opcode },
6521     { Bad_Opcode },
6522     { Bad_Opcode },
6523     { Bad_Opcode },
6524     { Bad_Opcode },
6525     { Bad_Opcode },
6526     { Bad_Opcode },
6527     /* 78 */
6528     { Bad_Opcode },
6529     { Bad_Opcode },
6530     { Bad_Opcode },
6531     { Bad_Opcode },
6532     { Bad_Opcode },
6533     { Bad_Opcode },
6534     { Bad_Opcode },
6535     { Bad_Opcode },
6536     /* 80 */
6537     { Bad_Opcode },
6538     { Bad_Opcode },
6539     { Bad_Opcode },
6540     { Bad_Opcode },
6541     { Bad_Opcode },
6542     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6543     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6544     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6545     /* 88 */
6546     { Bad_Opcode },
6547     { Bad_Opcode },
6548     { Bad_Opcode },
6549     { Bad_Opcode },
6550     { Bad_Opcode },
6551     { Bad_Opcode },
6552     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6553     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6554     /* 90 */
6555     { Bad_Opcode },
6556     { Bad_Opcode },
6557     { Bad_Opcode },
6558     { Bad_Opcode },
6559     { Bad_Opcode },
6560     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6561     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6562     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6563     /* 98 */
6564     { Bad_Opcode },
6565     { Bad_Opcode },
6566     { Bad_Opcode },
6567     { Bad_Opcode },
6568     { Bad_Opcode },
6569     { Bad_Opcode },
6570     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6571     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6572     /* a0 */
6573     { Bad_Opcode },
6574     { Bad_Opcode },
6575     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6576     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6577     { Bad_Opcode },
6578     { Bad_Opcode },
6579     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6580     { Bad_Opcode },
6581     /* a8 */
6582     { Bad_Opcode },
6583     { Bad_Opcode },
6584     { Bad_Opcode },
6585     { Bad_Opcode },
6586     { Bad_Opcode },
6587     { Bad_Opcode },
6588     { Bad_Opcode },
6589     { Bad_Opcode },
6590     /* b0 */
6591     { Bad_Opcode },
6592     { Bad_Opcode },
6593     { Bad_Opcode },
6594     { Bad_Opcode },
6595     { Bad_Opcode },
6596     { Bad_Opcode },
6597     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6598     { Bad_Opcode },
6599     /* b8 */
6600     { Bad_Opcode },
6601     { Bad_Opcode },
6602     { Bad_Opcode },
6603     { Bad_Opcode },
6604     { Bad_Opcode },
6605     { Bad_Opcode },
6606     { Bad_Opcode },
6607     { Bad_Opcode },
6608     /* c0 */
6609     { "vprotb",         { XM, Vex_2src_1, Ib } },
6610     { "vprotw",         { XM, Vex_2src_1, Ib } },
6611     { "vprotd",         { XM, Vex_2src_1, Ib } },
6612     { "vprotq",         { XM, Vex_2src_1, Ib } },
6613     { Bad_Opcode },
6614     { Bad_Opcode },
6615     { Bad_Opcode },
6616     { Bad_Opcode },
6617     /* c8 */
6618     { Bad_Opcode },
6619     { Bad_Opcode },
6620     { Bad_Opcode },
6621     { Bad_Opcode },
6622     { "vpcomb",         { XM, Vex128, EXx, Ib } },
6623     { "vpcomw",         { XM, Vex128, EXx, Ib } },
6624     { "vpcomd",         { XM, Vex128, EXx, Ib } },
6625     { "vpcomq",         { XM, Vex128, EXx, Ib } },
6626     /* d0 */
6627     { Bad_Opcode },
6628     { Bad_Opcode },
6629     { Bad_Opcode },
6630     { Bad_Opcode },
6631     { Bad_Opcode },
6632     { Bad_Opcode },
6633     { Bad_Opcode },
6634     { Bad_Opcode },
6635     /* d8 */
6636     { Bad_Opcode },
6637     { Bad_Opcode },
6638     { Bad_Opcode },
6639     { Bad_Opcode },
6640     { Bad_Opcode },
6641     { Bad_Opcode },
6642     { Bad_Opcode },
6643     { Bad_Opcode },
6644     /* e0 */
6645     { Bad_Opcode },
6646     { Bad_Opcode },
6647     { Bad_Opcode },
6648     { Bad_Opcode },
6649     { Bad_Opcode },
6650     { Bad_Opcode },
6651     { Bad_Opcode },
6652     { Bad_Opcode },
6653     /* e8 */
6654     { Bad_Opcode },
6655     { Bad_Opcode },
6656     { Bad_Opcode },
6657     { Bad_Opcode },
6658     { "vpcomub",        { XM, Vex128, EXx, Ib } },
6659     { "vpcomuw",        { XM, Vex128, EXx, Ib } },
6660     { "vpcomud",        { XM, Vex128, EXx, Ib } },
6661     { "vpcomuq",        { XM, Vex128, EXx, Ib } },
6662     /* f0 */
6663     { Bad_Opcode },
6664     { Bad_Opcode },
6665     { Bad_Opcode },
6666     { Bad_Opcode },
6667     { Bad_Opcode },
6668     { Bad_Opcode },
6669     { Bad_Opcode },
6670     { Bad_Opcode },
6671     /* f8 */
6672     { Bad_Opcode },
6673     { Bad_Opcode },
6674     { Bad_Opcode },
6675     { Bad_Opcode },
6676     { Bad_Opcode },
6677     { Bad_Opcode },
6678     { Bad_Opcode },
6679     { Bad_Opcode },
6680   },
6681   /* XOP_09 */
6682   {
6683     /* 00 */
6684     { Bad_Opcode },
6685     { Bad_Opcode },
6686     { Bad_Opcode },
6687     { Bad_Opcode },
6688     { Bad_Opcode },
6689     { Bad_Opcode },
6690     { Bad_Opcode },
6691     { Bad_Opcode },
6692     /* 08 */
6693     { Bad_Opcode },
6694     { Bad_Opcode },
6695     { Bad_Opcode },
6696     { Bad_Opcode },
6697     { Bad_Opcode },
6698     { Bad_Opcode },
6699     { Bad_Opcode },
6700     { Bad_Opcode },
6701     /* 10 */
6702     { Bad_Opcode },
6703     { Bad_Opcode },
6704     { REG_TABLE (REG_XOP_LWPCB) },
6705     { Bad_Opcode },
6706     { Bad_Opcode },
6707     { Bad_Opcode },
6708     { Bad_Opcode },
6709     { Bad_Opcode },
6710     /* 18 */
6711     { Bad_Opcode },
6712     { Bad_Opcode },
6713     { Bad_Opcode },
6714     { Bad_Opcode },
6715     { Bad_Opcode },
6716     { Bad_Opcode },
6717     { Bad_Opcode },
6718     { Bad_Opcode },
6719     /* 20 */
6720     { Bad_Opcode },
6721     { Bad_Opcode },
6722     { Bad_Opcode },
6723     { Bad_Opcode },
6724     { Bad_Opcode },
6725     { Bad_Opcode },
6726     { Bad_Opcode },
6727     { Bad_Opcode },
6728     /* 28 */
6729     { Bad_Opcode },
6730     { Bad_Opcode },
6731     { Bad_Opcode },
6732     { Bad_Opcode },
6733     { Bad_Opcode },
6734     { Bad_Opcode },
6735     { Bad_Opcode },
6736     { Bad_Opcode },
6737     /* 30 */
6738     { Bad_Opcode },
6739     { Bad_Opcode },
6740     { Bad_Opcode },
6741     { Bad_Opcode },
6742     { Bad_Opcode },
6743     { Bad_Opcode },
6744     { Bad_Opcode },
6745     { Bad_Opcode },
6746     /* 38 */
6747     { Bad_Opcode },
6748     { Bad_Opcode },
6749     { Bad_Opcode },
6750     { Bad_Opcode },
6751     { Bad_Opcode },
6752     { Bad_Opcode },
6753     { Bad_Opcode },
6754     { Bad_Opcode },
6755     /* 40 */
6756     { Bad_Opcode },
6757     { Bad_Opcode },
6758     { Bad_Opcode },
6759     { Bad_Opcode },
6760     { Bad_Opcode },
6761     { Bad_Opcode },
6762     { Bad_Opcode },
6763     { Bad_Opcode },
6764     /* 48 */
6765     { Bad_Opcode },
6766     { Bad_Opcode },
6767     { Bad_Opcode },
6768     { Bad_Opcode },
6769     { Bad_Opcode },
6770     { Bad_Opcode },
6771     { Bad_Opcode },
6772     { Bad_Opcode },
6773     /* 50 */
6774     { Bad_Opcode },
6775     { Bad_Opcode },
6776     { Bad_Opcode },
6777     { Bad_Opcode },
6778     { Bad_Opcode },
6779     { Bad_Opcode },
6780     { Bad_Opcode },
6781     { Bad_Opcode },
6782     /* 58 */
6783     { Bad_Opcode },
6784     { Bad_Opcode },
6785     { Bad_Opcode },
6786     { Bad_Opcode },
6787     { Bad_Opcode },
6788     { Bad_Opcode },
6789     { Bad_Opcode },
6790     { Bad_Opcode },
6791     /* 60 */
6792     { Bad_Opcode },
6793     { Bad_Opcode },
6794     { Bad_Opcode },
6795     { Bad_Opcode },
6796     { Bad_Opcode },
6797     { Bad_Opcode },
6798     { Bad_Opcode },
6799     { Bad_Opcode },
6800     /* 68 */
6801     { Bad_Opcode },
6802     { Bad_Opcode },
6803     { Bad_Opcode },
6804     { Bad_Opcode },
6805     { Bad_Opcode },
6806     { Bad_Opcode },
6807     { Bad_Opcode },
6808     { Bad_Opcode },
6809     /* 70 */
6810     { Bad_Opcode },
6811     { Bad_Opcode },
6812     { Bad_Opcode },
6813     { Bad_Opcode },
6814     { Bad_Opcode },
6815     { Bad_Opcode },
6816     { Bad_Opcode },
6817     { Bad_Opcode },
6818     /* 78 */
6819     { Bad_Opcode },
6820     { Bad_Opcode },
6821     { Bad_Opcode },
6822     { Bad_Opcode },
6823     { Bad_Opcode },
6824     { Bad_Opcode },
6825     { Bad_Opcode },
6826     { Bad_Opcode },
6827     /* 80 */
6828     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
6829     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
6830     { "vfrczss",        { XM, EXd } },
6831     { "vfrczsd",        { XM, EXq } },
6832     { Bad_Opcode },
6833     { Bad_Opcode },
6834     { Bad_Opcode },
6835     { Bad_Opcode },
6836     /* 88 */
6837     { Bad_Opcode },
6838     { Bad_Opcode },
6839     { Bad_Opcode },
6840     { Bad_Opcode },
6841     { Bad_Opcode },
6842     { Bad_Opcode },
6843     { Bad_Opcode },
6844     { Bad_Opcode },
6845     /* 90 */
6846     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 } },
6847     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 } },
6848     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 } },
6849     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 } },
6850     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 } },
6851     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 } },
6852     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 } },
6853     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 } },
6854     /* 98 */
6855     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 } },
6856     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 } },
6857     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 } },
6858     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 } },
6859     { Bad_Opcode },
6860     { Bad_Opcode },
6861     { Bad_Opcode },
6862     { Bad_Opcode },
6863     /* a0 */
6864     { Bad_Opcode },
6865     { Bad_Opcode },
6866     { Bad_Opcode },
6867     { Bad_Opcode },
6868     { Bad_Opcode },
6869     { Bad_Opcode },
6870     { Bad_Opcode },
6871     { Bad_Opcode },
6872     /* a8 */
6873     { Bad_Opcode },
6874     { Bad_Opcode },
6875     { Bad_Opcode },
6876     { Bad_Opcode },
6877     { Bad_Opcode },
6878     { Bad_Opcode },
6879     { Bad_Opcode },
6880     { Bad_Opcode },
6881     /* b0 */
6882     { Bad_Opcode },
6883     { Bad_Opcode },
6884     { Bad_Opcode },
6885     { Bad_Opcode },
6886     { Bad_Opcode },
6887     { Bad_Opcode },
6888     { Bad_Opcode },
6889     { Bad_Opcode },
6890     /* b8 */
6891     { Bad_Opcode },
6892     { Bad_Opcode },
6893     { Bad_Opcode },
6894     { Bad_Opcode },
6895     { Bad_Opcode },
6896     { Bad_Opcode },
6897     { Bad_Opcode },
6898     { Bad_Opcode },
6899     /* c0 */
6900     { Bad_Opcode },
6901     { "vphaddbw",       { XM, EXxmm } },
6902     { "vphaddbd",       { XM, EXxmm } },
6903     { "vphaddbq",       { XM, EXxmm } },
6904     { Bad_Opcode },
6905     { Bad_Opcode },
6906     { "vphaddwd",       { XM, EXxmm } },
6907     { "vphaddwq",       { XM, EXxmm } },
6908     /* c8 */
6909     { Bad_Opcode },
6910     { Bad_Opcode },
6911     { Bad_Opcode },
6912     { "vphadddq",       { XM, EXxmm } },
6913     { Bad_Opcode },
6914     { Bad_Opcode },
6915     { Bad_Opcode },
6916     { Bad_Opcode },
6917     /* d0 */
6918     { Bad_Opcode },
6919     { "vphaddubw",      { XM, EXxmm } },
6920     { "vphaddubd",      { XM, EXxmm } },
6921     { "vphaddubq",      { XM, EXxmm } },
6922     { Bad_Opcode },
6923     { Bad_Opcode },
6924     { "vphadduwd",      { XM, EXxmm } },
6925     { "vphadduwq",      { XM, EXxmm } },
6926     /* d8 */
6927     { Bad_Opcode },
6928     { Bad_Opcode },
6929     { Bad_Opcode },
6930     { "vphaddudq",      { XM, EXxmm } },
6931     { Bad_Opcode },
6932     { Bad_Opcode },
6933     { Bad_Opcode },
6934     { Bad_Opcode },
6935     /* e0 */
6936     { Bad_Opcode },
6937     { "vphsubbw",       { XM, EXxmm } },
6938     { "vphsubwd",       { XM, EXxmm } },
6939     { "vphsubdq",       { XM, EXxmm } },
6940     { Bad_Opcode },
6941     { Bad_Opcode },
6942     { Bad_Opcode },
6943     { Bad_Opcode },
6944     /* e8 */
6945     { Bad_Opcode },
6946     { Bad_Opcode },
6947     { Bad_Opcode },
6948     { Bad_Opcode },
6949     { Bad_Opcode },
6950     { Bad_Opcode },
6951     { Bad_Opcode },
6952     { Bad_Opcode },
6953     /* f0 */
6954     { Bad_Opcode },
6955     { Bad_Opcode },
6956     { Bad_Opcode },
6957     { Bad_Opcode },
6958     { Bad_Opcode },
6959     { Bad_Opcode },
6960     { Bad_Opcode },
6961     { Bad_Opcode },
6962     /* f8 */
6963     { Bad_Opcode },
6964     { Bad_Opcode },
6965     { Bad_Opcode },
6966     { Bad_Opcode },
6967     { Bad_Opcode },
6968     { Bad_Opcode },
6969     { Bad_Opcode },
6970     { Bad_Opcode },
6971   },
6972   /* XOP_0A */
6973   {
6974     /* 00 */
6975     { Bad_Opcode },
6976     { Bad_Opcode },
6977     { Bad_Opcode },
6978     { Bad_Opcode },
6979     { Bad_Opcode },
6980     { Bad_Opcode },
6981     { Bad_Opcode },
6982     { Bad_Opcode },
6983     /* 08 */
6984     { Bad_Opcode },
6985     { Bad_Opcode },
6986     { Bad_Opcode },
6987     { Bad_Opcode },
6988     { Bad_Opcode },
6989     { Bad_Opcode },
6990     { Bad_Opcode },
6991     { Bad_Opcode },
6992     /* 10 */
6993     { Bad_Opcode },
6994     { Bad_Opcode },
6995     { REG_TABLE (REG_XOP_LWP) },
6996     { Bad_Opcode },
6997     { Bad_Opcode },
6998     { Bad_Opcode },
6999     { Bad_Opcode },
7000     { Bad_Opcode },
7001     /* 18 */
7002     { Bad_Opcode },
7003     { Bad_Opcode },
7004     { Bad_Opcode },
7005     { Bad_Opcode },
7006     { Bad_Opcode },
7007     { Bad_Opcode },
7008     { Bad_Opcode },
7009     { Bad_Opcode },
7010     /* 20 */
7011     { Bad_Opcode },
7012     { Bad_Opcode },
7013     { Bad_Opcode },
7014     { Bad_Opcode },
7015     { Bad_Opcode },
7016     { Bad_Opcode },
7017     { Bad_Opcode },
7018     { Bad_Opcode },
7019     /* 28 */
7020     { Bad_Opcode },
7021     { Bad_Opcode },
7022     { Bad_Opcode },
7023     { Bad_Opcode },
7024     { Bad_Opcode },
7025     { Bad_Opcode },
7026     { Bad_Opcode },
7027     { Bad_Opcode },
7028     /* 30 */
7029     { Bad_Opcode },
7030     { Bad_Opcode },
7031     { Bad_Opcode },
7032     { Bad_Opcode },
7033     { Bad_Opcode },
7034     { Bad_Opcode },
7035     { Bad_Opcode },
7036     { Bad_Opcode },
7037     /* 38 */
7038     { Bad_Opcode },
7039     { Bad_Opcode },
7040     { Bad_Opcode },
7041     { Bad_Opcode },
7042     { Bad_Opcode },
7043     { Bad_Opcode },
7044     { Bad_Opcode },
7045     { Bad_Opcode },
7046     /* 40 */
7047     { Bad_Opcode },
7048     { Bad_Opcode },
7049     { Bad_Opcode },
7050     { Bad_Opcode },
7051     { Bad_Opcode },
7052     { Bad_Opcode },
7053     { Bad_Opcode },
7054     { Bad_Opcode },
7055     /* 48 */
7056     { Bad_Opcode },
7057     { Bad_Opcode },
7058     { Bad_Opcode },
7059     { Bad_Opcode },
7060     { Bad_Opcode },
7061     { Bad_Opcode },
7062     { Bad_Opcode },
7063     { Bad_Opcode },
7064     /* 50 */
7065     { Bad_Opcode },
7066     { Bad_Opcode },
7067     { Bad_Opcode },
7068     { Bad_Opcode },
7069     { Bad_Opcode },
7070     { Bad_Opcode },
7071     { Bad_Opcode },
7072     { Bad_Opcode },
7073     /* 58 */
7074     { Bad_Opcode },
7075     { Bad_Opcode },
7076     { Bad_Opcode },
7077     { Bad_Opcode },
7078     { Bad_Opcode },
7079     { Bad_Opcode },
7080     { Bad_Opcode },
7081     { Bad_Opcode },
7082     /* 60 */
7083     { Bad_Opcode },
7084     { Bad_Opcode },
7085     { Bad_Opcode },
7086     { Bad_Opcode },
7087     { Bad_Opcode },
7088     { Bad_Opcode },
7089     { Bad_Opcode },
7090     { Bad_Opcode },
7091     /* 68 */
7092     { Bad_Opcode },
7093     { Bad_Opcode },
7094     { Bad_Opcode },
7095     { Bad_Opcode },
7096     { Bad_Opcode },
7097     { Bad_Opcode },
7098     { Bad_Opcode },
7099     { Bad_Opcode },
7100     /* 70 */
7101     { Bad_Opcode },
7102     { Bad_Opcode },
7103     { Bad_Opcode },
7104     { Bad_Opcode },
7105     { Bad_Opcode },
7106     { Bad_Opcode },
7107     { Bad_Opcode },
7108     { Bad_Opcode },
7109     /* 78 */
7110     { Bad_Opcode },
7111     { Bad_Opcode },
7112     { Bad_Opcode },
7113     { Bad_Opcode },
7114     { Bad_Opcode },
7115     { Bad_Opcode },
7116     { Bad_Opcode },
7117     { Bad_Opcode },
7118     /* 80 */
7119     { Bad_Opcode },
7120     { Bad_Opcode },
7121     { Bad_Opcode },
7122     { Bad_Opcode },
7123     { Bad_Opcode },
7124     { Bad_Opcode },
7125     { Bad_Opcode },
7126     { Bad_Opcode },
7127     /* 88 */
7128     { Bad_Opcode },
7129     { Bad_Opcode },
7130     { Bad_Opcode },
7131     { Bad_Opcode },
7132     { Bad_Opcode },
7133     { Bad_Opcode },
7134     { Bad_Opcode },
7135     { Bad_Opcode },
7136     /* 90 */
7137     { Bad_Opcode },
7138     { Bad_Opcode },
7139     { Bad_Opcode },
7140     { Bad_Opcode },
7141     { Bad_Opcode },
7142     { Bad_Opcode },
7143     { Bad_Opcode },
7144     { Bad_Opcode },
7145     /* 98 */
7146     { Bad_Opcode },
7147     { Bad_Opcode },
7148     { Bad_Opcode },
7149     { Bad_Opcode },
7150     { Bad_Opcode },
7151     { Bad_Opcode },
7152     { Bad_Opcode },
7153     { Bad_Opcode },
7154     /* a0 */
7155     { Bad_Opcode },
7156     { Bad_Opcode },
7157     { Bad_Opcode },
7158     { Bad_Opcode },
7159     { Bad_Opcode },
7160     { Bad_Opcode },
7161     { Bad_Opcode },
7162     { Bad_Opcode },
7163     /* a8 */
7164     { Bad_Opcode },
7165     { Bad_Opcode },
7166     { Bad_Opcode },
7167     { Bad_Opcode },
7168     { Bad_Opcode },
7169     { Bad_Opcode },
7170     { Bad_Opcode },
7171     { Bad_Opcode },
7172     /* b0 */
7173     { Bad_Opcode },
7174     { Bad_Opcode },
7175     { Bad_Opcode },
7176     { Bad_Opcode },
7177     { Bad_Opcode },
7178     { Bad_Opcode },
7179     { Bad_Opcode },
7180     { Bad_Opcode },
7181     /* b8 */
7182     { Bad_Opcode },
7183     { Bad_Opcode },
7184     { Bad_Opcode },
7185     { Bad_Opcode },
7186     { Bad_Opcode },
7187     { Bad_Opcode },
7188     { Bad_Opcode },
7189     { Bad_Opcode },
7190     /* c0 */
7191     { Bad_Opcode },
7192     { Bad_Opcode },
7193     { Bad_Opcode },
7194     { Bad_Opcode },
7195     { Bad_Opcode },
7196     { Bad_Opcode },
7197     { Bad_Opcode },
7198     { Bad_Opcode },
7199     /* c8 */
7200     { Bad_Opcode },
7201     { Bad_Opcode },
7202     { Bad_Opcode },
7203     { Bad_Opcode },
7204     { Bad_Opcode },
7205     { Bad_Opcode },
7206     { Bad_Opcode },
7207     { Bad_Opcode },
7208     /* d0 */
7209     { Bad_Opcode },
7210     { Bad_Opcode },
7211     { Bad_Opcode },
7212     { Bad_Opcode },
7213     { Bad_Opcode },
7214     { Bad_Opcode },
7215     { Bad_Opcode },
7216     { Bad_Opcode },
7217     /* d8 */
7218     { Bad_Opcode },
7219     { Bad_Opcode },
7220     { Bad_Opcode },
7221     { Bad_Opcode },
7222     { Bad_Opcode },
7223     { Bad_Opcode },
7224     { Bad_Opcode },
7225     { Bad_Opcode },
7226     /* e0 */
7227     { Bad_Opcode },
7228     { Bad_Opcode },
7229     { Bad_Opcode },
7230     { Bad_Opcode },
7231     { Bad_Opcode },
7232     { Bad_Opcode },
7233     { Bad_Opcode },
7234     { Bad_Opcode },
7235     /* e8 */
7236     { Bad_Opcode },
7237     { Bad_Opcode },
7238     { Bad_Opcode },
7239     { Bad_Opcode },
7240     { Bad_Opcode },
7241     { Bad_Opcode },
7242     { Bad_Opcode },
7243     { Bad_Opcode },
7244     /* f0 */
7245     { Bad_Opcode },
7246     { Bad_Opcode },
7247     { Bad_Opcode },
7248     { Bad_Opcode },
7249     { Bad_Opcode },
7250     { Bad_Opcode },
7251     { Bad_Opcode },
7252     { Bad_Opcode },
7253     /* f8 */
7254     { Bad_Opcode },
7255     { Bad_Opcode },
7256     { Bad_Opcode },
7257     { Bad_Opcode },
7258     { Bad_Opcode },
7259     { Bad_Opcode },
7260     { Bad_Opcode },
7261     { Bad_Opcode },
7262   },
7263 };
7264
7265 static const struct dis386 vex_table[][256] = {
7266   /* VEX_0F */
7267   {
7268     /* 00 */
7269     { Bad_Opcode },
7270     { Bad_Opcode },
7271     { Bad_Opcode },
7272     { Bad_Opcode },
7273     { Bad_Opcode },
7274     { Bad_Opcode },
7275     { Bad_Opcode },
7276     { Bad_Opcode },
7277     /* 08 */
7278     { Bad_Opcode },
7279     { Bad_Opcode },
7280     { Bad_Opcode },
7281     { Bad_Opcode },
7282     { Bad_Opcode },
7283     { Bad_Opcode },
7284     { Bad_Opcode },
7285     { Bad_Opcode },
7286     /* 10 */
7287     { PREFIX_TABLE (PREFIX_VEX_0F10) },
7288     { PREFIX_TABLE (PREFIX_VEX_0F11) },
7289     { PREFIX_TABLE (PREFIX_VEX_0F12) },
7290     { MOD_TABLE (MOD_VEX_0F13) },
7291     { VEX_W_TABLE (VEX_W_0F14) },
7292     { VEX_W_TABLE (VEX_W_0F15) },
7293     { PREFIX_TABLE (PREFIX_VEX_0F16) },
7294     { MOD_TABLE (MOD_VEX_0F17) },
7295     /* 18 */
7296     { Bad_Opcode },
7297     { Bad_Opcode },
7298     { Bad_Opcode },
7299     { Bad_Opcode },
7300     { Bad_Opcode },
7301     { Bad_Opcode },
7302     { Bad_Opcode },
7303     { Bad_Opcode },
7304     /* 20 */
7305     { Bad_Opcode },
7306     { Bad_Opcode },
7307     { Bad_Opcode },
7308     { Bad_Opcode },
7309     { Bad_Opcode },
7310     { Bad_Opcode },
7311     { Bad_Opcode },
7312     { Bad_Opcode },
7313     /* 28 */
7314     { VEX_W_TABLE (VEX_W_0F28) },
7315     { VEX_W_TABLE (VEX_W_0F29) },
7316     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
7317     { MOD_TABLE (MOD_VEX_0F2B) },
7318     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
7319     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
7320     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
7321     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
7322     /* 30 */
7323     { Bad_Opcode },
7324     { Bad_Opcode },
7325     { Bad_Opcode },
7326     { Bad_Opcode },
7327     { Bad_Opcode },
7328     { Bad_Opcode },
7329     { Bad_Opcode },
7330     { Bad_Opcode },
7331     /* 38 */
7332     { Bad_Opcode },
7333     { Bad_Opcode },
7334     { Bad_Opcode },
7335     { Bad_Opcode },
7336     { Bad_Opcode },
7337     { Bad_Opcode },
7338     { Bad_Opcode },
7339     { Bad_Opcode },
7340     /* 40 */
7341     { Bad_Opcode },
7342     { Bad_Opcode },
7343     { Bad_Opcode },
7344     { Bad_Opcode },
7345     { Bad_Opcode },
7346     { Bad_Opcode },
7347     { Bad_Opcode },
7348     { Bad_Opcode },
7349     /* 48 */
7350     { Bad_Opcode },
7351     { Bad_Opcode },
7352     { Bad_Opcode },
7353     { Bad_Opcode },
7354     { Bad_Opcode },
7355     { Bad_Opcode },
7356     { Bad_Opcode },
7357     { Bad_Opcode },
7358     /* 50 */
7359     { MOD_TABLE (MOD_VEX_0F50) },
7360     { PREFIX_TABLE (PREFIX_VEX_0F51) },
7361     { PREFIX_TABLE (PREFIX_VEX_0F52) },
7362     { PREFIX_TABLE (PREFIX_VEX_0F53) },
7363     { "vandpX",         { XM, Vex, EXx } },
7364     { "vandnpX",        { XM, Vex, EXx } },
7365     { "vorpX",          { XM, Vex, EXx } },
7366     { "vxorpX",         { XM, Vex, EXx } },
7367     /* 58 */
7368     { PREFIX_TABLE (PREFIX_VEX_0F58) },
7369     { PREFIX_TABLE (PREFIX_VEX_0F59) },
7370     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
7371     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
7372     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
7373     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
7374     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
7375     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
7376     /* 60 */
7377     { PREFIX_TABLE (PREFIX_VEX_0F60) },
7378     { PREFIX_TABLE (PREFIX_VEX_0F61) },
7379     { PREFIX_TABLE (PREFIX_VEX_0F62) },
7380     { PREFIX_TABLE (PREFIX_VEX_0F63) },
7381     { PREFIX_TABLE (PREFIX_VEX_0F64) },
7382     { PREFIX_TABLE (PREFIX_VEX_0F65) },
7383     { PREFIX_TABLE (PREFIX_VEX_0F66) },
7384     { PREFIX_TABLE (PREFIX_VEX_0F67) },
7385     /* 68 */
7386     { PREFIX_TABLE (PREFIX_VEX_0F68) },
7387     { PREFIX_TABLE (PREFIX_VEX_0F69) },
7388     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
7389     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
7390     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
7391     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
7392     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
7393     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
7394     /* 70 */
7395     { PREFIX_TABLE (PREFIX_VEX_0F70) },
7396     { REG_TABLE (REG_VEX_0F71) },
7397     { REG_TABLE (REG_VEX_0F72) },
7398     { REG_TABLE (REG_VEX_0F73) },
7399     { PREFIX_TABLE (PREFIX_VEX_0F74) },
7400     { PREFIX_TABLE (PREFIX_VEX_0F75) },
7401     { PREFIX_TABLE (PREFIX_VEX_0F76) },
7402     { PREFIX_TABLE (PREFIX_VEX_0F77) },
7403     /* 78 */
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     { Bad_Opcode },
7407     { Bad_Opcode },
7408     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
7409     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
7410     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
7411     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
7412     /* 80 */
7413     { Bad_Opcode },
7414     { Bad_Opcode },
7415     { Bad_Opcode },
7416     { Bad_Opcode },
7417     { Bad_Opcode },
7418     { Bad_Opcode },
7419     { Bad_Opcode },
7420     { Bad_Opcode },
7421     /* 88 */
7422     { Bad_Opcode },
7423     { Bad_Opcode },
7424     { Bad_Opcode },
7425     { Bad_Opcode },
7426     { Bad_Opcode },
7427     { Bad_Opcode },
7428     { Bad_Opcode },
7429     { Bad_Opcode },
7430     /* 90 */
7431     { Bad_Opcode },
7432     { Bad_Opcode },
7433     { Bad_Opcode },
7434     { Bad_Opcode },
7435     { Bad_Opcode },
7436     { Bad_Opcode },
7437     { Bad_Opcode },
7438     { Bad_Opcode },
7439     /* 98 */
7440     { Bad_Opcode },
7441     { Bad_Opcode },
7442     { Bad_Opcode },
7443     { Bad_Opcode },
7444     { Bad_Opcode },
7445     { Bad_Opcode },
7446     { Bad_Opcode },
7447     { Bad_Opcode },
7448     /* a0 */
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     { Bad_Opcode },
7452     { Bad_Opcode },
7453     { Bad_Opcode },
7454     { Bad_Opcode },
7455     { Bad_Opcode },
7456     { Bad_Opcode },
7457     /* a8 */
7458     { Bad_Opcode },
7459     { Bad_Opcode },
7460     { Bad_Opcode },
7461     { Bad_Opcode },
7462     { Bad_Opcode },
7463     { Bad_Opcode },
7464     { REG_TABLE (REG_VEX_0FAE) },
7465     { Bad_Opcode },
7466     /* b0 */
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469     { Bad_Opcode },
7470     { Bad_Opcode },
7471     { Bad_Opcode },
7472     { Bad_Opcode },
7473     { Bad_Opcode },
7474     { Bad_Opcode },
7475     /* b8 */
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     { Bad_Opcode },
7479     { Bad_Opcode },
7480     { Bad_Opcode },
7481     { Bad_Opcode },
7482     { Bad_Opcode },
7483     { Bad_Opcode },
7484     /* c0 */
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
7488     { Bad_Opcode },
7489     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
7490     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
7491     { "vshufpX",        { XM, Vex, EXx, Ib } },
7492     { Bad_Opcode },
7493     /* c8 */
7494     { Bad_Opcode },
7495     { Bad_Opcode },
7496     { Bad_Opcode },
7497     { Bad_Opcode },
7498     { Bad_Opcode },
7499     { Bad_Opcode },
7500     { Bad_Opcode },
7501     { Bad_Opcode },
7502     /* d0 */
7503     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
7504     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
7505     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
7506     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
7507     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
7508     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
7509     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
7510     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
7511     /* d8 */
7512     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
7513     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
7514     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
7515     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
7516     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
7517     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
7518     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
7519     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
7520     /* e0 */
7521     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
7522     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
7523     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
7524     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
7525     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
7526     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
7527     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
7528     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
7529     /* e8 */
7530     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
7531     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
7532     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
7533     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
7534     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
7535     { PREFIX_TABLE (PREFIX_VEX_0FED) },
7536     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
7537     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
7538     /* f0 */
7539     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
7540     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
7541     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
7542     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
7543     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
7544     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
7545     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
7546     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
7547     /* f8 */
7548     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
7549     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
7550     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
7551     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
7552     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
7553     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
7554     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
7555     { Bad_Opcode },
7556   },
7557   /* VEX_0F38 */
7558   {
7559     /* 00 */
7560     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
7561     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
7562     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
7563     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
7564     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
7565     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
7566     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
7567     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
7568     /* 08 */
7569     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
7570     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
7571     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
7572     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
7573     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
7574     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
7575     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
7576     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
7577     /* 10 */
7578     { Bad_Opcode },
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
7582     { Bad_Opcode },
7583     { Bad_Opcode },
7584     { Bad_Opcode },
7585     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
7586     /* 18 */
7587     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
7588     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
7589     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
7590     { Bad_Opcode },
7591     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
7592     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
7593     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
7594     { Bad_Opcode },
7595     /* 20 */
7596     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
7597     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
7598     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
7599     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
7600     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
7601     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
7602     { Bad_Opcode },
7603     { Bad_Opcode },
7604     /* 28 */
7605     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
7606     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
7607     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
7608     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
7609     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
7610     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
7611     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
7612     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
7613     /* 30 */
7614     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
7615     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
7616     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
7617     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
7618     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
7619     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
7620     { Bad_Opcode },
7621     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
7622     /* 38 */
7623     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
7624     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
7625     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
7626     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
7627     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
7628     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
7629     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
7630     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
7631     /* 40 */
7632     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
7633     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
7634     { Bad_Opcode },
7635     { Bad_Opcode },
7636     { Bad_Opcode },
7637     { Bad_Opcode },
7638     { Bad_Opcode },
7639     { Bad_Opcode },
7640     /* 48 */
7641     { Bad_Opcode },
7642     { Bad_Opcode },
7643     { Bad_Opcode },
7644     { Bad_Opcode },
7645     { Bad_Opcode },
7646     { Bad_Opcode },
7647     { Bad_Opcode },
7648     { Bad_Opcode },
7649     /* 50 */
7650     { Bad_Opcode },
7651     { Bad_Opcode },
7652     { Bad_Opcode },
7653     { Bad_Opcode },
7654     { Bad_Opcode },
7655     { Bad_Opcode },
7656     { Bad_Opcode },
7657     { Bad_Opcode },
7658     /* 58 */
7659     { Bad_Opcode },
7660     { Bad_Opcode },
7661     { Bad_Opcode },
7662     { Bad_Opcode },
7663     { Bad_Opcode },
7664     { Bad_Opcode },
7665     { Bad_Opcode },
7666     { Bad_Opcode },
7667     /* 60 */
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     { Bad_Opcode },
7671     { Bad_Opcode },
7672     { Bad_Opcode },
7673     { Bad_Opcode },
7674     { Bad_Opcode },
7675     { Bad_Opcode },
7676     /* 68 */
7677     { Bad_Opcode },
7678     { Bad_Opcode },
7679     { Bad_Opcode },
7680     { Bad_Opcode },
7681     { Bad_Opcode },
7682     { Bad_Opcode },
7683     { Bad_Opcode },
7684     { Bad_Opcode },
7685     /* 70 */
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     { Bad_Opcode },
7691     { Bad_Opcode },
7692     { Bad_Opcode },
7693     { Bad_Opcode },
7694     /* 78 */
7695     { Bad_Opcode },
7696     { Bad_Opcode },
7697     { Bad_Opcode },
7698     { Bad_Opcode },
7699     { Bad_Opcode },
7700     { Bad_Opcode },
7701     { Bad_Opcode },
7702     { Bad_Opcode },
7703     /* 80 */
7704     { Bad_Opcode },
7705     { Bad_Opcode },
7706     { Bad_Opcode },
7707     { Bad_Opcode },
7708     { Bad_Opcode },
7709     { Bad_Opcode },
7710     { Bad_Opcode },
7711     { Bad_Opcode },
7712     /* 88 */
7713     { Bad_Opcode },
7714     { Bad_Opcode },
7715     { Bad_Opcode },
7716     { Bad_Opcode },
7717     { Bad_Opcode },
7718     { Bad_Opcode },
7719     { Bad_Opcode },
7720     { Bad_Opcode },
7721     /* 90 */
7722     { Bad_Opcode },
7723     { Bad_Opcode },
7724     { Bad_Opcode },
7725     { Bad_Opcode },
7726     { Bad_Opcode },
7727     { Bad_Opcode },
7728     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
7729     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
7730     /* 98 */
7731     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
7732     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
7733     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
7734     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
7735     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
7736     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
7737     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
7738     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
7739     /* a0 */
7740     { Bad_Opcode },
7741     { Bad_Opcode },
7742     { Bad_Opcode },
7743     { Bad_Opcode },
7744     { Bad_Opcode },
7745     { Bad_Opcode },
7746     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
7747     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
7748     /* a8 */
7749     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
7750     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
7751     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
7752     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
7753     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
7754     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
7755     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
7756     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
7757     /* b0 */
7758     { Bad_Opcode },
7759     { Bad_Opcode },
7760     { Bad_Opcode },
7761     { Bad_Opcode },
7762     { Bad_Opcode },
7763     { Bad_Opcode },
7764     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
7765     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
7766     /* b8 */
7767     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
7768     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
7769     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
7770     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
7771     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
7772     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
7773     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
7774     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
7775     /* c0 */
7776     { Bad_Opcode },
7777     { Bad_Opcode },
7778     { Bad_Opcode },
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     { Bad_Opcode },
7782     { Bad_Opcode },
7783     { Bad_Opcode },
7784     /* c8 */
7785     { Bad_Opcode },
7786     { Bad_Opcode },
7787     { Bad_Opcode },
7788     { Bad_Opcode },
7789     { Bad_Opcode },
7790     { Bad_Opcode },
7791     { Bad_Opcode },
7792     { Bad_Opcode },
7793     /* d0 */
7794     { Bad_Opcode },
7795     { Bad_Opcode },
7796     { Bad_Opcode },
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     { Bad_Opcode },
7800     { Bad_Opcode },
7801     { Bad_Opcode },
7802     /* d8 */
7803     { Bad_Opcode },
7804     { Bad_Opcode },
7805     { Bad_Opcode },
7806     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
7807     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
7808     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
7809     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
7810     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
7811     /* e0 */
7812     { Bad_Opcode },
7813     { Bad_Opcode },
7814     { Bad_Opcode },
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     { Bad_Opcode },
7818     { Bad_Opcode },
7819     { Bad_Opcode },
7820     /* e8 */
7821     { Bad_Opcode },
7822     { Bad_Opcode },
7823     { Bad_Opcode },
7824     { Bad_Opcode },
7825     { Bad_Opcode },
7826     { Bad_Opcode },
7827     { Bad_Opcode },
7828     { Bad_Opcode },
7829     /* f0 */
7830     { Bad_Opcode },
7831     { Bad_Opcode },
7832     { Bad_Opcode },
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     { Bad_Opcode },
7836     { Bad_Opcode },
7837     { Bad_Opcode },
7838     /* f8 */
7839     { Bad_Opcode },
7840     { Bad_Opcode },
7841     { Bad_Opcode },
7842     { Bad_Opcode },
7843     { Bad_Opcode },
7844     { Bad_Opcode },
7845     { Bad_Opcode },
7846     { Bad_Opcode },
7847   },
7848   /* VEX_0F3A */
7849   {
7850     /* 00 */
7851     { Bad_Opcode },
7852     { Bad_Opcode },
7853     { Bad_Opcode },
7854     { Bad_Opcode },
7855     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
7856     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
7857     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
7858     { Bad_Opcode },
7859     /* 08 */
7860     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
7861     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
7862     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
7863     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
7864     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
7865     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
7866     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
7867     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
7868     /* 10 */
7869     { Bad_Opcode },
7870     { Bad_Opcode },
7871     { Bad_Opcode },
7872     { Bad_Opcode },
7873     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
7874     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
7875     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
7876     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
7877     /* 18 */
7878     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
7879     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
7880     { Bad_Opcode },
7881     { Bad_Opcode },
7882     { Bad_Opcode },
7883     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
7884     { Bad_Opcode },
7885     { Bad_Opcode },
7886     /* 20 */
7887     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
7888     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
7889     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
7890     { Bad_Opcode },
7891     { Bad_Opcode },
7892     { Bad_Opcode },
7893     { Bad_Opcode },
7894     { Bad_Opcode },
7895     /* 28 */
7896     { Bad_Opcode },
7897     { Bad_Opcode },
7898     { Bad_Opcode },
7899     { Bad_Opcode },
7900     { Bad_Opcode },
7901     { Bad_Opcode },
7902     { Bad_Opcode },
7903     { Bad_Opcode },
7904     /* 30 */
7905     { Bad_Opcode },
7906     { Bad_Opcode },
7907     { Bad_Opcode },
7908     { Bad_Opcode },
7909     { Bad_Opcode },
7910     { Bad_Opcode },
7911     { Bad_Opcode },
7912     { Bad_Opcode },
7913     /* 38 */
7914     { Bad_Opcode },
7915     { Bad_Opcode },
7916     { Bad_Opcode },
7917     { Bad_Opcode },
7918     { Bad_Opcode },
7919     { Bad_Opcode },
7920     { Bad_Opcode },
7921     { Bad_Opcode },
7922     /* 40 */
7923     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
7924     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
7925     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
7926     { Bad_Opcode },
7927     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
7928     { Bad_Opcode },
7929     { Bad_Opcode },
7930     { Bad_Opcode },
7931     /* 48 */
7932     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
7933     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
7934     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
7935     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
7936     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
7937     { Bad_Opcode },
7938     { Bad_Opcode },
7939     { Bad_Opcode },
7940     /* 50 */
7941     { Bad_Opcode },
7942     { Bad_Opcode },
7943     { Bad_Opcode },
7944     { Bad_Opcode },
7945     { Bad_Opcode },
7946     { Bad_Opcode },
7947     { Bad_Opcode },
7948     { Bad_Opcode },
7949     /* 58 */
7950     { Bad_Opcode },
7951     { Bad_Opcode },
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
7955     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
7956     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
7957     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
7958     /* 60 */
7959     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
7960     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
7961     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
7962     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
7963     { Bad_Opcode },
7964     { Bad_Opcode },
7965     { Bad_Opcode },
7966     { Bad_Opcode },
7967     /* 68 */
7968     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
7969     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
7970     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
7971     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
7972     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
7973     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
7974     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
7975     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
7976     /* 70 */
7977     { Bad_Opcode },
7978     { Bad_Opcode },
7979     { Bad_Opcode },
7980     { Bad_Opcode },
7981     { Bad_Opcode },
7982     { Bad_Opcode },
7983     { Bad_Opcode },
7984     { Bad_Opcode },
7985     /* 78 */
7986     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
7987     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
7988     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
7989     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
7990     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
7991     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
7992     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
7993     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
7994     /* 80 */
7995     { Bad_Opcode },
7996     { Bad_Opcode },
7997     { Bad_Opcode },
7998     { Bad_Opcode },
7999     { Bad_Opcode },
8000     { Bad_Opcode },
8001     { Bad_Opcode },
8002     { Bad_Opcode },
8003     /* 88 */
8004     { Bad_Opcode },
8005     { Bad_Opcode },
8006     { Bad_Opcode },
8007     { Bad_Opcode },
8008     { Bad_Opcode },
8009     { Bad_Opcode },
8010     { Bad_Opcode },
8011     { Bad_Opcode },
8012     /* 90 */
8013     { Bad_Opcode },
8014     { Bad_Opcode },
8015     { Bad_Opcode },
8016     { Bad_Opcode },
8017     { Bad_Opcode },
8018     { Bad_Opcode },
8019     { Bad_Opcode },
8020     { Bad_Opcode },
8021     /* 98 */
8022     { Bad_Opcode },
8023     { Bad_Opcode },
8024     { Bad_Opcode },
8025     { Bad_Opcode },
8026     { Bad_Opcode },
8027     { Bad_Opcode },
8028     { Bad_Opcode },
8029     { Bad_Opcode },
8030     /* a0 */
8031     { Bad_Opcode },
8032     { Bad_Opcode },
8033     { Bad_Opcode },
8034     { Bad_Opcode },
8035     { Bad_Opcode },
8036     { Bad_Opcode },
8037     { Bad_Opcode },
8038     { Bad_Opcode },
8039     /* a8 */
8040     { Bad_Opcode },
8041     { Bad_Opcode },
8042     { Bad_Opcode },
8043     { Bad_Opcode },
8044     { Bad_Opcode },
8045     { Bad_Opcode },
8046     { Bad_Opcode },
8047     { Bad_Opcode },
8048     /* b0 */
8049     { Bad_Opcode },
8050     { Bad_Opcode },
8051     { Bad_Opcode },
8052     { Bad_Opcode },
8053     { Bad_Opcode },
8054     { Bad_Opcode },
8055     { Bad_Opcode },
8056     { Bad_Opcode },
8057     /* b8 */
8058     { Bad_Opcode },
8059     { Bad_Opcode },
8060     { Bad_Opcode },
8061     { Bad_Opcode },
8062     { Bad_Opcode },
8063     { Bad_Opcode },
8064     { Bad_Opcode },
8065     { Bad_Opcode },
8066     /* c0 */
8067     { Bad_Opcode },
8068     { Bad_Opcode },
8069     { Bad_Opcode },
8070     { Bad_Opcode },
8071     { Bad_Opcode },
8072     { Bad_Opcode },
8073     { Bad_Opcode },
8074     { Bad_Opcode },
8075     /* c8 */
8076     { Bad_Opcode },
8077     { Bad_Opcode },
8078     { Bad_Opcode },
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     { Bad_Opcode },
8082     { Bad_Opcode },
8083     { Bad_Opcode },
8084     /* d0 */
8085     { Bad_Opcode },
8086     { Bad_Opcode },
8087     { Bad_Opcode },
8088     { Bad_Opcode },
8089     { Bad_Opcode },
8090     { Bad_Opcode },
8091     { Bad_Opcode },
8092     { Bad_Opcode },
8093     /* d8 */
8094     { Bad_Opcode },
8095     { Bad_Opcode },
8096     { Bad_Opcode },
8097     { Bad_Opcode },
8098     { Bad_Opcode },
8099     { Bad_Opcode },
8100     { Bad_Opcode },
8101     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
8102     /* e0 */
8103     { Bad_Opcode },
8104     { Bad_Opcode },
8105     { Bad_Opcode },
8106     { Bad_Opcode },
8107     { Bad_Opcode },
8108     { Bad_Opcode },
8109     { Bad_Opcode },
8110     { Bad_Opcode },
8111     /* e8 */
8112     { Bad_Opcode },
8113     { Bad_Opcode },
8114     { Bad_Opcode },
8115     { Bad_Opcode },
8116     { Bad_Opcode },
8117     { Bad_Opcode },
8118     { Bad_Opcode },
8119     { Bad_Opcode },
8120     /* f0 */
8121     { Bad_Opcode },
8122     { Bad_Opcode },
8123     { Bad_Opcode },
8124     { Bad_Opcode },
8125     { Bad_Opcode },
8126     { Bad_Opcode },
8127     { Bad_Opcode },
8128     { Bad_Opcode },
8129     /* f8 */
8130     { Bad_Opcode },
8131     { Bad_Opcode },
8132     { Bad_Opcode },
8133     { Bad_Opcode },
8134     { Bad_Opcode },
8135     { Bad_Opcode },
8136     { Bad_Opcode },
8137     { Bad_Opcode },
8138   },
8139 };
8140
8141 static const struct dis386 vex_len_table[][2] = {
8142   /* VEX_LEN_0F10_P_1 */
8143   {
8144     { VEX_W_TABLE (VEX_W_0F10_P_1) },
8145     { VEX_W_TABLE (VEX_W_0F10_P_1) },
8146   },
8147
8148   /* VEX_LEN_0F10_P_3 */
8149   {
8150     { VEX_W_TABLE (VEX_W_0F10_P_3) },
8151     { VEX_W_TABLE (VEX_W_0F10_P_3) },
8152   },
8153
8154   /* VEX_LEN_0F11_P_1 */
8155   {
8156     { VEX_W_TABLE (VEX_W_0F11_P_1) },
8157     { VEX_W_TABLE (VEX_W_0F11_P_1) },
8158   },
8159
8160   /* VEX_LEN_0F11_P_3 */
8161   {
8162     { VEX_W_TABLE (VEX_W_0F11_P_3) },
8163     { VEX_W_TABLE (VEX_W_0F11_P_3) },
8164   },
8165
8166   /* VEX_LEN_0F12_P_0_M_0 */
8167   {
8168     { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
8169   },
8170
8171   /* VEX_LEN_0F12_P_0_M_1 */
8172   {
8173     { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
8174   },
8175
8176   /* VEX_LEN_0F12_P_2 */
8177   {
8178     { VEX_W_TABLE (VEX_W_0F12_P_2) },
8179   },
8180
8181   /* VEX_LEN_0F13_M_0 */
8182   {
8183     { VEX_W_TABLE (VEX_W_0F13_M_0) },
8184   },
8185
8186   /* VEX_LEN_0F16_P_0_M_0 */
8187   {
8188     { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
8189   },
8190
8191   /* VEX_LEN_0F16_P_0_M_1 */
8192   {
8193     { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
8194   },
8195
8196   /* VEX_LEN_0F16_P_2 */
8197   {
8198     { VEX_W_TABLE (VEX_W_0F16_P_2) },
8199   },
8200
8201   /* VEX_LEN_0F17_M_0 */
8202   {
8203     { VEX_W_TABLE (VEX_W_0F17_M_0) },
8204   },
8205
8206   /* VEX_LEN_0F2A_P_1 */
8207   {
8208     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev } },
8209     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev } },
8210   },
8211
8212   /* VEX_LEN_0F2A_P_3 */
8213   {
8214     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev } },
8215     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev } },
8216   },
8217
8218   /* VEX_LEN_0F2C_P_1 */
8219   {
8220     { "vcvttss2siY",    { Gv, EXdScalar } },
8221     { "vcvttss2siY",    { Gv, EXdScalar } },
8222   },
8223
8224   /* VEX_LEN_0F2C_P_3 */
8225   {
8226     { "vcvttsd2siY",    { Gv, EXqScalar } },
8227     { "vcvttsd2siY",    { Gv, EXqScalar } },
8228   },
8229
8230   /* VEX_LEN_0F2D_P_1 */
8231   {
8232     { "vcvtss2siY",     { Gv, EXdScalar } },
8233     { "vcvtss2siY",     { Gv, EXdScalar } },
8234   },
8235
8236   /* VEX_LEN_0F2D_P_3 */
8237   {
8238     { "vcvtsd2siY",     { Gv, EXqScalar } },
8239     { "vcvtsd2siY",     { Gv, EXqScalar } },
8240   },
8241
8242   /* VEX_LEN_0F2E_P_0 */
8243   {
8244     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
8245     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
8246   },
8247
8248   /* VEX_LEN_0F2E_P_2 */
8249   {
8250     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
8251     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
8252   },
8253
8254   /* VEX_LEN_0F2F_P_0 */
8255   {
8256     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
8257     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
8258   },
8259
8260   /* VEX_LEN_0F2F_P_2 */
8261   {
8262     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
8263     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
8264   },
8265
8266   /* VEX_LEN_0F51_P_1 */
8267   {
8268     { VEX_W_TABLE (VEX_W_0F51_P_1) },
8269     { VEX_W_TABLE (VEX_W_0F51_P_1) },
8270   },
8271
8272   /* VEX_LEN_0F51_P_3 */
8273   {
8274     { VEX_W_TABLE (VEX_W_0F51_P_3) },
8275     { VEX_W_TABLE (VEX_W_0F51_P_3) },
8276   },
8277
8278   /* VEX_LEN_0F52_P_1 */
8279   {
8280     { VEX_W_TABLE (VEX_W_0F52_P_1) },
8281     { VEX_W_TABLE (VEX_W_0F52_P_1) },
8282   },
8283
8284   /* VEX_LEN_0F53_P_1 */
8285   {
8286     { VEX_W_TABLE (VEX_W_0F53_P_1) },
8287     { VEX_W_TABLE (VEX_W_0F53_P_1) },
8288   },
8289
8290   /* VEX_LEN_0F58_P_1 */
8291   {
8292     { VEX_W_TABLE (VEX_W_0F58_P_1) },
8293     { VEX_W_TABLE (VEX_W_0F58_P_1) },
8294   },
8295
8296   /* VEX_LEN_0F58_P_3 */
8297   {
8298     { VEX_W_TABLE (VEX_W_0F58_P_3) },
8299     { VEX_W_TABLE (VEX_W_0F58_P_3) },
8300   },
8301
8302   /* VEX_LEN_0F59_P_1 */
8303   {
8304     { VEX_W_TABLE (VEX_W_0F59_P_1) },
8305     { VEX_W_TABLE (VEX_W_0F59_P_1) },
8306   },
8307
8308   /* VEX_LEN_0F59_P_3 */
8309   {
8310     { VEX_W_TABLE (VEX_W_0F59_P_3) },
8311     { VEX_W_TABLE (VEX_W_0F59_P_3) },
8312   },
8313
8314   /* VEX_LEN_0F5A_P_1 */
8315   {
8316     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
8317     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
8318   },
8319
8320   /* VEX_LEN_0F5A_P_3 */
8321   {
8322     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
8323     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
8324   },
8325
8326   /* VEX_LEN_0F5C_P_1 */
8327   {
8328     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
8329     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
8330   },
8331
8332   /* VEX_LEN_0F5C_P_3 */
8333   {
8334     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
8335     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
8336   },
8337
8338   /* VEX_LEN_0F5D_P_1 */
8339   {
8340     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
8341     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
8342   },
8343
8344   /* VEX_LEN_0F5D_P_3 */
8345   {
8346     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
8347     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
8348   },
8349
8350   /* VEX_LEN_0F5E_P_1 */
8351   {
8352     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
8353     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
8354   },
8355
8356   /* VEX_LEN_0F5E_P_3 */
8357   {
8358     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
8359     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
8360   },
8361
8362   /* VEX_LEN_0F5F_P_1 */
8363   {
8364     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
8365     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
8366   },
8367
8368   /* VEX_LEN_0F5F_P_3 */
8369   {
8370     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
8371     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
8372   },
8373
8374   /* VEX_LEN_0F60_P_2 */
8375   {
8376     { VEX_W_TABLE (VEX_W_0F60_P_2) },
8377   },
8378
8379   /* VEX_LEN_0F61_P_2 */
8380   {
8381     { VEX_W_TABLE (VEX_W_0F61_P_2) },
8382   },
8383
8384   /* VEX_LEN_0F62_P_2 */
8385   {
8386     { VEX_W_TABLE (VEX_W_0F62_P_2) },
8387   },
8388
8389   /* VEX_LEN_0F63_P_2 */
8390   {
8391     { VEX_W_TABLE (VEX_W_0F63_P_2) },
8392   },
8393
8394   /* VEX_LEN_0F64_P_2 */
8395   {
8396     { VEX_W_TABLE (VEX_W_0F64_P_2) },
8397   },
8398
8399   /* VEX_LEN_0F65_P_2 */
8400   {
8401     { VEX_W_TABLE (VEX_W_0F65_P_2) },
8402   },
8403
8404   /* VEX_LEN_0F66_P_2 */
8405   {
8406     { VEX_W_TABLE (VEX_W_0F66_P_2) },
8407   },
8408
8409   /* VEX_LEN_0F67_P_2 */
8410   {
8411     { VEX_W_TABLE (VEX_W_0F67_P_2) },
8412   },
8413
8414   /* VEX_LEN_0F68_P_2 */
8415   {
8416     { VEX_W_TABLE (VEX_W_0F68_P_2) },
8417   },
8418
8419   /* VEX_LEN_0F69_P_2 */
8420   {
8421     { VEX_W_TABLE (VEX_W_0F69_P_2) },
8422   },
8423
8424   /* VEX_LEN_0F6A_P_2 */
8425   {
8426     { VEX_W_TABLE (VEX_W_0F6A_P_2) },
8427   },
8428
8429   /* VEX_LEN_0F6B_P_2 */
8430   {
8431     { VEX_W_TABLE (VEX_W_0F6B_P_2) },
8432   },
8433
8434   /* VEX_LEN_0F6C_P_2 */
8435   {
8436     { VEX_W_TABLE (VEX_W_0F6C_P_2) },
8437   },
8438
8439   /* VEX_LEN_0F6D_P_2 */
8440   {
8441     { VEX_W_TABLE (VEX_W_0F6D_P_2) },
8442   },
8443
8444   /* VEX_LEN_0F6E_P_2 */
8445   {
8446     { "vmovK",          { XMScalar, Edq } },
8447     { "vmovK",          { XMScalar, Edq } },
8448   },
8449
8450   /* VEX_LEN_0F70_P_1 */
8451   {
8452     { VEX_W_TABLE (VEX_W_0F70_P_1) },
8453   },
8454
8455   /* VEX_LEN_0F70_P_2 */
8456   {
8457     { VEX_W_TABLE (VEX_W_0F70_P_2) },
8458   },
8459
8460   /* VEX_LEN_0F70_P_3 */
8461   {
8462     { VEX_W_TABLE (VEX_W_0F70_P_3) },
8463   },
8464
8465   /* VEX_LEN_0F71_R_2_P_2 */
8466   {
8467     { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
8468   },
8469
8470   /* VEX_LEN_0F71_R_4_P_2 */
8471   {
8472     { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
8473   },
8474
8475   /* VEX_LEN_0F71_R_6_P_2 */
8476   {
8477     { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
8478   },
8479
8480   /* VEX_LEN_0F72_R_2_P_2 */
8481   {
8482     { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
8483   },
8484
8485   /* VEX_LEN_0F72_R_4_P_2 */
8486   {
8487     { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
8488   },
8489
8490   /* VEX_LEN_0F72_R_6_P_2 */
8491   {
8492     { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
8493   },
8494
8495   /* VEX_LEN_0F73_R_2_P_2 */
8496   {
8497     { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
8498   },
8499
8500   /* VEX_LEN_0F73_R_3_P_2 */
8501   {
8502     { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
8503   },
8504
8505   /* VEX_LEN_0F73_R_6_P_2 */
8506   {
8507     { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
8508   },
8509
8510   /* VEX_LEN_0F73_R_7_P_2 */
8511   {
8512     { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
8513   },
8514
8515   /* VEX_LEN_0F74_P_2 */
8516   {
8517     { VEX_W_TABLE (VEX_W_0F74_P_2) },
8518   },
8519
8520   /* VEX_LEN_0F75_P_2 */
8521   {
8522     { VEX_W_TABLE (VEX_W_0F75_P_2) },
8523   },
8524
8525   /* VEX_LEN_0F76_P_2 */
8526   {
8527     { VEX_W_TABLE (VEX_W_0F76_P_2) },
8528   },
8529
8530   /* VEX_LEN_0F7E_P_1 */
8531   {
8532     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
8533     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
8534   },
8535
8536   /* VEX_LEN_0F7E_P_2 */
8537   {
8538     { "vmovK",          { Edq, XMScalar } },
8539     { "vmovK",          { Edq, XMScalar } },
8540   },
8541
8542   /* VEX_LEN_0FAE_R_2_M_0 */
8543   {
8544     { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
8545   },
8546
8547   /* VEX_LEN_0FAE_R_3_M_0 */
8548   {
8549     { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
8550   },
8551
8552   /* VEX_LEN_0FC2_P_1 */
8553   {
8554     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
8555     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
8556   },
8557
8558   /* VEX_LEN_0FC2_P_3 */
8559   {
8560     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
8561     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
8562   },
8563
8564   /* VEX_LEN_0FC4_P_2 */
8565   {
8566     { VEX_W_TABLE (VEX_W_0FC4_P_2) },
8567   },
8568
8569   /* VEX_LEN_0FC5_P_2 */
8570   {
8571     { VEX_W_TABLE (VEX_W_0FC5_P_2) },
8572   },
8573
8574   /* VEX_LEN_0FD1_P_2 */
8575   {
8576     { VEX_W_TABLE (VEX_W_0FD1_P_2) },
8577   },
8578
8579   /* VEX_LEN_0FD2_P_2 */
8580   {
8581     { VEX_W_TABLE (VEX_W_0FD2_P_2) },
8582   },
8583
8584   /* VEX_LEN_0FD3_P_2 */
8585   {
8586     { VEX_W_TABLE (VEX_W_0FD3_P_2) },
8587   },
8588
8589   /* VEX_LEN_0FD4_P_2 */
8590   {
8591     { VEX_W_TABLE (VEX_W_0FD4_P_2) },
8592   },
8593
8594   /* VEX_LEN_0FD5_P_2 */
8595   {
8596     { VEX_W_TABLE (VEX_W_0FD5_P_2) },
8597   },
8598
8599   /* VEX_LEN_0FD6_P_2 */
8600   {
8601     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
8602     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
8603   },
8604
8605   /* VEX_LEN_0FD7_P_2_M_1 */
8606   {
8607     { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
8608   },
8609
8610   /* VEX_LEN_0FD8_P_2 */
8611   {
8612     { VEX_W_TABLE (VEX_W_0FD8_P_2) },
8613   },
8614
8615   /* VEX_LEN_0FD9_P_2 */
8616   {
8617     { VEX_W_TABLE (VEX_W_0FD9_P_2) },
8618   },
8619
8620   /* VEX_LEN_0FDA_P_2 */
8621   {
8622     { VEX_W_TABLE (VEX_W_0FDA_P_2) },
8623   },
8624
8625   /* VEX_LEN_0FDB_P_2 */
8626   {
8627     { VEX_W_TABLE (VEX_W_0FDB_P_2) },
8628   },
8629
8630   /* VEX_LEN_0FDC_P_2 */
8631   {
8632     { VEX_W_TABLE (VEX_W_0FDC_P_2) },
8633   },
8634
8635   /* VEX_LEN_0FDD_P_2 */
8636   {
8637     { VEX_W_TABLE (VEX_W_0FDD_P_2) },
8638   },
8639
8640   /* VEX_LEN_0FDE_P_2 */
8641   {
8642     { VEX_W_TABLE (VEX_W_0FDE_P_2) },
8643   },
8644
8645   /* VEX_LEN_0FDF_P_2 */
8646   {
8647     { VEX_W_TABLE (VEX_W_0FDF_P_2) },
8648   },
8649
8650   /* VEX_LEN_0FE0_P_2 */
8651   {
8652     { VEX_W_TABLE (VEX_W_0FE0_P_2) },
8653   },
8654
8655   /* VEX_LEN_0FE1_P_2 */
8656   {
8657     { VEX_W_TABLE (VEX_W_0FE1_P_2) },
8658   },
8659
8660   /* VEX_LEN_0FE2_P_2 */
8661   {
8662     { VEX_W_TABLE (VEX_W_0FE2_P_2) },
8663   },
8664
8665   /* VEX_LEN_0FE3_P_2 */
8666   {
8667     { VEX_W_TABLE (VEX_W_0FE3_P_2) },
8668   },
8669
8670   /* VEX_LEN_0FE4_P_2 */
8671   {
8672     { VEX_W_TABLE (VEX_W_0FE4_P_2) },
8673   },
8674
8675   /* VEX_LEN_0FE5_P_2 */
8676   {
8677     { VEX_W_TABLE (VEX_W_0FE5_P_2) },
8678   },
8679
8680   /* VEX_LEN_0FE8_P_2 */
8681   {
8682     { VEX_W_TABLE (VEX_W_0FE8_P_2) },
8683   },
8684
8685   /* VEX_LEN_0FE9_P_2 */
8686   {
8687     { VEX_W_TABLE (VEX_W_0FE9_P_2) },
8688   },
8689
8690   /* VEX_LEN_0FEA_P_2 */
8691   {
8692     { VEX_W_TABLE (VEX_W_0FEA_P_2) },
8693   },
8694
8695   /* VEX_LEN_0FEB_P_2 */
8696   {
8697     { VEX_W_TABLE (VEX_W_0FEB_P_2) },
8698   },
8699
8700   /* VEX_LEN_0FEC_P_2 */
8701   {
8702     { VEX_W_TABLE (VEX_W_0FEC_P_2) },
8703   },
8704
8705   /* VEX_LEN_0FED_P_2 */
8706   {
8707     { VEX_W_TABLE (VEX_W_0FED_P_2) },
8708   },
8709
8710   /* VEX_LEN_0FEE_P_2 */
8711   {
8712     { VEX_W_TABLE (VEX_W_0FEE_P_2) },
8713   },
8714
8715   /* VEX_LEN_0FEF_P_2 */
8716   {
8717     { VEX_W_TABLE (VEX_W_0FEF_P_2) },
8718   },
8719
8720   /* VEX_LEN_0FF1_P_2 */
8721   {
8722     { VEX_W_TABLE (VEX_W_0FF1_P_2) },
8723   },
8724
8725   /* VEX_LEN_0FF2_P_2 */
8726   {
8727     { VEX_W_TABLE (VEX_W_0FF2_P_2) },
8728   },
8729
8730   /* VEX_LEN_0FF3_P_2 */
8731   {
8732     { VEX_W_TABLE (VEX_W_0FF3_P_2) },
8733   },
8734
8735   /* VEX_LEN_0FF4_P_2 */
8736   {
8737     { VEX_W_TABLE (VEX_W_0FF4_P_2) },
8738   },
8739
8740   /* VEX_LEN_0FF5_P_2 */
8741   {
8742     { VEX_W_TABLE (VEX_W_0FF5_P_2) },
8743   },
8744
8745   /* VEX_LEN_0FF6_P_2 */
8746   {
8747     { VEX_W_TABLE (VEX_W_0FF6_P_2) },
8748   },
8749
8750   /* VEX_LEN_0FF7_P_2 */
8751   {
8752     { VEX_W_TABLE (VEX_W_0FF7_P_2) },
8753   },
8754
8755   /* VEX_LEN_0FF8_P_2 */
8756   {
8757     { VEX_W_TABLE (VEX_W_0FF8_P_2) },
8758   },
8759
8760   /* VEX_LEN_0FF9_P_2 */
8761   {
8762     { VEX_W_TABLE (VEX_W_0FF9_P_2) },
8763   },
8764
8765   /* VEX_LEN_0FFA_P_2 */
8766   {
8767     { VEX_W_TABLE (VEX_W_0FFA_P_2) },
8768   },
8769
8770   /* VEX_LEN_0FFB_P_2 */
8771   {
8772     { VEX_W_TABLE (VEX_W_0FFB_P_2) },
8773   },
8774
8775   /* VEX_LEN_0FFC_P_2 */
8776   {
8777     { VEX_W_TABLE (VEX_W_0FFC_P_2) },
8778   },
8779
8780   /* VEX_LEN_0FFD_P_2 */
8781   {
8782     { VEX_W_TABLE (VEX_W_0FFD_P_2) },
8783   },
8784
8785   /* VEX_LEN_0FFE_P_2 */
8786   {
8787     { VEX_W_TABLE (VEX_W_0FFE_P_2) },
8788   },
8789
8790   /* VEX_LEN_0F3800_P_2 */
8791   {
8792     { VEX_W_TABLE (VEX_W_0F3800_P_2) },
8793   },
8794
8795   /* VEX_LEN_0F3801_P_2 */
8796   {
8797     { VEX_W_TABLE (VEX_W_0F3801_P_2) },
8798   },
8799
8800   /* VEX_LEN_0F3802_P_2 */
8801   {
8802     { VEX_W_TABLE (VEX_W_0F3802_P_2) },
8803   },
8804
8805   /* VEX_LEN_0F3803_P_2 */
8806   {
8807     { VEX_W_TABLE (VEX_W_0F3803_P_2) },
8808   },
8809
8810   /* VEX_LEN_0F3804_P_2 */
8811   {
8812     { VEX_W_TABLE (VEX_W_0F3804_P_2) },
8813   },
8814
8815   /* VEX_LEN_0F3805_P_2 */
8816   {
8817     { VEX_W_TABLE (VEX_W_0F3805_P_2) },
8818   },
8819
8820   /* VEX_LEN_0F3806_P_2 */
8821   {
8822     { VEX_W_TABLE (VEX_W_0F3806_P_2) },
8823   },
8824
8825   /* VEX_LEN_0F3807_P_2 */
8826   {
8827     { VEX_W_TABLE (VEX_W_0F3807_P_2) },
8828   },
8829
8830   /* VEX_LEN_0F3808_P_2 */
8831   {
8832     { VEX_W_TABLE (VEX_W_0F3808_P_2) },
8833   },
8834
8835   /* VEX_LEN_0F3809_P_2 */
8836   {
8837     { VEX_W_TABLE (VEX_W_0F3809_P_2) },
8838   },
8839
8840   /* VEX_LEN_0F380A_P_2 */
8841   {
8842     { VEX_W_TABLE (VEX_W_0F380A_P_2) },
8843   },
8844
8845   /* VEX_LEN_0F380B_P_2 */
8846   {
8847     { VEX_W_TABLE (VEX_W_0F380B_P_2) },
8848   },
8849
8850   /* VEX_LEN_0F3819_P_2_M_0 */
8851   {
8852     { Bad_Opcode },
8853     { VEX_W_TABLE (VEX_W_0F3819_P_2_M_0) },
8854   },
8855
8856   /* VEX_LEN_0F381A_P_2_M_0 */
8857   {
8858     { Bad_Opcode },
8859     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
8860   },
8861
8862   /* VEX_LEN_0F381C_P_2 */
8863   {
8864     { VEX_W_TABLE (VEX_W_0F381C_P_2) },
8865   },
8866
8867   /* VEX_LEN_0F381D_P_2 */
8868   {
8869     { VEX_W_TABLE (VEX_W_0F381D_P_2) },
8870   },
8871
8872   /* VEX_LEN_0F381E_P_2 */
8873   {
8874     { VEX_W_TABLE (VEX_W_0F381E_P_2) },
8875   },
8876
8877   /* VEX_LEN_0F3820_P_2 */
8878   {
8879     { VEX_W_TABLE (VEX_W_0F3820_P_2) },
8880   },
8881
8882   /* VEX_LEN_0F3821_P_2 */
8883   {
8884     { VEX_W_TABLE (VEX_W_0F3821_P_2) },
8885   },
8886
8887   /* VEX_LEN_0F3822_P_2 */
8888   {
8889     { VEX_W_TABLE (VEX_W_0F3822_P_2) },
8890   },
8891
8892   /* VEX_LEN_0F3823_P_2 */
8893   {
8894     { VEX_W_TABLE (VEX_W_0F3823_P_2) },
8895   },
8896
8897   /* VEX_LEN_0F3824_P_2 */
8898   {
8899     { VEX_W_TABLE (VEX_W_0F3824_P_2) },
8900   },
8901
8902   /* VEX_LEN_0F3825_P_2 */
8903   {
8904     { VEX_W_TABLE (VEX_W_0F3825_P_2) },
8905   },
8906
8907   /* VEX_LEN_0F3828_P_2 */
8908   {
8909     { VEX_W_TABLE (VEX_W_0F3828_P_2) },
8910   },
8911
8912   /* VEX_LEN_0F3829_P_2 */
8913   {
8914     { VEX_W_TABLE (VEX_W_0F3829_P_2) },
8915   },
8916
8917   /* VEX_LEN_0F382A_P_2_M_0 */
8918   {
8919     { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
8920   },
8921
8922   /* VEX_LEN_0F382B_P_2 */
8923   {
8924     { VEX_W_TABLE (VEX_W_0F382B_P_2) },
8925   },
8926
8927   /* VEX_LEN_0F3830_P_2 */
8928   {
8929     { VEX_W_TABLE (VEX_W_0F3830_P_2) },
8930   },
8931
8932   /* VEX_LEN_0F3831_P_2 */
8933   {
8934     { VEX_W_TABLE (VEX_W_0F3831_P_2) },
8935   },
8936
8937   /* VEX_LEN_0F3832_P_2 */
8938   {
8939     { VEX_W_TABLE (VEX_W_0F3832_P_2) },
8940   },
8941
8942   /* VEX_LEN_0F3833_P_2 */
8943   {
8944     { VEX_W_TABLE (VEX_W_0F3833_P_2) },
8945   },
8946
8947   /* VEX_LEN_0F3834_P_2 */
8948   {
8949     { VEX_W_TABLE (VEX_W_0F3834_P_2) },
8950   },
8951
8952   /* VEX_LEN_0F3835_P_2 */
8953   {
8954     { VEX_W_TABLE (VEX_W_0F3835_P_2) },
8955   },
8956
8957   /* VEX_LEN_0F3837_P_2 */
8958   {
8959     { VEX_W_TABLE (VEX_W_0F3837_P_2) },
8960   },
8961
8962   /* VEX_LEN_0F3838_P_2 */
8963   {
8964     { VEX_W_TABLE (VEX_W_0F3838_P_2) },
8965   },
8966
8967   /* VEX_LEN_0F3839_P_2 */
8968   {
8969     { VEX_W_TABLE (VEX_W_0F3839_P_2) },
8970   },
8971
8972   /* VEX_LEN_0F383A_P_2 */
8973   {
8974     { VEX_W_TABLE (VEX_W_0F383A_P_2) },
8975   },
8976
8977   /* VEX_LEN_0F383B_P_2 */
8978   {
8979     { VEX_W_TABLE (VEX_W_0F383B_P_2) },
8980   },
8981
8982   /* VEX_LEN_0F383C_P_2 */
8983   {
8984     { VEX_W_TABLE (VEX_W_0F383C_P_2) },
8985   },
8986
8987   /* VEX_LEN_0F383D_P_2 */
8988   {
8989     { VEX_W_TABLE (VEX_W_0F383D_P_2) },
8990   },
8991
8992   /* VEX_LEN_0F383E_P_2 */
8993   {
8994     { VEX_W_TABLE (VEX_W_0F383E_P_2) },
8995   },
8996
8997   /* VEX_LEN_0F383F_P_2 */
8998   {
8999     { VEX_W_TABLE (VEX_W_0F383F_P_2) },
9000   },
9001
9002   /* VEX_LEN_0F3840_P_2 */
9003   {
9004     { VEX_W_TABLE (VEX_W_0F3840_P_2) },
9005   },
9006
9007   /* VEX_LEN_0F3841_P_2 */
9008   {
9009     { VEX_W_TABLE (VEX_W_0F3841_P_2) },
9010   },
9011
9012   /* VEX_LEN_0F38DB_P_2 */
9013   {
9014     { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
9015   },
9016
9017   /* VEX_LEN_0F38DC_P_2 */
9018   {
9019     { VEX_W_TABLE (VEX_W_0F38DC_P_2) },
9020   },
9021
9022   /* VEX_LEN_0F38DD_P_2 */
9023   {
9024     { VEX_W_TABLE (VEX_W_0F38DD_P_2) },
9025   },
9026
9027   /* VEX_LEN_0F38DE_P_2 */
9028   {
9029     { VEX_W_TABLE (VEX_W_0F38DE_P_2) },
9030   },
9031
9032   /* VEX_LEN_0F38DF_P_2 */
9033   {
9034     { VEX_W_TABLE (VEX_W_0F38DF_P_2) },
9035   },
9036
9037   /* VEX_LEN_0F3A06_P_2 */
9038   {
9039     { Bad_Opcode },
9040     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
9041   },
9042
9043   /* VEX_LEN_0F3A0A_P_2 */
9044   {
9045     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
9046     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
9047   },
9048
9049   /* VEX_LEN_0F3A0B_P_2 */
9050   {
9051     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
9052     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
9053   },
9054
9055   /* VEX_LEN_0F3A0E_P_2 */
9056   {
9057     { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
9058   },
9059
9060   /* VEX_LEN_0F3A0F_P_2 */
9061   {
9062     { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
9063   },
9064
9065   /* VEX_LEN_0F3A14_P_2 */
9066   {
9067     { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
9068   },
9069
9070   /* VEX_LEN_0F3A15_P_2 */
9071   {
9072     { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
9073   },
9074
9075   /* VEX_LEN_0F3A16_P_2  */
9076   {
9077     { "vpextrK",        { Edq, XM, Ib } },
9078   },
9079
9080   /* VEX_LEN_0F3A17_P_2 */
9081   {
9082     { "vextractps",     { Edqd, XM, Ib } },
9083   },
9084
9085   /* VEX_LEN_0F3A18_P_2 */
9086   {
9087     { Bad_Opcode },
9088     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
9089   },
9090
9091   /* VEX_LEN_0F3A19_P_2 */
9092   {
9093     { Bad_Opcode },
9094     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
9095   },
9096
9097   /* VEX_LEN_0F3A20_P_2 */
9098   {
9099     { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
9100   },
9101
9102   /* VEX_LEN_0F3A21_P_2 */
9103   {
9104     { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
9105   },
9106
9107   /* VEX_LEN_0F3A22_P_2 */
9108   {
9109     { "vpinsrK",        { XM, Vex128, Edq, Ib } },
9110   },
9111
9112   /* VEX_LEN_0F3A41_P_2 */
9113   {
9114     { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
9115   },
9116
9117   /* VEX_LEN_0F3A42_P_2 */
9118   {
9119     { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
9120   },
9121
9122   /* VEX_LEN_0F3A44_P_2 */
9123   {
9124     { VEX_W_TABLE (VEX_W_0F3A44_P_2) },
9125   },
9126
9127   /* VEX_LEN_0F3A4C_P_2 */
9128   {
9129     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
9130   },
9131
9132   /* VEX_LEN_0F3A60_P_2 */
9133   {
9134     { VEX_W_TABLE (VEX_W_0F3A60_P_2) },
9135   },
9136
9137   /* VEX_LEN_0F3A61_P_2 */
9138   {
9139     { VEX_W_TABLE (VEX_W_0F3A61_P_2) },
9140   },
9141
9142   /* VEX_LEN_0F3A62_P_2 */
9143   {
9144     { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
9145   },
9146
9147   /* VEX_LEN_0F3A63_P_2 */
9148   {
9149     { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
9150   },
9151
9152   /* VEX_LEN_0F3A6A_P_2 */
9153   {
9154     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9155   },
9156
9157   /* VEX_LEN_0F3A6B_P_2 */
9158   {
9159     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9160   },
9161
9162   /* VEX_LEN_0F3A6E_P_2 */
9163   {
9164     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9165   },
9166
9167   /* VEX_LEN_0F3A6F_P_2 */
9168   {
9169     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9170   },
9171
9172   /* VEX_LEN_0F3A7A_P_2 */
9173   {
9174     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9175   },
9176
9177   /* VEX_LEN_0F3A7B_P_2 */
9178   {
9179     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9180   },
9181
9182   /* VEX_LEN_0F3A7E_P_2 */
9183   {
9184     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9185   },
9186
9187   /* VEX_LEN_0F3A7F_P_2 */
9188   {
9189     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9190   },
9191
9192   /* VEX_LEN_0F3ADF_P_2 */
9193   {
9194     { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
9195   },
9196
9197   /* VEX_LEN_0FXOP_09_80 */
9198   {
9199     { "vfrczps",        { XM, EXxmm } },
9200     { "vfrczps",        { XM, EXymmq } },
9201   },
9202
9203   /* VEX_LEN_0FXOP_09_81 */
9204   {
9205     { "vfrczpd",        { XM, EXxmm } },
9206     { "vfrczpd",        { XM, EXymmq } },
9207   },
9208 };
9209
9210 static const struct dis386 vex_w_table[][2] = {
9211   {
9212     /* VEX_W_0F10_P_0 */
9213     { "vmovups",        { XM, EXx } },
9214   },
9215   {
9216     /* VEX_W_0F10_P_1 */
9217     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar } },
9218   },
9219   {
9220     /* VEX_W_0F10_P_2 */
9221     { "vmovupd",        { XM, EXx } },
9222   },
9223   {
9224     /* VEX_W_0F10_P_3 */
9225     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar } },
9226   },
9227   {
9228     /* VEX_W_0F11_P_0 */
9229     { "vmovups",        { EXxS, XM } },
9230   },
9231   {
9232     /* VEX_W_0F11_P_1 */
9233     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar } },
9234   },
9235   {
9236     /* VEX_W_0F11_P_2 */
9237     { "vmovupd",        { EXxS, XM } },
9238   },
9239   {
9240     /* VEX_W_0F11_P_3 */
9241     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar } },
9242   },
9243   {
9244     /* VEX_W_0F12_P_0_M_0 */
9245     { "vmovlps",        { XM, Vex128, EXq } },
9246   },
9247   {
9248     /* VEX_W_0F12_P_0_M_1 */
9249     { "vmovhlps",       { XM, Vex128, EXq } },
9250   },
9251   {
9252     /* VEX_W_0F12_P_1 */
9253     { "vmovsldup",      { XM, EXx } },
9254   },
9255   {
9256     /* VEX_W_0F12_P_2 */
9257     { "vmovlpd",        { XM, Vex128, EXq } },
9258   },
9259   {
9260     /* VEX_W_0F12_P_3 */
9261     { "vmovddup",       { XM, EXymmq } },
9262   },
9263   {
9264     /* VEX_W_0F13_M_0 */
9265     { "vmovlpX",        { EXq, XM } },
9266   },
9267   {
9268     /* VEX_W_0F14 */
9269     { "vunpcklpX",      { XM, Vex, EXx } },
9270   },
9271   {
9272     /* VEX_W_0F15 */
9273     { "vunpckhpX",      { XM, Vex, EXx } },
9274   },
9275   {
9276     /* VEX_W_0F16_P_0_M_0 */
9277     { "vmovhps",        { XM, Vex128, EXq } },
9278   },
9279   {
9280     /* VEX_W_0F16_P_0_M_1 */
9281     { "vmovlhps",       { XM, Vex128, EXq } },
9282   },
9283   {
9284     /* VEX_W_0F16_P_1 */
9285     { "vmovshdup",      { XM, EXx } },
9286   },
9287   {
9288     /* VEX_W_0F16_P_2 */
9289     { "vmovhpd",        { XM, Vex128, EXq } },
9290   },
9291   {
9292     /* VEX_W_0F17_M_0 */
9293     { "vmovhpX",        { EXq, XM } },
9294   },
9295   {
9296     /* VEX_W_0F28 */
9297     { "vmovapX",        { XM, EXx } },
9298   },
9299   {
9300     /* VEX_W_0F29 */
9301     { "vmovapX",        { EXxS, XM } },
9302   },
9303   {
9304     /* VEX_W_0F2B_M_0 */
9305     { "vmovntpX",       { Mx, XM } },
9306   },
9307   {
9308     /* VEX_W_0F2E_P_0 */
9309     { "vucomiss",       { XMScalar, EXdScalar } },
9310   },
9311   {
9312     /* VEX_W_0F2E_P_2 */
9313     { "vucomisd",       { XMScalar, EXqScalar } },
9314   },
9315   {
9316     /* VEX_W_0F2F_P_0 */
9317     { "vcomiss",        { XMScalar, EXdScalar } },
9318   },
9319   {
9320     /* VEX_W_0F2F_P_2 */
9321     { "vcomisd",        { XMScalar, EXqScalar } },
9322   },
9323   {
9324     /* VEX_W_0F50_M_0 */
9325     { "vmovmskpX",      { Gdq, XS } },
9326   },
9327   {
9328     /* VEX_W_0F51_P_0 */
9329     { "vsqrtps",        { XM, EXx } },
9330   },
9331   {
9332     /* VEX_W_0F51_P_1 */
9333     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar } },
9334   },
9335   {
9336     /* VEX_W_0F51_P_2  */
9337     { "vsqrtpd",        { XM, EXx } },
9338   },
9339   {
9340     /* VEX_W_0F51_P_3 */
9341     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar } },
9342   },
9343   {
9344     /* VEX_W_0F52_P_0 */
9345     { "vrsqrtps",       { XM, EXx } },
9346   },
9347   {
9348     /* VEX_W_0F52_P_1 */
9349     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar } },
9350   },
9351   {
9352     /* VEX_W_0F53_P_0  */
9353     { "vrcpps",         { XM, EXx } },
9354   },
9355   {
9356     /* VEX_W_0F53_P_1  */
9357     { "vrcpss",         { XMScalar, VexScalar, EXdScalar } },
9358   },
9359   {
9360     /* VEX_W_0F58_P_0  */
9361     { "vaddps",         { XM, Vex, EXx } },
9362   },
9363   {
9364     /* VEX_W_0F58_P_1  */
9365     { "vaddss",         { XMScalar, VexScalar, EXdScalar } },
9366   },
9367   {
9368     /* VEX_W_0F58_P_2  */
9369     { "vaddpd",         { XM, Vex, EXx } },
9370   },
9371   {
9372     /* VEX_W_0F58_P_3  */
9373     { "vaddsd",         { XMScalar, VexScalar, EXqScalar } },
9374   },
9375   {
9376     /* VEX_W_0F59_P_0  */
9377     { "vmulps",         { XM, Vex, EXx } },
9378   },
9379   {
9380     /* VEX_W_0F59_P_1  */
9381     { "vmulss",         { XMScalar, VexScalar, EXdScalar } },
9382   },
9383   {
9384     /* VEX_W_0F59_P_2  */
9385     { "vmulpd",         { XM, Vex, EXx } },
9386   },
9387   {
9388     /* VEX_W_0F59_P_3  */
9389     { "vmulsd",         { XMScalar, VexScalar, EXqScalar } },
9390   },
9391   {
9392     /* VEX_W_0F5A_P_0  */
9393     { "vcvtps2pd",      { XM, EXxmmq } },
9394   },
9395   {
9396     /* VEX_W_0F5A_P_1  */
9397     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar } },
9398   },
9399   {
9400     /* VEX_W_0F5A_P_3  */
9401     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar } },
9402   },
9403   {
9404     /* VEX_W_0F5B_P_0  */
9405     { "vcvtdq2ps",      { XM, EXx } },
9406   },
9407   {
9408     /* VEX_W_0F5B_P_1  */
9409     { "vcvttps2dq",     { XM, EXx } },
9410   },
9411   {
9412     /* VEX_W_0F5B_P_2  */
9413     { "vcvtps2dq",      { XM, EXx } },
9414   },
9415   {
9416     /* VEX_W_0F5C_P_0  */
9417     { "vsubps",         { XM, Vex, EXx } },
9418   },
9419   {
9420     /* VEX_W_0F5C_P_1  */
9421     { "vsubss",         { XMScalar, VexScalar, EXdScalar } },
9422   },
9423   {
9424     /* VEX_W_0F5C_P_2  */
9425     { "vsubpd",         { XM, Vex, EXx } },
9426   },
9427   {
9428     /* VEX_W_0F5C_P_3  */
9429     { "vsubsd",         { XMScalar, VexScalar, EXqScalar } },
9430   },
9431   {
9432     /* VEX_W_0F5D_P_0  */
9433     { "vminps",         { XM, Vex, EXx } },
9434   },
9435   {
9436     /* VEX_W_0F5D_P_1  */
9437     { "vminss",         { XMScalar, VexScalar, EXdScalar } },
9438   },
9439   {
9440     /* VEX_W_0F5D_P_2  */
9441     { "vminpd",         { XM, Vex, EXx } },
9442   },
9443   {
9444     /* VEX_W_0F5D_P_3  */
9445     { "vminsd",         { XMScalar, VexScalar, EXqScalar } },
9446   },
9447   {
9448     /* VEX_W_0F5E_P_0  */
9449     { "vdivps",         { XM, Vex, EXx } },
9450   },
9451   {
9452     /* VEX_W_0F5E_P_1  */
9453     { "vdivss",         { XMScalar, VexScalar, EXdScalar } },
9454   },
9455   {
9456     /* VEX_W_0F5E_P_2  */
9457     { "vdivpd",         { XM, Vex, EXx } },
9458   },
9459   {
9460     /* VEX_W_0F5E_P_3  */
9461     { "vdivsd",         { XMScalar, VexScalar, EXqScalar } },
9462   },
9463   {
9464     /* VEX_W_0F5F_P_0  */
9465     { "vmaxps",         { XM, Vex, EXx } },
9466   },
9467   {
9468     /* VEX_W_0F5F_P_1  */
9469     { "vmaxss",         { XMScalar, VexScalar, EXdScalar } },
9470   },
9471   {
9472     /* VEX_W_0F5F_P_2  */
9473     { "vmaxpd",         { XM, Vex, EXx } },
9474   },
9475   {
9476     /* VEX_W_0F5F_P_3  */
9477     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar } },
9478   },
9479   {
9480     /* VEX_W_0F60_P_2  */
9481     { "vpunpcklbw",     { XM, Vex128, EXx } },
9482   },
9483   {
9484     /* VEX_W_0F61_P_2  */
9485     { "vpunpcklwd",     { XM, Vex128, EXx } },
9486   },
9487   {
9488     /* VEX_W_0F62_P_2  */
9489     { "vpunpckldq",     { XM, Vex128, EXx } },
9490   },
9491   {
9492     /* VEX_W_0F63_P_2  */
9493     { "vpacksswb",      { XM, Vex128, EXx } },
9494   },
9495   {
9496     /* VEX_W_0F64_P_2  */
9497     { "vpcmpgtb",       { XM, Vex128, EXx } },
9498   },
9499   {
9500     /* VEX_W_0F65_P_2  */
9501     { "vpcmpgtw",       { XM, Vex128, EXx } },
9502   },
9503   {
9504     /* VEX_W_0F66_P_2  */
9505     { "vpcmpgtd",       { XM, Vex128, EXx } },
9506   },
9507   {
9508     /* VEX_W_0F67_P_2  */
9509     { "vpackuswb",      { XM, Vex128, EXx } },
9510   },
9511   {
9512     /* VEX_W_0F68_P_2  */
9513     { "vpunpckhbw",     { XM, Vex128, EXx } },
9514   },
9515   {
9516     /* VEX_W_0F69_P_2  */
9517     { "vpunpckhwd",     { XM, Vex128, EXx } },
9518   },
9519   {
9520     /* VEX_W_0F6A_P_2  */
9521     { "vpunpckhdq",     { XM, Vex128, EXx } },
9522   },
9523   {
9524     /* VEX_W_0F6B_P_2  */
9525     { "vpackssdw",      { XM, Vex128, EXx } },
9526   },
9527   {
9528     /* VEX_W_0F6C_P_2  */
9529     { "vpunpcklqdq",    { XM, Vex128, EXx } },
9530   },
9531   {
9532     /* VEX_W_0F6D_P_2  */
9533     { "vpunpckhqdq",    { XM, Vex128, EXx } },
9534   },
9535   {
9536     /* VEX_W_0F6F_P_1  */
9537     { "vmovdqu",        { XM, EXx } },
9538   },
9539   {
9540     /* VEX_W_0F6F_P_2  */
9541     { "vmovdqa",        { XM, EXx } },
9542   },
9543   {
9544     /* VEX_W_0F70_P_1 */
9545     { "vpshufhw",       { XM, EXx, Ib } },
9546   },
9547   {
9548     /* VEX_W_0F70_P_2 */
9549     { "vpshufd",        { XM, EXx, Ib } },
9550   },
9551   {
9552     /* VEX_W_0F70_P_3 */
9553     { "vpshuflw",       { XM, EXx, Ib } },
9554   },
9555   {
9556     /* VEX_W_0F71_R_2_P_2  */
9557     { "vpsrlw",         { Vex128, XS, Ib } },
9558   },
9559   {
9560     /* VEX_W_0F71_R_4_P_2  */
9561     { "vpsraw",         { Vex128, XS, Ib } },
9562   },
9563   {
9564     /* VEX_W_0F71_R_6_P_2  */
9565     { "vpsllw",         { Vex128, XS, Ib } },
9566   },
9567   {
9568     /* VEX_W_0F72_R_2_P_2  */
9569     { "vpsrld",         { Vex128, XS, Ib } },
9570   },
9571   {
9572     /* VEX_W_0F72_R_4_P_2  */
9573     { "vpsrad",         { Vex128, XS, Ib } },
9574   },
9575   {
9576     /* VEX_W_0F72_R_6_P_2  */
9577     { "vpslld",         { Vex128, XS, Ib } },
9578   },
9579   {
9580     /* VEX_W_0F73_R_2_P_2  */
9581     { "vpsrlq",         { Vex128, XS, Ib } },
9582   },
9583   {
9584     /* VEX_W_0F73_R_3_P_2  */
9585     { "vpsrldq",        { Vex128, XS, Ib } },
9586   },
9587   {
9588     /* VEX_W_0F73_R_6_P_2  */
9589     { "vpsllq",         { Vex128, XS, Ib } },
9590   },
9591   {
9592     /* VEX_W_0F73_R_7_P_2  */
9593     { "vpslldq",        { Vex128, XS, Ib } },
9594   },
9595   {
9596     /* VEX_W_0F74_P_2 */
9597     { "vpcmpeqb",       { XM, Vex128, EXx } },
9598   },
9599   {
9600     /* VEX_W_0F75_P_2 */
9601     { "vpcmpeqw",       { XM, Vex128, EXx } },
9602   },
9603   {
9604     /* VEX_W_0F76_P_2 */
9605     { "vpcmpeqd",       { XM, Vex128, EXx } },
9606   },
9607   {
9608     /* VEX_W_0F77_P_0 */
9609     { "",               { VZERO } },
9610   },
9611   {
9612     /* VEX_W_0F7C_P_2 */
9613     { "vhaddpd",        { XM, Vex, EXx } },
9614   },
9615   {
9616     /* VEX_W_0F7C_P_3 */
9617     { "vhaddps",        { XM, Vex, EXx } },
9618   },
9619   {
9620     /* VEX_W_0F7D_P_2 */
9621     { "vhsubpd",        { XM, Vex, EXx } },
9622   },
9623   {
9624     /* VEX_W_0F7D_P_3 */
9625     { "vhsubps",        { XM, Vex, EXx } },
9626   },
9627   {
9628     /* VEX_W_0F7E_P_1 */
9629     { "vmovq",          { XMScalar, EXqScalar } },
9630   },
9631   {
9632     /* VEX_W_0F7F_P_1 */
9633     { "vmovdqu",        { EXxS, XM } },
9634   },
9635   {
9636     /* VEX_W_0F7F_P_2 */
9637     { "vmovdqa",        { EXxS, XM } },
9638   },
9639   {
9640     /* VEX_W_0FAE_R_2_M_0 */
9641     { "vldmxcsr",       { Md } },
9642   },
9643   {
9644     /* VEX_W_0FAE_R_3_M_0 */
9645     { "vstmxcsr",       { Md } },
9646   },
9647   {
9648     /* VEX_W_0FC2_P_0 */
9649     { "vcmpps",         { XM, Vex, EXx, VCMP } },
9650   },
9651   {
9652     /* VEX_W_0FC2_P_1 */
9653     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP } },
9654   },
9655   {
9656     /* VEX_W_0FC2_P_2 */
9657     { "vcmppd",         { XM, Vex, EXx, VCMP } },
9658   },
9659   {
9660     /* VEX_W_0FC2_P_3 */
9661     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP } },
9662   },
9663   {
9664     /* VEX_W_0FC4_P_2 */
9665     { "vpinsrw",        { XM, Vex128, Edqw, Ib } },
9666   },
9667   {
9668     /* VEX_W_0FC5_P_2 */
9669     { "vpextrw",        { Gdq, XS, Ib } },
9670   },
9671   {
9672     /* VEX_W_0FD0_P_2 */
9673     { "vaddsubpd",      { XM, Vex, EXx } },
9674   },
9675   {
9676     /* VEX_W_0FD0_P_3 */
9677     { "vaddsubps",      { XM, Vex, EXx } },
9678   },
9679   {
9680     /* VEX_W_0FD1_P_2 */
9681     { "vpsrlw",         { XM, Vex128, EXx } },
9682   },
9683   {
9684     /* VEX_W_0FD2_P_2 */
9685     { "vpsrld",         { XM, Vex128, EXx } },
9686   },
9687   {
9688     /* VEX_W_0FD3_P_2 */
9689     { "vpsrlq",         { XM, Vex128, EXx } },
9690   },
9691   {
9692     /* VEX_W_0FD4_P_2 */
9693     { "vpaddq",         { XM, Vex128, EXx } },
9694   },
9695   {
9696     /* VEX_W_0FD5_P_2 */
9697     { "vpmullw",        { XM, Vex128, EXx } },
9698   },
9699   {
9700     /* VEX_W_0FD6_P_2 */
9701     { "vmovq",          { EXqScalarS, XMScalar } },
9702   },
9703   {
9704     /* VEX_W_0FD7_P_2_M_1 */
9705     { "vpmovmskb",      { Gdq, XS } },
9706   },
9707   {
9708     /* VEX_W_0FD8_P_2 */
9709     { "vpsubusb",       { XM, Vex128, EXx } },
9710   },
9711   {
9712     /* VEX_W_0FD9_P_2 */
9713     { "vpsubusw",       { XM, Vex128, EXx } },
9714   },
9715   {
9716     /* VEX_W_0FDA_P_2 */
9717     { "vpminub",        { XM, Vex128, EXx } },
9718   },
9719   {
9720     /* VEX_W_0FDB_P_2 */
9721     { "vpand",          { XM, Vex128, EXx } },
9722   },
9723   {
9724     /* VEX_W_0FDC_P_2 */
9725     { "vpaddusb",       { XM, Vex128, EXx } },
9726   },
9727   {
9728     /* VEX_W_0FDD_P_2 */
9729     { "vpaddusw",       { XM, Vex128, EXx } },
9730   },
9731   {
9732     /* VEX_W_0FDE_P_2 */
9733     { "vpmaxub",        { XM, Vex128, EXx } },
9734   },
9735   {
9736     /* VEX_W_0FDF_P_2 */
9737     { "vpandn",         { XM, Vex128, EXx } },
9738   },
9739   {
9740     /* VEX_W_0FE0_P_2  */
9741     { "vpavgb",         { XM, Vex128, EXx } },
9742   },
9743   {
9744     /* VEX_W_0FE1_P_2  */
9745     { "vpsraw",         { XM, Vex128, EXx } },
9746   },
9747   {
9748     /* VEX_W_0FE2_P_2  */
9749     { "vpsrad",         { XM, Vex128, EXx } },
9750   },
9751   {
9752     /* VEX_W_0FE3_P_2  */
9753     { "vpavgw",         { XM, Vex128, EXx } },
9754   },
9755   {
9756     /* VEX_W_0FE4_P_2  */
9757     { "vpmulhuw",       { XM, Vex128, EXx } },
9758   },
9759   {
9760     /* VEX_W_0FE5_P_2  */
9761     { "vpmulhw",        { XM, Vex128, EXx } },
9762   },
9763   {
9764     /* VEX_W_0FE6_P_1  */
9765     { "vcvtdq2pd",      { XM, EXxmmq } },
9766   },
9767   {
9768     /* VEX_W_0FE6_P_2  */
9769     { "vcvttpd2dq%XY",  { XMM, EXx } },
9770   },
9771   {
9772     /* VEX_W_0FE6_P_3  */
9773     { "vcvtpd2dq%XY",   { XMM, EXx } },
9774   },
9775   {
9776     /* VEX_W_0FE7_P_2_M_0 */
9777     { "vmovntdq",       { Mx, XM } },
9778   },
9779   {
9780     /* VEX_W_0FE8_P_2  */
9781     { "vpsubsb",        { XM, Vex128, EXx } },
9782   },
9783   {
9784     /* VEX_W_0FE9_P_2  */
9785     { "vpsubsw",        { XM, Vex128, EXx } },
9786   },
9787   {
9788     /* VEX_W_0FEA_P_2  */
9789     { "vpminsw",        { XM, Vex128, EXx } },
9790   },
9791   {
9792     /* VEX_W_0FEB_P_2  */
9793     { "vpor",           { XM, Vex128, EXx } },
9794   },
9795   {
9796     /* VEX_W_0FEC_P_2  */
9797     { "vpaddsb",        { XM, Vex128, EXx } },
9798   },
9799   {
9800     /* VEX_W_0FED_P_2  */
9801     { "vpaddsw",        { XM, Vex128, EXx } },
9802   },
9803   {
9804     /* VEX_W_0FEE_P_2  */
9805     { "vpmaxsw",        { XM, Vex128, EXx } },
9806   },
9807   {
9808     /* VEX_W_0FEF_P_2  */
9809     { "vpxor",          { XM, Vex128, EXx } },
9810   },
9811   {
9812     /* VEX_W_0FF0_P_3_M_0 */
9813     { "vlddqu",         { XM, M } },
9814   },
9815   {
9816     /* VEX_W_0FF1_P_2 */
9817     { "vpsllw",         { XM, Vex128, EXx } },
9818   },
9819   {
9820     /* VEX_W_0FF2_P_2 */
9821     { "vpslld",         { XM, Vex128, EXx } },
9822   },
9823   {
9824     /* VEX_W_0FF3_P_2 */
9825     { "vpsllq",         { XM, Vex128, EXx } },
9826   },
9827   {
9828     /* VEX_W_0FF4_P_2 */
9829     { "vpmuludq",       { XM, Vex128, EXx } },
9830   },
9831   {
9832     /* VEX_W_0FF5_P_2 */
9833     { "vpmaddwd",       { XM, Vex128, EXx } },
9834   },
9835   {
9836     /* VEX_W_0FF6_P_2 */
9837     { "vpsadbw",        { XM, Vex128, EXx } },
9838   },
9839   {
9840     /* VEX_W_0FF7_P_2 */
9841     { "vmaskmovdqu",    { XM, XS } },
9842   },
9843   {
9844     /* VEX_W_0FF8_P_2 */
9845     { "vpsubb",         { XM, Vex128, EXx } },
9846   },
9847   {
9848     /* VEX_W_0FF9_P_2 */
9849     { "vpsubw",         { XM, Vex128, EXx } },
9850   },
9851   {
9852     /* VEX_W_0FFA_P_2 */
9853     { "vpsubd",         { XM, Vex128, EXx } },
9854   },
9855   {
9856     /* VEX_W_0FFB_P_2 */
9857     { "vpsubq",         { XM, Vex128, EXx } },
9858   },
9859   {
9860     /* VEX_W_0FFC_P_2 */
9861     { "vpaddb",         { XM, Vex128, EXx } },
9862   },
9863   {
9864     /* VEX_W_0FFD_P_2 */
9865     { "vpaddw",         { XM, Vex128, EXx } },
9866   },
9867   {
9868     /* VEX_W_0FFE_P_2 */
9869     { "vpaddd",         { XM, Vex128, EXx } },
9870   },
9871   {
9872     /* VEX_W_0F3800_P_2  */
9873     { "vpshufb",        { XM, Vex128, EXx } },
9874   },
9875   {
9876     /* VEX_W_0F3801_P_2  */
9877     { "vphaddw",        { XM, Vex128, EXx } },
9878   },
9879   {
9880     /* VEX_W_0F3802_P_2  */
9881     { "vphaddd",        { XM, Vex128, EXx } },
9882   },
9883   {
9884     /* VEX_W_0F3803_P_2  */
9885     { "vphaddsw",       { XM, Vex128, EXx } },
9886   },
9887   {
9888     /* VEX_W_0F3804_P_2  */
9889     { "vpmaddubsw",     { XM, Vex128, EXx } },
9890   },
9891   {
9892     /* VEX_W_0F3805_P_2  */
9893     { "vphsubw",        { XM, Vex128, EXx } },
9894   },
9895   {
9896     /* VEX_W_0F3806_P_2  */
9897     { "vphsubd",        { XM, Vex128, EXx } },
9898   },
9899   {
9900     /* VEX_W_0F3807_P_2  */
9901     { "vphsubsw",       { XM, Vex128, EXx } },
9902   },
9903   {
9904     /* VEX_W_0F3808_P_2  */
9905     { "vpsignb",        { XM, Vex128, EXx } },
9906   },
9907   {
9908     /* VEX_W_0F3809_P_2  */
9909     { "vpsignw",        { XM, Vex128, EXx } },
9910   },
9911   {
9912     /* VEX_W_0F380A_P_2  */
9913     { "vpsignd",        { XM, Vex128, EXx } },
9914   },
9915   {
9916     /* VEX_W_0F380B_P_2  */
9917     { "vpmulhrsw",      { XM, Vex128, EXx } },
9918   },
9919   {
9920     /* VEX_W_0F380C_P_2  */
9921     { "vpermilps",      { XM, Vex, EXx } },
9922   },
9923   {
9924     /* VEX_W_0F380D_P_2  */
9925     { "vpermilpd",      { XM, Vex, EXx } },
9926   },
9927   {
9928     /* VEX_W_0F380E_P_2  */
9929     { "vtestps",        { XM, EXx } },
9930   },
9931   {
9932     /* VEX_W_0F380F_P_2  */
9933     { "vtestpd",        { XM, EXx } },
9934   },
9935   {
9936     /* VEX_W_0F3817_P_2 */
9937     { "vptest",         { XM, EXx } },
9938   },
9939   {
9940     /* VEX_W_0F3818_P_2_M_0 */
9941     { "vbroadcastss",   { XM, Md } },
9942   },
9943   {
9944     /* VEX_W_0F3819_P_2_M_0 */
9945     { "vbroadcastsd",   { XM, Mq } },
9946   },
9947   {
9948     /* VEX_W_0F381A_P_2_M_0 */
9949     { "vbroadcastf128", { XM, Mxmm } },
9950   },
9951   {
9952     /* VEX_W_0F381C_P_2 */
9953     { "vpabsb",         { XM, EXx } },
9954   },
9955   {
9956     /* VEX_W_0F381D_P_2 */
9957     { "vpabsw",         { XM, EXx } },
9958   },
9959   {
9960     /* VEX_W_0F381E_P_2 */
9961     { "vpabsd",         { XM, EXx } },
9962   },
9963   {
9964     /* VEX_W_0F3820_P_2 */
9965     { "vpmovsxbw",      { XM, EXq } },
9966   },
9967   {
9968     /* VEX_W_0F3821_P_2 */
9969     { "vpmovsxbd",      { XM, EXd } },
9970   },
9971   {
9972     /* VEX_W_0F3822_P_2 */
9973     { "vpmovsxbq",      { XM, EXw } },
9974   },
9975   {
9976     /* VEX_W_0F3823_P_2 */
9977     { "vpmovsxwd",      { XM, EXq } },
9978   },
9979   {
9980     /* VEX_W_0F3824_P_2 */
9981     { "vpmovsxwq",      { XM, EXd } },
9982   },
9983   {
9984     /* VEX_W_0F3825_P_2 */
9985     { "vpmovsxdq",      { XM, EXq } },
9986   },
9987   {
9988     /* VEX_W_0F3828_P_2 */
9989     { "vpmuldq",        { XM, Vex128, EXx } },
9990   },
9991   {
9992     /* VEX_W_0F3829_P_2 */
9993     { "vpcmpeqq",       { XM, Vex128, EXx } },
9994   },
9995   {
9996     /* VEX_W_0F382A_P_2_M_0 */
9997     { "vmovntdqa",      { XM, Mx } },
9998   },
9999   {
10000     /* VEX_W_0F382B_P_2 */
10001     { "vpackusdw",      { XM, Vex128, EXx } },
10002   },
10003   {
10004     /* VEX_W_0F382C_P_2_M_0 */
10005     { "vmaskmovps",     { XM, Vex, Mx } },
10006   },
10007   {
10008     /* VEX_W_0F382D_P_2_M_0 */
10009     { "vmaskmovpd",     { XM, Vex, Mx } },
10010   },
10011   {
10012     /* VEX_W_0F382E_P_2_M_0 */
10013     { "vmaskmovps",     { Mx, Vex, XM } },
10014   },
10015   {
10016     /* VEX_W_0F382F_P_2_M_0 */
10017     { "vmaskmovpd",     { Mx, Vex, XM } },
10018   },
10019   {
10020     /* VEX_W_0F3830_P_2 */
10021     { "vpmovzxbw",      { XM, EXq } },
10022   },
10023   {
10024     /* VEX_W_0F3831_P_2 */
10025     { "vpmovzxbd",      { XM, EXd } },
10026   },
10027   {
10028     /* VEX_W_0F3832_P_2 */
10029     { "vpmovzxbq",      { XM, EXw } },
10030   },
10031   {
10032     /* VEX_W_0F3833_P_2 */
10033     { "vpmovzxwd",      { XM, EXq } },
10034   },
10035   {
10036     /* VEX_W_0F3834_P_2 */
10037     { "vpmovzxwq",      { XM, EXd } },
10038   },
10039   {
10040     /* VEX_W_0F3835_P_2 */
10041     { "vpmovzxdq",      { XM, EXq } },
10042   },
10043   {
10044     /* VEX_W_0F3837_P_2 */
10045     { "vpcmpgtq",       { XM, Vex128, EXx } },
10046   },
10047   {
10048     /* VEX_W_0F3838_P_2 */
10049     { "vpminsb",        { XM, Vex128, EXx } },
10050   },
10051   {
10052     /* VEX_W_0F3839_P_2 */
10053     { "vpminsd",        { XM, Vex128, EXx } },
10054   },
10055   {
10056     /* VEX_W_0F383A_P_2 */
10057     { "vpminuw",        { XM, Vex128, EXx } },
10058   },
10059   {
10060     /* VEX_W_0F383B_P_2 */
10061     { "vpminud",        { XM, Vex128, EXx } },
10062   },
10063   {
10064     /* VEX_W_0F383C_P_2 */
10065     { "vpmaxsb",        { XM, Vex128, EXx } },
10066   },
10067   {
10068     /* VEX_W_0F383D_P_2 */
10069     { "vpmaxsd",        { XM, Vex128, EXx } },
10070   },
10071   {
10072     /* VEX_W_0F383E_P_2 */
10073     { "vpmaxuw",        { XM, Vex128, EXx } },
10074   },
10075   {
10076     /* VEX_W_0F383F_P_2 */
10077     { "vpmaxud",        { XM, Vex128, EXx } },
10078   },
10079   {
10080     /* VEX_W_0F3840_P_2 */
10081     { "vpmulld",        { XM, Vex128, EXx } },
10082   },
10083   {
10084     /* VEX_W_0F3841_P_2 */
10085     { "vphminposuw",    { XM, EXx } },
10086   },
10087   {
10088     /* VEX_W_0F38DB_P_2 */
10089     { "vaesimc",        { XM, EXx } },
10090   },
10091   {
10092     /* VEX_W_0F38DC_P_2 */
10093     { "vaesenc",        { XM, Vex128, EXx } },
10094   },
10095   {
10096     /* VEX_W_0F38DD_P_2 */
10097     { "vaesenclast",    { XM, Vex128, EXx } },
10098   },
10099   {
10100     /* VEX_W_0F38DE_P_2 */
10101     { "vaesdec",        { XM, Vex128, EXx } },
10102   },
10103   {
10104     /* VEX_W_0F38DF_P_2 */
10105     { "vaesdeclast",    { XM, Vex128, EXx } },
10106   },
10107   {
10108     /* VEX_W_0F3A04_P_2 */
10109     { "vpermilps",      { XM, EXx, Ib } },
10110   },
10111   {
10112     /* VEX_W_0F3A05_P_2 */
10113     { "vpermilpd",      { XM, EXx, Ib } },
10114   },
10115   {
10116     /* VEX_W_0F3A06_P_2 */
10117     { "vperm2f128",     { XM, Vex256, EXx, Ib } },
10118   },
10119   {
10120     /* VEX_W_0F3A08_P_2 */
10121     { "vroundps",       { XM, EXx, Ib } },
10122   },
10123   {
10124     /* VEX_W_0F3A09_P_2 */
10125     { "vroundpd",       { XM, EXx, Ib } },
10126   },
10127   {
10128     /* VEX_W_0F3A0A_P_2 */
10129     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib } },
10130   },
10131   {
10132     /* VEX_W_0F3A0B_P_2 */
10133     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib } },
10134   },
10135   {
10136     /* VEX_W_0F3A0C_P_2 */
10137     { "vblendps",       { XM, Vex, EXx, Ib } },
10138   },
10139   {
10140     /* VEX_W_0F3A0D_P_2 */
10141     { "vblendpd",       { XM, Vex, EXx, Ib } },
10142   },
10143   {
10144     /* VEX_W_0F3A0E_P_2 */
10145     { "vpblendw",       { XM, Vex128, EXx, Ib } },
10146   },
10147   {
10148     /* VEX_W_0F3A0F_P_2 */
10149     { "vpalignr",       { XM, Vex128, EXx, Ib } },
10150   },
10151   {
10152     /* VEX_W_0F3A14_P_2 */
10153     { "vpextrb",        { Edqb, XM, Ib } },
10154   },
10155   {
10156     /* VEX_W_0F3A15_P_2 */
10157     { "vpextrw",        { Edqw, XM, Ib } },
10158   },
10159   {
10160     /* VEX_W_0F3A18_P_2 */
10161     { "vinsertf128",    { XM, Vex256, EXxmm, Ib } },
10162   },
10163   {
10164     /* VEX_W_0F3A19_P_2 */
10165     { "vextractf128",   { EXxmm, XM, Ib } },
10166   },
10167   {
10168     /* VEX_W_0F3A20_P_2 */
10169     { "vpinsrb",        { XM, Vex128, Edqb, Ib } },
10170   },
10171   {
10172     /* VEX_W_0F3A21_P_2 */
10173     { "vinsertps",      { XM, Vex128, EXd, Ib } },
10174   },
10175   {
10176     /* VEX_W_0F3A40_P_2 */
10177     { "vdpps",          { XM, Vex, EXx, Ib } },
10178   },
10179   {
10180     /* VEX_W_0F3A41_P_2 */
10181     { "vdppd",          { XM, Vex128, EXx, Ib } },
10182   },
10183   {
10184     /* VEX_W_0F3A42_P_2 */
10185     { "vmpsadbw",       { XM, Vex128, EXx, Ib } },
10186   },
10187   {
10188     /* VEX_W_0F3A44_P_2 */
10189     { "vpclmulqdq",     { XM, Vex128, EXx, PCLMUL } },
10190   },
10191   {
10192     /* VEX_W_0F3A48_P_2 */
10193     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10194     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10195   },
10196   {
10197     /* VEX_W_0F3A49_P_2 */
10198     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10199     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10200   },
10201   {
10202     /* VEX_W_0F3A4A_P_2 */
10203     { "vblendvps",      { XM, Vex, EXx, XMVexI4 } },
10204   },
10205   {
10206     /* VEX_W_0F3A4B_P_2 */
10207     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 } },
10208   },
10209   {
10210     /* VEX_W_0F3A4C_P_2 */
10211     { "vpblendvb",      { XM, Vex128, EXx, XMVexI4 } },
10212   },
10213   {
10214     /* VEX_W_0F3A60_P_2 */
10215     { "vpcmpestrm",     { XM, EXx, Ib } },
10216   },
10217   {
10218     /* VEX_W_0F3A61_P_2 */
10219     { "vpcmpestri",     { XM, EXx, Ib } },
10220   },
10221   {
10222     /* VEX_W_0F3A62_P_2 */
10223     { "vpcmpistrm",     { XM, EXx, Ib } },
10224   },
10225   {
10226     /* VEX_W_0F3A63_P_2 */
10227     { "vpcmpistri",     { XM, EXx, Ib } },
10228   },
10229   {
10230     /* VEX_W_0F3ADF_P_2 */
10231     { "vaeskeygenassist", { XM, EXx, Ib } },
10232   },
10233 };
10234
10235 static const struct dis386 mod_table[][2] = {
10236   {
10237     /* MOD_8D */
10238     { "leaS",           { Gv, M } },
10239   },
10240   {
10241     /* MOD_0F01_REG_0 */
10242     { X86_64_TABLE (X86_64_0F01_REG_0) },
10243     { RM_TABLE (RM_0F01_REG_0) },
10244   },
10245   {
10246     /* MOD_0F01_REG_1 */
10247     { X86_64_TABLE (X86_64_0F01_REG_1) },
10248     { RM_TABLE (RM_0F01_REG_1) },
10249   },
10250   {
10251     /* MOD_0F01_REG_2 */
10252     { X86_64_TABLE (X86_64_0F01_REG_2) },
10253     { RM_TABLE (RM_0F01_REG_2) },
10254   },
10255   {
10256     /* MOD_0F01_REG_3 */
10257     { X86_64_TABLE (X86_64_0F01_REG_3) },
10258     { RM_TABLE (RM_0F01_REG_3) },
10259   },
10260   {
10261     /* MOD_0F01_REG_7 */
10262     { "invlpg",         { Mb } },
10263     { RM_TABLE (RM_0F01_REG_7) },
10264   },
10265   {
10266     /* MOD_0F12_PREFIX_0 */
10267     { "movlps",         { XM, EXq } },
10268     { "movhlps",        { XM, EXq } },
10269   },
10270   {
10271     /* MOD_0F13 */
10272     { "movlpX",         { EXq, XM } },
10273   },
10274   {
10275     /* MOD_0F16_PREFIX_0 */
10276     { "movhps",         { XM, EXq } },
10277     { "movlhps",        { XM, EXq } },
10278   },
10279   {
10280     /* MOD_0F17 */
10281     { "movhpX",         { EXq, XM } },
10282   },
10283   {
10284     /* MOD_0F18_REG_0 */
10285     { "prefetchnta",    { Mb } },
10286   },
10287   {
10288     /* MOD_0F18_REG_1 */
10289     { "prefetcht0",     { Mb } },
10290   },
10291   {
10292     /* MOD_0F18_REG_2 */
10293     { "prefetcht1",     { Mb } },
10294   },
10295   {
10296     /* MOD_0F18_REG_3 */
10297     { "prefetcht2",     { Mb } },
10298   },
10299   {
10300     /* MOD_0F20 */
10301     { Bad_Opcode },
10302     { "movZ",           { Rm, Cm } },
10303   },
10304   {
10305     /* MOD_0F21 */
10306     { Bad_Opcode },
10307     { "movZ",           { Rm, Dm } },
10308   },
10309   {
10310     /* MOD_0F22 */
10311     { Bad_Opcode },
10312     { "movZ",           { Cm, Rm } },
10313   },
10314   {
10315     /* MOD_0F23 */
10316     { Bad_Opcode },
10317     { "movZ",           { Dm, Rm } },
10318   },
10319   {
10320     /* MOD_0F24 */
10321     { Bad_Opcode },
10322     { "movL",           { Rd, Td } },
10323   },
10324   {
10325     /* MOD_0F26 */
10326     { Bad_Opcode },
10327     { "movL",           { Td, Rd } },
10328   },
10329   {
10330     /* MOD_0F2B_PREFIX_0 */
10331     {"movntps",         { Mx, XM } },
10332   },
10333   {
10334     /* MOD_0F2B_PREFIX_1 */
10335     {"movntss",         { Md, XM } },
10336   },
10337   {
10338     /* MOD_0F2B_PREFIX_2 */
10339     {"movntpd",         { Mx, XM } },
10340   },
10341   {
10342     /* MOD_0F2B_PREFIX_3 */
10343     {"movntsd",         { Mq, XM } },
10344   },
10345   {
10346     /* MOD_0F51 */
10347     { Bad_Opcode },
10348     { "movmskpX",       { Gdq, XS } },
10349   },
10350   {
10351     /* MOD_0F71_REG_2 */
10352     { Bad_Opcode },
10353     { "psrlw",          { MS, Ib } },
10354   },
10355   {
10356     /* MOD_0F71_REG_4 */
10357     { Bad_Opcode },
10358     { "psraw",          { MS, Ib } },
10359   },
10360   {
10361     /* MOD_0F71_REG_6 */
10362     { Bad_Opcode },
10363     { "psllw",          { MS, Ib } },
10364   },
10365   {
10366     /* MOD_0F72_REG_2 */
10367     { Bad_Opcode },
10368     { "psrld",          { MS, Ib } },
10369   },
10370   {
10371     /* MOD_0F72_REG_4 */
10372     { Bad_Opcode },
10373     { "psrad",          { MS, Ib } },
10374   },
10375   {
10376     /* MOD_0F72_REG_6 */
10377     { Bad_Opcode },
10378     { "pslld",          { MS, Ib } },
10379   },
10380   {
10381     /* MOD_0F73_REG_2 */
10382     { Bad_Opcode },
10383     { "psrlq",          { MS, Ib } },
10384   },
10385   {
10386     /* MOD_0F73_REG_3 */
10387     { Bad_Opcode },
10388     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
10389   },
10390   {
10391     /* MOD_0F73_REG_6 */
10392     { Bad_Opcode },
10393     { "psllq",          { MS, Ib } },
10394   },
10395   {
10396     /* MOD_0F73_REG_7 */
10397     { Bad_Opcode },
10398     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
10399   },
10400   {
10401     /* MOD_0FAE_REG_0 */
10402     { "fxsave",         { FXSAVE } },
10403     { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
10404   },
10405   {
10406     /* MOD_0FAE_REG_1 */
10407     { "fxrstor",        { FXSAVE } },
10408     { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
10409   },
10410   {
10411     /* MOD_0FAE_REG_2 */
10412     { "ldmxcsr",        { Md } },
10413     { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
10414   },
10415   {
10416     /* MOD_0FAE_REG_3 */
10417     { "stmxcsr",        { Md } },
10418     { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
10419   },
10420   {
10421     /* MOD_0FAE_REG_4 */
10422     { "xsave",          { FXSAVE } },
10423   },
10424   {
10425     /* MOD_0FAE_REG_5 */
10426     { "xrstor",         { FXSAVE } },
10427     { RM_TABLE (RM_0FAE_REG_5) },
10428   },
10429   {
10430     /* MOD_0FAE_REG_6 */
10431     { "xsaveopt",       { FXSAVE } },
10432     { RM_TABLE (RM_0FAE_REG_6) },
10433   },
10434   {
10435     /* MOD_0FAE_REG_7 */
10436     { "clflush",        { Mb } },
10437     { RM_TABLE (RM_0FAE_REG_7) },
10438   },
10439   {
10440     /* MOD_0FB2 */
10441     { "lssS",           { Gv, Mp } },
10442   },
10443   {
10444     /* MOD_0FB4 */
10445     { "lfsS",           { Gv, Mp } },
10446   },
10447   {
10448     /* MOD_0FB5 */
10449     { "lgsS",           { Gv, Mp } },
10450   },
10451   {
10452     /* MOD_0FC7_REG_6 */
10453     { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
10454     { "rdrand",         { Ev } },
10455   },
10456   {
10457     /* MOD_0FC7_REG_7 */
10458     { "vmptrst",        { Mq } },
10459   },
10460   {
10461     /* MOD_0FD7 */
10462     { Bad_Opcode },
10463     { "pmovmskb",       { Gdq, MS } },
10464   },
10465   {
10466     /* MOD_0FE7_PREFIX_2 */
10467     { "movntdq",        { Mx, XM } },
10468   },
10469   {
10470     /* MOD_0FF0_PREFIX_3 */
10471     { "lddqu",          { XM, M } },
10472   },
10473   {
10474     /* MOD_0F382A_PREFIX_2 */
10475     { "movntdqa",       { XM, Mx } },
10476   },
10477   {
10478     /* MOD_62_32BIT */
10479     { "bound{S|}",      { Gv, Ma } },
10480   },
10481   {
10482     /* MOD_C4_32BIT */
10483     { "lesS",           { Gv, Mp } },
10484     { VEX_C4_TABLE (VEX_0F) },
10485   },
10486   {
10487     /* MOD_C5_32BIT */
10488     { "ldsS",           { Gv, Mp } },
10489     { VEX_C5_TABLE (VEX_0F) },
10490   },
10491   {
10492     /* MOD_VEX_0F12_PREFIX_0 */
10493     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
10494     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
10495   },
10496   {
10497     /* MOD_VEX_0F13 */
10498     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
10499   },
10500   {
10501     /* MOD_VEX_0F16_PREFIX_0 */
10502     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
10503     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
10504   },
10505   {
10506     /* MOD_VEX_0F17 */
10507     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
10508   },
10509   {
10510     /* MOD_VEX_0F2B */
10511     { VEX_W_TABLE (VEX_W_0F2B_M_0) },
10512   },
10513   {
10514     /* MOD_VEX_0F50 */
10515     { Bad_Opcode },
10516     { VEX_W_TABLE (VEX_W_0F50_M_0) },
10517   },
10518   {
10519     /* MOD_VEX_0F71_REG_2 */
10520     { Bad_Opcode },
10521     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
10522   },
10523   {
10524     /* MOD_VEX_0F71_REG_4 */
10525     { Bad_Opcode },
10526     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
10527   },
10528   {
10529     /* MOD_VEX_0F71_REG_6 */
10530     { Bad_Opcode },
10531     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
10532   },
10533   {
10534     /* MOD_VEX_0F72_REG_2 */
10535     { Bad_Opcode },
10536     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
10537   },
10538   {
10539     /* MOD_VEX_0F72_REG_4 */
10540     { Bad_Opcode },
10541     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
10542   },
10543   {
10544     /* MOD_VEX_0F72_REG_6 */
10545     { Bad_Opcode },
10546     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
10547   },
10548   {
10549     /* MOD_VEX_0F73_REG_2 */
10550     { Bad_Opcode },
10551     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
10552   },
10553   {
10554     /* MOD_VEX_0F73_REG_3 */
10555     { Bad_Opcode },
10556     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
10557   },
10558   {
10559     /* MOD_VEX_0F73_REG_6 */
10560     { Bad_Opcode },
10561     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
10562   },
10563   {
10564     /* MOD_VEX_0F73_REG_7 */
10565     { Bad_Opcode },
10566     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
10567   },
10568   {
10569     /* MOD_VEX_0FAE_REG_2 */
10570     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
10571   },
10572   {
10573     /* MOD_VEX_0FAE_REG_3 */
10574     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
10575   },
10576   {
10577     /* MOD_VEX_0FD7_PREFIX_2 */
10578     { Bad_Opcode },
10579     { VEX_LEN_TABLE (VEX_LEN_0FD7_P_2_M_1) },
10580   },
10581   {
10582     /* MOD_VEX_0FE7_PREFIX_2 */
10583     { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
10584   },
10585   {
10586     /* MOD_VEX_0FF0_PREFIX_3 */
10587     { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
10588   },
10589   {
10590     /* MOD_VEX_0F3818_PREFIX_2 */
10591     { VEX_W_TABLE (VEX_W_0F3818_P_2_M_0) },
10592   },
10593   {
10594     /* MOD_VEX_0F3819_PREFIX_2 */
10595     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2_M_0) },
10596   },
10597   {
10598     /* MOD_VEX_0F381A_PREFIX_2 */
10599     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
10600   },
10601   {
10602     /* MOD_VEX_0F382A_PREFIX_2 */
10603     { VEX_LEN_TABLE (VEX_LEN_0F382A_P_2_M_0) },
10604   },
10605   {
10606     /* MOD_VEX_0F382C_PREFIX_2 */
10607     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
10608   },
10609   {
10610     /* MOD_VEX_0F382D_PREFIX_2 */
10611     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
10612   },
10613   {
10614     /* MOD_VEX_0F382E_PREFIX_2 */
10615     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
10616   },
10617   {
10618     /* MOD_VEX_0F382F_PREFIX_2 */
10619     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
10620   },
10621 };
10622
10623 static const struct dis386 rm_table[][8] = {
10624   {
10625     /* RM_0F01_REG_0 */
10626     { Bad_Opcode },
10627     { "vmcall",         { Skip_MODRM } },
10628     { "vmlaunch",       { Skip_MODRM } },
10629     { "vmresume",       { Skip_MODRM } },
10630     { "vmxoff",         { Skip_MODRM } },
10631   },
10632   {
10633     /* RM_0F01_REG_1 */
10634     { "monitor",        { { OP_Monitor, 0 } } },
10635     { "mwait",          { { OP_Mwait, 0 } } },
10636   },
10637   {
10638     /* RM_0F01_REG_2 */
10639     { "xgetbv",         { Skip_MODRM } },
10640     { "xsetbv",         { Skip_MODRM } },
10641   },
10642   {
10643     /* RM_0F01_REG_3 */
10644     { "vmrun",          { Skip_MODRM } },
10645     { "vmmcall",        { Skip_MODRM } },
10646     { "vmload",         { Skip_MODRM } },
10647     { "vmsave",         { Skip_MODRM } },
10648     { "stgi",           { Skip_MODRM } },
10649     { "clgi",           { Skip_MODRM } },
10650     { "skinit",         { Skip_MODRM } },
10651     { "invlpga",        { Skip_MODRM } },
10652   },
10653   {
10654     /* RM_0F01_REG_7 */
10655     { "swapgs",         { Skip_MODRM } },
10656     { "rdtscp",         { Skip_MODRM } },
10657   },
10658   {
10659     /* RM_0FAE_REG_5 */
10660     { "lfence",         { Skip_MODRM } },
10661   },
10662   {
10663     /* RM_0FAE_REG_6 */
10664     { "mfence",         { Skip_MODRM } },
10665   },
10666   {
10667     /* RM_0FAE_REG_7 */
10668     { "sfence",         { Skip_MODRM } },
10669   },
10670 };
10671
10672 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
10673
10674 /* We use the high bit to indicate different name for the same
10675    prefix.  */
10676 #define ADDR16_PREFIX   (0x67 | 0x100)
10677 #define ADDR32_PREFIX   (0x67 | 0x200)
10678 #define DATA16_PREFIX   (0x66 | 0x100)
10679 #define DATA32_PREFIX   (0x66 | 0x200)
10680 #define REP_PREFIX      (0xf3 | 0x100)
10681
10682 static int
10683 ckprefix (void)
10684 {
10685   int newrex, i, length;
10686   rex = 0;
10687   rex_ignored = 0;
10688   prefixes = 0;
10689   used_prefixes = 0;
10690   rex_used = 0;
10691   last_lock_prefix = -1;
10692   last_repz_prefix = -1;
10693   last_repnz_prefix = -1;
10694   last_data_prefix = -1;
10695   last_addr_prefix = -1;
10696   last_rex_prefix = -1;
10697   last_seg_prefix = -1;
10698   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
10699     all_prefixes[i] = 0;
10700   i = 0;
10701   length = 0;
10702   /* The maximum instruction length is 15bytes.  */
10703   while (length < MAX_CODE_LENGTH - 1)
10704     {
10705       FETCH_DATA (the_info, codep + 1);
10706       newrex = 0;
10707       switch (*codep)
10708         {
10709         /* REX prefixes family.  */
10710         case 0x40:
10711         case 0x41:
10712         case 0x42:
10713         case 0x43:
10714         case 0x44:
10715         case 0x45:
10716         case 0x46:
10717         case 0x47:
10718         case 0x48:
10719         case 0x49:
10720         case 0x4a:
10721         case 0x4b:
10722         case 0x4c:
10723         case 0x4d:
10724         case 0x4e:
10725         case 0x4f:
10726           if (address_mode == mode_64bit)
10727             newrex = *codep;
10728           else
10729             return 1;
10730           last_rex_prefix = i;
10731           break;
10732         case 0xf3:
10733           prefixes |= PREFIX_REPZ;
10734           last_repz_prefix = i;
10735           break;
10736         case 0xf2:
10737           prefixes |= PREFIX_REPNZ;
10738           last_repnz_prefix = i;
10739           break;
10740         case 0xf0:
10741           prefixes |= PREFIX_LOCK;
10742           last_lock_prefix = i;
10743           break;
10744         case 0x2e:
10745           prefixes |= PREFIX_CS;
10746           last_seg_prefix = i;
10747           break;
10748         case 0x36:
10749           prefixes |= PREFIX_SS;
10750           last_seg_prefix = i;
10751           break;
10752         case 0x3e:
10753           prefixes |= PREFIX_DS;
10754           last_seg_prefix = i;
10755           break;
10756         case 0x26:
10757           prefixes |= PREFIX_ES;
10758           last_seg_prefix = i;
10759           break;
10760         case 0x64:
10761           prefixes |= PREFIX_FS;
10762           last_seg_prefix = i;
10763           break;
10764         case 0x65:
10765           prefixes |= PREFIX_GS;
10766           last_seg_prefix = i;
10767           break;
10768         case 0x66:
10769           prefixes |= PREFIX_DATA;
10770           last_data_prefix = i;
10771           break;
10772         case 0x67:
10773           prefixes |= PREFIX_ADDR;
10774           last_addr_prefix = i;
10775           break;
10776         case FWAIT_OPCODE:
10777           /* fwait is really an instruction.  If there are prefixes
10778              before the fwait, they belong to the fwait, *not* to the
10779              following instruction.  */
10780           if (prefixes || rex)
10781             {
10782               prefixes |= PREFIX_FWAIT;
10783               codep++;
10784               return 1;
10785             }
10786           prefixes = PREFIX_FWAIT;
10787           break;
10788         default:
10789           return 1;
10790         }
10791       /* Rex is ignored when followed by another prefix.  */
10792       if (rex)
10793         {
10794           rex_used = rex;
10795           return 1;
10796         }
10797       if (*codep != FWAIT_OPCODE)
10798         all_prefixes[i++] = *codep;
10799       rex = newrex;
10800       codep++;
10801       length++;
10802     }
10803   return 0;
10804 }
10805
10806 static int
10807 seg_prefix (int pref)
10808 {
10809   switch (pref)
10810     {
10811     case 0x2e:
10812       return PREFIX_CS;
10813     case 0x36:
10814       return PREFIX_SS;
10815     case 0x3e:
10816       return PREFIX_DS;
10817     case 0x26:
10818       return PREFIX_ES;
10819     case 0x64:
10820       return PREFIX_FS;
10821     case 0x65:
10822       return PREFIX_GS;
10823     default:
10824       return 0;
10825     }
10826 }
10827
10828 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
10829    prefix byte.  */
10830
10831 static const char *
10832 prefix_name (int pref, int sizeflag)
10833 {
10834   static const char *rexes [16] =
10835     {
10836       "rex",            /* 0x40 */
10837       "rex.B",          /* 0x41 */
10838       "rex.X",          /* 0x42 */
10839       "rex.XB",         /* 0x43 */
10840       "rex.R",          /* 0x44 */
10841       "rex.RB",         /* 0x45 */
10842       "rex.RX",         /* 0x46 */
10843       "rex.RXB",        /* 0x47 */
10844       "rex.W",          /* 0x48 */
10845       "rex.WB",         /* 0x49 */
10846       "rex.WX",         /* 0x4a */
10847       "rex.WXB",        /* 0x4b */
10848       "rex.WR",         /* 0x4c */
10849       "rex.WRB",        /* 0x4d */
10850       "rex.WRX",        /* 0x4e */
10851       "rex.WRXB",       /* 0x4f */
10852     };
10853
10854   switch (pref)
10855     {
10856     /* REX prefixes family.  */
10857     case 0x40:
10858     case 0x41:
10859     case 0x42:
10860     case 0x43:
10861     case 0x44:
10862     case 0x45:
10863     case 0x46:
10864     case 0x47:
10865     case 0x48:
10866     case 0x49:
10867     case 0x4a:
10868     case 0x4b:
10869     case 0x4c:
10870     case 0x4d:
10871     case 0x4e:
10872     case 0x4f:
10873       return rexes [pref - 0x40];
10874     case 0xf3:
10875       return "repz";
10876     case 0xf2:
10877       return "repnz";
10878     case 0xf0:
10879       return "lock";
10880     case 0x2e:
10881       return "cs";
10882     case 0x36:
10883       return "ss";
10884     case 0x3e:
10885       return "ds";
10886     case 0x26:
10887       return "es";
10888     case 0x64:
10889       return "fs";
10890     case 0x65:
10891       return "gs";
10892     case 0x66:
10893       return (sizeflag & DFLAG) ? "data16" : "data32";
10894     case 0x67:
10895       if (address_mode == mode_64bit)
10896         return (sizeflag & AFLAG) ? "addr32" : "addr64";
10897       else
10898         return (sizeflag & AFLAG) ? "addr16" : "addr32";
10899     case FWAIT_OPCODE:
10900       return "fwait";
10901     case ADDR16_PREFIX:
10902       return "addr16";
10903     case ADDR32_PREFIX:
10904       return "addr32";
10905     case DATA16_PREFIX:
10906       return "data16";
10907     case DATA32_PREFIX:
10908       return "data32";
10909     case REP_PREFIX:
10910       return "rep";
10911     default:
10912       return NULL;
10913     }
10914 }
10915
10916 static char op_out[MAX_OPERANDS][100];
10917 static int op_ad, op_index[MAX_OPERANDS];
10918 static int two_source_ops;
10919 static bfd_vma op_address[MAX_OPERANDS];
10920 static bfd_vma op_riprel[MAX_OPERANDS];
10921 static bfd_vma start_pc;
10922
10923 /*
10924  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
10925  *   (see topic "Redundant prefixes" in the "Differences from 8086"
10926  *   section of the "Virtual 8086 Mode" chapter.)
10927  * 'pc' should be the address of this instruction, it will
10928  *   be used to print the target address if this is a relative jump or call
10929  * The function returns the length of this instruction in bytes.
10930  */
10931
10932 static char intel_syntax;
10933 static char intel_mnemonic = !SYSV386_COMPAT;
10934 static char open_char;
10935 static char close_char;
10936 static char separator_char;
10937 static char scale_char;
10938
10939 /* Here for backwards compatibility.  When gdb stops using
10940    print_insn_i386_att and print_insn_i386_intel these functions can
10941    disappear, and print_insn_i386 be merged into print_insn.  */
10942 int
10943 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
10944 {
10945   intel_syntax = 0;
10946
10947   return print_insn (pc, info);
10948 }
10949
10950 int
10951 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
10952 {
10953   intel_syntax = 1;
10954
10955   return print_insn (pc, info);
10956 }
10957
10958 int
10959 print_insn_i386 (bfd_vma pc, disassemble_info *info)
10960 {
10961   intel_syntax = -1;
10962
10963   return print_insn (pc, info);
10964 }
10965
10966 void
10967 print_i386_disassembler_options (FILE *stream)
10968 {
10969   fprintf (stream, _("\n\
10970 The following i386/x86-64 specific disassembler options are supported for use\n\
10971 with the -M switch (multiple options should be separated by commas):\n"));
10972
10973   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
10974   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
10975   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
10976   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
10977   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
10978   fprintf (stream, _("  att-mnemonic\n"
10979                      "              Display instruction in AT&T mnemonic\n"));
10980   fprintf (stream, _("  intel-mnemonic\n"
10981                      "              Display instruction in Intel mnemonic\n"));
10982   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
10983   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
10984   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
10985   fprintf (stream, _("  data32      Assume 32bit data size\n"));
10986   fprintf (stream, _("  data16      Assume 16bit data size\n"));
10987   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
10988 }
10989
10990 /* Bad opcode.  */
10991 static const struct dis386 bad_opcode = { "(bad)", { XX } };
10992
10993 /* Get a pointer to struct dis386 with a valid name.  */
10994
10995 static const struct dis386 *
10996 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
10997 {
10998   int vindex, vex_table_index;
10999
11000   if (dp->name != NULL)
11001     return dp;
11002
11003   switch (dp->op[0].bytemode)
11004     {
11005     case USE_REG_TABLE:
11006       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
11007       break;
11008
11009     case USE_MOD_TABLE:
11010       vindex = modrm.mod == 0x3 ? 1 : 0;
11011       dp = &mod_table[dp->op[1].bytemode][vindex];
11012       break;
11013
11014     case USE_RM_TABLE:
11015       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
11016       break;
11017
11018     case USE_PREFIX_TABLE:
11019       if (need_vex)
11020         {
11021           /* The prefix in VEX is implicit.  */
11022           switch (vex.prefix)
11023             {
11024             case 0:
11025               vindex = 0;
11026               break;
11027             case REPE_PREFIX_OPCODE:
11028               vindex = 1;
11029               break;
11030             case DATA_PREFIX_OPCODE:
11031               vindex = 2;
11032               break;
11033             case REPNE_PREFIX_OPCODE:
11034               vindex = 3;
11035               break;
11036             default:
11037               abort ();
11038               break;
11039             }
11040         }
11041       else
11042         {
11043           vindex = 0;
11044           used_prefixes |= (prefixes & PREFIX_REPZ);
11045           if (prefixes & PREFIX_REPZ)
11046             {
11047               vindex = 1;
11048               all_prefixes[last_repz_prefix] = 0;
11049             }
11050           else
11051             {
11052               /* We should check PREFIX_REPNZ and PREFIX_REPZ before
11053                  PREFIX_DATA.  */
11054               used_prefixes |= (prefixes & PREFIX_REPNZ);
11055               if (prefixes & PREFIX_REPNZ)
11056                 {
11057                   vindex = 3;
11058                   all_prefixes[last_repnz_prefix] = 0;
11059                 }
11060               else
11061                 {
11062                   used_prefixes |= (prefixes & PREFIX_DATA);
11063                   if (prefixes & PREFIX_DATA)
11064                     {
11065                       vindex = 2;
11066                       all_prefixes[last_data_prefix] = 0;
11067                     }
11068                 }
11069             }
11070         }
11071       dp = &prefix_table[dp->op[1].bytemode][vindex];
11072       break;
11073
11074     case USE_X86_64_TABLE:
11075       vindex = address_mode == mode_64bit ? 1 : 0;
11076       dp = &x86_64_table[dp->op[1].bytemode][vindex];
11077       break;
11078
11079     case USE_3BYTE_TABLE:
11080       FETCH_DATA (info, codep + 2);
11081       vindex = *codep++;
11082       dp = &three_byte_table[dp->op[1].bytemode][vindex];
11083       modrm.mod = (*codep >> 6) & 3;
11084       modrm.reg = (*codep >> 3) & 7;
11085       modrm.rm = *codep & 7;
11086       break;
11087
11088     case USE_VEX_LEN_TABLE:
11089       if (!need_vex)
11090         abort ();
11091
11092       switch (vex.length)
11093         {
11094         case 128:
11095           vindex = 0;
11096           break;
11097         case 256:
11098           vindex = 1;
11099           break;
11100         default:
11101           abort ();
11102           break;
11103         }
11104
11105       dp = &vex_len_table[dp->op[1].bytemode][vindex];
11106       break;
11107
11108     case USE_XOP_8F_TABLE:
11109       FETCH_DATA (info, codep + 3);
11110       /* All bits in the REX prefix are ignored.  */
11111       rex_ignored = rex;
11112       rex = ~(*codep >> 5) & 0x7;
11113
11114       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
11115       switch ((*codep & 0x1f))
11116         {
11117         default:
11118           dp = &bad_opcode;
11119           return dp;
11120         case 0x8:
11121           vex_table_index = XOP_08;
11122           break;
11123         case 0x9:
11124           vex_table_index = XOP_09;
11125           break;
11126         case 0xa:
11127           vex_table_index = XOP_0A;
11128           break;
11129         }
11130       codep++;
11131       vex.w = *codep & 0x80;
11132       if (vex.w && address_mode == mode_64bit)
11133         rex |= REX_W;
11134
11135       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11136       if (address_mode != mode_64bit
11137           && vex.register_specifier > 0x7)
11138         {
11139           dp = &bad_opcode;
11140           return dp;
11141         }
11142
11143       vex.length = (*codep & 0x4) ? 256 : 128;
11144       switch ((*codep & 0x3))
11145         {
11146         case 0:
11147           vex.prefix = 0;
11148           break;
11149         case 1:
11150           vex.prefix = DATA_PREFIX_OPCODE;
11151           break;
11152         case 2:
11153           vex.prefix = REPE_PREFIX_OPCODE;
11154           break;
11155         case 3:
11156           vex.prefix = REPNE_PREFIX_OPCODE;
11157           break;
11158         }
11159       need_vex = 1;
11160       need_vex_reg = 1;
11161       codep++;
11162       vindex = *codep++;
11163       dp = &xop_table[vex_table_index][vindex];
11164
11165       FETCH_DATA (info, codep + 1);
11166       modrm.mod = (*codep >> 6) & 3;
11167       modrm.reg = (*codep >> 3) & 7;
11168       modrm.rm = *codep & 7;
11169       break;
11170
11171     case USE_VEX_C4_TABLE:
11172       FETCH_DATA (info, codep + 3);
11173       /* All bits in the REX prefix are ignored.  */
11174       rex_ignored = rex;
11175       rex = ~(*codep >> 5) & 0x7;
11176       switch ((*codep & 0x1f))
11177         {
11178         default:
11179           dp = &bad_opcode;
11180           return dp;
11181         case 0x1:
11182           vex_table_index = VEX_0F;
11183           break;
11184         case 0x2:
11185           vex_table_index = VEX_0F38;
11186           break;
11187         case 0x3:
11188           vex_table_index = VEX_0F3A;
11189           break;
11190         }
11191       codep++;
11192       vex.w = *codep & 0x80;
11193       if (vex.w && address_mode == mode_64bit)
11194         rex |= REX_W;
11195
11196       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11197       if (address_mode != mode_64bit
11198           && vex.register_specifier > 0x7)
11199         {
11200           dp = &bad_opcode;
11201           return dp;
11202         }
11203
11204       vex.length = (*codep & 0x4) ? 256 : 128;
11205       switch ((*codep & 0x3))
11206         {
11207         case 0:
11208           vex.prefix = 0;
11209           break;
11210         case 1:
11211           vex.prefix = DATA_PREFIX_OPCODE;
11212           break;
11213         case 2:
11214           vex.prefix = REPE_PREFIX_OPCODE;
11215           break;
11216         case 3:
11217           vex.prefix = REPNE_PREFIX_OPCODE;
11218           break;
11219         }
11220       need_vex = 1;
11221       need_vex_reg = 1;
11222       codep++;
11223       vindex = *codep++;
11224       dp = &vex_table[vex_table_index][vindex];
11225       /* There is no MODRM byte for VEX [82|77].  */
11226       if (vindex != 0x77 && vindex != 0x82)
11227         {
11228           FETCH_DATA (info, codep + 1);
11229           modrm.mod = (*codep >> 6) & 3;
11230           modrm.reg = (*codep >> 3) & 7;
11231           modrm.rm = *codep & 7;
11232         }
11233       break;
11234
11235     case USE_VEX_C5_TABLE:
11236       FETCH_DATA (info, codep + 2);
11237       /* All bits in the REX prefix are ignored.  */
11238       rex_ignored = rex;
11239       rex = (*codep & 0x80) ? 0 : REX_R;
11240
11241       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11242       if (address_mode != mode_64bit
11243           && vex.register_specifier > 0x7)
11244         {
11245           dp = &bad_opcode;
11246           return dp;
11247         }
11248
11249       vex.w = 0;
11250
11251       vex.length = (*codep & 0x4) ? 256 : 128;
11252       switch ((*codep & 0x3))
11253         {
11254         case 0:
11255           vex.prefix = 0;
11256           break;
11257         case 1:
11258           vex.prefix = DATA_PREFIX_OPCODE;
11259           break;
11260         case 2:
11261           vex.prefix = REPE_PREFIX_OPCODE;
11262           break;
11263         case 3:
11264           vex.prefix = REPNE_PREFIX_OPCODE;
11265           break;
11266         }
11267       need_vex = 1;
11268       need_vex_reg = 1;
11269       codep++;
11270       vindex = *codep++;
11271       dp = &vex_table[dp->op[1].bytemode][vindex];
11272       /* There is no MODRM byte for VEX [82|77].  */
11273       if (vindex != 0x77 && vindex != 0x82)
11274         {
11275           FETCH_DATA (info, codep + 1);
11276           modrm.mod = (*codep >> 6) & 3;
11277           modrm.reg = (*codep >> 3) & 7;
11278           modrm.rm = *codep & 7;
11279         }
11280       break;
11281
11282     case USE_VEX_W_TABLE:
11283       if (!need_vex)
11284         abort ();
11285
11286       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
11287       break;
11288
11289     case 0:
11290       dp = &bad_opcode;
11291       break;
11292
11293     default:
11294       abort ();
11295     }
11296
11297   if (dp->name != NULL)
11298     return dp;
11299   else
11300     return get_valid_dis386 (dp, info);
11301 }
11302
11303 static void
11304 get_sib (disassemble_info *info)
11305 {
11306   /* If modrm.mod == 3, operand must be register.  */
11307   if (need_modrm
11308       && address_mode != mode_16bit
11309       && modrm.mod != 3
11310       && modrm.rm == 4)
11311     {
11312       FETCH_DATA (info, codep + 2);
11313       sib.index = (codep [1] >> 3) & 7;
11314       sib.scale = (codep [1] >> 6) & 3;
11315       sib.base = codep [1] & 7;
11316     }
11317 }
11318
11319 static int
11320 print_insn (bfd_vma pc, disassemble_info *info)
11321 {
11322   const struct dis386 *dp;
11323   int i;
11324   char *op_txt[MAX_OPERANDS];
11325   int needcomma;
11326   int sizeflag;
11327   const char *p;
11328   struct dis_private priv;
11329   int prefix_length;
11330   int default_prefixes;
11331
11332   if (info->mach == bfd_mach_x86_64_intel_syntax
11333       || info->mach == bfd_mach_x86_64
11334       || info->mach == bfd_mach_l1om
11335       || info->mach == bfd_mach_l1om_intel_syntax)
11336     address_mode = mode_64bit;
11337   else
11338     address_mode = mode_32bit;
11339
11340   if (intel_syntax == (char) -1)
11341     intel_syntax = (info->mach == bfd_mach_i386_i386_intel_syntax
11342                     || info->mach == bfd_mach_x86_64_intel_syntax
11343                     || info->mach == bfd_mach_l1om_intel_syntax);
11344
11345   if (info->mach == bfd_mach_i386_i386
11346       || info->mach == bfd_mach_x86_64
11347       || info->mach == bfd_mach_l1om
11348       || info->mach == bfd_mach_i386_i386_intel_syntax
11349       || info->mach == bfd_mach_x86_64_intel_syntax
11350       || info->mach == bfd_mach_l1om_intel_syntax)
11351     priv.orig_sizeflag = AFLAG | DFLAG;
11352   else if (info->mach == bfd_mach_i386_i8086)
11353     priv.orig_sizeflag = 0;
11354   else
11355     abort ();
11356
11357   for (p = info->disassembler_options; p != NULL; )
11358     {
11359       if (CONST_STRNEQ (p, "x86-64"))
11360         {
11361           address_mode = mode_64bit;
11362           priv.orig_sizeflag = AFLAG | DFLAG;
11363         }
11364       else if (CONST_STRNEQ (p, "i386"))
11365         {
11366           address_mode = mode_32bit;
11367           priv.orig_sizeflag = AFLAG | DFLAG;
11368         }
11369       else if (CONST_STRNEQ (p, "i8086"))
11370         {
11371           address_mode = mode_16bit;
11372           priv.orig_sizeflag = 0;
11373         }
11374       else if (CONST_STRNEQ (p, "intel"))
11375         {
11376           intel_syntax = 1;
11377           if (CONST_STRNEQ (p + 5, "-mnemonic"))
11378             intel_mnemonic = 1;
11379         }
11380       else if (CONST_STRNEQ (p, "att"))
11381         {
11382           intel_syntax = 0;
11383           if (CONST_STRNEQ (p + 3, "-mnemonic"))
11384             intel_mnemonic = 0;
11385         }
11386       else if (CONST_STRNEQ (p, "addr"))
11387         {
11388           if (address_mode == mode_64bit)
11389             {
11390               if (p[4] == '3' && p[5] == '2')
11391                 priv.orig_sizeflag &= ~AFLAG;
11392               else if (p[4] == '6' && p[5] == '4')
11393                 priv.orig_sizeflag |= AFLAG;
11394             }
11395           else
11396             {
11397               if (p[4] == '1' && p[5] == '6')
11398                 priv.orig_sizeflag &= ~AFLAG;
11399               else if (p[4] == '3' && p[5] == '2')
11400                 priv.orig_sizeflag |= AFLAG;
11401             }
11402         }
11403       else if (CONST_STRNEQ (p, "data"))
11404         {
11405           if (p[4] == '1' && p[5] == '6')
11406             priv.orig_sizeflag &= ~DFLAG;
11407           else if (p[4] == '3' && p[5] == '2')
11408             priv.orig_sizeflag |= DFLAG;
11409         }
11410       else if (CONST_STRNEQ (p, "suffix"))
11411         priv.orig_sizeflag |= SUFFIX_ALWAYS;
11412
11413       p = strchr (p, ',');
11414       if (p != NULL)
11415         p++;
11416     }
11417
11418   if (intel_syntax)
11419     {
11420       names64 = intel_names64;
11421       names32 = intel_names32;
11422       names16 = intel_names16;
11423       names8 = intel_names8;
11424       names8rex = intel_names8rex;
11425       names_seg = intel_names_seg;
11426       names_mm = intel_names_mm;
11427       names_xmm = intel_names_xmm;
11428       names_ymm = intel_names_ymm;
11429       index64 = intel_index64;
11430       index32 = intel_index32;
11431       index16 = intel_index16;
11432       open_char = '[';
11433       close_char = ']';
11434       separator_char = '+';
11435       scale_char = '*';
11436     }
11437   else
11438     {
11439       names64 = att_names64;
11440       names32 = att_names32;
11441       names16 = att_names16;
11442       names8 = att_names8;
11443       names8rex = att_names8rex;
11444       names_seg = att_names_seg;
11445       names_mm = att_names_mm;
11446       names_xmm = att_names_xmm;
11447       names_ymm = att_names_ymm;
11448       index64 = att_index64;
11449       index32 = att_index32;
11450       index16 = att_index16;
11451       open_char = '(';
11452       close_char =  ')';
11453       separator_char = ',';
11454       scale_char = ',';
11455     }
11456
11457   /* The output looks better if we put 7 bytes on a line, since that
11458      puts most long word instructions on a single line.  Use 8 bytes
11459      for Intel L1OM.  */
11460   if (info->mach == bfd_mach_l1om
11461       || info->mach == bfd_mach_l1om_intel_syntax)
11462     info->bytes_per_line = 8;
11463   else
11464     info->bytes_per_line = 7;
11465
11466   info->private_data = &priv;
11467   priv.max_fetched = priv.the_buffer;
11468   priv.insn_start = pc;
11469
11470   obuf[0] = 0;
11471   for (i = 0; i < MAX_OPERANDS; ++i)
11472     {
11473       op_out[i][0] = 0;
11474       op_index[i] = -1;
11475     }
11476
11477   the_info = info;
11478   start_pc = pc;
11479   start_codep = priv.the_buffer;
11480   codep = priv.the_buffer;
11481
11482   if (setjmp (priv.bailout) != 0)
11483     {
11484       const char *name;
11485
11486       /* Getting here means we tried for data but didn't get it.  That
11487          means we have an incomplete instruction of some sort.  Just
11488          print the first byte as a prefix or a .byte pseudo-op.  */
11489       if (codep > priv.the_buffer)
11490         {
11491           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
11492           if (name != NULL)
11493             (*info->fprintf_func) (info->stream, "%s", name);
11494           else
11495             {
11496               /* Just print the first byte as a .byte instruction.  */
11497               (*info->fprintf_func) (info->stream, ".byte 0x%x",
11498                                      (unsigned int) priv.the_buffer[0]);
11499             }
11500
11501           return 1;
11502         }
11503
11504       return -1;
11505     }
11506
11507   obufp = obuf;
11508   sizeflag = priv.orig_sizeflag;
11509
11510   if (!ckprefix () || rex_used)
11511     {
11512       /* Too many prefixes or unused REX prefixes.  */
11513       for (i = 0;
11514            all_prefixes[i] && i < (int) ARRAY_SIZE (all_prefixes);
11515            i++)
11516         (*info->fprintf_func) (info->stream, "%s",
11517                                prefix_name (all_prefixes[i], sizeflag));
11518       return 1;
11519     }
11520
11521   insn_codep = codep;
11522
11523   FETCH_DATA (info, codep + 1);
11524   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
11525
11526   if (((prefixes & PREFIX_FWAIT)
11527        && ((*codep < 0xd8) || (*codep > 0xdf))))
11528     {
11529       (*info->fprintf_func) (info->stream, "fwait");
11530       return 1;
11531     }
11532
11533   if (*codep == 0x0f)
11534     {
11535       unsigned char threebyte;
11536       FETCH_DATA (info, codep + 2);
11537       threebyte = *++codep;
11538       dp = &dis386_twobyte[threebyte];
11539       need_modrm = twobyte_has_modrm[*codep];
11540       codep++;
11541     }
11542   else
11543     {
11544       dp = &dis386[*codep];
11545       need_modrm = onebyte_has_modrm[*codep];
11546       codep++;
11547     }
11548
11549   if ((prefixes & PREFIX_REPZ))
11550     used_prefixes |= PREFIX_REPZ;
11551   if ((prefixes & PREFIX_REPNZ))
11552     used_prefixes |= PREFIX_REPNZ;
11553   if ((prefixes & PREFIX_LOCK))
11554     used_prefixes |= PREFIX_LOCK;
11555
11556   default_prefixes = 0;
11557   if (prefixes & PREFIX_ADDR)
11558     {
11559       sizeflag ^= AFLAG;
11560       if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax)
11561         {
11562           if ((sizeflag & AFLAG) || address_mode == mode_64bit)
11563             all_prefixes[last_addr_prefix] = ADDR32_PREFIX;
11564           else
11565             all_prefixes[last_addr_prefix] = ADDR16_PREFIX;
11566           default_prefixes |= PREFIX_ADDR;
11567         }
11568     }
11569
11570   if ((prefixes & PREFIX_DATA))
11571     {
11572       sizeflag ^= DFLAG;
11573       if (dp->op[2].bytemode == cond_jump_mode
11574           && dp->op[0].bytemode == v_mode
11575           && !intel_syntax)
11576         {
11577           if (sizeflag & DFLAG)
11578             all_prefixes[last_data_prefix] = DATA32_PREFIX;
11579           else
11580             all_prefixes[last_data_prefix] = DATA16_PREFIX;
11581           default_prefixes |= PREFIX_DATA;
11582         }
11583       else if (rex & REX_W)
11584         {
11585           /* REX_W will override PREFIX_DATA.  */
11586           default_prefixes |= PREFIX_DATA;
11587         }
11588     }
11589
11590   if (need_modrm)
11591     {
11592       FETCH_DATA (info, codep + 1);
11593       modrm.mod = (*codep >> 6) & 3;
11594       modrm.reg = (*codep >> 3) & 7;
11595       modrm.rm = *codep & 7;
11596     }
11597
11598    need_vex = 0;
11599    need_vex_reg = 0;
11600    vex_w_done = 0;
11601
11602   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
11603     {
11604       get_sib (info);
11605       dofloat (sizeflag);
11606     }
11607   else
11608     {
11609       dp = get_valid_dis386 (dp, info);
11610       if (dp != NULL && putop (dp->name, sizeflag) == 0)
11611         {
11612           get_sib (info);
11613           for (i = 0; i < MAX_OPERANDS; ++i)
11614             {
11615               obufp = op_out[i];
11616               op_ad = MAX_OPERANDS - 1 - i;
11617               if (dp->op[i].rtn)
11618                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
11619             }
11620         }
11621     }
11622
11623   /* See if any prefixes were not used.  If so, print the first one
11624      separately.  If we don't do this, we'll wind up printing an
11625      instruction stream which does not precisely correspond to the
11626      bytes we are disassembling.  */
11627   if ((prefixes & ~(used_prefixes | default_prefixes)) != 0)
11628     {
11629       for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11630         if (all_prefixes[i])
11631           {
11632             const char *name;
11633             name = prefix_name (all_prefixes[i], priv.orig_sizeflag);
11634             if (name == NULL)
11635               name = INTERNAL_DISASSEMBLER_ERROR;
11636             (*info->fprintf_func) (info->stream, "%s", name);
11637             return 1;
11638           }
11639     }
11640
11641   /* Check if the REX prefix is used.  */
11642   if (rex_ignored == 0 && (rex ^ rex_used) == 0)
11643     all_prefixes[last_rex_prefix] = 0;
11644
11645   /* Check if the SEG prefix is used.  */
11646   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
11647                    | PREFIX_FS | PREFIX_GS)) != 0
11648       && (used_prefixes
11649           & seg_prefix (all_prefixes[last_seg_prefix])) != 0)
11650     all_prefixes[last_seg_prefix] = 0;
11651
11652   /* Check if the ADDR prefix is used.  */
11653   if ((prefixes & PREFIX_ADDR) != 0
11654       && (used_prefixes & PREFIX_ADDR) != 0)
11655     all_prefixes[last_addr_prefix] = 0;
11656
11657   /* Check if the DATA prefix is used.  */
11658   if ((prefixes & PREFIX_DATA) != 0
11659       && (used_prefixes & PREFIX_DATA) != 0)
11660     all_prefixes[last_data_prefix] = 0;
11661
11662   prefix_length = 0;
11663   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11664     if (all_prefixes[i])
11665       {
11666         const char *name;
11667         name = prefix_name (all_prefixes[i], sizeflag);
11668         if (name == NULL)
11669           abort ();
11670         prefix_length += strlen (name) + 1;
11671         (*info->fprintf_func) (info->stream, "%s ", name);
11672       }
11673
11674   /* Check maximum code length.  */
11675   if ((codep - start_codep) > MAX_CODE_LENGTH)
11676     {
11677       (*info->fprintf_func) (info->stream, "(bad)");
11678       return MAX_CODE_LENGTH;
11679     }
11680
11681   obufp = mnemonicendp;
11682   for (i = strlen (obuf) + prefix_length; i < 6; i++)
11683     oappend (" ");
11684   oappend (" ");
11685   (*info->fprintf_func) (info->stream, "%s", obuf);
11686
11687   /* The enter and bound instructions are printed with operands in the same
11688      order as the intel book; everything else is printed in reverse order.  */
11689   if (intel_syntax || two_source_ops)
11690     {
11691       bfd_vma riprel;
11692
11693       for (i = 0; i < MAX_OPERANDS; ++i)
11694         op_txt[i] = op_out[i];
11695
11696       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
11697         {
11698           op_ad = op_index[i];
11699           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
11700           op_index[MAX_OPERANDS - 1 - i] = op_ad;
11701           riprel = op_riprel[i];
11702           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
11703           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
11704         }
11705     }
11706   else
11707     {
11708       for (i = 0; i < MAX_OPERANDS; ++i)
11709         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
11710     }
11711
11712   needcomma = 0;
11713   for (i = 0; i < MAX_OPERANDS; ++i)
11714     if (*op_txt[i])
11715       {
11716         if (needcomma)
11717           (*info->fprintf_func) (info->stream, ",");
11718         if (op_index[i] != -1 && !op_riprel[i])
11719           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
11720         else
11721           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
11722         needcomma = 1;
11723       }
11724
11725   for (i = 0; i < MAX_OPERANDS; i++)
11726     if (op_index[i] != -1 && op_riprel[i])
11727       {
11728         (*info->fprintf_func) (info->stream, "        # ");
11729         (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
11730                                                 + op_address[op_index[i]]), info);
11731         break;
11732       }
11733   return codep - priv.the_buffer;
11734 }
11735
11736 static const char *float_mem[] = {
11737   /* d8 */
11738   "fadd{s|}",
11739   "fmul{s|}",
11740   "fcom{s|}",
11741   "fcomp{s|}",
11742   "fsub{s|}",
11743   "fsubr{s|}",
11744   "fdiv{s|}",
11745   "fdivr{s|}",
11746   /* d9 */
11747   "fld{s|}",
11748   "(bad)",
11749   "fst{s|}",
11750   "fstp{s|}",
11751   "fldenvIC",
11752   "fldcw",
11753   "fNstenvIC",
11754   "fNstcw",
11755   /* da */
11756   "fiadd{l|}",
11757   "fimul{l|}",
11758   "ficom{l|}",
11759   "ficomp{l|}",
11760   "fisub{l|}",
11761   "fisubr{l|}",
11762   "fidiv{l|}",
11763   "fidivr{l|}",
11764   /* db */
11765   "fild{l|}",
11766   "fisttp{l|}",
11767   "fist{l|}",
11768   "fistp{l|}",
11769   "(bad)",
11770   "fld{t||t|}",
11771   "(bad)",
11772   "fstp{t||t|}",
11773   /* dc */
11774   "fadd{l|}",
11775   "fmul{l|}",
11776   "fcom{l|}",
11777   "fcomp{l|}",
11778   "fsub{l|}",
11779   "fsubr{l|}",
11780   "fdiv{l|}",
11781   "fdivr{l|}",
11782   /* dd */
11783   "fld{l|}",
11784   "fisttp{ll|}",
11785   "fst{l||}",
11786   "fstp{l|}",
11787   "frstorIC",
11788   "(bad)",
11789   "fNsaveIC",
11790   "fNstsw",
11791   /* de */
11792   "fiadd",
11793   "fimul",
11794   "ficom",
11795   "ficomp",
11796   "fisub",
11797   "fisubr",
11798   "fidiv",
11799   "fidivr",
11800   /* df */
11801   "fild",
11802   "fisttp",
11803   "fist",
11804   "fistp",
11805   "fbld",
11806   "fild{ll|}",
11807   "fbstp",
11808   "fistp{ll|}",
11809 };
11810
11811 static const unsigned char float_mem_mode[] = {
11812   /* d8 */
11813   d_mode,
11814   d_mode,
11815   d_mode,
11816   d_mode,
11817   d_mode,
11818   d_mode,
11819   d_mode,
11820   d_mode,
11821   /* d9 */
11822   d_mode,
11823   0,
11824   d_mode,
11825   d_mode,
11826   0,
11827   w_mode,
11828   0,
11829   w_mode,
11830   /* da */
11831   d_mode,
11832   d_mode,
11833   d_mode,
11834   d_mode,
11835   d_mode,
11836   d_mode,
11837   d_mode,
11838   d_mode,
11839   /* db */
11840   d_mode,
11841   d_mode,
11842   d_mode,
11843   d_mode,
11844   0,
11845   t_mode,
11846   0,
11847   t_mode,
11848   /* dc */
11849   q_mode,
11850   q_mode,
11851   q_mode,
11852   q_mode,
11853   q_mode,
11854   q_mode,
11855   q_mode,
11856   q_mode,
11857   /* dd */
11858   q_mode,
11859   q_mode,
11860   q_mode,
11861   q_mode,
11862   0,
11863   0,
11864   0,
11865   w_mode,
11866   /* de */
11867   w_mode,
11868   w_mode,
11869   w_mode,
11870   w_mode,
11871   w_mode,
11872   w_mode,
11873   w_mode,
11874   w_mode,
11875   /* df */
11876   w_mode,
11877   w_mode,
11878   w_mode,
11879   w_mode,
11880   t_mode,
11881   q_mode,
11882   t_mode,
11883   q_mode
11884 };
11885
11886 #define ST { OP_ST, 0 }
11887 #define STi { OP_STi, 0 }
11888
11889 #define FGRPd9_2 NULL, { { NULL, 0 } }
11890 #define FGRPd9_4 NULL, { { NULL, 1 } }
11891 #define FGRPd9_5 NULL, { { NULL, 2 } }
11892 #define FGRPd9_6 NULL, { { NULL, 3 } }
11893 #define FGRPd9_7 NULL, { { NULL, 4 } }
11894 #define FGRPda_5 NULL, { { NULL, 5 } }
11895 #define FGRPdb_4 NULL, { { NULL, 6 } }
11896 #define FGRPde_3 NULL, { { NULL, 7 } }
11897 #define FGRPdf_4 NULL, { { NULL, 8 } }
11898
11899 static const struct dis386 float_reg[][8] = {
11900   /* d8 */
11901   {
11902     { "fadd",   { ST, STi } },
11903     { "fmul",   { ST, STi } },
11904     { "fcom",   { STi } },
11905     { "fcomp",  { STi } },
11906     { "fsub",   { ST, STi } },
11907     { "fsubr",  { ST, STi } },
11908     { "fdiv",   { ST, STi } },
11909     { "fdivr",  { ST, STi } },
11910   },
11911   /* d9 */
11912   {
11913     { "fld",    { STi } },
11914     { "fxch",   { STi } },
11915     { FGRPd9_2 },
11916     { Bad_Opcode },
11917     { FGRPd9_4 },
11918     { FGRPd9_5 },
11919     { FGRPd9_6 },
11920     { FGRPd9_7 },
11921   },
11922   /* da */
11923   {
11924     { "fcmovb", { ST, STi } },
11925     { "fcmove", { ST, STi } },
11926     { "fcmovbe",{ ST, STi } },
11927     { "fcmovu", { ST, STi } },
11928     { Bad_Opcode },
11929     { FGRPda_5 },
11930     { Bad_Opcode },
11931     { Bad_Opcode },
11932   },
11933   /* db */
11934   {
11935     { "fcmovnb",{ ST, STi } },
11936     { "fcmovne",{ ST, STi } },
11937     { "fcmovnbe",{ ST, STi } },
11938     { "fcmovnu",{ ST, STi } },
11939     { FGRPdb_4 },
11940     { "fucomi", { ST, STi } },
11941     { "fcomi",  { ST, STi } },
11942     { Bad_Opcode },
11943   },
11944   /* dc */
11945   {
11946     { "fadd",   { STi, ST } },
11947     { "fmul",   { STi, ST } },
11948     { Bad_Opcode },
11949     { Bad_Opcode },
11950     { "fsub!M", { STi, ST } },
11951     { "fsubM",  { STi, ST } },
11952     { "fdiv!M", { STi, ST } },
11953     { "fdivM",  { STi, ST } },
11954   },
11955   /* dd */
11956   {
11957     { "ffree",  { STi } },
11958     { Bad_Opcode },
11959     { "fst",    { STi } },
11960     { "fstp",   { STi } },
11961     { "fucom",  { STi } },
11962     { "fucomp", { STi } },
11963     { Bad_Opcode },
11964     { Bad_Opcode },
11965   },
11966   /* de */
11967   {
11968     { "faddp",  { STi, ST } },
11969     { "fmulp",  { STi, ST } },
11970     { Bad_Opcode },
11971     { FGRPde_3 },
11972     { "fsub!Mp", { STi, ST } },
11973     { "fsubMp", { STi, ST } },
11974     { "fdiv!Mp", { STi, ST } },
11975     { "fdivMp", { STi, ST } },
11976   },
11977   /* df */
11978   {
11979     { "ffreep", { STi } },
11980     { Bad_Opcode },
11981     { Bad_Opcode },
11982     { Bad_Opcode },
11983     { FGRPdf_4 },
11984     { "fucomip", { ST, STi } },
11985     { "fcomip", { ST, STi } },
11986     { Bad_Opcode },
11987   },
11988 };
11989
11990 static char *fgrps[][8] = {
11991   /* d9_2  0 */
11992   {
11993     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11994   },
11995
11996   /* d9_4  1 */
11997   {
11998     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
11999   },
12000
12001   /* d9_5  2 */
12002   {
12003     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
12004   },
12005
12006   /* d9_6  3 */
12007   {
12008     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
12009   },
12010
12011   /* d9_7  4 */
12012   {
12013     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
12014   },
12015
12016   /* da_5  5 */
12017   {
12018     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12019   },
12020
12021   /* db_4  6 */
12022   {
12023     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
12024     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
12025   },
12026
12027   /* de_3  7 */
12028   {
12029     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12030   },
12031
12032   /* df_4  8 */
12033   {
12034     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12035   },
12036 };
12037
12038 static void
12039 swap_operand (void)
12040 {
12041   mnemonicendp[0] = '.';
12042   mnemonicendp[1] = 's';
12043   mnemonicendp += 2;
12044 }
12045
12046 static void
12047 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
12048                int sizeflag ATTRIBUTE_UNUSED)
12049 {
12050   /* Skip mod/rm byte.  */
12051   MODRM_CHECK;
12052   codep++;
12053 }
12054
12055 static void
12056 dofloat (int sizeflag)
12057 {
12058   const struct dis386 *dp;
12059   unsigned char floatop;
12060
12061   floatop = codep[-1];
12062
12063   if (modrm.mod != 3)
12064     {
12065       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
12066
12067       putop (float_mem[fp_indx], sizeflag);
12068       obufp = op_out[0];
12069       op_ad = 2;
12070       OP_E (float_mem_mode[fp_indx], sizeflag);
12071       return;
12072     }
12073   /* Skip mod/rm byte.  */
12074   MODRM_CHECK;
12075   codep++;
12076
12077   dp = &float_reg[floatop - 0xd8][modrm.reg];
12078   if (dp->name == NULL)
12079     {
12080       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
12081
12082       /* Instruction fnstsw is only one with strange arg.  */
12083       if (floatop == 0xdf && codep[-1] == 0xe0)
12084         strcpy (op_out[0], names16[0]);
12085     }
12086   else
12087     {
12088       putop (dp->name, sizeflag);
12089
12090       obufp = op_out[0];
12091       op_ad = 2;
12092       if (dp->op[0].rtn)
12093         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
12094
12095       obufp = op_out[1];
12096       op_ad = 1;
12097       if (dp->op[1].rtn)
12098         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
12099     }
12100 }
12101
12102 static void
12103 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12104 {
12105   oappend ("%st" + intel_syntax);
12106 }
12107
12108 static void
12109 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12110 {
12111   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
12112   oappend (scratchbuf + intel_syntax);
12113 }
12114
12115 /* Capital letters in template are macros.  */
12116 static int
12117 putop (const char *in_template, int sizeflag)
12118 {
12119   const char *p;
12120   int alt = 0;
12121   int cond = 1;
12122   unsigned int l = 0, len = 1;
12123   char last[4];
12124
12125 #define SAVE_LAST(c)                    \
12126   if (l < len && l < sizeof (last))     \
12127     last[l++] = c;                      \
12128   else                                  \
12129     abort ();
12130
12131   for (p = in_template; *p; p++)
12132     {
12133       switch (*p)
12134         {
12135         default:
12136           *obufp++ = *p;
12137           break;
12138         case '%':
12139           len++;
12140           break;
12141         case '!':
12142           cond = 0;
12143           break;
12144         case '{':
12145           alt = 0;
12146           if (intel_syntax)
12147             {
12148               while (*++p != '|')
12149                 if (*p == '}' || *p == '\0')
12150                   abort ();
12151             }
12152           /* Fall through.  */
12153         case 'I':
12154           alt = 1;
12155           continue;
12156         case '|':
12157           while (*++p != '}')
12158             {
12159               if (*p == '\0')
12160                 abort ();
12161             }
12162           break;
12163         case '}':
12164           break;
12165         case 'A':
12166           if (intel_syntax)
12167             break;
12168           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12169             *obufp++ = 'b';
12170           break;
12171         case 'B':
12172           if (l == 0 && len == 1)
12173             {
12174 case_B:
12175               if (intel_syntax)
12176                 break;
12177               if (sizeflag & SUFFIX_ALWAYS)
12178                 *obufp++ = 'b';
12179             }
12180           else
12181             {
12182               if (l != 1
12183                   || len != 2
12184                   || last[0] != 'L')
12185                 {
12186                   SAVE_LAST (*p);
12187                   break;
12188                 }
12189
12190               if (address_mode == mode_64bit
12191                   && !(prefixes & PREFIX_ADDR))
12192                 {
12193                   *obufp++ = 'a';
12194                   *obufp++ = 'b';
12195                   *obufp++ = 's';
12196                 }
12197
12198               goto case_B;
12199             }
12200           break;
12201         case 'C':
12202           if (intel_syntax && !alt)
12203             break;
12204           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
12205             {
12206               if (sizeflag & DFLAG)
12207                 *obufp++ = intel_syntax ? 'd' : 'l';
12208               else
12209                 *obufp++ = intel_syntax ? 'w' : 's';
12210               used_prefixes |= (prefixes & PREFIX_DATA);
12211             }
12212           break;
12213         case 'D':
12214           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12215             break;
12216           USED_REX (REX_W);
12217           if (modrm.mod == 3)
12218             {
12219               if (rex & REX_W)
12220                 *obufp++ = 'q';
12221               else
12222                 {
12223                   if (sizeflag & DFLAG)
12224                     *obufp++ = intel_syntax ? 'd' : 'l';
12225                   else
12226                     *obufp++ = 'w';
12227                   used_prefixes |= (prefixes & PREFIX_DATA);
12228                 }
12229             }
12230           else
12231             *obufp++ = 'w';
12232           break;
12233         case 'E':               /* For jcxz/jecxz */
12234           if (address_mode == mode_64bit)
12235             {
12236               if (sizeflag & AFLAG)
12237                 *obufp++ = 'r';
12238               else
12239                 *obufp++ = 'e';
12240             }
12241           else
12242             if (sizeflag & AFLAG)
12243               *obufp++ = 'e';
12244           used_prefixes |= (prefixes & PREFIX_ADDR);
12245           break;
12246         case 'F':
12247           if (intel_syntax)
12248             break;
12249           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
12250             {
12251               if (sizeflag & AFLAG)
12252                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
12253               else
12254                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
12255               used_prefixes |= (prefixes & PREFIX_ADDR);
12256             }
12257           break;
12258         case 'G':
12259           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
12260             break;
12261           if ((rex & REX_W) || (sizeflag & DFLAG))
12262             *obufp++ = 'l';
12263           else
12264             *obufp++ = 'w';
12265           if (!(rex & REX_W))
12266             used_prefixes |= (prefixes & PREFIX_DATA);
12267           break;
12268         case 'H':
12269           if (intel_syntax)
12270             break;
12271           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
12272               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
12273             {
12274               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
12275               *obufp++ = ',';
12276               *obufp++ = 'p';
12277               if (prefixes & PREFIX_DS)
12278                 *obufp++ = 't';
12279               else
12280                 *obufp++ = 'n';
12281             }
12282           break;
12283         case 'J':
12284           if (intel_syntax)
12285             break;
12286           *obufp++ = 'l';
12287           break;
12288         case 'K':
12289           USED_REX (REX_W);
12290           if (rex & REX_W)
12291             *obufp++ = 'q';
12292           else
12293             *obufp++ = 'd';
12294           break;
12295         case 'Z':
12296           if (intel_syntax)
12297             break;
12298           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
12299             {
12300               *obufp++ = 'q';
12301               break;
12302             }
12303           /* Fall through.  */
12304           goto case_L;
12305         case 'L':
12306           if (l != 0 || len != 1)
12307             {
12308               SAVE_LAST (*p);
12309               break;
12310             }
12311 case_L:
12312           if (intel_syntax)
12313             break;
12314           if (sizeflag & SUFFIX_ALWAYS)
12315             *obufp++ = 'l';
12316           break;
12317         case 'M':
12318           if (intel_mnemonic != cond)
12319             *obufp++ = 'r';
12320           break;
12321         case 'N':
12322           if ((prefixes & PREFIX_FWAIT) == 0)
12323             *obufp++ = 'n';
12324           else
12325             used_prefixes |= PREFIX_FWAIT;
12326           break;
12327         case 'O':
12328           USED_REX (REX_W);
12329           if (rex & REX_W)
12330             *obufp++ = 'o';
12331           else if (intel_syntax && (sizeflag & DFLAG))
12332             *obufp++ = 'q';
12333           else
12334             *obufp++ = 'd';
12335           if (!(rex & REX_W))
12336             used_prefixes |= (prefixes & PREFIX_DATA);
12337           break;
12338         case 'T':
12339           if (!intel_syntax
12340               && address_mode == mode_64bit
12341               && (sizeflag & DFLAG))
12342             {
12343               *obufp++ = 'q';
12344               break;
12345             }
12346           /* Fall through.  */
12347         case 'P':
12348           if (intel_syntax)
12349             {
12350               if ((rex & REX_W) == 0
12351                   && (prefixes & PREFIX_DATA))
12352                 {
12353                   if ((sizeflag & DFLAG) == 0)
12354                     *obufp++ = 'w';
12355                    used_prefixes |= (prefixes & PREFIX_DATA);
12356                 }
12357               break;
12358             }
12359           if ((prefixes & PREFIX_DATA)
12360               || (rex & REX_W)
12361               || (sizeflag & SUFFIX_ALWAYS))
12362             {
12363               USED_REX (REX_W);
12364               if (rex & REX_W)
12365                 *obufp++ = 'q';
12366               else
12367                 {
12368                    if (sizeflag & DFLAG)
12369                       *obufp++ = 'l';
12370                    else
12371                      *obufp++ = 'w';
12372                    used_prefixes |= (prefixes & PREFIX_DATA);
12373                 }
12374             }
12375           break;
12376         case 'U':
12377           if (intel_syntax)
12378             break;
12379           if (address_mode == mode_64bit && (sizeflag & DFLAG))
12380             {
12381               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12382                 *obufp++ = 'q';
12383               break;
12384             }
12385           /* Fall through.  */
12386           goto case_Q;
12387         case 'Q':
12388           if (l == 0 && len == 1)
12389             {
12390 case_Q:
12391               if (intel_syntax && !alt)
12392                 break;
12393               USED_REX (REX_W);
12394               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12395                 {
12396                   if (rex & REX_W)
12397                     *obufp++ = 'q';
12398                   else
12399                     {
12400                       if (sizeflag & DFLAG)
12401                         *obufp++ = intel_syntax ? 'd' : 'l';
12402                       else
12403                         *obufp++ = 'w';
12404                       used_prefixes |= (prefixes & PREFIX_DATA);
12405                     }
12406                 }
12407             }
12408           else
12409             {
12410               if (l != 1 || len != 2 || last[0] != 'L')
12411                 {
12412                   SAVE_LAST (*p);
12413                   break;
12414                 }
12415               if (intel_syntax
12416                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
12417                 break;
12418               if ((rex & REX_W))
12419                 {
12420                   USED_REX (REX_W);
12421                   *obufp++ = 'q';
12422                 }
12423               else
12424                 *obufp++ = 'l';
12425             }
12426           break;
12427         case 'R':
12428           USED_REX (REX_W);
12429           if (rex & REX_W)
12430             *obufp++ = 'q';
12431           else if (sizeflag & DFLAG)
12432             {
12433               if (intel_syntax)
12434                   *obufp++ = 'd';
12435               else
12436                   *obufp++ = 'l';
12437             }
12438           else
12439             *obufp++ = 'w';
12440           if (intel_syntax && !p[1]
12441               && ((rex & REX_W) || (sizeflag & DFLAG)))
12442             *obufp++ = 'e';
12443           if (!(rex & REX_W))
12444             used_prefixes |= (prefixes & PREFIX_DATA);
12445           break;
12446         case 'V':
12447           if (l == 0 && len == 1)
12448             {
12449               if (intel_syntax)
12450                 break;
12451               if (address_mode == mode_64bit && (sizeflag & DFLAG))
12452                 {
12453                   if (sizeflag & SUFFIX_ALWAYS)
12454                     *obufp++ = 'q';
12455                   break;
12456                 }
12457             }
12458           else
12459             {
12460               if (l != 1
12461                   || len != 2
12462                   || last[0] != 'L')
12463                 {
12464                   SAVE_LAST (*p);
12465                   break;
12466                 }
12467
12468               if (rex & REX_W)
12469                 {
12470                   *obufp++ = 'a';
12471                   *obufp++ = 'b';
12472                   *obufp++ = 's';
12473                 }
12474             }
12475           /* Fall through.  */
12476           goto case_S;
12477         case 'S':
12478           if (l == 0 && len == 1)
12479             {
12480 case_S:
12481               if (intel_syntax)
12482                 break;
12483               if (sizeflag & SUFFIX_ALWAYS)
12484                 {
12485                   if (rex & REX_W)
12486                     *obufp++ = 'q';
12487                   else
12488                     {
12489                       if (sizeflag & DFLAG)
12490                         *obufp++ = 'l';
12491                       else
12492                         *obufp++ = 'w';
12493                       used_prefixes |= (prefixes & PREFIX_DATA);
12494                     }
12495                 }
12496             }
12497           else
12498             {
12499               if (l != 1
12500                   || len != 2
12501                   || last[0] != 'L')
12502                 {
12503                   SAVE_LAST (*p);
12504                   break;
12505                 }
12506
12507               if (address_mode == mode_64bit
12508                   && !(prefixes & PREFIX_ADDR))
12509                 {
12510                   *obufp++ = 'a';
12511                   *obufp++ = 'b';
12512                   *obufp++ = 's';
12513                 }
12514
12515               goto case_S;
12516             }
12517           break;
12518         case 'X':
12519           if (l != 0 || len != 1)
12520             {
12521               SAVE_LAST (*p);
12522               break;
12523             }
12524           if (need_vex && vex.prefix)
12525             {
12526               if (vex.prefix == DATA_PREFIX_OPCODE)
12527                 *obufp++ = 'd';
12528               else
12529                 *obufp++ = 's';
12530             }
12531           else
12532             {
12533               if (prefixes & PREFIX_DATA)
12534                 *obufp++ = 'd';
12535               else
12536                 *obufp++ = 's';
12537               used_prefixes |= (prefixes & PREFIX_DATA);
12538             }
12539           break;
12540         case 'Y':
12541           if (l == 0 && len == 1)
12542             {
12543               if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12544                 break;
12545               if (rex & REX_W)
12546                 {
12547                   USED_REX (REX_W);
12548                   *obufp++ = 'q';
12549                 }
12550               break;
12551             }
12552           else
12553             {
12554               if (l != 1 || len != 2 || last[0] != 'X')
12555                 {
12556                   SAVE_LAST (*p);
12557                   break;
12558                 }
12559               if (!need_vex)
12560                 abort ();
12561               if (intel_syntax
12562                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
12563                 break;
12564               switch (vex.length)
12565                 {
12566                 case 128:
12567                   *obufp++ = 'x';
12568                   break;
12569                 case 256:
12570                   *obufp++ = 'y';
12571                   break;
12572                 default:
12573                   abort ();
12574                 }
12575             }
12576           break;
12577         case 'W':
12578           if (l == 0 && len == 1)
12579             {
12580               /* operand size flag for cwtl, cbtw */
12581               USED_REX (REX_W);
12582               if (rex & REX_W)
12583                 {
12584                   if (intel_syntax)
12585                     *obufp++ = 'd';
12586                   else
12587                     *obufp++ = 'l';
12588                 }
12589               else if (sizeflag & DFLAG)
12590                 *obufp++ = 'w';
12591               else
12592                 *obufp++ = 'b';
12593               if (!(rex & REX_W))
12594                 used_prefixes |= (prefixes & PREFIX_DATA);
12595             }
12596           else
12597             {
12598               if (l != 1 || len != 2 || last[0] != 'X')
12599                 {
12600                   SAVE_LAST (*p);
12601                   break;
12602                 }
12603               if (!need_vex)
12604                 abort ();
12605               *obufp++ = vex.w ? 'd': 's';
12606             }
12607           break;
12608         }
12609       alt = 0;
12610     }
12611   *obufp = 0;
12612   mnemonicendp = obufp;
12613   return 0;
12614 }
12615
12616 static void
12617 oappend (const char *s)
12618 {
12619   obufp = stpcpy (obufp, s);
12620 }
12621
12622 static void
12623 append_seg (void)
12624 {
12625   if (prefixes & PREFIX_CS)
12626     {
12627       used_prefixes |= PREFIX_CS;
12628       oappend ("%cs:" + intel_syntax);
12629     }
12630   if (prefixes & PREFIX_DS)
12631     {
12632       used_prefixes |= PREFIX_DS;
12633       oappend ("%ds:" + intel_syntax);
12634     }
12635   if (prefixes & PREFIX_SS)
12636     {
12637       used_prefixes |= PREFIX_SS;
12638       oappend ("%ss:" + intel_syntax);
12639     }
12640   if (prefixes & PREFIX_ES)
12641     {
12642       used_prefixes |= PREFIX_ES;
12643       oappend ("%es:" + intel_syntax);
12644     }
12645   if (prefixes & PREFIX_FS)
12646     {
12647       used_prefixes |= PREFIX_FS;
12648       oappend ("%fs:" + intel_syntax);
12649     }
12650   if (prefixes & PREFIX_GS)
12651     {
12652       used_prefixes |= PREFIX_GS;
12653       oappend ("%gs:" + intel_syntax);
12654     }
12655 }
12656
12657 static void
12658 OP_indirE (int bytemode, int sizeflag)
12659 {
12660   if (!intel_syntax)
12661     oappend ("*");
12662   OP_E (bytemode, sizeflag);
12663 }
12664
12665 static void
12666 print_operand_value (char *buf, int hex, bfd_vma disp)
12667 {
12668   if (address_mode == mode_64bit)
12669     {
12670       if (hex)
12671         {
12672           char tmp[30];
12673           int i;
12674           buf[0] = '0';
12675           buf[1] = 'x';
12676           sprintf_vma (tmp, disp);
12677           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
12678           strcpy (buf + 2, tmp + i);
12679         }
12680       else
12681         {
12682           bfd_signed_vma v = disp;
12683           char tmp[30];
12684           int i;
12685           if (v < 0)
12686             {
12687               *(buf++) = '-';
12688               v = -disp;
12689               /* Check for possible overflow on 0x8000000000000000.  */
12690               if (v < 0)
12691                 {
12692                   strcpy (buf, "9223372036854775808");
12693                   return;
12694                 }
12695             }
12696           if (!v)
12697             {
12698               strcpy (buf, "0");
12699               return;
12700             }
12701
12702           i = 0;
12703           tmp[29] = 0;
12704           while (v)
12705             {
12706               tmp[28 - i] = (v % 10) + '0';
12707               v /= 10;
12708               i++;
12709             }
12710           strcpy (buf, tmp + 29 - i);
12711         }
12712     }
12713   else
12714     {
12715       if (hex)
12716         sprintf (buf, "0x%x", (unsigned int) disp);
12717       else
12718         sprintf (buf, "%d", (int) disp);
12719     }
12720 }
12721
12722 /* Put DISP in BUF as signed hex number.  */
12723
12724 static void
12725 print_displacement (char *buf, bfd_vma disp)
12726 {
12727   bfd_signed_vma val = disp;
12728   char tmp[30];
12729   int i, j = 0;
12730
12731   if (val < 0)
12732     {
12733       buf[j++] = '-';
12734       val = -disp;
12735
12736       /* Check for possible overflow.  */
12737       if (val < 0)
12738         {
12739           switch (address_mode)
12740             {
12741             case mode_64bit:
12742               strcpy (buf + j, "0x8000000000000000");
12743               break;
12744             case mode_32bit:
12745               strcpy (buf + j, "0x80000000");
12746               break;
12747             case mode_16bit:
12748               strcpy (buf + j, "0x8000");
12749               break;
12750             }
12751           return;
12752         }
12753     }
12754
12755   buf[j++] = '0';
12756   buf[j++] = 'x';
12757
12758   sprintf_vma (tmp, (bfd_vma) val);
12759   for (i = 0; tmp[i] == '0'; i++)
12760     continue;
12761   if (tmp[i] == '\0')
12762     i--;
12763   strcpy (buf + j, tmp + i);
12764 }
12765
12766 static void
12767 intel_operand_size (int bytemode, int sizeflag)
12768 {
12769   switch (bytemode)
12770     {
12771     case b_mode:
12772     case b_swap_mode:
12773     case dqb_mode:
12774       oappend ("BYTE PTR ");
12775       break;
12776     case w_mode:
12777     case dqw_mode:
12778       oappend ("WORD PTR ");
12779       break;
12780     case stack_v_mode:
12781       if (address_mode == mode_64bit && (sizeflag & DFLAG))
12782         {
12783           oappend ("QWORD PTR ");
12784           break;
12785         }
12786       /* FALLTHRU */
12787     case v_mode:
12788     case v_swap_mode:
12789     case dq_mode:
12790       USED_REX (REX_W);
12791       if (rex & REX_W)
12792         oappend ("QWORD PTR ");
12793       else
12794         {
12795           if ((sizeflag & DFLAG) || bytemode == dq_mode)
12796             oappend ("DWORD PTR ");
12797           else
12798             oappend ("WORD PTR ");
12799           used_prefixes |= (prefixes & PREFIX_DATA);
12800         }
12801       break;
12802     case z_mode:
12803       if ((rex & REX_W) || (sizeflag & DFLAG))
12804         *obufp++ = 'D';
12805       oappend ("WORD PTR ");
12806       if (!(rex & REX_W))
12807         used_prefixes |= (prefixes & PREFIX_DATA);
12808       break;
12809     case a_mode:
12810       if (sizeflag & DFLAG)
12811         oappend ("QWORD PTR ");
12812       else
12813         oappend ("DWORD PTR ");
12814       used_prefixes |= (prefixes & PREFIX_DATA);
12815       break;
12816     case d_mode:
12817     case d_scalar_mode:
12818     case d_scalar_swap_mode:
12819     case d_swap_mode:
12820     case dqd_mode:
12821       oappend ("DWORD PTR ");
12822       break;
12823     case q_mode:
12824     case q_scalar_mode:
12825     case q_scalar_swap_mode:
12826     case q_swap_mode:
12827       oappend ("QWORD PTR ");
12828       break;
12829     case m_mode:
12830       if (address_mode == mode_64bit)
12831         oappend ("QWORD PTR ");
12832       else
12833         oappend ("DWORD PTR ");
12834       break;
12835     case f_mode:
12836       if (sizeflag & DFLAG)
12837         oappend ("FWORD PTR ");
12838       else
12839         oappend ("DWORD PTR ");
12840       used_prefixes |= (prefixes & PREFIX_DATA);
12841       break;
12842     case t_mode:
12843       oappend ("TBYTE PTR ");
12844       break;
12845     case x_mode:
12846     case x_swap_mode:
12847       if (need_vex)
12848         {
12849           switch (vex.length)
12850             {
12851             case 128:
12852               oappend ("XMMWORD PTR ");
12853               break;
12854             case 256:
12855               oappend ("YMMWORD PTR ");
12856               break;
12857             default:
12858               abort ();
12859             }
12860         }
12861       else
12862         oappend ("XMMWORD PTR ");
12863       break;
12864     case xmm_mode:
12865       oappend ("XMMWORD PTR ");
12866       break;
12867     case xmmq_mode:
12868       if (!need_vex)
12869         abort ();
12870
12871       switch (vex.length)
12872         {
12873         case 128:
12874           oappend ("QWORD PTR ");
12875           break;
12876         case 256:
12877           oappend ("XMMWORD PTR ");
12878           break;
12879         default:
12880           abort ();
12881         }
12882       break;
12883     case ymmq_mode:
12884       if (!need_vex)
12885         abort ();
12886
12887       switch (vex.length)
12888         {
12889         case 128:
12890           oappend ("QWORD PTR ");
12891           break;
12892         case 256:
12893           oappend ("YMMWORD PTR ");
12894           break;
12895         default:
12896           abort ();
12897         }
12898       break;
12899     case o_mode:
12900       oappend ("OWORD PTR ");
12901       break;
12902     case vex_w_dq_mode:
12903     case vex_scalar_w_dq_mode:
12904       if (!need_vex)
12905         abort ();
12906
12907       if (vex.w)
12908         oappend ("QWORD PTR ");
12909       else
12910         oappend ("DWORD PTR ");
12911       break;
12912     default:
12913       break;
12914     }
12915 }
12916
12917 static void
12918 OP_E_register (int bytemode, int sizeflag)
12919 {
12920   int reg = modrm.rm;
12921   const char **names;
12922
12923   USED_REX (REX_B);
12924   if ((rex & REX_B))
12925     reg += 8;
12926
12927   if ((sizeflag & SUFFIX_ALWAYS)
12928       && (bytemode == b_swap_mode || bytemode == v_swap_mode))
12929     swap_operand ();
12930
12931   switch (bytemode)
12932     {
12933     case b_mode:
12934     case b_swap_mode:
12935       USED_REX (0);
12936       if (rex)
12937         names = names8rex;
12938       else
12939         names = names8;
12940       break;
12941     case w_mode:
12942       names = names16;
12943       break;
12944     case d_mode:
12945       names = names32;
12946       break;
12947     case q_mode:
12948       names = names64;
12949       break;
12950     case m_mode:
12951       names = address_mode == mode_64bit ? names64 : names32;
12952       break;
12953     case stack_v_mode:
12954       if (address_mode == mode_64bit && (sizeflag & DFLAG))
12955         {
12956           names = names64;
12957           break;
12958         }
12959       bytemode = v_mode;
12960       /* FALLTHRU */
12961     case v_mode:
12962     case v_swap_mode:
12963     case dq_mode:
12964     case dqb_mode:
12965     case dqd_mode:
12966     case dqw_mode:
12967       USED_REX (REX_W);
12968       if (rex & REX_W)
12969         names = names64;
12970       else
12971         {
12972           if ((sizeflag & DFLAG)
12973               || (bytemode != v_mode
12974                   && bytemode != v_swap_mode))
12975             names = names32;
12976           else
12977             names = names16;
12978           used_prefixes |= (prefixes & PREFIX_DATA);
12979         }
12980       break;
12981     case 0:
12982       return;
12983     default:
12984       oappend (INTERNAL_DISASSEMBLER_ERROR);
12985       return;
12986     }
12987   oappend (names[reg]);
12988 }
12989
12990 static void
12991 OP_E_memory (int bytemode, int sizeflag)
12992 {
12993   bfd_vma disp = 0;
12994   int add = (rex & REX_B) ? 8 : 0;
12995   int riprel = 0;
12996
12997   USED_REX (REX_B);
12998   if (intel_syntax)
12999     intel_operand_size (bytemode, sizeflag);
13000   append_seg ();
13001
13002   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
13003     {
13004       /* 32/64 bit address mode */
13005       int havedisp;
13006       int havesib;
13007       int havebase;
13008       int haveindex;
13009       int needindex;
13010       int base, rbase;
13011       int vindex = 0;
13012       int scale = 0;
13013
13014       havesib = 0;
13015       havebase = 1;
13016       haveindex = 0;
13017       base = modrm.rm;
13018
13019       if (base == 4)
13020         {
13021           havesib = 1;
13022           vindex = sib.index;
13023           scale = sib.scale;
13024           base = sib.base;
13025           USED_REX (REX_X);
13026           if (rex & REX_X)
13027             vindex += 8;
13028           haveindex = vindex != 4;
13029           codep++;
13030         }
13031       rbase = base + add;
13032
13033       switch (modrm.mod)
13034         {
13035         case 0:
13036           if (base == 5)
13037             {
13038               havebase = 0;
13039               if (address_mode == mode_64bit && !havesib)
13040                 riprel = 1;
13041               disp = get32s ();
13042             }
13043           break;
13044         case 1:
13045           FETCH_DATA (the_info, codep + 1);
13046           disp = *codep++;
13047           if ((disp & 0x80) != 0)
13048             disp -= 0x100;
13049           break;
13050         case 2:
13051           disp = get32s ();
13052           break;
13053         }
13054
13055       /* In 32bit mode, we need index register to tell [offset] from
13056          [eiz*1 + offset].  */
13057       needindex = (havesib
13058                    && !havebase
13059                    && !haveindex
13060                    && address_mode == mode_32bit);
13061       havedisp = (havebase
13062                   || needindex
13063                   || (havesib && (haveindex || scale != 0)));
13064
13065       if (!intel_syntax)
13066         if (modrm.mod != 0 || base == 5)
13067           {
13068             if (havedisp || riprel)
13069               print_displacement (scratchbuf, disp);
13070             else
13071               print_operand_value (scratchbuf, 1, disp);
13072             oappend (scratchbuf);
13073             if (riprel)
13074               {
13075                 set_op (disp, 1);
13076                 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
13077               }
13078           }
13079
13080       if (havebase || haveindex || riprel)
13081         used_prefixes |= PREFIX_ADDR;
13082
13083       if (havedisp || (intel_syntax && riprel))
13084         {
13085           *obufp++ = open_char;
13086           if (intel_syntax && riprel)
13087             {
13088               set_op (disp, 1);
13089               oappend (sizeflag & AFLAG ? "rip" : "eip");
13090             }
13091           *obufp = '\0';
13092           if (havebase)
13093             oappend (address_mode == mode_64bit && (sizeflag & AFLAG)
13094                      ? names64[rbase] : names32[rbase]);
13095           if (havesib)
13096             {
13097               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
13098                  print index to tell base + index from base.  */
13099               if (scale != 0
13100                   || needindex
13101                   || haveindex
13102                   || (havebase && base != ESP_REG_NUM))
13103                 {
13104                   if (!intel_syntax || havebase)
13105                     {
13106                       *obufp++ = separator_char;
13107                       *obufp = '\0';
13108                     }
13109                   if (haveindex)
13110                     oappend (address_mode == mode_64bit
13111                              && (sizeflag & AFLAG)
13112                              ? names64[vindex] : names32[vindex]);
13113                   else
13114                     oappend (address_mode == mode_64bit
13115                              && (sizeflag & AFLAG)
13116                              ? index64 : index32);
13117
13118                   *obufp++ = scale_char;
13119                   *obufp = '\0';
13120                   sprintf (scratchbuf, "%d", 1 << scale);
13121                   oappend (scratchbuf);
13122                 }
13123             }
13124           if (intel_syntax
13125               && (disp || modrm.mod != 0 || base == 5))
13126             {
13127               if (!havedisp || (bfd_signed_vma) disp >= 0)
13128                 {
13129                   *obufp++ = '+';
13130                   *obufp = '\0';
13131                 }
13132               else if (modrm.mod != 1 && disp != -disp)
13133                 {
13134                   *obufp++ = '-';
13135                   *obufp = '\0';
13136                   disp = - (bfd_signed_vma) disp;
13137                 }
13138
13139               if (havedisp)
13140                 print_displacement (scratchbuf, disp);
13141               else
13142                 print_operand_value (scratchbuf, 1, disp);
13143               oappend (scratchbuf);
13144             }
13145
13146           *obufp++ = close_char;
13147           *obufp = '\0';
13148         }
13149       else if (intel_syntax)
13150         {
13151           if (modrm.mod != 0 || base == 5)
13152             {
13153               if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13154                               | PREFIX_ES | PREFIX_FS | PREFIX_GS))
13155                 ;
13156               else
13157                 {
13158                   oappend (names_seg[ds_reg - es_reg]);
13159                   oappend (":");
13160                 }
13161               print_operand_value (scratchbuf, 1, disp);
13162               oappend (scratchbuf);
13163             }
13164         }
13165     }
13166   else
13167     {
13168       /* 16 bit address mode */
13169       used_prefixes |= prefixes & PREFIX_ADDR;
13170       switch (modrm.mod)
13171         {
13172         case 0:
13173           if (modrm.rm == 6)
13174             {
13175               disp = get16 ();
13176               if ((disp & 0x8000) != 0)
13177                 disp -= 0x10000;
13178             }
13179           break;
13180         case 1:
13181           FETCH_DATA (the_info, codep + 1);
13182           disp = *codep++;
13183           if ((disp & 0x80) != 0)
13184             disp -= 0x100;
13185           break;
13186         case 2:
13187           disp = get16 ();
13188           if ((disp & 0x8000) != 0)
13189             disp -= 0x10000;
13190           break;
13191         }
13192
13193       if (!intel_syntax)
13194         if (modrm.mod != 0 || modrm.rm == 6)
13195           {
13196             print_displacement (scratchbuf, disp);
13197             oappend (scratchbuf);
13198           }
13199
13200       if (modrm.mod != 0 || modrm.rm != 6)
13201         {
13202           *obufp++ = open_char;
13203           *obufp = '\0';
13204           oappend (index16[modrm.rm]);
13205           if (intel_syntax
13206               && (disp || modrm.mod != 0 || modrm.rm == 6))
13207             {
13208               if ((bfd_signed_vma) disp >= 0)
13209                 {
13210                   *obufp++ = '+';
13211                   *obufp = '\0';
13212                 }
13213               else if (modrm.mod != 1)
13214                 {
13215                   *obufp++ = '-';
13216                   *obufp = '\0';
13217                   disp = - (bfd_signed_vma) disp;
13218                 }
13219
13220               print_displacement (scratchbuf, disp);
13221               oappend (scratchbuf);
13222             }
13223
13224           *obufp++ = close_char;
13225           *obufp = '\0';
13226         }
13227       else if (intel_syntax)
13228         {
13229           if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13230                           | PREFIX_ES | PREFIX_FS | PREFIX_GS))
13231             ;
13232           else
13233             {
13234               oappend (names_seg[ds_reg - es_reg]);
13235               oappend (":");
13236             }
13237           print_operand_value (scratchbuf, 1, disp & 0xffff);
13238           oappend (scratchbuf);
13239         }
13240     }
13241 }
13242
13243 static void
13244 OP_E (int bytemode, int sizeflag)
13245 {
13246   /* Skip mod/rm byte.  */
13247   MODRM_CHECK;
13248   codep++;
13249
13250   if (modrm.mod == 3)
13251     OP_E_register (bytemode, sizeflag);
13252   else
13253     OP_E_memory (bytemode, sizeflag);
13254 }
13255
13256 static void
13257 OP_G (int bytemode, int sizeflag)
13258 {
13259   int add = 0;
13260   USED_REX (REX_R);
13261   if (rex & REX_R)
13262     add += 8;
13263   switch (bytemode)
13264     {
13265     case b_mode:
13266       USED_REX (0);
13267       if (rex)
13268         oappend (names8rex[modrm.reg + add]);
13269       else
13270         oappend (names8[modrm.reg + add]);
13271       break;
13272     case w_mode:
13273       oappend (names16[modrm.reg + add]);
13274       break;
13275     case d_mode:
13276       oappend (names32[modrm.reg + add]);
13277       break;
13278     case q_mode:
13279       oappend (names64[modrm.reg + add]);
13280       break;
13281     case v_mode:
13282     case dq_mode:
13283     case dqb_mode:
13284     case dqd_mode:
13285     case dqw_mode:
13286       USED_REX (REX_W);
13287       if (rex & REX_W)
13288         oappend (names64[modrm.reg + add]);
13289       else
13290         {
13291           if ((sizeflag & DFLAG) || bytemode != v_mode)
13292             oappend (names32[modrm.reg + add]);
13293           else
13294             oappend (names16[modrm.reg + add]);
13295           used_prefixes |= (prefixes & PREFIX_DATA);
13296         }
13297       break;
13298     case m_mode:
13299       if (address_mode == mode_64bit)
13300         oappend (names64[modrm.reg + add]);
13301       else
13302         oappend (names32[modrm.reg + add]);
13303       break;
13304     default:
13305       oappend (INTERNAL_DISASSEMBLER_ERROR);
13306       break;
13307     }
13308 }
13309
13310 static bfd_vma
13311 get64 (void)
13312 {
13313   bfd_vma x;
13314 #ifdef BFD64
13315   unsigned int a;
13316   unsigned int b;
13317
13318   FETCH_DATA (the_info, codep + 8);
13319   a = *codep++ & 0xff;
13320   a |= (*codep++ & 0xff) << 8;
13321   a |= (*codep++ & 0xff) << 16;
13322   a |= (*codep++ & 0xff) << 24;
13323   b = *codep++ & 0xff;
13324   b |= (*codep++ & 0xff) << 8;
13325   b |= (*codep++ & 0xff) << 16;
13326   b |= (*codep++ & 0xff) << 24;
13327   x = a + ((bfd_vma) b << 32);
13328 #else
13329   abort ();
13330   x = 0;
13331 #endif
13332   return x;
13333 }
13334
13335 static bfd_signed_vma
13336 get32 (void)
13337 {
13338   bfd_signed_vma x = 0;
13339
13340   FETCH_DATA (the_info, codep + 4);
13341   x = *codep++ & (bfd_signed_vma) 0xff;
13342   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
13343   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
13344   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
13345   return x;
13346 }
13347
13348 static bfd_signed_vma
13349 get32s (void)
13350 {
13351   bfd_signed_vma x = 0;
13352
13353   FETCH_DATA (the_info, codep + 4);
13354   x = *codep++ & (bfd_signed_vma) 0xff;
13355   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
13356   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
13357   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
13358
13359   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
13360
13361   return x;
13362 }
13363
13364 static int
13365 get16 (void)
13366 {
13367   int x = 0;
13368
13369   FETCH_DATA (the_info, codep + 2);
13370   x = *codep++ & 0xff;
13371   x |= (*codep++ & 0xff) << 8;
13372   return x;
13373 }
13374
13375 static void
13376 set_op (bfd_vma op, int riprel)
13377 {
13378   op_index[op_ad] = op_ad;
13379   if (address_mode == mode_64bit)
13380     {
13381       op_address[op_ad] = op;
13382       op_riprel[op_ad] = riprel;
13383     }
13384   else
13385     {
13386       /* Mask to get a 32-bit address.  */
13387       op_address[op_ad] = op & 0xffffffff;
13388       op_riprel[op_ad] = riprel & 0xffffffff;
13389     }
13390 }
13391
13392 static void
13393 OP_REG (int code, int sizeflag)
13394 {
13395   const char *s;
13396   int add;
13397   USED_REX (REX_B);
13398   if (rex & REX_B)
13399     add = 8;
13400   else
13401     add = 0;
13402
13403   switch (code)
13404     {
13405     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
13406     case sp_reg: case bp_reg: case si_reg: case di_reg:
13407       s = names16[code - ax_reg + add];
13408       break;
13409     case es_reg: case ss_reg: case cs_reg:
13410     case ds_reg: case fs_reg: case gs_reg:
13411       s = names_seg[code - es_reg + add];
13412       break;
13413     case al_reg: case ah_reg: case cl_reg: case ch_reg:
13414     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
13415       USED_REX (0);
13416       if (rex)
13417         s = names8rex[code - al_reg + add];
13418       else
13419         s = names8[code - al_reg];
13420       break;
13421     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
13422     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
13423       if (address_mode == mode_64bit && (sizeflag & DFLAG))
13424         {
13425           s = names64[code - rAX_reg + add];
13426           break;
13427         }
13428       code += eAX_reg - rAX_reg;
13429       /* Fall through.  */
13430     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
13431     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
13432       USED_REX (REX_W);
13433       if (rex & REX_W)
13434         s = names64[code - eAX_reg + add];
13435       else
13436         {
13437           if (sizeflag & DFLAG)
13438             s = names32[code - eAX_reg + add];
13439           else
13440             s = names16[code - eAX_reg + add];
13441           used_prefixes |= (prefixes & PREFIX_DATA);
13442         }
13443       break;
13444     default:
13445       s = INTERNAL_DISASSEMBLER_ERROR;
13446       break;
13447     }
13448   oappend (s);
13449 }
13450
13451 static void
13452 OP_IMREG (int code, int sizeflag)
13453 {
13454   const char *s;
13455
13456   switch (code)
13457     {
13458     case indir_dx_reg:
13459       if (intel_syntax)
13460         s = "dx";
13461       else
13462         s = "(%dx)";
13463       break;
13464     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
13465     case sp_reg: case bp_reg: case si_reg: case di_reg:
13466       s = names16[code - ax_reg];
13467       break;
13468     case es_reg: case ss_reg: case cs_reg:
13469     case ds_reg: case fs_reg: case gs_reg:
13470       s = names_seg[code - es_reg];
13471       break;
13472     case al_reg: case ah_reg: case cl_reg: case ch_reg:
13473     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
13474       USED_REX (0);
13475       if (rex)
13476         s = names8rex[code - al_reg];
13477       else
13478         s = names8[code - al_reg];
13479       break;
13480     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
13481     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
13482       USED_REX (REX_W);
13483       if (rex & REX_W)
13484         s = names64[code - eAX_reg];
13485       else
13486         {
13487           if (sizeflag & DFLAG)
13488             s = names32[code - eAX_reg];
13489           else
13490             s = names16[code - eAX_reg];
13491           used_prefixes |= (prefixes & PREFIX_DATA);
13492         }
13493       break;
13494     case z_mode_ax_reg:
13495       if ((rex & REX_W) || (sizeflag & DFLAG))
13496         s = *names32;
13497       else
13498         s = *names16;
13499       if (!(rex & REX_W))
13500         used_prefixes |= (prefixes & PREFIX_DATA);
13501       break;
13502     default:
13503       s = INTERNAL_DISASSEMBLER_ERROR;
13504       break;
13505     }
13506   oappend (s);
13507 }
13508
13509 static void
13510 OP_I (int bytemode, int sizeflag)
13511 {
13512   bfd_signed_vma op;
13513   bfd_signed_vma mask = -1;
13514
13515   switch (bytemode)
13516     {
13517     case b_mode:
13518       FETCH_DATA (the_info, codep + 1);
13519       op = *codep++;
13520       mask = 0xff;
13521       break;
13522     case q_mode:
13523       if (address_mode == mode_64bit)
13524         {
13525           op = get32s ();
13526           break;
13527         }
13528       /* Fall through.  */
13529     case v_mode:
13530       USED_REX (REX_W);
13531       if (rex & REX_W)
13532         op = get32s ();
13533       else
13534         {
13535           if (sizeflag & DFLAG)
13536             {
13537               op = get32 ();
13538               mask = 0xffffffff;
13539             }
13540           else
13541             {
13542               op = get16 ();
13543               mask = 0xfffff;
13544             }
13545           used_prefixes |= (prefixes & PREFIX_DATA);
13546         }
13547       break;
13548     case w_mode:
13549       mask = 0xfffff;
13550       op = get16 ();
13551       break;
13552     case const_1_mode:
13553       if (intel_syntax)
13554         oappend ("1");
13555       return;
13556     default:
13557       oappend (INTERNAL_DISASSEMBLER_ERROR);
13558       return;
13559     }
13560
13561   op &= mask;
13562   scratchbuf[0] = '$';
13563   print_operand_value (scratchbuf + 1, 1, op);
13564   oappend (scratchbuf + intel_syntax);
13565   scratchbuf[0] = '\0';
13566 }
13567
13568 static void
13569 OP_I64 (int bytemode, int sizeflag)
13570 {
13571   bfd_signed_vma op;
13572   bfd_signed_vma mask = -1;
13573
13574   if (address_mode != mode_64bit)
13575     {
13576       OP_I (bytemode, sizeflag);
13577       return;
13578     }
13579
13580   switch (bytemode)
13581     {
13582     case b_mode:
13583       FETCH_DATA (the_info, codep + 1);
13584       op = *codep++;
13585       mask = 0xff;
13586       break;
13587     case v_mode:
13588       USED_REX (REX_W);
13589       if (rex & REX_W)
13590         op = get64 ();
13591       else
13592         {
13593           if (sizeflag & DFLAG)
13594             {
13595               op = get32 ();
13596               mask = 0xffffffff;
13597             }
13598           else
13599             {
13600               op = get16 ();
13601               mask = 0xfffff;
13602             }
13603           used_prefixes |= (prefixes & PREFIX_DATA);
13604         }
13605       break;
13606     case w_mode:
13607       mask = 0xfffff;
13608       op = get16 ();
13609       break;
13610     default:
13611       oappend (INTERNAL_DISASSEMBLER_ERROR);
13612       return;
13613     }
13614
13615   op &= mask;
13616   scratchbuf[0] = '$';
13617   print_operand_value (scratchbuf + 1, 1, op);
13618   oappend (scratchbuf + intel_syntax);
13619   scratchbuf[0] = '\0';
13620 }
13621
13622 static void
13623 OP_sI (int bytemode, int sizeflag)
13624 {
13625   bfd_signed_vma op;
13626
13627   switch (bytemode)
13628     {
13629     case b_mode:
13630       FETCH_DATA (the_info, codep + 1);
13631       op = *codep++;
13632       if ((op & 0x80) != 0)
13633         op -= 0x100;
13634       break;
13635     case v_mode:
13636       if (sizeflag & DFLAG)
13637         op = get32s ();
13638       else
13639         op = get16 ();
13640       break;
13641     default:
13642       oappend (INTERNAL_DISASSEMBLER_ERROR);
13643       return;
13644     }
13645
13646   scratchbuf[0] = '$';
13647   print_operand_value (scratchbuf + 1, 1, op);
13648   oappend (scratchbuf + intel_syntax);
13649 }
13650
13651 static void
13652 OP_J (int bytemode, int sizeflag)
13653 {
13654   bfd_vma disp;
13655   bfd_vma mask = -1;
13656   bfd_vma segment = 0;
13657
13658   switch (bytemode)
13659     {
13660     case b_mode:
13661       FETCH_DATA (the_info, codep + 1);
13662       disp = *codep++;
13663       if ((disp & 0x80) != 0)
13664         disp -= 0x100;
13665       break;
13666     case v_mode:
13667       USED_REX (REX_W);
13668       if ((sizeflag & DFLAG) || (rex & REX_W))
13669         disp = get32s ();
13670       else
13671         {
13672           disp = get16 ();
13673           if ((disp & 0x8000) != 0)
13674             disp -= 0x10000;
13675           /* In 16bit mode, address is wrapped around at 64k within
13676              the same segment.  Otherwise, a data16 prefix on a jump
13677              instruction means that the pc is masked to 16 bits after
13678              the displacement is added!  */
13679           mask = 0xffff;
13680           if ((prefixes & PREFIX_DATA) == 0)
13681             segment = ((start_pc + codep - start_codep)
13682                        & ~((bfd_vma) 0xffff));
13683         }
13684       if (!(rex & REX_W))
13685         used_prefixes |= (prefixes & PREFIX_DATA);
13686       break;
13687     default:
13688       oappend (INTERNAL_DISASSEMBLER_ERROR);
13689       return;
13690     }
13691   disp = ((start_pc + codep - start_codep + disp) & mask) | segment;
13692   set_op (disp, 0);
13693   print_operand_value (scratchbuf, 1, disp);
13694   oappend (scratchbuf);
13695 }
13696
13697 static void
13698 OP_SEG (int bytemode, int sizeflag)
13699 {
13700   if (bytemode == w_mode)
13701     oappend (names_seg[modrm.reg]);
13702   else
13703     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
13704 }
13705
13706 static void
13707 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
13708 {
13709   int seg, offset;
13710
13711   if (sizeflag & DFLAG)
13712     {
13713       offset = get32 ();
13714       seg = get16 ();
13715     }
13716   else
13717     {
13718       offset = get16 ();
13719       seg = get16 ();
13720     }
13721   used_prefixes |= (prefixes & PREFIX_DATA);
13722   if (intel_syntax)
13723     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
13724   else
13725     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
13726   oappend (scratchbuf);
13727 }
13728
13729 static void
13730 OP_OFF (int bytemode, int sizeflag)
13731 {
13732   bfd_vma off;
13733
13734   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
13735     intel_operand_size (bytemode, sizeflag);
13736   append_seg ();
13737
13738   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
13739     off = get32 ();
13740   else
13741     off = get16 ();
13742
13743   if (intel_syntax)
13744     {
13745       if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13746                         | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
13747         {
13748           oappend (names_seg[ds_reg - es_reg]);
13749           oappend (":");
13750         }
13751     }
13752   print_operand_value (scratchbuf, 1, off);
13753   oappend (scratchbuf);
13754 }
13755
13756 static void
13757 OP_OFF64 (int bytemode, int sizeflag)
13758 {
13759   bfd_vma off;
13760
13761   if (address_mode != mode_64bit
13762       || (prefixes & PREFIX_ADDR))
13763     {
13764       OP_OFF (bytemode, sizeflag);
13765       return;
13766     }
13767
13768   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
13769     intel_operand_size (bytemode, sizeflag);
13770   append_seg ();
13771
13772   off = get64 ();
13773
13774   if (intel_syntax)
13775     {
13776       if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13777                         | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
13778         {
13779           oappend (names_seg[ds_reg - es_reg]);
13780           oappend (":");
13781         }
13782     }
13783   print_operand_value (scratchbuf, 1, off);
13784   oappend (scratchbuf);
13785 }
13786
13787 static void
13788 ptr_reg (int code, int sizeflag)
13789 {
13790   const char *s;
13791
13792   *obufp++ = open_char;
13793   used_prefixes |= (prefixes & PREFIX_ADDR);
13794   if (address_mode == mode_64bit)
13795     {
13796       if (!(sizeflag & AFLAG))
13797         s = names32[code - eAX_reg];
13798       else
13799         s = names64[code - eAX_reg];
13800     }
13801   else if (sizeflag & AFLAG)
13802     s = names32[code - eAX_reg];
13803   else
13804     s = names16[code - eAX_reg];
13805   oappend (s);
13806   *obufp++ = close_char;
13807   *obufp = 0;
13808 }
13809
13810 static void
13811 OP_ESreg (int code, int sizeflag)
13812 {
13813   if (intel_syntax)
13814     {
13815       switch (codep[-1])
13816         {
13817         case 0x6d:      /* insw/insl */
13818           intel_operand_size (z_mode, sizeflag);
13819           break;
13820         case 0xa5:      /* movsw/movsl/movsq */
13821         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
13822         case 0xab:      /* stosw/stosl */
13823         case 0xaf:      /* scasw/scasl */
13824           intel_operand_size (v_mode, sizeflag);
13825           break;
13826         default:
13827           intel_operand_size (b_mode, sizeflag);
13828         }
13829     }
13830   oappend ("%es:" + intel_syntax);
13831   ptr_reg (code, sizeflag);
13832 }
13833
13834 static void
13835 OP_DSreg (int code, int sizeflag)
13836 {
13837   if (intel_syntax)
13838     {
13839       switch (codep[-1])
13840         {
13841         case 0x6f:      /* outsw/outsl */
13842           intel_operand_size (z_mode, sizeflag);
13843           break;
13844         case 0xa5:      /* movsw/movsl/movsq */
13845         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
13846         case 0xad:      /* lodsw/lodsl/lodsq */
13847           intel_operand_size (v_mode, sizeflag);
13848           break;
13849         default:
13850           intel_operand_size (b_mode, sizeflag);
13851         }
13852     }
13853   if ((prefixes
13854        & (PREFIX_CS
13855           | PREFIX_DS
13856           | PREFIX_SS
13857           | PREFIX_ES
13858           | PREFIX_FS
13859           | PREFIX_GS)) == 0)
13860     prefixes |= PREFIX_DS;
13861   append_seg ();
13862   ptr_reg (code, sizeflag);
13863 }
13864
13865 static void
13866 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13867 {
13868   int add;
13869   if (rex & REX_R)
13870     {
13871       USED_REX (REX_R);
13872       add = 8;
13873     }
13874   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
13875     {
13876       all_prefixes[last_lock_prefix] = 0;
13877       used_prefixes |= PREFIX_LOCK;
13878       add = 8;
13879     }
13880   else
13881     add = 0;
13882   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
13883   oappend (scratchbuf + intel_syntax);
13884 }
13885
13886 static void
13887 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13888 {
13889   int add;
13890   USED_REX (REX_R);
13891   if (rex & REX_R)
13892     add = 8;
13893   else
13894     add = 0;
13895   if (intel_syntax)
13896     sprintf (scratchbuf, "db%d", modrm.reg + add);
13897   else
13898     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
13899   oappend (scratchbuf);
13900 }
13901
13902 static void
13903 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13904 {
13905   sprintf (scratchbuf, "%%tr%d", modrm.reg);
13906   oappend (scratchbuf + intel_syntax);
13907 }
13908
13909 static void
13910 OP_R (int bytemode, int sizeflag)
13911 {
13912   if (modrm.mod == 3)
13913     OP_E (bytemode, sizeflag);
13914   else
13915     BadOp ();
13916 }
13917
13918 static void
13919 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13920 {
13921   int reg = modrm.reg;
13922   const char **names;
13923
13924   used_prefixes |= (prefixes & PREFIX_DATA);
13925   if (prefixes & PREFIX_DATA)
13926     {
13927       names = names_xmm;
13928       USED_REX (REX_R);
13929       if (rex & REX_R)
13930         reg += 8;
13931     }
13932   else
13933     names = names_mm;
13934   oappend (names[reg]);
13935 }
13936
13937 static void
13938 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13939 {
13940   int reg = modrm.reg;
13941   const char **names;
13942
13943   USED_REX (REX_R);
13944   if (rex & REX_R)
13945     reg += 8;
13946   if (need_vex
13947       && bytemode != xmm_mode
13948       && bytemode != scalar_mode)
13949     {
13950       switch (vex.length)
13951         {
13952         case 128:
13953           names = names_xmm;
13954           break;
13955         case 256:
13956           names = names_ymm;
13957           break;
13958         default:
13959           abort ();
13960         }
13961     }
13962   else
13963     names = names_xmm;
13964   oappend (names[reg]);
13965 }
13966
13967 static void
13968 OP_EM (int bytemode, int sizeflag)
13969 {
13970   int reg;
13971   const char **names;
13972
13973   if (modrm.mod != 3)
13974     {
13975       if (intel_syntax
13976           && (bytemode == v_mode || bytemode == v_swap_mode))
13977         {
13978           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
13979           used_prefixes |= (prefixes & PREFIX_DATA);
13980         }
13981       OP_E (bytemode, sizeflag);
13982       return;
13983     }
13984
13985   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
13986     swap_operand ();
13987
13988   /* Skip mod/rm byte.  */
13989   MODRM_CHECK;
13990   codep++;
13991   used_prefixes |= (prefixes & PREFIX_DATA);
13992   reg = modrm.rm;
13993   if (prefixes & PREFIX_DATA)
13994     {
13995       names = names_xmm;
13996       USED_REX (REX_B);
13997       if (rex & REX_B)
13998         reg += 8;
13999     }
14000   else
14001     names = names_mm;
14002   oappend (names[reg]);
14003 }
14004
14005 /* cvt* are the only instructions in sse2 which have
14006    both SSE and MMX operands and also have 0x66 prefix
14007    in their opcode. 0x66 was originally used to differentiate
14008    between SSE and MMX instruction(operands). So we have to handle the
14009    cvt* separately using OP_EMC and OP_MXC */
14010 static void
14011 OP_EMC (int bytemode, int sizeflag)
14012 {
14013   if (modrm.mod != 3)
14014     {
14015       if (intel_syntax && bytemode == v_mode)
14016         {
14017           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
14018           used_prefixes |= (prefixes & PREFIX_DATA);
14019         }
14020       OP_E (bytemode, sizeflag);
14021       return;
14022     }
14023
14024   /* Skip mod/rm byte.  */
14025   MODRM_CHECK;
14026   codep++;
14027   used_prefixes |= (prefixes & PREFIX_DATA);
14028   oappend (names_mm[modrm.rm]);
14029 }
14030
14031 static void
14032 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14033 {
14034   used_prefixes |= (prefixes & PREFIX_DATA);
14035   oappend (names_mm[modrm.reg]);
14036 }
14037
14038 static void
14039 OP_EX (int bytemode, int sizeflag)
14040 {
14041   int reg;
14042   const char **names;
14043
14044   /* Skip mod/rm byte.  */
14045   MODRM_CHECK;
14046   codep++;
14047
14048   if (modrm.mod != 3)
14049     {
14050       OP_E_memory (bytemode, sizeflag);
14051       return;
14052     }
14053
14054   reg = modrm.rm;
14055   USED_REX (REX_B);
14056   if (rex & REX_B)
14057     reg += 8;
14058
14059   if ((sizeflag & SUFFIX_ALWAYS)
14060       && (bytemode == x_swap_mode
14061           || bytemode == d_swap_mode
14062           || bytemode == d_scalar_swap_mode
14063           || bytemode == q_swap_mode
14064           || bytemode == q_scalar_swap_mode))
14065     swap_operand ();
14066
14067   if (need_vex
14068       && bytemode != xmm_mode
14069       && bytemode != xmmq_mode
14070       && bytemode != d_scalar_mode
14071       && bytemode != d_scalar_swap_mode
14072       && bytemode != q_scalar_mode
14073       && bytemode != q_scalar_swap_mode
14074       && bytemode != vex_scalar_w_dq_mode)
14075     {
14076       switch (vex.length)
14077         {
14078         case 128:
14079           names = names_xmm;
14080           break;
14081         case 256:
14082           names = names_ymm;
14083           break;
14084         default:
14085           abort ();
14086         }
14087     }
14088   else
14089     names = names_xmm;
14090   oappend (names[reg]);
14091 }
14092
14093 static void
14094 OP_MS (int bytemode, int sizeflag)
14095 {
14096   if (modrm.mod == 3)
14097     OP_EM (bytemode, sizeflag);
14098   else
14099     BadOp ();
14100 }
14101
14102 static void
14103 OP_XS (int bytemode, int sizeflag)
14104 {
14105   if (modrm.mod == 3)
14106     OP_EX (bytemode, sizeflag);
14107   else
14108     BadOp ();
14109 }
14110
14111 static void
14112 OP_M (int bytemode, int sizeflag)
14113 {
14114   if (modrm.mod == 3)
14115     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
14116     BadOp ();
14117   else
14118     OP_E (bytemode, sizeflag);
14119 }
14120
14121 static void
14122 OP_0f07 (int bytemode, int sizeflag)
14123 {
14124   if (modrm.mod != 3 || modrm.rm != 0)
14125     BadOp ();
14126   else
14127     OP_E (bytemode, sizeflag);
14128 }
14129
14130 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
14131    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
14132
14133 static void
14134 NOP_Fixup1 (int bytemode, int sizeflag)
14135 {
14136   if ((prefixes & PREFIX_DATA) != 0
14137       || (rex != 0
14138           && rex != 0x48
14139           && address_mode == mode_64bit))
14140     OP_REG (bytemode, sizeflag);
14141   else
14142     strcpy (obuf, "nop");
14143 }
14144
14145 static void
14146 NOP_Fixup2 (int bytemode, int sizeflag)
14147 {
14148   if ((prefixes & PREFIX_DATA) != 0
14149       || (rex != 0
14150           && rex != 0x48
14151           && address_mode == mode_64bit))
14152     OP_IMREG (bytemode, sizeflag);
14153 }
14154
14155 static const char *const Suffix3DNow[] = {
14156 /* 00 */        NULL,           NULL,           NULL,           NULL,
14157 /* 04 */        NULL,           NULL,           NULL,           NULL,
14158 /* 08 */        NULL,           NULL,           NULL,           NULL,
14159 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
14160 /* 10 */        NULL,           NULL,           NULL,           NULL,
14161 /* 14 */        NULL,           NULL,           NULL,           NULL,
14162 /* 18 */        NULL,           NULL,           NULL,           NULL,
14163 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
14164 /* 20 */        NULL,           NULL,           NULL,           NULL,
14165 /* 24 */        NULL,           NULL,           NULL,           NULL,
14166 /* 28 */        NULL,           NULL,           NULL,           NULL,
14167 /* 2C */        NULL,           NULL,           NULL,           NULL,
14168 /* 30 */        NULL,           NULL,           NULL,           NULL,
14169 /* 34 */        NULL,           NULL,           NULL,           NULL,
14170 /* 38 */        NULL,           NULL,           NULL,           NULL,
14171 /* 3C */        NULL,           NULL,           NULL,           NULL,
14172 /* 40 */        NULL,           NULL,           NULL,           NULL,
14173 /* 44 */        NULL,           NULL,           NULL,           NULL,
14174 /* 48 */        NULL,           NULL,           NULL,           NULL,
14175 /* 4C */        NULL,           NULL,           NULL,           NULL,
14176 /* 50 */        NULL,           NULL,           NULL,           NULL,
14177 /* 54 */        NULL,           NULL,           NULL,           NULL,
14178 /* 58 */        NULL,           NULL,           NULL,           NULL,
14179 /* 5C */        NULL,           NULL,           NULL,           NULL,
14180 /* 60 */        NULL,           NULL,           NULL,           NULL,
14181 /* 64 */        NULL,           NULL,           NULL,           NULL,
14182 /* 68 */        NULL,           NULL,           NULL,           NULL,
14183 /* 6C */        NULL,           NULL,           NULL,           NULL,
14184 /* 70 */        NULL,           NULL,           NULL,           NULL,
14185 /* 74 */        NULL,           NULL,           NULL,           NULL,
14186 /* 78 */        NULL,           NULL,           NULL,           NULL,
14187 /* 7C */        NULL,           NULL,           NULL,           NULL,
14188 /* 80 */        NULL,           NULL,           NULL,           NULL,
14189 /* 84 */        NULL,           NULL,           NULL,           NULL,
14190 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
14191 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
14192 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
14193 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
14194 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
14195 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
14196 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
14197 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
14198 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
14199 /* AC */        NULL,           NULL,           "pfacc",        NULL,
14200 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
14201 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
14202 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
14203 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
14204 /* C0 */        NULL,           NULL,           NULL,           NULL,
14205 /* C4 */        NULL,           NULL,           NULL,           NULL,
14206 /* C8 */        NULL,           NULL,           NULL,           NULL,
14207 /* CC */        NULL,           NULL,           NULL,           NULL,
14208 /* D0 */        NULL,           NULL,           NULL,           NULL,
14209 /* D4 */        NULL,           NULL,           NULL,           NULL,
14210 /* D8 */        NULL,           NULL,           NULL,           NULL,
14211 /* DC */        NULL,           NULL,           NULL,           NULL,
14212 /* E0 */        NULL,           NULL,           NULL,           NULL,
14213 /* E4 */        NULL,           NULL,           NULL,           NULL,
14214 /* E8 */        NULL,           NULL,           NULL,           NULL,
14215 /* EC */        NULL,           NULL,           NULL,           NULL,
14216 /* F0 */        NULL,           NULL,           NULL,           NULL,
14217 /* F4 */        NULL,           NULL,           NULL,           NULL,
14218 /* F8 */        NULL,           NULL,           NULL,           NULL,
14219 /* FC */        NULL,           NULL,           NULL,           NULL,
14220 };
14221
14222 static void
14223 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14224 {
14225   const char *mnemonic;
14226
14227   FETCH_DATA (the_info, codep + 1);
14228   /* AMD 3DNow! instructions are specified by an opcode suffix in the
14229      place where an 8-bit immediate would normally go.  ie. the last
14230      byte of the instruction.  */
14231   obufp = mnemonicendp;
14232   mnemonic = Suffix3DNow[*codep++ & 0xff];
14233   if (mnemonic)
14234     oappend (mnemonic);
14235   else
14236     {
14237       /* Since a variable sized modrm/sib chunk is between the start
14238          of the opcode (0x0f0f) and the opcode suffix, we need to do
14239          all the modrm processing first, and don't know until now that
14240          we have a bad opcode.  This necessitates some cleaning up.  */
14241       op_out[0][0] = '\0';
14242       op_out[1][0] = '\0';
14243       BadOp ();
14244     }
14245   mnemonicendp = obufp;
14246 }
14247
14248 static struct op simd_cmp_op[] =
14249 {
14250   { STRING_COMMA_LEN ("eq") },
14251   { STRING_COMMA_LEN ("lt") },
14252   { STRING_COMMA_LEN ("le") },
14253   { STRING_COMMA_LEN ("unord") },
14254   { STRING_COMMA_LEN ("neq") },
14255   { STRING_COMMA_LEN ("nlt") },
14256   { STRING_COMMA_LEN ("nle") },
14257   { STRING_COMMA_LEN ("ord") }
14258 };
14259
14260 static void
14261 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14262 {
14263   unsigned int cmp_type;
14264
14265   FETCH_DATA (the_info, codep + 1);
14266   cmp_type = *codep++ & 0xff;
14267   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
14268     {
14269       char suffix [3];
14270       char *p = mnemonicendp - 2;
14271       suffix[0] = p[0];
14272       suffix[1] = p[1];
14273       suffix[2] = '\0';
14274       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
14275       mnemonicendp += simd_cmp_op[cmp_type].len;
14276     }
14277   else
14278     {
14279       /* We have a reserved extension byte.  Output it directly.  */
14280       scratchbuf[0] = '$';
14281       print_operand_value (scratchbuf + 1, 1, cmp_type);
14282       oappend (scratchbuf + intel_syntax);
14283       scratchbuf[0] = '\0';
14284     }
14285 }
14286
14287 static void
14288 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
14289           int sizeflag ATTRIBUTE_UNUSED)
14290 {
14291   /* mwait %eax,%ecx  */
14292   if (!intel_syntax)
14293     {
14294       const char **names = (address_mode == mode_64bit
14295                             ? names64 : names32);
14296       strcpy (op_out[0], names[0]);
14297       strcpy (op_out[1], names[1]);
14298       two_source_ops = 1;
14299     }
14300   /* Skip mod/rm byte.  */
14301   MODRM_CHECK;
14302   codep++;
14303 }
14304
14305 static void
14306 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
14307             int sizeflag ATTRIBUTE_UNUSED)
14308 {
14309   /* monitor %eax,%ecx,%edx"  */
14310   if (!intel_syntax)
14311     {
14312       const char **op1_names;
14313       const char **names = (address_mode == mode_64bit
14314                             ? names64 : names32);
14315
14316       if (!(prefixes & PREFIX_ADDR))
14317         op1_names = (address_mode == mode_16bit
14318                      ? names16 : names);
14319       else
14320         {
14321           /* Remove "addr16/addr32".  */
14322           all_prefixes[last_addr_prefix] = 0;
14323           op1_names = (address_mode != mode_32bit
14324                        ? names32 : names16);
14325           used_prefixes |= PREFIX_ADDR;
14326         }
14327       strcpy (op_out[0], op1_names[0]);
14328       strcpy (op_out[1], names[1]);
14329       strcpy (op_out[2], names[2]);
14330       two_source_ops = 1;
14331     }
14332   /* Skip mod/rm byte.  */
14333   MODRM_CHECK;
14334   codep++;
14335 }
14336
14337 static void
14338 BadOp (void)
14339 {
14340   /* Throw away prefixes and 1st. opcode byte.  */
14341   codep = insn_codep + 1;
14342   oappend ("(bad)");
14343 }
14344
14345 static void
14346 REP_Fixup (int bytemode, int sizeflag)
14347 {
14348   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
14349      lods and stos.  */
14350   if (prefixes & PREFIX_REPZ)
14351     all_prefixes[last_repz_prefix] = REP_PREFIX;
14352
14353   switch (bytemode)
14354     {
14355     case al_reg:
14356     case eAX_reg:
14357     case indir_dx_reg:
14358       OP_IMREG (bytemode, sizeflag);
14359       break;
14360     case eDI_reg:
14361       OP_ESreg (bytemode, sizeflag);
14362       break;
14363     case eSI_reg:
14364       OP_DSreg (bytemode, sizeflag);
14365       break;
14366     default:
14367       abort ();
14368       break;
14369     }
14370 }
14371
14372 static void
14373 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
14374 {
14375   USED_REX (REX_W);
14376   if (rex & REX_W)
14377     {
14378       /* Change cmpxchg8b to cmpxchg16b.  */
14379       char *p = mnemonicendp - 2;
14380       mnemonicendp = stpcpy (p, "16b");
14381       bytemode = o_mode;
14382     }
14383   OP_M (bytemode, sizeflag);
14384 }
14385
14386 static void
14387 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
14388 {
14389   const char **names;
14390
14391   if (need_vex)
14392     {
14393       switch (vex.length)
14394         {
14395         case 128:
14396           names = names_xmm;
14397           break;
14398         case 256:
14399           names = names_ymm;
14400           break;
14401         default:
14402           abort ();
14403         }
14404     }
14405   else
14406     names = names_xmm;
14407   oappend (names[reg]);
14408 }
14409
14410 static void
14411 CRC32_Fixup (int bytemode, int sizeflag)
14412 {
14413   /* Add proper suffix to "crc32".  */
14414   char *p = mnemonicendp;
14415
14416   switch (bytemode)
14417     {
14418     case b_mode:
14419       if (intel_syntax)
14420         goto skip;
14421
14422       *p++ = 'b';
14423       break;
14424     case v_mode:
14425       if (intel_syntax)
14426         goto skip;
14427
14428       USED_REX (REX_W);
14429       if (rex & REX_W)
14430         *p++ = 'q';
14431       else
14432         {
14433           if (sizeflag & DFLAG)
14434             *p++ = 'l';
14435           else
14436             *p++ = 'w';
14437           used_prefixes |= (prefixes & PREFIX_DATA);
14438         }
14439       break;
14440     default:
14441       oappend (INTERNAL_DISASSEMBLER_ERROR);
14442       break;
14443     }
14444   mnemonicendp = p;
14445   *p = '\0';
14446
14447 skip:
14448   if (modrm.mod == 3)
14449     {
14450       int add;
14451
14452       /* Skip mod/rm byte.  */
14453       MODRM_CHECK;
14454       codep++;
14455
14456       USED_REX (REX_B);
14457       add = (rex & REX_B) ? 8 : 0;
14458       if (bytemode == b_mode)
14459         {
14460           USED_REX (0);
14461           if (rex)
14462             oappend (names8rex[modrm.rm + add]);
14463           else
14464             oappend (names8[modrm.rm + add]);
14465         }
14466       else
14467         {
14468           USED_REX (REX_W);
14469           if (rex & REX_W)
14470             oappend (names64[modrm.rm + add]);
14471           else if ((prefixes & PREFIX_DATA))
14472             oappend (names16[modrm.rm + add]);
14473           else
14474             oappend (names32[modrm.rm + add]);
14475         }
14476     }
14477   else
14478     OP_E (bytemode, sizeflag);
14479 }
14480
14481 static void
14482 FXSAVE_Fixup (int bytemode, int sizeflag)
14483 {
14484   /* Add proper suffix to "fxsave" and "fxrstor".  */
14485   USED_REX (REX_W);
14486   if (rex & REX_W)
14487     {
14488       char *p = mnemonicendp;
14489       *p++ = '6';
14490       *p++ = '4';
14491       *p = '\0';
14492       mnemonicendp = p;
14493     }
14494   OP_M (bytemode, sizeflag);
14495 }
14496
14497 /* Display the destination register operand for instructions with
14498    VEX. */
14499
14500 static void
14501 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
14502 {
14503   int reg;
14504   const char **names;
14505
14506   if (!need_vex)
14507     abort ();
14508
14509   if (!need_vex_reg)
14510     return;
14511
14512   reg = vex.register_specifier;
14513   if (bytemode == vex_scalar_mode)
14514     {
14515       oappend (names_xmm[reg]);
14516       return;
14517     }
14518
14519   switch (vex.length)
14520     {
14521     case 128:
14522       switch (bytemode)
14523         {
14524         case vex_mode:
14525         case vex128_mode:
14526           break;
14527         default:
14528           abort ();
14529           return;
14530         }
14531
14532       names = names_xmm;
14533       break;
14534     case 256:
14535       switch (bytemode)
14536         {
14537         case vex_mode:
14538         case vex256_mode:
14539           break;
14540         default:
14541           abort ();
14542           return;
14543         }
14544
14545       names = names_ymm;
14546       break;
14547     default:
14548       abort ();
14549       break;
14550     }
14551   oappend (names[reg]);
14552 }
14553
14554 /* Get the VEX immediate byte without moving codep.  */
14555
14556 static unsigned char
14557 get_vex_imm8 (int sizeflag, int opnum)
14558 {
14559   int bytes_before_imm = 0;
14560
14561   if (modrm.mod != 3)
14562     {
14563       /* There are SIB/displacement bytes.  */
14564       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14565         {
14566           /* 32/64 bit address mode */
14567           int base = modrm.rm;
14568
14569           /* Check SIB byte.  */
14570           if (base == 4)
14571             {
14572               FETCH_DATA (the_info, codep + 1);
14573               base = *codep & 7;
14574               /* When decoding the third source, don't increase
14575                  bytes_before_imm as this has already been incremented
14576                  by one in OP_E_memory while decoding the second
14577                  source operand.  */
14578               if (opnum == 0)
14579                 bytes_before_imm++;
14580             }
14581
14582           /* Don't increase bytes_before_imm when decoding the third source,
14583              it has already been incremented by OP_E_memory while decoding
14584              the second source operand.  */
14585           if (opnum == 0)
14586             {
14587               switch (modrm.mod)
14588                 {
14589                   case 0:
14590                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
14591                        SIB == 5, there is a 4 byte displacement.  */
14592                     if (base != 5)
14593                       /* No displacement. */
14594                       break;
14595                   case 2:
14596                     /* 4 byte displacement.  */
14597                     bytes_before_imm += 4;
14598                     break;
14599                   case 1:
14600                     /* 1 byte displacement.  */
14601                     bytes_before_imm++;
14602                     break;
14603                 }
14604             }
14605         }
14606       else
14607         {
14608           /* 16 bit address mode */
14609           /* Don't increase bytes_before_imm when decoding the third source,
14610              it has already been incremented by OP_E_memory while decoding
14611              the second source operand.  */
14612           if (opnum == 0)
14613             {
14614               switch (modrm.mod)
14615                 {
14616                 case 0:
14617                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
14618                   if (modrm.rm != 6)
14619                     /* No displacement. */
14620                     break;
14621                 case 2:
14622                   /* 2 byte displacement.  */
14623                   bytes_before_imm += 2;
14624                   break;
14625                 case 1:
14626                   /* 1 byte displacement: when decoding the third source,
14627                      don't increase bytes_before_imm as this has already
14628                      been incremented by one in OP_E_memory while decoding
14629                      the second source operand.  */
14630                   if (opnum == 0)
14631                     bytes_before_imm++;
14632
14633                   break;
14634                 }
14635             }
14636         }
14637     }
14638
14639   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
14640   return codep [bytes_before_imm];
14641 }
14642
14643 static void
14644 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
14645 {
14646   const char **names;
14647
14648   if (reg == -1 && modrm.mod != 3)
14649     {
14650       OP_E_memory (bytemode, sizeflag);
14651       return;
14652     }
14653   else
14654     {
14655       if (reg == -1)
14656         {
14657           reg = modrm.rm;
14658           USED_REX (REX_B);
14659           if (rex & REX_B)
14660             reg += 8;
14661         }
14662       else if (reg > 7 && address_mode != mode_64bit)
14663         BadOp ();
14664     }
14665
14666   switch (vex.length)
14667     {
14668     case 128:
14669       names = names_xmm;
14670       break;
14671     case 256:
14672       names = names_ymm;
14673       break;
14674     default:
14675       abort ();
14676     }
14677   oappend (names[reg]);
14678 }
14679
14680 static void
14681 OP_EX_VexImmW (int bytemode, int sizeflag)
14682 {
14683   int reg = -1;
14684   static unsigned char vex_imm8;
14685
14686   if (vex_w_done == 0)
14687     {
14688       vex_w_done = 1;
14689
14690       /* Skip mod/rm byte.  */
14691       MODRM_CHECK;
14692       codep++;
14693
14694       vex_imm8 = get_vex_imm8 (sizeflag, 0);
14695
14696       if (vex.w)
14697           reg = vex_imm8 >> 4;
14698
14699       OP_EX_VexReg (bytemode, sizeflag, reg);
14700     }
14701   else if (vex_w_done == 1)
14702     {
14703       vex_w_done = 2;
14704
14705       if (!vex.w)
14706           reg = vex_imm8 >> 4;
14707
14708       OP_EX_VexReg (bytemode, sizeflag, reg);
14709     }
14710   else
14711     {
14712       /* Output the imm8 directly.  */
14713       scratchbuf[0] = '$';
14714       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
14715       oappend (scratchbuf + intel_syntax);
14716       scratchbuf[0] = '\0';
14717       codep++;
14718     }
14719 }
14720
14721 static void
14722 OP_Vex_2src (int bytemode, int sizeflag)
14723 {
14724   if (modrm.mod == 3)
14725     {
14726       int reg = modrm.rm;
14727       USED_REX (REX_B);
14728       if (rex & REX_B)
14729         reg += 8;
14730       oappend (names_xmm[reg]);
14731     }
14732   else
14733     {
14734       if (intel_syntax
14735           && (bytemode == v_mode || bytemode == v_swap_mode))
14736         {
14737           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
14738           used_prefixes |= (prefixes & PREFIX_DATA);
14739         }
14740       OP_E (bytemode, sizeflag);
14741     }
14742 }
14743
14744 static void
14745 OP_Vex_2src_1 (int bytemode, int sizeflag)
14746 {
14747   if (modrm.mod == 3)
14748     {
14749       /* Skip mod/rm byte.   */
14750       MODRM_CHECK;
14751       codep++;
14752     }
14753
14754   if (vex.w)
14755     oappend (names_xmm[vex.register_specifier]);
14756   else
14757     OP_Vex_2src (bytemode, sizeflag);
14758 }
14759
14760 static void
14761 OP_Vex_2src_2 (int bytemode, int sizeflag)
14762 {
14763   if (vex.w)
14764     OP_Vex_2src (bytemode, sizeflag);
14765   else
14766     oappend (names_xmm[vex.register_specifier]);
14767 }
14768
14769 static void
14770 OP_EX_VexW (int bytemode, int sizeflag)
14771 {
14772   int reg = -1;
14773
14774   if (!vex_w_done)
14775     {
14776       vex_w_done = 1;
14777
14778       /* Skip mod/rm byte.  */
14779       MODRM_CHECK;
14780       codep++;
14781
14782       if (vex.w)
14783         reg = get_vex_imm8 (sizeflag, 0) >> 4;
14784     }
14785   else
14786     {
14787       if (!vex.w)
14788         reg = get_vex_imm8 (sizeflag, 1) >> 4;
14789     }
14790
14791   OP_EX_VexReg (bytemode, sizeflag, reg);
14792 }
14793
14794 static void
14795 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
14796              int sizeflag ATTRIBUTE_UNUSED)
14797 {
14798   /* Skip the immediate byte and check for invalid bits.  */
14799   FETCH_DATA (the_info, codep + 1);
14800   if (*codep++ & 0xf)
14801     BadOp ();
14802 }
14803
14804 static void
14805 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
14806 {
14807   int reg;
14808   const char **names;
14809
14810   FETCH_DATA (the_info, codep + 1);
14811   reg = *codep++;
14812
14813   if (bytemode != x_mode)
14814     abort ();
14815
14816   if (reg & 0xf)
14817       BadOp ();
14818
14819   reg >>= 4;
14820   if (reg > 7 && address_mode != mode_64bit)
14821     BadOp ();
14822
14823   switch (vex.length)
14824     {
14825     case 128:
14826       names = names_xmm;
14827       break;
14828     case 256:
14829       names = names_ymm;
14830       break;
14831     default:
14832       abort ();
14833     }
14834   oappend (names[reg]);
14835 }
14836
14837 static void
14838 OP_XMM_VexW (int bytemode, int sizeflag)
14839 {
14840   /* Turn off the REX.W bit since it is used for swapping operands
14841      now.  */
14842   rex &= ~REX_W;
14843   OP_XMM (bytemode, sizeflag);
14844 }
14845
14846 static void
14847 OP_EX_Vex (int bytemode, int sizeflag)
14848 {
14849   if (modrm.mod != 3)
14850     {
14851       if (vex.register_specifier != 0)
14852         BadOp ();
14853       need_vex_reg = 0;
14854     }
14855   OP_EX (bytemode, sizeflag);
14856 }
14857
14858 static void
14859 OP_XMM_Vex (int bytemode, int sizeflag)
14860 {
14861   if (modrm.mod != 3)
14862     {
14863       if (vex.register_specifier != 0)
14864         BadOp ();
14865       need_vex_reg = 0;
14866     }
14867   OP_XMM (bytemode, sizeflag);
14868 }
14869
14870 static void
14871 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14872 {
14873   switch (vex.length)
14874     {
14875     case 128:
14876       mnemonicendp = stpcpy (obuf, "vzeroupper");
14877       break;
14878     case 256:
14879       mnemonicendp = stpcpy (obuf, "vzeroall");
14880       break;
14881     default:
14882       abort ();
14883     }
14884 }
14885
14886 static struct op vex_cmp_op[] =
14887 {
14888   { STRING_COMMA_LEN ("eq") },
14889   { STRING_COMMA_LEN ("lt") },
14890   { STRING_COMMA_LEN ("le") },
14891   { STRING_COMMA_LEN ("unord") },
14892   { STRING_COMMA_LEN ("neq") },
14893   { STRING_COMMA_LEN ("nlt") },
14894   { STRING_COMMA_LEN ("nle") },
14895   { STRING_COMMA_LEN ("ord") },
14896   { STRING_COMMA_LEN ("eq_uq") },
14897   { STRING_COMMA_LEN ("nge") },
14898   { STRING_COMMA_LEN ("ngt") },
14899   { STRING_COMMA_LEN ("false") },
14900   { STRING_COMMA_LEN ("neq_oq") },
14901   { STRING_COMMA_LEN ("ge") },
14902   { STRING_COMMA_LEN ("gt") },
14903   { STRING_COMMA_LEN ("true") },
14904   { STRING_COMMA_LEN ("eq_os") },
14905   { STRING_COMMA_LEN ("lt_oq") },
14906   { STRING_COMMA_LEN ("le_oq") },
14907   { STRING_COMMA_LEN ("unord_s") },
14908   { STRING_COMMA_LEN ("neq_us") },
14909   { STRING_COMMA_LEN ("nlt_uq") },
14910   { STRING_COMMA_LEN ("nle_uq") },
14911   { STRING_COMMA_LEN ("ord_s") },
14912   { STRING_COMMA_LEN ("eq_us") },
14913   { STRING_COMMA_LEN ("nge_uq") },
14914   { STRING_COMMA_LEN ("ngt_uq") },
14915   { STRING_COMMA_LEN ("false_os") },
14916   { STRING_COMMA_LEN ("neq_os") },
14917   { STRING_COMMA_LEN ("ge_oq") },
14918   { STRING_COMMA_LEN ("gt_oq") },
14919   { STRING_COMMA_LEN ("true_us") },
14920 };
14921
14922 static void
14923 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14924 {
14925   unsigned int cmp_type;
14926
14927   FETCH_DATA (the_info, codep + 1);
14928   cmp_type = *codep++ & 0xff;
14929   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
14930     {
14931       char suffix [3];
14932       char *p = mnemonicendp - 2;
14933       suffix[0] = p[0];
14934       suffix[1] = p[1];
14935       suffix[2] = '\0';
14936       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
14937       mnemonicendp += vex_cmp_op[cmp_type].len;
14938     }
14939   else
14940     {
14941       /* We have a reserved extension byte.  Output it directly.  */
14942       scratchbuf[0] = '$';
14943       print_operand_value (scratchbuf + 1, 1, cmp_type);
14944       oappend (scratchbuf + intel_syntax);
14945       scratchbuf[0] = '\0';
14946     }
14947 }
14948
14949 static const struct op pclmul_op[] =
14950 {
14951   { STRING_COMMA_LEN ("lql") },
14952   { STRING_COMMA_LEN ("hql") },
14953   { STRING_COMMA_LEN ("lqh") },
14954   { STRING_COMMA_LEN ("hqh") }
14955 };
14956
14957 static void
14958 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
14959               int sizeflag ATTRIBUTE_UNUSED)
14960 {
14961   unsigned int pclmul_type;
14962
14963   FETCH_DATA (the_info, codep + 1);
14964   pclmul_type = *codep++ & 0xff;
14965   switch (pclmul_type)
14966     {
14967     case 0x10:
14968       pclmul_type = 2;
14969       break;
14970     case 0x11:
14971       pclmul_type = 3;
14972       break;
14973     default:
14974       break;
14975     }
14976   if (pclmul_type < ARRAY_SIZE (pclmul_op))
14977     {
14978       char suffix [4];
14979       char *p = mnemonicendp - 3;
14980       suffix[0] = p[0];
14981       suffix[1] = p[1];
14982       suffix[2] = p[2];
14983       suffix[3] = '\0';
14984       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
14985       mnemonicendp += pclmul_op[pclmul_type].len;
14986     }
14987   else
14988     {
14989       /* We have a reserved extension byte.  Output it directly.  */
14990       scratchbuf[0] = '$';
14991       print_operand_value (scratchbuf + 1, 1, pclmul_type);
14992       oappend (scratchbuf + intel_syntax);
14993       scratchbuf[0] = '\0';
14994     }
14995 }
14996
14997 static void
14998 MOVBE_Fixup (int bytemode, int sizeflag)
14999 {
15000   /* Add proper suffix to "movbe".  */
15001   char *p = mnemonicendp;
15002
15003   switch (bytemode)
15004     {
15005     case v_mode:
15006       if (intel_syntax)
15007         goto skip;
15008
15009       USED_REX (REX_W);
15010       if (sizeflag & SUFFIX_ALWAYS)
15011         {
15012           if (rex & REX_W)
15013             *p++ = 'q';
15014           else
15015             {
15016               if (sizeflag & DFLAG)
15017                 *p++ = 'l';
15018               else
15019                 *p++ = 'w';
15020               used_prefixes |= (prefixes & PREFIX_DATA);
15021             }
15022         }
15023       break;
15024     default:
15025       oappend (INTERNAL_DISASSEMBLER_ERROR);
15026       break;
15027     }
15028   mnemonicendp = p;
15029   *p = '\0';
15030
15031 skip:
15032   OP_M (bytemode, sizeflag);
15033 }
15034
15035 static void
15036 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15037 {
15038   int reg;
15039   const char **names;
15040
15041   /* Skip mod/rm byte.  */
15042   MODRM_CHECK;
15043   codep++;
15044
15045   if (vex.w)
15046     names = names64;
15047   else
15048     names = names32;
15049
15050   reg = modrm.rm;
15051   USED_REX (REX_B);
15052   if (rex & REX_B)
15053     reg += 8;
15054
15055   oappend (names[reg]);
15056 }
15057
15058 static void
15059 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15060 {
15061   const char **names;
15062
15063   if (vex.w)
15064     names = names64;
15065   else
15066     names = names32;
15067
15068   oappend (names[vex.register_specifier]);
15069 }
15070