opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
   3    2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
   4    Free Software Foundation, Inc.
   5
   6    This file is part of the GNU opcodes library.
   7
   8    This library is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3, or (at your option)
  11    any later version.
  12
  13    It is distributed in the hope that it will be useful, but WITHOUT
  14    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16    License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; if not, write to the Free Software
  20    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  21    MA 02110-1301, USA.  */
  22
  23
  24 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  25    July 1988
  26     modified by John Hassey (hassey@dg-rtp.dg.com)
  27     x86-64 support added by Jan Hubicka (jh@suse.cz)
  28     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  29
  30 /* The main tables describing the instructions is essentially a copy
  31    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  32    Programmers Manual.  Usually, there is a capital letter, followed
  33    by a small letter.  The capital letter tell the addressing mode,
  34    and the small letter tells about the operand size.  Refer to
  35    the Intel manual for details.  */
  36
  37 #include "sysdep.h"
  38 #include "dis-asm.h"
  39 #include "opintl.h"
  40 #include "opcode/i386.h"
  41 #include "libiberty.h"
  42
  43 #include <setjmp.h>
  44
  45 static int print_insn (bfd_vma, disassemble_info *);
  46 static void dofloat (int);
  47 static void OP_ST (int, int);
  48 static void OP_STi (int, int);
  49 static int putop (const char *, int);
  50 static void oappend (const char *);
  51 static void append_seg (void);
  52 static void OP_indirE (int, int);
  53 static void print_operand_value (char *, int, bfd_vma);
  54 static void OP_E_register (int, int);
  55 static void OP_E_memory (int, int);
  56 static void print_displacement (char *, bfd_vma);
  57 static void OP_E (int, int);
  58 static void OP_G (int, int);
  59 static bfd_vma get64 (void);
  60 static bfd_signed_vma get32 (void);
  61 static bfd_signed_vma get32s (void);
  62 static int get16 (void);
  63 static void set_op (bfd_vma, int);
  64 static void OP_Skip_MODRM (int, int);
  65 static void OP_REG (int, int);
  66 static void OP_IMREG (int, int);
  67 static void OP_I (int, int);
  68 static void OP_I64 (int, int);
  69 static void OP_sI (int, int);
  70 static void OP_J (int, int);
  71 static void OP_SEG (int, int);
  72 static void OP_DIR (int, int);
  73 static void OP_OFF (int, int);
  74 static void OP_OFF64 (int, int);
  75 static void ptr_reg (int, int);
  76 static void OP_ESreg (int, int);
  77 static void OP_DSreg (int, int);
  78 static void OP_C (int, int);
  79 static void OP_D (int, int);
  80 static void OP_T (int, int);
  81 static void OP_R (int, int);
  82 static void OP_MMX (int, int);
  83 static void OP_XMM (int, int);
  84 static void OP_EM (int, int);
  85 static void OP_EX (int, int);
  86 static void OP_EMC (int,int);
  87 static void OP_MXC (int,int);
  88 static void OP_MS (int, int);
  89 static void OP_XS (int, int);
  90 static void OP_M (int, int);
  91 static void OP_VEX (int, int);
  92 static void OP_EX_Vex (int, int);
  93 static void OP_EX_VexW (int, int);
  94 static void OP_EX_VexImmW (int, int);
  95 static void OP_XMM_Vex (int, int);
  96 static void OP_XMM_VexW (int, int);
  97 static void OP_REG_VexI4 (int, int);
  98 static void PCLMUL_Fixup (int, int);
  99 static void VEXI4_Fixup (int, int);
 100 static void VZERO_Fixup (int, int);
 101 static void VCMP_Fixup (int, int);
 102 static void OP_0f07 (int, int);
 103 static void OP_Monitor (int, int);
 104 static void OP_Mwait (int, int);
 105 static void NOP_Fixup1 (int, int);
 106 static void NOP_Fixup2 (int, int);
 107 static void OP_3DNowSuffix (int, int);
 108 static void CMP_Fixup (int, int);
 109 static void BadOp (void);
 110 static void REP_Fixup (int, int);
 111 static void HLE_Fixup1 (int, int);
 112 static void HLE_Fixup2 (int, int);
 113 static void HLE_Fixup3 (int, int);
 114 static void CMPXCHG8B_Fixup (int, int);
 115 static void XMM_Fixup (int, int);
 116 static void CRC32_Fixup (int, int);
 117 static void FXSAVE_Fixup (int, int);
 118 static void OP_LWPCB_E (int, int);
 119 static void OP_LWP_E (int, int);
 120 static void OP_Vex_2src_1 (int, int);
 121 static void OP_Vex_2src_2 (int, int);
 122
 123 static void MOVBE_Fixup (int, int);
 124
 125 struct dis_private {
 126   /* Points to first byte not fetched.  */
 127   bfd_byte *max_fetched;
 128   bfd_byte the_buffer[MAX_MNEM_SIZE];
 129   bfd_vma insn_start;
 130   int orig_sizeflag;
 131   jmp_buf bailout;
 132 };
 133
 134 enum address_mode
 135 {
 136   mode_16bit,
 137   mode_32bit,
 138   mode_64bit
 139 };
 140
 141 enum address_mode address_mode;
 142
 143 /* Flags for the prefixes for the current instruction.  See below.  */
 144 static int prefixes;
 145
 146 /* REX prefix the current instruction.  See below.  */
 147 static int rex;
 148 /* Bits of REX we've already used.  */
 149 static int rex_used;
 150 /* REX bits in original REX prefix ignored.  */
 151 static int rex_ignored;
 152 /* Mark parts used in the REX prefix.  When we are testing for
 153    empty prefix (for 8bit register REX extension), just mask it
 154    out.  Otherwise test for REX bit is excuse for existence of REX
 155    only in case value is nonzero.  */
 156 #define USED_REX(value)                                 \
 157   {                                                     \
 158     if (value)                                          \
 159       {                                                 \
 160         if ((rex & value))                              \
 161           rex_used |= (value) | REX_OPCODE;             \
 162       }                                                 \
 163     else                                                \
 164       rex_used |= REX_OPCODE;                           \
 165   }
 166
 167 /* Flags for prefixes which we somehow handled when printing the
 168    current instruction.  */
 169 static int used_prefixes;
 170
 171 /* Flags stored in PREFIXES.  */
 172 #define PREFIX_REPZ 1
 173 #define PREFIX_REPNZ 2
 174 #define PREFIX_LOCK 4
 175 #define PREFIX_CS 8
 176 #define PREFIX_SS 0x10
 177 #define PREFIX_DS 0x20
 178 #define PREFIX_ES 0x40
 179 #define PREFIX_FS 0x80
 180 #define PREFIX_GS 0x100
 181 #define PREFIX_DATA 0x200
 182 #define PREFIX_ADDR 0x400
 183 #define PREFIX_FWAIT 0x800
 184
 185 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 186    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 187    on error.  */
 188 #define FETCH_DATA(info, addr) \
 189   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 190    ? 1 : fetch_data ((info), (addr)))
 191
 192 static int
 193 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 194 {
 195   int status;
 196   struct dis_private *priv = (struct dis_private *) info->private_data;
 197   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 198
 199   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 200     status = (*info->read_memory_func) (start,
 201                                         priv->max_fetched,
 202                                         addr - priv->max_fetched,
 203                                         info);
 204   else
 205     status = -1;
 206   if (status != 0)
 207     {
 208       /* If we did manage to read at least one byte, then
 209          print_insn_i386 will do something sensible.  Otherwise, print
 210          an error.  We do that here because this is where we know
 211          STATUS.  */
 212       if (priv->max_fetched == priv->the_buffer)
 213         (*info->memory_error_func) (status, start, info);
 214       longjmp (priv->bailout, 1);
 215     }
 216   else
 217     priv->max_fetched = addr;
 218   return 1;
 219 }
 220
 221 #define XX { NULL, 0 }
 222 #define Bad_Opcode NULL, { { NULL, 0 } }
 223
 224 #define Eb { OP_E, b_mode }
 225 #define EbS { OP_E, b_swap_mode }
 226 #define Ev { OP_E, v_mode }
 227 #define EvS { OP_E, v_swap_mode }
 228 #define Ed { OP_E, d_mode }
 229 #define Edq { OP_E, dq_mode }
 230 #define Edqw { OP_E, dqw_mode }
 231 #define Edqb { OP_E, dqb_mode }
 232 #define Edqd { OP_E, dqd_mode }
 233 #define Eq { OP_E, q_mode }
 234 #define indirEv { OP_indirE, stack_v_mode }
 235 #define indirEp { OP_indirE, f_mode }
 236 #define stackEv { OP_E, stack_v_mode }
 237 #define Em { OP_E, m_mode }
 238 #define Ew { OP_E, w_mode }
 239 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 240 #define Ma { OP_M, a_mode }
 241 #define Mb { OP_M, b_mode }
 242 #define Md { OP_M, d_mode }
 243 #define Mo { OP_M, o_mode }
 244 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 245 #define Mq { OP_M, q_mode }
 246 #define Mx { OP_M, x_mode }
 247 #define Mxmm { OP_M, xmm_mode }
 248 #define Gb { OP_G, b_mode }
 249 #define Gv { OP_G, v_mode }
 250 #define Gd { OP_G, d_mode }
 251 #define Gdq { OP_G, dq_mode }
 252 #define Gm { OP_G, m_mode }
 253 #define Gw { OP_G, w_mode }
 254 #define Rd { OP_R, d_mode }
 255 #define Rm { OP_R, m_mode }
 256 #define Ib { OP_I, b_mode }
 257 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 258 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 259 #define Iv { OP_I, v_mode }
 260 #define sIv { OP_sI, v_mode }
 261 #define Iq { OP_I, q_mode }
 262 #define Iv64 { OP_I64, v_mode }
 263 #define Iw { OP_I, w_mode }
 264 #define I1 { OP_I, const_1_mode }
 265 #define Jb { OP_J, b_mode }
 266 #define Jv { OP_J, v_mode }
 267 #define Cm { OP_C, m_mode }
 268 #define Dm { OP_D, m_mode }
 269 #define Td { OP_T, d_mode }
 270 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 271
 272 #define RMeAX { OP_REG, eAX_reg }
 273 #define RMeBX { OP_REG, eBX_reg }
 274 #define RMeCX { OP_REG, eCX_reg }
 275 #define RMeDX { OP_REG, eDX_reg }
 276 #define RMeSP { OP_REG, eSP_reg }
 277 #define RMeBP { OP_REG, eBP_reg }
 278 #define RMeSI { OP_REG, eSI_reg }
 279 #define RMeDI { OP_REG, eDI_reg }
 280 #define RMrAX { OP_REG, rAX_reg }
 281 #define RMrBX { OP_REG, rBX_reg }
 282 #define RMrCX { OP_REG, rCX_reg }
 283 #define RMrDX { OP_REG, rDX_reg }
 284 #define RMrSP { OP_REG, rSP_reg }
 285 #define RMrBP { OP_REG, rBP_reg }
 286 #define RMrSI { OP_REG, rSI_reg }
 287 #define RMrDI { OP_REG, rDI_reg }
 288 #define RMAL { OP_REG, al_reg }
 289 #define RMCL { OP_REG, cl_reg }
 290 #define RMDL { OP_REG, dl_reg }
 291 #define RMBL { OP_REG, bl_reg }
 292 #define RMAH { OP_REG, ah_reg }
 293 #define RMCH { OP_REG, ch_reg }
 294 #define RMDH { OP_REG, dh_reg }
 295 #define RMBH { OP_REG, bh_reg }
 296 #define RMAX { OP_REG, ax_reg }
 297 #define RMDX { OP_REG, dx_reg }
 298
 299 #define eAX { OP_IMREG, eAX_reg }
 300 #define eBX { OP_IMREG, eBX_reg }
 301 #define eCX { OP_IMREG, eCX_reg }
 302 #define eDX { OP_IMREG, eDX_reg }
 303 #define eSP { OP_IMREG, eSP_reg }
 304 #define eBP { OP_IMREG, eBP_reg }
 305 #define eSI { OP_IMREG, eSI_reg }
 306 #define eDI { OP_IMREG, eDI_reg }
 307 #define AL { OP_IMREG, al_reg }
 308 #define CL { OP_IMREG, cl_reg }
 309 #define DL { OP_IMREG, dl_reg }
 310 #define BL { OP_IMREG, bl_reg }
 311 #define AH { OP_IMREG, ah_reg }
 312 #define CH { OP_IMREG, ch_reg }
 313 #define DH { OP_IMREG, dh_reg }
 314 #define BH { OP_IMREG, bh_reg }
 315 #define AX { OP_IMREG, ax_reg }
 316 #define DX { OP_IMREG, dx_reg }
 317 #define zAX { OP_IMREG, z_mode_ax_reg }
 318 #define indirDX { OP_IMREG, indir_dx_reg }
 319
 320 #define Sw { OP_SEG, w_mode }
 321 #define Sv { OP_SEG, v_mode }
 322 #define Ap { OP_DIR, 0 }
 323 #define Ob { OP_OFF64, b_mode }
 324 #define Ov { OP_OFF64, v_mode }
 325 #define Xb { OP_DSreg, eSI_reg }
 326 #define Xv { OP_DSreg, eSI_reg }
 327 #define Xz { OP_DSreg, eSI_reg }
 328 #define Yb { OP_ESreg, eDI_reg }
 329 #define Yv { OP_ESreg, eDI_reg }
 330 #define DSBX { OP_DSreg, eBX_reg }
 331
 332 #define es { OP_REG, es_reg }
 333 #define ss { OP_REG, ss_reg }
 334 #define cs { OP_REG, cs_reg }
 335 #define ds { OP_REG, ds_reg }
 336 #define fs { OP_REG, fs_reg }
 337 #define gs { OP_REG, gs_reg }
 338
 339 #define MX { OP_MMX, 0 }
 340 #define XM { OP_XMM, 0 }
 341 #define XMScalar { OP_XMM, scalar_mode }
 342 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 343 #define XMM { OP_XMM, xmm_mode }
 344 #define EM { OP_EM, v_mode }
 345 #define EMS { OP_EM, v_swap_mode }
 346 #define EMd { OP_EM, d_mode }
 347 #define EMx { OP_EM, x_mode }
 348 #define EXw { OP_EX, w_mode }
 349 #define EXd { OP_EX, d_mode }
 350 #define EXdScalar { OP_EX, d_scalar_mode }
 351 #define EXdS { OP_EX, d_swap_mode }
 352 #define EXq { OP_EX, q_mode }
 353 #define EXqScalar { OP_EX, q_scalar_mode }
 354 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 355 #define EXqS { OP_EX, q_swap_mode }
 356 #define EXx { OP_EX, x_mode }
 357 #define EXxS { OP_EX, x_swap_mode }
 358 #define EXxmm { OP_EX, xmm_mode }
 359 #define EXxmmq { OP_EX, xmmq_mode }
 360 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 361 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 362 #define EXxmm_md { OP_EX, xmm_md_mode }
 363 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 364 #define EXxmmdw { OP_EX, xmmdw_mode }
 365 #define EXxmmqd { OP_EX, xmmqd_mode }
 366 #define EXymmq { OP_EX, ymmq_mode }
 367 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 368 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 369 #define MS { OP_MS, v_mode }
 370 #define XS { OP_XS, v_mode }
 371 #define EMCq { OP_EMC, q_mode }
 372 #define MXC { OP_MXC, 0 }
 373 #define OPSUF { OP_3DNowSuffix, 0 }
 374 #define CMP { CMP_Fixup, 0 }
 375 #define XMM0 { XMM_Fixup, 0 }
 376 #define FXSAVE { FXSAVE_Fixup, 0 }
 377 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 378 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 379
 380 #define Vex { OP_VEX, vex_mode }
 381 #define VexScalar { OP_VEX, vex_scalar_mode }
 382 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 383 #define Vex128 { OP_VEX, vex128_mode }
 384 #define Vex256 { OP_VEX, vex256_mode }
 385 #define VexGdq { OP_VEX, dq_mode }
 386 #define VexI4 { VEXI4_Fixup, 0}
 387 #define EXdVex { OP_EX_Vex, d_mode }
 388 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 389 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 390 #define EXqVex { OP_EX_Vex, q_mode }
 391 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 392 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 393 #define EXVexW { OP_EX_VexW, x_mode }
 394 #define EXdVexW { OP_EX_VexW, d_mode }
 395 #define EXqVexW { OP_EX_VexW, q_mode }
 396 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 397 #define XMVex { OP_XMM_Vex, 0 }
 398 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 399 #define XMVexW { OP_XMM_VexW, 0 }
 400 #define XMVexI4 { OP_REG_VexI4, x_mode }
 401 #define PCLMUL { PCLMUL_Fixup, 0 }
 402 #define VZERO { VZERO_Fixup, 0 }
 403 #define VCMP { VCMP_Fixup, 0 }
 404
 405 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 406 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 407
 408 /* Used handle "rep" prefix for string instructions.  */
 409 #define Xbr { REP_Fixup, eSI_reg }
 410 #define Xvr { REP_Fixup, eSI_reg }
 411 #define Ybr { REP_Fixup, eDI_reg }
 412 #define Yvr { REP_Fixup, eDI_reg }
 413 #define Yzr { REP_Fixup, eDI_reg }
 414 #define indirDXr { REP_Fixup, indir_dx_reg }
 415 #define ALr { REP_Fixup, al_reg }
 416 #define eAXr { REP_Fixup, eAX_reg }
 417
 418 /* Used handle HLE prefix for lockable instructions.  */
 419 #define Ebh1 { HLE_Fixup1, b_mode }
 420 #define Evh1 { HLE_Fixup1, v_mode }
 421 #define Ebh2 { HLE_Fixup2, b_mode }
 422 #define Evh2 { HLE_Fixup2, v_mode }
 423 #define Ebh3 { HLE_Fixup3, b_mode }
 424 #define Evh3 { HLE_Fixup3, v_mode }
 425
 426 #define cond_jump_flag { NULL, cond_jump_mode }
 427 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 428
 429 /* bits in sizeflag */
 430 #define SUFFIX_ALWAYS 4
 431 #define AFLAG 2
 432 #define DFLAG 1
 433
 434 enum
 435 {
 436   /* byte operand */
 437   b_mode = 1,
 438   /* byte operand with operand swapped */
 439   b_swap_mode,
 440   /* byte operand, sign extend like 'T' suffix */
 441   b_T_mode,
 442   /* operand size depends on prefixes */
 443   v_mode,
 444   /* operand size depends on prefixes with operand swapped */
 445   v_swap_mode,
 446   /* word operand */
 447   w_mode,
 448   /* double word operand  */
 449   d_mode,
 450   /* double word operand with operand swapped */
 451   d_swap_mode,
 452   /* quad word operand */
 453   q_mode,
 454   /* quad word operand with operand swapped */
 455   q_swap_mode,
 456   /* ten-byte operand */
 457   t_mode,
 458   /* 16-byte XMM or 32-byte YMM operand */
 459   x_mode,
 460   /* 16-byte XMM or 32-byte YMM operand with operand swapped */
 461   x_swap_mode,
 462   /* 16-byte XMM operand */
 463   xmm_mode,
 464   /* 16-byte XMM or quad word operand */
 465   xmmq_mode,
 466   /* XMM register or byte memory operand */
 467   xmm_mb_mode,
 468   /* XMM register or word memory operand */
 469   xmm_mw_mode,
 470   /* XMM register or double word memory operand */
 471   xmm_md_mode,
 472   /* XMM register or quad word memory operand */
 473   xmm_mq_mode,
 474   /* 16-byte XMM, word or double word operand  */
 475   xmmdw_mode,
 476   /* 16-byte XMM, double word or quad word operand */
 477   xmmqd_mode,
 478   /* 32-byte YMM or quad word operand */
 479   ymmq_mode,
 480   /* 32-byte YMM or 16-byte word operand */
 481   ymmxmm_mode,
 482   /* d_mode in 32bit, q_mode in 64bit mode.  */
 483   m_mode,
 484   /* pair of v_mode operands */
 485   a_mode,
 486   cond_jump_mode,
 487   loop_jcxz_mode,
 488   /* operand size depends on REX prefixes.  */
 489   dq_mode,
 490   /* registers like dq_mode, memory like w_mode.  */
 491   dqw_mode,
 492   /* 4- or 6-byte pointer operand */
 493   f_mode,
 494   const_1_mode,
 495   /* v_mode for stack-related opcodes.  */
 496   stack_v_mode,
 497   /* non-quad operand size depends on prefixes */
 498   z_mode,
 499   /* 16-byte operand */
 500   o_mode,
 501   /* registers like dq_mode, memory like b_mode.  */
 502   dqb_mode,
 503   /* registers like dq_mode, memory like d_mode.  */
 504   dqd_mode,
 505   /* normal vex mode */
 506   vex_mode,
 507   /* 128bit vex mode */
 508   vex128_mode,
 509   /* 256bit vex mode */
 510   vex256_mode,
 511   /* operand size depends on the VEX.W bit.  */
 512   vex_w_dq_mode,
 513
 514   /* Similar to vex_w_dq_mode, with VSIB dword indices.  */
 515   vex_vsib_d_w_dq_mode,
 516   /* Similar to vex_w_dq_mode, with VSIB qword indices.  */
 517   vex_vsib_q_w_dq_mode,
 518
 519   /* scalar, ignore vector length.  */
 520   scalar_mode,
 521   /* like d_mode, ignore vector length.  */
 522   d_scalar_mode,
 523   /* like d_swap_mode, ignore vector length.  */
 524   d_scalar_swap_mode,
 525   /* like q_mode, ignore vector length.  */
 526   q_scalar_mode,
 527   /* like q_swap_mode, ignore vector length.  */
 528   q_scalar_swap_mode,
 529   /* like vex_mode, ignore vector length.  */
 530   vex_scalar_mode,
 531   /* like vex_w_dq_mode, ignore vector length.  */
 532   vex_scalar_w_dq_mode,
 533
 534   es_reg,
 535   cs_reg,
 536   ss_reg,
 537   ds_reg,
 538   fs_reg,
 539   gs_reg,
 540
 541   eAX_reg,
 542   eCX_reg,
 543   eDX_reg,
 544   eBX_reg,
 545   eSP_reg,
 546   eBP_reg,
 547   eSI_reg,
 548   eDI_reg,
 549
 550   al_reg,
 551   cl_reg,
 552   dl_reg,
 553   bl_reg,
 554   ah_reg,
 555   ch_reg,
 556   dh_reg,
 557   bh_reg,
 558
 559   ax_reg,
 560   cx_reg,
 561   dx_reg,
 562   bx_reg,
 563   sp_reg,
 564   bp_reg,
 565   si_reg,
 566   di_reg,
 567
 568   rAX_reg,
 569   rCX_reg,
 570   rDX_reg,
 571   rBX_reg,
 572   rSP_reg,
 573   rBP_reg,
 574   rSI_reg,
 575   rDI_reg,
 576
 577   z_mode_ax_reg,
 578   indir_dx_reg
 579 };
 580
 581 enum
 582 {
 583   FLOATCODE = 1,
 584   USE_REG_TABLE,
 585   USE_MOD_TABLE,
 586   USE_RM_TABLE,
 587   USE_PREFIX_TABLE,
 588   USE_X86_64_TABLE,
 589   USE_3BYTE_TABLE,
 590   USE_XOP_8F_TABLE,
 591   USE_VEX_C4_TABLE,
 592   USE_VEX_C5_TABLE,
 593   USE_VEX_LEN_TABLE,
 594   USE_VEX_W_TABLE
 595 };
 596
 597 #define FLOAT                   NULL, { { NULL, FLOATCODE } }
 598
 599 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }
 600 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 601 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 602 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 603 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 604 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 605 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 606 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 607 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 608 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 609 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 610 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 611
 612 enum
 613 {
 614   REG_80 = 0,
 615   REG_81,
 616   REG_82,
 617   REG_8F,
 618   REG_C0,
 619   REG_C1,
 620   REG_C6,
 621   REG_C7,
 622   REG_D0,
 623   REG_D1,
 624   REG_D2,
 625   REG_D3,
 626   REG_F6,
 627   REG_F7,
 628   REG_FE,
 629   REG_FF,
 630   REG_0F00,
 631   REG_0F01,
 632   REG_0F0D,
 633   REG_0F18,
 634   REG_0F71,
 635   REG_0F72,
 636   REG_0F73,
 637   REG_0FA6,
 638   REG_0FA7,
 639   REG_0FAE,
 640   REG_0FBA,
 641   REG_0FC7,
 642   REG_VEX_0F71,
 643   REG_VEX_0F72,
 644   REG_VEX_0F73,
 645   REG_VEX_0FAE,
 646   REG_VEX_0F38F3,
 647   REG_XOP_LWPCB,
 648   REG_XOP_LWP,
 649   REG_XOP_TBM_01,
 650   REG_XOP_TBM_02
 651 };
 652
 653 enum
 654 {
 655   MOD_8D = 0,
 656   MOD_C6_REG_7,
 657   MOD_C7_REG_7,
 658   MOD_0F01_REG_0,
 659   MOD_0F01_REG_1,
 660   MOD_0F01_REG_2,
 661   MOD_0F01_REG_3,
 662   MOD_0F01_REG_7,
 663   MOD_0F12_PREFIX_0,
 664   MOD_0F13,
 665   MOD_0F16_PREFIX_0,
 666   MOD_0F17,
 667   MOD_0F18_REG_0,
 668   MOD_0F18_REG_1,
 669   MOD_0F18_REG_2,
 670   MOD_0F18_REG_3,
 671   MOD_0F18_REG_4,
 672   MOD_0F18_REG_5,
 673   MOD_0F18_REG_6,
 674   MOD_0F18_REG_7,
 675   MOD_0F20,
 676   MOD_0F21,
 677   MOD_0F22,
 678   MOD_0F23,
 679   MOD_0F24,
 680   MOD_0F26,
 681   MOD_0F2B_PREFIX_0,
 682   MOD_0F2B_PREFIX_1,
 683   MOD_0F2B_PREFIX_2,
 684   MOD_0F2B_PREFIX_3,
 685   MOD_0F51,
 686   MOD_0F71_REG_2,
 687   MOD_0F71_REG_4,
 688   MOD_0F71_REG_6,
 689   MOD_0F72_REG_2,
 690   MOD_0F72_REG_4,
 691   MOD_0F72_REG_6,
 692   MOD_0F73_REG_2,
 693   MOD_0F73_REG_3,
 694   MOD_0F73_REG_6,
 695   MOD_0F73_REG_7,
 696   MOD_0FAE_REG_0,
 697   MOD_0FAE_REG_1,
 698   MOD_0FAE_REG_2,
 699   MOD_0FAE_REG_3,
 700   MOD_0FAE_REG_4,
 701   MOD_0FAE_REG_5,
 702   MOD_0FAE_REG_6,
 703   MOD_0FAE_REG_7,
 704   MOD_0FB2,
 705   MOD_0FB4,
 706   MOD_0FB5,
 707   MOD_0FC7_REG_6,
 708   MOD_0FC7_REG_7,
 709   MOD_0FD7,
 710   MOD_0FE7_PREFIX_2,
 711   MOD_0FF0_PREFIX_3,
 712   MOD_0F382A_PREFIX_2,
 713   MOD_62_32BIT,
 714   MOD_C4_32BIT,
 715   MOD_C5_32BIT,
 716   MOD_VEX_0F12_PREFIX_0,
 717   MOD_VEX_0F13,
 718   MOD_VEX_0F16_PREFIX_0,
 719   MOD_VEX_0F17,
 720   MOD_VEX_0F2B,
 721   MOD_VEX_0F50,
 722   MOD_VEX_0F71_REG_2,
 723   MOD_VEX_0F71_REG_4,
 724   MOD_VEX_0F71_REG_6,
 725   MOD_VEX_0F72_REG_2,
 726   MOD_VEX_0F72_REG_4,
 727   MOD_VEX_0F72_REG_6,
 728   MOD_VEX_0F73_REG_2,
 729   MOD_VEX_0F73_REG_3,
 730   MOD_VEX_0F73_REG_6,
 731   MOD_VEX_0F73_REG_7,
 732   MOD_VEX_0FAE_REG_2,
 733   MOD_VEX_0FAE_REG_3,
 734   MOD_VEX_0FD7_PREFIX_2,
 735   MOD_VEX_0FE7_PREFIX_2,
 736   MOD_VEX_0FF0_PREFIX_3,
 737   MOD_VEX_0F381A_PREFIX_2,
 738   MOD_VEX_0F382A_PREFIX_2,
 739   MOD_VEX_0F382C_PREFIX_2,
 740   MOD_VEX_0F382D_PREFIX_2,
 741   MOD_VEX_0F382E_PREFIX_2,
 742   MOD_VEX_0F382F_PREFIX_2,
 743   MOD_VEX_0F385A_PREFIX_2,
 744   MOD_VEX_0F388C_PREFIX_2,
 745   MOD_VEX_0F388E_PREFIX_2,
 746 };
 747
 748 enum
 749 {
 750   RM_C6_REG_7 = 0,
 751   RM_C7_REG_7,
 752   RM_0F01_REG_0,
 753   RM_0F01_REG_1,
 754   RM_0F01_REG_2,
 755   RM_0F01_REG_3,
 756   RM_0F01_REG_7,
 757   RM_0FAE_REG_5,
 758   RM_0FAE_REG_6,
 759   RM_0FAE_REG_7
 760 };
 761
 762 enum
 763 {
 764   PREFIX_90 = 0,
 765   PREFIX_0F10,
 766   PREFIX_0F11,
 767   PREFIX_0F12,
 768   PREFIX_0F16,
 769   PREFIX_0F2A,
 770   PREFIX_0F2B,
 771   PREFIX_0F2C,
 772   PREFIX_0F2D,
 773   PREFIX_0F2E,
 774   PREFIX_0F2F,
 775   PREFIX_0F51,
 776   PREFIX_0F52,
 777   PREFIX_0F53,
 778   PREFIX_0F58,
 779   PREFIX_0F59,
 780   PREFIX_0F5A,
 781   PREFIX_0F5B,
 782   PREFIX_0F5C,
 783   PREFIX_0F5D,
 784   PREFIX_0F5E,
 785   PREFIX_0F5F,
 786   PREFIX_0F60,
 787   PREFIX_0F61,
 788   PREFIX_0F62,
 789   PREFIX_0F6C,
 790   PREFIX_0F6D,
 791   PREFIX_0F6F,
 792   PREFIX_0F70,
 793   PREFIX_0F73_REG_3,
 794   PREFIX_0F73_REG_7,
 795   PREFIX_0F78,
 796   PREFIX_0F79,
 797   PREFIX_0F7C,
 798   PREFIX_0F7D,
 799   PREFIX_0F7E,
 800   PREFIX_0F7F,
 801   PREFIX_0FAE_REG_0,
 802   PREFIX_0FAE_REG_1,
 803   PREFIX_0FAE_REG_2,
 804   PREFIX_0FAE_REG_3,
 805   PREFIX_0FB8,
 806   PREFIX_0FBC,
 807   PREFIX_0FBD,
 808   PREFIX_0FC2,
 809   PREFIX_0FC3,
 810   PREFIX_0FC7_REG_6,
 811   PREFIX_0FD0,
 812   PREFIX_0FD6,
 813   PREFIX_0FE6,
 814   PREFIX_0FE7,
 815   PREFIX_0FF0,
 816   PREFIX_0FF7,
 817   PREFIX_0F3810,
 818   PREFIX_0F3814,
 819   PREFIX_0F3815,
 820   PREFIX_0F3817,
 821   PREFIX_0F3820,
 822   PREFIX_0F3821,
 823   PREFIX_0F3822,
 824   PREFIX_0F3823,
 825   PREFIX_0F3824,
 826   PREFIX_0F3825,
 827   PREFIX_0F3828,
 828   PREFIX_0F3829,
 829   PREFIX_0F382A,
 830   PREFIX_0F382B,
 831   PREFIX_0F3830,
 832   PREFIX_0F3831,
 833   PREFIX_0F3832,
 834   PREFIX_0F3833,
 835   PREFIX_0F3834,
 836   PREFIX_0F3835,
 837   PREFIX_0F3837,
 838   PREFIX_0F3838,
 839   PREFIX_0F3839,
 840   PREFIX_0F383A,
 841   PREFIX_0F383B,
 842   PREFIX_0F383C,
 843   PREFIX_0F383D,
 844   PREFIX_0F383E,
 845   PREFIX_0F383F,
 846   PREFIX_0F3840,
 847   PREFIX_0F3841,
 848   PREFIX_0F3880,
 849   PREFIX_0F3881,
 850   PREFIX_0F3882,
 851   PREFIX_0F38DB,
 852   PREFIX_0F38DC,
 853   PREFIX_0F38DD,
 854   PREFIX_0F38DE,
 855   PREFIX_0F38DF,
 856   PREFIX_0F38F0,
 857   PREFIX_0F38F1,
 858   PREFIX_0F38F6,
 859   PREFIX_0F3A08,
 860   PREFIX_0F3A09,
 861   PREFIX_0F3A0A,
 862   PREFIX_0F3A0B,
 863   PREFIX_0F3A0C,
 864   PREFIX_0F3A0D,
 865   PREFIX_0F3A0E,
 866   PREFIX_0F3A14,
 867   PREFIX_0F3A15,
 868   PREFIX_0F3A16,
 869   PREFIX_0F3A17,
 870   PREFIX_0F3A20,
 871   PREFIX_0F3A21,
 872   PREFIX_0F3A22,
 873   PREFIX_0F3A40,
 874   PREFIX_0F3A41,
 875   PREFIX_0F3A42,
 876   PREFIX_0F3A44,
 877   PREFIX_0F3A60,
 878   PREFIX_0F3A61,
 879   PREFIX_0F3A62,
 880   PREFIX_0F3A63,
 881   PREFIX_0F3ADF,
 882   PREFIX_VEX_0F10,
 883   PREFIX_VEX_0F11,
 884   PREFIX_VEX_0F12,
 885   PREFIX_VEX_0F16,
 886   PREFIX_VEX_0F2A,
 887   PREFIX_VEX_0F2C,
 888   PREFIX_VEX_0F2D,
 889   PREFIX_VEX_0F2E,
 890   PREFIX_VEX_0F2F,
 891   PREFIX_VEX_0F51,
 892   PREFIX_VEX_0F52,
 893   PREFIX_VEX_0F53,
 894   PREFIX_VEX_0F58,
 895   PREFIX_VEX_0F59,
 896   PREFIX_VEX_0F5A,
 897   PREFIX_VEX_0F5B,
 898   PREFIX_VEX_0F5C,
 899   PREFIX_VEX_0F5D,
 900   PREFIX_VEX_0F5E,
 901   PREFIX_VEX_0F5F,
 902   PREFIX_VEX_0F60,
 903   PREFIX_VEX_0F61,
 904   PREFIX_VEX_0F62,
 905   PREFIX_VEX_0F63,
 906   PREFIX_VEX_0F64,
 907   PREFIX_VEX_0F65,
 908   PREFIX_VEX_0F66,
 909   PREFIX_VEX_0F67,
 910   PREFIX_VEX_0F68,
 911   PREFIX_VEX_0F69,
 912   PREFIX_VEX_0F6A,
 913   PREFIX_VEX_0F6B,
 914   PREFIX_VEX_0F6C,
 915   PREFIX_VEX_0F6D,
 916   PREFIX_VEX_0F6E,
 917   PREFIX_VEX_0F6F,
 918   PREFIX_VEX_0F70,
 919   PREFIX_VEX_0F71_REG_2,
 920   PREFIX_VEX_0F71_REG_4,
 921   PREFIX_VEX_0F71_REG_6,
 922   PREFIX_VEX_0F72_REG_2,
 923   PREFIX_VEX_0F72_REG_4,
 924   PREFIX_VEX_0F72_REG_6,
 925   PREFIX_VEX_0F73_REG_2,
 926   PREFIX_VEX_0F73_REG_3,
 927   PREFIX_VEX_0F73_REG_6,
 928   PREFIX_VEX_0F73_REG_7,
 929   PREFIX_VEX_0F74,
 930   PREFIX_VEX_0F75,
 931   PREFIX_VEX_0F76,
 932   PREFIX_VEX_0F77,
 933   PREFIX_VEX_0F7C,
 934   PREFIX_VEX_0F7D,
 935   PREFIX_VEX_0F7E,
 936   PREFIX_VEX_0F7F,
 937   PREFIX_VEX_0FC2,
 938   PREFIX_VEX_0FC4,
 939   PREFIX_VEX_0FC5,
 940   PREFIX_VEX_0FD0,
 941   PREFIX_VEX_0FD1,
 942   PREFIX_VEX_0FD2,
 943   PREFIX_VEX_0FD3,
 944   PREFIX_VEX_0FD4,
 945   PREFIX_VEX_0FD5,
 946   PREFIX_VEX_0FD6,
 947   PREFIX_VEX_0FD7,
 948   PREFIX_VEX_0FD8,
 949   PREFIX_VEX_0FD9,
 950   PREFIX_VEX_0FDA,
 951   PREFIX_VEX_0FDB,
 952   PREFIX_VEX_0FDC,
 953   PREFIX_VEX_0FDD,
 954   PREFIX_VEX_0FDE,
 955   PREFIX_VEX_0FDF,
 956   PREFIX_VEX_0FE0,
 957   PREFIX_VEX_0FE1,
 958   PREFIX_VEX_0FE2,
 959   PREFIX_VEX_0FE3,
 960   PREFIX_VEX_0FE4,
 961   PREFIX_VEX_0FE5,
 962   PREFIX_VEX_0FE6,
 963   PREFIX_VEX_0FE7,
 964   PREFIX_VEX_0FE8,
 965   PREFIX_VEX_0FE9,
 966   PREFIX_VEX_0FEA,
 967   PREFIX_VEX_0FEB,
 968   PREFIX_VEX_0FEC,
 969   PREFIX_VEX_0FED,
 970   PREFIX_VEX_0FEE,
 971   PREFIX_VEX_0FEF,
 972   PREFIX_VEX_0FF0,
 973   PREFIX_VEX_0FF1,
 974   PREFIX_VEX_0FF2,
 975   PREFIX_VEX_0FF3,
 976   PREFIX_VEX_0FF4,
 977   PREFIX_VEX_0FF5,
 978   PREFIX_VEX_0FF6,
 979   PREFIX_VEX_0FF7,
 980   PREFIX_VEX_0FF8,
 981   PREFIX_VEX_0FF9,
 982   PREFIX_VEX_0FFA,
 983   PREFIX_VEX_0FFB,
 984   PREFIX_VEX_0FFC,
 985   PREFIX_VEX_0FFD,
 986   PREFIX_VEX_0FFE,
 987   PREFIX_VEX_0F3800,
 988   PREFIX_VEX_0F3801,
 989   PREFIX_VEX_0F3802,
 990   PREFIX_VEX_0F3803,
 991   PREFIX_VEX_0F3804,
 992   PREFIX_VEX_0F3805,
 993   PREFIX_VEX_0F3806,
 994   PREFIX_VEX_0F3807,
 995   PREFIX_VEX_0F3808,
 996   PREFIX_VEX_0F3809,
 997   PREFIX_VEX_0F380A,
 998   PREFIX_VEX_0F380B,
 999   PREFIX_VEX_0F380C,
1000   PREFIX_VEX_0F380D,
1001   PREFIX_VEX_0F380E,
1002   PREFIX_VEX_0F380F,
1003   PREFIX_VEX_0F3813,
1004   PREFIX_VEX_0F3816,
1005   PREFIX_VEX_0F3817,
1006   PREFIX_VEX_0F3818,
1007   PREFIX_VEX_0F3819,
1008   PREFIX_VEX_0F381A,
1009   PREFIX_VEX_0F381C,
1010   PREFIX_VEX_0F381D,
1011   PREFIX_VEX_0F381E,
1012   PREFIX_VEX_0F3820,
1013   PREFIX_VEX_0F3821,
1014   PREFIX_VEX_0F3822,
1015   PREFIX_VEX_0F3823,
1016   PREFIX_VEX_0F3824,
1017   PREFIX_VEX_0F3825,
1018   PREFIX_VEX_0F3828,
1019   PREFIX_VEX_0F3829,
1020   PREFIX_VEX_0F382A,
1021   PREFIX_VEX_0F382B,
1022   PREFIX_VEX_0F382C,
1023   PREFIX_VEX_0F382D,
1024   PREFIX_VEX_0F382E,
1025   PREFIX_VEX_0F382F,
1026   PREFIX_VEX_0F3830,
1027   PREFIX_VEX_0F3831,
1028   PREFIX_VEX_0F3832,
1029   PREFIX_VEX_0F3833,
1030   PREFIX_VEX_0F3834,
1031   PREFIX_VEX_0F3835,
1032   PREFIX_VEX_0F3836,
1033   PREFIX_VEX_0F3837,
1034   PREFIX_VEX_0F3838,
1035   PREFIX_VEX_0F3839,
1036   PREFIX_VEX_0F383A,
1037   PREFIX_VEX_0F383B,
1038   PREFIX_VEX_0F383C,
1039   PREFIX_VEX_0F383D,
1040   PREFIX_VEX_0F383E,
1041   PREFIX_VEX_0F383F,
1042   PREFIX_VEX_0F3840,
1043   PREFIX_VEX_0F3841,
1044   PREFIX_VEX_0F3845,
1045   PREFIX_VEX_0F3846,
1046   PREFIX_VEX_0F3847,
1047   PREFIX_VEX_0F3858,
1048   PREFIX_VEX_0F3859,
1049   PREFIX_VEX_0F385A,
1050   PREFIX_VEX_0F3878,
1051   PREFIX_VEX_0F3879,
1052   PREFIX_VEX_0F388C,
1053   PREFIX_VEX_0F388E,
1054   PREFIX_VEX_0F3890,
1055   PREFIX_VEX_0F3891,
1056   PREFIX_VEX_0F3892,
1057   PREFIX_VEX_0F3893,
1058   PREFIX_VEX_0F3896,
1059   PREFIX_VEX_0F3897,
1060   PREFIX_VEX_0F3898,
1061   PREFIX_VEX_0F3899,
1062   PREFIX_VEX_0F389A,
1063   PREFIX_VEX_0F389B,
1064   PREFIX_VEX_0F389C,
1065   PREFIX_VEX_0F389D,
1066   PREFIX_VEX_0F389E,
1067   PREFIX_VEX_0F389F,
1068   PREFIX_VEX_0F38A6,
1069   PREFIX_VEX_0F38A7,
1070   PREFIX_VEX_0F38A8,
1071   PREFIX_VEX_0F38A9,
1072   PREFIX_VEX_0F38AA,
1073   PREFIX_VEX_0F38AB,
1074   PREFIX_VEX_0F38AC,
1075   PREFIX_VEX_0F38AD,
1076   PREFIX_VEX_0F38AE,
1077   PREFIX_VEX_0F38AF,
1078   PREFIX_VEX_0F38B6,
1079   PREFIX_VEX_0F38B7,
1080   PREFIX_VEX_0F38B8,
1081   PREFIX_VEX_0F38B9,
1082   PREFIX_VEX_0F38BA,
1083   PREFIX_VEX_0F38BB,
1084   PREFIX_VEX_0F38BC,
1085   PREFIX_VEX_0F38BD,
1086   PREFIX_VEX_0F38BE,
1087   PREFIX_VEX_0F38BF,
1088   PREFIX_VEX_0F38DB,
1089   PREFIX_VEX_0F38DC,
1090   PREFIX_VEX_0F38DD,
1091   PREFIX_VEX_0F38DE,
1092   PREFIX_VEX_0F38DF,
1093   PREFIX_VEX_0F38F2,
1094   PREFIX_VEX_0F38F3_REG_1,
1095   PREFIX_VEX_0F38F3_REG_2,
1096   PREFIX_VEX_0F38F3_REG_3,
1097   PREFIX_VEX_0F38F5,
1098   PREFIX_VEX_0F38F6,
1099   PREFIX_VEX_0F38F7,
1100   PREFIX_VEX_0F3A00,
1101   PREFIX_VEX_0F3A01,
1102   PREFIX_VEX_0F3A02,
1103   PREFIX_VEX_0F3A04,
1104   PREFIX_VEX_0F3A05,
1105   PREFIX_VEX_0F3A06,
1106   PREFIX_VEX_0F3A08,
1107   PREFIX_VEX_0F3A09,
1108   PREFIX_VEX_0F3A0A,
1109   PREFIX_VEX_0F3A0B,
1110   PREFIX_VEX_0F3A0C,
1111   PREFIX_VEX_0F3A0D,
1112   PREFIX_VEX_0F3A0E,
1113   PREFIX_VEX_0F3A0F,
1114   PREFIX_VEX_0F3A14,
1115   PREFIX_VEX_0F3A15,
1116   PREFIX_VEX_0F3A16,
1117   PREFIX_VEX_0F3A17,
1118   PREFIX_VEX_0F3A18,
1119   PREFIX_VEX_0F3A19,
1120   PREFIX_VEX_0F3A1D,
1121   PREFIX_VEX_0F3A20,
1122   PREFIX_VEX_0F3A21,
1123   PREFIX_VEX_0F3A22,
1124   PREFIX_VEX_0F3A38,
1125   PREFIX_VEX_0F3A39,
1126   PREFIX_VEX_0F3A40,
1127   PREFIX_VEX_0F3A41,
1128   PREFIX_VEX_0F3A42,
1129   PREFIX_VEX_0F3A44,
1130   PREFIX_VEX_0F3A46,
1131   PREFIX_VEX_0F3A48,
1132   PREFIX_VEX_0F3A49,
1133   PREFIX_VEX_0F3A4A,
1134   PREFIX_VEX_0F3A4B,
1135   PREFIX_VEX_0F3A4C,
1136   PREFIX_VEX_0F3A5C,
1137   PREFIX_VEX_0F3A5D,
1138   PREFIX_VEX_0F3A5E,
1139   PREFIX_VEX_0F3A5F,
1140   PREFIX_VEX_0F3A60,
1141   PREFIX_VEX_0F3A61,
1142   PREFIX_VEX_0F3A62,
1143   PREFIX_VEX_0F3A63,
1144   PREFIX_VEX_0F3A68,
1145   PREFIX_VEX_0F3A69,
1146   PREFIX_VEX_0F3A6A,
1147   PREFIX_VEX_0F3A6B,
1148   PREFIX_VEX_0F3A6C,
1149   PREFIX_VEX_0F3A6D,
1150   PREFIX_VEX_0F3A6E,
1151   PREFIX_VEX_0F3A6F,
1152   PREFIX_VEX_0F3A78,
1153   PREFIX_VEX_0F3A79,
1154   PREFIX_VEX_0F3A7A,
1155   PREFIX_VEX_0F3A7B,
1156   PREFIX_VEX_0F3A7C,
1157   PREFIX_VEX_0F3A7D,
1158   PREFIX_VEX_0F3A7E,
1159   PREFIX_VEX_0F3A7F,
1160   PREFIX_VEX_0F3ADF,
1161   PREFIX_VEX_0F3AF0
1162 };
1163
1164 enum
1165 {
1166   X86_64_06 = 0,
1167   X86_64_07,
1168   X86_64_0D,
1169   X86_64_16,
1170   X86_64_17,
1171   X86_64_1E,
1172   X86_64_1F,
1173   X86_64_27,
1174   X86_64_2F,
1175   X86_64_37,
1176   X86_64_3F,
1177   X86_64_60,
1178   X86_64_61,
1179   X86_64_62,
1180   X86_64_63,
1181   X86_64_6D,
1182   X86_64_6F,
1183   X86_64_9A,
1184   X86_64_C4,
1185   X86_64_C5,
1186   X86_64_CE,
1187   X86_64_D4,
1188   X86_64_D5,
1189   X86_64_EA,
1190   X86_64_0F01_REG_0,
1191   X86_64_0F01_REG_1,
1192   X86_64_0F01_REG_2,
1193   X86_64_0F01_REG_3
1194 };
1195
1196 enum
1197 {
1198   THREE_BYTE_0F38 = 0,
1199   THREE_BYTE_0F3A,
1200   THREE_BYTE_0F7A
1201 };
1202
1203 enum
1204 {
1205   XOP_08 = 0,
1206   XOP_09,
1207   XOP_0A
1208 };
1209
1210 enum
1211 {
1212   VEX_0F = 0,
1213   VEX_0F38,
1214   VEX_0F3A
1215 };
1216
1217 enum
1218 {
1219   VEX_LEN_0F10_P_1 = 0,
1220   VEX_LEN_0F10_P_3,
1221   VEX_LEN_0F11_P_1,
1222   VEX_LEN_0F11_P_3,
1223   VEX_LEN_0F12_P_0_M_0,
1224   VEX_LEN_0F12_P_0_M_1,
1225   VEX_LEN_0F12_P_2,
1226   VEX_LEN_0F13_M_0,
1227   VEX_LEN_0F16_P_0_M_0,
1228   VEX_LEN_0F16_P_0_M_1,
1229   VEX_LEN_0F16_P_2,
1230   VEX_LEN_0F17_M_0,
1231   VEX_LEN_0F2A_P_1,
1232   VEX_LEN_0F2A_P_3,
1233   VEX_LEN_0F2C_P_1,
1234   VEX_LEN_0F2C_P_3,
1235   VEX_LEN_0F2D_P_1,
1236   VEX_LEN_0F2D_P_3,
1237   VEX_LEN_0F2E_P_0,
1238   VEX_LEN_0F2E_P_2,
1239   VEX_LEN_0F2F_P_0,
1240   VEX_LEN_0F2F_P_2,
1241   VEX_LEN_0F51_P_1,
1242   VEX_LEN_0F51_P_3,
1243   VEX_LEN_0F52_P_1,
1244   VEX_LEN_0F53_P_1,
1245   VEX_LEN_0F58_P_1,
1246   VEX_LEN_0F58_P_3,
1247   VEX_LEN_0F59_P_1,
1248   VEX_LEN_0F59_P_3,
1249   VEX_LEN_0F5A_P_1,
1250   VEX_LEN_0F5A_P_3,
1251   VEX_LEN_0F5C_P_1,
1252   VEX_LEN_0F5C_P_3,
1253   VEX_LEN_0F5D_P_1,
1254   VEX_LEN_0F5D_P_3,
1255   VEX_LEN_0F5E_P_1,
1256   VEX_LEN_0F5E_P_3,
1257   VEX_LEN_0F5F_P_1,
1258   VEX_LEN_0F5F_P_3,
1259   VEX_LEN_0F6E_P_2,
1260   VEX_LEN_0F7E_P_1,
1261   VEX_LEN_0F7E_P_2,
1262   VEX_LEN_0FAE_R_2_M_0,
1263   VEX_LEN_0FAE_R_3_M_0,
1264   VEX_LEN_0FC2_P_1,
1265   VEX_LEN_0FC2_P_3,
1266   VEX_LEN_0FC4_P_2,
1267   VEX_LEN_0FC5_P_2,
1268   VEX_LEN_0FD6_P_2,
1269   VEX_LEN_0FF7_P_2,
1270   VEX_LEN_0F3816_P_2,
1271   VEX_LEN_0F3819_P_2,
1272   VEX_LEN_0F381A_P_2_M_0,
1273   VEX_LEN_0F3836_P_2,
1274   VEX_LEN_0F3841_P_2,
1275   VEX_LEN_0F385A_P_2_M_0,
1276   VEX_LEN_0F38DB_P_2,
1277   VEX_LEN_0F38DC_P_2,
1278   VEX_LEN_0F38DD_P_2,
1279   VEX_LEN_0F38DE_P_2,
1280   VEX_LEN_0F38DF_P_2,
1281   VEX_LEN_0F38F2_P_0,
1282   VEX_LEN_0F38F3_R_1_P_0,
1283   VEX_LEN_0F38F3_R_2_P_0,
1284   VEX_LEN_0F38F3_R_3_P_0,
1285   VEX_LEN_0F38F5_P_0,
1286   VEX_LEN_0F38F5_P_1,
1287   VEX_LEN_0F38F5_P_3,
1288   VEX_LEN_0F38F6_P_3,
1289   VEX_LEN_0F38F7_P_0,
1290   VEX_LEN_0F38F7_P_1,
1291   VEX_LEN_0F38F7_P_2,
1292   VEX_LEN_0F38F7_P_3,
1293   VEX_LEN_0F3A00_P_2,
1294   VEX_LEN_0F3A01_P_2,
1295   VEX_LEN_0F3A06_P_2,
1296   VEX_LEN_0F3A0A_P_2,
1297   VEX_LEN_0F3A0B_P_2,
1298   VEX_LEN_0F3A14_P_2,
1299   VEX_LEN_0F3A15_P_2,
1300   VEX_LEN_0F3A16_P_2,
1301   VEX_LEN_0F3A17_P_2,
1302   VEX_LEN_0F3A18_P_2,
1303   VEX_LEN_0F3A19_P_2,
1304   VEX_LEN_0F3A20_P_2,
1305   VEX_LEN_0F3A21_P_2,
1306   VEX_LEN_0F3A22_P_2,
1307   VEX_LEN_0F3A38_P_2,
1308   VEX_LEN_0F3A39_P_2,
1309   VEX_LEN_0F3A41_P_2,
1310   VEX_LEN_0F3A44_P_2,
1311   VEX_LEN_0F3A46_P_2,
1312   VEX_LEN_0F3A60_P_2,
1313   VEX_LEN_0F3A61_P_2,
1314   VEX_LEN_0F3A62_P_2,
1315   VEX_LEN_0F3A63_P_2,
1316   VEX_LEN_0F3A6A_P_2,
1317   VEX_LEN_0F3A6B_P_2,
1318   VEX_LEN_0F3A6E_P_2,
1319   VEX_LEN_0F3A6F_P_2,
1320   VEX_LEN_0F3A7A_P_2,
1321   VEX_LEN_0F3A7B_P_2,
1322   VEX_LEN_0F3A7E_P_2,
1323   VEX_LEN_0F3A7F_P_2,
1324   VEX_LEN_0F3ADF_P_2,
1325   VEX_LEN_0F3AF0_P_3,
1326   VEX_LEN_0FXOP_08_CC,
1327   VEX_LEN_0FXOP_08_CD,
1328   VEX_LEN_0FXOP_08_CE,
1329   VEX_LEN_0FXOP_08_CF,
1330   VEX_LEN_0FXOP_08_EC,
1331   VEX_LEN_0FXOP_08_ED,
1332   VEX_LEN_0FXOP_08_EE,
1333   VEX_LEN_0FXOP_08_EF,
1334   VEX_LEN_0FXOP_09_80,
1335   VEX_LEN_0FXOP_09_81
1336 };
1337
1338 enum
1339 {
1340   VEX_W_0F10_P_0 = 0,
1341   VEX_W_0F10_P_1,
1342   VEX_W_0F10_P_2,
1343   VEX_W_0F10_P_3,
1344   VEX_W_0F11_P_0,
1345   VEX_W_0F11_P_1,
1346   VEX_W_0F11_P_2,
1347   VEX_W_0F11_P_3,
1348   VEX_W_0F12_P_0_M_0,
1349   VEX_W_0F12_P_0_M_1,
1350   VEX_W_0F12_P_1,
1351   VEX_W_0F12_P_2,
1352   VEX_W_0F12_P_3,
1353   VEX_W_0F13_M_0,
1354   VEX_W_0F14,
1355   VEX_W_0F15,
1356   VEX_W_0F16_P_0_M_0,
1357   VEX_W_0F16_P_0_M_1,
1358   VEX_W_0F16_P_1,
1359   VEX_W_0F16_P_2,
1360   VEX_W_0F17_M_0,
1361   VEX_W_0F28,
1362   VEX_W_0F29,
1363   VEX_W_0F2B_M_0,
1364   VEX_W_0F2E_P_0,
1365   VEX_W_0F2E_P_2,
1366   VEX_W_0F2F_P_0,
1367   VEX_W_0F2F_P_2,
1368   VEX_W_0F50_M_0,
1369   VEX_W_0F51_P_0,
1370   VEX_W_0F51_P_1,
1371   VEX_W_0F51_P_2,
1372   VEX_W_0F51_P_3,
1373   VEX_W_0F52_P_0,
1374   VEX_W_0F52_P_1,
1375   VEX_W_0F53_P_0,
1376   VEX_W_0F53_P_1,
1377   VEX_W_0F58_P_0,
1378   VEX_W_0F58_P_1,
1379   VEX_W_0F58_P_2,
1380   VEX_W_0F58_P_3,
1381   VEX_W_0F59_P_0,
1382   VEX_W_0F59_P_1,
1383   VEX_W_0F59_P_2,
1384   VEX_W_0F59_P_3,
1385   VEX_W_0F5A_P_0,
1386   VEX_W_0F5A_P_1,
1387   VEX_W_0F5A_P_3,
1388   VEX_W_0F5B_P_0,
1389   VEX_W_0F5B_P_1,
1390   VEX_W_0F5B_P_2,
1391   VEX_W_0F5C_P_0,
1392   VEX_W_0F5C_P_1,
1393   VEX_W_0F5C_P_2,
1394   VEX_W_0F5C_P_3,
1395   VEX_W_0F5D_P_0,
1396   VEX_W_0F5D_P_1,
1397   VEX_W_0F5D_P_2,
1398   VEX_W_0F5D_P_3,
1399   VEX_W_0F5E_P_0,
1400   VEX_W_0F5E_P_1,
1401   VEX_W_0F5E_P_2,
1402   VEX_W_0F5E_P_3,
1403   VEX_W_0F5F_P_0,
1404   VEX_W_0F5F_P_1,
1405   VEX_W_0F5F_P_2,
1406   VEX_W_0F5F_P_3,
1407   VEX_W_0F60_P_2,
1408   VEX_W_0F61_P_2,
1409   VEX_W_0F62_P_2,
1410   VEX_W_0F63_P_2,
1411   VEX_W_0F64_P_2,
1412   VEX_W_0F65_P_2,
1413   VEX_W_0F66_P_2,
1414   VEX_W_0F67_P_2,
1415   VEX_W_0F68_P_2,
1416   VEX_W_0F69_P_2,
1417   VEX_W_0F6A_P_2,
1418   VEX_W_0F6B_P_2,
1419   VEX_W_0F6C_P_2,
1420   VEX_W_0F6D_P_2,
1421   VEX_W_0F6F_P_1,
1422   VEX_W_0F6F_P_2,
1423   VEX_W_0F70_P_1,
1424   VEX_W_0F70_P_2,
1425   VEX_W_0F70_P_3,
1426   VEX_W_0F71_R_2_P_2,
1427   VEX_W_0F71_R_4_P_2,
1428   VEX_W_0F71_R_6_P_2,
1429   VEX_W_0F72_R_2_P_2,
1430   VEX_W_0F72_R_4_P_2,
1431   VEX_W_0F72_R_6_P_2,
1432   VEX_W_0F73_R_2_P_2,
1433   VEX_W_0F73_R_3_P_2,
1434   VEX_W_0F73_R_6_P_2,
1435   VEX_W_0F73_R_7_P_2,
1436   VEX_W_0F74_P_2,
1437   VEX_W_0F75_P_2,
1438   VEX_W_0F76_P_2,
1439   VEX_W_0F77_P_0,
1440   VEX_W_0F7C_P_2,
1441   VEX_W_0F7C_P_3,
1442   VEX_W_0F7D_P_2,
1443   VEX_W_0F7D_P_3,
1444   VEX_W_0F7E_P_1,
1445   VEX_W_0F7F_P_1,
1446   VEX_W_0F7F_P_2,
1447   VEX_W_0FAE_R_2_M_0,
1448   VEX_W_0FAE_R_3_M_0,
1449   VEX_W_0FC2_P_0,
1450   VEX_W_0FC2_P_1,
1451   VEX_W_0FC2_P_2,
1452   VEX_W_0FC2_P_3,
1453   VEX_W_0FC4_P_2,
1454   VEX_W_0FC5_P_2,
1455   VEX_W_0FD0_P_2,
1456   VEX_W_0FD0_P_3,
1457   VEX_W_0FD1_P_2,
1458   VEX_W_0FD2_P_2,
1459   VEX_W_0FD3_P_2,
1460   VEX_W_0FD4_P_2,
1461   VEX_W_0FD5_P_2,
1462   VEX_W_0FD6_P_2,
1463   VEX_W_0FD7_P_2_M_1,
1464   VEX_W_0FD8_P_2,
1465   VEX_W_0FD9_P_2,
1466   VEX_W_0FDA_P_2,
1467   VEX_W_0FDB_P_2,
1468   VEX_W_0FDC_P_2,
1469   VEX_W_0FDD_P_2,
1470   VEX_W_0FDE_P_2,
1471   VEX_W_0FDF_P_2,
1472   VEX_W_0FE0_P_2,
1473   VEX_W_0FE1_P_2,
1474   VEX_W_0FE2_P_2,
1475   VEX_W_0FE3_P_2,
1476   VEX_W_0FE4_P_2,
1477   VEX_W_0FE5_P_2,
1478   VEX_W_0FE6_P_1,
1479   VEX_W_0FE6_P_2,
1480   VEX_W_0FE6_P_3,
1481   VEX_W_0FE7_P_2_M_0,
1482   VEX_W_0FE8_P_2,
1483   VEX_W_0FE9_P_2,
1484   VEX_W_0FEA_P_2,
1485   VEX_W_0FEB_P_2,
1486   VEX_W_0FEC_P_2,
1487   VEX_W_0FED_P_2,
1488   VEX_W_0FEE_P_2,
1489   VEX_W_0FEF_P_2,
1490   VEX_W_0FF0_P_3_M_0,
1491   VEX_W_0FF1_P_2,
1492   VEX_W_0FF2_P_2,
1493   VEX_W_0FF3_P_2,
1494   VEX_W_0FF4_P_2,
1495   VEX_W_0FF5_P_2,
1496   VEX_W_0FF6_P_2,
1497   VEX_W_0FF7_P_2,
1498   VEX_W_0FF8_P_2,
1499   VEX_W_0FF9_P_2,
1500   VEX_W_0FFA_P_2,
1501   VEX_W_0FFB_P_2,
1502   VEX_W_0FFC_P_2,
1503   VEX_W_0FFD_P_2,
1504   VEX_W_0FFE_P_2,
1505   VEX_W_0F3800_P_2,
1506   VEX_W_0F3801_P_2,
1507   VEX_W_0F3802_P_2,
1508   VEX_W_0F3803_P_2,
1509   VEX_W_0F3804_P_2,
1510   VEX_W_0F3805_P_2,
1511   VEX_W_0F3806_P_2,
1512   VEX_W_0F3807_P_2,
1513   VEX_W_0F3808_P_2,
1514   VEX_W_0F3809_P_2,
1515   VEX_W_0F380A_P_2,
1516   VEX_W_0F380B_P_2,
1517   VEX_W_0F380C_P_2,
1518   VEX_W_0F380D_P_2,
1519   VEX_W_0F380E_P_2,
1520   VEX_W_0F380F_P_2,
1521   VEX_W_0F3816_P_2,
1522   VEX_W_0F3817_P_2,
1523   VEX_W_0F3818_P_2,
1524   VEX_W_0F3819_P_2,
1525   VEX_W_0F381A_P_2_M_0,
1526   VEX_W_0F381C_P_2,
1527   VEX_W_0F381D_P_2,
1528   VEX_W_0F381E_P_2,
1529   VEX_W_0F3820_P_2,
1530   VEX_W_0F3821_P_2,
1531   VEX_W_0F3822_P_2,
1532   VEX_W_0F3823_P_2,
1533   VEX_W_0F3824_P_2,
1534   VEX_W_0F3825_P_2,
1535   VEX_W_0F3828_P_2,
1536   VEX_W_0F3829_P_2,
1537   VEX_W_0F382A_P_2_M_0,
1538   VEX_W_0F382B_P_2,
1539   VEX_W_0F382C_P_2_M_0,
1540   VEX_W_0F382D_P_2_M_0,
1541   VEX_W_0F382E_P_2_M_0,
1542   VEX_W_0F382F_P_2_M_0,
1543   VEX_W_0F3830_P_2,
1544   VEX_W_0F3831_P_2,
1545   VEX_W_0F3832_P_2,
1546   VEX_W_0F3833_P_2,
1547   VEX_W_0F3834_P_2,
1548   VEX_W_0F3835_P_2,
1549   VEX_W_0F3836_P_2,
1550   VEX_W_0F3837_P_2,
1551   VEX_W_0F3838_P_2,
1552   VEX_W_0F3839_P_2,
1553   VEX_W_0F383A_P_2,
1554   VEX_W_0F383B_P_2,
1555   VEX_W_0F383C_P_2,
1556   VEX_W_0F383D_P_2,
1557   VEX_W_0F383E_P_2,
1558   VEX_W_0F383F_P_2,
1559   VEX_W_0F3840_P_2,
1560   VEX_W_0F3841_P_2,
1561   VEX_W_0F3846_P_2,
1562   VEX_W_0F3858_P_2,
1563   VEX_W_0F3859_P_2,
1564   VEX_W_0F385A_P_2_M_0,
1565   VEX_W_0F3878_P_2,
1566   VEX_W_0F3879_P_2,
1567   VEX_W_0F38DB_P_2,
1568   VEX_W_0F38DC_P_2,
1569   VEX_W_0F38DD_P_2,
1570   VEX_W_0F38DE_P_2,
1571   VEX_W_0F38DF_P_2,
1572   VEX_W_0F3A00_P_2,
1573   VEX_W_0F3A01_P_2,
1574   VEX_W_0F3A02_P_2,
1575   VEX_W_0F3A04_P_2,
1576   VEX_W_0F3A05_P_2,
1577   VEX_W_0F3A06_P_2,
1578   VEX_W_0F3A08_P_2,
1579   VEX_W_0F3A09_P_2,
1580   VEX_W_0F3A0A_P_2,
1581   VEX_W_0F3A0B_P_2,
1582   VEX_W_0F3A0C_P_2,
1583   VEX_W_0F3A0D_P_2,
1584   VEX_W_0F3A0E_P_2,
1585   VEX_W_0F3A0F_P_2,
1586   VEX_W_0F3A14_P_2,
1587   VEX_W_0F3A15_P_2,
1588   VEX_W_0F3A18_P_2,
1589   VEX_W_0F3A19_P_2,
1590   VEX_W_0F3A20_P_2,
1591   VEX_W_0F3A21_P_2,
1592   VEX_W_0F3A38_P_2,
1593   VEX_W_0F3A39_P_2,
1594   VEX_W_0F3A40_P_2,
1595   VEX_W_0F3A41_P_2,
1596   VEX_W_0F3A42_P_2,
1597   VEX_W_0F3A44_P_2,
1598   VEX_W_0F3A46_P_2,
1599   VEX_W_0F3A48_P_2,
1600   VEX_W_0F3A49_P_2,
1601   VEX_W_0F3A4A_P_2,
1602   VEX_W_0F3A4B_P_2,
1603   VEX_W_0F3A4C_P_2,
1604   VEX_W_0F3A60_P_2,
1605   VEX_W_0F3A61_P_2,
1606   VEX_W_0F3A62_P_2,
1607   VEX_W_0F3A63_P_2,
1608   VEX_W_0F3ADF_P_2
1609 };
1610
1611 typedef void (*op_rtn) (int bytemode, int sizeflag);
1612
1613 struct dis386 {
1614   const char *name;
1615   struct
1616     {
1617       op_rtn rtn;
1618       int bytemode;
1619     } op[MAX_OPERANDS];
1620 };
1621
1622 /* Upper case letters in the instruction names here are macros.
1623    'A' => print 'b' if no register operands or suffix_always is true
1624    'B' => print 'b' if suffix_always is true
1625    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1626           size prefix
1627    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1628           suffix_always is true
1629    'E' => print 'e' if 32-bit form of jcxz
1630    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1631    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1632    'H' => print ",pt" or ",pn" branch hint
1633    'I' => honor following macro letter even in Intel mode (implemented only
1634           for some of the macro letters)
1635    'J' => print 'l'
1636    'K' => print 'd' or 'q' if rex prefix is present.
1637    'L' => print 'l' if suffix_always is true
1638    'M' => print 'r' if intel_mnemonic is false.
1639    'N' => print 'n' if instruction has no wait "prefix"
1640    'O' => print 'd' or 'o' (or 'q' in Intel mode)
1641    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
1642           or suffix_always is true.  print 'q' if rex prefix is present.
1643    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1644           is true
1645    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1646    'S' => print 'w', 'l' or 'q' if suffix_always is true
1647    'T' => print 'q' in 64bit mode and behave as 'P' otherwise
1648    'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
1649    'V' => print 'q' in 64bit mode and behave as 'S' otherwise
1650    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1651    'X' => print 's', 'd' depending on data16 prefix (for XMM)
1652    'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
1653           suffix_always is true.
1654    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
1655    '!' => change condition from true to false or from false to true.
1656    '%' => add 1 upper case letter to the macro.
1657
1658    2 upper case letter macros:
1659    "XY" => print 'x' or 'y' if no register operands or suffix_always
1660            is true.
1661    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1662    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
1663            or suffix_always is true
1664    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1665    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1666    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1667    "LW" => print 'd', 'q' depending on the VEX.W bit
1668
1669    Many of the above letters print nothing in Intel mode.  See "putop"
1670    for the details.
1671
1672    Braces '{' and '}', and vertical bars '|', indicate alternative
1673    mnemonic strings for AT&T and Intel.  */
1674
1675 static const struct dis386 dis386[] = {
1676   /* 00 */
1677   { "addB",             { Ebh1, Gb } },
1678   { "addS",             { Evh1, Gv } },
1679   { "addB",             { Gb, EbS } },
1680   { "addS",             { Gv, EvS } },
1681   { "addB",             { AL, Ib } },
1682   { "addS",             { eAX, Iv } },
1683   { X86_64_TABLE (X86_64_06) },
1684   { X86_64_TABLE (X86_64_07) },
1685   /* 08 */
1686   { "orB",              { Ebh1, Gb } },
1687   { "orS",              { Evh1, Gv } },
1688   { "orB",              { Gb, EbS } },
1689   { "orS",              { Gv, EvS } },
1690   { "orB",              { AL, Ib } },
1691   { "orS",              { eAX, Iv } },
1692   { X86_64_TABLE (X86_64_0D) },
1693   { Bad_Opcode },       /* 0x0f extended opcode escape */
1694   /* 10 */
1695   { "adcB",             { Ebh1, Gb } },
1696   { "adcS",             { Evh1, Gv } },
1697   { "adcB",             { Gb, EbS } },
1698   { "adcS",             { Gv, EvS } },
1699   { "adcB",             { AL, Ib } },
1700   { "adcS",             { eAX, Iv } },
1701   { X86_64_TABLE (X86_64_16) },
1702   { X86_64_TABLE (X86_64_17) },
1703   /* 18 */
1704   { "sbbB",             { Ebh1, Gb } },
1705   { "sbbS",             { Evh1, Gv } },
1706   { "sbbB",             { Gb, EbS } },
1707   { "sbbS",             { Gv, EvS } },
1708   { "sbbB",             { AL, Ib } },
1709   { "sbbS",             { eAX, Iv } },
1710   { X86_64_TABLE (X86_64_1E) },
1711   { X86_64_TABLE (X86_64_1F) },
1712   /* 20 */
1713   { "andB",             { Ebh1, Gb } },
1714   { "andS",             { Evh1, Gv } },
1715   { "andB",             { Gb, EbS } },
1716   { "andS",             { Gv, EvS } },
1717   { "andB",             { AL, Ib } },
1718   { "andS",             { eAX, Iv } },
1719   { Bad_Opcode },       /* SEG ES prefix */
1720   { X86_64_TABLE (X86_64_27) },
1721   /* 28 */
1722   { "subB",             { Ebh1, Gb } },
1723   { "subS",             { Evh1, Gv } },
1724   { "subB",             { Gb, EbS } },
1725   { "subS",             { Gv, EvS } },
1726   { "subB",             { AL, Ib } },
1727   { "subS",             { eAX, Iv } },
1728   { Bad_Opcode },       /* SEG CS prefix */
1729   { X86_64_TABLE (X86_64_2F) },
1730   /* 30 */
1731   { "xorB",             { Ebh1, Gb } },
1732   { "xorS",             { Evh1, Gv } },
1733   { "xorB",             { Gb, EbS } },
1734   { "xorS",             { Gv, EvS } },
1735   { "xorB",             { AL, Ib } },
1736   { "xorS",             { eAX, Iv } },
1737   { Bad_Opcode },       /* SEG SS prefix */
1738   { X86_64_TABLE (X86_64_37) },
1739   /* 38 */
1740   { "cmpB",             { Eb, Gb } },
1741   { "cmpS",             { Ev, Gv } },
1742   { "cmpB",             { Gb, EbS } },
1743   { "cmpS",             { Gv, EvS } },
1744   { "cmpB",             { AL, Ib } },
1745   { "cmpS",             { eAX, Iv } },
1746   { Bad_Opcode },       /* SEG DS prefix */
1747   { X86_64_TABLE (X86_64_3F) },
1748   /* 40 */
1749   { "inc{S|}",          { RMeAX } },
1750   { "inc{S|}",          { RMeCX } },
1751   { "inc{S|}",          { RMeDX } },
1752   { "inc{S|}",          { RMeBX } },
1753   { "inc{S|}",          { RMeSP } },
1754   { "inc{S|}",          { RMeBP } },
1755   { "inc{S|}",          { RMeSI } },
1756   { "inc{S|}",          { RMeDI } },
1757   /* 48 */
1758   { "dec{S|}",          { RMeAX } },
1759   { "dec{S|}",          { RMeCX } },
1760   { "dec{S|}",          { RMeDX } },
1761   { "dec{S|}",          { RMeBX } },
1762   { "dec{S|}",          { RMeSP } },
1763   { "dec{S|}",          { RMeBP } },
1764   { "dec{S|}",          { RMeSI } },
1765   { "dec{S|}",          { RMeDI } },
1766   /* 50 */
1767   { "pushV",            { RMrAX } },
1768   { "pushV",            { RMrCX } },
1769   { "pushV",            { RMrDX } },
1770   { "pushV",            { RMrBX } },
1771   { "pushV",            { RMrSP } },
1772   { "pushV",            { RMrBP } },
1773   { "pushV",            { RMrSI } },
1774   { "pushV",            { RMrDI } },
1775   /* 58 */
1776   { "popV",             { RMrAX } },
1777   { "popV",             { RMrCX } },
1778   { "popV",             { RMrDX } },
1779   { "popV",             { RMrBX } },
1780   { "popV",             { RMrSP } },
1781   { "popV",             { RMrBP } },
1782   { "popV",             { RMrSI } },
1783   { "popV",             { RMrDI } },
1784   /* 60 */
1785   { X86_64_TABLE (X86_64_60) },
1786   { X86_64_TABLE (X86_64_61) },
1787   { X86_64_TABLE (X86_64_62) },
1788   { X86_64_TABLE (X86_64_63) },
1789   { Bad_Opcode },       /* seg fs */
1790   { Bad_Opcode },       /* seg gs */
1791   { Bad_Opcode },       /* op size prefix */
1792   { Bad_Opcode },       /* adr size prefix */
1793   /* 68 */
1794   { "pushT",            { sIv } },
1795   { "imulS",            { Gv, Ev, Iv } },
1796   { "pushT",            { sIbT } },
1797   { "imulS",            { Gv, Ev, sIb } },
1798   { "ins{b|}",          { Ybr, indirDX } },
1799   { X86_64_TABLE (X86_64_6D) },
1800   { "outs{b|}",         { indirDXr, Xb } },
1801   { X86_64_TABLE (X86_64_6F) },
1802   /* 70 */
1803   { "joH",              { Jb, XX, cond_jump_flag } },
1804   { "jnoH",             { Jb, XX, cond_jump_flag } },
1805   { "jbH",              { Jb, XX, cond_jump_flag } },
1806   { "jaeH",             { Jb, XX, cond_jump_flag } },
1807   { "jeH",              { Jb, XX, cond_jump_flag } },
1808   { "jneH",             { Jb, XX, cond_jump_flag } },
1809   { "jbeH",             { Jb, XX, cond_jump_flag } },
1810   { "jaH",              { Jb, XX, cond_jump_flag } },
1811   /* 78 */
1812   { "jsH",              { Jb, XX, cond_jump_flag } },
1813   { "jnsH",             { Jb, XX, cond_jump_flag } },
1814   { "jpH",              { Jb, XX, cond_jump_flag } },
1815   { "jnpH",             { Jb, XX, cond_jump_flag } },
1816   { "jlH",              { Jb, XX, cond_jump_flag } },
1817   { "jgeH",             { Jb, XX, cond_jump_flag } },
1818   { "jleH",             { Jb, XX, cond_jump_flag } },
1819   { "jgH",              { Jb, XX, cond_jump_flag } },
1820   /* 80 */
1821   { REG_TABLE (REG_80) },
1822   { REG_TABLE (REG_81) },
1823   { Bad_Opcode },
1824   { REG_TABLE (REG_82) },
1825   { "testB",            { Eb, Gb } },
1826   { "testS",            { Ev, Gv } },
1827   { "xchgB",            { Ebh2, Gb } },
1828   { "xchgS",            { Evh2, Gv } },
1829   /* 88 */
1830   { "movB",             { Ebh3, Gb } },
1831   { "movS",             { Evh3, Gv } },
1832   { "movB",             { Gb, EbS } },
1833   { "movS",             { Gv, EvS } },
1834   { "movD",             { Sv, Sw } },
1835   { MOD_TABLE (MOD_8D) },
1836   { "movD",             { Sw, Sv } },
1837   { REG_TABLE (REG_8F) },
1838   /* 90 */
1839   { PREFIX_TABLE (PREFIX_90) },
1840   { "xchgS",            { RMeCX, eAX } },
1841   { "xchgS",            { RMeDX, eAX } },
1842   { "xchgS",            { RMeBX, eAX } },
1843   { "xchgS",            { RMeSP, eAX } },
1844   { "xchgS",            { RMeBP, eAX } },
1845   { "xchgS",            { RMeSI, eAX } },
1846   { "xchgS",            { RMeDI, eAX } },
1847   /* 98 */
1848   { "cW{t|}R",          { XX } },
1849   { "cR{t|}O",          { XX } },
1850   { X86_64_TABLE (X86_64_9A) },
1851   { Bad_Opcode },       /* fwait */
1852   { "pushfT",           { XX } },
1853   { "popfT",            { XX } },
1854   { "sahf",             { XX } },
1855   { "lahf",             { XX } },
1856   /* a0 */
1857   { "mov%LB",           { AL, Ob } },
1858   { "mov%LS",           { eAX, Ov } },
1859   { "mov%LB",           { Ob, AL } },
1860   { "mov%LS",           { Ov, eAX } },
1861   { "movs{b|}",         { Ybr, Xb } },
1862   { "movs{R|}",         { Yvr, Xv } },
1863   { "cmps{b|}",         { Xb, Yb } },
1864   { "cmps{R|}",         { Xv, Yv } },
1865   /* a8 */
1866   { "testB",            { AL, Ib } },
1867   { "testS",            { eAX, Iv } },
1868   { "stosB",            { Ybr, AL } },
1869   { "stosS",            { Yvr, eAX } },
1870   { "lodsB",            { ALr, Xb } },
1871   { "lodsS",            { eAXr, Xv } },
1872   { "scasB",            { AL, Yb } },
1873   { "scasS",            { eAX, Yv } },
1874   /* b0 */
1875   { "movB",             { RMAL, Ib } },
1876   { "movB",             { RMCL, Ib } },
1877   { "movB",             { RMDL, Ib } },
1878   { "movB",             { RMBL, Ib } },
1879   { "movB",             { RMAH, Ib } },
1880   { "movB",             { RMCH, Ib } },
1881   { "movB",             { RMDH, Ib } },
1882   { "movB",             { RMBH, Ib } },
1883   /* b8 */
1884   { "mov%LV",           { RMeAX, Iv64 } },
1885   { "mov%LV",           { RMeCX, Iv64 } },
1886   { "mov%LV",           { RMeDX, Iv64 } },
1887   { "mov%LV",           { RMeBX, Iv64 } },
1888   { "mov%LV",           { RMeSP, Iv64 } },
1889   { "mov%LV",           { RMeBP, Iv64 } },
1890   { "mov%LV",           { RMeSI, Iv64 } },
1891   { "mov%LV",           { RMeDI, Iv64 } },
1892   /* c0 */
1893   { REG_TABLE (REG_C0) },
1894   { REG_TABLE (REG_C1) },
1895   { "retT",             { Iw } },
1896   { "retT",             { XX } },
1897   { X86_64_TABLE (X86_64_C4) },
1898   { X86_64_TABLE (X86_64_C5) },
1899   { REG_TABLE (REG_C6) },
1900   { REG_TABLE (REG_C7) },
1901   /* c8 */
1902   { "enterT",           { Iw, Ib } },
1903   { "leaveT",           { XX } },
1904   { "Jret{|f}P",        { Iw } },
1905   { "Jret{|f}P",        { XX } },
1906   { "int3",             { XX } },
1907   { "int",              { Ib } },
1908   { X86_64_TABLE (X86_64_CE) },
1909   { "iretP",            { XX } },
1910   /* d0 */
1911   { REG_TABLE (REG_D0) },
1912   { REG_TABLE (REG_D1) },
1913   { REG_TABLE (REG_D2) },
1914   { REG_TABLE (REG_D3) },
1915   { X86_64_TABLE (X86_64_D4) },
1916   { X86_64_TABLE (X86_64_D5) },
1917   { Bad_Opcode },
1918   { "xlat",             { DSBX } },
1919   /* d8 */
1920   { FLOAT },
1921   { FLOAT },
1922   { FLOAT },
1923   { FLOAT },
1924   { FLOAT },
1925   { FLOAT },
1926   { FLOAT },
1927   { FLOAT },
1928   /* e0 */
1929   { "loopneFH",         { Jb, XX, loop_jcxz_flag } },
1930   { "loopeFH",          { Jb, XX, loop_jcxz_flag } },
1931   { "loopFH",           { Jb, XX, loop_jcxz_flag } },
1932   { "jEcxzH",           { Jb, XX, loop_jcxz_flag } },
1933   { "inB",              { AL, Ib } },
1934   { "inG",              { zAX, Ib } },
1935   { "outB",             { Ib, AL } },
1936   { "outG",             { Ib, zAX } },
1937   /* e8 */
1938   { "callT",            { Jv } },
1939   { "jmpT",             { Jv } },
1940   { X86_64_TABLE (X86_64_EA) },
1941   { "jmp",              { Jb } },
1942   { "inB",              { AL, indirDX } },
1943   { "inG",              { zAX, indirDX } },
1944   { "outB",             { indirDX, AL } },
1945   { "outG",             { indirDX, zAX } },
1946   /* f0 */
1947   { Bad_Opcode },       /* lock prefix */
1948   { "icebp",            { XX } },
1949   { Bad_Opcode },       /* repne */
1950   { Bad_Opcode },       /* repz */
1951   { "hlt",              { XX } },
1952   { "cmc",              { XX } },
1953   { REG_TABLE (REG_F6) },
1954   { REG_TABLE (REG_F7) },
1955   /* f8 */
1956   { "clc",              { XX } },
1957   { "stc",              { XX } },
1958   { "cli",              { XX } },
1959   { "sti",              { XX } },
1960   { "cld",              { XX } },
1961   { "std",              { XX } },
1962   { REG_TABLE (REG_FE) },
1963   { REG_TABLE (REG_FF) },
1964 };
1965
1966 static const struct dis386 dis386_twobyte[] = {
1967   /* 00 */
1968   { REG_TABLE (REG_0F00 ) },
1969   { REG_TABLE (REG_0F01 ) },
1970   { "larS",             { Gv, Ew } },
1971   { "lslS",             { Gv, Ew } },
1972   { Bad_Opcode },
1973   { "syscall",          { XX } },
1974   { "clts",             { XX } },
1975   { "sysretP",          { XX } },
1976   /* 08 */
1977   { "invd",             { XX } },
1978   { "wbinvd",           { XX } },
1979   { Bad_Opcode },
1980   { "ud2",              { XX } },
1981   { Bad_Opcode },
1982   { REG_TABLE (REG_0F0D) },
1983   { "femms",            { XX } },
1984   { "",                 { MX, EM, OPSUF } }, /* See OP_3DNowSuffix.  */
1985   /* 10 */
1986   { PREFIX_TABLE (PREFIX_0F10) },
1987   { PREFIX_TABLE (PREFIX_0F11) },
1988   { PREFIX_TABLE (PREFIX_0F12) },
1989   { MOD_TABLE (MOD_0F13) },
1990   { "unpcklpX",         { XM, EXx } },
1991   { "unpckhpX",         { XM, EXx } },
1992   { PREFIX_TABLE (PREFIX_0F16) },
1993   { MOD_TABLE (MOD_0F17) },
1994   /* 18 */
1995   { REG_TABLE (REG_0F18) },
1996   { "nopQ",             { Ev } },
1997   { "nopQ",             { Ev } },
1998   { "nopQ",             { Ev } },
1999   { "nopQ",             { Ev } },
2000   { "nopQ",             { Ev } },
2001   { "nopQ",             { Ev } },
2002   { "nopQ",             { Ev } },
2003   /* 20 */
2004   { MOD_TABLE (MOD_0F20) },
2005   { MOD_TABLE (MOD_0F21) },
2006   { MOD_TABLE (MOD_0F22) },
2007   { MOD_TABLE (MOD_0F23) },
2008   { MOD_TABLE (MOD_0F24) },
2009   { Bad_Opcode },
2010   { MOD_TABLE (MOD_0F26) },
2011   { Bad_Opcode },
2012   /* 28 */
2013   { "movapX",           { XM, EXx } },
2014   { "movapX",           { EXxS, XM } },
2015   { PREFIX_TABLE (PREFIX_0F2A) },
2016   { PREFIX_TABLE (PREFIX_0F2B) },
2017   { PREFIX_TABLE (PREFIX_0F2C) },
2018   { PREFIX_TABLE (PREFIX_0F2D) },
2019   { PREFIX_TABLE (PREFIX_0F2E) },
2020   { PREFIX_TABLE (PREFIX_0F2F) },
2021   /* 30 */
2022   { "wrmsr",            { XX } },
2023   { "rdtsc",            { XX } },
2024   { "rdmsr",            { XX } },
2025   { "rdpmc",            { XX } },
2026   { "sysenter",         { XX } },
2027   { "sysexit",          { XX } },
2028   { Bad_Opcode },
2029   { "getsec",           { XX } },
2030   /* 38 */
2031   { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
2032   { Bad_Opcode },
2033   { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
2034   { Bad_Opcode },
2035   { Bad_Opcode },
2036   { Bad_Opcode },
2037   { Bad_Opcode },
2038   { Bad_Opcode },
2039   /* 40 */
2040   { "cmovoS",           { Gv, Ev } },
2041   { "cmovnoS",          { Gv, Ev } },
2042   { "cmovbS",           { Gv, Ev } },
2043   { "cmovaeS",          { Gv, Ev } },
2044   { "cmoveS",           { Gv, Ev } },
2045   { "cmovneS",          { Gv, Ev } },
2046   { "cmovbeS",          { Gv, Ev } },
2047   { "cmovaS",           { Gv, Ev } },
2048   /* 48 */
2049   { "cmovsS",           { Gv, Ev } },
2050   { "cmovnsS",          { Gv, Ev } },
2051   { "cmovpS",           { Gv, Ev } },
2052   { "cmovnpS",          { Gv, Ev } },
2053   { "cmovlS",           { Gv, Ev } },
2054   { "cmovgeS",          { Gv, Ev } },
2055   { "cmovleS",          { Gv, Ev } },
2056   { "cmovgS",           { Gv, Ev } },
2057   /* 50 */
2058   { MOD_TABLE (MOD_0F51) },
2059   { PREFIX_TABLE (PREFIX_0F51) },
2060   { PREFIX_TABLE (PREFIX_0F52) },
2061   { PREFIX_TABLE (PREFIX_0F53) },
2062   { "andpX",            { XM, EXx } },
2063   { "andnpX",           { XM, EXx } },
2064   { "orpX",             { XM, EXx } },
2065   { "xorpX",            { XM, EXx } },
2066   /* 58 */
2067   { PREFIX_TABLE (PREFIX_0F58) },
2068   { PREFIX_TABLE (PREFIX_0F59) },
2069   { PREFIX_TABLE (PREFIX_0F5A) },
2070   { PREFIX_TABLE (PREFIX_0F5B) },
2071   { PREFIX_TABLE (PREFIX_0F5C) },
2072   { PREFIX_TABLE (PREFIX_0F5D) },
2073   { PREFIX_TABLE (PREFIX_0F5E) },
2074   { PREFIX_TABLE (PREFIX_0F5F) },
2075   /* 60 */
2076   { PREFIX_TABLE (PREFIX_0F60) },
2077   { PREFIX_TABLE (PREFIX_0F61) },
2078   { PREFIX_TABLE (PREFIX_0F62) },
2079   { "packsswb",         { MX, EM } },
2080   { "pcmpgtb",          { MX, EM } },
2081   { "pcmpgtw",          { MX, EM } },
2082   { "pcmpgtd",          { MX, EM } },
2083   { "packuswb",         { MX, EM } },
2084   /* 68 */
2085   { "punpckhbw",        { MX, EM } },
2086   { "punpckhwd",        { MX, EM } },
2087   { "punpckhdq",        { MX, EM } },
2088   { "packssdw",         { MX, EM } },
2089   { PREFIX_TABLE (PREFIX_0F6C) },
2090   { PREFIX_TABLE (PREFIX_0F6D) },
2091   { "movK",             { MX, Edq } },
2092   { PREFIX_TABLE (PREFIX_0F6F) },
2093   /* 70 */
2094   { PREFIX_TABLE (PREFIX_0F70) },
2095   { REG_TABLE (REG_0F71) },
2096   { REG_TABLE (REG_0F72) },
2097   { REG_TABLE (REG_0F73) },
2098   { "pcmpeqb",          { MX, EM } },
2099   { "pcmpeqw",          { MX, EM } },
2100   { "pcmpeqd",          { MX, EM } },
2101   { "emms",             { XX } },
2102   /* 78 */
2103   { PREFIX_TABLE (PREFIX_0F78) },
2104   { PREFIX_TABLE (PREFIX_0F79) },
2105   { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
2106   { Bad_Opcode },
2107   { PREFIX_TABLE (PREFIX_0F7C) },
2108   { PREFIX_TABLE (PREFIX_0F7D) },
2109   { PREFIX_TABLE (PREFIX_0F7E) },
2110   { PREFIX_TABLE (PREFIX_0F7F) },
2111   /* 80 */
2112   { "joH",              { Jv, XX, cond_jump_flag } },
2113   { "jnoH",             { Jv, XX, cond_jump_flag } },
2114   { "jbH",              { Jv, XX, cond_jump_flag } },
2115   { "jaeH",             { Jv, XX, cond_jump_flag } },
2116   { "jeH",              { Jv, XX, cond_jump_flag } },
2117   { "jneH",             { Jv, XX, cond_jump_flag } },
2118   { "jbeH",             { Jv, XX, cond_jump_flag } },
2119   { "jaH",              { Jv, XX, cond_jump_flag } },
2120   /* 88 */
2121   { "jsH",              { Jv, XX, cond_jump_flag } },
2122   { "jnsH",             { Jv, XX, cond_jump_flag } },
2123   { "jpH",              { Jv, XX, cond_jump_flag } },
2124   { "jnpH",             { Jv, XX, cond_jump_flag } },
2125   { "jlH",              { Jv, XX, cond_jump_flag } },
2126   { "jgeH",             { Jv, XX, cond_jump_flag } },
2127   { "jleH",             { Jv, XX, cond_jump_flag } },
2128   { "jgH",              { Jv, XX, cond_jump_flag } },
2129   /* 90 */
2130   { "seto",             { Eb } },
2131   { "setno",            { Eb } },
2132   { "setb",             { Eb } },
2133   { "setae",            { Eb } },
2134   { "sete",             { Eb } },
2135   { "setne",            { Eb } },
2136   { "setbe",            { Eb } },
2137   { "seta",             { Eb } },
2138   /* 98 */
2139   { "sets",             { Eb } },
2140   { "setns",            { Eb } },
2141   { "setp",             { Eb } },
2142   { "setnp",            { Eb } },
2143   { "setl",             { Eb } },
2144   { "setge",            { Eb } },
2145   { "setle",            { Eb } },
2146   { "setg",             { Eb } },
2147   /* a0 */
2148   { "pushT",            { fs } },
2149   { "popT",             { fs } },
2150   { "cpuid",            { XX } },
2151   { "btS",              { Ev, Gv } },
2152   { "shldS",            { Ev, Gv, Ib } },
2153   { "shldS",            { Ev, Gv, CL } },
2154   { REG_TABLE (REG_0FA6) },
2155   { REG_TABLE (REG_0FA7) },
2156   /* a8 */
2157   { "pushT",            { gs } },
2158   { "popT",             { gs } },
2159   { "rsm",              { XX } },
2160   { "btsS",             { Evh1, Gv } },
2161   { "shrdS",            { Ev, Gv, Ib } },
2162   { "shrdS",            { Ev, Gv, CL } },
2163   { REG_TABLE (REG_0FAE) },
2164   { "imulS",            { Gv, Ev } },
2165   /* b0 */
2166   { "cmpxchgB",         { Ebh1, Gb } },
2167   { "cmpxchgS",         { Evh1, Gv } },
2168   { MOD_TABLE (MOD_0FB2) },
2169   { "btrS",             { Evh1, Gv } },
2170   { MOD_TABLE (MOD_0FB4) },
2171   { MOD_TABLE (MOD_0FB5) },
2172   { "movz{bR|x}",       { Gv, Eb } },
2173   { "movz{wR|x}",       { Gv, Ew } }, /* yes, there really is movzww ! */
2174   /* b8 */
2175   { PREFIX_TABLE (PREFIX_0FB8) },
2176   { "ud1",              { XX } },
2177   { REG_TABLE (REG_0FBA) },
2178   { "btcS",             { Evh1, Gv } },
2179   { PREFIX_TABLE (PREFIX_0FBC) },
2180   { PREFIX_TABLE (PREFIX_0FBD) },
2181   { "movs{bR|x}",       { Gv, Eb } },
2182   { "movs{wR|x}",       { Gv, Ew } }, /* yes, there really is movsww ! */
2183   /* c0 */
2184   { "xaddB",            { Ebh1, Gb } },
2185   { "xaddS",            { Evh1, Gv } },
2186   { PREFIX_TABLE (PREFIX_0FC2) },
2187   { PREFIX_TABLE (PREFIX_0FC3) },
2188   { "pinsrw",           { MX, Edqw, Ib } },
2189   { "pextrw",           { Gdq, MS, Ib } },
2190   { "shufpX",           { XM, EXx, Ib } },
2191   { REG_TABLE (REG_0FC7) },
2192   /* c8 */
2193   { "bswap",            { RMeAX } },
2194   { "bswap",            { RMeCX } },
2195   { "bswap",            { RMeDX } },
2196   { "bswap",            { RMeBX } },
2197   { "bswap",            { RMeSP } },
2198   { "bswap",            { RMeBP } },
2199   { "bswap",            { RMeSI } },
2200   { "bswap",            { RMeDI } },
2201   /* d0 */
2202   { PREFIX_TABLE (PREFIX_0FD0) },
2203   { "psrlw",            { MX, EM } },
2204   { "psrld",            { MX, EM } },
2205   { "psrlq",            { MX, EM } },
2206   { "paddq",            { MX, EM } },
2207   { "pmullw",           { MX, EM } },
2208   { PREFIX_TABLE (PREFIX_0FD6) },
2209   { MOD_TABLE (MOD_0FD7) },
2210   /* d8 */
2211   { "psubusb",          { MX, EM } },
2212   { "psubusw",          { MX, EM } },
2213   { "pminub",           { MX, EM } },
2214   { "pand",             { MX, EM } },
2215   { "paddusb",          { MX, EM } },
2216   { "paddusw",          { MX, EM } },
2217   { "pmaxub",           { MX, EM } },
2218   { "pandn",            { MX, EM } },
2219   /* e0 */
2220   { "pavgb",            { MX, EM } },
2221   { "psraw",            { MX, EM } },
2222   { "psrad",            { MX, EM } },
2223   { "pavgw",            { MX, EM } },
2224   { "pmulhuw",          { MX, EM } },
2225   { "pmulhw",           { MX, EM } },
2226   { PREFIX_TABLE (PREFIX_0FE6) },
2227   { PREFIX_TABLE (PREFIX_0FE7) },
2228   /* e8 */
2229   { "psubsb",           { MX, EM } },
2230   { "psubsw",           { MX, EM } },
2231   { "pminsw",           { MX, EM } },
2232   { "por",              { MX, EM } },
2233   { "paddsb",           { MX, EM } },
2234   { "paddsw",           { MX, EM } },
2235   { "pmaxsw",           { MX, EM } },
2236   { "pxor",             { MX, EM } },
2237   /* f0 */
2238   { PREFIX_TABLE (PREFIX_0FF0) },
2239   { "psllw",            { MX, EM } },
2240   { "pslld",            { MX, EM } },
2241   { "psllq",            { MX, EM } },
2242   { "pmuludq",          { MX, EM } },
2243   { "pmaddwd",          { MX, EM } },
2244   { "psadbw",           { MX, EM } },
2245   { PREFIX_TABLE (PREFIX_0FF7) },
2246   /* f8 */
2247   { "psubb",            { MX, EM } },
2248   { "psubw",            { MX, EM } },
2249   { "psubd",            { MX, EM } },
2250   { "psubq",            { MX, EM } },
2251   { "paddb",            { MX, EM } },
2252   { "paddw",            { MX, EM } },
2253   { "paddd",            { MX, EM } },
2254   { Bad_Opcode },
2255 };
2256
2257 static const unsigned char onebyte_has_modrm[256] = {
2258   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2259   /*       -------------------------------        */
2260   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2261   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2262   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2263   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2264   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2265   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2266   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2267   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2268   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2269   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2270   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2271   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2272   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2273   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2274   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2275   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2276   /*       -------------------------------        */
2277   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2278 };
2279
2280 static const unsigned char twobyte_has_modrm[256] = {
2281   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2282   /*       -------------------------------        */
2283   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2284   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2285   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2286   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2287   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2288   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2289   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2290   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2291   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2292   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2293   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2294   /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
2295   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2296   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2297   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2298   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
2299   /*       -------------------------------        */
2300   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2301 };
2302
2303 static char obuf[100];
2304 static char *obufp;
2305 static char *mnemonicendp;
2306 static char scratchbuf[100];
2307 static unsigned char *start_codep;
2308 static unsigned char *insn_codep;
2309 static unsigned char *codep;
2310 static int last_lock_prefix;
2311 static int last_repz_prefix;
2312 static int last_repnz_prefix;
2313 static int last_data_prefix;
2314 static int last_addr_prefix;
2315 static int last_rex_prefix;
2316 static int last_seg_prefix;
2317 #define MAX_CODE_LENGTH 15
2318 /* We can up to 14 prefixes since the maximum instruction length is
2319    15bytes.  */
2320 static int all_prefixes[MAX_CODE_LENGTH - 1];
2321 static disassemble_info *the_info;
2322 static struct
2323   {
2324     int mod;
2325     int reg;
2326     int rm;
2327   }
2328 modrm;
2329 static unsigned char need_modrm;
2330 static struct
2331   {
2332     int scale;
2333     int index;
2334     int base;
2335   }
2336 sib;
2337 static struct
2338   {
2339     int register_specifier;
2340     int length;
2341     int prefix;
2342     int w;
2343   }
2344 vex;
2345 static unsigned char need_vex;
2346 static unsigned char need_vex_reg;
2347 static unsigned char vex_w_done;
2348
2349 struct op
2350   {
2351     const char *name;
2352     unsigned int len;
2353   };
2354
2355 /* If we are accessing mod/rm/reg without need_modrm set, then the
2356    values are stale.  Hitting this abort likely indicates that you
2357    need to update onebyte_has_modrm or twobyte_has_modrm.  */
2358 #define MODRM_CHECK  if (!need_modrm) abort ()
2359
2360 static const char **names64;
2361 static const char **names32;
2362 static const char **names16;
2363 static const char **names8;
2364 static const char **names8rex;
2365 static const char **names_seg;
2366 static const char *index64;
2367 static const char *index32;
2368 static const char **index16;
2369
2370 static const char *intel_names64[] = {
2371   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2372   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2373 };
2374 static const char *intel_names32[] = {
2375   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2376   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2377 };
2378 static const char *intel_names16[] = {
2379   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2380   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2381 };
2382 static const char *intel_names8[] = {
2383   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2384 };
2385 static const char *intel_names8rex[] = {
2386   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2387   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2388 };
2389 static const char *intel_names_seg[] = {
2390   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2391 };
2392 static const char *intel_index64 = "riz";
2393 static const char *intel_index32 = "eiz";
2394 static const char *intel_index16[] = {
2395   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2396 };
2397
2398 static const char *att_names64[] = {
2399   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2400   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2401 };
2402 static const char *att_names32[] = {
2403   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2404   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2405 };
2406 static const char *att_names16[] = {
2407   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2408   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2409 };
2410 static const char *att_names8[] = {
2411   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2412 };
2413 static const char *att_names8rex[] = {
2414   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2415   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2416 };
2417 static const char *att_names_seg[] = {
2418   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2419 };
2420 static const char *att_index64 = "%riz";
2421 static const char *att_index32 = "%eiz";
2422 static const char *att_index16[] = {
2423   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2424 };
2425
2426 static const char **names_mm;
2427 static const char *intel_names_mm[] = {
2428   "mm0", "mm1", "mm2", "mm3",
2429   "mm4", "mm5", "mm6", "mm7"
2430 };
2431 static const char *att_names_mm[] = {
2432   "%mm0", "%mm1", "%mm2", "%mm3",
2433   "%mm4", "%mm5", "%mm6", "%mm7"
2434 };
2435
2436 static const char **names_xmm;
2437 static const char *intel_names_xmm[] = {
2438   "xmm0", "xmm1", "xmm2", "xmm3",
2439   "xmm4", "xmm5", "xmm6", "xmm7",
2440   "xmm8", "xmm9", "xmm10", "xmm11",
2441   "xmm12", "xmm13", "xmm14", "xmm15"
2442 };
2443 static const char *att_names_xmm[] = {
2444   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2445   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2446   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2447   "%xmm12", "%xmm13", "%xmm14", "%xmm15"
2448 };
2449
2450 static const char **names_ymm;
2451 static const char *intel_names_ymm[] = {
2452   "ymm0", "ymm1", "ymm2", "ymm3",
2453   "ymm4", "ymm5", "ymm6", "ymm7",
2454   "ymm8", "ymm9", "ymm10", "ymm11",
2455   "ymm12", "ymm13", "ymm14", "ymm15"
2456 };
2457 static const char *att_names_ymm[] = {
2458   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2459   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2460   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2461   "%ymm12", "%ymm13", "%ymm14", "%ymm15"
2462 };
2463
2464 static const struct dis386 reg_table[][8] = {
2465   /* REG_80 */
2466   {
2467     { "addA",   { Ebh1, Ib } },
2468     { "orA",    { Ebh1, Ib } },
2469     { "adcA",   { Ebh1, Ib } },
2470     { "sbbA",   { Ebh1, Ib } },
2471     { "andA",   { Ebh1, Ib } },
2472     { "subA",   { Ebh1, Ib } },
2473     { "xorA",   { Ebh1, Ib } },
2474     { "cmpA",   { Eb, Ib } },
2475   },
2476   /* REG_81 */
2477   {
2478     { "addQ",   { Evh1, Iv } },
2479     { "orQ",    { Evh1, Iv } },
2480     { "adcQ",   { Evh1, Iv } },
2481     { "sbbQ",   { Evh1, Iv } },
2482     { "andQ",   { Evh1, Iv } },
2483     { "subQ",   { Evh1, Iv } },
2484     { "xorQ",   { Evh1, Iv } },
2485     { "cmpQ",   { Ev, Iv } },
2486   },
2487   /* REG_82 */
2488   {
2489     { "addQ",   { Evh1, sIb } },
2490     { "orQ",    { Evh1, sIb } },
2491     { "adcQ",   { Evh1, sIb } },
2492     { "sbbQ",   { Evh1, sIb } },
2493     { "andQ",   { Evh1, sIb } },
2494     { "subQ",   { Evh1, sIb } },
2495     { "xorQ",   { Evh1, sIb } },
2496     { "cmpQ",   { Ev, sIb } },
2497   },
2498   /* REG_8F */
2499   {
2500     { "popU",   { stackEv } },
2501     { XOP_8F_TABLE (XOP_09) },
2502     { Bad_Opcode },
2503     { Bad_Opcode },
2504     { Bad_Opcode },
2505     { XOP_8F_TABLE (XOP_09) },
2506   },
2507   /* REG_C0 */
2508   {
2509     { "rolA",   { Eb, Ib } },
2510     { "rorA",   { Eb, Ib } },
2511     { "rclA",   { Eb, Ib } },
2512     { "rcrA",   { Eb, Ib } },
2513     { "shlA",   { Eb, Ib } },
2514     { "shrA",   { Eb, Ib } },
2515     { Bad_Opcode },
2516     { "sarA",   { Eb, Ib } },
2517   },
2518   /* REG_C1 */
2519   {
2520     { "rolQ",   { Ev, Ib } },
2521     { "rorQ",   { Ev, Ib } },
2522     { "rclQ",   { Ev, Ib } },
2523     { "rcrQ",   { Ev, Ib } },
2524     { "shlQ",   { Ev, Ib } },
2525     { "shrQ",   { Ev, Ib } },
2526     { Bad_Opcode },
2527     { "sarQ",   { Ev, Ib } },
2528   },
2529   /* REG_C6 */
2530   {
2531     { "movA",   { Ebh3, Ib } },
2532     { Bad_Opcode },
2533     { Bad_Opcode },
2534     { Bad_Opcode },
2535     { Bad_Opcode },
2536     { Bad_Opcode },
2537     { Bad_Opcode },
2538     { MOD_TABLE (MOD_C6_REG_7) },
2539   },
2540   /* REG_C7 */
2541   {
2542     { "movQ",   { Evh3, Iv } },
2543     { Bad_Opcode },
2544     { Bad_Opcode },
2545     { Bad_Opcode },
2546     { Bad_Opcode },
2547     { Bad_Opcode },
2548     { Bad_Opcode },
2549     { MOD_TABLE (MOD_C7_REG_7) },
2550   },
2551   /* REG_D0 */
2552   {
2553     { "rolA",   { Eb, I1 } },
2554     { "rorA",   { Eb, I1 } },
2555     { "rclA",   { Eb, I1 } },
2556     { "rcrA",   { Eb, I1 } },
2557     { "shlA",   { Eb, I1 } },
2558     { "shrA",   { Eb, I1 } },
2559     { Bad_Opcode },
2560     { "sarA",   { Eb, I1 } },
2561   },
2562   /* REG_D1 */
2563   {
2564     { "rolQ",   { Ev, I1 } },
2565     { "rorQ",   { Ev, I1 } },
2566     { "rclQ",   { Ev, I1 } },
2567     { "rcrQ",   { Ev, I1 } },
2568     { "shlQ",   { Ev, I1 } },
2569     { "shrQ",   { Ev, I1 } },
2570     { Bad_Opcode },
2571     { "sarQ",   { Ev, I1 } },
2572   },
2573   /* REG_D2 */
2574   {
2575     { "rolA",   { Eb, CL } },
2576     { "rorA",   { Eb, CL } },
2577     { "rclA",   { Eb, CL } },
2578     { "rcrA",   { Eb, CL } },
2579     { "shlA",   { Eb, CL } },
2580     { "shrA",   { Eb, CL } },
2581     { Bad_Opcode },
2582     { "sarA",   { Eb, CL } },
2583   },
2584   /* REG_D3 */
2585   {
2586     { "rolQ",   { Ev, CL } },
2587     { "rorQ",   { Ev, CL } },
2588     { "rclQ",   { Ev, CL } },
2589     { "rcrQ",   { Ev, CL } },
2590     { "shlQ",   { Ev, CL } },
2591     { "shrQ",   { Ev, CL } },
2592     { Bad_Opcode },
2593     { "sarQ",   { Ev, CL } },
2594   },
2595   /* REG_F6 */
2596   {
2597     { "testA",  { Eb, Ib } },
2598     { Bad_Opcode },
2599     { "notA",   { Ebh1 } },
2600     { "negA",   { Ebh1 } },
2601     { "mulA",   { Eb } },       /* Don't print the implicit %al register,  */
2602     { "imulA",  { Eb } },       /* to distinguish these opcodes from other */
2603     { "divA",   { Eb } },       /* mul/imul opcodes.  Do the same for div  */
2604     { "idivA",  { Eb } },       /* and idiv for consistency.               */
2605   },
2606   /* REG_F7 */
2607   {
2608     { "testQ",  { Ev, Iv } },
2609     { Bad_Opcode },
2610     { "notQ",   { Evh1 } },
2611     { "negQ",   { Evh1 } },
2612     { "mulQ",   { Ev } },       /* Don't print the implicit register.  */
2613     { "imulQ",  { Ev } },
2614     { "divQ",   { Ev } },
2615     { "idivQ",  { Ev } },
2616   },
2617   /* REG_FE */
2618   {
2619     { "incA",   { Ebh1 } },
2620     { "decA",   { Ebh1 } },
2621   },
2622   /* REG_FF */
2623   {
2624     { "incQ",   { Evh1 } },
2625     { "decQ",   { Evh1 } },
2626     { "call{T|}", { indirEv } },
2627     { "Jcall{T|}", { indirEp } },
2628     { "jmp{T|}", { indirEv } },
2629     { "Jjmp{T|}", { indirEp } },
2630     { "pushU",  { stackEv } },
2631     { Bad_Opcode },
2632   },
2633   /* REG_0F00 */
2634   {
2635     { "sldtD",  { Sv } },
2636     { "strD",   { Sv } },
2637     { "lldt",   { Ew } },
2638     { "ltr",    { Ew } },
2639     { "verr",   { Ew } },
2640     { "verw",   { Ew } },
2641     { Bad_Opcode },
2642     { Bad_Opcode },
2643   },
2644   /* REG_0F01 */
2645   {
2646     { MOD_TABLE (MOD_0F01_REG_0) },
2647     { MOD_TABLE (MOD_0F01_REG_1) },
2648     { MOD_TABLE (MOD_0F01_REG_2) },
2649     { MOD_TABLE (MOD_0F01_REG_3) },
2650     { "smswD",  { Sv } },
2651     { Bad_Opcode },
2652     { "lmsw",   { Ew } },
2653     { MOD_TABLE (MOD_0F01_REG_7) },
2654   },
2655   /* REG_0F0D */
2656   {
2657     { "prefetch",       { Mb } },
2658     { "prefetchw",      { Mb } },
2659     { "prefetch",       { Mb } },
2660     { "prefetch",       { Mb } },
2661     { "prefetch",       { Mb } },
2662     { "prefetch",       { Mb } },
2663     { "prefetch",       { Mb } },
2664     { "prefetch",       { Mb } },
2665   },
2666   /* REG_0F18 */
2667   {
2668     { MOD_TABLE (MOD_0F18_REG_0) },
2669     { MOD_TABLE (MOD_0F18_REG_1) },
2670     { MOD_TABLE (MOD_0F18_REG_2) },
2671     { MOD_TABLE (MOD_0F18_REG_3) },
2672     { MOD_TABLE (MOD_0F18_REG_4) },
2673     { MOD_TABLE (MOD_0F18_REG_5) },
2674     { MOD_TABLE (MOD_0F18_REG_6) },
2675     { MOD_TABLE (MOD_0F18_REG_7) },
2676   },
2677   /* REG_0F71 */
2678   {
2679     { Bad_Opcode },
2680     { Bad_Opcode },
2681     { MOD_TABLE (MOD_0F71_REG_2) },
2682     { Bad_Opcode },
2683     { MOD_TABLE (MOD_0F71_REG_4) },
2684     { Bad_Opcode },
2685     { MOD_TABLE (MOD_0F71_REG_6) },
2686   },
2687   /* REG_0F72 */
2688   {
2689     { Bad_Opcode },
2690     { Bad_Opcode },
2691     { MOD_TABLE (MOD_0F72_REG_2) },
2692     { Bad_Opcode },
2693     { MOD_TABLE (MOD_0F72_REG_4) },
2694     { Bad_Opcode },
2695     { MOD_TABLE (MOD_0F72_REG_6) },
2696   },
2697   /* REG_0F73 */
2698   {
2699     { Bad_Opcode },
2700     { Bad_Opcode },
2701     { MOD_TABLE (MOD_0F73_REG_2) },
2702     { MOD_TABLE (MOD_0F73_REG_3) },
2703     { Bad_Opcode },
2704     { Bad_Opcode },
2705     { MOD_TABLE (MOD_0F73_REG_6) },
2706     { MOD_TABLE (MOD_0F73_REG_7) },
2707   },
2708   /* REG_0FA6 */
2709   {
2710     { "montmul",        { { OP_0f07, 0 } } },
2711     { "xsha1",          { { OP_0f07, 0 } } },
2712     { "xsha256",        { { OP_0f07, 0 } } },
2713   },
2714   /* REG_0FA7 */
2715   {
2716     { "xstore-rng",     { { OP_0f07, 0 } } },
2717     { "xcrypt-ecb",     { { OP_0f07, 0 } } },
2718     { "xcrypt-cbc",     { { OP_0f07, 0 } } },
2719     { "xcrypt-ctr",     { { OP_0f07, 0 } } },
2720     { "xcrypt-cfb",     { { OP_0f07, 0 } } },
2721     { "xcrypt-ofb",     { { OP_0f07, 0 } } },
2722   },
2723   /* REG_0FAE */
2724   {
2725     { MOD_TABLE (MOD_0FAE_REG_0) },
2726     { MOD_TABLE (MOD_0FAE_REG_1) },
2727     { MOD_TABLE (MOD_0FAE_REG_2) },
2728     { MOD_TABLE (MOD_0FAE_REG_3) },
2729     { MOD_TABLE (MOD_0FAE_REG_4) },
2730     { MOD_TABLE (MOD_0FAE_REG_5) },
2731     { MOD_TABLE (MOD_0FAE_REG_6) },
2732     { MOD_TABLE (MOD_0FAE_REG_7) },
2733   },
2734   /* REG_0FBA */
2735   {
2736     { Bad_Opcode },
2737     { Bad_Opcode },
2738     { Bad_Opcode },
2739     { Bad_Opcode },
2740     { "btQ",    { Ev, Ib } },
2741     { "btsQ",   { Evh1, Ib } },
2742     { "btrQ",   { Evh1, Ib } },
2743     { "btcQ",   { Evh1, Ib } },
2744   },
2745   /* REG_0FC7 */
2746   {
2747     { Bad_Opcode },
2748     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
2749     { Bad_Opcode },
2750     { Bad_Opcode },
2751     { Bad_Opcode },
2752     { Bad_Opcode },
2753     { MOD_TABLE (MOD_0FC7_REG_6) },
2754     { MOD_TABLE (MOD_0FC7_REG_7) },
2755   },
2756   /* REG_VEX_0F71 */
2757   {
2758     { Bad_Opcode },
2759     { Bad_Opcode },
2760     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
2761     { Bad_Opcode },
2762     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
2763     { Bad_Opcode },
2764     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
2765   },
2766   /* REG_VEX_0F72 */
2767   {
2768     { Bad_Opcode },
2769     { Bad_Opcode },
2770     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
2771     { Bad_Opcode },
2772     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
2773     { Bad_Opcode },
2774     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
2775   },
2776   /* REG_VEX_0F73 */
2777   {
2778     { Bad_Opcode },
2779     { Bad_Opcode },
2780     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
2781     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
2782     { Bad_Opcode },
2783     { Bad_Opcode },
2784     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
2785     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
2786   },
2787   /* REG_VEX_0FAE */
2788   {
2789     { Bad_Opcode },
2790     { Bad_Opcode },
2791     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
2792     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
2793   },
2794   /* REG_VEX_0F38F3 */
2795   {
2796     { Bad_Opcode },
2797     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
2798     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
2799     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
2800   },
2801   /* REG_XOP_LWPCB */
2802   {
2803     { "llwpcb", { { OP_LWPCB_E, 0 } } },
2804     { "slwpcb", { { OP_LWPCB_E, 0 } } },
2805   },
2806   /* REG_XOP_LWP */
2807   {
2808     { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq } },
2809     { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq } },
2810   },
2811   /* REG_XOP_TBM_01 */
2812   {
2813     { Bad_Opcode },
2814     { "blcfill",        { { OP_LWP_E, 0 }, Ev } },
2815     { "blsfill",        { { OP_LWP_E, 0 }, Ev } },
2816     { "blcs",   { { OP_LWP_E, 0 }, Ev } },
2817     { "tzmsk",  { { OP_LWP_E, 0 }, Ev } },
2818     { "blcic",  { { OP_LWP_E, 0 }, Ev } },
2819     { "blsic",  { { OP_LWP_E, 0 }, Ev } },
2820     { "t1mskc", { { OP_LWP_E, 0 }, Ev } },
2821   },
2822   /* REG_XOP_TBM_02 */
2823   {
2824     { Bad_Opcode },
2825     { "blcmsk", { { OP_LWP_E, 0 }, Ev } },
2826     { Bad_Opcode },
2827     { Bad_Opcode },
2828     { Bad_Opcode },
2829     { Bad_Opcode },
2830     { "blci",   { { OP_LWP_E, 0 }, Ev } },
2831   },
2832 };
2833
2834 static const struct dis386 prefix_table[][4] = {
2835   /* PREFIX_90 */
2836   {
2837     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2838     { "pause", { XX } },
2839     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2840   },
2841
2842   /* PREFIX_0F10 */
2843   {
2844     { "movups", { XM, EXx } },
2845     { "movss",  { XM, EXd } },
2846     { "movupd", { XM, EXx } },
2847     { "movsd",  { XM, EXq } },
2848   },
2849
2850   /* PREFIX_0F11 */
2851   {
2852     { "movups", { EXxS, XM } },
2853     { "movss",  { EXdS, XM } },
2854     { "movupd", { EXxS, XM } },
2855     { "movsd",  { EXqS, XM } },
2856   },
2857
2858   /* PREFIX_0F12 */
2859   {
2860     { MOD_TABLE (MOD_0F12_PREFIX_0) },
2861     { "movsldup", { XM, EXx } },
2862     { "movlpd", { XM, EXq } },
2863     { "movddup", { XM, EXq } },
2864   },
2865
2866   /* PREFIX_0F16 */
2867   {
2868     { MOD_TABLE (MOD_0F16_PREFIX_0) },
2869     { "movshdup", { XM, EXx } },
2870     { "movhpd", { XM, EXq } },
2871   },
2872
2873   /* PREFIX_0F2A */
2874   {
2875     { "cvtpi2ps", { XM, EMCq } },
2876     { "cvtsi2ss%LQ", { XM, Ev } },
2877     { "cvtpi2pd", { XM, EMCq } },
2878     { "cvtsi2sd%LQ", { XM, Ev } },
2879   },
2880
2881   /* PREFIX_0F2B */
2882   {
2883     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
2884     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
2885     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
2886     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
2887   },
2888
2889   /* PREFIX_0F2C */
2890   {
2891     { "cvttps2pi", { MXC, EXq } },
2892     { "cvttss2siY", { Gv, EXd } },
2893     { "cvttpd2pi", { MXC, EXx } },
2894     { "cvttsd2siY", { Gv, EXq } },
2895   },
2896
2897   /* PREFIX_0F2D */
2898   {
2899     { "cvtps2pi", { MXC, EXq } },
2900     { "cvtss2siY", { Gv, EXd } },
2901     { "cvtpd2pi", { MXC, EXx } },
2902     { "cvtsd2siY", { Gv, EXq } },
2903   },
2904
2905   /* PREFIX_0F2E */
2906   {
2907     { "ucomiss",{ XM, EXd } },
2908     { Bad_Opcode },
2909     { "ucomisd",{ XM, EXq } },
2910   },
2911
2912   /* PREFIX_0F2F */
2913   {
2914     { "comiss", { XM, EXd } },
2915     { Bad_Opcode },
2916     { "comisd", { XM, EXq } },
2917   },
2918
2919   /* PREFIX_0F51 */
2920   {
2921     { "sqrtps", { XM, EXx } },
2922     { "sqrtss", { XM, EXd } },
2923     { "sqrtpd", { XM, EXx } },
2924     { "sqrtsd", { XM, EXq } },
2925   },
2926
2927   /* PREFIX_0F52 */
2928   {
2929     { "rsqrtps",{ XM, EXx } },
2930     { "rsqrtss",{ XM, EXd } },
2931   },
2932
2933   /* PREFIX_0F53 */
2934   {
2935     { "rcpps",  { XM, EXx } },
2936     { "rcpss",  { XM, EXd } },
2937   },
2938
2939   /* PREFIX_0F58 */
2940   {
2941     { "addps", { XM, EXx } },
2942     { "addss", { XM, EXd } },
2943     { "addpd", { XM, EXx } },
2944     { "addsd", { XM, EXq } },
2945   },
2946
2947   /* PREFIX_0F59 */
2948   {
2949     { "mulps",  { XM, EXx } },
2950     { "mulss",  { XM, EXd } },
2951     { "mulpd",  { XM, EXx } },
2952     { "mulsd",  { XM, EXq } },
2953   },
2954
2955   /* PREFIX_0F5A */
2956   {
2957     { "cvtps2pd", { XM, EXq } },
2958     { "cvtss2sd", { XM, EXd } },
2959     { "cvtpd2ps", { XM, EXx } },
2960     { "cvtsd2ss", { XM, EXq } },
2961   },
2962
2963   /* PREFIX_0F5B */
2964   {
2965     { "cvtdq2ps", { XM, EXx } },
2966     { "cvttps2dq", { XM, EXx } },
2967     { "cvtps2dq", { XM, EXx } },
2968   },
2969
2970   /* PREFIX_0F5C */
2971   {
2972     { "subps",  { XM, EXx } },
2973     { "subss",  { XM, EXd } },
2974     { "subpd",  { XM, EXx } },
2975     { "subsd",  { XM, EXq } },
2976   },
2977
2978   /* PREFIX_0F5D */
2979   {
2980     { "minps",  { XM, EXx } },
2981     { "minss",  { XM, EXd } },
2982     { "minpd",  { XM, EXx } },
2983     { "minsd",  { XM, EXq } },
2984   },
2985
2986   /* PREFIX_0F5E */
2987   {
2988     { "divps",  { XM, EXx } },
2989     { "divss",  { XM, EXd } },
2990     { "divpd",  { XM, EXx } },
2991     { "divsd",  { XM, EXq } },
2992   },
2993
2994   /* PREFIX_0F5F */
2995   {
2996     { "maxps",  { XM, EXx } },
2997     { "maxss",  { XM, EXd } },
2998     { "maxpd",  { XM, EXx } },
2999     { "maxsd",  { XM, EXq } },
3000   },
3001
3002   /* PREFIX_0F60 */
3003   {
3004     { "punpcklbw",{ MX, EMd } },
3005     { Bad_Opcode },
3006     { "punpcklbw",{ MX, EMx } },
3007   },
3008
3009   /* PREFIX_0F61 */
3010   {
3011     { "punpcklwd",{ MX, EMd } },
3012     { Bad_Opcode },
3013     { "punpcklwd",{ MX, EMx } },
3014   },
3015
3016   /* PREFIX_0F62 */
3017   {
3018     { "punpckldq",{ MX, EMd } },
3019     { Bad_Opcode },
3020     { "punpckldq",{ MX, EMx } },
3021   },
3022
3023   /* PREFIX_0F6C */
3024   {
3025     { Bad_Opcode },
3026     { Bad_Opcode },
3027     { "punpcklqdq", { XM, EXx } },
3028   },
3029
3030   /* PREFIX_0F6D */
3031   {
3032     { Bad_Opcode },
3033     { Bad_Opcode },
3034     { "punpckhqdq", { XM, EXx } },
3035   },
3036
3037   /* PREFIX_0F6F */
3038   {
3039     { "movq",   { MX, EM } },
3040     { "movdqu", { XM, EXx } },
3041     { "movdqa", { XM, EXx } },
3042   },
3043
3044   /* PREFIX_0F70 */
3045   {
3046     { "pshufw", { MX, EM, Ib } },
3047     { "pshufhw",{ XM, EXx, Ib } },
3048     { "pshufd", { XM, EXx, Ib } },
3049     { "pshuflw",{ XM, EXx, Ib } },
3050   },
3051
3052   /* PREFIX_0F73_REG_3 */
3053   {
3054     { Bad_Opcode },
3055     { Bad_Opcode },
3056     { "psrldq", { XS, Ib } },
3057   },
3058
3059   /* PREFIX_0F73_REG_7 */
3060   {
3061     { Bad_Opcode },
3062     { Bad_Opcode },
3063     { "pslldq", { XS, Ib } },
3064   },
3065
3066   /* PREFIX_0F78 */
3067   {
3068     {"vmread",  { Em, Gm } },
3069     { Bad_Opcode },
3070     {"extrq",   { XS, Ib, Ib } },
3071     {"insertq", { XM, XS, Ib, Ib } },
3072   },
3073
3074   /* PREFIX_0F79 */
3075   {
3076     {"vmwrite", { Gm, Em } },
3077     { Bad_Opcode },
3078     {"extrq",   { XM, XS } },
3079     {"insertq", { XM, XS } },
3080   },
3081
3082   /* PREFIX_0F7C */
3083   {
3084     { Bad_Opcode },
3085     { Bad_Opcode },
3086     { "haddpd", { XM, EXx } },
3087     { "haddps", { XM, EXx } },
3088   },
3089
3090   /* PREFIX_0F7D */
3091   {
3092     { Bad_Opcode },
3093     { Bad_Opcode },
3094     { "hsubpd", { XM, EXx } },
3095     { "hsubps", { XM, EXx } },
3096   },
3097
3098   /* PREFIX_0F7E */
3099   {
3100     { "movK",   { Edq, MX } },
3101     { "movq",   { XM, EXq } },
3102     { "movK",   { Edq, XM } },
3103   },
3104
3105   /* PREFIX_0F7F */
3106   {
3107     { "movq",   { EMS, MX } },
3108     { "movdqu", { EXxS, XM } },
3109     { "movdqa", { EXxS, XM } },
3110   },
3111
3112   /* PREFIX_0FAE_REG_0 */
3113   {
3114     { Bad_Opcode },
3115     { "rdfsbase", { Ev } },
3116   },
3117
3118   /* PREFIX_0FAE_REG_1 */
3119   {
3120     { Bad_Opcode },
3121     { "rdgsbase", { Ev } },
3122   },
3123
3124   /* PREFIX_0FAE_REG_2 */
3125   {
3126     { Bad_Opcode },
3127     { "wrfsbase", { Ev } },
3128   },
3129
3130   /* PREFIX_0FAE_REG_3 */
3131   {
3132     { Bad_Opcode },
3133     { "wrgsbase", { Ev } },
3134   },
3135
3136   /* PREFIX_0FB8 */
3137   {
3138     { Bad_Opcode },
3139     { "popcntS", { Gv, Ev } },
3140   },
3141
3142   /* PREFIX_0FBC */
3143   {
3144     { "bsfS",   { Gv, Ev } },
3145     { "tzcntS", { Gv, Ev } },
3146     { "bsfS",   { Gv, Ev } },
3147   },
3148
3149   /* PREFIX_0FBD */
3150   {
3151     { "bsrS",   { Gv, Ev } },
3152     { "lzcntS", { Gv, Ev } },
3153     { "bsrS",   { Gv, Ev } },
3154   },
3155
3156   /* PREFIX_0FC2 */
3157   {
3158     { "cmpps",  { XM, EXx, CMP } },
3159     { "cmpss",  { XM, EXd, CMP } },
3160     { "cmppd",  { XM, EXx, CMP } },
3161     { "cmpsd",  { XM, EXq, CMP } },
3162   },
3163
3164   /* PREFIX_0FC3 */
3165   {
3166     { "movntiS", { Ma, Gv } },
3167   },
3168
3169   /* PREFIX_0FC7_REG_6 */
3170   {
3171     { "vmptrld",{ Mq } },
3172     { "vmxon",  { Mq } },
3173     { "vmclear",{ Mq } },
3174   },
3175
3176   /* PREFIX_0FD0 */
3177   {
3178     { Bad_Opcode },
3179     { Bad_Opcode },
3180     { "addsubpd", { XM, EXx } },
3181     { "addsubps", { XM, EXx } },
3182   },
3183
3184   /* PREFIX_0FD6 */
3185   {
3186     { Bad_Opcode },
3187     { "movq2dq",{ XM, MS } },
3188     { "movq",   { EXqS, XM } },
3189     { "movdq2q",{ MX, XS } },
3190   },
3191
3192   /* PREFIX_0FE6 */
3193   {
3194     { Bad_Opcode },
3195     { "cvtdq2pd", { XM, EXq } },
3196     { "cvttpd2dq", { XM, EXx } },
3197     { "cvtpd2dq", { XM, EXx } },
3198   },
3199
3200   /* PREFIX_0FE7 */
3201   {
3202     { "movntq", { Mq, MX } },
3203     { Bad_Opcode },
3204     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
3205   },
3206
3207   /* PREFIX_0FF0 */
3208   {
3209     { Bad_Opcode },
3210     { Bad_Opcode },
3211     { Bad_Opcode },
3212     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
3213   },
3214
3215   /* PREFIX_0FF7 */
3216   {
3217     { "maskmovq", { MX, MS } },
3218     { Bad_Opcode },
3219     { "maskmovdqu", { XM, XS } },
3220   },
3221
3222   /* PREFIX_0F3810 */
3223   {
3224     { Bad_Opcode },
3225     { Bad_Opcode },
3226     { "pblendvb", { XM, EXx, XMM0 } },
3227   },
3228
3229   /* PREFIX_0F3814 */
3230   {
3231     { Bad_Opcode },
3232     { Bad_Opcode },
3233     { "blendvps", { XM, EXx, XMM0 } },
3234   },
3235
3236   /* PREFIX_0F3815 */
3237   {
3238     { Bad_Opcode },
3239     { Bad_Opcode },
3240     { "blendvpd", { XM, EXx, XMM0 } },
3241   },
3242
3243   /* PREFIX_0F3817 */
3244   {
3245     { Bad_Opcode },
3246     { Bad_Opcode },
3247     { "ptest",  { XM, EXx } },
3248   },
3249
3250   /* PREFIX_0F3820 */
3251   {
3252     { Bad_Opcode },
3253     { Bad_Opcode },
3254     { "pmovsxbw", { XM, EXq } },
3255   },
3256
3257   /* PREFIX_0F3821 */
3258   {
3259     { Bad_Opcode },
3260     { Bad_Opcode },
3261     { "pmovsxbd", { XM, EXd } },
3262   },
3263
3264   /* PREFIX_0F3822 */
3265   {
3266     { Bad_Opcode },
3267     { Bad_Opcode },
3268     { "pmovsxbq", { XM, EXw } },
3269   },
3270
3271   /* PREFIX_0F3823 */
3272   {
3273     { Bad_Opcode },
3274     { Bad_Opcode },
3275     { "pmovsxwd", { XM, EXq } },
3276   },
3277
3278   /* PREFIX_0F3824 */
3279   {
3280     { Bad_Opcode },
3281     { Bad_Opcode },
3282     { "pmovsxwq", { XM, EXd } },
3283   },
3284
3285   /* PREFIX_0F3825 */
3286   {
3287     { Bad_Opcode },
3288     { Bad_Opcode },
3289     { "pmovsxdq", { XM, EXq } },
3290   },
3291
3292   /* PREFIX_0F3828 */
3293   {
3294     { Bad_Opcode },
3295     { Bad_Opcode },
3296     { "pmuldq", { XM, EXx } },
3297   },
3298
3299   /* PREFIX_0F3829 */
3300   {
3301     { Bad_Opcode },
3302     { Bad_Opcode },
3303     { "pcmpeqq", { XM, EXx } },
3304   },
3305
3306   /* PREFIX_0F382A */
3307   {
3308     { Bad_Opcode },
3309     { Bad_Opcode },
3310     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
3311   },
3312
3313   /* PREFIX_0F382B */
3314   {
3315     { Bad_Opcode },
3316     { Bad_Opcode },
3317     { "packusdw", { XM, EXx } },
3318   },
3319
3320   /* PREFIX_0F3830 */
3321   {
3322     { Bad_Opcode },
3323     { Bad_Opcode },
3324     { "pmovzxbw", { XM, EXq } },
3325   },
3326
3327   /* PREFIX_0F3831 */
3328   {
3329     { Bad_Opcode },
3330     { Bad_Opcode },
3331     { "pmovzxbd", { XM, EXd } },
3332   },
3333
3334   /* PREFIX_0F3832 */
3335   {
3336     { Bad_Opcode },
3337     { Bad_Opcode },
3338     { "pmovzxbq", { XM, EXw } },
3339   },
3340
3341   /* PREFIX_0F3833 */
3342   {
3343     { Bad_Opcode },
3344     { Bad_Opcode },
3345     { "pmovzxwd", { XM, EXq } },
3346   },
3347
3348   /* PREFIX_0F3834 */
3349   {
3350     { Bad_Opcode },
3351     { Bad_Opcode },
3352     { "pmovzxwq", { XM, EXd } },
3353   },
3354
3355   /* PREFIX_0F3835 */
3356   {
3357     { Bad_Opcode },
3358     { Bad_Opcode },
3359     { "pmovzxdq", { XM, EXq } },
3360   },
3361
3362   /* PREFIX_0F3837 */
3363   {
3364     { Bad_Opcode },
3365     { Bad_Opcode },
3366     { "pcmpgtq", { XM, EXx } },
3367   },
3368
3369   /* PREFIX_0F3838 */
3370   {
3371     { Bad_Opcode },
3372     { Bad_Opcode },
3373     { "pminsb", { XM, EXx } },
3374   },
3375
3376   /* PREFIX_0F3839 */
3377   {
3378     { Bad_Opcode },
3379     { Bad_Opcode },
3380     { "pminsd", { XM, EXx } },
3381   },
3382
3383   /* PREFIX_0F383A */
3384   {
3385     { Bad_Opcode },
3386     { Bad_Opcode },
3387     { "pminuw", { XM, EXx } },
3388   },
3389
3390   /* PREFIX_0F383B */
3391   {
3392     { Bad_Opcode },
3393     { Bad_Opcode },
3394     { "pminud", { XM, EXx } },
3395   },
3396
3397   /* PREFIX_0F383C */
3398   {
3399     { Bad_Opcode },
3400     { Bad_Opcode },
3401     { "pmaxsb", { XM, EXx } },
3402   },
3403
3404   /* PREFIX_0F383D */
3405   {
3406     { Bad_Opcode },
3407     { Bad_Opcode },
3408     { "pmaxsd", { XM, EXx } },
3409   },
3410
3411   /* PREFIX_0F383E */
3412   {
3413     { Bad_Opcode },
3414     { Bad_Opcode },
3415     { "pmaxuw", { XM, EXx } },
3416   },
3417
3418   /* PREFIX_0F383F */
3419   {
3420     { Bad_Opcode },
3421     { Bad_Opcode },
3422     { "pmaxud", { XM, EXx } },
3423   },
3424
3425   /* PREFIX_0F3840 */
3426   {
3427     { Bad_Opcode },
3428     { Bad_Opcode },
3429     { "pmulld", { XM, EXx } },
3430   },
3431
3432   /* PREFIX_0F3841 */
3433   {
3434     { Bad_Opcode },
3435     { Bad_Opcode },
3436     { "phminposuw", { XM, EXx } },
3437   },
3438
3439   /* PREFIX_0F3880 */
3440   {
3441     { Bad_Opcode },
3442     { Bad_Opcode },
3443     { "invept", { Gm, Mo } },
3444   },
3445
3446   /* PREFIX_0F3881 */
3447   {
3448     { Bad_Opcode },
3449     { Bad_Opcode },
3450     { "invvpid", { Gm, Mo } },
3451   },
3452
3453   /* PREFIX_0F3882 */
3454   {
3455     { Bad_Opcode },
3456     { Bad_Opcode },
3457     { "invpcid", { Gm, M } },
3458   },
3459
3460   /* PREFIX_0F38DB */
3461   {
3462     { Bad_Opcode },
3463     { Bad_Opcode },
3464     { "aesimc", { XM, EXx } },
3465   },
3466
3467   /* PREFIX_0F38DC */
3468   {
3469     { Bad_Opcode },
3470     { Bad_Opcode },
3471     { "aesenc", { XM, EXx } },
3472   },
3473
3474   /* PREFIX_0F38DD */
3475   {
3476     { Bad_Opcode },
3477     { Bad_Opcode },
3478     { "aesenclast", { XM, EXx } },
3479   },
3480
3481   /* PREFIX_0F38DE */
3482   {
3483     { Bad_Opcode },
3484     { Bad_Opcode },
3485     { "aesdec", { XM, EXx } },
3486   },
3487
3488   /* PREFIX_0F38DF */
3489   {
3490     { Bad_Opcode },
3491     { Bad_Opcode },
3492     { "aesdeclast", { XM, EXx } },
3493   },
3494
3495   /* PREFIX_0F38F0 */
3496   {
3497     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
3498     { Bad_Opcode },
3499     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
3500     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } } },
3501   },
3502
3503   /* PREFIX_0F38F1 */
3504   {
3505     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
3506     { Bad_Opcode },
3507     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
3508     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } } },
3509   },
3510
3511   /* PREFIX_0F38F6 */
3512   {
3513     { Bad_Opcode },
3514     { "adoxS",  { Gdq, Edq} },
3515     { "adcxS",  { Gdq, Edq} },
3516     { Bad_Opcode },
3517   },
3518
3519   /* PREFIX_0F3A08 */
3520   {
3521     { Bad_Opcode },
3522     { Bad_Opcode },
3523     { "roundps", { XM, EXx, Ib } },
3524   },
3525
3526   /* PREFIX_0F3A09 */
3527   {
3528     { Bad_Opcode },
3529     { Bad_Opcode },
3530     { "roundpd", { XM, EXx, Ib } },
3531   },
3532
3533   /* PREFIX_0F3A0A */
3534   {
3535     { Bad_Opcode },
3536     { Bad_Opcode },
3537     { "roundss", { XM, EXd, Ib } },
3538   },
3539
3540   /* PREFIX_0F3A0B */
3541   {
3542     { Bad_Opcode },
3543     { Bad_Opcode },
3544     { "roundsd", { XM, EXq, Ib } },
3545   },
3546
3547   /* PREFIX_0F3A0C */
3548   {
3549     { Bad_Opcode },
3550     { Bad_Opcode },
3551     { "blendps", { XM, EXx, Ib } },
3552   },
3553
3554   /* PREFIX_0F3A0D */
3555   {
3556     { Bad_Opcode },
3557     { Bad_Opcode },
3558     { "blendpd", { XM, EXx, Ib } },
3559   },
3560
3561   /* PREFIX_0F3A0E */
3562   {
3563     { Bad_Opcode },
3564     { Bad_Opcode },
3565     { "pblendw", { XM, EXx, Ib } },
3566   },
3567
3568   /* PREFIX_0F3A14 */
3569   {
3570     { Bad_Opcode },
3571     { Bad_Opcode },
3572     { "pextrb", { Edqb, XM, Ib } },
3573   },
3574
3575   /* PREFIX_0F3A15 */
3576   {
3577     { Bad_Opcode },
3578     { Bad_Opcode },
3579     { "pextrw", { Edqw, XM, Ib } },
3580   },
3581
3582   /* PREFIX_0F3A16 */
3583   {
3584     { Bad_Opcode },
3585     { Bad_Opcode },
3586     { "pextrK", { Edq, XM, Ib } },
3587   },
3588
3589   /* PREFIX_0F3A17 */
3590   {
3591     { Bad_Opcode },
3592     { Bad_Opcode },
3593     { "extractps", { Edqd, XM, Ib } },
3594   },
3595
3596   /* PREFIX_0F3A20 */
3597   {
3598     { Bad_Opcode },
3599     { Bad_Opcode },
3600     { "pinsrb", { XM, Edqb, Ib } },
3601   },
3602
3603   /* PREFIX_0F3A21 */
3604   {
3605     { Bad_Opcode },
3606     { Bad_Opcode },
3607     { "insertps", { XM, EXd, Ib } },
3608   },
3609
3610   /* PREFIX_0F3A22 */
3611   {
3612     { Bad_Opcode },
3613     { Bad_Opcode },
3614     { "pinsrK", { XM, Edq, Ib } },
3615   },
3616
3617   /* PREFIX_0F3A40 */
3618   {
3619     { Bad_Opcode },
3620     { Bad_Opcode },
3621     { "dpps",   { XM, EXx, Ib } },
3622   },
3623
3624   /* PREFIX_0F3A41 */
3625   {
3626     { Bad_Opcode },
3627     { Bad_Opcode },
3628     { "dppd",   { XM, EXx, Ib } },
3629   },
3630
3631   /* PREFIX_0F3A42 */
3632   {
3633     { Bad_Opcode },
3634     { Bad_Opcode },
3635     { "mpsadbw", { XM, EXx, Ib } },
3636   },
3637
3638   /* PREFIX_0F3A44 */
3639   {
3640     { Bad_Opcode },
3641     { Bad_Opcode },
3642     { "pclmulqdq", { XM, EXx, PCLMUL } },
3643   },
3644
3645   /* PREFIX_0F3A60 */
3646   {
3647     { Bad_Opcode },
3648     { Bad_Opcode },
3649     { "pcmpestrm", { XM, EXx, Ib } },
3650   },
3651
3652   /* PREFIX_0F3A61 */
3653   {
3654     { Bad_Opcode },
3655     { Bad_Opcode },
3656     { "pcmpestri", { XM, EXx, Ib } },
3657   },
3658
3659   /* PREFIX_0F3A62 */
3660   {
3661     { Bad_Opcode },
3662     { Bad_Opcode },
3663     { "pcmpistrm", { XM, EXx, Ib } },
3664   },
3665
3666   /* PREFIX_0F3A63 */
3667   {
3668     { Bad_Opcode },
3669     { Bad_Opcode },
3670     { "pcmpistri", { XM, EXx, Ib } },
3671   },
3672
3673   /* PREFIX_0F3ADF */
3674   {
3675     { Bad_Opcode },
3676     { Bad_Opcode },
3677     { "aeskeygenassist", { XM, EXx, Ib } },
3678   },
3679
3680   /* PREFIX_VEX_0F10 */
3681   {
3682     { VEX_W_TABLE (VEX_W_0F10_P_0) },
3683     { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
3684     { VEX_W_TABLE (VEX_W_0F10_P_2) },
3685     { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
3686   },
3687
3688   /* PREFIX_VEX_0F11 */
3689   {
3690     { VEX_W_TABLE (VEX_W_0F11_P_0) },
3691     { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
3692     { VEX_W_TABLE (VEX_W_0F11_P_2) },
3693     { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
3694   },
3695
3696   /* PREFIX_VEX_0F12 */
3697   {
3698     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
3699     { VEX_W_TABLE (VEX_W_0F12_P_1) },
3700     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
3701     { VEX_W_TABLE (VEX_W_0F12_P_3) },
3702   },
3703
3704   /* PREFIX_VEX_0F16 */
3705   {
3706     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
3707     { VEX_W_TABLE (VEX_W_0F16_P_1) },
3708     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
3709   },
3710
3711   /* PREFIX_VEX_0F2A */
3712   {
3713     { Bad_Opcode },
3714     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
3715     { Bad_Opcode },
3716     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
3717   },
3718
3719   /* PREFIX_VEX_0F2C */
3720   {
3721     { Bad_Opcode },
3722     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
3723     { Bad_Opcode },
3724     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
3725   },
3726
3727   /* PREFIX_VEX_0F2D */
3728   {
3729     { Bad_Opcode },
3730     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
3731     { Bad_Opcode },
3732     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
3733   },
3734
3735   /* PREFIX_VEX_0F2E */
3736   {
3737     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
3738     { Bad_Opcode },
3739     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
3740   },
3741
3742   /* PREFIX_VEX_0F2F */
3743   {
3744     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
3745     { Bad_Opcode },
3746     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
3747   },
3748
3749   /* PREFIX_VEX_0F51 */
3750   {
3751     { VEX_W_TABLE (VEX_W_0F51_P_0) },
3752     { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
3753     { VEX_W_TABLE (VEX_W_0F51_P_2) },
3754     { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
3755   },
3756
3757   /* PREFIX_VEX_0F52 */
3758   {
3759     { VEX_W_TABLE (VEX_W_0F52_P_0) },
3760     { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
3761   },
3762
3763   /* PREFIX_VEX_0F53 */
3764   {
3765     { VEX_W_TABLE (VEX_W_0F53_P_0) },
3766     { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
3767   },
3768
3769   /* PREFIX_VEX_0F58 */
3770   {
3771     { VEX_W_TABLE (VEX_W_0F58_P_0) },
3772     { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
3773     { VEX_W_TABLE (VEX_W_0F58_P_2) },
3774     { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
3775   },
3776
3777   /* PREFIX_VEX_0F59 */
3778   {
3779     { VEX_W_TABLE (VEX_W_0F59_P_0) },
3780     { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
3781     { VEX_W_TABLE (VEX_W_0F59_P_2) },
3782     { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
3783   },
3784
3785   /* PREFIX_VEX_0F5A */
3786   {
3787     { VEX_W_TABLE (VEX_W_0F5A_P_0) },
3788     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
3789     { "vcvtpd2ps%XY", { XMM, EXx } },
3790     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
3791   },
3792
3793   /* PREFIX_VEX_0F5B */
3794   {
3795     { VEX_W_TABLE (VEX_W_0F5B_P_0) },
3796     { VEX_W_TABLE (VEX_W_0F5B_P_1) },
3797     { VEX_W_TABLE (VEX_W_0F5B_P_2) },
3798   },
3799
3800   /* PREFIX_VEX_0F5C */
3801   {
3802     { VEX_W_TABLE (VEX_W_0F5C_P_0) },
3803     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
3804     { VEX_W_TABLE (VEX_W_0F5C_P_2) },
3805     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
3806   },
3807
3808   /* PREFIX_VEX_0F5D */
3809   {
3810     { VEX_W_TABLE (VEX_W_0F5D_P_0) },
3811     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
3812     { VEX_W_TABLE (VEX_W_0F5D_P_2) },
3813     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
3814   },
3815
3816   /* PREFIX_VEX_0F5E */
3817   {
3818     { VEX_W_TABLE (VEX_W_0F5E_P_0) },
3819     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
3820     { VEX_W_TABLE (VEX_W_0F5E_P_2) },
3821     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
3822   },
3823
3824   /* PREFIX_VEX_0F5F */
3825   {
3826     { VEX_W_TABLE (VEX_W_0F5F_P_0) },
3827     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
3828     { VEX_W_TABLE (VEX_W_0F5F_P_2) },
3829     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
3830   },
3831
3832   /* PREFIX_VEX_0F60 */
3833   {
3834     { Bad_Opcode },
3835     { Bad_Opcode },
3836     { VEX_W_TABLE (VEX_W_0F60_P_2) },
3837   },
3838
3839   /* PREFIX_VEX_0F61 */
3840   {
3841     { Bad_Opcode },
3842     { Bad_Opcode },
3843     { VEX_W_TABLE (VEX_W_0F61_P_2) },
3844   },
3845
3846   /* PREFIX_VEX_0F62 */
3847   {
3848     { Bad_Opcode },
3849     { Bad_Opcode },
3850     { VEX_W_TABLE (VEX_W_0F62_P_2) },
3851   },
3852
3853   /* PREFIX_VEX_0F63 */
3854   {
3855     { Bad_Opcode },
3856     { Bad_Opcode },
3857     { VEX_W_TABLE (VEX_W_0F63_P_2) },
3858   },
3859
3860   /* PREFIX_VEX_0F64 */
3861   {
3862     { Bad_Opcode },
3863     { Bad_Opcode },
3864     { VEX_W_TABLE (VEX_W_0F64_P_2) },
3865   },
3866
3867   /* PREFIX_VEX_0F65 */
3868   {
3869     { Bad_Opcode },
3870     { Bad_Opcode },
3871     { VEX_W_TABLE (VEX_W_0F65_P_2) },
3872   },
3873
3874   /* PREFIX_VEX_0F66 */
3875   {
3876     { Bad_Opcode },
3877     { Bad_Opcode },
3878     { VEX_W_TABLE (VEX_W_0F66_P_2) },
3879   },
3880
3881   /* PREFIX_VEX_0F67 */
3882   {
3883     { Bad_Opcode },
3884     { Bad_Opcode },
3885     { VEX_W_TABLE (VEX_W_0F67_P_2) },
3886   },
3887
3888   /* PREFIX_VEX_0F68 */
3889   {
3890     { Bad_Opcode },
3891     { Bad_Opcode },
3892     { VEX_W_TABLE (VEX_W_0F68_P_2) },
3893   },
3894
3895   /* PREFIX_VEX_0F69 */
3896   {
3897     { Bad_Opcode },
3898     { Bad_Opcode },
3899     { VEX_W_TABLE (VEX_W_0F69_P_2) },
3900   },
3901
3902   /* PREFIX_VEX_0F6A */
3903   {
3904     { Bad_Opcode },
3905     { Bad_Opcode },
3906     { VEX_W_TABLE (VEX_W_0F6A_P_2) },
3907   },
3908
3909   /* PREFIX_VEX_0F6B */
3910   {
3911     { Bad_Opcode },
3912     { Bad_Opcode },
3913     { VEX_W_TABLE (VEX_W_0F6B_P_2) },
3914   },
3915
3916   /* PREFIX_VEX_0F6C */
3917   {
3918     { Bad_Opcode },
3919     { Bad_Opcode },
3920     { VEX_W_TABLE (VEX_W_0F6C_P_2) },
3921   },
3922
3923   /* PREFIX_VEX_0F6D */
3924   {
3925     { Bad_Opcode },
3926     { Bad_Opcode },
3927     { VEX_W_TABLE (VEX_W_0F6D_P_2) },
3928   },
3929
3930   /* PREFIX_VEX_0F6E */
3931   {
3932     { Bad_Opcode },
3933     { Bad_Opcode },
3934     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
3935   },
3936
3937   /* PREFIX_VEX_0F6F */
3938   {
3939     { Bad_Opcode },
3940     { VEX_W_TABLE (VEX_W_0F6F_P_1) },
3941     { VEX_W_TABLE (VEX_W_0F6F_P_2) },
3942   },
3943
3944   /* PREFIX_VEX_0F70 */
3945   {
3946     { Bad_Opcode },
3947     { VEX_W_TABLE (VEX_W_0F70_P_1) },
3948     { VEX_W_TABLE (VEX_W_0F70_P_2) },
3949     { VEX_W_TABLE (VEX_W_0F70_P_3) },
3950   },
3951
3952   /* PREFIX_VEX_0F71_REG_2 */
3953   {
3954     { Bad_Opcode },
3955     { Bad_Opcode },
3956     { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
3957   },
3958
3959   /* PREFIX_VEX_0F71_REG_4 */
3960   {
3961     { Bad_Opcode },
3962     { Bad_Opcode },
3963     { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
3964   },
3965
3966   /* PREFIX_VEX_0F71_REG_6 */
3967   {
3968     { Bad_Opcode },
3969     { Bad_Opcode },
3970     { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
3971   },
3972
3973   /* PREFIX_VEX_0F72_REG_2 */
3974   {
3975     { Bad_Opcode },
3976     { Bad_Opcode },
3977     { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
3978   },
3979
3980   /* PREFIX_VEX_0F72_REG_4 */
3981   {
3982     { Bad_Opcode },
3983     { Bad_Opcode },
3984     { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
3985   },
3986
3987   /* PREFIX_VEX_0F72_REG_6 */
3988   {
3989     { Bad_Opcode },
3990     { Bad_Opcode },
3991     { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
3992   },
3993
3994   /* PREFIX_VEX_0F73_REG_2 */
3995   {
3996     { Bad_Opcode },
3997     { Bad_Opcode },
3998     { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
3999   },
4000
4001   /* PREFIX_VEX_0F73_REG_3 */
4002   {
4003     { Bad_Opcode },
4004     { Bad_Opcode },
4005     { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
4006   },
4007
4008   /* PREFIX_VEX_0F73_REG_6 */
4009   {
4010     { Bad_Opcode },
4011     { Bad_Opcode },
4012     { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
4013   },
4014
4015   /* PREFIX_VEX_0F73_REG_7 */
4016   {
4017     { Bad_Opcode },
4018     { Bad_Opcode },
4019     { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
4020   },
4021
4022   /* PREFIX_VEX_0F74 */
4023   {
4024     { Bad_Opcode },
4025     { Bad_Opcode },
4026     { VEX_W_TABLE (VEX_W_0F74_P_2) },
4027   },
4028
4029   /* PREFIX_VEX_0F75 */
4030   {
4031     { Bad_Opcode },
4032     { Bad_Opcode },
4033     { VEX_W_TABLE (VEX_W_0F75_P_2) },
4034   },
4035
4036   /* PREFIX_VEX_0F76 */
4037   {
4038     { Bad_Opcode },
4039     { Bad_Opcode },
4040     { VEX_W_TABLE (VEX_W_0F76_P_2) },
4041   },
4042
4043   /* PREFIX_VEX_0F77 */
4044   {
4045     { VEX_W_TABLE (VEX_W_0F77_P_0) },
4046   },
4047
4048   /* PREFIX_VEX_0F7C */
4049   {
4050     { Bad_Opcode },
4051     { Bad_Opcode },
4052     { VEX_W_TABLE (VEX_W_0F7C_P_2) },
4053     { VEX_W_TABLE (VEX_W_0F7C_P_3) },
4054   },
4055
4056   /* PREFIX_VEX_0F7D */
4057   {
4058     { Bad_Opcode },
4059     { Bad_Opcode },
4060     { VEX_W_TABLE (VEX_W_0F7D_P_2) },
4061     { VEX_W_TABLE (VEX_W_0F7D_P_3) },
4062   },
4063
4064   /* PREFIX_VEX_0F7E */
4065   {
4066     { Bad_Opcode },
4067     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
4068     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
4069   },
4070
4071   /* PREFIX_VEX_0F7F */
4072   {
4073     { Bad_Opcode },
4074     { VEX_W_TABLE (VEX_W_0F7F_P_1) },
4075     { VEX_W_TABLE (VEX_W_0F7F_P_2) },
4076   },
4077
4078   /* PREFIX_VEX_0FC2 */
4079   {
4080     { VEX_W_TABLE (VEX_W_0FC2_P_0) },
4081     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
4082     { VEX_W_TABLE (VEX_W_0FC2_P_2) },
4083     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
4084   },
4085
4086   /* PREFIX_VEX_0FC4 */
4087   {
4088     { Bad_Opcode },
4089     { Bad_Opcode },
4090     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
4091   },
4092
4093   /* PREFIX_VEX_0FC5 */
4094   {
4095     { Bad_Opcode },
4096     { Bad_Opcode },
4097     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
4098   },
4099
4100   /* PREFIX_VEX_0FD0 */
4101   {
4102     { Bad_Opcode },
4103     { Bad_Opcode },
4104     { VEX_W_TABLE (VEX_W_0FD0_P_2) },
4105     { VEX_W_TABLE (VEX_W_0FD0_P_3) },
4106   },
4107
4108   /* PREFIX_VEX_0FD1 */
4109   {
4110     { Bad_Opcode },
4111     { Bad_Opcode },
4112     { VEX_W_TABLE (VEX_W_0FD1_P_2) },
4113   },
4114
4115   /* PREFIX_VEX_0FD2 */
4116   {
4117     { Bad_Opcode },
4118     { Bad_Opcode },
4119     { VEX_W_TABLE (VEX_W_0FD2_P_2) },
4120   },
4121
4122   /* PREFIX_VEX_0FD3 */
4123   {
4124     { Bad_Opcode },
4125     { Bad_Opcode },
4126     { VEX_W_TABLE (VEX_W_0FD3_P_2) },
4127   },
4128
4129   /* PREFIX_VEX_0FD4 */
4130   {
4131     { Bad_Opcode },
4132     { Bad_Opcode },
4133     { VEX_W_TABLE (VEX_W_0FD4_P_2) },
4134   },
4135
4136   /* PREFIX_VEX_0FD5 */
4137   {
4138     { Bad_Opcode },
4139     { Bad_Opcode },
4140     { VEX_W_TABLE (VEX_W_0FD5_P_2) },
4141   },
4142
4143   /* PREFIX_VEX_0FD6 */
4144   {
4145     { Bad_Opcode },
4146     { Bad_Opcode },
4147     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
4148   },
4149
4150   /* PREFIX_VEX_0FD7 */
4151   {
4152     { Bad_Opcode },
4153     { Bad_Opcode },
4154     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
4155   },
4156
4157   /* PREFIX_VEX_0FD8 */
4158   {
4159     { Bad_Opcode },
4160     { Bad_Opcode },
4161     { VEX_W_TABLE (VEX_W_0FD8_P_2) },
4162   },
4163
4164   /* PREFIX_VEX_0FD9 */
4165   {
4166     { Bad_Opcode },
4167     { Bad_Opcode },
4168     { VEX_W_TABLE (VEX_W_0FD9_P_2) },
4169   },
4170
4171   /* PREFIX_VEX_0FDA */
4172   {
4173     { Bad_Opcode },
4174     { Bad_Opcode },
4175     { VEX_W_TABLE (VEX_W_0FDA_P_2) },
4176   },
4177
4178   /* PREFIX_VEX_0FDB */
4179   {
4180     { Bad_Opcode },
4181     { Bad_Opcode },
4182     { VEX_W_TABLE (VEX_W_0FDB_P_2) },
4183   },
4184
4185   /* PREFIX_VEX_0FDC */
4186   {
4187     { Bad_Opcode },
4188     { Bad_Opcode },
4189     { VEX_W_TABLE (VEX_W_0FDC_P_2) },
4190   },
4191
4192   /* PREFIX_VEX_0FDD */
4193   {
4194     { Bad_Opcode },
4195     { Bad_Opcode },
4196     { VEX_W_TABLE (VEX_W_0FDD_P_2) },
4197   },
4198
4199   /* PREFIX_VEX_0FDE */
4200   {
4201     { Bad_Opcode },
4202     { Bad_Opcode },
4203     { VEX_W_TABLE (VEX_W_0FDE_P_2) },
4204   },
4205
4206   /* PREFIX_VEX_0FDF */
4207   {
4208     { Bad_Opcode },
4209     { Bad_Opcode },
4210     { VEX_W_TABLE (VEX_W_0FDF_P_2) },
4211   },
4212
4213   /* PREFIX_VEX_0FE0 */
4214   {
4215     { Bad_Opcode },
4216     { Bad_Opcode },
4217     { VEX_W_TABLE (VEX_W_0FE0_P_2) },
4218   },
4219
4220   /* PREFIX_VEX_0FE1 */
4221   {
4222     { Bad_Opcode },
4223     { Bad_Opcode },
4224     { VEX_W_TABLE (VEX_W_0FE1_P_2) },
4225   },
4226
4227   /* PREFIX_VEX_0FE2 */
4228   {
4229     { Bad_Opcode },
4230     { Bad_Opcode },
4231     { VEX_W_TABLE (VEX_W_0FE2_P_2) },
4232   },
4233
4234   /* PREFIX_VEX_0FE3 */
4235   {
4236     { Bad_Opcode },
4237     { Bad_Opcode },
4238     { VEX_W_TABLE (VEX_W_0FE3_P_2) },
4239   },
4240
4241   /* PREFIX_VEX_0FE4 */
4242   {
4243     { Bad_Opcode },
4244     { Bad_Opcode },
4245     { VEX_W_TABLE (VEX_W_0FE4_P_2) },
4246   },
4247
4248   /* PREFIX_VEX_0FE5 */
4249   {
4250     { Bad_Opcode },
4251     { Bad_Opcode },
4252     { VEX_W_TABLE (VEX_W_0FE5_P_2) },
4253   },
4254
4255   /* PREFIX_VEX_0FE6 */
4256   {
4257     { Bad_Opcode },
4258     { VEX_W_TABLE (VEX_W_0FE6_P_1) },
4259     { VEX_W_TABLE (VEX_W_0FE6_P_2) },
4260     { VEX_W_TABLE (VEX_W_0FE6_P_3) },
4261   },
4262
4263   /* PREFIX_VEX_0FE7 */
4264   {
4265     { Bad_Opcode },
4266     { Bad_Opcode },
4267     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
4268   },
4269
4270   /* PREFIX_VEX_0FE8 */
4271   {
4272     { Bad_Opcode },
4273     { Bad_Opcode },
4274     { VEX_W_TABLE (VEX_W_0FE8_P_2) },
4275   },
4276
4277   /* PREFIX_VEX_0FE9 */
4278   {
4279     { Bad_Opcode },
4280     { Bad_Opcode },
4281     { VEX_W_TABLE (VEX_W_0FE9_P_2) },
4282   },
4283
4284   /* PREFIX_VEX_0FEA */
4285   {
4286     { Bad_Opcode },
4287     { Bad_Opcode },
4288     { VEX_W_TABLE (VEX_W_0FEA_P_2) },
4289   },
4290
4291   /* PREFIX_VEX_0FEB */
4292   {
4293     { Bad_Opcode },
4294     { Bad_Opcode },
4295     { VEX_W_TABLE (VEX_W_0FEB_P_2) },
4296   },
4297
4298   /* PREFIX_VEX_0FEC */
4299   {
4300     { Bad_Opcode },
4301     { Bad_Opcode },
4302     { VEX_W_TABLE (VEX_W_0FEC_P_2) },
4303   },
4304
4305   /* PREFIX_VEX_0FED */
4306   {
4307     { Bad_Opcode },
4308     { Bad_Opcode },
4309     { VEX_W_TABLE (VEX_W_0FED_P_2) },
4310   },
4311
4312   /* PREFIX_VEX_0FEE */
4313   {
4314     { Bad_Opcode },
4315     { Bad_Opcode },
4316     { VEX_W_TABLE (VEX_W_0FEE_P_2) },
4317   },
4318
4319   /* PREFIX_VEX_0FEF */
4320   {
4321     { Bad_Opcode },
4322     { Bad_Opcode },
4323     { VEX_W_TABLE (VEX_W_0FEF_P_2) },
4324   },
4325
4326   /* PREFIX_VEX_0FF0 */
4327   {
4328     { Bad_Opcode },
4329     { Bad_Opcode },
4330     { Bad_Opcode },
4331     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
4332   },
4333
4334   /* PREFIX_VEX_0FF1 */
4335   {
4336     { Bad_Opcode },
4337     { Bad_Opcode },
4338     { VEX_W_TABLE (VEX_W_0FF1_P_2) },
4339   },
4340
4341   /* PREFIX_VEX_0FF2 */
4342   {
4343     { Bad_Opcode },
4344     { Bad_Opcode },
4345     { VEX_W_TABLE (VEX_W_0FF2_P_2) },
4346   },
4347
4348   /* PREFIX_VEX_0FF3 */
4349   {
4350     { Bad_Opcode },
4351     { Bad_Opcode },
4352     { VEX_W_TABLE (VEX_W_0FF3_P_2) },
4353   },
4354
4355   /* PREFIX_VEX_0FF4 */
4356   {
4357     { Bad_Opcode },
4358     { Bad_Opcode },
4359     { VEX_W_TABLE (VEX_W_0FF4_P_2) },
4360   },
4361
4362   /* PREFIX_VEX_0FF5 */
4363   {
4364     { Bad_Opcode },
4365     { Bad_Opcode },
4366     { VEX_W_TABLE (VEX_W_0FF5_P_2) },
4367   },
4368
4369   /* PREFIX_VEX_0FF6 */
4370   {
4371     { Bad_Opcode },
4372     { Bad_Opcode },
4373     { VEX_W_TABLE (VEX_W_0FF6_P_2) },
4374   },
4375
4376   /* PREFIX_VEX_0FF7 */
4377   {
4378     { Bad_Opcode },
4379     { Bad_Opcode },
4380     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
4381   },
4382
4383   /* PREFIX_VEX_0FF8 */
4384   {
4385     { Bad_Opcode },
4386     { Bad_Opcode },
4387     { VEX_W_TABLE (VEX_W_0FF8_P_2) },
4388   },
4389
4390   /* PREFIX_VEX_0FF9 */
4391   {
4392     { Bad_Opcode },
4393     { Bad_Opcode },
4394     { VEX_W_TABLE (VEX_W_0FF9_P_2) },
4395   },
4396
4397   /* PREFIX_VEX_0FFA */
4398   {
4399     { Bad_Opcode },
4400     { Bad_Opcode },
4401     { VEX_W_TABLE (VEX_W_0FFA_P_2) },
4402   },
4403
4404   /* PREFIX_VEX_0FFB */
4405   {
4406     { Bad_Opcode },
4407     { Bad_Opcode },
4408     { VEX_W_TABLE (VEX_W_0FFB_P_2) },
4409   },
4410
4411   /* PREFIX_VEX_0FFC */
4412   {
4413     { Bad_Opcode },
4414     { Bad_Opcode },
4415     { VEX_W_TABLE (VEX_W_0FFC_P_2) },
4416   },
4417
4418   /* PREFIX_VEX_0FFD */
4419   {
4420     { Bad_Opcode },
4421     { Bad_Opcode },
4422     { VEX_W_TABLE (VEX_W_0FFD_P_2) },
4423   },
4424
4425   /* PREFIX_VEX_0FFE */
4426   {
4427     { Bad_Opcode },
4428     { Bad_Opcode },
4429     { VEX_W_TABLE (VEX_W_0FFE_P_2) },
4430   },
4431
4432   /* PREFIX_VEX_0F3800 */
4433   {
4434     { Bad_Opcode },
4435     { Bad_Opcode },
4436     { VEX_W_TABLE (VEX_W_0F3800_P_2) },
4437   },
4438
4439   /* PREFIX_VEX_0F3801 */
4440   {
4441     { Bad_Opcode },
4442     { Bad_Opcode },
4443     { VEX_W_TABLE (VEX_W_0F3801_P_2) },
4444   },
4445
4446   /* PREFIX_VEX_0F3802 */
4447   {
4448     { Bad_Opcode },
4449     { Bad_Opcode },
4450     { VEX_W_TABLE (VEX_W_0F3802_P_2) },
4451   },
4452
4453   /* PREFIX_VEX_0F3803 */
4454   {
4455     { Bad_Opcode },
4456     { Bad_Opcode },
4457     { VEX_W_TABLE (VEX_W_0F3803_P_2) },
4458   },
4459
4460   /* PREFIX_VEX_0F3804 */
4461   {
4462     { Bad_Opcode },
4463     { Bad_Opcode },
4464     { VEX_W_TABLE (VEX_W_0F3804_P_2) },
4465   },
4466
4467   /* PREFIX_VEX_0F3805 */
4468   {
4469     { Bad_Opcode },
4470     { Bad_Opcode },
4471     { VEX_W_TABLE (VEX_W_0F3805_P_2) },
4472   },
4473
4474   /* PREFIX_VEX_0F3806 */
4475   {
4476     { Bad_Opcode },
4477     { Bad_Opcode },
4478     { VEX_W_TABLE (VEX_W_0F3806_P_2) },
4479   },
4480
4481   /* PREFIX_VEX_0F3807 */
4482   {
4483     { Bad_Opcode },
4484     { Bad_Opcode },
4485     { VEX_W_TABLE (VEX_W_0F3807_P_2) },
4486   },
4487
4488   /* PREFIX_VEX_0F3808 */
4489   {
4490     { Bad_Opcode },
4491     { Bad_Opcode },
4492     { VEX_W_TABLE (VEX_W_0F3808_P_2) },
4493   },
4494
4495   /* PREFIX_VEX_0F3809 */
4496   {
4497     { Bad_Opcode },
4498     { Bad_Opcode },
4499     { VEX_W_TABLE (VEX_W_0F3809_P_2) },
4500   },
4501
4502   /* PREFIX_VEX_0F380A */
4503   {
4504     { Bad_Opcode },
4505     { Bad_Opcode },
4506     { VEX_W_TABLE (VEX_W_0F380A_P_2) },
4507   },
4508
4509   /* PREFIX_VEX_0F380B */
4510   {
4511     { Bad_Opcode },
4512     { Bad_Opcode },
4513     { VEX_W_TABLE (VEX_W_0F380B_P_2) },
4514   },
4515
4516   /* PREFIX_VEX_0F380C */
4517   {
4518     { Bad_Opcode },
4519     { Bad_Opcode },
4520     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
4521   },
4522
4523   /* PREFIX_VEX_0F380D */
4524   {
4525     { Bad_Opcode },
4526     { Bad_Opcode },
4527     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
4528   },
4529
4530   /* PREFIX_VEX_0F380E */
4531   {
4532     { Bad_Opcode },
4533     { Bad_Opcode },
4534     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
4535   },
4536
4537   /* PREFIX_VEX_0F380F */
4538   {
4539     { Bad_Opcode },
4540     { Bad_Opcode },
4541     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
4542   },
4543
4544   /* PREFIX_VEX_0F3813 */
4545   {
4546     { Bad_Opcode },
4547     { Bad_Opcode },
4548     { "vcvtph2ps", { XM, EXxmmq } },
4549   },
4550
4551   /* PREFIX_VEX_0F3816 */
4552   {
4553     { Bad_Opcode },
4554     { Bad_Opcode },
4555     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
4556   },
4557
4558   /* PREFIX_VEX_0F3817 */
4559   {
4560     { Bad_Opcode },
4561     { Bad_Opcode },
4562     { VEX_W_TABLE (VEX_W_0F3817_P_2) },
4563   },
4564
4565   /* PREFIX_VEX_0F3818 */
4566   {
4567     { Bad_Opcode },
4568     { Bad_Opcode },
4569     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
4570   },
4571
4572   /* PREFIX_VEX_0F3819 */
4573   {
4574     { Bad_Opcode },
4575     { Bad_Opcode },
4576     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
4577   },
4578
4579   /* PREFIX_VEX_0F381A */
4580   {
4581     { Bad_Opcode },
4582     { Bad_Opcode },
4583     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
4584   },
4585
4586   /* PREFIX_VEX_0F381C */
4587   {
4588     { Bad_Opcode },
4589     { Bad_Opcode },
4590     { VEX_W_TABLE (VEX_W_0F381C_P_2) },
4591   },
4592
4593   /* PREFIX_VEX_0F381D */
4594   {
4595     { Bad_Opcode },
4596     { Bad_Opcode },
4597     { VEX_W_TABLE (VEX_W_0F381D_P_2) },
4598   },
4599
4600   /* PREFIX_VEX_0F381E */
4601   {
4602     { Bad_Opcode },
4603     { Bad_Opcode },
4604     { VEX_W_TABLE (VEX_W_0F381E_P_2) },
4605   },
4606
4607   /* PREFIX_VEX_0F3820 */
4608   {
4609     { Bad_Opcode },
4610     { Bad_Opcode },
4611     { VEX_W_TABLE (VEX_W_0F3820_P_2) },
4612   },
4613
4614   /* PREFIX_VEX_0F3821 */
4615   {
4616     { Bad_Opcode },
4617     { Bad_Opcode },
4618     { VEX_W_TABLE (VEX_W_0F3821_P_2) },
4619   },
4620
4621   /* PREFIX_VEX_0F3822 */
4622   {
4623     { Bad_Opcode },
4624     { Bad_Opcode },
4625     { VEX_W_TABLE (VEX_W_0F3822_P_2) },
4626   },
4627
4628   /* PREFIX_VEX_0F3823 */
4629   {
4630     { Bad_Opcode },
4631     { Bad_Opcode },
4632     { VEX_W_TABLE (VEX_W_0F3823_P_2) },
4633   },
4634
4635   /* PREFIX_VEX_0F3824 */
4636   {
4637     { Bad_Opcode },
4638     { Bad_Opcode },
4639     { VEX_W_TABLE (VEX_W_0F3824_P_2) },
4640   },
4641
4642   /* PREFIX_VEX_0F3825 */
4643   {
4644     { Bad_Opcode },
4645     { Bad_Opcode },
4646     { VEX_W_TABLE (VEX_W_0F3825_P_2) },
4647   },
4648
4649   /* PREFIX_VEX_0F3828 */
4650   {
4651     { Bad_Opcode },
4652     { Bad_Opcode },
4653     { VEX_W_TABLE (VEX_W_0F3828_P_2) },
4654   },
4655
4656   /* PREFIX_VEX_0F3829 */
4657   {
4658     { Bad_Opcode },
4659     { Bad_Opcode },
4660     { VEX_W_TABLE (VEX_W_0F3829_P_2) },
4661   },
4662
4663   /* PREFIX_VEX_0F382A */
4664   {
4665     { Bad_Opcode },
4666     { Bad_Opcode },
4667     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
4668   },
4669
4670   /* PREFIX_VEX_0F382B */
4671   {
4672     { Bad_Opcode },
4673     { Bad_Opcode },
4674     { VEX_W_TABLE (VEX_W_0F382B_P_2) },
4675   },
4676
4677   /* PREFIX_VEX_0F382C */
4678   {
4679     { Bad_Opcode },
4680     { Bad_Opcode },
4681      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
4682   },
4683
4684   /* PREFIX_VEX_0F382D */
4685   {
4686     { Bad_Opcode },
4687     { Bad_Opcode },
4688      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
4689   },
4690
4691   /* PREFIX_VEX_0F382E */
4692   {
4693     { Bad_Opcode },
4694     { Bad_Opcode },
4695      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
4696   },
4697
4698   /* PREFIX_VEX_0F382F */
4699   {
4700     { Bad_Opcode },
4701     { Bad_Opcode },
4702      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
4703   },
4704
4705   /* PREFIX_VEX_0F3830 */
4706   {
4707     { Bad_Opcode },
4708     { Bad_Opcode },
4709     { VEX_W_TABLE (VEX_W_0F3830_P_2) },
4710   },
4711
4712   /* PREFIX_VEX_0F3831 */
4713   {
4714     { Bad_Opcode },
4715     { Bad_Opcode },
4716     { VEX_W_TABLE (VEX_W_0F3831_P_2) },
4717   },
4718
4719   /* PREFIX_VEX_0F3832 */
4720   {
4721     { Bad_Opcode },
4722     { Bad_Opcode },
4723     { VEX_W_TABLE (VEX_W_0F3832_P_2) },
4724   },
4725
4726   /* PREFIX_VEX_0F3833 */
4727   {
4728     { Bad_Opcode },
4729     { Bad_Opcode },
4730     { VEX_W_TABLE (VEX_W_0F3833_P_2) },
4731   },
4732
4733   /* PREFIX_VEX_0F3834 */
4734   {
4735     { Bad_Opcode },
4736     { Bad_Opcode },
4737     { VEX_W_TABLE (VEX_W_0F3834_P_2) },
4738   },
4739
4740   /* PREFIX_VEX_0F3835 */
4741   {
4742     { Bad_Opcode },
4743     { Bad_Opcode },
4744     { VEX_W_TABLE (VEX_W_0F3835_P_2) },
4745   },
4746
4747   /* PREFIX_VEX_0F3836 */
4748   {
4749     { Bad_Opcode },
4750     { Bad_Opcode },
4751     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
4752   },
4753
4754   /* PREFIX_VEX_0F3837 */
4755   {
4756     { Bad_Opcode },
4757     { Bad_Opcode },
4758     { VEX_W_TABLE (VEX_W_0F3837_P_2) },
4759   },
4760
4761   /* PREFIX_VEX_0F3838 */
4762   {
4763     { Bad_Opcode },
4764     { Bad_Opcode },
4765     { VEX_W_TABLE (VEX_W_0F3838_P_2) },
4766   },
4767
4768   /* PREFIX_VEX_0F3839 */
4769   {
4770     { Bad_Opcode },
4771     { Bad_Opcode },
4772     { VEX_W_TABLE (VEX_W_0F3839_P_2) },
4773   },
4774
4775   /* PREFIX_VEX_0F383A */
4776   {
4777     { Bad_Opcode },
4778     { Bad_Opcode },
4779     { VEX_W_TABLE (VEX_W_0F383A_P_2) },
4780   },
4781
4782   /* PREFIX_VEX_0F383B */
4783   {
4784     { Bad_Opcode },
4785     { Bad_Opcode },
4786     { VEX_W_TABLE (VEX_W_0F383B_P_2) },
4787   },
4788
4789   /* PREFIX_VEX_0F383C */
4790   {
4791     { Bad_Opcode },
4792     { Bad_Opcode },
4793     { VEX_W_TABLE (VEX_W_0F383C_P_2) },
4794   },
4795
4796   /* PREFIX_VEX_0F383D */
4797   {
4798     { Bad_Opcode },
4799     { Bad_Opcode },
4800     { VEX_W_TABLE (VEX_W_0F383D_P_2) },
4801   },
4802
4803   /* PREFIX_VEX_0F383E */
4804   {
4805     { Bad_Opcode },
4806     { Bad_Opcode },
4807     { VEX_W_TABLE (VEX_W_0F383E_P_2) },
4808   },
4809
4810   /* PREFIX_VEX_0F383F */
4811   {
4812     { Bad_Opcode },
4813     { Bad_Opcode },
4814     { VEX_W_TABLE (VEX_W_0F383F_P_2) },
4815   },
4816
4817   /* PREFIX_VEX_0F3840 */
4818   {
4819     { Bad_Opcode },
4820     { Bad_Opcode },
4821     { VEX_W_TABLE (VEX_W_0F3840_P_2) },
4822   },
4823
4824   /* PREFIX_VEX_0F3841 */
4825   {
4826     { Bad_Opcode },
4827     { Bad_Opcode },
4828     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
4829   },
4830
4831   /* PREFIX_VEX_0F3845 */
4832   {
4833     { Bad_Opcode },
4834     { Bad_Opcode },
4835     { "vpsrlv%LW", { XM, Vex, EXx } },
4836   },
4837
4838   /* PREFIX_VEX_0F3846 */
4839   {
4840     { Bad_Opcode },
4841     { Bad_Opcode },
4842     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
4843   },
4844
4845   /* PREFIX_VEX_0F3847 */
4846   {
4847     { Bad_Opcode },
4848     { Bad_Opcode },
4849     { "vpsllv%LW", { XM, Vex, EXx } },
4850   },
4851
4852   /* PREFIX_VEX_0F3858 */
4853   {
4854     { Bad_Opcode },
4855     { Bad_Opcode },
4856     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
4857   },
4858
4859   /* PREFIX_VEX_0F3859 */
4860   {
4861     { Bad_Opcode },
4862     { Bad_Opcode },
4863     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
4864   },
4865
4866   /* PREFIX_VEX_0F385A */
4867   {
4868     { Bad_Opcode },
4869     { Bad_Opcode },
4870     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
4871   },
4872
4873   /* PREFIX_VEX_0F3878 */
4874   {
4875     { Bad_Opcode },
4876     { Bad_Opcode },
4877     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
4878   },
4879
4880   /* PREFIX_VEX_0F3879 */
4881   {
4882     { Bad_Opcode },
4883     { Bad_Opcode },
4884     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
4885   },
4886
4887   /* PREFIX_VEX_0F388C */
4888   {
4889     { Bad_Opcode },
4890     { Bad_Opcode },
4891     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
4892   },
4893
4894   /* PREFIX_VEX_0F388E */
4895   {
4896     { Bad_Opcode },
4897     { Bad_Opcode },
4898     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
4899   },
4900
4901   /* PREFIX_VEX_0F3890 */
4902   {
4903     { Bad_Opcode },
4904     { Bad_Opcode },
4905     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex } },
4906   },
4907
4908   /* PREFIX_VEX_0F3891 */
4909   {
4910     { Bad_Opcode },
4911     { Bad_Opcode },
4912     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } },
4913   },
4914
4915   /* PREFIX_VEX_0F3892 */
4916   {
4917     { Bad_Opcode },
4918     { Bad_Opcode },
4919     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex } },
4920   },
4921
4922   /* PREFIX_VEX_0F3893 */
4923   {
4924     { Bad_Opcode },
4925     { Bad_Opcode },
4926     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } },
4927   },
4928
4929   /* PREFIX_VEX_0F3896 */
4930   {
4931     { Bad_Opcode },
4932     { Bad_Opcode },
4933     { "vfmaddsub132p%XW", { XM, Vex, EXx } },
4934   },
4935
4936   /* PREFIX_VEX_0F3897 */
4937   {
4938     { Bad_Opcode },
4939     { Bad_Opcode },
4940     { "vfmsubadd132p%XW", { XM, Vex, EXx } },
4941   },
4942
4943   /* PREFIX_VEX_0F3898 */
4944   {
4945     { Bad_Opcode },
4946     { Bad_Opcode },
4947     { "vfmadd132p%XW", { XM, Vex, EXx } },
4948   },
4949
4950   /* PREFIX_VEX_0F3899 */
4951   {
4952     { Bad_Opcode },
4953     { Bad_Opcode },
4954     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4955   },
4956
4957   /* PREFIX_VEX_0F389A */
4958   {
4959     { Bad_Opcode },
4960     { Bad_Opcode },
4961     { "vfmsub132p%XW", { XM, Vex, EXx } },
4962   },
4963
4964   /* PREFIX_VEX_0F389B */
4965   {
4966     { Bad_Opcode },
4967     { Bad_Opcode },
4968     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4969   },
4970
4971   /* PREFIX_VEX_0F389C */
4972   {
4973     { Bad_Opcode },
4974     { Bad_Opcode },
4975     { "vfnmadd132p%XW", { XM, Vex, EXx } },
4976   },
4977
4978   /* PREFIX_VEX_0F389D */
4979   {
4980     { Bad_Opcode },
4981     { Bad_Opcode },
4982     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4983   },
4984
4985   /* PREFIX_VEX_0F389E */
4986   {
4987     { Bad_Opcode },
4988     { Bad_Opcode },
4989     { "vfnmsub132p%XW", { XM, Vex, EXx } },
4990   },
4991
4992   /* PREFIX_VEX_0F389F */
4993   {
4994     { Bad_Opcode },
4995     { Bad_Opcode },
4996     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4997   },
4998
4999   /* PREFIX_VEX_0F38A6 */
5000   {
5001     { Bad_Opcode },
5002     { Bad_Opcode },
5003     { "vfmaddsub213p%XW", { XM, Vex, EXx } },
5004     { Bad_Opcode },
5005   },
5006
5007   /* PREFIX_VEX_0F38A7 */
5008   {
5009     { Bad_Opcode },
5010     { Bad_Opcode },
5011     { "vfmsubadd213p%XW", { XM, Vex, EXx } },
5012   },
5013
5014   /* PREFIX_VEX_0F38A8 */
5015   {
5016     { Bad_Opcode },
5017     { Bad_Opcode },
5018     { "vfmadd213p%XW", { XM, Vex, EXx } },
5019   },
5020
5021   /* PREFIX_VEX_0F38A9 */
5022   {
5023     { Bad_Opcode },
5024     { Bad_Opcode },
5025     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5026   },
5027
5028   /* PREFIX_VEX_0F38AA */
5029   {
5030     { Bad_Opcode },
5031     { Bad_Opcode },
5032     { "vfmsub213p%XW", { XM, Vex, EXx } },
5033   },
5034
5035   /* PREFIX_VEX_0F38AB */
5036   {
5037     { Bad_Opcode },
5038     { Bad_Opcode },
5039     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5040   },
5041
5042   /* PREFIX_VEX_0F38AC */
5043   {
5044     { Bad_Opcode },
5045     { Bad_Opcode },
5046     { "vfnmadd213p%XW", { XM, Vex, EXx } },
5047   },
5048
5049   /* PREFIX_VEX_0F38AD */
5050   {
5051     { Bad_Opcode },
5052     { Bad_Opcode },
5053     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5054   },
5055
5056   /* PREFIX_VEX_0F38AE */
5057   {
5058     { Bad_Opcode },
5059     { Bad_Opcode },
5060     { "vfnmsub213p%XW", { XM, Vex, EXx } },
5061   },
5062
5063   /* PREFIX_VEX_0F38AF */
5064   {
5065     { Bad_Opcode },
5066     { Bad_Opcode },
5067     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5068   },
5069
5070   /* PREFIX_VEX_0F38B6 */
5071   {
5072     { Bad_Opcode },
5073     { Bad_Opcode },
5074     { "vfmaddsub231p%XW", { XM, Vex, EXx } },
5075   },
5076
5077   /* PREFIX_VEX_0F38B7 */
5078   {
5079     { Bad_Opcode },
5080     { Bad_Opcode },
5081     { "vfmsubadd231p%XW", { XM, Vex, EXx } },
5082   },
5083
5084   /* PREFIX_VEX_0F38B8 */
5085   {
5086     { Bad_Opcode },
5087     { Bad_Opcode },
5088     { "vfmadd231p%XW", { XM, Vex, EXx } },
5089   },
5090
5091   /* PREFIX_VEX_0F38B9 */
5092   {
5093     { Bad_Opcode },
5094     { Bad_Opcode },
5095     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5096   },
5097
5098   /* PREFIX_VEX_0F38BA */
5099   {
5100     { Bad_Opcode },
5101     { Bad_Opcode },
5102     { "vfmsub231p%XW", { XM, Vex, EXx } },
5103   },
5104
5105   /* PREFIX_VEX_0F38BB */
5106   {
5107     { Bad_Opcode },
5108     { Bad_Opcode },
5109     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5110   },
5111
5112   /* PREFIX_VEX_0F38BC */
5113   {
5114     { Bad_Opcode },
5115     { Bad_Opcode },
5116     { "vfnmadd231p%XW", { XM, Vex, EXx } },
5117   },
5118
5119   /* PREFIX_VEX_0F38BD */
5120   {
5121     { Bad_Opcode },
5122     { Bad_Opcode },
5123     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5124   },
5125
5126   /* PREFIX_VEX_0F38BE */
5127   {
5128     { Bad_Opcode },
5129     { Bad_Opcode },
5130     { "vfnmsub231p%XW", { XM, Vex, EXx } },
5131   },
5132
5133   /* PREFIX_VEX_0F38BF */
5134   {
5135     { Bad_Opcode },
5136     { Bad_Opcode },
5137     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5138   },
5139
5140   /* PREFIX_VEX_0F38DB */
5141   {
5142     { Bad_Opcode },
5143     { Bad_Opcode },
5144     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
5145   },
5146
5147   /* PREFIX_VEX_0F38DC */
5148   {
5149     { Bad_Opcode },
5150     { Bad_Opcode },
5151     { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) },
5152   },
5153
5154   /* PREFIX_VEX_0F38DD */
5155   {
5156     { Bad_Opcode },
5157     { Bad_Opcode },
5158     { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) },
5159   },
5160
5161   /* PREFIX_VEX_0F38DE */
5162   {
5163     { Bad_Opcode },
5164     { Bad_Opcode },
5165     { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) },
5166   },
5167
5168   /* PREFIX_VEX_0F38DF */
5169   {
5170     { Bad_Opcode },
5171     { Bad_Opcode },
5172     { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) },
5173   },
5174
5175   /* PREFIX_VEX_0F38F2 */
5176   {
5177     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
5178   },
5179
5180   /* PREFIX_VEX_0F38F3_REG_1 */
5181   {
5182     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
5183   },
5184
5185   /* PREFIX_VEX_0F38F3_REG_2 */
5186   {
5187     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
5188   },
5189
5190   /* PREFIX_VEX_0F38F3_REG_3 */
5191   {
5192     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
5193   },
5194
5195   /* PREFIX_VEX_0F38F5 */
5196   {
5197     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
5198     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
5199     { Bad_Opcode },
5200     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
5201   },
5202
5203   /* PREFIX_VEX_0F38F6 */
5204   {
5205     { Bad_Opcode },
5206     { Bad_Opcode },
5207     { Bad_Opcode },
5208     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
5209   },
5210
5211   /* PREFIX_VEX_0F38F7 */
5212   {
5213     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
5214     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
5215     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
5216     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
5217   },
5218
5219   /* PREFIX_VEX_0F3A00 */
5220   {
5221     { Bad_Opcode },
5222     { Bad_Opcode },
5223     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
5224   },
5225
5226   /* PREFIX_VEX_0F3A01 */
5227   {
5228     { Bad_Opcode },
5229     { Bad_Opcode },
5230     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
5231   },
5232
5233   /* PREFIX_VEX_0F3A02 */
5234   {
5235     { Bad_Opcode },
5236     { Bad_Opcode },
5237     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
5238   },
5239
5240   /* PREFIX_VEX_0F3A04 */
5241   {
5242     { Bad_Opcode },
5243     { Bad_Opcode },
5244     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
5245   },
5246
5247   /* PREFIX_VEX_0F3A05 */
5248   {
5249     { Bad_Opcode },
5250     { Bad_Opcode },
5251     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
5252   },
5253
5254   /* PREFIX_VEX_0F3A06 */
5255   {
5256     { Bad_Opcode },
5257     { Bad_Opcode },
5258     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
5259   },
5260
5261   /* PREFIX_VEX_0F3A08 */
5262   {
5263     { Bad_Opcode },
5264     { Bad_Opcode },
5265     { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
5266   },
5267
5268   /* PREFIX_VEX_0F3A09 */
5269   {
5270     { Bad_Opcode },
5271     { Bad_Opcode },
5272     { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
5273   },
5274
5275   /* PREFIX_VEX_0F3A0A */
5276   {
5277     { Bad_Opcode },
5278     { Bad_Opcode },
5279     { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
5280   },
5281
5282   /* PREFIX_VEX_0F3A0B */
5283   {
5284     { Bad_Opcode },
5285     { Bad_Opcode },
5286     { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
5287   },
5288
5289   /* PREFIX_VEX_0F3A0C */
5290   {
5291     { Bad_Opcode },
5292     { Bad_Opcode },
5293     { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
5294   },
5295
5296   /* PREFIX_VEX_0F3A0D */
5297   {
5298     { Bad_Opcode },
5299     { Bad_Opcode },
5300     { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
5301   },
5302
5303   /* PREFIX_VEX_0F3A0E */
5304   {
5305     { Bad_Opcode },
5306     { Bad_Opcode },
5307     { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
5308   },
5309
5310   /* PREFIX_VEX_0F3A0F */
5311   {
5312     { Bad_Opcode },
5313     { Bad_Opcode },
5314     { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
5315   },
5316
5317   /* PREFIX_VEX_0F3A14 */
5318   {
5319     { Bad_Opcode },
5320     { Bad_Opcode },
5321     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
5322   },
5323
5324   /* PREFIX_VEX_0F3A15 */
5325   {
5326     { Bad_Opcode },
5327     { Bad_Opcode },
5328     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
5329   },
5330
5331   /* PREFIX_VEX_0F3A16 */
5332   {
5333     { Bad_Opcode },
5334     { Bad_Opcode },
5335     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
5336   },
5337
5338   /* PREFIX_VEX_0F3A17 */
5339   {
5340     { Bad_Opcode },
5341     { Bad_Opcode },
5342     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
5343   },
5344
5345   /* PREFIX_VEX_0F3A18 */
5346   {
5347     { Bad_Opcode },
5348     { Bad_Opcode },
5349     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
5350   },
5351
5352   /* PREFIX_VEX_0F3A19 */
5353   {
5354     { Bad_Opcode },
5355     { Bad_Opcode },
5356     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
5357   },
5358
5359   /* PREFIX_VEX_0F3A1D */
5360   {
5361     { Bad_Opcode },
5362     { Bad_Opcode },
5363     { "vcvtps2ph", { EXxmmq, XM, Ib } },
5364   },
5365
5366   /* PREFIX_VEX_0F3A20 */
5367   {
5368     { Bad_Opcode },
5369     { Bad_Opcode },
5370     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
5371   },
5372
5373   /* PREFIX_VEX_0F3A21 */
5374   {
5375     { Bad_Opcode },
5376     { Bad_Opcode },
5377     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
5378   },
5379
5380   /* PREFIX_VEX_0F3A22 */
5381   {
5382     { Bad_Opcode },
5383     { Bad_Opcode },
5384     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
5385   },
5386
5387   /* PREFIX_VEX_0F3A38 */
5388   {
5389     { Bad_Opcode },
5390     { Bad_Opcode },
5391     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
5392   },
5393
5394   /* PREFIX_VEX_0F3A39 */
5395   {
5396     { Bad_Opcode },
5397     { Bad_Opcode },
5398     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
5399   },
5400
5401   /* PREFIX_VEX_0F3A40 */
5402   {
5403     { Bad_Opcode },
5404     { Bad_Opcode },
5405     { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
5406   },
5407
5408   /* PREFIX_VEX_0F3A41 */
5409   {
5410     { Bad_Opcode },
5411     { Bad_Opcode },
5412     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
5413   },
5414
5415   /* PREFIX_VEX_0F3A42 */
5416   {
5417     { Bad_Opcode },
5418     { Bad_Opcode },
5419     { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
5420   },
5421
5422   /* PREFIX_VEX_0F3A44 */
5423   {
5424     { Bad_Opcode },
5425     { Bad_Opcode },
5426     { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) },
5427   },
5428
5429   /* PREFIX_VEX_0F3A46 */
5430   {
5431     { Bad_Opcode },
5432     { Bad_Opcode },
5433     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
5434   },
5435
5436   /* PREFIX_VEX_0F3A48 */
5437   {
5438     { Bad_Opcode },
5439     { Bad_Opcode },
5440     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
5441   },
5442
5443   /* PREFIX_VEX_0F3A49 */
5444   {
5445     { Bad_Opcode },
5446     { Bad_Opcode },
5447     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
5448   },
5449
5450   /* PREFIX_VEX_0F3A4A */
5451   {
5452     { Bad_Opcode },
5453     { Bad_Opcode },
5454     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
5455   },
5456
5457   /* PREFIX_VEX_0F3A4B */
5458   {
5459     { Bad_Opcode },
5460     { Bad_Opcode },
5461     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
5462   },
5463
5464   /* PREFIX_VEX_0F3A4C */
5465   {
5466     { Bad_Opcode },
5467     { Bad_Opcode },
5468     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
5469   },
5470
5471   /* PREFIX_VEX_0F3A5C */
5472   {
5473     { Bad_Opcode },
5474     { Bad_Opcode },
5475     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5476   },
5477
5478   /* PREFIX_VEX_0F3A5D */
5479   {
5480     { Bad_Opcode },
5481     { Bad_Opcode },
5482     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5483   },
5484
5485   /* PREFIX_VEX_0F3A5E */
5486   {
5487     { Bad_Opcode },
5488     { Bad_Opcode },
5489     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5490   },
5491
5492   /* PREFIX_VEX_0F3A5F */
5493   {
5494     { Bad_Opcode },
5495     { Bad_Opcode },
5496     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5497   },
5498
5499   /* PREFIX_VEX_0F3A60 */
5500   {
5501     { Bad_Opcode },
5502     { Bad_Opcode },
5503     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
5504     { Bad_Opcode },
5505   },
5506
5507   /* PREFIX_VEX_0F3A61 */
5508   {
5509     { Bad_Opcode },
5510     { Bad_Opcode },
5511     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
5512   },
5513
5514   /* PREFIX_VEX_0F3A62 */
5515   {
5516     { Bad_Opcode },
5517     { Bad_Opcode },
5518     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
5519   },
5520
5521   /* PREFIX_VEX_0F3A63 */
5522   {
5523     { Bad_Opcode },
5524     { Bad_Opcode },
5525     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
5526   },
5527
5528   /* PREFIX_VEX_0F3A68 */
5529   {
5530     { Bad_Opcode },
5531     { Bad_Opcode },
5532     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5533   },
5534
5535   /* PREFIX_VEX_0F3A69 */
5536   {
5537     { Bad_Opcode },
5538     { Bad_Opcode },
5539     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5540   },
5541
5542   /* PREFIX_VEX_0F3A6A */
5543   {
5544     { Bad_Opcode },
5545     { Bad_Opcode },
5546     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
5547   },
5548
5549   /* PREFIX_VEX_0F3A6B */
5550   {
5551     { Bad_Opcode },
5552     { Bad_Opcode },
5553     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
5554   },
5555
5556   /* PREFIX_VEX_0F3A6C */
5557   {
5558     { Bad_Opcode },
5559     { Bad_Opcode },
5560     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5561   },
5562
5563   /* PREFIX_VEX_0F3A6D */
5564   {
5565     { Bad_Opcode },
5566     { Bad_Opcode },
5567     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5568   },
5569
5570   /* PREFIX_VEX_0F3A6E */
5571   {
5572     { Bad_Opcode },
5573     { Bad_Opcode },
5574     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
5575   },
5576
5577   /* PREFIX_VEX_0F3A6F */
5578   {
5579     { Bad_Opcode },
5580     { Bad_Opcode },
5581     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
5582   },
5583
5584   /* PREFIX_VEX_0F3A78 */
5585   {
5586     { Bad_Opcode },
5587     { Bad_Opcode },
5588     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5589   },
5590
5591   /* PREFIX_VEX_0F3A79 */
5592   {
5593     { Bad_Opcode },
5594     { Bad_Opcode },
5595     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5596   },
5597
5598   /* PREFIX_VEX_0F3A7A */
5599   {
5600     { Bad_Opcode },
5601     { Bad_Opcode },
5602     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
5603   },
5604
5605   /* PREFIX_VEX_0F3A7B */
5606   {
5607     { Bad_Opcode },
5608     { Bad_Opcode },
5609     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
5610   },
5611
5612   /* PREFIX_VEX_0F3A7C */
5613   {
5614     { Bad_Opcode },
5615     { Bad_Opcode },
5616     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5617     { Bad_Opcode },
5618   },
5619
5620   /* PREFIX_VEX_0F3A7D */
5621   {
5622     { Bad_Opcode },
5623     { Bad_Opcode },
5624     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5625   },
5626
5627   /* PREFIX_VEX_0F3A7E */
5628   {
5629     { Bad_Opcode },
5630     { Bad_Opcode },
5631     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
5632   },
5633
5634   /* PREFIX_VEX_0F3A7F */
5635   {
5636     { Bad_Opcode },
5637     { Bad_Opcode },
5638     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
5639   },
5640
5641   /* PREFIX_VEX_0F3ADF */
5642   {
5643     { Bad_Opcode },
5644     { Bad_Opcode },
5645     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
5646   },
5647
5648   /* PREFIX_VEX_0F3AF0 */
5649   {
5650     { Bad_Opcode },
5651     { Bad_Opcode },
5652     { Bad_Opcode },
5653     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
5654   },
5655 };
5656
5657 static const struct dis386 x86_64_table[][2] = {
5658   /* X86_64_06 */
5659   {
5660     { "pushP", { es } },
5661   },
5662
5663   /* X86_64_07 */
5664   {
5665     { "popP", { es } },
5666   },
5667
5668   /* X86_64_0D */
5669   {
5670     { "pushP", { cs } },
5671   },
5672
5673   /* X86_64_16 */
5674   {
5675     { "pushP", { ss } },
5676   },
5677
5678   /* X86_64_17 */
5679   {
5680     { "popP", { ss } },
5681   },
5682
5683   /* X86_64_1E */
5684   {
5685     { "pushP", { ds } },
5686   },
5687
5688   /* X86_64_1F */
5689   {
5690     { "popP", { ds } },
5691   },
5692
5693   /* X86_64_27 */
5694   {
5695     { "daa", { XX } },
5696   },
5697
5698   /* X86_64_2F */
5699   {
5700     { "das", { XX } },
5701   },
5702
5703   /* X86_64_37 */
5704   {
5705     { "aaa", { XX } },
5706   },
5707
5708   /* X86_64_3F */
5709   {
5710     { "aas", { XX } },
5711   },
5712
5713   /* X86_64_60 */
5714   {
5715     { "pushaP", { XX } },
5716   },
5717
5718   /* X86_64_61 */
5719   {
5720     { "popaP", { XX } },
5721   },
5722
5723   /* X86_64_62 */
5724   {
5725     { MOD_TABLE (MOD_62_32BIT) },
5726   },
5727
5728   /* X86_64_63 */
5729   {
5730     { "arpl", { Ew, Gw } },
5731     { "movs{lq|xd}", { Gv, Ed } },
5732   },
5733
5734   /* X86_64_6D */
5735   {
5736     { "ins{R|}", { Yzr, indirDX } },
5737     { "ins{G|}", { Yzr, indirDX } },
5738   },
5739
5740   /* X86_64_6F */
5741   {
5742     { "outs{R|}", { indirDXr, Xz } },
5743     { "outs{G|}", { indirDXr, Xz } },
5744   },
5745
5746   /* X86_64_9A */
5747   {
5748     { "Jcall{T|}", { Ap } },
5749   },
5750
5751   /* X86_64_C4 */
5752   {
5753     { MOD_TABLE (MOD_C4_32BIT) },
5754     { VEX_C4_TABLE (VEX_0F) },
5755   },
5756
5757   /* X86_64_C5 */
5758   {
5759     { MOD_TABLE (MOD_C5_32BIT) },
5760     { VEX_C5_TABLE (VEX_0F) },
5761   },
5762
5763   /* X86_64_CE */
5764   {
5765     { "into", { XX } },
5766   },
5767
5768   /* X86_64_D4 */
5769   {
5770     { "aam", { Ib } },
5771   },
5772
5773   /* X86_64_D5 */
5774   {
5775     { "aad", { Ib } },
5776   },
5777
5778   /* X86_64_EA */
5779   {
5780     { "Jjmp{T|}", { Ap } },
5781   },
5782
5783   /* X86_64_0F01_REG_0 */
5784   {
5785     { "sgdt{Q|IQ}", { M } },
5786     { "sgdt", { M } },
5787   },
5788
5789   /* X86_64_0F01_REG_1 */
5790   {
5791     { "sidt{Q|IQ}", { M } },
5792     { "sidt", { M } },
5793   },
5794
5795   /* X86_64_0F01_REG_2 */
5796   {
5797     { "lgdt{Q|Q}", { M } },
5798     { "lgdt", { M } },
5799   },
5800
5801   /* X86_64_0F01_REG_3 */
5802   {
5803     { "lidt{Q|Q}", { M } },
5804     { "lidt", { M } },
5805   },
5806 };
5807
5808 static const struct dis386 three_byte_table[][256] = {
5809
5810   /* THREE_BYTE_0F38 */
5811   {
5812     /* 00 */
5813     { "pshufb",         { MX, EM } },
5814     { "phaddw",         { MX, EM } },
5815     { "phaddd",         { MX, EM } },
5816     { "phaddsw",        { MX, EM } },
5817     { "pmaddubsw",      { MX, EM } },
5818     { "phsubw",         { MX, EM } },
5819     { "phsubd",         { MX, EM } },
5820     { "phsubsw",        { MX, EM } },
5821     /* 08 */
5822     { "psignb",         { MX, EM } },
5823     { "psignw",         { MX, EM } },
5824     { "psignd",         { MX, EM } },
5825     { "pmulhrsw",       { MX, EM } },
5826     { Bad_Opcode },
5827     { Bad_Opcode },
5828     { Bad_Opcode },
5829     { Bad_Opcode },
5830     /* 10 */
5831     { PREFIX_TABLE (PREFIX_0F3810) },
5832     { Bad_Opcode },
5833     { Bad_Opcode },
5834     { Bad_Opcode },
5835     { PREFIX_TABLE (PREFIX_0F3814) },
5836     { PREFIX_TABLE (PREFIX_0F3815) },
5837     { Bad_Opcode },
5838     { PREFIX_TABLE (PREFIX_0F3817) },
5839     /* 18 */
5840     { Bad_Opcode },
5841     { Bad_Opcode },
5842     { Bad_Opcode },
5843     { Bad_Opcode },
5844     { "pabsb",          { MX, EM } },
5845     { "pabsw",          { MX, EM } },
5846     { "pabsd",          { MX, EM } },
5847     { Bad_Opcode },
5848     /* 20 */
5849     { PREFIX_TABLE (PREFIX_0F3820) },
5850     { PREFIX_TABLE (PREFIX_0F3821) },
5851     { PREFIX_TABLE (PREFIX_0F3822) },
5852     { PREFIX_TABLE (PREFIX_0F3823) },
5853     { PREFIX_TABLE (PREFIX_0F3824) },
5854     { PREFIX_TABLE (PREFIX_0F3825) },
5855     { Bad_Opcode },
5856     { Bad_Opcode },
5857     /* 28 */
5858     { PREFIX_TABLE (PREFIX_0F3828) },
5859     { PREFIX_TABLE (PREFIX_0F3829) },
5860     { PREFIX_TABLE (PREFIX_0F382A) },
5861     { PREFIX_TABLE (PREFIX_0F382B) },
5862     { Bad_Opcode },
5863     { Bad_Opcode },
5864     { Bad_Opcode },
5865     { Bad_Opcode },
5866     /* 30 */
5867     { PREFIX_TABLE (PREFIX_0F3830) },
5868     { PREFIX_TABLE (PREFIX_0F3831) },
5869     { PREFIX_TABLE (PREFIX_0F3832) },
5870     { PREFIX_TABLE (PREFIX_0F3833) },
5871     { PREFIX_TABLE (PREFIX_0F3834) },
5872     { PREFIX_TABLE (PREFIX_0F3835) },
5873     { Bad_Opcode },
5874     { PREFIX_TABLE (PREFIX_0F3837) },
5875     /* 38 */
5876     { PREFIX_TABLE (PREFIX_0F3838) },
5877     { PREFIX_TABLE (PREFIX_0F3839) },
5878     { PREFIX_TABLE (PREFIX_0F383A) },
5879     { PREFIX_TABLE (PREFIX_0F383B) },
5880     { PREFIX_TABLE (PREFIX_0F383C) },
5881     { PREFIX_TABLE (PREFIX_0F383D) },
5882     { PREFIX_TABLE (PREFIX_0F383E) },
5883     { PREFIX_TABLE (PREFIX_0F383F) },
5884     /* 40 */
5885     { PREFIX_TABLE (PREFIX_0F3840) },
5886     { PREFIX_TABLE (PREFIX_0F3841) },
5887     { Bad_Opcode },
5888     { Bad_Opcode },
5889     { Bad_Opcode },
5890     { Bad_Opcode },
5891     { Bad_Opcode },
5892     { Bad_Opcode },
5893     /* 48 */
5894     { Bad_Opcode },
5895     { Bad_Opcode },
5896     { Bad_Opcode },
5897     { Bad_Opcode },
5898     { Bad_Opcode },
5899     { Bad_Opcode },
5900     { Bad_Opcode },
5901     { Bad_Opcode },
5902     /* 50 */
5903     { Bad_Opcode },
5904     { Bad_Opcode },
5905     { Bad_Opcode },
5906     { Bad_Opcode },
5907     { Bad_Opcode },
5908     { Bad_Opcode },
5909     { Bad_Opcode },
5910     { Bad_Opcode },
5911     /* 58 */
5912     { Bad_Opcode },
5913     { Bad_Opcode },
5914     { Bad_Opcode },
5915     { Bad_Opcode },
5916     { Bad_Opcode },
5917     { Bad_Opcode },
5918     { Bad_Opcode },
5919     { Bad_Opcode },
5920     /* 60 */
5921     { Bad_Opcode },
5922     { Bad_Opcode },
5923     { Bad_Opcode },
5924     { Bad_Opcode },
5925     { Bad_Opcode },
5926     { Bad_Opcode },
5927     { Bad_Opcode },
5928     { Bad_Opcode },
5929     /* 68 */
5930     { Bad_Opcode },
5931     { Bad_Opcode },
5932     { Bad_Opcode },
5933     { Bad_Opcode },
5934     { Bad_Opcode },
5935     { Bad_Opcode },
5936     { Bad_Opcode },
5937     { Bad_Opcode },
5938     /* 70 */
5939     { Bad_Opcode },
5940     { Bad_Opcode },
5941     { Bad_Opcode },
5942     { Bad_Opcode },
5943     { Bad_Opcode },
5944     { Bad_Opcode },
5945     { Bad_Opcode },
5946     { Bad_Opcode },
5947     /* 78 */
5948     { Bad_Opcode },
5949     { Bad_Opcode },
5950     { Bad_Opcode },
5951     { Bad_Opcode },
5952     { Bad_Opcode },
5953     { Bad_Opcode },
5954     { Bad_Opcode },
5955     { Bad_Opcode },
5956     /* 80 */
5957     { PREFIX_TABLE (PREFIX_0F3880) },
5958     { PREFIX_TABLE (PREFIX_0F3881) },
5959     { PREFIX_TABLE (PREFIX_0F3882) },
5960     { Bad_Opcode },
5961     { Bad_Opcode },
5962     { Bad_Opcode },
5963     { Bad_Opcode },
5964     { Bad_Opcode },
5965     /* 88 */
5966     { Bad_Opcode },
5967     { Bad_Opcode },
5968     { Bad_Opcode },
5969     { Bad_Opcode },
5970     { Bad_Opcode },
5971     { Bad_Opcode },
5972     { Bad_Opcode },
5973     { Bad_Opcode },
5974     /* 90 */
5975     { Bad_Opcode },
5976     { Bad_Opcode },
5977     { Bad_Opcode },
5978     { Bad_Opcode },
5979     { Bad_Opcode },
5980     { Bad_Opcode },
5981     { Bad_Opcode },
5982     { Bad_Opcode },
5983     /* 98 */
5984     { Bad_Opcode },
5985     { Bad_Opcode },
5986     { Bad_Opcode },
5987     { Bad_Opcode },
5988     { Bad_Opcode },
5989     { Bad_Opcode },
5990     { Bad_Opcode },
5991     { Bad_Opcode },
5992     /* a0 */
5993     { Bad_Opcode },
5994     { Bad_Opcode },
5995     { Bad_Opcode },
5996     { Bad_Opcode },
5997     { Bad_Opcode },
5998     { Bad_Opcode },
5999     { Bad_Opcode },
6000     { Bad_Opcode },
6001     /* a8 */
6002     { Bad_Opcode },
6003     { Bad_Opcode },
6004     { Bad_Opcode },
6005     { Bad_Opcode },
6006     { Bad_Opcode },
6007     { Bad_Opcode },
6008     { Bad_Opcode },
6009     { Bad_Opcode },
6010     /* b0 */
6011     { Bad_Opcode },
6012     { Bad_Opcode },
6013     { Bad_Opcode },
6014     { Bad_Opcode },
6015     { Bad_Opcode },
6016     { Bad_Opcode },
6017     { Bad_Opcode },
6018     { Bad_Opcode },
6019     /* b8 */
6020     { Bad_Opcode },
6021     { Bad_Opcode },
6022     { Bad_Opcode },
6023     { Bad_Opcode },
6024     { Bad_Opcode },
6025     { Bad_Opcode },
6026     { Bad_Opcode },
6027     { Bad_Opcode },
6028     /* c0 */
6029     { Bad_Opcode },
6030     { Bad_Opcode },
6031     { Bad_Opcode },
6032     { Bad_Opcode },
6033     { Bad_Opcode },
6034     { Bad_Opcode },
6035     { Bad_Opcode },
6036     { Bad_Opcode },
6037     /* c8 */
6038     { Bad_Opcode },
6039     { Bad_Opcode },
6040     { Bad_Opcode },
6041     { Bad_Opcode },
6042     { Bad_Opcode },
6043     { Bad_Opcode },
6044     { Bad_Opcode },
6045     { Bad_Opcode },
6046     /* d0 */
6047     { Bad_Opcode },
6048     { Bad_Opcode },
6049     { Bad_Opcode },
6050     { Bad_Opcode },
6051     { Bad_Opcode },
6052     { Bad_Opcode },
6053     { Bad_Opcode },
6054     { Bad_Opcode },
6055     /* d8 */
6056     { Bad_Opcode },
6057     { Bad_Opcode },
6058     { Bad_Opcode },
6059     { PREFIX_TABLE (PREFIX_0F38DB) },
6060     { PREFIX_TABLE (PREFIX_0F38DC) },
6061     { PREFIX_TABLE (PREFIX_0F38DD) },
6062     { PREFIX_TABLE (PREFIX_0F38DE) },
6063     { PREFIX_TABLE (PREFIX_0F38DF) },
6064     /* e0 */
6065     { Bad_Opcode },
6066     { Bad_Opcode },
6067     { Bad_Opcode },
6068     { Bad_Opcode },
6069     { Bad_Opcode },
6070     { Bad_Opcode },
6071     { Bad_Opcode },
6072     { Bad_Opcode },
6073     /* e8 */
6074     { Bad_Opcode },
6075     { Bad_Opcode },
6076     { Bad_Opcode },
6077     { Bad_Opcode },
6078     { Bad_Opcode },
6079     { Bad_Opcode },
6080     { Bad_Opcode },
6081     { Bad_Opcode },
6082     /* f0 */
6083     { PREFIX_TABLE (PREFIX_0F38F0) },
6084     { PREFIX_TABLE (PREFIX_0F38F1) },
6085     { Bad_Opcode },
6086     { Bad_Opcode },
6087     { Bad_Opcode },
6088     { Bad_Opcode },
6089     { PREFIX_TABLE (PREFIX_0F38F6) },
6090     { Bad_Opcode },
6091     /* f8 */
6092     { Bad_Opcode },
6093     { Bad_Opcode },
6094     { Bad_Opcode },
6095     { Bad_Opcode },
6096     { Bad_Opcode },
6097     { Bad_Opcode },
6098     { Bad_Opcode },
6099     { Bad_Opcode },
6100   },
6101   /* THREE_BYTE_0F3A */
6102   {
6103     /* 00 */
6104     { Bad_Opcode },
6105     { Bad_Opcode },
6106     { Bad_Opcode },
6107     { Bad_Opcode },
6108     { Bad_Opcode },
6109     { Bad_Opcode },
6110     { Bad_Opcode },
6111     { Bad_Opcode },
6112     /* 08 */
6113     { PREFIX_TABLE (PREFIX_0F3A08) },
6114     { PREFIX_TABLE (PREFIX_0F3A09) },
6115     { PREFIX_TABLE (PREFIX_0F3A0A) },
6116     { PREFIX_TABLE (PREFIX_0F3A0B) },
6117     { PREFIX_TABLE (PREFIX_0F3A0C) },
6118     { PREFIX_TABLE (PREFIX_0F3A0D) },
6119     { PREFIX_TABLE (PREFIX_0F3A0E) },
6120     { "palignr",        { MX, EM, Ib } },
6121     /* 10 */
6122     { Bad_Opcode },
6123     { Bad_Opcode },
6124     { Bad_Opcode },
6125     { Bad_Opcode },
6126     { PREFIX_TABLE (PREFIX_0F3A14) },
6127     { PREFIX_TABLE (PREFIX_0F3A15) },
6128     { PREFIX_TABLE (PREFIX_0F3A16) },
6129     { PREFIX_TABLE (PREFIX_0F3A17) },
6130     /* 18 */
6131     { Bad_Opcode },
6132     { Bad_Opcode },
6133     { Bad_Opcode },
6134     { Bad_Opcode },
6135     { Bad_Opcode },
6136     { Bad_Opcode },
6137     { Bad_Opcode },
6138     { Bad_Opcode },
6139     /* 20 */
6140     { PREFIX_TABLE (PREFIX_0F3A20) },
6141     { PREFIX_TABLE (PREFIX_0F3A21) },
6142     { PREFIX_TABLE (PREFIX_0F3A22) },
6143     { Bad_Opcode },
6144     { Bad_Opcode },
6145     { Bad_Opcode },
6146     { Bad_Opcode },
6147     { Bad_Opcode },
6148     /* 28 */
6149     { Bad_Opcode },
6150     { Bad_Opcode },
6151     { Bad_Opcode },
6152     { Bad_Opcode },
6153     { Bad_Opcode },
6154     { Bad_Opcode },
6155     { Bad_Opcode },
6156     { Bad_Opcode },
6157     /* 30 */
6158     { Bad_Opcode },
6159     { Bad_Opcode },
6160     { Bad_Opcode },
6161     { Bad_Opcode },
6162     { Bad_Opcode },
6163     { Bad_Opcode },
6164     { Bad_Opcode },
6165     { Bad_Opcode },
6166     /* 38 */
6167     { Bad_Opcode },
6168     { Bad_Opcode },
6169     { Bad_Opcode },
6170     { Bad_Opcode },
6171     { Bad_Opcode },
6172     { Bad_Opcode },
6173     { Bad_Opcode },
6174     { Bad_Opcode },
6175     /* 40 */
6176     { PREFIX_TABLE (PREFIX_0F3A40) },
6177     { PREFIX_TABLE (PREFIX_0F3A41) },
6178     { PREFIX_TABLE (PREFIX_0F3A42) },
6179     { Bad_Opcode },
6180     { PREFIX_TABLE (PREFIX_0F3A44) },
6181     { Bad_Opcode },
6182     { Bad_Opcode },
6183     { Bad_Opcode },
6184     /* 48 */
6185     { Bad_Opcode },
6186     { Bad_Opcode },
6187     { Bad_Opcode },
6188     { Bad_Opcode },
6189     { Bad_Opcode },
6190     { Bad_Opcode },
6191     { Bad_Opcode },
6192     { Bad_Opcode },
6193     /* 50 */
6194     { Bad_Opcode },
6195     { Bad_Opcode },
6196     { Bad_Opcode },
6197     { Bad_Opcode },
6198     { Bad_Opcode },
6199     { Bad_Opcode },
6200     { Bad_Opcode },
6201     { Bad_Opcode },
6202     /* 58 */
6203     { Bad_Opcode },
6204     { Bad_Opcode },
6205     { Bad_Opcode },
6206     { Bad_Opcode },
6207     { Bad_Opcode },
6208     { Bad_Opcode },
6209     { Bad_Opcode },
6210     { Bad_Opcode },
6211     /* 60 */
6212     { PREFIX_TABLE (PREFIX_0F3A60) },
6213     { PREFIX_TABLE (PREFIX_0F3A61) },
6214     { PREFIX_TABLE (PREFIX_0F3A62) },
6215     { PREFIX_TABLE (PREFIX_0F3A63) },
6216     { Bad_Opcode },
6217     { Bad_Opcode },
6218     { Bad_Opcode },
6219     { Bad_Opcode },
6220     /* 68 */
6221     { Bad_Opcode },
6222     { Bad_Opcode },
6223     { Bad_Opcode },
6224     { Bad_Opcode },
6225     { Bad_Opcode },
6226     { Bad_Opcode },
6227     { Bad_Opcode },
6228     { Bad_Opcode },
6229     /* 70 */
6230     { Bad_Opcode },
6231     { Bad_Opcode },
6232     { Bad_Opcode },
6233     { Bad_Opcode },
6234     { Bad_Opcode },
6235     { Bad_Opcode },
6236     { Bad_Opcode },
6237     { Bad_Opcode },
6238     /* 78 */
6239     { Bad_Opcode },
6240     { Bad_Opcode },
6241     { Bad_Opcode },
6242     { Bad_Opcode },
6243     { Bad_Opcode },
6244     { Bad_Opcode },
6245     { Bad_Opcode },
6246     { Bad_Opcode },
6247     /* 80 */
6248     { Bad_Opcode },
6249     { Bad_Opcode },
6250     { Bad_Opcode },
6251     { Bad_Opcode },
6252     { Bad_Opcode },
6253     { Bad_Opcode },
6254     { Bad_Opcode },
6255     { Bad_Opcode },
6256     /* 88 */
6257     { Bad_Opcode },
6258     { Bad_Opcode },
6259     { Bad_Opcode },
6260     { Bad_Opcode },
6261     { Bad_Opcode },
6262     { Bad_Opcode },
6263     { Bad_Opcode },
6264     { Bad_Opcode },
6265     /* 90 */
6266     { Bad_Opcode },
6267     { Bad_Opcode },
6268     { Bad_Opcode },
6269     { Bad_Opcode },
6270     { Bad_Opcode },
6271     { Bad_Opcode },
6272     { Bad_Opcode },
6273     { Bad_Opcode },
6274     /* 98 */
6275     { Bad_Opcode },
6276     { Bad_Opcode },
6277     { Bad_Opcode },
6278     { Bad_Opcode },
6279     { Bad_Opcode },
6280     { Bad_Opcode },
6281     { Bad_Opcode },
6282     { Bad_Opcode },
6283     /* a0 */
6284     { Bad_Opcode },
6285     { Bad_Opcode },
6286     { Bad_Opcode },
6287     { Bad_Opcode },
6288     { Bad_Opcode },
6289     { Bad_Opcode },
6290     { Bad_Opcode },
6291     { Bad_Opcode },
6292     /* a8 */
6293     { Bad_Opcode },
6294     { Bad_Opcode },
6295     { Bad_Opcode },
6296     { Bad_Opcode },
6297     { Bad_Opcode },
6298     { Bad_Opcode },
6299     { Bad_Opcode },
6300     { Bad_Opcode },
6301     /* b0 */
6302     { Bad_Opcode },
6303     { Bad_Opcode },
6304     { Bad_Opcode },
6305     { Bad_Opcode },
6306     { Bad_Opcode },
6307     { Bad_Opcode },
6308     { Bad_Opcode },
6309     { Bad_Opcode },
6310     /* b8 */
6311     { Bad_Opcode },
6312     { Bad_Opcode },
6313     { Bad_Opcode },
6314     { Bad_Opcode },
6315     { Bad_Opcode },
6316     { Bad_Opcode },
6317     { Bad_Opcode },
6318     { Bad_Opcode },
6319     /* c0 */
6320     { Bad_Opcode },
6321     { Bad_Opcode },
6322     { Bad_Opcode },
6323     { Bad_Opcode },
6324     { Bad_Opcode },
6325     { Bad_Opcode },
6326     { Bad_Opcode },
6327     { Bad_Opcode },
6328     /* c8 */
6329     { Bad_Opcode },
6330     { Bad_Opcode },
6331     { Bad_Opcode },
6332     { Bad_Opcode },
6333     { Bad_Opcode },
6334     { Bad_Opcode },
6335     { Bad_Opcode },
6336     { Bad_Opcode },
6337     /* d0 */
6338     { Bad_Opcode },
6339     { Bad_Opcode },
6340     { Bad_Opcode },
6341     { Bad_Opcode },
6342     { Bad_Opcode },
6343     { Bad_Opcode },
6344     { Bad_Opcode },
6345     { Bad_Opcode },
6346     /* d8 */
6347     { Bad_Opcode },
6348     { Bad_Opcode },
6349     { Bad_Opcode },
6350     { Bad_Opcode },
6351     { Bad_Opcode },
6352     { Bad_Opcode },
6353     { Bad_Opcode },
6354     { PREFIX_TABLE (PREFIX_0F3ADF) },
6355     /* e0 */
6356     { Bad_Opcode },
6357     { Bad_Opcode },
6358     { Bad_Opcode },
6359     { Bad_Opcode },
6360     { Bad_Opcode },
6361     { Bad_Opcode },
6362     { Bad_Opcode },
6363     { Bad_Opcode },
6364     /* e8 */
6365     { Bad_Opcode },
6366     { Bad_Opcode },
6367     { Bad_Opcode },
6368     { Bad_Opcode },
6369     { Bad_Opcode },
6370     { Bad_Opcode },
6371     { Bad_Opcode },
6372     { Bad_Opcode },
6373     /* f0 */
6374     { Bad_Opcode },
6375     { Bad_Opcode },
6376     { Bad_Opcode },
6377     { Bad_Opcode },
6378     { Bad_Opcode },
6379     { Bad_Opcode },
6380     { Bad_Opcode },
6381     { Bad_Opcode },
6382     /* f8 */
6383     { Bad_Opcode },
6384     { Bad_Opcode },
6385     { Bad_Opcode },
6386     { Bad_Opcode },
6387     { Bad_Opcode },
6388     { Bad_Opcode },
6389     { Bad_Opcode },
6390     { Bad_Opcode },
6391   },
6392
6393   /* THREE_BYTE_0F7A */
6394   {
6395     /* 00 */
6396     { Bad_Opcode },
6397     { Bad_Opcode },
6398     { Bad_Opcode },
6399     { Bad_Opcode },
6400     { Bad_Opcode },
6401     { Bad_Opcode },
6402     { Bad_Opcode },
6403     { Bad_Opcode },
6404     /* 08 */
6405     { Bad_Opcode },
6406     { Bad_Opcode },
6407     { Bad_Opcode },
6408     { Bad_Opcode },
6409     { Bad_Opcode },
6410     { Bad_Opcode },
6411     { Bad_Opcode },
6412     { Bad_Opcode },
6413     /* 10 */
6414     { Bad_Opcode },
6415     { Bad_Opcode },
6416     { Bad_Opcode },
6417     { Bad_Opcode },
6418     { Bad_Opcode },
6419     { Bad_Opcode },
6420     { Bad_Opcode },
6421     { Bad_Opcode },
6422     /* 18 */
6423     { Bad_Opcode },
6424     { Bad_Opcode },
6425     { Bad_Opcode },
6426     { Bad_Opcode },
6427     { Bad_Opcode },
6428     { Bad_Opcode },
6429     { Bad_Opcode },
6430     { Bad_Opcode },
6431     /* 20 */
6432     { "ptest",          { XX } },
6433     { Bad_Opcode },
6434     { Bad_Opcode },
6435     { Bad_Opcode },
6436     { Bad_Opcode },
6437     { Bad_Opcode },
6438     { Bad_Opcode },
6439     { Bad_Opcode },
6440     /* 28 */
6441     { Bad_Opcode },
6442     { Bad_Opcode },
6443     { Bad_Opcode },
6444     { Bad_Opcode },
6445     { Bad_Opcode },
6446     { Bad_Opcode },
6447     { Bad_Opcode },
6448     { Bad_Opcode },
6449     /* 30 */
6450     { Bad_Opcode },
6451     { Bad_Opcode },
6452     { Bad_Opcode },
6453     { Bad_Opcode },
6454     { Bad_Opcode },
6455     { Bad_Opcode },
6456     { Bad_Opcode },
6457     { Bad_Opcode },
6458     /* 38 */
6459     { Bad_Opcode },
6460     { Bad_Opcode },
6461     { Bad_Opcode },
6462     { Bad_Opcode },
6463     { Bad_Opcode },
6464     { Bad_Opcode },
6465     { Bad_Opcode },
6466     { Bad_Opcode },
6467     /* 40 */
6468     { Bad_Opcode },
6469     { "phaddbw",        { XM, EXq } },
6470     { "phaddbd",        { XM, EXq } },
6471     { "phaddbq",        { XM, EXq } },
6472     { Bad_Opcode },
6473     { Bad_Opcode },
6474     { "phaddwd",        { XM, EXq } },
6475     { "phaddwq",        { XM, EXq } },
6476     /* 48 */
6477     { Bad_Opcode },
6478     { Bad_Opcode },
6479     { Bad_Opcode },
6480     { "phadddq",        { XM, EXq } },
6481     { Bad_Opcode },
6482     { Bad_Opcode },
6483     { Bad_Opcode },
6484     { Bad_Opcode },
6485     /* 50 */
6486     { Bad_Opcode },
6487     { "phaddubw",       { XM, EXq } },
6488     { "phaddubd",       { XM, EXq } },
6489     { "phaddubq",       { XM, EXq } },
6490     { Bad_Opcode },
6491     { Bad_Opcode },
6492     { "phadduwd",       { XM, EXq } },
6493     { "phadduwq",       { XM, EXq } },
6494     /* 58 */
6495     { Bad_Opcode },
6496     { Bad_Opcode },
6497     { Bad_Opcode },
6498     { "phaddudq",       { XM, EXq } },
6499     { Bad_Opcode },
6500     { Bad_Opcode },
6501     { Bad_Opcode },
6502     { Bad_Opcode },
6503     /* 60 */
6504     { Bad_Opcode },
6505     { "phsubbw",        { XM, EXq } },
6506     { "phsubbd",        { XM, EXq } },
6507     { "phsubbq",        { XM, EXq } },
6508     { Bad_Opcode },
6509     { Bad_Opcode },
6510     { Bad_Opcode },
6511     { Bad_Opcode },
6512     /* 68 */
6513     { Bad_Opcode },
6514     { Bad_Opcode },
6515     { Bad_Opcode },
6516     { Bad_Opcode },
6517     { Bad_Opcode },
6518     { Bad_Opcode },
6519     { Bad_Opcode },
6520     { Bad_Opcode },
6521     /* 70 */
6522     { Bad_Opcode },
6523     { Bad_Opcode },
6524     { Bad_Opcode },
6525     { Bad_Opcode },
6526     { Bad_Opcode },
6527     { Bad_Opcode },
6528     { Bad_Opcode },
6529     { Bad_Opcode },
6530     /* 78 */
6531     { Bad_Opcode },
6532     { Bad_Opcode },
6533     { Bad_Opcode },
6534     { Bad_Opcode },
6535     { Bad_Opcode },
6536     { Bad_Opcode },
6537     { Bad_Opcode },
6538     { Bad_Opcode },
6539     /* 80 */
6540     { Bad_Opcode },
6541     { Bad_Opcode },
6542     { Bad_Opcode },
6543     { Bad_Opcode },
6544     { Bad_Opcode },
6545     { Bad_Opcode },
6546     { Bad_Opcode },
6547     { Bad_Opcode },
6548     /* 88 */
6549     { Bad_Opcode },
6550     { Bad_Opcode },
6551     { Bad_Opcode },
6552     { Bad_Opcode },
6553     { Bad_Opcode },
6554     { Bad_Opcode },
6555     { Bad_Opcode },
6556     { Bad_Opcode },
6557     /* 90 */
6558     { Bad_Opcode },
6559     { Bad_Opcode },
6560     { Bad_Opcode },
6561     { Bad_Opcode },
6562     { Bad_Opcode },
6563     { Bad_Opcode },
6564     { Bad_Opcode },
6565     { Bad_Opcode },
6566     /* 98 */
6567     { Bad_Opcode },
6568     { Bad_Opcode },
6569     { Bad_Opcode },
6570     { Bad_Opcode },
6571     { Bad_Opcode },
6572     { Bad_Opcode },
6573     { Bad_Opcode },
6574     { Bad_Opcode },
6575     /* a0 */
6576     { Bad_Opcode },
6577     { Bad_Opcode },
6578     { Bad_Opcode },
6579     { Bad_Opcode },
6580     { Bad_Opcode },
6581     { Bad_Opcode },
6582     { Bad_Opcode },
6583     { Bad_Opcode },
6584     /* a8 */
6585     { Bad_Opcode },
6586     { Bad_Opcode },
6587     { Bad_Opcode },
6588     { Bad_Opcode },
6589     { Bad_Opcode },
6590     { Bad_Opcode },
6591     { Bad_Opcode },
6592     { Bad_Opcode },
6593     /* b0 */
6594     { Bad_Opcode },
6595     { Bad_Opcode },
6596     { Bad_Opcode },
6597     { Bad_Opcode },
6598     { Bad_Opcode },
6599     { Bad_Opcode },
6600     { Bad_Opcode },
6601     { Bad_Opcode },
6602     /* b8 */
6603     { Bad_Opcode },
6604     { Bad_Opcode },
6605     { Bad_Opcode },
6606     { Bad_Opcode },
6607     { Bad_Opcode },
6608     { Bad_Opcode },
6609     { Bad_Opcode },
6610     { Bad_Opcode },
6611     /* c0 */
6612     { Bad_Opcode },
6613     { Bad_Opcode },
6614     { Bad_Opcode },
6615     { Bad_Opcode },
6616     { Bad_Opcode },
6617     { Bad_Opcode },
6618     { Bad_Opcode },
6619     { Bad_Opcode },
6620     /* c8 */
6621     { Bad_Opcode },
6622     { Bad_Opcode },
6623     { Bad_Opcode },
6624     { Bad_Opcode },
6625     { Bad_Opcode },
6626     { Bad_Opcode },
6627     { Bad_Opcode },
6628     { Bad_Opcode },
6629     /* d0 */
6630     { Bad_Opcode },
6631     { Bad_Opcode },
6632     { Bad_Opcode },
6633     { Bad_Opcode },
6634     { Bad_Opcode },
6635     { Bad_Opcode },
6636     { Bad_Opcode },
6637     { Bad_Opcode },
6638     /* d8 */
6639     { Bad_Opcode },
6640     { Bad_Opcode },
6641     { Bad_Opcode },
6642     { Bad_Opcode },
6643     { Bad_Opcode },
6644     { Bad_Opcode },
6645     { Bad_Opcode },
6646     { Bad_Opcode },
6647     /* e0 */
6648     { Bad_Opcode },
6649     { Bad_Opcode },
6650     { Bad_Opcode },
6651     { Bad_Opcode },
6652     { Bad_Opcode },
6653     { Bad_Opcode },
6654     { Bad_Opcode },
6655     { Bad_Opcode },
6656     /* e8 */
6657     { Bad_Opcode },
6658     { Bad_Opcode },
6659     { Bad_Opcode },
6660     { Bad_Opcode },
6661     { Bad_Opcode },
6662     { Bad_Opcode },
6663     { Bad_Opcode },
6664     { Bad_Opcode },
6665     /* f0 */
6666     { Bad_Opcode },
6667     { Bad_Opcode },
6668     { Bad_Opcode },
6669     { Bad_Opcode },
6670     { Bad_Opcode },
6671     { Bad_Opcode },
6672     { Bad_Opcode },
6673     { Bad_Opcode },
6674     /* f8 */
6675     { Bad_Opcode },
6676     { Bad_Opcode },
6677     { Bad_Opcode },
6678     { Bad_Opcode },
6679     { Bad_Opcode },
6680     { Bad_Opcode },
6681     { Bad_Opcode },
6682     { Bad_Opcode },
6683   },
6684 };
6685
6686 static const struct dis386 xop_table[][256] = {
6687   /* XOP_08 */
6688   {
6689     /* 00 */
6690     { Bad_Opcode },
6691     { Bad_Opcode },
6692     { Bad_Opcode },
6693     { Bad_Opcode },
6694     { Bad_Opcode },
6695     { Bad_Opcode },
6696     { Bad_Opcode },
6697     { Bad_Opcode },
6698     /* 08 */
6699     { Bad_Opcode },
6700     { Bad_Opcode },
6701     { Bad_Opcode },
6702     { Bad_Opcode },
6703     { Bad_Opcode },
6704     { Bad_Opcode },
6705     { Bad_Opcode },
6706     { Bad_Opcode },
6707     /* 10 */
6708     { Bad_Opcode },
6709     { Bad_Opcode },
6710     { Bad_Opcode },
6711     { Bad_Opcode },
6712     { Bad_Opcode },
6713     { Bad_Opcode },
6714     { Bad_Opcode },
6715     { Bad_Opcode },
6716     /* 18 */
6717     { Bad_Opcode },
6718     { Bad_Opcode },
6719     { Bad_Opcode },
6720     { Bad_Opcode },
6721     { Bad_Opcode },
6722     { Bad_Opcode },
6723     { Bad_Opcode },
6724     { Bad_Opcode },
6725     /* 20 */
6726     { Bad_Opcode },
6727     { Bad_Opcode },
6728     { Bad_Opcode },
6729     { Bad_Opcode },
6730     { Bad_Opcode },
6731     { Bad_Opcode },
6732     { Bad_Opcode },
6733     { Bad_Opcode },
6734     /* 28 */
6735     { Bad_Opcode },
6736     { Bad_Opcode },
6737     { Bad_Opcode },
6738     { Bad_Opcode },
6739     { Bad_Opcode },
6740     { Bad_Opcode },
6741     { Bad_Opcode },
6742     { Bad_Opcode },
6743     /* 30 */
6744     { Bad_Opcode },
6745     { Bad_Opcode },
6746     { Bad_Opcode },
6747     { Bad_Opcode },
6748     { Bad_Opcode },
6749     { Bad_Opcode },
6750     { Bad_Opcode },
6751     { Bad_Opcode },
6752     /* 38 */
6753     { Bad_Opcode },
6754     { Bad_Opcode },
6755     { Bad_Opcode },
6756     { Bad_Opcode },
6757     { Bad_Opcode },
6758     { Bad_Opcode },
6759     { Bad_Opcode },
6760     { Bad_Opcode },
6761     /* 40 */
6762     { Bad_Opcode },
6763     { Bad_Opcode },
6764     { Bad_Opcode },
6765     { Bad_Opcode },
6766     { Bad_Opcode },
6767     { Bad_Opcode },
6768     { Bad_Opcode },
6769     { Bad_Opcode },
6770     /* 48 */
6771     { Bad_Opcode },
6772     { Bad_Opcode },
6773     { Bad_Opcode },
6774     { Bad_Opcode },
6775     { Bad_Opcode },
6776     { Bad_Opcode },
6777     { Bad_Opcode },
6778     { Bad_Opcode },
6779     /* 50 */
6780     { Bad_Opcode },
6781     { Bad_Opcode },
6782     { Bad_Opcode },
6783     { Bad_Opcode },
6784     { Bad_Opcode },
6785     { Bad_Opcode },
6786     { Bad_Opcode },
6787     { Bad_Opcode },
6788     /* 58 */
6789     { Bad_Opcode },
6790     { Bad_Opcode },
6791     { Bad_Opcode },
6792     { Bad_Opcode },
6793     { Bad_Opcode },
6794     { Bad_Opcode },
6795     { Bad_Opcode },
6796     { Bad_Opcode },
6797     /* 60 */
6798     { Bad_Opcode },
6799     { Bad_Opcode },
6800     { Bad_Opcode },
6801     { Bad_Opcode },
6802     { Bad_Opcode },
6803     { Bad_Opcode },
6804     { Bad_Opcode },
6805     { Bad_Opcode },
6806     /* 68 */
6807     { Bad_Opcode },
6808     { Bad_Opcode },
6809     { Bad_Opcode },
6810     { Bad_Opcode },
6811     { Bad_Opcode },
6812     { Bad_Opcode },
6813     { Bad_Opcode },
6814     { Bad_Opcode },
6815     /* 70 */
6816     { Bad_Opcode },
6817     { Bad_Opcode },
6818     { Bad_Opcode },
6819     { Bad_Opcode },
6820     { Bad_Opcode },
6821     { Bad_Opcode },
6822     { Bad_Opcode },
6823     { Bad_Opcode },
6824     /* 78 */
6825     { Bad_Opcode },
6826     { Bad_Opcode },
6827     { Bad_Opcode },
6828     { Bad_Opcode },
6829     { Bad_Opcode },
6830     { Bad_Opcode },
6831     { Bad_Opcode },
6832     { Bad_Opcode },
6833     /* 80 */
6834     { Bad_Opcode },
6835     { Bad_Opcode },
6836     { Bad_Opcode },
6837     { Bad_Opcode },
6838     { Bad_Opcode },
6839     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6840     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6841     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6842     /* 88 */
6843     { Bad_Opcode },
6844     { Bad_Opcode },
6845     { Bad_Opcode },
6846     { Bad_Opcode },
6847     { Bad_Opcode },
6848     { Bad_Opcode },
6849     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6850     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6851     /* 90 */
6852     { Bad_Opcode },
6853     { Bad_Opcode },
6854     { Bad_Opcode },
6855     { Bad_Opcode },
6856     { Bad_Opcode },
6857     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6858     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6859     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6860     /* 98 */
6861     { Bad_Opcode },
6862     { Bad_Opcode },
6863     { Bad_Opcode },
6864     { Bad_Opcode },
6865     { Bad_Opcode },
6866     { Bad_Opcode },
6867     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6868     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6869     /* a0 */
6870     { Bad_Opcode },
6871     { Bad_Opcode },
6872     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6873     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6874     { Bad_Opcode },
6875     { Bad_Opcode },
6876     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6877     { Bad_Opcode },
6878     /* a8 */
6879     { Bad_Opcode },
6880     { Bad_Opcode },
6881     { Bad_Opcode },
6882     { Bad_Opcode },
6883     { Bad_Opcode },
6884     { Bad_Opcode },
6885     { Bad_Opcode },
6886     { Bad_Opcode },
6887     /* b0 */
6888     { Bad_Opcode },
6889     { Bad_Opcode },
6890     { Bad_Opcode },
6891     { Bad_Opcode },
6892     { Bad_Opcode },
6893     { Bad_Opcode },
6894     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6895     { Bad_Opcode },
6896     /* b8 */
6897     { Bad_Opcode },
6898     { Bad_Opcode },
6899     { Bad_Opcode },
6900     { Bad_Opcode },
6901     { Bad_Opcode },
6902     { Bad_Opcode },
6903     { Bad_Opcode },
6904     { Bad_Opcode },
6905     /* c0 */
6906     { "vprotb",         { XM, Vex_2src_1, Ib } },
6907     { "vprotw",         { XM, Vex_2src_1, Ib } },
6908     { "vprotd",         { XM, Vex_2src_1, Ib } },
6909     { "vprotq",         { XM, Vex_2src_1, Ib } },
6910     { Bad_Opcode },
6911     { Bad_Opcode },
6912     { Bad_Opcode },
6913     { Bad_Opcode },
6914     /* c8 */
6915     { Bad_Opcode },
6916     { Bad_Opcode },
6917     { Bad_Opcode },
6918     { Bad_Opcode },
6919     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
6920     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
6921     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
6922     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
6923     /* d0 */
6924     { Bad_Opcode },
6925     { Bad_Opcode },
6926     { Bad_Opcode },
6927     { Bad_Opcode },
6928     { Bad_Opcode },
6929     { Bad_Opcode },
6930     { Bad_Opcode },
6931     { Bad_Opcode },
6932     /* d8 */
6933     { Bad_Opcode },
6934     { Bad_Opcode },
6935     { Bad_Opcode },
6936     { Bad_Opcode },
6937     { Bad_Opcode },
6938     { Bad_Opcode },
6939     { Bad_Opcode },
6940     { Bad_Opcode },
6941     /* e0 */
6942     { Bad_Opcode },
6943     { Bad_Opcode },
6944     { Bad_Opcode },
6945     { Bad_Opcode },
6946     { Bad_Opcode },
6947     { Bad_Opcode },
6948     { Bad_Opcode },
6949     { Bad_Opcode },
6950     /* e8 */
6951     { Bad_Opcode },
6952     { Bad_Opcode },
6953     { Bad_Opcode },
6954     { Bad_Opcode },
6955     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
6956     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
6957     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
6958     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
6959     /* f0 */
6960     { Bad_Opcode },
6961     { Bad_Opcode },
6962     { Bad_Opcode },
6963     { Bad_Opcode },
6964     { Bad_Opcode },
6965     { Bad_Opcode },
6966     { Bad_Opcode },
6967     { Bad_Opcode },
6968     /* f8 */
6969     { Bad_Opcode },
6970     { Bad_Opcode },
6971     { Bad_Opcode },
6972     { Bad_Opcode },
6973     { Bad_Opcode },
6974     { Bad_Opcode },
6975     { Bad_Opcode },
6976     { Bad_Opcode },
6977   },
6978   /* XOP_09 */
6979   {
6980     /* 00 */
6981     { Bad_Opcode },
6982     { REG_TABLE (REG_XOP_TBM_01) },
6983     { REG_TABLE (REG_XOP_TBM_02) },
6984     { Bad_Opcode },
6985     { Bad_Opcode },
6986     { Bad_Opcode },
6987     { Bad_Opcode },
6988     { Bad_Opcode },
6989     /* 08 */
6990     { Bad_Opcode },
6991     { Bad_Opcode },
6992     { Bad_Opcode },
6993     { Bad_Opcode },
6994     { Bad_Opcode },
6995     { Bad_Opcode },
6996     { Bad_Opcode },
6997     { Bad_Opcode },
6998     /* 10 */
6999     { Bad_Opcode },
7000     { Bad_Opcode },
7001     { REG_TABLE (REG_XOP_LWPCB) },
7002     { Bad_Opcode },
7003     { Bad_Opcode },
7004     { Bad_Opcode },
7005     { Bad_Opcode },
7006     { Bad_Opcode },
7007     /* 18 */
7008     { Bad_Opcode },
7009     { Bad_Opcode },
7010     { Bad_Opcode },
7011     { Bad_Opcode },
7012     { Bad_Opcode },
7013     { Bad_Opcode },
7014     { Bad_Opcode },
7015     { Bad_Opcode },
7016     /* 20 */
7017     { Bad_Opcode },
7018     { Bad_Opcode },
7019     { Bad_Opcode },
7020     { Bad_Opcode },
7021     { Bad_Opcode },
7022     { Bad_Opcode },
7023     { Bad_Opcode },
7024     { Bad_Opcode },
7025     /* 28 */
7026     { Bad_Opcode },
7027     { Bad_Opcode },
7028     { Bad_Opcode },
7029     { Bad_Opcode },
7030     { Bad_Opcode },
7031     { Bad_Opcode },
7032     { Bad_Opcode },
7033     { Bad_Opcode },
7034     /* 30 */
7035     { Bad_Opcode },
7036     { Bad_Opcode },
7037     { Bad_Opcode },
7038     { Bad_Opcode },
7039     { Bad_Opcode },
7040     { Bad_Opcode },
7041     { Bad_Opcode },
7042     { Bad_Opcode },
7043     /* 38 */
7044     { Bad_Opcode },
7045     { Bad_Opcode },
7046     { Bad_Opcode },
7047     { Bad_Opcode },
7048     { Bad_Opcode },
7049     { Bad_Opcode },
7050     { Bad_Opcode },
7051     { Bad_Opcode },
7052     /* 40 */
7053     { Bad_Opcode },
7054     { Bad_Opcode },
7055     { Bad_Opcode },
7056     { Bad_Opcode },
7057     { Bad_Opcode },
7058     { Bad_Opcode },
7059     { Bad_Opcode },
7060     { Bad_Opcode },
7061     /* 48 */
7062     { Bad_Opcode },
7063     { Bad_Opcode },
7064     { Bad_Opcode },
7065     { Bad_Opcode },
7066     { Bad_Opcode },
7067     { Bad_Opcode },
7068     { Bad_Opcode },
7069     { Bad_Opcode },
7070     /* 50 */
7071     { Bad_Opcode },
7072     { Bad_Opcode },
7073     { Bad_Opcode },
7074     { Bad_Opcode },
7075     { Bad_Opcode },
7076     { Bad_Opcode },
7077     { Bad_Opcode },
7078     { Bad_Opcode },
7079     /* 58 */
7080     { Bad_Opcode },
7081     { Bad_Opcode },
7082     { Bad_Opcode },
7083     { Bad_Opcode },
7084     { Bad_Opcode },
7085     { Bad_Opcode },
7086     { Bad_Opcode },
7087     { Bad_Opcode },
7088     /* 60 */
7089     { Bad_Opcode },
7090     { Bad_Opcode },
7091     { Bad_Opcode },
7092     { Bad_Opcode },
7093     { Bad_Opcode },
7094     { Bad_Opcode },
7095     { Bad_Opcode },
7096     { Bad_Opcode },
7097     /* 68 */
7098     { Bad_Opcode },
7099     { Bad_Opcode },
7100     { Bad_Opcode },
7101     { Bad_Opcode },
7102     { Bad_Opcode },
7103     { Bad_Opcode },
7104     { Bad_Opcode },
7105     { Bad_Opcode },
7106     /* 70 */
7107     { Bad_Opcode },
7108     { Bad_Opcode },
7109     { Bad_Opcode },
7110     { Bad_Opcode },
7111     { Bad_Opcode },
7112     { Bad_Opcode },
7113     { Bad_Opcode },
7114     { Bad_Opcode },
7115     /* 78 */
7116     { Bad_Opcode },
7117     { Bad_Opcode },
7118     { Bad_Opcode },
7119     { Bad_Opcode },
7120     { Bad_Opcode },
7121     { Bad_Opcode },
7122     { Bad_Opcode },
7123     { Bad_Opcode },
7124     /* 80 */
7125     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
7126     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
7127     { "vfrczss",        { XM, EXd } },
7128     { "vfrczsd",        { XM, EXq } },
7129     { Bad_Opcode },
7130     { Bad_Opcode },
7131     { Bad_Opcode },
7132     { Bad_Opcode },
7133     /* 88 */
7134     { Bad_Opcode },
7135     { Bad_Opcode },
7136     { Bad_Opcode },
7137     { Bad_Opcode },
7138     { Bad_Opcode },
7139     { Bad_Opcode },
7140     { Bad_Opcode },
7141     { Bad_Opcode },
7142     /* 90 */
7143     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 } },
7144     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 } },
7145     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 } },
7146     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 } },
7147     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 } },
7148     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 } },
7149     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 } },
7150     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 } },
7151     /* 98 */
7152     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 } },
7153     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 } },
7154     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 } },
7155     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 } },
7156     { Bad_Opcode },
7157     { Bad_Opcode },
7158     { Bad_Opcode },
7159     { Bad_Opcode },
7160     /* a0 */
7161     { Bad_Opcode },
7162     { Bad_Opcode },
7163     { Bad_Opcode },
7164     { Bad_Opcode },
7165     { Bad_Opcode },
7166     { Bad_Opcode },
7167     { Bad_Opcode },
7168     { Bad_Opcode },
7169     /* a8 */
7170     { Bad_Opcode },
7171     { Bad_Opcode },
7172     { Bad_Opcode },
7173     { Bad_Opcode },
7174     { Bad_Opcode },
7175     { Bad_Opcode },
7176     { Bad_Opcode },
7177     { Bad_Opcode },
7178     /* b0 */
7179     { Bad_Opcode },
7180     { Bad_Opcode },
7181     { Bad_Opcode },
7182     { Bad_Opcode },
7183     { Bad_Opcode },
7184     { Bad_Opcode },
7185     { Bad_Opcode },
7186     { Bad_Opcode },
7187     /* b8 */
7188     { Bad_Opcode },
7189     { Bad_Opcode },
7190     { Bad_Opcode },
7191     { Bad_Opcode },
7192     { Bad_Opcode },
7193     { Bad_Opcode },
7194     { Bad_Opcode },
7195     { Bad_Opcode },
7196     /* c0 */
7197     { Bad_Opcode },
7198     { "vphaddbw",       { XM, EXxmm } },
7199     { "vphaddbd",       { XM, EXxmm } },
7200     { "vphaddbq",       { XM, EXxmm } },
7201     { Bad_Opcode },
7202     { Bad_Opcode },
7203     { "vphaddwd",       { XM, EXxmm } },
7204     { "vphaddwq",       { XM, EXxmm } },
7205     /* c8 */
7206     { Bad_Opcode },
7207     { Bad_Opcode },
7208     { Bad_Opcode },
7209     { "vphadddq",       { XM, EXxmm } },
7210     { Bad_Opcode },
7211     { Bad_Opcode },
7212     { Bad_Opcode },
7213     { Bad_Opcode },
7214     /* d0 */
7215     { Bad_Opcode },
7216     { "vphaddubw",      { XM, EXxmm } },
7217     { "vphaddubd",      { XM, EXxmm } },
7218     { "vphaddubq",      { XM, EXxmm } },
7219     { Bad_Opcode },
7220     { Bad_Opcode },
7221     { "vphadduwd",      { XM, EXxmm } },
7222     { "vphadduwq",      { XM, EXxmm } },
7223     /* d8 */
7224     { Bad_Opcode },
7225     { Bad_Opcode },
7226     { Bad_Opcode },
7227     { "vphaddudq",      { XM, EXxmm } },
7228     { Bad_Opcode },
7229     { Bad_Opcode },
7230     { Bad_Opcode },
7231     { Bad_Opcode },
7232     /* e0 */
7233     { Bad_Opcode },
7234     { "vphsubbw",       { XM, EXxmm } },
7235     { "vphsubwd",       { XM, EXxmm } },
7236     { "vphsubdq",       { XM, EXxmm } },
7237     { Bad_Opcode },
7238     { Bad_Opcode },
7239     { Bad_Opcode },
7240     { Bad_Opcode },
7241     /* e8 */
7242     { Bad_Opcode },
7243     { Bad_Opcode },
7244     { Bad_Opcode },
7245     { Bad_Opcode },
7246     { Bad_Opcode },
7247     { Bad_Opcode },
7248     { Bad_Opcode },
7249     { Bad_Opcode },
7250     /* f0 */
7251     { Bad_Opcode },
7252     { Bad_Opcode },
7253     { Bad_Opcode },
7254     { Bad_Opcode },
7255     { Bad_Opcode },
7256     { Bad_Opcode },
7257     { Bad_Opcode },
7258     { Bad_Opcode },
7259     /* f8 */
7260     { Bad_Opcode },
7261     { Bad_Opcode },
7262     { Bad_Opcode },
7263     { Bad_Opcode },
7264     { Bad_Opcode },
7265     { Bad_Opcode },
7266     { Bad_Opcode },
7267     { Bad_Opcode },
7268   },
7269   /* XOP_0A */
7270   {
7271     /* 00 */
7272     { Bad_Opcode },
7273     { Bad_Opcode },
7274     { Bad_Opcode },
7275     { Bad_Opcode },
7276     { Bad_Opcode },
7277     { Bad_Opcode },
7278     { Bad_Opcode },
7279     { Bad_Opcode },
7280     /* 08 */
7281     { Bad_Opcode },
7282     { Bad_Opcode },
7283     { Bad_Opcode },
7284     { Bad_Opcode },
7285     { Bad_Opcode },
7286     { Bad_Opcode },
7287     { Bad_Opcode },
7288     { Bad_Opcode },
7289     /* 10 */
7290     { "bextr",  { Gv, Ev, Iq } },
7291     { Bad_Opcode },
7292     { REG_TABLE (REG_XOP_LWP) },
7293     { Bad_Opcode },
7294     { Bad_Opcode },
7295     { Bad_Opcode },
7296     { Bad_Opcode },
7297     { Bad_Opcode },
7298     /* 18 */
7299     { Bad_Opcode },
7300     { Bad_Opcode },
7301     { Bad_Opcode },
7302     { Bad_Opcode },
7303     { Bad_Opcode },
7304     { Bad_Opcode },
7305     { Bad_Opcode },
7306     { Bad_Opcode },
7307     /* 20 */
7308     { Bad_Opcode },
7309     { Bad_Opcode },
7310     { Bad_Opcode },
7311     { Bad_Opcode },
7312     { Bad_Opcode },
7313     { Bad_Opcode },
7314     { Bad_Opcode },
7315     { Bad_Opcode },
7316     /* 28 */
7317     { Bad_Opcode },
7318     { Bad_Opcode },
7319     { Bad_Opcode },
7320     { Bad_Opcode },
7321     { Bad_Opcode },
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     { Bad_Opcode },
7325     /* 30 */
7326     { Bad_Opcode },
7327     { Bad_Opcode },
7328     { Bad_Opcode },
7329     { Bad_Opcode },
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     { Bad_Opcode },
7334     /* 38 */
7335     { Bad_Opcode },
7336     { Bad_Opcode },
7337     { Bad_Opcode },
7338     { Bad_Opcode },
7339     { Bad_Opcode },
7340     { Bad_Opcode },
7341     { Bad_Opcode },
7342     { Bad_Opcode },
7343     /* 40 */
7344     { Bad_Opcode },
7345     { Bad_Opcode },
7346     { Bad_Opcode },
7347     { Bad_Opcode },
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     { Bad_Opcode },
7352     /* 48 */
7353     { Bad_Opcode },
7354     { Bad_Opcode },
7355     { Bad_Opcode },
7356     { Bad_Opcode },
7357     { Bad_Opcode },
7358     { Bad_Opcode },
7359     { Bad_Opcode },
7360     { Bad_Opcode },
7361     /* 50 */
7362     { Bad_Opcode },
7363     { Bad_Opcode },
7364     { Bad_Opcode },
7365     { Bad_Opcode },
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     { Bad_Opcode },
7370     /* 58 */
7371     { Bad_Opcode },
7372     { Bad_Opcode },
7373     { Bad_Opcode },
7374     { Bad_Opcode },
7375     { Bad_Opcode },
7376     { Bad_Opcode },
7377     { Bad_Opcode },
7378     { Bad_Opcode },
7379     /* 60 */
7380     { Bad_Opcode },
7381     { Bad_Opcode },
7382     { Bad_Opcode },
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     /* 68 */
7389     { Bad_Opcode },
7390     { Bad_Opcode },
7391     { Bad_Opcode },
7392     { Bad_Opcode },
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     { Bad_Opcode },
7396     { Bad_Opcode },
7397     /* 70 */
7398     { Bad_Opcode },
7399     { Bad_Opcode },
7400     { Bad_Opcode },
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     /* 78 */
7407     { Bad_Opcode },
7408     { Bad_Opcode },
7409     { Bad_Opcode },
7410     { Bad_Opcode },
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413     { Bad_Opcode },
7414     { Bad_Opcode },
7415     /* 80 */
7416     { Bad_Opcode },
7417     { Bad_Opcode },
7418     { Bad_Opcode },
7419     { Bad_Opcode },
7420     { Bad_Opcode },
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423     { Bad_Opcode },
7424     /* 88 */
7425     { Bad_Opcode },
7426     { Bad_Opcode },
7427     { Bad_Opcode },
7428     { Bad_Opcode },
7429     { Bad_Opcode },
7430     { Bad_Opcode },
7431     { Bad_Opcode },
7432     { Bad_Opcode },
7433     /* 90 */
7434     { Bad_Opcode },
7435     { Bad_Opcode },
7436     { Bad_Opcode },
7437     { Bad_Opcode },
7438     { Bad_Opcode },
7439     { Bad_Opcode },
7440     { Bad_Opcode },
7441     { Bad_Opcode },
7442     /* 98 */
7443     { Bad_Opcode },
7444     { Bad_Opcode },
7445     { Bad_Opcode },
7446     { Bad_Opcode },
7447     { Bad_Opcode },
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     /* a0 */
7452     { Bad_Opcode },
7453     { Bad_Opcode },
7454     { Bad_Opcode },
7455     { Bad_Opcode },
7456     { Bad_Opcode },
7457     { Bad_Opcode },
7458     { Bad_Opcode },
7459     { Bad_Opcode },
7460     /* a8 */
7461     { Bad_Opcode },
7462     { Bad_Opcode },
7463     { Bad_Opcode },
7464     { Bad_Opcode },
7465     { Bad_Opcode },
7466     { Bad_Opcode },
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469     /* b0 */
7470     { Bad_Opcode },
7471     { Bad_Opcode },
7472     { Bad_Opcode },
7473     { Bad_Opcode },
7474     { Bad_Opcode },
7475     { Bad_Opcode },
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     /* b8 */
7479     { Bad_Opcode },
7480     { Bad_Opcode },
7481     { Bad_Opcode },
7482     { Bad_Opcode },
7483     { Bad_Opcode },
7484     { Bad_Opcode },
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     /* c0 */
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     { Bad_Opcode },
7491     { Bad_Opcode },
7492     { Bad_Opcode },
7493     { Bad_Opcode },
7494     { Bad_Opcode },
7495     { Bad_Opcode },
7496     /* c8 */
7497     { Bad_Opcode },
7498     { Bad_Opcode },
7499     { Bad_Opcode },
7500     { Bad_Opcode },
7501     { Bad_Opcode },
7502     { Bad_Opcode },
7503     { Bad_Opcode },
7504     { Bad_Opcode },
7505     /* d0 */
7506     { Bad_Opcode },
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     { Bad_Opcode },
7510     { Bad_Opcode },
7511     { Bad_Opcode },
7512     { Bad_Opcode },
7513     { Bad_Opcode },
7514     /* d8 */
7515     { Bad_Opcode },
7516     { Bad_Opcode },
7517     { Bad_Opcode },
7518     { Bad_Opcode },
7519     { Bad_Opcode },
7520     { Bad_Opcode },
7521     { Bad_Opcode },
7522     { Bad_Opcode },
7523     /* e0 */
7524     { Bad_Opcode },
7525     { Bad_Opcode },
7526     { Bad_Opcode },
7527     { Bad_Opcode },
7528     { Bad_Opcode },
7529     { Bad_Opcode },
7530     { Bad_Opcode },
7531     { Bad_Opcode },
7532     /* e8 */
7533     { Bad_Opcode },
7534     { Bad_Opcode },
7535     { Bad_Opcode },
7536     { Bad_Opcode },
7537     { Bad_Opcode },
7538     { Bad_Opcode },
7539     { Bad_Opcode },
7540     { Bad_Opcode },
7541     /* f0 */
7542     { Bad_Opcode },
7543     { Bad_Opcode },
7544     { Bad_Opcode },
7545     { Bad_Opcode },
7546     { Bad_Opcode },
7547     { Bad_Opcode },
7548     { Bad_Opcode },
7549     { Bad_Opcode },
7550     /* f8 */
7551     { Bad_Opcode },
7552     { Bad_Opcode },
7553     { Bad_Opcode },
7554     { Bad_Opcode },
7555     { Bad_Opcode },
7556     { Bad_Opcode },
7557     { Bad_Opcode },
7558     { Bad_Opcode },
7559   },
7560 };
7561
7562 static const struct dis386 vex_table[][256] = {
7563   /* VEX_0F */
7564   {
7565     /* 00 */
7566     { Bad_Opcode },
7567     { Bad_Opcode },
7568     { Bad_Opcode },
7569     { Bad_Opcode },
7570     { Bad_Opcode },
7571     { Bad_Opcode },
7572     { Bad_Opcode },
7573     { Bad_Opcode },
7574     /* 08 */
7575     { Bad_Opcode },
7576     { Bad_Opcode },
7577     { Bad_Opcode },
7578     { Bad_Opcode },
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     { Bad_Opcode },
7582     { Bad_Opcode },
7583     /* 10 */
7584     { PREFIX_TABLE (PREFIX_VEX_0F10) },
7585     { PREFIX_TABLE (PREFIX_VEX_0F11) },
7586     { PREFIX_TABLE (PREFIX_VEX_0F12) },
7587     { MOD_TABLE (MOD_VEX_0F13) },
7588     { VEX_W_TABLE (VEX_W_0F14) },
7589     { VEX_W_TABLE (VEX_W_0F15) },
7590     { PREFIX_TABLE (PREFIX_VEX_0F16) },
7591     { MOD_TABLE (MOD_VEX_0F17) },
7592     /* 18 */
7593     { Bad_Opcode },
7594     { Bad_Opcode },
7595     { Bad_Opcode },
7596     { Bad_Opcode },
7597     { Bad_Opcode },
7598     { Bad_Opcode },
7599     { Bad_Opcode },
7600     { Bad_Opcode },
7601     /* 20 */
7602     { Bad_Opcode },
7603     { Bad_Opcode },
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     { Bad_Opcode },
7608     { Bad_Opcode },
7609     { Bad_Opcode },
7610     /* 28 */
7611     { VEX_W_TABLE (VEX_W_0F28) },
7612     { VEX_W_TABLE (VEX_W_0F29) },
7613     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
7614     { MOD_TABLE (MOD_VEX_0F2B) },
7615     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
7616     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
7617     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
7618     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
7619     /* 30 */
7620     { Bad_Opcode },
7621     { Bad_Opcode },
7622     { Bad_Opcode },
7623     { Bad_Opcode },
7624     { Bad_Opcode },
7625     { Bad_Opcode },
7626     { Bad_Opcode },
7627     { Bad_Opcode },
7628     /* 38 */
7629     { Bad_Opcode },
7630     { Bad_Opcode },
7631     { Bad_Opcode },
7632     { Bad_Opcode },
7633     { Bad_Opcode },
7634     { Bad_Opcode },
7635     { Bad_Opcode },
7636     { Bad_Opcode },
7637     /* 40 */
7638     { Bad_Opcode },
7639     { Bad_Opcode },
7640     { Bad_Opcode },
7641     { Bad_Opcode },
7642     { Bad_Opcode },
7643     { Bad_Opcode },
7644     { Bad_Opcode },
7645     { Bad_Opcode },
7646     /* 48 */
7647     { Bad_Opcode },
7648     { Bad_Opcode },
7649     { Bad_Opcode },
7650     { Bad_Opcode },
7651     { Bad_Opcode },
7652     { Bad_Opcode },
7653     { Bad_Opcode },
7654     { Bad_Opcode },
7655     /* 50 */
7656     { MOD_TABLE (MOD_VEX_0F50) },
7657     { PREFIX_TABLE (PREFIX_VEX_0F51) },
7658     { PREFIX_TABLE (PREFIX_VEX_0F52) },
7659     { PREFIX_TABLE (PREFIX_VEX_0F53) },
7660     { "vandpX",         { XM, Vex, EXx } },
7661     { "vandnpX",        { XM, Vex, EXx } },
7662     { "vorpX",          { XM, Vex, EXx } },
7663     { "vxorpX",         { XM, Vex, EXx } },
7664     /* 58 */
7665     { PREFIX_TABLE (PREFIX_VEX_0F58) },
7666     { PREFIX_TABLE (PREFIX_VEX_0F59) },
7667     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
7668     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
7669     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
7670     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
7671     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
7672     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
7673     /* 60 */
7674     { PREFIX_TABLE (PREFIX_VEX_0F60) },
7675     { PREFIX_TABLE (PREFIX_VEX_0F61) },
7676     { PREFIX_TABLE (PREFIX_VEX_0F62) },
7677     { PREFIX_TABLE (PREFIX_VEX_0F63) },
7678     { PREFIX_TABLE (PREFIX_VEX_0F64) },
7679     { PREFIX_TABLE (PREFIX_VEX_0F65) },
7680     { PREFIX_TABLE (PREFIX_VEX_0F66) },
7681     { PREFIX_TABLE (PREFIX_VEX_0F67) },
7682     /* 68 */
7683     { PREFIX_TABLE (PREFIX_VEX_0F68) },
7684     { PREFIX_TABLE (PREFIX_VEX_0F69) },
7685     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
7686     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
7687     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
7688     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
7689     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
7690     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
7691     /* 70 */
7692     { PREFIX_TABLE (PREFIX_VEX_0F70) },
7693     { REG_TABLE (REG_VEX_0F71) },
7694     { REG_TABLE (REG_VEX_0F72) },
7695     { REG_TABLE (REG_VEX_0F73) },
7696     { PREFIX_TABLE (PREFIX_VEX_0F74) },
7697     { PREFIX_TABLE (PREFIX_VEX_0F75) },
7698     { PREFIX_TABLE (PREFIX_VEX_0F76) },
7699     { PREFIX_TABLE (PREFIX_VEX_0F77) },
7700     /* 78 */
7701     { Bad_Opcode },
7702     { Bad_Opcode },
7703     { Bad_Opcode },
7704     { Bad_Opcode },
7705     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
7706     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
7707     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
7708     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
7709     /* 80 */
7710     { Bad_Opcode },
7711     { Bad_Opcode },
7712     { Bad_Opcode },
7713     { Bad_Opcode },
7714     { Bad_Opcode },
7715     { Bad_Opcode },
7716     { Bad_Opcode },
7717     { Bad_Opcode },
7718     /* 88 */
7719     { Bad_Opcode },
7720     { Bad_Opcode },
7721     { Bad_Opcode },
7722     { Bad_Opcode },
7723     { Bad_Opcode },
7724     { Bad_Opcode },
7725     { Bad_Opcode },
7726     { Bad_Opcode },
7727     /* 90 */
7728     { Bad_Opcode },
7729     { Bad_Opcode },
7730     { Bad_Opcode },
7731     { Bad_Opcode },
7732     { Bad_Opcode },
7733     { Bad_Opcode },
7734     { Bad_Opcode },
7735     { Bad_Opcode },
7736     /* 98 */
7737     { Bad_Opcode },
7738     { Bad_Opcode },
7739     { Bad_Opcode },
7740     { Bad_Opcode },
7741     { Bad_Opcode },
7742     { Bad_Opcode },
7743     { Bad_Opcode },
7744     { Bad_Opcode },
7745     /* a0 */
7746     { Bad_Opcode },
7747     { Bad_Opcode },
7748     { Bad_Opcode },
7749     { Bad_Opcode },
7750     { Bad_Opcode },
7751     { Bad_Opcode },
7752     { Bad_Opcode },
7753     { Bad_Opcode },
7754     /* a8 */
7755     { Bad_Opcode },
7756     { Bad_Opcode },
7757     { Bad_Opcode },
7758     { Bad_Opcode },
7759     { Bad_Opcode },
7760     { Bad_Opcode },
7761     { REG_TABLE (REG_VEX_0FAE) },
7762     { Bad_Opcode },
7763     /* b0 */
7764     { Bad_Opcode },
7765     { Bad_Opcode },
7766     { Bad_Opcode },
7767     { Bad_Opcode },
7768     { Bad_Opcode },
7769     { Bad_Opcode },
7770     { Bad_Opcode },
7771     { Bad_Opcode },
7772     /* b8 */
7773     { Bad_Opcode },
7774     { Bad_Opcode },
7775     { Bad_Opcode },
7776     { Bad_Opcode },
7777     { Bad_Opcode },
7778     { Bad_Opcode },
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     /* c0 */
7782     { Bad_Opcode },
7783     { Bad_Opcode },
7784     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
7785     { Bad_Opcode },
7786     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
7787     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
7788     { "vshufpX",        { XM, Vex, EXx, Ib } },
7789     { Bad_Opcode },
7790     /* c8 */
7791     { Bad_Opcode },
7792     { Bad_Opcode },
7793     { Bad_Opcode },
7794     { Bad_Opcode },
7795     { Bad_Opcode },
7796     { Bad_Opcode },
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     /* d0 */
7800     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
7801     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
7802     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
7803     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
7804     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
7805     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
7806     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
7807     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
7808     /* d8 */
7809     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
7810     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
7811     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
7812     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
7813     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
7814     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
7815     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
7816     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
7817     /* e0 */
7818     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
7819     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
7820     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
7821     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
7822     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
7823     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
7824     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
7825     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
7826     /* e8 */
7827     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
7828     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
7829     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
7830     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
7831     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
7832     { PREFIX_TABLE (PREFIX_VEX_0FED) },
7833     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
7834     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
7835     /* f0 */
7836     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
7837     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
7838     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
7839     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
7840     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
7841     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
7842     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
7843     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
7844     /* f8 */
7845     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
7846     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
7847     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
7848     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
7849     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
7850     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
7851     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
7852     { Bad_Opcode },
7853   },
7854   /* VEX_0F38 */
7855   {
7856     /* 00 */
7857     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
7858     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
7859     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
7860     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
7861     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
7862     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
7863     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
7864     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
7865     /* 08 */
7866     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
7867     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
7868     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
7869     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
7870     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
7871     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
7872     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
7873     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
7874     /* 10 */
7875     { Bad_Opcode },
7876     { Bad_Opcode },
7877     { Bad_Opcode },
7878     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
7879     { Bad_Opcode },
7880     { Bad_Opcode },
7881     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
7882     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
7883     /* 18 */
7884     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
7885     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
7886     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
7887     { Bad_Opcode },
7888     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
7889     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
7890     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
7891     { Bad_Opcode },
7892     /* 20 */
7893     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
7894     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
7895     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
7896     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
7897     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
7898     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
7899     { Bad_Opcode },
7900     { Bad_Opcode },
7901     /* 28 */
7902     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
7903     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
7904     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
7905     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
7906     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
7907     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
7908     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
7909     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
7910     /* 30 */
7911     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
7912     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
7913     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
7914     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
7915     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
7916     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
7917     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
7918     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
7919     /* 38 */
7920     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
7921     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
7922     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
7923     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
7924     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
7925     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
7926     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
7927     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
7928     /* 40 */
7929     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
7930     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
7931     { Bad_Opcode },
7932     { Bad_Opcode },
7933     { Bad_Opcode },
7934     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
7935     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
7936     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
7937     /* 48 */
7938     { Bad_Opcode },
7939     { Bad_Opcode },
7940     { Bad_Opcode },
7941     { Bad_Opcode },
7942     { Bad_Opcode },
7943     { Bad_Opcode },
7944     { Bad_Opcode },
7945     { Bad_Opcode },
7946     /* 50 */
7947     { Bad_Opcode },
7948     { Bad_Opcode },
7949     { Bad_Opcode },
7950     { Bad_Opcode },
7951     { Bad_Opcode },
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     { Bad_Opcode },
7955     /* 58 */
7956     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
7957     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
7958     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
7959     { Bad_Opcode },
7960     { Bad_Opcode },
7961     { Bad_Opcode },
7962     { Bad_Opcode },
7963     { Bad_Opcode },
7964     /* 60 */
7965     { Bad_Opcode },
7966     { Bad_Opcode },
7967     { Bad_Opcode },
7968     { Bad_Opcode },
7969     { Bad_Opcode },
7970     { Bad_Opcode },
7971     { Bad_Opcode },
7972     { Bad_Opcode },
7973     /* 68 */
7974     { Bad_Opcode },
7975     { Bad_Opcode },
7976     { Bad_Opcode },
7977     { Bad_Opcode },
7978     { Bad_Opcode },
7979     { Bad_Opcode },
7980     { Bad_Opcode },
7981     { Bad_Opcode },
7982     /* 70 */
7983     { Bad_Opcode },
7984     { Bad_Opcode },
7985     { Bad_Opcode },
7986     { Bad_Opcode },
7987     { Bad_Opcode },
7988     { Bad_Opcode },
7989     { Bad_Opcode },
7990     { Bad_Opcode },
7991     /* 78 */
7992     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
7993     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
7994     { Bad_Opcode },
7995     { Bad_Opcode },
7996     { Bad_Opcode },
7997     { Bad_Opcode },
7998     { Bad_Opcode },
7999     { Bad_Opcode },
8000     /* 80 */
8001     { Bad_Opcode },
8002     { Bad_Opcode },
8003     { Bad_Opcode },
8004     { Bad_Opcode },
8005     { Bad_Opcode },
8006     { Bad_Opcode },
8007     { Bad_Opcode },
8008     { Bad_Opcode },
8009     /* 88 */
8010     { Bad_Opcode },
8011     { Bad_Opcode },
8012     { Bad_Opcode },
8013     { Bad_Opcode },
8014     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
8015     { Bad_Opcode },
8016     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
8017     { Bad_Opcode },
8018     /* 90 */
8019     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
8020     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
8021     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
8022     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
8023     { Bad_Opcode },
8024     { Bad_Opcode },
8025     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
8026     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
8027     /* 98 */
8028     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
8029     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
8030     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
8031     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
8032     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
8033     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
8034     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
8035     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
8036     /* a0 */
8037     { Bad_Opcode },
8038     { Bad_Opcode },
8039     { Bad_Opcode },
8040     { Bad_Opcode },
8041     { Bad_Opcode },
8042     { Bad_Opcode },
8043     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
8044     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
8045     /* a8 */
8046     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
8047     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
8048     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
8049     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
8050     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
8051     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
8052     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
8053     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
8054     /* b0 */
8055     { Bad_Opcode },
8056     { Bad_Opcode },
8057     { Bad_Opcode },
8058     { Bad_Opcode },
8059     { Bad_Opcode },
8060     { Bad_Opcode },
8061     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
8062     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
8063     /* b8 */
8064     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
8065     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
8066     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
8067     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
8068     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
8069     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
8070     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
8071     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
8072     /* c0 */
8073     { Bad_Opcode },
8074     { Bad_Opcode },
8075     { Bad_Opcode },
8076     { Bad_Opcode },
8077     { Bad_Opcode },
8078     { Bad_Opcode },
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     /* c8 */
8082     { Bad_Opcode },
8083     { Bad_Opcode },
8084     { Bad_Opcode },
8085     { Bad_Opcode },
8086     { Bad_Opcode },
8087     { Bad_Opcode },
8088     { Bad_Opcode },
8089     { Bad_Opcode },
8090     /* d0 */
8091     { Bad_Opcode },
8092     { Bad_Opcode },
8093     { Bad_Opcode },
8094     { Bad_Opcode },
8095     { Bad_Opcode },
8096     { Bad_Opcode },
8097     { Bad_Opcode },
8098     { Bad_Opcode },
8099     /* d8 */
8100     { Bad_Opcode },
8101     { Bad_Opcode },
8102     { Bad_Opcode },
8103     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
8104     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
8105     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
8106     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
8107     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
8108     /* e0 */
8109     { Bad_Opcode },
8110     { Bad_Opcode },
8111     { Bad_Opcode },
8112     { Bad_Opcode },
8113     { Bad_Opcode },
8114     { Bad_Opcode },
8115     { Bad_Opcode },
8116     { Bad_Opcode },
8117     /* e8 */
8118     { Bad_Opcode },
8119     { Bad_Opcode },
8120     { Bad_Opcode },
8121     { Bad_Opcode },
8122     { Bad_Opcode },
8123     { Bad_Opcode },
8124     { Bad_Opcode },
8125     { Bad_Opcode },
8126     /* f0 */
8127     { Bad_Opcode },
8128     { Bad_Opcode },
8129     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
8130     { REG_TABLE (REG_VEX_0F38F3) },
8131     { Bad_Opcode },
8132     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
8133     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
8134     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
8135     /* f8 */
8136     { Bad_Opcode },
8137     { Bad_Opcode },
8138     { Bad_Opcode },
8139     { Bad_Opcode },
8140     { Bad_Opcode },
8141     { Bad_Opcode },
8142     { Bad_Opcode },
8143     { Bad_Opcode },
8144   },
8145   /* VEX_0F3A */
8146   {
8147     /* 00 */
8148     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
8149     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
8150     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
8151     { Bad_Opcode },
8152     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
8153     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
8154     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
8155     { Bad_Opcode },
8156     /* 08 */
8157     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
8158     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
8159     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
8160     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
8161     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
8162     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
8163     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
8164     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
8165     /* 10 */
8166     { Bad_Opcode },
8167     { Bad_Opcode },
8168     { Bad_Opcode },
8169     { Bad_Opcode },
8170     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
8171     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
8172     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
8173     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
8174     /* 18 */
8175     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
8176     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
8177     { Bad_Opcode },
8178     { Bad_Opcode },
8179     { Bad_Opcode },
8180     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
8181     { Bad_Opcode },
8182     { Bad_Opcode },
8183     /* 20 */
8184     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
8185     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
8186     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
8187     { Bad_Opcode },
8188     { Bad_Opcode },
8189     { Bad_Opcode },
8190     { Bad_Opcode },
8191     { Bad_Opcode },
8192     /* 28 */
8193     { Bad_Opcode },
8194     { Bad_Opcode },
8195     { Bad_Opcode },
8196     { Bad_Opcode },
8197     { Bad_Opcode },
8198     { Bad_Opcode },
8199     { Bad_Opcode },
8200     { Bad_Opcode },
8201     /* 30 */
8202     { Bad_Opcode },
8203     { Bad_Opcode },
8204     { Bad_Opcode },
8205     { Bad_Opcode },
8206     { Bad_Opcode },
8207     { Bad_Opcode },
8208     { Bad_Opcode },
8209     { Bad_Opcode },
8210     /* 38 */
8211     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
8212     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
8213     { Bad_Opcode },
8214     { Bad_Opcode },
8215     { Bad_Opcode },
8216     { Bad_Opcode },
8217     { Bad_Opcode },
8218     { Bad_Opcode },
8219     /* 40 */
8220     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
8221     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
8222     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
8223     { Bad_Opcode },
8224     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
8225     { Bad_Opcode },
8226     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
8227     { Bad_Opcode },
8228     /* 48 */
8229     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
8230     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
8231     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
8232     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
8233     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
8234     { Bad_Opcode },
8235     { Bad_Opcode },
8236     { Bad_Opcode },
8237     /* 50 */
8238     { Bad_Opcode },
8239     { Bad_Opcode },
8240     { Bad_Opcode },
8241     { Bad_Opcode },
8242     { Bad_Opcode },
8243     { Bad_Opcode },
8244     { Bad_Opcode },
8245     { Bad_Opcode },
8246     /* 58 */
8247     { Bad_Opcode },
8248     { Bad_Opcode },
8249     { Bad_Opcode },
8250     { Bad_Opcode },
8251     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
8252     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
8253     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
8254     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
8255     /* 60 */
8256     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
8257     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
8258     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
8259     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
8260     { Bad_Opcode },
8261     { Bad_Opcode },
8262     { Bad_Opcode },
8263     { Bad_Opcode },
8264     /* 68 */
8265     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
8266     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
8267     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
8268     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
8269     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
8270     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
8271     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
8272     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
8273     /* 70 */
8274     { Bad_Opcode },
8275     { Bad_Opcode },
8276     { Bad_Opcode },
8277     { Bad_Opcode },
8278     { Bad_Opcode },
8279     { Bad_Opcode },
8280     { Bad_Opcode },
8281     { Bad_Opcode },
8282     /* 78 */
8283     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
8284     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
8285     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
8286     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
8287     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
8288     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
8289     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
8290     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
8291     /* 80 */
8292     { Bad_Opcode },
8293     { Bad_Opcode },
8294     { Bad_Opcode },
8295     { Bad_Opcode },
8296     { Bad_Opcode },
8297     { Bad_Opcode },
8298     { Bad_Opcode },
8299     { Bad_Opcode },
8300     /* 88 */
8301     { Bad_Opcode },
8302     { Bad_Opcode },
8303     { Bad_Opcode },
8304     { Bad_Opcode },
8305     { Bad_Opcode },
8306     { Bad_Opcode },
8307     { Bad_Opcode },
8308     { Bad_Opcode },
8309     /* 90 */
8310     { Bad_Opcode },
8311     { Bad_Opcode },
8312     { Bad_Opcode },
8313     { Bad_Opcode },
8314     { Bad_Opcode },
8315     { Bad_Opcode },
8316     { Bad_Opcode },
8317     { Bad_Opcode },
8318     /* 98 */
8319     { Bad_Opcode },
8320     { Bad_Opcode },
8321     { Bad_Opcode },
8322     { Bad_Opcode },
8323     { Bad_Opcode },
8324     { Bad_Opcode },
8325     { Bad_Opcode },
8326     { Bad_Opcode },
8327     /* a0 */
8328     { Bad_Opcode },
8329     { Bad_Opcode },
8330     { Bad_Opcode },
8331     { Bad_Opcode },
8332     { Bad_Opcode },
8333     { Bad_Opcode },
8334     { Bad_Opcode },
8335     { Bad_Opcode },
8336     /* a8 */
8337     { Bad_Opcode },
8338     { Bad_Opcode },
8339     { Bad_Opcode },
8340     { Bad_Opcode },
8341     { Bad_Opcode },
8342     { Bad_Opcode },
8343     { Bad_Opcode },
8344     { Bad_Opcode },
8345     /* b0 */
8346     { Bad_Opcode },
8347     { Bad_Opcode },
8348     { Bad_Opcode },
8349     { Bad_Opcode },
8350     { Bad_Opcode },
8351     { Bad_Opcode },
8352     { Bad_Opcode },
8353     { Bad_Opcode },
8354     /* b8 */
8355     { Bad_Opcode },
8356     { Bad_Opcode },
8357     { Bad_Opcode },
8358     { Bad_Opcode },
8359     { Bad_Opcode },
8360     { Bad_Opcode },
8361     { Bad_Opcode },
8362     { Bad_Opcode },
8363     /* c0 */
8364     { Bad_Opcode },
8365     { Bad_Opcode },
8366     { Bad_Opcode },
8367     { Bad_Opcode },
8368     { Bad_Opcode },
8369     { Bad_Opcode },
8370     { Bad_Opcode },
8371     { Bad_Opcode },
8372     /* c8 */
8373     { Bad_Opcode },
8374     { Bad_Opcode },
8375     { Bad_Opcode },
8376     { Bad_Opcode },
8377     { Bad_Opcode },
8378     { Bad_Opcode },
8379     { Bad_Opcode },
8380     { Bad_Opcode },
8381     /* d0 */
8382     { Bad_Opcode },
8383     { Bad_Opcode },
8384     { Bad_Opcode },
8385     { Bad_Opcode },
8386     { Bad_Opcode },
8387     { Bad_Opcode },
8388     { Bad_Opcode },
8389     { Bad_Opcode },
8390     /* d8 */
8391     { Bad_Opcode },
8392     { Bad_Opcode },
8393     { Bad_Opcode },
8394     { Bad_Opcode },
8395     { Bad_Opcode },
8396     { Bad_Opcode },
8397     { Bad_Opcode },
8398     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
8399     /* e0 */
8400     { Bad_Opcode },
8401     { Bad_Opcode },
8402     { Bad_Opcode },
8403     { Bad_Opcode },
8404     { Bad_Opcode },
8405     { Bad_Opcode },
8406     { Bad_Opcode },
8407     { Bad_Opcode },
8408     /* e8 */
8409     { Bad_Opcode },
8410     { Bad_Opcode },
8411     { Bad_Opcode },
8412     { Bad_Opcode },
8413     { Bad_Opcode },
8414     { Bad_Opcode },
8415     { Bad_Opcode },
8416     { Bad_Opcode },
8417     /* f0 */
8418     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
8419     { Bad_Opcode },
8420     { Bad_Opcode },
8421     { Bad_Opcode },
8422     { Bad_Opcode },
8423     { Bad_Opcode },
8424     { Bad_Opcode },
8425     { Bad_Opcode },
8426     /* f8 */
8427     { Bad_Opcode },
8428     { Bad_Opcode },
8429     { Bad_Opcode },
8430     { Bad_Opcode },
8431     { Bad_Opcode },
8432     { Bad_Opcode },
8433     { Bad_Opcode },
8434     { Bad_Opcode },
8435   },
8436 };
8437
8438 static const struct dis386 vex_len_table[][2] = {
8439   /* VEX_LEN_0F10_P_1 */
8440   {
8441     { VEX_W_TABLE (VEX_W_0F10_P_1) },
8442     { VEX_W_TABLE (VEX_W_0F10_P_1) },
8443   },
8444
8445   /* VEX_LEN_0F10_P_3 */
8446   {
8447     { VEX_W_TABLE (VEX_W_0F10_P_3) },
8448     { VEX_W_TABLE (VEX_W_0F10_P_3) },
8449   },
8450
8451   /* VEX_LEN_0F11_P_1 */
8452   {
8453     { VEX_W_TABLE (VEX_W_0F11_P_1) },
8454     { VEX_W_TABLE (VEX_W_0F11_P_1) },
8455   },
8456
8457   /* VEX_LEN_0F11_P_3 */
8458   {
8459     { VEX_W_TABLE (VEX_W_0F11_P_3) },
8460     { VEX_W_TABLE (VEX_W_0F11_P_3) },
8461   },
8462
8463   /* VEX_LEN_0F12_P_0_M_0 */
8464   {
8465     { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
8466   },
8467
8468   /* VEX_LEN_0F12_P_0_M_1 */
8469   {
8470     { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
8471   },
8472
8473   /* VEX_LEN_0F12_P_2 */
8474   {
8475     { VEX_W_TABLE (VEX_W_0F12_P_2) },
8476   },
8477
8478   /* VEX_LEN_0F13_M_0 */
8479   {
8480     { VEX_W_TABLE (VEX_W_0F13_M_0) },
8481   },
8482
8483   /* VEX_LEN_0F16_P_0_M_0 */
8484   {
8485     { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
8486   },
8487
8488   /* VEX_LEN_0F16_P_0_M_1 */
8489   {
8490     { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
8491   },
8492
8493   /* VEX_LEN_0F16_P_2 */
8494   {
8495     { VEX_W_TABLE (VEX_W_0F16_P_2) },
8496   },
8497
8498   /* VEX_LEN_0F17_M_0 */
8499   {
8500     { VEX_W_TABLE (VEX_W_0F17_M_0) },
8501   },
8502
8503   /* VEX_LEN_0F2A_P_1 */
8504   {
8505     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev } },
8506     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev } },
8507   },
8508
8509   /* VEX_LEN_0F2A_P_3 */
8510   {
8511     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev } },
8512     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev } },
8513   },
8514
8515   /* VEX_LEN_0F2C_P_1 */
8516   {
8517     { "vcvttss2siY",    { Gv, EXdScalar } },
8518     { "vcvttss2siY",    { Gv, EXdScalar } },
8519   },
8520
8521   /* VEX_LEN_0F2C_P_3 */
8522   {
8523     { "vcvttsd2siY",    { Gv, EXqScalar } },
8524     { "vcvttsd2siY",    { Gv, EXqScalar } },
8525   },
8526
8527   /* VEX_LEN_0F2D_P_1 */
8528   {
8529     { "vcvtss2siY",     { Gv, EXdScalar } },
8530     { "vcvtss2siY",     { Gv, EXdScalar } },
8531   },
8532
8533   /* VEX_LEN_0F2D_P_3 */
8534   {
8535     { "vcvtsd2siY",     { Gv, EXqScalar } },
8536     { "vcvtsd2siY",     { Gv, EXqScalar } },
8537   },
8538
8539   /* VEX_LEN_0F2E_P_0 */
8540   {
8541     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
8542     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
8543   },
8544
8545   /* VEX_LEN_0F2E_P_2 */
8546   {
8547     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
8548     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
8549   },
8550
8551   /* VEX_LEN_0F2F_P_0 */
8552   {
8553     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
8554     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
8555   },
8556
8557   /* VEX_LEN_0F2F_P_2 */
8558   {
8559     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
8560     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
8561   },
8562
8563   /* VEX_LEN_0F51_P_1 */
8564   {
8565     { VEX_W_TABLE (VEX_W_0F51_P_1) },
8566     { VEX_W_TABLE (VEX_W_0F51_P_1) },
8567   },
8568
8569   /* VEX_LEN_0F51_P_3 */
8570   {
8571     { VEX_W_TABLE (VEX_W_0F51_P_3) },
8572     { VEX_W_TABLE (VEX_W_0F51_P_3) },
8573   },
8574
8575   /* VEX_LEN_0F52_P_1 */
8576   {
8577     { VEX_W_TABLE (VEX_W_0F52_P_1) },
8578     { VEX_W_TABLE (VEX_W_0F52_P_1) },
8579   },
8580
8581   /* VEX_LEN_0F53_P_1 */
8582   {
8583     { VEX_W_TABLE (VEX_W_0F53_P_1) },
8584     { VEX_W_TABLE (VEX_W_0F53_P_1) },
8585   },
8586
8587   /* VEX_LEN_0F58_P_1 */
8588   {
8589     { VEX_W_TABLE (VEX_W_0F58_P_1) },
8590     { VEX_W_TABLE (VEX_W_0F58_P_1) },
8591   },
8592
8593   /* VEX_LEN_0F58_P_3 */
8594   {
8595     { VEX_W_TABLE (VEX_W_0F58_P_3) },
8596     { VEX_W_TABLE (VEX_W_0F58_P_3) },
8597   },
8598
8599   /* VEX_LEN_0F59_P_1 */
8600   {
8601     { VEX_W_TABLE (VEX_W_0F59_P_1) },
8602     { VEX_W_TABLE (VEX_W_0F59_P_1) },
8603   },
8604
8605   /* VEX_LEN_0F59_P_3 */
8606   {
8607     { VEX_W_TABLE (VEX_W_0F59_P_3) },
8608     { VEX_W_TABLE (VEX_W_0F59_P_3) },
8609   },
8610
8611   /* VEX_LEN_0F5A_P_1 */
8612   {
8613     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
8614     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
8615   },
8616
8617   /* VEX_LEN_0F5A_P_3 */
8618   {
8619     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
8620     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
8621   },
8622
8623   /* VEX_LEN_0F5C_P_1 */
8624   {
8625     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
8626     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
8627   },
8628
8629   /* VEX_LEN_0F5C_P_3 */
8630   {
8631     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
8632     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
8633   },
8634
8635   /* VEX_LEN_0F5D_P_1 */
8636   {
8637     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
8638     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
8639   },
8640
8641   /* VEX_LEN_0F5D_P_3 */
8642   {
8643     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
8644     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
8645   },
8646
8647   /* VEX_LEN_0F5E_P_1 */
8648   {
8649     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
8650     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
8651   },
8652
8653   /* VEX_LEN_0F5E_P_3 */
8654   {
8655     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
8656     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
8657   },
8658
8659   /* VEX_LEN_0F5F_P_1 */
8660   {
8661     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
8662     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
8663   },
8664
8665   /* VEX_LEN_0F5F_P_3 */
8666   {
8667     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
8668     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
8669   },
8670
8671   /* VEX_LEN_0F6E_P_2 */
8672   {
8673     { "vmovK",          { XMScalar, Edq } },
8674     { "vmovK",          { XMScalar, Edq } },
8675   },
8676
8677   /* VEX_LEN_0F7E_P_1 */
8678   {
8679     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
8680     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
8681   },
8682
8683   /* VEX_LEN_0F7E_P_2 */
8684   {
8685     { "vmovK",          { Edq, XMScalar } },
8686     { "vmovK",          { Edq, XMScalar } },
8687   },
8688
8689   /* VEX_LEN_0FAE_R_2_M_0 */
8690   {
8691     { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
8692   },
8693
8694   /* VEX_LEN_0FAE_R_3_M_0 */
8695   {
8696     { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
8697   },
8698
8699   /* VEX_LEN_0FC2_P_1 */
8700   {
8701     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
8702     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
8703   },
8704
8705   /* VEX_LEN_0FC2_P_3 */
8706   {
8707     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
8708     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
8709   },
8710
8711   /* VEX_LEN_0FC4_P_2 */
8712   {
8713     { VEX_W_TABLE (VEX_W_0FC4_P_2) },
8714   },
8715
8716   /* VEX_LEN_0FC5_P_2 */
8717   {
8718     { VEX_W_TABLE (VEX_W_0FC5_P_2) },
8719   },
8720
8721   /* VEX_LEN_0FD6_P_2 */
8722   {
8723     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
8724     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
8725   },
8726
8727   /* VEX_LEN_0FF7_P_2 */
8728   {
8729     { VEX_W_TABLE (VEX_W_0FF7_P_2) },
8730   },
8731
8732   /* VEX_LEN_0F3816_P_2 */
8733   {
8734     { Bad_Opcode },
8735     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
8736   },
8737
8738   /* VEX_LEN_0F3819_P_2 */
8739   {
8740     { Bad_Opcode },
8741     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
8742   },
8743
8744   /* VEX_LEN_0F381A_P_2_M_0 */
8745   {
8746     { Bad_Opcode },
8747     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
8748   },
8749
8750   /* VEX_LEN_0F3836_P_2 */
8751   {
8752     { Bad_Opcode },
8753     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
8754   },
8755
8756   /* VEX_LEN_0F3841_P_2 */
8757   {
8758     { VEX_W_TABLE (VEX_W_0F3841_P_2) },
8759   },
8760
8761   /* VEX_LEN_0F385A_P_2_M_0 */
8762   {
8763     { Bad_Opcode },
8764     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
8765   },
8766
8767   /* VEX_LEN_0F38DB_P_2 */
8768   {
8769     { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
8770   },
8771
8772   /* VEX_LEN_0F38DC_P_2 */
8773   {
8774     { VEX_W_TABLE (VEX_W_0F38DC_P_2) },
8775   },
8776
8777   /* VEX_LEN_0F38DD_P_2 */
8778   {
8779     { VEX_W_TABLE (VEX_W_0F38DD_P_2) },
8780   },
8781
8782   /* VEX_LEN_0F38DE_P_2 */
8783   {
8784     { VEX_W_TABLE (VEX_W_0F38DE_P_2) },
8785   },
8786
8787   /* VEX_LEN_0F38DF_P_2 */
8788   {
8789     { VEX_W_TABLE (VEX_W_0F38DF_P_2) },
8790   },
8791
8792   /* VEX_LEN_0F38F2_P_0 */
8793   {
8794     { "andnS",          { Gdq, VexGdq, Edq } },
8795   },
8796
8797   /* VEX_LEN_0F38F3_R_1_P_0 */
8798   {
8799     { "blsrS",          { VexGdq, Edq } },
8800   },
8801
8802   /* VEX_LEN_0F38F3_R_2_P_0 */
8803   {
8804     { "blsmskS",        { VexGdq, Edq } },
8805   },
8806
8807   /* VEX_LEN_0F38F3_R_3_P_0 */
8808   {
8809     { "blsiS",          { VexGdq, Edq } },
8810   },
8811
8812   /* VEX_LEN_0F38F5_P_0 */
8813   {
8814     { "bzhiS",          { Gdq, Edq, VexGdq } },
8815   },
8816
8817   /* VEX_LEN_0F38F5_P_1 */
8818   {
8819     { "pextS",          { Gdq, VexGdq, Edq } },
8820   },
8821
8822   /* VEX_LEN_0F38F5_P_3 */
8823   {
8824     { "pdepS",          { Gdq, VexGdq, Edq } },
8825   },
8826
8827   /* VEX_LEN_0F38F6_P_3 */
8828   {
8829     { "mulxS",          { Gdq, VexGdq, Edq } },
8830   },
8831
8832   /* VEX_LEN_0F38F7_P_0 */
8833   {
8834     { "bextrS",         { Gdq, Edq, VexGdq } },
8835   },
8836
8837   /* VEX_LEN_0F38F7_P_1 */
8838   {
8839     { "sarxS",          { Gdq, Edq, VexGdq } },
8840   },
8841
8842   /* VEX_LEN_0F38F7_P_2 */
8843   {
8844     { "shlxS",          { Gdq, Edq, VexGdq } },
8845   },
8846
8847   /* VEX_LEN_0F38F7_P_3 */
8848   {
8849     { "shrxS",          { Gdq, Edq, VexGdq } },
8850   },
8851
8852   /* VEX_LEN_0F3A00_P_2 */
8853   {
8854     { Bad_Opcode },
8855     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
8856   },
8857
8858   /* VEX_LEN_0F3A01_P_2 */
8859   {
8860     { Bad_Opcode },
8861     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
8862   },
8863
8864   /* VEX_LEN_0F3A06_P_2 */
8865   {
8866     { Bad_Opcode },
8867     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
8868   },
8869
8870   /* VEX_LEN_0F3A0A_P_2 */
8871   {
8872     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
8873     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
8874   },
8875
8876   /* VEX_LEN_0F3A0B_P_2 */
8877   {
8878     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
8879     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
8880   },
8881
8882   /* VEX_LEN_0F3A14_P_2 */
8883   {
8884     { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
8885   },
8886
8887   /* VEX_LEN_0F3A15_P_2 */
8888   {
8889     { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
8890   },
8891
8892   /* VEX_LEN_0F3A16_P_2  */
8893   {
8894     { "vpextrK",        { Edq, XM, Ib } },
8895   },
8896
8897   /* VEX_LEN_0F3A17_P_2 */
8898   {
8899     { "vextractps",     { Edqd, XM, Ib } },
8900   },
8901
8902   /* VEX_LEN_0F3A18_P_2 */
8903   {
8904     { Bad_Opcode },
8905     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
8906   },
8907
8908   /* VEX_LEN_0F3A19_P_2 */
8909   {
8910     { Bad_Opcode },
8911     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
8912   },
8913
8914   /* VEX_LEN_0F3A20_P_2 */
8915   {
8916     { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
8917   },
8918
8919   /* VEX_LEN_0F3A21_P_2 */
8920   {
8921     { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
8922   },
8923
8924   /* VEX_LEN_0F3A22_P_2 */
8925   {
8926     { "vpinsrK",        { XM, Vex128, Edq, Ib } },
8927   },
8928
8929   /* VEX_LEN_0F3A38_P_2 */
8930   {
8931     { Bad_Opcode },
8932     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
8933   },
8934
8935   /* VEX_LEN_0F3A39_P_2 */
8936   {
8937     { Bad_Opcode },
8938     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
8939   },
8940
8941   /* VEX_LEN_0F3A41_P_2 */
8942   {
8943     { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
8944   },
8945
8946   /* VEX_LEN_0F3A44_P_2 */
8947   {
8948     { VEX_W_TABLE (VEX_W_0F3A44_P_2) },
8949   },
8950
8951   /* VEX_LEN_0F3A46_P_2 */
8952   {
8953     { Bad_Opcode },
8954     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
8955   },
8956
8957   /* VEX_LEN_0F3A60_P_2 */
8958   {
8959     { VEX_W_TABLE (VEX_W_0F3A60_P_2) },
8960   },
8961
8962   /* VEX_LEN_0F3A61_P_2 */
8963   {
8964     { VEX_W_TABLE (VEX_W_0F3A61_P_2) },
8965   },
8966
8967   /* VEX_LEN_0F3A62_P_2 */
8968   {
8969     { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
8970   },
8971
8972   /* VEX_LEN_0F3A63_P_2 */
8973   {
8974     { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
8975   },
8976
8977   /* VEX_LEN_0F3A6A_P_2 */
8978   {
8979     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
8980   },
8981
8982   /* VEX_LEN_0F3A6B_P_2 */
8983   {
8984     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
8985   },
8986
8987   /* VEX_LEN_0F3A6E_P_2 */
8988   {
8989     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
8990   },
8991
8992   /* VEX_LEN_0F3A6F_P_2 */
8993   {
8994     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
8995   },
8996
8997   /* VEX_LEN_0F3A7A_P_2 */
8998   {
8999     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9000   },
9001
9002   /* VEX_LEN_0F3A7B_P_2 */
9003   {
9004     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9005   },
9006
9007   /* VEX_LEN_0F3A7E_P_2 */
9008   {
9009     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9010   },
9011
9012   /* VEX_LEN_0F3A7F_P_2 */
9013   {
9014     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9015   },
9016
9017   /* VEX_LEN_0F3ADF_P_2 */
9018   {
9019     { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
9020   },
9021
9022   /* VEX_LEN_0F3AF0_P_3 */
9023   {
9024     { "rorxS",          { Gdq, Edq, Ib } },
9025   },
9026
9027   /* VEX_LEN_0FXOP_08_CC */
9028   {
9029      { "vpcomb",        { XM, Vex128, EXx, Ib } },
9030   },
9031
9032   /* VEX_LEN_0FXOP_08_CD */
9033   {
9034      { "vpcomw",        { XM, Vex128, EXx, Ib } },
9035   },
9036
9037   /* VEX_LEN_0FXOP_08_CE */
9038   {
9039      { "vpcomd",        { XM, Vex128, EXx, Ib } },
9040   },
9041
9042   /* VEX_LEN_0FXOP_08_CF */
9043   {
9044      { "vpcomq",        { XM, Vex128, EXx, Ib } },
9045   },
9046
9047   /* VEX_LEN_0FXOP_08_EC */
9048   {
9049      { "vpcomub",       { XM, Vex128, EXx, Ib } },
9050   },
9051
9052   /* VEX_LEN_0FXOP_08_ED */
9053   {
9054      { "vpcomuw",       { XM, Vex128, EXx, Ib } },
9055   },
9056
9057   /* VEX_LEN_0FXOP_08_EE */
9058   {
9059      { "vpcomud",       { XM, Vex128, EXx, Ib } },
9060   },
9061
9062   /* VEX_LEN_0FXOP_08_EF */
9063   {
9064      { "vpcomuq",       { XM, Vex128, EXx, Ib } },
9065   },
9066
9067   /* VEX_LEN_0FXOP_09_80 */
9068   {
9069     { "vfrczps",        { XM, EXxmm } },
9070     { "vfrczps",        { XM, EXymmq } },
9071   },
9072
9073   /* VEX_LEN_0FXOP_09_81 */
9074   {
9075     { "vfrczpd",        { XM, EXxmm } },
9076     { "vfrczpd",        { XM, EXymmq } },
9077   },
9078 };
9079
9080 static const struct dis386 vex_w_table[][2] = {
9081   {
9082     /* VEX_W_0F10_P_0 */
9083     { "vmovups",        { XM, EXx } },
9084   },
9085   {
9086     /* VEX_W_0F10_P_1 */
9087     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar } },
9088   },
9089   {
9090     /* VEX_W_0F10_P_2 */
9091     { "vmovupd",        { XM, EXx } },
9092   },
9093   {
9094     /* VEX_W_0F10_P_3 */
9095     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar } },
9096   },
9097   {
9098     /* VEX_W_0F11_P_0 */
9099     { "vmovups",        { EXxS, XM } },
9100   },
9101   {
9102     /* VEX_W_0F11_P_1 */
9103     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar } },
9104   },
9105   {
9106     /* VEX_W_0F11_P_2 */
9107     { "vmovupd",        { EXxS, XM } },
9108   },
9109   {
9110     /* VEX_W_0F11_P_3 */
9111     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar } },
9112   },
9113   {
9114     /* VEX_W_0F12_P_0_M_0 */
9115     { "vmovlps",        { XM, Vex128, EXq } },
9116   },
9117   {
9118     /* VEX_W_0F12_P_0_M_1 */
9119     { "vmovhlps",       { XM, Vex128, EXq } },
9120   },
9121   {
9122     /* VEX_W_0F12_P_1 */
9123     { "vmovsldup",      { XM, EXx } },
9124   },
9125   {
9126     /* VEX_W_0F12_P_2 */
9127     { "vmovlpd",        { XM, Vex128, EXq } },
9128   },
9129   {
9130     /* VEX_W_0F12_P_3 */
9131     { "vmovddup",       { XM, EXymmq } },
9132   },
9133   {
9134     /* VEX_W_0F13_M_0 */
9135     { "vmovlpX",        { EXq, XM } },
9136   },
9137   {
9138     /* VEX_W_0F14 */
9139     { "vunpcklpX",      { XM, Vex, EXx } },
9140   },
9141   {
9142     /* VEX_W_0F15 */
9143     { "vunpckhpX",      { XM, Vex, EXx } },
9144   },
9145   {
9146     /* VEX_W_0F16_P_0_M_0 */
9147     { "vmovhps",        { XM, Vex128, EXq } },
9148   },
9149   {
9150     /* VEX_W_0F16_P_0_M_1 */
9151     { "vmovlhps",       { XM, Vex128, EXq } },
9152   },
9153   {
9154     /* VEX_W_0F16_P_1 */
9155     { "vmovshdup",      { XM, EXx } },
9156   },
9157   {
9158     /* VEX_W_0F16_P_2 */
9159     { "vmovhpd",        { XM, Vex128, EXq } },
9160   },
9161   {
9162     /* VEX_W_0F17_M_0 */
9163     { "vmovhpX",        { EXq, XM } },
9164   },
9165   {
9166     /* VEX_W_0F28 */
9167     { "vmovapX",        { XM, EXx } },
9168   },
9169   {
9170     /* VEX_W_0F29 */
9171     { "vmovapX",        { EXxS, XM } },
9172   },
9173   {
9174     /* VEX_W_0F2B_M_0 */
9175     { "vmovntpX",       { Mx, XM } },
9176   },
9177   {
9178     /* VEX_W_0F2E_P_0 */
9179     { "vucomiss",       { XMScalar, EXdScalar } },
9180   },
9181   {
9182     /* VEX_W_0F2E_P_2 */
9183     { "vucomisd",       { XMScalar, EXqScalar } },
9184   },
9185   {
9186     /* VEX_W_0F2F_P_0 */
9187     { "vcomiss",        { XMScalar, EXdScalar } },
9188   },
9189   {
9190     /* VEX_W_0F2F_P_2 */
9191     { "vcomisd",        { XMScalar, EXqScalar } },
9192   },
9193   {
9194     /* VEX_W_0F50_M_0 */
9195     { "vmovmskpX",      { Gdq, XS } },
9196   },
9197   {
9198     /* VEX_W_0F51_P_0 */
9199     { "vsqrtps",        { XM, EXx } },
9200   },
9201   {
9202     /* VEX_W_0F51_P_1 */
9203     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar } },
9204   },
9205   {
9206     /* VEX_W_0F51_P_2  */
9207     { "vsqrtpd",        { XM, EXx } },
9208   },
9209   {
9210     /* VEX_W_0F51_P_3 */
9211     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar } },
9212   },
9213   {
9214     /* VEX_W_0F52_P_0 */
9215     { "vrsqrtps",       { XM, EXx } },
9216   },
9217   {
9218     /* VEX_W_0F52_P_1 */
9219     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar } },
9220   },
9221   {
9222     /* VEX_W_0F53_P_0  */
9223     { "vrcpps",         { XM, EXx } },
9224   },
9225   {
9226     /* VEX_W_0F53_P_1  */
9227     { "vrcpss",         { XMScalar, VexScalar, EXdScalar } },
9228   },
9229   {
9230     /* VEX_W_0F58_P_0  */
9231     { "vaddps",         { XM, Vex, EXx } },
9232   },
9233   {
9234     /* VEX_W_0F58_P_1  */
9235     { "vaddss",         { XMScalar, VexScalar, EXdScalar } },
9236   },
9237   {
9238     /* VEX_W_0F58_P_2  */
9239     { "vaddpd",         { XM, Vex, EXx } },
9240   },
9241   {
9242     /* VEX_W_0F58_P_3  */
9243     { "vaddsd",         { XMScalar, VexScalar, EXqScalar } },
9244   },
9245   {
9246     /* VEX_W_0F59_P_0  */
9247     { "vmulps",         { XM, Vex, EXx } },
9248   },
9249   {
9250     /* VEX_W_0F59_P_1  */
9251     { "vmulss",         { XMScalar, VexScalar, EXdScalar } },
9252   },
9253   {
9254     /* VEX_W_0F59_P_2  */
9255     { "vmulpd",         { XM, Vex, EXx } },
9256   },
9257   {
9258     /* VEX_W_0F59_P_3  */
9259     { "vmulsd",         { XMScalar, VexScalar, EXqScalar } },
9260   },
9261   {
9262     /* VEX_W_0F5A_P_0  */
9263     { "vcvtps2pd",      { XM, EXxmmq } },
9264   },
9265   {
9266     /* VEX_W_0F5A_P_1  */
9267     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar } },
9268   },
9269   {
9270     /* VEX_W_0F5A_P_3  */
9271     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar } },
9272   },
9273   {
9274     /* VEX_W_0F5B_P_0  */
9275     { "vcvtdq2ps",      { XM, EXx } },
9276   },
9277   {
9278     /* VEX_W_0F5B_P_1  */
9279     { "vcvttps2dq",     { XM, EXx } },
9280   },
9281   {
9282     /* VEX_W_0F5B_P_2  */
9283     { "vcvtps2dq",      { XM, EXx } },
9284   },
9285   {
9286     /* VEX_W_0F5C_P_0  */
9287     { "vsubps",         { XM, Vex, EXx } },
9288   },
9289   {
9290     /* VEX_W_0F5C_P_1  */
9291     { "vsubss",         { XMScalar, VexScalar, EXdScalar } },
9292   },
9293   {
9294     /* VEX_W_0F5C_P_2  */
9295     { "vsubpd",         { XM, Vex, EXx } },
9296   },
9297   {
9298     /* VEX_W_0F5C_P_3  */
9299     { "vsubsd",         { XMScalar, VexScalar, EXqScalar } },
9300   },
9301   {
9302     /* VEX_W_0F5D_P_0  */
9303     { "vminps",         { XM, Vex, EXx } },
9304   },
9305   {
9306     /* VEX_W_0F5D_P_1  */
9307     { "vminss",         { XMScalar, VexScalar, EXdScalar } },
9308   },
9309   {
9310     /* VEX_W_0F5D_P_2  */
9311     { "vminpd",         { XM, Vex, EXx } },
9312   },
9313   {
9314     /* VEX_W_0F5D_P_3  */
9315     { "vminsd",         { XMScalar, VexScalar, EXqScalar } },
9316   },
9317   {
9318     /* VEX_W_0F5E_P_0  */
9319     { "vdivps",         { XM, Vex, EXx } },
9320   },
9321   {
9322     /* VEX_W_0F5E_P_1  */
9323     { "vdivss",         { XMScalar, VexScalar, EXdScalar } },
9324   },
9325   {
9326     /* VEX_W_0F5E_P_2  */
9327     { "vdivpd",         { XM, Vex, EXx } },
9328   },
9329   {
9330     /* VEX_W_0F5E_P_3  */
9331     { "vdivsd",         { XMScalar, VexScalar, EXqScalar } },
9332   },
9333   {
9334     /* VEX_W_0F5F_P_0  */
9335     { "vmaxps",         { XM, Vex, EXx } },
9336   },
9337   {
9338     /* VEX_W_0F5F_P_1  */
9339     { "vmaxss",         { XMScalar, VexScalar, EXdScalar } },
9340   },
9341   {
9342     /* VEX_W_0F5F_P_2  */
9343     { "vmaxpd",         { XM, Vex, EXx } },
9344   },
9345   {
9346     /* VEX_W_0F5F_P_3  */
9347     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar } },
9348   },
9349   {
9350     /* VEX_W_0F60_P_2  */
9351     { "vpunpcklbw",     { XM, Vex, EXx } },
9352   },
9353   {
9354     /* VEX_W_0F61_P_2  */
9355     { "vpunpcklwd",     { XM, Vex, EXx } },
9356   },
9357   {
9358     /* VEX_W_0F62_P_2  */
9359     { "vpunpckldq",     { XM, Vex, EXx } },
9360   },
9361   {
9362     /* VEX_W_0F63_P_2  */
9363     { "vpacksswb",      { XM, Vex, EXx } },
9364   },
9365   {
9366     /* VEX_W_0F64_P_2  */
9367     { "vpcmpgtb",       { XM, Vex, EXx } },
9368   },
9369   {
9370     /* VEX_W_0F65_P_2  */
9371     { "vpcmpgtw",       { XM, Vex, EXx } },
9372   },
9373   {
9374     /* VEX_W_0F66_P_2  */
9375     { "vpcmpgtd",       { XM, Vex, EXx } },
9376   },
9377   {
9378     /* VEX_W_0F67_P_2  */
9379     { "vpackuswb",      { XM, Vex, EXx } },
9380   },
9381   {
9382     /* VEX_W_0F68_P_2  */
9383     { "vpunpckhbw",     { XM, Vex, EXx } },
9384   },
9385   {
9386     /* VEX_W_0F69_P_2  */
9387     { "vpunpckhwd",     { XM, Vex, EXx } },
9388   },
9389   {
9390     /* VEX_W_0F6A_P_2  */
9391     { "vpunpckhdq",     { XM, Vex, EXx } },
9392   },
9393   {
9394     /* VEX_W_0F6B_P_2  */
9395     { "vpackssdw",      { XM, Vex, EXx } },
9396   },
9397   {
9398     /* VEX_W_0F6C_P_2  */
9399     { "vpunpcklqdq",    { XM, Vex, EXx } },
9400   },
9401   {
9402     /* VEX_W_0F6D_P_2  */
9403     { "vpunpckhqdq",    { XM, Vex, EXx } },
9404   },
9405   {
9406     /* VEX_W_0F6F_P_1  */
9407     { "vmovdqu",        { XM, EXx } },
9408   },
9409   {
9410     /* VEX_W_0F6F_P_2  */
9411     { "vmovdqa",        { XM, EXx } },
9412   },
9413   {
9414     /* VEX_W_0F70_P_1 */
9415     { "vpshufhw",       { XM, EXx, Ib } },
9416   },
9417   {
9418     /* VEX_W_0F70_P_2 */
9419     { "vpshufd",        { XM, EXx, Ib } },
9420   },
9421   {
9422     /* VEX_W_0F70_P_3 */
9423     { "vpshuflw",       { XM, EXx, Ib } },
9424   },
9425   {
9426     /* VEX_W_0F71_R_2_P_2  */
9427     { "vpsrlw",         { Vex, XS, Ib } },
9428   },
9429   {
9430     /* VEX_W_0F71_R_4_P_2  */
9431     { "vpsraw",         { Vex, XS, Ib } },
9432   },
9433   {
9434     /* VEX_W_0F71_R_6_P_2  */
9435     { "vpsllw",         { Vex, XS, Ib } },
9436   },
9437   {
9438     /* VEX_W_0F72_R_2_P_2  */
9439     { "vpsrld",         { Vex, XS, Ib } },
9440   },
9441   {
9442     /* VEX_W_0F72_R_4_P_2  */
9443     { "vpsrad",         { Vex, XS, Ib } },
9444   },
9445   {
9446     /* VEX_W_0F72_R_6_P_2  */
9447     { "vpslld",         { Vex, XS, Ib } },
9448   },
9449   {
9450     /* VEX_W_0F73_R_2_P_2  */
9451     { "vpsrlq",         { Vex, XS, Ib } },
9452   },
9453   {
9454     /* VEX_W_0F73_R_3_P_2  */
9455     { "vpsrldq",        { Vex, XS, Ib } },
9456   },
9457   {
9458     /* VEX_W_0F73_R_6_P_2  */
9459     { "vpsllq",         { Vex, XS, Ib } },
9460   },
9461   {
9462     /* VEX_W_0F73_R_7_P_2  */
9463     { "vpslldq",        { Vex, XS, Ib } },
9464   },
9465   {
9466     /* VEX_W_0F74_P_2 */
9467     { "vpcmpeqb",       { XM, Vex, EXx } },
9468   },
9469   {
9470     /* VEX_W_0F75_P_2 */
9471     { "vpcmpeqw",       { XM, Vex, EXx } },
9472   },
9473   {
9474     /* VEX_W_0F76_P_2 */
9475     { "vpcmpeqd",       { XM, Vex, EXx } },
9476   },
9477   {
9478     /* VEX_W_0F77_P_0 */
9479     { "",               { VZERO } },
9480   },
9481   {
9482     /* VEX_W_0F7C_P_2 */
9483     { "vhaddpd",        { XM, Vex, EXx } },
9484   },
9485   {
9486     /* VEX_W_0F7C_P_3 */
9487     { "vhaddps",        { XM, Vex, EXx } },
9488   },
9489   {
9490     /* VEX_W_0F7D_P_2 */
9491     { "vhsubpd",        { XM, Vex, EXx } },
9492   },
9493   {
9494     /* VEX_W_0F7D_P_3 */
9495     { "vhsubps",        { XM, Vex, EXx } },
9496   },
9497   {
9498     /* VEX_W_0F7E_P_1 */
9499     { "vmovq",          { XMScalar, EXqScalar } },
9500   },
9501   {
9502     /* VEX_W_0F7F_P_1 */
9503     { "vmovdqu",        { EXxS, XM } },
9504   },
9505   {
9506     /* VEX_W_0F7F_P_2 */
9507     { "vmovdqa",        { EXxS, XM } },
9508   },
9509   {
9510     /* VEX_W_0FAE_R_2_M_0 */
9511     { "vldmxcsr",       { Md } },
9512   },
9513   {
9514     /* VEX_W_0FAE_R_3_M_0 */
9515     { "vstmxcsr",       { Md } },
9516   },
9517   {
9518     /* VEX_W_0FC2_P_0 */
9519     { "vcmpps",         { XM, Vex, EXx, VCMP } },
9520   },
9521   {
9522     /* VEX_W_0FC2_P_1 */
9523     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP } },
9524   },
9525   {
9526     /* VEX_W_0FC2_P_2 */
9527     { "vcmppd",         { XM, Vex, EXx, VCMP } },
9528   },
9529   {
9530     /* VEX_W_0FC2_P_3 */
9531     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP } },
9532   },
9533   {
9534     /* VEX_W_0FC4_P_2 */
9535     { "vpinsrw",        { XM, Vex128, Edqw, Ib } },
9536   },
9537   {
9538     /* VEX_W_0FC5_P_2 */
9539     { "vpextrw",        { Gdq, XS, Ib } },
9540   },
9541   {
9542     /* VEX_W_0FD0_P_2 */
9543     { "vaddsubpd",      { XM, Vex, EXx } },
9544   },
9545   {
9546     /* VEX_W_0FD0_P_3 */
9547     { "vaddsubps",      { XM, Vex, EXx } },
9548   },
9549   {
9550     /* VEX_W_0FD1_P_2 */
9551     { "vpsrlw",         { XM, Vex, EXxmm } },
9552   },
9553   {
9554     /* VEX_W_0FD2_P_2 */
9555     { "vpsrld",         { XM, Vex, EXxmm } },
9556   },
9557   {
9558     /* VEX_W_0FD3_P_2 */
9559     { "vpsrlq",         { XM, Vex, EXxmm } },
9560   },
9561   {
9562     /* VEX_W_0FD4_P_2 */
9563     { "vpaddq",         { XM, Vex, EXx } },
9564   },
9565   {
9566     /* VEX_W_0FD5_P_2 */
9567     { "vpmullw",        { XM, Vex, EXx } },
9568   },
9569   {
9570     /* VEX_W_0FD6_P_2 */
9571     { "vmovq",          { EXqScalarS, XMScalar } },
9572   },
9573   {
9574     /* VEX_W_0FD7_P_2_M_1 */
9575     { "vpmovmskb",      { Gdq, XS } },
9576   },
9577   {
9578     /* VEX_W_0FD8_P_2 */
9579     { "vpsubusb",       { XM, Vex, EXx } },
9580   },
9581   {
9582     /* VEX_W_0FD9_P_2 */
9583     { "vpsubusw",       { XM, Vex, EXx } },
9584   },
9585   {
9586     /* VEX_W_0FDA_P_2 */
9587     { "vpminub",        { XM, Vex, EXx } },
9588   },
9589   {
9590     /* VEX_W_0FDB_P_2 */
9591     { "vpand",          { XM, Vex, EXx } },
9592   },
9593   {
9594     /* VEX_W_0FDC_P_2 */
9595     { "vpaddusb",       { XM, Vex, EXx } },
9596   },
9597   {
9598     /* VEX_W_0FDD_P_2 */
9599     { "vpaddusw",       { XM, Vex, EXx } },
9600   },
9601   {
9602     /* VEX_W_0FDE_P_2 */
9603     { "vpmaxub",        { XM, Vex, EXx } },
9604   },
9605   {
9606     /* VEX_W_0FDF_P_2 */
9607     { "vpandn",         { XM, Vex, EXx } },
9608   },
9609   {
9610     /* VEX_W_0FE0_P_2  */
9611     { "vpavgb",         { XM, Vex, EXx } },
9612   },
9613   {
9614     /* VEX_W_0FE1_P_2  */
9615     { "vpsraw",         { XM, Vex, EXxmm } },
9616   },
9617   {
9618     /* VEX_W_0FE2_P_2  */
9619     { "vpsrad",         { XM, Vex, EXxmm } },
9620   },
9621   {
9622     /* VEX_W_0FE3_P_2  */
9623     { "vpavgw",         { XM, Vex, EXx } },
9624   },
9625   {
9626     /* VEX_W_0FE4_P_2  */
9627     { "vpmulhuw",       { XM, Vex, EXx } },
9628   },
9629   {
9630     /* VEX_W_0FE5_P_2  */
9631     { "vpmulhw",        { XM, Vex, EXx } },
9632   },
9633   {
9634     /* VEX_W_0FE6_P_1  */
9635     { "vcvtdq2pd",      { XM, EXxmmq } },
9636   },
9637   {
9638     /* VEX_W_0FE6_P_2  */
9639     { "vcvttpd2dq%XY",  { XMM, EXx } },
9640   },
9641   {
9642     /* VEX_W_0FE6_P_3  */
9643     { "vcvtpd2dq%XY",   { XMM, EXx } },
9644   },
9645   {
9646     /* VEX_W_0FE7_P_2_M_0 */
9647     { "vmovntdq",       { Mx, XM } },
9648   },
9649   {
9650     /* VEX_W_0FE8_P_2  */
9651     { "vpsubsb",        { XM, Vex, EXx } },
9652   },
9653   {
9654     /* VEX_W_0FE9_P_2  */
9655     { "vpsubsw",        { XM, Vex, EXx } },
9656   },
9657   {
9658     /* VEX_W_0FEA_P_2  */
9659     { "vpminsw",        { XM, Vex, EXx } },
9660   },
9661   {
9662     /* VEX_W_0FEB_P_2  */
9663     { "vpor",           { XM, Vex, EXx } },
9664   },
9665   {
9666     /* VEX_W_0FEC_P_2  */
9667     { "vpaddsb",        { XM, Vex, EXx } },
9668   },
9669   {
9670     /* VEX_W_0FED_P_2  */
9671     { "vpaddsw",        { XM, Vex, EXx } },
9672   },
9673   {
9674     /* VEX_W_0FEE_P_2  */
9675     { "vpmaxsw",        { XM, Vex, EXx } },
9676   },
9677   {
9678     /* VEX_W_0FEF_P_2  */
9679     { "vpxor",          { XM, Vex, EXx } },
9680   },
9681   {
9682     /* VEX_W_0FF0_P_3_M_0 */
9683     { "vlddqu",         { XM, M } },
9684   },
9685   {
9686     /* VEX_W_0FF1_P_2 */
9687     { "vpsllw",         { XM, Vex, EXxmm } },
9688   },
9689   {
9690     /* VEX_W_0FF2_P_2 */
9691     { "vpslld",         { XM, Vex, EXxmm } },
9692   },
9693   {
9694     /* VEX_W_0FF3_P_2 */
9695     { "vpsllq",         { XM, Vex, EXxmm } },
9696   },
9697   {
9698     /* VEX_W_0FF4_P_2 */
9699     { "vpmuludq",       { XM, Vex, EXx } },
9700   },
9701   {
9702     /* VEX_W_0FF5_P_2 */
9703     { "vpmaddwd",       { XM, Vex, EXx } },
9704   },
9705   {
9706     /* VEX_W_0FF6_P_2 */
9707     { "vpsadbw",        { XM, Vex, EXx } },
9708   },
9709   {
9710     /* VEX_W_0FF7_P_2 */
9711     { "vmaskmovdqu",    { XM, XS } },
9712   },
9713   {
9714     /* VEX_W_0FF8_P_2 */
9715     { "vpsubb",         { XM, Vex, EXx } },
9716   },
9717   {
9718     /* VEX_W_0FF9_P_2 */
9719     { "vpsubw",         { XM, Vex, EXx } },
9720   },
9721   {
9722     /* VEX_W_0FFA_P_2 */
9723     { "vpsubd",         { XM, Vex, EXx } },
9724   },
9725   {
9726     /* VEX_W_0FFB_P_2 */
9727     { "vpsubq",         { XM, Vex, EXx } },
9728   },
9729   {
9730     /* VEX_W_0FFC_P_2 */
9731     { "vpaddb",         { XM, Vex, EXx } },
9732   },
9733   {
9734     /* VEX_W_0FFD_P_2 */
9735     { "vpaddw",         { XM, Vex, EXx } },
9736   },
9737   {
9738     /* VEX_W_0FFE_P_2 */
9739     { "vpaddd",         { XM, Vex, EXx } },
9740   },
9741   {
9742     /* VEX_W_0F3800_P_2  */
9743     { "vpshufb",        { XM, Vex, EXx } },
9744   },
9745   {
9746     /* VEX_W_0F3801_P_2  */
9747     { "vphaddw",        { XM, Vex, EXx } },
9748   },
9749   {
9750     /* VEX_W_0F3802_P_2  */
9751     { "vphaddd",        { XM, Vex, EXx } },
9752   },
9753   {
9754     /* VEX_W_0F3803_P_2  */
9755     { "vphaddsw",       { XM, Vex, EXx } },
9756   },
9757   {
9758     /* VEX_W_0F3804_P_2  */
9759     { "vpmaddubsw",     { XM, Vex, EXx } },
9760   },
9761   {
9762     /* VEX_W_0F3805_P_2  */
9763     { "vphsubw",        { XM, Vex, EXx } },
9764   },
9765   {
9766     /* VEX_W_0F3806_P_2  */
9767     { "vphsubd",        { XM, Vex, EXx } },
9768   },
9769   {
9770     /* VEX_W_0F3807_P_2  */
9771     { "vphsubsw",       { XM, Vex, EXx } },
9772   },
9773   {
9774     /* VEX_W_0F3808_P_2  */
9775     { "vpsignb",        { XM, Vex, EXx } },
9776   },
9777   {
9778     /* VEX_W_0F3809_P_2  */
9779     { "vpsignw",        { XM, Vex, EXx } },
9780   },
9781   {
9782     /* VEX_W_0F380A_P_2  */
9783     { "vpsignd",        { XM, Vex, EXx } },
9784   },
9785   {
9786     /* VEX_W_0F380B_P_2  */
9787     { "vpmulhrsw",      { XM, Vex, EXx } },
9788   },
9789   {
9790     /* VEX_W_0F380C_P_2  */
9791     { "vpermilps",      { XM, Vex, EXx } },
9792   },
9793   {
9794     /* VEX_W_0F380D_P_2  */
9795     { "vpermilpd",      { XM, Vex, EXx } },
9796   },
9797   {
9798     /* VEX_W_0F380E_P_2  */
9799     { "vtestps",        { XM, EXx } },
9800   },
9801   {
9802     /* VEX_W_0F380F_P_2  */
9803     { "vtestpd",        { XM, EXx } },
9804   },
9805   {
9806     /* VEX_W_0F3816_P_2  */
9807     { "vpermps",        { XM, Vex, EXx } },
9808   },
9809   {
9810     /* VEX_W_0F3817_P_2 */
9811     { "vptest",         { XM, EXx } },
9812   },
9813   {
9814     /* VEX_W_0F3818_P_2 */
9815     { "vbroadcastss",   { XM, EXxmm_md } },
9816   },
9817   {
9818     /* VEX_W_0F3819_P_2 */
9819     { "vbroadcastsd",   { XM, EXxmm_mq } },
9820   },
9821   {
9822     /* VEX_W_0F381A_P_2_M_0 */
9823     { "vbroadcastf128", { XM, Mxmm } },
9824   },
9825   {
9826     /* VEX_W_0F381C_P_2 */
9827     { "vpabsb",         { XM, EXx } },
9828   },
9829   {
9830     /* VEX_W_0F381D_P_2 */
9831     { "vpabsw",         { XM, EXx } },
9832   },
9833   {
9834     /* VEX_W_0F381E_P_2 */
9835     { "vpabsd",         { XM, EXx } },
9836   },
9837   {
9838     /* VEX_W_0F3820_P_2 */
9839     { "vpmovsxbw",      { XM, EXxmmq } },
9840   },
9841   {
9842     /* VEX_W_0F3821_P_2 */
9843     { "vpmovsxbd",      { XM, EXxmmqd } },
9844   },
9845   {
9846     /* VEX_W_0F3822_P_2 */
9847     { "vpmovsxbq",      { XM, EXxmmdw } },
9848   },
9849   {
9850     /* VEX_W_0F3823_P_2 */
9851     { "vpmovsxwd",      { XM, EXxmmq } },
9852   },
9853   {
9854     /* VEX_W_0F3824_P_2 */
9855     { "vpmovsxwq",      { XM, EXxmmqd } },
9856   },
9857   {
9858     /* VEX_W_0F3825_P_2 */
9859     { "vpmovsxdq",      { XM, EXxmmq } },
9860   },
9861   {
9862     /* VEX_W_0F3828_P_2 */
9863     { "vpmuldq",        { XM, Vex, EXx } },
9864   },
9865   {
9866     /* VEX_W_0F3829_P_2 */
9867     { "vpcmpeqq",       { XM, Vex, EXx } },
9868   },
9869   {
9870     /* VEX_W_0F382A_P_2_M_0 */
9871     { "vmovntdqa",      { XM, Mx } },
9872   },
9873   {
9874     /* VEX_W_0F382B_P_2 */
9875     { "vpackusdw",      { XM, Vex, EXx } },
9876   },
9877   {
9878     /* VEX_W_0F382C_P_2_M_0 */
9879     { "vmaskmovps",     { XM, Vex, Mx } },
9880   },
9881   {
9882     /* VEX_W_0F382D_P_2_M_0 */
9883     { "vmaskmovpd",     { XM, Vex, Mx } },
9884   },
9885   {
9886     /* VEX_W_0F382E_P_2_M_0 */
9887     { "vmaskmovps",     { Mx, Vex, XM } },
9888   },
9889   {
9890     /* VEX_W_0F382F_P_2_M_0 */
9891     { "vmaskmovpd",     { Mx, Vex, XM } },
9892   },
9893   {
9894     /* VEX_W_0F3830_P_2 */
9895     { "vpmovzxbw",      { XM, EXxmmq } },
9896   },
9897   {
9898     /* VEX_W_0F3831_P_2 */
9899     { "vpmovzxbd",      { XM, EXxmmqd } },
9900   },
9901   {
9902     /* VEX_W_0F3832_P_2 */
9903     { "vpmovzxbq",      { XM, EXxmmdw } },
9904   },
9905   {
9906     /* VEX_W_0F3833_P_2 */
9907     { "vpmovzxwd",      { XM, EXxmmq } },
9908   },
9909   {
9910     /* VEX_W_0F3834_P_2 */
9911     { "vpmovzxwq",      { XM, EXxmmqd } },
9912   },
9913   {
9914     /* VEX_W_0F3835_P_2 */
9915     { "vpmovzxdq",      { XM, EXxmmq } },
9916   },
9917   {
9918     /* VEX_W_0F3836_P_2  */
9919     { "vpermd",         { XM, Vex, EXx } },
9920   },
9921   {
9922     /* VEX_W_0F3837_P_2 */
9923     { "vpcmpgtq",       { XM, Vex, EXx } },
9924   },
9925   {
9926     /* VEX_W_0F3838_P_2 */
9927     { "vpminsb",        { XM, Vex, EXx } },
9928   },
9929   {
9930     /* VEX_W_0F3839_P_2 */
9931     { "vpminsd",        { XM, Vex, EXx } },
9932   },
9933   {
9934     /* VEX_W_0F383A_P_2 */
9935     { "vpminuw",        { XM, Vex, EXx } },
9936   },
9937   {
9938     /* VEX_W_0F383B_P_2 */
9939     { "vpminud",        { XM, Vex, EXx } },
9940   },
9941   {
9942     /* VEX_W_0F383C_P_2 */
9943     { "vpmaxsb",        { XM, Vex, EXx } },
9944   },
9945   {
9946     /* VEX_W_0F383D_P_2 */
9947     { "vpmaxsd",        { XM, Vex, EXx } },
9948   },
9949   {
9950     /* VEX_W_0F383E_P_2 */
9951     { "vpmaxuw",        { XM, Vex, EXx } },
9952   },
9953   {
9954     /* VEX_W_0F383F_P_2 */
9955     { "vpmaxud",        { XM, Vex, EXx } },
9956   },
9957   {
9958     /* VEX_W_0F3840_P_2 */
9959     { "vpmulld",        { XM, Vex, EXx } },
9960   },
9961   {
9962     /* VEX_W_0F3841_P_2 */
9963     { "vphminposuw",    { XM, EXx } },
9964   },
9965   {
9966     /* VEX_W_0F3846_P_2 */
9967     { "vpsravd",        { XM, Vex, EXx } },
9968   },
9969   {
9970     /* VEX_W_0F3858_P_2 */
9971     { "vpbroadcastd", { XM, EXxmm_md } },
9972   },
9973   {
9974     /* VEX_W_0F3859_P_2 */
9975     { "vpbroadcastq",   { XM, EXxmm_mq } },
9976   },
9977   {
9978     /* VEX_W_0F385A_P_2_M_0 */
9979     { "vbroadcasti128", { XM, Mxmm } },
9980   },
9981   {
9982     /* VEX_W_0F3878_P_2 */
9983     { "vpbroadcastb",   { XM, EXxmm_mb } },
9984   },
9985   {
9986     /* VEX_W_0F3879_P_2 */
9987     { "vpbroadcastw",   { XM, EXxmm_mw } },
9988   },
9989   {
9990     /* VEX_W_0F38DB_P_2 */
9991     { "vaesimc",        { XM, EXx } },
9992   },
9993   {
9994     /* VEX_W_0F38DC_P_2 */
9995     { "vaesenc",        { XM, Vex128, EXx } },
9996   },
9997   {
9998     /* VEX_W_0F38DD_P_2 */
9999     { "vaesenclast",    { XM, Vex128, EXx } },
10000   },
10001   {
10002     /* VEX_W_0F38DE_P_2 */
10003     { "vaesdec",        { XM, Vex128, EXx } },
10004   },
10005   {
10006     /* VEX_W_0F38DF_P_2 */
10007     { "vaesdeclast",    { XM, Vex128, EXx } },
10008   },
10009   {
10010     /* VEX_W_0F3A00_P_2 */
10011     { Bad_Opcode },
10012     { "vpermq",         { XM, EXx, Ib } },
10013   },
10014   {
10015     /* VEX_W_0F3A01_P_2 */
10016     { Bad_Opcode },
10017     { "vpermpd",        { XM, EXx, Ib } },
10018   },
10019   {
10020     /* VEX_W_0F3A02_P_2 */
10021     { "vpblendd",       { XM, Vex, EXx, Ib } },
10022   },
10023   {
10024     /* VEX_W_0F3A04_P_2 */
10025     { "vpermilps",      { XM, EXx, Ib } },
10026   },
10027   {
10028     /* VEX_W_0F3A05_P_2 */
10029     { "vpermilpd",      { XM, EXx, Ib } },
10030   },
10031   {
10032     /* VEX_W_0F3A06_P_2 */
10033     { "vperm2f128",     { XM, Vex256, EXx, Ib } },
10034   },
10035   {
10036     /* VEX_W_0F3A08_P_2 */
10037     { "vroundps",       { XM, EXx, Ib } },
10038   },
10039   {
10040     /* VEX_W_0F3A09_P_2 */
10041     { "vroundpd",       { XM, EXx, Ib } },
10042   },
10043   {
10044     /* VEX_W_0F3A0A_P_2 */
10045     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib } },
10046   },
10047   {
10048     /* VEX_W_0F3A0B_P_2 */
10049     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib } },
10050   },
10051   {
10052     /* VEX_W_0F3A0C_P_2 */
10053     { "vblendps",       { XM, Vex, EXx, Ib } },
10054   },
10055   {
10056     /* VEX_W_0F3A0D_P_2 */
10057     { "vblendpd",       { XM, Vex, EXx, Ib } },
10058   },
10059   {
10060     /* VEX_W_0F3A0E_P_2 */
10061     { "vpblendw",       { XM, Vex, EXx, Ib } },
10062   },
10063   {
10064     /* VEX_W_0F3A0F_P_2 */
10065     { "vpalignr",       { XM, Vex, EXx, Ib } },
10066   },
10067   {
10068     /* VEX_W_0F3A14_P_2 */
10069     { "vpextrb",        { Edqb, XM, Ib } },
10070   },
10071   {
10072     /* VEX_W_0F3A15_P_2 */
10073     { "vpextrw",        { Edqw, XM, Ib } },
10074   },
10075   {
10076     /* VEX_W_0F3A18_P_2 */
10077     { "vinsertf128",    { XM, Vex256, EXxmm, Ib } },
10078   },
10079   {
10080     /* VEX_W_0F3A19_P_2 */
10081     { "vextractf128",   { EXxmm, XM, Ib } },
10082   },
10083   {
10084     /* VEX_W_0F3A20_P_2 */
10085     { "vpinsrb",        { XM, Vex128, Edqb, Ib } },
10086   },
10087   {
10088     /* VEX_W_0F3A21_P_2 */
10089     { "vinsertps",      { XM, Vex128, EXd, Ib } },
10090   },
10091   {
10092     /* VEX_W_0F3A38_P_2 */
10093     { "vinserti128",    { XM, Vex256, EXxmm, Ib } },
10094   },
10095   {
10096     /* VEX_W_0F3A39_P_2 */
10097     { "vextracti128",   { EXxmm, XM, Ib } },
10098   },
10099   {
10100     /* VEX_W_0F3A40_P_2 */
10101     { "vdpps",          { XM, Vex, EXx, Ib } },
10102   },
10103   {
10104     /* VEX_W_0F3A41_P_2 */
10105     { "vdppd",          { XM, Vex128, EXx, Ib } },
10106   },
10107   {
10108     /* VEX_W_0F3A42_P_2 */
10109     { "vmpsadbw",       { XM, Vex, EXx, Ib } },
10110   },
10111   {
10112     /* VEX_W_0F3A44_P_2 */
10113     { "vpclmulqdq",     { XM, Vex128, EXx, PCLMUL } },
10114   },
10115   {
10116     /* VEX_W_0F3A46_P_2 */
10117     { "vperm2i128",     { XM, Vex256, EXx, Ib } },
10118   },
10119   {
10120     /* VEX_W_0F3A48_P_2 */
10121     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10122     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10123   },
10124   {
10125     /* VEX_W_0F3A49_P_2 */
10126     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10127     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10128   },
10129   {
10130     /* VEX_W_0F3A4A_P_2 */
10131     { "vblendvps",      { XM, Vex, EXx, XMVexI4 } },
10132   },
10133   {
10134     /* VEX_W_0F3A4B_P_2 */
10135     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 } },
10136   },
10137   {
10138     /* VEX_W_0F3A4C_P_2 */
10139     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 } },
10140   },
10141   {
10142     /* VEX_W_0F3A60_P_2 */
10143     { "vpcmpestrm",     { XM, EXx, Ib } },
10144   },
10145   {
10146     /* VEX_W_0F3A61_P_2 */
10147     { "vpcmpestri",     { XM, EXx, Ib } },
10148   },
10149   {
10150     /* VEX_W_0F3A62_P_2 */
10151     { "vpcmpistrm",     { XM, EXx, Ib } },
10152   },
10153   {
10154     /* VEX_W_0F3A63_P_2 */
10155     { "vpcmpistri",     { XM, EXx, Ib } },
10156   },
10157   {
10158     /* VEX_W_0F3ADF_P_2 */
10159     { "vaeskeygenassist", { XM, EXx, Ib } },
10160   },
10161 };
10162
10163 static const struct dis386 mod_table[][2] = {
10164   {
10165     /* MOD_8D */
10166     { "leaS",           { Gv, M } },
10167   },
10168   {
10169     /* MOD_C6_REG_7 */
10170     { Bad_Opcode },
10171     { RM_TABLE (RM_C6_REG_7) },
10172   },
10173   {
10174     /* MOD_C7_REG_7 */
10175     { Bad_Opcode },
10176     { RM_TABLE (RM_C7_REG_7) },
10177   },
10178   {
10179     /* MOD_0F01_REG_0 */
10180     { X86_64_TABLE (X86_64_0F01_REG_0) },
10181     { RM_TABLE (RM_0F01_REG_0) },
10182   },
10183   {
10184     /* MOD_0F01_REG_1 */
10185     { X86_64_TABLE (X86_64_0F01_REG_1) },
10186     { RM_TABLE (RM_0F01_REG_1) },
10187   },
10188   {
10189     /* MOD_0F01_REG_2 */
10190     { X86_64_TABLE (X86_64_0F01_REG_2) },
10191     { RM_TABLE (RM_0F01_REG_2) },
10192   },
10193   {
10194     /* MOD_0F01_REG_3 */
10195     { X86_64_TABLE (X86_64_0F01_REG_3) },
10196     { RM_TABLE (RM_0F01_REG_3) },
10197   },
10198   {
10199     /* MOD_0F01_REG_7 */
10200     { "invlpg",         { Mb } },
10201     { RM_TABLE (RM_0F01_REG_7) },
10202   },
10203   {
10204     /* MOD_0F12_PREFIX_0 */
10205     { "movlps",         { XM, EXq } },
10206     { "movhlps",        { XM, EXq } },
10207   },
10208   {
10209     /* MOD_0F13 */
10210     { "movlpX",         { EXq, XM } },
10211   },
10212   {
10213     /* MOD_0F16_PREFIX_0 */
10214     { "movhps",         { XM, EXq } },
10215     { "movlhps",        { XM, EXq } },
10216   },
10217   {
10218     /* MOD_0F17 */
10219     { "movhpX",         { EXq, XM } },
10220   },
10221   {
10222     /* MOD_0F18_REG_0 */
10223     { "prefetchnta",    { Mb } },
10224   },
10225   {
10226     /* MOD_0F18_REG_1 */
10227     { "prefetcht0",     { Mb } },
10228   },
10229   {
10230     /* MOD_0F18_REG_2 */
10231     { "prefetcht1",     { Mb } },
10232   },
10233   {
10234     /* MOD_0F18_REG_3 */
10235     { "prefetcht2",     { Mb } },
10236   },
10237   {
10238     /* MOD_0F18_REG_4 */
10239     { "nop/reserved",   { Mb } },
10240   },
10241   {
10242     /* MOD_0F18_REG_5 */
10243     { "nop/reserved",   { Mb } },
10244   },
10245   {
10246     /* MOD_0F18_REG_6 */
10247     { "nop/reserved",   { Mb } },
10248   },
10249   {
10250     /* MOD_0F18_REG_7 */
10251     { "nop/reserved",   { Mb } },
10252   },
10253   {
10254     /* MOD_0F20 */
10255     { Bad_Opcode },
10256     { "movZ",           { Rm, Cm } },
10257   },
10258   {
10259     /* MOD_0F21 */
10260     { Bad_Opcode },
10261     { "movZ",           { Rm, Dm } },
10262   },
10263   {
10264     /* MOD_0F22 */
10265     { Bad_Opcode },
10266     { "movZ",           { Cm, Rm } },
10267   },
10268   {
10269     /* MOD_0F23 */
10270     { Bad_Opcode },
10271     { "movZ",           { Dm, Rm } },
10272   },
10273   {
10274     /* MOD_0F24 */
10275     { Bad_Opcode },
10276     { "movL",           { Rd, Td } },
10277   },
10278   {
10279     /* MOD_0F26 */
10280     { Bad_Opcode },
10281     { "movL",           { Td, Rd } },
10282   },
10283   {
10284     /* MOD_0F2B_PREFIX_0 */
10285     {"movntps",         { Mx, XM } },
10286   },
10287   {
10288     /* MOD_0F2B_PREFIX_1 */
10289     {"movntss",         { Md, XM } },
10290   },
10291   {
10292     /* MOD_0F2B_PREFIX_2 */
10293     {"movntpd",         { Mx, XM } },
10294   },
10295   {
10296     /* MOD_0F2B_PREFIX_3 */
10297     {"movntsd",         { Mq, XM } },
10298   },
10299   {
10300     /* MOD_0F51 */
10301     { Bad_Opcode },
10302     { "movmskpX",       { Gdq, XS } },
10303   },
10304   {
10305     /* MOD_0F71_REG_2 */
10306     { Bad_Opcode },
10307     { "psrlw",          { MS, Ib } },
10308   },
10309   {
10310     /* MOD_0F71_REG_4 */
10311     { Bad_Opcode },
10312     { "psraw",          { MS, Ib } },
10313   },
10314   {
10315     /* MOD_0F71_REG_6 */
10316     { Bad_Opcode },
10317     { "psllw",          { MS, Ib } },
10318   },
10319   {
10320     /* MOD_0F72_REG_2 */
10321     { Bad_Opcode },
10322     { "psrld",          { MS, Ib } },
10323   },
10324   {
10325     /* MOD_0F72_REG_4 */
10326     { Bad_Opcode },
10327     { "psrad",          { MS, Ib } },
10328   },
10329   {
10330     /* MOD_0F72_REG_6 */
10331     { Bad_Opcode },
10332     { "pslld",          { MS, Ib } },
10333   },
10334   {
10335     /* MOD_0F73_REG_2 */
10336     { Bad_Opcode },
10337     { "psrlq",          { MS, Ib } },
10338   },
10339   {
10340     /* MOD_0F73_REG_3 */
10341     { Bad_Opcode },
10342     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
10343   },
10344   {
10345     /* MOD_0F73_REG_6 */
10346     { Bad_Opcode },
10347     { "psllq",          { MS, Ib } },
10348   },
10349   {
10350     /* MOD_0F73_REG_7 */
10351     { Bad_Opcode },
10352     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
10353   },
10354   {
10355     /* MOD_0FAE_REG_0 */
10356     { "fxsave",         { FXSAVE } },
10357     { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
10358   },
10359   {
10360     /* MOD_0FAE_REG_1 */
10361     { "fxrstor",        { FXSAVE } },
10362     { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
10363   },
10364   {
10365     /* MOD_0FAE_REG_2 */
10366     { "ldmxcsr",        { Md } },
10367     { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
10368   },
10369   {
10370     /* MOD_0FAE_REG_3 */
10371     { "stmxcsr",        { Md } },
10372     { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
10373   },
10374   {
10375     /* MOD_0FAE_REG_4 */
10376     { "xsave",          { FXSAVE } },
10377   },
10378   {
10379     /* MOD_0FAE_REG_5 */
10380     { "xrstor",         { FXSAVE } },
10381     { RM_TABLE (RM_0FAE_REG_5) },
10382   },
10383   {
10384     /* MOD_0FAE_REG_6 */
10385     { "xsaveopt",       { FXSAVE } },
10386     { RM_TABLE (RM_0FAE_REG_6) },
10387   },
10388   {
10389     /* MOD_0FAE_REG_7 */
10390     { "clflush",        { Mb } },
10391     { RM_TABLE (RM_0FAE_REG_7) },
10392   },
10393   {
10394     /* MOD_0FB2 */
10395     { "lssS",           { Gv, Mp } },
10396   },
10397   {
10398     /* MOD_0FB4 */
10399     { "lfsS",           { Gv, Mp } },
10400   },
10401   {
10402     /* MOD_0FB5 */
10403     { "lgsS",           { Gv, Mp } },
10404   },
10405   {
10406     /* MOD_0FC7_REG_6 */
10407     { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
10408     { "rdrand",         { Ev } },
10409   },
10410   {
10411     /* MOD_0FC7_REG_7 */
10412     { "vmptrst",        { Mq } },
10413     { "rdseed",         { Ev } },
10414   },
10415   {
10416     /* MOD_0FD7 */
10417     { Bad_Opcode },
10418     { "pmovmskb",       { Gdq, MS } },
10419   },
10420   {
10421     /* MOD_0FE7_PREFIX_2 */
10422     { "movntdq",        { Mx, XM } },
10423   },
10424   {
10425     /* MOD_0FF0_PREFIX_3 */
10426     { "lddqu",          { XM, M } },
10427   },
10428   {
10429     /* MOD_0F382A_PREFIX_2 */
10430     { "movntdqa",       { XM, Mx } },
10431   },
10432   {
10433     /* MOD_62_32BIT */
10434     { "bound{S|}",      { Gv, Ma } },
10435   },
10436   {
10437     /* MOD_C4_32BIT */
10438     { "lesS",           { Gv, Mp } },
10439     { VEX_C4_TABLE (VEX_0F) },
10440   },
10441   {
10442     /* MOD_C5_32BIT */
10443     { "ldsS",           { Gv, Mp } },
10444     { VEX_C5_TABLE (VEX_0F) },
10445   },
10446   {
10447     /* MOD_VEX_0F12_PREFIX_0 */
10448     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
10449     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
10450   },
10451   {
10452     /* MOD_VEX_0F13 */
10453     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
10454   },
10455   {
10456     /* MOD_VEX_0F16_PREFIX_0 */
10457     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
10458     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
10459   },
10460   {
10461     /* MOD_VEX_0F17 */
10462     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
10463   },
10464   {
10465     /* MOD_VEX_0F2B */
10466     { VEX_W_TABLE (VEX_W_0F2B_M_0) },
10467   },
10468   {
10469     /* MOD_VEX_0F50 */
10470     { Bad_Opcode },
10471     { VEX_W_TABLE (VEX_W_0F50_M_0) },
10472   },
10473   {
10474     /* MOD_VEX_0F71_REG_2 */
10475     { Bad_Opcode },
10476     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
10477   },
10478   {
10479     /* MOD_VEX_0F71_REG_4 */
10480     { Bad_Opcode },
10481     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
10482   },
10483   {
10484     /* MOD_VEX_0F71_REG_6 */
10485     { Bad_Opcode },
10486     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
10487   },
10488   {
10489     /* MOD_VEX_0F72_REG_2 */
10490     { Bad_Opcode },
10491     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
10492   },
10493   {
10494     /* MOD_VEX_0F72_REG_4 */
10495     { Bad_Opcode },
10496     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
10497   },
10498   {
10499     /* MOD_VEX_0F72_REG_6 */
10500     { Bad_Opcode },
10501     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
10502   },
10503   {
10504     /* MOD_VEX_0F73_REG_2 */
10505     { Bad_Opcode },
10506     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
10507   },
10508   {
10509     /* MOD_VEX_0F73_REG_3 */
10510     { Bad_Opcode },
10511     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
10512   },
10513   {
10514     /* MOD_VEX_0F73_REG_6 */
10515     { Bad_Opcode },
10516     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
10517   },
10518   {
10519     /* MOD_VEX_0F73_REG_7 */
10520     { Bad_Opcode },
10521     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
10522   },
10523   {
10524     /* MOD_VEX_0FAE_REG_2 */
10525     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
10526   },
10527   {
10528     /* MOD_VEX_0FAE_REG_3 */
10529     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
10530   },
10531   {
10532     /* MOD_VEX_0FD7_PREFIX_2 */
10533     { Bad_Opcode },
10534     { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
10535   },
10536   {
10537     /* MOD_VEX_0FE7_PREFIX_2 */
10538     { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
10539   },
10540   {
10541     /* MOD_VEX_0FF0_PREFIX_3 */
10542     { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
10543   },
10544   {
10545     /* MOD_VEX_0F381A_PREFIX_2 */
10546     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
10547   },
10548   {
10549     /* MOD_VEX_0F382A_PREFIX_2 */
10550     { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
10551   },
10552   {
10553     /* MOD_VEX_0F382C_PREFIX_2 */
10554     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
10555   },
10556   {
10557     /* MOD_VEX_0F382D_PREFIX_2 */
10558     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
10559   },
10560   {
10561     /* MOD_VEX_0F382E_PREFIX_2 */
10562     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
10563   },
10564   {
10565     /* MOD_VEX_0F382F_PREFIX_2 */
10566     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
10567   },
10568   {
10569     /* MOD_VEX_0F385A_PREFIX_2 */
10570     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
10571   },
10572   {
10573     /* MOD_VEX_0F388C_PREFIX_2 */
10574     { "vpmaskmov%LW",   { XM, Vex, Mx } },
10575   },
10576   {
10577     /* MOD_VEX_0F388E_PREFIX_2 */
10578     { "vpmaskmov%LW",   { Mx, Vex, XM } },
10579   },
10580 };
10581
10582 static const struct dis386 rm_table[][8] = {
10583   {
10584     /* RM_C6_REG_7 */
10585     { "xabort",         { Skip_MODRM, Ib } },
10586   },
10587   {
10588     /* RM_C7_REG_7 */
10589     { "xbeginT",        { Skip_MODRM, Jv } },
10590   },
10591   {
10592     /* RM_0F01_REG_0 */
10593     { Bad_Opcode },
10594     { "vmcall",         { Skip_MODRM } },
10595     { "vmlaunch",       { Skip_MODRM } },
10596     { "vmresume",       { Skip_MODRM } },
10597     { "vmxoff",         { Skip_MODRM } },
10598   },
10599   {
10600     /* RM_0F01_REG_1 */
10601     { "monitor",        { { OP_Monitor, 0 } } },
10602     { "mwait",          { { OP_Mwait, 0 } } },
10603   },
10604   {
10605     /* RM_0F01_REG_2 */
10606     { "xgetbv",         { Skip_MODRM } },
10607     { "xsetbv",         { Skip_MODRM } },
10608     { Bad_Opcode },
10609     { Bad_Opcode },
10610     { "vmfunc",         { Skip_MODRM } },
10611     { "xend",           { Skip_MODRM } },
10612     { "xtest",          { Skip_MODRM } },
10613     { Bad_Opcode },
10614   },
10615   {
10616     /* RM_0F01_REG_3 */
10617     { "vmrun",          { Skip_MODRM } },
10618     { "vmmcall",        { Skip_MODRM } },
10619     { "vmload",         { Skip_MODRM } },
10620     { "vmsave",         { Skip_MODRM } },
10621     { "stgi",           { Skip_MODRM } },
10622     { "clgi",           { Skip_MODRM } },
10623     { "skinit",         { Skip_MODRM } },
10624     { "invlpga",        { Skip_MODRM } },
10625   },
10626   {
10627     /* RM_0F01_REG_7 */
10628     { "swapgs",         { Skip_MODRM } },
10629     { "rdtscp",         { Skip_MODRM } },
10630   },
10631   {
10632     /* RM_0FAE_REG_5 */
10633     { "lfence",         { Skip_MODRM } },
10634   },
10635   {
10636     /* RM_0FAE_REG_6 */
10637     { "mfence",         { Skip_MODRM } },
10638   },
10639   {
10640     /* RM_0FAE_REG_7 */
10641     { "sfence",         { Skip_MODRM } },
10642   },
10643 };
10644
10645 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
10646
10647 /* We use the high bit to indicate different name for the same
10648    prefix.  */
10649 #define ADDR16_PREFIX   (0x67 | 0x100)
10650 #define ADDR32_PREFIX   (0x67 | 0x200)
10651 #define DATA16_PREFIX   (0x66 | 0x100)
10652 #define DATA32_PREFIX   (0x66 | 0x200)
10653 #define REP_PREFIX      (0xf3 | 0x100)
10654 #define XACQUIRE_PREFIX (0xf2 | 0x200)
10655 #define XRELEASE_PREFIX (0xf3 | 0x400)
10656
10657 static int
10658 ckprefix (void)
10659 {
10660   int newrex, i, length;
10661   rex = 0;
10662   rex_ignored = 0;
10663   prefixes = 0;
10664   used_prefixes = 0;
10665   rex_used = 0;
10666   last_lock_prefix = -1;
10667   last_repz_prefix = -1;
10668   last_repnz_prefix = -1;
10669   last_data_prefix = -1;
10670   last_addr_prefix = -1;
10671   last_rex_prefix = -1;
10672   last_seg_prefix = -1;
10673   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
10674     all_prefixes[i] = 0;
10675   i = 0;
10676   length = 0;
10677   /* The maximum instruction length is 15bytes.  */
10678   while (length < MAX_CODE_LENGTH - 1)
10679     {
10680       FETCH_DATA (the_info, codep + 1);
10681       newrex = 0;
10682       switch (*codep)
10683         {
10684         /* REX prefixes family.  */
10685         case 0x40:
10686         case 0x41:
10687         case 0x42:
10688         case 0x43:
10689         case 0x44:
10690         case 0x45:
10691         case 0x46:
10692         case 0x47:
10693         case 0x48:
10694         case 0x49:
10695         case 0x4a:
10696         case 0x4b:
10697         case 0x4c:
10698         case 0x4d:
10699         case 0x4e:
10700         case 0x4f:
10701           if (address_mode == mode_64bit)
10702             newrex = *codep;
10703           else
10704             return 1;
10705           last_rex_prefix = i;
10706           break;
10707         case 0xf3:
10708           prefixes |= PREFIX_REPZ;
10709           last_repz_prefix = i;
10710           break;
10711         case 0xf2:
10712           prefixes |= PREFIX_REPNZ;
10713           last_repnz_prefix = i;
10714           break;
10715         case 0xf0:
10716           prefixes |= PREFIX_LOCK;
10717           last_lock_prefix = i;
10718           break;
10719         case 0x2e:
10720           prefixes |= PREFIX_CS;
10721           last_seg_prefix = i;
10722           break;
10723         case 0x36:
10724           prefixes |= PREFIX_SS;
10725           last_seg_prefix = i;
10726           break;
10727         case 0x3e:
10728           prefixes |= PREFIX_DS;
10729           last_seg_prefix = i;
10730           break;
10731         case 0x26:
10732           prefixes |= PREFIX_ES;
10733           last_seg_prefix = i;
10734           break;
10735         case 0x64:
10736           prefixes |= PREFIX_FS;
10737           last_seg_prefix = i;
10738           break;
10739         case 0x65:
10740           prefixes |= PREFIX_GS;
10741           last_seg_prefix = i;
10742           break;
10743         case 0x66:
10744           prefixes |= PREFIX_DATA;
10745           last_data_prefix = i;
10746           break;
10747         case 0x67:
10748           prefixes |= PREFIX_ADDR;
10749           last_addr_prefix = i;
10750           break;
10751         case FWAIT_OPCODE:
10752           /* fwait is really an instruction.  If there are prefixes
10753              before the fwait, they belong to the fwait, *not* to the
10754              following instruction.  */
10755           if (prefixes || rex)
10756             {
10757               prefixes |= PREFIX_FWAIT;
10758               codep++;
10759               /* This ensures that the previous REX prefixes are noticed
10760                  as unused prefixes, as in the return case below.  */
10761               rex_used = rex;
10762               return 1;
10763             }
10764           prefixes = PREFIX_FWAIT;
10765           break;
10766         default:
10767           return 1;
10768         }
10769       /* Rex is ignored when followed by another prefix.  */
10770       if (rex)
10771         {
10772           rex_used = rex;
10773           return 1;
10774         }
10775       if (*codep != FWAIT_OPCODE)
10776         all_prefixes[i++] = *codep;
10777       rex = newrex;
10778       codep++;
10779       length++;
10780     }
10781   return 0;
10782 }
10783
10784 static int
10785 seg_prefix (int pref)
10786 {
10787   switch (pref)
10788     {
10789     case 0x2e:
10790       return PREFIX_CS;
10791     case 0x36:
10792       return PREFIX_SS;
10793     case 0x3e:
10794       return PREFIX_DS;
10795     case 0x26:
10796       return PREFIX_ES;
10797     case 0x64:
10798       return PREFIX_FS;
10799     case 0x65:
10800       return PREFIX_GS;
10801     default:
10802       return 0;
10803     }
10804 }
10805
10806 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
10807    prefix byte.  */
10808
10809 static const char *
10810 prefix_name (int pref, int sizeflag)
10811 {
10812   static const char *rexes [16] =
10813     {
10814       "rex",            /* 0x40 */
10815       "rex.B",          /* 0x41 */
10816       "rex.X",          /* 0x42 */
10817       "rex.XB",         /* 0x43 */
10818       "rex.R",          /* 0x44 */
10819       "rex.RB",         /* 0x45 */
10820       "rex.RX",         /* 0x46 */
10821       "rex.RXB",        /* 0x47 */
10822       "rex.W",          /* 0x48 */
10823       "rex.WB",         /* 0x49 */
10824       "rex.WX",         /* 0x4a */
10825       "rex.WXB",        /* 0x4b */
10826       "rex.WR",         /* 0x4c */
10827       "rex.WRB",        /* 0x4d */
10828       "rex.WRX",        /* 0x4e */
10829       "rex.WRXB",       /* 0x4f */
10830     };
10831
10832   switch (pref)
10833     {
10834     /* REX prefixes family.  */
10835     case 0x40:
10836     case 0x41:
10837     case 0x42:
10838     case 0x43:
10839     case 0x44:
10840     case 0x45:
10841     case 0x46:
10842     case 0x47:
10843     case 0x48:
10844     case 0x49:
10845     case 0x4a:
10846     case 0x4b:
10847     case 0x4c:
10848     case 0x4d:
10849     case 0x4e:
10850     case 0x4f:
10851       return rexes [pref - 0x40];
10852     case 0xf3:
10853       return "repz";
10854     case 0xf2:
10855       return "repnz";
10856     case 0xf0:
10857       return "lock";
10858     case 0x2e:
10859       return "cs";
10860     case 0x36:
10861       return "ss";
10862     case 0x3e:
10863       return "ds";
10864     case 0x26:
10865       return "es";
10866     case 0x64:
10867       return "fs";
10868     case 0x65:
10869       return "gs";
10870     case 0x66:
10871       return (sizeflag & DFLAG) ? "data16" : "data32";
10872     case 0x67:
10873       if (address_mode == mode_64bit)
10874         return (sizeflag & AFLAG) ? "addr32" : "addr64";
10875       else
10876         return (sizeflag & AFLAG) ? "addr16" : "addr32";
10877     case FWAIT_OPCODE:
10878       return "fwait";
10879     case ADDR16_PREFIX:
10880       return "addr16";
10881     case ADDR32_PREFIX:
10882       return "addr32";
10883     case DATA16_PREFIX:
10884       return "data16";
10885     case DATA32_PREFIX:
10886       return "data32";
10887     case REP_PREFIX:
10888       return "rep";
10889     case XACQUIRE_PREFIX:
10890       return "xacquire";
10891     case XRELEASE_PREFIX:
10892       return "xrelease";
10893     default:
10894       return NULL;
10895     }
10896 }
10897
10898 static char op_out[MAX_OPERANDS][100];
10899 static int op_ad, op_index[MAX_OPERANDS];
10900 static int two_source_ops;
10901 static bfd_vma op_address[MAX_OPERANDS];
10902 static bfd_vma op_riprel[MAX_OPERANDS];
10903 static bfd_vma start_pc;
10904
10905 /*
10906  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
10907  *   (see topic "Redundant prefixes" in the "Differences from 8086"
10908  *   section of the "Virtual 8086 Mode" chapter.)
10909  * 'pc' should be the address of this instruction, it will
10910  *   be used to print the target address if this is a relative jump or call
10911  * The function returns the length of this instruction in bytes.
10912  */
10913
10914 static char intel_syntax;
10915 static char intel_mnemonic = !SYSV386_COMPAT;
10916 static char open_char;
10917 static char close_char;
10918 static char separator_char;
10919 static char scale_char;
10920
10921 /* Here for backwards compatibility.  When gdb stops using
10922    print_insn_i386_att and print_insn_i386_intel these functions can
10923    disappear, and print_insn_i386 be merged into print_insn.  */
10924 int
10925 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
10926 {
10927   intel_syntax = 0;
10928
10929   return print_insn (pc, info);
10930 }
10931
10932 int
10933 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
10934 {
10935   intel_syntax = 1;
10936
10937   return print_insn (pc, info);
10938 }
10939
10940 int
10941 print_insn_i386 (bfd_vma pc, disassemble_info *info)
10942 {
10943   intel_syntax = -1;
10944
10945   return print_insn (pc, info);
10946 }
10947
10948 void
10949 print_i386_disassembler_options (FILE *stream)
10950 {
10951   fprintf (stream, _("\n\
10952 The following i386/x86-64 specific disassembler options are supported for use\n\
10953 with the -M switch (multiple options should be separated by commas):\n"));
10954
10955   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
10956   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
10957   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
10958   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
10959   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
10960   fprintf (stream, _("  att-mnemonic\n"
10961                      "              Display instruction in AT&T mnemonic\n"));
10962   fprintf (stream, _("  intel-mnemonic\n"
10963                      "              Display instruction in Intel mnemonic\n"));
10964   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
10965   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
10966   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
10967   fprintf (stream, _("  data32      Assume 32bit data size\n"));
10968   fprintf (stream, _("  data16      Assume 16bit data size\n"));
10969   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
10970 }
10971
10972 /* Bad opcode.  */
10973 static const struct dis386 bad_opcode = { "(bad)", { XX } };
10974
10975 /* Get a pointer to struct dis386 with a valid name.  */
10976
10977 static const struct dis386 *
10978 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
10979 {
10980   int vindex, vex_table_index;
10981
10982   if (dp->name != NULL)
10983     return dp;
10984
10985   switch (dp->op[0].bytemode)
10986     {
10987     case USE_REG_TABLE:
10988       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
10989       break;
10990
10991     case USE_MOD_TABLE:
10992       vindex = modrm.mod == 0x3 ? 1 : 0;
10993       dp = &mod_table[dp->op[1].bytemode][vindex];
10994       break;
10995
10996     case USE_RM_TABLE:
10997       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
10998       break;
10999
11000     case USE_PREFIX_TABLE:
11001       if (need_vex)
11002         {
11003           /* The prefix in VEX is implicit.  */
11004           switch (vex.prefix)
11005             {
11006             case 0:
11007               vindex = 0;
11008               break;
11009             case REPE_PREFIX_OPCODE:
11010               vindex = 1;
11011               break;
11012             case DATA_PREFIX_OPCODE:
11013               vindex = 2;
11014               break;
11015             case REPNE_PREFIX_OPCODE:
11016               vindex = 3;
11017               break;
11018             default:
11019               abort ();
11020               break;
11021             }
11022         }
11023       else
11024         {
11025           vindex = 0;
11026           used_prefixes |= (prefixes & PREFIX_REPZ);
11027           if (prefixes & PREFIX_REPZ)
11028             {
11029               vindex = 1;
11030               all_prefixes[last_repz_prefix] = 0;
11031             }
11032           else
11033             {
11034               /* We should check PREFIX_REPNZ and PREFIX_REPZ before
11035                  PREFIX_DATA.  */
11036               used_prefixes |= (prefixes & PREFIX_REPNZ);
11037               if (prefixes & PREFIX_REPNZ)
11038                 {
11039                   vindex = 3;
11040                   all_prefixes[last_repnz_prefix] = 0;
11041                 }
11042               else
11043                 {
11044                   used_prefixes |= (prefixes & PREFIX_DATA);
11045                   if (prefixes & PREFIX_DATA)
11046                     {
11047                       vindex = 2;
11048                       all_prefixes[last_data_prefix] = 0;
11049                     }
11050                 }
11051             }
11052         }
11053       dp = &prefix_table[dp->op[1].bytemode][vindex];
11054       break;
11055
11056     case USE_X86_64_TABLE:
11057       vindex = address_mode == mode_64bit ? 1 : 0;
11058       dp = &x86_64_table[dp->op[1].bytemode][vindex];
11059       break;
11060
11061     case USE_3BYTE_TABLE:
11062       FETCH_DATA (info, codep + 2);
11063       vindex = *codep++;
11064       dp = &three_byte_table[dp->op[1].bytemode][vindex];
11065       modrm.mod = (*codep >> 6) & 3;
11066       modrm.reg = (*codep >> 3) & 7;
11067       modrm.rm = *codep & 7;
11068       break;
11069
11070     case USE_VEX_LEN_TABLE:
11071       if (!need_vex)
11072         abort ();
11073
11074       switch (vex.length)
11075         {
11076         case 128:
11077           vindex = 0;
11078           break;
11079         case 256:
11080           vindex = 1;
11081           break;
11082         default:
11083           abort ();
11084           break;
11085         }
11086
11087       dp = &vex_len_table[dp->op[1].bytemode][vindex];
11088       break;
11089
11090     case USE_XOP_8F_TABLE:
11091       FETCH_DATA (info, codep + 3);
11092       /* All bits in the REX prefix are ignored.  */
11093       rex_ignored = rex;
11094       rex = ~(*codep >> 5) & 0x7;
11095
11096       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
11097       switch ((*codep & 0x1f))
11098         {
11099         default:
11100           dp = &bad_opcode;
11101           return dp;
11102         case 0x8:
11103           vex_table_index = XOP_08;
11104           break;
11105         case 0x9:
11106           vex_table_index = XOP_09;
11107           break;
11108         case 0xa:
11109           vex_table_index = XOP_0A;
11110           break;
11111         }
11112       codep++;
11113       vex.w = *codep & 0x80;
11114       if (vex.w && address_mode == mode_64bit)
11115         rex |= REX_W;
11116
11117       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11118       if (address_mode != mode_64bit
11119           && vex.register_specifier > 0x7)
11120         {
11121           dp = &bad_opcode;
11122           return dp;
11123         }
11124
11125       vex.length = (*codep & 0x4) ? 256 : 128;
11126       switch ((*codep & 0x3))
11127         {
11128         case 0:
11129           vex.prefix = 0;
11130           break;
11131         case 1:
11132           vex.prefix = DATA_PREFIX_OPCODE;
11133           break;
11134         case 2:
11135           vex.prefix = REPE_PREFIX_OPCODE;
11136           break;
11137         case 3:
11138           vex.prefix = REPNE_PREFIX_OPCODE;
11139           break;
11140         }
11141       need_vex = 1;
11142       need_vex_reg = 1;
11143       codep++;
11144       vindex = *codep++;
11145       dp = &xop_table[vex_table_index][vindex];
11146
11147       FETCH_DATA (info, codep + 1);
11148       modrm.mod = (*codep >> 6) & 3;
11149       modrm.reg = (*codep >> 3) & 7;
11150       modrm.rm = *codep & 7;
11151       break;
11152
11153     case USE_VEX_C4_TABLE:
11154       FETCH_DATA (info, codep + 3);
11155       /* All bits in the REX prefix are ignored.  */
11156       rex_ignored = rex;
11157       rex = ~(*codep >> 5) & 0x7;
11158       switch ((*codep & 0x1f))
11159         {
11160         default:
11161           dp = &bad_opcode;
11162           return dp;
11163         case 0x1:
11164           vex_table_index = VEX_0F;
11165           break;
11166         case 0x2:
11167           vex_table_index = VEX_0F38;
11168           break;
11169         case 0x3:
11170           vex_table_index = VEX_0F3A;
11171           break;
11172         }
11173       codep++;
11174       vex.w = *codep & 0x80;
11175       if (vex.w && address_mode == mode_64bit)
11176         rex |= REX_W;
11177
11178       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11179       if (address_mode != mode_64bit
11180           && vex.register_specifier > 0x7)
11181         {
11182           dp = &bad_opcode;
11183           return dp;
11184         }
11185
11186       vex.length = (*codep & 0x4) ? 256 : 128;
11187       switch ((*codep & 0x3))
11188         {
11189         case 0:
11190           vex.prefix = 0;
11191           break;
11192         case 1:
11193           vex.prefix = DATA_PREFIX_OPCODE;
11194           break;
11195         case 2:
11196           vex.prefix = REPE_PREFIX_OPCODE;
11197           break;
11198         case 3:
11199           vex.prefix = REPNE_PREFIX_OPCODE;
11200           break;
11201         }
11202       need_vex = 1;
11203       need_vex_reg = 1;
11204       codep++;
11205       vindex = *codep++;
11206       dp = &vex_table[vex_table_index][vindex];
11207       /* There is no MODRM byte for VEX [82|77].  */
11208       if (vindex != 0x77 && vindex != 0x82)
11209         {
11210           FETCH_DATA (info, codep + 1);
11211           modrm.mod = (*codep >> 6) & 3;
11212           modrm.reg = (*codep >> 3) & 7;
11213           modrm.rm = *codep & 7;
11214         }
11215       break;
11216
11217     case USE_VEX_C5_TABLE:
11218       FETCH_DATA (info, codep + 2);
11219       /* All bits in the REX prefix are ignored.  */
11220       rex_ignored = rex;
11221       rex = (*codep & 0x80) ? 0 : REX_R;
11222
11223       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11224       if (address_mode != mode_64bit
11225           && vex.register_specifier > 0x7)
11226         {
11227           dp = &bad_opcode;
11228           return dp;
11229         }
11230
11231       vex.w = 0;
11232
11233       vex.length = (*codep & 0x4) ? 256 : 128;
11234       switch ((*codep & 0x3))
11235         {
11236         case 0:
11237           vex.prefix = 0;
11238           break;
11239         case 1:
11240           vex.prefix = DATA_PREFIX_OPCODE;
11241           break;
11242         case 2:
11243           vex.prefix = REPE_PREFIX_OPCODE;
11244           break;
11245         case 3:
11246           vex.prefix = REPNE_PREFIX_OPCODE;
11247           break;
11248         }
11249       need_vex = 1;
11250       need_vex_reg = 1;
11251       codep++;
11252       vindex = *codep++;
11253       dp = &vex_table[dp->op[1].bytemode][vindex];
11254       /* There is no MODRM byte for VEX [82|77].  */
11255       if (vindex != 0x77 && vindex != 0x82)
11256         {
11257           FETCH_DATA (info, codep + 1);
11258           modrm.mod = (*codep >> 6) & 3;
11259           modrm.reg = (*codep >> 3) & 7;
11260           modrm.rm = *codep & 7;
11261         }
11262       break;
11263
11264     case USE_VEX_W_TABLE:
11265       if (!need_vex)
11266         abort ();
11267
11268       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
11269       break;
11270
11271     case 0:
11272       dp = &bad_opcode;
11273       break;
11274
11275     default:
11276       abort ();
11277     }
11278
11279   if (dp->name != NULL)
11280     return dp;
11281   else
11282     return get_valid_dis386 (dp, info);
11283 }
11284
11285 static void
11286 get_sib (disassemble_info *info)
11287 {
11288   /* If modrm.mod == 3, operand must be register.  */
11289   if (need_modrm
11290       && address_mode != mode_16bit
11291       && modrm.mod != 3
11292       && modrm.rm == 4)
11293     {
11294       FETCH_DATA (info, codep + 2);
11295       sib.index = (codep [1] >> 3) & 7;
11296       sib.scale = (codep [1] >> 6) & 3;
11297       sib.base = codep [1] & 7;
11298     }
11299 }
11300
11301 static int
11302 print_insn (bfd_vma pc, disassemble_info *info)
11303 {
11304   const struct dis386 *dp;
11305   int i;
11306   char *op_txt[MAX_OPERANDS];
11307   int needcomma;
11308   int sizeflag;
11309   const char *p;
11310   struct dis_private priv;
11311   int prefix_length;
11312   int default_prefixes;
11313
11314   priv.orig_sizeflag = AFLAG | DFLAG;
11315   if ((info->mach & bfd_mach_i386_i386) != 0)
11316     address_mode = mode_32bit;
11317   else if (info->mach == bfd_mach_i386_i8086)
11318     {
11319       address_mode = mode_16bit;
11320       priv.orig_sizeflag = 0;
11321     }
11322   else
11323     address_mode = mode_64bit;
11324
11325   if (intel_syntax == (char) -1)
11326     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
11327
11328   for (p = info->disassembler_options; p != NULL; )
11329     {
11330       if (CONST_STRNEQ (p, "x86-64"))
11331         {
11332           address_mode = mode_64bit;
11333           priv.orig_sizeflag = AFLAG | DFLAG;
11334         }
11335       else if (CONST_STRNEQ (p, "i386"))
11336         {
11337           address_mode = mode_32bit;
11338           priv.orig_sizeflag = AFLAG | DFLAG;
11339         }
11340       else if (CONST_STRNEQ (p, "i8086"))
11341         {
11342           address_mode = mode_16bit;
11343           priv.orig_sizeflag = 0;
11344         }
11345       else if (CONST_STRNEQ (p, "intel"))
11346         {
11347           intel_syntax = 1;
11348           if (CONST_STRNEQ (p + 5, "-mnemonic"))
11349             intel_mnemonic = 1;
11350         }
11351       else if (CONST_STRNEQ (p, "att"))
11352         {
11353           intel_syntax = 0;
11354           if (CONST_STRNEQ (p + 3, "-mnemonic"))
11355             intel_mnemonic = 0;
11356         }
11357       else if (CONST_STRNEQ (p, "addr"))
11358         {
11359           if (address_mode == mode_64bit)
11360             {
11361               if (p[4] == '3' && p[5] == '2')
11362                 priv.orig_sizeflag &= ~AFLAG;
11363               else if (p[4] == '6' && p[5] == '4')
11364                 priv.orig_sizeflag |= AFLAG;
11365             }
11366           else
11367             {
11368               if (p[4] == '1' && p[5] == '6')
11369                 priv.orig_sizeflag &= ~AFLAG;
11370               else if (p[4] == '3' && p[5] == '2')
11371                 priv.orig_sizeflag |= AFLAG;
11372             }
11373         }
11374       else if (CONST_STRNEQ (p, "data"))
11375         {
11376           if (p[4] == '1' && p[5] == '6')
11377             priv.orig_sizeflag &= ~DFLAG;
11378           else if (p[4] == '3' && p[5] == '2')
11379             priv.orig_sizeflag |= DFLAG;
11380         }
11381       else if (CONST_STRNEQ (p, "suffix"))
11382         priv.orig_sizeflag |= SUFFIX_ALWAYS;
11383
11384       p = strchr (p, ',');
11385       if (p != NULL)
11386         p++;
11387     }
11388
11389   if (intel_syntax)
11390     {
11391       names64 = intel_names64;
11392       names32 = intel_names32;
11393       names16 = intel_names16;
11394       names8 = intel_names8;
11395       names8rex = intel_names8rex;
11396       names_seg = intel_names_seg;
11397       names_mm = intel_names_mm;
11398       names_xmm = intel_names_xmm;
11399       names_ymm = intel_names_ymm;
11400       index64 = intel_index64;
11401       index32 = intel_index32;
11402       index16 = intel_index16;
11403       open_char = '[';
11404       close_char = ']';
11405       separator_char = '+';
11406       scale_char = '*';
11407     }
11408   else
11409     {
11410       names64 = att_names64;
11411       names32 = att_names32;
11412       names16 = att_names16;
11413       names8 = att_names8;
11414       names8rex = att_names8rex;
11415       names_seg = att_names_seg;
11416       names_mm = att_names_mm;
11417       names_xmm = att_names_xmm;
11418       names_ymm = att_names_ymm;
11419       index64 = att_index64;
11420       index32 = att_index32;
11421       index16 = att_index16;
11422       open_char = '(';
11423       close_char =  ')';
11424       separator_char = ',';
11425       scale_char = ',';
11426     }
11427
11428   /* The output looks better if we put 7 bytes on a line, since that
11429      puts most long word instructions on a single line.  Use 8 bytes
11430      for Intel L1OM.  */
11431   if ((info->mach & bfd_mach_l1om) != 0)
11432     info->bytes_per_line = 8;
11433   else
11434     info->bytes_per_line = 7;
11435
11436   info->private_data = &priv;
11437   priv.max_fetched = priv.the_buffer;
11438   priv.insn_start = pc;
11439
11440   obuf[0] = 0;
11441   for (i = 0; i < MAX_OPERANDS; ++i)
11442     {
11443       op_out[i][0] = 0;
11444       op_index[i] = -1;
11445     }
11446
11447   the_info = info;
11448   start_pc = pc;
11449   start_codep = priv.the_buffer;
11450   codep = priv.the_buffer;
11451
11452   if (setjmp (priv.bailout) != 0)
11453     {
11454       const char *name;
11455
11456       /* Getting here means we tried for data but didn't get it.  That
11457          means we have an incomplete instruction of some sort.  Just
11458          print the first byte as a prefix or a .byte pseudo-op.  */
11459       if (codep > priv.the_buffer)
11460         {
11461           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
11462           if (name != NULL)
11463             (*info->fprintf_func) (info->stream, "%s", name);
11464           else
11465             {
11466               /* Just print the first byte as a .byte instruction.  */
11467               (*info->fprintf_func) (info->stream, ".byte 0x%x",
11468                                      (unsigned int) priv.the_buffer[0]);
11469             }
11470
11471           return 1;
11472         }
11473
11474       return -1;
11475     }
11476
11477   obufp = obuf;
11478   sizeflag = priv.orig_sizeflag;
11479
11480   if (!ckprefix () || rex_used)
11481     {
11482       /* Too many prefixes or unused REX prefixes.  */
11483       for (i = 0;
11484            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
11485            i++)
11486         (*info->fprintf_func) (info->stream, "%s%s",
11487                                i == 0 ? "" : " ",
11488                                prefix_name (all_prefixes[i], sizeflag));
11489       return i;
11490     }
11491
11492   insn_codep = codep;
11493
11494   FETCH_DATA (info, codep + 1);
11495   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
11496
11497   if (((prefixes & PREFIX_FWAIT)
11498        && ((*codep < 0xd8) || (*codep > 0xdf))))
11499     {
11500       (*info->fprintf_func) (info->stream, "fwait");
11501       return 1;
11502     }
11503
11504   if (*codep == 0x0f)
11505     {
11506       unsigned char threebyte;
11507       FETCH_DATA (info, codep + 2);
11508       threebyte = *++codep;
11509       dp = &dis386_twobyte[threebyte];
11510       need_modrm = twobyte_has_modrm[*codep];
11511       codep++;
11512     }
11513   else
11514     {
11515       dp = &dis386[*codep];
11516       need_modrm = onebyte_has_modrm[*codep];
11517       codep++;
11518     }
11519
11520   if ((prefixes & PREFIX_REPZ))
11521     used_prefixes |= PREFIX_REPZ;
11522   if ((prefixes & PREFIX_REPNZ))
11523     used_prefixes |= PREFIX_REPNZ;
11524   if ((prefixes & PREFIX_LOCK))
11525     used_prefixes |= PREFIX_LOCK;
11526
11527   default_prefixes = 0;
11528   if (prefixes & PREFIX_ADDR)
11529     {
11530       sizeflag ^= AFLAG;
11531       if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax)
11532         {
11533           if ((sizeflag & AFLAG) || address_mode == mode_64bit)
11534             all_prefixes[last_addr_prefix] = ADDR32_PREFIX;
11535           else
11536             all_prefixes[last_addr_prefix] = ADDR16_PREFIX;
11537           default_prefixes |= PREFIX_ADDR;
11538         }
11539     }
11540
11541   if ((prefixes & PREFIX_DATA))
11542     {
11543       sizeflag ^= DFLAG;
11544       if (dp->op[2].bytemode == cond_jump_mode
11545           && dp->op[0].bytemode == v_mode
11546           && !intel_syntax)
11547         {
11548           if (sizeflag & DFLAG)
11549             all_prefixes[last_data_prefix] = DATA32_PREFIX;
11550           else
11551             all_prefixes[last_data_prefix] = DATA16_PREFIX;
11552           default_prefixes |= PREFIX_DATA;
11553         }
11554       else if (rex & REX_W)
11555         {
11556           /* REX_W will override PREFIX_DATA.  */
11557           default_prefixes |= PREFIX_DATA;
11558         }
11559     }
11560
11561   if (need_modrm)
11562     {
11563       FETCH_DATA (info, codep + 1);
11564       modrm.mod = (*codep >> 6) & 3;
11565       modrm.reg = (*codep >> 3) & 7;
11566       modrm.rm = *codep & 7;
11567     }
11568
11569   need_vex = 0;
11570   need_vex_reg = 0;
11571   vex_w_done = 0;
11572
11573   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
11574     {
11575       get_sib (info);
11576       dofloat (sizeflag);
11577     }
11578   else
11579     {
11580       dp = get_valid_dis386 (dp, info);
11581       if (dp != NULL && putop (dp->name, sizeflag) == 0)
11582         {
11583           get_sib (info);
11584           for (i = 0; i < MAX_OPERANDS; ++i)
11585             {
11586               obufp = op_out[i];
11587               op_ad = MAX_OPERANDS - 1 - i;
11588               if (dp->op[i].rtn)
11589                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
11590             }
11591         }
11592     }
11593
11594   /* See if any prefixes were not used.  If so, print the first one
11595      separately.  If we don't do this, we'll wind up printing an
11596      instruction stream which does not precisely correspond to the
11597      bytes we are disassembling.  */
11598   if ((prefixes & ~(used_prefixes | default_prefixes)) != 0)
11599     {
11600       for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11601         if (all_prefixes[i])
11602           {
11603             const char *name;
11604             name = prefix_name (all_prefixes[i], priv.orig_sizeflag);
11605             if (name == NULL)
11606               name = INTERNAL_DISASSEMBLER_ERROR;
11607             (*info->fprintf_func) (info->stream, "%s", name);
11608             return 1;
11609           }
11610     }
11611
11612   /* Check if the REX prefix is used.  */
11613   if (rex_ignored == 0 && (rex ^ rex_used) == 0)
11614     all_prefixes[last_rex_prefix] = 0;
11615
11616   /* Check if the SEG prefix is used.  */
11617   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
11618                    | PREFIX_FS | PREFIX_GS)) != 0
11619       && (used_prefixes
11620           & seg_prefix (all_prefixes[last_seg_prefix])) != 0)
11621     all_prefixes[last_seg_prefix] = 0;
11622
11623   /* Check if the ADDR prefix is used.  */
11624   if ((prefixes & PREFIX_ADDR) != 0
11625       && (used_prefixes & PREFIX_ADDR) != 0)
11626     all_prefixes[last_addr_prefix] = 0;
11627
11628   /* Check if the DATA prefix is used.  */
11629   if ((prefixes & PREFIX_DATA) != 0
11630       && (used_prefixes & PREFIX_DATA) != 0)
11631     all_prefixes[last_data_prefix] = 0;
11632
11633   prefix_length = 0;
11634   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11635     if (all_prefixes[i])
11636       {
11637         const char *name;
11638         name = prefix_name (all_prefixes[i], sizeflag);
11639         if (name == NULL)
11640           abort ();
11641         prefix_length += strlen (name) + 1;
11642         (*info->fprintf_func) (info->stream, "%s ", name);
11643       }
11644
11645   /* Check maximum code length.  */
11646   if ((codep - start_codep) > MAX_CODE_LENGTH)
11647     {
11648       (*info->fprintf_func) (info->stream, "(bad)");
11649       return MAX_CODE_LENGTH;
11650     }
11651
11652   obufp = mnemonicendp;
11653   for (i = strlen (obuf) + prefix_length; i < 6; i++)
11654     oappend (" ");
11655   oappend (" ");
11656   (*info->fprintf_func) (info->stream, "%s", obuf);
11657
11658   /* The enter and bound instructions are printed with operands in the same
11659      order as the intel book; everything else is printed in reverse order.  */
11660   if (intel_syntax || two_source_ops)
11661     {
11662       bfd_vma riprel;
11663
11664       for (i = 0; i < MAX_OPERANDS; ++i)
11665         op_txt[i] = op_out[i];
11666
11667       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
11668         {
11669           op_ad = op_index[i];
11670           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
11671           op_index[MAX_OPERANDS - 1 - i] = op_ad;
11672           riprel = op_riprel[i];
11673           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
11674           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
11675         }
11676     }
11677   else
11678     {
11679       for (i = 0; i < MAX_OPERANDS; ++i)
11680         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
11681     }
11682
11683   needcomma = 0;
11684   for (i = 0; i < MAX_OPERANDS; ++i)
11685     if (*op_txt[i])
11686       {
11687         if (needcomma)
11688           (*info->fprintf_func) (info->stream, ",");
11689         if (op_index[i] != -1 && !op_riprel[i])
11690           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
11691         else
11692           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
11693         needcomma = 1;
11694       }
11695
11696   for (i = 0; i < MAX_OPERANDS; i++)
11697     if (op_index[i] != -1 && op_riprel[i])
11698       {
11699         (*info->fprintf_func) (info->stream, "        # ");
11700         (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
11701                                                 + op_address[op_index[i]]), info);
11702         break;
11703       }
11704   return codep - priv.the_buffer;
11705 }
11706
11707 static const char *float_mem[] = {
11708   /* d8 */
11709   "fadd{s|}",
11710   "fmul{s|}",
11711   "fcom{s|}",
11712   "fcomp{s|}",
11713   "fsub{s|}",
11714   "fsubr{s|}",
11715   "fdiv{s|}",
11716   "fdivr{s|}",
11717   /* d9 */
11718   "fld{s|}",
11719   "(bad)",
11720   "fst{s|}",
11721   "fstp{s|}",
11722   "fldenvIC",
11723   "fldcw",
11724   "fNstenvIC",
11725   "fNstcw",
11726   /* da */
11727   "fiadd{l|}",
11728   "fimul{l|}",
11729   "ficom{l|}",
11730   "ficomp{l|}",
11731   "fisub{l|}",
11732   "fisubr{l|}",
11733   "fidiv{l|}",
11734   "fidivr{l|}",
11735   /* db */
11736   "fild{l|}",
11737   "fisttp{l|}",
11738   "fist{l|}",
11739   "fistp{l|}",
11740   "(bad)",
11741   "fld{t||t|}",
11742   "(bad)",
11743   "fstp{t||t|}",
11744   /* dc */
11745   "fadd{l|}",
11746   "fmul{l|}",
11747   "fcom{l|}",
11748   "fcomp{l|}",
11749   "fsub{l|}",
11750   "fsubr{l|}",
11751   "fdiv{l|}",
11752   "fdivr{l|}",
11753   /* dd */
11754   "fld{l|}",
11755   "fisttp{ll|}",
11756   "fst{l||}",
11757   "fstp{l|}",
11758   "frstorIC",
11759   "(bad)",
11760   "fNsaveIC",
11761   "fNstsw",
11762   /* de */
11763   "fiadd",
11764   "fimul",
11765   "ficom",
11766   "ficomp",
11767   "fisub",
11768   "fisubr",
11769   "fidiv",
11770   "fidivr",
11771   /* df */
11772   "fild",
11773   "fisttp",
11774   "fist",
11775   "fistp",
11776   "fbld",
11777   "fild{ll|}",
11778   "fbstp",
11779   "fistp{ll|}",
11780 };
11781
11782 static const unsigned char float_mem_mode[] = {
11783   /* d8 */
11784   d_mode,
11785   d_mode,
11786   d_mode,
11787   d_mode,
11788   d_mode,
11789   d_mode,
11790   d_mode,
11791   d_mode,
11792   /* d9 */
11793   d_mode,
11794   0,
11795   d_mode,
11796   d_mode,
11797   0,
11798   w_mode,
11799   0,
11800   w_mode,
11801   /* da */
11802   d_mode,
11803   d_mode,
11804   d_mode,
11805   d_mode,
11806   d_mode,
11807   d_mode,
11808   d_mode,
11809   d_mode,
11810   /* db */
11811   d_mode,
11812   d_mode,
11813   d_mode,
11814   d_mode,
11815   0,
11816   t_mode,
11817   0,
11818   t_mode,
11819   /* dc */
11820   q_mode,
11821   q_mode,
11822   q_mode,
11823   q_mode,
11824   q_mode,
11825   q_mode,
11826   q_mode,
11827   q_mode,
11828   /* dd */
11829   q_mode,
11830   q_mode,
11831   q_mode,
11832   q_mode,
11833   0,
11834   0,
11835   0,
11836   w_mode,
11837   /* de */
11838   w_mode,
11839   w_mode,
11840   w_mode,
11841   w_mode,
11842   w_mode,
11843   w_mode,
11844   w_mode,
11845   w_mode,
11846   /* df */
11847   w_mode,
11848   w_mode,
11849   w_mode,
11850   w_mode,
11851   t_mode,
11852   q_mode,
11853   t_mode,
11854   q_mode
11855 };
11856
11857 #define ST { OP_ST, 0 }
11858 #define STi { OP_STi, 0 }
11859
11860 #define FGRPd9_2 NULL, { { NULL, 0 } }
11861 #define FGRPd9_4 NULL, { { NULL, 1 } }
11862 #define FGRPd9_5 NULL, { { NULL, 2 } }
11863 #define FGRPd9_6 NULL, { { NULL, 3 } }
11864 #define FGRPd9_7 NULL, { { NULL, 4 } }
11865 #define FGRPda_5 NULL, { { NULL, 5 } }
11866 #define FGRPdb_4 NULL, { { NULL, 6 } }
11867 #define FGRPde_3 NULL, { { NULL, 7 } }
11868 #define FGRPdf_4 NULL, { { NULL, 8 } }
11869
11870 static const struct dis386 float_reg[][8] = {
11871   /* d8 */
11872   {
11873     { "fadd",   { ST, STi } },
11874     { "fmul",   { ST, STi } },
11875     { "fcom",   { STi } },
11876     { "fcomp",  { STi } },
11877     { "fsub",   { ST, STi } },
11878     { "fsubr",  { ST, STi } },
11879     { "fdiv",   { ST, STi } },
11880     { "fdivr",  { ST, STi } },
11881   },
11882   /* d9 */
11883   {
11884     { "fld",    { STi } },
11885     { "fxch",   { STi } },
11886     { FGRPd9_2 },
11887     { Bad_Opcode },
11888     { FGRPd9_4 },
11889     { FGRPd9_5 },
11890     { FGRPd9_6 },
11891     { FGRPd9_7 },
11892   },
11893   /* da */
11894   {
11895     { "fcmovb", { ST, STi } },
11896     { "fcmove", { ST, STi } },
11897     { "fcmovbe",{ ST, STi } },
11898     { "fcmovu", { ST, STi } },
11899     { Bad_Opcode },
11900     { FGRPda_5 },
11901     { Bad_Opcode },
11902     { Bad_Opcode },
11903   },
11904   /* db */
11905   {
11906     { "fcmovnb",{ ST, STi } },
11907     { "fcmovne",{ ST, STi } },
11908     { "fcmovnbe",{ ST, STi } },
11909     { "fcmovnu",{ ST, STi } },
11910     { FGRPdb_4 },
11911     { "fucomi", { ST, STi } },
11912     { "fcomi",  { ST, STi } },
11913     { Bad_Opcode },
11914   },
11915   /* dc */
11916   {
11917     { "fadd",   { STi, ST } },
11918     { "fmul",   { STi, ST } },
11919     { Bad_Opcode },
11920     { Bad_Opcode },
11921     { "fsub!M", { STi, ST } },
11922     { "fsubM",  { STi, ST } },
11923     { "fdiv!M", { STi, ST } },
11924     { "fdivM",  { STi, ST } },
11925   },
11926   /* dd */
11927   {
11928     { "ffree",  { STi } },
11929     { Bad_Opcode },
11930     { "fst",    { STi } },
11931     { "fstp",   { STi } },
11932     { "fucom",  { STi } },
11933     { "fucomp", { STi } },
11934     { Bad_Opcode },
11935     { Bad_Opcode },
11936   },
11937   /* de */
11938   {
11939     { "faddp",  { STi, ST } },
11940     { "fmulp",  { STi, ST } },
11941     { Bad_Opcode },
11942     { FGRPde_3 },
11943     { "fsub!Mp", { STi, ST } },
11944     { "fsubMp", { STi, ST } },
11945     { "fdiv!Mp", { STi, ST } },
11946     { "fdivMp", { STi, ST } },
11947   },
11948   /* df */
11949   {
11950     { "ffreep", { STi } },
11951     { Bad_Opcode },
11952     { Bad_Opcode },
11953     { Bad_Opcode },
11954     { FGRPdf_4 },
11955     { "fucomip", { ST, STi } },
11956     { "fcomip", { ST, STi } },
11957     { Bad_Opcode },
11958   },
11959 };
11960
11961 static char *fgrps[][8] = {
11962   /* d9_2  0 */
11963   {
11964     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11965   },
11966
11967   /* d9_4  1 */
11968   {
11969     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
11970   },
11971
11972   /* d9_5  2 */
11973   {
11974     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
11975   },
11976
11977   /* d9_6  3 */
11978   {
11979     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
11980   },
11981
11982   /* d9_7  4 */
11983   {
11984     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
11985   },
11986
11987   /* da_5  5 */
11988   {
11989     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11990   },
11991
11992   /* db_4  6 */
11993   {
11994     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
11995     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
11996   },
11997
11998   /* de_3  7 */
11999   {
12000     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12001   },
12002
12003   /* df_4  8 */
12004   {
12005     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12006   },
12007 };
12008
12009 static void
12010 swap_operand (void)
12011 {
12012   mnemonicendp[0] = '.';
12013   mnemonicendp[1] = 's';
12014   mnemonicendp += 2;
12015 }
12016
12017 static void
12018 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
12019                int sizeflag ATTRIBUTE_UNUSED)
12020 {
12021   /* Skip mod/rm byte.  */
12022   MODRM_CHECK;
12023   codep++;
12024 }
12025
12026 static void
12027 dofloat (int sizeflag)
12028 {
12029   const struct dis386 *dp;
12030   unsigned char floatop;
12031
12032   floatop = codep[-1];
12033
12034   if (modrm.mod != 3)
12035     {
12036       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
12037
12038       putop (float_mem[fp_indx], sizeflag);
12039       obufp = op_out[0];
12040       op_ad = 2;
12041       OP_E (float_mem_mode[fp_indx], sizeflag);
12042       return;
12043     }
12044   /* Skip mod/rm byte.  */
12045   MODRM_CHECK;
12046   codep++;
12047
12048   dp = &float_reg[floatop - 0xd8][modrm.reg];
12049   if (dp->name == NULL)
12050     {
12051       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
12052
12053       /* Instruction fnstsw is only one with strange arg.  */
12054       if (floatop == 0xdf && codep[-1] == 0xe0)
12055         strcpy (op_out[0], names16[0]);
12056     }
12057   else
12058     {
12059       putop (dp->name, sizeflag);
12060
12061       obufp = op_out[0];
12062       op_ad = 2;
12063       if (dp->op[0].rtn)
12064         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
12065
12066       obufp = op_out[1];
12067       op_ad = 1;
12068       if (dp->op[1].rtn)
12069         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
12070     }
12071 }
12072
12073 static void
12074 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12075 {
12076   oappend ("%st" + intel_syntax);
12077 }
12078
12079 static void
12080 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12081 {
12082   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
12083   oappend (scratchbuf + intel_syntax);
12084 }
12085
12086 /* Capital letters in template are macros.  */
12087 static int
12088 putop (const char *in_template, int sizeflag)
12089 {
12090   const char *p;
12091   int alt = 0;
12092   int cond = 1;
12093   unsigned int l = 0, len = 1;
12094   char last[4];
12095
12096 #define SAVE_LAST(c)                    \
12097   if (l < len && l < sizeof (last))     \
12098     last[l++] = c;                      \
12099   else                                  \
12100     abort ();
12101
12102   for (p = in_template; *p; p++)
12103     {
12104       switch (*p)
12105         {
12106         default:
12107           *obufp++ = *p;
12108           break;
12109         case '%':
12110           len++;
12111           break;
12112         case '!':
12113           cond = 0;
12114           break;
12115         case '{':
12116           alt = 0;
12117           if (intel_syntax)
12118             {
12119               while (*++p != '|')
12120                 if (*p == '}' || *p == '\0')
12121                   abort ();
12122             }
12123           /* Fall through.  */
12124         case 'I':
12125           alt = 1;
12126           continue;
12127         case '|':
12128           while (*++p != '}')
12129             {
12130               if (*p == '\0')
12131                 abort ();
12132             }
12133           break;
12134         case '}':
12135           break;
12136         case 'A':
12137           if (intel_syntax)
12138             break;
12139           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12140             *obufp++ = 'b';
12141           break;
12142         case 'B':
12143           if (l == 0 && len == 1)
12144             {
12145 case_B:
12146               if (intel_syntax)
12147                 break;
12148               if (sizeflag & SUFFIX_ALWAYS)
12149                 *obufp++ = 'b';
12150             }
12151           else
12152             {
12153               if (l != 1
12154                   || len != 2
12155                   || last[0] != 'L')
12156                 {
12157                   SAVE_LAST (*p);
12158                   break;
12159                 }
12160
12161               if (address_mode == mode_64bit
12162                   && !(prefixes & PREFIX_ADDR))
12163                 {
12164                   *obufp++ = 'a';
12165                   *obufp++ = 'b';
12166                   *obufp++ = 's';
12167                 }
12168
12169               goto case_B;
12170             }
12171           break;
12172         case 'C':
12173           if (intel_syntax && !alt)
12174             break;
12175           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
12176             {
12177               if (sizeflag & DFLAG)
12178                 *obufp++ = intel_syntax ? 'd' : 'l';
12179               else
12180                 *obufp++ = intel_syntax ? 'w' : 's';
12181               used_prefixes |= (prefixes & PREFIX_DATA);
12182             }
12183           break;
12184         case 'D':
12185           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12186             break;
12187           USED_REX (REX_W);
12188           if (modrm.mod == 3)
12189             {
12190               if (rex & REX_W)
12191                 *obufp++ = 'q';
12192               else
12193                 {
12194                   if (sizeflag & DFLAG)
12195                     *obufp++ = intel_syntax ? 'd' : 'l';
12196                   else
12197                     *obufp++ = 'w';
12198                   used_prefixes |= (prefixes & PREFIX_DATA);
12199                 }
12200             }
12201           else
12202             *obufp++ = 'w';
12203           break;
12204         case 'E':               /* For jcxz/jecxz */
12205           if (address_mode == mode_64bit)
12206             {
12207               if (sizeflag & AFLAG)
12208                 *obufp++ = 'r';
12209               else
12210                 *obufp++ = 'e';
12211             }
12212           else
12213             if (sizeflag & AFLAG)
12214               *obufp++ = 'e';
12215           used_prefixes |= (prefixes & PREFIX_ADDR);
12216           break;
12217         case 'F':
12218           if (intel_syntax)
12219             break;
12220           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
12221             {
12222               if (sizeflag & AFLAG)
12223                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
12224               else
12225                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
12226               used_prefixes |= (prefixes & PREFIX_ADDR);
12227             }
12228           break;
12229         case 'G':
12230           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
12231             break;
12232           if ((rex & REX_W) || (sizeflag & DFLAG))
12233             *obufp++ = 'l';
12234           else
12235             *obufp++ = 'w';
12236           if (!(rex & REX_W))
12237             used_prefixes |= (prefixes & PREFIX_DATA);
12238           break;
12239         case 'H':
12240           if (intel_syntax)
12241             break;
12242           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
12243               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
12244             {
12245               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
12246               *obufp++ = ',';
12247               *obufp++ = 'p';
12248               if (prefixes & PREFIX_DS)
12249                 *obufp++ = 't';
12250               else
12251                 *obufp++ = 'n';
12252             }
12253           break;
12254         case 'J':
12255           if (intel_syntax)
12256             break;
12257           *obufp++ = 'l';
12258           break;
12259         case 'K':
12260           USED_REX (REX_W);
12261           if (rex & REX_W)
12262             *obufp++ = 'q';
12263           else
12264             *obufp++ = 'd';
12265           break;
12266         case 'Z':
12267           if (intel_syntax)
12268             break;
12269           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
12270             {
12271               *obufp++ = 'q';
12272               break;
12273             }
12274           /* Fall through.  */
12275           goto case_L;
12276         case 'L':
12277           if (l != 0 || len != 1)
12278             {
12279               SAVE_LAST (*p);
12280               break;
12281             }
12282 case_L:
12283           if (intel_syntax)
12284             break;
12285           if (sizeflag & SUFFIX_ALWAYS)
12286             *obufp++ = 'l';
12287           break;
12288         case 'M':
12289           if (intel_mnemonic != cond)
12290             *obufp++ = 'r';
12291           break;
12292         case 'N':
12293           if ((prefixes & PREFIX_FWAIT) == 0)
12294             *obufp++ = 'n';
12295           else
12296             used_prefixes |= PREFIX_FWAIT;
12297           break;
12298         case 'O':
12299           USED_REX (REX_W);
12300           if (rex & REX_W)
12301             *obufp++ = 'o';
12302           else if (intel_syntax && (sizeflag & DFLAG))
12303             *obufp++ = 'q';
12304           else
12305             *obufp++ = 'd';
12306           if (!(rex & REX_W))
12307             used_prefixes |= (prefixes & PREFIX_DATA);
12308           break;
12309         case 'T':
12310           if (!intel_syntax
12311               && address_mode == mode_64bit
12312               && ((sizeflag & DFLAG) || (rex & REX_W)))
12313             {
12314               *obufp++ = 'q';
12315               break;
12316             }
12317           /* Fall through.  */
12318         case 'P':
12319           if (intel_syntax)
12320             {
12321               if ((rex & REX_W) == 0
12322                   && (prefixes & PREFIX_DATA))
12323                 {
12324                   if ((sizeflag & DFLAG) == 0)
12325                     *obufp++ = 'w';
12326                    used_prefixes |= (prefixes & PREFIX_DATA);
12327                 }
12328               break;
12329             }
12330           if ((prefixes & PREFIX_DATA)
12331               || (rex & REX_W)
12332               || (sizeflag & SUFFIX_ALWAYS))
12333             {
12334               USED_REX (REX_W);
12335               if (rex & REX_W)
12336                 *obufp++ = 'q';
12337               else
12338                 {
12339                    if (sizeflag & DFLAG)
12340                       *obufp++ = 'l';
12341                    else
12342                      *obufp++ = 'w';
12343                    used_prefixes |= (prefixes & PREFIX_DATA);
12344                 }
12345             }
12346           break;
12347         case 'U':
12348           if (intel_syntax)
12349             break;
12350           if (address_mode == mode_64bit
12351               && ((sizeflag & DFLAG) || (rex & REX_W)))
12352             {
12353               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12354                 *obufp++ = 'q';
12355               break;
12356             }
12357           /* Fall through.  */
12358           goto case_Q;
12359         case 'Q':
12360           if (l == 0 && len == 1)
12361             {
12362 case_Q:
12363               if (intel_syntax && !alt)
12364                 break;
12365               USED_REX (REX_W);
12366               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12367                 {
12368                   if (rex & REX_W)
12369                     *obufp++ = 'q';
12370                   else
12371                     {
12372                       if (sizeflag & DFLAG)
12373                         *obufp++ = intel_syntax ? 'd' : 'l';
12374                       else
12375                         *obufp++ = 'w';
12376                       used_prefixes |= (prefixes & PREFIX_DATA);
12377                     }
12378                 }
12379             }
12380           else
12381             {
12382               if (l != 1 || len != 2 || last[0] != 'L')
12383                 {
12384                   SAVE_LAST (*p);
12385                   break;
12386                 }
12387               if (intel_syntax
12388                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
12389                 break;
12390               if ((rex & REX_W))
12391                 {
12392                   USED_REX (REX_W);
12393                   *obufp++ = 'q';
12394                 }
12395               else
12396                 *obufp++ = 'l';
12397             }
12398           break;
12399         case 'R':
12400           USED_REX (REX_W);
12401           if (rex & REX_W)
12402             *obufp++ = 'q';
12403           else if (sizeflag & DFLAG)
12404             {
12405               if (intel_syntax)
12406                   *obufp++ = 'd';
12407               else
12408                   *obufp++ = 'l';
12409             }
12410           else
12411             *obufp++ = 'w';
12412           if (intel_syntax && !p[1]
12413               && ((rex & REX_W) || (sizeflag & DFLAG)))
12414             *obufp++ = 'e';
12415           if (!(rex & REX_W))
12416             used_prefixes |= (prefixes & PREFIX_DATA);
12417           break;
12418         case 'V':
12419           if (l == 0 && len == 1)
12420             {
12421               if (intel_syntax)
12422                 break;
12423               if (address_mode == mode_64bit
12424                   && ((sizeflag & DFLAG) || (rex & REX_W)))
12425                 {
12426                   if (sizeflag & SUFFIX_ALWAYS)
12427                     *obufp++ = 'q';
12428                   break;
12429                 }
12430             }
12431           else
12432             {
12433               if (l != 1
12434                   || len != 2
12435                   || last[0] != 'L')
12436                 {
12437                   SAVE_LAST (*p);
12438                   break;
12439                 }
12440
12441               if (rex & REX_W)
12442                 {
12443                   *obufp++ = 'a';
12444                   *obufp++ = 'b';
12445                   *obufp++ = 's';
12446                 }
12447             }
12448           /* Fall through.  */
12449           goto case_S;
12450         case 'S':
12451           if (l == 0 && len == 1)
12452             {
12453 case_S:
12454               if (intel_syntax)
12455                 break;
12456               if (sizeflag & SUFFIX_ALWAYS)
12457                 {
12458                   if (rex & REX_W)
12459                     *obufp++ = 'q';
12460                   else
12461                     {
12462                       if (sizeflag & DFLAG)
12463                         *obufp++ = 'l';
12464                       else
12465                         *obufp++ = 'w';
12466                       used_prefixes |= (prefixes & PREFIX_DATA);
12467                     }
12468                 }
12469             }
12470           else
12471             {
12472               if (l != 1
12473                   || len != 2
12474                   || last[0] != 'L')
12475                 {
12476                   SAVE_LAST (*p);
12477                   break;
12478                 }
12479
12480               if (address_mode == mode_64bit
12481                   && !(prefixes & PREFIX_ADDR))
12482                 {
12483                   *obufp++ = 'a';
12484                   *obufp++ = 'b';
12485                   *obufp++ = 's';
12486                 }
12487
12488               goto case_S;
12489             }
12490           break;
12491         case 'X':
12492           if (l != 0 || len != 1)
12493             {
12494               SAVE_LAST (*p);
12495               break;
12496             }
12497           if (need_vex && vex.prefix)
12498             {
12499               if (vex.prefix == DATA_PREFIX_OPCODE)
12500                 *obufp++ = 'd';
12501               else
12502                 *obufp++ = 's';
12503             }
12504           else
12505             {
12506               if (prefixes & PREFIX_DATA)
12507                 *obufp++ = 'd';
12508               else
12509                 *obufp++ = 's';
12510               used_prefixes |= (prefixes & PREFIX_DATA);
12511             }
12512           break;
12513         case 'Y':
12514           if (l == 0 && len == 1)
12515             {
12516               if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12517                 break;
12518               if (rex & REX_W)
12519                 {
12520                   USED_REX (REX_W);
12521                   *obufp++ = 'q';
12522                 }
12523               break;
12524             }
12525           else
12526             {
12527               if (l != 1 || len != 2 || last[0] != 'X')
12528                 {
12529                   SAVE_LAST (*p);
12530                   break;
12531                 }
12532               if (!need_vex)
12533                 abort ();
12534               if (intel_syntax
12535                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
12536                 break;
12537               switch (vex.length)
12538                 {
12539                 case 128:
12540                   *obufp++ = 'x';
12541                   break;
12542                 case 256:
12543                   *obufp++ = 'y';
12544                   break;
12545                 default:
12546                   abort ();
12547                 }
12548             }
12549           break;
12550         case 'W':
12551           if (l == 0 && len == 1)
12552             {
12553               /* operand size flag for cwtl, cbtw */
12554               USED_REX (REX_W);
12555               if (rex & REX_W)
12556                 {
12557                   if (intel_syntax)
12558                     *obufp++ = 'd';
12559                   else
12560                     *obufp++ = 'l';
12561                 }
12562               else if (sizeflag & DFLAG)
12563                 *obufp++ = 'w';
12564               else
12565                 *obufp++ = 'b';
12566               if (!(rex & REX_W))
12567                 used_prefixes |= (prefixes & PREFIX_DATA);
12568             }
12569           else
12570             {
12571               if (l != 1
12572                   || len != 2
12573                   || (last[0] != 'X'
12574                       && last[0] != 'L'))
12575                 {
12576                   SAVE_LAST (*p);
12577                   break;
12578                 }
12579               if (!need_vex)
12580                 abort ();
12581               if (last[0] == 'X')
12582                 *obufp++ = vex.w ? 'd': 's';
12583               else
12584                 *obufp++ = vex.w ? 'q': 'd';
12585             }
12586           break;
12587         }
12588       alt = 0;
12589     }
12590   *obufp = 0;
12591   mnemonicendp = obufp;
12592   return 0;
12593 }
12594
12595 static void
12596 oappend (const char *s)
12597 {
12598   obufp = stpcpy (obufp, s);
12599 }
12600
12601 static void
12602 append_seg (void)
12603 {
12604   if (prefixes & PREFIX_CS)
12605     {
12606       used_prefixes |= PREFIX_CS;
12607       oappend ("%cs:" + intel_syntax);
12608     }
12609   if (prefixes & PREFIX_DS)
12610     {
12611       used_prefixes |= PREFIX_DS;
12612       oappend ("%ds:" + intel_syntax);
12613     }
12614   if (prefixes & PREFIX_SS)
12615     {
12616       used_prefixes |= PREFIX_SS;
12617       oappend ("%ss:" + intel_syntax);
12618     }
12619   if (prefixes & PREFIX_ES)
12620     {
12621       used_prefixes |= PREFIX_ES;
12622       oappend ("%es:" + intel_syntax);
12623     }
12624   if (prefixes & PREFIX_FS)
12625     {
12626       used_prefixes |= PREFIX_FS;
12627       oappend ("%fs:" + intel_syntax);
12628     }
12629   if (prefixes & PREFIX_GS)
12630     {
12631       used_prefixes |= PREFIX_GS;
12632       oappend ("%gs:" + intel_syntax);
12633     }
12634 }
12635
12636 static void
12637 OP_indirE (int bytemode, int sizeflag)
12638 {
12639   if (!intel_syntax)
12640     oappend ("*");
12641   OP_E (bytemode, sizeflag);
12642 }
12643
12644 static void
12645 print_operand_value (char *buf, int hex, bfd_vma disp)
12646 {
12647   if (address_mode == mode_64bit)
12648     {
12649       if (hex)
12650         {
12651           char tmp[30];
12652           int i;
12653           buf[0] = '0';
12654           buf[1] = 'x';
12655           sprintf_vma (tmp, disp);
12656           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
12657           strcpy (buf + 2, tmp + i);
12658         }
12659       else
12660         {
12661           bfd_signed_vma v = disp;
12662           char tmp[30];
12663           int i;
12664           if (v < 0)
12665             {
12666               *(buf++) = '-';
12667               v = -disp;
12668               /* Check for possible overflow on 0x8000000000000000.  */
12669               if (v < 0)
12670                 {
12671                   strcpy (buf, "9223372036854775808");
12672                   return;
12673                 }
12674             }
12675           if (!v)
12676             {
12677               strcpy (buf, "0");
12678               return;
12679             }
12680
12681           i = 0;
12682           tmp[29] = 0;
12683           while (v)
12684             {
12685               tmp[28 - i] = (v % 10) + '0';
12686               v /= 10;
12687               i++;
12688             }
12689           strcpy (buf, tmp + 29 - i);
12690         }
12691     }
12692   else
12693     {
12694       if (hex)
12695         sprintf (buf, "0x%x", (unsigned int) disp);
12696       else
12697         sprintf (buf, "%d", (int) disp);
12698     }
12699 }
12700
12701 /* Put DISP in BUF as signed hex number.  */
12702
12703 static void
12704 print_displacement (char *buf, bfd_vma disp)
12705 {
12706   bfd_signed_vma val = disp;
12707   char tmp[30];
12708   int i, j = 0;
12709
12710   if (val < 0)
12711     {
12712       buf[j++] = '-';
12713       val = -disp;
12714
12715       /* Check for possible overflow.  */
12716       if (val < 0)
12717         {
12718           switch (address_mode)
12719             {
12720             case mode_64bit:
12721               strcpy (buf + j, "0x8000000000000000");
12722               break;
12723             case mode_32bit:
12724               strcpy (buf + j, "0x80000000");
12725               break;
12726             case mode_16bit:
12727               strcpy (buf + j, "0x8000");
12728               break;
12729             }
12730           return;
12731         }
12732     }
12733
12734   buf[j++] = '0';
12735   buf[j++] = 'x';
12736
12737   sprintf_vma (tmp, (bfd_vma) val);
12738   for (i = 0; tmp[i] == '0'; i++)
12739     continue;
12740   if (tmp[i] == '\0')
12741     i--;
12742   strcpy (buf + j, tmp + i);
12743 }
12744
12745 static void
12746 intel_operand_size (int bytemode, int sizeflag)
12747 {
12748   switch (bytemode)
12749     {
12750     case b_mode:
12751     case b_swap_mode:
12752     case dqb_mode:
12753       oappend ("BYTE PTR ");
12754       break;
12755     case w_mode:
12756     case dqw_mode:
12757       oappend ("WORD PTR ");
12758       break;
12759     case stack_v_mode:
12760       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
12761         {
12762           oappend ("QWORD PTR ");
12763           break;
12764         }
12765       /* FALLTHRU */
12766     case v_mode:
12767     case v_swap_mode:
12768     case dq_mode:
12769       USED_REX (REX_W);
12770       if (rex & REX_W)
12771         oappend ("QWORD PTR ");
12772       else
12773         {
12774           if ((sizeflag & DFLAG) || bytemode == dq_mode)
12775             oappend ("DWORD PTR ");
12776           else
12777             oappend ("WORD PTR ");
12778           used_prefixes |= (prefixes & PREFIX_DATA);
12779         }
12780       break;
12781     case z_mode:
12782       if ((rex & REX_W) || (sizeflag & DFLAG))
12783         *obufp++ = 'D';
12784       oappend ("WORD PTR ");
12785       if (!(rex & REX_W))
12786         used_prefixes |= (prefixes & PREFIX_DATA);
12787       break;
12788     case a_mode:
12789       if (sizeflag & DFLAG)
12790         oappend ("QWORD PTR ");
12791       else
12792         oappend ("DWORD PTR ");
12793       used_prefixes |= (prefixes & PREFIX_DATA);
12794       break;
12795     case d_mode:
12796     case d_scalar_mode:
12797     case d_scalar_swap_mode:
12798     case d_swap_mode:
12799     case dqd_mode:
12800       oappend ("DWORD PTR ");
12801       break;
12802     case q_mode:
12803     case q_scalar_mode:
12804     case q_scalar_swap_mode:
12805     case q_swap_mode:
12806       oappend ("QWORD PTR ");
12807       break;
12808     case m_mode:
12809       if (address_mode == mode_64bit)
12810         oappend ("QWORD PTR ");
12811       else
12812         oappend ("DWORD PTR ");
12813       break;
12814     case f_mode:
12815       if (sizeflag & DFLAG)
12816         oappend ("FWORD PTR ");
12817       else
12818         oappend ("DWORD PTR ");
12819       used_prefixes |= (prefixes & PREFIX_DATA);
12820       break;
12821     case t_mode:
12822       oappend ("TBYTE PTR ");
12823       break;
12824     case x_mode:
12825     case x_swap_mode:
12826       if (need_vex)
12827         {
12828           switch (vex.length)
12829             {
12830             case 128:
12831               oappend ("XMMWORD PTR ");
12832               break;
12833             case 256:
12834               oappend ("YMMWORD PTR ");
12835               break;
12836             default:
12837               abort ();
12838             }
12839         }
12840       else
12841         oappend ("XMMWORD PTR ");
12842       break;
12843     case xmm_mode:
12844       oappend ("XMMWORD PTR ");
12845       break;
12846     case xmmq_mode:
12847       if (!need_vex)
12848         abort ();
12849
12850       switch (vex.length)
12851         {
12852         case 128:
12853           oappend ("QWORD PTR ");
12854           break;
12855         case 256:
12856           oappend ("XMMWORD PTR ");
12857           break;
12858         default:
12859           abort ();
12860         }
12861       break;
12862     case xmm_mb_mode:
12863       if (!need_vex)
12864         abort ();
12865
12866       switch (vex.length)
12867         {
12868         case 128:
12869         case 256:
12870           oappend ("BYTE PTR ");
12871           break;
12872         default:
12873           abort ();
12874         }
12875       break;
12876     case xmm_mw_mode:
12877       if (!need_vex)
12878         abort ();
12879
12880       switch (vex.length)
12881         {
12882         case 128:
12883         case 256:
12884           oappend ("WORD PTR ");
12885           break;
12886         default:
12887           abort ();
12888         }
12889       break;
12890     case xmm_md_mode:
12891       if (!need_vex)
12892         abort ();
12893
12894       switch (vex.length)
12895         {
12896         case 128:
12897         case 256:
12898           oappend ("DWORD PTR ");
12899           break;
12900         default:
12901           abort ();
12902         }
12903       break;
12904     case xmm_mq_mode:
12905       if (!need_vex)
12906         abort ();
12907
12908       switch (vex.length)
12909         {
12910         case 128:
12911         case 256:
12912           oappend ("QWORD PTR ");
12913           break;
12914         default:
12915           abort ();
12916         }
12917       break;
12918     case xmmdw_mode:
12919       if (!need_vex)
12920         abort ();
12921
12922       switch (vex.length)
12923         {
12924         case 128:
12925           oappend ("WORD PTR ");
12926           break;
12927         case 256:
12928           oappend ("DWORD PTR ");
12929           break;
12930         default:
12931           abort ();
12932         }
12933       break;
12934     case xmmqd_mode:
12935       if (!need_vex)
12936         abort ();
12937
12938       switch (vex.length)
12939         {
12940         case 128:
12941           oappend ("DWORD PTR ");
12942           break;
12943         case 256:
12944           oappend ("QWORD PTR ");
12945           break;
12946         default:
12947           abort ();
12948         }
12949       break;
12950     case ymmq_mode:
12951       if (!need_vex)
12952         abort ();
12953
12954       switch (vex.length)
12955         {
12956         case 128:
12957           oappend ("QWORD PTR ");
12958           break;
12959         case 256:
12960           oappend ("YMMWORD PTR ");
12961           break;
12962         default:
12963           abort ();
12964         }
12965       break;
12966     case ymmxmm_mode:
12967       if (!need_vex)
12968         abort ();
12969
12970       switch (vex.length)
12971         {
12972         case 128:
12973         case 256:
12974           oappend ("XMMWORD PTR ");
12975           break;
12976         default:
12977           abort ();
12978         }
12979       break;
12980     case o_mode:
12981       oappend ("OWORD PTR ");
12982       break;
12983     case vex_w_dq_mode:
12984     case vex_scalar_w_dq_mode:
12985     case vex_vsib_d_w_dq_mode:
12986     case vex_vsib_q_w_dq_mode:
12987       if (!need_vex)
12988         abort ();
12989
12990       if (vex.w)
12991         oappend ("QWORD PTR ");
12992       else
12993         oappend ("DWORD PTR ");
12994       break;
12995     default:
12996       break;
12997     }
12998 }
12999
13000 static void
13001 OP_E_register (int bytemode, int sizeflag)
13002 {
13003   int reg = modrm.rm;
13004   const char **names;
13005
13006   USED_REX (REX_B);
13007   if ((rex & REX_B))
13008     reg += 8;
13009
13010   if ((sizeflag & SUFFIX_ALWAYS)
13011       && (bytemode == b_swap_mode || bytemode == v_swap_mode))
13012     swap_operand ();
13013
13014   switch (bytemode)
13015     {
13016     case b_mode:
13017     case b_swap_mode:
13018       USED_REX (0);
13019       if (rex)
13020         names = names8rex;
13021       else
13022         names = names8;
13023       break;
13024     case w_mode:
13025       names = names16;
13026       break;
13027     case d_mode:
13028       names = names32;
13029       break;
13030     case q_mode:
13031       names = names64;
13032       break;
13033     case m_mode:
13034       names = address_mode == mode_64bit ? names64 : names32;
13035       break;
13036     case stack_v_mode:
13037       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13038         {
13039           names = names64;
13040           break;
13041         }
13042       bytemode = v_mode;
13043       /* FALLTHRU */
13044     case v_mode:
13045     case v_swap_mode:
13046     case dq_mode:
13047     case dqb_mode:
13048     case dqd_mode:
13049     case dqw_mode:
13050       USED_REX (REX_W);
13051       if (rex & REX_W)
13052         names = names64;
13053       else
13054         {
13055           if ((sizeflag & DFLAG)
13056               || (bytemode != v_mode
13057                   && bytemode != v_swap_mode))
13058             names = names32;
13059           else
13060             names = names16;
13061           used_prefixes |= (prefixes & PREFIX_DATA);
13062         }
13063       break;
13064     case 0:
13065       return;
13066     default:
13067       oappend (INTERNAL_DISASSEMBLER_ERROR);
13068       return;
13069     }
13070   oappend (names[reg]);
13071 }
13072
13073 static void
13074 OP_E_memory (int bytemode, int sizeflag)
13075 {
13076   bfd_vma disp = 0;
13077   int add = (rex & REX_B) ? 8 : 0;
13078   int riprel = 0;
13079
13080   USED_REX (REX_B);
13081   if (intel_syntax)
13082     intel_operand_size (bytemode, sizeflag);
13083   append_seg ();
13084
13085   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
13086     {
13087       /* 32/64 bit address mode */
13088       int havedisp;
13089       int havesib;
13090       int havebase;
13091       int haveindex;
13092       int needindex;
13093       int base, rbase;
13094       int vindex = 0;
13095       int scale = 0;
13096       const char **indexes64 = names64;
13097       const char **indexes32 = names32;
13098
13099       havesib = 0;
13100       havebase = 1;
13101       haveindex = 0;
13102       base = modrm.rm;
13103
13104       if (base == 4)
13105         {
13106           havesib = 1;
13107           vindex = sib.index;
13108           USED_REX (REX_X);
13109           if (rex & REX_X)
13110             vindex += 8;
13111           switch (bytemode)
13112             {
13113             case vex_vsib_d_w_dq_mode:
13114             case vex_vsib_q_w_dq_mode:
13115               if (!need_vex)
13116                 abort ();
13117
13118               haveindex = 1;
13119               switch (vex.length)
13120                 {
13121                 case 128:
13122                   indexes64 = indexes32 = names_xmm;
13123                   break;
13124                 case 256:
13125                   if (!vex.w || bytemode == vex_vsib_q_w_dq_mode)
13126                     indexes64 = indexes32 = names_ymm;
13127                   else
13128                     indexes64 = indexes32 = names_xmm;
13129                   break;
13130                 default:
13131                   abort ();
13132                 }
13133               break;
13134             default:
13135               haveindex = vindex != 4;
13136               break;
13137             }
13138           scale = sib.scale;
13139           base = sib.base;
13140           codep++;
13141         }
13142       rbase = base + add;
13143
13144       switch (modrm.mod)
13145         {
13146         case 0:
13147           if (base == 5)
13148             {
13149               havebase = 0;
13150               if (address_mode == mode_64bit && !havesib)
13151                 riprel = 1;
13152               disp = get32s ();
13153             }
13154           break;
13155         case 1:
13156           FETCH_DATA (the_info, codep + 1);
13157           disp = *codep++;
13158           if ((disp & 0x80) != 0)
13159             disp -= 0x100;
13160           break;
13161         case 2:
13162           disp = get32s ();
13163           break;
13164         }
13165
13166       /* In 32bit mode, we need index register to tell [offset] from
13167          [eiz*1 + offset].  */
13168       needindex = (havesib
13169                    && !havebase
13170                    && !haveindex
13171                    && address_mode == mode_32bit);
13172       havedisp = (havebase
13173                   || needindex
13174                   || (havesib && (haveindex || scale != 0)));
13175
13176       if (!intel_syntax)
13177         if (modrm.mod != 0 || base == 5)
13178           {
13179             if (havedisp || riprel)
13180               print_displacement (scratchbuf, disp);
13181             else
13182               print_operand_value (scratchbuf, 1, disp);
13183             oappend (scratchbuf);
13184             if (riprel)
13185               {
13186                 set_op (disp, 1);
13187                 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
13188               }
13189           }
13190
13191       if (havebase || haveindex || riprel)
13192         used_prefixes |= PREFIX_ADDR;
13193
13194       if (havedisp || (intel_syntax && riprel))
13195         {
13196           *obufp++ = open_char;
13197           if (intel_syntax && riprel)
13198             {
13199               set_op (disp, 1);
13200               oappend (sizeflag & AFLAG ? "rip" : "eip");
13201             }
13202           *obufp = '\0';
13203           if (havebase)
13204             oappend (address_mode == mode_64bit && (sizeflag & AFLAG)
13205                      ? names64[rbase] : names32[rbase]);
13206           if (havesib)
13207             {
13208               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
13209                  print index to tell base + index from base.  */
13210               if (scale != 0
13211                   || needindex
13212                   || haveindex
13213                   || (havebase && base != ESP_REG_NUM))
13214                 {
13215                   if (!intel_syntax || havebase)
13216                     {
13217                       *obufp++ = separator_char;
13218                       *obufp = '\0';
13219                     }
13220                   if (haveindex)
13221                     oappend (address_mode == mode_64bit
13222                              && (sizeflag & AFLAG)
13223                              ? indexes64[vindex] : indexes32[vindex]);
13224                   else
13225                     oappend (address_mode == mode_64bit
13226                              && (sizeflag & AFLAG)
13227                              ? index64 : index32);
13228
13229                   *obufp++ = scale_char;
13230                   *obufp = '\0';
13231                   sprintf (scratchbuf, "%d", 1 << scale);
13232                   oappend (scratchbuf);
13233                 }
13234             }
13235           if (intel_syntax
13236               && (disp || modrm.mod != 0 || base == 5))
13237             {
13238               if (!havedisp || (bfd_signed_vma) disp >= 0)
13239                 {
13240                   *obufp++ = '+';
13241                   *obufp = '\0';
13242                 }
13243               else if (modrm.mod != 1 && disp != -disp)
13244                 {
13245                   *obufp++ = '-';
13246                   *obufp = '\0';
13247                   disp = - (bfd_signed_vma) disp;
13248                 }
13249
13250               if (havedisp)
13251                 print_displacement (scratchbuf, disp);
13252               else
13253                 print_operand_value (scratchbuf, 1, disp);
13254               oappend (scratchbuf);
13255             }
13256
13257           *obufp++ = close_char;
13258           *obufp = '\0';
13259         }
13260       else if (intel_syntax)
13261         {
13262           if (modrm.mod != 0 || base == 5)
13263             {
13264               if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13265                               | PREFIX_ES | PREFIX_FS | PREFIX_GS))
13266                 ;
13267               else
13268                 {
13269                   oappend (names_seg[ds_reg - es_reg]);
13270                   oappend (":");
13271                 }
13272               print_operand_value (scratchbuf, 1, disp);
13273               oappend (scratchbuf);
13274             }
13275         }
13276     }
13277   else
13278     {
13279       /* 16 bit address mode */
13280       used_prefixes |= prefixes & PREFIX_ADDR;
13281       switch (modrm.mod)
13282         {
13283         case 0:
13284           if (modrm.rm == 6)
13285             {
13286               disp = get16 ();
13287               if ((disp & 0x8000) != 0)
13288                 disp -= 0x10000;
13289             }
13290           break;
13291         case 1:
13292           FETCH_DATA (the_info, codep + 1);
13293           disp = *codep++;
13294           if ((disp & 0x80) != 0)
13295             disp -= 0x100;
13296           break;
13297         case 2:
13298           disp = get16 ();
13299           if ((disp & 0x8000) != 0)
13300             disp -= 0x10000;
13301           break;
13302         }
13303
13304       if (!intel_syntax)
13305         if (modrm.mod != 0 || modrm.rm == 6)
13306           {
13307             print_displacement (scratchbuf, disp);
13308             oappend (scratchbuf);
13309           }
13310
13311       if (modrm.mod != 0 || modrm.rm != 6)
13312         {
13313           *obufp++ = open_char;
13314           *obufp = '\0';
13315           oappend (index16[modrm.rm]);
13316           if (intel_syntax
13317               && (disp || modrm.mod != 0 || modrm.rm == 6))
13318             {
13319               if ((bfd_signed_vma) disp >= 0)
13320                 {
13321                   *obufp++ = '+';
13322                   *obufp = '\0';
13323                 }
13324               else if (modrm.mod != 1)
13325                 {
13326                   *obufp++ = '-';
13327                   *obufp = '\0';
13328                   disp = - (bfd_signed_vma) disp;
13329                 }
13330
13331               print_displacement (scratchbuf, disp);
13332               oappend (scratchbuf);
13333             }
13334
13335           *obufp++ = close_char;
13336           *obufp = '\0';
13337         }
13338       else if (intel_syntax)
13339         {
13340           if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13341                           | PREFIX_ES | PREFIX_FS | PREFIX_GS))
13342             ;
13343           else
13344             {
13345               oappend (names_seg[ds_reg - es_reg]);
13346               oappend (":");
13347             }
13348           print_operand_value (scratchbuf, 1, disp & 0xffff);
13349           oappend (scratchbuf);
13350         }
13351     }
13352 }
13353
13354 static void
13355 OP_E (int bytemode, int sizeflag)
13356 {
13357   /* Skip mod/rm byte.  */
13358   MODRM_CHECK;
13359   codep++;
13360
13361   if (modrm.mod == 3)
13362     OP_E_register (bytemode, sizeflag);
13363   else
13364     OP_E_memory (bytemode, sizeflag);
13365 }
13366
13367 static void
13368 OP_G (int bytemode, int sizeflag)
13369 {
13370   int add = 0;
13371   USED_REX (REX_R);
13372   if (rex & REX_R)
13373     add += 8;
13374   switch (bytemode)
13375     {
13376     case b_mode:
13377       USED_REX (0);
13378       if (rex)
13379         oappend (names8rex[modrm.reg + add]);
13380       else
13381         oappend (names8[modrm.reg + add]);
13382       break;
13383     case w_mode:
13384       oappend (names16[modrm.reg + add]);
13385       break;
13386     case d_mode:
13387       oappend (names32[modrm.reg + add]);
13388       break;
13389     case q_mode:
13390       oappend (names64[modrm.reg + add]);
13391       break;
13392     case v_mode:
13393     case dq_mode:
13394     case dqb_mode:
13395     case dqd_mode:
13396     case dqw_mode:
13397       USED_REX (REX_W);
13398       if (rex & REX_W)
13399         oappend (names64[modrm.reg + add]);
13400       else
13401         {
13402           if ((sizeflag & DFLAG) || bytemode != v_mode)
13403             oappend (names32[modrm.reg + add]);
13404           else
13405             oappend (names16[modrm.reg + add]);
13406           used_prefixes |= (prefixes & PREFIX_DATA);
13407         }
13408       break;
13409     case m_mode:
13410       if (address_mode == mode_64bit)
13411         oappend (names64[modrm.reg + add]);
13412       else
13413         oappend (names32[modrm.reg + add]);
13414       break;
13415     default:
13416       oappend (INTERNAL_DISASSEMBLER_ERROR);
13417       break;
13418     }
13419 }
13420
13421 static bfd_vma
13422 get64 (void)
13423 {
13424   bfd_vma x;
13425 #ifdef BFD64
13426   unsigned int a;
13427   unsigned int b;
13428
13429   FETCH_DATA (the_info, codep + 8);
13430   a = *codep++ & 0xff;
13431   a |= (*codep++ & 0xff) << 8;
13432   a |= (*codep++ & 0xff) << 16;
13433   a |= (*codep++ & 0xff) << 24;
13434   b = *codep++ & 0xff;
13435   b |= (*codep++ & 0xff) << 8;
13436   b |= (*codep++ & 0xff) << 16;
13437   b |= (*codep++ & 0xff) << 24;
13438   x = a + ((bfd_vma) b << 32);
13439 #else
13440   abort ();
13441   x = 0;
13442 #endif
13443   return x;
13444 }
13445
13446 static bfd_signed_vma
13447 get32 (void)
13448 {
13449   bfd_signed_vma x = 0;
13450
13451   FETCH_DATA (the_info, codep + 4);
13452   x = *codep++ & (bfd_signed_vma) 0xff;
13453   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
13454   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
13455   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
13456   return x;
13457 }
13458
13459 static bfd_signed_vma
13460 get32s (void)
13461 {
13462   bfd_signed_vma x = 0;
13463
13464   FETCH_DATA (the_info, codep + 4);
13465   x = *codep++ & (bfd_signed_vma) 0xff;
13466   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
13467   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
13468   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
13469
13470   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
13471
13472   return x;
13473 }
13474
13475 static int
13476 get16 (void)
13477 {
13478   int x = 0;
13479
13480   FETCH_DATA (the_info, codep + 2);
13481   x = *codep++ & 0xff;
13482   x |= (*codep++ & 0xff) << 8;
13483   return x;
13484 }
13485
13486 static void
13487 set_op (bfd_vma op, int riprel)
13488 {
13489   op_index[op_ad] = op_ad;
13490   if (address_mode == mode_64bit)
13491     {
13492       op_address[op_ad] = op;
13493       op_riprel[op_ad] = riprel;
13494     }
13495   else
13496     {
13497       /* Mask to get a 32-bit address.  */
13498       op_address[op_ad] = op & 0xffffffff;
13499       op_riprel[op_ad] = riprel & 0xffffffff;
13500     }
13501 }
13502
13503 static void
13504 OP_REG (int code, int sizeflag)
13505 {
13506   const char *s;
13507   int add;
13508
13509   switch (code)
13510     {
13511     case es_reg: case ss_reg: case cs_reg:
13512     case ds_reg: case fs_reg: case gs_reg:
13513       oappend (names_seg[code - es_reg]);
13514       return;
13515     }
13516
13517   USED_REX (REX_B);
13518   if (rex & REX_B)
13519     add = 8;
13520   else
13521     add = 0;
13522
13523   switch (code)
13524     {
13525     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
13526     case sp_reg: case bp_reg: case si_reg: case di_reg:
13527       s = names16[code - ax_reg + add];
13528       break;
13529     case al_reg: case ah_reg: case cl_reg: case ch_reg:
13530     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
13531       USED_REX (0);
13532       if (rex)
13533         s = names8rex[code - al_reg + add];
13534       else
13535         s = names8[code - al_reg];
13536       break;
13537     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
13538     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
13539       if (address_mode == mode_64bit
13540           && ((sizeflag & DFLAG) || (rex & REX_W)))
13541         {
13542           s = names64[code - rAX_reg + add];
13543           break;
13544         }
13545       code += eAX_reg - rAX_reg;
13546       /* Fall through.  */
13547     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
13548     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
13549       USED_REX (REX_W);
13550       if (rex & REX_W)
13551         s = names64[code - eAX_reg + add];
13552       else
13553         {
13554           if (sizeflag & DFLAG)
13555             s = names32[code - eAX_reg + add];
13556           else
13557             s = names16[code - eAX_reg + add];
13558           used_prefixes |= (prefixes & PREFIX_DATA);
13559         }
13560       break;
13561     default:
13562       s = INTERNAL_DISASSEMBLER_ERROR;
13563       break;
13564     }
13565   oappend (s);
13566 }
13567
13568 static void
13569 OP_IMREG (int code, int sizeflag)
13570 {
13571   const char *s;
13572
13573   switch (code)
13574     {
13575     case indir_dx_reg:
13576       if (intel_syntax)
13577         s = "dx";
13578       else
13579         s = "(%dx)";
13580       break;
13581     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
13582     case sp_reg: case bp_reg: case si_reg: case di_reg:
13583       s = names16[code - ax_reg];
13584       break;
13585     case es_reg: case ss_reg: case cs_reg:
13586     case ds_reg: case fs_reg: case gs_reg:
13587       s = names_seg[code - es_reg];
13588       break;
13589     case al_reg: case ah_reg: case cl_reg: case ch_reg:
13590     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
13591       USED_REX (0);
13592       if (rex)
13593         s = names8rex[code - al_reg];
13594       else
13595         s = names8[code - al_reg];
13596       break;
13597     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
13598     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
13599       USED_REX (REX_W);
13600       if (rex & REX_W)
13601         s = names64[code - eAX_reg];
13602       else
13603         {
13604           if (sizeflag & DFLAG)
13605             s = names32[code - eAX_reg];
13606           else
13607             s = names16[code - eAX_reg];
13608           used_prefixes |= (prefixes & PREFIX_DATA);
13609         }
13610       break;
13611     case z_mode_ax_reg:
13612       if ((rex & REX_W) || (sizeflag & DFLAG))
13613         s = *names32;
13614       else
13615         s = *names16;
13616       if (!(rex & REX_W))
13617         used_prefixes |= (prefixes & PREFIX_DATA);
13618       break;
13619     default:
13620       s = INTERNAL_DISASSEMBLER_ERROR;
13621       break;
13622     }
13623   oappend (s);
13624 }
13625
13626 static void
13627 OP_I (int bytemode, int sizeflag)
13628 {
13629   bfd_signed_vma op;
13630   bfd_signed_vma mask = -1;
13631
13632   switch (bytemode)
13633     {
13634     case b_mode:
13635       FETCH_DATA (the_info, codep + 1);
13636       op = *codep++;
13637       mask = 0xff;
13638       break;
13639     case q_mode:
13640       if (address_mode == mode_64bit)
13641         {
13642           op = get32s ();
13643           break;
13644         }
13645       /* Fall through.  */
13646     case v_mode:
13647       USED_REX (REX_W);
13648       if (rex & REX_W)
13649         op = get32s ();
13650       else
13651         {
13652           if (sizeflag & DFLAG)
13653             {
13654               op = get32 ();
13655               mask = 0xffffffff;
13656             }
13657           else
13658             {
13659               op = get16 ();
13660               mask = 0xfffff;
13661             }
13662           used_prefixes |= (prefixes & PREFIX_DATA);
13663         }
13664       break;
13665     case w_mode:
13666       mask = 0xfffff;
13667       op = get16 ();
13668       break;
13669     case const_1_mode:
13670       if (intel_syntax)
13671         oappend ("1");
13672       return;
13673     default:
13674       oappend (INTERNAL_DISASSEMBLER_ERROR);
13675       return;
13676     }
13677
13678   op &= mask;
13679   scratchbuf[0] = '$';
13680   print_operand_value (scratchbuf + 1, 1, op);
13681   oappend (scratchbuf + intel_syntax);
13682   scratchbuf[0] = '\0';
13683 }
13684
13685 static void
13686 OP_I64 (int bytemode, int sizeflag)
13687 {
13688   bfd_signed_vma op;
13689   bfd_signed_vma mask = -1;
13690
13691   if (address_mode != mode_64bit)
13692     {
13693       OP_I (bytemode, sizeflag);
13694       return;
13695     }
13696
13697   switch (bytemode)
13698     {
13699     case b_mode:
13700       FETCH_DATA (the_info, codep + 1);
13701       op = *codep++;
13702       mask = 0xff;
13703       break;
13704     case v_mode:
13705       USED_REX (REX_W);
13706       if (rex & REX_W)
13707         op = get64 ();
13708       else
13709         {
13710           if (sizeflag & DFLAG)
13711             {
13712               op = get32 ();
13713               mask = 0xffffffff;
13714             }
13715           else
13716             {
13717               op = get16 ();
13718               mask = 0xfffff;
13719             }
13720           used_prefixes |= (prefixes & PREFIX_DATA);
13721         }
13722       break;
13723     case w_mode:
13724       mask = 0xfffff;
13725       op = get16 ();
13726       break;
13727     default:
13728       oappend (INTERNAL_DISASSEMBLER_ERROR);
13729       return;
13730     }
13731
13732   op &= mask;
13733   scratchbuf[0] = '$';
13734   print_operand_value (scratchbuf + 1, 1, op);
13735   oappend (scratchbuf + intel_syntax);
13736   scratchbuf[0] = '\0';
13737 }
13738
13739 static void
13740 OP_sI (int bytemode, int sizeflag)
13741 {
13742   bfd_signed_vma op;
13743
13744   switch (bytemode)
13745     {
13746     case b_mode:
13747     case b_T_mode:
13748       FETCH_DATA (the_info, codep + 1);
13749       op = *codep++;
13750       if ((op & 0x80) != 0)
13751         op -= 0x100;
13752       if (bytemode == b_T_mode)
13753         {
13754           if (address_mode != mode_64bit
13755               || !((sizeflag & DFLAG) || (rex & REX_W)))
13756             {
13757               /* The operand-size prefix is overridden by a REX prefix.  */
13758               if ((sizeflag & DFLAG) || (rex & REX_W))
13759                 op &= 0xffffffff;
13760               else
13761                 op &= 0xffff;
13762           }
13763         }
13764       else
13765         {
13766           if (!(rex & REX_W))
13767             {
13768               if (sizeflag & DFLAG)
13769                 op &= 0xffffffff;
13770               else
13771                 op &= 0xffff;
13772             }
13773         }
13774       break;
13775     case v_mode:
13776       /* The operand-size prefix is overridden by a REX prefix.  */
13777       if ((sizeflag & DFLAG) || (rex & REX_W))
13778         op = get32s ();
13779       else
13780         op = get16 ();
13781       break;
13782     default:
13783       oappend (INTERNAL_DISASSEMBLER_ERROR);
13784       return;
13785     }
13786
13787   scratchbuf[0] = '$';
13788   print_operand_value (scratchbuf + 1, 1, op);
13789   oappend (scratchbuf + intel_syntax);
13790 }
13791
13792 static void
13793 OP_J (int bytemode, int sizeflag)
13794 {
13795   bfd_vma disp;
13796   bfd_vma mask = -1;
13797   bfd_vma segment = 0;
13798
13799   switch (bytemode)
13800     {
13801     case b_mode:
13802       FETCH_DATA (the_info, codep + 1);
13803       disp = *codep++;
13804       if ((disp & 0x80) != 0)
13805         disp -= 0x100;
13806       break;
13807     case v_mode:
13808       USED_REX (REX_W);
13809       if ((sizeflag & DFLAG) || (rex & REX_W))
13810         disp = get32s ();
13811       else
13812         {
13813           disp = get16 ();
13814           if ((disp & 0x8000) != 0)
13815             disp -= 0x10000;
13816           /* In 16bit mode, address is wrapped around at 64k within
13817              the same segment.  Otherwise, a data16 prefix on a jump
13818              instruction means that the pc is masked to 16 bits after
13819              the displacement is added!  */
13820           mask = 0xffff;
13821           if ((prefixes & PREFIX_DATA) == 0)
13822             segment = ((start_pc + codep - start_codep)
13823                        & ~((bfd_vma) 0xffff));
13824         }
13825       if (!(rex & REX_W))
13826         used_prefixes |= (prefixes & PREFIX_DATA);
13827       break;
13828     default:
13829       oappend (INTERNAL_DISASSEMBLER_ERROR);
13830       return;
13831     }
13832   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
13833   set_op (disp, 0);
13834   print_operand_value (scratchbuf, 1, disp);
13835   oappend (scratchbuf);
13836 }
13837
13838 static void
13839 OP_SEG (int bytemode, int sizeflag)
13840 {
13841   if (bytemode == w_mode)
13842     oappend (names_seg[modrm.reg]);
13843   else
13844     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
13845 }
13846
13847 static void
13848 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
13849 {
13850   int seg, offset;
13851
13852   if (sizeflag & DFLAG)
13853     {
13854       offset = get32 ();
13855       seg = get16 ();
13856     }
13857   else
13858     {
13859       offset = get16 ();
13860       seg = get16 ();
13861     }
13862   used_prefixes |= (prefixes & PREFIX_DATA);
13863   if (intel_syntax)
13864     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
13865   else
13866     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
13867   oappend (scratchbuf);
13868 }
13869
13870 static void
13871 OP_OFF (int bytemode, int sizeflag)
13872 {
13873   bfd_vma off;
13874
13875   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
13876     intel_operand_size (bytemode, sizeflag);
13877   append_seg ();
13878
13879   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
13880     off = get32 ();
13881   else
13882     off = get16 ();
13883
13884   if (intel_syntax)
13885     {
13886       if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13887                         | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
13888         {
13889           oappend (names_seg[ds_reg - es_reg]);
13890           oappend (":");
13891         }
13892     }
13893   print_operand_value (scratchbuf, 1, off);
13894   oappend (scratchbuf);
13895 }
13896
13897 static void
13898 OP_OFF64 (int bytemode, int sizeflag)
13899 {
13900   bfd_vma off;
13901
13902   if (address_mode != mode_64bit
13903       || (prefixes & PREFIX_ADDR))
13904     {
13905       OP_OFF (bytemode, sizeflag);
13906       return;
13907     }
13908
13909   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
13910     intel_operand_size (bytemode, sizeflag);
13911   append_seg ();
13912
13913   off = get64 ();
13914
13915   if (intel_syntax)
13916     {
13917       if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13918                         | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
13919         {
13920           oappend (names_seg[ds_reg - es_reg]);
13921           oappend (":");
13922         }
13923     }
13924   print_operand_value (scratchbuf, 1, off);
13925   oappend (scratchbuf);
13926 }
13927
13928 static void
13929 ptr_reg (int code, int sizeflag)
13930 {
13931   const char *s;
13932
13933   *obufp++ = open_char;
13934   used_prefixes |= (prefixes & PREFIX_ADDR);
13935   if (address_mode == mode_64bit)
13936     {
13937       if (!(sizeflag & AFLAG))
13938         s = names32[code - eAX_reg];
13939       else
13940         s = names64[code - eAX_reg];
13941     }
13942   else if (sizeflag & AFLAG)
13943     s = names32[code - eAX_reg];
13944   else
13945     s = names16[code - eAX_reg];
13946   oappend (s);
13947   *obufp++ = close_char;
13948   *obufp = 0;
13949 }
13950
13951 static void
13952 OP_ESreg (int code, int sizeflag)
13953 {
13954   if (intel_syntax)
13955     {
13956       switch (codep[-1])
13957         {
13958         case 0x6d:      /* insw/insl */
13959           intel_operand_size (z_mode, sizeflag);
13960           break;
13961         case 0xa5:      /* movsw/movsl/movsq */
13962         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
13963         case 0xab:      /* stosw/stosl */
13964         case 0xaf:      /* scasw/scasl */
13965           intel_operand_size (v_mode, sizeflag);
13966           break;
13967         default:
13968           intel_operand_size (b_mode, sizeflag);
13969         }
13970     }
13971   oappend ("%es:" + intel_syntax);
13972   ptr_reg (code, sizeflag);
13973 }
13974
13975 static void
13976 OP_DSreg (int code, int sizeflag)
13977 {
13978   if (intel_syntax)
13979     {
13980       switch (codep[-1])
13981         {
13982         case 0x6f:      /* outsw/outsl */
13983           intel_operand_size (z_mode, sizeflag);
13984           break;
13985         case 0xa5:      /* movsw/movsl/movsq */
13986         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
13987         case 0xad:      /* lodsw/lodsl/lodsq */
13988           intel_operand_size (v_mode, sizeflag);
13989           break;
13990         default:
13991           intel_operand_size (b_mode, sizeflag);
13992         }
13993     }
13994   if ((prefixes
13995        & (PREFIX_CS
13996           | PREFIX_DS
13997           | PREFIX_SS
13998           | PREFIX_ES
13999           | PREFIX_FS
14000           | PREFIX_GS)) == 0)
14001     prefixes |= PREFIX_DS;
14002   append_seg ();
14003   ptr_reg (code, sizeflag);
14004 }
14005
14006 static void
14007 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14008 {
14009   int add;
14010   if (rex & REX_R)
14011     {
14012       USED_REX (REX_R);
14013       add = 8;
14014     }
14015   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
14016     {
14017       all_prefixes[last_lock_prefix] = 0;
14018       used_prefixes |= PREFIX_LOCK;
14019       add = 8;
14020     }
14021   else
14022     add = 0;
14023   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
14024   oappend (scratchbuf + intel_syntax);
14025 }
14026
14027 static void
14028 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14029 {
14030   int add;
14031   USED_REX (REX_R);
14032   if (rex & REX_R)
14033     add = 8;
14034   else
14035     add = 0;
14036   if (intel_syntax)
14037     sprintf (scratchbuf, "db%d", modrm.reg + add);
14038   else
14039     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
14040   oappend (scratchbuf);
14041 }
14042
14043 static void
14044 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14045 {
14046   sprintf (scratchbuf, "%%tr%d", modrm.reg);
14047   oappend (scratchbuf + intel_syntax);
14048 }
14049
14050 static void
14051 OP_R (int bytemode, int sizeflag)
14052 {
14053   if (modrm.mod == 3)
14054     OP_E (bytemode, sizeflag);
14055   else
14056     BadOp ();
14057 }
14058
14059 static void
14060 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14061 {
14062   int reg = modrm.reg;
14063   const char **names;
14064
14065   used_prefixes |= (prefixes & PREFIX_DATA);
14066   if (prefixes & PREFIX_DATA)
14067     {
14068       names = names_xmm;
14069       USED_REX (REX_R);
14070       if (rex & REX_R)
14071         reg += 8;
14072     }
14073   else
14074     names = names_mm;
14075   oappend (names[reg]);
14076 }
14077
14078 static void
14079 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
14080 {
14081   int reg = modrm.reg;
14082   const char **names;
14083
14084   USED_REX (REX_R);
14085   if (rex & REX_R)
14086     reg += 8;
14087   if (need_vex
14088       && bytemode != xmm_mode
14089       && bytemode != scalar_mode)
14090     {
14091       switch (vex.length)
14092         {
14093         case 128:
14094           names = names_xmm;
14095           break;
14096         case 256:
14097           if (vex.w || bytemode != vex_vsib_q_w_dq_mode)
14098             names = names_ymm;
14099           else
14100             names = names_xmm;
14101           break;
14102         default:
14103           abort ();
14104         }
14105     }
14106   else
14107     names = names_xmm;
14108   oappend (names[reg]);
14109 }
14110
14111 static void
14112 OP_EM (int bytemode, int sizeflag)
14113 {
14114   int reg;
14115   const char **names;
14116
14117   if (modrm.mod != 3)
14118     {
14119       if (intel_syntax
14120           && (bytemode == v_mode || bytemode == v_swap_mode))
14121         {
14122           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
14123           used_prefixes |= (prefixes & PREFIX_DATA);
14124         }
14125       OP_E (bytemode, sizeflag);
14126       return;
14127     }
14128
14129   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
14130     swap_operand ();
14131
14132   /* Skip mod/rm byte.  */
14133   MODRM_CHECK;
14134   codep++;
14135   used_prefixes |= (prefixes & PREFIX_DATA);
14136   reg = modrm.rm;
14137   if (prefixes & PREFIX_DATA)
14138     {
14139       names = names_xmm;
14140       USED_REX (REX_B);
14141       if (rex & REX_B)
14142         reg += 8;
14143     }
14144   else
14145     names = names_mm;
14146   oappend (names[reg]);
14147 }
14148
14149 /* cvt* are the only instructions in sse2 which have
14150    both SSE and MMX operands and also have 0x66 prefix
14151    in their opcode. 0x66 was originally used to differentiate
14152    between SSE and MMX instruction(operands). So we have to handle the
14153    cvt* separately using OP_EMC and OP_MXC */
14154 static void
14155 OP_EMC (int bytemode, int sizeflag)
14156 {
14157   if (modrm.mod != 3)
14158     {
14159       if (intel_syntax && bytemode == v_mode)
14160         {
14161           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
14162           used_prefixes |= (prefixes & PREFIX_DATA);
14163         }
14164       OP_E (bytemode, sizeflag);
14165       return;
14166     }
14167
14168   /* Skip mod/rm byte.  */
14169   MODRM_CHECK;
14170   codep++;
14171   used_prefixes |= (prefixes & PREFIX_DATA);
14172   oappend (names_mm[modrm.rm]);
14173 }
14174
14175 static void
14176 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14177 {
14178   used_prefixes |= (prefixes & PREFIX_DATA);
14179   oappend (names_mm[modrm.reg]);
14180 }
14181
14182 static void
14183 OP_EX (int bytemode, int sizeflag)
14184 {
14185   int reg;
14186   const char **names;
14187
14188   /* Skip mod/rm byte.  */
14189   MODRM_CHECK;
14190   codep++;
14191
14192   if (modrm.mod != 3)
14193     {
14194       OP_E_memory (bytemode, sizeflag);
14195       return;
14196     }
14197
14198   reg = modrm.rm;
14199   USED_REX (REX_B);
14200   if (rex & REX_B)
14201     reg += 8;
14202
14203   if ((sizeflag & SUFFIX_ALWAYS)
14204       && (bytemode == x_swap_mode
14205           || bytemode == d_swap_mode
14206           || bytemode == d_scalar_swap_mode
14207           || bytemode == q_swap_mode
14208           || bytemode == q_scalar_swap_mode))
14209     swap_operand ();
14210
14211   if (need_vex
14212       && bytemode != xmm_mode
14213       && bytemode != xmmdw_mode
14214       && bytemode != xmmqd_mode
14215       && bytemode != xmm_mb_mode
14216       && bytemode != xmm_mw_mode
14217       && bytemode != xmm_md_mode
14218       && bytemode != xmm_mq_mode
14219       && bytemode != xmmq_mode
14220       && bytemode != d_scalar_mode
14221       && bytemode != d_scalar_swap_mode
14222       && bytemode != q_scalar_mode
14223       && bytemode != q_scalar_swap_mode
14224       && bytemode != vex_scalar_w_dq_mode)
14225     {
14226       switch (vex.length)
14227         {
14228         case 128:
14229           names = names_xmm;
14230           break;
14231         case 256:
14232           names = names_ymm;
14233           break;
14234         default:
14235           abort ();
14236         }
14237     }
14238   else
14239     names = names_xmm;
14240   oappend (names[reg]);
14241 }
14242
14243 static void
14244 OP_MS (int bytemode, int sizeflag)
14245 {
14246   if (modrm.mod == 3)
14247     OP_EM (bytemode, sizeflag);
14248   else
14249     BadOp ();
14250 }
14251
14252 static void
14253 OP_XS (int bytemode, int sizeflag)
14254 {
14255   if (modrm.mod == 3)
14256     OP_EX (bytemode, sizeflag);
14257   else
14258     BadOp ();
14259 }
14260
14261 static void
14262 OP_M (int bytemode, int sizeflag)
14263 {
14264   if (modrm.mod == 3)
14265     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
14266     BadOp ();
14267   else
14268     OP_E (bytemode, sizeflag);
14269 }
14270
14271 static void
14272 OP_0f07 (int bytemode, int sizeflag)
14273 {
14274   if (modrm.mod != 3 || modrm.rm != 0)
14275     BadOp ();
14276   else
14277     OP_E (bytemode, sizeflag);
14278 }
14279
14280 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
14281    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
14282
14283 static void
14284 NOP_Fixup1 (int bytemode, int sizeflag)
14285 {
14286   if ((prefixes & PREFIX_DATA) != 0
14287       || (rex != 0
14288           && rex != 0x48
14289           && address_mode == mode_64bit))
14290     OP_REG (bytemode, sizeflag);
14291   else
14292     strcpy (obuf, "nop");
14293 }
14294
14295 static void
14296 NOP_Fixup2 (int bytemode, int sizeflag)
14297 {
14298   if ((prefixes & PREFIX_DATA) != 0
14299       || (rex != 0
14300           && rex != 0x48
14301           && address_mode == mode_64bit))
14302     OP_IMREG (bytemode, sizeflag);
14303 }
14304
14305 static const char *const Suffix3DNow[] = {
14306 /* 00 */        NULL,           NULL,           NULL,           NULL,
14307 /* 04 */        NULL,           NULL,           NULL,           NULL,
14308 /* 08 */        NULL,           NULL,           NULL,           NULL,
14309 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
14310 /* 10 */        NULL,           NULL,           NULL,           NULL,
14311 /* 14 */        NULL,           NULL,           NULL,           NULL,
14312 /* 18 */        NULL,           NULL,           NULL,           NULL,
14313 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
14314 /* 20 */        NULL,           NULL,           NULL,           NULL,
14315 /* 24 */        NULL,           NULL,           NULL,           NULL,
14316 /* 28 */        NULL,           NULL,           NULL,           NULL,
14317 /* 2C */        NULL,           NULL,           NULL,           NULL,
14318 /* 30 */        NULL,           NULL,           NULL,           NULL,
14319 /* 34 */        NULL,           NULL,           NULL,           NULL,
14320 /* 38 */        NULL,           NULL,           NULL,           NULL,
14321 /* 3C */        NULL,           NULL,           NULL,           NULL,
14322 /* 40 */        NULL,           NULL,           NULL,           NULL,
14323 /* 44 */        NULL,           NULL,           NULL,           NULL,
14324 /* 48 */        NULL,           NULL,           NULL,           NULL,
14325 /* 4C */        NULL,           NULL,           NULL,           NULL,
14326 /* 50 */        NULL,           NULL,           NULL,           NULL,
14327 /* 54 */        NULL,           NULL,           NULL,           NULL,
14328 /* 58 */        NULL,           NULL,           NULL,           NULL,
14329 /* 5C */        NULL,           NULL,           NULL,           NULL,
14330 /* 60 */        NULL,           NULL,           NULL,           NULL,
14331 /* 64 */        NULL,           NULL,           NULL,           NULL,
14332 /* 68 */        NULL,           NULL,           NULL,           NULL,
14333 /* 6C */        NULL,           NULL,           NULL,           NULL,
14334 /* 70 */        NULL,           NULL,           NULL,           NULL,
14335 /* 74 */        NULL,           NULL,           NULL,           NULL,
14336 /* 78 */        NULL,           NULL,           NULL,           NULL,
14337 /* 7C */        NULL,           NULL,           NULL,           NULL,
14338 /* 80 */        NULL,           NULL,           NULL,           NULL,
14339 /* 84 */        NULL,           NULL,           NULL,           NULL,
14340 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
14341 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
14342 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
14343 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
14344 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
14345 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
14346 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
14347 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
14348 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
14349 /* AC */        NULL,           NULL,           "pfacc",        NULL,
14350 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
14351 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
14352 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
14353 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
14354 /* C0 */        NULL,           NULL,           NULL,           NULL,
14355 /* C4 */        NULL,           NULL,           NULL,           NULL,
14356 /* C8 */        NULL,           NULL,           NULL,           NULL,
14357 /* CC */        NULL,           NULL,           NULL,           NULL,
14358 /* D0 */        NULL,           NULL,           NULL,           NULL,
14359 /* D4 */        NULL,           NULL,           NULL,           NULL,
14360 /* D8 */        NULL,           NULL,           NULL,           NULL,
14361 /* DC */        NULL,           NULL,           NULL,           NULL,
14362 /* E0 */        NULL,           NULL,           NULL,           NULL,
14363 /* E4 */        NULL,           NULL,           NULL,           NULL,
14364 /* E8 */        NULL,           NULL,           NULL,           NULL,
14365 /* EC */        NULL,           NULL,           NULL,           NULL,
14366 /* F0 */        NULL,           NULL,           NULL,           NULL,
14367 /* F4 */        NULL,           NULL,           NULL,           NULL,
14368 /* F8 */        NULL,           NULL,           NULL,           NULL,
14369 /* FC */        NULL,           NULL,           NULL,           NULL,
14370 };
14371
14372 static void
14373 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14374 {
14375   const char *mnemonic;
14376
14377   FETCH_DATA (the_info, codep + 1);
14378   /* AMD 3DNow! instructions are specified by an opcode suffix in the
14379      place where an 8-bit immediate would normally go.  ie. the last
14380      byte of the instruction.  */
14381   obufp = mnemonicendp;
14382   mnemonic = Suffix3DNow[*codep++ & 0xff];
14383   if (mnemonic)
14384     oappend (mnemonic);
14385   else
14386     {
14387       /* Since a variable sized modrm/sib chunk is between the start
14388          of the opcode (0x0f0f) and the opcode suffix, we need to do
14389          all the modrm processing first, and don't know until now that
14390          we have a bad opcode.  This necessitates some cleaning up.  */
14391       op_out[0][0] = '\0';
14392       op_out[1][0] = '\0';
14393       BadOp ();
14394     }
14395   mnemonicendp = obufp;
14396 }
14397
14398 static struct op simd_cmp_op[] =
14399 {
14400   { STRING_COMMA_LEN ("eq") },
14401   { STRING_COMMA_LEN ("lt") },
14402   { STRING_COMMA_LEN ("le") },
14403   { STRING_COMMA_LEN ("unord") },
14404   { STRING_COMMA_LEN ("neq") },
14405   { STRING_COMMA_LEN ("nlt") },
14406   { STRING_COMMA_LEN ("nle") },
14407   { STRING_COMMA_LEN ("ord") }
14408 };
14409
14410 static void
14411 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14412 {
14413   unsigned int cmp_type;
14414
14415   FETCH_DATA (the_info, codep + 1);
14416   cmp_type = *codep++ & 0xff;
14417   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
14418     {
14419       char suffix [3];
14420       char *p = mnemonicendp - 2;
14421       suffix[0] = p[0];
14422       suffix[1] = p[1];
14423       suffix[2] = '\0';
14424       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
14425       mnemonicendp += simd_cmp_op[cmp_type].len;
14426     }
14427   else
14428     {
14429       /* We have a reserved extension byte.  Output it directly.  */
14430       scratchbuf[0] = '$';
14431       print_operand_value (scratchbuf + 1, 1, cmp_type);
14432       oappend (scratchbuf + intel_syntax);
14433       scratchbuf[0] = '\0';
14434     }
14435 }
14436
14437 static void
14438 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
14439           int sizeflag ATTRIBUTE_UNUSED)
14440 {
14441   /* mwait %eax,%ecx  */
14442   if (!intel_syntax)
14443     {
14444       const char **names = (address_mode == mode_64bit
14445                             ? names64 : names32);
14446       strcpy (op_out[0], names[0]);
14447       strcpy (op_out[1], names[1]);
14448       two_source_ops = 1;
14449     }
14450   /* Skip mod/rm byte.  */
14451   MODRM_CHECK;
14452   codep++;
14453 }
14454
14455 static void
14456 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
14457             int sizeflag ATTRIBUTE_UNUSED)
14458 {
14459   /* monitor %eax,%ecx,%edx"  */
14460   if (!intel_syntax)
14461     {
14462       const char **op1_names;
14463       const char **names = (address_mode == mode_64bit
14464                             ? names64 : names32);
14465
14466       if (!(prefixes & PREFIX_ADDR))
14467         op1_names = (address_mode == mode_16bit
14468                      ? names16 : names);
14469       else
14470         {
14471           /* Remove "addr16/addr32".  */
14472           all_prefixes[last_addr_prefix] = 0;
14473           op1_names = (address_mode != mode_32bit
14474                        ? names32 : names16);
14475           used_prefixes |= PREFIX_ADDR;
14476         }
14477       strcpy (op_out[0], op1_names[0]);
14478       strcpy (op_out[1], names[1]);
14479       strcpy (op_out[2], names[2]);
14480       two_source_ops = 1;
14481     }
14482   /* Skip mod/rm byte.  */
14483   MODRM_CHECK;
14484   codep++;
14485 }
14486
14487 static void
14488 BadOp (void)
14489 {
14490   /* Throw away prefixes and 1st. opcode byte.  */
14491   codep = insn_codep + 1;
14492   oappend ("(bad)");
14493 }
14494
14495 static void
14496 REP_Fixup (int bytemode, int sizeflag)
14497 {
14498   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
14499      lods and stos.  */
14500   if (prefixes & PREFIX_REPZ)
14501     all_prefixes[last_repz_prefix] = REP_PREFIX;
14502
14503   switch (bytemode)
14504     {
14505     case al_reg:
14506     case eAX_reg:
14507     case indir_dx_reg:
14508       OP_IMREG (bytemode, sizeflag);
14509       break;
14510     case eDI_reg:
14511       OP_ESreg (bytemode, sizeflag);
14512       break;
14513     case eSI_reg:
14514       OP_DSreg (bytemode, sizeflag);
14515       break;
14516     default:
14517       abort ();
14518       break;
14519     }
14520 }
14521
14522 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
14523    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
14524  */
14525
14526 static void
14527 HLE_Fixup1 (int bytemode, int sizeflag)
14528 {
14529   if (modrm.mod != 3
14530       && (prefixes & PREFIX_LOCK) != 0)
14531     {
14532       if (prefixes & PREFIX_REPZ)
14533         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
14534       if (prefixes & PREFIX_REPNZ)
14535         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
14536     }
14537
14538   OP_E (bytemode, sizeflag);
14539 }
14540
14541 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
14542    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
14543  */
14544
14545 static void
14546 HLE_Fixup2 (int bytemode, int sizeflag)
14547 {
14548   if (modrm.mod != 3)
14549     {
14550       if (prefixes & PREFIX_REPZ)
14551         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
14552       if (prefixes & PREFIX_REPNZ)
14553         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
14554     }
14555
14556   OP_E (bytemode, sizeflag);
14557 }
14558
14559 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
14560    "xrelease" for memory operand.  No check for LOCK prefix.   */
14561
14562 static void
14563 HLE_Fixup3 (int bytemode, int sizeflag)
14564 {
14565   if (modrm.mod != 3
14566       && last_repz_prefix > last_repnz_prefix
14567       && (prefixes & PREFIX_REPZ) != 0)
14568     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
14569
14570   OP_E (bytemode, sizeflag);
14571 }
14572
14573 static void
14574 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
14575 {
14576   USED_REX (REX_W);
14577   if (rex & REX_W)
14578     {
14579       /* Change cmpxchg8b to cmpxchg16b.  */
14580       char *p = mnemonicendp - 2;
14581       mnemonicendp = stpcpy (p, "16b");
14582       bytemode = o_mode;
14583     }
14584   else if ((prefixes & PREFIX_LOCK) != 0)
14585     {
14586       if (prefixes & PREFIX_REPZ)
14587         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
14588       if (prefixes & PREFIX_REPNZ)
14589         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
14590     }
14591
14592   OP_M (bytemode, sizeflag);
14593 }
14594
14595 static void
14596 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
14597 {
14598   const char **names;
14599
14600   if (need_vex)
14601     {
14602       switch (vex.length)
14603         {
14604         case 128:
14605           names = names_xmm;
14606           break;
14607         case 256:
14608           names = names_ymm;
14609           break;
14610         default:
14611           abort ();
14612         }
14613     }
14614   else
14615     names = names_xmm;
14616   oappend (names[reg]);
14617 }
14618
14619 static void
14620 CRC32_Fixup (int bytemode, int sizeflag)
14621 {
14622   /* Add proper suffix to "crc32".  */
14623   char *p = mnemonicendp;
14624
14625   switch (bytemode)
14626     {
14627     case b_mode:
14628       if (intel_syntax)
14629         goto skip;
14630
14631       *p++ = 'b';
14632       break;
14633     case v_mode:
14634       if (intel_syntax)
14635         goto skip;
14636
14637       USED_REX (REX_W);
14638       if (rex & REX_W)
14639         *p++ = 'q';
14640       else
14641         {
14642           if (sizeflag & DFLAG)
14643             *p++ = 'l';
14644           else
14645             *p++ = 'w';
14646           used_prefixes |= (prefixes & PREFIX_DATA);
14647         }
14648       break;
14649     default:
14650       oappend (INTERNAL_DISASSEMBLER_ERROR);
14651       break;
14652     }
14653   mnemonicendp = p;
14654   *p = '\0';
14655
14656 skip:
14657   if (modrm.mod == 3)
14658     {
14659       int add;
14660
14661       /* Skip mod/rm byte.  */
14662       MODRM_CHECK;
14663       codep++;
14664
14665       USED_REX (REX_B);
14666       add = (rex & REX_B) ? 8 : 0;
14667       if (bytemode == b_mode)
14668         {
14669           USED_REX (0);
14670           if (rex)
14671             oappend (names8rex[modrm.rm + add]);
14672           else
14673             oappend (names8[modrm.rm + add]);
14674         }
14675       else
14676         {
14677           USED_REX (REX_W);
14678           if (rex & REX_W)
14679             oappend (names64[modrm.rm + add]);
14680           else if ((prefixes & PREFIX_DATA))
14681             oappend (names16[modrm.rm + add]);
14682           else
14683             oappend (names32[modrm.rm + add]);
14684         }
14685     }
14686   else
14687     OP_E (bytemode, sizeflag);
14688 }
14689
14690 static void
14691 FXSAVE_Fixup (int bytemode, int sizeflag)
14692 {
14693   /* Add proper suffix to "fxsave" and "fxrstor".  */
14694   USED_REX (REX_W);
14695   if (rex & REX_W)
14696     {
14697       char *p = mnemonicendp;
14698       *p++ = '6';
14699       *p++ = '4';
14700       *p = '\0';
14701       mnemonicendp = p;
14702     }
14703   OP_M (bytemode, sizeflag);
14704 }
14705
14706 /* Display the destination register operand for instructions with
14707    VEX. */
14708
14709 static void
14710 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
14711 {
14712   int reg;
14713   const char **names;
14714
14715   if (!need_vex)
14716     abort ();
14717
14718   if (!need_vex_reg)
14719     return;
14720
14721   reg = vex.register_specifier;
14722   if (bytemode == vex_scalar_mode)
14723     {
14724       oappend (names_xmm[reg]);
14725       return;
14726     }
14727
14728   switch (vex.length)
14729     {
14730     case 128:
14731       switch (bytemode)
14732         {
14733         case vex_mode:
14734         case vex128_mode:
14735         case vex_vsib_q_w_dq_mode:
14736           names = names_xmm;
14737           break;
14738         case dq_mode:
14739           if (vex.w)
14740             names = names64;
14741           else
14742             names = names32;
14743           break;
14744         default:
14745           abort ();
14746           return;
14747         }
14748       break;
14749     case 256:
14750       switch (bytemode)
14751         {
14752         case vex_mode:
14753         case vex256_mode:
14754           names = names_ymm;
14755           break;
14756         case vex_vsib_q_w_dq_mode:
14757           names = vex.w ? names_ymm : names_xmm;
14758           break;
14759         default:
14760           abort ();
14761           return;
14762         }
14763       break;
14764     default:
14765       abort ();
14766       break;
14767     }
14768   oappend (names[reg]);
14769 }
14770
14771 /* Get the VEX immediate byte without moving codep.  */
14772
14773 static unsigned char
14774 get_vex_imm8 (int sizeflag, int opnum)
14775 {
14776   int bytes_before_imm = 0;
14777
14778   if (modrm.mod != 3)
14779     {
14780       /* There are SIB/displacement bytes.  */
14781       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14782         {
14783           /* 32/64 bit address mode */
14784           int base = modrm.rm;
14785
14786           /* Check SIB byte.  */
14787           if (base == 4)
14788             {
14789               FETCH_DATA (the_info, codep + 1);
14790               base = *codep & 7;
14791               /* When decoding the third source, don't increase
14792                  bytes_before_imm as this has already been incremented
14793                  by one in OP_E_memory while decoding the second
14794                  source operand.  */
14795               if (opnum == 0)
14796                 bytes_before_imm++;
14797             }
14798
14799           /* Don't increase bytes_before_imm when decoding the third source,
14800              it has already been incremented by OP_E_memory while decoding
14801              the second source operand.  */
14802           if (opnum == 0)
14803             {
14804               switch (modrm.mod)
14805                 {
14806                   case 0:
14807                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
14808                        SIB == 5, there is a 4 byte displacement.  */
14809                     if (base != 5)
14810                       /* No displacement. */
14811                       break;
14812                   case 2:
14813                     /* 4 byte displacement.  */
14814                     bytes_before_imm += 4;
14815                     break;
14816                   case 1:
14817                     /* 1 byte displacement.  */
14818                     bytes_before_imm++;
14819                     break;
14820                 }
14821             }
14822         }
14823       else
14824         {
14825           /* 16 bit address mode */
14826           /* Don't increase bytes_before_imm when decoding the third source,
14827              it has already been incremented by OP_E_memory while decoding
14828              the second source operand.  */
14829           if (opnum == 0)
14830             {
14831               switch (modrm.mod)
14832                 {
14833                 case 0:
14834                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
14835                   if (modrm.rm != 6)
14836                     /* No displacement. */
14837                     break;
14838                 case 2:
14839                   /* 2 byte displacement.  */
14840                   bytes_before_imm += 2;
14841                   break;
14842                 case 1:
14843                   /* 1 byte displacement: when decoding the third source,
14844                      don't increase bytes_before_imm as this has already
14845                      been incremented by one in OP_E_memory while decoding
14846                      the second source operand.  */
14847                   if (opnum == 0)
14848                     bytes_before_imm++;
14849
14850                   break;
14851                 }
14852             }
14853         }
14854     }
14855
14856   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
14857   return codep [bytes_before_imm];
14858 }
14859
14860 static void
14861 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
14862 {
14863   const char **names;
14864
14865   if (reg == -1 && modrm.mod != 3)
14866     {
14867       OP_E_memory (bytemode, sizeflag);
14868       return;
14869     }
14870   else
14871     {
14872       if (reg == -1)
14873         {
14874           reg = modrm.rm;
14875           USED_REX (REX_B);
14876           if (rex & REX_B)
14877             reg += 8;
14878         }
14879       else if (reg > 7 && address_mode != mode_64bit)
14880         BadOp ();
14881     }
14882
14883   switch (vex.length)
14884     {
14885     case 128:
14886       names = names_xmm;
14887       break;
14888     case 256:
14889       names = names_ymm;
14890       break;
14891     default:
14892       abort ();
14893     }
14894   oappend (names[reg]);
14895 }
14896
14897 static void
14898 OP_EX_VexImmW (int bytemode, int sizeflag)
14899 {
14900   int reg = -1;
14901   static unsigned char vex_imm8;
14902
14903   if (vex_w_done == 0)
14904     {
14905       vex_w_done = 1;
14906
14907       /* Skip mod/rm byte.  */
14908       MODRM_CHECK;
14909       codep++;
14910
14911       vex_imm8 = get_vex_imm8 (sizeflag, 0);
14912
14913       if (vex.w)
14914           reg = vex_imm8 >> 4;
14915
14916       OP_EX_VexReg (bytemode, sizeflag, reg);
14917     }
14918   else if (vex_w_done == 1)
14919     {
14920       vex_w_done = 2;
14921
14922       if (!vex.w)
14923           reg = vex_imm8 >> 4;
14924
14925       OP_EX_VexReg (bytemode, sizeflag, reg);
14926     }
14927   else
14928     {
14929       /* Output the imm8 directly.  */
14930       scratchbuf[0] = '$';
14931       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
14932       oappend (scratchbuf + intel_syntax);
14933       scratchbuf[0] = '\0';
14934       codep++;
14935     }
14936 }
14937
14938 static void
14939 OP_Vex_2src (int bytemode, int sizeflag)
14940 {
14941   if (modrm.mod == 3)
14942     {
14943       int reg = modrm.rm;
14944       USED_REX (REX_B);
14945       if (rex & REX_B)
14946         reg += 8;
14947       oappend (names_xmm[reg]);
14948     }
14949   else
14950     {
14951       if (intel_syntax
14952           && (bytemode == v_mode || bytemode == v_swap_mode))
14953         {
14954           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
14955           used_prefixes |= (prefixes & PREFIX_DATA);
14956         }
14957       OP_E (bytemode, sizeflag);
14958     }
14959 }
14960
14961 static void
14962 OP_Vex_2src_1 (int bytemode, int sizeflag)
14963 {
14964   if (modrm.mod == 3)
14965     {
14966       /* Skip mod/rm byte.   */
14967       MODRM_CHECK;
14968       codep++;
14969     }
14970
14971   if (vex.w)
14972     oappend (names_xmm[vex.register_specifier]);
14973   else
14974     OP_Vex_2src (bytemode, sizeflag);
14975 }
14976
14977 static void
14978 OP_Vex_2src_2 (int bytemode, int sizeflag)
14979 {
14980   if (vex.w)
14981     OP_Vex_2src (bytemode, sizeflag);
14982   else
14983     oappend (names_xmm[vex.register_specifier]);
14984 }
14985
14986 static void
14987 OP_EX_VexW (int bytemode, int sizeflag)
14988 {
14989   int reg = -1;
14990
14991   if (!vex_w_done)
14992     {
14993       vex_w_done = 1;
14994
14995       /* Skip mod/rm byte.  */
14996       MODRM_CHECK;
14997       codep++;
14998
14999       if (vex.w)
15000         reg = get_vex_imm8 (sizeflag, 0) >> 4;
15001     }
15002   else
15003     {
15004       if (!vex.w)
15005         reg = get_vex_imm8 (sizeflag, 1) >> 4;
15006     }
15007
15008   OP_EX_VexReg (bytemode, sizeflag, reg);
15009 }
15010
15011 static void
15012 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
15013              int sizeflag ATTRIBUTE_UNUSED)
15014 {
15015   /* Skip the immediate byte and check for invalid bits.  */
15016   FETCH_DATA (the_info, codep + 1);
15017   if (*codep++ & 0xf)
15018     BadOp ();
15019 }
15020
15021 static void
15022 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15023 {
15024   int reg;
15025   const char **names;
15026
15027   FETCH_DATA (the_info, codep + 1);
15028   reg = *codep++;
15029
15030   if (bytemode != x_mode)
15031     abort ();
15032
15033   if (reg & 0xf)
15034       BadOp ();
15035
15036   reg >>= 4;
15037   if (reg > 7 && address_mode != mode_64bit)
15038     BadOp ();
15039
15040   switch (vex.length)
15041     {
15042     case 128:
15043       names = names_xmm;
15044       break;
15045     case 256:
15046       names = names_ymm;
15047       break;
15048     default:
15049       abort ();
15050     }
15051   oappend (names[reg]);
15052 }
15053
15054 static void
15055 OP_XMM_VexW (int bytemode, int sizeflag)
15056 {
15057   /* Turn off the REX.W bit since it is used for swapping operands
15058      now.  */
15059   rex &= ~REX_W;
15060   OP_XMM (bytemode, sizeflag);
15061 }
15062
15063 static void
15064 OP_EX_Vex (int bytemode, int sizeflag)
15065 {
15066   if (modrm.mod != 3)
15067     {
15068       if (vex.register_specifier != 0)
15069         BadOp ();
15070       need_vex_reg = 0;
15071     }
15072   OP_EX (bytemode, sizeflag);
15073 }
15074
15075 static void
15076 OP_XMM_Vex (int bytemode, int sizeflag)
15077 {
15078   if (modrm.mod != 3)
15079     {
15080       if (vex.register_specifier != 0)
15081         BadOp ();
15082       need_vex_reg = 0;
15083     }
15084   OP_XMM (bytemode, sizeflag);
15085 }
15086
15087 static void
15088 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15089 {
15090   switch (vex.length)
15091     {
15092     case 128:
15093       mnemonicendp = stpcpy (obuf, "vzeroupper");
15094       break;
15095     case 256:
15096       mnemonicendp = stpcpy (obuf, "vzeroall");
15097       break;
15098     default:
15099       abort ();
15100     }
15101 }
15102
15103 static struct op vex_cmp_op[] =
15104 {
15105   { STRING_COMMA_LEN ("eq") },
15106   { STRING_COMMA_LEN ("lt") },
15107   { STRING_COMMA_LEN ("le") },
15108   { STRING_COMMA_LEN ("unord") },
15109   { STRING_COMMA_LEN ("neq") },
15110   { STRING_COMMA_LEN ("nlt") },
15111   { STRING_COMMA_LEN ("nle") },
15112   { STRING_COMMA_LEN ("ord") },
15113   { STRING_COMMA_LEN ("eq_uq") },
15114   { STRING_COMMA_LEN ("nge") },
15115   { STRING_COMMA_LEN ("ngt") },
15116   { STRING_COMMA_LEN ("false") },
15117   { STRING_COMMA_LEN ("neq_oq") },
15118   { STRING_COMMA_LEN ("ge") },
15119   { STRING_COMMA_LEN ("gt") },
15120   { STRING_COMMA_LEN ("true") },
15121   { STRING_COMMA_LEN ("eq_os") },
15122   { STRING_COMMA_LEN ("lt_oq") },
15123   { STRING_COMMA_LEN ("le_oq") },
15124   { STRING_COMMA_LEN ("unord_s") },
15125   { STRING_COMMA_LEN ("neq_us") },
15126   { STRING_COMMA_LEN ("nlt_uq") },
15127   { STRING_COMMA_LEN ("nle_uq") },
15128   { STRING_COMMA_LEN ("ord_s") },
15129   { STRING_COMMA_LEN ("eq_us") },
15130   { STRING_COMMA_LEN ("nge_uq") },
15131   { STRING_COMMA_LEN ("ngt_uq") },
15132   { STRING_COMMA_LEN ("false_os") },
15133   { STRING_COMMA_LEN ("neq_os") },
15134   { STRING_COMMA_LEN ("ge_oq") },
15135   { STRING_COMMA_LEN ("gt_oq") },
15136   { STRING_COMMA_LEN ("true_us") },
15137 };
15138
15139 static void
15140 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15141 {
15142   unsigned int cmp_type;
15143
15144   FETCH_DATA (the_info, codep + 1);
15145   cmp_type = *codep++ & 0xff;
15146   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
15147     {
15148       char suffix [3];
15149       char *p = mnemonicendp - 2;
15150       suffix[0] = p[0];
15151       suffix[1] = p[1];
15152       suffix[2] = '\0';
15153       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
15154       mnemonicendp += vex_cmp_op[cmp_type].len;
15155     }
15156   else
15157     {
15158       /* We have a reserved extension byte.  Output it directly.  */
15159       scratchbuf[0] = '$';
15160       print_operand_value (scratchbuf + 1, 1, cmp_type);
15161       oappend (scratchbuf + intel_syntax);
15162       scratchbuf[0] = '\0';
15163     }
15164 }
15165
15166 static const struct op pclmul_op[] =
15167 {
15168   { STRING_COMMA_LEN ("lql") },
15169   { STRING_COMMA_LEN ("hql") },
15170   { STRING_COMMA_LEN ("lqh") },
15171   { STRING_COMMA_LEN ("hqh") }
15172 };
15173
15174 static void
15175 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
15176               int sizeflag ATTRIBUTE_UNUSED)
15177 {
15178   unsigned int pclmul_type;
15179
15180   FETCH_DATA (the_info, codep + 1);
15181   pclmul_type = *codep++ & 0xff;
15182   switch (pclmul_type)
15183     {
15184     case 0x10:
15185       pclmul_type = 2;
15186       break;
15187     case 0x11:
15188       pclmul_type = 3;
15189       break;
15190     default:
15191       break;
15192     }
15193   if (pclmul_type < ARRAY_SIZE (pclmul_op))
15194     {
15195       char suffix [4];
15196       char *p = mnemonicendp - 3;
15197       suffix[0] = p[0];
15198       suffix[1] = p[1];
15199       suffix[2] = p[2];
15200       suffix[3] = '\0';
15201       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
15202       mnemonicendp += pclmul_op[pclmul_type].len;
15203     }
15204   else
15205     {
15206       /* We have a reserved extension byte.  Output it directly.  */
15207       scratchbuf[0] = '$';
15208       print_operand_value (scratchbuf + 1, 1, pclmul_type);
15209       oappend (scratchbuf + intel_syntax);
15210       scratchbuf[0] = '\0';
15211     }
15212 }
15213
15214 static void
15215 MOVBE_Fixup (int bytemode, int sizeflag)
15216 {
15217   /* Add proper suffix to "movbe".  */
15218   char *p = mnemonicendp;
15219
15220   switch (bytemode)
15221     {
15222     case v_mode:
15223       if (intel_syntax)
15224         goto skip;
15225
15226       USED_REX (REX_W);
15227       if (sizeflag & SUFFIX_ALWAYS)
15228         {
15229           if (rex & REX_W)
15230             *p++ = 'q';
15231           else
15232             {
15233               if (sizeflag & DFLAG)
15234                 *p++ = 'l';
15235               else
15236                 *p++ = 'w';
15237               used_prefixes |= (prefixes & PREFIX_DATA);
15238             }
15239         }
15240       break;
15241     default:
15242       oappend (INTERNAL_DISASSEMBLER_ERROR);
15243       break;
15244     }
15245   mnemonicendp = p;
15246   *p = '\0';
15247
15248 skip:
15249   OP_M (bytemode, sizeflag);
15250 }
15251
15252 static void
15253 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15254 {
15255   int reg;
15256   const char **names;
15257
15258   /* Skip mod/rm byte.  */
15259   MODRM_CHECK;
15260   codep++;
15261
15262   if (vex.w)
15263     names = names64;
15264   else
15265     names = names32;
15266
15267   reg = modrm.rm;
15268   USED_REX (REX_B);
15269   if (rex & REX_B)
15270     reg += 8;
15271
15272   oappend (names[reg]);
15273 }
15274
15275 static void
15276 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15277 {
15278   const char **names;
15279
15280   if (vex.w)
15281     names = names64;
15282   else
15283     names = names32;
15284
15285   oappend (names[vex.register_specifier]);
15286 }