opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2022 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "disassemble.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40 #include "safe-ctype.h"
  41
  42 #include <setjmp.h>
  43 typedef struct instr_info instr_info;
  44
  45 static void dofloat (instr_info *, int);
  46 static void OP_ST (instr_info *, int, int);
  47 static void OP_STi (instr_info *, int, int);
  48 static int putop (instr_info *, const char *, int);
  49 static void oappend_with_style (instr_info *, const char *,
  50                                 enum disassembler_style);
  51 static void oappend (instr_info *, const char *);
  52 static void append_seg (instr_info *);
  53 static void OP_indirE (instr_info *, int, int);
  54 static void OP_E_memory (instr_info *, int, int);
  55 static void OP_E (instr_info *, int, int);
  56 static void OP_G (instr_info *, int, int);
  57 static bfd_vma get64 (instr_info *);
  58 static bfd_signed_vma get32 (instr_info *);
  59 static bfd_signed_vma get32s (instr_info *);
  60 static int get16 (instr_info *);
  61 static void set_op (instr_info *, bfd_vma, bool);
  62 static void OP_Skip_MODRM (instr_info *, int, int);
  63 static void OP_REG (instr_info *, int, int);
  64 static void OP_IMREG (instr_info *, int, int);
  65 static void OP_I (instr_info *, int, int);
  66 static void OP_I64 (instr_info *, int, int);
  67 static void OP_sI (instr_info *, int, int);
  68 static void OP_J (instr_info *, int, int);
  69 static void OP_SEG (instr_info *, int, int);
  70 static void OP_DIR (instr_info *, int, int);
  71 static void OP_OFF (instr_info *, int, int);
  72 static void OP_OFF64 (instr_info *, int, int);
  73 static void ptr_reg (instr_info *, int, int);
  74 static void OP_ESreg (instr_info *, int, int);
  75 static void OP_DSreg (instr_info *, int, int);
  76 static void OP_C (instr_info *, int, int);
  77 static void OP_D (instr_info *, int, int);
  78 static void OP_T (instr_info *, int, int);
  79 static void OP_MMX (instr_info *, int, int);
  80 static void OP_XMM (instr_info *, int, int);
  81 static void OP_EM (instr_info *, int, int);
  82 static void OP_EX (instr_info *, int, int);
  83 static void OP_EMC (instr_info *, int,int);
  84 static void OP_MXC (instr_info *, int,int);
  85 static void OP_MS (instr_info *, int, int);
  86 static void OP_XS (instr_info *, int, int);
  87 static void OP_M (instr_info *, int, int);
  88 static void OP_VEX (instr_info *, int, int);
  89 static void OP_VexR (instr_info *, int, int);
  90 static void OP_VexW (instr_info *, int, int);
  91 static void OP_Rounding (instr_info *, int, int);
  92 static void OP_REG_VexI4 (instr_info *, int, int);
  93 static void OP_VexI4 (instr_info *, int, int);
  94 static void PCLMUL_Fixup (instr_info *, int, int);
  95 static void VPCMP_Fixup (instr_info *, int, int);
  96 static void VPCOM_Fixup (instr_info *, int, int);
  97 static void OP_0f07 (instr_info *, int, int);
  98 static void OP_Monitor (instr_info *, int, int);
  99 static void OP_Mwait (instr_info *, int, int);
 100 static void NOP_Fixup (instr_info *, int, int);
 101 static void OP_3DNowSuffix (instr_info *, int, int);
 102 static void CMP_Fixup (instr_info *, int, int);
 103 static void BadOp (instr_info *);
 104 static void REP_Fixup (instr_info *, int, int);
 105 static void SEP_Fixup (instr_info *, int, int);
 106 static void BND_Fixup (instr_info *, int, int);
 107 static void NOTRACK_Fixup (instr_info *, int, int);
 108 static void HLE_Fixup1 (instr_info *, int, int);
 109 static void HLE_Fixup2 (instr_info *, int, int);
 110 static void HLE_Fixup3 (instr_info *, int, int);
 111 static void CMPXCHG8B_Fixup (instr_info *, int, int);
 112 static void XMM_Fixup (instr_info *, int, int);
 113 static void FXSAVE_Fixup (instr_info *, int, int);
 114
 115 static void MOVSXD_Fixup (instr_info *, int, int);
 116 static void DistinctDest_Fixup (instr_info *, int, int);
 117 static void PREFETCHI_Fixup (instr_info *, int, int);
 118
 119 /* This character is used to encode style information within the output
 120    buffers.  See oappend_insert_style for more details.  */
 121 #define STYLE_MARKER_CHAR '\002'
 122
 123 /* The maximum operand buffer size.  */
 124 #define MAX_OPERAND_BUFFER_SIZE 128
 125
 126 struct dis_private {
 127   /* Points to first byte not fetched.  */
 128   bfd_byte *max_fetched;
 129   bfd_byte the_buffer[MAX_MNEM_SIZE];
 130   bfd_vma insn_start;
 131   int orig_sizeflag;
 132   OPCODES_SIGJMP_BUF bailout;
 133 };
 134
 135 enum address_mode
 136 {
 137   mode_16bit,
 138   mode_32bit,
 139   mode_64bit
 140 };
 141
 142 enum x86_64_isa
 143 {
 144   amd64 = 1,
 145   intel64
 146 };
 147
 148 struct instr_info
 149 {
 150   enum address_mode address_mode;
 151
 152   /* Flags for the prefixes for the current instruction.  See below.  */
 153   int prefixes;
 154
 155   /* REX prefix the current instruction.  See below.  */
 156   unsigned char rex;
 157   /* Bits of REX we've already used.  */
 158   unsigned char rex_used;
 159
 160   bool need_modrm;
 161   bool need_vex;
 162   bool has_sib;
 163
 164   /* Flags for ins->prefixes which we somehow handled when printing the
 165      current instruction.  */
 166   int used_prefixes;
 167
 168   /* Flags for EVEX bits which we somehow handled when printing the
 169      current instruction.  */
 170   int evex_used;
 171
 172   char obuf[MAX_OPERAND_BUFFER_SIZE];
 173   char *obufp;
 174   char *mnemonicendp;
 175   unsigned char *start_codep;
 176   unsigned char *insn_codep;
 177   unsigned char *codep;
 178   unsigned char *end_codep;
 179   signed char last_lock_prefix;
 180   signed char last_repz_prefix;
 181   signed char last_repnz_prefix;
 182   signed char last_data_prefix;
 183   signed char last_addr_prefix;
 184   signed char last_rex_prefix;
 185   signed char last_seg_prefix;
 186   signed char fwait_prefix;
 187   /* The active segment register prefix.  */
 188   unsigned char active_seg_prefix;
 189
 190 #define MAX_CODE_LENGTH 15
 191   /* We can up to 14 ins->prefixes since the maximum instruction length is
 192      15bytes.  */
 193   unsigned char all_prefixes[MAX_CODE_LENGTH - 1];
 194   disassemble_info *info;
 195
 196   struct
 197   {
 198     int mod;
 199     int reg;
 200     int rm;
 201   }
 202   modrm;
 203
 204   struct
 205   {
 206     int scale;
 207     int index;
 208     int base;
 209   }
 210   sib;
 211
 212   struct
 213   {
 214     int register_specifier;
 215     int length;
 216     int prefix;
 217     int mask_register_specifier;
 218     int ll;
 219     bool w;
 220     bool evex;
 221     bool r;
 222     bool v;
 223     bool zeroing;
 224     bool b;
 225     bool no_broadcast;
 226   }
 227   vex;
 228
 229   /* Remember if the current op is a jump instruction.  */
 230   bool op_is_jump;
 231
 232   bool two_source_ops;
 233
 234   unsigned char op_ad;
 235   signed char op_index[MAX_OPERANDS];
 236   bool op_riprel[MAX_OPERANDS];
 237   char *op_out[MAX_OPERANDS];
 238   bfd_vma op_address[MAX_OPERANDS];
 239   bfd_vma start_pc;
 240
 241   /* On the 386's of 1988, the maximum length of an instruction is 15 bytes.
 242    *   (see topic "Redundant ins->prefixes" in the "Differences from 8086"
 243    *   section of the "Virtual 8086 Mode" chapter.)
 244    * 'pc' should be the address of this instruction, it will
 245    *   be used to print the target address if this is a relative jump or call
 246    * The function returns the length of this instruction in bytes.
 247    */
 248   char intel_syntax;
 249   bool intel_mnemonic;
 250   char open_char;
 251   char close_char;
 252   char separator_char;
 253   char scale_char;
 254
 255   enum x86_64_isa isa64;
 256 };
 257
 258 /* Mark parts used in the REX prefix.  When we are testing for
 259    empty prefix (for 8bit register REX extension), just mask it
 260    out.  Otherwise test for REX bit is excuse for existence of REX
 261    only in case value is nonzero.  */
 262 #define USED_REX(value)                                 \
 263   {                                                     \
 264     if (value)                                          \
 265       {                                                 \
 266         if ((ins->rex & value))                         \
 267           ins->rex_used |= (value) | REX_OPCODE;        \
 268       }                                                 \
 269     else                                                \
 270       ins->rex_used |= REX_OPCODE;                      \
 271   }
 272
 273
 274 #define EVEX_b_used 1
 275 #define EVEX_len_used 2
 276
 277 /* Flags stored in PREFIXES.  */
 278 #define PREFIX_REPZ 1
 279 #define PREFIX_REPNZ 2
 280 #define PREFIX_CS 4
 281 #define PREFIX_SS 8
 282 #define PREFIX_DS 0x10
 283 #define PREFIX_ES 0x20
 284 #define PREFIX_FS 0x40
 285 #define PREFIX_GS 0x80
 286 #define PREFIX_LOCK 0x100
 287 #define PREFIX_DATA 0x200
 288 #define PREFIX_ADDR 0x400
 289 #define PREFIX_FWAIT 0x800
 290
 291 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 292    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 293    on error.  */
 294 #define FETCH_DATA(info, addr) \
 295   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 296    ? 1 : fetch_data ((info), (addr)))
 297
 298 static int
 299 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 300 {
 301   int status;
 302   struct dis_private *priv = (struct dis_private *) info->private_data;
 303   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 304
 305   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 306     status = (*info->read_memory_func) (start,
 307                                         priv->max_fetched,
 308                                         addr - priv->max_fetched,
 309                                         info);
 310   else
 311     status = -1;
 312   if (status != 0)
 313     {
 314       /* If we did manage to read at least one byte, then
 315          print_insn_i386 will do something sensible.  Otherwise, print
 316          an error.  We do that here because this is where we know
 317          STATUS.  */
 318       if (priv->max_fetched == priv->the_buffer)
 319         (*info->memory_error_func) (status, start, info);
 320       OPCODES_SIGLONGJMP (priv->bailout, 1);
 321     }
 322   else
 323     priv->max_fetched = addr;
 324   return 1;
 325 }
 326
 327 /* Possible values for prefix requirement.  */
 328 #define PREFIX_IGNORED_SHIFT    16
 329 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 330 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 331 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 332 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 333 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 334
 335 /* Opcode prefixes.  */
 336 #define PREFIX_OPCODE           (PREFIX_REPZ \
 337                                  | PREFIX_REPNZ \
 338                                  | PREFIX_DATA)
 339
 340 /* Prefixes ignored.  */
 341 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 342                                  | PREFIX_IGNORED_REPNZ \
 343                                  | PREFIX_IGNORED_DATA)
 344
 345 #define XX { NULL, 0 }
 346 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 347
 348 #define Eb { OP_E, b_mode }
 349 #define Ebnd { OP_E, bnd_mode }
 350 #define EbS { OP_E, b_swap_mode }
 351 #define EbndS { OP_E, bnd_swap_mode }
 352 #define Ev { OP_E, v_mode }
 353 #define Eva { OP_E, va_mode }
 354 #define Ev_bnd { OP_E, v_bnd_mode }
 355 #define EvS { OP_E, v_swap_mode }
 356 #define Ed { OP_E, d_mode }
 357 #define Edq { OP_E, dq_mode }
 358 #define Edb { OP_E, db_mode }
 359 #define Edw { OP_E, dw_mode }
 360 #define Eq { OP_E, q_mode }
 361 #define indirEv { OP_indirE, indir_v_mode }
 362 #define indirEp { OP_indirE, f_mode }
 363 #define stackEv { OP_E, stack_v_mode }
 364 #define Em { OP_E, m_mode }
 365 #define Ew { OP_E, w_mode }
 366 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 367 #define Ma { OP_M, a_mode }
 368 #define Mb { OP_M, b_mode }
 369 #define Md { OP_M, d_mode }
 370 #define Mdq { OP_M, dq_mode }
 371 #define Mo { OP_M, o_mode }
 372 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 373 #define Mq { OP_M, q_mode }
 374 #define Mv { OP_M, v_mode }
 375 #define Mv_bnd { OP_M, v_bndmk_mode }
 376 #define Mw { OP_M, w_mode }
 377 #define Mx { OP_M, x_mode }
 378 #define Mxmm { OP_M, xmm_mode }
 379 #define Gb { OP_G, b_mode }
 380 #define Gbnd { OP_G, bnd_mode }
 381 #define Gv { OP_G, v_mode }
 382 #define Gd { OP_G, d_mode }
 383 #define Gdq { OP_G, dq_mode }
 384 #define Gm { OP_G, m_mode }
 385 #define Gva { OP_G, va_mode }
 386 #define Gw { OP_G, w_mode }
 387 #define Ib { OP_I, b_mode }
 388 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 389 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 390 #define Iv { OP_I, v_mode }
 391 #define sIv { OP_sI, v_mode }
 392 #define Iv64 { OP_I64, v_mode }
 393 #define Id { OP_I, d_mode }
 394 #define Iw { OP_I, w_mode }
 395 #define I1 { OP_I, const_1_mode }
 396 #define Jb { OP_J, b_mode }
 397 #define Jv { OP_J, v_mode }
 398 #define Jdqw { OP_J, dqw_mode }
 399 #define Cm { OP_C, m_mode }
 400 #define Dm { OP_D, m_mode }
 401 #define Td { OP_T, d_mode }
 402 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 403
 404 #define RMeAX { OP_REG, eAX_reg }
 405 #define RMeBX { OP_REG, eBX_reg }
 406 #define RMeCX { OP_REG, eCX_reg }
 407 #define RMeDX { OP_REG, eDX_reg }
 408 #define RMeSP { OP_REG, eSP_reg }
 409 #define RMeBP { OP_REG, eBP_reg }
 410 #define RMeSI { OP_REG, eSI_reg }
 411 #define RMeDI { OP_REG, eDI_reg }
 412 #define RMrAX { OP_REG, rAX_reg }
 413 #define RMrBX { OP_REG, rBX_reg }
 414 #define RMrCX { OP_REG, rCX_reg }
 415 #define RMrDX { OP_REG, rDX_reg }
 416 #define RMrSP { OP_REG, rSP_reg }
 417 #define RMrBP { OP_REG, rBP_reg }
 418 #define RMrSI { OP_REG, rSI_reg }
 419 #define RMrDI { OP_REG, rDI_reg }
 420 #define RMAL { OP_REG, al_reg }
 421 #define RMCL { OP_REG, cl_reg }
 422 #define RMDL { OP_REG, dl_reg }
 423 #define RMBL { OP_REG, bl_reg }
 424 #define RMAH { OP_REG, ah_reg }
 425 #define RMCH { OP_REG, ch_reg }
 426 #define RMDH { OP_REG, dh_reg }
 427 #define RMBH { OP_REG, bh_reg }
 428 #define RMAX { OP_REG, ax_reg }
 429 #define RMDX { OP_REG, dx_reg }
 430
 431 #define eAX { OP_IMREG, eAX_reg }
 432 #define AL { OP_IMREG, al_reg }
 433 #define CL { OP_IMREG, cl_reg }
 434 #define zAX { OP_IMREG, z_mode_ax_reg }
 435 #define indirDX { OP_IMREG, indir_dx_reg }
 436
 437 #define Sw { OP_SEG, w_mode }
 438 #define Sv { OP_SEG, v_mode }
 439 #define Ap { OP_DIR, 0 }
 440 #define Ob { OP_OFF64, b_mode }
 441 #define Ov { OP_OFF64, v_mode }
 442 #define Xb { OP_DSreg, eSI_reg }
 443 #define Xv { OP_DSreg, eSI_reg }
 444 #define Xz { OP_DSreg, eSI_reg }
 445 #define Yb { OP_ESreg, eDI_reg }
 446 #define Yv { OP_ESreg, eDI_reg }
 447 #define DSBX { OP_DSreg, eBX_reg }
 448
 449 #define es { OP_REG, es_reg }
 450 #define ss { OP_REG, ss_reg }
 451 #define cs { OP_REG, cs_reg }
 452 #define ds { OP_REG, ds_reg }
 453 #define fs { OP_REG, fs_reg }
 454 #define gs { OP_REG, gs_reg }
 455
 456 #define MX { OP_MMX, 0 }
 457 #define XM { OP_XMM, 0 }
 458 #define XMScalar { OP_XMM, scalar_mode }
 459 #define XMGatherD { OP_XMM, vex_vsib_d_w_dq_mode }
 460 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 461 #define XMM { OP_XMM, xmm_mode }
 462 #define TMM { OP_XMM, tmm_mode }
 463 #define XMxmmq { OP_XMM, xmmq_mode }
 464 #define EM { OP_EM, v_mode }
 465 #define EMS { OP_EM, v_swap_mode }
 466 #define EMd { OP_EM, d_mode }
 467 #define EMx { OP_EM, x_mode }
 468 #define EXbwUnit { OP_EX, bw_unit_mode }
 469 #define EXb { OP_EX, b_mode }
 470 #define EXw { OP_EX, w_mode }
 471 #define EXd { OP_EX, d_mode }
 472 #define EXdS { OP_EX, d_swap_mode }
 473 #define EXwS { OP_EX, w_swap_mode }
 474 #define EXq { OP_EX, q_mode }
 475 #define EXqS { OP_EX, q_swap_mode }
 476 #define EXdq { OP_EX, dq_mode }
 477 #define EXx { OP_EX, x_mode }
 478 #define EXxh { OP_EX, xh_mode }
 479 #define EXxS { OP_EX, x_swap_mode }
 480 #define EXxmm { OP_EX, xmm_mode }
 481 #define EXymm { OP_EX, ymm_mode }
 482 #define EXtmm { OP_EX, tmm_mode }
 483 #define EXxmmq { OP_EX, xmmq_mode }
 484 #define EXxmmqh { OP_EX, evex_half_bcst_xmmqh_mode }
 485 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 486 #define EXxmmdw { OP_EX, xmmdw_mode }
 487 #define EXxmmqd { OP_EX, xmmqd_mode }
 488 #define EXxmmqdh { OP_EX, evex_half_bcst_xmmqdh_mode }
 489 #define EXymmq { OP_EX, ymmq_mode }
 490 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 491 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 492 #define MS { OP_MS, v_mode }
 493 #define XS { OP_XS, v_mode }
 494 #define EMCq { OP_EMC, q_mode }
 495 #define MXC { OP_MXC, 0 }
 496 #define OPSUF { OP_3DNowSuffix, 0 }
 497 #define SEP { SEP_Fixup, 0 }
 498 #define CMP { CMP_Fixup, 0 }
 499 #define XMM0 { XMM_Fixup, 0 }
 500 #define FXSAVE { FXSAVE_Fixup, 0 }
 501
 502 #define Vex { OP_VEX, x_mode }
 503 #define VexW { OP_VexW, x_mode }
 504 #define VexScalar { OP_VEX, scalar_mode }
 505 #define VexScalarR { OP_VexR, scalar_mode }
 506 #define VexGatherD { OP_VEX, vex_vsib_d_w_dq_mode }
 507 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 508 #define VexGdq { OP_VEX, dq_mode }
 509 #define VexTmm { OP_VEX, tmm_mode }
 510 #define XMVexI4 { OP_REG_VexI4, x_mode }
 511 #define XMVexScalarI4 { OP_REG_VexI4, scalar_mode }
 512 #define VexI4 { OP_VexI4, 0 }
 513 #define PCLMUL { PCLMUL_Fixup, 0 }
 514 #define VPCMP { VPCMP_Fixup, 0 }
 515 #define VPCOM { VPCOM_Fixup, 0 }
 516
 517 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 518 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
 519 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 520
 521 #define MaskG { OP_G, mask_mode }
 522 #define MaskE { OP_E, mask_mode }
 523 #define MaskBDE { OP_E, mask_bd_mode }
 524 #define MaskVex { OP_VEX, mask_mode }
 525
 526 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 527 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 528
 529 #define MVexSIBMEM { OP_M, vex_sibmem_mode }
 530
 531 /* Used handle "rep" prefix for string instructions.  */
 532 #define Xbr { REP_Fixup, eSI_reg }
 533 #define Xvr { REP_Fixup, eSI_reg }
 534 #define Ybr { REP_Fixup, eDI_reg }
 535 #define Yvr { REP_Fixup, eDI_reg }
 536 #define Yzr { REP_Fixup, eDI_reg }
 537 #define indirDXr { REP_Fixup, indir_dx_reg }
 538 #define ALr { REP_Fixup, al_reg }
 539 #define eAXr { REP_Fixup, eAX_reg }
 540
 541 /* Used handle HLE prefix for lockable instructions.  */
 542 #define Ebh1 { HLE_Fixup1, b_mode }
 543 #define Evh1 { HLE_Fixup1, v_mode }
 544 #define Ebh2 { HLE_Fixup2, b_mode }
 545 #define Evh2 { HLE_Fixup2, v_mode }
 546 #define Ebh3 { HLE_Fixup3, b_mode }
 547 #define Evh3 { HLE_Fixup3, v_mode }
 548
 549 #define BND { BND_Fixup, 0 }
 550 #define NOTRACK { NOTRACK_Fixup, 0 }
 551
 552 #define cond_jump_flag { NULL, cond_jump_mode }
 553 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 554
 555 /* bits in sizeflag */
 556 #define SUFFIX_ALWAYS 4
 557 #define AFLAG 2
 558 #define DFLAG 1
 559
 560 enum
 561 {
 562   /* byte operand */
 563   b_mode = 1,
 564   /* byte operand with operand swapped */
 565   b_swap_mode,
 566   /* byte operand, sign extend like 'T' suffix */
 567   b_T_mode,
 568   /* operand size depends on prefixes */
 569   v_mode,
 570   /* operand size depends on prefixes with operand swapped */
 571   v_swap_mode,
 572   /* operand size depends on address prefix */
 573   va_mode,
 574   /* word operand */
 575   w_mode,
 576   /* double word operand  */
 577   d_mode,
 578   /* word operand with operand swapped  */
 579   w_swap_mode,
 580   /* double word operand with operand swapped */
 581   d_swap_mode,
 582   /* quad word operand */
 583   q_mode,
 584   /* quad word operand with operand swapped */
 585   q_swap_mode,
 586   /* ten-byte operand */
 587   t_mode,
 588   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 589      broadcast enabled.  */
 590   x_mode,
 591   /* Similar to x_mode, but with different EVEX mem shifts.  */
 592   evex_x_gscat_mode,
 593   /* Similar to x_mode, but with yet different EVEX mem shifts.  */
 594   bw_unit_mode,
 595   /* Similar to x_mode, but with disabled broadcast.  */
 596   evex_x_nobcst_mode,
 597   /* Similar to x_mode, but with operands swapped and disabled broadcast
 598      in EVEX.  */
 599   x_swap_mode,
 600   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 601      broadcast of 16bit enabled.  */
 602   xh_mode,
 603   /* 16-byte XMM operand */
 604   xmm_mode,
 605   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 606      memory operand (depending on vector length).  Broadcast isn't
 607      allowed.  */
 608   xmmq_mode,
 609   /* Same as xmmq_mode, but broadcast is allowed.  */
 610   evex_half_bcst_xmmq_mode,
 611   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 612      memory operand (depending on vector length).  16bit broadcast.  */
 613   evex_half_bcst_xmmqh_mode,
 614   /* 16-byte XMM, word, double word or quad word operand.  */
 615   xmmdw_mode,
 616   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 617   xmmqd_mode,
 618   /* 16-byte XMM, double word, quad word operand or xmm word operand.
 619      16bit broadcast.  */
 620   evex_half_bcst_xmmqdh_mode,
 621   /* 32-byte YMM operand */
 622   ymm_mode,
 623   /* quad word, ymmword or zmmword memory operand.  */
 624   ymmq_mode,
 625   /* TMM operand */
 626   tmm_mode,
 627   /* d_mode in 32bit, q_mode in 64bit mode.  */
 628   m_mode,
 629   /* pair of v_mode operands */
 630   a_mode,
 631   cond_jump_mode,
 632   loop_jcxz_mode,
 633   movsxd_mode,
 634   v_bnd_mode,
 635   /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode.  */
 636   v_bndmk_mode,
 637   /* operand size depends on REX.W / VEX.W.  */
 638   dq_mode,
 639   /* Displacements like v_mode without considering Intel64 ISA.  */
 640   dqw_mode,
 641   /* bounds operand */
 642   bnd_mode,
 643   /* bounds operand with operand swapped */
 644   bnd_swap_mode,
 645   /* 4- or 6-byte pointer operand */
 646   f_mode,
 647   const_1_mode,
 648   /* v_mode for indirect branch opcodes.  */
 649   indir_v_mode,
 650   /* v_mode for stack-related opcodes.  */
 651   stack_v_mode,
 652   /* non-quad operand size depends on prefixes */
 653   z_mode,
 654   /* 16-byte operand */
 655   o_mode,
 656   /* registers like d_mode, memory like b_mode.  */
 657   db_mode,
 658   /* registers like d_mode, memory like w_mode.  */
 659   dw_mode,
 660
 661   /* Operand size depends on the VEX.W bit, with VSIB dword indices.  */
 662   vex_vsib_d_w_dq_mode,
 663   /* Operand size depends on the VEX.W bit, with VSIB qword indices.  */
 664   vex_vsib_q_w_dq_mode,
 665   /* mandatory non-vector SIB.  */
 666   vex_sibmem_mode,
 667
 668   /* scalar, ignore vector length.  */
 669   scalar_mode,
 670
 671   /* Static rounding.  */
 672   evex_rounding_mode,
 673   /* Static rounding, 64-bit mode only.  */
 674   evex_rounding_64_mode,
 675   /* Supress all exceptions.  */
 676   evex_sae_mode,
 677
 678   /* Mask register operand.  */
 679   mask_mode,
 680   /* Mask register operand.  */
 681   mask_bd_mode,
 682
 683   es_reg,
 684   cs_reg,
 685   ss_reg,
 686   ds_reg,
 687   fs_reg,
 688   gs_reg,
 689
 690   eAX_reg,
 691   eCX_reg,
 692   eDX_reg,
 693   eBX_reg,
 694   eSP_reg,
 695   eBP_reg,
 696   eSI_reg,
 697   eDI_reg,
 698
 699   al_reg,
 700   cl_reg,
 701   dl_reg,
 702   bl_reg,
 703   ah_reg,
 704   ch_reg,
 705   dh_reg,
 706   bh_reg,
 707
 708   ax_reg,
 709   cx_reg,
 710   dx_reg,
 711   bx_reg,
 712   sp_reg,
 713   bp_reg,
 714   si_reg,
 715   di_reg,
 716
 717   rAX_reg,
 718   rCX_reg,
 719   rDX_reg,
 720   rBX_reg,
 721   rSP_reg,
 722   rBP_reg,
 723   rSI_reg,
 724   rDI_reg,
 725
 726   z_mode_ax_reg,
 727   indir_dx_reg
 728 };
 729
 730 enum
 731 {
 732   FLOATCODE = 1,
 733   USE_REG_TABLE,
 734   USE_MOD_TABLE,
 735   USE_RM_TABLE,
 736   USE_PREFIX_TABLE,
 737   USE_X86_64_TABLE,
 738   USE_3BYTE_TABLE,
 739   USE_XOP_8F_TABLE,
 740   USE_VEX_C4_TABLE,
 741   USE_VEX_C5_TABLE,
 742   USE_VEX_LEN_TABLE,
 743   USE_VEX_W_TABLE,
 744   USE_EVEX_TABLE,
 745   USE_EVEX_LEN_TABLE
 746 };
 747
 748 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 749
 750 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 751 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 752 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 753 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 754 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 755 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 756 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 757 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 758 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 759 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 760 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 761 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 762 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 763 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 764 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 765 #define EVEX_LEN_TABLE(I)       DIS386 (USE_EVEX_LEN_TABLE, (I))
 766
 767 enum
 768 {
 769   REG_80 = 0,
 770   REG_81,
 771   REG_83,
 772   REG_8F,
 773   REG_C0,
 774   REG_C1,
 775   REG_C6,
 776   REG_C7,
 777   REG_D0,
 778   REG_D1,
 779   REG_D2,
 780   REG_D3,
 781   REG_F6,
 782   REG_F7,
 783   REG_FE,
 784   REG_FF,
 785   REG_0F00,
 786   REG_0F01,
 787   REG_0F0D,
 788   REG_0F18,
 789   REG_0F1C_P_0_MOD_0,
 790   REG_0F1E_P_1_MOD_3,
 791   REG_0F38D8_PREFIX_1,
 792   REG_0F3A0F_PREFIX_1_MOD_3,
 793   REG_0F71_MOD_0,
 794   REG_0F72_MOD_0,
 795   REG_0F73_MOD_0,
 796   REG_0FA6,
 797   REG_0FA7,
 798   REG_0FAE,
 799   REG_0FBA,
 800   REG_0FC7,
 801   REG_VEX_0F71_M_0,
 802   REG_VEX_0F72_M_0,
 803   REG_VEX_0F73_M_0,
 804   REG_VEX_0FAE,
 805   REG_VEX_0F3849_X86_64_P_0_W_0_M_1,
 806   REG_VEX_0F38F3_L_0,
 807
 808   REG_XOP_09_01_L_0,
 809   REG_XOP_09_02_L_0,
 810   REG_XOP_09_12_M_1_L_0,
 811   REG_XOP_0A_12_L_0,
 812
 813   REG_EVEX_0F71,
 814   REG_EVEX_0F72,
 815   REG_EVEX_0F73,
 816   REG_EVEX_0F38C6_M_0_L_2,
 817   REG_EVEX_0F38C7_M_0_L_2
 818 };
 819
 820 enum
 821 {
 822   MOD_62_32BIT = 0,
 823   MOD_8D,
 824   MOD_C4_32BIT,
 825   MOD_C5_32BIT,
 826   MOD_C6_REG_7,
 827   MOD_C7_REG_7,
 828   MOD_FF_REG_3,
 829   MOD_FF_REG_5,
 830   MOD_0F01_REG_0,
 831   MOD_0F01_REG_1,
 832   MOD_0F01_REG_2,
 833   MOD_0F01_REG_3,
 834   MOD_0F01_REG_5,
 835   MOD_0F01_REG_7,
 836   MOD_0F12_PREFIX_0,
 837   MOD_0F12_PREFIX_2,
 838   MOD_0F13,
 839   MOD_0F16_PREFIX_0,
 840   MOD_0F16_PREFIX_2,
 841   MOD_0F17,
 842   MOD_0F18_REG_0,
 843   MOD_0F18_REG_1,
 844   MOD_0F18_REG_2,
 845   MOD_0F18_REG_3,
 846   MOD_0F18_REG_6,
 847   MOD_0F18_REG_7,
 848   MOD_0F1A_PREFIX_0,
 849   MOD_0F1B_PREFIX_0,
 850   MOD_0F1B_PREFIX_1,
 851   MOD_0F1C_PREFIX_0,
 852   MOD_0F1E_PREFIX_1,
 853   MOD_0F2B_PREFIX_0,
 854   MOD_0F2B_PREFIX_1,
 855   MOD_0F2B_PREFIX_2,
 856   MOD_0F2B_PREFIX_3,
 857   MOD_0F50,
 858   MOD_0F71,
 859   MOD_0F72,
 860   MOD_0F73,
 861   MOD_0FAE_REG_0,
 862   MOD_0FAE_REG_1,
 863   MOD_0FAE_REG_2,
 864   MOD_0FAE_REG_3,
 865   MOD_0FAE_REG_4,
 866   MOD_0FAE_REG_5,
 867   MOD_0FAE_REG_6,
 868   MOD_0FAE_REG_7,
 869   MOD_0FB2,
 870   MOD_0FB4,
 871   MOD_0FB5,
 872   MOD_0FC3,
 873   MOD_0FC7_REG_3,
 874   MOD_0FC7_REG_4,
 875   MOD_0FC7_REG_5,
 876   MOD_0FC7_REG_6,
 877   MOD_0FC7_REG_7,
 878   MOD_0FD7,
 879   MOD_0FE7_PREFIX_2,
 880   MOD_0FF0_PREFIX_3,
 881   MOD_0F382A,
 882   MOD_0F38DC_PREFIX_1,
 883   MOD_0F38DD_PREFIX_1,
 884   MOD_0F38DE_PREFIX_1,
 885   MOD_0F38DF_PREFIX_1,
 886   MOD_0F38F5,
 887   MOD_0F38F6_PREFIX_0,
 888   MOD_0F38F8_PREFIX_1,
 889   MOD_0F38F8_PREFIX_2,
 890   MOD_0F38F8_PREFIX_3,
 891   MOD_0F38F9,
 892   MOD_0F38FA_PREFIX_1,
 893   MOD_0F38FB_PREFIX_1,
 894   MOD_0F3A0F_PREFIX_1,
 895
 896   MOD_VEX_0F12_PREFIX_0,
 897   MOD_VEX_0F12_PREFIX_2,
 898   MOD_VEX_0F13,
 899   MOD_VEX_0F16_PREFIX_0,
 900   MOD_VEX_0F16_PREFIX_2,
 901   MOD_VEX_0F17,
 902   MOD_VEX_0F2B,
 903   MOD_VEX_0F41_L_1,
 904   MOD_VEX_0F42_L_1,
 905   MOD_VEX_0F44_L_0,
 906   MOD_VEX_0F45_L_1,
 907   MOD_VEX_0F46_L_1,
 908   MOD_VEX_0F47_L_1,
 909   MOD_VEX_0F4A_L_1,
 910   MOD_VEX_0F4B_L_1,
 911   MOD_VEX_0F50,
 912   MOD_VEX_0F71,
 913   MOD_VEX_0F72,
 914   MOD_VEX_0F73,
 915   MOD_VEX_0F91_L_0,
 916   MOD_VEX_0F92_L_0,
 917   MOD_VEX_0F93_L_0,
 918   MOD_VEX_0F98_L_0,
 919   MOD_VEX_0F99_L_0,
 920   MOD_VEX_0FAE_REG_2,
 921   MOD_VEX_0FAE_REG_3,
 922   MOD_VEX_0FD7,
 923   MOD_VEX_0FE7,
 924   MOD_VEX_0FF0_PREFIX_3,
 925   MOD_VEX_0F381A,
 926   MOD_VEX_0F382A,
 927   MOD_VEX_0F382C,
 928   MOD_VEX_0F382D,
 929   MOD_VEX_0F382E,
 930   MOD_VEX_0F382F,
 931   MOD_VEX_0F3849_X86_64_P_0_W_0,
 932   MOD_VEX_0F3849_X86_64_P_2_W_0,
 933   MOD_VEX_0F3849_X86_64_P_3_W_0,
 934   MOD_VEX_0F384B_X86_64_P_1_W_0,
 935   MOD_VEX_0F384B_X86_64_P_2_W_0,
 936   MOD_VEX_0F384B_X86_64_P_3_W_0,
 937   MOD_VEX_0F385A,
 938   MOD_VEX_0F385C_X86_64_P_1_W_0,
 939   MOD_VEX_0F385C_X86_64_P_3_W_0,
 940   MOD_VEX_0F385E_X86_64_P_0_W_0,
 941   MOD_VEX_0F385E_X86_64_P_1_W_0,
 942   MOD_VEX_0F385E_X86_64_P_2_W_0,
 943   MOD_VEX_0F385E_X86_64_P_3_W_0,
 944   MOD_VEX_0F388C,
 945   MOD_VEX_0F388E,
 946   MOD_VEX_0F3A30_L_0,
 947   MOD_VEX_0F3A31_L_0,
 948   MOD_VEX_0F3A32_L_0,
 949   MOD_VEX_0F3A33_L_0,
 950
 951   MOD_XOP_09_12,
 952
 953   MOD_EVEX_0F381A,
 954   MOD_EVEX_0F381B,
 955   MOD_EVEX_0F3828_P_1,
 956   MOD_EVEX_0F382A_P_1_W_1,
 957   MOD_EVEX_0F3838_P_1,
 958   MOD_EVEX_0F383A_P_1_W_0,
 959   MOD_EVEX_0F385A,
 960   MOD_EVEX_0F385B,
 961   MOD_EVEX_0F387A_W_0,
 962   MOD_EVEX_0F387B_W_0,
 963   MOD_EVEX_0F387C,
 964   MOD_EVEX_0F38C6,
 965   MOD_EVEX_0F38C7,
 966 };
 967
 968 enum
 969 {
 970   RM_C6_REG_7 = 0,
 971   RM_C7_REG_7,
 972   RM_0F01_REG_0,
 973   RM_0F01_REG_1,
 974   RM_0F01_REG_2,
 975   RM_0F01_REG_3,
 976   RM_0F01_REG_5_MOD_3,
 977   RM_0F01_REG_7_MOD_3,
 978   RM_0F1E_P_1_MOD_3_REG_7,
 979   RM_0FAE_REG_6_MOD_3_P_0,
 980   RM_0FAE_REG_7_MOD_3,
 981   RM_0F3A0F_P_1_MOD_3_REG_0,
 982
 983   RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0
 984 };
 985
 986 enum
 987 {
 988   PREFIX_90 = 0,
 989   PREFIX_0F01_REG_0_MOD_3_RM_6,
 990   PREFIX_0F01_REG_1_RM_4,
 991   PREFIX_0F01_REG_1_RM_5,
 992   PREFIX_0F01_REG_1_RM_6,
 993   PREFIX_0F01_REG_1_RM_7,
 994   PREFIX_0F01_REG_3_RM_1,
 995   PREFIX_0F01_REG_5_MOD_0,
 996   PREFIX_0F01_REG_5_MOD_3_RM_0,
 997   PREFIX_0F01_REG_5_MOD_3_RM_1,
 998   PREFIX_0F01_REG_5_MOD_3_RM_2,
 999   PREFIX_0F01_REG_5_MOD_3_RM_4,
1000   PREFIX_0F01_REG_5_MOD_3_RM_5,
1001   PREFIX_0F01_REG_5_MOD_3_RM_6,
1002   PREFIX_0F01_REG_5_MOD_3_RM_7,
1003   PREFIX_0F01_REG_7_MOD_3_RM_2,
1004   PREFIX_0F01_REG_7_MOD_3_RM_6,
1005   PREFIX_0F01_REG_7_MOD_3_RM_7,
1006   PREFIX_0F09,
1007   PREFIX_0F10,
1008   PREFIX_0F11,
1009   PREFIX_0F12,
1010   PREFIX_0F16,
1011   PREFIX_0F18_REG_6_MOD_0_X86_64,
1012   PREFIX_0F18_REG_7_MOD_0_X86_64,
1013   PREFIX_0F1A,
1014   PREFIX_0F1B,
1015   PREFIX_0F1C,
1016   PREFIX_0F1E,
1017   PREFIX_0F2A,
1018   PREFIX_0F2B,
1019   PREFIX_0F2C,
1020   PREFIX_0F2D,
1021   PREFIX_0F2E,
1022   PREFIX_0F2F,
1023   PREFIX_0F51,
1024   PREFIX_0F52,
1025   PREFIX_0F53,
1026   PREFIX_0F58,
1027   PREFIX_0F59,
1028   PREFIX_0F5A,
1029   PREFIX_0F5B,
1030   PREFIX_0F5C,
1031   PREFIX_0F5D,
1032   PREFIX_0F5E,
1033   PREFIX_0F5F,
1034   PREFIX_0F60,
1035   PREFIX_0F61,
1036   PREFIX_0F62,
1037   PREFIX_0F6F,
1038   PREFIX_0F70,
1039   PREFIX_0F78,
1040   PREFIX_0F79,
1041   PREFIX_0F7C,
1042   PREFIX_0F7D,
1043   PREFIX_0F7E,
1044   PREFIX_0F7F,
1045   PREFIX_0FAE_REG_0_MOD_3,
1046   PREFIX_0FAE_REG_1_MOD_3,
1047   PREFIX_0FAE_REG_2_MOD_3,
1048   PREFIX_0FAE_REG_3_MOD_3,
1049   PREFIX_0FAE_REG_4_MOD_0,
1050   PREFIX_0FAE_REG_4_MOD_3,
1051   PREFIX_0FAE_REG_5_MOD_3,
1052   PREFIX_0FAE_REG_6_MOD_0,
1053   PREFIX_0FAE_REG_6_MOD_3,
1054   PREFIX_0FAE_REG_7_MOD_0,
1055   PREFIX_0FB8,
1056   PREFIX_0FBC,
1057   PREFIX_0FBD,
1058   PREFIX_0FC2,
1059   PREFIX_0FC7_REG_6_MOD_0,
1060   PREFIX_0FC7_REG_6_MOD_3,
1061   PREFIX_0FC7_REG_7_MOD_3,
1062   PREFIX_0FD0,
1063   PREFIX_0FD6,
1064   PREFIX_0FE6,
1065   PREFIX_0FE7,
1066   PREFIX_0FF0,
1067   PREFIX_0FF7,
1068   PREFIX_0F38D8,
1069   PREFIX_0F38DC,
1070   PREFIX_0F38DD,
1071   PREFIX_0F38DE,
1072   PREFIX_0F38DF,
1073   PREFIX_0F38F0,
1074   PREFIX_0F38F1,
1075   PREFIX_0F38F6,
1076   PREFIX_0F38F8,
1077   PREFIX_0F38FA,
1078   PREFIX_0F38FB,
1079   PREFIX_0F3A0F,
1080   PREFIX_VEX_0F10,
1081   PREFIX_VEX_0F11,
1082   PREFIX_VEX_0F12,
1083   PREFIX_VEX_0F16,
1084   PREFIX_VEX_0F2A,
1085   PREFIX_VEX_0F2C,
1086   PREFIX_VEX_0F2D,
1087   PREFIX_VEX_0F2E,
1088   PREFIX_VEX_0F2F,
1089   PREFIX_VEX_0F41_L_1_M_1_W_0,
1090   PREFIX_VEX_0F41_L_1_M_1_W_1,
1091   PREFIX_VEX_0F42_L_1_M_1_W_0,
1092   PREFIX_VEX_0F42_L_1_M_1_W_1,
1093   PREFIX_VEX_0F44_L_0_M_1_W_0,
1094   PREFIX_VEX_0F44_L_0_M_1_W_1,
1095   PREFIX_VEX_0F45_L_1_M_1_W_0,
1096   PREFIX_VEX_0F45_L_1_M_1_W_1,
1097   PREFIX_VEX_0F46_L_1_M_1_W_0,
1098   PREFIX_VEX_0F46_L_1_M_1_W_1,
1099   PREFIX_VEX_0F47_L_1_M_1_W_0,
1100   PREFIX_VEX_0F47_L_1_M_1_W_1,
1101   PREFIX_VEX_0F4A_L_1_M_1_W_0,
1102   PREFIX_VEX_0F4A_L_1_M_1_W_1,
1103   PREFIX_VEX_0F4B_L_1_M_1_W_0,
1104   PREFIX_VEX_0F4B_L_1_M_1_W_1,
1105   PREFIX_VEX_0F51,
1106   PREFIX_VEX_0F52,
1107   PREFIX_VEX_0F53,
1108   PREFIX_VEX_0F58,
1109   PREFIX_VEX_0F59,
1110   PREFIX_VEX_0F5A,
1111   PREFIX_VEX_0F5B,
1112   PREFIX_VEX_0F5C,
1113   PREFIX_VEX_0F5D,
1114   PREFIX_VEX_0F5E,
1115   PREFIX_VEX_0F5F,
1116   PREFIX_VEX_0F6F,
1117   PREFIX_VEX_0F70,
1118   PREFIX_VEX_0F7C,
1119   PREFIX_VEX_0F7D,
1120   PREFIX_VEX_0F7E,
1121   PREFIX_VEX_0F7F,
1122   PREFIX_VEX_0F90_L_0_W_0,
1123   PREFIX_VEX_0F90_L_0_W_1,
1124   PREFIX_VEX_0F91_L_0_M_0_W_0,
1125   PREFIX_VEX_0F91_L_0_M_0_W_1,
1126   PREFIX_VEX_0F92_L_0_M_1_W_0,
1127   PREFIX_VEX_0F92_L_0_M_1_W_1,
1128   PREFIX_VEX_0F93_L_0_M_1_W_0,
1129   PREFIX_VEX_0F93_L_0_M_1_W_1,
1130   PREFIX_VEX_0F98_L_0_M_1_W_0,
1131   PREFIX_VEX_0F98_L_0_M_1_W_1,
1132   PREFIX_VEX_0F99_L_0_M_1_W_0,
1133   PREFIX_VEX_0F99_L_0_M_1_W_1,
1134   PREFIX_VEX_0FC2,
1135   PREFIX_VEX_0FD0,
1136   PREFIX_VEX_0FE6,
1137   PREFIX_VEX_0FF0,
1138   PREFIX_VEX_0F3849_X86_64,
1139   PREFIX_VEX_0F384B_X86_64,
1140   PREFIX_VEX_0F3850_W_0,
1141   PREFIX_VEX_0F3851_W_0,
1142   PREFIX_VEX_0F385C_X86_64,
1143   PREFIX_VEX_0F385E_X86_64,
1144   PREFIX_VEX_0F3872,
1145   PREFIX_VEX_0F38B0_W_0,
1146   PREFIX_VEX_0F38B1_W_0,
1147   PREFIX_VEX_0F38F5_L_0,
1148   PREFIX_VEX_0F38F6_L_0,
1149   PREFIX_VEX_0F38F7_L_0,
1150   PREFIX_VEX_0F3AF0_L_0,
1151
1152   PREFIX_EVEX_0F5B,
1153   PREFIX_EVEX_0F6F,
1154   PREFIX_EVEX_0F70,
1155   PREFIX_EVEX_0F78,
1156   PREFIX_EVEX_0F79,
1157   PREFIX_EVEX_0F7A,
1158   PREFIX_EVEX_0F7B,
1159   PREFIX_EVEX_0F7E,
1160   PREFIX_EVEX_0F7F,
1161   PREFIX_EVEX_0FC2,
1162   PREFIX_EVEX_0FE6,
1163   PREFIX_EVEX_0F3810,
1164   PREFIX_EVEX_0F3811,
1165   PREFIX_EVEX_0F3812,
1166   PREFIX_EVEX_0F3813,
1167   PREFIX_EVEX_0F3814,
1168   PREFIX_EVEX_0F3815,
1169   PREFIX_EVEX_0F3820,
1170   PREFIX_EVEX_0F3821,
1171   PREFIX_EVEX_0F3822,
1172   PREFIX_EVEX_0F3823,
1173   PREFIX_EVEX_0F3824,
1174   PREFIX_EVEX_0F3825,
1175   PREFIX_EVEX_0F3826,
1176   PREFIX_EVEX_0F3827,
1177   PREFIX_EVEX_0F3828,
1178   PREFIX_EVEX_0F3829,
1179   PREFIX_EVEX_0F382A,
1180   PREFIX_EVEX_0F3830,
1181   PREFIX_EVEX_0F3831,
1182   PREFIX_EVEX_0F3832,
1183   PREFIX_EVEX_0F3833,
1184   PREFIX_EVEX_0F3834,
1185   PREFIX_EVEX_0F3835,
1186   PREFIX_EVEX_0F3838,
1187   PREFIX_EVEX_0F3839,
1188   PREFIX_EVEX_0F383A,
1189   PREFIX_EVEX_0F3852,
1190   PREFIX_EVEX_0F3853,
1191   PREFIX_EVEX_0F3868,
1192   PREFIX_EVEX_0F3872,
1193   PREFIX_EVEX_0F389A,
1194   PREFIX_EVEX_0F389B,
1195   PREFIX_EVEX_0F38AA,
1196   PREFIX_EVEX_0F38AB,
1197
1198   PREFIX_EVEX_0F3A08,
1199   PREFIX_EVEX_0F3A0A,
1200   PREFIX_EVEX_0F3A26,
1201   PREFIX_EVEX_0F3A27,
1202   PREFIX_EVEX_0F3A56,
1203   PREFIX_EVEX_0F3A57,
1204   PREFIX_EVEX_0F3A66,
1205   PREFIX_EVEX_0F3A67,
1206   PREFIX_EVEX_0F3AC2,
1207
1208   PREFIX_EVEX_MAP5_10,
1209   PREFIX_EVEX_MAP5_11,
1210   PREFIX_EVEX_MAP5_1D,
1211   PREFIX_EVEX_MAP5_2A,
1212   PREFIX_EVEX_MAP5_2C,
1213   PREFIX_EVEX_MAP5_2D,
1214   PREFIX_EVEX_MAP5_2E,
1215   PREFIX_EVEX_MAP5_2F,
1216   PREFIX_EVEX_MAP5_51,
1217   PREFIX_EVEX_MAP5_58,
1218   PREFIX_EVEX_MAP5_59,
1219   PREFIX_EVEX_MAP5_5A,
1220   PREFIX_EVEX_MAP5_5B,
1221   PREFIX_EVEX_MAP5_5C,
1222   PREFIX_EVEX_MAP5_5D,
1223   PREFIX_EVEX_MAP5_5E,
1224   PREFIX_EVEX_MAP5_5F,
1225   PREFIX_EVEX_MAP5_78,
1226   PREFIX_EVEX_MAP5_79,
1227   PREFIX_EVEX_MAP5_7A,
1228   PREFIX_EVEX_MAP5_7B,
1229   PREFIX_EVEX_MAP5_7C,
1230   PREFIX_EVEX_MAP5_7D,
1231
1232   PREFIX_EVEX_MAP6_13,
1233   PREFIX_EVEX_MAP6_56,
1234   PREFIX_EVEX_MAP6_57,
1235   PREFIX_EVEX_MAP6_D6,
1236   PREFIX_EVEX_MAP6_D7,
1237 };
1238
1239 enum
1240 {
1241   X86_64_06 = 0,
1242   X86_64_07,
1243   X86_64_0E,
1244   X86_64_16,
1245   X86_64_17,
1246   X86_64_1E,
1247   X86_64_1F,
1248   X86_64_27,
1249   X86_64_2F,
1250   X86_64_37,
1251   X86_64_3F,
1252   X86_64_60,
1253   X86_64_61,
1254   X86_64_62,
1255   X86_64_63,
1256   X86_64_6D,
1257   X86_64_6F,
1258   X86_64_82,
1259   X86_64_9A,
1260   X86_64_C2,
1261   X86_64_C3,
1262   X86_64_C4,
1263   X86_64_C5,
1264   X86_64_CE,
1265   X86_64_D4,
1266   X86_64_D5,
1267   X86_64_E8,
1268   X86_64_E9,
1269   X86_64_EA,
1270   X86_64_0F01_REG_0,
1271   X86_64_0F01_REG_0_MOD_3_RM_6_P_1,
1272   X86_64_0F01_REG_0_MOD_3_RM_6_P_3,
1273   X86_64_0F01_REG_1,
1274   X86_64_0F01_REG_1_RM_5_PREFIX_2,
1275   X86_64_0F01_REG_1_RM_6_PREFIX_2,
1276   X86_64_0F01_REG_1_RM_7_PREFIX_2,
1277   X86_64_0F01_REG_2,
1278   X86_64_0F01_REG_3,
1279   X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1,
1280   X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1,
1281   X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1,
1282   X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1,
1283   X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1,
1284   X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3,
1285   X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1,
1286   X86_64_0F18_REG_6_MOD_0,
1287   X86_64_0F18_REG_7_MOD_0,
1288   X86_64_0F24,
1289   X86_64_0F26,
1290   X86_64_0FC7_REG_6_MOD_3_PREFIX_1,
1291
1292   X86_64_VEX_0F3849,
1293   X86_64_VEX_0F384B,
1294   X86_64_VEX_0F385C,
1295   X86_64_VEX_0F385E,
1296   X86_64_VEX_0F38E0,
1297   X86_64_VEX_0F38E1,
1298   X86_64_VEX_0F38E2,
1299   X86_64_VEX_0F38E3,
1300   X86_64_VEX_0F38E4,
1301   X86_64_VEX_0F38E5,
1302   X86_64_VEX_0F38E6,
1303   X86_64_VEX_0F38E7,
1304   X86_64_VEX_0F38E8,
1305   X86_64_VEX_0F38E9,
1306   X86_64_VEX_0F38EA,
1307   X86_64_VEX_0F38EB,
1308   X86_64_VEX_0F38EC,
1309   X86_64_VEX_0F38ED,
1310   X86_64_VEX_0F38EE,
1311   X86_64_VEX_0F38EF,
1312 };
1313
1314 enum
1315 {
1316   THREE_BYTE_0F38 = 0,
1317   THREE_BYTE_0F3A
1318 };
1319
1320 enum
1321 {
1322   XOP_08 = 0,
1323   XOP_09,
1324   XOP_0A
1325 };
1326
1327 enum
1328 {
1329   VEX_0F = 0,
1330   VEX_0F38,
1331   VEX_0F3A
1332 };
1333
1334 enum
1335 {
1336   EVEX_0F = 0,
1337   EVEX_0F38,
1338   EVEX_0F3A,
1339   EVEX_MAP5,
1340   EVEX_MAP6,
1341 };
1342
1343 enum
1344 {
1345   VEX_LEN_0F12_P_0_M_0 = 0,
1346   VEX_LEN_0F12_P_0_M_1,
1347 #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0
1348   VEX_LEN_0F13_M_0,
1349   VEX_LEN_0F16_P_0_M_0,
1350   VEX_LEN_0F16_P_0_M_1,
1351 #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0
1352   VEX_LEN_0F17_M_0,
1353   VEX_LEN_0F41,
1354   VEX_LEN_0F42,
1355   VEX_LEN_0F44,
1356   VEX_LEN_0F45,
1357   VEX_LEN_0F46,
1358   VEX_LEN_0F47,
1359   VEX_LEN_0F4A,
1360   VEX_LEN_0F4B,
1361   VEX_LEN_0F6E,
1362   VEX_LEN_0F77,
1363   VEX_LEN_0F7E_P_1,
1364   VEX_LEN_0F7E_P_2,
1365   VEX_LEN_0F90,
1366   VEX_LEN_0F91,
1367   VEX_LEN_0F92,
1368   VEX_LEN_0F93,
1369   VEX_LEN_0F98,
1370   VEX_LEN_0F99,
1371   VEX_LEN_0FAE_R_2_M_0,
1372   VEX_LEN_0FAE_R_3_M_0,
1373   VEX_LEN_0FC4,
1374   VEX_LEN_0FC5,
1375   VEX_LEN_0FD6,
1376   VEX_LEN_0FF7,
1377   VEX_LEN_0F3816,
1378   VEX_LEN_0F3819,
1379   VEX_LEN_0F381A_M_0,
1380   VEX_LEN_0F3836,
1381   VEX_LEN_0F3841,
1382   VEX_LEN_0F3849_X86_64_P_0_W_0_M_0,
1383   VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0,
1384   VEX_LEN_0F3849_X86_64_P_2_W_0_M_0,
1385   VEX_LEN_0F3849_X86_64_P_3_W_0_M_0,
1386   VEX_LEN_0F384B_X86_64_P_1_W_0_M_0,
1387   VEX_LEN_0F384B_X86_64_P_2_W_0_M_0,
1388   VEX_LEN_0F384B_X86_64_P_3_W_0_M_0,
1389   VEX_LEN_0F385A_M_0,
1390   VEX_LEN_0F385C_X86_64_P_1_W_0_M_0,
1391   VEX_LEN_0F385C_X86_64_P_3_W_0_M_0,
1392   VEX_LEN_0F385E_X86_64_P_0_W_0_M_0,
1393   VEX_LEN_0F385E_X86_64_P_1_W_0_M_0,
1394   VEX_LEN_0F385E_X86_64_P_2_W_0_M_0,
1395   VEX_LEN_0F385E_X86_64_P_3_W_0_M_0,
1396   VEX_LEN_0F38DB,
1397   VEX_LEN_0F38F2,
1398   VEX_LEN_0F38F3,
1399   VEX_LEN_0F38F5,
1400   VEX_LEN_0F38F6,
1401   VEX_LEN_0F38F7,
1402   VEX_LEN_0F3A00,
1403   VEX_LEN_0F3A01,
1404   VEX_LEN_0F3A06,
1405   VEX_LEN_0F3A14,
1406   VEX_LEN_0F3A15,
1407   VEX_LEN_0F3A16,
1408   VEX_LEN_0F3A17,
1409   VEX_LEN_0F3A18,
1410   VEX_LEN_0F3A19,
1411   VEX_LEN_0F3A20,
1412   VEX_LEN_0F3A21,
1413   VEX_LEN_0F3A22,
1414   VEX_LEN_0F3A30,
1415   VEX_LEN_0F3A31,
1416   VEX_LEN_0F3A32,
1417   VEX_LEN_0F3A33,
1418   VEX_LEN_0F3A38,
1419   VEX_LEN_0F3A39,
1420   VEX_LEN_0F3A41,
1421   VEX_LEN_0F3A46,
1422   VEX_LEN_0F3A60,
1423   VEX_LEN_0F3A61,
1424   VEX_LEN_0F3A62,
1425   VEX_LEN_0F3A63,
1426   VEX_LEN_0F3ADF,
1427   VEX_LEN_0F3AF0,
1428   VEX_LEN_0FXOP_08_85,
1429   VEX_LEN_0FXOP_08_86,
1430   VEX_LEN_0FXOP_08_87,
1431   VEX_LEN_0FXOP_08_8E,
1432   VEX_LEN_0FXOP_08_8F,
1433   VEX_LEN_0FXOP_08_95,
1434   VEX_LEN_0FXOP_08_96,
1435   VEX_LEN_0FXOP_08_97,
1436   VEX_LEN_0FXOP_08_9E,
1437   VEX_LEN_0FXOP_08_9F,
1438   VEX_LEN_0FXOP_08_A3,
1439   VEX_LEN_0FXOP_08_A6,
1440   VEX_LEN_0FXOP_08_B6,
1441   VEX_LEN_0FXOP_08_C0,
1442   VEX_LEN_0FXOP_08_C1,
1443   VEX_LEN_0FXOP_08_C2,
1444   VEX_LEN_0FXOP_08_C3,
1445   VEX_LEN_0FXOP_08_CC,
1446   VEX_LEN_0FXOP_08_CD,
1447   VEX_LEN_0FXOP_08_CE,
1448   VEX_LEN_0FXOP_08_CF,
1449   VEX_LEN_0FXOP_08_EC,
1450   VEX_LEN_0FXOP_08_ED,
1451   VEX_LEN_0FXOP_08_EE,
1452   VEX_LEN_0FXOP_08_EF,
1453   VEX_LEN_0FXOP_09_01,
1454   VEX_LEN_0FXOP_09_02,
1455   VEX_LEN_0FXOP_09_12_M_1,
1456   VEX_LEN_0FXOP_09_82_W_0,
1457   VEX_LEN_0FXOP_09_83_W_0,
1458   VEX_LEN_0FXOP_09_90,
1459   VEX_LEN_0FXOP_09_91,
1460   VEX_LEN_0FXOP_09_92,
1461   VEX_LEN_0FXOP_09_93,
1462   VEX_LEN_0FXOP_09_94,
1463   VEX_LEN_0FXOP_09_95,
1464   VEX_LEN_0FXOP_09_96,
1465   VEX_LEN_0FXOP_09_97,
1466   VEX_LEN_0FXOP_09_98,
1467   VEX_LEN_0FXOP_09_99,
1468   VEX_LEN_0FXOP_09_9A,
1469   VEX_LEN_0FXOP_09_9B,
1470   VEX_LEN_0FXOP_09_C1,
1471   VEX_LEN_0FXOP_09_C2,
1472   VEX_LEN_0FXOP_09_C3,
1473   VEX_LEN_0FXOP_09_C6,
1474   VEX_LEN_0FXOP_09_C7,
1475   VEX_LEN_0FXOP_09_CB,
1476   VEX_LEN_0FXOP_09_D1,
1477   VEX_LEN_0FXOP_09_D2,
1478   VEX_LEN_0FXOP_09_D3,
1479   VEX_LEN_0FXOP_09_D6,
1480   VEX_LEN_0FXOP_09_D7,
1481   VEX_LEN_0FXOP_09_DB,
1482   VEX_LEN_0FXOP_09_E1,
1483   VEX_LEN_0FXOP_09_E2,
1484   VEX_LEN_0FXOP_09_E3,
1485   VEX_LEN_0FXOP_0A_12,
1486 };
1487
1488 enum
1489 {
1490   EVEX_LEN_0F3816 = 0,
1491   EVEX_LEN_0F3819,
1492   EVEX_LEN_0F381A_M_0,
1493   EVEX_LEN_0F381B_M_0,
1494   EVEX_LEN_0F3836,
1495   EVEX_LEN_0F385A_M_0,
1496   EVEX_LEN_0F385B_M_0,
1497   EVEX_LEN_0F38C6_M_0,
1498   EVEX_LEN_0F38C7_M_0,
1499   EVEX_LEN_0F3A00,
1500   EVEX_LEN_0F3A01,
1501   EVEX_LEN_0F3A18,
1502   EVEX_LEN_0F3A19,
1503   EVEX_LEN_0F3A1A,
1504   EVEX_LEN_0F3A1B,
1505   EVEX_LEN_0F3A23,
1506   EVEX_LEN_0F3A38,
1507   EVEX_LEN_0F3A39,
1508   EVEX_LEN_0F3A3A,
1509   EVEX_LEN_0F3A3B,
1510   EVEX_LEN_0F3A43
1511 };
1512
1513 enum
1514 {
1515   VEX_W_0F41_L_1_M_1 = 0,
1516   VEX_W_0F42_L_1_M_1,
1517   VEX_W_0F44_L_0_M_1,
1518   VEX_W_0F45_L_1_M_1,
1519   VEX_W_0F46_L_1_M_1,
1520   VEX_W_0F47_L_1_M_1,
1521   VEX_W_0F4A_L_1_M_1,
1522   VEX_W_0F4B_L_1_M_1,
1523   VEX_W_0F90_L_0,
1524   VEX_W_0F91_L_0_M_0,
1525   VEX_W_0F92_L_0_M_1,
1526   VEX_W_0F93_L_0_M_1,
1527   VEX_W_0F98_L_0_M_1,
1528   VEX_W_0F99_L_0_M_1,
1529   VEX_W_0F380C,
1530   VEX_W_0F380D,
1531   VEX_W_0F380E,
1532   VEX_W_0F380F,
1533   VEX_W_0F3813,
1534   VEX_W_0F3816_L_1,
1535   VEX_W_0F3818,
1536   VEX_W_0F3819_L_1,
1537   VEX_W_0F381A_M_0_L_1,
1538   VEX_W_0F382C_M_0,
1539   VEX_W_0F382D_M_0,
1540   VEX_W_0F382E_M_0,
1541   VEX_W_0F382F_M_0,
1542   VEX_W_0F3836,
1543   VEX_W_0F3846,
1544   VEX_W_0F3849_X86_64_P_0,
1545   VEX_W_0F3849_X86_64_P_2,
1546   VEX_W_0F3849_X86_64_P_3,
1547   VEX_W_0F384B_X86_64_P_1,
1548   VEX_W_0F384B_X86_64_P_2,
1549   VEX_W_0F384B_X86_64_P_3,
1550   VEX_W_0F3850,
1551   VEX_W_0F3851,
1552   VEX_W_0F3852,
1553   VEX_W_0F3853,
1554   VEX_W_0F3858,
1555   VEX_W_0F3859,
1556   VEX_W_0F385A_M_0_L_0,
1557   VEX_W_0F385C_X86_64_P_1,
1558   VEX_W_0F385C_X86_64_P_3,
1559   VEX_W_0F385E_X86_64_P_0,
1560   VEX_W_0F385E_X86_64_P_1,
1561   VEX_W_0F385E_X86_64_P_2,
1562   VEX_W_0F385E_X86_64_P_3,
1563   VEX_W_0F3872_P_1,
1564   VEX_W_0F3878,
1565   VEX_W_0F3879,
1566   VEX_W_0F38B0,
1567   VEX_W_0F38B1,
1568   VEX_W_0F38B4,
1569   VEX_W_0F38B5,
1570   VEX_W_0F38CF,
1571   VEX_W_0F3A00_L_1,
1572   VEX_W_0F3A01_L_1,
1573   VEX_W_0F3A02,
1574   VEX_W_0F3A04,
1575   VEX_W_0F3A05,
1576   VEX_W_0F3A06_L_1,
1577   VEX_W_0F3A18_L_1,
1578   VEX_W_0F3A19_L_1,
1579   VEX_W_0F3A1D,
1580   VEX_W_0F3A38_L_1,
1581   VEX_W_0F3A39_L_1,
1582   VEX_W_0F3A46_L_1,
1583   VEX_W_0F3A4A,
1584   VEX_W_0F3A4B,
1585   VEX_W_0F3A4C,
1586   VEX_W_0F3ACE,
1587   VEX_W_0F3ACF,
1588
1589   VEX_W_0FXOP_08_85_L_0,
1590   VEX_W_0FXOP_08_86_L_0,
1591   VEX_W_0FXOP_08_87_L_0,
1592   VEX_W_0FXOP_08_8E_L_0,
1593   VEX_W_0FXOP_08_8F_L_0,
1594   VEX_W_0FXOP_08_95_L_0,
1595   VEX_W_0FXOP_08_96_L_0,
1596   VEX_W_0FXOP_08_97_L_0,
1597   VEX_W_0FXOP_08_9E_L_0,
1598   VEX_W_0FXOP_08_9F_L_0,
1599   VEX_W_0FXOP_08_A6_L_0,
1600   VEX_W_0FXOP_08_B6_L_0,
1601   VEX_W_0FXOP_08_C0_L_0,
1602   VEX_W_0FXOP_08_C1_L_0,
1603   VEX_W_0FXOP_08_C2_L_0,
1604   VEX_W_0FXOP_08_C3_L_0,
1605   VEX_W_0FXOP_08_CC_L_0,
1606   VEX_W_0FXOP_08_CD_L_0,
1607   VEX_W_0FXOP_08_CE_L_0,
1608   VEX_W_0FXOP_08_CF_L_0,
1609   VEX_W_0FXOP_08_EC_L_0,
1610   VEX_W_0FXOP_08_ED_L_0,
1611   VEX_W_0FXOP_08_EE_L_0,
1612   VEX_W_0FXOP_08_EF_L_0,
1613
1614   VEX_W_0FXOP_09_80,
1615   VEX_W_0FXOP_09_81,
1616   VEX_W_0FXOP_09_82,
1617   VEX_W_0FXOP_09_83,
1618   VEX_W_0FXOP_09_C1_L_0,
1619   VEX_W_0FXOP_09_C2_L_0,
1620   VEX_W_0FXOP_09_C3_L_0,
1621   VEX_W_0FXOP_09_C6_L_0,
1622   VEX_W_0FXOP_09_C7_L_0,
1623   VEX_W_0FXOP_09_CB_L_0,
1624   VEX_W_0FXOP_09_D1_L_0,
1625   VEX_W_0FXOP_09_D2_L_0,
1626   VEX_W_0FXOP_09_D3_L_0,
1627   VEX_W_0FXOP_09_D6_L_0,
1628   VEX_W_0FXOP_09_D7_L_0,
1629   VEX_W_0FXOP_09_DB_L_0,
1630   VEX_W_0FXOP_09_E1_L_0,
1631   VEX_W_0FXOP_09_E2_L_0,
1632   VEX_W_0FXOP_09_E3_L_0,
1633
1634   EVEX_W_0F5B_P_0,
1635   EVEX_W_0F62,
1636   EVEX_W_0F66,
1637   EVEX_W_0F6A,
1638   EVEX_W_0F6B,
1639   EVEX_W_0F6C,
1640   EVEX_W_0F6D,
1641   EVEX_W_0F6F_P_1,
1642   EVEX_W_0F6F_P_2,
1643   EVEX_W_0F6F_P_3,
1644   EVEX_W_0F70_P_2,
1645   EVEX_W_0F72_R_2,
1646   EVEX_W_0F72_R_6,
1647   EVEX_W_0F73_R_2,
1648   EVEX_W_0F73_R_6,
1649   EVEX_W_0F76,
1650   EVEX_W_0F78_P_0,
1651   EVEX_W_0F78_P_2,
1652   EVEX_W_0F79_P_0,
1653   EVEX_W_0F79_P_2,
1654   EVEX_W_0F7A_P_1,
1655   EVEX_W_0F7A_P_2,
1656   EVEX_W_0F7A_P_3,
1657   EVEX_W_0F7B_P_2,
1658   EVEX_W_0F7E_P_1,
1659   EVEX_W_0F7F_P_1,
1660   EVEX_W_0F7F_P_2,
1661   EVEX_W_0F7F_P_3,
1662   EVEX_W_0FD2,
1663   EVEX_W_0FD3,
1664   EVEX_W_0FD4,
1665   EVEX_W_0FD6,
1666   EVEX_W_0FE6_P_1,
1667   EVEX_W_0FE7,
1668   EVEX_W_0FF2,
1669   EVEX_W_0FF3,
1670   EVEX_W_0FF4,
1671   EVEX_W_0FFA,
1672   EVEX_W_0FFB,
1673   EVEX_W_0FFE,
1674
1675   EVEX_W_0F3810_P_1,
1676   EVEX_W_0F3810_P_2,
1677   EVEX_W_0F3811_P_1,
1678   EVEX_W_0F3811_P_2,
1679   EVEX_W_0F3812_P_1,
1680   EVEX_W_0F3812_P_2,
1681   EVEX_W_0F3813_P_1,
1682   EVEX_W_0F3814_P_1,
1683   EVEX_W_0F3815_P_1,
1684   EVEX_W_0F3819_L_n,
1685   EVEX_W_0F381A_M_0_L_n,
1686   EVEX_W_0F381B_M_0_L_2,
1687   EVEX_W_0F381E,
1688   EVEX_W_0F381F,
1689   EVEX_W_0F3820_P_1,
1690   EVEX_W_0F3821_P_1,
1691   EVEX_W_0F3822_P_1,
1692   EVEX_W_0F3823_P_1,
1693   EVEX_W_0F3824_P_1,
1694   EVEX_W_0F3825_P_1,
1695   EVEX_W_0F3825_P_2,
1696   EVEX_W_0F3828_P_2,
1697   EVEX_W_0F3829_P_2,
1698   EVEX_W_0F382A_P_1,
1699   EVEX_W_0F382A_P_2,
1700   EVEX_W_0F382B,
1701   EVEX_W_0F3830_P_1,
1702   EVEX_W_0F3831_P_1,
1703   EVEX_W_0F3832_P_1,
1704   EVEX_W_0F3833_P_1,
1705   EVEX_W_0F3834_P_1,
1706   EVEX_W_0F3835_P_1,
1707   EVEX_W_0F3835_P_2,
1708   EVEX_W_0F3837,
1709   EVEX_W_0F383A_P_1,
1710   EVEX_W_0F3859,
1711   EVEX_W_0F385A_M_0_L_n,
1712   EVEX_W_0F385B_M_0_L_2,
1713   EVEX_W_0F3870,
1714   EVEX_W_0F3872_P_2,
1715   EVEX_W_0F387A,
1716   EVEX_W_0F387B,
1717   EVEX_W_0F3883,
1718
1719   EVEX_W_0F3A18_L_n,
1720   EVEX_W_0F3A19_L_n,
1721   EVEX_W_0F3A1A_L_2,
1722   EVEX_W_0F3A1B_L_2,
1723   EVEX_W_0F3A21,
1724   EVEX_W_0F3A23_L_n,
1725   EVEX_W_0F3A38_L_n,
1726   EVEX_W_0F3A39_L_n,
1727   EVEX_W_0F3A3A_L_2,
1728   EVEX_W_0F3A3B_L_2,
1729   EVEX_W_0F3A42,
1730   EVEX_W_0F3A43_L_n,
1731   EVEX_W_0F3A70,
1732   EVEX_W_0F3A72,
1733
1734   EVEX_W_MAP5_5B_P_0,
1735   EVEX_W_MAP5_7A_P_3,
1736 };
1737
1738 typedef void (*op_rtn) (instr_info *ins, int bytemode, int sizeflag);
1739
1740 struct dis386 {
1741   const char *name;
1742   struct
1743     {
1744       op_rtn rtn;
1745       int bytemode;
1746     } op[MAX_OPERANDS];
1747   unsigned int prefix_requirement;
1748 };
1749
1750 /* Upper case letters in the instruction names here are macros.
1751    'A' => print 'b' if no register operands or suffix_always is true
1752    'B' => print 'b' if suffix_always is true
1753    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1754           size prefix
1755    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1756           suffix_always is true
1757    'E' => print 'e' if 32-bit form of jcxz
1758    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1759    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1760    'H' => print ",pt" or ",pn" branch hint
1761    'I' unused.
1762    'J' unused.
1763    'K' => print 'd' or 'q' if rex prefix is present.
1764    'L' unused.
1765    'M' => print 'r' if intel_mnemonic is false.
1766    'N' => print 'n' if instruction has no wait "prefix"
1767    'O' => print 'd' or 'o' (or 'q' in Intel mode)
1768    'P' => behave as 'T' except with register operand outside of suffix_always
1769           mode
1770    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1771           is true
1772    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1773    'S' => print 'w', 'l' or 'q' if suffix_always is true
1774    'T' => print 'w', 'l'/'d', or 'q' if instruction has an operand size
1775           prefix or if suffix_always is true.
1776    'U' unused.
1777    'V' unused.
1778    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1779    'X' => print 's', 'd' depending on data16 prefix (for XMM)
1780    'Y' unused.
1781    'Z' => print 'q' in 64bit mode and 'l' otherwise, if suffix_always is true.
1782    '!' => change condition from true to false or from false to true.
1783    '%' => add 1 upper case letter to the macro.
1784    '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
1785           prefix or suffix_always is true (lcall/ljmp).
1786    '@' => in 64bit mode for Intel64 ISA or if instruction
1787           has no operand sizing prefix, print 'q' if suffix_always is true or
1788           nothing otherwise; behave as 'P' in all other cases
1789
1790    2 upper case letter macros:
1791    "XY" => print 'x' or 'y' if suffix_always is true or no register
1792            operands and no broadcast.
1793    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
1794            register operands and no broadcast.
1795    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1796    "XD" => print 'd' if !EVEX or EVEX.W=1, EVEX.W=0 is not a valid encoding
1797    "XH" => print 'h' if EVEX.W=0, EVEX.W=1 is not a valid encoding (for FP16)
1798    "XS" => print 's' if !EVEX or EVEX.W=0, EVEX.W=1 is not a valid encoding
1799    "XV" => print "{vex} " pseudo prefix
1800    "XE" => print "{evex} " pseudo prefix if no EVEX-specific functionality is
1801            is used by an EVEX-encoded (AVX512VL) instruction.
1802    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond
1803            being false, or no operand at all in 64bit mode, or if suffix_always
1804            is true.
1805    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1806    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1807    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1808    "DQ" => print 'd' or 'q' depending on the VEX.W bit
1809    "BW" => print 'b' or 'w' depending on the VEX.W bit
1810    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
1811            an operand size prefix, or suffix_always is true.  print
1812            'q' if rex prefix is present.
1813
1814    Many of the above letters print nothing in Intel mode.  See "putop"
1815    for the details.
1816
1817    Braces '{' and '}', and vertical bars '|', indicate alternative
1818    mnemonic strings for AT&T and Intel.  */
1819
1820 static const struct dis386 dis386[] = {
1821   /* 00 */
1822   { "addB",             { Ebh1, Gb }, 0 },
1823   { "addS",             { Evh1, Gv }, 0 },
1824   { "addB",             { Gb, EbS }, 0 },
1825   { "addS",             { Gv, EvS }, 0 },
1826   { "addB",             { AL, Ib }, 0 },
1827   { "addS",             { eAX, Iv }, 0 },
1828   { X86_64_TABLE (X86_64_06) },
1829   { X86_64_TABLE (X86_64_07) },
1830   /* 08 */
1831   { "orB",              { Ebh1, Gb }, 0 },
1832   { "orS",              { Evh1, Gv }, 0 },
1833   { "orB",              { Gb, EbS }, 0 },
1834   { "orS",              { Gv, EvS }, 0 },
1835   { "orB",              { AL, Ib }, 0 },
1836   { "orS",              { eAX, Iv }, 0 },
1837   { X86_64_TABLE (X86_64_0E) },
1838   { Bad_Opcode },       /* 0x0f extended opcode escape */
1839   /* 10 */
1840   { "adcB",             { Ebh1, Gb }, 0 },
1841   { "adcS",             { Evh1, Gv }, 0 },
1842   { "adcB",             { Gb, EbS }, 0 },
1843   { "adcS",             { Gv, EvS }, 0 },
1844   { "adcB",             { AL, Ib }, 0 },
1845   { "adcS",             { eAX, Iv }, 0 },
1846   { X86_64_TABLE (X86_64_16) },
1847   { X86_64_TABLE (X86_64_17) },
1848   /* 18 */
1849   { "sbbB",             { Ebh1, Gb }, 0 },
1850   { "sbbS",             { Evh1, Gv }, 0 },
1851   { "sbbB",             { Gb, EbS }, 0 },
1852   { "sbbS",             { Gv, EvS }, 0 },
1853   { "sbbB",             { AL, Ib }, 0 },
1854   { "sbbS",             { eAX, Iv }, 0 },
1855   { X86_64_TABLE (X86_64_1E) },
1856   { X86_64_TABLE (X86_64_1F) },
1857   /* 20 */
1858   { "andB",             { Ebh1, Gb }, 0 },
1859   { "andS",             { Evh1, Gv }, 0 },
1860   { "andB",             { Gb, EbS }, 0 },
1861   { "andS",             { Gv, EvS }, 0 },
1862   { "andB",             { AL, Ib }, 0 },
1863   { "andS",             { eAX, Iv }, 0 },
1864   { Bad_Opcode },       /* SEG ES prefix */
1865   { X86_64_TABLE (X86_64_27) },
1866   /* 28 */
1867   { "subB",             { Ebh1, Gb }, 0 },
1868   { "subS",             { Evh1, Gv }, 0 },
1869   { "subB",             { Gb, EbS }, 0 },
1870   { "subS",             { Gv, EvS }, 0 },
1871   { "subB",             { AL, Ib }, 0 },
1872   { "subS",             { eAX, Iv }, 0 },
1873   { Bad_Opcode },       /* SEG CS prefix */
1874   { X86_64_TABLE (X86_64_2F) },
1875   /* 30 */
1876   { "xorB",             { Ebh1, Gb }, 0 },
1877   { "xorS",             { Evh1, Gv }, 0 },
1878   { "xorB",             { Gb, EbS }, 0 },
1879   { "xorS",             { Gv, EvS }, 0 },
1880   { "xorB",             { AL, Ib }, 0 },
1881   { "xorS",             { eAX, Iv }, 0 },
1882   { Bad_Opcode },       /* SEG SS prefix */
1883   { X86_64_TABLE (X86_64_37) },
1884   /* 38 */
1885   { "cmpB",             { Eb, Gb }, 0 },
1886   { "cmpS",             { Ev, Gv }, 0 },
1887   { "cmpB",             { Gb, EbS }, 0 },
1888   { "cmpS",             { Gv, EvS }, 0 },
1889   { "cmpB",             { AL, Ib }, 0 },
1890   { "cmpS",             { eAX, Iv }, 0 },
1891   { Bad_Opcode },       /* SEG DS prefix */
1892   { X86_64_TABLE (X86_64_3F) },
1893   /* 40 */
1894   { "inc{S|}",          { RMeAX }, 0 },
1895   { "inc{S|}",          { RMeCX }, 0 },
1896   { "inc{S|}",          { RMeDX }, 0 },
1897   { "inc{S|}",          { RMeBX }, 0 },
1898   { "inc{S|}",          { RMeSP }, 0 },
1899   { "inc{S|}",          { RMeBP }, 0 },
1900   { "inc{S|}",          { RMeSI }, 0 },
1901   { "inc{S|}",          { RMeDI }, 0 },
1902   /* 48 */
1903   { "dec{S|}",          { RMeAX }, 0 },
1904   { "dec{S|}",          { RMeCX }, 0 },
1905   { "dec{S|}",          { RMeDX }, 0 },
1906   { "dec{S|}",          { RMeBX }, 0 },
1907   { "dec{S|}",          { RMeSP }, 0 },
1908   { "dec{S|}",          { RMeBP }, 0 },
1909   { "dec{S|}",          { RMeSI }, 0 },
1910   { "dec{S|}",          { RMeDI }, 0 },
1911   /* 50 */
1912   { "push{!P|}",                { RMrAX }, 0 },
1913   { "push{!P|}",                { RMrCX }, 0 },
1914   { "push{!P|}",                { RMrDX }, 0 },
1915   { "push{!P|}",                { RMrBX }, 0 },
1916   { "push{!P|}",                { RMrSP }, 0 },
1917   { "push{!P|}",                { RMrBP }, 0 },
1918   { "push{!P|}",                { RMrSI }, 0 },
1919   { "push{!P|}",                { RMrDI }, 0 },
1920   /* 58 */
1921   { "pop{!P|}",         { RMrAX }, 0 },
1922   { "pop{!P|}",         { RMrCX }, 0 },
1923   { "pop{!P|}",         { RMrDX }, 0 },
1924   { "pop{!P|}",         { RMrBX }, 0 },
1925   { "pop{!P|}",         { RMrSP }, 0 },
1926   { "pop{!P|}",         { RMrBP }, 0 },
1927   { "pop{!P|}",         { RMrSI }, 0 },
1928   { "pop{!P|}",         { RMrDI }, 0 },
1929   /* 60 */
1930   { X86_64_TABLE (X86_64_60) },
1931   { X86_64_TABLE (X86_64_61) },
1932   { X86_64_TABLE (X86_64_62) },
1933   { X86_64_TABLE (X86_64_63) },
1934   { Bad_Opcode },       /* seg fs */
1935   { Bad_Opcode },       /* seg gs */
1936   { Bad_Opcode },       /* op size prefix */
1937   { Bad_Opcode },       /* adr size prefix */
1938   /* 68 */
1939   { "pushP",            { sIv }, 0 },
1940   { "imulS",            { Gv, Ev, Iv }, 0 },
1941   { "pushP",            { sIbT }, 0 },
1942   { "imulS",            { Gv, Ev, sIb }, 0 },
1943   { "ins{b|}",          { Ybr, indirDX }, 0 },
1944   { X86_64_TABLE (X86_64_6D) },
1945   { "outs{b|}",         { indirDXr, Xb }, 0 },
1946   { X86_64_TABLE (X86_64_6F) },
1947   /* 70 */
1948   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
1949   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
1950   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
1951   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
1952   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
1953   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
1954   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
1955   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
1956   /* 78 */
1957   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
1958   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
1959   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
1960   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
1961   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
1962   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
1963   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
1964   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
1965   /* 80 */
1966   { REG_TABLE (REG_80) },
1967   { REG_TABLE (REG_81) },
1968   { X86_64_TABLE (X86_64_82) },
1969   { REG_TABLE (REG_83) },
1970   { "testB",            { Eb, Gb }, 0 },
1971   { "testS",            { Ev, Gv }, 0 },
1972   { "xchgB",            { Ebh2, Gb }, 0 },
1973   { "xchgS",            { Evh2, Gv }, 0 },
1974   /* 88 */
1975   { "movB",             { Ebh3, Gb }, 0 },
1976   { "movS",             { Evh3, Gv }, 0 },
1977   { "movB",             { Gb, EbS }, 0 },
1978   { "movS",             { Gv, EvS }, 0 },
1979   { "movD",             { Sv, Sw }, 0 },
1980   { MOD_TABLE (MOD_8D) },
1981   { "movD",             { Sw, Sv }, 0 },
1982   { REG_TABLE (REG_8F) },
1983   /* 90 */
1984   { PREFIX_TABLE (PREFIX_90) },
1985   { "xchgS",            { RMeCX, eAX }, 0 },
1986   { "xchgS",            { RMeDX, eAX }, 0 },
1987   { "xchgS",            { RMeBX, eAX }, 0 },
1988   { "xchgS",            { RMeSP, eAX }, 0 },
1989   { "xchgS",            { RMeBP, eAX }, 0 },
1990   { "xchgS",            { RMeSI, eAX }, 0 },
1991   { "xchgS",            { RMeDI, eAX }, 0 },
1992   /* 98 */
1993   { "cW{t|}R",          { XX }, 0 },
1994   { "cR{t|}O",          { XX }, 0 },
1995   { X86_64_TABLE (X86_64_9A) },
1996   { Bad_Opcode },       /* fwait */
1997   { "pushfP",           { XX }, 0 },
1998   { "popfP",            { XX }, 0 },
1999   { "sahf",             { XX }, 0 },
2000   { "lahf",             { XX }, 0 },
2001   /* a0 */
2002   { "mov%LB",           { AL, Ob }, 0 },
2003   { "mov%LS",           { eAX, Ov }, 0 },
2004   { "mov%LB",           { Ob, AL }, 0 },
2005   { "mov%LS",           { Ov, eAX }, 0 },
2006   { "movs{b|}",         { Ybr, Xb }, 0 },
2007   { "movs{R|}",         { Yvr, Xv }, 0 },
2008   { "cmps{b|}",         { Xb, Yb }, 0 },
2009   { "cmps{R|}",         { Xv, Yv }, 0 },
2010   /* a8 */
2011   { "testB",            { AL, Ib }, 0 },
2012   { "testS",            { eAX, Iv }, 0 },
2013   { "stosB",            { Ybr, AL }, 0 },
2014   { "stosS",            { Yvr, eAX }, 0 },
2015   { "lodsB",            { ALr, Xb }, 0 },
2016   { "lodsS",            { eAXr, Xv }, 0 },
2017   { "scasB",            { AL, Yb }, 0 },
2018   { "scasS",            { eAX, Yv }, 0 },
2019   /* b0 */
2020   { "movB",             { RMAL, Ib }, 0 },
2021   { "movB",             { RMCL, Ib }, 0 },
2022   { "movB",             { RMDL, Ib }, 0 },
2023   { "movB",             { RMBL, Ib }, 0 },
2024   { "movB",             { RMAH, Ib }, 0 },
2025   { "movB",             { RMCH, Ib }, 0 },
2026   { "movB",             { RMDH, Ib }, 0 },
2027   { "movB",             { RMBH, Ib }, 0 },
2028   /* b8 */
2029   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2030   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2031   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2032   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2033   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2034   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2035   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2036   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2037   /* c0 */
2038   { REG_TABLE (REG_C0) },
2039   { REG_TABLE (REG_C1) },
2040   { X86_64_TABLE (X86_64_C2) },
2041   { X86_64_TABLE (X86_64_C3) },
2042   { X86_64_TABLE (X86_64_C4) },
2043   { X86_64_TABLE (X86_64_C5) },
2044   { REG_TABLE (REG_C6) },
2045   { REG_TABLE (REG_C7) },
2046   /* c8 */
2047   { "enterP",           { Iw, Ib }, 0 },
2048   { "leaveP",           { XX }, 0 },
2049   { "{l|}ret{|f}%LP",   { Iw }, 0 },
2050   { "{l|}ret{|f}%LP",   { XX }, 0 },
2051   { "int3",             { XX }, 0 },
2052   { "int",              { Ib }, 0 },
2053   { X86_64_TABLE (X86_64_CE) },
2054   { "iret%LP",          { XX }, 0 },
2055   /* d0 */
2056   { REG_TABLE (REG_D0) },
2057   { REG_TABLE (REG_D1) },
2058   { REG_TABLE (REG_D2) },
2059   { REG_TABLE (REG_D3) },
2060   { X86_64_TABLE (X86_64_D4) },
2061   { X86_64_TABLE (X86_64_D5) },
2062   { Bad_Opcode },
2063   { "xlat",             { DSBX }, 0 },
2064   /* d8 */
2065   { FLOAT },
2066   { FLOAT },
2067   { FLOAT },
2068   { FLOAT },
2069   { FLOAT },
2070   { FLOAT },
2071   { FLOAT },
2072   { FLOAT },
2073   /* e0 */
2074   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2075   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2076   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2077   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2078   { "inB",              { AL, Ib }, 0 },
2079   { "inG",              { zAX, Ib }, 0 },
2080   { "outB",             { Ib, AL }, 0 },
2081   { "outG",             { Ib, zAX }, 0 },
2082   /* e8 */
2083   { X86_64_TABLE (X86_64_E8) },
2084   { X86_64_TABLE (X86_64_E9) },
2085   { X86_64_TABLE (X86_64_EA) },
2086   { "jmp",              { Jb, BND }, 0 },
2087   { "inB",              { AL, indirDX }, 0 },
2088   { "inG",              { zAX, indirDX }, 0 },
2089   { "outB",             { indirDX, AL }, 0 },
2090   { "outG",             { indirDX, zAX }, 0 },
2091   /* f0 */
2092   { Bad_Opcode },       /* lock prefix */
2093   { "int1",             { XX }, 0 },
2094   { Bad_Opcode },       /* repne */
2095   { Bad_Opcode },       /* repz */
2096   { "hlt",              { XX }, 0 },
2097   { "cmc",              { XX }, 0 },
2098   { REG_TABLE (REG_F6) },
2099   { REG_TABLE (REG_F7) },
2100   /* f8 */
2101   { "clc",              { XX }, 0 },
2102   { "stc",              { XX }, 0 },
2103   { "cli",              { XX }, 0 },
2104   { "sti",              { XX }, 0 },
2105   { "cld",              { XX }, 0 },
2106   { "std",              { XX }, 0 },
2107   { REG_TABLE (REG_FE) },
2108   { REG_TABLE (REG_FF) },
2109 };
2110
2111 static const struct dis386 dis386_twobyte[] = {
2112   /* 00 */
2113   { REG_TABLE (REG_0F00 ) },
2114   { REG_TABLE (REG_0F01 ) },
2115   { "larS",             { Gv, Ew }, 0 },
2116   { "lslS",             { Gv, Ew }, 0 },
2117   { Bad_Opcode },
2118   { "syscall",          { XX }, 0 },
2119   { "clts",             { XX }, 0 },
2120   { "sysret%LQ",                { XX }, 0 },
2121   /* 08 */
2122   { "invd",             { XX }, 0 },
2123   { PREFIX_TABLE (PREFIX_0F09) },
2124   { Bad_Opcode },
2125   { "ud2",              { XX }, 0 },
2126   { Bad_Opcode },
2127   { REG_TABLE (REG_0F0D) },
2128   { "femms",            { XX }, 0 },
2129   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2130   /* 10 */
2131   { PREFIX_TABLE (PREFIX_0F10) },
2132   { PREFIX_TABLE (PREFIX_0F11) },
2133   { PREFIX_TABLE (PREFIX_0F12) },
2134   { MOD_TABLE (MOD_0F13) },
2135   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2136   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2137   { PREFIX_TABLE (PREFIX_0F16) },
2138   { MOD_TABLE (MOD_0F17) },
2139   /* 18 */
2140   { REG_TABLE (REG_0F18) },
2141   { "nopQ",             { Ev }, 0 },
2142   { PREFIX_TABLE (PREFIX_0F1A) },
2143   { PREFIX_TABLE (PREFIX_0F1B) },
2144   { PREFIX_TABLE (PREFIX_0F1C) },
2145   { "nopQ",             { Ev }, 0 },
2146   { PREFIX_TABLE (PREFIX_0F1E) },
2147   { "nopQ",             { Ev }, 0 },
2148   /* 20 */
2149   { "movZ",             { Em, Cm }, 0 },
2150   { "movZ",             { Em, Dm }, 0 },
2151   { "movZ",             { Cm, Em }, 0 },
2152   { "movZ",             { Dm, Em }, 0 },
2153   { X86_64_TABLE (X86_64_0F24) },
2154   { Bad_Opcode },
2155   { X86_64_TABLE (X86_64_0F26) },
2156   { Bad_Opcode },
2157   /* 28 */
2158   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2159   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2160   { PREFIX_TABLE (PREFIX_0F2A) },
2161   { PREFIX_TABLE (PREFIX_0F2B) },
2162   { PREFIX_TABLE (PREFIX_0F2C) },
2163   { PREFIX_TABLE (PREFIX_0F2D) },
2164   { PREFIX_TABLE (PREFIX_0F2E) },
2165   { PREFIX_TABLE (PREFIX_0F2F) },
2166   /* 30 */
2167   { "wrmsr",            { XX }, 0 },
2168   { "rdtsc",            { XX }, 0 },
2169   { "rdmsr",            { XX }, 0 },
2170   { "rdpmc",            { XX }, 0 },
2171   { "sysenter",         { SEP }, 0 },
2172   { "sysexit%LQ",       { SEP }, 0 },
2173   { Bad_Opcode },
2174   { "getsec",           { XX }, 0 },
2175   /* 38 */
2176   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2177   { Bad_Opcode },
2178   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2179   { Bad_Opcode },
2180   { Bad_Opcode },
2181   { Bad_Opcode },
2182   { Bad_Opcode },
2183   { Bad_Opcode },
2184   /* 40 */
2185   { "cmovoS",           { Gv, Ev }, 0 },
2186   { "cmovnoS",          { Gv, Ev }, 0 },
2187   { "cmovbS",           { Gv, Ev }, 0 },
2188   { "cmovaeS",          { Gv, Ev }, 0 },
2189   { "cmoveS",           { Gv, Ev }, 0 },
2190   { "cmovneS",          { Gv, Ev }, 0 },
2191   { "cmovbeS",          { Gv, Ev }, 0 },
2192   { "cmovaS",           { Gv, Ev }, 0 },
2193   /* 48 */
2194   { "cmovsS",           { Gv, Ev }, 0 },
2195   { "cmovnsS",          { Gv, Ev }, 0 },
2196   { "cmovpS",           { Gv, Ev }, 0 },
2197   { "cmovnpS",          { Gv, Ev }, 0 },
2198   { "cmovlS",           { Gv, Ev }, 0 },
2199   { "cmovgeS",          { Gv, Ev }, 0 },
2200   { "cmovleS",          { Gv, Ev }, 0 },
2201   { "cmovgS",           { Gv, Ev }, 0 },
2202   /* 50 */
2203   { MOD_TABLE (MOD_0F50) },
2204   { PREFIX_TABLE (PREFIX_0F51) },
2205   { PREFIX_TABLE (PREFIX_0F52) },
2206   { PREFIX_TABLE (PREFIX_0F53) },
2207   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2208   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2209   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2210   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2211   /* 58 */
2212   { PREFIX_TABLE (PREFIX_0F58) },
2213   { PREFIX_TABLE (PREFIX_0F59) },
2214   { PREFIX_TABLE (PREFIX_0F5A) },
2215   { PREFIX_TABLE (PREFIX_0F5B) },
2216   { PREFIX_TABLE (PREFIX_0F5C) },
2217   { PREFIX_TABLE (PREFIX_0F5D) },
2218   { PREFIX_TABLE (PREFIX_0F5E) },
2219   { PREFIX_TABLE (PREFIX_0F5F) },
2220   /* 60 */
2221   { PREFIX_TABLE (PREFIX_0F60) },
2222   { PREFIX_TABLE (PREFIX_0F61) },
2223   { PREFIX_TABLE (PREFIX_0F62) },
2224   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2225   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2226   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2227   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2228   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2229   /* 68 */
2230   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2231   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2232   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2233   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2234   { "punpcklqdq", { XM, EXx }, PREFIX_DATA },
2235   { "punpckhqdq", { XM, EXx }, PREFIX_DATA },
2236   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2237   { PREFIX_TABLE (PREFIX_0F6F) },
2238   /* 70 */
2239   { PREFIX_TABLE (PREFIX_0F70) },
2240   { MOD_TABLE (MOD_0F71) },
2241   { MOD_TABLE (MOD_0F72) },
2242   { MOD_TABLE (MOD_0F73) },
2243   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2244   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2245   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2246   { "emms",             { XX }, PREFIX_OPCODE },
2247   /* 78 */
2248   { PREFIX_TABLE (PREFIX_0F78) },
2249   { PREFIX_TABLE (PREFIX_0F79) },
2250   { Bad_Opcode },
2251   { Bad_Opcode },
2252   { PREFIX_TABLE (PREFIX_0F7C) },
2253   { PREFIX_TABLE (PREFIX_0F7D) },
2254   { PREFIX_TABLE (PREFIX_0F7E) },
2255   { PREFIX_TABLE (PREFIX_0F7F) },
2256   /* 80 */
2257   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2258   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2259   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2260   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2261   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2262   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2263   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2264   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2265   /* 88 */
2266   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2267   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2268   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2269   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2270   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2271   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2272   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2273   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2274   /* 90 */
2275   { "seto",             { Eb }, 0 },
2276   { "setno",            { Eb }, 0 },
2277   { "setb",             { Eb }, 0 },
2278   { "setae",            { Eb }, 0 },
2279   { "sete",             { Eb }, 0 },
2280   { "setne",            { Eb }, 0 },
2281   { "setbe",            { Eb }, 0 },
2282   { "seta",             { Eb }, 0 },
2283   /* 98 */
2284   { "sets",             { Eb }, 0 },
2285   { "setns",            { Eb }, 0 },
2286   { "setp",             { Eb }, 0 },
2287   { "setnp",            { Eb }, 0 },
2288   { "setl",             { Eb }, 0 },
2289   { "setge",            { Eb }, 0 },
2290   { "setle",            { Eb }, 0 },
2291   { "setg",             { Eb }, 0 },
2292   /* a0 */
2293   { "pushP",            { fs }, 0 },
2294   { "popP",             { fs }, 0 },
2295   { "cpuid",            { XX }, 0 },
2296   { "btS",              { Ev, Gv }, 0 },
2297   { "shldS",            { Ev, Gv, Ib }, 0 },
2298   { "shldS",            { Ev, Gv, CL }, 0 },
2299   { REG_TABLE (REG_0FA6) },
2300   { REG_TABLE (REG_0FA7) },
2301   /* a8 */
2302   { "pushP",            { gs }, 0 },
2303   { "popP",             { gs }, 0 },
2304   { "rsm",              { XX }, 0 },
2305   { "btsS",             { Evh1, Gv }, 0 },
2306   { "shrdS",            { Ev, Gv, Ib }, 0 },
2307   { "shrdS",            { Ev, Gv, CL }, 0 },
2308   { REG_TABLE (REG_0FAE) },
2309   { "imulS",            { Gv, Ev }, 0 },
2310   /* b0 */
2311   { "cmpxchgB",         { Ebh1, Gb }, 0 },
2312   { "cmpxchgS",         { Evh1, Gv }, 0 },
2313   { MOD_TABLE (MOD_0FB2) },
2314   { "btrS",             { Evh1, Gv }, 0 },
2315   { MOD_TABLE (MOD_0FB4) },
2316   { MOD_TABLE (MOD_0FB5) },
2317   { "movz{bR|x}",       { Gv, Eb }, 0 },
2318   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2319   /* b8 */
2320   { PREFIX_TABLE (PREFIX_0FB8) },
2321   { "ud1S",             { Gv, Ev }, 0 },
2322   { REG_TABLE (REG_0FBA) },
2323   { "btcS",             { Evh1, Gv }, 0 },
2324   { PREFIX_TABLE (PREFIX_0FBC) },
2325   { PREFIX_TABLE (PREFIX_0FBD) },
2326   { "movs{bR|x}",       { Gv, Eb }, 0 },
2327   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2328   /* c0 */
2329   { "xaddB",            { Ebh1, Gb }, 0 },
2330   { "xaddS",            { Evh1, Gv }, 0 },
2331   { PREFIX_TABLE (PREFIX_0FC2) },
2332   { MOD_TABLE (MOD_0FC3) },
2333   { "pinsrw",           { MX, Edw, Ib }, PREFIX_OPCODE },
2334   { "pextrw",           { Gd, MS, Ib }, PREFIX_OPCODE },
2335   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
2336   { REG_TABLE (REG_0FC7) },
2337   /* c8 */
2338   { "bswap",            { RMeAX }, 0 },
2339   { "bswap",            { RMeCX }, 0 },
2340   { "bswap",            { RMeDX }, 0 },
2341   { "bswap",            { RMeBX }, 0 },
2342   { "bswap",            { RMeSP }, 0 },
2343   { "bswap",            { RMeBP }, 0 },
2344   { "bswap",            { RMeSI }, 0 },
2345   { "bswap",            { RMeDI }, 0 },
2346   /* d0 */
2347   { PREFIX_TABLE (PREFIX_0FD0) },
2348   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
2349   { "psrld",            { MX, EM }, PREFIX_OPCODE },
2350   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
2351   { "paddq",            { MX, EM }, PREFIX_OPCODE },
2352   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
2353   { PREFIX_TABLE (PREFIX_0FD6) },
2354   { MOD_TABLE (MOD_0FD7) },
2355   /* d8 */
2356   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
2357   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
2358   { "pminub",           { MX, EM }, PREFIX_OPCODE },
2359   { "pand",             { MX, EM }, PREFIX_OPCODE },
2360   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
2361   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
2362   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
2363   { "pandn",            { MX, EM }, PREFIX_OPCODE },
2364   /* e0 */
2365   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
2366   { "psraw",            { MX, EM }, PREFIX_OPCODE },
2367   { "psrad",            { MX, EM }, PREFIX_OPCODE },
2368   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
2369   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
2370   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
2371   { PREFIX_TABLE (PREFIX_0FE6) },
2372   { PREFIX_TABLE (PREFIX_0FE7) },
2373   /* e8 */
2374   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
2375   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
2376   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
2377   { "por",              { MX, EM }, PREFIX_OPCODE },
2378   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
2379   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
2380   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
2381   { "pxor",             { MX, EM }, PREFIX_OPCODE },
2382   /* f0 */
2383   { PREFIX_TABLE (PREFIX_0FF0) },
2384   { "psllw",            { MX, EM }, PREFIX_OPCODE },
2385   { "pslld",            { MX, EM }, PREFIX_OPCODE },
2386   { "psllq",            { MX, EM }, PREFIX_OPCODE },
2387   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
2388   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
2389   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
2390   { PREFIX_TABLE (PREFIX_0FF7) },
2391   /* f8 */
2392   { "psubb",            { MX, EM }, PREFIX_OPCODE },
2393   { "psubw",            { MX, EM }, PREFIX_OPCODE },
2394   { "psubd",            { MX, EM }, PREFIX_OPCODE },
2395   { "psubq",            { MX, EM }, PREFIX_OPCODE },
2396   { "paddb",            { MX, EM }, PREFIX_OPCODE },
2397   { "paddw",            { MX, EM }, PREFIX_OPCODE },
2398   { "paddd",            { MX, EM }, PREFIX_OPCODE },
2399   { "ud0S",             { Gv, Ev }, 0 },
2400 };
2401
2402 static const bool onebyte_has_modrm[256] = {
2403   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2404   /*       -------------------------------        */
2405   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2406   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2407   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2408   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2409   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2410   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2411   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2412   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2413   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2414   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2415   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2416   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2417   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2418   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2419   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2420   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2421   /*       -------------------------------        */
2422   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2423 };
2424
2425 static const bool twobyte_has_modrm[256] = {
2426   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2427   /*       -------------------------------        */
2428   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2429   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2430   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2431   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2432   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2433   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2434   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2435   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2436   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2437   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2438   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2439   /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2440   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2441   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2442   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2443   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1  /* ff */
2444   /*       -------------------------------        */
2445   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2446 };
2447
2448
2449 struct op
2450   {
2451     const char *name;
2452     unsigned int len;
2453   };
2454
2455 /* If we are accessing mod/rm/reg without need_modrm set, then the
2456    values are stale.  Hitting this abort likely indicates that you
2457    need to update onebyte_has_modrm or twobyte_has_modrm.  */
2458 #define MODRM_CHECK  if (!ins->need_modrm) abort ()
2459
2460 static const char *const intel_index16[] = {
2461   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2462 };
2463
2464 static const char *const att_names64[] = {
2465   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2466   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2467 };
2468 static const char *const att_names32[] = {
2469   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2470   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2471 };
2472 static const char *const att_names16[] = {
2473   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2474   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2475 };
2476 static const char *const att_names8[] = {
2477   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2478 };
2479 static const char *const att_names8rex[] = {
2480   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2481   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2482 };
2483 static const char *const att_names_seg[] = {
2484   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2485 };
2486 static const char att_index64[] = "%riz";
2487 static const char att_index32[] = "%eiz";
2488 static const char *const att_index16[] = {
2489   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2490 };
2491
2492 static const char *const att_names_mm[] = {
2493   "%mm0", "%mm1", "%mm2", "%mm3",
2494   "%mm4", "%mm5", "%mm6", "%mm7"
2495 };
2496
2497 static const char *const att_names_bnd[] = {
2498   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
2499 };
2500
2501 static const char *const att_names_xmm[] = {
2502   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2503   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2504   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2505   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
2506   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
2507   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
2508   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
2509   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
2510 };
2511
2512 static const char *const att_names_ymm[] = {
2513   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2514   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2515   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2516   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
2517   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
2518   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
2519   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
2520   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
2521 };
2522
2523 static const char *const att_names_zmm[] = {
2524   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
2525   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
2526   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
2527   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
2528   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
2529   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
2530   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
2531   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
2532 };
2533
2534 static const char *const att_names_tmm[] = {
2535   "%tmm0", "%tmm1", "%tmm2", "%tmm3",
2536   "%tmm4", "%tmm5", "%tmm6", "%tmm7"
2537 };
2538
2539 static const char *const att_names_mask[] = {
2540   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
2541 };
2542
2543 static const char *const names_rounding[] =
2544 {
2545   "{rn-",
2546   "{rd-",
2547   "{ru-",
2548   "{rz-"
2549 };
2550
2551 static const struct dis386 reg_table[][8] = {
2552   /* REG_80 */
2553   {
2554     { "addA",   { Ebh1, Ib }, 0 },
2555     { "orA",    { Ebh1, Ib }, 0 },
2556     { "adcA",   { Ebh1, Ib }, 0 },
2557     { "sbbA",   { Ebh1, Ib }, 0 },
2558     { "andA",   { Ebh1, Ib }, 0 },
2559     { "subA",   { Ebh1, Ib }, 0 },
2560     { "xorA",   { Ebh1, Ib }, 0 },
2561     { "cmpA",   { Eb, Ib }, 0 },
2562   },
2563   /* REG_81 */
2564   {
2565     { "addQ",   { Evh1, Iv }, 0 },
2566     { "orQ",    { Evh1, Iv }, 0 },
2567     { "adcQ",   { Evh1, Iv }, 0 },
2568     { "sbbQ",   { Evh1, Iv }, 0 },
2569     { "andQ",   { Evh1, Iv }, 0 },
2570     { "subQ",   { Evh1, Iv }, 0 },
2571     { "xorQ",   { Evh1, Iv }, 0 },
2572     { "cmpQ",   { Ev, Iv }, 0 },
2573   },
2574   /* REG_83 */
2575   {
2576     { "addQ",   { Evh1, sIb }, 0 },
2577     { "orQ",    { Evh1, sIb }, 0 },
2578     { "adcQ",   { Evh1, sIb }, 0 },
2579     { "sbbQ",   { Evh1, sIb }, 0 },
2580     { "andQ",   { Evh1, sIb }, 0 },
2581     { "subQ",   { Evh1, sIb }, 0 },
2582     { "xorQ",   { Evh1, sIb }, 0 },
2583     { "cmpQ",   { Ev, sIb }, 0 },
2584   },
2585   /* REG_8F */
2586   {
2587     { "pop{P|}", { stackEv }, 0 },
2588     { XOP_8F_TABLE (XOP_09) },
2589     { Bad_Opcode },
2590     { Bad_Opcode },
2591     { Bad_Opcode },
2592     { XOP_8F_TABLE (XOP_09) },
2593   },
2594   /* REG_C0 */
2595   {
2596     { "rolA",   { Eb, Ib }, 0 },
2597     { "rorA",   { Eb, Ib }, 0 },
2598     { "rclA",   { Eb, Ib }, 0 },
2599     { "rcrA",   { Eb, Ib }, 0 },
2600     { "shlA",   { Eb, Ib }, 0 },
2601     { "shrA",   { Eb, Ib }, 0 },
2602     { "shlA",   { Eb, Ib }, 0 },
2603     { "sarA",   { Eb, Ib }, 0 },
2604   },
2605   /* REG_C1 */
2606   {
2607     { "rolQ",   { Ev, Ib }, 0 },
2608     { "rorQ",   { Ev, Ib }, 0 },
2609     { "rclQ",   { Ev, Ib }, 0 },
2610     { "rcrQ",   { Ev, Ib }, 0 },
2611     { "shlQ",   { Ev, Ib }, 0 },
2612     { "shrQ",   { Ev, Ib }, 0 },
2613     { "shlQ",   { Ev, Ib }, 0 },
2614     { "sarQ",   { Ev, Ib }, 0 },
2615   },
2616   /* REG_C6 */
2617   {
2618     { "movA",   { Ebh3, Ib }, 0 },
2619     { Bad_Opcode },
2620     { Bad_Opcode },
2621     { Bad_Opcode },
2622     { Bad_Opcode },
2623     { Bad_Opcode },
2624     { Bad_Opcode },
2625     { MOD_TABLE (MOD_C6_REG_7) },
2626   },
2627   /* REG_C7 */
2628   {
2629     { "movQ",   { Evh3, Iv }, 0 },
2630     { Bad_Opcode },
2631     { Bad_Opcode },
2632     { Bad_Opcode },
2633     { Bad_Opcode },
2634     { Bad_Opcode },
2635     { Bad_Opcode },
2636     { MOD_TABLE (MOD_C7_REG_7) },
2637   },
2638   /* REG_D0 */
2639   {
2640     { "rolA",   { Eb, I1 }, 0 },
2641     { "rorA",   { Eb, I1 }, 0 },
2642     { "rclA",   { Eb, I1 }, 0 },
2643     { "rcrA",   { Eb, I1 }, 0 },
2644     { "shlA",   { Eb, I1 }, 0 },
2645     { "shrA",   { Eb, I1 }, 0 },
2646     { "shlA",   { Eb, I1 }, 0 },
2647     { "sarA",   { Eb, I1 }, 0 },
2648   },
2649   /* REG_D1 */
2650   {
2651     { "rolQ",   { Ev, I1 }, 0 },
2652     { "rorQ",   { Ev, I1 }, 0 },
2653     { "rclQ",   { Ev, I1 }, 0 },
2654     { "rcrQ",   { Ev, I1 }, 0 },
2655     { "shlQ",   { Ev, I1 }, 0 },
2656     { "shrQ",   { Ev, I1 }, 0 },
2657     { "shlQ",   { Ev, I1 }, 0 },
2658     { "sarQ",   { Ev, I1 }, 0 },
2659   },
2660   /* REG_D2 */
2661   {
2662     { "rolA",   { Eb, CL }, 0 },
2663     { "rorA",   { Eb, CL }, 0 },
2664     { "rclA",   { Eb, CL }, 0 },
2665     { "rcrA",   { Eb, CL }, 0 },
2666     { "shlA",   { Eb, CL }, 0 },
2667     { "shrA",   { Eb, CL }, 0 },
2668     { "shlA",   { Eb, CL }, 0 },
2669     { "sarA",   { Eb, CL }, 0 },
2670   },
2671   /* REG_D3 */
2672   {
2673     { "rolQ",   { Ev, CL }, 0 },
2674     { "rorQ",   { Ev, CL }, 0 },
2675     { "rclQ",   { Ev, CL }, 0 },
2676     { "rcrQ",   { Ev, CL }, 0 },
2677     { "shlQ",   { Ev, CL }, 0 },
2678     { "shrQ",   { Ev, CL }, 0 },
2679     { "shlQ",   { Ev, CL }, 0 },
2680     { "sarQ",   { Ev, CL }, 0 },
2681   },
2682   /* REG_F6 */
2683   {
2684     { "testA",  { Eb, Ib }, 0 },
2685     { "testA",  { Eb, Ib }, 0 },
2686     { "notA",   { Ebh1 }, 0 },
2687     { "negA",   { Ebh1 }, 0 },
2688     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
2689     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
2690     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
2691     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
2692   },
2693   /* REG_F7 */
2694   {
2695     { "testQ",  { Ev, Iv }, 0 },
2696     { "testQ",  { Ev, Iv }, 0 },
2697     { "notQ",   { Evh1 }, 0 },
2698     { "negQ",   { Evh1 }, 0 },
2699     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
2700     { "imulQ",  { Ev }, 0 },
2701     { "divQ",   { Ev }, 0 },
2702     { "idivQ",  { Ev }, 0 },
2703   },
2704   /* REG_FE */
2705   {
2706     { "incA",   { Ebh1 }, 0 },
2707     { "decA",   { Ebh1 }, 0 },
2708   },
2709   /* REG_FF */
2710   {
2711     { "incQ",   { Evh1 }, 0 },
2712     { "decQ",   { Evh1 }, 0 },
2713     { "call{@|}", { NOTRACK, indirEv, BND }, 0 },
2714     { MOD_TABLE (MOD_FF_REG_3) },
2715     { "jmp{@|}", { NOTRACK, indirEv, BND }, 0 },
2716     { MOD_TABLE (MOD_FF_REG_5) },
2717     { "push{P|}", { stackEv }, 0 },
2718     { Bad_Opcode },
2719   },
2720   /* REG_0F00 */
2721   {
2722     { "sldtD",  { Sv }, 0 },
2723     { "strD",   { Sv }, 0 },
2724     { "lldt",   { Ew }, 0 },
2725     { "ltr",    { Ew }, 0 },
2726     { "verr",   { Ew }, 0 },
2727     { "verw",   { Ew }, 0 },
2728     { Bad_Opcode },
2729     { Bad_Opcode },
2730   },
2731   /* REG_0F01 */
2732   {
2733     { MOD_TABLE (MOD_0F01_REG_0) },
2734     { MOD_TABLE (MOD_0F01_REG_1) },
2735     { MOD_TABLE (MOD_0F01_REG_2) },
2736     { MOD_TABLE (MOD_0F01_REG_3) },
2737     { "smswD",  { Sv }, 0 },
2738     { MOD_TABLE (MOD_0F01_REG_5) },
2739     { "lmsw",   { Ew }, 0 },
2740     { MOD_TABLE (MOD_0F01_REG_7) },
2741   },
2742   /* REG_0F0D */
2743   {
2744     { "prefetch",       { Mb }, 0 },
2745     { "prefetchw",      { Mb }, 0 },
2746     { "prefetchwt1",    { Mb }, 0 },
2747     { "prefetch",       { Mb }, 0 },
2748     { "prefetch",       { Mb }, 0 },
2749     { "prefetch",       { Mb }, 0 },
2750     { "prefetch",       { Mb }, 0 },
2751     { "prefetch",       { Mb }, 0 },
2752   },
2753   /* REG_0F18 */
2754   {
2755     { MOD_TABLE (MOD_0F18_REG_0) },
2756     { MOD_TABLE (MOD_0F18_REG_1) },
2757     { MOD_TABLE (MOD_0F18_REG_2) },
2758     { MOD_TABLE (MOD_0F18_REG_3) },
2759     { "nopQ",           { Ev }, 0 },
2760     { "nopQ",           { Ev }, 0 },
2761     { MOD_TABLE (MOD_0F18_REG_6) },
2762     { MOD_TABLE (MOD_0F18_REG_7) },
2763   },
2764   /* REG_0F1C_P_0_MOD_0 */
2765   {
2766     { "cldemote",       { Mb }, 0 },
2767     { "nopQ",           { Ev }, 0 },
2768     { "nopQ",           { Ev }, 0 },
2769     { "nopQ",           { Ev }, 0 },
2770     { "nopQ",           { Ev }, 0 },
2771     { "nopQ",           { Ev }, 0 },
2772     { "nopQ",           { Ev }, 0 },
2773     { "nopQ",           { Ev }, 0 },
2774   },
2775   /* REG_0F1E_P_1_MOD_3 */
2776   {
2777     { "nopQ",           { Ev }, PREFIX_IGNORED },
2778     { "rdsspK",         { Edq }, 0 },
2779     { "nopQ",           { Ev }, PREFIX_IGNORED },
2780     { "nopQ",           { Ev }, PREFIX_IGNORED },
2781     { "nopQ",           { Ev }, PREFIX_IGNORED },
2782     { "nopQ",           { Ev }, PREFIX_IGNORED },
2783     { "nopQ",           { Ev }, PREFIX_IGNORED },
2784     { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) },
2785   },
2786   /* REG_0F38D8_PREFIX_1 */
2787   {
2788     { "aesencwide128kl",        { M }, 0 },
2789     { "aesdecwide128kl",        { M }, 0 },
2790     { "aesencwide256kl",        { M }, 0 },
2791     { "aesdecwide256kl",        { M }, 0 },
2792   },
2793   /* REG_0F3A0F_PREFIX_1_MOD_3 */
2794   {
2795     { RM_TABLE (RM_0F3A0F_P_1_MOD_3_REG_0) },
2796   },
2797   /* REG_0F71_MOD_0 */
2798   {
2799     { Bad_Opcode },
2800     { Bad_Opcode },
2801     { "psrlw",          { MS, Ib }, PREFIX_OPCODE },
2802     { Bad_Opcode },
2803     { "psraw",          { MS, Ib }, PREFIX_OPCODE },
2804     { Bad_Opcode },
2805     { "psllw",          { MS, Ib }, PREFIX_OPCODE },
2806   },
2807   /* REG_0F72_MOD_0 */
2808   {
2809     { Bad_Opcode },
2810     { Bad_Opcode },
2811     { "psrld",          { MS, Ib }, PREFIX_OPCODE },
2812     { Bad_Opcode },
2813     { "psrad",          { MS, Ib }, PREFIX_OPCODE },
2814     { Bad_Opcode },
2815     { "pslld",          { MS, Ib }, PREFIX_OPCODE },
2816   },
2817   /* REG_0F73_MOD_0 */
2818   {
2819     { Bad_Opcode },
2820     { Bad_Opcode },
2821     { "psrlq",          { MS, Ib }, PREFIX_OPCODE },
2822     { "psrldq",         { XS, Ib }, PREFIX_DATA },
2823     { Bad_Opcode },
2824     { Bad_Opcode },
2825     { "psllq",          { MS, Ib }, PREFIX_OPCODE },
2826     { "pslldq",         { XS, Ib }, PREFIX_DATA },
2827   },
2828   /* REG_0FA6 */
2829   {
2830     { "montmul",        { { OP_0f07, 0 } }, 0 },
2831     { "xsha1",          { { OP_0f07, 0 } }, 0 },
2832     { "xsha256",        { { OP_0f07, 0 } }, 0 },
2833   },
2834   /* REG_0FA7 */
2835   {
2836     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
2837     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
2838     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
2839     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
2840     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
2841     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
2842   },
2843   /* REG_0FAE */
2844   {
2845     { MOD_TABLE (MOD_0FAE_REG_0) },
2846     { MOD_TABLE (MOD_0FAE_REG_1) },
2847     { MOD_TABLE (MOD_0FAE_REG_2) },
2848     { MOD_TABLE (MOD_0FAE_REG_3) },
2849     { MOD_TABLE (MOD_0FAE_REG_4) },
2850     { MOD_TABLE (MOD_0FAE_REG_5) },
2851     { MOD_TABLE (MOD_0FAE_REG_6) },
2852     { MOD_TABLE (MOD_0FAE_REG_7) },
2853   },
2854   /* REG_0FBA */
2855   {
2856     { Bad_Opcode },
2857     { Bad_Opcode },
2858     { Bad_Opcode },
2859     { Bad_Opcode },
2860     { "btQ",    { Ev, Ib }, 0 },
2861     { "btsQ",   { Evh1, Ib }, 0 },
2862     { "btrQ",   { Evh1, Ib }, 0 },
2863     { "btcQ",   { Evh1, Ib }, 0 },
2864   },
2865   /* REG_0FC7 */
2866   {
2867     { Bad_Opcode },
2868     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
2869     { Bad_Opcode },
2870     { MOD_TABLE (MOD_0FC7_REG_3) },
2871     { MOD_TABLE (MOD_0FC7_REG_4) },
2872     { MOD_TABLE (MOD_0FC7_REG_5) },
2873     { MOD_TABLE (MOD_0FC7_REG_6) },
2874     { MOD_TABLE (MOD_0FC7_REG_7) },
2875   },
2876   /* REG_VEX_0F71_M_0 */
2877   {
2878     { Bad_Opcode },
2879     { Bad_Opcode },
2880     { "vpsrlw",         { Vex, XS, Ib }, PREFIX_DATA },
2881     { Bad_Opcode },
2882     { "vpsraw",         { Vex, XS, Ib }, PREFIX_DATA },
2883     { Bad_Opcode },
2884     { "vpsllw",         { Vex, XS, Ib }, PREFIX_DATA },
2885   },
2886   /* REG_VEX_0F72_M_0 */
2887   {
2888     { Bad_Opcode },
2889     { Bad_Opcode },
2890     { "vpsrld",         { Vex, XS, Ib }, PREFIX_DATA },
2891     { Bad_Opcode },
2892     { "vpsrad",         { Vex, XS, Ib }, PREFIX_DATA },
2893     { Bad_Opcode },
2894     { "vpslld",         { Vex, XS, Ib }, PREFIX_DATA },
2895   },
2896   /* REG_VEX_0F73_M_0 */
2897   {
2898     { Bad_Opcode },
2899     { Bad_Opcode },
2900     { "vpsrlq",         { Vex, XS, Ib }, PREFIX_DATA },
2901     { "vpsrldq",        { Vex, XS, Ib }, PREFIX_DATA },
2902     { Bad_Opcode },
2903     { Bad_Opcode },
2904     { "vpsllq",         { Vex, XS, Ib }, PREFIX_DATA },
2905     { "vpslldq",        { Vex, XS, Ib }, PREFIX_DATA },
2906   },
2907   /* REG_VEX_0FAE */
2908   {
2909     { Bad_Opcode },
2910     { Bad_Opcode },
2911     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
2912     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
2913   },
2914   /* REG_VEX_0F3849_X86_64_P_0_W_0_M_1 */
2915   {
2916     { RM_TABLE (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0) },
2917   },
2918   /* REG_VEX_0F38F3_L_0 */
2919   {
2920     { Bad_Opcode },
2921     { "blsrS",          { VexGdq, Edq }, PREFIX_OPCODE },
2922     { "blsmskS",        { VexGdq, Edq }, PREFIX_OPCODE },
2923     { "blsiS",          { VexGdq, Edq }, PREFIX_OPCODE },
2924   },
2925   /* REG_XOP_09_01_L_0 */
2926   {
2927     { Bad_Opcode },
2928     { "blcfill",        { VexGdq, Edq }, 0 },
2929     { "blsfill",        { VexGdq, Edq }, 0 },
2930     { "blcs",   { VexGdq, Edq }, 0 },
2931     { "tzmsk",  { VexGdq, Edq }, 0 },
2932     { "blcic",  { VexGdq, Edq }, 0 },
2933     { "blsic",  { VexGdq, Edq }, 0 },
2934     { "t1mskc", { VexGdq, Edq }, 0 },
2935   },
2936   /* REG_XOP_09_02_L_0 */
2937   {
2938     { Bad_Opcode },
2939     { "blcmsk", { VexGdq, Edq }, 0 },
2940     { Bad_Opcode },
2941     { Bad_Opcode },
2942     { Bad_Opcode },
2943     { Bad_Opcode },
2944     { "blci",   { VexGdq, Edq }, 0 },
2945   },
2946   /* REG_XOP_09_12_M_1_L_0 */
2947   {
2948     { "llwpcb", { Edq }, 0 },
2949     { "slwpcb", { Edq }, 0 },
2950   },
2951   /* REG_XOP_0A_12_L_0 */
2952   {
2953     { "lwpins", { VexGdq, Ed, Id }, 0 },
2954     { "lwpval", { VexGdq, Ed, Id }, 0 },
2955   },
2956
2957 #include "i386-dis-evex-reg.h"
2958 };
2959
2960 static const struct dis386 prefix_table[][4] = {
2961   /* PREFIX_90 */
2962   {
2963     { "xchgS", { { NOP_Fixup, 0 }, { NOP_Fixup, 1 } }, 0 },
2964     { "pause", { XX }, 0 },
2965     { "xchgS", { { NOP_Fixup, 0 }, { NOP_Fixup, 1 } }, 0 },
2966     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
2967   },
2968
2969   /* PREFIX_0F01_REG_0_MOD_3_RM_6 */
2970   {
2971     { "wrmsrns",        { Skip_MODRM }, 0 },
2972     { X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_6_P_1) },
2973     { Bad_Opcode },
2974     { X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_6_P_3) },
2975   },
2976
2977   /* PREFIX_0F01_REG_1_RM_4 */
2978   {
2979     { Bad_Opcode },
2980     { Bad_Opcode },
2981     { "tdcall",         { Skip_MODRM }, 0 },
2982     { Bad_Opcode },
2983   },
2984
2985   /* PREFIX_0F01_REG_1_RM_5 */
2986   {
2987     { Bad_Opcode },
2988     { Bad_Opcode },
2989     { X86_64_TABLE (X86_64_0F01_REG_1_RM_5_PREFIX_2) },
2990     { Bad_Opcode },
2991   },
2992
2993   /* PREFIX_0F01_REG_1_RM_6 */
2994   {
2995     { Bad_Opcode },
2996     { Bad_Opcode },
2997     { X86_64_TABLE (X86_64_0F01_REG_1_RM_6_PREFIX_2) },
2998     { Bad_Opcode },
2999   },
3000
3001   /* PREFIX_0F01_REG_1_RM_7 */
3002   {
3003     { "encls",          { Skip_MODRM }, 0 },
3004     { Bad_Opcode },
3005     { X86_64_TABLE (X86_64_0F01_REG_1_RM_7_PREFIX_2) },
3006     { Bad_Opcode },
3007   },
3008
3009   /* PREFIX_0F01_REG_3_RM_1 */
3010   {
3011     { "vmmcall",        { Skip_MODRM }, 0 },
3012     { "vmgexit",        { Skip_MODRM }, 0 },
3013     { Bad_Opcode },
3014     { "vmgexit",        { Skip_MODRM }, 0 },
3015   },
3016
3017   /* PREFIX_0F01_REG_5_MOD_0 */
3018   {
3019     { Bad_Opcode },
3020     { "rstorssp",       { Mq }, PREFIX_OPCODE },
3021   },
3022
3023   /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3024   {
3025     { "serialize",      { Skip_MODRM }, PREFIX_OPCODE },
3026     { "setssbsy",       { Skip_MODRM }, PREFIX_OPCODE },
3027     { Bad_Opcode },
3028     { "xsusldtrk",      { Skip_MODRM }, PREFIX_OPCODE },
3029   },
3030
3031   /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
3032   {
3033     { Bad_Opcode },
3034     { Bad_Opcode },
3035     { Bad_Opcode },
3036     { "xresldtrk",     { Skip_MODRM }, PREFIX_OPCODE },
3037   },
3038
3039   /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3040   {
3041     { Bad_Opcode },
3042     { "saveprevssp",    { Skip_MODRM }, PREFIX_OPCODE },
3043   },
3044
3045   /* PREFIX_0F01_REG_5_MOD_3_RM_4 */
3046   {
3047     { Bad_Opcode },
3048     { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1) },
3049   },
3050
3051   /* PREFIX_0F01_REG_5_MOD_3_RM_5 */
3052   {
3053     { Bad_Opcode },
3054     { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1) },
3055   },
3056
3057   /* PREFIX_0F01_REG_5_MOD_3_RM_6 */
3058   {
3059     { "rdpkru", { Skip_MODRM }, 0 },
3060     { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1) },
3061   },
3062
3063   /* PREFIX_0F01_REG_5_MOD_3_RM_7 */
3064   {
3065     { "wrpkru", { Skip_MODRM }, 0 },
3066     { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1) },
3067   },
3068
3069   /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3070   {
3071     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
3072     { "mcommit",        { Skip_MODRM }, 0 },
3073   },
3074
3075   /* PREFIX_0F01_REG_7_MOD_3_RM_6 */
3076   {
3077     { "invlpgb",        { Skip_MODRM }, 0 },
3078     { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1) },
3079     { Bad_Opcode },
3080     { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3) },
3081   },
3082
3083   /* PREFIX_0F01_REG_7_MOD_3_RM_7 */
3084   {
3085     { "tlbsync",        { Skip_MODRM }, 0 },
3086     { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1) },
3087     { Bad_Opcode },
3088     { "pvalidate",      { Skip_MODRM }, 0 },
3089   },
3090
3091   /* PREFIX_0F09 */
3092   {
3093     { "wbinvd",   { XX }, 0 },
3094     { "wbnoinvd", { XX }, 0 },
3095   },
3096
3097   /* PREFIX_0F10 */
3098   {
3099     { "movups", { XM, EXx }, PREFIX_OPCODE },
3100     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3101     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3102     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3103   },
3104
3105   /* PREFIX_0F11 */
3106   {
3107     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3108     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3109     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3110     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3111   },
3112
3113   /* PREFIX_0F12 */
3114   {
3115     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3116     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3117     { MOD_TABLE (MOD_0F12_PREFIX_2) },
3118     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3119   },
3120
3121   /* PREFIX_0F16 */
3122   {
3123     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3124     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3125     { MOD_TABLE (MOD_0F16_PREFIX_2) },
3126   },
3127
3128   /* PREFIX_0F18_REG_6_MOD_0_X86_64 */
3129   {
3130     { "prefetchit1",    { { PREFETCHI_Fixup, b_mode } }, 0 },
3131     { "nopQ",           { Ev }, 0 },
3132     { "nopQ",           { Ev }, 0 },
3133     { "nopQ",           { Ev }, 0 },
3134   },
3135
3136   /* PREFIX_0F18_REG_7_MOD_0_X86_64 */
3137   {
3138     { "prefetchit0",    { { PREFETCHI_Fixup, b_mode } }, 0 },
3139     { "nopQ",           { Ev }, 0 },
3140     { "nopQ",           { Ev }, 0 },
3141     { "nopQ",           { Ev }, 0 },
3142   },
3143
3144   /* PREFIX_0F1A */
3145   {
3146     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3147     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3148     { "bndmov", { Gbnd, Ebnd }, 0 },
3149     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3150   },
3151
3152   /* PREFIX_0F1B */
3153   {
3154     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3155     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3156     { "bndmov", { EbndS, Gbnd }, 0 },
3157     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3158   },
3159
3160   /* PREFIX_0F1C */
3161   {
3162     { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3163     { "nopQ",   { Ev }, PREFIX_IGNORED },
3164     { "nopQ",   { Ev }, 0 },
3165     { "nopQ",   { Ev }, PREFIX_IGNORED },
3166   },
3167
3168   /* PREFIX_0F1E */
3169   {
3170     { "nopQ",   { Ev }, 0 },
3171     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3172     { "nopQ",   { Ev }, 0 },
3173     { NULL,     { XX }, PREFIX_IGNORED },
3174   },
3175
3176   /* PREFIX_0F2A */
3177   {
3178     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3179     { "cvtsi2ss{%LQ|}", { XM, Edq }, PREFIX_OPCODE },
3180     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3181     { "cvtsi2sd{%LQ|}", { XM, Edq }, 0 },
3182   },
3183
3184   /* PREFIX_0F2B */
3185   {
3186     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3187     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3188     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3189     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3190   },
3191
3192   /* PREFIX_0F2C */
3193   {
3194     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3195     { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
3196     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3197     { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3198   },
3199
3200   /* PREFIX_0F2D */
3201   {
3202     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3203     { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
3204     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3205     { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3206   },
3207
3208   /* PREFIX_0F2E */
3209   {
3210     { "ucomiss",{ XM, EXd }, 0 },
3211     { Bad_Opcode },
3212     { "ucomisd",{ XM, EXq }, 0 },
3213   },
3214
3215   /* PREFIX_0F2F */
3216   {
3217     { "comiss", { XM, EXd }, 0 },
3218     { Bad_Opcode },
3219     { "comisd", { XM, EXq }, 0 },
3220   },
3221
3222   /* PREFIX_0F51 */
3223   {
3224     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3225     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3226     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3227     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3228   },
3229
3230   /* PREFIX_0F52 */
3231   {
3232     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3233     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3234   },
3235
3236   /* PREFIX_0F53 */
3237   {
3238     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3239     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3240   },
3241
3242   /* PREFIX_0F58 */
3243   {
3244     { "addps", { XM, EXx }, PREFIX_OPCODE },
3245     { "addss", { XM, EXd }, PREFIX_OPCODE },
3246     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3247     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3248   },
3249
3250   /* PREFIX_0F59 */
3251   {
3252     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3253     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3254     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3255     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3256   },
3257
3258   /* PREFIX_0F5A */
3259   {
3260     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3261     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3262     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3263     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3264   },
3265
3266   /* PREFIX_0F5B */
3267   {
3268     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3269     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3270     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3271   },
3272
3273   /* PREFIX_0F5C */
3274   {
3275     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3276     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3277     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3278     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3279   },
3280
3281   /* PREFIX_0F5D */
3282   {
3283     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3284     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3285     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3286     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3287   },
3288
3289   /* PREFIX_0F5E */
3290   {
3291     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3292     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3293     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3294     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3295   },
3296
3297   /* PREFIX_0F5F */
3298   {
3299     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3300     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3301     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3302     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3303   },
3304
3305   /* PREFIX_0F60 */
3306   {
3307     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3308     { Bad_Opcode },
3309     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3310   },
3311
3312   /* PREFIX_0F61 */
3313   {
3314     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3315     { Bad_Opcode },
3316     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3317   },
3318
3319   /* PREFIX_0F62 */
3320   {
3321     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3322     { Bad_Opcode },
3323     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3324   },
3325
3326   /* PREFIX_0F6F */
3327   {
3328     { "movq",   { MX, EM }, PREFIX_OPCODE },
3329     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3330     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3331   },
3332
3333   /* PREFIX_0F70 */
3334   {
3335     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3336     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3337     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3338     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3339   },
3340
3341   /* PREFIX_0F78 */
3342   {
3343     {"vmread",  { Em, Gm }, 0 },
3344     { Bad_Opcode },
3345     {"extrq",   { XS, Ib, Ib }, 0 },
3346     {"insertq", { XM, XS, Ib, Ib }, 0 },
3347   },
3348
3349   /* PREFIX_0F79 */
3350   {
3351     {"vmwrite", { Gm, Em }, 0 },
3352     { Bad_Opcode },
3353     {"extrq",   { XM, XS }, 0 },
3354     {"insertq", { XM, XS }, 0 },
3355   },
3356
3357   /* PREFIX_0F7C */
3358   {
3359     { Bad_Opcode },
3360     { Bad_Opcode },
3361     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3362     { "haddps", { XM, EXx }, PREFIX_OPCODE },
3363   },
3364
3365   /* PREFIX_0F7D */
3366   {
3367     { Bad_Opcode },
3368     { Bad_Opcode },
3369     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3370     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3371   },
3372
3373   /* PREFIX_0F7E */
3374   {
3375     { "movK",   { Edq, MX }, PREFIX_OPCODE },
3376     { "movq",   { XM, EXq }, PREFIX_OPCODE },
3377     { "movK",   { Edq, XM }, PREFIX_OPCODE },
3378   },
3379
3380   /* PREFIX_0F7F */
3381   {
3382     { "movq",   { EMS, MX }, PREFIX_OPCODE },
3383     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3384     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3385   },
3386
3387   /* PREFIX_0FAE_REG_0_MOD_3 */
3388   {
3389     { Bad_Opcode },
3390     { "rdfsbase", { Ev }, 0 },
3391   },
3392
3393   /* PREFIX_0FAE_REG_1_MOD_3 */
3394   {
3395     { Bad_Opcode },
3396     { "rdgsbase", { Ev }, 0 },
3397   },
3398
3399   /* PREFIX_0FAE_REG_2_MOD_3 */
3400   {
3401     { Bad_Opcode },
3402     { "wrfsbase", { Ev }, 0 },
3403   },
3404
3405   /* PREFIX_0FAE_REG_3_MOD_3 */
3406   {
3407     { Bad_Opcode },
3408     { "wrgsbase", { Ev }, 0 },
3409   },
3410
3411   /* PREFIX_0FAE_REG_4_MOD_0 */
3412   {
3413     { "xsave",  { FXSAVE }, 0 },
3414     { "ptwrite{%LQ|}", { Edq }, 0 },
3415   },
3416
3417   /* PREFIX_0FAE_REG_4_MOD_3 */
3418   {
3419     { Bad_Opcode },
3420     { "ptwrite{%LQ|}", { Edq }, 0 },
3421   },
3422
3423   /* PREFIX_0FAE_REG_5_MOD_3 */
3424   {
3425     { "lfence",         { Skip_MODRM }, 0 },
3426     { "incsspK",        { Edq }, PREFIX_OPCODE },
3427   },
3428
3429   /* PREFIX_0FAE_REG_6_MOD_0 */
3430   {
3431     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE },
3432     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
3433     { "clwb",   { Mb }, PREFIX_OPCODE },
3434   },
3435
3436   /* PREFIX_0FAE_REG_6_MOD_3 */
3437   {
3438     { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) },
3439     { "umonitor",       { Eva }, PREFIX_OPCODE },
3440     { "tpause", { Edq }, PREFIX_OPCODE },
3441     { "umwait", { Edq }, PREFIX_OPCODE },
3442   },
3443
3444   /* PREFIX_0FAE_REG_7_MOD_0 */
3445   {
3446     { "clflush",        { Mb }, 0 },
3447     { Bad_Opcode },
3448     { "clflushopt",     { Mb }, 0 },
3449   },
3450
3451   /* PREFIX_0FB8 */
3452   {
3453     { Bad_Opcode },
3454     { "popcntS", { Gv, Ev }, 0 },
3455   },
3456
3457   /* PREFIX_0FBC */
3458   {
3459     { "bsfS",   { Gv, Ev }, 0 },
3460     { "tzcntS", { Gv, Ev }, 0 },
3461     { "bsfS",   { Gv, Ev }, 0 },
3462   },
3463
3464   /* PREFIX_0FBD */
3465   {
3466     { "bsrS",   { Gv, Ev }, 0 },
3467     { "lzcntS", { Gv, Ev }, 0 },
3468     { "bsrS",   { Gv, Ev }, 0 },
3469   },
3470
3471   /* PREFIX_0FC2 */
3472   {
3473     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
3474     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
3475     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
3476     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
3477   },
3478
3479   /* PREFIX_0FC7_REG_6_MOD_0 */
3480   {
3481     { "vmptrld",{ Mq }, 0 },
3482     { "vmxon",  { Mq }, 0 },
3483     { "vmclear",{ Mq }, 0 },
3484   },
3485
3486   /* PREFIX_0FC7_REG_6_MOD_3 */
3487   {
3488     { "rdrand", { Ev }, 0 },
3489     { X86_64_TABLE (X86_64_0FC7_REG_6_MOD_3_PREFIX_1) },
3490     { "rdrand", { Ev }, 0 }
3491   },
3492
3493   /* PREFIX_0FC7_REG_7_MOD_3 */
3494   {
3495     { "rdseed", { Ev }, 0 },
3496     { "rdpid",  { Em }, 0 },
3497     { "rdseed", { Ev }, 0 },
3498   },
3499
3500   /* PREFIX_0FD0 */
3501   {
3502     { Bad_Opcode },
3503     { Bad_Opcode },
3504     { "addsubpd", { XM, EXx }, 0 },
3505     { "addsubps", { XM, EXx }, 0 },
3506   },
3507
3508   /* PREFIX_0FD6 */
3509   {
3510     { Bad_Opcode },
3511     { "movq2dq",{ XM, MS }, 0 },
3512     { "movq",   { EXqS, XM }, 0 },
3513     { "movdq2q",{ MX, XS }, 0 },
3514   },
3515
3516   /* PREFIX_0FE6 */
3517   {
3518     { Bad_Opcode },
3519     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
3520     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
3521     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
3522   },
3523
3524   /* PREFIX_0FE7 */
3525   {
3526     { "movntq", { Mq, MX }, PREFIX_OPCODE },
3527     { Bad_Opcode },
3528     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
3529   },
3530
3531   /* PREFIX_0FF0 */
3532   {
3533     { Bad_Opcode },
3534     { Bad_Opcode },
3535     { Bad_Opcode },
3536     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
3537   },
3538
3539   /* PREFIX_0FF7 */
3540   {
3541     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
3542     { Bad_Opcode },
3543     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
3544   },
3545
3546   /* PREFIX_0F38D8 */
3547   {
3548     { Bad_Opcode },
3549     { REG_TABLE (REG_0F38D8_PREFIX_1) },
3550   },
3551
3552   /* PREFIX_0F38DC */
3553   {
3554     { Bad_Opcode },
3555     { MOD_TABLE (MOD_0F38DC_PREFIX_1) },
3556     { "aesenc", { XM, EXx }, 0 },
3557   },
3558
3559   /* PREFIX_0F38DD */
3560   {
3561     { Bad_Opcode },
3562     { MOD_TABLE (MOD_0F38DD_PREFIX_1) },
3563     { "aesenclast", { XM, EXx }, 0 },
3564   },
3565
3566   /* PREFIX_0F38DE */
3567   {
3568     { Bad_Opcode },
3569     { MOD_TABLE (MOD_0F38DE_PREFIX_1) },
3570     { "aesdec", { XM, EXx }, 0 },
3571   },
3572
3573   /* PREFIX_0F38DF */
3574   {
3575     { Bad_Opcode },
3576     { MOD_TABLE (MOD_0F38DF_PREFIX_1) },
3577     { "aesdeclast", { XM, EXx }, 0 },
3578   },
3579
3580   /* PREFIX_0F38F0 */
3581   {
3582     { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3583     { Bad_Opcode },
3584     { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3585     { "crc32A", { Gdq, Eb }, PREFIX_OPCODE },
3586   },
3587
3588   /* PREFIX_0F38F1 */
3589   {
3590     { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3591     { Bad_Opcode },
3592     { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3593     { "crc32Q", { Gdq, Ev }, PREFIX_OPCODE },
3594   },
3595
3596   /* PREFIX_0F38F6 */
3597   {
3598     { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
3599     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
3600     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
3601     { Bad_Opcode },
3602   },
3603
3604   /* PREFIX_0F38F8 */
3605   {
3606     { Bad_Opcode },
3607     { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
3608     { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
3609     { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
3610   },
3611   /* PREFIX_0F38FA */
3612   {
3613     { Bad_Opcode },
3614     { MOD_TABLE (MOD_0F38FA_PREFIX_1) },
3615   },
3616
3617   /* PREFIX_0F38FB */
3618   {
3619     { Bad_Opcode },
3620     { MOD_TABLE (MOD_0F38FB_PREFIX_1) },
3621   },
3622
3623   /* PREFIX_0F3A0F */
3624   {
3625     { Bad_Opcode },
3626     { MOD_TABLE (MOD_0F3A0F_PREFIX_1)},
3627   },
3628
3629   /* PREFIX_VEX_0F10 */
3630   {
3631     { "%XEvmovupX",     { XM, EXEvexXNoBcst }, 0 },
3632     { "%XEvmovs%XS",    { XMScalar, VexScalarR, EXd }, 0 },
3633     { "%XEvmovupX",     { XM, EXEvexXNoBcst }, 0 },
3634     { "%XEvmovs%XD",    { XMScalar, VexScalarR, EXq }, 0 },
3635   },
3636
3637   /* PREFIX_VEX_0F11 */
3638   {
3639     { "%XEvmovupX",     { EXxS, XM }, 0 },
3640     { "%XEvmovs%XS",    { EXdS, VexScalarR, XMScalar }, 0 },
3641     { "%XEvmovupX",     { EXxS, XM }, 0 },
3642     { "%XEvmovs%XD",    { EXqS, VexScalarR, XMScalar }, 0 },
3643   },
3644
3645   /* PREFIX_VEX_0F12 */
3646   {
3647     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
3648     { "%XEvmov%XSldup", { XM, EXEvexXNoBcst }, 0 },
3649     { MOD_TABLE (MOD_VEX_0F12_PREFIX_2) },
3650     { "%XEvmov%XDdup",  { XM, EXymmq }, 0 },
3651   },
3652
3653   /* PREFIX_VEX_0F16 */
3654   {
3655     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
3656     { "%XEvmov%XShdup", { XM, EXEvexXNoBcst }, 0 },
3657     { MOD_TABLE (MOD_VEX_0F16_PREFIX_2) },
3658   },
3659
3660   /* PREFIX_VEX_0F2A */
3661   {
3662     { Bad_Opcode },
3663     { "%XEvcvtsi2ss{%LQ|}",     { XMScalar, VexScalar, EXxEVexR, Edq }, 0 },
3664     { Bad_Opcode },
3665     { "%XEvcvtsi2sd{%LQ|}",     { XMScalar, VexScalar, EXxEVexR64, Edq }, 0 },
3666   },
3667
3668   /* PREFIX_VEX_0F2C */
3669   {
3670     { Bad_Opcode },
3671     { "%XEvcvttss2si",  { Gdq, EXd, EXxEVexS }, 0 },
3672     { Bad_Opcode },
3673     { "%XEvcvttsd2si",  { Gdq, EXq, EXxEVexS }, 0 },
3674   },
3675
3676   /* PREFIX_VEX_0F2D */
3677   {
3678     { Bad_Opcode },
3679     { "%XEvcvtss2si",   { Gdq, EXd, EXxEVexR }, 0 },
3680     { Bad_Opcode },
3681     { "%XEvcvtsd2si",   { Gdq, EXq, EXxEVexR }, 0 },
3682   },
3683
3684   /* PREFIX_VEX_0F2E */
3685   {
3686     { "%XEvucomisX",    { XMScalar, EXd, EXxEVexS }, 0 },
3687     { Bad_Opcode },
3688     { "%XEvucomisX",    { XMScalar, EXq, EXxEVexS }, 0 },
3689   },
3690
3691   /* PREFIX_VEX_0F2F */
3692   {
3693     { "%XEvcomisX",     { XMScalar, EXd, EXxEVexS }, 0 },
3694     { Bad_Opcode },
3695     { "%XEvcomisX",     { XMScalar, EXq, EXxEVexS }, 0 },
3696   },
3697
3698   /* PREFIX_VEX_0F41_L_1_M_1_W_0 */
3699   {
3700     { "kandw",          { MaskG, MaskVex, MaskE }, 0 },
3701     { Bad_Opcode },
3702     { "kandb",          { MaskG, MaskVex, MaskE }, 0 },
3703   },
3704
3705   /* PREFIX_VEX_0F41_L_1_M_1_W_1 */
3706   {
3707     { "kandq",          { MaskG, MaskVex, MaskE }, 0 },
3708     { Bad_Opcode },
3709     { "kandd",          { MaskG, MaskVex, MaskE }, 0 },
3710   },
3711
3712   /* PREFIX_VEX_0F42_L_1_M_1_W_0 */
3713   {
3714     { "kandnw",         { MaskG, MaskVex, MaskE }, 0 },
3715     { Bad_Opcode },
3716     { "kandnb",         { MaskG, MaskVex, MaskE }, 0 },
3717   },
3718
3719   /* PREFIX_VEX_0F42_L_1_M_1_W_1 */
3720   {
3721     { "kandnq",         { MaskG, MaskVex, MaskE }, 0 },
3722     { Bad_Opcode },
3723     { "kandnd",         { MaskG, MaskVex, MaskE }, 0 },
3724   },
3725
3726   /* PREFIX_VEX_0F44_L_0_M_1_W_0 */
3727   {
3728     { "knotw",          { MaskG, MaskE }, 0 },
3729     { Bad_Opcode },
3730     { "knotb",          { MaskG, MaskE }, 0 },
3731   },
3732
3733   /* PREFIX_VEX_0F44_L_0_M_1_W_1 */
3734   {
3735     { "knotq",          { MaskG, MaskE }, 0 },
3736     { Bad_Opcode },
3737     { "knotd",          { MaskG, MaskE }, 0 },
3738   },
3739
3740   /* PREFIX_VEX_0F45_L_1_M_1_W_0 */
3741   {
3742     { "korw",       { MaskG, MaskVex, MaskE }, 0 },
3743     { Bad_Opcode },
3744     { "korb",       { MaskG, MaskVex, MaskE }, 0 },
3745   },
3746
3747   /* PREFIX_VEX_0F45_L_1_M_1_W_1 */
3748   {
3749     { "korq",       { MaskG, MaskVex, MaskE }, 0 },
3750     { Bad_Opcode },
3751     { "kord",       { MaskG, MaskVex, MaskE }, 0 },
3752   },
3753
3754   /* PREFIX_VEX_0F46_L_1_M_1_W_0 */
3755   {
3756     { "kxnorw",     { MaskG, MaskVex, MaskE }, 0 },
3757     { Bad_Opcode },
3758     { "kxnorb",     { MaskG, MaskVex, MaskE }, 0 },
3759   },
3760
3761   /* PREFIX_VEX_0F46_L_1_M_1_W_1 */
3762   {
3763     { "kxnorq",     { MaskG, MaskVex, MaskE }, 0 },
3764     { Bad_Opcode },
3765     { "kxnord",     { MaskG, MaskVex, MaskE }, 0 },
3766   },
3767
3768   /* PREFIX_VEX_0F47_L_1_M_1_W_0 */
3769   {
3770     { "kxorw",      { MaskG, MaskVex, MaskE }, 0 },
3771     { Bad_Opcode },
3772     { "kxorb",      { MaskG, MaskVex, MaskE }, 0 },
3773   },
3774
3775   /* PREFIX_VEX_0F47_L_1_M_1_W_1 */
3776   {
3777     { "kxorq",      { MaskG, MaskVex, MaskE }, 0 },
3778     { Bad_Opcode },
3779     { "kxord",      { MaskG, MaskVex, MaskE }, 0 },
3780   },
3781
3782   /* PREFIX_VEX_0F4A_L_1_M_1_W_0 */
3783   {
3784     { "kaddw",          { MaskG, MaskVex, MaskE }, 0 },
3785     { Bad_Opcode },
3786     { "kaddb",          { MaskG, MaskVex, MaskE }, 0 },
3787   },
3788
3789   /* PREFIX_VEX_0F4A_L_1_M_1_W_1 */
3790   {
3791     { "kaddq",          { MaskG, MaskVex, MaskE }, 0 },
3792     { Bad_Opcode },
3793     { "kaddd",          { MaskG, MaskVex, MaskE }, 0 },
3794   },
3795
3796   /* PREFIX_VEX_0F4B_L_1_M_1_W_0 */
3797   {
3798     { "kunpckwd",   { MaskG, MaskVex, MaskE }, 0 },
3799     { Bad_Opcode },
3800     { "kunpckbw",   { MaskG, MaskVex, MaskE }, 0 },
3801   },
3802
3803   /* PREFIX_VEX_0F4B_L_1_M_1_W_1 */
3804   {
3805     { "kunpckdq",   { MaskG, MaskVex, MaskE }, 0 },
3806   },
3807
3808   /* PREFIX_VEX_0F51 */
3809   {
3810     { "%XEvsqrtpX",     { XM, EXx, EXxEVexR }, 0 },
3811     { "%XEvsqrts%XS",   { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3812     { "%XEvsqrtpX",     { XM, EXx, EXxEVexR }, 0 },
3813     { "%XEvsqrts%XD",   { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3814   },
3815
3816   /* PREFIX_VEX_0F52 */
3817   {
3818     { "vrsqrtps",       { XM, EXx }, 0 },
3819     { "vrsqrtss",       { XMScalar, VexScalar, EXd }, 0 },
3820   },
3821
3822   /* PREFIX_VEX_0F53 */
3823   {
3824     { "vrcpps",         { XM, EXx }, 0 },
3825     { "vrcpss",         { XMScalar, VexScalar, EXd }, 0 },
3826   },
3827
3828   /* PREFIX_VEX_0F58 */
3829   {
3830     { "%XEvaddpX",      { XM, Vex, EXx, EXxEVexR }, 0 },
3831     { "%XEvadds%XS",    { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3832     { "%XEvaddpX",      { XM, Vex, EXx, EXxEVexR }, 0 },
3833     { "%XEvadds%XD",    { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3834   },
3835
3836   /* PREFIX_VEX_0F59 */
3837   {
3838     { "%XEvmulpX",      { XM, Vex, EXx, EXxEVexR }, 0 },
3839     { "%XEvmuls%XS",    { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3840     { "%XEvmulpX",      { XM, Vex, EXx, EXxEVexR }, 0 },
3841     { "%XEvmuls%XD",    { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3842   },
3843
3844   /* PREFIX_VEX_0F5A */
3845   {
3846     { "%XEvcvtp%XS2pd", { XM, EXEvexHalfBcstXmmq, EXxEVexS }, 0 },
3847     { "%XEvcvts%XS2sd", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
3848     { "%XEvcvtp%XD2ps%XY", { XMxmmq, EXx, EXxEVexR }, 0 },
3849     { "%XEvcvts%XD2ss", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3850   },
3851
3852   /* PREFIX_VEX_0F5B */
3853   {
3854     { "vcvtdq2ps",      { XM, EXx }, 0 },
3855     { "vcvttps2dq",     { XM, EXx }, 0 },
3856     { "vcvtps2dq",      { XM, EXx }, 0 },
3857   },
3858
3859   /* PREFIX_VEX_0F5C */
3860   {
3861     { "%XEvsubpX",      { XM, Vex, EXx, EXxEVexR }, 0 },
3862     { "%XEvsubs%XS",    { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3863     { "%XEvsubpX",      { XM, Vex, EXx, EXxEVexR }, 0 },
3864     { "%XEvsubs%XD",    { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3865   },
3866
3867   /* PREFIX_VEX_0F5D */
3868   {
3869     { "%XEvminpX",      { XM, Vex, EXx, EXxEVexS }, 0 },
3870     { "%XEvmins%XS",    { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
3871     { "%XEvminpX",      { XM, Vex, EXx, EXxEVexS }, 0 },
3872     { "%XEvmins%XD",    { XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
3873   },
3874
3875   /* PREFIX_VEX_0F5E */
3876   {
3877     { "%XEvdivpX",      { XM, Vex, EXx, EXxEVexR }, 0 },
3878     { "%XEvdivs%XS",    { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3879     { "%XEvdivpX",      { XM, Vex, EXx, EXxEVexR }, 0 },
3880     { "%XEvdivs%XD",    { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3881   },
3882
3883   /* PREFIX_VEX_0F5F */
3884   {
3885     { "%XEvmaxpX",      { XM, Vex, EXx, EXxEVexS }, 0 },
3886     { "%XEvmaxs%XS",    { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
3887     { "%XEvmaxpX",      { XM, Vex, EXx, EXxEVexS }, 0 },
3888     { "%XEvmaxs%XD",    { XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
3889   },
3890
3891   /* PREFIX_VEX_0F6F */
3892   {
3893     { Bad_Opcode },
3894     { "vmovdqu",        { XM, EXx }, 0 },
3895     { "vmovdqa",        { XM, EXx }, 0 },
3896   },
3897
3898   /* PREFIX_VEX_0F70 */
3899   {
3900     { Bad_Opcode },
3901     { "vpshufhw",       { XM, EXx, Ib }, 0 },
3902     { "vpshufd",        { XM, EXx, Ib }, 0 },
3903     { "vpshuflw",       { XM, EXx, Ib }, 0 },
3904   },
3905
3906   /* PREFIX_VEX_0F7C */
3907   {
3908     { Bad_Opcode },
3909     { Bad_Opcode },
3910     { "vhaddpd",        { XM, Vex, EXx }, 0 },
3911     { "vhaddps",        { XM, Vex, EXx }, 0 },
3912   },
3913
3914   /* PREFIX_VEX_0F7D */
3915   {
3916     { Bad_Opcode },
3917     { Bad_Opcode },
3918     { "vhsubpd",        { XM, Vex, EXx }, 0 },
3919     { "vhsubps",        { XM, Vex, EXx }, 0 },
3920   },
3921
3922   /* PREFIX_VEX_0F7E */
3923   {
3924     { Bad_Opcode },
3925     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
3926     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
3927   },
3928
3929   /* PREFIX_VEX_0F7F */
3930   {
3931     { Bad_Opcode },
3932     { "vmovdqu",        { EXxS, XM }, 0 },
3933     { "vmovdqa",        { EXxS, XM }, 0 },
3934   },
3935
3936   /* PREFIX_VEX_0F90_L_0_W_0 */
3937   {
3938     { "kmovw",          { MaskG, MaskE }, 0 },
3939     { Bad_Opcode },
3940     { "kmovb",          { MaskG, MaskBDE }, 0 },
3941   },
3942
3943   /* PREFIX_VEX_0F90_L_0_W_1 */
3944   {
3945     { "kmovq",          { MaskG, MaskE }, 0 },
3946     { Bad_Opcode },
3947     { "kmovd",          { MaskG, MaskBDE }, 0 },
3948   },
3949
3950   /* PREFIX_VEX_0F91_L_0_M_0_W_0 */
3951   {
3952     { "kmovw",          { Ew, MaskG }, 0 },
3953     { Bad_Opcode },
3954     { "kmovb",          { Eb, MaskG }, 0 },
3955   },
3956
3957   /* PREFIX_VEX_0F91_L_0_M_0_W_1 */
3958   {
3959     { "kmovq",          { Eq, MaskG }, 0 },
3960     { Bad_Opcode },
3961     { "kmovd",          { Ed, MaskG }, 0 },
3962   },
3963
3964   /* PREFIX_VEX_0F92_L_0_M_1_W_0 */
3965   {
3966     { "kmovw",          { MaskG, Edq }, 0 },
3967     { Bad_Opcode },
3968     { "kmovb",          { MaskG, Edq }, 0 },
3969     { "kmovd",          { MaskG, Edq }, 0 },
3970   },
3971
3972   /* PREFIX_VEX_0F92_L_0_M_1_W_1 */
3973   {
3974     { Bad_Opcode },
3975     { Bad_Opcode },
3976     { Bad_Opcode },
3977     { "kmovK",          { MaskG, Edq }, 0 },
3978   },
3979
3980   /* PREFIX_VEX_0F93_L_0_M_1_W_0 */
3981   {
3982     { "kmovw",          { Gdq, MaskE }, 0 },
3983     { Bad_Opcode },
3984     { "kmovb",          { Gdq, MaskE }, 0 },
3985     { "kmovd",          { Gdq, MaskE }, 0 },
3986   },
3987
3988   /* PREFIX_VEX_0F93_L_0_M_1_W_1 */
3989   {
3990     { Bad_Opcode },
3991     { Bad_Opcode },
3992     { Bad_Opcode },
3993     { "kmovK",          { Gdq, MaskE }, 0 },
3994   },
3995
3996   /* PREFIX_VEX_0F98_L_0_M_1_W_0 */
3997   {
3998     { "kortestw", { MaskG, MaskE }, 0 },
3999     { Bad_Opcode },
4000     { "kortestb", { MaskG, MaskE }, 0 },
4001   },
4002
4003   /* PREFIX_VEX_0F98_L_0_M_1_W_1 */
4004   {
4005     { "kortestq", { MaskG, MaskE }, 0 },
4006     { Bad_Opcode },
4007     { "kortestd", { MaskG, MaskE }, 0 },
4008   },
4009
4010   /* PREFIX_VEX_0F99_L_0_M_1_W_0 */
4011   {
4012     { "ktestw", { MaskG, MaskE }, 0 },
4013     { Bad_Opcode },
4014     { "ktestb", { MaskG, MaskE }, 0 },
4015   },
4016
4017   /* PREFIX_VEX_0F99_L_0_M_1_W_1 */
4018   {
4019     { "ktestq", { MaskG, MaskE }, 0 },
4020     { Bad_Opcode },
4021     { "ktestd", { MaskG, MaskE }, 0 },
4022   },
4023
4024   /* PREFIX_VEX_0FC2 */
4025   {
4026     { "vcmpps",         { XM, Vex, EXx, CMP }, 0 },
4027     { "vcmpss",         { XMScalar, VexScalar, EXd, CMP }, 0 },
4028     { "vcmppd",         { XM, Vex, EXx, CMP }, 0 },
4029     { "vcmpsd",         { XMScalar, VexScalar, EXq, CMP }, 0 },
4030   },
4031
4032   /* PREFIX_VEX_0FD0 */
4033   {
4034     { Bad_Opcode },
4035     { Bad_Opcode },
4036     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
4037     { "vaddsubps",      { XM, Vex, EXx }, 0 },
4038   },
4039
4040   /* PREFIX_VEX_0FE6 */
4041   {
4042     { Bad_Opcode },
4043     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
4044     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
4045     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
4046   },
4047
4048   /* PREFIX_VEX_0FF0 */
4049   {
4050     { Bad_Opcode },
4051     { Bad_Opcode },
4052     { Bad_Opcode },
4053     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
4054   },
4055
4056   /* PREFIX_VEX_0F3849_X86_64 */
4057   {
4058     { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_0) },
4059     { Bad_Opcode },
4060     { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_2) },
4061     { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_3) },
4062   },
4063
4064   /* PREFIX_VEX_0F384B_X86_64 */
4065   {
4066     { Bad_Opcode },
4067     { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_1) },
4068     { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_2) },
4069     { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_3) },
4070   },
4071
4072   /* PREFIX_VEX_0F3850_W_0 */
4073   {
4074     { "vpdpbuud",       { XM, Vex, EXx }, 0 },
4075     { "vpdpbsud",       { XM, Vex, EXx }, 0 },
4076     { "%XVvpdpbusd",    { XM, Vex, EXx }, 0 },
4077     { "vpdpbssd",       { XM, Vex, EXx }, 0 },
4078   },
4079
4080   /* PREFIX_VEX_0F3851_W_0 */
4081   {
4082     { "vpdpbuuds",      { XM, Vex, EXx }, 0 },
4083     { "vpdpbsuds",      { XM, Vex, EXx }, 0 },
4084     { "%XVvpdpbusds",   { XM, Vex, EXx }, 0 },
4085     { "vpdpbssds",      { XM, Vex, EXx }, 0 },
4086   },
4087   /* PREFIX_VEX_0F385C_X86_64 */
4088   {
4089     { Bad_Opcode },
4090     { VEX_W_TABLE (VEX_W_0F385C_X86_64_P_1) },
4091     { Bad_Opcode },
4092     { VEX_W_TABLE (VEX_W_0F385C_X86_64_P_3) },
4093   },
4094
4095   /* PREFIX_VEX_0F385E_X86_64 */
4096   {
4097     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_0) },
4098     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_1) },
4099     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_2) },
4100     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_3) },
4101   },
4102
4103   /* PREFIX_VEX_0F3872 */
4104   {
4105     { Bad_Opcode },
4106     { VEX_W_TABLE (VEX_W_0F3872_P_1) },
4107   },
4108
4109   /* PREFIX_VEX_0F38B0_W_0 */
4110   {
4111     { "vcvtneoph2ps", { XM, Mx }, 0 },
4112     { "vcvtneebf162ps", { XM, Mx }, 0 },
4113     { "vcvtneeph2ps", { XM, Mx }, 0 },
4114     { "vcvtneobf162ps", { XM, Mx }, 0 },
4115   },
4116
4117   /* PREFIX_VEX_0F38B1_W_0 */
4118   {
4119     { Bad_Opcode },
4120     { "vbcstnebf162ps", { XM, Mw }, 0 },
4121     { "vbcstnesh2ps", { XM, Mw }, 0 },
4122   },
4123
4124   /* PREFIX_VEX_0F38F5_L_0 */
4125   {
4126     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
4127     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
4128     { Bad_Opcode },
4129     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
4130   },
4131
4132   /* PREFIX_VEX_0F38F6_L_0 */
4133   {
4134     { Bad_Opcode },
4135     { Bad_Opcode },
4136     { Bad_Opcode },
4137     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
4138   },
4139
4140   /* PREFIX_VEX_0F38F7_L_0 */
4141   {
4142     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
4143     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
4144     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
4145     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
4146   },
4147
4148   /* PREFIX_VEX_0F3AF0_L_0 */
4149   {
4150     { Bad_Opcode },
4151     { Bad_Opcode },
4152     { Bad_Opcode },
4153     { "rorxS",          { Gdq, Edq, Ib }, 0 },
4154   },
4155
4156 #include "i386-dis-evex-prefix.h"
4157 };
4158
4159 static const struct dis386 x86_64_table[][2] = {
4160   /* X86_64_06 */
4161   {
4162     { "pushP", { es }, 0 },
4163   },
4164
4165   /* X86_64_07 */
4166   {
4167     { "popP", { es }, 0 },
4168   },
4169
4170   /* X86_64_0E */
4171   {
4172     { "pushP", { cs }, 0 },
4173   },
4174
4175   /* X86_64_16 */
4176   {
4177     { "pushP", { ss }, 0 },
4178   },
4179
4180   /* X86_64_17 */
4181   {
4182     { "popP", { ss }, 0 },
4183   },
4184
4185   /* X86_64_1E */
4186   {
4187     { "pushP", { ds }, 0 },
4188   },
4189
4190   /* X86_64_1F */
4191   {
4192     { "popP", { ds }, 0 },
4193   },
4194
4195   /* X86_64_27 */
4196   {
4197     { "daa", { XX }, 0 },
4198   },
4199
4200   /* X86_64_2F */
4201   {
4202     { "das", { XX }, 0 },
4203   },
4204
4205   /* X86_64_37 */
4206   {
4207     { "aaa", { XX }, 0 },
4208   },
4209
4210   /* X86_64_3F */
4211   {
4212     { "aas", { XX }, 0 },
4213   },
4214
4215   /* X86_64_60 */
4216   {
4217     { "pushaP", { XX }, 0 },
4218   },
4219
4220   /* X86_64_61 */
4221   {
4222     { "popaP", { XX }, 0 },
4223   },
4224
4225   /* X86_64_62 */
4226   {
4227     { MOD_TABLE (MOD_62_32BIT) },
4228     { EVEX_TABLE (EVEX_0F) },
4229   },
4230
4231   /* X86_64_63 */
4232   {
4233     { "arpl", { Ew, Gw }, 0 },
4234     { "movs", { Gv, { MOVSXD_Fixup, movsxd_mode } }, 0 },
4235   },
4236
4237   /* X86_64_6D */
4238   {
4239     { "ins{R|}", { Yzr, indirDX }, 0 },
4240     { "ins{G|}", { Yzr, indirDX }, 0 },
4241   },
4242
4243   /* X86_64_6F */
4244   {
4245     { "outs{R|}", { indirDXr, Xz }, 0 },
4246     { "outs{G|}", { indirDXr, Xz }, 0 },
4247   },
4248
4249   /* X86_64_82 */
4250   {
4251     /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
4252     { REG_TABLE (REG_80) },
4253   },
4254
4255   /* X86_64_9A */
4256   {
4257     { "{l|}call{P|}", { Ap }, 0 },
4258   },
4259
4260   /* X86_64_C2 */
4261   {
4262     { "retP",           { Iw, BND }, 0 },
4263     { "ret@",           { Iw, BND }, 0 },
4264   },
4265
4266   /* X86_64_C3 */
4267   {
4268     { "retP",           { BND }, 0 },
4269     { "ret@",           { BND }, 0 },
4270   },
4271
4272   /* X86_64_C4 */
4273   {
4274     { MOD_TABLE (MOD_C4_32BIT) },
4275     { VEX_C4_TABLE (VEX_0F) },
4276   },
4277
4278   /* X86_64_C5 */
4279   {
4280     { MOD_TABLE (MOD_C5_32BIT) },
4281     { VEX_C5_TABLE (VEX_0F) },
4282   },
4283
4284   /* X86_64_CE */
4285   {
4286     { "into", { XX }, 0 },
4287   },
4288
4289   /* X86_64_D4 */
4290   {
4291     { "aam", { Ib }, 0 },
4292   },
4293
4294   /* X86_64_D5 */
4295   {
4296     { "aad", { Ib }, 0 },
4297   },
4298
4299   /* X86_64_E8 */
4300   {
4301     { "callP",          { Jv, BND }, 0 },
4302     { "call@",          { Jv, BND }, 0 }
4303   },
4304
4305   /* X86_64_E9 */
4306   {
4307     { "jmpP",           { Jv, BND }, 0 },
4308     { "jmp@",           { Jv, BND }, 0 }
4309   },
4310
4311   /* X86_64_EA */
4312   {
4313     { "{l|}jmp{P|}", { Ap }, 0 },
4314   },
4315
4316   /* X86_64_0F01_REG_0 */
4317   {
4318     { "sgdt{Q|Q}", { M }, 0 },
4319     { "sgdt", { M }, 0 },
4320   },
4321
4322   /* X86_64_0F01_REG_0_MOD_3_RM_6_P_1 */
4323   {
4324     { Bad_Opcode },
4325     { "wrmsrlist",      { Skip_MODRM }, 0 },
4326   },
4327
4328   /* X86_64_0F01_REG_0_MOD_3_RM_6_P_3 */
4329   {
4330     { Bad_Opcode },
4331     { "rdmsrlist",      { Skip_MODRM }, 0 },
4332   },
4333
4334   /* X86_64_0F01_REG_1 */
4335   {
4336     { "sidt{Q|Q}", { M }, 0 },
4337     { "sidt", { M }, 0 },
4338   },
4339
4340   /* X86_64_0F01_REG_1_RM_5_PREFIX_2 */
4341   {
4342     { Bad_Opcode },
4343     { "seamret",        { Skip_MODRM }, 0 },
4344   },
4345
4346   /* X86_64_0F01_REG_1_RM_6_PREFIX_2 */
4347   {
4348     { Bad_Opcode },
4349     { "seamops",        { Skip_MODRM }, 0 },
4350   },
4351
4352   /* X86_64_0F01_REG_1_RM_7_PREFIX_2 */
4353   {
4354     { Bad_Opcode },
4355     { "seamcall",       { Skip_MODRM }, 0 },
4356   },
4357
4358   /* X86_64_0F01_REG_2 */
4359   {
4360     { "lgdt{Q|Q}", { M }, 0 },
4361     { "lgdt", { M }, 0 },
4362   },
4363
4364   /* X86_64_0F01_REG_3 */
4365   {
4366     { "lidt{Q|Q}", { M }, 0 },
4367     { "lidt", { M }, 0 },
4368   },
4369
4370   /* X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1 */
4371   {
4372     { Bad_Opcode },
4373     { "uiret",  { Skip_MODRM }, 0 },
4374   },
4375
4376   /* X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1 */
4377   {
4378     { Bad_Opcode },
4379     { "testui", { Skip_MODRM }, 0 },
4380   },
4381
4382   /* X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1 */
4383   {
4384     { Bad_Opcode },
4385     { "clui",   { Skip_MODRM }, 0 },
4386   },
4387
4388   /* X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1 */
4389   {
4390     { Bad_Opcode },
4391     { "stui",   { Skip_MODRM }, 0 },
4392   },
4393
4394   /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1 */
4395   {
4396     { Bad_Opcode },
4397     { "rmpadjust",      { Skip_MODRM }, 0 },
4398   },
4399
4400   /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3 */
4401   {
4402     { Bad_Opcode },
4403     { "rmpupdate",      { Skip_MODRM }, 0 },
4404   },
4405
4406   /* X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1 */
4407   {
4408     { Bad_Opcode },
4409     { "psmash", { Skip_MODRM }, 0 },
4410   },
4411
4412   /* X86_64_0F18_REG_6_MOD_0 */
4413   {
4414     { "nopQ",           { Ev }, 0 },
4415     { PREFIX_TABLE (PREFIX_0F18_REG_6_MOD_0_X86_64) },
4416   },
4417
4418   /* X86_64_0F18_REG_7_MOD_0 */
4419   {
4420     { "nopQ",           { Ev }, 0 },
4421     { PREFIX_TABLE (PREFIX_0F18_REG_7_MOD_0_X86_64) },
4422   },
4423
4424   {
4425     /* X86_64_0F24 */
4426     { "movZ",           { Em, Td }, 0 },
4427   },
4428
4429   {
4430     /* X86_64_0F26 */
4431     { "movZ",           { Td, Em }, 0 },
4432   },
4433
4434   /* X86_64_0FC7_REG_6_MOD_3_PREFIX_1 */
4435   {
4436     { Bad_Opcode },
4437     { "senduipi",       { Eq }, 0 },
4438   },
4439
4440   /* X86_64_VEX_0F3849 */
4441   {
4442     { Bad_Opcode },
4443     { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64) },
4444   },
4445
4446   /* X86_64_VEX_0F384B */
4447   {
4448     { Bad_Opcode },
4449     { PREFIX_TABLE (PREFIX_VEX_0F384B_X86_64) },
4450   },
4451
4452   /* X86_64_VEX_0F385C */
4453   {
4454     { Bad_Opcode },
4455     { PREFIX_TABLE (PREFIX_VEX_0F385C_X86_64) },
4456   },
4457
4458   /* X86_64_VEX_0F385E */
4459   {
4460     { Bad_Opcode },
4461     { PREFIX_TABLE (PREFIX_VEX_0F385E_X86_64) },
4462   },
4463
4464   /* X86_64_VEX_0F38E0 */
4465   {
4466     { Bad_Opcode },
4467     { "cmpoxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4468   },
4469
4470   /* X86_64_VEX_0F38E1 */
4471   {
4472     { Bad_Opcode },
4473     { "cmpnoxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4474   },
4475
4476   /* X86_64_VEX_0F38E2 */
4477   {
4478     { Bad_Opcode },
4479     { "cmpbxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4480   },
4481
4482   /* X86_64_VEX_0F38E3 */
4483   {
4484     { Bad_Opcode },
4485     { "cmpnbxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4486   },
4487
4488   /* X86_64_VEX_0F38E4 */
4489   {
4490     { Bad_Opcode },
4491     { "cmpzxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4492   },
4493
4494   /* X86_64_VEX_0F38E5 */
4495   {
4496     { Bad_Opcode },
4497     { "cmpnzxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4498   },
4499
4500   /* X86_64_VEX_0F38E6 */
4501   {
4502     { Bad_Opcode },
4503     { "cmpbexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4504   },
4505
4506   /* X86_64_VEX_0F38E7 */
4507   {
4508     { Bad_Opcode },
4509     { "cmpnbexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4510   },
4511
4512   /* X86_64_VEX_0F38E8 */
4513   {
4514     { Bad_Opcode },
4515     { "cmpsxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4516   },
4517
4518   /* X86_64_VEX_0F38E9 */
4519   {
4520     { Bad_Opcode },
4521     { "cmpnsxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4522   },
4523
4524   /* X86_64_VEX_0F38EA */
4525   {
4526     { Bad_Opcode },
4527     { "cmppxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4528   },
4529
4530   /* X86_64_VEX_0F38EB */
4531   {
4532     { Bad_Opcode },
4533     { "cmpnpxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4534   },
4535
4536   /* X86_64_VEX_0F38EC */
4537   {
4538     { Bad_Opcode },
4539     { "cmplxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4540   },
4541
4542   /* X86_64_VEX_0F38ED */
4543   {
4544     { Bad_Opcode },
4545     { "cmpnlxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4546   },
4547
4548   /* X86_64_VEX_0F38EE */
4549   {
4550     { Bad_Opcode },
4551     { "cmplexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4552   },
4553
4554   /* X86_64_VEX_0F38EF */
4555   {
4556     { Bad_Opcode },
4557     { "cmpnlexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4558   },
4559 };
4560
4561 static const struct dis386 three_byte_table[][256] = {
4562
4563   /* THREE_BYTE_0F38 */
4564   {
4565     /* 00 */
4566     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
4567     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
4568     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
4569     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
4570     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
4571     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
4572     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
4573     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
4574     /* 08 */
4575     { "psignb",         { MX, EM }, PREFIX_OPCODE },
4576     { "psignw",         { MX, EM }, PREFIX_OPCODE },
4577     { "psignd",         { MX, EM }, PREFIX_OPCODE },
4578     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
4579     { Bad_Opcode },
4580     { Bad_Opcode },
4581     { Bad_Opcode },
4582     { Bad_Opcode },
4583     /* 10 */
4584     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_DATA },
4585     { Bad_Opcode },
4586     { Bad_Opcode },
4587     { Bad_Opcode },
4588     { "blendvps", { XM, EXx, XMM0 }, PREFIX_DATA },
4589     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_DATA },
4590     { Bad_Opcode },
4591     { "ptest",  { XM, EXx }, PREFIX_DATA },
4592     /* 18 */
4593     { Bad_Opcode },
4594     { Bad_Opcode },
4595     { Bad_Opcode },
4596     { Bad_Opcode },
4597     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
4598     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
4599     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
4600     { Bad_Opcode },
4601     /* 20 */
4602     { "pmovsxbw", { XM, EXq }, PREFIX_DATA },
4603     { "pmovsxbd", { XM, EXd }, PREFIX_DATA },
4604     { "pmovsxbq", { XM, EXw }, PREFIX_DATA },
4605     { "pmovsxwd", { XM, EXq }, PREFIX_DATA },
4606     { "pmovsxwq", { XM, EXd }, PREFIX_DATA },
4607     { "pmovsxdq", { XM, EXq }, PREFIX_DATA },
4608     { Bad_Opcode },
4609     { Bad_Opcode },
4610     /* 28 */
4611     { "pmuldq", { XM, EXx }, PREFIX_DATA },
4612     { "pcmpeqq", { XM, EXx }, PREFIX_DATA },
4613     { MOD_TABLE (MOD_0F382A) },
4614     { "packusdw", { XM, EXx }, PREFIX_DATA },
4615     { Bad_Opcode },
4616     { Bad_Opcode },
4617     { Bad_Opcode },
4618     { Bad_Opcode },
4619     /* 30 */
4620     { "pmovzxbw", { XM, EXq }, PREFIX_DATA },
4621     { "pmovzxbd", { XM, EXd }, PREFIX_DATA },
4622     { "pmovzxbq", { XM, EXw }, PREFIX_DATA },
4623     { "pmovzxwd", { XM, EXq }, PREFIX_DATA },
4624     { "pmovzxwq", { XM, EXd }, PREFIX_DATA },
4625     { "pmovzxdq", { XM, EXq }, PREFIX_DATA },
4626     { Bad_Opcode },
4627     { "pcmpgtq", { XM, EXx }, PREFIX_DATA },
4628     /* 38 */
4629     { "pminsb", { XM, EXx }, PREFIX_DATA },
4630     { "pminsd", { XM, EXx }, PREFIX_DATA },
4631     { "pminuw", { XM, EXx }, PREFIX_DATA },
4632     { "pminud", { XM, EXx }, PREFIX_DATA },
4633     { "pmaxsb", { XM, EXx }, PREFIX_DATA },
4634     { "pmaxsd", { XM, EXx }, PREFIX_DATA },
4635     { "pmaxuw", { XM, EXx }, PREFIX_DATA },
4636     { "pmaxud", { XM, EXx }, PREFIX_DATA },
4637     /* 40 */
4638     { "pmulld", { XM, EXx }, PREFIX_DATA },
4639     { "phminposuw", { XM, EXx }, PREFIX_DATA },
4640     { Bad_Opcode },
4641     { Bad_Opcode },
4642     { Bad_Opcode },
4643     { Bad_Opcode },
4644     { Bad_Opcode },
4645     { Bad_Opcode },
4646     /* 48 */
4647     { Bad_Opcode },
4648     { Bad_Opcode },
4649     { Bad_Opcode },
4650     { Bad_Opcode },
4651     { Bad_Opcode },
4652     { Bad_Opcode },
4653     { Bad_Opcode },
4654     { Bad_Opcode },
4655     /* 50 */
4656     { Bad_Opcode },
4657     { Bad_Opcode },
4658     { Bad_Opcode },
4659     { Bad_Opcode },
4660     { Bad_Opcode },
4661     { Bad_Opcode },
4662     { Bad_Opcode },
4663     { Bad_Opcode },
4664     /* 58 */
4665     { Bad_Opcode },
4666     { Bad_Opcode },
4667     { Bad_Opcode },
4668     { Bad_Opcode },
4669     { Bad_Opcode },
4670     { Bad_Opcode },
4671     { Bad_Opcode },
4672     { Bad_Opcode },
4673     /* 60 */
4674     { Bad_Opcode },
4675     { Bad_Opcode },
4676     { Bad_Opcode },
4677     { Bad_Opcode },
4678     { Bad_Opcode },
4679     { Bad_Opcode },
4680     { Bad_Opcode },
4681     { Bad_Opcode },
4682     /* 68 */
4683     { Bad_Opcode },
4684     { Bad_Opcode },
4685     { Bad_Opcode },
4686     { Bad_Opcode },
4687     { Bad_Opcode },
4688     { Bad_Opcode },
4689     { Bad_Opcode },
4690     { Bad_Opcode },
4691     /* 70 */
4692     { Bad_Opcode },
4693     { Bad_Opcode },
4694     { Bad_Opcode },
4695     { Bad_Opcode },
4696     { Bad_Opcode },
4697     { Bad_Opcode },
4698     { Bad_Opcode },
4699     { Bad_Opcode },
4700     /* 78 */
4701     { Bad_Opcode },
4702     { Bad_Opcode },
4703     { Bad_Opcode },
4704     { Bad_Opcode },
4705     { Bad_Opcode },
4706     { Bad_Opcode },
4707     { Bad_Opcode },
4708     { Bad_Opcode },
4709     /* 80 */
4710     { "invept", { Gm, Mo }, PREFIX_DATA },
4711     { "invvpid", { Gm, Mo }, PREFIX_DATA },
4712     { "invpcid", { Gm, M }, PREFIX_DATA },
4713     { Bad_Opcode },
4714     { Bad_Opcode },
4715     { Bad_Opcode },
4716     { Bad_Opcode },
4717     { Bad_Opcode },
4718     /* 88 */
4719     { Bad_Opcode },
4720     { Bad_Opcode },
4721     { Bad_Opcode },
4722     { Bad_Opcode },
4723     { Bad_Opcode },
4724     { Bad_Opcode },
4725     { Bad_Opcode },
4726     { Bad_Opcode },
4727     /* 90 */
4728     { Bad_Opcode },
4729     { Bad_Opcode },
4730     { Bad_Opcode },
4731     { Bad_Opcode },
4732     { Bad_Opcode },
4733     { Bad_Opcode },
4734     { Bad_Opcode },
4735     { Bad_Opcode },
4736     /* 98 */
4737     { Bad_Opcode },
4738     { Bad_Opcode },
4739     { Bad_Opcode },
4740     { Bad_Opcode },
4741     { Bad_Opcode },
4742     { Bad_Opcode },
4743     { Bad_Opcode },
4744     { Bad_Opcode },
4745     /* a0 */
4746     { Bad_Opcode },
4747     { Bad_Opcode },
4748     { Bad_Opcode },
4749     { Bad_Opcode },
4750     { Bad_Opcode },
4751     { Bad_Opcode },
4752     { Bad_Opcode },
4753     { Bad_Opcode },
4754     /* a8 */
4755     { Bad_Opcode },
4756     { Bad_Opcode },
4757     { Bad_Opcode },
4758     { Bad_Opcode },
4759     { Bad_Opcode },
4760     { Bad_Opcode },
4761     { Bad_Opcode },
4762     { Bad_Opcode },
4763     /* b0 */
4764     { Bad_Opcode },
4765     { Bad_Opcode },
4766     { Bad_Opcode },
4767     { Bad_Opcode },
4768     { Bad_Opcode },
4769     { Bad_Opcode },
4770     { Bad_Opcode },
4771     { Bad_Opcode },
4772     /* b8 */
4773     { Bad_Opcode },
4774     { Bad_Opcode },
4775     { Bad_Opcode },
4776     { Bad_Opcode },
4777     { Bad_Opcode },
4778     { Bad_Opcode },
4779     { Bad_Opcode },
4780     { Bad_Opcode },
4781     /* c0 */
4782     { Bad_Opcode },
4783     { Bad_Opcode },
4784     { Bad_Opcode },
4785     { Bad_Opcode },
4786     { Bad_Opcode },
4787     { Bad_Opcode },
4788     { Bad_Opcode },
4789     { Bad_Opcode },
4790     /* c8 */
4791     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4792     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4793     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4794     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4795     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4796     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4797     { Bad_Opcode },
4798     { "gf2p8mulb", { XM, EXxmm }, PREFIX_DATA },
4799     /* d0 */
4800     { Bad_Opcode },
4801     { Bad_Opcode },
4802     { Bad_Opcode },
4803     { Bad_Opcode },
4804     { Bad_Opcode },
4805     { Bad_Opcode },
4806     { Bad_Opcode },
4807     { Bad_Opcode },
4808     /* d8 */
4809     { PREFIX_TABLE (PREFIX_0F38D8) },
4810     { Bad_Opcode },
4811     { Bad_Opcode },
4812     { "aesimc", { XM, EXx }, PREFIX_DATA },
4813     { PREFIX_TABLE (PREFIX_0F38DC) },
4814     { PREFIX_TABLE (PREFIX_0F38DD) },
4815     { PREFIX_TABLE (PREFIX_0F38DE) },
4816     { PREFIX_TABLE (PREFIX_0F38DF) },
4817     /* e0 */
4818     { Bad_Opcode },
4819     { Bad_Opcode },
4820     { Bad_Opcode },
4821     { Bad_Opcode },
4822     { Bad_Opcode },
4823     { Bad_Opcode },
4824     { Bad_Opcode },
4825     { Bad_Opcode },
4826     /* e8 */
4827     { Bad_Opcode },
4828     { Bad_Opcode },
4829     { Bad_Opcode },
4830     { Bad_Opcode },
4831     { Bad_Opcode },
4832     { Bad_Opcode },
4833     { Bad_Opcode },
4834     { Bad_Opcode },
4835     /* f0 */
4836     { PREFIX_TABLE (PREFIX_0F38F0) },
4837     { PREFIX_TABLE (PREFIX_0F38F1) },
4838     { Bad_Opcode },
4839     { Bad_Opcode },
4840     { Bad_Opcode },
4841     { MOD_TABLE (MOD_0F38F5) },
4842     { PREFIX_TABLE (PREFIX_0F38F6) },
4843     { Bad_Opcode },
4844     /* f8 */
4845     { PREFIX_TABLE (PREFIX_0F38F8) },
4846     { MOD_TABLE (MOD_0F38F9) },
4847     { PREFIX_TABLE (PREFIX_0F38FA) },
4848     { PREFIX_TABLE (PREFIX_0F38FB) },
4849     { Bad_Opcode },
4850     { Bad_Opcode },
4851     { Bad_Opcode },
4852     { Bad_Opcode },
4853   },
4854   /* THREE_BYTE_0F3A */
4855   {
4856     /* 00 */
4857     { Bad_Opcode },
4858     { Bad_Opcode },
4859     { Bad_Opcode },
4860     { Bad_Opcode },
4861     { Bad_Opcode },
4862     { Bad_Opcode },
4863     { Bad_Opcode },
4864     { Bad_Opcode },
4865     /* 08 */
4866     { "roundps", { XM, EXx, Ib }, PREFIX_DATA },
4867     { "roundpd", { XM, EXx, Ib }, PREFIX_DATA },
4868     { "roundss", { XM, EXd, Ib }, PREFIX_DATA },
4869     { "roundsd", { XM, EXq, Ib }, PREFIX_DATA },
4870     { "blendps", { XM, EXx, Ib }, PREFIX_DATA },
4871     { "blendpd", { XM, EXx, Ib }, PREFIX_DATA },
4872     { "pblendw", { XM, EXx, Ib }, PREFIX_DATA },
4873     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
4874     /* 10 */
4875     { Bad_Opcode },
4876     { Bad_Opcode },
4877     { Bad_Opcode },
4878     { Bad_Opcode },
4879     { "pextrb", { Edb, XM, Ib }, PREFIX_DATA },
4880     { "pextrw", { Edw, XM, Ib }, PREFIX_DATA },
4881     { "pextrK", { Edq, XM, Ib }, PREFIX_DATA },
4882     { "extractps", { Ed, XM, Ib }, PREFIX_DATA },
4883     /* 18 */
4884     { Bad_Opcode },
4885     { Bad_Opcode },
4886     { Bad_Opcode },
4887     { Bad_Opcode },
4888     { Bad_Opcode },
4889     { Bad_Opcode },
4890     { Bad_Opcode },
4891     { Bad_Opcode },
4892     /* 20 */
4893     { "pinsrb", { XM, Edb, Ib }, PREFIX_DATA },
4894     { "insertps", { XM, EXd, Ib }, PREFIX_DATA },
4895     { "pinsrK", { XM, Edq, Ib }, PREFIX_DATA },
4896     { Bad_Opcode },
4897     { Bad_Opcode },
4898     { Bad_Opcode },
4899     { Bad_Opcode },
4900     { Bad_Opcode },
4901     /* 28 */
4902     { Bad_Opcode },
4903     { Bad_Opcode },
4904     { Bad_Opcode },
4905     { Bad_Opcode },
4906     { Bad_Opcode },
4907     { Bad_Opcode },
4908     { Bad_Opcode },
4909     { Bad_Opcode },
4910     /* 30 */
4911     { Bad_Opcode },
4912     { Bad_Opcode },
4913     { Bad_Opcode },
4914     { Bad_Opcode },
4915     { Bad_Opcode },
4916     { Bad_Opcode },
4917     { Bad_Opcode },
4918     { Bad_Opcode },
4919     /* 38 */
4920     { Bad_Opcode },
4921     { Bad_Opcode },
4922     { Bad_Opcode },
4923     { Bad_Opcode },
4924     { Bad_Opcode },
4925     { Bad_Opcode },
4926     { Bad_Opcode },
4927     { Bad_Opcode },
4928     /* 40 */
4929     { "dpps",   { XM, EXx, Ib }, PREFIX_DATA },
4930     { "dppd",   { XM, EXx, Ib }, PREFIX_DATA },
4931     { "mpsadbw", { XM, EXx, Ib }, PREFIX_DATA },
4932     { Bad_Opcode },
4933     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_DATA },
4934     { Bad_Opcode },
4935     { Bad_Opcode },
4936     { Bad_Opcode },
4937     /* 48 */
4938     { Bad_Opcode },
4939     { Bad_Opcode },
4940     { Bad_Opcode },
4941     { Bad_Opcode },
4942     { Bad_Opcode },
4943     { Bad_Opcode },
4944     { Bad_Opcode },
4945     { Bad_Opcode },
4946     /* 50 */
4947     { Bad_Opcode },
4948     { Bad_Opcode },
4949     { Bad_Opcode },
4950     { Bad_Opcode },
4951     { Bad_Opcode },
4952     { Bad_Opcode },
4953     { Bad_Opcode },
4954     { Bad_Opcode },
4955     /* 58 */
4956     { Bad_Opcode },
4957     { Bad_Opcode },
4958     { Bad_Opcode },
4959     { Bad_Opcode },
4960     { Bad_Opcode },
4961     { Bad_Opcode },
4962     { Bad_Opcode },
4963     { Bad_Opcode },
4964     /* 60 */
4965     { "pcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
4966     { "pcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
4967     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_DATA },
4968     { "pcmpistri", { XM, EXx, Ib }, PREFIX_DATA },
4969     { Bad_Opcode },
4970     { Bad_Opcode },
4971     { Bad_Opcode },
4972     { Bad_Opcode },
4973     /* 68 */
4974     { Bad_Opcode },
4975     { Bad_Opcode },
4976     { Bad_Opcode },
4977     { Bad_Opcode },
4978     { Bad_Opcode },
4979     { Bad_Opcode },
4980     { Bad_Opcode },
4981     { Bad_Opcode },
4982     /* 70 */
4983     { Bad_Opcode },
4984     { Bad_Opcode },
4985     { Bad_Opcode },
4986     { Bad_Opcode },
4987     { Bad_Opcode },
4988     { Bad_Opcode },
4989     { Bad_Opcode },
4990     { Bad_Opcode },
4991     /* 78 */
4992     { Bad_Opcode },
4993     { Bad_Opcode },
4994     { Bad_Opcode },
4995     { Bad_Opcode },
4996     { Bad_Opcode },
4997     { Bad_Opcode },
4998     { Bad_Opcode },
4999     { Bad_Opcode },
5000     /* 80 */
5001     { Bad_Opcode },
5002     { Bad_Opcode },
5003     { Bad_Opcode },
5004     { Bad_Opcode },
5005     { Bad_Opcode },
5006     { Bad_Opcode },
5007     { Bad_Opcode },
5008     { Bad_Opcode },
5009     /* 88 */
5010     { Bad_Opcode },
5011     { Bad_Opcode },
5012     { Bad_Opcode },
5013     { Bad_Opcode },
5014     { Bad_Opcode },
5015     { Bad_Opcode },
5016     { Bad_Opcode },
5017     { Bad_Opcode },
5018     /* 90 */
5019     { Bad_Opcode },
5020     { Bad_Opcode },
5021     { Bad_Opcode },
5022     { Bad_Opcode },
5023     { Bad_Opcode },
5024     { Bad_Opcode },
5025     { Bad_Opcode },
5026     { Bad_Opcode },
5027     /* 98 */
5028     { Bad_Opcode },
5029     { Bad_Opcode },
5030     { Bad_Opcode },
5031     { Bad_Opcode },
5032     { Bad_Opcode },
5033     { Bad_Opcode },
5034     { Bad_Opcode },
5035     { Bad_Opcode },
5036     /* a0 */
5037     { Bad_Opcode },
5038     { Bad_Opcode },
5039     { Bad_Opcode },
5040     { Bad_Opcode },
5041     { Bad_Opcode },
5042     { Bad_Opcode },
5043     { Bad_Opcode },
5044     { Bad_Opcode },
5045     /* a8 */
5046     { Bad_Opcode },
5047     { Bad_Opcode },
5048     { Bad_Opcode },
5049     { Bad_Opcode },
5050     { Bad_Opcode },
5051     { Bad_Opcode },
5052     { Bad_Opcode },
5053     { Bad_Opcode },
5054     /* b0 */
5055     { Bad_Opcode },
5056     { Bad_Opcode },
5057     { Bad_Opcode },
5058     { Bad_Opcode },
5059     { Bad_Opcode },
5060     { Bad_Opcode },
5061     { Bad_Opcode },
5062     { Bad_Opcode },
5063     /* b8 */
5064     { Bad_Opcode },
5065     { Bad_Opcode },
5066     { Bad_Opcode },
5067     { Bad_Opcode },
5068     { Bad_Opcode },
5069     { Bad_Opcode },
5070     { Bad_Opcode },
5071     { Bad_Opcode },
5072     /* c0 */
5073     { Bad_Opcode },
5074     { Bad_Opcode },
5075     { Bad_Opcode },
5076     { Bad_Opcode },
5077     { Bad_Opcode },
5078     { Bad_Opcode },
5079     { Bad_Opcode },
5080     { Bad_Opcode },
5081     /* c8 */
5082     { Bad_Opcode },
5083     { Bad_Opcode },
5084     { Bad_Opcode },
5085     { Bad_Opcode },
5086     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
5087     { Bad_Opcode },
5088     { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_DATA },
5089     { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_DATA },
5090     /* d0 */
5091     { Bad_Opcode },
5092     { Bad_Opcode },
5093     { Bad_Opcode },
5094     { Bad_Opcode },
5095     { Bad_Opcode },
5096     { Bad_Opcode },
5097     { Bad_Opcode },
5098     { Bad_Opcode },
5099     /* d8 */
5100     { Bad_Opcode },
5101     { Bad_Opcode },
5102     { Bad_Opcode },
5103     { Bad_Opcode },
5104     { Bad_Opcode },
5105     { Bad_Opcode },
5106     { Bad_Opcode },
5107     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
5108     /* e0 */
5109     { Bad_Opcode },
5110     { Bad_Opcode },
5111     { Bad_Opcode },
5112     { Bad_Opcode },
5113     { Bad_Opcode },
5114     { Bad_Opcode },
5115     { Bad_Opcode },
5116     { Bad_Opcode },
5117     /* e8 */
5118     { Bad_Opcode },
5119     { Bad_Opcode },
5120     { Bad_Opcode },
5121     { Bad_Opcode },
5122     { Bad_Opcode },
5123     { Bad_Opcode },
5124     { Bad_Opcode },
5125     { Bad_Opcode },
5126     /* f0 */
5127     { PREFIX_TABLE (PREFIX_0F3A0F) },
5128     { Bad_Opcode },
5129     { Bad_Opcode },
5130     { Bad_Opcode },
5131     { Bad_Opcode },
5132     { Bad_Opcode },
5133     { Bad_Opcode },
5134     { Bad_Opcode },
5135     /* f8 */
5136     { Bad_Opcode },
5137     { Bad_Opcode },
5138     { Bad_Opcode },
5139     { Bad_Opcode },
5140     { Bad_Opcode },
5141     { Bad_Opcode },
5142     { Bad_Opcode },
5143     { Bad_Opcode },
5144   },
5145 };
5146
5147 static const struct dis386 xop_table[][256] = {
5148   /* XOP_08 */
5149   {
5150     /* 00 */
5151     { Bad_Opcode },
5152     { Bad_Opcode },
5153     { Bad_Opcode },
5154     { Bad_Opcode },
5155     { Bad_Opcode },
5156     { Bad_Opcode },
5157     { Bad_Opcode },
5158     { Bad_Opcode },
5159     /* 08 */
5160     { Bad_Opcode },
5161     { Bad_Opcode },
5162     { Bad_Opcode },
5163     { Bad_Opcode },
5164     { Bad_Opcode },
5165     { Bad_Opcode },
5166     { Bad_Opcode },
5167     { Bad_Opcode },
5168     /* 10 */
5169     { Bad_Opcode },
5170     { Bad_Opcode },
5171     { Bad_Opcode },
5172     { Bad_Opcode },
5173     { Bad_Opcode },
5174     { Bad_Opcode },
5175     { Bad_Opcode },
5176     { Bad_Opcode },
5177     /* 18 */
5178     { Bad_Opcode },
5179     { Bad_Opcode },
5180     { Bad_Opcode },
5181     { Bad_Opcode },
5182     { Bad_Opcode },
5183     { Bad_Opcode },
5184     { Bad_Opcode },
5185     { Bad_Opcode },
5186     /* 20 */
5187     { Bad_Opcode },
5188     { Bad_Opcode },
5189     { Bad_Opcode },
5190     { Bad_Opcode },
5191     { Bad_Opcode },
5192     { Bad_Opcode },
5193     { Bad_Opcode },
5194     { Bad_Opcode },
5195     /* 28 */
5196     { Bad_Opcode },
5197     { Bad_Opcode },
5198     { Bad_Opcode },
5199     { Bad_Opcode },
5200     { Bad_Opcode },
5201     { Bad_Opcode },
5202     { Bad_Opcode },
5203     { Bad_Opcode },
5204     /* 30 */
5205     { Bad_Opcode },
5206     { Bad_Opcode },
5207     { Bad_Opcode },
5208     { Bad_Opcode },
5209     { Bad_Opcode },
5210     { Bad_Opcode },
5211     { Bad_Opcode },
5212     { Bad_Opcode },
5213     /* 38 */
5214     { Bad_Opcode },
5215     { Bad_Opcode },
5216     { Bad_Opcode },
5217     { Bad_Opcode },
5218     { Bad_Opcode },
5219     { Bad_Opcode },
5220     { Bad_Opcode },
5221     { Bad_Opcode },
5222     /* 40 */
5223     { Bad_Opcode },
5224     { Bad_Opcode },
5225     { Bad_Opcode },
5226     { Bad_Opcode },
5227     { Bad_Opcode },
5228     { Bad_Opcode },
5229     { Bad_Opcode },
5230     { Bad_Opcode },
5231     /* 48 */
5232     { Bad_Opcode },
5233     { Bad_Opcode },
5234     { Bad_Opcode },
5235     { Bad_Opcode },
5236     { Bad_Opcode },
5237     { Bad_Opcode },
5238     { Bad_Opcode },
5239     { Bad_Opcode },
5240     /* 50 */
5241     { Bad_Opcode },
5242     { Bad_Opcode },
5243     { Bad_Opcode },
5244     { Bad_Opcode },
5245     { Bad_Opcode },
5246     { Bad_Opcode },
5247     { Bad_Opcode },
5248     { Bad_Opcode },
5249     /* 58 */
5250     { Bad_Opcode },
5251     { Bad_Opcode },
5252     { Bad_Opcode },
5253     { Bad_Opcode },
5254     { Bad_Opcode },
5255     { Bad_Opcode },
5256     { Bad_Opcode },
5257     { Bad_Opcode },
5258     /* 60 */
5259     { Bad_Opcode },
5260     { Bad_Opcode },
5261     { Bad_Opcode },
5262     { Bad_Opcode },
5263     { Bad_Opcode },
5264     { Bad_Opcode },
5265     { Bad_Opcode },
5266     { Bad_Opcode },
5267     /* 68 */
5268     { Bad_Opcode },
5269     { Bad_Opcode },
5270     { Bad_Opcode },
5271     { Bad_Opcode },
5272     { Bad_Opcode },
5273     { Bad_Opcode },
5274     { Bad_Opcode },
5275     { Bad_Opcode },
5276     /* 70 */
5277     { Bad_Opcode },
5278     { Bad_Opcode },
5279     { Bad_Opcode },
5280     { Bad_Opcode },
5281     { Bad_Opcode },
5282     { Bad_Opcode },
5283     { Bad_Opcode },
5284     { Bad_Opcode },
5285     /* 78 */
5286     { Bad_Opcode },
5287     { Bad_Opcode },
5288     { Bad_Opcode },
5289     { Bad_Opcode },
5290     { Bad_Opcode },
5291     { Bad_Opcode },
5292     { Bad_Opcode },
5293     { Bad_Opcode },
5294     /* 80 */
5295     { Bad_Opcode },
5296     { Bad_Opcode },
5297     { Bad_Opcode },
5298     { Bad_Opcode },
5299     { Bad_Opcode },
5300     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_85) },
5301     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_86) },
5302     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_87) },
5303     /* 88 */
5304     { Bad_Opcode },
5305     { Bad_Opcode },
5306     { Bad_Opcode },
5307     { Bad_Opcode },
5308     { Bad_Opcode },
5309     { Bad_Opcode },
5310     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8E) },
5311     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8F) },
5312     /* 90 */
5313     { Bad_Opcode },
5314     { Bad_Opcode },
5315     { Bad_Opcode },
5316     { Bad_Opcode },
5317     { Bad_Opcode },
5318     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_95) },
5319     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_96) },
5320     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_97) },
5321     /* 98 */
5322     { Bad_Opcode },
5323     { Bad_Opcode },
5324     { Bad_Opcode },
5325     { Bad_Opcode },
5326     { Bad_Opcode },
5327     { Bad_Opcode },
5328     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9E) },
5329     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9F) },
5330     /* a0 */
5331     { Bad_Opcode },
5332     { Bad_Opcode },
5333     { "vpcmov",         { XM, Vex, EXx, XMVexI4 }, 0 },
5334     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A3) },
5335     { Bad_Opcode },
5336     { Bad_Opcode },
5337     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A6) },
5338     { Bad_Opcode },
5339     /* a8 */
5340     { Bad_Opcode },
5341     { Bad_Opcode },
5342     { Bad_Opcode },
5343     { Bad_Opcode },
5344     { Bad_Opcode },
5345     { Bad_Opcode },
5346     { Bad_Opcode },
5347     { Bad_Opcode },
5348     /* b0 */
5349     { Bad_Opcode },
5350     { Bad_Opcode },
5351     { Bad_Opcode },
5352     { Bad_Opcode },
5353     { Bad_Opcode },
5354     { Bad_Opcode },
5355     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_B6) },
5356     { Bad_Opcode },
5357     /* b8 */
5358     { Bad_Opcode },
5359     { Bad_Opcode },
5360     { Bad_Opcode },
5361     { Bad_Opcode },
5362     { Bad_Opcode },
5363     { Bad_Opcode },
5364     { Bad_Opcode },
5365     { Bad_Opcode },
5366     /* c0 */
5367     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C0) },
5368     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C1) },
5369     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C2) },
5370     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C3) },
5371     { Bad_Opcode },
5372     { Bad_Opcode },
5373     { Bad_Opcode },
5374     { Bad_Opcode },
5375     /* c8 */
5376     { Bad_Opcode },
5377     { Bad_Opcode },
5378     { Bad_Opcode },
5379     { Bad_Opcode },
5380     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
5381     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
5382     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
5383     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
5384     /* d0 */
5385     { Bad_Opcode },
5386     { Bad_Opcode },
5387     { Bad_Opcode },
5388     { Bad_Opcode },
5389     { Bad_Opcode },
5390     { Bad_Opcode },
5391     { Bad_Opcode },
5392     { Bad_Opcode },
5393     /* d8 */
5394     { Bad_Opcode },
5395     { Bad_Opcode },
5396     { Bad_Opcode },
5397     { Bad_Opcode },
5398     { Bad_Opcode },
5399     { Bad_Opcode },
5400     { Bad_Opcode },
5401     { Bad_Opcode },
5402     /* e0 */
5403     { Bad_Opcode },
5404     { Bad_Opcode },
5405     { Bad_Opcode },
5406     { Bad_Opcode },
5407     { Bad_Opcode },
5408     { Bad_Opcode },
5409     { Bad_Opcode },
5410     { Bad_Opcode },
5411     /* e8 */
5412     { Bad_Opcode },
5413     { Bad_Opcode },
5414     { Bad_Opcode },
5415     { Bad_Opcode },
5416     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
5417     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
5418     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
5419     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
5420     /* f0 */
5421     { Bad_Opcode },
5422     { Bad_Opcode },
5423     { Bad_Opcode },
5424     { Bad_Opcode },
5425     { Bad_Opcode },
5426     { Bad_Opcode },
5427     { Bad_Opcode },
5428     { Bad_Opcode },
5429     /* f8 */
5430     { Bad_Opcode },
5431     { Bad_Opcode },
5432     { Bad_Opcode },
5433     { Bad_Opcode },
5434     { Bad_Opcode },
5435     { Bad_Opcode },
5436     { Bad_Opcode },
5437     { Bad_Opcode },
5438   },
5439   /* XOP_09 */
5440   {
5441     /* 00 */
5442     { Bad_Opcode },
5443     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_01) },
5444     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_02) },
5445     { Bad_Opcode },
5446     { Bad_Opcode },
5447     { Bad_Opcode },
5448     { Bad_Opcode },
5449     { Bad_Opcode },
5450     /* 08 */
5451     { Bad_Opcode },
5452     { Bad_Opcode },
5453     { Bad_Opcode },
5454     { Bad_Opcode },
5455     { Bad_Opcode },
5456     { Bad_Opcode },
5457     { Bad_Opcode },
5458     { Bad_Opcode },
5459     /* 10 */
5460     { Bad_Opcode },
5461     { Bad_Opcode },
5462     { MOD_TABLE (MOD_XOP_09_12) },
5463     { Bad_Opcode },
5464     { Bad_Opcode },
5465     { Bad_Opcode },
5466     { Bad_Opcode },
5467     { Bad_Opcode },
5468     /* 18 */
5469     { Bad_Opcode },
5470     { Bad_Opcode },
5471     { Bad_Opcode },
5472     { Bad_Opcode },
5473     { Bad_Opcode },
5474     { Bad_Opcode },
5475     { Bad_Opcode },
5476     { Bad_Opcode },
5477     /* 20 */
5478     { Bad_Opcode },
5479     { Bad_Opcode },
5480     { Bad_Opcode },
5481     { Bad_Opcode },
5482     { Bad_Opcode },
5483     { Bad_Opcode },
5484     { Bad_Opcode },
5485     { Bad_Opcode },
5486     /* 28 */
5487     { Bad_Opcode },
5488     { Bad_Opcode },
5489     { Bad_Opcode },
5490     { Bad_Opcode },
5491     { Bad_Opcode },
5492     { Bad_Opcode },
5493     { Bad_Opcode },
5494     { Bad_Opcode },
5495     /* 30 */
5496     { Bad_Opcode },
5497     { Bad_Opcode },
5498     { Bad_Opcode },
5499     { Bad_Opcode },
5500     { Bad_Opcode },
5501     { Bad_Opcode },
5502     { Bad_Opcode },
5503     { Bad_Opcode },
5504     /* 38 */
5505     { Bad_Opcode },
5506     { Bad_Opcode },
5507     { Bad_Opcode },
5508     { Bad_Opcode },
5509     { Bad_Opcode },
5510     { Bad_Opcode },
5511     { Bad_Opcode },
5512     { Bad_Opcode },
5513     /* 40 */
5514     { Bad_Opcode },
5515     { Bad_Opcode },
5516     { Bad_Opcode },
5517     { Bad_Opcode },
5518     { Bad_Opcode },
5519     { Bad_Opcode },
5520     { Bad_Opcode },
5521     { Bad_Opcode },
5522     /* 48 */
5523     { Bad_Opcode },
5524     { Bad_Opcode },
5525     { Bad_Opcode },
5526     { Bad_Opcode },
5527     { Bad_Opcode },
5528     { Bad_Opcode },
5529     { Bad_Opcode },
5530     { Bad_Opcode },
5531     /* 50 */
5532     { Bad_Opcode },
5533     { Bad_Opcode },
5534     { Bad_Opcode },
5535     { Bad_Opcode },
5536     { Bad_Opcode },
5537     { Bad_Opcode },
5538     { Bad_Opcode },
5539     { Bad_Opcode },
5540     /* 58 */
5541     { Bad_Opcode },
5542     { Bad_Opcode },
5543     { Bad_Opcode },
5544     { Bad_Opcode },
5545     { Bad_Opcode },
5546     { Bad_Opcode },
5547     { Bad_Opcode },
5548     { Bad_Opcode },
5549     /* 60 */
5550     { Bad_Opcode },
5551     { Bad_Opcode },
5552     { Bad_Opcode },
5553     { Bad_Opcode },
5554     { Bad_Opcode },
5555     { Bad_Opcode },
5556     { Bad_Opcode },
5557     { Bad_Opcode },
5558     /* 68 */
5559     { Bad_Opcode },
5560     { Bad_Opcode },
5561     { Bad_Opcode },
5562     { Bad_Opcode },
5563     { Bad_Opcode },
5564     { Bad_Opcode },
5565     { Bad_Opcode },
5566     { Bad_Opcode },
5567     /* 70 */
5568     { Bad_Opcode },
5569     { Bad_Opcode },
5570     { Bad_Opcode },
5571     { Bad_Opcode },
5572     { Bad_Opcode },
5573     { Bad_Opcode },
5574     { Bad_Opcode },
5575     { Bad_Opcode },
5576     /* 78 */
5577     { Bad_Opcode },
5578     { Bad_Opcode },
5579     { Bad_Opcode },
5580     { Bad_Opcode },
5581     { Bad_Opcode },
5582     { Bad_Opcode },
5583     { Bad_Opcode },
5584     { Bad_Opcode },
5585     /* 80 */
5586     { VEX_W_TABLE (VEX_W_0FXOP_09_80) },
5587     { VEX_W_TABLE (VEX_W_0FXOP_09_81) },
5588     { VEX_W_TABLE (VEX_W_0FXOP_09_82) },
5589     { VEX_W_TABLE (VEX_W_0FXOP_09_83) },
5590     { Bad_Opcode },
5591     { Bad_Opcode },
5592     { Bad_Opcode },
5593     { Bad_Opcode },
5594     /* 88 */
5595     { Bad_Opcode },
5596     { Bad_Opcode },
5597     { Bad_Opcode },
5598     { Bad_Opcode },
5599     { Bad_Opcode },
5600     { Bad_Opcode },
5601     { Bad_Opcode },
5602     { Bad_Opcode },
5603     /* 90 */
5604     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_90) },
5605     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_91) },
5606     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_92) },
5607     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_93) },
5608     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_94) },
5609     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_95) },
5610     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_96) },
5611     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_97) },
5612     /* 98 */
5613     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_98) },
5614     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_99) },
5615     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9A) },
5616     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9B) },
5617     { Bad_Opcode },
5618     { Bad_Opcode },
5619     { Bad_Opcode },
5620     { Bad_Opcode },
5621     /* a0 */
5622     { Bad_Opcode },
5623     { Bad_Opcode },
5624     { Bad_Opcode },
5625     { Bad_Opcode },
5626     { Bad_Opcode },
5627     { Bad_Opcode },
5628     { Bad_Opcode },
5629     { Bad_Opcode },
5630     /* a8 */
5631     { Bad_Opcode },
5632     { Bad_Opcode },
5633     { Bad_Opcode },
5634     { Bad_Opcode },
5635     { Bad_Opcode },
5636     { Bad_Opcode },
5637     { Bad_Opcode },
5638     { Bad_Opcode },
5639     /* b0 */
5640     { Bad_Opcode },
5641     { Bad_Opcode },
5642     { Bad_Opcode },
5643     { Bad_Opcode },
5644     { Bad_Opcode },
5645     { Bad_Opcode },
5646     { Bad_Opcode },
5647     { Bad_Opcode },
5648     /* b8 */
5649     { Bad_Opcode },
5650     { Bad_Opcode },
5651     { Bad_Opcode },
5652     { Bad_Opcode },
5653     { Bad_Opcode },
5654     { Bad_Opcode },
5655     { Bad_Opcode },
5656     { Bad_Opcode },
5657     /* c0 */
5658     { Bad_Opcode },
5659     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C1) },
5660     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C2) },
5661     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C3) },
5662     { Bad_Opcode },
5663     { Bad_Opcode },
5664     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C6) },
5665     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C7) },
5666     /* c8 */
5667     { Bad_Opcode },
5668     { Bad_Opcode },
5669     { Bad_Opcode },
5670     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_CB) },
5671     { Bad_Opcode },
5672     { Bad_Opcode },
5673     { Bad_Opcode },
5674     { Bad_Opcode },
5675     /* d0 */
5676     { Bad_Opcode },
5677     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D1) },
5678     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D2) },
5679     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D3) },
5680     { Bad_Opcode },
5681     { Bad_Opcode },
5682     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D6) },
5683     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D7) },
5684     /* d8 */
5685     { Bad_Opcode },
5686     { Bad_Opcode },
5687     { Bad_Opcode },
5688     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_DB) },
5689     { Bad_Opcode },
5690     { Bad_Opcode },
5691     { Bad_Opcode },
5692     { Bad_Opcode },
5693     /* e0 */
5694     { Bad_Opcode },
5695     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E1) },
5696     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E2) },
5697     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E3) },
5698     { Bad_Opcode },
5699     { Bad_Opcode },
5700     { Bad_Opcode },
5701     { Bad_Opcode },
5702     /* e8 */
5703     { Bad_Opcode },
5704     { Bad_Opcode },
5705     { Bad_Opcode },
5706     { Bad_Opcode },
5707     { Bad_Opcode },
5708     { Bad_Opcode },
5709     { Bad_Opcode },
5710     { Bad_Opcode },
5711     /* f0 */
5712     { Bad_Opcode },
5713     { Bad_Opcode },
5714     { Bad_Opcode },
5715     { Bad_Opcode },
5716     { Bad_Opcode },
5717     { Bad_Opcode },
5718     { Bad_Opcode },
5719     { Bad_Opcode },
5720     /* f8 */
5721     { Bad_Opcode },
5722     { Bad_Opcode },
5723     { Bad_Opcode },
5724     { Bad_Opcode },
5725     { Bad_Opcode },
5726     { Bad_Opcode },
5727     { Bad_Opcode },
5728     { Bad_Opcode },
5729   },
5730   /* XOP_0A */
5731   {
5732     /* 00 */
5733     { Bad_Opcode },
5734     { Bad_Opcode },
5735     { Bad_Opcode },
5736     { Bad_Opcode },
5737     { Bad_Opcode },
5738     { Bad_Opcode },
5739     { Bad_Opcode },
5740     { Bad_Opcode },
5741     /* 08 */
5742     { Bad_Opcode },
5743     { Bad_Opcode },
5744     { Bad_Opcode },
5745     { Bad_Opcode },
5746     { Bad_Opcode },
5747     { Bad_Opcode },
5748     { Bad_Opcode },
5749     { Bad_Opcode },
5750     /* 10 */
5751     { "bextrS", { Gdq, Edq, Id }, 0 },
5752     { Bad_Opcode },
5753     { VEX_LEN_TABLE (VEX_LEN_0FXOP_0A_12) },
5754     { Bad_Opcode },
5755     { Bad_Opcode },
5756     { Bad_Opcode },
5757     { Bad_Opcode },
5758     { Bad_Opcode },
5759     /* 18 */
5760     { Bad_Opcode },
5761     { Bad_Opcode },
5762     { Bad_Opcode },
5763     { Bad_Opcode },
5764     { Bad_Opcode },
5765     { Bad_Opcode },
5766     { Bad_Opcode },
5767     { Bad_Opcode },
5768     /* 20 */
5769     { Bad_Opcode },
5770     { Bad_Opcode },
5771     { Bad_Opcode },
5772     { Bad_Opcode },
5773     { Bad_Opcode },
5774     { Bad_Opcode },
5775     { Bad_Opcode },
5776     { Bad_Opcode },
5777     /* 28 */
5778     { Bad_Opcode },
5779     { Bad_Opcode },
5780     { Bad_Opcode },
5781     { Bad_Opcode },
5782     { Bad_Opcode },
5783     { Bad_Opcode },
5784     { Bad_Opcode },
5785     { Bad_Opcode },
5786     /* 30 */
5787     { Bad_Opcode },
5788     { Bad_Opcode },
5789     { Bad_Opcode },
5790     { Bad_Opcode },
5791     { Bad_Opcode },
5792     { Bad_Opcode },
5793     { Bad_Opcode },
5794     { Bad_Opcode },
5795     /* 38 */
5796     { Bad_Opcode },
5797     { Bad_Opcode },
5798     { Bad_Opcode },
5799     { Bad_Opcode },
5800     { Bad_Opcode },
5801     { Bad_Opcode },
5802     { Bad_Opcode },
5803     { Bad_Opcode },
5804     /* 40 */
5805     { Bad_Opcode },
5806     { Bad_Opcode },
5807     { Bad_Opcode },
5808     { Bad_Opcode },
5809     { Bad_Opcode },
5810     { Bad_Opcode },
5811     { Bad_Opcode },
5812     { Bad_Opcode },
5813     /* 48 */
5814     { Bad_Opcode },
5815     { Bad_Opcode },
5816     { Bad_Opcode },
5817     { Bad_Opcode },
5818     { Bad_Opcode },
5819     { Bad_Opcode },
5820     { Bad_Opcode },
5821     { Bad_Opcode },
5822     /* 50 */
5823     { Bad_Opcode },
5824     { Bad_Opcode },
5825     { Bad_Opcode },
5826     { Bad_Opcode },
5827     { Bad_Opcode },
5828     { Bad_Opcode },
5829     { Bad_Opcode },
5830     { Bad_Opcode },
5831     /* 58 */
5832     { Bad_Opcode },
5833     { Bad_Opcode },
5834     { Bad_Opcode },
5835     { Bad_Opcode },
5836     { Bad_Opcode },
5837     { Bad_Opcode },
5838     { Bad_Opcode },
5839     { Bad_Opcode },
5840     /* 60 */
5841     { Bad_Opcode },
5842     { Bad_Opcode },
5843     { Bad_Opcode },
5844     { Bad_Opcode },
5845     { Bad_Opcode },
5846     { Bad_Opcode },
5847     { Bad_Opcode },
5848     { Bad_Opcode },
5849     /* 68 */
5850     { Bad_Opcode },
5851     { Bad_Opcode },
5852     { Bad_Opcode },
5853     { Bad_Opcode },
5854     { Bad_Opcode },
5855     { Bad_Opcode },
5856     { Bad_Opcode },
5857     { Bad_Opcode },
5858     /* 70 */
5859     { Bad_Opcode },
5860     { Bad_Opcode },
5861     { Bad_Opcode },
5862     { Bad_Opcode },
5863     { Bad_Opcode },
5864     { Bad_Opcode },
5865     { Bad_Opcode },
5866     { Bad_Opcode },
5867     /* 78 */
5868     { Bad_Opcode },
5869     { Bad_Opcode },
5870     { Bad_Opcode },
5871     { Bad_Opcode },
5872     { Bad_Opcode },
5873     { Bad_Opcode },
5874     { Bad_Opcode },
5875     { Bad_Opcode },
5876     /* 80 */
5877     { Bad_Opcode },
5878     { Bad_Opcode },
5879     { Bad_Opcode },
5880     { Bad_Opcode },
5881     { Bad_Opcode },
5882     { Bad_Opcode },
5883     { Bad_Opcode },
5884     { Bad_Opcode },
5885     /* 88 */
5886     { Bad_Opcode },
5887     { Bad_Opcode },
5888     { Bad_Opcode },
5889     { Bad_Opcode },
5890     { Bad_Opcode },
5891     { Bad_Opcode },
5892     { Bad_Opcode },
5893     { Bad_Opcode },
5894     /* 90 */
5895     { Bad_Opcode },
5896     { Bad_Opcode },
5897     { Bad_Opcode },
5898     { Bad_Opcode },
5899     { Bad_Opcode },
5900     { Bad_Opcode },
5901     { Bad_Opcode },
5902     { Bad_Opcode },
5903     /* 98 */
5904     { Bad_Opcode },
5905     { Bad_Opcode },
5906     { Bad_Opcode },
5907     { Bad_Opcode },
5908     { Bad_Opcode },
5909     { Bad_Opcode },
5910     { Bad_Opcode },
5911     { Bad_Opcode },
5912     /* a0 */
5913     { Bad_Opcode },
5914     { Bad_Opcode },
5915     { Bad_Opcode },
5916     { Bad_Opcode },
5917     { Bad_Opcode },
5918     { Bad_Opcode },
5919     { Bad_Opcode },
5920     { Bad_Opcode },
5921     /* a8 */
5922     { Bad_Opcode },
5923     { Bad_Opcode },
5924     { Bad_Opcode },
5925     { Bad_Opcode },
5926     { Bad_Opcode },
5927     { Bad_Opcode },
5928     { Bad_Opcode },
5929     { Bad_Opcode },
5930     /* b0 */
5931     { Bad_Opcode },
5932     { Bad_Opcode },
5933     { Bad_Opcode },
5934     { Bad_Opcode },
5935     { Bad_Opcode },
5936     { Bad_Opcode },
5937     { Bad_Opcode },
5938     { Bad_Opcode },
5939     /* b8 */
5940     { Bad_Opcode },
5941     { Bad_Opcode },
5942     { Bad_Opcode },
5943     { Bad_Opcode },
5944     { Bad_Opcode },
5945     { Bad_Opcode },
5946     { Bad_Opcode },
5947     { Bad_Opcode },
5948     /* c0 */
5949     { Bad_Opcode },
5950     { Bad_Opcode },
5951     { Bad_Opcode },
5952     { Bad_Opcode },
5953     { Bad_Opcode },
5954     { Bad_Opcode },
5955     { Bad_Opcode },
5956     { Bad_Opcode },
5957     /* c8 */
5958     { Bad_Opcode },
5959     { Bad_Opcode },
5960     { Bad_Opcode },
5961     { Bad_Opcode },
5962     { Bad_Opcode },
5963     { Bad_Opcode },
5964     { Bad_Opcode },
5965     { Bad_Opcode },
5966     /* d0 */
5967     { Bad_Opcode },
5968     { Bad_Opcode },
5969     { Bad_Opcode },
5970     { Bad_Opcode },
5971     { Bad_Opcode },
5972     { Bad_Opcode },
5973     { Bad_Opcode },
5974     { Bad_Opcode },
5975     /* d8 */
5976     { Bad_Opcode },
5977     { Bad_Opcode },
5978     { Bad_Opcode },
5979     { Bad_Opcode },
5980     { Bad_Opcode },
5981     { Bad_Opcode },
5982     { Bad_Opcode },
5983     { Bad_Opcode },
5984     /* e0 */
5985     { Bad_Opcode },
5986     { Bad_Opcode },
5987     { Bad_Opcode },
5988     { Bad_Opcode },
5989     { Bad_Opcode },
5990     { Bad_Opcode },
5991     { Bad_Opcode },
5992     { Bad_Opcode },
5993     /* e8 */
5994     { Bad_Opcode },
5995     { Bad_Opcode },
5996     { Bad_Opcode },
5997     { Bad_Opcode },
5998     { Bad_Opcode },
5999     { Bad_Opcode },
6000     { Bad_Opcode },
6001     { Bad_Opcode },
6002     /* f0 */
6003     { Bad_Opcode },
6004     { Bad_Opcode },
6005     { Bad_Opcode },
6006     { Bad_Opcode },
6007     { Bad_Opcode },
6008     { Bad_Opcode },
6009     { Bad_Opcode },
6010     { Bad_Opcode },
6011     /* f8 */
6012     { Bad_Opcode },
6013     { Bad_Opcode },
6014     { Bad_Opcode },
6015     { Bad_Opcode },
6016     { Bad_Opcode },
6017     { Bad_Opcode },
6018     { Bad_Opcode },
6019     { Bad_Opcode },
6020   },
6021 };
6022
6023 static const struct dis386 vex_table[][256] = {
6024   /* VEX_0F */
6025   {
6026     /* 00 */
6027     { Bad_Opcode },
6028     { Bad_Opcode },
6029     { Bad_Opcode },
6030     { Bad_Opcode },
6031     { Bad_Opcode },
6032     { Bad_Opcode },
6033     { Bad_Opcode },
6034     { Bad_Opcode },
6035     /* 08 */
6036     { Bad_Opcode },
6037     { Bad_Opcode },
6038     { Bad_Opcode },
6039     { Bad_Opcode },
6040     { Bad_Opcode },
6041     { Bad_Opcode },
6042     { Bad_Opcode },
6043     { Bad_Opcode },
6044     /* 10 */
6045     { PREFIX_TABLE (PREFIX_VEX_0F10) },
6046     { PREFIX_TABLE (PREFIX_VEX_0F11) },
6047     { PREFIX_TABLE (PREFIX_VEX_0F12) },
6048     { MOD_TABLE (MOD_VEX_0F13) },
6049     { "vunpcklpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
6050     { "vunpckhpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
6051     { PREFIX_TABLE (PREFIX_VEX_0F16) },
6052     { MOD_TABLE (MOD_VEX_0F17) },
6053     /* 18 */
6054     { Bad_Opcode },
6055     { Bad_Opcode },
6056     { Bad_Opcode },
6057     { Bad_Opcode },
6058     { Bad_Opcode },
6059     { Bad_Opcode },
6060     { Bad_Opcode },
6061     { Bad_Opcode },
6062     /* 20 */
6063     { Bad_Opcode },
6064     { Bad_Opcode },
6065     { Bad_Opcode },
6066     { Bad_Opcode },
6067     { Bad_Opcode },
6068     { Bad_Opcode },
6069     { Bad_Opcode },
6070     { Bad_Opcode },
6071     /* 28 */
6072     { "vmovapX",        { XM, EXx }, PREFIX_OPCODE },
6073     { "vmovapX",        { EXxS, XM }, PREFIX_OPCODE },
6074     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
6075     { MOD_TABLE (MOD_VEX_0F2B) },
6076     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
6077     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
6078     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
6079     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
6080     /* 30 */
6081     { Bad_Opcode },
6082     { Bad_Opcode },
6083     { Bad_Opcode },
6084     { Bad_Opcode },
6085     { Bad_Opcode },
6086     { Bad_Opcode },
6087     { Bad_Opcode },
6088     { Bad_Opcode },
6089     /* 38 */
6090     { Bad_Opcode },
6091     { Bad_Opcode },
6092     { Bad_Opcode },
6093     { Bad_Opcode },
6094     { Bad_Opcode },
6095     { Bad_Opcode },
6096     { Bad_Opcode },
6097     { Bad_Opcode },
6098     /* 40 */
6099     { Bad_Opcode },
6100     { VEX_LEN_TABLE (VEX_LEN_0F41) },
6101     { VEX_LEN_TABLE (VEX_LEN_0F42) },
6102     { Bad_Opcode },
6103     { VEX_LEN_TABLE (VEX_LEN_0F44) },
6104     { VEX_LEN_TABLE (VEX_LEN_0F45) },
6105     { VEX_LEN_TABLE (VEX_LEN_0F46) },
6106     { VEX_LEN_TABLE (VEX_LEN_0F47) },
6107     /* 48 */
6108     { Bad_Opcode },
6109     { Bad_Opcode },
6110     { VEX_LEN_TABLE (VEX_LEN_0F4A) },
6111     { VEX_LEN_TABLE (VEX_LEN_0F4B) },
6112     { Bad_Opcode },
6113     { Bad_Opcode },
6114     { Bad_Opcode },
6115     { Bad_Opcode },
6116     /* 50 */
6117     { MOD_TABLE (MOD_VEX_0F50) },
6118     { PREFIX_TABLE (PREFIX_VEX_0F51) },
6119     { PREFIX_TABLE (PREFIX_VEX_0F52) },
6120     { PREFIX_TABLE (PREFIX_VEX_0F53) },
6121     { "vandpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
6122     { "vandnpX",        { XM, Vex, EXx }, PREFIX_OPCODE },
6123     { "vorpX",          { XM, Vex, EXx }, PREFIX_OPCODE },
6124     { "vxorpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
6125     /* 58 */
6126     { PREFIX_TABLE (PREFIX_VEX_0F58) },
6127     { PREFIX_TABLE (PREFIX_VEX_0F59) },
6128     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
6129     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
6130     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
6131     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
6132     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
6133     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
6134     /* 60 */
6135     { "vpunpcklbw",     { XM, Vex, EXx }, PREFIX_DATA },
6136     { "vpunpcklwd",     { XM, Vex, EXx }, PREFIX_DATA },
6137     { "vpunpckldq",     { XM, Vex, EXx }, PREFIX_DATA },
6138     { "vpacksswb",      { XM, Vex, EXx }, PREFIX_DATA },
6139     { "vpcmpgtb",       { XM, Vex, EXx }, PREFIX_DATA },
6140     { "vpcmpgtw",       { XM, Vex, EXx }, PREFIX_DATA },
6141     { "vpcmpgtd",       { XM, Vex, EXx }, PREFIX_DATA },
6142     { "vpackuswb",      { XM, Vex, EXx }, PREFIX_DATA },
6143     /* 68 */
6144     { "vpunpckhbw",     { XM, Vex, EXx }, PREFIX_DATA },
6145     { "vpunpckhwd",     { XM, Vex, EXx }, PREFIX_DATA },
6146     { "vpunpckhdq",     { XM, Vex, EXx }, PREFIX_DATA },
6147     { "vpackssdw",      { XM, Vex, EXx }, PREFIX_DATA },
6148     { "vpunpcklqdq",    { XM, Vex, EXx }, PREFIX_DATA },
6149     { "vpunpckhqdq",    { XM, Vex, EXx }, PREFIX_DATA },
6150     { VEX_LEN_TABLE (VEX_LEN_0F6E) },
6151     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
6152     /* 70 */
6153     { PREFIX_TABLE (PREFIX_VEX_0F70) },
6154     { MOD_TABLE (MOD_VEX_0F71) },
6155     { MOD_TABLE (MOD_VEX_0F72) },
6156     { MOD_TABLE (MOD_VEX_0F73) },
6157     { "vpcmpeqb",       { XM, Vex, EXx }, PREFIX_DATA },
6158     { "vpcmpeqw",       { XM, Vex, EXx }, PREFIX_DATA },
6159     { "vpcmpeqd",       { XM, Vex, EXx }, PREFIX_DATA },
6160     { VEX_LEN_TABLE (VEX_LEN_0F77) },
6161     /* 78 */
6162     { Bad_Opcode },
6163     { Bad_Opcode },
6164     { Bad_Opcode },
6165     { Bad_Opcode },
6166     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
6167     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
6168     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
6169     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
6170     /* 80 */
6171     { Bad_Opcode },
6172     { Bad_Opcode },
6173     { Bad_Opcode },
6174     { Bad_Opcode },
6175     { Bad_Opcode },
6176     { Bad_Opcode },
6177     { Bad_Opcode },
6178     { Bad_Opcode },
6179     /* 88 */
6180     { Bad_Opcode },
6181     { Bad_Opcode },
6182     { Bad_Opcode },
6183     { Bad_Opcode },
6184     { Bad_Opcode },
6185     { Bad_Opcode },
6186     { Bad_Opcode },
6187     { Bad_Opcode },
6188     /* 90 */
6189     { VEX_LEN_TABLE (VEX_LEN_0F90) },
6190     { VEX_LEN_TABLE (VEX_LEN_0F91) },
6191     { VEX_LEN_TABLE (VEX_LEN_0F92) },
6192     { VEX_LEN_TABLE (VEX_LEN_0F93) },
6193     { Bad_Opcode },
6194     { Bad_Opcode },
6195     { Bad_Opcode },
6196     { Bad_Opcode },
6197     /* 98 */
6198     { VEX_LEN_TABLE (VEX_LEN_0F98) },
6199     { VEX_LEN_TABLE (VEX_LEN_0F99) },
6200     { Bad_Opcode },
6201     { Bad_Opcode },
6202     { Bad_Opcode },
6203     { Bad_Opcode },
6204     { Bad_Opcode },
6205     { Bad_Opcode },
6206     /* a0 */
6207     { Bad_Opcode },
6208     { Bad_Opcode },
6209     { Bad_Opcode },
6210     { Bad_Opcode },
6211     { Bad_Opcode },
6212     { Bad_Opcode },
6213     { Bad_Opcode },
6214     { Bad_Opcode },
6215     /* a8 */
6216     { Bad_Opcode },
6217     { Bad_Opcode },
6218     { Bad_Opcode },
6219     { Bad_Opcode },
6220     { Bad_Opcode },
6221     { Bad_Opcode },
6222     { REG_TABLE (REG_VEX_0FAE) },
6223     { Bad_Opcode },
6224     /* b0 */
6225     { Bad_Opcode },
6226     { Bad_Opcode },
6227     { Bad_Opcode },
6228     { Bad_Opcode },
6229     { Bad_Opcode },
6230     { Bad_Opcode },
6231     { Bad_Opcode },
6232     { Bad_Opcode },
6233     /* b8 */
6234     { Bad_Opcode },
6235     { Bad_Opcode },
6236     { Bad_Opcode },
6237     { Bad_Opcode },
6238     { Bad_Opcode },
6239     { Bad_Opcode },
6240     { Bad_Opcode },
6241     { Bad_Opcode },
6242     /* c0 */
6243     { Bad_Opcode },
6244     { Bad_Opcode },
6245     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
6246     { Bad_Opcode },
6247     { VEX_LEN_TABLE (VEX_LEN_0FC4) },
6248     { VEX_LEN_TABLE (VEX_LEN_0FC5) },
6249     { "vshufpX",        { XM, Vex, EXx, Ib }, PREFIX_OPCODE },
6250     { Bad_Opcode },
6251     /* c8 */
6252     { Bad_Opcode },
6253     { Bad_Opcode },
6254     { Bad_Opcode },
6255     { Bad_Opcode },
6256     { Bad_Opcode },
6257     { Bad_Opcode },
6258     { Bad_Opcode },
6259     { Bad_Opcode },
6260     /* d0 */
6261     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
6262     { "vpsrlw",         { XM, Vex, EXxmm }, PREFIX_DATA },
6263     { "vpsrld",         { XM, Vex, EXxmm }, PREFIX_DATA },
6264     { "vpsrlq",         { XM, Vex, EXxmm }, PREFIX_DATA },
6265     { "vpaddq",         { XM, Vex, EXx }, PREFIX_DATA },
6266     { "vpmullw",        { XM, Vex, EXx }, PREFIX_DATA },
6267     { VEX_LEN_TABLE (VEX_LEN_0FD6) },
6268     { MOD_TABLE (MOD_VEX_0FD7) },
6269     /* d8 */
6270     { "vpsubusb",       { XM, Vex, EXx }, PREFIX_DATA },
6271     { "vpsubusw",       { XM, Vex, EXx }, PREFIX_DATA },
6272     { "vpminub",        { XM, Vex, EXx }, PREFIX_DATA },
6273     { "vpand",          { XM, Vex, EXx }, PREFIX_DATA },
6274     { "vpaddusb",       { XM, Vex, EXx }, PREFIX_DATA },
6275     { "vpaddusw",       { XM, Vex, EXx }, PREFIX_DATA },
6276     { "vpmaxub",        { XM, Vex, EXx }, PREFIX_DATA },
6277     { "vpandn",         { XM, Vex, EXx }, PREFIX_DATA },
6278     /* e0 */
6279     { "vpavgb",         { XM, Vex, EXx }, PREFIX_DATA },
6280     { "vpsraw",         { XM, Vex, EXxmm }, PREFIX_DATA },
6281     { "vpsrad",         { XM, Vex, EXxmm }, PREFIX_DATA },
6282     { "vpavgw",         { XM, Vex, EXx }, PREFIX_DATA },
6283     { "vpmulhuw",       { XM, Vex, EXx }, PREFIX_DATA },
6284     { "vpmulhw",        { XM, Vex, EXx }, PREFIX_DATA },
6285     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
6286     { MOD_TABLE (MOD_VEX_0FE7) },
6287     /* e8 */
6288     { "vpsubsb",        { XM, Vex, EXx }, PREFIX_DATA },
6289     { "vpsubsw",        { XM, Vex, EXx }, PREFIX_DATA },
6290     { "vpminsw",        { XM, Vex, EXx }, PREFIX_DATA },
6291     { "vpor",           { XM, Vex, EXx }, PREFIX_DATA },
6292     { "vpaddsb",        { XM, Vex, EXx }, PREFIX_DATA },
6293     { "vpaddsw",        { XM, Vex, EXx }, PREFIX_DATA },
6294     { "vpmaxsw",        { XM, Vex, EXx }, PREFIX_DATA },
6295     { "vpxor",          { XM, Vex, EXx }, PREFIX_DATA },
6296     /* f0 */
6297     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
6298     { "vpsllw",         { XM, Vex, EXxmm }, PREFIX_DATA },
6299     { "vpslld",         { XM, Vex, EXxmm }, PREFIX_DATA },
6300     { "vpsllq",         { XM, Vex, EXxmm }, PREFIX_DATA },
6301     { "vpmuludq",       { XM, Vex, EXx }, PREFIX_DATA },
6302     { "vpmaddwd",       { XM, Vex, EXx }, PREFIX_DATA },
6303     { "vpsadbw",        { XM, Vex, EXx }, PREFIX_DATA },
6304     { VEX_LEN_TABLE (VEX_LEN_0FF7) },
6305     /* f8 */
6306     { "vpsubb",         { XM, Vex, EXx }, PREFIX_DATA },
6307     { "vpsubw",         { XM, Vex, EXx }, PREFIX_DATA },
6308     { "vpsubd",         { XM, Vex, EXx }, PREFIX_DATA },
6309     { "vpsubq",         { XM, Vex, EXx }, PREFIX_DATA },
6310     { "vpaddb",         { XM, Vex, EXx }, PREFIX_DATA },
6311     { "vpaddw",         { XM, Vex, EXx }, PREFIX_DATA },
6312     { "vpaddd",         { XM, Vex, EXx }, PREFIX_DATA },
6313     { Bad_Opcode },
6314   },
6315   /* VEX_0F38 */
6316   {
6317     /* 00 */
6318     { "vpshufb",        { XM, Vex, EXx }, PREFIX_DATA },
6319     { "vphaddw",        { XM, Vex, EXx }, PREFIX_DATA },
6320     { "vphaddd",        { XM, Vex, EXx }, PREFIX_DATA },
6321     { "vphaddsw",       { XM, Vex, EXx }, PREFIX_DATA },
6322     { "vpmaddubsw",     { XM, Vex, EXx }, PREFIX_DATA },
6323     { "vphsubw",        { XM, Vex, EXx }, PREFIX_DATA },
6324     { "vphsubd",        { XM, Vex, EXx }, PREFIX_DATA },
6325     { "vphsubsw",       { XM, Vex, EXx }, PREFIX_DATA },
6326     /* 08 */
6327     { "vpsignb",        { XM, Vex, EXx }, PREFIX_DATA },
6328     { "vpsignw",        { XM, Vex, EXx }, PREFIX_DATA },
6329     { "vpsignd",        { XM, Vex, EXx }, PREFIX_DATA },
6330     { "vpmulhrsw",      { XM, Vex, EXx }, PREFIX_DATA },
6331     { VEX_W_TABLE (VEX_W_0F380C) },
6332     { VEX_W_TABLE (VEX_W_0F380D) },
6333     { VEX_W_TABLE (VEX_W_0F380E) },
6334     { VEX_W_TABLE (VEX_W_0F380F) },
6335     /* 10 */
6336     { Bad_Opcode },
6337     { Bad_Opcode },
6338     { Bad_Opcode },
6339     { VEX_W_TABLE (VEX_W_0F3813) },
6340     { Bad_Opcode },
6341     { Bad_Opcode },
6342     { VEX_LEN_TABLE (VEX_LEN_0F3816) },
6343     { "vptest",         { XM, EXx }, PREFIX_DATA },
6344     /* 18 */
6345     { VEX_W_TABLE (VEX_W_0F3818) },
6346     { VEX_LEN_TABLE (VEX_LEN_0F3819) },
6347     { MOD_TABLE (MOD_VEX_0F381A) },
6348     { Bad_Opcode },
6349     { "vpabsb",         { XM, EXx }, PREFIX_DATA },
6350     { "vpabsw",         { XM, EXx }, PREFIX_DATA },
6351     { "vpabsd",         { XM, EXx }, PREFIX_DATA },
6352     { Bad_Opcode },
6353     /* 20 */
6354     { "vpmovsxbw",      { XM, EXxmmq }, PREFIX_DATA },
6355     { "vpmovsxbd",      { XM, EXxmmqd }, PREFIX_DATA },
6356     { "vpmovsxbq",      { XM, EXxmmdw }, PREFIX_DATA },
6357     { "vpmovsxwd",      { XM, EXxmmq }, PREFIX_DATA },
6358     { "vpmovsxwq",      { XM, EXxmmqd }, PREFIX_DATA },
6359     { "vpmovsxdq",      { XM, EXxmmq }, PREFIX_DATA },
6360     { Bad_Opcode },
6361     { Bad_Opcode },
6362     /* 28 */
6363     { "vpmuldq",        { XM, Vex, EXx }, PREFIX_DATA },
6364     { "vpcmpeqq",       { XM, Vex, EXx }, PREFIX_DATA },
6365     { MOD_TABLE (MOD_VEX_0F382A) },
6366     { "vpackusdw",      { XM, Vex, EXx }, PREFIX_DATA },
6367     { MOD_TABLE (MOD_VEX_0F382C) },
6368     { MOD_TABLE (MOD_VEX_0F382D) },
6369     { MOD_TABLE (MOD_VEX_0F382E) },
6370     { MOD_TABLE (MOD_VEX_0F382F) },
6371     /* 30 */
6372     { "vpmovzxbw",      { XM, EXxmmq }, PREFIX_DATA },
6373     { "vpmovzxbd",      { XM, EXxmmqd }, PREFIX_DATA },
6374     { "vpmovzxbq",      { XM, EXxmmdw }, PREFIX_DATA },
6375     { "vpmovzxwd",      { XM, EXxmmq }, PREFIX_DATA },
6376     { "vpmovzxwq",      { XM, EXxmmqd }, PREFIX_DATA },
6377     { "vpmovzxdq",      { XM, EXxmmq }, PREFIX_DATA },
6378     { VEX_LEN_TABLE (VEX_LEN_0F3836) },
6379     { "vpcmpgtq",       { XM, Vex, EXx }, PREFIX_DATA },
6380     /* 38 */
6381     { "vpminsb",        { XM, Vex, EXx }, PREFIX_DATA },
6382     { "vpminsd",        { XM, Vex, EXx }, PREFIX_DATA },
6383     { "vpminuw",        { XM, Vex, EXx }, PREFIX_DATA },
6384     { "vpminud",        { XM, Vex, EXx }, PREFIX_DATA },
6385     { "vpmaxsb",        { XM, Vex, EXx }, PREFIX_DATA },
6386     { "vpmaxsd",        { XM, Vex, EXx }, PREFIX_DATA },
6387     { "vpmaxuw",        { XM, Vex, EXx }, PREFIX_DATA },
6388     { "vpmaxud",        { XM, Vex, EXx }, PREFIX_DATA },
6389     /* 40 */
6390     { "vpmulld",        { XM, Vex, EXx }, PREFIX_DATA },
6391     { VEX_LEN_TABLE (VEX_LEN_0F3841) },
6392     { Bad_Opcode },
6393     { Bad_Opcode },
6394     { Bad_Opcode },
6395     { "vpsrlv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6396     { VEX_W_TABLE (VEX_W_0F3846) },
6397     { "vpsllv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6398     /* 48 */
6399     { Bad_Opcode },
6400     { X86_64_TABLE (X86_64_VEX_0F3849) },
6401     { Bad_Opcode },
6402     { X86_64_TABLE (X86_64_VEX_0F384B) },
6403     { Bad_Opcode },
6404     { Bad_Opcode },
6405     { Bad_Opcode },
6406     { Bad_Opcode },
6407     /* 50 */
6408     { VEX_W_TABLE (VEX_W_0F3850) },
6409     { VEX_W_TABLE (VEX_W_0F3851) },
6410     { VEX_W_TABLE (VEX_W_0F3852) },
6411     { VEX_W_TABLE (VEX_W_0F3853) },
6412     { Bad_Opcode },
6413     { Bad_Opcode },
6414     { Bad_Opcode },
6415     { Bad_Opcode },
6416     /* 58 */
6417     { VEX_W_TABLE (VEX_W_0F3858) },
6418     { VEX_W_TABLE (VEX_W_0F3859) },
6419     { MOD_TABLE (MOD_VEX_0F385A) },
6420     { Bad_Opcode },
6421     { X86_64_TABLE (X86_64_VEX_0F385C) },
6422     { Bad_Opcode },
6423     { X86_64_TABLE (X86_64_VEX_0F385E) },
6424     { Bad_Opcode },
6425     /* 60 */
6426     { Bad_Opcode },
6427     { Bad_Opcode },
6428     { Bad_Opcode },
6429     { Bad_Opcode },
6430     { Bad_Opcode },
6431     { Bad_Opcode },
6432     { Bad_Opcode },
6433     { Bad_Opcode },
6434     /* 68 */
6435     { Bad_Opcode },
6436     { Bad_Opcode },
6437     { Bad_Opcode },
6438     { Bad_Opcode },
6439     { Bad_Opcode },
6440     { Bad_Opcode },
6441     { Bad_Opcode },
6442     { Bad_Opcode },
6443     /* 70 */
6444     { Bad_Opcode },
6445     { Bad_Opcode },
6446     { PREFIX_TABLE (PREFIX_VEX_0F3872) },
6447     { Bad_Opcode },
6448     { Bad_Opcode },
6449     { Bad_Opcode },
6450     { Bad_Opcode },
6451     { Bad_Opcode },
6452     /* 78 */
6453     { VEX_W_TABLE (VEX_W_0F3878) },
6454     { VEX_W_TABLE (VEX_W_0F3879) },
6455     { Bad_Opcode },
6456     { Bad_Opcode },
6457     { Bad_Opcode },
6458     { Bad_Opcode },
6459     { Bad_Opcode },
6460     { Bad_Opcode },
6461     /* 80 */
6462     { Bad_Opcode },
6463     { Bad_Opcode },
6464     { Bad_Opcode },
6465     { Bad_Opcode },
6466     { Bad_Opcode },
6467     { Bad_Opcode },
6468     { Bad_Opcode },
6469     { Bad_Opcode },
6470     /* 88 */
6471     { Bad_Opcode },
6472     { Bad_Opcode },
6473     { Bad_Opcode },
6474     { Bad_Opcode },
6475     { MOD_TABLE (MOD_VEX_0F388C) },
6476     { Bad_Opcode },
6477     { MOD_TABLE (MOD_VEX_0F388E) },
6478     { Bad_Opcode },
6479     /* 90 */
6480     { "vpgatherd%DQ", { XM, MVexVSIBDWpX, VexGatherD }, PREFIX_DATA },
6481     { "vpgatherq%DQ", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6482     { "vgatherdp%XW", { XM, MVexVSIBDWpX, VexGatherD }, PREFIX_DATA },
6483     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6484     { Bad_Opcode },
6485     { Bad_Opcode },
6486     { "vfmaddsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6487     { "vfmsubadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6488     /* 98 */
6489     { "vfmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6490     { "vfmadd132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6491     { "vfmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6492     { "vfmsub132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6493     { "vfnmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6494     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6495     { "vfnmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6496     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6497     /* a0 */
6498     { Bad_Opcode },
6499     { Bad_Opcode },
6500     { Bad_Opcode },
6501     { Bad_Opcode },
6502     { Bad_Opcode },
6503     { Bad_Opcode },
6504     { "vfmaddsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6505     { "vfmsubadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6506     /* a8 */
6507     { "vfmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6508     { "vfmadd213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6509     { "vfmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6510     { "vfmsub213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6511     { "vfnmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6512     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6513     { "vfnmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6514     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6515     /* b0 */
6516     { VEX_W_TABLE (VEX_W_0F38B0) },
6517     { VEX_W_TABLE (VEX_W_0F38B1) },
6518     { Bad_Opcode },
6519     { Bad_Opcode },
6520     { VEX_W_TABLE (VEX_W_0F38B4) },
6521     { VEX_W_TABLE (VEX_W_0F38B5) },
6522     { "vfmaddsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6523     { "vfmsubadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6524     /* b8 */
6525     { "vfmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6526     { "vfmadd231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6527     { "vfmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6528     { "vfmsub231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6529     { "vfnmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6530     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6531     { "vfnmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6532     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6533     /* c0 */
6534     { Bad_Opcode },
6535     { Bad_Opcode },
6536     { Bad_Opcode },
6537     { Bad_Opcode },
6538     { Bad_Opcode },
6539     { Bad_Opcode },
6540     { Bad_Opcode },
6541     { Bad_Opcode },
6542     /* c8 */
6543     { Bad_Opcode },
6544     { Bad_Opcode },
6545     { Bad_Opcode },
6546     { Bad_Opcode },
6547     { Bad_Opcode },
6548     { Bad_Opcode },
6549     { Bad_Opcode },
6550     { VEX_W_TABLE (VEX_W_0F38CF) },
6551     /* d0 */
6552     { Bad_Opcode },
6553     { Bad_Opcode },
6554     { Bad_Opcode },
6555     { Bad_Opcode },
6556     { Bad_Opcode },
6557     { Bad_Opcode },
6558     { Bad_Opcode },
6559     { Bad_Opcode },
6560     /* d8 */
6561     { Bad_Opcode },
6562     { Bad_Opcode },
6563     { Bad_Opcode },
6564     { VEX_LEN_TABLE (VEX_LEN_0F38DB) },
6565     { "vaesenc",        { XM, Vex, EXx }, PREFIX_DATA },
6566     { "vaesenclast",    { XM, Vex, EXx }, PREFIX_DATA },
6567     { "vaesdec",        { XM, Vex, EXx }, PREFIX_DATA },
6568     { "vaesdeclast",    { XM, Vex, EXx }, PREFIX_DATA },
6569     /* e0 */
6570     { X86_64_TABLE (X86_64_VEX_0F38E0) },
6571     { X86_64_TABLE (X86_64_VEX_0F38E1) },
6572     { X86_64_TABLE (X86_64_VEX_0F38E2) },
6573     { X86_64_TABLE (X86_64_VEX_0F38E3) },
6574     { X86_64_TABLE (X86_64_VEX_0F38E4) },
6575     { X86_64_TABLE (X86_64_VEX_0F38E5) },
6576     { X86_64_TABLE (X86_64_VEX_0F38E6) },
6577     { X86_64_TABLE (X86_64_VEX_0F38E7) },
6578     /* e8 */
6579     { X86_64_TABLE (X86_64_VEX_0F38E8) },
6580     { X86_64_TABLE (X86_64_VEX_0F38E9) },
6581     { X86_64_TABLE (X86_64_VEX_0F38EA) },
6582     { X86_64_TABLE (X86_64_VEX_0F38EB) },
6583     { X86_64_TABLE (X86_64_VEX_0F38EC) },
6584     { X86_64_TABLE (X86_64_VEX_0F38ED) },
6585     { X86_64_TABLE (X86_64_VEX_0F38EE) },
6586     { X86_64_TABLE (X86_64_VEX_0F38EF) },
6587     /* f0 */
6588     { Bad_Opcode },
6589     { Bad_Opcode },
6590     { VEX_LEN_TABLE (VEX_LEN_0F38F2) },
6591     { VEX_LEN_TABLE (VEX_LEN_0F38F3) },
6592     { Bad_Opcode },
6593     { VEX_LEN_TABLE (VEX_LEN_0F38F5) },
6594     { VEX_LEN_TABLE (VEX_LEN_0F38F6) },
6595     { VEX_LEN_TABLE (VEX_LEN_0F38F7) },
6596     /* f8 */
6597     { Bad_Opcode },
6598     { Bad_Opcode },
6599     { Bad_Opcode },
6600     { Bad_Opcode },
6601     { Bad_Opcode },
6602     { Bad_Opcode },
6603     { Bad_Opcode },
6604     { Bad_Opcode },
6605   },
6606   /* VEX_0F3A */
6607   {
6608     /* 00 */
6609     { VEX_LEN_TABLE (VEX_LEN_0F3A00) },
6610     { VEX_LEN_TABLE (VEX_LEN_0F3A01) },
6611     { VEX_W_TABLE (VEX_W_0F3A02) },
6612     { Bad_Opcode },
6613     { VEX_W_TABLE (VEX_W_0F3A04) },
6614     { VEX_W_TABLE (VEX_W_0F3A05) },
6615     { VEX_LEN_TABLE (VEX_LEN_0F3A06) },
6616     { Bad_Opcode },
6617     /* 08 */
6618     { "vroundps",       { XM, EXx, Ib }, PREFIX_DATA },
6619     { "vroundpd",       { XM, EXx, Ib }, PREFIX_DATA },
6620     { "vroundss",       { XMScalar, VexScalar, EXd, Ib }, PREFIX_DATA },
6621     { "vroundsd",       { XMScalar, VexScalar, EXq, Ib }, PREFIX_DATA },
6622     { "vblendps",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6623     { "vblendpd",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6624     { "vpblendw",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6625     { "vpalignr",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6626     /* 10 */
6627     { Bad_Opcode },
6628     { Bad_Opcode },
6629     { Bad_Opcode },
6630     { Bad_Opcode },
6631     { VEX_LEN_TABLE (VEX_LEN_0F3A14) },
6632     { VEX_LEN_TABLE (VEX_LEN_0F3A15) },
6633     { VEX_LEN_TABLE (VEX_LEN_0F3A16) },
6634     { VEX_LEN_TABLE (VEX_LEN_0F3A17) },
6635     /* 18 */
6636     { VEX_LEN_TABLE (VEX_LEN_0F3A18) },
6637     { VEX_LEN_TABLE (VEX_LEN_0F3A19) },
6638     { Bad_Opcode },
6639     { Bad_Opcode },
6640     { Bad_Opcode },
6641     { VEX_W_TABLE (VEX_W_0F3A1D) },
6642     { Bad_Opcode },
6643     { Bad_Opcode },
6644     /* 20 */
6645     { VEX_LEN_TABLE (VEX_LEN_0F3A20) },
6646     { VEX_LEN_TABLE (VEX_LEN_0F3A21) },
6647     { VEX_LEN_TABLE (VEX_LEN_0F3A22) },
6648     { Bad_Opcode },
6649     { Bad_Opcode },
6650     { Bad_Opcode },
6651     { Bad_Opcode },
6652     { Bad_Opcode },
6653     /* 28 */
6654     { Bad_Opcode },
6655     { Bad_Opcode },
6656     { Bad_Opcode },
6657     { Bad_Opcode },
6658     { Bad_Opcode },
6659     { Bad_Opcode },
6660     { Bad_Opcode },
6661     { Bad_Opcode },
6662     /* 30 */
6663     { VEX_LEN_TABLE (VEX_LEN_0F3A30) },
6664     { VEX_LEN_TABLE (VEX_LEN_0F3A31) },
6665     { VEX_LEN_TABLE (VEX_LEN_0F3A32) },
6666     { VEX_LEN_TABLE (VEX_LEN_0F3A33) },
6667     { Bad_Opcode },
6668     { Bad_Opcode },
6669     { Bad_Opcode },
6670     { Bad_Opcode },
6671     /* 38 */
6672     { VEX_LEN_TABLE (VEX_LEN_0F3A38) },
6673     { VEX_LEN_TABLE (VEX_LEN_0F3A39) },
6674     { Bad_Opcode },
6675     { Bad_Opcode },
6676     { Bad_Opcode },
6677     { Bad_Opcode },
6678     { Bad_Opcode },
6679     { Bad_Opcode },
6680     /* 40 */
6681     { "vdpps",          { XM, Vex, EXx, Ib }, PREFIX_DATA },
6682     { VEX_LEN_TABLE (VEX_LEN_0F3A41) },
6683     { "vmpsadbw",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6684     { Bad_Opcode },
6685     { "vpclmulqdq",     { XM, Vex, EXx, PCLMUL }, PREFIX_DATA },
6686     { Bad_Opcode },
6687     { VEX_LEN_TABLE (VEX_LEN_0F3A46) },
6688     { Bad_Opcode },
6689     /* 48 */
6690     { "vpermil2ps",     { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6691     { "vpermil2pd",     { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6692     { VEX_W_TABLE (VEX_W_0F3A4A) },
6693     { VEX_W_TABLE (VEX_W_0F3A4B) },
6694     { VEX_W_TABLE (VEX_W_0F3A4C) },
6695     { Bad_Opcode },
6696     { Bad_Opcode },
6697     { Bad_Opcode },
6698     /* 50 */
6699     { Bad_Opcode },
6700     { Bad_Opcode },
6701     { Bad_Opcode },
6702     { Bad_Opcode },
6703     { Bad_Opcode },
6704     { Bad_Opcode },
6705     { Bad_Opcode },
6706     { Bad_Opcode },
6707     /* 58 */
6708     { Bad_Opcode },
6709     { Bad_Opcode },
6710     { Bad_Opcode },
6711     { Bad_Opcode },
6712     { "vfmaddsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6713     { "vfmaddsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6714     { "vfmsubaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6715     { "vfmsubaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6716     /* 60 */
6717     { VEX_LEN_TABLE (VEX_LEN_0F3A60) },
6718     { VEX_LEN_TABLE (VEX_LEN_0F3A61) },
6719     { VEX_LEN_TABLE (VEX_LEN_0F3A62) },
6720     { VEX_LEN_TABLE (VEX_LEN_0F3A63) },
6721     { Bad_Opcode },
6722     { Bad_Opcode },
6723     { Bad_Opcode },
6724     { Bad_Opcode },
6725     /* 68 */
6726     { "vfmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6727     { "vfmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6728     { "vfmaddss",       { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6729     { "vfmaddsd",       { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6730     { "vfmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6731     { "vfmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6732     { "vfmsubss",       { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6733     { "vfmsubsd",       { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6734     /* 70 */
6735     { Bad_Opcode },
6736     { Bad_Opcode },
6737     { Bad_Opcode },
6738     { Bad_Opcode },
6739     { Bad_Opcode },
6740     { Bad_Opcode },
6741     { Bad_Opcode },
6742     { Bad_Opcode },
6743     /* 78 */
6744     { "vfnmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6745     { "vfnmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6746     { "vfnmaddss",      { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6747     { "vfnmaddsd",      { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6748     { "vfnmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6749     { "vfnmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6750     { "vfnmsubss",      { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6751     { "vfnmsubsd",      { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6752     /* 80 */
6753     { Bad_Opcode },
6754     { Bad_Opcode },
6755     { Bad_Opcode },
6756     { Bad_Opcode },
6757     { Bad_Opcode },
6758     { Bad_Opcode },
6759     { Bad_Opcode },
6760     { Bad_Opcode },
6761     /* 88 */
6762     { Bad_Opcode },
6763     { Bad_Opcode },
6764     { Bad_Opcode },
6765     { Bad_Opcode },
6766     { Bad_Opcode },
6767     { Bad_Opcode },
6768     { Bad_Opcode },
6769     { Bad_Opcode },
6770     /* 90 */
6771     { Bad_Opcode },
6772     { Bad_Opcode },
6773     { Bad_Opcode },
6774     { Bad_Opcode },
6775     { Bad_Opcode },
6776     { Bad_Opcode },
6777     { Bad_Opcode },
6778     { Bad_Opcode },
6779     /* 98 */
6780     { Bad_Opcode },
6781     { Bad_Opcode },
6782     { Bad_Opcode },
6783     { Bad_Opcode },
6784     { Bad_Opcode },
6785     { Bad_Opcode },
6786     { Bad_Opcode },
6787     { Bad_Opcode },
6788     /* a0 */
6789     { Bad_Opcode },
6790     { Bad_Opcode },
6791     { Bad_Opcode },
6792     { Bad_Opcode },
6793     { Bad_Opcode },
6794     { Bad_Opcode },
6795     { Bad_Opcode },
6796     { Bad_Opcode },
6797     /* a8 */
6798     { Bad_Opcode },
6799     { Bad_Opcode },
6800     { Bad_Opcode },
6801     { Bad_Opcode },
6802     { Bad_Opcode },
6803     { Bad_Opcode },
6804     { Bad_Opcode },
6805     { Bad_Opcode },
6806     /* b0 */
6807     { Bad_Opcode },
6808     { Bad_Opcode },
6809     { Bad_Opcode },
6810     { Bad_Opcode },
6811     { Bad_Opcode },
6812     { Bad_Opcode },
6813     { Bad_Opcode },
6814     { Bad_Opcode },
6815     /* b8 */
6816     { Bad_Opcode },
6817     { Bad_Opcode },
6818     { Bad_Opcode },
6819     { Bad_Opcode },
6820     { Bad_Opcode },
6821     { Bad_Opcode },
6822     { Bad_Opcode },
6823     { Bad_Opcode },
6824     /* c0 */
6825     { Bad_Opcode },
6826     { Bad_Opcode },
6827     { Bad_Opcode },
6828     { Bad_Opcode },
6829     { Bad_Opcode },
6830     { Bad_Opcode },
6831     { Bad_Opcode },
6832     { Bad_Opcode },
6833     /* c8 */
6834     { Bad_Opcode },
6835     { Bad_Opcode },
6836     { Bad_Opcode },
6837     { Bad_Opcode },
6838     { Bad_Opcode },
6839     { Bad_Opcode },
6840     { VEX_W_TABLE (VEX_W_0F3ACE) },
6841     { VEX_W_TABLE (VEX_W_0F3ACF) },
6842     /* d0 */
6843     { Bad_Opcode },
6844     { Bad_Opcode },
6845     { Bad_Opcode },
6846     { Bad_Opcode },
6847     { Bad_Opcode },
6848     { Bad_Opcode },
6849     { Bad_Opcode },
6850     { Bad_Opcode },
6851     /* d8 */
6852     { Bad_Opcode },
6853     { Bad_Opcode },
6854     { Bad_Opcode },
6855     { Bad_Opcode },
6856     { Bad_Opcode },
6857     { Bad_Opcode },
6858     { Bad_Opcode },
6859     { VEX_LEN_TABLE (VEX_LEN_0F3ADF) },
6860     /* e0 */
6861     { Bad_Opcode },
6862     { Bad_Opcode },
6863     { Bad_Opcode },
6864     { Bad_Opcode },
6865     { Bad_Opcode },
6866     { Bad_Opcode },
6867     { Bad_Opcode },
6868     { Bad_Opcode },
6869     /* e8 */
6870     { Bad_Opcode },
6871     { Bad_Opcode },
6872     { Bad_Opcode },
6873     { Bad_Opcode },
6874     { Bad_Opcode },
6875     { Bad_Opcode },
6876     { Bad_Opcode },
6877     { Bad_Opcode },
6878     /* f0 */
6879     { VEX_LEN_TABLE (VEX_LEN_0F3AF0) },
6880     { Bad_Opcode },
6881     { Bad_Opcode },
6882     { Bad_Opcode },
6883     { Bad_Opcode },
6884     { Bad_Opcode },
6885     { Bad_Opcode },
6886     { Bad_Opcode },
6887     /* f8 */
6888     { Bad_Opcode },
6889     { Bad_Opcode },
6890     { Bad_Opcode },
6891     { Bad_Opcode },
6892     { Bad_Opcode },
6893     { Bad_Opcode },
6894     { Bad_Opcode },
6895     { Bad_Opcode },
6896   },
6897 };
6898
6899 #include "i386-dis-evex.h"
6900
6901 static const struct dis386 vex_len_table[][2] = {
6902   /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */
6903   {
6904     { "%XEvmovlpX",     { XM, Vex, EXq }, 0 },
6905   },
6906
6907   /* VEX_LEN_0F12_P_0_M_1 */
6908   {
6909     { "%XEvmovhlp%XS",  { XM, Vex, EXq }, 0 },
6910   },
6911
6912   /* VEX_LEN_0F13_M_0 */
6913   {
6914     { "%XEvmovlpX",     { EXq, XM }, PREFIX_OPCODE },
6915   },
6916
6917   /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */
6918   {
6919     { "%XEvmovhpX",     { XM, Vex, EXq }, 0 },
6920   },
6921
6922   /* VEX_LEN_0F16_P_0_M_1 */
6923   {
6924     { "%XEvmovlhp%XS",  { XM, Vex, EXq }, 0 },
6925   },
6926
6927   /* VEX_LEN_0F17_M_0 */
6928   {
6929     { "%XEvmovhpX",     { EXq, XM }, PREFIX_OPCODE },
6930   },
6931
6932   /* VEX_LEN_0F41 */
6933   {
6934     { Bad_Opcode },
6935     { MOD_TABLE (MOD_VEX_0F41_L_1) },
6936   },
6937
6938   /* VEX_LEN_0F42 */
6939   {
6940     { Bad_Opcode },
6941     { MOD_TABLE (MOD_VEX_0F42_L_1) },
6942   },
6943
6944   /* VEX_LEN_0F44 */
6945   {
6946     { MOD_TABLE (MOD_VEX_0F44_L_0) },
6947   },
6948
6949   /* VEX_LEN_0F45 */
6950   {
6951     { Bad_Opcode },
6952     { MOD_TABLE (MOD_VEX_0F45_L_1) },
6953   },
6954
6955   /* VEX_LEN_0F46 */
6956   {
6957     { Bad_Opcode },
6958     { MOD_TABLE (MOD_VEX_0F46_L_1) },
6959   },
6960
6961   /* VEX_LEN_0F47 */
6962   {
6963     { Bad_Opcode },
6964     { MOD_TABLE (MOD_VEX_0F47_L_1) },
6965   },
6966
6967   /* VEX_LEN_0F4A */
6968   {
6969     { Bad_Opcode },
6970     { MOD_TABLE (MOD_VEX_0F4A_L_1) },
6971   },
6972
6973   /* VEX_LEN_0F4B */
6974   {
6975     { Bad_Opcode },
6976     { MOD_TABLE (MOD_VEX_0F4B_L_1) },
6977   },
6978
6979   /* VEX_LEN_0F6E */
6980   {
6981     { "%XEvmovK",       { XMScalar, Edq }, PREFIX_DATA },
6982   },
6983
6984   /* VEX_LEN_0F77 */
6985   {
6986     { "vzeroupper",     { XX }, 0 },
6987     { "vzeroall",       { XX }, 0 },
6988   },
6989
6990   /* VEX_LEN_0F7E_P_1 */
6991   {
6992     { "%XEvmovq",       { XMScalar, EXq }, 0 },
6993   },
6994
6995   /* VEX_LEN_0F7E_P_2 */
6996   {
6997     { "%XEvmovK",       { Edq, XMScalar }, 0 },
6998   },
6999
7000   /* VEX_LEN_0F90 */
7001   {
7002     { VEX_W_TABLE (VEX_W_0F90_L_0) },
7003   },
7004
7005   /* VEX_LEN_0F91 */
7006   {
7007     { MOD_TABLE (MOD_VEX_0F91_L_0) },
7008   },
7009
7010   /* VEX_LEN_0F92 */
7011   {
7012     { MOD_TABLE (MOD_VEX_0F92_L_0) },
7013   },
7014
7015   /* VEX_LEN_0F93 */
7016   {
7017     { MOD_TABLE (MOD_VEX_0F93_L_0) },
7018   },
7019
7020   /* VEX_LEN_0F98 */
7021   {
7022     { MOD_TABLE (MOD_VEX_0F98_L_0) },
7023   },
7024
7025   /* VEX_LEN_0F99 */
7026   {
7027     { MOD_TABLE (MOD_VEX_0F99_L_0) },
7028   },
7029
7030   /* VEX_LEN_0FAE_R_2_M_0 */
7031   {
7032     { "vldmxcsr",       { Md }, 0 },
7033   },
7034
7035   /* VEX_LEN_0FAE_R_3_M_0 */
7036   {
7037     { "vstmxcsr",       { Md }, 0 },
7038   },
7039
7040   /* VEX_LEN_0FC4 */
7041   {
7042     { "%XEvpinsrw",     { XM, Vex, Edw, Ib }, PREFIX_DATA },
7043   },
7044
7045   /* VEX_LEN_0FC5 */
7046   {
7047     { "%XEvpextrw",     { Gd, XS, Ib }, PREFIX_DATA },
7048   },
7049
7050   /* VEX_LEN_0FD6 */
7051   {
7052     { "%XEvmovq",       { EXqS, XMScalar }, PREFIX_DATA },
7053   },
7054
7055   /* VEX_LEN_0FF7 */
7056   {
7057     { "vmaskmovdqu",    { XM, XS }, PREFIX_DATA },
7058   },
7059
7060   /* VEX_LEN_0F3816 */
7061   {
7062     { Bad_Opcode },
7063     { VEX_W_TABLE (VEX_W_0F3816_L_1) },
7064   },
7065
7066   /* VEX_LEN_0F3819 */
7067   {
7068     { Bad_Opcode },
7069     { VEX_W_TABLE (VEX_W_0F3819_L_1) },
7070   },
7071
7072   /* VEX_LEN_0F381A_M_0 */
7073   {
7074     { Bad_Opcode },
7075     { VEX_W_TABLE (VEX_W_0F381A_M_0_L_1) },
7076   },
7077
7078   /* VEX_LEN_0F3836 */
7079   {
7080     { Bad_Opcode },
7081     { VEX_W_TABLE (VEX_W_0F3836) },
7082   },
7083
7084   /* VEX_LEN_0F3841 */
7085   {
7086     { "vphminposuw",    { XM, EXx }, PREFIX_DATA },
7087   },
7088
7089    /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_0 */
7090   {
7091     { "ldtilecfg", { M }, 0 },
7092   },
7093
7094   /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0 */
7095   {
7096     { "tilerelease", { Skip_MODRM }, 0 },
7097   },
7098
7099   /* VEX_LEN_0F3849_X86_64_P_2_W_0_M_0 */
7100   {
7101     { "sttilecfg", { M }, 0 },
7102   },
7103
7104   /* VEX_LEN_0F3849_X86_64_P_3_W_0_M_0 */
7105   {
7106     { "tilezero", { TMM, Skip_MODRM }, 0 },
7107   },
7108
7109   /* VEX_LEN_0F384B_X86_64_P_1_W_0_M_0 */
7110   {
7111     { "tilestored", { MVexSIBMEM, TMM }, 0 },
7112   },
7113   /* VEX_LEN_0F384B_X86_64_P_2_W_0_M_0 */
7114   {
7115     { "tileloaddt1", { TMM, MVexSIBMEM }, 0 },
7116   },
7117
7118   /* VEX_LEN_0F384B_X86_64_P_3_W_0_M_0 */
7119   {
7120     { "tileloadd", { TMM, MVexSIBMEM }, 0 },
7121   },
7122
7123   /* VEX_LEN_0F385A_M_0 */
7124   {
7125     { Bad_Opcode },
7126     { VEX_W_TABLE (VEX_W_0F385A_M_0_L_0) },
7127   },
7128
7129   /* VEX_LEN_0F385C_X86_64_P_1_W_0_M_0 */
7130   {
7131     { "tdpbf16ps", { TMM, EXtmm, VexTmm }, 0 },
7132   },
7133
7134   /* VEX_LEN_0F385C_X86_64_P_3_W_0_M_0 */
7135   {
7136     { "tdpfp16ps", { TMM, EXtmm, VexTmm }, 0 },
7137   },
7138
7139   /* VEX_LEN_0F385E_X86_64_P_0_W_0_M_0 */
7140   {
7141     { "tdpbuud", {TMM, EXtmm, VexTmm }, 0 },
7142   },
7143
7144   /* VEX_LEN_0F385E_X86_64_P_1_W_0_M_0 */
7145   {
7146     { "tdpbsud", {TMM, EXtmm, VexTmm }, 0 },
7147   },
7148
7149   /* VEX_LEN_0F385E_X86_64_P_2_W_0_M_0 */
7150   {
7151     { "tdpbusd", {TMM, EXtmm, VexTmm }, 0 },
7152   },
7153
7154   /* VEX_LEN_0F385E_X86_64_P_3_W_0_M_0 */
7155   {
7156     { "tdpbssd", {TMM, EXtmm, VexTmm }, 0 },
7157   },
7158
7159   /* VEX_LEN_0F38DB */
7160   {
7161     { "vaesimc",        { XM, EXx }, PREFIX_DATA },
7162   },
7163
7164   /* VEX_LEN_0F38F2 */
7165   {
7166     { "andnS",          { Gdq, VexGdq, Edq }, PREFIX_OPCODE },
7167   },
7168
7169   /* VEX_LEN_0F38F3 */
7170   {
7171     { REG_TABLE(REG_VEX_0F38F3_L_0) },
7172   },
7173
7174   /* VEX_LEN_0F38F5 */
7175   {
7176     { PREFIX_TABLE(PREFIX_VEX_0F38F5_L_0) },
7177   },
7178
7179   /* VEX_LEN_0F38F6 */
7180   {
7181     { PREFIX_TABLE(PREFIX_VEX_0F38F6_L_0) },
7182   },
7183
7184   /* VEX_LEN_0F38F7 */
7185   {
7186     { PREFIX_TABLE(PREFIX_VEX_0F38F7_L_0) },
7187   },
7188
7189   /* VEX_LEN_0F3A00 */
7190   {
7191     { Bad_Opcode },
7192     { VEX_W_TABLE (VEX_W_0F3A00_L_1) },
7193   },
7194
7195   /* VEX_LEN_0F3A01 */
7196   {
7197     { Bad_Opcode },
7198     { VEX_W_TABLE (VEX_W_0F3A01_L_1) },
7199   },
7200
7201   /* VEX_LEN_0F3A06 */
7202   {
7203     { Bad_Opcode },
7204     { VEX_W_TABLE (VEX_W_0F3A06_L_1) },
7205   },
7206
7207   /* VEX_LEN_0F3A14 */
7208   {
7209     { "%XEvpextrb",     { Edb, XM, Ib }, PREFIX_DATA },
7210   },
7211
7212   /* VEX_LEN_0F3A15 */
7213   {
7214     { "%XEvpextrw",     { Edw, XM, Ib }, PREFIX_DATA },
7215   },
7216
7217   /* VEX_LEN_0F3A16  */
7218   {
7219     { "%XEvpextrK",     { Edq, XM, Ib }, PREFIX_DATA },
7220   },
7221
7222   /* VEX_LEN_0F3A17 */
7223   {
7224     { "%XEvextractps",  { Ed, XM, Ib }, PREFIX_DATA },
7225   },
7226
7227   /* VEX_LEN_0F3A18 */
7228   {
7229     { Bad_Opcode },
7230     { VEX_W_TABLE (VEX_W_0F3A18_L_1) },
7231   },
7232
7233   /* VEX_LEN_0F3A19 */
7234   {
7235     { Bad_Opcode },
7236     { VEX_W_TABLE (VEX_W_0F3A19_L_1) },
7237   },
7238
7239   /* VEX_LEN_0F3A20 */
7240   {
7241     { "%XEvpinsrb",     { XM, Vex, Edb, Ib }, PREFIX_DATA },
7242   },
7243
7244   /* VEX_LEN_0F3A21 */
7245   {
7246     { "%XEvinsertps",   { XM, Vex, EXd, Ib }, PREFIX_DATA },
7247   },
7248
7249   /* VEX_LEN_0F3A22 */
7250   {
7251     { "%XEvpinsrK",     { XM, Vex, Edq, Ib }, PREFIX_DATA },
7252   },
7253
7254   /* VEX_LEN_0F3A30 */
7255   {
7256     { MOD_TABLE (MOD_VEX_0F3A30_L_0) },
7257   },
7258
7259   /* VEX_LEN_0F3A31 */
7260   {
7261     { MOD_TABLE (MOD_VEX_0F3A31_L_0) },
7262   },
7263
7264   /* VEX_LEN_0F3A32 */
7265   {
7266     { MOD_TABLE (MOD_VEX_0F3A32_L_0) },
7267   },
7268
7269   /* VEX_LEN_0F3A33 */
7270   {
7271     { MOD_TABLE (MOD_VEX_0F3A33_L_0) },
7272   },
7273
7274   /* VEX_LEN_0F3A38 */
7275   {
7276     { Bad_Opcode },
7277     { VEX_W_TABLE (VEX_W_0F3A38_L_1) },
7278   },
7279
7280   /* VEX_LEN_0F3A39 */
7281   {
7282     { Bad_Opcode },
7283     { VEX_W_TABLE (VEX_W_0F3A39_L_1) },
7284   },
7285
7286   /* VEX_LEN_0F3A41 */
7287   {
7288     { "vdppd",          { XM, Vex, EXx, Ib }, PREFIX_DATA },
7289   },
7290
7291   /* VEX_LEN_0F3A46 */
7292   {
7293     { Bad_Opcode },
7294     { VEX_W_TABLE (VEX_W_0F3A46_L_1) },
7295   },
7296
7297   /* VEX_LEN_0F3A60 */
7298   {
7299     { "vpcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7300   },
7301
7302   /* VEX_LEN_0F3A61 */
7303   {
7304     { "vpcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7305   },
7306
7307   /* VEX_LEN_0F3A62 */
7308   {
7309     { "vpcmpistrm",     { XM, EXx, Ib }, PREFIX_DATA },
7310   },
7311
7312   /* VEX_LEN_0F3A63 */
7313   {
7314     { "vpcmpistri",     { XM, EXx, Ib }, PREFIX_DATA },
7315   },
7316
7317   /* VEX_LEN_0F3ADF */
7318   {
7319     { "vaeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
7320   },
7321
7322   /* VEX_LEN_0F3AF0 */
7323   {
7324     { PREFIX_TABLE (PREFIX_VEX_0F3AF0_L_0) },
7325   },
7326
7327   /* VEX_LEN_0FXOP_08_85 */
7328   {
7329     { VEX_W_TABLE (VEX_W_0FXOP_08_85_L_0) },
7330   },
7331
7332   /* VEX_LEN_0FXOP_08_86 */
7333   {
7334     { VEX_W_TABLE (VEX_W_0FXOP_08_86_L_0) },
7335   },
7336
7337   /* VEX_LEN_0FXOP_08_87 */
7338   {
7339     { VEX_W_TABLE (VEX_W_0FXOP_08_87_L_0) },
7340   },
7341
7342   /* VEX_LEN_0FXOP_08_8E */
7343   {
7344     { VEX_W_TABLE (VEX_W_0FXOP_08_8E_L_0) },
7345   },
7346
7347   /* VEX_LEN_0FXOP_08_8F */
7348   {
7349     { VEX_W_TABLE (VEX_W_0FXOP_08_8F_L_0) },
7350   },
7351
7352   /* VEX_LEN_0FXOP_08_95 */
7353   {
7354     { VEX_W_TABLE (VEX_W_0FXOP_08_95_L_0) },
7355   },
7356
7357   /* VEX_LEN_0FXOP_08_96 */
7358   {
7359     { VEX_W_TABLE (VEX_W_0FXOP_08_96_L_0) },
7360   },
7361
7362   /* VEX_LEN_0FXOP_08_97 */
7363   {
7364     { VEX_W_TABLE (VEX_W_0FXOP_08_97_L_0) },
7365   },
7366
7367   /* VEX_LEN_0FXOP_08_9E */
7368   {
7369     { VEX_W_TABLE (VEX_W_0FXOP_08_9E_L_0) },
7370   },
7371
7372   /* VEX_LEN_0FXOP_08_9F */
7373   {
7374     { VEX_W_TABLE (VEX_W_0FXOP_08_9F_L_0) },
7375   },
7376
7377   /* VEX_LEN_0FXOP_08_A3 */
7378   {
7379     { "vpperm",         { XM, Vex, EXx, XMVexI4 }, 0 },
7380   },
7381
7382   /* VEX_LEN_0FXOP_08_A6 */
7383   {
7384     { VEX_W_TABLE (VEX_W_0FXOP_08_A6_L_0) },
7385   },
7386
7387   /* VEX_LEN_0FXOP_08_B6 */
7388   {
7389     { VEX_W_TABLE (VEX_W_0FXOP_08_B6_L_0) },
7390   },
7391
7392   /* VEX_LEN_0FXOP_08_C0 */
7393   {
7394     { VEX_W_TABLE (VEX_W_0FXOP_08_C0_L_0) },
7395   },
7396
7397   /* VEX_LEN_0FXOP_08_C1 */
7398   {
7399     { VEX_W_TABLE (VEX_W_0FXOP_08_C1_L_0) },
7400   },
7401
7402   /* VEX_LEN_0FXOP_08_C2 */
7403   {
7404     { VEX_W_TABLE (VEX_W_0FXOP_08_C2_L_0) },
7405   },
7406
7407   /* VEX_LEN_0FXOP_08_C3 */
7408   {
7409     { VEX_W_TABLE (VEX_W_0FXOP_08_C3_L_0) },
7410   },
7411
7412   /* VEX_LEN_0FXOP_08_CC */
7413   {
7414     { VEX_W_TABLE (VEX_W_0FXOP_08_CC_L_0) },
7415   },
7416
7417   /* VEX_LEN_0FXOP_08_CD */
7418   {
7419     { VEX_W_TABLE (VEX_W_0FXOP_08_CD_L_0) },
7420   },
7421
7422   /* VEX_LEN_0FXOP_08_CE */
7423   {
7424     { VEX_W_TABLE (VEX_W_0FXOP_08_CE_L_0) },
7425   },
7426
7427   /* VEX_LEN_0FXOP_08_CF */
7428   {
7429     { VEX_W_TABLE (VEX_W_0FXOP_08_CF_L_0) },
7430   },
7431
7432   /* VEX_LEN_0FXOP_08_EC */
7433   {
7434     { VEX_W_TABLE (VEX_W_0FXOP_08_EC_L_0) },
7435   },
7436
7437   /* VEX_LEN_0FXOP_08_ED */
7438   {
7439     { VEX_W_TABLE (VEX_W_0FXOP_08_ED_L_0) },
7440   },
7441
7442   /* VEX_LEN_0FXOP_08_EE */
7443   {
7444     { VEX_W_TABLE (VEX_W_0FXOP_08_EE_L_0) },
7445   },
7446
7447   /* VEX_LEN_0FXOP_08_EF */
7448   {
7449     { VEX_W_TABLE (VEX_W_0FXOP_08_EF_L_0) },
7450   },
7451
7452   /* VEX_LEN_0FXOP_09_01 */
7453   {
7454     { REG_TABLE (REG_XOP_09_01_L_0) },
7455   },
7456
7457   /* VEX_LEN_0FXOP_09_02 */
7458   {
7459     { REG_TABLE (REG_XOP_09_02_L_0) },
7460   },
7461
7462   /* VEX_LEN_0FXOP_09_12_M_1 */
7463   {
7464     { REG_TABLE (REG_XOP_09_12_M_1_L_0) },
7465   },
7466
7467   /* VEX_LEN_0FXOP_09_82_W_0 */
7468   {
7469     { "vfrczss",        { XM, EXd }, 0 },
7470   },
7471
7472   /* VEX_LEN_0FXOP_09_83_W_0 */
7473   {
7474     { "vfrczsd",        { XM, EXq }, 0 },
7475   },
7476
7477   /* VEX_LEN_0FXOP_09_90 */
7478   {
7479     { "vprotb",         { XM, EXx, VexW }, 0 },
7480   },
7481
7482   /* VEX_LEN_0FXOP_09_91 */
7483   {
7484     { "vprotw",         { XM, EXx, VexW }, 0 },
7485   },
7486
7487   /* VEX_LEN_0FXOP_09_92 */
7488   {
7489     { "vprotd",         { XM, EXx, VexW }, 0 },
7490   },
7491
7492   /* VEX_LEN_0FXOP_09_93 */
7493   {
7494     { "vprotq",         { XM, EXx, VexW }, 0 },
7495   },
7496
7497   /* VEX_LEN_0FXOP_09_94 */
7498   {
7499     { "vpshlb",         { XM, EXx, VexW }, 0 },
7500   },
7501
7502   /* VEX_LEN_0FXOP_09_95 */
7503   {
7504     { "vpshlw",         { XM, EXx, VexW }, 0 },
7505   },
7506
7507   /* VEX_LEN_0FXOP_09_96 */
7508   {
7509     { "vpshld",         { XM, EXx, VexW }, 0 },
7510   },
7511
7512   /* VEX_LEN_0FXOP_09_97 */
7513   {
7514     { "vpshlq",         { XM, EXx, VexW }, 0 },
7515   },
7516
7517   /* VEX_LEN_0FXOP_09_98 */
7518   {
7519     { "vpshab",         { XM, EXx, VexW }, 0 },
7520   },
7521
7522   /* VEX_LEN_0FXOP_09_99 */
7523   {
7524     { "vpshaw",         { XM, EXx, VexW }, 0 },
7525   },
7526
7527   /* VEX_LEN_0FXOP_09_9A */
7528   {
7529     { "vpshad",         { XM, EXx, VexW }, 0 },
7530   },
7531
7532   /* VEX_LEN_0FXOP_09_9B */
7533   {
7534     { "vpshaq",         { XM, EXx, VexW }, 0 },
7535   },
7536
7537   /* VEX_LEN_0FXOP_09_C1 */
7538   {
7539     { VEX_W_TABLE (VEX_W_0FXOP_09_C1_L_0) },
7540   },
7541
7542   /* VEX_LEN_0FXOP_09_C2 */
7543   {
7544     { VEX_W_TABLE (VEX_W_0FXOP_09_C2_L_0) },
7545   },
7546
7547   /* VEX_LEN_0FXOP_09_C3 */
7548   {
7549     { VEX_W_TABLE (VEX_W_0FXOP_09_C3_L_0) },
7550   },
7551
7552   /* VEX_LEN_0FXOP_09_C6 */
7553   {
7554     { VEX_W_TABLE (VEX_W_0FXOP_09_C6_L_0) },
7555   },
7556
7557   /* VEX_LEN_0FXOP_09_C7 */
7558   {
7559     { VEX_W_TABLE (VEX_W_0FXOP_09_C7_L_0) },
7560   },
7561
7562   /* VEX_LEN_0FXOP_09_CB */
7563   {
7564     { VEX_W_TABLE (VEX_W_0FXOP_09_CB_L_0) },
7565   },
7566
7567   /* VEX_LEN_0FXOP_09_D1 */
7568   {
7569     { VEX_W_TABLE (VEX_W_0FXOP_09_D1_L_0) },
7570   },
7571
7572   /* VEX_LEN_0FXOP_09_D2 */
7573   {
7574     { VEX_W_TABLE (VEX_W_0FXOP_09_D2_L_0) },
7575   },
7576
7577   /* VEX_LEN_0FXOP_09_D3 */
7578   {
7579     { VEX_W_TABLE (VEX_W_0FXOP_09_D3_L_0) },
7580   },
7581
7582   /* VEX_LEN_0FXOP_09_D6 */
7583   {
7584     { VEX_W_TABLE (VEX_W_0FXOP_09_D6_L_0) },
7585   },
7586
7587   /* VEX_LEN_0FXOP_09_D7 */
7588   {
7589     { VEX_W_TABLE (VEX_W_0FXOP_09_D7_L_0) },
7590   },
7591
7592   /* VEX_LEN_0FXOP_09_DB */
7593   {
7594     { VEX_W_TABLE (VEX_W_0FXOP_09_DB_L_0) },
7595   },
7596
7597   /* VEX_LEN_0FXOP_09_E1 */
7598   {
7599     { VEX_W_TABLE (VEX_W_0FXOP_09_E1_L_0) },
7600   },
7601
7602   /* VEX_LEN_0FXOP_09_E2 */
7603   {
7604     { VEX_W_TABLE (VEX_W_0FXOP_09_E2_L_0) },
7605   },
7606
7607   /* VEX_LEN_0FXOP_09_E3 */
7608   {
7609     { VEX_W_TABLE (VEX_W_0FXOP_09_E3_L_0) },
7610   },
7611
7612   /* VEX_LEN_0FXOP_0A_12 */
7613   {
7614     { REG_TABLE (REG_XOP_0A_12_L_0) },
7615   },
7616 };
7617
7618 #include "i386-dis-evex-len.h"
7619
7620 static const struct dis386 vex_w_table[][2] = {
7621   {
7622     /* VEX_W_0F41_L_1_M_1 */
7623     { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_M_1_W_0) },
7624     { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_M_1_W_1) },
7625   },
7626   {
7627     /* VEX_W_0F42_L_1_M_1 */
7628     { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_M_1_W_0) },
7629     { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_M_1_W_1) },
7630   },
7631   {
7632     /* VEX_W_0F44_L_0_M_1 */
7633     { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_M_1_W_0) },
7634     { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_M_1_W_1) },
7635   },
7636   {
7637     /* VEX_W_0F45_L_1_M_1 */
7638     { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_M_1_W_0) },
7639     { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_M_1_W_1) },
7640   },
7641   {
7642     /* VEX_W_0F46_L_1_M_1 */
7643     { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_M_1_W_0) },
7644     { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_M_1_W_1) },
7645   },
7646   {
7647     /* VEX_W_0F47_L_1_M_1 */
7648     { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_M_1_W_0) },
7649     { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_M_1_W_1) },
7650   },
7651   {
7652     /* VEX_W_0F4A_L_1_M_1 */
7653     { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_M_1_W_0) },
7654     { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_M_1_W_1) },
7655   },
7656   {
7657     /* VEX_W_0F4B_L_1_M_1 */
7658     { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_M_1_W_0) },
7659     { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_M_1_W_1) },
7660   },
7661   {
7662     /* VEX_W_0F90_L_0 */
7663     { PREFIX_TABLE (PREFIX_VEX_0F90_L_0_W_0) },
7664     { PREFIX_TABLE (PREFIX_VEX_0F90_L_0_W_1) },
7665   },
7666   {
7667     /* VEX_W_0F91_L_0_M_0 */
7668     { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_M_0_W_0) },
7669     { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_M_0_W_1) },
7670   },
7671   {
7672     /* VEX_W_0F92_L_0_M_1 */
7673     { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_M_1_W_0) },
7674     { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_M_1_W_1) },
7675   },
7676   {
7677     /* VEX_W_0F93_L_0_M_1 */
7678     { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_M_1_W_0) },
7679     { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_M_1_W_1) },
7680   },
7681   {
7682     /* VEX_W_0F98_L_0_M_1 */
7683     { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_M_1_W_0) },
7684     { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_M_1_W_1) },
7685   },
7686   {
7687     /* VEX_W_0F99_L_0_M_1 */
7688     { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_M_1_W_0) },
7689     { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_M_1_W_1) },
7690   },
7691   {
7692     /* VEX_W_0F380C  */
7693     { "%XEvpermilps",   { XM, Vex, EXx }, PREFIX_DATA },
7694   },
7695   {
7696     /* VEX_W_0F380D  */
7697     { "vpermilpd",      { XM, Vex, EXx }, PREFIX_DATA },
7698   },
7699   {
7700     /* VEX_W_0F380E  */
7701     { "vtestps",        { XM, EXx }, PREFIX_DATA },
7702   },
7703   {
7704     /* VEX_W_0F380F  */
7705     { "vtestpd",        { XM, EXx }, PREFIX_DATA },
7706   },
7707   {
7708     /* VEX_W_0F3813 */
7709     { "vcvtph2ps", { XM, EXxmmq }, PREFIX_DATA },
7710   },
7711   {
7712     /* VEX_W_0F3816_L_1  */
7713     { "vpermps",        { XM, Vex, EXx }, PREFIX_DATA },
7714   },
7715   {
7716     /* VEX_W_0F3818 */
7717     { "%XEvbroadcastss",        { XM, EXd }, PREFIX_DATA },
7718   },
7719   {
7720     /* VEX_W_0F3819_L_1 */
7721     { "vbroadcastsd",   { XM, EXq }, PREFIX_DATA },
7722   },
7723   {
7724     /* VEX_W_0F381A_M_0_L_1 */
7725     { "vbroadcastf128", { XM, Mxmm }, PREFIX_DATA },
7726   },
7727   {
7728     /* VEX_W_0F382C_M_0 */
7729     { "vmaskmovps",     { XM, Vex, Mx }, PREFIX_DATA },
7730   },
7731   {
7732     /* VEX_W_0F382D_M_0 */
7733     { "vmaskmovpd",     { XM, Vex, Mx }, PREFIX_DATA },
7734   },
7735   {
7736     /* VEX_W_0F382E_M_0 */
7737     { "vmaskmovps",     { Mx, Vex, XM }, PREFIX_DATA },
7738   },
7739   {
7740     /* VEX_W_0F382F_M_0 */
7741     { "vmaskmovpd",     { Mx, Vex, XM }, PREFIX_DATA },
7742   },
7743   {
7744     /* VEX_W_0F3836  */
7745     { "vpermd",         { XM, Vex, EXx }, PREFIX_DATA },
7746   },
7747   {
7748     /* VEX_W_0F3846 */
7749     { "vpsravd",        { XM, Vex, EXx }, PREFIX_DATA },
7750   },
7751   {
7752     /* VEX_W_0F3849_X86_64_P_0 */
7753     { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_0_W_0) },
7754   },
7755   {
7756     /* VEX_W_0F3849_X86_64_P_2 */
7757     { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_2_W_0) },
7758   },
7759   {
7760     /* VEX_W_0F3849_X86_64_P_3 */
7761     { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_3_W_0) },
7762   },
7763   {
7764     /* VEX_W_0F384B_X86_64_P_1 */
7765     { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_1_W_0) },
7766   },
7767   {
7768     /* VEX_W_0F384B_X86_64_P_2 */
7769     { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_2_W_0) },
7770   },
7771   {
7772     /* VEX_W_0F384B_X86_64_P_3 */
7773     { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_3_W_0) },
7774   },
7775   {
7776     /* VEX_W_0F3850 */
7777     { PREFIX_TABLE (PREFIX_VEX_0F3850_W_0) },
7778   },
7779   {
7780     /* VEX_W_0F3851_P_0 */
7781     { PREFIX_TABLE (PREFIX_VEX_0F3851_W_0) },
7782   },
7783   {
7784     /* VEX_W_0F3852 */
7785     { "%XVvpdpwssd",    { XM, Vex, EXx }, PREFIX_DATA },
7786   },
7787   {
7788     /* VEX_W_0F3853 */
7789     { "%XVvpdpwssds",   { XM, Vex, EXx }, PREFIX_DATA },
7790   },
7791   {
7792     /* VEX_W_0F3858 */
7793     { "%XEvpbroadcastd", { XM, EXd }, PREFIX_DATA },
7794   },
7795   {
7796     /* VEX_W_0F3859 */
7797     { "vpbroadcastq", { XM, EXq }, PREFIX_DATA },
7798   },
7799   {
7800     /* VEX_W_0F385A_M_0_L_0 */
7801     { "vbroadcasti128", { XM, Mxmm }, PREFIX_DATA },
7802   },
7803   {
7804     /* VEX_W_0F385C_X86_64_P_1 */
7805     { MOD_TABLE (MOD_VEX_0F385C_X86_64_P_1_W_0) },
7806   },
7807   {
7808     /* VEX_W_0F385C_X86_64_P_3 */
7809     { MOD_TABLE (MOD_VEX_0F385C_X86_64_P_3_W_0) },
7810   },
7811   {
7812     /* VEX_W_0F385E_X86_64_P_0 */
7813     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_0_W_0) },
7814   },
7815   {
7816     /* VEX_W_0F385E_X86_64_P_1 */
7817     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_1_W_0) },
7818   },
7819   {
7820     /* VEX_W_0F385E_X86_64_P_2 */
7821     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_2_W_0) },
7822   },
7823   {
7824     /* VEX_W_0F385E_X86_64_P_3 */
7825     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_3_W_0) },
7826   },
7827   {
7828     /* VEX_W_0F3872_P_1 */
7829     { "%XVvcvtneps2bf16%XY", { XMM, EXx }, 0 },
7830   },
7831   {
7832     /* VEX_W_0F3878 */
7833     { "%XEvpbroadcastb",        { XM, EXb }, PREFIX_DATA },
7834   },
7835   {
7836     /* VEX_W_0F3879 */
7837     { "%XEvpbroadcastw",        { XM, EXw }, PREFIX_DATA },
7838   },
7839   {
7840     /* VEX_W_0F38B0 */
7841     { PREFIX_TABLE (PREFIX_VEX_0F38B0_W_0) },
7842   },
7843   {
7844     /* VEX_W_0F38B1 */
7845     { PREFIX_TABLE (PREFIX_VEX_0F38B1_W_0) },
7846   },
7847   {
7848     /* VEX_W_0F38B4 */
7849     { Bad_Opcode },
7850     { "%XVvpmadd52luq", { XM, Vex, EXx }, PREFIX_DATA },
7851   },
7852   {
7853     /* VEX_W_0F38B5 */
7854     { Bad_Opcode },
7855     { "%XVvpmadd52huq", { XM, Vex, EXx }, PREFIX_DATA },
7856   },
7857   {
7858     /* VEX_W_0F38CF */
7859     { "%XEvgf2p8mulb", { XM, Vex, EXx }, PREFIX_DATA },
7860   },
7861   {
7862     /* VEX_W_0F3A00_L_1 */
7863     { Bad_Opcode },
7864     { "%XEvpermq",              { XM, EXx, Ib }, PREFIX_DATA },
7865   },
7866   {
7867     /* VEX_W_0F3A01_L_1 */
7868     { Bad_Opcode },
7869     { "%XEvpermpd",     { XM, EXx, Ib }, PREFIX_DATA },
7870   },
7871   {
7872     /* VEX_W_0F3A02 */
7873     { "vpblendd",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
7874   },
7875   {
7876     /* VEX_W_0F3A04 */
7877     { "%XEvpermilps",   { XM, EXx, Ib }, PREFIX_DATA },
7878   },
7879   {
7880     /* VEX_W_0F3A05 */
7881     { "vpermilpd",      { XM, EXx, Ib }, PREFIX_DATA },
7882   },
7883   {
7884     /* VEX_W_0F3A06_L_1 */
7885     { "vperm2f128",     { XM, Vex, EXx, Ib }, PREFIX_DATA },
7886   },
7887   {
7888     /* VEX_W_0F3A18_L_1 */
7889     { "vinsertf128",    { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7890   },
7891   {
7892     /* VEX_W_0F3A19_L_1 */
7893     { "vextractf128",   { EXxmm, XM, Ib }, PREFIX_DATA },
7894   },
7895   {
7896     /* VEX_W_0F3A1D */
7897     { "%XEvcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, PREFIX_DATA },
7898   },
7899   {
7900     /* VEX_W_0F3A38_L_1 */
7901     { "vinserti128",    { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7902   },
7903   {
7904     /* VEX_W_0F3A39_L_1 */
7905     { "vextracti128",   { EXxmm, XM, Ib }, PREFIX_DATA },
7906   },
7907   {
7908     /* VEX_W_0F3A46_L_1 */
7909     { "vperm2i128",     { XM, Vex, EXx, Ib }, PREFIX_DATA },
7910   },
7911   {
7912     /* VEX_W_0F3A4A */
7913     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7914   },
7915   {
7916     /* VEX_W_0F3A4B */
7917     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7918   },
7919   {
7920     /* VEX_W_0F3A4C */
7921     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7922   },
7923   {
7924     /* VEX_W_0F3ACE */
7925     { Bad_Opcode },
7926     { "%XEvgf2p8affineqb", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7927   },
7928   {
7929     /* VEX_W_0F3ACF */
7930     { Bad_Opcode },
7931     { "%XEvgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, PREFIX_DATA },
7932   },
7933   /* VEX_W_0FXOP_08_85_L_0 */
7934   {
7935     { "vpmacssww",      { XM, Vex, EXx, XMVexI4 }, 0 },
7936   },
7937   /* VEX_W_0FXOP_08_86_L_0 */
7938   {
7939     { "vpmacsswd",      { XM, Vex, EXx, XMVexI4 }, 0 },
7940   },
7941   /* VEX_W_0FXOP_08_87_L_0 */
7942   {
7943     { "vpmacssdql",     { XM, Vex, EXx, XMVexI4 }, 0 },
7944   },
7945   /* VEX_W_0FXOP_08_8E_L_0 */
7946   {
7947     { "vpmacssdd",      { XM, Vex, EXx, XMVexI4 }, 0 },
7948   },
7949   /* VEX_W_0FXOP_08_8F_L_0 */
7950   {
7951     { "vpmacssdqh",     { XM, Vex, EXx, XMVexI4 }, 0 },
7952   },
7953   /* VEX_W_0FXOP_08_95_L_0 */
7954   {
7955     { "vpmacsww",       { XM, Vex, EXx, XMVexI4 }, 0 },
7956   },
7957   /* VEX_W_0FXOP_08_96_L_0 */
7958   {
7959     { "vpmacswd",       { XM, Vex, EXx, XMVexI4 }, 0 },
7960   },
7961   /* VEX_W_0FXOP_08_97_L_0 */
7962   {
7963     { "vpmacsdql",      { XM, Vex, EXx, XMVexI4 }, 0 },
7964   },
7965   /* VEX_W_0FXOP_08_9E_L_0 */
7966   {
7967     { "vpmacsdd",       { XM, Vex, EXx, XMVexI4 }, 0 },
7968   },
7969   /* VEX_W_0FXOP_08_9F_L_0 */
7970   {
7971     { "vpmacsdqh",      { XM, Vex, EXx, XMVexI4 }, 0 },
7972   },
7973   /* VEX_W_0FXOP_08_A6_L_0 */
7974   {
7975     { "vpmadcsswd",     { XM, Vex, EXx, XMVexI4 }, 0 },
7976   },
7977   /* VEX_W_0FXOP_08_B6_L_0 */
7978   {
7979     { "vpmadcswd",      { XM, Vex, EXx, XMVexI4 }, 0 },
7980   },
7981   /* VEX_W_0FXOP_08_C0_L_0 */
7982   {
7983     { "vprotb",         { XM, EXx, Ib }, 0 },
7984   },
7985   /* VEX_W_0FXOP_08_C1_L_0 */
7986   {
7987     { "vprotw",         { XM, EXx, Ib }, 0 },
7988   },
7989   /* VEX_W_0FXOP_08_C2_L_0 */
7990   {
7991     { "vprotd",         { XM, EXx, Ib }, 0 },
7992   },
7993   /* VEX_W_0FXOP_08_C3_L_0 */
7994   {
7995     { "vprotq",         { XM, EXx, Ib }, 0 },
7996   },
7997   /* VEX_W_0FXOP_08_CC_L_0 */
7998   {
7999      { "vpcomb",        { XM, Vex, EXx, VPCOM }, 0 },
8000   },
8001   /* VEX_W_0FXOP_08_CD_L_0 */
8002   {
8003      { "vpcomw",        { XM, Vex, EXx, VPCOM }, 0 },
8004   },
8005   /* VEX_W_0FXOP_08_CE_L_0 */
8006   {
8007      { "vpcomd",        { XM, Vex, EXx, VPCOM }, 0 },
8008   },
8009   /* VEX_W_0FXOP_08_CF_L_0 */
8010   {
8011      { "vpcomq",        { XM, Vex, EXx, VPCOM }, 0 },
8012   },
8013   /* VEX_W_0FXOP_08_EC_L_0 */
8014   {
8015      { "vpcomub",       { XM, Vex, EXx, VPCOM }, 0 },
8016   },
8017   /* VEX_W_0FXOP_08_ED_L_0 */
8018   {
8019      { "vpcomuw",       { XM, Vex, EXx, VPCOM }, 0 },
8020   },
8021   /* VEX_W_0FXOP_08_EE_L_0 */
8022   {
8023      { "vpcomud",       { XM, Vex, EXx, VPCOM }, 0 },
8024   },
8025   /* VEX_W_0FXOP_08_EF_L_0 */
8026   {
8027      { "vpcomuq",       { XM, Vex, EXx, VPCOM }, 0 },
8028   },
8029   /* VEX_W_0FXOP_09_80 */
8030   {
8031     { "vfrczps",        { XM, EXx }, 0 },
8032   },
8033   /* VEX_W_0FXOP_09_81 */
8034   {
8035     { "vfrczpd",        { XM, EXx }, 0 },
8036   },
8037   /* VEX_W_0FXOP_09_82 */
8038   {
8039     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_82_W_0) },
8040   },
8041   /* VEX_W_0FXOP_09_83 */
8042   {
8043     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_83_W_0) },
8044   },
8045   /* VEX_W_0FXOP_09_C1_L_0 */
8046   {
8047     { "vphaddbw",       { XM, EXxmm }, 0 },
8048   },
8049   /* VEX_W_0FXOP_09_C2_L_0 */
8050   {
8051     { "vphaddbd",       { XM, EXxmm }, 0 },
8052   },
8053   /* VEX_W_0FXOP_09_C3_L_0 */
8054   {
8055     { "vphaddbq",       { XM, EXxmm }, 0 },
8056   },
8057   /* VEX_W_0FXOP_09_C6_L_0 */
8058   {
8059     { "vphaddwd",       { XM, EXxmm }, 0 },
8060   },
8061   /* VEX_W_0FXOP_09_C7_L_0 */
8062   {
8063     { "vphaddwq",       { XM, EXxmm }, 0 },
8064   },
8065   /* VEX_W_0FXOP_09_CB_L_0 */
8066   {
8067     { "vphadddq",       { XM, EXxmm }, 0 },
8068   },
8069   /* VEX_W_0FXOP_09_D1_L_0 */
8070   {
8071     { "vphaddubw",      { XM, EXxmm }, 0 },
8072   },
8073   /* VEX_W_0FXOP_09_D2_L_0 */
8074   {
8075     { "vphaddubd",      { XM, EXxmm }, 0 },
8076   },
8077   /* VEX_W_0FXOP_09_D3_L_0 */
8078   {
8079     { "vphaddubq",      { XM, EXxmm }, 0 },
8080   },
8081   /* VEX_W_0FXOP_09_D6_L_0 */
8082   {
8083     { "vphadduwd",      { XM, EXxmm }, 0 },
8084   },
8085   /* VEX_W_0FXOP_09_D7_L_0 */
8086   {
8087     { "vphadduwq",      { XM, EXxmm }, 0 },
8088   },
8089   /* VEX_W_0FXOP_09_DB_L_0 */
8090   {
8091     { "vphaddudq",      { XM, EXxmm }, 0 },
8092   },
8093   /* VEX_W_0FXOP_09_E1_L_0 */
8094   {
8095     { "vphsubbw",       { XM, EXxmm }, 0 },
8096   },
8097   /* VEX_W_0FXOP_09_E2_L_0 */
8098   {
8099     { "vphsubwd",       { XM, EXxmm }, 0 },
8100   },
8101   /* VEX_W_0FXOP_09_E3_L_0 */
8102   {
8103     { "vphsubdq",       { XM, EXxmm }, 0 },
8104   },
8105
8106 #include "i386-dis-evex-w.h"
8107 };
8108
8109 static const struct dis386 mod_table[][2] = {
8110   {
8111     /* MOD_62_32BIT */
8112     { "bound{S|}",      { Gv, Ma }, 0 },
8113     { EVEX_TABLE (EVEX_0F) },
8114   },
8115   {
8116     /* MOD_8D */
8117     { "leaS",           { Gv, M }, 0 },
8118   },
8119   {
8120     /* MOD_C4_32BIT */
8121     { "lesS",           { Gv, Mp }, 0 },
8122     { VEX_C4_TABLE (VEX_0F) },
8123   },
8124   {
8125     /* MOD_C5_32BIT */
8126     { "ldsS",           { Gv, Mp }, 0 },
8127     { VEX_C5_TABLE (VEX_0F) },
8128   },
8129   {
8130     /* MOD_C6_REG_7 */
8131     { Bad_Opcode },
8132     { RM_TABLE (RM_C6_REG_7) },
8133   },
8134   {
8135     /* MOD_C7_REG_7 */
8136     { Bad_Opcode },
8137     { RM_TABLE (RM_C7_REG_7) },
8138   },
8139   {
8140     /* MOD_FF_REG_3 */
8141     { "{l|}call^", { indirEp }, 0 },
8142   },
8143   {
8144     /* MOD_FF_REG_5 */
8145     { "{l|}jmp^", { indirEp }, 0 },
8146   },
8147   {
8148     /* MOD_0F01_REG_0 */
8149     { X86_64_TABLE (X86_64_0F01_REG_0) },
8150     { RM_TABLE (RM_0F01_REG_0) },
8151   },
8152   {
8153     /* MOD_0F01_REG_1 */
8154     { X86_64_TABLE (X86_64_0F01_REG_1) },
8155     { RM_TABLE (RM_0F01_REG_1) },
8156   },
8157   {
8158     /* MOD_0F01_REG_2 */
8159     { X86_64_TABLE (X86_64_0F01_REG_2) },
8160     { RM_TABLE (RM_0F01_REG_2) },
8161   },
8162   {
8163     /* MOD_0F01_REG_3 */
8164     { X86_64_TABLE (X86_64_0F01_REG_3) },
8165     { RM_TABLE (RM_0F01_REG_3) },
8166   },
8167   {
8168     /* MOD_0F01_REG_5 */
8169     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) },
8170     { RM_TABLE (RM_0F01_REG_5_MOD_3) },
8171   },
8172   {
8173     /* MOD_0F01_REG_7 */
8174     { "invlpg",         { Mb }, 0 },
8175     { RM_TABLE (RM_0F01_REG_7_MOD_3) },
8176   },
8177   {
8178     /* MOD_0F12_PREFIX_0 */
8179     { "movlpX",         { XM, EXq }, 0 },
8180     { "movhlps",        { XM, EXq }, 0 },
8181   },
8182   {
8183     /* MOD_0F12_PREFIX_2 */
8184     { "movlpX", { XM, EXq }, 0 },
8185   },
8186   {
8187     /* MOD_0F13 */
8188     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
8189   },
8190   {
8191     /* MOD_0F16_PREFIX_0 */
8192     { "movhpX",         { XM, EXq }, 0 },
8193     { "movlhps",        { XM, EXq }, 0 },
8194   },
8195   {
8196     /* MOD_0F16_PREFIX_2 */
8197     { "movhpX", { XM, EXq }, 0 },
8198   },
8199   {
8200     /* MOD_0F17 */
8201     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
8202   },
8203   {
8204     /* MOD_0F18_REG_0 */
8205     { "prefetchnta",    { Mb }, 0 },
8206     { "nopQ",           { Ev }, 0 },
8207   },
8208   {
8209     /* MOD_0F18_REG_1 */
8210     { "prefetcht0",     { Mb }, 0 },
8211     { "nopQ",           { Ev }, 0 },
8212   },
8213   {
8214     /* MOD_0F18_REG_2 */
8215     { "prefetcht1",     { Mb }, 0 },
8216     { "nopQ",           { Ev }, 0 },
8217   },
8218   {
8219     /* MOD_0F18_REG_3 */
8220     { "prefetcht2",     { Mb }, 0 },
8221     { "nopQ",           { Ev }, 0 },
8222   },
8223   {
8224     /* MOD_0F18_REG_6 */
8225     { X86_64_TABLE (X86_64_0F18_REG_6_MOD_0) },
8226     { "nopQ",           { Ev }, 0 },
8227   },
8228   {
8229     /* MOD_0F18_REG_7 */
8230     { X86_64_TABLE (X86_64_0F18_REG_7_MOD_0) },
8231     { "nopQ",           { Ev }, 0 },
8232   },
8233   {
8234     /* MOD_0F1A_PREFIX_0 */
8235     { "bndldx",         { Gbnd, Mv_bnd }, 0 },
8236     { "nopQ",           { Ev }, 0 },
8237   },
8238   {
8239     /* MOD_0F1B_PREFIX_0 */
8240     { "bndstx",         { Mv_bnd, Gbnd }, 0 },
8241     { "nopQ",           { Ev }, 0 },
8242   },
8243   {
8244     /* MOD_0F1B_PREFIX_1 */
8245     { "bndmk",          { Gbnd, Mv_bnd }, 0 },
8246     { "nopQ",           { Ev }, PREFIX_IGNORED },
8247   },
8248   {
8249     /* MOD_0F1C_PREFIX_0 */
8250     { REG_TABLE (REG_0F1C_P_0_MOD_0) },
8251     { "nopQ",           { Ev }, 0 },
8252   },
8253   {
8254     /* MOD_0F1E_PREFIX_1 */
8255     { "nopQ",           { Ev }, PREFIX_IGNORED },
8256     { REG_TABLE (REG_0F1E_P_1_MOD_3) },
8257   },
8258   {
8259     /* MOD_0F2B_PREFIX_0 */
8260     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
8261   },
8262   {
8263     /* MOD_0F2B_PREFIX_1 */
8264     {"movntss",         { Md, XM }, PREFIX_OPCODE },
8265   },
8266   {
8267     /* MOD_0F2B_PREFIX_2 */
8268     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
8269   },
8270   {
8271     /* MOD_0F2B_PREFIX_3 */
8272     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
8273   },
8274   {
8275     /* MOD_0F50 */
8276     { Bad_Opcode },
8277     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
8278   },
8279   {
8280     /* MOD_0F71 */
8281     { Bad_Opcode },
8282     { REG_TABLE (REG_0F71_MOD_0) },
8283   },
8284   {
8285     /* MOD_0F72 */
8286     { Bad_Opcode },
8287     { REG_TABLE (REG_0F72_MOD_0) },
8288   },
8289   {
8290     /* MOD_0F73 */
8291     { Bad_Opcode },
8292     { REG_TABLE (REG_0F73_MOD_0) },
8293   },
8294   {
8295     /* MOD_0FAE_REG_0 */
8296     { "fxsave",         { FXSAVE }, 0 },
8297     { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) },
8298   },
8299   {
8300     /* MOD_0FAE_REG_1 */
8301     { "fxrstor",        { FXSAVE }, 0 },
8302     { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) },
8303   },
8304   {
8305     /* MOD_0FAE_REG_2 */
8306     { "ldmxcsr",        { Md }, 0 },
8307     { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) },
8308   },
8309   {
8310     /* MOD_0FAE_REG_3 */
8311     { "stmxcsr",        { Md }, 0 },
8312     { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) },
8313   },
8314   {
8315     /* MOD_0FAE_REG_4 */
8316     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) },
8317     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) },
8318   },
8319   {
8320     /* MOD_0FAE_REG_5 */
8321     { "xrstor",         { FXSAVE }, PREFIX_OPCODE },
8322     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) },
8323   },
8324   {
8325     /* MOD_0FAE_REG_6 */
8326     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) },
8327     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) },
8328   },
8329   {
8330     /* MOD_0FAE_REG_7 */
8331     { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) },
8332     { RM_TABLE (RM_0FAE_REG_7_MOD_3) },
8333   },
8334   {
8335     /* MOD_0FB2 */
8336     { "lssS",           { Gv, Mp }, 0 },
8337   },
8338   {
8339     /* MOD_0FB4 */
8340     { "lfsS",           { Gv, Mp }, 0 },
8341   },
8342   {
8343     /* MOD_0FB5 */
8344     { "lgsS",           { Gv, Mp }, 0 },
8345   },
8346   {
8347     /* MOD_0FC3 */
8348     { "movntiS", { Edq, Gdq }, PREFIX_OPCODE },
8349   },
8350   {
8351     /* MOD_0FC7_REG_3 */
8352     { "xrstors",        { FXSAVE }, 0 },
8353   },
8354   {
8355     /* MOD_0FC7_REG_4 */
8356     { "xsavec",         { FXSAVE }, 0 },
8357   },
8358   {
8359     /* MOD_0FC7_REG_5 */
8360     { "xsaves",         { FXSAVE }, 0 },
8361   },
8362   {
8363     /* MOD_0FC7_REG_6 */
8364     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) },
8365     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) }
8366   },
8367   {
8368     /* MOD_0FC7_REG_7 */
8369     { "vmptrst",        { Mq }, 0 },
8370     { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) }
8371   },
8372   {
8373     /* MOD_0FD7 */
8374     { Bad_Opcode },
8375     { "pmovmskb",       { Gdq, MS }, 0 },
8376   },
8377   {
8378     /* MOD_0FE7_PREFIX_2 */
8379     { "movntdq",        { Mx, XM }, 0 },
8380   },
8381   {
8382     /* MOD_0FF0_PREFIX_3 */
8383     { "lddqu",          { XM, M }, 0 },
8384   },
8385   {
8386     /* MOD_0F382A */
8387     { "movntdqa",       { XM, Mx }, PREFIX_DATA },
8388   },
8389   {
8390     /* MOD_0F38DC_PREFIX_1 */
8391     { "aesenc128kl",    { XM, M }, 0 },
8392     { "loadiwkey",      { XM, EXx }, 0 },
8393   },
8394   {
8395     /* MOD_0F38DD_PREFIX_1 */
8396     { "aesdec128kl",    { XM, M }, 0 },
8397   },
8398   {
8399     /* MOD_0F38DE_PREFIX_1 */
8400     { "aesenc256kl",    { XM, M }, 0 },
8401   },
8402   {
8403     /* MOD_0F38DF_PREFIX_1 */
8404     { "aesdec256kl",    { XM, M }, 0 },
8405   },
8406   {
8407     /* MOD_0F38F5 */
8408     { "wrussK",         { M, Gdq }, PREFIX_DATA },
8409   },
8410   {
8411     /* MOD_0F38F6_PREFIX_0 */
8412     { "wrssK",          { M, Gdq }, PREFIX_OPCODE },
8413   },
8414   {
8415     /* MOD_0F38F8_PREFIX_1 */
8416     { "enqcmds",        { Gva, M }, PREFIX_OPCODE },
8417   },
8418   {
8419     /* MOD_0F38F8_PREFIX_2 */
8420     { "movdir64b",      { Gva, M }, PREFIX_OPCODE },
8421   },
8422   {
8423     /* MOD_0F38F8_PREFIX_3 */
8424     { "enqcmd",         { Gva, M }, PREFIX_OPCODE },
8425   },
8426   {
8427     /* MOD_0F38F9 */
8428     { "movdiri",        { Edq, Gdq }, PREFIX_OPCODE },
8429   },
8430   {
8431     /* MOD_0F38FA_PREFIX_1 */
8432     { Bad_Opcode },
8433     { "encodekey128", { Gd, Ed }, 0 },
8434   },
8435   {
8436     /* MOD_0F38FB_PREFIX_1 */
8437     { Bad_Opcode },
8438     { "encodekey256", { Gd, Ed }, 0 },
8439   },
8440   {
8441     /* MOD_0F3A0F_PREFIX_1 */
8442     { Bad_Opcode },
8443     { REG_TABLE (REG_0F3A0F_PREFIX_1_MOD_3) },
8444   },
8445   {
8446     /* MOD_VEX_0F12_PREFIX_0 */
8447     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
8448     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
8449   },
8450   {
8451     /* MOD_VEX_0F12_PREFIX_2 */
8452     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0) },
8453   },
8454   {
8455     /* MOD_VEX_0F13 */
8456     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
8457   },
8458   {
8459     /* MOD_VEX_0F16_PREFIX_0 */
8460     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
8461     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
8462   },
8463   {
8464     /* MOD_VEX_0F16_PREFIX_2 */
8465     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0) },
8466   },
8467   {
8468     /* MOD_VEX_0F17 */
8469     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
8470   },
8471   {
8472     /* MOD_VEX_0F2B */
8473     { "%XEvmovntpX",    { Mx, XM }, PREFIX_OPCODE },
8474   },
8475   {
8476     /* MOD_VEX_0F41_L_1 */
8477     { Bad_Opcode },
8478     { VEX_W_TABLE (VEX_W_0F41_L_1_M_1) },
8479   },
8480   {
8481     /* MOD_VEX_0F42_L_1 */
8482     { Bad_Opcode },
8483     { VEX_W_TABLE (VEX_W_0F42_L_1_M_1) },
8484   },
8485   {
8486     /* MOD_VEX_0F44_L_0 */
8487     { Bad_Opcode },
8488     { VEX_W_TABLE (VEX_W_0F44_L_0_M_1) },
8489   },
8490   {
8491     /* MOD_VEX_0F45_L_1 */
8492     { Bad_Opcode },
8493     { VEX_W_TABLE (VEX_W_0F45_L_1_M_1) },
8494   },
8495   {
8496     /* MOD_VEX_0F46_L_1 */
8497     { Bad_Opcode },
8498     { VEX_W_TABLE (VEX_W_0F46_L_1_M_1) },
8499   },
8500   {
8501     /* MOD_VEX_0F47_L_1 */
8502     { Bad_Opcode },
8503     { VEX_W_TABLE (VEX_W_0F47_L_1_M_1) },
8504   },
8505   {
8506     /* MOD_VEX_0F4A_L_1 */
8507     { Bad_Opcode },
8508     { VEX_W_TABLE (VEX_W_0F4A_L_1_M_1) },
8509   },
8510   {
8511     /* MOD_VEX_0F4B_L_1 */
8512     { Bad_Opcode },
8513     { VEX_W_TABLE (VEX_W_0F4B_L_1_M_1) },
8514   },
8515   {
8516     /* MOD_VEX_0F50 */
8517     { Bad_Opcode },
8518     { "vmovmskpX",      { Gdq, XS }, PREFIX_OPCODE },
8519   },
8520   {
8521     /* MOD_VEX_0F71 */
8522     { Bad_Opcode },
8523     { REG_TABLE (REG_VEX_0F71_M_0) },
8524   },
8525   {
8526     /* MOD_VEX_0F72 */
8527     { Bad_Opcode },
8528     { REG_TABLE (REG_VEX_0F72_M_0) },
8529   },
8530   {
8531     /* MOD_VEX_0F73 */
8532     { Bad_Opcode },
8533     { REG_TABLE (REG_VEX_0F73_M_0) },
8534   },
8535   {
8536     /* MOD_VEX_0F91_L_0 */
8537     { VEX_W_TABLE (VEX_W_0F91_L_0_M_0) },
8538   },
8539   {
8540     /* MOD_VEX_0F92_L_0 */
8541     { Bad_Opcode },
8542     { VEX_W_TABLE (VEX_W_0F92_L_0_M_1) },
8543   },
8544   {
8545     /* MOD_VEX_0F93_L_0 */
8546     { Bad_Opcode },
8547     { VEX_W_TABLE (VEX_W_0F93_L_0_M_1) },
8548   },
8549   {
8550     /* MOD_VEX_0F98_L_0 */
8551     { Bad_Opcode },
8552     { VEX_W_TABLE (VEX_W_0F98_L_0_M_1) },
8553   },
8554   {
8555     /* MOD_VEX_0F99_L_0 */
8556     { Bad_Opcode },
8557     { VEX_W_TABLE (VEX_W_0F99_L_0_M_1) },
8558   },
8559   {
8560     /* MOD_VEX_0FAE_REG_2 */
8561     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
8562   },
8563   {
8564     /* MOD_VEX_0FAE_REG_3 */
8565     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
8566   },
8567   {
8568     /* MOD_VEX_0FD7 */
8569     { Bad_Opcode },
8570     { "vpmovmskb",      { Gdq, XS }, PREFIX_DATA },
8571   },
8572   {
8573     /* MOD_VEX_0FE7 */
8574     { "vmovntdq",       { Mx, XM }, PREFIX_DATA },
8575   },
8576   {
8577     /* MOD_VEX_0FF0_PREFIX_3 */
8578     { "vlddqu",         { XM, M }, 0 },
8579   },
8580   {
8581     /* MOD_VEX_0F381A */
8582     { VEX_LEN_TABLE (VEX_LEN_0F381A_M_0) },
8583   },
8584   {
8585     /* MOD_VEX_0F382A */
8586     { "vmovntdqa",      { XM, Mx }, PREFIX_DATA },
8587   },
8588   {
8589     /* MOD_VEX_0F382C */
8590     { VEX_W_TABLE (VEX_W_0F382C_M_0) },
8591   },
8592   {
8593     /* MOD_VEX_0F382D */
8594     { VEX_W_TABLE (VEX_W_0F382D_M_0) },
8595   },
8596   {
8597     /* MOD_VEX_0F382E */
8598     { VEX_W_TABLE (VEX_W_0F382E_M_0) },
8599   },
8600   {
8601     /* MOD_VEX_0F382F */
8602     { VEX_W_TABLE (VEX_W_0F382F_M_0) },
8603   },
8604   {
8605     /* MOD_VEX_0F3849_X86_64_P_0_W_0 */
8606     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0) },
8607     { REG_TABLE (REG_VEX_0F3849_X86_64_P_0_W_0_M_1) },
8608   },
8609   {
8610     /* MOD_VEX_0F3849_X86_64_P_2_W_0 */
8611     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0) },
8612   },
8613   {
8614     /* MOD_VEX_0F3849_X86_64_P_3_W_0 */
8615     { Bad_Opcode },
8616     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0) },
8617   },
8618   {
8619     /* MOD_VEX_0F384B_X86_64_P_1_W_0 */
8620     { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0) },
8621   },
8622   {
8623     /* MOD_VEX_0F384B_X86_64_P_2_W_0 */
8624     { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0) },
8625   },
8626   {
8627     /* MOD_VEX_0F384B_X86_64_P_3_W_0 */
8628     { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0) },
8629   },
8630   {
8631     /* MOD_VEX_0F385A */
8632     { VEX_LEN_TABLE (VEX_LEN_0F385A_M_0) },
8633   },
8634   {
8635     /* MOD_VEX_0F385C_X86_64_P_1_W_0 */
8636     { Bad_Opcode },
8637     { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0) },
8638   },
8639   {
8640     /* MOD_VEX_0F385C_X86_64_P_3_W_0 */
8641     { Bad_Opcode },
8642     { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64_P_3_W_0_M_0) },
8643   },
8644   {
8645     /* MOD_VEX_0F385E_X86_64_P_0_W_0 */
8646     { Bad_Opcode },
8647     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0) },
8648   },
8649   {
8650     /* MOD_VEX_0F385E_X86_64_P_1_W_0 */
8651     { Bad_Opcode },
8652     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0) },
8653   },
8654   {
8655     /* MOD_VEX_0F385E_X86_64_P_2_W_0 */
8656     { Bad_Opcode },
8657     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0) },
8658   },
8659   {
8660     /* MOD_VEX_0F385E_X86_64_P_3_W_0 */
8661     { Bad_Opcode },
8662     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0) },
8663   },
8664   {
8665     /* MOD_VEX_0F388C */
8666     { "vpmaskmov%DQ",   { XM, Vex, Mx }, PREFIX_DATA },
8667   },
8668   {
8669     /* MOD_VEX_0F388E */
8670     { "vpmaskmov%DQ",   { Mx, Vex, XM }, PREFIX_DATA },
8671   },
8672   {
8673     /* MOD_VEX_0F3A30_L_0 */
8674     { Bad_Opcode },
8675     { "kshiftr%BW",     { MaskG, MaskE, Ib }, PREFIX_DATA },
8676   },
8677   {
8678     /* MOD_VEX_0F3A31_L_0 */
8679     { Bad_Opcode },
8680     { "kshiftr%DQ",     { MaskG, MaskE, Ib }, PREFIX_DATA },
8681   },
8682   {
8683     /* MOD_VEX_0F3A32_L_0 */
8684     { Bad_Opcode },
8685     { "kshiftl%BW",     { MaskG, MaskE, Ib }, PREFIX_DATA },
8686   },
8687   {
8688     /* MOD_VEX_0F3A33_L_0 */
8689     { Bad_Opcode },
8690     { "kshiftl%DQ",     { MaskG, MaskE, Ib }, PREFIX_DATA },
8691   },
8692   {
8693     /* MOD_XOP_09_12 */
8694     { Bad_Opcode },
8695     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_12_M_1) },
8696   },
8697
8698 #include "i386-dis-evex-mod.h"
8699 };
8700
8701 static const struct dis386 rm_table[][8] = {
8702   {
8703     /* RM_C6_REG_7 */
8704     { "xabort",         { Skip_MODRM, Ib }, 0 },
8705   },
8706   {
8707     /* RM_C7_REG_7 */
8708     { "xbeginT",        { Skip_MODRM, Jdqw }, 0 },
8709   },
8710   {
8711     /* RM_0F01_REG_0 */
8712     { "enclv",          { Skip_MODRM }, 0 },
8713     { "vmcall",         { Skip_MODRM }, 0 },
8714     { "vmlaunch",       { Skip_MODRM }, 0 },
8715     { "vmresume",       { Skip_MODRM }, 0 },
8716     { "vmxoff",         { Skip_MODRM }, 0 },
8717     { "pconfig",        { Skip_MODRM }, 0 },
8718     { PREFIX_TABLE (PREFIX_0F01_REG_0_MOD_3_RM_6) },
8719   },
8720   {
8721     /* RM_0F01_REG_1 */
8722     { "monitor",        { { OP_Monitor, 0 } }, 0 },
8723     { "mwait",          { { OP_Mwait, 0 } }, 0 },
8724     { "clac",           { Skip_MODRM }, 0 },
8725     { "stac",           { Skip_MODRM }, 0 },
8726     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_4) },
8727     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_5) },
8728     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_6) },
8729     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_7) },
8730   },
8731   {
8732     /* RM_0F01_REG_2 */
8733     { "xgetbv",         { Skip_MODRM }, 0 },
8734     { "xsetbv",         { Skip_MODRM }, 0 },
8735     { Bad_Opcode },
8736     { Bad_Opcode },
8737     { "vmfunc",         { Skip_MODRM }, 0 },
8738     { "xend",           { Skip_MODRM }, 0 },
8739     { "xtest",          { Skip_MODRM }, 0 },
8740     { "enclu",          { Skip_MODRM }, 0 },
8741   },
8742   {
8743     /* RM_0F01_REG_3 */
8744     { "vmrun",          { Skip_MODRM }, 0 },
8745     { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) },
8746     { "vmload",         { Skip_MODRM }, 0 },
8747     { "vmsave",         { Skip_MODRM }, 0 },
8748     { "stgi",           { Skip_MODRM }, 0 },
8749     { "clgi",           { Skip_MODRM }, 0 },
8750     { "skinit",         { Skip_MODRM }, 0 },
8751     { "invlpga",        { Skip_MODRM }, 0 },
8752   },
8753   {
8754     /* RM_0F01_REG_5_MOD_3 */
8755     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) },
8756     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) },
8757     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) },
8758     { Bad_Opcode },
8759     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_4) },
8760     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_5) },
8761     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_6) },
8762     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_7) },
8763   },
8764   {
8765     /* RM_0F01_REG_7_MOD_3 */
8766     { "swapgs",         { Skip_MODRM }, 0  },
8767     { "rdtscp",         { Skip_MODRM }, 0  },
8768     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) },
8769     { "mwaitx",         { { OP_Mwait, eBX_reg } }, PREFIX_OPCODE },
8770     { "clzero",         { Skip_MODRM }, 0  },
8771     { "rdpru",          { Skip_MODRM }, 0  },
8772     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_6) },
8773     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_7) },
8774   },
8775   {
8776     /* RM_0F1E_P_1_MOD_3_REG_7 */
8777     { "nopQ",           { Ev }, PREFIX_IGNORED },
8778     { "nopQ",           { Ev }, PREFIX_IGNORED },
8779     { "endbr64",        { Skip_MODRM }, 0 },
8780     { "endbr32",        { Skip_MODRM }, 0 },
8781     { "nopQ",           { Ev }, PREFIX_IGNORED },
8782     { "nopQ",           { Ev }, PREFIX_IGNORED },
8783     { "nopQ",           { Ev }, PREFIX_IGNORED },
8784     { "nopQ",           { Ev }, PREFIX_IGNORED },
8785   },
8786   {
8787     /* RM_0FAE_REG_6_MOD_3 */
8788     { "mfence",         { Skip_MODRM }, 0 },
8789   },
8790   {
8791     /* RM_0FAE_REG_7_MOD_3 */
8792     { "sfence",         { Skip_MODRM }, 0 },
8793   },
8794   {
8795     /* RM_0F3A0F_P_1_MOD_3_REG_0 */
8796     { "hreset",         { Skip_MODRM, Ib }, 0 },
8797   },
8798   {
8799     /* RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0 */
8800     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0) },
8801   },
8802 };
8803
8804 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
8805
8806 /* The values used here must be non-zero, fit in 'unsigned char', and not be
8807    in conflict with actual prefix opcodes.  */
8808 #define REP_PREFIX      0x01
8809 #define XACQUIRE_PREFIX 0x02
8810 #define XRELEASE_PREFIX 0x03
8811 #define BND_PREFIX      0x04
8812 #define NOTRACK_PREFIX  0x05
8813
8814 static int
8815 ckprefix (instr_info *ins)
8816 {
8817   int newrex, i, length;
8818
8819   i = 0;
8820   length = 0;
8821   /* The maximum instruction length is 15bytes.  */
8822   while (length < MAX_CODE_LENGTH - 1)
8823     {
8824       FETCH_DATA (ins->info, ins->codep + 1);
8825       newrex = 0;
8826       switch (*ins->codep)
8827         {
8828         /* REX prefixes family.  */
8829         case 0x40:
8830         case 0x41:
8831         case 0x42:
8832         case 0x43:
8833         case 0x44:
8834         case 0x45:
8835         case 0x46:
8836         case 0x47:
8837         case 0x48:
8838         case 0x49:
8839         case 0x4a:
8840         case 0x4b:
8841         case 0x4c:
8842         case 0x4d:
8843         case 0x4e:
8844         case 0x4f:
8845           if (ins->address_mode == mode_64bit)
8846             newrex = *ins->codep;
8847           else
8848             return 1;
8849           ins->last_rex_prefix = i;
8850           break;
8851         case 0xf3:
8852           ins->prefixes |= PREFIX_REPZ;
8853           ins->last_repz_prefix = i;
8854           break;
8855         case 0xf2:
8856           ins->prefixes |= PREFIX_REPNZ;
8857           ins->last_repnz_prefix = i;
8858           break;
8859         case 0xf0:
8860           ins->prefixes |= PREFIX_LOCK;
8861           ins->last_lock_prefix = i;
8862           break;
8863         case 0x2e:
8864           ins->prefixes |= PREFIX_CS;
8865           ins->last_seg_prefix = i;
8866           if (ins->address_mode != mode_64bit)
8867             ins->active_seg_prefix = PREFIX_CS;
8868           break;
8869         case 0x36:
8870           ins->prefixes |= PREFIX_SS;
8871           ins->last_seg_prefix = i;
8872           if (ins->address_mode != mode_64bit)
8873             ins->active_seg_prefix = PREFIX_SS;
8874           break;
8875         case 0x3e:
8876           ins->prefixes |= PREFIX_DS;
8877           ins->last_seg_prefix = i;
8878           if (ins->address_mode != mode_64bit)
8879             ins->active_seg_prefix = PREFIX_DS;
8880           break;
8881         case 0x26:
8882           ins->prefixes |= PREFIX_ES;
8883           ins->last_seg_prefix = i;
8884           if (ins->address_mode != mode_64bit)
8885             ins->active_seg_prefix = PREFIX_ES;
8886           break;
8887         case 0x64:
8888           ins->prefixes |= PREFIX_FS;
8889           ins->last_seg_prefix = i;
8890           ins->active_seg_prefix = PREFIX_FS;
8891           break;
8892         case 0x65:
8893           ins->prefixes |= PREFIX_GS;
8894           ins->last_seg_prefix = i;
8895           ins->active_seg_prefix = PREFIX_GS;
8896           break;
8897         case 0x66:
8898           ins->prefixes |= PREFIX_DATA;
8899           ins->last_data_prefix = i;
8900           break;
8901         case 0x67:
8902           ins->prefixes |= PREFIX_ADDR;
8903           ins->last_addr_prefix = i;
8904           break;
8905         case FWAIT_OPCODE:
8906           /* fwait is really an instruction.  If there are prefixes
8907              before the fwait, they belong to the fwait, *not* to the
8908              following instruction.  */
8909           ins->fwait_prefix = i;
8910           if (ins->prefixes || ins->rex)
8911             {
8912               ins->prefixes |= PREFIX_FWAIT;
8913               ins->codep++;
8914               /* This ensures that the previous REX prefixes are noticed
8915                  as unused prefixes, as in the return case below.  */
8916               ins->rex_used = ins->rex;
8917               return 1;
8918             }
8919           ins->prefixes = PREFIX_FWAIT;
8920           break;
8921         default:
8922           return 1;
8923         }
8924       /* Rex is ignored when followed by another prefix.  */
8925       if (ins->rex)
8926         {
8927           ins->rex_used = ins->rex;
8928           return 1;
8929         }
8930       if (*ins->codep != FWAIT_OPCODE)
8931         ins->all_prefixes[i++] = *ins->codep;
8932       ins->rex = newrex;
8933       ins->codep++;
8934       length++;
8935     }
8936   return 0;
8937 }
8938
8939 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
8940    prefix byte.  */
8941
8942 static const char *
8943 prefix_name (instr_info *ins, int pref, int sizeflag)
8944 {
8945   static const char *rexes [16] =
8946     {
8947       "rex",            /* 0x40 */
8948       "rex.B",          /* 0x41 */
8949       "rex.X",          /* 0x42 */
8950       "rex.XB",         /* 0x43 */
8951       "rex.R",          /* 0x44 */
8952       "rex.RB",         /* 0x45 */
8953       "rex.RX",         /* 0x46 */
8954       "rex.RXB",        /* 0x47 */
8955       "rex.W",          /* 0x48 */
8956       "rex.WB",         /* 0x49 */
8957       "rex.WX",         /* 0x4a */
8958       "rex.WXB",        /* 0x4b */
8959       "rex.WR",         /* 0x4c */
8960       "rex.WRB",        /* 0x4d */
8961       "rex.WRX",        /* 0x4e */
8962       "rex.WRXB",       /* 0x4f */
8963     };
8964
8965   switch (pref)
8966     {
8967     /* REX prefixes family.  */
8968     case 0x40:
8969     case 0x41:
8970     case 0x42:
8971     case 0x43:
8972     case 0x44:
8973     case 0x45:
8974     case 0x46:
8975     case 0x47:
8976     case 0x48:
8977     case 0x49:
8978     case 0x4a:
8979     case 0x4b:
8980     case 0x4c:
8981     case 0x4d:
8982     case 0x4e:
8983     case 0x4f:
8984       return rexes [pref - 0x40];
8985     case 0xf3:
8986       return "repz";
8987     case 0xf2:
8988       return "repnz";
8989     case 0xf0:
8990       return "lock";
8991     case 0x2e:
8992       return "cs";
8993     case 0x36:
8994       return "ss";
8995     case 0x3e:
8996       return "ds";
8997     case 0x26:
8998       return "es";
8999     case 0x64:
9000       return "fs";
9001     case 0x65:
9002       return "gs";
9003     case 0x66:
9004       return (sizeflag & DFLAG) ? "data16" : "data32";
9005     case 0x67:
9006       if (ins->address_mode == mode_64bit)
9007         return (sizeflag & AFLAG) ? "addr32" : "addr64";
9008       else
9009         return (sizeflag & AFLAG) ? "addr16" : "addr32";
9010     case FWAIT_OPCODE:
9011       return "fwait";
9012     case REP_PREFIX:
9013       return "rep";
9014     case XACQUIRE_PREFIX:
9015       return "xacquire";
9016     case XRELEASE_PREFIX:
9017       return "xrelease";
9018     case BND_PREFIX:
9019       return "bnd";
9020     case NOTRACK_PREFIX:
9021       return "notrack";
9022     default:
9023       return NULL;
9024     }
9025 }
9026
9027 void
9028 print_i386_disassembler_options (FILE *stream)
9029 {
9030   fprintf (stream, _("\n\
9031 The following i386/x86-64 specific disassembler options are supported for use\n\
9032 with the -M switch (multiple options should be separated by commas):\n"));
9033
9034   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
9035   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
9036   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
9037   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
9038   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
9039   fprintf (stream, _("  att-mnemonic\n"
9040                      "              Display instruction in AT&T mnemonic\n"));
9041   fprintf (stream, _("  intel-mnemonic\n"
9042                      "              Display instruction in Intel mnemonic\n"));
9043   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
9044   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
9045   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
9046   fprintf (stream, _("  data32      Assume 32bit data size\n"));
9047   fprintf (stream, _("  data16      Assume 16bit data size\n"));
9048   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
9049   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
9050   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
9051 }
9052
9053 /* Bad opcode.  */
9054 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
9055
9056 /* Get a pointer to struct dis386 with a valid name.  */
9057
9058 static const struct dis386 *
9059 get_valid_dis386 (const struct dis386 *dp, instr_info *ins)
9060 {
9061   int vindex, vex_table_index;
9062
9063   if (dp->name != NULL)
9064     return dp;
9065
9066   switch (dp->op[0].bytemode)
9067     {
9068     case USE_REG_TABLE:
9069       dp = &reg_table[dp->op[1].bytemode][ins->modrm.reg];
9070       break;
9071
9072     case USE_MOD_TABLE:
9073       vindex = ins->modrm.mod == 0x3 ? 1 : 0;
9074       dp = &mod_table[dp->op[1].bytemode][vindex];
9075       break;
9076
9077     case USE_RM_TABLE:
9078       dp = &rm_table[dp->op[1].bytemode][ins->modrm.rm];
9079       break;
9080
9081     case USE_PREFIX_TABLE:
9082       if (ins->need_vex)
9083         {
9084           /* The prefix in VEX is implicit.  */
9085           switch (ins->vex.prefix)
9086             {
9087             case 0:
9088               vindex = 0;
9089               break;
9090             case REPE_PREFIX_OPCODE:
9091               vindex = 1;
9092               break;
9093             case DATA_PREFIX_OPCODE:
9094               vindex = 2;
9095               break;
9096             case REPNE_PREFIX_OPCODE:
9097               vindex = 3;
9098               break;
9099             default:
9100               abort ();
9101               break;
9102             }
9103         }
9104       else
9105         {
9106           int last_prefix = -1;
9107           int prefix = 0;
9108           vindex = 0;
9109           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
9110              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
9111              last one wins.  */
9112           if ((ins->prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
9113             {
9114               if (ins->last_repz_prefix > ins->last_repnz_prefix)
9115                 {
9116                   vindex = 1;
9117                   prefix = PREFIX_REPZ;
9118                   last_prefix = ins->last_repz_prefix;
9119                 }
9120               else
9121                 {
9122                   vindex = 3;
9123                   prefix = PREFIX_REPNZ;
9124                   last_prefix = ins->last_repnz_prefix;
9125                 }
9126
9127               /* Check if prefix should be ignored.  */
9128               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
9129                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
9130                    & prefix) != 0
9131                   && !prefix_table[dp->op[1].bytemode][vindex].name)
9132                 vindex = 0;
9133             }
9134
9135           if (vindex == 0 && (ins->prefixes & PREFIX_DATA) != 0)
9136             {
9137               vindex = 2;
9138               prefix = PREFIX_DATA;
9139               last_prefix = ins->last_data_prefix;
9140             }
9141
9142           if (vindex != 0)
9143             {
9144               ins->used_prefixes |= prefix;
9145               ins->all_prefixes[last_prefix] = 0;
9146             }
9147         }
9148       dp = &prefix_table[dp->op[1].bytemode][vindex];
9149       break;
9150
9151     case USE_X86_64_TABLE:
9152       vindex = ins->address_mode == mode_64bit ? 1 : 0;
9153       dp = &x86_64_table[dp->op[1].bytemode][vindex];
9154       break;
9155
9156     case USE_3BYTE_TABLE:
9157       FETCH_DATA (ins->info, ins->codep + 2);
9158       vindex = *ins->codep++;
9159       dp = &three_byte_table[dp->op[1].bytemode][vindex];
9160       ins->end_codep = ins->codep;
9161       ins->modrm.mod = (*ins->codep >> 6) & 3;
9162       ins->modrm.reg = (*ins->codep >> 3) & 7;
9163       ins->modrm.rm = *ins->codep & 7;
9164       break;
9165
9166     case USE_VEX_LEN_TABLE:
9167       if (!ins->need_vex)
9168         abort ();
9169
9170       switch (ins->vex.length)
9171         {
9172         case 128:
9173           vindex = 0;
9174           break;
9175         case 512:
9176           /* This allows re-using in particular table entries where only
9177              128-bit operand size (VEX.L=0 / EVEX.L'L=0) are valid.  */
9178           if (ins->vex.evex)
9179             {
9180         case 256:
9181               vindex = 1;
9182               break;
9183             }
9184         /* Fall through.  */
9185         default:
9186           abort ();
9187           break;
9188         }
9189
9190       dp = &vex_len_table[dp->op[1].bytemode][vindex];
9191       break;
9192
9193     case USE_EVEX_LEN_TABLE:
9194       if (!ins->vex.evex)
9195         abort ();
9196
9197       switch (ins->vex.length)
9198         {
9199         case 128:
9200           vindex = 0;
9201           break;
9202         case 256:
9203           vindex = 1;
9204           break;
9205         case 512:
9206           vindex = 2;
9207           break;
9208         default:
9209           abort ();
9210           break;
9211         }
9212
9213       dp = &evex_len_table[dp->op[1].bytemode][vindex];
9214       break;
9215
9216     case USE_XOP_8F_TABLE:
9217       FETCH_DATA (ins->info, ins->codep + 3);
9218       ins->rex = ~(*ins->codep >> 5) & 0x7;
9219
9220       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
9221       switch ((*ins->codep & 0x1f))
9222         {
9223         default:
9224           dp = &bad_opcode;
9225           return dp;
9226         case 0x8:
9227           vex_table_index = XOP_08;
9228           break;
9229         case 0x9:
9230           vex_table_index = XOP_09;
9231           break;
9232         case 0xa:
9233           vex_table_index = XOP_0A;
9234           break;
9235         }
9236       ins->codep++;
9237       ins->vex.w = *ins->codep & 0x80;
9238       if (ins->vex.w && ins->address_mode == mode_64bit)
9239         ins->rex |= REX_W;
9240
9241       ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
9242       if (ins->address_mode != mode_64bit)
9243         {
9244           /* In 16/32-bit mode REX_B is silently ignored.  */
9245           ins->rex &= ~REX_B;
9246         }
9247
9248       ins->vex.length = (*ins->codep & 0x4) ? 256 : 128;
9249       switch ((*ins->codep & 0x3))
9250         {
9251         case 0:
9252           break;
9253         case 1:
9254           ins->vex.prefix = DATA_PREFIX_OPCODE;
9255           break;
9256         case 2:
9257           ins->vex.prefix = REPE_PREFIX_OPCODE;
9258           break;
9259         case 3:
9260           ins->vex.prefix = REPNE_PREFIX_OPCODE;
9261           break;
9262         }
9263       ins->need_vex = true;
9264       ins->codep++;
9265       vindex = *ins->codep++;
9266       dp = &xop_table[vex_table_index][vindex];
9267
9268       ins->end_codep = ins->codep;
9269       FETCH_DATA (ins->info, ins->codep + 1);
9270       ins->modrm.mod = (*ins->codep >> 6) & 3;
9271       ins->modrm.reg = (*ins->codep >> 3) & 7;
9272       ins->modrm.rm = *ins->codep & 7;
9273
9274       /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid
9275          having to decode the bits for every otherwise valid encoding.  */
9276       if (ins->vex.prefix)
9277         return &bad_opcode;
9278       break;
9279
9280     case USE_VEX_C4_TABLE:
9281       /* VEX prefix.  */
9282       FETCH_DATA (ins->info, ins->codep + 3);
9283       ins->rex = ~(*ins->codep >> 5) & 0x7;
9284       switch ((*ins->codep & 0x1f))
9285         {
9286         default:
9287           dp = &bad_opcode;
9288           return dp;
9289         case 0x1:
9290           vex_table_index = VEX_0F;
9291           break;
9292         case 0x2:
9293           vex_table_index = VEX_0F38;
9294           break;
9295         case 0x3:
9296           vex_table_index = VEX_0F3A;
9297           break;
9298         }
9299       ins->codep++;
9300       ins->vex.w = *ins->codep & 0x80;
9301       if (ins->address_mode == mode_64bit)
9302         {
9303           if (ins->vex.w)
9304             ins->rex |= REX_W;
9305         }
9306       else
9307         {
9308           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
9309              is ignored, other REX bits are 0 and the highest bit in
9310              VEX.vvvv is also ignored (but we mustn't clear it here).  */
9311           ins->rex = 0;
9312         }
9313       ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
9314       ins->vex.length = (*ins->codep & 0x4) ? 256 : 128;
9315       switch ((*ins->codep & 0x3))
9316         {
9317         case 0:
9318           break;
9319         case 1:
9320           ins->vex.prefix = DATA_PREFIX_OPCODE;
9321           break;
9322         case 2:
9323           ins->vex.prefix = REPE_PREFIX_OPCODE;
9324           break;
9325         case 3:
9326           ins->vex.prefix = REPNE_PREFIX_OPCODE;
9327           break;
9328         }
9329       ins->need_vex = true;
9330       ins->codep++;
9331       vindex = *ins->codep++;
9332       dp = &vex_table[vex_table_index][vindex];
9333       ins->end_codep = ins->codep;
9334       /* There is no MODRM byte for VEX0F 77.  */
9335       if (vex_table_index != VEX_0F || vindex != 0x77)
9336         {
9337           FETCH_DATA (ins->info, ins->codep + 1);
9338           ins->modrm.mod = (*ins->codep >> 6) & 3;
9339           ins->modrm.reg = (*ins->codep >> 3) & 7;
9340           ins->modrm.rm = *ins->codep & 7;
9341         }
9342       break;
9343
9344     case USE_VEX_C5_TABLE:
9345       /* VEX prefix.  */
9346       FETCH_DATA (ins->info, ins->codep + 2);
9347       ins->rex = (*ins->codep & 0x80) ? 0 : REX_R;
9348
9349       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
9350          VEX.vvvv is 1.  */
9351       ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
9352       ins->vex.length = (*ins->codep & 0x4) ? 256 : 128;
9353       switch ((*ins->codep & 0x3))
9354         {
9355         case 0:
9356           break;
9357         case 1:
9358           ins->vex.prefix = DATA_PREFIX_OPCODE;
9359           break;
9360         case 2:
9361           ins->vex.prefix = REPE_PREFIX_OPCODE;
9362           break;
9363         case 3:
9364           ins->vex.prefix = REPNE_PREFIX_OPCODE;
9365           break;
9366         }
9367       ins->need_vex = true;
9368       ins->codep++;
9369       vindex = *ins->codep++;
9370       dp = &vex_table[dp->op[1].bytemode][vindex];
9371       ins->end_codep = ins->codep;
9372       /* There is no MODRM byte for VEX 77.  */
9373       if (vindex != 0x77)
9374         {
9375           FETCH_DATA (ins->info, ins->codep + 1);
9376           ins->modrm.mod = (*ins->codep >> 6) & 3;
9377           ins->modrm.reg = (*ins->codep >> 3) & 7;
9378           ins->modrm.rm = *ins->codep & 7;
9379         }
9380       break;
9381
9382     case USE_VEX_W_TABLE:
9383       if (!ins->need_vex)
9384         abort ();
9385
9386       dp = &vex_w_table[dp->op[1].bytemode][ins->vex.w];
9387       break;
9388
9389     case USE_EVEX_TABLE:
9390       ins->two_source_ops = false;
9391       /* EVEX prefix.  */
9392       ins->vex.evex = true;
9393       FETCH_DATA (ins->info, ins->codep + 4);
9394       /* The first byte after 0x62.  */
9395       ins->rex = ~(*ins->codep >> 5) & 0x7;
9396       ins->vex.r = *ins->codep & 0x10;
9397       switch ((*ins->codep & 0xf))
9398         {
9399         default:
9400           return &bad_opcode;
9401         case 0x1:
9402           vex_table_index = EVEX_0F;
9403           break;
9404         case 0x2:
9405           vex_table_index = EVEX_0F38;
9406           break;
9407         case 0x3:
9408           vex_table_index = EVEX_0F3A;
9409           break;
9410         case 0x5:
9411           vex_table_index = EVEX_MAP5;
9412           break;
9413         case 0x6:
9414           vex_table_index = EVEX_MAP6;
9415           break;
9416         }
9417
9418       /* The second byte after 0x62.  */
9419       ins->codep++;
9420       ins->vex.w = *ins->codep & 0x80;
9421       if (ins->vex.w && ins->address_mode == mode_64bit)
9422         ins->rex |= REX_W;
9423
9424       ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
9425
9426       /* The U bit.  */
9427       if (!(*ins->codep & 0x4))
9428         return &bad_opcode;
9429
9430       switch ((*ins->codep & 0x3))
9431         {
9432         case 0:
9433           break;
9434         case 1:
9435           ins->vex.prefix = DATA_PREFIX_OPCODE;
9436           break;
9437         case 2:
9438           ins->vex.prefix = REPE_PREFIX_OPCODE;
9439           break;
9440         case 3:
9441           ins->vex.prefix = REPNE_PREFIX_OPCODE;
9442           break;
9443         }
9444
9445       /* The third byte after 0x62.  */
9446       ins->codep++;
9447
9448       /* Remember the static rounding bits.  */
9449       ins->vex.ll = (*ins->codep >> 5) & 3;
9450       ins->vex.b = *ins->codep & 0x10;
9451
9452       ins->vex.v = *ins->codep & 0x8;
9453       ins->vex.mask_register_specifier = *ins->codep & 0x7;
9454       ins->vex.zeroing = *ins->codep & 0x80;
9455
9456       if (ins->address_mode != mode_64bit)
9457         {
9458           /* In 16/32-bit mode silently ignore following bits.  */
9459           ins->rex &= ~REX_B;
9460           ins->vex.r = true;
9461         }
9462
9463       ins->need_vex = true;
9464       ins->codep++;
9465       vindex = *ins->codep++;
9466       dp = &evex_table[vex_table_index][vindex];
9467       ins->end_codep = ins->codep;
9468       FETCH_DATA (ins->info, ins->codep + 1);
9469       ins->modrm.mod = (*ins->codep >> 6) & 3;
9470       ins->modrm.reg = (*ins->codep >> 3) & 7;
9471       ins->modrm.rm = *ins->codep & 7;
9472
9473       /* Set vector length.  */
9474       if (ins->modrm.mod == 3 && ins->vex.b)
9475         ins->vex.length = 512;
9476       else
9477         {
9478           switch (ins->vex.ll)
9479             {
9480             case 0x0:
9481               ins->vex.length = 128;
9482               break;
9483             case 0x1:
9484               ins->vex.length = 256;
9485               break;
9486             case 0x2:
9487               ins->vex.length = 512;
9488               break;
9489             default:
9490               return &bad_opcode;
9491             }
9492         }
9493       break;
9494
9495     case 0:
9496       dp = &bad_opcode;
9497       break;
9498
9499     default:
9500       abort ();
9501     }
9502
9503   if (dp->name != NULL)
9504     return dp;
9505   else
9506     return get_valid_dis386 (dp, ins);
9507 }
9508
9509 static void
9510 get_sib (instr_info *ins, int sizeflag)
9511 {
9512   /* If modrm.mod == 3, operand must be register.  */
9513   if (ins->need_modrm
9514       && ((sizeflag & AFLAG) || ins->address_mode == mode_64bit)
9515       && ins->modrm.mod != 3
9516       && ins->modrm.rm == 4)
9517     {
9518       FETCH_DATA (ins->info, ins->codep + 2);
9519       ins->sib.index = (ins->codep[1] >> 3) & 7;
9520       ins->sib.scale = (ins->codep[1] >> 6) & 3;
9521       ins->sib.base = ins->codep[1] & 7;
9522       ins->has_sib = true;
9523     }
9524   else
9525     ins->has_sib = false;
9526 }
9527
9528 /* Like oappend (below), but S is a string starting with '%'.  In
9529    Intel syntax, the '%' is elided.  */
9530
9531 static void
9532 oappend_register (instr_info *ins, const char *s)
9533 {
9534   oappend_with_style (ins, s + ins->intel_syntax, dis_style_register);
9535 }
9536
9537 /* Wrap around a call to INS->info->fprintf_styled_func, printing FMT.
9538    STYLE is the default style to use in the fprintf_styled_func calls,
9539    however, FMT might include embedded style markers (see oappend_style),
9540    these embedded markers are not printed, but instead change the style
9541    used in the next fprintf_styled_func call.  */
9542
9543 static void ATTRIBUTE_PRINTF_3
9544 i386_dis_printf (instr_info *ins, enum disassembler_style style,
9545                  const char *fmt, ...)
9546 {
9547   va_list ap;
9548   enum disassembler_style curr_style = style;
9549   const char *start, *curr;
9550   char staging_area[40];
9551
9552   va_start (ap, fmt);
9553   /* In particular print_insn()'s processing of op_txt[] can hand rather long
9554      strings here.  Bypass vsnprintf() in such cases to avoid capacity issues
9555      with the staging area.  */
9556   if (strcmp (fmt, "%s"))
9557     {
9558       int res = vsnprintf (staging_area, sizeof (staging_area), fmt, ap);
9559
9560       va_end (ap);
9561
9562       if (res < 0)
9563         return;
9564
9565       if ((size_t) res >= sizeof (staging_area))
9566         abort ();
9567
9568       start = curr = staging_area;
9569     }
9570   else
9571     {
9572       start = curr = va_arg (ap, const char *);
9573       va_end (ap);
9574     }
9575
9576   do
9577     {
9578       if (*curr == '\0'
9579           || (*curr == STYLE_MARKER_CHAR
9580               && ISXDIGIT (*(curr + 1))
9581               && *(curr + 2) == STYLE_MARKER_CHAR))
9582         {
9583           /* Output content between our START position and CURR.  */
9584           int len = curr - start;
9585           int n = (*ins->info->fprintf_styled_func) (ins->info->stream,
9586                                                      curr_style,
9587                                                      "%.*s", len, start);
9588           if (n < 0)
9589             break;
9590
9591           if (*curr == '\0')
9592             break;
9593
9594           /* Skip over the initial STYLE_MARKER_CHAR.  */
9595           ++curr;
9596
9597           /* Update the CURR_STYLE.  As there are less than 16 styles, it
9598              is possible, that if the input is corrupted in some way, that
9599              we might set CURR_STYLE to an invalid value.  Don't worry
9600              though, we check for this situation.  */
9601           if (*curr >= '0' && *curr <= '9')
9602             curr_style = (enum disassembler_style) (*curr - '0');
9603           else if (*curr >= 'a' && *curr <= 'f')
9604             curr_style = (enum disassembler_style) (*curr - 'a' + 10);
9605           else
9606             curr_style = dis_style_text;
9607
9608           /* Check for an invalid style having been selected.  This should
9609              never happen, but it doesn't hurt to be a little paranoid.  */
9610           if (curr_style > dis_style_comment_start)
9611             curr_style = dis_style_text;
9612
9613           /* Skip the hex character, and the closing STYLE_MARKER_CHAR.  */
9614           curr += 2;
9615
9616           /* Reset the START to after the style marker.  */
9617           start = curr;
9618         }
9619       else
9620         ++curr;
9621     }
9622   while (true);
9623 }
9624
9625 static int
9626 print_insn (bfd_vma pc, disassemble_info *info, int intel_syntax)
9627 {
9628   const struct dis386 *dp;
9629   int i;
9630   char *op_txt[MAX_OPERANDS];
9631   int needcomma;
9632   bool intel_swap_2_3;
9633   int sizeflag, orig_sizeflag;
9634   const char *p;
9635   struct dis_private priv;
9636   int prefix_length;
9637   int op_count;
9638   instr_info ins = {
9639     .info = info,
9640     .intel_syntax = intel_syntax >= 0
9641                     ? intel_syntax
9642                     : (info->mach & bfd_mach_i386_intel_syntax) != 0,
9643     .intel_mnemonic = !SYSV386_COMPAT,
9644     .op_index[0 ... MAX_OPERANDS - 1] = -1,
9645     .start_pc = pc,
9646     .start_codep = priv.the_buffer,
9647     .codep = priv.the_buffer,
9648     .obufp = ins.obuf,
9649     .last_lock_prefix = -1,
9650     .last_repz_prefix = -1,
9651     .last_repnz_prefix = -1,
9652     .last_data_prefix = -1,
9653     .last_addr_prefix = -1,
9654     .last_rex_prefix = -1,
9655     .last_seg_prefix = -1,
9656     .fwait_prefix = -1,
9657   };
9658   char op_out[MAX_OPERANDS][MAX_OPERAND_BUFFER_SIZE];
9659
9660   priv.orig_sizeflag = AFLAG | DFLAG;
9661   if ((info->mach & bfd_mach_i386_i386) != 0)
9662     ins.address_mode = mode_32bit;
9663   else if (info->mach == bfd_mach_i386_i8086)
9664     {
9665       ins.address_mode = mode_16bit;
9666       priv.orig_sizeflag = 0;
9667     }
9668   else
9669     ins.address_mode = mode_64bit;
9670
9671   for (p = info->disassembler_options; p != NULL;)
9672     {
9673       if (startswith (p, "amd64"))
9674         ins.isa64 = amd64;
9675       else if (startswith (p, "intel64"))
9676         ins.isa64 = intel64;
9677       else if (startswith (p, "x86-64"))
9678         {
9679           ins.address_mode = mode_64bit;
9680           priv.orig_sizeflag |= AFLAG | DFLAG;
9681         }
9682       else if (startswith (p, "i386"))
9683         {
9684           ins.address_mode = mode_32bit;
9685           priv.orig_sizeflag |= AFLAG | DFLAG;
9686         }
9687       else if (startswith (p, "i8086"))
9688         {
9689           ins.address_mode = mode_16bit;
9690           priv.orig_sizeflag &= ~(AFLAG | DFLAG);
9691         }
9692       else if (startswith (p, "intel"))
9693         {
9694           ins.intel_syntax = 1;
9695           if (startswith (p + 5, "-mnemonic"))
9696             ins.intel_mnemonic = true;
9697         }
9698       else if (startswith (p, "att"))
9699         {
9700           ins.intel_syntax = 0;
9701           if (startswith (p + 3, "-mnemonic"))
9702             ins.intel_mnemonic = false;
9703         }
9704       else if (startswith (p, "addr"))
9705         {
9706           if (ins.address_mode == mode_64bit)
9707             {
9708               if (p[4] == '3' && p[5] == '2')
9709                 priv.orig_sizeflag &= ~AFLAG;
9710               else if (p[4] == '6' && p[5] == '4')
9711                 priv.orig_sizeflag |= AFLAG;
9712             }
9713           else
9714             {
9715               if (p[4] == '1' && p[5] == '6')
9716                 priv.orig_sizeflag &= ~AFLAG;
9717               else if (p[4] == '3' && p[5] == '2')
9718                 priv.orig_sizeflag |= AFLAG;
9719             }
9720         }
9721       else if (startswith (p, "data"))
9722         {
9723           if (p[4] == '1' && p[5] == '6')
9724             priv.orig_sizeflag &= ~DFLAG;
9725           else if (p[4] == '3' && p[5] == '2')
9726             priv.orig_sizeflag |= DFLAG;
9727         }
9728       else if (startswith (p, "suffix"))
9729         priv.orig_sizeflag |= SUFFIX_ALWAYS;
9730
9731       p = strchr (p, ',');
9732       if (p != NULL)
9733         p++;
9734     }
9735
9736   if (ins.address_mode == mode_64bit && sizeof (bfd_vma) < 8)
9737     {
9738       i386_dis_printf (&ins, dis_style_text, _("64-bit address is disabled"));
9739       return -1;
9740     }
9741
9742   if (ins.intel_syntax)
9743     {
9744       ins.open_char = '[';
9745       ins.close_char = ']';
9746       ins.separator_char = '+';
9747       ins.scale_char = '*';
9748     }
9749   else
9750     {
9751       ins.open_char = '(';
9752       ins.close_char =  ')';
9753       ins.separator_char = ',';
9754       ins.scale_char = ',';
9755     }
9756
9757   /* The output looks better if we put 7 bytes on a line, since that
9758      puts most long word instructions on a single line.  */
9759   info->bytes_per_line = 7;
9760
9761   info->private_data = &priv;
9762   priv.max_fetched = priv.the_buffer;
9763   priv.insn_start = pc;
9764
9765   for (i = 0; i < MAX_OPERANDS; ++i)
9766     {
9767       op_out[i][0] = 0;
9768       ins.op_out[i] = op_out[i];
9769     }
9770
9771   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
9772     {
9773       /* Getting here means we tried for data but didn't get it.  That
9774          means we have an incomplete instruction of some sort.  Just
9775          print the first byte as a prefix or a .byte pseudo-op.  */
9776       if (ins.codep > priv.the_buffer)
9777         {
9778           const char *name = NULL;
9779
9780           if (ins.prefixes || ins.fwait_prefix >= 0 || (ins.rex & REX_OPCODE))
9781             name = prefix_name (&ins, priv.the_buffer[0], priv.orig_sizeflag);
9782           if (name != NULL)
9783             i386_dis_printf (&ins, dis_style_mnemonic, "%s", name);
9784           else
9785             {
9786               /* Just print the first byte as a .byte instruction.  */
9787               i386_dis_printf (&ins, dis_style_assembler_directive,
9788                                ".byte ");
9789               i386_dis_printf (&ins, dis_style_immediate, "0x%x",
9790                                (unsigned int) priv.the_buffer[0]);
9791             }
9792
9793           return 1;
9794         }
9795
9796       return -1;
9797     }
9798
9799   sizeflag = priv.orig_sizeflag;
9800
9801   if (!ckprefix (&ins) || ins.rex_used)
9802     {
9803       /* Too many prefixes or unused REX prefixes.  */
9804       for (i = 0;
9805            i < (int) ARRAY_SIZE (ins.all_prefixes) && ins.all_prefixes[i];
9806            i++)
9807         i386_dis_printf (&ins, dis_style_mnemonic, "%s%s",
9808                          (i == 0 ? "" : " "),
9809                          prefix_name (&ins, ins.all_prefixes[i], sizeflag));
9810       return i;
9811     }
9812
9813   ins.insn_codep = ins.codep;
9814
9815   FETCH_DATA (info, ins.codep + 1);
9816   ins.two_source_ops = (*ins.codep == 0x62) || (*ins.codep == 0xc8);
9817
9818   if (((ins.prefixes & PREFIX_FWAIT)
9819        && ((*ins.codep < 0xd8) || (*ins.codep > 0xdf))))
9820     {
9821       /* Handle ins.prefixes before fwait.  */
9822       for (i = 0; i < ins.fwait_prefix && ins.all_prefixes[i];
9823            i++)
9824         i386_dis_printf (&ins, dis_style_mnemonic, "%s ",
9825                          prefix_name (&ins, ins.all_prefixes[i], sizeflag));
9826       i386_dis_printf (&ins, dis_style_mnemonic, "fwait");
9827       return i + 1;
9828     }
9829
9830   if (*ins.codep == 0x0f)
9831     {
9832       unsigned char threebyte;
9833
9834       ins.codep++;
9835       FETCH_DATA (info, ins.codep + 1);
9836       threebyte = *ins.codep;
9837       dp = &dis386_twobyte[threebyte];
9838       ins.need_modrm = twobyte_has_modrm[threebyte];
9839       ins.codep++;
9840     }
9841   else
9842     {
9843       dp = &dis386[*ins.codep];
9844       ins.need_modrm = onebyte_has_modrm[*ins.codep];
9845       ins.codep++;
9846     }
9847
9848   /* Save sizeflag for printing the extra ins.prefixes later before updating
9849      it for mnemonic and operand processing.  The prefix names depend
9850      only on the address mode.  */
9851   orig_sizeflag = sizeflag;
9852   if (ins.prefixes & PREFIX_ADDR)
9853     sizeflag ^= AFLAG;
9854   if ((ins.prefixes & PREFIX_DATA))
9855     sizeflag ^= DFLAG;
9856
9857   ins.end_codep = ins.codep;
9858   if (ins.need_modrm)
9859     {
9860       FETCH_DATA (info, ins.codep + 1);
9861       ins.modrm.mod = (*ins.codep >> 6) & 3;
9862       ins.modrm.reg = (*ins.codep >> 3) & 7;
9863       ins.modrm.rm = *ins.codep & 7;
9864     }
9865
9866   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
9867     {
9868       get_sib (&ins, sizeflag);
9869       dofloat (&ins, sizeflag);
9870     }
9871   else
9872     {
9873       dp = get_valid_dis386 (dp, &ins);
9874       if (dp != NULL && putop (&ins, dp->name, sizeflag) == 0)
9875         {
9876           get_sib (&ins, sizeflag);
9877           for (i = 0; i < MAX_OPERANDS; ++i)
9878             {
9879               ins.obufp = ins.op_out[i];
9880               ins.op_ad = MAX_OPERANDS - 1 - i;
9881               if (dp->op[i].rtn)
9882                 (*dp->op[i].rtn) (&ins, dp->op[i].bytemode, sizeflag);
9883               /* For EVEX instruction after the last operand masking
9884                  should be printed.  */
9885               if (i == 0 && ins.vex.evex)
9886                 {
9887                   /* Don't print {%k0}.  */
9888                   if (ins.vex.mask_register_specifier)
9889                     {
9890                       const char *reg_name
9891                         = att_names_mask[ins.vex.mask_register_specifier];
9892
9893                       oappend (&ins, "{");
9894                       oappend_register (&ins, reg_name);
9895                       oappend (&ins, "}");
9896                     }
9897                   if (ins.vex.zeroing)
9898                     oappend (&ins, "{z}");
9899
9900                   /* S/G insns require a mask and don't allow
9901                      zeroing-masking.  */
9902                   if ((dp->op[0].bytemode == vex_vsib_d_w_dq_mode
9903                        || dp->op[0].bytemode == vex_vsib_q_w_dq_mode)
9904                       && (ins.vex.mask_register_specifier == 0
9905                           || ins.vex.zeroing))
9906                     oappend (&ins, "/(bad)");
9907                 }
9908             }
9909
9910           /* Check whether rounding control was enabled for an insn not
9911              supporting it.  */
9912           if (ins.modrm.mod == 3 && ins.vex.b
9913               && !(ins.evex_used & EVEX_b_used))
9914             {
9915               for (i = 0; i < MAX_OPERANDS; ++i)
9916                 {
9917                   ins.obufp = ins.op_out[i];
9918                   if (*ins.obufp)
9919                     continue;
9920                   oappend (&ins, names_rounding[ins.vex.ll]);
9921                   oappend (&ins, "bad}");
9922                   break;
9923                 }
9924             }
9925         }
9926     }
9927
9928   /* Clear instruction information.  */
9929   info->insn_info_valid = 0;
9930   info->branch_delay_insns = 0;
9931   info->data_size = 0;
9932   info->insn_type = dis_noninsn;
9933   info->target = 0;
9934   info->target2 = 0;
9935
9936   /* Reset jump operation indicator.  */
9937   ins.op_is_jump = false;
9938   {
9939     int jump_detection = 0;
9940
9941     /* Extract flags.  */
9942     for (i = 0; i < MAX_OPERANDS; ++i)
9943       {
9944         if ((dp->op[i].rtn == OP_J)
9945             || (dp->op[i].rtn == OP_indirE))
9946           jump_detection |= 1;
9947         else if ((dp->op[i].rtn == BND_Fixup)
9948                  || (!dp->op[i].rtn && !dp->op[i].bytemode))
9949           jump_detection |= 2;
9950         else if ((dp->op[i].bytemode == cond_jump_mode)
9951                  || (dp->op[i].bytemode == loop_jcxz_mode))
9952           jump_detection |= 4;
9953       }
9954
9955     /* Determine if this is a jump or branch.  */
9956     if ((jump_detection & 0x3) == 0x3)
9957       {
9958         ins.op_is_jump = true;
9959         if (jump_detection & 0x4)
9960           info->insn_type = dis_condbranch;
9961         else
9962           info->insn_type = (dp->name && !strncmp (dp->name, "call", 4))
9963             ? dis_jsr : dis_branch;
9964       }
9965   }
9966
9967   /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
9968      are all 0s in inverted form.  */
9969   if (ins.need_vex && ins.vex.register_specifier != 0)
9970     {
9971       i386_dis_printf (&ins, dis_style_text, "(bad)");
9972       return ins.end_codep - priv.the_buffer;
9973     }
9974
9975   /* If EVEX.z is set, there must be an actual mask register in use.  */
9976   if (ins.vex.zeroing && ins.vex.mask_register_specifier == 0)
9977     {
9978       i386_dis_printf (&ins, dis_style_text, "(bad)");
9979       return ins.end_codep - priv.the_buffer;
9980     }
9981
9982   switch (dp->prefix_requirement)
9983     {
9984     case PREFIX_DATA:
9985       /* If only the data prefix is marked as mandatory, its absence renders
9986          the encoding invalid.  Most other PREFIX_OPCODE rules still apply.  */
9987       if (ins.need_vex ? !ins.vex.prefix : !(ins.prefixes & PREFIX_DATA))
9988         {
9989           i386_dis_printf (&ins, dis_style_text, "(bad)");
9990           return ins.end_codep - priv.the_buffer;
9991         }
9992       ins.used_prefixes |= PREFIX_DATA;
9993       /* Fall through.  */
9994     case PREFIX_OPCODE:
9995       /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
9996          unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
9997          used by putop and MMX/SSE operand and may be overridden by the
9998          PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
9999          separately.  */
10000       if (((ins.need_vex
10001             ? ins.vex.prefix == REPE_PREFIX_OPCODE
10002               || ins.vex.prefix == REPNE_PREFIX_OPCODE
10003             : (ins.prefixes
10004                & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
10005            && (ins.used_prefixes
10006                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
10007           || (((ins.need_vex
10008                 ? ins.vex.prefix == DATA_PREFIX_OPCODE
10009                 : ((ins.prefixes
10010                     & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
10011                    == PREFIX_DATA))
10012                && (ins.used_prefixes & PREFIX_DATA) == 0))
10013           || (ins.vex.evex && dp->prefix_requirement != PREFIX_DATA
10014               && !ins.vex.w != !(ins.used_prefixes & PREFIX_DATA)))
10015         {
10016           i386_dis_printf (&ins, dis_style_text, "(bad)");
10017           return ins.end_codep - priv.the_buffer;
10018         }
10019       break;
10020
10021     case PREFIX_IGNORED:
10022       /* Zap data size and rep prefixes from used_prefixes and reinstate their
10023          origins in all_prefixes.  */
10024       ins.used_prefixes &= ~PREFIX_OPCODE;
10025       if (ins.last_data_prefix >= 0)
10026         ins.all_prefixes[ins.last_data_prefix] = 0x66;
10027       if (ins.last_repz_prefix >= 0)
10028         ins.all_prefixes[ins.last_repz_prefix] = 0xf3;
10029       if (ins.last_repnz_prefix >= 0)
10030         ins.all_prefixes[ins.last_repnz_prefix] = 0xf2;
10031       break;
10032     }
10033
10034   /* Check if the REX prefix is used.  */
10035   if ((ins.rex ^ ins.rex_used) == 0
10036       && !ins.need_vex && ins.last_rex_prefix >= 0)
10037     ins.all_prefixes[ins.last_rex_prefix] = 0;
10038
10039   /* Check if the SEG prefix is used.  */
10040   if ((ins.prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
10041                        | PREFIX_FS | PREFIX_GS)) != 0
10042       && (ins.used_prefixes & ins.active_seg_prefix) != 0)
10043     ins.all_prefixes[ins.last_seg_prefix] = 0;
10044
10045   /* Check if the ADDR prefix is used.  */
10046   if ((ins.prefixes & PREFIX_ADDR) != 0
10047       && (ins.used_prefixes & PREFIX_ADDR) != 0)
10048     ins.all_prefixes[ins.last_addr_prefix] = 0;
10049
10050   /* Check if the DATA prefix is used.  */
10051   if ((ins.prefixes & PREFIX_DATA) != 0
10052       && (ins.used_prefixes & PREFIX_DATA) != 0
10053       && !ins.need_vex)
10054     ins.all_prefixes[ins.last_data_prefix] = 0;
10055
10056   /* Print the extra ins.prefixes.  */
10057   prefix_length = 0;
10058   for (i = 0; i < (int) ARRAY_SIZE (ins.all_prefixes); i++)
10059     if (ins.all_prefixes[i])
10060       {
10061         const char *name;
10062         name = prefix_name (&ins, ins.all_prefixes[i], orig_sizeflag);
10063         if (name == NULL)
10064           abort ();
10065         prefix_length += strlen (name) + 1;
10066         i386_dis_printf (&ins, dis_style_mnemonic, "%s ", name);
10067       }
10068
10069   /* Check maximum code length.  */
10070   if ((ins.codep - ins.start_codep) > MAX_CODE_LENGTH)
10071     {
10072       i386_dis_printf (&ins, dis_style_text, "(bad)");
10073       return MAX_CODE_LENGTH;
10074     }
10075
10076   /* Calculate the number of operands this instruction has.  */
10077   op_count = 0;
10078   for (i = 0; i < MAX_OPERANDS; ++i)
10079     if (*ins.op_out[i] != '\0')
10080       ++op_count;
10081
10082   /* Calculate the number of spaces to print after the mnemonic.  */
10083   ins.obufp = ins.mnemonicendp;
10084   if (op_count > 0)
10085     {
10086       i = strlen (ins.obuf) + prefix_length;
10087       if (i < 7)
10088         i = 7 - i;
10089       else
10090         i = 1;
10091     }
10092   else
10093     i = 0;
10094
10095   /* Print the instruction mnemonic along with any trailing whitespace.  */
10096   i386_dis_printf (&ins, dis_style_mnemonic, "%s%*s", ins.obuf, i, "");
10097
10098   /* The enter and bound instructions are printed with operands in the same
10099      order as the intel book; everything else is printed in reverse order.  */
10100   intel_swap_2_3 = false;
10101   if (ins.intel_syntax || ins.two_source_ops)
10102     {
10103       for (i = 0; i < MAX_OPERANDS; ++i)
10104         op_txt[i] = ins.op_out[i];
10105
10106       if (ins.intel_syntax && dp && dp->op[2].rtn == OP_Rounding
10107           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
10108         {
10109           op_txt[2] = ins.op_out[3];
10110           op_txt[3] = ins.op_out[2];
10111           intel_swap_2_3 = true;
10112         }
10113
10114       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
10115         {
10116           bool riprel;
10117
10118           ins.op_ad = ins.op_index[i];
10119           ins.op_index[i] = ins.op_index[MAX_OPERANDS - 1 - i];
10120           ins.op_index[MAX_OPERANDS - 1 - i] = ins.op_ad;
10121           riprel = ins.op_riprel[i];
10122           ins.op_riprel[i] = ins.op_riprel[MAX_OPERANDS - 1 - i];
10123           ins.op_riprel[MAX_OPERANDS - 1 - i] = riprel;
10124         }
10125     }
10126   else
10127     {
10128       for (i = 0; i < MAX_OPERANDS; ++i)
10129         op_txt[MAX_OPERANDS - 1 - i] = ins.op_out[i];
10130     }
10131
10132   needcomma = 0;
10133   for (i = 0; i < MAX_OPERANDS; ++i)
10134     if (*op_txt[i])
10135       {
10136         /* In Intel syntax embedded rounding / SAE are not separate operands.
10137            Instead they're attached to the prior register operand.  Simply
10138            suppress emission of the comma to achieve that effect.  */
10139         switch (i & -(ins.intel_syntax && dp))
10140           {
10141           case 2:
10142             if (dp->op[2].rtn == OP_Rounding && !intel_swap_2_3)
10143               needcomma = 0;
10144             break;
10145           case 3:
10146             if (dp->op[3].rtn == OP_Rounding || intel_swap_2_3)
10147               needcomma = 0;
10148             break;
10149           }
10150         if (needcomma)
10151           i386_dis_printf (&ins, dis_style_text, ",");
10152         if (ins.op_index[i] != -1 && !ins.op_riprel[i])
10153           {
10154             bfd_vma target = (bfd_vma) ins.op_address[ins.op_index[i]];
10155
10156             if (ins.op_is_jump)
10157               {
10158                 info->insn_info_valid = 1;
10159                 info->branch_delay_insns = 0;
10160                 info->data_size = 0;
10161                 info->target = target;
10162                 info->target2 = 0;
10163               }
10164             (*info->print_address_func) (target, info);
10165           }
10166         else
10167           i386_dis_printf (&ins, dis_style_text, "%s", op_txt[i]);
10168         needcomma = 1;
10169       }
10170
10171   for (i = 0; i < MAX_OPERANDS; i++)
10172     if (ins.op_index[i] != -1 && ins.op_riprel[i])
10173       {
10174         i386_dis_printf (&ins, dis_style_comment_start, "        # ");
10175         (*info->print_address_func)
10176           ((bfd_vma)(ins.start_pc + (ins.codep - ins.start_codep)
10177                      + ins.op_address[ins.op_index[i]]),
10178           info);
10179         break;
10180       }
10181   return ins.codep - priv.the_buffer;
10182 }
10183
10184 /* Here for backwards compatibility.  When gdb stops using
10185    print_insn_i386_att and print_insn_i386_intel these functions can
10186    disappear, and print_insn_i386 be merged into print_insn.  */
10187 int
10188 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
10189 {
10190   return print_insn (pc, info, 0);
10191 }
10192
10193 int
10194 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
10195 {
10196   return print_insn (pc, info, 1);
10197 }
10198
10199 int
10200 print_insn_i386 (bfd_vma pc, disassemble_info *info)
10201 {
10202   return print_insn (pc, info, -1);
10203 }
10204
10205 static const char *float_mem[] = {
10206   /* d8 */
10207   "fadd{s|}",
10208   "fmul{s|}",
10209   "fcom{s|}",
10210   "fcomp{s|}",
10211   "fsub{s|}",
10212   "fsubr{s|}",
10213   "fdiv{s|}",
10214   "fdivr{s|}",
10215   /* d9 */
10216   "fld{s|}",
10217   "(bad)",
10218   "fst{s|}",
10219   "fstp{s|}",
10220   "fldenv{C|C}",
10221   "fldcw",
10222   "fNstenv{C|C}",
10223   "fNstcw",
10224   /* da */
10225   "fiadd{l|}",
10226   "fimul{l|}",
10227   "ficom{l|}",
10228   "ficomp{l|}",
10229   "fisub{l|}",
10230   "fisubr{l|}",
10231   "fidiv{l|}",
10232   "fidivr{l|}",
10233   /* db */
10234   "fild{l|}",
10235   "fisttp{l|}",
10236   "fist{l|}",
10237   "fistp{l|}",
10238   "(bad)",
10239   "fld{t|}",
10240   "(bad)",
10241   "fstp{t|}",
10242   /* dc */
10243   "fadd{l|}",
10244   "fmul{l|}",
10245   "fcom{l|}",
10246   "fcomp{l|}",
10247   "fsub{l|}",
10248   "fsubr{l|}",
10249   "fdiv{l|}",
10250   "fdivr{l|}",
10251   /* dd */
10252   "fld{l|}",
10253   "fisttp{ll|}",
10254   "fst{l||}",
10255   "fstp{l|}",
10256   "frstor{C|C}",
10257   "(bad)",
10258   "fNsave{C|C}",
10259   "fNstsw",
10260   /* de */
10261   "fiadd{s|}",
10262   "fimul{s|}",
10263   "ficom{s|}",
10264   "ficomp{s|}",
10265   "fisub{s|}",
10266   "fisubr{s|}",
10267   "fidiv{s|}",
10268   "fidivr{s|}",
10269   /* df */
10270   "fild{s|}",
10271   "fisttp{s|}",
10272   "fist{s|}",
10273   "fistp{s|}",
10274   "fbld",
10275   "fild{ll|}",
10276   "fbstp",
10277   "fistp{ll|}",
10278 };
10279
10280 static const unsigned char float_mem_mode[] = {
10281   /* d8 */
10282   d_mode,
10283   d_mode,
10284   d_mode,
10285   d_mode,
10286   d_mode,
10287   d_mode,
10288   d_mode,
10289   d_mode,
10290   /* d9 */
10291   d_mode,
10292   0,
10293   d_mode,
10294   d_mode,
10295   0,
10296   w_mode,
10297   0,
10298   w_mode,
10299   /* da */
10300   d_mode,
10301   d_mode,
10302   d_mode,
10303   d_mode,
10304   d_mode,
10305   d_mode,
10306   d_mode,
10307   d_mode,
10308   /* db */
10309   d_mode,
10310   d_mode,
10311   d_mode,
10312   d_mode,
10313   0,
10314   t_mode,
10315   0,
10316   t_mode,
10317   /* dc */
10318   q_mode,
10319   q_mode,
10320   q_mode,
10321   q_mode,
10322   q_mode,
10323   q_mode,
10324   q_mode,
10325   q_mode,
10326   /* dd */
10327   q_mode,
10328   q_mode,
10329   q_mode,
10330   q_mode,
10331   0,
10332   0,
10333   0,
10334   w_mode,
10335   /* de */
10336   w_mode,
10337   w_mode,
10338   w_mode,
10339   w_mode,
10340   w_mode,
10341   w_mode,
10342   w_mode,
10343   w_mode,
10344   /* df */
10345   w_mode,
10346   w_mode,
10347   w_mode,
10348   w_mode,
10349   t_mode,
10350   q_mode,
10351   t_mode,
10352   q_mode
10353 };
10354
10355 #define ST { OP_ST, 0 }
10356 #define STi { OP_STi, 0 }
10357
10358 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
10359 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
10360 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
10361 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
10362 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
10363 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
10364 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
10365 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
10366 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
10367
10368 static const struct dis386 float_reg[][8] = {
10369   /* d8 */
10370   {
10371     { "fadd",   { ST, STi }, 0 },
10372     { "fmul",   { ST, STi }, 0 },
10373     { "fcom",   { STi }, 0 },
10374     { "fcomp",  { STi }, 0 },
10375     { "fsub",   { ST, STi }, 0 },
10376     { "fsubr",  { ST, STi }, 0 },
10377     { "fdiv",   { ST, STi }, 0 },
10378     { "fdivr",  { ST, STi }, 0 },
10379   },
10380   /* d9 */
10381   {
10382     { "fld",    { STi }, 0 },
10383     { "fxch",   { STi }, 0 },
10384     { FGRPd9_2 },
10385     { Bad_Opcode },
10386     { FGRPd9_4 },
10387     { FGRPd9_5 },
10388     { FGRPd9_6 },
10389     { FGRPd9_7 },
10390   },
10391   /* da */
10392   {
10393     { "fcmovb", { ST, STi }, 0 },
10394     { "fcmove", { ST, STi }, 0 },
10395     { "fcmovbe",{ ST, STi }, 0 },
10396     { "fcmovu", { ST, STi }, 0 },
10397     { Bad_Opcode },
10398     { FGRPda_5 },
10399     { Bad_Opcode },
10400     { Bad_Opcode },
10401   },
10402   /* db */
10403   {
10404     { "fcmovnb",{ ST, STi }, 0 },
10405     { "fcmovne",{ ST, STi }, 0 },
10406     { "fcmovnbe",{ ST, STi }, 0 },
10407     { "fcmovnu",{ ST, STi }, 0 },
10408     { FGRPdb_4 },
10409     { "fucomi", { ST, STi }, 0 },
10410     { "fcomi",  { ST, STi }, 0 },
10411     { Bad_Opcode },
10412   },
10413   /* dc */
10414   {
10415     { "fadd",   { STi, ST }, 0 },
10416     { "fmul",   { STi, ST }, 0 },
10417     { Bad_Opcode },
10418     { Bad_Opcode },
10419     { "fsub{!M|r}",     { STi, ST }, 0 },
10420     { "fsub{M|}",       { STi, ST }, 0 },
10421     { "fdiv{!M|r}",     { STi, ST }, 0 },
10422     { "fdiv{M|}",       { STi, ST }, 0 },
10423   },
10424   /* dd */
10425   {
10426     { "ffree",  { STi }, 0 },
10427     { Bad_Opcode },
10428     { "fst",    { STi }, 0 },
10429     { "fstp",   { STi }, 0 },
10430     { "fucom",  { STi }, 0 },
10431     { "fucomp", { STi }, 0 },
10432     { Bad_Opcode },
10433     { Bad_Opcode },
10434   },
10435   /* de */
10436   {
10437     { "faddp",  { STi, ST }, 0 },
10438     { "fmulp",  { STi, ST }, 0 },
10439     { Bad_Opcode },
10440     { FGRPde_3 },
10441     { "fsub{!M|r}p",    { STi, ST }, 0 },
10442     { "fsub{M|}p",      { STi, ST }, 0 },
10443     { "fdiv{!M|r}p",    { STi, ST }, 0 },
10444     { "fdiv{M|}p",      { STi, ST }, 0 },
10445   },
10446   /* df */
10447   {
10448     { "ffreep", { STi }, 0 },
10449     { Bad_Opcode },
10450     { Bad_Opcode },
10451     { Bad_Opcode },
10452     { FGRPdf_4 },
10453     { "fucomip", { ST, STi }, 0 },
10454     { "fcomip", { ST, STi }, 0 },
10455     { Bad_Opcode },
10456   },
10457 };
10458
10459 static const char *const fgrps[][8] = {
10460   /* Bad opcode 0 */
10461   {
10462     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10463   },
10464
10465   /* d9_2  1 */
10466   {
10467     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10468   },
10469
10470   /* d9_4  2 */
10471   {
10472     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
10473   },
10474
10475   /* d9_5  3 */
10476   {
10477     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
10478   },
10479
10480   /* d9_6  4 */
10481   {
10482     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
10483   },
10484
10485   /* d9_7  5 */
10486   {
10487     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
10488   },
10489
10490   /* da_5  6 */
10491   {
10492     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10493   },
10494
10495   /* db_4  7 */
10496   {
10497     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
10498     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
10499   },
10500
10501   /* de_3  8 */
10502   {
10503     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10504   },
10505
10506   /* df_4  9 */
10507   {
10508     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10509   },
10510 };
10511
10512 static void
10513 swap_operand (instr_info *ins)
10514 {
10515   ins->mnemonicendp[0] = '.';
10516   ins->mnemonicendp[1] = 's';
10517   ins->mnemonicendp[2] = '\0';
10518   ins->mnemonicendp += 2;
10519 }
10520
10521 static void
10522 OP_Skip_MODRM (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
10523                int sizeflag ATTRIBUTE_UNUSED)
10524 {
10525   /* Skip mod/rm byte.  */
10526   MODRM_CHECK;
10527   ins->codep++;
10528 }
10529
10530 static void
10531 dofloat (instr_info *ins, int sizeflag)
10532 {
10533   const struct dis386 *dp;
10534   unsigned char floatop;
10535
10536   floatop = ins->codep[-1];
10537
10538   if (ins->modrm.mod != 3)
10539     {
10540       int fp_indx = (floatop - 0xd8) * 8 + ins->modrm.reg;
10541
10542       putop (ins, float_mem[fp_indx], sizeflag);
10543       ins->obufp = ins->op_out[0];
10544       ins->op_ad = 2;
10545       OP_E (ins, float_mem_mode[fp_indx], sizeflag);
10546       return;
10547     }
10548   /* Skip mod/rm byte.  */
10549   MODRM_CHECK;
10550   ins->codep++;
10551
10552   dp = &float_reg[floatop - 0xd8][ins->modrm.reg];
10553   if (dp->name == NULL)
10554     {
10555       putop (ins, fgrps[dp->op[0].bytemode][ins->modrm.rm], sizeflag);
10556
10557       /* Instruction fnstsw is only one with strange arg.  */
10558       if (floatop == 0xdf && ins->codep[-1] == 0xe0)
10559         strcpy (ins->op_out[0], att_names16[0] + ins->intel_syntax);
10560     }
10561   else
10562     {
10563       putop (ins, dp->name, sizeflag);
10564
10565       ins->obufp = ins->op_out[0];
10566       ins->op_ad = 2;
10567       if (dp->op[0].rtn)
10568         (*dp->op[0].rtn) (ins, dp->op[0].bytemode, sizeflag);
10569
10570       ins->obufp = ins->op_out[1];
10571       ins->op_ad = 1;
10572       if (dp->op[1].rtn)
10573         (*dp->op[1].rtn) (ins, dp->op[1].bytemode, sizeflag);
10574     }
10575 }
10576
10577 static void
10578 OP_ST (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
10579        int sizeflag ATTRIBUTE_UNUSED)
10580 {
10581   oappend_register (ins, "%st");
10582 }
10583
10584 static void
10585 OP_STi (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
10586         int sizeflag ATTRIBUTE_UNUSED)
10587 {
10588   char scratch[8];
10589   int res = snprintf (scratch, ARRAY_SIZE (scratch), "%%st(%d)", ins->modrm.rm);
10590
10591   if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
10592     abort ();
10593   oappend_register (ins, scratch);
10594 }
10595
10596 /* Capital letters in template are macros.  */
10597 static int
10598 putop (instr_info *ins, const char *in_template, int sizeflag)
10599 {
10600   const char *p;
10601   int alt = 0;
10602   int cond = 1;
10603   unsigned int l = 0, len = 0;
10604   char last[4];
10605
10606   for (p = in_template; *p; p++)
10607     {
10608       if (len > l)
10609         {
10610           if (l >= sizeof (last) || !ISUPPER (*p))
10611             abort ();
10612           last[l++] = *p;
10613           continue;
10614         }
10615       switch (*p)
10616         {
10617         default:
10618           *ins->obufp++ = *p;
10619           break;
10620         case '%':
10621           len++;
10622           break;
10623         case '!':
10624           cond = 0;
10625           break;
10626         case '{':
10627           if (ins->intel_syntax)
10628             {
10629               while (*++p != '|')
10630                 if (*p == '}' || *p == '\0')
10631                   abort ();
10632               alt = 1;
10633             }
10634           break;
10635         case '|':
10636           while (*++p != '}')
10637             {
10638               if (*p == '\0')
10639                 abort ();
10640             }
10641           break;
10642         case '}':
10643           alt = 0;
10644           break;
10645         case 'A':
10646           if (ins->intel_syntax)
10647             break;
10648           if ((ins->need_modrm && ins->modrm.mod != 3)
10649               || (sizeflag & SUFFIX_ALWAYS))
10650             *ins->obufp++ = 'b';
10651           break;
10652         case 'B':
10653           if (l == 0)
10654             {
10655             case_B:
10656               if (ins->intel_syntax)
10657                 break;
10658               if (sizeflag & SUFFIX_ALWAYS)
10659                 *ins->obufp++ = 'b';
10660             }
10661           else if (l == 1 && last[0] == 'L')
10662             {
10663               if (ins->address_mode == mode_64bit
10664                   && !(ins->prefixes & PREFIX_ADDR))
10665                 {
10666                   *ins->obufp++ = 'a';
10667                   *ins->obufp++ = 'b';
10668                   *ins->obufp++ = 's';
10669                 }
10670
10671               goto case_B;
10672             }
10673           else
10674             abort ();
10675           break;
10676         case 'C':
10677           if (ins->intel_syntax && !alt)
10678             break;
10679           if ((ins->prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10680             {
10681               if (sizeflag & DFLAG)
10682                 *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10683               else
10684                 *ins->obufp++ = ins->intel_syntax ? 'w' : 's';
10685               ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10686             }
10687           break;
10688         case 'D':
10689           if (l == 1)
10690             {
10691               switch (last[0])
10692               {
10693               case 'X':
10694                 if (!ins->vex.evex || ins->vex.w)
10695                   *ins->obufp++ = 'd';
10696                 else
10697                   oappend (ins, "{bad}");
10698                 break;
10699               default:
10700                 abort ();
10701               }
10702               break;
10703             }
10704           if (l)
10705             abort ();
10706           if (ins->intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
10707             break;
10708           USED_REX (REX_W);
10709           if (ins->modrm.mod == 3)
10710             {
10711               if (ins->rex & REX_W)
10712                 *ins->obufp++ = 'q';
10713               else
10714                 {
10715                   if (sizeflag & DFLAG)
10716                     *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10717                   else
10718                     *ins->obufp++ = 'w';
10719                   ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10720                 }
10721             }
10722           else
10723             *ins->obufp++ = 'w';
10724           break;
10725         case 'E':
10726           if (l == 1)
10727             {
10728               switch (last[0])
10729                 {
10730                 case 'X':
10731                   if (!ins->vex.evex || ins->vex.b || ins->vex.ll >= 2
10732                       || !ins->vex.r
10733                       || (ins->modrm.mod == 3 && (ins->rex & REX_X))
10734                       || !ins->vex.v || ins->vex.mask_register_specifier)
10735                     break;
10736                   /* AVX512 extends a number of V*D insns to also have V*Q variants,
10737                      merely distinguished by EVEX.W.  Look for a use of the
10738                      respective macro.  */
10739                   if (ins->vex.w)
10740                     {
10741                       const char *pct = strchr (p + 1, '%');
10742
10743                       if (pct != NULL && pct[1] == 'D' && pct[2] == 'Q')
10744                         break;
10745                     }
10746                   *ins->obufp++ = '{';
10747                   *ins->obufp++ = 'e';
10748                   *ins->obufp++ = 'v';
10749                   *ins->obufp++ = 'e';
10750                   *ins->obufp++ = 'x';
10751                   *ins->obufp++ = '}';
10752                   *ins->obufp++ = ' ';
10753                   break;
10754                 default:
10755                   abort ();
10756                 }
10757                 break;
10758             }
10759           /* For jcxz/jecxz */
10760           if (ins->address_mode == mode_64bit)
10761             {
10762               if (sizeflag & AFLAG)
10763                 *ins->obufp++ = 'r';
10764               else
10765                 *ins->obufp++ = 'e';
10766             }
10767           else
10768             if (sizeflag & AFLAG)
10769               *ins->obufp++ = 'e';
10770           ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR);
10771           break;
10772         case 'F':
10773           if (ins->intel_syntax)
10774             break;
10775           if ((ins->prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
10776             {
10777               if (sizeflag & AFLAG)
10778                 *ins->obufp++ = ins->address_mode == mode_64bit ? 'q' : 'l';
10779               else
10780                 *ins->obufp++ = ins->address_mode == mode_64bit ? 'l' : 'w';
10781               ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR);
10782             }
10783           break;
10784         case 'G':
10785           if (ins->intel_syntax || (ins->obufp[-1] != 's'
10786                                     && !(sizeflag & SUFFIX_ALWAYS)))
10787             break;
10788           if ((ins->rex & REX_W) || (sizeflag & DFLAG))
10789             *ins->obufp++ = 'l';
10790           else
10791             *ins->obufp++ = 'w';
10792           if (!(ins->rex & REX_W))
10793             ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10794           break;
10795         case 'H':
10796           if (l == 0)
10797             {
10798               if (ins->intel_syntax)
10799                 break;
10800               if ((ins->prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
10801                   || (ins->prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
10802                 {
10803                   ins->used_prefixes |= ins->prefixes & (PREFIX_CS | PREFIX_DS);
10804                   *ins->obufp++ = ',';
10805                   *ins->obufp++ = 'p';
10806
10807                   /* Set active_seg_prefix even if not set in 64-bit mode
10808                      because here it is a valid branch hint. */
10809                   if (ins->prefixes & PREFIX_DS)
10810                     {
10811                       ins->active_seg_prefix = PREFIX_DS;
10812                       *ins->obufp++ = 't';
10813                     }
10814                   else
10815                     {
10816                       ins->active_seg_prefix = PREFIX_CS;
10817                       *ins->obufp++ = 'n';
10818                     }
10819                 }
10820             }
10821           else if (l == 1 && last[0] == 'X')
10822             {
10823               if (!ins->vex.w)
10824                 *ins->obufp++ = 'h';
10825               else
10826                 oappend (ins, "{bad}");
10827             }
10828           else
10829             abort ();
10830           break;
10831         case 'K':
10832           USED_REX (REX_W);
10833           if (ins->rex & REX_W)
10834             *ins->obufp++ = 'q';
10835           else
10836             *ins->obufp++ = 'd';
10837           break;
10838         case 'L':
10839           abort ();
10840         case 'M':
10841           if (ins->intel_mnemonic != cond)
10842             *ins->obufp++ = 'r';
10843           break;
10844         case 'N':
10845           if ((ins->prefixes & PREFIX_FWAIT) == 0)
10846             *ins->obufp++ = 'n';
10847           else
10848             ins->used_prefixes |= PREFIX_FWAIT;
10849           break;
10850         case 'O':
10851           USED_REX (REX_W);
10852           if (ins->rex & REX_W)
10853             *ins->obufp++ = 'o';
10854           else if (ins->intel_syntax && (sizeflag & DFLAG))
10855             *ins->obufp++ = 'q';
10856           else
10857             *ins->obufp++ = 'd';
10858           if (!(ins->rex & REX_W))
10859             ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10860           break;
10861         case '@':
10862           if (ins->address_mode == mode_64bit
10863               && (ins->isa64 == intel64 || (ins->rex & REX_W)
10864                   || !(ins->prefixes & PREFIX_DATA)))
10865             {
10866               if (sizeflag & SUFFIX_ALWAYS)
10867                 *ins->obufp++ = 'q';
10868               break;
10869             }
10870           /* Fall through.  */
10871         case 'P':
10872           if (l == 0)
10873             {
10874               if ((ins->modrm.mod == 3 || !cond)
10875                   && !(sizeflag & SUFFIX_ALWAYS))
10876                 break;
10877           /* Fall through.  */
10878         case 'T':
10879               if ((!(ins->rex & REX_W) && (ins->prefixes & PREFIX_DATA))
10880                   || ((sizeflag & SUFFIX_ALWAYS)
10881                       && ins->address_mode != mode_64bit))
10882                 {
10883                   *ins->obufp++ = (sizeflag & DFLAG)
10884                                   ? ins->intel_syntax ? 'd' : 'l' : 'w';
10885                   ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10886                 }
10887               else if (sizeflag & SUFFIX_ALWAYS)
10888                 *ins->obufp++ = 'q';
10889             }
10890           else if (l == 1 && last[0] == 'L')
10891             {
10892               if ((ins->prefixes & PREFIX_DATA)
10893                   || (ins->rex & REX_W)
10894                   || (sizeflag & SUFFIX_ALWAYS))
10895                 {
10896                   USED_REX (REX_W);
10897                   if (ins->rex & REX_W)
10898                     *ins->obufp++ = 'q';
10899                   else
10900                     {
10901                       if (sizeflag & DFLAG)
10902                         *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10903                       else
10904                         *ins->obufp++ = 'w';
10905                       ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10906                     }
10907                 }
10908             }
10909           else
10910             abort ();
10911           break;
10912         case 'Q':
10913           if (l == 0)
10914             {
10915               if (ins->intel_syntax && !alt)
10916                 break;
10917               USED_REX (REX_W);
10918               if ((ins->need_modrm && ins->modrm.mod != 3)
10919                   || (sizeflag & SUFFIX_ALWAYS))
10920                 {
10921                   if (ins->rex & REX_W)
10922                     *ins->obufp++ = 'q';
10923                   else
10924                     {
10925                       if (sizeflag & DFLAG)
10926                         *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10927                       else
10928                         *ins->obufp++ = 'w';
10929                       ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10930                     }
10931                 }
10932             }
10933           else if (l == 1 && last[0] == 'D')
10934             *ins->obufp++ = ins->vex.w ? 'q' : 'd';
10935           else if (l == 1 && last[0] == 'L')
10936             {
10937               if (cond ? ins->modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)
10938                        : ins->address_mode != mode_64bit)
10939                 break;
10940               if ((ins->rex & REX_W))
10941                 {
10942                   USED_REX (REX_W);
10943                   *ins->obufp++ = 'q';
10944                 }
10945               else if ((ins->address_mode == mode_64bit && cond)
10946                       || (sizeflag & SUFFIX_ALWAYS))
10947                 *ins->obufp++ = ins->intel_syntax? 'd' : 'l';
10948             }
10949           else
10950             abort ();
10951           break;
10952         case 'R':
10953           USED_REX (REX_W);
10954           if (ins->rex & REX_W)
10955             *ins->obufp++ = 'q';
10956           else if (sizeflag & DFLAG)
10957             {
10958               if (ins->intel_syntax)
10959                   *ins->obufp++ = 'd';
10960               else
10961                   *ins->obufp++ = 'l';
10962             }
10963           else
10964             *ins->obufp++ = 'w';
10965           if (ins->intel_syntax && !p[1]
10966               && ((ins->rex & REX_W) || (sizeflag & DFLAG)))
10967             *ins->obufp++ = 'e';
10968           if (!(ins->rex & REX_W))
10969             ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10970           break;
10971         case 'S':
10972           if (l == 0)
10973             {
10974             case_S:
10975               if (ins->intel_syntax)
10976                 break;
10977               if (sizeflag & SUFFIX_ALWAYS)
10978                 {
10979                   if (ins->rex & REX_W)
10980                     *ins->obufp++ = 'q';
10981                   else
10982                     {
10983                       if (sizeflag & DFLAG)
10984                         *ins->obufp++ = 'l';
10985                       else
10986                         *ins->obufp++ = 'w';
10987                       ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10988                     }
10989                 }
10990               break;
10991             }
10992           if (l != 1)
10993             abort ();
10994           switch (last[0])
10995             {
10996             case 'L':
10997               if (ins->address_mode == mode_64bit
10998                   && !(ins->prefixes & PREFIX_ADDR))
10999                 {
11000                   *ins->obufp++ = 'a';
11001                   *ins->obufp++ = 'b';
11002                   *ins->obufp++ = 's';
11003                 }
11004
11005               goto case_S;
11006             case 'X':
11007               if (!ins->vex.evex || !ins->vex.w)
11008                 *ins->obufp++ = 's';
11009               else
11010                 oappend (ins, "{bad}");
11011               break;
11012             default:
11013               abort ();
11014             }
11015           break;
11016         case 'V':
11017           if (l == 0)
11018             abort ();
11019           else if (l == 1)
11020             {
11021               switch (last[0])
11022                 {
11023                 case 'X':
11024                   if (ins->vex.evex)
11025                     break;
11026                   *ins->obufp++ = '{';
11027                   *ins->obufp++ = 'v';
11028                   *ins->obufp++ = 'e';
11029                   *ins->obufp++ = 'x';
11030                   *ins->obufp++ = '}';
11031                   *ins->obufp++ = ' ';
11032                   break;
11033                 case 'L':
11034                   if (!(ins->rex & REX_W))
11035                     break;
11036                   *ins->obufp++ = 'a';
11037                   *ins->obufp++ = 'b';
11038                   *ins->obufp++ = 's';
11039                   break;
11040                 default:
11041                   abort ();
11042                 }
11043             }
11044           else
11045             abort ();
11046           goto case_S;
11047         case 'W':
11048           if (l == 0)
11049             {
11050               /* operand size flag for cwtl, cbtw */
11051               USED_REX (REX_W);
11052               if (ins->rex & REX_W)
11053                 {
11054                   if (ins->intel_syntax)
11055                     *ins->obufp++ = 'd';
11056                   else
11057                     *ins->obufp++ = 'l';
11058                 }
11059               else if (sizeflag & DFLAG)
11060                 *ins->obufp++ = 'w';
11061               else
11062                 *ins->obufp++ = 'b';
11063               if (!(ins->rex & REX_W))
11064                 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11065             }
11066           else if (l == 1)
11067             {
11068               if (!ins->need_vex)
11069                 abort ();
11070               if (last[0] == 'X')
11071                 *ins->obufp++ = ins->vex.w ? 'd': 's';
11072               else if (last[0] == 'B')
11073                 *ins->obufp++ = ins->vex.w ? 'w': 'b';
11074               else
11075                 abort ();
11076             }
11077           else
11078             abort ();
11079           break;
11080         case 'X':
11081           if (l != 0)
11082             abort ();
11083           if (ins->need_vex
11084               ? ins->vex.prefix == DATA_PREFIX_OPCODE
11085               : ins->prefixes & PREFIX_DATA)
11086             {
11087               *ins->obufp++ = 'd';
11088               ins->used_prefixes |= PREFIX_DATA;
11089             }
11090           else
11091             *ins->obufp++ = 's';
11092           break;
11093         case 'Y':
11094           if (l == 1 && last[0] == 'X')
11095             {
11096               if (!ins->need_vex)
11097                 abort ();
11098               if (ins->intel_syntax
11099                   || ((ins->modrm.mod == 3 || ins->vex.b)
11100                       && !(sizeflag & SUFFIX_ALWAYS)))
11101                 break;
11102               switch (ins->vex.length)
11103                 {
11104                 case 128:
11105                   *ins->obufp++ = 'x';
11106                   break;
11107                 case 256:
11108                   *ins->obufp++ = 'y';
11109                   break;
11110                 case 512:
11111                   if (!ins->vex.evex)
11112                 default:
11113                     abort ();
11114                 }
11115             }
11116           else
11117             abort ();
11118           break;
11119         case 'Z':
11120           if (l == 0)
11121             {
11122               /* These insns ignore ModR/M.mod: Force it to 3 for OP_E().  */
11123               ins->modrm.mod = 3;
11124               if (!ins->intel_syntax && (sizeflag & SUFFIX_ALWAYS))
11125                 *ins->obufp++ = ins->address_mode == mode_64bit ? 'q' : 'l';
11126             }
11127           else if (l == 1 && last[0] == 'X')
11128             {
11129               if (!ins->vex.evex)
11130                 abort ();
11131               if (ins->intel_syntax
11132                   || ((ins->modrm.mod == 3 || ins->vex.b)
11133                       && !(sizeflag & SUFFIX_ALWAYS)))
11134                 break;
11135               switch (ins->vex.length)
11136                 {
11137                 case 128:
11138                   *ins->obufp++ = 'x';
11139                   break;
11140                 case 256:
11141                   *ins->obufp++ = 'y';
11142                   break;
11143                 case 512:
11144                   *ins->obufp++ = 'z';
11145                   break;
11146                 default:
11147                   abort ();
11148                 }
11149             }
11150           else
11151             abort ();
11152           break;
11153         case '^':
11154           if (ins->intel_syntax)
11155             break;
11156           if (ins->isa64 == intel64 && (ins->rex & REX_W))
11157             {
11158               USED_REX (REX_W);
11159               *ins->obufp++ = 'q';
11160               break;
11161             }
11162           if ((ins->prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
11163             {
11164               if (sizeflag & DFLAG)
11165                 *ins->obufp++ = 'l';
11166               else
11167                 *ins->obufp++ = 'w';
11168               ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11169             }
11170           break;
11171         }
11172
11173       if (len == l)
11174         len = l = 0;
11175     }
11176   *ins->obufp = 0;
11177   ins->mnemonicendp = ins->obufp;
11178   return 0;
11179 }
11180
11181 /* Add a style marker to *INS->obufp that encodes STYLE.  This assumes that
11182    the buffer pointed to by INS->obufp has space.  A style marker is made
11183    from the STYLE_MARKER_CHAR followed by STYLE converted to a single hex
11184    digit, followed by another STYLE_MARKER_CHAR.  This function assumes
11185    that the number of styles is not greater than 16.  */
11186
11187 static void
11188 oappend_insert_style (instr_info *ins, enum disassembler_style style)
11189 {
11190   unsigned num = (unsigned) style;
11191
11192   /* We currently assume that STYLE can be encoded as a single hex
11193      character.  If more styles are added then this might start to fail,
11194      and we'll need to expand this code.  */
11195   if (num > 0xf)
11196     abort ();
11197
11198   *ins->obufp++ = STYLE_MARKER_CHAR;
11199   *ins->obufp++ = (num < 10 ? ('0' + num)
11200                    : ((num < 16) ? ('a' + (num - 10)) : '0'));
11201   *ins->obufp++ = STYLE_MARKER_CHAR;
11202
11203   /* This final null character is not strictly necessary, after inserting a
11204      style marker we should always be inserting some additional content.
11205      However, having the buffer null terminated doesn't cost much, and make
11206      it easier to debug what's going on.  Also, if we do ever forget to add
11207      any additional content after this style marker, then the buffer will
11208      still be well formed.  */
11209   *ins->obufp = '\0';
11210 }
11211
11212 static void
11213 oappend_with_style (instr_info *ins, const char *s,
11214                     enum disassembler_style style)
11215 {
11216   oappend_insert_style (ins, style);
11217   ins->obufp = stpcpy (ins->obufp, s);
11218 }
11219
11220 /* Like oappend_with_style but always with text style.  */
11221
11222 static void
11223 oappend (instr_info *ins, const char *s)
11224 {
11225   oappend_with_style (ins, s, dis_style_text);
11226 }
11227
11228 /* Add a single character C to the buffer pointer to by INS->obufp, marking
11229    the style for the character as STYLE.  */
11230
11231 static void
11232 oappend_char_with_style (instr_info *ins, const char c,
11233                          enum disassembler_style style)
11234 {
11235   oappend_insert_style (ins, style);
11236   *ins->obufp++ = c;
11237   *ins->obufp = '\0';
11238 }
11239
11240 /* Like oappend_char_with_style, but always uses dis_style_text.  */
11241
11242 static void
11243 oappend_char (instr_info *ins, const char c)
11244 {
11245   oappend_char_with_style (ins, c, dis_style_text);
11246 }
11247
11248 static void
11249 append_seg (instr_info *ins)
11250 {
11251   /* Only print the active segment register.  */
11252   if (!ins->active_seg_prefix)
11253     return;
11254
11255   ins->used_prefixes |= ins->active_seg_prefix;
11256   switch (ins->active_seg_prefix)
11257     {
11258     case PREFIX_CS:
11259       oappend_register (ins, "%cs");
11260       break;
11261     case PREFIX_DS:
11262       oappend_register (ins, "%ds");
11263       break;
11264     case PREFIX_SS:
11265       oappend_register (ins, "%ss");
11266       break;
11267     case PREFIX_ES:
11268       oappend_register (ins, "%es");
11269       break;
11270     case PREFIX_FS:
11271       oappend_register (ins, "%fs");
11272       break;
11273     case PREFIX_GS:
11274       oappend_register (ins, "%gs");
11275       break;
11276     default:
11277       break;
11278     }
11279   oappend_char (ins, ':');
11280 }
11281
11282 static void
11283 OP_indirE (instr_info *ins, int bytemode, int sizeflag)
11284 {
11285   if (!ins->intel_syntax)
11286     oappend (ins, "*");
11287   OP_E (ins, bytemode, sizeflag);
11288 }
11289
11290 static void
11291 print_operand_value (instr_info *ins, bfd_vma disp,
11292                      enum disassembler_style style)
11293 {
11294   char tmp[30];
11295
11296   if (ins->address_mode == mode_64bit)
11297     sprintf (tmp, "0x%" PRIx64, (uint64_t) disp);
11298   else
11299     sprintf (tmp, "0x%x", (unsigned int) disp);
11300   oappend_with_style (ins, tmp, style);
11301 }
11302
11303 /* Like oappend, but called for immediate operands.  */
11304
11305 static void
11306 oappend_immediate (instr_info *ins, bfd_vma imm)
11307 {
11308   if (!ins->intel_syntax)
11309     oappend_char_with_style (ins, '$', dis_style_immediate);
11310   print_operand_value (ins, imm, dis_style_immediate);
11311 }
11312
11313 /* Put DISP in BUF as signed hex number.  */
11314
11315 static void
11316 print_displacement (instr_info *ins, bfd_vma disp)
11317 {
11318   bfd_signed_vma val = disp;
11319   char tmp[30];
11320
11321   if (val < 0)
11322     {
11323       oappend_char_with_style (ins, '-', dis_style_address_offset);
11324       val = -disp;
11325
11326       /* Check for possible overflow.  */
11327       if (val < 0)
11328         {
11329           switch (ins->address_mode)
11330             {
11331             case mode_64bit:
11332               oappend_with_style (ins, "0x8000000000000000",
11333                                   dis_style_address_offset);
11334               break;
11335             case mode_32bit:
11336               oappend_with_style (ins, "0x80000000",
11337                                   dis_style_address_offset);
11338               break;
11339             case mode_16bit:
11340               oappend_with_style (ins, "0x8000",
11341                                   dis_style_address_offset);
11342               break;
11343             }
11344           return;
11345         }
11346     }
11347
11348   sprintf (tmp, "0x%" PRIx64, (int64_t) val);
11349   oappend_with_style (ins, tmp, dis_style_address_offset);
11350 }
11351
11352 static void
11353 intel_operand_size (instr_info *ins, int bytemode, int sizeflag)
11354 {
11355   if (ins->vex.b)
11356     {
11357       if (!ins->vex.no_broadcast)
11358         switch (bytemode)
11359           {
11360           case x_mode:
11361           case evex_half_bcst_xmmq_mode:
11362             if (ins->vex.w)
11363               oappend (ins, "QWORD BCST ");
11364             else
11365               oappend (ins, "DWORD BCST ");
11366             break;
11367           case xh_mode:
11368           case evex_half_bcst_xmmqh_mode:
11369           case evex_half_bcst_xmmqdh_mode:
11370             oappend (ins, "WORD BCST ");
11371             break;
11372           default:
11373             ins->vex.no_broadcast = true;
11374             break;
11375           }
11376       return;
11377     }
11378   switch (bytemode)
11379     {
11380     case b_mode:
11381     case b_swap_mode:
11382     case db_mode:
11383       oappend (ins, "BYTE PTR ");
11384       break;
11385     case w_mode:
11386     case w_swap_mode:
11387     case dw_mode:
11388       oappend (ins, "WORD PTR ");
11389       break;
11390     case indir_v_mode:
11391       if (ins->address_mode == mode_64bit && ins->isa64 == intel64)
11392         {
11393           oappend (ins, "QWORD PTR ");
11394           break;
11395         }
11396       /* Fall through.  */
11397     case stack_v_mode:
11398       if (ins->address_mode == mode_64bit && ((sizeflag & DFLAG)
11399                                               || (ins->rex & REX_W)))
11400         {
11401           oappend (ins, "QWORD PTR ");
11402           break;
11403         }
11404       /* Fall through.  */
11405     case v_mode:
11406     case v_swap_mode:
11407     case dq_mode:
11408       USED_REX (REX_W);
11409       if (ins->rex & REX_W)
11410         oappend (ins, "QWORD PTR ");
11411       else if (bytemode == dq_mode)
11412         oappend (ins, "DWORD PTR ");
11413       else
11414         {
11415           if (sizeflag & DFLAG)
11416             oappend (ins, "DWORD PTR ");
11417           else
11418             oappend (ins, "WORD PTR ");
11419           ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11420         }
11421       break;
11422     case z_mode:
11423       if ((ins->rex & REX_W) || (sizeflag & DFLAG))
11424         *ins->obufp++ = 'D';
11425       oappend (ins, "WORD PTR ");
11426       if (!(ins->rex & REX_W))
11427         ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11428       break;
11429     case a_mode:
11430       if (sizeflag & DFLAG)
11431         oappend (ins, "QWORD PTR ");
11432       else
11433         oappend (ins, "DWORD PTR ");
11434       ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11435       break;
11436     case movsxd_mode:
11437       if (!(sizeflag & DFLAG) && ins->isa64 == intel64)
11438         oappend (ins, "WORD PTR ");
11439       else
11440         oappend (ins, "DWORD PTR ");
11441       ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11442       break;
11443     case d_mode:
11444     case d_swap_mode:
11445       oappend (ins, "DWORD PTR ");
11446       break;
11447     case q_mode:
11448     case q_swap_mode:
11449       oappend (ins, "QWORD PTR ");
11450       break;
11451     case m_mode:
11452       if (ins->address_mode == mode_64bit)
11453         oappend (ins, "QWORD PTR ");
11454       else
11455         oappend (ins, "DWORD PTR ");
11456       break;
11457     case f_mode:
11458       if (sizeflag & DFLAG)
11459         oappend (ins, "FWORD PTR ");
11460       else
11461         oappend (ins, "DWORD PTR ");
11462       ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11463       break;
11464     case t_mode:
11465       oappend (ins, "TBYTE PTR ");
11466       break;
11467     case x_mode:
11468     case xh_mode:
11469     case x_swap_mode:
11470     case evex_x_gscat_mode:
11471     case evex_x_nobcst_mode:
11472     case bw_unit_mode:
11473       if (ins->need_vex)
11474         {
11475           switch (ins->vex.length)
11476             {
11477             case 128:
11478               oappend (ins, "XMMWORD PTR ");
11479               break;
11480             case 256:
11481               oappend (ins, "YMMWORD PTR ");
11482               break;
11483             case 512:
11484               oappend (ins, "ZMMWORD PTR ");
11485               break;
11486             default:
11487               abort ();
11488             }
11489         }
11490       else
11491         oappend (ins, "XMMWORD PTR ");
11492       break;
11493     case xmm_mode:
11494       oappend (ins, "XMMWORD PTR ");
11495       break;
11496     case ymm_mode:
11497       oappend (ins, "YMMWORD PTR ");
11498       break;
11499     case xmmq_mode:
11500     case evex_half_bcst_xmmqh_mode:
11501     case evex_half_bcst_xmmq_mode:
11502       if (!ins->need_vex)
11503         abort ();
11504
11505       switch (ins->vex.length)
11506         {
11507         case 128:
11508           oappend (ins, "QWORD PTR ");
11509           break;
11510         case 256:
11511           oappend (ins, "XMMWORD PTR ");
11512           break;
11513         case 512:
11514           oappend (ins, "YMMWORD PTR ");
11515           break;
11516         default:
11517           abort ();
11518         }
11519       break;
11520     case xmmdw_mode:
11521       if (!ins->need_vex)
11522         abort ();
11523
11524       switch (ins->vex.length)
11525         {
11526         case 128:
11527           oappend (ins, "WORD PTR ");
11528           break;
11529         case 256:
11530           oappend (ins, "DWORD PTR ");
11531           break;
11532         case 512:
11533           oappend (ins, "QWORD PTR ");
11534           break;
11535         default:
11536           abort ();
11537         }
11538       break;
11539     case xmmqd_mode:
11540     case evex_half_bcst_xmmqdh_mode:
11541       if (!ins->need_vex)
11542         abort ();
11543
11544       switch (ins->vex.length)
11545         {
11546         case 128:
11547           oappend (ins, "DWORD PTR ");
11548           break;
11549         case 256:
11550           oappend (ins, "QWORD PTR ");
11551           break;
11552         case 512:
11553           oappend (ins, "XMMWORD PTR ");
11554           break;
11555         default:
11556           abort ();
11557         }
11558       break;
11559     case ymmq_mode:
11560       if (!ins->need_vex)
11561         abort ();
11562
11563       switch (ins->vex.length)
11564         {
11565         case 128:
11566           oappend (ins, "QWORD PTR ");
11567           break;
11568         case 256:
11569           oappend (ins, "YMMWORD PTR ");
11570           break;
11571         case 512:
11572           oappend (ins, "ZMMWORD PTR ");
11573           break;
11574         default:
11575           abort ();
11576         }
11577       break;
11578     case o_mode:
11579       oappend (ins, "OWORD PTR ");
11580       break;
11581     case vex_vsib_d_w_dq_mode:
11582     case vex_vsib_q_w_dq_mode:
11583       if (!ins->need_vex)
11584         abort ();
11585       if (ins->vex.w)
11586         oappend (ins, "QWORD PTR ");
11587       else
11588         oappend (ins, "DWORD PTR ");
11589       break;
11590     case mask_bd_mode:
11591       if (!ins->need_vex || ins->vex.length != 128)
11592         abort ();
11593       if (ins->vex.w)
11594         oappend (ins, "DWORD PTR ");
11595       else
11596         oappend (ins, "BYTE PTR ");
11597       break;
11598     case mask_mode:
11599       if (!ins->need_vex)
11600         abort ();
11601       if (ins->vex.w)
11602         oappend (ins, "QWORD PTR ");
11603       else
11604         oappend (ins, "WORD PTR ");
11605       break;
11606     case v_bnd_mode:
11607     case v_bndmk_mode:
11608     default:
11609       break;
11610     }
11611 }
11612
11613 static void
11614 print_register (instr_info *ins, unsigned int reg, unsigned int rexmask,
11615                 int bytemode, int sizeflag)
11616 {
11617   const char *const *names;
11618
11619   USED_REX (rexmask);
11620   if (ins->rex & rexmask)
11621     reg += 8;
11622
11623   switch (bytemode)
11624     {
11625     case b_mode:
11626     case b_swap_mode:
11627       if (reg & 4)
11628         USED_REX (0);
11629       if (ins->rex)
11630         names = att_names8rex;
11631       else
11632         names = att_names8;
11633       break;
11634     case w_mode:
11635       names = att_names16;
11636       break;
11637     case d_mode:
11638     case dw_mode:
11639     case db_mode:
11640       names = att_names32;
11641       break;
11642     case q_mode:
11643       names = att_names64;
11644       break;
11645     case m_mode:
11646     case v_bnd_mode:
11647       names = ins->address_mode == mode_64bit ? att_names64 : att_names32;
11648       break;
11649     case bnd_mode:
11650     case bnd_swap_mode:
11651       if (reg > 0x3)
11652         {
11653           oappend (ins, "(bad)");
11654           return;
11655         }
11656       names = att_names_bnd;
11657       break;
11658     case indir_v_mode:
11659       if (ins->address_mode == mode_64bit && ins->isa64 == intel64)
11660         {
11661           names = att_names64;
11662           break;
11663         }
11664       /* Fall through.  */
11665     case stack_v_mode:
11666       if (ins->address_mode == mode_64bit && ((sizeflag & DFLAG)
11667                                               || (ins->rex & REX_W)))
11668         {
11669           names = att_names64;
11670           break;
11671         }
11672       bytemode = v_mode;
11673       /* Fall through.  */
11674     case v_mode:
11675     case v_swap_mode:
11676     case dq_mode:
11677       USED_REX (REX_W);
11678       if (ins->rex & REX_W)
11679         names = att_names64;
11680       else if (bytemode != v_mode && bytemode != v_swap_mode)
11681         names = att_names32;
11682       else
11683         {
11684           if (sizeflag & DFLAG)
11685             names = att_names32;
11686           else
11687             names = att_names16;
11688           ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11689         }
11690       break;
11691     case movsxd_mode:
11692       if (!(sizeflag & DFLAG) && ins->isa64 == intel64)
11693         names = att_names16;
11694       else
11695         names = att_names32;
11696       ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11697       break;
11698     case va_mode:
11699       names = (ins->address_mode == mode_64bit
11700                ? att_names64 : att_names32);
11701       if (!(ins->prefixes & PREFIX_ADDR))
11702         names = (ins->address_mode == mode_16bit
11703                      ? att_names16 : names);
11704       else
11705         {
11706           /* Remove "addr16/addr32".  */
11707           ins->all_prefixes[ins->last_addr_prefix] = 0;
11708           names = (ins->address_mode != mode_32bit
11709                        ? att_names32 : att_names16);
11710           ins->used_prefixes |= PREFIX_ADDR;
11711         }
11712       break;
11713     case mask_bd_mode:
11714     case mask_mode:
11715       if (reg > 0x7)
11716         {
11717           oappend (ins, "(bad)");
11718           return;
11719         }
11720       names = att_names_mask;
11721       break;
11722     case 0:
11723       return;
11724     default:
11725       oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
11726       return;
11727     }
11728   oappend_register (ins, names[reg]);
11729 }
11730
11731 static void
11732 OP_E_memory (instr_info *ins, int bytemode, int sizeflag)
11733 {
11734   bfd_vma disp = 0;
11735   int add = (ins->rex & REX_B) ? 8 : 0;
11736   int riprel = 0;
11737   int shift;
11738
11739   if (ins->vex.evex)
11740     {
11741       switch (bytemode)
11742         {
11743         case dw_mode:
11744         case w_mode:
11745         case w_swap_mode:
11746           shift = 1;
11747           break;
11748         case db_mode:
11749         case b_mode:
11750           shift = 0;
11751           break;
11752         case dq_mode:
11753           if (ins->address_mode != mode_64bit)
11754             {
11755         case d_mode:
11756         case d_swap_mode:
11757               shift = 2;
11758               break;
11759             }
11760             /* fall through */
11761         case vex_vsib_d_w_dq_mode:
11762         case vex_vsib_q_w_dq_mode:
11763         case evex_x_gscat_mode:
11764           shift = ins->vex.w ? 3 : 2;
11765           break;
11766         case xh_mode:
11767         case evex_half_bcst_xmmqh_mode:
11768         case evex_half_bcst_xmmqdh_mode:
11769           if (ins->vex.b)
11770             {
11771               shift = ins->vex.w ? 2 : 1;
11772               break;
11773             }
11774           /* Fall through.  */
11775         case x_mode:
11776         case evex_half_bcst_xmmq_mode:
11777           if (ins->vex.b)
11778             {
11779               shift = ins->vex.w ? 3 : 2;
11780               break;
11781             }
11782           /* Fall through.  */
11783         case xmmqd_mode:
11784         case xmmdw_mode:
11785         case xmmq_mode:
11786         case ymmq_mode:
11787         case evex_x_nobcst_mode:
11788         case x_swap_mode:
11789           switch (ins->vex.length)
11790             {
11791             case 128:
11792               shift = 4;
11793               break;
11794             case 256:
11795               shift = 5;
11796               break;
11797             case 512:
11798               shift = 6;
11799               break;
11800             default:
11801               abort ();
11802             }
11803           /* Make necessary corrections to shift for modes that need it.  */
11804           if (bytemode == xmmq_mode
11805               || bytemode == evex_half_bcst_xmmqh_mode
11806               || bytemode == evex_half_bcst_xmmq_mode
11807               || (bytemode == ymmq_mode && ins->vex.length == 128))
11808             shift -= 1;
11809           else if (bytemode == xmmqd_mode
11810                    || bytemode == evex_half_bcst_xmmqdh_mode)
11811             shift -= 2;
11812           else if (bytemode == xmmdw_mode)
11813             shift -= 3;
11814           break;
11815         case ymm_mode:
11816           shift = 5;
11817           break;
11818         case xmm_mode:
11819           shift = 4;
11820           break;
11821         case q_mode:
11822         case q_swap_mode:
11823           shift = 3;
11824           break;
11825         case bw_unit_mode:
11826           shift = ins->vex.w ? 1 : 0;
11827           break;
11828         default:
11829           abort ();
11830         }
11831     }
11832   else
11833     shift = 0;
11834
11835   USED_REX (REX_B);
11836   if (ins->intel_syntax)
11837     intel_operand_size (ins, bytemode, sizeflag);
11838   append_seg (ins);
11839
11840   if ((sizeflag & AFLAG) || ins->address_mode == mode_64bit)
11841     {
11842       /* 32/64 bit address mode */
11843       int havedisp;
11844       int havebase;
11845       int needindex;
11846       int needaddr32;
11847       int base, rbase;
11848       int vindex = 0;
11849       int scale = 0;
11850       int addr32flag = !((sizeflag & AFLAG)
11851                          || bytemode == v_bnd_mode
11852                          || bytemode == v_bndmk_mode
11853                          || bytemode == bnd_mode
11854                          || bytemode == bnd_swap_mode);
11855       bool check_gather = false;
11856       const char *const *indexes = NULL;
11857
11858       havebase = 1;
11859       base = ins->modrm.rm;
11860
11861       if (base == 4)
11862         {
11863           vindex = ins->sib.index;
11864           USED_REX (REX_X);
11865           if (ins->rex & REX_X)
11866             vindex += 8;
11867           switch (bytemode)
11868             {
11869             case vex_vsib_d_w_dq_mode:
11870             case vex_vsib_q_w_dq_mode:
11871               if (!ins->need_vex)
11872                 abort ();
11873               if (ins->vex.evex)
11874                 {
11875                   if (!ins->vex.v)
11876                     vindex += 16;
11877                   check_gather = ins->obufp == ins->op_out[1];
11878                 }
11879
11880               switch (ins->vex.length)
11881                 {
11882                 case 128:
11883                   indexes = att_names_xmm;
11884                   break;
11885                 case 256:
11886                   if (!ins->vex.w
11887                       || bytemode == vex_vsib_q_w_dq_mode)
11888                     indexes = att_names_ymm;
11889                   else
11890                     indexes = att_names_xmm;
11891                   break;
11892                 case 512:
11893                   if (!ins->vex.w
11894                       || bytemode == vex_vsib_q_w_dq_mode)
11895                     indexes = att_names_zmm;
11896                   else
11897                     indexes = att_names_ymm;
11898                   break;
11899                 default:
11900                   abort ();
11901                 }
11902               break;
11903             default:
11904               if (vindex != 4)
11905                 indexes = ins->address_mode == mode_64bit && !addr32flag
11906                           ? att_names64 : att_names32;
11907               break;
11908             }
11909           scale = ins->sib.scale;
11910           base = ins->sib.base;
11911           ins->codep++;
11912         }
11913       else
11914         {
11915           /* Check for mandatory SIB.  */
11916           if (bytemode == vex_vsib_d_w_dq_mode
11917               || bytemode == vex_vsib_q_w_dq_mode
11918               || bytemode == vex_sibmem_mode)
11919             {
11920               oappend (ins, "(bad)");
11921               return;
11922             }
11923         }
11924       rbase = base + add;
11925
11926       switch (ins->modrm.mod)
11927         {
11928         case 0:
11929           if (base == 5)
11930             {
11931               havebase = 0;
11932               if (ins->address_mode == mode_64bit && !ins->has_sib)
11933                 riprel = 1;
11934               disp = get32s (ins);
11935               if (riprel && bytemode == v_bndmk_mode)
11936                 {
11937                   oappend (ins, "(bad)");
11938                   return;
11939                 }
11940             }
11941           break;
11942         case 1:
11943           FETCH_DATA (ins->info, ins->codep + 1);
11944           disp = *ins->codep++;
11945           if ((disp & 0x80) != 0)
11946             disp -= 0x100;
11947           if (ins->vex.evex && shift > 0)
11948             disp <<= shift;
11949           break;
11950         case 2:
11951           disp = get32s (ins);
11952           break;
11953         }
11954
11955       needindex = 0;
11956       needaddr32 = 0;
11957       if (ins->has_sib
11958           && !havebase
11959           && !indexes
11960           && ins->address_mode != mode_16bit)
11961         {
11962           if (ins->address_mode == mode_64bit)
11963             {
11964               if (addr32flag)
11965                 {
11966                   /* Without base nor index registers, zero-extend the
11967                      lower 32-bit displacement to 64 bits.  */
11968                   disp = (unsigned int) disp;
11969                   needindex = 1;
11970                 }
11971               needaddr32 = 1;
11972             }
11973           else
11974             {
11975               /* In 32-bit mode, we need index register to tell [offset]
11976                  from [eiz*1 + offset].  */
11977               needindex = 1;
11978             }
11979         }
11980
11981       havedisp = (havebase
11982                   || needindex
11983                   || (ins->has_sib && (indexes || scale != 0)));
11984
11985       if (!ins->intel_syntax)
11986         if (ins->modrm.mod != 0 || base == 5)
11987           {
11988             if (havedisp || riprel)
11989               print_displacement (ins, disp);
11990             else
11991               print_operand_value (ins, disp, dis_style_address_offset);
11992             if (riprel)
11993               {
11994                 set_op (ins, disp, true);
11995                 oappend_char (ins, '(');
11996                 oappend_with_style (ins, !addr32flag ? "%rip" : "%eip",
11997                                     dis_style_register);
11998                 oappend_char (ins, ')');
11999               }
12000           }
12001
12002       if ((havebase || indexes || needindex || needaddr32 || riprel)
12003           && (ins->address_mode != mode_64bit
12004               || ((bytemode != v_bnd_mode)
12005                   && (bytemode != v_bndmk_mode)
12006                   && (bytemode != bnd_mode)
12007                   && (bytemode != bnd_swap_mode))))
12008         ins->used_prefixes |= PREFIX_ADDR;
12009
12010       if (havedisp || (ins->intel_syntax && riprel))
12011         {
12012           oappend_char (ins, ins->open_char);
12013           if (ins->intel_syntax && riprel)
12014             {
12015               set_op (ins, disp, true);
12016               oappend_with_style (ins, !addr32flag ? "rip" : "eip",
12017                                   dis_style_register);
12018             }
12019           if (havebase)
12020             oappend_register
12021               (ins,
12022                (ins->address_mode == mode_64bit && !addr32flag
12023                 ? att_names64 : att_names32)[rbase]);
12024           if (ins->has_sib)
12025             {
12026               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
12027                  print index to tell base + index from base.  */
12028               if (scale != 0
12029                   || needindex
12030                   || indexes
12031                   || (havebase && base != ESP_REG_NUM))
12032                 {
12033                   if (!ins->intel_syntax || havebase)
12034                     oappend_char (ins, ins->separator_char);
12035                   if (indexes)
12036                     {
12037                       if (ins->address_mode == mode_64bit || vindex < 16)
12038                         oappend_register (ins, indexes[vindex]);
12039                       else
12040                         oappend (ins, "(bad)");
12041                     }
12042                   else
12043                     oappend_register (ins,
12044                                       ins->address_mode == mode_64bit
12045                                       && !addr32flag
12046                                       ? att_index64
12047                                       : att_index32);
12048
12049                   oappend_char (ins, ins->scale_char);
12050                   oappend_char_with_style (ins, '0' + (1 << scale),
12051                                            dis_style_immediate);
12052                 }
12053             }
12054           if (ins->intel_syntax
12055               && (disp || ins->modrm.mod != 0 || base == 5))
12056             {
12057               if (!havedisp || (bfd_signed_vma) disp >= 0)
12058                   oappend_char (ins, '+');
12059               else if (ins->modrm.mod != 1 && disp != -disp)
12060                 {
12061                   oappend_char (ins, '-');
12062                   disp = -disp;
12063                 }
12064
12065               if (havedisp)
12066                 print_displacement (ins, disp);
12067               else
12068                 print_operand_value (ins, disp, dis_style_address_offset);
12069             }
12070
12071           oappend_char (ins, ins->close_char);
12072
12073           if (check_gather)
12074             {
12075               /* Both XMM/YMM/ZMM registers must be distinct.  */
12076               int modrm_reg = ins->modrm.reg;
12077
12078               if (ins->rex & REX_R)
12079                 modrm_reg += 8;
12080               if (!ins->vex.r)
12081                 modrm_reg += 16;
12082               if (vindex == modrm_reg)
12083                 oappend (ins, "/(bad)");
12084             }
12085         }
12086       else if (ins->intel_syntax)
12087         {
12088           if (ins->modrm.mod != 0 || base == 5)
12089             {
12090               if (!ins->active_seg_prefix)
12091                 {
12092                   oappend_register (ins, att_names_seg[ds_reg - es_reg]);
12093                   oappend (ins, ":");
12094                 }
12095               print_operand_value (ins, disp, dis_style_text);
12096             }
12097         }
12098     }
12099   else if (bytemode == v_bnd_mode
12100            || bytemode == v_bndmk_mode
12101            || bytemode == bnd_mode
12102            || bytemode == bnd_swap_mode
12103            || bytemode == vex_vsib_d_w_dq_mode
12104            || bytemode == vex_vsib_q_w_dq_mode)
12105     {
12106       oappend (ins, "(bad)");
12107       return;
12108     }
12109   else
12110     {
12111       /* 16 bit address mode */
12112       ins->used_prefixes |= ins->prefixes & PREFIX_ADDR;
12113       switch (ins->modrm.mod)
12114         {
12115         case 0:
12116           if (ins->modrm.rm == 6)
12117             {
12118               disp = get16 (ins);
12119               if ((disp & 0x8000) != 0)
12120                 disp -= 0x10000;
12121             }
12122           break;
12123         case 1:
12124           FETCH_DATA (ins->info, ins->codep + 1);
12125           disp = *ins->codep++;
12126           if ((disp & 0x80) != 0)
12127             disp -= 0x100;
12128           if (ins->vex.evex && shift > 0)
12129             disp <<= shift;
12130           break;
12131         case 2:
12132           disp = get16 (ins);
12133           if ((disp & 0x8000) != 0)
12134             disp -= 0x10000;
12135           break;
12136         }
12137
12138       if (!ins->intel_syntax)
12139         if (ins->modrm.mod != 0 || ins->modrm.rm == 6)
12140           print_displacement (ins, disp);
12141
12142       if (ins->modrm.mod != 0 || ins->modrm.rm != 6)
12143         {
12144           oappend_char (ins, ins->open_char);
12145           oappend (ins, (ins->intel_syntax ? intel_index16
12146                          : att_index16)[ins->modrm.rm]);
12147           if (ins->intel_syntax
12148               && (disp || ins->modrm.mod != 0 || ins->modrm.rm == 6))
12149             {
12150               if ((bfd_signed_vma) disp >= 0)
12151                 oappend_char (ins, '+');
12152               else if (ins->modrm.mod != 1)
12153                 {
12154                   oappend_char (ins, '-');
12155                   disp = -disp;
12156                 }
12157
12158               print_displacement (ins, disp);
12159             }
12160
12161           oappend_char (ins, ins->close_char);
12162         }
12163       else if (ins->intel_syntax)
12164         {
12165           if (!ins->active_seg_prefix)
12166             {
12167               oappend_register (ins, att_names_seg[ds_reg - es_reg]);
12168               oappend (ins, ":");
12169             }
12170           print_operand_value (ins, disp & 0xffff, dis_style_text);
12171         }
12172     }
12173   if (ins->vex.b)
12174     {
12175       ins->evex_used |= EVEX_b_used;
12176
12177       /* Broadcast can only ever be valid for memory sources.  */
12178       if (ins->obufp == ins->op_out[0])
12179         ins->vex.no_broadcast = true;
12180
12181       if (!ins->vex.no_broadcast
12182           && (!ins->intel_syntax || !(ins->evex_used & EVEX_len_used)))
12183         {
12184           if (bytemode == xh_mode)
12185             {
12186               if (ins->vex.w)
12187                 oappend (ins, "{bad}");
12188               else
12189                 {
12190                   switch (ins->vex.length)
12191                     {
12192                     case 128:
12193                       oappend (ins, "{1to8}");
12194                       break;
12195                     case 256:
12196                       oappend (ins, "{1to16}");
12197                       break;
12198                     case 512:
12199                       oappend (ins, "{1to32}");
12200                       break;
12201                     default:
12202                       abort ();
12203                     }
12204                 }
12205             }
12206           else if (bytemode == q_mode
12207                    || bytemode == ymmq_mode)
12208             ins->vex.no_broadcast = true;
12209           else if (ins->vex.w
12210                    || bytemode == evex_half_bcst_xmmqdh_mode
12211                    || bytemode == evex_half_bcst_xmmq_mode)
12212             {
12213               switch (ins->vex.length)
12214                 {
12215                 case 128:
12216                   oappend (ins, "{1to2}");
12217                   break;
12218                 case 256:
12219                   oappend (ins, "{1to4}");
12220                   break;
12221                 case 512:
12222                   oappend (ins, "{1to8}");
12223                   break;
12224                 default:
12225                   abort ();
12226                 }
12227             }
12228           else if (bytemode == x_mode
12229                    || bytemode == evex_half_bcst_xmmqh_mode)
12230             {
12231               switch (ins->vex.length)
12232                 {
12233                 case 128:
12234                   oappend (ins, "{1to4}");
12235                   break;
12236                 case 256:
12237                   oappend (ins, "{1to8}");
12238                   break;
12239                 case 512:
12240                   oappend (ins, "{1to16}");
12241                   break;
12242                 default:
12243                   abort ();
12244                 }
12245             }
12246           else
12247             ins->vex.no_broadcast = true;
12248         }
12249       if (ins->vex.no_broadcast)
12250         oappend (ins, "{bad}");
12251     }
12252 }
12253
12254 static void
12255 OP_E (instr_info *ins, int bytemode, int sizeflag)
12256 {
12257   /* Skip mod/rm byte.  */
12258   MODRM_CHECK;
12259   ins->codep++;
12260
12261   if (ins->modrm.mod == 3)
12262     {
12263       if ((sizeflag & SUFFIX_ALWAYS)
12264           && (bytemode == b_swap_mode
12265               || bytemode == bnd_swap_mode
12266               || bytemode == v_swap_mode))
12267         swap_operand (ins);
12268
12269       print_register (ins, ins->modrm.rm, REX_B, bytemode, sizeflag);
12270     }
12271   else
12272     OP_E_memory (ins, bytemode, sizeflag);
12273 }
12274
12275 static void
12276 OP_G (instr_info *ins, int bytemode, int sizeflag)
12277 {
12278   if (ins->vex.evex && !ins->vex.r && ins->address_mode == mode_64bit)
12279     {
12280       oappend (ins, "(bad)");
12281       return;
12282     }
12283
12284   print_register (ins, ins->modrm.reg, REX_R, bytemode, sizeflag);
12285 }
12286
12287 #ifdef BFD64
12288 static bfd_vma
12289 get64 (instr_info *ins)
12290 {
12291   bfd_vma x;
12292   unsigned int a;
12293   unsigned int b;
12294
12295   FETCH_DATA (ins->info, ins->codep + 8);
12296   a = *ins->codep++ & 0xff;
12297   a |= (*ins->codep++ & 0xff) << 8;
12298   a |= (*ins->codep++ & 0xff) << 16;
12299   a |= (*ins->codep++ & 0xffu) << 24;
12300   b = *ins->codep++ & 0xff;
12301   b |= (*ins->codep++ & 0xff) << 8;
12302   b |= (*ins->codep++ & 0xff) << 16;
12303   b |= (*ins->codep++ & 0xffu) << 24;
12304   x = a + ((bfd_vma) b << 32);
12305   return x;
12306 }
12307 #else
12308 static bfd_vma
12309 get64 (instr_info *ins ATTRIBUTE_UNUSED)
12310 {
12311   abort ();
12312   return 0;
12313 }
12314 #endif
12315
12316 static bfd_signed_vma
12317 get32 (instr_info *ins)
12318 {
12319   bfd_vma x = 0;
12320
12321   FETCH_DATA (ins->info, ins->codep + 4);
12322   x = *ins->codep++ & (bfd_vma) 0xff;
12323   x |= (*ins->codep++ & (bfd_vma) 0xff) << 8;
12324   x |= (*ins->codep++ & (bfd_vma) 0xff) << 16;
12325   x |= (*ins->codep++ & (bfd_vma) 0xff) << 24;
12326   return x;
12327 }
12328
12329 static bfd_signed_vma
12330 get32s (instr_info *ins)
12331 {
12332   bfd_vma x = 0;
12333
12334   FETCH_DATA (ins->info, ins->codep + 4);
12335   x = *ins->codep++ & (bfd_vma) 0xff;
12336   x |= (*ins->codep++ & (bfd_vma) 0xff) << 8;
12337   x |= (*ins->codep++ & (bfd_vma) 0xff) << 16;
12338   x |= (*ins->codep++ & (bfd_vma) 0xff) << 24;
12339
12340   x = (x ^ ((bfd_vma) 1 << 31)) - ((bfd_vma) 1 << 31);
12341
12342   return x;
12343 }
12344
12345 static int
12346 get16 (instr_info *ins)
12347 {
12348   int x = 0;
12349
12350   FETCH_DATA (ins->info, ins->codep + 2);
12351   x = *ins->codep++ & 0xff;
12352   x |= (*ins->codep++ & 0xff) << 8;
12353   return x;
12354 }
12355
12356 static void
12357 set_op (instr_info *ins, bfd_vma op, bool riprel)
12358 {
12359   ins->op_index[ins->op_ad] = ins->op_ad;
12360   if (ins->address_mode == mode_64bit)
12361     ins->op_address[ins->op_ad] = op;
12362   else /* Mask to get a 32-bit address.  */
12363     ins->op_address[ins->op_ad] = op & 0xffffffff;
12364   ins->op_riprel[ins->op_ad] = riprel;
12365 }
12366
12367 static void
12368 OP_REG (instr_info *ins, int code, int sizeflag)
12369 {
12370   const char *s;
12371   int add;
12372
12373   switch (code)
12374     {
12375     case es_reg: case ss_reg: case cs_reg:
12376     case ds_reg: case fs_reg: case gs_reg:
12377       oappend_register (ins, att_names_seg[code - es_reg]);
12378       return;
12379     }
12380
12381   USED_REX (REX_B);
12382   if (ins->rex & REX_B)
12383     add = 8;
12384   else
12385     add = 0;
12386
12387   switch (code)
12388     {
12389     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
12390     case sp_reg: case bp_reg: case si_reg: case di_reg:
12391       s = att_names16[code - ax_reg + add];
12392       break;
12393     case ah_reg: case ch_reg: case dh_reg: case bh_reg:
12394       USED_REX (0);
12395       /* Fall through.  */
12396     case al_reg: case cl_reg: case dl_reg: case bl_reg:
12397       if (ins->rex)
12398         s = att_names8rex[code - al_reg + add];
12399       else
12400         s = att_names8[code - al_reg];
12401       break;
12402     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
12403     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
12404       if (ins->address_mode == mode_64bit
12405           && ((sizeflag & DFLAG) || (ins->rex & REX_W)))
12406         {
12407           s = att_names64[code - rAX_reg + add];
12408           break;
12409         }
12410       code += eAX_reg - rAX_reg;
12411       /* Fall through.  */
12412     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
12413     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
12414       USED_REX (REX_W);
12415       if (ins->rex & REX_W)
12416         s = att_names64[code - eAX_reg + add];
12417       else
12418         {
12419           if (sizeflag & DFLAG)
12420             s = att_names32[code - eAX_reg + add];
12421           else
12422             s = att_names16[code - eAX_reg + add];
12423           ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12424         }
12425       break;
12426     default:
12427       oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12428       return;
12429     }
12430   oappend_register (ins, s);
12431 }
12432
12433 static void
12434 OP_IMREG (instr_info *ins, int code, int sizeflag)
12435 {
12436   const char *s;
12437
12438   switch (code)
12439     {
12440     case indir_dx_reg:
12441       if (!ins->intel_syntax)
12442         {
12443           oappend (ins, "(%dx)");
12444           return;
12445         }
12446       s = att_names16[dx_reg - ax_reg];
12447       break;
12448     case al_reg: case cl_reg:
12449       s = att_names8[code - al_reg];
12450       break;
12451     case eAX_reg:
12452       USED_REX (REX_W);
12453       if (ins->rex & REX_W)
12454         {
12455           s = *att_names64;
12456           break;
12457         }
12458       /* Fall through.  */
12459     case z_mode_ax_reg:
12460       if ((ins->rex & REX_W) || (sizeflag & DFLAG))
12461         s = *att_names32;
12462       else
12463         s = *att_names16;
12464       if (!(ins->rex & REX_W))
12465         ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12466       break;
12467     default:
12468       oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12469       return;
12470     }
12471   oappend_register (ins, s);
12472 }
12473
12474 static void
12475 OP_I (instr_info *ins, int bytemode, int sizeflag)
12476 {
12477   bfd_signed_vma op;
12478   bfd_signed_vma mask = -1;
12479
12480   switch (bytemode)
12481     {
12482     case b_mode:
12483       FETCH_DATA (ins->info, ins->codep + 1);
12484       op = *ins->codep++;
12485       mask = 0xff;
12486       break;
12487     case v_mode:
12488       USED_REX (REX_W);
12489       if (ins->rex & REX_W)
12490         op = get32s (ins);
12491       else
12492         {
12493           if (sizeflag & DFLAG)
12494             {
12495               op = get32 (ins);
12496               mask = 0xffffffff;
12497             }
12498           else
12499             {
12500               op = get16 (ins);
12501               mask = 0xfffff;
12502             }
12503           ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12504         }
12505       break;
12506     case d_mode:
12507       mask = 0xffffffff;
12508       op = get32 (ins);
12509       break;
12510     case w_mode:
12511       mask = 0xfffff;
12512       op = get16 (ins);
12513       break;
12514     case const_1_mode:
12515       if (ins->intel_syntax)
12516         oappend (ins, "1");
12517       return;
12518     default:
12519       oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12520       return;
12521     }
12522
12523   op &= mask;
12524   oappend_immediate (ins, op);
12525 }
12526
12527 static void
12528 OP_I64 (instr_info *ins, int bytemode, int sizeflag)
12529 {
12530   if (bytemode != v_mode || ins->address_mode != mode_64bit
12531       || !(ins->rex & REX_W))
12532     {
12533       OP_I (ins, bytemode, sizeflag);
12534       return;
12535     }
12536
12537   USED_REX (REX_W);
12538
12539   oappend_immediate (ins, get64 (ins));
12540 }
12541
12542 static void
12543 OP_sI (instr_info *ins, int bytemode, int sizeflag)
12544 {
12545   bfd_signed_vma op;
12546
12547   switch (bytemode)
12548     {
12549     case b_mode:
12550     case b_T_mode:
12551       FETCH_DATA (ins->info, ins->codep + 1);
12552       op = *ins->codep++;
12553       if ((op & 0x80) != 0)
12554         op -= 0x100;
12555       if (bytemode == b_T_mode)
12556         {
12557           if (ins->address_mode != mode_64bit
12558               || !((sizeflag & DFLAG) || (ins->rex & REX_W)))
12559             {
12560               /* The operand-size prefix is overridden by a REX prefix.  */
12561               if ((sizeflag & DFLAG) || (ins->rex & REX_W))
12562                 op &= 0xffffffff;
12563               else
12564                 op &= 0xffff;
12565           }
12566         }
12567       else
12568         {
12569           if (!(ins->rex & REX_W))
12570             {
12571               if (sizeflag & DFLAG)
12572                 op &= 0xffffffff;
12573               else
12574                 op &= 0xffff;
12575             }
12576         }
12577       break;
12578     case v_mode:
12579       /* The operand-size prefix is overridden by a REX prefix.  */
12580       if ((sizeflag & DFLAG) || (ins->rex & REX_W))
12581         op = get32s (ins);
12582       else
12583         op = get16 (ins);
12584       break;
12585     default:
12586       oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12587       return;
12588     }
12589
12590   oappend_immediate (ins, op);
12591 }
12592
12593 static void
12594 OP_J (instr_info *ins, int bytemode, int sizeflag)
12595 {
12596   bfd_vma disp;
12597   bfd_vma mask = -1;
12598   bfd_vma segment = 0;
12599
12600   switch (bytemode)
12601     {
12602     case b_mode:
12603       FETCH_DATA (ins->info, ins->codep + 1);
12604       disp = *ins->codep++;
12605       if ((disp & 0x80) != 0)
12606         disp -= 0x100;
12607       break;
12608     case v_mode:
12609     case dqw_mode:
12610       if ((sizeflag & DFLAG)
12611           || (ins->address_mode == mode_64bit
12612               && ((ins->isa64 == intel64 && bytemode != dqw_mode)
12613                   || (ins->rex & REX_W))))
12614         disp = get32s (ins);
12615       else
12616         {
12617           disp = get16 (ins);
12618           if ((disp & 0x8000) != 0)
12619             disp -= 0x10000;
12620           /* In 16bit mode, address is wrapped around at 64k within
12621              the same segment.  Otherwise, a data16 prefix on a jump
12622              instruction means that the pc is masked to 16 bits after
12623              the displacement is added!  */
12624           mask = 0xffff;
12625           if ((ins->prefixes & PREFIX_DATA) == 0)
12626             segment = ((ins->start_pc + (ins->codep - ins->start_codep))
12627                        & ~((bfd_vma) 0xffff));
12628         }
12629       if (ins->address_mode != mode_64bit
12630           || (ins->isa64 != intel64 && !(ins->rex & REX_W)))
12631         ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12632       break;
12633     default:
12634       oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12635       return;
12636     }
12637   disp = ((ins->start_pc + (ins->codep - ins->start_codep) + disp) & mask)
12638          | segment;
12639   set_op (ins, disp, false);
12640   print_operand_value (ins, disp, dis_style_text);
12641 }
12642
12643 static void
12644 OP_SEG (instr_info *ins, int bytemode, int sizeflag)
12645 {
12646   if (bytemode == w_mode)
12647     oappend_register (ins, att_names_seg[ins->modrm.reg]);
12648   else
12649     OP_E (ins, ins->modrm.mod == 3 ? bytemode : w_mode, sizeflag);
12650 }
12651
12652 static void
12653 OP_DIR (instr_info *ins, int dummy ATTRIBUTE_UNUSED, int sizeflag)
12654 {
12655   int seg, offset, res;
12656   char scratch[24];
12657
12658   if (sizeflag & DFLAG)
12659     {
12660       offset = get32 (ins);
12661       seg = get16 (ins);
12662     }
12663   else
12664     {
12665       offset = get16 (ins);
12666       seg = get16 (ins);
12667     }
12668   ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12669
12670   res = snprintf (scratch, ARRAY_SIZE (scratch),
12671                   ins->intel_syntax ? "0x%x:0x%x" : "$0x%x,$0x%x",
12672                   seg, offset);
12673   if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
12674     abort ();
12675   oappend (ins, scratch);
12676 }
12677
12678 static void
12679 OP_OFF (instr_info *ins, int bytemode, int sizeflag)
12680 {
12681   bfd_vma off;
12682
12683   if (ins->intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12684     intel_operand_size (ins, bytemode, sizeflag);
12685   append_seg (ins);
12686
12687   if ((sizeflag & AFLAG) || ins->address_mode == mode_64bit)
12688     off = get32 (ins);
12689   else
12690     off = get16 (ins);
12691
12692   if (ins->intel_syntax)
12693     {
12694       if (!ins->active_seg_prefix)
12695         {
12696           oappend_register (ins, att_names_seg[ds_reg - es_reg]);
12697           oappend (ins, ":");
12698         }
12699     }
12700   print_operand_value (ins, off, dis_style_address_offset);
12701 }
12702
12703 static void
12704 OP_OFF64 (instr_info *ins, int bytemode, int sizeflag)
12705 {
12706   bfd_vma off;
12707
12708   if (ins->address_mode != mode_64bit
12709       || (ins->prefixes & PREFIX_ADDR))
12710     {
12711       OP_OFF (ins, bytemode, sizeflag);
12712       return;
12713     }
12714
12715   if (ins->intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12716     intel_operand_size (ins, bytemode, sizeflag);
12717   append_seg (ins);
12718
12719   off = get64 (ins);
12720
12721   if (ins->intel_syntax)
12722     {
12723       if (!ins->active_seg_prefix)
12724         {
12725           oappend_register (ins, att_names_seg[ds_reg - es_reg]);
12726           oappend (ins, ":");
12727         }
12728     }
12729   print_operand_value (ins, off, dis_style_address_offset);
12730 }
12731
12732 static void
12733 ptr_reg (instr_info *ins, int code, int sizeflag)
12734 {
12735   const char *s;
12736
12737   *ins->obufp++ = ins->open_char;
12738   ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR);
12739   if (ins->address_mode == mode_64bit)
12740     {
12741       if (!(sizeflag & AFLAG))
12742         s = att_names32[code - eAX_reg];
12743       else
12744         s = att_names64[code - eAX_reg];
12745     }
12746   else if (sizeflag & AFLAG)
12747     s = att_names32[code - eAX_reg];
12748   else
12749     s = att_names16[code - eAX_reg];
12750   oappend_register (ins, s);
12751   oappend_char (ins, ins->close_char);
12752 }
12753
12754 static void
12755 OP_ESreg (instr_info *ins, int code, int sizeflag)
12756 {
12757   if (ins->intel_syntax)
12758     {
12759       switch (ins->codep[-1])
12760         {
12761         case 0x6d:      /* insw/insl */
12762           intel_operand_size (ins, z_mode, sizeflag);
12763           break;
12764         case 0xa5:      /* movsw/movsl/movsq */
12765         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
12766         case 0xab:      /* stosw/stosl */
12767         case 0xaf:      /* scasw/scasl */
12768           intel_operand_size (ins, v_mode, sizeflag);
12769           break;
12770         default:
12771           intel_operand_size (ins, b_mode, sizeflag);
12772         }
12773     }
12774   oappend_register (ins, "%es");
12775   oappend_char (ins, ':');
12776   ptr_reg (ins, code, sizeflag);
12777 }
12778
12779 static void
12780 OP_DSreg (instr_info *ins, int code, int sizeflag)
12781 {
12782   if (ins->intel_syntax)
12783     {
12784       switch (ins->codep[-1])
12785         {
12786         case 0x6f:      /* outsw/outsl */
12787           intel_operand_size (ins, z_mode, sizeflag);
12788           break;
12789         case 0xa5:      /* movsw/movsl/movsq */
12790         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
12791         case 0xad:      /* lodsw/lodsl/lodsq */
12792           intel_operand_size (ins, v_mode, sizeflag);
12793           break;
12794         default:
12795           intel_operand_size (ins, b_mode, sizeflag);
12796         }
12797     }
12798   /* Set ins->active_seg_prefix to PREFIX_DS if it is unset so that the
12799      default segment register DS is printed.  */
12800   if (!ins->active_seg_prefix)
12801     ins->active_seg_prefix = PREFIX_DS;
12802   append_seg (ins);
12803   ptr_reg (ins, code, sizeflag);
12804 }
12805
12806 static void
12807 OP_C (instr_info *ins, int dummy ATTRIBUTE_UNUSED,
12808       int sizeflag ATTRIBUTE_UNUSED)
12809 {
12810   int add, res;
12811   char scratch[8];
12812
12813   if (ins->rex & REX_R)
12814     {
12815       USED_REX (REX_R);
12816       add = 8;
12817     }
12818   else if (ins->address_mode != mode_64bit && (ins->prefixes & PREFIX_LOCK))
12819     {
12820       ins->all_prefixes[ins->last_lock_prefix] = 0;
12821       ins->used_prefixes |= PREFIX_LOCK;
12822       add = 8;
12823     }
12824   else
12825     add = 0;
12826   res = snprintf (scratch, ARRAY_SIZE (scratch), "%%cr%d",
12827                   ins->modrm.reg + add);
12828   if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
12829     abort ();
12830   oappend_register (ins, scratch);
12831 }
12832
12833 static void
12834 OP_D (instr_info *ins, int dummy ATTRIBUTE_UNUSED,
12835       int sizeflag ATTRIBUTE_UNUSED)
12836 {
12837   int add, res;
12838   char scratch[8];
12839
12840   USED_REX (REX_R);
12841   if (ins->rex & REX_R)
12842     add = 8;
12843   else
12844     add = 0;
12845   res = snprintf (scratch, ARRAY_SIZE (scratch),
12846                   ins->intel_syntax ? "dr%d" : "%%db%d",
12847                   ins->modrm.reg + add);
12848   if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
12849     abort ();
12850   oappend (ins, scratch);
12851 }
12852
12853 static void
12854 OP_T (instr_info *ins, int dummy ATTRIBUTE_UNUSED,
12855       int sizeflag ATTRIBUTE_UNUSED)
12856 {
12857   int res;
12858   char scratch[8];
12859
12860   res = snprintf (scratch, ARRAY_SIZE (scratch), "%%tr%d", ins->modrm.reg);
12861   if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
12862     abort ();
12863   oappend_register (ins, scratch);
12864 }
12865
12866 static void
12867 OP_MMX (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
12868         int sizeflag ATTRIBUTE_UNUSED)
12869 {
12870   int reg = ins->modrm.reg;
12871   const char *const *names;
12872
12873   ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12874   if (ins->prefixes & PREFIX_DATA)
12875     {
12876       names = att_names_xmm;
12877       USED_REX (REX_R);
12878       if (ins->rex & REX_R)
12879         reg += 8;
12880     }
12881   else
12882     names = att_names_mm;
12883   oappend_register (ins, names[reg]);
12884 }
12885
12886 static void
12887 print_vector_reg (instr_info *ins, unsigned int reg, int bytemode)
12888 {
12889   const char *const *names;
12890
12891   if (bytemode == xmmq_mode
12892       || bytemode == evex_half_bcst_xmmqh_mode
12893       || bytemode == evex_half_bcst_xmmq_mode)
12894     {
12895       switch (ins->vex.length)
12896         {
12897         case 128:
12898         case 256:
12899           names = att_names_xmm;
12900           break;
12901         case 512:
12902           names = att_names_ymm;
12903           ins->evex_used |= EVEX_len_used;
12904           break;
12905         default:
12906           abort ();
12907         }
12908     }
12909   else if (bytemode == ymm_mode)
12910     names = att_names_ymm;
12911   else if (bytemode == tmm_mode)
12912     {
12913       if (reg >= 8)
12914         {
12915           oappend (ins, "(bad)");
12916           return;
12917         }
12918       names = att_names_tmm;
12919     }
12920   else if (ins->need_vex
12921            && bytemode != xmm_mode
12922            && bytemode != scalar_mode
12923            && bytemode != xmmdw_mode
12924            && bytemode != xmmqd_mode
12925            && bytemode != evex_half_bcst_xmmqdh_mode
12926            && bytemode != w_swap_mode
12927            && bytemode != b_mode
12928            && bytemode != w_mode
12929            && bytemode != d_mode
12930            && bytemode != q_mode)
12931     {
12932       ins->evex_used |= EVEX_len_used;
12933       switch (ins->vex.length)
12934         {
12935         case 128:
12936           names = att_names_xmm;
12937           break;
12938         case 256:
12939           if (ins->vex.w
12940               || bytemode != vex_vsib_q_w_dq_mode)
12941             names = att_names_ymm;
12942           else
12943             names = att_names_xmm;
12944           break;
12945         case 512:
12946           if (ins->vex.w
12947               || bytemode != vex_vsib_q_w_dq_mode)
12948             names = att_names_zmm;
12949           else
12950             names = att_names_ymm;
12951           break;
12952         default:
12953           abort ();
12954         }
12955     }
12956   else
12957     names = att_names_xmm;
12958   oappend_register (ins, names[reg]);
12959 }
12960
12961 static void
12962 OP_XMM (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
12963 {
12964   unsigned int reg = ins->modrm.reg;
12965
12966   USED_REX (REX_R);
12967   if (ins->rex & REX_R)
12968     reg += 8;
12969   if (ins->vex.evex)
12970     {
12971       if (!ins->vex.r)
12972         reg += 16;
12973     }
12974
12975   if (bytemode == tmm_mode)
12976     ins->modrm.reg = reg;
12977   else if (bytemode == scalar_mode)
12978     ins->vex.no_broadcast = true;
12979
12980   print_vector_reg (ins, reg, bytemode);
12981 }
12982
12983 static void
12984 OP_EM (instr_info *ins, int bytemode, int sizeflag)
12985 {
12986   int reg;
12987   const char *const *names;
12988
12989   if (ins->modrm.mod != 3)
12990     {
12991       if (ins->intel_syntax
12992           && (bytemode == v_mode || bytemode == v_swap_mode))
12993         {
12994           bytemode = (ins->prefixes & PREFIX_DATA) ? x_mode : q_mode;
12995           ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12996         }
12997       OP_E (ins, bytemode, sizeflag);
12998       return;
12999     }
13000
13001   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
13002     swap_operand (ins);
13003
13004   /* Skip mod/rm byte.  */
13005   MODRM_CHECK;
13006   ins->codep++;
13007   ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
13008   reg = ins->modrm.rm;
13009   if (ins->prefixes & PREFIX_DATA)
13010     {
13011       names = att_names_xmm;
13012       USED_REX (REX_B);
13013       if (ins->rex & REX_B)
13014         reg += 8;
13015     }
13016   else
13017     names = att_names_mm;
13018   oappend_register (ins, names[reg]);
13019 }
13020
13021 /* cvt* are the only instructions in sse2 which have
13022    both SSE and MMX operands and also have 0x66 prefix
13023    in their opcode. 0x66 was originally used to differentiate
13024    between SSE and MMX instruction(operands). So we have to handle the
13025    cvt* separately using OP_EMC and OP_MXC */
13026 static void
13027 OP_EMC (instr_info *ins, int bytemode, int sizeflag)
13028 {
13029   if (ins->modrm.mod != 3)
13030     {
13031       if (ins->intel_syntax && bytemode == v_mode)
13032         {
13033           bytemode = (ins->prefixes & PREFIX_DATA) ? x_mode : q_mode;
13034           ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
13035         }
13036       OP_E (ins, bytemode, sizeflag);
13037       return;
13038     }
13039
13040   /* Skip mod/rm byte.  */
13041   MODRM_CHECK;
13042   ins->codep++;
13043   ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
13044   oappend_register (ins, att_names_mm[ins->modrm.rm]);
13045 }
13046
13047 static void
13048 OP_MXC (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13049         int sizeflag ATTRIBUTE_UNUSED)
13050 {
13051   ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
13052   oappend_register (ins, att_names_mm[ins->modrm.reg]);
13053 }
13054
13055 static void
13056 OP_EX (instr_info *ins, int bytemode, int sizeflag)
13057 {
13058   int reg;
13059
13060   /* Skip mod/rm byte.  */
13061   MODRM_CHECK;
13062   ins->codep++;
13063
13064   if (bytemode == dq_mode)
13065     bytemode = ins->vex.w ? q_mode : d_mode;
13066
13067   if (ins->modrm.mod != 3)
13068     {
13069       OP_E_memory (ins, bytemode, sizeflag);
13070       return;
13071     }
13072
13073   reg = ins->modrm.rm;
13074   USED_REX (REX_B);
13075   if (ins->rex & REX_B)
13076     reg += 8;
13077   if (ins->vex.evex)
13078     {
13079       USED_REX (REX_X);
13080       if ((ins->rex & REX_X))
13081         reg += 16;
13082     }
13083
13084   if ((sizeflag & SUFFIX_ALWAYS)
13085       && (bytemode == x_swap_mode
13086           || bytemode == w_swap_mode
13087           || bytemode == d_swap_mode
13088           || bytemode == q_swap_mode))
13089     swap_operand (ins);
13090
13091   if (bytemode == tmm_mode)
13092     ins->modrm.rm = reg;
13093
13094   print_vector_reg (ins, reg, bytemode);
13095 }
13096
13097 static void
13098 OP_MS (instr_info *ins, int bytemode, int sizeflag)
13099 {
13100   if (ins->modrm.mod == 3)
13101     OP_EM (ins, bytemode, sizeflag);
13102   else
13103     BadOp (ins);
13104 }
13105
13106 static void
13107 OP_XS (instr_info *ins, int bytemode, int sizeflag)
13108 {
13109   if (ins->modrm.mod == 3)
13110     OP_EX (ins, bytemode, sizeflag);
13111   else
13112     BadOp (ins);
13113 }
13114
13115 static void
13116 OP_M (instr_info *ins, int bytemode, int sizeflag)
13117 {
13118   if (ins->modrm.mod == 3)
13119     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
13120     BadOp (ins);
13121   else
13122     OP_E (ins, bytemode, sizeflag);
13123 }
13124
13125 static void
13126 OP_0f07 (instr_info *ins, int bytemode, int sizeflag)
13127 {
13128   if (ins->modrm.mod != 3 || ins->modrm.rm != 0)
13129     BadOp (ins);
13130   else
13131     OP_E (ins, bytemode, sizeflag);
13132 }
13133
13134 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
13135    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
13136
13137 static void
13138 NOP_Fixup (instr_info *ins, int opnd, int sizeflag)
13139 {
13140   if ((ins->prefixes & PREFIX_DATA) == 0 && (ins->rex & REX_B) == 0)
13141     ins->mnemonicendp = stpcpy (ins->obuf, "nop");
13142   else if (opnd == 0)
13143     OP_REG (ins, eAX_reg, sizeflag);
13144   else
13145     OP_IMREG (ins, eAX_reg, sizeflag);
13146 }
13147
13148 static const char *const Suffix3DNow[] = {
13149 /* 00 */        NULL,           NULL,           NULL,           NULL,
13150 /* 04 */        NULL,           NULL,           NULL,           NULL,
13151 /* 08 */        NULL,           NULL,           NULL,           NULL,
13152 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
13153 /* 10 */        NULL,           NULL,           NULL,           NULL,
13154 /* 14 */        NULL,           NULL,           NULL,           NULL,
13155 /* 18 */        NULL,           NULL,           NULL,           NULL,
13156 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
13157 /* 20 */        NULL,           NULL,           NULL,           NULL,
13158 /* 24 */        NULL,           NULL,           NULL,           NULL,
13159 /* 28 */        NULL,           NULL,           NULL,           NULL,
13160 /* 2C */        NULL,           NULL,           NULL,           NULL,
13161 /* 30 */        NULL,           NULL,           NULL,           NULL,
13162 /* 34 */        NULL,           NULL,           NULL,           NULL,
13163 /* 38 */        NULL,           NULL,           NULL,           NULL,
13164 /* 3C */        NULL,           NULL,           NULL,           NULL,
13165 /* 40 */        NULL,           NULL,           NULL,           NULL,
13166 /* 44 */        NULL,           NULL,           NULL,           NULL,
13167 /* 48 */        NULL,           NULL,           NULL,           NULL,
13168 /* 4C */        NULL,           NULL,           NULL,           NULL,
13169 /* 50 */        NULL,           NULL,           NULL,           NULL,
13170 /* 54 */        NULL,           NULL,           NULL,           NULL,
13171 /* 58 */        NULL,           NULL,           NULL,           NULL,
13172 /* 5C */        NULL,           NULL,           NULL,           NULL,
13173 /* 60 */        NULL,           NULL,           NULL,           NULL,
13174 /* 64 */        NULL,           NULL,           NULL,           NULL,
13175 /* 68 */        NULL,           NULL,           NULL,           NULL,
13176 /* 6C */        NULL,           NULL,           NULL,           NULL,
13177 /* 70 */        NULL,           NULL,           NULL,           NULL,
13178 /* 74 */        NULL,           NULL,           NULL,           NULL,
13179 /* 78 */        NULL,           NULL,           NULL,           NULL,
13180 /* 7C */        NULL,           NULL,           NULL,           NULL,
13181 /* 80 */        NULL,           NULL,           NULL,           NULL,
13182 /* 84 */        NULL,           NULL,           NULL,           NULL,
13183 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
13184 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
13185 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
13186 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
13187 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
13188 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
13189 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
13190 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
13191 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
13192 /* AC */        NULL,           NULL,           "pfacc",        NULL,
13193 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
13194 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
13195 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
13196 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
13197 /* C0 */        NULL,           NULL,           NULL,           NULL,
13198 /* C4 */        NULL,           NULL,           NULL,           NULL,
13199 /* C8 */        NULL,           NULL,           NULL,           NULL,
13200 /* CC */        NULL,           NULL,           NULL,           NULL,
13201 /* D0 */        NULL,           NULL,           NULL,           NULL,
13202 /* D4 */        NULL,           NULL,           NULL,           NULL,
13203 /* D8 */        NULL,           NULL,           NULL,           NULL,
13204 /* DC */        NULL,           NULL,           NULL,           NULL,
13205 /* E0 */        NULL,           NULL,           NULL,           NULL,
13206 /* E4 */        NULL,           NULL,           NULL,           NULL,
13207 /* E8 */        NULL,           NULL,           NULL,           NULL,
13208 /* EC */        NULL,           NULL,           NULL,           NULL,
13209 /* F0 */        NULL,           NULL,           NULL,           NULL,
13210 /* F4 */        NULL,           NULL,           NULL,           NULL,
13211 /* F8 */        NULL,           NULL,           NULL,           NULL,
13212 /* FC */        NULL,           NULL,           NULL,           NULL,
13213 };
13214
13215 static void
13216 OP_3DNowSuffix (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13217                 int sizeflag ATTRIBUTE_UNUSED)
13218 {
13219   const char *mnemonic;
13220
13221   FETCH_DATA (ins->info, ins->codep + 1);
13222   /* AMD 3DNow! instructions are specified by an opcode suffix in the
13223      place where an 8-bit immediate would normally go.  ie. the last
13224      byte of the instruction.  */
13225   ins->obufp = ins->mnemonicendp;
13226   mnemonic = Suffix3DNow[*ins->codep++ & 0xff];
13227   if (mnemonic)
13228     ins->obufp = stpcpy (ins->obufp, mnemonic);
13229   else
13230     {
13231       /* Since a variable sized ins->modrm/ins->sib chunk is between the start
13232          of the opcode (0x0f0f) and the opcode suffix, we need to do
13233          all the ins->modrm processing first, and don't know until now that
13234          we have a bad opcode.  This necessitates some cleaning up.  */
13235       ins->op_out[0][0] = '\0';
13236       ins->op_out[1][0] = '\0';
13237       BadOp (ins);
13238     }
13239   ins->mnemonicendp = ins->obufp;
13240 }
13241
13242 static const struct op simd_cmp_op[] =
13243 {
13244   { STRING_COMMA_LEN ("eq") },
13245   { STRING_COMMA_LEN ("lt") },
13246   { STRING_COMMA_LEN ("le") },
13247   { STRING_COMMA_LEN ("unord") },
13248   { STRING_COMMA_LEN ("neq") },
13249   { STRING_COMMA_LEN ("nlt") },
13250   { STRING_COMMA_LEN ("nle") },
13251   { STRING_COMMA_LEN ("ord") }
13252 };
13253
13254 static const struct op vex_cmp_op[] =
13255 {
13256   { STRING_COMMA_LEN ("eq_uq") },
13257   { STRING_COMMA_LEN ("nge") },
13258   { STRING_COMMA_LEN ("ngt") },
13259   { STRING_COMMA_LEN ("false") },
13260   { STRING_COMMA_LEN ("neq_oq") },
13261   { STRING_COMMA_LEN ("ge") },
13262   { STRING_COMMA_LEN ("gt") },
13263   { STRING_COMMA_LEN ("true") },
13264   { STRING_COMMA_LEN ("eq_os") },
13265   { STRING_COMMA_LEN ("lt_oq") },
13266   { STRING_COMMA_LEN ("le_oq") },
13267   { STRING_COMMA_LEN ("unord_s") },
13268   { STRING_COMMA_LEN ("neq_us") },
13269   { STRING_COMMA_LEN ("nlt_uq") },
13270   { STRING_COMMA_LEN ("nle_uq") },
13271   { STRING_COMMA_LEN ("ord_s") },
13272   { STRING_COMMA_LEN ("eq_us") },
13273   { STRING_COMMA_LEN ("nge_uq") },
13274   { STRING_COMMA_LEN ("ngt_uq") },
13275   { STRING_COMMA_LEN ("false_os") },
13276   { STRING_COMMA_LEN ("neq_os") },
13277   { STRING_COMMA_LEN ("ge_oq") },
13278   { STRING_COMMA_LEN ("gt_oq") },
13279   { STRING_COMMA_LEN ("true_us") },
13280 };
13281
13282 static void
13283 CMP_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13284            int sizeflag ATTRIBUTE_UNUSED)
13285 {
13286   unsigned int cmp_type;
13287
13288   FETCH_DATA (ins->info, ins->codep + 1);
13289   cmp_type = *ins->codep++ & 0xff;
13290   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
13291     {
13292       char suffix[3];
13293       char *p = ins->mnemonicendp - 2;
13294       suffix[0] = p[0];
13295       suffix[1] = p[1];
13296       suffix[2] = '\0';
13297       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13298       ins->mnemonicendp += simd_cmp_op[cmp_type].len;
13299     }
13300   else if (ins->need_vex
13301            && cmp_type < ARRAY_SIZE (simd_cmp_op) + ARRAY_SIZE (vex_cmp_op))
13302     {
13303       char suffix[3];
13304       char *p = ins->mnemonicendp - 2;
13305       suffix[0] = p[0];
13306       suffix[1] = p[1];
13307       suffix[2] = '\0';
13308       cmp_type -= ARRAY_SIZE (simd_cmp_op);
13309       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
13310       ins->mnemonicendp += vex_cmp_op[cmp_type].len;
13311     }
13312   else
13313     {
13314       /* We have a reserved extension byte.  Output it directly.  */
13315       oappend_immediate (ins, cmp_type);
13316     }
13317 }
13318
13319 static void
13320 OP_Mwait (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13321 {
13322   /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx  */
13323   if (!ins->intel_syntax)
13324     {
13325       strcpy (ins->op_out[0], att_names32[0] + ins->intel_syntax);
13326       strcpy (ins->op_out[1], att_names32[1] + ins->intel_syntax);
13327       if (bytemode == eBX_reg)
13328         strcpy (ins->op_out[2], att_names32[3] + ins->intel_syntax);
13329       ins->two_source_ops = true;
13330     }
13331   /* Skip mod/rm byte.  */
13332   MODRM_CHECK;
13333   ins->codep++;
13334 }
13335
13336 static void
13337 OP_Monitor (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13338             int sizeflag ATTRIBUTE_UNUSED)
13339 {
13340   /* monitor %{e,r,}ax,%ecx,%edx"  */
13341   if (!ins->intel_syntax)
13342     {
13343       const char *const *names = (ins->address_mode == mode_64bit
13344                                   ? att_names64 : att_names32);
13345
13346       if (ins->prefixes & PREFIX_ADDR)
13347         {
13348           /* Remove "addr16/addr32".  */
13349           ins->all_prefixes[ins->last_addr_prefix] = 0;
13350           names = (ins->address_mode != mode_32bit
13351                    ? att_names32 : att_names16);
13352           ins->used_prefixes |= PREFIX_ADDR;
13353         }
13354       else if (ins->address_mode == mode_16bit)
13355         names = att_names16;
13356       strcpy (ins->op_out[0], names[0] + ins->intel_syntax);
13357       strcpy (ins->op_out[1], att_names32[1] + ins->intel_syntax);
13358       strcpy (ins->op_out[2], att_names32[2] + ins->intel_syntax);
13359       ins->two_source_ops = true;
13360     }
13361   /* Skip mod/rm byte.  */
13362   MODRM_CHECK;
13363   ins->codep++;
13364 }
13365
13366 static void
13367 BadOp (instr_info *ins)
13368 {
13369   /* Throw away prefixes and 1st. opcode byte.  */
13370   ins->codep = ins->insn_codep + 1;
13371   ins->obufp = stpcpy (ins->obufp, "(bad)");
13372 }
13373
13374 static void
13375 REP_Fixup (instr_info *ins, int bytemode, int sizeflag)
13376 {
13377   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
13378      lods and stos.  */
13379   if (ins->prefixes & PREFIX_REPZ)
13380     ins->all_prefixes[ins->last_repz_prefix] = REP_PREFIX;
13381
13382   switch (bytemode)
13383     {
13384     case al_reg:
13385     case eAX_reg:
13386     case indir_dx_reg:
13387       OP_IMREG (ins, bytemode, sizeflag);
13388       break;
13389     case eDI_reg:
13390       OP_ESreg (ins, bytemode, sizeflag);
13391       break;
13392     case eSI_reg:
13393       OP_DSreg (ins, bytemode, sizeflag);
13394       break;
13395     default:
13396       abort ();
13397       break;
13398     }
13399 }
13400
13401 static void
13402 SEP_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13403            int sizeflag ATTRIBUTE_UNUSED)
13404 {
13405   if (ins->isa64 != amd64)
13406     return;
13407
13408   ins->obufp = ins->obuf;
13409   BadOp (ins);
13410   ins->mnemonicendp = ins->obufp;
13411   ++ins->codep;
13412 }
13413
13414 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
13415    "bnd".  */
13416
13417 static void
13418 BND_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13419            int sizeflag ATTRIBUTE_UNUSED)
13420 {
13421   if (ins->prefixes & PREFIX_REPNZ)
13422     ins->all_prefixes[ins->last_repnz_prefix] = BND_PREFIX;
13423 }
13424
13425 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
13426    "notrack".  */
13427
13428 static void
13429 NOTRACK_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13430                int sizeflag ATTRIBUTE_UNUSED)
13431 {
13432   /* Since active_seg_prefix is not set in 64-bit mode, check whether
13433      we've seen a PREFIX_DS.  */
13434   if ((ins->prefixes & PREFIX_DS) != 0
13435       && (ins->address_mode != mode_64bit || ins->last_data_prefix < 0))
13436     {
13437       /* NOTRACK prefix is only valid on indirect branch instructions.
13438          NB: DATA prefix is unsupported for Intel64.  */
13439       ins->active_seg_prefix = 0;
13440       ins->all_prefixes[ins->last_seg_prefix] = NOTRACK_PREFIX;
13441     }
13442 }
13443
13444 /* Similar to OP_E.  But the 0xf2/0xf3 ins->prefixes should be displayed as
13445    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
13446  */
13447
13448 static void
13449 HLE_Fixup1 (instr_info *ins, int bytemode, int sizeflag)
13450 {
13451   if (ins->modrm.mod != 3
13452       && (ins->prefixes & PREFIX_LOCK) != 0)
13453     {
13454       if (ins->prefixes & PREFIX_REPZ)
13455         ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13456       if (ins->prefixes & PREFIX_REPNZ)
13457         ins->all_prefixes[ins->last_repnz_prefix] = XACQUIRE_PREFIX;
13458     }
13459
13460   OP_E (ins, bytemode, sizeflag);
13461 }
13462
13463 /* Similar to OP_E.  But the 0xf2/0xf3 ins->prefixes should be displayed as
13464    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
13465  */
13466
13467 static void
13468 HLE_Fixup2 (instr_info *ins, int bytemode, int sizeflag)
13469 {
13470   if (ins->modrm.mod != 3)
13471     {
13472       if (ins->prefixes & PREFIX_REPZ)
13473         ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13474       if (ins->prefixes & PREFIX_REPNZ)
13475         ins->all_prefixes[ins->last_repnz_prefix] = XACQUIRE_PREFIX;
13476     }
13477
13478   OP_E (ins, bytemode, sizeflag);
13479 }
13480
13481 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
13482    "xrelease" for memory operand.  No check for LOCK prefix.   */
13483
13484 static void
13485 HLE_Fixup3 (instr_info *ins, int bytemode, int sizeflag)
13486 {
13487   if (ins->modrm.mod != 3
13488       && ins->last_repz_prefix > ins->last_repnz_prefix
13489       && (ins->prefixes & PREFIX_REPZ) != 0)
13490     ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13491
13492   OP_E (ins, bytemode, sizeflag);
13493 }
13494
13495 static void
13496 CMPXCHG8B_Fixup (instr_info *ins, int bytemode, int sizeflag)
13497 {
13498   USED_REX (REX_W);
13499   if (ins->rex & REX_W)
13500     {
13501       /* Change cmpxchg8b to cmpxchg16b.  */
13502       char *p = ins->mnemonicendp - 2;
13503       ins->mnemonicendp = stpcpy (p, "16b");
13504       bytemode = o_mode;
13505     }
13506   else if ((ins->prefixes & PREFIX_LOCK) != 0)
13507     {
13508       if (ins->prefixes & PREFIX_REPZ)
13509         ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13510       if (ins->prefixes & PREFIX_REPNZ)
13511         ins->all_prefixes[ins->last_repnz_prefix] = XACQUIRE_PREFIX;
13512     }
13513
13514   OP_M (ins, bytemode, sizeflag);
13515 }
13516
13517 static void
13518 XMM_Fixup (instr_info *ins, int reg, int sizeflag ATTRIBUTE_UNUSED)
13519 {
13520   const char *const *names = att_names_xmm;
13521
13522   if (ins->need_vex)
13523     {
13524       switch (ins->vex.length)
13525         {
13526         case 128:
13527           break;
13528         case 256:
13529           names = att_names_ymm;
13530           break;
13531         default:
13532           abort ();
13533         }
13534     }
13535   oappend_register (ins, names[reg]);
13536 }
13537
13538 static void
13539 FXSAVE_Fixup (instr_info *ins, int bytemode, int sizeflag)
13540 {
13541   /* Add proper suffix to "fxsave" and "fxrstor".  */
13542   USED_REX (REX_W);
13543   if (ins->rex & REX_W)
13544     {
13545       char *p = ins->mnemonicendp;
13546       *p++ = '6';
13547       *p++ = '4';
13548       *p = '\0';
13549       ins->mnemonicendp = p;
13550     }
13551   OP_M (ins, bytemode, sizeflag);
13552 }
13553
13554 /* Display the destination register operand for instructions with
13555    VEX. */
13556
13557 static void
13558 OP_VEX (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13559 {
13560   int reg, modrm_reg, sib_index = -1;
13561   const char *const *names;
13562
13563   if (!ins->need_vex)
13564     abort ();
13565
13566   reg = ins->vex.register_specifier;
13567   ins->vex.register_specifier = 0;
13568   if (ins->address_mode != mode_64bit)
13569     {
13570       if (ins->vex.evex && !ins->vex.v)
13571         {
13572           oappend (ins, "(bad)");
13573           return;
13574         }
13575
13576       reg &= 7;
13577     }
13578   else if (ins->vex.evex && !ins->vex.v)
13579     reg += 16;
13580
13581   switch (bytemode)
13582     {
13583     case scalar_mode:
13584       oappend_register (ins, att_names_xmm[reg]);
13585       return;
13586
13587     case vex_vsib_d_w_dq_mode:
13588     case vex_vsib_q_w_dq_mode:
13589       /* This must be the 3rd operand.  */
13590       if (ins->obufp != ins->op_out[2])
13591         abort ();
13592       if (ins->vex.length == 128
13593           || (bytemode != vex_vsib_d_w_dq_mode
13594               && !ins->vex.w))
13595         oappend_register (ins, att_names_xmm[reg]);
13596       else
13597         oappend_register (ins, att_names_ymm[reg]);
13598
13599       /* All 3 XMM/YMM registers must be distinct.  */
13600       modrm_reg = ins->modrm.reg;
13601       if (ins->rex & REX_R)
13602         modrm_reg += 8;
13603
13604       if (ins->has_sib && ins->modrm.rm == 4)
13605         {
13606           sib_index = ins->sib.index;
13607           if (ins->rex & REX_X)
13608             sib_index += 8;
13609         }
13610
13611       if (reg == modrm_reg || reg == sib_index)
13612         strcpy (ins->obufp, "/(bad)");
13613       if (modrm_reg == sib_index || modrm_reg == reg)
13614         strcat (ins->op_out[0], "/(bad)");
13615       if (sib_index == modrm_reg || sib_index == reg)
13616         strcat (ins->op_out[1], "/(bad)");
13617
13618       return;
13619
13620     case tmm_mode:
13621       /* All 3 TMM registers must be distinct.  */
13622       if (reg >= 8)
13623         oappend (ins, "(bad)");
13624       else
13625         {
13626           /* This must be the 3rd operand.  */
13627           if (ins->obufp != ins->op_out[2])
13628             abort ();
13629           oappend_register (ins, att_names_tmm[reg]);
13630           if (reg == ins->modrm.reg || reg == ins->modrm.rm)
13631             strcpy (ins->obufp, "/(bad)");
13632         }
13633
13634       if (ins->modrm.reg == ins->modrm.rm || ins->modrm.reg == reg
13635           || ins->modrm.rm == reg)
13636         {
13637           if (ins->modrm.reg <= 8
13638               && (ins->modrm.reg == ins->modrm.rm || ins->modrm.reg == reg))
13639             strcat (ins->op_out[0], "/(bad)");
13640           if (ins->modrm.rm <= 8
13641               && (ins->modrm.rm == ins->modrm.reg || ins->modrm.rm == reg))
13642             strcat (ins->op_out[1], "/(bad)");
13643         }
13644
13645       return;
13646     }
13647
13648   switch (ins->vex.length)
13649     {
13650     case 128:
13651       switch (bytemode)
13652         {
13653         case x_mode:
13654           names = att_names_xmm;
13655           ins->evex_used |= EVEX_len_used;
13656           break;
13657         case dq_mode:
13658           if (ins->rex & REX_W)
13659             names = att_names64;
13660           else
13661             names = att_names32;
13662           break;
13663         case mask_bd_mode:
13664         case mask_mode:
13665           if (reg > 0x7)
13666             {
13667               oappend (ins, "(bad)");
13668               return;
13669             }
13670           names = att_names_mask;
13671           break;
13672         default:
13673           abort ();
13674           return;
13675         }
13676       break;
13677     case 256:
13678       switch (bytemode)
13679         {
13680         case x_mode:
13681           names = att_names_ymm;
13682           ins->evex_used |= EVEX_len_used;
13683           break;
13684         case mask_bd_mode:
13685         case mask_mode:
13686           if (reg > 0x7)
13687             {
13688               oappend (ins, "(bad)");
13689               return;
13690             }
13691           names = att_names_mask;
13692           break;
13693         default:
13694           /* See PR binutils/20893 for a reproducer.  */
13695           oappend (ins, "(bad)");
13696           return;
13697         }
13698       break;
13699     case 512:
13700       names = att_names_zmm;
13701       ins->evex_used |= EVEX_len_used;
13702       break;
13703     default:
13704       abort ();
13705       break;
13706     }
13707   oappend_register (ins, names[reg]);
13708 }
13709
13710 static void
13711 OP_VexR (instr_info *ins, int bytemode, int sizeflag)
13712 {
13713   if (ins->modrm.mod == 3)
13714     OP_VEX (ins, bytemode, sizeflag);
13715 }
13716
13717 static void
13718 OP_VexW (instr_info *ins, int bytemode, int sizeflag)
13719 {
13720   OP_VEX (ins, bytemode, sizeflag);
13721
13722   if (ins->vex.w)
13723     {
13724       /* Swap 2nd and 3rd operands.  */
13725       char *tmp = ins->op_out[2];
13726
13727       ins->op_out[2] = ins->op_out[1];
13728       ins->op_out[1] = tmp;
13729     }
13730 }
13731
13732 static void
13733 OP_REG_VexI4 (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13734 {
13735   int reg;
13736   const char *const *names = att_names_xmm;
13737
13738   FETCH_DATA (ins->info, ins->codep + 1);
13739   reg = *ins->codep++;
13740
13741   if (bytemode != x_mode && bytemode != scalar_mode)
13742     abort ();
13743
13744   reg >>= 4;
13745   if (ins->address_mode != mode_64bit)
13746     reg &= 7;
13747
13748   if (bytemode == x_mode && ins->vex.length == 256)
13749     names = att_names_ymm;
13750
13751   oappend_register (ins, names[reg]);
13752
13753   if (ins->vex.w)
13754     {
13755       /* Swap 3rd and 4th operands.  */
13756       char *tmp = ins->op_out[3];
13757
13758       ins->op_out[3] = ins->op_out[2];
13759       ins->op_out[2] = tmp;
13760     }
13761 }
13762
13763 static void
13764 OP_VexI4 (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13765           int sizeflag ATTRIBUTE_UNUSED)
13766 {
13767   oappend_immediate (ins, ins->codep[-1] & 0xf);
13768 }
13769
13770 static void
13771 VPCMP_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13772              int sizeflag ATTRIBUTE_UNUSED)
13773 {
13774   unsigned int cmp_type;
13775
13776   if (!ins->vex.evex)
13777     abort ();
13778
13779   FETCH_DATA (ins->info, ins->codep + 1);
13780   cmp_type = *ins->codep++ & 0xff;
13781   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
13782      If it's the case, print suffix, otherwise - print the immediate.  */
13783   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
13784       && cmp_type != 3
13785       && cmp_type != 7)
13786     {
13787       char suffix[3];
13788       char *p = ins->mnemonicendp - 2;
13789
13790       /* vpcmp* can have both one- and two-lettered suffix.  */
13791       if (p[0] == 'p')
13792         {
13793           p++;
13794           suffix[0] = p[0];
13795           suffix[1] = '\0';
13796         }
13797       else
13798         {
13799           suffix[0] = p[0];
13800           suffix[1] = p[1];
13801           suffix[2] = '\0';
13802         }
13803
13804       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13805       ins->mnemonicendp += simd_cmp_op[cmp_type].len;
13806     }
13807   else
13808     {
13809       /* We have a reserved extension byte.  Output it directly.  */
13810       oappend_immediate (ins, cmp_type);
13811     }
13812 }
13813
13814 static const struct op xop_cmp_op[] =
13815 {
13816   { STRING_COMMA_LEN ("lt") },
13817   { STRING_COMMA_LEN ("le") },
13818   { STRING_COMMA_LEN ("gt") },
13819   { STRING_COMMA_LEN ("ge") },
13820   { STRING_COMMA_LEN ("eq") },
13821   { STRING_COMMA_LEN ("neq") },
13822   { STRING_COMMA_LEN ("false") },
13823   { STRING_COMMA_LEN ("true") }
13824 };
13825
13826 static void
13827 VPCOM_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13828              int sizeflag ATTRIBUTE_UNUSED)
13829 {
13830   unsigned int cmp_type;
13831
13832   FETCH_DATA (ins->info, ins->codep + 1);
13833   cmp_type = *ins->codep++ & 0xff;
13834   if (cmp_type < ARRAY_SIZE (xop_cmp_op))
13835     {
13836       char suffix[3];
13837       char *p = ins->mnemonicendp - 2;
13838
13839       /* vpcom* can have both one- and two-lettered suffix.  */
13840       if (p[0] == 'm')
13841         {
13842           p++;
13843           suffix[0] = p[0];
13844           suffix[1] = '\0';
13845         }
13846       else
13847         {
13848           suffix[0] = p[0];
13849           suffix[1] = p[1];
13850           suffix[2] = '\0';
13851         }
13852
13853       sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
13854       ins->mnemonicendp += xop_cmp_op[cmp_type].len;
13855     }
13856   else
13857     {
13858       /* We have a reserved extension byte.  Output it directly.  */
13859       oappend_immediate (ins, cmp_type);
13860     }
13861 }
13862
13863 static const struct op pclmul_op[] =
13864 {
13865   { STRING_COMMA_LEN ("lql") },
13866   { STRING_COMMA_LEN ("hql") },
13867   { STRING_COMMA_LEN ("lqh") },
13868   { STRING_COMMA_LEN ("hqh") }
13869 };
13870
13871 static void
13872 PCLMUL_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13873               int sizeflag ATTRIBUTE_UNUSED)
13874 {
13875   unsigned int pclmul_type;
13876
13877   FETCH_DATA (ins->info, ins->codep + 1);
13878   pclmul_type = *ins->codep++ & 0xff;
13879   switch (pclmul_type)
13880     {
13881     case 0x10:
13882       pclmul_type = 2;
13883       break;
13884     case 0x11:
13885       pclmul_type = 3;
13886       break;
13887     default:
13888       break;
13889     }
13890   if (pclmul_type < ARRAY_SIZE (pclmul_op))
13891     {
13892       char suffix[4];
13893       char *p = ins->mnemonicendp - 3;
13894       suffix[0] = p[0];
13895       suffix[1] = p[1];
13896       suffix[2] = p[2];
13897       suffix[3] = '\0';
13898       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
13899       ins->mnemonicendp += pclmul_op[pclmul_type].len;
13900     }
13901   else
13902     {
13903       /* We have a reserved extension byte.  Output it directly.  */
13904       oappend_immediate (ins, pclmul_type);
13905     }
13906 }
13907
13908 static void
13909 MOVSXD_Fixup (instr_info *ins, int bytemode, int sizeflag)
13910 {
13911   /* Add proper suffix to "movsxd".  */
13912   char *p = ins->mnemonicendp;
13913
13914   switch (bytemode)
13915     {
13916     case movsxd_mode:
13917       if (!ins->intel_syntax)
13918         {
13919           USED_REX (REX_W);
13920           if (ins->rex & REX_W)
13921             {
13922               *p++ = 'l';
13923               *p++ = 'q';
13924               break;
13925             }
13926         }
13927
13928       *p++ = 'x';
13929       *p++ = 'd';
13930       break;
13931     default:
13932       oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
13933       break;
13934     }
13935
13936   ins->mnemonicendp = p;
13937   *p = '\0';
13938   OP_E (ins, bytemode, sizeflag);
13939 }
13940
13941 static void
13942 DistinctDest_Fixup (instr_info *ins, int bytemode, int sizeflag)
13943 {
13944   unsigned int reg = ins->vex.register_specifier;
13945   unsigned int modrm_reg = ins->modrm.reg;
13946   unsigned int modrm_rm = ins->modrm.rm;
13947
13948   /* Calc destination register number.  */
13949   if (ins->rex & REX_R)
13950     modrm_reg += 8;
13951   if (!ins->vex.r)
13952     modrm_reg += 16;
13953
13954   /* Calc src1 register number.  */
13955   if (ins->address_mode != mode_64bit)
13956     reg &= 7;
13957   else if (ins->vex.evex && !ins->vex.v)
13958     reg += 16;
13959
13960   /* Calc src2 register number.  */
13961   if (ins->modrm.mod == 3)
13962     {
13963       if (ins->rex & REX_B)
13964         modrm_rm += 8;
13965       if (ins->rex & REX_X)
13966         modrm_rm += 16;
13967     }
13968
13969   /* Destination and source registers must be distinct, output bad if
13970      dest == src1 or dest == src2.  */
13971   if (modrm_reg == reg
13972       || (ins->modrm.mod == 3
13973           && modrm_reg == modrm_rm))
13974     {
13975       oappend (ins, "(bad)");
13976     }
13977   else
13978     OP_XMM (ins, bytemode, sizeflag);
13979 }
13980
13981 static void
13982 OP_Rounding (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13983 {
13984   if (ins->modrm.mod != 3 || !ins->vex.b)
13985     return;
13986
13987   switch (bytemode)
13988     {
13989     case evex_rounding_64_mode:
13990       if (ins->address_mode != mode_64bit || !ins->vex.w)
13991         return;
13992       /* Fall through.  */
13993     case evex_rounding_mode:
13994       ins->evex_used |= EVEX_b_used;
13995       oappend (ins, names_rounding[ins->vex.ll]);
13996       break;
13997     case evex_sae_mode:
13998       ins->evex_used |= EVEX_b_used;
13999       oappend (ins, "{");
14000       break;
14001     default:
14002       abort ();
14003     }
14004   oappend (ins, "sae}");
14005 }
14006
14007 static void
14008 PREFETCHI_Fixup (instr_info *ins, int bytemode, int sizeflag)
14009 {
14010   if (ins->modrm.mod != 0 || ins->modrm.rm != 5)
14011     {
14012       if (ins->intel_syntax)
14013         {
14014           ins->mnemonicendp = stpcpy (ins->obuf, "nop   ");
14015         }
14016       else
14017         {
14018           USED_REX (REX_W);
14019           if (ins->rex & REX_W)
14020             ins->mnemonicendp = stpcpy (ins->obuf, "nopq  ");
14021           else
14022             {
14023               if (sizeflag & DFLAG)
14024                 ins->mnemonicendp = stpcpy (ins->obuf, "nopl  ");
14025               else
14026                 ins->mnemonicendp = stpcpy (ins->obuf, "nopw  ");
14027               ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
14028             }
14029         }
14030       bytemode = v_mode;
14031     }
14032
14033   OP_M (ins, bytemode, sizeflag);
14034 }