opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2020 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "disassemble.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40 #include "safe-ctype.h"
  41
  42 #include <setjmp.h>
  43
  44 static int print_insn (bfd_vma, disassemble_info *);
  45 static void dofloat (int);
  46 static void OP_ST (int, int);
  47 static void OP_STi (int, int);
  48 static int putop (const char *, int);
  49 static void oappend (const char *);
  50 static void append_seg (void);
  51 static void OP_indirE (int, int);
  52 static void print_operand_value (char *, int, bfd_vma);
  53 static void OP_E_register (int, int);
  54 static void OP_E_memory (int, int);
  55 static void print_displacement (char *, bfd_vma);
  56 static void OP_E (int, int);
  57 static void OP_G (int, int);
  58 static bfd_vma get64 (void);
  59 static bfd_signed_vma get32 (void);
  60 static bfd_signed_vma get32s (void);
  61 static int get16 (void);
  62 static void set_op (bfd_vma, int);
  63 static void OP_Skip_MODRM (int, int);
  64 static void OP_REG (int, int);
  65 static void OP_IMREG (int, int);
  66 static void OP_I (int, int);
  67 static void OP_I64 (int, int);
  68 static void OP_sI (int, int);
  69 static void OP_J (int, int);
  70 static void OP_SEG (int, int);
  71 static void OP_DIR (int, int);
  72 static void OP_OFF (int, int);
  73 static void OP_OFF64 (int, int);
  74 static void ptr_reg (int, int);
  75 static void OP_ESreg (int, int);
  76 static void OP_DSreg (int, int);
  77 static void OP_C (int, int);
  78 static void OP_D (int, int);
  79 static void OP_T (int, int);
  80 static void OP_R (int, int);
  81 static void OP_MMX (int, int);
  82 static void OP_XMM (int, int);
  83 static void OP_EM (int, int);
  84 static void OP_EX (int, int);
  85 static void OP_EMC (int,int);
  86 static void OP_MXC (int,int);
  87 static void OP_MS (int, int);
  88 static void OP_XS (int, int);
  89 static void OP_M (int, int);
  90 static void OP_VEX (int, int);
  91 static void OP_VexW (int, int);
  92 static void OP_EX_Vex (int, int);
  93 static void OP_XMM_Vex (int, int);
  94 static void OP_Rounding (int, int);
  95 static void OP_REG_VexI4 (int, int);
  96 static void OP_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VPCMP_Fixup (int, int);
  99 static void VPCOM_Fixup (int, int);
 100 static void OP_0f07 (int, int);
 101 static void OP_Monitor (int, int);
 102 static void OP_Mwait (int, int);
 103 static void NOP_Fixup1 (int, int);
 104 static void NOP_Fixup2 (int, int);
 105 static void OP_3DNowSuffix (int, int);
 106 static void CMP_Fixup (int, int);
 107 static void BadOp (void);
 108 static void REP_Fixup (int, int);
 109 static void SEP_Fixup (int, int);
 110 static void BND_Fixup (int, int);
 111 static void NOTRACK_Fixup (int, int);
 112 static void HLE_Fixup1 (int, int);
 113 static void HLE_Fixup2 (int, int);
 114 static void HLE_Fixup3 (int, int);
 115 static void CMPXCHG8B_Fixup (int, int);
 116 static void XMM_Fixup (int, int);
 117 static void FXSAVE_Fixup (int, int);
 118
 119 static void MOVSXD_Fixup (int, int);
 120
 121 static void OP_Mask (int, int);
 122
 123 struct dis_private {
 124   /* Points to first byte not fetched.  */
 125   bfd_byte *max_fetched;
 126   bfd_byte the_buffer[MAX_MNEM_SIZE];
 127   bfd_vma insn_start;
 128   int orig_sizeflag;
 129   OPCODES_SIGJMP_BUF bailout;
 130 };
 131
 132 enum address_mode
 133 {
 134   mode_16bit,
 135   mode_32bit,
 136   mode_64bit
 137 };
 138
 139 enum address_mode address_mode;
 140
 141 /* Flags for the prefixes for the current instruction.  See below.  */
 142 static int prefixes;
 143
 144 /* REX prefix the current instruction.  See below.  */
 145 static int rex;
 146 /* Bits of REX we've already used.  */
 147 static int rex_used;
 148 /* Mark parts used in the REX prefix.  When we are testing for
 149    empty prefix (for 8bit register REX extension), just mask it
 150    out.  Otherwise test for REX bit is excuse for existence of REX
 151    only in case value is nonzero.  */
 152 #define USED_REX(value)                                 \
 153   {                                                     \
 154     if (value)                                          \
 155       {                                                 \
 156         if ((rex & value))                              \
 157           rex_used |= (value) | REX_OPCODE;             \
 158       }                                                 \
 159     else                                                \
 160       rex_used |= REX_OPCODE;                           \
 161   }
 162
 163 /* Flags for prefixes which we somehow handled when printing the
 164    current instruction.  */
 165 static int used_prefixes;
 166
 167 /* Flags stored in PREFIXES.  */
 168 #define PREFIX_REPZ 1
 169 #define PREFIX_REPNZ 2
 170 #define PREFIX_LOCK 4
 171 #define PREFIX_CS 8
 172 #define PREFIX_SS 0x10
 173 #define PREFIX_DS 0x20
 174 #define PREFIX_ES 0x40
 175 #define PREFIX_FS 0x80
 176 #define PREFIX_GS 0x100
 177 #define PREFIX_DATA 0x200
 178 #define PREFIX_ADDR 0x400
 179 #define PREFIX_FWAIT 0x800
 180
 181 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 182    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 183    on error.  */
 184 #define FETCH_DATA(info, addr) \
 185   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 186    ? 1 : fetch_data ((info), (addr)))
 187
 188 static int
 189 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 190 {
 191   int status;
 192   struct dis_private *priv = (struct dis_private *) info->private_data;
 193   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 194
 195   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 196     status = (*info->read_memory_func) (start,
 197                                         priv->max_fetched,
 198                                         addr - priv->max_fetched,
 199                                         info);
 200   else
 201     status = -1;
 202   if (status != 0)
 203     {
 204       /* If we did manage to read at least one byte, then
 205          print_insn_i386 will do something sensible.  Otherwise, print
 206          an error.  We do that here because this is where we know
 207          STATUS.  */
 208       if (priv->max_fetched == priv->the_buffer)
 209         (*info->memory_error_func) (status, start, info);
 210       OPCODES_SIGLONGJMP (priv->bailout, 1);
 211     }
 212   else
 213     priv->max_fetched = addr;
 214   return 1;
 215 }
 216
 217 /* Possible values for prefix requirement.  */
 218 #define PREFIX_IGNORED_SHIFT    16
 219 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 220 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 221 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 222 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 223 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 224
 225 /* Opcode prefixes.  */
 226 #define PREFIX_OPCODE           (PREFIX_REPZ \
 227                                  | PREFIX_REPNZ \
 228                                  | PREFIX_DATA)
 229
 230 /* Prefixes ignored.  */
 231 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 232                                  | PREFIX_IGNORED_REPNZ \
 233                                  | PREFIX_IGNORED_DATA)
 234
 235 #define XX { NULL, 0 }
 236 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 237
 238 #define Eb { OP_E, b_mode }
 239 #define Ebnd { OP_E, bnd_mode }
 240 #define EbS { OP_E, b_swap_mode }
 241 #define EbndS { OP_E, bnd_swap_mode }
 242 #define Ev { OP_E, v_mode }
 243 #define Eva { OP_E, va_mode }
 244 #define Ev_bnd { OP_E, v_bnd_mode }
 245 #define EvS { OP_E, v_swap_mode }
 246 #define Ed { OP_E, d_mode }
 247 #define Edq { OP_E, dq_mode }
 248 #define Edqw { OP_E, dqw_mode }
 249 #define Edqb { OP_E, dqb_mode }
 250 #define Edb { OP_E, db_mode }
 251 #define Edw { OP_E, dw_mode }
 252 #define Edqd { OP_E, dqd_mode }
 253 #define Eq { OP_E, q_mode }
 254 #define indirEv { OP_indirE, indir_v_mode }
 255 #define indirEp { OP_indirE, f_mode }
 256 #define stackEv { OP_E, stack_v_mode }
 257 #define Em { OP_E, m_mode }
 258 #define Ew { OP_E, w_mode }
 259 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 260 #define Ma { OP_M, a_mode }
 261 #define Mb { OP_M, b_mode }
 262 #define Md { OP_M, d_mode }
 263 #define Mo { OP_M, o_mode }
 264 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 265 #define Mq { OP_M, q_mode }
 266 #define Mv { OP_M, v_mode }
 267 #define Mv_bnd { OP_M, v_bndmk_mode }
 268 #define Mx { OP_M, x_mode }
 269 #define Mxmm { OP_M, xmm_mode }
 270 #define Gb { OP_G, b_mode }
 271 #define Gbnd { OP_G, bnd_mode }
 272 #define Gv { OP_G, v_mode }
 273 #define Gd { OP_G, d_mode }
 274 #define Gdq { OP_G, dq_mode }
 275 #define Gm { OP_G, m_mode }
 276 #define Gva { OP_G, va_mode }
 277 #define Gw { OP_G, w_mode }
 278 #define Rd { OP_R, d_mode }
 279 #define Rdq { OP_R, dq_mode }
 280 #define Rm { OP_R, m_mode }
 281 #define Ib { OP_I, b_mode }
 282 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 283 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 284 #define Iv { OP_I, v_mode }
 285 #define sIv { OP_sI, v_mode }
 286 #define Iv64 { OP_I64, v_mode }
 287 #define Id { OP_I, d_mode }
 288 #define Iw { OP_I, w_mode }
 289 #define I1 { OP_I, const_1_mode }
 290 #define Jb { OP_J, b_mode }
 291 #define Jv { OP_J, v_mode }
 292 #define Jdqw { OP_J, dqw_mode }
 293 #define Cm { OP_C, m_mode }
 294 #define Dm { OP_D, m_mode }
 295 #define Td { OP_T, d_mode }
 296 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 297
 298 #define RMeAX { OP_REG, eAX_reg }
 299 #define RMeBX { OP_REG, eBX_reg }
 300 #define RMeCX { OP_REG, eCX_reg }
 301 #define RMeDX { OP_REG, eDX_reg }
 302 #define RMeSP { OP_REG, eSP_reg }
 303 #define RMeBP { OP_REG, eBP_reg }
 304 #define RMeSI { OP_REG, eSI_reg }
 305 #define RMeDI { OP_REG, eDI_reg }
 306 #define RMrAX { OP_REG, rAX_reg }
 307 #define RMrBX { OP_REG, rBX_reg }
 308 #define RMrCX { OP_REG, rCX_reg }
 309 #define RMrDX { OP_REG, rDX_reg }
 310 #define RMrSP { OP_REG, rSP_reg }
 311 #define RMrBP { OP_REG, rBP_reg }
 312 #define RMrSI { OP_REG, rSI_reg }
 313 #define RMrDI { OP_REG, rDI_reg }
 314 #define RMAL { OP_REG, al_reg }
 315 #define RMCL { OP_REG, cl_reg }
 316 #define RMDL { OP_REG, dl_reg }
 317 #define RMBL { OP_REG, bl_reg }
 318 #define RMAH { OP_REG, ah_reg }
 319 #define RMCH { OP_REG, ch_reg }
 320 #define RMDH { OP_REG, dh_reg }
 321 #define RMBH { OP_REG, bh_reg }
 322 #define RMAX { OP_REG, ax_reg }
 323 #define RMDX { OP_REG, dx_reg }
 324
 325 #define eAX { OP_IMREG, eAX_reg }
 326 #define AL { OP_IMREG, al_reg }
 327 #define CL { OP_IMREG, cl_reg }
 328 #define zAX { OP_IMREG, z_mode_ax_reg }
 329 #define indirDX { OP_IMREG, indir_dx_reg }
 330
 331 #define Sw { OP_SEG, w_mode }
 332 #define Sv { OP_SEG, v_mode }
 333 #define Ap { OP_DIR, 0 }
 334 #define Ob { OP_OFF64, b_mode }
 335 #define Ov { OP_OFF64, v_mode }
 336 #define Xb { OP_DSreg, eSI_reg }
 337 #define Xv { OP_DSreg, eSI_reg }
 338 #define Xz { OP_DSreg, eSI_reg }
 339 #define Yb { OP_ESreg, eDI_reg }
 340 #define Yv { OP_ESreg, eDI_reg }
 341 #define DSBX { OP_DSreg, eBX_reg }
 342
 343 #define es { OP_REG, es_reg }
 344 #define ss { OP_REG, ss_reg }
 345 #define cs { OP_REG, cs_reg }
 346 #define ds { OP_REG, ds_reg }
 347 #define fs { OP_REG, fs_reg }
 348 #define gs { OP_REG, gs_reg }
 349
 350 #define MX { OP_MMX, 0 }
 351 #define XM { OP_XMM, 0 }
 352 #define XMScalar { OP_XMM, scalar_mode }
 353 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 354 #define XMM { OP_XMM, xmm_mode }
 355 #define TMM { OP_XMM, tmm_mode }
 356 #define XMxmmq { OP_XMM, xmmq_mode }
 357 #define EM { OP_EM, v_mode }
 358 #define EMS { OP_EM, v_swap_mode }
 359 #define EMd { OP_EM, d_mode }
 360 #define EMx { OP_EM, x_mode }
 361 #define EXbwUnit { OP_EX, bw_unit_mode }
 362 #define EXw { OP_EX, w_mode }
 363 #define EXd { OP_EX, d_mode }
 364 #define EXdS { OP_EX, d_swap_mode }
 365 #define EXq { OP_EX, q_mode }
 366 #define EXqS { OP_EX, q_swap_mode }
 367 #define EXx { OP_EX, x_mode }
 368 #define EXxS { OP_EX, x_swap_mode }
 369 #define EXxmm { OP_EX, xmm_mode }
 370 #define EXymm { OP_EX, ymm_mode }
 371 #define EXtmm { OP_EX, tmm_mode }
 372 #define EXxmmq { OP_EX, xmmq_mode }
 373 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 374 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 375 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 376 #define EXxmm_md { OP_EX, xmm_md_mode }
 377 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 378 #define EXxmmdw { OP_EX, xmmdw_mode }
 379 #define EXxmmqd { OP_EX, xmmqd_mode }
 380 #define EXymmq { OP_EX, ymmq_mode }
 381 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 382 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 383 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 384 #define MS { OP_MS, v_mode }
 385 #define XS { OP_XS, v_mode }
 386 #define EMCq { OP_EMC, q_mode }
 387 #define MXC { OP_MXC, 0 }
 388 #define OPSUF { OP_3DNowSuffix, 0 }
 389 #define SEP { SEP_Fixup, 0 }
 390 #define CMP { CMP_Fixup, 0 }
 391 #define XMM0 { XMM_Fixup, 0 }
 392 #define FXSAVE { FXSAVE_Fixup, 0 }
 393
 394 #define Vex { OP_VEX, vex_mode }
 395 #define VexW { OP_VexW, vex_mode }
 396 #define VexScalar { OP_VEX, vex_scalar_mode }
 397 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 398 #define Vex128 { OP_VEX, vex128_mode }
 399 #define Vex256 { OP_VEX, vex256_mode }
 400 #define VexGdq { OP_VEX, dq_mode }
 401 #define VexTmm { OP_VEX, tmm_mode }
 402 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 403 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 404 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 405 #define XMVexI4 { OP_REG_VexI4, x_mode }
 406 #define XMVexScalarI4 { OP_REG_VexI4, scalar_mode }
 407 #define VexI4 { OP_VexI4, 0 }
 408 #define PCLMUL { PCLMUL_Fixup, 0 }
 409 #define VPCMP { VPCMP_Fixup, 0 }
 410 #define VPCOM { VPCOM_Fixup, 0 }
 411
 412 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 413 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
 414 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 415
 416 #define XMask { OP_Mask, mask_mode }
 417 #define MaskG { OP_G, mask_mode }
 418 #define MaskE { OP_E, mask_mode }
 419 #define MaskBDE { OP_E, mask_bd_mode }
 420 #define MaskR { OP_R, mask_mode }
 421 #define MaskVex { OP_VEX, mask_mode }
 422
 423 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 424 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 425 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 426 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 427
 428 #define MVexSIBMEM { OP_M, vex_sibmem_mode }
 429
 430 /* Used handle "rep" prefix for string instructions.  */
 431 #define Xbr { REP_Fixup, eSI_reg }
 432 #define Xvr { REP_Fixup, eSI_reg }
 433 #define Ybr { REP_Fixup, eDI_reg }
 434 #define Yvr { REP_Fixup, eDI_reg }
 435 #define Yzr { REP_Fixup, eDI_reg }
 436 #define indirDXr { REP_Fixup, indir_dx_reg }
 437 #define ALr { REP_Fixup, al_reg }
 438 #define eAXr { REP_Fixup, eAX_reg }
 439
 440 /* Used handle HLE prefix for lockable instructions.  */
 441 #define Ebh1 { HLE_Fixup1, b_mode }
 442 #define Evh1 { HLE_Fixup1, v_mode }
 443 #define Ebh2 { HLE_Fixup2, b_mode }
 444 #define Evh2 { HLE_Fixup2, v_mode }
 445 #define Ebh3 { HLE_Fixup3, b_mode }
 446 #define Evh3 { HLE_Fixup3, v_mode }
 447
 448 #define BND { BND_Fixup, 0 }
 449 #define NOTRACK { NOTRACK_Fixup, 0 }
 450
 451 #define cond_jump_flag { NULL, cond_jump_mode }
 452 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 453
 454 /* bits in sizeflag */
 455 #define SUFFIX_ALWAYS 4
 456 #define AFLAG 2
 457 #define DFLAG 1
 458
 459 enum
 460 {
 461   /* byte operand */
 462   b_mode = 1,
 463   /* byte operand with operand swapped */
 464   b_swap_mode,
 465   /* byte operand, sign extend like 'T' suffix */
 466   b_T_mode,
 467   /* operand size depends on prefixes */
 468   v_mode,
 469   /* operand size depends on prefixes with operand swapped */
 470   v_swap_mode,
 471   /* operand size depends on address prefix */
 472   va_mode,
 473   /* word operand */
 474   w_mode,
 475   /* double word operand  */
 476   d_mode,
 477   /* double word operand with operand swapped */
 478   d_swap_mode,
 479   /* quad word operand */
 480   q_mode,
 481   /* quad word operand with operand swapped */
 482   q_swap_mode,
 483   /* ten-byte operand */
 484   t_mode,
 485   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 486      broadcast enabled.  */
 487   x_mode,
 488   /* Similar to x_mode, but with different EVEX mem shifts.  */
 489   evex_x_gscat_mode,
 490   /* Similar to x_mode, but with yet different EVEX mem shifts.  */
 491   bw_unit_mode,
 492   /* Similar to x_mode, but with disabled broadcast.  */
 493   evex_x_nobcst_mode,
 494   /* Similar to x_mode, but with operands swapped and disabled broadcast
 495      in EVEX.  */
 496   x_swap_mode,
 497   /* 16-byte XMM operand */
 498   xmm_mode,
 499   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 500      memory operand (depending on vector length).  Broadcast isn't
 501      allowed.  */
 502   xmmq_mode,
 503   /* Same as xmmq_mode, but broadcast is allowed.  */
 504   evex_half_bcst_xmmq_mode,
 505   /* XMM register or byte memory operand */
 506   xmm_mb_mode,
 507   /* XMM register or word memory operand */
 508   xmm_mw_mode,
 509   /* XMM register or double word memory operand */
 510   xmm_md_mode,
 511   /* XMM register or quad word memory operand */
 512   xmm_mq_mode,
 513   /* 16-byte XMM, word, double word or quad word operand.  */
 514   xmmdw_mode,
 515   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 516   xmmqd_mode,
 517   /* 32-byte YMM operand */
 518   ymm_mode,
 519   /* quad word, ymmword or zmmword memory operand.  */
 520   ymmq_mode,
 521   /* 32-byte YMM or 16-byte word operand */
 522   ymmxmm_mode,
 523   /* TMM operand */
 524   tmm_mode,
 525   /* d_mode in 32bit, q_mode in 64bit mode.  */
 526   m_mode,
 527   /* pair of v_mode operands */
 528   a_mode,
 529   cond_jump_mode,
 530   loop_jcxz_mode,
 531   movsxd_mode,
 532   v_bnd_mode,
 533   /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode.  */
 534   v_bndmk_mode,
 535   /* operand size depends on REX prefixes.  */
 536   dq_mode,
 537   /* registers like dq_mode, memory like w_mode, displacements like
 538      v_mode without considering Intel64 ISA.  */
 539   dqw_mode,
 540   /* bounds operand */
 541   bnd_mode,
 542   /* bounds operand with operand swapped */
 543   bnd_swap_mode,
 544   /* 4- or 6-byte pointer operand */
 545   f_mode,
 546   const_1_mode,
 547   /* v_mode for indirect branch opcodes.  */
 548   indir_v_mode,
 549   /* v_mode for stack-related opcodes.  */
 550   stack_v_mode,
 551   /* non-quad operand size depends on prefixes */
 552   z_mode,
 553   /* 16-byte operand */
 554   o_mode,
 555   /* registers like dq_mode, memory like b_mode.  */
 556   dqb_mode,
 557   /* registers like d_mode, memory like b_mode.  */
 558   db_mode,
 559   /* registers like d_mode, memory like w_mode.  */
 560   dw_mode,
 561   /* registers like dq_mode, memory like d_mode.  */
 562   dqd_mode,
 563   /* normal vex mode */
 564   vex_mode,
 565   /* 128bit vex mode */
 566   vex128_mode,
 567   /* 256bit vex mode */
 568   vex256_mode,
 569
 570   /* Operand size depends on the VEX.W bit, with VSIB dword indices.  */
 571   vex_vsib_d_w_dq_mode,
 572   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 573   vex_vsib_d_w_d_mode,
 574   /* Operand size depends on the VEX.W bit, with VSIB qword indices.  */
 575   vex_vsib_q_w_dq_mode,
 576   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 577   vex_vsib_q_w_d_mode,
 578   /* mandatory non-vector SIB.  */
 579   vex_sibmem_mode,
 580
 581   /* scalar, ignore vector length.  */
 582   scalar_mode,
 583   /* like d_swap_mode, ignore vector length.  */
 584   d_scalar_swap_mode,
 585   /* like q_swap_mode, ignore vector length.  */
 586   q_scalar_swap_mode,
 587   /* like vex_mode, ignore vector length.  */
 588   vex_scalar_mode,
 589   /* Operand size depends on the VEX.W bit, ignore vector length.  */
 590   vex_scalar_w_dq_mode,
 591
 592   /* Static rounding.  */
 593   evex_rounding_mode,
 594   /* Static rounding, 64-bit mode only.  */
 595   evex_rounding_64_mode,
 596   /* Supress all exceptions.  */
 597   evex_sae_mode,
 598
 599   /* Mask register operand.  */
 600   mask_mode,
 601   /* Mask register operand.  */
 602   mask_bd_mode,
 603
 604   es_reg,
 605   cs_reg,
 606   ss_reg,
 607   ds_reg,
 608   fs_reg,
 609   gs_reg,
 610
 611   eAX_reg,
 612   eCX_reg,
 613   eDX_reg,
 614   eBX_reg,
 615   eSP_reg,
 616   eBP_reg,
 617   eSI_reg,
 618   eDI_reg,
 619
 620   al_reg,
 621   cl_reg,
 622   dl_reg,
 623   bl_reg,
 624   ah_reg,
 625   ch_reg,
 626   dh_reg,
 627   bh_reg,
 628
 629   ax_reg,
 630   cx_reg,
 631   dx_reg,
 632   bx_reg,
 633   sp_reg,
 634   bp_reg,
 635   si_reg,
 636   di_reg,
 637
 638   rAX_reg,
 639   rCX_reg,
 640   rDX_reg,
 641   rBX_reg,
 642   rSP_reg,
 643   rBP_reg,
 644   rSI_reg,
 645   rDI_reg,
 646
 647   z_mode_ax_reg,
 648   indir_dx_reg
 649 };
 650
 651 enum
 652 {
 653   FLOATCODE = 1,
 654   USE_REG_TABLE,
 655   USE_MOD_TABLE,
 656   USE_RM_TABLE,
 657   USE_PREFIX_TABLE,
 658   USE_X86_64_TABLE,
 659   USE_3BYTE_TABLE,
 660   USE_XOP_8F_TABLE,
 661   USE_VEX_C4_TABLE,
 662   USE_VEX_C5_TABLE,
 663   USE_VEX_LEN_TABLE,
 664   USE_VEX_W_TABLE,
 665   USE_EVEX_TABLE,
 666   USE_EVEX_LEN_TABLE
 667 };
 668
 669 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 670
 671 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 672 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 673 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 674 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 675 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 676 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 677 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 678 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 679 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 680 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 681 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 682 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 683 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 684 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 685 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 686 #define EVEX_LEN_TABLE(I)       DIS386 (USE_EVEX_LEN_TABLE, (I))
 687
 688 enum
 689 {
 690   REG_80 = 0,
 691   REG_81,
 692   REG_83,
 693   REG_8F,
 694   REG_C0,
 695   REG_C1,
 696   REG_C6,
 697   REG_C7,
 698   REG_D0,
 699   REG_D1,
 700   REG_D2,
 701   REG_D3,
 702   REG_F6,
 703   REG_F7,
 704   REG_FE,
 705   REG_FF,
 706   REG_0F00,
 707   REG_0F01,
 708   REG_0F0D,
 709   REG_0F18,
 710   REG_0F1C_P_0_MOD_0,
 711   REG_0F1E_P_1_MOD_3,
 712   REG_0F71,
 713   REG_0F72,
 714   REG_0F73,
 715   REG_0FA6,
 716   REG_0FA7,
 717   REG_0FAE,
 718   REG_0FBA,
 719   REG_0FC7,
 720   REG_VEX_0F71,
 721   REG_VEX_0F72,
 722   REG_VEX_0F73,
 723   REG_VEX_0FAE,
 724   REG_VEX_0F3849_X86_64_P_0_W_0_M_1,
 725   REG_VEX_0F38F3,
 726
 727   REG_0FXOP_09_01_L_0,
 728   REG_0FXOP_09_02_L_0,
 729   REG_0FXOP_09_12_M_1_L_0,
 730   REG_0FXOP_0A_12_L_0,
 731
 732   REG_EVEX_0F71,
 733   REG_EVEX_0F72,
 734   REG_EVEX_0F73,
 735   REG_EVEX_0F38C6,
 736   REG_EVEX_0F38C7
 737 };
 738
 739 enum
 740 {
 741   MOD_8D = 0,
 742   MOD_C6_REG_7,
 743   MOD_C7_REG_7,
 744   MOD_FF_REG_3,
 745   MOD_FF_REG_5,
 746   MOD_0F01_REG_0,
 747   MOD_0F01_REG_1,
 748   MOD_0F01_REG_2,
 749   MOD_0F01_REG_3,
 750   MOD_0F01_REG_5,
 751   MOD_0F01_REG_7,
 752   MOD_0F12_PREFIX_0,
 753   MOD_0F12_PREFIX_2,
 754   MOD_0F13,
 755   MOD_0F16_PREFIX_0,
 756   MOD_0F16_PREFIX_2,
 757   MOD_0F17,
 758   MOD_0F18_REG_0,
 759   MOD_0F18_REG_1,
 760   MOD_0F18_REG_2,
 761   MOD_0F18_REG_3,
 762   MOD_0F18_REG_4,
 763   MOD_0F18_REG_5,
 764   MOD_0F18_REG_6,
 765   MOD_0F18_REG_7,
 766   MOD_0F1A_PREFIX_0,
 767   MOD_0F1B_PREFIX_0,
 768   MOD_0F1B_PREFIX_1,
 769   MOD_0F1C_PREFIX_0,
 770   MOD_0F1E_PREFIX_1,
 771   MOD_0F24,
 772   MOD_0F26,
 773   MOD_0F2B_PREFIX_0,
 774   MOD_0F2B_PREFIX_1,
 775   MOD_0F2B_PREFIX_2,
 776   MOD_0F2B_PREFIX_3,
 777   MOD_0F50,
 778   MOD_0F71_REG_2,
 779   MOD_0F71_REG_4,
 780   MOD_0F71_REG_6,
 781   MOD_0F72_REG_2,
 782   MOD_0F72_REG_4,
 783   MOD_0F72_REG_6,
 784   MOD_0F73_REG_2,
 785   MOD_0F73_REG_3,
 786   MOD_0F73_REG_6,
 787   MOD_0F73_REG_7,
 788   MOD_0FAE_REG_0,
 789   MOD_0FAE_REG_1,
 790   MOD_0FAE_REG_2,
 791   MOD_0FAE_REG_3,
 792   MOD_0FAE_REG_4,
 793   MOD_0FAE_REG_5,
 794   MOD_0FAE_REG_6,
 795   MOD_0FAE_REG_7,
 796   MOD_0FB2,
 797   MOD_0FB4,
 798   MOD_0FB5,
 799   MOD_0FC3,
 800   MOD_0FC7_REG_3,
 801   MOD_0FC7_REG_4,
 802   MOD_0FC7_REG_5,
 803   MOD_0FC7_REG_6,
 804   MOD_0FC7_REG_7,
 805   MOD_0FD7,
 806   MOD_0FE7_PREFIX_2,
 807   MOD_0FF0_PREFIX_3,
 808   MOD_0F382A_PREFIX_2,
 809   MOD_VEX_0F3849_X86_64_P_0_W_0,
 810   MOD_VEX_0F3849_X86_64_P_2_W_0,
 811   MOD_VEX_0F3849_X86_64_P_3_W_0,
 812   MOD_VEX_0F384B_X86_64_P_1_W_0,
 813   MOD_VEX_0F384B_X86_64_P_2_W_0,
 814   MOD_VEX_0F384B_X86_64_P_3_W_0,
 815   MOD_VEX_0F385C_X86_64_P_1_W_0,
 816   MOD_VEX_0F385E_X86_64_P_0_W_0,
 817   MOD_VEX_0F385E_X86_64_P_1_W_0,
 818   MOD_VEX_0F385E_X86_64_P_2_W_0,
 819   MOD_VEX_0F385E_X86_64_P_3_W_0,
 820   MOD_0F38F5_PREFIX_2,
 821   MOD_0F38F6_PREFIX_0,
 822   MOD_0F38F8_PREFIX_1,
 823   MOD_0F38F8_PREFIX_2,
 824   MOD_0F38F8_PREFIX_3,
 825   MOD_0F38F9_PREFIX_0,
 826   MOD_62_32BIT,
 827   MOD_C4_32BIT,
 828   MOD_C5_32BIT,
 829   MOD_VEX_0F12_PREFIX_0,
 830   MOD_VEX_0F12_PREFIX_2,
 831   MOD_VEX_0F13,
 832   MOD_VEX_0F16_PREFIX_0,
 833   MOD_VEX_0F16_PREFIX_2,
 834   MOD_VEX_0F17,
 835   MOD_VEX_0F2B,
 836   MOD_VEX_W_0_0F41_P_0_LEN_1,
 837   MOD_VEX_W_1_0F41_P_0_LEN_1,
 838   MOD_VEX_W_0_0F41_P_2_LEN_1,
 839   MOD_VEX_W_1_0F41_P_2_LEN_1,
 840   MOD_VEX_W_0_0F42_P_0_LEN_1,
 841   MOD_VEX_W_1_0F42_P_0_LEN_1,
 842   MOD_VEX_W_0_0F42_P_2_LEN_1,
 843   MOD_VEX_W_1_0F42_P_2_LEN_1,
 844   MOD_VEX_W_0_0F44_P_0_LEN_1,
 845   MOD_VEX_W_1_0F44_P_0_LEN_1,
 846   MOD_VEX_W_0_0F44_P_2_LEN_1,
 847   MOD_VEX_W_1_0F44_P_2_LEN_1,
 848   MOD_VEX_W_0_0F45_P_0_LEN_1,
 849   MOD_VEX_W_1_0F45_P_0_LEN_1,
 850   MOD_VEX_W_0_0F45_P_2_LEN_1,
 851   MOD_VEX_W_1_0F45_P_2_LEN_1,
 852   MOD_VEX_W_0_0F46_P_0_LEN_1,
 853   MOD_VEX_W_1_0F46_P_0_LEN_1,
 854   MOD_VEX_W_0_0F46_P_2_LEN_1,
 855   MOD_VEX_W_1_0F46_P_2_LEN_1,
 856   MOD_VEX_W_0_0F47_P_0_LEN_1,
 857   MOD_VEX_W_1_0F47_P_0_LEN_1,
 858   MOD_VEX_W_0_0F47_P_2_LEN_1,
 859   MOD_VEX_W_1_0F47_P_2_LEN_1,
 860   MOD_VEX_W_0_0F4A_P_0_LEN_1,
 861   MOD_VEX_W_1_0F4A_P_0_LEN_1,
 862   MOD_VEX_W_0_0F4A_P_2_LEN_1,
 863   MOD_VEX_W_1_0F4A_P_2_LEN_1,
 864   MOD_VEX_W_0_0F4B_P_0_LEN_1,
 865   MOD_VEX_W_1_0F4B_P_0_LEN_1,
 866   MOD_VEX_W_0_0F4B_P_2_LEN_1,
 867   MOD_VEX_0F50,
 868   MOD_VEX_0F71_REG_2,
 869   MOD_VEX_0F71_REG_4,
 870   MOD_VEX_0F71_REG_6,
 871   MOD_VEX_0F72_REG_2,
 872   MOD_VEX_0F72_REG_4,
 873   MOD_VEX_0F72_REG_6,
 874   MOD_VEX_0F73_REG_2,
 875   MOD_VEX_0F73_REG_3,
 876   MOD_VEX_0F73_REG_6,
 877   MOD_VEX_0F73_REG_7,
 878   MOD_VEX_W_0_0F91_P_0_LEN_0,
 879   MOD_VEX_W_1_0F91_P_0_LEN_0,
 880   MOD_VEX_W_0_0F91_P_2_LEN_0,
 881   MOD_VEX_W_1_0F91_P_2_LEN_0,
 882   MOD_VEX_W_0_0F92_P_0_LEN_0,
 883   MOD_VEX_W_0_0F92_P_2_LEN_0,
 884   MOD_VEX_0F92_P_3_LEN_0,
 885   MOD_VEX_W_0_0F93_P_0_LEN_0,
 886   MOD_VEX_W_0_0F93_P_2_LEN_0,
 887   MOD_VEX_0F93_P_3_LEN_0,
 888   MOD_VEX_W_0_0F98_P_0_LEN_0,
 889   MOD_VEX_W_1_0F98_P_0_LEN_0,
 890   MOD_VEX_W_0_0F98_P_2_LEN_0,
 891   MOD_VEX_W_1_0F98_P_2_LEN_0,
 892   MOD_VEX_W_0_0F99_P_0_LEN_0,
 893   MOD_VEX_W_1_0F99_P_0_LEN_0,
 894   MOD_VEX_W_0_0F99_P_2_LEN_0,
 895   MOD_VEX_W_1_0F99_P_2_LEN_0,
 896   MOD_VEX_0FAE_REG_2,
 897   MOD_VEX_0FAE_REG_3,
 898   MOD_VEX_0FD7_PREFIX_2,
 899   MOD_VEX_0FE7_PREFIX_2,
 900   MOD_VEX_0FF0_PREFIX_3,
 901   MOD_VEX_0F381A_PREFIX_2,
 902   MOD_VEX_0F382A_PREFIX_2,
 903   MOD_VEX_0F382C_PREFIX_2,
 904   MOD_VEX_0F382D_PREFIX_2,
 905   MOD_VEX_0F382E_PREFIX_2,
 906   MOD_VEX_0F382F_PREFIX_2,
 907   MOD_VEX_0F385A_PREFIX_2,
 908   MOD_VEX_0F388C_PREFIX_2,
 909   MOD_VEX_0F388E_PREFIX_2,
 910   MOD_VEX_W_0_0F3A30_P_2_LEN_0,
 911   MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 912   MOD_VEX_W_0_0F3A31_P_2_LEN_0,
 913   MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 914   MOD_VEX_W_0_0F3A32_P_2_LEN_0,
 915   MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 916   MOD_VEX_W_0_0F3A33_P_2_LEN_0,
 917   MOD_VEX_W_1_0F3A33_P_2_LEN_0,
 918
 919   MOD_VEX_0FXOP_09_12,
 920
 921   MOD_EVEX_0F12_PREFIX_0,
 922   MOD_EVEX_0F12_PREFIX_2,
 923   MOD_EVEX_0F13,
 924   MOD_EVEX_0F16_PREFIX_0,
 925   MOD_EVEX_0F16_PREFIX_2,
 926   MOD_EVEX_0F17,
 927   MOD_EVEX_0F2B,
 928   MOD_EVEX_0F381A_P_2_W_0,
 929   MOD_EVEX_0F381A_P_2_W_1,
 930   MOD_EVEX_0F381B_P_2_W_0,
 931   MOD_EVEX_0F381B_P_2_W_1,
 932   MOD_EVEX_0F385A_P_2_W_0,
 933   MOD_EVEX_0F385A_P_2_W_1,
 934   MOD_EVEX_0F385B_P_2_W_0,
 935   MOD_EVEX_0F385B_P_2_W_1,
 936   MOD_EVEX_0F38C6_REG_1,
 937   MOD_EVEX_0F38C6_REG_2,
 938   MOD_EVEX_0F38C6_REG_5,
 939   MOD_EVEX_0F38C6_REG_6,
 940   MOD_EVEX_0F38C7_REG_1,
 941   MOD_EVEX_0F38C7_REG_2,
 942   MOD_EVEX_0F38C7_REG_5,
 943   MOD_EVEX_0F38C7_REG_6
 944 };
 945
 946 enum
 947 {
 948   RM_C6_REG_7 = 0,
 949   RM_C7_REG_7,
 950   RM_0F01_REG_0,
 951   RM_0F01_REG_1,
 952   RM_0F01_REG_2,
 953   RM_0F01_REG_3,
 954   RM_0F01_REG_5_MOD_3,
 955   RM_0F01_REG_7_MOD_3,
 956   RM_0F1E_P_1_MOD_3_REG_7,
 957   RM_0FAE_REG_6_MOD_3_P_0,
 958   RM_0FAE_REG_7_MOD_3,
 959   RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0
 960 };
 961
 962 enum
 963 {
 964   PREFIX_90 = 0,
 965   PREFIX_0F01_REG_3_RM_1,
 966   PREFIX_0F01_REG_5_MOD_0,
 967   PREFIX_0F01_REG_5_MOD_3_RM_0,
 968   PREFIX_0F01_REG_5_MOD_3_RM_1,
 969   PREFIX_0F01_REG_5_MOD_3_RM_2,
 970   PREFIX_0F01_REG_7_MOD_3_RM_2,
 971   PREFIX_0F01_REG_7_MOD_3_RM_3,
 972   PREFIX_0F09,
 973   PREFIX_0F10,
 974   PREFIX_0F11,
 975   PREFIX_0F12,
 976   PREFIX_0F16,
 977   PREFIX_0F1A,
 978   PREFIX_0F1B,
 979   PREFIX_0F1C,
 980   PREFIX_0F1E,
 981   PREFIX_0F2A,
 982   PREFIX_0F2B,
 983   PREFIX_0F2C,
 984   PREFIX_0F2D,
 985   PREFIX_0F2E,
 986   PREFIX_0F2F,
 987   PREFIX_0F51,
 988   PREFIX_0F52,
 989   PREFIX_0F53,
 990   PREFIX_0F58,
 991   PREFIX_0F59,
 992   PREFIX_0F5A,
 993   PREFIX_0F5B,
 994   PREFIX_0F5C,
 995   PREFIX_0F5D,
 996   PREFIX_0F5E,
 997   PREFIX_0F5F,
 998   PREFIX_0F60,
 999   PREFIX_0F61,
1000   PREFIX_0F62,
1001   PREFIX_0F6C,
1002   PREFIX_0F6D,
1003   PREFIX_0F6F,
1004   PREFIX_0F70,
1005   PREFIX_0F73_REG_3,
1006   PREFIX_0F73_REG_7,
1007   PREFIX_0F78,
1008   PREFIX_0F79,
1009   PREFIX_0F7C,
1010   PREFIX_0F7D,
1011   PREFIX_0F7E,
1012   PREFIX_0F7F,
1013   PREFIX_0FAE_REG_0_MOD_3,
1014   PREFIX_0FAE_REG_1_MOD_3,
1015   PREFIX_0FAE_REG_2_MOD_3,
1016   PREFIX_0FAE_REG_3_MOD_3,
1017   PREFIX_0FAE_REG_4_MOD_0,
1018   PREFIX_0FAE_REG_4_MOD_3,
1019   PREFIX_0FAE_REG_5_MOD_0,
1020   PREFIX_0FAE_REG_5_MOD_3,
1021   PREFIX_0FAE_REG_6_MOD_0,
1022   PREFIX_0FAE_REG_6_MOD_3,
1023   PREFIX_0FAE_REG_7_MOD_0,
1024   PREFIX_0FB8,
1025   PREFIX_0FBC,
1026   PREFIX_0FBD,
1027   PREFIX_0FC2,
1028   PREFIX_0FC3_MOD_0,
1029   PREFIX_0FC7_REG_6_MOD_0,
1030   PREFIX_0FC7_REG_6_MOD_3,
1031   PREFIX_0FC7_REG_7_MOD_3,
1032   PREFIX_0FD0,
1033   PREFIX_0FD6,
1034   PREFIX_0FE6,
1035   PREFIX_0FE7,
1036   PREFIX_0FF0,
1037   PREFIX_0FF7,
1038   PREFIX_0F3810,
1039   PREFIX_0F3814,
1040   PREFIX_0F3815,
1041   PREFIX_0F3817,
1042   PREFIX_0F3820,
1043   PREFIX_0F3821,
1044   PREFIX_0F3822,
1045   PREFIX_0F3823,
1046   PREFIX_0F3824,
1047   PREFIX_0F3825,
1048   PREFIX_0F3828,
1049   PREFIX_0F3829,
1050   PREFIX_0F382A,
1051   PREFIX_0F382B,
1052   PREFIX_0F3830,
1053   PREFIX_0F3831,
1054   PREFIX_0F3832,
1055   PREFIX_0F3833,
1056   PREFIX_0F3834,
1057   PREFIX_0F3835,
1058   PREFIX_0F3837,
1059   PREFIX_0F3838,
1060   PREFIX_0F3839,
1061   PREFIX_0F383A,
1062   PREFIX_0F383B,
1063   PREFIX_0F383C,
1064   PREFIX_0F383D,
1065   PREFIX_0F383E,
1066   PREFIX_0F383F,
1067   PREFIX_0F3840,
1068   PREFIX_0F3841,
1069   PREFIX_0F3880,
1070   PREFIX_0F3881,
1071   PREFIX_0F3882,
1072   PREFIX_0F38C8,
1073   PREFIX_0F38C9,
1074   PREFIX_0F38CA,
1075   PREFIX_0F38CB,
1076   PREFIX_0F38CC,
1077   PREFIX_0F38CD,
1078   PREFIX_0F38CF,
1079   PREFIX_0F38DB,
1080   PREFIX_0F38DC,
1081   PREFIX_0F38DD,
1082   PREFIX_0F38DE,
1083   PREFIX_0F38DF,
1084   PREFIX_0F38F0,
1085   PREFIX_0F38F1,
1086   PREFIX_0F38F5,
1087   PREFIX_0F38F6,
1088   PREFIX_0F38F8,
1089   PREFIX_0F38F9,
1090   PREFIX_0F3A08,
1091   PREFIX_0F3A09,
1092   PREFIX_0F3A0A,
1093   PREFIX_0F3A0B,
1094   PREFIX_0F3A0C,
1095   PREFIX_0F3A0D,
1096   PREFIX_0F3A0E,
1097   PREFIX_0F3A14,
1098   PREFIX_0F3A15,
1099   PREFIX_0F3A16,
1100   PREFIX_0F3A17,
1101   PREFIX_0F3A20,
1102   PREFIX_0F3A21,
1103   PREFIX_0F3A22,
1104   PREFIX_0F3A40,
1105   PREFIX_0F3A41,
1106   PREFIX_0F3A42,
1107   PREFIX_0F3A44,
1108   PREFIX_0F3A60,
1109   PREFIX_0F3A61,
1110   PREFIX_0F3A62,
1111   PREFIX_0F3A63,
1112   PREFIX_0F3ACC,
1113   PREFIX_0F3ACE,
1114   PREFIX_0F3ACF,
1115   PREFIX_0F3ADF,
1116   PREFIX_VEX_0F10,
1117   PREFIX_VEX_0F11,
1118   PREFIX_VEX_0F12,
1119   PREFIX_VEX_0F16,
1120   PREFIX_VEX_0F2A,
1121   PREFIX_VEX_0F2C,
1122   PREFIX_VEX_0F2D,
1123   PREFIX_VEX_0F2E,
1124   PREFIX_VEX_0F2F,
1125   PREFIX_VEX_0F41,
1126   PREFIX_VEX_0F42,
1127   PREFIX_VEX_0F44,
1128   PREFIX_VEX_0F45,
1129   PREFIX_VEX_0F46,
1130   PREFIX_VEX_0F47,
1131   PREFIX_VEX_0F4A,
1132   PREFIX_VEX_0F4B,
1133   PREFIX_VEX_0F51,
1134   PREFIX_VEX_0F52,
1135   PREFIX_VEX_0F53,
1136   PREFIX_VEX_0F58,
1137   PREFIX_VEX_0F59,
1138   PREFIX_VEX_0F5A,
1139   PREFIX_VEX_0F5B,
1140   PREFIX_VEX_0F5C,
1141   PREFIX_VEX_0F5D,
1142   PREFIX_VEX_0F5E,
1143   PREFIX_VEX_0F5F,
1144   PREFIX_VEX_0F60,
1145   PREFIX_VEX_0F61,
1146   PREFIX_VEX_0F62,
1147   PREFIX_VEX_0F63,
1148   PREFIX_VEX_0F64,
1149   PREFIX_VEX_0F65,
1150   PREFIX_VEX_0F66,
1151   PREFIX_VEX_0F67,
1152   PREFIX_VEX_0F68,
1153   PREFIX_VEX_0F69,
1154   PREFIX_VEX_0F6A,
1155   PREFIX_VEX_0F6B,
1156   PREFIX_VEX_0F6C,
1157   PREFIX_VEX_0F6D,
1158   PREFIX_VEX_0F6E,
1159   PREFIX_VEX_0F6F,
1160   PREFIX_VEX_0F70,
1161   PREFIX_VEX_0F71_REG_2,
1162   PREFIX_VEX_0F71_REG_4,
1163   PREFIX_VEX_0F71_REG_6,
1164   PREFIX_VEX_0F72_REG_2,
1165   PREFIX_VEX_0F72_REG_4,
1166   PREFIX_VEX_0F72_REG_6,
1167   PREFIX_VEX_0F73_REG_2,
1168   PREFIX_VEX_0F73_REG_3,
1169   PREFIX_VEX_0F73_REG_6,
1170   PREFIX_VEX_0F73_REG_7,
1171   PREFIX_VEX_0F74,
1172   PREFIX_VEX_0F75,
1173   PREFIX_VEX_0F76,
1174   PREFIX_VEX_0F77,
1175   PREFIX_VEX_0F7C,
1176   PREFIX_VEX_0F7D,
1177   PREFIX_VEX_0F7E,
1178   PREFIX_VEX_0F7F,
1179   PREFIX_VEX_0F90,
1180   PREFIX_VEX_0F91,
1181   PREFIX_VEX_0F92,
1182   PREFIX_VEX_0F93,
1183   PREFIX_VEX_0F98,
1184   PREFIX_VEX_0F99,
1185   PREFIX_VEX_0FC2,
1186   PREFIX_VEX_0FC4,
1187   PREFIX_VEX_0FC5,
1188   PREFIX_VEX_0FD0,
1189   PREFIX_VEX_0FD1,
1190   PREFIX_VEX_0FD2,
1191   PREFIX_VEX_0FD3,
1192   PREFIX_VEX_0FD4,
1193   PREFIX_VEX_0FD5,
1194   PREFIX_VEX_0FD6,
1195   PREFIX_VEX_0FD7,
1196   PREFIX_VEX_0FD8,
1197   PREFIX_VEX_0FD9,
1198   PREFIX_VEX_0FDA,
1199   PREFIX_VEX_0FDB,
1200   PREFIX_VEX_0FDC,
1201   PREFIX_VEX_0FDD,
1202   PREFIX_VEX_0FDE,
1203   PREFIX_VEX_0FDF,
1204   PREFIX_VEX_0FE0,
1205   PREFIX_VEX_0FE1,
1206   PREFIX_VEX_0FE2,
1207   PREFIX_VEX_0FE3,
1208   PREFIX_VEX_0FE4,
1209   PREFIX_VEX_0FE5,
1210   PREFIX_VEX_0FE6,
1211   PREFIX_VEX_0FE7,
1212   PREFIX_VEX_0FE8,
1213   PREFIX_VEX_0FE9,
1214   PREFIX_VEX_0FEA,
1215   PREFIX_VEX_0FEB,
1216   PREFIX_VEX_0FEC,
1217   PREFIX_VEX_0FED,
1218   PREFIX_VEX_0FEE,
1219   PREFIX_VEX_0FEF,
1220   PREFIX_VEX_0FF0,
1221   PREFIX_VEX_0FF1,
1222   PREFIX_VEX_0FF2,
1223   PREFIX_VEX_0FF3,
1224   PREFIX_VEX_0FF4,
1225   PREFIX_VEX_0FF5,
1226   PREFIX_VEX_0FF6,
1227   PREFIX_VEX_0FF7,
1228   PREFIX_VEX_0FF8,
1229   PREFIX_VEX_0FF9,
1230   PREFIX_VEX_0FFA,
1231   PREFIX_VEX_0FFB,
1232   PREFIX_VEX_0FFC,
1233   PREFIX_VEX_0FFD,
1234   PREFIX_VEX_0FFE,
1235   PREFIX_VEX_0F3800,
1236   PREFIX_VEX_0F3801,
1237   PREFIX_VEX_0F3802,
1238   PREFIX_VEX_0F3803,
1239   PREFIX_VEX_0F3804,
1240   PREFIX_VEX_0F3805,
1241   PREFIX_VEX_0F3806,
1242   PREFIX_VEX_0F3807,
1243   PREFIX_VEX_0F3808,
1244   PREFIX_VEX_0F3809,
1245   PREFIX_VEX_0F380A,
1246   PREFIX_VEX_0F380B,
1247   PREFIX_VEX_0F380C,
1248   PREFIX_VEX_0F380D,
1249   PREFIX_VEX_0F380E,
1250   PREFIX_VEX_0F380F,
1251   PREFIX_VEX_0F3813,
1252   PREFIX_VEX_0F3816,
1253   PREFIX_VEX_0F3817,
1254   PREFIX_VEX_0F3818,
1255   PREFIX_VEX_0F3819,
1256   PREFIX_VEX_0F381A,
1257   PREFIX_VEX_0F381C,
1258   PREFIX_VEX_0F381D,
1259   PREFIX_VEX_0F381E,
1260   PREFIX_VEX_0F3820,
1261   PREFIX_VEX_0F3821,
1262   PREFIX_VEX_0F3822,
1263   PREFIX_VEX_0F3823,
1264   PREFIX_VEX_0F3824,
1265   PREFIX_VEX_0F3825,
1266   PREFIX_VEX_0F3828,
1267   PREFIX_VEX_0F3829,
1268   PREFIX_VEX_0F382A,
1269   PREFIX_VEX_0F382B,
1270   PREFIX_VEX_0F382C,
1271   PREFIX_VEX_0F382D,
1272   PREFIX_VEX_0F382E,
1273   PREFIX_VEX_0F382F,
1274   PREFIX_VEX_0F3830,
1275   PREFIX_VEX_0F3831,
1276   PREFIX_VEX_0F3832,
1277   PREFIX_VEX_0F3833,
1278   PREFIX_VEX_0F3834,
1279   PREFIX_VEX_0F3835,
1280   PREFIX_VEX_0F3836,
1281   PREFIX_VEX_0F3837,
1282   PREFIX_VEX_0F3838,
1283   PREFIX_VEX_0F3839,
1284   PREFIX_VEX_0F383A,
1285   PREFIX_VEX_0F383B,
1286   PREFIX_VEX_0F383C,
1287   PREFIX_VEX_0F383D,
1288   PREFIX_VEX_0F383E,
1289   PREFIX_VEX_0F383F,
1290   PREFIX_VEX_0F3840,
1291   PREFIX_VEX_0F3841,
1292   PREFIX_VEX_0F3845,
1293   PREFIX_VEX_0F3846,
1294   PREFIX_VEX_0F3847,
1295   PREFIX_VEX_0F3849_X86_64,
1296   PREFIX_VEX_0F384B_X86_64,
1297   PREFIX_VEX_0F3858,
1298   PREFIX_VEX_0F3859,
1299   PREFIX_VEX_0F385A,
1300   PREFIX_VEX_0F385C_X86_64,
1301   PREFIX_VEX_0F385E_X86_64,
1302   PREFIX_VEX_0F3878,
1303   PREFIX_VEX_0F3879,
1304   PREFIX_VEX_0F388C,
1305   PREFIX_VEX_0F388E,
1306   PREFIX_VEX_0F3890,
1307   PREFIX_VEX_0F3891,
1308   PREFIX_VEX_0F3892,
1309   PREFIX_VEX_0F3893,
1310   PREFIX_VEX_0F3896,
1311   PREFIX_VEX_0F3897,
1312   PREFIX_VEX_0F3898,
1313   PREFIX_VEX_0F3899,
1314   PREFIX_VEX_0F389A,
1315   PREFIX_VEX_0F389B,
1316   PREFIX_VEX_0F389C,
1317   PREFIX_VEX_0F389D,
1318   PREFIX_VEX_0F389E,
1319   PREFIX_VEX_0F389F,
1320   PREFIX_VEX_0F38A6,
1321   PREFIX_VEX_0F38A7,
1322   PREFIX_VEX_0F38A8,
1323   PREFIX_VEX_0F38A9,
1324   PREFIX_VEX_0F38AA,
1325   PREFIX_VEX_0F38AB,
1326   PREFIX_VEX_0F38AC,
1327   PREFIX_VEX_0F38AD,
1328   PREFIX_VEX_0F38AE,
1329   PREFIX_VEX_0F38AF,
1330   PREFIX_VEX_0F38B6,
1331   PREFIX_VEX_0F38B7,
1332   PREFIX_VEX_0F38B8,
1333   PREFIX_VEX_0F38B9,
1334   PREFIX_VEX_0F38BA,
1335   PREFIX_VEX_0F38BB,
1336   PREFIX_VEX_0F38BC,
1337   PREFIX_VEX_0F38BD,
1338   PREFIX_VEX_0F38BE,
1339   PREFIX_VEX_0F38BF,
1340   PREFIX_VEX_0F38CF,
1341   PREFIX_VEX_0F38DB,
1342   PREFIX_VEX_0F38DC,
1343   PREFIX_VEX_0F38DD,
1344   PREFIX_VEX_0F38DE,
1345   PREFIX_VEX_0F38DF,
1346   PREFIX_VEX_0F38F2,
1347   PREFIX_VEX_0F38F3_REG_1,
1348   PREFIX_VEX_0F38F3_REG_2,
1349   PREFIX_VEX_0F38F3_REG_3,
1350   PREFIX_VEX_0F38F5,
1351   PREFIX_VEX_0F38F6,
1352   PREFIX_VEX_0F38F7,
1353   PREFIX_VEX_0F3A00,
1354   PREFIX_VEX_0F3A01,
1355   PREFIX_VEX_0F3A02,
1356   PREFIX_VEX_0F3A04,
1357   PREFIX_VEX_0F3A05,
1358   PREFIX_VEX_0F3A06,
1359   PREFIX_VEX_0F3A08,
1360   PREFIX_VEX_0F3A09,
1361   PREFIX_VEX_0F3A0A,
1362   PREFIX_VEX_0F3A0B,
1363   PREFIX_VEX_0F3A0C,
1364   PREFIX_VEX_0F3A0D,
1365   PREFIX_VEX_0F3A0E,
1366   PREFIX_VEX_0F3A0F,
1367   PREFIX_VEX_0F3A14,
1368   PREFIX_VEX_0F3A15,
1369   PREFIX_VEX_0F3A16,
1370   PREFIX_VEX_0F3A17,
1371   PREFIX_VEX_0F3A18,
1372   PREFIX_VEX_0F3A19,
1373   PREFIX_VEX_0F3A1D,
1374   PREFIX_VEX_0F3A20,
1375   PREFIX_VEX_0F3A21,
1376   PREFIX_VEX_0F3A22,
1377   PREFIX_VEX_0F3A30,
1378   PREFIX_VEX_0F3A31,
1379   PREFIX_VEX_0F3A32,
1380   PREFIX_VEX_0F3A33,
1381   PREFIX_VEX_0F3A38,
1382   PREFIX_VEX_0F3A39,
1383   PREFIX_VEX_0F3A40,
1384   PREFIX_VEX_0F3A41,
1385   PREFIX_VEX_0F3A42,
1386   PREFIX_VEX_0F3A44,
1387   PREFIX_VEX_0F3A46,
1388   PREFIX_VEX_0F3A48,
1389   PREFIX_VEX_0F3A49,
1390   PREFIX_VEX_0F3A4A,
1391   PREFIX_VEX_0F3A4B,
1392   PREFIX_VEX_0F3A4C,
1393   PREFIX_VEX_0F3A5C,
1394   PREFIX_VEX_0F3A5D,
1395   PREFIX_VEX_0F3A5E,
1396   PREFIX_VEX_0F3A5F,
1397   PREFIX_VEX_0F3A60,
1398   PREFIX_VEX_0F3A61,
1399   PREFIX_VEX_0F3A62,
1400   PREFIX_VEX_0F3A63,
1401   PREFIX_VEX_0F3A68,
1402   PREFIX_VEX_0F3A69,
1403   PREFIX_VEX_0F3A6A,
1404   PREFIX_VEX_0F3A6B,
1405   PREFIX_VEX_0F3A6C,
1406   PREFIX_VEX_0F3A6D,
1407   PREFIX_VEX_0F3A6E,
1408   PREFIX_VEX_0F3A6F,
1409   PREFIX_VEX_0F3A78,
1410   PREFIX_VEX_0F3A79,
1411   PREFIX_VEX_0F3A7A,
1412   PREFIX_VEX_0F3A7B,
1413   PREFIX_VEX_0F3A7C,
1414   PREFIX_VEX_0F3A7D,
1415   PREFIX_VEX_0F3A7E,
1416   PREFIX_VEX_0F3A7F,
1417   PREFIX_VEX_0F3ACE,
1418   PREFIX_VEX_0F3ACF,
1419   PREFIX_VEX_0F3ADF,
1420   PREFIX_VEX_0F3AF0,
1421
1422   PREFIX_EVEX_0F10,
1423   PREFIX_EVEX_0F11,
1424   PREFIX_EVEX_0F12,
1425   PREFIX_EVEX_0F16,
1426   PREFIX_EVEX_0F2A,
1427   PREFIX_EVEX_0F2C,
1428   PREFIX_EVEX_0F2D,
1429   PREFIX_EVEX_0F2E,
1430   PREFIX_EVEX_0F2F,
1431   PREFIX_EVEX_0F51,
1432   PREFIX_EVEX_0F58,
1433   PREFIX_EVEX_0F59,
1434   PREFIX_EVEX_0F5A,
1435   PREFIX_EVEX_0F5B,
1436   PREFIX_EVEX_0F5C,
1437   PREFIX_EVEX_0F5D,
1438   PREFIX_EVEX_0F5E,
1439   PREFIX_EVEX_0F5F,
1440   PREFIX_EVEX_0F64,
1441   PREFIX_EVEX_0F65,
1442   PREFIX_EVEX_0F66,
1443   PREFIX_EVEX_0F6E,
1444   PREFIX_EVEX_0F6F,
1445   PREFIX_EVEX_0F70,
1446   PREFIX_EVEX_0F71_REG_2,
1447   PREFIX_EVEX_0F71_REG_4,
1448   PREFIX_EVEX_0F71_REG_6,
1449   PREFIX_EVEX_0F72_REG_0,
1450   PREFIX_EVEX_0F72_REG_1,
1451   PREFIX_EVEX_0F72_REG_2,
1452   PREFIX_EVEX_0F72_REG_4,
1453   PREFIX_EVEX_0F72_REG_6,
1454   PREFIX_EVEX_0F73_REG_2,
1455   PREFIX_EVEX_0F73_REG_3,
1456   PREFIX_EVEX_0F73_REG_6,
1457   PREFIX_EVEX_0F73_REG_7,
1458   PREFIX_EVEX_0F74,
1459   PREFIX_EVEX_0F75,
1460   PREFIX_EVEX_0F76,
1461   PREFIX_EVEX_0F78,
1462   PREFIX_EVEX_0F79,
1463   PREFIX_EVEX_0F7A,
1464   PREFIX_EVEX_0F7B,
1465   PREFIX_EVEX_0F7E,
1466   PREFIX_EVEX_0F7F,
1467   PREFIX_EVEX_0FC2,
1468   PREFIX_EVEX_0FC4,
1469   PREFIX_EVEX_0FC5,
1470   PREFIX_EVEX_0FD6,
1471   PREFIX_EVEX_0FDB,
1472   PREFIX_EVEX_0FDF,
1473   PREFIX_EVEX_0FE2,
1474   PREFIX_EVEX_0FE6,
1475   PREFIX_EVEX_0FE7,
1476   PREFIX_EVEX_0FEB,
1477   PREFIX_EVEX_0FEF,
1478   PREFIX_EVEX_0F380D,
1479   PREFIX_EVEX_0F3810,
1480   PREFIX_EVEX_0F3811,
1481   PREFIX_EVEX_0F3812,
1482   PREFIX_EVEX_0F3813,
1483   PREFIX_EVEX_0F3814,
1484   PREFIX_EVEX_0F3815,
1485   PREFIX_EVEX_0F3816,
1486   PREFIX_EVEX_0F3819,
1487   PREFIX_EVEX_0F381A,
1488   PREFIX_EVEX_0F381B,
1489   PREFIX_EVEX_0F381E,
1490   PREFIX_EVEX_0F381F,
1491   PREFIX_EVEX_0F3820,
1492   PREFIX_EVEX_0F3821,
1493   PREFIX_EVEX_0F3822,
1494   PREFIX_EVEX_0F3823,
1495   PREFIX_EVEX_0F3824,
1496   PREFIX_EVEX_0F3825,
1497   PREFIX_EVEX_0F3826,
1498   PREFIX_EVEX_0F3827,
1499   PREFIX_EVEX_0F3828,
1500   PREFIX_EVEX_0F3829,
1501   PREFIX_EVEX_0F382A,
1502   PREFIX_EVEX_0F382C,
1503   PREFIX_EVEX_0F382D,
1504   PREFIX_EVEX_0F3830,
1505   PREFIX_EVEX_0F3831,
1506   PREFIX_EVEX_0F3832,
1507   PREFIX_EVEX_0F3833,
1508   PREFIX_EVEX_0F3834,
1509   PREFIX_EVEX_0F3835,
1510   PREFIX_EVEX_0F3836,
1511   PREFIX_EVEX_0F3837,
1512   PREFIX_EVEX_0F3838,
1513   PREFIX_EVEX_0F3839,
1514   PREFIX_EVEX_0F383A,
1515   PREFIX_EVEX_0F383B,
1516   PREFIX_EVEX_0F383D,
1517   PREFIX_EVEX_0F383F,
1518   PREFIX_EVEX_0F3840,
1519   PREFIX_EVEX_0F3842,
1520   PREFIX_EVEX_0F3843,
1521   PREFIX_EVEX_0F3844,
1522   PREFIX_EVEX_0F3845,
1523   PREFIX_EVEX_0F3846,
1524   PREFIX_EVEX_0F3847,
1525   PREFIX_EVEX_0F384C,
1526   PREFIX_EVEX_0F384D,
1527   PREFIX_EVEX_0F384E,
1528   PREFIX_EVEX_0F384F,
1529   PREFIX_EVEX_0F3850,
1530   PREFIX_EVEX_0F3851,
1531   PREFIX_EVEX_0F3852,
1532   PREFIX_EVEX_0F3853,
1533   PREFIX_EVEX_0F3854,
1534   PREFIX_EVEX_0F3855,
1535   PREFIX_EVEX_0F3859,
1536   PREFIX_EVEX_0F385A,
1537   PREFIX_EVEX_0F385B,
1538   PREFIX_EVEX_0F3862,
1539   PREFIX_EVEX_0F3863,
1540   PREFIX_EVEX_0F3864,
1541   PREFIX_EVEX_0F3865,
1542   PREFIX_EVEX_0F3866,
1543   PREFIX_EVEX_0F3868,
1544   PREFIX_EVEX_0F3870,
1545   PREFIX_EVEX_0F3871,
1546   PREFIX_EVEX_0F3872,
1547   PREFIX_EVEX_0F3873,
1548   PREFIX_EVEX_0F3875,
1549   PREFIX_EVEX_0F3876,
1550   PREFIX_EVEX_0F3877,
1551   PREFIX_EVEX_0F387A,
1552   PREFIX_EVEX_0F387B,
1553   PREFIX_EVEX_0F387C,
1554   PREFIX_EVEX_0F387D,
1555   PREFIX_EVEX_0F387E,
1556   PREFIX_EVEX_0F387F,
1557   PREFIX_EVEX_0F3883,
1558   PREFIX_EVEX_0F3888,
1559   PREFIX_EVEX_0F3889,
1560   PREFIX_EVEX_0F388A,
1561   PREFIX_EVEX_0F388B,
1562   PREFIX_EVEX_0F388D,
1563   PREFIX_EVEX_0F388F,
1564   PREFIX_EVEX_0F3890,
1565   PREFIX_EVEX_0F3891,
1566   PREFIX_EVEX_0F3892,
1567   PREFIX_EVEX_0F3893,
1568   PREFIX_EVEX_0F389A,
1569   PREFIX_EVEX_0F389B,
1570   PREFIX_EVEX_0F38A0,
1571   PREFIX_EVEX_0F38A1,
1572   PREFIX_EVEX_0F38A2,
1573   PREFIX_EVEX_0F38A3,
1574   PREFIX_EVEX_0F38AA,
1575   PREFIX_EVEX_0F38AB,
1576   PREFIX_EVEX_0F38B4,
1577   PREFIX_EVEX_0F38B5,
1578   PREFIX_EVEX_0F38C4,
1579   PREFIX_EVEX_0F38C6_REG_1,
1580   PREFIX_EVEX_0F38C6_REG_2,
1581   PREFIX_EVEX_0F38C6_REG_5,
1582   PREFIX_EVEX_0F38C6_REG_6,
1583   PREFIX_EVEX_0F38C7_REG_1,
1584   PREFIX_EVEX_0F38C7_REG_2,
1585   PREFIX_EVEX_0F38C7_REG_5,
1586   PREFIX_EVEX_0F38C7_REG_6,
1587   PREFIX_EVEX_0F38C8,
1588   PREFIX_EVEX_0F38CA,
1589   PREFIX_EVEX_0F38CB,
1590   PREFIX_EVEX_0F38CC,
1591   PREFIX_EVEX_0F38CD,
1592
1593   PREFIX_EVEX_0F3A00,
1594   PREFIX_EVEX_0F3A01,
1595   PREFIX_EVEX_0F3A03,
1596   PREFIX_EVEX_0F3A05,
1597   PREFIX_EVEX_0F3A08,
1598   PREFIX_EVEX_0F3A09,
1599   PREFIX_EVEX_0F3A0A,
1600   PREFIX_EVEX_0F3A0B,
1601   PREFIX_EVEX_0F3A14,
1602   PREFIX_EVEX_0F3A15,
1603   PREFIX_EVEX_0F3A16,
1604   PREFIX_EVEX_0F3A17,
1605   PREFIX_EVEX_0F3A18,
1606   PREFIX_EVEX_0F3A19,
1607   PREFIX_EVEX_0F3A1A,
1608   PREFIX_EVEX_0F3A1B,
1609   PREFIX_EVEX_0F3A1E,
1610   PREFIX_EVEX_0F3A1F,
1611   PREFIX_EVEX_0F3A20,
1612   PREFIX_EVEX_0F3A21,
1613   PREFIX_EVEX_0F3A22,
1614   PREFIX_EVEX_0F3A23,
1615   PREFIX_EVEX_0F3A25,
1616   PREFIX_EVEX_0F3A26,
1617   PREFIX_EVEX_0F3A27,
1618   PREFIX_EVEX_0F3A38,
1619   PREFIX_EVEX_0F3A39,
1620   PREFIX_EVEX_0F3A3A,
1621   PREFIX_EVEX_0F3A3B,
1622   PREFIX_EVEX_0F3A3E,
1623   PREFIX_EVEX_0F3A3F,
1624   PREFIX_EVEX_0F3A42,
1625   PREFIX_EVEX_0F3A43,
1626   PREFIX_EVEX_0F3A50,
1627   PREFIX_EVEX_0F3A51,
1628   PREFIX_EVEX_0F3A54,
1629   PREFIX_EVEX_0F3A55,
1630   PREFIX_EVEX_0F3A56,
1631   PREFIX_EVEX_0F3A57,
1632   PREFIX_EVEX_0F3A66,
1633   PREFIX_EVEX_0F3A67,
1634   PREFIX_EVEX_0F3A70,
1635   PREFIX_EVEX_0F3A71,
1636   PREFIX_EVEX_0F3A72,
1637   PREFIX_EVEX_0F3A73,
1638 };
1639
1640 enum
1641 {
1642   X86_64_06 = 0,
1643   X86_64_07,
1644   X86_64_0E,
1645   X86_64_16,
1646   X86_64_17,
1647   X86_64_1E,
1648   X86_64_1F,
1649   X86_64_27,
1650   X86_64_2F,
1651   X86_64_37,
1652   X86_64_3F,
1653   X86_64_60,
1654   X86_64_61,
1655   X86_64_62,
1656   X86_64_63,
1657   X86_64_6D,
1658   X86_64_6F,
1659   X86_64_82,
1660   X86_64_9A,
1661   X86_64_C2,
1662   X86_64_C3,
1663   X86_64_C4,
1664   X86_64_C5,
1665   X86_64_CE,
1666   X86_64_D4,
1667   X86_64_D5,
1668   X86_64_E8,
1669   X86_64_E9,
1670   X86_64_EA,
1671   X86_64_0F01_REG_0,
1672   X86_64_0F01_REG_1,
1673   X86_64_0F01_REG_2,
1674   X86_64_0F01_REG_3,
1675   X86_64_VEX_0F3849,
1676   X86_64_VEX_0F384B,
1677   X86_64_VEX_0F385C,
1678   X86_64_VEX_0F385E
1679 };
1680
1681 enum
1682 {
1683   THREE_BYTE_0F38 = 0,
1684   THREE_BYTE_0F3A
1685 };
1686
1687 enum
1688 {
1689   XOP_08 = 0,
1690   XOP_09,
1691   XOP_0A
1692 };
1693
1694 enum
1695 {
1696   VEX_0F = 0,
1697   VEX_0F38,
1698   VEX_0F3A
1699 };
1700
1701 enum
1702 {
1703   EVEX_0F = 0,
1704   EVEX_0F38,
1705   EVEX_0F3A
1706 };
1707
1708 enum
1709 {
1710   VEX_LEN_0F12_P_0_M_0 = 0,
1711   VEX_LEN_0F12_P_0_M_1,
1712 #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0
1713   VEX_LEN_0F13_M_0,
1714   VEX_LEN_0F16_P_0_M_0,
1715   VEX_LEN_0F16_P_0_M_1,
1716 #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0
1717   VEX_LEN_0F17_M_0,
1718   VEX_LEN_0F41_P_0,
1719   VEX_LEN_0F41_P_2,
1720   VEX_LEN_0F42_P_0,
1721   VEX_LEN_0F42_P_2,
1722   VEX_LEN_0F44_P_0,
1723   VEX_LEN_0F44_P_2,
1724   VEX_LEN_0F45_P_0,
1725   VEX_LEN_0F45_P_2,
1726   VEX_LEN_0F46_P_0,
1727   VEX_LEN_0F46_P_2,
1728   VEX_LEN_0F47_P_0,
1729   VEX_LEN_0F47_P_2,
1730   VEX_LEN_0F4A_P_0,
1731   VEX_LEN_0F4A_P_2,
1732   VEX_LEN_0F4B_P_0,
1733   VEX_LEN_0F4B_P_2,
1734   VEX_LEN_0F6E_P_2,
1735   VEX_LEN_0F77_P_0,
1736   VEX_LEN_0F7E_P_1,
1737   VEX_LEN_0F7E_P_2,
1738   VEX_LEN_0F90_P_0,
1739   VEX_LEN_0F90_P_2,
1740   VEX_LEN_0F91_P_0,
1741   VEX_LEN_0F91_P_2,
1742   VEX_LEN_0F92_P_0,
1743   VEX_LEN_0F92_P_2,
1744   VEX_LEN_0F92_P_3,
1745   VEX_LEN_0F93_P_0,
1746   VEX_LEN_0F93_P_2,
1747   VEX_LEN_0F93_P_3,
1748   VEX_LEN_0F98_P_0,
1749   VEX_LEN_0F98_P_2,
1750   VEX_LEN_0F99_P_0,
1751   VEX_LEN_0F99_P_2,
1752   VEX_LEN_0FAE_R_2_M_0,
1753   VEX_LEN_0FAE_R_3_M_0,
1754   VEX_LEN_0FC4_P_2,
1755   VEX_LEN_0FC5_P_2,
1756   VEX_LEN_0FD6_P_2,
1757   VEX_LEN_0FF7_P_2,
1758   VEX_LEN_0F3816_P_2,
1759   VEX_LEN_0F3819_P_2,
1760   VEX_LEN_0F381A_P_2_M_0,
1761   VEX_LEN_0F3836_P_2,
1762   VEX_LEN_0F3841_P_2,
1763   VEX_LEN_0F3849_X86_64_P_0_W_0_M_0,
1764   VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0,
1765   VEX_LEN_0F3849_X86_64_P_2_W_0_M_0,
1766   VEX_LEN_0F3849_X86_64_P_3_W_0_M_0,
1767   VEX_LEN_0F384B_X86_64_P_1_W_0_M_0,
1768   VEX_LEN_0F384B_X86_64_P_2_W_0_M_0,
1769   VEX_LEN_0F384B_X86_64_P_3_W_0_M_0,
1770   VEX_LEN_0F385A_P_2_M_0,
1771   VEX_LEN_0F385C_X86_64_P_1_W_0_M_0,
1772   VEX_LEN_0F385E_X86_64_P_0_W_0_M_0,
1773   VEX_LEN_0F385E_X86_64_P_1_W_0_M_0,
1774   VEX_LEN_0F385E_X86_64_P_2_W_0_M_0,
1775   VEX_LEN_0F385E_X86_64_P_3_W_0_M_0,
1776   VEX_LEN_0F38DB_P_2,
1777   VEX_LEN_0F38F2_P_0,
1778   VEX_LEN_0F38F3_R_1_P_0,
1779   VEX_LEN_0F38F3_R_2_P_0,
1780   VEX_LEN_0F38F3_R_3_P_0,
1781   VEX_LEN_0F38F5_P_0,
1782   VEX_LEN_0F38F5_P_1,
1783   VEX_LEN_0F38F5_P_3,
1784   VEX_LEN_0F38F6_P_3,
1785   VEX_LEN_0F38F7_P_0,
1786   VEX_LEN_0F38F7_P_1,
1787   VEX_LEN_0F38F7_P_2,
1788   VEX_LEN_0F38F7_P_3,
1789   VEX_LEN_0F3A00_P_2,
1790   VEX_LEN_0F3A01_P_2,
1791   VEX_LEN_0F3A06_P_2,
1792   VEX_LEN_0F3A14_P_2,
1793   VEX_LEN_0F3A15_P_2,
1794   VEX_LEN_0F3A16_P_2,
1795   VEX_LEN_0F3A17_P_2,
1796   VEX_LEN_0F3A18_P_2,
1797   VEX_LEN_0F3A19_P_2,
1798   VEX_LEN_0F3A20_P_2,
1799   VEX_LEN_0F3A21_P_2,
1800   VEX_LEN_0F3A22_P_2,
1801   VEX_LEN_0F3A30_P_2,
1802   VEX_LEN_0F3A31_P_2,
1803   VEX_LEN_0F3A32_P_2,
1804   VEX_LEN_0F3A33_P_2,
1805   VEX_LEN_0F3A38_P_2,
1806   VEX_LEN_0F3A39_P_2,
1807   VEX_LEN_0F3A41_P_2,
1808   VEX_LEN_0F3A46_P_2,
1809   VEX_LEN_0F3A60_P_2,
1810   VEX_LEN_0F3A61_P_2,
1811   VEX_LEN_0F3A62_P_2,
1812   VEX_LEN_0F3A63_P_2,
1813   VEX_LEN_0F3ADF_P_2,
1814   VEX_LEN_0F3AF0_P_3,
1815   VEX_LEN_0FXOP_08_85,
1816   VEX_LEN_0FXOP_08_86,
1817   VEX_LEN_0FXOP_08_87,
1818   VEX_LEN_0FXOP_08_8E,
1819   VEX_LEN_0FXOP_08_8F,
1820   VEX_LEN_0FXOP_08_95,
1821   VEX_LEN_0FXOP_08_96,
1822   VEX_LEN_0FXOP_08_97,
1823   VEX_LEN_0FXOP_08_9E,
1824   VEX_LEN_0FXOP_08_9F,
1825   VEX_LEN_0FXOP_08_A3,
1826   VEX_LEN_0FXOP_08_A6,
1827   VEX_LEN_0FXOP_08_B6,
1828   VEX_LEN_0FXOP_08_C0,
1829   VEX_LEN_0FXOP_08_C1,
1830   VEX_LEN_0FXOP_08_C2,
1831   VEX_LEN_0FXOP_08_C3,
1832   VEX_LEN_0FXOP_08_CC,
1833   VEX_LEN_0FXOP_08_CD,
1834   VEX_LEN_0FXOP_08_CE,
1835   VEX_LEN_0FXOP_08_CF,
1836   VEX_LEN_0FXOP_08_EC,
1837   VEX_LEN_0FXOP_08_ED,
1838   VEX_LEN_0FXOP_08_EE,
1839   VEX_LEN_0FXOP_08_EF,
1840   VEX_LEN_0FXOP_09_01,
1841   VEX_LEN_0FXOP_09_02,
1842   VEX_LEN_0FXOP_09_12_M_1,
1843   VEX_LEN_0FXOP_09_82_W_0,
1844   VEX_LEN_0FXOP_09_83_W_0,
1845   VEX_LEN_0FXOP_09_90,
1846   VEX_LEN_0FXOP_09_91,
1847   VEX_LEN_0FXOP_09_92,
1848   VEX_LEN_0FXOP_09_93,
1849   VEX_LEN_0FXOP_09_94,
1850   VEX_LEN_0FXOP_09_95,
1851   VEX_LEN_0FXOP_09_96,
1852   VEX_LEN_0FXOP_09_97,
1853   VEX_LEN_0FXOP_09_98,
1854   VEX_LEN_0FXOP_09_99,
1855   VEX_LEN_0FXOP_09_9A,
1856   VEX_LEN_0FXOP_09_9B,
1857   VEX_LEN_0FXOP_09_C1,
1858   VEX_LEN_0FXOP_09_C2,
1859   VEX_LEN_0FXOP_09_C3,
1860   VEX_LEN_0FXOP_09_C6,
1861   VEX_LEN_0FXOP_09_C7,
1862   VEX_LEN_0FXOP_09_CB,
1863   VEX_LEN_0FXOP_09_D1,
1864   VEX_LEN_0FXOP_09_D2,
1865   VEX_LEN_0FXOP_09_D3,
1866   VEX_LEN_0FXOP_09_D6,
1867   VEX_LEN_0FXOP_09_D7,
1868   VEX_LEN_0FXOP_09_DB,
1869   VEX_LEN_0FXOP_09_E1,
1870   VEX_LEN_0FXOP_09_E2,
1871   VEX_LEN_0FXOP_09_E3,
1872   VEX_LEN_0FXOP_0A_12,
1873 };
1874
1875 enum
1876 {
1877   EVEX_LEN_0F6E_P_2 = 0,
1878   EVEX_LEN_0F7E_P_1,
1879   EVEX_LEN_0F7E_P_2,
1880   EVEX_LEN_0FC4_P_2,
1881   EVEX_LEN_0FC5_P_2,
1882   EVEX_LEN_0FD6_P_2,
1883   EVEX_LEN_0F3816_P_2,
1884   EVEX_LEN_0F3819_P_2_W_0,
1885   EVEX_LEN_0F3819_P_2_W_1,
1886   EVEX_LEN_0F381A_P_2_W_0_M_0,
1887   EVEX_LEN_0F381A_P_2_W_1_M_0,
1888   EVEX_LEN_0F381B_P_2_W_0_M_0,
1889   EVEX_LEN_0F381B_P_2_W_1_M_0,
1890   EVEX_LEN_0F3836_P_2,
1891   EVEX_LEN_0F385A_P_2_W_0_M_0,
1892   EVEX_LEN_0F385A_P_2_W_1_M_0,
1893   EVEX_LEN_0F385B_P_2_W_0_M_0,
1894   EVEX_LEN_0F385B_P_2_W_1_M_0,
1895   EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1896   EVEX_LEN_0F38C6_REG_2_PREFIX_2,
1897   EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1898   EVEX_LEN_0F38C6_REG_6_PREFIX_2,
1899   EVEX_LEN_0F38C7_R_1_P_2_W_0,
1900   EVEX_LEN_0F38C7_R_1_P_2_W_1,
1901   EVEX_LEN_0F38C7_R_2_P_2_W_0,
1902   EVEX_LEN_0F38C7_R_2_P_2_W_1,
1903   EVEX_LEN_0F38C7_R_5_P_2_W_0,
1904   EVEX_LEN_0F38C7_R_5_P_2_W_1,
1905   EVEX_LEN_0F38C7_R_6_P_2_W_0,
1906   EVEX_LEN_0F38C7_R_6_P_2_W_1,
1907   EVEX_LEN_0F3A00_P_2_W_1,
1908   EVEX_LEN_0F3A01_P_2_W_1,
1909   EVEX_LEN_0F3A14_P_2,
1910   EVEX_LEN_0F3A15_P_2,
1911   EVEX_LEN_0F3A16_P_2,
1912   EVEX_LEN_0F3A17_P_2,
1913   EVEX_LEN_0F3A18_P_2_W_0,
1914   EVEX_LEN_0F3A18_P_2_W_1,
1915   EVEX_LEN_0F3A19_P_2_W_0,
1916   EVEX_LEN_0F3A19_P_2_W_1,
1917   EVEX_LEN_0F3A1A_P_2_W_0,
1918   EVEX_LEN_0F3A1A_P_2_W_1,
1919   EVEX_LEN_0F3A1B_P_2_W_0,
1920   EVEX_LEN_0F3A1B_P_2_W_1,
1921   EVEX_LEN_0F3A20_P_2,
1922   EVEX_LEN_0F3A21_P_2_W_0,
1923   EVEX_LEN_0F3A22_P_2,
1924   EVEX_LEN_0F3A23_P_2_W_0,
1925   EVEX_LEN_0F3A23_P_2_W_1,
1926   EVEX_LEN_0F3A38_P_2_W_0,
1927   EVEX_LEN_0F3A38_P_2_W_1,
1928   EVEX_LEN_0F3A39_P_2_W_0,
1929   EVEX_LEN_0F3A39_P_2_W_1,
1930   EVEX_LEN_0F3A3A_P_2_W_0,
1931   EVEX_LEN_0F3A3A_P_2_W_1,
1932   EVEX_LEN_0F3A3B_P_2_W_0,
1933   EVEX_LEN_0F3A3B_P_2_W_1,
1934   EVEX_LEN_0F3A43_P_2_W_0,
1935   EVEX_LEN_0F3A43_P_2_W_1
1936 };
1937
1938 enum
1939 {
1940   VEX_W_0F41_P_0_LEN_1 = 0,
1941   VEX_W_0F41_P_2_LEN_1,
1942   VEX_W_0F42_P_0_LEN_1,
1943   VEX_W_0F42_P_2_LEN_1,
1944   VEX_W_0F44_P_0_LEN_0,
1945   VEX_W_0F44_P_2_LEN_0,
1946   VEX_W_0F45_P_0_LEN_1,
1947   VEX_W_0F45_P_2_LEN_1,
1948   VEX_W_0F46_P_0_LEN_1,
1949   VEX_W_0F46_P_2_LEN_1,
1950   VEX_W_0F47_P_0_LEN_1,
1951   VEX_W_0F47_P_2_LEN_1,
1952   VEX_W_0F4A_P_0_LEN_1,
1953   VEX_W_0F4A_P_2_LEN_1,
1954   VEX_W_0F4B_P_0_LEN_1,
1955   VEX_W_0F4B_P_2_LEN_1,
1956   VEX_W_0F90_P_0_LEN_0,
1957   VEX_W_0F90_P_2_LEN_0,
1958   VEX_W_0F91_P_0_LEN_0,
1959   VEX_W_0F91_P_2_LEN_0,
1960   VEX_W_0F92_P_0_LEN_0,
1961   VEX_W_0F92_P_2_LEN_0,
1962   VEX_W_0F93_P_0_LEN_0,
1963   VEX_W_0F93_P_2_LEN_0,
1964   VEX_W_0F98_P_0_LEN_0,
1965   VEX_W_0F98_P_2_LEN_0,
1966   VEX_W_0F99_P_0_LEN_0,
1967   VEX_W_0F99_P_2_LEN_0,
1968   VEX_W_0F380C_P_2,
1969   VEX_W_0F380D_P_2,
1970   VEX_W_0F380E_P_2,
1971   VEX_W_0F380F_P_2,
1972   VEX_W_0F3813_P_2,
1973   VEX_W_0F3816_P_2,
1974   VEX_W_0F3818_P_2,
1975   VEX_W_0F3819_P_2,
1976   VEX_W_0F381A_P_2_M_0,
1977   VEX_W_0F382C_P_2_M_0,
1978   VEX_W_0F382D_P_2_M_0,
1979   VEX_W_0F382E_P_2_M_0,
1980   VEX_W_0F382F_P_2_M_0,
1981   VEX_W_0F3836_P_2,
1982   VEX_W_0F3846_P_2,
1983   VEX_W_0F3849_X86_64_P_0,
1984   VEX_W_0F3849_X86_64_P_2,
1985   VEX_W_0F3849_X86_64_P_3,
1986   VEX_W_0F384B_X86_64_P_1,
1987   VEX_W_0F384B_X86_64_P_2,
1988   VEX_W_0F384B_X86_64_P_3,
1989   VEX_W_0F3858_P_2,
1990   VEX_W_0F3859_P_2,
1991   VEX_W_0F385A_P_2_M_0,
1992   VEX_W_0F385C_X86_64_P_1,
1993   VEX_W_0F385E_X86_64_P_0,
1994   VEX_W_0F385E_X86_64_P_1,
1995   VEX_W_0F385E_X86_64_P_2,
1996   VEX_W_0F385E_X86_64_P_3,
1997   VEX_W_0F3878_P_2,
1998   VEX_W_0F3879_P_2,
1999   VEX_W_0F38CF_P_2,
2000   VEX_W_0F3A00_P_2,
2001   VEX_W_0F3A01_P_2,
2002   VEX_W_0F3A02_P_2,
2003   VEX_W_0F3A04_P_2,
2004   VEX_W_0F3A05_P_2,
2005   VEX_W_0F3A06_P_2,
2006   VEX_W_0F3A18_P_2,
2007   VEX_W_0F3A19_P_2,
2008   VEX_W_0F3A1D_P_2,
2009   VEX_W_0F3A30_P_2_LEN_0,
2010   VEX_W_0F3A31_P_2_LEN_0,
2011   VEX_W_0F3A32_P_2_LEN_0,
2012   VEX_W_0F3A33_P_2_LEN_0,
2013   VEX_W_0F3A38_P_2,
2014   VEX_W_0F3A39_P_2,
2015   VEX_W_0F3A46_P_2,
2016   VEX_W_0F3A4A_P_2,
2017   VEX_W_0F3A4B_P_2,
2018   VEX_W_0F3A4C_P_2,
2019   VEX_W_0F3ACE_P_2,
2020   VEX_W_0F3ACF_P_2,
2021
2022   VEX_W_0FXOP_08_85_L_0,
2023   VEX_W_0FXOP_08_86_L_0,
2024   VEX_W_0FXOP_08_87_L_0,
2025   VEX_W_0FXOP_08_8E_L_0,
2026   VEX_W_0FXOP_08_8F_L_0,
2027   VEX_W_0FXOP_08_95_L_0,
2028   VEX_W_0FXOP_08_96_L_0,
2029   VEX_W_0FXOP_08_97_L_0,
2030   VEX_W_0FXOP_08_9E_L_0,
2031   VEX_W_0FXOP_08_9F_L_0,
2032   VEX_W_0FXOP_08_A6_L_0,
2033   VEX_W_0FXOP_08_B6_L_0,
2034   VEX_W_0FXOP_08_C0_L_0,
2035   VEX_W_0FXOP_08_C1_L_0,
2036   VEX_W_0FXOP_08_C2_L_0,
2037   VEX_W_0FXOP_08_C3_L_0,
2038   VEX_W_0FXOP_08_CC_L_0,
2039   VEX_W_0FXOP_08_CD_L_0,
2040   VEX_W_0FXOP_08_CE_L_0,
2041   VEX_W_0FXOP_08_CF_L_0,
2042   VEX_W_0FXOP_08_EC_L_0,
2043   VEX_W_0FXOP_08_ED_L_0,
2044   VEX_W_0FXOP_08_EE_L_0,
2045   VEX_W_0FXOP_08_EF_L_0,
2046
2047   VEX_W_0FXOP_09_80,
2048   VEX_W_0FXOP_09_81,
2049   VEX_W_0FXOP_09_82,
2050   VEX_W_0FXOP_09_83,
2051   VEX_W_0FXOP_09_C1_L_0,
2052   VEX_W_0FXOP_09_C2_L_0,
2053   VEX_W_0FXOP_09_C3_L_0,
2054   VEX_W_0FXOP_09_C6_L_0,
2055   VEX_W_0FXOP_09_C7_L_0,
2056   VEX_W_0FXOP_09_CB_L_0,
2057   VEX_W_0FXOP_09_D1_L_0,
2058   VEX_W_0FXOP_09_D2_L_0,
2059   VEX_W_0FXOP_09_D3_L_0,
2060   VEX_W_0FXOP_09_D6_L_0,
2061   VEX_W_0FXOP_09_D7_L_0,
2062   VEX_W_0FXOP_09_DB_L_0,
2063   VEX_W_0FXOP_09_E1_L_0,
2064   VEX_W_0FXOP_09_E2_L_0,
2065   VEX_W_0FXOP_09_E3_L_0,
2066
2067   EVEX_W_0F10_P_1,
2068   EVEX_W_0F10_P_3,
2069   EVEX_W_0F11_P_1,
2070   EVEX_W_0F11_P_3,
2071   EVEX_W_0F12_P_0_M_1,
2072   EVEX_W_0F12_P_1,
2073   EVEX_W_0F12_P_3,
2074   EVEX_W_0F16_P_0_M_1,
2075   EVEX_W_0F16_P_1,
2076   EVEX_W_0F2A_P_3,
2077   EVEX_W_0F51_P_1,
2078   EVEX_W_0F51_P_3,
2079   EVEX_W_0F58_P_1,
2080   EVEX_W_0F58_P_3,
2081   EVEX_W_0F59_P_1,
2082   EVEX_W_0F59_P_3,
2083   EVEX_W_0F5A_P_0,
2084   EVEX_W_0F5A_P_1,
2085   EVEX_W_0F5A_P_2,
2086   EVEX_W_0F5A_P_3,
2087   EVEX_W_0F5B_P_0,
2088   EVEX_W_0F5B_P_1,
2089   EVEX_W_0F5B_P_2,
2090   EVEX_W_0F5C_P_1,
2091   EVEX_W_0F5C_P_3,
2092   EVEX_W_0F5D_P_1,
2093   EVEX_W_0F5D_P_3,
2094   EVEX_W_0F5E_P_1,
2095   EVEX_W_0F5E_P_3,
2096   EVEX_W_0F5F_P_1,
2097   EVEX_W_0F5F_P_3,
2098   EVEX_W_0F62,
2099   EVEX_W_0F66_P_2,
2100   EVEX_W_0F6A,
2101   EVEX_W_0F6B,
2102   EVEX_W_0F6C,
2103   EVEX_W_0F6D,
2104   EVEX_W_0F6F_P_1,
2105   EVEX_W_0F6F_P_2,
2106   EVEX_W_0F6F_P_3,
2107   EVEX_W_0F70_P_2,
2108   EVEX_W_0F72_R_2_P_2,
2109   EVEX_W_0F72_R_6_P_2,
2110   EVEX_W_0F73_R_2_P_2,
2111   EVEX_W_0F73_R_6_P_2,
2112   EVEX_W_0F76_P_2,
2113   EVEX_W_0F78_P_0,
2114   EVEX_W_0F78_P_2,
2115   EVEX_W_0F79_P_0,
2116   EVEX_W_0F79_P_2,
2117   EVEX_W_0F7A_P_1,
2118   EVEX_W_0F7A_P_2,
2119   EVEX_W_0F7A_P_3,
2120   EVEX_W_0F7B_P_2,
2121   EVEX_W_0F7B_P_3,
2122   EVEX_W_0F7E_P_1,
2123   EVEX_W_0F7F_P_1,
2124   EVEX_W_0F7F_P_2,
2125   EVEX_W_0F7F_P_3,
2126   EVEX_W_0FC2_P_1,
2127   EVEX_W_0FC2_P_3,
2128   EVEX_W_0FD2,
2129   EVEX_W_0FD3,
2130   EVEX_W_0FD4,
2131   EVEX_W_0FD6_P_2,
2132   EVEX_W_0FE6_P_1,
2133   EVEX_W_0FE6_P_2,
2134   EVEX_W_0FE6_P_3,
2135   EVEX_W_0FE7_P_2,
2136   EVEX_W_0FF2,
2137   EVEX_W_0FF3,
2138   EVEX_W_0FF4,
2139   EVEX_W_0FFA,
2140   EVEX_W_0FFB,
2141   EVEX_W_0FFE,
2142   EVEX_W_0F380D_P_2,
2143   EVEX_W_0F3810_P_1,
2144   EVEX_W_0F3810_P_2,
2145   EVEX_W_0F3811_P_1,
2146   EVEX_W_0F3811_P_2,
2147   EVEX_W_0F3812_P_1,
2148   EVEX_W_0F3812_P_2,
2149   EVEX_W_0F3813_P_1,
2150   EVEX_W_0F3813_P_2,
2151   EVEX_W_0F3814_P_1,
2152   EVEX_W_0F3815_P_1,
2153   EVEX_W_0F3819_P_2,
2154   EVEX_W_0F381A_P_2,
2155   EVEX_W_0F381B_P_2,
2156   EVEX_W_0F381E_P_2,
2157   EVEX_W_0F381F_P_2,
2158   EVEX_W_0F3820_P_1,
2159   EVEX_W_0F3821_P_1,
2160   EVEX_W_0F3822_P_1,
2161   EVEX_W_0F3823_P_1,
2162   EVEX_W_0F3824_P_1,
2163   EVEX_W_0F3825_P_1,
2164   EVEX_W_0F3825_P_2,
2165   EVEX_W_0F3828_P_2,
2166   EVEX_W_0F3829_P_2,
2167   EVEX_W_0F382A_P_1,
2168   EVEX_W_0F382A_P_2,
2169   EVEX_W_0F382B,
2170   EVEX_W_0F3830_P_1,
2171   EVEX_W_0F3831_P_1,
2172   EVEX_W_0F3832_P_1,
2173   EVEX_W_0F3833_P_1,
2174   EVEX_W_0F3834_P_1,
2175   EVEX_W_0F3835_P_1,
2176   EVEX_W_0F3835_P_2,
2177   EVEX_W_0F3837_P_2,
2178   EVEX_W_0F383A_P_1,
2179   EVEX_W_0F3852_P_1,
2180   EVEX_W_0F3859_P_2,
2181   EVEX_W_0F385A_P_2,
2182   EVEX_W_0F385B_P_2,
2183   EVEX_W_0F3870_P_2,
2184   EVEX_W_0F3872_P_1,
2185   EVEX_W_0F3872_P_2,
2186   EVEX_W_0F3872_P_3,
2187   EVEX_W_0F387A_P_2,
2188   EVEX_W_0F387B_P_2,
2189   EVEX_W_0F3883_P_2,
2190   EVEX_W_0F3891_P_2,
2191   EVEX_W_0F3893_P_2,
2192   EVEX_W_0F38A1_P_2,
2193   EVEX_W_0F38A3_P_2,
2194   EVEX_W_0F38C7_R_1_P_2,
2195   EVEX_W_0F38C7_R_2_P_2,
2196   EVEX_W_0F38C7_R_5_P_2,
2197   EVEX_W_0F38C7_R_6_P_2,
2198
2199   EVEX_W_0F3A00_P_2,
2200   EVEX_W_0F3A01_P_2,
2201   EVEX_W_0F3A05_P_2,
2202   EVEX_W_0F3A08_P_2,
2203   EVEX_W_0F3A09_P_2,
2204   EVEX_W_0F3A0A_P_2,
2205   EVEX_W_0F3A0B_P_2,
2206   EVEX_W_0F3A18_P_2,
2207   EVEX_W_0F3A19_P_2,
2208   EVEX_W_0F3A1A_P_2,
2209   EVEX_W_0F3A1B_P_2,
2210   EVEX_W_0F3A21_P_2,
2211   EVEX_W_0F3A23_P_2,
2212   EVEX_W_0F3A38_P_2,
2213   EVEX_W_0F3A39_P_2,
2214   EVEX_W_0F3A3A_P_2,
2215   EVEX_W_0F3A3B_P_2,
2216   EVEX_W_0F3A42_P_2,
2217   EVEX_W_0F3A43_P_2,
2218   EVEX_W_0F3A70_P_2,
2219   EVEX_W_0F3A72_P_2,
2220 };
2221
2222 typedef void (*op_rtn) (int bytemode, int sizeflag);
2223
2224 struct dis386 {
2225   const char *name;
2226   struct
2227     {
2228       op_rtn rtn;
2229       int bytemode;
2230     } op[MAX_OPERANDS];
2231   unsigned int prefix_requirement;
2232 };
2233
2234 /* Upper case letters in the instruction names here are macros.
2235    'A' => print 'b' if no register operands or suffix_always is true
2236    'B' => print 'b' if suffix_always is true
2237    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2238           size prefix
2239    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2240           suffix_always is true
2241    'E' => print 'e' if 32-bit form of jcxz
2242    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2243    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2244    'H' => print ",pt" or ",pn" branch hint
2245    'I' unused.
2246    'J' unused.
2247    'K' => print 'd' or 'q' if rex prefix is present.
2248    'L' => print 'l' if suffix_always is true
2249    'M' => print 'r' if intel_mnemonic is false.
2250    'N' => print 'n' if instruction has no wait "prefix"
2251    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2252    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2253           or suffix_always is true.  print 'q' if rex prefix is present.
2254    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2255           is true
2256    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2257    'S' => print 'w', 'l' or 'q' if suffix_always is true
2258    'T' => print 'q' in 64bit mode if instruction has no operand size
2259           prefix and behave as 'P' otherwise
2260    'U' => print 'q' in 64bit mode if instruction has no operand size
2261           prefix and behave as 'Q' otherwise
2262    'V' => print 'q' in 64bit mode if instruction has no operand size
2263           prefix and behave as 'S' otherwise
2264    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2265    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2266    'Y' unused.
2267    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2268    '!' => change condition from true to false or from false to true.
2269    '%' => add 1 upper case letter to the macro.
2270    '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
2271           prefix or suffix_always is true (lcall/ljmp).
2272    '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2273           on operand size prefix.
2274    '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2275           has no operand size prefix for AMD64 ISA, behave as 'P'
2276           otherwise
2277
2278    2 upper case letter macros:
2279    "XY" => print 'x' or 'y' if suffix_always is true or no register
2280            operands and no broadcast.
2281    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2282            register operands and no broadcast.
2283    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2284    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond
2285            being false, or no operand at all in 64bit mode, or if suffix_always
2286            is true.
2287    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2288    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2289    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2290    "LW" => print 'd', 'q' depending on the VEX.W bit
2291    "BW" => print 'b' or 'w' depending on the EVEX.W bit
2292    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2293            an operand size prefix, or suffix_always is true.  print
2294            'q' if rex prefix is present.
2295
2296    Many of the above letters print nothing in Intel mode.  See "putop"
2297    for the details.
2298
2299    Braces '{' and '}', and vertical bars '|', indicate alternative
2300    mnemonic strings for AT&T and Intel.  */
2301
2302 static const struct dis386 dis386[] = {
2303   /* 00 */
2304   { "addB",             { Ebh1, Gb }, 0 },
2305   { "addS",             { Evh1, Gv }, 0 },
2306   { "addB",             { Gb, EbS }, 0 },
2307   { "addS",             { Gv, EvS }, 0 },
2308   { "addB",             { AL, Ib }, 0 },
2309   { "addS",             { eAX, Iv }, 0 },
2310   { X86_64_TABLE (X86_64_06) },
2311   { X86_64_TABLE (X86_64_07) },
2312   /* 08 */
2313   { "orB",              { Ebh1, Gb }, 0 },
2314   { "orS",              { Evh1, Gv }, 0 },
2315   { "orB",              { Gb, EbS }, 0 },
2316   { "orS",              { Gv, EvS }, 0 },
2317   { "orB",              { AL, Ib }, 0 },
2318   { "orS",              { eAX, Iv }, 0 },
2319   { X86_64_TABLE (X86_64_0E) },
2320   { Bad_Opcode },       /* 0x0f extended opcode escape */
2321   /* 10 */
2322   { "adcB",             { Ebh1, Gb }, 0 },
2323   { "adcS",             { Evh1, Gv }, 0 },
2324   { "adcB",             { Gb, EbS }, 0 },
2325   { "adcS",             { Gv, EvS }, 0 },
2326   { "adcB",             { AL, Ib }, 0 },
2327   { "adcS",             { eAX, Iv }, 0 },
2328   { X86_64_TABLE (X86_64_16) },
2329   { X86_64_TABLE (X86_64_17) },
2330   /* 18 */
2331   { "sbbB",             { Ebh1, Gb }, 0 },
2332   { "sbbS",             { Evh1, Gv }, 0 },
2333   { "sbbB",             { Gb, EbS }, 0 },
2334   { "sbbS",             { Gv, EvS }, 0 },
2335   { "sbbB",             { AL, Ib }, 0 },
2336   { "sbbS",             { eAX, Iv }, 0 },
2337   { X86_64_TABLE (X86_64_1E) },
2338   { X86_64_TABLE (X86_64_1F) },
2339   /* 20 */
2340   { "andB",             { Ebh1, Gb }, 0 },
2341   { "andS",             { Evh1, Gv }, 0 },
2342   { "andB",             { Gb, EbS }, 0 },
2343   { "andS",             { Gv, EvS }, 0 },
2344   { "andB",             { AL, Ib }, 0 },
2345   { "andS",             { eAX, Iv }, 0 },
2346   { Bad_Opcode },       /* SEG ES prefix */
2347   { X86_64_TABLE (X86_64_27) },
2348   /* 28 */
2349   { "subB",             { Ebh1, Gb }, 0 },
2350   { "subS",             { Evh1, Gv }, 0 },
2351   { "subB",             { Gb, EbS }, 0 },
2352   { "subS",             { Gv, EvS }, 0 },
2353   { "subB",             { AL, Ib }, 0 },
2354   { "subS",             { eAX, Iv }, 0 },
2355   { Bad_Opcode },       /* SEG CS prefix */
2356   { X86_64_TABLE (X86_64_2F) },
2357   /* 30 */
2358   { "xorB",             { Ebh1, Gb }, 0 },
2359   { "xorS",             { Evh1, Gv }, 0 },
2360   { "xorB",             { Gb, EbS }, 0 },
2361   { "xorS",             { Gv, EvS }, 0 },
2362   { "xorB",             { AL, Ib }, 0 },
2363   { "xorS",             { eAX, Iv }, 0 },
2364   { Bad_Opcode },       /* SEG SS prefix */
2365   { X86_64_TABLE (X86_64_37) },
2366   /* 38 */
2367   { "cmpB",             { Eb, Gb }, 0 },
2368   { "cmpS",             { Ev, Gv }, 0 },
2369   { "cmpB",             { Gb, EbS }, 0 },
2370   { "cmpS",             { Gv, EvS }, 0 },
2371   { "cmpB",             { AL, Ib }, 0 },
2372   { "cmpS",             { eAX, Iv }, 0 },
2373   { Bad_Opcode },       /* SEG DS prefix */
2374   { X86_64_TABLE (X86_64_3F) },
2375   /* 40 */
2376   { "inc{S|}",          { RMeAX }, 0 },
2377   { "inc{S|}",          { RMeCX }, 0 },
2378   { "inc{S|}",          { RMeDX }, 0 },
2379   { "inc{S|}",          { RMeBX }, 0 },
2380   { "inc{S|}",          { RMeSP }, 0 },
2381   { "inc{S|}",          { RMeBP }, 0 },
2382   { "inc{S|}",          { RMeSI }, 0 },
2383   { "inc{S|}",          { RMeDI }, 0 },
2384   /* 48 */
2385   { "dec{S|}",          { RMeAX }, 0 },
2386   { "dec{S|}",          { RMeCX }, 0 },
2387   { "dec{S|}",          { RMeDX }, 0 },
2388   { "dec{S|}",          { RMeBX }, 0 },
2389   { "dec{S|}",          { RMeSP }, 0 },
2390   { "dec{S|}",          { RMeBP }, 0 },
2391   { "dec{S|}",          { RMeSI }, 0 },
2392   { "dec{S|}",          { RMeDI }, 0 },
2393   /* 50 */
2394   { "pushV",            { RMrAX }, 0 },
2395   { "pushV",            { RMrCX }, 0 },
2396   { "pushV",            { RMrDX }, 0 },
2397   { "pushV",            { RMrBX }, 0 },
2398   { "pushV",            { RMrSP }, 0 },
2399   { "pushV",            { RMrBP }, 0 },
2400   { "pushV",            { RMrSI }, 0 },
2401   { "pushV",            { RMrDI }, 0 },
2402   /* 58 */
2403   { "popV",             { RMrAX }, 0 },
2404   { "popV",             { RMrCX }, 0 },
2405   { "popV",             { RMrDX }, 0 },
2406   { "popV",             { RMrBX }, 0 },
2407   { "popV",             { RMrSP }, 0 },
2408   { "popV",             { RMrBP }, 0 },
2409   { "popV",             { RMrSI }, 0 },
2410   { "popV",             { RMrDI }, 0 },
2411   /* 60 */
2412   { X86_64_TABLE (X86_64_60) },
2413   { X86_64_TABLE (X86_64_61) },
2414   { X86_64_TABLE (X86_64_62) },
2415   { X86_64_TABLE (X86_64_63) },
2416   { Bad_Opcode },       /* seg fs */
2417   { Bad_Opcode },       /* seg gs */
2418   { Bad_Opcode },       /* op size prefix */
2419   { Bad_Opcode },       /* adr size prefix */
2420   /* 68 */
2421   { "pushT",            { sIv }, 0 },
2422   { "imulS",            { Gv, Ev, Iv }, 0 },
2423   { "pushT",            { sIbT }, 0 },
2424   { "imulS",            { Gv, Ev, sIb }, 0 },
2425   { "ins{b|}",          { Ybr, indirDX }, 0 },
2426   { X86_64_TABLE (X86_64_6D) },
2427   { "outs{b|}",         { indirDXr, Xb }, 0 },
2428   { X86_64_TABLE (X86_64_6F) },
2429   /* 70 */
2430   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
2431   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
2432   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
2433   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
2434   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
2435   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
2436   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
2437   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
2438   /* 78 */
2439   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
2440   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
2441   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
2442   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
2443   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
2444   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
2445   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
2446   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
2447   /* 80 */
2448   { REG_TABLE (REG_80) },
2449   { REG_TABLE (REG_81) },
2450   { X86_64_TABLE (X86_64_82) },
2451   { REG_TABLE (REG_83) },
2452   { "testB",            { Eb, Gb }, 0 },
2453   { "testS",            { Ev, Gv }, 0 },
2454   { "xchgB",            { Ebh2, Gb }, 0 },
2455   { "xchgS",            { Evh2, Gv }, 0 },
2456   /* 88 */
2457   { "movB",             { Ebh3, Gb }, 0 },
2458   { "movS",             { Evh3, Gv }, 0 },
2459   { "movB",             { Gb, EbS }, 0 },
2460   { "movS",             { Gv, EvS }, 0 },
2461   { "movD",             { Sv, Sw }, 0 },
2462   { MOD_TABLE (MOD_8D) },
2463   { "movD",             { Sw, Sv }, 0 },
2464   { REG_TABLE (REG_8F) },
2465   /* 90 */
2466   { PREFIX_TABLE (PREFIX_90) },
2467   { "xchgS",            { RMeCX, eAX }, 0 },
2468   { "xchgS",            { RMeDX, eAX }, 0 },
2469   { "xchgS",            { RMeBX, eAX }, 0 },
2470   { "xchgS",            { RMeSP, eAX }, 0 },
2471   { "xchgS",            { RMeBP, eAX }, 0 },
2472   { "xchgS",            { RMeSI, eAX }, 0 },
2473   { "xchgS",            { RMeDI, eAX }, 0 },
2474   /* 98 */
2475   { "cW{t|}R",          { XX }, 0 },
2476   { "cR{t|}O",          { XX }, 0 },
2477   { X86_64_TABLE (X86_64_9A) },
2478   { Bad_Opcode },       /* fwait */
2479   { "pushfT",           { XX }, 0 },
2480   { "popfT",            { XX }, 0 },
2481   { "sahf",             { XX }, 0 },
2482   { "lahf",             { XX }, 0 },
2483   /* a0 */
2484   { "mov%LB",           { AL, Ob }, 0 },
2485   { "mov%LS",           { eAX, Ov }, 0 },
2486   { "mov%LB",           { Ob, AL }, 0 },
2487   { "mov%LS",           { Ov, eAX }, 0 },
2488   { "movs{b|}",         { Ybr, Xb }, 0 },
2489   { "movs{R|}",         { Yvr, Xv }, 0 },
2490   { "cmps{b|}",         { Xb, Yb }, 0 },
2491   { "cmps{R|}",         { Xv, Yv }, 0 },
2492   /* a8 */
2493   { "testB",            { AL, Ib }, 0 },
2494   { "testS",            { eAX, Iv }, 0 },
2495   { "stosB",            { Ybr, AL }, 0 },
2496   { "stosS",            { Yvr, eAX }, 0 },
2497   { "lodsB",            { ALr, Xb }, 0 },
2498   { "lodsS",            { eAXr, Xv }, 0 },
2499   { "scasB",            { AL, Yb }, 0 },
2500   { "scasS",            { eAX, Yv }, 0 },
2501   /* b0 */
2502   { "movB",             { RMAL, Ib }, 0 },
2503   { "movB",             { RMCL, Ib }, 0 },
2504   { "movB",             { RMDL, Ib }, 0 },
2505   { "movB",             { RMBL, Ib }, 0 },
2506   { "movB",             { RMAH, Ib }, 0 },
2507   { "movB",             { RMCH, Ib }, 0 },
2508   { "movB",             { RMDH, Ib }, 0 },
2509   { "movB",             { RMBH, Ib }, 0 },
2510   /* b8 */
2511   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2512   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2513   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2514   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2515   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2516   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2517   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2518   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2519   /* c0 */
2520   { REG_TABLE (REG_C0) },
2521   { REG_TABLE (REG_C1) },
2522   { X86_64_TABLE (X86_64_C2) },
2523   { X86_64_TABLE (X86_64_C3) },
2524   { X86_64_TABLE (X86_64_C4) },
2525   { X86_64_TABLE (X86_64_C5) },
2526   { REG_TABLE (REG_C6) },
2527   { REG_TABLE (REG_C7) },
2528   /* c8 */
2529   { "enterT",           { Iw, Ib }, 0 },
2530   { "leaveT",           { XX }, 0 },
2531   { "{l|}ret{|f}P",     { Iw }, 0 },
2532   { "{l|}ret{|f}P",     { XX }, 0 },
2533   { "int3",             { XX }, 0 },
2534   { "int",              { Ib }, 0 },
2535   { X86_64_TABLE (X86_64_CE) },
2536   { "iret%LP",          { XX }, 0 },
2537   /* d0 */
2538   { REG_TABLE (REG_D0) },
2539   { REG_TABLE (REG_D1) },
2540   { REG_TABLE (REG_D2) },
2541   { REG_TABLE (REG_D3) },
2542   { X86_64_TABLE (X86_64_D4) },
2543   { X86_64_TABLE (X86_64_D5) },
2544   { Bad_Opcode },
2545   { "xlat",             { DSBX }, 0 },
2546   /* d8 */
2547   { FLOAT },
2548   { FLOAT },
2549   { FLOAT },
2550   { FLOAT },
2551   { FLOAT },
2552   { FLOAT },
2553   { FLOAT },
2554   { FLOAT },
2555   /* e0 */
2556   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2557   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2558   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2559   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2560   { "inB",              { AL, Ib }, 0 },
2561   { "inG",              { zAX, Ib }, 0 },
2562   { "outB",             { Ib, AL }, 0 },
2563   { "outG",             { Ib, zAX }, 0 },
2564   /* e8 */
2565   { X86_64_TABLE (X86_64_E8) },
2566   { X86_64_TABLE (X86_64_E9) },
2567   { X86_64_TABLE (X86_64_EA) },
2568   { "jmp",              { Jb, BND }, 0 },
2569   { "inB",              { AL, indirDX }, 0 },
2570   { "inG",              { zAX, indirDX }, 0 },
2571   { "outB",             { indirDX, AL }, 0 },
2572   { "outG",             { indirDX, zAX }, 0 },
2573   /* f0 */
2574   { Bad_Opcode },       /* lock prefix */
2575   { "icebp",            { XX }, 0 },
2576   { Bad_Opcode },       /* repne */
2577   { Bad_Opcode },       /* repz */
2578   { "hlt",              { XX }, 0 },
2579   { "cmc",              { XX }, 0 },
2580   { REG_TABLE (REG_F6) },
2581   { REG_TABLE (REG_F7) },
2582   /* f8 */
2583   { "clc",              { XX }, 0 },
2584   { "stc",              { XX }, 0 },
2585   { "cli",              { XX }, 0 },
2586   { "sti",              { XX }, 0 },
2587   { "cld",              { XX }, 0 },
2588   { "std",              { XX }, 0 },
2589   { REG_TABLE (REG_FE) },
2590   { REG_TABLE (REG_FF) },
2591 };
2592
2593 static const struct dis386 dis386_twobyte[] = {
2594   /* 00 */
2595   { REG_TABLE (REG_0F00 ) },
2596   { REG_TABLE (REG_0F01 ) },
2597   { "larS",             { Gv, Ew }, 0 },
2598   { "lslS",             { Gv, Ew }, 0 },
2599   { Bad_Opcode },
2600   { "syscall",          { XX }, 0 },
2601   { "clts",             { XX }, 0 },
2602   { "sysret%LQ",                { XX }, 0 },
2603   /* 08 */
2604   { "invd",             { XX }, 0 },
2605   { PREFIX_TABLE (PREFIX_0F09) },
2606   { Bad_Opcode },
2607   { "ud2",              { XX }, 0 },
2608   { Bad_Opcode },
2609   { REG_TABLE (REG_0F0D) },
2610   { "femms",            { XX }, 0 },
2611   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2612   /* 10 */
2613   { PREFIX_TABLE (PREFIX_0F10) },
2614   { PREFIX_TABLE (PREFIX_0F11) },
2615   { PREFIX_TABLE (PREFIX_0F12) },
2616   { MOD_TABLE (MOD_0F13) },
2617   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2618   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2619   { PREFIX_TABLE (PREFIX_0F16) },
2620   { MOD_TABLE (MOD_0F17) },
2621   /* 18 */
2622   { REG_TABLE (REG_0F18) },
2623   { "nopQ",             { Ev }, 0 },
2624   { PREFIX_TABLE (PREFIX_0F1A) },
2625   { PREFIX_TABLE (PREFIX_0F1B) },
2626   { PREFIX_TABLE (PREFIX_0F1C) },
2627   { "nopQ",             { Ev }, 0 },
2628   { PREFIX_TABLE (PREFIX_0F1E) },
2629   { "nopQ",             { Ev }, 0 },
2630   /* 20 */
2631   { "movZ",             { Rm, Cm }, 0 },
2632   { "movZ",             { Rm, Dm }, 0 },
2633   { "movZ",             { Cm, Rm }, 0 },
2634   { "movZ",             { Dm, Rm }, 0 },
2635   { MOD_TABLE (MOD_0F24) },
2636   { Bad_Opcode },
2637   { MOD_TABLE (MOD_0F26) },
2638   { Bad_Opcode },
2639   /* 28 */
2640   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2641   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2642   { PREFIX_TABLE (PREFIX_0F2A) },
2643   { PREFIX_TABLE (PREFIX_0F2B) },
2644   { PREFIX_TABLE (PREFIX_0F2C) },
2645   { PREFIX_TABLE (PREFIX_0F2D) },
2646   { PREFIX_TABLE (PREFIX_0F2E) },
2647   { PREFIX_TABLE (PREFIX_0F2F) },
2648   /* 30 */
2649   { "wrmsr",            { XX }, 0 },
2650   { "rdtsc",            { XX }, 0 },
2651   { "rdmsr",            { XX }, 0 },
2652   { "rdpmc",            { XX }, 0 },
2653   { "sysenter",         { SEP }, 0 },
2654   { "sysexit",          { SEP }, 0 },
2655   { Bad_Opcode },
2656   { "getsec",           { XX }, 0 },
2657   /* 38 */
2658   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2659   { Bad_Opcode },
2660   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2661   { Bad_Opcode },
2662   { Bad_Opcode },
2663   { Bad_Opcode },
2664   { Bad_Opcode },
2665   { Bad_Opcode },
2666   /* 40 */
2667   { "cmovoS",           { Gv, Ev }, 0 },
2668   { "cmovnoS",          { Gv, Ev }, 0 },
2669   { "cmovbS",           { Gv, Ev }, 0 },
2670   { "cmovaeS",          { Gv, Ev }, 0 },
2671   { "cmoveS",           { Gv, Ev }, 0 },
2672   { "cmovneS",          { Gv, Ev }, 0 },
2673   { "cmovbeS",          { Gv, Ev }, 0 },
2674   { "cmovaS",           { Gv, Ev }, 0 },
2675   /* 48 */
2676   { "cmovsS",           { Gv, Ev }, 0 },
2677   { "cmovnsS",          { Gv, Ev }, 0 },
2678   { "cmovpS",           { Gv, Ev }, 0 },
2679   { "cmovnpS",          { Gv, Ev }, 0 },
2680   { "cmovlS",           { Gv, Ev }, 0 },
2681   { "cmovgeS",          { Gv, Ev }, 0 },
2682   { "cmovleS",          { Gv, Ev }, 0 },
2683   { "cmovgS",           { Gv, Ev }, 0 },
2684   /* 50 */
2685   { MOD_TABLE (MOD_0F50) },
2686   { PREFIX_TABLE (PREFIX_0F51) },
2687   { PREFIX_TABLE (PREFIX_0F52) },
2688   { PREFIX_TABLE (PREFIX_0F53) },
2689   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2690   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2691   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2692   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2693   /* 58 */
2694   { PREFIX_TABLE (PREFIX_0F58) },
2695   { PREFIX_TABLE (PREFIX_0F59) },
2696   { PREFIX_TABLE (PREFIX_0F5A) },
2697   { PREFIX_TABLE (PREFIX_0F5B) },
2698   { PREFIX_TABLE (PREFIX_0F5C) },
2699   { PREFIX_TABLE (PREFIX_0F5D) },
2700   { PREFIX_TABLE (PREFIX_0F5E) },
2701   { PREFIX_TABLE (PREFIX_0F5F) },
2702   /* 60 */
2703   { PREFIX_TABLE (PREFIX_0F60) },
2704   { PREFIX_TABLE (PREFIX_0F61) },
2705   { PREFIX_TABLE (PREFIX_0F62) },
2706   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2707   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2708   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2709   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2710   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2711   /* 68 */
2712   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2713   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2714   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2715   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2716   { PREFIX_TABLE (PREFIX_0F6C) },
2717   { PREFIX_TABLE (PREFIX_0F6D) },
2718   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2719   { PREFIX_TABLE (PREFIX_0F6F) },
2720   /* 70 */
2721   { PREFIX_TABLE (PREFIX_0F70) },
2722   { REG_TABLE (REG_0F71) },
2723   { REG_TABLE (REG_0F72) },
2724   { REG_TABLE (REG_0F73) },
2725   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2726   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2727   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2728   { "emms",             { XX }, PREFIX_OPCODE },
2729   /* 78 */
2730   { PREFIX_TABLE (PREFIX_0F78) },
2731   { PREFIX_TABLE (PREFIX_0F79) },
2732   { Bad_Opcode },
2733   { Bad_Opcode },
2734   { PREFIX_TABLE (PREFIX_0F7C) },
2735   { PREFIX_TABLE (PREFIX_0F7D) },
2736   { PREFIX_TABLE (PREFIX_0F7E) },
2737   { PREFIX_TABLE (PREFIX_0F7F) },
2738   /* 80 */
2739   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2740   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2741   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2742   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2743   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2744   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2745   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2746   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2747   /* 88 */
2748   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2749   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2750   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2751   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2752   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2753   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2754   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2755   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2756   /* 90 */
2757   { "seto",             { Eb }, 0 },
2758   { "setno",            { Eb }, 0 },
2759   { "setb",             { Eb }, 0 },
2760   { "setae",            { Eb }, 0 },
2761   { "sete",             { Eb }, 0 },
2762   { "setne",            { Eb }, 0 },
2763   { "setbe",            { Eb }, 0 },
2764   { "seta",             { Eb }, 0 },
2765   /* 98 */
2766   { "sets",             { Eb }, 0 },
2767   { "setns",            { Eb }, 0 },
2768   { "setp",             { Eb }, 0 },
2769   { "setnp",            { Eb }, 0 },
2770   { "setl",             { Eb }, 0 },
2771   { "setge",            { Eb }, 0 },
2772   { "setle",            { Eb }, 0 },
2773   { "setg",             { Eb }, 0 },
2774   /* a0 */
2775   { "pushT",            { fs }, 0 },
2776   { "popT",             { fs }, 0 },
2777   { "cpuid",            { XX }, 0 },
2778   { "btS",              { Ev, Gv }, 0 },
2779   { "shldS",            { Ev, Gv, Ib }, 0 },
2780   { "shldS",            { Ev, Gv, CL }, 0 },
2781   { REG_TABLE (REG_0FA6) },
2782   { REG_TABLE (REG_0FA7) },
2783   /* a8 */
2784   { "pushT",            { gs }, 0 },
2785   { "popT",             { gs }, 0 },
2786   { "rsm",              { XX }, 0 },
2787   { "btsS",             { Evh1, Gv }, 0 },
2788   { "shrdS",            { Ev, Gv, Ib }, 0 },
2789   { "shrdS",            { Ev, Gv, CL }, 0 },
2790   { REG_TABLE (REG_0FAE) },
2791   { "imulS",            { Gv, Ev }, 0 },
2792   /* b0 */
2793   { "cmpxchgB",         { Ebh1, Gb }, 0 },
2794   { "cmpxchgS",         { Evh1, Gv }, 0 },
2795   { MOD_TABLE (MOD_0FB2) },
2796   { "btrS",             { Evh1, Gv }, 0 },
2797   { MOD_TABLE (MOD_0FB4) },
2798   { MOD_TABLE (MOD_0FB5) },
2799   { "movz{bR|x}",       { Gv, Eb }, 0 },
2800   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2801   /* b8 */
2802   { PREFIX_TABLE (PREFIX_0FB8) },
2803   { "ud1S",             { Gv, Ev }, 0 },
2804   { REG_TABLE (REG_0FBA) },
2805   { "btcS",             { Evh1, Gv }, 0 },
2806   { PREFIX_TABLE (PREFIX_0FBC) },
2807   { PREFIX_TABLE (PREFIX_0FBD) },
2808   { "movs{bR|x}",       { Gv, Eb }, 0 },
2809   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2810   /* c0 */
2811   { "xaddB",            { Ebh1, Gb }, 0 },
2812   { "xaddS",            { Evh1, Gv }, 0 },
2813   { PREFIX_TABLE (PREFIX_0FC2) },
2814   { MOD_TABLE (MOD_0FC3) },
2815   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
2816   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
2817   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
2818   { REG_TABLE (REG_0FC7) },
2819   /* c8 */
2820   { "bswap",            { RMeAX }, 0 },
2821   { "bswap",            { RMeCX }, 0 },
2822   { "bswap",            { RMeDX }, 0 },
2823   { "bswap",            { RMeBX }, 0 },
2824   { "bswap",            { RMeSP }, 0 },
2825   { "bswap",            { RMeBP }, 0 },
2826   { "bswap",            { RMeSI }, 0 },
2827   { "bswap",            { RMeDI }, 0 },
2828   /* d0 */
2829   { PREFIX_TABLE (PREFIX_0FD0) },
2830   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
2831   { "psrld",            { MX, EM }, PREFIX_OPCODE },
2832   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
2833   { "paddq",            { MX, EM }, PREFIX_OPCODE },
2834   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
2835   { PREFIX_TABLE (PREFIX_0FD6) },
2836   { MOD_TABLE (MOD_0FD7) },
2837   /* d8 */
2838   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
2839   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
2840   { "pminub",           { MX, EM }, PREFIX_OPCODE },
2841   { "pand",             { MX, EM }, PREFIX_OPCODE },
2842   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
2843   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
2844   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
2845   { "pandn",            { MX, EM }, PREFIX_OPCODE },
2846   /* e0 */
2847   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
2848   { "psraw",            { MX, EM }, PREFIX_OPCODE },
2849   { "psrad",            { MX, EM }, PREFIX_OPCODE },
2850   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
2851   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
2852   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
2853   { PREFIX_TABLE (PREFIX_0FE6) },
2854   { PREFIX_TABLE (PREFIX_0FE7) },
2855   /* e8 */
2856   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
2857   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
2858   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
2859   { "por",              { MX, EM }, PREFIX_OPCODE },
2860   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
2861   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
2862   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
2863   { "pxor",             { MX, EM }, PREFIX_OPCODE },
2864   /* f0 */
2865   { PREFIX_TABLE (PREFIX_0FF0) },
2866   { "psllw",            { MX, EM }, PREFIX_OPCODE },
2867   { "pslld",            { MX, EM }, PREFIX_OPCODE },
2868   { "psllq",            { MX, EM }, PREFIX_OPCODE },
2869   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
2870   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
2871   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
2872   { PREFIX_TABLE (PREFIX_0FF7) },
2873   /* f8 */
2874   { "psubb",            { MX, EM }, PREFIX_OPCODE },
2875   { "psubw",            { MX, EM }, PREFIX_OPCODE },
2876   { "psubd",            { MX, EM }, PREFIX_OPCODE },
2877   { "psubq",            { MX, EM }, PREFIX_OPCODE },
2878   { "paddb",            { MX, EM }, PREFIX_OPCODE },
2879   { "paddw",            { MX, EM }, PREFIX_OPCODE },
2880   { "paddd",            { MX, EM }, PREFIX_OPCODE },
2881   { "ud0S",             { Gv, Ev }, 0 },
2882 };
2883
2884 static const unsigned char onebyte_has_modrm[256] = {
2885   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2886   /*       -------------------------------        */
2887   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2888   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2889   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2890   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2891   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2892   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2893   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2894   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2895   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2896   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2897   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2898   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2899   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2900   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2901   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2902   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2903   /*       -------------------------------        */
2904   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2905 };
2906
2907 static const unsigned char twobyte_has_modrm[256] = {
2908   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2909   /*       -------------------------------        */
2910   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2911   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2912   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2913   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2914   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2915   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2916   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2917   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2918   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2919   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2920   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2921   /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2922   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2923   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2924   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2925   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1  /* ff */
2926   /*       -------------------------------        */
2927   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2928 };
2929
2930 static char obuf[100];
2931 static char *obufp;
2932 static char *mnemonicendp;
2933 static char scratchbuf[100];
2934 static unsigned char *start_codep;
2935 static unsigned char *insn_codep;
2936 static unsigned char *codep;
2937 static unsigned char *end_codep;
2938 static int last_lock_prefix;
2939 static int last_repz_prefix;
2940 static int last_repnz_prefix;
2941 static int last_data_prefix;
2942 static int last_addr_prefix;
2943 static int last_rex_prefix;
2944 static int last_seg_prefix;
2945 static int fwait_prefix;
2946 /* The active segment register prefix.  */
2947 static int active_seg_prefix;
2948 #define MAX_CODE_LENGTH 15
2949 /* We can up to 14 prefixes since the maximum instruction length is
2950    15bytes.  */
2951 static int all_prefixes[MAX_CODE_LENGTH - 1];
2952 static disassemble_info *the_info;
2953 static struct
2954   {
2955     int mod;
2956     int reg;
2957     int rm;
2958   }
2959 modrm;
2960 static unsigned char need_modrm;
2961 static struct
2962   {
2963     int scale;
2964     int index;
2965     int base;
2966   }
2967 sib;
2968 static struct
2969   {
2970     int register_specifier;
2971     int length;
2972     int prefix;
2973     int w;
2974     int evex;
2975     int r;
2976     int v;
2977     int mask_register_specifier;
2978     int zeroing;
2979     int ll;
2980     int b;
2981   }
2982 vex;
2983 static unsigned char need_vex;
2984 static unsigned char need_vex_reg;
2985
2986 struct op
2987   {
2988     const char *name;
2989     unsigned int len;
2990   };
2991
2992 /* If we are accessing mod/rm/reg without need_modrm set, then the
2993    values are stale.  Hitting this abort likely indicates that you
2994    need to update onebyte_has_modrm or twobyte_has_modrm.  */
2995 #define MODRM_CHECK  if (!need_modrm) abort ()
2996
2997 static const char **names64;
2998 static const char **names32;
2999 static const char **names16;
3000 static const char **names8;
3001 static const char **names8rex;
3002 static const char **names_seg;
3003 static const char *index64;
3004 static const char *index32;
3005 static const char **index16;
3006 static const char **names_bnd;
3007
3008 static const char *intel_names64[] = {
3009   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3010   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3011 };
3012 static const char *intel_names32[] = {
3013   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3014   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3015 };
3016 static const char *intel_names16[] = {
3017   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3018   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3019 };
3020 static const char *intel_names8[] = {
3021   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3022 };
3023 static const char *intel_names8rex[] = {
3024   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3025   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3026 };
3027 static const char *intel_names_seg[] = {
3028   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3029 };
3030 static const char *intel_index64 = "riz";
3031 static const char *intel_index32 = "eiz";
3032 static const char *intel_index16[] = {
3033   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3034 };
3035
3036 static const char *att_names64[] = {
3037   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3038   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3039 };
3040 static const char *att_names32[] = {
3041   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3042   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3043 };
3044 static const char *att_names16[] = {
3045   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3046   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3047 };
3048 static const char *att_names8[] = {
3049   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3050 };
3051 static const char *att_names8rex[] = {
3052   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3053   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3054 };
3055 static const char *att_names_seg[] = {
3056   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3057 };
3058 static const char *att_index64 = "%riz";
3059 static const char *att_index32 = "%eiz";
3060 static const char *att_index16[] = {
3061   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3062 };
3063
3064 static const char **names_mm;
3065 static const char *intel_names_mm[] = {
3066   "mm0", "mm1", "mm2", "mm3",
3067   "mm4", "mm5", "mm6", "mm7"
3068 };
3069 static const char *att_names_mm[] = {
3070   "%mm0", "%mm1", "%mm2", "%mm3",
3071   "%mm4", "%mm5", "%mm6", "%mm7"
3072 };
3073
3074 static const char *intel_names_bnd[] = {
3075   "bnd0", "bnd1", "bnd2", "bnd3"
3076 };
3077
3078 static const char *att_names_bnd[] = {
3079   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3080 };
3081
3082 static const char **names_xmm;
3083 static const char *intel_names_xmm[] = {
3084   "xmm0", "xmm1", "xmm2", "xmm3",
3085   "xmm4", "xmm5", "xmm6", "xmm7",
3086   "xmm8", "xmm9", "xmm10", "xmm11",
3087   "xmm12", "xmm13", "xmm14", "xmm15",
3088   "xmm16", "xmm17", "xmm18", "xmm19",
3089   "xmm20", "xmm21", "xmm22", "xmm23",
3090   "xmm24", "xmm25", "xmm26", "xmm27",
3091   "xmm28", "xmm29", "xmm30", "xmm31"
3092 };
3093 static const char *att_names_xmm[] = {
3094   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3095   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3096   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3097   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3098   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3099   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3100   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3101   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3102 };
3103
3104 static const char **names_ymm;
3105 static const char *intel_names_ymm[] = {
3106   "ymm0", "ymm1", "ymm2", "ymm3",
3107   "ymm4", "ymm5", "ymm6", "ymm7",
3108   "ymm8", "ymm9", "ymm10", "ymm11",
3109   "ymm12", "ymm13", "ymm14", "ymm15",
3110   "ymm16", "ymm17", "ymm18", "ymm19",
3111   "ymm20", "ymm21", "ymm22", "ymm23",
3112   "ymm24", "ymm25", "ymm26", "ymm27",
3113   "ymm28", "ymm29", "ymm30", "ymm31"
3114 };
3115 static const char *att_names_ymm[] = {
3116   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3117   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3118   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3119   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3120   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3121   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3122   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3123   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3124 };
3125
3126 static const char **names_zmm;
3127 static const char *intel_names_zmm[] = {
3128   "zmm0", "zmm1", "zmm2", "zmm3",
3129   "zmm4", "zmm5", "zmm6", "zmm7",
3130   "zmm8", "zmm9", "zmm10", "zmm11",
3131   "zmm12", "zmm13", "zmm14", "zmm15",
3132   "zmm16", "zmm17", "zmm18", "zmm19",
3133   "zmm20", "zmm21", "zmm22", "zmm23",
3134   "zmm24", "zmm25", "zmm26", "zmm27",
3135   "zmm28", "zmm29", "zmm30", "zmm31"
3136 };
3137 static const char *att_names_zmm[] = {
3138   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3139   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3140   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3141   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3142   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3143   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3144   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3145   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3146 };
3147
3148 static const char **names_tmm;
3149 static const char *intel_names_tmm[] = {
3150   "tmm0", "tmm1", "tmm2", "tmm3",
3151   "tmm4", "tmm5", "tmm6", "tmm7"
3152 };
3153 static const char *att_names_tmm[] = {
3154   "%tmm0", "%tmm1", "%tmm2", "%tmm3",
3155   "%tmm4", "%tmm5", "%tmm6", "%tmm7"
3156 };
3157
3158 static const char **names_mask;
3159 static const char *intel_names_mask[] = {
3160   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3161 };
3162 static const char *att_names_mask[] = {
3163   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3164 };
3165
3166 static const char *names_rounding[] =
3167 {
3168   "{rn-sae}",
3169   "{rd-sae}",
3170   "{ru-sae}",
3171   "{rz-sae}"
3172 };
3173
3174 static const struct dis386 reg_table[][8] = {
3175   /* REG_80 */
3176   {
3177     { "addA",   { Ebh1, Ib }, 0 },
3178     { "orA",    { Ebh1, Ib }, 0 },
3179     { "adcA",   { Ebh1, Ib }, 0 },
3180     { "sbbA",   { Ebh1, Ib }, 0 },
3181     { "andA",   { Ebh1, Ib }, 0 },
3182     { "subA",   { Ebh1, Ib }, 0 },
3183     { "xorA",   { Ebh1, Ib }, 0 },
3184     { "cmpA",   { Eb, Ib }, 0 },
3185   },
3186   /* REG_81 */
3187   {
3188     { "addQ",   { Evh1, Iv }, 0 },
3189     { "orQ",    { Evh1, Iv }, 0 },
3190     { "adcQ",   { Evh1, Iv }, 0 },
3191     { "sbbQ",   { Evh1, Iv }, 0 },
3192     { "andQ",   { Evh1, Iv }, 0 },
3193     { "subQ",   { Evh1, Iv }, 0 },
3194     { "xorQ",   { Evh1, Iv }, 0 },
3195     { "cmpQ",   { Ev, Iv }, 0 },
3196   },
3197   /* REG_83 */
3198   {
3199     { "addQ",   { Evh1, sIb }, 0 },
3200     { "orQ",    { Evh1, sIb }, 0 },
3201     { "adcQ",   { Evh1, sIb }, 0 },
3202     { "sbbQ",   { Evh1, sIb }, 0 },
3203     { "andQ",   { Evh1, sIb }, 0 },
3204     { "subQ",   { Evh1, sIb }, 0 },
3205     { "xorQ",   { Evh1, sIb }, 0 },
3206     { "cmpQ",   { Ev, sIb }, 0 },
3207   },
3208   /* REG_8F */
3209   {
3210     { "popU",   { stackEv }, 0 },
3211     { XOP_8F_TABLE (XOP_09) },
3212     { Bad_Opcode },
3213     { Bad_Opcode },
3214     { Bad_Opcode },
3215     { XOP_8F_TABLE (XOP_09) },
3216   },
3217   /* REG_C0 */
3218   {
3219     { "rolA",   { Eb, Ib }, 0 },
3220     { "rorA",   { Eb, Ib }, 0 },
3221     { "rclA",   { Eb, Ib }, 0 },
3222     { "rcrA",   { Eb, Ib }, 0 },
3223     { "shlA",   { Eb, Ib }, 0 },
3224     { "shrA",   { Eb, Ib }, 0 },
3225     { "shlA",   { Eb, Ib }, 0 },
3226     { "sarA",   { Eb, Ib }, 0 },
3227   },
3228   /* REG_C1 */
3229   {
3230     { "rolQ",   { Ev, Ib }, 0 },
3231     { "rorQ",   { Ev, Ib }, 0 },
3232     { "rclQ",   { Ev, Ib }, 0 },
3233     { "rcrQ",   { Ev, Ib }, 0 },
3234     { "shlQ",   { Ev, Ib }, 0 },
3235     { "shrQ",   { Ev, Ib }, 0 },
3236     { "shlQ",   { Ev, Ib }, 0 },
3237     { "sarQ",   { Ev, Ib }, 0 },
3238   },
3239   /* REG_C6 */
3240   {
3241     { "movA",   { Ebh3, Ib }, 0 },
3242     { Bad_Opcode },
3243     { Bad_Opcode },
3244     { Bad_Opcode },
3245     { Bad_Opcode },
3246     { Bad_Opcode },
3247     { Bad_Opcode },
3248     { MOD_TABLE (MOD_C6_REG_7) },
3249   },
3250   /* REG_C7 */
3251   {
3252     { "movQ",   { Evh3, Iv }, 0 },
3253     { Bad_Opcode },
3254     { Bad_Opcode },
3255     { Bad_Opcode },
3256     { Bad_Opcode },
3257     { Bad_Opcode },
3258     { Bad_Opcode },
3259     { MOD_TABLE (MOD_C7_REG_7) },
3260   },
3261   /* REG_D0 */
3262   {
3263     { "rolA",   { Eb, I1 }, 0 },
3264     { "rorA",   { Eb, I1 }, 0 },
3265     { "rclA",   { Eb, I1 }, 0 },
3266     { "rcrA",   { Eb, I1 }, 0 },
3267     { "shlA",   { Eb, I1 }, 0 },
3268     { "shrA",   { Eb, I1 }, 0 },
3269     { "shlA",   { Eb, I1 }, 0 },
3270     { "sarA",   { Eb, I1 }, 0 },
3271   },
3272   /* REG_D1 */
3273   {
3274     { "rolQ",   { Ev, I1 }, 0 },
3275     { "rorQ",   { Ev, I1 }, 0 },
3276     { "rclQ",   { Ev, I1 }, 0 },
3277     { "rcrQ",   { Ev, I1 }, 0 },
3278     { "shlQ",   { Ev, I1 }, 0 },
3279     { "shrQ",   { Ev, I1 }, 0 },
3280     { "shlQ",   { Ev, I1 }, 0 },
3281     { "sarQ",   { Ev, I1 }, 0 },
3282   },
3283   /* REG_D2 */
3284   {
3285     { "rolA",   { Eb, CL }, 0 },
3286     { "rorA",   { Eb, CL }, 0 },
3287     { "rclA",   { Eb, CL }, 0 },
3288     { "rcrA",   { Eb, CL }, 0 },
3289     { "shlA",   { Eb, CL }, 0 },
3290     { "shrA",   { Eb, CL }, 0 },
3291     { "shlA",   { Eb, CL }, 0 },
3292     { "sarA",   { Eb, CL }, 0 },
3293   },
3294   /* REG_D3 */
3295   {
3296     { "rolQ",   { Ev, CL }, 0 },
3297     { "rorQ",   { Ev, CL }, 0 },
3298     { "rclQ",   { Ev, CL }, 0 },
3299     { "rcrQ",   { Ev, CL }, 0 },
3300     { "shlQ",   { Ev, CL }, 0 },
3301     { "shrQ",   { Ev, CL }, 0 },
3302     { "shlQ",   { Ev, CL }, 0 },
3303     { "sarQ",   { Ev, CL }, 0 },
3304   },
3305   /* REG_F6 */
3306   {
3307     { "testA",  { Eb, Ib }, 0 },
3308     { "testA",  { Eb, Ib }, 0 },
3309     { "notA",   { Ebh1 }, 0 },
3310     { "negA",   { Ebh1 }, 0 },
3311     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
3312     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
3313     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
3314     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
3315   },
3316   /* REG_F7 */
3317   {
3318     { "testQ",  { Ev, Iv }, 0 },
3319     { "testQ",  { Ev, Iv }, 0 },
3320     { "notQ",   { Evh1 }, 0 },
3321     { "negQ",   { Evh1 }, 0 },
3322     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
3323     { "imulQ",  { Ev }, 0 },
3324     { "divQ",   { Ev }, 0 },
3325     { "idivQ",  { Ev }, 0 },
3326   },
3327   /* REG_FE */
3328   {
3329     { "incA",   { Ebh1 }, 0 },
3330     { "decA",   { Ebh1 }, 0 },
3331   },
3332   /* REG_FF */
3333   {
3334     { "incQ",   { Evh1 }, 0 },
3335     { "decQ",   { Evh1 }, 0 },
3336     { "call{&|}", { NOTRACK, indirEv, BND }, 0 },
3337     { MOD_TABLE (MOD_FF_REG_3) },
3338     { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 },
3339     { MOD_TABLE (MOD_FF_REG_5) },
3340     { "pushU",  { stackEv }, 0 },
3341     { Bad_Opcode },
3342   },
3343   /* REG_0F00 */
3344   {
3345     { "sldtD",  { Sv }, 0 },
3346     { "strD",   { Sv }, 0 },
3347     { "lldt",   { Ew }, 0 },
3348     { "ltr",    { Ew }, 0 },
3349     { "verr",   { Ew }, 0 },
3350     { "verw",   { Ew }, 0 },
3351     { Bad_Opcode },
3352     { Bad_Opcode },
3353   },
3354   /* REG_0F01 */
3355   {
3356     { MOD_TABLE (MOD_0F01_REG_0) },
3357     { MOD_TABLE (MOD_0F01_REG_1) },
3358     { MOD_TABLE (MOD_0F01_REG_2) },
3359     { MOD_TABLE (MOD_0F01_REG_3) },
3360     { "smswD",  { Sv }, 0 },
3361     { MOD_TABLE (MOD_0F01_REG_5) },
3362     { "lmsw",   { Ew }, 0 },
3363     { MOD_TABLE (MOD_0F01_REG_7) },
3364   },
3365   /* REG_0F0D */
3366   {
3367     { "prefetch",       { Mb }, 0 },
3368     { "prefetchw",      { Mb }, 0 },
3369     { "prefetchwt1",    { Mb }, 0 },
3370     { "prefetch",       { Mb }, 0 },
3371     { "prefetch",       { Mb }, 0 },
3372     { "prefetch",       { Mb }, 0 },
3373     { "prefetch",       { Mb }, 0 },
3374     { "prefetch",       { Mb }, 0 },
3375   },
3376   /* REG_0F18 */
3377   {
3378     { MOD_TABLE (MOD_0F18_REG_0) },
3379     { MOD_TABLE (MOD_0F18_REG_1) },
3380     { MOD_TABLE (MOD_0F18_REG_2) },
3381     { MOD_TABLE (MOD_0F18_REG_3) },
3382     { MOD_TABLE (MOD_0F18_REG_4) },
3383     { MOD_TABLE (MOD_0F18_REG_5) },
3384     { MOD_TABLE (MOD_0F18_REG_6) },
3385     { MOD_TABLE (MOD_0F18_REG_7) },
3386   },
3387   /* REG_0F1C_P_0_MOD_0 */
3388   {
3389     { "cldemote",       { Mb }, 0 },
3390     { "nopQ",           { Ev }, 0 },
3391     { "nopQ",           { Ev }, 0 },
3392     { "nopQ",           { Ev }, 0 },
3393     { "nopQ",           { Ev }, 0 },
3394     { "nopQ",           { Ev }, 0 },
3395     { "nopQ",           { Ev }, 0 },
3396     { "nopQ",           { Ev }, 0 },
3397   },
3398   /* REG_0F1E_P_1_MOD_3 */
3399   {
3400     { "nopQ",           { Ev }, 0 },
3401     { "rdsspK",         { Rdq }, PREFIX_OPCODE },
3402     { "nopQ",           { Ev }, 0 },
3403     { "nopQ",           { Ev }, 0 },
3404     { "nopQ",           { Ev }, 0 },
3405     { "nopQ",           { Ev }, 0 },
3406     { "nopQ",           { Ev }, 0 },
3407     { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) },
3408   },
3409   /* REG_0F71 */
3410   {
3411     { Bad_Opcode },
3412     { Bad_Opcode },
3413     { MOD_TABLE (MOD_0F71_REG_2) },
3414     { Bad_Opcode },
3415     { MOD_TABLE (MOD_0F71_REG_4) },
3416     { Bad_Opcode },
3417     { MOD_TABLE (MOD_0F71_REG_6) },
3418   },
3419   /* REG_0F72 */
3420   {
3421     { Bad_Opcode },
3422     { Bad_Opcode },
3423     { MOD_TABLE (MOD_0F72_REG_2) },
3424     { Bad_Opcode },
3425     { MOD_TABLE (MOD_0F72_REG_4) },
3426     { Bad_Opcode },
3427     { MOD_TABLE (MOD_0F72_REG_6) },
3428   },
3429   /* REG_0F73 */
3430   {
3431     { Bad_Opcode },
3432     { Bad_Opcode },
3433     { MOD_TABLE (MOD_0F73_REG_2) },
3434     { MOD_TABLE (MOD_0F73_REG_3) },
3435     { Bad_Opcode },
3436     { Bad_Opcode },
3437     { MOD_TABLE (MOD_0F73_REG_6) },
3438     { MOD_TABLE (MOD_0F73_REG_7) },
3439   },
3440   /* REG_0FA6 */
3441   {
3442     { "montmul",        { { OP_0f07, 0 } }, 0 },
3443     { "xsha1",          { { OP_0f07, 0 } }, 0 },
3444     { "xsha256",        { { OP_0f07, 0 } }, 0 },
3445   },
3446   /* REG_0FA7 */
3447   {
3448     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
3449     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
3450     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
3451     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
3452     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
3453     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
3454   },
3455   /* REG_0FAE */
3456   {
3457     { MOD_TABLE (MOD_0FAE_REG_0) },
3458     { MOD_TABLE (MOD_0FAE_REG_1) },
3459     { MOD_TABLE (MOD_0FAE_REG_2) },
3460     { MOD_TABLE (MOD_0FAE_REG_3) },
3461     { MOD_TABLE (MOD_0FAE_REG_4) },
3462     { MOD_TABLE (MOD_0FAE_REG_5) },
3463     { MOD_TABLE (MOD_0FAE_REG_6) },
3464     { MOD_TABLE (MOD_0FAE_REG_7) },
3465   },
3466   /* REG_0FBA */
3467   {
3468     { Bad_Opcode },
3469     { Bad_Opcode },
3470     { Bad_Opcode },
3471     { Bad_Opcode },
3472     { "btQ",    { Ev, Ib }, 0 },
3473     { "btsQ",   { Evh1, Ib }, 0 },
3474     { "btrQ",   { Evh1, Ib }, 0 },
3475     { "btcQ",   { Evh1, Ib }, 0 },
3476   },
3477   /* REG_0FC7 */
3478   {
3479     { Bad_Opcode },
3480     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3481     { Bad_Opcode },
3482     { MOD_TABLE (MOD_0FC7_REG_3) },
3483     { MOD_TABLE (MOD_0FC7_REG_4) },
3484     { MOD_TABLE (MOD_0FC7_REG_5) },
3485     { MOD_TABLE (MOD_0FC7_REG_6) },
3486     { MOD_TABLE (MOD_0FC7_REG_7) },
3487   },
3488   /* REG_VEX_0F71 */
3489   {
3490     { Bad_Opcode },
3491     { Bad_Opcode },
3492     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3493     { Bad_Opcode },
3494     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3495     { Bad_Opcode },
3496     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3497   },
3498   /* REG_VEX_0F72 */
3499   {
3500     { Bad_Opcode },
3501     { Bad_Opcode },
3502     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3503     { Bad_Opcode },
3504     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3505     { Bad_Opcode },
3506     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3507   },
3508   /* REG_VEX_0F73 */
3509   {
3510     { Bad_Opcode },
3511     { Bad_Opcode },
3512     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3513     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3514     { Bad_Opcode },
3515     { Bad_Opcode },
3516     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3517     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3518   },
3519   /* REG_VEX_0FAE */
3520   {
3521     { Bad_Opcode },
3522     { Bad_Opcode },
3523     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3524     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3525   },
3526   /* REG_VEX_0F3849_X86_64_P_0_W_0_M_1 */
3527   {
3528     { RM_TABLE (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0) },
3529   },
3530   /* REG_VEX_0F38F3 */
3531   {
3532     { Bad_Opcode },
3533     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3534     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3535     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3536   },
3537   /* REG_0FXOP_09_01_L_0 */
3538   {
3539     { Bad_Opcode },
3540     { "blcfill",        { VexGdq, Edq }, 0 },
3541     { "blsfill",        { VexGdq, Edq }, 0 },
3542     { "blcs",   { VexGdq, Edq }, 0 },
3543     { "tzmsk",  { VexGdq, Edq }, 0 },
3544     { "blcic",  { VexGdq, Edq }, 0 },
3545     { "blsic",  { VexGdq, Edq }, 0 },
3546     { "t1mskc", { VexGdq, Edq }, 0 },
3547   },
3548   /* REG_0FXOP_09_02_L_0 */
3549   {
3550     { Bad_Opcode },
3551     { "blcmsk", { VexGdq, Edq }, 0 },
3552     { Bad_Opcode },
3553     { Bad_Opcode },
3554     { Bad_Opcode },
3555     { Bad_Opcode },
3556     { "blci",   { VexGdq, Edq }, 0 },
3557   },
3558   /* REG_0FXOP_09_12_M_1_L_0 */
3559   {
3560     { "llwpcb", { Edq }, 0 },
3561     { "slwpcb", { Edq }, 0 },
3562   },
3563   /* REG_0FXOP_0A_12_L_0 */
3564   {
3565     { "lwpins", { VexGdq, Ed, Id }, 0 },
3566     { "lwpval", { VexGdq, Ed, Id }, 0 },
3567   },
3568
3569 #include "i386-dis-evex-reg.h"
3570 };
3571
3572 static const struct dis386 prefix_table[][4] = {
3573   /* PREFIX_90 */
3574   {
3575     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3576     { "pause", { XX }, 0 },
3577     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3578     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3579   },
3580
3581   /* PREFIX_0F01_REG_3_RM_1 */
3582   {
3583     { "vmmcall",        { Skip_MODRM }, 0 },
3584     { "vmgexit",        { Skip_MODRM }, 0 },
3585     { Bad_Opcode },
3586     { "vmgexit",        { Skip_MODRM }, 0 },
3587   },
3588
3589   /* PREFIX_0F01_REG_5_MOD_0 */
3590   {
3591     { Bad_Opcode },
3592     { "rstorssp",       { Mq }, PREFIX_OPCODE },
3593   },
3594
3595   /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3596   {
3597     { "serialize",      { Skip_MODRM }, PREFIX_OPCODE },
3598     { "setssbsy",       { Skip_MODRM }, PREFIX_OPCODE },
3599     { Bad_Opcode },
3600     { "xsusldtrk",      { Skip_MODRM }, PREFIX_OPCODE },
3601   },
3602
3603   /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
3604   {
3605     { Bad_Opcode },
3606     { Bad_Opcode },
3607     { Bad_Opcode },
3608     { "xresldtrk",     { Skip_MODRM }, PREFIX_OPCODE },
3609   },
3610
3611   /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3612   {
3613     { Bad_Opcode },
3614     { "saveprevssp",    { Skip_MODRM }, PREFIX_OPCODE },
3615   },
3616
3617   /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3618   {
3619     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
3620     { "mcommit",        { Skip_MODRM }, 0 },
3621   },
3622
3623   /* PREFIX_0F01_REG_7_MOD_3_RM_3 */
3624   {
3625     { "mwaitx",         { { OP_Mwait, eBX_reg } }, 0  },
3626   },
3627
3628   /* PREFIX_0F09 */
3629   {
3630     { "wbinvd",   { XX }, 0 },
3631     { "wbnoinvd", { XX }, 0 },
3632   },
3633
3634   /* PREFIX_0F10 */
3635   {
3636     { "movups", { XM, EXx }, PREFIX_OPCODE },
3637     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3638     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3639     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3640   },
3641
3642   /* PREFIX_0F11 */
3643   {
3644     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3645     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3646     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3647     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3648   },
3649
3650   /* PREFIX_0F12 */
3651   {
3652     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3653     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3654     { MOD_TABLE (MOD_0F12_PREFIX_2) },
3655     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3656   },
3657
3658   /* PREFIX_0F16 */
3659   {
3660     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3661     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3662     { MOD_TABLE (MOD_0F16_PREFIX_2) },
3663   },
3664
3665   /* PREFIX_0F1A */
3666   {
3667     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3668     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3669     { "bndmov", { Gbnd, Ebnd }, 0 },
3670     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3671   },
3672
3673   /* PREFIX_0F1B */
3674   {
3675     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3676     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3677     { "bndmov", { EbndS, Gbnd }, 0 },
3678     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3679   },
3680
3681   /* PREFIX_0F1C */
3682   {
3683     { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3684     { "nopQ",   { Ev }, PREFIX_OPCODE },
3685     { "nopQ",   { Ev }, PREFIX_OPCODE },
3686     { "nopQ",   { Ev }, PREFIX_OPCODE },
3687   },
3688
3689   /* PREFIX_0F1E */
3690   {
3691     { "nopQ",   { Ev }, PREFIX_OPCODE },
3692     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3693     { "nopQ",   { Ev }, PREFIX_OPCODE },
3694     { "nopQ",   { Ev }, PREFIX_OPCODE },
3695   },
3696
3697   /* PREFIX_0F2A */
3698   {
3699     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3700     { "cvtsi2ss{%LQ|}", { XM, Edq }, PREFIX_OPCODE },
3701     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3702     { "cvtsi2sd{%LQ|}", { XM, Edq }, 0 },
3703   },
3704
3705   /* PREFIX_0F2B */
3706   {
3707     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3708     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3709     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3710     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3711   },
3712
3713   /* PREFIX_0F2C */
3714   {
3715     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3716     { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
3717     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3718     { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3719   },
3720
3721   /* PREFIX_0F2D */
3722   {
3723     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3724     { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
3725     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3726     { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3727   },
3728
3729   /* PREFIX_0F2E */
3730   {
3731     { "ucomiss",{ XM, EXd }, 0 },
3732     { Bad_Opcode },
3733     { "ucomisd",{ XM, EXq }, 0 },
3734   },
3735
3736   /* PREFIX_0F2F */
3737   {
3738     { "comiss", { XM, EXd }, 0 },
3739     { Bad_Opcode },
3740     { "comisd", { XM, EXq }, 0 },
3741   },
3742
3743   /* PREFIX_0F51 */
3744   {
3745     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3746     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3747     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3748     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3749   },
3750
3751   /* PREFIX_0F52 */
3752   {
3753     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3754     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3755   },
3756
3757   /* PREFIX_0F53 */
3758   {
3759     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3760     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3761   },
3762
3763   /* PREFIX_0F58 */
3764   {
3765     { "addps", { XM, EXx }, PREFIX_OPCODE },
3766     { "addss", { XM, EXd }, PREFIX_OPCODE },
3767     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3768     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3769   },
3770
3771   /* PREFIX_0F59 */
3772   {
3773     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3774     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3775     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3776     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3777   },
3778
3779   /* PREFIX_0F5A */
3780   {
3781     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3782     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3783     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3784     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3785   },
3786
3787   /* PREFIX_0F5B */
3788   {
3789     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3790     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3791     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3792   },
3793
3794   /* PREFIX_0F5C */
3795   {
3796     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3797     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3798     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3799     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3800   },
3801
3802   /* PREFIX_0F5D */
3803   {
3804     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3805     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3806     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3807     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3808   },
3809
3810   /* PREFIX_0F5E */
3811   {
3812     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3813     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3814     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3815     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3816   },
3817
3818   /* PREFIX_0F5F */
3819   {
3820     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3821     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3822     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3823     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3824   },
3825
3826   /* PREFIX_0F60 */
3827   {
3828     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3829     { Bad_Opcode },
3830     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3831   },
3832
3833   /* PREFIX_0F61 */
3834   {
3835     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3836     { Bad_Opcode },
3837     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3838   },
3839
3840   /* PREFIX_0F62 */
3841   {
3842     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3843     { Bad_Opcode },
3844     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3845   },
3846
3847   /* PREFIX_0F6C */
3848   {
3849     { Bad_Opcode },
3850     { Bad_Opcode },
3851     { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
3852   },
3853
3854   /* PREFIX_0F6D */
3855   {
3856     { Bad_Opcode },
3857     { Bad_Opcode },
3858     { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
3859   },
3860
3861   /* PREFIX_0F6F */
3862   {
3863     { "movq",   { MX, EM }, PREFIX_OPCODE },
3864     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3865     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3866   },
3867
3868   /* PREFIX_0F70 */
3869   {
3870     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3871     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3872     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3873     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3874   },
3875
3876   /* PREFIX_0F73_REG_3 */
3877   {
3878     { Bad_Opcode },
3879     { Bad_Opcode },
3880     { "psrldq", { XS, Ib }, 0 },
3881   },
3882
3883   /* PREFIX_0F73_REG_7 */
3884   {
3885     { Bad_Opcode },
3886     { Bad_Opcode },
3887     { "pslldq", { XS, Ib }, 0 },
3888   },
3889
3890   /* PREFIX_0F78 */
3891   {
3892     {"vmread",  { Em, Gm }, 0 },
3893     { Bad_Opcode },
3894     {"extrq",   { XS, Ib, Ib }, 0 },
3895     {"insertq", { XM, XS, Ib, Ib }, 0 },
3896   },
3897
3898   /* PREFIX_0F79 */
3899   {
3900     {"vmwrite", { Gm, Em }, 0 },
3901     { Bad_Opcode },
3902     {"extrq",   { XM, XS }, 0 },
3903     {"insertq", { XM, XS }, 0 },
3904   },
3905
3906   /* PREFIX_0F7C */
3907   {
3908     { Bad_Opcode },
3909     { Bad_Opcode },
3910     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3911     { "haddps", { XM, EXx }, PREFIX_OPCODE },
3912   },
3913
3914   /* PREFIX_0F7D */
3915   {
3916     { Bad_Opcode },
3917     { Bad_Opcode },
3918     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3919     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3920   },
3921
3922   /* PREFIX_0F7E */
3923   {
3924     { "movK",   { Edq, MX }, PREFIX_OPCODE },
3925     { "movq",   { XM, EXq }, PREFIX_OPCODE },
3926     { "movK",   { Edq, XM }, PREFIX_OPCODE },
3927   },
3928
3929   /* PREFIX_0F7F */
3930   {
3931     { "movq",   { EMS, MX }, PREFIX_OPCODE },
3932     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3933     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3934   },
3935
3936   /* PREFIX_0FAE_REG_0_MOD_3 */
3937   {
3938     { Bad_Opcode },
3939     { "rdfsbase", { Ev }, 0 },
3940   },
3941
3942   /* PREFIX_0FAE_REG_1_MOD_3 */
3943   {
3944     { Bad_Opcode },
3945     { "rdgsbase", { Ev }, 0 },
3946   },
3947
3948   /* PREFIX_0FAE_REG_2_MOD_3 */
3949   {
3950     { Bad_Opcode },
3951     { "wrfsbase", { Ev }, 0 },
3952   },
3953
3954   /* PREFIX_0FAE_REG_3_MOD_3 */
3955   {
3956     { Bad_Opcode },
3957     { "wrgsbase", { Ev }, 0 },
3958   },
3959
3960   /* PREFIX_0FAE_REG_4_MOD_0 */
3961   {
3962     { "xsave",  { FXSAVE }, 0 },
3963     { "ptwrite{%LQ|}", { Edq }, 0 },
3964   },
3965
3966   /* PREFIX_0FAE_REG_4_MOD_3 */
3967   {
3968     { Bad_Opcode },
3969     { "ptwrite{%LQ|}", { Edq }, 0 },
3970   },
3971
3972   /* PREFIX_0FAE_REG_5_MOD_0 */
3973   {
3974     { "xrstor",         { FXSAVE }, PREFIX_OPCODE },
3975   },
3976
3977   /* PREFIX_0FAE_REG_5_MOD_3 */
3978   {
3979     { "lfence",         { Skip_MODRM }, 0 },
3980     { "incsspK",        { Rdq }, PREFIX_OPCODE },
3981   },
3982
3983   /* PREFIX_0FAE_REG_6_MOD_0 */
3984   {
3985     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE },
3986     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
3987     { "clwb",   { Mb }, PREFIX_OPCODE },
3988   },
3989
3990   /* PREFIX_0FAE_REG_6_MOD_3 */
3991   {
3992     { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) },
3993     { "umonitor",       { Eva }, PREFIX_OPCODE },
3994     { "tpause", { Edq }, PREFIX_OPCODE },
3995     { "umwait", { Edq }, PREFIX_OPCODE },
3996   },
3997
3998   /* PREFIX_0FAE_REG_7_MOD_0 */
3999   {
4000     { "clflush",        { Mb }, 0 },
4001     { Bad_Opcode },
4002     { "clflushopt",     { Mb }, 0 },
4003   },
4004
4005   /* PREFIX_0FB8 */
4006   {
4007     { Bad_Opcode },
4008     { "popcntS", { Gv, Ev }, 0 },
4009   },
4010
4011   /* PREFIX_0FBC */
4012   {
4013     { "bsfS",   { Gv, Ev }, 0 },
4014     { "tzcntS", { Gv, Ev }, 0 },
4015     { "bsfS",   { Gv, Ev }, 0 },
4016   },
4017
4018   /* PREFIX_0FBD */
4019   {
4020     { "bsrS",   { Gv, Ev }, 0 },
4021     { "lzcntS", { Gv, Ev }, 0 },
4022     { "bsrS",   { Gv, Ev }, 0 },
4023   },
4024
4025   /* PREFIX_0FC2 */
4026   {
4027     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
4028     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
4029     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
4030     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
4031   },
4032
4033   /* PREFIX_0FC3_MOD_0 */
4034   {
4035     { "movntiS", { Edq, Gdq }, PREFIX_OPCODE },
4036   },
4037
4038   /* PREFIX_0FC7_REG_6_MOD_0 */
4039   {
4040     { "vmptrld",{ Mq }, 0 },
4041     { "vmxon",  { Mq }, 0 },
4042     { "vmclear",{ Mq }, 0 },
4043   },
4044
4045   /* PREFIX_0FC7_REG_6_MOD_3 */
4046   {
4047     { "rdrand", { Ev }, 0 },
4048     { Bad_Opcode },
4049     { "rdrand", { Ev }, 0 }
4050   },
4051
4052   /* PREFIX_0FC7_REG_7_MOD_3 */
4053   {
4054     { "rdseed", { Ev }, 0 },
4055     { "rdpid",  { Em }, 0 },
4056     { "rdseed", { Ev }, 0 },
4057   },
4058
4059   /* PREFIX_0FD0 */
4060   {
4061     { Bad_Opcode },
4062     { Bad_Opcode },
4063     { "addsubpd", { XM, EXx }, 0 },
4064     { "addsubps", { XM, EXx }, 0 },
4065   },
4066
4067   /* PREFIX_0FD6 */
4068   {
4069     { Bad_Opcode },
4070     { "movq2dq",{ XM, MS }, 0 },
4071     { "movq",   { EXqS, XM }, 0 },
4072     { "movdq2q",{ MX, XS }, 0 },
4073   },
4074
4075   /* PREFIX_0FE6 */
4076   {
4077     { Bad_Opcode },
4078     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4079     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4080     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4081   },
4082
4083   /* PREFIX_0FE7 */
4084   {
4085     { "movntq", { Mq, MX }, PREFIX_OPCODE },
4086     { Bad_Opcode },
4087     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4088   },
4089
4090   /* PREFIX_0FF0 */
4091   {
4092     { Bad_Opcode },
4093     { Bad_Opcode },
4094     { Bad_Opcode },
4095     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4096   },
4097
4098   /* PREFIX_0FF7 */
4099   {
4100     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4101     { Bad_Opcode },
4102     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4103   },
4104
4105   /* PREFIX_0F3810 */
4106   {
4107     { Bad_Opcode },
4108     { Bad_Opcode },
4109     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4110   },
4111
4112   /* PREFIX_0F3814 */
4113   {
4114     { Bad_Opcode },
4115     { Bad_Opcode },
4116     { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4117   },
4118
4119   /* PREFIX_0F3815 */
4120   {
4121     { Bad_Opcode },
4122     { Bad_Opcode },
4123     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4124   },
4125
4126   /* PREFIX_0F3817 */
4127   {
4128     { Bad_Opcode },
4129     { Bad_Opcode },
4130     { "ptest",  { XM, EXx }, PREFIX_OPCODE },
4131   },
4132
4133   /* PREFIX_0F3820 */
4134   {
4135     { Bad_Opcode },
4136     { Bad_Opcode },
4137     { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4138   },
4139
4140   /* PREFIX_0F3821 */
4141   {
4142     { Bad_Opcode },
4143     { Bad_Opcode },
4144     { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4145   },
4146
4147   /* PREFIX_0F3822 */
4148   {
4149     { Bad_Opcode },
4150     { Bad_Opcode },
4151     { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4152   },
4153
4154   /* PREFIX_0F3823 */
4155   {
4156     { Bad_Opcode },
4157     { Bad_Opcode },
4158     { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4159   },
4160
4161   /* PREFIX_0F3824 */
4162   {
4163     { Bad_Opcode },
4164     { Bad_Opcode },
4165     { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4166   },
4167
4168   /* PREFIX_0F3825 */
4169   {
4170     { Bad_Opcode },
4171     { Bad_Opcode },
4172     { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4173   },
4174
4175   /* PREFIX_0F3828 */
4176   {
4177     { Bad_Opcode },
4178     { Bad_Opcode },
4179     { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4180   },
4181
4182   /* PREFIX_0F3829 */
4183   {
4184     { Bad_Opcode },
4185     { Bad_Opcode },
4186     { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4187   },
4188
4189   /* PREFIX_0F382A */
4190   {
4191     { Bad_Opcode },
4192     { Bad_Opcode },
4193     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4194   },
4195
4196   /* PREFIX_0F382B */
4197   {
4198     { Bad_Opcode },
4199     { Bad_Opcode },
4200     { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4201   },
4202
4203   /* PREFIX_0F3830 */
4204   {
4205     { Bad_Opcode },
4206     { Bad_Opcode },
4207     { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4208   },
4209
4210   /* PREFIX_0F3831 */
4211   {
4212     { Bad_Opcode },
4213     { Bad_Opcode },
4214     { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4215   },
4216
4217   /* PREFIX_0F3832 */
4218   {
4219     { Bad_Opcode },
4220     { Bad_Opcode },
4221     { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4222   },
4223
4224   /* PREFIX_0F3833 */
4225   {
4226     { Bad_Opcode },
4227     { Bad_Opcode },
4228     { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4229   },
4230
4231   /* PREFIX_0F3834 */
4232   {
4233     { Bad_Opcode },
4234     { Bad_Opcode },
4235     { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4236   },
4237
4238   /* PREFIX_0F3835 */
4239   {
4240     { Bad_Opcode },
4241     { Bad_Opcode },
4242     { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4243   },
4244
4245   /* PREFIX_0F3837 */
4246   {
4247     { Bad_Opcode },
4248     { Bad_Opcode },
4249     { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4250   },
4251
4252   /* PREFIX_0F3838 */
4253   {
4254     { Bad_Opcode },
4255     { Bad_Opcode },
4256     { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4257   },
4258
4259   /* PREFIX_0F3839 */
4260   {
4261     { Bad_Opcode },
4262     { Bad_Opcode },
4263     { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4264   },
4265
4266   /* PREFIX_0F383A */
4267   {
4268     { Bad_Opcode },
4269     { Bad_Opcode },
4270     { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4271   },
4272
4273   /* PREFIX_0F383B */
4274   {
4275     { Bad_Opcode },
4276     { Bad_Opcode },
4277     { "pminud", { XM, EXx }, PREFIX_OPCODE },
4278   },
4279
4280   /* PREFIX_0F383C */
4281   {
4282     { Bad_Opcode },
4283     { Bad_Opcode },
4284     { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4285   },
4286
4287   /* PREFIX_0F383D */
4288   {
4289     { Bad_Opcode },
4290     { Bad_Opcode },
4291     { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4292   },
4293
4294   /* PREFIX_0F383E */
4295   {
4296     { Bad_Opcode },
4297     { Bad_Opcode },
4298     { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4299   },
4300
4301   /* PREFIX_0F383F */
4302   {
4303     { Bad_Opcode },
4304     { Bad_Opcode },
4305     { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4306   },
4307
4308   /* PREFIX_0F3840 */
4309   {
4310     { Bad_Opcode },
4311     { Bad_Opcode },
4312     { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4313   },
4314
4315   /* PREFIX_0F3841 */
4316   {
4317     { Bad_Opcode },
4318     { Bad_Opcode },
4319     { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4320   },
4321
4322   /* PREFIX_0F3880 */
4323   {
4324     { Bad_Opcode },
4325     { Bad_Opcode },
4326     { "invept", { Gm, Mo }, PREFIX_OPCODE },
4327   },
4328
4329   /* PREFIX_0F3881 */
4330   {
4331     { Bad_Opcode },
4332     { Bad_Opcode },
4333     { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4334   },
4335
4336   /* PREFIX_0F3882 */
4337   {
4338     { Bad_Opcode },
4339     { Bad_Opcode },
4340     { "invpcid", { Gm, M }, PREFIX_OPCODE },
4341   },
4342
4343   /* PREFIX_0F38C8 */
4344   {
4345     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4346   },
4347
4348   /* PREFIX_0F38C9 */
4349   {
4350     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4351   },
4352
4353   /* PREFIX_0F38CA */
4354   {
4355     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4356   },
4357
4358   /* PREFIX_0F38CB */
4359   {
4360     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4361   },
4362
4363   /* PREFIX_0F38CC */
4364   {
4365     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4366   },
4367
4368   /* PREFIX_0F38CD */
4369   {
4370     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4371   },
4372
4373   /* PREFIX_0F38CF */
4374   {
4375     { Bad_Opcode },
4376     { Bad_Opcode },
4377     { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE },
4378   },
4379
4380   /* PREFIX_0F38DB */
4381   {
4382     { Bad_Opcode },
4383     { Bad_Opcode },
4384     { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4385   },
4386
4387   /* PREFIX_0F38DC */
4388   {
4389     { Bad_Opcode },
4390     { Bad_Opcode },
4391     { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4392   },
4393
4394   /* PREFIX_0F38DD */
4395   {
4396     { Bad_Opcode },
4397     { Bad_Opcode },
4398     { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4399   },
4400
4401   /* PREFIX_0F38DE */
4402   {
4403     { Bad_Opcode },
4404     { Bad_Opcode },
4405     { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4406   },
4407
4408   /* PREFIX_0F38DF */
4409   {
4410     { Bad_Opcode },
4411     { Bad_Opcode },
4412     { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4413   },
4414
4415   /* PREFIX_0F38F0 */
4416   {
4417     { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
4418     { Bad_Opcode },
4419     { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
4420     { "crc32A", { Gdq, Eb }, PREFIX_OPCODE },
4421   },
4422
4423   /* PREFIX_0F38F1 */
4424   {
4425     { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
4426     { Bad_Opcode },
4427     { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
4428     { "crc32Q", { Gdq, Ev }, PREFIX_OPCODE },
4429   },
4430
4431   /* PREFIX_0F38F5 */
4432   {
4433     { Bad_Opcode },
4434     { Bad_Opcode },
4435     { MOD_TABLE (MOD_0F38F5_PREFIX_2) },
4436   },
4437
4438   /* PREFIX_0F38F6 */
4439   {
4440     { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
4441     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
4442     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
4443     { Bad_Opcode },
4444   },
4445
4446   /* PREFIX_0F38F8 */
4447   {
4448     { Bad_Opcode },
4449     { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
4450     { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
4451     { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
4452   },
4453
4454   /* PREFIX_0F38F9 */
4455   {
4456     { MOD_TABLE (MOD_0F38F9_PREFIX_0) },
4457   },
4458
4459   /* PREFIX_0F3A08 */
4460   {
4461     { Bad_Opcode },
4462     { Bad_Opcode },
4463     { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4464   },
4465
4466   /* PREFIX_0F3A09 */
4467   {
4468     { Bad_Opcode },
4469     { Bad_Opcode },
4470     { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4471   },
4472
4473   /* PREFIX_0F3A0A */
4474   {
4475     { Bad_Opcode },
4476     { Bad_Opcode },
4477     { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4478   },
4479
4480   /* PREFIX_0F3A0B */
4481   {
4482     { Bad_Opcode },
4483     { Bad_Opcode },
4484     { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4485   },
4486
4487   /* PREFIX_0F3A0C */
4488   {
4489     { Bad_Opcode },
4490     { Bad_Opcode },
4491     { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4492   },
4493
4494   /* PREFIX_0F3A0D */
4495   {
4496     { Bad_Opcode },
4497     { Bad_Opcode },
4498     { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4499   },
4500
4501   /* PREFIX_0F3A0E */
4502   {
4503     { Bad_Opcode },
4504     { Bad_Opcode },
4505     { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4506   },
4507
4508   /* PREFIX_0F3A14 */
4509   {
4510     { Bad_Opcode },
4511     { Bad_Opcode },
4512     { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4513   },
4514
4515   /* PREFIX_0F3A15 */
4516   {
4517     { Bad_Opcode },
4518     { Bad_Opcode },
4519     { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4520   },
4521
4522   /* PREFIX_0F3A16 */
4523   {
4524     { Bad_Opcode },
4525     { Bad_Opcode },
4526     { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4527   },
4528
4529   /* PREFIX_0F3A17 */
4530   {
4531     { Bad_Opcode },
4532     { Bad_Opcode },
4533     { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4534   },
4535
4536   /* PREFIX_0F3A20 */
4537   {
4538     { Bad_Opcode },
4539     { Bad_Opcode },
4540     { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4541   },
4542
4543   /* PREFIX_0F3A21 */
4544   {
4545     { Bad_Opcode },
4546     { Bad_Opcode },
4547     { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4548   },
4549
4550   /* PREFIX_0F3A22 */
4551   {
4552     { Bad_Opcode },
4553     { Bad_Opcode },
4554     { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4555   },
4556
4557   /* PREFIX_0F3A40 */
4558   {
4559     { Bad_Opcode },
4560     { Bad_Opcode },
4561     { "dpps",   { XM, EXx, Ib }, PREFIX_OPCODE },
4562   },
4563
4564   /* PREFIX_0F3A41 */
4565   {
4566     { Bad_Opcode },
4567     { Bad_Opcode },
4568     { "dppd",   { XM, EXx, Ib }, PREFIX_OPCODE },
4569   },
4570
4571   /* PREFIX_0F3A42 */
4572   {
4573     { Bad_Opcode },
4574     { Bad_Opcode },
4575     { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4576   },
4577
4578   /* PREFIX_0F3A44 */
4579   {
4580     { Bad_Opcode },
4581     { Bad_Opcode },
4582     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4583   },
4584
4585   /* PREFIX_0F3A60 */
4586   {
4587     { Bad_Opcode },
4588     { Bad_Opcode },
4589     { "pcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_OPCODE },
4590   },
4591
4592   /* PREFIX_0F3A61 */
4593   {
4594     { Bad_Opcode },
4595     { Bad_Opcode },
4596     { "pcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_OPCODE },
4597   },
4598
4599   /* PREFIX_0F3A62 */
4600   {
4601     { Bad_Opcode },
4602     { Bad_Opcode },
4603     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4604   },
4605
4606   /* PREFIX_0F3A63 */
4607   {
4608     { Bad_Opcode },
4609     { Bad_Opcode },
4610     { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4611   },
4612
4613   /* PREFIX_0F3ACC */
4614   {
4615     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4616   },
4617
4618   /* PREFIX_0F3ACE */
4619   {
4620     { Bad_Opcode },
4621     { Bad_Opcode },
4622     { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4623   },
4624
4625   /* PREFIX_0F3ACF */
4626   {
4627     { Bad_Opcode },
4628     { Bad_Opcode },
4629     { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4630   },
4631
4632   /* PREFIX_0F3ADF */
4633   {
4634     { Bad_Opcode },
4635     { Bad_Opcode },
4636     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4637   },
4638
4639   /* PREFIX_VEX_0F10 */
4640   {
4641     { "vmovups",        { XM, EXx }, 0 },
4642     { "vmovss",         { XMVexScalar, VexScalar, EXxmm_md }, 0 },
4643     { "vmovupd",        { XM, EXx }, 0 },
4644     { "vmovsd",         { XMVexScalar, VexScalar, EXxmm_mq }, 0 },
4645   },
4646
4647   /* PREFIX_VEX_0F11 */
4648   {
4649     { "vmovups",        { EXxS, XM }, 0 },
4650     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar }, 0 },
4651     { "vmovupd",        { EXxS, XM }, 0 },
4652     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar }, 0 },
4653   },
4654
4655   /* PREFIX_VEX_0F12 */
4656   {
4657     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4658     { "vmovsldup",      { XM, EXx }, 0 },
4659     { MOD_TABLE (MOD_VEX_0F12_PREFIX_2) },
4660     { "vmovddup",       { XM, EXymmq }, 0 },
4661   },
4662
4663   /* PREFIX_VEX_0F16 */
4664   {
4665     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4666     { "vmovshdup",      { XM, EXx }, 0 },
4667     { MOD_TABLE (MOD_VEX_0F16_PREFIX_2) },
4668   },
4669
4670   /* PREFIX_VEX_0F2A */
4671   {
4672     { Bad_Opcode },
4673     { "vcvtsi2ss{%LQ|}",        { XMScalar, VexScalar, Edq }, 0 },
4674     { Bad_Opcode },
4675     { "vcvtsi2sd{%LQ|}",        { XMScalar, VexScalar, Edq }, 0 },
4676   },
4677
4678   /* PREFIX_VEX_0F2C */
4679   {
4680     { Bad_Opcode },
4681     { "vcvttss2si",     { Gdq, EXxmm_md }, 0 },
4682     { Bad_Opcode },
4683     { "vcvttsd2si",     { Gdq, EXxmm_mq }, 0 },
4684   },
4685
4686   /* PREFIX_VEX_0F2D */
4687   {
4688     { Bad_Opcode },
4689     { "vcvtss2si",      { Gdq, EXxmm_md }, 0 },
4690     { Bad_Opcode },
4691     { "vcvtsd2si",      { Gdq, EXxmm_mq }, 0 },
4692   },
4693
4694   /* PREFIX_VEX_0F2E */
4695   {
4696     { "vucomiss",       { XMScalar, EXxmm_md }, 0 },
4697     { Bad_Opcode },
4698     { "vucomisd",       { XMScalar, EXxmm_mq }, 0 },
4699   },
4700
4701   /* PREFIX_VEX_0F2F */
4702   {
4703     { "vcomiss",        { XMScalar, EXxmm_md }, 0 },
4704     { Bad_Opcode },
4705     { "vcomisd",        { XMScalar, EXxmm_mq }, 0 },
4706   },
4707
4708   /* PREFIX_VEX_0F41 */
4709   {
4710     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4711     { Bad_Opcode },
4712     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4713   },
4714
4715   /* PREFIX_VEX_0F42 */
4716   {
4717     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4718     { Bad_Opcode },
4719     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4720   },
4721
4722   /* PREFIX_VEX_0F44 */
4723   {
4724     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4725     { Bad_Opcode },
4726     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4727   },
4728
4729   /* PREFIX_VEX_0F45 */
4730   {
4731     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4732     { Bad_Opcode },
4733     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4734   },
4735
4736   /* PREFIX_VEX_0F46 */
4737   {
4738     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4739     { Bad_Opcode },
4740     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4741   },
4742
4743   /* PREFIX_VEX_0F47 */
4744   {
4745     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4746     { Bad_Opcode },
4747     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4748   },
4749
4750   /* PREFIX_VEX_0F4A */
4751   {
4752     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4753     { Bad_Opcode },
4754     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4755   },
4756
4757   /* PREFIX_VEX_0F4B */
4758   {
4759     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4760     { Bad_Opcode },
4761     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4762   },
4763
4764   /* PREFIX_VEX_0F51 */
4765   {
4766     { "vsqrtps",        { XM, EXx }, 0 },
4767     { "vsqrtss",        { XMScalar, VexScalar, EXxmm_md }, 0 },
4768     { "vsqrtpd",        { XM, EXx }, 0 },
4769     { "vsqrtsd",        { XMScalar, VexScalar, EXxmm_mq }, 0 },
4770   },
4771
4772   /* PREFIX_VEX_0F52 */
4773   {
4774     { "vrsqrtps",       { XM, EXx }, 0 },
4775     { "vrsqrtss",       { XMScalar, VexScalar, EXxmm_md }, 0 },
4776   },
4777
4778   /* PREFIX_VEX_0F53 */
4779   {
4780     { "vrcpps",         { XM, EXx }, 0 },
4781     { "vrcpss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4782   },
4783
4784   /* PREFIX_VEX_0F58 */
4785   {
4786     { "vaddps",         { XM, Vex, EXx }, 0 },
4787     { "vaddss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4788     { "vaddpd",         { XM, Vex, EXx }, 0 },
4789     { "vaddsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4790   },
4791
4792   /* PREFIX_VEX_0F59 */
4793   {
4794     { "vmulps",         { XM, Vex, EXx }, 0 },
4795     { "vmulss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4796     { "vmulpd",         { XM, Vex, EXx }, 0 },
4797     { "vmulsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4798   },
4799
4800   /* PREFIX_VEX_0F5A */
4801   {
4802     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
4803     { "vcvtss2sd",      { XMScalar, VexScalar, EXxmm_md }, 0 },
4804     { "vcvtpd2ps%XY",{ XMM, EXx }, 0 },
4805     { "vcvtsd2ss",      { XMScalar, VexScalar, EXxmm_mq }, 0 },
4806   },
4807
4808   /* PREFIX_VEX_0F5B */
4809   {
4810     { "vcvtdq2ps",      { XM, EXx }, 0 },
4811     { "vcvttps2dq",     { XM, EXx }, 0 },
4812     { "vcvtps2dq",      { XM, EXx }, 0 },
4813   },
4814
4815   /* PREFIX_VEX_0F5C */
4816   {
4817     { "vsubps",         { XM, Vex, EXx }, 0 },
4818     { "vsubss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4819     { "vsubpd",         { XM, Vex, EXx }, 0 },
4820     { "vsubsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4821   },
4822
4823   /* PREFIX_VEX_0F5D */
4824   {
4825     { "vminps",         { XM, Vex, EXx }, 0 },
4826     { "vminss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4827     { "vminpd",         { XM, Vex, EXx }, 0 },
4828     { "vminsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4829   },
4830
4831   /* PREFIX_VEX_0F5E */
4832   {
4833     { "vdivps",         { XM, Vex, EXx }, 0 },
4834     { "vdivss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4835     { "vdivpd",         { XM, Vex, EXx }, 0 },
4836     { "vdivsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4837   },
4838
4839   /* PREFIX_VEX_0F5F */
4840   {
4841     { "vmaxps",         { XM, Vex, EXx }, 0 },
4842     { "vmaxss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4843     { "vmaxpd",         { XM, Vex, EXx }, 0 },
4844     { "vmaxsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4845   },
4846
4847   /* PREFIX_VEX_0F60 */
4848   {
4849     { Bad_Opcode },
4850     { Bad_Opcode },
4851     { "vpunpcklbw",     { XM, Vex, EXx }, 0 },
4852   },
4853
4854   /* PREFIX_VEX_0F61 */
4855   {
4856     { Bad_Opcode },
4857     { Bad_Opcode },
4858     { "vpunpcklwd",     { XM, Vex, EXx }, 0 },
4859   },
4860
4861   /* PREFIX_VEX_0F62 */
4862   {
4863     { Bad_Opcode },
4864     { Bad_Opcode },
4865     { "vpunpckldq",     { XM, Vex, EXx }, 0 },
4866   },
4867
4868   /* PREFIX_VEX_0F63 */
4869   {
4870     { Bad_Opcode },
4871     { Bad_Opcode },
4872     { "vpacksswb",      { XM, Vex, EXx }, 0 },
4873   },
4874
4875   /* PREFIX_VEX_0F64 */
4876   {
4877     { Bad_Opcode },
4878     { Bad_Opcode },
4879     { "vpcmpgtb",       { XM, Vex, EXx }, 0 },
4880   },
4881
4882   /* PREFIX_VEX_0F65 */
4883   {
4884     { Bad_Opcode },
4885     { Bad_Opcode },
4886     { "vpcmpgtw",       { XM, Vex, EXx }, 0 },
4887   },
4888
4889   /* PREFIX_VEX_0F66 */
4890   {
4891     { Bad_Opcode },
4892     { Bad_Opcode },
4893     { "vpcmpgtd",       { XM, Vex, EXx }, 0 },
4894   },
4895
4896   /* PREFIX_VEX_0F67 */
4897   {
4898     { Bad_Opcode },
4899     { Bad_Opcode },
4900     { "vpackuswb",      { XM, Vex, EXx }, 0 },
4901   },
4902
4903   /* PREFIX_VEX_0F68 */
4904   {
4905     { Bad_Opcode },
4906     { Bad_Opcode },
4907     { "vpunpckhbw",     { XM, Vex, EXx }, 0 },
4908   },
4909
4910   /* PREFIX_VEX_0F69 */
4911   {
4912     { Bad_Opcode },
4913     { Bad_Opcode },
4914     { "vpunpckhwd",     { XM, Vex, EXx }, 0 },
4915   },
4916
4917   /* PREFIX_VEX_0F6A */
4918   {
4919     { Bad_Opcode },
4920     { Bad_Opcode },
4921     { "vpunpckhdq",     { XM, Vex, EXx }, 0 },
4922   },
4923
4924   /* PREFIX_VEX_0F6B */
4925   {
4926     { Bad_Opcode },
4927     { Bad_Opcode },
4928     { "vpackssdw",      { XM, Vex, EXx }, 0 },
4929   },
4930
4931   /* PREFIX_VEX_0F6C */
4932   {
4933     { Bad_Opcode },
4934     { Bad_Opcode },
4935     { "vpunpcklqdq",    { XM, Vex, EXx }, 0 },
4936   },
4937
4938   /* PREFIX_VEX_0F6D */
4939   {
4940     { Bad_Opcode },
4941     { Bad_Opcode },
4942     { "vpunpckhqdq",    { XM, Vex, EXx }, 0 },
4943   },
4944
4945   /* PREFIX_VEX_0F6E */
4946   {
4947     { Bad_Opcode },
4948     { Bad_Opcode },
4949     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4950   },
4951
4952   /* PREFIX_VEX_0F6F */
4953   {
4954     { Bad_Opcode },
4955     { "vmovdqu",        { XM, EXx }, 0 },
4956     { "vmovdqa",        { XM, EXx }, 0 },
4957   },
4958
4959   /* PREFIX_VEX_0F70 */
4960   {
4961     { Bad_Opcode },
4962     { "vpshufhw",       { XM, EXx, Ib }, 0 },
4963     { "vpshufd",        { XM, EXx, Ib }, 0 },
4964     { "vpshuflw",       { XM, EXx, Ib }, 0 },
4965   },
4966
4967   /* PREFIX_VEX_0F71_REG_2 */
4968   {
4969     { Bad_Opcode },
4970     { Bad_Opcode },
4971     { "vpsrlw",         { Vex, XS, Ib }, 0 },
4972   },
4973
4974   /* PREFIX_VEX_0F71_REG_4 */
4975   {
4976     { Bad_Opcode },
4977     { Bad_Opcode },
4978     { "vpsraw",         { Vex, XS, Ib }, 0 },
4979   },
4980
4981   /* PREFIX_VEX_0F71_REG_6 */
4982   {
4983     { Bad_Opcode },
4984     { Bad_Opcode },
4985     { "vpsllw",         { Vex, XS, Ib }, 0 },
4986   },
4987
4988   /* PREFIX_VEX_0F72_REG_2 */
4989   {
4990     { Bad_Opcode },
4991     { Bad_Opcode },
4992     { "vpsrld",         { Vex, XS, Ib }, 0 },
4993   },
4994
4995   /* PREFIX_VEX_0F72_REG_4 */
4996   {
4997     { Bad_Opcode },
4998     { Bad_Opcode },
4999     { "vpsrad",         { Vex, XS, Ib }, 0 },
5000   },
5001
5002   /* PREFIX_VEX_0F72_REG_6 */
5003   {
5004     { Bad_Opcode },
5005     { Bad_Opcode },
5006     { "vpslld",         { Vex, XS, Ib }, 0 },
5007   },
5008
5009   /* PREFIX_VEX_0F73_REG_2 */
5010   {
5011     { Bad_Opcode },
5012     { Bad_Opcode },
5013     { "vpsrlq",         { Vex, XS, Ib }, 0 },
5014   },
5015
5016   /* PREFIX_VEX_0F73_REG_3 */
5017   {
5018     { Bad_Opcode },
5019     { Bad_Opcode },
5020     { "vpsrldq",        { Vex, XS, Ib }, 0 },
5021   },
5022
5023   /* PREFIX_VEX_0F73_REG_6 */
5024   {
5025     { Bad_Opcode },
5026     { Bad_Opcode },
5027     { "vpsllq",         { Vex, XS, Ib }, 0 },
5028   },
5029
5030   /* PREFIX_VEX_0F73_REG_7 */
5031   {
5032     { Bad_Opcode },
5033     { Bad_Opcode },
5034     { "vpslldq",        { Vex, XS, Ib }, 0 },
5035   },
5036
5037   /* PREFIX_VEX_0F74 */
5038   {
5039     { Bad_Opcode },
5040     { Bad_Opcode },
5041     { "vpcmpeqb",       { XM, Vex, EXx }, 0 },
5042   },
5043
5044   /* PREFIX_VEX_0F75 */
5045   {
5046     { Bad_Opcode },
5047     { Bad_Opcode },
5048     { "vpcmpeqw",       { XM, Vex, EXx }, 0 },
5049   },
5050
5051   /* PREFIX_VEX_0F76 */
5052   {
5053     { Bad_Opcode },
5054     { Bad_Opcode },
5055     { "vpcmpeqd",       { XM, Vex, EXx }, 0 },
5056   },
5057
5058   /* PREFIX_VEX_0F77 */
5059   {
5060     { VEX_LEN_TABLE (VEX_LEN_0F77_P_0) },
5061   },
5062
5063   /* PREFIX_VEX_0F7C */
5064   {
5065     { Bad_Opcode },
5066     { Bad_Opcode },
5067     { "vhaddpd",        { XM, Vex, EXx }, 0 },
5068     { "vhaddps",        { XM, Vex, EXx }, 0 },
5069   },
5070
5071   /* PREFIX_VEX_0F7D */
5072   {
5073     { Bad_Opcode },
5074     { Bad_Opcode },
5075     { "vhsubpd",        { XM, Vex, EXx }, 0 },
5076     { "vhsubps",        { XM, Vex, EXx }, 0 },
5077   },
5078
5079   /* PREFIX_VEX_0F7E */
5080   {
5081     { Bad_Opcode },
5082     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5083     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5084   },
5085
5086   /* PREFIX_VEX_0F7F */
5087   {
5088     { Bad_Opcode },
5089     { "vmovdqu",        { EXxS, XM }, 0 },
5090     { "vmovdqa",        { EXxS, XM }, 0 },
5091   },
5092
5093   /* PREFIX_VEX_0F90 */
5094   {
5095     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5096     { Bad_Opcode },
5097     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5098   },
5099
5100   /* PREFIX_VEX_0F91 */
5101   {
5102     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5103     { Bad_Opcode },
5104     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5105   },
5106
5107   /* PREFIX_VEX_0F92 */
5108   {
5109     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5110     { Bad_Opcode },
5111     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5112     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5113   },
5114
5115   /* PREFIX_VEX_0F93 */
5116   {
5117     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5118     { Bad_Opcode },
5119     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5120     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5121   },
5122
5123   /* PREFIX_VEX_0F98 */
5124   {
5125     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5126     { Bad_Opcode },
5127     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5128   },
5129
5130   /* PREFIX_VEX_0F99 */
5131   {
5132     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5133     { Bad_Opcode },
5134     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5135   },
5136
5137   /* PREFIX_VEX_0FC2 */
5138   {
5139     { "vcmpps",         { XM, Vex, EXx, CMP }, 0 },
5140     { "vcmpss",         { XMScalar, VexScalar, EXxmm_md, CMP }, 0 },
5141     { "vcmppd",         { XM, Vex, EXx, CMP }, 0 },
5142     { "vcmpsd",         { XMScalar, VexScalar, EXxmm_mq, CMP }, 0 },
5143   },
5144
5145   /* PREFIX_VEX_0FC4 */
5146   {
5147     { Bad_Opcode },
5148     { Bad_Opcode },
5149     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5150   },
5151
5152   /* PREFIX_VEX_0FC5 */
5153   {
5154     { Bad_Opcode },
5155     { Bad_Opcode },
5156     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5157   },
5158
5159   /* PREFIX_VEX_0FD0 */
5160   {
5161     { Bad_Opcode },
5162     { Bad_Opcode },
5163     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
5164     { "vaddsubps",      { XM, Vex, EXx }, 0 },
5165   },
5166
5167   /* PREFIX_VEX_0FD1 */
5168   {
5169     { Bad_Opcode },
5170     { Bad_Opcode },
5171     { "vpsrlw",         { XM, Vex, EXxmm }, 0 },
5172   },
5173
5174   /* PREFIX_VEX_0FD2 */
5175   {
5176     { Bad_Opcode },
5177     { Bad_Opcode },
5178     { "vpsrld",         { XM, Vex, EXxmm }, 0 },
5179   },
5180
5181   /* PREFIX_VEX_0FD3 */
5182   {
5183     { Bad_Opcode },
5184     { Bad_Opcode },
5185     { "vpsrlq",         { XM, Vex, EXxmm }, 0 },
5186   },
5187
5188   /* PREFIX_VEX_0FD4 */
5189   {
5190     { Bad_Opcode },
5191     { Bad_Opcode },
5192     { "vpaddq",         { XM, Vex, EXx }, 0 },
5193   },
5194
5195   /* PREFIX_VEX_0FD5 */
5196   {
5197     { Bad_Opcode },
5198     { Bad_Opcode },
5199     { "vpmullw",        { XM, Vex, EXx }, 0 },
5200   },
5201
5202   /* PREFIX_VEX_0FD6 */
5203   {
5204     { Bad_Opcode },
5205     { Bad_Opcode },
5206     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5207   },
5208
5209   /* PREFIX_VEX_0FD7 */
5210   {
5211     { Bad_Opcode },
5212     { Bad_Opcode },
5213     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5214   },
5215
5216   /* PREFIX_VEX_0FD8 */
5217   {
5218     { Bad_Opcode },
5219     { Bad_Opcode },
5220     { "vpsubusb",       { XM, Vex, EXx }, 0 },
5221   },
5222
5223   /* PREFIX_VEX_0FD9 */
5224   {
5225     { Bad_Opcode },
5226     { Bad_Opcode },
5227     { "vpsubusw",       { XM, Vex, EXx }, 0 },
5228   },
5229
5230   /* PREFIX_VEX_0FDA */
5231   {
5232     { Bad_Opcode },
5233     { Bad_Opcode },
5234     { "vpminub",        { XM, Vex, EXx }, 0 },
5235   },
5236
5237   /* PREFIX_VEX_0FDB */
5238   {
5239     { Bad_Opcode },
5240     { Bad_Opcode },
5241     { "vpand",          { XM, Vex, EXx }, 0 },
5242   },
5243
5244   /* PREFIX_VEX_0FDC */
5245   {
5246     { Bad_Opcode },
5247     { Bad_Opcode },
5248     { "vpaddusb",       { XM, Vex, EXx }, 0 },
5249   },
5250
5251   /* PREFIX_VEX_0FDD */
5252   {
5253     { Bad_Opcode },
5254     { Bad_Opcode },
5255     { "vpaddusw",       { XM, Vex, EXx }, 0 },
5256   },
5257
5258   /* PREFIX_VEX_0FDE */
5259   {
5260     { Bad_Opcode },
5261     { Bad_Opcode },
5262     { "vpmaxub",        { XM, Vex, EXx }, 0 },
5263   },
5264
5265   /* PREFIX_VEX_0FDF */
5266   {
5267     { Bad_Opcode },
5268     { Bad_Opcode },
5269     { "vpandn",         { XM, Vex, EXx }, 0 },
5270   },
5271
5272   /* PREFIX_VEX_0FE0 */
5273   {
5274     { Bad_Opcode },
5275     { Bad_Opcode },
5276     { "vpavgb",         { XM, Vex, EXx }, 0 },
5277   },
5278
5279   /* PREFIX_VEX_0FE1 */
5280   {
5281     { Bad_Opcode },
5282     { Bad_Opcode },
5283     { "vpsraw",         { XM, Vex, EXxmm }, 0 },
5284   },
5285
5286   /* PREFIX_VEX_0FE2 */
5287   {
5288     { Bad_Opcode },
5289     { Bad_Opcode },
5290     { "vpsrad",         { XM, Vex, EXxmm }, 0 },
5291   },
5292
5293   /* PREFIX_VEX_0FE3 */
5294   {
5295     { Bad_Opcode },
5296     { Bad_Opcode },
5297     { "vpavgw",         { XM, Vex, EXx }, 0 },
5298   },
5299
5300   /* PREFIX_VEX_0FE4 */
5301   {
5302     { Bad_Opcode },
5303     { Bad_Opcode },
5304     { "vpmulhuw",       { XM, Vex, EXx }, 0 },
5305   },
5306
5307   /* PREFIX_VEX_0FE5 */
5308   {
5309     { Bad_Opcode },
5310     { Bad_Opcode },
5311     { "vpmulhw",        { XM, Vex, EXx }, 0 },
5312   },
5313
5314   /* PREFIX_VEX_0FE6 */
5315   {
5316     { Bad_Opcode },
5317     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
5318     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
5319     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
5320   },
5321
5322   /* PREFIX_VEX_0FE7 */
5323   {
5324     { Bad_Opcode },
5325     { Bad_Opcode },
5326     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5327   },
5328
5329   /* PREFIX_VEX_0FE8 */
5330   {
5331     { Bad_Opcode },
5332     { Bad_Opcode },
5333     { "vpsubsb",        { XM, Vex, EXx }, 0 },
5334   },
5335
5336   /* PREFIX_VEX_0FE9 */
5337   {
5338     { Bad_Opcode },
5339     { Bad_Opcode },
5340     { "vpsubsw",        { XM, Vex, EXx }, 0 },
5341   },
5342
5343   /* PREFIX_VEX_0FEA */
5344   {
5345     { Bad_Opcode },
5346     { Bad_Opcode },
5347     { "vpminsw",        { XM, Vex, EXx }, 0 },
5348   },
5349
5350   /* PREFIX_VEX_0FEB */
5351   {
5352     { Bad_Opcode },
5353     { Bad_Opcode },
5354     { "vpor",           { XM, Vex, EXx }, 0 },
5355   },
5356
5357   /* PREFIX_VEX_0FEC */
5358   {
5359     { Bad_Opcode },
5360     { Bad_Opcode },
5361     { "vpaddsb",        { XM, Vex, EXx }, 0 },
5362   },
5363
5364   /* PREFIX_VEX_0FED */
5365   {
5366     { Bad_Opcode },
5367     { Bad_Opcode },
5368     { "vpaddsw",        { XM, Vex, EXx }, 0 },
5369   },
5370
5371   /* PREFIX_VEX_0FEE */
5372   {
5373     { Bad_Opcode },
5374     { Bad_Opcode },
5375     { "vpmaxsw",        { XM, Vex, EXx }, 0 },
5376   },
5377
5378   /* PREFIX_VEX_0FEF */
5379   {
5380     { Bad_Opcode },
5381     { Bad_Opcode },
5382     { "vpxor",          { XM, Vex, EXx }, 0 },
5383   },
5384
5385   /* PREFIX_VEX_0FF0 */
5386   {
5387     { Bad_Opcode },
5388     { Bad_Opcode },
5389     { Bad_Opcode },
5390     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5391   },
5392
5393   /* PREFIX_VEX_0FF1 */
5394   {
5395     { Bad_Opcode },
5396     { Bad_Opcode },
5397     { "vpsllw",         { XM, Vex, EXxmm }, 0 },
5398   },
5399
5400   /* PREFIX_VEX_0FF2 */
5401   {
5402     { Bad_Opcode },
5403     { Bad_Opcode },
5404     { "vpslld",         { XM, Vex, EXxmm }, 0 },
5405   },
5406
5407   /* PREFIX_VEX_0FF3 */
5408   {
5409     { Bad_Opcode },
5410     { Bad_Opcode },
5411     { "vpsllq",         { XM, Vex, EXxmm }, 0 },
5412   },
5413
5414   /* PREFIX_VEX_0FF4 */
5415   {
5416     { Bad_Opcode },
5417     { Bad_Opcode },
5418     { "vpmuludq",       { XM, Vex, EXx }, 0 },
5419   },
5420
5421   /* PREFIX_VEX_0FF5 */
5422   {
5423     { Bad_Opcode },
5424     { Bad_Opcode },
5425     { "vpmaddwd",       { XM, Vex, EXx }, 0 },
5426   },
5427
5428   /* PREFIX_VEX_0FF6 */
5429   {
5430     { Bad_Opcode },
5431     { Bad_Opcode },
5432     { "vpsadbw",        { XM, Vex, EXx }, 0 },
5433   },
5434
5435   /* PREFIX_VEX_0FF7 */
5436   {
5437     { Bad_Opcode },
5438     { Bad_Opcode },
5439     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5440   },
5441
5442   /* PREFIX_VEX_0FF8 */
5443   {
5444     { Bad_Opcode },
5445     { Bad_Opcode },
5446     { "vpsubb",         { XM, Vex, EXx }, 0 },
5447   },
5448
5449   /* PREFIX_VEX_0FF9 */
5450   {
5451     { Bad_Opcode },
5452     { Bad_Opcode },
5453     { "vpsubw",         { XM, Vex, EXx }, 0 },
5454   },
5455
5456   /* PREFIX_VEX_0FFA */
5457   {
5458     { Bad_Opcode },
5459     { Bad_Opcode },
5460     { "vpsubd",         { XM, Vex, EXx }, 0 },
5461   },
5462
5463   /* PREFIX_VEX_0FFB */
5464   {
5465     { Bad_Opcode },
5466     { Bad_Opcode },
5467     { "vpsubq",         { XM, Vex, EXx }, 0 },
5468   },
5469
5470   /* PREFIX_VEX_0FFC */
5471   {
5472     { Bad_Opcode },
5473     { Bad_Opcode },
5474     { "vpaddb",         { XM, Vex, EXx }, 0 },
5475   },
5476
5477   /* PREFIX_VEX_0FFD */
5478   {
5479     { Bad_Opcode },
5480     { Bad_Opcode },
5481     { "vpaddw",         { XM, Vex, EXx }, 0 },
5482   },
5483
5484   /* PREFIX_VEX_0FFE */
5485   {
5486     { Bad_Opcode },
5487     { Bad_Opcode },
5488     { "vpaddd",         { XM, Vex, EXx }, 0 },
5489   },
5490
5491   /* PREFIX_VEX_0F3800 */
5492   {
5493     { Bad_Opcode },
5494     { Bad_Opcode },
5495     { "vpshufb",        { XM, Vex, EXx }, 0 },
5496   },
5497
5498   /* PREFIX_VEX_0F3801 */
5499   {
5500     { Bad_Opcode },
5501     { Bad_Opcode },
5502     { "vphaddw",        { XM, Vex, EXx }, 0 },
5503   },
5504
5505   /* PREFIX_VEX_0F3802 */
5506   {
5507     { Bad_Opcode },
5508     { Bad_Opcode },
5509     { "vphaddd",        { XM, Vex, EXx }, 0 },
5510   },
5511
5512   /* PREFIX_VEX_0F3803 */
5513   {
5514     { Bad_Opcode },
5515     { Bad_Opcode },
5516     { "vphaddsw",       { XM, Vex, EXx }, 0 },
5517   },
5518
5519   /* PREFIX_VEX_0F3804 */
5520   {
5521     { Bad_Opcode },
5522     { Bad_Opcode },
5523     { "vpmaddubsw",     { XM, Vex, EXx }, 0 },
5524   },
5525
5526   /* PREFIX_VEX_0F3805 */
5527   {
5528     { Bad_Opcode },
5529     { Bad_Opcode },
5530     { "vphsubw",        { XM, Vex, EXx }, 0 },
5531   },
5532
5533   /* PREFIX_VEX_0F3806 */
5534   {
5535     { Bad_Opcode },
5536     { Bad_Opcode },
5537     { "vphsubd",        { XM, Vex, EXx }, 0 },
5538   },
5539
5540   /* PREFIX_VEX_0F3807 */
5541   {
5542     { Bad_Opcode },
5543     { Bad_Opcode },
5544     { "vphsubsw",       { XM, Vex, EXx }, 0 },
5545   },
5546
5547   /* PREFIX_VEX_0F3808 */
5548   {
5549     { Bad_Opcode },
5550     { Bad_Opcode },
5551     { "vpsignb",        { XM, Vex, EXx }, 0 },
5552   },
5553
5554   /* PREFIX_VEX_0F3809 */
5555   {
5556     { Bad_Opcode },
5557     { Bad_Opcode },
5558     { "vpsignw",        { XM, Vex, EXx }, 0 },
5559   },
5560
5561   /* PREFIX_VEX_0F380A */
5562   {
5563     { Bad_Opcode },
5564     { Bad_Opcode },
5565     { "vpsignd",        { XM, Vex, EXx }, 0 },
5566   },
5567
5568   /* PREFIX_VEX_0F380B */
5569   {
5570     { Bad_Opcode },
5571     { Bad_Opcode },
5572     { "vpmulhrsw",      { XM, Vex, EXx }, 0 },
5573   },
5574
5575   /* PREFIX_VEX_0F380C */
5576   {
5577     { Bad_Opcode },
5578     { Bad_Opcode },
5579     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5580   },
5581
5582   /* PREFIX_VEX_0F380D */
5583   {
5584     { Bad_Opcode },
5585     { Bad_Opcode },
5586     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5587   },
5588
5589   /* PREFIX_VEX_0F380E */
5590   {
5591     { Bad_Opcode },
5592     { Bad_Opcode },
5593     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5594   },
5595
5596   /* PREFIX_VEX_0F380F */
5597   {
5598     { Bad_Opcode },
5599     { Bad_Opcode },
5600     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5601   },
5602
5603   /* PREFIX_VEX_0F3813 */
5604   {
5605     { Bad_Opcode },
5606     { Bad_Opcode },
5607     { VEX_W_TABLE (VEX_W_0F3813_P_2) },
5608   },
5609
5610   /* PREFIX_VEX_0F3816 */
5611   {
5612     { Bad_Opcode },
5613     { Bad_Opcode },
5614     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5615   },
5616
5617   /* PREFIX_VEX_0F3817 */
5618   {
5619     { Bad_Opcode },
5620     { Bad_Opcode },
5621     { "vptest",         { XM, EXx }, 0 },
5622   },
5623
5624   /* PREFIX_VEX_0F3818 */
5625   {
5626     { Bad_Opcode },
5627     { Bad_Opcode },
5628     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5629   },
5630
5631   /* PREFIX_VEX_0F3819 */
5632   {
5633     { Bad_Opcode },
5634     { Bad_Opcode },
5635     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5636   },
5637
5638   /* PREFIX_VEX_0F381A */
5639   {
5640     { Bad_Opcode },
5641     { Bad_Opcode },
5642     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5643   },
5644
5645   /* PREFIX_VEX_0F381C */
5646   {
5647     { Bad_Opcode },
5648     { Bad_Opcode },
5649     { "vpabsb",         { XM, EXx }, 0 },
5650   },
5651
5652   /* PREFIX_VEX_0F381D */
5653   {
5654     { Bad_Opcode },
5655     { Bad_Opcode },
5656     { "vpabsw",         { XM, EXx }, 0 },
5657   },
5658
5659   /* PREFIX_VEX_0F381E */
5660   {
5661     { Bad_Opcode },
5662     { Bad_Opcode },
5663     { "vpabsd",         { XM, EXx }, 0 },
5664   },
5665
5666   /* PREFIX_VEX_0F3820 */
5667   {
5668     { Bad_Opcode },
5669     { Bad_Opcode },
5670     { "vpmovsxbw",      { XM, EXxmmq }, 0 },
5671   },
5672
5673   /* PREFIX_VEX_0F3821 */
5674   {
5675     { Bad_Opcode },
5676     { Bad_Opcode },
5677     { "vpmovsxbd",      { XM, EXxmmqd }, 0 },
5678   },
5679
5680   /* PREFIX_VEX_0F3822 */
5681   {
5682     { Bad_Opcode },
5683     { Bad_Opcode },
5684     { "vpmovsxbq",      { XM, EXxmmdw }, 0 },
5685   },
5686
5687   /* PREFIX_VEX_0F3823 */
5688   {
5689     { Bad_Opcode },
5690     { Bad_Opcode },
5691     { "vpmovsxwd",      { XM, EXxmmq }, 0 },
5692   },
5693
5694   /* PREFIX_VEX_0F3824 */
5695   {
5696     { Bad_Opcode },
5697     { Bad_Opcode },
5698     { "vpmovsxwq",      { XM, EXxmmqd }, 0 },
5699   },
5700
5701   /* PREFIX_VEX_0F3825 */
5702   {
5703     { Bad_Opcode },
5704     { Bad_Opcode },
5705     { "vpmovsxdq",      { XM, EXxmmq }, 0 },
5706   },
5707
5708   /* PREFIX_VEX_0F3828 */
5709   {
5710     { Bad_Opcode },
5711     { Bad_Opcode },
5712     { "vpmuldq",        { XM, Vex, EXx }, 0 },
5713   },
5714
5715   /* PREFIX_VEX_0F3829 */
5716   {
5717     { Bad_Opcode },
5718     { Bad_Opcode },
5719     { "vpcmpeqq",       { XM, Vex, EXx }, 0 },
5720   },
5721
5722   /* PREFIX_VEX_0F382A */
5723   {
5724     { Bad_Opcode },
5725     { Bad_Opcode },
5726     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5727   },
5728
5729   /* PREFIX_VEX_0F382B */
5730   {
5731     { Bad_Opcode },
5732     { Bad_Opcode },
5733     { "vpackusdw",      { XM, Vex, EXx }, 0 },
5734   },
5735
5736   /* PREFIX_VEX_0F382C */
5737   {
5738     { Bad_Opcode },
5739     { Bad_Opcode },
5740      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5741   },
5742
5743   /* PREFIX_VEX_0F382D */
5744   {
5745     { Bad_Opcode },
5746     { Bad_Opcode },
5747      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5748   },
5749
5750   /* PREFIX_VEX_0F382E */
5751   {
5752     { Bad_Opcode },
5753     { Bad_Opcode },
5754      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5755   },
5756
5757   /* PREFIX_VEX_0F382F */
5758   {
5759     { Bad_Opcode },
5760     { Bad_Opcode },
5761      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5762   },
5763
5764   /* PREFIX_VEX_0F3830 */
5765   {
5766     { Bad_Opcode },
5767     { Bad_Opcode },
5768     { "vpmovzxbw",      { XM, EXxmmq }, 0 },
5769   },
5770
5771   /* PREFIX_VEX_0F3831 */
5772   {
5773     { Bad_Opcode },
5774     { Bad_Opcode },
5775     { "vpmovzxbd",      { XM, EXxmmqd }, 0 },
5776   },
5777
5778   /* PREFIX_VEX_0F3832 */
5779   {
5780     { Bad_Opcode },
5781     { Bad_Opcode },
5782     { "vpmovzxbq",      { XM, EXxmmdw }, 0 },
5783   },
5784
5785   /* PREFIX_VEX_0F3833 */
5786   {
5787     { Bad_Opcode },
5788     { Bad_Opcode },
5789     { "vpmovzxwd",      { XM, EXxmmq }, 0 },
5790   },
5791
5792   /* PREFIX_VEX_0F3834 */
5793   {
5794     { Bad_Opcode },
5795     { Bad_Opcode },
5796     { "vpmovzxwq",      { XM, EXxmmqd }, 0 },
5797   },
5798
5799   /* PREFIX_VEX_0F3835 */
5800   {
5801     { Bad_Opcode },
5802     { Bad_Opcode },
5803     { "vpmovzxdq",      { XM, EXxmmq }, 0 },
5804   },
5805
5806   /* PREFIX_VEX_0F3836 */
5807   {
5808     { Bad_Opcode },
5809     { Bad_Opcode },
5810     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5811   },
5812
5813   /* PREFIX_VEX_0F3837 */
5814   {
5815     { Bad_Opcode },
5816     { Bad_Opcode },
5817     { "vpcmpgtq",       { XM, Vex, EXx }, 0 },
5818   },
5819
5820   /* PREFIX_VEX_0F3838 */
5821   {
5822     { Bad_Opcode },
5823     { Bad_Opcode },
5824     { "vpminsb",        { XM, Vex, EXx }, 0 },
5825   },
5826
5827   /* PREFIX_VEX_0F3839 */
5828   {
5829     { Bad_Opcode },
5830     { Bad_Opcode },
5831     { "vpminsd",        { XM, Vex, EXx }, 0 },
5832   },
5833
5834   /* PREFIX_VEX_0F383A */
5835   {
5836     { Bad_Opcode },
5837     { Bad_Opcode },
5838     { "vpminuw",        { XM, Vex, EXx }, 0 },
5839   },
5840
5841   /* PREFIX_VEX_0F383B */
5842   {
5843     { Bad_Opcode },
5844     { Bad_Opcode },
5845     { "vpminud",        { XM, Vex, EXx }, 0 },
5846   },
5847
5848   /* PREFIX_VEX_0F383C */
5849   {
5850     { Bad_Opcode },
5851     { Bad_Opcode },
5852     { "vpmaxsb",        { XM, Vex, EXx }, 0 },
5853   },
5854
5855   /* PREFIX_VEX_0F383D */
5856   {
5857     { Bad_Opcode },
5858     { Bad_Opcode },
5859     { "vpmaxsd",        { XM, Vex, EXx }, 0 },
5860   },
5861
5862   /* PREFIX_VEX_0F383E */
5863   {
5864     { Bad_Opcode },
5865     { Bad_Opcode },
5866     { "vpmaxuw",        { XM, Vex, EXx }, 0 },
5867   },
5868
5869   /* PREFIX_VEX_0F383F */
5870   {
5871     { Bad_Opcode },
5872     { Bad_Opcode },
5873     { "vpmaxud",        { XM, Vex, EXx }, 0 },
5874   },
5875
5876   /* PREFIX_VEX_0F3840 */
5877   {
5878     { Bad_Opcode },
5879     { Bad_Opcode },
5880     { "vpmulld",        { XM, Vex, EXx }, 0 },
5881   },
5882
5883   /* PREFIX_VEX_0F3841 */
5884   {
5885     { Bad_Opcode },
5886     { Bad_Opcode },
5887     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5888   },
5889
5890   /* PREFIX_VEX_0F3845 */
5891   {
5892     { Bad_Opcode },
5893     { Bad_Opcode },
5894     { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
5895   },
5896
5897   /* PREFIX_VEX_0F3846 */
5898   {
5899     { Bad_Opcode },
5900     { Bad_Opcode },
5901     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5902   },
5903
5904   /* PREFIX_VEX_0F3847 */
5905   {
5906     { Bad_Opcode },
5907     { Bad_Opcode },
5908     { "vpsllv%LW", { XM, Vex, EXx }, 0 },
5909   },
5910
5911   /* PREFIX_VEX_0F3849_X86_64 */
5912   {
5913     { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_0) },
5914     { Bad_Opcode },
5915     { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_2) },
5916     { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_3) },
5917   },
5918
5919   /* PREFIX_VEX_0F384B_X86_64 */
5920   {
5921     { Bad_Opcode },
5922     { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_1) },
5923     { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_2) },
5924     { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_3) },
5925   },
5926
5927   /* PREFIX_VEX_0F3858 */
5928   {
5929     { Bad_Opcode },
5930     { Bad_Opcode },
5931     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5932   },
5933
5934   /* PREFIX_VEX_0F3859 */
5935   {
5936     { Bad_Opcode },
5937     { Bad_Opcode },
5938     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5939   },
5940
5941   /* PREFIX_VEX_0F385A */
5942   {
5943     { Bad_Opcode },
5944     { Bad_Opcode },
5945     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5946   },
5947
5948   /* PREFIX_VEX_0F385C_X86_64 */
5949   {
5950     { Bad_Opcode },
5951     { VEX_W_TABLE (VEX_W_0F385C_X86_64_P_1) },
5952     { Bad_Opcode },
5953   },
5954
5955   /* PREFIX_VEX_0F385E_X86_64 */
5956   {
5957     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_0) },
5958     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_1) },
5959     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_2) },
5960     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_3) },
5961   },
5962
5963   /* PREFIX_VEX_0F3878 */
5964   {
5965     { Bad_Opcode },
5966     { Bad_Opcode },
5967     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5968   },
5969
5970   /* PREFIX_VEX_0F3879 */
5971   {
5972     { Bad_Opcode },
5973     { Bad_Opcode },
5974     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5975   },
5976
5977   /* PREFIX_VEX_0F388C */
5978   {
5979     { Bad_Opcode },
5980     { Bad_Opcode },
5981     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5982   },
5983
5984   /* PREFIX_VEX_0F388E */
5985   {
5986     { Bad_Opcode },
5987     { Bad_Opcode },
5988     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5989   },
5990
5991   /* PREFIX_VEX_0F3890 */
5992   {
5993     { Bad_Opcode },
5994     { Bad_Opcode },
5995     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
5996   },
5997
5998   /* PREFIX_VEX_0F3891 */
5999   {
6000     { Bad_Opcode },
6001     { Bad_Opcode },
6002     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6003   },
6004
6005   /* PREFIX_VEX_0F3892 */
6006   {
6007     { Bad_Opcode },
6008     { Bad_Opcode },
6009     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
6010   },
6011
6012   /* PREFIX_VEX_0F3893 */
6013   {
6014     { Bad_Opcode },
6015     { Bad_Opcode },
6016     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6017   },
6018
6019   /* PREFIX_VEX_0F3896 */
6020   {
6021     { Bad_Opcode },
6022     { Bad_Opcode },
6023     { "vfmaddsub132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6024   },
6025
6026   /* PREFIX_VEX_0F3897 */
6027   {
6028     { Bad_Opcode },
6029     { Bad_Opcode },
6030     { "vfmsubadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6031   },
6032
6033   /* PREFIX_VEX_0F3898 */
6034   {
6035     { Bad_Opcode },
6036     { Bad_Opcode },
6037     { "vfmadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6038   },
6039
6040   /* PREFIX_VEX_0F3899 */
6041   {
6042     { Bad_Opcode },
6043     { Bad_Opcode },
6044     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6045   },
6046
6047   /* PREFIX_VEX_0F389A */
6048   {
6049     { Bad_Opcode },
6050     { Bad_Opcode },
6051     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
6052   },
6053
6054   /* PREFIX_VEX_0F389B */
6055   {
6056     { Bad_Opcode },
6057     { Bad_Opcode },
6058     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6059   },
6060
6061   /* PREFIX_VEX_0F389C */
6062   {
6063     { Bad_Opcode },
6064     { Bad_Opcode },
6065     { "vfnmadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6066   },
6067
6068   /* PREFIX_VEX_0F389D */
6069   {
6070     { Bad_Opcode },
6071     { Bad_Opcode },
6072     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6073   },
6074
6075   /* PREFIX_VEX_0F389E */
6076   {
6077     { Bad_Opcode },
6078     { Bad_Opcode },
6079     { "vfnmsub132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6080   },
6081
6082   /* PREFIX_VEX_0F389F */
6083   {
6084     { Bad_Opcode },
6085     { Bad_Opcode },
6086     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6087   },
6088
6089   /* PREFIX_VEX_0F38A6 */
6090   {
6091     { Bad_Opcode },
6092     { Bad_Opcode },
6093     { "vfmaddsub213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6094     { Bad_Opcode },
6095   },
6096
6097   /* PREFIX_VEX_0F38A7 */
6098   {
6099     { Bad_Opcode },
6100     { Bad_Opcode },
6101     { "vfmsubadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6102   },
6103
6104   /* PREFIX_VEX_0F38A8 */
6105   {
6106     { Bad_Opcode },
6107     { Bad_Opcode },
6108     { "vfmadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6109   },
6110
6111   /* PREFIX_VEX_0F38A9 */
6112   {
6113     { Bad_Opcode },
6114     { Bad_Opcode },
6115     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6116   },
6117
6118   /* PREFIX_VEX_0F38AA */
6119   {
6120     { Bad_Opcode },
6121     { Bad_Opcode },
6122     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6123   },
6124
6125   /* PREFIX_VEX_0F38AB */
6126   {
6127     { Bad_Opcode },
6128     { Bad_Opcode },
6129     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6130   },
6131
6132   /* PREFIX_VEX_0F38AC */
6133   {
6134     { Bad_Opcode },
6135     { Bad_Opcode },
6136     { "vfnmadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6137   },
6138
6139   /* PREFIX_VEX_0F38AD */
6140   {
6141     { Bad_Opcode },
6142     { Bad_Opcode },
6143     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6144   },
6145
6146   /* PREFIX_VEX_0F38AE */
6147   {
6148     { Bad_Opcode },
6149     { Bad_Opcode },
6150     { "vfnmsub213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6151   },
6152
6153   /* PREFIX_VEX_0F38AF */
6154   {
6155     { Bad_Opcode },
6156     { Bad_Opcode },
6157     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6158   },
6159
6160   /* PREFIX_VEX_0F38B6 */
6161   {
6162     { Bad_Opcode },
6163     { Bad_Opcode },
6164     { "vfmaddsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6165   },
6166
6167   /* PREFIX_VEX_0F38B7 */
6168   {
6169     { Bad_Opcode },
6170     { Bad_Opcode },
6171     { "vfmsubadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6172   },
6173
6174   /* PREFIX_VEX_0F38B8 */
6175   {
6176     { Bad_Opcode },
6177     { Bad_Opcode },
6178     { "vfmadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6179   },
6180
6181   /* PREFIX_VEX_0F38B9 */
6182   {
6183     { Bad_Opcode },
6184     { Bad_Opcode },
6185     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6186   },
6187
6188   /* PREFIX_VEX_0F38BA */
6189   {
6190     { Bad_Opcode },
6191     { Bad_Opcode },
6192     { "vfmsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6193   },
6194
6195   /* PREFIX_VEX_0F38BB */
6196   {
6197     { Bad_Opcode },
6198     { Bad_Opcode },
6199     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6200   },
6201
6202   /* PREFIX_VEX_0F38BC */
6203   {
6204     { Bad_Opcode },
6205     { Bad_Opcode },
6206     { "vfnmadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6207   },
6208
6209   /* PREFIX_VEX_0F38BD */
6210   {
6211     { Bad_Opcode },
6212     { Bad_Opcode },
6213     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6214   },
6215
6216   /* PREFIX_VEX_0F38BE */
6217   {
6218     { Bad_Opcode },
6219     { Bad_Opcode },
6220     { "vfnmsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6221   },
6222
6223   /* PREFIX_VEX_0F38BF */
6224   {
6225     { Bad_Opcode },
6226     { Bad_Opcode },
6227     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6228   },
6229
6230   /* PREFIX_VEX_0F38CF */
6231   {
6232     { Bad_Opcode },
6233     { Bad_Opcode },
6234     { VEX_W_TABLE (VEX_W_0F38CF_P_2) },
6235   },
6236
6237   /* PREFIX_VEX_0F38DB */
6238   {
6239     { Bad_Opcode },
6240     { Bad_Opcode },
6241     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6242   },
6243
6244   /* PREFIX_VEX_0F38DC */
6245   {
6246     { Bad_Opcode },
6247     { Bad_Opcode },
6248     { "vaesenc",        { XM, Vex, EXx }, 0 },
6249   },
6250
6251   /* PREFIX_VEX_0F38DD */
6252   {
6253     { Bad_Opcode },
6254     { Bad_Opcode },
6255     { "vaesenclast",    { XM, Vex, EXx }, 0 },
6256   },
6257
6258   /* PREFIX_VEX_0F38DE */
6259   {
6260     { Bad_Opcode },
6261     { Bad_Opcode },
6262     { "vaesdec",        { XM, Vex, EXx }, 0 },
6263   },
6264
6265   /* PREFIX_VEX_0F38DF */
6266   {
6267     { Bad_Opcode },
6268     { Bad_Opcode },
6269     { "vaesdeclast",    { XM, Vex, EXx }, 0 },
6270   },
6271
6272   /* PREFIX_VEX_0F38F2 */
6273   {
6274     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6275   },
6276
6277   /* PREFIX_VEX_0F38F3_REG_1 */
6278   {
6279     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6280   },
6281
6282   /* PREFIX_VEX_0F38F3_REG_2 */
6283   {
6284     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6285   },
6286
6287   /* PREFIX_VEX_0F38F3_REG_3 */
6288   {
6289     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6290   },
6291
6292   /* PREFIX_VEX_0F38F5 */
6293   {
6294     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6295     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6296     { Bad_Opcode },
6297     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6298   },
6299
6300   /* PREFIX_VEX_0F38F6 */
6301   {
6302     { Bad_Opcode },
6303     { Bad_Opcode },
6304     { Bad_Opcode },
6305     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6306   },
6307
6308   /* PREFIX_VEX_0F38F7 */
6309   {
6310     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6311     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6312     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6313     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6314   },
6315
6316   /* PREFIX_VEX_0F3A00 */
6317   {
6318     { Bad_Opcode },
6319     { Bad_Opcode },
6320     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6321   },
6322
6323   /* PREFIX_VEX_0F3A01 */
6324   {
6325     { Bad_Opcode },
6326     { Bad_Opcode },
6327     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6328   },
6329
6330   /* PREFIX_VEX_0F3A02 */
6331   {
6332     { Bad_Opcode },
6333     { Bad_Opcode },
6334     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6335   },
6336
6337   /* PREFIX_VEX_0F3A04 */
6338   {
6339     { Bad_Opcode },
6340     { Bad_Opcode },
6341     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6342   },
6343
6344   /* PREFIX_VEX_0F3A05 */
6345   {
6346     { Bad_Opcode },
6347     { Bad_Opcode },
6348     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6349   },
6350
6351   /* PREFIX_VEX_0F3A06 */
6352   {
6353     { Bad_Opcode },
6354     { Bad_Opcode },
6355     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6356   },
6357
6358   /* PREFIX_VEX_0F3A08 */
6359   {
6360     { Bad_Opcode },
6361     { Bad_Opcode },
6362     { "vroundps",       { XM, EXx, Ib }, 0 },
6363   },
6364
6365   /* PREFIX_VEX_0F3A09 */
6366   {
6367     { Bad_Opcode },
6368     { Bad_Opcode },
6369     { "vroundpd",       { XM, EXx, Ib }, 0 },
6370   },
6371
6372   /* PREFIX_VEX_0F3A0A */
6373   {
6374     { Bad_Opcode },
6375     { Bad_Opcode },
6376     { "vroundss",       { XMScalar, VexScalar, EXxmm_md, Ib }, 0 },
6377   },
6378
6379   /* PREFIX_VEX_0F3A0B */
6380   {
6381     { Bad_Opcode },
6382     { Bad_Opcode },
6383     { "vroundsd",       { XMScalar, VexScalar, EXxmm_mq, Ib }, 0 },
6384   },
6385
6386   /* PREFIX_VEX_0F3A0C */
6387   {
6388     { Bad_Opcode },
6389     { Bad_Opcode },
6390     { "vblendps",       { XM, Vex, EXx, Ib }, 0 },
6391   },
6392
6393   /* PREFIX_VEX_0F3A0D */
6394   {
6395     { Bad_Opcode },
6396     { Bad_Opcode },
6397     { "vblendpd",       { XM, Vex, EXx, Ib }, 0 },
6398   },
6399
6400   /* PREFIX_VEX_0F3A0E */
6401   {
6402     { Bad_Opcode },
6403     { Bad_Opcode },
6404     { "vpblendw",       { XM, Vex, EXx, Ib }, 0 },
6405   },
6406
6407   /* PREFIX_VEX_0F3A0F */
6408   {
6409     { Bad_Opcode },
6410     { Bad_Opcode },
6411     { "vpalignr",       { XM, Vex, EXx, Ib }, 0 },
6412   },
6413
6414   /* PREFIX_VEX_0F3A14 */
6415   {
6416     { Bad_Opcode },
6417     { Bad_Opcode },
6418     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6419   },
6420
6421   /* PREFIX_VEX_0F3A15 */
6422   {
6423     { Bad_Opcode },
6424     { Bad_Opcode },
6425     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6426   },
6427
6428   /* PREFIX_VEX_0F3A16 */
6429   {
6430     { Bad_Opcode },
6431     { Bad_Opcode },
6432     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6433   },
6434
6435   /* PREFIX_VEX_0F3A17 */
6436   {
6437     { Bad_Opcode },
6438     { Bad_Opcode },
6439     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6440   },
6441
6442   /* PREFIX_VEX_0F3A18 */
6443   {
6444     { Bad_Opcode },
6445     { Bad_Opcode },
6446     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6447   },
6448
6449   /* PREFIX_VEX_0F3A19 */
6450   {
6451     { Bad_Opcode },
6452     { Bad_Opcode },
6453     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6454   },
6455
6456   /* PREFIX_VEX_0F3A1D */
6457   {
6458     { Bad_Opcode },
6459     { Bad_Opcode },
6460     { VEX_W_TABLE (VEX_W_0F3A1D_P_2) },
6461   },
6462
6463   /* PREFIX_VEX_0F3A20 */
6464   {
6465     { Bad_Opcode },
6466     { Bad_Opcode },
6467     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6468   },
6469
6470   /* PREFIX_VEX_0F3A21 */
6471   {
6472     { Bad_Opcode },
6473     { Bad_Opcode },
6474     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6475   },
6476
6477   /* PREFIX_VEX_0F3A22 */
6478   {
6479     { Bad_Opcode },
6480     { Bad_Opcode },
6481     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6482   },
6483
6484   /* PREFIX_VEX_0F3A30 */
6485   {
6486     { Bad_Opcode },
6487     { Bad_Opcode },
6488     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6489   },
6490
6491   /* PREFIX_VEX_0F3A31 */
6492   {
6493     { Bad_Opcode },
6494     { Bad_Opcode },
6495     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6496   },
6497
6498   /* PREFIX_VEX_0F3A32 */
6499   {
6500     { Bad_Opcode },
6501     { Bad_Opcode },
6502     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6503   },
6504
6505   /* PREFIX_VEX_0F3A33 */
6506   {
6507     { Bad_Opcode },
6508     { Bad_Opcode },
6509     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6510   },
6511
6512   /* PREFIX_VEX_0F3A38 */
6513   {
6514     { Bad_Opcode },
6515     { Bad_Opcode },
6516     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6517   },
6518
6519   /* PREFIX_VEX_0F3A39 */
6520   {
6521     { Bad_Opcode },
6522     { Bad_Opcode },
6523     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6524   },
6525
6526   /* PREFIX_VEX_0F3A40 */
6527   {
6528     { Bad_Opcode },
6529     { Bad_Opcode },
6530     { "vdpps",          { XM, Vex, EXx, Ib }, 0 },
6531   },
6532
6533   /* PREFIX_VEX_0F3A41 */
6534   {
6535     { Bad_Opcode },
6536     { Bad_Opcode },
6537     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6538   },
6539
6540   /* PREFIX_VEX_0F3A42 */
6541   {
6542     { Bad_Opcode },
6543     { Bad_Opcode },
6544     { "vmpsadbw",       { XM, Vex, EXx, Ib }, 0 },
6545   },
6546
6547   /* PREFIX_VEX_0F3A44 */
6548   {
6549     { Bad_Opcode },
6550     { Bad_Opcode },
6551     { "vpclmulqdq",     { XM, Vex, EXx, PCLMUL }, 0 },
6552   },
6553
6554   /* PREFIX_VEX_0F3A46 */
6555   {
6556     { Bad_Opcode },
6557     { Bad_Opcode },
6558     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6559   },
6560
6561   /* PREFIX_VEX_0F3A48 */
6562   {
6563     { Bad_Opcode },
6564     { Bad_Opcode },
6565     { "vpermil2ps",     { XM, Vex, EXx, XMVexI4, VexI4 }, 0 },
6566   },
6567
6568   /* PREFIX_VEX_0F3A49 */
6569   {
6570     { Bad_Opcode },
6571     { Bad_Opcode },
6572     { "vpermil2pd",     { XM, Vex, EXx, XMVexI4, VexI4 }, 0 },
6573   },
6574
6575   /* PREFIX_VEX_0F3A4A */
6576   {
6577     { Bad_Opcode },
6578     { Bad_Opcode },
6579     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6580   },
6581
6582   /* PREFIX_VEX_0F3A4B */
6583   {
6584     { Bad_Opcode },
6585     { Bad_Opcode },
6586     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6587   },
6588
6589   /* PREFIX_VEX_0F3A4C */
6590   {
6591     { Bad_Opcode },
6592     { Bad_Opcode },
6593     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6594   },
6595
6596   /* PREFIX_VEX_0F3A5C */
6597   {
6598     { Bad_Opcode },
6599     { Bad_Opcode },
6600     { "vfmaddsubps", { XM, Vex, EXx, XMVexI4 }, 0 },
6601   },
6602
6603   /* PREFIX_VEX_0F3A5D */
6604   {
6605     { Bad_Opcode },
6606     { Bad_Opcode },
6607     { "vfmaddsubpd", { XM, Vex, EXx, XMVexI4 }, 0 },
6608   },
6609
6610   /* PREFIX_VEX_0F3A5E */
6611   {
6612     { Bad_Opcode },
6613     { Bad_Opcode },
6614     { "vfmsubaddps", { XM, Vex, EXx, XMVexI4 }, 0 },
6615   },
6616
6617   /* PREFIX_VEX_0F3A5F */
6618   {
6619     { Bad_Opcode },
6620     { Bad_Opcode },
6621     { "vfmsubaddpd", { XM, Vex, EXx, XMVexI4 }, 0 },
6622   },
6623
6624   /* PREFIX_VEX_0F3A60 */
6625   {
6626     { Bad_Opcode },
6627     { Bad_Opcode },
6628     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6629     { Bad_Opcode },
6630   },
6631
6632   /* PREFIX_VEX_0F3A61 */
6633   {
6634     { Bad_Opcode },
6635     { Bad_Opcode },
6636     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6637   },
6638
6639   /* PREFIX_VEX_0F3A62 */
6640   {
6641     { Bad_Opcode },
6642     { Bad_Opcode },
6643     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6644   },
6645
6646   /* PREFIX_VEX_0F3A63 */
6647   {
6648     { Bad_Opcode },
6649     { Bad_Opcode },
6650     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6651   },
6652
6653   /* PREFIX_VEX_0F3A68 */
6654   {
6655     { Bad_Opcode },
6656     { Bad_Opcode },
6657     { "vfmaddps", { XM, Vex, EXx, XMVexI4 }, 0 },
6658   },
6659
6660   /* PREFIX_VEX_0F3A69 */
6661   {
6662     { Bad_Opcode },
6663     { Bad_Opcode },
6664     { "vfmaddpd", { XM, Vex, EXx, XMVexI4 }, 0 },
6665   },
6666
6667   /* PREFIX_VEX_0F3A6A */
6668   {
6669     { Bad_Opcode },
6670     { Bad_Opcode },
6671     { "vfmaddss",       { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, 0 },
6672   },
6673
6674   /* PREFIX_VEX_0F3A6B */
6675   {
6676     { Bad_Opcode },
6677     { Bad_Opcode },
6678     { "vfmaddsd",       { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, 0 },
6679   },
6680
6681   /* PREFIX_VEX_0F3A6C */
6682   {
6683     { Bad_Opcode },
6684     { Bad_Opcode },
6685     { "vfmsubps", { XM, Vex, EXx, XMVexI4 }, 0 },
6686   },
6687
6688   /* PREFIX_VEX_0F3A6D */
6689   {
6690     { Bad_Opcode },
6691     { Bad_Opcode },
6692     { "vfmsubpd", { XM, Vex, EXx, XMVexI4 }, 0 },
6693   },
6694
6695   /* PREFIX_VEX_0F3A6E */
6696   {
6697     { Bad_Opcode },
6698     { Bad_Opcode },
6699     { "vfmsubss",       { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, 0 },
6700   },
6701
6702   /* PREFIX_VEX_0F3A6F */
6703   {
6704     { Bad_Opcode },
6705     { Bad_Opcode },
6706     { "vfmsubsd",       { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, 0 },
6707   },
6708
6709   /* PREFIX_VEX_0F3A78 */
6710   {
6711     { Bad_Opcode },
6712     { Bad_Opcode },
6713     { "vfnmaddps", { XM, Vex, EXx, XMVexI4 }, 0 },
6714   },
6715
6716   /* PREFIX_VEX_0F3A79 */
6717   {
6718     { Bad_Opcode },
6719     { Bad_Opcode },
6720     { "vfnmaddpd", { XM, Vex, EXx, XMVexI4 }, 0 },
6721   },
6722
6723   /* PREFIX_VEX_0F3A7A */
6724   {
6725     { Bad_Opcode },
6726     { Bad_Opcode },
6727     { "vfnmaddss",      { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, 0 },
6728   },
6729
6730   /* PREFIX_VEX_0F3A7B */
6731   {
6732     { Bad_Opcode },
6733     { Bad_Opcode },
6734     { "vfnmaddsd",      { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, 0 },
6735   },
6736
6737   /* PREFIX_VEX_0F3A7C */
6738   {
6739     { Bad_Opcode },
6740     { Bad_Opcode },
6741     { "vfnmsubps", { XM, Vex, EXx, XMVexI4 }, 0 },
6742     { Bad_Opcode },
6743   },
6744
6745   /* PREFIX_VEX_0F3A7D */
6746   {
6747     { Bad_Opcode },
6748     { Bad_Opcode },
6749     { "vfnmsubpd", { XM, Vex, EXx, XMVexI4 }, 0 },
6750   },
6751
6752   /* PREFIX_VEX_0F3A7E */
6753   {
6754     { Bad_Opcode },
6755     { Bad_Opcode },
6756     { "vfnmsubss",      { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, 0 },
6757   },
6758
6759   /* PREFIX_VEX_0F3A7F */
6760   {
6761     { Bad_Opcode },
6762     { Bad_Opcode },
6763     { "vfnmsubsd",      { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, 0 },
6764   },
6765
6766   /* PREFIX_VEX_0F3ACE */
6767   {
6768     { Bad_Opcode },
6769     { Bad_Opcode },
6770     { VEX_W_TABLE (VEX_W_0F3ACE_P_2) },
6771   },
6772
6773   /* PREFIX_VEX_0F3ACF */
6774   {
6775     { Bad_Opcode },
6776     { Bad_Opcode },
6777     { VEX_W_TABLE (VEX_W_0F3ACF_P_2) },
6778   },
6779
6780   /* PREFIX_VEX_0F3ADF */
6781   {
6782     { Bad_Opcode },
6783     { Bad_Opcode },
6784     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6785   },
6786
6787   /* PREFIX_VEX_0F3AF0 */
6788   {
6789     { Bad_Opcode },
6790     { Bad_Opcode },
6791     { Bad_Opcode },
6792     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6793   },
6794
6795 #include "i386-dis-evex-prefix.h"
6796 };
6797
6798 static const struct dis386 x86_64_table[][2] = {
6799   /* X86_64_06 */
6800   {
6801     { "pushP", { es }, 0 },
6802   },
6803
6804   /* X86_64_07 */
6805   {
6806     { "popP", { es }, 0 },
6807   },
6808
6809   /* X86_64_0E */
6810   {
6811     { "pushP", { cs }, 0 },
6812   },
6813
6814   /* X86_64_16 */
6815   {
6816     { "pushP", { ss }, 0 },
6817   },
6818
6819   /* X86_64_17 */
6820   {
6821     { "popP", { ss }, 0 },
6822   },
6823
6824   /* X86_64_1E */
6825   {
6826     { "pushP", { ds }, 0 },
6827   },
6828
6829   /* X86_64_1F */
6830   {
6831     { "popP", { ds }, 0 },
6832   },
6833
6834   /* X86_64_27 */
6835   {
6836     { "daa", { XX }, 0 },
6837   },
6838
6839   /* X86_64_2F */
6840   {
6841     { "das", { XX }, 0 },
6842   },
6843
6844   /* X86_64_37 */
6845   {
6846     { "aaa", { XX }, 0 },
6847   },
6848
6849   /* X86_64_3F */
6850   {
6851     { "aas", { XX }, 0 },
6852   },
6853
6854   /* X86_64_60 */
6855   {
6856     { "pushaP", { XX }, 0 },
6857   },
6858
6859   /* X86_64_61 */
6860   {
6861     { "popaP", { XX }, 0 },
6862   },
6863
6864   /* X86_64_62 */
6865   {
6866     { MOD_TABLE (MOD_62_32BIT) },
6867     { EVEX_TABLE (EVEX_0F) },
6868   },
6869
6870   /* X86_64_63 */
6871   {
6872     { "arpl", { Ew, Gw }, 0 },
6873     { "movs", { { OP_G, movsxd_mode }, { MOVSXD_Fixup, movsxd_mode } }, 0 },
6874   },
6875
6876   /* X86_64_6D */
6877   {
6878     { "ins{R|}", { Yzr, indirDX }, 0 },
6879     { "ins{G|}", { Yzr, indirDX }, 0 },
6880   },
6881
6882   /* X86_64_6F */
6883   {
6884     { "outs{R|}", { indirDXr, Xz }, 0 },
6885     { "outs{G|}", { indirDXr, Xz }, 0 },
6886   },
6887
6888   /* X86_64_82 */
6889   {
6890     /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
6891     { REG_TABLE (REG_80) },
6892   },
6893
6894   /* X86_64_9A */
6895   {
6896     { "{l|}call{T|}", { Ap }, 0 },
6897   },
6898
6899   /* X86_64_C2 */
6900   {
6901     { "retP",           { Iw, BND }, 0 },
6902     { "ret@",           { Iw, BND }, 0 },
6903   },
6904
6905   /* X86_64_C3 */
6906   {
6907     { "retP",           { BND }, 0 },
6908     { "ret@",           { BND }, 0 },
6909   },
6910
6911   /* X86_64_C4 */
6912   {
6913     { MOD_TABLE (MOD_C4_32BIT) },
6914     { VEX_C4_TABLE (VEX_0F) },
6915   },
6916
6917   /* X86_64_C5 */
6918   {
6919     { MOD_TABLE (MOD_C5_32BIT) },
6920     { VEX_C5_TABLE (VEX_0F) },
6921   },
6922
6923   /* X86_64_CE */
6924   {
6925     { "into", { XX }, 0 },
6926   },
6927
6928   /* X86_64_D4 */
6929   {
6930     { "aam", { Ib }, 0 },
6931   },
6932
6933   /* X86_64_D5 */
6934   {
6935     { "aad", { Ib }, 0 },
6936   },
6937
6938   /* X86_64_E8 */
6939   {
6940     { "callP",          { Jv, BND }, 0 },
6941     { "call@",          { Jv, BND }, 0 }
6942   },
6943
6944   /* X86_64_E9 */
6945   {
6946     { "jmpP",           { Jv, BND }, 0 },
6947     { "jmp@",           { Jv, BND }, 0 }
6948   },
6949
6950   /* X86_64_EA */
6951   {
6952     { "{l|}jmp{T|}", { Ap }, 0 },
6953   },
6954
6955   /* X86_64_0F01_REG_0 */
6956   {
6957     { "sgdt{Q|Q}", { M }, 0 },
6958     { "sgdt", { M }, 0 },
6959   },
6960
6961   /* X86_64_0F01_REG_1 */
6962   {
6963     { "sidt{Q|Q}", { M }, 0 },
6964     { "sidt", { M }, 0 },
6965   },
6966
6967   /* X86_64_0F01_REG_2 */
6968   {
6969     { "lgdt{Q|Q}", { M }, 0 },
6970     { "lgdt", { M }, 0 },
6971   },
6972
6973   /* X86_64_0F01_REG_3 */
6974   {
6975     { "lidt{Q|Q}", { M }, 0 },
6976     { "lidt", { M }, 0 },
6977   },
6978
6979   /* X86_64_VEX_0F3849 */
6980   {
6981     { Bad_Opcode },
6982     { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64) },
6983   },
6984
6985   /* X86_64_VEX_0F384B */
6986   {
6987     { Bad_Opcode },
6988     { PREFIX_TABLE (PREFIX_VEX_0F384B_X86_64) },
6989   },
6990
6991   /* X86_64_VEX_0F385C */
6992   {
6993     { Bad_Opcode },
6994     { PREFIX_TABLE (PREFIX_VEX_0F385C_X86_64) },
6995   },
6996
6997   /* X86_64_VEX_0F385E */
6998   {
6999     { Bad_Opcode },
7000     { PREFIX_TABLE (PREFIX_VEX_0F385E_X86_64) },
7001   },
7002 };
7003
7004 static const struct dis386 three_byte_table[][256] = {
7005
7006   /* THREE_BYTE_0F38 */
7007   {
7008     /* 00 */
7009     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
7010     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
7011     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
7012     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
7013     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
7014     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
7015     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
7016     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
7017     /* 08 */
7018     { "psignb",         { MX, EM }, PREFIX_OPCODE },
7019     { "psignw",         { MX, EM }, PREFIX_OPCODE },
7020     { "psignd",         { MX, EM }, PREFIX_OPCODE },
7021     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
7022     { Bad_Opcode },
7023     { Bad_Opcode },
7024     { Bad_Opcode },
7025     { Bad_Opcode },
7026     /* 10 */
7027     { PREFIX_TABLE (PREFIX_0F3810) },
7028     { Bad_Opcode },
7029     { Bad_Opcode },
7030     { Bad_Opcode },
7031     { PREFIX_TABLE (PREFIX_0F3814) },
7032     { PREFIX_TABLE (PREFIX_0F3815) },
7033     { Bad_Opcode },
7034     { PREFIX_TABLE (PREFIX_0F3817) },
7035     /* 18 */
7036     { Bad_Opcode },
7037     { Bad_Opcode },
7038     { Bad_Opcode },
7039     { Bad_Opcode },
7040     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
7041     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
7042     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
7043     { Bad_Opcode },
7044     /* 20 */
7045     { PREFIX_TABLE (PREFIX_0F3820) },
7046     { PREFIX_TABLE (PREFIX_0F3821) },
7047     { PREFIX_TABLE (PREFIX_0F3822) },
7048     { PREFIX_TABLE (PREFIX_0F3823) },
7049     { PREFIX_TABLE (PREFIX_0F3824) },
7050     { PREFIX_TABLE (PREFIX_0F3825) },
7051     { Bad_Opcode },
7052     { Bad_Opcode },
7053     /* 28 */
7054     { PREFIX_TABLE (PREFIX_0F3828) },
7055     { PREFIX_TABLE (PREFIX_0F3829) },
7056     { PREFIX_TABLE (PREFIX_0F382A) },
7057     { PREFIX_TABLE (PREFIX_0F382B) },
7058     { Bad_Opcode },
7059     { Bad_Opcode },
7060     { Bad_Opcode },
7061     { Bad_Opcode },
7062     /* 30 */
7063     { PREFIX_TABLE (PREFIX_0F3830) },
7064     { PREFIX_TABLE (PREFIX_0F3831) },
7065     { PREFIX_TABLE (PREFIX_0F3832) },
7066     { PREFIX_TABLE (PREFIX_0F3833) },
7067     { PREFIX_TABLE (PREFIX_0F3834) },
7068     { PREFIX_TABLE (PREFIX_0F3835) },
7069     { Bad_Opcode },
7070     { PREFIX_TABLE (PREFIX_0F3837) },
7071     /* 38 */
7072     { PREFIX_TABLE (PREFIX_0F3838) },
7073     { PREFIX_TABLE (PREFIX_0F3839) },
7074     { PREFIX_TABLE (PREFIX_0F383A) },
7075     { PREFIX_TABLE (PREFIX_0F383B) },
7076     { PREFIX_TABLE (PREFIX_0F383C) },
7077     { PREFIX_TABLE (PREFIX_0F383D) },
7078     { PREFIX_TABLE (PREFIX_0F383E) },
7079     { PREFIX_TABLE (PREFIX_0F383F) },
7080     /* 40 */
7081     { PREFIX_TABLE (PREFIX_0F3840) },
7082     { PREFIX_TABLE (PREFIX_0F3841) },
7083     { Bad_Opcode },
7084     { Bad_Opcode },
7085     { Bad_Opcode },
7086     { Bad_Opcode },
7087     { Bad_Opcode },
7088     { Bad_Opcode },
7089     /* 48 */
7090     { Bad_Opcode },
7091     { Bad_Opcode },
7092     { Bad_Opcode },
7093     { Bad_Opcode },
7094     { Bad_Opcode },
7095     { Bad_Opcode },
7096     { Bad_Opcode },
7097     { Bad_Opcode },
7098     /* 50 */
7099     { Bad_Opcode },
7100     { Bad_Opcode },
7101     { Bad_Opcode },
7102     { Bad_Opcode },
7103     { Bad_Opcode },
7104     { Bad_Opcode },
7105     { Bad_Opcode },
7106     { Bad_Opcode },
7107     /* 58 */
7108     { Bad_Opcode },
7109     { Bad_Opcode },
7110     { Bad_Opcode },
7111     { Bad_Opcode },
7112     { Bad_Opcode },
7113     { Bad_Opcode },
7114     { Bad_Opcode },
7115     { Bad_Opcode },
7116     /* 60 */
7117     { Bad_Opcode },
7118     { Bad_Opcode },
7119     { Bad_Opcode },
7120     { Bad_Opcode },
7121     { Bad_Opcode },
7122     { Bad_Opcode },
7123     { Bad_Opcode },
7124     { Bad_Opcode },
7125     /* 68 */
7126     { Bad_Opcode },
7127     { Bad_Opcode },
7128     { Bad_Opcode },
7129     { Bad_Opcode },
7130     { Bad_Opcode },
7131     { Bad_Opcode },
7132     { Bad_Opcode },
7133     { Bad_Opcode },
7134     /* 70 */
7135     { Bad_Opcode },
7136     { Bad_Opcode },
7137     { Bad_Opcode },
7138     { Bad_Opcode },
7139     { Bad_Opcode },
7140     { Bad_Opcode },
7141     { Bad_Opcode },
7142     { Bad_Opcode },
7143     /* 78 */
7144     { Bad_Opcode },
7145     { Bad_Opcode },
7146     { Bad_Opcode },
7147     { Bad_Opcode },
7148     { Bad_Opcode },
7149     { Bad_Opcode },
7150     { Bad_Opcode },
7151     { Bad_Opcode },
7152     /* 80 */
7153     { PREFIX_TABLE (PREFIX_0F3880) },
7154     { PREFIX_TABLE (PREFIX_0F3881) },
7155     { PREFIX_TABLE (PREFIX_0F3882) },
7156     { Bad_Opcode },
7157     { Bad_Opcode },
7158     { Bad_Opcode },
7159     { Bad_Opcode },
7160     { Bad_Opcode },
7161     /* 88 */
7162     { Bad_Opcode },
7163     { Bad_Opcode },
7164     { Bad_Opcode },
7165     { Bad_Opcode },
7166     { Bad_Opcode },
7167     { Bad_Opcode },
7168     { Bad_Opcode },
7169     { Bad_Opcode },
7170     /* 90 */
7171     { Bad_Opcode },
7172     { Bad_Opcode },
7173     { Bad_Opcode },
7174     { Bad_Opcode },
7175     { Bad_Opcode },
7176     { Bad_Opcode },
7177     { Bad_Opcode },
7178     { Bad_Opcode },
7179     /* 98 */
7180     { Bad_Opcode },
7181     { Bad_Opcode },
7182     { Bad_Opcode },
7183     { Bad_Opcode },
7184     { Bad_Opcode },
7185     { Bad_Opcode },
7186     { Bad_Opcode },
7187     { Bad_Opcode },
7188     /* a0 */
7189     { Bad_Opcode },
7190     { Bad_Opcode },
7191     { Bad_Opcode },
7192     { Bad_Opcode },
7193     { Bad_Opcode },
7194     { Bad_Opcode },
7195     { Bad_Opcode },
7196     { Bad_Opcode },
7197     /* a8 */
7198     { Bad_Opcode },
7199     { Bad_Opcode },
7200     { Bad_Opcode },
7201     { Bad_Opcode },
7202     { Bad_Opcode },
7203     { Bad_Opcode },
7204     { Bad_Opcode },
7205     { Bad_Opcode },
7206     /* b0 */
7207     { Bad_Opcode },
7208     { Bad_Opcode },
7209     { Bad_Opcode },
7210     { Bad_Opcode },
7211     { Bad_Opcode },
7212     { Bad_Opcode },
7213     { Bad_Opcode },
7214     { Bad_Opcode },
7215     /* b8 */
7216     { Bad_Opcode },
7217     { Bad_Opcode },
7218     { Bad_Opcode },
7219     { Bad_Opcode },
7220     { Bad_Opcode },
7221     { Bad_Opcode },
7222     { Bad_Opcode },
7223     { Bad_Opcode },
7224     /* c0 */
7225     { Bad_Opcode },
7226     { Bad_Opcode },
7227     { Bad_Opcode },
7228     { Bad_Opcode },
7229     { Bad_Opcode },
7230     { Bad_Opcode },
7231     { Bad_Opcode },
7232     { Bad_Opcode },
7233     /* c8 */
7234     { PREFIX_TABLE (PREFIX_0F38C8) },
7235     { PREFIX_TABLE (PREFIX_0F38C9) },
7236     { PREFIX_TABLE (PREFIX_0F38CA) },
7237     { PREFIX_TABLE (PREFIX_0F38CB) },
7238     { PREFIX_TABLE (PREFIX_0F38CC) },
7239     { PREFIX_TABLE (PREFIX_0F38CD) },
7240     { Bad_Opcode },
7241     { PREFIX_TABLE (PREFIX_0F38CF) },
7242     /* d0 */
7243     { Bad_Opcode },
7244     { Bad_Opcode },
7245     { Bad_Opcode },
7246     { Bad_Opcode },
7247     { Bad_Opcode },
7248     { Bad_Opcode },
7249     { Bad_Opcode },
7250     { Bad_Opcode },
7251     /* d8 */
7252     { Bad_Opcode },
7253     { Bad_Opcode },
7254     { Bad_Opcode },
7255     { PREFIX_TABLE (PREFIX_0F38DB) },
7256     { PREFIX_TABLE (PREFIX_0F38DC) },
7257     { PREFIX_TABLE (PREFIX_0F38DD) },
7258     { PREFIX_TABLE (PREFIX_0F38DE) },
7259     { PREFIX_TABLE (PREFIX_0F38DF) },
7260     /* e0 */
7261     { Bad_Opcode },
7262     { Bad_Opcode },
7263     { Bad_Opcode },
7264     { Bad_Opcode },
7265     { Bad_Opcode },
7266     { Bad_Opcode },
7267     { Bad_Opcode },
7268     { Bad_Opcode },
7269     /* e8 */
7270     { Bad_Opcode },
7271     { Bad_Opcode },
7272     { Bad_Opcode },
7273     { Bad_Opcode },
7274     { Bad_Opcode },
7275     { Bad_Opcode },
7276     { Bad_Opcode },
7277     { Bad_Opcode },
7278     /* f0 */
7279     { PREFIX_TABLE (PREFIX_0F38F0) },
7280     { PREFIX_TABLE (PREFIX_0F38F1) },
7281     { Bad_Opcode },
7282     { Bad_Opcode },
7283     { Bad_Opcode },
7284     { PREFIX_TABLE (PREFIX_0F38F5) },
7285     { PREFIX_TABLE (PREFIX_0F38F6) },
7286     { Bad_Opcode },
7287     /* f8 */
7288     { PREFIX_TABLE (PREFIX_0F38F8) },
7289     { PREFIX_TABLE (PREFIX_0F38F9) },
7290     { Bad_Opcode },
7291     { Bad_Opcode },
7292     { Bad_Opcode },
7293     { Bad_Opcode },
7294     { Bad_Opcode },
7295     { Bad_Opcode },
7296   },
7297   /* THREE_BYTE_0F3A */
7298   {
7299     /* 00 */
7300     { Bad_Opcode },
7301     { Bad_Opcode },
7302     { Bad_Opcode },
7303     { Bad_Opcode },
7304     { Bad_Opcode },
7305     { Bad_Opcode },
7306     { Bad_Opcode },
7307     { Bad_Opcode },
7308     /* 08 */
7309     { PREFIX_TABLE (PREFIX_0F3A08) },
7310     { PREFIX_TABLE (PREFIX_0F3A09) },
7311     { PREFIX_TABLE (PREFIX_0F3A0A) },
7312     { PREFIX_TABLE (PREFIX_0F3A0B) },
7313     { PREFIX_TABLE (PREFIX_0F3A0C) },
7314     { PREFIX_TABLE (PREFIX_0F3A0D) },
7315     { PREFIX_TABLE (PREFIX_0F3A0E) },
7316     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
7317     /* 10 */
7318     { Bad_Opcode },
7319     { Bad_Opcode },
7320     { Bad_Opcode },
7321     { Bad_Opcode },
7322     { PREFIX_TABLE (PREFIX_0F3A14) },
7323     { PREFIX_TABLE (PREFIX_0F3A15) },
7324     { PREFIX_TABLE (PREFIX_0F3A16) },
7325     { PREFIX_TABLE (PREFIX_0F3A17) },
7326     /* 18 */
7327     { Bad_Opcode },
7328     { Bad_Opcode },
7329     { Bad_Opcode },
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     { Bad_Opcode },
7334     { Bad_Opcode },
7335     /* 20 */
7336     { PREFIX_TABLE (PREFIX_0F3A20) },
7337     { PREFIX_TABLE (PREFIX_0F3A21) },
7338     { PREFIX_TABLE (PREFIX_0F3A22) },
7339     { Bad_Opcode },
7340     { Bad_Opcode },
7341     { Bad_Opcode },
7342     { Bad_Opcode },
7343     { Bad_Opcode },
7344     /* 28 */
7345     { Bad_Opcode },
7346     { Bad_Opcode },
7347     { Bad_Opcode },
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     { Bad_Opcode },
7352     { Bad_Opcode },
7353     /* 30 */
7354     { Bad_Opcode },
7355     { Bad_Opcode },
7356     { Bad_Opcode },
7357     { Bad_Opcode },
7358     { Bad_Opcode },
7359     { Bad_Opcode },
7360     { Bad_Opcode },
7361     { Bad_Opcode },
7362     /* 38 */
7363     { Bad_Opcode },
7364     { Bad_Opcode },
7365     { Bad_Opcode },
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     { Bad_Opcode },
7370     { Bad_Opcode },
7371     /* 40 */
7372     { PREFIX_TABLE (PREFIX_0F3A40) },
7373     { PREFIX_TABLE (PREFIX_0F3A41) },
7374     { PREFIX_TABLE (PREFIX_0F3A42) },
7375     { Bad_Opcode },
7376     { PREFIX_TABLE (PREFIX_0F3A44) },
7377     { Bad_Opcode },
7378     { Bad_Opcode },
7379     { Bad_Opcode },
7380     /* 48 */
7381     { Bad_Opcode },
7382     { Bad_Opcode },
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     { Bad_Opcode },
7389     /* 50 */
7390     { Bad_Opcode },
7391     { Bad_Opcode },
7392     { Bad_Opcode },
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     { Bad_Opcode },
7396     { Bad_Opcode },
7397     { Bad_Opcode },
7398     /* 58 */
7399     { Bad_Opcode },
7400     { Bad_Opcode },
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     { Bad_Opcode },
7407     /* 60 */
7408     { PREFIX_TABLE (PREFIX_0F3A60) },
7409     { PREFIX_TABLE (PREFIX_0F3A61) },
7410     { PREFIX_TABLE (PREFIX_0F3A62) },
7411     { PREFIX_TABLE (PREFIX_0F3A63) },
7412     { Bad_Opcode },
7413     { Bad_Opcode },
7414     { Bad_Opcode },
7415     { Bad_Opcode },
7416     /* 68 */
7417     { Bad_Opcode },
7418     { Bad_Opcode },
7419     { Bad_Opcode },
7420     { Bad_Opcode },
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423     { Bad_Opcode },
7424     { Bad_Opcode },
7425     /* 70 */
7426     { Bad_Opcode },
7427     { Bad_Opcode },
7428     { Bad_Opcode },
7429     { Bad_Opcode },
7430     { Bad_Opcode },
7431     { Bad_Opcode },
7432     { Bad_Opcode },
7433     { Bad_Opcode },
7434     /* 78 */
7435     { Bad_Opcode },
7436     { Bad_Opcode },
7437     { Bad_Opcode },
7438     { Bad_Opcode },
7439     { Bad_Opcode },
7440     { Bad_Opcode },
7441     { Bad_Opcode },
7442     { Bad_Opcode },
7443     /* 80 */
7444     { Bad_Opcode },
7445     { Bad_Opcode },
7446     { Bad_Opcode },
7447     { Bad_Opcode },
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     { Bad_Opcode },
7452     /* 88 */
7453     { Bad_Opcode },
7454     { Bad_Opcode },
7455     { Bad_Opcode },
7456     { Bad_Opcode },
7457     { Bad_Opcode },
7458     { Bad_Opcode },
7459     { Bad_Opcode },
7460     { Bad_Opcode },
7461     /* 90 */
7462     { Bad_Opcode },
7463     { Bad_Opcode },
7464     { Bad_Opcode },
7465     { Bad_Opcode },
7466     { Bad_Opcode },
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469     { Bad_Opcode },
7470     /* 98 */
7471     { Bad_Opcode },
7472     { Bad_Opcode },
7473     { Bad_Opcode },
7474     { Bad_Opcode },
7475     { Bad_Opcode },
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     { Bad_Opcode },
7479     /* a0 */
7480     { Bad_Opcode },
7481     { Bad_Opcode },
7482     { Bad_Opcode },
7483     { Bad_Opcode },
7484     { Bad_Opcode },
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     { Bad_Opcode },
7488     /* a8 */
7489     { Bad_Opcode },
7490     { Bad_Opcode },
7491     { Bad_Opcode },
7492     { Bad_Opcode },
7493     { Bad_Opcode },
7494     { Bad_Opcode },
7495     { Bad_Opcode },
7496     { Bad_Opcode },
7497     /* b0 */
7498     { Bad_Opcode },
7499     { Bad_Opcode },
7500     { Bad_Opcode },
7501     { Bad_Opcode },
7502     { Bad_Opcode },
7503     { Bad_Opcode },
7504     { Bad_Opcode },
7505     { Bad_Opcode },
7506     /* b8 */
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     { Bad_Opcode },
7510     { Bad_Opcode },
7511     { Bad_Opcode },
7512     { Bad_Opcode },
7513     { Bad_Opcode },
7514     { Bad_Opcode },
7515     /* c0 */
7516     { Bad_Opcode },
7517     { Bad_Opcode },
7518     { Bad_Opcode },
7519     { Bad_Opcode },
7520     { Bad_Opcode },
7521     { Bad_Opcode },
7522     { Bad_Opcode },
7523     { Bad_Opcode },
7524     /* c8 */
7525     { Bad_Opcode },
7526     { Bad_Opcode },
7527     { Bad_Opcode },
7528     { Bad_Opcode },
7529     { PREFIX_TABLE (PREFIX_0F3ACC) },
7530     { Bad_Opcode },
7531     { PREFIX_TABLE (PREFIX_0F3ACE) },
7532     { PREFIX_TABLE (PREFIX_0F3ACF) },
7533     /* d0 */
7534     { Bad_Opcode },
7535     { Bad_Opcode },
7536     { Bad_Opcode },
7537     { Bad_Opcode },
7538     { Bad_Opcode },
7539     { Bad_Opcode },
7540     { Bad_Opcode },
7541     { Bad_Opcode },
7542     /* d8 */
7543     { Bad_Opcode },
7544     { Bad_Opcode },
7545     { Bad_Opcode },
7546     { Bad_Opcode },
7547     { Bad_Opcode },
7548     { Bad_Opcode },
7549     { Bad_Opcode },
7550     { PREFIX_TABLE (PREFIX_0F3ADF) },
7551     /* e0 */
7552     { Bad_Opcode },
7553     { Bad_Opcode },
7554     { Bad_Opcode },
7555     { Bad_Opcode },
7556     { Bad_Opcode },
7557     { Bad_Opcode },
7558     { Bad_Opcode },
7559     { Bad_Opcode },
7560     /* e8 */
7561     { Bad_Opcode },
7562     { Bad_Opcode },
7563     { Bad_Opcode },
7564     { Bad_Opcode },
7565     { Bad_Opcode },
7566     { Bad_Opcode },
7567     { Bad_Opcode },
7568     { Bad_Opcode },
7569     /* f0 */
7570     { Bad_Opcode },
7571     { Bad_Opcode },
7572     { Bad_Opcode },
7573     { Bad_Opcode },
7574     { Bad_Opcode },
7575     { Bad_Opcode },
7576     { Bad_Opcode },
7577     { Bad_Opcode },
7578     /* f8 */
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     { Bad_Opcode },
7582     { Bad_Opcode },
7583     { Bad_Opcode },
7584     { Bad_Opcode },
7585     { Bad_Opcode },
7586     { Bad_Opcode },
7587   },
7588 };
7589
7590 static const struct dis386 xop_table[][256] = {
7591   /* XOP_08 */
7592   {
7593     /* 00 */
7594     { Bad_Opcode },
7595     { Bad_Opcode },
7596     { Bad_Opcode },
7597     { Bad_Opcode },
7598     { Bad_Opcode },
7599     { Bad_Opcode },
7600     { Bad_Opcode },
7601     { Bad_Opcode },
7602     /* 08 */
7603     { Bad_Opcode },
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     { Bad_Opcode },
7608     { Bad_Opcode },
7609     { Bad_Opcode },
7610     { Bad_Opcode },
7611     /* 10 */
7612     { Bad_Opcode },
7613     { Bad_Opcode },
7614     { Bad_Opcode },
7615     { Bad_Opcode },
7616     { Bad_Opcode },
7617     { Bad_Opcode },
7618     { Bad_Opcode },
7619     { Bad_Opcode },
7620     /* 18 */
7621     { Bad_Opcode },
7622     { Bad_Opcode },
7623     { Bad_Opcode },
7624     { Bad_Opcode },
7625     { Bad_Opcode },
7626     { Bad_Opcode },
7627     { Bad_Opcode },
7628     { Bad_Opcode },
7629     /* 20 */
7630     { Bad_Opcode },
7631     { Bad_Opcode },
7632     { Bad_Opcode },
7633     { Bad_Opcode },
7634     { Bad_Opcode },
7635     { Bad_Opcode },
7636     { Bad_Opcode },
7637     { Bad_Opcode },
7638     /* 28 */
7639     { Bad_Opcode },
7640     { Bad_Opcode },
7641     { Bad_Opcode },
7642     { Bad_Opcode },
7643     { Bad_Opcode },
7644     { Bad_Opcode },
7645     { Bad_Opcode },
7646     { Bad_Opcode },
7647     /* 30 */
7648     { Bad_Opcode },
7649     { Bad_Opcode },
7650     { Bad_Opcode },
7651     { Bad_Opcode },
7652     { Bad_Opcode },
7653     { Bad_Opcode },
7654     { Bad_Opcode },
7655     { Bad_Opcode },
7656     /* 38 */
7657     { Bad_Opcode },
7658     { Bad_Opcode },
7659     { Bad_Opcode },
7660     { Bad_Opcode },
7661     { Bad_Opcode },
7662     { Bad_Opcode },
7663     { Bad_Opcode },
7664     { Bad_Opcode },
7665     /* 40 */
7666     { Bad_Opcode },
7667     { Bad_Opcode },
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     { Bad_Opcode },
7671     { Bad_Opcode },
7672     { Bad_Opcode },
7673     { Bad_Opcode },
7674     /* 48 */
7675     { Bad_Opcode },
7676     { Bad_Opcode },
7677     { Bad_Opcode },
7678     { Bad_Opcode },
7679     { Bad_Opcode },
7680     { Bad_Opcode },
7681     { Bad_Opcode },
7682     { Bad_Opcode },
7683     /* 50 */
7684     { Bad_Opcode },
7685     { Bad_Opcode },
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     { Bad_Opcode },
7691     { Bad_Opcode },
7692     /* 58 */
7693     { Bad_Opcode },
7694     { Bad_Opcode },
7695     { Bad_Opcode },
7696     { Bad_Opcode },
7697     { Bad_Opcode },
7698     { Bad_Opcode },
7699     { Bad_Opcode },
7700     { Bad_Opcode },
7701     /* 60 */
7702     { Bad_Opcode },
7703     { Bad_Opcode },
7704     { Bad_Opcode },
7705     { Bad_Opcode },
7706     { Bad_Opcode },
7707     { Bad_Opcode },
7708     { Bad_Opcode },
7709     { Bad_Opcode },
7710     /* 68 */
7711     { Bad_Opcode },
7712     { Bad_Opcode },
7713     { Bad_Opcode },
7714     { Bad_Opcode },
7715     { Bad_Opcode },
7716     { Bad_Opcode },
7717     { Bad_Opcode },
7718     { Bad_Opcode },
7719     /* 70 */
7720     { Bad_Opcode },
7721     { Bad_Opcode },
7722     { Bad_Opcode },
7723     { Bad_Opcode },
7724     { Bad_Opcode },
7725     { Bad_Opcode },
7726     { Bad_Opcode },
7727     { Bad_Opcode },
7728     /* 78 */
7729     { Bad_Opcode },
7730     { Bad_Opcode },
7731     { Bad_Opcode },
7732     { Bad_Opcode },
7733     { Bad_Opcode },
7734     { Bad_Opcode },
7735     { Bad_Opcode },
7736     { Bad_Opcode },
7737     /* 80 */
7738     { Bad_Opcode },
7739     { Bad_Opcode },
7740     { Bad_Opcode },
7741     { Bad_Opcode },
7742     { Bad_Opcode },
7743     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_85) },
7744     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_86) },
7745     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_87) },
7746     /* 88 */
7747     { Bad_Opcode },
7748     { Bad_Opcode },
7749     { Bad_Opcode },
7750     { Bad_Opcode },
7751     { Bad_Opcode },
7752     { Bad_Opcode },
7753     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8E) },
7754     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8F) },
7755     /* 90 */
7756     { Bad_Opcode },
7757     { Bad_Opcode },
7758     { Bad_Opcode },
7759     { Bad_Opcode },
7760     { Bad_Opcode },
7761     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_95) },
7762     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_96) },
7763     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_97) },
7764     /* 98 */
7765     { Bad_Opcode },
7766     { Bad_Opcode },
7767     { Bad_Opcode },
7768     { Bad_Opcode },
7769     { Bad_Opcode },
7770     { Bad_Opcode },
7771     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9E) },
7772     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9F) },
7773     /* a0 */
7774     { Bad_Opcode },
7775     { Bad_Opcode },
7776     { "vpcmov",         { XM, Vex, EXx, XMVexI4 }, 0 },
7777     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A3) },
7778     { Bad_Opcode },
7779     { Bad_Opcode },
7780     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A6) },
7781     { Bad_Opcode },
7782     /* a8 */
7783     { Bad_Opcode },
7784     { Bad_Opcode },
7785     { Bad_Opcode },
7786     { Bad_Opcode },
7787     { Bad_Opcode },
7788     { Bad_Opcode },
7789     { Bad_Opcode },
7790     { Bad_Opcode },
7791     /* b0 */
7792     { Bad_Opcode },
7793     { Bad_Opcode },
7794     { Bad_Opcode },
7795     { Bad_Opcode },
7796     { Bad_Opcode },
7797     { Bad_Opcode },
7798     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_B6) },
7799     { Bad_Opcode },
7800     /* b8 */
7801     { Bad_Opcode },
7802     { Bad_Opcode },
7803     { Bad_Opcode },
7804     { Bad_Opcode },
7805     { Bad_Opcode },
7806     { Bad_Opcode },
7807     { Bad_Opcode },
7808     { Bad_Opcode },
7809     /* c0 */
7810     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C0) },
7811     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C1) },
7812     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C2) },
7813     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C3) },
7814     { Bad_Opcode },
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     { Bad_Opcode },
7818     /* c8 */
7819     { Bad_Opcode },
7820     { Bad_Opcode },
7821     { Bad_Opcode },
7822     { Bad_Opcode },
7823     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7824     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7825     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7826     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7827     /* d0 */
7828     { Bad_Opcode },
7829     { Bad_Opcode },
7830     { Bad_Opcode },
7831     { Bad_Opcode },
7832     { Bad_Opcode },
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     { Bad_Opcode },
7836     /* d8 */
7837     { Bad_Opcode },
7838     { Bad_Opcode },
7839     { Bad_Opcode },
7840     { Bad_Opcode },
7841     { Bad_Opcode },
7842     { Bad_Opcode },
7843     { Bad_Opcode },
7844     { Bad_Opcode },
7845     /* e0 */
7846     { Bad_Opcode },
7847     { Bad_Opcode },
7848     { Bad_Opcode },
7849     { Bad_Opcode },
7850     { Bad_Opcode },
7851     { Bad_Opcode },
7852     { Bad_Opcode },
7853     { Bad_Opcode },
7854     /* e8 */
7855     { Bad_Opcode },
7856     { Bad_Opcode },
7857     { Bad_Opcode },
7858     { Bad_Opcode },
7859     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7860     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7861     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7862     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7863     /* f0 */
7864     { Bad_Opcode },
7865     { Bad_Opcode },
7866     { Bad_Opcode },
7867     { Bad_Opcode },
7868     { Bad_Opcode },
7869     { Bad_Opcode },
7870     { Bad_Opcode },
7871     { Bad_Opcode },
7872     /* f8 */
7873     { Bad_Opcode },
7874     { Bad_Opcode },
7875     { Bad_Opcode },
7876     { Bad_Opcode },
7877     { Bad_Opcode },
7878     { Bad_Opcode },
7879     { Bad_Opcode },
7880     { Bad_Opcode },
7881   },
7882   /* XOP_09 */
7883   {
7884     /* 00 */
7885     { Bad_Opcode },
7886     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_01) },
7887     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_02) },
7888     { Bad_Opcode },
7889     { Bad_Opcode },
7890     { Bad_Opcode },
7891     { Bad_Opcode },
7892     { Bad_Opcode },
7893     /* 08 */
7894     { Bad_Opcode },
7895     { Bad_Opcode },
7896     { Bad_Opcode },
7897     { Bad_Opcode },
7898     { Bad_Opcode },
7899     { Bad_Opcode },
7900     { Bad_Opcode },
7901     { Bad_Opcode },
7902     /* 10 */
7903     { Bad_Opcode },
7904     { Bad_Opcode },
7905     { MOD_TABLE (MOD_VEX_0FXOP_09_12) },
7906     { Bad_Opcode },
7907     { Bad_Opcode },
7908     { Bad_Opcode },
7909     { Bad_Opcode },
7910     { Bad_Opcode },
7911     /* 18 */
7912     { Bad_Opcode },
7913     { Bad_Opcode },
7914     { Bad_Opcode },
7915     { Bad_Opcode },
7916     { Bad_Opcode },
7917     { Bad_Opcode },
7918     { Bad_Opcode },
7919     { Bad_Opcode },
7920     /* 20 */
7921     { Bad_Opcode },
7922     { Bad_Opcode },
7923     { Bad_Opcode },
7924     { Bad_Opcode },
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     { Bad_Opcode },
7928     { Bad_Opcode },
7929     /* 28 */
7930     { Bad_Opcode },
7931     { Bad_Opcode },
7932     { Bad_Opcode },
7933     { Bad_Opcode },
7934     { Bad_Opcode },
7935     { Bad_Opcode },
7936     { Bad_Opcode },
7937     { Bad_Opcode },
7938     /* 30 */
7939     { Bad_Opcode },
7940     { Bad_Opcode },
7941     { Bad_Opcode },
7942     { Bad_Opcode },
7943     { Bad_Opcode },
7944     { Bad_Opcode },
7945     { Bad_Opcode },
7946     { Bad_Opcode },
7947     /* 38 */
7948     { Bad_Opcode },
7949     { Bad_Opcode },
7950     { Bad_Opcode },
7951     { Bad_Opcode },
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     { Bad_Opcode },
7955     { Bad_Opcode },
7956     /* 40 */
7957     { Bad_Opcode },
7958     { Bad_Opcode },
7959     { Bad_Opcode },
7960     { Bad_Opcode },
7961     { Bad_Opcode },
7962     { Bad_Opcode },
7963     { Bad_Opcode },
7964     { Bad_Opcode },
7965     /* 48 */
7966     { Bad_Opcode },
7967     { Bad_Opcode },
7968     { Bad_Opcode },
7969     { Bad_Opcode },
7970     { Bad_Opcode },
7971     { Bad_Opcode },
7972     { Bad_Opcode },
7973     { Bad_Opcode },
7974     /* 50 */
7975     { Bad_Opcode },
7976     { Bad_Opcode },
7977     { Bad_Opcode },
7978     { Bad_Opcode },
7979     { Bad_Opcode },
7980     { Bad_Opcode },
7981     { Bad_Opcode },
7982     { Bad_Opcode },
7983     /* 58 */
7984     { Bad_Opcode },
7985     { Bad_Opcode },
7986     { Bad_Opcode },
7987     { Bad_Opcode },
7988     { Bad_Opcode },
7989     { Bad_Opcode },
7990     { Bad_Opcode },
7991     { Bad_Opcode },
7992     /* 60 */
7993     { Bad_Opcode },
7994     { Bad_Opcode },
7995     { Bad_Opcode },
7996     { Bad_Opcode },
7997     { Bad_Opcode },
7998     { Bad_Opcode },
7999     { Bad_Opcode },
8000     { Bad_Opcode },
8001     /* 68 */
8002     { Bad_Opcode },
8003     { Bad_Opcode },
8004     { Bad_Opcode },
8005     { Bad_Opcode },
8006     { Bad_Opcode },
8007     { Bad_Opcode },
8008     { Bad_Opcode },
8009     { Bad_Opcode },
8010     /* 70 */
8011     { Bad_Opcode },
8012     { Bad_Opcode },
8013     { Bad_Opcode },
8014     { Bad_Opcode },
8015     { Bad_Opcode },
8016     { Bad_Opcode },
8017     { Bad_Opcode },
8018     { Bad_Opcode },
8019     /* 78 */
8020     { Bad_Opcode },
8021     { Bad_Opcode },
8022     { Bad_Opcode },
8023     { Bad_Opcode },
8024     { Bad_Opcode },
8025     { Bad_Opcode },
8026     { Bad_Opcode },
8027     { Bad_Opcode },
8028     /* 80 */
8029     { VEX_W_TABLE (VEX_W_0FXOP_09_80) },
8030     { VEX_W_TABLE (VEX_W_0FXOP_09_81) },
8031     { VEX_W_TABLE (VEX_W_0FXOP_09_82) },
8032     { VEX_W_TABLE (VEX_W_0FXOP_09_83) },
8033     { Bad_Opcode },
8034     { Bad_Opcode },
8035     { Bad_Opcode },
8036     { Bad_Opcode },
8037     /* 88 */
8038     { Bad_Opcode },
8039     { Bad_Opcode },
8040     { Bad_Opcode },
8041     { Bad_Opcode },
8042     { Bad_Opcode },
8043     { Bad_Opcode },
8044     { Bad_Opcode },
8045     { Bad_Opcode },
8046     /* 90 */
8047     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_90) },
8048     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_91) },
8049     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_92) },
8050     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_93) },
8051     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_94) },
8052     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_95) },
8053     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_96) },
8054     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_97) },
8055     /* 98 */
8056     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_98) },
8057     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_99) },
8058     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9A) },
8059     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9B) },
8060     { Bad_Opcode },
8061     { Bad_Opcode },
8062     { Bad_Opcode },
8063     { Bad_Opcode },
8064     /* a0 */
8065     { Bad_Opcode },
8066     { Bad_Opcode },
8067     { Bad_Opcode },
8068     { Bad_Opcode },
8069     { Bad_Opcode },
8070     { Bad_Opcode },
8071     { Bad_Opcode },
8072     { Bad_Opcode },
8073     /* a8 */
8074     { Bad_Opcode },
8075     { Bad_Opcode },
8076     { Bad_Opcode },
8077     { Bad_Opcode },
8078     { Bad_Opcode },
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     { Bad_Opcode },
8082     /* b0 */
8083     { Bad_Opcode },
8084     { Bad_Opcode },
8085     { Bad_Opcode },
8086     { Bad_Opcode },
8087     { Bad_Opcode },
8088     { Bad_Opcode },
8089     { Bad_Opcode },
8090     { Bad_Opcode },
8091     /* b8 */
8092     { Bad_Opcode },
8093     { Bad_Opcode },
8094     { Bad_Opcode },
8095     { Bad_Opcode },
8096     { Bad_Opcode },
8097     { Bad_Opcode },
8098     { Bad_Opcode },
8099     { Bad_Opcode },
8100     /* c0 */
8101     { Bad_Opcode },
8102     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C1) },
8103     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C2) },
8104     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C3) },
8105     { Bad_Opcode },
8106     { Bad_Opcode },
8107     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C6) },
8108     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C7) },
8109     /* c8 */
8110     { Bad_Opcode },
8111     { Bad_Opcode },
8112     { Bad_Opcode },
8113     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_CB) },
8114     { Bad_Opcode },
8115     { Bad_Opcode },
8116     { Bad_Opcode },
8117     { Bad_Opcode },
8118     /* d0 */
8119     { Bad_Opcode },
8120     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D1) },
8121     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D2) },
8122     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D3) },
8123     { Bad_Opcode },
8124     { Bad_Opcode },
8125     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D6) },
8126     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D7) },
8127     /* d8 */
8128     { Bad_Opcode },
8129     { Bad_Opcode },
8130     { Bad_Opcode },
8131     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_DB) },
8132     { Bad_Opcode },
8133     { Bad_Opcode },
8134     { Bad_Opcode },
8135     { Bad_Opcode },
8136     /* e0 */
8137     { Bad_Opcode },
8138     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E1) },
8139     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E2) },
8140     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E3) },
8141     { Bad_Opcode },
8142     { Bad_Opcode },
8143     { Bad_Opcode },
8144     { Bad_Opcode },
8145     /* e8 */
8146     { Bad_Opcode },
8147     { Bad_Opcode },
8148     { Bad_Opcode },
8149     { Bad_Opcode },
8150     { Bad_Opcode },
8151     { Bad_Opcode },
8152     { Bad_Opcode },
8153     { Bad_Opcode },
8154     /* f0 */
8155     { Bad_Opcode },
8156     { Bad_Opcode },
8157     { Bad_Opcode },
8158     { Bad_Opcode },
8159     { Bad_Opcode },
8160     { Bad_Opcode },
8161     { Bad_Opcode },
8162     { Bad_Opcode },
8163     /* f8 */
8164     { Bad_Opcode },
8165     { Bad_Opcode },
8166     { Bad_Opcode },
8167     { Bad_Opcode },
8168     { Bad_Opcode },
8169     { Bad_Opcode },
8170     { Bad_Opcode },
8171     { Bad_Opcode },
8172   },
8173   /* XOP_0A */
8174   {
8175     /* 00 */
8176     { Bad_Opcode },
8177     { Bad_Opcode },
8178     { Bad_Opcode },
8179     { Bad_Opcode },
8180     { Bad_Opcode },
8181     { Bad_Opcode },
8182     { Bad_Opcode },
8183     { Bad_Opcode },
8184     /* 08 */
8185     { Bad_Opcode },
8186     { Bad_Opcode },
8187     { Bad_Opcode },
8188     { Bad_Opcode },
8189     { Bad_Opcode },
8190     { Bad_Opcode },
8191     { Bad_Opcode },
8192     { Bad_Opcode },
8193     /* 10 */
8194     { "bextrS", { Gdq, Edq, Id }, 0 },
8195     { Bad_Opcode },
8196     { VEX_LEN_TABLE (VEX_LEN_0FXOP_0A_12) },
8197     { Bad_Opcode },
8198     { Bad_Opcode },
8199     { Bad_Opcode },
8200     { Bad_Opcode },
8201     { Bad_Opcode },
8202     /* 18 */
8203     { Bad_Opcode },
8204     { Bad_Opcode },
8205     { Bad_Opcode },
8206     { Bad_Opcode },
8207     { Bad_Opcode },
8208     { Bad_Opcode },
8209     { Bad_Opcode },
8210     { Bad_Opcode },
8211     /* 20 */
8212     { Bad_Opcode },
8213     { Bad_Opcode },
8214     { Bad_Opcode },
8215     { Bad_Opcode },
8216     { Bad_Opcode },
8217     { Bad_Opcode },
8218     { Bad_Opcode },
8219     { Bad_Opcode },
8220     /* 28 */
8221     { Bad_Opcode },
8222     { Bad_Opcode },
8223     { Bad_Opcode },
8224     { Bad_Opcode },
8225     { Bad_Opcode },
8226     { Bad_Opcode },
8227     { Bad_Opcode },
8228     { Bad_Opcode },
8229     /* 30 */
8230     { Bad_Opcode },
8231     { Bad_Opcode },
8232     { Bad_Opcode },
8233     { Bad_Opcode },
8234     { Bad_Opcode },
8235     { Bad_Opcode },
8236     { Bad_Opcode },
8237     { Bad_Opcode },
8238     /* 38 */
8239     { Bad_Opcode },
8240     { Bad_Opcode },
8241     { Bad_Opcode },
8242     { Bad_Opcode },
8243     { Bad_Opcode },
8244     { Bad_Opcode },
8245     { Bad_Opcode },
8246     { Bad_Opcode },
8247     /* 40 */
8248     { Bad_Opcode },
8249     { Bad_Opcode },
8250     { Bad_Opcode },
8251     { Bad_Opcode },
8252     { Bad_Opcode },
8253     { Bad_Opcode },
8254     { Bad_Opcode },
8255     { Bad_Opcode },
8256     /* 48 */
8257     { Bad_Opcode },
8258     { Bad_Opcode },
8259     { Bad_Opcode },
8260     { Bad_Opcode },
8261     { Bad_Opcode },
8262     { Bad_Opcode },
8263     { Bad_Opcode },
8264     { Bad_Opcode },
8265     /* 50 */
8266     { Bad_Opcode },
8267     { Bad_Opcode },
8268     { Bad_Opcode },
8269     { Bad_Opcode },
8270     { Bad_Opcode },
8271     { Bad_Opcode },
8272     { Bad_Opcode },
8273     { Bad_Opcode },
8274     /* 58 */
8275     { Bad_Opcode },
8276     { Bad_Opcode },
8277     { Bad_Opcode },
8278     { Bad_Opcode },
8279     { Bad_Opcode },
8280     { Bad_Opcode },
8281     { Bad_Opcode },
8282     { Bad_Opcode },
8283     /* 60 */
8284     { Bad_Opcode },
8285     { Bad_Opcode },
8286     { Bad_Opcode },
8287     { Bad_Opcode },
8288     { Bad_Opcode },
8289     { Bad_Opcode },
8290     { Bad_Opcode },
8291     { Bad_Opcode },
8292     /* 68 */
8293     { Bad_Opcode },
8294     { Bad_Opcode },
8295     { Bad_Opcode },
8296     { Bad_Opcode },
8297     { Bad_Opcode },
8298     { Bad_Opcode },
8299     { Bad_Opcode },
8300     { Bad_Opcode },
8301     /* 70 */
8302     { Bad_Opcode },
8303     { Bad_Opcode },
8304     { Bad_Opcode },
8305     { Bad_Opcode },
8306     { Bad_Opcode },
8307     { Bad_Opcode },
8308     { Bad_Opcode },
8309     { Bad_Opcode },
8310     /* 78 */
8311     { Bad_Opcode },
8312     { Bad_Opcode },
8313     { Bad_Opcode },
8314     { Bad_Opcode },
8315     { Bad_Opcode },
8316     { Bad_Opcode },
8317     { Bad_Opcode },
8318     { Bad_Opcode },
8319     /* 80 */
8320     { Bad_Opcode },
8321     { Bad_Opcode },
8322     { Bad_Opcode },
8323     { Bad_Opcode },
8324     { Bad_Opcode },
8325     { Bad_Opcode },
8326     { Bad_Opcode },
8327     { Bad_Opcode },
8328     /* 88 */
8329     { Bad_Opcode },
8330     { Bad_Opcode },
8331     { Bad_Opcode },
8332     { Bad_Opcode },
8333     { Bad_Opcode },
8334     { Bad_Opcode },
8335     { Bad_Opcode },
8336     { Bad_Opcode },
8337     /* 90 */
8338     { Bad_Opcode },
8339     { Bad_Opcode },
8340     { Bad_Opcode },
8341     { Bad_Opcode },
8342     { Bad_Opcode },
8343     { Bad_Opcode },
8344     { Bad_Opcode },
8345     { Bad_Opcode },
8346     /* 98 */
8347     { Bad_Opcode },
8348     { Bad_Opcode },
8349     { Bad_Opcode },
8350     { Bad_Opcode },
8351     { Bad_Opcode },
8352     { Bad_Opcode },
8353     { Bad_Opcode },
8354     { Bad_Opcode },
8355     /* a0 */
8356     { Bad_Opcode },
8357     { Bad_Opcode },
8358     { Bad_Opcode },
8359     { Bad_Opcode },
8360     { Bad_Opcode },
8361     { Bad_Opcode },
8362     { Bad_Opcode },
8363     { Bad_Opcode },
8364     /* a8 */
8365     { Bad_Opcode },
8366     { Bad_Opcode },
8367     { Bad_Opcode },
8368     { Bad_Opcode },
8369     { Bad_Opcode },
8370     { Bad_Opcode },
8371     { Bad_Opcode },
8372     { Bad_Opcode },
8373     /* b0 */
8374     { Bad_Opcode },
8375     { Bad_Opcode },
8376     { Bad_Opcode },
8377     { Bad_Opcode },
8378     { Bad_Opcode },
8379     { Bad_Opcode },
8380     { Bad_Opcode },
8381     { Bad_Opcode },
8382     /* b8 */
8383     { Bad_Opcode },
8384     { Bad_Opcode },
8385     { Bad_Opcode },
8386     { Bad_Opcode },
8387     { Bad_Opcode },
8388     { Bad_Opcode },
8389     { Bad_Opcode },
8390     { Bad_Opcode },
8391     /* c0 */
8392     { Bad_Opcode },
8393     { Bad_Opcode },
8394     { Bad_Opcode },
8395     { Bad_Opcode },
8396     { Bad_Opcode },
8397     { Bad_Opcode },
8398     { Bad_Opcode },
8399     { Bad_Opcode },
8400     /* c8 */
8401     { Bad_Opcode },
8402     { Bad_Opcode },
8403     { Bad_Opcode },
8404     { Bad_Opcode },
8405     { Bad_Opcode },
8406     { Bad_Opcode },
8407     { Bad_Opcode },
8408     { Bad_Opcode },
8409     /* d0 */
8410     { Bad_Opcode },
8411     { Bad_Opcode },
8412     { Bad_Opcode },
8413     { Bad_Opcode },
8414     { Bad_Opcode },
8415     { Bad_Opcode },
8416     { Bad_Opcode },
8417     { Bad_Opcode },
8418     /* d8 */
8419     { Bad_Opcode },
8420     { Bad_Opcode },
8421     { Bad_Opcode },
8422     { Bad_Opcode },
8423     { Bad_Opcode },
8424     { Bad_Opcode },
8425     { Bad_Opcode },
8426     { Bad_Opcode },
8427     /* e0 */
8428     { Bad_Opcode },
8429     { Bad_Opcode },
8430     { Bad_Opcode },
8431     { Bad_Opcode },
8432     { Bad_Opcode },
8433     { Bad_Opcode },
8434     { Bad_Opcode },
8435     { Bad_Opcode },
8436     /* e8 */
8437     { Bad_Opcode },
8438     { Bad_Opcode },
8439     { Bad_Opcode },
8440     { Bad_Opcode },
8441     { Bad_Opcode },
8442     { Bad_Opcode },
8443     { Bad_Opcode },
8444     { Bad_Opcode },
8445     /* f0 */
8446     { Bad_Opcode },
8447     { Bad_Opcode },
8448     { Bad_Opcode },
8449     { Bad_Opcode },
8450     { Bad_Opcode },
8451     { Bad_Opcode },
8452     { Bad_Opcode },
8453     { Bad_Opcode },
8454     /* f8 */
8455     { Bad_Opcode },
8456     { Bad_Opcode },
8457     { Bad_Opcode },
8458     { Bad_Opcode },
8459     { Bad_Opcode },
8460     { Bad_Opcode },
8461     { Bad_Opcode },
8462     { Bad_Opcode },
8463   },
8464 };
8465
8466 static const struct dis386 vex_table[][256] = {
8467   /* VEX_0F */
8468   {
8469     /* 00 */
8470     { Bad_Opcode },
8471     { Bad_Opcode },
8472     { Bad_Opcode },
8473     { Bad_Opcode },
8474     { Bad_Opcode },
8475     { Bad_Opcode },
8476     { Bad_Opcode },
8477     { Bad_Opcode },
8478     /* 08 */
8479     { Bad_Opcode },
8480     { Bad_Opcode },
8481     { Bad_Opcode },
8482     { Bad_Opcode },
8483     { Bad_Opcode },
8484     { Bad_Opcode },
8485     { Bad_Opcode },
8486     { Bad_Opcode },
8487     /* 10 */
8488     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8489     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8490     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8491     { MOD_TABLE (MOD_VEX_0F13) },
8492     { "vunpcklpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
8493     { "vunpckhpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
8494     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8495     { MOD_TABLE (MOD_VEX_0F17) },
8496     /* 18 */
8497     { Bad_Opcode },
8498     { Bad_Opcode },
8499     { Bad_Opcode },
8500     { Bad_Opcode },
8501     { Bad_Opcode },
8502     { Bad_Opcode },
8503     { Bad_Opcode },
8504     { Bad_Opcode },
8505     /* 20 */
8506     { Bad_Opcode },
8507     { Bad_Opcode },
8508     { Bad_Opcode },
8509     { Bad_Opcode },
8510     { Bad_Opcode },
8511     { Bad_Opcode },
8512     { Bad_Opcode },
8513     { Bad_Opcode },
8514     /* 28 */
8515     { "vmovapX",        { XM, EXx }, PREFIX_OPCODE },
8516     { "vmovapX",        { EXxS, XM }, PREFIX_OPCODE },
8517     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8518     { MOD_TABLE (MOD_VEX_0F2B) },
8519     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8520     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8521     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8522     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8523     /* 30 */
8524     { Bad_Opcode },
8525     { Bad_Opcode },
8526     { Bad_Opcode },
8527     { Bad_Opcode },
8528     { Bad_Opcode },
8529     { Bad_Opcode },
8530     { Bad_Opcode },
8531     { Bad_Opcode },
8532     /* 38 */
8533     { Bad_Opcode },
8534     { Bad_Opcode },
8535     { Bad_Opcode },
8536     { Bad_Opcode },
8537     { Bad_Opcode },
8538     { Bad_Opcode },
8539     { Bad_Opcode },
8540     { Bad_Opcode },
8541     /* 40 */
8542     { Bad_Opcode },
8543     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8544     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8545     { Bad_Opcode },
8546     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8547     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8548     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8549     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8550     /* 48 */
8551     { Bad_Opcode },
8552     { Bad_Opcode },
8553     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8554     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8555     { Bad_Opcode },
8556     { Bad_Opcode },
8557     { Bad_Opcode },
8558     { Bad_Opcode },
8559     /* 50 */
8560     { MOD_TABLE (MOD_VEX_0F50) },
8561     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8562     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8563     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8564     { "vandpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
8565     { "vandnpX",        { XM, Vex, EXx }, PREFIX_OPCODE },
8566     { "vorpX",          { XM, Vex, EXx }, PREFIX_OPCODE },
8567     { "vxorpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
8568     /* 58 */
8569     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8570     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8571     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8572     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8573     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8574     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8575     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8576     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8577     /* 60 */
8578     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8579     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8580     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8581     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8582     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8583     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8584     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8585     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8586     /* 68 */
8587     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8588     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8589     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8590     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8591     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8592     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8593     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8594     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8595     /* 70 */
8596     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8597     { REG_TABLE (REG_VEX_0F71) },
8598     { REG_TABLE (REG_VEX_0F72) },
8599     { REG_TABLE (REG_VEX_0F73) },
8600     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8601     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8602     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8603     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8604     /* 78 */
8605     { Bad_Opcode },
8606     { Bad_Opcode },
8607     { Bad_Opcode },
8608     { Bad_Opcode },
8609     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8610     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8611     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8612     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8613     /* 80 */
8614     { Bad_Opcode },
8615     { Bad_Opcode },
8616     { Bad_Opcode },
8617     { Bad_Opcode },
8618     { Bad_Opcode },
8619     { Bad_Opcode },
8620     { Bad_Opcode },
8621     { Bad_Opcode },
8622     /* 88 */
8623     { Bad_Opcode },
8624     { Bad_Opcode },
8625     { Bad_Opcode },
8626     { Bad_Opcode },
8627     { Bad_Opcode },
8628     { Bad_Opcode },
8629     { Bad_Opcode },
8630     { Bad_Opcode },
8631     /* 90 */
8632     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8633     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8634     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8635     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8636     { Bad_Opcode },
8637     { Bad_Opcode },
8638     { Bad_Opcode },
8639     { Bad_Opcode },
8640     /* 98 */
8641     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8642     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8643     { Bad_Opcode },
8644     { Bad_Opcode },
8645     { Bad_Opcode },
8646     { Bad_Opcode },
8647     { Bad_Opcode },
8648     { Bad_Opcode },
8649     /* a0 */
8650     { Bad_Opcode },
8651     { Bad_Opcode },
8652     { Bad_Opcode },
8653     { Bad_Opcode },
8654     { Bad_Opcode },
8655     { Bad_Opcode },
8656     { Bad_Opcode },
8657     { Bad_Opcode },
8658     /* a8 */
8659     { Bad_Opcode },
8660     { Bad_Opcode },
8661     { Bad_Opcode },
8662     { Bad_Opcode },
8663     { Bad_Opcode },
8664     { Bad_Opcode },
8665     { REG_TABLE (REG_VEX_0FAE) },
8666     { Bad_Opcode },
8667     /* b0 */
8668     { Bad_Opcode },
8669     { Bad_Opcode },
8670     { Bad_Opcode },
8671     { Bad_Opcode },
8672     { Bad_Opcode },
8673     { Bad_Opcode },
8674     { Bad_Opcode },
8675     { Bad_Opcode },
8676     /* b8 */
8677     { Bad_Opcode },
8678     { Bad_Opcode },
8679     { Bad_Opcode },
8680     { Bad_Opcode },
8681     { Bad_Opcode },
8682     { Bad_Opcode },
8683     { Bad_Opcode },
8684     { Bad_Opcode },
8685     /* c0 */
8686     { Bad_Opcode },
8687     { Bad_Opcode },
8688     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8689     { Bad_Opcode },
8690     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8691     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8692     { "vshufpX",        { XM, Vex, EXx, Ib }, PREFIX_OPCODE },
8693     { Bad_Opcode },
8694     /* c8 */
8695     { Bad_Opcode },
8696     { Bad_Opcode },
8697     { Bad_Opcode },
8698     { Bad_Opcode },
8699     { Bad_Opcode },
8700     { Bad_Opcode },
8701     { Bad_Opcode },
8702     { Bad_Opcode },
8703     /* d0 */
8704     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8705     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8706     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8707     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8708     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8709     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8710     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8711     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8712     /* d8 */
8713     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8714     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8715     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8716     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8717     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8718     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8719     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8720     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8721     /* e0 */
8722     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8723     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8724     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8725     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8726     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8727     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8728     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8729     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8730     /* e8 */
8731     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8732     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8733     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8734     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8735     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8736     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8737     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8738     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8739     /* f0 */
8740     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8741     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8742     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8743     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8744     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8745     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8746     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8747     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8748     /* f8 */
8749     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8750     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8751     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8752     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8753     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8754     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8755     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8756     { Bad_Opcode },
8757   },
8758   /* VEX_0F38 */
8759   {
8760     /* 00 */
8761     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8762     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8763     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8764     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8765     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8766     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8767     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8768     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8769     /* 08 */
8770     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8771     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8772     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8773     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8774     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8775     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8776     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8777     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8778     /* 10 */
8779     { Bad_Opcode },
8780     { Bad_Opcode },
8781     { Bad_Opcode },
8782     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8783     { Bad_Opcode },
8784     { Bad_Opcode },
8785     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8786     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8787     /* 18 */
8788     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8789     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8790     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8791     { Bad_Opcode },
8792     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8793     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8794     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8795     { Bad_Opcode },
8796     /* 20 */
8797     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8798     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8799     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8800     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8801     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8802     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8803     { Bad_Opcode },
8804     { Bad_Opcode },
8805     /* 28 */
8806     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8807     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8808     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8809     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8810     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8811     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8812     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8813     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8814     /* 30 */
8815     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8816     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8817     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8818     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8819     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8820     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8821     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8822     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8823     /* 38 */
8824     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8825     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8826     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8827     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8828     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8829     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8830     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8831     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8832     /* 40 */
8833     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8834     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8835     { Bad_Opcode },
8836     { Bad_Opcode },
8837     { Bad_Opcode },
8838     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8839     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8840     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8841     /* 48 */
8842     { Bad_Opcode },
8843     { X86_64_TABLE (X86_64_VEX_0F3849) },
8844     { Bad_Opcode },
8845     { X86_64_TABLE (X86_64_VEX_0F384B) },
8846     { Bad_Opcode },
8847     { Bad_Opcode },
8848     { Bad_Opcode },
8849     { Bad_Opcode },
8850     /* 50 */
8851     { Bad_Opcode },
8852     { Bad_Opcode },
8853     { Bad_Opcode },
8854     { Bad_Opcode },
8855     { Bad_Opcode },
8856     { Bad_Opcode },
8857     { Bad_Opcode },
8858     { Bad_Opcode },
8859     /* 58 */
8860     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8861     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8862     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8863     { Bad_Opcode },
8864     { X86_64_TABLE (X86_64_VEX_0F385C) },
8865     { Bad_Opcode },
8866     { X86_64_TABLE (X86_64_VEX_0F385E) },
8867     { Bad_Opcode },
8868     /* 60 */
8869     { Bad_Opcode },
8870     { Bad_Opcode },
8871     { Bad_Opcode },
8872     { Bad_Opcode },
8873     { Bad_Opcode },
8874     { Bad_Opcode },
8875     { Bad_Opcode },
8876     { Bad_Opcode },
8877     /* 68 */
8878     { Bad_Opcode },
8879     { Bad_Opcode },
8880     { Bad_Opcode },
8881     { Bad_Opcode },
8882     { Bad_Opcode },
8883     { Bad_Opcode },
8884     { Bad_Opcode },
8885     { Bad_Opcode },
8886     /* 70 */
8887     { Bad_Opcode },
8888     { Bad_Opcode },
8889     { Bad_Opcode },
8890     { Bad_Opcode },
8891     { Bad_Opcode },
8892     { Bad_Opcode },
8893     { Bad_Opcode },
8894     { Bad_Opcode },
8895     /* 78 */
8896     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
8897     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
8898     { Bad_Opcode },
8899     { Bad_Opcode },
8900     { Bad_Opcode },
8901     { Bad_Opcode },
8902     { Bad_Opcode },
8903     { Bad_Opcode },
8904     /* 80 */
8905     { Bad_Opcode },
8906     { Bad_Opcode },
8907     { Bad_Opcode },
8908     { Bad_Opcode },
8909     { Bad_Opcode },
8910     { Bad_Opcode },
8911     { Bad_Opcode },
8912     { Bad_Opcode },
8913     /* 88 */
8914     { Bad_Opcode },
8915     { Bad_Opcode },
8916     { Bad_Opcode },
8917     { Bad_Opcode },
8918     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
8919     { Bad_Opcode },
8920     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
8921     { Bad_Opcode },
8922     /* 90 */
8923     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
8924     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
8925     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
8926     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
8927     { Bad_Opcode },
8928     { Bad_Opcode },
8929     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
8930     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
8931     /* 98 */
8932     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
8933     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
8934     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
8935     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
8936     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
8937     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
8938     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
8939     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
8940     /* a0 */
8941     { Bad_Opcode },
8942     { Bad_Opcode },
8943     { Bad_Opcode },
8944     { Bad_Opcode },
8945     { Bad_Opcode },
8946     { Bad_Opcode },
8947     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
8948     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
8949     /* a8 */
8950     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
8951     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
8952     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
8953     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
8954     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
8955     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
8956     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
8957     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
8958     /* b0 */
8959     { Bad_Opcode },
8960     { Bad_Opcode },
8961     { Bad_Opcode },
8962     { Bad_Opcode },
8963     { Bad_Opcode },
8964     { Bad_Opcode },
8965     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
8966     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
8967     /* b8 */
8968     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
8969     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
8970     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
8971     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
8972     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
8973     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
8974     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
8975     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
8976     /* c0 */
8977     { Bad_Opcode },
8978     { Bad_Opcode },
8979     { Bad_Opcode },
8980     { Bad_Opcode },
8981     { Bad_Opcode },
8982     { Bad_Opcode },
8983     { Bad_Opcode },
8984     { Bad_Opcode },
8985     /* c8 */
8986     { Bad_Opcode },
8987     { Bad_Opcode },
8988     { Bad_Opcode },
8989     { Bad_Opcode },
8990     { Bad_Opcode },
8991     { Bad_Opcode },
8992     { Bad_Opcode },
8993     { PREFIX_TABLE (PREFIX_VEX_0F38CF) },
8994     /* d0 */
8995     { Bad_Opcode },
8996     { Bad_Opcode },
8997     { Bad_Opcode },
8998     { Bad_Opcode },
8999     { Bad_Opcode },
9000     { Bad_Opcode },
9001     { Bad_Opcode },
9002     { Bad_Opcode },
9003     /* d8 */
9004     { Bad_Opcode },
9005     { Bad_Opcode },
9006     { Bad_Opcode },
9007     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
9008     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
9009     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
9010     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
9011     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
9012     /* e0 */
9013     { Bad_Opcode },
9014     { Bad_Opcode },
9015     { Bad_Opcode },
9016     { Bad_Opcode },
9017     { Bad_Opcode },
9018     { Bad_Opcode },
9019     { Bad_Opcode },
9020     { Bad_Opcode },
9021     /* e8 */
9022     { Bad_Opcode },
9023     { Bad_Opcode },
9024     { Bad_Opcode },
9025     { Bad_Opcode },
9026     { Bad_Opcode },
9027     { Bad_Opcode },
9028     { Bad_Opcode },
9029     { Bad_Opcode },
9030     /* f0 */
9031     { Bad_Opcode },
9032     { Bad_Opcode },
9033     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
9034     { REG_TABLE (REG_VEX_0F38F3) },
9035     { Bad_Opcode },
9036     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9037     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9038     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9039     /* f8 */
9040     { Bad_Opcode },
9041     { Bad_Opcode },
9042     { Bad_Opcode },
9043     { Bad_Opcode },
9044     { Bad_Opcode },
9045     { Bad_Opcode },
9046     { Bad_Opcode },
9047     { Bad_Opcode },
9048   },
9049   /* VEX_0F3A */
9050   {
9051     /* 00 */
9052     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9053     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9054     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9055     { Bad_Opcode },
9056     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9057     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9058     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9059     { Bad_Opcode },
9060     /* 08 */
9061     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9062     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9063     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9064     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9065     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9066     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9067     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9068     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9069     /* 10 */
9070     { Bad_Opcode },
9071     { Bad_Opcode },
9072     { Bad_Opcode },
9073     { Bad_Opcode },
9074     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9075     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9076     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9077     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9078     /* 18 */
9079     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9080     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9081     { Bad_Opcode },
9082     { Bad_Opcode },
9083     { Bad_Opcode },
9084     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9085     { Bad_Opcode },
9086     { Bad_Opcode },
9087     /* 20 */
9088     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9089     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9090     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9091     { Bad_Opcode },
9092     { Bad_Opcode },
9093     { Bad_Opcode },
9094     { Bad_Opcode },
9095     { Bad_Opcode },
9096     /* 28 */
9097     { Bad_Opcode },
9098     { Bad_Opcode },
9099     { Bad_Opcode },
9100     { Bad_Opcode },
9101     { Bad_Opcode },
9102     { Bad_Opcode },
9103     { Bad_Opcode },
9104     { Bad_Opcode },
9105     /* 30 */
9106     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9107     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9108     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9109     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9110     { Bad_Opcode },
9111     { Bad_Opcode },
9112     { Bad_Opcode },
9113     { Bad_Opcode },
9114     /* 38 */
9115     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9116     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9117     { Bad_Opcode },
9118     { Bad_Opcode },
9119     { Bad_Opcode },
9120     { Bad_Opcode },
9121     { Bad_Opcode },
9122     { Bad_Opcode },
9123     /* 40 */
9124     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9125     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9126     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9127     { Bad_Opcode },
9128     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9129     { Bad_Opcode },
9130     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9131     { Bad_Opcode },
9132     /* 48 */
9133     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9134     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9135     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9136     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9137     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9138     { Bad_Opcode },
9139     { Bad_Opcode },
9140     { Bad_Opcode },
9141     /* 50 */
9142     { Bad_Opcode },
9143     { Bad_Opcode },
9144     { Bad_Opcode },
9145     { Bad_Opcode },
9146     { Bad_Opcode },
9147     { Bad_Opcode },
9148     { Bad_Opcode },
9149     { Bad_Opcode },
9150     /* 58 */
9151     { Bad_Opcode },
9152     { Bad_Opcode },
9153     { Bad_Opcode },
9154     { Bad_Opcode },
9155     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9156     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9157     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9158     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9159     /* 60 */
9160     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9161     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9162     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9163     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9164     { Bad_Opcode },
9165     { Bad_Opcode },
9166     { Bad_Opcode },
9167     { Bad_Opcode },
9168     /* 68 */
9169     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9170     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9171     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9172     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9173     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9174     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9175     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9176     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9177     /* 70 */
9178     { Bad_Opcode },
9179     { Bad_Opcode },
9180     { Bad_Opcode },
9181     { Bad_Opcode },
9182     { Bad_Opcode },
9183     { Bad_Opcode },
9184     { Bad_Opcode },
9185     { Bad_Opcode },
9186     /* 78 */
9187     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9188     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9189     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9190     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9191     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9192     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9193     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9194     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9195     /* 80 */
9196     { Bad_Opcode },
9197     { Bad_Opcode },
9198     { Bad_Opcode },
9199     { Bad_Opcode },
9200     { Bad_Opcode },
9201     { Bad_Opcode },
9202     { Bad_Opcode },
9203     { Bad_Opcode },
9204     /* 88 */
9205     { Bad_Opcode },
9206     { Bad_Opcode },
9207     { Bad_Opcode },
9208     { Bad_Opcode },
9209     { Bad_Opcode },
9210     { Bad_Opcode },
9211     { Bad_Opcode },
9212     { Bad_Opcode },
9213     /* 90 */
9214     { Bad_Opcode },
9215     { Bad_Opcode },
9216     { Bad_Opcode },
9217     { Bad_Opcode },
9218     { Bad_Opcode },
9219     { Bad_Opcode },
9220     { Bad_Opcode },
9221     { Bad_Opcode },
9222     /* 98 */
9223     { Bad_Opcode },
9224     { Bad_Opcode },
9225     { Bad_Opcode },
9226     { Bad_Opcode },
9227     { Bad_Opcode },
9228     { Bad_Opcode },
9229     { Bad_Opcode },
9230     { Bad_Opcode },
9231     /* a0 */
9232     { Bad_Opcode },
9233     { Bad_Opcode },
9234     { Bad_Opcode },
9235     { Bad_Opcode },
9236     { Bad_Opcode },
9237     { Bad_Opcode },
9238     { Bad_Opcode },
9239     { Bad_Opcode },
9240     /* a8 */
9241     { Bad_Opcode },
9242     { Bad_Opcode },
9243     { Bad_Opcode },
9244     { Bad_Opcode },
9245     { Bad_Opcode },
9246     { Bad_Opcode },
9247     { Bad_Opcode },
9248     { Bad_Opcode },
9249     /* b0 */
9250     { Bad_Opcode },
9251     { Bad_Opcode },
9252     { Bad_Opcode },
9253     { Bad_Opcode },
9254     { Bad_Opcode },
9255     { Bad_Opcode },
9256     { Bad_Opcode },
9257     { Bad_Opcode },
9258     /* b8 */
9259     { Bad_Opcode },
9260     { Bad_Opcode },
9261     { Bad_Opcode },
9262     { Bad_Opcode },
9263     { Bad_Opcode },
9264     { Bad_Opcode },
9265     { Bad_Opcode },
9266     { Bad_Opcode },
9267     /* c0 */
9268     { Bad_Opcode },
9269     { Bad_Opcode },
9270     { Bad_Opcode },
9271     { Bad_Opcode },
9272     { Bad_Opcode },
9273     { Bad_Opcode },
9274     { Bad_Opcode },
9275     { Bad_Opcode },
9276     /* c8 */
9277     { Bad_Opcode },
9278     { Bad_Opcode },
9279     { Bad_Opcode },
9280     { Bad_Opcode },
9281     { Bad_Opcode },
9282     { Bad_Opcode },
9283     { PREFIX_TABLE(PREFIX_VEX_0F3ACE) },
9284     { PREFIX_TABLE(PREFIX_VEX_0F3ACF) },
9285     /* d0 */
9286     { Bad_Opcode },
9287     { Bad_Opcode },
9288     { Bad_Opcode },
9289     { Bad_Opcode },
9290     { Bad_Opcode },
9291     { Bad_Opcode },
9292     { Bad_Opcode },
9293     { Bad_Opcode },
9294     /* d8 */
9295     { Bad_Opcode },
9296     { Bad_Opcode },
9297     { Bad_Opcode },
9298     { Bad_Opcode },
9299     { Bad_Opcode },
9300     { Bad_Opcode },
9301     { Bad_Opcode },
9302     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9303     /* e0 */
9304     { Bad_Opcode },
9305     { Bad_Opcode },
9306     { Bad_Opcode },
9307     { Bad_Opcode },
9308     { Bad_Opcode },
9309     { Bad_Opcode },
9310     { Bad_Opcode },
9311     { Bad_Opcode },
9312     /* e8 */
9313     { Bad_Opcode },
9314     { Bad_Opcode },
9315     { Bad_Opcode },
9316     { Bad_Opcode },
9317     { Bad_Opcode },
9318     { Bad_Opcode },
9319     { Bad_Opcode },
9320     { Bad_Opcode },
9321     /* f0 */
9322     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9323     { Bad_Opcode },
9324     { Bad_Opcode },
9325     { Bad_Opcode },
9326     { Bad_Opcode },
9327     { Bad_Opcode },
9328     { Bad_Opcode },
9329     { Bad_Opcode },
9330     /* f8 */
9331     { Bad_Opcode },
9332     { Bad_Opcode },
9333     { Bad_Opcode },
9334     { Bad_Opcode },
9335     { Bad_Opcode },
9336     { Bad_Opcode },
9337     { Bad_Opcode },
9338     { Bad_Opcode },
9339   },
9340 };
9341
9342 #include "i386-dis-evex.h"
9343
9344 static const struct dis386 vex_len_table[][2] = {
9345   /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */
9346   {
9347     { "vmovlpX",        { XM, Vex128, EXq }, 0 },
9348   },
9349
9350   /* VEX_LEN_0F12_P_0_M_1 */
9351   {
9352     { "vmovhlps",       { XM, Vex128, EXq }, 0 },
9353   },
9354
9355   /* VEX_LEN_0F13_M_0 */
9356   {
9357     { "vmovlpX",        { EXq, XM }, PREFIX_OPCODE },
9358   },
9359
9360   /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */
9361   {
9362     { "vmovhpX",        { XM, Vex128, EXq }, 0 },
9363   },
9364
9365   /* VEX_LEN_0F16_P_0_M_1 */
9366   {
9367     { "vmovlhps",       { XM, Vex128, EXq }, 0 },
9368   },
9369
9370   /* VEX_LEN_0F17_M_0 */
9371   {
9372     { "vmovhpX",        { EXq, XM }, PREFIX_OPCODE },
9373   },
9374
9375   /* VEX_LEN_0F41_P_0 */
9376   {
9377     { Bad_Opcode },
9378     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9379   },
9380   /* VEX_LEN_0F41_P_2 */
9381   {
9382     { Bad_Opcode },
9383     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9384   },
9385   /* VEX_LEN_0F42_P_0 */
9386   {
9387     { Bad_Opcode },
9388     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9389   },
9390   /* VEX_LEN_0F42_P_2 */
9391   {
9392     { Bad_Opcode },
9393     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9394   },
9395   /* VEX_LEN_0F44_P_0 */
9396   {
9397     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9398   },
9399   /* VEX_LEN_0F44_P_2 */
9400   {
9401     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9402   },
9403   /* VEX_LEN_0F45_P_0 */
9404   {
9405     { Bad_Opcode },
9406     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9407   },
9408   /* VEX_LEN_0F45_P_2 */
9409   {
9410     { Bad_Opcode },
9411     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9412   },
9413   /* VEX_LEN_0F46_P_0 */
9414   {
9415     { Bad_Opcode },
9416     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9417   },
9418   /* VEX_LEN_0F46_P_2 */
9419   {
9420     { Bad_Opcode },
9421     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9422   },
9423   /* VEX_LEN_0F47_P_0 */
9424   {
9425     { Bad_Opcode },
9426     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9427   },
9428   /* VEX_LEN_0F47_P_2 */
9429   {
9430     { Bad_Opcode },
9431     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9432   },
9433   /* VEX_LEN_0F4A_P_0 */
9434   {
9435     { Bad_Opcode },
9436     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9437   },
9438   /* VEX_LEN_0F4A_P_2 */
9439   {
9440     { Bad_Opcode },
9441     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9442   },
9443   /* VEX_LEN_0F4B_P_0 */
9444   {
9445     { Bad_Opcode },
9446     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9447   },
9448   /* VEX_LEN_0F4B_P_2 */
9449   {
9450     { Bad_Opcode },
9451     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9452   },
9453
9454   /* VEX_LEN_0F6E_P_2 */
9455   {
9456     { "vmovK",          { XMScalar, Edq }, 0 },
9457   },
9458
9459   /* VEX_LEN_0F77_P_1 */
9460   {
9461     { "vzeroupper",     { XX }, 0 },
9462     { "vzeroall",       { XX }, 0 },
9463   },
9464
9465   /* VEX_LEN_0F7E_P_1 */
9466   {
9467     { "vmovq",          { XMScalar, EXxmm_mq }, 0 },
9468   },
9469
9470   /* VEX_LEN_0F7E_P_2 */
9471   {
9472     { "vmovK",          { Edq, XMScalar }, 0 },
9473   },
9474
9475   /* VEX_LEN_0F90_P_0 */
9476   {
9477     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9478   },
9479
9480   /* VEX_LEN_0F90_P_2 */
9481   {
9482     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9483   },
9484
9485   /* VEX_LEN_0F91_P_0 */
9486   {
9487     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9488   },
9489
9490   /* VEX_LEN_0F91_P_2 */
9491   {
9492     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9493   },
9494
9495   /* VEX_LEN_0F92_P_0 */
9496   {
9497     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9498   },
9499
9500   /* VEX_LEN_0F92_P_2 */
9501   {
9502     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9503   },
9504
9505   /* VEX_LEN_0F92_P_3 */
9506   {
9507     { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) },
9508   },
9509
9510   /* VEX_LEN_0F93_P_0 */
9511   {
9512     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9513   },
9514
9515   /* VEX_LEN_0F93_P_2 */
9516   {
9517     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9518   },
9519
9520   /* VEX_LEN_0F93_P_3 */
9521   {
9522     { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) },
9523   },
9524
9525   /* VEX_LEN_0F98_P_0 */
9526   {
9527     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9528   },
9529
9530   /* VEX_LEN_0F98_P_2 */
9531   {
9532     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9533   },
9534
9535   /* VEX_LEN_0F99_P_0 */
9536   {
9537     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9538   },
9539
9540   /* VEX_LEN_0F99_P_2 */
9541   {
9542     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9543   },
9544
9545   /* VEX_LEN_0FAE_R_2_M_0 */
9546   {
9547     { "vldmxcsr",       { Md }, 0 },
9548   },
9549
9550   /* VEX_LEN_0FAE_R_3_M_0 */
9551   {
9552     { "vstmxcsr",       { Md }, 0 },
9553   },
9554
9555   /* VEX_LEN_0FC4_P_2 */
9556   {
9557     { "vpinsrw",        { XM, Vex128, Edqw, Ib }, 0 },
9558   },
9559
9560   /* VEX_LEN_0FC5_P_2 */
9561   {
9562     { "vpextrw",        { Gdq, XS, Ib }, 0 },
9563   },
9564
9565   /* VEX_LEN_0FD6_P_2 */
9566   {
9567     { "vmovq",          { EXqVexScalarS, XMScalar }, 0 },
9568   },
9569
9570   /* VEX_LEN_0FF7_P_2 */
9571   {
9572     { "vmaskmovdqu",    { XM, XS }, 0 },
9573   },
9574
9575   /* VEX_LEN_0F3816_P_2 */
9576   {
9577     { Bad_Opcode },
9578     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9579   },
9580
9581   /* VEX_LEN_0F3819_P_2 */
9582   {
9583     { Bad_Opcode },
9584     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9585   },
9586
9587   /* VEX_LEN_0F381A_P_2_M_0 */
9588   {
9589     { Bad_Opcode },
9590     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9591   },
9592
9593   /* VEX_LEN_0F3836_P_2 */
9594   {
9595     { Bad_Opcode },
9596     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9597   },
9598
9599   /* VEX_LEN_0F3841_P_2 */
9600   {
9601     { "vphminposuw",    { XM, EXx }, 0 },
9602   },
9603
9604    /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_0 */
9605   {
9606     { "ldtilecfg", { M }, 0 },
9607   },
9608
9609   /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0 */
9610   {
9611     { "tilerelease", { Skip_MODRM }, 0 },
9612   },
9613
9614   /* VEX_LEN_0F3849_X86_64_P_2_W_0_M_0 */
9615   {
9616     { "sttilecfg", { M }, 0 },
9617   },
9618
9619   /* VEX_LEN_0F3849_X86_64_P_3_W_0_M_0 */
9620   {
9621     { "tilezero", { TMM, Skip_MODRM }, 0 },
9622   },
9623
9624   /* VEX_LEN_0F384B_X86_64_P_1_W_0_M_0 */
9625   {
9626     { "tilestored", { MVexSIBMEM, TMM }, 0 },
9627   },
9628   /* VEX_LEN_0F384B_X86_64_P_2_W_0_M_0 */
9629   {
9630     { "tileloaddt1", { TMM, MVexSIBMEM }, 0 },
9631   },
9632
9633   /* VEX_LEN_0F384B_X86_64_P_3_W_0_M_0 */
9634   {
9635     { "tileloadd", { TMM, MVexSIBMEM }, 0 },
9636   },
9637
9638   /* VEX_LEN_0F385A_P_2_M_0 */
9639   {
9640     { Bad_Opcode },
9641     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9642   },
9643
9644   /* VEX_LEN_0F385C_X86_64_P_1_W_0_M_0 */
9645   {
9646     { "tdpbf16ps", { TMM, EXtmm, VexTmm }, 0 },
9647   },
9648
9649   /* VEX_LEN_0F385E_X86_64_P_0_W_0_M_0 */
9650   {
9651     { "tdpbuud", {TMM, EXtmm, VexTmm }, 0 },
9652   },
9653
9654   /* VEX_LEN_0F385E_X86_64_P_1_W_0_M_0 */
9655   {
9656     { "tdpbsud", {TMM, EXtmm, VexTmm }, 0 },
9657   },
9658
9659   /* VEX_LEN_0F385E_X86_64_P_2_W_0_M_0 */
9660   {
9661     { "tdpbusd", {TMM, EXtmm, VexTmm }, 0 },
9662   },
9663
9664   /* VEX_LEN_0F385E_X86_64_P_3_W_0_M_0 */
9665   {
9666     { "tdpbssd", {TMM, EXtmm, VexTmm }, 0 },
9667   },
9668
9669   /* VEX_LEN_0F38DB_P_2 */
9670   {
9671     { "vaesimc",        { XM, EXx }, 0 },
9672   },
9673
9674   /* VEX_LEN_0F38F2_P_0 */
9675   {
9676     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
9677   },
9678
9679   /* VEX_LEN_0F38F3_R_1_P_0 */
9680   {
9681     { "blsrS",          { VexGdq, Edq }, 0 },
9682   },
9683
9684   /* VEX_LEN_0F38F3_R_2_P_0 */
9685   {
9686     { "blsmskS",        { VexGdq, Edq }, 0 },
9687   },
9688
9689   /* VEX_LEN_0F38F3_R_3_P_0 */
9690   {
9691     { "blsiS",          { VexGdq, Edq }, 0 },
9692   },
9693
9694   /* VEX_LEN_0F38F5_P_0 */
9695   {
9696     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
9697   },
9698
9699   /* VEX_LEN_0F38F5_P_1 */
9700   {
9701     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
9702   },
9703
9704   /* VEX_LEN_0F38F5_P_3 */
9705   {
9706     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
9707   },
9708
9709   /* VEX_LEN_0F38F6_P_3 */
9710   {
9711     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
9712   },
9713
9714   /* VEX_LEN_0F38F7_P_0 */
9715   {
9716     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
9717   },
9718
9719   /* VEX_LEN_0F38F7_P_1 */
9720   {
9721     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
9722   },
9723
9724   /* VEX_LEN_0F38F7_P_2 */
9725   {
9726     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
9727   },
9728
9729   /* VEX_LEN_0F38F7_P_3 */
9730   {
9731     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
9732   },
9733
9734   /* VEX_LEN_0F3A00_P_2 */
9735   {
9736     { Bad_Opcode },
9737     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
9738   },
9739
9740   /* VEX_LEN_0F3A01_P_2 */
9741   {
9742     { Bad_Opcode },
9743     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
9744   },
9745
9746   /* VEX_LEN_0F3A06_P_2 */
9747   {
9748     { Bad_Opcode },
9749     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
9750   },
9751
9752   /* VEX_LEN_0F3A14_P_2 */
9753   {
9754     { "vpextrb",        { Edqb, XM, Ib }, 0 },
9755   },
9756
9757   /* VEX_LEN_0F3A15_P_2 */
9758   {
9759     { "vpextrw",        { Edqw, XM, Ib }, 0 },
9760   },
9761
9762   /* VEX_LEN_0F3A16_P_2  */
9763   {
9764     { "vpextrK",        { Edq, XM, Ib }, 0 },
9765   },
9766
9767   /* VEX_LEN_0F3A17_P_2 */
9768   {
9769     { "vextractps",     { Edqd, XM, Ib }, 0 },
9770   },
9771
9772   /* VEX_LEN_0F3A18_P_2 */
9773   {
9774     { Bad_Opcode },
9775     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
9776   },
9777
9778   /* VEX_LEN_0F3A19_P_2 */
9779   {
9780     { Bad_Opcode },
9781     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
9782   },
9783
9784   /* VEX_LEN_0F3A20_P_2 */
9785   {
9786     { "vpinsrb",        { XM, Vex128, Edqb, Ib }, 0 },
9787   },
9788
9789   /* VEX_LEN_0F3A21_P_2 */
9790   {
9791     { "vinsertps",      { XM, Vex128, EXd, Ib }, 0 },
9792   },
9793
9794   /* VEX_LEN_0F3A22_P_2 */
9795   {
9796     { "vpinsrK",        { XM, Vex128, Edq, Ib }, 0 },
9797   },
9798
9799   /* VEX_LEN_0F3A30_P_2 */
9800   {
9801     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
9802   },
9803
9804   /* VEX_LEN_0F3A31_P_2 */
9805   {
9806     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
9807   },
9808
9809   /* VEX_LEN_0F3A32_P_2 */
9810   {
9811     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
9812   },
9813
9814   /* VEX_LEN_0F3A33_P_2 */
9815   {
9816     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
9817   },
9818
9819   /* VEX_LEN_0F3A38_P_2 */
9820   {
9821     { Bad_Opcode },
9822     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
9823   },
9824
9825   /* VEX_LEN_0F3A39_P_2 */
9826   {
9827     { Bad_Opcode },
9828     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
9829   },
9830
9831   /* VEX_LEN_0F3A41_P_2 */
9832   {
9833     { "vdppd",          { XM, Vex128, EXx, Ib }, 0 },
9834   },
9835
9836   /* VEX_LEN_0F3A46_P_2 */
9837   {
9838     { Bad_Opcode },
9839     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
9840   },
9841
9842   /* VEX_LEN_0F3A60_P_2 */
9843   {
9844     { "vpcmpestrm!%LQ", { XM, EXx, Ib }, 0 },
9845   },
9846
9847   /* VEX_LEN_0F3A61_P_2 */
9848   {
9849     { "vpcmpestri!%LQ", { XM, EXx, Ib }, 0 },
9850   },
9851
9852   /* VEX_LEN_0F3A62_P_2 */
9853   {
9854     { "vpcmpistrm",     { XM, EXx, Ib }, 0 },
9855   },
9856
9857   /* VEX_LEN_0F3A63_P_2 */
9858   {
9859     { "vpcmpistri",     { XM, EXx, Ib }, 0 },
9860   },
9861
9862   /* VEX_LEN_0F3ADF_P_2 */
9863   {
9864     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
9865   },
9866
9867   /* VEX_LEN_0F3AF0_P_3 */
9868   {
9869     { "rorxS",          { Gdq, Edq, Ib }, 0 },
9870   },
9871
9872   /* VEX_LEN_0FXOP_08_85 */
9873   {
9874     { VEX_W_TABLE (VEX_W_0FXOP_08_85_L_0) },
9875   },
9876
9877   /* VEX_LEN_0FXOP_08_86 */
9878   {
9879     { VEX_W_TABLE (VEX_W_0FXOP_08_86_L_0) },
9880   },
9881
9882   /* VEX_LEN_0FXOP_08_87 */
9883   {
9884     { VEX_W_TABLE (VEX_W_0FXOP_08_87_L_0) },
9885   },
9886
9887   /* VEX_LEN_0FXOP_08_8E */
9888   {
9889     { VEX_W_TABLE (VEX_W_0FXOP_08_8E_L_0) },
9890   },
9891
9892   /* VEX_LEN_0FXOP_08_8F */
9893   {
9894     { VEX_W_TABLE (VEX_W_0FXOP_08_8F_L_0) },
9895   },
9896
9897   /* VEX_LEN_0FXOP_08_95 */
9898   {
9899     { VEX_W_TABLE (VEX_W_0FXOP_08_95_L_0) },
9900   },
9901
9902   /* VEX_LEN_0FXOP_08_96 */
9903   {
9904     { VEX_W_TABLE (VEX_W_0FXOP_08_96_L_0) },
9905   },
9906
9907   /* VEX_LEN_0FXOP_08_97 */
9908   {
9909     { VEX_W_TABLE (VEX_W_0FXOP_08_97_L_0) },
9910   },
9911
9912   /* VEX_LEN_0FXOP_08_9E */
9913   {
9914     { VEX_W_TABLE (VEX_W_0FXOP_08_9E_L_0) },
9915   },
9916
9917   /* VEX_LEN_0FXOP_08_9F */
9918   {
9919     { VEX_W_TABLE (VEX_W_0FXOP_08_9F_L_0) },
9920   },
9921
9922   /* VEX_LEN_0FXOP_08_A3 */
9923   {
9924     { "vpperm",         { XM, Vex, EXx, XMVexI4 }, 0 },
9925   },
9926
9927   /* VEX_LEN_0FXOP_08_A6 */
9928   {
9929     { VEX_W_TABLE (VEX_W_0FXOP_08_A6_L_0) },
9930   },
9931
9932   /* VEX_LEN_0FXOP_08_B6 */
9933   {
9934     { VEX_W_TABLE (VEX_W_0FXOP_08_B6_L_0) },
9935   },
9936
9937   /* VEX_LEN_0FXOP_08_C0 */
9938   {
9939     { VEX_W_TABLE (VEX_W_0FXOP_08_C0_L_0) },
9940   },
9941
9942   /* VEX_LEN_0FXOP_08_C1 */
9943   {
9944     { VEX_W_TABLE (VEX_W_0FXOP_08_C1_L_0) },
9945   },
9946
9947   /* VEX_LEN_0FXOP_08_C2 */
9948   {
9949     { VEX_W_TABLE (VEX_W_0FXOP_08_C2_L_0) },
9950   },
9951
9952   /* VEX_LEN_0FXOP_08_C3 */
9953   {
9954     { VEX_W_TABLE (VEX_W_0FXOP_08_C3_L_0) },
9955   },
9956
9957   /* VEX_LEN_0FXOP_08_CC */
9958   {
9959     { VEX_W_TABLE (VEX_W_0FXOP_08_CC_L_0) },
9960   },
9961
9962   /* VEX_LEN_0FXOP_08_CD */
9963   {
9964     { VEX_W_TABLE (VEX_W_0FXOP_08_CD_L_0) },
9965   },
9966
9967   /* VEX_LEN_0FXOP_08_CE */
9968   {
9969     { VEX_W_TABLE (VEX_W_0FXOP_08_CE_L_0) },
9970   },
9971
9972   /* VEX_LEN_0FXOP_08_CF */
9973   {
9974     { VEX_W_TABLE (VEX_W_0FXOP_08_CF_L_0) },
9975   },
9976
9977   /* VEX_LEN_0FXOP_08_EC */
9978   {
9979     { VEX_W_TABLE (VEX_W_0FXOP_08_EC_L_0) },
9980   },
9981
9982   /* VEX_LEN_0FXOP_08_ED */
9983   {
9984     { VEX_W_TABLE (VEX_W_0FXOP_08_ED_L_0) },
9985   },
9986
9987   /* VEX_LEN_0FXOP_08_EE */
9988   {
9989     { VEX_W_TABLE (VEX_W_0FXOP_08_EE_L_0) },
9990   },
9991
9992   /* VEX_LEN_0FXOP_08_EF */
9993   {
9994     { VEX_W_TABLE (VEX_W_0FXOP_08_EF_L_0) },
9995   },
9996
9997   /* VEX_LEN_0FXOP_09_01 */
9998   {
9999     { REG_TABLE (REG_0FXOP_09_01_L_0) },
10000   },
10001
10002   /* VEX_LEN_0FXOP_09_02 */
10003   {
10004     { REG_TABLE (REG_0FXOP_09_02_L_0) },
10005   },
10006
10007   /* VEX_LEN_0FXOP_09_12_M_1 */
10008   {
10009     { REG_TABLE (REG_0FXOP_09_12_M_1_L_0) },
10010   },
10011
10012   /* VEX_LEN_0FXOP_09_82_W_0 */
10013   {
10014     { "vfrczss",        { XM, EXd }, 0 },
10015   },
10016
10017   /* VEX_LEN_0FXOP_09_83_W_0 */
10018   {
10019     { "vfrczsd",        { XM, EXq }, 0 },
10020   },
10021
10022   /* VEX_LEN_0FXOP_09_90 */
10023   {
10024     { "vprotb",         { XM, EXx, VexW }, 0 },
10025   },
10026
10027   /* VEX_LEN_0FXOP_09_91 */
10028   {
10029     { "vprotw",         { XM, EXx, VexW }, 0 },
10030   },
10031
10032   /* VEX_LEN_0FXOP_09_92 */
10033   {
10034     { "vprotd",         { XM, EXx, VexW }, 0 },
10035   },
10036
10037   /* VEX_LEN_0FXOP_09_93 */
10038   {
10039     { "vprotq",         { XM, EXx, VexW }, 0 },
10040   },
10041
10042   /* VEX_LEN_0FXOP_09_94 */
10043   {
10044     { "vpshlb",         { XM, EXx, VexW }, 0 },
10045   },
10046
10047   /* VEX_LEN_0FXOP_09_95 */
10048   {
10049     { "vpshlw",         { XM, EXx, VexW }, 0 },
10050   },
10051
10052   /* VEX_LEN_0FXOP_09_96 */
10053   {
10054     { "vpshld",         { XM, EXx, VexW }, 0 },
10055   },
10056
10057   /* VEX_LEN_0FXOP_09_97 */
10058   {
10059     { "vpshlq",         { XM, EXx, VexW }, 0 },
10060   },
10061
10062   /* VEX_LEN_0FXOP_09_98 */
10063   {
10064     { "vpshab",         { XM, EXx, VexW }, 0 },
10065   },
10066
10067   /* VEX_LEN_0FXOP_09_99 */
10068   {
10069     { "vpshaw",         { XM, EXx, VexW }, 0 },
10070   },
10071
10072   /* VEX_LEN_0FXOP_09_9A */
10073   {
10074     { "vpshad",         { XM, EXx, VexW }, 0 },
10075   },
10076
10077   /* VEX_LEN_0FXOP_09_9B */
10078   {
10079     { "vpshaq",         { XM, EXx, VexW }, 0 },
10080   },
10081
10082   /* VEX_LEN_0FXOP_09_C1 */
10083   {
10084     { VEX_W_TABLE (VEX_W_0FXOP_09_C1_L_0) },
10085   },
10086
10087   /* VEX_LEN_0FXOP_09_C2 */
10088   {
10089     { VEX_W_TABLE (VEX_W_0FXOP_09_C2_L_0) },
10090   },
10091
10092   /* VEX_LEN_0FXOP_09_C3 */
10093   {
10094     { VEX_W_TABLE (VEX_W_0FXOP_09_C3_L_0) },
10095   },
10096
10097   /* VEX_LEN_0FXOP_09_C6 */
10098   {
10099     { VEX_W_TABLE (VEX_W_0FXOP_09_C6_L_0) },
10100   },
10101
10102   /* VEX_LEN_0FXOP_09_C7 */
10103   {
10104     { VEX_W_TABLE (VEX_W_0FXOP_09_C7_L_0) },
10105   },
10106
10107   /* VEX_LEN_0FXOP_09_CB */
10108   {
10109     { VEX_W_TABLE (VEX_W_0FXOP_09_CB_L_0) },
10110   },
10111
10112   /* VEX_LEN_0FXOP_09_D1 */
10113   {
10114     { VEX_W_TABLE (VEX_W_0FXOP_09_D1_L_0) },
10115   },
10116
10117   /* VEX_LEN_0FXOP_09_D2 */
10118   {
10119     { VEX_W_TABLE (VEX_W_0FXOP_09_D2_L_0) },
10120   },
10121
10122   /* VEX_LEN_0FXOP_09_D3 */
10123   {
10124     { VEX_W_TABLE (VEX_W_0FXOP_09_D3_L_0) },
10125   },
10126
10127   /* VEX_LEN_0FXOP_09_D6 */
10128   {
10129     { VEX_W_TABLE (VEX_W_0FXOP_09_D6_L_0) },
10130   },
10131
10132   /* VEX_LEN_0FXOP_09_D7 */
10133   {
10134     { VEX_W_TABLE (VEX_W_0FXOP_09_D7_L_0) },
10135   },
10136
10137   /* VEX_LEN_0FXOP_09_DB */
10138   {
10139     { VEX_W_TABLE (VEX_W_0FXOP_09_DB_L_0) },
10140   },
10141
10142   /* VEX_LEN_0FXOP_09_E1 */
10143   {
10144     { VEX_W_TABLE (VEX_W_0FXOP_09_E1_L_0) },
10145   },
10146
10147   /* VEX_LEN_0FXOP_09_E2 */
10148   {
10149     { VEX_W_TABLE (VEX_W_0FXOP_09_E2_L_0) },
10150   },
10151
10152   /* VEX_LEN_0FXOP_09_E3 */
10153   {
10154     { VEX_W_TABLE (VEX_W_0FXOP_09_E3_L_0) },
10155   },
10156
10157   /* VEX_LEN_0FXOP_0A_12 */
10158   {
10159     { REG_TABLE (REG_0FXOP_0A_12_L_0) },
10160   },
10161 };
10162
10163 #include "i386-dis-evex-len.h"
10164
10165 static const struct dis386 vex_w_table[][2] = {
10166   {
10167     /* VEX_W_0F41_P_0_LEN_1 */
10168     { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
10169     { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
10170   },
10171   {
10172     /* VEX_W_0F41_P_2_LEN_1 */
10173     { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
10174     { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
10175   },
10176   {
10177     /* VEX_W_0F42_P_0_LEN_1 */
10178     { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
10179     { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
10180   },
10181   {
10182     /* VEX_W_0F42_P_2_LEN_1 */
10183     { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
10184     { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
10185   },
10186   {
10187     /* VEX_W_0F44_P_0_LEN_0 */
10188     { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
10189     { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
10190   },
10191   {
10192     /* VEX_W_0F44_P_2_LEN_0 */
10193     { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
10194     { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
10195   },
10196   {
10197     /* VEX_W_0F45_P_0_LEN_1 */
10198     { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
10199     { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
10200   },
10201   {
10202     /* VEX_W_0F45_P_2_LEN_1 */
10203     { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
10204     { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
10205   },
10206   {
10207     /* VEX_W_0F46_P_0_LEN_1 */
10208     { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
10209     { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
10210   },
10211   {
10212     /* VEX_W_0F46_P_2_LEN_1 */
10213     { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
10214     { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
10215   },
10216   {
10217     /* VEX_W_0F47_P_0_LEN_1 */
10218     { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
10219     { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
10220   },
10221   {
10222     /* VEX_W_0F47_P_2_LEN_1 */
10223     { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
10224     { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
10225   },
10226   {
10227     /* VEX_W_0F4A_P_0_LEN_1 */
10228     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
10229     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
10230   },
10231   {
10232     /* VEX_W_0F4A_P_2_LEN_1 */
10233     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
10234     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
10235   },
10236   {
10237     /* VEX_W_0F4B_P_0_LEN_1 */
10238     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
10239     { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
10240   },
10241   {
10242     /* VEX_W_0F4B_P_2_LEN_1 */
10243     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
10244   },
10245   {
10246     /* VEX_W_0F90_P_0_LEN_0 */
10247     { "kmovw",          { MaskG, MaskE }, 0 },
10248     { "kmovq",          { MaskG, MaskE }, 0 },
10249   },
10250   {
10251     /* VEX_W_0F90_P_2_LEN_0 */
10252     { "kmovb",          { MaskG, MaskBDE }, 0 },
10253     { "kmovd",          { MaskG, MaskBDE }, 0 },
10254   },
10255   {
10256     /* VEX_W_0F91_P_0_LEN_0 */
10257     { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
10258     { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
10259   },
10260   {
10261     /* VEX_W_0F91_P_2_LEN_0 */
10262     { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
10263     { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
10264   },
10265   {
10266     /* VEX_W_0F92_P_0_LEN_0 */
10267     { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
10268   },
10269   {
10270     /* VEX_W_0F92_P_2_LEN_0 */
10271     { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
10272   },
10273   {
10274     /* VEX_W_0F93_P_0_LEN_0 */
10275     { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
10276   },
10277   {
10278     /* VEX_W_0F93_P_2_LEN_0 */
10279     { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
10280   },
10281   {
10282     /* VEX_W_0F98_P_0_LEN_0 */
10283     { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
10284     { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
10285   },
10286   {
10287     /* VEX_W_0F98_P_2_LEN_0 */
10288     { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
10289     { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
10290   },
10291   {
10292     /* VEX_W_0F99_P_0_LEN_0 */
10293     { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
10294     { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
10295   },
10296   {
10297     /* VEX_W_0F99_P_2_LEN_0 */
10298     { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
10299     { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
10300   },
10301   {
10302     /* VEX_W_0F380C_P_2  */
10303     { "vpermilps",      { XM, Vex, EXx }, 0 },
10304   },
10305   {
10306     /* VEX_W_0F380D_P_2  */
10307     { "vpermilpd",      { XM, Vex, EXx }, 0 },
10308   },
10309   {
10310     /* VEX_W_0F380E_P_2  */
10311     { "vtestps",        { XM, EXx }, 0 },
10312   },
10313   {
10314     /* VEX_W_0F380F_P_2  */
10315     { "vtestpd",        { XM, EXx }, 0 },
10316   },
10317   {
10318     /* VEX_W_0F3813_P_2 */
10319     { "vcvtph2ps", { XM, EXxmmq }, 0 },
10320   },
10321   {
10322     /* VEX_W_0F3816_P_2  */
10323     { "vpermps",        { XM, Vex, EXx }, 0 },
10324   },
10325   {
10326     /* VEX_W_0F3818_P_2 */
10327     { "vbroadcastss",   { XM, EXxmm_md }, 0 },
10328   },
10329   {
10330     /* VEX_W_0F3819_P_2 */
10331     { "vbroadcastsd",   { XM, EXxmm_mq }, 0 },
10332   },
10333   {
10334     /* VEX_W_0F381A_P_2_M_0 */
10335     { "vbroadcastf128", { XM, Mxmm }, 0 },
10336   },
10337   {
10338     /* VEX_W_0F382C_P_2_M_0 */
10339     { "vmaskmovps",     { XM, Vex, Mx }, 0 },
10340   },
10341   {
10342     /* VEX_W_0F382D_P_2_M_0 */
10343     { "vmaskmovpd",     { XM, Vex, Mx }, 0 },
10344   },
10345   {
10346     /* VEX_W_0F382E_P_2_M_0 */
10347     { "vmaskmovps",     { Mx, Vex, XM }, 0 },
10348   },
10349   {
10350     /* VEX_W_0F382F_P_2_M_0 */
10351     { "vmaskmovpd",     { Mx, Vex, XM }, 0 },
10352   },
10353   {
10354     /* VEX_W_0F3836_P_2  */
10355     { "vpermd",         { XM, Vex, EXx }, 0 },
10356   },
10357   {
10358     /* VEX_W_0F3846_P_2 */
10359     { "vpsravd",        { XM, Vex, EXx }, 0 },
10360   },
10361   {
10362     /* VEX_W_0F3849_X86_64_P_0 */
10363     { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_0_W_0) },
10364   },
10365   {
10366     /* VEX_W_0F3849_X86_64_P_2 */
10367     { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_2_W_0) },
10368   },
10369   {
10370     /* VEX_W_0F3849_X86_64_P_3 */
10371     { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_3_W_0) },
10372   },
10373   {
10374     /* VEX_W_0F384B_X86_64_P_1 */
10375     { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_1_W_0) },
10376   },
10377   {
10378     /* VEX_W_0F384B_X86_64_P_2 */
10379     { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_2_W_0) },
10380   },
10381   {
10382     /* VEX_W_0F384B_X86_64_P_3 */
10383     { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_3_W_0) },
10384   },
10385   {
10386     /* VEX_W_0F3858_P_2 */
10387     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
10388   },
10389   {
10390     /* VEX_W_0F3859_P_2 */
10391     { "vpbroadcastq",   { XM, EXxmm_mq }, 0 },
10392   },
10393   {
10394     /* VEX_W_0F385A_P_2_M_0 */
10395     { "vbroadcasti128", { XM, Mxmm }, 0 },
10396   },
10397   {
10398     /* VEX_W_0F385C_X86_64_P_1 */
10399     { MOD_TABLE (MOD_VEX_0F385C_X86_64_P_1_W_0) },
10400   },
10401   {
10402     /* VEX_W_0F385E_X86_64_P_0 */
10403     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_0_W_0) },
10404   },
10405   {
10406     /* VEX_W_0F385E_X86_64_P_1 */
10407     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_1_W_0) },
10408   },
10409   {
10410     /* VEX_W_0F385E_X86_64_P_2 */
10411     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_2_W_0) },
10412   },
10413   {
10414     /* VEX_W_0F385E_X86_64_P_3 */
10415     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_3_W_0) },
10416   },
10417   {
10418     /* VEX_W_0F3878_P_2 */
10419     { "vpbroadcastb",   { XM, EXxmm_mb }, 0 },
10420   },
10421   {
10422     /* VEX_W_0F3879_P_2 */
10423     { "vpbroadcastw",   { XM, EXxmm_mw }, 0 },
10424   },
10425   {
10426     /* VEX_W_0F38CF_P_2 */
10427     { "vgf2p8mulb", { XM, Vex, EXx }, 0 },
10428   },
10429   {
10430     /* VEX_W_0F3A00_P_2 */
10431     { Bad_Opcode },
10432     { "vpermq",         { XM, EXx, Ib }, 0 },
10433   },
10434   {
10435     /* VEX_W_0F3A01_P_2 */
10436     { Bad_Opcode },
10437     { "vpermpd",        { XM, EXx, Ib }, 0 },
10438   },
10439   {
10440     /* VEX_W_0F3A02_P_2 */
10441     { "vpblendd",       { XM, Vex, EXx, Ib }, 0 },
10442   },
10443   {
10444     /* VEX_W_0F3A04_P_2 */
10445     { "vpermilps",      { XM, EXx, Ib }, 0 },
10446   },
10447   {
10448     /* VEX_W_0F3A05_P_2 */
10449     { "vpermilpd",      { XM, EXx, Ib }, 0 },
10450   },
10451   {
10452     /* VEX_W_0F3A06_P_2 */
10453     { "vperm2f128",     { XM, Vex256, EXx, Ib }, 0 },
10454   },
10455   {
10456     /* VEX_W_0F3A18_P_2 */
10457     { "vinsertf128",    { XM, Vex256, EXxmm, Ib }, 0 },
10458   },
10459   {
10460     /* VEX_W_0F3A19_P_2 */
10461     { "vextractf128",   { EXxmm, XM, Ib }, 0 },
10462   },
10463   {
10464     /* VEX_W_0F3A1D_P_2 */
10465     { "vcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, 0 },
10466   },
10467   {
10468     /* VEX_W_0F3A30_P_2_LEN_0 */
10469     { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
10470     { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
10471   },
10472   {
10473     /* VEX_W_0F3A31_P_2_LEN_0 */
10474     { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
10475     { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
10476   },
10477   {
10478     /* VEX_W_0F3A32_P_2_LEN_0 */
10479     { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
10480     { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
10481   },
10482   {
10483     /* VEX_W_0F3A33_P_2_LEN_0 */
10484     { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
10485     { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
10486   },
10487   {
10488     /* VEX_W_0F3A38_P_2 */
10489     { "vinserti128",    { XM, Vex256, EXxmm, Ib }, 0 },
10490   },
10491   {
10492     /* VEX_W_0F3A39_P_2 */
10493     { "vextracti128",   { EXxmm, XM, Ib }, 0 },
10494   },
10495   {
10496     /* VEX_W_0F3A46_P_2 */
10497     { "vperm2i128",     { XM, Vex256, EXx, Ib }, 0 },
10498   },
10499   {
10500     /* VEX_W_0F3A4A_P_2 */
10501     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, 0 },
10502   },
10503   {
10504     /* VEX_W_0F3A4B_P_2 */
10505     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, 0 },
10506   },
10507   {
10508     /* VEX_W_0F3A4C_P_2 */
10509     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, 0 },
10510   },
10511   {
10512     /* VEX_W_0F3ACE_P_2 */
10513     { Bad_Opcode },
10514     { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 },
10515   },
10516   {
10517     /* VEX_W_0F3ACF_P_2 */
10518     { Bad_Opcode },
10519     { "vgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, 0 },
10520   },
10521   /* VEX_W_0FXOP_08_85_L_0 */
10522   {
10523     { "vpmacssww",      { XM, Vex, EXx, XMVexI4 }, 0 },
10524   },
10525   /* VEX_W_0FXOP_08_86_L_0 */
10526   {
10527     { "vpmacsswd",      { XM, Vex, EXx, XMVexI4 }, 0 },
10528   },
10529   /* VEX_W_0FXOP_08_87_L_0 */
10530   {
10531     { "vpmacssdql",     { XM, Vex, EXx, XMVexI4 }, 0 },
10532   },
10533   /* VEX_W_0FXOP_08_8E_L_0 */
10534   {
10535     { "vpmacssdd",      { XM, Vex, EXx, XMVexI4 }, 0 },
10536   },
10537   /* VEX_W_0FXOP_08_8F_L_0 */
10538   {
10539     { "vpmacssdqh",     { XM, Vex, EXx, XMVexI4 }, 0 },
10540   },
10541   /* VEX_W_0FXOP_08_95_L_0 */
10542   {
10543     { "vpmacsww",       { XM, Vex, EXx, XMVexI4 }, 0 },
10544   },
10545   /* VEX_W_0FXOP_08_96_L_0 */
10546   {
10547     { "vpmacswd",       { XM, Vex, EXx, XMVexI4 }, 0 },
10548   },
10549   /* VEX_W_0FXOP_08_97_L_0 */
10550   {
10551     { "vpmacsdql",      { XM, Vex, EXx, XMVexI4 }, 0 },
10552   },
10553   /* VEX_W_0FXOP_08_9E_L_0 */
10554   {
10555     { "vpmacsdd",       { XM, Vex, EXx, XMVexI4 }, 0 },
10556   },
10557   /* VEX_W_0FXOP_08_9F_L_0 */
10558   {
10559     { "vpmacsdqh",      { XM, Vex, EXx, XMVexI4 }, 0 },
10560   },
10561   /* VEX_W_0FXOP_08_A6_L_0 */
10562   {
10563     { "vpmadcsswd",     { XM, Vex, EXx, XMVexI4 }, 0 },
10564   },
10565   /* VEX_W_0FXOP_08_B6_L_0 */
10566   {
10567     { "vpmadcswd",      { XM, Vex, EXx, XMVexI4 }, 0 },
10568   },
10569   /* VEX_W_0FXOP_08_C0_L_0 */
10570   {
10571     { "vprotb",         { XM, EXx, Ib }, 0 },
10572   },
10573   /* VEX_W_0FXOP_08_C1_L_0 */
10574   {
10575     { "vprotw",         { XM, EXx, Ib }, 0 },
10576   },
10577   /* VEX_W_0FXOP_08_C2_L_0 */
10578   {
10579     { "vprotd",         { XM, EXx, Ib }, 0 },
10580   },
10581   /* VEX_W_0FXOP_08_C3_L_0 */
10582   {
10583     { "vprotq",         { XM, EXx, Ib }, 0 },
10584   },
10585   /* VEX_W_0FXOP_08_CC_L_0 */
10586   {
10587      { "vpcomb",        { XM, Vex128, EXx, VPCOM }, 0 },
10588   },
10589   /* VEX_W_0FXOP_08_CD_L_0 */
10590   {
10591      { "vpcomw",        { XM, Vex128, EXx, VPCOM }, 0 },
10592   },
10593   /* VEX_W_0FXOP_08_CE_L_0 */
10594   {
10595      { "vpcomd",        { XM, Vex128, EXx, VPCOM }, 0 },
10596   },
10597   /* VEX_W_0FXOP_08_CF_L_0 */
10598   {
10599      { "vpcomq",        { XM, Vex128, EXx, VPCOM }, 0 },
10600   },
10601   /* VEX_W_0FXOP_08_EC_L_0 */
10602   {
10603      { "vpcomub",       { XM, Vex128, EXx, VPCOM }, 0 },
10604   },
10605   /* VEX_W_0FXOP_08_ED_L_0 */
10606   {
10607      { "vpcomuw",       { XM, Vex128, EXx, VPCOM }, 0 },
10608   },
10609   /* VEX_W_0FXOP_08_EE_L_0 */
10610   {
10611      { "vpcomud",       { XM, Vex128, EXx, VPCOM }, 0 },
10612   },
10613   /* VEX_W_0FXOP_08_EF_L_0 */
10614   {
10615      { "vpcomuq",       { XM, Vex128, EXx, VPCOM }, 0 },
10616   },
10617   /* VEX_W_0FXOP_09_80 */
10618   {
10619     { "vfrczps",        { XM, EXx }, 0 },
10620   },
10621   /* VEX_W_0FXOP_09_81 */
10622   {
10623     { "vfrczpd",        { XM, EXx }, 0 },
10624   },
10625   /* VEX_W_0FXOP_09_82 */
10626   {
10627     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_82_W_0) },
10628   },
10629   /* VEX_W_0FXOP_09_83 */
10630   {
10631     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_83_W_0) },
10632   },
10633   /* VEX_W_0FXOP_09_C1_L_0 */
10634   {
10635     { "vphaddbw",       { XM, EXxmm }, 0 },
10636   },
10637   /* VEX_W_0FXOP_09_C2_L_0 */
10638   {
10639     { "vphaddbd",       { XM, EXxmm }, 0 },
10640   },
10641   /* VEX_W_0FXOP_09_C3_L_0 */
10642   {
10643     { "vphaddbq",       { XM, EXxmm }, 0 },
10644   },
10645   /* VEX_W_0FXOP_09_C6_L_0 */
10646   {
10647     { "vphaddwd",       { XM, EXxmm }, 0 },
10648   },
10649   /* VEX_W_0FXOP_09_C7_L_0 */
10650   {
10651     { "vphaddwq",       { XM, EXxmm }, 0 },
10652   },
10653   /* VEX_W_0FXOP_09_CB_L_0 */
10654   {
10655     { "vphadddq",       { XM, EXxmm }, 0 },
10656   },
10657   /* VEX_W_0FXOP_09_D1_L_0 */
10658   {
10659     { "vphaddubw",      { XM, EXxmm }, 0 },
10660   },
10661   /* VEX_W_0FXOP_09_D2_L_0 */
10662   {
10663     { "vphaddubd",      { XM, EXxmm }, 0 },
10664   },
10665   /* VEX_W_0FXOP_09_D3_L_0 */
10666   {
10667     { "vphaddubq",      { XM, EXxmm }, 0 },
10668   },
10669   /* VEX_W_0FXOP_09_D6_L_0 */
10670   {
10671     { "vphadduwd",      { XM, EXxmm }, 0 },
10672   },
10673   /* VEX_W_0FXOP_09_D7_L_0 */
10674   {
10675     { "vphadduwq",      { XM, EXxmm }, 0 },
10676   },
10677   /* VEX_W_0FXOP_09_DB_L_0 */
10678   {
10679     { "vphaddudq",      { XM, EXxmm }, 0 },
10680   },
10681   /* VEX_W_0FXOP_09_E1_L_0 */
10682   {
10683     { "vphsubbw",       { XM, EXxmm }, 0 },
10684   },
10685   /* VEX_W_0FXOP_09_E2_L_0 */
10686   {
10687     { "vphsubwd",       { XM, EXxmm }, 0 },
10688   },
10689   /* VEX_W_0FXOP_09_E3_L_0 */
10690   {
10691     { "vphsubdq",       { XM, EXxmm }, 0 },
10692   },
10693
10694 #include "i386-dis-evex-w.h"
10695 };
10696
10697 static const struct dis386 mod_table[][2] = {
10698   {
10699     /* MOD_8D */
10700     { "leaS",           { Gv, M }, 0 },
10701   },
10702   {
10703     /* MOD_C6_REG_7 */
10704     { Bad_Opcode },
10705     { RM_TABLE (RM_C6_REG_7) },
10706   },
10707   {
10708     /* MOD_C7_REG_7 */
10709     { Bad_Opcode },
10710     { RM_TABLE (RM_C7_REG_7) },
10711   },
10712   {
10713     /* MOD_FF_REG_3 */
10714     { "{l|}call^", { indirEp }, 0 },
10715   },
10716   {
10717     /* MOD_FF_REG_5 */
10718     { "{l|}jmp^", { indirEp }, 0 },
10719   },
10720   {
10721     /* MOD_0F01_REG_0 */
10722     { X86_64_TABLE (X86_64_0F01_REG_0) },
10723     { RM_TABLE (RM_0F01_REG_0) },
10724   },
10725   {
10726     /* MOD_0F01_REG_1 */
10727     { X86_64_TABLE (X86_64_0F01_REG_1) },
10728     { RM_TABLE (RM_0F01_REG_1) },
10729   },
10730   {
10731     /* MOD_0F01_REG_2 */
10732     { X86_64_TABLE (X86_64_0F01_REG_2) },
10733     { RM_TABLE (RM_0F01_REG_2) },
10734   },
10735   {
10736     /* MOD_0F01_REG_3 */
10737     { X86_64_TABLE (X86_64_0F01_REG_3) },
10738     { RM_TABLE (RM_0F01_REG_3) },
10739   },
10740   {
10741     /* MOD_0F01_REG_5 */
10742     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) },
10743     { RM_TABLE (RM_0F01_REG_5_MOD_3) },
10744   },
10745   {
10746     /* MOD_0F01_REG_7 */
10747     { "invlpg",         { Mb }, 0 },
10748     { RM_TABLE (RM_0F01_REG_7_MOD_3) },
10749   },
10750   {
10751     /* MOD_0F12_PREFIX_0 */
10752     { "movlpX",         { XM, EXq }, 0 },
10753     { "movhlps",        { XM, EXq }, 0 },
10754   },
10755   {
10756     /* MOD_0F12_PREFIX_2 */
10757     { "movlpX", { XM, EXq }, 0 },
10758   },
10759   {
10760     /* MOD_0F13 */
10761     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
10762   },
10763   {
10764     /* MOD_0F16_PREFIX_0 */
10765     { "movhpX",         { XM, EXq }, 0 },
10766     { "movlhps",        { XM, EXq }, 0 },
10767   },
10768   {
10769     /* MOD_0F16_PREFIX_2 */
10770     { "movhpX", { XM, EXq }, 0 },
10771   },
10772   {
10773     /* MOD_0F17 */
10774     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
10775   },
10776   {
10777     /* MOD_0F18_REG_0 */
10778     { "prefetchnta",    { Mb }, 0 },
10779   },
10780   {
10781     /* MOD_0F18_REG_1 */
10782     { "prefetcht0",     { Mb }, 0 },
10783   },
10784   {
10785     /* MOD_0F18_REG_2 */
10786     { "prefetcht1",     { Mb }, 0 },
10787   },
10788   {
10789     /* MOD_0F18_REG_3 */
10790     { "prefetcht2",     { Mb }, 0 },
10791   },
10792   {
10793     /* MOD_0F18_REG_4 */
10794     { "nop/reserved",   { Mb }, 0 },
10795   },
10796   {
10797     /* MOD_0F18_REG_5 */
10798     { "nop/reserved",   { Mb }, 0 },
10799   },
10800   {
10801     /* MOD_0F18_REG_6 */
10802     { "nop/reserved",   { Mb }, 0 },
10803   },
10804   {
10805     /* MOD_0F18_REG_7 */
10806     { "nop/reserved",   { Mb }, 0 },
10807   },
10808   {
10809     /* MOD_0F1A_PREFIX_0 */
10810     { "bndldx",         { Gbnd, Mv_bnd }, 0 },
10811     { "nopQ",           { Ev }, 0 },
10812   },
10813   {
10814     /* MOD_0F1B_PREFIX_0 */
10815     { "bndstx",         { Mv_bnd, Gbnd }, 0 },
10816     { "nopQ",           { Ev }, 0 },
10817   },
10818   {
10819     /* MOD_0F1B_PREFIX_1 */
10820     { "bndmk",          { Gbnd, Mv_bnd }, 0 },
10821     { "nopQ",           { Ev }, 0 },
10822   },
10823   {
10824     /* MOD_0F1C_PREFIX_0 */
10825     { REG_TABLE (REG_0F1C_P_0_MOD_0) },
10826     { "nopQ",           { Ev }, 0 },
10827   },
10828   {
10829     /* MOD_0F1E_PREFIX_1 */
10830     { "nopQ",           { Ev }, 0 },
10831     { REG_TABLE (REG_0F1E_P_1_MOD_3) },
10832   },
10833   {
10834     /* MOD_0F24 */
10835     { Bad_Opcode },
10836     { "movL",           { Rd, Td }, 0 },
10837   },
10838   {
10839     /* MOD_0F26 */
10840     { Bad_Opcode },
10841     { "movL",           { Td, Rd }, 0 },
10842   },
10843   {
10844     /* MOD_0F2B_PREFIX_0 */
10845     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
10846   },
10847   {
10848     /* MOD_0F2B_PREFIX_1 */
10849     {"movntss",         { Md, XM }, PREFIX_OPCODE },
10850   },
10851   {
10852     /* MOD_0F2B_PREFIX_2 */
10853     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
10854   },
10855   {
10856     /* MOD_0F2B_PREFIX_3 */
10857     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
10858   },
10859   {
10860     /* MOD_0F50 */
10861     { Bad_Opcode },
10862     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
10863   },
10864   {
10865     /* MOD_0F71_REG_2 */
10866     { Bad_Opcode },
10867     { "psrlw",          { MS, Ib }, 0 },
10868   },
10869   {
10870     /* MOD_0F71_REG_4 */
10871     { Bad_Opcode },
10872     { "psraw",          { MS, Ib }, 0 },
10873   },
10874   {
10875     /* MOD_0F71_REG_6 */
10876     { Bad_Opcode },
10877     { "psllw",          { MS, Ib }, 0 },
10878   },
10879   {
10880     /* MOD_0F72_REG_2 */
10881     { Bad_Opcode },
10882     { "psrld",          { MS, Ib }, 0 },
10883   },
10884   {
10885     /* MOD_0F72_REG_4 */
10886     { Bad_Opcode },
10887     { "psrad",          { MS, Ib }, 0 },
10888   },
10889   {
10890     /* MOD_0F72_REG_6 */
10891     { Bad_Opcode },
10892     { "pslld",          { MS, Ib }, 0 },
10893   },
10894   {
10895     /* MOD_0F73_REG_2 */
10896     { Bad_Opcode },
10897     { "psrlq",          { MS, Ib }, 0 },
10898   },
10899   {
10900     /* MOD_0F73_REG_3 */
10901     { Bad_Opcode },
10902     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
10903   },
10904   {
10905     /* MOD_0F73_REG_6 */
10906     { Bad_Opcode },
10907     { "psllq",          { MS, Ib }, 0 },
10908   },
10909   {
10910     /* MOD_0F73_REG_7 */
10911     { Bad_Opcode },
10912     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
10913   },
10914   {
10915     /* MOD_0FAE_REG_0 */
10916     { "fxsave",         { FXSAVE }, 0 },
10917     { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) },
10918   },
10919   {
10920     /* MOD_0FAE_REG_1 */
10921     { "fxrstor",        { FXSAVE }, 0 },
10922     { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) },
10923   },
10924   {
10925     /* MOD_0FAE_REG_2 */
10926     { "ldmxcsr",        { Md }, 0 },
10927     { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) },
10928   },
10929   {
10930     /* MOD_0FAE_REG_3 */
10931     { "stmxcsr",        { Md }, 0 },
10932     { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) },
10933   },
10934   {
10935     /* MOD_0FAE_REG_4 */
10936     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) },
10937     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) },
10938   },
10939   {
10940     /* MOD_0FAE_REG_5 */
10941     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_0) },
10942     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) },
10943   },
10944   {
10945     /* MOD_0FAE_REG_6 */
10946     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) },
10947     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) },
10948   },
10949   {
10950     /* MOD_0FAE_REG_7 */
10951     { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) },
10952     { RM_TABLE (RM_0FAE_REG_7_MOD_3) },
10953   },
10954   {
10955     /* MOD_0FB2 */
10956     { "lssS",           { Gv, Mp }, 0 },
10957   },
10958   {
10959     /* MOD_0FB4 */
10960     { "lfsS",           { Gv, Mp }, 0 },
10961   },
10962   {
10963     /* MOD_0FB5 */
10964     { "lgsS",           { Gv, Mp }, 0 },
10965   },
10966   {
10967     /* MOD_0FC3 */
10968     { PREFIX_TABLE (PREFIX_0FC3_MOD_0) },
10969   },
10970   {
10971     /* MOD_0FC7_REG_3 */
10972     { "xrstors",        { FXSAVE }, 0 },
10973   },
10974   {
10975     /* MOD_0FC7_REG_4 */
10976     { "xsavec",         { FXSAVE }, 0 },
10977   },
10978   {
10979     /* MOD_0FC7_REG_5 */
10980     { "xsaves",         { FXSAVE }, 0 },
10981   },
10982   {
10983     /* MOD_0FC7_REG_6 */
10984     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) },
10985     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) }
10986   },
10987   {
10988     /* MOD_0FC7_REG_7 */
10989     { "vmptrst",        { Mq }, 0 },
10990     { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) }
10991   },
10992   {
10993     /* MOD_0FD7 */
10994     { Bad_Opcode },
10995     { "pmovmskb",       { Gdq, MS }, 0 },
10996   },
10997   {
10998     /* MOD_0FE7_PREFIX_2 */
10999     { "movntdq",        { Mx, XM }, 0 },
11000   },
11001   {
11002     /* MOD_0FF0_PREFIX_3 */
11003     { "lddqu",          { XM, M }, 0 },
11004   },
11005   {
11006     /* MOD_0F382A_PREFIX_2 */
11007     { "movntdqa",       { XM, Mx }, 0 },
11008   },
11009   {
11010     /* MOD_VEX_0F3849_X86_64_P_0_W_0 */
11011     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0) },
11012     { REG_TABLE (REG_VEX_0F3849_X86_64_P_0_W_0_M_1) },
11013   },
11014   {
11015     /* MOD_VEX_0F3849_X86_64_P_2_W_0 */
11016     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0) },
11017   },
11018   {
11019     /* MOD_VEX_0F3849_X86_64_P_3_W_0 */
11020     { Bad_Opcode },
11021     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0) },
11022   },
11023   {
11024     /* MOD_VEX_0F384B_X86_64_P_1_W_0 */
11025     { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0) },
11026   },
11027   {
11028     /* MOD_VEX_0F384B_X86_64_P_2_W_0 */
11029     { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0) },
11030   },
11031   {
11032     /* MOD_VEX_0F384B_X86_64_P_3_W_0 */
11033     { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0) },
11034   },
11035   {
11036     /* MOD_VEX_0F385C_X86_64_P_1_W_0 */
11037     { Bad_Opcode },
11038     { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0) },
11039   },
11040   {
11041     /* MOD_VEX_0F385E_X86_64_P_0_W_0 */
11042     { Bad_Opcode },
11043     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0) },
11044   },
11045   {
11046     /* MOD_VEX_0F385E_X86_64_P_1_W_0 */
11047     { Bad_Opcode },
11048     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0) },
11049   },
11050   {
11051     /* MOD_VEX_0F385E_X86_64_P_2_W_0 */
11052     { Bad_Opcode },
11053     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0) },
11054   },
11055   {
11056     /* MOD_VEX_0F385E_X86_64_P_3_W_0 */
11057     { Bad_Opcode },
11058     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0) },
11059   },
11060   {
11061     /* MOD_0F38F5_PREFIX_2 */
11062     { "wrussK",         { M, Gdq }, PREFIX_OPCODE },
11063   },
11064   {
11065     /* MOD_0F38F6_PREFIX_0 */
11066     { "wrssK",          { M, Gdq }, PREFIX_OPCODE },
11067   },
11068   {
11069     /* MOD_0F38F8_PREFIX_1 */
11070     { "enqcmds",        { Gva, M }, PREFIX_OPCODE },
11071   },
11072   {
11073     /* MOD_0F38F8_PREFIX_2 */
11074     { "movdir64b",      { Gva, M }, PREFIX_OPCODE },
11075   },
11076   {
11077     /* MOD_0F38F8_PREFIX_3 */
11078     { "enqcmd",         { Gva, M }, PREFIX_OPCODE },
11079   },
11080   {
11081     /* MOD_0F38F9_PREFIX_0 */
11082     { "movdiri",        { Ev, Gv }, PREFIX_OPCODE },
11083   },
11084   {
11085     /* MOD_62_32BIT */
11086     { "bound{S|}",      { Gv, Ma }, 0 },
11087     { EVEX_TABLE (EVEX_0F) },
11088   },
11089   {
11090     /* MOD_C4_32BIT */
11091     { "lesS",           { Gv, Mp }, 0 },
11092     { VEX_C4_TABLE (VEX_0F) },
11093   },
11094   {
11095     /* MOD_C5_32BIT */
11096     { "ldsS",           { Gv, Mp }, 0 },
11097     { VEX_C5_TABLE (VEX_0F) },
11098   },
11099   {
11100     /* MOD_VEX_0F12_PREFIX_0 */
11101     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
11102     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
11103   },
11104   {
11105     /* MOD_VEX_0F12_PREFIX_2 */
11106     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0) },
11107   },
11108   {
11109     /* MOD_VEX_0F13 */
11110     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
11111   },
11112   {
11113     /* MOD_VEX_0F16_PREFIX_0 */
11114     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
11115     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
11116   },
11117   {
11118     /* MOD_VEX_0F16_PREFIX_2 */
11119     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0) },
11120   },
11121   {
11122     /* MOD_VEX_0F17 */
11123     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
11124   },
11125   {
11126     /* MOD_VEX_0F2B */
11127     { "vmovntpX",       { Mx, XM }, PREFIX_OPCODE },
11128   },
11129   {
11130     /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
11131     { Bad_Opcode },
11132     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
11133   },
11134   {
11135     /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
11136     { Bad_Opcode },
11137     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
11138   },
11139   {
11140     /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
11141     { Bad_Opcode },
11142     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
11143   },
11144   {
11145     /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
11146     { Bad_Opcode },
11147     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
11148   },
11149   {
11150     /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
11151     { Bad_Opcode },
11152     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
11153   },
11154   {
11155     /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
11156     { Bad_Opcode },
11157     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
11158   },
11159   {
11160     /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
11161     { Bad_Opcode },
11162     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
11163   },
11164   {
11165     /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
11166     { Bad_Opcode },
11167     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
11168   },
11169   {
11170     /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
11171     { Bad_Opcode },
11172     { "knotw",          { MaskG, MaskR }, 0 },
11173   },
11174   {
11175     /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
11176     { Bad_Opcode },
11177     { "knotq",          { MaskG, MaskR }, 0 },
11178   },
11179   {
11180     /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
11181     { Bad_Opcode },
11182     { "knotb",          { MaskG, MaskR }, 0 },
11183   },
11184   {
11185     /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
11186     { Bad_Opcode },
11187     { "knotd",          { MaskG, MaskR }, 0 },
11188   },
11189   {
11190     /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
11191     { Bad_Opcode },
11192     { "korw",       { MaskG, MaskVex, MaskR }, 0 },
11193   },
11194   {
11195     /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
11196     { Bad_Opcode },
11197     { "korq",       { MaskG, MaskVex, MaskR }, 0 },
11198   },
11199   {
11200     /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
11201     { Bad_Opcode },
11202     { "korb",       { MaskG, MaskVex, MaskR }, 0 },
11203   },
11204   {
11205     /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
11206     { Bad_Opcode },
11207     { "kord",       { MaskG, MaskVex, MaskR }, 0 },
11208   },
11209  {
11210     /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
11211     { Bad_Opcode },
11212     { "kxnorw",     { MaskG, MaskVex, MaskR }, 0 },
11213   },
11214   {
11215     /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
11216     { Bad_Opcode },
11217     { "kxnorq",     { MaskG, MaskVex, MaskR }, 0 },
11218   },
11219   {
11220     /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
11221     { Bad_Opcode },
11222     { "kxnorb",     { MaskG, MaskVex, MaskR }, 0 },
11223   },
11224   {
11225     /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
11226     { Bad_Opcode },
11227     { "kxnord",     { MaskG, MaskVex, MaskR }, 0 },
11228   },
11229   {
11230     /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
11231     { Bad_Opcode },
11232     { "kxorw",      { MaskG, MaskVex, MaskR }, 0 },
11233   },
11234   {
11235     /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
11236     { Bad_Opcode },
11237     { "kxorq",      { MaskG, MaskVex, MaskR }, 0 },
11238   },
11239   {
11240     /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
11241     { Bad_Opcode },
11242     { "kxorb",      { MaskG, MaskVex, MaskR }, 0 },
11243   },
11244   {
11245     /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
11246     { Bad_Opcode },
11247     { "kxord",      { MaskG, MaskVex, MaskR }, 0 },
11248   },
11249   {
11250     /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
11251     { Bad_Opcode },
11252     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
11253   },
11254   {
11255     /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
11256     { Bad_Opcode },
11257     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
11258   },
11259   {
11260     /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
11261     { Bad_Opcode },
11262     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
11263   },
11264   {
11265     /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
11266     { Bad_Opcode },
11267     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
11268   },
11269   {
11270     /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
11271     { Bad_Opcode },
11272     { "kunpckwd",   { MaskG, MaskVex, MaskR }, 0 },
11273   },
11274   {
11275     /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
11276     { Bad_Opcode },
11277     { "kunpckdq",   { MaskG, MaskVex, MaskR }, 0 },
11278   },
11279   {
11280     /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
11281     { Bad_Opcode },
11282     { "kunpckbw",   { MaskG, MaskVex, MaskR }, 0 },
11283   },
11284   {
11285     /* MOD_VEX_0F50 */
11286     { Bad_Opcode },
11287     { "vmovmskpX",      { Gdq, XS }, PREFIX_OPCODE },
11288   },
11289   {
11290     /* MOD_VEX_0F71_REG_2 */
11291     { Bad_Opcode },
11292     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
11293   },
11294   {
11295     /* MOD_VEX_0F71_REG_4 */
11296     { Bad_Opcode },
11297     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
11298   },
11299   {
11300     /* MOD_VEX_0F71_REG_6 */
11301     { Bad_Opcode },
11302     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
11303   },
11304   {
11305     /* MOD_VEX_0F72_REG_2 */
11306     { Bad_Opcode },
11307     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
11308   },
11309   {
11310     /* MOD_VEX_0F72_REG_4 */
11311     { Bad_Opcode },
11312     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
11313   },
11314   {
11315     /* MOD_VEX_0F72_REG_6 */
11316     { Bad_Opcode },
11317     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
11318   },
11319   {
11320     /* MOD_VEX_0F73_REG_2 */
11321     { Bad_Opcode },
11322     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
11323   },
11324   {
11325     /* MOD_VEX_0F73_REG_3 */
11326     { Bad_Opcode },
11327     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
11328   },
11329   {
11330     /* MOD_VEX_0F73_REG_6 */
11331     { Bad_Opcode },
11332     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
11333   },
11334   {
11335     /* MOD_VEX_0F73_REG_7 */
11336     { Bad_Opcode },
11337     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
11338   },
11339   {
11340     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
11341     { "kmovw",          { Ew, MaskG }, 0 },
11342     { Bad_Opcode },
11343   },
11344   {
11345     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
11346     { "kmovq",          { Eq, MaskG }, 0 },
11347     { Bad_Opcode },
11348   },
11349   {
11350     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
11351     { "kmovb",          { Eb, MaskG }, 0 },
11352     { Bad_Opcode },
11353   },
11354   {
11355     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
11356     { "kmovd",          { Ed, MaskG }, 0 },
11357     { Bad_Opcode },
11358   },
11359   {
11360     /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
11361     { Bad_Opcode },
11362     { "kmovw",          { MaskG, Rdq }, 0 },
11363   },
11364   {
11365     /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
11366     { Bad_Opcode },
11367     { "kmovb",          { MaskG, Rdq }, 0 },
11368   },
11369   {
11370     /* MOD_VEX_0F92_P_3_LEN_0 */
11371     { Bad_Opcode },
11372     { "kmovK",          { MaskG, Rdq }, 0 },
11373   },
11374   {
11375     /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
11376     { Bad_Opcode },
11377     { "kmovw",          { Gdq, MaskR }, 0 },
11378   },
11379   {
11380     /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
11381     { Bad_Opcode },
11382     { "kmovb",          { Gdq, MaskR }, 0 },
11383   },
11384   {
11385     /* MOD_VEX_0F93_P_3_LEN_0 */
11386     { Bad_Opcode },
11387     { "kmovK",          { Gdq, MaskR }, 0 },
11388   },
11389   {
11390     /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
11391     { Bad_Opcode },
11392     { "kortestw", { MaskG, MaskR }, 0 },
11393   },
11394   {
11395     /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
11396     { Bad_Opcode },
11397     { "kortestq", { MaskG, MaskR }, 0 },
11398   },
11399   {
11400     /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
11401     { Bad_Opcode },
11402     { "kortestb", { MaskG, MaskR }, 0 },
11403   },
11404   {
11405     /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
11406     { Bad_Opcode },
11407     { "kortestd", { MaskG, MaskR }, 0 },
11408   },
11409   {
11410     /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
11411     { Bad_Opcode },
11412     { "ktestw", { MaskG, MaskR }, 0 },
11413   },
11414   {
11415     /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
11416     { Bad_Opcode },
11417     { "ktestq", { MaskG, MaskR }, 0 },
11418   },
11419   {
11420     /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
11421     { Bad_Opcode },
11422     { "ktestb", { MaskG, MaskR }, 0 },
11423   },
11424   {
11425     /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
11426     { Bad_Opcode },
11427     { "ktestd", { MaskG, MaskR }, 0 },
11428   },
11429   {
11430     /* MOD_VEX_0FAE_REG_2 */
11431     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
11432   },
11433   {
11434     /* MOD_VEX_0FAE_REG_3 */
11435     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
11436   },
11437   {
11438     /* MOD_VEX_0FD7_PREFIX_2 */
11439     { Bad_Opcode },
11440     { "vpmovmskb",      { Gdq, XS }, 0 },
11441   },
11442   {
11443     /* MOD_VEX_0FE7_PREFIX_2 */
11444     { "vmovntdq",       { Mx, XM }, 0 },
11445   },
11446   {
11447     /* MOD_VEX_0FF0_PREFIX_3 */
11448     { "vlddqu",         { XM, M }, 0 },
11449   },
11450   {
11451     /* MOD_VEX_0F381A_PREFIX_2 */
11452     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
11453   },
11454   {
11455     /* MOD_VEX_0F382A_PREFIX_2 */
11456     { "vmovntdqa",      { XM, Mx }, 0 },
11457   },
11458   {
11459     /* MOD_VEX_0F382C_PREFIX_2 */
11460     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
11461   },
11462   {
11463     /* MOD_VEX_0F382D_PREFIX_2 */
11464     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
11465   },
11466   {
11467     /* MOD_VEX_0F382E_PREFIX_2 */
11468     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
11469   },
11470   {
11471     /* MOD_VEX_0F382F_PREFIX_2 */
11472     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
11473   },
11474   {
11475     /* MOD_VEX_0F385A_PREFIX_2 */
11476     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
11477   },
11478   {
11479     /* MOD_VEX_0F388C_PREFIX_2 */
11480     { "vpmaskmov%LW",   { XM, Vex, Mx }, 0 },
11481   },
11482   {
11483     /* MOD_VEX_0F388E_PREFIX_2 */
11484     { "vpmaskmov%LW",   { Mx, Vex, XM }, 0 },
11485   },
11486   {
11487     /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
11488     { Bad_Opcode },
11489     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
11490   },
11491   {
11492     /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
11493     { Bad_Opcode },
11494     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
11495   },
11496   {
11497     /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
11498     { Bad_Opcode },
11499     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
11500   },
11501   {
11502     /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
11503     { Bad_Opcode },
11504     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
11505   },
11506   {
11507     /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
11508     { Bad_Opcode },
11509     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
11510   },
11511   {
11512     /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
11513     { Bad_Opcode },
11514     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
11515   },
11516   {
11517     /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
11518     { Bad_Opcode },
11519     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
11520   },
11521   {
11522     /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
11523     { Bad_Opcode },
11524     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
11525   },
11526   {
11527     /* MOD_VEX_0FXOP_09_12 */
11528     { Bad_Opcode },
11529     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_12_M_1) },
11530   },
11531
11532 #include "i386-dis-evex-mod.h"
11533 };
11534
11535 static const struct dis386 rm_table[][8] = {
11536   {
11537     /* RM_C6_REG_7 */
11538     { "xabort",         { Skip_MODRM, Ib }, 0 },
11539   },
11540   {
11541     /* RM_C7_REG_7 */
11542     { "xbeginT",        { Skip_MODRM, Jdqw }, 0 },
11543   },
11544   {
11545     /* RM_0F01_REG_0 */
11546     { "enclv",          { Skip_MODRM }, 0 },
11547     { "vmcall",         { Skip_MODRM }, 0 },
11548     { "vmlaunch",       { Skip_MODRM }, 0 },
11549     { "vmresume",       { Skip_MODRM }, 0 },
11550     { "vmxoff",         { Skip_MODRM }, 0 },
11551     { "pconfig",        { Skip_MODRM }, 0 },
11552   },
11553   {
11554     /* RM_0F01_REG_1 */
11555     { "monitor",        { { OP_Monitor, 0 } }, 0 },
11556     { "mwait",          { { OP_Mwait, 0 } }, 0 },
11557     { "clac",           { Skip_MODRM }, 0 },
11558     { "stac",           { Skip_MODRM }, 0 },
11559     { Bad_Opcode },
11560     { Bad_Opcode },
11561     { Bad_Opcode },
11562     { "encls",          { Skip_MODRM }, 0 },
11563   },
11564   {
11565     /* RM_0F01_REG_2 */
11566     { "xgetbv",         { Skip_MODRM }, 0 },
11567     { "xsetbv",         { Skip_MODRM }, 0 },
11568     { Bad_Opcode },
11569     { Bad_Opcode },
11570     { "vmfunc",         { Skip_MODRM }, 0 },
11571     { "xend",           { Skip_MODRM }, 0 },
11572     { "xtest",          { Skip_MODRM }, 0 },
11573     { "enclu",          { Skip_MODRM }, 0 },
11574   },
11575   {
11576     /* RM_0F01_REG_3 */
11577     { "vmrun",          { Skip_MODRM }, 0 },
11578     { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) },
11579     { "vmload",         { Skip_MODRM }, 0 },
11580     { "vmsave",         { Skip_MODRM }, 0 },
11581     { "stgi",           { Skip_MODRM }, 0 },
11582     { "clgi",           { Skip_MODRM }, 0 },
11583     { "skinit",         { Skip_MODRM }, 0 },
11584     { "invlpga",        { Skip_MODRM }, 0 },
11585   },
11586   {
11587     /* RM_0F01_REG_5_MOD_3 */
11588     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) },
11589     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) },
11590     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) },
11591     { Bad_Opcode },
11592     { Bad_Opcode },
11593     { Bad_Opcode },
11594     { "rdpkru",         { Skip_MODRM }, 0 },
11595     { "wrpkru",         { Skip_MODRM }, 0 },
11596   },
11597   {
11598     /* RM_0F01_REG_7_MOD_3 */
11599     { "swapgs",         { Skip_MODRM }, 0  },
11600     { "rdtscp",         { Skip_MODRM }, 0  },
11601     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) },
11602     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_3) },
11603     { "clzero",         { Skip_MODRM }, 0  },
11604     { "rdpru",          { Skip_MODRM }, 0  },
11605   },
11606   {
11607     /* RM_0F1E_P_1_MOD_3_REG_7 */
11608     { "nopQ",           { Ev }, 0 },
11609     { "nopQ",           { Ev }, 0 },
11610     { "endbr64",        { Skip_MODRM },  PREFIX_OPCODE },
11611     { "endbr32",        { Skip_MODRM },  PREFIX_OPCODE },
11612     { "nopQ",           { Ev }, 0 },
11613     { "nopQ",           { Ev }, 0 },
11614     { "nopQ",           { Ev }, 0 },
11615     { "nopQ",           { Ev }, 0 },
11616   },
11617   {
11618     /* RM_0FAE_REG_6_MOD_3 */
11619     { "mfence",         { Skip_MODRM }, 0 },
11620   },
11621   {
11622     /* RM_0FAE_REG_7_MOD_3 */
11623     { "sfence",         { Skip_MODRM }, 0 },
11624
11625   },
11626   {
11627     /* RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0 */
11628     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0) },
11629   },
11630 };
11631
11632 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
11633
11634 /* We use the high bit to indicate different name for the same
11635    prefix.  */
11636 #define REP_PREFIX      (0xf3 | 0x100)
11637 #define XACQUIRE_PREFIX (0xf2 | 0x200)
11638 #define XRELEASE_PREFIX (0xf3 | 0x400)
11639 #define BND_PREFIX      (0xf2 | 0x400)
11640 #define NOTRACK_PREFIX  (0x3e | 0x100)
11641
11642 /* Remember if the current op is a jump instruction.  */
11643 static bfd_boolean op_is_jump = FALSE;
11644
11645 static int
11646 ckprefix (void)
11647 {
11648   int newrex, i, length;
11649   rex = 0;
11650   prefixes = 0;
11651   used_prefixes = 0;
11652   rex_used = 0;
11653   last_lock_prefix = -1;
11654   last_repz_prefix = -1;
11655   last_repnz_prefix = -1;
11656   last_data_prefix = -1;
11657   last_addr_prefix = -1;
11658   last_rex_prefix = -1;
11659   last_seg_prefix = -1;
11660   fwait_prefix = -1;
11661   active_seg_prefix = 0;
11662   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11663     all_prefixes[i] = 0;
11664   i = 0;
11665   length = 0;
11666   /* The maximum instruction length is 15bytes.  */
11667   while (length < MAX_CODE_LENGTH - 1)
11668     {
11669       FETCH_DATA (the_info, codep + 1);
11670       newrex = 0;
11671       switch (*codep)
11672         {
11673         /* REX prefixes family.  */
11674         case 0x40:
11675         case 0x41:
11676         case 0x42:
11677         case 0x43:
11678         case 0x44:
11679         case 0x45:
11680         case 0x46:
11681         case 0x47:
11682         case 0x48:
11683         case 0x49:
11684         case 0x4a:
11685         case 0x4b:
11686         case 0x4c:
11687         case 0x4d:
11688         case 0x4e:
11689         case 0x4f:
11690           if (address_mode == mode_64bit)
11691             newrex = *codep;
11692           else
11693             return 1;
11694           last_rex_prefix = i;
11695           break;
11696         case 0xf3:
11697           prefixes |= PREFIX_REPZ;
11698           last_repz_prefix = i;
11699           break;
11700         case 0xf2:
11701           prefixes |= PREFIX_REPNZ;
11702           last_repnz_prefix = i;
11703           break;
11704         case 0xf0:
11705           prefixes |= PREFIX_LOCK;
11706           last_lock_prefix = i;
11707           break;
11708         case 0x2e:
11709           prefixes |= PREFIX_CS;
11710           last_seg_prefix = i;
11711           active_seg_prefix = PREFIX_CS;
11712           break;
11713         case 0x36:
11714           prefixes |= PREFIX_SS;
11715           last_seg_prefix = i;
11716           active_seg_prefix = PREFIX_SS;
11717           break;
11718         case 0x3e:
11719           prefixes |= PREFIX_DS;
11720           last_seg_prefix = i;
11721           active_seg_prefix = PREFIX_DS;
11722           break;
11723         case 0x26:
11724           prefixes |= PREFIX_ES;
11725           last_seg_prefix = i;
11726           active_seg_prefix = PREFIX_ES;
11727           break;
11728         case 0x64:
11729           prefixes |= PREFIX_FS;
11730           last_seg_prefix = i;
11731           active_seg_prefix = PREFIX_FS;
11732           break;
11733         case 0x65:
11734           prefixes |= PREFIX_GS;
11735           last_seg_prefix = i;
11736           active_seg_prefix = PREFIX_GS;
11737           break;
11738         case 0x66:
11739           prefixes |= PREFIX_DATA;
11740           last_data_prefix = i;
11741           break;
11742         case 0x67:
11743           prefixes |= PREFIX_ADDR;
11744           last_addr_prefix = i;
11745           break;
11746         case FWAIT_OPCODE:
11747           /* fwait is really an instruction.  If there are prefixes
11748              before the fwait, they belong to the fwait, *not* to the
11749              following instruction.  */
11750           fwait_prefix = i;
11751           if (prefixes || rex)
11752             {
11753               prefixes |= PREFIX_FWAIT;
11754               codep++;
11755               /* This ensures that the previous REX prefixes are noticed
11756                  as unused prefixes, as in the return case below.  */
11757               rex_used = rex;
11758               return 1;
11759             }
11760           prefixes = PREFIX_FWAIT;
11761           break;
11762         default:
11763           return 1;
11764         }
11765       /* Rex is ignored when followed by another prefix.  */
11766       if (rex)
11767         {
11768           rex_used = rex;
11769           return 1;
11770         }
11771       if (*codep != FWAIT_OPCODE)
11772         all_prefixes[i++] = *codep;
11773       rex = newrex;
11774       codep++;
11775       length++;
11776     }
11777   return 0;
11778 }
11779
11780 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11781    prefix byte.  */
11782
11783 static const char *
11784 prefix_name (int pref, int sizeflag)
11785 {
11786   static const char *rexes [16] =
11787     {
11788       "rex",            /* 0x40 */
11789       "rex.B",          /* 0x41 */
11790       "rex.X",          /* 0x42 */
11791       "rex.XB",         /* 0x43 */
11792       "rex.R",          /* 0x44 */
11793       "rex.RB",         /* 0x45 */
11794       "rex.RX",         /* 0x46 */
11795       "rex.RXB",        /* 0x47 */
11796       "rex.W",          /* 0x48 */
11797       "rex.WB",         /* 0x49 */
11798       "rex.WX",         /* 0x4a */
11799       "rex.WXB",        /* 0x4b */
11800       "rex.WR",         /* 0x4c */
11801       "rex.WRB",        /* 0x4d */
11802       "rex.WRX",        /* 0x4e */
11803       "rex.WRXB",       /* 0x4f */
11804     };
11805
11806   switch (pref)
11807     {
11808     /* REX prefixes family.  */
11809     case 0x40:
11810     case 0x41:
11811     case 0x42:
11812     case 0x43:
11813     case 0x44:
11814     case 0x45:
11815     case 0x46:
11816     case 0x47:
11817     case 0x48:
11818     case 0x49:
11819     case 0x4a:
11820     case 0x4b:
11821     case 0x4c:
11822     case 0x4d:
11823     case 0x4e:
11824     case 0x4f:
11825       return rexes [pref - 0x40];
11826     case 0xf3:
11827       return "repz";
11828     case 0xf2:
11829       return "repnz";
11830     case 0xf0:
11831       return "lock";
11832     case 0x2e:
11833       return "cs";
11834     case 0x36:
11835       return "ss";
11836     case 0x3e:
11837       return "ds";
11838     case 0x26:
11839       return "es";
11840     case 0x64:
11841       return "fs";
11842     case 0x65:
11843       return "gs";
11844     case 0x66:
11845       return (sizeflag & DFLAG) ? "data16" : "data32";
11846     case 0x67:
11847       if (address_mode == mode_64bit)
11848         return (sizeflag & AFLAG) ? "addr32" : "addr64";
11849       else
11850         return (sizeflag & AFLAG) ? "addr16" : "addr32";
11851     case FWAIT_OPCODE:
11852       return "fwait";
11853     case REP_PREFIX:
11854       return "rep";
11855     case XACQUIRE_PREFIX:
11856       return "xacquire";
11857     case XRELEASE_PREFIX:
11858       return "xrelease";
11859     case BND_PREFIX:
11860       return "bnd";
11861     case NOTRACK_PREFIX:
11862       return "notrack";
11863     default:
11864       return NULL;
11865     }
11866 }
11867
11868 static char op_out[MAX_OPERANDS][100];
11869 static int op_ad, op_index[MAX_OPERANDS];
11870 static int two_source_ops;
11871 static bfd_vma op_address[MAX_OPERANDS];
11872 static bfd_vma op_riprel[MAX_OPERANDS];
11873 static bfd_vma start_pc;
11874
11875 /*
11876  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11877  *   (see topic "Redundant prefixes" in the "Differences from 8086"
11878  *   section of the "Virtual 8086 Mode" chapter.)
11879  * 'pc' should be the address of this instruction, it will
11880  *   be used to print the target address if this is a relative jump or call
11881  * The function returns the length of this instruction in bytes.
11882  */
11883
11884 static char intel_syntax;
11885 static char intel_mnemonic = !SYSV386_COMPAT;
11886 static char open_char;
11887 static char close_char;
11888 static char separator_char;
11889 static char scale_char;
11890
11891 enum x86_64_isa
11892 {
11893   amd64 = 1,
11894   intel64
11895 };
11896
11897 static enum x86_64_isa isa64;
11898
11899 /* Here for backwards compatibility.  When gdb stops using
11900    print_insn_i386_att and print_insn_i386_intel these functions can
11901    disappear, and print_insn_i386 be merged into print_insn.  */
11902 int
11903 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
11904 {
11905   intel_syntax = 0;
11906
11907   return print_insn (pc, info);
11908 }
11909
11910 int
11911 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
11912 {
11913   intel_syntax = 1;
11914
11915   return print_insn (pc, info);
11916 }
11917
11918 int
11919 print_insn_i386 (bfd_vma pc, disassemble_info *info)
11920 {
11921   intel_syntax = -1;
11922
11923   return print_insn (pc, info);
11924 }
11925
11926 void
11927 print_i386_disassembler_options (FILE *stream)
11928 {
11929   fprintf (stream, _("\n\
11930 The following i386/x86-64 specific disassembler options are supported for use\n\
11931 with the -M switch (multiple options should be separated by commas):\n"));
11932
11933   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
11934   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
11935   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
11936   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
11937   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
11938   fprintf (stream, _("  att-mnemonic\n"
11939                      "              Display instruction in AT&T mnemonic\n"));
11940   fprintf (stream, _("  intel-mnemonic\n"
11941                      "              Display instruction in Intel mnemonic\n"));
11942   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
11943   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
11944   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
11945   fprintf (stream, _("  data32      Assume 32bit data size\n"));
11946   fprintf (stream, _("  data16      Assume 16bit data size\n"));
11947   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
11948   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
11949   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
11950 }
11951
11952 /* Bad opcode.  */
11953 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
11954
11955 /* Get a pointer to struct dis386 with a valid name.  */
11956
11957 static const struct dis386 *
11958 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
11959 {
11960   int vindex, vex_table_index;
11961
11962   if (dp->name != NULL)
11963     return dp;
11964
11965   switch (dp->op[0].bytemode)
11966     {
11967     case USE_REG_TABLE:
11968       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
11969       break;
11970
11971     case USE_MOD_TABLE:
11972       vindex = modrm.mod == 0x3 ? 1 : 0;
11973       dp = &mod_table[dp->op[1].bytemode][vindex];
11974       break;
11975
11976     case USE_RM_TABLE:
11977       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
11978       break;
11979
11980     case USE_PREFIX_TABLE:
11981       if (need_vex)
11982         {
11983           /* The prefix in VEX is implicit.  */
11984           switch (vex.prefix)
11985             {
11986             case 0:
11987               vindex = 0;
11988               break;
11989             case REPE_PREFIX_OPCODE:
11990               vindex = 1;
11991               break;
11992             case DATA_PREFIX_OPCODE:
11993               vindex = 2;
11994               break;
11995             case REPNE_PREFIX_OPCODE:
11996               vindex = 3;
11997               break;
11998             default:
11999               abort ();
12000               break;
12001             }
12002         }
12003       else
12004         {
12005           int last_prefix = -1;
12006           int prefix = 0;
12007           vindex = 0;
12008           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12009              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12010              last one wins.  */
12011           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12012             {
12013               if (last_repz_prefix > last_repnz_prefix)
12014                 {
12015                   vindex = 1;
12016                   prefix = PREFIX_REPZ;
12017                   last_prefix = last_repz_prefix;
12018                 }
12019               else
12020                 {
12021                   vindex = 3;
12022                   prefix = PREFIX_REPNZ;
12023                   last_prefix = last_repnz_prefix;
12024                 }
12025
12026               /* Check if prefix should be ignored.  */
12027               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
12028                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
12029                    & prefix) != 0)
12030                 vindex = 0;
12031             }
12032
12033           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
12034             {
12035               vindex = 2;
12036               prefix = PREFIX_DATA;
12037               last_prefix = last_data_prefix;
12038             }
12039
12040           if (vindex != 0)
12041             {
12042               used_prefixes |= prefix;
12043               all_prefixes[last_prefix] = 0;
12044             }
12045         }
12046       dp = &prefix_table[dp->op[1].bytemode][vindex];
12047       break;
12048
12049     case USE_X86_64_TABLE:
12050       vindex = address_mode == mode_64bit ? 1 : 0;
12051       dp = &x86_64_table[dp->op[1].bytemode][vindex];
12052       break;
12053
12054     case USE_3BYTE_TABLE:
12055       FETCH_DATA (info, codep + 2);
12056       vindex = *codep++;
12057       dp = &three_byte_table[dp->op[1].bytemode][vindex];
12058       end_codep = codep;
12059       modrm.mod = (*codep >> 6) & 3;
12060       modrm.reg = (*codep >> 3) & 7;
12061       modrm.rm = *codep & 7;
12062       break;
12063
12064     case USE_VEX_LEN_TABLE:
12065       if (!need_vex)
12066         abort ();
12067
12068       switch (vex.length)
12069         {
12070         case 128:
12071           vindex = 0;
12072           break;
12073         case 256:
12074           vindex = 1;
12075           break;
12076         default:
12077           abort ();
12078           break;
12079         }
12080
12081       dp = &vex_len_table[dp->op[1].bytemode][vindex];
12082       break;
12083
12084     case USE_EVEX_LEN_TABLE:
12085       if (!vex.evex)
12086         abort ();
12087
12088       switch (vex.length)
12089         {
12090         case 128:
12091           vindex = 0;
12092           break;
12093         case 256:
12094           vindex = 1;
12095           break;
12096         case 512:
12097           vindex = 2;
12098           break;
12099         default:
12100           abort ();
12101           break;
12102         }
12103
12104       dp = &evex_len_table[dp->op[1].bytemode][vindex];
12105       break;
12106
12107     case USE_XOP_8F_TABLE:
12108       FETCH_DATA (info, codep + 3);
12109       rex = ~(*codep >> 5) & 0x7;
12110
12111       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
12112       switch ((*codep & 0x1f))
12113         {
12114         default:
12115           dp = &bad_opcode;
12116           return dp;
12117         case 0x8:
12118           vex_table_index = XOP_08;
12119           break;
12120         case 0x9:
12121           vex_table_index = XOP_09;
12122           break;
12123         case 0xa:
12124           vex_table_index = XOP_0A;
12125           break;
12126         }
12127       codep++;
12128       vex.w = *codep & 0x80;
12129       if (vex.w && address_mode == mode_64bit)
12130         rex |= REX_W;
12131
12132       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12133       if (address_mode != mode_64bit)
12134         {
12135           /* In 16/32-bit mode REX_B is silently ignored.  */
12136           rex &= ~REX_B;
12137         }
12138
12139       vex.length = (*codep & 0x4) ? 256 : 128;
12140       switch ((*codep & 0x3))
12141         {
12142         case 0:
12143           break;
12144         case 1:
12145           vex.prefix = DATA_PREFIX_OPCODE;
12146           break;
12147         case 2:
12148           vex.prefix = REPE_PREFIX_OPCODE;
12149           break;
12150         case 3:
12151           vex.prefix = REPNE_PREFIX_OPCODE;
12152           break;
12153         }
12154       need_vex = 1;
12155       need_vex_reg = 1;
12156       codep++;
12157       vindex = *codep++;
12158       dp = &xop_table[vex_table_index][vindex];
12159
12160       end_codep = codep;
12161       FETCH_DATA (info, codep + 1);
12162       modrm.mod = (*codep >> 6) & 3;
12163       modrm.reg = (*codep >> 3) & 7;
12164       modrm.rm = *codep & 7;
12165
12166       /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid
12167          having to decode the bits for every otherwise valid encoding.  */
12168       if (vex.prefix)
12169         return &bad_opcode;
12170       break;
12171
12172     case USE_VEX_C4_TABLE:
12173       /* VEX prefix.  */
12174       FETCH_DATA (info, codep + 3);
12175       rex = ~(*codep >> 5) & 0x7;
12176       switch ((*codep & 0x1f))
12177         {
12178         default:
12179           dp = &bad_opcode;
12180           return dp;
12181         case 0x1:
12182           vex_table_index = VEX_0F;
12183           break;
12184         case 0x2:
12185           vex_table_index = VEX_0F38;
12186           break;
12187         case 0x3:
12188           vex_table_index = VEX_0F3A;
12189           break;
12190         }
12191       codep++;
12192       vex.w = *codep & 0x80;
12193       if (address_mode == mode_64bit)
12194         {
12195           if (vex.w)
12196             rex |= REX_W;
12197         }
12198       else
12199         {
12200           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
12201              is ignored, other REX bits are 0 and the highest bit in
12202              VEX.vvvv is also ignored (but we mustn't clear it here).  */
12203           rex = 0;
12204         }
12205       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12206       vex.length = (*codep & 0x4) ? 256 : 128;
12207       switch ((*codep & 0x3))
12208         {
12209         case 0:
12210           break;
12211         case 1:
12212           vex.prefix = DATA_PREFIX_OPCODE;
12213           break;
12214         case 2:
12215           vex.prefix = REPE_PREFIX_OPCODE;
12216           break;
12217         case 3:
12218           vex.prefix = REPNE_PREFIX_OPCODE;
12219           break;
12220         }
12221       need_vex = 1;
12222       need_vex_reg = 1;
12223       codep++;
12224       vindex = *codep++;
12225       dp = &vex_table[vex_table_index][vindex];
12226       end_codep = codep;
12227       /* There is no MODRM byte for VEX0F 77.  */
12228       if (vex_table_index != VEX_0F || vindex != 0x77)
12229         {
12230           FETCH_DATA (info, codep + 1);
12231           modrm.mod = (*codep >> 6) & 3;
12232           modrm.reg = (*codep >> 3) & 7;
12233           modrm.rm = *codep & 7;
12234         }
12235       break;
12236
12237     case USE_VEX_C5_TABLE:
12238       /* VEX prefix.  */
12239       FETCH_DATA (info, codep + 2);
12240       rex = (*codep & 0x80) ? 0 : REX_R;
12241
12242       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
12243          VEX.vvvv is 1.  */
12244       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12245       vex.length = (*codep & 0x4) ? 256 : 128;
12246       switch ((*codep & 0x3))
12247         {
12248         case 0:
12249           break;
12250         case 1:
12251           vex.prefix = DATA_PREFIX_OPCODE;
12252           break;
12253         case 2:
12254           vex.prefix = REPE_PREFIX_OPCODE;
12255           break;
12256         case 3:
12257           vex.prefix = REPNE_PREFIX_OPCODE;
12258           break;
12259         }
12260       need_vex = 1;
12261       need_vex_reg = 1;
12262       codep++;
12263       vindex = *codep++;
12264       dp = &vex_table[dp->op[1].bytemode][vindex];
12265       end_codep = codep;
12266       /* There is no MODRM byte for VEX 77.  */
12267       if (vindex != 0x77)
12268         {
12269           FETCH_DATA (info, codep + 1);
12270           modrm.mod = (*codep >> 6) & 3;
12271           modrm.reg = (*codep >> 3) & 7;
12272           modrm.rm = *codep & 7;
12273         }
12274       break;
12275
12276     case USE_VEX_W_TABLE:
12277       if (!need_vex)
12278         abort ();
12279
12280       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
12281       break;
12282
12283     case USE_EVEX_TABLE:
12284       two_source_ops = 0;
12285       /* EVEX prefix.  */
12286       vex.evex = 1;
12287       FETCH_DATA (info, codep + 4);
12288       /* The first byte after 0x62.  */
12289       rex = ~(*codep >> 5) & 0x7;
12290       vex.r = *codep & 0x10;
12291       switch ((*codep & 0xf))
12292         {
12293         default:
12294           return &bad_opcode;
12295         case 0x1:
12296           vex_table_index = EVEX_0F;
12297           break;
12298         case 0x2:
12299           vex_table_index = EVEX_0F38;
12300           break;
12301         case 0x3:
12302           vex_table_index = EVEX_0F3A;
12303           break;
12304         }
12305
12306       /* The second byte after 0x62.  */
12307       codep++;
12308       vex.w = *codep & 0x80;
12309       if (vex.w && address_mode == mode_64bit)
12310         rex |= REX_W;
12311
12312       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12313
12314       /* The U bit.  */
12315       if (!(*codep & 0x4))
12316         return &bad_opcode;
12317
12318       switch ((*codep & 0x3))
12319         {
12320         case 0:
12321           break;
12322         case 1:
12323           vex.prefix = DATA_PREFIX_OPCODE;
12324           break;
12325         case 2:
12326           vex.prefix = REPE_PREFIX_OPCODE;
12327           break;
12328         case 3:
12329           vex.prefix = REPNE_PREFIX_OPCODE;
12330           break;
12331         }
12332
12333       /* The third byte after 0x62.  */
12334       codep++;
12335
12336       /* Remember the static rounding bits.  */
12337       vex.ll = (*codep >> 5) & 3;
12338       vex.b = (*codep & 0x10) != 0;
12339
12340       vex.v = *codep & 0x8;
12341       vex.mask_register_specifier = *codep & 0x7;
12342       vex.zeroing = *codep & 0x80;
12343
12344       if (address_mode != mode_64bit)
12345         {
12346           /* In 16/32-bit mode silently ignore following bits.  */
12347           rex &= ~REX_B;
12348           vex.r = 1;
12349           vex.v = 1;
12350         }
12351
12352       need_vex = 1;
12353       need_vex_reg = 1;
12354       codep++;
12355       vindex = *codep++;
12356       dp = &evex_table[vex_table_index][vindex];
12357       end_codep = codep;
12358       FETCH_DATA (info, codep + 1);
12359       modrm.mod = (*codep >> 6) & 3;
12360       modrm.reg = (*codep >> 3) & 7;
12361       modrm.rm = *codep & 7;
12362
12363       /* Set vector length.  */
12364       if (modrm.mod == 3 && vex.b)
12365         vex.length = 512;
12366       else
12367         {
12368           switch (vex.ll)
12369             {
12370             case 0x0:
12371               vex.length = 128;
12372               break;
12373             case 0x1:
12374               vex.length = 256;
12375               break;
12376             case 0x2:
12377               vex.length = 512;
12378               break;
12379             default:
12380               return &bad_opcode;
12381             }
12382         }
12383       break;
12384
12385     case 0:
12386       dp = &bad_opcode;
12387       break;
12388
12389     default:
12390       abort ();
12391     }
12392
12393   if (dp->name != NULL)
12394     return dp;
12395   else
12396     return get_valid_dis386 (dp, info);
12397 }
12398
12399 static void
12400 get_sib (disassemble_info *info, int sizeflag)
12401 {
12402   /* If modrm.mod == 3, operand must be register.  */
12403   if (need_modrm
12404       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
12405       && modrm.mod != 3
12406       && modrm.rm == 4)
12407     {
12408       FETCH_DATA (info, codep + 2);
12409       sib.index = (codep [1] >> 3) & 7;
12410       sib.scale = (codep [1] >> 6) & 3;
12411       sib.base = codep [1] & 7;
12412     }
12413 }
12414
12415 static int
12416 print_insn (bfd_vma pc, disassemble_info *info)
12417 {
12418   const struct dis386 *dp;
12419   int i;
12420   char *op_txt[MAX_OPERANDS];
12421   int needcomma;
12422   int sizeflag, orig_sizeflag;
12423   const char *p;
12424   struct dis_private priv;
12425   int prefix_length;
12426
12427   priv.orig_sizeflag = AFLAG | DFLAG;
12428   if ((info->mach & bfd_mach_i386_i386) != 0)
12429     address_mode = mode_32bit;
12430   else if (info->mach == bfd_mach_i386_i8086)
12431     {
12432       address_mode = mode_16bit;
12433       priv.orig_sizeflag = 0;
12434     }
12435   else
12436     address_mode = mode_64bit;
12437
12438   if (intel_syntax == (char) -1)
12439     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
12440
12441   for (p = info->disassembler_options; p != NULL; )
12442     {
12443       if (CONST_STRNEQ (p, "amd64"))
12444         isa64 = amd64;
12445       else if (CONST_STRNEQ (p, "intel64"))
12446         isa64 = intel64;
12447       else if (CONST_STRNEQ (p, "x86-64"))
12448         {
12449           address_mode = mode_64bit;
12450           priv.orig_sizeflag |= AFLAG | DFLAG;
12451         }
12452       else if (CONST_STRNEQ (p, "i386"))
12453         {
12454           address_mode = mode_32bit;
12455           priv.orig_sizeflag |= AFLAG | DFLAG;
12456         }
12457       else if (CONST_STRNEQ (p, "i8086"))
12458         {
12459           address_mode = mode_16bit;
12460           priv.orig_sizeflag &= ~(AFLAG | DFLAG);
12461         }
12462       else if (CONST_STRNEQ (p, "intel"))
12463         {
12464           intel_syntax = 1;
12465           if (CONST_STRNEQ (p + 5, "-mnemonic"))
12466             intel_mnemonic = 1;
12467         }
12468       else if (CONST_STRNEQ (p, "att"))
12469         {
12470           intel_syntax = 0;
12471           if (CONST_STRNEQ (p + 3, "-mnemonic"))
12472             intel_mnemonic = 0;
12473         }
12474       else if (CONST_STRNEQ (p, "addr"))
12475         {
12476           if (address_mode == mode_64bit)
12477             {
12478               if (p[4] == '3' && p[5] == '2')
12479                 priv.orig_sizeflag &= ~AFLAG;
12480               else if (p[4] == '6' && p[5] == '4')
12481                 priv.orig_sizeflag |= AFLAG;
12482             }
12483           else
12484             {
12485               if (p[4] == '1' && p[5] == '6')
12486                 priv.orig_sizeflag &= ~AFLAG;
12487               else if (p[4] == '3' && p[5] == '2')
12488                 priv.orig_sizeflag |= AFLAG;
12489             }
12490         }
12491       else if (CONST_STRNEQ (p, "data"))
12492         {
12493           if (p[4] == '1' && p[5] == '6')
12494             priv.orig_sizeflag &= ~DFLAG;
12495           else if (p[4] == '3' && p[5] == '2')
12496             priv.orig_sizeflag |= DFLAG;
12497         }
12498       else if (CONST_STRNEQ (p, "suffix"))
12499         priv.orig_sizeflag |= SUFFIX_ALWAYS;
12500
12501       p = strchr (p, ',');
12502       if (p != NULL)
12503         p++;
12504     }
12505
12506   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
12507     {
12508       (*info->fprintf_func) (info->stream,
12509                              _("64-bit address is disabled"));
12510       return -1;
12511     }
12512
12513   if (intel_syntax)
12514     {
12515       names64 = intel_names64;
12516       names32 = intel_names32;
12517       names16 = intel_names16;
12518       names8 = intel_names8;
12519       names8rex = intel_names8rex;
12520       names_seg = intel_names_seg;
12521       names_mm = intel_names_mm;
12522       names_bnd = intel_names_bnd;
12523       names_xmm = intel_names_xmm;
12524       names_ymm = intel_names_ymm;
12525       names_zmm = intel_names_zmm;
12526       names_tmm = intel_names_tmm;
12527       index64 = intel_index64;
12528       index32 = intel_index32;
12529       names_mask = intel_names_mask;
12530       index16 = intel_index16;
12531       open_char = '[';
12532       close_char = ']';
12533       separator_char = '+';
12534       scale_char = '*';
12535     }
12536   else
12537     {
12538       names64 = att_names64;
12539       names32 = att_names32;
12540       names16 = att_names16;
12541       names8 = att_names8;
12542       names8rex = att_names8rex;
12543       names_seg = att_names_seg;
12544       names_mm = att_names_mm;
12545       names_bnd = att_names_bnd;
12546       names_xmm = att_names_xmm;
12547       names_ymm = att_names_ymm;
12548       names_zmm = att_names_zmm;
12549       names_tmm = att_names_tmm;
12550       index64 = att_index64;
12551       index32 = att_index32;
12552       names_mask = att_names_mask;
12553       index16 = att_index16;
12554       open_char = '(';
12555       close_char =  ')';
12556       separator_char = ',';
12557       scale_char = ',';
12558     }
12559
12560   /* The output looks better if we put 7 bytes on a line, since that
12561      puts most long word instructions on a single line.  Use 8 bytes
12562      for Intel L1OM.  */
12563   if ((info->mach & bfd_mach_l1om) != 0)
12564     info->bytes_per_line = 8;
12565   else
12566     info->bytes_per_line = 7;
12567
12568   info->private_data = &priv;
12569   priv.max_fetched = priv.the_buffer;
12570   priv.insn_start = pc;
12571
12572   obuf[0] = 0;
12573   for (i = 0; i < MAX_OPERANDS; ++i)
12574     {
12575       op_out[i][0] = 0;
12576       op_index[i] = -1;
12577     }
12578
12579   the_info = info;
12580   start_pc = pc;
12581   start_codep = priv.the_buffer;
12582   codep = priv.the_buffer;
12583
12584   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
12585     {
12586       const char *name;
12587
12588       /* Getting here means we tried for data but didn't get it.  That
12589          means we have an incomplete instruction of some sort.  Just
12590          print the first byte as a prefix or a .byte pseudo-op.  */
12591       if (codep > priv.the_buffer)
12592         {
12593           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
12594           if (name != NULL)
12595             (*info->fprintf_func) (info->stream, "%s", name);
12596           else
12597             {
12598               /* Just print the first byte as a .byte instruction.  */
12599               (*info->fprintf_func) (info->stream, ".byte 0x%x",
12600                                      (unsigned int) priv.the_buffer[0]);
12601             }
12602
12603           return 1;
12604         }
12605
12606       return -1;
12607     }
12608
12609   obufp = obuf;
12610   sizeflag = priv.orig_sizeflag;
12611
12612   if (!ckprefix () || rex_used)
12613     {
12614       /* Too many prefixes or unused REX prefixes.  */
12615       for (i = 0;
12616            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
12617            i++)
12618         (*info->fprintf_func) (info->stream, "%s%s",
12619                                i == 0 ? "" : " ",
12620                                prefix_name (all_prefixes[i], sizeflag));
12621       return i;
12622     }
12623
12624   insn_codep = codep;
12625
12626   FETCH_DATA (info, codep + 1);
12627   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
12628
12629   if (((prefixes & PREFIX_FWAIT)
12630        && ((*codep < 0xd8) || (*codep > 0xdf))))
12631     {
12632       /* Handle prefixes before fwait.  */
12633       for (i = 0; i < fwait_prefix && all_prefixes[i];
12634            i++)
12635         (*info->fprintf_func) (info->stream, "%s ",
12636                                prefix_name (all_prefixes[i], sizeflag));
12637       (*info->fprintf_func) (info->stream, "fwait");
12638       return i + 1;
12639     }
12640
12641   if (*codep == 0x0f)
12642     {
12643       unsigned char threebyte;
12644
12645       codep++;
12646       FETCH_DATA (info, codep + 1);
12647       threebyte = *codep;
12648       dp = &dis386_twobyte[threebyte];
12649       need_modrm = twobyte_has_modrm[*codep];
12650       codep++;
12651     }
12652   else
12653     {
12654       dp = &dis386[*codep];
12655       need_modrm = onebyte_has_modrm[*codep];
12656       codep++;
12657     }
12658
12659   /* Save sizeflag for printing the extra prefixes later before updating
12660      it for mnemonic and operand processing.  The prefix names depend
12661      only on the address mode.  */
12662   orig_sizeflag = sizeflag;
12663   if (prefixes & PREFIX_ADDR)
12664     sizeflag ^= AFLAG;
12665   if ((prefixes & PREFIX_DATA))
12666     sizeflag ^= DFLAG;
12667
12668   end_codep = codep;
12669   if (need_modrm)
12670     {
12671       FETCH_DATA (info, codep + 1);
12672       modrm.mod = (*codep >> 6) & 3;
12673       modrm.reg = (*codep >> 3) & 7;
12674       modrm.rm = *codep & 7;
12675     }
12676
12677   need_vex = 0;
12678   need_vex_reg = 0;
12679   memset (&vex, 0, sizeof (vex));
12680
12681   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
12682     {
12683       get_sib (info, sizeflag);
12684       dofloat (sizeflag);
12685     }
12686   else
12687     {
12688       dp = get_valid_dis386 (dp, info);
12689       if (dp != NULL && putop (dp->name, sizeflag) == 0)
12690         {
12691           get_sib (info, sizeflag);
12692           for (i = 0; i < MAX_OPERANDS; ++i)
12693             {
12694               obufp = op_out[i];
12695               op_ad = MAX_OPERANDS - 1 - i;
12696               if (dp->op[i].rtn)
12697                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
12698               /* For EVEX instruction after the last operand masking
12699                  should be printed.  */
12700               if (i == 0 && vex.evex)
12701                 {
12702                   /* Don't print {%k0}.  */
12703                   if (vex.mask_register_specifier)
12704                     {
12705                       oappend ("{");
12706                       oappend (names_mask[vex.mask_register_specifier]);
12707                       oappend ("}");
12708                     }
12709                   if (vex.zeroing)
12710                     oappend ("{z}");
12711                 }
12712             }
12713         }
12714     }
12715
12716   /* Clear instruction information.  */
12717   if (the_info)
12718     {
12719       the_info->insn_info_valid = 0;
12720       the_info->branch_delay_insns = 0;
12721       the_info->data_size = 0;
12722       the_info->insn_type = dis_noninsn;
12723       the_info->target = 0;
12724       the_info->target2 = 0;
12725     }
12726
12727   /* Reset jump operation indicator.  */
12728   op_is_jump = FALSE;
12729
12730   {
12731     int jump_detection = 0;
12732
12733     /* Extract flags.  */
12734     for (i = 0; i < MAX_OPERANDS; ++i)
12735       {
12736         if ((dp->op[i].rtn == OP_J)
12737             || (dp->op[i].rtn == OP_indirE))
12738           jump_detection |= 1;
12739         else if ((dp->op[i].rtn == BND_Fixup)
12740                  || (!dp->op[i].rtn && !dp->op[i].bytemode))
12741           jump_detection |= 2;
12742         else if ((dp->op[i].bytemode == cond_jump_mode)
12743                  || (dp->op[i].bytemode == loop_jcxz_mode))
12744           jump_detection |= 4;
12745       }
12746
12747     /* Determine if this is a jump or branch.  */
12748     if ((jump_detection & 0x3) == 0x3)
12749       {
12750         op_is_jump = TRUE;
12751         if (jump_detection & 0x4)
12752           the_info->insn_type = dis_condbranch;
12753         else
12754           the_info->insn_type =
12755             (dp->name && !strncmp(dp->name, "call", 4))
12756             ? dis_jsr : dis_branch;
12757       }
12758   }
12759
12760   /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
12761      are all 0s in inverted form.  */
12762   if (need_vex && vex.register_specifier != 0)
12763     {
12764       (*info->fprintf_func) (info->stream, "(bad)");
12765       return end_codep - priv.the_buffer;
12766     }
12767
12768   /* Check if the REX prefix is used.  */
12769   if ((rex ^ rex_used) == 0 && !need_vex && last_rex_prefix >= 0)
12770     all_prefixes[last_rex_prefix] = 0;
12771
12772   /* Check if the SEG prefix is used.  */
12773   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
12774                    | PREFIX_FS | PREFIX_GS)) != 0
12775       && (used_prefixes & active_seg_prefix) != 0)
12776     all_prefixes[last_seg_prefix] = 0;
12777
12778   /* Check if the ADDR prefix is used.  */
12779   if ((prefixes & PREFIX_ADDR) != 0
12780       && (used_prefixes & PREFIX_ADDR) != 0)
12781     all_prefixes[last_addr_prefix] = 0;
12782
12783   /* Check if the DATA prefix is used.  */
12784   if ((prefixes & PREFIX_DATA) != 0
12785       && (used_prefixes & PREFIX_DATA) != 0
12786       && !need_vex)
12787     all_prefixes[last_data_prefix] = 0;
12788
12789   /* Print the extra prefixes.  */
12790   prefix_length = 0;
12791   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12792     if (all_prefixes[i])
12793       {
12794         const char *name;
12795         name = prefix_name (all_prefixes[i], orig_sizeflag);
12796         if (name == NULL)
12797           abort ();
12798         prefix_length += strlen (name) + 1;
12799         (*info->fprintf_func) (info->stream, "%s ", name);
12800       }
12801
12802   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
12803      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
12804      used by putop and MMX/SSE operand and may be overriden by the
12805      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
12806      separately.  */
12807   if (dp->prefix_requirement == PREFIX_OPCODE
12808       && (((need_vex
12809             ? vex.prefix == REPE_PREFIX_OPCODE
12810               || vex.prefix == REPNE_PREFIX_OPCODE
12811             : (prefixes
12812                & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12813            && (used_prefixes
12814                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
12815           || (((need_vex
12816                 ? vex.prefix == DATA_PREFIX_OPCODE
12817                 : ((prefixes
12818                     & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
12819                    == PREFIX_DATA))
12820                && (used_prefixes & PREFIX_DATA) == 0))
12821           || (vex.evex && !vex.w != !(used_prefixes & PREFIX_DATA))))
12822     {
12823       (*info->fprintf_func) (info->stream, "(bad)");
12824       return end_codep - priv.the_buffer;
12825     }
12826
12827   /* Check maximum code length.  */
12828   if ((codep - start_codep) > MAX_CODE_LENGTH)
12829     {
12830       (*info->fprintf_func) (info->stream, "(bad)");
12831       return MAX_CODE_LENGTH;
12832     }
12833
12834   obufp = mnemonicendp;
12835   for (i = strlen (obuf) + prefix_length; i < 6; i++)
12836     oappend (" ");
12837   oappend (" ");
12838   (*info->fprintf_func) (info->stream, "%s", obuf);
12839
12840   /* The enter and bound instructions are printed with operands in the same
12841      order as the intel book; everything else is printed in reverse order.  */
12842   if (intel_syntax || two_source_ops)
12843     {
12844       bfd_vma riprel;
12845
12846       for (i = 0; i < MAX_OPERANDS; ++i)
12847         op_txt[i] = op_out[i];
12848
12849       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
12850           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
12851         {
12852           op_txt[2] = op_out[3];
12853           op_txt[3] = op_out[2];
12854         }
12855
12856       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
12857         {
12858           op_ad = op_index[i];
12859           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
12860           op_index[MAX_OPERANDS - 1 - i] = op_ad;
12861           riprel = op_riprel[i];
12862           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
12863           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
12864         }
12865     }
12866   else
12867     {
12868       for (i = 0; i < MAX_OPERANDS; ++i)
12869         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
12870     }
12871
12872   needcomma = 0;
12873   for (i = 0; i < MAX_OPERANDS; ++i)
12874     if (*op_txt[i])
12875       {
12876         if (needcomma)
12877           (*info->fprintf_func) (info->stream, ",");
12878         if (op_index[i] != -1 && !op_riprel[i])
12879           {
12880             bfd_vma target = (bfd_vma) op_address[op_index[i]];
12881
12882             if (the_info && op_is_jump)
12883               {
12884                 the_info->insn_info_valid = 1;
12885                 the_info->branch_delay_insns = 0;
12886                 the_info->data_size = 0;
12887                 the_info->target = target;
12888                 the_info->target2 = 0;
12889               }
12890             (*info->print_address_func) (target, info);
12891           }
12892         else
12893           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
12894         needcomma = 1;
12895       }
12896
12897   for (i = 0; i < MAX_OPERANDS; i++)
12898     if (op_index[i] != -1 && op_riprel[i])
12899       {
12900         (*info->fprintf_func) (info->stream, "        # ");
12901         (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
12902                                                 + op_address[op_index[i]]), info);
12903         break;
12904       }
12905   return codep - priv.the_buffer;
12906 }
12907
12908 static const char *float_mem[] = {
12909   /* d8 */
12910   "fadd{s|}",
12911   "fmul{s|}",
12912   "fcom{s|}",
12913   "fcomp{s|}",
12914   "fsub{s|}",
12915   "fsubr{s|}",
12916   "fdiv{s|}",
12917   "fdivr{s|}",
12918   /* d9 */
12919   "fld{s|}",
12920   "(bad)",
12921   "fst{s|}",
12922   "fstp{s|}",
12923   "fldenv{C|C}",
12924   "fldcw",
12925   "fNstenv{C|C}",
12926   "fNstcw",
12927   /* da */
12928   "fiadd{l|}",
12929   "fimul{l|}",
12930   "ficom{l|}",
12931   "ficomp{l|}",
12932   "fisub{l|}",
12933   "fisubr{l|}",
12934   "fidiv{l|}",
12935   "fidivr{l|}",
12936   /* db */
12937   "fild{l|}",
12938   "fisttp{l|}",
12939   "fist{l|}",
12940   "fistp{l|}",
12941   "(bad)",
12942   "fld{t|}",
12943   "(bad)",
12944   "fstp{t|}",
12945   /* dc */
12946   "fadd{l|}",
12947   "fmul{l|}",
12948   "fcom{l|}",
12949   "fcomp{l|}",
12950   "fsub{l|}",
12951   "fsubr{l|}",
12952   "fdiv{l|}",
12953   "fdivr{l|}",
12954   /* dd */
12955   "fld{l|}",
12956   "fisttp{ll|}",
12957   "fst{l||}",
12958   "fstp{l|}",
12959   "frstor{C|C}",
12960   "(bad)",
12961   "fNsave{C|C}",
12962   "fNstsw",
12963   /* de */
12964   "fiadd{s|}",
12965   "fimul{s|}",
12966   "ficom{s|}",
12967   "ficomp{s|}",
12968   "fisub{s|}",
12969   "fisubr{s|}",
12970   "fidiv{s|}",
12971   "fidivr{s|}",
12972   /* df */
12973   "fild{s|}",
12974   "fisttp{s|}",
12975   "fist{s|}",
12976   "fistp{s|}",
12977   "fbld",
12978   "fild{ll|}",
12979   "fbstp",
12980   "fistp{ll|}",
12981 };
12982
12983 static const unsigned char float_mem_mode[] = {
12984   /* d8 */
12985   d_mode,
12986   d_mode,
12987   d_mode,
12988   d_mode,
12989   d_mode,
12990   d_mode,
12991   d_mode,
12992   d_mode,
12993   /* d9 */
12994   d_mode,
12995   0,
12996   d_mode,
12997   d_mode,
12998   0,
12999   w_mode,
13000   0,
13001   w_mode,
13002   /* da */
13003   d_mode,
13004   d_mode,
13005   d_mode,
13006   d_mode,
13007   d_mode,
13008   d_mode,
13009   d_mode,
13010   d_mode,
13011   /* db */
13012   d_mode,
13013   d_mode,
13014   d_mode,
13015   d_mode,
13016   0,
13017   t_mode,
13018   0,
13019   t_mode,
13020   /* dc */
13021   q_mode,
13022   q_mode,
13023   q_mode,
13024   q_mode,
13025   q_mode,
13026   q_mode,
13027   q_mode,
13028   q_mode,
13029   /* dd */
13030   q_mode,
13031   q_mode,
13032   q_mode,
13033   q_mode,
13034   0,
13035   0,
13036   0,
13037   w_mode,
13038   /* de */
13039   w_mode,
13040   w_mode,
13041   w_mode,
13042   w_mode,
13043   w_mode,
13044   w_mode,
13045   w_mode,
13046   w_mode,
13047   /* df */
13048   w_mode,
13049   w_mode,
13050   w_mode,
13051   w_mode,
13052   t_mode,
13053   q_mode,
13054   t_mode,
13055   q_mode
13056 };
13057
13058 #define ST { OP_ST, 0 }
13059 #define STi { OP_STi, 0 }
13060
13061 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
13062 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
13063 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
13064 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
13065 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
13066 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
13067 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
13068 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
13069 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
13070
13071 static const struct dis386 float_reg[][8] = {
13072   /* d8 */
13073   {
13074     { "fadd",   { ST, STi }, 0 },
13075     { "fmul",   { ST, STi }, 0 },
13076     { "fcom",   { STi }, 0 },
13077     { "fcomp",  { STi }, 0 },
13078     { "fsub",   { ST, STi }, 0 },
13079     { "fsubr",  { ST, STi }, 0 },
13080     { "fdiv",   { ST, STi }, 0 },
13081     { "fdivr",  { ST, STi }, 0 },
13082   },
13083   /* d9 */
13084   {
13085     { "fld",    { STi }, 0 },
13086     { "fxch",   { STi }, 0 },
13087     { FGRPd9_2 },
13088     { Bad_Opcode },
13089     { FGRPd9_4 },
13090     { FGRPd9_5 },
13091     { FGRPd9_6 },
13092     { FGRPd9_7 },
13093   },
13094   /* da */
13095   {
13096     { "fcmovb", { ST, STi }, 0 },
13097     { "fcmove", { ST, STi }, 0 },
13098     { "fcmovbe",{ ST, STi }, 0 },
13099     { "fcmovu", { ST, STi }, 0 },
13100     { Bad_Opcode },
13101     { FGRPda_5 },
13102     { Bad_Opcode },
13103     { Bad_Opcode },
13104   },
13105   /* db */
13106   {
13107     { "fcmovnb",{ ST, STi }, 0 },
13108     { "fcmovne",{ ST, STi }, 0 },
13109     { "fcmovnbe",{ ST, STi }, 0 },
13110     { "fcmovnu",{ ST, STi }, 0 },
13111     { FGRPdb_4 },
13112     { "fucomi", { ST, STi }, 0 },
13113     { "fcomi",  { ST, STi }, 0 },
13114     { Bad_Opcode },
13115   },
13116   /* dc */
13117   {
13118     { "fadd",   { STi, ST }, 0 },
13119     { "fmul",   { STi, ST }, 0 },
13120     { Bad_Opcode },
13121     { Bad_Opcode },
13122     { "fsub{!M|r}",     { STi, ST }, 0 },
13123     { "fsub{M|}",       { STi, ST }, 0 },
13124     { "fdiv{!M|r}",     { STi, ST }, 0 },
13125     { "fdiv{M|}",       { STi, ST }, 0 },
13126   },
13127   /* dd */
13128   {
13129     { "ffree",  { STi }, 0 },
13130     { Bad_Opcode },
13131     { "fst",    { STi }, 0 },
13132     { "fstp",   { STi }, 0 },
13133     { "fucom",  { STi }, 0 },
13134     { "fucomp", { STi }, 0 },
13135     { Bad_Opcode },
13136     { Bad_Opcode },
13137   },
13138   /* de */
13139   {
13140     { "faddp",  { STi, ST }, 0 },
13141     { "fmulp",  { STi, ST }, 0 },
13142     { Bad_Opcode },
13143     { FGRPde_3 },
13144     { "fsub{!M|r}p",    { STi, ST }, 0 },
13145     { "fsub{M|}p",      { STi, ST }, 0 },
13146     { "fdiv{!M|r}p",    { STi, ST }, 0 },
13147     { "fdiv{M|}p",      { STi, ST }, 0 },
13148   },
13149   /* df */
13150   {
13151     { "ffreep", { STi }, 0 },
13152     { Bad_Opcode },
13153     { Bad_Opcode },
13154     { Bad_Opcode },
13155     { FGRPdf_4 },
13156     { "fucomip", { ST, STi }, 0 },
13157     { "fcomip", { ST, STi }, 0 },
13158     { Bad_Opcode },
13159   },
13160 };
13161
13162 static char *fgrps[][8] = {
13163   /* Bad opcode 0 */
13164   {
13165     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13166   },
13167
13168   /* d9_2  1 */
13169   {
13170     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13171   },
13172
13173   /* d9_4  2 */
13174   {
13175     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13176   },
13177
13178   /* d9_5  3 */
13179   {
13180     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13181   },
13182
13183   /* d9_6  4 */
13184   {
13185     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13186   },
13187
13188   /* d9_7  5 */
13189   {
13190     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13191   },
13192
13193   /* da_5  6 */
13194   {
13195     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13196   },
13197
13198   /* db_4  7 */
13199   {
13200     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13201     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13202   },
13203
13204   /* de_3  8 */
13205   {
13206     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13207   },
13208
13209   /* df_4  9 */
13210   {
13211     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13212   },
13213 };
13214
13215 static void
13216 swap_operand (void)
13217 {
13218   mnemonicendp[0] = '.';
13219   mnemonicendp[1] = 's';
13220   mnemonicendp += 2;
13221 }
13222
13223 static void
13224 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
13225                int sizeflag ATTRIBUTE_UNUSED)
13226 {
13227   /* Skip mod/rm byte.  */
13228   MODRM_CHECK;
13229   codep++;
13230 }
13231
13232 static void
13233 dofloat (int sizeflag)
13234 {
13235   const struct dis386 *dp;
13236   unsigned char floatop;
13237
13238   floatop = codep[-1];
13239
13240   if (modrm.mod != 3)
13241     {
13242       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
13243
13244       putop (float_mem[fp_indx], sizeflag);
13245       obufp = op_out[0];
13246       op_ad = 2;
13247       OP_E (float_mem_mode[fp_indx], sizeflag);
13248       return;
13249     }
13250   /* Skip mod/rm byte.  */
13251   MODRM_CHECK;
13252   codep++;
13253
13254   dp = &float_reg[floatop - 0xd8][modrm.reg];
13255   if (dp->name == NULL)
13256     {
13257       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
13258
13259       /* Instruction fnstsw is only one with strange arg.  */
13260       if (floatop == 0xdf && codep[-1] == 0xe0)
13261         strcpy (op_out[0], names16[0]);
13262     }
13263   else
13264     {
13265       putop (dp->name, sizeflag);
13266
13267       obufp = op_out[0];
13268       op_ad = 2;
13269       if (dp->op[0].rtn)
13270         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
13271
13272       obufp = op_out[1];
13273       op_ad = 1;
13274       if (dp->op[1].rtn)
13275         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
13276     }
13277 }
13278
13279 /* Like oappend (below), but S is a string starting with '%'.
13280    In Intel syntax, the '%' is elided.  */
13281 static void
13282 oappend_maybe_intel (const char *s)
13283 {
13284   oappend (s + intel_syntax);
13285 }
13286
13287 static void
13288 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13289 {
13290   oappend_maybe_intel ("%st");
13291 }
13292
13293 static void
13294 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13295 {
13296   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
13297   oappend_maybe_intel (scratchbuf);
13298 }
13299
13300 /* Capital letters in template are macros.  */
13301 static int
13302 putop (const char *in_template, int sizeflag)
13303 {
13304   const char *p;
13305   int alt = 0;
13306   int cond = 1;
13307   unsigned int l = 0, len = 0;
13308   char last[4];
13309
13310   for (p = in_template; *p; p++)
13311     {
13312       if (len > l)
13313         {
13314           if (l >= sizeof (last) || !ISUPPER (*p))
13315             abort ();
13316           last[l++] = *p;
13317           continue;
13318         }
13319       switch (*p)
13320         {
13321         default:
13322           *obufp++ = *p;
13323           break;
13324         case '%':
13325           len++;
13326           break;
13327         case '!':
13328           cond = 0;
13329           break;
13330         case '{':
13331           if (intel_syntax)
13332             {
13333               while (*++p != '|')
13334                 if (*p == '}' || *p == '\0')
13335                   abort ();
13336               alt = 1;
13337             }
13338           break;
13339         case '|':
13340           while (*++p != '}')
13341             {
13342               if (*p == '\0')
13343                 abort ();
13344             }
13345           break;
13346         case '}':
13347           alt = 0;
13348           break;
13349         case 'A':
13350           if (intel_syntax)
13351             break;
13352           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13353             *obufp++ = 'b';
13354           break;
13355         case 'B':
13356           if (l == 0)
13357             {
13358             case_B:
13359               if (intel_syntax)
13360                 break;
13361               if (sizeflag & SUFFIX_ALWAYS)
13362                 *obufp++ = 'b';
13363             }
13364           else if (l == 1 && last[0] == 'L')
13365             {
13366               if (address_mode == mode_64bit
13367                   && !(prefixes & PREFIX_ADDR))
13368                 {
13369                   *obufp++ = 'a';
13370                   *obufp++ = 'b';
13371                   *obufp++ = 's';
13372                 }
13373
13374               goto case_B;
13375             }
13376           else
13377             abort ();
13378           break;
13379         case 'C':
13380           if (intel_syntax && !alt)
13381             break;
13382           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13383             {
13384               if (sizeflag & DFLAG)
13385                 *obufp++ = intel_syntax ? 'd' : 'l';
13386               else
13387                 *obufp++ = intel_syntax ? 'w' : 's';
13388               used_prefixes |= (prefixes & PREFIX_DATA);
13389             }
13390           break;
13391         case 'D':
13392           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
13393             break;
13394           USED_REX (REX_W);
13395           if (modrm.mod == 3)
13396             {
13397               if (rex & REX_W)
13398                 *obufp++ = 'q';
13399               else
13400                 {
13401                   if (sizeflag & DFLAG)
13402                     *obufp++ = intel_syntax ? 'd' : 'l';
13403                   else
13404                     *obufp++ = 'w';
13405                   used_prefixes |= (prefixes & PREFIX_DATA);
13406                 }
13407             }
13408           else
13409             *obufp++ = 'w';
13410           break;
13411         case 'E':               /* For jcxz/jecxz */
13412           if (address_mode == mode_64bit)
13413             {
13414               if (sizeflag & AFLAG)
13415                 *obufp++ = 'r';
13416               else
13417                 *obufp++ = 'e';
13418             }
13419           else
13420             if (sizeflag & AFLAG)
13421               *obufp++ = 'e';
13422           used_prefixes |= (prefixes & PREFIX_ADDR);
13423           break;
13424         case 'F':
13425           if (intel_syntax)
13426             break;
13427           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
13428             {
13429               if (sizeflag & AFLAG)
13430                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
13431               else
13432                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
13433               used_prefixes |= (prefixes & PREFIX_ADDR);
13434             }
13435           break;
13436         case 'G':
13437           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
13438             break;
13439           if ((rex & REX_W) || (sizeflag & DFLAG))
13440             *obufp++ = 'l';
13441           else
13442             *obufp++ = 'w';
13443           if (!(rex & REX_W))
13444             used_prefixes |= (prefixes & PREFIX_DATA);
13445           break;
13446         case 'H':
13447           if (intel_syntax)
13448             break;
13449           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
13450               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
13451             {
13452               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
13453               *obufp++ = ',';
13454               *obufp++ = 'p';
13455               if (prefixes & PREFIX_DS)
13456                 *obufp++ = 't';
13457               else
13458                 *obufp++ = 'n';
13459             }
13460           break;
13461         case 'K':
13462           USED_REX (REX_W);
13463           if (rex & REX_W)
13464             *obufp++ = 'q';
13465           else
13466             *obufp++ = 'd';
13467           break;
13468         case 'Z':
13469           if (l != 0)
13470             {
13471               if (l != 1 || last[0] != 'X')
13472                 abort ();
13473               if (!need_vex || !vex.evex)
13474                 abort ();
13475               if (intel_syntax
13476                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
13477                 break;
13478               switch (vex.length)
13479                 {
13480                 case 128:
13481                   *obufp++ = 'x';
13482                   break;
13483                 case 256:
13484                   *obufp++ = 'y';
13485                   break;
13486                 case 512:
13487                   *obufp++ = 'z';
13488                   break;
13489                 default:
13490                   abort ();
13491                 }
13492               break;
13493             }
13494           if (intel_syntax)
13495             break;
13496           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
13497             {
13498               *obufp++ = 'q';
13499               break;
13500             }
13501           /* Fall through.  */
13502           goto case_L;
13503         case 'L':
13504           if (l != 0)
13505             abort ();
13506         case_L:
13507           if (intel_syntax)
13508             break;
13509           if (sizeflag & SUFFIX_ALWAYS)
13510             *obufp++ = 'l';
13511           break;
13512         case 'M':
13513           if (intel_mnemonic != cond)
13514             *obufp++ = 'r';
13515           break;
13516         case 'N':
13517           if ((prefixes & PREFIX_FWAIT) == 0)
13518             *obufp++ = 'n';
13519           else
13520             used_prefixes |= PREFIX_FWAIT;
13521           break;
13522         case 'O':
13523           USED_REX (REX_W);
13524           if (rex & REX_W)
13525             *obufp++ = 'o';
13526           else if (intel_syntax && (sizeflag & DFLAG))
13527             *obufp++ = 'q';
13528           else
13529             *obufp++ = 'd';
13530           if (!(rex & REX_W))
13531             used_prefixes |= (prefixes & PREFIX_DATA);
13532           break;
13533         case '&':
13534           if (!intel_syntax
13535               && address_mode == mode_64bit
13536               && isa64 == intel64)
13537             {
13538               *obufp++ = 'q';
13539               break;
13540             }
13541           /* Fall through.  */
13542         case 'T':
13543           if (!intel_syntax
13544               && address_mode == mode_64bit
13545               && ((sizeflag & DFLAG) || (rex & REX_W)))
13546             {
13547               *obufp++ = 'q';
13548               break;
13549             }
13550           /* Fall through.  */
13551           goto case_P;
13552         case 'P':
13553           if (l == 0)
13554             {
13555             case_P:
13556               if (intel_syntax)
13557                 {
13558                   if ((rex & REX_W) == 0
13559                       && (prefixes & PREFIX_DATA))
13560                     {
13561                       if ((sizeflag & DFLAG) == 0)
13562                         *obufp++ = 'w';
13563                       used_prefixes |= (prefixes & PREFIX_DATA);
13564                     }
13565                   break;
13566                 }
13567               if ((prefixes & PREFIX_DATA)
13568                   || (rex & REX_W)
13569                   || (sizeflag & SUFFIX_ALWAYS))
13570                 {
13571                   USED_REX (REX_W);
13572                   if (rex & REX_W)
13573                     *obufp++ = 'q';
13574                   else
13575                     {
13576                       if (sizeflag & DFLAG)
13577                         *obufp++ = 'l';
13578                       else
13579                         *obufp++ = 'w';
13580                       used_prefixes |= (prefixes & PREFIX_DATA);
13581                     }
13582                 }
13583             }
13584           else if (l == 1 && last[0] == 'L')
13585             {
13586               if ((prefixes & PREFIX_DATA)
13587                   || (rex & REX_W)
13588                   || (sizeflag & SUFFIX_ALWAYS))
13589                 {
13590                   USED_REX (REX_W);
13591                   if (rex & REX_W)
13592                     *obufp++ = 'q';
13593                   else
13594                     {
13595                       if (sizeflag & DFLAG)
13596                         *obufp++ = intel_syntax ? 'd' : 'l';
13597                       else
13598                         *obufp++ = 'w';
13599                       used_prefixes |= (prefixes & PREFIX_DATA);
13600                     }
13601                 }
13602             }
13603           else
13604             abort ();
13605           break;
13606         case 'U':
13607           if (intel_syntax)
13608             break;
13609           if (address_mode == mode_64bit
13610               && ((sizeflag & DFLAG) || (rex & REX_W)))
13611             {
13612               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13613                 *obufp++ = 'q';
13614               break;
13615             }
13616           /* Fall through.  */
13617           goto case_Q;
13618         case 'Q':
13619           if (l == 0)
13620             {
13621             case_Q:
13622               if (intel_syntax && !alt)
13623                 break;
13624               USED_REX (REX_W);
13625               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13626                 {
13627                   if (rex & REX_W)
13628                     *obufp++ = 'q';
13629                   else
13630                     {
13631                       if (sizeflag & DFLAG)
13632                         *obufp++ = intel_syntax ? 'd' : 'l';
13633                       else
13634                         *obufp++ = 'w';
13635                       used_prefixes |= (prefixes & PREFIX_DATA);
13636                     }
13637                 }
13638             }
13639           else if (l == 1 && last[0] == 'L')
13640             {
13641               if (cond ? modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)
13642                        : address_mode != mode_64bit)
13643                 break;
13644               if ((rex & REX_W))
13645                 {
13646                   USED_REX (REX_W);
13647                   *obufp++ = 'q';
13648                 }
13649               else if((address_mode == mode_64bit && need_modrm && cond)
13650                       || (sizeflag & SUFFIX_ALWAYS))
13651                 *obufp++ = intel_syntax? 'd' : 'l';
13652             }
13653           else
13654             abort ();
13655           break;
13656         case 'R':
13657           USED_REX (REX_W);
13658           if (rex & REX_W)
13659             *obufp++ = 'q';
13660           else if (sizeflag & DFLAG)
13661             {
13662               if (intel_syntax)
13663                   *obufp++ = 'd';
13664               else
13665                   *obufp++ = 'l';
13666             }
13667           else
13668             *obufp++ = 'w';
13669           if (intel_syntax && !p[1]
13670               && ((rex & REX_W) || (sizeflag & DFLAG)))
13671             *obufp++ = 'e';
13672           if (!(rex & REX_W))
13673             used_prefixes |= (prefixes & PREFIX_DATA);
13674           break;
13675         case 'V':
13676           if (l == 0)
13677             {
13678               if (intel_syntax)
13679                 break;
13680               if (address_mode == mode_64bit
13681                   && ((sizeflag & DFLAG) || (rex & REX_W)))
13682                 {
13683                   if (sizeflag & SUFFIX_ALWAYS)
13684                     *obufp++ = 'q';
13685                   break;
13686                 }
13687             }
13688           else if (l == 1 && last[0] == 'L')
13689             {
13690               if (rex & REX_W)
13691                 {
13692                   *obufp++ = 'a';
13693                   *obufp++ = 'b';
13694                   *obufp++ = 's';
13695                 }
13696             }
13697           else
13698             abort ();
13699           /* Fall through.  */
13700           goto case_S;
13701         case 'S':
13702           if (l == 0)
13703             {
13704             case_S:
13705               if (intel_syntax)
13706                 break;
13707               if (sizeflag & SUFFIX_ALWAYS)
13708                 {
13709                   if (rex & REX_W)
13710                     *obufp++ = 'q';
13711                   else
13712                     {
13713                       if (sizeflag & DFLAG)
13714                         *obufp++ = 'l';
13715                       else
13716                         *obufp++ = 'w';
13717                       used_prefixes |= (prefixes & PREFIX_DATA);
13718                     }
13719                 }
13720             }
13721           else if (l == 1 && last[0] == 'L')
13722             {
13723               if (address_mode == mode_64bit
13724                   && !(prefixes & PREFIX_ADDR))
13725                 {
13726                   *obufp++ = 'a';
13727                   *obufp++ = 'b';
13728                   *obufp++ = 's';
13729                 }
13730
13731               goto case_S;
13732             }
13733           else
13734             abort ();
13735           break;
13736         case 'X':
13737           if (l != 0)
13738             abort ();
13739           if (need_vex
13740               ? vex.prefix == DATA_PREFIX_OPCODE
13741               : prefixes & PREFIX_DATA)
13742             {
13743               *obufp++ = 'd';
13744               used_prefixes |= PREFIX_DATA;
13745             }
13746           else
13747             *obufp++ = 's';
13748           break;
13749         case 'Y':
13750           if (l == 1 && last[0] == 'X')
13751             {
13752               if (!need_vex)
13753                 abort ();
13754               if (intel_syntax
13755                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
13756                 break;
13757               switch (vex.length)
13758                 {
13759                 case 128:
13760                   *obufp++ = 'x';
13761                   break;
13762                 case 256:
13763                   *obufp++ = 'y';
13764                   break;
13765                 case 512:
13766                   if (!vex.evex)
13767                 default:
13768                     abort ();
13769                 }
13770             }
13771           else
13772             abort ();
13773           break;
13774         case 'W':
13775           if (l == 0)
13776             {
13777               /* operand size flag for cwtl, cbtw */
13778               USED_REX (REX_W);
13779               if (rex & REX_W)
13780                 {
13781                   if (intel_syntax)
13782                     *obufp++ = 'd';
13783                   else
13784                     *obufp++ = 'l';
13785                 }
13786               else if (sizeflag & DFLAG)
13787                 *obufp++ = 'w';
13788               else
13789                 *obufp++ = 'b';
13790               if (!(rex & REX_W))
13791                 used_prefixes |= (prefixes & PREFIX_DATA);
13792             }
13793           else if (l == 1)
13794             {
13795               if (!need_vex)
13796                 abort ();
13797               if (last[0] == 'X')
13798                 *obufp++ = vex.w ? 'd': 's';
13799               else if (last[0] == 'L')
13800                 *obufp++ = vex.w ? 'q': 'd';
13801               else if (last[0] == 'B')
13802                 *obufp++ = vex.w ? 'w': 'b';
13803               else
13804                 abort ();
13805             }
13806           else
13807             abort ();
13808           break;
13809         case '^':
13810           if (intel_syntax)
13811             break;
13812           if (isa64 == intel64 && (rex & REX_W))
13813             {
13814               USED_REX (REX_W);
13815               *obufp++ = 'q';
13816               break;
13817             }
13818           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13819             {
13820               if (sizeflag & DFLAG)
13821                 *obufp++ = 'l';
13822               else
13823                 *obufp++ = 'w';
13824               used_prefixes |= (prefixes & PREFIX_DATA);
13825             }
13826           break;
13827         case '@':
13828           if (intel_syntax)
13829             break;
13830           if (address_mode == mode_64bit
13831               && (isa64 == intel64
13832                   || ((sizeflag & DFLAG) || (rex & REX_W))))
13833               *obufp++ = 'q';
13834           else if ((prefixes & PREFIX_DATA))
13835             {
13836               if (!(sizeflag & DFLAG))
13837                 *obufp++ = 'w';
13838               used_prefixes |= (prefixes & PREFIX_DATA);
13839             }
13840           break;
13841         }
13842
13843       if (len == l)
13844         len = l = 0;
13845     }
13846   *obufp = 0;
13847   mnemonicendp = obufp;
13848   return 0;
13849 }
13850
13851 static void
13852 oappend (const char *s)
13853 {
13854   obufp = stpcpy (obufp, s);
13855 }
13856
13857 static void
13858 append_seg (void)
13859 {
13860   /* Only print the active segment register.  */
13861   if (!active_seg_prefix)
13862     return;
13863
13864   used_prefixes |= active_seg_prefix;
13865   switch (active_seg_prefix)
13866     {
13867     case PREFIX_CS:
13868       oappend_maybe_intel ("%cs:");
13869       break;
13870     case PREFIX_DS:
13871       oappend_maybe_intel ("%ds:");
13872       break;
13873     case PREFIX_SS:
13874       oappend_maybe_intel ("%ss:");
13875       break;
13876     case PREFIX_ES:
13877       oappend_maybe_intel ("%es:");
13878       break;
13879     case PREFIX_FS:
13880       oappend_maybe_intel ("%fs:");
13881       break;
13882     case PREFIX_GS:
13883       oappend_maybe_intel ("%gs:");
13884       break;
13885     default:
13886       break;
13887     }
13888 }
13889
13890 static void
13891 OP_indirE (int bytemode, int sizeflag)
13892 {
13893   if (!intel_syntax)
13894     oappend ("*");
13895   OP_E (bytemode, sizeflag);
13896 }
13897
13898 static void
13899 print_operand_value (char *buf, int hex, bfd_vma disp)
13900 {
13901   if (address_mode == mode_64bit)
13902     {
13903       if (hex)
13904         {
13905           char tmp[30];
13906           int i;
13907           buf[0] = '0';
13908           buf[1] = 'x';
13909           sprintf_vma (tmp, disp);
13910           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
13911           strcpy (buf + 2, tmp + i);
13912         }
13913       else
13914         {
13915           bfd_signed_vma v = disp;
13916           char tmp[30];
13917           int i;
13918           if (v < 0)
13919             {
13920               *(buf++) = '-';
13921               v = -disp;
13922               /* Check for possible overflow on 0x8000000000000000.  */
13923               if (v < 0)
13924                 {
13925                   strcpy (buf, "9223372036854775808");
13926                   return;
13927                 }
13928             }
13929           if (!v)
13930             {
13931               strcpy (buf, "0");
13932               return;
13933             }
13934
13935           i = 0;
13936           tmp[29] = 0;
13937           while (v)
13938             {
13939               tmp[28 - i] = (v % 10) + '0';
13940               v /= 10;
13941               i++;
13942             }
13943           strcpy (buf, tmp + 29 - i);
13944         }
13945     }
13946   else
13947     {
13948       if (hex)
13949         sprintf (buf, "0x%x", (unsigned int) disp);
13950       else
13951         sprintf (buf, "%d", (int) disp);
13952     }
13953 }
13954
13955 /* Put DISP in BUF as signed hex number.  */
13956
13957 static void
13958 print_displacement (char *buf, bfd_vma disp)
13959 {
13960   bfd_signed_vma val = disp;
13961   char tmp[30];
13962   int i, j = 0;
13963
13964   if (val < 0)
13965     {
13966       buf[j++] = '-';
13967       val = -disp;
13968
13969       /* Check for possible overflow.  */
13970       if (val < 0)
13971         {
13972           switch (address_mode)
13973             {
13974             case mode_64bit:
13975               strcpy (buf + j, "0x8000000000000000");
13976               break;
13977             case mode_32bit:
13978               strcpy (buf + j, "0x80000000");
13979               break;
13980             case mode_16bit:
13981               strcpy (buf + j, "0x8000");
13982               break;
13983             }
13984           return;
13985         }
13986     }
13987
13988   buf[j++] = '0';
13989   buf[j++] = 'x';
13990
13991   sprintf_vma (tmp, (bfd_vma) val);
13992   for (i = 0; tmp[i] == '0'; i++)
13993     continue;
13994   if (tmp[i] == '\0')
13995     i--;
13996   strcpy (buf + j, tmp + i);
13997 }
13998
13999 static void
14000 intel_operand_size (int bytemode, int sizeflag)
14001 {
14002   if (vex.evex
14003       && vex.b
14004       && (bytemode == x_mode
14005           || bytemode == evex_half_bcst_xmmq_mode))
14006     {
14007       if (vex.w)
14008         oappend ("QWORD PTR ");
14009       else
14010         oappend ("DWORD PTR ");
14011       return;
14012     }
14013   switch (bytemode)
14014     {
14015     case b_mode:
14016     case b_swap_mode:
14017     case dqb_mode:
14018     case db_mode:
14019       oappend ("BYTE PTR ");
14020       break;
14021     case w_mode:
14022     case dw_mode:
14023     case dqw_mode:
14024       oappend ("WORD PTR ");
14025       break;
14026     case indir_v_mode:
14027       if (address_mode == mode_64bit && isa64 == intel64)
14028         {
14029           oappend ("QWORD PTR ");
14030           break;
14031         }
14032       /* Fall through.  */
14033     case stack_v_mode:
14034       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14035         {
14036           oappend ("QWORD PTR ");
14037           break;
14038         }
14039       /* Fall through.  */
14040     case v_mode:
14041     case v_swap_mode:
14042     case dq_mode:
14043       USED_REX (REX_W);
14044       if (rex & REX_W)
14045         oappend ("QWORD PTR ");
14046       else
14047         {
14048           if ((sizeflag & DFLAG) || bytemode == dq_mode)
14049             oappend ("DWORD PTR ");
14050           else
14051             oappend ("WORD PTR ");
14052           used_prefixes |= (prefixes & PREFIX_DATA);
14053         }
14054       break;
14055     case z_mode:
14056       if ((rex & REX_W) || (sizeflag & DFLAG))
14057         *obufp++ = 'D';
14058       oappend ("WORD PTR ");
14059       if (!(rex & REX_W))
14060         used_prefixes |= (prefixes & PREFIX_DATA);
14061       break;
14062     case a_mode:
14063       if (sizeflag & DFLAG)
14064         oappend ("QWORD PTR ");
14065       else
14066         oappend ("DWORD PTR ");
14067       used_prefixes |= (prefixes & PREFIX_DATA);
14068       break;
14069     case movsxd_mode:
14070       if (!(sizeflag & DFLAG) && isa64 == intel64)
14071         oappend ("WORD PTR ");
14072       else
14073         oappend ("DWORD PTR ");
14074       used_prefixes |= (prefixes & PREFIX_DATA);
14075       break;
14076     case d_mode:
14077     case d_scalar_swap_mode:
14078     case d_swap_mode:
14079     case dqd_mode:
14080       oappend ("DWORD PTR ");
14081       break;
14082     case q_mode:
14083     case q_scalar_swap_mode:
14084     case q_swap_mode:
14085       oappend ("QWORD PTR ");
14086       break;
14087     case m_mode:
14088       if (address_mode == mode_64bit)
14089         oappend ("QWORD PTR ");
14090       else
14091         oappend ("DWORD PTR ");
14092       break;
14093     case f_mode:
14094       if (sizeflag & DFLAG)
14095         oappend ("FWORD PTR ");
14096       else
14097         oappend ("DWORD PTR ");
14098       used_prefixes |= (prefixes & PREFIX_DATA);
14099       break;
14100     case t_mode:
14101       oappend ("TBYTE PTR ");
14102       break;
14103     case x_mode:
14104     case x_swap_mode:
14105     case evex_x_gscat_mode:
14106     case evex_x_nobcst_mode:
14107     case bw_unit_mode:
14108       if (need_vex)
14109         {
14110           switch (vex.length)
14111             {
14112             case 128:
14113               oappend ("XMMWORD PTR ");
14114               break;
14115             case 256:
14116               oappend ("YMMWORD PTR ");
14117               break;
14118             case 512:
14119               oappend ("ZMMWORD PTR ");
14120               break;
14121             default:
14122               abort ();
14123             }
14124         }
14125       else
14126         oappend ("XMMWORD PTR ");
14127       break;
14128     case xmm_mode:
14129       oappend ("XMMWORD PTR ");
14130       break;
14131     case ymm_mode:
14132       oappend ("YMMWORD PTR ");
14133       break;
14134     case xmmq_mode:
14135     case evex_half_bcst_xmmq_mode:
14136       if (!need_vex)
14137         abort ();
14138
14139       switch (vex.length)
14140         {
14141         case 128:
14142           oappend ("QWORD PTR ");
14143           break;
14144         case 256:
14145           oappend ("XMMWORD PTR ");
14146           break;
14147         case 512:
14148           oappend ("YMMWORD PTR ");
14149           break;
14150         default:
14151           abort ();
14152         }
14153       break;
14154     case xmm_mb_mode:
14155       if (!need_vex)
14156         abort ();
14157
14158       switch (vex.length)
14159         {
14160         case 128:
14161         case 256:
14162         case 512:
14163           oappend ("BYTE PTR ");
14164           break;
14165         default:
14166           abort ();
14167         }
14168       break;
14169     case xmm_mw_mode:
14170       if (!need_vex)
14171         abort ();
14172
14173       switch (vex.length)
14174         {
14175         case 128:
14176         case 256:
14177         case 512:
14178           oappend ("WORD PTR ");
14179           break;
14180         default:
14181           abort ();
14182         }
14183       break;
14184     case xmm_md_mode:
14185       if (!need_vex)
14186         abort ();
14187
14188       switch (vex.length)
14189         {
14190         case 128:
14191         case 256:
14192         case 512:
14193           oappend ("DWORD PTR ");
14194           break;
14195         default:
14196           abort ();
14197         }
14198       break;
14199     case xmm_mq_mode:
14200       if (!need_vex)
14201         abort ();
14202
14203       switch (vex.length)
14204         {
14205         case 128:
14206         case 256:
14207         case 512:
14208           oappend ("QWORD PTR ");
14209           break;
14210         default:
14211           abort ();
14212         }
14213       break;
14214     case xmmdw_mode:
14215       if (!need_vex)
14216         abort ();
14217
14218       switch (vex.length)
14219         {
14220         case 128:
14221           oappend ("WORD PTR ");
14222           break;
14223         case 256:
14224           oappend ("DWORD PTR ");
14225           break;
14226         case 512:
14227           oappend ("QWORD PTR ");
14228           break;
14229         default:
14230           abort ();
14231         }
14232       break;
14233     case xmmqd_mode:
14234       if (!need_vex)
14235         abort ();
14236
14237       switch (vex.length)
14238         {
14239         case 128:
14240           oappend ("DWORD PTR ");
14241           break;
14242         case 256:
14243           oappend ("QWORD PTR ");
14244           break;
14245         case 512:
14246           oappend ("XMMWORD PTR ");
14247           break;
14248         default:
14249           abort ();
14250         }
14251       break;
14252     case ymmq_mode:
14253       if (!need_vex)
14254         abort ();
14255
14256       switch (vex.length)
14257         {
14258         case 128:
14259           oappend ("QWORD PTR ");
14260           break;
14261         case 256:
14262           oappend ("YMMWORD PTR ");
14263           break;
14264         case 512:
14265           oappend ("ZMMWORD PTR ");
14266           break;
14267         default:
14268           abort ();
14269         }
14270       break;
14271     case ymmxmm_mode:
14272       if (!need_vex)
14273         abort ();
14274
14275       switch (vex.length)
14276         {
14277         case 128:
14278         case 256:
14279           oappend ("XMMWORD PTR ");
14280           break;
14281         default:
14282           abort ();
14283         }
14284       break;
14285     case o_mode:
14286       oappend ("OWORD PTR ");
14287       break;
14288     case vex_scalar_w_dq_mode:
14289       if (!need_vex)
14290         abort ();
14291
14292       if (vex.w)
14293         oappend ("QWORD PTR ");
14294       else
14295         oappend ("DWORD PTR ");
14296       break;
14297     case vex_vsib_d_w_dq_mode:
14298     case vex_vsib_q_w_dq_mode:
14299       if (!need_vex)
14300         abort ();
14301
14302       if (!vex.evex)
14303         {
14304           if (vex.w)
14305             oappend ("QWORD PTR ");
14306           else
14307             oappend ("DWORD PTR ");
14308         }
14309       else
14310         {
14311           switch (vex.length)
14312             {
14313             case 128:
14314               oappend ("XMMWORD PTR ");
14315               break;
14316             case 256:
14317               oappend ("YMMWORD PTR ");
14318               break;
14319             case 512:
14320               oappend ("ZMMWORD PTR ");
14321               break;
14322             default:
14323               abort ();
14324             }
14325         }
14326       break;
14327     case vex_vsib_q_w_d_mode:
14328     case vex_vsib_d_w_d_mode:
14329       if (!need_vex || !vex.evex)
14330         abort ();
14331
14332       switch (vex.length)
14333         {
14334         case 128:
14335           oappend ("QWORD PTR ");
14336           break;
14337         case 256:
14338           oappend ("XMMWORD PTR ");
14339           break;
14340         case 512:
14341           oappend ("YMMWORD PTR ");
14342           break;
14343         default:
14344           abort ();
14345         }
14346
14347       break;
14348     case mask_bd_mode:
14349       if (!need_vex || vex.length != 128)
14350         abort ();
14351       if (vex.w)
14352         oappend ("DWORD PTR ");
14353       else
14354         oappend ("BYTE PTR ");
14355       break;
14356     case mask_mode:
14357       if (!need_vex)
14358         abort ();
14359       if (vex.w)
14360         oappend ("QWORD PTR ");
14361       else
14362         oappend ("WORD PTR ");
14363       break;
14364     case v_bnd_mode:
14365     case v_bndmk_mode:
14366     default:
14367       break;
14368     }
14369 }
14370
14371 static void
14372 OP_E_register (int bytemode, int sizeflag)
14373 {
14374   int reg = modrm.rm;
14375   const char **names;
14376
14377   USED_REX (REX_B);
14378   if ((rex & REX_B))
14379     reg += 8;
14380
14381   if ((sizeflag & SUFFIX_ALWAYS)
14382       && (bytemode == b_swap_mode
14383           || bytemode == bnd_swap_mode
14384           || bytemode == v_swap_mode))
14385     swap_operand ();
14386
14387   switch (bytemode)
14388     {
14389     case b_mode:
14390     case b_swap_mode:
14391       if (reg & 4)
14392         USED_REX (0);
14393       if (rex)
14394         names = names8rex;
14395       else
14396         names = names8;
14397       break;
14398     case w_mode:
14399       names = names16;
14400       break;
14401     case d_mode:
14402     case dw_mode:
14403     case db_mode:
14404       names = names32;
14405       break;
14406     case q_mode:
14407       names = names64;
14408       break;
14409     case m_mode:
14410     case v_bnd_mode:
14411       names = address_mode == mode_64bit ? names64 : names32;
14412       break;
14413     case bnd_mode:
14414     case bnd_swap_mode:
14415       if (reg > 0x3)
14416         {
14417           oappend ("(bad)");
14418           return;
14419         }
14420       names = names_bnd;
14421       break;
14422     case indir_v_mode:
14423       if (address_mode == mode_64bit && isa64 == intel64)
14424         {
14425           names = names64;
14426           break;
14427         }
14428       /* Fall through.  */
14429     case stack_v_mode:
14430       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14431         {
14432           names = names64;
14433           break;
14434         }
14435       bytemode = v_mode;
14436       /* Fall through.  */
14437     case v_mode:
14438     case v_swap_mode:
14439     case dq_mode:
14440     case dqb_mode:
14441     case dqd_mode:
14442     case dqw_mode:
14443       USED_REX (REX_W);
14444       if (rex & REX_W)
14445         names = names64;
14446       else
14447         {
14448           if ((sizeflag & DFLAG)
14449               || (bytemode != v_mode
14450                   && bytemode != v_swap_mode))
14451             names = names32;
14452           else
14453             names = names16;
14454           used_prefixes |= (prefixes & PREFIX_DATA);
14455         }
14456       break;
14457     case movsxd_mode:
14458       if (!(sizeflag & DFLAG) && isa64 == intel64)
14459         names = names16;
14460       else
14461         names = names32;
14462       used_prefixes |= (prefixes & PREFIX_DATA);
14463       break;
14464     case va_mode:
14465       names = (address_mode == mode_64bit
14466                ? names64 : names32);
14467       if (!(prefixes & PREFIX_ADDR))
14468         names = (address_mode == mode_16bit
14469                      ? names16 : names);
14470       else
14471         {
14472           /* Remove "addr16/addr32".  */
14473           all_prefixes[last_addr_prefix] = 0;
14474           names = (address_mode != mode_32bit
14475                        ? names32 : names16);
14476           used_prefixes |= PREFIX_ADDR;
14477         }
14478       break;
14479     case mask_bd_mode:
14480     case mask_mode:
14481       if (reg > 0x7)
14482         {
14483           oappend ("(bad)");
14484           return;
14485         }
14486       names = names_mask;
14487       break;
14488     case 0:
14489       return;
14490     default:
14491       oappend (INTERNAL_DISASSEMBLER_ERROR);
14492       return;
14493     }
14494   oappend (names[reg]);
14495 }
14496
14497 static void
14498 OP_E_memory (int bytemode, int sizeflag)
14499 {
14500   bfd_vma disp = 0;
14501   int add = (rex & REX_B) ? 8 : 0;
14502   int riprel = 0;
14503   int shift;
14504
14505   if (vex.evex)
14506     {
14507       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
14508       if (vex.b
14509           && bytemode != x_mode
14510           && bytemode != xmmq_mode
14511           && bytemode != evex_half_bcst_xmmq_mode)
14512         {
14513           BadOp ();
14514           return;
14515         }
14516       switch (bytemode)
14517         {
14518         case dqw_mode:
14519         case dw_mode:
14520         case xmm_mw_mode:
14521           shift = 1;
14522           break;
14523         case dqb_mode:
14524         case db_mode:
14525         case xmm_mb_mode:
14526           shift = 0;
14527           break;
14528         case dq_mode:
14529           if (address_mode != mode_64bit)
14530             {
14531         case dqd_mode:
14532         case xmm_md_mode:
14533         case d_mode:
14534         case d_swap_mode:
14535         case d_scalar_swap_mode:
14536               shift = 2;
14537               break;
14538             }
14539             /* fall through */
14540         case vex_scalar_w_dq_mode:
14541         case vex_vsib_d_w_dq_mode:
14542         case vex_vsib_d_w_d_mode:
14543         case vex_vsib_q_w_dq_mode:
14544         case vex_vsib_q_w_d_mode:
14545         case evex_x_gscat_mode:
14546           shift = vex.w ? 3 : 2;
14547           break;
14548         case x_mode:
14549         case evex_half_bcst_xmmq_mode:
14550         case xmmq_mode:
14551           if (vex.b)
14552             {
14553               shift = vex.w ? 3 : 2;
14554               break;
14555             }
14556           /* Fall through.  */
14557         case xmmqd_mode:
14558         case xmmdw_mode:
14559         case ymmq_mode:
14560         case evex_x_nobcst_mode:
14561         case x_swap_mode:
14562           switch (vex.length)
14563             {
14564             case 128:
14565               shift = 4;
14566               break;
14567             case 256:
14568               shift = 5;
14569               break;
14570             case 512:
14571               shift = 6;
14572               break;
14573             default:
14574               abort ();
14575             }
14576           /* Make necessary corrections to shift for modes that need it.  */
14577           if (bytemode == xmmq_mode
14578               || bytemode == evex_half_bcst_xmmq_mode
14579               || (bytemode == ymmq_mode && vex.length == 128))
14580             shift -= 1;
14581           else if (bytemode == xmmqd_mode)
14582             shift -= 2;
14583           else if (bytemode == xmmdw_mode)
14584             shift -= 3;
14585           break;
14586         case ymm_mode:
14587           shift = 5;
14588           break;
14589         case xmm_mode:
14590           shift = 4;
14591           break;
14592         case xmm_mq_mode:
14593         case q_mode:
14594         case q_swap_mode:
14595         case q_scalar_swap_mode:
14596           shift = 3;
14597           break;
14598         case bw_unit_mode:
14599           shift = vex.w ? 1 : 0;
14600           break;
14601         default:
14602           abort ();
14603         }
14604     }
14605   else
14606     shift = 0;
14607
14608   USED_REX (REX_B);
14609   if (intel_syntax)
14610     intel_operand_size (bytemode, sizeflag);
14611   append_seg ();
14612
14613   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14614     {
14615       /* 32/64 bit address mode */
14616       int havedisp;
14617       int havesib;
14618       int havebase;
14619       int haveindex;
14620       int needindex;
14621       int needaddr32;
14622       int base, rbase;
14623       int vindex = 0;
14624       int scale = 0;
14625       int addr32flag = !((sizeflag & AFLAG)
14626                          || bytemode == v_bnd_mode
14627                          || bytemode == v_bndmk_mode
14628                          || bytemode == bnd_mode
14629                          || bytemode == bnd_swap_mode);
14630       const char **indexes64 = names64;
14631       const char **indexes32 = names32;
14632
14633       havesib = 0;
14634       havebase = 1;
14635       haveindex = 0;
14636       base = modrm.rm;
14637
14638       if (base == 4)
14639         {
14640           havesib = 1;
14641           vindex = sib.index;
14642           USED_REX (REX_X);
14643           if (rex & REX_X)
14644             vindex += 8;
14645           switch (bytemode)
14646             {
14647             case vex_vsib_d_w_dq_mode:
14648             case vex_vsib_d_w_d_mode:
14649             case vex_vsib_q_w_dq_mode:
14650             case vex_vsib_q_w_d_mode:
14651               if (!need_vex)
14652                 abort ();
14653               if (vex.evex)
14654                 {
14655                   if (!vex.v)
14656                     vindex += 16;
14657                 }
14658
14659               haveindex = 1;
14660               switch (vex.length)
14661                 {
14662                 case 128:
14663                   indexes64 = indexes32 = names_xmm;
14664                   break;
14665                 case 256:
14666                   if (!vex.w
14667                       || bytemode == vex_vsib_q_w_dq_mode
14668                       || bytemode == vex_vsib_q_w_d_mode)
14669                     indexes64 = indexes32 = names_ymm;
14670                   else
14671                     indexes64 = indexes32 = names_xmm;
14672                   break;
14673                 case 512:
14674                   if (!vex.w
14675                       || bytemode == vex_vsib_q_w_dq_mode
14676                       || bytemode == vex_vsib_q_w_d_mode)
14677                     indexes64 = indexes32 = names_zmm;
14678                   else
14679                     indexes64 = indexes32 = names_ymm;
14680                   break;
14681                 default:
14682                   abort ();
14683                 }
14684               break;
14685             default:
14686               haveindex = vindex != 4;
14687               break;
14688             }
14689           scale = sib.scale;
14690           base = sib.base;
14691           codep++;
14692         }
14693       else
14694         {
14695           /* mandatory non-vector SIB must have sib */
14696           if (bytemode == vex_sibmem_mode)
14697             {
14698               oappend ("(bad)");
14699               return;
14700             }
14701         }
14702       rbase = base + add;
14703
14704       switch (modrm.mod)
14705         {
14706         case 0:
14707           if (base == 5)
14708             {
14709               havebase = 0;
14710               if (address_mode == mode_64bit && !havesib)
14711                 riprel = 1;
14712               disp = get32s ();
14713               if (riprel && bytemode == v_bndmk_mode)
14714                 {
14715                   oappend ("(bad)");
14716                   return;
14717                 }
14718             }
14719           break;
14720         case 1:
14721           FETCH_DATA (the_info, codep + 1);
14722           disp = *codep++;
14723           if ((disp & 0x80) != 0)
14724             disp -= 0x100;
14725           if (vex.evex && shift > 0)
14726             disp <<= shift;
14727           break;
14728         case 2:
14729           disp = get32s ();
14730           break;
14731         }
14732
14733       needindex = 0;
14734       needaddr32 = 0;
14735       if (havesib
14736           && !havebase
14737           && !haveindex
14738           && address_mode != mode_16bit)
14739         {
14740           if (address_mode == mode_64bit)
14741             {
14742               /* Display eiz instead of addr32.  */
14743               needindex = addr32flag;
14744               needaddr32 = 1;
14745             }
14746           else
14747             {
14748               /* In 32-bit mode, we need index register to tell [offset]
14749                  from [eiz*1 + offset].  */
14750               needindex = 1;
14751             }
14752         }
14753
14754       havedisp = (havebase
14755                   || needindex
14756                   || (havesib && (haveindex || scale != 0)));
14757
14758       if (!intel_syntax)
14759         if (modrm.mod != 0 || base == 5)
14760           {
14761             if (havedisp || riprel)
14762               print_displacement (scratchbuf, disp);
14763             else
14764               print_operand_value (scratchbuf, 1, disp);
14765             oappend (scratchbuf);
14766             if (riprel)
14767               {
14768                 set_op (disp, 1);
14769                 oappend (!addr32flag ? "(%rip)" : "(%eip)");
14770               }
14771           }
14772
14773       if ((havebase || haveindex || needindex || needaddr32 || riprel)
14774           && (address_mode != mode_64bit
14775               || ((bytemode != v_bnd_mode)
14776                   && (bytemode != v_bndmk_mode)
14777                   && (bytemode != bnd_mode)
14778                   && (bytemode != bnd_swap_mode))))
14779         used_prefixes |= PREFIX_ADDR;
14780
14781       if (havedisp || (intel_syntax && riprel))
14782         {
14783           *obufp++ = open_char;
14784           if (intel_syntax && riprel)
14785             {
14786               set_op (disp, 1);
14787               oappend (!addr32flag ? "rip" : "eip");
14788             }
14789           *obufp = '\0';
14790           if (havebase)
14791             oappend (address_mode == mode_64bit && !addr32flag
14792                      ? names64[rbase] : names32[rbase]);
14793           if (havesib)
14794             {
14795               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
14796                  print index to tell base + index from base.  */
14797               if (scale != 0
14798                   || needindex
14799                   || haveindex
14800                   || (havebase && base != ESP_REG_NUM))
14801                 {
14802                   if (!intel_syntax || havebase)
14803                     {
14804                       *obufp++ = separator_char;
14805                       *obufp = '\0';
14806                     }
14807                   if (haveindex)
14808                     oappend (address_mode == mode_64bit && !addr32flag
14809                              ? indexes64[vindex] : indexes32[vindex]);
14810                   else
14811                     oappend (address_mode == mode_64bit && !addr32flag
14812                              ? index64 : index32);
14813
14814                   *obufp++ = scale_char;
14815                   *obufp = '\0';
14816                   sprintf (scratchbuf, "%d", 1 << scale);
14817                   oappend (scratchbuf);
14818                 }
14819             }
14820           if (intel_syntax
14821               && (disp || modrm.mod != 0 || base == 5))
14822             {
14823               if (!havedisp || (bfd_signed_vma) disp >= 0)
14824                 {
14825                   *obufp++ = '+';
14826                   *obufp = '\0';
14827                 }
14828               else if (modrm.mod != 1 && disp != -disp)
14829                 {
14830                   *obufp++ = '-';
14831                   *obufp = '\0';
14832                   disp = - (bfd_signed_vma) disp;
14833                 }
14834
14835               if (havedisp)
14836                 print_displacement (scratchbuf, disp);
14837               else
14838                 print_operand_value (scratchbuf, 1, disp);
14839               oappend (scratchbuf);
14840             }
14841
14842           *obufp++ = close_char;
14843           *obufp = '\0';
14844         }
14845       else if (intel_syntax)
14846         {
14847           if (modrm.mod != 0 || base == 5)
14848             {
14849               if (!active_seg_prefix)
14850                 {
14851                   oappend (names_seg[ds_reg - es_reg]);
14852                   oappend (":");
14853                 }
14854               print_operand_value (scratchbuf, 1, disp);
14855               oappend (scratchbuf);
14856             }
14857         }
14858     }
14859   else if (bytemode == v_bnd_mode
14860            || bytemode == v_bndmk_mode
14861            || bytemode == bnd_mode
14862            || bytemode == bnd_swap_mode)
14863     {
14864       oappend ("(bad)");
14865       return;
14866     }
14867   else
14868     {
14869       /* 16 bit address mode */
14870       used_prefixes |= prefixes & PREFIX_ADDR;
14871       switch (modrm.mod)
14872         {
14873         case 0:
14874           if (modrm.rm == 6)
14875             {
14876               disp = get16 ();
14877               if ((disp & 0x8000) != 0)
14878                 disp -= 0x10000;
14879             }
14880           break;
14881         case 1:
14882           FETCH_DATA (the_info, codep + 1);
14883           disp = *codep++;
14884           if ((disp & 0x80) != 0)
14885             disp -= 0x100;
14886           if (vex.evex && shift > 0)
14887             disp <<= shift;
14888           break;
14889         case 2:
14890           disp = get16 ();
14891           if ((disp & 0x8000) != 0)
14892             disp -= 0x10000;
14893           break;
14894         }
14895
14896       if (!intel_syntax)
14897         if (modrm.mod != 0 || modrm.rm == 6)
14898           {
14899             print_displacement (scratchbuf, disp);
14900             oappend (scratchbuf);
14901           }
14902
14903       if (modrm.mod != 0 || modrm.rm != 6)
14904         {
14905           *obufp++ = open_char;
14906           *obufp = '\0';
14907           oappend (index16[modrm.rm]);
14908           if (intel_syntax
14909               && (disp || modrm.mod != 0 || modrm.rm == 6))
14910             {
14911               if ((bfd_signed_vma) disp >= 0)
14912                 {
14913                   *obufp++ = '+';
14914                   *obufp = '\0';
14915                 }
14916               else if (modrm.mod != 1)
14917                 {
14918                   *obufp++ = '-';
14919                   *obufp = '\0';
14920                   disp = - (bfd_signed_vma) disp;
14921                 }
14922
14923               print_displacement (scratchbuf, disp);
14924               oappend (scratchbuf);
14925             }
14926
14927           *obufp++ = close_char;
14928           *obufp = '\0';
14929         }
14930       else if (intel_syntax)
14931         {
14932           if (!active_seg_prefix)
14933             {
14934               oappend (names_seg[ds_reg - es_reg]);
14935               oappend (":");
14936             }
14937           print_operand_value (scratchbuf, 1, disp & 0xffff);
14938           oappend (scratchbuf);
14939         }
14940     }
14941   if (vex.evex && vex.b
14942       && (bytemode == x_mode
14943           || bytemode == xmmq_mode
14944           || bytemode == evex_half_bcst_xmmq_mode))
14945     {
14946       if (vex.w
14947           || bytemode == xmmq_mode
14948           || bytemode == evex_half_bcst_xmmq_mode)
14949         {
14950           switch (vex.length)
14951             {
14952             case 128:
14953               oappend ("{1to2}");
14954               break;
14955             case 256:
14956               oappend ("{1to4}");
14957               break;
14958             case 512:
14959               oappend ("{1to8}");
14960               break;
14961             default:
14962               abort ();
14963             }
14964         }
14965       else
14966         {
14967           switch (vex.length)
14968             {
14969             case 128:
14970               oappend ("{1to4}");
14971               break;
14972             case 256:
14973               oappend ("{1to8}");
14974               break;
14975             case 512:
14976               oappend ("{1to16}");
14977               break;
14978             default:
14979               abort ();
14980             }
14981         }
14982     }
14983 }
14984
14985 static void
14986 OP_E (int bytemode, int sizeflag)
14987 {
14988   /* Skip mod/rm byte.  */
14989   MODRM_CHECK;
14990   codep++;
14991
14992   if (modrm.mod == 3)
14993     OP_E_register (bytemode, sizeflag);
14994   else
14995     OP_E_memory (bytemode, sizeflag);
14996 }
14997
14998 static void
14999 OP_G (int bytemode, int sizeflag)
15000 {
15001   int add = 0;
15002   const char **names;
15003   USED_REX (REX_R);
15004   if (rex & REX_R)
15005     add += 8;
15006   switch (bytemode)
15007     {
15008     case b_mode:
15009       if (modrm.reg & 4)
15010         USED_REX (0);
15011       if (rex)
15012         oappend (names8rex[modrm.reg + add]);
15013       else
15014         oappend (names8[modrm.reg + add]);
15015       break;
15016     case w_mode:
15017       oappend (names16[modrm.reg + add]);
15018       break;
15019     case d_mode:
15020     case db_mode:
15021     case dw_mode:
15022       oappend (names32[modrm.reg + add]);
15023       break;
15024     case q_mode:
15025       oappend (names64[modrm.reg + add]);
15026       break;
15027     case bnd_mode:
15028       if (modrm.reg > 0x3)
15029         {
15030           oappend ("(bad)");
15031           return;
15032         }
15033       oappend (names_bnd[modrm.reg]);
15034       break;
15035     case v_mode:
15036     case dq_mode:
15037     case dqb_mode:
15038     case dqd_mode:
15039     case dqw_mode:
15040     case movsxd_mode:
15041       USED_REX (REX_W);
15042       if (rex & REX_W)
15043         oappend (names64[modrm.reg + add]);
15044       else
15045         {
15046           if ((sizeflag & DFLAG)
15047               || (bytemode != v_mode && bytemode != movsxd_mode))
15048             oappend (names32[modrm.reg + add]);
15049           else
15050             oappend (names16[modrm.reg + add]);
15051           used_prefixes |= (prefixes & PREFIX_DATA);
15052         }
15053       break;
15054     case va_mode:
15055       names = (address_mode == mode_64bit
15056                ? names64 : names32);
15057       if (!(prefixes & PREFIX_ADDR))
15058         {
15059           if (address_mode == mode_16bit)
15060             names = names16;
15061         }
15062       else
15063         {
15064           /* Remove "addr16/addr32".  */
15065           all_prefixes[last_addr_prefix] = 0;
15066           names = (address_mode != mode_32bit
15067                        ? names32 : names16);
15068           used_prefixes |= PREFIX_ADDR;
15069         }
15070       oappend (names[modrm.reg + add]);
15071       break;
15072     case m_mode:
15073       if (address_mode == mode_64bit)
15074         oappend (names64[modrm.reg + add]);
15075       else
15076         oappend (names32[modrm.reg + add]);
15077       break;
15078     case mask_bd_mode:
15079     case mask_mode:
15080       if ((modrm.reg + add) > 0x7)
15081         {
15082           oappend ("(bad)");
15083           return;
15084         }
15085       oappend (names_mask[modrm.reg + add]);
15086       break;
15087     default:
15088       oappend (INTERNAL_DISASSEMBLER_ERROR);
15089       break;
15090     }
15091 }
15092
15093 static bfd_vma
15094 get64 (void)
15095 {
15096   bfd_vma x;
15097 #ifdef BFD64
15098   unsigned int a;
15099   unsigned int b;
15100
15101   FETCH_DATA (the_info, codep + 8);
15102   a = *codep++ & 0xff;
15103   a |= (*codep++ & 0xff) << 8;
15104   a |= (*codep++ & 0xff) << 16;
15105   a |= (*codep++ & 0xffu) << 24;
15106   b = *codep++ & 0xff;
15107   b |= (*codep++ & 0xff) << 8;
15108   b |= (*codep++ & 0xff) << 16;
15109   b |= (*codep++ & 0xffu) << 24;
15110   x = a + ((bfd_vma) b << 32);
15111 #else
15112   abort ();
15113   x = 0;
15114 #endif
15115   return x;
15116 }
15117
15118 static bfd_signed_vma
15119 get32 (void)
15120 {
15121   bfd_signed_vma x = 0;
15122
15123   FETCH_DATA (the_info, codep + 4);
15124   x = *codep++ & (bfd_signed_vma) 0xff;
15125   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15126   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15127   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15128   return x;
15129 }
15130
15131 static bfd_signed_vma
15132 get32s (void)
15133 {
15134   bfd_signed_vma x = 0;
15135
15136   FETCH_DATA (the_info, codep + 4);
15137   x = *codep++ & (bfd_signed_vma) 0xff;
15138   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15139   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15140   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15141
15142   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
15143
15144   return x;
15145 }
15146
15147 static int
15148 get16 (void)
15149 {
15150   int x = 0;
15151
15152   FETCH_DATA (the_info, codep + 2);
15153   x = *codep++ & 0xff;
15154   x |= (*codep++ & 0xff) << 8;
15155   return x;
15156 }
15157
15158 static void
15159 set_op (bfd_vma op, int riprel)
15160 {
15161   op_index[op_ad] = op_ad;
15162   if (address_mode == mode_64bit)
15163     {
15164       op_address[op_ad] = op;
15165       op_riprel[op_ad] = riprel;
15166     }
15167   else
15168     {
15169       /* Mask to get a 32-bit address.  */
15170       op_address[op_ad] = op & 0xffffffff;
15171       op_riprel[op_ad] = riprel & 0xffffffff;
15172     }
15173 }
15174
15175 static void
15176 OP_REG (int code, int sizeflag)
15177 {
15178   const char *s;
15179   int add;
15180
15181   switch (code)
15182     {
15183     case es_reg: case ss_reg: case cs_reg:
15184     case ds_reg: case fs_reg: case gs_reg:
15185       oappend (names_seg[code - es_reg]);
15186       return;
15187     }
15188
15189   USED_REX (REX_B);
15190   if (rex & REX_B)
15191     add = 8;
15192   else
15193     add = 0;
15194
15195   switch (code)
15196     {
15197     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15198     case sp_reg: case bp_reg: case si_reg: case di_reg:
15199       s = names16[code - ax_reg + add];
15200       break;
15201     case ah_reg: case ch_reg: case dh_reg: case bh_reg:
15202       USED_REX (0);
15203       /* Fall through.  */
15204     case al_reg: case cl_reg: case dl_reg: case bl_reg:
15205       if (rex)
15206         s = names8rex[code - al_reg + add];
15207       else
15208         s = names8[code - al_reg];
15209       break;
15210     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
15211     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
15212       if (address_mode == mode_64bit
15213           && ((sizeflag & DFLAG) || (rex & REX_W)))
15214         {
15215           s = names64[code - rAX_reg + add];
15216           break;
15217         }
15218       code += eAX_reg - rAX_reg;
15219       /* Fall through.  */
15220     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15221     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15222       USED_REX (REX_W);
15223       if (rex & REX_W)
15224         s = names64[code - eAX_reg + add];
15225       else
15226         {
15227           if (sizeflag & DFLAG)
15228             s = names32[code - eAX_reg + add];
15229           else
15230             s = names16[code - eAX_reg + add];
15231           used_prefixes |= (prefixes & PREFIX_DATA);
15232         }
15233       break;
15234     default:
15235       s = INTERNAL_DISASSEMBLER_ERROR;
15236       break;
15237     }
15238   oappend (s);
15239 }
15240
15241 static void
15242 OP_IMREG (int code, int sizeflag)
15243 {
15244   const char *s;
15245
15246   switch (code)
15247     {
15248     case indir_dx_reg:
15249       if (intel_syntax)
15250         s = "dx";
15251       else
15252         s = "(%dx)";
15253       break;
15254     case al_reg: case cl_reg:
15255       s = names8[code - al_reg];
15256       break;
15257     case eAX_reg:
15258       USED_REX (REX_W);
15259       if (rex & REX_W)
15260         {
15261           s = *names64;
15262           break;
15263         }
15264       /* Fall through.  */
15265     case z_mode_ax_reg:
15266       if ((rex & REX_W) || (sizeflag & DFLAG))
15267         s = *names32;
15268       else
15269         s = *names16;
15270       if (!(rex & REX_W))
15271         used_prefixes |= (prefixes & PREFIX_DATA);
15272       break;
15273     default:
15274       s = INTERNAL_DISASSEMBLER_ERROR;
15275       break;
15276     }
15277   oappend (s);
15278 }
15279
15280 static void
15281 OP_I (int bytemode, int sizeflag)
15282 {
15283   bfd_signed_vma op;
15284   bfd_signed_vma mask = -1;
15285
15286   switch (bytemode)
15287     {
15288     case b_mode:
15289       FETCH_DATA (the_info, codep + 1);
15290       op = *codep++;
15291       mask = 0xff;
15292       break;
15293     case v_mode:
15294       USED_REX (REX_W);
15295       if (rex & REX_W)
15296         op = get32s ();
15297       else
15298         {
15299           if (sizeflag & DFLAG)
15300             {
15301               op = get32 ();
15302               mask = 0xffffffff;
15303             }
15304           else
15305             {
15306               op = get16 ();
15307               mask = 0xfffff;
15308             }
15309           used_prefixes |= (prefixes & PREFIX_DATA);
15310         }
15311       break;
15312     case d_mode:
15313       mask = 0xffffffff;
15314       op = get32 ();
15315       break;
15316     case w_mode:
15317       mask = 0xfffff;
15318       op = get16 ();
15319       break;
15320     case const_1_mode:
15321       if (intel_syntax)
15322         oappend ("1");
15323       return;
15324     default:
15325       oappend (INTERNAL_DISASSEMBLER_ERROR);
15326       return;
15327     }
15328
15329   op &= mask;
15330   scratchbuf[0] = '$';
15331   print_operand_value (scratchbuf + 1, 1, op);
15332   oappend_maybe_intel (scratchbuf);
15333   scratchbuf[0] = '\0';
15334 }
15335
15336 static void
15337 OP_I64 (int bytemode, int sizeflag)
15338 {
15339   if (bytemode != v_mode || address_mode != mode_64bit || !(rex & REX_W))
15340     {
15341       OP_I (bytemode, sizeflag);
15342       return;
15343     }
15344
15345   USED_REX (REX_W);
15346
15347   scratchbuf[0] = '$';
15348   print_operand_value (scratchbuf + 1, 1, get64 ());
15349   oappend_maybe_intel (scratchbuf);
15350   scratchbuf[0] = '\0';
15351 }
15352
15353 static void
15354 OP_sI (int bytemode, int sizeflag)
15355 {
15356   bfd_signed_vma op;
15357
15358   switch (bytemode)
15359     {
15360     case b_mode:
15361     case b_T_mode:
15362       FETCH_DATA (the_info, codep + 1);
15363       op = *codep++;
15364       if ((op & 0x80) != 0)
15365         op -= 0x100;
15366       if (bytemode == b_T_mode)
15367         {
15368           if (address_mode != mode_64bit
15369               || !((sizeflag & DFLAG) || (rex & REX_W)))
15370             {
15371               /* The operand-size prefix is overridden by a REX prefix.  */
15372               if ((sizeflag & DFLAG) || (rex & REX_W))
15373                 op &= 0xffffffff;
15374               else
15375                 op &= 0xffff;
15376           }
15377         }
15378       else
15379         {
15380           if (!(rex & REX_W))
15381             {
15382               if (sizeflag & DFLAG)
15383                 op &= 0xffffffff;
15384               else
15385                 op &= 0xffff;
15386             }
15387         }
15388       break;
15389     case v_mode:
15390       /* The operand-size prefix is overridden by a REX prefix.  */
15391       if ((sizeflag & DFLAG) || (rex & REX_W))
15392         op = get32s ();
15393       else
15394         op = get16 ();
15395       break;
15396     default:
15397       oappend (INTERNAL_DISASSEMBLER_ERROR);
15398       return;
15399     }
15400
15401   scratchbuf[0] = '$';
15402   print_operand_value (scratchbuf + 1, 1, op);
15403   oappend_maybe_intel (scratchbuf);
15404 }
15405
15406 static void
15407 OP_J (int bytemode, int sizeflag)
15408 {
15409   bfd_vma disp;
15410   bfd_vma mask = -1;
15411   bfd_vma segment = 0;
15412
15413   switch (bytemode)
15414     {
15415     case b_mode:
15416       FETCH_DATA (the_info, codep + 1);
15417       disp = *codep++;
15418       if ((disp & 0x80) != 0)
15419         disp -= 0x100;
15420       break;
15421     case v_mode:
15422       if (isa64 != intel64)
15423     case dqw_mode:
15424         USED_REX (REX_W);
15425       if ((sizeflag & DFLAG)
15426           || (address_mode == mode_64bit
15427               && ((isa64 == intel64 && bytemode != dqw_mode)
15428                   || (rex & REX_W))))
15429         disp = get32s ();
15430       else
15431         {
15432           disp = get16 ();
15433           if ((disp & 0x8000) != 0)
15434             disp -= 0x10000;
15435           /* In 16bit mode, address is wrapped around at 64k within
15436              the same segment.  Otherwise, a data16 prefix on a jump
15437              instruction means that the pc is masked to 16 bits after
15438              the displacement is added!  */
15439           mask = 0xffff;
15440           if ((prefixes & PREFIX_DATA) == 0)
15441             segment = ((start_pc + (codep - start_codep))
15442                        & ~((bfd_vma) 0xffff));
15443         }
15444       if (address_mode != mode_64bit
15445           || (isa64 != intel64 && !(rex & REX_W)))
15446         used_prefixes |= (prefixes & PREFIX_DATA);
15447       break;
15448     default:
15449       oappend (INTERNAL_DISASSEMBLER_ERROR);
15450       return;
15451     }
15452   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
15453   set_op (disp, 0);
15454   print_operand_value (scratchbuf, 1, disp);
15455   oappend (scratchbuf);
15456 }
15457
15458 static void
15459 OP_SEG (int bytemode, int sizeflag)
15460 {
15461   if (bytemode == w_mode)
15462     oappend (names_seg[modrm.reg]);
15463   else
15464     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
15465 }
15466
15467 static void
15468 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
15469 {
15470   int seg, offset;
15471
15472   if (sizeflag & DFLAG)
15473     {
15474       offset = get32 ();
15475       seg = get16 ();
15476     }
15477   else
15478     {
15479       offset = get16 ();
15480       seg = get16 ();
15481     }
15482   used_prefixes |= (prefixes & PREFIX_DATA);
15483   if (intel_syntax)
15484     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
15485   else
15486     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
15487   oappend (scratchbuf);
15488 }
15489
15490 static void
15491 OP_OFF (int bytemode, int sizeflag)
15492 {
15493   bfd_vma off;
15494
15495   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15496     intel_operand_size (bytemode, sizeflag);
15497   append_seg ();
15498
15499   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15500     off = get32 ();
15501   else
15502     off = get16 ();
15503
15504   if (intel_syntax)
15505     {
15506       if (!active_seg_prefix)
15507         {
15508           oappend (names_seg[ds_reg - es_reg]);
15509           oappend (":");
15510         }
15511     }
15512   print_operand_value (scratchbuf, 1, off);
15513   oappend (scratchbuf);
15514 }
15515
15516 static void
15517 OP_OFF64 (int bytemode, int sizeflag)
15518 {
15519   bfd_vma off;
15520
15521   if (address_mode != mode_64bit
15522       || (prefixes & PREFIX_ADDR))
15523     {
15524       OP_OFF (bytemode, sizeflag);
15525       return;
15526     }
15527
15528   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15529     intel_operand_size (bytemode, sizeflag);
15530   append_seg ();
15531
15532   off = get64 ();
15533
15534   if (intel_syntax)
15535     {
15536       if (!active_seg_prefix)
15537         {
15538           oappend (names_seg[ds_reg - es_reg]);
15539           oappend (":");
15540         }
15541     }
15542   print_operand_value (scratchbuf, 1, off);
15543   oappend (scratchbuf);
15544 }
15545
15546 static void
15547 ptr_reg (int code, int sizeflag)
15548 {
15549   const char *s;
15550
15551   *obufp++ = open_char;
15552   used_prefixes |= (prefixes & PREFIX_ADDR);
15553   if (address_mode == mode_64bit)
15554     {
15555       if (!(sizeflag & AFLAG))
15556         s = names32[code - eAX_reg];
15557       else
15558         s = names64[code - eAX_reg];
15559     }
15560   else if (sizeflag & AFLAG)
15561     s = names32[code - eAX_reg];
15562   else
15563     s = names16[code - eAX_reg];
15564   oappend (s);
15565   *obufp++ = close_char;
15566   *obufp = 0;
15567 }
15568
15569 static void
15570 OP_ESreg (int code, int sizeflag)
15571 {
15572   if (intel_syntax)
15573     {
15574       switch (codep[-1])
15575         {
15576         case 0x6d:      /* insw/insl */
15577           intel_operand_size (z_mode, sizeflag);
15578           break;
15579         case 0xa5:      /* movsw/movsl/movsq */
15580         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15581         case 0xab:      /* stosw/stosl */
15582         case 0xaf:      /* scasw/scasl */
15583           intel_operand_size (v_mode, sizeflag);
15584           break;
15585         default:
15586           intel_operand_size (b_mode, sizeflag);
15587         }
15588     }
15589   oappend_maybe_intel ("%es:");
15590   ptr_reg (code, sizeflag);
15591 }
15592
15593 static void
15594 OP_DSreg (int code, int sizeflag)
15595 {
15596   if (intel_syntax)
15597     {
15598       switch (codep[-1])
15599         {
15600         case 0x6f:      /* outsw/outsl */
15601           intel_operand_size (z_mode, sizeflag);
15602           break;
15603         case 0xa5:      /* movsw/movsl/movsq */
15604         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15605         case 0xad:      /* lodsw/lodsl/lodsq */
15606           intel_operand_size (v_mode, sizeflag);
15607           break;
15608         default:
15609           intel_operand_size (b_mode, sizeflag);
15610         }
15611     }
15612   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15613      default segment register DS is printed.  */
15614   if (!active_seg_prefix)
15615     active_seg_prefix = PREFIX_DS;
15616   append_seg ();
15617   ptr_reg (code, sizeflag);
15618 }
15619
15620 static void
15621 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15622 {
15623   int add;
15624   if (rex & REX_R)
15625     {
15626       USED_REX (REX_R);
15627       add = 8;
15628     }
15629   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
15630     {
15631       all_prefixes[last_lock_prefix] = 0;
15632       used_prefixes |= PREFIX_LOCK;
15633       add = 8;
15634     }
15635   else
15636     add = 0;
15637   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
15638   oappend_maybe_intel (scratchbuf);
15639 }
15640
15641 static void
15642 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15643 {
15644   int add;
15645   USED_REX (REX_R);
15646   if (rex & REX_R)
15647     add = 8;
15648   else
15649     add = 0;
15650   if (intel_syntax)
15651     sprintf (scratchbuf, "db%d", modrm.reg + add);
15652   else
15653     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
15654   oappend (scratchbuf);
15655 }
15656
15657 static void
15658 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15659 {
15660   sprintf (scratchbuf, "%%tr%d", modrm.reg);
15661   oappend_maybe_intel (scratchbuf);
15662 }
15663
15664 static void
15665 OP_R (int bytemode, int sizeflag)
15666 {
15667   /* Skip mod/rm byte.  */
15668   MODRM_CHECK;
15669   codep++;
15670   OP_E_register (bytemode, sizeflag);
15671 }
15672
15673 static void
15674 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15675 {
15676   int reg = modrm.reg;
15677   const char **names;
15678
15679   used_prefixes |= (prefixes & PREFIX_DATA);
15680   if (prefixes & PREFIX_DATA)
15681     {
15682       names = names_xmm;
15683       USED_REX (REX_R);
15684       if (rex & REX_R)
15685         reg += 8;
15686     }
15687   else
15688     names = names_mm;
15689   oappend (names[reg]);
15690 }
15691
15692 static void
15693 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15694 {
15695   int reg = modrm.reg;
15696   const char **names;
15697
15698   USED_REX (REX_R);
15699   if (rex & REX_R)
15700     reg += 8;
15701   if (vex.evex)
15702     {
15703       if (!vex.r)
15704         reg += 16;
15705     }
15706
15707   if (need_vex
15708       && bytemode != xmm_mode
15709       && bytemode != xmmq_mode
15710       && bytemode != evex_half_bcst_xmmq_mode
15711       && bytemode != ymm_mode
15712       && bytemode != tmm_mode
15713       && bytemode != scalar_mode)
15714     {
15715       switch (vex.length)
15716         {
15717         case 128:
15718           names = names_xmm;
15719           break;
15720         case 256:
15721           if (vex.w
15722               || (bytemode != vex_vsib_q_w_dq_mode
15723                   && bytemode != vex_vsib_q_w_d_mode))
15724             names = names_ymm;
15725           else
15726             names = names_xmm;
15727           break;
15728         case 512:
15729           names = names_zmm;
15730           break;
15731         default:
15732           abort ();
15733         }
15734     }
15735   else if (bytemode == xmmq_mode
15736            || bytemode == evex_half_bcst_xmmq_mode)
15737     {
15738       switch (vex.length)
15739         {
15740         case 128:
15741         case 256:
15742           names = names_xmm;
15743           break;
15744         case 512:
15745           names = names_ymm;
15746           break;
15747         default:
15748           abort ();
15749         }
15750     }
15751   else if (bytemode == tmm_mode)
15752     {
15753       modrm.reg = reg;
15754       if (reg >= 8)
15755         {
15756           oappend ("(bad)");
15757           return;
15758         }
15759       names = names_tmm;
15760     }
15761   else if (bytemode == ymm_mode)
15762     names = names_ymm;
15763   else
15764     names = names_xmm;
15765   oappend (names[reg]);
15766 }
15767
15768 static void
15769 OP_EM (int bytemode, int sizeflag)
15770 {
15771   int reg;
15772   const char **names;
15773
15774   if (modrm.mod != 3)
15775     {
15776       if (intel_syntax
15777           && (bytemode == v_mode || bytemode == v_swap_mode))
15778         {
15779           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15780           used_prefixes |= (prefixes & PREFIX_DATA);
15781         }
15782       OP_E (bytemode, sizeflag);
15783       return;
15784     }
15785
15786   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
15787     swap_operand ();
15788
15789   /* Skip mod/rm byte.  */
15790   MODRM_CHECK;
15791   codep++;
15792   used_prefixes |= (prefixes & PREFIX_DATA);
15793   reg = modrm.rm;
15794   if (prefixes & PREFIX_DATA)
15795     {
15796       names = names_xmm;
15797       USED_REX (REX_B);
15798       if (rex & REX_B)
15799         reg += 8;
15800     }
15801   else
15802     names = names_mm;
15803   oappend (names[reg]);
15804 }
15805
15806 /* cvt* are the only instructions in sse2 which have
15807    both SSE and MMX operands and also have 0x66 prefix
15808    in their opcode. 0x66 was originally used to differentiate
15809    between SSE and MMX instruction(operands). So we have to handle the
15810    cvt* separately using OP_EMC and OP_MXC */
15811 static void
15812 OP_EMC (int bytemode, int sizeflag)
15813 {
15814   if (modrm.mod != 3)
15815     {
15816       if (intel_syntax && bytemode == v_mode)
15817         {
15818           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15819           used_prefixes |= (prefixes & PREFIX_DATA);
15820         }
15821       OP_E (bytemode, sizeflag);
15822       return;
15823     }
15824
15825   /* Skip mod/rm byte.  */
15826   MODRM_CHECK;
15827   codep++;
15828   used_prefixes |= (prefixes & PREFIX_DATA);
15829   oappend (names_mm[modrm.rm]);
15830 }
15831
15832 static void
15833 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15834 {
15835   used_prefixes |= (prefixes & PREFIX_DATA);
15836   oappend (names_mm[modrm.reg]);
15837 }
15838
15839 static void
15840 OP_EX (int bytemode, int sizeflag)
15841 {
15842   int reg;
15843   const char **names;
15844
15845   /* Skip mod/rm byte.  */
15846   MODRM_CHECK;
15847   codep++;
15848
15849   if (modrm.mod != 3)
15850     {
15851       OP_E_memory (bytemode, sizeflag);
15852       return;
15853     }
15854
15855   reg = modrm.rm;
15856   USED_REX (REX_B);
15857   if (rex & REX_B)
15858     reg += 8;
15859   if (vex.evex)
15860     {
15861       USED_REX (REX_X);
15862       if ((rex & REX_X))
15863         reg += 16;
15864     }
15865
15866   if ((sizeflag & SUFFIX_ALWAYS)
15867       && (bytemode == x_swap_mode
15868           || bytemode == d_swap_mode
15869           || bytemode == d_scalar_swap_mode
15870           || bytemode == q_swap_mode
15871           || bytemode == q_scalar_swap_mode))
15872     swap_operand ();
15873
15874   if (need_vex
15875       && bytemode != xmm_mode
15876       && bytemode != xmmdw_mode
15877       && bytemode != xmmqd_mode
15878       && bytemode != xmm_mb_mode
15879       && bytemode != xmm_mw_mode
15880       && bytemode != xmm_md_mode
15881       && bytemode != xmm_mq_mode
15882       && bytemode != xmmq_mode
15883       && bytemode != evex_half_bcst_xmmq_mode
15884       && bytemode != ymm_mode
15885       && bytemode != tmm_mode
15886       && bytemode != d_scalar_swap_mode
15887       && bytemode != q_scalar_swap_mode
15888       && bytemode != vex_scalar_w_dq_mode)
15889     {
15890       switch (vex.length)
15891         {
15892         case 128:
15893           names = names_xmm;
15894           break;
15895         case 256:
15896           names = names_ymm;
15897           break;
15898         case 512:
15899           names = names_zmm;
15900           break;
15901         default:
15902           abort ();
15903         }
15904     }
15905   else if (bytemode == xmmq_mode
15906            || bytemode == evex_half_bcst_xmmq_mode)
15907     {
15908       switch (vex.length)
15909         {
15910         case 128:
15911         case 256:
15912           names = names_xmm;
15913           break;
15914         case 512:
15915           names = names_ymm;
15916           break;
15917         default:
15918           abort ();
15919         }
15920     }
15921   else if (bytemode == tmm_mode)
15922     {
15923       modrm.rm = reg;
15924       if (reg >= 8)
15925         {
15926           oappend ("(bad)");
15927           return;
15928         }
15929       names = names_tmm;
15930     }
15931   else if (bytemode == ymm_mode)
15932     names = names_ymm;
15933   else
15934     names = names_xmm;
15935   oappend (names[reg]);
15936 }
15937
15938 static void
15939 OP_MS (int bytemode, int sizeflag)
15940 {
15941   if (modrm.mod == 3)
15942     OP_EM (bytemode, sizeflag);
15943   else
15944     BadOp ();
15945 }
15946
15947 static void
15948 OP_XS (int bytemode, int sizeflag)
15949 {
15950   if (modrm.mod == 3)
15951     OP_EX (bytemode, sizeflag);
15952   else
15953     BadOp ();
15954 }
15955
15956 static void
15957 OP_M (int bytemode, int sizeflag)
15958 {
15959   if (modrm.mod == 3)
15960     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15961     BadOp ();
15962   else
15963     OP_E (bytemode, sizeflag);
15964 }
15965
15966 static void
15967 OP_0f07 (int bytemode, int sizeflag)
15968 {
15969   if (modrm.mod != 3 || modrm.rm != 0)
15970     BadOp ();
15971   else
15972     OP_E (bytemode, sizeflag);
15973 }
15974
15975 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15976    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
15977
15978 static void
15979 NOP_Fixup1 (int bytemode, int sizeflag)
15980 {
15981   if ((prefixes & PREFIX_DATA) != 0
15982       || (rex != 0
15983           && rex != 0x48
15984           && address_mode == mode_64bit))
15985     OP_REG (bytemode, sizeflag);
15986   else
15987     strcpy (obuf, "nop");
15988 }
15989
15990 static void
15991 NOP_Fixup2 (int bytemode, int sizeflag)
15992 {
15993   if ((prefixes & PREFIX_DATA) != 0
15994       || (rex != 0
15995           && rex != 0x48
15996           && address_mode == mode_64bit))
15997     OP_IMREG (bytemode, sizeflag);
15998 }
15999
16000 static const char *const Suffix3DNow[] = {
16001 /* 00 */        NULL,           NULL,           NULL,           NULL,
16002 /* 04 */        NULL,           NULL,           NULL,           NULL,
16003 /* 08 */        NULL,           NULL,           NULL,           NULL,
16004 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
16005 /* 10 */        NULL,           NULL,           NULL,           NULL,
16006 /* 14 */        NULL,           NULL,           NULL,           NULL,
16007 /* 18 */        NULL,           NULL,           NULL,           NULL,
16008 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
16009 /* 20 */        NULL,           NULL,           NULL,           NULL,
16010 /* 24 */        NULL,           NULL,           NULL,           NULL,
16011 /* 28 */        NULL,           NULL,           NULL,           NULL,
16012 /* 2C */        NULL,           NULL,           NULL,           NULL,
16013 /* 30 */        NULL,           NULL,           NULL,           NULL,
16014 /* 34 */        NULL,           NULL,           NULL,           NULL,
16015 /* 38 */        NULL,           NULL,           NULL,           NULL,
16016 /* 3C */        NULL,           NULL,           NULL,           NULL,
16017 /* 40 */        NULL,           NULL,           NULL,           NULL,
16018 /* 44 */        NULL,           NULL,           NULL,           NULL,
16019 /* 48 */        NULL,           NULL,           NULL,           NULL,
16020 /* 4C */        NULL,           NULL,           NULL,           NULL,
16021 /* 50 */        NULL,           NULL,           NULL,           NULL,
16022 /* 54 */        NULL,           NULL,           NULL,           NULL,
16023 /* 58 */        NULL,           NULL,           NULL,           NULL,
16024 /* 5C */        NULL,           NULL,           NULL,           NULL,
16025 /* 60 */        NULL,           NULL,           NULL,           NULL,
16026 /* 64 */        NULL,           NULL,           NULL,           NULL,
16027 /* 68 */        NULL,           NULL,           NULL,           NULL,
16028 /* 6C */        NULL,           NULL,           NULL,           NULL,
16029 /* 70 */        NULL,           NULL,           NULL,           NULL,
16030 /* 74 */        NULL,           NULL,           NULL,           NULL,
16031 /* 78 */        NULL,           NULL,           NULL,           NULL,
16032 /* 7C */        NULL,           NULL,           NULL,           NULL,
16033 /* 80 */        NULL,           NULL,           NULL,           NULL,
16034 /* 84 */        NULL,           NULL,           NULL,           NULL,
16035 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
16036 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
16037 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
16038 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
16039 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
16040 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
16041 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
16042 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
16043 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
16044 /* AC */        NULL,           NULL,           "pfacc",        NULL,
16045 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
16046 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
16047 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
16048 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
16049 /* C0 */        NULL,           NULL,           NULL,           NULL,
16050 /* C4 */        NULL,           NULL,           NULL,           NULL,
16051 /* C8 */        NULL,           NULL,           NULL,           NULL,
16052 /* CC */        NULL,           NULL,           NULL,           NULL,
16053 /* D0 */        NULL,           NULL,           NULL,           NULL,
16054 /* D4 */        NULL,           NULL,           NULL,           NULL,
16055 /* D8 */        NULL,           NULL,           NULL,           NULL,
16056 /* DC */        NULL,           NULL,           NULL,           NULL,
16057 /* E0 */        NULL,           NULL,           NULL,           NULL,
16058 /* E4 */        NULL,           NULL,           NULL,           NULL,
16059 /* E8 */        NULL,           NULL,           NULL,           NULL,
16060 /* EC */        NULL,           NULL,           NULL,           NULL,
16061 /* F0 */        NULL,           NULL,           NULL,           NULL,
16062 /* F4 */        NULL,           NULL,           NULL,           NULL,
16063 /* F8 */        NULL,           NULL,           NULL,           NULL,
16064 /* FC */        NULL,           NULL,           NULL,           NULL,
16065 };
16066
16067 static void
16068 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16069 {
16070   const char *mnemonic;
16071
16072   FETCH_DATA (the_info, codep + 1);
16073   /* AMD 3DNow! instructions are specified by an opcode suffix in the
16074      place where an 8-bit immediate would normally go.  ie. the last
16075      byte of the instruction.  */
16076   obufp = mnemonicendp;
16077   mnemonic = Suffix3DNow[*codep++ & 0xff];
16078   if (mnemonic)
16079     oappend (mnemonic);
16080   else
16081     {
16082       /* Since a variable sized modrm/sib chunk is between the start
16083          of the opcode (0x0f0f) and the opcode suffix, we need to do
16084          all the modrm processing first, and don't know until now that
16085          we have a bad opcode.  This necessitates some cleaning up.  */
16086       op_out[0][0] = '\0';
16087       op_out[1][0] = '\0';
16088       BadOp ();
16089     }
16090   mnemonicendp = obufp;
16091 }
16092
16093 static const struct op simd_cmp_op[] =
16094 {
16095   { STRING_COMMA_LEN ("eq") },
16096   { STRING_COMMA_LEN ("lt") },
16097   { STRING_COMMA_LEN ("le") },
16098   { STRING_COMMA_LEN ("unord") },
16099   { STRING_COMMA_LEN ("neq") },
16100   { STRING_COMMA_LEN ("nlt") },
16101   { STRING_COMMA_LEN ("nle") },
16102   { STRING_COMMA_LEN ("ord") }
16103 };
16104
16105 static const struct op vex_cmp_op[] =
16106 {
16107   { STRING_COMMA_LEN ("eq_uq") },
16108   { STRING_COMMA_LEN ("nge") },
16109   { STRING_COMMA_LEN ("ngt") },
16110   { STRING_COMMA_LEN ("false") },
16111   { STRING_COMMA_LEN ("neq_oq") },
16112   { STRING_COMMA_LEN ("ge") },
16113   { STRING_COMMA_LEN ("gt") },
16114   { STRING_COMMA_LEN ("true") },
16115   { STRING_COMMA_LEN ("eq_os") },
16116   { STRING_COMMA_LEN ("lt_oq") },
16117   { STRING_COMMA_LEN ("le_oq") },
16118   { STRING_COMMA_LEN ("unord_s") },
16119   { STRING_COMMA_LEN ("neq_us") },
16120   { STRING_COMMA_LEN ("nlt_uq") },
16121   { STRING_COMMA_LEN ("nle_uq") },
16122   { STRING_COMMA_LEN ("ord_s") },
16123   { STRING_COMMA_LEN ("eq_us") },
16124   { STRING_COMMA_LEN ("nge_uq") },
16125   { STRING_COMMA_LEN ("ngt_uq") },
16126   { STRING_COMMA_LEN ("false_os") },
16127   { STRING_COMMA_LEN ("neq_os") },
16128   { STRING_COMMA_LEN ("ge_oq") },
16129   { STRING_COMMA_LEN ("gt_oq") },
16130   { STRING_COMMA_LEN ("true_us") },
16131 };
16132
16133 static void
16134 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16135 {
16136   unsigned int cmp_type;
16137
16138   FETCH_DATA (the_info, codep + 1);
16139   cmp_type = *codep++ & 0xff;
16140   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
16141     {
16142       char suffix [3];
16143       char *p = mnemonicendp - 2;
16144       suffix[0] = p[0];
16145       suffix[1] = p[1];
16146       suffix[2] = '\0';
16147       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16148       mnemonicendp += simd_cmp_op[cmp_type].len;
16149     }
16150   else if (need_vex
16151            && cmp_type < ARRAY_SIZE (simd_cmp_op) + ARRAY_SIZE (vex_cmp_op))
16152     {
16153       char suffix [3];
16154       char *p = mnemonicendp - 2;
16155       suffix[0] = p[0];
16156       suffix[1] = p[1];
16157       suffix[2] = '\0';
16158       cmp_type -= ARRAY_SIZE (simd_cmp_op);
16159       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
16160       mnemonicendp += vex_cmp_op[cmp_type].len;
16161     }
16162   else
16163     {
16164       /* We have a reserved extension byte.  Output it directly.  */
16165       scratchbuf[0] = '$';
16166       print_operand_value (scratchbuf + 1, 1, cmp_type);
16167       oappend_maybe_intel (scratchbuf);
16168       scratchbuf[0] = '\0';
16169     }
16170 }
16171
16172 static void
16173 OP_Mwait (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16174 {
16175   /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx  */
16176   if (!intel_syntax)
16177     {
16178       strcpy (op_out[0], names32[0]);
16179       strcpy (op_out[1], names32[1]);
16180       if (bytemode == eBX_reg)
16181         strcpy (op_out[2], names32[3]);
16182       two_source_ops = 1;
16183     }
16184   /* Skip mod/rm byte.  */
16185   MODRM_CHECK;
16186   codep++;
16187 }
16188
16189 static void
16190 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
16191             int sizeflag ATTRIBUTE_UNUSED)
16192 {
16193   /* monitor %{e,r,}ax,%ecx,%edx"  */
16194   if (!intel_syntax)
16195     {
16196       const char **names = (address_mode == mode_64bit
16197                             ? names64 : names32);
16198
16199       if (prefixes & PREFIX_ADDR)
16200         {
16201           /* Remove "addr16/addr32".  */
16202           all_prefixes[last_addr_prefix] = 0;
16203           names = (address_mode != mode_32bit
16204                    ? names32 : names16);
16205           used_prefixes |= PREFIX_ADDR;
16206         }
16207       else if (address_mode == mode_16bit)
16208         names = names16;
16209       strcpy (op_out[0], names[0]);
16210       strcpy (op_out[1], names32[1]);
16211       strcpy (op_out[2], names32[2]);
16212       two_source_ops = 1;
16213     }
16214   /* Skip mod/rm byte.  */
16215   MODRM_CHECK;
16216   codep++;
16217 }
16218
16219 static void
16220 BadOp (void)
16221 {
16222   /* Throw away prefixes and 1st. opcode byte.  */
16223   codep = insn_codep + 1;
16224   oappend ("(bad)");
16225 }
16226
16227 static void
16228 REP_Fixup (int bytemode, int sizeflag)
16229 {
16230   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16231      lods and stos.  */
16232   if (prefixes & PREFIX_REPZ)
16233     all_prefixes[last_repz_prefix] = REP_PREFIX;
16234
16235   switch (bytemode)
16236     {
16237     case al_reg:
16238     case eAX_reg:
16239     case indir_dx_reg:
16240       OP_IMREG (bytemode, sizeflag);
16241       break;
16242     case eDI_reg:
16243       OP_ESreg (bytemode, sizeflag);
16244       break;
16245     case eSI_reg:
16246       OP_DSreg (bytemode, sizeflag);
16247       break;
16248     default:
16249       abort ();
16250       break;
16251     }
16252 }
16253
16254 static void
16255 SEP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16256 {
16257   if ( isa64 != amd64 )
16258     return;
16259
16260   obufp = obuf;
16261   BadOp ();
16262   mnemonicendp = obufp;
16263   ++codep;
16264 }
16265
16266 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16267    "bnd".  */
16268
16269 static void
16270 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16271 {
16272   if (prefixes & PREFIX_REPNZ)
16273     all_prefixes[last_repnz_prefix] = BND_PREFIX;
16274 }
16275
16276 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
16277    "notrack".  */
16278
16279 static void
16280 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
16281                int sizeflag ATTRIBUTE_UNUSED)
16282 {
16283   if (active_seg_prefix == PREFIX_DS
16284       && (address_mode != mode_64bit || last_data_prefix < 0))
16285     {
16286       /* NOTRACK prefix is only valid on indirect branch instructions.
16287          NB: DATA prefix is unsupported for Intel64.  */
16288       active_seg_prefix = 0;
16289       all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
16290     }
16291 }
16292
16293 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16294    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
16295  */
16296
16297 static void
16298 HLE_Fixup1 (int bytemode, int sizeflag)
16299 {
16300   if (modrm.mod != 3
16301       && (prefixes & PREFIX_LOCK) != 0)
16302     {
16303       if (prefixes & PREFIX_REPZ)
16304         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16305       if (prefixes & PREFIX_REPNZ)
16306         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16307     }
16308
16309   OP_E (bytemode, sizeflag);
16310 }
16311
16312 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16313    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
16314  */
16315
16316 static void
16317 HLE_Fixup2 (int bytemode, int sizeflag)
16318 {
16319   if (modrm.mod != 3)
16320     {
16321       if (prefixes & PREFIX_REPZ)
16322         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16323       if (prefixes & PREFIX_REPNZ)
16324         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16325     }
16326
16327   OP_E (bytemode, sizeflag);
16328 }
16329
16330 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
16331    "xrelease" for memory operand.  No check for LOCK prefix.   */
16332
16333 static void
16334 HLE_Fixup3 (int bytemode, int sizeflag)
16335 {
16336   if (modrm.mod != 3
16337       && last_repz_prefix > last_repnz_prefix
16338       && (prefixes & PREFIX_REPZ) != 0)
16339     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16340
16341   OP_E (bytemode, sizeflag);
16342 }
16343
16344 static void
16345 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
16346 {
16347   USED_REX (REX_W);
16348   if (rex & REX_W)
16349     {
16350       /* Change cmpxchg8b to cmpxchg16b.  */
16351       char *p = mnemonicendp - 2;
16352       mnemonicendp = stpcpy (p, "16b");
16353       bytemode = o_mode;
16354     }
16355   else if ((prefixes & PREFIX_LOCK) != 0)
16356     {
16357       if (prefixes & PREFIX_REPZ)
16358         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16359       if (prefixes & PREFIX_REPNZ)
16360         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16361     }
16362
16363   OP_M (bytemode, sizeflag);
16364 }
16365
16366 static void
16367 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
16368 {
16369   const char **names;
16370
16371   if (need_vex)
16372     {
16373       switch (vex.length)
16374         {
16375         case 128:
16376           names = names_xmm;
16377           break;
16378         case 256:
16379           names = names_ymm;
16380           break;
16381         default:
16382           abort ();
16383         }
16384     }
16385   else
16386     names = names_xmm;
16387   oappend (names[reg]);
16388 }
16389
16390 static void
16391 FXSAVE_Fixup (int bytemode, int sizeflag)
16392 {
16393   /* Add proper suffix to "fxsave" and "fxrstor".  */
16394   USED_REX (REX_W);
16395   if (rex & REX_W)
16396     {
16397       char *p = mnemonicendp;
16398       *p++ = '6';
16399       *p++ = '4';
16400       *p = '\0';
16401       mnemonicendp = p;
16402     }
16403   OP_M (bytemode, sizeflag);
16404 }
16405
16406 /* Display the destination register operand for instructions with
16407    VEX. */
16408
16409 static void
16410 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16411 {
16412   int reg;
16413   const char **names;
16414
16415   if (!need_vex)
16416     abort ();
16417
16418   if (!need_vex_reg)
16419     return;
16420
16421   reg = vex.register_specifier;
16422   vex.register_specifier = 0;
16423   if (address_mode != mode_64bit)
16424     reg &= 7;
16425   else if (vex.evex && !vex.v)
16426     reg += 16;
16427
16428   if (bytemode == vex_scalar_mode)
16429     {
16430       oappend (names_xmm[reg]);
16431       return;
16432     }
16433
16434   if (bytemode == tmm_mode)
16435     {
16436       /* All 3 TMM registers must be distinct.  */
16437       if (reg >= 8)
16438         oappend ("(bad)");
16439       else
16440         {
16441           /* This must be the 3rd operand.  */
16442           if (obufp != op_out[2])
16443             abort ();
16444           oappend (names_tmm[reg]);
16445           if (reg == modrm.reg || reg == modrm.rm)
16446             strcpy (obufp, "/(bad)");
16447         }
16448
16449       if (modrm.reg == modrm.rm || modrm.reg == reg || modrm.rm == reg)
16450         {
16451           if (modrm.reg <= 8
16452               && (modrm.reg == modrm.rm || modrm.reg == reg))
16453             strcat (op_out[0], "/(bad)");
16454           if (modrm.rm <= 8
16455               && (modrm.rm == modrm.reg || modrm.rm == reg))
16456             strcat (op_out[1], "/(bad)");
16457         }
16458
16459       return;
16460     }
16461
16462   switch (vex.length)
16463     {
16464     case 128:
16465       switch (bytemode)
16466         {
16467         case vex_mode:
16468         case vex128_mode:
16469         case vex_vsib_q_w_dq_mode:
16470         case vex_vsib_q_w_d_mode:
16471           names = names_xmm;
16472           break;
16473         case dq_mode:
16474           if (rex & REX_W)
16475             names = names64;
16476           else
16477             names = names32;
16478           break;
16479         case mask_bd_mode:
16480         case mask_mode:
16481           if (reg > 0x7)
16482             {
16483               oappend ("(bad)");
16484               return;
16485             }
16486           names = names_mask;
16487           break;
16488         default:
16489           abort ();
16490           return;
16491         }
16492       break;
16493     case 256:
16494       switch (bytemode)
16495         {
16496         case vex_mode:
16497         case vex256_mode:
16498           names = names_ymm;
16499           break;
16500         case vex_vsib_q_w_dq_mode:
16501         case vex_vsib_q_w_d_mode:
16502           names = vex.w ? names_ymm : names_xmm;
16503           break;
16504         case mask_bd_mode:
16505         case mask_mode:
16506           if (reg > 0x7)
16507             {
16508               oappend ("(bad)");
16509               return;
16510             }
16511           names = names_mask;
16512           break;
16513         default:
16514           /* See PR binutils/20893 for a reproducer.  */
16515           oappend ("(bad)");
16516           return;
16517         }
16518       break;
16519     case 512:
16520       names = names_zmm;
16521       break;
16522     default:
16523       abort ();
16524       break;
16525     }
16526   oappend (names[reg]);
16527 }
16528
16529 static void
16530 OP_VexW (int bytemode, int sizeflag)
16531 {
16532   OP_VEX (bytemode, sizeflag);
16533
16534   if (vex.w)
16535     {
16536       /* Swap 2nd and 3rd operands.  */
16537       strcpy (scratchbuf, op_out[2]);
16538       strcpy (op_out[2], op_out[1]);
16539       strcpy (op_out[1], scratchbuf);
16540     }
16541 }
16542
16543 static void
16544 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16545 {
16546   int reg;
16547   const char **names = names_xmm;
16548
16549   FETCH_DATA (the_info, codep + 1);
16550   reg = *codep++;
16551
16552   if (bytemode != x_mode && bytemode != scalar_mode)
16553     abort ();
16554
16555   reg >>= 4;
16556   if (address_mode != mode_64bit)
16557     reg &= 7;
16558
16559   if (bytemode == x_mode && vex.length == 256)
16560     names = names_ymm;
16561
16562   oappend (names[reg]);
16563
16564   if (vex.w)
16565     {
16566       /* Swap 3rd and 4th operands.  */
16567       strcpy (scratchbuf, op_out[3]);
16568       strcpy (op_out[3], op_out[2]);
16569       strcpy (op_out[2], scratchbuf);
16570     }
16571 }
16572
16573 static void
16574 OP_VexI4 (int bytemode ATTRIBUTE_UNUSED,
16575           int sizeflag ATTRIBUTE_UNUSED)
16576 {
16577   scratchbuf[0] = '$';
16578   print_operand_value (scratchbuf + 1, 1, codep[-1] & 0xf);
16579   oappend_maybe_intel (scratchbuf);
16580 }
16581
16582 static void
16583 OP_EX_Vex (int bytemode, int sizeflag)
16584 {
16585   if (modrm.mod != 3)
16586     need_vex_reg = 0;
16587   OP_EX (bytemode, sizeflag);
16588 }
16589
16590 static void
16591 OP_XMM_Vex (int bytemode, int sizeflag)
16592 {
16593   if (modrm.mod != 3)
16594     need_vex_reg = 0;
16595   OP_XMM (bytemode, sizeflag);
16596 }
16597
16598 static void
16599 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
16600              int sizeflag ATTRIBUTE_UNUSED)
16601 {
16602   unsigned int cmp_type;
16603
16604   if (!vex.evex)
16605     abort ();
16606
16607   FETCH_DATA (the_info, codep + 1);
16608   cmp_type = *codep++ & 0xff;
16609   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16610      If it's the case, print suffix, otherwise - print the immediate.  */
16611   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
16612       && cmp_type != 3
16613       && cmp_type != 7)
16614     {
16615       char suffix [3];
16616       char *p = mnemonicendp - 2;
16617
16618       /* vpcmp* can have both one- and two-lettered suffix.  */
16619       if (p[0] == 'p')
16620         {
16621           p++;
16622           suffix[0] = p[0];
16623           suffix[1] = '\0';
16624         }
16625       else
16626         {
16627           suffix[0] = p[0];
16628           suffix[1] = p[1];
16629           suffix[2] = '\0';
16630         }
16631
16632       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16633       mnemonicendp += simd_cmp_op[cmp_type].len;
16634     }
16635   else
16636     {
16637       /* We have a reserved extension byte.  Output it directly.  */
16638       scratchbuf[0] = '$';
16639       print_operand_value (scratchbuf + 1, 1, cmp_type);
16640       oappend_maybe_intel (scratchbuf);
16641       scratchbuf[0] = '\0';
16642     }
16643 }
16644
16645 static const struct op xop_cmp_op[] =
16646 {
16647   { STRING_COMMA_LEN ("lt") },
16648   { STRING_COMMA_LEN ("le") },
16649   { STRING_COMMA_LEN ("gt") },
16650   { STRING_COMMA_LEN ("ge") },
16651   { STRING_COMMA_LEN ("eq") },
16652   { STRING_COMMA_LEN ("neq") },
16653   { STRING_COMMA_LEN ("false") },
16654   { STRING_COMMA_LEN ("true") }
16655 };
16656
16657 static void
16658 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
16659              int sizeflag ATTRIBUTE_UNUSED)
16660 {
16661   unsigned int cmp_type;
16662
16663   FETCH_DATA (the_info, codep + 1);
16664   cmp_type = *codep++ & 0xff;
16665   if (cmp_type < ARRAY_SIZE (xop_cmp_op))
16666     {
16667       char suffix[3];
16668       char *p = mnemonicendp - 2;
16669
16670       /* vpcom* can have both one- and two-lettered suffix.  */
16671       if (p[0] == 'm')
16672         {
16673           p++;
16674           suffix[0] = p[0];
16675           suffix[1] = '\0';
16676         }
16677       else
16678         {
16679           suffix[0] = p[0];
16680           suffix[1] = p[1];
16681           suffix[2] = '\0';
16682         }
16683
16684       sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
16685       mnemonicendp += xop_cmp_op[cmp_type].len;
16686     }
16687   else
16688     {
16689       /* We have a reserved extension byte.  Output it directly.  */
16690       scratchbuf[0] = '$';
16691       print_operand_value (scratchbuf + 1, 1, cmp_type);
16692       oappend_maybe_intel (scratchbuf);
16693       scratchbuf[0] = '\0';
16694     }
16695 }
16696
16697 static const struct op pclmul_op[] =
16698 {
16699   { STRING_COMMA_LEN ("lql") },
16700   { STRING_COMMA_LEN ("hql") },
16701   { STRING_COMMA_LEN ("lqh") },
16702   { STRING_COMMA_LEN ("hqh") }
16703 };
16704
16705 static void
16706 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
16707               int sizeflag ATTRIBUTE_UNUSED)
16708 {
16709   unsigned int pclmul_type;
16710
16711   FETCH_DATA (the_info, codep + 1);
16712   pclmul_type = *codep++ & 0xff;
16713   switch (pclmul_type)
16714     {
16715     case 0x10:
16716       pclmul_type = 2;
16717       break;
16718     case 0x11:
16719       pclmul_type = 3;
16720       break;
16721     default:
16722       break;
16723     }
16724   if (pclmul_type < ARRAY_SIZE (pclmul_op))
16725     {
16726       char suffix [4];
16727       char *p = mnemonicendp - 3;
16728       suffix[0] = p[0];
16729       suffix[1] = p[1];
16730       suffix[2] = p[2];
16731       suffix[3] = '\0';
16732       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
16733       mnemonicendp += pclmul_op[pclmul_type].len;
16734     }
16735   else
16736     {
16737       /* We have a reserved extension byte.  Output it directly.  */
16738       scratchbuf[0] = '$';
16739       print_operand_value (scratchbuf + 1, 1, pclmul_type);
16740       oappend_maybe_intel (scratchbuf);
16741       scratchbuf[0] = '\0';
16742     }
16743 }
16744
16745 static void
16746 MOVSXD_Fixup (int bytemode, int sizeflag)
16747 {
16748   /* Add proper suffix to "movsxd".  */
16749   char *p = mnemonicendp;
16750
16751   switch (bytemode)
16752     {
16753     case movsxd_mode:
16754       if (intel_syntax)
16755         {
16756           *p++ = 'x';
16757           *p++ = 'd';
16758           goto skip;
16759         }
16760
16761       USED_REX (REX_W);
16762       if (rex & REX_W)
16763         {
16764           *p++ = 'l';
16765           *p++ = 'q';
16766         }
16767       else
16768         {
16769           *p++ = 'x';
16770           *p++ = 'd';
16771         }
16772       break;
16773     default:
16774       oappend (INTERNAL_DISASSEMBLER_ERROR);
16775       break;
16776     }
16777
16778  skip:
16779   mnemonicendp = p;
16780   *p = '\0';
16781   OP_E (bytemode, sizeflag);
16782 }
16783
16784 static void
16785 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16786 {
16787   if (!vex.evex
16788       || (bytemode != mask_mode && bytemode != mask_bd_mode))
16789     abort ();
16790
16791   USED_REX (REX_R);
16792   if ((rex & REX_R) != 0 || !vex.r)
16793     {
16794       BadOp ();
16795       return;
16796     }
16797
16798   oappend (names_mask [modrm.reg]);
16799 }
16800
16801 static void
16802 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16803 {
16804   if (modrm.mod == 3 && vex.b)
16805     switch (bytemode)
16806       {
16807       case evex_rounding_64_mode:
16808         if (address_mode != mode_64bit)
16809           {
16810             oappend ("(bad)");
16811             break;
16812           }
16813         /* Fall through.  */
16814       case evex_rounding_mode:
16815         oappend (names_rounding[vex.ll]);
16816         break;
16817       case evex_sae_mode:
16818         oappend ("{sae}");
16819         break;
16820       default:
16821         abort ();
16822         break;
16823       }
16824 }