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Change avxvnni disassembler output from {vex3} to {vex}
[binutils-gdb.git] / opcodes / i386-dis.c
1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2020 Free Software Foundation, Inc.
3
4 This file is part of the GNU opcodes library.
5
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
20
21
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
23 July 1988
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
27
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
34
35 #include "sysdep.h"
36 #include "disassemble.h"
37 #include "opintl.h"
38 #include "opcode/i386.h"
39 #include "libiberty.h"
40 #include "safe-ctype.h"
41
42 #include <setjmp.h>
43
44 static int print_insn (bfd_vma, disassemble_info *);
45 static void dofloat (int);
46 static void OP_ST (int, int);
47 static void OP_STi (int, int);
48 static int putop (const char *, int);
49 static void oappend (const char *);
50 static void append_seg (void);
51 static void OP_indirE (int, int);
52 static void print_operand_value (char *, int, bfd_vma);
53 static void OP_E_register (int, int);
54 static void OP_E_memory (int, int);
55 static void print_displacement (char *, bfd_vma);
56 static void OP_E (int, int);
57 static void OP_G (int, int);
58 static bfd_vma get64 (void);
59 static bfd_signed_vma get32 (void);
60 static bfd_signed_vma get32s (void);
61 static int get16 (void);
62 static void set_op (bfd_vma, int);
63 static void OP_Skip_MODRM (int, int);
64 static void OP_REG (int, int);
65 static void OP_IMREG (int, int);
66 static void OP_I (int, int);
67 static void OP_I64 (int, int);
68 static void OP_sI (int, int);
69 static void OP_J (int, int);
70 static void OP_SEG (int, int);
71 static void OP_DIR (int, int);
72 static void OP_OFF (int, int);
73 static void OP_OFF64 (int, int);
74 static void ptr_reg (int, int);
75 static void OP_ESreg (int, int);
76 static void OP_DSreg (int, int);
77 static void OP_C (int, int);
78 static void OP_D (int, int);
79 static void OP_T (int, int);
80 static void OP_MMX (int, int);
81 static void OP_XMM (int, int);
82 static void OP_EM (int, int);
83 static void OP_EX (int, int);
84 static void OP_EMC (int,int);
85 static void OP_MXC (int,int);
86 static void OP_MS (int, int);
87 static void OP_XS (int, int);
88 static void OP_M (int, int);
89 static void OP_VEX (int, int);
90 static void OP_VexR (int, int);
91 static void OP_VexW (int, int);
92 static void OP_Rounding (int, int);
93 static void OP_REG_VexI4 (int, int);
94 static void OP_VexI4 (int, int);
95 static void PCLMUL_Fixup (int, int);
96 static void VPCMP_Fixup (int, int);
97 static void VPCOM_Fixup (int, int);
98 static void OP_0f07 (int, int);
99 static void OP_Monitor (int, int);
100 static void OP_Mwait (int, int);
101 static void NOP_Fixup1 (int, int);
102 static void NOP_Fixup2 (int, int);
103 static void OP_3DNowSuffix (int, int);
104 static void CMP_Fixup (int, int);
105 static void BadOp (void);
106 static void REP_Fixup (int, int);
107 static void SEP_Fixup (int, int);
108 static void BND_Fixup (int, int);
109 static void NOTRACK_Fixup (int, int);
110 static void HLE_Fixup1 (int, int);
111 static void HLE_Fixup2 (int, int);
112 static void HLE_Fixup3 (int, int);
113 static void CMPXCHG8B_Fixup (int, int);
114 static void XMM_Fixup (int, int);
115 static void FXSAVE_Fixup (int, int);
116
117 static void MOVSXD_Fixup (int, int);
118
119 static void OP_Mask (int, int);
120
121 struct dis_private {
122 /* Points to first byte not fetched. */
123 bfd_byte *max_fetched;
124 bfd_byte the_buffer[MAX_MNEM_SIZE];
125 bfd_vma insn_start;
126 int orig_sizeflag;
127 OPCODES_SIGJMP_BUF bailout;
128 };
129
130 enum address_mode
131 {
132 mode_16bit,
133 mode_32bit,
134 mode_64bit
135 };
136
137 enum address_mode address_mode;
138
139 /* Flags for the prefixes for the current instruction. See below. */
140 static int prefixes;
141
142 /* REX prefix the current instruction. See below. */
143 static int rex;
144 /* Bits of REX we've already used. */
145 static int rex_used;
146 /* Mark parts used in the REX prefix. When we are testing for
147 empty prefix (for 8bit register REX extension), just mask it
148 out. Otherwise test for REX bit is excuse for existence of REX
149 only in case value is nonzero. */
150 #define USED_REX(value) \
151 { \
152 if (value) \
153 { \
154 if ((rex & value)) \
155 rex_used |= (value) | REX_OPCODE; \
156 } \
157 else \
158 rex_used |= REX_OPCODE; \
159 }
160
161 /* Flags for prefixes which we somehow handled when printing the
162 current instruction. */
163 static int used_prefixes;
164
165 /* Flags stored in PREFIXES. */
166 #define PREFIX_REPZ 1
167 #define PREFIX_REPNZ 2
168 #define PREFIX_LOCK 4
169 #define PREFIX_CS 8
170 #define PREFIX_SS 0x10
171 #define PREFIX_DS 0x20
172 #define PREFIX_ES 0x40
173 #define PREFIX_FS 0x80
174 #define PREFIX_GS 0x100
175 #define PREFIX_DATA 0x200
176 #define PREFIX_ADDR 0x400
177 #define PREFIX_FWAIT 0x800
178
179 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
180 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
181 on error. */
182 #define FETCH_DATA(info, addr) \
183 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
184 ? 1 : fetch_data ((info), (addr)))
185
186 static int
187 fetch_data (struct disassemble_info *info, bfd_byte *addr)
188 {
189 int status;
190 struct dis_private *priv = (struct dis_private *) info->private_data;
191 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
192
193 if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
194 status = (*info->read_memory_func) (start,
195 priv->max_fetched,
196 addr - priv->max_fetched,
197 info);
198 else
199 status = -1;
200 if (status != 0)
201 {
202 /* If we did manage to read at least one byte, then
203 print_insn_i386 will do something sensible. Otherwise, print
204 an error. We do that here because this is where we know
205 STATUS. */
206 if (priv->max_fetched == priv->the_buffer)
207 (*info->memory_error_func) (status, start, info);
208 OPCODES_SIGLONGJMP (priv->bailout, 1);
209 }
210 else
211 priv->max_fetched = addr;
212 return 1;
213 }
214
215 /* Possible values for prefix requirement. */
216 #define PREFIX_IGNORED_SHIFT 16
217 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
218 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
219 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
220 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
221 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
222
223 /* Opcode prefixes. */
224 #define PREFIX_OPCODE (PREFIX_REPZ \
225 | PREFIX_REPNZ \
226 | PREFIX_DATA)
227
228 /* Prefixes ignored. */
229 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
230 | PREFIX_IGNORED_REPNZ \
231 | PREFIX_IGNORED_DATA)
232
233 #define XX { NULL, 0 }
234 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
235
236 #define Eb { OP_E, b_mode }
237 #define Ebnd { OP_E, bnd_mode }
238 #define EbS { OP_E, b_swap_mode }
239 #define EbndS { OP_E, bnd_swap_mode }
240 #define Ev { OP_E, v_mode }
241 #define Eva { OP_E, va_mode }
242 #define Ev_bnd { OP_E, v_bnd_mode }
243 #define EvS { OP_E, v_swap_mode }
244 #define Ed { OP_E, d_mode }
245 #define Edq { OP_E, dq_mode }
246 #define Edqw { OP_E, dqw_mode }
247 #define Edqb { OP_E, dqb_mode }
248 #define Edb { OP_E, db_mode }
249 #define Edw { OP_E, dw_mode }
250 #define Edqd { OP_E, dqd_mode }
251 #define Eq { OP_E, q_mode }
252 #define indirEv { OP_indirE, indir_v_mode }
253 #define indirEp { OP_indirE, f_mode }
254 #define stackEv { OP_E, stack_v_mode }
255 #define Em { OP_E, m_mode }
256 #define Ew { OP_E, w_mode }
257 #define M { OP_M, 0 } /* lea, lgdt, etc. */
258 #define Ma { OP_M, a_mode }
259 #define Mb { OP_M, b_mode }
260 #define Md { OP_M, d_mode }
261 #define Mo { OP_M, o_mode }
262 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
263 #define Mq { OP_M, q_mode }
264 #define Mv { OP_M, v_mode }
265 #define Mv_bnd { OP_M, v_bndmk_mode }
266 #define Mx { OP_M, x_mode }
267 #define Mxmm { OP_M, xmm_mode }
268 #define Gb { OP_G, b_mode }
269 #define Gbnd { OP_G, bnd_mode }
270 #define Gv { OP_G, v_mode }
271 #define Gd { OP_G, d_mode }
272 #define Gdq { OP_G, dq_mode }
273 #define Gm { OP_G, m_mode }
274 #define Gva { OP_G, va_mode }
275 #define Gw { OP_G, w_mode }
276 #define Ib { OP_I, b_mode }
277 #define sIb { OP_sI, b_mode } /* sign extened byte */
278 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
279 #define Iv { OP_I, v_mode }
280 #define sIv { OP_sI, v_mode }
281 #define Iv64 { OP_I64, v_mode }
282 #define Id { OP_I, d_mode }
283 #define Iw { OP_I, w_mode }
284 #define I1 { OP_I, const_1_mode }
285 #define Jb { OP_J, b_mode }
286 #define Jv { OP_J, v_mode }
287 #define Jdqw { OP_J, dqw_mode }
288 #define Cm { OP_C, m_mode }
289 #define Dm { OP_D, m_mode }
290 #define Td { OP_T, d_mode }
291 #define Skip_MODRM { OP_Skip_MODRM, 0 }
292
293 #define RMeAX { OP_REG, eAX_reg }
294 #define RMeBX { OP_REG, eBX_reg }
295 #define RMeCX { OP_REG, eCX_reg }
296 #define RMeDX { OP_REG, eDX_reg }
297 #define RMeSP { OP_REG, eSP_reg }
298 #define RMeBP { OP_REG, eBP_reg }
299 #define RMeSI { OP_REG, eSI_reg }
300 #define RMeDI { OP_REG, eDI_reg }
301 #define RMrAX { OP_REG, rAX_reg }
302 #define RMrBX { OP_REG, rBX_reg }
303 #define RMrCX { OP_REG, rCX_reg }
304 #define RMrDX { OP_REG, rDX_reg }
305 #define RMrSP { OP_REG, rSP_reg }
306 #define RMrBP { OP_REG, rBP_reg }
307 #define RMrSI { OP_REG, rSI_reg }
308 #define RMrDI { OP_REG, rDI_reg }
309 #define RMAL { OP_REG, al_reg }
310 #define RMCL { OP_REG, cl_reg }
311 #define RMDL { OP_REG, dl_reg }
312 #define RMBL { OP_REG, bl_reg }
313 #define RMAH { OP_REG, ah_reg }
314 #define RMCH { OP_REG, ch_reg }
315 #define RMDH { OP_REG, dh_reg }
316 #define RMBH { OP_REG, bh_reg }
317 #define RMAX { OP_REG, ax_reg }
318 #define RMDX { OP_REG, dx_reg }
319
320 #define eAX { OP_IMREG, eAX_reg }
321 #define AL { OP_IMREG, al_reg }
322 #define CL { OP_IMREG, cl_reg }
323 #define zAX { OP_IMREG, z_mode_ax_reg }
324 #define indirDX { OP_IMREG, indir_dx_reg }
325
326 #define Sw { OP_SEG, w_mode }
327 #define Sv { OP_SEG, v_mode }
328 #define Ap { OP_DIR, 0 }
329 #define Ob { OP_OFF64, b_mode }
330 #define Ov { OP_OFF64, v_mode }
331 #define Xb { OP_DSreg, eSI_reg }
332 #define Xv { OP_DSreg, eSI_reg }
333 #define Xz { OP_DSreg, eSI_reg }
334 #define Yb { OP_ESreg, eDI_reg }
335 #define Yv { OP_ESreg, eDI_reg }
336 #define DSBX { OP_DSreg, eBX_reg }
337
338 #define es { OP_REG, es_reg }
339 #define ss { OP_REG, ss_reg }
340 #define cs { OP_REG, cs_reg }
341 #define ds { OP_REG, ds_reg }
342 #define fs { OP_REG, fs_reg }
343 #define gs { OP_REG, gs_reg }
344
345 #define MX { OP_MMX, 0 }
346 #define XM { OP_XMM, 0 }
347 #define XMScalar { OP_XMM, scalar_mode }
348 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
349 #define XMM { OP_XMM, xmm_mode }
350 #define TMM { OP_XMM, tmm_mode }
351 #define XMxmmq { OP_XMM, xmmq_mode }
352 #define EM { OP_EM, v_mode }
353 #define EMS { OP_EM, v_swap_mode }
354 #define EMd { OP_EM, d_mode }
355 #define EMx { OP_EM, x_mode }
356 #define EXbwUnit { OP_EX, bw_unit_mode }
357 #define EXw { OP_EX, w_mode }
358 #define EXd { OP_EX, d_mode }
359 #define EXdS { OP_EX, d_swap_mode }
360 #define EXq { OP_EX, q_mode }
361 #define EXqS { OP_EX, q_swap_mode }
362 #define EXx { OP_EX, x_mode }
363 #define EXxS { OP_EX, x_swap_mode }
364 #define EXxmm { OP_EX, xmm_mode }
365 #define EXymm { OP_EX, ymm_mode }
366 #define EXtmm { OP_EX, tmm_mode }
367 #define EXxmmq { OP_EX, xmmq_mode }
368 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
369 #define EXxmm_mb { OP_EX, xmm_mb_mode }
370 #define EXxmm_mw { OP_EX, xmm_mw_mode }
371 #define EXxmm_md { OP_EX, xmm_md_mode }
372 #define EXxmm_mq { OP_EX, xmm_mq_mode }
373 #define EXxmmdw { OP_EX, xmmdw_mode }
374 #define EXxmmqd { OP_EX, xmmqd_mode }
375 #define EXymmq { OP_EX, ymmq_mode }
376 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
377 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
378 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
379 #define MS { OP_MS, v_mode }
380 #define XS { OP_XS, v_mode }
381 #define EMCq { OP_EMC, q_mode }
382 #define MXC { OP_MXC, 0 }
383 #define OPSUF { OP_3DNowSuffix, 0 }
384 #define SEP { SEP_Fixup, 0 }
385 #define CMP { CMP_Fixup, 0 }
386 #define XMM0 { XMM_Fixup, 0 }
387 #define FXSAVE { FXSAVE_Fixup, 0 }
388
389 #define Vex { OP_VEX, vex_mode }
390 #define VexW { OP_VexW, vex_mode }
391 #define VexScalar { OP_VEX, vex_scalar_mode }
392 #define VexScalarR { OP_VexR, vex_scalar_mode }
393 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
394 #define VexGdq { OP_VEX, dq_mode }
395 #define VexTmm { OP_VEX, tmm_mode }
396 #define XMVexI4 { OP_REG_VexI4, x_mode }
397 #define XMVexScalarI4 { OP_REG_VexI4, scalar_mode }
398 #define VexI4 { OP_VexI4, 0 }
399 #define PCLMUL { PCLMUL_Fixup, 0 }
400 #define VPCMP { VPCMP_Fixup, 0 }
401 #define VPCOM { VPCOM_Fixup, 0 }
402
403 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
404 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
405 #define EXxEVexS { OP_Rounding, evex_sae_mode }
406
407 #define XMask { OP_Mask, mask_mode }
408 #define MaskG { OP_G, mask_mode }
409 #define MaskE { OP_E, mask_mode }
410 #define MaskBDE { OP_E, mask_bd_mode }
411 #define MaskVex { OP_VEX, mask_mode }
412
413 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
414 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
415 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
416 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
417
418 #define MVexSIBMEM { OP_M, vex_sibmem_mode }
419
420 /* Used handle "rep" prefix for string instructions. */
421 #define Xbr { REP_Fixup, eSI_reg }
422 #define Xvr { REP_Fixup, eSI_reg }
423 #define Ybr { REP_Fixup, eDI_reg }
424 #define Yvr { REP_Fixup, eDI_reg }
425 #define Yzr { REP_Fixup, eDI_reg }
426 #define indirDXr { REP_Fixup, indir_dx_reg }
427 #define ALr { REP_Fixup, al_reg }
428 #define eAXr { REP_Fixup, eAX_reg }
429
430 /* Used handle HLE prefix for lockable instructions. */
431 #define Ebh1 { HLE_Fixup1, b_mode }
432 #define Evh1 { HLE_Fixup1, v_mode }
433 #define Ebh2 { HLE_Fixup2, b_mode }
434 #define Evh2 { HLE_Fixup2, v_mode }
435 #define Ebh3 { HLE_Fixup3, b_mode }
436 #define Evh3 { HLE_Fixup3, v_mode }
437
438 #define BND { BND_Fixup, 0 }
439 #define NOTRACK { NOTRACK_Fixup, 0 }
440
441 #define cond_jump_flag { NULL, cond_jump_mode }
442 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
443
444 /* bits in sizeflag */
445 #define SUFFIX_ALWAYS 4
446 #define AFLAG 2
447 #define DFLAG 1
448
449 enum
450 {
451 /* byte operand */
452 b_mode = 1,
453 /* byte operand with operand swapped */
454 b_swap_mode,
455 /* byte operand, sign extend like 'T' suffix */
456 b_T_mode,
457 /* operand size depends on prefixes */
458 v_mode,
459 /* operand size depends on prefixes with operand swapped */
460 v_swap_mode,
461 /* operand size depends on address prefix */
462 va_mode,
463 /* word operand */
464 w_mode,
465 /* double word operand */
466 d_mode,
467 /* double word operand with operand swapped */
468 d_swap_mode,
469 /* quad word operand */
470 q_mode,
471 /* quad word operand with operand swapped */
472 q_swap_mode,
473 /* ten-byte operand */
474 t_mode,
475 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
476 broadcast enabled. */
477 x_mode,
478 /* Similar to x_mode, but with different EVEX mem shifts. */
479 evex_x_gscat_mode,
480 /* Similar to x_mode, but with yet different EVEX mem shifts. */
481 bw_unit_mode,
482 /* Similar to x_mode, but with disabled broadcast. */
483 evex_x_nobcst_mode,
484 /* Similar to x_mode, but with operands swapped and disabled broadcast
485 in EVEX. */
486 x_swap_mode,
487 /* 16-byte XMM operand */
488 xmm_mode,
489 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
490 memory operand (depending on vector length). Broadcast isn't
491 allowed. */
492 xmmq_mode,
493 /* Same as xmmq_mode, but broadcast is allowed. */
494 evex_half_bcst_xmmq_mode,
495 /* XMM register or byte memory operand */
496 xmm_mb_mode,
497 /* XMM register or word memory operand */
498 xmm_mw_mode,
499 /* XMM register or double word memory operand */
500 xmm_md_mode,
501 /* XMM register or quad word memory operand */
502 xmm_mq_mode,
503 /* 16-byte XMM, word, double word or quad word operand. */
504 xmmdw_mode,
505 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
506 xmmqd_mode,
507 /* 32-byte YMM operand */
508 ymm_mode,
509 /* quad word, ymmword or zmmword memory operand. */
510 ymmq_mode,
511 /* 32-byte YMM or 16-byte word operand */
512 ymmxmm_mode,
513 /* TMM operand */
514 tmm_mode,
515 /* d_mode in 32bit, q_mode in 64bit mode. */
516 m_mode,
517 /* pair of v_mode operands */
518 a_mode,
519 cond_jump_mode,
520 loop_jcxz_mode,
521 movsxd_mode,
522 v_bnd_mode,
523 /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */
524 v_bndmk_mode,
525 /* operand size depends on REX prefixes. */
526 dq_mode,
527 /* registers like dq_mode, memory like w_mode, displacements like
528 v_mode without considering Intel64 ISA. */
529 dqw_mode,
530 /* bounds operand */
531 bnd_mode,
532 /* bounds operand with operand swapped */
533 bnd_swap_mode,
534 /* 4- or 6-byte pointer operand */
535 f_mode,
536 const_1_mode,
537 /* v_mode for indirect branch opcodes. */
538 indir_v_mode,
539 /* v_mode for stack-related opcodes. */
540 stack_v_mode,
541 /* non-quad operand size depends on prefixes */
542 z_mode,
543 /* 16-byte operand */
544 o_mode,
545 /* registers like dq_mode, memory like b_mode. */
546 dqb_mode,
547 /* registers like d_mode, memory like b_mode. */
548 db_mode,
549 /* registers like d_mode, memory like w_mode. */
550 dw_mode,
551 /* registers like dq_mode, memory like d_mode. */
552 dqd_mode,
553 /* normal vex mode */
554 vex_mode,
555
556 /* Operand size depends on the VEX.W bit, with VSIB dword indices. */
557 vex_vsib_d_w_dq_mode,
558 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
559 vex_vsib_d_w_d_mode,
560 /* Operand size depends on the VEX.W bit, with VSIB qword indices. */
561 vex_vsib_q_w_dq_mode,
562 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
563 vex_vsib_q_w_d_mode,
564 /* mandatory non-vector SIB. */
565 vex_sibmem_mode,
566
567 /* scalar, ignore vector length. */
568 scalar_mode,
569 /* like vex_mode, ignore vector length. */
570 vex_scalar_mode,
571 /* Operand size depends on the VEX.W bit, ignore vector length. */
572 vex_scalar_w_dq_mode,
573
574 /* Static rounding. */
575 evex_rounding_mode,
576 /* Static rounding, 64-bit mode only. */
577 evex_rounding_64_mode,
578 /* Supress all exceptions. */
579 evex_sae_mode,
580
581 /* Mask register operand. */
582 mask_mode,
583 /* Mask register operand. */
584 mask_bd_mode,
585
586 es_reg,
587 cs_reg,
588 ss_reg,
589 ds_reg,
590 fs_reg,
591 gs_reg,
592
593 eAX_reg,
594 eCX_reg,
595 eDX_reg,
596 eBX_reg,
597 eSP_reg,
598 eBP_reg,
599 eSI_reg,
600 eDI_reg,
601
602 al_reg,
603 cl_reg,
604 dl_reg,
605 bl_reg,
606 ah_reg,
607 ch_reg,
608 dh_reg,
609 bh_reg,
610
611 ax_reg,
612 cx_reg,
613 dx_reg,
614 bx_reg,
615 sp_reg,
616 bp_reg,
617 si_reg,
618 di_reg,
619
620 rAX_reg,
621 rCX_reg,
622 rDX_reg,
623 rBX_reg,
624 rSP_reg,
625 rBP_reg,
626 rSI_reg,
627 rDI_reg,
628
629 z_mode_ax_reg,
630 indir_dx_reg
631 };
632
633 enum
634 {
635 FLOATCODE = 1,
636 USE_REG_TABLE,
637 USE_MOD_TABLE,
638 USE_RM_TABLE,
639 USE_PREFIX_TABLE,
640 USE_X86_64_TABLE,
641 USE_3BYTE_TABLE,
642 USE_XOP_8F_TABLE,
643 USE_VEX_C4_TABLE,
644 USE_VEX_C5_TABLE,
645 USE_VEX_LEN_TABLE,
646 USE_VEX_W_TABLE,
647 USE_EVEX_TABLE,
648 USE_EVEX_LEN_TABLE
649 };
650
651 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
652
653 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
654 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
655 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
656 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
657 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
658 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
659 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
660 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
661 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
662 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
663 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
664 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
665 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
666 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
667 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
668 #define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I))
669
670 enum
671 {
672 REG_80 = 0,
673 REG_81,
674 REG_83,
675 REG_8F,
676 REG_C0,
677 REG_C1,
678 REG_C6,
679 REG_C7,
680 REG_D0,
681 REG_D1,
682 REG_D2,
683 REG_D3,
684 REG_F6,
685 REG_F7,
686 REG_FE,
687 REG_FF,
688 REG_0F00,
689 REG_0F01,
690 REG_0F0D,
691 REG_0F18,
692 REG_0F1C_P_0_MOD_0,
693 REG_0F1E_P_1_MOD_3,
694 REG_0F38D8_PREFIX_1,
695 REG_0F3A0F_PREFIX_1_MOD_3,
696 REG_0F71,
697 REG_0F72,
698 REG_0F73,
699 REG_0FA6,
700 REG_0FA7,
701 REG_0FAE,
702 REG_0FBA,
703 REG_0FC7,
704 REG_VEX_0F71,
705 REG_VEX_0F72,
706 REG_VEX_0F73,
707 REG_VEX_0FAE,
708 REG_VEX_0F3849_X86_64_P_0_W_0_M_1,
709 REG_VEX_0F38F3,
710
711 REG_0FXOP_09_01_L_0,
712 REG_0FXOP_09_02_L_0,
713 REG_0FXOP_09_12_M_1_L_0,
714 REG_0FXOP_0A_12_L_0,
715
716 REG_EVEX_0F71,
717 REG_EVEX_0F72,
718 REG_EVEX_0F73,
719 REG_EVEX_0F38C6,
720 REG_EVEX_0F38C7
721 };
722
723 enum
724 {
725 MOD_8D = 0,
726 MOD_C6_REG_7,
727 MOD_C7_REG_7,
728 MOD_FF_REG_3,
729 MOD_FF_REG_5,
730 MOD_0F01_REG_0,
731 MOD_0F01_REG_1,
732 MOD_0F01_REG_2,
733 MOD_0F01_REG_3,
734 MOD_0F01_REG_5,
735 MOD_0F01_REG_7,
736 MOD_0F12_PREFIX_0,
737 MOD_0F12_PREFIX_2,
738 MOD_0F13,
739 MOD_0F16_PREFIX_0,
740 MOD_0F16_PREFIX_2,
741 MOD_0F17,
742 MOD_0F18_REG_0,
743 MOD_0F18_REG_1,
744 MOD_0F18_REG_2,
745 MOD_0F18_REG_3,
746 MOD_0F18_REG_4,
747 MOD_0F18_REG_5,
748 MOD_0F18_REG_6,
749 MOD_0F18_REG_7,
750 MOD_0F1A_PREFIX_0,
751 MOD_0F1B_PREFIX_0,
752 MOD_0F1B_PREFIX_1,
753 MOD_0F1C_PREFIX_0,
754 MOD_0F1E_PREFIX_1,
755 MOD_0F2B_PREFIX_0,
756 MOD_0F2B_PREFIX_1,
757 MOD_0F2B_PREFIX_2,
758 MOD_0F2B_PREFIX_3,
759 MOD_0F50,
760 MOD_0F71_REG_2,
761 MOD_0F71_REG_4,
762 MOD_0F71_REG_6,
763 MOD_0F72_REG_2,
764 MOD_0F72_REG_4,
765 MOD_0F72_REG_6,
766 MOD_0F73_REG_2,
767 MOD_0F73_REG_3,
768 MOD_0F73_REG_6,
769 MOD_0F73_REG_7,
770 MOD_0FAE_REG_0,
771 MOD_0FAE_REG_1,
772 MOD_0FAE_REG_2,
773 MOD_0FAE_REG_3,
774 MOD_0FAE_REG_4,
775 MOD_0FAE_REG_5,
776 MOD_0FAE_REG_6,
777 MOD_0FAE_REG_7,
778 MOD_0FB2,
779 MOD_0FB4,
780 MOD_0FB5,
781 MOD_0FC3,
782 MOD_0FC7_REG_3,
783 MOD_0FC7_REG_4,
784 MOD_0FC7_REG_5,
785 MOD_0FC7_REG_6,
786 MOD_0FC7_REG_7,
787 MOD_0FD7,
788 MOD_0FE7_PREFIX_2,
789 MOD_0FF0_PREFIX_3,
790 MOD_0F382A,
791 MOD_0F38DC_PREFIX_1,
792 MOD_0F38DD_PREFIX_1,
793 MOD_0F38DE_PREFIX_1,
794 MOD_0F38DF_PREFIX_1,
795 MOD_0F38F5,
796 MOD_0F38F6_PREFIX_0,
797 MOD_0F38F8_PREFIX_1,
798 MOD_0F38F8_PREFIX_2,
799 MOD_0F38F8_PREFIX_3,
800 MOD_0F38F9,
801 MOD_0F38FA_PREFIX_1,
802 MOD_0F38FB_PREFIX_1,
803 MOD_0F3A0F_PREFIX_1,
804 MOD_62_32BIT,
805 MOD_C4_32BIT,
806 MOD_C5_32BIT,
807 MOD_VEX_0F12_PREFIX_0,
808 MOD_VEX_0F12_PREFIX_2,
809 MOD_VEX_0F13,
810 MOD_VEX_0F16_PREFIX_0,
811 MOD_VEX_0F16_PREFIX_2,
812 MOD_VEX_0F17,
813 MOD_VEX_0F2B,
814 MOD_VEX_W_0_0F41_P_0_LEN_1,
815 MOD_VEX_W_1_0F41_P_0_LEN_1,
816 MOD_VEX_W_0_0F41_P_2_LEN_1,
817 MOD_VEX_W_1_0F41_P_2_LEN_1,
818 MOD_VEX_W_0_0F42_P_0_LEN_1,
819 MOD_VEX_W_1_0F42_P_0_LEN_1,
820 MOD_VEX_W_0_0F42_P_2_LEN_1,
821 MOD_VEX_W_1_0F42_P_2_LEN_1,
822 MOD_VEX_W_0_0F44_P_0_LEN_1,
823 MOD_VEX_W_1_0F44_P_0_LEN_1,
824 MOD_VEX_W_0_0F44_P_2_LEN_1,
825 MOD_VEX_W_1_0F44_P_2_LEN_1,
826 MOD_VEX_W_0_0F45_P_0_LEN_1,
827 MOD_VEX_W_1_0F45_P_0_LEN_1,
828 MOD_VEX_W_0_0F45_P_2_LEN_1,
829 MOD_VEX_W_1_0F45_P_2_LEN_1,
830 MOD_VEX_W_0_0F46_P_0_LEN_1,
831 MOD_VEX_W_1_0F46_P_0_LEN_1,
832 MOD_VEX_W_0_0F46_P_2_LEN_1,
833 MOD_VEX_W_1_0F46_P_2_LEN_1,
834 MOD_VEX_W_0_0F47_P_0_LEN_1,
835 MOD_VEX_W_1_0F47_P_0_LEN_1,
836 MOD_VEX_W_0_0F47_P_2_LEN_1,
837 MOD_VEX_W_1_0F47_P_2_LEN_1,
838 MOD_VEX_W_0_0F4A_P_0_LEN_1,
839 MOD_VEX_W_1_0F4A_P_0_LEN_1,
840 MOD_VEX_W_0_0F4A_P_2_LEN_1,
841 MOD_VEX_W_1_0F4A_P_2_LEN_1,
842 MOD_VEX_W_0_0F4B_P_0_LEN_1,
843 MOD_VEX_W_1_0F4B_P_0_LEN_1,
844 MOD_VEX_W_0_0F4B_P_2_LEN_1,
845 MOD_VEX_0F50,
846 MOD_VEX_0F71_REG_2,
847 MOD_VEX_0F71_REG_4,
848 MOD_VEX_0F71_REG_6,
849 MOD_VEX_0F72_REG_2,
850 MOD_VEX_0F72_REG_4,
851 MOD_VEX_0F72_REG_6,
852 MOD_VEX_0F73_REG_2,
853 MOD_VEX_0F73_REG_3,
854 MOD_VEX_0F73_REG_6,
855 MOD_VEX_0F73_REG_7,
856 MOD_VEX_W_0_0F91_P_0_LEN_0,
857 MOD_VEX_W_1_0F91_P_0_LEN_0,
858 MOD_VEX_W_0_0F91_P_2_LEN_0,
859 MOD_VEX_W_1_0F91_P_2_LEN_0,
860 MOD_VEX_W_0_0F92_P_0_LEN_0,
861 MOD_VEX_W_0_0F92_P_2_LEN_0,
862 MOD_VEX_0F92_P_3_LEN_0,
863 MOD_VEX_W_0_0F93_P_0_LEN_0,
864 MOD_VEX_W_0_0F93_P_2_LEN_0,
865 MOD_VEX_0F93_P_3_LEN_0,
866 MOD_VEX_W_0_0F98_P_0_LEN_0,
867 MOD_VEX_W_1_0F98_P_0_LEN_0,
868 MOD_VEX_W_0_0F98_P_2_LEN_0,
869 MOD_VEX_W_1_0F98_P_2_LEN_0,
870 MOD_VEX_W_0_0F99_P_0_LEN_0,
871 MOD_VEX_W_1_0F99_P_0_LEN_0,
872 MOD_VEX_W_0_0F99_P_2_LEN_0,
873 MOD_VEX_W_1_0F99_P_2_LEN_0,
874 MOD_VEX_0FAE_REG_2,
875 MOD_VEX_0FAE_REG_3,
876 MOD_VEX_0FD7,
877 MOD_VEX_0FE7,
878 MOD_VEX_0FF0_PREFIX_3,
879 MOD_VEX_0F381A,
880 MOD_VEX_0F382A,
881 MOD_VEX_0F382C,
882 MOD_VEX_0F382D,
883 MOD_VEX_0F382E,
884 MOD_VEX_0F382F,
885 MOD_VEX_0F3849_X86_64_P_0_W_0,
886 MOD_VEX_0F3849_X86_64_P_2_W_0,
887 MOD_VEX_0F3849_X86_64_P_3_W_0,
888 MOD_VEX_0F384B_X86_64_P_1_W_0,
889 MOD_VEX_0F384B_X86_64_P_2_W_0,
890 MOD_VEX_0F384B_X86_64_P_3_W_0,
891 MOD_VEX_0F385A,
892 MOD_VEX_0F385C_X86_64_P_1_W_0,
893 MOD_VEX_0F385E_X86_64_P_0_W_0,
894 MOD_VEX_0F385E_X86_64_P_1_W_0,
895 MOD_VEX_0F385E_X86_64_P_2_W_0,
896 MOD_VEX_0F385E_X86_64_P_3_W_0,
897 MOD_VEX_0F388C,
898 MOD_VEX_0F388E,
899 MOD_VEX_0F3A30_L_0,
900 MOD_VEX_0F3A31_L_0,
901 MOD_VEX_0F3A32_L_0,
902 MOD_VEX_0F3A33_L_0,
903
904 MOD_VEX_0FXOP_09_12,
905
906 MOD_EVEX_0F12_PREFIX_0,
907 MOD_EVEX_0F12_PREFIX_2,
908 MOD_EVEX_0F13,
909 MOD_EVEX_0F16_PREFIX_0,
910 MOD_EVEX_0F16_PREFIX_2,
911 MOD_EVEX_0F17,
912 MOD_EVEX_0F2B,
913 MOD_EVEX_0F381A_W_0,
914 MOD_EVEX_0F381A_W_1,
915 MOD_EVEX_0F381B_W_0,
916 MOD_EVEX_0F381B_W_1,
917 MOD_EVEX_0F3828_P_1,
918 MOD_EVEX_0F382A_P_1_W_1,
919 MOD_EVEX_0F3838_P_1,
920 MOD_EVEX_0F383A_P_1_W_0,
921 MOD_EVEX_0F385A_W_0,
922 MOD_EVEX_0F385A_W_1,
923 MOD_EVEX_0F385B_W_0,
924 MOD_EVEX_0F385B_W_1,
925 MOD_EVEX_0F387A_W_0,
926 MOD_EVEX_0F387B_W_0,
927 MOD_EVEX_0F387C,
928 MOD_EVEX_0F38C6_REG_1,
929 MOD_EVEX_0F38C6_REG_2,
930 MOD_EVEX_0F38C6_REG_5,
931 MOD_EVEX_0F38C6_REG_6,
932 MOD_EVEX_0F38C7_REG_1,
933 MOD_EVEX_0F38C7_REG_2,
934 MOD_EVEX_0F38C7_REG_5,
935 MOD_EVEX_0F38C7_REG_6
936 };
937
938 enum
939 {
940 RM_C6_REG_7 = 0,
941 RM_C7_REG_7,
942 RM_0F01_REG_0,
943 RM_0F01_REG_1,
944 RM_0F01_REG_2,
945 RM_0F01_REG_3,
946 RM_0F01_REG_5_MOD_3,
947 RM_0F01_REG_7_MOD_3,
948 RM_0F1E_P_1_MOD_3_REG_7,
949 RM_0F3A0F_P_1_MOD_3_REG_0,
950 RM_0FAE_REG_6_MOD_3_P_0,
951 RM_0FAE_REG_7_MOD_3,
952 RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0
953 };
954
955 enum
956 {
957 PREFIX_90 = 0,
958 PREFIX_0F01_REG_1_RM_4,
959 PREFIX_0F01_REG_1_RM_5,
960 PREFIX_0F01_REG_1_RM_6,
961 PREFIX_0F01_REG_1_RM_7,
962 PREFIX_0F01_REG_3_RM_1,
963 PREFIX_0F01_REG_5_MOD_0,
964 PREFIX_0F01_REG_5_MOD_3_RM_0,
965 PREFIX_0F01_REG_5_MOD_3_RM_1,
966 PREFIX_0F01_REG_5_MOD_3_RM_2,
967 PREFIX_0F01_REG_5_MOD_3_RM_4,
968 PREFIX_0F01_REG_5_MOD_3_RM_5,
969 PREFIX_0F01_REG_5_MOD_3_RM_6,
970 PREFIX_0F01_REG_5_MOD_3_RM_7,
971 PREFIX_0F01_REG_7_MOD_3_RM_2,
972 PREFIX_0F01_REG_7_MOD_3_RM_6,
973 PREFIX_0F01_REG_7_MOD_3_RM_7,
974 PREFIX_0F09,
975 PREFIX_0F10,
976 PREFIX_0F11,
977 PREFIX_0F12,
978 PREFIX_0F16,
979 PREFIX_0F1A,
980 PREFIX_0F1B,
981 PREFIX_0F1C,
982 PREFIX_0F1E,
983 PREFIX_0F2A,
984 PREFIX_0F2B,
985 PREFIX_0F2C,
986 PREFIX_0F2D,
987 PREFIX_0F2E,
988 PREFIX_0F2F,
989 PREFIX_0F51,
990 PREFIX_0F52,
991 PREFIX_0F53,
992 PREFIX_0F58,
993 PREFIX_0F59,
994 PREFIX_0F5A,
995 PREFIX_0F5B,
996 PREFIX_0F5C,
997 PREFIX_0F5D,
998 PREFIX_0F5E,
999 PREFIX_0F5F,
1000 PREFIX_0F60,
1001 PREFIX_0F61,
1002 PREFIX_0F62,
1003 PREFIX_0F6F,
1004 PREFIX_0F70,
1005 PREFIX_0F78,
1006 PREFIX_0F79,
1007 PREFIX_0F7C,
1008 PREFIX_0F7D,
1009 PREFIX_0F7E,
1010 PREFIX_0F7F,
1011 PREFIX_0FAE_REG_0_MOD_3,
1012 PREFIX_0FAE_REG_1_MOD_3,
1013 PREFIX_0FAE_REG_2_MOD_3,
1014 PREFIX_0FAE_REG_3_MOD_3,
1015 PREFIX_0FAE_REG_4_MOD_0,
1016 PREFIX_0FAE_REG_4_MOD_3,
1017 PREFIX_0FAE_REG_5_MOD_3,
1018 PREFIX_0FAE_REG_6_MOD_0,
1019 PREFIX_0FAE_REG_6_MOD_3,
1020 PREFIX_0FAE_REG_7_MOD_0,
1021 PREFIX_0FB8,
1022 PREFIX_0FBC,
1023 PREFIX_0FBD,
1024 PREFIX_0FC2,
1025 PREFIX_0FC7_REG_6_MOD_0,
1026 PREFIX_0FC7_REG_6_MOD_3,
1027 PREFIX_0FC7_REG_7_MOD_3,
1028 PREFIX_0FD0,
1029 PREFIX_0FD6,
1030 PREFIX_0FE6,
1031 PREFIX_0FE7,
1032 PREFIX_0FF0,
1033 PREFIX_0FF7,
1034 PREFIX_0F38D8,
1035 PREFIX_0F38DC,
1036 PREFIX_0F38DD,
1037 PREFIX_0F38DE,
1038 PREFIX_0F38DF,
1039 PREFIX_0F38F0,
1040 PREFIX_0F38F1,
1041 PREFIX_0F38F6,
1042 PREFIX_0F38F8,
1043 PREFIX_0F38FA,
1044 PREFIX_0F38FB,
1045 PREFIX_0F3A0F,
1046 PREFIX_VEX_0F10,
1047 PREFIX_VEX_0F11,
1048 PREFIX_VEX_0F12,
1049 PREFIX_VEX_0F16,
1050 PREFIX_VEX_0F2A,
1051 PREFIX_VEX_0F2C,
1052 PREFIX_VEX_0F2D,
1053 PREFIX_VEX_0F2E,
1054 PREFIX_VEX_0F2F,
1055 PREFIX_VEX_0F41,
1056 PREFIX_VEX_0F42,
1057 PREFIX_VEX_0F44,
1058 PREFIX_VEX_0F45,
1059 PREFIX_VEX_0F46,
1060 PREFIX_VEX_0F47,
1061 PREFIX_VEX_0F4A,
1062 PREFIX_VEX_0F4B,
1063 PREFIX_VEX_0F51,
1064 PREFIX_VEX_0F52,
1065 PREFIX_VEX_0F53,
1066 PREFIX_VEX_0F58,
1067 PREFIX_VEX_0F59,
1068 PREFIX_VEX_0F5A,
1069 PREFIX_VEX_0F5B,
1070 PREFIX_VEX_0F5C,
1071 PREFIX_VEX_0F5D,
1072 PREFIX_VEX_0F5E,
1073 PREFIX_VEX_0F5F,
1074 PREFIX_VEX_0F6F,
1075 PREFIX_VEX_0F70,
1076 PREFIX_VEX_0F7C,
1077 PREFIX_VEX_0F7D,
1078 PREFIX_VEX_0F7E,
1079 PREFIX_VEX_0F7F,
1080 PREFIX_VEX_0F90,
1081 PREFIX_VEX_0F91,
1082 PREFIX_VEX_0F92,
1083 PREFIX_VEX_0F93,
1084 PREFIX_VEX_0F98,
1085 PREFIX_VEX_0F99,
1086 PREFIX_VEX_0FC2,
1087 PREFIX_VEX_0FD0,
1088 PREFIX_VEX_0FE6,
1089 PREFIX_VEX_0FF0,
1090 PREFIX_VEX_0F3849_X86_64,
1091 PREFIX_VEX_0F384B_X86_64,
1092 PREFIX_VEX_0F385C_X86_64,
1093 PREFIX_VEX_0F385E_X86_64,
1094 PREFIX_VEX_0F38F5,
1095 PREFIX_VEX_0F38F6,
1096 PREFIX_VEX_0F38F7,
1097 PREFIX_VEX_0F3AF0,
1098
1099 PREFIX_EVEX_0F10,
1100 PREFIX_EVEX_0F11,
1101 PREFIX_EVEX_0F12,
1102 PREFIX_EVEX_0F16,
1103 PREFIX_EVEX_0F2A,
1104 PREFIX_EVEX_0F51,
1105 PREFIX_EVEX_0F58,
1106 PREFIX_EVEX_0F59,
1107 PREFIX_EVEX_0F5A,
1108 PREFIX_EVEX_0F5B,
1109 PREFIX_EVEX_0F5C,
1110 PREFIX_EVEX_0F5D,
1111 PREFIX_EVEX_0F5E,
1112 PREFIX_EVEX_0F5F,
1113 PREFIX_EVEX_0F6F,
1114 PREFIX_EVEX_0F70,
1115 PREFIX_EVEX_0F78,
1116 PREFIX_EVEX_0F79,
1117 PREFIX_EVEX_0F7A,
1118 PREFIX_EVEX_0F7B,
1119 PREFIX_EVEX_0F7E,
1120 PREFIX_EVEX_0F7F,
1121 PREFIX_EVEX_0FC2,
1122 PREFIX_EVEX_0FE6,
1123 PREFIX_EVEX_0F3810,
1124 PREFIX_EVEX_0F3811,
1125 PREFIX_EVEX_0F3812,
1126 PREFIX_EVEX_0F3813,
1127 PREFIX_EVEX_0F3814,
1128 PREFIX_EVEX_0F3815,
1129 PREFIX_EVEX_0F3820,
1130 PREFIX_EVEX_0F3821,
1131 PREFIX_EVEX_0F3822,
1132 PREFIX_EVEX_0F3823,
1133 PREFIX_EVEX_0F3824,
1134 PREFIX_EVEX_0F3825,
1135 PREFIX_EVEX_0F3826,
1136 PREFIX_EVEX_0F3827,
1137 PREFIX_EVEX_0F3828,
1138 PREFIX_EVEX_0F3829,
1139 PREFIX_EVEX_0F382A,
1140 PREFIX_EVEX_0F3830,
1141 PREFIX_EVEX_0F3831,
1142 PREFIX_EVEX_0F3832,
1143 PREFIX_EVEX_0F3833,
1144 PREFIX_EVEX_0F3834,
1145 PREFIX_EVEX_0F3835,
1146 PREFIX_EVEX_0F3838,
1147 PREFIX_EVEX_0F3839,
1148 PREFIX_EVEX_0F383A,
1149 PREFIX_EVEX_0F3852,
1150 PREFIX_EVEX_0F3853,
1151 PREFIX_EVEX_0F3868,
1152 PREFIX_EVEX_0F3872,
1153 PREFIX_EVEX_0F389A,
1154 PREFIX_EVEX_0F389B,
1155 PREFIX_EVEX_0F38AA,
1156 PREFIX_EVEX_0F38AB,
1157 };
1158
1159 enum
1160 {
1161 X86_64_06 = 0,
1162 X86_64_07,
1163 X86_64_0E,
1164 X86_64_16,
1165 X86_64_17,
1166 X86_64_1E,
1167 X86_64_1F,
1168 X86_64_27,
1169 X86_64_2F,
1170 X86_64_37,
1171 X86_64_3F,
1172 X86_64_60,
1173 X86_64_61,
1174 X86_64_62,
1175 X86_64_63,
1176 X86_64_6D,
1177 X86_64_6F,
1178 X86_64_82,
1179 X86_64_9A,
1180 X86_64_C2,
1181 X86_64_C3,
1182 X86_64_C4,
1183 X86_64_C5,
1184 X86_64_CE,
1185 X86_64_D4,
1186 X86_64_D5,
1187 X86_64_E8,
1188 X86_64_E9,
1189 X86_64_EA,
1190 X86_64_0F01_REG_0,
1191 X86_64_0F01_REG_1,
1192 X86_64_0F01_REG_1_RM_5_PREFIX_2,
1193 X86_64_0F01_REG_1_RM_6_PREFIX_2,
1194 X86_64_0F01_REG_1_RM_7_PREFIX_2,
1195 X86_64_0F01_REG_2,
1196 X86_64_0F01_REG_3,
1197 X86_64_0F24,
1198 X86_64_0F26,
1199 X86_64_VEX_0F3849,
1200 X86_64_VEX_0F384B,
1201 X86_64_VEX_0F385C,
1202 X86_64_VEX_0F385E,
1203 X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1,
1204 X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1,
1205 X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1,
1206 X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1,
1207 X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1,
1208 X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3,
1209 X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1,
1210 X86_64_0FC7_REG_6_MOD_3_PREFIX_1
1211 };
1212
1213 enum
1214 {
1215 THREE_BYTE_0F38 = 0,
1216 THREE_BYTE_0F3A
1217 };
1218
1219 enum
1220 {
1221 XOP_08 = 0,
1222 XOP_09,
1223 XOP_0A
1224 };
1225
1226 enum
1227 {
1228 VEX_0F = 0,
1229 VEX_0F38,
1230 VEX_0F3A
1231 };
1232
1233 enum
1234 {
1235 EVEX_0F = 0,
1236 EVEX_0F38,
1237 EVEX_0F3A
1238 };
1239
1240 enum
1241 {
1242 VEX_LEN_0F12_P_0_M_0 = 0,
1243 VEX_LEN_0F12_P_0_M_1,
1244 #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0
1245 VEX_LEN_0F13_M_0,
1246 VEX_LEN_0F16_P_0_M_0,
1247 VEX_LEN_0F16_P_0_M_1,
1248 #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0
1249 VEX_LEN_0F17_M_0,
1250 VEX_LEN_0F41_P_0,
1251 VEX_LEN_0F41_P_2,
1252 VEX_LEN_0F42_P_0,
1253 VEX_LEN_0F42_P_2,
1254 VEX_LEN_0F44_P_0,
1255 VEX_LEN_0F44_P_2,
1256 VEX_LEN_0F45_P_0,
1257 VEX_LEN_0F45_P_2,
1258 VEX_LEN_0F46_P_0,
1259 VEX_LEN_0F46_P_2,
1260 VEX_LEN_0F47_P_0,
1261 VEX_LEN_0F47_P_2,
1262 VEX_LEN_0F4A_P_0,
1263 VEX_LEN_0F4A_P_2,
1264 VEX_LEN_0F4B_P_0,
1265 VEX_LEN_0F4B_P_2,
1266 VEX_LEN_0F6E,
1267 VEX_LEN_0F77,
1268 VEX_LEN_0F7E_P_1,
1269 VEX_LEN_0F7E_P_2,
1270 VEX_LEN_0F90_P_0,
1271 VEX_LEN_0F90_P_2,
1272 VEX_LEN_0F91_P_0,
1273 VEX_LEN_0F91_P_2,
1274 VEX_LEN_0F92_P_0,
1275 VEX_LEN_0F92_P_2,
1276 VEX_LEN_0F92_P_3,
1277 VEX_LEN_0F93_P_0,
1278 VEX_LEN_0F93_P_2,
1279 VEX_LEN_0F93_P_3,
1280 VEX_LEN_0F98_P_0,
1281 VEX_LEN_0F98_P_2,
1282 VEX_LEN_0F99_P_0,
1283 VEX_LEN_0F99_P_2,
1284 VEX_LEN_0FAE_R_2_M_0,
1285 VEX_LEN_0FAE_R_3_M_0,
1286 VEX_LEN_0FC4,
1287 VEX_LEN_0FC5,
1288 VEX_LEN_0FD6,
1289 VEX_LEN_0FF7,
1290 VEX_LEN_0F3816,
1291 VEX_LEN_0F3819,
1292 VEX_LEN_0F381A_M_0,
1293 VEX_LEN_0F3836,
1294 VEX_LEN_0F3841,
1295 VEX_LEN_0F3849_X86_64_P_0_W_0_M_0,
1296 VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0,
1297 VEX_LEN_0F3849_X86_64_P_2_W_0_M_0,
1298 VEX_LEN_0F3849_X86_64_P_3_W_0_M_0,
1299 VEX_LEN_0F384B_X86_64_P_1_W_0_M_0,
1300 VEX_LEN_0F384B_X86_64_P_2_W_0_M_0,
1301 VEX_LEN_0F384B_X86_64_P_3_W_0_M_0,
1302 VEX_LEN_0F385A_M_0,
1303 VEX_LEN_0F385C_X86_64_P_1_W_0_M_0,
1304 VEX_LEN_0F385E_X86_64_P_0_W_0_M_0,
1305 VEX_LEN_0F385E_X86_64_P_1_W_0_M_0,
1306 VEX_LEN_0F385E_X86_64_P_2_W_0_M_0,
1307 VEX_LEN_0F385E_X86_64_P_3_W_0_M_0,
1308 VEX_LEN_0F38DB,
1309 VEX_LEN_0F38F2,
1310 VEX_LEN_0F38F3_R_1,
1311 VEX_LEN_0F38F3_R_2,
1312 VEX_LEN_0F38F3_R_3,
1313 VEX_LEN_0F38F5_P_0,
1314 VEX_LEN_0F38F5_P_1,
1315 VEX_LEN_0F38F5_P_3,
1316 VEX_LEN_0F38F6_P_3,
1317 VEX_LEN_0F38F7_P_0,
1318 VEX_LEN_0F38F7_P_1,
1319 VEX_LEN_0F38F7_P_2,
1320 VEX_LEN_0F38F7_P_3,
1321 VEX_LEN_0F3A00,
1322 VEX_LEN_0F3A01,
1323 VEX_LEN_0F3A06,
1324 VEX_LEN_0F3A14,
1325 VEX_LEN_0F3A15,
1326 VEX_LEN_0F3A16,
1327 VEX_LEN_0F3A17,
1328 VEX_LEN_0F3A18,
1329 VEX_LEN_0F3A19,
1330 VEX_LEN_0F3A20,
1331 VEX_LEN_0F3A21,
1332 VEX_LEN_0F3A22,
1333 VEX_LEN_0F3A30,
1334 VEX_LEN_0F3A31,
1335 VEX_LEN_0F3A32,
1336 VEX_LEN_0F3A33,
1337 VEX_LEN_0F3A38,
1338 VEX_LEN_0F3A39,
1339 VEX_LEN_0F3A41,
1340 VEX_LEN_0F3A46,
1341 VEX_LEN_0F3A60,
1342 VEX_LEN_0F3A61,
1343 VEX_LEN_0F3A62,
1344 VEX_LEN_0F3A63,
1345 VEX_LEN_0F3ADF,
1346 VEX_LEN_0F3AF0_P_3,
1347 VEX_LEN_0FXOP_08_85,
1348 VEX_LEN_0FXOP_08_86,
1349 VEX_LEN_0FXOP_08_87,
1350 VEX_LEN_0FXOP_08_8E,
1351 VEX_LEN_0FXOP_08_8F,
1352 VEX_LEN_0FXOP_08_95,
1353 VEX_LEN_0FXOP_08_96,
1354 VEX_LEN_0FXOP_08_97,
1355 VEX_LEN_0FXOP_08_9E,
1356 VEX_LEN_0FXOP_08_9F,
1357 VEX_LEN_0FXOP_08_A3,
1358 VEX_LEN_0FXOP_08_A6,
1359 VEX_LEN_0FXOP_08_B6,
1360 VEX_LEN_0FXOP_08_C0,
1361 VEX_LEN_0FXOP_08_C1,
1362 VEX_LEN_0FXOP_08_C2,
1363 VEX_LEN_0FXOP_08_C3,
1364 VEX_LEN_0FXOP_08_CC,
1365 VEX_LEN_0FXOP_08_CD,
1366 VEX_LEN_0FXOP_08_CE,
1367 VEX_LEN_0FXOP_08_CF,
1368 VEX_LEN_0FXOP_08_EC,
1369 VEX_LEN_0FXOP_08_ED,
1370 VEX_LEN_0FXOP_08_EE,
1371 VEX_LEN_0FXOP_08_EF,
1372 VEX_LEN_0FXOP_09_01,
1373 VEX_LEN_0FXOP_09_02,
1374 VEX_LEN_0FXOP_09_12_M_1,
1375 VEX_LEN_0FXOP_09_82_W_0,
1376 VEX_LEN_0FXOP_09_83_W_0,
1377 VEX_LEN_0FXOP_09_90,
1378 VEX_LEN_0FXOP_09_91,
1379 VEX_LEN_0FXOP_09_92,
1380 VEX_LEN_0FXOP_09_93,
1381 VEX_LEN_0FXOP_09_94,
1382 VEX_LEN_0FXOP_09_95,
1383 VEX_LEN_0FXOP_09_96,
1384 VEX_LEN_0FXOP_09_97,
1385 VEX_LEN_0FXOP_09_98,
1386 VEX_LEN_0FXOP_09_99,
1387 VEX_LEN_0FXOP_09_9A,
1388 VEX_LEN_0FXOP_09_9B,
1389 VEX_LEN_0FXOP_09_C1,
1390 VEX_LEN_0FXOP_09_C2,
1391 VEX_LEN_0FXOP_09_C3,
1392 VEX_LEN_0FXOP_09_C6,
1393 VEX_LEN_0FXOP_09_C7,
1394 VEX_LEN_0FXOP_09_CB,
1395 VEX_LEN_0FXOP_09_D1,
1396 VEX_LEN_0FXOP_09_D2,
1397 VEX_LEN_0FXOP_09_D3,
1398 VEX_LEN_0FXOP_09_D6,
1399 VEX_LEN_0FXOP_09_D7,
1400 VEX_LEN_0FXOP_09_DB,
1401 VEX_LEN_0FXOP_09_E1,
1402 VEX_LEN_0FXOP_09_E2,
1403 VEX_LEN_0FXOP_09_E3,
1404 VEX_LEN_0FXOP_0A_12,
1405 };
1406
1407 enum
1408 {
1409 EVEX_LEN_0F6E = 0,
1410 EVEX_LEN_0F7E_P_1,
1411 EVEX_LEN_0F7E_P_2,
1412 EVEX_LEN_0FC4,
1413 EVEX_LEN_0FC5,
1414 EVEX_LEN_0FD6,
1415 EVEX_LEN_0F3816,
1416 EVEX_LEN_0F3819_W_0,
1417 EVEX_LEN_0F3819_W_1,
1418 EVEX_LEN_0F381A_W_0_M_0,
1419 EVEX_LEN_0F381A_W_1_M_0,
1420 EVEX_LEN_0F381B_W_0_M_0,
1421 EVEX_LEN_0F381B_W_1_M_0,
1422 EVEX_LEN_0F3836,
1423 EVEX_LEN_0F385A_W_0_M_0,
1424 EVEX_LEN_0F385A_W_1_M_0,
1425 EVEX_LEN_0F385B_W_0_M_0,
1426 EVEX_LEN_0F385B_W_1_M_0,
1427 EVEX_LEN_0F38C6_R_1_M_0,
1428 EVEX_LEN_0F38C6_R_2_M_0,
1429 EVEX_LEN_0F38C6_R_5_M_0,
1430 EVEX_LEN_0F38C6_R_6_M_0,
1431 EVEX_LEN_0F38C7_R_1_M_0_W_0,
1432 EVEX_LEN_0F38C7_R_1_M_0_W_1,
1433 EVEX_LEN_0F38C7_R_2_M_0_W_0,
1434 EVEX_LEN_0F38C7_R_2_M_0_W_1,
1435 EVEX_LEN_0F38C7_R_5_M_0_W_0,
1436 EVEX_LEN_0F38C7_R_5_M_0_W_1,
1437 EVEX_LEN_0F38C7_R_6_M_0_W_0,
1438 EVEX_LEN_0F38C7_R_6_M_0_W_1,
1439 EVEX_LEN_0F3A00_W_1,
1440 EVEX_LEN_0F3A01_W_1,
1441 EVEX_LEN_0F3A14,
1442 EVEX_LEN_0F3A15,
1443 EVEX_LEN_0F3A16,
1444 EVEX_LEN_0F3A17,
1445 EVEX_LEN_0F3A18_W_0,
1446 EVEX_LEN_0F3A18_W_1,
1447 EVEX_LEN_0F3A19_W_0,
1448 EVEX_LEN_0F3A19_W_1,
1449 EVEX_LEN_0F3A1A_W_0,
1450 EVEX_LEN_0F3A1A_W_1,
1451 EVEX_LEN_0F3A1B_W_0,
1452 EVEX_LEN_0F3A1B_W_1,
1453 EVEX_LEN_0F3A20,
1454 EVEX_LEN_0F3A21_W_0,
1455 EVEX_LEN_0F3A22,
1456 EVEX_LEN_0F3A23_W_0,
1457 EVEX_LEN_0F3A23_W_1,
1458 EVEX_LEN_0F3A38_W_0,
1459 EVEX_LEN_0F3A38_W_1,
1460 EVEX_LEN_0F3A39_W_0,
1461 EVEX_LEN_0F3A39_W_1,
1462 EVEX_LEN_0F3A3A_W_0,
1463 EVEX_LEN_0F3A3A_W_1,
1464 EVEX_LEN_0F3A3B_W_0,
1465 EVEX_LEN_0F3A3B_W_1,
1466 EVEX_LEN_0F3A43_W_0,
1467 EVEX_LEN_0F3A43_W_1
1468 };
1469
1470 enum
1471 {
1472 VEX_W_0F41_P_0_LEN_1 = 0,
1473 VEX_W_0F41_P_2_LEN_1,
1474 VEX_W_0F42_P_0_LEN_1,
1475 VEX_W_0F42_P_2_LEN_1,
1476 VEX_W_0F44_P_0_LEN_0,
1477 VEX_W_0F44_P_2_LEN_0,
1478 VEX_W_0F45_P_0_LEN_1,
1479 VEX_W_0F45_P_2_LEN_1,
1480 VEX_W_0F46_P_0_LEN_1,
1481 VEX_W_0F46_P_2_LEN_1,
1482 VEX_W_0F47_P_0_LEN_1,
1483 VEX_W_0F47_P_2_LEN_1,
1484 VEX_W_0F4A_P_0_LEN_1,
1485 VEX_W_0F4A_P_2_LEN_1,
1486 VEX_W_0F4B_P_0_LEN_1,
1487 VEX_W_0F4B_P_2_LEN_1,
1488 VEX_W_0F90_P_0_LEN_0,
1489 VEX_W_0F90_P_2_LEN_0,
1490 VEX_W_0F91_P_0_LEN_0,
1491 VEX_W_0F91_P_2_LEN_0,
1492 VEX_W_0F92_P_0_LEN_0,
1493 VEX_W_0F92_P_2_LEN_0,
1494 VEX_W_0F93_P_0_LEN_0,
1495 VEX_W_0F93_P_2_LEN_0,
1496 VEX_W_0F98_P_0_LEN_0,
1497 VEX_W_0F98_P_2_LEN_0,
1498 VEX_W_0F99_P_0_LEN_0,
1499 VEX_W_0F99_P_2_LEN_0,
1500 VEX_W_0F380C,
1501 VEX_W_0F380D,
1502 VEX_W_0F380E,
1503 VEX_W_0F380F,
1504 VEX_W_0F3813,
1505 VEX_W_0F3816_L_1,
1506 VEX_W_0F3818,
1507 VEX_W_0F3819_L_1,
1508 VEX_W_0F381A_M_0_L_1,
1509 VEX_W_0F382C_M_0,
1510 VEX_W_0F382D_M_0,
1511 VEX_W_0F382E_M_0,
1512 VEX_W_0F382F_M_0,
1513 VEX_W_0F3836,
1514 VEX_W_0F3846,
1515 VEX_W_0F3849_X86_64_P_0,
1516 VEX_W_0F3849_X86_64_P_2,
1517 VEX_W_0F3849_X86_64_P_3,
1518 VEX_W_0F384B_X86_64_P_1,
1519 VEX_W_0F384B_X86_64_P_2,
1520 VEX_W_0F384B_X86_64_P_3,
1521 VEX_W_0F3850,
1522 VEX_W_0F3851,
1523 VEX_W_0F3852,
1524 VEX_W_0F3853,
1525 VEX_W_0F3858,
1526 VEX_W_0F3859,
1527 VEX_W_0F385A_M_0_L_0,
1528 VEX_W_0F385C_X86_64_P_1,
1529 VEX_W_0F385E_X86_64_P_0,
1530 VEX_W_0F385E_X86_64_P_1,
1531 VEX_W_0F385E_X86_64_P_2,
1532 VEX_W_0F385E_X86_64_P_3,
1533 VEX_W_0F3878,
1534 VEX_W_0F3879,
1535 VEX_W_0F38CF,
1536 VEX_W_0F3A00_L_1,
1537 VEX_W_0F3A01_L_1,
1538 VEX_W_0F3A02,
1539 VEX_W_0F3A04,
1540 VEX_W_0F3A05,
1541 VEX_W_0F3A06_L_1,
1542 VEX_W_0F3A18_L_1,
1543 VEX_W_0F3A19_L_1,
1544 VEX_W_0F3A1D,
1545 VEX_W_0F3A38_L_1,
1546 VEX_W_0F3A39_L_1,
1547 VEX_W_0F3A46_L_1,
1548 VEX_W_0F3A4A,
1549 VEX_W_0F3A4B,
1550 VEX_W_0F3A4C,
1551 VEX_W_0F3ACE,
1552 VEX_W_0F3ACF,
1553
1554 VEX_W_0FXOP_08_85_L_0,
1555 VEX_W_0FXOP_08_86_L_0,
1556 VEX_W_0FXOP_08_87_L_0,
1557 VEX_W_0FXOP_08_8E_L_0,
1558 VEX_W_0FXOP_08_8F_L_0,
1559 VEX_W_0FXOP_08_95_L_0,
1560 VEX_W_0FXOP_08_96_L_0,
1561 VEX_W_0FXOP_08_97_L_0,
1562 VEX_W_0FXOP_08_9E_L_0,
1563 VEX_W_0FXOP_08_9F_L_0,
1564 VEX_W_0FXOP_08_A6_L_0,
1565 VEX_W_0FXOP_08_B6_L_0,
1566 VEX_W_0FXOP_08_C0_L_0,
1567 VEX_W_0FXOP_08_C1_L_0,
1568 VEX_W_0FXOP_08_C2_L_0,
1569 VEX_W_0FXOP_08_C3_L_0,
1570 VEX_W_0FXOP_08_CC_L_0,
1571 VEX_W_0FXOP_08_CD_L_0,
1572 VEX_W_0FXOP_08_CE_L_0,
1573 VEX_W_0FXOP_08_CF_L_0,
1574 VEX_W_0FXOP_08_EC_L_0,
1575 VEX_W_0FXOP_08_ED_L_0,
1576 VEX_W_0FXOP_08_EE_L_0,
1577 VEX_W_0FXOP_08_EF_L_0,
1578
1579 VEX_W_0FXOP_09_80,
1580 VEX_W_0FXOP_09_81,
1581 VEX_W_0FXOP_09_82,
1582 VEX_W_0FXOP_09_83,
1583 VEX_W_0FXOP_09_C1_L_0,
1584 VEX_W_0FXOP_09_C2_L_0,
1585 VEX_W_0FXOP_09_C3_L_0,
1586 VEX_W_0FXOP_09_C6_L_0,
1587 VEX_W_0FXOP_09_C7_L_0,
1588 VEX_W_0FXOP_09_CB_L_0,
1589 VEX_W_0FXOP_09_D1_L_0,
1590 VEX_W_0FXOP_09_D2_L_0,
1591 VEX_W_0FXOP_09_D3_L_0,
1592 VEX_W_0FXOP_09_D6_L_0,
1593 VEX_W_0FXOP_09_D7_L_0,
1594 VEX_W_0FXOP_09_DB_L_0,
1595 VEX_W_0FXOP_09_E1_L_0,
1596 VEX_W_0FXOP_09_E2_L_0,
1597 VEX_W_0FXOP_09_E3_L_0,
1598
1599 EVEX_W_0F10_P_1,
1600 EVEX_W_0F10_P_3,
1601 EVEX_W_0F11_P_1,
1602 EVEX_W_0F11_P_3,
1603 EVEX_W_0F12_P_0_M_1,
1604 EVEX_W_0F12_P_1,
1605 EVEX_W_0F12_P_3,
1606 EVEX_W_0F16_P_0_M_1,
1607 EVEX_W_0F16_P_1,
1608 EVEX_W_0F2A_P_3,
1609 EVEX_W_0F51_P_1,
1610 EVEX_W_0F51_P_3,
1611 EVEX_W_0F58_P_1,
1612 EVEX_W_0F58_P_3,
1613 EVEX_W_0F59_P_1,
1614 EVEX_W_0F59_P_3,
1615 EVEX_W_0F5A_P_0,
1616 EVEX_W_0F5A_P_1,
1617 EVEX_W_0F5A_P_2,
1618 EVEX_W_0F5A_P_3,
1619 EVEX_W_0F5B_P_0,
1620 EVEX_W_0F5B_P_1,
1621 EVEX_W_0F5B_P_2,
1622 EVEX_W_0F5C_P_1,
1623 EVEX_W_0F5C_P_3,
1624 EVEX_W_0F5D_P_1,
1625 EVEX_W_0F5D_P_3,
1626 EVEX_W_0F5E_P_1,
1627 EVEX_W_0F5E_P_3,
1628 EVEX_W_0F5F_P_1,
1629 EVEX_W_0F5F_P_3,
1630 EVEX_W_0F62,
1631 EVEX_W_0F66,
1632 EVEX_W_0F6A,
1633 EVEX_W_0F6B,
1634 EVEX_W_0F6C,
1635 EVEX_W_0F6D,
1636 EVEX_W_0F6F_P_1,
1637 EVEX_W_0F6F_P_2,
1638 EVEX_W_0F6F_P_3,
1639 EVEX_W_0F70_P_2,
1640 EVEX_W_0F72_R_2,
1641 EVEX_W_0F72_R_6,
1642 EVEX_W_0F73_R_2,
1643 EVEX_W_0F73_R_6,
1644 EVEX_W_0F76,
1645 EVEX_W_0F78_P_0,
1646 EVEX_W_0F78_P_2,
1647 EVEX_W_0F79_P_0,
1648 EVEX_W_0F79_P_2,
1649 EVEX_W_0F7A_P_1,
1650 EVEX_W_0F7A_P_2,
1651 EVEX_W_0F7A_P_3,
1652 EVEX_W_0F7B_P_2,
1653 EVEX_W_0F7B_P_3,
1654 EVEX_W_0F7E_P_1,
1655 EVEX_W_0F7F_P_1,
1656 EVEX_W_0F7F_P_2,
1657 EVEX_W_0F7F_P_3,
1658 EVEX_W_0FC2_P_1,
1659 EVEX_W_0FC2_P_3,
1660 EVEX_W_0FD2,
1661 EVEX_W_0FD3,
1662 EVEX_W_0FD4,
1663 EVEX_W_0FD6_L_0,
1664 EVEX_W_0FE6_P_1,
1665 EVEX_W_0FE6_P_2,
1666 EVEX_W_0FE6_P_3,
1667 EVEX_W_0FE7,
1668 EVEX_W_0FF2,
1669 EVEX_W_0FF3,
1670 EVEX_W_0FF4,
1671 EVEX_W_0FFA,
1672 EVEX_W_0FFB,
1673 EVEX_W_0FFE,
1674 EVEX_W_0F380D,
1675 EVEX_W_0F3810_P_1,
1676 EVEX_W_0F3810_P_2,
1677 EVEX_W_0F3811_P_1,
1678 EVEX_W_0F3811_P_2,
1679 EVEX_W_0F3812_P_1,
1680 EVEX_W_0F3812_P_2,
1681 EVEX_W_0F3813_P_1,
1682 EVEX_W_0F3813_P_2,
1683 EVEX_W_0F3814_P_1,
1684 EVEX_W_0F3815_P_1,
1685 EVEX_W_0F3819,
1686 EVEX_W_0F381A,
1687 EVEX_W_0F381B,
1688 EVEX_W_0F381E,
1689 EVEX_W_0F381F,
1690 EVEX_W_0F3820_P_1,
1691 EVEX_W_0F3821_P_1,
1692 EVEX_W_0F3822_P_1,
1693 EVEX_W_0F3823_P_1,
1694 EVEX_W_0F3824_P_1,
1695 EVEX_W_0F3825_P_1,
1696 EVEX_W_0F3825_P_2,
1697 EVEX_W_0F3828_P_2,
1698 EVEX_W_0F3829_P_2,
1699 EVEX_W_0F382A_P_1,
1700 EVEX_W_0F382A_P_2,
1701 EVEX_W_0F382B,
1702 EVEX_W_0F3830_P_1,
1703 EVEX_W_0F3831_P_1,
1704 EVEX_W_0F3832_P_1,
1705 EVEX_W_0F3833_P_1,
1706 EVEX_W_0F3834_P_1,
1707 EVEX_W_0F3835_P_1,
1708 EVEX_W_0F3835_P_2,
1709 EVEX_W_0F3837,
1710 EVEX_W_0F383A_P_1,
1711 EVEX_W_0F3852_P_1,
1712 EVEX_W_0F3859,
1713 EVEX_W_0F385A,
1714 EVEX_W_0F385B,
1715 EVEX_W_0F3870,
1716 EVEX_W_0F3872_P_1,
1717 EVEX_W_0F3872_P_2,
1718 EVEX_W_0F3872_P_3,
1719 EVEX_W_0F387A,
1720 EVEX_W_0F387B,
1721 EVEX_W_0F3883,
1722 EVEX_W_0F3891,
1723 EVEX_W_0F3893,
1724 EVEX_W_0F38A1,
1725 EVEX_W_0F38A3,
1726 EVEX_W_0F38C7_R_1_M_0,
1727 EVEX_W_0F38C7_R_2_M_0,
1728 EVEX_W_0F38C7_R_5_M_0,
1729 EVEX_W_0F38C7_R_6_M_0,
1730
1731 EVEX_W_0F3A00,
1732 EVEX_W_0F3A01,
1733 EVEX_W_0F3A05,
1734 EVEX_W_0F3A08,
1735 EVEX_W_0F3A09,
1736 EVEX_W_0F3A0A,
1737 EVEX_W_0F3A0B,
1738 EVEX_W_0F3A18,
1739 EVEX_W_0F3A19,
1740 EVEX_W_0F3A1A,
1741 EVEX_W_0F3A1B,
1742 EVEX_W_0F3A21,
1743 EVEX_W_0F3A23,
1744 EVEX_W_0F3A38,
1745 EVEX_W_0F3A39,
1746 EVEX_W_0F3A3A,
1747 EVEX_W_0F3A3B,
1748 EVEX_W_0F3A42,
1749 EVEX_W_0F3A43,
1750 EVEX_W_0F3A70,
1751 EVEX_W_0F3A72,
1752 };
1753
1754 typedef void (*op_rtn) (int bytemode, int sizeflag);
1755
1756 struct dis386 {
1757 const char *name;
1758 struct
1759 {
1760 op_rtn rtn;
1761 int bytemode;
1762 } op[MAX_OPERANDS];
1763 unsigned int prefix_requirement;
1764 };
1765
1766 /* Upper case letters in the instruction names here are macros.
1767 'A' => print 'b' if no register operands or suffix_always is true
1768 'B' => print 'b' if suffix_always is true
1769 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1770 size prefix
1771 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1772 suffix_always is true
1773 'E' => print 'e' if 32-bit form of jcxz
1774 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1775 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1776 'H' => print ",pt" or ",pn" branch hint
1777 'I' unused.
1778 'J' unused.
1779 'K' => print 'd' or 'q' if rex prefix is present.
1780 'L' unused.
1781 'M' => print 'r' if intel_mnemonic is false.
1782 'N' => print 'n' if instruction has no wait "prefix"
1783 'O' => print 'd' or 'o' (or 'q' in Intel mode)
1784 'P' => behave as 'T' except with register operand outside of suffix_always
1785 mode
1786 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1787 is true
1788 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1789 'S' => print 'w', 'l' or 'q' if suffix_always is true
1790 'T' => print 'w', 'l'/'d', or 'q' if instruction has an operand size
1791 prefix or if suffix_always is true.
1792 'U' unused.
1793 'V' unused.
1794 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1795 'X' => print 's', 'd' depending on data16 prefix (for XMM)
1796 'Y' unused.
1797 'Z' => print 'q' in 64bit mode and 'l' otherwise, if suffix_always is true.
1798 '!' => change condition from true to false or from false to true.
1799 '%' => add 1 upper case letter to the macro.
1800 '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
1801 prefix or suffix_always is true (lcall/ljmp).
1802 '@' => in 64bit mode for Intel64 ISA or if instruction
1803 has no operand sizing prefix, print 'q' if suffix_always is true or
1804 nothing otherwise; behave as 'P' in all other cases
1805
1806 2 upper case letter macros:
1807 "XY" => print 'x' or 'y' if suffix_always is true or no register
1808 operands and no broadcast.
1809 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
1810 register operands and no broadcast.
1811 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1812 "XV" => print "{vex3}" pseudo prefix
1813 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond
1814 being false, or no operand at all in 64bit mode, or if suffix_always
1815 is true.
1816 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1817 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1818 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1819 "DQ" => print 'd' or 'q' depending on the VEX.W bit
1820 "BW" => print 'b' or 'w' depending on the VEX.W bit
1821 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
1822 an operand size prefix, or suffix_always is true. print
1823 'q' if rex prefix is present.
1824
1825 Many of the above letters print nothing in Intel mode. See "putop"
1826 for the details.
1827
1828 Braces '{' and '}', and vertical bars '|', indicate alternative
1829 mnemonic strings for AT&T and Intel. */
1830
1831 static const struct dis386 dis386[] = {
1832 /* 00 */
1833 { "addB", { Ebh1, Gb }, 0 },
1834 { "addS", { Evh1, Gv }, 0 },
1835 { "addB", { Gb, EbS }, 0 },
1836 { "addS", { Gv, EvS }, 0 },
1837 { "addB", { AL, Ib }, 0 },
1838 { "addS", { eAX, Iv }, 0 },
1839 { X86_64_TABLE (X86_64_06) },
1840 { X86_64_TABLE (X86_64_07) },
1841 /* 08 */
1842 { "orB", { Ebh1, Gb }, 0 },
1843 { "orS", { Evh1, Gv }, 0 },
1844 { "orB", { Gb, EbS }, 0 },
1845 { "orS", { Gv, EvS }, 0 },
1846 { "orB", { AL, Ib }, 0 },
1847 { "orS", { eAX, Iv }, 0 },
1848 { X86_64_TABLE (X86_64_0E) },
1849 { Bad_Opcode }, /* 0x0f extended opcode escape */
1850 /* 10 */
1851 { "adcB", { Ebh1, Gb }, 0 },
1852 { "adcS", { Evh1, Gv }, 0 },
1853 { "adcB", { Gb, EbS }, 0 },
1854 { "adcS", { Gv, EvS }, 0 },
1855 { "adcB", { AL, Ib }, 0 },
1856 { "adcS", { eAX, Iv }, 0 },
1857 { X86_64_TABLE (X86_64_16) },
1858 { X86_64_TABLE (X86_64_17) },
1859 /* 18 */
1860 { "sbbB", { Ebh1, Gb }, 0 },
1861 { "sbbS", { Evh1, Gv }, 0 },
1862 { "sbbB", { Gb, EbS }, 0 },
1863 { "sbbS", { Gv, EvS }, 0 },
1864 { "sbbB", { AL, Ib }, 0 },
1865 { "sbbS", { eAX, Iv }, 0 },
1866 { X86_64_TABLE (X86_64_1E) },
1867 { X86_64_TABLE (X86_64_1F) },
1868 /* 20 */
1869 { "andB", { Ebh1, Gb }, 0 },
1870 { "andS", { Evh1, Gv }, 0 },
1871 { "andB", { Gb, EbS }, 0 },
1872 { "andS", { Gv, EvS }, 0 },
1873 { "andB", { AL, Ib }, 0 },
1874 { "andS", { eAX, Iv }, 0 },
1875 { Bad_Opcode }, /* SEG ES prefix */
1876 { X86_64_TABLE (X86_64_27) },
1877 /* 28 */
1878 { "subB", { Ebh1, Gb }, 0 },
1879 { "subS", { Evh1, Gv }, 0 },
1880 { "subB", { Gb, EbS }, 0 },
1881 { "subS", { Gv, EvS }, 0 },
1882 { "subB", { AL, Ib }, 0 },
1883 { "subS", { eAX, Iv }, 0 },
1884 { Bad_Opcode }, /* SEG CS prefix */
1885 { X86_64_TABLE (X86_64_2F) },
1886 /* 30 */
1887 { "xorB", { Ebh1, Gb }, 0 },
1888 { "xorS", { Evh1, Gv }, 0 },
1889 { "xorB", { Gb, EbS }, 0 },
1890 { "xorS", { Gv, EvS }, 0 },
1891 { "xorB", { AL, Ib }, 0 },
1892 { "xorS", { eAX, Iv }, 0 },
1893 { Bad_Opcode }, /* SEG SS prefix */
1894 { X86_64_TABLE (X86_64_37) },
1895 /* 38 */
1896 { "cmpB", { Eb, Gb }, 0 },
1897 { "cmpS", { Ev, Gv }, 0 },
1898 { "cmpB", { Gb, EbS }, 0 },
1899 { "cmpS", { Gv, EvS }, 0 },
1900 { "cmpB", { AL, Ib }, 0 },
1901 { "cmpS", { eAX, Iv }, 0 },
1902 { Bad_Opcode }, /* SEG DS prefix */
1903 { X86_64_TABLE (X86_64_3F) },
1904 /* 40 */
1905 { "inc{S|}", { RMeAX }, 0 },
1906 { "inc{S|}", { RMeCX }, 0 },
1907 { "inc{S|}", { RMeDX }, 0 },
1908 { "inc{S|}", { RMeBX }, 0 },
1909 { "inc{S|}", { RMeSP }, 0 },
1910 { "inc{S|}", { RMeBP }, 0 },
1911 { "inc{S|}", { RMeSI }, 0 },
1912 { "inc{S|}", { RMeDI }, 0 },
1913 /* 48 */
1914 { "dec{S|}", { RMeAX }, 0 },
1915 { "dec{S|}", { RMeCX }, 0 },
1916 { "dec{S|}", { RMeDX }, 0 },
1917 { "dec{S|}", { RMeBX }, 0 },
1918 { "dec{S|}", { RMeSP }, 0 },
1919 { "dec{S|}", { RMeBP }, 0 },
1920 { "dec{S|}", { RMeSI }, 0 },
1921 { "dec{S|}", { RMeDI }, 0 },
1922 /* 50 */
1923 { "push{!P|}", { RMrAX }, 0 },
1924 { "push{!P|}", { RMrCX }, 0 },
1925 { "push{!P|}", { RMrDX }, 0 },
1926 { "push{!P|}", { RMrBX }, 0 },
1927 { "push{!P|}", { RMrSP }, 0 },
1928 { "push{!P|}", { RMrBP }, 0 },
1929 { "push{!P|}", { RMrSI }, 0 },
1930 { "push{!P|}", { RMrDI }, 0 },
1931 /* 58 */
1932 { "pop{!P|}", { RMrAX }, 0 },
1933 { "pop{!P|}", { RMrCX }, 0 },
1934 { "pop{!P|}", { RMrDX }, 0 },
1935 { "pop{!P|}", { RMrBX }, 0 },
1936 { "pop{!P|}", { RMrSP }, 0 },
1937 { "pop{!P|}", { RMrBP }, 0 },
1938 { "pop{!P|}", { RMrSI }, 0 },
1939 { "pop{!P|}", { RMrDI }, 0 },
1940 /* 60 */
1941 { X86_64_TABLE (X86_64_60) },
1942 { X86_64_TABLE (X86_64_61) },
1943 { X86_64_TABLE (X86_64_62) },
1944 { X86_64_TABLE (X86_64_63) },
1945 { Bad_Opcode }, /* seg fs */
1946 { Bad_Opcode }, /* seg gs */
1947 { Bad_Opcode }, /* op size prefix */
1948 { Bad_Opcode }, /* adr size prefix */
1949 /* 68 */
1950 { "pushP", { sIv }, 0 },
1951 { "imulS", { Gv, Ev, Iv }, 0 },
1952 { "pushP", { sIbT }, 0 },
1953 { "imulS", { Gv, Ev, sIb }, 0 },
1954 { "ins{b|}", { Ybr, indirDX }, 0 },
1955 { X86_64_TABLE (X86_64_6D) },
1956 { "outs{b|}", { indirDXr, Xb }, 0 },
1957 { X86_64_TABLE (X86_64_6F) },
1958 /* 70 */
1959 { "joH", { Jb, BND, cond_jump_flag }, 0 },
1960 { "jnoH", { Jb, BND, cond_jump_flag }, 0 },
1961 { "jbH", { Jb, BND, cond_jump_flag }, 0 },
1962 { "jaeH", { Jb, BND, cond_jump_flag }, 0 },
1963 { "jeH", { Jb, BND, cond_jump_flag }, 0 },
1964 { "jneH", { Jb, BND, cond_jump_flag }, 0 },
1965 { "jbeH", { Jb, BND, cond_jump_flag }, 0 },
1966 { "jaH", { Jb, BND, cond_jump_flag }, 0 },
1967 /* 78 */
1968 { "jsH", { Jb, BND, cond_jump_flag }, 0 },
1969 { "jnsH", { Jb, BND, cond_jump_flag }, 0 },
1970 { "jpH", { Jb, BND, cond_jump_flag }, 0 },
1971 { "jnpH", { Jb, BND, cond_jump_flag }, 0 },
1972 { "jlH", { Jb, BND, cond_jump_flag }, 0 },
1973 { "jgeH", { Jb, BND, cond_jump_flag }, 0 },
1974 { "jleH", { Jb, BND, cond_jump_flag }, 0 },
1975 { "jgH", { Jb, BND, cond_jump_flag }, 0 },
1976 /* 80 */
1977 { REG_TABLE (REG_80) },
1978 { REG_TABLE (REG_81) },
1979 { X86_64_TABLE (X86_64_82) },
1980 { REG_TABLE (REG_83) },
1981 { "testB", { Eb, Gb }, 0 },
1982 { "testS", { Ev, Gv }, 0 },
1983 { "xchgB", { Ebh2, Gb }, 0 },
1984 { "xchgS", { Evh2, Gv }, 0 },
1985 /* 88 */
1986 { "movB", { Ebh3, Gb }, 0 },
1987 { "movS", { Evh3, Gv }, 0 },
1988 { "movB", { Gb, EbS }, 0 },
1989 { "movS", { Gv, EvS }, 0 },
1990 { "movD", { Sv, Sw }, 0 },
1991 { MOD_TABLE (MOD_8D) },
1992 { "movD", { Sw, Sv }, 0 },
1993 { REG_TABLE (REG_8F) },
1994 /* 90 */
1995 { PREFIX_TABLE (PREFIX_90) },
1996 { "xchgS", { RMeCX, eAX }, 0 },
1997 { "xchgS", { RMeDX, eAX }, 0 },
1998 { "xchgS", { RMeBX, eAX }, 0 },
1999 { "xchgS", { RMeSP, eAX }, 0 },
2000 { "xchgS", { RMeBP, eAX }, 0 },
2001 { "xchgS", { RMeSI, eAX }, 0 },
2002 { "xchgS", { RMeDI, eAX }, 0 },
2003 /* 98 */
2004 { "cW{t|}R", { XX }, 0 },
2005 { "cR{t|}O", { XX }, 0 },
2006 { X86_64_TABLE (X86_64_9A) },
2007 { Bad_Opcode }, /* fwait */
2008 { "pushfP", { XX }, 0 },
2009 { "popfP", { XX }, 0 },
2010 { "sahf", { XX }, 0 },
2011 { "lahf", { XX }, 0 },
2012 /* a0 */
2013 { "mov%LB", { AL, Ob }, 0 },
2014 { "mov%LS", { eAX, Ov }, 0 },
2015 { "mov%LB", { Ob, AL }, 0 },
2016 { "mov%LS", { Ov, eAX }, 0 },
2017 { "movs{b|}", { Ybr, Xb }, 0 },
2018 { "movs{R|}", { Yvr, Xv }, 0 },
2019 { "cmps{b|}", { Xb, Yb }, 0 },
2020 { "cmps{R|}", { Xv, Yv }, 0 },
2021 /* a8 */
2022 { "testB", { AL, Ib }, 0 },
2023 { "testS", { eAX, Iv }, 0 },
2024 { "stosB", { Ybr, AL }, 0 },
2025 { "stosS", { Yvr, eAX }, 0 },
2026 { "lodsB", { ALr, Xb }, 0 },
2027 { "lodsS", { eAXr, Xv }, 0 },
2028 { "scasB", { AL, Yb }, 0 },
2029 { "scasS", { eAX, Yv }, 0 },
2030 /* b0 */
2031 { "movB", { RMAL, Ib }, 0 },
2032 { "movB", { RMCL, Ib }, 0 },
2033 { "movB", { RMDL, Ib }, 0 },
2034 { "movB", { RMBL, Ib }, 0 },
2035 { "movB", { RMAH, Ib }, 0 },
2036 { "movB", { RMCH, Ib }, 0 },
2037 { "movB", { RMDH, Ib }, 0 },
2038 { "movB", { RMBH, Ib }, 0 },
2039 /* b8 */
2040 { "mov%LV", { RMeAX, Iv64 }, 0 },
2041 { "mov%LV", { RMeCX, Iv64 }, 0 },
2042 { "mov%LV", { RMeDX, Iv64 }, 0 },
2043 { "mov%LV", { RMeBX, Iv64 }, 0 },
2044 { "mov%LV", { RMeSP, Iv64 }, 0 },
2045 { "mov%LV", { RMeBP, Iv64 }, 0 },
2046 { "mov%LV", { RMeSI, Iv64 }, 0 },
2047 { "mov%LV", { RMeDI, Iv64 }, 0 },
2048 /* c0 */
2049 { REG_TABLE (REG_C0) },
2050 { REG_TABLE (REG_C1) },
2051 { X86_64_TABLE (X86_64_C2) },
2052 { X86_64_TABLE (X86_64_C3) },
2053 { X86_64_TABLE (X86_64_C4) },
2054 { X86_64_TABLE (X86_64_C5) },
2055 { REG_TABLE (REG_C6) },
2056 { REG_TABLE (REG_C7) },
2057 /* c8 */
2058 { "enterP", { Iw, Ib }, 0 },
2059 { "leaveP", { XX }, 0 },
2060 { "{l|}ret{|f}%LP", { Iw }, 0 },
2061 { "{l|}ret{|f}%LP", { XX }, 0 },
2062 { "int3", { XX }, 0 },
2063 { "int", { Ib }, 0 },
2064 { X86_64_TABLE (X86_64_CE) },
2065 { "iret%LP", { XX }, 0 },
2066 /* d0 */
2067 { REG_TABLE (REG_D0) },
2068 { REG_TABLE (REG_D1) },
2069 { REG_TABLE (REG_D2) },
2070 { REG_TABLE (REG_D3) },
2071 { X86_64_TABLE (X86_64_D4) },
2072 { X86_64_TABLE (X86_64_D5) },
2073 { Bad_Opcode },
2074 { "xlat", { DSBX }, 0 },
2075 /* d8 */
2076 { FLOAT },
2077 { FLOAT },
2078 { FLOAT },
2079 { FLOAT },
2080 { FLOAT },
2081 { FLOAT },
2082 { FLOAT },
2083 { FLOAT },
2084 /* e0 */
2085 { "loopneFH", { Jb, XX, loop_jcxz_flag }, 0 },
2086 { "loopeFH", { Jb, XX, loop_jcxz_flag }, 0 },
2087 { "loopFH", { Jb, XX, loop_jcxz_flag }, 0 },
2088 { "jEcxzH", { Jb, XX, loop_jcxz_flag }, 0 },
2089 { "inB", { AL, Ib }, 0 },
2090 { "inG", { zAX, Ib }, 0 },
2091 { "outB", { Ib, AL }, 0 },
2092 { "outG", { Ib, zAX }, 0 },
2093 /* e8 */
2094 { X86_64_TABLE (X86_64_E8) },
2095 { X86_64_TABLE (X86_64_E9) },
2096 { X86_64_TABLE (X86_64_EA) },
2097 { "jmp", { Jb, BND }, 0 },
2098 { "inB", { AL, indirDX }, 0 },
2099 { "inG", { zAX, indirDX }, 0 },
2100 { "outB", { indirDX, AL }, 0 },
2101 { "outG", { indirDX, zAX }, 0 },
2102 /* f0 */
2103 { Bad_Opcode }, /* lock prefix */
2104 { "icebp", { XX }, 0 },
2105 { Bad_Opcode }, /* repne */
2106 { Bad_Opcode }, /* repz */
2107 { "hlt", { XX }, 0 },
2108 { "cmc", { XX }, 0 },
2109 { REG_TABLE (REG_F6) },
2110 { REG_TABLE (REG_F7) },
2111 /* f8 */
2112 { "clc", { XX }, 0 },
2113 { "stc", { XX }, 0 },
2114 { "cli", { XX }, 0 },
2115 { "sti", { XX }, 0 },
2116 { "cld", { XX }, 0 },
2117 { "std", { XX }, 0 },
2118 { REG_TABLE (REG_FE) },
2119 { REG_TABLE (REG_FF) },
2120 };
2121
2122 static const struct dis386 dis386_twobyte[] = {
2123 /* 00 */
2124 { REG_TABLE (REG_0F00 ) },
2125 { REG_TABLE (REG_0F01 ) },
2126 { "larS", { Gv, Ew }, 0 },
2127 { "lslS", { Gv, Ew }, 0 },
2128 { Bad_Opcode },
2129 { "syscall", { XX }, 0 },
2130 { "clts", { XX }, 0 },
2131 { "sysret%LQ", { XX }, 0 },
2132 /* 08 */
2133 { "invd", { XX }, 0 },
2134 { PREFIX_TABLE (PREFIX_0F09) },
2135 { Bad_Opcode },
2136 { "ud2", { XX }, 0 },
2137 { Bad_Opcode },
2138 { REG_TABLE (REG_0F0D) },
2139 { "femms", { XX }, 0 },
2140 { "", { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix. */
2141 /* 10 */
2142 { PREFIX_TABLE (PREFIX_0F10) },
2143 { PREFIX_TABLE (PREFIX_0F11) },
2144 { PREFIX_TABLE (PREFIX_0F12) },
2145 { MOD_TABLE (MOD_0F13) },
2146 { "unpcklpX", { XM, EXx }, PREFIX_OPCODE },
2147 { "unpckhpX", { XM, EXx }, PREFIX_OPCODE },
2148 { PREFIX_TABLE (PREFIX_0F16) },
2149 { MOD_TABLE (MOD_0F17) },
2150 /* 18 */
2151 { REG_TABLE (REG_0F18) },
2152 { "nopQ", { Ev }, 0 },
2153 { PREFIX_TABLE (PREFIX_0F1A) },
2154 { PREFIX_TABLE (PREFIX_0F1B) },
2155 { PREFIX_TABLE (PREFIX_0F1C) },
2156 { "nopQ", { Ev }, 0 },
2157 { PREFIX_TABLE (PREFIX_0F1E) },
2158 { "nopQ", { Ev }, 0 },
2159 /* 20 */
2160 { "movZ", { Em, Cm }, 0 },
2161 { "movZ", { Em, Dm }, 0 },
2162 { "movZ", { Cm, Em }, 0 },
2163 { "movZ", { Dm, Em }, 0 },
2164 { X86_64_TABLE (X86_64_0F24) },
2165 { Bad_Opcode },
2166 { X86_64_TABLE (X86_64_0F26) },
2167 { Bad_Opcode },
2168 /* 28 */
2169 { "movapX", { XM, EXx }, PREFIX_OPCODE },
2170 { "movapX", { EXxS, XM }, PREFIX_OPCODE },
2171 { PREFIX_TABLE (PREFIX_0F2A) },
2172 { PREFIX_TABLE (PREFIX_0F2B) },
2173 { PREFIX_TABLE (PREFIX_0F2C) },
2174 { PREFIX_TABLE (PREFIX_0F2D) },
2175 { PREFIX_TABLE (PREFIX_0F2E) },
2176 { PREFIX_TABLE (PREFIX_0F2F) },
2177 /* 30 */
2178 { "wrmsr", { XX }, 0 },
2179 { "rdtsc", { XX }, 0 },
2180 { "rdmsr", { XX }, 0 },
2181 { "rdpmc", { XX }, 0 },
2182 { "sysenter", { SEP }, 0 },
2183 { "sysexit", { SEP }, 0 },
2184 { Bad_Opcode },
2185 { "getsec", { XX }, 0 },
2186 /* 38 */
2187 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2188 { Bad_Opcode },
2189 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2190 { Bad_Opcode },
2191 { Bad_Opcode },
2192 { Bad_Opcode },
2193 { Bad_Opcode },
2194 { Bad_Opcode },
2195 /* 40 */
2196 { "cmovoS", { Gv, Ev }, 0 },
2197 { "cmovnoS", { Gv, Ev }, 0 },
2198 { "cmovbS", { Gv, Ev }, 0 },
2199 { "cmovaeS", { Gv, Ev }, 0 },
2200 { "cmoveS", { Gv, Ev }, 0 },
2201 { "cmovneS", { Gv, Ev }, 0 },
2202 { "cmovbeS", { Gv, Ev }, 0 },
2203 { "cmovaS", { Gv, Ev }, 0 },
2204 /* 48 */
2205 { "cmovsS", { Gv, Ev }, 0 },
2206 { "cmovnsS", { Gv, Ev }, 0 },
2207 { "cmovpS", { Gv, Ev }, 0 },
2208 { "cmovnpS", { Gv, Ev }, 0 },
2209 { "cmovlS", { Gv, Ev }, 0 },
2210 { "cmovgeS", { Gv, Ev }, 0 },
2211 { "cmovleS", { Gv, Ev }, 0 },
2212 { "cmovgS", { Gv, Ev }, 0 },
2213 /* 50 */
2214 { MOD_TABLE (MOD_0F50) },
2215 { PREFIX_TABLE (PREFIX_0F51) },
2216 { PREFIX_TABLE (PREFIX_0F52) },
2217 { PREFIX_TABLE (PREFIX_0F53) },
2218 { "andpX", { XM, EXx }, PREFIX_OPCODE },
2219 { "andnpX", { XM, EXx }, PREFIX_OPCODE },
2220 { "orpX", { XM, EXx }, PREFIX_OPCODE },
2221 { "xorpX", { XM, EXx }, PREFIX_OPCODE },
2222 /* 58 */
2223 { PREFIX_TABLE (PREFIX_0F58) },
2224 { PREFIX_TABLE (PREFIX_0F59) },
2225 { PREFIX_TABLE (PREFIX_0F5A) },
2226 { PREFIX_TABLE (PREFIX_0F5B) },
2227 { PREFIX_TABLE (PREFIX_0F5C) },
2228 { PREFIX_TABLE (PREFIX_0F5D) },
2229 { PREFIX_TABLE (PREFIX_0F5E) },
2230 { PREFIX_TABLE (PREFIX_0F5F) },
2231 /* 60 */
2232 { PREFIX_TABLE (PREFIX_0F60) },
2233 { PREFIX_TABLE (PREFIX_0F61) },
2234 { PREFIX_TABLE (PREFIX_0F62) },
2235 { "packsswb", { MX, EM }, PREFIX_OPCODE },
2236 { "pcmpgtb", { MX, EM }, PREFIX_OPCODE },
2237 { "pcmpgtw", { MX, EM }, PREFIX_OPCODE },
2238 { "pcmpgtd", { MX, EM }, PREFIX_OPCODE },
2239 { "packuswb", { MX, EM }, PREFIX_OPCODE },
2240 /* 68 */
2241 { "punpckhbw", { MX, EM }, PREFIX_OPCODE },
2242 { "punpckhwd", { MX, EM }, PREFIX_OPCODE },
2243 { "punpckhdq", { MX, EM }, PREFIX_OPCODE },
2244 { "packssdw", { MX, EM }, PREFIX_OPCODE },
2245 { "punpcklqdq", { XM, EXx }, PREFIX_DATA },
2246 { "punpckhqdq", { XM, EXx }, PREFIX_DATA },
2247 { "movK", { MX, Edq }, PREFIX_OPCODE },
2248 { PREFIX_TABLE (PREFIX_0F6F) },
2249 /* 70 */
2250 { PREFIX_TABLE (PREFIX_0F70) },
2251 { REG_TABLE (REG_0F71) },
2252 { REG_TABLE (REG_0F72) },
2253 { REG_TABLE (REG_0F73) },
2254 { "pcmpeqb", { MX, EM }, PREFIX_OPCODE },
2255 { "pcmpeqw", { MX, EM }, PREFIX_OPCODE },
2256 { "pcmpeqd", { MX, EM }, PREFIX_OPCODE },
2257 { "emms", { XX }, PREFIX_OPCODE },
2258 /* 78 */
2259 { PREFIX_TABLE (PREFIX_0F78) },
2260 { PREFIX_TABLE (PREFIX_0F79) },
2261 { Bad_Opcode },
2262 { Bad_Opcode },
2263 { PREFIX_TABLE (PREFIX_0F7C) },
2264 { PREFIX_TABLE (PREFIX_0F7D) },
2265 { PREFIX_TABLE (PREFIX_0F7E) },
2266 { PREFIX_TABLE (PREFIX_0F7F) },
2267 /* 80 */
2268 { "joH", { Jv, BND, cond_jump_flag }, 0 },
2269 { "jnoH", { Jv, BND, cond_jump_flag }, 0 },
2270 { "jbH", { Jv, BND, cond_jump_flag }, 0 },
2271 { "jaeH", { Jv, BND, cond_jump_flag }, 0 },
2272 { "jeH", { Jv, BND, cond_jump_flag }, 0 },
2273 { "jneH", { Jv, BND, cond_jump_flag }, 0 },
2274 { "jbeH", { Jv, BND, cond_jump_flag }, 0 },
2275 { "jaH", { Jv, BND, cond_jump_flag }, 0 },
2276 /* 88 */
2277 { "jsH", { Jv, BND, cond_jump_flag }, 0 },
2278 { "jnsH", { Jv, BND, cond_jump_flag }, 0 },
2279 { "jpH", { Jv, BND, cond_jump_flag }, 0 },
2280 { "jnpH", { Jv, BND, cond_jump_flag }, 0 },
2281 { "jlH", { Jv, BND, cond_jump_flag }, 0 },
2282 { "jgeH", { Jv, BND, cond_jump_flag }, 0 },
2283 { "jleH", { Jv, BND, cond_jump_flag }, 0 },
2284 { "jgH", { Jv, BND, cond_jump_flag }, 0 },
2285 /* 90 */
2286 { "seto", { Eb }, 0 },
2287 { "setno", { Eb }, 0 },
2288 { "setb", { Eb }, 0 },
2289 { "setae", { Eb }, 0 },
2290 { "sete", { Eb }, 0 },
2291 { "setne", { Eb }, 0 },
2292 { "setbe", { Eb }, 0 },
2293 { "seta", { Eb }, 0 },
2294 /* 98 */
2295 { "sets", { Eb }, 0 },
2296 { "setns", { Eb }, 0 },
2297 { "setp", { Eb }, 0 },
2298 { "setnp", { Eb }, 0 },
2299 { "setl", { Eb }, 0 },
2300 { "setge", { Eb }, 0 },
2301 { "setle", { Eb }, 0 },
2302 { "setg", { Eb }, 0 },
2303 /* a0 */
2304 { "pushP", { fs }, 0 },
2305 { "popP", { fs }, 0 },
2306 { "cpuid", { XX }, 0 },
2307 { "btS", { Ev, Gv }, 0 },
2308 { "shldS", { Ev, Gv, Ib }, 0 },
2309 { "shldS", { Ev, Gv, CL }, 0 },
2310 { REG_TABLE (REG_0FA6) },
2311 { REG_TABLE (REG_0FA7) },
2312 /* a8 */
2313 { "pushP", { gs }, 0 },
2314 { "popP", { gs }, 0 },
2315 { "rsm", { XX }, 0 },
2316 { "btsS", { Evh1, Gv }, 0 },
2317 { "shrdS", { Ev, Gv, Ib }, 0 },
2318 { "shrdS", { Ev, Gv, CL }, 0 },
2319 { REG_TABLE (REG_0FAE) },
2320 { "imulS", { Gv, Ev }, 0 },
2321 /* b0 */
2322 { "cmpxchgB", { Ebh1, Gb }, 0 },
2323 { "cmpxchgS", { Evh1, Gv }, 0 },
2324 { MOD_TABLE (MOD_0FB2) },
2325 { "btrS", { Evh1, Gv }, 0 },
2326 { MOD_TABLE (MOD_0FB4) },
2327 { MOD_TABLE (MOD_0FB5) },
2328 { "movz{bR|x}", { Gv, Eb }, 0 },
2329 { "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2330 /* b8 */
2331 { PREFIX_TABLE (PREFIX_0FB8) },
2332 { "ud1S", { Gv, Ev }, 0 },
2333 { REG_TABLE (REG_0FBA) },
2334 { "btcS", { Evh1, Gv }, 0 },
2335 { PREFIX_TABLE (PREFIX_0FBC) },
2336 { PREFIX_TABLE (PREFIX_0FBD) },
2337 { "movs{bR|x}", { Gv, Eb }, 0 },
2338 { "movs{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2339 /* c0 */
2340 { "xaddB", { Ebh1, Gb }, 0 },
2341 { "xaddS", { Evh1, Gv }, 0 },
2342 { PREFIX_TABLE (PREFIX_0FC2) },
2343 { MOD_TABLE (MOD_0FC3) },
2344 { "pinsrw", { MX, Edqw, Ib }, PREFIX_OPCODE },
2345 { "pextrw", { Gdq, MS, Ib }, PREFIX_OPCODE },
2346 { "shufpX", { XM, EXx, Ib }, PREFIX_OPCODE },
2347 { REG_TABLE (REG_0FC7) },
2348 /* c8 */
2349 { "bswap", { RMeAX }, 0 },
2350 { "bswap", { RMeCX }, 0 },
2351 { "bswap", { RMeDX }, 0 },
2352 { "bswap", { RMeBX }, 0 },
2353 { "bswap", { RMeSP }, 0 },
2354 { "bswap", { RMeBP }, 0 },
2355 { "bswap", { RMeSI }, 0 },
2356 { "bswap", { RMeDI }, 0 },
2357 /* d0 */
2358 { PREFIX_TABLE (PREFIX_0FD0) },
2359 { "psrlw", { MX, EM }, PREFIX_OPCODE },
2360 { "psrld", { MX, EM }, PREFIX_OPCODE },
2361 { "psrlq", { MX, EM }, PREFIX_OPCODE },
2362 { "paddq", { MX, EM }, PREFIX_OPCODE },
2363 { "pmullw", { MX, EM }, PREFIX_OPCODE },
2364 { PREFIX_TABLE (PREFIX_0FD6) },
2365 { MOD_TABLE (MOD_0FD7) },
2366 /* d8 */
2367 { "psubusb", { MX, EM }, PREFIX_OPCODE },
2368 { "psubusw", { MX, EM }, PREFIX_OPCODE },
2369 { "pminub", { MX, EM }, PREFIX_OPCODE },
2370 { "pand", { MX, EM }, PREFIX_OPCODE },
2371 { "paddusb", { MX, EM }, PREFIX_OPCODE },
2372 { "paddusw", { MX, EM }, PREFIX_OPCODE },
2373 { "pmaxub", { MX, EM }, PREFIX_OPCODE },
2374 { "pandn", { MX, EM }, PREFIX_OPCODE },
2375 /* e0 */
2376 { "pavgb", { MX, EM }, PREFIX_OPCODE },
2377 { "psraw", { MX, EM }, PREFIX_OPCODE },
2378 { "psrad", { MX, EM }, PREFIX_OPCODE },
2379 { "pavgw", { MX, EM }, PREFIX_OPCODE },
2380 { "pmulhuw", { MX, EM }, PREFIX_OPCODE },
2381 { "pmulhw", { MX, EM }, PREFIX_OPCODE },
2382 { PREFIX_TABLE (PREFIX_0FE6) },
2383 { PREFIX_TABLE (PREFIX_0FE7) },
2384 /* e8 */
2385 { "psubsb", { MX, EM }, PREFIX_OPCODE },
2386 { "psubsw", { MX, EM }, PREFIX_OPCODE },
2387 { "pminsw", { MX, EM }, PREFIX_OPCODE },
2388 { "por", { MX, EM }, PREFIX_OPCODE },
2389 { "paddsb", { MX, EM }, PREFIX_OPCODE },
2390 { "paddsw", { MX, EM }, PREFIX_OPCODE },
2391 { "pmaxsw", { MX, EM }, PREFIX_OPCODE },
2392 { "pxor", { MX, EM }, PREFIX_OPCODE },
2393 /* f0 */
2394 { PREFIX_TABLE (PREFIX_0FF0) },
2395 { "psllw", { MX, EM }, PREFIX_OPCODE },
2396 { "pslld", { MX, EM }, PREFIX_OPCODE },
2397 { "psllq", { MX, EM }, PREFIX_OPCODE },
2398 { "pmuludq", { MX, EM }, PREFIX_OPCODE },
2399 { "pmaddwd", { MX, EM }, PREFIX_OPCODE },
2400 { "psadbw", { MX, EM }, PREFIX_OPCODE },
2401 { PREFIX_TABLE (PREFIX_0FF7) },
2402 /* f8 */
2403 { "psubb", { MX, EM }, PREFIX_OPCODE },
2404 { "psubw", { MX, EM }, PREFIX_OPCODE },
2405 { "psubd", { MX, EM }, PREFIX_OPCODE },
2406 { "psubq", { MX, EM }, PREFIX_OPCODE },
2407 { "paddb", { MX, EM }, PREFIX_OPCODE },
2408 { "paddw", { MX, EM }, PREFIX_OPCODE },
2409 { "paddd", { MX, EM }, PREFIX_OPCODE },
2410 { "ud0S", { Gv, Ev }, 0 },
2411 };
2412
2413 static const unsigned char onebyte_has_modrm[256] = {
2414 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2415 /* ------------------------------- */
2416 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2417 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2418 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2419 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2420 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2421 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2422 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2423 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2424 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2425 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2426 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2427 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2428 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2429 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2430 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2431 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2432 /* ------------------------------- */
2433 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2434 };
2435
2436 static const unsigned char twobyte_has_modrm[256] = {
2437 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2438 /* ------------------------------- */
2439 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2440 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2441 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2442 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2443 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2444 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2445 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2446 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2447 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2448 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2449 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2450 /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2451 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2452 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2453 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2454 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */
2455 /* ------------------------------- */
2456 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2457 };
2458
2459 static char obuf[100];
2460 static char *obufp;
2461 static char *mnemonicendp;
2462 static char scratchbuf[100];
2463 static unsigned char *start_codep;
2464 static unsigned char *insn_codep;
2465 static unsigned char *codep;
2466 static unsigned char *end_codep;
2467 static int last_lock_prefix;
2468 static int last_repz_prefix;
2469 static int last_repnz_prefix;
2470 static int last_data_prefix;
2471 static int last_addr_prefix;
2472 static int last_rex_prefix;
2473 static int last_seg_prefix;
2474 static int fwait_prefix;
2475 /* The active segment register prefix. */
2476 static int active_seg_prefix;
2477 #define MAX_CODE_LENGTH 15
2478 /* We can up to 14 prefixes since the maximum instruction length is
2479 15bytes. */
2480 static int all_prefixes[MAX_CODE_LENGTH - 1];
2481 static disassemble_info *the_info;
2482 static struct
2483 {
2484 int mod;
2485 int reg;
2486 int rm;
2487 }
2488 modrm;
2489 static unsigned char need_modrm;
2490 static struct
2491 {
2492 int scale;
2493 int index;
2494 int base;
2495 }
2496 sib;
2497 static struct
2498 {
2499 int register_specifier;
2500 int length;
2501 int prefix;
2502 int w;
2503 int evex;
2504 int r;
2505 int v;
2506 int mask_register_specifier;
2507 int zeroing;
2508 int ll;
2509 int b;
2510 }
2511 vex;
2512 static unsigned char need_vex;
2513
2514 struct op
2515 {
2516 const char *name;
2517 unsigned int len;
2518 };
2519
2520 /* If we are accessing mod/rm/reg without need_modrm set, then the
2521 values are stale. Hitting this abort likely indicates that you
2522 need to update onebyte_has_modrm or twobyte_has_modrm. */
2523 #define MODRM_CHECK if (!need_modrm) abort ()
2524
2525 static const char **names64;
2526 static const char **names32;
2527 static const char **names16;
2528 static const char **names8;
2529 static const char **names8rex;
2530 static const char **names_seg;
2531 static const char *index64;
2532 static const char *index32;
2533 static const char **index16;
2534 static const char **names_bnd;
2535
2536 static const char *intel_names64[] = {
2537 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2538 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2539 };
2540 static const char *intel_names32[] = {
2541 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2542 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2543 };
2544 static const char *intel_names16[] = {
2545 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2546 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2547 };
2548 static const char *intel_names8[] = {
2549 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2550 };
2551 static const char *intel_names8rex[] = {
2552 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2553 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2554 };
2555 static const char *intel_names_seg[] = {
2556 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2557 };
2558 static const char *intel_index64 = "riz";
2559 static const char *intel_index32 = "eiz";
2560 static const char *intel_index16[] = {
2561 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2562 };
2563
2564 static const char *att_names64[] = {
2565 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2566 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2567 };
2568 static const char *att_names32[] = {
2569 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2570 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2571 };
2572 static const char *att_names16[] = {
2573 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2574 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2575 };
2576 static const char *att_names8[] = {
2577 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2578 };
2579 static const char *att_names8rex[] = {
2580 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2581 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2582 };
2583 static const char *att_names_seg[] = {
2584 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2585 };
2586 static const char *att_index64 = "%riz";
2587 static const char *att_index32 = "%eiz";
2588 static const char *att_index16[] = {
2589 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2590 };
2591
2592 static const char **names_mm;
2593 static const char *intel_names_mm[] = {
2594 "mm0", "mm1", "mm2", "mm3",
2595 "mm4", "mm5", "mm6", "mm7"
2596 };
2597 static const char *att_names_mm[] = {
2598 "%mm0", "%mm1", "%mm2", "%mm3",
2599 "%mm4", "%mm5", "%mm6", "%mm7"
2600 };
2601
2602 static const char *intel_names_bnd[] = {
2603 "bnd0", "bnd1", "bnd2", "bnd3"
2604 };
2605
2606 static const char *att_names_bnd[] = {
2607 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
2608 };
2609
2610 static const char **names_xmm;
2611 static const char *intel_names_xmm[] = {
2612 "xmm0", "xmm1", "xmm2", "xmm3",
2613 "xmm4", "xmm5", "xmm6", "xmm7",
2614 "xmm8", "xmm9", "xmm10", "xmm11",
2615 "xmm12", "xmm13", "xmm14", "xmm15",
2616 "xmm16", "xmm17", "xmm18", "xmm19",
2617 "xmm20", "xmm21", "xmm22", "xmm23",
2618 "xmm24", "xmm25", "xmm26", "xmm27",
2619 "xmm28", "xmm29", "xmm30", "xmm31"
2620 };
2621 static const char *att_names_xmm[] = {
2622 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2623 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2624 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2625 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
2626 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
2627 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
2628 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
2629 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
2630 };
2631
2632 static const char **names_ymm;
2633 static const char *intel_names_ymm[] = {
2634 "ymm0", "ymm1", "ymm2", "ymm3",
2635 "ymm4", "ymm5", "ymm6", "ymm7",
2636 "ymm8", "ymm9", "ymm10", "ymm11",
2637 "ymm12", "ymm13", "ymm14", "ymm15",
2638 "ymm16", "ymm17", "ymm18", "ymm19",
2639 "ymm20", "ymm21", "ymm22", "ymm23",
2640 "ymm24", "ymm25", "ymm26", "ymm27",
2641 "ymm28", "ymm29", "ymm30", "ymm31"
2642 };
2643 static const char *att_names_ymm[] = {
2644 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2645 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2646 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2647 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
2648 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
2649 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
2650 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
2651 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
2652 };
2653
2654 static const char **names_zmm;
2655 static const char *intel_names_zmm[] = {
2656 "zmm0", "zmm1", "zmm2", "zmm3",
2657 "zmm4", "zmm5", "zmm6", "zmm7",
2658 "zmm8", "zmm9", "zmm10", "zmm11",
2659 "zmm12", "zmm13", "zmm14", "zmm15",
2660 "zmm16", "zmm17", "zmm18", "zmm19",
2661 "zmm20", "zmm21", "zmm22", "zmm23",
2662 "zmm24", "zmm25", "zmm26", "zmm27",
2663 "zmm28", "zmm29", "zmm30", "zmm31"
2664 };
2665 static const char *att_names_zmm[] = {
2666 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
2667 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
2668 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
2669 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
2670 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
2671 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
2672 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
2673 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
2674 };
2675
2676 static const char **names_tmm;
2677 static const char *intel_names_tmm[] = {
2678 "tmm0", "tmm1", "tmm2", "tmm3",
2679 "tmm4", "tmm5", "tmm6", "tmm7"
2680 };
2681 static const char *att_names_tmm[] = {
2682 "%tmm0", "%tmm1", "%tmm2", "%tmm3",
2683 "%tmm4", "%tmm5", "%tmm6", "%tmm7"
2684 };
2685
2686 static const char **names_mask;
2687 static const char *intel_names_mask[] = {
2688 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
2689 };
2690 static const char *att_names_mask[] = {
2691 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
2692 };
2693
2694 static const char *names_rounding[] =
2695 {
2696 "{rn-sae}",
2697 "{rd-sae}",
2698 "{ru-sae}",
2699 "{rz-sae}"
2700 };
2701
2702 static const struct dis386 reg_table[][8] = {
2703 /* REG_80 */
2704 {
2705 { "addA", { Ebh1, Ib }, 0 },
2706 { "orA", { Ebh1, Ib }, 0 },
2707 { "adcA", { Ebh1, Ib }, 0 },
2708 { "sbbA", { Ebh1, Ib }, 0 },
2709 { "andA", { Ebh1, Ib }, 0 },
2710 { "subA", { Ebh1, Ib }, 0 },
2711 { "xorA", { Ebh1, Ib }, 0 },
2712 { "cmpA", { Eb, Ib }, 0 },
2713 },
2714 /* REG_81 */
2715 {
2716 { "addQ", { Evh1, Iv }, 0 },
2717 { "orQ", { Evh1, Iv }, 0 },
2718 { "adcQ", { Evh1, Iv }, 0 },
2719 { "sbbQ", { Evh1, Iv }, 0 },
2720 { "andQ", { Evh1, Iv }, 0 },
2721 { "subQ", { Evh1, Iv }, 0 },
2722 { "xorQ", { Evh1, Iv }, 0 },
2723 { "cmpQ", { Ev, Iv }, 0 },
2724 },
2725 /* REG_83 */
2726 {
2727 { "addQ", { Evh1, sIb }, 0 },
2728 { "orQ", { Evh1, sIb }, 0 },
2729 { "adcQ", { Evh1, sIb }, 0 },
2730 { "sbbQ", { Evh1, sIb }, 0 },
2731 { "andQ", { Evh1, sIb }, 0 },
2732 { "subQ", { Evh1, sIb }, 0 },
2733 { "xorQ", { Evh1, sIb }, 0 },
2734 { "cmpQ", { Ev, sIb }, 0 },
2735 },
2736 /* REG_8F */
2737 {
2738 { "pop{P|}", { stackEv }, 0 },
2739 { XOP_8F_TABLE (XOP_09) },
2740 { Bad_Opcode },
2741 { Bad_Opcode },
2742 { Bad_Opcode },
2743 { XOP_8F_TABLE (XOP_09) },
2744 },
2745 /* REG_C0 */
2746 {
2747 { "rolA", { Eb, Ib }, 0 },
2748 { "rorA", { Eb, Ib }, 0 },
2749 { "rclA", { Eb, Ib }, 0 },
2750 { "rcrA", { Eb, Ib }, 0 },
2751 { "shlA", { Eb, Ib }, 0 },
2752 { "shrA", { Eb, Ib }, 0 },
2753 { "shlA", { Eb, Ib }, 0 },
2754 { "sarA", { Eb, Ib }, 0 },
2755 },
2756 /* REG_C1 */
2757 {
2758 { "rolQ", { Ev, Ib }, 0 },
2759 { "rorQ", { Ev, Ib }, 0 },
2760 { "rclQ", { Ev, Ib }, 0 },
2761 { "rcrQ", { Ev, Ib }, 0 },
2762 { "shlQ", { Ev, Ib }, 0 },
2763 { "shrQ", { Ev, Ib }, 0 },
2764 { "shlQ", { Ev, Ib }, 0 },
2765 { "sarQ", { Ev, Ib }, 0 },
2766 },
2767 /* REG_C6 */
2768 {
2769 { "movA", { Ebh3, Ib }, 0 },
2770 { Bad_Opcode },
2771 { Bad_Opcode },
2772 { Bad_Opcode },
2773 { Bad_Opcode },
2774 { Bad_Opcode },
2775 { Bad_Opcode },
2776 { MOD_TABLE (MOD_C6_REG_7) },
2777 },
2778 /* REG_C7 */
2779 {
2780 { "movQ", { Evh3, Iv }, 0 },
2781 { Bad_Opcode },
2782 { Bad_Opcode },
2783 { Bad_Opcode },
2784 { Bad_Opcode },
2785 { Bad_Opcode },
2786 { Bad_Opcode },
2787 { MOD_TABLE (MOD_C7_REG_7) },
2788 },
2789 /* REG_D0 */
2790 {
2791 { "rolA", { Eb, I1 }, 0 },
2792 { "rorA", { Eb, I1 }, 0 },
2793 { "rclA", { Eb, I1 }, 0 },
2794 { "rcrA", { Eb, I1 }, 0 },
2795 { "shlA", { Eb, I1 }, 0 },
2796 { "shrA", { Eb, I1 }, 0 },
2797 { "shlA", { Eb, I1 }, 0 },
2798 { "sarA", { Eb, I1 }, 0 },
2799 },
2800 /* REG_D1 */
2801 {
2802 { "rolQ", { Ev, I1 }, 0 },
2803 { "rorQ", { Ev, I1 }, 0 },
2804 { "rclQ", { Ev, I1 }, 0 },
2805 { "rcrQ", { Ev, I1 }, 0 },
2806 { "shlQ", { Ev, I1 }, 0 },
2807 { "shrQ", { Ev, I1 }, 0 },
2808 { "shlQ", { Ev, I1 }, 0 },
2809 { "sarQ", { Ev, I1 }, 0 },
2810 },
2811 /* REG_D2 */
2812 {
2813 { "rolA", { Eb, CL }, 0 },
2814 { "rorA", { Eb, CL }, 0 },
2815 { "rclA", { Eb, CL }, 0 },
2816 { "rcrA", { Eb, CL }, 0 },
2817 { "shlA", { Eb, CL }, 0 },
2818 { "shrA", { Eb, CL }, 0 },
2819 { "shlA", { Eb, CL }, 0 },
2820 { "sarA", { Eb, CL }, 0 },
2821 },
2822 /* REG_D3 */
2823 {
2824 { "rolQ", { Ev, CL }, 0 },
2825 { "rorQ", { Ev, CL }, 0 },
2826 { "rclQ", { Ev, CL }, 0 },
2827 { "rcrQ", { Ev, CL }, 0 },
2828 { "shlQ", { Ev, CL }, 0 },
2829 { "shrQ", { Ev, CL }, 0 },
2830 { "shlQ", { Ev, CL }, 0 },
2831 { "sarQ", { Ev, CL }, 0 },
2832 },
2833 /* REG_F6 */
2834 {
2835 { "testA", { Eb, Ib }, 0 },
2836 { "testA", { Eb, Ib }, 0 },
2837 { "notA", { Ebh1 }, 0 },
2838 { "negA", { Ebh1 }, 0 },
2839 { "mulA", { Eb }, 0 }, /* Don't print the implicit %al register, */
2840 { "imulA", { Eb }, 0 }, /* to distinguish these opcodes from other */
2841 { "divA", { Eb }, 0 }, /* mul/imul opcodes. Do the same for div */
2842 { "idivA", { Eb }, 0 }, /* and idiv for consistency. */
2843 },
2844 /* REG_F7 */
2845 {
2846 { "testQ", { Ev, Iv }, 0 },
2847 { "testQ", { Ev, Iv }, 0 },
2848 { "notQ", { Evh1 }, 0 },
2849 { "negQ", { Evh1 }, 0 },
2850 { "mulQ", { Ev }, 0 }, /* Don't print the implicit register. */
2851 { "imulQ", { Ev }, 0 },
2852 { "divQ", { Ev }, 0 },
2853 { "idivQ", { Ev }, 0 },
2854 },
2855 /* REG_FE */
2856 {
2857 { "incA", { Ebh1 }, 0 },
2858 { "decA", { Ebh1 }, 0 },
2859 },
2860 /* REG_FF */
2861 {
2862 { "incQ", { Evh1 }, 0 },
2863 { "decQ", { Evh1 }, 0 },
2864 { "call{@|}", { NOTRACK, indirEv, BND }, 0 },
2865 { MOD_TABLE (MOD_FF_REG_3) },
2866 { "jmp{@|}", { NOTRACK, indirEv, BND }, 0 },
2867 { MOD_TABLE (MOD_FF_REG_5) },
2868 { "push{P|}", { stackEv }, 0 },
2869 { Bad_Opcode },
2870 },
2871 /* REG_0F00 */
2872 {
2873 { "sldtD", { Sv }, 0 },
2874 { "strD", { Sv }, 0 },
2875 { "lldt", { Ew }, 0 },
2876 { "ltr", { Ew }, 0 },
2877 { "verr", { Ew }, 0 },
2878 { "verw", { Ew }, 0 },
2879 { Bad_Opcode },
2880 { Bad_Opcode },
2881 },
2882 /* REG_0F01 */
2883 {
2884 { MOD_TABLE (MOD_0F01_REG_0) },
2885 { MOD_TABLE (MOD_0F01_REG_1) },
2886 { MOD_TABLE (MOD_0F01_REG_2) },
2887 { MOD_TABLE (MOD_0F01_REG_3) },
2888 { "smswD", { Sv }, 0 },
2889 { MOD_TABLE (MOD_0F01_REG_5) },
2890 { "lmsw", { Ew }, 0 },
2891 { MOD_TABLE (MOD_0F01_REG_7) },
2892 },
2893 /* REG_0F0D */
2894 {
2895 { "prefetch", { Mb }, 0 },
2896 { "prefetchw", { Mb }, 0 },
2897 { "prefetchwt1", { Mb }, 0 },
2898 { "prefetch", { Mb }, 0 },
2899 { "prefetch", { Mb }, 0 },
2900 { "prefetch", { Mb }, 0 },
2901 { "prefetch", { Mb }, 0 },
2902 { "prefetch", { Mb }, 0 },
2903 },
2904 /* REG_0F18 */
2905 {
2906 { MOD_TABLE (MOD_0F18_REG_0) },
2907 { MOD_TABLE (MOD_0F18_REG_1) },
2908 { MOD_TABLE (MOD_0F18_REG_2) },
2909 { MOD_TABLE (MOD_0F18_REG_3) },
2910 { MOD_TABLE (MOD_0F18_REG_4) },
2911 { MOD_TABLE (MOD_0F18_REG_5) },
2912 { MOD_TABLE (MOD_0F18_REG_6) },
2913 { MOD_TABLE (MOD_0F18_REG_7) },
2914 },
2915 /* REG_0F1C_P_0_MOD_0 */
2916 {
2917 { "cldemote", { Mb }, 0 },
2918 { "nopQ", { Ev }, 0 },
2919 { "nopQ", { Ev }, 0 },
2920 { "nopQ", { Ev }, 0 },
2921 { "nopQ", { Ev }, 0 },
2922 { "nopQ", { Ev }, 0 },
2923 { "nopQ", { Ev }, 0 },
2924 { "nopQ", { Ev }, 0 },
2925 },
2926 /* REG_0F1E_P_1_MOD_3 */
2927 {
2928 { "nopQ", { Ev }, 0 },
2929 { "rdsspK", { Edq }, PREFIX_OPCODE },
2930 { "nopQ", { Ev }, 0 },
2931 { "nopQ", { Ev }, 0 },
2932 { "nopQ", { Ev }, 0 },
2933 { "nopQ", { Ev }, 0 },
2934 { "nopQ", { Ev }, 0 },
2935 { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) },
2936 },
2937 /* REG_0F38D8_PREFIX_1 */
2938 {
2939 { "aesencwide128kl", { M }, 0 },
2940 { "aesdecwide128kl", { M }, 0 },
2941 { "aesencwide256kl", { M }, 0 },
2942 { "aesdecwide256kl", { M }, 0 },
2943 },
2944 /* REG_0F3A0F_PREFIX_1_MOD_3 */
2945 {
2946 { RM_TABLE (RM_0F3A0F_P_1_MOD_3_REG_0) },
2947 },
2948 /* REG_0F71 */
2949 {
2950 { Bad_Opcode },
2951 { Bad_Opcode },
2952 { MOD_TABLE (MOD_0F71_REG_2) },
2953 { Bad_Opcode },
2954 { MOD_TABLE (MOD_0F71_REG_4) },
2955 { Bad_Opcode },
2956 { MOD_TABLE (MOD_0F71_REG_6) },
2957 },
2958 /* REG_0F72 */
2959 {
2960 { Bad_Opcode },
2961 { Bad_Opcode },
2962 { MOD_TABLE (MOD_0F72_REG_2) },
2963 { Bad_Opcode },
2964 { MOD_TABLE (MOD_0F72_REG_4) },
2965 { Bad_Opcode },
2966 { MOD_TABLE (MOD_0F72_REG_6) },
2967 },
2968 /* REG_0F73 */
2969 {
2970 { Bad_Opcode },
2971 { Bad_Opcode },
2972 { MOD_TABLE (MOD_0F73_REG_2) },
2973 { MOD_TABLE (MOD_0F73_REG_3) },
2974 { Bad_Opcode },
2975 { Bad_Opcode },
2976 { MOD_TABLE (MOD_0F73_REG_6) },
2977 { MOD_TABLE (MOD_0F73_REG_7) },
2978 },
2979 /* REG_0FA6 */
2980 {
2981 { "montmul", { { OP_0f07, 0 } }, 0 },
2982 { "xsha1", { { OP_0f07, 0 } }, 0 },
2983 { "xsha256", { { OP_0f07, 0 } }, 0 },
2984 },
2985 /* REG_0FA7 */
2986 {
2987 { "xstore-rng", { { OP_0f07, 0 } }, 0 },
2988 { "xcrypt-ecb", { { OP_0f07, 0 } }, 0 },
2989 { "xcrypt-cbc", { { OP_0f07, 0 } }, 0 },
2990 { "xcrypt-ctr", { { OP_0f07, 0 } }, 0 },
2991 { "xcrypt-cfb", { { OP_0f07, 0 } }, 0 },
2992 { "xcrypt-ofb", { { OP_0f07, 0 } }, 0 },
2993 },
2994 /* REG_0FAE */
2995 {
2996 { MOD_TABLE (MOD_0FAE_REG_0) },
2997 { MOD_TABLE (MOD_0FAE_REG_1) },
2998 { MOD_TABLE (MOD_0FAE_REG_2) },
2999 { MOD_TABLE (MOD_0FAE_REG_3) },
3000 { MOD_TABLE (MOD_0FAE_REG_4) },
3001 { MOD_TABLE (MOD_0FAE_REG_5) },
3002 { MOD_TABLE (MOD_0FAE_REG_6) },
3003 { MOD_TABLE (MOD_0FAE_REG_7) },
3004 },
3005 /* REG_0FBA */
3006 {
3007 { Bad_Opcode },
3008 { Bad_Opcode },
3009 { Bad_Opcode },
3010 { Bad_Opcode },
3011 { "btQ", { Ev, Ib }, 0 },
3012 { "btsQ", { Evh1, Ib }, 0 },
3013 { "btrQ", { Evh1, Ib }, 0 },
3014 { "btcQ", { Evh1, Ib }, 0 },
3015 },
3016 /* REG_0FC7 */
3017 {
3018 { Bad_Opcode },
3019 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3020 { Bad_Opcode },
3021 { MOD_TABLE (MOD_0FC7_REG_3) },
3022 { MOD_TABLE (MOD_0FC7_REG_4) },
3023 { MOD_TABLE (MOD_0FC7_REG_5) },
3024 { MOD_TABLE (MOD_0FC7_REG_6) },
3025 { MOD_TABLE (MOD_0FC7_REG_7) },
3026 },
3027 /* REG_VEX_0F71 */
3028 {
3029 { Bad_Opcode },
3030 { Bad_Opcode },
3031 { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3032 { Bad_Opcode },
3033 { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3034 { Bad_Opcode },
3035 { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3036 },
3037 /* REG_VEX_0F72 */
3038 {
3039 { Bad_Opcode },
3040 { Bad_Opcode },
3041 { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3042 { Bad_Opcode },
3043 { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3044 { Bad_Opcode },
3045 { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3046 },
3047 /* REG_VEX_0F73 */
3048 {
3049 { Bad_Opcode },
3050 { Bad_Opcode },
3051 { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3052 { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3053 { Bad_Opcode },
3054 { Bad_Opcode },
3055 { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3056 { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3057 },
3058 /* REG_VEX_0FAE */
3059 {
3060 { Bad_Opcode },
3061 { Bad_Opcode },
3062 { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3063 { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3064 },
3065 /* REG_VEX_0F3849_X86_64_P_0_W_0_M_1 */
3066 {
3067 { RM_TABLE (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0) },
3068 },
3069 /* REG_VEX_0F38F3 */
3070 {
3071 { Bad_Opcode },
3072 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1) },
3073 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2) },
3074 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3) },
3075 },
3076 /* REG_0FXOP_09_01_L_0 */
3077 {
3078 { Bad_Opcode },
3079 { "blcfill", { VexGdq, Edq }, 0 },
3080 { "blsfill", { VexGdq, Edq }, 0 },
3081 { "blcs", { VexGdq, Edq }, 0 },
3082 { "tzmsk", { VexGdq, Edq }, 0 },
3083 { "blcic", { VexGdq, Edq }, 0 },
3084 { "blsic", { VexGdq, Edq }, 0 },
3085 { "t1mskc", { VexGdq, Edq }, 0 },
3086 },
3087 /* REG_0FXOP_09_02_L_0 */
3088 {
3089 { Bad_Opcode },
3090 { "blcmsk", { VexGdq, Edq }, 0 },
3091 { Bad_Opcode },
3092 { Bad_Opcode },
3093 { Bad_Opcode },
3094 { Bad_Opcode },
3095 { "blci", { VexGdq, Edq }, 0 },
3096 },
3097 /* REG_0FXOP_09_12_M_1_L_0 */
3098 {
3099 { "llwpcb", { Edq }, 0 },
3100 { "slwpcb", { Edq }, 0 },
3101 },
3102 /* REG_0FXOP_0A_12_L_0 */
3103 {
3104 { "lwpins", { VexGdq, Ed, Id }, 0 },
3105 { "lwpval", { VexGdq, Ed, Id }, 0 },
3106 },
3107
3108 #include "i386-dis-evex-reg.h"
3109 };
3110
3111 static const struct dis386 prefix_table[][4] = {
3112 /* PREFIX_90 */
3113 {
3114 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3115 { "pause", { XX }, 0 },
3116 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3117 { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3118 },
3119
3120 /* PREFIX_0F01_REG_1_RM_4 */
3121 {
3122 { Bad_Opcode },
3123 { Bad_Opcode },
3124 { "tdcall", { Skip_MODRM }, 0 },
3125 { Bad_Opcode },
3126 },
3127
3128 /* PREFIX_0F01_REG_1_RM_5 */
3129 {
3130 { Bad_Opcode },
3131 { Bad_Opcode },
3132 { X86_64_TABLE (X86_64_0F01_REG_1_RM_5_PREFIX_2) },
3133 { Bad_Opcode },
3134 },
3135
3136 /* PREFIX_0F01_REG_1_RM_6 */
3137 {
3138 { Bad_Opcode },
3139 { Bad_Opcode },
3140 { X86_64_TABLE (X86_64_0F01_REG_1_RM_6_PREFIX_2) },
3141 { Bad_Opcode },
3142 },
3143
3144 /* PREFIX_0F01_REG_1_RM_7 */
3145 {
3146 { "encls", { Skip_MODRM }, 0 },
3147 { Bad_Opcode },
3148 { X86_64_TABLE (X86_64_0F01_REG_1_RM_7_PREFIX_2) },
3149 { Bad_Opcode },
3150 },
3151
3152 /* PREFIX_0F01_REG_3_RM_1 */
3153 {
3154 { "vmmcall", { Skip_MODRM }, 0 },
3155 { "vmgexit", { Skip_MODRM }, 0 },
3156 { Bad_Opcode },
3157 { "vmgexit", { Skip_MODRM }, 0 },
3158 },
3159
3160 /* PREFIX_0F01_REG_5_MOD_0 */
3161 {
3162 { Bad_Opcode },
3163 { "rstorssp", { Mq }, PREFIX_OPCODE },
3164 },
3165
3166 /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3167 {
3168 { "serialize", { Skip_MODRM }, PREFIX_OPCODE },
3169 { "setssbsy", { Skip_MODRM }, PREFIX_OPCODE },
3170 { Bad_Opcode },
3171 { "xsusldtrk", { Skip_MODRM }, PREFIX_OPCODE },
3172 },
3173
3174 /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
3175 {
3176 { Bad_Opcode },
3177 { Bad_Opcode },
3178 { Bad_Opcode },
3179 { "xresldtrk", { Skip_MODRM }, PREFIX_OPCODE },
3180 },
3181
3182 /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3183 {
3184 { Bad_Opcode },
3185 { "saveprevssp", { Skip_MODRM }, PREFIX_OPCODE },
3186 },
3187
3188 /* PREFIX_0F01_REG_5_MOD_3_RM_4 */
3189 {
3190 { Bad_Opcode },
3191 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1) },
3192 },
3193
3194 /* PREFIX_0F01_REG_5_MOD_3_RM_5 */
3195 {
3196 { Bad_Opcode },
3197 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1) },
3198 },
3199
3200 /* PREFIX_0F01_REG_5_MOD_3_RM_6 */
3201 {
3202 { "rdpkru", { Skip_MODRM }, 0 },
3203 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1) },
3204 },
3205
3206 /* PREFIX_0F01_REG_5_MOD_3_RM_7 */
3207 {
3208 { "wrpkru", { Skip_MODRM }, 0 },
3209 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1) },
3210 },
3211
3212 /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3213 {
3214 { "monitorx", { { OP_Monitor, 0 } }, 0 },
3215 { "mcommit", { Skip_MODRM }, 0 },
3216 },
3217
3218 /* PREFIX_0F01_REG_7_MOD_3_RM_6 */
3219 {
3220 { "invlpgb", { Skip_MODRM }, 0 },
3221 { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1) },
3222 { Bad_Opcode },
3223 { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3) },
3224 },
3225
3226 /* PREFIX_0F01_REG_7_MOD_3_RM_7 */
3227 {
3228 { "tlbsync", { Skip_MODRM }, 0 },
3229 { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1) },
3230 { Bad_Opcode },
3231 { "pvalidate", { Skip_MODRM }, 0 },
3232 },
3233
3234 /* PREFIX_0F09 */
3235 {
3236 { "wbinvd", { XX }, 0 },
3237 { "wbnoinvd", { XX }, 0 },
3238 },
3239
3240 /* PREFIX_0F10 */
3241 {
3242 { "movups", { XM, EXx }, PREFIX_OPCODE },
3243 { "movss", { XM, EXd }, PREFIX_OPCODE },
3244 { "movupd", { XM, EXx }, PREFIX_OPCODE },
3245 { "movsd", { XM, EXq }, PREFIX_OPCODE },
3246 },
3247
3248 /* PREFIX_0F11 */
3249 {
3250 { "movups", { EXxS, XM }, PREFIX_OPCODE },
3251 { "movss", { EXdS, XM }, PREFIX_OPCODE },
3252 { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3253 { "movsd", { EXqS, XM }, PREFIX_OPCODE },
3254 },
3255
3256 /* PREFIX_0F12 */
3257 {
3258 { MOD_TABLE (MOD_0F12_PREFIX_0) },
3259 { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3260 { MOD_TABLE (MOD_0F12_PREFIX_2) },
3261 { "movddup", { XM, EXq }, PREFIX_OPCODE },
3262 },
3263
3264 /* PREFIX_0F16 */
3265 {
3266 { MOD_TABLE (MOD_0F16_PREFIX_0) },
3267 { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3268 { MOD_TABLE (MOD_0F16_PREFIX_2) },
3269 },
3270
3271 /* PREFIX_0F1A */
3272 {
3273 { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3274 { "bndcl", { Gbnd, Ev_bnd }, 0 },
3275 { "bndmov", { Gbnd, Ebnd }, 0 },
3276 { "bndcu", { Gbnd, Ev_bnd }, 0 },
3277 },
3278
3279 /* PREFIX_0F1B */
3280 {
3281 { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3282 { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3283 { "bndmov", { EbndS, Gbnd }, 0 },
3284 { "bndcn", { Gbnd, Ev_bnd }, 0 },
3285 },
3286
3287 /* PREFIX_0F1C */
3288 {
3289 { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3290 { "nopQ", { Ev }, PREFIX_OPCODE },
3291 { "nopQ", { Ev }, PREFIX_OPCODE },
3292 { "nopQ", { Ev }, PREFIX_OPCODE },
3293 },
3294
3295 /* PREFIX_0F1E */
3296 {
3297 { "nopQ", { Ev }, PREFIX_OPCODE },
3298 { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3299 { "nopQ", { Ev }, PREFIX_OPCODE },
3300 { "nopQ", { Ev }, PREFIX_OPCODE },
3301 },
3302
3303 /* PREFIX_0F2A */
3304 {
3305 { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3306 { "cvtsi2ss{%LQ|}", { XM, Edq }, PREFIX_OPCODE },
3307 { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3308 { "cvtsi2sd{%LQ|}", { XM, Edq }, 0 },
3309 },
3310
3311 /* PREFIX_0F2B */
3312 {
3313 { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3314 { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3315 { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3316 { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3317 },
3318
3319 /* PREFIX_0F2C */
3320 {
3321 { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3322 { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
3323 { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3324 { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3325 },
3326
3327 /* PREFIX_0F2D */
3328 {
3329 { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3330 { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
3331 { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3332 { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3333 },
3334
3335 /* PREFIX_0F2E */
3336 {
3337 { "ucomiss",{ XM, EXd }, 0 },
3338 { Bad_Opcode },
3339 { "ucomisd",{ XM, EXq }, 0 },
3340 },
3341
3342 /* PREFIX_0F2F */
3343 {
3344 { "comiss", { XM, EXd }, 0 },
3345 { Bad_Opcode },
3346 { "comisd", { XM, EXq }, 0 },
3347 },
3348
3349 /* PREFIX_0F51 */
3350 {
3351 { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3352 { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3353 { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3354 { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3355 },
3356
3357 /* PREFIX_0F52 */
3358 {
3359 { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3360 { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3361 },
3362
3363 /* PREFIX_0F53 */
3364 {
3365 { "rcpps", { XM, EXx }, PREFIX_OPCODE },
3366 { "rcpss", { XM, EXd }, PREFIX_OPCODE },
3367 },
3368
3369 /* PREFIX_0F58 */
3370 {
3371 { "addps", { XM, EXx }, PREFIX_OPCODE },
3372 { "addss", { XM, EXd }, PREFIX_OPCODE },
3373 { "addpd", { XM, EXx }, PREFIX_OPCODE },
3374 { "addsd", { XM, EXq }, PREFIX_OPCODE },
3375 },
3376
3377 /* PREFIX_0F59 */
3378 {
3379 { "mulps", { XM, EXx }, PREFIX_OPCODE },
3380 { "mulss", { XM, EXd }, PREFIX_OPCODE },
3381 { "mulpd", { XM, EXx }, PREFIX_OPCODE },
3382 { "mulsd", { XM, EXq }, PREFIX_OPCODE },
3383 },
3384
3385 /* PREFIX_0F5A */
3386 {
3387 { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3388 { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3389 { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3390 { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3391 },
3392
3393 /* PREFIX_0F5B */
3394 {
3395 { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3396 { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3397 { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3398 },
3399
3400 /* PREFIX_0F5C */
3401 {
3402 { "subps", { XM, EXx }, PREFIX_OPCODE },
3403 { "subss", { XM, EXd }, PREFIX_OPCODE },
3404 { "subpd", { XM, EXx }, PREFIX_OPCODE },
3405 { "subsd", { XM, EXq }, PREFIX_OPCODE },
3406 },
3407
3408 /* PREFIX_0F5D */
3409 {
3410 { "minps", { XM, EXx }, PREFIX_OPCODE },
3411 { "minss", { XM, EXd }, PREFIX_OPCODE },
3412 { "minpd", { XM, EXx }, PREFIX_OPCODE },
3413 { "minsd", { XM, EXq }, PREFIX_OPCODE },
3414 },
3415
3416 /* PREFIX_0F5E */
3417 {
3418 { "divps", { XM, EXx }, PREFIX_OPCODE },
3419 { "divss", { XM, EXd }, PREFIX_OPCODE },
3420 { "divpd", { XM, EXx }, PREFIX_OPCODE },
3421 { "divsd", { XM, EXq }, PREFIX_OPCODE },
3422 },
3423
3424 /* PREFIX_0F5F */
3425 {
3426 { "maxps", { XM, EXx }, PREFIX_OPCODE },
3427 { "maxss", { XM, EXd }, PREFIX_OPCODE },
3428 { "maxpd", { XM, EXx }, PREFIX_OPCODE },
3429 { "maxsd", { XM, EXq }, PREFIX_OPCODE },
3430 },
3431
3432 /* PREFIX_0F60 */
3433 {
3434 { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3435 { Bad_Opcode },
3436 { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3437 },
3438
3439 /* PREFIX_0F61 */
3440 {
3441 { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3442 { Bad_Opcode },
3443 { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3444 },
3445
3446 /* PREFIX_0F62 */
3447 {
3448 { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3449 { Bad_Opcode },
3450 { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3451 },
3452
3453 /* PREFIX_0F6F */
3454 {
3455 { "movq", { MX, EM }, PREFIX_OPCODE },
3456 { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3457 { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3458 },
3459
3460 /* PREFIX_0F70 */
3461 {
3462 { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3463 { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3464 { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3465 { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3466 },
3467
3468 /* PREFIX_0F78 */
3469 {
3470 {"vmread", { Em, Gm }, 0 },
3471 { Bad_Opcode },
3472 {"extrq", { XS, Ib, Ib }, 0 },
3473 {"insertq", { XM, XS, Ib, Ib }, 0 },
3474 },
3475
3476 /* PREFIX_0F79 */
3477 {
3478 {"vmwrite", { Gm, Em }, 0 },
3479 { Bad_Opcode },
3480 {"extrq", { XM, XS }, 0 },
3481 {"insertq", { XM, XS }, 0 },
3482 },
3483
3484 /* PREFIX_0F7C */
3485 {
3486 { Bad_Opcode },
3487 { Bad_Opcode },
3488 { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3489 { "haddps", { XM, EXx }, PREFIX_OPCODE },
3490 },
3491
3492 /* PREFIX_0F7D */
3493 {
3494 { Bad_Opcode },
3495 { Bad_Opcode },
3496 { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3497 { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3498 },
3499
3500 /* PREFIX_0F7E */
3501 {
3502 { "movK", { Edq, MX }, PREFIX_OPCODE },
3503 { "movq", { XM, EXq }, PREFIX_OPCODE },
3504 { "movK", { Edq, XM }, PREFIX_OPCODE },
3505 },
3506
3507 /* PREFIX_0F7F */
3508 {
3509 { "movq", { EMS, MX }, PREFIX_OPCODE },
3510 { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3511 { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3512 },
3513
3514 /* PREFIX_0FAE_REG_0_MOD_3 */
3515 {
3516 { Bad_Opcode },
3517 { "rdfsbase", { Ev }, 0 },
3518 },
3519
3520 /* PREFIX_0FAE_REG_1_MOD_3 */
3521 {
3522 { Bad_Opcode },
3523 { "rdgsbase", { Ev }, 0 },
3524 },
3525
3526 /* PREFIX_0FAE_REG_2_MOD_3 */
3527 {
3528 { Bad_Opcode },
3529 { "wrfsbase", { Ev }, 0 },
3530 },
3531
3532 /* PREFIX_0FAE_REG_3_MOD_3 */
3533 {
3534 { Bad_Opcode },
3535 { "wrgsbase", { Ev }, 0 },
3536 },
3537
3538 /* PREFIX_0FAE_REG_4_MOD_0 */
3539 {
3540 { "xsave", { FXSAVE }, 0 },
3541 { "ptwrite{%LQ|}", { Edq }, 0 },
3542 },
3543
3544 /* PREFIX_0FAE_REG_4_MOD_3 */
3545 {
3546 { Bad_Opcode },
3547 { "ptwrite{%LQ|}", { Edq }, 0 },
3548 },
3549
3550 /* PREFIX_0FAE_REG_5_MOD_3 */
3551 {
3552 { "lfence", { Skip_MODRM }, 0 },
3553 { "incsspK", { Edq }, PREFIX_OPCODE },
3554 },
3555
3556 /* PREFIX_0FAE_REG_6_MOD_0 */
3557 {
3558 { "xsaveopt", { FXSAVE }, PREFIX_OPCODE },
3559 { "clrssbsy", { Mq }, PREFIX_OPCODE },
3560 { "clwb", { Mb }, PREFIX_OPCODE },
3561 },
3562
3563 /* PREFIX_0FAE_REG_6_MOD_3 */
3564 {
3565 { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) },
3566 { "umonitor", { Eva }, PREFIX_OPCODE },
3567 { "tpause", { Edq }, PREFIX_OPCODE },
3568 { "umwait", { Edq }, PREFIX_OPCODE },
3569 },
3570
3571 /* PREFIX_0FAE_REG_7_MOD_0 */
3572 {
3573 { "clflush", { Mb }, 0 },
3574 { Bad_Opcode },
3575 { "clflushopt", { Mb }, 0 },
3576 },
3577
3578 /* PREFIX_0FB8 */
3579 {
3580 { Bad_Opcode },
3581 { "popcntS", { Gv, Ev }, 0 },
3582 },
3583
3584 /* PREFIX_0FBC */
3585 {
3586 { "bsfS", { Gv, Ev }, 0 },
3587 { "tzcntS", { Gv, Ev }, 0 },
3588 { "bsfS", { Gv, Ev }, 0 },
3589 },
3590
3591 /* PREFIX_0FBD */
3592 {
3593 { "bsrS", { Gv, Ev }, 0 },
3594 { "lzcntS", { Gv, Ev }, 0 },
3595 { "bsrS", { Gv, Ev }, 0 },
3596 },
3597
3598 /* PREFIX_0FC2 */
3599 {
3600 { "cmpps", { XM, EXx, CMP }, PREFIX_OPCODE },
3601 { "cmpss", { XM, EXd, CMP }, PREFIX_OPCODE },
3602 { "cmppd", { XM, EXx, CMP }, PREFIX_OPCODE },
3603 { "cmpsd", { XM, EXq, CMP }, PREFIX_OPCODE },
3604 },
3605
3606 /* PREFIX_0FC7_REG_6_MOD_0 */
3607 {
3608 { "vmptrld",{ Mq }, 0 },
3609 { "vmxon", { Mq }, 0 },
3610 { "vmclear",{ Mq }, 0 },
3611 },
3612
3613 /* PREFIX_0FC7_REG_6_MOD_3 */
3614 {
3615 { "rdrand", { Ev }, 0 },
3616 { X86_64_TABLE (X86_64_0FC7_REG_6_MOD_3_PREFIX_1) },
3617 { "rdrand", { Ev }, 0 }
3618 },
3619
3620 /* PREFIX_0FC7_REG_7_MOD_3 */
3621 {
3622 { "rdseed", { Ev }, 0 },
3623 { "rdpid", { Em }, 0 },
3624 { "rdseed", { Ev }, 0 },
3625 },
3626
3627 /* PREFIX_0FD0 */
3628 {
3629 { Bad_Opcode },
3630 { Bad_Opcode },
3631 { "addsubpd", { XM, EXx }, 0 },
3632 { "addsubps", { XM, EXx }, 0 },
3633 },
3634
3635 /* PREFIX_0FD6 */
3636 {
3637 { Bad_Opcode },
3638 { "movq2dq",{ XM, MS }, 0 },
3639 { "movq", { EXqS, XM }, 0 },
3640 { "movdq2q",{ MX, XS }, 0 },
3641 },
3642
3643 /* PREFIX_0FE6 */
3644 {
3645 { Bad_Opcode },
3646 { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
3647 { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
3648 { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
3649 },
3650
3651 /* PREFIX_0FE7 */
3652 {
3653 { "movntq", { Mq, MX }, PREFIX_OPCODE },
3654 { Bad_Opcode },
3655 { MOD_TABLE (MOD_0FE7_PREFIX_2) },
3656 },
3657
3658 /* PREFIX_0FF0 */
3659 {
3660 { Bad_Opcode },
3661 { Bad_Opcode },
3662 { Bad_Opcode },
3663 { MOD_TABLE (MOD_0FF0_PREFIX_3) },
3664 },
3665
3666 /* PREFIX_0FF7 */
3667 {
3668 { "maskmovq", { MX, MS }, PREFIX_OPCODE },
3669 { Bad_Opcode },
3670 { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
3671 },
3672
3673 /* PREFIX_0F38D8 */
3674 {
3675 { Bad_Opcode },
3676 { REG_TABLE (REG_0F38D8_PREFIX_1) },
3677 },
3678
3679 /* PREFIX_0F38DC */
3680 {
3681 { Bad_Opcode },
3682 { MOD_TABLE (MOD_0F38DC_PREFIX_1) },
3683 { "aesenc", { XM, EXx }, 0 },
3684 },
3685
3686 /* PREFIX_0F38DD */
3687 {
3688 { Bad_Opcode },
3689 { MOD_TABLE (MOD_0F38DD_PREFIX_1) },
3690 { "aesenclast", { XM, EXx }, 0 },
3691 },
3692
3693 /* PREFIX_0F38DE */
3694 {
3695 { Bad_Opcode },
3696 { MOD_TABLE (MOD_0F38DE_PREFIX_1) },
3697 { "aesdec", { XM, EXx }, 0 },
3698 },
3699
3700 /* PREFIX_0F38DF */
3701 {
3702 { Bad_Opcode },
3703 { MOD_TABLE (MOD_0F38DF_PREFIX_1) },
3704 { "aesdeclast", { XM, EXx }, 0 },
3705 },
3706
3707 /* PREFIX_0F38F0 */
3708 {
3709 { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3710 { Bad_Opcode },
3711 { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3712 { "crc32A", { Gdq, Eb }, PREFIX_OPCODE },
3713 },
3714
3715 /* PREFIX_0F38F1 */
3716 {
3717 { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3718 { Bad_Opcode },
3719 { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3720 { "crc32Q", { Gdq, Ev }, PREFIX_OPCODE },
3721 },
3722
3723 /* PREFIX_0F38F6 */
3724 {
3725 { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
3726 { "adoxS", { Gdq, Edq}, PREFIX_OPCODE },
3727 { "adcxS", { Gdq, Edq}, PREFIX_OPCODE },
3728 { Bad_Opcode },
3729 },
3730
3731 /* PREFIX_0F38F8 */
3732 {
3733 { Bad_Opcode },
3734 { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
3735 { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
3736 { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
3737 },
3738 /* PREFIX_0F38FA */
3739 {
3740 { Bad_Opcode },
3741 { MOD_TABLE (MOD_0F38FA_PREFIX_1) },
3742 },
3743
3744 /* PREFIX_0F38FB */
3745 {
3746 { Bad_Opcode },
3747 { MOD_TABLE (MOD_0F38FB_PREFIX_1) },
3748 },
3749
3750 /* PREFIX_0F3A0F */
3751 {
3752 { Bad_Opcode },
3753 { MOD_TABLE (MOD_0F3A0F_PREFIX_1)},
3754 },
3755
3756 /* PREFIX_VEX_0F10 */
3757 {
3758 { "vmovups", { XM, EXx }, 0 },
3759 { "vmovss", { XMScalar, VexScalarR, EXxmm_md }, 0 },
3760 { "vmovupd", { XM, EXx }, 0 },
3761 { "vmovsd", { XMScalar, VexScalarR, EXxmm_mq }, 0 },
3762 },
3763
3764 /* PREFIX_VEX_0F11 */
3765 {
3766 { "vmovups", { EXxS, XM }, 0 },
3767 { "vmovss", { EXdS, VexScalarR, XMScalar }, 0 },
3768 { "vmovupd", { EXxS, XM }, 0 },
3769 { "vmovsd", { EXqS, VexScalarR, XMScalar }, 0 },
3770 },
3771
3772 /* PREFIX_VEX_0F12 */
3773 {
3774 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
3775 { "vmovsldup", { XM, EXx }, 0 },
3776 { MOD_TABLE (MOD_VEX_0F12_PREFIX_2) },
3777 { "vmovddup", { XM, EXymmq }, 0 },
3778 },
3779
3780 /* PREFIX_VEX_0F16 */
3781 {
3782 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
3783 { "vmovshdup", { XM, EXx }, 0 },
3784 { MOD_TABLE (MOD_VEX_0F16_PREFIX_2) },
3785 },
3786
3787 /* PREFIX_VEX_0F2A */
3788 {
3789 { Bad_Opcode },
3790 { "vcvtsi2ss{%LQ|}", { XMScalar, VexScalar, Edq }, 0 },
3791 { Bad_Opcode },
3792 { "vcvtsi2sd{%LQ|}", { XMScalar, VexScalar, Edq }, 0 },
3793 },
3794
3795 /* PREFIX_VEX_0F2C */
3796 {
3797 { Bad_Opcode },
3798 { "vcvttss2si", { Gdq, EXxmm_md, EXxEVexS }, 0 },
3799 { Bad_Opcode },
3800 { "vcvttsd2si", { Gdq, EXxmm_mq, EXxEVexS }, 0 },
3801 },
3802
3803 /* PREFIX_VEX_0F2D */
3804 {
3805 { Bad_Opcode },
3806 { "vcvtss2si", { Gdq, EXxmm_md, EXxEVexR }, 0 },
3807 { Bad_Opcode },
3808 { "vcvtsd2si", { Gdq, EXxmm_mq, EXxEVexR }, 0 },
3809 },
3810
3811 /* PREFIX_VEX_0F2E */
3812 {
3813 { "vucomisX", { XMScalar, EXxmm_md, EXxEVexS }, PREFIX_OPCODE },
3814 { Bad_Opcode },
3815 { "vucomisX", { XMScalar, EXxmm_mq, EXxEVexS }, PREFIX_OPCODE },
3816 },
3817
3818 /* PREFIX_VEX_0F2F */
3819 {
3820 { "vcomisX", { XMScalar, EXxmm_md, EXxEVexS }, PREFIX_OPCODE },
3821 { Bad_Opcode },
3822 { "vcomisX", { XMScalar, EXxmm_mq, EXxEVexS }, PREFIX_OPCODE },
3823 },
3824
3825 /* PREFIX_VEX_0F41 */
3826 {
3827 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
3828 { Bad_Opcode },
3829 { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
3830 },
3831
3832 /* PREFIX_VEX_0F42 */
3833 {
3834 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
3835 { Bad_Opcode },
3836 { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
3837 },
3838
3839 /* PREFIX_VEX_0F44 */
3840 {
3841 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
3842 { Bad_Opcode },
3843 { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
3844 },
3845
3846 /* PREFIX_VEX_0F45 */
3847 {
3848 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
3849 { Bad_Opcode },
3850 { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
3851 },
3852
3853 /* PREFIX_VEX_0F46 */
3854 {
3855 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
3856 { Bad_Opcode },
3857 { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
3858 },
3859
3860 /* PREFIX_VEX_0F47 */
3861 {
3862 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
3863 { Bad_Opcode },
3864 { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
3865 },
3866
3867 /* PREFIX_VEX_0F4A */
3868 {
3869 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
3870 { Bad_Opcode },
3871 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
3872 },
3873
3874 /* PREFIX_VEX_0F4B */
3875 {
3876 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
3877 { Bad_Opcode },
3878 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
3879 },
3880
3881 /* PREFIX_VEX_0F51 */
3882 {
3883 { "vsqrtps", { XM, EXx }, 0 },
3884 { "vsqrtss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3885 { "vsqrtpd", { XM, EXx }, 0 },
3886 { "vsqrtsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
3887 },
3888
3889 /* PREFIX_VEX_0F52 */
3890 {
3891 { "vrsqrtps", { XM, EXx }, 0 },
3892 { "vrsqrtss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3893 },
3894
3895 /* PREFIX_VEX_0F53 */
3896 {
3897 { "vrcpps", { XM, EXx }, 0 },
3898 { "vrcpss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3899 },
3900
3901 /* PREFIX_VEX_0F58 */
3902 {
3903 { "vaddps", { XM, Vex, EXx }, 0 },
3904 { "vaddss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3905 { "vaddpd", { XM, Vex, EXx }, 0 },
3906 { "vaddsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
3907 },
3908
3909 /* PREFIX_VEX_0F59 */
3910 {
3911 { "vmulps", { XM, Vex, EXx }, 0 },
3912 { "vmulss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3913 { "vmulpd", { XM, Vex, EXx }, 0 },
3914 { "vmulsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
3915 },
3916
3917 /* PREFIX_VEX_0F5A */
3918 {
3919 { "vcvtps2pd", { XM, EXxmmq }, 0 },
3920 { "vcvtss2sd", { XMScalar, VexScalar, EXxmm_md }, 0 },
3921 { "vcvtpd2ps%XY",{ XMM, EXx }, 0 },
3922 { "vcvtsd2ss", { XMScalar, VexScalar, EXxmm_mq }, 0 },
3923 },
3924
3925 /* PREFIX_VEX_0F5B */
3926 {
3927 { "vcvtdq2ps", { XM, EXx }, 0 },
3928 { "vcvttps2dq", { XM, EXx }, 0 },
3929 { "vcvtps2dq", { XM, EXx }, 0 },
3930 },
3931
3932 /* PREFIX_VEX_0F5C */
3933 {
3934 { "vsubps", { XM, Vex, EXx }, 0 },
3935 { "vsubss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3936 { "vsubpd", { XM, Vex, EXx }, 0 },
3937 { "vsubsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
3938 },
3939
3940 /* PREFIX_VEX_0F5D */
3941 {
3942 { "vminps", { XM, Vex, EXx }, 0 },
3943 { "vminss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3944 { "vminpd", { XM, Vex, EXx }, 0 },
3945 { "vminsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
3946 },
3947
3948 /* PREFIX_VEX_0F5E */
3949 {
3950 { "vdivps", { XM, Vex, EXx }, 0 },
3951 { "vdivss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3952 { "vdivpd", { XM, Vex, EXx }, 0 },
3953 { "vdivsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
3954 },
3955
3956 /* PREFIX_VEX_0F5F */
3957 {
3958 { "vmaxps", { XM, Vex, EXx }, 0 },
3959 { "vmaxss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3960 { "vmaxpd", { XM, Vex, EXx }, 0 },
3961 { "vmaxsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
3962 },
3963
3964 /* PREFIX_VEX_0F6F */
3965 {
3966 { Bad_Opcode },
3967 { "vmovdqu", { XM, EXx }, 0 },
3968 { "vmovdqa", { XM, EXx }, 0 },
3969 },
3970
3971 /* PREFIX_VEX_0F70 */
3972 {
3973 { Bad_Opcode },
3974 { "vpshufhw", { XM, EXx, Ib }, 0 },
3975 { "vpshufd", { XM, EXx, Ib }, 0 },
3976 { "vpshuflw", { XM, EXx, Ib }, 0 },
3977 },
3978
3979 /* PREFIX_VEX_0F7C */
3980 {
3981 { Bad_Opcode },
3982 { Bad_Opcode },
3983 { "vhaddpd", { XM, Vex, EXx }, 0 },
3984 { "vhaddps", { XM, Vex, EXx }, 0 },
3985 },
3986
3987 /* PREFIX_VEX_0F7D */
3988 {
3989 { Bad_Opcode },
3990 { Bad_Opcode },
3991 { "vhsubpd", { XM, Vex, EXx }, 0 },
3992 { "vhsubps", { XM, Vex, EXx }, 0 },
3993 },
3994
3995 /* PREFIX_VEX_0F7E */
3996 {
3997 { Bad_Opcode },
3998 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
3999 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
4000 },
4001
4002 /* PREFIX_VEX_0F7F */
4003 {
4004 { Bad_Opcode },
4005 { "vmovdqu", { EXxS, XM }, 0 },
4006 { "vmovdqa", { EXxS, XM }, 0 },
4007 },
4008
4009 /* PREFIX_VEX_0F90 */
4010 {
4011 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
4012 { Bad_Opcode },
4013 { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
4014 },
4015
4016 /* PREFIX_VEX_0F91 */
4017 {
4018 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
4019 { Bad_Opcode },
4020 { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
4021 },
4022
4023 /* PREFIX_VEX_0F92 */
4024 {
4025 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
4026 { Bad_Opcode },
4027 { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
4028 { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
4029 },
4030
4031 /* PREFIX_VEX_0F93 */
4032 {
4033 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
4034 { Bad_Opcode },
4035 { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
4036 { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
4037 },
4038
4039 /* PREFIX_VEX_0F98 */
4040 {
4041 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
4042 { Bad_Opcode },
4043 { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
4044 },
4045
4046 /* PREFIX_VEX_0F99 */
4047 {
4048 { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
4049 { Bad_Opcode },
4050 { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
4051 },
4052
4053 /* PREFIX_VEX_0FC2 */
4054 {
4055 { "vcmpps", { XM, Vex, EXx, CMP }, 0 },
4056 { "vcmpss", { XMScalar, VexScalar, EXxmm_md, CMP }, 0 },
4057 { "vcmppd", { XM, Vex, EXx, CMP }, 0 },
4058 { "vcmpsd", { XMScalar, VexScalar, EXxmm_mq, CMP }, 0 },
4059 },
4060
4061 /* PREFIX_VEX_0FD0 */
4062 {
4063 { Bad_Opcode },
4064 { Bad_Opcode },
4065 { "vaddsubpd", { XM, Vex, EXx }, 0 },
4066 { "vaddsubps", { XM, Vex, EXx }, 0 },
4067 },
4068
4069 /* PREFIX_VEX_0FE6 */
4070 {
4071 { Bad_Opcode },
4072 { "vcvtdq2pd", { XM, EXxmmq }, 0 },
4073 { "vcvttpd2dq%XY", { XMM, EXx }, 0 },
4074 { "vcvtpd2dq%XY", { XMM, EXx }, 0 },
4075 },
4076
4077 /* PREFIX_VEX_0FF0 */
4078 {
4079 { Bad_Opcode },
4080 { Bad_Opcode },
4081 { Bad_Opcode },
4082 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
4083 },
4084
4085 /* PREFIX_VEX_0F3849_X86_64 */
4086 {
4087 { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_0) },
4088 { Bad_Opcode },
4089 { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_2) },
4090 { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_3) },
4091 },
4092
4093 /* PREFIX_VEX_0F384B_X86_64 */
4094 {
4095 { Bad_Opcode },
4096 { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_1) },
4097 { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_2) },
4098 { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_3) },
4099 },
4100
4101 /* PREFIX_VEX_0F385C_X86_64 */
4102 {
4103 { Bad_Opcode },
4104 { VEX_W_TABLE (VEX_W_0F385C_X86_64_P_1) },
4105 { Bad_Opcode },
4106 },
4107
4108 /* PREFIX_VEX_0F385E_X86_64 */
4109 {
4110 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_0) },
4111 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_1) },
4112 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_2) },
4113 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_3) },
4114 },
4115
4116 /* PREFIX_VEX_0F38F5 */
4117 {
4118 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
4119 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
4120 { Bad_Opcode },
4121 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
4122 },
4123
4124 /* PREFIX_VEX_0F38F6 */
4125 {
4126 { Bad_Opcode },
4127 { Bad_Opcode },
4128 { Bad_Opcode },
4129 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
4130 },
4131
4132 /* PREFIX_VEX_0F38F7 */
4133 {
4134 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
4135 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
4136 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
4137 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
4138 },
4139
4140 /* PREFIX_VEX_0F3AF0 */
4141 {
4142 { Bad_Opcode },
4143 { Bad_Opcode },
4144 { Bad_Opcode },
4145 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
4146 },
4147
4148 #include "i386-dis-evex-prefix.h"
4149 };
4150
4151 static const struct dis386 x86_64_table[][2] = {
4152 /* X86_64_06 */
4153 {
4154 { "pushP", { es }, 0 },
4155 },
4156
4157 /* X86_64_07 */
4158 {
4159 { "popP", { es }, 0 },
4160 },
4161
4162 /* X86_64_0E */
4163 {
4164 { "pushP", { cs }, 0 },
4165 },
4166
4167 /* X86_64_16 */
4168 {
4169 { "pushP", { ss }, 0 },
4170 },
4171
4172 /* X86_64_17 */
4173 {
4174 { "popP", { ss }, 0 },
4175 },
4176
4177 /* X86_64_1E */
4178 {
4179 { "pushP", { ds }, 0 },
4180 },
4181
4182 /* X86_64_1F */
4183 {
4184 { "popP", { ds }, 0 },
4185 },
4186
4187 /* X86_64_27 */
4188 {
4189 { "daa", { XX }, 0 },
4190 },
4191
4192 /* X86_64_2F */
4193 {
4194 { "das", { XX }, 0 },
4195 },
4196
4197 /* X86_64_37 */
4198 {
4199 { "aaa", { XX }, 0 },
4200 },
4201
4202 /* X86_64_3F */
4203 {
4204 { "aas", { XX }, 0 },
4205 },
4206
4207 /* X86_64_60 */
4208 {
4209 { "pushaP", { XX }, 0 },
4210 },
4211
4212 /* X86_64_61 */
4213 {
4214 { "popaP", { XX }, 0 },
4215 },
4216
4217 /* X86_64_62 */
4218 {
4219 { MOD_TABLE (MOD_62_32BIT) },
4220 { EVEX_TABLE (EVEX_0F) },
4221 },
4222
4223 /* X86_64_63 */
4224 {
4225 { "arpl", { Ew, Gw }, 0 },
4226 { "movs", { { OP_G, movsxd_mode }, { MOVSXD_Fixup, movsxd_mode } }, 0 },
4227 },
4228
4229 /* X86_64_6D */
4230 {
4231 { "ins{R|}", { Yzr, indirDX }, 0 },
4232 { "ins{G|}", { Yzr, indirDX }, 0 },
4233 },
4234
4235 /* X86_64_6F */
4236 {
4237 { "outs{R|}", { indirDXr, Xz }, 0 },
4238 { "outs{G|}", { indirDXr, Xz }, 0 },
4239 },
4240
4241 /* X86_64_82 */
4242 {
4243 /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */
4244 { REG_TABLE (REG_80) },
4245 },
4246
4247 /* X86_64_9A */
4248 {
4249 { "{l|}call{P|}", { Ap }, 0 },
4250 },
4251
4252 /* X86_64_C2 */
4253 {
4254 { "retP", { Iw, BND }, 0 },
4255 { "ret@", { Iw, BND }, 0 },
4256 },
4257
4258 /* X86_64_C3 */
4259 {
4260 { "retP", { BND }, 0 },
4261 { "ret@", { BND }, 0 },
4262 },
4263
4264 /* X86_64_C4 */
4265 {
4266 { MOD_TABLE (MOD_C4_32BIT) },
4267 { VEX_C4_TABLE (VEX_0F) },
4268 },
4269
4270 /* X86_64_C5 */
4271 {
4272 { MOD_TABLE (MOD_C5_32BIT) },
4273 { VEX_C5_TABLE (VEX_0F) },
4274 },
4275
4276 /* X86_64_CE */
4277 {
4278 { "into", { XX }, 0 },
4279 },
4280
4281 /* X86_64_D4 */
4282 {
4283 { "aam", { Ib }, 0 },
4284 },
4285
4286 /* X86_64_D5 */
4287 {
4288 { "aad", { Ib }, 0 },
4289 },
4290
4291 /* X86_64_E8 */
4292 {
4293 { "callP", { Jv, BND }, 0 },
4294 { "call@", { Jv, BND }, 0 }
4295 },
4296
4297 /* X86_64_E9 */
4298 {
4299 { "jmpP", { Jv, BND }, 0 },
4300 { "jmp@", { Jv, BND }, 0 }
4301 },
4302
4303 /* X86_64_EA */
4304 {
4305 { "{l|}jmp{P|}", { Ap }, 0 },
4306 },
4307
4308 /* X86_64_0F01_REG_0 */
4309 {
4310 { "sgdt{Q|Q}", { M }, 0 },
4311 { "sgdt", { M }, 0 },
4312 },
4313
4314 /* X86_64_0F01_REG_1 */
4315 {
4316 { "sidt{Q|Q}", { M }, 0 },
4317 { "sidt", { M }, 0 },
4318 },
4319
4320 /* X86_64_0F01_REG_1_RM_5_PREFIX_2 */
4321 {
4322 { Bad_Opcode },
4323 { "seamret", { Skip_MODRM }, 0 },
4324 },
4325
4326 /* X86_64_0F01_REG_1_RM_6_PREFIX_2 */
4327 {
4328 { Bad_Opcode },
4329 { "seamops", { Skip_MODRM }, 0 },
4330 },
4331
4332 /* X86_64_0F01_REG_1_RM_7_PREFIX_2 */
4333 {
4334 { Bad_Opcode },
4335 { "seamcall", { Skip_MODRM }, 0 },
4336 },
4337
4338 /* X86_64_0F01_REG_2 */
4339 {
4340 { "lgdt{Q|Q}", { M }, 0 },
4341 { "lgdt", { M }, 0 },
4342 },
4343
4344 /* X86_64_0F01_REG_3 */
4345 {
4346 { "lidt{Q|Q}", { M }, 0 },
4347 { "lidt", { M }, 0 },
4348 },
4349
4350 {
4351 /* X86_64_0F24 */
4352 { "movZ", { Em, Td }, 0 },
4353 },
4354
4355 {
4356 /* X86_64_0F26 */
4357 { "movZ", { Td, Em }, 0 },
4358 },
4359
4360 /* X86_64_VEX_0F3849 */
4361 {
4362 { Bad_Opcode },
4363 { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64) },
4364 },
4365
4366 /* X86_64_VEX_0F384B */
4367 {
4368 { Bad_Opcode },
4369 { PREFIX_TABLE (PREFIX_VEX_0F384B_X86_64) },
4370 },
4371
4372 /* X86_64_VEX_0F385C */
4373 {
4374 { Bad_Opcode },
4375 { PREFIX_TABLE (PREFIX_VEX_0F385C_X86_64) },
4376 },
4377
4378 /* X86_64_VEX_0F385E */
4379 {
4380 { Bad_Opcode },
4381 { PREFIX_TABLE (PREFIX_VEX_0F385E_X86_64) },
4382 },
4383
4384 /* X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1 */
4385 {
4386 { Bad_Opcode },
4387 { "uiret", { Skip_MODRM }, 0 },
4388 },
4389
4390 /* X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1 */
4391 {
4392 { Bad_Opcode },
4393 { "testui", { Skip_MODRM }, 0 },
4394 },
4395
4396 /* X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1 */
4397 {
4398 { Bad_Opcode },
4399 { "clui", { Skip_MODRM }, 0 },
4400 },
4401
4402 /* X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1 */
4403 {
4404 { Bad_Opcode },
4405 { "stui", { Skip_MODRM }, 0 },
4406 },
4407
4408 /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1 */
4409 {
4410 { Bad_Opcode },
4411 { "rmpadjust", { Skip_MODRM }, 0 },
4412 },
4413
4414 /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3 */
4415 {
4416 { Bad_Opcode },
4417 { "rmpupdate", { Skip_MODRM }, 0 },
4418 },
4419
4420 /* X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1 */
4421 {
4422 { Bad_Opcode },
4423 { "psmash", { Skip_MODRM }, 0 },
4424 },
4425
4426 /* X86_64_0FC7_REG_6_MOD_3_PREFIX_1 */
4427 {
4428 { Bad_Opcode },
4429 { "senduipi", { Eq }, 0 },
4430 },
4431 };
4432
4433 static const struct dis386 three_byte_table[][256] = {
4434
4435 /* THREE_BYTE_0F38 */
4436 {
4437 /* 00 */
4438 { "pshufb", { MX, EM }, PREFIX_OPCODE },
4439 { "phaddw", { MX, EM }, PREFIX_OPCODE },
4440 { "phaddd", { MX, EM }, PREFIX_OPCODE },
4441 { "phaddsw", { MX, EM }, PREFIX_OPCODE },
4442 { "pmaddubsw", { MX, EM }, PREFIX_OPCODE },
4443 { "phsubw", { MX, EM }, PREFIX_OPCODE },
4444 { "phsubd", { MX, EM }, PREFIX_OPCODE },
4445 { "phsubsw", { MX, EM }, PREFIX_OPCODE },
4446 /* 08 */
4447 { "psignb", { MX, EM }, PREFIX_OPCODE },
4448 { "psignw", { MX, EM }, PREFIX_OPCODE },
4449 { "psignd", { MX, EM }, PREFIX_OPCODE },
4450 { "pmulhrsw", { MX, EM }, PREFIX_OPCODE },
4451 { Bad_Opcode },
4452 { Bad_Opcode },
4453 { Bad_Opcode },
4454 { Bad_Opcode },
4455 /* 10 */
4456 { "pblendvb", { XM, EXx, XMM0 }, PREFIX_DATA },
4457 { Bad_Opcode },
4458 { Bad_Opcode },
4459 { Bad_Opcode },
4460 { "blendvps", { XM, EXx, XMM0 }, PREFIX_DATA },
4461 { "blendvpd", { XM, EXx, XMM0 }, PREFIX_DATA },
4462 { Bad_Opcode },
4463 { "ptest", { XM, EXx }, PREFIX_DATA },
4464 /* 18 */
4465 { Bad_Opcode },
4466 { Bad_Opcode },
4467 { Bad_Opcode },
4468 { Bad_Opcode },
4469 { "pabsb", { MX, EM }, PREFIX_OPCODE },
4470 { "pabsw", { MX, EM }, PREFIX_OPCODE },
4471 { "pabsd", { MX, EM }, PREFIX_OPCODE },
4472 { Bad_Opcode },
4473 /* 20 */
4474 { "pmovsxbw", { XM, EXq }, PREFIX_DATA },
4475 { "pmovsxbd", { XM, EXd }, PREFIX_DATA },
4476 { "pmovsxbq", { XM, EXw }, PREFIX_DATA },
4477 { "pmovsxwd", { XM, EXq }, PREFIX_DATA },
4478 { "pmovsxwq", { XM, EXd }, PREFIX_DATA },
4479 { "pmovsxdq", { XM, EXq }, PREFIX_DATA },
4480 { Bad_Opcode },
4481 { Bad_Opcode },
4482 /* 28 */
4483 { "pmuldq", { XM, EXx }, PREFIX_DATA },
4484 { "pcmpeqq", { XM, EXx }, PREFIX_DATA },
4485 { MOD_TABLE (MOD_0F382A) },
4486 { "packusdw", { XM, EXx }, PREFIX_DATA },
4487 { Bad_Opcode },
4488 { Bad_Opcode },
4489 { Bad_Opcode },
4490 { Bad_Opcode },
4491 /* 30 */
4492 { "pmovzxbw", { XM, EXq }, PREFIX_DATA },
4493 { "pmovzxbd", { XM, EXd }, PREFIX_DATA },
4494 { "pmovzxbq", { XM, EXw }, PREFIX_DATA },
4495 { "pmovzxwd", { XM, EXq }, PREFIX_DATA },
4496 { "pmovzxwq", { XM, EXd }, PREFIX_DATA },
4497 { "pmovzxdq", { XM, EXq }, PREFIX_DATA },
4498 { Bad_Opcode },
4499 { "pcmpgtq", { XM, EXx }, PREFIX_DATA },
4500 /* 38 */
4501 { "pminsb", { XM, EXx }, PREFIX_DATA },
4502 { "pminsd", { XM, EXx }, PREFIX_DATA },
4503 { "pminuw", { XM, EXx }, PREFIX_DATA },
4504 { "pminud", { XM, EXx }, PREFIX_DATA },
4505 { "pmaxsb", { XM, EXx }, PREFIX_DATA },
4506 { "pmaxsd", { XM, EXx }, PREFIX_DATA },
4507 { "pmaxuw", { XM, EXx }, PREFIX_DATA },
4508 { "pmaxud", { XM, EXx }, PREFIX_DATA },
4509 /* 40 */
4510 { "pmulld", { XM, EXx }, PREFIX_DATA },
4511 { "phminposuw", { XM, EXx }, PREFIX_DATA },
4512 { Bad_Opcode },
4513 { Bad_Opcode },
4514 { Bad_Opcode },
4515 { Bad_Opcode },
4516 { Bad_Opcode },
4517 { Bad_Opcode },
4518 /* 48 */
4519 { Bad_Opcode },
4520 { Bad_Opcode },
4521 { Bad_Opcode },
4522 { Bad_Opcode },
4523 { Bad_Opcode },
4524 { Bad_Opcode },
4525 { Bad_Opcode },
4526 { Bad_Opcode },
4527 /* 50 */
4528 { Bad_Opcode },
4529 { Bad_Opcode },
4530 { Bad_Opcode },
4531 { Bad_Opcode },
4532 { Bad_Opcode },
4533 { Bad_Opcode },
4534 { Bad_Opcode },
4535 { Bad_Opcode },
4536 /* 58 */
4537 { Bad_Opcode },
4538 { Bad_Opcode },
4539 { Bad_Opcode },
4540 { Bad_Opcode },
4541 { Bad_Opcode },
4542 { Bad_Opcode },
4543 { Bad_Opcode },
4544 { Bad_Opcode },
4545 /* 60 */
4546 { Bad_Opcode },
4547 { Bad_Opcode },
4548 { Bad_Opcode },
4549 { Bad_Opcode },
4550 { Bad_Opcode },
4551 { Bad_Opcode },
4552 { Bad_Opcode },
4553 { Bad_Opcode },
4554 /* 68 */
4555 { Bad_Opcode },
4556 { Bad_Opcode },
4557 { Bad_Opcode },
4558 { Bad_Opcode },
4559 { Bad_Opcode },
4560 { Bad_Opcode },
4561 { Bad_Opcode },
4562 { Bad_Opcode },
4563 /* 70 */
4564 { Bad_Opcode },
4565 { Bad_Opcode },
4566 { Bad_Opcode },
4567 { Bad_Opcode },
4568 { Bad_Opcode },
4569 { Bad_Opcode },
4570 { Bad_Opcode },
4571 { Bad_Opcode },
4572 /* 78 */
4573 { Bad_Opcode },
4574 { Bad_Opcode },
4575 { Bad_Opcode },
4576 { Bad_Opcode },
4577 { Bad_Opcode },
4578 { Bad_Opcode },
4579 { Bad_Opcode },
4580 { Bad_Opcode },
4581 /* 80 */
4582 { "invept", { Gm, Mo }, PREFIX_DATA },
4583 { "invvpid", { Gm, Mo }, PREFIX_DATA },
4584 { "invpcid", { Gm, M }, PREFIX_DATA },
4585 { Bad_Opcode },
4586 { Bad_Opcode },
4587 { Bad_Opcode },
4588 { Bad_Opcode },
4589 { Bad_Opcode },
4590 /* 88 */
4591 { Bad_Opcode },
4592 { Bad_Opcode },
4593 { Bad_Opcode },
4594 { Bad_Opcode },
4595 { Bad_Opcode },
4596 { Bad_Opcode },
4597 { Bad_Opcode },
4598 { Bad_Opcode },
4599 /* 90 */
4600 { Bad_Opcode },
4601 { Bad_Opcode },
4602 { Bad_Opcode },
4603 { Bad_Opcode },
4604 { Bad_Opcode },
4605 { Bad_Opcode },
4606 { Bad_Opcode },
4607 { Bad_Opcode },
4608 /* 98 */
4609 { Bad_Opcode },
4610 { Bad_Opcode },
4611 { Bad_Opcode },
4612 { Bad_Opcode },
4613 { Bad_Opcode },
4614 { Bad_Opcode },
4615 { Bad_Opcode },
4616 { Bad_Opcode },
4617 /* a0 */
4618 { Bad_Opcode },
4619 { Bad_Opcode },
4620 { Bad_Opcode },
4621 { Bad_Opcode },
4622 { Bad_Opcode },
4623 { Bad_Opcode },
4624 { Bad_Opcode },
4625 { Bad_Opcode },
4626 /* a8 */
4627 { Bad_Opcode },
4628 { Bad_Opcode },
4629 { Bad_Opcode },
4630 { Bad_Opcode },
4631 { Bad_Opcode },
4632 { Bad_Opcode },
4633 { Bad_Opcode },
4634 { Bad_Opcode },
4635 /* b0 */
4636 { Bad_Opcode },
4637 { Bad_Opcode },
4638 { Bad_Opcode },
4639 { Bad_Opcode },
4640 { Bad_Opcode },
4641 { Bad_Opcode },
4642 { Bad_Opcode },
4643 { Bad_Opcode },
4644 /* b8 */
4645 { Bad_Opcode },
4646 { Bad_Opcode },
4647 { Bad_Opcode },
4648 { Bad_Opcode },
4649 { Bad_Opcode },
4650 { Bad_Opcode },
4651 { Bad_Opcode },
4652 { Bad_Opcode },
4653 /* c0 */
4654 { Bad_Opcode },
4655 { Bad_Opcode },
4656 { Bad_Opcode },
4657 { Bad_Opcode },
4658 { Bad_Opcode },
4659 { Bad_Opcode },
4660 { Bad_Opcode },
4661 { Bad_Opcode },
4662 /* c8 */
4663 { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4664 { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4665 { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4666 { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4667 { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4668 { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4669 { Bad_Opcode },
4670 { "gf2p8mulb", { XM, EXxmm }, PREFIX_DATA },
4671 /* d0 */
4672 { Bad_Opcode },
4673 { Bad_Opcode },
4674 { Bad_Opcode },
4675 { Bad_Opcode },
4676 { Bad_Opcode },
4677 { Bad_Opcode },
4678 { Bad_Opcode },
4679 { Bad_Opcode },
4680 /* d8 */
4681 { PREFIX_TABLE (PREFIX_0F38D8) },
4682 { Bad_Opcode },
4683 { Bad_Opcode },
4684 { "aesimc", { XM, EXx }, PREFIX_DATA },
4685 { PREFIX_TABLE (PREFIX_0F38DC) },
4686 { PREFIX_TABLE (PREFIX_0F38DD) },
4687 { PREFIX_TABLE (PREFIX_0F38DE) },
4688 { PREFIX_TABLE (PREFIX_0F38DF) },
4689 /* e0 */
4690 { Bad_Opcode },
4691 { Bad_Opcode },
4692 { Bad_Opcode },
4693 { Bad_Opcode },
4694 { Bad_Opcode },
4695 { Bad_Opcode },
4696 { Bad_Opcode },
4697 { Bad_Opcode },
4698 /* e8 */
4699 { Bad_Opcode },
4700 { Bad_Opcode },
4701 { Bad_Opcode },
4702 { Bad_Opcode },
4703 { Bad_Opcode },
4704 { Bad_Opcode },
4705 { Bad_Opcode },
4706 { Bad_Opcode },
4707 /* f0 */
4708 { PREFIX_TABLE (PREFIX_0F38F0) },
4709 { PREFIX_TABLE (PREFIX_0F38F1) },
4710 { Bad_Opcode },
4711 { Bad_Opcode },
4712 { Bad_Opcode },
4713 { MOD_TABLE (MOD_0F38F5) },
4714 { PREFIX_TABLE (PREFIX_0F38F6) },
4715 { Bad_Opcode },
4716 /* f8 */
4717 { PREFIX_TABLE (PREFIX_0F38F8) },
4718 { MOD_TABLE (MOD_0F38F9) },
4719 { PREFIX_TABLE (PREFIX_0F38FA) },
4720 { PREFIX_TABLE (PREFIX_0F38FB) },
4721 { Bad_Opcode },
4722 { Bad_Opcode },
4723 { Bad_Opcode },
4724 { Bad_Opcode },
4725 },
4726 /* THREE_BYTE_0F3A */
4727 {
4728 /* 00 */
4729 { Bad_Opcode },
4730 { Bad_Opcode },
4731 { Bad_Opcode },
4732 { Bad_Opcode },
4733 { Bad_Opcode },
4734 { Bad_Opcode },
4735 { Bad_Opcode },
4736 { Bad_Opcode },
4737 /* 08 */
4738 { "roundps", { XM, EXx, Ib }, PREFIX_DATA },
4739 { "roundpd", { XM, EXx, Ib }, PREFIX_DATA },
4740 { "roundss", { XM, EXd, Ib }, PREFIX_DATA },
4741 { "roundsd", { XM, EXq, Ib }, PREFIX_DATA },
4742 { "blendps", { XM, EXx, Ib }, PREFIX_DATA },
4743 { "blendpd", { XM, EXx, Ib }, PREFIX_DATA },
4744 { "pblendw", { XM, EXx, Ib }, PREFIX_DATA },
4745 { "palignr", { MX, EM, Ib }, PREFIX_OPCODE },
4746 /* 10 */
4747 { Bad_Opcode },
4748 { Bad_Opcode },
4749 { Bad_Opcode },
4750 { Bad_Opcode },
4751 { "pextrb", { Edqb, XM, Ib }, PREFIX_DATA },
4752 { "pextrw", { Edqw, XM, Ib }, PREFIX_DATA },
4753 { "pextrK", { Edq, XM, Ib }, PREFIX_DATA },
4754 { "extractps", { Edqd, XM, Ib }, PREFIX_DATA },
4755 /* 18 */
4756 { Bad_Opcode },
4757 { Bad_Opcode },
4758 { Bad_Opcode },
4759 { Bad_Opcode },
4760 { Bad_Opcode },
4761 { Bad_Opcode },
4762 { Bad_Opcode },
4763 { Bad_Opcode },
4764 /* 20 */
4765 { "pinsrb", { XM, Edqb, Ib }, PREFIX_DATA },
4766 { "insertps", { XM, EXd, Ib }, PREFIX_DATA },
4767 { "pinsrK", { XM, Edq, Ib }, PREFIX_DATA },
4768 { Bad_Opcode },
4769 { Bad_Opcode },
4770 { Bad_Opcode },
4771 { Bad_Opcode },
4772 { Bad_Opcode },
4773 /* 28 */
4774 { Bad_Opcode },
4775 { Bad_Opcode },
4776 { Bad_Opcode },
4777 { Bad_Opcode },
4778 { Bad_Opcode },
4779 { Bad_Opcode },
4780 { Bad_Opcode },
4781 { Bad_Opcode },
4782 /* 30 */
4783 { Bad_Opcode },
4784 { Bad_Opcode },
4785 { Bad_Opcode },
4786 { Bad_Opcode },
4787 { Bad_Opcode },
4788 { Bad_Opcode },
4789 { Bad_Opcode },
4790 { Bad_Opcode },
4791 /* 38 */
4792 { Bad_Opcode },
4793 { Bad_Opcode },
4794 { Bad_Opcode },
4795 { Bad_Opcode },
4796 { Bad_Opcode },
4797 { Bad_Opcode },
4798 { Bad_Opcode },
4799 { Bad_Opcode },
4800 /* 40 */
4801 { "dpps", { XM, EXx, Ib }, PREFIX_DATA },
4802 { "dppd", { XM, EXx, Ib }, PREFIX_DATA },
4803 { "mpsadbw", { XM, EXx, Ib }, PREFIX_DATA },
4804 { Bad_Opcode },
4805 { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_DATA },
4806 { Bad_Opcode },
4807 { Bad_Opcode },
4808 { Bad_Opcode },
4809 /* 48 */
4810 { Bad_Opcode },
4811 { Bad_Opcode },
4812 { Bad_Opcode },
4813 { Bad_Opcode },
4814 { Bad_Opcode },
4815 { Bad_Opcode },
4816 { Bad_Opcode },
4817 { Bad_Opcode },
4818 /* 50 */
4819 { Bad_Opcode },
4820 { Bad_Opcode },
4821 { Bad_Opcode },
4822 { Bad_Opcode },
4823 { Bad_Opcode },
4824 { Bad_Opcode },
4825 { Bad_Opcode },
4826 { Bad_Opcode },
4827 /* 58 */
4828 { Bad_Opcode },
4829 { Bad_Opcode },
4830 { Bad_Opcode },
4831 { Bad_Opcode },
4832 { Bad_Opcode },
4833 { Bad_Opcode },
4834 { Bad_Opcode },
4835 { Bad_Opcode },
4836 /* 60 */
4837 { "pcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
4838 { "pcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
4839 { "pcmpistrm", { XM, EXx, Ib }, PREFIX_DATA },
4840 { "pcmpistri", { XM, EXx, Ib }, PREFIX_DATA },
4841 { Bad_Opcode },
4842 { Bad_Opcode },
4843 { Bad_Opcode },
4844 { Bad_Opcode },
4845 /* 68 */
4846 { Bad_Opcode },
4847 { Bad_Opcode },
4848 { Bad_Opcode },
4849 { Bad_Opcode },
4850 { Bad_Opcode },
4851 { Bad_Opcode },
4852 { Bad_Opcode },
4853 { Bad_Opcode },
4854 /* 70 */
4855 { Bad_Opcode },
4856 { Bad_Opcode },
4857 { Bad_Opcode },
4858 { Bad_Opcode },
4859 { Bad_Opcode },
4860 { Bad_Opcode },
4861 { Bad_Opcode },
4862 { Bad_Opcode },
4863 /* 78 */
4864 { Bad_Opcode },
4865 { Bad_Opcode },
4866 { Bad_Opcode },
4867 { Bad_Opcode },
4868 { Bad_Opcode },
4869 { Bad_Opcode },
4870 { Bad_Opcode },
4871 { Bad_Opcode },
4872 /* 80 */
4873 { Bad_Opcode },
4874 { Bad_Opcode },
4875 { Bad_Opcode },
4876 { Bad_Opcode },
4877 { Bad_Opcode },
4878 { Bad_Opcode },
4879 { Bad_Opcode },
4880 { Bad_Opcode },
4881 /* 88 */
4882 { Bad_Opcode },
4883 { Bad_Opcode },
4884 { Bad_Opcode },
4885 { Bad_Opcode },
4886 { Bad_Opcode },
4887 { Bad_Opcode },
4888 { Bad_Opcode },
4889 { Bad_Opcode },
4890 /* 90 */
4891 { Bad_Opcode },
4892 { Bad_Opcode },
4893 { Bad_Opcode },
4894 { Bad_Opcode },
4895 { Bad_Opcode },
4896 { Bad_Opcode },
4897 { Bad_Opcode },
4898 { Bad_Opcode },
4899 /* 98 */
4900 { Bad_Opcode },
4901 { Bad_Opcode },
4902 { Bad_Opcode },
4903 { Bad_Opcode },
4904 { Bad_Opcode },
4905 { Bad_Opcode },
4906 { Bad_Opcode },
4907 { Bad_Opcode },
4908 /* a0 */
4909 { Bad_Opcode },
4910 { Bad_Opcode },
4911 { Bad_Opcode },
4912 { Bad_Opcode },
4913 { Bad_Opcode },
4914 { Bad_Opcode },
4915 { Bad_Opcode },
4916 { Bad_Opcode },
4917 /* a8 */
4918 { Bad_Opcode },
4919 { Bad_Opcode },
4920 { Bad_Opcode },
4921 { Bad_Opcode },
4922 { Bad_Opcode },
4923 { Bad_Opcode },
4924 { Bad_Opcode },
4925 { Bad_Opcode },
4926 /* b0 */
4927 { Bad_Opcode },
4928 { Bad_Opcode },
4929 { Bad_Opcode },
4930 { Bad_Opcode },
4931 { Bad_Opcode },
4932 { Bad_Opcode },
4933 { Bad_Opcode },
4934 { Bad_Opcode },
4935 /* b8 */
4936 { Bad_Opcode },
4937 { Bad_Opcode },
4938 { Bad_Opcode },
4939 { Bad_Opcode },
4940 { Bad_Opcode },
4941 { Bad_Opcode },
4942 { Bad_Opcode },
4943 { Bad_Opcode },
4944 /* c0 */
4945 { Bad_Opcode },
4946 { Bad_Opcode },
4947 { Bad_Opcode },
4948 { Bad_Opcode },
4949 { Bad_Opcode },
4950 { Bad_Opcode },
4951 { Bad_Opcode },
4952 { Bad_Opcode },
4953 /* c8 */
4954 { Bad_Opcode },
4955 { Bad_Opcode },
4956 { Bad_Opcode },
4957 { Bad_Opcode },
4958 { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4959 { Bad_Opcode },
4960 { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_DATA },
4961 { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_DATA },
4962 /* d0 */
4963 { Bad_Opcode },
4964 { Bad_Opcode },
4965 { Bad_Opcode },
4966 { Bad_Opcode },
4967 { Bad_Opcode },
4968 { Bad_Opcode },
4969 { Bad_Opcode },
4970 { Bad_Opcode },
4971 /* d8 */
4972 { Bad_Opcode },
4973 { Bad_Opcode },
4974 { Bad_Opcode },
4975 { Bad_Opcode },
4976 { Bad_Opcode },
4977 { Bad_Opcode },
4978 { Bad_Opcode },
4979 { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
4980 /* e0 */
4981 { Bad_Opcode },
4982 { Bad_Opcode },
4983 { Bad_Opcode },
4984 { Bad_Opcode },
4985 { Bad_Opcode },
4986 { Bad_Opcode },
4987 { Bad_Opcode },
4988 { Bad_Opcode },
4989 /* e8 */
4990 { Bad_Opcode },
4991 { Bad_Opcode },
4992 { Bad_Opcode },
4993 { Bad_Opcode },
4994 { Bad_Opcode },
4995 { Bad_Opcode },
4996 { Bad_Opcode },
4997 { Bad_Opcode },
4998 /* f0 */
4999 { PREFIX_TABLE (PREFIX_0F3A0F) },
5000 { Bad_Opcode },
5001 { Bad_Opcode },
5002 { Bad_Opcode },
5003 { Bad_Opcode },
5004 { Bad_Opcode },
5005 { Bad_Opcode },
5006 { Bad_Opcode },
5007 /* f8 */
5008 { Bad_Opcode },
5009 { Bad_Opcode },
5010 { Bad_Opcode },
5011 { Bad_Opcode },
5012 { Bad_Opcode },
5013 { Bad_Opcode },
5014 { Bad_Opcode },
5015 { Bad_Opcode },
5016 },
5017 };
5018
5019 static const struct dis386 xop_table[][256] = {
5020 /* XOP_08 */
5021 {
5022 /* 00 */
5023 { Bad_Opcode },
5024 { Bad_Opcode },
5025 { Bad_Opcode },
5026 { Bad_Opcode },
5027 { Bad_Opcode },
5028 { Bad_Opcode },
5029 { Bad_Opcode },
5030 { Bad_Opcode },
5031 /* 08 */
5032 { Bad_Opcode },
5033 { Bad_Opcode },
5034 { Bad_Opcode },
5035 { Bad_Opcode },
5036 { Bad_Opcode },
5037 { Bad_Opcode },
5038 { Bad_Opcode },
5039 { Bad_Opcode },
5040 /* 10 */
5041 { Bad_Opcode },
5042 { Bad_Opcode },
5043 { Bad_Opcode },
5044 { Bad_Opcode },
5045 { Bad_Opcode },
5046 { Bad_Opcode },
5047 { Bad_Opcode },
5048 { Bad_Opcode },
5049 /* 18 */
5050 { Bad_Opcode },
5051 { Bad_Opcode },
5052 { Bad_Opcode },
5053 { Bad_Opcode },
5054 { Bad_Opcode },
5055 { Bad_Opcode },
5056 { Bad_Opcode },
5057 { Bad_Opcode },
5058 /* 20 */
5059 { Bad_Opcode },
5060 { Bad_Opcode },
5061 { Bad_Opcode },
5062 { Bad_Opcode },
5063 { Bad_Opcode },
5064 { Bad_Opcode },
5065 { Bad_Opcode },
5066 { Bad_Opcode },
5067 /* 28 */
5068 { Bad_Opcode },
5069 { Bad_Opcode },
5070 { Bad_Opcode },
5071 { Bad_Opcode },
5072 { Bad_Opcode },
5073 { Bad_Opcode },
5074 { Bad_Opcode },
5075 { Bad_Opcode },
5076 /* 30 */
5077 { Bad_Opcode },
5078 { Bad_Opcode },
5079 { Bad_Opcode },
5080 { Bad_Opcode },
5081 { Bad_Opcode },
5082 { Bad_Opcode },
5083 { Bad_Opcode },
5084 { Bad_Opcode },
5085 /* 38 */
5086 { Bad_Opcode },
5087 { Bad_Opcode },
5088 { Bad_Opcode },
5089 { Bad_Opcode },
5090 { Bad_Opcode },
5091 { Bad_Opcode },
5092 { Bad_Opcode },
5093 { Bad_Opcode },
5094 /* 40 */
5095 { Bad_Opcode },
5096 { Bad_Opcode },
5097 { Bad_Opcode },
5098 { Bad_Opcode },
5099 { Bad_Opcode },
5100 { Bad_Opcode },
5101 { Bad_Opcode },
5102 { Bad_Opcode },
5103 /* 48 */
5104 { Bad_Opcode },
5105 { Bad_Opcode },
5106 { Bad_Opcode },
5107 { Bad_Opcode },
5108 { Bad_Opcode },
5109 { Bad_Opcode },
5110 { Bad_Opcode },
5111 { Bad_Opcode },
5112 /* 50 */
5113 { Bad_Opcode },
5114 { Bad_Opcode },
5115 { Bad_Opcode },
5116 { Bad_Opcode },
5117 { Bad_Opcode },
5118 { Bad_Opcode },
5119 { Bad_Opcode },
5120 { Bad_Opcode },
5121 /* 58 */
5122 { Bad_Opcode },
5123 { Bad_Opcode },
5124 { Bad_Opcode },
5125 { Bad_Opcode },
5126 { Bad_Opcode },
5127 { Bad_Opcode },
5128 { Bad_Opcode },
5129 { Bad_Opcode },
5130 /* 60 */
5131 { Bad_Opcode },
5132 { Bad_Opcode },
5133 { Bad_Opcode },
5134 { Bad_Opcode },
5135 { Bad_Opcode },
5136 { Bad_Opcode },
5137 { Bad_Opcode },
5138 { Bad_Opcode },
5139 /* 68 */
5140 { Bad_Opcode },
5141 { Bad_Opcode },
5142 { Bad_Opcode },
5143 { Bad_Opcode },
5144 { Bad_Opcode },
5145 { Bad_Opcode },
5146 { Bad_Opcode },
5147 { Bad_Opcode },
5148 /* 70 */
5149 { Bad_Opcode },
5150 { Bad_Opcode },
5151 { Bad_Opcode },
5152 { Bad_Opcode },
5153 { Bad_Opcode },
5154 { Bad_Opcode },
5155 { Bad_Opcode },
5156 { Bad_Opcode },
5157 /* 78 */
5158 { Bad_Opcode },
5159 { Bad_Opcode },
5160 { Bad_Opcode },
5161 { Bad_Opcode },
5162 { Bad_Opcode },
5163 { Bad_Opcode },
5164 { Bad_Opcode },
5165 { Bad_Opcode },
5166 /* 80 */
5167 { Bad_Opcode },
5168 { Bad_Opcode },
5169 { Bad_Opcode },
5170 { Bad_Opcode },
5171 { Bad_Opcode },
5172 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_85) },
5173 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_86) },
5174 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_87) },
5175 /* 88 */
5176 { Bad_Opcode },
5177 { Bad_Opcode },
5178 { Bad_Opcode },
5179 { Bad_Opcode },
5180 { Bad_Opcode },
5181 { Bad_Opcode },
5182 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8E) },
5183 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8F) },
5184 /* 90 */
5185 { Bad_Opcode },
5186 { Bad_Opcode },
5187 { Bad_Opcode },
5188 { Bad_Opcode },
5189 { Bad_Opcode },
5190 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_95) },
5191 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_96) },
5192 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_97) },
5193 /* 98 */
5194 { Bad_Opcode },
5195 { Bad_Opcode },
5196 { Bad_Opcode },
5197 { Bad_Opcode },
5198 { Bad_Opcode },
5199 { Bad_Opcode },
5200 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9E) },
5201 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9F) },
5202 /* a0 */
5203 { Bad_Opcode },
5204 { Bad_Opcode },
5205 { "vpcmov", { XM, Vex, EXx, XMVexI4 }, 0 },
5206 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A3) },
5207 { Bad_Opcode },
5208 { Bad_Opcode },
5209 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A6) },
5210 { Bad_Opcode },
5211 /* a8 */
5212 { Bad_Opcode },
5213 { Bad_Opcode },
5214 { Bad_Opcode },
5215 { Bad_Opcode },
5216 { Bad_Opcode },
5217 { Bad_Opcode },
5218 { Bad_Opcode },
5219 { Bad_Opcode },
5220 /* b0 */
5221 { Bad_Opcode },
5222 { Bad_Opcode },
5223 { Bad_Opcode },
5224 { Bad_Opcode },
5225 { Bad_Opcode },
5226 { Bad_Opcode },
5227 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_B6) },
5228 { Bad_Opcode },
5229 /* b8 */
5230 { Bad_Opcode },
5231 { Bad_Opcode },
5232 { Bad_Opcode },
5233 { Bad_Opcode },
5234 { Bad_Opcode },
5235 { Bad_Opcode },
5236 { Bad_Opcode },
5237 { Bad_Opcode },
5238 /* c0 */
5239 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C0) },
5240 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C1) },
5241 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C2) },
5242 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C3) },
5243 { Bad_Opcode },
5244 { Bad_Opcode },
5245 { Bad_Opcode },
5246 { Bad_Opcode },
5247 /* c8 */
5248 { Bad_Opcode },
5249 { Bad_Opcode },
5250 { Bad_Opcode },
5251 { Bad_Opcode },
5252 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
5253 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
5254 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
5255 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
5256 /* d0 */
5257 { Bad_Opcode },
5258 { Bad_Opcode },
5259 { Bad_Opcode },
5260 { Bad_Opcode },
5261 { Bad_Opcode },
5262 { Bad_Opcode },
5263 { Bad_Opcode },
5264 { Bad_Opcode },
5265 /* d8 */
5266 { Bad_Opcode },
5267 { Bad_Opcode },
5268 { Bad_Opcode },
5269 { Bad_Opcode },
5270 { Bad_Opcode },
5271 { Bad_Opcode },
5272 { Bad_Opcode },
5273 { Bad_Opcode },
5274 /* e0 */
5275 { Bad_Opcode },
5276 { Bad_Opcode },
5277 { Bad_Opcode },
5278 { Bad_Opcode },
5279 { Bad_Opcode },
5280 { Bad_Opcode },
5281 { Bad_Opcode },
5282 { Bad_Opcode },
5283 /* e8 */
5284 { Bad_Opcode },
5285 { Bad_Opcode },
5286 { Bad_Opcode },
5287 { Bad_Opcode },
5288 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
5289 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
5290 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
5291 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
5292 /* f0 */
5293 { Bad_Opcode },
5294 { Bad_Opcode },
5295 { Bad_Opcode },
5296 { Bad_Opcode },
5297 { Bad_Opcode },
5298 { Bad_Opcode },
5299 { Bad_Opcode },
5300 { Bad_Opcode },
5301 /* f8 */
5302 { Bad_Opcode },
5303 { Bad_Opcode },
5304 { Bad_Opcode },
5305 { Bad_Opcode },
5306 { Bad_Opcode },
5307 { Bad_Opcode },
5308 { Bad_Opcode },
5309 { Bad_Opcode },
5310 },
5311 /* XOP_09 */
5312 {
5313 /* 00 */
5314 { Bad_Opcode },
5315 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_01) },
5316 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_02) },
5317 { Bad_Opcode },
5318 { Bad_Opcode },
5319 { Bad_Opcode },
5320 { Bad_Opcode },
5321 { Bad_Opcode },
5322 /* 08 */
5323 { Bad_Opcode },
5324 { Bad_Opcode },
5325 { Bad_Opcode },
5326 { Bad_Opcode },
5327 { Bad_Opcode },
5328 { Bad_Opcode },
5329 { Bad_Opcode },
5330 { Bad_Opcode },
5331 /* 10 */
5332 { Bad_Opcode },
5333 { Bad_Opcode },
5334 { MOD_TABLE (MOD_VEX_0FXOP_09_12) },
5335 { Bad_Opcode },
5336 { Bad_Opcode },
5337 { Bad_Opcode },
5338 { Bad_Opcode },
5339 { Bad_Opcode },
5340 /* 18 */
5341 { Bad_Opcode },
5342 { Bad_Opcode },
5343 { Bad_Opcode },
5344 { Bad_Opcode },
5345 { Bad_Opcode },
5346 { Bad_Opcode },
5347 { Bad_Opcode },
5348 { Bad_Opcode },
5349 /* 20 */
5350 { Bad_Opcode },
5351 { Bad_Opcode },
5352 { Bad_Opcode },
5353 { Bad_Opcode },
5354 { Bad_Opcode },
5355 { Bad_Opcode },
5356 { Bad_Opcode },
5357 { Bad_Opcode },
5358 /* 28 */
5359 { Bad_Opcode },
5360 { Bad_Opcode },
5361 { Bad_Opcode },
5362 { Bad_Opcode },
5363 { Bad_Opcode },
5364 { Bad_Opcode },
5365 { Bad_Opcode },
5366 { Bad_Opcode },
5367 /* 30 */
5368 { Bad_Opcode },
5369 { Bad_Opcode },
5370 { Bad_Opcode },
5371 { Bad_Opcode },
5372 { Bad_Opcode },
5373 { Bad_Opcode },
5374 { Bad_Opcode },
5375 { Bad_Opcode },
5376 /* 38 */
5377 { Bad_Opcode },
5378 { Bad_Opcode },
5379 { Bad_Opcode },
5380 { Bad_Opcode },
5381 { Bad_Opcode },
5382 { Bad_Opcode },
5383 { Bad_Opcode },
5384 { Bad_Opcode },
5385 /* 40 */
5386 { Bad_Opcode },
5387 { Bad_Opcode },
5388 { Bad_Opcode },
5389 { Bad_Opcode },
5390 { Bad_Opcode },
5391 { Bad_Opcode },
5392 { Bad_Opcode },
5393 { Bad_Opcode },
5394 /* 48 */
5395 { Bad_Opcode },
5396 { Bad_Opcode },
5397 { Bad_Opcode },
5398 { Bad_Opcode },
5399 { Bad_Opcode },
5400 { Bad_Opcode },
5401 { Bad_Opcode },
5402 { Bad_Opcode },
5403 /* 50 */
5404 { Bad_Opcode },
5405 { Bad_Opcode },
5406 { Bad_Opcode },
5407 { Bad_Opcode },
5408 { Bad_Opcode },
5409 { Bad_Opcode },
5410 { Bad_Opcode },
5411 { Bad_Opcode },
5412 /* 58 */
5413 { Bad_Opcode },
5414 { Bad_Opcode },
5415 { Bad_Opcode },
5416 { Bad_Opcode },
5417 { Bad_Opcode },
5418 { Bad_Opcode },
5419 { Bad_Opcode },
5420 { Bad_Opcode },
5421 /* 60 */
5422 { Bad_Opcode },
5423 { Bad_Opcode },
5424 { Bad_Opcode },
5425 { Bad_Opcode },
5426 { Bad_Opcode },
5427 { Bad_Opcode },
5428 { Bad_Opcode },
5429 { Bad_Opcode },
5430 /* 68 */
5431 { Bad_Opcode },
5432 { Bad_Opcode },
5433 { Bad_Opcode },
5434 { Bad_Opcode },
5435 { Bad_Opcode },
5436 { Bad_Opcode },
5437 { Bad_Opcode },
5438 { Bad_Opcode },
5439 /* 70 */
5440 { Bad_Opcode },
5441 { Bad_Opcode },
5442 { Bad_Opcode },
5443 { Bad_Opcode },
5444 { Bad_Opcode },
5445 { Bad_Opcode },
5446 { Bad_Opcode },
5447 { Bad_Opcode },
5448 /* 78 */
5449 { Bad_Opcode },
5450 { Bad_Opcode },
5451 { Bad_Opcode },
5452 { Bad_Opcode },
5453 { Bad_Opcode },
5454 { Bad_Opcode },
5455 { Bad_Opcode },
5456 { Bad_Opcode },
5457 /* 80 */
5458 { VEX_W_TABLE (VEX_W_0FXOP_09_80) },
5459 { VEX_W_TABLE (VEX_W_0FXOP_09_81) },
5460 { VEX_W_TABLE (VEX_W_0FXOP_09_82) },
5461 { VEX_W_TABLE (VEX_W_0FXOP_09_83) },
5462 { Bad_Opcode },
5463 { Bad_Opcode },
5464 { Bad_Opcode },
5465 { Bad_Opcode },
5466 /* 88 */
5467 { Bad_Opcode },
5468 { Bad_Opcode },
5469 { Bad_Opcode },
5470 { Bad_Opcode },
5471 { Bad_Opcode },
5472 { Bad_Opcode },
5473 { Bad_Opcode },
5474 { Bad_Opcode },
5475 /* 90 */
5476 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_90) },
5477 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_91) },
5478 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_92) },
5479 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_93) },
5480 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_94) },
5481 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_95) },
5482 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_96) },
5483 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_97) },
5484 /* 98 */
5485 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_98) },
5486 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_99) },
5487 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9A) },
5488 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9B) },
5489 { Bad_Opcode },
5490 { Bad_Opcode },
5491 { Bad_Opcode },
5492 { Bad_Opcode },
5493 /* a0 */
5494 { Bad_Opcode },
5495 { Bad_Opcode },
5496 { Bad_Opcode },
5497 { Bad_Opcode },
5498 { Bad_Opcode },
5499 { Bad_Opcode },
5500 { Bad_Opcode },
5501 { Bad_Opcode },
5502 /* a8 */
5503 { Bad_Opcode },
5504 { Bad_Opcode },
5505 { Bad_Opcode },
5506 { Bad_Opcode },
5507 { Bad_Opcode },
5508 { Bad_Opcode },
5509 { Bad_Opcode },
5510 { Bad_Opcode },
5511 /* b0 */
5512 { Bad_Opcode },
5513 { Bad_Opcode },
5514 { Bad_Opcode },
5515 { Bad_Opcode },
5516 { Bad_Opcode },
5517 { Bad_Opcode },
5518 { Bad_Opcode },
5519 { Bad_Opcode },
5520 /* b8 */
5521 { Bad_Opcode },
5522 { Bad_Opcode },
5523 { Bad_Opcode },
5524 { Bad_Opcode },
5525 { Bad_Opcode },
5526 { Bad_Opcode },
5527 { Bad_Opcode },
5528 { Bad_Opcode },
5529 /* c0 */
5530 { Bad_Opcode },
5531 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C1) },
5532 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C2) },
5533 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C3) },
5534 { Bad_Opcode },
5535 { Bad_Opcode },
5536 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C6) },
5537 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C7) },
5538 /* c8 */
5539 { Bad_Opcode },
5540 { Bad_Opcode },
5541 { Bad_Opcode },
5542 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_CB) },
5543 { Bad_Opcode },
5544 { Bad_Opcode },
5545 { Bad_Opcode },
5546 { Bad_Opcode },
5547 /* d0 */
5548 { Bad_Opcode },
5549 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D1) },
5550 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D2) },
5551 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D3) },
5552 { Bad_Opcode },
5553 { Bad_Opcode },
5554 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D6) },
5555 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D7) },
5556 /* d8 */
5557 { Bad_Opcode },
5558 { Bad_Opcode },
5559 { Bad_Opcode },
5560 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_DB) },
5561 { Bad_Opcode },
5562 { Bad_Opcode },
5563 { Bad_Opcode },
5564 { Bad_Opcode },
5565 /* e0 */
5566 { Bad_Opcode },
5567 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E1) },
5568 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E2) },
5569 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E3) },
5570 { Bad_Opcode },
5571 { Bad_Opcode },
5572 { Bad_Opcode },
5573 { Bad_Opcode },
5574 /* e8 */
5575 { Bad_Opcode },
5576 { Bad_Opcode },
5577 { Bad_Opcode },
5578 { Bad_Opcode },
5579 { Bad_Opcode },
5580 { Bad_Opcode },
5581 { Bad_Opcode },
5582 { Bad_Opcode },
5583 /* f0 */
5584 { Bad_Opcode },
5585 { Bad_Opcode },
5586 { Bad_Opcode },
5587 { Bad_Opcode },
5588 { Bad_Opcode },
5589 { Bad_Opcode },
5590 { Bad_Opcode },
5591 { Bad_Opcode },
5592 /* f8 */
5593 { Bad_Opcode },
5594 { Bad_Opcode },
5595 { Bad_Opcode },
5596 { Bad_Opcode },
5597 { Bad_Opcode },
5598 { Bad_Opcode },
5599 { Bad_Opcode },
5600 { Bad_Opcode },
5601 },
5602 /* XOP_0A */
5603 {
5604 /* 00 */
5605 { Bad_Opcode },
5606 { Bad_Opcode },
5607 { Bad_Opcode },
5608 { Bad_Opcode },
5609 { Bad_Opcode },
5610 { Bad_Opcode },
5611 { Bad_Opcode },
5612 { Bad_Opcode },
5613 /* 08 */
5614 { Bad_Opcode },
5615 { Bad_Opcode },
5616 { Bad_Opcode },
5617 { Bad_Opcode },
5618 { Bad_Opcode },
5619 { Bad_Opcode },
5620 { Bad_Opcode },
5621 { Bad_Opcode },
5622 /* 10 */
5623 { "bextrS", { Gdq, Edq, Id }, 0 },
5624 { Bad_Opcode },
5625 { VEX_LEN_TABLE (VEX_LEN_0FXOP_0A_12) },
5626 { Bad_Opcode },
5627 { Bad_Opcode },
5628 { Bad_Opcode },
5629 { Bad_Opcode },
5630 { Bad_Opcode },
5631 /* 18 */
5632 { Bad_Opcode },
5633 { Bad_Opcode },
5634 { Bad_Opcode },
5635 { Bad_Opcode },
5636 { Bad_Opcode },
5637 { Bad_Opcode },
5638 { Bad_Opcode },
5639 { Bad_Opcode },
5640 /* 20 */
5641 { Bad_Opcode },
5642 { Bad_Opcode },
5643 { Bad_Opcode },
5644 { Bad_Opcode },
5645 { Bad_Opcode },
5646 { Bad_Opcode },
5647 { Bad_Opcode },
5648 { Bad_Opcode },
5649 /* 28 */
5650 { Bad_Opcode },
5651 { Bad_Opcode },
5652 { Bad_Opcode },
5653 { Bad_Opcode },
5654 { Bad_Opcode },
5655 { Bad_Opcode },
5656 { Bad_Opcode },
5657 { Bad_Opcode },
5658 /* 30 */
5659 { Bad_Opcode },
5660 { Bad_Opcode },
5661 { Bad_Opcode },
5662 { Bad_Opcode },
5663 { Bad_Opcode },
5664 { Bad_Opcode },
5665 { Bad_Opcode },
5666 { Bad_Opcode },
5667 /* 38 */
5668 { Bad_Opcode },
5669 { Bad_Opcode },
5670 { Bad_Opcode },
5671 { Bad_Opcode },
5672 { Bad_Opcode },
5673 { Bad_Opcode },
5674 { Bad_Opcode },
5675 { Bad_Opcode },
5676 /* 40 */
5677 { Bad_Opcode },
5678 { Bad_Opcode },
5679 { Bad_Opcode },
5680 { Bad_Opcode },
5681 { Bad_Opcode },
5682 { Bad_Opcode },
5683 { Bad_Opcode },
5684 { Bad_Opcode },
5685 /* 48 */
5686 { Bad_Opcode },
5687 { Bad_Opcode },
5688 { Bad_Opcode },
5689 { Bad_Opcode },
5690 { Bad_Opcode },
5691 { Bad_Opcode },
5692 { Bad_Opcode },
5693 { Bad_Opcode },
5694 /* 50 */
5695 { Bad_Opcode },
5696 { Bad_Opcode },
5697 { Bad_Opcode },
5698 { Bad_Opcode },
5699 { Bad_Opcode },
5700 { Bad_Opcode },
5701 { Bad_Opcode },
5702 { Bad_Opcode },
5703 /* 58 */
5704 { Bad_Opcode },
5705 { Bad_Opcode },
5706 { Bad_Opcode },
5707 { Bad_Opcode },
5708 { Bad_Opcode },
5709 { Bad_Opcode },
5710 { Bad_Opcode },
5711 { Bad_Opcode },
5712 /* 60 */
5713 { Bad_Opcode },
5714 { Bad_Opcode },
5715 { Bad_Opcode },
5716 { Bad_Opcode },
5717 { Bad_Opcode },
5718 { Bad_Opcode },
5719 { Bad_Opcode },
5720 { Bad_Opcode },
5721 /* 68 */
5722 { Bad_Opcode },
5723 { Bad_Opcode },
5724 { Bad_Opcode },
5725 { Bad_Opcode },
5726 { Bad_Opcode },
5727 { Bad_Opcode },
5728 { Bad_Opcode },
5729 { Bad_Opcode },
5730 /* 70 */
5731 { Bad_Opcode },
5732 { Bad_Opcode },
5733 { Bad_Opcode },
5734 { Bad_Opcode },
5735 { Bad_Opcode },
5736 { Bad_Opcode },
5737 { Bad_Opcode },
5738 { Bad_Opcode },
5739 /* 78 */
5740 { Bad_Opcode },
5741 { Bad_Opcode },
5742 { Bad_Opcode },
5743 { Bad_Opcode },
5744 { Bad_Opcode },
5745 { Bad_Opcode },
5746 { Bad_Opcode },
5747 { Bad_Opcode },
5748 /* 80 */
5749 { Bad_Opcode },
5750 { Bad_Opcode },
5751 { Bad_Opcode },
5752 { Bad_Opcode },
5753 { Bad_Opcode },
5754 { Bad_Opcode },
5755 { Bad_Opcode },
5756 { Bad_Opcode },
5757 /* 88 */
5758 { Bad_Opcode },
5759 { Bad_Opcode },
5760 { Bad_Opcode },
5761 { Bad_Opcode },
5762 { Bad_Opcode },
5763 { Bad_Opcode },
5764 { Bad_Opcode },
5765 { Bad_Opcode },
5766 /* 90 */
5767 { Bad_Opcode },
5768 { Bad_Opcode },
5769 { Bad_Opcode },
5770 { Bad_Opcode },
5771 { Bad_Opcode },
5772 { Bad_Opcode },
5773 { Bad_Opcode },
5774 { Bad_Opcode },
5775 /* 98 */
5776 { Bad_Opcode },
5777 { Bad_Opcode },
5778 { Bad_Opcode },
5779 { Bad_Opcode },
5780 { Bad_Opcode },
5781 { Bad_Opcode },
5782 { Bad_Opcode },
5783 { Bad_Opcode },
5784 /* a0 */
5785 { Bad_Opcode },
5786 { Bad_Opcode },
5787 { Bad_Opcode },
5788 { Bad_Opcode },
5789 { Bad_Opcode },
5790 { Bad_Opcode },
5791 { Bad_Opcode },
5792 { Bad_Opcode },
5793 /* a8 */
5794 { Bad_Opcode },
5795 { Bad_Opcode },
5796 { Bad_Opcode },
5797 { Bad_Opcode },
5798 { Bad_Opcode },
5799 { Bad_Opcode },
5800 { Bad_Opcode },
5801 { Bad_Opcode },
5802 /* b0 */
5803 { Bad_Opcode },
5804 { Bad_Opcode },
5805 { Bad_Opcode },
5806 { Bad_Opcode },
5807 { Bad_Opcode },
5808 { Bad_Opcode },
5809 { Bad_Opcode },
5810 { Bad_Opcode },
5811 /* b8 */
5812 { Bad_Opcode },
5813 { Bad_Opcode },
5814 { Bad_Opcode },
5815 { Bad_Opcode },
5816 { Bad_Opcode },
5817 { Bad_Opcode },
5818 { Bad_Opcode },
5819 { Bad_Opcode },
5820 /* c0 */
5821 { Bad_Opcode },
5822 { Bad_Opcode },
5823 { Bad_Opcode },
5824 { Bad_Opcode },
5825 { Bad_Opcode },
5826 { Bad_Opcode },
5827 { Bad_Opcode },
5828 { Bad_Opcode },
5829 /* c8 */
5830 { Bad_Opcode },
5831 { Bad_Opcode },
5832 { Bad_Opcode },
5833 { Bad_Opcode },
5834 { Bad_Opcode },
5835 { Bad_Opcode },
5836 { Bad_Opcode },
5837 { Bad_Opcode },
5838 /* d0 */
5839 { Bad_Opcode },
5840 { Bad_Opcode },
5841 { Bad_Opcode },
5842 { Bad_Opcode },
5843 { Bad_Opcode },
5844 { Bad_Opcode },
5845 { Bad_Opcode },
5846 { Bad_Opcode },
5847 /* d8 */
5848 { Bad_Opcode },
5849 { Bad_Opcode },
5850 { Bad_Opcode },
5851 { Bad_Opcode },
5852 { Bad_Opcode },
5853 { Bad_Opcode },
5854 { Bad_Opcode },
5855 { Bad_Opcode },
5856 /* e0 */
5857 { Bad_Opcode },
5858 { Bad_Opcode },
5859 { Bad_Opcode },
5860 { Bad_Opcode },
5861 { Bad_Opcode },
5862 { Bad_Opcode },
5863 { Bad_Opcode },
5864 { Bad_Opcode },
5865 /* e8 */
5866 { Bad_Opcode },
5867 { Bad_Opcode },
5868 { Bad_Opcode },
5869 { Bad_Opcode },
5870 { Bad_Opcode },
5871 { Bad_Opcode },
5872 { Bad_Opcode },
5873 { Bad_Opcode },
5874 /* f0 */
5875 { Bad_Opcode },
5876 { Bad_Opcode },
5877 { Bad_Opcode },
5878 { Bad_Opcode },
5879 { Bad_Opcode },
5880 { Bad_Opcode },
5881 { Bad_Opcode },
5882 { Bad_Opcode },
5883 /* f8 */
5884 { Bad_Opcode },
5885 { Bad_Opcode },
5886 { Bad_Opcode },
5887 { Bad_Opcode },
5888 { Bad_Opcode },
5889 { Bad_Opcode },
5890 { Bad_Opcode },
5891 { Bad_Opcode },
5892 },
5893 };
5894
5895 static const struct dis386 vex_table[][256] = {
5896 /* VEX_0F */
5897 {
5898 /* 00 */
5899 { Bad_Opcode },
5900 { Bad_Opcode },
5901 { Bad_Opcode },
5902 { Bad_Opcode },
5903 { Bad_Opcode },
5904 { Bad_Opcode },
5905 { Bad_Opcode },
5906 { Bad_Opcode },
5907 /* 08 */
5908 { Bad_Opcode },
5909 { Bad_Opcode },
5910 { Bad_Opcode },
5911 { Bad_Opcode },
5912 { Bad_Opcode },
5913 { Bad_Opcode },
5914 { Bad_Opcode },
5915 { Bad_Opcode },
5916 /* 10 */
5917 { PREFIX_TABLE (PREFIX_VEX_0F10) },
5918 { PREFIX_TABLE (PREFIX_VEX_0F11) },
5919 { PREFIX_TABLE (PREFIX_VEX_0F12) },
5920 { MOD_TABLE (MOD_VEX_0F13) },
5921 { "vunpcklpX", { XM, Vex, EXx }, PREFIX_OPCODE },
5922 { "vunpckhpX", { XM, Vex, EXx }, PREFIX_OPCODE },
5923 { PREFIX_TABLE (PREFIX_VEX_0F16) },
5924 { MOD_TABLE (MOD_VEX_0F17) },
5925 /* 18 */
5926 { Bad_Opcode },
5927 { Bad_Opcode },
5928 { Bad_Opcode },
5929 { Bad_Opcode },
5930 { Bad_Opcode },
5931 { Bad_Opcode },
5932 { Bad_Opcode },
5933 { Bad_Opcode },
5934 /* 20 */
5935 { Bad_Opcode },
5936 { Bad_Opcode },
5937 { Bad_Opcode },
5938 { Bad_Opcode },
5939 { Bad_Opcode },
5940 { Bad_Opcode },
5941 { Bad_Opcode },
5942 { Bad_Opcode },
5943 /* 28 */
5944 { "vmovapX", { XM, EXx }, PREFIX_OPCODE },
5945 { "vmovapX", { EXxS, XM }, PREFIX_OPCODE },
5946 { PREFIX_TABLE (PREFIX_VEX_0F2A) },
5947 { MOD_TABLE (MOD_VEX_0F2B) },
5948 { PREFIX_TABLE (PREFIX_VEX_0F2C) },
5949 { PREFIX_TABLE (PREFIX_VEX_0F2D) },
5950 { PREFIX_TABLE (PREFIX_VEX_0F2E) },
5951 { PREFIX_TABLE (PREFIX_VEX_0F2F) },
5952 /* 30 */
5953 { Bad_Opcode },
5954 { Bad_Opcode },
5955 { Bad_Opcode },
5956 { Bad_Opcode },
5957 { Bad_Opcode },
5958 { Bad_Opcode },
5959 { Bad_Opcode },
5960 { Bad_Opcode },
5961 /* 38 */
5962 { Bad_Opcode },
5963 { Bad_Opcode },
5964 { Bad_Opcode },
5965 { Bad_Opcode },
5966 { Bad_Opcode },
5967 { Bad_Opcode },
5968 { Bad_Opcode },
5969 { Bad_Opcode },
5970 /* 40 */
5971 { Bad_Opcode },
5972 { PREFIX_TABLE (PREFIX_VEX_0F41) },
5973 { PREFIX_TABLE (PREFIX_VEX_0F42) },
5974 { Bad_Opcode },
5975 { PREFIX_TABLE (PREFIX_VEX_0F44) },
5976 { PREFIX_TABLE (PREFIX_VEX_0F45) },
5977 { PREFIX_TABLE (PREFIX_VEX_0F46) },
5978 { PREFIX_TABLE (PREFIX_VEX_0F47) },
5979 /* 48 */
5980 { Bad_Opcode },
5981 { Bad_Opcode },
5982 { PREFIX_TABLE (PREFIX_VEX_0F4A) },
5983 { PREFIX_TABLE (PREFIX_VEX_0F4B) },
5984 { Bad_Opcode },
5985 { Bad_Opcode },
5986 { Bad_Opcode },
5987 { Bad_Opcode },
5988 /* 50 */
5989 { MOD_TABLE (MOD_VEX_0F50) },
5990 { PREFIX_TABLE (PREFIX_VEX_0F51) },
5991 { PREFIX_TABLE (PREFIX_VEX_0F52) },
5992 { PREFIX_TABLE (PREFIX_VEX_0F53) },
5993 { "vandpX", { XM, Vex, EXx }, PREFIX_OPCODE },
5994 { "vandnpX", { XM, Vex, EXx }, PREFIX_OPCODE },
5995 { "vorpX", { XM, Vex, EXx }, PREFIX_OPCODE },
5996 { "vxorpX", { XM, Vex, EXx }, PREFIX_OPCODE },
5997 /* 58 */
5998 { PREFIX_TABLE (PREFIX_VEX_0F58) },
5999 { PREFIX_TABLE (PREFIX_VEX_0F59) },
6000 { PREFIX_TABLE (PREFIX_VEX_0F5A) },
6001 { PREFIX_TABLE (PREFIX_VEX_0F5B) },
6002 { PREFIX_TABLE (PREFIX_VEX_0F5C) },
6003 { PREFIX_TABLE (PREFIX_VEX_0F5D) },
6004 { PREFIX_TABLE (PREFIX_VEX_0F5E) },
6005 { PREFIX_TABLE (PREFIX_VEX_0F5F) },
6006 /* 60 */
6007 { "vpunpcklbw", { XM, Vex, EXx }, PREFIX_DATA },
6008 { "vpunpcklwd", { XM, Vex, EXx }, PREFIX_DATA },
6009 { "vpunpckldq", { XM, Vex, EXx }, PREFIX_DATA },
6010 { "vpacksswb", { XM, Vex, EXx }, PREFIX_DATA },
6011 { "vpcmpgtb", { XM, Vex, EXx }, PREFIX_DATA },
6012 { "vpcmpgtw", { XM, Vex, EXx }, PREFIX_DATA },
6013 { "vpcmpgtd", { XM, Vex, EXx }, PREFIX_DATA },
6014 { "vpackuswb", { XM, Vex, EXx }, PREFIX_DATA },
6015 /* 68 */
6016 { "vpunpckhbw", { XM, Vex, EXx }, PREFIX_DATA },
6017 { "vpunpckhwd", { XM, Vex, EXx }, PREFIX_DATA },
6018 { "vpunpckhdq", { XM, Vex, EXx }, PREFIX_DATA },
6019 { "vpackssdw", { XM, Vex, EXx }, PREFIX_DATA },
6020 { "vpunpcklqdq", { XM, Vex, EXx }, PREFIX_DATA },
6021 { "vpunpckhqdq", { XM, Vex, EXx }, PREFIX_DATA },
6022 { VEX_LEN_TABLE (VEX_LEN_0F6E) },
6023 { PREFIX_TABLE (PREFIX_VEX_0F6F) },
6024 /* 70 */
6025 { PREFIX_TABLE (PREFIX_VEX_0F70) },
6026 { REG_TABLE (REG_VEX_0F71) },
6027 { REG_TABLE (REG_VEX_0F72) },
6028 { REG_TABLE (REG_VEX_0F73) },
6029 { "vpcmpeqb", { XM, Vex, EXx }, PREFIX_DATA },
6030 { "vpcmpeqw", { XM, Vex, EXx }, PREFIX_DATA },
6031 { "vpcmpeqd", { XM, Vex, EXx }, PREFIX_DATA },
6032 { VEX_LEN_TABLE (VEX_LEN_0F77) },
6033 /* 78 */
6034 { Bad_Opcode },
6035 { Bad_Opcode },
6036 { Bad_Opcode },
6037 { Bad_Opcode },
6038 { PREFIX_TABLE (PREFIX_VEX_0F7C) },
6039 { PREFIX_TABLE (PREFIX_VEX_0F7D) },
6040 { PREFIX_TABLE (PREFIX_VEX_0F7E) },
6041 { PREFIX_TABLE (PREFIX_VEX_0F7F) },
6042 /* 80 */
6043 { Bad_Opcode },
6044 { Bad_Opcode },
6045 { Bad_Opcode },
6046 { Bad_Opcode },
6047 { Bad_Opcode },
6048 { Bad_Opcode },
6049 { Bad_Opcode },
6050 { Bad_Opcode },
6051 /* 88 */
6052 { Bad_Opcode },
6053 { Bad_Opcode },
6054 { Bad_Opcode },
6055 { Bad_Opcode },
6056 { Bad_Opcode },
6057 { Bad_Opcode },
6058 { Bad_Opcode },
6059 { Bad_Opcode },
6060 /* 90 */
6061 { PREFIX_TABLE (PREFIX_VEX_0F90) },
6062 { PREFIX_TABLE (PREFIX_VEX_0F91) },
6063 { PREFIX_TABLE (PREFIX_VEX_0F92) },
6064 { PREFIX_TABLE (PREFIX_VEX_0F93) },
6065 { Bad_Opcode },
6066 { Bad_Opcode },
6067 { Bad_Opcode },
6068 { Bad_Opcode },
6069 /* 98 */
6070 { PREFIX_TABLE (PREFIX_VEX_0F98) },
6071 { PREFIX_TABLE (PREFIX_VEX_0F99) },
6072 { Bad_Opcode },
6073 { Bad_Opcode },
6074 { Bad_Opcode },
6075 { Bad_Opcode },
6076 { Bad_Opcode },
6077 { Bad_Opcode },
6078 /* a0 */
6079 { Bad_Opcode },
6080 { Bad_Opcode },
6081 { Bad_Opcode },
6082 { Bad_Opcode },
6083 { Bad_Opcode },
6084 { Bad_Opcode },
6085 { Bad_Opcode },
6086 { Bad_Opcode },
6087 /* a8 */
6088 { Bad_Opcode },
6089 { Bad_Opcode },
6090 { Bad_Opcode },
6091 { Bad_Opcode },
6092 { Bad_Opcode },
6093 { Bad_Opcode },
6094 { REG_TABLE (REG_VEX_0FAE) },
6095 { Bad_Opcode },
6096 /* b0 */
6097 { Bad_Opcode },
6098 { Bad_Opcode },
6099 { Bad_Opcode },
6100 { Bad_Opcode },
6101 { Bad_Opcode },
6102 { Bad_Opcode },
6103 { Bad_Opcode },
6104 { Bad_Opcode },
6105 /* b8 */
6106 { Bad_Opcode },
6107 { Bad_Opcode },
6108 { Bad_Opcode },
6109 { Bad_Opcode },
6110 { Bad_Opcode },
6111 { Bad_Opcode },
6112 { Bad_Opcode },
6113 { Bad_Opcode },
6114 /* c0 */
6115 { Bad_Opcode },
6116 { Bad_Opcode },
6117 { PREFIX_TABLE (PREFIX_VEX_0FC2) },
6118 { Bad_Opcode },
6119 { VEX_LEN_TABLE (VEX_LEN_0FC4) },
6120 { VEX_LEN_TABLE (VEX_LEN_0FC5) },
6121 { "vshufpX", { XM, Vex, EXx, Ib }, PREFIX_OPCODE },
6122 { Bad_Opcode },
6123 /* c8 */
6124 { Bad_Opcode },
6125 { Bad_Opcode },
6126 { Bad_Opcode },
6127 { Bad_Opcode },
6128 { Bad_Opcode },
6129 { Bad_Opcode },
6130 { Bad_Opcode },
6131 { Bad_Opcode },
6132 /* d0 */
6133 { PREFIX_TABLE (PREFIX_VEX_0FD0) },
6134 { "vpsrlw", { XM, Vex, EXxmm }, PREFIX_DATA },
6135 { "vpsrld", { XM, Vex, EXxmm }, PREFIX_DATA },
6136 { "vpsrlq", { XM, Vex, EXxmm }, PREFIX_DATA },
6137 { "vpaddq", { XM, Vex, EXx }, PREFIX_DATA },
6138 { "vpmullw", { XM, Vex, EXx }, PREFIX_DATA },
6139 { VEX_LEN_TABLE (VEX_LEN_0FD6) },
6140 { MOD_TABLE (MOD_VEX_0FD7) },
6141 /* d8 */
6142 { "vpsubusb", { XM, Vex, EXx }, PREFIX_DATA },
6143 { "vpsubusw", { XM, Vex, EXx }, PREFIX_DATA },
6144 { "vpminub", { XM, Vex, EXx }, PREFIX_DATA },
6145 { "vpand", { XM, Vex, EXx }, PREFIX_DATA },
6146 { "vpaddusb", { XM, Vex, EXx }, PREFIX_DATA },
6147 { "vpaddusw", { XM, Vex, EXx }, PREFIX_DATA },
6148 { "vpmaxub", { XM, Vex, EXx }, PREFIX_DATA },
6149 { "vpandn", { XM, Vex, EXx }, PREFIX_DATA },
6150 /* e0 */
6151 { "vpavgb", { XM, Vex, EXx }, PREFIX_DATA },
6152 { "vpsraw", { XM, Vex, EXxmm }, PREFIX_DATA },
6153 { "vpsrad", { XM, Vex, EXxmm }, PREFIX_DATA },
6154 { "vpavgw", { XM, Vex, EXx }, PREFIX_DATA },
6155 { "vpmulhuw", { XM, Vex, EXx }, PREFIX_DATA },
6156 { "vpmulhw", { XM, Vex, EXx }, PREFIX_DATA },
6157 { PREFIX_TABLE (PREFIX_VEX_0FE6) },
6158 { MOD_TABLE (MOD_VEX_0FE7) },
6159 /* e8 */
6160 { "vpsubsb", { XM, Vex, EXx }, PREFIX_DATA },
6161 { "vpsubsw", { XM, Vex, EXx }, PREFIX_DATA },
6162 { "vpminsw", { XM, Vex, EXx }, PREFIX_DATA },
6163 { "vpor", { XM, Vex, EXx }, PREFIX_DATA },
6164 { "vpaddsb", { XM, Vex, EXx }, PREFIX_DATA },
6165 { "vpaddsw", { XM, Vex, EXx }, PREFIX_DATA },
6166 { "vpmaxsw", { XM, Vex, EXx }, PREFIX_DATA },
6167 { "vpxor", { XM, Vex, EXx }, PREFIX_DATA },
6168 /* f0 */
6169 { PREFIX_TABLE (PREFIX_VEX_0FF0) },
6170 { "vpsllw", { XM, Vex, EXxmm }, PREFIX_DATA },
6171 { "vpslld", { XM, Vex, EXxmm }, PREFIX_DATA },
6172 { "vpsllq", { XM, Vex, EXxmm }, PREFIX_DATA },
6173 { "vpmuludq", { XM, Vex, EXx }, PREFIX_DATA },
6174 { "vpmaddwd", { XM, Vex, EXx }, PREFIX_DATA },
6175 { "vpsadbw", { XM, Vex, EXx }, PREFIX_DATA },
6176 { VEX_LEN_TABLE (VEX_LEN_0FF7) },
6177 /* f8 */
6178 { "vpsubb", { XM, Vex, EXx }, PREFIX_DATA },
6179 { "vpsubw", { XM, Vex, EXx }, PREFIX_DATA },
6180 { "vpsubd", { XM, Vex, EXx }, PREFIX_DATA },
6181 { "vpsubq", { XM, Vex, EXx }, PREFIX_DATA },
6182 { "vpaddb", { XM, Vex, EXx }, PREFIX_DATA },
6183 { "vpaddw", { XM, Vex, EXx }, PREFIX_DATA },
6184 { "vpaddd", { XM, Vex, EXx }, PREFIX_DATA },
6185 { Bad_Opcode },
6186 },
6187 /* VEX_0F38 */
6188 {
6189 /* 00 */
6190 { "vpshufb", { XM, Vex, EXx }, PREFIX_DATA },
6191 { "vphaddw", { XM, Vex, EXx }, PREFIX_DATA },
6192 { "vphaddd", { XM, Vex, EXx }, PREFIX_DATA },
6193 { "vphaddsw", { XM, Vex, EXx }, PREFIX_DATA },
6194 { "vpmaddubsw", { XM, Vex, EXx }, PREFIX_DATA },
6195 { "vphsubw", { XM, Vex, EXx }, PREFIX_DATA },
6196 { "vphsubd", { XM, Vex, EXx }, PREFIX_DATA },
6197 { "vphsubsw", { XM, Vex, EXx }, PREFIX_DATA },
6198 /* 08 */
6199 { "vpsignb", { XM, Vex, EXx }, PREFIX_DATA },
6200 { "vpsignw", { XM, Vex, EXx }, PREFIX_DATA },
6201 { "vpsignd", { XM, Vex, EXx }, PREFIX_DATA },
6202 { "vpmulhrsw", { XM, Vex, EXx }, PREFIX_DATA },
6203 { VEX_W_TABLE (VEX_W_0F380C) },
6204 { VEX_W_TABLE (VEX_W_0F380D) },
6205 { VEX_W_TABLE (VEX_W_0F380E) },
6206 { VEX_W_TABLE (VEX_W_0F380F) },
6207 /* 10 */
6208 { Bad_Opcode },
6209 { Bad_Opcode },
6210 { Bad_Opcode },
6211 { VEX_W_TABLE (VEX_W_0F3813) },
6212 { Bad_Opcode },
6213 { Bad_Opcode },
6214 { VEX_LEN_TABLE (VEX_LEN_0F3816) },
6215 { "vptest", { XM, EXx }, PREFIX_DATA },
6216 /* 18 */
6217 { VEX_W_TABLE (VEX_W_0F3818) },
6218 { VEX_LEN_TABLE (VEX_LEN_0F3819) },
6219 { MOD_TABLE (MOD_VEX_0F381A) },
6220 { Bad_Opcode },
6221 { "vpabsb", { XM, EXx }, PREFIX_DATA },
6222 { "vpabsw", { XM, EXx }, PREFIX_DATA },
6223 { "vpabsd", { XM, EXx }, PREFIX_DATA },
6224 { Bad_Opcode },
6225 /* 20 */
6226 { "vpmovsxbw", { XM, EXxmmq }, PREFIX_DATA },
6227 { "vpmovsxbd", { XM, EXxmmqd }, PREFIX_DATA },
6228 { "vpmovsxbq", { XM, EXxmmdw }, PREFIX_DATA },
6229 { "vpmovsxwd", { XM, EXxmmq }, PREFIX_DATA },
6230 { "vpmovsxwq", { XM, EXxmmqd }, PREFIX_DATA },
6231 { "vpmovsxdq", { XM, EXxmmq }, PREFIX_DATA },
6232 { Bad_Opcode },
6233 { Bad_Opcode },
6234 /* 28 */
6235 { "vpmuldq", { XM, Vex, EXx }, PREFIX_DATA },
6236 { "vpcmpeqq", { XM, Vex, EXx }, PREFIX_DATA },
6237 { MOD_TABLE (MOD_VEX_0F382A) },
6238 { "vpackusdw", { XM, Vex, EXx }, PREFIX_DATA },
6239 { MOD_TABLE (MOD_VEX_0F382C) },
6240 { MOD_TABLE (MOD_VEX_0F382D) },
6241 { MOD_TABLE (MOD_VEX_0F382E) },
6242 { MOD_TABLE (MOD_VEX_0F382F) },
6243 /* 30 */
6244 { "vpmovzxbw", { XM, EXxmmq }, PREFIX_DATA },
6245 { "vpmovzxbd", { XM, EXxmmqd }, PREFIX_DATA },
6246 { "vpmovzxbq", { XM, EXxmmdw }, PREFIX_DATA },
6247 { "vpmovzxwd", { XM, EXxmmq }, PREFIX_DATA },
6248 { "vpmovzxwq", { XM, EXxmmqd }, PREFIX_DATA },
6249 { "vpmovzxdq", { XM, EXxmmq }, PREFIX_DATA },
6250 { VEX_LEN_TABLE (VEX_LEN_0F3836) },
6251 { "vpcmpgtq", { XM, Vex, EXx }, PREFIX_DATA },
6252 /* 38 */
6253 { "vpminsb", { XM, Vex, EXx }, PREFIX_DATA },
6254 { "vpminsd", { XM, Vex, EXx }, PREFIX_DATA },
6255 { "vpminuw", { XM, Vex, EXx }, PREFIX_DATA },
6256 { "vpminud", { XM, Vex, EXx }, PREFIX_DATA },
6257 { "vpmaxsb", { XM, Vex, EXx }, PREFIX_DATA },
6258 { "vpmaxsd", { XM, Vex, EXx }, PREFIX_DATA },
6259 { "vpmaxuw", { XM, Vex, EXx }, PREFIX_DATA },
6260 { "vpmaxud", { XM, Vex, EXx }, PREFIX_DATA },
6261 /* 40 */
6262 { "vpmulld", { XM, Vex, EXx }, PREFIX_DATA },
6263 { VEX_LEN_TABLE (VEX_LEN_0F3841) },
6264 { Bad_Opcode },
6265 { Bad_Opcode },
6266 { Bad_Opcode },
6267 { "vpsrlv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6268 { VEX_W_TABLE (VEX_W_0F3846) },
6269 { "vpsllv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6270 /* 48 */
6271 { Bad_Opcode },
6272 { X86_64_TABLE (X86_64_VEX_0F3849) },
6273 { Bad_Opcode },
6274 { X86_64_TABLE (X86_64_VEX_0F384B) },
6275 { Bad_Opcode },
6276 { Bad_Opcode },
6277 { Bad_Opcode },
6278 { Bad_Opcode },
6279 /* 50 */
6280 { VEX_W_TABLE (VEX_W_0F3850) },
6281 { VEX_W_TABLE (VEX_W_0F3851) },
6282 { VEX_W_TABLE (VEX_W_0F3852) },
6283 { VEX_W_TABLE (VEX_W_0F3853) },
6284 { Bad_Opcode },
6285 { Bad_Opcode },
6286 { Bad_Opcode },
6287 { Bad_Opcode },
6288 /* 58 */
6289 { VEX_W_TABLE (VEX_W_0F3858) },
6290 { VEX_W_TABLE (VEX_W_0F3859) },
6291 { MOD_TABLE (MOD_VEX_0F385A) },
6292 { Bad_Opcode },
6293 { X86_64_TABLE (X86_64_VEX_0F385C) },
6294 { Bad_Opcode },
6295 { X86_64_TABLE (X86_64_VEX_0F385E) },
6296 { Bad_Opcode },
6297 /* 60 */
6298 { Bad_Opcode },
6299 { Bad_Opcode },
6300 { Bad_Opcode },
6301 { Bad_Opcode },
6302 { Bad_Opcode },
6303 { Bad_Opcode },
6304 { Bad_Opcode },
6305 { Bad_Opcode },
6306 /* 68 */
6307 { Bad_Opcode },
6308 { Bad_Opcode },
6309 { Bad_Opcode },
6310 { Bad_Opcode },
6311 { Bad_Opcode },
6312 { Bad_Opcode },
6313 { Bad_Opcode },
6314 { Bad_Opcode },
6315 /* 70 */
6316 { Bad_Opcode },
6317 { Bad_Opcode },
6318 { Bad_Opcode },
6319 { Bad_Opcode },
6320 { Bad_Opcode },
6321 { Bad_Opcode },
6322 { Bad_Opcode },
6323 { Bad_Opcode },
6324 /* 78 */
6325 { VEX_W_TABLE (VEX_W_0F3878) },
6326 { VEX_W_TABLE (VEX_W_0F3879) },
6327 { Bad_Opcode },
6328 { Bad_Opcode },
6329 { Bad_Opcode },
6330 { Bad_Opcode },
6331 { Bad_Opcode },
6332 { Bad_Opcode },
6333 /* 80 */
6334 { Bad_Opcode },
6335 { Bad_Opcode },
6336 { Bad_Opcode },
6337 { Bad_Opcode },
6338 { Bad_Opcode },
6339 { Bad_Opcode },
6340 { Bad_Opcode },
6341 { Bad_Opcode },
6342 /* 88 */
6343 { Bad_Opcode },
6344 { Bad_Opcode },
6345 { Bad_Opcode },
6346 { Bad_Opcode },
6347 { MOD_TABLE (MOD_VEX_0F388C) },
6348 { Bad_Opcode },
6349 { MOD_TABLE (MOD_VEX_0F388E) },
6350 { Bad_Opcode },
6351 /* 90 */
6352 { "vpgatherd%DQ", { XM, MVexVSIBDWpX, Vex }, PREFIX_DATA },
6353 { "vpgatherq%DQ", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6354 { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, PREFIX_DATA },
6355 { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6356 { Bad_Opcode },
6357 { Bad_Opcode },
6358 { "vfmaddsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6359 { "vfmsubadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6360 /* 98 */
6361 { "vfmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6362 { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6363 { "vfmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6364 { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6365 { "vfnmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6366 { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6367 { "vfnmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6368 { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6369 /* a0 */
6370 { Bad_Opcode },
6371 { Bad_Opcode },
6372 { Bad_Opcode },
6373 { Bad_Opcode },
6374 { Bad_Opcode },
6375 { Bad_Opcode },
6376 { "vfmaddsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6377 { "vfmsubadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6378 /* a8 */
6379 { "vfmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6380 { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6381 { "vfmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6382 { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6383 { "vfnmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6384 { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6385 { "vfnmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6386 { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6387 /* b0 */
6388 { Bad_Opcode },
6389 { Bad_Opcode },
6390 { Bad_Opcode },
6391 { Bad_Opcode },
6392 { Bad_Opcode },
6393 { Bad_Opcode },
6394 { "vfmaddsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6395 { "vfmsubadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6396 /* b8 */
6397 { "vfmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6398 { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6399 { "vfmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6400 { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6401 { "vfnmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6402 { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6403 { "vfnmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6404 { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6405 /* c0 */
6406 { Bad_Opcode },
6407 { Bad_Opcode },
6408 { Bad_Opcode },
6409 { Bad_Opcode },
6410 { Bad_Opcode },
6411 { Bad_Opcode },
6412 { Bad_Opcode },
6413 { Bad_Opcode },
6414 /* c8 */
6415 { Bad_Opcode },
6416 { Bad_Opcode },
6417 { Bad_Opcode },
6418 { Bad_Opcode },
6419 { Bad_Opcode },
6420 { Bad_Opcode },
6421 { Bad_Opcode },
6422 { VEX_W_TABLE (VEX_W_0F38CF) },
6423 /* d0 */
6424 { Bad_Opcode },
6425 { Bad_Opcode },
6426 { Bad_Opcode },
6427 { Bad_Opcode },
6428 { Bad_Opcode },
6429 { Bad_Opcode },
6430 { Bad_Opcode },
6431 { Bad_Opcode },
6432 /* d8 */
6433 { Bad_Opcode },
6434 { Bad_Opcode },
6435 { Bad_Opcode },
6436 { VEX_LEN_TABLE (VEX_LEN_0F38DB) },
6437 { "vaesenc", { XM, Vex, EXx }, PREFIX_DATA },
6438 { "vaesenclast", { XM, Vex, EXx }, PREFIX_DATA },
6439 { "vaesdec", { XM, Vex, EXx }, PREFIX_DATA },
6440 { "vaesdeclast", { XM, Vex, EXx }, PREFIX_DATA },
6441 /* e0 */
6442 { Bad_Opcode },
6443 { Bad_Opcode },
6444 { Bad_Opcode },
6445 { Bad_Opcode },
6446 { Bad_Opcode },
6447 { Bad_Opcode },
6448 { Bad_Opcode },
6449 { Bad_Opcode },
6450 /* e8 */
6451 { Bad_Opcode },
6452 { Bad_Opcode },
6453 { Bad_Opcode },
6454 { Bad_Opcode },
6455 { Bad_Opcode },
6456 { Bad_Opcode },
6457 { Bad_Opcode },
6458 { Bad_Opcode },
6459 /* f0 */
6460 { Bad_Opcode },
6461 { Bad_Opcode },
6462 { VEX_LEN_TABLE (VEX_LEN_0F38F2) },
6463 { REG_TABLE (REG_VEX_0F38F3) },
6464 { Bad_Opcode },
6465 { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
6466 { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
6467 { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
6468 /* f8 */
6469 { Bad_Opcode },
6470 { Bad_Opcode },
6471 { Bad_Opcode },
6472 { Bad_Opcode },
6473 { Bad_Opcode },
6474 { Bad_Opcode },
6475 { Bad_Opcode },
6476 { Bad_Opcode },
6477 },
6478 /* VEX_0F3A */
6479 {
6480 /* 00 */
6481 { VEX_LEN_TABLE (VEX_LEN_0F3A00) },
6482 { VEX_LEN_TABLE (VEX_LEN_0F3A01) },
6483 { VEX_W_TABLE (VEX_W_0F3A02) },
6484 { Bad_Opcode },
6485 { VEX_W_TABLE (VEX_W_0F3A04) },
6486 { VEX_W_TABLE (VEX_W_0F3A05) },
6487 { VEX_LEN_TABLE (VEX_LEN_0F3A06) },
6488 { Bad_Opcode },
6489 /* 08 */
6490 { "vroundps", { XM, EXx, Ib }, PREFIX_DATA },
6491 { "vroundpd", { XM, EXx, Ib }, PREFIX_DATA },
6492 { "vroundss", { XMScalar, VexScalar, EXxmm_md, Ib }, PREFIX_DATA },
6493 { "vroundsd", { XMScalar, VexScalar, EXxmm_mq, Ib }, PREFIX_DATA },
6494 { "vblendps", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6495 { "vblendpd", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6496 { "vpblendw", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6497 { "vpalignr", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6498 /* 10 */
6499 { Bad_Opcode },
6500 { Bad_Opcode },
6501 { Bad_Opcode },
6502 { Bad_Opcode },
6503 { VEX_LEN_TABLE (VEX_LEN_0F3A14) },
6504 { VEX_LEN_TABLE (VEX_LEN_0F3A15) },
6505 { VEX_LEN_TABLE (VEX_LEN_0F3A16) },
6506 { VEX_LEN_TABLE (VEX_LEN_0F3A17) },
6507 /* 18 */
6508 { VEX_LEN_TABLE (VEX_LEN_0F3A18) },
6509 { VEX_LEN_TABLE (VEX_LEN_0F3A19) },
6510 { Bad_Opcode },
6511 { Bad_Opcode },
6512 { Bad_Opcode },
6513 { VEX_W_TABLE (VEX_W_0F3A1D) },
6514 { Bad_Opcode },
6515 { Bad_Opcode },
6516 /* 20 */
6517 { VEX_LEN_TABLE (VEX_LEN_0F3A20) },
6518 { VEX_LEN_TABLE (VEX_LEN_0F3A21) },
6519 { VEX_LEN_TABLE (VEX_LEN_0F3A22) },
6520 { Bad_Opcode },
6521 { Bad_Opcode },
6522 { Bad_Opcode },
6523 { Bad_Opcode },
6524 { Bad_Opcode },
6525 /* 28 */
6526 { Bad_Opcode },
6527 { Bad_Opcode },
6528 { Bad_Opcode },
6529 { Bad_Opcode },
6530 { Bad_Opcode },
6531 { Bad_Opcode },
6532 { Bad_Opcode },
6533 { Bad_Opcode },
6534 /* 30 */
6535 { VEX_LEN_TABLE (VEX_LEN_0F3A30) },
6536 { VEX_LEN_TABLE (VEX_LEN_0F3A31) },
6537 { VEX_LEN_TABLE (VEX_LEN_0F3A32) },
6538 { VEX_LEN_TABLE (VEX_LEN_0F3A33) },
6539 { Bad_Opcode },
6540 { Bad_Opcode },
6541 { Bad_Opcode },
6542 { Bad_Opcode },
6543 /* 38 */
6544 { VEX_LEN_TABLE (VEX_LEN_0F3A38) },
6545 { VEX_LEN_TABLE (VEX_LEN_0F3A39) },
6546 { Bad_Opcode },
6547 { Bad_Opcode },
6548 { Bad_Opcode },
6549 { Bad_Opcode },
6550 { Bad_Opcode },
6551 { Bad_Opcode },
6552 /* 40 */
6553 { "vdpps", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6554 { VEX_LEN_TABLE (VEX_LEN_0F3A41) },
6555 { "vmpsadbw", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6556 { Bad_Opcode },
6557 { "vpclmulqdq", { XM, Vex, EXx, PCLMUL }, PREFIX_DATA },
6558 { Bad_Opcode },
6559 { VEX_LEN_TABLE (VEX_LEN_0F3A46) },
6560 { Bad_Opcode },
6561 /* 48 */
6562 { "vpermil2ps", { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6563 { "vpermil2pd", { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6564 { VEX_W_TABLE (VEX_W_0F3A4A) },
6565 { VEX_W_TABLE (VEX_W_0F3A4B) },
6566 { VEX_W_TABLE (VEX_W_0F3A4C) },
6567 { Bad_Opcode },
6568 { Bad_Opcode },
6569 { Bad_Opcode },
6570 /* 50 */
6571 { Bad_Opcode },
6572 { Bad_Opcode },
6573 { Bad_Opcode },
6574 { Bad_Opcode },
6575 { Bad_Opcode },
6576 { Bad_Opcode },
6577 { Bad_Opcode },
6578 { Bad_Opcode },
6579 /* 58 */
6580 { Bad_Opcode },
6581 { Bad_Opcode },
6582 { Bad_Opcode },
6583 { Bad_Opcode },
6584 { "vfmaddsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6585 { "vfmaddsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6586 { "vfmsubaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6587 { "vfmsubaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6588 /* 60 */
6589 { VEX_LEN_TABLE (VEX_LEN_0F3A60) },
6590 { VEX_LEN_TABLE (VEX_LEN_0F3A61) },
6591 { VEX_LEN_TABLE (VEX_LEN_0F3A62) },
6592 { VEX_LEN_TABLE (VEX_LEN_0F3A63) },
6593 { Bad_Opcode },
6594 { Bad_Opcode },
6595 { Bad_Opcode },
6596 { Bad_Opcode },
6597 /* 68 */
6598 { "vfmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6599 { "vfmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6600 { "vfmaddss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
6601 { "vfmaddsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
6602 { "vfmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6603 { "vfmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6604 { "vfmsubss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
6605 { "vfmsubsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
6606 /* 70 */
6607 { Bad_Opcode },
6608 { Bad_Opcode },
6609 { Bad_Opcode },
6610 { Bad_Opcode },
6611 { Bad_Opcode },
6612 { Bad_Opcode },
6613 { Bad_Opcode },
6614 { Bad_Opcode },
6615 /* 78 */
6616 { "vfnmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6617 { "vfnmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6618 { "vfnmaddss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
6619 { "vfnmaddsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
6620 { "vfnmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6621 { "vfnmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6622 { "vfnmsubss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
6623 { "vfnmsubsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
6624 /* 80 */
6625 { Bad_Opcode },
6626 { Bad_Opcode },
6627 { Bad_Opcode },
6628 { Bad_Opcode },
6629 { Bad_Opcode },
6630 { Bad_Opcode },
6631 { Bad_Opcode },
6632 { Bad_Opcode },
6633 /* 88 */
6634 { Bad_Opcode },
6635 { Bad_Opcode },
6636 { Bad_Opcode },
6637 { Bad_Opcode },
6638 { Bad_Opcode },
6639 { Bad_Opcode },
6640 { Bad_Opcode },
6641 { Bad_Opcode },
6642 /* 90 */
6643 { Bad_Opcode },
6644 { Bad_Opcode },
6645 { Bad_Opcode },
6646 { Bad_Opcode },
6647 { Bad_Opcode },
6648 { Bad_Opcode },
6649 { Bad_Opcode },
6650 { Bad_Opcode },
6651 /* 98 */
6652 { Bad_Opcode },
6653 { Bad_Opcode },
6654 { Bad_Opcode },
6655 { Bad_Opcode },
6656 { Bad_Opcode },
6657 { Bad_Opcode },
6658 { Bad_Opcode },
6659 { Bad_Opcode },
6660 /* a0 */
6661 { Bad_Opcode },
6662 { Bad_Opcode },
6663 { Bad_Opcode },
6664 { Bad_Opcode },
6665 { Bad_Opcode },
6666 { Bad_Opcode },
6667 { Bad_Opcode },
6668 { Bad_Opcode },
6669 /* a8 */
6670 { Bad_Opcode },
6671 { Bad_Opcode },
6672 { Bad_Opcode },
6673 { Bad_Opcode },
6674 { Bad_Opcode },
6675 { Bad_Opcode },
6676 { Bad_Opcode },
6677 { Bad_Opcode },
6678 /* b0 */
6679 { Bad_Opcode },
6680 { Bad_Opcode },
6681 { Bad_Opcode },
6682 { Bad_Opcode },
6683 { Bad_Opcode },
6684 { Bad_Opcode },
6685 { Bad_Opcode },
6686 { Bad_Opcode },
6687 /* b8 */
6688 { Bad_Opcode },
6689 { Bad_Opcode },
6690 { Bad_Opcode },
6691 { Bad_Opcode },
6692 { Bad_Opcode },
6693 { Bad_Opcode },
6694 { Bad_Opcode },
6695 { Bad_Opcode },
6696 /* c0 */
6697 { Bad_Opcode },
6698 { Bad_Opcode },
6699 { Bad_Opcode },
6700 { Bad_Opcode },
6701 { Bad_Opcode },
6702 { Bad_Opcode },
6703 { Bad_Opcode },
6704 { Bad_Opcode },
6705 /* c8 */
6706 { Bad_Opcode },
6707 { Bad_Opcode },
6708 { Bad_Opcode },
6709 { Bad_Opcode },
6710 { Bad_Opcode },
6711 { Bad_Opcode },
6712 { VEX_W_TABLE (VEX_W_0F3ACE) },
6713 { VEX_W_TABLE (VEX_W_0F3ACF) },
6714 /* d0 */
6715 { Bad_Opcode },
6716 { Bad_Opcode },
6717 { Bad_Opcode },
6718 { Bad_Opcode },
6719 { Bad_Opcode },
6720 { Bad_Opcode },
6721 { Bad_Opcode },
6722 { Bad_Opcode },
6723 /* d8 */
6724 { Bad_Opcode },
6725 { Bad_Opcode },
6726 { Bad_Opcode },
6727 { Bad_Opcode },
6728 { Bad_Opcode },
6729 { Bad_Opcode },
6730 { Bad_Opcode },
6731 { VEX_LEN_TABLE (VEX_LEN_0F3ADF) },
6732 /* e0 */
6733 { Bad_Opcode },
6734 { Bad_Opcode },
6735 { Bad_Opcode },
6736 { Bad_Opcode },
6737 { Bad_Opcode },
6738 { Bad_Opcode },
6739 { Bad_Opcode },
6740 { Bad_Opcode },
6741 /* e8 */
6742 { Bad_Opcode },
6743 { Bad_Opcode },
6744 { Bad_Opcode },
6745 { Bad_Opcode },
6746 { Bad_Opcode },
6747 { Bad_Opcode },
6748 { Bad_Opcode },
6749 { Bad_Opcode },
6750 /* f0 */
6751 { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
6752 { Bad_Opcode },
6753 { Bad_Opcode },
6754 { Bad_Opcode },
6755 { Bad_Opcode },
6756 { Bad_Opcode },
6757 { Bad_Opcode },
6758 { Bad_Opcode },
6759 /* f8 */
6760 { Bad_Opcode },
6761 { Bad_Opcode },
6762 { Bad_Opcode },
6763 { Bad_Opcode },
6764 { Bad_Opcode },
6765 { Bad_Opcode },
6766 { Bad_Opcode },
6767 { Bad_Opcode },
6768 },
6769 };
6770
6771 #include "i386-dis-evex.h"
6772
6773 static const struct dis386 vex_len_table[][2] = {
6774 /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */
6775 {
6776 { "vmovlpX", { XM, Vex, EXq }, 0 },
6777 },
6778
6779 /* VEX_LEN_0F12_P_0_M_1 */
6780 {
6781 { "vmovhlps", { XM, Vex, EXq }, 0 },
6782 },
6783
6784 /* VEX_LEN_0F13_M_0 */
6785 {
6786 { "vmovlpX", { EXq, XM }, PREFIX_OPCODE },
6787 },
6788
6789 /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */
6790 {
6791 { "vmovhpX", { XM, Vex, EXq }, 0 },
6792 },
6793
6794 /* VEX_LEN_0F16_P_0_M_1 */
6795 {
6796 { "vmovlhps", { XM, Vex, EXq }, 0 },
6797 },
6798
6799 /* VEX_LEN_0F17_M_0 */
6800 {
6801 { "vmovhpX", { EXq, XM }, PREFIX_OPCODE },
6802 },
6803
6804 /* VEX_LEN_0F41_P_0 */
6805 {
6806 { Bad_Opcode },
6807 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
6808 },
6809 /* VEX_LEN_0F41_P_2 */
6810 {
6811 { Bad_Opcode },
6812 { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
6813 },
6814 /* VEX_LEN_0F42_P_0 */
6815 {
6816 { Bad_Opcode },
6817 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
6818 },
6819 /* VEX_LEN_0F42_P_2 */
6820 {
6821 { Bad_Opcode },
6822 { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
6823 },
6824 /* VEX_LEN_0F44_P_0 */
6825 {
6826 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
6827 },
6828 /* VEX_LEN_0F44_P_2 */
6829 {
6830 { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
6831 },
6832 /* VEX_LEN_0F45_P_0 */
6833 {
6834 { Bad_Opcode },
6835 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
6836 },
6837 /* VEX_LEN_0F45_P_2 */
6838 {
6839 { Bad_Opcode },
6840 { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
6841 },
6842 /* VEX_LEN_0F46_P_0 */
6843 {
6844 { Bad_Opcode },
6845 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
6846 },
6847 /* VEX_LEN_0F46_P_2 */
6848 {
6849 { Bad_Opcode },
6850 { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
6851 },
6852 /* VEX_LEN_0F47_P_0 */
6853 {
6854 { Bad_Opcode },
6855 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
6856 },
6857 /* VEX_LEN_0F47_P_2 */
6858 {
6859 { Bad_Opcode },
6860 { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
6861 },
6862 /* VEX_LEN_0F4A_P_0 */
6863 {
6864 { Bad_Opcode },
6865 { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
6866 },
6867 /* VEX_LEN_0F4A_P_2 */
6868 {
6869 { Bad_Opcode },
6870 { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
6871 },
6872 /* VEX_LEN_0F4B_P_0 */
6873 {
6874 { Bad_Opcode },
6875 { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
6876 },
6877 /* VEX_LEN_0F4B_P_2 */
6878 {
6879 { Bad_Opcode },
6880 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
6881 },
6882
6883 /* VEX_LEN_0F6E */
6884 {
6885 { "vmovK", { XMScalar, Edq }, PREFIX_DATA },
6886 },
6887
6888 /* VEX_LEN_0F77 */
6889 {
6890 { "vzeroupper", { XX }, 0 },
6891 { "vzeroall", { XX }, 0 },
6892 },
6893
6894 /* VEX_LEN_0F7E_P_1 */
6895 {
6896 { "vmovq", { XMScalar, EXxmm_mq }, 0 },
6897 },
6898
6899 /* VEX_LEN_0F7E_P_2 */
6900 {
6901 { "vmovK", { Edq, XMScalar }, 0 },
6902 },
6903
6904 /* VEX_LEN_0F90_P_0 */
6905 {
6906 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
6907 },
6908
6909 /* VEX_LEN_0F90_P_2 */
6910 {
6911 { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
6912 },
6913
6914 /* VEX_LEN_0F91_P_0 */
6915 {
6916 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
6917 },
6918
6919 /* VEX_LEN_0F91_P_2 */
6920 {
6921 { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
6922 },
6923
6924 /* VEX_LEN_0F92_P_0 */
6925 {
6926 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
6927 },
6928
6929 /* VEX_LEN_0F92_P_2 */
6930 {
6931 { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
6932 },
6933
6934 /* VEX_LEN_0F92_P_3 */
6935 {
6936 { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) },
6937 },
6938
6939 /* VEX_LEN_0F93_P_0 */
6940 {
6941 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
6942 },
6943
6944 /* VEX_LEN_0F93_P_2 */
6945 {
6946 { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
6947 },
6948
6949 /* VEX_LEN_0F93_P_3 */
6950 {
6951 { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) },
6952 },
6953
6954 /* VEX_LEN_0F98_P_0 */
6955 {
6956 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
6957 },
6958
6959 /* VEX_LEN_0F98_P_2 */
6960 {
6961 { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
6962 },
6963
6964 /* VEX_LEN_0F99_P_0 */
6965 {
6966 { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
6967 },
6968
6969 /* VEX_LEN_0F99_P_2 */
6970 {
6971 { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
6972 },
6973
6974 /* VEX_LEN_0FAE_R_2_M_0 */
6975 {
6976 { "vldmxcsr", { Md }, 0 },
6977 },
6978
6979 /* VEX_LEN_0FAE_R_3_M_0 */
6980 {
6981 { "vstmxcsr", { Md }, 0 },
6982 },
6983
6984 /* VEX_LEN_0FC4 */
6985 {
6986 { "vpinsrw", { XM, Vex, Edqw, Ib }, PREFIX_DATA },
6987 },
6988
6989 /* VEX_LEN_0FC5 */
6990 {
6991 { "vpextrw", { Gdq, XS, Ib }, PREFIX_DATA },
6992 },
6993
6994 /* VEX_LEN_0FD6 */
6995 {
6996 { "vmovq", { EXqS, XMScalar }, PREFIX_DATA },
6997 },
6998
6999 /* VEX_LEN_0FF7 */
7000 {
7001 { "vmaskmovdqu", { XM, XS }, PREFIX_DATA },
7002 },
7003
7004 /* VEX_LEN_0F3816 */
7005 {
7006 { Bad_Opcode },
7007 { VEX_W_TABLE (VEX_W_0F3816_L_1) },
7008 },
7009
7010 /* VEX_LEN_0F3819 */
7011 {
7012 { Bad_Opcode },
7013 { VEX_W_TABLE (VEX_W_0F3819_L_1) },
7014 },
7015
7016 /* VEX_LEN_0F381A_M_0 */
7017 {
7018 { Bad_Opcode },
7019 { VEX_W_TABLE (VEX_W_0F381A_M_0_L_1) },
7020 },
7021
7022 /* VEX_LEN_0F3836 */
7023 {
7024 { Bad_Opcode },
7025 { VEX_W_TABLE (VEX_W_0F3836) },
7026 },
7027
7028 /* VEX_LEN_0F3841 */
7029 {
7030 { "vphminposuw", { XM, EXx }, PREFIX_DATA },
7031 },
7032
7033 /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_0 */
7034 {
7035 { "ldtilecfg", { M }, 0 },
7036 },
7037
7038 /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0 */
7039 {
7040 { "tilerelease", { Skip_MODRM }, 0 },
7041 },
7042
7043 /* VEX_LEN_0F3849_X86_64_P_2_W_0_M_0 */
7044 {
7045 { "sttilecfg", { M }, 0 },
7046 },
7047
7048 /* VEX_LEN_0F3849_X86_64_P_3_W_0_M_0 */
7049 {
7050 { "tilezero", { TMM, Skip_MODRM }, 0 },
7051 },
7052
7053 /* VEX_LEN_0F384B_X86_64_P_1_W_0_M_0 */
7054 {
7055 { "tilestored", { MVexSIBMEM, TMM }, 0 },
7056 },
7057 /* VEX_LEN_0F384B_X86_64_P_2_W_0_M_0 */
7058 {
7059 { "tileloaddt1", { TMM, MVexSIBMEM }, 0 },
7060 },
7061
7062 /* VEX_LEN_0F384B_X86_64_P_3_W_0_M_0 */
7063 {
7064 { "tileloadd", { TMM, MVexSIBMEM }, 0 },
7065 },
7066
7067 /* VEX_LEN_0F385A_M_0 */
7068 {
7069 { Bad_Opcode },
7070 { VEX_W_TABLE (VEX_W_0F385A_M_0_L_0) },
7071 },
7072
7073 /* VEX_LEN_0F385C_X86_64_P_1_W_0_M_0 */
7074 {
7075 { "tdpbf16ps", { TMM, EXtmm, VexTmm }, 0 },
7076 },
7077
7078 /* VEX_LEN_0F385E_X86_64_P_0_W_0_M_0 */
7079 {
7080 { "tdpbuud", {TMM, EXtmm, VexTmm }, 0 },
7081 },
7082
7083 /* VEX_LEN_0F385E_X86_64_P_1_W_0_M_0 */
7084 {
7085 { "tdpbsud", {TMM, EXtmm, VexTmm }, 0 },
7086 },
7087
7088 /* VEX_LEN_0F385E_X86_64_P_2_W_0_M_0 */
7089 {
7090 { "tdpbusd", {TMM, EXtmm, VexTmm }, 0 },
7091 },
7092
7093 /* VEX_LEN_0F385E_X86_64_P_3_W_0_M_0 */
7094 {
7095 { "tdpbssd", {TMM, EXtmm, VexTmm }, 0 },
7096 },
7097
7098 /* VEX_LEN_0F38DB */
7099 {
7100 { "vaesimc", { XM, EXx }, PREFIX_DATA },
7101 },
7102
7103 /* VEX_LEN_0F38F2 */
7104 {
7105 { "andnS", { Gdq, VexGdq, Edq }, PREFIX_OPCODE },
7106 },
7107
7108 /* VEX_LEN_0F38F3_R_1 */
7109 {
7110 { "blsrS", { VexGdq, Edq }, PREFIX_OPCODE },
7111 },
7112
7113 /* VEX_LEN_0F38F3_R_2 */
7114 {
7115 { "blsmskS", { VexGdq, Edq }, PREFIX_OPCODE },
7116 },
7117
7118 /* VEX_LEN_0F38F3_R_3 */
7119 {
7120 { "blsiS", { VexGdq, Edq }, PREFIX_OPCODE },
7121 },
7122
7123 /* VEX_LEN_0F38F5_P_0 */
7124 {
7125 { "bzhiS", { Gdq, Edq, VexGdq }, 0 },
7126 },
7127
7128 /* VEX_LEN_0F38F5_P_1 */
7129 {
7130 { "pextS", { Gdq, VexGdq, Edq }, 0 },
7131 },
7132
7133 /* VEX_LEN_0F38F5_P_3 */
7134 {
7135 { "pdepS", { Gdq, VexGdq, Edq }, 0 },
7136 },
7137
7138 /* VEX_LEN_0F38F6_P_3 */
7139 {
7140 { "mulxS", { Gdq, VexGdq, Edq }, 0 },
7141 },
7142
7143 /* VEX_LEN_0F38F7_P_0 */
7144 {
7145 { "bextrS", { Gdq, Edq, VexGdq }, 0 },
7146 },
7147
7148 /* VEX_LEN_0F38F7_P_1 */
7149 {
7150 { "sarxS", { Gdq, Edq, VexGdq }, 0 },
7151 },
7152
7153 /* VEX_LEN_0F38F7_P_2 */
7154 {
7155 { "shlxS", { Gdq, Edq, VexGdq }, 0 },
7156 },
7157
7158 /* VEX_LEN_0F38F7_P_3 */
7159 {
7160 { "shrxS", { Gdq, Edq, VexGdq }, 0 },
7161 },
7162
7163 /* VEX_LEN_0F3A00 */
7164 {
7165 { Bad_Opcode },
7166 { VEX_W_TABLE (VEX_W_0F3A00_L_1) },
7167 },
7168
7169 /* VEX_LEN_0F3A01 */
7170 {
7171 { Bad_Opcode },
7172 { VEX_W_TABLE (VEX_W_0F3A01_L_1) },
7173 },
7174
7175 /* VEX_LEN_0F3A06 */
7176 {
7177 { Bad_Opcode },
7178 { VEX_W_TABLE (VEX_W_0F3A06_L_1) },
7179 },
7180
7181 /* VEX_LEN_0F3A14 */
7182 {
7183 { "vpextrb", { Edqb, XM, Ib }, PREFIX_DATA },
7184 },
7185
7186 /* VEX_LEN_0F3A15 */
7187 {
7188 { "vpextrw", { Edqw, XM, Ib }, PREFIX_DATA },
7189 },
7190
7191 /* VEX_LEN_0F3A16 */
7192 {
7193 { "vpextrK", { Edq, XM, Ib }, PREFIX_DATA },
7194 },
7195
7196 /* VEX_LEN_0F3A17 */
7197 {
7198 { "vextractps", { Edqd, XM, Ib }, PREFIX_DATA },
7199 },
7200
7201 /* VEX_LEN_0F3A18 */
7202 {
7203 { Bad_Opcode },
7204 { VEX_W_TABLE (VEX_W_0F3A18_L_1) },
7205 },
7206
7207 /* VEX_LEN_0F3A19 */
7208 {
7209 { Bad_Opcode },
7210 { VEX_W_TABLE (VEX_W_0F3A19_L_1) },
7211 },
7212
7213 /* VEX_LEN_0F3A20 */
7214 {
7215 { "vpinsrb", { XM, Vex, Edqb, Ib }, PREFIX_DATA },
7216 },
7217
7218 /* VEX_LEN_0F3A21 */
7219 {
7220 { "vinsertps", { XM, Vex, EXd, Ib }, PREFIX_DATA },
7221 },
7222
7223 /* VEX_LEN_0F3A22 */
7224 {
7225 { "vpinsrK", { XM, Vex, Edq, Ib }, PREFIX_DATA },
7226 },
7227
7228 /* VEX_LEN_0F3A30 */
7229 {
7230 { MOD_TABLE (MOD_VEX_0F3A30_L_0) },
7231 },
7232
7233 /* VEX_LEN_0F3A31 */
7234 {
7235 { MOD_TABLE (MOD_VEX_0F3A31_L_0) },
7236 },
7237
7238 /* VEX_LEN_0F3A32 */
7239 {
7240 { MOD_TABLE (MOD_VEX_0F3A32_L_0) },
7241 },
7242
7243 /* VEX_LEN_0F3A33 */
7244 {
7245 { MOD_TABLE (MOD_VEX_0F3A33_L_0) },
7246 },
7247
7248 /* VEX_LEN_0F3A38 */
7249 {
7250 { Bad_Opcode },
7251 { VEX_W_TABLE (VEX_W_0F3A38_L_1) },
7252 },
7253
7254 /* VEX_LEN_0F3A39 */
7255 {
7256 { Bad_Opcode },
7257 { VEX_W_TABLE (VEX_W_0F3A39_L_1) },
7258 },
7259
7260 /* VEX_LEN_0F3A41 */
7261 {
7262 { "vdppd", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7263 },
7264
7265 /* VEX_LEN_0F3A46 */
7266 {
7267 { Bad_Opcode },
7268 { VEX_W_TABLE (VEX_W_0F3A46_L_1) },
7269 },
7270
7271 /* VEX_LEN_0F3A60 */
7272 {
7273 { "vpcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7274 },
7275
7276 /* VEX_LEN_0F3A61 */
7277 {
7278 { "vpcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7279 },
7280
7281 /* VEX_LEN_0F3A62 */
7282 {
7283 { "vpcmpistrm", { XM, EXx, Ib }, PREFIX_DATA },
7284 },
7285
7286 /* VEX_LEN_0F3A63 */
7287 {
7288 { "vpcmpistri", { XM, EXx, Ib }, PREFIX_DATA },
7289 },
7290
7291 /* VEX_LEN_0F3ADF */
7292 {
7293 { "vaeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
7294 },
7295
7296 /* VEX_LEN_0F3AF0_P_3 */
7297 {
7298 { "rorxS", { Gdq, Edq, Ib }, 0 },
7299 },
7300
7301 /* VEX_LEN_0FXOP_08_85 */
7302 {
7303 { VEX_W_TABLE (VEX_W_0FXOP_08_85_L_0) },
7304 },
7305
7306 /* VEX_LEN_0FXOP_08_86 */
7307 {
7308 { VEX_W_TABLE (VEX_W_0FXOP_08_86_L_0) },
7309 },
7310
7311 /* VEX_LEN_0FXOP_08_87 */
7312 {
7313 { VEX_W_TABLE (VEX_W_0FXOP_08_87_L_0) },
7314 },
7315
7316 /* VEX_LEN_0FXOP_08_8E */
7317 {
7318 { VEX_W_TABLE (VEX_W_0FXOP_08_8E_L_0) },
7319 },
7320
7321 /* VEX_LEN_0FXOP_08_8F */
7322 {
7323 { VEX_W_TABLE (VEX_W_0FXOP_08_8F_L_0) },
7324 },
7325
7326 /* VEX_LEN_0FXOP_08_95 */
7327 {
7328 { VEX_W_TABLE (VEX_W_0FXOP_08_95_L_0) },
7329 },
7330
7331 /* VEX_LEN_0FXOP_08_96 */
7332 {
7333 { VEX_W_TABLE (VEX_W_0FXOP_08_96_L_0) },
7334 },
7335
7336 /* VEX_LEN_0FXOP_08_97 */
7337 {
7338 { VEX_W_TABLE (VEX_W_0FXOP_08_97_L_0) },
7339 },
7340
7341 /* VEX_LEN_0FXOP_08_9E */
7342 {
7343 { VEX_W_TABLE (VEX_W_0FXOP_08_9E_L_0) },
7344 },
7345
7346 /* VEX_LEN_0FXOP_08_9F */
7347 {
7348 { VEX_W_TABLE (VEX_W_0FXOP_08_9F_L_0) },
7349 },
7350
7351 /* VEX_LEN_0FXOP_08_A3 */
7352 {
7353 { "vpperm", { XM, Vex, EXx, XMVexI4 }, 0 },
7354 },
7355
7356 /* VEX_LEN_0FXOP_08_A6 */
7357 {
7358 { VEX_W_TABLE (VEX_W_0FXOP_08_A6_L_0) },
7359 },
7360
7361 /* VEX_LEN_0FXOP_08_B6 */
7362 {
7363 { VEX_W_TABLE (VEX_W_0FXOP_08_B6_L_0) },
7364 },
7365
7366 /* VEX_LEN_0FXOP_08_C0 */
7367 {
7368 { VEX_W_TABLE (VEX_W_0FXOP_08_C0_L_0) },
7369 },
7370
7371 /* VEX_LEN_0FXOP_08_C1 */
7372 {
7373 { VEX_W_TABLE (VEX_W_0FXOP_08_C1_L_0) },
7374 },
7375
7376 /* VEX_LEN_0FXOP_08_C2 */
7377 {
7378 { VEX_W_TABLE (VEX_W_0FXOP_08_C2_L_0) },
7379 },
7380
7381 /* VEX_LEN_0FXOP_08_C3 */
7382 {
7383 { VEX_W_TABLE (VEX_W_0FXOP_08_C3_L_0) },
7384 },
7385
7386 /* VEX_LEN_0FXOP_08_CC */
7387 {
7388 { VEX_W_TABLE (VEX_W_0FXOP_08_CC_L_0) },
7389 },
7390
7391 /* VEX_LEN_0FXOP_08_CD */
7392 {
7393 { VEX_W_TABLE (VEX_W_0FXOP_08_CD_L_0) },
7394 },
7395
7396 /* VEX_LEN_0FXOP_08_CE */
7397 {
7398 { VEX_W_TABLE (VEX_W_0FXOP_08_CE_L_0) },
7399 },
7400
7401 /* VEX_LEN_0FXOP_08_CF */
7402 {
7403 { VEX_W_TABLE (VEX_W_0FXOP_08_CF_L_0) },
7404 },
7405
7406 /* VEX_LEN_0FXOP_08_EC */
7407 {
7408 { VEX_W_TABLE (VEX_W_0FXOP_08_EC_L_0) },
7409 },
7410
7411 /* VEX_LEN_0FXOP_08_ED */
7412 {
7413 { VEX_W_TABLE (VEX_W_0FXOP_08_ED_L_0) },
7414 },
7415
7416 /* VEX_LEN_0FXOP_08_EE */
7417 {
7418 { VEX_W_TABLE (VEX_W_0FXOP_08_EE_L_0) },
7419 },
7420
7421 /* VEX_LEN_0FXOP_08_EF */
7422 {
7423 { VEX_W_TABLE (VEX_W_0FXOP_08_EF_L_0) },
7424 },
7425
7426 /* VEX_LEN_0FXOP_09_01 */
7427 {
7428 { REG_TABLE (REG_0FXOP_09_01_L_0) },
7429 },
7430
7431 /* VEX_LEN_0FXOP_09_02 */
7432 {
7433 { REG_TABLE (REG_0FXOP_09_02_L_0) },
7434 },
7435
7436 /* VEX_LEN_0FXOP_09_12_M_1 */
7437 {
7438 { REG_TABLE (REG_0FXOP_09_12_M_1_L_0) },
7439 },
7440
7441 /* VEX_LEN_0FXOP_09_82_W_0 */
7442 {
7443 { "vfrczss", { XM, EXd }, 0 },
7444 },
7445
7446 /* VEX_LEN_0FXOP_09_83_W_0 */
7447 {
7448 { "vfrczsd", { XM, EXq }, 0 },
7449 },
7450
7451 /* VEX_LEN_0FXOP_09_90 */
7452 {
7453 { "vprotb", { XM, EXx, VexW }, 0 },
7454 },
7455
7456 /* VEX_LEN_0FXOP_09_91 */
7457 {
7458 { "vprotw", { XM, EXx, VexW }, 0 },
7459 },
7460
7461 /* VEX_LEN_0FXOP_09_92 */
7462 {
7463 { "vprotd", { XM, EXx, VexW }, 0 },
7464 },
7465
7466 /* VEX_LEN_0FXOP_09_93 */
7467 {
7468 { "vprotq", { XM, EXx, VexW }, 0 },
7469 },
7470
7471 /* VEX_LEN_0FXOP_09_94 */
7472 {
7473 { "vpshlb", { XM, EXx, VexW }, 0 },
7474 },
7475
7476 /* VEX_LEN_0FXOP_09_95 */
7477 {
7478 { "vpshlw", { XM, EXx, VexW }, 0 },
7479 },
7480
7481 /* VEX_LEN_0FXOP_09_96 */
7482 {
7483 { "vpshld", { XM, EXx, VexW }, 0 },
7484 },
7485
7486 /* VEX_LEN_0FXOP_09_97 */
7487 {
7488 { "vpshlq", { XM, EXx, VexW }, 0 },
7489 },
7490
7491 /* VEX_LEN_0FXOP_09_98 */
7492 {
7493 { "vpshab", { XM, EXx, VexW }, 0 },
7494 },
7495
7496 /* VEX_LEN_0FXOP_09_99 */
7497 {
7498 { "vpshaw", { XM, EXx, VexW }, 0 },
7499 },
7500
7501 /* VEX_LEN_0FXOP_09_9A */
7502 {
7503 { "vpshad", { XM, EXx, VexW }, 0 },
7504 },
7505
7506 /* VEX_LEN_0FXOP_09_9B */
7507 {
7508 { "vpshaq", { XM, EXx, VexW }, 0 },
7509 },
7510
7511 /* VEX_LEN_0FXOP_09_C1 */
7512 {
7513 { VEX_W_TABLE (VEX_W_0FXOP_09_C1_L_0) },
7514 },
7515
7516 /* VEX_LEN_0FXOP_09_C2 */
7517 {
7518 { VEX_W_TABLE (VEX_W_0FXOP_09_C2_L_0) },
7519 },
7520
7521 /* VEX_LEN_0FXOP_09_C3 */
7522 {
7523 { VEX_W_TABLE (VEX_W_0FXOP_09_C3_L_0) },
7524 },
7525
7526 /* VEX_LEN_0FXOP_09_C6 */
7527 {
7528 { VEX_W_TABLE (VEX_W_0FXOP_09_C6_L_0) },
7529 },
7530
7531 /* VEX_LEN_0FXOP_09_C7 */
7532 {
7533 { VEX_W_TABLE (VEX_W_0FXOP_09_C7_L_0) },
7534 },
7535
7536 /* VEX_LEN_0FXOP_09_CB */
7537 {
7538 { VEX_W_TABLE (VEX_W_0FXOP_09_CB_L_0) },
7539 },
7540
7541 /* VEX_LEN_0FXOP_09_D1 */
7542 {
7543 { VEX_W_TABLE (VEX_W_0FXOP_09_D1_L_0) },
7544 },
7545
7546 /* VEX_LEN_0FXOP_09_D2 */
7547 {
7548 { VEX_W_TABLE (VEX_W_0FXOP_09_D2_L_0) },
7549 },
7550
7551 /* VEX_LEN_0FXOP_09_D3 */
7552 {
7553 { VEX_W_TABLE (VEX_W_0FXOP_09_D3_L_0) },
7554 },
7555
7556 /* VEX_LEN_0FXOP_09_D6 */
7557 {
7558 { VEX_W_TABLE (VEX_W_0FXOP_09_D6_L_0) },
7559 },
7560
7561 /* VEX_LEN_0FXOP_09_D7 */
7562 {
7563 { VEX_W_TABLE (VEX_W_0FXOP_09_D7_L_0) },
7564 },
7565
7566 /* VEX_LEN_0FXOP_09_DB */
7567 {
7568 { VEX_W_TABLE (VEX_W_0FXOP_09_DB_L_0) },
7569 },
7570
7571 /* VEX_LEN_0FXOP_09_E1 */
7572 {
7573 { VEX_W_TABLE (VEX_W_0FXOP_09_E1_L_0) },
7574 },
7575
7576 /* VEX_LEN_0FXOP_09_E2 */
7577 {
7578 { VEX_W_TABLE (VEX_W_0FXOP_09_E2_L_0) },
7579 },
7580
7581 /* VEX_LEN_0FXOP_09_E3 */
7582 {
7583 { VEX_W_TABLE (VEX_W_0FXOP_09_E3_L_0) },
7584 },
7585
7586 /* VEX_LEN_0FXOP_0A_12 */
7587 {
7588 { REG_TABLE (REG_0FXOP_0A_12_L_0) },
7589 },
7590 };
7591
7592 #include "i386-dis-evex-len.h"
7593
7594 static const struct dis386 vex_w_table[][2] = {
7595 {
7596 /* VEX_W_0F41_P_0_LEN_1 */
7597 { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
7598 { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
7599 },
7600 {
7601 /* VEX_W_0F41_P_2_LEN_1 */
7602 { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
7603 { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
7604 },
7605 {
7606 /* VEX_W_0F42_P_0_LEN_1 */
7607 { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
7608 { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
7609 },
7610 {
7611 /* VEX_W_0F42_P_2_LEN_1 */
7612 { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
7613 { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
7614 },
7615 {
7616 /* VEX_W_0F44_P_0_LEN_0 */
7617 { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
7618 { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
7619 },
7620 {
7621 /* VEX_W_0F44_P_2_LEN_0 */
7622 { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
7623 { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
7624 },
7625 {
7626 /* VEX_W_0F45_P_0_LEN_1 */
7627 { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
7628 { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
7629 },
7630 {
7631 /* VEX_W_0F45_P_2_LEN_1 */
7632 { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
7633 { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
7634 },
7635 {
7636 /* VEX_W_0F46_P_0_LEN_1 */
7637 { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
7638 { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
7639 },
7640 {
7641 /* VEX_W_0F46_P_2_LEN_1 */
7642 { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
7643 { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
7644 },
7645 {
7646 /* VEX_W_0F47_P_0_LEN_1 */
7647 { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
7648 { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
7649 },
7650 {
7651 /* VEX_W_0F47_P_2_LEN_1 */
7652 { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
7653 { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
7654 },
7655 {
7656 /* VEX_W_0F4A_P_0_LEN_1 */
7657 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
7658 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
7659 },
7660 {
7661 /* VEX_W_0F4A_P_2_LEN_1 */
7662 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
7663 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
7664 },
7665 {
7666 /* VEX_W_0F4B_P_0_LEN_1 */
7667 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
7668 { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
7669 },
7670 {
7671 /* VEX_W_0F4B_P_2_LEN_1 */
7672 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
7673 },
7674 {
7675 /* VEX_W_0F90_P_0_LEN_0 */
7676 { "kmovw", { MaskG, MaskE }, 0 },
7677 { "kmovq", { MaskG, MaskE }, 0 },
7678 },
7679 {
7680 /* VEX_W_0F90_P_2_LEN_0 */
7681 { "kmovb", { MaskG, MaskBDE }, 0 },
7682 { "kmovd", { MaskG, MaskBDE }, 0 },
7683 },
7684 {
7685 /* VEX_W_0F91_P_0_LEN_0 */
7686 { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
7687 { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
7688 },
7689 {
7690 /* VEX_W_0F91_P_2_LEN_0 */
7691 { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
7692 { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
7693 },
7694 {
7695 /* VEX_W_0F92_P_0_LEN_0 */
7696 { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
7697 },
7698 {
7699 /* VEX_W_0F92_P_2_LEN_0 */
7700 { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
7701 },
7702 {
7703 /* VEX_W_0F93_P_0_LEN_0 */
7704 { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
7705 },
7706 {
7707 /* VEX_W_0F93_P_2_LEN_0 */
7708 { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
7709 },
7710 {
7711 /* VEX_W_0F98_P_0_LEN_0 */
7712 { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
7713 { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
7714 },
7715 {
7716 /* VEX_W_0F98_P_2_LEN_0 */
7717 { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
7718 { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
7719 },
7720 {
7721 /* VEX_W_0F99_P_0_LEN_0 */
7722 { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
7723 { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
7724 },
7725 {
7726 /* VEX_W_0F99_P_2_LEN_0 */
7727 { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
7728 { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
7729 },
7730 {
7731 /* VEX_W_0F380C */
7732 { "vpermilps", { XM, Vex, EXx }, PREFIX_DATA },
7733 },
7734 {
7735 /* VEX_W_0F380D */
7736 { "vpermilpd", { XM, Vex, EXx }, PREFIX_DATA },
7737 },
7738 {
7739 /* VEX_W_0F380E */
7740 { "vtestps", { XM, EXx }, PREFIX_DATA },
7741 },
7742 {
7743 /* VEX_W_0F380F */
7744 { "vtestpd", { XM, EXx }, PREFIX_DATA },
7745 },
7746 {
7747 /* VEX_W_0F3813 */
7748 { "vcvtph2ps", { XM, EXxmmq }, PREFIX_DATA },
7749 },
7750 {
7751 /* VEX_W_0F3816_L_1 */
7752 { "vpermps", { XM, Vex, EXx }, PREFIX_DATA },
7753 },
7754 {
7755 /* VEX_W_0F3818 */
7756 { "vbroadcastss", { XM, EXxmm_md }, PREFIX_DATA },
7757 },
7758 {
7759 /* VEX_W_0F3819_L_1 */
7760 { "vbroadcastsd", { XM, EXxmm_mq }, PREFIX_DATA },
7761 },
7762 {
7763 /* VEX_W_0F381A_M_0_L_1 */
7764 { "vbroadcastf128", { XM, Mxmm }, PREFIX_DATA },
7765 },
7766 {
7767 /* VEX_W_0F382C_M_0 */
7768 { "vmaskmovps", { XM, Vex, Mx }, PREFIX_DATA },
7769 },
7770 {
7771 /* VEX_W_0F382D_M_0 */
7772 { "vmaskmovpd", { XM, Vex, Mx }, PREFIX_DATA },
7773 },
7774 {
7775 /* VEX_W_0F382E_M_0 */
7776 { "vmaskmovps", { Mx, Vex, XM }, PREFIX_DATA },
7777 },
7778 {
7779 /* VEX_W_0F382F_M_0 */
7780 { "vmaskmovpd", { Mx, Vex, XM }, PREFIX_DATA },
7781 },
7782 {
7783 /* VEX_W_0F3836 */
7784 { "vpermd", { XM, Vex, EXx }, PREFIX_DATA },
7785 },
7786 {
7787 /* VEX_W_0F3846 */
7788 { "vpsravd", { XM, Vex, EXx }, PREFIX_DATA },
7789 },
7790 {
7791 /* VEX_W_0F3849_X86_64_P_0 */
7792 { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_0_W_0) },
7793 },
7794 {
7795 /* VEX_W_0F3849_X86_64_P_2 */
7796 { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_2_W_0) },
7797 },
7798 {
7799 /* VEX_W_0F3849_X86_64_P_3 */
7800 { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_3_W_0) },
7801 },
7802 {
7803 /* VEX_W_0F384B_X86_64_P_1 */
7804 { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_1_W_0) },
7805 },
7806 {
7807 /* VEX_W_0F384B_X86_64_P_2 */
7808 { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_2_W_0) },
7809 },
7810 {
7811 /* VEX_W_0F384B_X86_64_P_3 */
7812 { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_3_W_0) },
7813 },
7814 {
7815 /* VEX_W_0F3850 */
7816 { "%XV vpdpbusd", { XM, Vex, EXx }, 0 },
7817 },
7818 {
7819 /* VEX_W_0F3851 */
7820 { "%XV vpdpbusds", { XM, Vex, EXx }, 0 },
7821 },
7822 {
7823 /* VEX_W_0F3852 */
7824 { "%XV vpdpwssd", { XM, Vex, EXx }, 0 },
7825 },
7826 {
7827 /* VEX_W_0F3853 */
7828 { "%XV vpdpwssds", { XM, Vex, EXx }, 0 },
7829 },
7830 {
7831 /* VEX_W_0F3858 */
7832 { "vpbroadcastd", { XM, EXxmm_md }, PREFIX_DATA },
7833 },
7834 {
7835 /* VEX_W_0F3859 */
7836 { "vpbroadcastq", { XM, EXxmm_mq }, PREFIX_DATA },
7837 },
7838 {
7839 /* VEX_W_0F385A_M_0_L_0 */
7840 { "vbroadcasti128", { XM, Mxmm }, PREFIX_DATA },
7841 },
7842 {
7843 /* VEX_W_0F385C_X86_64_P_1 */
7844 { MOD_TABLE (MOD_VEX_0F385C_X86_64_P_1_W_0) },
7845 },
7846 {
7847 /* VEX_W_0F385E_X86_64_P_0 */
7848 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_0_W_0) },
7849 },
7850 {
7851 /* VEX_W_0F385E_X86_64_P_1 */
7852 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_1_W_0) },
7853 },
7854 {
7855 /* VEX_W_0F385E_X86_64_P_2 */
7856 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_2_W_0) },
7857 },
7858 {
7859 /* VEX_W_0F385E_X86_64_P_3 */
7860 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_3_W_0) },
7861 },
7862 {
7863 /* VEX_W_0F3878 */
7864 { "vpbroadcastb", { XM, EXxmm_mb }, PREFIX_DATA },
7865 },
7866 {
7867 /* VEX_W_0F3879 */
7868 { "vpbroadcastw", { XM, EXxmm_mw }, PREFIX_DATA },
7869 },
7870 {
7871 /* VEX_W_0F38CF */
7872 { "vgf2p8mulb", { XM, Vex, EXx }, PREFIX_DATA },
7873 },
7874 {
7875 /* VEX_W_0F3A00_L_1 */
7876 { Bad_Opcode },
7877 { "vpermq", { XM, EXx, Ib }, PREFIX_DATA },
7878 },
7879 {
7880 /* VEX_W_0F3A01_L_1 */
7881 { Bad_Opcode },
7882 { "vpermpd", { XM, EXx, Ib }, PREFIX_DATA },
7883 },
7884 {
7885 /* VEX_W_0F3A02 */
7886 { "vpblendd", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7887 },
7888 {
7889 /* VEX_W_0F3A04 */
7890 { "vpermilps", { XM, EXx, Ib }, PREFIX_DATA },
7891 },
7892 {
7893 /* VEX_W_0F3A05 */
7894 { "vpermilpd", { XM, EXx, Ib }, PREFIX_DATA },
7895 },
7896 {
7897 /* VEX_W_0F3A06_L_1 */
7898 { "vperm2f128", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7899 },
7900 {
7901 /* VEX_W_0F3A18_L_1 */
7902 { "vinsertf128", { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7903 },
7904 {
7905 /* VEX_W_0F3A19_L_1 */
7906 { "vextractf128", { EXxmm, XM, Ib }, PREFIX_DATA },
7907 },
7908 {
7909 /* VEX_W_0F3A1D */
7910 { "vcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, PREFIX_DATA },
7911 },
7912 {
7913 /* VEX_W_0F3A38_L_1 */
7914 { "vinserti128", { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7915 },
7916 {
7917 /* VEX_W_0F3A39_L_1 */
7918 { "vextracti128", { EXxmm, XM, Ib }, PREFIX_DATA },
7919 },
7920 {
7921 /* VEX_W_0F3A46_L_1 */
7922 { "vperm2i128", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7923 },
7924 {
7925 /* VEX_W_0F3A4A */
7926 { "vblendvps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7927 },
7928 {
7929 /* VEX_W_0F3A4B */
7930 { "vblendvpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7931 },
7932 {
7933 /* VEX_W_0F3A4C */
7934 { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7935 },
7936 {
7937 /* VEX_W_0F3ACE */
7938 { Bad_Opcode },
7939 { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7940 },
7941 {
7942 /* VEX_W_0F3ACF */
7943 { Bad_Opcode },
7944 { "vgf2p8affineinvqb", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7945 },
7946 /* VEX_W_0FXOP_08_85_L_0 */
7947 {
7948 { "vpmacssww", { XM, Vex, EXx, XMVexI4 }, 0 },
7949 },
7950 /* VEX_W_0FXOP_08_86_L_0 */
7951 {
7952 { "vpmacsswd", { XM, Vex, EXx, XMVexI4 }, 0 },
7953 },
7954 /* VEX_W_0FXOP_08_87_L_0 */
7955 {
7956 { "vpmacssdql", { XM, Vex, EXx, XMVexI4 }, 0 },
7957 },
7958 /* VEX_W_0FXOP_08_8E_L_0 */
7959 {
7960 { "vpmacssdd", { XM, Vex, EXx, XMVexI4 }, 0 },
7961 },
7962 /* VEX_W_0FXOP_08_8F_L_0 */
7963 {
7964 { "vpmacssdqh", { XM, Vex, EXx, XMVexI4 }, 0 },
7965 },
7966 /* VEX_W_0FXOP_08_95_L_0 */
7967 {
7968 { "vpmacsww", { XM, Vex, EXx, XMVexI4 }, 0 },
7969 },
7970 /* VEX_W_0FXOP_08_96_L_0 */
7971 {
7972 { "vpmacswd", { XM, Vex, EXx, XMVexI4 }, 0 },
7973 },
7974 /* VEX_W_0FXOP_08_97_L_0 */
7975 {
7976 { "vpmacsdql", { XM, Vex, EXx, XMVexI4 }, 0 },
7977 },
7978 /* VEX_W_0FXOP_08_9E_L_0 */
7979 {
7980 { "vpmacsdd", { XM, Vex, EXx, XMVexI4 }, 0 },
7981 },
7982 /* VEX_W_0FXOP_08_9F_L_0 */
7983 {
7984 { "vpmacsdqh", { XM, Vex, EXx, XMVexI4 }, 0 },
7985 },
7986 /* VEX_W_0FXOP_08_A6_L_0 */
7987 {
7988 { "vpmadcsswd", { XM, Vex, EXx, XMVexI4 }, 0 },
7989 },
7990 /* VEX_W_0FXOP_08_B6_L_0 */
7991 {
7992 { "vpmadcswd", { XM, Vex, EXx, XMVexI4 }, 0 },
7993 },
7994 /* VEX_W_0FXOP_08_C0_L_0 */
7995 {
7996 { "vprotb", { XM, EXx, Ib }, 0 },
7997 },
7998 /* VEX_W_0FXOP_08_C1_L_0 */
7999 {
8000 { "vprotw", { XM, EXx, Ib }, 0 },
8001 },
8002 /* VEX_W_0FXOP_08_C2_L_0 */
8003 {
8004 { "vprotd", { XM, EXx, Ib }, 0 },
8005 },
8006 /* VEX_W_0FXOP_08_C3_L_0 */
8007 {
8008 { "vprotq", { XM, EXx, Ib }, 0 },
8009 },
8010 /* VEX_W_0FXOP_08_CC_L_0 */
8011 {
8012 { "vpcomb", { XM, Vex, EXx, VPCOM }, 0 },
8013 },
8014 /* VEX_W_0FXOP_08_CD_L_0 */
8015 {
8016 { "vpcomw", { XM, Vex, EXx, VPCOM }, 0 },
8017 },
8018 /* VEX_W_0FXOP_08_CE_L_0 */
8019 {
8020 { "vpcomd", { XM, Vex, EXx, VPCOM }, 0 },
8021 },
8022 /* VEX_W_0FXOP_08_CF_L_0 */
8023 {
8024 { "vpcomq", { XM, Vex, EXx, VPCOM }, 0 },
8025 },
8026 /* VEX_W_0FXOP_08_EC_L_0 */
8027 {
8028 { "vpcomub", { XM, Vex, EXx, VPCOM }, 0 },
8029 },
8030 /* VEX_W_0FXOP_08_ED_L_0 */
8031 {
8032 { "vpcomuw", { XM, Vex, EXx, VPCOM }, 0 },
8033 },
8034 /* VEX_W_0FXOP_08_EE_L_0 */
8035 {
8036 { "vpcomud", { XM, Vex, EXx, VPCOM }, 0 },
8037 },
8038 /* VEX_W_0FXOP_08_EF_L_0 */
8039 {
8040 { "vpcomuq", { XM, Vex, EXx, VPCOM }, 0 },
8041 },
8042 /* VEX_W_0FXOP_09_80 */
8043 {
8044 { "vfrczps", { XM, EXx }, 0 },
8045 },
8046 /* VEX_W_0FXOP_09_81 */
8047 {
8048 { "vfrczpd", { XM, EXx }, 0 },
8049 },
8050 /* VEX_W_0FXOP_09_82 */
8051 {
8052 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_82_W_0) },
8053 },
8054 /* VEX_W_0FXOP_09_83 */
8055 {
8056 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_83_W_0) },
8057 },
8058 /* VEX_W_0FXOP_09_C1_L_0 */
8059 {
8060 { "vphaddbw", { XM, EXxmm }, 0 },
8061 },
8062 /* VEX_W_0FXOP_09_C2_L_0 */
8063 {
8064 { "vphaddbd", { XM, EXxmm }, 0 },
8065 },
8066 /* VEX_W_0FXOP_09_C3_L_0 */
8067 {
8068 { "vphaddbq", { XM, EXxmm }, 0 },
8069 },
8070 /* VEX_W_0FXOP_09_C6_L_0 */
8071 {
8072 { "vphaddwd", { XM, EXxmm }, 0 },
8073 },
8074 /* VEX_W_0FXOP_09_C7_L_0 */
8075 {
8076 { "vphaddwq", { XM, EXxmm }, 0 },
8077 },
8078 /* VEX_W_0FXOP_09_CB_L_0 */
8079 {
8080 { "vphadddq", { XM, EXxmm }, 0 },
8081 },
8082 /* VEX_W_0FXOP_09_D1_L_0 */
8083 {
8084 { "vphaddubw", { XM, EXxmm }, 0 },
8085 },
8086 /* VEX_W_0FXOP_09_D2_L_0 */
8087 {
8088 { "vphaddubd", { XM, EXxmm }, 0 },
8089 },
8090 /* VEX_W_0FXOP_09_D3_L_0 */
8091 {
8092 { "vphaddubq", { XM, EXxmm }, 0 },
8093 },
8094 /* VEX_W_0FXOP_09_D6_L_0 */
8095 {
8096 { "vphadduwd", { XM, EXxmm }, 0 },
8097 },
8098 /* VEX_W_0FXOP_09_D7_L_0 */
8099 {
8100 { "vphadduwq", { XM, EXxmm }, 0 },
8101 },
8102 /* VEX_W_0FXOP_09_DB_L_0 */
8103 {
8104 { "vphaddudq", { XM, EXxmm }, 0 },
8105 },
8106 /* VEX_W_0FXOP_09_E1_L_0 */
8107 {
8108 { "vphsubbw", { XM, EXxmm }, 0 },
8109 },
8110 /* VEX_W_0FXOP_09_E2_L_0 */
8111 {
8112 { "vphsubwd", { XM, EXxmm }, 0 },
8113 },
8114 /* VEX_W_0FXOP_09_E3_L_0 */
8115 {
8116 { "vphsubdq", { XM, EXxmm }, 0 },
8117 },
8118
8119 #include "i386-dis-evex-w.h"
8120 };
8121
8122 static const struct dis386 mod_table[][2] = {
8123 {
8124 /* MOD_8D */
8125 { "leaS", { Gv, M }, 0 },
8126 },
8127 {
8128 /* MOD_C6_REG_7 */
8129 { Bad_Opcode },
8130 { RM_TABLE (RM_C6_REG_7) },
8131 },
8132 {
8133 /* MOD_C7_REG_7 */
8134 { Bad_Opcode },
8135 { RM_TABLE (RM_C7_REG_7) },
8136 },
8137 {
8138 /* MOD_FF_REG_3 */
8139 { "{l|}call^", { indirEp }, 0 },
8140 },
8141 {
8142 /* MOD_FF_REG_5 */
8143 { "{l|}jmp^", { indirEp }, 0 },
8144 },
8145 {
8146 /* MOD_0F01_REG_0 */
8147 { X86_64_TABLE (X86_64_0F01_REG_0) },
8148 { RM_TABLE (RM_0F01_REG_0) },
8149 },
8150 {
8151 /* MOD_0F01_REG_1 */
8152 { X86_64_TABLE (X86_64_0F01_REG_1) },
8153 { RM_TABLE (RM_0F01_REG_1) },
8154 },
8155 {
8156 /* MOD_0F01_REG_2 */
8157 { X86_64_TABLE (X86_64_0F01_REG_2) },
8158 { RM_TABLE (RM_0F01_REG_2) },
8159 },
8160 {
8161 /* MOD_0F01_REG_3 */
8162 { X86_64_TABLE (X86_64_0F01_REG_3) },
8163 { RM_TABLE (RM_0F01_REG_3) },
8164 },
8165 {
8166 /* MOD_0F01_REG_5 */
8167 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) },
8168 { RM_TABLE (RM_0F01_REG_5_MOD_3) },
8169 },
8170 {
8171 /* MOD_0F01_REG_7 */
8172 { "invlpg", { Mb }, 0 },
8173 { RM_TABLE (RM_0F01_REG_7_MOD_3) },
8174 },
8175 {
8176 /* MOD_0F12_PREFIX_0 */
8177 { "movlpX", { XM, EXq }, 0 },
8178 { "movhlps", { XM, EXq }, 0 },
8179 },
8180 {
8181 /* MOD_0F12_PREFIX_2 */
8182 { "movlpX", { XM, EXq }, 0 },
8183 },
8184 {
8185 /* MOD_0F13 */
8186 { "movlpX", { EXq, XM }, PREFIX_OPCODE },
8187 },
8188 {
8189 /* MOD_0F16_PREFIX_0 */
8190 { "movhpX", { XM, EXq }, 0 },
8191 { "movlhps", { XM, EXq }, 0 },
8192 },
8193 {
8194 /* MOD_0F16_PREFIX_2 */
8195 { "movhpX", { XM, EXq }, 0 },
8196 },
8197 {
8198 /* MOD_0F17 */
8199 { "movhpX", { EXq, XM }, PREFIX_OPCODE },
8200 },
8201 {
8202 /* MOD_0F18_REG_0 */
8203 { "prefetchnta", { Mb }, 0 },
8204 },
8205 {
8206 /* MOD_0F18_REG_1 */
8207 { "prefetcht0", { Mb }, 0 },
8208 },
8209 {
8210 /* MOD_0F18_REG_2 */
8211 { "prefetcht1", { Mb }, 0 },
8212 },
8213 {
8214 /* MOD_0F18_REG_3 */
8215 { "prefetcht2", { Mb }, 0 },
8216 },
8217 {
8218 /* MOD_0F18_REG_4 */
8219 { "nop/reserved", { Mb }, 0 },
8220 },
8221 {
8222 /* MOD_0F18_REG_5 */
8223 { "nop/reserved", { Mb }, 0 },
8224 },
8225 {
8226 /* MOD_0F18_REG_6 */
8227 { "nop/reserved", { Mb }, 0 },
8228 },
8229 {
8230 /* MOD_0F18_REG_7 */
8231 { "nop/reserved", { Mb }, 0 },
8232 },
8233 {
8234 /* MOD_0F1A_PREFIX_0 */
8235 { "bndldx", { Gbnd, Mv_bnd }, 0 },
8236 { "nopQ", { Ev }, 0 },
8237 },
8238 {
8239 /* MOD_0F1B_PREFIX_0 */
8240 { "bndstx", { Mv_bnd, Gbnd }, 0 },
8241 { "nopQ", { Ev }, 0 },
8242 },
8243 {
8244 /* MOD_0F1B_PREFIX_1 */
8245 { "bndmk", { Gbnd, Mv_bnd }, 0 },
8246 { "nopQ", { Ev }, 0 },
8247 },
8248 {
8249 /* MOD_0F1C_PREFIX_0 */
8250 { REG_TABLE (REG_0F1C_P_0_MOD_0) },
8251 { "nopQ", { Ev }, 0 },
8252 },
8253 {
8254 /* MOD_0F1E_PREFIX_1 */
8255 { "nopQ", { Ev }, 0 },
8256 { REG_TABLE (REG_0F1E_P_1_MOD_3) },
8257 },
8258 {
8259 /* MOD_0F2B_PREFIX_0 */
8260 {"movntps", { Mx, XM }, PREFIX_OPCODE },
8261 },
8262 {
8263 /* MOD_0F2B_PREFIX_1 */
8264 {"movntss", { Md, XM }, PREFIX_OPCODE },
8265 },
8266 {
8267 /* MOD_0F2B_PREFIX_2 */
8268 {"movntpd", { Mx, XM }, PREFIX_OPCODE },
8269 },
8270 {
8271 /* MOD_0F2B_PREFIX_3 */
8272 {"movntsd", { Mq, XM }, PREFIX_OPCODE },
8273 },
8274 {
8275 /* MOD_0F50 */
8276 { Bad_Opcode },
8277 { "movmskpX", { Gdq, XS }, PREFIX_OPCODE },
8278 },
8279 {
8280 /* MOD_0F71_REG_2 */
8281 { Bad_Opcode },
8282 { "psrlw", { MS, Ib }, PREFIX_OPCODE },
8283 },
8284 {
8285 /* MOD_0F71_REG_4 */
8286 { Bad_Opcode },
8287 { "psraw", { MS, Ib }, PREFIX_OPCODE },
8288 },
8289 {
8290 /* MOD_0F71_REG_6 */
8291 { Bad_Opcode },
8292 { "psllw", { MS, Ib }, PREFIX_OPCODE },
8293 },
8294 {
8295 /* MOD_0F72_REG_2 */
8296 { Bad_Opcode },
8297 { "psrld", { MS, Ib }, PREFIX_OPCODE },
8298 },
8299 {
8300 /* MOD_0F72_REG_4 */
8301 { Bad_Opcode },
8302 { "psrad", { MS, Ib }, PREFIX_OPCODE },
8303 },
8304 {
8305 /* MOD_0F72_REG_6 */
8306 { Bad_Opcode },
8307 { "pslld", { MS, Ib }, PREFIX_OPCODE },
8308 },
8309 {
8310 /* MOD_0F73_REG_2 */
8311 { Bad_Opcode },
8312 { "psrlq", { MS, Ib }, PREFIX_OPCODE },
8313 },
8314 {
8315 /* MOD_0F73_REG_3 */
8316 { Bad_Opcode },
8317 { "psrldq", { XS, Ib }, PREFIX_DATA },
8318 },
8319 {
8320 /* MOD_0F73_REG_6 */
8321 { Bad_Opcode },
8322 { "psllq", { MS, Ib }, PREFIX_OPCODE },
8323 },
8324 {
8325 /* MOD_0F73_REG_7 */
8326 { Bad_Opcode },
8327 { "pslldq", { XS, Ib }, PREFIX_DATA },
8328 },
8329 {
8330 /* MOD_0FAE_REG_0 */
8331 { "fxsave", { FXSAVE }, 0 },
8332 { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) },
8333 },
8334 {
8335 /* MOD_0FAE_REG_1 */
8336 { "fxrstor", { FXSAVE }, 0 },
8337 { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) },
8338 },
8339 {
8340 /* MOD_0FAE_REG_2 */
8341 { "ldmxcsr", { Md }, 0 },
8342 { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) },
8343 },
8344 {
8345 /* MOD_0FAE_REG_3 */
8346 { "stmxcsr", { Md }, 0 },
8347 { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) },
8348 },
8349 {
8350 /* MOD_0FAE_REG_4 */
8351 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) },
8352 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) },
8353 },
8354 {
8355 /* MOD_0FAE_REG_5 */
8356 { "xrstor", { FXSAVE }, PREFIX_OPCODE },
8357 { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) },
8358 },
8359 {
8360 /* MOD_0FAE_REG_6 */
8361 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) },
8362 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) },
8363 },
8364 {
8365 /* MOD_0FAE_REG_7 */
8366 { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) },
8367 { RM_TABLE (RM_0FAE_REG_7_MOD_3) },
8368 },
8369 {
8370 /* MOD_0FB2 */
8371 { "lssS", { Gv, Mp }, 0 },
8372 },
8373 {
8374 /* MOD_0FB4 */
8375 { "lfsS", { Gv, Mp }, 0 },
8376 },
8377 {
8378 /* MOD_0FB5 */
8379 { "lgsS", { Gv, Mp }, 0 },
8380 },
8381 {
8382 /* MOD_0FC3 */
8383 { "movntiS", { Edq, Gdq }, PREFIX_OPCODE },
8384 },
8385 {
8386 /* MOD_0FC7_REG_3 */
8387 { "xrstors", { FXSAVE }, 0 },
8388 },
8389 {
8390 /* MOD_0FC7_REG_4 */
8391 { "xsavec", { FXSAVE }, 0 },
8392 },
8393 {
8394 /* MOD_0FC7_REG_5 */
8395 { "xsaves", { FXSAVE }, 0 },
8396 },
8397 {
8398 /* MOD_0FC7_REG_6 */
8399 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) },
8400 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) }
8401 },
8402 {
8403 /* MOD_0FC7_REG_7 */
8404 { "vmptrst", { Mq }, 0 },
8405 { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) }
8406 },
8407 {
8408 /* MOD_0FD7 */
8409 { Bad_Opcode },
8410 { "pmovmskb", { Gdq, MS }, 0 },
8411 },
8412 {
8413 /* MOD_0FE7_PREFIX_2 */
8414 { "movntdq", { Mx, XM }, 0 },
8415 },
8416 {
8417 /* MOD_0FF0_PREFIX_3 */
8418 { "lddqu", { XM, M }, 0 },
8419 },
8420 {
8421 /* MOD_0F382A */
8422 { "movntdqa", { XM, Mx }, PREFIX_DATA },
8423 },
8424 {
8425 /* MOD_0F38DC_PREFIX_1 */
8426 { "aesenc128kl", { XM, M }, 0 },
8427 { "loadiwkey", { XM, EXx }, 0 },
8428 },
8429 {
8430 /* MOD_0F38DD_PREFIX_1 */
8431 { "aesdec128kl", { XM, M }, 0 },
8432 },
8433 {
8434 /* MOD_0F38DE_PREFIX_1 */
8435 { "aesenc256kl", { XM, M }, 0 },
8436 },
8437 {
8438 /* MOD_0F38DF_PREFIX_1 */
8439 { "aesdec256kl", { XM, M }, 0 },
8440 },
8441 {
8442 /* MOD_0F38F5 */
8443 { "wrussK", { M, Gdq }, PREFIX_DATA },
8444 },
8445 {
8446 /* MOD_0F38F6_PREFIX_0 */
8447 { "wrssK", { M, Gdq }, PREFIX_OPCODE },
8448 },
8449 {
8450 /* MOD_0F38F8_PREFIX_1 */
8451 { "enqcmds", { Gva, M }, PREFIX_OPCODE },
8452 },
8453 {
8454 /* MOD_0F38F8_PREFIX_2 */
8455 { "movdir64b", { Gva, M }, PREFIX_OPCODE },
8456 },
8457 {
8458 /* MOD_0F38F8_PREFIX_3 */
8459 { "enqcmd", { Gva, M }, PREFIX_OPCODE },
8460 },
8461 {
8462 /* MOD_0F38F9 */
8463 { "movdiri", { Edq, Gdq }, PREFIX_OPCODE },
8464 },
8465 {
8466 /* MOD_0F38FA_PREFIX_1 */
8467 { Bad_Opcode },
8468 { "encodekey128", { Gd, Ed }, 0 },
8469 },
8470 {
8471 /* MOD_0F38FB_PREFIX_1 */
8472 { Bad_Opcode },
8473 { "encodekey256", { Gd, Ed }, 0 },
8474 },
8475 {
8476 /* MOD_0F3A0F_PREFIX_1 */
8477 { Bad_Opcode },
8478 { REG_TABLE (REG_0F3A0F_PREFIX_1_MOD_3) },
8479 },
8480 {
8481 /* MOD_62_32BIT */
8482 { "bound{S|}", { Gv, Ma }, 0 },
8483 { EVEX_TABLE (EVEX_0F) },
8484 },
8485 {
8486 /* MOD_C4_32BIT */
8487 { "lesS", { Gv, Mp }, 0 },
8488 { VEX_C4_TABLE (VEX_0F) },
8489 },
8490 {
8491 /* MOD_C5_32BIT */
8492 { "ldsS", { Gv, Mp }, 0 },
8493 { VEX_C5_TABLE (VEX_0F) },
8494 },
8495 {
8496 /* MOD_VEX_0F12_PREFIX_0 */
8497 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
8498 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
8499 },
8500 {
8501 /* MOD_VEX_0F12_PREFIX_2 */
8502 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0) },
8503 },
8504 {
8505 /* MOD_VEX_0F13 */
8506 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
8507 },
8508 {
8509 /* MOD_VEX_0F16_PREFIX_0 */
8510 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
8511 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
8512 },
8513 {
8514 /* MOD_VEX_0F16_PREFIX_2 */
8515 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0) },
8516 },
8517 {
8518 /* MOD_VEX_0F17 */
8519 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
8520 },
8521 {
8522 /* MOD_VEX_0F2B */
8523 { "vmovntpX", { Mx, XM }, PREFIX_OPCODE },
8524 },
8525 {
8526 /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
8527 { Bad_Opcode },
8528 { "kandw", { MaskG, MaskVex, MaskE }, 0 },
8529 },
8530 {
8531 /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
8532 { Bad_Opcode },
8533 { "kandq", { MaskG, MaskVex, MaskE }, 0 },
8534 },
8535 {
8536 /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
8537 { Bad_Opcode },
8538 { "kandb", { MaskG, MaskVex, MaskE }, 0 },
8539 },
8540 {
8541 /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
8542 { Bad_Opcode },
8543 { "kandd", { MaskG, MaskVex, MaskE }, 0 },
8544 },
8545 {
8546 /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
8547 { Bad_Opcode },
8548 { "kandnw", { MaskG, MaskVex, MaskE }, 0 },
8549 },
8550 {
8551 /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
8552 { Bad_Opcode },
8553 { "kandnq", { MaskG, MaskVex, MaskE }, 0 },
8554 },
8555 {
8556 /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
8557 { Bad_Opcode },
8558 { "kandnb", { MaskG, MaskVex, MaskE }, 0 },
8559 },
8560 {
8561 /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
8562 { Bad_Opcode },
8563 { "kandnd", { MaskG, MaskVex, MaskE }, 0 },
8564 },
8565 {
8566 /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
8567 { Bad_Opcode },
8568 { "knotw", { MaskG, MaskE }, 0 },
8569 },
8570 {
8571 /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
8572 { Bad_Opcode },
8573 { "knotq", { MaskG, MaskE }, 0 },
8574 },
8575 {
8576 /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
8577 { Bad_Opcode },
8578 { "knotb", { MaskG, MaskE }, 0 },
8579 },
8580 {
8581 /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
8582 { Bad_Opcode },
8583 { "knotd", { MaskG, MaskE }, 0 },
8584 },
8585 {
8586 /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
8587 { Bad_Opcode },
8588 { "korw", { MaskG, MaskVex, MaskE }, 0 },
8589 },
8590 {
8591 /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
8592 { Bad_Opcode },
8593 { "korq", { MaskG, MaskVex, MaskE }, 0 },
8594 },
8595 {
8596 /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
8597 { Bad_Opcode },
8598 { "korb", { MaskG, MaskVex, MaskE }, 0 },
8599 },
8600 {
8601 /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
8602 { Bad_Opcode },
8603 { "kord", { MaskG, MaskVex, MaskE }, 0 },
8604 },
8605 {
8606 /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
8607 { Bad_Opcode },
8608 { "kxnorw", { MaskG, MaskVex, MaskE }, 0 },
8609 },
8610 {
8611 /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
8612 { Bad_Opcode },
8613 { "kxnorq", { MaskG, MaskVex, MaskE }, 0 },
8614 },
8615 {
8616 /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
8617 { Bad_Opcode },
8618 { "kxnorb", { MaskG, MaskVex, MaskE }, 0 },
8619 },
8620 {
8621 /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
8622 { Bad_Opcode },
8623 { "kxnord", { MaskG, MaskVex, MaskE }, 0 },
8624 },
8625 {
8626 /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
8627 { Bad_Opcode },
8628 { "kxorw", { MaskG, MaskVex, MaskE }, 0 },
8629 },
8630 {
8631 /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
8632 { Bad_Opcode },
8633 { "kxorq", { MaskG, MaskVex, MaskE }, 0 },
8634 },
8635 {
8636 /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
8637 { Bad_Opcode },
8638 { "kxorb", { MaskG, MaskVex, MaskE }, 0 },
8639 },
8640 {
8641 /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
8642 { Bad_Opcode },
8643 { "kxord", { MaskG, MaskVex, MaskE }, 0 },
8644 },
8645 {
8646 /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
8647 { Bad_Opcode },
8648 { "kaddw", { MaskG, MaskVex, MaskE }, 0 },
8649 },
8650 {
8651 /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
8652 { Bad_Opcode },
8653 { "kaddq", { MaskG, MaskVex, MaskE }, 0 },
8654 },
8655 {
8656 /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
8657 { Bad_Opcode },
8658 { "kaddb", { MaskG, MaskVex, MaskE }, 0 },
8659 },
8660 {
8661 /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
8662 { Bad_Opcode },
8663 { "kaddd", { MaskG, MaskVex, MaskE }, 0 },
8664 },
8665 {
8666 /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
8667 { Bad_Opcode },
8668 { "kunpckwd", { MaskG, MaskVex, MaskE }, 0 },
8669 },
8670 {
8671 /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
8672 { Bad_Opcode },
8673 { "kunpckdq", { MaskG, MaskVex, MaskE }, 0 },
8674 },
8675 {
8676 /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
8677 { Bad_Opcode },
8678 { "kunpckbw", { MaskG, MaskVex, MaskE }, 0 },
8679 },
8680 {
8681 /* MOD_VEX_0F50 */
8682 { Bad_Opcode },
8683 { "vmovmskpX", { Gdq, XS }, PREFIX_OPCODE },
8684 },
8685 {
8686 /* MOD_VEX_0F71_REG_2 */
8687 { Bad_Opcode },
8688 { "vpsrlw", { Vex, XS, Ib }, PREFIX_DATA },
8689 },
8690 {
8691 /* MOD_VEX_0F71_REG_4 */
8692 { Bad_Opcode },
8693 { "vpsraw", { Vex, XS, Ib }, PREFIX_DATA },
8694 },
8695 {
8696 /* MOD_VEX_0F71_REG_6 */
8697 { Bad_Opcode },
8698 { "vpsllw", { Vex, XS, Ib }, PREFIX_DATA },
8699 },
8700 {
8701 /* MOD_VEX_0F72_REG_2 */
8702 { Bad_Opcode },
8703 { "vpsrld", { Vex, XS, Ib }, PREFIX_DATA },
8704 },
8705 {
8706 /* MOD_VEX_0F72_REG_4 */
8707 { Bad_Opcode },
8708 { "vpsrad", { Vex, XS, Ib }, PREFIX_DATA },
8709 },
8710 {
8711 /* MOD_VEX_0F72_REG_6 */
8712 { Bad_Opcode },
8713 { "vpslld", { Vex, XS, Ib }, PREFIX_DATA },
8714 },
8715 {
8716 /* MOD_VEX_0F73_REG_2 */
8717 { Bad_Opcode },
8718 { "vpsrlq", { Vex, XS, Ib }, PREFIX_DATA },
8719 },
8720 {
8721 /* MOD_VEX_0F73_REG_3 */
8722 { Bad_Opcode },
8723 { "vpsrldq", { Vex, XS, Ib }, PREFIX_DATA },
8724 },
8725 {
8726 /* MOD_VEX_0F73_REG_6 */
8727 { Bad_Opcode },
8728 { "vpsllq", { Vex, XS, Ib }, PREFIX_DATA },
8729 },
8730 {
8731 /* MOD_VEX_0F73_REG_7 */
8732 { Bad_Opcode },
8733 { "vpslldq", { Vex, XS, Ib }, PREFIX_DATA },
8734 },
8735 {
8736 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
8737 { "kmovw", { Ew, MaskG }, 0 },
8738 { Bad_Opcode },
8739 },
8740 {
8741 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
8742 { "kmovq", { Eq, MaskG }, 0 },
8743 { Bad_Opcode },
8744 },
8745 {
8746 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
8747 { "kmovb", { Eb, MaskG }, 0 },
8748 { Bad_Opcode },
8749 },
8750 {
8751 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
8752 { "kmovd", { Ed, MaskG }, 0 },
8753 { Bad_Opcode },
8754 },
8755 {
8756 /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
8757 { Bad_Opcode },
8758 { "kmovw", { MaskG, Edq }, 0 },
8759 },
8760 {
8761 /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
8762 { Bad_Opcode },
8763 { "kmovb", { MaskG, Edq }, 0 },
8764 },
8765 {
8766 /* MOD_VEX_0F92_P_3_LEN_0 */
8767 { Bad_Opcode },
8768 { "kmovK", { MaskG, Edq }, 0 },
8769 },
8770 {
8771 /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
8772 { Bad_Opcode },
8773 { "kmovw", { Gdq, MaskE }, 0 },
8774 },
8775 {
8776 /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
8777 { Bad_Opcode },
8778 { "kmovb", { Gdq, MaskE }, 0 },
8779 },
8780 {
8781 /* MOD_VEX_0F93_P_3_LEN_0 */
8782 { Bad_Opcode },
8783 { "kmovK", { Gdq, MaskE }, 0 },
8784 },
8785 {
8786 /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
8787 { Bad_Opcode },
8788 { "kortestw", { MaskG, MaskE }, 0 },
8789 },
8790 {
8791 /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
8792 { Bad_Opcode },
8793 { "kortestq", { MaskG, MaskE }, 0 },
8794 },
8795 {
8796 /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
8797 { Bad_Opcode },
8798 { "kortestb", { MaskG, MaskE }, 0 },
8799 },
8800 {
8801 /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
8802 { Bad_Opcode },
8803 { "kortestd", { MaskG, MaskE }, 0 },
8804 },
8805 {
8806 /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
8807 { Bad_Opcode },
8808 { "ktestw", { MaskG, MaskE }, 0 },
8809 },
8810 {
8811 /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
8812 { Bad_Opcode },
8813 { "ktestq", { MaskG, MaskE }, 0 },
8814 },
8815 {
8816 /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
8817 { Bad_Opcode },
8818 { "ktestb", { MaskG, MaskE }, 0 },
8819 },
8820 {
8821 /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
8822 { Bad_Opcode },
8823 { "ktestd", { MaskG, MaskE }, 0 },
8824 },
8825 {
8826 /* MOD_VEX_0FAE_REG_2 */
8827 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
8828 },
8829 {
8830 /* MOD_VEX_0FAE_REG_3 */
8831 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
8832 },
8833 {
8834 /* MOD_VEX_0FD7 */
8835 { Bad_Opcode },
8836 { "vpmovmskb", { Gdq, XS }, PREFIX_DATA },
8837 },
8838 {
8839 /* MOD_VEX_0FE7 */
8840 { "vmovntdq", { Mx, XM }, PREFIX_DATA },
8841 },
8842 {
8843 /* MOD_VEX_0FF0_PREFIX_3 */
8844 { "vlddqu", { XM, M }, 0 },
8845 },
8846 {
8847 /* MOD_VEX_0F381A */
8848 { VEX_LEN_TABLE (VEX_LEN_0F381A_M_0) },
8849 },
8850 {
8851 /* MOD_VEX_0F382A */
8852 { "vmovntdqa", { XM, Mx }, PREFIX_DATA },
8853 },
8854 {
8855 /* MOD_VEX_0F382C */
8856 { VEX_W_TABLE (VEX_W_0F382C_M_0) },
8857 },
8858 {
8859 /* MOD_VEX_0F382D */
8860 { VEX_W_TABLE (VEX_W_0F382D_M_0) },
8861 },
8862 {
8863 /* MOD_VEX_0F382E */
8864 { VEX_W_TABLE (VEX_W_0F382E_M_0) },
8865 },
8866 {
8867 /* MOD_VEX_0F382F */
8868 { VEX_W_TABLE (VEX_W_0F382F_M_0) },
8869 },
8870 {
8871 /* MOD_VEX_0F3849_X86_64_P_0_W_0 */
8872 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0) },
8873 { REG_TABLE (REG_VEX_0F3849_X86_64_P_0_W_0_M_1) },
8874 },
8875 {
8876 /* MOD_VEX_0F3849_X86_64_P_2_W_0 */
8877 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0) },
8878 },
8879 {
8880 /* MOD_VEX_0F3849_X86_64_P_3_W_0 */
8881 { Bad_Opcode },
8882 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0) },
8883 },
8884 {
8885 /* MOD_VEX_0F384B_X86_64_P_1_W_0 */
8886 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0) },
8887 },
8888 {
8889 /* MOD_VEX_0F384B_X86_64_P_2_W_0 */
8890 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0) },
8891 },
8892 {
8893 /* MOD_VEX_0F384B_X86_64_P_3_W_0 */
8894 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0) },
8895 },
8896 {
8897 /* MOD_VEX_0F385A */
8898 { VEX_LEN_TABLE (VEX_LEN_0F385A_M_0) },
8899 },
8900 {
8901 /* MOD_VEX_0F385C_X86_64_P_1_W_0 */
8902 { Bad_Opcode },
8903 { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0) },
8904 },
8905 {
8906 /* MOD_VEX_0F385E_X86_64_P_0_W_0 */
8907 { Bad_Opcode },
8908 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0) },
8909 },
8910 {
8911 /* MOD_VEX_0F385E_X86_64_P_1_W_0 */
8912 { Bad_Opcode },
8913 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0) },
8914 },
8915 {
8916 /* MOD_VEX_0F385E_X86_64_P_2_W_0 */
8917 { Bad_Opcode },
8918 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0) },
8919 },
8920 {
8921 /* MOD_VEX_0F385E_X86_64_P_3_W_0 */
8922 { Bad_Opcode },
8923 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0) },
8924 },
8925 {
8926 /* MOD_VEX_0F388C */
8927 { "vpmaskmov%DQ", { XM, Vex, Mx }, PREFIX_DATA },
8928 },
8929 {
8930 /* MOD_VEX_0F388E */
8931 { "vpmaskmov%DQ", { Mx, Vex, XM }, PREFIX_DATA },
8932 },
8933 {
8934 /* MOD_VEX_0F3A30_L_0 */
8935 { Bad_Opcode },
8936 { "kshiftr%BW", { MaskG, MaskE, Ib }, PREFIX_DATA },
8937 },
8938 {
8939 /* MOD_VEX_0F3A31_L_0 */
8940 { Bad_Opcode },
8941 { "kshiftr%DQ", { MaskG, MaskE, Ib }, PREFIX_DATA },
8942 },
8943 {
8944 /* MOD_VEX_0F3A32_L_0 */
8945 { Bad_Opcode },
8946 { "kshiftl%BW", { MaskG, MaskE, Ib }, PREFIX_DATA },
8947 },
8948 {
8949 /* MOD_VEX_0F3A33_L_0 */
8950 { Bad_Opcode },
8951 { "kshiftl%DQ", { MaskG, MaskE, Ib }, PREFIX_DATA },
8952 },
8953 {
8954 /* MOD_VEX_0FXOP_09_12 */
8955 { Bad_Opcode },
8956 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_12_M_1) },
8957 },
8958
8959 #include "i386-dis-evex-mod.h"
8960 };
8961
8962 static const struct dis386 rm_table[][8] = {
8963 {
8964 /* RM_C6_REG_7 */
8965 { "xabort", { Skip_MODRM, Ib }, 0 },
8966 },
8967 {
8968 /* RM_C7_REG_7 */
8969 { "xbeginT", { Skip_MODRM, Jdqw }, 0 },
8970 },
8971 {
8972 /* RM_0F01_REG_0 */
8973 { "enclv", { Skip_MODRM }, 0 },
8974 { "vmcall", { Skip_MODRM }, 0 },
8975 { "vmlaunch", { Skip_MODRM }, 0 },
8976 { "vmresume", { Skip_MODRM }, 0 },
8977 { "vmxoff", { Skip_MODRM }, 0 },
8978 { "pconfig", { Skip_MODRM }, 0 },
8979 },
8980 {
8981 /* RM_0F01_REG_1 */
8982 { "monitor", { { OP_Monitor, 0 } }, 0 },
8983 { "mwait", { { OP_Mwait, 0 } }, 0 },
8984 { "clac", { Skip_MODRM }, 0 },
8985 { "stac", { Skip_MODRM }, 0 },
8986 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_4) },
8987 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_5) },
8988 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_6) },
8989 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_7) },
8990 },
8991 {
8992 /* RM_0F01_REG_2 */
8993 { "xgetbv", { Skip_MODRM }, 0 },
8994 { "xsetbv", { Skip_MODRM }, 0 },
8995 { Bad_Opcode },
8996 { Bad_Opcode },
8997 { "vmfunc", { Skip_MODRM }, 0 },
8998 { "xend", { Skip_MODRM }, 0 },
8999 { "xtest", { Skip_MODRM }, 0 },
9000 { "enclu", { Skip_MODRM }, 0 },
9001 },
9002 {
9003 /* RM_0F01_REG_3 */
9004 { "vmrun", { Skip_MODRM }, 0 },
9005 { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) },
9006 { "vmload", { Skip_MODRM }, 0 },
9007 { "vmsave", { Skip_MODRM }, 0 },
9008 { "stgi", { Skip_MODRM }, 0 },
9009 { "clgi", { Skip_MODRM }, 0 },
9010 { "skinit", { Skip_MODRM }, 0 },
9011 { "invlpga", { Skip_MODRM }, 0 },
9012 },
9013 {
9014 /* RM_0F01_REG_5_MOD_3 */
9015 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) },
9016 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) },
9017 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) },
9018 { Bad_Opcode },
9019 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_4) },
9020 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_5) },
9021 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_6) },
9022 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_7) },
9023 },
9024 {
9025 /* RM_0F01_REG_7_MOD_3 */
9026 { "swapgs", { Skip_MODRM }, 0 },
9027 { "rdtscp", { Skip_MODRM }, 0 },
9028 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) },
9029 { "mwaitx", { { OP_Mwait, eBX_reg } }, PREFIX_OPCODE },
9030 { "clzero", { Skip_MODRM }, 0 },
9031 { "rdpru", { Skip_MODRM }, 0 },
9032 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_6) },
9033 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_7) },
9034 },
9035 {
9036 /* RM_0F1E_P_1_MOD_3_REG_7 */
9037 { "nopQ", { Ev }, 0 },
9038 { "nopQ", { Ev }, 0 },
9039 { "endbr64", { Skip_MODRM }, PREFIX_OPCODE },
9040 { "endbr32", { Skip_MODRM }, PREFIX_OPCODE },
9041 { "nopQ", { Ev }, 0 },
9042 { "nopQ", { Ev }, 0 },
9043 { "nopQ", { Ev }, 0 },
9044 { "nopQ", { Ev }, 0 },
9045 },
9046 {
9047 /* RM_0F3A0F_P_1_MOD_3_REG_0 */
9048 { "hreset", { Skip_MODRM, Ib }, 0 },
9049 },
9050 {
9051 /* RM_0FAE_REG_6_MOD_3 */
9052 { "mfence", { Skip_MODRM }, 0 },
9053 },
9054 {
9055 /* RM_0FAE_REG_7_MOD_3 */
9056 { "sfence", { Skip_MODRM }, 0 },
9057
9058 },
9059 {
9060 /* RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0 */
9061 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0) },
9062 },
9063 };
9064
9065 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
9066
9067 /* We use the high bit to indicate different name for the same
9068 prefix. */
9069 #define REP_PREFIX (0xf3 | 0x100)
9070 #define XACQUIRE_PREFIX (0xf2 | 0x200)
9071 #define XRELEASE_PREFIX (0xf3 | 0x400)
9072 #define BND_PREFIX (0xf2 | 0x400)
9073 #define NOTRACK_PREFIX (0x3e | 0x100)
9074
9075 /* Remember if the current op is a jump instruction. */
9076 static bfd_boolean op_is_jump = FALSE;
9077
9078 static int
9079 ckprefix (void)
9080 {
9081 int newrex, i, length;
9082 rex = 0;
9083 prefixes = 0;
9084 used_prefixes = 0;
9085 rex_used = 0;
9086 last_lock_prefix = -1;
9087 last_repz_prefix = -1;
9088 last_repnz_prefix = -1;
9089 last_data_prefix = -1;
9090 last_addr_prefix = -1;
9091 last_rex_prefix = -1;
9092 last_seg_prefix = -1;
9093 fwait_prefix = -1;
9094 active_seg_prefix = 0;
9095 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
9096 all_prefixes[i] = 0;
9097 i = 0;
9098 length = 0;
9099 /* The maximum instruction length is 15bytes. */
9100 while (length < MAX_CODE_LENGTH - 1)
9101 {
9102 FETCH_DATA (the_info, codep + 1);
9103 newrex = 0;
9104 switch (*codep)
9105 {
9106 /* REX prefixes family. */
9107 case 0x40:
9108 case 0x41:
9109 case 0x42:
9110 case 0x43:
9111 case 0x44:
9112 case 0x45:
9113 case 0x46:
9114 case 0x47:
9115 case 0x48:
9116 case 0x49:
9117 case 0x4a:
9118 case 0x4b:
9119 case 0x4c:
9120 case 0x4d:
9121 case 0x4e:
9122 case 0x4f:
9123 if (address_mode == mode_64bit)
9124 newrex = *codep;
9125 else
9126 return 1;
9127 last_rex_prefix = i;
9128 break;
9129 case 0xf3:
9130 prefixes |= PREFIX_REPZ;
9131 last_repz_prefix = i;
9132 break;
9133 case 0xf2:
9134 prefixes |= PREFIX_REPNZ;
9135 last_repnz_prefix = i;
9136 break;
9137 case 0xf0:
9138 prefixes |= PREFIX_LOCK;
9139 last_lock_prefix = i;
9140 break;
9141 case 0x2e:
9142 prefixes |= PREFIX_CS;
9143 last_seg_prefix = i;
9144 active_seg_prefix = PREFIX_CS;
9145 break;
9146 case 0x36:
9147 prefixes |= PREFIX_SS;
9148 last_seg_prefix = i;
9149 active_seg_prefix = PREFIX_SS;
9150 break;
9151 case 0x3e:
9152 prefixes |= PREFIX_DS;
9153 last_seg_prefix = i;
9154 active_seg_prefix = PREFIX_DS;
9155 break;
9156 case 0x26:
9157 prefixes |= PREFIX_ES;
9158 last_seg_prefix = i;
9159 active_seg_prefix = PREFIX_ES;
9160 break;
9161 case 0x64:
9162 prefixes |= PREFIX_FS;
9163 last_seg_prefix = i;
9164 active_seg_prefix = PREFIX_FS;
9165 break;
9166 case 0x65:
9167 prefixes |= PREFIX_GS;
9168 last_seg_prefix = i;
9169 active_seg_prefix = PREFIX_GS;
9170 break;
9171 case 0x66:
9172 prefixes |= PREFIX_DATA;
9173 last_data_prefix = i;
9174 break;
9175 case 0x67:
9176 prefixes |= PREFIX_ADDR;
9177 last_addr_prefix = i;
9178 break;
9179 case FWAIT_OPCODE:
9180 /* fwait is really an instruction. If there are prefixes
9181 before the fwait, they belong to the fwait, *not* to the
9182 following instruction. */
9183 fwait_prefix = i;
9184 if (prefixes || rex)
9185 {
9186 prefixes |= PREFIX_FWAIT;
9187 codep++;
9188 /* This ensures that the previous REX prefixes are noticed
9189 as unused prefixes, as in the return case below. */
9190 rex_used = rex;
9191 return 1;
9192 }
9193 prefixes = PREFIX_FWAIT;
9194 break;
9195 default:
9196 return 1;
9197 }
9198 /* Rex is ignored when followed by another prefix. */
9199 if (rex)
9200 {
9201 rex_used = rex;
9202 return 1;
9203 }
9204 if (*codep != FWAIT_OPCODE)
9205 all_prefixes[i++] = *codep;
9206 rex = newrex;
9207 codep++;
9208 length++;
9209 }
9210 return 0;
9211 }
9212
9213 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
9214 prefix byte. */
9215
9216 static const char *
9217 prefix_name (int pref, int sizeflag)
9218 {
9219 static const char *rexes [16] =
9220 {
9221 "rex", /* 0x40 */
9222 "rex.B", /* 0x41 */
9223 "rex.X", /* 0x42 */
9224 "rex.XB", /* 0x43 */
9225 "rex.R", /* 0x44 */
9226 "rex.RB", /* 0x45 */
9227 "rex.RX", /* 0x46 */
9228 "rex.RXB", /* 0x47 */
9229 "rex.W", /* 0x48 */
9230 "rex.WB", /* 0x49 */
9231 "rex.WX", /* 0x4a */
9232 "rex.WXB", /* 0x4b */
9233 "rex.WR", /* 0x4c */
9234 "rex.WRB", /* 0x4d */
9235 "rex.WRX", /* 0x4e */
9236 "rex.WRXB", /* 0x4f */
9237 };
9238
9239 switch (pref)
9240 {
9241 /* REX prefixes family. */
9242 case 0x40:
9243 case 0x41:
9244 case 0x42:
9245 case 0x43:
9246 case 0x44:
9247 case 0x45:
9248 case 0x46:
9249 case 0x47:
9250 case 0x48:
9251 case 0x49:
9252 case 0x4a:
9253 case 0x4b:
9254 case 0x4c:
9255 case 0x4d:
9256 case 0x4e:
9257 case 0x4f:
9258 return rexes [pref - 0x40];
9259 case 0xf3:
9260 return "repz";
9261 case 0xf2:
9262 return "repnz";
9263 case 0xf0:
9264 return "lock";
9265 case 0x2e:
9266 return "cs";
9267 case 0x36:
9268 return "ss";
9269 case 0x3e:
9270 return "ds";
9271 case 0x26:
9272 return "es";
9273 case 0x64:
9274 return "fs";
9275 case 0x65:
9276 return "gs";
9277 case 0x66:
9278 return (sizeflag & DFLAG) ? "data16" : "data32";
9279 case 0x67:
9280 if (address_mode == mode_64bit)
9281 return (sizeflag & AFLAG) ? "addr32" : "addr64";
9282 else
9283 return (sizeflag & AFLAG) ? "addr16" : "addr32";
9284 case FWAIT_OPCODE:
9285 return "fwait";
9286 case REP_PREFIX:
9287 return "rep";
9288 case XACQUIRE_PREFIX:
9289 return "xacquire";
9290 case XRELEASE_PREFIX:
9291 return "xrelease";
9292 case BND_PREFIX:
9293 return "bnd";
9294 case NOTRACK_PREFIX:
9295 return "notrack";
9296 default:
9297 return NULL;
9298 }
9299 }
9300
9301 static char op_out[MAX_OPERANDS][100];
9302 static int op_ad, op_index[MAX_OPERANDS];
9303 static int two_source_ops;
9304 static bfd_vma op_address[MAX_OPERANDS];
9305 static bfd_vma op_riprel[MAX_OPERANDS];
9306 static bfd_vma start_pc;
9307
9308 /*
9309 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
9310 * (see topic "Redundant prefixes" in the "Differences from 8086"
9311 * section of the "Virtual 8086 Mode" chapter.)
9312 * 'pc' should be the address of this instruction, it will
9313 * be used to print the target address if this is a relative jump or call
9314 * The function returns the length of this instruction in bytes.
9315 */
9316
9317 static char intel_syntax;
9318 static char intel_mnemonic = !SYSV386_COMPAT;
9319 static char open_char;
9320 static char close_char;
9321 static char separator_char;
9322 static char scale_char;
9323
9324 enum x86_64_isa
9325 {
9326 amd64 = 1,
9327 intel64
9328 };
9329
9330 static enum x86_64_isa isa64;
9331
9332 /* Here for backwards compatibility. When gdb stops using
9333 print_insn_i386_att and print_insn_i386_intel these functions can
9334 disappear, and print_insn_i386 be merged into print_insn. */
9335 int
9336 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
9337 {
9338 intel_syntax = 0;
9339
9340 return print_insn (pc, info);
9341 }
9342
9343 int
9344 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
9345 {
9346 intel_syntax = 1;
9347
9348 return print_insn (pc, info);
9349 }
9350
9351 int
9352 print_insn_i386 (bfd_vma pc, disassemble_info *info)
9353 {
9354 intel_syntax = -1;
9355
9356 return print_insn (pc, info);
9357 }
9358
9359 void
9360 print_i386_disassembler_options (FILE *stream)
9361 {
9362 fprintf (stream, _("\n\
9363 The following i386/x86-64 specific disassembler options are supported for use\n\
9364 with the -M switch (multiple options should be separated by commas):\n"));
9365
9366 fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n"));
9367 fprintf (stream, _(" i386 Disassemble in 32bit mode\n"));
9368 fprintf (stream, _(" i8086 Disassemble in 16bit mode\n"));
9369 fprintf (stream, _(" att Display instruction in AT&T syntax\n"));
9370 fprintf (stream, _(" intel Display instruction in Intel syntax\n"));
9371 fprintf (stream, _(" att-mnemonic\n"
9372 " Display instruction in AT&T mnemonic\n"));
9373 fprintf (stream, _(" intel-mnemonic\n"
9374 " Display instruction in Intel mnemonic\n"));
9375 fprintf (stream, _(" addr64 Assume 64bit address size\n"));
9376 fprintf (stream, _(" addr32 Assume 32bit address size\n"));
9377 fprintf (stream, _(" addr16 Assume 16bit address size\n"));
9378 fprintf (stream, _(" data32 Assume 32bit data size\n"));
9379 fprintf (stream, _(" data16 Assume 16bit data size\n"));
9380 fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n"));
9381 fprintf (stream, _(" amd64 Display instruction in AMD64 ISA\n"));
9382 fprintf (stream, _(" intel64 Display instruction in Intel64 ISA\n"));
9383 }
9384
9385 /* Bad opcode. */
9386 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
9387
9388 /* Get a pointer to struct dis386 with a valid name. */
9389
9390 static const struct dis386 *
9391 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
9392 {
9393 int vindex, vex_table_index;
9394
9395 if (dp->name != NULL)
9396 return dp;
9397
9398 switch (dp->op[0].bytemode)
9399 {
9400 case USE_REG_TABLE:
9401 dp = &reg_table[dp->op[1].bytemode][modrm.reg];
9402 break;
9403
9404 case USE_MOD_TABLE:
9405 vindex = modrm.mod == 0x3 ? 1 : 0;
9406 dp = &mod_table[dp->op[1].bytemode][vindex];
9407 break;
9408
9409 case USE_RM_TABLE:
9410 dp = &rm_table[dp->op[1].bytemode][modrm.rm];
9411 break;
9412
9413 case USE_PREFIX_TABLE:
9414 if (need_vex)
9415 {
9416 /* The prefix in VEX is implicit. */
9417 switch (vex.prefix)
9418 {
9419 case 0:
9420 vindex = 0;
9421 break;
9422 case REPE_PREFIX_OPCODE:
9423 vindex = 1;
9424 break;
9425 case DATA_PREFIX_OPCODE:
9426 vindex = 2;
9427 break;
9428 case REPNE_PREFIX_OPCODE:
9429 vindex = 3;
9430 break;
9431 default:
9432 abort ();
9433 break;
9434 }
9435 }
9436 else
9437 {
9438 int last_prefix = -1;
9439 int prefix = 0;
9440 vindex = 0;
9441 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
9442 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
9443 last one wins. */
9444 if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
9445 {
9446 if (last_repz_prefix > last_repnz_prefix)
9447 {
9448 vindex = 1;
9449 prefix = PREFIX_REPZ;
9450 last_prefix = last_repz_prefix;
9451 }
9452 else
9453 {
9454 vindex = 3;
9455 prefix = PREFIX_REPNZ;
9456 last_prefix = last_repnz_prefix;
9457 }
9458
9459 /* Check if prefix should be ignored. */
9460 if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
9461 & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
9462 & prefix) != 0)
9463 vindex = 0;
9464 }
9465
9466 if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
9467 {
9468 vindex = 2;
9469 prefix = PREFIX_DATA;
9470 last_prefix = last_data_prefix;
9471 }
9472
9473 if (vindex != 0)
9474 {
9475 used_prefixes |= prefix;
9476 all_prefixes[last_prefix] = 0;
9477 }
9478 }
9479 dp = &prefix_table[dp->op[1].bytemode][vindex];
9480 break;
9481
9482 case USE_X86_64_TABLE:
9483 vindex = address_mode == mode_64bit ? 1 : 0;
9484 dp = &x86_64_table[dp->op[1].bytemode][vindex];
9485 break;
9486
9487 case USE_3BYTE_TABLE:
9488 FETCH_DATA (info, codep + 2);
9489 vindex = *codep++;
9490 dp = &three_byte_table[dp->op[1].bytemode][vindex];
9491 end_codep = codep;
9492 modrm.mod = (*codep >> 6) & 3;
9493 modrm.reg = (*codep >> 3) & 7;
9494 modrm.rm = *codep & 7;
9495 break;
9496
9497 case USE_VEX_LEN_TABLE:
9498 if (!need_vex)
9499 abort ();
9500
9501 switch (vex.length)
9502 {
9503 case 128:
9504 vindex = 0;
9505 break;
9506 case 256:
9507 vindex = 1;
9508 break;
9509 default:
9510 abort ();
9511 break;
9512 }
9513
9514 dp = &vex_len_table[dp->op[1].bytemode][vindex];
9515 break;
9516
9517 case USE_EVEX_LEN_TABLE:
9518 if (!vex.evex)
9519 abort ();
9520
9521 switch (vex.length)
9522 {
9523 case 128:
9524 vindex = 0;
9525 break;
9526 case 256:
9527 vindex = 1;
9528 break;
9529 case 512:
9530 vindex = 2;
9531 break;
9532 default:
9533 abort ();
9534 break;
9535 }
9536
9537 dp = &evex_len_table[dp->op[1].bytemode][vindex];
9538 break;
9539
9540 case USE_XOP_8F_TABLE:
9541 FETCH_DATA (info, codep + 3);
9542 rex = ~(*codep >> 5) & 0x7;
9543
9544 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
9545 switch ((*codep & 0x1f))
9546 {
9547 default:
9548 dp = &bad_opcode;
9549 return dp;
9550 case 0x8:
9551 vex_table_index = XOP_08;
9552 break;
9553 case 0x9:
9554 vex_table_index = XOP_09;
9555 break;
9556 case 0xa:
9557 vex_table_index = XOP_0A;
9558 break;
9559 }
9560 codep++;
9561 vex.w = *codep & 0x80;
9562 if (vex.w && address_mode == mode_64bit)
9563 rex |= REX_W;
9564
9565 vex.register_specifier = (~(*codep >> 3)) & 0xf;
9566 if (address_mode != mode_64bit)
9567 {
9568 /* In 16/32-bit mode REX_B is silently ignored. */
9569 rex &= ~REX_B;
9570 }
9571
9572 vex.length = (*codep & 0x4) ? 256 : 128;
9573 switch ((*codep & 0x3))
9574 {
9575 case 0:
9576 break;
9577 case 1:
9578 vex.prefix = DATA_PREFIX_OPCODE;
9579 break;
9580 case 2:
9581 vex.prefix = REPE_PREFIX_OPCODE;
9582 break;
9583 case 3:
9584 vex.prefix = REPNE_PREFIX_OPCODE;
9585 break;
9586 }
9587 need_vex = 1;
9588 codep++;
9589 vindex = *codep++;
9590 dp = &xop_table[vex_table_index][vindex];
9591
9592 end_codep = codep;
9593 FETCH_DATA (info, codep + 1);
9594 modrm.mod = (*codep >> 6) & 3;
9595 modrm.reg = (*codep >> 3) & 7;
9596 modrm.rm = *codep & 7;
9597
9598 /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid
9599 having to decode the bits for every otherwise valid encoding. */
9600 if (vex.prefix)
9601 return &bad_opcode;
9602 break;
9603
9604 case USE_VEX_C4_TABLE:
9605 /* VEX prefix. */
9606 FETCH_DATA (info, codep + 3);
9607 rex = ~(*codep >> 5) & 0x7;
9608 switch ((*codep & 0x1f))
9609 {
9610 default:
9611 dp = &bad_opcode;
9612 return dp;
9613 case 0x1:
9614 vex_table_index = VEX_0F;
9615 break;
9616 case 0x2:
9617 vex_table_index = VEX_0F38;
9618 break;
9619 case 0x3:
9620 vex_table_index = VEX_0F3A;
9621 break;
9622 }
9623 codep++;
9624 vex.w = *codep & 0x80;
9625 if (address_mode == mode_64bit)
9626 {
9627 if (vex.w)
9628 rex |= REX_W;
9629 }
9630 else
9631 {
9632 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
9633 is ignored, other REX bits are 0 and the highest bit in
9634 VEX.vvvv is also ignored (but we mustn't clear it here). */
9635 rex = 0;
9636 }
9637 vex.register_specifier = (~(*codep >> 3)) & 0xf;
9638 vex.length = (*codep & 0x4) ? 256 : 128;
9639 switch ((*codep & 0x3))
9640 {
9641 case 0:
9642 break;
9643 case 1:
9644 vex.prefix = DATA_PREFIX_OPCODE;
9645 break;
9646 case 2:
9647 vex.prefix = REPE_PREFIX_OPCODE;
9648 break;
9649 case 3:
9650 vex.prefix = REPNE_PREFIX_OPCODE;
9651 break;
9652 }
9653 need_vex = 1;
9654 codep++;
9655 vindex = *codep++;
9656 dp = &vex_table[vex_table_index][vindex];
9657 end_codep = codep;
9658 /* There is no MODRM byte for VEX0F 77. */
9659 if (vex_table_index != VEX_0F || vindex != 0x77)
9660 {
9661 FETCH_DATA (info, codep + 1);
9662 modrm.mod = (*codep >> 6) & 3;
9663 modrm.reg = (*codep >> 3) & 7;
9664 modrm.rm = *codep & 7;
9665 }
9666 break;
9667
9668 case USE_VEX_C5_TABLE:
9669 /* VEX prefix. */
9670 FETCH_DATA (info, codep + 2);
9671 rex = (*codep & 0x80) ? 0 : REX_R;
9672
9673 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
9674 VEX.vvvv is 1. */
9675 vex.register_specifier = (~(*codep >> 3)) & 0xf;
9676 vex.length = (*codep & 0x4) ? 256 : 128;
9677 switch ((*codep & 0x3))
9678 {
9679 case 0:
9680 break;
9681 case 1:
9682 vex.prefix = DATA_PREFIX_OPCODE;
9683 break;
9684 case 2:
9685 vex.prefix = REPE_PREFIX_OPCODE;
9686 break;
9687 case 3:
9688 vex.prefix = REPNE_PREFIX_OPCODE;
9689 break;
9690 }
9691 need_vex = 1;
9692 codep++;
9693 vindex = *codep++;
9694 dp = &vex_table[dp->op[1].bytemode][vindex];
9695 end_codep = codep;
9696 /* There is no MODRM byte for VEX 77. */
9697 if (vindex != 0x77)
9698 {
9699 FETCH_DATA (info, codep + 1);
9700 modrm.mod = (*codep >> 6) & 3;
9701 modrm.reg = (*codep >> 3) & 7;
9702 modrm.rm = *codep & 7;
9703 }
9704 break;
9705
9706 case USE_VEX_W_TABLE:
9707 if (!need_vex)
9708 abort ();
9709
9710 dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
9711 break;
9712
9713 case USE_EVEX_TABLE:
9714 two_source_ops = 0;
9715 /* EVEX prefix. */
9716 vex.evex = 1;
9717 FETCH_DATA (info, codep + 4);
9718 /* The first byte after 0x62. */
9719 rex = ~(*codep >> 5) & 0x7;
9720 vex.r = *codep & 0x10;
9721 switch ((*codep & 0xf))
9722 {
9723 default:
9724 return &bad_opcode;
9725 case 0x1:
9726 vex_table_index = EVEX_0F;
9727 break;
9728 case 0x2:
9729 vex_table_index = EVEX_0F38;
9730 break;
9731 case 0x3:
9732 vex_table_index = EVEX_0F3A;
9733 break;
9734 }
9735
9736 /* The second byte after 0x62. */
9737 codep++;
9738 vex.w = *codep & 0x80;
9739 if (vex.w && address_mode == mode_64bit)
9740 rex |= REX_W;
9741
9742 vex.register_specifier = (~(*codep >> 3)) & 0xf;
9743
9744 /* The U bit. */
9745 if (!(*codep & 0x4))
9746 return &bad_opcode;
9747
9748 switch ((*codep & 0x3))
9749 {
9750 case 0:
9751 break;
9752 case 1:
9753 vex.prefix = DATA_PREFIX_OPCODE;
9754 break;
9755 case 2:
9756 vex.prefix = REPE_PREFIX_OPCODE;
9757 break;
9758 case 3:
9759 vex.prefix = REPNE_PREFIX_OPCODE;
9760 break;
9761 }
9762
9763 /* The third byte after 0x62. */
9764 codep++;
9765
9766 /* Remember the static rounding bits. */
9767 vex.ll = (*codep >> 5) & 3;
9768 vex.b = (*codep & 0x10) != 0;
9769
9770 vex.v = *codep & 0x8;
9771 vex.mask_register_specifier = *codep & 0x7;
9772 vex.zeroing = *codep & 0x80;
9773
9774 if (address_mode != mode_64bit)
9775 {
9776 /* In 16/32-bit mode silently ignore following bits. */
9777 rex &= ~REX_B;
9778 vex.r = 1;
9779 vex.v = 1;
9780 }
9781
9782 need_vex = 1;
9783 codep++;
9784 vindex = *codep++;
9785 dp = &evex_table[vex_table_index][vindex];
9786 end_codep = codep;
9787 FETCH_DATA (info, codep + 1);
9788 modrm.mod = (*codep >> 6) & 3;
9789 modrm.reg = (*codep >> 3) & 7;
9790 modrm.rm = *codep & 7;
9791
9792 /* Set vector length. */
9793 if (modrm.mod == 3 && vex.b)
9794 vex.length = 512;
9795 else
9796 {
9797 switch (vex.ll)
9798 {
9799 case 0x0:
9800 vex.length = 128;
9801 break;
9802 case 0x1:
9803 vex.length = 256;
9804 break;
9805 case 0x2:
9806 vex.length = 512;
9807 break;
9808 default:
9809 return &bad_opcode;
9810 }
9811 }
9812 break;
9813
9814 case 0:
9815 dp = &bad_opcode;
9816 break;
9817
9818 default:
9819 abort ();
9820 }
9821
9822 if (dp->name != NULL)
9823 return dp;
9824 else
9825 return get_valid_dis386 (dp, info);
9826 }
9827
9828 static void
9829 get_sib (disassemble_info *info, int sizeflag)
9830 {
9831 /* If modrm.mod == 3, operand must be register. */
9832 if (need_modrm
9833 && ((sizeflag & AFLAG) || address_mode == mode_64bit)
9834 && modrm.mod != 3
9835 && modrm.rm == 4)
9836 {
9837 FETCH_DATA (info, codep + 2);
9838 sib.index = (codep [1] >> 3) & 7;
9839 sib.scale = (codep [1] >> 6) & 3;
9840 sib.base = codep [1] & 7;
9841 }
9842 }
9843
9844 static int
9845 print_insn (bfd_vma pc, disassemble_info *info)
9846 {
9847 const struct dis386 *dp;
9848 int i;
9849 char *op_txt[MAX_OPERANDS];
9850 int needcomma;
9851 int sizeflag, orig_sizeflag;
9852 const char *p;
9853 struct dis_private priv;
9854 int prefix_length;
9855
9856 priv.orig_sizeflag = AFLAG | DFLAG;
9857 if ((info->mach & bfd_mach_i386_i386) != 0)
9858 address_mode = mode_32bit;
9859 else if (info->mach == bfd_mach_i386_i8086)
9860 {
9861 address_mode = mode_16bit;
9862 priv.orig_sizeflag = 0;
9863 }
9864 else
9865 address_mode = mode_64bit;
9866
9867 if (intel_syntax == (char) -1)
9868 intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
9869
9870 for (p = info->disassembler_options; p != NULL; )
9871 {
9872 if (CONST_STRNEQ (p, "amd64"))
9873 isa64 = amd64;
9874 else if (CONST_STRNEQ (p, "intel64"))
9875 isa64 = intel64;
9876 else if (CONST_STRNEQ (p, "x86-64"))
9877 {
9878 address_mode = mode_64bit;
9879 priv.orig_sizeflag |= AFLAG | DFLAG;
9880 }
9881 else if (CONST_STRNEQ (p, "i386"))
9882 {
9883 address_mode = mode_32bit;
9884 priv.orig_sizeflag |= AFLAG | DFLAG;
9885 }
9886 else if (CONST_STRNEQ (p, "i8086"))
9887 {
9888 address_mode = mode_16bit;
9889 priv.orig_sizeflag &= ~(AFLAG | DFLAG);
9890 }
9891 else if (CONST_STRNEQ (p, "intel"))
9892 {
9893 intel_syntax = 1;
9894 if (CONST_STRNEQ (p + 5, "-mnemonic"))
9895 intel_mnemonic = 1;
9896 }
9897 else if (CONST_STRNEQ (p, "att"))
9898 {
9899 intel_syntax = 0;
9900 if (CONST_STRNEQ (p + 3, "-mnemonic"))
9901 intel_mnemonic = 0;
9902 }
9903 else if (CONST_STRNEQ (p, "addr"))
9904 {
9905 if (address_mode == mode_64bit)
9906 {
9907 if (p[4] == '3' && p[5] == '2')
9908 priv.orig_sizeflag &= ~AFLAG;
9909 else if (p[4] == '6' && p[5] == '4')
9910 priv.orig_sizeflag |= AFLAG;
9911 }
9912 else
9913 {
9914 if (p[4] == '1' && p[5] == '6')
9915 priv.orig_sizeflag &= ~AFLAG;
9916 else if (p[4] == '3' && p[5] == '2')
9917 priv.orig_sizeflag |= AFLAG;
9918 }
9919 }
9920 else if (CONST_STRNEQ (p, "data"))
9921 {
9922 if (p[4] == '1' && p[5] == '6')
9923 priv.orig_sizeflag &= ~DFLAG;
9924 else if (p[4] == '3' && p[5] == '2')
9925 priv.orig_sizeflag |= DFLAG;
9926 }
9927 else if (CONST_STRNEQ (p, "suffix"))
9928 priv.orig_sizeflag |= SUFFIX_ALWAYS;
9929
9930 p = strchr (p, ',');
9931 if (p != NULL)
9932 p++;
9933 }
9934
9935 if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
9936 {
9937 (*info->fprintf_func) (info->stream,
9938 _("64-bit address is disabled"));
9939 return -1;
9940 }
9941
9942 if (intel_syntax)
9943 {
9944 names64 = intel_names64;
9945 names32 = intel_names32;
9946 names16 = intel_names16;
9947 names8 = intel_names8;
9948 names8rex = intel_names8rex;
9949 names_seg = intel_names_seg;
9950 names_mm = intel_names_mm;
9951 names_bnd = intel_names_bnd;
9952 names_xmm = intel_names_xmm;
9953 names_ymm = intel_names_ymm;
9954 names_zmm = intel_names_zmm;
9955 names_tmm = intel_names_tmm;
9956 index64 = intel_index64;
9957 index32 = intel_index32;
9958 names_mask = intel_names_mask;
9959 index16 = intel_index16;
9960 open_char = '[';
9961 close_char = ']';
9962 separator_char = '+';
9963 scale_char = '*';
9964 }
9965 else
9966 {
9967 names64 = att_names64;
9968 names32 = att_names32;
9969 names16 = att_names16;
9970 names8 = att_names8;
9971 names8rex = att_names8rex;
9972 names_seg = att_names_seg;
9973 names_mm = att_names_mm;
9974 names_bnd = att_names_bnd;
9975 names_xmm = att_names_xmm;
9976 names_ymm = att_names_ymm;
9977 names_zmm = att_names_zmm;
9978 names_tmm = att_names_tmm;
9979 index64 = att_index64;
9980 index32 = att_index32;
9981 names_mask = att_names_mask;
9982 index16 = att_index16;
9983 open_char = '(';
9984 close_char = ')';
9985 separator_char = ',';
9986 scale_char = ',';
9987 }
9988
9989 /* The output looks better if we put 7 bytes on a line, since that
9990 puts most long word instructions on a single line. Use 8 bytes
9991 for Intel L1OM. */
9992 if ((info->mach & bfd_mach_l1om) != 0)
9993 info->bytes_per_line = 8;
9994 else
9995 info->bytes_per_line = 7;
9996
9997 info->private_data = &priv;
9998 priv.max_fetched = priv.the_buffer;
9999 priv.insn_start = pc;
10000
10001 obuf[0] = 0;
10002 for (i = 0; i < MAX_OPERANDS; ++i)
10003 {
10004 op_out[i][0] = 0;
10005 op_index[i] = -1;
10006 }
10007
10008 the_info = info;
10009 start_pc = pc;
10010 start_codep = priv.the_buffer;
10011 codep = priv.the_buffer;
10012
10013 if (OPCODES_SIGSETJMP (priv.bailout) != 0)
10014 {
10015 const char *name;
10016
10017 /* Getting here means we tried for data but didn't get it. That
10018 means we have an incomplete instruction of some sort. Just
10019 print the first byte as a prefix or a .byte pseudo-op. */
10020 if (codep > priv.the_buffer)
10021 {
10022 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
10023 if (name != NULL)
10024 (*info->fprintf_func) (info->stream, "%s", name);
10025 else
10026 {
10027 /* Just print the first byte as a .byte instruction. */
10028 (*info->fprintf_func) (info->stream, ".byte 0x%x",
10029 (unsigned int) priv.the_buffer[0]);
10030 }
10031
10032 return 1;
10033 }
10034
10035 return -1;
10036 }
10037
10038 obufp = obuf;
10039 sizeflag = priv.orig_sizeflag;
10040
10041 if (!ckprefix () || rex_used)
10042 {
10043 /* Too many prefixes or unused REX prefixes. */
10044 for (i = 0;
10045 i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
10046 i++)
10047 (*info->fprintf_func) (info->stream, "%s%s",
10048 i == 0 ? "" : " ",
10049 prefix_name (all_prefixes[i], sizeflag));
10050 return i;
10051 }
10052
10053 insn_codep = codep;
10054
10055 FETCH_DATA (info, codep + 1);
10056 two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
10057
10058 if (((prefixes & PREFIX_FWAIT)
10059 && ((*codep < 0xd8) || (*codep > 0xdf))))
10060 {
10061 /* Handle prefixes before fwait. */
10062 for (i = 0; i < fwait_prefix && all_prefixes[i];
10063 i++)
10064 (*info->fprintf_func) (info->stream, "%s ",
10065 prefix_name (all_prefixes[i], sizeflag));
10066 (*info->fprintf_func) (info->stream, "fwait");
10067 return i + 1;
10068 }
10069
10070 if (*codep == 0x0f)
10071 {
10072 unsigned char threebyte;
10073
10074 codep++;
10075 FETCH_DATA (info, codep + 1);
10076 threebyte = *codep;
10077 dp = &dis386_twobyte[threebyte];
10078 need_modrm = twobyte_has_modrm[threebyte];
10079 codep++;
10080 }
10081 else
10082 {
10083 dp = &dis386[*codep];
10084 need_modrm = onebyte_has_modrm[*codep];
10085 codep++;
10086 }
10087
10088 /* Save sizeflag for printing the extra prefixes later before updating
10089 it for mnemonic and operand processing. The prefix names depend
10090 only on the address mode. */
10091 orig_sizeflag = sizeflag;
10092 if (prefixes & PREFIX_ADDR)
10093 sizeflag ^= AFLAG;
10094 if ((prefixes & PREFIX_DATA))
10095 sizeflag ^= DFLAG;
10096
10097 end_codep = codep;
10098 if (need_modrm)
10099 {
10100 FETCH_DATA (info, codep + 1);
10101 modrm.mod = (*codep >> 6) & 3;
10102 modrm.reg = (*codep >> 3) & 7;
10103 modrm.rm = *codep & 7;
10104 }
10105 else
10106 memset (&modrm, 0, sizeof (modrm));
10107
10108 need_vex = 0;
10109 memset (&vex, 0, sizeof (vex));
10110
10111 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
10112 {
10113 get_sib (info, sizeflag);
10114 dofloat (sizeflag);
10115 }
10116 else
10117 {
10118 dp = get_valid_dis386 (dp, info);
10119 if (dp != NULL && putop (dp->name, sizeflag) == 0)
10120 {
10121 get_sib (info, sizeflag);
10122 for (i = 0; i < MAX_OPERANDS; ++i)
10123 {
10124 obufp = op_out[i];
10125 op_ad = MAX_OPERANDS - 1 - i;
10126 if (dp->op[i].rtn)
10127 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
10128 /* For EVEX instruction after the last operand masking
10129 should be printed. */
10130 if (i == 0 && vex.evex)
10131 {
10132 /* Don't print {%k0}. */
10133 if (vex.mask_register_specifier)
10134 {
10135 oappend ("{");
10136 oappend (names_mask[vex.mask_register_specifier]);
10137 oappend ("}");
10138 }
10139 if (vex.zeroing)
10140 oappend ("{z}");
10141 }
10142 }
10143 }
10144 }
10145
10146 /* Clear instruction information. */
10147 if (the_info)
10148 {
10149 the_info->insn_info_valid = 0;
10150 the_info->branch_delay_insns = 0;
10151 the_info->data_size = 0;
10152 the_info->insn_type = dis_noninsn;
10153 the_info->target = 0;
10154 the_info->target2 = 0;
10155 }
10156
10157 /* Reset jump operation indicator. */
10158 op_is_jump = FALSE;
10159
10160 {
10161 int jump_detection = 0;
10162
10163 /* Extract flags. */
10164 for (i = 0; i < MAX_OPERANDS; ++i)
10165 {
10166 if ((dp->op[i].rtn == OP_J)
10167 || (dp->op[i].rtn == OP_indirE))
10168 jump_detection |= 1;
10169 else if ((dp->op[i].rtn == BND_Fixup)
10170 || (!dp->op[i].rtn && !dp->op[i].bytemode))
10171 jump_detection |= 2;
10172 else if ((dp->op[i].bytemode == cond_jump_mode)
10173 || (dp->op[i].bytemode == loop_jcxz_mode))
10174 jump_detection |= 4;
10175 }
10176
10177 /* Determine if this is a jump or branch. */
10178 if ((jump_detection & 0x3) == 0x3)
10179 {
10180 op_is_jump = TRUE;
10181 if (jump_detection & 0x4)
10182 the_info->insn_type = dis_condbranch;
10183 else
10184 the_info->insn_type =
10185 (dp->name && !strncmp(dp->name, "call", 4))
10186 ? dis_jsr : dis_branch;
10187 }
10188 }
10189
10190 /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
10191 are all 0s in inverted form. */
10192 if (need_vex && vex.register_specifier != 0)
10193 {
10194 (*info->fprintf_func) (info->stream, "(bad)");
10195 return end_codep - priv.the_buffer;
10196 }
10197
10198 switch (dp->prefix_requirement)
10199 {
10200 case PREFIX_DATA:
10201 /* If only the data prefix is marked as mandatory, its absence renders
10202 the encoding invalid. Most other PREFIX_OPCODE rules still apply. */
10203 if (need_vex ? !vex.prefix : !(prefixes & PREFIX_DATA))
10204 {
10205 (*info->fprintf_func) (info->stream, "(bad)");
10206 return end_codep - priv.the_buffer;
10207 }
10208 used_prefixes |= PREFIX_DATA;
10209 /* Fall through. */
10210 case PREFIX_OPCODE:
10211 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
10212 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
10213 used by putop and MMX/SSE operand and may be overridden by the
10214 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
10215 separately. */
10216 if (((need_vex
10217 ? vex.prefix == REPE_PREFIX_OPCODE
10218 || vex.prefix == REPNE_PREFIX_OPCODE
10219 : (prefixes
10220 & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
10221 && (used_prefixes
10222 & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
10223 || (((need_vex
10224 ? vex.prefix == DATA_PREFIX_OPCODE
10225 : ((prefixes
10226 & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
10227 == PREFIX_DATA))
10228 && (used_prefixes & PREFIX_DATA) == 0))
10229 || (vex.evex && dp->prefix_requirement != PREFIX_DATA
10230 && !vex.w != !(used_prefixes & PREFIX_DATA)))
10231 {
10232 (*info->fprintf_func) (info->stream, "(bad)");
10233 return end_codep - priv.the_buffer;
10234 }
10235 break;
10236 }
10237
10238 /* Check if the REX prefix is used. */
10239 if ((rex ^ rex_used) == 0 && !need_vex && last_rex_prefix >= 0)
10240 all_prefixes[last_rex_prefix] = 0;
10241
10242 /* Check if the SEG prefix is used. */
10243 if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
10244 | PREFIX_FS | PREFIX_GS)) != 0
10245 && (used_prefixes & active_seg_prefix) != 0)
10246 all_prefixes[last_seg_prefix] = 0;
10247
10248 /* Check if the ADDR prefix is used. */
10249 if ((prefixes & PREFIX_ADDR) != 0
10250 && (used_prefixes & PREFIX_ADDR) != 0)
10251 all_prefixes[last_addr_prefix] = 0;
10252
10253 /* Check if the DATA prefix is used. */
10254 if ((prefixes & PREFIX_DATA) != 0
10255 && (used_prefixes & PREFIX_DATA) != 0
10256 && !need_vex)
10257 all_prefixes[last_data_prefix] = 0;
10258
10259 /* Print the extra prefixes. */
10260 prefix_length = 0;
10261 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
10262 if (all_prefixes[i])
10263 {
10264 const char *name;
10265 name = prefix_name (all_prefixes[i], orig_sizeflag);
10266 if (name == NULL)
10267 abort ();
10268 prefix_length += strlen (name) + 1;
10269 (*info->fprintf_func) (info->stream, "%s ", name);
10270 }
10271
10272 /* Check maximum code length. */
10273 if ((codep - start_codep) > MAX_CODE_LENGTH)
10274 {
10275 (*info->fprintf_func) (info->stream, "(bad)");
10276 return MAX_CODE_LENGTH;
10277 }
10278
10279 obufp = mnemonicendp;
10280 for (i = strlen (obuf) + prefix_length; i < 6; i++)
10281 oappend (" ");
10282 oappend (" ");
10283 (*info->fprintf_func) (info->stream, "%s", obuf);
10284
10285 /* The enter and bound instructions are printed with operands in the same
10286 order as the intel book; everything else is printed in reverse order. */
10287 if (intel_syntax || two_source_ops)
10288 {
10289 bfd_vma riprel;
10290
10291 for (i = 0; i < MAX_OPERANDS; ++i)
10292 op_txt[i] = op_out[i];
10293
10294 if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
10295 && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
10296 {
10297 op_txt[2] = op_out[3];
10298 op_txt[3] = op_out[2];
10299 }
10300
10301 for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
10302 {
10303 op_ad = op_index[i];
10304 op_index[i] = op_index[MAX_OPERANDS - 1 - i];
10305 op_index[MAX_OPERANDS - 1 - i] = op_ad;
10306 riprel = op_riprel[i];
10307 op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
10308 op_riprel[MAX_OPERANDS - 1 - i] = riprel;
10309 }
10310 }
10311 else
10312 {
10313 for (i = 0; i < MAX_OPERANDS; ++i)
10314 op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
10315 }
10316
10317 needcomma = 0;
10318 for (i = 0; i < MAX_OPERANDS; ++i)
10319 if (*op_txt[i])
10320 {
10321 if (needcomma)
10322 (*info->fprintf_func) (info->stream, ",");
10323 if (op_index[i] != -1 && !op_riprel[i])
10324 {
10325 bfd_vma target = (bfd_vma) op_address[op_index[i]];
10326
10327 if (the_info && op_is_jump)
10328 {
10329 the_info->insn_info_valid = 1;
10330 the_info->branch_delay_insns = 0;
10331 the_info->data_size = 0;
10332 the_info->target = target;
10333 the_info->target2 = 0;
10334 }
10335 (*info->print_address_func) (target, info);
10336 }
10337 else
10338 (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
10339 needcomma = 1;
10340 }
10341
10342 for (i = 0; i < MAX_OPERANDS; i++)
10343 if (op_index[i] != -1 && op_riprel[i])
10344 {
10345 (*info->fprintf_func) (info->stream, " # ");
10346 (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
10347 + op_address[op_index[i]]), info);
10348 break;
10349 }
10350 return codep - priv.the_buffer;
10351 }
10352
10353 static const char *float_mem[] = {
10354 /* d8 */
10355 "fadd{s|}",
10356 "fmul{s|}",
10357 "fcom{s|}",
10358 "fcomp{s|}",
10359 "fsub{s|}",
10360 "fsubr{s|}",
10361 "fdiv{s|}",
10362 "fdivr{s|}",
10363 /* d9 */
10364 "fld{s|}",
10365 "(bad)",
10366 "fst{s|}",
10367 "fstp{s|}",
10368 "fldenv{C|C}",
10369 "fldcw",
10370 "fNstenv{C|C}",
10371 "fNstcw",
10372 /* da */
10373 "fiadd{l|}",
10374 "fimul{l|}",
10375 "ficom{l|}",
10376 "ficomp{l|}",
10377 "fisub{l|}",
10378 "fisubr{l|}",
10379 "fidiv{l|}",
10380 "fidivr{l|}",
10381 /* db */
10382 "fild{l|}",
10383 "fisttp{l|}",
10384 "fist{l|}",
10385 "fistp{l|}",
10386 "(bad)",
10387 "fld{t|}",
10388 "(bad)",
10389 "fstp{t|}",
10390 /* dc */
10391 "fadd{l|}",
10392 "fmul{l|}",
10393 "fcom{l|}",
10394 "fcomp{l|}",
10395 "fsub{l|}",
10396 "fsubr{l|}",
10397 "fdiv{l|}",
10398 "fdivr{l|}",
10399 /* dd */
10400 "fld{l|}",
10401 "fisttp{ll|}",
10402 "fst{l||}",
10403 "fstp{l|}",
10404 "frstor{C|C}",
10405 "(bad)",
10406 "fNsave{C|C}",
10407 "fNstsw",
10408 /* de */
10409 "fiadd{s|}",
10410 "fimul{s|}",
10411 "ficom{s|}",
10412 "ficomp{s|}",
10413 "fisub{s|}",
10414 "fisubr{s|}",
10415 "fidiv{s|}",
10416 "fidivr{s|}",
10417 /* df */
10418 "fild{s|}",
10419 "fisttp{s|}",
10420 "fist{s|}",
10421 "fistp{s|}",
10422 "fbld",
10423 "fild{ll|}",
10424 "fbstp",
10425 "fistp{ll|}",
10426 };
10427
10428 static const unsigned char float_mem_mode[] = {
10429 /* d8 */
10430 d_mode,
10431 d_mode,
10432 d_mode,
10433 d_mode,
10434 d_mode,
10435 d_mode,
10436 d_mode,
10437 d_mode,
10438 /* d9 */
10439 d_mode,
10440 0,
10441 d_mode,
10442 d_mode,
10443 0,
10444 w_mode,
10445 0,
10446 w_mode,
10447 /* da */
10448 d_mode,
10449 d_mode,
10450 d_mode,
10451 d_mode,
10452 d_mode,
10453 d_mode,
10454 d_mode,
10455 d_mode,
10456 /* db */
10457 d_mode,
10458 d_mode,
10459 d_mode,
10460 d_mode,
10461 0,
10462 t_mode,
10463 0,
10464 t_mode,
10465 /* dc */
10466 q_mode,
10467 q_mode,
10468 q_mode,
10469 q_mode,
10470 q_mode,
10471 q_mode,
10472 q_mode,
10473 q_mode,
10474 /* dd */
10475 q_mode,
10476 q_mode,
10477 q_mode,
10478 q_mode,
10479 0,
10480 0,
10481 0,
10482 w_mode,
10483 /* de */
10484 w_mode,
10485 w_mode,
10486 w_mode,
10487 w_mode,
10488 w_mode,
10489 w_mode,
10490 w_mode,
10491 w_mode,
10492 /* df */
10493 w_mode,
10494 w_mode,
10495 w_mode,
10496 w_mode,
10497 t_mode,
10498 q_mode,
10499 t_mode,
10500 q_mode
10501 };
10502
10503 #define ST { OP_ST, 0 }
10504 #define STi { OP_STi, 0 }
10505
10506 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
10507 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
10508 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
10509 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
10510 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
10511 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
10512 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
10513 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
10514 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
10515
10516 static const struct dis386 float_reg[][8] = {
10517 /* d8 */
10518 {
10519 { "fadd", { ST, STi }, 0 },
10520 { "fmul", { ST, STi }, 0 },
10521 { "fcom", { STi }, 0 },
10522 { "fcomp", { STi }, 0 },
10523 { "fsub", { ST, STi }, 0 },
10524 { "fsubr", { ST, STi }, 0 },
10525 { "fdiv", { ST, STi }, 0 },
10526 { "fdivr", { ST, STi }, 0 },
10527 },
10528 /* d9 */
10529 {
10530 { "fld", { STi }, 0 },
10531 { "fxch", { STi }, 0 },
10532 { FGRPd9_2 },
10533 { Bad_Opcode },
10534 { FGRPd9_4 },
10535 { FGRPd9_5 },
10536 { FGRPd9_6 },
10537 { FGRPd9_7 },
10538 },
10539 /* da */
10540 {
10541 { "fcmovb", { ST, STi }, 0 },
10542 { "fcmove", { ST, STi }, 0 },
10543 { "fcmovbe",{ ST, STi }, 0 },
10544 { "fcmovu", { ST, STi }, 0 },
10545 { Bad_Opcode },
10546 { FGRPda_5 },
10547 { Bad_Opcode },
10548 { Bad_Opcode },
10549 },
10550 /* db */
10551 {
10552 { "fcmovnb",{ ST, STi }, 0 },
10553 { "fcmovne",{ ST, STi }, 0 },
10554 { "fcmovnbe",{ ST, STi }, 0 },
10555 { "fcmovnu",{ ST, STi }, 0 },
10556 { FGRPdb_4 },
10557 { "fucomi", { ST, STi }, 0 },
10558 { "fcomi", { ST, STi }, 0 },
10559 { Bad_Opcode },
10560 },
10561 /* dc */
10562 {
10563 { "fadd", { STi, ST }, 0 },
10564 { "fmul", { STi, ST }, 0 },
10565 { Bad_Opcode },
10566 { Bad_Opcode },
10567 { "fsub{!M|r}", { STi, ST }, 0 },
10568 { "fsub{M|}", { STi, ST }, 0 },
10569 { "fdiv{!M|r}", { STi, ST }, 0 },
10570 { "fdiv{M|}", { STi, ST }, 0 },
10571 },
10572 /* dd */
10573 {
10574 { "ffree", { STi }, 0 },
10575 { Bad_Opcode },
10576 { "fst", { STi }, 0 },
10577 { "fstp", { STi }, 0 },
10578 { "fucom", { STi }, 0 },
10579 { "fucomp", { STi }, 0 },
10580 { Bad_Opcode },
10581 { Bad_Opcode },
10582 },
10583 /* de */
10584 {
10585 { "faddp", { STi, ST }, 0 },
10586 { "fmulp", { STi, ST }, 0 },
10587 { Bad_Opcode },
10588 { FGRPde_3 },
10589 { "fsub{!M|r}p", { STi, ST }, 0 },
10590 { "fsub{M|}p", { STi, ST }, 0 },
10591 { "fdiv{!M|r}p", { STi, ST }, 0 },
10592 { "fdiv{M|}p", { STi, ST }, 0 },
10593 },
10594 /* df */
10595 {
10596 { "ffreep", { STi }, 0 },
10597 { Bad_Opcode },
10598 { Bad_Opcode },
10599 { Bad_Opcode },
10600 { FGRPdf_4 },
10601 { "fucomip", { ST, STi }, 0 },
10602 { "fcomip", { ST, STi }, 0 },
10603 { Bad_Opcode },
10604 },
10605 };
10606
10607 static char *fgrps[][8] = {
10608 /* Bad opcode 0 */
10609 {
10610 "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10611 },
10612
10613 /* d9_2 1 */
10614 {
10615 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10616 },
10617
10618 /* d9_4 2 */
10619 {
10620 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
10621 },
10622
10623 /* d9_5 3 */
10624 {
10625 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
10626 },
10627
10628 /* d9_6 4 */
10629 {
10630 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
10631 },
10632
10633 /* d9_7 5 */
10634 {
10635 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
10636 },
10637
10638 /* da_5 6 */
10639 {
10640 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10641 },
10642
10643 /* db_4 7 */
10644 {
10645 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
10646 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
10647 },
10648
10649 /* de_3 8 */
10650 {
10651 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10652 },
10653
10654 /* df_4 9 */
10655 {
10656 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10657 },
10658 };
10659
10660 static void
10661 swap_operand (void)
10662 {
10663 mnemonicendp[0] = '.';
10664 mnemonicendp[1] = 's';
10665 mnemonicendp += 2;
10666 }
10667
10668 static void
10669 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
10670 int sizeflag ATTRIBUTE_UNUSED)
10671 {
10672 /* Skip mod/rm byte. */
10673 MODRM_CHECK;
10674 codep++;
10675 }
10676
10677 static void
10678 dofloat (int sizeflag)
10679 {
10680 const struct dis386 *dp;
10681 unsigned char floatop;
10682
10683 floatop = codep[-1];
10684
10685 if (modrm.mod != 3)
10686 {
10687 int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
10688
10689 putop (float_mem[fp_indx], sizeflag);
10690 obufp = op_out[0];
10691 op_ad = 2;
10692 OP_E (float_mem_mode[fp_indx], sizeflag);
10693 return;
10694 }
10695 /* Skip mod/rm byte. */
10696 MODRM_CHECK;
10697 codep++;
10698
10699 dp = &float_reg[floatop - 0xd8][modrm.reg];
10700 if (dp->name == NULL)
10701 {
10702 putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
10703
10704 /* Instruction fnstsw is only one with strange arg. */
10705 if (floatop == 0xdf && codep[-1] == 0xe0)
10706 strcpy (op_out[0], names16[0]);
10707 }
10708 else
10709 {
10710 putop (dp->name, sizeflag);
10711
10712 obufp = op_out[0];
10713 op_ad = 2;
10714 if (dp->op[0].rtn)
10715 (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
10716
10717 obufp = op_out[1];
10718 op_ad = 1;
10719 if (dp->op[1].rtn)
10720 (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
10721 }
10722 }
10723
10724 /* Like oappend (below), but S is a string starting with '%'.
10725 In Intel syntax, the '%' is elided. */
10726 static void
10727 oappend_maybe_intel (const char *s)
10728 {
10729 oappend (s + intel_syntax);
10730 }
10731
10732 static void
10733 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
10734 {
10735 oappend_maybe_intel ("%st");
10736 }
10737
10738 static void
10739 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
10740 {
10741 sprintf (scratchbuf, "%%st(%d)", modrm.rm);
10742 oappend_maybe_intel (scratchbuf);
10743 }
10744
10745 /* Capital letters in template are macros. */
10746 static int
10747 putop (const char *in_template, int sizeflag)
10748 {
10749 const char *p;
10750 int alt = 0;
10751 int cond = 1;
10752 unsigned int l = 0, len = 0;
10753 char last[4];
10754
10755 for (p = in_template; *p; p++)
10756 {
10757 if (len > l)
10758 {
10759 if (l >= sizeof (last) || !ISUPPER (*p))
10760 abort ();
10761 last[l++] = *p;
10762 continue;
10763 }
10764 switch (*p)
10765 {
10766 default:
10767 *obufp++ = *p;
10768 break;
10769 case '%':
10770 len++;
10771 break;
10772 case '!':
10773 cond = 0;
10774 break;
10775 case '{':
10776 if (intel_syntax)
10777 {
10778 while (*++p != '|')
10779 if (*p == '}' || *p == '\0')
10780 abort ();
10781 alt = 1;
10782 }
10783 break;
10784 case '|':
10785 while (*++p != '}')
10786 {
10787 if (*p == '\0')
10788 abort ();
10789 }
10790 break;
10791 case '}':
10792 alt = 0;
10793 break;
10794 case 'A':
10795 if (intel_syntax)
10796 break;
10797 if ((need_modrm && modrm.mod != 3)
10798 || (sizeflag & SUFFIX_ALWAYS))
10799 *obufp++ = 'b';
10800 break;
10801 case 'B':
10802 if (l == 0)
10803 {
10804 case_B:
10805 if (intel_syntax)
10806 break;
10807 if (sizeflag & SUFFIX_ALWAYS)
10808 *obufp++ = 'b';
10809 }
10810 else if (l == 1 && last[0] == 'L')
10811 {
10812 if (address_mode == mode_64bit
10813 && !(prefixes & PREFIX_ADDR))
10814 {
10815 *obufp++ = 'a';
10816 *obufp++ = 'b';
10817 *obufp++ = 's';
10818 }
10819
10820 goto case_B;
10821 }
10822 else
10823 abort ();
10824 break;
10825 case 'C':
10826 if (intel_syntax && !alt)
10827 break;
10828 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10829 {
10830 if (sizeflag & DFLAG)
10831 *obufp++ = intel_syntax ? 'd' : 'l';
10832 else
10833 *obufp++ = intel_syntax ? 'w' : 's';
10834 used_prefixes |= (prefixes & PREFIX_DATA);
10835 }
10836 break;
10837 case 'D':
10838 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
10839 break;
10840 USED_REX (REX_W);
10841 if (modrm.mod == 3)
10842 {
10843 if (rex & REX_W)
10844 *obufp++ = 'q';
10845 else
10846 {
10847 if (sizeflag & DFLAG)
10848 *obufp++ = intel_syntax ? 'd' : 'l';
10849 else
10850 *obufp++ = 'w';
10851 used_prefixes |= (prefixes & PREFIX_DATA);
10852 }
10853 }
10854 else
10855 *obufp++ = 'w';
10856 break;
10857 case 'E': /* For jcxz/jecxz */
10858 if (address_mode == mode_64bit)
10859 {
10860 if (sizeflag & AFLAG)
10861 *obufp++ = 'r';
10862 else
10863 *obufp++ = 'e';
10864 }
10865 else
10866 if (sizeflag & AFLAG)
10867 *obufp++ = 'e';
10868 used_prefixes |= (prefixes & PREFIX_ADDR);
10869 break;
10870 case 'F':
10871 if (intel_syntax)
10872 break;
10873 if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
10874 {
10875 if (sizeflag & AFLAG)
10876 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
10877 else
10878 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
10879 used_prefixes |= (prefixes & PREFIX_ADDR);
10880 }
10881 break;
10882 case 'G':
10883 if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
10884 break;
10885 if ((rex & REX_W) || (sizeflag & DFLAG))
10886 *obufp++ = 'l';
10887 else
10888 *obufp++ = 'w';
10889 if (!(rex & REX_W))
10890 used_prefixes |= (prefixes & PREFIX_DATA);
10891 break;
10892 case 'H':
10893 if (intel_syntax)
10894 break;
10895 if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
10896 || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
10897 {
10898 used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
10899 *obufp++ = ',';
10900 *obufp++ = 'p';
10901 if (prefixes & PREFIX_DS)
10902 *obufp++ = 't';
10903 else
10904 *obufp++ = 'n';
10905 }
10906 break;
10907 case 'K':
10908 USED_REX (REX_W);
10909 if (rex & REX_W)
10910 *obufp++ = 'q';
10911 else
10912 *obufp++ = 'd';
10913 break;
10914 case 'L':
10915 abort ();
10916 case 'M':
10917 if (intel_mnemonic != cond)
10918 *obufp++ = 'r';
10919 break;
10920 case 'N':
10921 if ((prefixes & PREFIX_FWAIT) == 0)
10922 *obufp++ = 'n';
10923 else
10924 used_prefixes |= PREFIX_FWAIT;
10925 break;
10926 case 'O':
10927 USED_REX (REX_W);
10928 if (rex & REX_W)
10929 *obufp++ = 'o';
10930 else if (intel_syntax && (sizeflag & DFLAG))
10931 *obufp++ = 'q';
10932 else
10933 *obufp++ = 'd';
10934 if (!(rex & REX_W))
10935 used_prefixes |= (prefixes & PREFIX_DATA);
10936 break;
10937 case '@':
10938 if (address_mode == mode_64bit
10939 && (isa64 == intel64 || (rex & REX_W)
10940 || !(prefixes & PREFIX_DATA)))
10941 {
10942 if (sizeflag & SUFFIX_ALWAYS)
10943 *obufp++ = 'q';
10944 break;
10945 }
10946 /* Fall through. */
10947 case 'P':
10948 if (l == 0)
10949 {
10950 if ((modrm.mod == 3 || !cond)
10951 && !(sizeflag & SUFFIX_ALWAYS))
10952 break;
10953 /* Fall through. */
10954 case 'T':
10955 if ((!(rex & REX_W) && (prefixes & PREFIX_DATA))
10956 || ((sizeflag & SUFFIX_ALWAYS)
10957 && address_mode != mode_64bit))
10958 {
10959 *obufp++ = (sizeflag & DFLAG) ?
10960 intel_syntax ? 'd' : 'l' : 'w';
10961 used_prefixes |= (prefixes & PREFIX_DATA);
10962 }
10963 else if (sizeflag & SUFFIX_ALWAYS)
10964 *obufp++ = 'q';
10965 }
10966 else if (l == 1 && last[0] == 'L')
10967 {
10968 if ((prefixes & PREFIX_DATA)
10969 || (rex & REX_W)
10970 || (sizeflag & SUFFIX_ALWAYS))
10971 {
10972 USED_REX (REX_W);
10973 if (rex & REX_W)
10974 *obufp++ = 'q';
10975 else
10976 {
10977 if (sizeflag & DFLAG)
10978 *obufp++ = intel_syntax ? 'd' : 'l';
10979 else
10980 *obufp++ = 'w';
10981 used_prefixes |= (prefixes & PREFIX_DATA);
10982 }
10983 }
10984 }
10985 else
10986 abort ();
10987 break;
10988 case 'Q':
10989 if (l == 0)
10990 {
10991 if (intel_syntax && !alt)
10992 break;
10993 USED_REX (REX_W);
10994 if ((need_modrm && modrm.mod != 3)
10995 || (sizeflag & SUFFIX_ALWAYS))
10996 {
10997 if (rex & REX_W)
10998 *obufp++ = 'q';
10999 else
11000 {
11001 if (sizeflag & DFLAG)
11002 *obufp++ = intel_syntax ? 'd' : 'l';
11003 else
11004 *obufp++ = 'w';
11005 used_prefixes |= (prefixes & PREFIX_DATA);
11006 }
11007 }
11008 }
11009 else if (l == 1 && last[0] == 'D')
11010 *obufp++ = vex.w ? 'q' : 'd';
11011 else if (l == 1 && last[0] == 'L')
11012 {
11013 if (cond ? modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)
11014 : address_mode != mode_64bit)
11015 break;
11016 if ((rex & REX_W))
11017 {
11018 USED_REX (REX_W);
11019 *obufp++ = 'q';
11020 }
11021 else if((address_mode == mode_64bit && cond)
11022 || (sizeflag & SUFFIX_ALWAYS))
11023 *obufp++ = intel_syntax? 'd' : 'l';
11024 }
11025 else
11026 abort ();
11027 break;
11028 case 'R':
11029 USED_REX (REX_W);
11030 if (rex & REX_W)
11031 *obufp++ = 'q';
11032 else if (sizeflag & DFLAG)
11033 {
11034 if (intel_syntax)
11035 *obufp++ = 'd';
11036 else
11037 *obufp++ = 'l';
11038 }
11039 else
11040 *obufp++ = 'w';
11041 if (intel_syntax && !p[1]
11042 && ((rex & REX_W) || (sizeflag & DFLAG)))
11043 *obufp++ = 'e';
11044 if (!(rex & REX_W))
11045 used_prefixes |= (prefixes & PREFIX_DATA);
11046 break;
11047 case 'S':
11048 if (l == 0)
11049 {
11050 case_S:
11051 if (intel_syntax)
11052 break;
11053 if (sizeflag & SUFFIX_ALWAYS)
11054 {
11055 if (rex & REX_W)
11056 *obufp++ = 'q';
11057 else
11058 {
11059 if (sizeflag & DFLAG)
11060 *obufp++ = 'l';
11061 else
11062 *obufp++ = 'w';
11063 used_prefixes |= (prefixes & PREFIX_DATA);
11064 }
11065 }
11066 }
11067 else if (l == 1 && last[0] == 'L')
11068 {
11069 if (address_mode == mode_64bit
11070 && !(prefixes & PREFIX_ADDR))
11071 {
11072 *obufp++ = 'a';
11073 *obufp++ = 'b';
11074 *obufp++ = 's';
11075 }
11076
11077 goto case_S;
11078 }
11079 else
11080 abort ();
11081 break;
11082 case 'V':
11083 if (l == 0)
11084 abort ();
11085 else if (l == 1
11086 && (last[0] == 'L' || last[0] == 'X'))
11087 {
11088 if (last[0] == 'X')
11089 {
11090 *obufp++ = '{';
11091 *obufp++ = 'v';
11092 *obufp++ = 'e';
11093 *obufp++ = 'x';
11094 *obufp++ = '}';
11095 }
11096 else if (rex & REX_W)
11097 {
11098 *obufp++ = 'a';
11099 *obufp++ = 'b';
11100 *obufp++ = 's';
11101 }
11102 }
11103 else
11104 abort ();
11105 goto case_S;
11106 case 'W':
11107 if (l == 0)
11108 {
11109 /* operand size flag for cwtl, cbtw */
11110 USED_REX (REX_W);
11111 if (rex & REX_W)
11112 {
11113 if (intel_syntax)
11114 *obufp++ = 'd';
11115 else
11116 *obufp++ = 'l';
11117 }
11118 else if (sizeflag & DFLAG)
11119 *obufp++ = 'w';
11120 else
11121 *obufp++ = 'b';
11122 if (!(rex & REX_W))
11123 used_prefixes |= (prefixes & PREFIX_DATA);
11124 }
11125 else if (l == 1)
11126 {
11127 if (!need_vex)
11128 abort ();
11129 if (last[0] == 'X')
11130 *obufp++ = vex.w ? 'd': 's';
11131 else if (last[0] == 'B')
11132 *obufp++ = vex.w ? 'w': 'b';
11133 else
11134 abort ();
11135 }
11136 else
11137 abort ();
11138 break;
11139 case 'X':
11140 if (l != 0)
11141 abort ();
11142 if (need_vex
11143 ? vex.prefix == DATA_PREFIX_OPCODE
11144 : prefixes & PREFIX_DATA)
11145 {
11146 *obufp++ = 'd';
11147 used_prefixes |= PREFIX_DATA;
11148 }
11149 else
11150 *obufp++ = 's';
11151 break;
11152 case 'Y':
11153 if (l == 1 && last[0] == 'X')
11154 {
11155 if (!need_vex)
11156 abort ();
11157 if (intel_syntax
11158 || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
11159 break;
11160 switch (vex.length)
11161 {
11162 case 128:
11163 *obufp++ = 'x';
11164 break;
11165 case 256:
11166 *obufp++ = 'y';
11167 break;
11168 case 512:
11169 if (!vex.evex)
11170 default:
11171 abort ();
11172 }
11173 }
11174 else
11175 abort ();
11176 break;
11177 case 'Z':
11178 if (l == 0)
11179 {
11180 /* These insns ignore ModR/M.mod: Force it to 3 for OP_E(). */
11181 modrm.mod = 3;
11182 if (!intel_syntax && (sizeflag & SUFFIX_ALWAYS))
11183 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
11184 }
11185 else if (l == 1 && last[0] == 'X')
11186 {
11187 if (!need_vex || !vex.evex)
11188 abort ();
11189 if (intel_syntax
11190 || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
11191 break;
11192 switch (vex.length)
11193 {
11194 case 128:
11195 *obufp++ = 'x';
11196 break;
11197 case 256:
11198 *obufp++ = 'y';
11199 break;
11200 case 512:
11201 *obufp++ = 'z';
11202 break;
11203 default:
11204 abort ();
11205 }
11206 }
11207 else
11208 abort ();
11209 break;
11210 case '^':
11211 if (intel_syntax)
11212 break;
11213 if (isa64 == intel64 && (rex & REX_W))
11214 {
11215 USED_REX (REX_W);
11216 *obufp++ = 'q';
11217 break;
11218 }
11219 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
11220 {
11221 if (sizeflag & DFLAG)
11222 *obufp++ = 'l';
11223 else
11224 *obufp++ = 'w';
11225 used_prefixes |= (prefixes & PREFIX_DATA);
11226 }
11227 break;
11228 }
11229
11230 if (len == l)
11231 len = l = 0;
11232 }
11233 *obufp = 0;
11234 mnemonicendp = obufp;
11235 return 0;
11236 }
11237
11238 static void
11239 oappend (const char *s)
11240 {
11241 obufp = stpcpy (obufp, s);
11242 }
11243
11244 static void
11245 append_seg (void)
11246 {
11247 /* Only print the active segment register. */
11248 if (!active_seg_prefix)
11249 return;
11250
11251 used_prefixes |= active_seg_prefix;
11252 switch (active_seg_prefix)
11253 {
11254 case PREFIX_CS:
11255 oappend_maybe_intel ("%cs:");
11256 break;
11257 case PREFIX_DS:
11258 oappend_maybe_intel ("%ds:");
11259 break;
11260 case PREFIX_SS:
11261 oappend_maybe_intel ("%ss:");
11262 break;
11263 case PREFIX_ES:
11264 oappend_maybe_intel ("%es:");
11265 break;
11266 case PREFIX_FS:
11267 oappend_maybe_intel ("%fs:");
11268 break;
11269 case PREFIX_GS:
11270 oappend_maybe_intel ("%gs:");
11271 break;
11272 default:
11273 break;
11274 }
11275 }
11276
11277 static void
11278 OP_indirE (int bytemode, int sizeflag)
11279 {
11280 if (!intel_syntax)
11281 oappend ("*");
11282 OP_E (bytemode, sizeflag);
11283 }
11284
11285 static void
11286 print_operand_value (char *buf, int hex, bfd_vma disp)
11287 {
11288 if (address_mode == mode_64bit)
11289 {
11290 if (hex)
11291 {
11292 char tmp[30];
11293 int i;
11294 buf[0] = '0';
11295 buf[1] = 'x';
11296 sprintf_vma (tmp, disp);
11297 for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
11298 strcpy (buf + 2, tmp + i);
11299 }
11300 else
11301 {
11302 bfd_signed_vma v = disp;
11303 char tmp[30];
11304 int i;
11305 if (v < 0)
11306 {
11307 *(buf++) = '-';
11308 v = -disp;
11309 /* Check for possible overflow on 0x8000000000000000. */
11310 if (v < 0)
11311 {
11312 strcpy (buf, "9223372036854775808");
11313 return;
11314 }
11315 }
11316 if (!v)
11317 {
11318 strcpy (buf, "0");
11319 return;
11320 }
11321
11322 i = 0;
11323 tmp[29] = 0;
11324 while (v)
11325 {
11326 tmp[28 - i] = (v % 10) + '0';
11327 v /= 10;
11328 i++;
11329 }
11330 strcpy (buf, tmp + 29 - i);
11331 }
11332 }
11333 else
11334 {
11335 if (hex)
11336 sprintf (buf, "0x%x", (unsigned int) disp);
11337 else
11338 sprintf (buf, "%d", (int) disp);
11339 }
11340 }
11341
11342 /* Put DISP in BUF as signed hex number. */
11343
11344 static void
11345 print_displacement (char *buf, bfd_vma disp)
11346 {
11347 bfd_signed_vma val = disp;
11348 char tmp[30];
11349 int i, j = 0;
11350
11351 if (val < 0)
11352 {
11353 buf[j++] = '-';
11354 val = -disp;
11355
11356 /* Check for possible overflow. */
11357 if (val < 0)
11358 {
11359 switch (address_mode)
11360 {
11361 case mode_64bit:
11362 strcpy (buf + j, "0x8000000000000000");
11363 break;
11364 case mode_32bit:
11365 strcpy (buf + j, "0x80000000");
11366 break;
11367 case mode_16bit:
11368 strcpy (buf + j, "0x8000");
11369 break;
11370 }
11371 return;
11372 }
11373 }
11374
11375 buf[j++] = '0';
11376 buf[j++] = 'x';
11377
11378 sprintf_vma (tmp, (bfd_vma) val);
11379 for (i = 0; tmp[i] == '0'; i++)
11380 continue;
11381 if (tmp[i] == '\0')
11382 i--;
11383 strcpy (buf + j, tmp + i);
11384 }
11385
11386 static void
11387 intel_operand_size (int bytemode, int sizeflag)
11388 {
11389 if (vex.evex
11390 && vex.b
11391 && (bytemode == x_mode
11392 || bytemode == evex_half_bcst_xmmq_mode))
11393 {
11394 if (vex.w)
11395 oappend ("QWORD PTR ");
11396 else
11397 oappend ("DWORD PTR ");
11398 return;
11399 }
11400 switch (bytemode)
11401 {
11402 case b_mode:
11403 case b_swap_mode:
11404 case dqb_mode:
11405 case db_mode:
11406 oappend ("BYTE PTR ");
11407 break;
11408 case w_mode:
11409 case dw_mode:
11410 case dqw_mode:
11411 oappend ("WORD PTR ");
11412 break;
11413 case indir_v_mode:
11414 if (address_mode == mode_64bit && isa64 == intel64)
11415 {
11416 oappend ("QWORD PTR ");
11417 break;
11418 }
11419 /* Fall through. */
11420 case stack_v_mode:
11421 if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
11422 {
11423 oappend ("QWORD PTR ");
11424 break;
11425 }
11426 /* Fall through. */
11427 case v_mode:
11428 case v_swap_mode:
11429 case dq_mode:
11430 USED_REX (REX_W);
11431 if (rex & REX_W)
11432 oappend ("QWORD PTR ");
11433 else if (bytemode == dq_mode)
11434 oappend ("DWORD PTR ");
11435 else
11436 {
11437 if (sizeflag & DFLAG)
11438 oappend ("DWORD PTR ");
11439 else
11440 oappend ("WORD PTR ");
11441 used_prefixes |= (prefixes & PREFIX_DATA);
11442 }
11443 break;
11444 case z_mode:
11445 if ((rex & REX_W) || (sizeflag & DFLAG))
11446 *obufp++ = 'D';
11447 oappend ("WORD PTR ");
11448 if (!(rex & REX_W))
11449 used_prefixes |= (prefixes & PREFIX_DATA);
11450 break;
11451 case a_mode:
11452 if (sizeflag & DFLAG)
11453 oappend ("QWORD PTR ");
11454 else
11455 oappend ("DWORD PTR ");
11456 used_prefixes |= (prefixes & PREFIX_DATA);
11457 break;
11458 case movsxd_mode:
11459 if (!(sizeflag & DFLAG) && isa64 == intel64)
11460 oappend ("WORD PTR ");
11461 else
11462 oappend ("DWORD PTR ");
11463 used_prefixes |= (prefixes & PREFIX_DATA);
11464 break;
11465 case d_mode:
11466 case d_swap_mode:
11467 case dqd_mode:
11468 oappend ("DWORD PTR ");
11469 break;
11470 case q_mode:
11471 case q_swap_mode:
11472 oappend ("QWORD PTR ");
11473 break;
11474 case m_mode:
11475 if (address_mode == mode_64bit)
11476 oappend ("QWORD PTR ");
11477 else
11478 oappend ("DWORD PTR ");
11479 break;
11480 case f_mode:
11481 if (sizeflag & DFLAG)
11482 oappend ("FWORD PTR ");
11483 else
11484 oappend ("DWORD PTR ");
11485 used_prefixes |= (prefixes & PREFIX_DATA);
11486 break;
11487 case t_mode:
11488 oappend ("TBYTE PTR ");
11489 break;
11490 case x_mode:
11491 case x_swap_mode:
11492 case evex_x_gscat_mode:
11493 case evex_x_nobcst_mode:
11494 case bw_unit_mode:
11495 if (need_vex)
11496 {
11497 switch (vex.length)
11498 {
11499 case 128:
11500 oappend ("XMMWORD PTR ");
11501 break;
11502 case 256:
11503 oappend ("YMMWORD PTR ");
11504 break;
11505 case 512:
11506 oappend ("ZMMWORD PTR ");
11507 break;
11508 default:
11509 abort ();
11510 }
11511 }
11512 else
11513 oappend ("XMMWORD PTR ");
11514 break;
11515 case xmm_mode:
11516 oappend ("XMMWORD PTR ");
11517 break;
11518 case ymm_mode:
11519 oappend ("YMMWORD PTR ");
11520 break;
11521 case xmmq_mode:
11522 case evex_half_bcst_xmmq_mode:
11523 if (!need_vex)
11524 abort ();
11525
11526 switch (vex.length)
11527 {
11528 case 128:
11529 oappend ("QWORD PTR ");
11530 break;
11531 case 256:
11532 oappend ("XMMWORD PTR ");
11533 break;
11534 case 512:
11535 oappend ("YMMWORD PTR ");
11536 break;
11537 default:
11538 abort ();
11539 }
11540 break;
11541 case xmm_mb_mode:
11542 if (!need_vex)
11543 abort ();
11544
11545 switch (vex.length)
11546 {
11547 case 128:
11548 case 256:
11549 case 512:
11550 oappend ("BYTE PTR ");
11551 break;
11552 default:
11553 abort ();
11554 }
11555 break;
11556 case xmm_mw_mode:
11557 if (!need_vex)
11558 abort ();
11559
11560 switch (vex.length)
11561 {
11562 case 128:
11563 case 256:
11564 case 512:
11565 oappend ("WORD PTR ");
11566 break;
11567 default:
11568 abort ();
11569 }
11570 break;
11571 case xmm_md_mode:
11572 if (!need_vex)
11573 abort ();
11574
11575 switch (vex.length)
11576 {
11577 case 128:
11578 case 256:
11579 case 512:
11580 oappend ("DWORD PTR ");
11581 break;
11582 default:
11583 abort ();
11584 }
11585 break;
11586 case xmm_mq_mode:
11587 if (!need_vex)
11588 abort ();
11589
11590 switch (vex.length)
11591 {
11592 case 128:
11593 case 256:
11594 case 512:
11595 oappend ("QWORD PTR ");
11596 break;
11597 default:
11598 abort ();
11599 }
11600 break;
11601 case xmmdw_mode:
11602 if (!need_vex)
11603 abort ();
11604
11605 switch (vex.length)
11606 {
11607 case 128:
11608 oappend ("WORD PTR ");
11609 break;
11610 case 256:
11611 oappend ("DWORD PTR ");
11612 break;
11613 case 512:
11614 oappend ("QWORD PTR ");
11615 break;
11616 default:
11617 abort ();
11618 }
11619 break;
11620 case xmmqd_mode:
11621 if (!need_vex)
11622 abort ();
11623
11624 switch (vex.length)
11625 {
11626 case 128:
11627 oappend ("DWORD PTR ");
11628 break;
11629 case 256:
11630 oappend ("QWORD PTR ");
11631 break;
11632 case 512:
11633 oappend ("XMMWORD PTR ");
11634 break;
11635 default:
11636 abort ();
11637 }
11638 break;
11639 case ymmq_mode:
11640 if (!need_vex)
11641 abort ();
11642
11643 switch (vex.length)
11644 {
11645 case 128:
11646 oappend ("QWORD PTR ");
11647 break;
11648 case 256:
11649 oappend ("YMMWORD PTR ");
11650 break;
11651 case 512:
11652 oappend ("ZMMWORD PTR ");
11653 break;
11654 default:
11655 abort ();
11656 }
11657 break;
11658 case ymmxmm_mode:
11659 if (!need_vex)
11660 abort ();
11661
11662 switch (vex.length)
11663 {
11664 case 128:
11665 case 256:
11666 oappend ("XMMWORD PTR ");
11667 break;
11668 default:
11669 abort ();
11670 }
11671 break;
11672 case o_mode:
11673 oappend ("OWORD PTR ");
11674 break;
11675 case vex_scalar_w_dq_mode:
11676 if (!need_vex)
11677 abort ();
11678
11679 if (vex.w)
11680 oappend ("QWORD PTR ");
11681 else
11682 oappend ("DWORD PTR ");
11683 break;
11684 case vex_vsib_d_w_dq_mode:
11685 case vex_vsib_q_w_dq_mode:
11686 if (!need_vex)
11687 abort ();
11688
11689 if (!vex.evex)
11690 {
11691 if (vex.w)
11692 oappend ("QWORD PTR ");
11693 else
11694 oappend ("DWORD PTR ");
11695 }
11696 else
11697 {
11698 switch (vex.length)
11699 {
11700 case 128:
11701 oappend ("XMMWORD PTR ");
11702 break;
11703 case 256:
11704 oappend ("YMMWORD PTR ");
11705 break;
11706 case 512:
11707 oappend ("ZMMWORD PTR ");
11708 break;
11709 default:
11710 abort ();
11711 }
11712 }
11713 break;
11714 case vex_vsib_q_w_d_mode:
11715 case vex_vsib_d_w_d_mode:
11716 if (!need_vex || !vex.evex)
11717 abort ();
11718
11719 switch (vex.length)
11720 {
11721 case 128:
11722 oappend ("QWORD PTR ");
11723 break;
11724 case 256:
11725 oappend ("XMMWORD PTR ");
11726 break;
11727 case 512:
11728 oappend ("YMMWORD PTR ");
11729 break;
11730 default:
11731 abort ();
11732 }
11733
11734 break;
11735 case mask_bd_mode:
11736 if (!need_vex || vex.length != 128)
11737 abort ();
11738 if (vex.w)
11739 oappend ("DWORD PTR ");
11740 else
11741 oappend ("BYTE PTR ");
11742 break;
11743 case mask_mode:
11744 if (!need_vex)
11745 abort ();
11746 if (vex.w)
11747 oappend ("QWORD PTR ");
11748 else
11749 oappend ("WORD PTR ");
11750 break;
11751 case v_bnd_mode:
11752 case v_bndmk_mode:
11753 default:
11754 break;
11755 }
11756 }
11757
11758 static void
11759 OP_E_register (int bytemode, int sizeflag)
11760 {
11761 int reg = modrm.rm;
11762 const char **names;
11763
11764 USED_REX (REX_B);
11765 if ((rex & REX_B))
11766 reg += 8;
11767
11768 if ((sizeflag & SUFFIX_ALWAYS)
11769 && (bytemode == b_swap_mode
11770 || bytemode == bnd_swap_mode
11771 || bytemode == v_swap_mode))
11772 swap_operand ();
11773
11774 switch (bytemode)
11775 {
11776 case b_mode:
11777 case b_swap_mode:
11778 if (reg & 4)
11779 USED_REX (0);
11780 if (rex)
11781 names = names8rex;
11782 else
11783 names = names8;
11784 break;
11785 case w_mode:
11786 names = names16;
11787 break;
11788 case d_mode:
11789 case dw_mode:
11790 case db_mode:
11791 names = names32;
11792 break;
11793 case q_mode:
11794 names = names64;
11795 break;
11796 case m_mode:
11797 case v_bnd_mode:
11798 names = address_mode == mode_64bit ? names64 : names32;
11799 break;
11800 case bnd_mode:
11801 case bnd_swap_mode:
11802 if (reg > 0x3)
11803 {
11804 oappend ("(bad)");
11805 return;
11806 }
11807 names = names_bnd;
11808 break;
11809 case indir_v_mode:
11810 if (address_mode == mode_64bit && isa64 == intel64)
11811 {
11812 names = names64;
11813 break;
11814 }
11815 /* Fall through. */
11816 case stack_v_mode:
11817 if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
11818 {
11819 names = names64;
11820 break;
11821 }
11822 bytemode = v_mode;
11823 /* Fall through. */
11824 case v_mode:
11825 case v_swap_mode:
11826 case dq_mode:
11827 case dqb_mode:
11828 case dqd_mode:
11829 case dqw_mode:
11830 USED_REX (REX_W);
11831 if (rex & REX_W)
11832 names = names64;
11833 else if (bytemode != v_mode && bytemode != v_swap_mode)
11834 names = names32;
11835 else
11836 {
11837 if (sizeflag & DFLAG)
11838 names = names32;
11839 else
11840 names = names16;
11841 used_prefixes |= (prefixes & PREFIX_DATA);
11842 }
11843 break;
11844 case movsxd_mode:
11845 if (!(sizeflag & DFLAG) && isa64 == intel64)
11846 names = names16;
11847 else
11848 names = names32;
11849 used_prefixes |= (prefixes & PREFIX_DATA);
11850 break;
11851 case va_mode:
11852 names = (address_mode == mode_64bit
11853 ? names64 : names32);
11854 if (!(prefixes & PREFIX_ADDR))
11855 names = (address_mode == mode_16bit
11856 ? names16 : names);
11857 else
11858 {
11859 /* Remove "addr16/addr32". */
11860 all_prefixes[last_addr_prefix] = 0;
11861 names = (address_mode != mode_32bit
11862 ? names32 : names16);
11863 used_prefixes |= PREFIX_ADDR;
11864 }
11865 break;
11866 case mask_bd_mode:
11867 case mask_mode:
11868 if (reg > 0x7)
11869 {
11870 oappend ("(bad)");
11871 return;
11872 }
11873 names = names_mask;
11874 break;
11875 case 0:
11876 return;
11877 default:
11878 oappend (INTERNAL_DISASSEMBLER_ERROR);
11879 return;
11880 }
11881 oappend (names[reg]);
11882 }
11883
11884 static void
11885 OP_E_memory (int bytemode, int sizeflag)
11886 {
11887 bfd_vma disp = 0;
11888 int add = (rex & REX_B) ? 8 : 0;
11889 int riprel = 0;
11890 int shift;
11891
11892 if (vex.evex)
11893 {
11894 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
11895 if (vex.b
11896 && bytemode != x_mode
11897 && bytemode != xmmq_mode
11898 && bytemode != evex_half_bcst_xmmq_mode)
11899 {
11900 BadOp ();
11901 return;
11902 }
11903 switch (bytemode)
11904 {
11905 case dqw_mode:
11906 case dw_mode:
11907 case xmm_mw_mode:
11908 shift = 1;
11909 break;
11910 case dqb_mode:
11911 case db_mode:
11912 case xmm_mb_mode:
11913 shift = 0;
11914 break;
11915 case dq_mode:
11916 if (address_mode != mode_64bit)
11917 {
11918 case dqd_mode:
11919 case xmm_md_mode:
11920 case d_mode:
11921 case d_swap_mode:
11922 shift = 2;
11923 break;
11924 }
11925 /* fall through */
11926 case vex_scalar_w_dq_mode:
11927 case vex_vsib_d_w_dq_mode:
11928 case vex_vsib_d_w_d_mode:
11929 case vex_vsib_q_w_dq_mode:
11930 case vex_vsib_q_w_d_mode:
11931 case evex_x_gscat_mode:
11932 shift = vex.w ? 3 : 2;
11933 break;
11934 case x_mode:
11935 case evex_half_bcst_xmmq_mode:
11936 case xmmq_mode:
11937 if (vex.b)
11938 {
11939 shift = vex.w ? 3 : 2;
11940 break;
11941 }
11942 /* Fall through. */
11943 case xmmqd_mode:
11944 case xmmdw_mode:
11945 case ymmq_mode:
11946 case evex_x_nobcst_mode:
11947 case x_swap_mode:
11948 switch (vex.length)
11949 {
11950 case 128:
11951 shift = 4;
11952 break;
11953 case 256:
11954 shift = 5;
11955 break;
11956 case 512:
11957 shift = 6;
11958 break;
11959 default:
11960 abort ();
11961 }
11962 /* Make necessary corrections to shift for modes that need it. */
11963 if (bytemode == xmmq_mode
11964 || bytemode == evex_half_bcst_xmmq_mode
11965 || (bytemode == ymmq_mode && vex.length == 128))
11966 shift -= 1;
11967 else if (bytemode == xmmqd_mode)
11968 shift -= 2;
11969 else if (bytemode == xmmdw_mode)
11970 shift -= 3;
11971 break;
11972 case ymm_mode:
11973 shift = 5;
11974 break;
11975 case xmm_mode:
11976 shift = 4;
11977 break;
11978 case xmm_mq_mode:
11979 case q_mode:
11980 case q_swap_mode:
11981 shift = 3;
11982 break;
11983 case bw_unit_mode:
11984 shift = vex.w ? 1 : 0;
11985 break;
11986 default:
11987 abort ();
11988 }
11989 }
11990 else
11991 shift = 0;
11992
11993 USED_REX (REX_B);
11994 if (intel_syntax)
11995 intel_operand_size (bytemode, sizeflag);
11996 append_seg ();
11997
11998 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
11999 {
12000 /* 32/64 bit address mode */
12001 int havedisp;
12002 int havesib;
12003 int havebase;
12004 int haveindex;
12005 int needindex;
12006 int needaddr32;
12007 int base, rbase;
12008 int vindex = 0;
12009 int scale = 0;
12010 int addr32flag = !((sizeflag & AFLAG)
12011 || bytemode == v_bnd_mode
12012 || bytemode == v_bndmk_mode
12013 || bytemode == bnd_mode
12014 || bytemode == bnd_swap_mode);
12015 const char **indexes64 = names64;
12016 const char **indexes32 = names32;
12017
12018 havesib = 0;
12019 havebase = 1;
12020 haveindex = 0;
12021 base = modrm.rm;
12022
12023 if (base == 4)
12024 {
12025 havesib = 1;
12026 vindex = sib.index;
12027 USED_REX (REX_X);
12028 if (rex & REX_X)
12029 vindex += 8;
12030 switch (bytemode)
12031 {
12032 case vex_vsib_d_w_dq_mode:
12033 case vex_vsib_d_w_d_mode:
12034 case vex_vsib_q_w_dq_mode:
12035 case vex_vsib_q_w_d_mode:
12036 if (!need_vex)
12037 abort ();
12038 if (vex.evex)
12039 {
12040 if (!vex.v)
12041 vindex += 16;
12042 }
12043
12044 haveindex = 1;
12045 switch (vex.length)
12046 {
12047 case 128:
12048 indexes64 = indexes32 = names_xmm;
12049 break;
12050 case 256:
12051 if (!vex.w
12052 || bytemode == vex_vsib_q_w_dq_mode
12053 || bytemode == vex_vsib_q_w_d_mode)
12054 indexes64 = indexes32 = names_ymm;
12055 else
12056 indexes64 = indexes32 = names_xmm;
12057 break;
12058 case 512:
12059 if (!vex.w
12060 || bytemode == vex_vsib_q_w_dq_mode
12061 || bytemode == vex_vsib_q_w_d_mode)
12062 indexes64 = indexes32 = names_zmm;
12063 else
12064 indexes64 = indexes32 = names_ymm;
12065 break;
12066 default:
12067 abort ();
12068 }
12069 break;
12070 default:
12071 haveindex = vindex != 4;
12072 break;
12073 }
12074 scale = sib.scale;
12075 base = sib.base;
12076 codep++;
12077 }
12078 else
12079 {
12080 /* mandatory non-vector SIB must have sib */
12081 if (bytemode == vex_sibmem_mode)
12082 {
12083 oappend ("(bad)");
12084 return;
12085 }
12086 }
12087 rbase = base + add;
12088
12089 switch (modrm.mod)
12090 {
12091 case 0:
12092 if (base == 5)
12093 {
12094 havebase = 0;
12095 if (address_mode == mode_64bit && !havesib)
12096 riprel = 1;
12097 disp = get32s ();
12098 if (riprel && bytemode == v_bndmk_mode)
12099 {
12100 oappend ("(bad)");
12101 return;
12102 }
12103 }
12104 break;
12105 case 1:
12106 FETCH_DATA (the_info, codep + 1);
12107 disp = *codep++;
12108 if ((disp & 0x80) != 0)
12109 disp -= 0x100;
12110 if (vex.evex && shift > 0)
12111 disp <<= shift;
12112 break;
12113 case 2:
12114 disp = get32s ();
12115 break;
12116 }
12117
12118 needindex = 0;
12119 needaddr32 = 0;
12120 if (havesib
12121 && !havebase
12122 && !haveindex
12123 && address_mode != mode_16bit)
12124 {
12125 if (address_mode == mode_64bit)
12126 {
12127 if (addr32flag)
12128 {
12129 /* Without base nor index registers, zero-extend the
12130 lower 32-bit displacement to 64 bits. */
12131 disp = (unsigned int) disp;
12132 needindex = 1;
12133 }
12134 needaddr32 = 1;
12135 }
12136 else
12137 {
12138 /* In 32-bit mode, we need index register to tell [offset]
12139 from [eiz*1 + offset]. */
12140 needindex = 1;
12141 }
12142 }
12143
12144 havedisp = (havebase
12145 || needindex
12146 || (havesib && (haveindex || scale != 0)));
12147
12148 if (!intel_syntax)
12149 if (modrm.mod != 0 || base == 5)
12150 {
12151 if (havedisp || riprel)
12152 print_displacement (scratchbuf, disp);
12153 else
12154 print_operand_value (scratchbuf, 1, disp);
12155 oappend (scratchbuf);
12156 if (riprel)
12157 {
12158 set_op (disp, 1);
12159 oappend (!addr32flag ? "(%rip)" : "(%eip)");
12160 }
12161 }
12162
12163 if ((havebase || haveindex || needindex || needaddr32 || riprel)
12164 && (address_mode != mode_64bit
12165 || ((bytemode != v_bnd_mode)
12166 && (bytemode != v_bndmk_mode)
12167 && (bytemode != bnd_mode)
12168 && (bytemode != bnd_swap_mode))))
12169 used_prefixes |= PREFIX_ADDR;
12170
12171 if (havedisp || (intel_syntax && riprel))
12172 {
12173 *obufp++ = open_char;
12174 if (intel_syntax && riprel)
12175 {
12176 set_op (disp, 1);
12177 oappend (!addr32flag ? "rip" : "eip");
12178 }
12179 *obufp = '\0';
12180 if (havebase)
12181 oappend (address_mode == mode_64bit && !addr32flag
12182 ? names64[rbase] : names32[rbase]);
12183 if (havesib)
12184 {
12185 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
12186 print index to tell base + index from base. */
12187 if (scale != 0
12188 || needindex
12189 || haveindex
12190 || (havebase && base != ESP_REG_NUM))
12191 {
12192 if (!intel_syntax || havebase)
12193 {
12194 *obufp++ = separator_char;
12195 *obufp = '\0';
12196 }
12197 if (haveindex)
12198 oappend (address_mode == mode_64bit && !addr32flag
12199 ? indexes64[vindex] : indexes32[vindex]);
12200 else
12201 oappend (address_mode == mode_64bit && !addr32flag
12202 ? index64 : index32);
12203
12204 *obufp++ = scale_char;
12205 *obufp = '\0';
12206 sprintf (scratchbuf, "%d", 1 << scale);
12207 oappend (scratchbuf);
12208 }
12209 }
12210 if (intel_syntax
12211 && (disp || modrm.mod != 0 || base == 5))
12212 {
12213 if (!havedisp || (bfd_signed_vma) disp >= 0)
12214 {
12215 *obufp++ = '+';
12216 *obufp = '\0';
12217 }
12218 else if (modrm.mod != 1 && disp != -disp)
12219 {
12220 *obufp++ = '-';
12221 *obufp = '\0';
12222 disp = -disp;
12223 }
12224
12225 if (havedisp)
12226 print_displacement (scratchbuf, disp);
12227 else
12228 print_operand_value (scratchbuf, 1, disp);
12229 oappend (scratchbuf);
12230 }
12231
12232 *obufp++ = close_char;
12233 *obufp = '\0';
12234 }
12235 else if (intel_syntax)
12236 {
12237 if (modrm.mod != 0 || base == 5)
12238 {
12239 if (!active_seg_prefix)
12240 {
12241 oappend (names_seg[ds_reg - es_reg]);
12242 oappend (":");
12243 }
12244 print_operand_value (scratchbuf, 1, disp);
12245 oappend (scratchbuf);
12246 }
12247 }
12248 }
12249 else if (bytemode == v_bnd_mode
12250 || bytemode == v_bndmk_mode
12251 || bytemode == bnd_mode
12252 || bytemode == bnd_swap_mode)
12253 {
12254 oappend ("(bad)");
12255 return;
12256 }
12257 else
12258 {
12259 /* 16 bit address mode */
12260 used_prefixes |= prefixes & PREFIX_ADDR;
12261 switch (modrm.mod)
12262 {
12263 case 0:
12264 if (modrm.rm == 6)
12265 {
12266 disp = get16 ();
12267 if ((disp & 0x8000) != 0)
12268 disp -= 0x10000;
12269 }
12270 break;
12271 case 1:
12272 FETCH_DATA (the_info, codep + 1);
12273 disp = *codep++;
12274 if ((disp & 0x80) != 0)
12275 disp -= 0x100;
12276 if (vex.evex && shift > 0)
12277 disp <<= shift;
12278 break;
12279 case 2:
12280 disp = get16 ();
12281 if ((disp & 0x8000) != 0)
12282 disp -= 0x10000;
12283 break;
12284 }
12285
12286 if (!intel_syntax)
12287 if (modrm.mod != 0 || modrm.rm == 6)
12288 {
12289 print_displacement (scratchbuf, disp);
12290 oappend (scratchbuf);
12291 }
12292
12293 if (modrm.mod != 0 || modrm.rm != 6)
12294 {
12295 *obufp++ = open_char;
12296 *obufp = '\0';
12297 oappend (index16[modrm.rm]);
12298 if (intel_syntax
12299 && (disp || modrm.mod != 0 || modrm.rm == 6))
12300 {
12301 if ((bfd_signed_vma) disp >= 0)
12302 {
12303 *obufp++ = '+';
12304 *obufp = '\0';
12305 }
12306 else if (modrm.mod != 1)
12307 {
12308 *obufp++ = '-';
12309 *obufp = '\0';
12310 disp = -disp;
12311 }
12312
12313 print_displacement (scratchbuf, disp);
12314 oappend (scratchbuf);
12315 }
12316
12317 *obufp++ = close_char;
12318 *obufp = '\0';
12319 }
12320 else if (intel_syntax)
12321 {
12322 if (!active_seg_prefix)
12323 {
12324 oappend (names_seg[ds_reg - es_reg]);
12325 oappend (":");
12326 }
12327 print_operand_value (scratchbuf, 1, disp & 0xffff);
12328 oappend (scratchbuf);
12329 }
12330 }
12331 if (vex.evex && vex.b
12332 && (bytemode == x_mode
12333 || bytemode == xmmq_mode
12334 || bytemode == evex_half_bcst_xmmq_mode))
12335 {
12336 if (vex.w
12337 || bytemode == xmmq_mode
12338 || bytemode == evex_half_bcst_xmmq_mode)
12339 {
12340 switch (vex.length)
12341 {
12342 case 128:
12343 oappend ("{1to2}");
12344 break;
12345 case 256:
12346 oappend ("{1to4}");
12347 break;
12348 case 512:
12349 oappend ("{1to8}");
12350 break;
12351 default:
12352 abort ();
12353 }
12354 }
12355 else
12356 {
12357 switch (vex.length)
12358 {
12359 case 128:
12360 oappend ("{1to4}");
12361 break;
12362 case 256:
12363 oappend ("{1to8}");
12364 break;
12365 case 512:
12366 oappend ("{1to16}");
12367 break;
12368 default:
12369 abort ();
12370 }
12371 }
12372 }
12373 }
12374
12375 static void
12376 OP_E (int bytemode, int sizeflag)
12377 {
12378 /* Skip mod/rm byte. */
12379 MODRM_CHECK;
12380 codep++;
12381
12382 if (modrm.mod == 3)
12383 OP_E_register (bytemode, sizeflag);
12384 else
12385 OP_E_memory (bytemode, sizeflag);
12386 }
12387
12388 static void
12389 OP_G (int bytemode, int sizeflag)
12390 {
12391 int add = 0;
12392 const char **names;
12393 USED_REX (REX_R);
12394 if (rex & REX_R)
12395 add += 8;
12396 switch (bytemode)
12397 {
12398 case b_mode:
12399 if (modrm.reg & 4)
12400 USED_REX (0);
12401 if (rex)
12402 oappend (names8rex[modrm.reg + add]);
12403 else
12404 oappend (names8[modrm.reg + add]);
12405 break;
12406 case w_mode:
12407 oappend (names16[modrm.reg + add]);
12408 break;
12409 case d_mode:
12410 case db_mode:
12411 case dw_mode:
12412 oappend (names32[modrm.reg + add]);
12413 break;
12414 case q_mode:
12415 oappend (names64[modrm.reg + add]);
12416 break;
12417 case bnd_mode:
12418 if (modrm.reg > 0x3)
12419 {
12420 oappend ("(bad)");
12421 return;
12422 }
12423 oappend (names_bnd[modrm.reg]);
12424 break;
12425 case v_mode:
12426 case dq_mode:
12427 case dqb_mode:
12428 case dqd_mode:
12429 case dqw_mode:
12430 case movsxd_mode:
12431 USED_REX (REX_W);
12432 if (rex & REX_W)
12433 oappend (names64[modrm.reg + add]);
12434 else if (bytemode != v_mode && bytemode != movsxd_mode)
12435 oappend (names32[modrm.reg + add]);
12436 else
12437 {
12438 if (sizeflag & DFLAG)
12439 oappend (names32[modrm.reg + add]);
12440 else
12441 oappend (names16[modrm.reg + add]);
12442 used_prefixes |= (prefixes & PREFIX_DATA);
12443 }
12444 break;
12445 case va_mode:
12446 names = (address_mode == mode_64bit
12447 ? names64 : names32);
12448 if (!(prefixes & PREFIX_ADDR))
12449 {
12450 if (address_mode == mode_16bit)
12451 names = names16;
12452 }
12453 else
12454 {
12455 /* Remove "addr16/addr32". */
12456 all_prefixes[last_addr_prefix] = 0;
12457 names = (address_mode != mode_32bit
12458 ? names32 : names16);
12459 used_prefixes |= PREFIX_ADDR;
12460 }
12461 oappend (names[modrm.reg + add]);
12462 break;
12463 case m_mode:
12464 if (address_mode == mode_64bit)
12465 oappend (names64[modrm.reg + add]);
12466 else
12467 oappend (names32[modrm.reg + add]);
12468 break;
12469 case mask_bd_mode:
12470 case mask_mode:
12471 if ((modrm.reg + add) > 0x7)
12472 {
12473 oappend ("(bad)");
12474 return;
12475 }
12476 oappend (names_mask[modrm.reg + add]);
12477 break;
12478 default:
12479 oappend (INTERNAL_DISASSEMBLER_ERROR);
12480 break;
12481 }
12482 }
12483
12484 static bfd_vma
12485 get64 (void)
12486 {
12487 bfd_vma x;
12488 #ifdef BFD64
12489 unsigned int a;
12490 unsigned int b;
12491
12492 FETCH_DATA (the_info, codep + 8);
12493 a = *codep++ & 0xff;
12494 a |= (*codep++ & 0xff) << 8;
12495 a |= (*codep++ & 0xff) << 16;
12496 a |= (*codep++ & 0xffu) << 24;
12497 b = *codep++ & 0xff;
12498 b |= (*codep++ & 0xff) << 8;
12499 b |= (*codep++ & 0xff) << 16;
12500 b |= (*codep++ & 0xffu) << 24;
12501 x = a + ((bfd_vma) b << 32);
12502 #else
12503 abort ();
12504 x = 0;
12505 #endif
12506 return x;
12507 }
12508
12509 static bfd_signed_vma
12510 get32 (void)
12511 {
12512 bfd_vma x = 0;
12513
12514 FETCH_DATA (the_info, codep + 4);
12515 x = *codep++ & (bfd_vma) 0xff;
12516 x |= (*codep++ & (bfd_vma) 0xff) << 8;
12517 x |= (*codep++ & (bfd_vma) 0xff) << 16;
12518 x |= (*codep++ & (bfd_vma) 0xff) << 24;
12519 return x;
12520 }
12521
12522 static bfd_signed_vma
12523 get32s (void)
12524 {
12525 bfd_vma x = 0;
12526
12527 FETCH_DATA (the_info, codep + 4);
12528 x = *codep++ & (bfd_vma) 0xff;
12529 x |= (*codep++ & (bfd_vma) 0xff) << 8;
12530 x |= (*codep++ & (bfd_vma) 0xff) << 16;
12531 x |= (*codep++ & (bfd_vma) 0xff) << 24;
12532
12533 x = (x ^ ((bfd_vma) 1 << 31)) - ((bfd_vma) 1 << 31);
12534
12535 return x;
12536 }
12537
12538 static int
12539 get16 (void)
12540 {
12541 int x = 0;
12542
12543 FETCH_DATA (the_info, codep + 2);
12544 x = *codep++ & 0xff;
12545 x |= (*codep++ & 0xff) << 8;
12546 return x;
12547 }
12548
12549 static void
12550 set_op (bfd_vma op, int riprel)
12551 {
12552 op_index[op_ad] = op_ad;
12553 if (address_mode == mode_64bit)
12554 {
12555 op_address[op_ad] = op;
12556 op_riprel[op_ad] = riprel;
12557 }
12558 else
12559 {
12560 /* Mask to get a 32-bit address. */
12561 op_address[op_ad] = op & 0xffffffff;
12562 op_riprel[op_ad] = riprel & 0xffffffff;
12563 }
12564 }
12565
12566 static void
12567 OP_REG (int code, int sizeflag)
12568 {
12569 const char *s;
12570 int add;
12571
12572 switch (code)
12573 {
12574 case es_reg: case ss_reg: case cs_reg:
12575 case ds_reg: case fs_reg: case gs_reg:
12576 oappend (names_seg[code - es_reg]);
12577 return;
12578 }
12579
12580 USED_REX (REX_B);
12581 if (rex & REX_B)
12582 add = 8;
12583 else
12584 add = 0;
12585
12586 switch (code)
12587 {
12588 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
12589 case sp_reg: case bp_reg: case si_reg: case di_reg:
12590 s = names16[code - ax_reg + add];
12591 break;
12592 case ah_reg: case ch_reg: case dh_reg: case bh_reg:
12593 USED_REX (0);
12594 /* Fall through. */
12595 case al_reg: case cl_reg: case dl_reg: case bl_reg:
12596 if (rex)
12597 s = names8rex[code - al_reg + add];
12598 else
12599 s = names8[code - al_reg];
12600 break;
12601 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
12602 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
12603 if (address_mode == mode_64bit
12604 && ((sizeflag & DFLAG) || (rex & REX_W)))
12605 {
12606 s = names64[code - rAX_reg + add];
12607 break;
12608 }
12609 code += eAX_reg - rAX_reg;
12610 /* Fall through. */
12611 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
12612 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
12613 USED_REX (REX_W);
12614 if (rex & REX_W)
12615 s = names64[code - eAX_reg + add];
12616 else
12617 {
12618 if (sizeflag & DFLAG)
12619 s = names32[code - eAX_reg + add];
12620 else
12621 s = names16[code - eAX_reg + add];
12622 used_prefixes |= (prefixes & PREFIX_DATA);
12623 }
12624 break;
12625 default:
12626 s = INTERNAL_DISASSEMBLER_ERROR;
12627 break;
12628 }
12629 oappend (s);
12630 }
12631
12632 static void
12633 OP_IMREG (int code, int sizeflag)
12634 {
12635 const char *s;
12636
12637 switch (code)
12638 {
12639 case indir_dx_reg:
12640 if (intel_syntax)
12641 s = "dx";
12642 else
12643 s = "(%dx)";
12644 break;
12645 case al_reg: case cl_reg:
12646 s = names8[code - al_reg];
12647 break;
12648 case eAX_reg:
12649 USED_REX (REX_W);
12650 if (rex & REX_W)
12651 {
12652 s = *names64;
12653 break;
12654 }
12655 /* Fall through. */
12656 case z_mode_ax_reg:
12657 if ((rex & REX_W) || (sizeflag & DFLAG))
12658 s = *names32;
12659 else
12660 s = *names16;
12661 if (!(rex & REX_W))
12662 used_prefixes |= (prefixes & PREFIX_DATA);
12663 break;
12664 default:
12665 s = INTERNAL_DISASSEMBLER_ERROR;
12666 break;
12667 }
12668 oappend (s);
12669 }
12670
12671 static void
12672 OP_I (int bytemode, int sizeflag)
12673 {
12674 bfd_signed_vma op;
12675 bfd_signed_vma mask = -1;
12676
12677 switch (bytemode)
12678 {
12679 case b_mode:
12680 FETCH_DATA (the_info, codep + 1);
12681 op = *codep++;
12682 mask = 0xff;
12683 break;
12684 case v_mode:
12685 USED_REX (REX_W);
12686 if (rex & REX_W)
12687 op = get32s ();
12688 else
12689 {
12690 if (sizeflag & DFLAG)
12691 {
12692 op = get32 ();
12693 mask = 0xffffffff;
12694 }
12695 else
12696 {
12697 op = get16 ();
12698 mask = 0xfffff;
12699 }
12700 used_prefixes |= (prefixes & PREFIX_DATA);
12701 }
12702 break;
12703 case d_mode:
12704 mask = 0xffffffff;
12705 op = get32 ();
12706 break;
12707 case w_mode:
12708 mask = 0xfffff;
12709 op = get16 ();
12710 break;
12711 case const_1_mode:
12712 if (intel_syntax)
12713 oappend ("1");
12714 return;
12715 default:
12716 oappend (INTERNAL_DISASSEMBLER_ERROR);
12717 return;
12718 }
12719
12720 op &= mask;
12721 scratchbuf[0] = '$';
12722 print_operand_value (scratchbuf + 1, 1, op);
12723 oappend_maybe_intel (scratchbuf);
12724 scratchbuf[0] = '\0';
12725 }
12726
12727 static void
12728 OP_I64 (int bytemode, int sizeflag)
12729 {
12730 if (bytemode != v_mode || address_mode != mode_64bit || !(rex & REX_W))
12731 {
12732 OP_I (bytemode, sizeflag);
12733 return;
12734 }
12735
12736 USED_REX (REX_W);
12737
12738 scratchbuf[0] = '$';
12739 print_operand_value (scratchbuf + 1, 1, get64 ());
12740 oappend_maybe_intel (scratchbuf);
12741 scratchbuf[0] = '\0';
12742 }
12743
12744 static void
12745 OP_sI (int bytemode, int sizeflag)
12746 {
12747 bfd_signed_vma op;
12748
12749 switch (bytemode)
12750 {
12751 case b_mode:
12752 case b_T_mode:
12753 FETCH_DATA (the_info, codep + 1);
12754 op = *codep++;
12755 if ((op & 0x80) != 0)
12756 op -= 0x100;
12757 if (bytemode == b_T_mode)
12758 {
12759 if (address_mode != mode_64bit
12760 || !((sizeflag & DFLAG) || (rex & REX_W)))
12761 {
12762 /* The operand-size prefix is overridden by a REX prefix. */
12763 if ((sizeflag & DFLAG) || (rex & REX_W))
12764 op &= 0xffffffff;
12765 else
12766 op &= 0xffff;
12767 }
12768 }
12769 else
12770 {
12771 if (!(rex & REX_W))
12772 {
12773 if (sizeflag & DFLAG)
12774 op &= 0xffffffff;
12775 else
12776 op &= 0xffff;
12777 }
12778 }
12779 break;
12780 case v_mode:
12781 /* The operand-size prefix is overridden by a REX prefix. */
12782 if ((sizeflag & DFLAG) || (rex & REX_W))
12783 op = get32s ();
12784 else
12785 op = get16 ();
12786 break;
12787 default:
12788 oappend (INTERNAL_DISASSEMBLER_ERROR);
12789 return;
12790 }
12791
12792 scratchbuf[0] = '$';
12793 print_operand_value (scratchbuf + 1, 1, op);
12794 oappend_maybe_intel (scratchbuf);
12795 }
12796
12797 static void
12798 OP_J (int bytemode, int sizeflag)
12799 {
12800 bfd_vma disp;
12801 bfd_vma mask = -1;
12802 bfd_vma segment = 0;
12803
12804 switch (bytemode)
12805 {
12806 case b_mode:
12807 FETCH_DATA (the_info, codep + 1);
12808 disp = *codep++;
12809 if ((disp & 0x80) != 0)
12810 disp -= 0x100;
12811 break;
12812 case v_mode:
12813 case dqw_mode:
12814 if ((sizeflag & DFLAG)
12815 || (address_mode == mode_64bit
12816 && ((isa64 == intel64 && bytemode != dqw_mode)
12817 || (rex & REX_W))))
12818 disp = get32s ();
12819 else
12820 {
12821 disp = get16 ();
12822 if ((disp & 0x8000) != 0)
12823 disp -= 0x10000;
12824 /* In 16bit mode, address is wrapped around at 64k within
12825 the same segment. Otherwise, a data16 prefix on a jump
12826 instruction means that the pc is masked to 16 bits after
12827 the displacement is added! */
12828 mask = 0xffff;
12829 if ((prefixes & PREFIX_DATA) == 0)
12830 segment = ((start_pc + (codep - start_codep))
12831 & ~((bfd_vma) 0xffff));
12832 }
12833 if (address_mode != mode_64bit
12834 || (isa64 != intel64 && !(rex & REX_W)))
12835 used_prefixes |= (prefixes & PREFIX_DATA);
12836 break;
12837 default:
12838 oappend (INTERNAL_DISASSEMBLER_ERROR);
12839 return;
12840 }
12841 disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
12842 set_op (disp, 0);
12843 print_operand_value (scratchbuf, 1, disp);
12844 oappend (scratchbuf);
12845 }
12846
12847 static void
12848 OP_SEG (int bytemode, int sizeflag)
12849 {
12850 if (bytemode == w_mode)
12851 oappend (names_seg[modrm.reg]);
12852 else
12853 OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
12854 }
12855
12856 static void
12857 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
12858 {
12859 int seg, offset;
12860
12861 if (sizeflag & DFLAG)
12862 {
12863 offset = get32 ();
12864 seg = get16 ();
12865 }
12866 else
12867 {
12868 offset = get16 ();
12869 seg = get16 ();
12870 }
12871 used_prefixes |= (prefixes & PREFIX_DATA);
12872 if (intel_syntax)
12873 sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
12874 else
12875 sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
12876 oappend (scratchbuf);
12877 }
12878
12879 static void
12880 OP_OFF (int bytemode, int sizeflag)
12881 {
12882 bfd_vma off;
12883
12884 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12885 intel_operand_size (bytemode, sizeflag);
12886 append_seg ();
12887
12888 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
12889 off = get32 ();
12890 else
12891 off = get16 ();
12892
12893 if (intel_syntax)
12894 {
12895 if (!active_seg_prefix)
12896 {
12897 oappend (names_seg[ds_reg - es_reg]);
12898 oappend (":");
12899 }
12900 }
12901 print_operand_value (scratchbuf, 1, off);
12902 oappend (scratchbuf);
12903 }
12904
12905 static void
12906 OP_OFF64 (int bytemode, int sizeflag)
12907 {
12908 bfd_vma off;
12909
12910 if (address_mode != mode_64bit
12911 || (prefixes & PREFIX_ADDR))
12912 {
12913 OP_OFF (bytemode, sizeflag);
12914 return;
12915 }
12916
12917 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12918 intel_operand_size (bytemode, sizeflag);
12919 append_seg ();
12920
12921 off = get64 ();
12922
12923 if (intel_syntax)
12924 {
12925 if (!active_seg_prefix)
12926 {
12927 oappend (names_seg[ds_reg - es_reg]);
12928 oappend (":");
12929 }
12930 }
12931 print_operand_value (scratchbuf, 1, off);
12932 oappend (scratchbuf);
12933 }
12934
12935 static void
12936 ptr_reg (int code, int sizeflag)
12937 {
12938 const char *s;
12939
12940 *obufp++ = open_char;
12941 used_prefixes |= (prefixes & PREFIX_ADDR);
12942 if (address_mode == mode_64bit)
12943 {
12944 if (!(sizeflag & AFLAG))
12945 s = names32[code - eAX_reg];
12946 else
12947 s = names64[code - eAX_reg];
12948 }
12949 else if (sizeflag & AFLAG)
12950 s = names32[code - eAX_reg];
12951 else
12952 s = names16[code - eAX_reg];
12953 oappend (s);
12954 *obufp++ = close_char;
12955 *obufp = 0;
12956 }
12957
12958 static void
12959 OP_ESreg (int code, int sizeflag)
12960 {
12961 if (intel_syntax)
12962 {
12963 switch (codep[-1])
12964 {
12965 case 0x6d: /* insw/insl */
12966 intel_operand_size (z_mode, sizeflag);
12967 break;
12968 case 0xa5: /* movsw/movsl/movsq */
12969 case 0xa7: /* cmpsw/cmpsl/cmpsq */
12970 case 0xab: /* stosw/stosl */
12971 case 0xaf: /* scasw/scasl */
12972 intel_operand_size (v_mode, sizeflag);
12973 break;
12974 default:
12975 intel_operand_size (b_mode, sizeflag);
12976 }
12977 }
12978 oappend_maybe_intel ("%es:");
12979 ptr_reg (code, sizeflag);
12980 }
12981
12982 static void
12983 OP_DSreg (int code, int sizeflag)
12984 {
12985 if (intel_syntax)
12986 {
12987 switch (codep[-1])
12988 {
12989 case 0x6f: /* outsw/outsl */
12990 intel_operand_size (z_mode, sizeflag);
12991 break;
12992 case 0xa5: /* movsw/movsl/movsq */
12993 case 0xa7: /* cmpsw/cmpsl/cmpsq */
12994 case 0xad: /* lodsw/lodsl/lodsq */
12995 intel_operand_size (v_mode, sizeflag);
12996 break;
12997 default:
12998 intel_operand_size (b_mode, sizeflag);
12999 }
13000 }
13001 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
13002 default segment register DS is printed. */
13003 if (!active_seg_prefix)
13004 active_seg_prefix = PREFIX_DS;
13005 append_seg ();
13006 ptr_reg (code, sizeflag);
13007 }
13008
13009 static void
13010 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13011 {
13012 int add;
13013 if (rex & REX_R)
13014 {
13015 USED_REX (REX_R);
13016 add = 8;
13017 }
13018 else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
13019 {
13020 all_prefixes[last_lock_prefix] = 0;
13021 used_prefixes |= PREFIX_LOCK;
13022 add = 8;
13023 }
13024 else
13025 add = 0;
13026 sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
13027 oappend_maybe_intel (scratchbuf);
13028 }
13029
13030 static void
13031 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13032 {
13033 int add;
13034 USED_REX (REX_R);
13035 if (rex & REX_R)
13036 add = 8;
13037 else
13038 add = 0;
13039 if (intel_syntax)
13040 sprintf (scratchbuf, "dr%d", modrm.reg + add);
13041 else
13042 sprintf (scratchbuf, "%%db%d", modrm.reg + add);
13043 oappend (scratchbuf);
13044 }
13045
13046 static void
13047 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13048 {
13049 sprintf (scratchbuf, "%%tr%d", modrm.reg);
13050 oappend_maybe_intel (scratchbuf);
13051 }
13052
13053 static void
13054 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13055 {
13056 int reg = modrm.reg;
13057 const char **names;
13058
13059 used_prefixes |= (prefixes & PREFIX_DATA);
13060 if (prefixes & PREFIX_DATA)
13061 {
13062 names = names_xmm;
13063 USED_REX (REX_R);
13064 if (rex & REX_R)
13065 reg += 8;
13066 }
13067 else
13068 names = names_mm;
13069 oappend (names[reg]);
13070 }
13071
13072 static void
13073 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13074 {
13075 int reg = modrm.reg;
13076 const char **names;
13077
13078 USED_REX (REX_R);
13079 if (rex & REX_R)
13080 reg += 8;
13081 if (vex.evex)
13082 {
13083 if (!vex.r)
13084 reg += 16;
13085 }
13086
13087 if (need_vex
13088 && bytemode != xmm_mode
13089 && bytemode != xmmq_mode
13090 && bytemode != evex_half_bcst_xmmq_mode
13091 && bytemode != ymm_mode
13092 && bytemode != tmm_mode
13093 && bytemode != scalar_mode)
13094 {
13095 switch (vex.length)
13096 {
13097 case 128:
13098 names = names_xmm;
13099 break;
13100 case 256:
13101 if (vex.w
13102 || (bytemode != vex_vsib_q_w_dq_mode
13103 && bytemode != vex_vsib_q_w_d_mode))
13104 names = names_ymm;
13105 else
13106 names = names_xmm;
13107 break;
13108 case 512:
13109 names = names_zmm;
13110 break;
13111 default:
13112 abort ();
13113 }
13114 }
13115 else if (bytemode == xmmq_mode
13116 || bytemode == evex_half_bcst_xmmq_mode)
13117 {
13118 switch (vex.length)
13119 {
13120 case 128:
13121 case 256:
13122 names = names_xmm;
13123 break;
13124 case 512:
13125 names = names_ymm;
13126 break;
13127 default:
13128 abort ();
13129 }
13130 }
13131 else if (bytemode == tmm_mode)
13132 {
13133 modrm.reg = reg;
13134 if (reg >= 8)
13135 {
13136 oappend ("(bad)");
13137 return;
13138 }
13139 names = names_tmm;
13140 }
13141 else if (bytemode == ymm_mode)
13142 names = names_ymm;
13143 else
13144 names = names_xmm;
13145 oappend (names[reg]);
13146 }
13147
13148 static void
13149 OP_EM (int bytemode, int sizeflag)
13150 {
13151 int reg;
13152 const char **names;
13153
13154 if (modrm.mod != 3)
13155 {
13156 if (intel_syntax
13157 && (bytemode == v_mode || bytemode == v_swap_mode))
13158 {
13159 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
13160 used_prefixes |= (prefixes & PREFIX_DATA);
13161 }
13162 OP_E (bytemode, sizeflag);
13163 return;
13164 }
13165
13166 if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
13167 swap_operand ();
13168
13169 /* Skip mod/rm byte. */
13170 MODRM_CHECK;
13171 codep++;
13172 used_prefixes |= (prefixes & PREFIX_DATA);
13173 reg = modrm.rm;
13174 if (prefixes & PREFIX_DATA)
13175 {
13176 names = names_xmm;
13177 USED_REX (REX_B);
13178 if (rex & REX_B)
13179 reg += 8;
13180 }
13181 else
13182 names = names_mm;
13183 oappend (names[reg]);
13184 }
13185
13186 /* cvt* are the only instructions in sse2 which have
13187 both SSE and MMX operands and also have 0x66 prefix
13188 in their opcode. 0x66 was originally used to differentiate
13189 between SSE and MMX instruction(operands). So we have to handle the
13190 cvt* separately using OP_EMC and OP_MXC */
13191 static void
13192 OP_EMC (int bytemode, int sizeflag)
13193 {
13194 if (modrm.mod != 3)
13195 {
13196 if (intel_syntax && bytemode == v_mode)
13197 {
13198 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
13199 used_prefixes |= (prefixes & PREFIX_DATA);
13200 }
13201 OP_E (bytemode, sizeflag);
13202 return;
13203 }
13204
13205 /* Skip mod/rm byte. */
13206 MODRM_CHECK;
13207 codep++;
13208 used_prefixes |= (prefixes & PREFIX_DATA);
13209 oappend (names_mm[modrm.rm]);
13210 }
13211
13212 static void
13213 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13214 {
13215 used_prefixes |= (prefixes & PREFIX_DATA);
13216 oappend (names_mm[modrm.reg]);
13217 }
13218
13219 static void
13220 OP_EX (int bytemode, int sizeflag)
13221 {
13222 int reg;
13223 const char **names;
13224
13225 /* Skip mod/rm byte. */
13226 MODRM_CHECK;
13227 codep++;
13228
13229 if (modrm.mod != 3)
13230 {
13231 OP_E_memory (bytemode, sizeflag);
13232 return;
13233 }
13234
13235 reg = modrm.rm;
13236 USED_REX (REX_B);
13237 if (rex & REX_B)
13238 reg += 8;
13239 if (vex.evex)
13240 {
13241 USED_REX (REX_X);
13242 if ((rex & REX_X))
13243 reg += 16;
13244 }
13245
13246 if ((sizeflag & SUFFIX_ALWAYS)
13247 && (bytemode == x_swap_mode
13248 || bytemode == d_swap_mode
13249 || bytemode == q_swap_mode))
13250 swap_operand ();
13251
13252 if (need_vex
13253 && bytemode != xmm_mode
13254 && bytemode != xmmdw_mode
13255 && bytemode != xmmqd_mode
13256 && bytemode != xmm_mb_mode
13257 && bytemode != xmm_mw_mode
13258 && bytemode != xmm_md_mode
13259 && bytemode != xmm_mq_mode
13260 && bytemode != xmmq_mode
13261 && bytemode != evex_half_bcst_xmmq_mode
13262 && bytemode != ymm_mode
13263 && bytemode != tmm_mode
13264 && bytemode != vex_scalar_w_dq_mode)
13265 {
13266 switch (vex.length)
13267 {
13268 case 128:
13269 names = names_xmm;
13270 break;
13271 case 256:
13272 names = names_ymm;
13273 break;
13274 case 512:
13275 names = names_zmm;
13276 break;
13277 default:
13278 abort ();
13279 }
13280 }
13281 else if (bytemode == xmmq_mode
13282 || bytemode == evex_half_bcst_xmmq_mode)
13283 {
13284 switch (vex.length)
13285 {
13286 case 128:
13287 case 256:
13288 names = names_xmm;
13289 break;
13290 case 512:
13291 names = names_ymm;
13292 break;
13293 default:
13294 abort ();
13295 }
13296 }
13297 else if (bytemode == tmm_mode)
13298 {
13299 modrm.rm = reg;
13300 if (reg >= 8)
13301 {
13302 oappend ("(bad)");
13303 return;
13304 }
13305 names = names_tmm;
13306 }
13307 else if (bytemode == ymm_mode)
13308 names = names_ymm;
13309 else
13310 names = names_xmm;
13311 oappend (names[reg]);
13312 }
13313
13314 static void
13315 OP_MS (int bytemode, int sizeflag)
13316 {
13317 if (modrm.mod == 3)
13318 OP_EM (bytemode, sizeflag);
13319 else
13320 BadOp ();
13321 }
13322
13323 static void
13324 OP_XS (int bytemode, int sizeflag)
13325 {
13326 if (modrm.mod == 3)
13327 OP_EX (bytemode, sizeflag);
13328 else
13329 BadOp ();
13330 }
13331
13332 static void
13333 OP_M (int bytemode, int sizeflag)
13334 {
13335 if (modrm.mod == 3)
13336 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
13337 BadOp ();
13338 else
13339 OP_E (bytemode, sizeflag);
13340 }
13341
13342 static void
13343 OP_0f07 (int bytemode, int sizeflag)
13344 {
13345 if (modrm.mod != 3 || modrm.rm != 0)
13346 BadOp ();
13347 else
13348 OP_E (bytemode, sizeflag);
13349 }
13350
13351 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
13352 32bit mode and "xchg %rax,%rax" in 64bit mode. */
13353
13354 static void
13355 NOP_Fixup1 (int bytemode, int sizeflag)
13356 {
13357 if ((prefixes & PREFIX_DATA) != 0
13358 || (rex != 0
13359 && rex != 0x48
13360 && address_mode == mode_64bit))
13361 OP_REG (bytemode, sizeflag);
13362 else
13363 strcpy (obuf, "nop");
13364 }
13365
13366 static void
13367 NOP_Fixup2 (int bytemode, int sizeflag)
13368 {
13369 if ((prefixes & PREFIX_DATA) != 0
13370 || (rex != 0
13371 && rex != 0x48
13372 && address_mode == mode_64bit))
13373 OP_IMREG (bytemode, sizeflag);
13374 }
13375
13376 static const char *const Suffix3DNow[] = {
13377 /* 00 */ NULL, NULL, NULL, NULL,
13378 /* 04 */ NULL, NULL, NULL, NULL,
13379 /* 08 */ NULL, NULL, NULL, NULL,
13380 /* 0C */ "pi2fw", "pi2fd", NULL, NULL,
13381 /* 10 */ NULL, NULL, NULL, NULL,
13382 /* 14 */ NULL, NULL, NULL, NULL,
13383 /* 18 */ NULL, NULL, NULL, NULL,
13384 /* 1C */ "pf2iw", "pf2id", NULL, NULL,
13385 /* 20 */ NULL, NULL, NULL, NULL,
13386 /* 24 */ NULL, NULL, NULL, NULL,
13387 /* 28 */ NULL, NULL, NULL, NULL,
13388 /* 2C */ NULL, NULL, NULL, NULL,
13389 /* 30 */ NULL, NULL, NULL, NULL,
13390 /* 34 */ NULL, NULL, NULL, NULL,
13391 /* 38 */ NULL, NULL, NULL, NULL,
13392 /* 3C */ NULL, NULL, NULL, NULL,
13393 /* 40 */ NULL, NULL, NULL, NULL,
13394 /* 44 */ NULL, NULL, NULL, NULL,
13395 /* 48 */ NULL, NULL, NULL, NULL,
13396 /* 4C */ NULL, NULL, NULL, NULL,
13397 /* 50 */ NULL, NULL, NULL, NULL,
13398 /* 54 */ NULL, NULL, NULL, NULL,
13399 /* 58 */ NULL, NULL, NULL, NULL,
13400 /* 5C */ NULL, NULL, NULL, NULL,
13401 /* 60 */ NULL, NULL, NULL, NULL,
13402 /* 64 */ NULL, NULL, NULL, NULL,
13403 /* 68 */ NULL, NULL, NULL, NULL,
13404 /* 6C */ NULL, NULL, NULL, NULL,
13405 /* 70 */ NULL, NULL, NULL, NULL,
13406 /* 74 */ NULL, NULL, NULL, NULL,
13407 /* 78 */ NULL, NULL, NULL, NULL,
13408 /* 7C */ NULL, NULL, NULL, NULL,
13409 /* 80 */ NULL, NULL, NULL, NULL,
13410 /* 84 */ NULL, NULL, NULL, NULL,
13411 /* 88 */ NULL, NULL, "pfnacc", NULL,
13412 /* 8C */ NULL, NULL, "pfpnacc", NULL,
13413 /* 90 */ "pfcmpge", NULL, NULL, NULL,
13414 /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt",
13415 /* 98 */ NULL, NULL, "pfsub", NULL,
13416 /* 9C */ NULL, NULL, "pfadd", NULL,
13417 /* A0 */ "pfcmpgt", NULL, NULL, NULL,
13418 /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1",
13419 /* A8 */ NULL, NULL, "pfsubr", NULL,
13420 /* AC */ NULL, NULL, "pfacc", NULL,
13421 /* B0 */ "pfcmpeq", NULL, NULL, NULL,
13422 /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw",
13423 /* B8 */ NULL, NULL, NULL, "pswapd",
13424 /* BC */ NULL, NULL, NULL, "pavgusb",
13425 /* C0 */ NULL, NULL, NULL, NULL,
13426 /* C4 */ NULL, NULL, NULL, NULL,
13427 /* C8 */ NULL, NULL, NULL, NULL,
13428 /* CC */ NULL, NULL, NULL, NULL,
13429 /* D0 */ NULL, NULL, NULL, NULL,
13430 /* D4 */ NULL, NULL, NULL, NULL,
13431 /* D8 */ NULL, NULL, NULL, NULL,
13432 /* DC */ NULL, NULL, NULL, NULL,
13433 /* E0 */ NULL, NULL, NULL, NULL,
13434 /* E4 */ NULL, NULL, NULL, NULL,
13435 /* E8 */ NULL, NULL, NULL, NULL,
13436 /* EC */ NULL, NULL, NULL, NULL,
13437 /* F0 */ NULL, NULL, NULL, NULL,
13438 /* F4 */ NULL, NULL, NULL, NULL,
13439 /* F8 */ NULL, NULL, NULL, NULL,
13440 /* FC */ NULL, NULL, NULL, NULL,
13441 };
13442
13443 static void
13444 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13445 {
13446 const char *mnemonic;
13447
13448 FETCH_DATA (the_info, codep + 1);
13449 /* AMD 3DNow! instructions are specified by an opcode suffix in the
13450 place where an 8-bit immediate would normally go. ie. the last
13451 byte of the instruction. */
13452 obufp = mnemonicendp;
13453 mnemonic = Suffix3DNow[*codep++ & 0xff];
13454 if (mnemonic)
13455 oappend (mnemonic);
13456 else
13457 {
13458 /* Since a variable sized modrm/sib chunk is between the start
13459 of the opcode (0x0f0f) and the opcode suffix, we need to do
13460 all the modrm processing first, and don't know until now that
13461 we have a bad opcode. This necessitates some cleaning up. */
13462 op_out[0][0] = '\0';
13463 op_out[1][0] = '\0';
13464 BadOp ();
13465 }
13466 mnemonicendp = obufp;
13467 }
13468
13469 static const struct op simd_cmp_op[] =
13470 {
13471 { STRING_COMMA_LEN ("eq") },
13472 { STRING_COMMA_LEN ("lt") },
13473 { STRING_COMMA_LEN ("le") },
13474 { STRING_COMMA_LEN ("unord") },
13475 { STRING_COMMA_LEN ("neq") },
13476 { STRING_COMMA_LEN ("nlt") },
13477 { STRING_COMMA_LEN ("nle") },
13478 { STRING_COMMA_LEN ("ord") }
13479 };
13480
13481 static const struct op vex_cmp_op[] =
13482 {
13483 { STRING_COMMA_LEN ("eq_uq") },
13484 { STRING_COMMA_LEN ("nge") },
13485 { STRING_COMMA_LEN ("ngt") },
13486 { STRING_COMMA_LEN ("false") },
13487 { STRING_COMMA_LEN ("neq_oq") },
13488 { STRING_COMMA_LEN ("ge") },
13489 { STRING_COMMA_LEN ("gt") },
13490 { STRING_COMMA_LEN ("true") },
13491 { STRING_COMMA_LEN ("eq_os") },
13492 { STRING_COMMA_LEN ("lt_oq") },
13493 { STRING_COMMA_LEN ("le_oq") },
13494 { STRING_COMMA_LEN ("unord_s") },
13495 { STRING_COMMA_LEN ("neq_us") },
13496 { STRING_COMMA_LEN ("nlt_uq") },
13497 { STRING_COMMA_LEN ("nle_uq") },
13498 { STRING_COMMA_LEN ("ord_s") },
13499 { STRING_COMMA_LEN ("eq_us") },
13500 { STRING_COMMA_LEN ("nge_uq") },
13501 { STRING_COMMA_LEN ("ngt_uq") },
13502 { STRING_COMMA_LEN ("false_os") },
13503 { STRING_COMMA_LEN ("neq_os") },
13504 { STRING_COMMA_LEN ("ge_oq") },
13505 { STRING_COMMA_LEN ("gt_oq") },
13506 { STRING_COMMA_LEN ("true_us") },
13507 };
13508
13509 static void
13510 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13511 {
13512 unsigned int cmp_type;
13513
13514 FETCH_DATA (the_info, codep + 1);
13515 cmp_type = *codep++ & 0xff;
13516 if (cmp_type < ARRAY_SIZE (simd_cmp_op))
13517 {
13518 char suffix [3];
13519 char *p = mnemonicendp - 2;
13520 suffix[0] = p[0];
13521 suffix[1] = p[1];
13522 suffix[2] = '\0';
13523 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13524 mnemonicendp += simd_cmp_op[cmp_type].len;
13525 }
13526 else if (need_vex
13527 && cmp_type < ARRAY_SIZE (simd_cmp_op) + ARRAY_SIZE (vex_cmp_op))
13528 {
13529 char suffix [3];
13530 char *p = mnemonicendp - 2;
13531 suffix[0] = p[0];
13532 suffix[1] = p[1];
13533 suffix[2] = '\0';
13534 cmp_type -= ARRAY_SIZE (simd_cmp_op);
13535 sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
13536 mnemonicendp += vex_cmp_op[cmp_type].len;
13537 }
13538 else
13539 {
13540 /* We have a reserved extension byte. Output it directly. */
13541 scratchbuf[0] = '$';
13542 print_operand_value (scratchbuf + 1, 1, cmp_type);
13543 oappend_maybe_intel (scratchbuf);
13544 scratchbuf[0] = '\0';
13545 }
13546 }
13547
13548 static void
13549 OP_Mwait (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13550 {
13551 /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx */
13552 if (!intel_syntax)
13553 {
13554 strcpy (op_out[0], names32[0]);
13555 strcpy (op_out[1], names32[1]);
13556 if (bytemode == eBX_reg)
13557 strcpy (op_out[2], names32[3]);
13558 two_source_ops = 1;
13559 }
13560 /* Skip mod/rm byte. */
13561 MODRM_CHECK;
13562 codep++;
13563 }
13564
13565 static void
13566 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
13567 int sizeflag ATTRIBUTE_UNUSED)
13568 {
13569 /* monitor %{e,r,}ax,%ecx,%edx" */
13570 if (!intel_syntax)
13571 {
13572 const char **names = (address_mode == mode_64bit
13573 ? names64 : names32);
13574
13575 if (prefixes & PREFIX_ADDR)
13576 {
13577 /* Remove "addr16/addr32". */
13578 all_prefixes[last_addr_prefix] = 0;
13579 names = (address_mode != mode_32bit
13580 ? names32 : names16);
13581 used_prefixes |= PREFIX_ADDR;
13582 }
13583 else if (address_mode == mode_16bit)
13584 names = names16;
13585 strcpy (op_out[0], names[0]);
13586 strcpy (op_out[1], names32[1]);
13587 strcpy (op_out[2], names32[2]);
13588 two_source_ops = 1;
13589 }
13590 /* Skip mod/rm byte. */
13591 MODRM_CHECK;
13592 codep++;
13593 }
13594
13595 static void
13596 BadOp (void)
13597 {
13598 /* Throw away prefixes and 1st. opcode byte. */
13599 codep = insn_codep + 1;
13600 oappend ("(bad)");
13601 }
13602
13603 static void
13604 REP_Fixup (int bytemode, int sizeflag)
13605 {
13606 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
13607 lods and stos. */
13608 if (prefixes & PREFIX_REPZ)
13609 all_prefixes[last_repz_prefix] = REP_PREFIX;
13610
13611 switch (bytemode)
13612 {
13613 case al_reg:
13614 case eAX_reg:
13615 case indir_dx_reg:
13616 OP_IMREG (bytemode, sizeflag);
13617 break;
13618 case eDI_reg:
13619 OP_ESreg (bytemode, sizeflag);
13620 break;
13621 case eSI_reg:
13622 OP_DSreg (bytemode, sizeflag);
13623 break;
13624 default:
13625 abort ();
13626 break;
13627 }
13628 }
13629
13630 static void
13631 SEP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13632 {
13633 if ( isa64 != amd64 )
13634 return;
13635
13636 obufp = obuf;
13637 BadOp ();
13638 mnemonicendp = obufp;
13639 ++codep;
13640 }
13641
13642 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
13643 "bnd". */
13644
13645 static void
13646 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13647 {
13648 if (prefixes & PREFIX_REPNZ)
13649 all_prefixes[last_repnz_prefix] = BND_PREFIX;
13650 }
13651
13652 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
13653 "notrack". */
13654
13655 static void
13656 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
13657 int sizeflag ATTRIBUTE_UNUSED)
13658 {
13659 if (active_seg_prefix == PREFIX_DS
13660 && (address_mode != mode_64bit || last_data_prefix < 0))
13661 {
13662 /* NOTRACK prefix is only valid on indirect branch instructions.
13663 NB: DATA prefix is unsupported for Intel64. */
13664 active_seg_prefix = 0;
13665 all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
13666 }
13667 }
13668
13669 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
13670 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
13671 */
13672
13673 static void
13674 HLE_Fixup1 (int bytemode, int sizeflag)
13675 {
13676 if (modrm.mod != 3
13677 && (prefixes & PREFIX_LOCK) != 0)
13678 {
13679 if (prefixes & PREFIX_REPZ)
13680 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
13681 if (prefixes & PREFIX_REPNZ)
13682 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
13683 }
13684
13685 OP_E (bytemode, sizeflag);
13686 }
13687
13688 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
13689 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
13690 */
13691
13692 static void
13693 HLE_Fixup2 (int bytemode, int sizeflag)
13694 {
13695 if (modrm.mod != 3)
13696 {
13697 if (prefixes & PREFIX_REPZ)
13698 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
13699 if (prefixes & PREFIX_REPNZ)
13700 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
13701 }
13702
13703 OP_E (bytemode, sizeflag);
13704 }
13705
13706 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
13707 "xrelease" for memory operand. No check for LOCK prefix. */
13708
13709 static void
13710 HLE_Fixup3 (int bytemode, int sizeflag)
13711 {
13712 if (modrm.mod != 3
13713 && last_repz_prefix > last_repnz_prefix
13714 && (prefixes & PREFIX_REPZ) != 0)
13715 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
13716
13717 OP_E (bytemode, sizeflag);
13718 }
13719
13720 static void
13721 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
13722 {
13723 USED_REX (REX_W);
13724 if (rex & REX_W)
13725 {
13726 /* Change cmpxchg8b to cmpxchg16b. */
13727 char *p = mnemonicendp - 2;
13728 mnemonicendp = stpcpy (p, "16b");
13729 bytemode = o_mode;
13730 }
13731 else if ((prefixes & PREFIX_LOCK) != 0)
13732 {
13733 if (prefixes & PREFIX_REPZ)
13734 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
13735 if (prefixes & PREFIX_REPNZ)
13736 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
13737 }
13738
13739 OP_M (bytemode, sizeflag);
13740 }
13741
13742 static void
13743 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
13744 {
13745 const char **names;
13746
13747 if (need_vex)
13748 {
13749 switch (vex.length)
13750 {
13751 case 128:
13752 names = names_xmm;
13753 break;
13754 case 256:
13755 names = names_ymm;
13756 break;
13757 default:
13758 abort ();
13759 }
13760 }
13761 else
13762 names = names_xmm;
13763 oappend (names[reg]);
13764 }
13765
13766 static void
13767 FXSAVE_Fixup (int bytemode, int sizeflag)
13768 {
13769 /* Add proper suffix to "fxsave" and "fxrstor". */
13770 USED_REX (REX_W);
13771 if (rex & REX_W)
13772 {
13773 char *p = mnemonicendp;
13774 *p++ = '6';
13775 *p++ = '4';
13776 *p = '\0';
13777 mnemonicendp = p;
13778 }
13779 OP_M (bytemode, sizeflag);
13780 }
13781
13782 /* Display the destination register operand for instructions with
13783 VEX. */
13784
13785 static void
13786 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13787 {
13788 int reg;
13789 const char **names;
13790
13791 if (!need_vex)
13792 abort ();
13793
13794 reg = vex.register_specifier;
13795 vex.register_specifier = 0;
13796 if (address_mode != mode_64bit)
13797 reg &= 7;
13798 else if (vex.evex && !vex.v)
13799 reg += 16;
13800
13801 if (bytemode == vex_scalar_mode)
13802 {
13803 oappend (names_xmm[reg]);
13804 return;
13805 }
13806
13807 if (bytemode == tmm_mode)
13808 {
13809 /* All 3 TMM registers must be distinct. */
13810 if (reg >= 8)
13811 oappend ("(bad)");
13812 else
13813 {
13814 /* This must be the 3rd operand. */
13815 if (obufp != op_out[2])
13816 abort ();
13817 oappend (names_tmm[reg]);
13818 if (reg == modrm.reg || reg == modrm.rm)
13819 strcpy (obufp, "/(bad)");
13820 }
13821
13822 if (modrm.reg == modrm.rm || modrm.reg == reg || modrm.rm == reg)
13823 {
13824 if (modrm.reg <= 8
13825 && (modrm.reg == modrm.rm || modrm.reg == reg))
13826 strcat (op_out[0], "/(bad)");
13827 if (modrm.rm <= 8
13828 && (modrm.rm == modrm.reg || modrm.rm == reg))
13829 strcat (op_out[1], "/(bad)");
13830 }
13831
13832 return;
13833 }
13834
13835 switch (vex.length)
13836 {
13837 case 128:
13838 switch (bytemode)
13839 {
13840 case vex_mode:
13841 case vex_vsib_q_w_dq_mode:
13842 case vex_vsib_q_w_d_mode:
13843 names = names_xmm;
13844 break;
13845 case dq_mode:
13846 if (rex & REX_W)
13847 names = names64;
13848 else
13849 names = names32;
13850 break;
13851 case mask_bd_mode:
13852 case mask_mode:
13853 if (reg > 0x7)
13854 {
13855 oappend ("(bad)");
13856 return;
13857 }
13858 names = names_mask;
13859 break;
13860 default:
13861 abort ();
13862 return;
13863 }
13864 break;
13865 case 256:
13866 switch (bytemode)
13867 {
13868 case vex_mode:
13869 names = names_ymm;
13870 break;
13871 case vex_vsib_q_w_dq_mode:
13872 case vex_vsib_q_w_d_mode:
13873 names = vex.w ? names_ymm : names_xmm;
13874 break;
13875 case mask_bd_mode:
13876 case mask_mode:
13877 if (reg > 0x7)
13878 {
13879 oappend ("(bad)");
13880 return;
13881 }
13882 names = names_mask;
13883 break;
13884 default:
13885 /* See PR binutils/20893 for a reproducer. */
13886 oappend ("(bad)");
13887 return;
13888 }
13889 break;
13890 case 512:
13891 names = names_zmm;
13892 break;
13893 default:
13894 abort ();
13895 break;
13896 }
13897 oappend (names[reg]);
13898 }
13899
13900 static void
13901 OP_VexR (int bytemode, int sizeflag)
13902 {
13903 if (modrm.mod == 3)
13904 OP_VEX (bytemode, sizeflag);
13905 }
13906
13907 static void
13908 OP_VexW (int bytemode, int sizeflag)
13909 {
13910 OP_VEX (bytemode, sizeflag);
13911
13912 if (vex.w)
13913 {
13914 /* Swap 2nd and 3rd operands. */
13915 strcpy (scratchbuf, op_out[2]);
13916 strcpy (op_out[2], op_out[1]);
13917 strcpy (op_out[1], scratchbuf);
13918 }
13919 }
13920
13921 static void
13922 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13923 {
13924 int reg;
13925 const char **names = names_xmm;
13926
13927 FETCH_DATA (the_info, codep + 1);
13928 reg = *codep++;
13929
13930 if (bytemode != x_mode && bytemode != scalar_mode)
13931 abort ();
13932
13933 reg >>= 4;
13934 if (address_mode != mode_64bit)
13935 reg &= 7;
13936
13937 if (bytemode == x_mode && vex.length == 256)
13938 names = names_ymm;
13939
13940 oappend (names[reg]);
13941
13942 if (vex.w)
13943 {
13944 /* Swap 3rd and 4th operands. */
13945 strcpy (scratchbuf, op_out[3]);
13946 strcpy (op_out[3], op_out[2]);
13947 strcpy (op_out[2], scratchbuf);
13948 }
13949 }
13950
13951 static void
13952 OP_VexI4 (int bytemode ATTRIBUTE_UNUSED,
13953 int sizeflag ATTRIBUTE_UNUSED)
13954 {
13955 scratchbuf[0] = '$';
13956 print_operand_value (scratchbuf + 1, 1, codep[-1] & 0xf);
13957 oappend_maybe_intel (scratchbuf);
13958 }
13959
13960 static void
13961 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
13962 int sizeflag ATTRIBUTE_UNUSED)
13963 {
13964 unsigned int cmp_type;
13965
13966 if (!vex.evex)
13967 abort ();
13968
13969 FETCH_DATA (the_info, codep + 1);
13970 cmp_type = *codep++ & 0xff;
13971 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
13972 If it's the case, print suffix, otherwise - print the immediate. */
13973 if (cmp_type < ARRAY_SIZE (simd_cmp_op)
13974 && cmp_type != 3
13975 && cmp_type != 7)
13976 {
13977 char suffix [3];
13978 char *p = mnemonicendp - 2;
13979
13980 /* vpcmp* can have both one- and two-lettered suffix. */
13981 if (p[0] == 'p')
13982 {
13983 p++;
13984 suffix[0] = p[0];
13985 suffix[1] = '\0';
13986 }
13987 else
13988 {
13989 suffix[0] = p[0];
13990 suffix[1] = p[1];
13991 suffix[2] = '\0';
13992 }
13993
13994 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13995 mnemonicendp += simd_cmp_op[cmp_type].len;
13996 }
13997 else
13998 {
13999 /* We have a reserved extension byte. Output it directly. */
14000 scratchbuf[0] = '$';
14001 print_operand_value (scratchbuf + 1, 1, cmp_type);
14002 oappend_maybe_intel (scratchbuf);
14003 scratchbuf[0] = '\0';
14004 }
14005 }
14006
14007 static const struct op xop_cmp_op[] =
14008 {
14009 { STRING_COMMA_LEN ("lt") },
14010 { STRING_COMMA_LEN ("le") },
14011 { STRING_COMMA_LEN ("gt") },
14012 { STRING_COMMA_LEN ("ge") },
14013 { STRING_COMMA_LEN ("eq") },
14014 { STRING_COMMA_LEN ("neq") },
14015 { STRING_COMMA_LEN ("false") },
14016 { STRING_COMMA_LEN ("true") }
14017 };
14018
14019 static void
14020 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
14021 int sizeflag ATTRIBUTE_UNUSED)
14022 {
14023 unsigned int cmp_type;
14024
14025 FETCH_DATA (the_info, codep + 1);
14026 cmp_type = *codep++ & 0xff;
14027 if (cmp_type < ARRAY_SIZE (xop_cmp_op))
14028 {
14029 char suffix[3];
14030 char *p = mnemonicendp - 2;
14031
14032 /* vpcom* can have both one- and two-lettered suffix. */
14033 if (p[0] == 'm')
14034 {
14035 p++;
14036 suffix[0] = p[0];
14037 suffix[1] = '\0';
14038 }
14039 else
14040 {
14041 suffix[0] = p[0];
14042 suffix[1] = p[1];
14043 suffix[2] = '\0';
14044 }
14045
14046 sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
14047 mnemonicendp += xop_cmp_op[cmp_type].len;
14048 }
14049 else
14050 {
14051 /* We have a reserved extension byte. Output it directly. */
14052 scratchbuf[0] = '$';
14053 print_operand_value (scratchbuf + 1, 1, cmp_type);
14054 oappend_maybe_intel (scratchbuf);
14055 scratchbuf[0] = '\0';
14056 }
14057 }
14058
14059 static const struct op pclmul_op[] =
14060 {
14061 { STRING_COMMA_LEN ("lql") },
14062 { STRING_COMMA_LEN ("hql") },
14063 { STRING_COMMA_LEN ("lqh") },
14064 { STRING_COMMA_LEN ("hqh") }
14065 };
14066
14067 static void
14068 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
14069 int sizeflag ATTRIBUTE_UNUSED)
14070 {
14071 unsigned int pclmul_type;
14072
14073 FETCH_DATA (the_info, codep + 1);
14074 pclmul_type = *codep++ & 0xff;
14075 switch (pclmul_type)
14076 {
14077 case 0x10:
14078 pclmul_type = 2;
14079 break;
14080 case 0x11:
14081 pclmul_type = 3;
14082 break;
14083 default:
14084 break;
14085 }
14086 if (pclmul_type < ARRAY_SIZE (pclmul_op))
14087 {
14088 char suffix [4];
14089 char *p = mnemonicendp - 3;
14090 suffix[0] = p[0];
14091 suffix[1] = p[1];
14092 suffix[2] = p[2];
14093 suffix[3] = '\0';
14094 sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
14095 mnemonicendp += pclmul_op[pclmul_type].len;
14096 }
14097 else
14098 {
14099 /* We have a reserved extension byte. Output it directly. */
14100 scratchbuf[0] = '$';
14101 print_operand_value (scratchbuf + 1, 1, pclmul_type);
14102 oappend_maybe_intel (scratchbuf);
14103 scratchbuf[0] = '\0';
14104 }
14105 }
14106
14107 static void
14108 MOVSXD_Fixup (int bytemode, int sizeflag)
14109 {
14110 /* Add proper suffix to "movsxd". */
14111 char *p = mnemonicendp;
14112
14113 switch (bytemode)
14114 {
14115 case movsxd_mode:
14116 if (intel_syntax)
14117 {
14118 *p++ = 'x';
14119 *p++ = 'd';
14120 goto skip;
14121 }
14122
14123 USED_REX (REX_W);
14124 if (rex & REX_W)
14125 {
14126 *p++ = 'l';
14127 *p++ = 'q';
14128 }
14129 else
14130 {
14131 *p++ = 'x';
14132 *p++ = 'd';
14133 }
14134 break;
14135 default:
14136 oappend (INTERNAL_DISASSEMBLER_ERROR);
14137 break;
14138 }
14139
14140 skip:
14141 mnemonicendp = p;
14142 *p = '\0';
14143 OP_E (bytemode, sizeflag);
14144 }
14145
14146 static void
14147 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
14148 {
14149 if (!vex.evex
14150 || (bytemode != mask_mode && bytemode != mask_bd_mode))
14151 abort ();
14152
14153 USED_REX (REX_R);
14154 if ((rex & REX_R) != 0 || !vex.r)
14155 {
14156 BadOp ();
14157 return;
14158 }
14159
14160 oappend (names_mask [modrm.reg]);
14161 }
14162
14163 static void
14164 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
14165 {
14166 if (modrm.mod == 3 && vex.b)
14167 switch (bytemode)
14168 {
14169 case evex_rounding_64_mode:
14170 if (address_mode != mode_64bit)
14171 {
14172 oappend ("(bad)");
14173 break;
14174 }
14175 /* Fall through. */
14176 case evex_rounding_mode:
14177 oappend (names_rounding[vex.ll]);
14178 break;
14179 case evex_sae_mode:
14180 oappend ("{sae}");
14181 break;
14182 default:
14183 abort ();
14184 break;
14185 }
14186 }