opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2021 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "disassemble.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40 #include "safe-ctype.h"
  41
  42 #include <setjmp.h>
  43
  44 static int print_insn (bfd_vma, disassemble_info *);
  45 static void dofloat (int);
  46 static void OP_ST (int, int);
  47 static void OP_STi (int, int);
  48 static int putop (const char *, int);
  49 static void oappend (const char *);
  50 static void append_seg (void);
  51 static void OP_indirE (int, int);
  52 static void print_operand_value (char *, int, bfd_vma);
  53 static void OP_E_memory (int, int);
  54 static void print_displacement (char *, bfd_vma);
  55 static void OP_E (int, int);
  56 static void OP_G (int, int);
  57 static bfd_vma get64 (void);
  58 static bfd_signed_vma get32 (void);
  59 static bfd_signed_vma get32s (void);
  60 static int get16 (void);
  61 static void set_op (bfd_vma, int);
  62 static void OP_Skip_MODRM (int, int);
  63 static void OP_REG (int, int);
  64 static void OP_IMREG (int, int);
  65 static void OP_I (int, int);
  66 static void OP_I64 (int, int);
  67 static void OP_sI (int, int);
  68 static void OP_J (int, int);
  69 static void OP_SEG (int, int);
  70 static void OP_DIR (int, int);
  71 static void OP_OFF (int, int);
  72 static void OP_OFF64 (int, int);
  73 static void ptr_reg (int, int);
  74 static void OP_ESreg (int, int);
  75 static void OP_DSreg (int, int);
  76 static void OP_C (int, int);
  77 static void OP_D (int, int);
  78 static void OP_T (int, int);
  79 static void OP_MMX (int, int);
  80 static void OP_XMM (int, int);
  81 static void OP_EM (int, int);
  82 static void OP_EX (int, int);
  83 static void OP_EMC (int,int);
  84 static void OP_MXC (int,int);
  85 static void OP_MS (int, int);
  86 static void OP_XS (int, int);
  87 static void OP_M (int, int);
  88 static void OP_VEX (int, int);
  89 static void OP_VexR (int, int);
  90 static void OP_VexW (int, int);
  91 static void OP_Rounding (int, int);
  92 static void OP_REG_VexI4 (int, int);
  93 static void OP_VexI4 (int, int);
  94 static void PCLMUL_Fixup (int, int);
  95 static void VPCMP_Fixup (int, int);
  96 static void VPCOM_Fixup (int, int);
  97 static void OP_0f07 (int, int);
  98 static void OP_Monitor (int, int);
  99 static void OP_Mwait (int, int);
 100 static void NOP_Fixup1 (int, int);
 101 static void NOP_Fixup2 (int, int);
 102 static void OP_3DNowSuffix (int, int);
 103 static void CMP_Fixup (int, int);
 104 static void BadOp (void);
 105 static void REP_Fixup (int, int);
 106 static void SEP_Fixup (int, int);
 107 static void BND_Fixup (int, int);
 108 static void NOTRACK_Fixup (int, int);
 109 static void HLE_Fixup1 (int, int);
 110 static void HLE_Fixup2 (int, int);
 111 static void HLE_Fixup3 (int, int);
 112 static void CMPXCHG8B_Fixup (int, int);
 113 static void XMM_Fixup (int, int);
 114 static void FXSAVE_Fixup (int, int);
 115
 116 static void MOVSXD_Fixup (int, int);
 117 static void DistinctDest_Fixup (int, int);
 118
 119 struct dis_private {
 120   /* Points to first byte not fetched.  */
 121   bfd_byte *max_fetched;
 122   bfd_byte the_buffer[MAX_MNEM_SIZE];
 123   bfd_vma insn_start;
 124   int orig_sizeflag;
 125   OPCODES_SIGJMP_BUF bailout;
 126 };
 127
 128 enum address_mode
 129 {
 130   mode_16bit,
 131   mode_32bit,
 132   mode_64bit
 133 };
 134
 135 enum address_mode address_mode;
 136
 137 /* Flags for the prefixes for the current instruction.  See below.  */
 138 static int prefixes;
 139
 140 /* REX prefix the current instruction.  See below.  */
 141 static int rex;
 142 /* Bits of REX we've already used.  */
 143 static int rex_used;
 144 /* Mark parts used in the REX prefix.  When we are testing for
 145    empty prefix (for 8bit register REX extension), just mask it
 146    out.  Otherwise test for REX bit is excuse for existence of REX
 147    only in case value is nonzero.  */
 148 #define USED_REX(value)                                 \
 149   {                                                     \
 150     if (value)                                          \
 151       {                                                 \
 152         if ((rex & value))                              \
 153           rex_used |= (value) | REX_OPCODE;             \
 154       }                                                 \
 155     else                                                \
 156       rex_used |= REX_OPCODE;                           \
 157   }
 158
 159 /* Flags for prefixes which we somehow handled when printing the
 160    current instruction.  */
 161 static int used_prefixes;
 162
 163 /* Flags for EVEX bits which we somehow handled when printing the
 164    current instruction.  */
 165 #define EVEX_b_used 1
 166 static int evex_used;
 167
 168 /* Flags stored in PREFIXES.  */
 169 #define PREFIX_REPZ 1
 170 #define PREFIX_REPNZ 2
 171 #define PREFIX_LOCK 4
 172 #define PREFIX_CS 8
 173 #define PREFIX_SS 0x10
 174 #define PREFIX_DS 0x20
 175 #define PREFIX_ES 0x40
 176 #define PREFIX_FS 0x80
 177 #define PREFIX_GS 0x100
 178 #define PREFIX_DATA 0x200
 179 #define PREFIX_ADDR 0x400
 180 #define PREFIX_FWAIT 0x800
 181
 182 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 183    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 184    on error.  */
 185 #define FETCH_DATA(info, addr) \
 186   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 187    ? 1 : fetch_data ((info), (addr)))
 188
 189 static int
 190 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 191 {
 192   int status;
 193   struct dis_private *priv = (struct dis_private *) info->private_data;
 194   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 195
 196   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 197     status = (*info->read_memory_func) (start,
 198                                         priv->max_fetched,
 199                                         addr - priv->max_fetched,
 200                                         info);
 201   else
 202     status = -1;
 203   if (status != 0)
 204     {
 205       /* If we did manage to read at least one byte, then
 206          print_insn_i386 will do something sensible.  Otherwise, print
 207          an error.  We do that here because this is where we know
 208          STATUS.  */
 209       if (priv->max_fetched == priv->the_buffer)
 210         (*info->memory_error_func) (status, start, info);
 211       OPCODES_SIGLONGJMP (priv->bailout, 1);
 212     }
 213   else
 214     priv->max_fetched = addr;
 215   return 1;
 216 }
 217
 218 /* Possible values for prefix requirement.  */
 219 #define PREFIX_IGNORED_SHIFT    16
 220 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 221 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 222 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 223 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 224 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 225
 226 /* Opcode prefixes.  */
 227 #define PREFIX_OPCODE           (PREFIX_REPZ \
 228                                  | PREFIX_REPNZ \
 229                                  | PREFIX_DATA)
 230
 231 /* Prefixes ignored.  */
 232 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 233                                  | PREFIX_IGNORED_REPNZ \
 234                                  | PREFIX_IGNORED_DATA)
 235
 236 #define XX { NULL, 0 }
 237 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 238
 239 #define Eb { OP_E, b_mode }
 240 #define Ebnd { OP_E, bnd_mode }
 241 #define EbS { OP_E, b_swap_mode }
 242 #define EbndS { OP_E, bnd_swap_mode }
 243 #define Ev { OP_E, v_mode }
 244 #define Eva { OP_E, va_mode }
 245 #define Ev_bnd { OP_E, v_bnd_mode }
 246 #define EvS { OP_E, v_swap_mode }
 247 #define Ed { OP_E, d_mode }
 248 #define Edq { OP_E, dq_mode }
 249 #define Edb { OP_E, db_mode }
 250 #define Edw { OP_E, dw_mode }
 251 #define Eq { OP_E, q_mode }
 252 #define indirEv { OP_indirE, indir_v_mode }
 253 #define indirEp { OP_indirE, f_mode }
 254 #define stackEv { OP_E, stack_v_mode }
 255 #define Em { OP_E, m_mode }
 256 #define Ew { OP_E, w_mode }
 257 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 258 #define Ma { OP_M, a_mode }
 259 #define Mb { OP_M, b_mode }
 260 #define Md { OP_M, d_mode }
 261 #define Mo { OP_M, o_mode }
 262 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 263 #define Mq { OP_M, q_mode }
 264 #define Mv { OP_M, v_mode }
 265 #define Mv_bnd { OP_M, v_bndmk_mode }
 266 #define Mx { OP_M, x_mode }
 267 #define Mxmm { OP_M, xmm_mode }
 268 #define Gb { OP_G, b_mode }
 269 #define Gbnd { OP_G, bnd_mode }
 270 #define Gv { OP_G, v_mode }
 271 #define Gd { OP_G, d_mode }
 272 #define Gdq { OP_G, dq_mode }
 273 #define Gm { OP_G, m_mode }
 274 #define Gva { OP_G, va_mode }
 275 #define Gw { OP_G, w_mode }
 276 #define Ib { OP_I, b_mode }
 277 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 278 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 279 #define Iv { OP_I, v_mode }
 280 #define sIv { OP_sI, v_mode }
 281 #define Iv64 { OP_I64, v_mode }
 282 #define Id { OP_I, d_mode }
 283 #define Iw { OP_I, w_mode }
 284 #define I1 { OP_I, const_1_mode }
 285 #define Jb { OP_J, b_mode }
 286 #define Jv { OP_J, v_mode }
 287 #define Jdqw { OP_J, dqw_mode }
 288 #define Cm { OP_C, m_mode }
 289 #define Dm { OP_D, m_mode }
 290 #define Td { OP_T, d_mode }
 291 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 292
 293 #define RMeAX { OP_REG, eAX_reg }
 294 #define RMeBX { OP_REG, eBX_reg }
 295 #define RMeCX { OP_REG, eCX_reg }
 296 #define RMeDX { OP_REG, eDX_reg }
 297 #define RMeSP { OP_REG, eSP_reg }
 298 #define RMeBP { OP_REG, eBP_reg }
 299 #define RMeSI { OP_REG, eSI_reg }
 300 #define RMeDI { OP_REG, eDI_reg }
 301 #define RMrAX { OP_REG, rAX_reg }
 302 #define RMrBX { OP_REG, rBX_reg }
 303 #define RMrCX { OP_REG, rCX_reg }
 304 #define RMrDX { OP_REG, rDX_reg }
 305 #define RMrSP { OP_REG, rSP_reg }
 306 #define RMrBP { OP_REG, rBP_reg }
 307 #define RMrSI { OP_REG, rSI_reg }
 308 #define RMrDI { OP_REG, rDI_reg }
 309 #define RMAL { OP_REG, al_reg }
 310 #define RMCL { OP_REG, cl_reg }
 311 #define RMDL { OP_REG, dl_reg }
 312 #define RMBL { OP_REG, bl_reg }
 313 #define RMAH { OP_REG, ah_reg }
 314 #define RMCH { OP_REG, ch_reg }
 315 #define RMDH { OP_REG, dh_reg }
 316 #define RMBH { OP_REG, bh_reg }
 317 #define RMAX { OP_REG, ax_reg }
 318 #define RMDX { OP_REG, dx_reg }
 319
 320 #define eAX { OP_IMREG, eAX_reg }
 321 #define AL { OP_IMREG, al_reg }
 322 #define CL { OP_IMREG, cl_reg }
 323 #define zAX { OP_IMREG, z_mode_ax_reg }
 324 #define indirDX { OP_IMREG, indir_dx_reg }
 325
 326 #define Sw { OP_SEG, w_mode }
 327 #define Sv { OP_SEG, v_mode }
 328 #define Ap { OP_DIR, 0 }
 329 #define Ob { OP_OFF64, b_mode }
 330 #define Ov { OP_OFF64, v_mode }
 331 #define Xb { OP_DSreg, eSI_reg }
 332 #define Xv { OP_DSreg, eSI_reg }
 333 #define Xz { OP_DSreg, eSI_reg }
 334 #define Yb { OP_ESreg, eDI_reg }
 335 #define Yv { OP_ESreg, eDI_reg }
 336 #define DSBX { OP_DSreg, eBX_reg }
 337
 338 #define es { OP_REG, es_reg }
 339 #define ss { OP_REG, ss_reg }
 340 #define cs { OP_REG, cs_reg }
 341 #define ds { OP_REG, ds_reg }
 342 #define fs { OP_REG, fs_reg }
 343 #define gs { OP_REG, gs_reg }
 344
 345 #define MX { OP_MMX, 0 }
 346 #define XM { OP_XMM, 0 }
 347 #define XMScalar { OP_XMM, scalar_mode }
 348 #define XMGatherD { OP_XMM, vex_vsib_d_w_dq_mode }
 349 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 350 #define XMM { OP_XMM, xmm_mode }
 351 #define TMM { OP_XMM, tmm_mode }
 352 #define XMxmmq { OP_XMM, xmmq_mode }
 353 #define EM { OP_EM, v_mode }
 354 #define EMS { OP_EM, v_swap_mode }
 355 #define EMd { OP_EM, d_mode }
 356 #define EMx { OP_EM, x_mode }
 357 #define EXbwUnit { OP_EX, bw_unit_mode }
 358 #define EXb { OP_EX, b_mode }
 359 #define EXw { OP_EX, w_mode }
 360 #define EXd { OP_EX, d_mode }
 361 #define EXdS { OP_EX, d_swap_mode }
 362 #define EXwS { OP_EX, w_swap_mode }
 363 #define EXq { OP_EX, q_mode }
 364 #define EXqS { OP_EX, q_swap_mode }
 365 #define EXdq { OP_EX, dq_mode }
 366 #define EXx { OP_EX, x_mode }
 367 #define EXxh { OP_EX, xh_mode }
 368 #define EXxS { OP_EX, x_swap_mode }
 369 #define EXxmm { OP_EX, xmm_mode }
 370 #define EXymm { OP_EX, ymm_mode }
 371 #define EXtmm { OP_EX, tmm_mode }
 372 #define EXxmmq { OP_EX, xmmq_mode }
 373 #define EXxmmqh { OP_EX, evex_half_bcst_xmmqh_mode }
 374 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 375 #define EXxmmdw { OP_EX, xmmdw_mode }
 376 #define EXxmmqd { OP_EX, xmmqd_mode }
 377 #define EXxmmqdh { OP_EX, evex_half_bcst_xmmqdh_mode }
 378 #define EXymmq { OP_EX, ymmq_mode }
 379 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 380 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 381 #define MS { OP_MS, v_mode }
 382 #define XS { OP_XS, v_mode }
 383 #define EMCq { OP_EMC, q_mode }
 384 #define MXC { OP_MXC, 0 }
 385 #define OPSUF { OP_3DNowSuffix, 0 }
 386 #define SEP { SEP_Fixup, 0 }
 387 #define CMP { CMP_Fixup, 0 }
 388 #define XMM0 { XMM_Fixup, 0 }
 389 #define FXSAVE { FXSAVE_Fixup, 0 }
 390
 391 #define Vex { OP_VEX, x_mode }
 392 #define VexW { OP_VexW, x_mode }
 393 #define VexScalar { OP_VEX, scalar_mode }
 394 #define VexScalarR { OP_VexR, scalar_mode }
 395 #define VexGatherD { OP_VEX, vex_vsib_d_w_dq_mode }
 396 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 397 #define VexGdq { OP_VEX, dq_mode }
 398 #define VexTmm { OP_VEX, tmm_mode }
 399 #define XMVexI4 { OP_REG_VexI4, x_mode }
 400 #define XMVexScalarI4 { OP_REG_VexI4, scalar_mode }
 401 #define VexI4 { OP_VexI4, 0 }
 402 #define PCLMUL { PCLMUL_Fixup, 0 }
 403 #define VPCMP { VPCMP_Fixup, 0 }
 404 #define VPCOM { VPCOM_Fixup, 0 }
 405
 406 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 407 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
 408 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 409
 410 #define MaskG { OP_G, mask_mode }
 411 #define MaskE { OP_E, mask_mode }
 412 #define MaskBDE { OP_E, mask_bd_mode }
 413 #define MaskVex { OP_VEX, mask_mode }
 414
 415 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 416 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 417
 418 #define MVexSIBMEM { OP_M, vex_sibmem_mode }
 419
 420 /* Used handle "rep" prefix for string instructions.  */
 421 #define Xbr { REP_Fixup, eSI_reg }
 422 #define Xvr { REP_Fixup, eSI_reg }
 423 #define Ybr { REP_Fixup, eDI_reg }
 424 #define Yvr { REP_Fixup, eDI_reg }
 425 #define Yzr { REP_Fixup, eDI_reg }
 426 #define indirDXr { REP_Fixup, indir_dx_reg }
 427 #define ALr { REP_Fixup, al_reg }
 428 #define eAXr { REP_Fixup, eAX_reg }
 429
 430 /* Used handle HLE prefix for lockable instructions.  */
 431 #define Ebh1 { HLE_Fixup1, b_mode }
 432 #define Evh1 { HLE_Fixup1, v_mode }
 433 #define Ebh2 { HLE_Fixup2, b_mode }
 434 #define Evh2 { HLE_Fixup2, v_mode }
 435 #define Ebh3 { HLE_Fixup3, b_mode }
 436 #define Evh3 { HLE_Fixup3, v_mode }
 437
 438 #define BND { BND_Fixup, 0 }
 439 #define NOTRACK { NOTRACK_Fixup, 0 }
 440
 441 #define cond_jump_flag { NULL, cond_jump_mode }
 442 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 443
 444 /* bits in sizeflag */
 445 #define SUFFIX_ALWAYS 4
 446 #define AFLAG 2
 447 #define DFLAG 1
 448
 449 enum
 450 {
 451   /* byte operand */
 452   b_mode = 1,
 453   /* byte operand with operand swapped */
 454   b_swap_mode,
 455   /* byte operand, sign extend like 'T' suffix */
 456   b_T_mode,
 457   /* operand size depends on prefixes */
 458   v_mode,
 459   /* operand size depends on prefixes with operand swapped */
 460   v_swap_mode,
 461   /* operand size depends on address prefix */
 462   va_mode,
 463   /* word operand */
 464   w_mode,
 465   /* double word operand  */
 466   d_mode,
 467   /* word operand with operand swapped  */
 468   w_swap_mode,
 469   /* double word operand with operand swapped */
 470   d_swap_mode,
 471   /* quad word operand */
 472   q_mode,
 473   /* quad word operand with operand swapped */
 474   q_swap_mode,
 475   /* ten-byte operand */
 476   t_mode,
 477   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 478      broadcast enabled.  */
 479   x_mode,
 480   /* Similar to x_mode, but with different EVEX mem shifts.  */
 481   evex_x_gscat_mode,
 482   /* Similar to x_mode, but with yet different EVEX mem shifts.  */
 483   bw_unit_mode,
 484   /* Similar to x_mode, but with disabled broadcast.  */
 485   evex_x_nobcst_mode,
 486   /* Similar to x_mode, but with operands swapped and disabled broadcast
 487      in EVEX.  */
 488   x_swap_mode,
 489   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 490      broadcast of 16bit enabled.  */
 491   xh_mode,
 492   /* 16-byte XMM operand */
 493   xmm_mode,
 494   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 495      memory operand (depending on vector length).  Broadcast isn't
 496      allowed.  */
 497   xmmq_mode,
 498   /* Same as xmmq_mode, but broadcast is allowed.  */
 499   evex_half_bcst_xmmq_mode,
 500   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 501      memory operand (depending on vector length).  16bit broadcast.  */
 502   evex_half_bcst_xmmqh_mode,
 503   /* 16-byte XMM, word, double word or quad word operand.  */
 504   xmmdw_mode,
 505   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 506   xmmqd_mode,
 507   /* 16-byte XMM, double word, quad word operand or xmm word operand.
 508      16bit broadcast.  */
 509   evex_half_bcst_xmmqdh_mode,
 510   /* 32-byte YMM operand */
 511   ymm_mode,
 512   /* quad word, ymmword or zmmword memory operand.  */
 513   ymmq_mode,
 514   /* 32-byte YMM or 16-byte word operand */
 515   ymmxmm_mode,
 516   /* TMM operand */
 517   tmm_mode,
 518   /* d_mode in 32bit, q_mode in 64bit mode.  */
 519   m_mode,
 520   /* pair of v_mode operands */
 521   a_mode,
 522   cond_jump_mode,
 523   loop_jcxz_mode,
 524   movsxd_mode,
 525   v_bnd_mode,
 526   /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode.  */
 527   v_bndmk_mode,
 528   /* operand size depends on REX.W / VEX.W.  */
 529   dq_mode,
 530   /* Displacements like v_mode without considering Intel64 ISA.  */
 531   dqw_mode,
 532   /* bounds operand */
 533   bnd_mode,
 534   /* bounds operand with operand swapped */
 535   bnd_swap_mode,
 536   /* 4- or 6-byte pointer operand */
 537   f_mode,
 538   const_1_mode,
 539   /* v_mode for indirect branch opcodes.  */
 540   indir_v_mode,
 541   /* v_mode for stack-related opcodes.  */
 542   stack_v_mode,
 543   /* non-quad operand size depends on prefixes */
 544   z_mode,
 545   /* 16-byte operand */
 546   o_mode,
 547   /* registers like d_mode, memory like b_mode.  */
 548   db_mode,
 549   /* registers like d_mode, memory like w_mode.  */
 550   dw_mode,
 551
 552   /* Operand size depends on the VEX.W bit, with VSIB dword indices.  */
 553   vex_vsib_d_w_dq_mode,
 554   /* Operand size depends on the VEX.W bit, with VSIB qword indices.  */
 555   vex_vsib_q_w_dq_mode,
 556   /* mandatory non-vector SIB.  */
 557   vex_sibmem_mode,
 558
 559   /* scalar, ignore vector length.  */
 560   scalar_mode,
 561
 562   /* Static rounding.  */
 563   evex_rounding_mode,
 564   /* Static rounding, 64-bit mode only.  */
 565   evex_rounding_64_mode,
 566   /* Supress all exceptions.  */
 567   evex_sae_mode,
 568
 569   /* Mask register operand.  */
 570   mask_mode,
 571   /* Mask register operand.  */
 572   mask_bd_mode,
 573
 574   es_reg,
 575   cs_reg,
 576   ss_reg,
 577   ds_reg,
 578   fs_reg,
 579   gs_reg,
 580
 581   eAX_reg,
 582   eCX_reg,
 583   eDX_reg,
 584   eBX_reg,
 585   eSP_reg,
 586   eBP_reg,
 587   eSI_reg,
 588   eDI_reg,
 589
 590   al_reg,
 591   cl_reg,
 592   dl_reg,
 593   bl_reg,
 594   ah_reg,
 595   ch_reg,
 596   dh_reg,
 597   bh_reg,
 598
 599   ax_reg,
 600   cx_reg,
 601   dx_reg,
 602   bx_reg,
 603   sp_reg,
 604   bp_reg,
 605   si_reg,
 606   di_reg,
 607
 608   rAX_reg,
 609   rCX_reg,
 610   rDX_reg,
 611   rBX_reg,
 612   rSP_reg,
 613   rBP_reg,
 614   rSI_reg,
 615   rDI_reg,
 616
 617   z_mode_ax_reg,
 618   indir_dx_reg
 619 };
 620
 621 enum
 622 {
 623   FLOATCODE = 1,
 624   USE_REG_TABLE,
 625   USE_MOD_TABLE,
 626   USE_RM_TABLE,
 627   USE_PREFIX_TABLE,
 628   USE_X86_64_TABLE,
 629   USE_3BYTE_TABLE,
 630   USE_XOP_8F_TABLE,
 631   USE_VEX_C4_TABLE,
 632   USE_VEX_C5_TABLE,
 633   USE_VEX_LEN_TABLE,
 634   USE_VEX_W_TABLE,
 635   USE_EVEX_TABLE,
 636   USE_EVEX_LEN_TABLE
 637 };
 638
 639 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 640
 641 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 642 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 643 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 644 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 645 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 646 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 647 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 648 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 649 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 650 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 651 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 652 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 653 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 654 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 655 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 656 #define EVEX_LEN_TABLE(I)       DIS386 (USE_EVEX_LEN_TABLE, (I))
 657
 658 enum
 659 {
 660   REG_80 = 0,
 661   REG_81,
 662   REG_83,
 663   REG_8F,
 664   REG_C0,
 665   REG_C1,
 666   REG_C6,
 667   REG_C7,
 668   REG_D0,
 669   REG_D1,
 670   REG_D2,
 671   REG_D3,
 672   REG_F6,
 673   REG_F7,
 674   REG_FE,
 675   REG_FF,
 676   REG_0F00,
 677   REG_0F01,
 678   REG_0F0D,
 679   REG_0F18,
 680   REG_0F1C_P_0_MOD_0,
 681   REG_0F1E_P_1_MOD_3,
 682   REG_0F38D8_PREFIX_1,
 683   REG_0F3A0F_PREFIX_1_MOD_3,
 684   REG_0F71_MOD_0,
 685   REG_0F72_MOD_0,
 686   REG_0F73_MOD_0,
 687   REG_0FA6,
 688   REG_0FA7,
 689   REG_0FAE,
 690   REG_0FBA,
 691   REG_0FC7,
 692   REG_VEX_0F71_M_0,
 693   REG_VEX_0F72_M_0,
 694   REG_VEX_0F73_M_0,
 695   REG_VEX_0FAE,
 696   REG_VEX_0F3849_X86_64_P_0_W_0_M_1,
 697   REG_VEX_0F38F3_L_0,
 698
 699   REG_XOP_09_01_L_0,
 700   REG_XOP_09_02_L_0,
 701   REG_XOP_09_12_M_1_L_0,
 702   REG_XOP_0A_12_L_0,
 703
 704   REG_EVEX_0F71,
 705   REG_EVEX_0F72,
 706   REG_EVEX_0F73,
 707   REG_EVEX_0F38C6_M_0_L_2,
 708   REG_EVEX_0F38C7_M_0_L_2
 709 };
 710
 711 enum
 712 {
 713   MOD_62_32BIT = 0,
 714   MOD_8D,
 715   MOD_C4_32BIT,
 716   MOD_C5_32BIT,
 717   MOD_C6_REG_7,
 718   MOD_C7_REG_7,
 719   MOD_FF_REG_3,
 720   MOD_FF_REG_5,
 721   MOD_0F01_REG_0,
 722   MOD_0F01_REG_1,
 723   MOD_0F01_REG_2,
 724   MOD_0F01_REG_3,
 725   MOD_0F01_REG_5,
 726   MOD_0F01_REG_7,
 727   MOD_0F12_PREFIX_0,
 728   MOD_0F12_PREFIX_2,
 729   MOD_0F13,
 730   MOD_0F16_PREFIX_0,
 731   MOD_0F16_PREFIX_2,
 732   MOD_0F17,
 733   MOD_0F18_REG_0,
 734   MOD_0F18_REG_1,
 735   MOD_0F18_REG_2,
 736   MOD_0F18_REG_3,
 737   MOD_0F1A_PREFIX_0,
 738   MOD_0F1B_PREFIX_0,
 739   MOD_0F1B_PREFIX_1,
 740   MOD_0F1C_PREFIX_0,
 741   MOD_0F1E_PREFIX_1,
 742   MOD_0F2B_PREFIX_0,
 743   MOD_0F2B_PREFIX_1,
 744   MOD_0F2B_PREFIX_2,
 745   MOD_0F2B_PREFIX_3,
 746   MOD_0F50,
 747   MOD_0F71,
 748   MOD_0F72,
 749   MOD_0F73,
 750   MOD_0FAE_REG_0,
 751   MOD_0FAE_REG_1,
 752   MOD_0FAE_REG_2,
 753   MOD_0FAE_REG_3,
 754   MOD_0FAE_REG_4,
 755   MOD_0FAE_REG_5,
 756   MOD_0FAE_REG_6,
 757   MOD_0FAE_REG_7,
 758   MOD_0FB2,
 759   MOD_0FB4,
 760   MOD_0FB5,
 761   MOD_0FC3,
 762   MOD_0FC7_REG_3,
 763   MOD_0FC7_REG_4,
 764   MOD_0FC7_REG_5,
 765   MOD_0FC7_REG_6,
 766   MOD_0FC7_REG_7,
 767   MOD_0FD7,
 768   MOD_0FE7_PREFIX_2,
 769   MOD_0FF0_PREFIX_3,
 770   MOD_0F382A,
 771   MOD_0F38DC_PREFIX_1,
 772   MOD_0F38DD_PREFIX_1,
 773   MOD_0F38DE_PREFIX_1,
 774   MOD_0F38DF_PREFIX_1,
 775   MOD_0F38F5,
 776   MOD_0F38F6_PREFIX_0,
 777   MOD_0F38F8_PREFIX_1,
 778   MOD_0F38F8_PREFIX_2,
 779   MOD_0F38F8_PREFIX_3,
 780   MOD_0F38F9,
 781   MOD_0F38FA_PREFIX_1,
 782   MOD_0F38FB_PREFIX_1,
 783   MOD_0F3A0F_PREFIX_1,
 784
 785   MOD_VEX_0F12_PREFIX_0,
 786   MOD_VEX_0F12_PREFIX_2,
 787   MOD_VEX_0F13,
 788   MOD_VEX_0F16_PREFIX_0,
 789   MOD_VEX_0F16_PREFIX_2,
 790   MOD_VEX_0F17,
 791   MOD_VEX_0F2B,
 792   MOD_VEX_0F41_L_1,
 793   MOD_VEX_0F42_L_1,
 794   MOD_VEX_0F44_L_0,
 795   MOD_VEX_0F45_L_1,
 796   MOD_VEX_0F46_L_1,
 797   MOD_VEX_0F47_L_1,
 798   MOD_VEX_0F4A_L_1,
 799   MOD_VEX_0F4B_L_1,
 800   MOD_VEX_0F50,
 801   MOD_VEX_0F71,
 802   MOD_VEX_0F72,
 803   MOD_VEX_0F73,
 804   MOD_VEX_0F91_L_0,
 805   MOD_VEX_0F92_L_0,
 806   MOD_VEX_0F93_L_0,
 807   MOD_VEX_0F98_L_0,
 808   MOD_VEX_0F99_L_0,
 809   MOD_VEX_0FAE_REG_2,
 810   MOD_VEX_0FAE_REG_3,
 811   MOD_VEX_0FD7,
 812   MOD_VEX_0FE7,
 813   MOD_VEX_0FF0_PREFIX_3,
 814   MOD_VEX_0F381A,
 815   MOD_VEX_0F382A,
 816   MOD_VEX_0F382C,
 817   MOD_VEX_0F382D,
 818   MOD_VEX_0F382E,
 819   MOD_VEX_0F382F,
 820   MOD_VEX_0F3849_X86_64_P_0_W_0,
 821   MOD_VEX_0F3849_X86_64_P_2_W_0,
 822   MOD_VEX_0F3849_X86_64_P_3_W_0,
 823   MOD_VEX_0F384B_X86_64_P_1_W_0,
 824   MOD_VEX_0F384B_X86_64_P_2_W_0,
 825   MOD_VEX_0F384B_X86_64_P_3_W_0,
 826   MOD_VEX_0F385A,
 827   MOD_VEX_0F385C_X86_64_P_1_W_0,
 828   MOD_VEX_0F385E_X86_64_P_0_W_0,
 829   MOD_VEX_0F385E_X86_64_P_1_W_0,
 830   MOD_VEX_0F385E_X86_64_P_2_W_0,
 831   MOD_VEX_0F385E_X86_64_P_3_W_0,
 832   MOD_VEX_0F388C,
 833   MOD_VEX_0F388E,
 834   MOD_VEX_0F3A30_L_0,
 835   MOD_VEX_0F3A31_L_0,
 836   MOD_VEX_0F3A32_L_0,
 837   MOD_VEX_0F3A33_L_0,
 838
 839   MOD_XOP_09_12,
 840
 841   MOD_EVEX_0F12_PREFIX_0,
 842   MOD_EVEX_0F12_PREFIX_2,
 843   MOD_EVEX_0F13,
 844   MOD_EVEX_0F16_PREFIX_0,
 845   MOD_EVEX_0F16_PREFIX_2,
 846   MOD_EVEX_0F17,
 847   MOD_EVEX_0F2B,
 848   MOD_EVEX_0F381A,
 849   MOD_EVEX_0F381B,
 850   MOD_EVEX_0F3828_P_1,
 851   MOD_EVEX_0F382A_P_1_W_1,
 852   MOD_EVEX_0F3838_P_1,
 853   MOD_EVEX_0F383A_P_1_W_0,
 854   MOD_EVEX_0F385A,
 855   MOD_EVEX_0F385B,
 856   MOD_EVEX_0F387A_W_0,
 857   MOD_EVEX_0F387B_W_0,
 858   MOD_EVEX_0F387C,
 859   MOD_EVEX_0F38C6,
 860   MOD_EVEX_0F38C7,
 861 };
 862
 863 enum
 864 {
 865   RM_C6_REG_7 = 0,
 866   RM_C7_REG_7,
 867   RM_0F01_REG_0,
 868   RM_0F01_REG_1,
 869   RM_0F01_REG_2,
 870   RM_0F01_REG_3,
 871   RM_0F01_REG_5_MOD_3,
 872   RM_0F01_REG_7_MOD_3,
 873   RM_0F1E_P_1_MOD_3_REG_7,
 874   RM_0FAE_REG_6_MOD_3_P_0,
 875   RM_0FAE_REG_7_MOD_3,
 876   RM_0F3A0F_P_1_MOD_3_REG_0,
 877
 878   RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0
 879 };
 880
 881 enum
 882 {
 883   PREFIX_90 = 0,
 884   PREFIX_0F01_REG_1_RM_4,
 885   PREFIX_0F01_REG_1_RM_5,
 886   PREFIX_0F01_REG_1_RM_6,
 887   PREFIX_0F01_REG_1_RM_7,
 888   PREFIX_0F01_REG_3_RM_1,
 889   PREFIX_0F01_REG_5_MOD_0,
 890   PREFIX_0F01_REG_5_MOD_3_RM_0,
 891   PREFIX_0F01_REG_5_MOD_3_RM_1,
 892   PREFIX_0F01_REG_5_MOD_3_RM_2,
 893   PREFIX_0F01_REG_5_MOD_3_RM_4,
 894   PREFIX_0F01_REG_5_MOD_3_RM_5,
 895   PREFIX_0F01_REG_5_MOD_3_RM_6,
 896   PREFIX_0F01_REG_5_MOD_3_RM_7,
 897   PREFIX_0F01_REG_7_MOD_3_RM_2,
 898   PREFIX_0F01_REG_7_MOD_3_RM_6,
 899   PREFIX_0F01_REG_7_MOD_3_RM_7,
 900   PREFIX_0F09,
 901   PREFIX_0F10,
 902   PREFIX_0F11,
 903   PREFIX_0F12,
 904   PREFIX_0F16,
 905   PREFIX_0F1A,
 906   PREFIX_0F1B,
 907   PREFIX_0F1C,
 908   PREFIX_0F1E,
 909   PREFIX_0F2A,
 910   PREFIX_0F2B,
 911   PREFIX_0F2C,
 912   PREFIX_0F2D,
 913   PREFIX_0F2E,
 914   PREFIX_0F2F,
 915   PREFIX_0F51,
 916   PREFIX_0F52,
 917   PREFIX_0F53,
 918   PREFIX_0F58,
 919   PREFIX_0F59,
 920   PREFIX_0F5A,
 921   PREFIX_0F5B,
 922   PREFIX_0F5C,
 923   PREFIX_0F5D,
 924   PREFIX_0F5E,
 925   PREFIX_0F5F,
 926   PREFIX_0F60,
 927   PREFIX_0F61,
 928   PREFIX_0F62,
 929   PREFIX_0F6F,
 930   PREFIX_0F70,
 931   PREFIX_0F78,
 932   PREFIX_0F79,
 933   PREFIX_0F7C,
 934   PREFIX_0F7D,
 935   PREFIX_0F7E,
 936   PREFIX_0F7F,
 937   PREFIX_0FAE_REG_0_MOD_3,
 938   PREFIX_0FAE_REG_1_MOD_3,
 939   PREFIX_0FAE_REG_2_MOD_3,
 940   PREFIX_0FAE_REG_3_MOD_3,
 941   PREFIX_0FAE_REG_4_MOD_0,
 942   PREFIX_0FAE_REG_4_MOD_3,
 943   PREFIX_0FAE_REG_5_MOD_3,
 944   PREFIX_0FAE_REG_6_MOD_0,
 945   PREFIX_0FAE_REG_6_MOD_3,
 946   PREFIX_0FAE_REG_7_MOD_0,
 947   PREFIX_0FB8,
 948   PREFIX_0FBC,
 949   PREFIX_0FBD,
 950   PREFIX_0FC2,
 951   PREFIX_0FC7_REG_6_MOD_0,
 952   PREFIX_0FC7_REG_6_MOD_3,
 953   PREFIX_0FC7_REG_7_MOD_3,
 954   PREFIX_0FD0,
 955   PREFIX_0FD6,
 956   PREFIX_0FE6,
 957   PREFIX_0FE7,
 958   PREFIX_0FF0,
 959   PREFIX_0FF7,
 960   PREFIX_0F38D8,
 961   PREFIX_0F38DC,
 962   PREFIX_0F38DD,
 963   PREFIX_0F38DE,
 964   PREFIX_0F38DF,
 965   PREFIX_0F38F0,
 966   PREFIX_0F38F1,
 967   PREFIX_0F38F6,
 968   PREFIX_0F38F8,
 969   PREFIX_0F38FA,
 970   PREFIX_0F38FB,
 971   PREFIX_0F3A0F,
 972   PREFIX_VEX_0F10,
 973   PREFIX_VEX_0F11,
 974   PREFIX_VEX_0F12,
 975   PREFIX_VEX_0F16,
 976   PREFIX_VEX_0F2A,
 977   PREFIX_VEX_0F2C,
 978   PREFIX_VEX_0F2D,
 979   PREFIX_VEX_0F2E,
 980   PREFIX_VEX_0F2F,
 981   PREFIX_VEX_0F41_L_1_M_1_W_0,
 982   PREFIX_VEX_0F41_L_1_M_1_W_1,
 983   PREFIX_VEX_0F42_L_1_M_1_W_0,
 984   PREFIX_VEX_0F42_L_1_M_1_W_1,
 985   PREFIX_VEX_0F44_L_0_M_1_W_0,
 986   PREFIX_VEX_0F44_L_0_M_1_W_1,
 987   PREFIX_VEX_0F45_L_1_M_1_W_0,
 988   PREFIX_VEX_0F45_L_1_M_1_W_1,
 989   PREFIX_VEX_0F46_L_1_M_1_W_0,
 990   PREFIX_VEX_0F46_L_1_M_1_W_1,
 991   PREFIX_VEX_0F47_L_1_M_1_W_0,
 992   PREFIX_VEX_0F47_L_1_M_1_W_1,
 993   PREFIX_VEX_0F4A_L_1_M_1_W_0,
 994   PREFIX_VEX_0F4A_L_1_M_1_W_1,
 995   PREFIX_VEX_0F4B_L_1_M_1_W_0,
 996   PREFIX_VEX_0F4B_L_1_M_1_W_1,
 997   PREFIX_VEX_0F51,
 998   PREFIX_VEX_0F52,
 999   PREFIX_VEX_0F53,
1000   PREFIX_VEX_0F58,
1001   PREFIX_VEX_0F59,
1002   PREFIX_VEX_0F5A,
1003   PREFIX_VEX_0F5B,
1004   PREFIX_VEX_0F5C,
1005   PREFIX_VEX_0F5D,
1006   PREFIX_VEX_0F5E,
1007   PREFIX_VEX_0F5F,
1008   PREFIX_VEX_0F6F,
1009   PREFIX_VEX_0F70,
1010   PREFIX_VEX_0F7C,
1011   PREFIX_VEX_0F7D,
1012   PREFIX_VEX_0F7E,
1013   PREFIX_VEX_0F7F,
1014   PREFIX_VEX_0F90_L_0_W_0,
1015   PREFIX_VEX_0F90_L_0_W_1,
1016   PREFIX_VEX_0F91_L_0_M_0_W_0,
1017   PREFIX_VEX_0F91_L_0_M_0_W_1,
1018   PREFIX_VEX_0F92_L_0_M_1_W_0,
1019   PREFIX_VEX_0F92_L_0_M_1_W_1,
1020   PREFIX_VEX_0F93_L_0_M_1_W_0,
1021   PREFIX_VEX_0F93_L_0_M_1_W_1,
1022   PREFIX_VEX_0F98_L_0_M_1_W_0,
1023   PREFIX_VEX_0F98_L_0_M_1_W_1,
1024   PREFIX_VEX_0F99_L_0_M_1_W_0,
1025   PREFIX_VEX_0F99_L_0_M_1_W_1,
1026   PREFIX_VEX_0FC2,
1027   PREFIX_VEX_0FD0,
1028   PREFIX_VEX_0FE6,
1029   PREFIX_VEX_0FF0,
1030   PREFIX_VEX_0F3849_X86_64,
1031   PREFIX_VEX_0F384B_X86_64,
1032   PREFIX_VEX_0F385C_X86_64,
1033   PREFIX_VEX_0F385E_X86_64,
1034   PREFIX_VEX_0F38F5_L_0,
1035   PREFIX_VEX_0F38F6_L_0,
1036   PREFIX_VEX_0F38F7_L_0,
1037   PREFIX_VEX_0F3AF0_L_0,
1038
1039   PREFIX_EVEX_0F10,
1040   PREFIX_EVEX_0F11,
1041   PREFIX_EVEX_0F12,
1042   PREFIX_EVEX_0F16,
1043   PREFIX_EVEX_0F2A,
1044   PREFIX_EVEX_0F51,
1045   PREFIX_EVEX_0F58,
1046   PREFIX_EVEX_0F59,
1047   PREFIX_EVEX_0F5A,
1048   PREFIX_EVEX_0F5B,
1049   PREFIX_EVEX_0F5C,
1050   PREFIX_EVEX_0F5D,
1051   PREFIX_EVEX_0F5E,
1052   PREFIX_EVEX_0F5F,
1053   PREFIX_EVEX_0F6F,
1054   PREFIX_EVEX_0F70,
1055   PREFIX_EVEX_0F78,
1056   PREFIX_EVEX_0F79,
1057   PREFIX_EVEX_0F7A,
1058   PREFIX_EVEX_0F7B,
1059   PREFIX_EVEX_0F7E,
1060   PREFIX_EVEX_0F7F,
1061   PREFIX_EVEX_0FC2,
1062   PREFIX_EVEX_0FE6,
1063   PREFIX_EVEX_0F3810,
1064   PREFIX_EVEX_0F3811,
1065   PREFIX_EVEX_0F3812,
1066   PREFIX_EVEX_0F3813,
1067   PREFIX_EVEX_0F3814,
1068   PREFIX_EVEX_0F3815,
1069   PREFIX_EVEX_0F3820,
1070   PREFIX_EVEX_0F3821,
1071   PREFIX_EVEX_0F3822,
1072   PREFIX_EVEX_0F3823,
1073   PREFIX_EVEX_0F3824,
1074   PREFIX_EVEX_0F3825,
1075   PREFIX_EVEX_0F3826,
1076   PREFIX_EVEX_0F3827,
1077   PREFIX_EVEX_0F3828,
1078   PREFIX_EVEX_0F3829,
1079   PREFIX_EVEX_0F382A,
1080   PREFIX_EVEX_0F3830,
1081   PREFIX_EVEX_0F3831,
1082   PREFIX_EVEX_0F3832,
1083   PREFIX_EVEX_0F3833,
1084   PREFIX_EVEX_0F3834,
1085   PREFIX_EVEX_0F3835,
1086   PREFIX_EVEX_0F3838,
1087   PREFIX_EVEX_0F3839,
1088   PREFIX_EVEX_0F383A,
1089   PREFIX_EVEX_0F3852,
1090   PREFIX_EVEX_0F3853,
1091   PREFIX_EVEX_0F3868,
1092   PREFIX_EVEX_0F3872,
1093   PREFIX_EVEX_0F389A,
1094   PREFIX_EVEX_0F389B,
1095   PREFIX_EVEX_0F38AA,
1096   PREFIX_EVEX_0F38AB,
1097
1098   PREFIX_EVEX_0F3A08_W_0,
1099   PREFIX_EVEX_0F3A0A_W_0,
1100   PREFIX_EVEX_0F3A26,
1101   PREFIX_EVEX_0F3A27,
1102   PREFIX_EVEX_0F3A56,
1103   PREFIX_EVEX_0F3A57,
1104   PREFIX_EVEX_0F3A66,
1105   PREFIX_EVEX_0F3A67,
1106   PREFIX_EVEX_0F3AC2,
1107
1108   PREFIX_EVEX_MAP5_10,
1109   PREFIX_EVEX_MAP5_11,
1110   PREFIX_EVEX_MAP5_1D,
1111   PREFIX_EVEX_MAP5_2A,
1112   PREFIX_EVEX_MAP5_2C,
1113   PREFIX_EVEX_MAP5_2D,
1114   PREFIX_EVEX_MAP5_2E,
1115   PREFIX_EVEX_MAP5_2F,
1116   PREFIX_EVEX_MAP5_51,
1117   PREFIX_EVEX_MAP5_58,
1118   PREFIX_EVEX_MAP5_59,
1119   PREFIX_EVEX_MAP5_5A_W_0,
1120   PREFIX_EVEX_MAP5_5A_W_1,
1121   PREFIX_EVEX_MAP5_5B_W_0,
1122   PREFIX_EVEX_MAP5_5B_W_1,
1123   PREFIX_EVEX_MAP5_5C,
1124   PREFIX_EVEX_MAP5_5D,
1125   PREFIX_EVEX_MAP5_5E,
1126   PREFIX_EVEX_MAP5_5F,
1127   PREFIX_EVEX_MAP5_78,
1128   PREFIX_EVEX_MAP5_79,
1129   PREFIX_EVEX_MAP5_7A,
1130   PREFIX_EVEX_MAP5_7B,
1131   PREFIX_EVEX_MAP5_7C,
1132   PREFIX_EVEX_MAP5_7D_W_0,
1133
1134   PREFIX_EVEX_MAP6_13,
1135   PREFIX_EVEX_MAP6_56,
1136   PREFIX_EVEX_MAP6_57,
1137   PREFIX_EVEX_MAP6_D6,
1138   PREFIX_EVEX_MAP6_D7,
1139 };
1140
1141 enum
1142 {
1143   X86_64_06 = 0,
1144   X86_64_07,
1145   X86_64_0E,
1146   X86_64_16,
1147   X86_64_17,
1148   X86_64_1E,
1149   X86_64_1F,
1150   X86_64_27,
1151   X86_64_2F,
1152   X86_64_37,
1153   X86_64_3F,
1154   X86_64_60,
1155   X86_64_61,
1156   X86_64_62,
1157   X86_64_63,
1158   X86_64_6D,
1159   X86_64_6F,
1160   X86_64_82,
1161   X86_64_9A,
1162   X86_64_C2,
1163   X86_64_C3,
1164   X86_64_C4,
1165   X86_64_C5,
1166   X86_64_CE,
1167   X86_64_D4,
1168   X86_64_D5,
1169   X86_64_E8,
1170   X86_64_E9,
1171   X86_64_EA,
1172   X86_64_0F01_REG_0,
1173   X86_64_0F01_REG_1,
1174   X86_64_0F01_REG_1_RM_5_PREFIX_2,
1175   X86_64_0F01_REG_1_RM_6_PREFIX_2,
1176   X86_64_0F01_REG_1_RM_7_PREFIX_2,
1177   X86_64_0F01_REG_2,
1178   X86_64_0F01_REG_3,
1179   X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1,
1180   X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1,
1181   X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1,
1182   X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1,
1183   X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1,
1184   X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3,
1185   X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1,
1186   X86_64_0F24,
1187   X86_64_0F26,
1188   X86_64_0FC7_REG_6_MOD_3_PREFIX_1,
1189
1190   X86_64_VEX_0F3849,
1191   X86_64_VEX_0F384B,
1192   X86_64_VEX_0F385C,
1193   X86_64_VEX_0F385E
1194 };
1195
1196 enum
1197 {
1198   THREE_BYTE_0F38 = 0,
1199   THREE_BYTE_0F3A
1200 };
1201
1202 enum
1203 {
1204   XOP_08 = 0,
1205   XOP_09,
1206   XOP_0A
1207 };
1208
1209 enum
1210 {
1211   VEX_0F = 0,
1212   VEX_0F38,
1213   VEX_0F3A
1214 };
1215
1216 enum
1217 {
1218   EVEX_0F = 0,
1219   EVEX_0F38,
1220   EVEX_0F3A,
1221   EVEX_MAP5,
1222   EVEX_MAP6,
1223 };
1224
1225 enum
1226 {
1227   VEX_LEN_0F12_P_0_M_0 = 0,
1228   VEX_LEN_0F12_P_0_M_1,
1229 #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0
1230   VEX_LEN_0F13_M_0,
1231   VEX_LEN_0F16_P_0_M_0,
1232   VEX_LEN_0F16_P_0_M_1,
1233 #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0
1234   VEX_LEN_0F17_M_0,
1235   VEX_LEN_0F41,
1236   VEX_LEN_0F42,
1237   VEX_LEN_0F44,
1238   VEX_LEN_0F45,
1239   VEX_LEN_0F46,
1240   VEX_LEN_0F47,
1241   VEX_LEN_0F4A,
1242   VEX_LEN_0F4B,
1243   VEX_LEN_0F6E,
1244   VEX_LEN_0F77,
1245   VEX_LEN_0F7E_P_1,
1246   VEX_LEN_0F7E_P_2,
1247   VEX_LEN_0F90,
1248   VEX_LEN_0F91,
1249   VEX_LEN_0F92,
1250   VEX_LEN_0F93,
1251   VEX_LEN_0F98,
1252   VEX_LEN_0F99,
1253   VEX_LEN_0FAE_R_2_M_0,
1254   VEX_LEN_0FAE_R_3_M_0,
1255   VEX_LEN_0FC4,
1256   VEX_LEN_0FC5,
1257   VEX_LEN_0FD6,
1258   VEX_LEN_0FF7,
1259   VEX_LEN_0F3816,
1260   VEX_LEN_0F3819,
1261   VEX_LEN_0F381A_M_0,
1262   VEX_LEN_0F3836,
1263   VEX_LEN_0F3841,
1264   VEX_LEN_0F3849_X86_64_P_0_W_0_M_0,
1265   VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0,
1266   VEX_LEN_0F3849_X86_64_P_2_W_0_M_0,
1267   VEX_LEN_0F3849_X86_64_P_3_W_0_M_0,
1268   VEX_LEN_0F384B_X86_64_P_1_W_0_M_0,
1269   VEX_LEN_0F384B_X86_64_P_2_W_0_M_0,
1270   VEX_LEN_0F384B_X86_64_P_3_W_0_M_0,
1271   VEX_LEN_0F385A_M_0,
1272   VEX_LEN_0F385C_X86_64_P_1_W_0_M_0,
1273   VEX_LEN_0F385E_X86_64_P_0_W_0_M_0,
1274   VEX_LEN_0F385E_X86_64_P_1_W_0_M_0,
1275   VEX_LEN_0F385E_X86_64_P_2_W_0_M_0,
1276   VEX_LEN_0F385E_X86_64_P_3_W_0_M_0,
1277   VEX_LEN_0F38DB,
1278   VEX_LEN_0F38F2,
1279   VEX_LEN_0F38F3,
1280   VEX_LEN_0F38F5,
1281   VEX_LEN_0F38F6,
1282   VEX_LEN_0F38F7,
1283   VEX_LEN_0F3A00,
1284   VEX_LEN_0F3A01,
1285   VEX_LEN_0F3A06,
1286   VEX_LEN_0F3A14,
1287   VEX_LEN_0F3A15,
1288   VEX_LEN_0F3A16,
1289   VEX_LEN_0F3A17,
1290   VEX_LEN_0F3A18,
1291   VEX_LEN_0F3A19,
1292   VEX_LEN_0F3A20,
1293   VEX_LEN_0F3A21,
1294   VEX_LEN_0F3A22,
1295   VEX_LEN_0F3A30,
1296   VEX_LEN_0F3A31,
1297   VEX_LEN_0F3A32,
1298   VEX_LEN_0F3A33,
1299   VEX_LEN_0F3A38,
1300   VEX_LEN_0F3A39,
1301   VEX_LEN_0F3A41,
1302   VEX_LEN_0F3A46,
1303   VEX_LEN_0F3A60,
1304   VEX_LEN_0F3A61,
1305   VEX_LEN_0F3A62,
1306   VEX_LEN_0F3A63,
1307   VEX_LEN_0F3ADF,
1308   VEX_LEN_0F3AF0,
1309   VEX_LEN_0FXOP_08_85,
1310   VEX_LEN_0FXOP_08_86,
1311   VEX_LEN_0FXOP_08_87,
1312   VEX_LEN_0FXOP_08_8E,
1313   VEX_LEN_0FXOP_08_8F,
1314   VEX_LEN_0FXOP_08_95,
1315   VEX_LEN_0FXOP_08_96,
1316   VEX_LEN_0FXOP_08_97,
1317   VEX_LEN_0FXOP_08_9E,
1318   VEX_LEN_0FXOP_08_9F,
1319   VEX_LEN_0FXOP_08_A3,
1320   VEX_LEN_0FXOP_08_A6,
1321   VEX_LEN_0FXOP_08_B6,
1322   VEX_LEN_0FXOP_08_C0,
1323   VEX_LEN_0FXOP_08_C1,
1324   VEX_LEN_0FXOP_08_C2,
1325   VEX_LEN_0FXOP_08_C3,
1326   VEX_LEN_0FXOP_08_CC,
1327   VEX_LEN_0FXOP_08_CD,
1328   VEX_LEN_0FXOP_08_CE,
1329   VEX_LEN_0FXOP_08_CF,
1330   VEX_LEN_0FXOP_08_EC,
1331   VEX_LEN_0FXOP_08_ED,
1332   VEX_LEN_0FXOP_08_EE,
1333   VEX_LEN_0FXOP_08_EF,
1334   VEX_LEN_0FXOP_09_01,
1335   VEX_LEN_0FXOP_09_02,
1336   VEX_LEN_0FXOP_09_12_M_1,
1337   VEX_LEN_0FXOP_09_82_W_0,
1338   VEX_LEN_0FXOP_09_83_W_0,
1339   VEX_LEN_0FXOP_09_90,
1340   VEX_LEN_0FXOP_09_91,
1341   VEX_LEN_0FXOP_09_92,
1342   VEX_LEN_0FXOP_09_93,
1343   VEX_LEN_0FXOP_09_94,
1344   VEX_LEN_0FXOP_09_95,
1345   VEX_LEN_0FXOP_09_96,
1346   VEX_LEN_0FXOP_09_97,
1347   VEX_LEN_0FXOP_09_98,
1348   VEX_LEN_0FXOP_09_99,
1349   VEX_LEN_0FXOP_09_9A,
1350   VEX_LEN_0FXOP_09_9B,
1351   VEX_LEN_0FXOP_09_C1,
1352   VEX_LEN_0FXOP_09_C2,
1353   VEX_LEN_0FXOP_09_C3,
1354   VEX_LEN_0FXOP_09_C6,
1355   VEX_LEN_0FXOP_09_C7,
1356   VEX_LEN_0FXOP_09_CB,
1357   VEX_LEN_0FXOP_09_D1,
1358   VEX_LEN_0FXOP_09_D2,
1359   VEX_LEN_0FXOP_09_D3,
1360   VEX_LEN_0FXOP_09_D6,
1361   VEX_LEN_0FXOP_09_D7,
1362   VEX_LEN_0FXOP_09_DB,
1363   VEX_LEN_0FXOP_09_E1,
1364   VEX_LEN_0FXOP_09_E2,
1365   VEX_LEN_0FXOP_09_E3,
1366   VEX_LEN_0FXOP_0A_12,
1367 };
1368
1369 enum
1370 {
1371   EVEX_LEN_0F3816 = 0,
1372   EVEX_LEN_0F3819,
1373   EVEX_LEN_0F381A_M_0,
1374   EVEX_LEN_0F381B_M_0,
1375   EVEX_LEN_0F3836,
1376   EVEX_LEN_0F385A_M_0,
1377   EVEX_LEN_0F385B_M_0,
1378   EVEX_LEN_0F38C6_M_0,
1379   EVEX_LEN_0F38C7_M_0,
1380   EVEX_LEN_0F3A00,
1381   EVEX_LEN_0F3A01,
1382   EVEX_LEN_0F3A18,
1383   EVEX_LEN_0F3A19,
1384   EVEX_LEN_0F3A1A,
1385   EVEX_LEN_0F3A1B,
1386   EVEX_LEN_0F3A23,
1387   EVEX_LEN_0F3A38,
1388   EVEX_LEN_0F3A39,
1389   EVEX_LEN_0F3A3A,
1390   EVEX_LEN_0F3A3B,
1391   EVEX_LEN_0F3A43
1392 };
1393
1394 enum
1395 {
1396   VEX_W_0F41_L_1_M_1 = 0,
1397   VEX_W_0F42_L_1_M_1,
1398   VEX_W_0F44_L_0_M_1,
1399   VEX_W_0F45_L_1_M_1,
1400   VEX_W_0F46_L_1_M_1,
1401   VEX_W_0F47_L_1_M_1,
1402   VEX_W_0F4A_L_1_M_1,
1403   VEX_W_0F4B_L_1_M_1,
1404   VEX_W_0F90_L_0,
1405   VEX_W_0F91_L_0_M_0,
1406   VEX_W_0F92_L_0_M_1,
1407   VEX_W_0F93_L_0_M_1,
1408   VEX_W_0F98_L_0_M_1,
1409   VEX_W_0F99_L_0_M_1,
1410   VEX_W_0F380C,
1411   VEX_W_0F380D,
1412   VEX_W_0F380E,
1413   VEX_W_0F380F,
1414   VEX_W_0F3813,
1415   VEX_W_0F3816_L_1,
1416   VEX_W_0F3818,
1417   VEX_W_0F3819_L_1,
1418   VEX_W_0F381A_M_0_L_1,
1419   VEX_W_0F382C_M_0,
1420   VEX_W_0F382D_M_0,
1421   VEX_W_0F382E_M_0,
1422   VEX_W_0F382F_M_0,
1423   VEX_W_0F3836,
1424   VEX_W_0F3846,
1425   VEX_W_0F3849_X86_64_P_0,
1426   VEX_W_0F3849_X86_64_P_2,
1427   VEX_W_0F3849_X86_64_P_3,
1428   VEX_W_0F384B_X86_64_P_1,
1429   VEX_W_0F384B_X86_64_P_2,
1430   VEX_W_0F384B_X86_64_P_3,
1431   VEX_W_0F3850,
1432   VEX_W_0F3851,
1433   VEX_W_0F3852,
1434   VEX_W_0F3853,
1435   VEX_W_0F3858,
1436   VEX_W_0F3859,
1437   VEX_W_0F385A_M_0_L_0,
1438   VEX_W_0F385C_X86_64_P_1,
1439   VEX_W_0F385E_X86_64_P_0,
1440   VEX_W_0F385E_X86_64_P_1,
1441   VEX_W_0F385E_X86_64_P_2,
1442   VEX_W_0F385E_X86_64_P_3,
1443   VEX_W_0F3878,
1444   VEX_W_0F3879,
1445   VEX_W_0F38CF,
1446   VEX_W_0F3A00_L_1,
1447   VEX_W_0F3A01_L_1,
1448   VEX_W_0F3A02,
1449   VEX_W_0F3A04,
1450   VEX_W_0F3A05,
1451   VEX_W_0F3A06_L_1,
1452   VEX_W_0F3A18_L_1,
1453   VEX_W_0F3A19_L_1,
1454   VEX_W_0F3A1D,
1455   VEX_W_0F3A38_L_1,
1456   VEX_W_0F3A39_L_1,
1457   VEX_W_0F3A46_L_1,
1458   VEX_W_0F3A4A,
1459   VEX_W_0F3A4B,
1460   VEX_W_0F3A4C,
1461   VEX_W_0F3ACE,
1462   VEX_W_0F3ACF,
1463
1464   VEX_W_0FXOP_08_85_L_0,
1465   VEX_W_0FXOP_08_86_L_0,
1466   VEX_W_0FXOP_08_87_L_0,
1467   VEX_W_0FXOP_08_8E_L_0,
1468   VEX_W_0FXOP_08_8F_L_0,
1469   VEX_W_0FXOP_08_95_L_0,
1470   VEX_W_0FXOP_08_96_L_0,
1471   VEX_W_0FXOP_08_97_L_0,
1472   VEX_W_0FXOP_08_9E_L_0,
1473   VEX_W_0FXOP_08_9F_L_0,
1474   VEX_W_0FXOP_08_A6_L_0,
1475   VEX_W_0FXOP_08_B6_L_0,
1476   VEX_W_0FXOP_08_C0_L_0,
1477   VEX_W_0FXOP_08_C1_L_0,
1478   VEX_W_0FXOP_08_C2_L_0,
1479   VEX_W_0FXOP_08_C3_L_0,
1480   VEX_W_0FXOP_08_CC_L_0,
1481   VEX_W_0FXOP_08_CD_L_0,
1482   VEX_W_0FXOP_08_CE_L_0,
1483   VEX_W_0FXOP_08_CF_L_0,
1484   VEX_W_0FXOP_08_EC_L_0,
1485   VEX_W_0FXOP_08_ED_L_0,
1486   VEX_W_0FXOP_08_EE_L_0,
1487   VEX_W_0FXOP_08_EF_L_0,
1488
1489   VEX_W_0FXOP_09_80,
1490   VEX_W_0FXOP_09_81,
1491   VEX_W_0FXOP_09_82,
1492   VEX_W_0FXOP_09_83,
1493   VEX_W_0FXOP_09_C1_L_0,
1494   VEX_W_0FXOP_09_C2_L_0,
1495   VEX_W_0FXOP_09_C3_L_0,
1496   VEX_W_0FXOP_09_C6_L_0,
1497   VEX_W_0FXOP_09_C7_L_0,
1498   VEX_W_0FXOP_09_CB_L_0,
1499   VEX_W_0FXOP_09_D1_L_0,
1500   VEX_W_0FXOP_09_D2_L_0,
1501   VEX_W_0FXOP_09_D3_L_0,
1502   VEX_W_0FXOP_09_D6_L_0,
1503   VEX_W_0FXOP_09_D7_L_0,
1504   VEX_W_0FXOP_09_DB_L_0,
1505   VEX_W_0FXOP_09_E1_L_0,
1506   VEX_W_0FXOP_09_E2_L_0,
1507   VEX_W_0FXOP_09_E3_L_0,
1508
1509   EVEX_W_0F10_P_1,
1510   EVEX_W_0F10_P_3,
1511   EVEX_W_0F11_P_1,
1512   EVEX_W_0F11_P_3,
1513   EVEX_W_0F12_P_0_M_1,
1514   EVEX_W_0F12_P_1,
1515   EVEX_W_0F12_P_3,
1516   EVEX_W_0F16_P_0_M_1,
1517   EVEX_W_0F16_P_1,
1518   EVEX_W_0F51_P_1,
1519   EVEX_W_0F51_P_3,
1520   EVEX_W_0F58_P_1,
1521   EVEX_W_0F58_P_3,
1522   EVEX_W_0F59_P_1,
1523   EVEX_W_0F59_P_3,
1524   EVEX_W_0F5A_P_0,
1525   EVEX_W_0F5A_P_1,
1526   EVEX_W_0F5A_P_2,
1527   EVEX_W_0F5A_P_3,
1528   EVEX_W_0F5B_P_0,
1529   EVEX_W_0F5B_P_1,
1530   EVEX_W_0F5B_P_2,
1531   EVEX_W_0F5C_P_1,
1532   EVEX_W_0F5C_P_3,
1533   EVEX_W_0F5D_P_1,
1534   EVEX_W_0F5D_P_3,
1535   EVEX_W_0F5E_P_1,
1536   EVEX_W_0F5E_P_3,
1537   EVEX_W_0F5F_P_1,
1538   EVEX_W_0F5F_P_3,
1539   EVEX_W_0F62,
1540   EVEX_W_0F66,
1541   EVEX_W_0F6A,
1542   EVEX_W_0F6B,
1543   EVEX_W_0F6C,
1544   EVEX_W_0F6D,
1545   EVEX_W_0F6F_P_1,
1546   EVEX_W_0F6F_P_2,
1547   EVEX_W_0F6F_P_3,
1548   EVEX_W_0F70_P_2,
1549   EVEX_W_0F72_R_2,
1550   EVEX_W_0F72_R_6,
1551   EVEX_W_0F73_R_2,
1552   EVEX_W_0F73_R_6,
1553   EVEX_W_0F76,
1554   EVEX_W_0F78_P_0,
1555   EVEX_W_0F78_P_2,
1556   EVEX_W_0F79_P_0,
1557   EVEX_W_0F79_P_2,
1558   EVEX_W_0F7A_P_1,
1559   EVEX_W_0F7A_P_2,
1560   EVEX_W_0F7A_P_3,
1561   EVEX_W_0F7B_P_2,
1562   EVEX_W_0F7E_P_1,
1563   EVEX_W_0F7F_P_1,
1564   EVEX_W_0F7F_P_2,
1565   EVEX_W_0F7F_P_3,
1566   EVEX_W_0FC2_P_1,
1567   EVEX_W_0FC2_P_3,
1568   EVEX_W_0FD2,
1569   EVEX_W_0FD3,
1570   EVEX_W_0FD4,
1571   EVEX_W_0FD6,
1572   EVEX_W_0FE6_P_1,
1573   EVEX_W_0FE6_P_2,
1574   EVEX_W_0FE6_P_3,
1575   EVEX_W_0FE7,
1576   EVEX_W_0FF2,
1577   EVEX_W_0FF3,
1578   EVEX_W_0FF4,
1579   EVEX_W_0FFA,
1580   EVEX_W_0FFB,
1581   EVEX_W_0FFE,
1582   EVEX_W_0F380D,
1583   EVEX_W_0F3810_P_1,
1584   EVEX_W_0F3810_P_2,
1585   EVEX_W_0F3811_P_1,
1586   EVEX_W_0F3811_P_2,
1587   EVEX_W_0F3812_P_1,
1588   EVEX_W_0F3812_P_2,
1589   EVEX_W_0F3813_P_1,
1590   EVEX_W_0F3813_P_2,
1591   EVEX_W_0F3814_P_1,
1592   EVEX_W_0F3815_P_1,
1593   EVEX_W_0F3819_L_n,
1594   EVEX_W_0F381A_M_0_L_n,
1595   EVEX_W_0F381B_M_0_L_2,
1596   EVEX_W_0F381E,
1597   EVEX_W_0F381F,
1598   EVEX_W_0F3820_P_1,
1599   EVEX_W_0F3821_P_1,
1600   EVEX_W_0F3822_P_1,
1601   EVEX_W_0F3823_P_1,
1602   EVEX_W_0F3824_P_1,
1603   EVEX_W_0F3825_P_1,
1604   EVEX_W_0F3825_P_2,
1605   EVEX_W_0F3828_P_2,
1606   EVEX_W_0F3829_P_2,
1607   EVEX_W_0F382A_P_1,
1608   EVEX_W_0F382A_P_2,
1609   EVEX_W_0F382B,
1610   EVEX_W_0F3830_P_1,
1611   EVEX_W_0F3831_P_1,
1612   EVEX_W_0F3832_P_1,
1613   EVEX_W_0F3833_P_1,
1614   EVEX_W_0F3834_P_1,
1615   EVEX_W_0F3835_P_1,
1616   EVEX_W_0F3835_P_2,
1617   EVEX_W_0F3837,
1618   EVEX_W_0F383A_P_1,
1619   EVEX_W_0F3852_P_1,
1620   EVEX_W_0F3859,
1621   EVEX_W_0F385A_M_0_L_n,
1622   EVEX_W_0F385B_M_0_L_2,
1623   EVEX_W_0F3870,
1624   EVEX_W_0F3872_P_1,
1625   EVEX_W_0F3872_P_2,
1626   EVEX_W_0F3872_P_3,
1627   EVEX_W_0F387A,
1628   EVEX_W_0F387B,
1629   EVEX_W_0F3883,
1630
1631   EVEX_W_0F3A05,
1632   EVEX_W_0F3A08,
1633   EVEX_W_0F3A09,
1634   EVEX_W_0F3A0A,
1635   EVEX_W_0F3A0B,
1636   EVEX_W_0F3A18_L_n,
1637   EVEX_W_0F3A19_L_n,
1638   EVEX_W_0F3A1A_L_2,
1639   EVEX_W_0F3A1B_L_2,
1640   EVEX_W_0F3A21,
1641   EVEX_W_0F3A23_L_n,
1642   EVEX_W_0F3A38_L_n,
1643   EVEX_W_0F3A39_L_n,
1644   EVEX_W_0F3A3A_L_2,
1645   EVEX_W_0F3A3B_L_2,
1646   EVEX_W_0F3A42,
1647   EVEX_W_0F3A43_L_n,
1648   EVEX_W_0F3A70,
1649   EVEX_W_0F3A72,
1650
1651   EVEX_W_MAP5_5A,
1652   EVEX_W_MAP5_5B,
1653   EVEX_W_MAP5_78_P_0,
1654   EVEX_W_MAP5_78_P_2,
1655   EVEX_W_MAP5_79_P_0,
1656   EVEX_W_MAP5_79_P_2,
1657   EVEX_W_MAP5_7A_P_2,
1658   EVEX_W_MAP5_7A_P_3,
1659   EVEX_W_MAP5_7B_P_2,
1660   EVEX_W_MAP5_7C_P_0,
1661   EVEX_W_MAP5_7C_P_2,
1662   EVEX_W_MAP5_7D,
1663
1664   EVEX_W_MAP6_13_P_0,
1665   EVEX_W_MAP6_13_P_2,
1666 };
1667
1668 typedef void (*op_rtn) (int bytemode, int sizeflag);
1669
1670 struct dis386 {
1671   const char *name;
1672   struct
1673     {
1674       op_rtn rtn;
1675       int bytemode;
1676     } op[MAX_OPERANDS];
1677   unsigned int prefix_requirement;
1678 };
1679
1680 /* Upper case letters in the instruction names here are macros.
1681    'A' => print 'b' if no register operands or suffix_always is true
1682    'B' => print 'b' if suffix_always is true
1683    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1684           size prefix
1685    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1686           suffix_always is true
1687    'E' => print 'e' if 32-bit form of jcxz
1688    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1689    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1690    'H' => print ",pt" or ",pn" branch hint
1691    'I' unused.
1692    'J' unused.
1693    'K' => print 'd' or 'q' if rex prefix is present.
1694    'L' unused.
1695    'M' => print 'r' if intel_mnemonic is false.
1696    'N' => print 'n' if instruction has no wait "prefix"
1697    'O' => print 'd' or 'o' (or 'q' in Intel mode)
1698    'P' => behave as 'T' except with register operand outside of suffix_always
1699           mode
1700    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1701           is true
1702    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1703    'S' => print 'w', 'l' or 'q' if suffix_always is true
1704    'T' => print 'w', 'l'/'d', or 'q' if instruction has an operand size
1705           prefix or if suffix_always is true.
1706    'U' unused.
1707    'V' unused.
1708    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1709    'X' => print 's', 'd' depending on data16 prefix (for XMM)
1710    'Y' unused.
1711    'Z' => print 'q' in 64bit mode and 'l' otherwise, if suffix_always is true.
1712    '!' => change condition from true to false or from false to true.
1713    '%' => add 1 upper case letter to the macro.
1714    '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
1715           prefix or suffix_always is true (lcall/ljmp).
1716    '@' => in 64bit mode for Intel64 ISA or if instruction
1717           has no operand sizing prefix, print 'q' if suffix_always is true or
1718           nothing otherwise; behave as 'P' in all other cases
1719
1720    2 upper case letter macros:
1721    "XY" => print 'x' or 'y' if suffix_always is true or no register
1722            operands and no broadcast.
1723    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
1724            register operands and no broadcast.
1725    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1726    "XH" => print 'h' if EVEX.W=0, EVEX.W=1 is not a valid encoding (for FP16)
1727    "XV" => print "{vex3}" pseudo prefix
1728    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond
1729            being false, or no operand at all in 64bit mode, or if suffix_always
1730            is true.
1731    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1732    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1733    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1734    "DQ" => print 'd' or 'q' depending on the VEX.W bit
1735    "BW" => print 'b' or 'w' depending on the VEX.W bit
1736    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
1737            an operand size prefix, or suffix_always is true.  print
1738            'q' if rex prefix is present.
1739
1740    Many of the above letters print nothing in Intel mode.  See "putop"
1741    for the details.
1742
1743    Braces '{' and '}', and vertical bars '|', indicate alternative
1744    mnemonic strings for AT&T and Intel.  */
1745
1746 static const struct dis386 dis386[] = {
1747   /* 00 */
1748   { "addB",             { Ebh1, Gb }, 0 },
1749   { "addS",             { Evh1, Gv }, 0 },
1750   { "addB",             { Gb, EbS }, 0 },
1751   { "addS",             { Gv, EvS }, 0 },
1752   { "addB",             { AL, Ib }, 0 },
1753   { "addS",             { eAX, Iv }, 0 },
1754   { X86_64_TABLE (X86_64_06) },
1755   { X86_64_TABLE (X86_64_07) },
1756   /* 08 */
1757   { "orB",              { Ebh1, Gb }, 0 },
1758   { "orS",              { Evh1, Gv }, 0 },
1759   { "orB",              { Gb, EbS }, 0 },
1760   { "orS",              { Gv, EvS }, 0 },
1761   { "orB",              { AL, Ib }, 0 },
1762   { "orS",              { eAX, Iv }, 0 },
1763   { X86_64_TABLE (X86_64_0E) },
1764   { Bad_Opcode },       /* 0x0f extended opcode escape */
1765   /* 10 */
1766   { "adcB",             { Ebh1, Gb }, 0 },
1767   { "adcS",             { Evh1, Gv }, 0 },
1768   { "adcB",             { Gb, EbS }, 0 },
1769   { "adcS",             { Gv, EvS }, 0 },
1770   { "adcB",             { AL, Ib }, 0 },
1771   { "adcS",             { eAX, Iv }, 0 },
1772   { X86_64_TABLE (X86_64_16) },
1773   { X86_64_TABLE (X86_64_17) },
1774   /* 18 */
1775   { "sbbB",             { Ebh1, Gb }, 0 },
1776   { "sbbS",             { Evh1, Gv }, 0 },
1777   { "sbbB",             { Gb, EbS }, 0 },
1778   { "sbbS",             { Gv, EvS }, 0 },
1779   { "sbbB",             { AL, Ib }, 0 },
1780   { "sbbS",             { eAX, Iv }, 0 },
1781   { X86_64_TABLE (X86_64_1E) },
1782   { X86_64_TABLE (X86_64_1F) },
1783   /* 20 */
1784   { "andB",             { Ebh1, Gb }, 0 },
1785   { "andS",             { Evh1, Gv }, 0 },
1786   { "andB",             { Gb, EbS }, 0 },
1787   { "andS",             { Gv, EvS }, 0 },
1788   { "andB",             { AL, Ib }, 0 },
1789   { "andS",             { eAX, Iv }, 0 },
1790   { Bad_Opcode },       /* SEG ES prefix */
1791   { X86_64_TABLE (X86_64_27) },
1792   /* 28 */
1793   { "subB",             { Ebh1, Gb }, 0 },
1794   { "subS",             { Evh1, Gv }, 0 },
1795   { "subB",             { Gb, EbS }, 0 },
1796   { "subS",             { Gv, EvS }, 0 },
1797   { "subB",             { AL, Ib }, 0 },
1798   { "subS",             { eAX, Iv }, 0 },
1799   { Bad_Opcode },       /* SEG CS prefix */
1800   { X86_64_TABLE (X86_64_2F) },
1801   /* 30 */
1802   { "xorB",             { Ebh1, Gb }, 0 },
1803   { "xorS",             { Evh1, Gv }, 0 },
1804   { "xorB",             { Gb, EbS }, 0 },
1805   { "xorS",             { Gv, EvS }, 0 },
1806   { "xorB",             { AL, Ib }, 0 },
1807   { "xorS",             { eAX, Iv }, 0 },
1808   { Bad_Opcode },       /* SEG SS prefix */
1809   { X86_64_TABLE (X86_64_37) },
1810   /* 38 */
1811   { "cmpB",             { Eb, Gb }, 0 },
1812   { "cmpS",             { Ev, Gv }, 0 },
1813   { "cmpB",             { Gb, EbS }, 0 },
1814   { "cmpS",             { Gv, EvS }, 0 },
1815   { "cmpB",             { AL, Ib }, 0 },
1816   { "cmpS",             { eAX, Iv }, 0 },
1817   { Bad_Opcode },       /* SEG DS prefix */
1818   { X86_64_TABLE (X86_64_3F) },
1819   /* 40 */
1820   { "inc{S|}",          { RMeAX }, 0 },
1821   { "inc{S|}",          { RMeCX }, 0 },
1822   { "inc{S|}",          { RMeDX }, 0 },
1823   { "inc{S|}",          { RMeBX }, 0 },
1824   { "inc{S|}",          { RMeSP }, 0 },
1825   { "inc{S|}",          { RMeBP }, 0 },
1826   { "inc{S|}",          { RMeSI }, 0 },
1827   { "inc{S|}",          { RMeDI }, 0 },
1828   /* 48 */
1829   { "dec{S|}",          { RMeAX }, 0 },
1830   { "dec{S|}",          { RMeCX }, 0 },
1831   { "dec{S|}",          { RMeDX }, 0 },
1832   { "dec{S|}",          { RMeBX }, 0 },
1833   { "dec{S|}",          { RMeSP }, 0 },
1834   { "dec{S|}",          { RMeBP }, 0 },
1835   { "dec{S|}",          { RMeSI }, 0 },
1836   { "dec{S|}",          { RMeDI }, 0 },
1837   /* 50 */
1838   { "push{!P|}",                { RMrAX }, 0 },
1839   { "push{!P|}",                { RMrCX }, 0 },
1840   { "push{!P|}",                { RMrDX }, 0 },
1841   { "push{!P|}",                { RMrBX }, 0 },
1842   { "push{!P|}",                { RMrSP }, 0 },
1843   { "push{!P|}",                { RMrBP }, 0 },
1844   { "push{!P|}",                { RMrSI }, 0 },
1845   { "push{!P|}",                { RMrDI }, 0 },
1846   /* 58 */
1847   { "pop{!P|}",         { RMrAX }, 0 },
1848   { "pop{!P|}",         { RMrCX }, 0 },
1849   { "pop{!P|}",         { RMrDX }, 0 },
1850   { "pop{!P|}",         { RMrBX }, 0 },
1851   { "pop{!P|}",         { RMrSP }, 0 },
1852   { "pop{!P|}",         { RMrBP }, 0 },
1853   { "pop{!P|}",         { RMrSI }, 0 },
1854   { "pop{!P|}",         { RMrDI }, 0 },
1855   /* 60 */
1856   { X86_64_TABLE (X86_64_60) },
1857   { X86_64_TABLE (X86_64_61) },
1858   { X86_64_TABLE (X86_64_62) },
1859   { X86_64_TABLE (X86_64_63) },
1860   { Bad_Opcode },       /* seg fs */
1861   { Bad_Opcode },       /* seg gs */
1862   { Bad_Opcode },       /* op size prefix */
1863   { Bad_Opcode },       /* adr size prefix */
1864   /* 68 */
1865   { "pushP",            { sIv }, 0 },
1866   { "imulS",            { Gv, Ev, Iv }, 0 },
1867   { "pushP",            { sIbT }, 0 },
1868   { "imulS",            { Gv, Ev, sIb }, 0 },
1869   { "ins{b|}",          { Ybr, indirDX }, 0 },
1870   { X86_64_TABLE (X86_64_6D) },
1871   { "outs{b|}",         { indirDXr, Xb }, 0 },
1872   { X86_64_TABLE (X86_64_6F) },
1873   /* 70 */
1874   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
1875   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
1876   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
1877   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
1878   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
1879   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
1880   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
1881   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
1882   /* 78 */
1883   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
1884   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
1885   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
1886   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
1887   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
1888   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
1889   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
1890   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
1891   /* 80 */
1892   { REG_TABLE (REG_80) },
1893   { REG_TABLE (REG_81) },
1894   { X86_64_TABLE (X86_64_82) },
1895   { REG_TABLE (REG_83) },
1896   { "testB",            { Eb, Gb }, 0 },
1897   { "testS",            { Ev, Gv }, 0 },
1898   { "xchgB",            { Ebh2, Gb }, 0 },
1899   { "xchgS",            { Evh2, Gv }, 0 },
1900   /* 88 */
1901   { "movB",             { Ebh3, Gb }, 0 },
1902   { "movS",             { Evh3, Gv }, 0 },
1903   { "movB",             { Gb, EbS }, 0 },
1904   { "movS",             { Gv, EvS }, 0 },
1905   { "movD",             { Sv, Sw }, 0 },
1906   { MOD_TABLE (MOD_8D) },
1907   { "movD",             { Sw, Sv }, 0 },
1908   { REG_TABLE (REG_8F) },
1909   /* 90 */
1910   { PREFIX_TABLE (PREFIX_90) },
1911   { "xchgS",            { RMeCX, eAX }, 0 },
1912   { "xchgS",            { RMeDX, eAX }, 0 },
1913   { "xchgS",            { RMeBX, eAX }, 0 },
1914   { "xchgS",            { RMeSP, eAX }, 0 },
1915   { "xchgS",            { RMeBP, eAX }, 0 },
1916   { "xchgS",            { RMeSI, eAX }, 0 },
1917   { "xchgS",            { RMeDI, eAX }, 0 },
1918   /* 98 */
1919   { "cW{t|}R",          { XX }, 0 },
1920   { "cR{t|}O",          { XX }, 0 },
1921   { X86_64_TABLE (X86_64_9A) },
1922   { Bad_Opcode },       /* fwait */
1923   { "pushfP",           { XX }, 0 },
1924   { "popfP",            { XX }, 0 },
1925   { "sahf",             { XX }, 0 },
1926   { "lahf",             { XX }, 0 },
1927   /* a0 */
1928   { "mov%LB",           { AL, Ob }, 0 },
1929   { "mov%LS",           { eAX, Ov }, 0 },
1930   { "mov%LB",           { Ob, AL }, 0 },
1931   { "mov%LS",           { Ov, eAX }, 0 },
1932   { "movs{b|}",         { Ybr, Xb }, 0 },
1933   { "movs{R|}",         { Yvr, Xv }, 0 },
1934   { "cmps{b|}",         { Xb, Yb }, 0 },
1935   { "cmps{R|}",         { Xv, Yv }, 0 },
1936   /* a8 */
1937   { "testB",            { AL, Ib }, 0 },
1938   { "testS",            { eAX, Iv }, 0 },
1939   { "stosB",            { Ybr, AL }, 0 },
1940   { "stosS",            { Yvr, eAX }, 0 },
1941   { "lodsB",            { ALr, Xb }, 0 },
1942   { "lodsS",            { eAXr, Xv }, 0 },
1943   { "scasB",            { AL, Yb }, 0 },
1944   { "scasS",            { eAX, Yv }, 0 },
1945   /* b0 */
1946   { "movB",             { RMAL, Ib }, 0 },
1947   { "movB",             { RMCL, Ib }, 0 },
1948   { "movB",             { RMDL, Ib }, 0 },
1949   { "movB",             { RMBL, Ib }, 0 },
1950   { "movB",             { RMAH, Ib }, 0 },
1951   { "movB",             { RMCH, Ib }, 0 },
1952   { "movB",             { RMDH, Ib }, 0 },
1953   { "movB",             { RMBH, Ib }, 0 },
1954   /* b8 */
1955   { "mov%LV",           { RMeAX, Iv64 }, 0 },
1956   { "mov%LV",           { RMeCX, Iv64 }, 0 },
1957   { "mov%LV",           { RMeDX, Iv64 }, 0 },
1958   { "mov%LV",           { RMeBX, Iv64 }, 0 },
1959   { "mov%LV",           { RMeSP, Iv64 }, 0 },
1960   { "mov%LV",           { RMeBP, Iv64 }, 0 },
1961   { "mov%LV",           { RMeSI, Iv64 }, 0 },
1962   { "mov%LV",           { RMeDI, Iv64 }, 0 },
1963   /* c0 */
1964   { REG_TABLE (REG_C0) },
1965   { REG_TABLE (REG_C1) },
1966   { X86_64_TABLE (X86_64_C2) },
1967   { X86_64_TABLE (X86_64_C3) },
1968   { X86_64_TABLE (X86_64_C4) },
1969   { X86_64_TABLE (X86_64_C5) },
1970   { REG_TABLE (REG_C6) },
1971   { REG_TABLE (REG_C7) },
1972   /* c8 */
1973   { "enterP",           { Iw, Ib }, 0 },
1974   { "leaveP",           { XX }, 0 },
1975   { "{l|}ret{|f}%LP",   { Iw }, 0 },
1976   { "{l|}ret{|f}%LP",   { XX }, 0 },
1977   { "int3",             { XX }, 0 },
1978   { "int",              { Ib }, 0 },
1979   { X86_64_TABLE (X86_64_CE) },
1980   { "iret%LP",          { XX }, 0 },
1981   /* d0 */
1982   { REG_TABLE (REG_D0) },
1983   { REG_TABLE (REG_D1) },
1984   { REG_TABLE (REG_D2) },
1985   { REG_TABLE (REG_D3) },
1986   { X86_64_TABLE (X86_64_D4) },
1987   { X86_64_TABLE (X86_64_D5) },
1988   { Bad_Opcode },
1989   { "xlat",             { DSBX }, 0 },
1990   /* d8 */
1991   { FLOAT },
1992   { FLOAT },
1993   { FLOAT },
1994   { FLOAT },
1995   { FLOAT },
1996   { FLOAT },
1997   { FLOAT },
1998   { FLOAT },
1999   /* e0 */
2000   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2001   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2002   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2003   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2004   { "inB",              { AL, Ib }, 0 },
2005   { "inG",              { zAX, Ib }, 0 },
2006   { "outB",             { Ib, AL }, 0 },
2007   { "outG",             { Ib, zAX }, 0 },
2008   /* e8 */
2009   { X86_64_TABLE (X86_64_E8) },
2010   { X86_64_TABLE (X86_64_E9) },
2011   { X86_64_TABLE (X86_64_EA) },
2012   { "jmp",              { Jb, BND }, 0 },
2013   { "inB",              { AL, indirDX }, 0 },
2014   { "inG",              { zAX, indirDX }, 0 },
2015   { "outB",             { indirDX, AL }, 0 },
2016   { "outG",             { indirDX, zAX }, 0 },
2017   /* f0 */
2018   { Bad_Opcode },       /* lock prefix */
2019   { "int1",             { XX }, 0 },
2020   { Bad_Opcode },       /* repne */
2021   { Bad_Opcode },       /* repz */
2022   { "hlt",              { XX }, 0 },
2023   { "cmc",              { XX }, 0 },
2024   { REG_TABLE (REG_F6) },
2025   { REG_TABLE (REG_F7) },
2026   /* f8 */
2027   { "clc",              { XX }, 0 },
2028   { "stc",              { XX }, 0 },
2029   { "cli",              { XX }, 0 },
2030   { "sti",              { XX }, 0 },
2031   { "cld",              { XX }, 0 },
2032   { "std",              { XX }, 0 },
2033   { REG_TABLE (REG_FE) },
2034   { REG_TABLE (REG_FF) },
2035 };
2036
2037 static const struct dis386 dis386_twobyte[] = {
2038   /* 00 */
2039   { REG_TABLE (REG_0F00 ) },
2040   { REG_TABLE (REG_0F01 ) },
2041   { "larS",             { Gv, Ew }, 0 },
2042   { "lslS",             { Gv, Ew }, 0 },
2043   { Bad_Opcode },
2044   { "syscall",          { XX }, 0 },
2045   { "clts",             { XX }, 0 },
2046   { "sysret%LQ",                { XX }, 0 },
2047   /* 08 */
2048   { "invd",             { XX }, 0 },
2049   { PREFIX_TABLE (PREFIX_0F09) },
2050   { Bad_Opcode },
2051   { "ud2",              { XX }, 0 },
2052   { Bad_Opcode },
2053   { REG_TABLE (REG_0F0D) },
2054   { "femms",            { XX }, 0 },
2055   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2056   /* 10 */
2057   { PREFIX_TABLE (PREFIX_0F10) },
2058   { PREFIX_TABLE (PREFIX_0F11) },
2059   { PREFIX_TABLE (PREFIX_0F12) },
2060   { MOD_TABLE (MOD_0F13) },
2061   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2062   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2063   { PREFIX_TABLE (PREFIX_0F16) },
2064   { MOD_TABLE (MOD_0F17) },
2065   /* 18 */
2066   { REG_TABLE (REG_0F18) },
2067   { "nopQ",             { Ev }, 0 },
2068   { PREFIX_TABLE (PREFIX_0F1A) },
2069   { PREFIX_TABLE (PREFIX_0F1B) },
2070   { PREFIX_TABLE (PREFIX_0F1C) },
2071   { "nopQ",             { Ev }, 0 },
2072   { PREFIX_TABLE (PREFIX_0F1E) },
2073   { "nopQ",             { Ev }, 0 },
2074   /* 20 */
2075   { "movZ",             { Em, Cm }, 0 },
2076   { "movZ",             { Em, Dm }, 0 },
2077   { "movZ",             { Cm, Em }, 0 },
2078   { "movZ",             { Dm, Em }, 0 },
2079   { X86_64_TABLE (X86_64_0F24) },
2080   { Bad_Opcode },
2081   { X86_64_TABLE (X86_64_0F26) },
2082   { Bad_Opcode },
2083   /* 28 */
2084   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2085   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2086   { PREFIX_TABLE (PREFIX_0F2A) },
2087   { PREFIX_TABLE (PREFIX_0F2B) },
2088   { PREFIX_TABLE (PREFIX_0F2C) },
2089   { PREFIX_TABLE (PREFIX_0F2D) },
2090   { PREFIX_TABLE (PREFIX_0F2E) },
2091   { PREFIX_TABLE (PREFIX_0F2F) },
2092   /* 30 */
2093   { "wrmsr",            { XX }, 0 },
2094   { "rdtsc",            { XX }, 0 },
2095   { "rdmsr",            { XX }, 0 },
2096   { "rdpmc",            { XX }, 0 },
2097   { "sysenter",         { SEP }, 0 },
2098   { "sysexit%LQ",       { SEP }, 0 },
2099   { Bad_Opcode },
2100   { "getsec",           { XX }, 0 },
2101   /* 38 */
2102   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2103   { Bad_Opcode },
2104   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2105   { Bad_Opcode },
2106   { Bad_Opcode },
2107   { Bad_Opcode },
2108   { Bad_Opcode },
2109   { Bad_Opcode },
2110   /* 40 */
2111   { "cmovoS",           { Gv, Ev }, 0 },
2112   { "cmovnoS",          { Gv, Ev }, 0 },
2113   { "cmovbS",           { Gv, Ev }, 0 },
2114   { "cmovaeS",          { Gv, Ev }, 0 },
2115   { "cmoveS",           { Gv, Ev }, 0 },
2116   { "cmovneS",          { Gv, Ev }, 0 },
2117   { "cmovbeS",          { Gv, Ev }, 0 },
2118   { "cmovaS",           { Gv, Ev }, 0 },
2119   /* 48 */
2120   { "cmovsS",           { Gv, Ev }, 0 },
2121   { "cmovnsS",          { Gv, Ev }, 0 },
2122   { "cmovpS",           { Gv, Ev }, 0 },
2123   { "cmovnpS",          { Gv, Ev }, 0 },
2124   { "cmovlS",           { Gv, Ev }, 0 },
2125   { "cmovgeS",          { Gv, Ev }, 0 },
2126   { "cmovleS",          { Gv, Ev }, 0 },
2127   { "cmovgS",           { Gv, Ev }, 0 },
2128   /* 50 */
2129   { MOD_TABLE (MOD_0F50) },
2130   { PREFIX_TABLE (PREFIX_0F51) },
2131   { PREFIX_TABLE (PREFIX_0F52) },
2132   { PREFIX_TABLE (PREFIX_0F53) },
2133   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2134   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2135   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2136   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2137   /* 58 */
2138   { PREFIX_TABLE (PREFIX_0F58) },
2139   { PREFIX_TABLE (PREFIX_0F59) },
2140   { PREFIX_TABLE (PREFIX_0F5A) },
2141   { PREFIX_TABLE (PREFIX_0F5B) },
2142   { PREFIX_TABLE (PREFIX_0F5C) },
2143   { PREFIX_TABLE (PREFIX_0F5D) },
2144   { PREFIX_TABLE (PREFIX_0F5E) },
2145   { PREFIX_TABLE (PREFIX_0F5F) },
2146   /* 60 */
2147   { PREFIX_TABLE (PREFIX_0F60) },
2148   { PREFIX_TABLE (PREFIX_0F61) },
2149   { PREFIX_TABLE (PREFIX_0F62) },
2150   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2151   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2152   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2153   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2154   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2155   /* 68 */
2156   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2157   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2158   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2159   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2160   { "punpcklqdq", { XM, EXx }, PREFIX_DATA },
2161   { "punpckhqdq", { XM, EXx }, PREFIX_DATA },
2162   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2163   { PREFIX_TABLE (PREFIX_0F6F) },
2164   /* 70 */
2165   { PREFIX_TABLE (PREFIX_0F70) },
2166   { MOD_TABLE (MOD_0F71) },
2167   { MOD_TABLE (MOD_0F72) },
2168   { MOD_TABLE (MOD_0F73) },
2169   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2170   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2171   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2172   { "emms",             { XX }, PREFIX_OPCODE },
2173   /* 78 */
2174   { PREFIX_TABLE (PREFIX_0F78) },
2175   { PREFIX_TABLE (PREFIX_0F79) },
2176   { Bad_Opcode },
2177   { Bad_Opcode },
2178   { PREFIX_TABLE (PREFIX_0F7C) },
2179   { PREFIX_TABLE (PREFIX_0F7D) },
2180   { PREFIX_TABLE (PREFIX_0F7E) },
2181   { PREFIX_TABLE (PREFIX_0F7F) },
2182   /* 80 */
2183   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2184   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2185   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2186   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2187   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2188   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2189   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2190   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2191   /* 88 */
2192   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2193   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2194   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2195   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2196   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2197   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2198   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2199   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2200   /* 90 */
2201   { "seto",             { Eb }, 0 },
2202   { "setno",            { Eb }, 0 },
2203   { "setb",             { Eb }, 0 },
2204   { "setae",            { Eb }, 0 },
2205   { "sete",             { Eb }, 0 },
2206   { "setne",            { Eb }, 0 },
2207   { "setbe",            { Eb }, 0 },
2208   { "seta",             { Eb }, 0 },
2209   /* 98 */
2210   { "sets",             { Eb }, 0 },
2211   { "setns",            { Eb }, 0 },
2212   { "setp",             { Eb }, 0 },
2213   { "setnp",            { Eb }, 0 },
2214   { "setl",             { Eb }, 0 },
2215   { "setge",            { Eb }, 0 },
2216   { "setle",            { Eb }, 0 },
2217   { "setg",             { Eb }, 0 },
2218   /* a0 */
2219   { "pushP",            { fs }, 0 },
2220   { "popP",             { fs }, 0 },
2221   { "cpuid",            { XX }, 0 },
2222   { "btS",              { Ev, Gv }, 0 },
2223   { "shldS",            { Ev, Gv, Ib }, 0 },
2224   { "shldS",            { Ev, Gv, CL }, 0 },
2225   { REG_TABLE (REG_0FA6) },
2226   { REG_TABLE (REG_0FA7) },
2227   /* a8 */
2228   { "pushP",            { gs }, 0 },
2229   { "popP",             { gs }, 0 },
2230   { "rsm",              { XX }, 0 },
2231   { "btsS",             { Evh1, Gv }, 0 },
2232   { "shrdS",            { Ev, Gv, Ib }, 0 },
2233   { "shrdS",            { Ev, Gv, CL }, 0 },
2234   { REG_TABLE (REG_0FAE) },
2235   { "imulS",            { Gv, Ev }, 0 },
2236   /* b0 */
2237   { "cmpxchgB",         { Ebh1, Gb }, 0 },
2238   { "cmpxchgS",         { Evh1, Gv }, 0 },
2239   { MOD_TABLE (MOD_0FB2) },
2240   { "btrS",             { Evh1, Gv }, 0 },
2241   { MOD_TABLE (MOD_0FB4) },
2242   { MOD_TABLE (MOD_0FB5) },
2243   { "movz{bR|x}",       { Gv, Eb }, 0 },
2244   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2245   /* b8 */
2246   { PREFIX_TABLE (PREFIX_0FB8) },
2247   { "ud1S",             { Gv, Ev }, 0 },
2248   { REG_TABLE (REG_0FBA) },
2249   { "btcS",             { Evh1, Gv }, 0 },
2250   { PREFIX_TABLE (PREFIX_0FBC) },
2251   { PREFIX_TABLE (PREFIX_0FBD) },
2252   { "movs{bR|x}",       { Gv, Eb }, 0 },
2253   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2254   /* c0 */
2255   { "xaddB",            { Ebh1, Gb }, 0 },
2256   { "xaddS",            { Evh1, Gv }, 0 },
2257   { PREFIX_TABLE (PREFIX_0FC2) },
2258   { MOD_TABLE (MOD_0FC3) },
2259   { "pinsrw",           { MX, Edw, Ib }, PREFIX_OPCODE },
2260   { "pextrw",           { Gd, MS, Ib }, PREFIX_OPCODE },
2261   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
2262   { REG_TABLE (REG_0FC7) },
2263   /* c8 */
2264   { "bswap",            { RMeAX }, 0 },
2265   { "bswap",            { RMeCX }, 0 },
2266   { "bswap",            { RMeDX }, 0 },
2267   { "bswap",            { RMeBX }, 0 },
2268   { "bswap",            { RMeSP }, 0 },
2269   { "bswap",            { RMeBP }, 0 },
2270   { "bswap",            { RMeSI }, 0 },
2271   { "bswap",            { RMeDI }, 0 },
2272   /* d0 */
2273   { PREFIX_TABLE (PREFIX_0FD0) },
2274   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
2275   { "psrld",            { MX, EM }, PREFIX_OPCODE },
2276   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
2277   { "paddq",            { MX, EM }, PREFIX_OPCODE },
2278   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
2279   { PREFIX_TABLE (PREFIX_0FD6) },
2280   { MOD_TABLE (MOD_0FD7) },
2281   /* d8 */
2282   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
2283   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
2284   { "pminub",           { MX, EM }, PREFIX_OPCODE },
2285   { "pand",             { MX, EM }, PREFIX_OPCODE },
2286   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
2287   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
2288   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
2289   { "pandn",            { MX, EM }, PREFIX_OPCODE },
2290   /* e0 */
2291   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
2292   { "psraw",            { MX, EM }, PREFIX_OPCODE },
2293   { "psrad",            { MX, EM }, PREFIX_OPCODE },
2294   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
2295   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
2296   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
2297   { PREFIX_TABLE (PREFIX_0FE6) },
2298   { PREFIX_TABLE (PREFIX_0FE7) },
2299   /* e8 */
2300   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
2301   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
2302   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
2303   { "por",              { MX, EM }, PREFIX_OPCODE },
2304   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
2305   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
2306   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
2307   { "pxor",             { MX, EM }, PREFIX_OPCODE },
2308   /* f0 */
2309   { PREFIX_TABLE (PREFIX_0FF0) },
2310   { "psllw",            { MX, EM }, PREFIX_OPCODE },
2311   { "pslld",            { MX, EM }, PREFIX_OPCODE },
2312   { "psllq",            { MX, EM }, PREFIX_OPCODE },
2313   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
2314   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
2315   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
2316   { PREFIX_TABLE (PREFIX_0FF7) },
2317   /* f8 */
2318   { "psubb",            { MX, EM }, PREFIX_OPCODE },
2319   { "psubw",            { MX, EM }, PREFIX_OPCODE },
2320   { "psubd",            { MX, EM }, PREFIX_OPCODE },
2321   { "psubq",            { MX, EM }, PREFIX_OPCODE },
2322   { "paddb",            { MX, EM }, PREFIX_OPCODE },
2323   { "paddw",            { MX, EM }, PREFIX_OPCODE },
2324   { "paddd",            { MX, EM }, PREFIX_OPCODE },
2325   { "ud0S",             { Gv, Ev }, 0 },
2326 };
2327
2328 static const unsigned char onebyte_has_modrm[256] = {
2329   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2330   /*       -------------------------------        */
2331   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2332   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2333   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2334   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2335   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2336   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2337   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2338   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2339   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2340   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2341   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2342   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2343   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2344   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2345   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2346   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2347   /*       -------------------------------        */
2348   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2349 };
2350
2351 static const unsigned char twobyte_has_modrm[256] = {
2352   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2353   /*       -------------------------------        */
2354   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2355   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2356   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2357   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2358   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2359   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2360   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2361   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2362   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2363   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2364   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2365   /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2366   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2367   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2368   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2369   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1  /* ff */
2370   /*       -------------------------------        */
2371   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2372 };
2373
2374 static char obuf[100];
2375 static char *obufp;
2376 static char *mnemonicendp;
2377 static char scratchbuf[100];
2378 static unsigned char *start_codep;
2379 static unsigned char *insn_codep;
2380 static unsigned char *codep;
2381 static unsigned char *end_codep;
2382 static int last_lock_prefix;
2383 static int last_repz_prefix;
2384 static int last_repnz_prefix;
2385 static int last_data_prefix;
2386 static int last_addr_prefix;
2387 static int last_rex_prefix;
2388 static int last_seg_prefix;
2389 static int fwait_prefix;
2390 /* The active segment register prefix.  */
2391 static int active_seg_prefix;
2392 #define MAX_CODE_LENGTH 15
2393 /* We can up to 14 prefixes since the maximum instruction length is
2394    15bytes.  */
2395 static int all_prefixes[MAX_CODE_LENGTH - 1];
2396 static disassemble_info *the_info;
2397 static struct
2398   {
2399     int mod;
2400     int reg;
2401     int rm;
2402   }
2403 modrm;
2404 static unsigned char need_modrm;
2405 static struct
2406   {
2407     int scale;
2408     int index;
2409     int base;
2410   }
2411 sib;
2412 static struct
2413   {
2414     int register_specifier;
2415     int length;
2416     int prefix;
2417     int w;
2418     int evex;
2419     int r;
2420     int v;
2421     int mask_register_specifier;
2422     int zeroing;
2423     int ll;
2424     int b;
2425   }
2426 vex;
2427 static unsigned char need_vex;
2428
2429 struct op
2430   {
2431     const char *name;
2432     unsigned int len;
2433   };
2434
2435 /* If we are accessing mod/rm/reg without need_modrm set, then the
2436    values are stale.  Hitting this abort likely indicates that you
2437    need to update onebyte_has_modrm or twobyte_has_modrm.  */
2438 #define MODRM_CHECK  if (!need_modrm) abort ()
2439
2440 static const char **names64;
2441 static const char **names32;
2442 static const char **names16;
2443 static const char **names8;
2444 static const char **names8rex;
2445 static const char **names_seg;
2446 static const char *index64;
2447 static const char *index32;
2448 static const char **index16;
2449 static const char **names_bnd;
2450
2451 static const char *intel_names64[] = {
2452   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2453   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2454 };
2455 static const char *intel_names32[] = {
2456   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2457   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2458 };
2459 static const char *intel_names16[] = {
2460   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2461   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2462 };
2463 static const char *intel_names8[] = {
2464   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2465 };
2466 static const char *intel_names8rex[] = {
2467   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2468   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2469 };
2470 static const char *intel_names_seg[] = {
2471   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2472 };
2473 static const char *intel_index64 = "riz";
2474 static const char *intel_index32 = "eiz";
2475 static const char *intel_index16[] = {
2476   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2477 };
2478
2479 static const char *att_names64[] = {
2480   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2481   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2482 };
2483 static const char *att_names32[] = {
2484   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2485   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2486 };
2487 static const char *att_names16[] = {
2488   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2489   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2490 };
2491 static const char *att_names8[] = {
2492   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2493 };
2494 static const char *att_names8rex[] = {
2495   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2496   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2497 };
2498 static const char *att_names_seg[] = {
2499   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2500 };
2501 static const char *att_index64 = "%riz";
2502 static const char *att_index32 = "%eiz";
2503 static const char *att_index16[] = {
2504   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2505 };
2506
2507 static const char **names_mm;
2508 static const char *intel_names_mm[] = {
2509   "mm0", "mm1", "mm2", "mm3",
2510   "mm4", "mm5", "mm6", "mm7"
2511 };
2512 static const char *att_names_mm[] = {
2513   "%mm0", "%mm1", "%mm2", "%mm3",
2514   "%mm4", "%mm5", "%mm6", "%mm7"
2515 };
2516
2517 static const char *intel_names_bnd[] = {
2518   "bnd0", "bnd1", "bnd2", "bnd3"
2519 };
2520
2521 static const char *att_names_bnd[] = {
2522   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
2523 };
2524
2525 static const char **names_xmm;
2526 static const char *intel_names_xmm[] = {
2527   "xmm0", "xmm1", "xmm2", "xmm3",
2528   "xmm4", "xmm5", "xmm6", "xmm7",
2529   "xmm8", "xmm9", "xmm10", "xmm11",
2530   "xmm12", "xmm13", "xmm14", "xmm15",
2531   "xmm16", "xmm17", "xmm18", "xmm19",
2532   "xmm20", "xmm21", "xmm22", "xmm23",
2533   "xmm24", "xmm25", "xmm26", "xmm27",
2534   "xmm28", "xmm29", "xmm30", "xmm31"
2535 };
2536 static const char *att_names_xmm[] = {
2537   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2538   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2539   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2540   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
2541   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
2542   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
2543   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
2544   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
2545 };
2546
2547 static const char **names_ymm;
2548 static const char *intel_names_ymm[] = {
2549   "ymm0", "ymm1", "ymm2", "ymm3",
2550   "ymm4", "ymm5", "ymm6", "ymm7",
2551   "ymm8", "ymm9", "ymm10", "ymm11",
2552   "ymm12", "ymm13", "ymm14", "ymm15",
2553   "ymm16", "ymm17", "ymm18", "ymm19",
2554   "ymm20", "ymm21", "ymm22", "ymm23",
2555   "ymm24", "ymm25", "ymm26", "ymm27",
2556   "ymm28", "ymm29", "ymm30", "ymm31"
2557 };
2558 static const char *att_names_ymm[] = {
2559   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2560   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2561   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2562   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
2563   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
2564   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
2565   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
2566   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
2567 };
2568
2569 static const char **names_zmm;
2570 static const char *intel_names_zmm[] = {
2571   "zmm0", "zmm1", "zmm2", "zmm3",
2572   "zmm4", "zmm5", "zmm6", "zmm7",
2573   "zmm8", "zmm9", "zmm10", "zmm11",
2574   "zmm12", "zmm13", "zmm14", "zmm15",
2575   "zmm16", "zmm17", "zmm18", "zmm19",
2576   "zmm20", "zmm21", "zmm22", "zmm23",
2577   "zmm24", "zmm25", "zmm26", "zmm27",
2578   "zmm28", "zmm29", "zmm30", "zmm31"
2579 };
2580 static const char *att_names_zmm[] = {
2581   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
2582   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
2583   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
2584   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
2585   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
2586   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
2587   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
2588   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
2589 };
2590
2591 static const char **names_tmm;
2592 static const char *intel_names_tmm[] = {
2593   "tmm0", "tmm1", "tmm2", "tmm3",
2594   "tmm4", "tmm5", "tmm6", "tmm7"
2595 };
2596 static const char *att_names_tmm[] = {
2597   "%tmm0", "%tmm1", "%tmm2", "%tmm3",
2598   "%tmm4", "%tmm5", "%tmm6", "%tmm7"
2599 };
2600
2601 static const char **names_mask;
2602 static const char *intel_names_mask[] = {
2603   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
2604 };
2605 static const char *att_names_mask[] = {
2606   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
2607 };
2608
2609 static const char *const names_rounding[] =
2610 {
2611   "{rn-",
2612   "{rd-",
2613   "{ru-",
2614   "{rz-"
2615 };
2616
2617 static const struct dis386 reg_table[][8] = {
2618   /* REG_80 */
2619   {
2620     { "addA",   { Ebh1, Ib }, 0 },
2621     { "orA",    { Ebh1, Ib }, 0 },
2622     { "adcA",   { Ebh1, Ib }, 0 },
2623     { "sbbA",   { Ebh1, Ib }, 0 },
2624     { "andA",   { Ebh1, Ib }, 0 },
2625     { "subA",   { Ebh1, Ib }, 0 },
2626     { "xorA",   { Ebh1, Ib }, 0 },
2627     { "cmpA",   { Eb, Ib }, 0 },
2628   },
2629   /* REG_81 */
2630   {
2631     { "addQ",   { Evh1, Iv }, 0 },
2632     { "orQ",    { Evh1, Iv }, 0 },
2633     { "adcQ",   { Evh1, Iv }, 0 },
2634     { "sbbQ",   { Evh1, Iv }, 0 },
2635     { "andQ",   { Evh1, Iv }, 0 },
2636     { "subQ",   { Evh1, Iv }, 0 },
2637     { "xorQ",   { Evh1, Iv }, 0 },
2638     { "cmpQ",   { Ev, Iv }, 0 },
2639   },
2640   /* REG_83 */
2641   {
2642     { "addQ",   { Evh1, sIb }, 0 },
2643     { "orQ",    { Evh1, sIb }, 0 },
2644     { "adcQ",   { Evh1, sIb }, 0 },
2645     { "sbbQ",   { Evh1, sIb }, 0 },
2646     { "andQ",   { Evh1, sIb }, 0 },
2647     { "subQ",   { Evh1, sIb }, 0 },
2648     { "xorQ",   { Evh1, sIb }, 0 },
2649     { "cmpQ",   { Ev, sIb }, 0 },
2650   },
2651   /* REG_8F */
2652   {
2653     { "pop{P|}", { stackEv }, 0 },
2654     { XOP_8F_TABLE (XOP_09) },
2655     { Bad_Opcode },
2656     { Bad_Opcode },
2657     { Bad_Opcode },
2658     { XOP_8F_TABLE (XOP_09) },
2659   },
2660   /* REG_C0 */
2661   {
2662     { "rolA",   { Eb, Ib }, 0 },
2663     { "rorA",   { Eb, Ib }, 0 },
2664     { "rclA",   { Eb, Ib }, 0 },
2665     { "rcrA",   { Eb, Ib }, 0 },
2666     { "shlA",   { Eb, Ib }, 0 },
2667     { "shrA",   { Eb, Ib }, 0 },
2668     { "shlA",   { Eb, Ib }, 0 },
2669     { "sarA",   { Eb, Ib }, 0 },
2670   },
2671   /* REG_C1 */
2672   {
2673     { "rolQ",   { Ev, Ib }, 0 },
2674     { "rorQ",   { Ev, Ib }, 0 },
2675     { "rclQ",   { Ev, Ib }, 0 },
2676     { "rcrQ",   { Ev, Ib }, 0 },
2677     { "shlQ",   { Ev, Ib }, 0 },
2678     { "shrQ",   { Ev, Ib }, 0 },
2679     { "shlQ",   { Ev, Ib }, 0 },
2680     { "sarQ",   { Ev, Ib }, 0 },
2681   },
2682   /* REG_C6 */
2683   {
2684     { "movA",   { Ebh3, Ib }, 0 },
2685     { Bad_Opcode },
2686     { Bad_Opcode },
2687     { Bad_Opcode },
2688     { Bad_Opcode },
2689     { Bad_Opcode },
2690     { Bad_Opcode },
2691     { MOD_TABLE (MOD_C6_REG_7) },
2692   },
2693   /* REG_C7 */
2694   {
2695     { "movQ",   { Evh3, Iv }, 0 },
2696     { Bad_Opcode },
2697     { Bad_Opcode },
2698     { Bad_Opcode },
2699     { Bad_Opcode },
2700     { Bad_Opcode },
2701     { Bad_Opcode },
2702     { MOD_TABLE (MOD_C7_REG_7) },
2703   },
2704   /* REG_D0 */
2705   {
2706     { "rolA",   { Eb, I1 }, 0 },
2707     { "rorA",   { Eb, I1 }, 0 },
2708     { "rclA",   { Eb, I1 }, 0 },
2709     { "rcrA",   { Eb, I1 }, 0 },
2710     { "shlA",   { Eb, I1 }, 0 },
2711     { "shrA",   { Eb, I1 }, 0 },
2712     { "shlA",   { Eb, I1 }, 0 },
2713     { "sarA",   { Eb, I1 }, 0 },
2714   },
2715   /* REG_D1 */
2716   {
2717     { "rolQ",   { Ev, I1 }, 0 },
2718     { "rorQ",   { Ev, I1 }, 0 },
2719     { "rclQ",   { Ev, I1 }, 0 },
2720     { "rcrQ",   { Ev, I1 }, 0 },
2721     { "shlQ",   { Ev, I1 }, 0 },
2722     { "shrQ",   { Ev, I1 }, 0 },
2723     { "shlQ",   { Ev, I1 }, 0 },
2724     { "sarQ",   { Ev, I1 }, 0 },
2725   },
2726   /* REG_D2 */
2727   {
2728     { "rolA",   { Eb, CL }, 0 },
2729     { "rorA",   { Eb, CL }, 0 },
2730     { "rclA",   { Eb, CL }, 0 },
2731     { "rcrA",   { Eb, CL }, 0 },
2732     { "shlA",   { Eb, CL }, 0 },
2733     { "shrA",   { Eb, CL }, 0 },
2734     { "shlA",   { Eb, CL }, 0 },
2735     { "sarA",   { Eb, CL }, 0 },
2736   },
2737   /* REG_D3 */
2738   {
2739     { "rolQ",   { Ev, CL }, 0 },
2740     { "rorQ",   { Ev, CL }, 0 },
2741     { "rclQ",   { Ev, CL }, 0 },
2742     { "rcrQ",   { Ev, CL }, 0 },
2743     { "shlQ",   { Ev, CL }, 0 },
2744     { "shrQ",   { Ev, CL }, 0 },
2745     { "shlQ",   { Ev, CL }, 0 },
2746     { "sarQ",   { Ev, CL }, 0 },
2747   },
2748   /* REG_F6 */
2749   {
2750     { "testA",  { Eb, Ib }, 0 },
2751     { "testA",  { Eb, Ib }, 0 },
2752     { "notA",   { Ebh1 }, 0 },
2753     { "negA",   { Ebh1 }, 0 },
2754     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
2755     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
2756     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
2757     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
2758   },
2759   /* REG_F7 */
2760   {
2761     { "testQ",  { Ev, Iv }, 0 },
2762     { "testQ",  { Ev, Iv }, 0 },
2763     { "notQ",   { Evh1 }, 0 },
2764     { "negQ",   { Evh1 }, 0 },
2765     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
2766     { "imulQ",  { Ev }, 0 },
2767     { "divQ",   { Ev }, 0 },
2768     { "idivQ",  { Ev }, 0 },
2769   },
2770   /* REG_FE */
2771   {
2772     { "incA",   { Ebh1 }, 0 },
2773     { "decA",   { Ebh1 }, 0 },
2774   },
2775   /* REG_FF */
2776   {
2777     { "incQ",   { Evh1 }, 0 },
2778     { "decQ",   { Evh1 }, 0 },
2779     { "call{@|}", { NOTRACK, indirEv, BND }, 0 },
2780     { MOD_TABLE (MOD_FF_REG_3) },
2781     { "jmp{@|}", { NOTRACK, indirEv, BND }, 0 },
2782     { MOD_TABLE (MOD_FF_REG_5) },
2783     { "push{P|}", { stackEv }, 0 },
2784     { Bad_Opcode },
2785   },
2786   /* REG_0F00 */
2787   {
2788     { "sldtD",  { Sv }, 0 },
2789     { "strD",   { Sv }, 0 },
2790     { "lldt",   { Ew }, 0 },
2791     { "ltr",    { Ew }, 0 },
2792     { "verr",   { Ew }, 0 },
2793     { "verw",   { Ew }, 0 },
2794     { Bad_Opcode },
2795     { Bad_Opcode },
2796   },
2797   /* REG_0F01 */
2798   {
2799     { MOD_TABLE (MOD_0F01_REG_0) },
2800     { MOD_TABLE (MOD_0F01_REG_1) },
2801     { MOD_TABLE (MOD_0F01_REG_2) },
2802     { MOD_TABLE (MOD_0F01_REG_3) },
2803     { "smswD",  { Sv }, 0 },
2804     { MOD_TABLE (MOD_0F01_REG_5) },
2805     { "lmsw",   { Ew }, 0 },
2806     { MOD_TABLE (MOD_0F01_REG_7) },
2807   },
2808   /* REG_0F0D */
2809   {
2810     { "prefetch",       { Mb }, 0 },
2811     { "prefetchw",      { Mb }, 0 },
2812     { "prefetchwt1",    { Mb }, 0 },
2813     { "prefetch",       { Mb }, 0 },
2814     { "prefetch",       { Mb }, 0 },
2815     { "prefetch",       { Mb }, 0 },
2816     { "prefetch",       { Mb }, 0 },
2817     { "prefetch",       { Mb }, 0 },
2818   },
2819   /* REG_0F18 */
2820   {
2821     { MOD_TABLE (MOD_0F18_REG_0) },
2822     { MOD_TABLE (MOD_0F18_REG_1) },
2823     { MOD_TABLE (MOD_0F18_REG_2) },
2824     { MOD_TABLE (MOD_0F18_REG_3) },
2825     { "nopQ",           { Ev }, 0 },
2826     { "nopQ",           { Ev }, 0 },
2827     { "nopQ",           { Ev }, 0 },
2828     { "nopQ",           { Ev }, 0 },
2829   },
2830   /* REG_0F1C_P_0_MOD_0 */
2831   {
2832     { "cldemote",       { Mb }, 0 },
2833     { "nopQ",           { Ev }, 0 },
2834     { "nopQ",           { Ev }, 0 },
2835     { "nopQ",           { Ev }, 0 },
2836     { "nopQ",           { Ev }, 0 },
2837     { "nopQ",           { Ev }, 0 },
2838     { "nopQ",           { Ev }, 0 },
2839     { "nopQ",           { Ev }, 0 },
2840   },
2841   /* REG_0F1E_P_1_MOD_3 */
2842   {
2843     { "nopQ",           { Ev }, PREFIX_IGNORED },
2844     { "rdsspK",         { Edq }, 0 },
2845     { "nopQ",           { Ev }, PREFIX_IGNORED },
2846     { "nopQ",           { Ev }, PREFIX_IGNORED },
2847     { "nopQ",           { Ev }, PREFIX_IGNORED },
2848     { "nopQ",           { Ev }, PREFIX_IGNORED },
2849     { "nopQ",           { Ev }, PREFIX_IGNORED },
2850     { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) },
2851   },
2852   /* REG_0F38D8_PREFIX_1 */
2853   {
2854     { "aesencwide128kl",        { M }, 0 },
2855     { "aesdecwide128kl",        { M }, 0 },
2856     { "aesencwide256kl",        { M }, 0 },
2857     { "aesdecwide256kl",        { M }, 0 },
2858   },
2859   /* REG_0F3A0F_PREFIX_1_MOD_3 */
2860   {
2861     { RM_TABLE (RM_0F3A0F_P_1_MOD_3_REG_0) },
2862   },
2863   /* REG_0F71_MOD_0 */
2864   {
2865     { Bad_Opcode },
2866     { Bad_Opcode },
2867     { "psrlw",          { MS, Ib }, PREFIX_OPCODE },
2868     { Bad_Opcode },
2869     { "psraw",          { MS, Ib }, PREFIX_OPCODE },
2870     { Bad_Opcode },
2871     { "psllw",          { MS, Ib }, PREFIX_OPCODE },
2872   },
2873   /* REG_0F72_MOD_0 */
2874   {
2875     { Bad_Opcode },
2876     { Bad_Opcode },
2877     { "psrld",          { MS, Ib }, PREFIX_OPCODE },
2878     { Bad_Opcode },
2879     { "psrad",          { MS, Ib }, PREFIX_OPCODE },
2880     { Bad_Opcode },
2881     { "pslld",          { MS, Ib }, PREFIX_OPCODE },
2882   },
2883   /* REG_0F73_MOD_0 */
2884   {
2885     { Bad_Opcode },
2886     { Bad_Opcode },
2887     { "psrlq",          { MS, Ib }, PREFIX_OPCODE },
2888     { "psrldq",         { XS, Ib }, PREFIX_DATA },
2889     { Bad_Opcode },
2890     { Bad_Opcode },
2891     { "psllq",          { MS, Ib }, PREFIX_OPCODE },
2892     { "pslldq",         { XS, Ib }, PREFIX_DATA },
2893   },
2894   /* REG_0FA6 */
2895   {
2896     { "montmul",        { { OP_0f07, 0 } }, 0 },
2897     { "xsha1",          { { OP_0f07, 0 } }, 0 },
2898     { "xsha256",        { { OP_0f07, 0 } }, 0 },
2899   },
2900   /* REG_0FA7 */
2901   {
2902     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
2903     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
2904     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
2905     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
2906     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
2907     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
2908   },
2909   /* REG_0FAE */
2910   {
2911     { MOD_TABLE (MOD_0FAE_REG_0) },
2912     { MOD_TABLE (MOD_0FAE_REG_1) },
2913     { MOD_TABLE (MOD_0FAE_REG_2) },
2914     { MOD_TABLE (MOD_0FAE_REG_3) },
2915     { MOD_TABLE (MOD_0FAE_REG_4) },
2916     { MOD_TABLE (MOD_0FAE_REG_5) },
2917     { MOD_TABLE (MOD_0FAE_REG_6) },
2918     { MOD_TABLE (MOD_0FAE_REG_7) },
2919   },
2920   /* REG_0FBA */
2921   {
2922     { Bad_Opcode },
2923     { Bad_Opcode },
2924     { Bad_Opcode },
2925     { Bad_Opcode },
2926     { "btQ",    { Ev, Ib }, 0 },
2927     { "btsQ",   { Evh1, Ib }, 0 },
2928     { "btrQ",   { Evh1, Ib }, 0 },
2929     { "btcQ",   { Evh1, Ib }, 0 },
2930   },
2931   /* REG_0FC7 */
2932   {
2933     { Bad_Opcode },
2934     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
2935     { Bad_Opcode },
2936     { MOD_TABLE (MOD_0FC7_REG_3) },
2937     { MOD_TABLE (MOD_0FC7_REG_4) },
2938     { MOD_TABLE (MOD_0FC7_REG_5) },
2939     { MOD_TABLE (MOD_0FC7_REG_6) },
2940     { MOD_TABLE (MOD_0FC7_REG_7) },
2941   },
2942   /* REG_VEX_0F71_M_0 */
2943   {
2944     { Bad_Opcode },
2945     { Bad_Opcode },
2946     { "vpsrlw",         { Vex, XS, Ib }, PREFIX_DATA },
2947     { Bad_Opcode },
2948     { "vpsraw",         { Vex, XS, Ib }, PREFIX_DATA },
2949     { Bad_Opcode },
2950     { "vpsllw",         { Vex, XS, Ib }, PREFIX_DATA },
2951   },
2952   /* REG_VEX_0F72_M_0 */
2953   {
2954     { Bad_Opcode },
2955     { Bad_Opcode },
2956     { "vpsrld",         { Vex, XS, Ib }, PREFIX_DATA },
2957     { Bad_Opcode },
2958     { "vpsrad",         { Vex, XS, Ib }, PREFIX_DATA },
2959     { Bad_Opcode },
2960     { "vpslld",         { Vex, XS, Ib }, PREFIX_DATA },
2961   },
2962   /* REG_VEX_0F73_M_0 */
2963   {
2964     { Bad_Opcode },
2965     { Bad_Opcode },
2966     { "vpsrlq",         { Vex, XS, Ib }, PREFIX_DATA },
2967     { "vpsrldq",        { Vex, XS, Ib }, PREFIX_DATA },
2968     { Bad_Opcode },
2969     { Bad_Opcode },
2970     { "vpsllq",         { Vex, XS, Ib }, PREFIX_DATA },
2971     { "vpslldq",        { Vex, XS, Ib }, PREFIX_DATA },
2972   },
2973   /* REG_VEX_0FAE */
2974   {
2975     { Bad_Opcode },
2976     { Bad_Opcode },
2977     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
2978     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
2979   },
2980   /* REG_VEX_0F3849_X86_64_P_0_W_0_M_1 */
2981   {
2982     { RM_TABLE (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0) },
2983   },
2984   /* REG_VEX_0F38F3_L_0 */
2985   {
2986     { Bad_Opcode },
2987     { "blsrS",          { VexGdq, Edq }, PREFIX_OPCODE },
2988     { "blsmskS",        { VexGdq, Edq }, PREFIX_OPCODE },
2989     { "blsiS",          { VexGdq, Edq }, PREFIX_OPCODE },
2990   },
2991   /* REG_XOP_09_01_L_0 */
2992   {
2993     { Bad_Opcode },
2994     { "blcfill",        { VexGdq, Edq }, 0 },
2995     { "blsfill",        { VexGdq, Edq }, 0 },
2996     { "blcs",   { VexGdq, Edq }, 0 },
2997     { "tzmsk",  { VexGdq, Edq }, 0 },
2998     { "blcic",  { VexGdq, Edq }, 0 },
2999     { "blsic",  { VexGdq, Edq }, 0 },
3000     { "t1mskc", { VexGdq, Edq }, 0 },
3001   },
3002   /* REG_XOP_09_02_L_0 */
3003   {
3004     { Bad_Opcode },
3005     { "blcmsk", { VexGdq, Edq }, 0 },
3006     { Bad_Opcode },
3007     { Bad_Opcode },
3008     { Bad_Opcode },
3009     { Bad_Opcode },
3010     { "blci",   { VexGdq, Edq }, 0 },
3011   },
3012   /* REG_XOP_09_12_M_1_L_0 */
3013   {
3014     { "llwpcb", { Edq }, 0 },
3015     { "slwpcb", { Edq }, 0 },
3016   },
3017   /* REG_XOP_0A_12_L_0 */
3018   {
3019     { "lwpins", { VexGdq, Ed, Id }, 0 },
3020     { "lwpval", { VexGdq, Ed, Id }, 0 },
3021   },
3022
3023 #include "i386-dis-evex-reg.h"
3024 };
3025
3026 static const struct dis386 prefix_table[][4] = {
3027   /* PREFIX_90 */
3028   {
3029     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3030     { "pause", { XX }, 0 },
3031     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3032     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3033   },
3034
3035   /* PREFIX_0F01_REG_1_RM_4 */
3036   {
3037     { Bad_Opcode },
3038     { Bad_Opcode },
3039     { "tdcall",         { Skip_MODRM }, 0 },
3040     { Bad_Opcode },
3041   },
3042
3043   /* PREFIX_0F01_REG_1_RM_5 */
3044   {
3045     { Bad_Opcode },
3046     { Bad_Opcode },
3047     { X86_64_TABLE (X86_64_0F01_REG_1_RM_5_PREFIX_2) },
3048     { Bad_Opcode },
3049   },
3050
3051   /* PREFIX_0F01_REG_1_RM_6 */
3052   {
3053     { Bad_Opcode },
3054     { Bad_Opcode },
3055     { X86_64_TABLE (X86_64_0F01_REG_1_RM_6_PREFIX_2) },
3056     { Bad_Opcode },
3057   },
3058
3059   /* PREFIX_0F01_REG_1_RM_7 */
3060   {
3061     { "encls",          { Skip_MODRM }, 0 },
3062     { Bad_Opcode },
3063     { X86_64_TABLE (X86_64_0F01_REG_1_RM_7_PREFIX_2) },
3064     { Bad_Opcode },
3065   },
3066
3067   /* PREFIX_0F01_REG_3_RM_1 */
3068   {
3069     { "vmmcall",        { Skip_MODRM }, 0 },
3070     { "vmgexit",        { Skip_MODRM }, 0 },
3071     { Bad_Opcode },
3072     { "vmgexit",        { Skip_MODRM }, 0 },
3073   },
3074
3075   /* PREFIX_0F01_REG_5_MOD_0 */
3076   {
3077     { Bad_Opcode },
3078     { "rstorssp",       { Mq }, PREFIX_OPCODE },
3079   },
3080
3081   /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3082   {
3083     { "serialize",      { Skip_MODRM }, PREFIX_OPCODE },
3084     { "setssbsy",       { Skip_MODRM }, PREFIX_OPCODE },
3085     { Bad_Opcode },
3086     { "xsusldtrk",      { Skip_MODRM }, PREFIX_OPCODE },
3087   },
3088
3089   /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
3090   {
3091     { Bad_Opcode },
3092     { Bad_Opcode },
3093     { Bad_Opcode },
3094     { "xresldtrk",     { Skip_MODRM }, PREFIX_OPCODE },
3095   },
3096
3097   /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3098   {
3099     { Bad_Opcode },
3100     { "saveprevssp",    { Skip_MODRM }, PREFIX_OPCODE },
3101   },
3102
3103   /* PREFIX_0F01_REG_5_MOD_3_RM_4 */
3104   {
3105     { Bad_Opcode },
3106     { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1) },
3107   },
3108
3109   /* PREFIX_0F01_REG_5_MOD_3_RM_5 */
3110   {
3111     { Bad_Opcode },
3112     { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1) },
3113   },
3114
3115   /* PREFIX_0F01_REG_5_MOD_3_RM_6 */
3116   {
3117     { "rdpkru", { Skip_MODRM }, 0 },
3118     { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1) },
3119   },
3120
3121   /* PREFIX_0F01_REG_5_MOD_3_RM_7 */
3122   {
3123     { "wrpkru", { Skip_MODRM }, 0 },
3124     { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1) },
3125   },
3126
3127   /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3128   {
3129     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
3130     { "mcommit",        { Skip_MODRM }, 0 },
3131   },
3132
3133   /* PREFIX_0F01_REG_7_MOD_3_RM_6 */
3134   {
3135     { "invlpgb",        { Skip_MODRM }, 0 },
3136     { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1) },
3137     { Bad_Opcode },
3138     { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3) },
3139   },
3140
3141   /* PREFIX_0F01_REG_7_MOD_3_RM_7 */
3142   {
3143     { "tlbsync",        { Skip_MODRM }, 0 },
3144     { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1) },
3145     { Bad_Opcode },
3146     { "pvalidate",      { Skip_MODRM }, 0 },
3147   },
3148
3149   /* PREFIX_0F09 */
3150   {
3151     { "wbinvd",   { XX }, 0 },
3152     { "wbnoinvd", { XX }, 0 },
3153   },
3154
3155   /* PREFIX_0F10 */
3156   {
3157     { "movups", { XM, EXx }, PREFIX_OPCODE },
3158     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3159     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3160     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3161   },
3162
3163   /* PREFIX_0F11 */
3164   {
3165     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3166     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3167     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3168     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3169   },
3170
3171   /* PREFIX_0F12 */
3172   {
3173     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3174     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3175     { MOD_TABLE (MOD_0F12_PREFIX_2) },
3176     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3177   },
3178
3179   /* PREFIX_0F16 */
3180   {
3181     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3182     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3183     { MOD_TABLE (MOD_0F16_PREFIX_2) },
3184   },
3185
3186   /* PREFIX_0F1A */
3187   {
3188     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3189     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3190     { "bndmov", { Gbnd, Ebnd }, 0 },
3191     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3192   },
3193
3194   /* PREFIX_0F1B */
3195   {
3196     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3197     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3198     { "bndmov", { EbndS, Gbnd }, 0 },
3199     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3200   },
3201
3202   /* PREFIX_0F1C */
3203   {
3204     { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3205     { "nopQ",   { Ev }, PREFIX_IGNORED },
3206     { "nopQ",   { Ev }, 0 },
3207     { "nopQ",   { Ev }, PREFIX_IGNORED },
3208   },
3209
3210   /* PREFIX_0F1E */
3211   {
3212     { "nopQ",   { Ev }, 0 },
3213     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3214     { "nopQ",   { Ev }, 0 },
3215     { NULL,     { XX }, PREFIX_IGNORED },
3216   },
3217
3218   /* PREFIX_0F2A */
3219   {
3220     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3221     { "cvtsi2ss{%LQ|}", { XM, Edq }, PREFIX_OPCODE },
3222     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3223     { "cvtsi2sd{%LQ|}", { XM, Edq }, 0 },
3224   },
3225
3226   /* PREFIX_0F2B */
3227   {
3228     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3229     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3230     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3231     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3232   },
3233
3234   /* PREFIX_0F2C */
3235   {
3236     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3237     { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
3238     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3239     { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3240   },
3241
3242   /* PREFIX_0F2D */
3243   {
3244     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3245     { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
3246     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3247     { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3248   },
3249
3250   /* PREFIX_0F2E */
3251   {
3252     { "ucomiss",{ XM, EXd }, 0 },
3253     { Bad_Opcode },
3254     { "ucomisd",{ XM, EXq }, 0 },
3255   },
3256
3257   /* PREFIX_0F2F */
3258   {
3259     { "comiss", { XM, EXd }, 0 },
3260     { Bad_Opcode },
3261     { "comisd", { XM, EXq }, 0 },
3262   },
3263
3264   /* PREFIX_0F51 */
3265   {
3266     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3267     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3268     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3269     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3270   },
3271
3272   /* PREFIX_0F52 */
3273   {
3274     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3275     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3276   },
3277
3278   /* PREFIX_0F53 */
3279   {
3280     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3281     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3282   },
3283
3284   /* PREFIX_0F58 */
3285   {
3286     { "addps", { XM, EXx }, PREFIX_OPCODE },
3287     { "addss", { XM, EXd }, PREFIX_OPCODE },
3288     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3289     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3290   },
3291
3292   /* PREFIX_0F59 */
3293   {
3294     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3295     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3296     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3297     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3298   },
3299
3300   /* PREFIX_0F5A */
3301   {
3302     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3303     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3304     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3305     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3306   },
3307
3308   /* PREFIX_0F5B */
3309   {
3310     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3311     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3312     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3313   },
3314
3315   /* PREFIX_0F5C */
3316   {
3317     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3318     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3319     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3320     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3321   },
3322
3323   /* PREFIX_0F5D */
3324   {
3325     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3326     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3327     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3328     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3329   },
3330
3331   /* PREFIX_0F5E */
3332   {
3333     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3334     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3335     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3336     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3337   },
3338
3339   /* PREFIX_0F5F */
3340   {
3341     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3342     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3343     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3344     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3345   },
3346
3347   /* PREFIX_0F60 */
3348   {
3349     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3350     { Bad_Opcode },
3351     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3352   },
3353
3354   /* PREFIX_0F61 */
3355   {
3356     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3357     { Bad_Opcode },
3358     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3359   },
3360
3361   /* PREFIX_0F62 */
3362   {
3363     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3364     { Bad_Opcode },
3365     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3366   },
3367
3368   /* PREFIX_0F6F */
3369   {
3370     { "movq",   { MX, EM }, PREFIX_OPCODE },
3371     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3372     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3373   },
3374
3375   /* PREFIX_0F70 */
3376   {
3377     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3378     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3379     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3380     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3381   },
3382
3383   /* PREFIX_0F78 */
3384   {
3385     {"vmread",  { Em, Gm }, 0 },
3386     { Bad_Opcode },
3387     {"extrq",   { XS, Ib, Ib }, 0 },
3388     {"insertq", { XM, XS, Ib, Ib }, 0 },
3389   },
3390
3391   /* PREFIX_0F79 */
3392   {
3393     {"vmwrite", { Gm, Em }, 0 },
3394     { Bad_Opcode },
3395     {"extrq",   { XM, XS }, 0 },
3396     {"insertq", { XM, XS }, 0 },
3397   },
3398
3399   /* PREFIX_0F7C */
3400   {
3401     { Bad_Opcode },
3402     { Bad_Opcode },
3403     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3404     { "haddps", { XM, EXx }, PREFIX_OPCODE },
3405   },
3406
3407   /* PREFIX_0F7D */
3408   {
3409     { Bad_Opcode },
3410     { Bad_Opcode },
3411     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3412     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3413   },
3414
3415   /* PREFIX_0F7E */
3416   {
3417     { "movK",   { Edq, MX }, PREFIX_OPCODE },
3418     { "movq",   { XM, EXq }, PREFIX_OPCODE },
3419     { "movK",   { Edq, XM }, PREFIX_OPCODE },
3420   },
3421
3422   /* PREFIX_0F7F */
3423   {
3424     { "movq",   { EMS, MX }, PREFIX_OPCODE },
3425     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3426     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3427   },
3428
3429   /* PREFIX_0FAE_REG_0_MOD_3 */
3430   {
3431     { Bad_Opcode },
3432     { "rdfsbase", { Ev }, 0 },
3433   },
3434
3435   /* PREFIX_0FAE_REG_1_MOD_3 */
3436   {
3437     { Bad_Opcode },
3438     { "rdgsbase", { Ev }, 0 },
3439   },
3440
3441   /* PREFIX_0FAE_REG_2_MOD_3 */
3442   {
3443     { Bad_Opcode },
3444     { "wrfsbase", { Ev }, 0 },
3445   },
3446
3447   /* PREFIX_0FAE_REG_3_MOD_3 */
3448   {
3449     { Bad_Opcode },
3450     { "wrgsbase", { Ev }, 0 },
3451   },
3452
3453   /* PREFIX_0FAE_REG_4_MOD_0 */
3454   {
3455     { "xsave",  { FXSAVE }, 0 },
3456     { "ptwrite{%LQ|}", { Edq }, 0 },
3457   },
3458
3459   /* PREFIX_0FAE_REG_4_MOD_3 */
3460   {
3461     { Bad_Opcode },
3462     { "ptwrite{%LQ|}", { Edq }, 0 },
3463   },
3464
3465   /* PREFIX_0FAE_REG_5_MOD_3 */
3466   {
3467     { "lfence",         { Skip_MODRM }, 0 },
3468     { "incsspK",        { Edq }, PREFIX_OPCODE },
3469   },
3470
3471   /* PREFIX_0FAE_REG_6_MOD_0 */
3472   {
3473     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE },
3474     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
3475     { "clwb",   { Mb }, PREFIX_OPCODE },
3476   },
3477
3478   /* PREFIX_0FAE_REG_6_MOD_3 */
3479   {
3480     { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) },
3481     { "umonitor",       { Eva }, PREFIX_OPCODE },
3482     { "tpause", { Edq }, PREFIX_OPCODE },
3483     { "umwait", { Edq }, PREFIX_OPCODE },
3484   },
3485
3486   /* PREFIX_0FAE_REG_7_MOD_0 */
3487   {
3488     { "clflush",        { Mb }, 0 },
3489     { Bad_Opcode },
3490     { "clflushopt",     { Mb }, 0 },
3491   },
3492
3493   /* PREFIX_0FB8 */
3494   {
3495     { Bad_Opcode },
3496     { "popcntS", { Gv, Ev }, 0 },
3497   },
3498
3499   /* PREFIX_0FBC */
3500   {
3501     { "bsfS",   { Gv, Ev }, 0 },
3502     { "tzcntS", { Gv, Ev }, 0 },
3503     { "bsfS",   { Gv, Ev }, 0 },
3504   },
3505
3506   /* PREFIX_0FBD */
3507   {
3508     { "bsrS",   { Gv, Ev }, 0 },
3509     { "lzcntS", { Gv, Ev }, 0 },
3510     { "bsrS",   { Gv, Ev }, 0 },
3511   },
3512
3513   /* PREFIX_0FC2 */
3514   {
3515     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
3516     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
3517     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
3518     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
3519   },
3520
3521   /* PREFIX_0FC7_REG_6_MOD_0 */
3522   {
3523     { "vmptrld",{ Mq }, 0 },
3524     { "vmxon",  { Mq }, 0 },
3525     { "vmclear",{ Mq }, 0 },
3526   },
3527
3528   /* PREFIX_0FC7_REG_6_MOD_3 */
3529   {
3530     { "rdrand", { Ev }, 0 },
3531     { X86_64_TABLE (X86_64_0FC7_REG_6_MOD_3_PREFIX_1) },
3532     { "rdrand", { Ev }, 0 }
3533   },
3534
3535   /* PREFIX_0FC7_REG_7_MOD_3 */
3536   {
3537     { "rdseed", { Ev }, 0 },
3538     { "rdpid",  { Em }, 0 },
3539     { "rdseed", { Ev }, 0 },
3540   },
3541
3542   /* PREFIX_0FD0 */
3543   {
3544     { Bad_Opcode },
3545     { Bad_Opcode },
3546     { "addsubpd", { XM, EXx }, 0 },
3547     { "addsubps", { XM, EXx }, 0 },
3548   },
3549
3550   /* PREFIX_0FD6 */
3551   {
3552     { Bad_Opcode },
3553     { "movq2dq",{ XM, MS }, 0 },
3554     { "movq",   { EXqS, XM }, 0 },
3555     { "movdq2q",{ MX, XS }, 0 },
3556   },
3557
3558   /* PREFIX_0FE6 */
3559   {
3560     { Bad_Opcode },
3561     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
3562     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
3563     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
3564   },
3565
3566   /* PREFIX_0FE7 */
3567   {
3568     { "movntq", { Mq, MX }, PREFIX_OPCODE },
3569     { Bad_Opcode },
3570     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
3571   },
3572
3573   /* PREFIX_0FF0 */
3574   {
3575     { Bad_Opcode },
3576     { Bad_Opcode },
3577     { Bad_Opcode },
3578     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
3579   },
3580
3581   /* PREFIX_0FF7 */
3582   {
3583     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
3584     { Bad_Opcode },
3585     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
3586   },
3587
3588   /* PREFIX_0F38D8 */
3589   {
3590     { Bad_Opcode },
3591     { REG_TABLE (REG_0F38D8_PREFIX_1) },
3592   },
3593
3594   /* PREFIX_0F38DC */
3595   {
3596     { Bad_Opcode },
3597     { MOD_TABLE (MOD_0F38DC_PREFIX_1) },
3598     { "aesenc", { XM, EXx }, 0 },
3599   },
3600
3601   /* PREFIX_0F38DD */
3602   {
3603     { Bad_Opcode },
3604     { MOD_TABLE (MOD_0F38DD_PREFIX_1) },
3605     { "aesenclast", { XM, EXx }, 0 },
3606   },
3607
3608   /* PREFIX_0F38DE */
3609   {
3610     { Bad_Opcode },
3611     { MOD_TABLE (MOD_0F38DE_PREFIX_1) },
3612     { "aesdec", { XM, EXx }, 0 },
3613   },
3614
3615   /* PREFIX_0F38DF */
3616   {
3617     { Bad_Opcode },
3618     { MOD_TABLE (MOD_0F38DF_PREFIX_1) },
3619     { "aesdeclast", { XM, EXx }, 0 },
3620   },
3621
3622   /* PREFIX_0F38F0 */
3623   {
3624     { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3625     { Bad_Opcode },
3626     { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3627     { "crc32A", { Gdq, Eb }, PREFIX_OPCODE },
3628   },
3629
3630   /* PREFIX_0F38F1 */
3631   {
3632     { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3633     { Bad_Opcode },
3634     { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3635     { "crc32Q", { Gdq, Ev }, PREFIX_OPCODE },
3636   },
3637
3638   /* PREFIX_0F38F6 */
3639   {
3640     { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
3641     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
3642     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
3643     { Bad_Opcode },
3644   },
3645
3646   /* PREFIX_0F38F8 */
3647   {
3648     { Bad_Opcode },
3649     { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
3650     { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
3651     { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
3652   },
3653   /* PREFIX_0F38FA */
3654   {
3655     { Bad_Opcode },
3656     { MOD_TABLE (MOD_0F38FA_PREFIX_1) },
3657   },
3658
3659   /* PREFIX_0F38FB */
3660   {
3661     { Bad_Opcode },
3662     { MOD_TABLE (MOD_0F38FB_PREFIX_1) },
3663   },
3664
3665   /* PREFIX_0F3A0F */
3666   {
3667     { Bad_Opcode },
3668     { MOD_TABLE (MOD_0F3A0F_PREFIX_1)},
3669   },
3670
3671   /* PREFIX_VEX_0F10 */
3672   {
3673     { "vmovups",        { XM, EXx }, 0 },
3674     { "vmovss",         { XMScalar, VexScalarR, EXd }, 0 },
3675     { "vmovupd",        { XM, EXx }, 0 },
3676     { "vmovsd",         { XMScalar, VexScalarR, EXq }, 0 },
3677   },
3678
3679   /* PREFIX_VEX_0F11 */
3680   {
3681     { "vmovups",        { EXxS, XM }, 0 },
3682     { "vmovss",         { EXdS, VexScalarR, XMScalar }, 0 },
3683     { "vmovupd",        { EXxS, XM }, 0 },
3684     { "vmovsd",         { EXqS, VexScalarR, XMScalar }, 0 },
3685   },
3686
3687   /* PREFIX_VEX_0F12 */
3688   {
3689     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
3690     { "vmovsldup",      { XM, EXx }, 0 },
3691     { MOD_TABLE (MOD_VEX_0F12_PREFIX_2) },
3692     { "vmovddup",       { XM, EXymmq }, 0 },
3693   },
3694
3695   /* PREFIX_VEX_0F16 */
3696   {
3697     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
3698     { "vmovshdup",      { XM, EXx }, 0 },
3699     { MOD_TABLE (MOD_VEX_0F16_PREFIX_2) },
3700   },
3701
3702   /* PREFIX_VEX_0F2A */
3703   {
3704     { Bad_Opcode },
3705     { "vcvtsi2ss{%LQ|}",        { XMScalar, VexScalar, Edq }, 0 },
3706     { Bad_Opcode },
3707     { "vcvtsi2sd{%LQ|}",        { XMScalar, VexScalar, Edq }, 0 },
3708   },
3709
3710   /* PREFIX_VEX_0F2C */
3711   {
3712     { Bad_Opcode },
3713     { "vcvttss2si",     { Gdq, EXd, EXxEVexS }, 0 },
3714     { Bad_Opcode },
3715     { "vcvttsd2si",     { Gdq, EXq, EXxEVexS }, 0 },
3716   },
3717
3718   /* PREFIX_VEX_0F2D */
3719   {
3720     { Bad_Opcode },
3721     { "vcvtss2si",      { Gdq, EXd, EXxEVexR }, 0 },
3722     { Bad_Opcode },
3723     { "vcvtsd2si",      { Gdq, EXq, EXxEVexR }, 0 },
3724   },
3725
3726   /* PREFIX_VEX_0F2E */
3727   {
3728     { "vucomisX",       { XMScalar, EXd, EXxEVexS }, PREFIX_OPCODE },
3729     { Bad_Opcode },
3730     { "vucomisX",       { XMScalar, EXq, EXxEVexS }, PREFIX_OPCODE },
3731   },
3732
3733   /* PREFIX_VEX_0F2F */
3734   {
3735     { "vcomisX",        { XMScalar, EXd, EXxEVexS }, PREFIX_OPCODE },
3736     { Bad_Opcode },
3737     { "vcomisX",        { XMScalar, EXq, EXxEVexS }, PREFIX_OPCODE },
3738   },
3739
3740   /* PREFIX_VEX_0F41_L_1_M_1_W_0 */
3741   {
3742     { "kandw",          { MaskG, MaskVex, MaskE }, 0 },
3743     { Bad_Opcode },
3744     { "kandb",          { MaskG, MaskVex, MaskE }, 0 },
3745   },
3746
3747   /* PREFIX_VEX_0F41_L_1_M_1_W_1 */
3748   {
3749     { "kandq",          { MaskG, MaskVex, MaskE }, 0 },
3750     { Bad_Opcode },
3751     { "kandd",          { MaskG, MaskVex, MaskE }, 0 },
3752   },
3753
3754   /* PREFIX_VEX_0F42_L_1_M_1_W_0 */
3755   {
3756     { "kandnw",         { MaskG, MaskVex, MaskE }, 0 },
3757     { Bad_Opcode },
3758     { "kandnb",         { MaskG, MaskVex, MaskE }, 0 },
3759   },
3760
3761   /* PREFIX_VEX_0F42_L_1_M_1_W_1 */
3762   {
3763     { "kandnq",         { MaskG, MaskVex, MaskE }, 0 },
3764     { Bad_Opcode },
3765     { "kandnd",         { MaskG, MaskVex, MaskE }, 0 },
3766   },
3767
3768   /* PREFIX_VEX_0F44_L_0_M_1_W_0 */
3769   {
3770     { "knotw",          { MaskG, MaskE }, 0 },
3771     { Bad_Opcode },
3772     { "knotb",          { MaskG, MaskE }, 0 },
3773   },
3774
3775   /* PREFIX_VEX_0F44_L_0_M_1_W_1 */
3776   {
3777     { "knotq",          { MaskG, MaskE }, 0 },
3778     { Bad_Opcode },
3779     { "knotd",          { MaskG, MaskE }, 0 },
3780   },
3781
3782   /* PREFIX_VEX_0F45_L_1_M_1_W_0 */
3783   {
3784     { "korw",       { MaskG, MaskVex, MaskE }, 0 },
3785     { Bad_Opcode },
3786     { "korb",       { MaskG, MaskVex, MaskE }, 0 },
3787   },
3788
3789   /* PREFIX_VEX_0F45_L_1_M_1_W_1 */
3790   {
3791     { "korq",       { MaskG, MaskVex, MaskE }, 0 },
3792     { Bad_Opcode },
3793     { "kord",       { MaskG, MaskVex, MaskE }, 0 },
3794   },
3795
3796   /* PREFIX_VEX_0F46_L_1_M_1_W_0 */
3797   {
3798     { "kxnorw",     { MaskG, MaskVex, MaskE }, 0 },
3799     { Bad_Opcode },
3800     { "kxnorb",     { MaskG, MaskVex, MaskE }, 0 },
3801   },
3802
3803   /* PREFIX_VEX_0F46_L_1_M_1_W_1 */
3804   {
3805     { "kxnorq",     { MaskG, MaskVex, MaskE }, 0 },
3806     { Bad_Opcode },
3807     { "kxnord",     { MaskG, MaskVex, MaskE }, 0 },
3808   },
3809
3810   /* PREFIX_VEX_0F47_L_1_M_1_W_0 */
3811   {
3812     { "kxorw",      { MaskG, MaskVex, MaskE }, 0 },
3813     { Bad_Opcode },
3814     { "kxorb",      { MaskG, MaskVex, MaskE }, 0 },
3815   },
3816
3817   /* PREFIX_VEX_0F47_L_1_M_1_W_1 */
3818   {
3819     { "kxorq",      { MaskG, MaskVex, MaskE }, 0 },
3820     { Bad_Opcode },
3821     { "kxord",      { MaskG, MaskVex, MaskE }, 0 },
3822   },
3823
3824   /* PREFIX_VEX_0F4A_L_1_M_1_W_0 */
3825   {
3826     { "kaddw",          { MaskG, MaskVex, MaskE }, 0 },
3827     { Bad_Opcode },
3828     { "kaddb",          { MaskG, MaskVex, MaskE }, 0 },
3829   },
3830
3831   /* PREFIX_VEX_0F4A_L_1_M_1_W_1 */
3832   {
3833     { "kaddq",          { MaskG, MaskVex, MaskE }, 0 },
3834     { Bad_Opcode },
3835     { "kaddd",          { MaskG, MaskVex, MaskE }, 0 },
3836   },
3837
3838   /* PREFIX_VEX_0F4B_L_1_M_1_W_0 */
3839   {
3840     { "kunpckwd",   { MaskG, MaskVex, MaskE }, 0 },
3841     { Bad_Opcode },
3842     { "kunpckbw",   { MaskG, MaskVex, MaskE }, 0 },
3843   },
3844
3845   /* PREFIX_VEX_0F4B_L_1_M_1_W_1 */
3846   {
3847     { "kunpckdq",   { MaskG, MaskVex, MaskE }, 0 },
3848   },
3849
3850   /* PREFIX_VEX_0F51 */
3851   {
3852     { "vsqrtps",        { XM, EXx }, 0 },
3853     { "vsqrtss",        { XMScalar, VexScalar, EXd }, 0 },
3854     { "vsqrtpd",        { XM, EXx }, 0 },
3855     { "vsqrtsd",        { XMScalar, VexScalar, EXq }, 0 },
3856   },
3857
3858   /* PREFIX_VEX_0F52 */
3859   {
3860     { "vrsqrtps",       { XM, EXx }, 0 },
3861     { "vrsqrtss",       { XMScalar, VexScalar, EXd }, 0 },
3862   },
3863
3864   /* PREFIX_VEX_0F53 */
3865   {
3866     { "vrcpps",         { XM, EXx }, 0 },
3867     { "vrcpss",         { XMScalar, VexScalar, EXd }, 0 },
3868   },
3869
3870   /* PREFIX_VEX_0F58 */
3871   {
3872     { "vaddps",         { XM, Vex, EXx }, 0 },
3873     { "vaddss",         { XMScalar, VexScalar, EXd }, 0 },
3874     { "vaddpd",         { XM, Vex, EXx }, 0 },
3875     { "vaddsd",         { XMScalar, VexScalar, EXq }, 0 },
3876   },
3877
3878   /* PREFIX_VEX_0F59 */
3879   {
3880     { "vmulps",         { XM, Vex, EXx }, 0 },
3881     { "vmulss",         { XMScalar, VexScalar, EXd }, 0 },
3882     { "vmulpd",         { XM, Vex, EXx }, 0 },
3883     { "vmulsd",         { XMScalar, VexScalar, EXq }, 0 },
3884   },
3885
3886   /* PREFIX_VEX_0F5A */
3887   {
3888     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
3889     { "vcvtss2sd",      { XMScalar, VexScalar, EXd }, 0 },
3890     { "vcvtpd2ps%XY",{ XMM, EXx }, 0 },
3891     { "vcvtsd2ss",      { XMScalar, VexScalar, EXq }, 0 },
3892   },
3893
3894   /* PREFIX_VEX_0F5B */
3895   {
3896     { "vcvtdq2ps",      { XM, EXx }, 0 },
3897     { "vcvttps2dq",     { XM, EXx }, 0 },
3898     { "vcvtps2dq",      { XM, EXx }, 0 },
3899   },
3900
3901   /* PREFIX_VEX_0F5C */
3902   {
3903     { "vsubps",         { XM, Vex, EXx }, 0 },
3904     { "vsubss",         { XMScalar, VexScalar, EXd }, 0 },
3905     { "vsubpd",         { XM, Vex, EXx }, 0 },
3906     { "vsubsd",         { XMScalar, VexScalar, EXq }, 0 },
3907   },
3908
3909   /* PREFIX_VEX_0F5D */
3910   {
3911     { "vminps",         { XM, Vex, EXx }, 0 },
3912     { "vminss",         { XMScalar, VexScalar, EXd }, 0 },
3913     { "vminpd",         { XM, Vex, EXx }, 0 },
3914     { "vminsd",         { XMScalar, VexScalar, EXq }, 0 },
3915   },
3916
3917   /* PREFIX_VEX_0F5E */
3918   {
3919     { "vdivps",         { XM, Vex, EXx }, 0 },
3920     { "vdivss",         { XMScalar, VexScalar, EXd }, 0 },
3921     { "vdivpd",         { XM, Vex, EXx }, 0 },
3922     { "vdivsd",         { XMScalar, VexScalar, EXq }, 0 },
3923   },
3924
3925   /* PREFIX_VEX_0F5F */
3926   {
3927     { "vmaxps",         { XM, Vex, EXx }, 0 },
3928     { "vmaxss",         { XMScalar, VexScalar, EXd }, 0 },
3929     { "vmaxpd",         { XM, Vex, EXx }, 0 },
3930     { "vmaxsd",         { XMScalar, VexScalar, EXq }, 0 },
3931   },
3932
3933   /* PREFIX_VEX_0F6F */
3934   {
3935     { Bad_Opcode },
3936     { "vmovdqu",        { XM, EXx }, 0 },
3937     { "vmovdqa",        { XM, EXx }, 0 },
3938   },
3939
3940   /* PREFIX_VEX_0F70 */
3941   {
3942     { Bad_Opcode },
3943     { "vpshufhw",       { XM, EXx, Ib }, 0 },
3944     { "vpshufd",        { XM, EXx, Ib }, 0 },
3945     { "vpshuflw",       { XM, EXx, Ib }, 0 },
3946   },
3947
3948   /* PREFIX_VEX_0F7C */
3949   {
3950     { Bad_Opcode },
3951     { Bad_Opcode },
3952     { "vhaddpd",        { XM, Vex, EXx }, 0 },
3953     { "vhaddps",        { XM, Vex, EXx }, 0 },
3954   },
3955
3956   /* PREFIX_VEX_0F7D */
3957   {
3958     { Bad_Opcode },
3959     { Bad_Opcode },
3960     { "vhsubpd",        { XM, Vex, EXx }, 0 },
3961     { "vhsubps",        { XM, Vex, EXx }, 0 },
3962   },
3963
3964   /* PREFIX_VEX_0F7E */
3965   {
3966     { Bad_Opcode },
3967     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
3968     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
3969   },
3970
3971   /* PREFIX_VEX_0F7F */
3972   {
3973     { Bad_Opcode },
3974     { "vmovdqu",        { EXxS, XM }, 0 },
3975     { "vmovdqa",        { EXxS, XM }, 0 },
3976   },
3977
3978   /* PREFIX_VEX_0F90_L_0_W_0 */
3979   {
3980     { "kmovw",          { MaskG, MaskE }, 0 },
3981     { Bad_Opcode },
3982     { "kmovb",          { MaskG, MaskBDE }, 0 },
3983   },
3984
3985   /* PREFIX_VEX_0F90_L_0_W_1 */
3986   {
3987     { "kmovq",          { MaskG, MaskE }, 0 },
3988     { Bad_Opcode },
3989     { "kmovd",          { MaskG, MaskBDE }, 0 },
3990   },
3991
3992   /* PREFIX_VEX_0F91_L_0_M_0_W_0 */
3993   {
3994     { "kmovw",          { Ew, MaskG }, 0 },
3995     { Bad_Opcode },
3996     { "kmovb",          { Eb, MaskG }, 0 },
3997   },
3998
3999   /* PREFIX_VEX_0F91_L_0_M_0_W_1 */
4000   {
4001     { "kmovq",          { Eq, MaskG }, 0 },
4002     { Bad_Opcode },
4003     { "kmovd",          { Ed, MaskG }, 0 },
4004   },
4005
4006   /* PREFIX_VEX_0F92_L_0_M_1_W_0 */
4007   {
4008     { "kmovw",          { MaskG, Edq }, 0 },
4009     { Bad_Opcode },
4010     { "kmovb",          { MaskG, Edq }, 0 },
4011     { "kmovd",          { MaskG, Edq }, 0 },
4012   },
4013
4014   /* PREFIX_VEX_0F92_L_0_M_1_W_1 */
4015   {
4016     { Bad_Opcode },
4017     { Bad_Opcode },
4018     { Bad_Opcode },
4019     { "kmovK",          { MaskG, Edq }, 0 },
4020   },
4021
4022   /* PREFIX_VEX_0F93_L_0_M_1_W_0 */
4023   {
4024     { "kmovw",          { Gdq, MaskE }, 0 },
4025     { Bad_Opcode },
4026     { "kmovb",          { Gdq, MaskE }, 0 },
4027     { "kmovd",          { Gdq, MaskE }, 0 },
4028   },
4029
4030   /* PREFIX_VEX_0F93_L_0_M_1_W_1 */
4031   {
4032     { Bad_Opcode },
4033     { Bad_Opcode },
4034     { Bad_Opcode },
4035     { "kmovK",          { Gdq, MaskE }, 0 },
4036   },
4037
4038   /* PREFIX_VEX_0F98_L_0_M_1_W_0 */
4039   {
4040     { "kortestw", { MaskG, MaskE }, 0 },
4041     { Bad_Opcode },
4042     { "kortestb", { MaskG, MaskE }, 0 },
4043   },
4044
4045   /* PREFIX_VEX_0F98_L_0_M_1_W_1 */
4046   {
4047     { "kortestq", { MaskG, MaskE }, 0 },
4048     { Bad_Opcode },
4049     { "kortestd", { MaskG, MaskE }, 0 },
4050   },
4051
4052   /* PREFIX_VEX_0F99_L_0_M_1_W_0 */
4053   {
4054     { "ktestw", { MaskG, MaskE }, 0 },
4055     { Bad_Opcode },
4056     { "ktestb", { MaskG, MaskE }, 0 },
4057   },
4058
4059   /* PREFIX_VEX_0F99_L_0_M_1_W_1 */
4060   {
4061     { "ktestq", { MaskG, MaskE }, 0 },
4062     { Bad_Opcode },
4063     { "ktestd", { MaskG, MaskE }, 0 },
4064   },
4065
4066   /* PREFIX_VEX_0FC2 */
4067   {
4068     { "vcmpps",         { XM, Vex, EXx, CMP }, 0 },
4069     { "vcmpss",         { XMScalar, VexScalar, EXd, CMP }, 0 },
4070     { "vcmppd",         { XM, Vex, EXx, CMP }, 0 },
4071     { "vcmpsd",         { XMScalar, VexScalar, EXq, CMP }, 0 },
4072   },
4073
4074   /* PREFIX_VEX_0FD0 */
4075   {
4076     { Bad_Opcode },
4077     { Bad_Opcode },
4078     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
4079     { "vaddsubps",      { XM, Vex, EXx }, 0 },
4080   },
4081
4082   /* PREFIX_VEX_0FE6 */
4083   {
4084     { Bad_Opcode },
4085     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
4086     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
4087     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
4088   },
4089
4090   /* PREFIX_VEX_0FF0 */
4091   {
4092     { Bad_Opcode },
4093     { Bad_Opcode },
4094     { Bad_Opcode },
4095     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
4096   },
4097
4098   /* PREFIX_VEX_0F3849_X86_64 */
4099   {
4100     { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_0) },
4101     { Bad_Opcode },
4102     { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_2) },
4103     { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_3) },
4104   },
4105
4106   /* PREFIX_VEX_0F384B_X86_64 */
4107   {
4108     { Bad_Opcode },
4109     { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_1) },
4110     { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_2) },
4111     { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_3) },
4112   },
4113
4114   /* PREFIX_VEX_0F385C_X86_64 */
4115   {
4116     { Bad_Opcode },
4117     { VEX_W_TABLE (VEX_W_0F385C_X86_64_P_1) },
4118     { Bad_Opcode },
4119   },
4120
4121   /* PREFIX_VEX_0F385E_X86_64 */
4122   {
4123     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_0) },
4124     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_1) },
4125     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_2) },
4126     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_3) },
4127   },
4128
4129   /* PREFIX_VEX_0F38F5_L_0 */
4130   {
4131     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
4132     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
4133     { Bad_Opcode },
4134     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
4135   },
4136
4137   /* PREFIX_VEX_0F38F6_L_0 */
4138   {
4139     { Bad_Opcode },
4140     { Bad_Opcode },
4141     { Bad_Opcode },
4142     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
4143   },
4144
4145   /* PREFIX_VEX_0F38F7_L_0 */
4146   {
4147     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
4148     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
4149     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
4150     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
4151   },
4152
4153   /* PREFIX_VEX_0F3AF0_L_0 */
4154   {
4155     { Bad_Opcode },
4156     { Bad_Opcode },
4157     { Bad_Opcode },
4158     { "rorxS",          { Gdq, Edq, Ib }, 0 },
4159   },
4160
4161 #include "i386-dis-evex-prefix.h"
4162 };
4163
4164 static const struct dis386 x86_64_table[][2] = {
4165   /* X86_64_06 */
4166   {
4167     { "pushP", { es }, 0 },
4168   },
4169
4170   /* X86_64_07 */
4171   {
4172     { "popP", { es }, 0 },
4173   },
4174
4175   /* X86_64_0E */
4176   {
4177     { "pushP", { cs }, 0 },
4178   },
4179
4180   /* X86_64_16 */
4181   {
4182     { "pushP", { ss }, 0 },
4183   },
4184
4185   /* X86_64_17 */
4186   {
4187     { "popP", { ss }, 0 },
4188   },
4189
4190   /* X86_64_1E */
4191   {
4192     { "pushP", { ds }, 0 },
4193   },
4194
4195   /* X86_64_1F */
4196   {
4197     { "popP", { ds }, 0 },
4198   },
4199
4200   /* X86_64_27 */
4201   {
4202     { "daa", { XX }, 0 },
4203   },
4204
4205   /* X86_64_2F */
4206   {
4207     { "das", { XX }, 0 },
4208   },
4209
4210   /* X86_64_37 */
4211   {
4212     { "aaa", { XX }, 0 },
4213   },
4214
4215   /* X86_64_3F */
4216   {
4217     { "aas", { XX }, 0 },
4218   },
4219
4220   /* X86_64_60 */
4221   {
4222     { "pushaP", { XX }, 0 },
4223   },
4224
4225   /* X86_64_61 */
4226   {
4227     { "popaP", { XX }, 0 },
4228   },
4229
4230   /* X86_64_62 */
4231   {
4232     { MOD_TABLE (MOD_62_32BIT) },
4233     { EVEX_TABLE (EVEX_0F) },
4234   },
4235
4236   /* X86_64_63 */
4237   {
4238     { "arpl", { Ew, Gw }, 0 },
4239     { "movs", { Gv, { MOVSXD_Fixup, movsxd_mode } }, 0 },
4240   },
4241
4242   /* X86_64_6D */
4243   {
4244     { "ins{R|}", { Yzr, indirDX }, 0 },
4245     { "ins{G|}", { Yzr, indirDX }, 0 },
4246   },
4247
4248   /* X86_64_6F */
4249   {
4250     { "outs{R|}", { indirDXr, Xz }, 0 },
4251     { "outs{G|}", { indirDXr, Xz }, 0 },
4252   },
4253
4254   /* X86_64_82 */
4255   {
4256     /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
4257     { REG_TABLE (REG_80) },
4258   },
4259
4260   /* X86_64_9A */
4261   {
4262     { "{l|}call{P|}", { Ap }, 0 },
4263   },
4264
4265   /* X86_64_C2 */
4266   {
4267     { "retP",           { Iw, BND }, 0 },
4268     { "ret@",           { Iw, BND }, 0 },
4269   },
4270
4271   /* X86_64_C3 */
4272   {
4273     { "retP",           { BND }, 0 },
4274     { "ret@",           { BND }, 0 },
4275   },
4276
4277   /* X86_64_C4 */
4278   {
4279     { MOD_TABLE (MOD_C4_32BIT) },
4280     { VEX_C4_TABLE (VEX_0F) },
4281   },
4282
4283   /* X86_64_C5 */
4284   {
4285     { MOD_TABLE (MOD_C5_32BIT) },
4286     { VEX_C5_TABLE (VEX_0F) },
4287   },
4288
4289   /* X86_64_CE */
4290   {
4291     { "into", { XX }, 0 },
4292   },
4293
4294   /* X86_64_D4 */
4295   {
4296     { "aam", { Ib }, 0 },
4297   },
4298
4299   /* X86_64_D5 */
4300   {
4301     { "aad", { Ib }, 0 },
4302   },
4303
4304   /* X86_64_E8 */
4305   {
4306     { "callP",          { Jv, BND }, 0 },
4307     { "call@",          { Jv, BND }, 0 }
4308   },
4309
4310   /* X86_64_E9 */
4311   {
4312     { "jmpP",           { Jv, BND }, 0 },
4313     { "jmp@",           { Jv, BND }, 0 }
4314   },
4315
4316   /* X86_64_EA */
4317   {
4318     { "{l|}jmp{P|}", { Ap }, 0 },
4319   },
4320
4321   /* X86_64_0F01_REG_0 */
4322   {
4323     { "sgdt{Q|Q}", { M }, 0 },
4324     { "sgdt", { M }, 0 },
4325   },
4326
4327   /* X86_64_0F01_REG_1 */
4328   {
4329     { "sidt{Q|Q}", { M }, 0 },
4330     { "sidt", { M }, 0 },
4331   },
4332
4333   /* X86_64_0F01_REG_1_RM_5_PREFIX_2 */
4334   {
4335     { Bad_Opcode },
4336     { "seamret",        { Skip_MODRM }, 0 },
4337   },
4338
4339   /* X86_64_0F01_REG_1_RM_6_PREFIX_2 */
4340   {
4341     { Bad_Opcode },
4342     { "seamops",        { Skip_MODRM }, 0 },
4343   },
4344
4345   /* X86_64_0F01_REG_1_RM_7_PREFIX_2 */
4346   {
4347     { Bad_Opcode },
4348     { "seamcall",       { Skip_MODRM }, 0 },
4349   },
4350
4351   /* X86_64_0F01_REG_2 */
4352   {
4353     { "lgdt{Q|Q}", { M }, 0 },
4354     { "lgdt", { M }, 0 },
4355   },
4356
4357   /* X86_64_0F01_REG_3 */
4358   {
4359     { "lidt{Q|Q}", { M }, 0 },
4360     { "lidt", { M }, 0 },
4361   },
4362
4363   /* X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1 */
4364   {
4365     { Bad_Opcode },
4366     { "uiret",  { Skip_MODRM }, 0 },
4367   },
4368
4369   /* X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1 */
4370   {
4371     { Bad_Opcode },
4372     { "testui", { Skip_MODRM }, 0 },
4373   },
4374
4375   /* X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1 */
4376   {
4377     { Bad_Opcode },
4378     { "clui",   { Skip_MODRM }, 0 },
4379   },
4380
4381   /* X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1 */
4382   {
4383     { Bad_Opcode },
4384     { "stui",   { Skip_MODRM }, 0 },
4385   },
4386
4387   /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1 */
4388   {
4389     { Bad_Opcode },
4390     { "rmpadjust",      { Skip_MODRM }, 0 },
4391   },
4392
4393   /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3 */
4394   {
4395     { Bad_Opcode },
4396     { "rmpupdate",      { Skip_MODRM }, 0 },
4397   },
4398
4399   /* X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1 */
4400   {
4401     { Bad_Opcode },
4402     { "psmash", { Skip_MODRM }, 0 },
4403   },
4404
4405   {
4406     /* X86_64_0F24 */
4407     { "movZ",           { Em, Td }, 0 },
4408   },
4409
4410   {
4411     /* X86_64_0F26 */
4412     { "movZ",           { Td, Em }, 0 },
4413   },
4414
4415   /* X86_64_0FC7_REG_6_MOD_3_PREFIX_1 */
4416   {
4417     { Bad_Opcode },
4418     { "senduipi",       { Eq }, 0 },
4419   },
4420
4421   /* X86_64_VEX_0F3849 */
4422   {
4423     { Bad_Opcode },
4424     { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64) },
4425   },
4426
4427   /* X86_64_VEX_0F384B */
4428   {
4429     { Bad_Opcode },
4430     { PREFIX_TABLE (PREFIX_VEX_0F384B_X86_64) },
4431   },
4432
4433   /* X86_64_VEX_0F385C */
4434   {
4435     { Bad_Opcode },
4436     { PREFIX_TABLE (PREFIX_VEX_0F385C_X86_64) },
4437   },
4438
4439   /* X86_64_VEX_0F385E */
4440   {
4441     { Bad_Opcode },
4442     { PREFIX_TABLE (PREFIX_VEX_0F385E_X86_64) },
4443   },
4444 };
4445
4446 static const struct dis386 three_byte_table[][256] = {
4447
4448   /* THREE_BYTE_0F38 */
4449   {
4450     /* 00 */
4451     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
4452     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
4453     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
4454     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
4455     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
4456     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
4457     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
4458     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
4459     /* 08 */
4460     { "psignb",         { MX, EM }, PREFIX_OPCODE },
4461     { "psignw",         { MX, EM }, PREFIX_OPCODE },
4462     { "psignd",         { MX, EM }, PREFIX_OPCODE },
4463     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
4464     { Bad_Opcode },
4465     { Bad_Opcode },
4466     { Bad_Opcode },
4467     { Bad_Opcode },
4468     /* 10 */
4469     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_DATA },
4470     { Bad_Opcode },
4471     { Bad_Opcode },
4472     { Bad_Opcode },
4473     { "blendvps", { XM, EXx, XMM0 }, PREFIX_DATA },
4474     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_DATA },
4475     { Bad_Opcode },
4476     { "ptest",  { XM, EXx }, PREFIX_DATA },
4477     /* 18 */
4478     { Bad_Opcode },
4479     { Bad_Opcode },
4480     { Bad_Opcode },
4481     { Bad_Opcode },
4482     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
4483     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
4484     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
4485     { Bad_Opcode },
4486     /* 20 */
4487     { "pmovsxbw", { XM, EXq }, PREFIX_DATA },
4488     { "pmovsxbd", { XM, EXd }, PREFIX_DATA },
4489     { "pmovsxbq", { XM, EXw }, PREFIX_DATA },
4490     { "pmovsxwd", { XM, EXq }, PREFIX_DATA },
4491     { "pmovsxwq", { XM, EXd }, PREFIX_DATA },
4492     { "pmovsxdq", { XM, EXq }, PREFIX_DATA },
4493     { Bad_Opcode },
4494     { Bad_Opcode },
4495     /* 28 */
4496     { "pmuldq", { XM, EXx }, PREFIX_DATA },
4497     { "pcmpeqq", { XM, EXx }, PREFIX_DATA },
4498     { MOD_TABLE (MOD_0F382A) },
4499     { "packusdw", { XM, EXx }, PREFIX_DATA },
4500     { Bad_Opcode },
4501     { Bad_Opcode },
4502     { Bad_Opcode },
4503     { Bad_Opcode },
4504     /* 30 */
4505     { "pmovzxbw", { XM, EXq }, PREFIX_DATA },
4506     { "pmovzxbd", { XM, EXd }, PREFIX_DATA },
4507     { "pmovzxbq", { XM, EXw }, PREFIX_DATA },
4508     { "pmovzxwd", { XM, EXq }, PREFIX_DATA },
4509     { "pmovzxwq", { XM, EXd }, PREFIX_DATA },
4510     { "pmovzxdq", { XM, EXq }, PREFIX_DATA },
4511     { Bad_Opcode },
4512     { "pcmpgtq", { XM, EXx }, PREFIX_DATA },
4513     /* 38 */
4514     { "pminsb", { XM, EXx }, PREFIX_DATA },
4515     { "pminsd", { XM, EXx }, PREFIX_DATA },
4516     { "pminuw", { XM, EXx }, PREFIX_DATA },
4517     { "pminud", { XM, EXx }, PREFIX_DATA },
4518     { "pmaxsb", { XM, EXx }, PREFIX_DATA },
4519     { "pmaxsd", { XM, EXx }, PREFIX_DATA },
4520     { "pmaxuw", { XM, EXx }, PREFIX_DATA },
4521     { "pmaxud", { XM, EXx }, PREFIX_DATA },
4522     /* 40 */
4523     { "pmulld", { XM, EXx }, PREFIX_DATA },
4524     { "phminposuw", { XM, EXx }, PREFIX_DATA },
4525     { Bad_Opcode },
4526     { Bad_Opcode },
4527     { Bad_Opcode },
4528     { Bad_Opcode },
4529     { Bad_Opcode },
4530     { Bad_Opcode },
4531     /* 48 */
4532     { Bad_Opcode },
4533     { Bad_Opcode },
4534     { Bad_Opcode },
4535     { Bad_Opcode },
4536     { Bad_Opcode },
4537     { Bad_Opcode },
4538     { Bad_Opcode },
4539     { Bad_Opcode },
4540     /* 50 */
4541     { Bad_Opcode },
4542     { Bad_Opcode },
4543     { Bad_Opcode },
4544     { Bad_Opcode },
4545     { Bad_Opcode },
4546     { Bad_Opcode },
4547     { Bad_Opcode },
4548     { Bad_Opcode },
4549     /* 58 */
4550     { Bad_Opcode },
4551     { Bad_Opcode },
4552     { Bad_Opcode },
4553     { Bad_Opcode },
4554     { Bad_Opcode },
4555     { Bad_Opcode },
4556     { Bad_Opcode },
4557     { Bad_Opcode },
4558     /* 60 */
4559     { Bad_Opcode },
4560     { Bad_Opcode },
4561     { Bad_Opcode },
4562     { Bad_Opcode },
4563     { Bad_Opcode },
4564     { Bad_Opcode },
4565     { Bad_Opcode },
4566     { Bad_Opcode },
4567     /* 68 */
4568     { Bad_Opcode },
4569     { Bad_Opcode },
4570     { Bad_Opcode },
4571     { Bad_Opcode },
4572     { Bad_Opcode },
4573     { Bad_Opcode },
4574     { Bad_Opcode },
4575     { Bad_Opcode },
4576     /* 70 */
4577     { Bad_Opcode },
4578     { Bad_Opcode },
4579     { Bad_Opcode },
4580     { Bad_Opcode },
4581     { Bad_Opcode },
4582     { Bad_Opcode },
4583     { Bad_Opcode },
4584     { Bad_Opcode },
4585     /* 78 */
4586     { Bad_Opcode },
4587     { Bad_Opcode },
4588     { Bad_Opcode },
4589     { Bad_Opcode },
4590     { Bad_Opcode },
4591     { Bad_Opcode },
4592     { Bad_Opcode },
4593     { Bad_Opcode },
4594     /* 80 */
4595     { "invept", { Gm, Mo }, PREFIX_DATA },
4596     { "invvpid", { Gm, Mo }, PREFIX_DATA },
4597     { "invpcid", { Gm, M }, PREFIX_DATA },
4598     { Bad_Opcode },
4599     { Bad_Opcode },
4600     { Bad_Opcode },
4601     { Bad_Opcode },
4602     { Bad_Opcode },
4603     /* 88 */
4604     { Bad_Opcode },
4605     { Bad_Opcode },
4606     { Bad_Opcode },
4607     { Bad_Opcode },
4608     { Bad_Opcode },
4609     { Bad_Opcode },
4610     { Bad_Opcode },
4611     { Bad_Opcode },
4612     /* 90 */
4613     { Bad_Opcode },
4614     { Bad_Opcode },
4615     { Bad_Opcode },
4616     { Bad_Opcode },
4617     { Bad_Opcode },
4618     { Bad_Opcode },
4619     { Bad_Opcode },
4620     { Bad_Opcode },
4621     /* 98 */
4622     { Bad_Opcode },
4623     { Bad_Opcode },
4624     { Bad_Opcode },
4625     { Bad_Opcode },
4626     { Bad_Opcode },
4627     { Bad_Opcode },
4628     { Bad_Opcode },
4629     { Bad_Opcode },
4630     /* a0 */
4631     { Bad_Opcode },
4632     { Bad_Opcode },
4633     { Bad_Opcode },
4634     { Bad_Opcode },
4635     { Bad_Opcode },
4636     { Bad_Opcode },
4637     { Bad_Opcode },
4638     { Bad_Opcode },
4639     /* a8 */
4640     { Bad_Opcode },
4641     { Bad_Opcode },
4642     { Bad_Opcode },
4643     { Bad_Opcode },
4644     { Bad_Opcode },
4645     { Bad_Opcode },
4646     { Bad_Opcode },
4647     { Bad_Opcode },
4648     /* b0 */
4649     { Bad_Opcode },
4650     { Bad_Opcode },
4651     { Bad_Opcode },
4652     { Bad_Opcode },
4653     { Bad_Opcode },
4654     { Bad_Opcode },
4655     { Bad_Opcode },
4656     { Bad_Opcode },
4657     /* b8 */
4658     { Bad_Opcode },
4659     { Bad_Opcode },
4660     { Bad_Opcode },
4661     { Bad_Opcode },
4662     { Bad_Opcode },
4663     { Bad_Opcode },
4664     { Bad_Opcode },
4665     { Bad_Opcode },
4666     /* c0 */
4667     { Bad_Opcode },
4668     { Bad_Opcode },
4669     { Bad_Opcode },
4670     { Bad_Opcode },
4671     { Bad_Opcode },
4672     { Bad_Opcode },
4673     { Bad_Opcode },
4674     { Bad_Opcode },
4675     /* c8 */
4676     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4677     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4678     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4679     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4680     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4681     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4682     { Bad_Opcode },
4683     { "gf2p8mulb", { XM, EXxmm }, PREFIX_DATA },
4684     /* d0 */
4685     { Bad_Opcode },
4686     { Bad_Opcode },
4687     { Bad_Opcode },
4688     { Bad_Opcode },
4689     { Bad_Opcode },
4690     { Bad_Opcode },
4691     { Bad_Opcode },
4692     { Bad_Opcode },
4693     /* d8 */
4694     { PREFIX_TABLE (PREFIX_0F38D8) },
4695     { Bad_Opcode },
4696     { Bad_Opcode },
4697     { "aesimc", { XM, EXx }, PREFIX_DATA },
4698     { PREFIX_TABLE (PREFIX_0F38DC) },
4699     { PREFIX_TABLE (PREFIX_0F38DD) },
4700     { PREFIX_TABLE (PREFIX_0F38DE) },
4701     { PREFIX_TABLE (PREFIX_0F38DF) },
4702     /* e0 */
4703     { Bad_Opcode },
4704     { Bad_Opcode },
4705     { Bad_Opcode },
4706     { Bad_Opcode },
4707     { Bad_Opcode },
4708     { Bad_Opcode },
4709     { Bad_Opcode },
4710     { Bad_Opcode },
4711     /* e8 */
4712     { Bad_Opcode },
4713     { Bad_Opcode },
4714     { Bad_Opcode },
4715     { Bad_Opcode },
4716     { Bad_Opcode },
4717     { Bad_Opcode },
4718     { Bad_Opcode },
4719     { Bad_Opcode },
4720     /* f0 */
4721     { PREFIX_TABLE (PREFIX_0F38F0) },
4722     { PREFIX_TABLE (PREFIX_0F38F1) },
4723     { Bad_Opcode },
4724     { Bad_Opcode },
4725     { Bad_Opcode },
4726     { MOD_TABLE (MOD_0F38F5) },
4727     { PREFIX_TABLE (PREFIX_0F38F6) },
4728     { Bad_Opcode },
4729     /* f8 */
4730     { PREFIX_TABLE (PREFIX_0F38F8) },
4731     { MOD_TABLE (MOD_0F38F9) },
4732     { PREFIX_TABLE (PREFIX_0F38FA) },
4733     { PREFIX_TABLE (PREFIX_0F38FB) },
4734     { Bad_Opcode },
4735     { Bad_Opcode },
4736     { Bad_Opcode },
4737     { Bad_Opcode },
4738   },
4739   /* THREE_BYTE_0F3A */
4740   {
4741     /* 00 */
4742     { Bad_Opcode },
4743     { Bad_Opcode },
4744     { Bad_Opcode },
4745     { Bad_Opcode },
4746     { Bad_Opcode },
4747     { Bad_Opcode },
4748     { Bad_Opcode },
4749     { Bad_Opcode },
4750     /* 08 */
4751     { "roundps", { XM, EXx, Ib }, PREFIX_DATA },
4752     { "roundpd", { XM, EXx, Ib }, PREFIX_DATA },
4753     { "roundss", { XM, EXd, Ib }, PREFIX_DATA },
4754     { "roundsd", { XM, EXq, Ib }, PREFIX_DATA },
4755     { "blendps", { XM, EXx, Ib }, PREFIX_DATA },
4756     { "blendpd", { XM, EXx, Ib }, PREFIX_DATA },
4757     { "pblendw", { XM, EXx, Ib }, PREFIX_DATA },
4758     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
4759     /* 10 */
4760     { Bad_Opcode },
4761     { Bad_Opcode },
4762     { Bad_Opcode },
4763     { Bad_Opcode },
4764     { "pextrb", { Edb, XM, Ib }, PREFIX_DATA },
4765     { "pextrw", { Edw, XM, Ib }, PREFIX_DATA },
4766     { "pextrK", { Edq, XM, Ib }, PREFIX_DATA },
4767     { "extractps", { Ed, XM, Ib }, PREFIX_DATA },
4768     /* 18 */
4769     { Bad_Opcode },
4770     { Bad_Opcode },
4771     { Bad_Opcode },
4772     { Bad_Opcode },
4773     { Bad_Opcode },
4774     { Bad_Opcode },
4775     { Bad_Opcode },
4776     { Bad_Opcode },
4777     /* 20 */
4778     { "pinsrb", { XM, Edb, Ib }, PREFIX_DATA },
4779     { "insertps", { XM, EXd, Ib }, PREFIX_DATA },
4780     { "pinsrK", { XM, Edq, Ib }, PREFIX_DATA },
4781     { Bad_Opcode },
4782     { Bad_Opcode },
4783     { Bad_Opcode },
4784     { Bad_Opcode },
4785     { Bad_Opcode },
4786     /* 28 */
4787     { Bad_Opcode },
4788     { Bad_Opcode },
4789     { Bad_Opcode },
4790     { Bad_Opcode },
4791     { Bad_Opcode },
4792     { Bad_Opcode },
4793     { Bad_Opcode },
4794     { Bad_Opcode },
4795     /* 30 */
4796     { Bad_Opcode },
4797     { Bad_Opcode },
4798     { Bad_Opcode },
4799     { Bad_Opcode },
4800     { Bad_Opcode },
4801     { Bad_Opcode },
4802     { Bad_Opcode },
4803     { Bad_Opcode },
4804     /* 38 */
4805     { Bad_Opcode },
4806     { Bad_Opcode },
4807     { Bad_Opcode },
4808     { Bad_Opcode },
4809     { Bad_Opcode },
4810     { Bad_Opcode },
4811     { Bad_Opcode },
4812     { Bad_Opcode },
4813     /* 40 */
4814     { "dpps",   { XM, EXx, Ib }, PREFIX_DATA },
4815     { "dppd",   { XM, EXx, Ib }, PREFIX_DATA },
4816     { "mpsadbw", { XM, EXx, Ib }, PREFIX_DATA },
4817     { Bad_Opcode },
4818     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_DATA },
4819     { Bad_Opcode },
4820     { Bad_Opcode },
4821     { Bad_Opcode },
4822     /* 48 */
4823     { Bad_Opcode },
4824     { Bad_Opcode },
4825     { Bad_Opcode },
4826     { Bad_Opcode },
4827     { Bad_Opcode },
4828     { Bad_Opcode },
4829     { Bad_Opcode },
4830     { Bad_Opcode },
4831     /* 50 */
4832     { Bad_Opcode },
4833     { Bad_Opcode },
4834     { Bad_Opcode },
4835     { Bad_Opcode },
4836     { Bad_Opcode },
4837     { Bad_Opcode },
4838     { Bad_Opcode },
4839     { Bad_Opcode },
4840     /* 58 */
4841     { Bad_Opcode },
4842     { Bad_Opcode },
4843     { Bad_Opcode },
4844     { Bad_Opcode },
4845     { Bad_Opcode },
4846     { Bad_Opcode },
4847     { Bad_Opcode },
4848     { Bad_Opcode },
4849     /* 60 */
4850     { "pcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
4851     { "pcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
4852     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_DATA },
4853     { "pcmpistri", { XM, EXx, Ib }, PREFIX_DATA },
4854     { Bad_Opcode },
4855     { Bad_Opcode },
4856     { Bad_Opcode },
4857     { Bad_Opcode },
4858     /* 68 */
4859     { Bad_Opcode },
4860     { Bad_Opcode },
4861     { Bad_Opcode },
4862     { Bad_Opcode },
4863     { Bad_Opcode },
4864     { Bad_Opcode },
4865     { Bad_Opcode },
4866     { Bad_Opcode },
4867     /* 70 */
4868     { Bad_Opcode },
4869     { Bad_Opcode },
4870     { Bad_Opcode },
4871     { Bad_Opcode },
4872     { Bad_Opcode },
4873     { Bad_Opcode },
4874     { Bad_Opcode },
4875     { Bad_Opcode },
4876     /* 78 */
4877     { Bad_Opcode },
4878     { Bad_Opcode },
4879     { Bad_Opcode },
4880     { Bad_Opcode },
4881     { Bad_Opcode },
4882     { Bad_Opcode },
4883     { Bad_Opcode },
4884     { Bad_Opcode },
4885     /* 80 */
4886     { Bad_Opcode },
4887     { Bad_Opcode },
4888     { Bad_Opcode },
4889     { Bad_Opcode },
4890     { Bad_Opcode },
4891     { Bad_Opcode },
4892     { Bad_Opcode },
4893     { Bad_Opcode },
4894     /* 88 */
4895     { Bad_Opcode },
4896     { Bad_Opcode },
4897     { Bad_Opcode },
4898     { Bad_Opcode },
4899     { Bad_Opcode },
4900     { Bad_Opcode },
4901     { Bad_Opcode },
4902     { Bad_Opcode },
4903     /* 90 */
4904     { Bad_Opcode },
4905     { Bad_Opcode },
4906     { Bad_Opcode },
4907     { Bad_Opcode },
4908     { Bad_Opcode },
4909     { Bad_Opcode },
4910     { Bad_Opcode },
4911     { Bad_Opcode },
4912     /* 98 */
4913     { Bad_Opcode },
4914     { Bad_Opcode },
4915     { Bad_Opcode },
4916     { Bad_Opcode },
4917     { Bad_Opcode },
4918     { Bad_Opcode },
4919     { Bad_Opcode },
4920     { Bad_Opcode },
4921     /* a0 */
4922     { Bad_Opcode },
4923     { Bad_Opcode },
4924     { Bad_Opcode },
4925     { Bad_Opcode },
4926     { Bad_Opcode },
4927     { Bad_Opcode },
4928     { Bad_Opcode },
4929     { Bad_Opcode },
4930     /* a8 */
4931     { Bad_Opcode },
4932     { Bad_Opcode },
4933     { Bad_Opcode },
4934     { Bad_Opcode },
4935     { Bad_Opcode },
4936     { Bad_Opcode },
4937     { Bad_Opcode },
4938     { Bad_Opcode },
4939     /* b0 */
4940     { Bad_Opcode },
4941     { Bad_Opcode },
4942     { Bad_Opcode },
4943     { Bad_Opcode },
4944     { Bad_Opcode },
4945     { Bad_Opcode },
4946     { Bad_Opcode },
4947     { Bad_Opcode },
4948     /* b8 */
4949     { Bad_Opcode },
4950     { Bad_Opcode },
4951     { Bad_Opcode },
4952     { Bad_Opcode },
4953     { Bad_Opcode },
4954     { Bad_Opcode },
4955     { Bad_Opcode },
4956     { Bad_Opcode },
4957     /* c0 */
4958     { Bad_Opcode },
4959     { Bad_Opcode },
4960     { Bad_Opcode },
4961     { Bad_Opcode },
4962     { Bad_Opcode },
4963     { Bad_Opcode },
4964     { Bad_Opcode },
4965     { Bad_Opcode },
4966     /* c8 */
4967     { Bad_Opcode },
4968     { Bad_Opcode },
4969     { Bad_Opcode },
4970     { Bad_Opcode },
4971     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4972     { Bad_Opcode },
4973     { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_DATA },
4974     { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_DATA },
4975     /* d0 */
4976     { Bad_Opcode },
4977     { Bad_Opcode },
4978     { Bad_Opcode },
4979     { Bad_Opcode },
4980     { Bad_Opcode },
4981     { Bad_Opcode },
4982     { Bad_Opcode },
4983     { Bad_Opcode },
4984     /* d8 */
4985     { Bad_Opcode },
4986     { Bad_Opcode },
4987     { Bad_Opcode },
4988     { Bad_Opcode },
4989     { Bad_Opcode },
4990     { Bad_Opcode },
4991     { Bad_Opcode },
4992     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
4993     /* e0 */
4994     { Bad_Opcode },
4995     { Bad_Opcode },
4996     { Bad_Opcode },
4997     { Bad_Opcode },
4998     { Bad_Opcode },
4999     { Bad_Opcode },
5000     { Bad_Opcode },
5001     { Bad_Opcode },
5002     /* e8 */
5003     { Bad_Opcode },
5004     { Bad_Opcode },
5005     { Bad_Opcode },
5006     { Bad_Opcode },
5007     { Bad_Opcode },
5008     { Bad_Opcode },
5009     { Bad_Opcode },
5010     { Bad_Opcode },
5011     /* f0 */
5012     { PREFIX_TABLE (PREFIX_0F3A0F) },
5013     { Bad_Opcode },
5014     { Bad_Opcode },
5015     { Bad_Opcode },
5016     { Bad_Opcode },
5017     { Bad_Opcode },
5018     { Bad_Opcode },
5019     { Bad_Opcode },
5020     /* f8 */
5021     { Bad_Opcode },
5022     { Bad_Opcode },
5023     { Bad_Opcode },
5024     { Bad_Opcode },
5025     { Bad_Opcode },
5026     { Bad_Opcode },
5027     { Bad_Opcode },
5028     { Bad_Opcode },
5029   },
5030 };
5031
5032 static const struct dis386 xop_table[][256] = {
5033   /* XOP_08 */
5034   {
5035     /* 00 */
5036     { Bad_Opcode },
5037     { Bad_Opcode },
5038     { Bad_Opcode },
5039     { Bad_Opcode },
5040     { Bad_Opcode },
5041     { Bad_Opcode },
5042     { Bad_Opcode },
5043     { Bad_Opcode },
5044     /* 08 */
5045     { Bad_Opcode },
5046     { Bad_Opcode },
5047     { Bad_Opcode },
5048     { Bad_Opcode },
5049     { Bad_Opcode },
5050     { Bad_Opcode },
5051     { Bad_Opcode },
5052     { Bad_Opcode },
5053     /* 10 */
5054     { Bad_Opcode },
5055     { Bad_Opcode },
5056     { Bad_Opcode },
5057     { Bad_Opcode },
5058     { Bad_Opcode },
5059     { Bad_Opcode },
5060     { Bad_Opcode },
5061     { Bad_Opcode },
5062     /* 18 */
5063     { Bad_Opcode },
5064     { Bad_Opcode },
5065     { Bad_Opcode },
5066     { Bad_Opcode },
5067     { Bad_Opcode },
5068     { Bad_Opcode },
5069     { Bad_Opcode },
5070     { Bad_Opcode },
5071     /* 20 */
5072     { Bad_Opcode },
5073     { Bad_Opcode },
5074     { Bad_Opcode },
5075     { Bad_Opcode },
5076     { Bad_Opcode },
5077     { Bad_Opcode },
5078     { Bad_Opcode },
5079     { Bad_Opcode },
5080     /* 28 */
5081     { Bad_Opcode },
5082     { Bad_Opcode },
5083     { Bad_Opcode },
5084     { Bad_Opcode },
5085     { Bad_Opcode },
5086     { Bad_Opcode },
5087     { Bad_Opcode },
5088     { Bad_Opcode },
5089     /* 30 */
5090     { Bad_Opcode },
5091     { Bad_Opcode },
5092     { Bad_Opcode },
5093     { Bad_Opcode },
5094     { Bad_Opcode },
5095     { Bad_Opcode },
5096     { Bad_Opcode },
5097     { Bad_Opcode },
5098     /* 38 */
5099     { Bad_Opcode },
5100     { Bad_Opcode },
5101     { Bad_Opcode },
5102     { Bad_Opcode },
5103     { Bad_Opcode },
5104     { Bad_Opcode },
5105     { Bad_Opcode },
5106     { Bad_Opcode },
5107     /* 40 */
5108     { Bad_Opcode },
5109     { Bad_Opcode },
5110     { Bad_Opcode },
5111     { Bad_Opcode },
5112     { Bad_Opcode },
5113     { Bad_Opcode },
5114     { Bad_Opcode },
5115     { Bad_Opcode },
5116     /* 48 */
5117     { Bad_Opcode },
5118     { Bad_Opcode },
5119     { Bad_Opcode },
5120     { Bad_Opcode },
5121     { Bad_Opcode },
5122     { Bad_Opcode },
5123     { Bad_Opcode },
5124     { Bad_Opcode },
5125     /* 50 */
5126     { Bad_Opcode },
5127     { Bad_Opcode },
5128     { Bad_Opcode },
5129     { Bad_Opcode },
5130     { Bad_Opcode },
5131     { Bad_Opcode },
5132     { Bad_Opcode },
5133     { Bad_Opcode },
5134     /* 58 */
5135     { Bad_Opcode },
5136     { Bad_Opcode },
5137     { Bad_Opcode },
5138     { Bad_Opcode },
5139     { Bad_Opcode },
5140     { Bad_Opcode },
5141     { Bad_Opcode },
5142     { Bad_Opcode },
5143     /* 60 */
5144     { Bad_Opcode },
5145     { Bad_Opcode },
5146     { Bad_Opcode },
5147     { Bad_Opcode },
5148     { Bad_Opcode },
5149     { Bad_Opcode },
5150     { Bad_Opcode },
5151     { Bad_Opcode },
5152     /* 68 */
5153     { Bad_Opcode },
5154     { Bad_Opcode },
5155     { Bad_Opcode },
5156     { Bad_Opcode },
5157     { Bad_Opcode },
5158     { Bad_Opcode },
5159     { Bad_Opcode },
5160     { Bad_Opcode },
5161     /* 70 */
5162     { Bad_Opcode },
5163     { Bad_Opcode },
5164     { Bad_Opcode },
5165     { Bad_Opcode },
5166     { Bad_Opcode },
5167     { Bad_Opcode },
5168     { Bad_Opcode },
5169     { Bad_Opcode },
5170     /* 78 */
5171     { Bad_Opcode },
5172     { Bad_Opcode },
5173     { Bad_Opcode },
5174     { Bad_Opcode },
5175     { Bad_Opcode },
5176     { Bad_Opcode },
5177     { Bad_Opcode },
5178     { Bad_Opcode },
5179     /* 80 */
5180     { Bad_Opcode },
5181     { Bad_Opcode },
5182     { Bad_Opcode },
5183     { Bad_Opcode },
5184     { Bad_Opcode },
5185     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_85) },
5186     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_86) },
5187     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_87) },
5188     /* 88 */
5189     { Bad_Opcode },
5190     { Bad_Opcode },
5191     { Bad_Opcode },
5192     { Bad_Opcode },
5193     { Bad_Opcode },
5194     { Bad_Opcode },
5195     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8E) },
5196     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8F) },
5197     /* 90 */
5198     { Bad_Opcode },
5199     { Bad_Opcode },
5200     { Bad_Opcode },
5201     { Bad_Opcode },
5202     { Bad_Opcode },
5203     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_95) },
5204     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_96) },
5205     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_97) },
5206     /* 98 */
5207     { Bad_Opcode },
5208     { Bad_Opcode },
5209     { Bad_Opcode },
5210     { Bad_Opcode },
5211     { Bad_Opcode },
5212     { Bad_Opcode },
5213     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9E) },
5214     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9F) },
5215     /* a0 */
5216     { Bad_Opcode },
5217     { Bad_Opcode },
5218     { "vpcmov",         { XM, Vex, EXx, XMVexI4 }, 0 },
5219     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A3) },
5220     { Bad_Opcode },
5221     { Bad_Opcode },
5222     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A6) },
5223     { Bad_Opcode },
5224     /* a8 */
5225     { Bad_Opcode },
5226     { Bad_Opcode },
5227     { Bad_Opcode },
5228     { Bad_Opcode },
5229     { Bad_Opcode },
5230     { Bad_Opcode },
5231     { Bad_Opcode },
5232     { Bad_Opcode },
5233     /* b0 */
5234     { Bad_Opcode },
5235     { Bad_Opcode },
5236     { Bad_Opcode },
5237     { Bad_Opcode },
5238     { Bad_Opcode },
5239     { Bad_Opcode },
5240     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_B6) },
5241     { Bad_Opcode },
5242     /* b8 */
5243     { Bad_Opcode },
5244     { Bad_Opcode },
5245     { Bad_Opcode },
5246     { Bad_Opcode },
5247     { Bad_Opcode },
5248     { Bad_Opcode },
5249     { Bad_Opcode },
5250     { Bad_Opcode },
5251     /* c0 */
5252     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C0) },
5253     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C1) },
5254     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C2) },
5255     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C3) },
5256     { Bad_Opcode },
5257     { Bad_Opcode },
5258     { Bad_Opcode },
5259     { Bad_Opcode },
5260     /* c8 */
5261     { Bad_Opcode },
5262     { Bad_Opcode },
5263     { Bad_Opcode },
5264     { Bad_Opcode },
5265     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
5266     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
5267     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
5268     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
5269     /* d0 */
5270     { Bad_Opcode },
5271     { Bad_Opcode },
5272     { Bad_Opcode },
5273     { Bad_Opcode },
5274     { Bad_Opcode },
5275     { Bad_Opcode },
5276     { Bad_Opcode },
5277     { Bad_Opcode },
5278     /* d8 */
5279     { Bad_Opcode },
5280     { Bad_Opcode },
5281     { Bad_Opcode },
5282     { Bad_Opcode },
5283     { Bad_Opcode },
5284     { Bad_Opcode },
5285     { Bad_Opcode },
5286     { Bad_Opcode },
5287     /* e0 */
5288     { Bad_Opcode },
5289     { Bad_Opcode },
5290     { Bad_Opcode },
5291     { Bad_Opcode },
5292     { Bad_Opcode },
5293     { Bad_Opcode },
5294     { Bad_Opcode },
5295     { Bad_Opcode },
5296     /* e8 */
5297     { Bad_Opcode },
5298     { Bad_Opcode },
5299     { Bad_Opcode },
5300     { Bad_Opcode },
5301     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
5302     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
5303     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
5304     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
5305     /* f0 */
5306     { Bad_Opcode },
5307     { Bad_Opcode },
5308     { Bad_Opcode },
5309     { Bad_Opcode },
5310     { Bad_Opcode },
5311     { Bad_Opcode },
5312     { Bad_Opcode },
5313     { Bad_Opcode },
5314     /* f8 */
5315     { Bad_Opcode },
5316     { Bad_Opcode },
5317     { Bad_Opcode },
5318     { Bad_Opcode },
5319     { Bad_Opcode },
5320     { Bad_Opcode },
5321     { Bad_Opcode },
5322     { Bad_Opcode },
5323   },
5324   /* XOP_09 */
5325   {
5326     /* 00 */
5327     { Bad_Opcode },
5328     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_01) },
5329     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_02) },
5330     { Bad_Opcode },
5331     { Bad_Opcode },
5332     { Bad_Opcode },
5333     { Bad_Opcode },
5334     { Bad_Opcode },
5335     /* 08 */
5336     { Bad_Opcode },
5337     { Bad_Opcode },
5338     { Bad_Opcode },
5339     { Bad_Opcode },
5340     { Bad_Opcode },
5341     { Bad_Opcode },
5342     { Bad_Opcode },
5343     { Bad_Opcode },
5344     /* 10 */
5345     { Bad_Opcode },
5346     { Bad_Opcode },
5347     { MOD_TABLE (MOD_XOP_09_12) },
5348     { Bad_Opcode },
5349     { Bad_Opcode },
5350     { Bad_Opcode },
5351     { Bad_Opcode },
5352     { Bad_Opcode },
5353     /* 18 */
5354     { Bad_Opcode },
5355     { Bad_Opcode },
5356     { Bad_Opcode },
5357     { Bad_Opcode },
5358     { Bad_Opcode },
5359     { Bad_Opcode },
5360     { Bad_Opcode },
5361     { Bad_Opcode },
5362     /* 20 */
5363     { Bad_Opcode },
5364     { Bad_Opcode },
5365     { Bad_Opcode },
5366     { Bad_Opcode },
5367     { Bad_Opcode },
5368     { Bad_Opcode },
5369     { Bad_Opcode },
5370     { Bad_Opcode },
5371     /* 28 */
5372     { Bad_Opcode },
5373     { Bad_Opcode },
5374     { Bad_Opcode },
5375     { Bad_Opcode },
5376     { Bad_Opcode },
5377     { Bad_Opcode },
5378     { Bad_Opcode },
5379     { Bad_Opcode },
5380     /* 30 */
5381     { Bad_Opcode },
5382     { Bad_Opcode },
5383     { Bad_Opcode },
5384     { Bad_Opcode },
5385     { Bad_Opcode },
5386     { Bad_Opcode },
5387     { Bad_Opcode },
5388     { Bad_Opcode },
5389     /* 38 */
5390     { Bad_Opcode },
5391     { Bad_Opcode },
5392     { Bad_Opcode },
5393     { Bad_Opcode },
5394     { Bad_Opcode },
5395     { Bad_Opcode },
5396     { Bad_Opcode },
5397     { Bad_Opcode },
5398     /* 40 */
5399     { Bad_Opcode },
5400     { Bad_Opcode },
5401     { Bad_Opcode },
5402     { Bad_Opcode },
5403     { Bad_Opcode },
5404     { Bad_Opcode },
5405     { Bad_Opcode },
5406     { Bad_Opcode },
5407     /* 48 */
5408     { Bad_Opcode },
5409     { Bad_Opcode },
5410     { Bad_Opcode },
5411     { Bad_Opcode },
5412     { Bad_Opcode },
5413     { Bad_Opcode },
5414     { Bad_Opcode },
5415     { Bad_Opcode },
5416     /* 50 */
5417     { Bad_Opcode },
5418     { Bad_Opcode },
5419     { Bad_Opcode },
5420     { Bad_Opcode },
5421     { Bad_Opcode },
5422     { Bad_Opcode },
5423     { Bad_Opcode },
5424     { Bad_Opcode },
5425     /* 58 */
5426     { Bad_Opcode },
5427     { Bad_Opcode },
5428     { Bad_Opcode },
5429     { Bad_Opcode },
5430     { Bad_Opcode },
5431     { Bad_Opcode },
5432     { Bad_Opcode },
5433     { Bad_Opcode },
5434     /* 60 */
5435     { Bad_Opcode },
5436     { Bad_Opcode },
5437     { Bad_Opcode },
5438     { Bad_Opcode },
5439     { Bad_Opcode },
5440     { Bad_Opcode },
5441     { Bad_Opcode },
5442     { Bad_Opcode },
5443     /* 68 */
5444     { Bad_Opcode },
5445     { Bad_Opcode },
5446     { Bad_Opcode },
5447     { Bad_Opcode },
5448     { Bad_Opcode },
5449     { Bad_Opcode },
5450     { Bad_Opcode },
5451     { Bad_Opcode },
5452     /* 70 */
5453     { Bad_Opcode },
5454     { Bad_Opcode },
5455     { Bad_Opcode },
5456     { Bad_Opcode },
5457     { Bad_Opcode },
5458     { Bad_Opcode },
5459     { Bad_Opcode },
5460     { Bad_Opcode },
5461     /* 78 */
5462     { Bad_Opcode },
5463     { Bad_Opcode },
5464     { Bad_Opcode },
5465     { Bad_Opcode },
5466     { Bad_Opcode },
5467     { Bad_Opcode },
5468     { Bad_Opcode },
5469     { Bad_Opcode },
5470     /* 80 */
5471     { VEX_W_TABLE (VEX_W_0FXOP_09_80) },
5472     { VEX_W_TABLE (VEX_W_0FXOP_09_81) },
5473     { VEX_W_TABLE (VEX_W_0FXOP_09_82) },
5474     { VEX_W_TABLE (VEX_W_0FXOP_09_83) },
5475     { Bad_Opcode },
5476     { Bad_Opcode },
5477     { Bad_Opcode },
5478     { Bad_Opcode },
5479     /* 88 */
5480     { Bad_Opcode },
5481     { Bad_Opcode },
5482     { Bad_Opcode },
5483     { Bad_Opcode },
5484     { Bad_Opcode },
5485     { Bad_Opcode },
5486     { Bad_Opcode },
5487     { Bad_Opcode },
5488     /* 90 */
5489     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_90) },
5490     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_91) },
5491     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_92) },
5492     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_93) },
5493     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_94) },
5494     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_95) },
5495     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_96) },
5496     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_97) },
5497     /* 98 */
5498     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_98) },
5499     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_99) },
5500     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9A) },
5501     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9B) },
5502     { Bad_Opcode },
5503     { Bad_Opcode },
5504     { Bad_Opcode },
5505     { Bad_Opcode },
5506     /* a0 */
5507     { Bad_Opcode },
5508     { Bad_Opcode },
5509     { Bad_Opcode },
5510     { Bad_Opcode },
5511     { Bad_Opcode },
5512     { Bad_Opcode },
5513     { Bad_Opcode },
5514     { Bad_Opcode },
5515     /* a8 */
5516     { Bad_Opcode },
5517     { Bad_Opcode },
5518     { Bad_Opcode },
5519     { Bad_Opcode },
5520     { Bad_Opcode },
5521     { Bad_Opcode },
5522     { Bad_Opcode },
5523     { Bad_Opcode },
5524     /* b0 */
5525     { Bad_Opcode },
5526     { Bad_Opcode },
5527     { Bad_Opcode },
5528     { Bad_Opcode },
5529     { Bad_Opcode },
5530     { Bad_Opcode },
5531     { Bad_Opcode },
5532     { Bad_Opcode },
5533     /* b8 */
5534     { Bad_Opcode },
5535     { Bad_Opcode },
5536     { Bad_Opcode },
5537     { Bad_Opcode },
5538     { Bad_Opcode },
5539     { Bad_Opcode },
5540     { Bad_Opcode },
5541     { Bad_Opcode },
5542     /* c0 */
5543     { Bad_Opcode },
5544     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C1) },
5545     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C2) },
5546     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C3) },
5547     { Bad_Opcode },
5548     { Bad_Opcode },
5549     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C6) },
5550     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C7) },
5551     /* c8 */
5552     { Bad_Opcode },
5553     { Bad_Opcode },
5554     { Bad_Opcode },
5555     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_CB) },
5556     { Bad_Opcode },
5557     { Bad_Opcode },
5558     { Bad_Opcode },
5559     { Bad_Opcode },
5560     /* d0 */
5561     { Bad_Opcode },
5562     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D1) },
5563     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D2) },
5564     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D3) },
5565     { Bad_Opcode },
5566     { Bad_Opcode },
5567     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D6) },
5568     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D7) },
5569     /* d8 */
5570     { Bad_Opcode },
5571     { Bad_Opcode },
5572     { Bad_Opcode },
5573     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_DB) },
5574     { Bad_Opcode },
5575     { Bad_Opcode },
5576     { Bad_Opcode },
5577     { Bad_Opcode },
5578     /* e0 */
5579     { Bad_Opcode },
5580     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E1) },
5581     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E2) },
5582     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E3) },
5583     { Bad_Opcode },
5584     { Bad_Opcode },
5585     { Bad_Opcode },
5586     { Bad_Opcode },
5587     /* e8 */
5588     { Bad_Opcode },
5589     { Bad_Opcode },
5590     { Bad_Opcode },
5591     { Bad_Opcode },
5592     { Bad_Opcode },
5593     { Bad_Opcode },
5594     { Bad_Opcode },
5595     { Bad_Opcode },
5596     /* f0 */
5597     { Bad_Opcode },
5598     { Bad_Opcode },
5599     { Bad_Opcode },
5600     { Bad_Opcode },
5601     { Bad_Opcode },
5602     { Bad_Opcode },
5603     { Bad_Opcode },
5604     { Bad_Opcode },
5605     /* f8 */
5606     { Bad_Opcode },
5607     { Bad_Opcode },
5608     { Bad_Opcode },
5609     { Bad_Opcode },
5610     { Bad_Opcode },
5611     { Bad_Opcode },
5612     { Bad_Opcode },
5613     { Bad_Opcode },
5614   },
5615   /* XOP_0A */
5616   {
5617     /* 00 */
5618     { Bad_Opcode },
5619     { Bad_Opcode },
5620     { Bad_Opcode },
5621     { Bad_Opcode },
5622     { Bad_Opcode },
5623     { Bad_Opcode },
5624     { Bad_Opcode },
5625     { Bad_Opcode },
5626     /* 08 */
5627     { Bad_Opcode },
5628     { Bad_Opcode },
5629     { Bad_Opcode },
5630     { Bad_Opcode },
5631     { Bad_Opcode },
5632     { Bad_Opcode },
5633     { Bad_Opcode },
5634     { Bad_Opcode },
5635     /* 10 */
5636     { "bextrS", { Gdq, Edq, Id }, 0 },
5637     { Bad_Opcode },
5638     { VEX_LEN_TABLE (VEX_LEN_0FXOP_0A_12) },
5639     { Bad_Opcode },
5640     { Bad_Opcode },
5641     { Bad_Opcode },
5642     { Bad_Opcode },
5643     { Bad_Opcode },
5644     /* 18 */
5645     { Bad_Opcode },
5646     { Bad_Opcode },
5647     { Bad_Opcode },
5648     { Bad_Opcode },
5649     { Bad_Opcode },
5650     { Bad_Opcode },
5651     { Bad_Opcode },
5652     { Bad_Opcode },
5653     /* 20 */
5654     { Bad_Opcode },
5655     { Bad_Opcode },
5656     { Bad_Opcode },
5657     { Bad_Opcode },
5658     { Bad_Opcode },
5659     { Bad_Opcode },
5660     { Bad_Opcode },
5661     { Bad_Opcode },
5662     /* 28 */
5663     { Bad_Opcode },
5664     { Bad_Opcode },
5665     { Bad_Opcode },
5666     { Bad_Opcode },
5667     { Bad_Opcode },
5668     { Bad_Opcode },
5669     { Bad_Opcode },
5670     { Bad_Opcode },
5671     /* 30 */
5672     { Bad_Opcode },
5673     { Bad_Opcode },
5674     { Bad_Opcode },
5675     { Bad_Opcode },
5676     { Bad_Opcode },
5677     { Bad_Opcode },
5678     { Bad_Opcode },
5679     { Bad_Opcode },
5680     /* 38 */
5681     { Bad_Opcode },
5682     { Bad_Opcode },
5683     { Bad_Opcode },
5684     { Bad_Opcode },
5685     { Bad_Opcode },
5686     { Bad_Opcode },
5687     { Bad_Opcode },
5688     { Bad_Opcode },
5689     /* 40 */
5690     { Bad_Opcode },
5691     { Bad_Opcode },
5692     { Bad_Opcode },
5693     { Bad_Opcode },
5694     { Bad_Opcode },
5695     { Bad_Opcode },
5696     { Bad_Opcode },
5697     { Bad_Opcode },
5698     /* 48 */
5699     { Bad_Opcode },
5700     { Bad_Opcode },
5701     { Bad_Opcode },
5702     { Bad_Opcode },
5703     { Bad_Opcode },
5704     { Bad_Opcode },
5705     { Bad_Opcode },
5706     { Bad_Opcode },
5707     /* 50 */
5708     { Bad_Opcode },
5709     { Bad_Opcode },
5710     { Bad_Opcode },
5711     { Bad_Opcode },
5712     { Bad_Opcode },
5713     { Bad_Opcode },
5714     { Bad_Opcode },
5715     { Bad_Opcode },
5716     /* 58 */
5717     { Bad_Opcode },
5718     { Bad_Opcode },
5719     { Bad_Opcode },
5720     { Bad_Opcode },
5721     { Bad_Opcode },
5722     { Bad_Opcode },
5723     { Bad_Opcode },
5724     { Bad_Opcode },
5725     /* 60 */
5726     { Bad_Opcode },
5727     { Bad_Opcode },
5728     { Bad_Opcode },
5729     { Bad_Opcode },
5730     { Bad_Opcode },
5731     { Bad_Opcode },
5732     { Bad_Opcode },
5733     { Bad_Opcode },
5734     /* 68 */
5735     { Bad_Opcode },
5736     { Bad_Opcode },
5737     { Bad_Opcode },
5738     { Bad_Opcode },
5739     { Bad_Opcode },
5740     { Bad_Opcode },
5741     { Bad_Opcode },
5742     { Bad_Opcode },
5743     /* 70 */
5744     { Bad_Opcode },
5745     { Bad_Opcode },
5746     { Bad_Opcode },
5747     { Bad_Opcode },
5748     { Bad_Opcode },
5749     { Bad_Opcode },
5750     { Bad_Opcode },
5751     { Bad_Opcode },
5752     /* 78 */
5753     { Bad_Opcode },
5754     { Bad_Opcode },
5755     { Bad_Opcode },
5756     { Bad_Opcode },
5757     { Bad_Opcode },
5758     { Bad_Opcode },
5759     { Bad_Opcode },
5760     { Bad_Opcode },
5761     /* 80 */
5762     { Bad_Opcode },
5763     { Bad_Opcode },
5764     { Bad_Opcode },
5765     { Bad_Opcode },
5766     { Bad_Opcode },
5767     { Bad_Opcode },
5768     { Bad_Opcode },
5769     { Bad_Opcode },
5770     /* 88 */
5771     { Bad_Opcode },
5772     { Bad_Opcode },
5773     { Bad_Opcode },
5774     { Bad_Opcode },
5775     { Bad_Opcode },
5776     { Bad_Opcode },
5777     { Bad_Opcode },
5778     { Bad_Opcode },
5779     /* 90 */
5780     { Bad_Opcode },
5781     { Bad_Opcode },
5782     { Bad_Opcode },
5783     { Bad_Opcode },
5784     { Bad_Opcode },
5785     { Bad_Opcode },
5786     { Bad_Opcode },
5787     { Bad_Opcode },
5788     /* 98 */
5789     { Bad_Opcode },
5790     { Bad_Opcode },
5791     { Bad_Opcode },
5792     { Bad_Opcode },
5793     { Bad_Opcode },
5794     { Bad_Opcode },
5795     { Bad_Opcode },
5796     { Bad_Opcode },
5797     /* a0 */
5798     { Bad_Opcode },
5799     { Bad_Opcode },
5800     { Bad_Opcode },
5801     { Bad_Opcode },
5802     { Bad_Opcode },
5803     { Bad_Opcode },
5804     { Bad_Opcode },
5805     { Bad_Opcode },
5806     /* a8 */
5807     { Bad_Opcode },
5808     { Bad_Opcode },
5809     { Bad_Opcode },
5810     { Bad_Opcode },
5811     { Bad_Opcode },
5812     { Bad_Opcode },
5813     { Bad_Opcode },
5814     { Bad_Opcode },
5815     /* b0 */
5816     { Bad_Opcode },
5817     { Bad_Opcode },
5818     { Bad_Opcode },
5819     { Bad_Opcode },
5820     { Bad_Opcode },
5821     { Bad_Opcode },
5822     { Bad_Opcode },
5823     { Bad_Opcode },
5824     /* b8 */
5825     { Bad_Opcode },
5826     { Bad_Opcode },
5827     { Bad_Opcode },
5828     { Bad_Opcode },
5829     { Bad_Opcode },
5830     { Bad_Opcode },
5831     { Bad_Opcode },
5832     { Bad_Opcode },
5833     /* c0 */
5834     { Bad_Opcode },
5835     { Bad_Opcode },
5836     { Bad_Opcode },
5837     { Bad_Opcode },
5838     { Bad_Opcode },
5839     { Bad_Opcode },
5840     { Bad_Opcode },
5841     { Bad_Opcode },
5842     /* c8 */
5843     { Bad_Opcode },
5844     { Bad_Opcode },
5845     { Bad_Opcode },
5846     { Bad_Opcode },
5847     { Bad_Opcode },
5848     { Bad_Opcode },
5849     { Bad_Opcode },
5850     { Bad_Opcode },
5851     /* d0 */
5852     { Bad_Opcode },
5853     { Bad_Opcode },
5854     { Bad_Opcode },
5855     { Bad_Opcode },
5856     { Bad_Opcode },
5857     { Bad_Opcode },
5858     { Bad_Opcode },
5859     { Bad_Opcode },
5860     /* d8 */
5861     { Bad_Opcode },
5862     { Bad_Opcode },
5863     { Bad_Opcode },
5864     { Bad_Opcode },
5865     { Bad_Opcode },
5866     { Bad_Opcode },
5867     { Bad_Opcode },
5868     { Bad_Opcode },
5869     /* e0 */
5870     { Bad_Opcode },
5871     { Bad_Opcode },
5872     { Bad_Opcode },
5873     { Bad_Opcode },
5874     { Bad_Opcode },
5875     { Bad_Opcode },
5876     { Bad_Opcode },
5877     { Bad_Opcode },
5878     /* e8 */
5879     { Bad_Opcode },
5880     { Bad_Opcode },
5881     { Bad_Opcode },
5882     { Bad_Opcode },
5883     { Bad_Opcode },
5884     { Bad_Opcode },
5885     { Bad_Opcode },
5886     { Bad_Opcode },
5887     /* f0 */
5888     { Bad_Opcode },
5889     { Bad_Opcode },
5890     { Bad_Opcode },
5891     { Bad_Opcode },
5892     { Bad_Opcode },
5893     { Bad_Opcode },
5894     { Bad_Opcode },
5895     { Bad_Opcode },
5896     /* f8 */
5897     { Bad_Opcode },
5898     { Bad_Opcode },
5899     { Bad_Opcode },
5900     { Bad_Opcode },
5901     { Bad_Opcode },
5902     { Bad_Opcode },
5903     { Bad_Opcode },
5904     { Bad_Opcode },
5905   },
5906 };
5907
5908 static const struct dis386 vex_table[][256] = {
5909   /* VEX_0F */
5910   {
5911     /* 00 */
5912     { Bad_Opcode },
5913     { Bad_Opcode },
5914     { Bad_Opcode },
5915     { Bad_Opcode },
5916     { Bad_Opcode },
5917     { Bad_Opcode },
5918     { Bad_Opcode },
5919     { Bad_Opcode },
5920     /* 08 */
5921     { Bad_Opcode },
5922     { Bad_Opcode },
5923     { Bad_Opcode },
5924     { Bad_Opcode },
5925     { Bad_Opcode },
5926     { Bad_Opcode },
5927     { Bad_Opcode },
5928     { Bad_Opcode },
5929     /* 10 */
5930     { PREFIX_TABLE (PREFIX_VEX_0F10) },
5931     { PREFIX_TABLE (PREFIX_VEX_0F11) },
5932     { PREFIX_TABLE (PREFIX_VEX_0F12) },
5933     { MOD_TABLE (MOD_VEX_0F13) },
5934     { "vunpcklpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
5935     { "vunpckhpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
5936     { PREFIX_TABLE (PREFIX_VEX_0F16) },
5937     { MOD_TABLE (MOD_VEX_0F17) },
5938     /* 18 */
5939     { Bad_Opcode },
5940     { Bad_Opcode },
5941     { Bad_Opcode },
5942     { Bad_Opcode },
5943     { Bad_Opcode },
5944     { Bad_Opcode },
5945     { Bad_Opcode },
5946     { Bad_Opcode },
5947     /* 20 */
5948     { Bad_Opcode },
5949     { Bad_Opcode },
5950     { Bad_Opcode },
5951     { Bad_Opcode },
5952     { Bad_Opcode },
5953     { Bad_Opcode },
5954     { Bad_Opcode },
5955     { Bad_Opcode },
5956     /* 28 */
5957     { "vmovapX",        { XM, EXx }, PREFIX_OPCODE },
5958     { "vmovapX",        { EXxS, XM }, PREFIX_OPCODE },
5959     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
5960     { MOD_TABLE (MOD_VEX_0F2B) },
5961     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
5962     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
5963     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
5964     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
5965     /* 30 */
5966     { Bad_Opcode },
5967     { Bad_Opcode },
5968     { Bad_Opcode },
5969     { Bad_Opcode },
5970     { Bad_Opcode },
5971     { Bad_Opcode },
5972     { Bad_Opcode },
5973     { Bad_Opcode },
5974     /* 38 */
5975     { Bad_Opcode },
5976     { Bad_Opcode },
5977     { Bad_Opcode },
5978     { Bad_Opcode },
5979     { Bad_Opcode },
5980     { Bad_Opcode },
5981     { Bad_Opcode },
5982     { Bad_Opcode },
5983     /* 40 */
5984     { Bad_Opcode },
5985     { VEX_LEN_TABLE (VEX_LEN_0F41) },
5986     { VEX_LEN_TABLE (VEX_LEN_0F42) },
5987     { Bad_Opcode },
5988     { VEX_LEN_TABLE (VEX_LEN_0F44) },
5989     { VEX_LEN_TABLE (VEX_LEN_0F45) },
5990     { VEX_LEN_TABLE (VEX_LEN_0F46) },
5991     { VEX_LEN_TABLE (VEX_LEN_0F47) },
5992     /* 48 */
5993     { Bad_Opcode },
5994     { Bad_Opcode },
5995     { VEX_LEN_TABLE (VEX_LEN_0F4A) },
5996     { VEX_LEN_TABLE (VEX_LEN_0F4B) },
5997     { Bad_Opcode },
5998     { Bad_Opcode },
5999     { Bad_Opcode },
6000     { Bad_Opcode },
6001     /* 50 */
6002     { MOD_TABLE (MOD_VEX_0F50) },
6003     { PREFIX_TABLE (PREFIX_VEX_0F51) },
6004     { PREFIX_TABLE (PREFIX_VEX_0F52) },
6005     { PREFIX_TABLE (PREFIX_VEX_0F53) },
6006     { "vandpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
6007     { "vandnpX",        { XM, Vex, EXx }, PREFIX_OPCODE },
6008     { "vorpX",          { XM, Vex, EXx }, PREFIX_OPCODE },
6009     { "vxorpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
6010     /* 58 */
6011     { PREFIX_TABLE (PREFIX_VEX_0F58) },
6012     { PREFIX_TABLE (PREFIX_VEX_0F59) },
6013     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
6014     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
6015     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
6016     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
6017     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
6018     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
6019     /* 60 */
6020     { "vpunpcklbw",     { XM, Vex, EXx }, PREFIX_DATA },
6021     { "vpunpcklwd",     { XM, Vex, EXx }, PREFIX_DATA },
6022     { "vpunpckldq",     { XM, Vex, EXx }, PREFIX_DATA },
6023     { "vpacksswb",      { XM, Vex, EXx }, PREFIX_DATA },
6024     { "vpcmpgtb",       { XM, Vex, EXx }, PREFIX_DATA },
6025     { "vpcmpgtw",       { XM, Vex, EXx }, PREFIX_DATA },
6026     { "vpcmpgtd",       { XM, Vex, EXx }, PREFIX_DATA },
6027     { "vpackuswb",      { XM, Vex, EXx }, PREFIX_DATA },
6028     /* 68 */
6029     { "vpunpckhbw",     { XM, Vex, EXx }, PREFIX_DATA },
6030     { "vpunpckhwd",     { XM, Vex, EXx }, PREFIX_DATA },
6031     { "vpunpckhdq",     { XM, Vex, EXx }, PREFIX_DATA },
6032     { "vpackssdw",      { XM, Vex, EXx }, PREFIX_DATA },
6033     { "vpunpcklqdq",    { XM, Vex, EXx }, PREFIX_DATA },
6034     { "vpunpckhqdq",    { XM, Vex, EXx }, PREFIX_DATA },
6035     { VEX_LEN_TABLE (VEX_LEN_0F6E) },
6036     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
6037     /* 70 */
6038     { PREFIX_TABLE (PREFIX_VEX_0F70) },
6039     { MOD_TABLE (MOD_VEX_0F71) },
6040     { MOD_TABLE (MOD_VEX_0F72) },
6041     { MOD_TABLE (MOD_VEX_0F73) },
6042     { "vpcmpeqb",       { XM, Vex, EXx }, PREFIX_DATA },
6043     { "vpcmpeqw",       { XM, Vex, EXx }, PREFIX_DATA },
6044     { "vpcmpeqd",       { XM, Vex, EXx }, PREFIX_DATA },
6045     { VEX_LEN_TABLE (VEX_LEN_0F77) },
6046     /* 78 */
6047     { Bad_Opcode },
6048     { Bad_Opcode },
6049     { Bad_Opcode },
6050     { Bad_Opcode },
6051     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
6052     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
6053     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
6054     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
6055     /* 80 */
6056     { Bad_Opcode },
6057     { Bad_Opcode },
6058     { Bad_Opcode },
6059     { Bad_Opcode },
6060     { Bad_Opcode },
6061     { Bad_Opcode },
6062     { Bad_Opcode },
6063     { Bad_Opcode },
6064     /* 88 */
6065     { Bad_Opcode },
6066     { Bad_Opcode },
6067     { Bad_Opcode },
6068     { Bad_Opcode },
6069     { Bad_Opcode },
6070     { Bad_Opcode },
6071     { Bad_Opcode },
6072     { Bad_Opcode },
6073     /* 90 */
6074     { VEX_LEN_TABLE (VEX_LEN_0F90) },
6075     { VEX_LEN_TABLE (VEX_LEN_0F91) },
6076     { VEX_LEN_TABLE (VEX_LEN_0F92) },
6077     { VEX_LEN_TABLE (VEX_LEN_0F93) },
6078     { Bad_Opcode },
6079     { Bad_Opcode },
6080     { Bad_Opcode },
6081     { Bad_Opcode },
6082     /* 98 */
6083     { VEX_LEN_TABLE (VEX_LEN_0F98) },
6084     { VEX_LEN_TABLE (VEX_LEN_0F99) },
6085     { Bad_Opcode },
6086     { Bad_Opcode },
6087     { Bad_Opcode },
6088     { Bad_Opcode },
6089     { Bad_Opcode },
6090     { Bad_Opcode },
6091     /* a0 */
6092     { Bad_Opcode },
6093     { Bad_Opcode },
6094     { Bad_Opcode },
6095     { Bad_Opcode },
6096     { Bad_Opcode },
6097     { Bad_Opcode },
6098     { Bad_Opcode },
6099     { Bad_Opcode },
6100     /* a8 */
6101     { Bad_Opcode },
6102     { Bad_Opcode },
6103     { Bad_Opcode },
6104     { Bad_Opcode },
6105     { Bad_Opcode },
6106     { Bad_Opcode },
6107     { REG_TABLE (REG_VEX_0FAE) },
6108     { Bad_Opcode },
6109     /* b0 */
6110     { Bad_Opcode },
6111     { Bad_Opcode },
6112     { Bad_Opcode },
6113     { Bad_Opcode },
6114     { Bad_Opcode },
6115     { Bad_Opcode },
6116     { Bad_Opcode },
6117     { Bad_Opcode },
6118     /* b8 */
6119     { Bad_Opcode },
6120     { Bad_Opcode },
6121     { Bad_Opcode },
6122     { Bad_Opcode },
6123     { Bad_Opcode },
6124     { Bad_Opcode },
6125     { Bad_Opcode },
6126     { Bad_Opcode },
6127     /* c0 */
6128     { Bad_Opcode },
6129     { Bad_Opcode },
6130     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
6131     { Bad_Opcode },
6132     { VEX_LEN_TABLE (VEX_LEN_0FC4) },
6133     { VEX_LEN_TABLE (VEX_LEN_0FC5) },
6134     { "vshufpX",        { XM, Vex, EXx, Ib }, PREFIX_OPCODE },
6135     { Bad_Opcode },
6136     /* c8 */
6137     { Bad_Opcode },
6138     { Bad_Opcode },
6139     { Bad_Opcode },
6140     { Bad_Opcode },
6141     { Bad_Opcode },
6142     { Bad_Opcode },
6143     { Bad_Opcode },
6144     { Bad_Opcode },
6145     /* d0 */
6146     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
6147     { "vpsrlw",         { XM, Vex, EXxmm }, PREFIX_DATA },
6148     { "vpsrld",         { XM, Vex, EXxmm }, PREFIX_DATA },
6149     { "vpsrlq",         { XM, Vex, EXxmm }, PREFIX_DATA },
6150     { "vpaddq",         { XM, Vex, EXx }, PREFIX_DATA },
6151     { "vpmullw",        { XM, Vex, EXx }, PREFIX_DATA },
6152     { VEX_LEN_TABLE (VEX_LEN_0FD6) },
6153     { MOD_TABLE (MOD_VEX_0FD7) },
6154     /* d8 */
6155     { "vpsubusb",       { XM, Vex, EXx }, PREFIX_DATA },
6156     { "vpsubusw",       { XM, Vex, EXx }, PREFIX_DATA },
6157     { "vpminub",        { XM, Vex, EXx }, PREFIX_DATA },
6158     { "vpand",          { XM, Vex, EXx }, PREFIX_DATA },
6159     { "vpaddusb",       { XM, Vex, EXx }, PREFIX_DATA },
6160     { "vpaddusw",       { XM, Vex, EXx }, PREFIX_DATA },
6161     { "vpmaxub",        { XM, Vex, EXx }, PREFIX_DATA },
6162     { "vpandn",         { XM, Vex, EXx }, PREFIX_DATA },
6163     /* e0 */
6164     { "vpavgb",         { XM, Vex, EXx }, PREFIX_DATA },
6165     { "vpsraw",         { XM, Vex, EXxmm }, PREFIX_DATA },
6166     { "vpsrad",         { XM, Vex, EXxmm }, PREFIX_DATA },
6167     { "vpavgw",         { XM, Vex, EXx }, PREFIX_DATA },
6168     { "vpmulhuw",       { XM, Vex, EXx }, PREFIX_DATA },
6169     { "vpmulhw",        { XM, Vex, EXx }, PREFIX_DATA },
6170     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
6171     { MOD_TABLE (MOD_VEX_0FE7) },
6172     /* e8 */
6173     { "vpsubsb",        { XM, Vex, EXx }, PREFIX_DATA },
6174     { "vpsubsw",        { XM, Vex, EXx }, PREFIX_DATA },
6175     { "vpminsw",        { XM, Vex, EXx }, PREFIX_DATA },
6176     { "vpor",           { XM, Vex, EXx }, PREFIX_DATA },
6177     { "vpaddsb",        { XM, Vex, EXx }, PREFIX_DATA },
6178     { "vpaddsw",        { XM, Vex, EXx }, PREFIX_DATA },
6179     { "vpmaxsw",        { XM, Vex, EXx }, PREFIX_DATA },
6180     { "vpxor",          { XM, Vex, EXx }, PREFIX_DATA },
6181     /* f0 */
6182     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
6183     { "vpsllw",         { XM, Vex, EXxmm }, PREFIX_DATA },
6184     { "vpslld",         { XM, Vex, EXxmm }, PREFIX_DATA },
6185     { "vpsllq",         { XM, Vex, EXxmm }, PREFIX_DATA },
6186     { "vpmuludq",       { XM, Vex, EXx }, PREFIX_DATA },
6187     { "vpmaddwd",       { XM, Vex, EXx }, PREFIX_DATA },
6188     { "vpsadbw",        { XM, Vex, EXx }, PREFIX_DATA },
6189     { VEX_LEN_TABLE (VEX_LEN_0FF7) },
6190     /* f8 */
6191     { "vpsubb",         { XM, Vex, EXx }, PREFIX_DATA },
6192     { "vpsubw",         { XM, Vex, EXx }, PREFIX_DATA },
6193     { "vpsubd",         { XM, Vex, EXx }, PREFIX_DATA },
6194     { "vpsubq",         { XM, Vex, EXx }, PREFIX_DATA },
6195     { "vpaddb",         { XM, Vex, EXx }, PREFIX_DATA },
6196     { "vpaddw",         { XM, Vex, EXx }, PREFIX_DATA },
6197     { "vpaddd",         { XM, Vex, EXx }, PREFIX_DATA },
6198     { Bad_Opcode },
6199   },
6200   /* VEX_0F38 */
6201   {
6202     /* 00 */
6203     { "vpshufb",        { XM, Vex, EXx }, PREFIX_DATA },
6204     { "vphaddw",        { XM, Vex, EXx }, PREFIX_DATA },
6205     { "vphaddd",        { XM, Vex, EXx }, PREFIX_DATA },
6206     { "vphaddsw",       { XM, Vex, EXx }, PREFIX_DATA },
6207     { "vpmaddubsw",     { XM, Vex, EXx }, PREFIX_DATA },
6208     { "vphsubw",        { XM, Vex, EXx }, PREFIX_DATA },
6209     { "vphsubd",        { XM, Vex, EXx }, PREFIX_DATA },
6210     { "vphsubsw",       { XM, Vex, EXx }, PREFIX_DATA },
6211     /* 08 */
6212     { "vpsignb",        { XM, Vex, EXx }, PREFIX_DATA },
6213     { "vpsignw",        { XM, Vex, EXx }, PREFIX_DATA },
6214     { "vpsignd",        { XM, Vex, EXx }, PREFIX_DATA },
6215     { "vpmulhrsw",      { XM, Vex, EXx }, PREFIX_DATA },
6216     { VEX_W_TABLE (VEX_W_0F380C) },
6217     { VEX_W_TABLE (VEX_W_0F380D) },
6218     { VEX_W_TABLE (VEX_W_0F380E) },
6219     { VEX_W_TABLE (VEX_W_0F380F) },
6220     /* 10 */
6221     { Bad_Opcode },
6222     { Bad_Opcode },
6223     { Bad_Opcode },
6224     { VEX_W_TABLE (VEX_W_0F3813) },
6225     { Bad_Opcode },
6226     { Bad_Opcode },
6227     { VEX_LEN_TABLE (VEX_LEN_0F3816) },
6228     { "vptest",         { XM, EXx }, PREFIX_DATA },
6229     /* 18 */
6230     { VEX_W_TABLE (VEX_W_0F3818) },
6231     { VEX_LEN_TABLE (VEX_LEN_0F3819) },
6232     { MOD_TABLE (MOD_VEX_0F381A) },
6233     { Bad_Opcode },
6234     { "vpabsb",         { XM, EXx }, PREFIX_DATA },
6235     { "vpabsw",         { XM, EXx }, PREFIX_DATA },
6236     { "vpabsd",         { XM, EXx }, PREFIX_DATA },
6237     { Bad_Opcode },
6238     /* 20 */
6239     { "vpmovsxbw",      { XM, EXxmmq }, PREFIX_DATA },
6240     { "vpmovsxbd",      { XM, EXxmmqd }, PREFIX_DATA },
6241     { "vpmovsxbq",      { XM, EXxmmdw }, PREFIX_DATA },
6242     { "vpmovsxwd",      { XM, EXxmmq }, PREFIX_DATA },
6243     { "vpmovsxwq",      { XM, EXxmmqd }, PREFIX_DATA },
6244     { "vpmovsxdq",      { XM, EXxmmq }, PREFIX_DATA },
6245     { Bad_Opcode },
6246     { Bad_Opcode },
6247     /* 28 */
6248     { "vpmuldq",        { XM, Vex, EXx }, PREFIX_DATA },
6249     { "vpcmpeqq",       { XM, Vex, EXx }, PREFIX_DATA },
6250     { MOD_TABLE (MOD_VEX_0F382A) },
6251     { "vpackusdw",      { XM, Vex, EXx }, PREFIX_DATA },
6252     { MOD_TABLE (MOD_VEX_0F382C) },
6253     { MOD_TABLE (MOD_VEX_0F382D) },
6254     { MOD_TABLE (MOD_VEX_0F382E) },
6255     { MOD_TABLE (MOD_VEX_0F382F) },
6256     /* 30 */
6257     { "vpmovzxbw",      { XM, EXxmmq }, PREFIX_DATA },
6258     { "vpmovzxbd",      { XM, EXxmmqd }, PREFIX_DATA },
6259     { "vpmovzxbq",      { XM, EXxmmdw }, PREFIX_DATA },
6260     { "vpmovzxwd",      { XM, EXxmmq }, PREFIX_DATA },
6261     { "vpmovzxwq",      { XM, EXxmmqd }, PREFIX_DATA },
6262     { "vpmovzxdq",      { XM, EXxmmq }, PREFIX_DATA },
6263     { VEX_LEN_TABLE (VEX_LEN_0F3836) },
6264     { "vpcmpgtq",       { XM, Vex, EXx }, PREFIX_DATA },
6265     /* 38 */
6266     { "vpminsb",        { XM, Vex, EXx }, PREFIX_DATA },
6267     { "vpminsd",        { XM, Vex, EXx }, PREFIX_DATA },
6268     { "vpminuw",        { XM, Vex, EXx }, PREFIX_DATA },
6269     { "vpminud",        { XM, Vex, EXx }, PREFIX_DATA },
6270     { "vpmaxsb",        { XM, Vex, EXx }, PREFIX_DATA },
6271     { "vpmaxsd",        { XM, Vex, EXx }, PREFIX_DATA },
6272     { "vpmaxuw",        { XM, Vex, EXx }, PREFIX_DATA },
6273     { "vpmaxud",        { XM, Vex, EXx }, PREFIX_DATA },
6274     /* 40 */
6275     { "vpmulld",        { XM, Vex, EXx }, PREFIX_DATA },
6276     { VEX_LEN_TABLE (VEX_LEN_0F3841) },
6277     { Bad_Opcode },
6278     { Bad_Opcode },
6279     { Bad_Opcode },
6280     { "vpsrlv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6281     { VEX_W_TABLE (VEX_W_0F3846) },
6282     { "vpsllv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6283     /* 48 */
6284     { Bad_Opcode },
6285     { X86_64_TABLE (X86_64_VEX_0F3849) },
6286     { Bad_Opcode },
6287     { X86_64_TABLE (X86_64_VEX_0F384B) },
6288     { Bad_Opcode },
6289     { Bad_Opcode },
6290     { Bad_Opcode },
6291     { Bad_Opcode },
6292     /* 50 */
6293     { VEX_W_TABLE (VEX_W_0F3850) },
6294     { VEX_W_TABLE (VEX_W_0F3851) },
6295     { VEX_W_TABLE (VEX_W_0F3852) },
6296     { VEX_W_TABLE (VEX_W_0F3853) },
6297     { Bad_Opcode },
6298     { Bad_Opcode },
6299     { Bad_Opcode },
6300     { Bad_Opcode },
6301     /* 58 */
6302     { VEX_W_TABLE (VEX_W_0F3858) },
6303     { VEX_W_TABLE (VEX_W_0F3859) },
6304     { MOD_TABLE (MOD_VEX_0F385A) },
6305     { Bad_Opcode },
6306     { X86_64_TABLE (X86_64_VEX_0F385C) },
6307     { Bad_Opcode },
6308     { X86_64_TABLE (X86_64_VEX_0F385E) },
6309     { Bad_Opcode },
6310     /* 60 */
6311     { Bad_Opcode },
6312     { Bad_Opcode },
6313     { Bad_Opcode },
6314     { Bad_Opcode },
6315     { Bad_Opcode },
6316     { Bad_Opcode },
6317     { Bad_Opcode },
6318     { Bad_Opcode },
6319     /* 68 */
6320     { Bad_Opcode },
6321     { Bad_Opcode },
6322     { Bad_Opcode },
6323     { Bad_Opcode },
6324     { Bad_Opcode },
6325     { Bad_Opcode },
6326     { Bad_Opcode },
6327     { Bad_Opcode },
6328     /* 70 */
6329     { Bad_Opcode },
6330     { Bad_Opcode },
6331     { Bad_Opcode },
6332     { Bad_Opcode },
6333     { Bad_Opcode },
6334     { Bad_Opcode },
6335     { Bad_Opcode },
6336     { Bad_Opcode },
6337     /* 78 */
6338     { VEX_W_TABLE (VEX_W_0F3878) },
6339     { VEX_W_TABLE (VEX_W_0F3879) },
6340     { Bad_Opcode },
6341     { Bad_Opcode },
6342     { Bad_Opcode },
6343     { Bad_Opcode },
6344     { Bad_Opcode },
6345     { Bad_Opcode },
6346     /* 80 */
6347     { Bad_Opcode },
6348     { Bad_Opcode },
6349     { Bad_Opcode },
6350     { Bad_Opcode },
6351     { Bad_Opcode },
6352     { Bad_Opcode },
6353     { Bad_Opcode },
6354     { Bad_Opcode },
6355     /* 88 */
6356     { Bad_Opcode },
6357     { Bad_Opcode },
6358     { Bad_Opcode },
6359     { Bad_Opcode },
6360     { MOD_TABLE (MOD_VEX_0F388C) },
6361     { Bad_Opcode },
6362     { MOD_TABLE (MOD_VEX_0F388E) },
6363     { Bad_Opcode },
6364     /* 90 */
6365     { "vpgatherd%DQ", { XM, MVexVSIBDWpX, VexGatherD }, PREFIX_DATA },
6366     { "vpgatherq%DQ", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6367     { "vgatherdp%XW", { XM, MVexVSIBDWpX, VexGatherD }, PREFIX_DATA },
6368     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6369     { Bad_Opcode },
6370     { Bad_Opcode },
6371     { "vfmaddsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6372     { "vfmsubadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6373     /* 98 */
6374     { "vfmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6375     { "vfmadd132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6376     { "vfmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6377     { "vfmsub132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6378     { "vfnmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6379     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6380     { "vfnmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6381     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6382     /* a0 */
6383     { Bad_Opcode },
6384     { Bad_Opcode },
6385     { Bad_Opcode },
6386     { Bad_Opcode },
6387     { Bad_Opcode },
6388     { Bad_Opcode },
6389     { "vfmaddsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6390     { "vfmsubadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6391     /* a8 */
6392     { "vfmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6393     { "vfmadd213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6394     { "vfmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6395     { "vfmsub213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6396     { "vfnmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6397     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6398     { "vfnmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6399     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6400     /* b0 */
6401     { Bad_Opcode },
6402     { Bad_Opcode },
6403     { Bad_Opcode },
6404     { Bad_Opcode },
6405     { Bad_Opcode },
6406     { Bad_Opcode },
6407     { "vfmaddsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6408     { "vfmsubadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6409     /* b8 */
6410     { "vfmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6411     { "vfmadd231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6412     { "vfmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6413     { "vfmsub231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6414     { "vfnmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6415     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6416     { "vfnmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6417     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6418     /* c0 */
6419     { Bad_Opcode },
6420     { Bad_Opcode },
6421     { Bad_Opcode },
6422     { Bad_Opcode },
6423     { Bad_Opcode },
6424     { Bad_Opcode },
6425     { Bad_Opcode },
6426     { Bad_Opcode },
6427     /* c8 */
6428     { Bad_Opcode },
6429     { Bad_Opcode },
6430     { Bad_Opcode },
6431     { Bad_Opcode },
6432     { Bad_Opcode },
6433     { Bad_Opcode },
6434     { Bad_Opcode },
6435     { VEX_W_TABLE (VEX_W_0F38CF) },
6436     /* d0 */
6437     { Bad_Opcode },
6438     { Bad_Opcode },
6439     { Bad_Opcode },
6440     { Bad_Opcode },
6441     { Bad_Opcode },
6442     { Bad_Opcode },
6443     { Bad_Opcode },
6444     { Bad_Opcode },
6445     /* d8 */
6446     { Bad_Opcode },
6447     { Bad_Opcode },
6448     { Bad_Opcode },
6449     { VEX_LEN_TABLE (VEX_LEN_0F38DB) },
6450     { "vaesenc",        { XM, Vex, EXx }, PREFIX_DATA },
6451     { "vaesenclast",    { XM, Vex, EXx }, PREFIX_DATA },
6452     { "vaesdec",        { XM, Vex, EXx }, PREFIX_DATA },
6453     { "vaesdeclast",    { XM, Vex, EXx }, PREFIX_DATA },
6454     /* e0 */
6455     { Bad_Opcode },
6456     { Bad_Opcode },
6457     { Bad_Opcode },
6458     { Bad_Opcode },
6459     { Bad_Opcode },
6460     { Bad_Opcode },
6461     { Bad_Opcode },
6462     { Bad_Opcode },
6463     /* e8 */
6464     { Bad_Opcode },
6465     { Bad_Opcode },
6466     { Bad_Opcode },
6467     { Bad_Opcode },
6468     { Bad_Opcode },
6469     { Bad_Opcode },
6470     { Bad_Opcode },
6471     { Bad_Opcode },
6472     /* f0 */
6473     { Bad_Opcode },
6474     { Bad_Opcode },
6475     { VEX_LEN_TABLE (VEX_LEN_0F38F2) },
6476     { VEX_LEN_TABLE (VEX_LEN_0F38F3) },
6477     { Bad_Opcode },
6478     { VEX_LEN_TABLE (VEX_LEN_0F38F5) },
6479     { VEX_LEN_TABLE (VEX_LEN_0F38F6) },
6480     { VEX_LEN_TABLE (VEX_LEN_0F38F7) },
6481     /* f8 */
6482     { Bad_Opcode },
6483     { Bad_Opcode },
6484     { Bad_Opcode },
6485     { Bad_Opcode },
6486     { Bad_Opcode },
6487     { Bad_Opcode },
6488     { Bad_Opcode },
6489     { Bad_Opcode },
6490   },
6491   /* VEX_0F3A */
6492   {
6493     /* 00 */
6494     { VEX_LEN_TABLE (VEX_LEN_0F3A00) },
6495     { VEX_LEN_TABLE (VEX_LEN_0F3A01) },
6496     { VEX_W_TABLE (VEX_W_0F3A02) },
6497     { Bad_Opcode },
6498     { VEX_W_TABLE (VEX_W_0F3A04) },
6499     { VEX_W_TABLE (VEX_W_0F3A05) },
6500     { VEX_LEN_TABLE (VEX_LEN_0F3A06) },
6501     { Bad_Opcode },
6502     /* 08 */
6503     { "vroundps",       { XM, EXx, Ib }, PREFIX_DATA },
6504     { "vroundpd",       { XM, EXx, Ib }, PREFIX_DATA },
6505     { "vroundss",       { XMScalar, VexScalar, EXd, Ib }, PREFIX_DATA },
6506     { "vroundsd",       { XMScalar, VexScalar, EXq, Ib }, PREFIX_DATA },
6507     { "vblendps",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6508     { "vblendpd",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6509     { "vpblendw",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6510     { "vpalignr",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6511     /* 10 */
6512     { Bad_Opcode },
6513     { Bad_Opcode },
6514     { Bad_Opcode },
6515     { Bad_Opcode },
6516     { VEX_LEN_TABLE (VEX_LEN_0F3A14) },
6517     { VEX_LEN_TABLE (VEX_LEN_0F3A15) },
6518     { VEX_LEN_TABLE (VEX_LEN_0F3A16) },
6519     { VEX_LEN_TABLE (VEX_LEN_0F3A17) },
6520     /* 18 */
6521     { VEX_LEN_TABLE (VEX_LEN_0F3A18) },
6522     { VEX_LEN_TABLE (VEX_LEN_0F3A19) },
6523     { Bad_Opcode },
6524     { Bad_Opcode },
6525     { Bad_Opcode },
6526     { VEX_W_TABLE (VEX_W_0F3A1D) },
6527     { Bad_Opcode },
6528     { Bad_Opcode },
6529     /* 20 */
6530     { VEX_LEN_TABLE (VEX_LEN_0F3A20) },
6531     { VEX_LEN_TABLE (VEX_LEN_0F3A21) },
6532     { VEX_LEN_TABLE (VEX_LEN_0F3A22) },
6533     { Bad_Opcode },
6534     { Bad_Opcode },
6535     { Bad_Opcode },
6536     { Bad_Opcode },
6537     { Bad_Opcode },
6538     /* 28 */
6539     { Bad_Opcode },
6540     { Bad_Opcode },
6541     { Bad_Opcode },
6542     { Bad_Opcode },
6543     { Bad_Opcode },
6544     { Bad_Opcode },
6545     { Bad_Opcode },
6546     { Bad_Opcode },
6547     /* 30 */
6548     { VEX_LEN_TABLE (VEX_LEN_0F3A30) },
6549     { VEX_LEN_TABLE (VEX_LEN_0F3A31) },
6550     { VEX_LEN_TABLE (VEX_LEN_0F3A32) },
6551     { VEX_LEN_TABLE (VEX_LEN_0F3A33) },
6552     { Bad_Opcode },
6553     { Bad_Opcode },
6554     { Bad_Opcode },
6555     { Bad_Opcode },
6556     /* 38 */
6557     { VEX_LEN_TABLE (VEX_LEN_0F3A38) },
6558     { VEX_LEN_TABLE (VEX_LEN_0F3A39) },
6559     { Bad_Opcode },
6560     { Bad_Opcode },
6561     { Bad_Opcode },
6562     { Bad_Opcode },
6563     { Bad_Opcode },
6564     { Bad_Opcode },
6565     /* 40 */
6566     { "vdpps",          { XM, Vex, EXx, Ib }, PREFIX_DATA },
6567     { VEX_LEN_TABLE (VEX_LEN_0F3A41) },
6568     { "vmpsadbw",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6569     { Bad_Opcode },
6570     { "vpclmulqdq",     { XM, Vex, EXx, PCLMUL }, PREFIX_DATA },
6571     { Bad_Opcode },
6572     { VEX_LEN_TABLE (VEX_LEN_0F3A46) },
6573     { Bad_Opcode },
6574     /* 48 */
6575     { "vpermil2ps",     { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6576     { "vpermil2pd",     { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6577     { VEX_W_TABLE (VEX_W_0F3A4A) },
6578     { VEX_W_TABLE (VEX_W_0F3A4B) },
6579     { VEX_W_TABLE (VEX_W_0F3A4C) },
6580     { Bad_Opcode },
6581     { Bad_Opcode },
6582     { Bad_Opcode },
6583     /* 50 */
6584     { Bad_Opcode },
6585     { Bad_Opcode },
6586     { Bad_Opcode },
6587     { Bad_Opcode },
6588     { Bad_Opcode },
6589     { Bad_Opcode },
6590     { Bad_Opcode },
6591     { Bad_Opcode },
6592     /* 58 */
6593     { Bad_Opcode },
6594     { Bad_Opcode },
6595     { Bad_Opcode },
6596     { Bad_Opcode },
6597     { "vfmaddsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6598     { "vfmaddsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6599     { "vfmsubaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6600     { "vfmsubaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6601     /* 60 */
6602     { VEX_LEN_TABLE (VEX_LEN_0F3A60) },
6603     { VEX_LEN_TABLE (VEX_LEN_0F3A61) },
6604     { VEX_LEN_TABLE (VEX_LEN_0F3A62) },
6605     { VEX_LEN_TABLE (VEX_LEN_0F3A63) },
6606     { Bad_Opcode },
6607     { Bad_Opcode },
6608     { Bad_Opcode },
6609     { Bad_Opcode },
6610     /* 68 */
6611     { "vfmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6612     { "vfmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6613     { "vfmaddss",       { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6614     { "vfmaddsd",       { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6615     { "vfmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6616     { "vfmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6617     { "vfmsubss",       { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6618     { "vfmsubsd",       { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6619     /* 70 */
6620     { Bad_Opcode },
6621     { Bad_Opcode },
6622     { Bad_Opcode },
6623     { Bad_Opcode },
6624     { Bad_Opcode },
6625     { Bad_Opcode },
6626     { Bad_Opcode },
6627     { Bad_Opcode },
6628     /* 78 */
6629     { "vfnmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6630     { "vfnmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6631     { "vfnmaddss",      { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6632     { "vfnmaddsd",      { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6633     { "vfnmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6634     { "vfnmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6635     { "vfnmsubss",      { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6636     { "vfnmsubsd",      { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6637     /* 80 */
6638     { Bad_Opcode },
6639     { Bad_Opcode },
6640     { Bad_Opcode },
6641     { Bad_Opcode },
6642     { Bad_Opcode },
6643     { Bad_Opcode },
6644     { Bad_Opcode },
6645     { Bad_Opcode },
6646     /* 88 */
6647     { Bad_Opcode },
6648     { Bad_Opcode },
6649     { Bad_Opcode },
6650     { Bad_Opcode },
6651     { Bad_Opcode },
6652     { Bad_Opcode },
6653     { Bad_Opcode },
6654     { Bad_Opcode },
6655     /* 90 */
6656     { Bad_Opcode },
6657     { Bad_Opcode },
6658     { Bad_Opcode },
6659     { Bad_Opcode },
6660     { Bad_Opcode },
6661     { Bad_Opcode },
6662     { Bad_Opcode },
6663     { Bad_Opcode },
6664     /* 98 */
6665     { Bad_Opcode },
6666     { Bad_Opcode },
6667     { Bad_Opcode },
6668     { Bad_Opcode },
6669     { Bad_Opcode },
6670     { Bad_Opcode },
6671     { Bad_Opcode },
6672     { Bad_Opcode },
6673     /* a0 */
6674     { Bad_Opcode },
6675     { Bad_Opcode },
6676     { Bad_Opcode },
6677     { Bad_Opcode },
6678     { Bad_Opcode },
6679     { Bad_Opcode },
6680     { Bad_Opcode },
6681     { Bad_Opcode },
6682     /* a8 */
6683     { Bad_Opcode },
6684     { Bad_Opcode },
6685     { Bad_Opcode },
6686     { Bad_Opcode },
6687     { Bad_Opcode },
6688     { Bad_Opcode },
6689     { Bad_Opcode },
6690     { Bad_Opcode },
6691     /* b0 */
6692     { Bad_Opcode },
6693     { Bad_Opcode },
6694     { Bad_Opcode },
6695     { Bad_Opcode },
6696     { Bad_Opcode },
6697     { Bad_Opcode },
6698     { Bad_Opcode },
6699     { Bad_Opcode },
6700     /* b8 */
6701     { Bad_Opcode },
6702     { Bad_Opcode },
6703     { Bad_Opcode },
6704     { Bad_Opcode },
6705     { Bad_Opcode },
6706     { Bad_Opcode },
6707     { Bad_Opcode },
6708     { Bad_Opcode },
6709     /* c0 */
6710     { Bad_Opcode },
6711     { Bad_Opcode },
6712     { Bad_Opcode },
6713     { Bad_Opcode },
6714     { Bad_Opcode },
6715     { Bad_Opcode },
6716     { Bad_Opcode },
6717     { Bad_Opcode },
6718     /* c8 */
6719     { Bad_Opcode },
6720     { Bad_Opcode },
6721     { Bad_Opcode },
6722     { Bad_Opcode },
6723     { Bad_Opcode },
6724     { Bad_Opcode },
6725     { VEX_W_TABLE (VEX_W_0F3ACE) },
6726     { VEX_W_TABLE (VEX_W_0F3ACF) },
6727     /* d0 */
6728     { Bad_Opcode },
6729     { Bad_Opcode },
6730     { Bad_Opcode },
6731     { Bad_Opcode },
6732     { Bad_Opcode },
6733     { Bad_Opcode },
6734     { Bad_Opcode },
6735     { Bad_Opcode },
6736     /* d8 */
6737     { Bad_Opcode },
6738     { Bad_Opcode },
6739     { Bad_Opcode },
6740     { Bad_Opcode },
6741     { Bad_Opcode },
6742     { Bad_Opcode },
6743     { Bad_Opcode },
6744     { VEX_LEN_TABLE (VEX_LEN_0F3ADF) },
6745     /* e0 */
6746     { Bad_Opcode },
6747     { Bad_Opcode },
6748     { Bad_Opcode },
6749     { Bad_Opcode },
6750     { Bad_Opcode },
6751     { Bad_Opcode },
6752     { Bad_Opcode },
6753     { Bad_Opcode },
6754     /* e8 */
6755     { Bad_Opcode },
6756     { Bad_Opcode },
6757     { Bad_Opcode },
6758     { Bad_Opcode },
6759     { Bad_Opcode },
6760     { Bad_Opcode },
6761     { Bad_Opcode },
6762     { Bad_Opcode },
6763     /* f0 */
6764     { VEX_LEN_TABLE (VEX_LEN_0F3AF0) },
6765     { Bad_Opcode },
6766     { Bad_Opcode },
6767     { Bad_Opcode },
6768     { Bad_Opcode },
6769     { Bad_Opcode },
6770     { Bad_Opcode },
6771     { Bad_Opcode },
6772     /* f8 */
6773     { Bad_Opcode },
6774     { Bad_Opcode },
6775     { Bad_Opcode },
6776     { Bad_Opcode },
6777     { Bad_Opcode },
6778     { Bad_Opcode },
6779     { Bad_Opcode },
6780     { Bad_Opcode },
6781   },
6782 };
6783
6784 #include "i386-dis-evex.h"
6785
6786 static const struct dis386 vex_len_table[][2] = {
6787   /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */
6788   {
6789     { "vmovlpX",        { XM, Vex, EXq }, 0 },
6790   },
6791
6792   /* VEX_LEN_0F12_P_0_M_1 */
6793   {
6794     { "vmovhlps",       { XM, Vex, EXq }, 0 },
6795   },
6796
6797   /* VEX_LEN_0F13_M_0 */
6798   {
6799     { "vmovlpX",        { EXq, XM }, PREFIX_OPCODE },
6800   },
6801
6802   /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */
6803   {
6804     { "vmovhpX",        { XM, Vex, EXq }, 0 },
6805   },
6806
6807   /* VEX_LEN_0F16_P_0_M_1 */
6808   {
6809     { "vmovlhps",       { XM, Vex, EXq }, 0 },
6810   },
6811
6812   /* VEX_LEN_0F17_M_0 */
6813   {
6814     { "vmovhpX",        { EXq, XM }, PREFIX_OPCODE },
6815   },
6816
6817   /* VEX_LEN_0F41 */
6818   {
6819     { Bad_Opcode },
6820     { MOD_TABLE (MOD_VEX_0F41_L_1) },
6821   },
6822
6823   /* VEX_LEN_0F42 */
6824   {
6825     { Bad_Opcode },
6826     { MOD_TABLE (MOD_VEX_0F42_L_1) },
6827   },
6828
6829   /* VEX_LEN_0F44 */
6830   {
6831     { MOD_TABLE (MOD_VEX_0F44_L_0) },
6832   },
6833
6834   /* VEX_LEN_0F45 */
6835   {
6836     { Bad_Opcode },
6837     { MOD_TABLE (MOD_VEX_0F45_L_1) },
6838   },
6839
6840   /* VEX_LEN_0F46 */
6841   {
6842     { Bad_Opcode },
6843     { MOD_TABLE (MOD_VEX_0F46_L_1) },
6844   },
6845
6846   /* VEX_LEN_0F47 */
6847   {
6848     { Bad_Opcode },
6849     { MOD_TABLE (MOD_VEX_0F47_L_1) },
6850   },
6851
6852   /* VEX_LEN_0F4A */
6853   {
6854     { Bad_Opcode },
6855     { MOD_TABLE (MOD_VEX_0F4A_L_1) },
6856   },
6857
6858   /* VEX_LEN_0F4B */
6859   {
6860     { Bad_Opcode },
6861     { MOD_TABLE (MOD_VEX_0F4B_L_1) },
6862   },
6863
6864   /* VEX_LEN_0F6E */
6865   {
6866     { "vmovK",          { XMScalar, Edq }, PREFIX_DATA },
6867   },
6868
6869   /* VEX_LEN_0F77 */
6870   {
6871     { "vzeroupper",     { XX }, 0 },
6872     { "vzeroall",       { XX }, 0 },
6873   },
6874
6875   /* VEX_LEN_0F7E_P_1 */
6876   {
6877     { "vmovq",          { XMScalar, EXq }, 0 },
6878   },
6879
6880   /* VEX_LEN_0F7E_P_2 */
6881   {
6882     { "vmovK",          { Edq, XMScalar }, 0 },
6883   },
6884
6885   /* VEX_LEN_0F90 */
6886   {
6887     { VEX_W_TABLE (VEX_W_0F90_L_0) },
6888   },
6889
6890   /* VEX_LEN_0F91 */
6891   {
6892     { MOD_TABLE (MOD_VEX_0F91_L_0) },
6893   },
6894
6895   /* VEX_LEN_0F92 */
6896   {
6897     { MOD_TABLE (MOD_VEX_0F92_L_0) },
6898   },
6899
6900   /* VEX_LEN_0F93 */
6901   {
6902     { MOD_TABLE (MOD_VEX_0F93_L_0) },
6903   },
6904
6905   /* VEX_LEN_0F98 */
6906   {
6907     { MOD_TABLE (MOD_VEX_0F98_L_0) },
6908   },
6909
6910   /* VEX_LEN_0F99 */
6911   {
6912     { MOD_TABLE (MOD_VEX_0F99_L_0) },
6913   },
6914
6915   /* VEX_LEN_0FAE_R_2_M_0 */
6916   {
6917     { "vldmxcsr",       { Md }, 0 },
6918   },
6919
6920   /* VEX_LEN_0FAE_R_3_M_0 */
6921   {
6922     { "vstmxcsr",       { Md }, 0 },
6923   },
6924
6925   /* VEX_LEN_0FC4 */
6926   {
6927     { "vpinsrw",        { XM, Vex, Edw, Ib }, PREFIX_DATA },
6928   },
6929
6930   /* VEX_LEN_0FC5 */
6931   {
6932     { "vpextrw",        { Gd, XS, Ib }, PREFIX_DATA },
6933   },
6934
6935   /* VEX_LEN_0FD6 */
6936   {
6937     { "vmovq",          { EXqS, XMScalar }, PREFIX_DATA },
6938   },
6939
6940   /* VEX_LEN_0FF7 */
6941   {
6942     { "vmaskmovdqu",    { XM, XS }, PREFIX_DATA },
6943   },
6944
6945   /* VEX_LEN_0F3816 */
6946   {
6947     { Bad_Opcode },
6948     { VEX_W_TABLE (VEX_W_0F3816_L_1) },
6949   },
6950
6951   /* VEX_LEN_0F3819 */
6952   {
6953     { Bad_Opcode },
6954     { VEX_W_TABLE (VEX_W_0F3819_L_1) },
6955   },
6956
6957   /* VEX_LEN_0F381A_M_0 */
6958   {
6959     { Bad_Opcode },
6960     { VEX_W_TABLE (VEX_W_0F381A_M_0_L_1) },
6961   },
6962
6963   /* VEX_LEN_0F3836 */
6964   {
6965     { Bad_Opcode },
6966     { VEX_W_TABLE (VEX_W_0F3836) },
6967   },
6968
6969   /* VEX_LEN_0F3841 */
6970   {
6971     { "vphminposuw",    { XM, EXx }, PREFIX_DATA },
6972   },
6973
6974    /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_0 */
6975   {
6976     { "ldtilecfg", { M }, 0 },
6977   },
6978
6979   /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0 */
6980   {
6981     { "tilerelease", { Skip_MODRM }, 0 },
6982   },
6983
6984   /* VEX_LEN_0F3849_X86_64_P_2_W_0_M_0 */
6985   {
6986     { "sttilecfg", { M }, 0 },
6987   },
6988
6989   /* VEX_LEN_0F3849_X86_64_P_3_W_0_M_0 */
6990   {
6991     { "tilezero", { TMM, Skip_MODRM }, 0 },
6992   },
6993
6994   /* VEX_LEN_0F384B_X86_64_P_1_W_0_M_0 */
6995   {
6996     { "tilestored", { MVexSIBMEM, TMM }, 0 },
6997   },
6998   /* VEX_LEN_0F384B_X86_64_P_2_W_0_M_0 */
6999   {
7000     { "tileloaddt1", { TMM, MVexSIBMEM }, 0 },
7001   },
7002
7003   /* VEX_LEN_0F384B_X86_64_P_3_W_0_M_0 */
7004   {
7005     { "tileloadd", { TMM, MVexSIBMEM }, 0 },
7006   },
7007
7008   /* VEX_LEN_0F385A_M_0 */
7009   {
7010     { Bad_Opcode },
7011     { VEX_W_TABLE (VEX_W_0F385A_M_0_L_0) },
7012   },
7013
7014   /* VEX_LEN_0F385C_X86_64_P_1_W_0_M_0 */
7015   {
7016     { "tdpbf16ps", { TMM, EXtmm, VexTmm }, 0 },
7017   },
7018
7019   /* VEX_LEN_0F385E_X86_64_P_0_W_0_M_0 */
7020   {
7021     { "tdpbuud", {TMM, EXtmm, VexTmm }, 0 },
7022   },
7023
7024   /* VEX_LEN_0F385E_X86_64_P_1_W_0_M_0 */
7025   {
7026     { "tdpbsud", {TMM, EXtmm, VexTmm }, 0 },
7027   },
7028
7029   /* VEX_LEN_0F385E_X86_64_P_2_W_0_M_0 */
7030   {
7031     { "tdpbusd", {TMM, EXtmm, VexTmm }, 0 },
7032   },
7033
7034   /* VEX_LEN_0F385E_X86_64_P_3_W_0_M_0 */
7035   {
7036     { "tdpbssd", {TMM, EXtmm, VexTmm }, 0 },
7037   },
7038
7039   /* VEX_LEN_0F38DB */
7040   {
7041     { "vaesimc",        { XM, EXx }, PREFIX_DATA },
7042   },
7043
7044   /* VEX_LEN_0F38F2 */
7045   {
7046     { "andnS",          { Gdq, VexGdq, Edq }, PREFIX_OPCODE },
7047   },
7048
7049   /* VEX_LEN_0F38F3 */
7050   {
7051     { REG_TABLE(REG_VEX_0F38F3_L_0) },
7052   },
7053
7054   /* VEX_LEN_0F38F5 */
7055   {
7056     { PREFIX_TABLE(PREFIX_VEX_0F38F5_L_0) },
7057   },
7058
7059   /* VEX_LEN_0F38F6 */
7060   {
7061     { PREFIX_TABLE(PREFIX_VEX_0F38F6_L_0) },
7062   },
7063
7064   /* VEX_LEN_0F38F7 */
7065   {
7066     { PREFIX_TABLE(PREFIX_VEX_0F38F7_L_0) },
7067   },
7068
7069   /* VEX_LEN_0F3A00 */
7070   {
7071     { Bad_Opcode },
7072     { VEX_W_TABLE (VEX_W_0F3A00_L_1) },
7073   },
7074
7075   /* VEX_LEN_0F3A01 */
7076   {
7077     { Bad_Opcode },
7078     { VEX_W_TABLE (VEX_W_0F3A01_L_1) },
7079   },
7080
7081   /* VEX_LEN_0F3A06 */
7082   {
7083     { Bad_Opcode },
7084     { VEX_W_TABLE (VEX_W_0F3A06_L_1) },
7085   },
7086
7087   /* VEX_LEN_0F3A14 */
7088   {
7089     { "vpextrb",        { Edb, XM, Ib }, PREFIX_DATA },
7090   },
7091
7092   /* VEX_LEN_0F3A15 */
7093   {
7094     { "vpextrw",        { Edw, XM, Ib }, PREFIX_DATA },
7095   },
7096
7097   /* VEX_LEN_0F3A16  */
7098   {
7099     { "vpextrK",        { Edq, XM, Ib }, PREFIX_DATA },
7100   },
7101
7102   /* VEX_LEN_0F3A17 */
7103   {
7104     { "vextractps",     { Ed, XM, Ib }, PREFIX_DATA },
7105   },
7106
7107   /* VEX_LEN_0F3A18 */
7108   {
7109     { Bad_Opcode },
7110     { VEX_W_TABLE (VEX_W_0F3A18_L_1) },
7111   },
7112
7113   /* VEX_LEN_0F3A19 */
7114   {
7115     { Bad_Opcode },
7116     { VEX_W_TABLE (VEX_W_0F3A19_L_1) },
7117   },
7118
7119   /* VEX_LEN_0F3A20 */
7120   {
7121     { "vpinsrb",        { XM, Vex, Edb, Ib }, PREFIX_DATA },
7122   },
7123
7124   /* VEX_LEN_0F3A21 */
7125   {
7126     { "vinsertps",      { XM, Vex, EXd, Ib }, PREFIX_DATA },
7127   },
7128
7129   /* VEX_LEN_0F3A22 */
7130   {
7131     { "vpinsrK",        { XM, Vex, Edq, Ib }, PREFIX_DATA },
7132   },
7133
7134   /* VEX_LEN_0F3A30 */
7135   {
7136     { MOD_TABLE (MOD_VEX_0F3A30_L_0) },
7137   },
7138
7139   /* VEX_LEN_0F3A31 */
7140   {
7141     { MOD_TABLE (MOD_VEX_0F3A31_L_0) },
7142   },
7143
7144   /* VEX_LEN_0F3A32 */
7145   {
7146     { MOD_TABLE (MOD_VEX_0F3A32_L_0) },
7147   },
7148
7149   /* VEX_LEN_0F3A33 */
7150   {
7151     { MOD_TABLE (MOD_VEX_0F3A33_L_0) },
7152   },
7153
7154   /* VEX_LEN_0F3A38 */
7155   {
7156     { Bad_Opcode },
7157     { VEX_W_TABLE (VEX_W_0F3A38_L_1) },
7158   },
7159
7160   /* VEX_LEN_0F3A39 */
7161   {
7162     { Bad_Opcode },
7163     { VEX_W_TABLE (VEX_W_0F3A39_L_1) },
7164   },
7165
7166   /* VEX_LEN_0F3A41 */
7167   {
7168     { "vdppd",          { XM, Vex, EXx, Ib }, PREFIX_DATA },
7169   },
7170
7171   /* VEX_LEN_0F3A46 */
7172   {
7173     { Bad_Opcode },
7174     { VEX_W_TABLE (VEX_W_0F3A46_L_1) },
7175   },
7176
7177   /* VEX_LEN_0F3A60 */
7178   {
7179     { "vpcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7180   },
7181
7182   /* VEX_LEN_0F3A61 */
7183   {
7184     { "vpcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7185   },
7186
7187   /* VEX_LEN_0F3A62 */
7188   {
7189     { "vpcmpistrm",     { XM, EXx, Ib }, PREFIX_DATA },
7190   },
7191
7192   /* VEX_LEN_0F3A63 */
7193   {
7194     { "vpcmpistri",     { XM, EXx, Ib }, PREFIX_DATA },
7195   },
7196
7197   /* VEX_LEN_0F3ADF */
7198   {
7199     { "vaeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
7200   },
7201
7202   /* VEX_LEN_0F3AF0 */
7203   {
7204     { PREFIX_TABLE (PREFIX_VEX_0F3AF0_L_0) },
7205   },
7206
7207   /* VEX_LEN_0FXOP_08_85 */
7208   {
7209     { VEX_W_TABLE (VEX_W_0FXOP_08_85_L_0) },
7210   },
7211
7212   /* VEX_LEN_0FXOP_08_86 */
7213   {
7214     { VEX_W_TABLE (VEX_W_0FXOP_08_86_L_0) },
7215   },
7216
7217   /* VEX_LEN_0FXOP_08_87 */
7218   {
7219     { VEX_W_TABLE (VEX_W_0FXOP_08_87_L_0) },
7220   },
7221
7222   /* VEX_LEN_0FXOP_08_8E */
7223   {
7224     { VEX_W_TABLE (VEX_W_0FXOP_08_8E_L_0) },
7225   },
7226
7227   /* VEX_LEN_0FXOP_08_8F */
7228   {
7229     { VEX_W_TABLE (VEX_W_0FXOP_08_8F_L_0) },
7230   },
7231
7232   /* VEX_LEN_0FXOP_08_95 */
7233   {
7234     { VEX_W_TABLE (VEX_W_0FXOP_08_95_L_0) },
7235   },
7236
7237   /* VEX_LEN_0FXOP_08_96 */
7238   {
7239     { VEX_W_TABLE (VEX_W_0FXOP_08_96_L_0) },
7240   },
7241
7242   /* VEX_LEN_0FXOP_08_97 */
7243   {
7244     { VEX_W_TABLE (VEX_W_0FXOP_08_97_L_0) },
7245   },
7246
7247   /* VEX_LEN_0FXOP_08_9E */
7248   {
7249     { VEX_W_TABLE (VEX_W_0FXOP_08_9E_L_0) },
7250   },
7251
7252   /* VEX_LEN_0FXOP_08_9F */
7253   {
7254     { VEX_W_TABLE (VEX_W_0FXOP_08_9F_L_0) },
7255   },
7256
7257   /* VEX_LEN_0FXOP_08_A3 */
7258   {
7259     { "vpperm",         { XM, Vex, EXx, XMVexI4 }, 0 },
7260   },
7261
7262   /* VEX_LEN_0FXOP_08_A6 */
7263   {
7264     { VEX_W_TABLE (VEX_W_0FXOP_08_A6_L_0) },
7265   },
7266
7267   /* VEX_LEN_0FXOP_08_B6 */
7268   {
7269     { VEX_W_TABLE (VEX_W_0FXOP_08_B6_L_0) },
7270   },
7271
7272   /* VEX_LEN_0FXOP_08_C0 */
7273   {
7274     { VEX_W_TABLE (VEX_W_0FXOP_08_C0_L_0) },
7275   },
7276
7277   /* VEX_LEN_0FXOP_08_C1 */
7278   {
7279     { VEX_W_TABLE (VEX_W_0FXOP_08_C1_L_0) },
7280   },
7281
7282   /* VEX_LEN_0FXOP_08_C2 */
7283   {
7284     { VEX_W_TABLE (VEX_W_0FXOP_08_C2_L_0) },
7285   },
7286
7287   /* VEX_LEN_0FXOP_08_C3 */
7288   {
7289     { VEX_W_TABLE (VEX_W_0FXOP_08_C3_L_0) },
7290   },
7291
7292   /* VEX_LEN_0FXOP_08_CC */
7293   {
7294     { VEX_W_TABLE (VEX_W_0FXOP_08_CC_L_0) },
7295   },
7296
7297   /* VEX_LEN_0FXOP_08_CD */
7298   {
7299     { VEX_W_TABLE (VEX_W_0FXOP_08_CD_L_0) },
7300   },
7301
7302   /* VEX_LEN_0FXOP_08_CE */
7303   {
7304     { VEX_W_TABLE (VEX_W_0FXOP_08_CE_L_0) },
7305   },
7306
7307   /* VEX_LEN_0FXOP_08_CF */
7308   {
7309     { VEX_W_TABLE (VEX_W_0FXOP_08_CF_L_0) },
7310   },
7311
7312   /* VEX_LEN_0FXOP_08_EC */
7313   {
7314     { VEX_W_TABLE (VEX_W_0FXOP_08_EC_L_0) },
7315   },
7316
7317   /* VEX_LEN_0FXOP_08_ED */
7318   {
7319     { VEX_W_TABLE (VEX_W_0FXOP_08_ED_L_0) },
7320   },
7321
7322   /* VEX_LEN_0FXOP_08_EE */
7323   {
7324     { VEX_W_TABLE (VEX_W_0FXOP_08_EE_L_0) },
7325   },
7326
7327   /* VEX_LEN_0FXOP_08_EF */
7328   {
7329     { VEX_W_TABLE (VEX_W_0FXOP_08_EF_L_0) },
7330   },
7331
7332   /* VEX_LEN_0FXOP_09_01 */
7333   {
7334     { REG_TABLE (REG_XOP_09_01_L_0) },
7335   },
7336
7337   /* VEX_LEN_0FXOP_09_02 */
7338   {
7339     { REG_TABLE (REG_XOP_09_02_L_0) },
7340   },
7341
7342   /* VEX_LEN_0FXOP_09_12_M_1 */
7343   {
7344     { REG_TABLE (REG_XOP_09_12_M_1_L_0) },
7345   },
7346
7347   /* VEX_LEN_0FXOP_09_82_W_0 */
7348   {
7349     { "vfrczss",        { XM, EXd }, 0 },
7350   },
7351
7352   /* VEX_LEN_0FXOP_09_83_W_0 */
7353   {
7354     { "vfrczsd",        { XM, EXq }, 0 },
7355   },
7356
7357   /* VEX_LEN_0FXOP_09_90 */
7358   {
7359     { "vprotb",         { XM, EXx, VexW }, 0 },
7360   },
7361
7362   /* VEX_LEN_0FXOP_09_91 */
7363   {
7364     { "vprotw",         { XM, EXx, VexW }, 0 },
7365   },
7366
7367   /* VEX_LEN_0FXOP_09_92 */
7368   {
7369     { "vprotd",         { XM, EXx, VexW }, 0 },
7370   },
7371
7372   /* VEX_LEN_0FXOP_09_93 */
7373   {
7374     { "vprotq",         { XM, EXx, VexW }, 0 },
7375   },
7376
7377   /* VEX_LEN_0FXOP_09_94 */
7378   {
7379     { "vpshlb",         { XM, EXx, VexW }, 0 },
7380   },
7381
7382   /* VEX_LEN_0FXOP_09_95 */
7383   {
7384     { "vpshlw",         { XM, EXx, VexW }, 0 },
7385   },
7386
7387   /* VEX_LEN_0FXOP_09_96 */
7388   {
7389     { "vpshld",         { XM, EXx, VexW }, 0 },
7390   },
7391
7392   /* VEX_LEN_0FXOP_09_97 */
7393   {
7394     { "vpshlq",         { XM, EXx, VexW }, 0 },
7395   },
7396
7397   /* VEX_LEN_0FXOP_09_98 */
7398   {
7399     { "vpshab",         { XM, EXx, VexW }, 0 },
7400   },
7401
7402   /* VEX_LEN_0FXOP_09_99 */
7403   {
7404     { "vpshaw",         { XM, EXx, VexW }, 0 },
7405   },
7406
7407   /* VEX_LEN_0FXOP_09_9A */
7408   {
7409     { "vpshad",         { XM, EXx, VexW }, 0 },
7410   },
7411
7412   /* VEX_LEN_0FXOP_09_9B */
7413   {
7414     { "vpshaq",         { XM, EXx, VexW }, 0 },
7415   },
7416
7417   /* VEX_LEN_0FXOP_09_C1 */
7418   {
7419     { VEX_W_TABLE (VEX_W_0FXOP_09_C1_L_0) },
7420   },
7421
7422   /* VEX_LEN_0FXOP_09_C2 */
7423   {
7424     { VEX_W_TABLE (VEX_W_0FXOP_09_C2_L_0) },
7425   },
7426
7427   /* VEX_LEN_0FXOP_09_C3 */
7428   {
7429     { VEX_W_TABLE (VEX_W_0FXOP_09_C3_L_0) },
7430   },
7431
7432   /* VEX_LEN_0FXOP_09_C6 */
7433   {
7434     { VEX_W_TABLE (VEX_W_0FXOP_09_C6_L_0) },
7435   },
7436
7437   /* VEX_LEN_0FXOP_09_C7 */
7438   {
7439     { VEX_W_TABLE (VEX_W_0FXOP_09_C7_L_0) },
7440   },
7441
7442   /* VEX_LEN_0FXOP_09_CB */
7443   {
7444     { VEX_W_TABLE (VEX_W_0FXOP_09_CB_L_0) },
7445   },
7446
7447   /* VEX_LEN_0FXOP_09_D1 */
7448   {
7449     { VEX_W_TABLE (VEX_W_0FXOP_09_D1_L_0) },
7450   },
7451
7452   /* VEX_LEN_0FXOP_09_D2 */
7453   {
7454     { VEX_W_TABLE (VEX_W_0FXOP_09_D2_L_0) },
7455   },
7456
7457   /* VEX_LEN_0FXOP_09_D3 */
7458   {
7459     { VEX_W_TABLE (VEX_W_0FXOP_09_D3_L_0) },
7460   },
7461
7462   /* VEX_LEN_0FXOP_09_D6 */
7463   {
7464     { VEX_W_TABLE (VEX_W_0FXOP_09_D6_L_0) },
7465   },
7466
7467   /* VEX_LEN_0FXOP_09_D7 */
7468   {
7469     { VEX_W_TABLE (VEX_W_0FXOP_09_D7_L_0) },
7470   },
7471
7472   /* VEX_LEN_0FXOP_09_DB */
7473   {
7474     { VEX_W_TABLE (VEX_W_0FXOP_09_DB_L_0) },
7475   },
7476
7477   /* VEX_LEN_0FXOP_09_E1 */
7478   {
7479     { VEX_W_TABLE (VEX_W_0FXOP_09_E1_L_0) },
7480   },
7481
7482   /* VEX_LEN_0FXOP_09_E2 */
7483   {
7484     { VEX_W_TABLE (VEX_W_0FXOP_09_E2_L_0) },
7485   },
7486
7487   /* VEX_LEN_0FXOP_09_E3 */
7488   {
7489     { VEX_W_TABLE (VEX_W_0FXOP_09_E3_L_0) },
7490   },
7491
7492   /* VEX_LEN_0FXOP_0A_12 */
7493   {
7494     { REG_TABLE (REG_XOP_0A_12_L_0) },
7495   },
7496 };
7497
7498 #include "i386-dis-evex-len.h"
7499
7500 static const struct dis386 vex_w_table[][2] = {
7501   {
7502     /* VEX_W_0F41_L_1_M_1 */
7503     { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_M_1_W_0) },
7504     { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_M_1_W_1) },
7505   },
7506   {
7507     /* VEX_W_0F42_L_1_M_1 */
7508     { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_M_1_W_0) },
7509     { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_M_1_W_1) },
7510   },
7511   {
7512     /* VEX_W_0F44_L_0_M_1 */
7513     { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_M_1_W_0) },
7514     { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_M_1_W_1) },
7515   },
7516   {
7517     /* VEX_W_0F45_L_1_M_1 */
7518     { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_M_1_W_0) },
7519     { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_M_1_W_1) },
7520   },
7521   {
7522     /* VEX_W_0F46_L_1_M_1 */
7523     { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_M_1_W_0) },
7524     { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_M_1_W_1) },
7525   },
7526   {
7527     /* VEX_W_0F47_L_1_M_1 */
7528     { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_M_1_W_0) },
7529     { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_M_1_W_1) },
7530   },
7531   {
7532     /* VEX_W_0F4A_L_1_M_1 */
7533     { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_M_1_W_0) },
7534     { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_M_1_W_1) },
7535   },
7536   {
7537     /* VEX_W_0F4B_L_1_M_1 */
7538     { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_M_1_W_0) },
7539     { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_M_1_W_1) },
7540   },
7541   {
7542     /* VEX_W_0F90_L_0 */
7543     { PREFIX_TABLE (PREFIX_VEX_0F90_L_0_W_0) },
7544     { PREFIX_TABLE (PREFIX_VEX_0F90_L_0_W_1) },
7545   },
7546   {
7547     /* VEX_W_0F91_L_0_M_0 */
7548     { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_M_0_W_0) },
7549     { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_M_0_W_1) },
7550   },
7551   {
7552     /* VEX_W_0F92_L_0_M_1 */
7553     { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_M_1_W_0) },
7554     { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_M_1_W_1) },
7555   },
7556   {
7557     /* VEX_W_0F93_L_0_M_1 */
7558     { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_M_1_W_0) },
7559     { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_M_1_W_1) },
7560   },
7561   {
7562     /* VEX_W_0F98_L_0_M_1 */
7563     { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_M_1_W_0) },
7564     { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_M_1_W_1) },
7565   },
7566   {
7567     /* VEX_W_0F99_L_0_M_1 */
7568     { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_M_1_W_0) },
7569     { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_M_1_W_1) },
7570   },
7571   {
7572     /* VEX_W_0F380C  */
7573     { "vpermilps",      { XM, Vex, EXx }, PREFIX_DATA },
7574   },
7575   {
7576     /* VEX_W_0F380D  */
7577     { "vpermilpd",      { XM, Vex, EXx }, PREFIX_DATA },
7578   },
7579   {
7580     /* VEX_W_0F380E  */
7581     { "vtestps",        { XM, EXx }, PREFIX_DATA },
7582   },
7583   {
7584     /* VEX_W_0F380F  */
7585     { "vtestpd",        { XM, EXx }, PREFIX_DATA },
7586   },
7587   {
7588     /* VEX_W_0F3813 */
7589     { "vcvtph2ps", { XM, EXxmmq }, PREFIX_DATA },
7590   },
7591   {
7592     /* VEX_W_0F3816_L_1  */
7593     { "vpermps",        { XM, Vex, EXx }, PREFIX_DATA },
7594   },
7595   {
7596     /* VEX_W_0F3818 */
7597     { "vbroadcastss",   { XM, EXd }, PREFIX_DATA },
7598   },
7599   {
7600     /* VEX_W_0F3819_L_1 */
7601     { "vbroadcastsd",   { XM, EXq }, PREFIX_DATA },
7602   },
7603   {
7604     /* VEX_W_0F381A_M_0_L_1 */
7605     { "vbroadcastf128", { XM, Mxmm }, PREFIX_DATA },
7606   },
7607   {
7608     /* VEX_W_0F382C_M_0 */
7609     { "vmaskmovps",     { XM, Vex, Mx }, PREFIX_DATA },
7610   },
7611   {
7612     /* VEX_W_0F382D_M_0 */
7613     { "vmaskmovpd",     { XM, Vex, Mx }, PREFIX_DATA },
7614   },
7615   {
7616     /* VEX_W_0F382E_M_0 */
7617     { "vmaskmovps",     { Mx, Vex, XM }, PREFIX_DATA },
7618   },
7619   {
7620     /* VEX_W_0F382F_M_0 */
7621     { "vmaskmovpd",     { Mx, Vex, XM }, PREFIX_DATA },
7622   },
7623   {
7624     /* VEX_W_0F3836  */
7625     { "vpermd",         { XM, Vex, EXx }, PREFIX_DATA },
7626   },
7627   {
7628     /* VEX_W_0F3846 */
7629     { "vpsravd",        { XM, Vex, EXx }, PREFIX_DATA },
7630   },
7631   {
7632     /* VEX_W_0F3849_X86_64_P_0 */
7633     { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_0_W_0) },
7634   },
7635   {
7636     /* VEX_W_0F3849_X86_64_P_2 */
7637     { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_2_W_0) },
7638   },
7639   {
7640     /* VEX_W_0F3849_X86_64_P_3 */
7641     { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_3_W_0) },
7642   },
7643   {
7644     /* VEX_W_0F384B_X86_64_P_1 */
7645     { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_1_W_0) },
7646   },
7647   {
7648     /* VEX_W_0F384B_X86_64_P_2 */
7649     { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_2_W_0) },
7650   },
7651   {
7652     /* VEX_W_0F384B_X86_64_P_3 */
7653     { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_3_W_0) },
7654   },
7655   {
7656     /* VEX_W_0F3850 */
7657     { "%XV vpdpbusd",   { XM, Vex, EXx }, 0 },
7658   },
7659   {
7660     /* VEX_W_0F3851 */
7661     { "%XV vpdpbusds",  { XM, Vex, EXx }, 0 },
7662   },
7663   {
7664     /* VEX_W_0F3852 */
7665     { "%XV vpdpwssd",   { XM, Vex, EXx }, 0 },
7666   },
7667   {
7668     /* VEX_W_0F3853 */
7669     { "%XV vpdpwssds",  { XM, Vex, EXx }, 0 },
7670   },
7671   {
7672     /* VEX_W_0F3858 */
7673     { "vpbroadcastd", { XM, EXd }, PREFIX_DATA },
7674   },
7675   {
7676     /* VEX_W_0F3859 */
7677     { "vpbroadcastq", { XM, EXq }, PREFIX_DATA },
7678   },
7679   {
7680     /* VEX_W_0F385A_M_0_L_0 */
7681     { "vbroadcasti128", { XM, Mxmm }, PREFIX_DATA },
7682   },
7683   {
7684     /* VEX_W_0F385C_X86_64_P_1 */
7685     { MOD_TABLE (MOD_VEX_0F385C_X86_64_P_1_W_0) },
7686   },
7687   {
7688     /* VEX_W_0F385E_X86_64_P_0 */
7689     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_0_W_0) },
7690   },
7691   {
7692     /* VEX_W_0F385E_X86_64_P_1 */
7693     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_1_W_0) },
7694   },
7695   {
7696     /* VEX_W_0F385E_X86_64_P_2 */
7697     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_2_W_0) },
7698   },
7699   {
7700     /* VEX_W_0F385E_X86_64_P_3 */
7701     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_3_W_0) },
7702   },
7703   {
7704     /* VEX_W_0F3878 */
7705     { "vpbroadcastb",   { XM, EXb }, PREFIX_DATA },
7706   },
7707   {
7708     /* VEX_W_0F3879 */
7709     { "vpbroadcastw",   { XM, EXw }, PREFIX_DATA },
7710   },
7711   {
7712     /* VEX_W_0F38CF */
7713     { "vgf2p8mulb", { XM, Vex, EXx }, PREFIX_DATA },
7714   },
7715   {
7716     /* VEX_W_0F3A00_L_1 */
7717     { Bad_Opcode },
7718     { "vpermq",         { XM, EXx, Ib }, PREFIX_DATA },
7719   },
7720   {
7721     /* VEX_W_0F3A01_L_1 */
7722     { Bad_Opcode },
7723     { "vpermpd",        { XM, EXx, Ib }, PREFIX_DATA },
7724   },
7725   {
7726     /* VEX_W_0F3A02 */
7727     { "vpblendd",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
7728   },
7729   {
7730     /* VEX_W_0F3A04 */
7731     { "vpermilps",      { XM, EXx, Ib }, PREFIX_DATA },
7732   },
7733   {
7734     /* VEX_W_0F3A05 */
7735     { "vpermilpd",      { XM, EXx, Ib }, PREFIX_DATA },
7736   },
7737   {
7738     /* VEX_W_0F3A06_L_1 */
7739     { "vperm2f128",     { XM, Vex, EXx, Ib }, PREFIX_DATA },
7740   },
7741   {
7742     /* VEX_W_0F3A18_L_1 */
7743     { "vinsertf128",    { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7744   },
7745   {
7746     /* VEX_W_0F3A19_L_1 */
7747     { "vextractf128",   { EXxmm, XM, Ib }, PREFIX_DATA },
7748   },
7749   {
7750     /* VEX_W_0F3A1D */
7751     { "vcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, PREFIX_DATA },
7752   },
7753   {
7754     /* VEX_W_0F3A38_L_1 */
7755     { "vinserti128",    { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7756   },
7757   {
7758     /* VEX_W_0F3A39_L_1 */
7759     { "vextracti128",   { EXxmm, XM, Ib }, PREFIX_DATA },
7760   },
7761   {
7762     /* VEX_W_0F3A46_L_1 */
7763     { "vperm2i128",     { XM, Vex, EXx, Ib }, PREFIX_DATA },
7764   },
7765   {
7766     /* VEX_W_0F3A4A */
7767     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7768   },
7769   {
7770     /* VEX_W_0F3A4B */
7771     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7772   },
7773   {
7774     /* VEX_W_0F3A4C */
7775     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7776   },
7777   {
7778     /* VEX_W_0F3ACE */
7779     { Bad_Opcode },
7780     { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7781   },
7782   {
7783     /* VEX_W_0F3ACF */
7784     { Bad_Opcode },
7785     { "vgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, PREFIX_DATA },
7786   },
7787   /* VEX_W_0FXOP_08_85_L_0 */
7788   {
7789     { "vpmacssww",      { XM, Vex, EXx, XMVexI4 }, 0 },
7790   },
7791   /* VEX_W_0FXOP_08_86_L_0 */
7792   {
7793     { "vpmacsswd",      { XM, Vex, EXx, XMVexI4 }, 0 },
7794   },
7795   /* VEX_W_0FXOP_08_87_L_0 */
7796   {
7797     { "vpmacssdql",     { XM, Vex, EXx, XMVexI4 }, 0 },
7798   },
7799   /* VEX_W_0FXOP_08_8E_L_0 */
7800   {
7801     { "vpmacssdd",      { XM, Vex, EXx, XMVexI4 }, 0 },
7802   },
7803   /* VEX_W_0FXOP_08_8F_L_0 */
7804   {
7805     { "vpmacssdqh",     { XM, Vex, EXx, XMVexI4 }, 0 },
7806   },
7807   /* VEX_W_0FXOP_08_95_L_0 */
7808   {
7809     { "vpmacsww",       { XM, Vex, EXx, XMVexI4 }, 0 },
7810   },
7811   /* VEX_W_0FXOP_08_96_L_0 */
7812   {
7813     { "vpmacswd",       { XM, Vex, EXx, XMVexI4 }, 0 },
7814   },
7815   /* VEX_W_0FXOP_08_97_L_0 */
7816   {
7817     { "vpmacsdql",      { XM, Vex, EXx, XMVexI4 }, 0 },
7818   },
7819   /* VEX_W_0FXOP_08_9E_L_0 */
7820   {
7821     { "vpmacsdd",       { XM, Vex, EXx, XMVexI4 }, 0 },
7822   },
7823   /* VEX_W_0FXOP_08_9F_L_0 */
7824   {
7825     { "vpmacsdqh",      { XM, Vex, EXx, XMVexI4 }, 0 },
7826   },
7827   /* VEX_W_0FXOP_08_A6_L_0 */
7828   {
7829     { "vpmadcsswd",     { XM, Vex, EXx, XMVexI4 }, 0 },
7830   },
7831   /* VEX_W_0FXOP_08_B6_L_0 */
7832   {
7833     { "vpmadcswd",      { XM, Vex, EXx, XMVexI4 }, 0 },
7834   },
7835   /* VEX_W_0FXOP_08_C0_L_0 */
7836   {
7837     { "vprotb",         { XM, EXx, Ib }, 0 },
7838   },
7839   /* VEX_W_0FXOP_08_C1_L_0 */
7840   {
7841     { "vprotw",         { XM, EXx, Ib }, 0 },
7842   },
7843   /* VEX_W_0FXOP_08_C2_L_0 */
7844   {
7845     { "vprotd",         { XM, EXx, Ib }, 0 },
7846   },
7847   /* VEX_W_0FXOP_08_C3_L_0 */
7848   {
7849     { "vprotq",         { XM, EXx, Ib }, 0 },
7850   },
7851   /* VEX_W_0FXOP_08_CC_L_0 */
7852   {
7853      { "vpcomb",        { XM, Vex, EXx, VPCOM }, 0 },
7854   },
7855   /* VEX_W_0FXOP_08_CD_L_0 */
7856   {
7857      { "vpcomw",        { XM, Vex, EXx, VPCOM }, 0 },
7858   },
7859   /* VEX_W_0FXOP_08_CE_L_0 */
7860   {
7861      { "vpcomd",        { XM, Vex, EXx, VPCOM }, 0 },
7862   },
7863   /* VEX_W_0FXOP_08_CF_L_0 */
7864   {
7865      { "vpcomq",        { XM, Vex, EXx, VPCOM }, 0 },
7866   },
7867   /* VEX_W_0FXOP_08_EC_L_0 */
7868   {
7869      { "vpcomub",       { XM, Vex, EXx, VPCOM }, 0 },
7870   },
7871   /* VEX_W_0FXOP_08_ED_L_0 */
7872   {
7873      { "vpcomuw",       { XM, Vex, EXx, VPCOM }, 0 },
7874   },
7875   /* VEX_W_0FXOP_08_EE_L_0 */
7876   {
7877      { "vpcomud",       { XM, Vex, EXx, VPCOM }, 0 },
7878   },
7879   /* VEX_W_0FXOP_08_EF_L_0 */
7880   {
7881      { "vpcomuq",       { XM, Vex, EXx, VPCOM }, 0 },
7882   },
7883   /* VEX_W_0FXOP_09_80 */
7884   {
7885     { "vfrczps",        { XM, EXx }, 0 },
7886   },
7887   /* VEX_W_0FXOP_09_81 */
7888   {
7889     { "vfrczpd",        { XM, EXx }, 0 },
7890   },
7891   /* VEX_W_0FXOP_09_82 */
7892   {
7893     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_82_W_0) },
7894   },
7895   /* VEX_W_0FXOP_09_83 */
7896   {
7897     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_83_W_0) },
7898   },
7899   /* VEX_W_0FXOP_09_C1_L_0 */
7900   {
7901     { "vphaddbw",       { XM, EXxmm }, 0 },
7902   },
7903   /* VEX_W_0FXOP_09_C2_L_0 */
7904   {
7905     { "vphaddbd",       { XM, EXxmm }, 0 },
7906   },
7907   /* VEX_W_0FXOP_09_C3_L_0 */
7908   {
7909     { "vphaddbq",       { XM, EXxmm }, 0 },
7910   },
7911   /* VEX_W_0FXOP_09_C6_L_0 */
7912   {
7913     { "vphaddwd",       { XM, EXxmm }, 0 },
7914   },
7915   /* VEX_W_0FXOP_09_C7_L_0 */
7916   {
7917     { "vphaddwq",       { XM, EXxmm }, 0 },
7918   },
7919   /* VEX_W_0FXOP_09_CB_L_0 */
7920   {
7921     { "vphadddq",       { XM, EXxmm }, 0 },
7922   },
7923   /* VEX_W_0FXOP_09_D1_L_0 */
7924   {
7925     { "vphaddubw",      { XM, EXxmm }, 0 },
7926   },
7927   /* VEX_W_0FXOP_09_D2_L_0 */
7928   {
7929     { "vphaddubd",      { XM, EXxmm }, 0 },
7930   },
7931   /* VEX_W_0FXOP_09_D3_L_0 */
7932   {
7933     { "vphaddubq",      { XM, EXxmm }, 0 },
7934   },
7935   /* VEX_W_0FXOP_09_D6_L_0 */
7936   {
7937     { "vphadduwd",      { XM, EXxmm }, 0 },
7938   },
7939   /* VEX_W_0FXOP_09_D7_L_0 */
7940   {
7941     { "vphadduwq",      { XM, EXxmm }, 0 },
7942   },
7943   /* VEX_W_0FXOP_09_DB_L_0 */
7944   {
7945     { "vphaddudq",      { XM, EXxmm }, 0 },
7946   },
7947   /* VEX_W_0FXOP_09_E1_L_0 */
7948   {
7949     { "vphsubbw",       { XM, EXxmm }, 0 },
7950   },
7951   /* VEX_W_0FXOP_09_E2_L_0 */
7952   {
7953     { "vphsubwd",       { XM, EXxmm }, 0 },
7954   },
7955   /* VEX_W_0FXOP_09_E3_L_0 */
7956   {
7957     { "vphsubdq",       { XM, EXxmm }, 0 },
7958   },
7959
7960 #include "i386-dis-evex-w.h"
7961 };
7962
7963 static const struct dis386 mod_table[][2] = {
7964   {
7965     /* MOD_62_32BIT */
7966     { "bound{S|}",      { Gv, Ma }, 0 },
7967     { EVEX_TABLE (EVEX_0F) },
7968   },
7969   {
7970     /* MOD_8D */
7971     { "leaS",           { Gv, M }, 0 },
7972   },
7973   {
7974     /* MOD_C4_32BIT */
7975     { "lesS",           { Gv, Mp }, 0 },
7976     { VEX_C4_TABLE (VEX_0F) },
7977   },
7978   {
7979     /* MOD_C5_32BIT */
7980     { "ldsS",           { Gv, Mp }, 0 },
7981     { VEX_C5_TABLE (VEX_0F) },
7982   },
7983   {
7984     /* MOD_C6_REG_7 */
7985     { Bad_Opcode },
7986     { RM_TABLE (RM_C6_REG_7) },
7987   },
7988   {
7989     /* MOD_C7_REG_7 */
7990     { Bad_Opcode },
7991     { RM_TABLE (RM_C7_REG_7) },
7992   },
7993   {
7994     /* MOD_FF_REG_3 */
7995     { "{l|}call^", { indirEp }, 0 },
7996   },
7997   {
7998     /* MOD_FF_REG_5 */
7999     { "{l|}jmp^", { indirEp }, 0 },
8000   },
8001   {
8002     /* MOD_0F01_REG_0 */
8003     { X86_64_TABLE (X86_64_0F01_REG_0) },
8004     { RM_TABLE (RM_0F01_REG_0) },
8005   },
8006   {
8007     /* MOD_0F01_REG_1 */
8008     { X86_64_TABLE (X86_64_0F01_REG_1) },
8009     { RM_TABLE (RM_0F01_REG_1) },
8010   },
8011   {
8012     /* MOD_0F01_REG_2 */
8013     { X86_64_TABLE (X86_64_0F01_REG_2) },
8014     { RM_TABLE (RM_0F01_REG_2) },
8015   },
8016   {
8017     /* MOD_0F01_REG_3 */
8018     { X86_64_TABLE (X86_64_0F01_REG_3) },
8019     { RM_TABLE (RM_0F01_REG_3) },
8020   },
8021   {
8022     /* MOD_0F01_REG_5 */
8023     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) },
8024     { RM_TABLE (RM_0F01_REG_5_MOD_3) },
8025   },
8026   {
8027     /* MOD_0F01_REG_7 */
8028     { "invlpg",         { Mb }, 0 },
8029     { RM_TABLE (RM_0F01_REG_7_MOD_3) },
8030   },
8031   {
8032     /* MOD_0F12_PREFIX_0 */
8033     { "movlpX",         { XM, EXq }, 0 },
8034     { "movhlps",        { XM, EXq }, 0 },
8035   },
8036   {
8037     /* MOD_0F12_PREFIX_2 */
8038     { "movlpX", { XM, EXq }, 0 },
8039   },
8040   {
8041     /* MOD_0F13 */
8042     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
8043   },
8044   {
8045     /* MOD_0F16_PREFIX_0 */
8046     { "movhpX",         { XM, EXq }, 0 },
8047     { "movlhps",        { XM, EXq }, 0 },
8048   },
8049   {
8050     /* MOD_0F16_PREFIX_2 */
8051     { "movhpX", { XM, EXq }, 0 },
8052   },
8053   {
8054     /* MOD_0F17 */
8055     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
8056   },
8057   {
8058     /* MOD_0F18_REG_0 */
8059     { "prefetchnta",    { Mb }, 0 },
8060     { "nopQ",           { Ev }, 0 },
8061   },
8062   {
8063     /* MOD_0F18_REG_1 */
8064     { "prefetcht0",     { Mb }, 0 },
8065     { "nopQ",           { Ev }, 0 },
8066   },
8067   {
8068     /* MOD_0F18_REG_2 */
8069     { "prefetcht1",     { Mb }, 0 },
8070     { "nopQ",           { Ev }, 0 },
8071   },
8072   {
8073     /* MOD_0F18_REG_3 */
8074     { "prefetcht2",     { Mb }, 0 },
8075     { "nopQ",           { Ev }, 0 },
8076   },
8077   {
8078     /* MOD_0F1A_PREFIX_0 */
8079     { "bndldx",         { Gbnd, Mv_bnd }, 0 },
8080     { "nopQ",           { Ev }, 0 },
8081   },
8082   {
8083     /* MOD_0F1B_PREFIX_0 */
8084     { "bndstx",         { Mv_bnd, Gbnd }, 0 },
8085     { "nopQ",           { Ev }, 0 },
8086   },
8087   {
8088     /* MOD_0F1B_PREFIX_1 */
8089     { "bndmk",          { Gbnd, Mv_bnd }, 0 },
8090     { "nopQ",           { Ev }, PREFIX_IGNORED },
8091   },
8092   {
8093     /* MOD_0F1C_PREFIX_0 */
8094     { REG_TABLE (REG_0F1C_P_0_MOD_0) },
8095     { "nopQ",           { Ev }, 0 },
8096   },
8097   {
8098     /* MOD_0F1E_PREFIX_1 */
8099     { "nopQ",           { Ev }, PREFIX_IGNORED },
8100     { REG_TABLE (REG_0F1E_P_1_MOD_3) },
8101   },
8102   {
8103     /* MOD_0F2B_PREFIX_0 */
8104     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
8105   },
8106   {
8107     /* MOD_0F2B_PREFIX_1 */
8108     {"movntss",         { Md, XM }, PREFIX_OPCODE },
8109   },
8110   {
8111     /* MOD_0F2B_PREFIX_2 */
8112     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
8113   },
8114   {
8115     /* MOD_0F2B_PREFIX_3 */
8116     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
8117   },
8118   {
8119     /* MOD_0F50 */
8120     { Bad_Opcode },
8121     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
8122   },
8123   {
8124     /* MOD_0F71 */
8125     { Bad_Opcode },
8126     { REG_TABLE (REG_0F71_MOD_0) },
8127   },
8128   {
8129     /* MOD_0F72 */
8130     { Bad_Opcode },
8131     { REG_TABLE (REG_0F72_MOD_0) },
8132   },
8133   {
8134     /* MOD_0F73 */
8135     { Bad_Opcode },
8136     { REG_TABLE (REG_0F73_MOD_0) },
8137   },
8138   {
8139     /* MOD_0FAE_REG_0 */
8140     { "fxsave",         { FXSAVE }, 0 },
8141     { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) },
8142   },
8143   {
8144     /* MOD_0FAE_REG_1 */
8145     { "fxrstor",        { FXSAVE }, 0 },
8146     { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) },
8147   },
8148   {
8149     /* MOD_0FAE_REG_2 */
8150     { "ldmxcsr",        { Md }, 0 },
8151     { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) },
8152   },
8153   {
8154     /* MOD_0FAE_REG_3 */
8155     { "stmxcsr",        { Md }, 0 },
8156     { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) },
8157   },
8158   {
8159     /* MOD_0FAE_REG_4 */
8160     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) },
8161     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) },
8162   },
8163   {
8164     /* MOD_0FAE_REG_5 */
8165     { "xrstor",         { FXSAVE }, PREFIX_OPCODE },
8166     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) },
8167   },
8168   {
8169     /* MOD_0FAE_REG_6 */
8170     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) },
8171     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) },
8172   },
8173   {
8174     /* MOD_0FAE_REG_7 */
8175     { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) },
8176     { RM_TABLE (RM_0FAE_REG_7_MOD_3) },
8177   },
8178   {
8179     /* MOD_0FB2 */
8180     { "lssS",           { Gv, Mp }, 0 },
8181   },
8182   {
8183     /* MOD_0FB4 */
8184     { "lfsS",           { Gv, Mp }, 0 },
8185   },
8186   {
8187     /* MOD_0FB5 */
8188     { "lgsS",           { Gv, Mp }, 0 },
8189   },
8190   {
8191     /* MOD_0FC3 */
8192     { "movntiS", { Edq, Gdq }, PREFIX_OPCODE },
8193   },
8194   {
8195     /* MOD_0FC7_REG_3 */
8196     { "xrstors",        { FXSAVE }, 0 },
8197   },
8198   {
8199     /* MOD_0FC7_REG_4 */
8200     { "xsavec",         { FXSAVE }, 0 },
8201   },
8202   {
8203     /* MOD_0FC7_REG_5 */
8204     { "xsaves",         { FXSAVE }, 0 },
8205   },
8206   {
8207     /* MOD_0FC7_REG_6 */
8208     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) },
8209     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) }
8210   },
8211   {
8212     /* MOD_0FC7_REG_7 */
8213     { "vmptrst",        { Mq }, 0 },
8214     { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) }
8215   },
8216   {
8217     /* MOD_0FD7 */
8218     { Bad_Opcode },
8219     { "pmovmskb",       { Gdq, MS }, 0 },
8220   },
8221   {
8222     /* MOD_0FE7_PREFIX_2 */
8223     { "movntdq",        { Mx, XM }, 0 },
8224   },
8225   {
8226     /* MOD_0FF0_PREFIX_3 */
8227     { "lddqu",          { XM, M }, 0 },
8228   },
8229   {
8230     /* MOD_0F382A */
8231     { "movntdqa",       { XM, Mx }, PREFIX_DATA },
8232   },
8233   {
8234     /* MOD_0F38DC_PREFIX_1 */
8235     { "aesenc128kl",    { XM, M }, 0 },
8236     { "loadiwkey",      { XM, EXx }, 0 },
8237   },
8238   {
8239     /* MOD_0F38DD_PREFIX_1 */
8240     { "aesdec128kl",    { XM, M }, 0 },
8241   },
8242   {
8243     /* MOD_0F38DE_PREFIX_1 */
8244     { "aesenc256kl",    { XM, M }, 0 },
8245   },
8246   {
8247     /* MOD_0F38DF_PREFIX_1 */
8248     { "aesdec256kl",    { XM, M }, 0 },
8249   },
8250   {
8251     /* MOD_0F38F5 */
8252     { "wrussK",         { M, Gdq }, PREFIX_DATA },
8253   },
8254   {
8255     /* MOD_0F38F6_PREFIX_0 */
8256     { "wrssK",          { M, Gdq }, PREFIX_OPCODE },
8257   },
8258   {
8259     /* MOD_0F38F8_PREFIX_1 */
8260     { "enqcmds",        { Gva, M }, PREFIX_OPCODE },
8261   },
8262   {
8263     /* MOD_0F38F8_PREFIX_2 */
8264     { "movdir64b",      { Gva, M }, PREFIX_OPCODE },
8265   },
8266   {
8267     /* MOD_0F38F8_PREFIX_3 */
8268     { "enqcmd",         { Gva, M }, PREFIX_OPCODE },
8269   },
8270   {
8271     /* MOD_0F38F9 */
8272     { "movdiri",        { Edq, Gdq }, PREFIX_OPCODE },
8273   },
8274   {
8275     /* MOD_0F38FA_PREFIX_1 */
8276     { Bad_Opcode },
8277     { "encodekey128", { Gd, Ed }, 0 },
8278   },
8279   {
8280     /* MOD_0F38FB_PREFIX_1 */
8281     { Bad_Opcode },
8282     { "encodekey256", { Gd, Ed }, 0 },
8283   },
8284   {
8285     /* MOD_0F3A0F_PREFIX_1 */
8286     { Bad_Opcode },
8287     { REG_TABLE (REG_0F3A0F_PREFIX_1_MOD_3) },
8288   },
8289   {
8290     /* MOD_VEX_0F12_PREFIX_0 */
8291     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
8292     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
8293   },
8294   {
8295     /* MOD_VEX_0F12_PREFIX_2 */
8296     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0) },
8297   },
8298   {
8299     /* MOD_VEX_0F13 */
8300     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
8301   },
8302   {
8303     /* MOD_VEX_0F16_PREFIX_0 */
8304     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
8305     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
8306   },
8307   {
8308     /* MOD_VEX_0F16_PREFIX_2 */
8309     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0) },
8310   },
8311   {
8312     /* MOD_VEX_0F17 */
8313     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
8314   },
8315   {
8316     /* MOD_VEX_0F2B */
8317     { "vmovntpX",       { Mx, XM }, PREFIX_OPCODE },
8318   },
8319   {
8320     /* MOD_VEX_0F41_L_1 */
8321     { Bad_Opcode },
8322     { VEX_W_TABLE (VEX_W_0F41_L_1_M_1) },
8323   },
8324   {
8325     /* MOD_VEX_0F42_L_1 */
8326     { Bad_Opcode },
8327     { VEX_W_TABLE (VEX_W_0F42_L_1_M_1) },
8328   },
8329   {
8330     /* MOD_VEX_0F44_L_0 */
8331     { Bad_Opcode },
8332     { VEX_W_TABLE (VEX_W_0F44_L_0_M_1) },
8333   },
8334   {
8335     /* MOD_VEX_0F45_L_1 */
8336     { Bad_Opcode },
8337     { VEX_W_TABLE (VEX_W_0F45_L_1_M_1) },
8338   },
8339   {
8340     /* MOD_VEX_0F46_L_1 */
8341     { Bad_Opcode },
8342     { VEX_W_TABLE (VEX_W_0F46_L_1_M_1) },
8343   },
8344   {
8345     /* MOD_VEX_0F47_L_1 */
8346     { Bad_Opcode },
8347     { VEX_W_TABLE (VEX_W_0F47_L_1_M_1) },
8348   },
8349   {
8350     /* MOD_VEX_0F4A_L_1 */
8351     { Bad_Opcode },
8352     { VEX_W_TABLE (VEX_W_0F4A_L_1_M_1) },
8353   },
8354   {
8355     /* MOD_VEX_0F4B_L_1 */
8356     { Bad_Opcode },
8357     { VEX_W_TABLE (VEX_W_0F4B_L_1_M_1) },
8358   },
8359   {
8360     /* MOD_VEX_0F50 */
8361     { Bad_Opcode },
8362     { "vmovmskpX",      { Gdq, XS }, PREFIX_OPCODE },
8363   },
8364   {
8365     /* MOD_VEX_0F71 */
8366     { Bad_Opcode },
8367     { REG_TABLE (REG_VEX_0F71_M_0) },
8368   },
8369   {
8370     /* MOD_VEX_0F72 */
8371     { Bad_Opcode },
8372     { REG_TABLE (REG_VEX_0F72_M_0) },
8373   },
8374   {
8375     /* MOD_VEX_0F73 */
8376     { Bad_Opcode },
8377     { REG_TABLE (REG_VEX_0F73_M_0) },
8378   },
8379   {
8380     /* MOD_VEX_0F91_L_0 */
8381     { VEX_W_TABLE (VEX_W_0F91_L_0_M_0) },
8382   },
8383   {
8384     /* MOD_VEX_0F92_L_0 */
8385     { Bad_Opcode },
8386     { VEX_W_TABLE (VEX_W_0F92_L_0_M_1) },
8387   },
8388   {
8389     /* MOD_VEX_0F93_L_0 */
8390     { Bad_Opcode },
8391     { VEX_W_TABLE (VEX_W_0F93_L_0_M_1) },
8392   },
8393   {
8394     /* MOD_VEX_0F98_L_0 */
8395     { Bad_Opcode },
8396     { VEX_W_TABLE (VEX_W_0F98_L_0_M_1) },
8397   },
8398   {
8399     /* MOD_VEX_0F99_L_0 */
8400     { Bad_Opcode },
8401     { VEX_W_TABLE (VEX_W_0F99_L_0_M_1) },
8402   },
8403   {
8404     /* MOD_VEX_0FAE_REG_2 */
8405     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
8406   },
8407   {
8408     /* MOD_VEX_0FAE_REG_3 */
8409     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
8410   },
8411   {
8412     /* MOD_VEX_0FD7 */
8413     { Bad_Opcode },
8414     { "vpmovmskb",      { Gdq, XS }, PREFIX_DATA },
8415   },
8416   {
8417     /* MOD_VEX_0FE7 */
8418     { "vmovntdq",       { Mx, XM }, PREFIX_DATA },
8419   },
8420   {
8421     /* MOD_VEX_0FF0_PREFIX_3 */
8422     { "vlddqu",         { XM, M }, 0 },
8423   },
8424   {
8425     /* MOD_VEX_0F381A */
8426     { VEX_LEN_TABLE (VEX_LEN_0F381A_M_0) },
8427   },
8428   {
8429     /* MOD_VEX_0F382A */
8430     { "vmovntdqa",      { XM, Mx }, PREFIX_DATA },
8431   },
8432   {
8433     /* MOD_VEX_0F382C */
8434     { VEX_W_TABLE (VEX_W_0F382C_M_0) },
8435   },
8436   {
8437     /* MOD_VEX_0F382D */
8438     { VEX_W_TABLE (VEX_W_0F382D_M_0) },
8439   },
8440   {
8441     /* MOD_VEX_0F382E */
8442     { VEX_W_TABLE (VEX_W_0F382E_M_0) },
8443   },
8444   {
8445     /* MOD_VEX_0F382F */
8446     { VEX_W_TABLE (VEX_W_0F382F_M_0) },
8447   },
8448   {
8449     /* MOD_VEX_0F3849_X86_64_P_0_W_0 */
8450     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0) },
8451     { REG_TABLE (REG_VEX_0F3849_X86_64_P_0_W_0_M_1) },
8452   },
8453   {
8454     /* MOD_VEX_0F3849_X86_64_P_2_W_0 */
8455     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0) },
8456   },
8457   {
8458     /* MOD_VEX_0F3849_X86_64_P_3_W_0 */
8459     { Bad_Opcode },
8460     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0) },
8461   },
8462   {
8463     /* MOD_VEX_0F384B_X86_64_P_1_W_0 */
8464     { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0) },
8465   },
8466   {
8467     /* MOD_VEX_0F384B_X86_64_P_2_W_0 */
8468     { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0) },
8469   },
8470   {
8471     /* MOD_VEX_0F384B_X86_64_P_3_W_0 */
8472     { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0) },
8473   },
8474   {
8475     /* MOD_VEX_0F385A */
8476     { VEX_LEN_TABLE (VEX_LEN_0F385A_M_0) },
8477   },
8478   {
8479     /* MOD_VEX_0F385C_X86_64_P_1_W_0 */
8480     { Bad_Opcode },
8481     { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0) },
8482   },
8483   {
8484     /* MOD_VEX_0F385E_X86_64_P_0_W_0 */
8485     { Bad_Opcode },
8486     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0) },
8487   },
8488   {
8489     /* MOD_VEX_0F385E_X86_64_P_1_W_0 */
8490     { Bad_Opcode },
8491     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0) },
8492   },
8493   {
8494     /* MOD_VEX_0F385E_X86_64_P_2_W_0 */
8495     { Bad_Opcode },
8496     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0) },
8497   },
8498   {
8499     /* MOD_VEX_0F385E_X86_64_P_3_W_0 */
8500     { Bad_Opcode },
8501     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0) },
8502   },
8503   {
8504     /* MOD_VEX_0F388C */
8505     { "vpmaskmov%DQ",   { XM, Vex, Mx }, PREFIX_DATA },
8506   },
8507   {
8508     /* MOD_VEX_0F388E */
8509     { "vpmaskmov%DQ",   { Mx, Vex, XM }, PREFIX_DATA },
8510   },
8511   {
8512     /* MOD_VEX_0F3A30_L_0 */
8513     { Bad_Opcode },
8514     { "kshiftr%BW",     { MaskG, MaskE, Ib }, PREFIX_DATA },
8515   },
8516   {
8517     /* MOD_VEX_0F3A31_L_0 */
8518     { Bad_Opcode },
8519     { "kshiftr%DQ",     { MaskG, MaskE, Ib }, PREFIX_DATA },
8520   },
8521   {
8522     /* MOD_VEX_0F3A32_L_0 */
8523     { Bad_Opcode },
8524     { "kshiftl%BW",     { MaskG, MaskE, Ib }, PREFIX_DATA },
8525   },
8526   {
8527     /* MOD_VEX_0F3A33_L_0 */
8528     { Bad_Opcode },
8529     { "kshiftl%DQ",     { MaskG, MaskE, Ib }, PREFIX_DATA },
8530   },
8531   {
8532     /* MOD_XOP_09_12 */
8533     { Bad_Opcode },
8534     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_12_M_1) },
8535   },
8536
8537 #include "i386-dis-evex-mod.h"
8538 };
8539
8540 static const struct dis386 rm_table[][8] = {
8541   {
8542     /* RM_C6_REG_7 */
8543     { "xabort",         { Skip_MODRM, Ib }, 0 },
8544   },
8545   {
8546     /* RM_C7_REG_7 */
8547     { "xbeginT",        { Skip_MODRM, Jdqw }, 0 },
8548   },
8549   {
8550     /* RM_0F01_REG_0 */
8551     { "enclv",          { Skip_MODRM }, 0 },
8552     { "vmcall",         { Skip_MODRM }, 0 },
8553     { "vmlaunch",       { Skip_MODRM }, 0 },
8554     { "vmresume",       { Skip_MODRM }, 0 },
8555     { "vmxoff",         { Skip_MODRM }, 0 },
8556     { "pconfig",        { Skip_MODRM }, 0 },
8557   },
8558   {
8559     /* RM_0F01_REG_1 */
8560     { "monitor",        { { OP_Monitor, 0 } }, 0 },
8561     { "mwait",          { { OP_Mwait, 0 } }, 0 },
8562     { "clac",           { Skip_MODRM }, 0 },
8563     { "stac",           { Skip_MODRM }, 0 },
8564     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_4) },
8565     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_5) },
8566     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_6) },
8567     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_7) },
8568   },
8569   {
8570     /* RM_0F01_REG_2 */
8571     { "xgetbv",         { Skip_MODRM }, 0 },
8572     { "xsetbv",         { Skip_MODRM }, 0 },
8573     { Bad_Opcode },
8574     { Bad_Opcode },
8575     { "vmfunc",         { Skip_MODRM }, 0 },
8576     { "xend",           { Skip_MODRM }, 0 },
8577     { "xtest",          { Skip_MODRM }, 0 },
8578     { "enclu",          { Skip_MODRM }, 0 },
8579   },
8580   {
8581     /* RM_0F01_REG_3 */
8582     { "vmrun",          { Skip_MODRM }, 0 },
8583     { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) },
8584     { "vmload",         { Skip_MODRM }, 0 },
8585     { "vmsave",         { Skip_MODRM }, 0 },
8586     { "stgi",           { Skip_MODRM }, 0 },
8587     { "clgi",           { Skip_MODRM }, 0 },
8588     { "skinit",         { Skip_MODRM }, 0 },
8589     { "invlpga",        { Skip_MODRM }, 0 },
8590   },
8591   {
8592     /* RM_0F01_REG_5_MOD_3 */
8593     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) },
8594     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) },
8595     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) },
8596     { Bad_Opcode },
8597     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_4) },
8598     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_5) },
8599     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_6) },
8600     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_7) },
8601   },
8602   {
8603     /* RM_0F01_REG_7_MOD_3 */
8604     { "swapgs",         { Skip_MODRM }, 0  },
8605     { "rdtscp",         { Skip_MODRM }, 0  },
8606     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) },
8607     { "mwaitx",         { { OP_Mwait, eBX_reg } }, PREFIX_OPCODE },
8608     { "clzero",         { Skip_MODRM }, 0  },
8609     { "rdpru",          { Skip_MODRM }, 0  },
8610     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_6) },
8611     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_7) },
8612   },
8613   {
8614     /* RM_0F1E_P_1_MOD_3_REG_7 */
8615     { "nopQ",           { Ev }, PREFIX_IGNORED },
8616     { "nopQ",           { Ev }, PREFIX_IGNORED },
8617     { "endbr64",        { Skip_MODRM }, 0 },
8618     { "endbr32",        { Skip_MODRM }, 0 },
8619     { "nopQ",           { Ev }, PREFIX_IGNORED },
8620     { "nopQ",           { Ev }, PREFIX_IGNORED },
8621     { "nopQ",           { Ev }, PREFIX_IGNORED },
8622     { "nopQ",           { Ev }, PREFIX_IGNORED },
8623   },
8624   {
8625     /* RM_0FAE_REG_6_MOD_3 */
8626     { "mfence",         { Skip_MODRM }, 0 },
8627   },
8628   {
8629     /* RM_0FAE_REG_7_MOD_3 */
8630     { "sfence",         { Skip_MODRM }, 0 },
8631   },
8632   {
8633     /* RM_0F3A0F_P_1_MOD_3_REG_0 */
8634     { "hreset",         { Skip_MODRM, Ib }, 0 },
8635   },
8636   {
8637     /* RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0 */
8638     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0) },
8639   },
8640 };
8641
8642 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
8643
8644 /* We use the high bit to indicate different name for the same
8645    prefix.  */
8646 #define REP_PREFIX      (0xf3 | 0x100)
8647 #define XACQUIRE_PREFIX (0xf2 | 0x200)
8648 #define XRELEASE_PREFIX (0xf3 | 0x400)
8649 #define BND_PREFIX      (0xf2 | 0x400)
8650 #define NOTRACK_PREFIX  (0x3e | 0x100)
8651
8652 /* Remember if the current op is a jump instruction.  */
8653 static bool op_is_jump = false;
8654
8655 static int
8656 ckprefix (void)
8657 {
8658   int newrex, i, length;
8659   rex = 0;
8660   prefixes = 0;
8661   used_prefixes = 0;
8662   rex_used = 0;
8663   evex_used = 0;
8664   last_lock_prefix = -1;
8665   last_repz_prefix = -1;
8666   last_repnz_prefix = -1;
8667   last_data_prefix = -1;
8668   last_addr_prefix = -1;
8669   last_rex_prefix = -1;
8670   last_seg_prefix = -1;
8671   fwait_prefix = -1;
8672   active_seg_prefix = 0;
8673   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
8674     all_prefixes[i] = 0;
8675   i = 0;
8676   length = 0;
8677   /* The maximum instruction length is 15bytes.  */
8678   while (length < MAX_CODE_LENGTH - 1)
8679     {
8680       FETCH_DATA (the_info, codep + 1);
8681       newrex = 0;
8682       switch (*codep)
8683         {
8684         /* REX prefixes family.  */
8685         case 0x40:
8686         case 0x41:
8687         case 0x42:
8688         case 0x43:
8689         case 0x44:
8690         case 0x45:
8691         case 0x46:
8692         case 0x47:
8693         case 0x48:
8694         case 0x49:
8695         case 0x4a:
8696         case 0x4b:
8697         case 0x4c:
8698         case 0x4d:
8699         case 0x4e:
8700         case 0x4f:
8701           if (address_mode == mode_64bit)
8702             newrex = *codep;
8703           else
8704             return 1;
8705           last_rex_prefix = i;
8706           break;
8707         case 0xf3:
8708           prefixes |= PREFIX_REPZ;
8709           last_repz_prefix = i;
8710           break;
8711         case 0xf2:
8712           prefixes |= PREFIX_REPNZ;
8713           last_repnz_prefix = i;
8714           break;
8715         case 0xf0:
8716           prefixes |= PREFIX_LOCK;
8717           last_lock_prefix = i;
8718           break;
8719         case 0x2e:
8720           prefixes |= PREFIX_CS;
8721           last_seg_prefix = i;
8722
8723           if (address_mode != mode_64bit)
8724             active_seg_prefix = PREFIX_CS;
8725
8726           break;
8727         case 0x36:
8728           prefixes |= PREFIX_SS;
8729           last_seg_prefix = i;
8730
8731           if (address_mode != mode_64bit)
8732             active_seg_prefix = PREFIX_SS;
8733
8734           break;
8735         case 0x3e:
8736           prefixes |= PREFIX_DS;
8737           last_seg_prefix = i;
8738
8739           if (address_mode != mode_64bit)
8740             active_seg_prefix = PREFIX_DS;
8741
8742           break;
8743         case 0x26:
8744           prefixes |= PREFIX_ES;
8745           last_seg_prefix = i;
8746
8747           if (address_mode != mode_64bit)
8748             active_seg_prefix = PREFIX_ES;
8749
8750           break;
8751         case 0x64:
8752           prefixes |= PREFIX_FS;
8753           last_seg_prefix = i;
8754           active_seg_prefix = PREFIX_FS;
8755           break;
8756         case 0x65:
8757           prefixes |= PREFIX_GS;
8758           last_seg_prefix = i;
8759           active_seg_prefix = PREFIX_GS;
8760           break;
8761         case 0x66:
8762           prefixes |= PREFIX_DATA;
8763           last_data_prefix = i;
8764           break;
8765         case 0x67:
8766           prefixes |= PREFIX_ADDR;
8767           last_addr_prefix = i;
8768           break;
8769         case FWAIT_OPCODE:
8770           /* fwait is really an instruction.  If there are prefixes
8771              before the fwait, they belong to the fwait, *not* to the
8772              following instruction.  */
8773           fwait_prefix = i;
8774           if (prefixes || rex)
8775             {
8776               prefixes |= PREFIX_FWAIT;
8777               codep++;
8778               /* This ensures that the previous REX prefixes are noticed
8779                  as unused prefixes, as in the return case below.  */
8780               rex_used = rex;
8781               return 1;
8782             }
8783           prefixes = PREFIX_FWAIT;
8784           break;
8785         default:
8786           return 1;
8787         }
8788       /* Rex is ignored when followed by another prefix.  */
8789       if (rex)
8790         {
8791           rex_used = rex;
8792           return 1;
8793         }
8794       if (*codep != FWAIT_OPCODE)
8795         all_prefixes[i++] = *codep;
8796       rex = newrex;
8797       codep++;
8798       length++;
8799     }
8800   return 0;
8801 }
8802
8803 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
8804    prefix byte.  */
8805
8806 static const char *
8807 prefix_name (int pref, int sizeflag)
8808 {
8809   static const char *rexes [16] =
8810     {
8811       "rex",            /* 0x40 */
8812       "rex.B",          /* 0x41 */
8813       "rex.X",          /* 0x42 */
8814       "rex.XB",         /* 0x43 */
8815       "rex.R",          /* 0x44 */
8816       "rex.RB",         /* 0x45 */
8817       "rex.RX",         /* 0x46 */
8818       "rex.RXB",        /* 0x47 */
8819       "rex.W",          /* 0x48 */
8820       "rex.WB",         /* 0x49 */
8821       "rex.WX",         /* 0x4a */
8822       "rex.WXB",        /* 0x4b */
8823       "rex.WR",         /* 0x4c */
8824       "rex.WRB",        /* 0x4d */
8825       "rex.WRX",        /* 0x4e */
8826       "rex.WRXB",       /* 0x4f */
8827     };
8828
8829   switch (pref)
8830     {
8831     /* REX prefixes family.  */
8832     case 0x40:
8833     case 0x41:
8834     case 0x42:
8835     case 0x43:
8836     case 0x44:
8837     case 0x45:
8838     case 0x46:
8839     case 0x47:
8840     case 0x48:
8841     case 0x49:
8842     case 0x4a:
8843     case 0x4b:
8844     case 0x4c:
8845     case 0x4d:
8846     case 0x4e:
8847     case 0x4f:
8848       return rexes [pref - 0x40];
8849     case 0xf3:
8850       return "repz";
8851     case 0xf2:
8852       return "repnz";
8853     case 0xf0:
8854       return "lock";
8855     case 0x2e:
8856       return "cs";
8857     case 0x36:
8858       return "ss";
8859     case 0x3e:
8860       return "ds";
8861     case 0x26:
8862       return "es";
8863     case 0x64:
8864       return "fs";
8865     case 0x65:
8866       return "gs";
8867     case 0x66:
8868       return (sizeflag & DFLAG) ? "data16" : "data32";
8869     case 0x67:
8870       if (address_mode == mode_64bit)
8871         return (sizeflag & AFLAG) ? "addr32" : "addr64";
8872       else
8873         return (sizeflag & AFLAG) ? "addr16" : "addr32";
8874     case FWAIT_OPCODE:
8875       return "fwait";
8876     case REP_PREFIX:
8877       return "rep";
8878     case XACQUIRE_PREFIX:
8879       return "xacquire";
8880     case XRELEASE_PREFIX:
8881       return "xrelease";
8882     case BND_PREFIX:
8883       return "bnd";
8884     case NOTRACK_PREFIX:
8885       return "notrack";
8886     default:
8887       return NULL;
8888     }
8889 }
8890
8891 static char op_out[MAX_OPERANDS][100];
8892 static int op_ad, op_index[MAX_OPERANDS];
8893 static int two_source_ops;
8894 static bfd_vma op_address[MAX_OPERANDS];
8895 static bfd_vma op_riprel[MAX_OPERANDS];
8896 static bfd_vma start_pc;
8897
8898 /*
8899  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
8900  *   (see topic "Redundant prefixes" in the "Differences from 8086"
8901  *   section of the "Virtual 8086 Mode" chapter.)
8902  * 'pc' should be the address of this instruction, it will
8903  *   be used to print the target address if this is a relative jump or call
8904  * The function returns the length of this instruction in bytes.
8905  */
8906
8907 static char intel_syntax;
8908 static char intel_mnemonic = !SYSV386_COMPAT;
8909 static char open_char;
8910 static char close_char;
8911 static char separator_char;
8912 static char scale_char;
8913
8914 enum x86_64_isa
8915 {
8916   amd64 = 1,
8917   intel64
8918 };
8919
8920 static enum x86_64_isa isa64;
8921
8922 /* Here for backwards compatibility.  When gdb stops using
8923    print_insn_i386_att and print_insn_i386_intel these functions can
8924    disappear, and print_insn_i386 be merged into print_insn.  */
8925 int
8926 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
8927 {
8928   intel_syntax = 0;
8929
8930   return print_insn (pc, info);
8931 }
8932
8933 int
8934 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
8935 {
8936   intel_syntax = 1;
8937
8938   return print_insn (pc, info);
8939 }
8940
8941 int
8942 print_insn_i386 (bfd_vma pc, disassemble_info *info)
8943 {
8944   intel_syntax = -1;
8945
8946   return print_insn (pc, info);
8947 }
8948
8949 void
8950 print_i386_disassembler_options (FILE *stream)
8951 {
8952   fprintf (stream, _("\n\
8953 The following i386/x86-64 specific disassembler options are supported for use\n\
8954 with the -M switch (multiple options should be separated by commas):\n"));
8955
8956   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
8957   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
8958   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
8959   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
8960   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
8961   fprintf (stream, _("  att-mnemonic\n"
8962                      "              Display instruction in AT&T mnemonic\n"));
8963   fprintf (stream, _("  intel-mnemonic\n"
8964                      "              Display instruction in Intel mnemonic\n"));
8965   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
8966   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
8967   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
8968   fprintf (stream, _("  data32      Assume 32bit data size\n"));
8969   fprintf (stream, _("  data16      Assume 16bit data size\n"));
8970   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
8971   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
8972   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
8973 }
8974
8975 /* Bad opcode.  */
8976 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
8977
8978 /* Get a pointer to struct dis386 with a valid name.  */
8979
8980 static const struct dis386 *
8981 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
8982 {
8983   int vindex, vex_table_index;
8984
8985   if (dp->name != NULL)
8986     return dp;
8987
8988   switch (dp->op[0].bytemode)
8989     {
8990     case USE_REG_TABLE:
8991       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
8992       break;
8993
8994     case USE_MOD_TABLE:
8995       vindex = modrm.mod == 0x3 ? 1 : 0;
8996       dp = &mod_table[dp->op[1].bytemode][vindex];
8997       break;
8998
8999     case USE_RM_TABLE:
9000       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
9001       break;
9002
9003     case USE_PREFIX_TABLE:
9004       if (need_vex)
9005         {
9006           /* The prefix in VEX is implicit.  */
9007           switch (vex.prefix)
9008             {
9009             case 0:
9010               vindex = 0;
9011               break;
9012             case REPE_PREFIX_OPCODE:
9013               vindex = 1;
9014               break;
9015             case DATA_PREFIX_OPCODE:
9016               vindex = 2;
9017               break;
9018             case REPNE_PREFIX_OPCODE:
9019               vindex = 3;
9020               break;
9021             default:
9022               abort ();
9023               break;
9024             }
9025         }
9026       else
9027         {
9028           int last_prefix = -1;
9029           int prefix = 0;
9030           vindex = 0;
9031           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
9032              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
9033              last one wins.  */
9034           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
9035             {
9036               if (last_repz_prefix > last_repnz_prefix)
9037                 {
9038                   vindex = 1;
9039                   prefix = PREFIX_REPZ;
9040                   last_prefix = last_repz_prefix;
9041                 }
9042               else
9043                 {
9044                   vindex = 3;
9045                   prefix = PREFIX_REPNZ;
9046                   last_prefix = last_repnz_prefix;
9047                 }
9048
9049               /* Check if prefix should be ignored.  */
9050               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
9051                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
9052                    & prefix) != 0
9053                   && !prefix_table[dp->op[1].bytemode][vindex].name)
9054                 vindex = 0;
9055             }
9056
9057           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
9058             {
9059               vindex = 2;
9060               prefix = PREFIX_DATA;
9061               last_prefix = last_data_prefix;
9062             }
9063
9064           if (vindex != 0)
9065             {
9066               used_prefixes |= prefix;
9067               all_prefixes[last_prefix] = 0;
9068             }
9069         }
9070       dp = &prefix_table[dp->op[1].bytemode][vindex];
9071       break;
9072
9073     case USE_X86_64_TABLE:
9074       vindex = address_mode == mode_64bit ? 1 : 0;
9075       dp = &x86_64_table[dp->op[1].bytemode][vindex];
9076       break;
9077
9078     case USE_3BYTE_TABLE:
9079       FETCH_DATA (info, codep + 2);
9080       vindex = *codep++;
9081       dp = &three_byte_table[dp->op[1].bytemode][vindex];
9082       end_codep = codep;
9083       modrm.mod = (*codep >> 6) & 3;
9084       modrm.reg = (*codep >> 3) & 7;
9085       modrm.rm = *codep & 7;
9086       break;
9087
9088     case USE_VEX_LEN_TABLE:
9089       if (!need_vex)
9090         abort ();
9091
9092       switch (vex.length)
9093         {
9094         case 128:
9095           vindex = 0;
9096           break;
9097         case 512:
9098           /* This allows re-using in particular table entries where only
9099              128-bit operand size (VEX.L=0 / EVEX.L'L=0) are valid.  */
9100           if (vex.evex)
9101             {
9102         case 256:
9103               vindex = 1;
9104               break;
9105             }
9106         /* Fall through.  */
9107         default:
9108           abort ();
9109           break;
9110         }
9111
9112       dp = &vex_len_table[dp->op[1].bytemode][vindex];
9113       break;
9114
9115     case USE_EVEX_LEN_TABLE:
9116       if (!vex.evex)
9117         abort ();
9118
9119       switch (vex.length)
9120         {
9121         case 128:
9122           vindex = 0;
9123           break;
9124         case 256:
9125           vindex = 1;
9126           break;
9127         case 512:
9128           vindex = 2;
9129           break;
9130         default:
9131           abort ();
9132           break;
9133         }
9134
9135       dp = &evex_len_table[dp->op[1].bytemode][vindex];
9136       break;
9137
9138     case USE_XOP_8F_TABLE:
9139       FETCH_DATA (info, codep + 3);
9140       rex = ~(*codep >> 5) & 0x7;
9141
9142       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
9143       switch ((*codep & 0x1f))
9144         {
9145         default:
9146           dp = &bad_opcode;
9147           return dp;
9148         case 0x8:
9149           vex_table_index = XOP_08;
9150           break;
9151         case 0x9:
9152           vex_table_index = XOP_09;
9153           break;
9154         case 0xa:
9155           vex_table_index = XOP_0A;
9156           break;
9157         }
9158       codep++;
9159       vex.w = *codep & 0x80;
9160       if (vex.w && address_mode == mode_64bit)
9161         rex |= REX_W;
9162
9163       vex.register_specifier = (~(*codep >> 3)) & 0xf;
9164       if (address_mode != mode_64bit)
9165         {
9166           /* In 16/32-bit mode REX_B is silently ignored.  */
9167           rex &= ~REX_B;
9168         }
9169
9170       vex.length = (*codep & 0x4) ? 256 : 128;
9171       switch ((*codep & 0x3))
9172         {
9173         case 0:
9174           break;
9175         case 1:
9176           vex.prefix = DATA_PREFIX_OPCODE;
9177           break;
9178         case 2:
9179           vex.prefix = REPE_PREFIX_OPCODE;
9180           break;
9181         case 3:
9182           vex.prefix = REPNE_PREFIX_OPCODE;
9183           break;
9184         }
9185       need_vex = 1;
9186       codep++;
9187       vindex = *codep++;
9188       dp = &xop_table[vex_table_index][vindex];
9189
9190       end_codep = codep;
9191       FETCH_DATA (info, codep + 1);
9192       modrm.mod = (*codep >> 6) & 3;
9193       modrm.reg = (*codep >> 3) & 7;
9194       modrm.rm = *codep & 7;
9195
9196       /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid
9197          having to decode the bits for every otherwise valid encoding.  */
9198       if (vex.prefix)
9199         return &bad_opcode;
9200       break;
9201
9202     case USE_VEX_C4_TABLE:
9203       /* VEX prefix.  */
9204       FETCH_DATA (info, codep + 3);
9205       rex = ~(*codep >> 5) & 0x7;
9206       switch ((*codep & 0x1f))
9207         {
9208         default:
9209           dp = &bad_opcode;
9210           return dp;
9211         case 0x1:
9212           vex_table_index = VEX_0F;
9213           break;
9214         case 0x2:
9215           vex_table_index = VEX_0F38;
9216           break;
9217         case 0x3:
9218           vex_table_index = VEX_0F3A;
9219           break;
9220         }
9221       codep++;
9222       vex.w = *codep & 0x80;
9223       if (address_mode == mode_64bit)
9224         {
9225           if (vex.w)
9226             rex |= REX_W;
9227         }
9228       else
9229         {
9230           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
9231              is ignored, other REX bits are 0 and the highest bit in
9232              VEX.vvvv is also ignored (but we mustn't clear it here).  */
9233           rex = 0;
9234         }
9235       vex.register_specifier = (~(*codep >> 3)) & 0xf;
9236       vex.length = (*codep & 0x4) ? 256 : 128;
9237       switch ((*codep & 0x3))
9238         {
9239         case 0:
9240           break;
9241         case 1:
9242           vex.prefix = DATA_PREFIX_OPCODE;
9243           break;
9244         case 2:
9245           vex.prefix = REPE_PREFIX_OPCODE;
9246           break;
9247         case 3:
9248           vex.prefix = REPNE_PREFIX_OPCODE;
9249           break;
9250         }
9251       need_vex = 1;
9252       codep++;
9253       vindex = *codep++;
9254       dp = &vex_table[vex_table_index][vindex];
9255       end_codep = codep;
9256       /* There is no MODRM byte for VEX0F 77.  */
9257       if (vex_table_index != VEX_0F || vindex != 0x77)
9258         {
9259           FETCH_DATA (info, codep + 1);
9260           modrm.mod = (*codep >> 6) & 3;
9261           modrm.reg = (*codep >> 3) & 7;
9262           modrm.rm = *codep & 7;
9263         }
9264       break;
9265
9266     case USE_VEX_C5_TABLE:
9267       /* VEX prefix.  */
9268       FETCH_DATA (info, codep + 2);
9269       rex = (*codep & 0x80) ? 0 : REX_R;
9270
9271       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
9272          VEX.vvvv is 1.  */
9273       vex.register_specifier = (~(*codep >> 3)) & 0xf;
9274       vex.length = (*codep & 0x4) ? 256 : 128;
9275       switch ((*codep & 0x3))
9276         {
9277         case 0:
9278           break;
9279         case 1:
9280           vex.prefix = DATA_PREFIX_OPCODE;
9281           break;
9282         case 2:
9283           vex.prefix = REPE_PREFIX_OPCODE;
9284           break;
9285         case 3:
9286           vex.prefix = REPNE_PREFIX_OPCODE;
9287           break;
9288         }
9289       need_vex = 1;
9290       codep++;
9291       vindex = *codep++;
9292       dp = &vex_table[dp->op[1].bytemode][vindex];
9293       end_codep = codep;
9294       /* There is no MODRM byte for VEX 77.  */
9295       if (vindex != 0x77)
9296         {
9297           FETCH_DATA (info, codep + 1);
9298           modrm.mod = (*codep >> 6) & 3;
9299           modrm.reg = (*codep >> 3) & 7;
9300           modrm.rm = *codep & 7;
9301         }
9302       break;
9303
9304     case USE_VEX_W_TABLE:
9305       if (!need_vex)
9306         abort ();
9307
9308       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
9309       break;
9310
9311     case USE_EVEX_TABLE:
9312       two_source_ops = 0;
9313       /* EVEX prefix.  */
9314       vex.evex = 1;
9315       FETCH_DATA (info, codep + 4);
9316       /* The first byte after 0x62.  */
9317       rex = ~(*codep >> 5) & 0x7;
9318       vex.r = *codep & 0x10;
9319       switch ((*codep & 0xf))
9320         {
9321         default:
9322           return &bad_opcode;
9323         case 0x1:
9324           vex_table_index = EVEX_0F;
9325           break;
9326         case 0x2:
9327           vex_table_index = EVEX_0F38;
9328           break;
9329         case 0x3:
9330           vex_table_index = EVEX_0F3A;
9331           break;
9332         case 0x5:
9333           vex_table_index = EVEX_MAP5;
9334           break;
9335         case 0x6:
9336           vex_table_index = EVEX_MAP6;
9337           break;
9338         }
9339
9340       /* The second byte after 0x62.  */
9341       codep++;
9342       vex.w = *codep & 0x80;
9343       if (vex.w && address_mode == mode_64bit)
9344         rex |= REX_W;
9345
9346       vex.register_specifier = (~(*codep >> 3)) & 0xf;
9347
9348       /* The U bit.  */
9349       if (!(*codep & 0x4))
9350         return &bad_opcode;
9351
9352       switch ((*codep & 0x3))
9353         {
9354         case 0:
9355           break;
9356         case 1:
9357           vex.prefix = DATA_PREFIX_OPCODE;
9358           break;
9359         case 2:
9360           vex.prefix = REPE_PREFIX_OPCODE;
9361           break;
9362         case 3:
9363           vex.prefix = REPNE_PREFIX_OPCODE;
9364           break;
9365         }
9366
9367       /* The third byte after 0x62.  */
9368       codep++;
9369
9370       /* Remember the static rounding bits.  */
9371       vex.ll = (*codep >> 5) & 3;
9372       vex.b = (*codep & 0x10) != 0;
9373
9374       vex.v = *codep & 0x8;
9375       vex.mask_register_specifier = *codep & 0x7;
9376       vex.zeroing = *codep & 0x80;
9377
9378       if (address_mode != mode_64bit)
9379         {
9380           /* In 16/32-bit mode silently ignore following bits.  */
9381           rex &= ~REX_B;
9382           vex.r = 1;
9383         }
9384
9385       need_vex = 1;
9386       codep++;
9387       vindex = *codep++;
9388       dp = &evex_table[vex_table_index][vindex];
9389       end_codep = codep;
9390       FETCH_DATA (info, codep + 1);
9391       modrm.mod = (*codep >> 6) & 3;
9392       modrm.reg = (*codep >> 3) & 7;
9393       modrm.rm = *codep & 7;
9394
9395       /* Set vector length.  */
9396       if (modrm.mod == 3 && vex.b)
9397         vex.length = 512;
9398       else
9399         {
9400           switch (vex.ll)
9401             {
9402             case 0x0:
9403               vex.length = 128;
9404               break;
9405             case 0x1:
9406               vex.length = 256;
9407               break;
9408             case 0x2:
9409               vex.length = 512;
9410               break;
9411             default:
9412               return &bad_opcode;
9413             }
9414         }
9415       break;
9416
9417     case 0:
9418       dp = &bad_opcode;
9419       break;
9420
9421     default:
9422       abort ();
9423     }
9424
9425   if (dp->name != NULL)
9426     return dp;
9427   else
9428     return get_valid_dis386 (dp, info);
9429 }
9430
9431 static void
9432 get_sib (disassemble_info *info, int sizeflag)
9433 {
9434   /* If modrm.mod == 3, operand must be register.  */
9435   if (need_modrm
9436       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
9437       && modrm.mod != 3
9438       && modrm.rm == 4)
9439     {
9440       FETCH_DATA (info, codep + 2);
9441       sib.index = (codep [1] >> 3) & 7;
9442       sib.scale = (codep [1] >> 6) & 3;
9443       sib.base = codep [1] & 7;
9444     }
9445 }
9446
9447 static int
9448 print_insn (bfd_vma pc, disassemble_info *info)
9449 {
9450   const struct dis386 *dp;
9451   int i;
9452   char *op_txt[MAX_OPERANDS];
9453   int needcomma;
9454   int sizeflag, orig_sizeflag;
9455   const char *p;
9456   struct dis_private priv;
9457   int prefix_length;
9458
9459   priv.orig_sizeflag = AFLAG | DFLAG;
9460   if ((info->mach & bfd_mach_i386_i386) != 0)
9461     address_mode = mode_32bit;
9462   else if (info->mach == bfd_mach_i386_i8086)
9463     {
9464       address_mode = mode_16bit;
9465       priv.orig_sizeflag = 0;
9466     }
9467   else
9468     address_mode = mode_64bit;
9469
9470   if (intel_syntax == (char) -1)
9471     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
9472
9473   for (p = info->disassembler_options; p != NULL; )
9474     {
9475       if (startswith (p, "amd64"))
9476         isa64 = amd64;
9477       else if (startswith (p, "intel64"))
9478         isa64 = intel64;
9479       else if (startswith (p, "x86-64"))
9480         {
9481           address_mode = mode_64bit;
9482           priv.orig_sizeflag |= AFLAG | DFLAG;
9483         }
9484       else if (startswith (p, "i386"))
9485         {
9486           address_mode = mode_32bit;
9487           priv.orig_sizeflag |= AFLAG | DFLAG;
9488         }
9489       else if (startswith (p, "i8086"))
9490         {
9491           address_mode = mode_16bit;
9492           priv.orig_sizeflag &= ~(AFLAG | DFLAG);
9493         }
9494       else if (startswith (p, "intel"))
9495         {
9496           intel_syntax = 1;
9497           if (startswith (p + 5, "-mnemonic"))
9498             intel_mnemonic = 1;
9499         }
9500       else if (startswith (p, "att"))
9501         {
9502           intel_syntax = 0;
9503           if (startswith (p + 3, "-mnemonic"))
9504             intel_mnemonic = 0;
9505         }
9506       else if (startswith (p, "addr"))
9507         {
9508           if (address_mode == mode_64bit)
9509             {
9510               if (p[4] == '3' && p[5] == '2')
9511                 priv.orig_sizeflag &= ~AFLAG;
9512               else if (p[4] == '6' && p[5] == '4')
9513                 priv.orig_sizeflag |= AFLAG;
9514             }
9515           else
9516             {
9517               if (p[4] == '1' && p[5] == '6')
9518                 priv.orig_sizeflag &= ~AFLAG;
9519               else if (p[4] == '3' && p[5] == '2')
9520                 priv.orig_sizeflag |= AFLAG;
9521             }
9522         }
9523       else if (startswith (p, "data"))
9524         {
9525           if (p[4] == '1' && p[5] == '6')
9526             priv.orig_sizeflag &= ~DFLAG;
9527           else if (p[4] == '3' && p[5] == '2')
9528             priv.orig_sizeflag |= DFLAG;
9529         }
9530       else if (startswith (p, "suffix"))
9531         priv.orig_sizeflag |= SUFFIX_ALWAYS;
9532
9533       p = strchr (p, ',');
9534       if (p != NULL)
9535         p++;
9536     }
9537
9538   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
9539     {
9540       (*info->fprintf_func) (info->stream,
9541                              _("64-bit address is disabled"));
9542       return -1;
9543     }
9544
9545   if (intel_syntax)
9546     {
9547       names64 = intel_names64;
9548       names32 = intel_names32;
9549       names16 = intel_names16;
9550       names8 = intel_names8;
9551       names8rex = intel_names8rex;
9552       names_seg = intel_names_seg;
9553       names_mm = intel_names_mm;
9554       names_bnd = intel_names_bnd;
9555       names_xmm = intel_names_xmm;
9556       names_ymm = intel_names_ymm;
9557       names_zmm = intel_names_zmm;
9558       names_tmm = intel_names_tmm;
9559       index64 = intel_index64;
9560       index32 = intel_index32;
9561       names_mask = intel_names_mask;
9562       index16 = intel_index16;
9563       open_char = '[';
9564       close_char = ']';
9565       separator_char = '+';
9566       scale_char = '*';
9567     }
9568   else
9569     {
9570       names64 = att_names64;
9571       names32 = att_names32;
9572       names16 = att_names16;
9573       names8 = att_names8;
9574       names8rex = att_names8rex;
9575       names_seg = att_names_seg;
9576       names_mm = att_names_mm;
9577       names_bnd = att_names_bnd;
9578       names_xmm = att_names_xmm;
9579       names_ymm = att_names_ymm;
9580       names_zmm = att_names_zmm;
9581       names_tmm = att_names_tmm;
9582       index64 = att_index64;
9583       index32 = att_index32;
9584       names_mask = att_names_mask;
9585       index16 = att_index16;
9586       open_char = '(';
9587       close_char =  ')';
9588       separator_char = ',';
9589       scale_char = ',';
9590     }
9591
9592   /* The output looks better if we put 7 bytes on a line, since that
9593      puts most long word instructions on a single line.  Use 8 bytes
9594      for Intel L1OM.  */
9595   if ((info->mach & bfd_mach_l1om) != 0)
9596     info->bytes_per_line = 8;
9597   else
9598     info->bytes_per_line = 7;
9599
9600   info->private_data = &priv;
9601   priv.max_fetched = priv.the_buffer;
9602   priv.insn_start = pc;
9603
9604   obuf[0] = 0;
9605   for (i = 0; i < MAX_OPERANDS; ++i)
9606     {
9607       op_out[i][0] = 0;
9608       op_index[i] = -1;
9609     }
9610
9611   the_info = info;
9612   start_pc = pc;
9613   start_codep = priv.the_buffer;
9614   codep = priv.the_buffer;
9615
9616   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
9617     {
9618       const char *name;
9619
9620       /* Getting here means we tried for data but didn't get it.  That
9621          means we have an incomplete instruction of some sort.  Just
9622          print the first byte as a prefix or a .byte pseudo-op.  */
9623       if (codep > priv.the_buffer)
9624         {
9625           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
9626           if (name != NULL)
9627             (*info->fprintf_func) (info->stream, "%s", name);
9628           else
9629             {
9630               /* Just print the first byte as a .byte instruction.  */
9631               (*info->fprintf_func) (info->stream, ".byte 0x%x",
9632                                      (unsigned int) priv.the_buffer[0]);
9633             }
9634
9635           return 1;
9636         }
9637
9638       return -1;
9639     }
9640
9641   obufp = obuf;
9642   sizeflag = priv.orig_sizeflag;
9643
9644   if (!ckprefix () || rex_used)
9645     {
9646       /* Too many prefixes or unused REX prefixes.  */
9647       for (i = 0;
9648            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
9649            i++)
9650         (*info->fprintf_func) (info->stream, "%s%s",
9651                                i == 0 ? "" : " ",
9652                                prefix_name (all_prefixes[i], sizeflag));
9653       return i;
9654     }
9655
9656   insn_codep = codep;
9657
9658   FETCH_DATA (info, codep + 1);
9659   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
9660
9661   if (((prefixes & PREFIX_FWAIT)
9662        && ((*codep < 0xd8) || (*codep > 0xdf))))
9663     {
9664       /* Handle prefixes before fwait.  */
9665       for (i = 0; i < fwait_prefix && all_prefixes[i];
9666            i++)
9667         (*info->fprintf_func) (info->stream, "%s ",
9668                                prefix_name (all_prefixes[i], sizeflag));
9669       (*info->fprintf_func) (info->stream, "fwait");
9670       return i + 1;
9671     }
9672
9673   if (*codep == 0x0f)
9674     {
9675       unsigned char threebyte;
9676
9677       codep++;
9678       FETCH_DATA (info, codep + 1);
9679       threebyte = *codep;
9680       dp = &dis386_twobyte[threebyte];
9681       need_modrm = twobyte_has_modrm[threebyte];
9682       codep++;
9683     }
9684   else
9685     {
9686       dp = &dis386[*codep];
9687       need_modrm = onebyte_has_modrm[*codep];
9688       codep++;
9689     }
9690
9691   /* Save sizeflag for printing the extra prefixes later before updating
9692      it for mnemonic and operand processing.  The prefix names depend
9693      only on the address mode.  */
9694   orig_sizeflag = sizeflag;
9695   if (prefixes & PREFIX_ADDR)
9696     sizeflag ^= AFLAG;
9697   if ((prefixes & PREFIX_DATA))
9698     sizeflag ^= DFLAG;
9699
9700   end_codep = codep;
9701   if (need_modrm)
9702     {
9703       FETCH_DATA (info, codep + 1);
9704       modrm.mod = (*codep >> 6) & 3;
9705       modrm.reg = (*codep >> 3) & 7;
9706       modrm.rm = *codep & 7;
9707     }
9708   else
9709     memset (&modrm, 0, sizeof (modrm));
9710
9711   need_vex = 0;
9712   memset (&vex, 0, sizeof (vex));
9713
9714   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
9715     {
9716       get_sib (info, sizeflag);
9717       dofloat (sizeflag);
9718     }
9719   else
9720     {
9721       dp = get_valid_dis386 (dp, info);
9722       if (dp != NULL && putop (dp->name, sizeflag) == 0)
9723         {
9724           get_sib (info, sizeflag);
9725           for (i = 0; i < MAX_OPERANDS; ++i)
9726             {
9727               obufp = op_out[i];
9728               op_ad = MAX_OPERANDS - 1 - i;
9729               if (dp->op[i].rtn)
9730                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
9731               /* For EVEX instruction after the last operand masking
9732                  should be printed.  */
9733               if (i == 0 && vex.evex)
9734                 {
9735                   /* Don't print {%k0}.  */
9736                   if (vex.mask_register_specifier)
9737                     {
9738                       oappend ("{");
9739                       oappend (names_mask[vex.mask_register_specifier]);
9740                       oappend ("}");
9741                     }
9742                   if (vex.zeroing)
9743                     oappend ("{z}");
9744
9745                   /* S/G insns require a mask and don't allow
9746                      zeroing-masking.  */
9747                   if ((dp->op[0].bytemode == vex_vsib_d_w_dq_mode
9748                        || dp->op[0].bytemode == vex_vsib_q_w_dq_mode)
9749                       && (vex.mask_register_specifier == 0 || vex.zeroing))
9750                     oappend ("/(bad)");
9751                 }
9752             }
9753
9754           /* Check whether rounding control was enabled for an insn not
9755              supporting it.  */
9756           if (modrm.mod == 3 && vex.b && !(evex_used & EVEX_b_used))
9757             {
9758               for (i = 0; i < MAX_OPERANDS; ++i)
9759                 {
9760                   obufp = op_out[i];
9761                   if (*obufp)
9762                     continue;
9763                   oappend (names_rounding[vex.ll]);
9764                   oappend ("bad}");
9765                   break;
9766                 }
9767             }
9768         }
9769     }
9770
9771   /* Clear instruction information.  */
9772   if (the_info)
9773     {
9774       the_info->insn_info_valid = 0;
9775       the_info->branch_delay_insns = 0;
9776       the_info->data_size = 0;
9777       the_info->insn_type = dis_noninsn;
9778       the_info->target = 0;
9779       the_info->target2 = 0;
9780     }
9781
9782   /* Reset jump operation indicator.  */
9783   op_is_jump = false;
9784
9785   {
9786     int jump_detection = 0;
9787
9788     /* Extract flags.  */
9789     for (i = 0; i < MAX_OPERANDS; ++i)
9790       {
9791         if ((dp->op[i].rtn == OP_J)
9792             || (dp->op[i].rtn == OP_indirE))
9793           jump_detection |= 1;
9794         else if ((dp->op[i].rtn == BND_Fixup)
9795                  || (!dp->op[i].rtn && !dp->op[i].bytemode))
9796           jump_detection |= 2;
9797         else if ((dp->op[i].bytemode == cond_jump_mode)
9798                  || (dp->op[i].bytemode == loop_jcxz_mode))
9799           jump_detection |= 4;
9800       }
9801
9802     /* Determine if this is a jump or branch.  */
9803     if ((jump_detection & 0x3) == 0x3)
9804       {
9805         op_is_jump = true;
9806         if (jump_detection & 0x4)
9807           the_info->insn_type = dis_condbranch;
9808         else
9809           the_info->insn_type =
9810             (dp->name && !strncmp(dp->name, "call", 4))
9811             ? dis_jsr : dis_branch;
9812       }
9813   }
9814
9815   /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
9816      are all 0s in inverted form.  */
9817   if (need_vex && vex.register_specifier != 0)
9818     {
9819       (*info->fprintf_func) (info->stream, "(bad)");
9820       return end_codep - priv.the_buffer;
9821     }
9822
9823   /* If EVEX.z is set, there must be an actual mask register in use.  */
9824   if (vex.zeroing && vex.mask_register_specifier == 0)
9825     {
9826       (*info->fprintf_func) (info->stream, "(bad)");
9827       return end_codep - priv.the_buffer;
9828     }
9829
9830   switch (dp->prefix_requirement)
9831     {
9832     case PREFIX_DATA:
9833       /* If only the data prefix is marked as mandatory, its absence renders
9834          the encoding invalid.  Most other PREFIX_OPCODE rules still apply.  */
9835       if (need_vex ? !vex.prefix : !(prefixes & PREFIX_DATA))
9836         {
9837           (*info->fprintf_func) (info->stream, "(bad)");
9838           return end_codep - priv.the_buffer;
9839         }
9840       used_prefixes |= PREFIX_DATA;
9841       /* Fall through.  */
9842     case PREFIX_OPCODE:
9843       /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
9844          unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
9845          used by putop and MMX/SSE operand and may be overridden by the
9846          PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
9847          separately.  */
9848       if (((need_vex
9849             ? vex.prefix == REPE_PREFIX_OPCODE
9850               || vex.prefix == REPNE_PREFIX_OPCODE
9851             : (prefixes
9852                & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
9853            && (used_prefixes
9854                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
9855           || (((need_vex
9856                 ? vex.prefix == DATA_PREFIX_OPCODE
9857                 : ((prefixes
9858                     & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
9859                    == PREFIX_DATA))
9860                && (used_prefixes & PREFIX_DATA) == 0))
9861           || (vex.evex && dp->prefix_requirement != PREFIX_DATA
9862               && !vex.w != !(used_prefixes & PREFIX_DATA)))
9863         {
9864           (*info->fprintf_func) (info->stream, "(bad)");
9865           return end_codep - priv.the_buffer;
9866         }
9867       break;
9868
9869     case PREFIX_IGNORED:
9870       /* Zap data size and rep prefixes from used_prefixes and reinstate their
9871          origins in all_prefixes.  */
9872       used_prefixes &= ~PREFIX_OPCODE;
9873       if (last_data_prefix >= 0)
9874         all_prefixes[last_data_prefix] = 0x66;
9875       if (last_repz_prefix >= 0)
9876         all_prefixes[last_repz_prefix] = 0xf3;
9877       if (last_repnz_prefix >= 0)
9878         all_prefixes[last_repnz_prefix] = 0xf2;
9879       break;
9880     }
9881
9882   /* Check if the REX prefix is used.  */
9883   if ((rex ^ rex_used) == 0 && !need_vex && last_rex_prefix >= 0)
9884     all_prefixes[last_rex_prefix] = 0;
9885
9886   /* Check if the SEG prefix is used.  */
9887   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
9888                    | PREFIX_FS | PREFIX_GS)) != 0
9889       && (used_prefixes & active_seg_prefix) != 0)
9890     all_prefixes[last_seg_prefix] = 0;
9891
9892   /* Check if the ADDR prefix is used.  */
9893   if ((prefixes & PREFIX_ADDR) != 0
9894       && (used_prefixes & PREFIX_ADDR) != 0)
9895     all_prefixes[last_addr_prefix] = 0;
9896
9897   /* Check if the DATA prefix is used.  */
9898   if ((prefixes & PREFIX_DATA) != 0
9899       && (used_prefixes & PREFIX_DATA) != 0
9900       && !need_vex)
9901     all_prefixes[last_data_prefix] = 0;
9902
9903   /* Print the extra prefixes.  */
9904   prefix_length = 0;
9905   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
9906     if (all_prefixes[i])
9907       {
9908         const char *name;
9909         name = prefix_name (all_prefixes[i], orig_sizeflag);
9910         if (name == NULL)
9911           abort ();
9912         prefix_length += strlen (name) + 1;
9913         (*info->fprintf_func) (info->stream, "%s ", name);
9914       }
9915
9916   /* Check maximum code length.  */
9917   if ((codep - start_codep) > MAX_CODE_LENGTH)
9918     {
9919       (*info->fprintf_func) (info->stream, "(bad)");
9920       return MAX_CODE_LENGTH;
9921     }
9922
9923   obufp = mnemonicendp;
9924   for (i = strlen (obuf) + prefix_length; i < 6; i++)
9925     oappend (" ");
9926   oappend (" ");
9927   (*info->fprintf_func) (info->stream, "%s", obuf);
9928
9929   /* The enter and bound instructions are printed with operands in the same
9930      order as the intel book; everything else is printed in reverse order.  */
9931   if (intel_syntax || two_source_ops)
9932     {
9933       bfd_vma riprel;
9934
9935       for (i = 0; i < MAX_OPERANDS; ++i)
9936         op_txt[i] = op_out[i];
9937
9938       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
9939           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
9940         {
9941           op_txt[2] = op_out[3];
9942           op_txt[3] = op_out[2];
9943         }
9944
9945       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
9946         {
9947           op_ad = op_index[i];
9948           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
9949           op_index[MAX_OPERANDS - 1 - i] = op_ad;
9950           riprel = op_riprel[i];
9951           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
9952           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
9953         }
9954     }
9955   else
9956     {
9957       for (i = 0; i < MAX_OPERANDS; ++i)
9958         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
9959     }
9960
9961   needcomma = 0;
9962   for (i = 0; i < MAX_OPERANDS; ++i)
9963     if (*op_txt[i])
9964       {
9965         if (needcomma)
9966           (*info->fprintf_func) (info->stream, ",");
9967         if (op_index[i] != -1 && !op_riprel[i])
9968           {
9969             bfd_vma target = (bfd_vma) op_address[op_index[i]];
9970
9971             if (the_info && op_is_jump)
9972               {
9973                 the_info->insn_info_valid = 1;
9974                 the_info->branch_delay_insns = 0;
9975                 the_info->data_size = 0;
9976                 the_info->target = target;
9977                 the_info->target2 = 0;
9978               }
9979             (*info->print_address_func) (target, info);
9980           }
9981         else
9982           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
9983         needcomma = 1;
9984       }
9985
9986   for (i = 0; i < MAX_OPERANDS; i++)
9987     if (op_index[i] != -1 && op_riprel[i])
9988       {
9989         (*info->fprintf_func) (info->stream, "        # ");
9990         (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
9991                                                 + op_address[op_index[i]]), info);
9992         break;
9993       }
9994   return codep - priv.the_buffer;
9995 }
9996
9997 static const char *float_mem[] = {
9998   /* d8 */
9999   "fadd{s|}",
10000   "fmul{s|}",
10001   "fcom{s|}",
10002   "fcomp{s|}",
10003   "fsub{s|}",
10004   "fsubr{s|}",
10005   "fdiv{s|}",
10006   "fdivr{s|}",
10007   /* d9 */
10008   "fld{s|}",
10009   "(bad)",
10010   "fst{s|}",
10011   "fstp{s|}",
10012   "fldenv{C|C}",
10013   "fldcw",
10014   "fNstenv{C|C}",
10015   "fNstcw",
10016   /* da */
10017   "fiadd{l|}",
10018   "fimul{l|}",
10019   "ficom{l|}",
10020   "ficomp{l|}",
10021   "fisub{l|}",
10022   "fisubr{l|}",
10023   "fidiv{l|}",
10024   "fidivr{l|}",
10025   /* db */
10026   "fild{l|}",
10027   "fisttp{l|}",
10028   "fist{l|}",
10029   "fistp{l|}",
10030   "(bad)",
10031   "fld{t|}",
10032   "(bad)",
10033   "fstp{t|}",
10034   /* dc */
10035   "fadd{l|}",
10036   "fmul{l|}",
10037   "fcom{l|}",
10038   "fcomp{l|}",
10039   "fsub{l|}",
10040   "fsubr{l|}",
10041   "fdiv{l|}",
10042   "fdivr{l|}",
10043   /* dd */
10044   "fld{l|}",
10045   "fisttp{ll|}",
10046   "fst{l||}",
10047   "fstp{l|}",
10048   "frstor{C|C}",
10049   "(bad)",
10050   "fNsave{C|C}",
10051   "fNstsw",
10052   /* de */
10053   "fiadd{s|}",
10054   "fimul{s|}",
10055   "ficom{s|}",
10056   "ficomp{s|}",
10057   "fisub{s|}",
10058   "fisubr{s|}",
10059   "fidiv{s|}",
10060   "fidivr{s|}",
10061   /* df */
10062   "fild{s|}",
10063   "fisttp{s|}",
10064   "fist{s|}",
10065   "fistp{s|}",
10066   "fbld",
10067   "fild{ll|}",
10068   "fbstp",
10069   "fistp{ll|}",
10070 };
10071
10072 static const unsigned char float_mem_mode[] = {
10073   /* d8 */
10074   d_mode,
10075   d_mode,
10076   d_mode,
10077   d_mode,
10078   d_mode,
10079   d_mode,
10080   d_mode,
10081   d_mode,
10082   /* d9 */
10083   d_mode,
10084   0,
10085   d_mode,
10086   d_mode,
10087   0,
10088   w_mode,
10089   0,
10090   w_mode,
10091   /* da */
10092   d_mode,
10093   d_mode,
10094   d_mode,
10095   d_mode,
10096   d_mode,
10097   d_mode,
10098   d_mode,
10099   d_mode,
10100   /* db */
10101   d_mode,
10102   d_mode,
10103   d_mode,
10104   d_mode,
10105   0,
10106   t_mode,
10107   0,
10108   t_mode,
10109   /* dc */
10110   q_mode,
10111   q_mode,
10112   q_mode,
10113   q_mode,
10114   q_mode,
10115   q_mode,
10116   q_mode,
10117   q_mode,
10118   /* dd */
10119   q_mode,
10120   q_mode,
10121   q_mode,
10122   q_mode,
10123   0,
10124   0,
10125   0,
10126   w_mode,
10127   /* de */
10128   w_mode,
10129   w_mode,
10130   w_mode,
10131   w_mode,
10132   w_mode,
10133   w_mode,
10134   w_mode,
10135   w_mode,
10136   /* df */
10137   w_mode,
10138   w_mode,
10139   w_mode,
10140   w_mode,
10141   t_mode,
10142   q_mode,
10143   t_mode,
10144   q_mode
10145 };
10146
10147 #define ST { OP_ST, 0 }
10148 #define STi { OP_STi, 0 }
10149
10150 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
10151 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
10152 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
10153 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
10154 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
10155 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
10156 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
10157 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
10158 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
10159
10160 static const struct dis386 float_reg[][8] = {
10161   /* d8 */
10162   {
10163     { "fadd",   { ST, STi }, 0 },
10164     { "fmul",   { ST, STi }, 0 },
10165     { "fcom",   { STi }, 0 },
10166     { "fcomp",  { STi }, 0 },
10167     { "fsub",   { ST, STi }, 0 },
10168     { "fsubr",  { ST, STi }, 0 },
10169     { "fdiv",   { ST, STi }, 0 },
10170     { "fdivr",  { ST, STi }, 0 },
10171   },
10172   /* d9 */
10173   {
10174     { "fld",    { STi }, 0 },
10175     { "fxch",   { STi }, 0 },
10176     { FGRPd9_2 },
10177     { Bad_Opcode },
10178     { FGRPd9_4 },
10179     { FGRPd9_5 },
10180     { FGRPd9_6 },
10181     { FGRPd9_7 },
10182   },
10183   /* da */
10184   {
10185     { "fcmovb", { ST, STi }, 0 },
10186     { "fcmove", { ST, STi }, 0 },
10187     { "fcmovbe",{ ST, STi }, 0 },
10188     { "fcmovu", { ST, STi }, 0 },
10189     { Bad_Opcode },
10190     { FGRPda_5 },
10191     { Bad_Opcode },
10192     { Bad_Opcode },
10193   },
10194   /* db */
10195   {
10196     { "fcmovnb",{ ST, STi }, 0 },
10197     { "fcmovne",{ ST, STi }, 0 },
10198     { "fcmovnbe",{ ST, STi }, 0 },
10199     { "fcmovnu",{ ST, STi }, 0 },
10200     { FGRPdb_4 },
10201     { "fucomi", { ST, STi }, 0 },
10202     { "fcomi",  { ST, STi }, 0 },
10203     { Bad_Opcode },
10204   },
10205   /* dc */
10206   {
10207     { "fadd",   { STi, ST }, 0 },
10208     { "fmul",   { STi, ST }, 0 },
10209     { Bad_Opcode },
10210     { Bad_Opcode },
10211     { "fsub{!M|r}",     { STi, ST }, 0 },
10212     { "fsub{M|}",       { STi, ST }, 0 },
10213     { "fdiv{!M|r}",     { STi, ST }, 0 },
10214     { "fdiv{M|}",       { STi, ST }, 0 },
10215   },
10216   /* dd */
10217   {
10218     { "ffree",  { STi }, 0 },
10219     { Bad_Opcode },
10220     { "fst",    { STi }, 0 },
10221     { "fstp",   { STi }, 0 },
10222     { "fucom",  { STi }, 0 },
10223     { "fucomp", { STi }, 0 },
10224     { Bad_Opcode },
10225     { Bad_Opcode },
10226   },
10227   /* de */
10228   {
10229     { "faddp",  { STi, ST }, 0 },
10230     { "fmulp",  { STi, ST }, 0 },
10231     { Bad_Opcode },
10232     { FGRPde_3 },
10233     { "fsub{!M|r}p",    { STi, ST }, 0 },
10234     { "fsub{M|}p",      { STi, ST }, 0 },
10235     { "fdiv{!M|r}p",    { STi, ST }, 0 },
10236     { "fdiv{M|}p",      { STi, ST }, 0 },
10237   },
10238   /* df */
10239   {
10240     { "ffreep", { STi }, 0 },
10241     { Bad_Opcode },
10242     { Bad_Opcode },
10243     { Bad_Opcode },
10244     { FGRPdf_4 },
10245     { "fucomip", { ST, STi }, 0 },
10246     { "fcomip", { ST, STi }, 0 },
10247     { Bad_Opcode },
10248   },
10249 };
10250
10251 static char *fgrps[][8] = {
10252   /* Bad opcode 0 */
10253   {
10254     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10255   },
10256
10257   /* d9_2  1 */
10258   {
10259     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10260   },
10261
10262   /* d9_4  2 */
10263   {
10264     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
10265   },
10266
10267   /* d9_5  3 */
10268   {
10269     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
10270   },
10271
10272   /* d9_6  4 */
10273   {
10274     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
10275   },
10276
10277   /* d9_7  5 */
10278   {
10279     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
10280   },
10281
10282   /* da_5  6 */
10283   {
10284     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10285   },
10286
10287   /* db_4  7 */
10288   {
10289     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
10290     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
10291   },
10292
10293   /* de_3  8 */
10294   {
10295     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10296   },
10297
10298   /* df_4  9 */
10299   {
10300     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10301   },
10302 };
10303
10304 static void
10305 swap_operand (void)
10306 {
10307   mnemonicendp[0] = '.';
10308   mnemonicendp[1] = 's';
10309   mnemonicendp += 2;
10310 }
10311
10312 static void
10313 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
10314                int sizeflag ATTRIBUTE_UNUSED)
10315 {
10316   /* Skip mod/rm byte.  */
10317   MODRM_CHECK;
10318   codep++;
10319 }
10320
10321 static void
10322 dofloat (int sizeflag)
10323 {
10324   const struct dis386 *dp;
10325   unsigned char floatop;
10326
10327   floatop = codep[-1];
10328
10329   if (modrm.mod != 3)
10330     {
10331       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
10332
10333       putop (float_mem[fp_indx], sizeflag);
10334       obufp = op_out[0];
10335       op_ad = 2;
10336       OP_E (float_mem_mode[fp_indx], sizeflag);
10337       return;
10338     }
10339   /* Skip mod/rm byte.  */
10340   MODRM_CHECK;
10341   codep++;
10342
10343   dp = &float_reg[floatop - 0xd8][modrm.reg];
10344   if (dp->name == NULL)
10345     {
10346       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
10347
10348       /* Instruction fnstsw is only one with strange arg.  */
10349       if (floatop == 0xdf && codep[-1] == 0xe0)
10350         strcpy (op_out[0], names16[0]);
10351     }
10352   else
10353     {
10354       putop (dp->name, sizeflag);
10355
10356       obufp = op_out[0];
10357       op_ad = 2;
10358       if (dp->op[0].rtn)
10359         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
10360
10361       obufp = op_out[1];
10362       op_ad = 1;
10363       if (dp->op[1].rtn)
10364         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
10365     }
10366 }
10367
10368 /* Like oappend (below), but S is a string starting with '%'.
10369    In Intel syntax, the '%' is elided.  */
10370 static void
10371 oappend_maybe_intel (const char *s)
10372 {
10373   oappend (s + intel_syntax);
10374 }
10375
10376 static void
10377 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
10378 {
10379   oappend_maybe_intel ("%st");
10380 }
10381
10382 static void
10383 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
10384 {
10385   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
10386   oappend_maybe_intel (scratchbuf);
10387 }
10388
10389 /* Capital letters in template are macros.  */
10390 static int
10391 putop (const char *in_template, int sizeflag)
10392 {
10393   const char *p;
10394   int alt = 0;
10395   int cond = 1;
10396   unsigned int l = 0, len = 0;
10397   char last[4];
10398
10399   for (p = in_template; *p; p++)
10400     {
10401       if (len > l)
10402         {
10403           if (l >= sizeof (last) || !ISUPPER (*p))
10404             abort ();
10405           last[l++] = *p;
10406           continue;
10407         }
10408       switch (*p)
10409         {
10410         default:
10411           *obufp++ = *p;
10412           break;
10413         case '%':
10414           len++;
10415           break;
10416         case '!':
10417           cond = 0;
10418           break;
10419         case '{':
10420           if (intel_syntax)
10421             {
10422               while (*++p != '|')
10423                 if (*p == '}' || *p == '\0')
10424                   abort ();
10425               alt = 1;
10426             }
10427           break;
10428         case '|':
10429           while (*++p != '}')
10430             {
10431               if (*p == '\0')
10432                 abort ();
10433             }
10434           break;
10435         case '}':
10436           alt = 0;
10437           break;
10438         case 'A':
10439           if (intel_syntax)
10440             break;
10441           if ((need_modrm && modrm.mod != 3)
10442               || (sizeflag & SUFFIX_ALWAYS))
10443             *obufp++ = 'b';
10444           break;
10445         case 'B':
10446           if (l == 0)
10447             {
10448             case_B:
10449               if (intel_syntax)
10450                 break;
10451               if (sizeflag & SUFFIX_ALWAYS)
10452                 *obufp++ = 'b';
10453             }
10454           else if (l == 1 && last[0] == 'L')
10455             {
10456               if (address_mode == mode_64bit
10457                   && !(prefixes & PREFIX_ADDR))
10458                 {
10459                   *obufp++ = 'a';
10460                   *obufp++ = 'b';
10461                   *obufp++ = 's';
10462                 }
10463
10464               goto case_B;
10465             }
10466           else
10467             abort ();
10468           break;
10469         case 'C':
10470           if (intel_syntax && !alt)
10471             break;
10472           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10473             {
10474               if (sizeflag & DFLAG)
10475                 *obufp++ = intel_syntax ? 'd' : 'l';
10476               else
10477                 *obufp++ = intel_syntax ? 'w' : 's';
10478               used_prefixes |= (prefixes & PREFIX_DATA);
10479             }
10480           break;
10481         case 'D':
10482           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
10483             break;
10484           USED_REX (REX_W);
10485           if (modrm.mod == 3)
10486             {
10487               if (rex & REX_W)
10488                 *obufp++ = 'q';
10489               else
10490                 {
10491                   if (sizeflag & DFLAG)
10492                     *obufp++ = intel_syntax ? 'd' : 'l';
10493                   else
10494                     *obufp++ = 'w';
10495                   used_prefixes |= (prefixes & PREFIX_DATA);
10496                 }
10497             }
10498           else
10499             *obufp++ = 'w';
10500           break;
10501         case 'E':               /* For jcxz/jecxz */
10502           if (address_mode == mode_64bit)
10503             {
10504               if (sizeflag & AFLAG)
10505                 *obufp++ = 'r';
10506               else
10507                 *obufp++ = 'e';
10508             }
10509           else
10510             if (sizeflag & AFLAG)
10511               *obufp++ = 'e';
10512           used_prefixes |= (prefixes & PREFIX_ADDR);
10513           break;
10514         case 'F':
10515           if (intel_syntax)
10516             break;
10517           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
10518             {
10519               if (sizeflag & AFLAG)
10520                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
10521               else
10522                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
10523               used_prefixes |= (prefixes & PREFIX_ADDR);
10524             }
10525           break;
10526         case 'G':
10527           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
10528             break;
10529           if ((rex & REX_W) || (sizeflag & DFLAG))
10530             *obufp++ = 'l';
10531           else
10532             *obufp++ = 'w';
10533           if (!(rex & REX_W))
10534             used_prefixes |= (prefixes & PREFIX_DATA);
10535           break;
10536         case 'H':
10537           if (l == 0)
10538             {
10539               if (intel_syntax)
10540                 break;
10541               if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
10542                   || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
10543                 {
10544                   used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
10545                   *obufp++ = ',';
10546                   *obufp++ = 'p';
10547
10548                   /* Set active_seg_prefix even if not set in 64-bit mode
10549                      because here it is a valid branch hint. */
10550                   if (prefixes & PREFIX_DS)
10551                     {
10552                       active_seg_prefix = PREFIX_DS;
10553                       *obufp++ = 't';
10554                     }
10555                   else
10556                     {
10557                       active_seg_prefix = PREFIX_CS;
10558                       *obufp++ = 'n';
10559                     }
10560                 }
10561             }
10562           else if (l == 1 && last[0] == 'X')
10563             {
10564               if (vex.w == 0)
10565                 *obufp++ = 'h';
10566               else
10567                 {
10568                   *obufp++ = '{';
10569                   *obufp++ = 'b';
10570                   *obufp++ = 'a';
10571                   *obufp++ = 'd';
10572                   *obufp++ = '}';
10573                 }
10574             }
10575           else
10576             abort ();
10577           break;
10578         case 'K':
10579           USED_REX (REX_W);
10580           if (rex & REX_W)
10581             *obufp++ = 'q';
10582           else
10583             *obufp++ = 'd';
10584           break;
10585         case 'L':
10586           abort ();
10587         case 'M':
10588           if (intel_mnemonic != cond)
10589             *obufp++ = 'r';
10590           break;
10591         case 'N':
10592           if ((prefixes & PREFIX_FWAIT) == 0)
10593             *obufp++ = 'n';
10594           else
10595             used_prefixes |= PREFIX_FWAIT;
10596           break;
10597         case 'O':
10598           USED_REX (REX_W);
10599           if (rex & REX_W)
10600             *obufp++ = 'o';
10601           else if (intel_syntax && (sizeflag & DFLAG))
10602             *obufp++ = 'q';
10603           else
10604             *obufp++ = 'd';
10605           if (!(rex & REX_W))
10606             used_prefixes |= (prefixes & PREFIX_DATA);
10607           break;
10608         case '@':
10609           if (address_mode == mode_64bit
10610               && (isa64 == intel64 || (rex & REX_W)
10611                   || !(prefixes & PREFIX_DATA)))
10612             {
10613               if (sizeflag & SUFFIX_ALWAYS)
10614                 *obufp++ = 'q';
10615               break;
10616             }
10617           /* Fall through.  */
10618         case 'P':
10619           if (l == 0)
10620             {
10621               if ((modrm.mod == 3 || !cond)
10622                   && !(sizeflag & SUFFIX_ALWAYS))
10623                 break;
10624           /* Fall through.  */
10625         case 'T':
10626               if ((!(rex & REX_W) && (prefixes & PREFIX_DATA))
10627                   || ((sizeflag & SUFFIX_ALWAYS)
10628                       && address_mode != mode_64bit))
10629                 {
10630                   *obufp++ = (sizeflag & DFLAG) ?
10631                              intel_syntax ? 'd' : 'l' : 'w';
10632                   used_prefixes |= (prefixes & PREFIX_DATA);
10633                 }
10634               else if (sizeflag & SUFFIX_ALWAYS)
10635                 *obufp++ = 'q';
10636             }
10637           else if (l == 1 && last[0] == 'L')
10638             {
10639               if ((prefixes & PREFIX_DATA)
10640                   || (rex & REX_W)
10641                   || (sizeflag & SUFFIX_ALWAYS))
10642                 {
10643                   USED_REX (REX_W);
10644                   if (rex & REX_W)
10645                     *obufp++ = 'q';
10646                   else
10647                     {
10648                       if (sizeflag & DFLAG)
10649                         *obufp++ = intel_syntax ? 'd' : 'l';
10650                       else
10651                         *obufp++ = 'w';
10652                       used_prefixes |= (prefixes & PREFIX_DATA);
10653                     }
10654                 }
10655             }
10656           else
10657             abort ();
10658           break;
10659         case 'Q':
10660           if (l == 0)
10661             {
10662               if (intel_syntax && !alt)
10663                 break;
10664               USED_REX (REX_W);
10665               if ((need_modrm && modrm.mod != 3)
10666                   || (sizeflag & SUFFIX_ALWAYS))
10667                 {
10668                   if (rex & REX_W)
10669                     *obufp++ = 'q';
10670                   else
10671                     {
10672                       if (sizeflag & DFLAG)
10673                         *obufp++ = intel_syntax ? 'd' : 'l';
10674                       else
10675                         *obufp++ = 'w';
10676                       used_prefixes |= (prefixes & PREFIX_DATA);
10677                     }
10678                 }
10679             }
10680           else if (l == 1 && last[0] == 'D')
10681             *obufp++ = vex.w ? 'q' : 'd';
10682           else if (l == 1 && last[0] == 'L')
10683             {
10684               if (cond ? modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)
10685                        : address_mode != mode_64bit)
10686                 break;
10687               if ((rex & REX_W))
10688                 {
10689                   USED_REX (REX_W);
10690                   *obufp++ = 'q';
10691                 }
10692               else if((address_mode == mode_64bit && cond)
10693                       || (sizeflag & SUFFIX_ALWAYS))
10694                 *obufp++ = intel_syntax? 'd' : 'l';
10695             }
10696           else
10697             abort ();
10698           break;
10699         case 'R':
10700           USED_REX (REX_W);
10701           if (rex & REX_W)
10702             *obufp++ = 'q';
10703           else if (sizeflag & DFLAG)
10704             {
10705               if (intel_syntax)
10706                   *obufp++ = 'd';
10707               else
10708                   *obufp++ = 'l';
10709             }
10710           else
10711             *obufp++ = 'w';
10712           if (intel_syntax && !p[1]
10713               && ((rex & REX_W) || (sizeflag & DFLAG)))
10714             *obufp++ = 'e';
10715           if (!(rex & REX_W))
10716             used_prefixes |= (prefixes & PREFIX_DATA);
10717           break;
10718         case 'S':
10719           if (l == 0)
10720             {
10721             case_S:
10722               if (intel_syntax)
10723                 break;
10724               if (sizeflag & SUFFIX_ALWAYS)
10725                 {
10726                   if (rex & REX_W)
10727                     *obufp++ = 'q';
10728                   else
10729                     {
10730                       if (sizeflag & DFLAG)
10731                         *obufp++ = 'l';
10732                       else
10733                         *obufp++ = 'w';
10734                       used_prefixes |= (prefixes & PREFIX_DATA);
10735                     }
10736                 }
10737             }
10738           else if (l == 1 && last[0] == 'L')
10739             {
10740               if (address_mode == mode_64bit
10741                   && !(prefixes & PREFIX_ADDR))
10742                 {
10743                   *obufp++ = 'a';
10744                   *obufp++ = 'b';
10745                   *obufp++ = 's';
10746                 }
10747
10748               goto case_S;
10749             }
10750           else
10751             abort ();
10752           break;
10753         case 'V':
10754           if (l == 0)
10755             abort ();
10756           else if (l == 1
10757                    && (last[0] == 'L' || last[0] == 'X'))
10758             {
10759               if (last[0] == 'X')
10760                 {
10761                   *obufp++ = '{';
10762                   *obufp++ = 'v';
10763                   *obufp++ = 'e';
10764                   *obufp++ = 'x';
10765                   *obufp++ = '}';
10766                 }
10767               else if (rex & REX_W)
10768                 {
10769                   *obufp++ = 'a';
10770                   *obufp++ = 'b';
10771                   *obufp++ = 's';
10772                 }
10773             }
10774           else
10775             abort ();
10776           goto case_S;
10777         case 'W':
10778           if (l == 0)
10779             {
10780               /* operand size flag for cwtl, cbtw */
10781               USED_REX (REX_W);
10782               if (rex & REX_W)
10783                 {
10784                   if (intel_syntax)
10785                     *obufp++ = 'd';
10786                   else
10787                     *obufp++ = 'l';
10788                 }
10789               else if (sizeflag & DFLAG)
10790                 *obufp++ = 'w';
10791               else
10792                 *obufp++ = 'b';
10793               if (!(rex & REX_W))
10794                 used_prefixes |= (prefixes & PREFIX_DATA);
10795             }
10796           else if (l == 1)
10797             {
10798               if (!need_vex)
10799                 abort ();
10800               if (last[0] == 'X')
10801                 *obufp++ = vex.w ? 'd': 's';
10802               else if (last[0] == 'B')
10803                 *obufp++ = vex.w ? 'w': 'b';
10804               else
10805                 abort ();
10806             }
10807           else
10808             abort ();
10809           break;
10810         case 'X':
10811           if (l != 0)
10812             abort ();
10813           if (need_vex
10814               ? vex.prefix == DATA_PREFIX_OPCODE
10815               : prefixes & PREFIX_DATA)
10816             {
10817               *obufp++ = 'd';
10818               used_prefixes |= PREFIX_DATA;
10819             }
10820           else
10821             *obufp++ = 's';
10822           break;
10823         case 'Y':
10824           if (l == 1 && last[0] == 'X')
10825             {
10826               if (!need_vex)
10827                 abort ();
10828               if (intel_syntax
10829                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
10830                 break;
10831               switch (vex.length)
10832                 {
10833                 case 128:
10834                   *obufp++ = 'x';
10835                   break;
10836                 case 256:
10837                   *obufp++ = 'y';
10838                   break;
10839                 case 512:
10840                   if (!vex.evex)
10841                 default:
10842                     abort ();
10843                 }
10844             }
10845           else
10846             abort ();
10847           break;
10848         case 'Z':
10849           if (l == 0)
10850             {
10851               /* These insns ignore ModR/M.mod: Force it to 3 for OP_E().  */
10852               modrm.mod = 3;
10853               if (!intel_syntax && (sizeflag & SUFFIX_ALWAYS))
10854                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
10855             }
10856           else if (l == 1 && last[0] == 'X')
10857             {
10858               if (!vex.evex)
10859                 abort ();
10860               if (intel_syntax
10861                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
10862                 break;
10863               switch (vex.length)
10864                 {
10865                 case 128:
10866                   *obufp++ = 'x';
10867                   break;
10868                 case 256:
10869                   *obufp++ = 'y';
10870                   break;
10871                 case 512:
10872                   *obufp++ = 'z';
10873                   break;
10874                 default:
10875                   abort ();
10876                 }
10877             }
10878           else
10879             abort ();
10880           break;
10881         case '^':
10882           if (intel_syntax)
10883             break;
10884           if (isa64 == intel64 && (rex & REX_W))
10885             {
10886               USED_REX (REX_W);
10887               *obufp++ = 'q';
10888               break;
10889             }
10890           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10891             {
10892               if (sizeflag & DFLAG)
10893                 *obufp++ = 'l';
10894               else
10895                 *obufp++ = 'w';
10896               used_prefixes |= (prefixes & PREFIX_DATA);
10897             }
10898           break;
10899         }
10900
10901       if (len == l)
10902         len = l = 0;
10903     }
10904   *obufp = 0;
10905   mnemonicendp = obufp;
10906   return 0;
10907 }
10908
10909 static void
10910 oappend (const char *s)
10911 {
10912   obufp = stpcpy (obufp, s);
10913 }
10914
10915 static void
10916 append_seg (void)
10917 {
10918   /* Only print the active segment register.  */
10919   if (!active_seg_prefix)
10920     return;
10921
10922   used_prefixes |= active_seg_prefix;
10923   switch (active_seg_prefix)
10924     {
10925     case PREFIX_CS:
10926       oappend_maybe_intel ("%cs:");
10927       break;
10928     case PREFIX_DS:
10929       oappend_maybe_intel ("%ds:");
10930       break;
10931     case PREFIX_SS:
10932       oappend_maybe_intel ("%ss:");
10933       break;
10934     case PREFIX_ES:
10935       oappend_maybe_intel ("%es:");
10936       break;
10937     case PREFIX_FS:
10938       oappend_maybe_intel ("%fs:");
10939       break;
10940     case PREFIX_GS:
10941       oappend_maybe_intel ("%gs:");
10942       break;
10943     default:
10944       break;
10945     }
10946 }
10947
10948 static void
10949 OP_indirE (int bytemode, int sizeflag)
10950 {
10951   if (!intel_syntax)
10952     oappend ("*");
10953   OP_E (bytemode, sizeflag);
10954 }
10955
10956 static void
10957 print_operand_value (char *buf, int hex, bfd_vma disp)
10958 {
10959   if (address_mode == mode_64bit)
10960     {
10961       if (hex)
10962         {
10963           char tmp[30];
10964           int i;
10965           buf[0] = '0';
10966           buf[1] = 'x';
10967           sprintf_vma (tmp, disp);
10968           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
10969           strcpy (buf + 2, tmp + i);
10970         }
10971       else
10972         {
10973           bfd_signed_vma v = disp;
10974           char tmp[30];
10975           int i;
10976           if (v < 0)
10977             {
10978               *(buf++) = '-';
10979               v = -disp;
10980               /* Check for possible overflow on 0x8000000000000000.  */
10981               if (v < 0)
10982                 {
10983                   strcpy (buf, "9223372036854775808");
10984                   return;
10985                 }
10986             }
10987           if (!v)
10988             {
10989               strcpy (buf, "0");
10990               return;
10991             }
10992
10993           i = 0;
10994           tmp[29] = 0;
10995           while (v)
10996             {
10997               tmp[28 - i] = (v % 10) + '0';
10998               v /= 10;
10999               i++;
11000             }
11001           strcpy (buf, tmp + 29 - i);
11002         }
11003     }
11004   else
11005     {
11006       if (hex)
11007         sprintf (buf, "0x%x", (unsigned int) disp);
11008       else
11009         sprintf (buf, "%d", (int) disp);
11010     }
11011 }
11012
11013 /* Put DISP in BUF as signed hex number.  */
11014
11015 static void
11016 print_displacement (char *buf, bfd_vma disp)
11017 {
11018   bfd_signed_vma val = disp;
11019   char tmp[30];
11020   int i, j = 0;
11021
11022   if (val < 0)
11023     {
11024       buf[j++] = '-';
11025       val = -disp;
11026
11027       /* Check for possible overflow.  */
11028       if (val < 0)
11029         {
11030           switch (address_mode)
11031             {
11032             case mode_64bit:
11033               strcpy (buf + j, "0x8000000000000000");
11034               break;
11035             case mode_32bit:
11036               strcpy (buf + j, "0x80000000");
11037               break;
11038             case mode_16bit:
11039               strcpy (buf + j, "0x8000");
11040               break;
11041             }
11042           return;
11043         }
11044     }
11045
11046   buf[j++] = '0';
11047   buf[j++] = 'x';
11048
11049   sprintf_vma (tmp, (bfd_vma) val);
11050   for (i = 0; tmp[i] == '0'; i++)
11051     continue;
11052   if (tmp[i] == '\0')
11053     i--;
11054   strcpy (buf + j, tmp + i);
11055 }
11056
11057 static void
11058 intel_operand_size (int bytemode, int sizeflag)
11059 {
11060   if (vex.b)
11061     {
11062       switch (bytemode)
11063         {
11064         case x_mode:
11065         case evex_half_bcst_xmmq_mode:
11066           if (vex.w)
11067             oappend ("QWORD PTR ");
11068           else
11069             oappend ("DWORD PTR ");
11070           break;
11071         case xh_mode:
11072         case evex_half_bcst_xmmqh_mode:
11073         case evex_half_bcst_xmmqdh_mode:
11074           oappend ("WORD PTR ");
11075           break;
11076         default:
11077           abort ();
11078         }
11079       return;
11080     }
11081   switch (bytemode)
11082     {
11083     case b_mode:
11084     case b_swap_mode:
11085     case db_mode:
11086       oappend ("BYTE PTR ");
11087       break;
11088     case w_mode:
11089     case w_swap_mode:
11090     case dw_mode:
11091       oappend ("WORD PTR ");
11092       break;
11093     case indir_v_mode:
11094       if (address_mode == mode_64bit && isa64 == intel64)
11095         {
11096           oappend ("QWORD PTR ");
11097           break;
11098         }
11099       /* Fall through.  */
11100     case stack_v_mode:
11101       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
11102         {
11103           oappend ("QWORD PTR ");
11104           break;
11105         }
11106       /* Fall through.  */
11107     case v_mode:
11108     case v_swap_mode:
11109     case dq_mode:
11110       USED_REX (REX_W);
11111       if (rex & REX_W)
11112         oappend ("QWORD PTR ");
11113       else if (bytemode == dq_mode)
11114         oappend ("DWORD PTR ");
11115       else
11116         {
11117           if (sizeflag & DFLAG)
11118             oappend ("DWORD PTR ");
11119           else
11120             oappend ("WORD PTR ");
11121           used_prefixes |= (prefixes & PREFIX_DATA);
11122         }
11123       break;
11124     case z_mode:
11125       if ((rex & REX_W) || (sizeflag & DFLAG))
11126         *obufp++ = 'D';
11127       oappend ("WORD PTR ");
11128       if (!(rex & REX_W))
11129         used_prefixes |= (prefixes & PREFIX_DATA);
11130       break;
11131     case a_mode:
11132       if (sizeflag & DFLAG)
11133         oappend ("QWORD PTR ");
11134       else
11135         oappend ("DWORD PTR ");
11136       used_prefixes |= (prefixes & PREFIX_DATA);
11137       break;
11138     case movsxd_mode:
11139       if (!(sizeflag & DFLAG) && isa64 == intel64)
11140         oappend ("WORD PTR ");
11141       else
11142         oappend ("DWORD PTR ");
11143       used_prefixes |= (prefixes & PREFIX_DATA);
11144       break;
11145     case d_mode:
11146     case d_swap_mode:
11147       oappend ("DWORD PTR ");
11148       break;
11149     case q_mode:
11150     case q_swap_mode:
11151       oappend ("QWORD PTR ");
11152       break;
11153     case m_mode:
11154       if (address_mode == mode_64bit)
11155         oappend ("QWORD PTR ");
11156       else
11157         oappend ("DWORD PTR ");
11158       break;
11159     case f_mode:
11160       if (sizeflag & DFLAG)
11161         oappend ("FWORD PTR ");
11162       else
11163         oappend ("DWORD PTR ");
11164       used_prefixes |= (prefixes & PREFIX_DATA);
11165       break;
11166     case t_mode:
11167       oappend ("TBYTE PTR ");
11168       break;
11169     case x_mode:
11170     case xh_mode:
11171     case x_swap_mode:
11172     case evex_x_gscat_mode:
11173     case evex_x_nobcst_mode:
11174     case bw_unit_mode:
11175       if (need_vex)
11176         {
11177           switch (vex.length)
11178             {
11179             case 128:
11180               oappend ("XMMWORD PTR ");
11181               break;
11182             case 256:
11183               oappend ("YMMWORD PTR ");
11184               break;
11185             case 512:
11186               oappend ("ZMMWORD PTR ");
11187               break;
11188             default:
11189               abort ();
11190             }
11191         }
11192       else
11193         oappend ("XMMWORD PTR ");
11194       break;
11195     case xmm_mode:
11196       oappend ("XMMWORD PTR ");
11197       break;
11198     case ymm_mode:
11199       oappend ("YMMWORD PTR ");
11200       break;
11201     case xmmq_mode:
11202     case evex_half_bcst_xmmqh_mode:
11203     case evex_half_bcst_xmmq_mode:
11204       if (!need_vex)
11205         abort ();
11206
11207       switch (vex.length)
11208         {
11209         case 128:
11210           oappend ("QWORD PTR ");
11211           break;
11212         case 256:
11213           oappend ("XMMWORD PTR ");
11214           break;
11215         case 512:
11216           oappend ("YMMWORD PTR ");
11217           break;
11218         default:
11219           abort ();
11220         }
11221       break;
11222     case xmmdw_mode:
11223       if (!need_vex)
11224         abort ();
11225
11226       switch (vex.length)
11227         {
11228         case 128:
11229           oappend ("WORD PTR ");
11230           break;
11231         case 256:
11232           oappend ("DWORD PTR ");
11233           break;
11234         case 512:
11235           oappend ("QWORD PTR ");
11236           break;
11237         default:
11238           abort ();
11239         }
11240       break;
11241     case xmmqd_mode:
11242     case evex_half_bcst_xmmqdh_mode:
11243       if (!need_vex)
11244         abort ();
11245
11246       switch (vex.length)
11247         {
11248         case 128:
11249           oappend ("DWORD PTR ");
11250           break;
11251         case 256:
11252           oappend ("QWORD PTR ");
11253           break;
11254         case 512:
11255           oappend ("XMMWORD PTR ");
11256           break;
11257         default:
11258           abort ();
11259         }
11260       break;
11261     case ymmq_mode:
11262       if (!need_vex)
11263         abort ();
11264
11265       switch (vex.length)
11266         {
11267         case 128:
11268           oappend ("QWORD PTR ");
11269           break;
11270         case 256:
11271           oappend ("YMMWORD PTR ");
11272           break;
11273         case 512:
11274           oappend ("ZMMWORD PTR ");
11275           break;
11276         default:
11277           abort ();
11278         }
11279       break;
11280     case ymmxmm_mode:
11281       if (!need_vex)
11282         abort ();
11283
11284       switch (vex.length)
11285         {
11286         case 128:
11287         case 256:
11288           oappend ("XMMWORD PTR ");
11289           break;
11290         default:
11291           abort ();
11292         }
11293       break;
11294     case o_mode:
11295       oappend ("OWORD PTR ");
11296       break;
11297     case vex_vsib_d_w_dq_mode:
11298     case vex_vsib_q_w_dq_mode:
11299       if (!need_vex)
11300         abort ();
11301
11302       if (vex.w)
11303         oappend ("QWORD PTR ");
11304       else
11305         oappend ("DWORD PTR ");
11306       break;
11307     case mask_bd_mode:
11308       if (!need_vex || vex.length != 128)
11309         abort ();
11310       if (vex.w)
11311         oappend ("DWORD PTR ");
11312       else
11313         oappend ("BYTE PTR ");
11314       break;
11315     case mask_mode:
11316       if (!need_vex)
11317         abort ();
11318       if (vex.w)
11319         oappend ("QWORD PTR ");
11320       else
11321         oappend ("WORD PTR ");
11322       break;
11323     case v_bnd_mode:
11324     case v_bndmk_mode:
11325     default:
11326       break;
11327     }
11328 }
11329
11330 static void
11331 print_register (unsigned int reg, unsigned int rexmask, int bytemode, int sizeflag)
11332 {
11333   const char **names;
11334
11335   USED_REX (rexmask);
11336   if (rex & rexmask)
11337     reg += 8;
11338
11339   switch (bytemode)
11340     {
11341     case b_mode:
11342     case b_swap_mode:
11343       if (reg & 4)
11344         USED_REX (0);
11345       if (rex)
11346         names = names8rex;
11347       else
11348         names = names8;
11349       break;
11350     case w_mode:
11351       names = names16;
11352       break;
11353     case d_mode:
11354     case dw_mode:
11355     case db_mode:
11356       names = names32;
11357       break;
11358     case q_mode:
11359       names = names64;
11360       break;
11361     case m_mode:
11362     case v_bnd_mode:
11363       names = address_mode == mode_64bit ? names64 : names32;
11364       break;
11365     case bnd_mode:
11366     case bnd_swap_mode:
11367       if (reg > 0x3)
11368         {
11369           oappend ("(bad)");
11370           return;
11371         }
11372       names = names_bnd;
11373       break;
11374     case indir_v_mode:
11375       if (address_mode == mode_64bit && isa64 == intel64)
11376         {
11377           names = names64;
11378           break;
11379         }
11380       /* Fall through.  */
11381     case stack_v_mode:
11382       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
11383         {
11384           names = names64;
11385           break;
11386         }
11387       bytemode = v_mode;
11388       /* Fall through.  */
11389     case v_mode:
11390     case v_swap_mode:
11391     case dq_mode:
11392       USED_REX (REX_W);
11393       if (rex & REX_W)
11394         names = names64;
11395       else if (bytemode != v_mode && bytemode != v_swap_mode)
11396         names = names32;
11397       else
11398         {
11399           if (sizeflag & DFLAG)
11400             names = names32;
11401           else
11402             names = names16;
11403           used_prefixes |= (prefixes & PREFIX_DATA);
11404         }
11405       break;
11406     case movsxd_mode:
11407       if (!(sizeflag & DFLAG) && isa64 == intel64)
11408         names = names16;
11409       else
11410         names = names32;
11411       used_prefixes |= (prefixes & PREFIX_DATA);
11412       break;
11413     case va_mode:
11414       names = (address_mode == mode_64bit
11415                ? names64 : names32);
11416       if (!(prefixes & PREFIX_ADDR))
11417         names = (address_mode == mode_16bit
11418                      ? names16 : names);
11419       else
11420         {
11421           /* Remove "addr16/addr32".  */
11422           all_prefixes[last_addr_prefix] = 0;
11423           names = (address_mode != mode_32bit
11424                        ? names32 : names16);
11425           used_prefixes |= PREFIX_ADDR;
11426         }
11427       break;
11428     case mask_bd_mode:
11429     case mask_mode:
11430       if (reg > 0x7)
11431         {
11432           oappend ("(bad)");
11433           return;
11434         }
11435       names = names_mask;
11436       break;
11437     case 0:
11438       return;
11439     default:
11440       oappend (INTERNAL_DISASSEMBLER_ERROR);
11441       return;
11442     }
11443   oappend (names[reg]);
11444 }
11445
11446 static void
11447 OP_E_memory (int bytemode, int sizeflag)
11448 {
11449   bfd_vma disp = 0;
11450   int add = (rex & REX_B) ? 8 : 0;
11451   int riprel = 0;
11452   int shift;
11453
11454   if (vex.evex)
11455     {
11456       switch (bytemode)
11457         {
11458         case dw_mode:
11459         case w_mode:
11460         case w_swap_mode:
11461           shift = 1;
11462           break;
11463         case db_mode:
11464         case b_mode:
11465           shift = 0;
11466           break;
11467         case dq_mode:
11468           if (address_mode != mode_64bit)
11469             {
11470         case d_mode:
11471         case d_swap_mode:
11472               shift = 2;
11473               break;
11474             }
11475             /* fall through */
11476         case vex_vsib_d_w_dq_mode:
11477         case vex_vsib_q_w_dq_mode:
11478         case evex_x_gscat_mode:
11479           shift = vex.w ? 3 : 2;
11480           break;
11481         case xh_mode:
11482         case evex_half_bcst_xmmqh_mode:
11483         case evex_half_bcst_xmmqdh_mode:
11484           if (vex.b)
11485             {
11486               shift = vex.w ? 2 : 1;
11487               break;
11488             }
11489           /* Fall through.  */
11490         case x_mode:
11491         case evex_half_bcst_xmmq_mode:
11492           if (vex.b)
11493             {
11494               shift = vex.w ? 3 : 2;
11495               break;
11496             }
11497           /* Fall through.  */
11498         case xmmqd_mode:
11499         case xmmdw_mode:
11500         case xmmq_mode:
11501         case ymmq_mode:
11502         case evex_x_nobcst_mode:
11503         case x_swap_mode:
11504           switch (vex.length)
11505             {
11506             case 128:
11507               shift = 4;
11508               break;
11509             case 256:
11510               shift = 5;
11511               break;
11512             case 512:
11513               shift = 6;
11514               break;
11515             default:
11516               abort ();
11517             }
11518           /* Make necessary corrections to shift for modes that need it.  */
11519           if (bytemode == xmmq_mode
11520               || bytemode == evex_half_bcst_xmmqh_mode
11521               || bytemode == evex_half_bcst_xmmq_mode
11522               || (bytemode == ymmq_mode && vex.length == 128))
11523             shift -= 1;
11524           else if (bytemode == xmmqd_mode
11525                    || bytemode == evex_half_bcst_xmmqdh_mode)
11526             shift -= 2;
11527           else if (bytemode == xmmdw_mode)
11528             shift -= 3;
11529           break;
11530         case ymm_mode:
11531           shift = 5;
11532           break;
11533         case xmm_mode:
11534           shift = 4;
11535           break;
11536         case q_mode:
11537         case q_swap_mode:
11538           shift = 3;
11539           break;
11540         case bw_unit_mode:
11541           shift = vex.w ? 1 : 0;
11542           break;
11543         default:
11544           abort ();
11545         }
11546     }
11547   else
11548     shift = 0;
11549
11550   USED_REX (REX_B);
11551   if (intel_syntax)
11552     intel_operand_size (bytemode, sizeflag);
11553   append_seg ();
11554
11555   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
11556     {
11557       /* 32/64 bit address mode */
11558       int havedisp;
11559       int havesib;
11560       int havebase;
11561       int haveindex;
11562       int needindex;
11563       int needaddr32;
11564       int base, rbase;
11565       int vindex = 0;
11566       int scale = 0;
11567       int addr32flag = !((sizeflag & AFLAG)
11568                          || bytemode == v_bnd_mode
11569                          || bytemode == v_bndmk_mode
11570                          || bytemode == bnd_mode
11571                          || bytemode == bnd_swap_mode);
11572       bool check_gather = false;
11573       const char **indexes64 = names64;
11574       const char **indexes32 = names32;
11575
11576       havesib = 0;
11577       havebase = 1;
11578       haveindex = 0;
11579       base = modrm.rm;
11580
11581       if (base == 4)
11582         {
11583           havesib = 1;
11584           vindex = sib.index;
11585           USED_REX (REX_X);
11586           if (rex & REX_X)
11587             vindex += 8;
11588           switch (bytemode)
11589             {
11590             case vex_vsib_d_w_dq_mode:
11591             case vex_vsib_q_w_dq_mode:
11592               if (!need_vex)
11593                 abort ();
11594               if (vex.evex)
11595                 {
11596                   if (!vex.v)
11597                     vindex += 16;
11598                   check_gather = obufp == op_out[1];
11599                 }
11600
11601               haveindex = 1;
11602               switch (vex.length)
11603                 {
11604                 case 128:
11605                   indexes64 = indexes32 = names_xmm;
11606                   break;
11607                 case 256:
11608                   if (!vex.w
11609                       || bytemode == vex_vsib_q_w_dq_mode)
11610                     indexes64 = indexes32 = names_ymm;
11611                   else
11612                     indexes64 = indexes32 = names_xmm;
11613                   break;
11614                 case 512:
11615                   if (!vex.w
11616                       || bytemode == vex_vsib_q_w_dq_mode)
11617                     indexes64 = indexes32 = names_zmm;
11618                   else
11619                     indexes64 = indexes32 = names_ymm;
11620                   break;
11621                 default:
11622                   abort ();
11623                 }
11624               break;
11625             default:
11626               haveindex = vindex != 4;
11627               break;
11628             }
11629           scale = sib.scale;
11630           base = sib.base;
11631           codep++;
11632         }
11633       else
11634         {
11635           /* Check for mandatory SIB.  */
11636           if (bytemode == vex_vsib_d_w_dq_mode
11637               || bytemode == vex_vsib_q_w_dq_mode
11638               || bytemode == vex_sibmem_mode)
11639             {
11640               oappend ("(bad)");
11641               return;
11642             }
11643         }
11644       rbase = base + add;
11645
11646       switch (modrm.mod)
11647         {
11648         case 0:
11649           if (base == 5)
11650             {
11651               havebase = 0;
11652               if (address_mode == mode_64bit && !havesib)
11653                 riprel = 1;
11654               disp = get32s ();
11655               if (riprel && bytemode == v_bndmk_mode)
11656                 {
11657                   oappend ("(bad)");
11658                   return;
11659                 }
11660             }
11661           break;
11662         case 1:
11663           FETCH_DATA (the_info, codep + 1);
11664           disp = *codep++;
11665           if ((disp & 0x80) != 0)
11666             disp -= 0x100;
11667           if (vex.evex && shift > 0)
11668             disp <<= shift;
11669           break;
11670         case 2:
11671           disp = get32s ();
11672           break;
11673         }
11674
11675       needindex = 0;
11676       needaddr32 = 0;
11677       if (havesib
11678           && !havebase
11679           && !haveindex
11680           && address_mode != mode_16bit)
11681         {
11682           if (address_mode == mode_64bit)
11683             {
11684               if (addr32flag)
11685                 {
11686                   /* Without base nor index registers, zero-extend the
11687                      lower 32-bit displacement to 64 bits.  */
11688                   disp = (unsigned int) disp;
11689                   needindex = 1;
11690                 }
11691               needaddr32 = 1;
11692             }
11693           else
11694             {
11695               /* In 32-bit mode, we need index register to tell [offset]
11696                  from [eiz*1 + offset].  */
11697               needindex = 1;
11698             }
11699         }
11700
11701       havedisp = (havebase
11702                   || needindex
11703                   || (havesib && (haveindex || scale != 0)));
11704
11705       if (!intel_syntax)
11706         if (modrm.mod != 0 || base == 5)
11707           {
11708             if (havedisp || riprel)
11709               print_displacement (scratchbuf, disp);
11710             else
11711               print_operand_value (scratchbuf, 1, disp);
11712             oappend (scratchbuf);
11713             if (riprel)
11714               {
11715                 set_op (disp, 1);
11716                 oappend (!addr32flag ? "(%rip)" : "(%eip)");
11717               }
11718           }
11719
11720       if ((havebase || haveindex || needindex || needaddr32 || riprel)
11721           && (address_mode != mode_64bit
11722               || ((bytemode != v_bnd_mode)
11723                   && (bytemode != v_bndmk_mode)
11724                   && (bytemode != bnd_mode)
11725                   && (bytemode != bnd_swap_mode))))
11726         used_prefixes |= PREFIX_ADDR;
11727
11728       if (havedisp || (intel_syntax && riprel))
11729         {
11730           *obufp++ = open_char;
11731           if (intel_syntax && riprel)
11732             {
11733               set_op (disp, 1);
11734               oappend (!addr32flag ? "rip" : "eip");
11735             }
11736           *obufp = '\0';
11737           if (havebase)
11738             oappend (address_mode == mode_64bit && !addr32flag
11739                      ? names64[rbase] : names32[rbase]);
11740           if (havesib)
11741             {
11742               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
11743                  print index to tell base + index from base.  */
11744               if (scale != 0
11745                   || needindex
11746                   || haveindex
11747                   || (havebase && base != ESP_REG_NUM))
11748                 {
11749                   if (!intel_syntax || havebase)
11750                     {
11751                       *obufp++ = separator_char;
11752                       *obufp = '\0';
11753                     }
11754                   if (haveindex)
11755                     {
11756                       if (address_mode == mode_64bit || vindex < 16)
11757                         oappend (address_mode == mode_64bit && !addr32flag
11758                                  ? indexes64[vindex] : indexes32[vindex]);
11759                       else
11760                         oappend ("(bad)");
11761                     }
11762                   else
11763                     oappend (address_mode == mode_64bit && !addr32flag
11764                              ? index64 : index32);
11765
11766                   *obufp++ = scale_char;
11767                   *obufp = '\0';
11768                   sprintf (scratchbuf, "%d", 1 << scale);
11769                   oappend (scratchbuf);
11770                 }
11771             }
11772           if (intel_syntax
11773               && (disp || modrm.mod != 0 || base == 5))
11774             {
11775               if (!havedisp || (bfd_signed_vma) disp >= 0)
11776                 {
11777                   *obufp++ = '+';
11778                   *obufp = '\0';
11779                 }
11780               else if (modrm.mod != 1 && disp != -disp)
11781                 {
11782                   *obufp++ = '-';
11783                   *obufp = '\0';
11784                   disp = -disp;
11785                 }
11786
11787               if (havedisp)
11788                 print_displacement (scratchbuf, disp);
11789               else
11790                 print_operand_value (scratchbuf, 1, disp);
11791               oappend (scratchbuf);
11792             }
11793
11794           *obufp++ = close_char;
11795           *obufp = '\0';
11796
11797           if (check_gather)
11798             {
11799               /* Both XMM/YMM/ZMM registers must be distinct.  */
11800               int modrm_reg = modrm.reg;
11801
11802               if (rex & REX_R)
11803                 modrm_reg += 8;
11804               if (!vex.r)
11805                 modrm_reg += 16;
11806               if (vindex == modrm_reg)
11807                 oappend ("/(bad)");
11808             }
11809         }
11810       else if (intel_syntax)
11811         {
11812           if (modrm.mod != 0 || base == 5)
11813             {
11814               if (!active_seg_prefix)
11815                 {
11816                   oappend (names_seg[ds_reg - es_reg]);
11817                   oappend (":");
11818                 }
11819               print_operand_value (scratchbuf, 1, disp);
11820               oappend (scratchbuf);
11821             }
11822         }
11823     }
11824   else if (bytemode == v_bnd_mode
11825            || bytemode == v_bndmk_mode
11826            || bytemode == bnd_mode
11827            || bytemode == bnd_swap_mode
11828            || bytemode == vex_vsib_d_w_dq_mode
11829            || bytemode == vex_vsib_q_w_dq_mode)
11830     {
11831       oappend ("(bad)");
11832       return;
11833     }
11834   else
11835     {
11836       /* 16 bit address mode */
11837       used_prefixes |= prefixes & PREFIX_ADDR;
11838       switch (modrm.mod)
11839         {
11840         case 0:
11841           if (modrm.rm == 6)
11842             {
11843               disp = get16 ();
11844               if ((disp & 0x8000) != 0)
11845                 disp -= 0x10000;
11846             }
11847           break;
11848         case 1:
11849           FETCH_DATA (the_info, codep + 1);
11850           disp = *codep++;
11851           if ((disp & 0x80) != 0)
11852             disp -= 0x100;
11853           if (vex.evex && shift > 0)
11854             disp <<= shift;
11855           break;
11856         case 2:
11857           disp = get16 ();
11858           if ((disp & 0x8000) != 0)
11859             disp -= 0x10000;
11860           break;
11861         }
11862
11863       if (!intel_syntax)
11864         if (modrm.mod != 0 || modrm.rm == 6)
11865           {
11866             print_displacement (scratchbuf, disp);
11867             oappend (scratchbuf);
11868           }
11869
11870       if (modrm.mod != 0 || modrm.rm != 6)
11871         {
11872           *obufp++ = open_char;
11873           *obufp = '\0';
11874           oappend (index16[modrm.rm]);
11875           if (intel_syntax
11876               && (disp || modrm.mod != 0 || modrm.rm == 6))
11877             {
11878               if ((bfd_signed_vma) disp >= 0)
11879                 {
11880                   *obufp++ = '+';
11881                   *obufp = '\0';
11882                 }
11883               else if (modrm.mod != 1)
11884                 {
11885                   *obufp++ = '-';
11886                   *obufp = '\0';
11887                   disp = -disp;
11888                 }
11889
11890               print_displacement (scratchbuf, disp);
11891               oappend (scratchbuf);
11892             }
11893
11894           *obufp++ = close_char;
11895           *obufp = '\0';
11896         }
11897       else if (intel_syntax)
11898         {
11899           if (!active_seg_prefix)
11900             {
11901               oappend (names_seg[ds_reg - es_reg]);
11902               oappend (":");
11903             }
11904           print_operand_value (scratchbuf, 1, disp & 0xffff);
11905           oappend (scratchbuf);
11906         }
11907     }
11908   if (vex.b)
11909     {
11910       evex_used |= EVEX_b_used;
11911       if (bytemode == xh_mode)
11912         {
11913           if (vex.w)
11914             {
11915               abort ();
11916             }
11917           else
11918             {
11919               switch (vex.length)
11920                 {
11921                 case 128:
11922                   oappend ("{1to8}");
11923                   break;
11924                 case 256:
11925                   oappend ("{1to16}");
11926                   break;
11927                 case 512:
11928                   oappend ("{1to32}");
11929                   break;
11930                 default:
11931                   abort ();
11932                 }
11933             }
11934         }
11935       else if (vex.w
11936           || bytemode == evex_half_bcst_xmmqdh_mode
11937           || bytemode == evex_half_bcst_xmmq_mode)
11938         {
11939           switch (vex.length)
11940             {
11941             case 128:
11942               oappend ("{1to2}");
11943               break;
11944             case 256:
11945               oappend ("{1to4}");
11946               break;
11947             case 512:
11948               oappend ("{1to8}");
11949               break;
11950             default:
11951               abort ();
11952             }
11953         }
11954       else if (bytemode == x_mode
11955           || bytemode == evex_half_bcst_xmmqh_mode)
11956         {
11957           switch (vex.length)
11958             {
11959             case 128:
11960               oappend ("{1to4}");
11961               break;
11962             case 256:
11963               oappend ("{1to8}");
11964               break;
11965             case 512:
11966               oappend ("{1to16}");
11967               break;
11968             default:
11969               abort ();
11970             }
11971         }
11972       else
11973         /* If operand doesn't allow broadcast, vex.b should be 0.  */
11974         oappend ("{bad}");
11975     }
11976 }
11977
11978 static void
11979 OP_E (int bytemode, int sizeflag)
11980 {
11981   /* Skip mod/rm byte.  */
11982   MODRM_CHECK;
11983   codep++;
11984
11985   if (modrm.mod == 3)
11986     {
11987       if ((sizeflag & SUFFIX_ALWAYS)
11988           && (bytemode == b_swap_mode
11989               || bytemode == bnd_swap_mode
11990               || bytemode == v_swap_mode))
11991         swap_operand ();
11992
11993       print_register (modrm.rm, REX_B, bytemode, sizeflag);
11994     }
11995   else
11996     OP_E_memory (bytemode, sizeflag);
11997 }
11998
11999 static void
12000 OP_G (int bytemode, int sizeflag)
12001 {
12002   if (vex.evex && !vex.r && address_mode == mode_64bit)
12003     {
12004       oappend ("(bad)");
12005       return;
12006     }
12007
12008   print_register (modrm.reg, REX_R, bytemode, sizeflag);
12009 }
12010
12011 static bfd_vma
12012 get64 (void)
12013 {
12014   bfd_vma x;
12015 #ifdef BFD64
12016   unsigned int a;
12017   unsigned int b;
12018
12019   FETCH_DATA (the_info, codep + 8);
12020   a = *codep++ & 0xff;
12021   a |= (*codep++ & 0xff) << 8;
12022   a |= (*codep++ & 0xff) << 16;
12023   a |= (*codep++ & 0xffu) << 24;
12024   b = *codep++ & 0xff;
12025   b |= (*codep++ & 0xff) << 8;
12026   b |= (*codep++ & 0xff) << 16;
12027   b |= (*codep++ & 0xffu) << 24;
12028   x = a + ((bfd_vma) b << 32);
12029 #else
12030   abort ();
12031   x = 0;
12032 #endif
12033   return x;
12034 }
12035
12036 static bfd_signed_vma
12037 get32 (void)
12038 {
12039   bfd_vma x = 0;
12040
12041   FETCH_DATA (the_info, codep + 4);
12042   x = *codep++ & (bfd_vma) 0xff;
12043   x |= (*codep++ & (bfd_vma) 0xff) << 8;
12044   x |= (*codep++ & (bfd_vma) 0xff) << 16;
12045   x |= (*codep++ & (bfd_vma) 0xff) << 24;
12046   return x;
12047 }
12048
12049 static bfd_signed_vma
12050 get32s (void)
12051 {
12052   bfd_vma x = 0;
12053
12054   FETCH_DATA (the_info, codep + 4);
12055   x = *codep++ & (bfd_vma) 0xff;
12056   x |= (*codep++ & (bfd_vma) 0xff) << 8;
12057   x |= (*codep++ & (bfd_vma) 0xff) << 16;
12058   x |= (*codep++ & (bfd_vma) 0xff) << 24;
12059
12060   x = (x ^ ((bfd_vma) 1 << 31)) - ((bfd_vma) 1 << 31);
12061
12062   return x;
12063 }
12064
12065 static int
12066 get16 (void)
12067 {
12068   int x = 0;
12069
12070   FETCH_DATA (the_info, codep + 2);
12071   x = *codep++ & 0xff;
12072   x |= (*codep++ & 0xff) << 8;
12073   return x;
12074 }
12075
12076 static void
12077 set_op (bfd_vma op, int riprel)
12078 {
12079   op_index[op_ad] = op_ad;
12080   if (address_mode == mode_64bit)
12081     {
12082       op_address[op_ad] = op;
12083       op_riprel[op_ad] = riprel;
12084     }
12085   else
12086     {
12087       /* Mask to get a 32-bit address.  */
12088       op_address[op_ad] = op & 0xffffffff;
12089       op_riprel[op_ad] = riprel & 0xffffffff;
12090     }
12091 }
12092
12093 static void
12094 OP_REG (int code, int sizeflag)
12095 {
12096   const char *s;
12097   int add;
12098
12099   switch (code)
12100     {
12101     case es_reg: case ss_reg: case cs_reg:
12102     case ds_reg: case fs_reg: case gs_reg:
12103       oappend (names_seg[code - es_reg]);
12104       return;
12105     }
12106
12107   USED_REX (REX_B);
12108   if (rex & REX_B)
12109     add = 8;
12110   else
12111     add = 0;
12112
12113   switch (code)
12114     {
12115     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
12116     case sp_reg: case bp_reg: case si_reg: case di_reg:
12117       s = names16[code - ax_reg + add];
12118       break;
12119     case ah_reg: case ch_reg: case dh_reg: case bh_reg:
12120       USED_REX (0);
12121       /* Fall through.  */
12122     case al_reg: case cl_reg: case dl_reg: case bl_reg:
12123       if (rex)
12124         s = names8rex[code - al_reg + add];
12125       else
12126         s = names8[code - al_reg];
12127       break;
12128     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
12129     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
12130       if (address_mode == mode_64bit
12131           && ((sizeflag & DFLAG) || (rex & REX_W)))
12132         {
12133           s = names64[code - rAX_reg + add];
12134           break;
12135         }
12136       code += eAX_reg - rAX_reg;
12137       /* Fall through.  */
12138     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
12139     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
12140       USED_REX (REX_W);
12141       if (rex & REX_W)
12142         s = names64[code - eAX_reg + add];
12143       else
12144         {
12145           if (sizeflag & DFLAG)
12146             s = names32[code - eAX_reg + add];
12147           else
12148             s = names16[code - eAX_reg + add];
12149           used_prefixes |= (prefixes & PREFIX_DATA);
12150         }
12151       break;
12152     default:
12153       s = INTERNAL_DISASSEMBLER_ERROR;
12154       break;
12155     }
12156   oappend (s);
12157 }
12158
12159 static void
12160 OP_IMREG (int code, int sizeflag)
12161 {
12162   const char *s;
12163
12164   switch (code)
12165     {
12166     case indir_dx_reg:
12167       if (intel_syntax)
12168         s = "dx";
12169       else
12170         s = "(%dx)";
12171       break;
12172     case al_reg: case cl_reg:
12173       s = names8[code - al_reg];
12174       break;
12175     case eAX_reg:
12176       USED_REX (REX_W);
12177       if (rex & REX_W)
12178         {
12179           s = *names64;
12180           break;
12181         }
12182       /* Fall through.  */
12183     case z_mode_ax_reg:
12184       if ((rex & REX_W) || (sizeflag & DFLAG))
12185         s = *names32;
12186       else
12187         s = *names16;
12188       if (!(rex & REX_W))
12189         used_prefixes |= (prefixes & PREFIX_DATA);
12190       break;
12191     default:
12192       s = INTERNAL_DISASSEMBLER_ERROR;
12193       break;
12194     }
12195   oappend (s);
12196 }
12197
12198 static void
12199 OP_I (int bytemode, int sizeflag)
12200 {
12201   bfd_signed_vma op;
12202   bfd_signed_vma mask = -1;
12203
12204   switch (bytemode)
12205     {
12206     case b_mode:
12207       FETCH_DATA (the_info, codep + 1);
12208       op = *codep++;
12209       mask = 0xff;
12210       break;
12211     case v_mode:
12212       USED_REX (REX_W);
12213       if (rex & REX_W)
12214         op = get32s ();
12215       else
12216         {
12217           if (sizeflag & DFLAG)
12218             {
12219               op = get32 ();
12220               mask = 0xffffffff;
12221             }
12222           else
12223             {
12224               op = get16 ();
12225               mask = 0xfffff;
12226             }
12227           used_prefixes |= (prefixes & PREFIX_DATA);
12228         }
12229       break;
12230     case d_mode:
12231       mask = 0xffffffff;
12232       op = get32 ();
12233       break;
12234     case w_mode:
12235       mask = 0xfffff;
12236       op = get16 ();
12237       break;
12238     case const_1_mode:
12239       if (intel_syntax)
12240         oappend ("1");
12241       return;
12242     default:
12243       oappend (INTERNAL_DISASSEMBLER_ERROR);
12244       return;
12245     }
12246
12247   op &= mask;
12248   scratchbuf[0] = '$';
12249   print_operand_value (scratchbuf + 1, 1, op);
12250   oappend_maybe_intel (scratchbuf);
12251   scratchbuf[0] = '\0';
12252 }
12253
12254 static void
12255 OP_I64 (int bytemode, int sizeflag)
12256 {
12257   if (bytemode != v_mode || address_mode != mode_64bit || !(rex & REX_W))
12258     {
12259       OP_I (bytemode, sizeflag);
12260       return;
12261     }
12262
12263   USED_REX (REX_W);
12264
12265   scratchbuf[0] = '$';
12266   print_operand_value (scratchbuf + 1, 1, get64 ());
12267   oappend_maybe_intel (scratchbuf);
12268   scratchbuf[0] = '\0';
12269 }
12270
12271 static void
12272 OP_sI (int bytemode, int sizeflag)
12273 {
12274   bfd_signed_vma op;
12275
12276   switch (bytemode)
12277     {
12278     case b_mode:
12279     case b_T_mode:
12280       FETCH_DATA (the_info, codep + 1);
12281       op = *codep++;
12282       if ((op & 0x80) != 0)
12283         op -= 0x100;
12284       if (bytemode == b_T_mode)
12285         {
12286           if (address_mode != mode_64bit
12287               || !((sizeflag & DFLAG) || (rex & REX_W)))
12288             {
12289               /* The operand-size prefix is overridden by a REX prefix.  */
12290               if ((sizeflag & DFLAG) || (rex & REX_W))
12291                 op &= 0xffffffff;
12292               else
12293                 op &= 0xffff;
12294           }
12295         }
12296       else
12297         {
12298           if (!(rex & REX_W))
12299             {
12300               if (sizeflag & DFLAG)
12301                 op &= 0xffffffff;
12302               else
12303                 op &= 0xffff;
12304             }
12305         }
12306       break;
12307     case v_mode:
12308       /* The operand-size prefix is overridden by a REX prefix.  */
12309       if ((sizeflag & DFLAG) || (rex & REX_W))
12310         op = get32s ();
12311       else
12312         op = get16 ();
12313       break;
12314     default:
12315       oappend (INTERNAL_DISASSEMBLER_ERROR);
12316       return;
12317     }
12318
12319   scratchbuf[0] = '$';
12320   print_operand_value (scratchbuf + 1, 1, op);
12321   oappend_maybe_intel (scratchbuf);
12322 }
12323
12324 static void
12325 OP_J (int bytemode, int sizeflag)
12326 {
12327   bfd_vma disp;
12328   bfd_vma mask = -1;
12329   bfd_vma segment = 0;
12330
12331   switch (bytemode)
12332     {
12333     case b_mode:
12334       FETCH_DATA (the_info, codep + 1);
12335       disp = *codep++;
12336       if ((disp & 0x80) != 0)
12337         disp -= 0x100;
12338       break;
12339     case v_mode:
12340     case dqw_mode:
12341       if ((sizeflag & DFLAG)
12342           || (address_mode == mode_64bit
12343               && ((isa64 == intel64 && bytemode != dqw_mode)
12344                   || (rex & REX_W))))
12345         disp = get32s ();
12346       else
12347         {
12348           disp = get16 ();
12349           if ((disp & 0x8000) != 0)
12350             disp -= 0x10000;
12351           /* In 16bit mode, address is wrapped around at 64k within
12352              the same segment.  Otherwise, a data16 prefix on a jump
12353              instruction means that the pc is masked to 16 bits after
12354              the displacement is added!  */
12355           mask = 0xffff;
12356           if ((prefixes & PREFIX_DATA) == 0)
12357             segment = ((start_pc + (codep - start_codep))
12358                        & ~((bfd_vma) 0xffff));
12359         }
12360       if (address_mode != mode_64bit
12361           || (isa64 != intel64 && !(rex & REX_W)))
12362         used_prefixes |= (prefixes & PREFIX_DATA);
12363       break;
12364     default:
12365       oappend (INTERNAL_DISASSEMBLER_ERROR);
12366       return;
12367     }
12368   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
12369   set_op (disp, 0);
12370   print_operand_value (scratchbuf, 1, disp);
12371   oappend (scratchbuf);
12372 }
12373
12374 static void
12375 OP_SEG (int bytemode, int sizeflag)
12376 {
12377   if (bytemode == w_mode)
12378     oappend (names_seg[modrm.reg]);
12379   else
12380     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
12381 }
12382
12383 static void
12384 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
12385 {
12386   int seg, offset;
12387
12388   if (sizeflag & DFLAG)
12389     {
12390       offset = get32 ();
12391       seg = get16 ();
12392     }
12393   else
12394     {
12395       offset = get16 ();
12396       seg = get16 ();
12397     }
12398   used_prefixes |= (prefixes & PREFIX_DATA);
12399   if (intel_syntax)
12400     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
12401   else
12402     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
12403   oappend (scratchbuf);
12404 }
12405
12406 static void
12407 OP_OFF (int bytemode, int sizeflag)
12408 {
12409   bfd_vma off;
12410
12411   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12412     intel_operand_size (bytemode, sizeflag);
12413   append_seg ();
12414
12415   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
12416     off = get32 ();
12417   else
12418     off = get16 ();
12419
12420   if (intel_syntax)
12421     {
12422       if (!active_seg_prefix)
12423         {
12424           oappend (names_seg[ds_reg - es_reg]);
12425           oappend (":");
12426         }
12427     }
12428   print_operand_value (scratchbuf, 1, off);
12429   oappend (scratchbuf);
12430 }
12431
12432 static void
12433 OP_OFF64 (int bytemode, int sizeflag)
12434 {
12435   bfd_vma off;
12436
12437   if (address_mode != mode_64bit
12438       || (prefixes & PREFIX_ADDR))
12439     {
12440       OP_OFF (bytemode, sizeflag);
12441       return;
12442     }
12443
12444   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12445     intel_operand_size (bytemode, sizeflag);
12446   append_seg ();
12447
12448   off = get64 ();
12449
12450   if (intel_syntax)
12451     {
12452       if (!active_seg_prefix)
12453         {
12454           oappend (names_seg[ds_reg - es_reg]);
12455           oappend (":");
12456         }
12457     }
12458   print_operand_value (scratchbuf, 1, off);
12459   oappend (scratchbuf);
12460 }
12461
12462 static void
12463 ptr_reg (int code, int sizeflag)
12464 {
12465   const char *s;
12466
12467   *obufp++ = open_char;
12468   used_prefixes |= (prefixes & PREFIX_ADDR);
12469   if (address_mode == mode_64bit)
12470     {
12471       if (!(sizeflag & AFLAG))
12472         s = names32[code - eAX_reg];
12473       else
12474         s = names64[code - eAX_reg];
12475     }
12476   else if (sizeflag & AFLAG)
12477     s = names32[code - eAX_reg];
12478   else
12479     s = names16[code - eAX_reg];
12480   oappend (s);
12481   *obufp++ = close_char;
12482   *obufp = 0;
12483 }
12484
12485 static void
12486 OP_ESreg (int code, int sizeflag)
12487 {
12488   if (intel_syntax)
12489     {
12490       switch (codep[-1])
12491         {
12492         case 0x6d:      /* insw/insl */
12493           intel_operand_size (z_mode, sizeflag);
12494           break;
12495         case 0xa5:      /* movsw/movsl/movsq */
12496         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
12497         case 0xab:      /* stosw/stosl */
12498         case 0xaf:      /* scasw/scasl */
12499           intel_operand_size (v_mode, sizeflag);
12500           break;
12501         default:
12502           intel_operand_size (b_mode, sizeflag);
12503         }
12504     }
12505   oappend_maybe_intel ("%es:");
12506   ptr_reg (code, sizeflag);
12507 }
12508
12509 static void
12510 OP_DSreg (int code, int sizeflag)
12511 {
12512   if (intel_syntax)
12513     {
12514       switch (codep[-1])
12515         {
12516         case 0x6f:      /* outsw/outsl */
12517           intel_operand_size (z_mode, sizeflag);
12518           break;
12519         case 0xa5:      /* movsw/movsl/movsq */
12520         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
12521         case 0xad:      /* lodsw/lodsl/lodsq */
12522           intel_operand_size (v_mode, sizeflag);
12523           break;
12524         default:
12525           intel_operand_size (b_mode, sizeflag);
12526         }
12527     }
12528   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
12529      default segment register DS is printed.  */
12530   if (!active_seg_prefix)
12531     active_seg_prefix = PREFIX_DS;
12532   append_seg ();
12533   ptr_reg (code, sizeflag);
12534 }
12535
12536 static void
12537 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12538 {
12539   int add;
12540   if (rex & REX_R)
12541     {
12542       USED_REX (REX_R);
12543       add = 8;
12544     }
12545   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
12546     {
12547       all_prefixes[last_lock_prefix] = 0;
12548       used_prefixes |= PREFIX_LOCK;
12549       add = 8;
12550     }
12551   else
12552     add = 0;
12553   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
12554   oappend_maybe_intel (scratchbuf);
12555 }
12556
12557 static void
12558 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12559 {
12560   int add;
12561   USED_REX (REX_R);
12562   if (rex & REX_R)
12563     add = 8;
12564   else
12565     add = 0;
12566   if (intel_syntax)
12567     sprintf (scratchbuf, "dr%d", modrm.reg + add);
12568   else
12569     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
12570   oappend (scratchbuf);
12571 }
12572
12573 static void
12574 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12575 {
12576   sprintf (scratchbuf, "%%tr%d", modrm.reg);
12577   oappend_maybe_intel (scratchbuf);
12578 }
12579
12580 static void
12581 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12582 {
12583   int reg = modrm.reg;
12584   const char **names;
12585
12586   used_prefixes |= (prefixes & PREFIX_DATA);
12587   if (prefixes & PREFIX_DATA)
12588     {
12589       names = names_xmm;
12590       USED_REX (REX_R);
12591       if (rex & REX_R)
12592         reg += 8;
12593     }
12594   else
12595     names = names_mm;
12596   oappend (names[reg]);
12597 }
12598
12599 static void
12600 print_vector_reg (unsigned int reg, int bytemode)
12601 {
12602   const char **names;
12603
12604   if (bytemode == xmmq_mode
12605       || bytemode == evex_half_bcst_xmmqh_mode
12606       || bytemode == evex_half_bcst_xmmq_mode)
12607     {
12608       switch (vex.length)
12609         {
12610         case 128:
12611         case 256:
12612           names = names_xmm;
12613           break;
12614         case 512:
12615           names = names_ymm;
12616           break;
12617         default:
12618           abort ();
12619         }
12620     }
12621   else if (bytemode == ymm_mode)
12622     names = names_ymm;
12623   else if (bytemode == tmm_mode)
12624     {
12625       if (reg >= 8)
12626         {
12627           oappend ("(bad)");
12628           return;
12629         }
12630       names = names_tmm;
12631     }
12632   else if (need_vex
12633            && bytemode != xmm_mode
12634            && bytemode != scalar_mode
12635            && bytemode != xmmdw_mode
12636            && bytemode != xmmqd_mode
12637            && bytemode != evex_half_bcst_xmmqdh_mode
12638            && bytemode != w_swap_mode
12639            && bytemode != b_mode
12640            && bytemode != w_mode
12641            && bytemode != d_mode
12642            && bytemode != q_mode)
12643     {
12644       switch (vex.length)
12645         {
12646         case 128:
12647           names = names_xmm;
12648           break;
12649         case 256:
12650           if (vex.w
12651               || bytemode != vex_vsib_q_w_dq_mode)
12652             names = names_ymm;
12653           else
12654             names = names_xmm;
12655           break;
12656         case 512:
12657           if (vex.w
12658               || bytemode != vex_vsib_q_w_dq_mode)
12659             names = names_zmm;
12660           else
12661             names = names_ymm;
12662           break;
12663         default:
12664           abort ();
12665         }
12666     }
12667   else
12668     names = names_xmm;
12669   oappend (names[reg]);
12670 }
12671
12672 static void
12673 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
12674 {
12675   unsigned int reg = modrm.reg;
12676
12677   USED_REX (REX_R);
12678   if (rex & REX_R)
12679     reg += 8;
12680   if (vex.evex)
12681     {
12682       if (!vex.r)
12683         reg += 16;
12684     }
12685
12686   if (bytemode == tmm_mode)
12687     modrm.reg = reg;
12688
12689   print_vector_reg (reg, bytemode);
12690 }
12691
12692 static void
12693 OP_EM (int bytemode, int sizeflag)
12694 {
12695   int reg;
12696   const char **names;
12697
12698   if (modrm.mod != 3)
12699     {
12700       if (intel_syntax
12701           && (bytemode == v_mode || bytemode == v_swap_mode))
12702         {
12703           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
12704           used_prefixes |= (prefixes & PREFIX_DATA);
12705         }
12706       OP_E (bytemode, sizeflag);
12707       return;
12708     }
12709
12710   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
12711     swap_operand ();
12712
12713   /* Skip mod/rm byte.  */
12714   MODRM_CHECK;
12715   codep++;
12716   used_prefixes |= (prefixes & PREFIX_DATA);
12717   reg = modrm.rm;
12718   if (prefixes & PREFIX_DATA)
12719     {
12720       names = names_xmm;
12721       USED_REX (REX_B);
12722       if (rex & REX_B)
12723         reg += 8;
12724     }
12725   else
12726     names = names_mm;
12727   oappend (names[reg]);
12728 }
12729
12730 /* cvt* are the only instructions in sse2 which have
12731    both SSE and MMX operands and also have 0x66 prefix
12732    in their opcode. 0x66 was originally used to differentiate
12733    between SSE and MMX instruction(operands). So we have to handle the
12734    cvt* separately using OP_EMC and OP_MXC */
12735 static void
12736 OP_EMC (int bytemode, int sizeflag)
12737 {
12738   if (modrm.mod != 3)
12739     {
12740       if (intel_syntax && bytemode == v_mode)
12741         {
12742           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
12743           used_prefixes |= (prefixes & PREFIX_DATA);
12744         }
12745       OP_E (bytemode, sizeflag);
12746       return;
12747     }
12748
12749   /* Skip mod/rm byte.  */
12750   MODRM_CHECK;
12751   codep++;
12752   used_prefixes |= (prefixes & PREFIX_DATA);
12753   oappend (names_mm[modrm.rm]);
12754 }
12755
12756 static void
12757 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12758 {
12759   used_prefixes |= (prefixes & PREFIX_DATA);
12760   oappend (names_mm[modrm.reg]);
12761 }
12762
12763 static void
12764 OP_EX (int bytemode, int sizeflag)
12765 {
12766   int reg;
12767
12768   /* Skip mod/rm byte.  */
12769   MODRM_CHECK;
12770   codep++;
12771
12772   if (bytemode == dq_mode)
12773     bytemode = vex.w ? q_mode : d_mode;
12774
12775   if (modrm.mod != 3)
12776     {
12777       OP_E_memory (bytemode, sizeflag);
12778       return;
12779     }
12780
12781   reg = modrm.rm;
12782   USED_REX (REX_B);
12783   if (rex & REX_B)
12784     reg += 8;
12785   if (vex.evex)
12786     {
12787       USED_REX (REX_X);
12788       if ((rex & REX_X))
12789         reg += 16;
12790     }
12791
12792   if ((sizeflag & SUFFIX_ALWAYS)
12793       && (bytemode == x_swap_mode
12794           || bytemode == w_swap_mode
12795           || bytemode == d_swap_mode
12796           || bytemode == q_swap_mode))
12797     swap_operand ();
12798
12799   if (bytemode == tmm_mode)
12800     modrm.rm = reg;
12801
12802   print_vector_reg (reg, bytemode);
12803 }
12804
12805 static void
12806 OP_MS (int bytemode, int sizeflag)
12807 {
12808   if (modrm.mod == 3)
12809     OP_EM (bytemode, sizeflag);
12810   else
12811     BadOp ();
12812 }
12813
12814 static void
12815 OP_XS (int bytemode, int sizeflag)
12816 {
12817   if (modrm.mod == 3)
12818     OP_EX (bytemode, sizeflag);
12819   else
12820     BadOp ();
12821 }
12822
12823 static void
12824 OP_M (int bytemode, int sizeflag)
12825 {
12826   if (modrm.mod == 3)
12827     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
12828     BadOp ();
12829   else
12830     OP_E (bytemode, sizeflag);
12831 }
12832
12833 static void
12834 OP_0f07 (int bytemode, int sizeflag)
12835 {
12836   if (modrm.mod != 3 || modrm.rm != 0)
12837     BadOp ();
12838   else
12839     OP_E (bytemode, sizeflag);
12840 }
12841
12842 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
12843    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
12844
12845 static void
12846 NOP_Fixup1 (int bytemode, int sizeflag)
12847 {
12848   if ((prefixes & PREFIX_DATA) != 0
12849       || (rex != 0
12850           && rex != 0x48
12851           && address_mode == mode_64bit))
12852     OP_REG (bytemode, sizeflag);
12853   else
12854     strcpy (obuf, "nop");
12855 }
12856
12857 static void
12858 NOP_Fixup2 (int bytemode, int sizeflag)
12859 {
12860   if ((prefixes & PREFIX_DATA) != 0
12861       || (rex != 0
12862           && rex != 0x48
12863           && address_mode == mode_64bit))
12864     OP_IMREG (bytemode, sizeflag);
12865 }
12866
12867 static const char *const Suffix3DNow[] = {
12868 /* 00 */        NULL,           NULL,           NULL,           NULL,
12869 /* 04 */        NULL,           NULL,           NULL,           NULL,
12870 /* 08 */        NULL,           NULL,           NULL,           NULL,
12871 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
12872 /* 10 */        NULL,           NULL,           NULL,           NULL,
12873 /* 14 */        NULL,           NULL,           NULL,           NULL,
12874 /* 18 */        NULL,           NULL,           NULL,           NULL,
12875 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
12876 /* 20 */        NULL,           NULL,           NULL,           NULL,
12877 /* 24 */        NULL,           NULL,           NULL,           NULL,
12878 /* 28 */        NULL,           NULL,           NULL,           NULL,
12879 /* 2C */        NULL,           NULL,           NULL,           NULL,
12880 /* 30 */        NULL,           NULL,           NULL,           NULL,
12881 /* 34 */        NULL,           NULL,           NULL,           NULL,
12882 /* 38 */        NULL,           NULL,           NULL,           NULL,
12883 /* 3C */        NULL,           NULL,           NULL,           NULL,
12884 /* 40 */        NULL,           NULL,           NULL,           NULL,
12885 /* 44 */        NULL,           NULL,           NULL,           NULL,
12886 /* 48 */        NULL,           NULL,           NULL,           NULL,
12887 /* 4C */        NULL,           NULL,           NULL,           NULL,
12888 /* 50 */        NULL,           NULL,           NULL,           NULL,
12889 /* 54 */        NULL,           NULL,           NULL,           NULL,
12890 /* 58 */        NULL,           NULL,           NULL,           NULL,
12891 /* 5C */        NULL,           NULL,           NULL,           NULL,
12892 /* 60 */        NULL,           NULL,           NULL,           NULL,
12893 /* 64 */        NULL,           NULL,           NULL,           NULL,
12894 /* 68 */        NULL,           NULL,           NULL,           NULL,
12895 /* 6C */        NULL,           NULL,           NULL,           NULL,
12896 /* 70 */        NULL,           NULL,           NULL,           NULL,
12897 /* 74 */        NULL,           NULL,           NULL,           NULL,
12898 /* 78 */        NULL,           NULL,           NULL,           NULL,
12899 /* 7C */        NULL,           NULL,           NULL,           NULL,
12900 /* 80 */        NULL,           NULL,           NULL,           NULL,
12901 /* 84 */        NULL,           NULL,           NULL,           NULL,
12902 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
12903 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
12904 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
12905 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
12906 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
12907 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
12908 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
12909 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
12910 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
12911 /* AC */        NULL,           NULL,           "pfacc",        NULL,
12912 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
12913 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
12914 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
12915 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
12916 /* C0 */        NULL,           NULL,           NULL,           NULL,
12917 /* C4 */        NULL,           NULL,           NULL,           NULL,
12918 /* C8 */        NULL,           NULL,           NULL,           NULL,
12919 /* CC */        NULL,           NULL,           NULL,           NULL,
12920 /* D0 */        NULL,           NULL,           NULL,           NULL,
12921 /* D4 */        NULL,           NULL,           NULL,           NULL,
12922 /* D8 */        NULL,           NULL,           NULL,           NULL,
12923 /* DC */        NULL,           NULL,           NULL,           NULL,
12924 /* E0 */        NULL,           NULL,           NULL,           NULL,
12925 /* E4 */        NULL,           NULL,           NULL,           NULL,
12926 /* E8 */        NULL,           NULL,           NULL,           NULL,
12927 /* EC */        NULL,           NULL,           NULL,           NULL,
12928 /* F0 */        NULL,           NULL,           NULL,           NULL,
12929 /* F4 */        NULL,           NULL,           NULL,           NULL,
12930 /* F8 */        NULL,           NULL,           NULL,           NULL,
12931 /* FC */        NULL,           NULL,           NULL,           NULL,
12932 };
12933
12934 static void
12935 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12936 {
12937   const char *mnemonic;
12938
12939   FETCH_DATA (the_info, codep + 1);
12940   /* AMD 3DNow! instructions are specified by an opcode suffix in the
12941      place where an 8-bit immediate would normally go.  ie. the last
12942      byte of the instruction.  */
12943   obufp = mnemonicendp;
12944   mnemonic = Suffix3DNow[*codep++ & 0xff];
12945   if (mnemonic)
12946     oappend (mnemonic);
12947   else
12948     {
12949       /* Since a variable sized modrm/sib chunk is between the start
12950          of the opcode (0x0f0f) and the opcode suffix, we need to do
12951          all the modrm processing first, and don't know until now that
12952          we have a bad opcode.  This necessitates some cleaning up.  */
12953       op_out[0][0] = '\0';
12954       op_out[1][0] = '\0';
12955       BadOp ();
12956     }
12957   mnemonicendp = obufp;
12958 }
12959
12960 static const struct op simd_cmp_op[] =
12961 {
12962   { STRING_COMMA_LEN ("eq") },
12963   { STRING_COMMA_LEN ("lt") },
12964   { STRING_COMMA_LEN ("le") },
12965   { STRING_COMMA_LEN ("unord") },
12966   { STRING_COMMA_LEN ("neq") },
12967   { STRING_COMMA_LEN ("nlt") },
12968   { STRING_COMMA_LEN ("nle") },
12969   { STRING_COMMA_LEN ("ord") }
12970 };
12971
12972 static const struct op vex_cmp_op[] =
12973 {
12974   { STRING_COMMA_LEN ("eq_uq") },
12975   { STRING_COMMA_LEN ("nge") },
12976   { STRING_COMMA_LEN ("ngt") },
12977   { STRING_COMMA_LEN ("false") },
12978   { STRING_COMMA_LEN ("neq_oq") },
12979   { STRING_COMMA_LEN ("ge") },
12980   { STRING_COMMA_LEN ("gt") },
12981   { STRING_COMMA_LEN ("true") },
12982   { STRING_COMMA_LEN ("eq_os") },
12983   { STRING_COMMA_LEN ("lt_oq") },
12984   { STRING_COMMA_LEN ("le_oq") },
12985   { STRING_COMMA_LEN ("unord_s") },
12986   { STRING_COMMA_LEN ("neq_us") },
12987   { STRING_COMMA_LEN ("nlt_uq") },
12988   { STRING_COMMA_LEN ("nle_uq") },
12989   { STRING_COMMA_LEN ("ord_s") },
12990   { STRING_COMMA_LEN ("eq_us") },
12991   { STRING_COMMA_LEN ("nge_uq") },
12992   { STRING_COMMA_LEN ("ngt_uq") },
12993   { STRING_COMMA_LEN ("false_os") },
12994   { STRING_COMMA_LEN ("neq_os") },
12995   { STRING_COMMA_LEN ("ge_oq") },
12996   { STRING_COMMA_LEN ("gt_oq") },
12997   { STRING_COMMA_LEN ("true_us") },
12998 };
12999
13000 static void
13001 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13002 {
13003   unsigned int cmp_type;
13004
13005   FETCH_DATA (the_info, codep + 1);
13006   cmp_type = *codep++ & 0xff;
13007   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
13008     {
13009       char suffix [3];
13010       char *p = mnemonicendp - 2;
13011       suffix[0] = p[0];
13012       suffix[1] = p[1];
13013       suffix[2] = '\0';
13014       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13015       mnemonicendp += simd_cmp_op[cmp_type].len;
13016     }
13017   else if (need_vex
13018            && cmp_type < ARRAY_SIZE (simd_cmp_op) + ARRAY_SIZE (vex_cmp_op))
13019     {
13020       char suffix [3];
13021       char *p = mnemonicendp - 2;
13022       suffix[0] = p[0];
13023       suffix[1] = p[1];
13024       suffix[2] = '\0';
13025       cmp_type -= ARRAY_SIZE (simd_cmp_op);
13026       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
13027       mnemonicendp += vex_cmp_op[cmp_type].len;
13028     }
13029   else
13030     {
13031       /* We have a reserved extension byte.  Output it directly.  */
13032       scratchbuf[0] = '$';
13033       print_operand_value (scratchbuf + 1, 1, cmp_type);
13034       oappend_maybe_intel (scratchbuf);
13035       scratchbuf[0] = '\0';
13036     }
13037 }
13038
13039 static void
13040 OP_Mwait (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13041 {
13042   /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx  */
13043   if (!intel_syntax)
13044     {
13045       strcpy (op_out[0], names32[0]);
13046       strcpy (op_out[1], names32[1]);
13047       if (bytemode == eBX_reg)
13048         strcpy (op_out[2], names32[3]);
13049       two_source_ops = 1;
13050     }
13051   /* Skip mod/rm byte.  */
13052   MODRM_CHECK;
13053   codep++;
13054 }
13055
13056 static void
13057 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
13058             int sizeflag ATTRIBUTE_UNUSED)
13059 {
13060   /* monitor %{e,r,}ax,%ecx,%edx"  */
13061   if (!intel_syntax)
13062     {
13063       const char **names = (address_mode == mode_64bit
13064                             ? names64 : names32);
13065
13066       if (prefixes & PREFIX_ADDR)
13067         {
13068           /* Remove "addr16/addr32".  */
13069           all_prefixes[last_addr_prefix] = 0;
13070           names = (address_mode != mode_32bit
13071                    ? names32 : names16);
13072           used_prefixes |= PREFIX_ADDR;
13073         }
13074       else if (address_mode == mode_16bit)
13075         names = names16;
13076       strcpy (op_out[0], names[0]);
13077       strcpy (op_out[1], names32[1]);
13078       strcpy (op_out[2], names32[2]);
13079       two_source_ops = 1;
13080     }
13081   /* Skip mod/rm byte.  */
13082   MODRM_CHECK;
13083   codep++;
13084 }
13085
13086 static void
13087 BadOp (void)
13088 {
13089   /* Throw away prefixes and 1st. opcode byte.  */
13090   codep = insn_codep + 1;
13091   oappend ("(bad)");
13092 }
13093
13094 static void
13095 REP_Fixup (int bytemode, int sizeflag)
13096 {
13097   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
13098      lods and stos.  */
13099   if (prefixes & PREFIX_REPZ)
13100     all_prefixes[last_repz_prefix] = REP_PREFIX;
13101
13102   switch (bytemode)
13103     {
13104     case al_reg:
13105     case eAX_reg:
13106     case indir_dx_reg:
13107       OP_IMREG (bytemode, sizeflag);
13108       break;
13109     case eDI_reg:
13110       OP_ESreg (bytemode, sizeflag);
13111       break;
13112     case eSI_reg:
13113       OP_DSreg (bytemode, sizeflag);
13114       break;
13115     default:
13116       abort ();
13117       break;
13118     }
13119 }
13120
13121 static void
13122 SEP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13123 {
13124   if ( isa64 != amd64 )
13125     return;
13126
13127   obufp = obuf;
13128   BadOp ();
13129   mnemonicendp = obufp;
13130   ++codep;
13131 }
13132
13133 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
13134    "bnd".  */
13135
13136 static void
13137 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13138 {
13139   if (prefixes & PREFIX_REPNZ)
13140     all_prefixes[last_repnz_prefix] = BND_PREFIX;
13141 }
13142
13143 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
13144    "notrack".  */
13145
13146 static void
13147 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
13148                int sizeflag ATTRIBUTE_UNUSED)
13149 {
13150
13151   /* Since active_seg_prefix is not set in 64-bit mode, check whether
13152      we've seen a PREFIX_DS.  */
13153   if ((prefixes & PREFIX_DS) != 0
13154       && (address_mode != mode_64bit || last_data_prefix < 0))
13155     {
13156       /* NOTRACK prefix is only valid on indirect branch instructions.
13157          NB: DATA prefix is unsupported for Intel64.  */
13158       active_seg_prefix = 0;
13159       all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
13160     }
13161 }
13162
13163 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
13164    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
13165  */
13166
13167 static void
13168 HLE_Fixup1 (int bytemode, int sizeflag)
13169 {
13170   if (modrm.mod != 3
13171       && (prefixes & PREFIX_LOCK) != 0)
13172     {
13173       if (prefixes & PREFIX_REPZ)
13174         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
13175       if (prefixes & PREFIX_REPNZ)
13176         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
13177     }
13178
13179   OP_E (bytemode, sizeflag);
13180 }
13181
13182 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
13183    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
13184  */
13185
13186 static void
13187 HLE_Fixup2 (int bytemode, int sizeflag)
13188 {
13189   if (modrm.mod != 3)
13190     {
13191       if (prefixes & PREFIX_REPZ)
13192         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
13193       if (prefixes & PREFIX_REPNZ)
13194         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
13195     }
13196
13197   OP_E (bytemode, sizeflag);
13198 }
13199
13200 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
13201    "xrelease" for memory operand.  No check for LOCK prefix.   */
13202
13203 static void
13204 HLE_Fixup3 (int bytemode, int sizeflag)
13205 {
13206   if (modrm.mod != 3
13207       && last_repz_prefix > last_repnz_prefix
13208       && (prefixes & PREFIX_REPZ) != 0)
13209     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
13210
13211   OP_E (bytemode, sizeflag);
13212 }
13213
13214 static void
13215 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
13216 {
13217   USED_REX (REX_W);
13218   if (rex & REX_W)
13219     {
13220       /* Change cmpxchg8b to cmpxchg16b.  */
13221       char *p = mnemonicendp - 2;
13222       mnemonicendp = stpcpy (p, "16b");
13223       bytemode = o_mode;
13224     }
13225   else if ((prefixes & PREFIX_LOCK) != 0)
13226     {
13227       if (prefixes & PREFIX_REPZ)
13228         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
13229       if (prefixes & PREFIX_REPNZ)
13230         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
13231     }
13232
13233   OP_M (bytemode, sizeflag);
13234 }
13235
13236 static void
13237 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
13238 {
13239   const char **names;
13240
13241   if (need_vex)
13242     {
13243       switch (vex.length)
13244         {
13245         case 128:
13246           names = names_xmm;
13247           break;
13248         case 256:
13249           names = names_ymm;
13250           break;
13251         default:
13252           abort ();
13253         }
13254     }
13255   else
13256     names = names_xmm;
13257   oappend (names[reg]);
13258 }
13259
13260 static void
13261 FXSAVE_Fixup (int bytemode, int sizeflag)
13262 {
13263   /* Add proper suffix to "fxsave" and "fxrstor".  */
13264   USED_REX (REX_W);
13265   if (rex & REX_W)
13266     {
13267       char *p = mnemonicendp;
13268       *p++ = '6';
13269       *p++ = '4';
13270       *p = '\0';
13271       mnemonicendp = p;
13272     }
13273   OP_M (bytemode, sizeflag);
13274 }
13275
13276 /* Display the destination register operand for instructions with
13277    VEX. */
13278
13279 static void
13280 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13281 {
13282   int reg, modrm_reg, sib_index = -1;
13283   const char **names;
13284
13285   if (!need_vex)
13286     abort ();
13287
13288   reg = vex.register_specifier;
13289   vex.register_specifier = 0;
13290   if (address_mode != mode_64bit)
13291     {
13292       if (vex.evex && !vex.v)
13293         {
13294           oappend ("(bad)");
13295           return;
13296         }
13297
13298       reg &= 7;
13299     }
13300   else if (vex.evex && !vex.v)
13301     reg += 16;
13302
13303   switch (bytemode)
13304     {
13305     case scalar_mode:
13306       oappend (names_xmm[reg]);
13307       return;
13308
13309     case vex_vsib_d_w_dq_mode:
13310     case vex_vsib_q_w_dq_mode:
13311       /* This must be the 3rd operand.  */
13312       if (obufp != op_out[2])
13313         abort ();
13314       if (vex.length == 128
13315           || (bytemode != vex_vsib_d_w_dq_mode
13316               && !vex.w))
13317         oappend (names_xmm[reg]);
13318       else
13319         oappend (names_ymm[reg]);
13320
13321       /* All 3 XMM/YMM registers must be distinct.  */
13322       modrm_reg = modrm.reg;
13323       if (rex & REX_R)
13324         modrm_reg += 8;
13325
13326       if (modrm.rm == 4)
13327         {
13328           sib_index = sib.index;
13329           if (rex & REX_X)
13330             sib_index += 8;
13331         }
13332
13333       if (reg == modrm_reg || reg == sib_index)
13334         strcpy (obufp, "/(bad)");
13335       if (modrm_reg == sib_index || modrm_reg == reg)
13336         strcat (op_out[0], "/(bad)");
13337       if (sib_index == modrm_reg || sib_index == reg)
13338         strcat (op_out[1], "/(bad)");
13339
13340       return;
13341
13342     case tmm_mode:
13343       /* All 3 TMM registers must be distinct.  */
13344       if (reg >= 8)
13345         oappend ("(bad)");
13346       else
13347         {
13348           /* This must be the 3rd operand.  */
13349           if (obufp != op_out[2])
13350             abort ();
13351           oappend (names_tmm[reg]);
13352           if (reg == modrm.reg || reg == modrm.rm)
13353             strcpy (obufp, "/(bad)");
13354         }
13355
13356       if (modrm.reg == modrm.rm || modrm.reg == reg || modrm.rm == reg)
13357         {
13358           if (modrm.reg <= 8
13359               && (modrm.reg == modrm.rm || modrm.reg == reg))
13360             strcat (op_out[0], "/(bad)");
13361           if (modrm.rm <= 8
13362               && (modrm.rm == modrm.reg || modrm.rm == reg))
13363             strcat (op_out[1], "/(bad)");
13364         }
13365
13366       return;
13367     }
13368
13369   switch (vex.length)
13370     {
13371     case 128:
13372       switch (bytemode)
13373         {
13374         case x_mode:
13375           names = names_xmm;
13376           break;
13377         case dq_mode:
13378           if (rex & REX_W)
13379             names = names64;
13380           else
13381             names = names32;
13382           break;
13383         case mask_bd_mode:
13384         case mask_mode:
13385           if (reg > 0x7)
13386             {
13387               oappend ("(bad)");
13388               return;
13389             }
13390           names = names_mask;
13391           break;
13392         default:
13393           abort ();
13394           return;
13395         }
13396       break;
13397     case 256:
13398       switch (bytemode)
13399         {
13400         case x_mode:
13401           names = names_ymm;
13402           break;
13403         case mask_bd_mode:
13404         case mask_mode:
13405           if (reg > 0x7)
13406             {
13407               oappend ("(bad)");
13408               return;
13409             }
13410           names = names_mask;
13411           break;
13412         default:
13413           /* See PR binutils/20893 for a reproducer.  */
13414           oappend ("(bad)");
13415           return;
13416         }
13417       break;
13418     case 512:
13419       names = names_zmm;
13420       break;
13421     default:
13422       abort ();
13423       break;
13424     }
13425   oappend (names[reg]);
13426 }
13427
13428 static void
13429 OP_VexR (int bytemode, int sizeflag)
13430 {
13431   if (modrm.mod == 3)
13432     OP_VEX (bytemode, sizeflag);
13433 }
13434
13435 static void
13436 OP_VexW (int bytemode, int sizeflag)
13437 {
13438   OP_VEX (bytemode, sizeflag);
13439
13440   if (vex.w)
13441     {
13442       /* Swap 2nd and 3rd operands.  */
13443       strcpy (scratchbuf, op_out[2]);
13444       strcpy (op_out[2], op_out[1]);
13445       strcpy (op_out[1], scratchbuf);
13446     }
13447 }
13448
13449 static void
13450 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13451 {
13452   int reg;
13453   const char **names = names_xmm;
13454
13455   FETCH_DATA (the_info, codep + 1);
13456   reg = *codep++;
13457
13458   if (bytemode != x_mode && bytemode != scalar_mode)
13459     abort ();
13460
13461   reg >>= 4;
13462   if (address_mode != mode_64bit)
13463     reg &= 7;
13464
13465   if (bytemode == x_mode && vex.length == 256)
13466     names = names_ymm;
13467
13468   oappend (names[reg]);
13469
13470   if (vex.w)
13471     {
13472       /* Swap 3rd and 4th operands.  */
13473       strcpy (scratchbuf, op_out[3]);
13474       strcpy (op_out[3], op_out[2]);
13475       strcpy (op_out[2], scratchbuf);
13476     }
13477 }
13478
13479 static void
13480 OP_VexI4 (int bytemode ATTRIBUTE_UNUSED,
13481           int sizeflag ATTRIBUTE_UNUSED)
13482 {
13483   scratchbuf[0] = '$';
13484   print_operand_value (scratchbuf + 1, 1, codep[-1] & 0xf);
13485   oappend_maybe_intel (scratchbuf);
13486 }
13487
13488 static void
13489 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
13490              int sizeflag ATTRIBUTE_UNUSED)
13491 {
13492   unsigned int cmp_type;
13493
13494   if (!vex.evex)
13495     abort ();
13496
13497   FETCH_DATA (the_info, codep + 1);
13498   cmp_type = *codep++ & 0xff;
13499   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
13500      If it's the case, print suffix, otherwise - print the immediate.  */
13501   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
13502       && cmp_type != 3
13503       && cmp_type != 7)
13504     {
13505       char suffix [3];
13506       char *p = mnemonicendp - 2;
13507
13508       /* vpcmp* can have both one- and two-lettered suffix.  */
13509       if (p[0] == 'p')
13510         {
13511           p++;
13512           suffix[0] = p[0];
13513           suffix[1] = '\0';
13514         }
13515       else
13516         {
13517           suffix[0] = p[0];
13518           suffix[1] = p[1];
13519           suffix[2] = '\0';
13520         }
13521
13522       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13523       mnemonicendp += simd_cmp_op[cmp_type].len;
13524     }
13525   else
13526     {
13527       /* We have a reserved extension byte.  Output it directly.  */
13528       scratchbuf[0] = '$';
13529       print_operand_value (scratchbuf + 1, 1, cmp_type);
13530       oappend_maybe_intel (scratchbuf);
13531       scratchbuf[0] = '\0';
13532     }
13533 }
13534
13535 static const struct op xop_cmp_op[] =
13536 {
13537   { STRING_COMMA_LEN ("lt") },
13538   { STRING_COMMA_LEN ("le") },
13539   { STRING_COMMA_LEN ("gt") },
13540   { STRING_COMMA_LEN ("ge") },
13541   { STRING_COMMA_LEN ("eq") },
13542   { STRING_COMMA_LEN ("neq") },
13543   { STRING_COMMA_LEN ("false") },
13544   { STRING_COMMA_LEN ("true") }
13545 };
13546
13547 static void
13548 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
13549              int sizeflag ATTRIBUTE_UNUSED)
13550 {
13551   unsigned int cmp_type;
13552
13553   FETCH_DATA (the_info, codep + 1);
13554   cmp_type = *codep++ & 0xff;
13555   if (cmp_type < ARRAY_SIZE (xop_cmp_op))
13556     {
13557       char suffix[3];
13558       char *p = mnemonicendp - 2;
13559
13560       /* vpcom* can have both one- and two-lettered suffix.  */
13561       if (p[0] == 'm')
13562         {
13563           p++;
13564           suffix[0] = p[0];
13565           suffix[1] = '\0';
13566         }
13567       else
13568         {
13569           suffix[0] = p[0];
13570           suffix[1] = p[1];
13571           suffix[2] = '\0';
13572         }
13573
13574       sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
13575       mnemonicendp += xop_cmp_op[cmp_type].len;
13576     }
13577   else
13578     {
13579       /* We have a reserved extension byte.  Output it directly.  */
13580       scratchbuf[0] = '$';
13581       print_operand_value (scratchbuf + 1, 1, cmp_type);
13582       oappend_maybe_intel (scratchbuf);
13583       scratchbuf[0] = '\0';
13584     }
13585 }
13586
13587 static const struct op pclmul_op[] =
13588 {
13589   { STRING_COMMA_LEN ("lql") },
13590   { STRING_COMMA_LEN ("hql") },
13591   { STRING_COMMA_LEN ("lqh") },
13592   { STRING_COMMA_LEN ("hqh") }
13593 };
13594
13595 static void
13596 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
13597               int sizeflag ATTRIBUTE_UNUSED)
13598 {
13599   unsigned int pclmul_type;
13600
13601   FETCH_DATA (the_info, codep + 1);
13602   pclmul_type = *codep++ & 0xff;
13603   switch (pclmul_type)
13604     {
13605     case 0x10:
13606       pclmul_type = 2;
13607       break;
13608     case 0x11:
13609       pclmul_type = 3;
13610       break;
13611     default:
13612       break;
13613     }
13614   if (pclmul_type < ARRAY_SIZE (pclmul_op))
13615     {
13616       char suffix [4];
13617       char *p = mnemonicendp - 3;
13618       suffix[0] = p[0];
13619       suffix[1] = p[1];
13620       suffix[2] = p[2];
13621       suffix[3] = '\0';
13622       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
13623       mnemonicendp += pclmul_op[pclmul_type].len;
13624     }
13625   else
13626     {
13627       /* We have a reserved extension byte.  Output it directly.  */
13628       scratchbuf[0] = '$';
13629       print_operand_value (scratchbuf + 1, 1, pclmul_type);
13630       oappend_maybe_intel (scratchbuf);
13631       scratchbuf[0] = '\0';
13632     }
13633 }
13634
13635 static void
13636 MOVSXD_Fixup (int bytemode, int sizeflag)
13637 {
13638   /* Add proper suffix to "movsxd".  */
13639   char *p = mnemonicendp;
13640
13641   switch (bytemode)
13642     {
13643     case movsxd_mode:
13644       if (!intel_syntax)
13645         {
13646           USED_REX (REX_W);
13647           if (rex & REX_W)
13648             {
13649               *p++ = 'l';
13650               *p++ = 'q';
13651               break;
13652             }
13653         }
13654
13655       *p++ = 'x';
13656       *p++ = 'd';
13657       break;
13658     default:
13659       oappend (INTERNAL_DISASSEMBLER_ERROR);
13660       break;
13661     }
13662
13663   mnemonicendp = p;
13664   *p = '\0';
13665   OP_E (bytemode, sizeflag);
13666 }
13667
13668 static void
13669 DistinctDest_Fixup (int bytemode, int sizeflag)
13670 {
13671   unsigned int reg = vex.register_specifier;
13672   unsigned int modrm_reg = modrm.reg;
13673   unsigned int modrm_rm = modrm.rm;
13674
13675   /* Calc destination register number.  */
13676   if (rex & REX_R)
13677     modrm_reg += 8;
13678   if (!vex.r)
13679     modrm_reg += 16;
13680
13681   /* Calc src1 register number.  */
13682   if (address_mode != mode_64bit)
13683     reg &= 7;
13684   else if (vex.evex && !vex.v)
13685     reg += 16;
13686
13687   /* Calc src2 register number.  */
13688   if (modrm.mod == 3)
13689     {
13690       if (rex & REX_B)
13691         modrm_rm += 8;
13692       if (rex & REX_X)
13693         modrm_rm += 16;
13694     }
13695
13696   /* Destination and source registers must be distinct, output bad if
13697      dest == src1 or dest == src2.  */
13698   if (modrm_reg == reg
13699       || (modrm.mod == 3
13700           && modrm_reg == modrm_rm))
13701     {
13702       oappend ("(bad)");
13703     }
13704   else
13705     OP_XMM (bytemode, sizeflag);
13706 }
13707
13708 static void
13709 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13710 {
13711   if (modrm.mod != 3 || !vex.b)
13712     return;
13713
13714   switch (bytemode)
13715     {
13716     case evex_rounding_64_mode:
13717       if (address_mode != mode_64bit || !vex.w)
13718         return;
13719       /* Fall through.  */
13720     case evex_rounding_mode:
13721       evex_used |= EVEX_b_used;
13722       oappend (names_rounding[vex.ll]);
13723       break;
13724     case evex_sae_mode:
13725       evex_used |= EVEX_b_used;
13726       oappend ("{");
13727       break;
13728     default:
13729       abort ();
13730     }
13731   oappend ("sae}");
13732 }