opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2022 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "disassemble.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40 #include "safe-ctype.h"
  41
  42 #include <setjmp.h>
  43 typedef struct instr_info instr_info;
  44
  45 static void dofloat (instr_info *, int);
  46 static void OP_ST (instr_info *, int, int);
  47 static void OP_STi (instr_info *, int, int);
  48 static int putop (instr_info *, const char *, int);
  49 static void oappend_with_style (instr_info *, const char *,
  50                                 enum disassembler_style);
  51 static void oappend (instr_info *, const char *);
  52 static void append_seg (instr_info *);
  53 static void OP_indirE (instr_info *, int, int);
  54 static void print_operand_value (instr_info *, char *, int, bfd_vma);
  55 static void OP_E_memory (instr_info *, int, int);
  56 static void print_displacement (instr_info *, char *, bfd_vma);
  57 static void OP_E (instr_info *, int, int);
  58 static void OP_G (instr_info *, int, int);
  59 static bfd_vma get64 (instr_info *);
  60 static bfd_signed_vma get32 (instr_info *);
  61 static bfd_signed_vma get32s (instr_info *);
  62 static int get16 (instr_info *);
  63 static void set_op (instr_info *, bfd_vma, bool);
  64 static void OP_Skip_MODRM (instr_info *, int, int);
  65 static void OP_REG (instr_info *, int, int);
  66 static void OP_IMREG (instr_info *, int, int);
  67 static void OP_I (instr_info *, int, int);
  68 static void OP_I64 (instr_info *, int, int);
  69 static void OP_sI (instr_info *, int, int);
  70 static void OP_J (instr_info *, int, int);
  71 static void OP_SEG (instr_info *, int, int);
  72 static void OP_DIR (instr_info *, int, int);
  73 static void OP_OFF (instr_info *, int, int);
  74 static void OP_OFF64 (instr_info *, int, int);
  75 static void ptr_reg (instr_info *, int, int);
  76 static void OP_ESreg (instr_info *, int, int);
  77 static void OP_DSreg (instr_info *, int, int);
  78 static void OP_C (instr_info *, int, int);
  79 static void OP_D (instr_info *, int, int);
  80 static void OP_T (instr_info *, int, int);
  81 static void OP_MMX (instr_info *, int, int);
  82 static void OP_XMM (instr_info *, int, int);
  83 static void OP_EM (instr_info *, int, int);
  84 static void OP_EX (instr_info *, int, int);
  85 static void OP_EMC (instr_info *, int,int);
  86 static void OP_MXC (instr_info *, int,int);
  87 static void OP_MS (instr_info *, int, int);
  88 static void OP_XS (instr_info *, int, int);
  89 static void OP_M (instr_info *, int, int);
  90 static void OP_VEX (instr_info *, int, int);
  91 static void OP_VexR (instr_info *, int, int);
  92 static void OP_VexW (instr_info *, int, int);
  93 static void OP_Rounding (instr_info *, int, int);
  94 static void OP_REG_VexI4 (instr_info *, int, int);
  95 static void OP_VexI4 (instr_info *, int, int);
  96 static void PCLMUL_Fixup (instr_info *, int, int);
  97 static void VPCMP_Fixup (instr_info *, int, int);
  98 static void VPCOM_Fixup (instr_info *, int, int);
  99 static void OP_0f07 (instr_info *, int, int);
 100 static void OP_Monitor (instr_info *, int, int);
 101 static void OP_Mwait (instr_info *, int, int);
 102 static void NOP_Fixup (instr_info *, int, int);
 103 static void OP_3DNowSuffix (instr_info *, int, int);
 104 static void CMP_Fixup (instr_info *, int, int);
 105 static void BadOp (instr_info *);
 106 static void REP_Fixup (instr_info *, int, int);
 107 static void SEP_Fixup (instr_info *, int, int);
 108 static void BND_Fixup (instr_info *, int, int);
 109 static void NOTRACK_Fixup (instr_info *, int, int);
 110 static void HLE_Fixup1 (instr_info *, int, int);
 111 static void HLE_Fixup2 (instr_info *, int, int);
 112 static void HLE_Fixup3 (instr_info *, int, int);
 113 static void CMPXCHG8B_Fixup (instr_info *, int, int);
 114 static void XMM_Fixup (instr_info *, int, int);
 115 static void FXSAVE_Fixup (instr_info *, int, int);
 116
 117 static void MOVSXD_Fixup (instr_info *, int, int);
 118 static void DistinctDest_Fixup (instr_info *, int, int);
 119
 120 /* This character is used to encode style information within the output
 121    buffers.  See oappend_insert_style for more details.  */
 122 #define STYLE_MARKER_CHAR '\002'
 123
 124 struct dis_private {
 125   /* Points to first byte not fetched.  */
 126   bfd_byte *max_fetched;
 127   bfd_byte the_buffer[MAX_MNEM_SIZE];
 128   bfd_vma insn_start;
 129   int orig_sizeflag;
 130   OPCODES_SIGJMP_BUF bailout;
 131 };
 132
 133 enum address_mode
 134 {
 135   mode_16bit,
 136   mode_32bit,
 137   mode_64bit
 138 };
 139
 140 enum x86_64_isa
 141 {
 142   amd64 = 1,
 143   intel64
 144 };
 145
 146 struct instr_info
 147 {
 148   enum address_mode address_mode;
 149
 150   /* Flags for the prefixes for the current instruction.  See below.  */
 151   int prefixes;
 152
 153   /* REX prefix the current instruction.  See below.  */
 154   unsigned char rex;
 155   /* Bits of REX we've already used.  */
 156   unsigned char rex_used;
 157
 158   bool need_modrm;
 159   bool need_vex;
 160   bool has_sib;
 161
 162   /* Flags for ins->prefixes which we somehow handled when printing the
 163      current instruction.  */
 164   int used_prefixes;
 165
 166   /* Flags for EVEX bits which we somehow handled when printing the
 167      current instruction.  */
 168   int evex_used;
 169
 170   char obuf[100];
 171   char *obufp;
 172   char *mnemonicendp;
 173   char scratchbuf[100];
 174   unsigned char *start_codep;
 175   unsigned char *insn_codep;
 176   unsigned char *codep;
 177   unsigned char *end_codep;
 178   int last_lock_prefix;
 179   int last_repz_prefix;
 180   int last_repnz_prefix;
 181   int last_data_prefix;
 182   int last_addr_prefix;
 183   int last_rex_prefix;
 184   int last_seg_prefix;
 185   int fwait_prefix;
 186   /* The active segment register prefix.  */
 187   int active_seg_prefix;
 188
 189 #define MAX_CODE_LENGTH 15
 190   /* We can up to 14 ins->prefixes since the maximum instruction length is
 191      15bytes.  */
 192   int all_prefixes[MAX_CODE_LENGTH - 1];
 193   disassemble_info *info;
 194
 195   struct
 196   {
 197     int mod;
 198     int reg;
 199     int rm;
 200   }
 201   modrm;
 202
 203   struct
 204   {
 205     int scale;
 206     int index;
 207     int base;
 208   }
 209   sib;
 210
 211   struct
 212   {
 213     int register_specifier;
 214     int length;
 215     int prefix;
 216     int mask_register_specifier;
 217     int ll;
 218     bool w;
 219     bool evex;
 220     bool r;
 221     bool v;
 222     bool zeroing;
 223     bool b;
 224     bool no_broadcast;
 225   }
 226   vex;
 227
 228   /* Remember if the current op is a jump instruction.  */
 229   bool op_is_jump;
 230
 231   bool two_source_ops;
 232
 233   unsigned char op_ad;
 234   signed char op_index[MAX_OPERANDS];
 235   bool op_riprel[MAX_OPERANDS];
 236   char *op_out[MAX_OPERANDS];
 237   bfd_vma op_address[MAX_OPERANDS];
 238   bfd_vma start_pc;
 239
 240   /* On the 386's of 1988, the maximum length of an instruction is 15 bytes.
 241    *   (see topic "Redundant ins->prefixes" in the "Differences from 8086"
 242    *   section of the "Virtual 8086 Mode" chapter.)
 243    * 'pc' should be the address of this instruction, it will
 244    *   be used to print the target address if this is a relative jump or call
 245    * The function returns the length of this instruction in bytes.
 246    */
 247   char intel_syntax;
 248   bool intel_mnemonic;
 249   char open_char;
 250   char close_char;
 251   char separator_char;
 252   char scale_char;
 253
 254   enum x86_64_isa isa64;
 255 };
 256
 257 /* Mark parts used in the REX prefix.  When we are testing for
 258    empty prefix (for 8bit register REX extension), just mask it
 259    out.  Otherwise test for REX bit is excuse for existence of REX
 260    only in case value is nonzero.  */
 261 #define USED_REX(value)                                 \
 262   {                                                     \
 263     if (value)                                          \
 264       {                                                 \
 265         if ((ins->rex & value))                         \
 266           ins->rex_used |= (value) | REX_OPCODE;        \
 267       }                                                 \
 268     else                                                \
 269       ins->rex_used |= REX_OPCODE;                      \
 270   }
 271
 272
 273 #define EVEX_b_used 1
 274 #define EVEX_len_used 2
 275
 276 /* Flags stored in PREFIXES.  */
 277 #define PREFIX_REPZ 1
 278 #define PREFIX_REPNZ 2
 279 #define PREFIX_LOCK 4
 280 #define PREFIX_CS 8
 281 #define PREFIX_SS 0x10
 282 #define PREFIX_DS 0x20
 283 #define PREFIX_ES 0x40
 284 #define PREFIX_FS 0x80
 285 #define PREFIX_GS 0x100
 286 #define PREFIX_DATA 0x200
 287 #define PREFIX_ADDR 0x400
 288 #define PREFIX_FWAIT 0x800
 289
 290 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 291    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 292    on error.  */
 293 #define FETCH_DATA(info, addr) \
 294   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 295    ? 1 : fetch_data ((info), (addr)))
 296
 297 static int
 298 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 299 {
 300   int status;
 301   struct dis_private *priv = (struct dis_private *) info->private_data;
 302   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 303
 304   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 305     status = (*info->read_memory_func) (start,
 306                                         priv->max_fetched,
 307                                         addr - priv->max_fetched,
 308                                         info);
 309   else
 310     status = -1;
 311   if (status != 0)
 312     {
 313       /* If we did manage to read at least one byte, then
 314          print_insn_i386 will do something sensible.  Otherwise, print
 315          an error.  We do that here because this is where we know
 316          STATUS.  */
 317       if (priv->max_fetched == priv->the_buffer)
 318         (*info->memory_error_func) (status, start, info);
 319       OPCODES_SIGLONGJMP (priv->bailout, 1);
 320     }
 321   else
 322     priv->max_fetched = addr;
 323   return 1;
 324 }
 325
 326 /* Possible values for prefix requirement.  */
 327 #define PREFIX_IGNORED_SHIFT    16
 328 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 329 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 330 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 331 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 332 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 333
 334 /* Opcode prefixes.  */
 335 #define PREFIX_OPCODE           (PREFIX_REPZ \
 336                                  | PREFIX_REPNZ \
 337                                  | PREFIX_DATA)
 338
 339 /* Prefixes ignored.  */
 340 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 341                                  | PREFIX_IGNORED_REPNZ \
 342                                  | PREFIX_IGNORED_DATA)
 343
 344 #define XX { NULL, 0 }
 345 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 346
 347 #define Eb { OP_E, b_mode }
 348 #define Ebnd { OP_E, bnd_mode }
 349 #define EbS { OP_E, b_swap_mode }
 350 #define EbndS { OP_E, bnd_swap_mode }
 351 #define Ev { OP_E, v_mode }
 352 #define Eva { OP_E, va_mode }
 353 #define Ev_bnd { OP_E, v_bnd_mode }
 354 #define EvS { OP_E, v_swap_mode }
 355 #define Ed { OP_E, d_mode }
 356 #define Edq { OP_E, dq_mode }
 357 #define Edb { OP_E, db_mode }
 358 #define Edw { OP_E, dw_mode }
 359 #define Eq { OP_E, q_mode }
 360 #define indirEv { OP_indirE, indir_v_mode }
 361 #define indirEp { OP_indirE, f_mode }
 362 #define stackEv { OP_E, stack_v_mode }
 363 #define Em { OP_E, m_mode }
 364 #define Ew { OP_E, w_mode }
 365 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 366 #define Ma { OP_M, a_mode }
 367 #define Mb { OP_M, b_mode }
 368 #define Md { OP_M, d_mode }
 369 #define Mo { OP_M, o_mode }
 370 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 371 #define Mq { OP_M, q_mode }
 372 #define Mv { OP_M, v_mode }
 373 #define Mv_bnd { OP_M, v_bndmk_mode }
 374 #define Mx { OP_M, x_mode }
 375 #define Mxmm { OP_M, xmm_mode }
 376 #define Gb { OP_G, b_mode }
 377 #define Gbnd { OP_G, bnd_mode }
 378 #define Gv { OP_G, v_mode }
 379 #define Gd { OP_G, d_mode }
 380 #define Gdq { OP_G, dq_mode }
 381 #define Gm { OP_G, m_mode }
 382 #define Gva { OP_G, va_mode }
 383 #define Gw { OP_G, w_mode }
 384 #define Ib { OP_I, b_mode }
 385 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 386 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 387 #define Iv { OP_I, v_mode }
 388 #define sIv { OP_sI, v_mode }
 389 #define Iv64 { OP_I64, v_mode }
 390 #define Id { OP_I, d_mode }
 391 #define Iw { OP_I, w_mode }
 392 #define I1 { OP_I, const_1_mode }
 393 #define Jb { OP_J, b_mode }
 394 #define Jv { OP_J, v_mode }
 395 #define Jdqw { OP_J, dqw_mode }
 396 #define Cm { OP_C, m_mode }
 397 #define Dm { OP_D, m_mode }
 398 #define Td { OP_T, d_mode }
 399 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 400
 401 #define RMeAX { OP_REG, eAX_reg }
 402 #define RMeBX { OP_REG, eBX_reg }
 403 #define RMeCX { OP_REG, eCX_reg }
 404 #define RMeDX { OP_REG, eDX_reg }
 405 #define RMeSP { OP_REG, eSP_reg }
 406 #define RMeBP { OP_REG, eBP_reg }
 407 #define RMeSI { OP_REG, eSI_reg }
 408 #define RMeDI { OP_REG, eDI_reg }
 409 #define RMrAX { OP_REG, rAX_reg }
 410 #define RMrBX { OP_REG, rBX_reg }
 411 #define RMrCX { OP_REG, rCX_reg }
 412 #define RMrDX { OP_REG, rDX_reg }
 413 #define RMrSP { OP_REG, rSP_reg }
 414 #define RMrBP { OP_REG, rBP_reg }
 415 #define RMrSI { OP_REG, rSI_reg }
 416 #define RMrDI { OP_REG, rDI_reg }
 417 #define RMAL { OP_REG, al_reg }
 418 #define RMCL { OP_REG, cl_reg }
 419 #define RMDL { OP_REG, dl_reg }
 420 #define RMBL { OP_REG, bl_reg }
 421 #define RMAH { OP_REG, ah_reg }
 422 #define RMCH { OP_REG, ch_reg }
 423 #define RMDH { OP_REG, dh_reg }
 424 #define RMBH { OP_REG, bh_reg }
 425 #define RMAX { OP_REG, ax_reg }
 426 #define RMDX { OP_REG, dx_reg }
 427
 428 #define eAX { OP_IMREG, eAX_reg }
 429 #define AL { OP_IMREG, al_reg }
 430 #define CL { OP_IMREG, cl_reg }
 431 #define zAX { OP_IMREG, z_mode_ax_reg }
 432 #define indirDX { OP_IMREG, indir_dx_reg }
 433
 434 #define Sw { OP_SEG, w_mode }
 435 #define Sv { OP_SEG, v_mode }
 436 #define Ap { OP_DIR, 0 }
 437 #define Ob { OP_OFF64, b_mode }
 438 #define Ov { OP_OFF64, v_mode }
 439 #define Xb { OP_DSreg, eSI_reg }
 440 #define Xv { OP_DSreg, eSI_reg }
 441 #define Xz { OP_DSreg, eSI_reg }
 442 #define Yb { OP_ESreg, eDI_reg }
 443 #define Yv { OP_ESreg, eDI_reg }
 444 #define DSBX { OP_DSreg, eBX_reg }
 445
 446 #define es { OP_REG, es_reg }
 447 #define ss { OP_REG, ss_reg }
 448 #define cs { OP_REG, cs_reg }
 449 #define ds { OP_REG, ds_reg }
 450 #define fs { OP_REG, fs_reg }
 451 #define gs { OP_REG, gs_reg }
 452
 453 #define MX { OP_MMX, 0 }
 454 #define XM { OP_XMM, 0 }
 455 #define XMScalar { OP_XMM, scalar_mode }
 456 #define XMGatherD { OP_XMM, vex_vsib_d_w_dq_mode }
 457 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 458 #define XMM { OP_XMM, xmm_mode }
 459 #define TMM { OP_XMM, tmm_mode }
 460 #define XMxmmq { OP_XMM, xmmq_mode }
 461 #define EM { OP_EM, v_mode }
 462 #define EMS { OP_EM, v_swap_mode }
 463 #define EMd { OP_EM, d_mode }
 464 #define EMx { OP_EM, x_mode }
 465 #define EXbwUnit { OP_EX, bw_unit_mode }
 466 #define EXb { OP_EX, b_mode }
 467 #define EXw { OP_EX, w_mode }
 468 #define EXd { OP_EX, d_mode }
 469 #define EXdS { OP_EX, d_swap_mode }
 470 #define EXwS { OP_EX, w_swap_mode }
 471 #define EXq { OP_EX, q_mode }
 472 #define EXqS { OP_EX, q_swap_mode }
 473 #define EXdq { OP_EX, dq_mode }
 474 #define EXx { OP_EX, x_mode }
 475 #define EXxh { OP_EX, xh_mode }
 476 #define EXxS { OP_EX, x_swap_mode }
 477 #define EXxmm { OP_EX, xmm_mode }
 478 #define EXymm { OP_EX, ymm_mode }
 479 #define EXtmm { OP_EX, tmm_mode }
 480 #define EXxmmq { OP_EX, xmmq_mode }
 481 #define EXxmmqh { OP_EX, evex_half_bcst_xmmqh_mode }
 482 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 483 #define EXxmmdw { OP_EX, xmmdw_mode }
 484 #define EXxmmqd { OP_EX, xmmqd_mode }
 485 #define EXxmmqdh { OP_EX, evex_half_bcst_xmmqdh_mode }
 486 #define EXymmq { OP_EX, ymmq_mode }
 487 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 488 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 489 #define MS { OP_MS, v_mode }
 490 #define XS { OP_XS, v_mode }
 491 #define EMCq { OP_EMC, q_mode }
 492 #define MXC { OP_MXC, 0 }
 493 #define OPSUF { OP_3DNowSuffix, 0 }
 494 #define SEP { SEP_Fixup, 0 }
 495 #define CMP { CMP_Fixup, 0 }
 496 #define XMM0 { XMM_Fixup, 0 }
 497 #define FXSAVE { FXSAVE_Fixup, 0 }
 498
 499 #define Vex { OP_VEX, x_mode }
 500 #define VexW { OP_VexW, x_mode }
 501 #define VexScalar { OP_VEX, scalar_mode }
 502 #define VexScalarR { OP_VexR, scalar_mode }
 503 #define VexGatherD { OP_VEX, vex_vsib_d_w_dq_mode }
 504 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 505 #define VexGdq { OP_VEX, dq_mode }
 506 #define VexTmm { OP_VEX, tmm_mode }
 507 #define XMVexI4 { OP_REG_VexI4, x_mode }
 508 #define XMVexScalarI4 { OP_REG_VexI4, scalar_mode }
 509 #define VexI4 { OP_VexI4, 0 }
 510 #define PCLMUL { PCLMUL_Fixup, 0 }
 511 #define VPCMP { VPCMP_Fixup, 0 }
 512 #define VPCOM { VPCOM_Fixup, 0 }
 513
 514 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 515 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
 516 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 517
 518 #define MaskG { OP_G, mask_mode }
 519 #define MaskE { OP_E, mask_mode }
 520 #define MaskBDE { OP_E, mask_bd_mode }
 521 #define MaskVex { OP_VEX, mask_mode }
 522
 523 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 524 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 525
 526 #define MVexSIBMEM { OP_M, vex_sibmem_mode }
 527
 528 /* Used handle "rep" prefix for string instructions.  */
 529 #define Xbr { REP_Fixup, eSI_reg }
 530 #define Xvr { REP_Fixup, eSI_reg }
 531 #define Ybr { REP_Fixup, eDI_reg }
 532 #define Yvr { REP_Fixup, eDI_reg }
 533 #define Yzr { REP_Fixup, eDI_reg }
 534 #define indirDXr { REP_Fixup, indir_dx_reg }
 535 #define ALr { REP_Fixup, al_reg }
 536 #define eAXr { REP_Fixup, eAX_reg }
 537
 538 /* Used handle HLE prefix for lockable instructions.  */
 539 #define Ebh1 { HLE_Fixup1, b_mode }
 540 #define Evh1 { HLE_Fixup1, v_mode }
 541 #define Ebh2 { HLE_Fixup2, b_mode }
 542 #define Evh2 { HLE_Fixup2, v_mode }
 543 #define Ebh3 { HLE_Fixup3, b_mode }
 544 #define Evh3 { HLE_Fixup3, v_mode }
 545
 546 #define BND { BND_Fixup, 0 }
 547 #define NOTRACK { NOTRACK_Fixup, 0 }
 548
 549 #define cond_jump_flag { NULL, cond_jump_mode }
 550 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 551
 552 /* bits in sizeflag */
 553 #define SUFFIX_ALWAYS 4
 554 #define AFLAG 2
 555 #define DFLAG 1
 556
 557 enum
 558 {
 559   /* byte operand */
 560   b_mode = 1,
 561   /* byte operand with operand swapped */
 562   b_swap_mode,
 563   /* byte operand, sign extend like 'T' suffix */
 564   b_T_mode,
 565   /* operand size depends on prefixes */
 566   v_mode,
 567   /* operand size depends on prefixes with operand swapped */
 568   v_swap_mode,
 569   /* operand size depends on address prefix */
 570   va_mode,
 571   /* word operand */
 572   w_mode,
 573   /* double word operand  */
 574   d_mode,
 575   /* word operand with operand swapped  */
 576   w_swap_mode,
 577   /* double word operand with operand swapped */
 578   d_swap_mode,
 579   /* quad word operand */
 580   q_mode,
 581   /* quad word operand with operand swapped */
 582   q_swap_mode,
 583   /* ten-byte operand */
 584   t_mode,
 585   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 586      broadcast enabled.  */
 587   x_mode,
 588   /* Similar to x_mode, but with different EVEX mem shifts.  */
 589   evex_x_gscat_mode,
 590   /* Similar to x_mode, but with yet different EVEX mem shifts.  */
 591   bw_unit_mode,
 592   /* Similar to x_mode, but with disabled broadcast.  */
 593   evex_x_nobcst_mode,
 594   /* Similar to x_mode, but with operands swapped and disabled broadcast
 595      in EVEX.  */
 596   x_swap_mode,
 597   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 598      broadcast of 16bit enabled.  */
 599   xh_mode,
 600   /* 16-byte XMM operand */
 601   xmm_mode,
 602   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 603      memory operand (depending on vector length).  Broadcast isn't
 604      allowed.  */
 605   xmmq_mode,
 606   /* Same as xmmq_mode, but broadcast is allowed.  */
 607   evex_half_bcst_xmmq_mode,
 608   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 609      memory operand (depending on vector length).  16bit broadcast.  */
 610   evex_half_bcst_xmmqh_mode,
 611   /* 16-byte XMM, word, double word or quad word operand.  */
 612   xmmdw_mode,
 613   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 614   xmmqd_mode,
 615   /* 16-byte XMM, double word, quad word operand or xmm word operand.
 616      16bit broadcast.  */
 617   evex_half_bcst_xmmqdh_mode,
 618   /* 32-byte YMM operand */
 619   ymm_mode,
 620   /* quad word, ymmword or zmmword memory operand.  */
 621   ymmq_mode,
 622   /* TMM operand */
 623   tmm_mode,
 624   /* d_mode in 32bit, q_mode in 64bit mode.  */
 625   m_mode,
 626   /* pair of v_mode operands */
 627   a_mode,
 628   cond_jump_mode,
 629   loop_jcxz_mode,
 630   movsxd_mode,
 631   v_bnd_mode,
 632   /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode.  */
 633   v_bndmk_mode,
 634   /* operand size depends on REX.W / VEX.W.  */
 635   dq_mode,
 636   /* Displacements like v_mode without considering Intel64 ISA.  */
 637   dqw_mode,
 638   /* bounds operand */
 639   bnd_mode,
 640   /* bounds operand with operand swapped */
 641   bnd_swap_mode,
 642   /* 4- or 6-byte pointer operand */
 643   f_mode,
 644   const_1_mode,
 645   /* v_mode for indirect branch opcodes.  */
 646   indir_v_mode,
 647   /* v_mode for stack-related opcodes.  */
 648   stack_v_mode,
 649   /* non-quad operand size depends on prefixes */
 650   z_mode,
 651   /* 16-byte operand */
 652   o_mode,
 653   /* registers like d_mode, memory like b_mode.  */
 654   db_mode,
 655   /* registers like d_mode, memory like w_mode.  */
 656   dw_mode,
 657
 658   /* Operand size depends on the VEX.W bit, with VSIB dword indices.  */
 659   vex_vsib_d_w_dq_mode,
 660   /* Operand size depends on the VEX.W bit, with VSIB qword indices.  */
 661   vex_vsib_q_w_dq_mode,
 662   /* mandatory non-vector SIB.  */
 663   vex_sibmem_mode,
 664
 665   /* scalar, ignore vector length.  */
 666   scalar_mode,
 667
 668   /* Static rounding.  */
 669   evex_rounding_mode,
 670   /* Static rounding, 64-bit mode only.  */
 671   evex_rounding_64_mode,
 672   /* Supress all exceptions.  */
 673   evex_sae_mode,
 674
 675   /* Mask register operand.  */
 676   mask_mode,
 677   /* Mask register operand.  */
 678   mask_bd_mode,
 679
 680   es_reg,
 681   cs_reg,
 682   ss_reg,
 683   ds_reg,
 684   fs_reg,
 685   gs_reg,
 686
 687   eAX_reg,
 688   eCX_reg,
 689   eDX_reg,
 690   eBX_reg,
 691   eSP_reg,
 692   eBP_reg,
 693   eSI_reg,
 694   eDI_reg,
 695
 696   al_reg,
 697   cl_reg,
 698   dl_reg,
 699   bl_reg,
 700   ah_reg,
 701   ch_reg,
 702   dh_reg,
 703   bh_reg,
 704
 705   ax_reg,
 706   cx_reg,
 707   dx_reg,
 708   bx_reg,
 709   sp_reg,
 710   bp_reg,
 711   si_reg,
 712   di_reg,
 713
 714   rAX_reg,
 715   rCX_reg,
 716   rDX_reg,
 717   rBX_reg,
 718   rSP_reg,
 719   rBP_reg,
 720   rSI_reg,
 721   rDI_reg,
 722
 723   z_mode_ax_reg,
 724   indir_dx_reg
 725 };
 726
 727 enum
 728 {
 729   FLOATCODE = 1,
 730   USE_REG_TABLE,
 731   USE_MOD_TABLE,
 732   USE_RM_TABLE,
 733   USE_PREFIX_TABLE,
 734   USE_X86_64_TABLE,
 735   USE_3BYTE_TABLE,
 736   USE_XOP_8F_TABLE,
 737   USE_VEX_C4_TABLE,
 738   USE_VEX_C5_TABLE,
 739   USE_VEX_LEN_TABLE,
 740   USE_VEX_W_TABLE,
 741   USE_EVEX_TABLE,
 742   USE_EVEX_LEN_TABLE
 743 };
 744
 745 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 746
 747 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 748 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 749 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 750 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 751 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 752 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 753 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 754 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 755 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 756 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 757 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 758 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 759 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 760 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 761 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 762 #define EVEX_LEN_TABLE(I)       DIS386 (USE_EVEX_LEN_TABLE, (I))
 763
 764 enum
 765 {
 766   REG_80 = 0,
 767   REG_81,
 768   REG_83,
 769   REG_8F,
 770   REG_C0,
 771   REG_C1,
 772   REG_C6,
 773   REG_C7,
 774   REG_D0,
 775   REG_D1,
 776   REG_D2,
 777   REG_D3,
 778   REG_F6,
 779   REG_F7,
 780   REG_FE,
 781   REG_FF,
 782   REG_0F00,
 783   REG_0F01,
 784   REG_0F0D,
 785   REG_0F18,
 786   REG_0F1C_P_0_MOD_0,
 787   REG_0F1E_P_1_MOD_3,
 788   REG_0F38D8_PREFIX_1,
 789   REG_0F3A0F_PREFIX_1_MOD_3,
 790   REG_0F71_MOD_0,
 791   REG_0F72_MOD_0,
 792   REG_0F73_MOD_0,
 793   REG_0FA6,
 794   REG_0FA7,
 795   REG_0FAE,
 796   REG_0FBA,
 797   REG_0FC7,
 798   REG_VEX_0F71_M_0,
 799   REG_VEX_0F72_M_0,
 800   REG_VEX_0F73_M_0,
 801   REG_VEX_0FAE,
 802   REG_VEX_0F3849_X86_64_P_0_W_0_M_1,
 803   REG_VEX_0F38F3_L_0,
 804
 805   REG_XOP_09_01_L_0,
 806   REG_XOP_09_02_L_0,
 807   REG_XOP_09_12_M_1_L_0,
 808   REG_XOP_0A_12_L_0,
 809
 810   REG_EVEX_0F71,
 811   REG_EVEX_0F72,
 812   REG_EVEX_0F73,
 813   REG_EVEX_0F38C6_M_0_L_2,
 814   REG_EVEX_0F38C7_M_0_L_2
 815 };
 816
 817 enum
 818 {
 819   MOD_62_32BIT = 0,
 820   MOD_8D,
 821   MOD_C4_32BIT,
 822   MOD_C5_32BIT,
 823   MOD_C6_REG_7,
 824   MOD_C7_REG_7,
 825   MOD_FF_REG_3,
 826   MOD_FF_REG_5,
 827   MOD_0F01_REG_0,
 828   MOD_0F01_REG_1,
 829   MOD_0F01_REG_2,
 830   MOD_0F01_REG_3,
 831   MOD_0F01_REG_5,
 832   MOD_0F01_REG_7,
 833   MOD_0F12_PREFIX_0,
 834   MOD_0F12_PREFIX_2,
 835   MOD_0F13,
 836   MOD_0F16_PREFIX_0,
 837   MOD_0F16_PREFIX_2,
 838   MOD_0F17,
 839   MOD_0F18_REG_0,
 840   MOD_0F18_REG_1,
 841   MOD_0F18_REG_2,
 842   MOD_0F18_REG_3,
 843   MOD_0F1A_PREFIX_0,
 844   MOD_0F1B_PREFIX_0,
 845   MOD_0F1B_PREFIX_1,
 846   MOD_0F1C_PREFIX_0,
 847   MOD_0F1E_PREFIX_1,
 848   MOD_0F2B_PREFIX_0,
 849   MOD_0F2B_PREFIX_1,
 850   MOD_0F2B_PREFIX_2,
 851   MOD_0F2B_PREFIX_3,
 852   MOD_0F50,
 853   MOD_0F71,
 854   MOD_0F72,
 855   MOD_0F73,
 856   MOD_0FAE_REG_0,
 857   MOD_0FAE_REG_1,
 858   MOD_0FAE_REG_2,
 859   MOD_0FAE_REG_3,
 860   MOD_0FAE_REG_4,
 861   MOD_0FAE_REG_5,
 862   MOD_0FAE_REG_6,
 863   MOD_0FAE_REG_7,
 864   MOD_0FB2,
 865   MOD_0FB4,
 866   MOD_0FB5,
 867   MOD_0FC3,
 868   MOD_0FC7_REG_3,
 869   MOD_0FC7_REG_4,
 870   MOD_0FC7_REG_5,
 871   MOD_0FC7_REG_6,
 872   MOD_0FC7_REG_7,
 873   MOD_0FD7,
 874   MOD_0FE7_PREFIX_2,
 875   MOD_0FF0_PREFIX_3,
 876   MOD_0F382A,
 877   MOD_0F38DC_PREFIX_1,
 878   MOD_0F38DD_PREFIX_1,
 879   MOD_0F38DE_PREFIX_1,
 880   MOD_0F38DF_PREFIX_1,
 881   MOD_0F38F5,
 882   MOD_0F38F6_PREFIX_0,
 883   MOD_0F38F8_PREFIX_1,
 884   MOD_0F38F8_PREFIX_2,
 885   MOD_0F38F8_PREFIX_3,
 886   MOD_0F38F9,
 887   MOD_0F38FA_PREFIX_1,
 888   MOD_0F38FB_PREFIX_1,
 889   MOD_0F3A0F_PREFIX_1,
 890
 891   MOD_VEX_0F12_PREFIX_0,
 892   MOD_VEX_0F12_PREFIX_2,
 893   MOD_VEX_0F13,
 894   MOD_VEX_0F16_PREFIX_0,
 895   MOD_VEX_0F16_PREFIX_2,
 896   MOD_VEX_0F17,
 897   MOD_VEX_0F2B,
 898   MOD_VEX_0F41_L_1,
 899   MOD_VEX_0F42_L_1,
 900   MOD_VEX_0F44_L_0,
 901   MOD_VEX_0F45_L_1,
 902   MOD_VEX_0F46_L_1,
 903   MOD_VEX_0F47_L_1,
 904   MOD_VEX_0F4A_L_1,
 905   MOD_VEX_0F4B_L_1,
 906   MOD_VEX_0F50,
 907   MOD_VEX_0F71,
 908   MOD_VEX_0F72,
 909   MOD_VEX_0F73,
 910   MOD_VEX_0F91_L_0,
 911   MOD_VEX_0F92_L_0,
 912   MOD_VEX_0F93_L_0,
 913   MOD_VEX_0F98_L_0,
 914   MOD_VEX_0F99_L_0,
 915   MOD_VEX_0FAE_REG_2,
 916   MOD_VEX_0FAE_REG_3,
 917   MOD_VEX_0FD7,
 918   MOD_VEX_0FE7,
 919   MOD_VEX_0FF0_PREFIX_3,
 920   MOD_VEX_0F381A,
 921   MOD_VEX_0F382A,
 922   MOD_VEX_0F382C,
 923   MOD_VEX_0F382D,
 924   MOD_VEX_0F382E,
 925   MOD_VEX_0F382F,
 926   MOD_VEX_0F3849_X86_64_P_0_W_0,
 927   MOD_VEX_0F3849_X86_64_P_2_W_0,
 928   MOD_VEX_0F3849_X86_64_P_3_W_0,
 929   MOD_VEX_0F384B_X86_64_P_1_W_0,
 930   MOD_VEX_0F384B_X86_64_P_2_W_0,
 931   MOD_VEX_0F384B_X86_64_P_3_W_0,
 932   MOD_VEX_0F385A,
 933   MOD_VEX_0F385C_X86_64_P_1_W_0,
 934   MOD_VEX_0F385E_X86_64_P_0_W_0,
 935   MOD_VEX_0F385E_X86_64_P_1_W_0,
 936   MOD_VEX_0F385E_X86_64_P_2_W_0,
 937   MOD_VEX_0F385E_X86_64_P_3_W_0,
 938   MOD_VEX_0F388C,
 939   MOD_VEX_0F388E,
 940   MOD_VEX_0F3A30_L_0,
 941   MOD_VEX_0F3A31_L_0,
 942   MOD_VEX_0F3A32_L_0,
 943   MOD_VEX_0F3A33_L_0,
 944
 945   MOD_XOP_09_12,
 946
 947   MOD_EVEX_0F381A,
 948   MOD_EVEX_0F381B,
 949   MOD_EVEX_0F3828_P_1,
 950   MOD_EVEX_0F382A_P_1_W_1,
 951   MOD_EVEX_0F3838_P_1,
 952   MOD_EVEX_0F383A_P_1_W_0,
 953   MOD_EVEX_0F385A,
 954   MOD_EVEX_0F385B,
 955   MOD_EVEX_0F387A_W_0,
 956   MOD_EVEX_0F387B_W_0,
 957   MOD_EVEX_0F387C,
 958   MOD_EVEX_0F38C6,
 959   MOD_EVEX_0F38C7,
 960 };
 961
 962 enum
 963 {
 964   RM_C6_REG_7 = 0,
 965   RM_C7_REG_7,
 966   RM_0F01_REG_0,
 967   RM_0F01_REG_1,
 968   RM_0F01_REG_2,
 969   RM_0F01_REG_3,
 970   RM_0F01_REG_5_MOD_3,
 971   RM_0F01_REG_7_MOD_3,
 972   RM_0F1E_P_1_MOD_3_REG_7,
 973   RM_0FAE_REG_6_MOD_3_P_0,
 974   RM_0FAE_REG_7_MOD_3,
 975   RM_0F3A0F_P_1_MOD_3_REG_0,
 976
 977   RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0
 978 };
 979
 980 enum
 981 {
 982   PREFIX_90 = 0,
 983   PREFIX_0F01_REG_1_RM_4,
 984   PREFIX_0F01_REG_1_RM_5,
 985   PREFIX_0F01_REG_1_RM_6,
 986   PREFIX_0F01_REG_1_RM_7,
 987   PREFIX_0F01_REG_3_RM_1,
 988   PREFIX_0F01_REG_5_MOD_0,
 989   PREFIX_0F01_REG_5_MOD_3_RM_0,
 990   PREFIX_0F01_REG_5_MOD_3_RM_1,
 991   PREFIX_0F01_REG_5_MOD_3_RM_2,
 992   PREFIX_0F01_REG_5_MOD_3_RM_4,
 993   PREFIX_0F01_REG_5_MOD_3_RM_5,
 994   PREFIX_0F01_REG_5_MOD_3_RM_6,
 995   PREFIX_0F01_REG_5_MOD_3_RM_7,
 996   PREFIX_0F01_REG_7_MOD_3_RM_2,
 997   PREFIX_0F01_REG_7_MOD_3_RM_6,
 998   PREFIX_0F01_REG_7_MOD_3_RM_7,
 999   PREFIX_0F09,
1000   PREFIX_0F10,
1001   PREFIX_0F11,
1002   PREFIX_0F12,
1003   PREFIX_0F16,
1004   PREFIX_0F1A,
1005   PREFIX_0F1B,
1006   PREFIX_0F1C,
1007   PREFIX_0F1E,
1008   PREFIX_0F2A,
1009   PREFIX_0F2B,
1010   PREFIX_0F2C,
1011   PREFIX_0F2D,
1012   PREFIX_0F2E,
1013   PREFIX_0F2F,
1014   PREFIX_0F51,
1015   PREFIX_0F52,
1016   PREFIX_0F53,
1017   PREFIX_0F58,
1018   PREFIX_0F59,
1019   PREFIX_0F5A,
1020   PREFIX_0F5B,
1021   PREFIX_0F5C,
1022   PREFIX_0F5D,
1023   PREFIX_0F5E,
1024   PREFIX_0F5F,
1025   PREFIX_0F60,
1026   PREFIX_0F61,
1027   PREFIX_0F62,
1028   PREFIX_0F6F,
1029   PREFIX_0F70,
1030   PREFIX_0F78,
1031   PREFIX_0F79,
1032   PREFIX_0F7C,
1033   PREFIX_0F7D,
1034   PREFIX_0F7E,
1035   PREFIX_0F7F,
1036   PREFIX_0FAE_REG_0_MOD_3,
1037   PREFIX_0FAE_REG_1_MOD_3,
1038   PREFIX_0FAE_REG_2_MOD_3,
1039   PREFIX_0FAE_REG_3_MOD_3,
1040   PREFIX_0FAE_REG_4_MOD_0,
1041   PREFIX_0FAE_REG_4_MOD_3,
1042   PREFIX_0FAE_REG_5_MOD_3,
1043   PREFIX_0FAE_REG_6_MOD_0,
1044   PREFIX_0FAE_REG_6_MOD_3,
1045   PREFIX_0FAE_REG_7_MOD_0,
1046   PREFIX_0FB8,
1047   PREFIX_0FBC,
1048   PREFIX_0FBD,
1049   PREFIX_0FC2,
1050   PREFIX_0FC7_REG_6_MOD_0,
1051   PREFIX_0FC7_REG_6_MOD_3,
1052   PREFIX_0FC7_REG_7_MOD_3,
1053   PREFIX_0FD0,
1054   PREFIX_0FD6,
1055   PREFIX_0FE6,
1056   PREFIX_0FE7,
1057   PREFIX_0FF0,
1058   PREFIX_0FF7,
1059   PREFIX_0F38D8,
1060   PREFIX_0F38DC,
1061   PREFIX_0F38DD,
1062   PREFIX_0F38DE,
1063   PREFIX_0F38DF,
1064   PREFIX_0F38F0,
1065   PREFIX_0F38F1,
1066   PREFIX_0F38F6,
1067   PREFIX_0F38F8,
1068   PREFIX_0F38FA,
1069   PREFIX_0F38FB,
1070   PREFIX_0F3A0F,
1071   PREFIX_VEX_0F10,
1072   PREFIX_VEX_0F11,
1073   PREFIX_VEX_0F12,
1074   PREFIX_VEX_0F16,
1075   PREFIX_VEX_0F2A,
1076   PREFIX_VEX_0F2C,
1077   PREFIX_VEX_0F2D,
1078   PREFIX_VEX_0F2E,
1079   PREFIX_VEX_0F2F,
1080   PREFIX_VEX_0F41_L_1_M_1_W_0,
1081   PREFIX_VEX_0F41_L_1_M_1_W_1,
1082   PREFIX_VEX_0F42_L_1_M_1_W_0,
1083   PREFIX_VEX_0F42_L_1_M_1_W_1,
1084   PREFIX_VEX_0F44_L_0_M_1_W_0,
1085   PREFIX_VEX_0F44_L_0_M_1_W_1,
1086   PREFIX_VEX_0F45_L_1_M_1_W_0,
1087   PREFIX_VEX_0F45_L_1_M_1_W_1,
1088   PREFIX_VEX_0F46_L_1_M_1_W_0,
1089   PREFIX_VEX_0F46_L_1_M_1_W_1,
1090   PREFIX_VEX_0F47_L_1_M_1_W_0,
1091   PREFIX_VEX_0F47_L_1_M_1_W_1,
1092   PREFIX_VEX_0F4A_L_1_M_1_W_0,
1093   PREFIX_VEX_0F4A_L_1_M_1_W_1,
1094   PREFIX_VEX_0F4B_L_1_M_1_W_0,
1095   PREFIX_VEX_0F4B_L_1_M_1_W_1,
1096   PREFIX_VEX_0F51,
1097   PREFIX_VEX_0F52,
1098   PREFIX_VEX_0F53,
1099   PREFIX_VEX_0F58,
1100   PREFIX_VEX_0F59,
1101   PREFIX_VEX_0F5A,
1102   PREFIX_VEX_0F5B,
1103   PREFIX_VEX_0F5C,
1104   PREFIX_VEX_0F5D,
1105   PREFIX_VEX_0F5E,
1106   PREFIX_VEX_0F5F,
1107   PREFIX_VEX_0F6F,
1108   PREFIX_VEX_0F70,
1109   PREFIX_VEX_0F7C,
1110   PREFIX_VEX_0F7D,
1111   PREFIX_VEX_0F7E,
1112   PREFIX_VEX_0F7F,
1113   PREFIX_VEX_0F90_L_0_W_0,
1114   PREFIX_VEX_0F90_L_0_W_1,
1115   PREFIX_VEX_0F91_L_0_M_0_W_0,
1116   PREFIX_VEX_0F91_L_0_M_0_W_1,
1117   PREFIX_VEX_0F92_L_0_M_1_W_0,
1118   PREFIX_VEX_0F92_L_0_M_1_W_1,
1119   PREFIX_VEX_0F93_L_0_M_1_W_0,
1120   PREFIX_VEX_0F93_L_0_M_1_W_1,
1121   PREFIX_VEX_0F98_L_0_M_1_W_0,
1122   PREFIX_VEX_0F98_L_0_M_1_W_1,
1123   PREFIX_VEX_0F99_L_0_M_1_W_0,
1124   PREFIX_VEX_0F99_L_0_M_1_W_1,
1125   PREFIX_VEX_0FC2,
1126   PREFIX_VEX_0FD0,
1127   PREFIX_VEX_0FE6,
1128   PREFIX_VEX_0FF0,
1129   PREFIX_VEX_0F3849_X86_64,
1130   PREFIX_VEX_0F384B_X86_64,
1131   PREFIX_VEX_0F385C_X86_64,
1132   PREFIX_VEX_0F385E_X86_64,
1133   PREFIX_VEX_0F38F5_L_0,
1134   PREFIX_VEX_0F38F6_L_0,
1135   PREFIX_VEX_0F38F7_L_0,
1136   PREFIX_VEX_0F3AF0_L_0,
1137
1138   PREFIX_EVEX_0F5B,
1139   PREFIX_EVEX_0F6F,
1140   PREFIX_EVEX_0F70,
1141   PREFIX_EVEX_0F78,
1142   PREFIX_EVEX_0F79,
1143   PREFIX_EVEX_0F7A,
1144   PREFIX_EVEX_0F7B,
1145   PREFIX_EVEX_0F7E,
1146   PREFIX_EVEX_0F7F,
1147   PREFIX_EVEX_0FC2,
1148   PREFIX_EVEX_0FE6,
1149   PREFIX_EVEX_0F3810,
1150   PREFIX_EVEX_0F3811,
1151   PREFIX_EVEX_0F3812,
1152   PREFIX_EVEX_0F3813,
1153   PREFIX_EVEX_0F3814,
1154   PREFIX_EVEX_0F3815,
1155   PREFIX_EVEX_0F3820,
1156   PREFIX_EVEX_0F3821,
1157   PREFIX_EVEX_0F3822,
1158   PREFIX_EVEX_0F3823,
1159   PREFIX_EVEX_0F3824,
1160   PREFIX_EVEX_0F3825,
1161   PREFIX_EVEX_0F3826,
1162   PREFIX_EVEX_0F3827,
1163   PREFIX_EVEX_0F3828,
1164   PREFIX_EVEX_0F3829,
1165   PREFIX_EVEX_0F382A,
1166   PREFIX_EVEX_0F3830,
1167   PREFIX_EVEX_0F3831,
1168   PREFIX_EVEX_0F3832,
1169   PREFIX_EVEX_0F3833,
1170   PREFIX_EVEX_0F3834,
1171   PREFIX_EVEX_0F3835,
1172   PREFIX_EVEX_0F3838,
1173   PREFIX_EVEX_0F3839,
1174   PREFIX_EVEX_0F383A,
1175   PREFIX_EVEX_0F3852,
1176   PREFIX_EVEX_0F3853,
1177   PREFIX_EVEX_0F3868,
1178   PREFIX_EVEX_0F3872,
1179   PREFIX_EVEX_0F389A,
1180   PREFIX_EVEX_0F389B,
1181   PREFIX_EVEX_0F38AA,
1182   PREFIX_EVEX_0F38AB,
1183
1184   PREFIX_EVEX_0F3A08,
1185   PREFIX_EVEX_0F3A0A,
1186   PREFIX_EVEX_0F3A26,
1187   PREFIX_EVEX_0F3A27,
1188   PREFIX_EVEX_0F3A56,
1189   PREFIX_EVEX_0F3A57,
1190   PREFIX_EVEX_0F3A66,
1191   PREFIX_EVEX_0F3A67,
1192   PREFIX_EVEX_0F3AC2,
1193
1194   PREFIX_EVEX_MAP5_10,
1195   PREFIX_EVEX_MAP5_11,
1196   PREFIX_EVEX_MAP5_1D,
1197   PREFIX_EVEX_MAP5_2A,
1198   PREFIX_EVEX_MAP5_2C,
1199   PREFIX_EVEX_MAP5_2D,
1200   PREFIX_EVEX_MAP5_2E,
1201   PREFIX_EVEX_MAP5_2F,
1202   PREFIX_EVEX_MAP5_51,
1203   PREFIX_EVEX_MAP5_58,
1204   PREFIX_EVEX_MAP5_59,
1205   PREFIX_EVEX_MAP5_5A,
1206   PREFIX_EVEX_MAP5_5B,
1207   PREFIX_EVEX_MAP5_5C,
1208   PREFIX_EVEX_MAP5_5D,
1209   PREFIX_EVEX_MAP5_5E,
1210   PREFIX_EVEX_MAP5_5F,
1211   PREFIX_EVEX_MAP5_78,
1212   PREFIX_EVEX_MAP5_79,
1213   PREFIX_EVEX_MAP5_7A,
1214   PREFIX_EVEX_MAP5_7B,
1215   PREFIX_EVEX_MAP5_7C,
1216   PREFIX_EVEX_MAP5_7D,
1217
1218   PREFIX_EVEX_MAP6_13,
1219   PREFIX_EVEX_MAP6_56,
1220   PREFIX_EVEX_MAP6_57,
1221   PREFIX_EVEX_MAP6_D6,
1222   PREFIX_EVEX_MAP6_D7,
1223 };
1224
1225 enum
1226 {
1227   X86_64_06 = 0,
1228   X86_64_07,
1229   X86_64_0E,
1230   X86_64_16,
1231   X86_64_17,
1232   X86_64_1E,
1233   X86_64_1F,
1234   X86_64_27,
1235   X86_64_2F,
1236   X86_64_37,
1237   X86_64_3F,
1238   X86_64_60,
1239   X86_64_61,
1240   X86_64_62,
1241   X86_64_63,
1242   X86_64_6D,
1243   X86_64_6F,
1244   X86_64_82,
1245   X86_64_9A,
1246   X86_64_C2,
1247   X86_64_C3,
1248   X86_64_C4,
1249   X86_64_C5,
1250   X86_64_CE,
1251   X86_64_D4,
1252   X86_64_D5,
1253   X86_64_E8,
1254   X86_64_E9,
1255   X86_64_EA,
1256   X86_64_0F01_REG_0,
1257   X86_64_0F01_REG_1,
1258   X86_64_0F01_REG_1_RM_5_PREFIX_2,
1259   X86_64_0F01_REG_1_RM_6_PREFIX_2,
1260   X86_64_0F01_REG_1_RM_7_PREFIX_2,
1261   X86_64_0F01_REG_2,
1262   X86_64_0F01_REG_3,
1263   X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1,
1264   X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1,
1265   X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1,
1266   X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1,
1267   X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1,
1268   X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3,
1269   X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1,
1270   X86_64_0F24,
1271   X86_64_0F26,
1272   X86_64_0FC7_REG_6_MOD_3_PREFIX_1,
1273
1274   X86_64_VEX_0F3849,
1275   X86_64_VEX_0F384B,
1276   X86_64_VEX_0F385C,
1277   X86_64_VEX_0F385E
1278 };
1279
1280 enum
1281 {
1282   THREE_BYTE_0F38 = 0,
1283   THREE_BYTE_0F3A
1284 };
1285
1286 enum
1287 {
1288   XOP_08 = 0,
1289   XOP_09,
1290   XOP_0A
1291 };
1292
1293 enum
1294 {
1295   VEX_0F = 0,
1296   VEX_0F38,
1297   VEX_0F3A
1298 };
1299
1300 enum
1301 {
1302   EVEX_0F = 0,
1303   EVEX_0F38,
1304   EVEX_0F3A,
1305   EVEX_MAP5,
1306   EVEX_MAP6,
1307 };
1308
1309 enum
1310 {
1311   VEX_LEN_0F12_P_0_M_0 = 0,
1312   VEX_LEN_0F12_P_0_M_1,
1313 #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0
1314   VEX_LEN_0F13_M_0,
1315   VEX_LEN_0F16_P_0_M_0,
1316   VEX_LEN_0F16_P_0_M_1,
1317 #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0
1318   VEX_LEN_0F17_M_0,
1319   VEX_LEN_0F41,
1320   VEX_LEN_0F42,
1321   VEX_LEN_0F44,
1322   VEX_LEN_0F45,
1323   VEX_LEN_0F46,
1324   VEX_LEN_0F47,
1325   VEX_LEN_0F4A,
1326   VEX_LEN_0F4B,
1327   VEX_LEN_0F6E,
1328   VEX_LEN_0F77,
1329   VEX_LEN_0F7E_P_1,
1330   VEX_LEN_0F7E_P_2,
1331   VEX_LEN_0F90,
1332   VEX_LEN_0F91,
1333   VEX_LEN_0F92,
1334   VEX_LEN_0F93,
1335   VEX_LEN_0F98,
1336   VEX_LEN_0F99,
1337   VEX_LEN_0FAE_R_2_M_0,
1338   VEX_LEN_0FAE_R_3_M_0,
1339   VEX_LEN_0FC4,
1340   VEX_LEN_0FC5,
1341   VEX_LEN_0FD6,
1342   VEX_LEN_0FF7,
1343   VEX_LEN_0F3816,
1344   VEX_LEN_0F3819,
1345   VEX_LEN_0F381A_M_0,
1346   VEX_LEN_0F3836,
1347   VEX_LEN_0F3841,
1348   VEX_LEN_0F3849_X86_64_P_0_W_0_M_0,
1349   VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0,
1350   VEX_LEN_0F3849_X86_64_P_2_W_0_M_0,
1351   VEX_LEN_0F3849_X86_64_P_3_W_0_M_0,
1352   VEX_LEN_0F384B_X86_64_P_1_W_0_M_0,
1353   VEX_LEN_0F384B_X86_64_P_2_W_0_M_0,
1354   VEX_LEN_0F384B_X86_64_P_3_W_0_M_0,
1355   VEX_LEN_0F385A_M_0,
1356   VEX_LEN_0F385C_X86_64_P_1_W_0_M_0,
1357   VEX_LEN_0F385E_X86_64_P_0_W_0_M_0,
1358   VEX_LEN_0F385E_X86_64_P_1_W_0_M_0,
1359   VEX_LEN_0F385E_X86_64_P_2_W_0_M_0,
1360   VEX_LEN_0F385E_X86_64_P_3_W_0_M_0,
1361   VEX_LEN_0F38DB,
1362   VEX_LEN_0F38F2,
1363   VEX_LEN_0F38F3,
1364   VEX_LEN_0F38F5,
1365   VEX_LEN_0F38F6,
1366   VEX_LEN_0F38F7,
1367   VEX_LEN_0F3A00,
1368   VEX_LEN_0F3A01,
1369   VEX_LEN_0F3A06,
1370   VEX_LEN_0F3A14,
1371   VEX_LEN_0F3A15,
1372   VEX_LEN_0F3A16,
1373   VEX_LEN_0F3A17,
1374   VEX_LEN_0F3A18,
1375   VEX_LEN_0F3A19,
1376   VEX_LEN_0F3A20,
1377   VEX_LEN_0F3A21,
1378   VEX_LEN_0F3A22,
1379   VEX_LEN_0F3A30,
1380   VEX_LEN_0F3A31,
1381   VEX_LEN_0F3A32,
1382   VEX_LEN_0F3A33,
1383   VEX_LEN_0F3A38,
1384   VEX_LEN_0F3A39,
1385   VEX_LEN_0F3A41,
1386   VEX_LEN_0F3A46,
1387   VEX_LEN_0F3A60,
1388   VEX_LEN_0F3A61,
1389   VEX_LEN_0F3A62,
1390   VEX_LEN_0F3A63,
1391   VEX_LEN_0F3ADF,
1392   VEX_LEN_0F3AF0,
1393   VEX_LEN_0FXOP_08_85,
1394   VEX_LEN_0FXOP_08_86,
1395   VEX_LEN_0FXOP_08_87,
1396   VEX_LEN_0FXOP_08_8E,
1397   VEX_LEN_0FXOP_08_8F,
1398   VEX_LEN_0FXOP_08_95,
1399   VEX_LEN_0FXOP_08_96,
1400   VEX_LEN_0FXOP_08_97,
1401   VEX_LEN_0FXOP_08_9E,
1402   VEX_LEN_0FXOP_08_9F,
1403   VEX_LEN_0FXOP_08_A3,
1404   VEX_LEN_0FXOP_08_A6,
1405   VEX_LEN_0FXOP_08_B6,
1406   VEX_LEN_0FXOP_08_C0,
1407   VEX_LEN_0FXOP_08_C1,
1408   VEX_LEN_0FXOP_08_C2,
1409   VEX_LEN_0FXOP_08_C3,
1410   VEX_LEN_0FXOP_08_CC,
1411   VEX_LEN_0FXOP_08_CD,
1412   VEX_LEN_0FXOP_08_CE,
1413   VEX_LEN_0FXOP_08_CF,
1414   VEX_LEN_0FXOP_08_EC,
1415   VEX_LEN_0FXOP_08_ED,
1416   VEX_LEN_0FXOP_08_EE,
1417   VEX_LEN_0FXOP_08_EF,
1418   VEX_LEN_0FXOP_09_01,
1419   VEX_LEN_0FXOP_09_02,
1420   VEX_LEN_0FXOP_09_12_M_1,
1421   VEX_LEN_0FXOP_09_82_W_0,
1422   VEX_LEN_0FXOP_09_83_W_0,
1423   VEX_LEN_0FXOP_09_90,
1424   VEX_LEN_0FXOP_09_91,
1425   VEX_LEN_0FXOP_09_92,
1426   VEX_LEN_0FXOP_09_93,
1427   VEX_LEN_0FXOP_09_94,
1428   VEX_LEN_0FXOP_09_95,
1429   VEX_LEN_0FXOP_09_96,
1430   VEX_LEN_0FXOP_09_97,
1431   VEX_LEN_0FXOP_09_98,
1432   VEX_LEN_0FXOP_09_99,
1433   VEX_LEN_0FXOP_09_9A,
1434   VEX_LEN_0FXOP_09_9B,
1435   VEX_LEN_0FXOP_09_C1,
1436   VEX_LEN_0FXOP_09_C2,
1437   VEX_LEN_0FXOP_09_C3,
1438   VEX_LEN_0FXOP_09_C6,
1439   VEX_LEN_0FXOP_09_C7,
1440   VEX_LEN_0FXOP_09_CB,
1441   VEX_LEN_0FXOP_09_D1,
1442   VEX_LEN_0FXOP_09_D2,
1443   VEX_LEN_0FXOP_09_D3,
1444   VEX_LEN_0FXOP_09_D6,
1445   VEX_LEN_0FXOP_09_D7,
1446   VEX_LEN_0FXOP_09_DB,
1447   VEX_LEN_0FXOP_09_E1,
1448   VEX_LEN_0FXOP_09_E2,
1449   VEX_LEN_0FXOP_09_E3,
1450   VEX_LEN_0FXOP_0A_12,
1451 };
1452
1453 enum
1454 {
1455   EVEX_LEN_0F3816 = 0,
1456   EVEX_LEN_0F3819,
1457   EVEX_LEN_0F381A_M_0,
1458   EVEX_LEN_0F381B_M_0,
1459   EVEX_LEN_0F3836,
1460   EVEX_LEN_0F385A_M_0,
1461   EVEX_LEN_0F385B_M_0,
1462   EVEX_LEN_0F38C6_M_0,
1463   EVEX_LEN_0F38C7_M_0,
1464   EVEX_LEN_0F3A00,
1465   EVEX_LEN_0F3A01,
1466   EVEX_LEN_0F3A18,
1467   EVEX_LEN_0F3A19,
1468   EVEX_LEN_0F3A1A,
1469   EVEX_LEN_0F3A1B,
1470   EVEX_LEN_0F3A23,
1471   EVEX_LEN_0F3A38,
1472   EVEX_LEN_0F3A39,
1473   EVEX_LEN_0F3A3A,
1474   EVEX_LEN_0F3A3B,
1475   EVEX_LEN_0F3A43
1476 };
1477
1478 enum
1479 {
1480   VEX_W_0F41_L_1_M_1 = 0,
1481   VEX_W_0F42_L_1_M_1,
1482   VEX_W_0F44_L_0_M_1,
1483   VEX_W_0F45_L_1_M_1,
1484   VEX_W_0F46_L_1_M_1,
1485   VEX_W_0F47_L_1_M_1,
1486   VEX_W_0F4A_L_1_M_1,
1487   VEX_W_0F4B_L_1_M_1,
1488   VEX_W_0F90_L_0,
1489   VEX_W_0F91_L_0_M_0,
1490   VEX_W_0F92_L_0_M_1,
1491   VEX_W_0F93_L_0_M_1,
1492   VEX_W_0F98_L_0_M_1,
1493   VEX_W_0F99_L_0_M_1,
1494   VEX_W_0F380C,
1495   VEX_W_0F380D,
1496   VEX_W_0F380E,
1497   VEX_W_0F380F,
1498   VEX_W_0F3813,
1499   VEX_W_0F3816_L_1,
1500   VEX_W_0F3818,
1501   VEX_W_0F3819_L_1,
1502   VEX_W_0F381A_M_0_L_1,
1503   VEX_W_0F382C_M_0,
1504   VEX_W_0F382D_M_0,
1505   VEX_W_0F382E_M_0,
1506   VEX_W_0F382F_M_0,
1507   VEX_W_0F3836,
1508   VEX_W_0F3846,
1509   VEX_W_0F3849_X86_64_P_0,
1510   VEX_W_0F3849_X86_64_P_2,
1511   VEX_W_0F3849_X86_64_P_3,
1512   VEX_W_0F384B_X86_64_P_1,
1513   VEX_W_0F384B_X86_64_P_2,
1514   VEX_W_0F384B_X86_64_P_3,
1515   VEX_W_0F3850,
1516   VEX_W_0F3851,
1517   VEX_W_0F3852,
1518   VEX_W_0F3853,
1519   VEX_W_0F3858,
1520   VEX_W_0F3859,
1521   VEX_W_0F385A_M_0_L_0,
1522   VEX_W_0F385C_X86_64_P_1,
1523   VEX_W_0F385E_X86_64_P_0,
1524   VEX_W_0F385E_X86_64_P_1,
1525   VEX_W_0F385E_X86_64_P_2,
1526   VEX_W_0F385E_X86_64_P_3,
1527   VEX_W_0F3878,
1528   VEX_W_0F3879,
1529   VEX_W_0F38CF,
1530   VEX_W_0F3A00_L_1,
1531   VEX_W_0F3A01_L_1,
1532   VEX_W_0F3A02,
1533   VEX_W_0F3A04,
1534   VEX_W_0F3A05,
1535   VEX_W_0F3A06_L_1,
1536   VEX_W_0F3A18_L_1,
1537   VEX_W_0F3A19_L_1,
1538   VEX_W_0F3A1D,
1539   VEX_W_0F3A38_L_1,
1540   VEX_W_0F3A39_L_1,
1541   VEX_W_0F3A46_L_1,
1542   VEX_W_0F3A4A,
1543   VEX_W_0F3A4B,
1544   VEX_W_0F3A4C,
1545   VEX_W_0F3ACE,
1546   VEX_W_0F3ACF,
1547
1548   VEX_W_0FXOP_08_85_L_0,
1549   VEX_W_0FXOP_08_86_L_0,
1550   VEX_W_0FXOP_08_87_L_0,
1551   VEX_W_0FXOP_08_8E_L_0,
1552   VEX_W_0FXOP_08_8F_L_0,
1553   VEX_W_0FXOP_08_95_L_0,
1554   VEX_W_0FXOP_08_96_L_0,
1555   VEX_W_0FXOP_08_97_L_0,
1556   VEX_W_0FXOP_08_9E_L_0,
1557   VEX_W_0FXOP_08_9F_L_0,
1558   VEX_W_0FXOP_08_A6_L_0,
1559   VEX_W_0FXOP_08_B6_L_0,
1560   VEX_W_0FXOP_08_C0_L_0,
1561   VEX_W_0FXOP_08_C1_L_0,
1562   VEX_W_0FXOP_08_C2_L_0,
1563   VEX_W_0FXOP_08_C3_L_0,
1564   VEX_W_0FXOP_08_CC_L_0,
1565   VEX_W_0FXOP_08_CD_L_0,
1566   VEX_W_0FXOP_08_CE_L_0,
1567   VEX_W_0FXOP_08_CF_L_0,
1568   VEX_W_0FXOP_08_EC_L_0,
1569   VEX_W_0FXOP_08_ED_L_0,
1570   VEX_W_0FXOP_08_EE_L_0,
1571   VEX_W_0FXOP_08_EF_L_0,
1572
1573   VEX_W_0FXOP_09_80,
1574   VEX_W_0FXOP_09_81,
1575   VEX_W_0FXOP_09_82,
1576   VEX_W_0FXOP_09_83,
1577   VEX_W_0FXOP_09_C1_L_0,
1578   VEX_W_0FXOP_09_C2_L_0,
1579   VEX_W_0FXOP_09_C3_L_0,
1580   VEX_W_0FXOP_09_C6_L_0,
1581   VEX_W_0FXOP_09_C7_L_0,
1582   VEX_W_0FXOP_09_CB_L_0,
1583   VEX_W_0FXOP_09_D1_L_0,
1584   VEX_W_0FXOP_09_D2_L_0,
1585   VEX_W_0FXOP_09_D3_L_0,
1586   VEX_W_0FXOP_09_D6_L_0,
1587   VEX_W_0FXOP_09_D7_L_0,
1588   VEX_W_0FXOP_09_DB_L_0,
1589   VEX_W_0FXOP_09_E1_L_0,
1590   VEX_W_0FXOP_09_E2_L_0,
1591   VEX_W_0FXOP_09_E3_L_0,
1592
1593   EVEX_W_0F5B_P_0,
1594   EVEX_W_0F62,
1595   EVEX_W_0F66,
1596   EVEX_W_0F6A,
1597   EVEX_W_0F6B,
1598   EVEX_W_0F6C,
1599   EVEX_W_0F6D,
1600   EVEX_W_0F6F_P_1,
1601   EVEX_W_0F6F_P_2,
1602   EVEX_W_0F6F_P_3,
1603   EVEX_W_0F70_P_2,
1604   EVEX_W_0F72_R_2,
1605   EVEX_W_0F72_R_6,
1606   EVEX_W_0F73_R_2,
1607   EVEX_W_0F73_R_6,
1608   EVEX_W_0F76,
1609   EVEX_W_0F78_P_0,
1610   EVEX_W_0F78_P_2,
1611   EVEX_W_0F79_P_0,
1612   EVEX_W_0F79_P_2,
1613   EVEX_W_0F7A_P_1,
1614   EVEX_W_0F7A_P_2,
1615   EVEX_W_0F7A_P_3,
1616   EVEX_W_0F7B_P_2,
1617   EVEX_W_0F7E_P_1,
1618   EVEX_W_0F7F_P_1,
1619   EVEX_W_0F7F_P_2,
1620   EVEX_W_0F7F_P_3,
1621   EVEX_W_0FD2,
1622   EVEX_W_0FD3,
1623   EVEX_W_0FD4,
1624   EVEX_W_0FD6,
1625   EVEX_W_0FE6_P_1,
1626   EVEX_W_0FE7,
1627   EVEX_W_0FF2,
1628   EVEX_W_0FF3,
1629   EVEX_W_0FF4,
1630   EVEX_W_0FFA,
1631   EVEX_W_0FFB,
1632   EVEX_W_0FFE,
1633
1634   EVEX_W_0F3810_P_1,
1635   EVEX_W_0F3810_P_2,
1636   EVEX_W_0F3811_P_1,
1637   EVEX_W_0F3811_P_2,
1638   EVEX_W_0F3812_P_1,
1639   EVEX_W_0F3812_P_2,
1640   EVEX_W_0F3813_P_1,
1641   EVEX_W_0F3814_P_1,
1642   EVEX_W_0F3815_P_1,
1643   EVEX_W_0F3819_L_n,
1644   EVEX_W_0F381A_M_0_L_n,
1645   EVEX_W_0F381B_M_0_L_2,
1646   EVEX_W_0F381E,
1647   EVEX_W_0F381F,
1648   EVEX_W_0F3820_P_1,
1649   EVEX_W_0F3821_P_1,
1650   EVEX_W_0F3822_P_1,
1651   EVEX_W_0F3823_P_1,
1652   EVEX_W_0F3824_P_1,
1653   EVEX_W_0F3825_P_1,
1654   EVEX_W_0F3825_P_2,
1655   EVEX_W_0F3828_P_2,
1656   EVEX_W_0F3829_P_2,
1657   EVEX_W_0F382A_P_1,
1658   EVEX_W_0F382A_P_2,
1659   EVEX_W_0F382B,
1660   EVEX_W_0F3830_P_1,
1661   EVEX_W_0F3831_P_1,
1662   EVEX_W_0F3832_P_1,
1663   EVEX_W_0F3833_P_1,
1664   EVEX_W_0F3834_P_1,
1665   EVEX_W_0F3835_P_1,
1666   EVEX_W_0F3835_P_2,
1667   EVEX_W_0F3837,
1668   EVEX_W_0F383A_P_1,
1669   EVEX_W_0F3859,
1670   EVEX_W_0F385A_M_0_L_n,
1671   EVEX_W_0F385B_M_0_L_2,
1672   EVEX_W_0F3870,
1673   EVEX_W_0F3872_P_2,
1674   EVEX_W_0F387A,
1675   EVEX_W_0F387B,
1676   EVEX_W_0F3883,
1677
1678   EVEX_W_0F3A18_L_n,
1679   EVEX_W_0F3A19_L_n,
1680   EVEX_W_0F3A1A_L_2,
1681   EVEX_W_0F3A1B_L_2,
1682   EVEX_W_0F3A21,
1683   EVEX_W_0F3A23_L_n,
1684   EVEX_W_0F3A38_L_n,
1685   EVEX_W_0F3A39_L_n,
1686   EVEX_W_0F3A3A_L_2,
1687   EVEX_W_0F3A3B_L_2,
1688   EVEX_W_0F3A42,
1689   EVEX_W_0F3A43_L_n,
1690   EVEX_W_0F3A70,
1691   EVEX_W_0F3A72,
1692
1693   EVEX_W_MAP5_5B_P_0,
1694   EVEX_W_MAP5_7A_P_3,
1695 };
1696
1697 typedef void (*op_rtn) (instr_info *ins, int bytemode, int sizeflag);
1698
1699 struct dis386 {
1700   const char *name;
1701   struct
1702     {
1703       op_rtn rtn;
1704       int bytemode;
1705     } op[MAX_OPERANDS];
1706   unsigned int prefix_requirement;
1707 };
1708
1709 /* Upper case letters in the instruction names here are macros.
1710    'A' => print 'b' if no register operands or suffix_always is true
1711    'B' => print 'b' if suffix_always is true
1712    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1713           size prefix
1714    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1715           suffix_always is true
1716    'E' => print 'e' if 32-bit form of jcxz
1717    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1718    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1719    'H' => print ",pt" or ",pn" branch hint
1720    'I' unused.
1721    'J' unused.
1722    'K' => print 'd' or 'q' if rex prefix is present.
1723    'L' unused.
1724    'M' => print 'r' if intel_mnemonic is false.
1725    'N' => print 'n' if instruction has no wait "prefix"
1726    'O' => print 'd' or 'o' (or 'q' in Intel mode)
1727    'P' => behave as 'T' except with register operand outside of suffix_always
1728           mode
1729    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1730           is true
1731    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1732    'S' => print 'w', 'l' or 'q' if suffix_always is true
1733    'T' => print 'w', 'l'/'d', or 'q' if instruction has an operand size
1734           prefix or if suffix_always is true.
1735    'U' unused.
1736    'V' unused.
1737    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1738    'X' => print 's', 'd' depending on data16 prefix (for XMM)
1739    'Y' unused.
1740    'Z' => print 'q' in 64bit mode and 'l' otherwise, if suffix_always is true.
1741    '!' => change condition from true to false or from false to true.
1742    '%' => add 1 upper case letter to the macro.
1743    '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
1744           prefix or suffix_always is true (lcall/ljmp).
1745    '@' => in 64bit mode for Intel64 ISA or if instruction
1746           has no operand sizing prefix, print 'q' if suffix_always is true or
1747           nothing otherwise; behave as 'P' in all other cases
1748
1749    2 upper case letter macros:
1750    "XY" => print 'x' or 'y' if suffix_always is true or no register
1751            operands and no broadcast.
1752    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
1753            register operands and no broadcast.
1754    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1755    "XD" => print 'd' if !EVEX or EVEX.W=1, EVEX.W=0 is not a valid encoding
1756    "XH" => print 'h' if EVEX.W=0, EVEX.W=1 is not a valid encoding (for FP16)
1757    "XS" => print 's' if !EVEX or EVEX.W=0, EVEX.W=1 is not a valid encoding
1758    "XV" => print "{vex3}" pseudo prefix
1759    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond
1760            being false, or no operand at all in 64bit mode, or if suffix_always
1761            is true.
1762    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1763    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1764    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1765    "DQ" => print 'd' or 'q' depending on the VEX.W bit
1766    "BW" => print 'b' or 'w' depending on the VEX.W bit
1767    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
1768            an operand size prefix, or suffix_always is true.  print
1769            'q' if rex prefix is present.
1770
1771    Many of the above letters print nothing in Intel mode.  See "putop"
1772    for the details.
1773
1774    Braces '{' and '}', and vertical bars '|', indicate alternative
1775    mnemonic strings for AT&T and Intel.  */
1776
1777 static const struct dis386 dis386[] = {
1778   /* 00 */
1779   { "addB",             { Ebh1, Gb }, 0 },
1780   { "addS",             { Evh1, Gv }, 0 },
1781   { "addB",             { Gb, EbS }, 0 },
1782   { "addS",             { Gv, EvS }, 0 },
1783   { "addB",             { AL, Ib }, 0 },
1784   { "addS",             { eAX, Iv }, 0 },
1785   { X86_64_TABLE (X86_64_06) },
1786   { X86_64_TABLE (X86_64_07) },
1787   /* 08 */
1788   { "orB",              { Ebh1, Gb }, 0 },
1789   { "orS",              { Evh1, Gv }, 0 },
1790   { "orB",              { Gb, EbS }, 0 },
1791   { "orS",              { Gv, EvS }, 0 },
1792   { "orB",              { AL, Ib }, 0 },
1793   { "orS",              { eAX, Iv }, 0 },
1794   { X86_64_TABLE (X86_64_0E) },
1795   { Bad_Opcode },       /* 0x0f extended opcode escape */
1796   /* 10 */
1797   { "adcB",             { Ebh1, Gb }, 0 },
1798   { "adcS",             { Evh1, Gv }, 0 },
1799   { "adcB",             { Gb, EbS }, 0 },
1800   { "adcS",             { Gv, EvS }, 0 },
1801   { "adcB",             { AL, Ib }, 0 },
1802   { "adcS",             { eAX, Iv }, 0 },
1803   { X86_64_TABLE (X86_64_16) },
1804   { X86_64_TABLE (X86_64_17) },
1805   /* 18 */
1806   { "sbbB",             { Ebh1, Gb }, 0 },
1807   { "sbbS",             { Evh1, Gv }, 0 },
1808   { "sbbB",             { Gb, EbS }, 0 },
1809   { "sbbS",             { Gv, EvS }, 0 },
1810   { "sbbB",             { AL, Ib }, 0 },
1811   { "sbbS",             { eAX, Iv }, 0 },
1812   { X86_64_TABLE (X86_64_1E) },
1813   { X86_64_TABLE (X86_64_1F) },
1814   /* 20 */
1815   { "andB",             { Ebh1, Gb }, 0 },
1816   { "andS",             { Evh1, Gv }, 0 },
1817   { "andB",             { Gb, EbS }, 0 },
1818   { "andS",             { Gv, EvS }, 0 },
1819   { "andB",             { AL, Ib }, 0 },
1820   { "andS",             { eAX, Iv }, 0 },
1821   { Bad_Opcode },       /* SEG ES prefix */
1822   { X86_64_TABLE (X86_64_27) },
1823   /* 28 */
1824   { "subB",             { Ebh1, Gb }, 0 },
1825   { "subS",             { Evh1, Gv }, 0 },
1826   { "subB",             { Gb, EbS }, 0 },
1827   { "subS",             { Gv, EvS }, 0 },
1828   { "subB",             { AL, Ib }, 0 },
1829   { "subS",             { eAX, Iv }, 0 },
1830   { Bad_Opcode },       /* SEG CS prefix */
1831   { X86_64_TABLE (X86_64_2F) },
1832   /* 30 */
1833   { "xorB",             { Ebh1, Gb }, 0 },
1834   { "xorS",             { Evh1, Gv }, 0 },
1835   { "xorB",             { Gb, EbS }, 0 },
1836   { "xorS",             { Gv, EvS }, 0 },
1837   { "xorB",             { AL, Ib }, 0 },
1838   { "xorS",             { eAX, Iv }, 0 },
1839   { Bad_Opcode },       /* SEG SS prefix */
1840   { X86_64_TABLE (X86_64_37) },
1841   /* 38 */
1842   { "cmpB",             { Eb, Gb }, 0 },
1843   { "cmpS",             { Ev, Gv }, 0 },
1844   { "cmpB",             { Gb, EbS }, 0 },
1845   { "cmpS",             { Gv, EvS }, 0 },
1846   { "cmpB",             { AL, Ib }, 0 },
1847   { "cmpS",             { eAX, Iv }, 0 },
1848   { Bad_Opcode },       /* SEG DS prefix */
1849   { X86_64_TABLE (X86_64_3F) },
1850   /* 40 */
1851   { "inc{S|}",          { RMeAX }, 0 },
1852   { "inc{S|}",          { RMeCX }, 0 },
1853   { "inc{S|}",          { RMeDX }, 0 },
1854   { "inc{S|}",          { RMeBX }, 0 },
1855   { "inc{S|}",          { RMeSP }, 0 },
1856   { "inc{S|}",          { RMeBP }, 0 },
1857   { "inc{S|}",          { RMeSI }, 0 },
1858   { "inc{S|}",          { RMeDI }, 0 },
1859   /* 48 */
1860   { "dec{S|}",          { RMeAX }, 0 },
1861   { "dec{S|}",          { RMeCX }, 0 },
1862   { "dec{S|}",          { RMeDX }, 0 },
1863   { "dec{S|}",          { RMeBX }, 0 },
1864   { "dec{S|}",          { RMeSP }, 0 },
1865   { "dec{S|}",          { RMeBP }, 0 },
1866   { "dec{S|}",          { RMeSI }, 0 },
1867   { "dec{S|}",          { RMeDI }, 0 },
1868   /* 50 */
1869   { "push{!P|}",                { RMrAX }, 0 },
1870   { "push{!P|}",                { RMrCX }, 0 },
1871   { "push{!P|}",                { RMrDX }, 0 },
1872   { "push{!P|}",                { RMrBX }, 0 },
1873   { "push{!P|}",                { RMrSP }, 0 },
1874   { "push{!P|}",                { RMrBP }, 0 },
1875   { "push{!P|}",                { RMrSI }, 0 },
1876   { "push{!P|}",                { RMrDI }, 0 },
1877   /* 58 */
1878   { "pop{!P|}",         { RMrAX }, 0 },
1879   { "pop{!P|}",         { RMrCX }, 0 },
1880   { "pop{!P|}",         { RMrDX }, 0 },
1881   { "pop{!P|}",         { RMrBX }, 0 },
1882   { "pop{!P|}",         { RMrSP }, 0 },
1883   { "pop{!P|}",         { RMrBP }, 0 },
1884   { "pop{!P|}",         { RMrSI }, 0 },
1885   { "pop{!P|}",         { RMrDI }, 0 },
1886   /* 60 */
1887   { X86_64_TABLE (X86_64_60) },
1888   { X86_64_TABLE (X86_64_61) },
1889   { X86_64_TABLE (X86_64_62) },
1890   { X86_64_TABLE (X86_64_63) },
1891   { Bad_Opcode },       /* seg fs */
1892   { Bad_Opcode },       /* seg gs */
1893   { Bad_Opcode },       /* op size prefix */
1894   { Bad_Opcode },       /* adr size prefix */
1895   /* 68 */
1896   { "pushP",            { sIv }, 0 },
1897   { "imulS",            { Gv, Ev, Iv }, 0 },
1898   { "pushP",            { sIbT }, 0 },
1899   { "imulS",            { Gv, Ev, sIb }, 0 },
1900   { "ins{b|}",          { Ybr, indirDX }, 0 },
1901   { X86_64_TABLE (X86_64_6D) },
1902   { "outs{b|}",         { indirDXr, Xb }, 0 },
1903   { X86_64_TABLE (X86_64_6F) },
1904   /* 70 */
1905   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
1906   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
1907   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
1908   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
1909   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
1910   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
1911   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
1912   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
1913   /* 78 */
1914   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
1915   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
1916   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
1917   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
1918   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
1919   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
1920   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
1921   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
1922   /* 80 */
1923   { REG_TABLE (REG_80) },
1924   { REG_TABLE (REG_81) },
1925   { X86_64_TABLE (X86_64_82) },
1926   { REG_TABLE (REG_83) },
1927   { "testB",            { Eb, Gb }, 0 },
1928   { "testS",            { Ev, Gv }, 0 },
1929   { "xchgB",            { Ebh2, Gb }, 0 },
1930   { "xchgS",            { Evh2, Gv }, 0 },
1931   /* 88 */
1932   { "movB",             { Ebh3, Gb }, 0 },
1933   { "movS",             { Evh3, Gv }, 0 },
1934   { "movB",             { Gb, EbS }, 0 },
1935   { "movS",             { Gv, EvS }, 0 },
1936   { "movD",             { Sv, Sw }, 0 },
1937   { MOD_TABLE (MOD_8D) },
1938   { "movD",             { Sw, Sv }, 0 },
1939   { REG_TABLE (REG_8F) },
1940   /* 90 */
1941   { PREFIX_TABLE (PREFIX_90) },
1942   { "xchgS",            { RMeCX, eAX }, 0 },
1943   { "xchgS",            { RMeDX, eAX }, 0 },
1944   { "xchgS",            { RMeBX, eAX }, 0 },
1945   { "xchgS",            { RMeSP, eAX }, 0 },
1946   { "xchgS",            { RMeBP, eAX }, 0 },
1947   { "xchgS",            { RMeSI, eAX }, 0 },
1948   { "xchgS",            { RMeDI, eAX }, 0 },
1949   /* 98 */
1950   { "cW{t|}R",          { XX }, 0 },
1951   { "cR{t|}O",          { XX }, 0 },
1952   { X86_64_TABLE (X86_64_9A) },
1953   { Bad_Opcode },       /* fwait */
1954   { "pushfP",           { XX }, 0 },
1955   { "popfP",            { XX }, 0 },
1956   { "sahf",             { XX }, 0 },
1957   { "lahf",             { XX }, 0 },
1958   /* a0 */
1959   { "mov%LB",           { AL, Ob }, 0 },
1960   { "mov%LS",           { eAX, Ov }, 0 },
1961   { "mov%LB",           { Ob, AL }, 0 },
1962   { "mov%LS",           { Ov, eAX }, 0 },
1963   { "movs{b|}",         { Ybr, Xb }, 0 },
1964   { "movs{R|}",         { Yvr, Xv }, 0 },
1965   { "cmps{b|}",         { Xb, Yb }, 0 },
1966   { "cmps{R|}",         { Xv, Yv }, 0 },
1967   /* a8 */
1968   { "testB",            { AL, Ib }, 0 },
1969   { "testS",            { eAX, Iv }, 0 },
1970   { "stosB",            { Ybr, AL }, 0 },
1971   { "stosS",            { Yvr, eAX }, 0 },
1972   { "lodsB",            { ALr, Xb }, 0 },
1973   { "lodsS",            { eAXr, Xv }, 0 },
1974   { "scasB",            { AL, Yb }, 0 },
1975   { "scasS",            { eAX, Yv }, 0 },
1976   /* b0 */
1977   { "movB",             { RMAL, Ib }, 0 },
1978   { "movB",             { RMCL, Ib }, 0 },
1979   { "movB",             { RMDL, Ib }, 0 },
1980   { "movB",             { RMBL, Ib }, 0 },
1981   { "movB",             { RMAH, Ib }, 0 },
1982   { "movB",             { RMCH, Ib }, 0 },
1983   { "movB",             { RMDH, Ib }, 0 },
1984   { "movB",             { RMBH, Ib }, 0 },
1985   /* b8 */
1986   { "mov%LV",           { RMeAX, Iv64 }, 0 },
1987   { "mov%LV",           { RMeCX, Iv64 }, 0 },
1988   { "mov%LV",           { RMeDX, Iv64 }, 0 },
1989   { "mov%LV",           { RMeBX, Iv64 }, 0 },
1990   { "mov%LV",           { RMeSP, Iv64 }, 0 },
1991   { "mov%LV",           { RMeBP, Iv64 }, 0 },
1992   { "mov%LV",           { RMeSI, Iv64 }, 0 },
1993   { "mov%LV",           { RMeDI, Iv64 }, 0 },
1994   /* c0 */
1995   { REG_TABLE (REG_C0) },
1996   { REG_TABLE (REG_C1) },
1997   { X86_64_TABLE (X86_64_C2) },
1998   { X86_64_TABLE (X86_64_C3) },
1999   { X86_64_TABLE (X86_64_C4) },
2000   { X86_64_TABLE (X86_64_C5) },
2001   { REG_TABLE (REG_C6) },
2002   { REG_TABLE (REG_C7) },
2003   /* c8 */
2004   { "enterP",           { Iw, Ib }, 0 },
2005   { "leaveP",           { XX }, 0 },
2006   { "{l|}ret{|f}%LP",   { Iw }, 0 },
2007   { "{l|}ret{|f}%LP",   { XX }, 0 },
2008   { "int3",             { XX }, 0 },
2009   { "int",              { Ib }, 0 },
2010   { X86_64_TABLE (X86_64_CE) },
2011   { "iret%LP",          { XX }, 0 },
2012   /* d0 */
2013   { REG_TABLE (REG_D0) },
2014   { REG_TABLE (REG_D1) },
2015   { REG_TABLE (REG_D2) },
2016   { REG_TABLE (REG_D3) },
2017   { X86_64_TABLE (X86_64_D4) },
2018   { X86_64_TABLE (X86_64_D5) },
2019   { Bad_Opcode },
2020   { "xlat",             { DSBX }, 0 },
2021   /* d8 */
2022   { FLOAT },
2023   { FLOAT },
2024   { FLOAT },
2025   { FLOAT },
2026   { FLOAT },
2027   { FLOAT },
2028   { FLOAT },
2029   { FLOAT },
2030   /* e0 */
2031   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2032   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2033   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2034   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2035   { "inB",              { AL, Ib }, 0 },
2036   { "inG",              { zAX, Ib }, 0 },
2037   { "outB",             { Ib, AL }, 0 },
2038   { "outG",             { Ib, zAX }, 0 },
2039   /* e8 */
2040   { X86_64_TABLE (X86_64_E8) },
2041   { X86_64_TABLE (X86_64_E9) },
2042   { X86_64_TABLE (X86_64_EA) },
2043   { "jmp",              { Jb, BND }, 0 },
2044   { "inB",              { AL, indirDX }, 0 },
2045   { "inG",              { zAX, indirDX }, 0 },
2046   { "outB",             { indirDX, AL }, 0 },
2047   { "outG",             { indirDX, zAX }, 0 },
2048   /* f0 */
2049   { Bad_Opcode },       /* lock prefix */
2050   { "int1",             { XX }, 0 },
2051   { Bad_Opcode },       /* repne */
2052   { Bad_Opcode },       /* repz */
2053   { "hlt",              { XX }, 0 },
2054   { "cmc",              { XX }, 0 },
2055   { REG_TABLE (REG_F6) },
2056   { REG_TABLE (REG_F7) },
2057   /* f8 */
2058   { "clc",              { XX }, 0 },
2059   { "stc",              { XX }, 0 },
2060   { "cli",              { XX }, 0 },
2061   { "sti",              { XX }, 0 },
2062   { "cld",              { XX }, 0 },
2063   { "std",              { XX }, 0 },
2064   { REG_TABLE (REG_FE) },
2065   { REG_TABLE (REG_FF) },
2066 };
2067
2068 static const struct dis386 dis386_twobyte[] = {
2069   /* 00 */
2070   { REG_TABLE (REG_0F00 ) },
2071   { REG_TABLE (REG_0F01 ) },
2072   { "larS",             { Gv, Ew }, 0 },
2073   { "lslS",             { Gv, Ew }, 0 },
2074   { Bad_Opcode },
2075   { "syscall",          { XX }, 0 },
2076   { "clts",             { XX }, 0 },
2077   { "sysret%LQ",                { XX }, 0 },
2078   /* 08 */
2079   { "invd",             { XX }, 0 },
2080   { PREFIX_TABLE (PREFIX_0F09) },
2081   { Bad_Opcode },
2082   { "ud2",              { XX }, 0 },
2083   { Bad_Opcode },
2084   { REG_TABLE (REG_0F0D) },
2085   { "femms",            { XX }, 0 },
2086   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2087   /* 10 */
2088   { PREFIX_TABLE (PREFIX_0F10) },
2089   { PREFIX_TABLE (PREFIX_0F11) },
2090   { PREFIX_TABLE (PREFIX_0F12) },
2091   { MOD_TABLE (MOD_0F13) },
2092   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2093   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2094   { PREFIX_TABLE (PREFIX_0F16) },
2095   { MOD_TABLE (MOD_0F17) },
2096   /* 18 */
2097   { REG_TABLE (REG_0F18) },
2098   { "nopQ",             { Ev }, 0 },
2099   { PREFIX_TABLE (PREFIX_0F1A) },
2100   { PREFIX_TABLE (PREFIX_0F1B) },
2101   { PREFIX_TABLE (PREFIX_0F1C) },
2102   { "nopQ",             { Ev }, 0 },
2103   { PREFIX_TABLE (PREFIX_0F1E) },
2104   { "nopQ",             { Ev }, 0 },
2105   /* 20 */
2106   { "movZ",             { Em, Cm }, 0 },
2107   { "movZ",             { Em, Dm }, 0 },
2108   { "movZ",             { Cm, Em }, 0 },
2109   { "movZ",             { Dm, Em }, 0 },
2110   { X86_64_TABLE (X86_64_0F24) },
2111   { Bad_Opcode },
2112   { X86_64_TABLE (X86_64_0F26) },
2113   { Bad_Opcode },
2114   /* 28 */
2115   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2116   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2117   { PREFIX_TABLE (PREFIX_0F2A) },
2118   { PREFIX_TABLE (PREFIX_0F2B) },
2119   { PREFIX_TABLE (PREFIX_0F2C) },
2120   { PREFIX_TABLE (PREFIX_0F2D) },
2121   { PREFIX_TABLE (PREFIX_0F2E) },
2122   { PREFIX_TABLE (PREFIX_0F2F) },
2123   /* 30 */
2124   { "wrmsr",            { XX }, 0 },
2125   { "rdtsc",            { XX }, 0 },
2126   { "rdmsr",            { XX }, 0 },
2127   { "rdpmc",            { XX }, 0 },
2128   { "sysenter",         { SEP }, 0 },
2129   { "sysexit%LQ",       { SEP }, 0 },
2130   { Bad_Opcode },
2131   { "getsec",           { XX }, 0 },
2132   /* 38 */
2133   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2134   { Bad_Opcode },
2135   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2136   { Bad_Opcode },
2137   { Bad_Opcode },
2138   { Bad_Opcode },
2139   { Bad_Opcode },
2140   { Bad_Opcode },
2141   /* 40 */
2142   { "cmovoS",           { Gv, Ev }, 0 },
2143   { "cmovnoS",          { Gv, Ev }, 0 },
2144   { "cmovbS",           { Gv, Ev }, 0 },
2145   { "cmovaeS",          { Gv, Ev }, 0 },
2146   { "cmoveS",           { Gv, Ev }, 0 },
2147   { "cmovneS",          { Gv, Ev }, 0 },
2148   { "cmovbeS",          { Gv, Ev }, 0 },
2149   { "cmovaS",           { Gv, Ev }, 0 },
2150   /* 48 */
2151   { "cmovsS",           { Gv, Ev }, 0 },
2152   { "cmovnsS",          { Gv, Ev }, 0 },
2153   { "cmovpS",           { Gv, Ev }, 0 },
2154   { "cmovnpS",          { Gv, Ev }, 0 },
2155   { "cmovlS",           { Gv, Ev }, 0 },
2156   { "cmovgeS",          { Gv, Ev }, 0 },
2157   { "cmovleS",          { Gv, Ev }, 0 },
2158   { "cmovgS",           { Gv, Ev }, 0 },
2159   /* 50 */
2160   { MOD_TABLE (MOD_0F50) },
2161   { PREFIX_TABLE (PREFIX_0F51) },
2162   { PREFIX_TABLE (PREFIX_0F52) },
2163   { PREFIX_TABLE (PREFIX_0F53) },
2164   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2165   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2166   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2167   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2168   /* 58 */
2169   { PREFIX_TABLE (PREFIX_0F58) },
2170   { PREFIX_TABLE (PREFIX_0F59) },
2171   { PREFIX_TABLE (PREFIX_0F5A) },
2172   { PREFIX_TABLE (PREFIX_0F5B) },
2173   { PREFIX_TABLE (PREFIX_0F5C) },
2174   { PREFIX_TABLE (PREFIX_0F5D) },
2175   { PREFIX_TABLE (PREFIX_0F5E) },
2176   { PREFIX_TABLE (PREFIX_0F5F) },
2177   /* 60 */
2178   { PREFIX_TABLE (PREFIX_0F60) },
2179   { PREFIX_TABLE (PREFIX_0F61) },
2180   { PREFIX_TABLE (PREFIX_0F62) },
2181   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2182   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2183   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2184   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2185   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2186   /* 68 */
2187   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2188   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2189   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2190   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2191   { "punpcklqdq", { XM, EXx }, PREFIX_DATA },
2192   { "punpckhqdq", { XM, EXx }, PREFIX_DATA },
2193   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2194   { PREFIX_TABLE (PREFIX_0F6F) },
2195   /* 70 */
2196   { PREFIX_TABLE (PREFIX_0F70) },
2197   { MOD_TABLE (MOD_0F71) },
2198   { MOD_TABLE (MOD_0F72) },
2199   { MOD_TABLE (MOD_0F73) },
2200   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2201   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2202   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2203   { "emms",             { XX }, PREFIX_OPCODE },
2204   /* 78 */
2205   { PREFIX_TABLE (PREFIX_0F78) },
2206   { PREFIX_TABLE (PREFIX_0F79) },
2207   { Bad_Opcode },
2208   { Bad_Opcode },
2209   { PREFIX_TABLE (PREFIX_0F7C) },
2210   { PREFIX_TABLE (PREFIX_0F7D) },
2211   { PREFIX_TABLE (PREFIX_0F7E) },
2212   { PREFIX_TABLE (PREFIX_0F7F) },
2213   /* 80 */
2214   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2215   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2216   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2217   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2218   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2219   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2220   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2221   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2222   /* 88 */
2223   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2224   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2225   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2226   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2227   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2228   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2229   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2230   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2231   /* 90 */
2232   { "seto",             { Eb }, 0 },
2233   { "setno",            { Eb }, 0 },
2234   { "setb",             { Eb }, 0 },
2235   { "setae",            { Eb }, 0 },
2236   { "sete",             { Eb }, 0 },
2237   { "setne",            { Eb }, 0 },
2238   { "setbe",            { Eb }, 0 },
2239   { "seta",             { Eb }, 0 },
2240   /* 98 */
2241   { "sets",             { Eb }, 0 },
2242   { "setns",            { Eb }, 0 },
2243   { "setp",             { Eb }, 0 },
2244   { "setnp",            { Eb }, 0 },
2245   { "setl",             { Eb }, 0 },
2246   { "setge",            { Eb }, 0 },
2247   { "setle",            { Eb }, 0 },
2248   { "setg",             { Eb }, 0 },
2249   /* a0 */
2250   { "pushP",            { fs }, 0 },
2251   { "popP",             { fs }, 0 },
2252   { "cpuid",            { XX }, 0 },
2253   { "btS",              { Ev, Gv }, 0 },
2254   { "shldS",            { Ev, Gv, Ib }, 0 },
2255   { "shldS",            { Ev, Gv, CL }, 0 },
2256   { REG_TABLE (REG_0FA6) },
2257   { REG_TABLE (REG_0FA7) },
2258   /* a8 */
2259   { "pushP",            { gs }, 0 },
2260   { "popP",             { gs }, 0 },
2261   { "rsm",              { XX }, 0 },
2262   { "btsS",             { Evh1, Gv }, 0 },
2263   { "shrdS",            { Ev, Gv, Ib }, 0 },
2264   { "shrdS",            { Ev, Gv, CL }, 0 },
2265   { REG_TABLE (REG_0FAE) },
2266   { "imulS",            { Gv, Ev }, 0 },
2267   /* b0 */
2268   { "cmpxchgB",         { Ebh1, Gb }, 0 },
2269   { "cmpxchgS",         { Evh1, Gv }, 0 },
2270   { MOD_TABLE (MOD_0FB2) },
2271   { "btrS",             { Evh1, Gv }, 0 },
2272   { MOD_TABLE (MOD_0FB4) },
2273   { MOD_TABLE (MOD_0FB5) },
2274   { "movz{bR|x}",       { Gv, Eb }, 0 },
2275   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2276   /* b8 */
2277   { PREFIX_TABLE (PREFIX_0FB8) },
2278   { "ud1S",             { Gv, Ev }, 0 },
2279   { REG_TABLE (REG_0FBA) },
2280   { "btcS",             { Evh1, Gv }, 0 },
2281   { PREFIX_TABLE (PREFIX_0FBC) },
2282   { PREFIX_TABLE (PREFIX_0FBD) },
2283   { "movs{bR|x}",       { Gv, Eb }, 0 },
2284   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2285   /* c0 */
2286   { "xaddB",            { Ebh1, Gb }, 0 },
2287   { "xaddS",            { Evh1, Gv }, 0 },
2288   { PREFIX_TABLE (PREFIX_0FC2) },
2289   { MOD_TABLE (MOD_0FC3) },
2290   { "pinsrw",           { MX, Edw, Ib }, PREFIX_OPCODE },
2291   { "pextrw",           { Gd, MS, Ib }, PREFIX_OPCODE },
2292   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
2293   { REG_TABLE (REG_0FC7) },
2294   /* c8 */
2295   { "bswap",            { RMeAX }, 0 },
2296   { "bswap",            { RMeCX }, 0 },
2297   { "bswap",            { RMeDX }, 0 },
2298   { "bswap",            { RMeBX }, 0 },
2299   { "bswap",            { RMeSP }, 0 },
2300   { "bswap",            { RMeBP }, 0 },
2301   { "bswap",            { RMeSI }, 0 },
2302   { "bswap",            { RMeDI }, 0 },
2303   /* d0 */
2304   { PREFIX_TABLE (PREFIX_0FD0) },
2305   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
2306   { "psrld",            { MX, EM }, PREFIX_OPCODE },
2307   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
2308   { "paddq",            { MX, EM }, PREFIX_OPCODE },
2309   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
2310   { PREFIX_TABLE (PREFIX_0FD6) },
2311   { MOD_TABLE (MOD_0FD7) },
2312   /* d8 */
2313   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
2314   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
2315   { "pminub",           { MX, EM }, PREFIX_OPCODE },
2316   { "pand",             { MX, EM }, PREFIX_OPCODE },
2317   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
2318   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
2319   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
2320   { "pandn",            { MX, EM }, PREFIX_OPCODE },
2321   /* e0 */
2322   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
2323   { "psraw",            { MX, EM }, PREFIX_OPCODE },
2324   { "psrad",            { MX, EM }, PREFIX_OPCODE },
2325   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
2326   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
2327   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
2328   { PREFIX_TABLE (PREFIX_0FE6) },
2329   { PREFIX_TABLE (PREFIX_0FE7) },
2330   /* e8 */
2331   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
2332   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
2333   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
2334   { "por",              { MX, EM }, PREFIX_OPCODE },
2335   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
2336   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
2337   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
2338   { "pxor",             { MX, EM }, PREFIX_OPCODE },
2339   /* f0 */
2340   { PREFIX_TABLE (PREFIX_0FF0) },
2341   { "psllw",            { MX, EM }, PREFIX_OPCODE },
2342   { "pslld",            { MX, EM }, PREFIX_OPCODE },
2343   { "psllq",            { MX, EM }, PREFIX_OPCODE },
2344   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
2345   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
2346   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
2347   { PREFIX_TABLE (PREFIX_0FF7) },
2348   /* f8 */
2349   { "psubb",            { MX, EM }, PREFIX_OPCODE },
2350   { "psubw",            { MX, EM }, PREFIX_OPCODE },
2351   { "psubd",            { MX, EM }, PREFIX_OPCODE },
2352   { "psubq",            { MX, EM }, PREFIX_OPCODE },
2353   { "paddb",            { MX, EM }, PREFIX_OPCODE },
2354   { "paddw",            { MX, EM }, PREFIX_OPCODE },
2355   { "paddd",            { MX, EM }, PREFIX_OPCODE },
2356   { "ud0S",             { Gv, Ev }, 0 },
2357 };
2358
2359 static const bool onebyte_has_modrm[256] = {
2360   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2361   /*       -------------------------------        */
2362   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2363   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2364   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2365   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2366   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2367   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2368   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2369   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2370   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2371   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2372   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2373   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2374   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2375   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2376   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2377   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2378   /*       -------------------------------        */
2379   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2380 };
2381
2382 static const bool twobyte_has_modrm[256] = {
2383   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2384   /*       -------------------------------        */
2385   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2386   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2387   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2388   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2389   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2390   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2391   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2392   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2393   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2394   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2395   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2396   /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2397   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2398   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2399   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2400   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1  /* ff */
2401   /*       -------------------------------        */
2402   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2403 };
2404
2405
2406 struct op
2407   {
2408     const char *name;
2409     unsigned int len;
2410   };
2411
2412 /* If we are accessing mod/rm/reg without need_modrm set, then the
2413    values are stale.  Hitting this abort likely indicates that you
2414    need to update onebyte_has_modrm or twobyte_has_modrm.  */
2415 #define MODRM_CHECK  if (!ins->need_modrm) abort ()
2416
2417 static const char *const intel_index16[] = {
2418   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2419 };
2420
2421 static const char *const att_names64[] = {
2422   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2423   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2424 };
2425 static const char *const att_names32[] = {
2426   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2427   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2428 };
2429 static const char *const att_names16[] = {
2430   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2431   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2432 };
2433 static const char *const att_names8[] = {
2434   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2435 };
2436 static const char *const att_names8rex[] = {
2437   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2438   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2439 };
2440 static const char *const att_names_seg[] = {
2441   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2442 };
2443 static const char att_index64[] = "%riz";
2444 static const char att_index32[] = "%eiz";
2445 static const char *const att_index16[] = {
2446   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2447 };
2448
2449 static const char *const att_names_mm[] = {
2450   "%mm0", "%mm1", "%mm2", "%mm3",
2451   "%mm4", "%mm5", "%mm6", "%mm7"
2452 };
2453
2454 static const char *const att_names_bnd[] = {
2455   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
2456 };
2457
2458 static const char *const att_names_xmm[] = {
2459   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2460   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2461   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2462   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
2463   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
2464   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
2465   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
2466   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
2467 };
2468
2469 static const char *const att_names_ymm[] = {
2470   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2471   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2472   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2473   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
2474   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
2475   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
2476   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
2477   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
2478 };
2479
2480 static const char *const att_names_zmm[] = {
2481   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
2482   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
2483   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
2484   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
2485   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
2486   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
2487   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
2488   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
2489 };
2490
2491 static const char *const att_names_tmm[] = {
2492   "%tmm0", "%tmm1", "%tmm2", "%tmm3",
2493   "%tmm4", "%tmm5", "%tmm6", "%tmm7"
2494 };
2495
2496 static const char *const att_names_mask[] = {
2497   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
2498 };
2499
2500 static const char *const names_rounding[] =
2501 {
2502   "{rn-",
2503   "{rd-",
2504   "{ru-",
2505   "{rz-"
2506 };
2507
2508 static const struct dis386 reg_table[][8] = {
2509   /* REG_80 */
2510   {
2511     { "addA",   { Ebh1, Ib }, 0 },
2512     { "orA",    { Ebh1, Ib }, 0 },
2513     { "adcA",   { Ebh1, Ib }, 0 },
2514     { "sbbA",   { Ebh1, Ib }, 0 },
2515     { "andA",   { Ebh1, Ib }, 0 },
2516     { "subA",   { Ebh1, Ib }, 0 },
2517     { "xorA",   { Ebh1, Ib }, 0 },
2518     { "cmpA",   { Eb, Ib }, 0 },
2519   },
2520   /* REG_81 */
2521   {
2522     { "addQ",   { Evh1, Iv }, 0 },
2523     { "orQ",    { Evh1, Iv }, 0 },
2524     { "adcQ",   { Evh1, Iv }, 0 },
2525     { "sbbQ",   { Evh1, Iv }, 0 },
2526     { "andQ",   { Evh1, Iv }, 0 },
2527     { "subQ",   { Evh1, Iv }, 0 },
2528     { "xorQ",   { Evh1, Iv }, 0 },
2529     { "cmpQ",   { Ev, Iv }, 0 },
2530   },
2531   /* REG_83 */
2532   {
2533     { "addQ",   { Evh1, sIb }, 0 },
2534     { "orQ",    { Evh1, sIb }, 0 },
2535     { "adcQ",   { Evh1, sIb }, 0 },
2536     { "sbbQ",   { Evh1, sIb }, 0 },
2537     { "andQ",   { Evh1, sIb }, 0 },
2538     { "subQ",   { Evh1, sIb }, 0 },
2539     { "xorQ",   { Evh1, sIb }, 0 },
2540     { "cmpQ",   { Ev, sIb }, 0 },
2541   },
2542   /* REG_8F */
2543   {
2544     { "pop{P|}", { stackEv }, 0 },
2545     { XOP_8F_TABLE (XOP_09) },
2546     { Bad_Opcode },
2547     { Bad_Opcode },
2548     { Bad_Opcode },
2549     { XOP_8F_TABLE (XOP_09) },
2550   },
2551   /* REG_C0 */
2552   {
2553     { "rolA",   { Eb, Ib }, 0 },
2554     { "rorA",   { Eb, Ib }, 0 },
2555     { "rclA",   { Eb, Ib }, 0 },
2556     { "rcrA",   { Eb, Ib }, 0 },
2557     { "shlA",   { Eb, Ib }, 0 },
2558     { "shrA",   { Eb, Ib }, 0 },
2559     { "shlA",   { Eb, Ib }, 0 },
2560     { "sarA",   { Eb, Ib }, 0 },
2561   },
2562   /* REG_C1 */
2563   {
2564     { "rolQ",   { Ev, Ib }, 0 },
2565     { "rorQ",   { Ev, Ib }, 0 },
2566     { "rclQ",   { Ev, Ib }, 0 },
2567     { "rcrQ",   { Ev, Ib }, 0 },
2568     { "shlQ",   { Ev, Ib }, 0 },
2569     { "shrQ",   { Ev, Ib }, 0 },
2570     { "shlQ",   { Ev, Ib }, 0 },
2571     { "sarQ",   { Ev, Ib }, 0 },
2572   },
2573   /* REG_C6 */
2574   {
2575     { "movA",   { Ebh3, Ib }, 0 },
2576     { Bad_Opcode },
2577     { Bad_Opcode },
2578     { Bad_Opcode },
2579     { Bad_Opcode },
2580     { Bad_Opcode },
2581     { Bad_Opcode },
2582     { MOD_TABLE (MOD_C6_REG_7) },
2583   },
2584   /* REG_C7 */
2585   {
2586     { "movQ",   { Evh3, Iv }, 0 },
2587     { Bad_Opcode },
2588     { Bad_Opcode },
2589     { Bad_Opcode },
2590     { Bad_Opcode },
2591     { Bad_Opcode },
2592     { Bad_Opcode },
2593     { MOD_TABLE (MOD_C7_REG_7) },
2594   },
2595   /* REG_D0 */
2596   {
2597     { "rolA",   { Eb, I1 }, 0 },
2598     { "rorA",   { Eb, I1 }, 0 },
2599     { "rclA",   { Eb, I1 }, 0 },
2600     { "rcrA",   { Eb, I1 }, 0 },
2601     { "shlA",   { Eb, I1 }, 0 },
2602     { "shrA",   { Eb, I1 }, 0 },
2603     { "shlA",   { Eb, I1 }, 0 },
2604     { "sarA",   { Eb, I1 }, 0 },
2605   },
2606   /* REG_D1 */
2607   {
2608     { "rolQ",   { Ev, I1 }, 0 },
2609     { "rorQ",   { Ev, I1 }, 0 },
2610     { "rclQ",   { Ev, I1 }, 0 },
2611     { "rcrQ",   { Ev, I1 }, 0 },
2612     { "shlQ",   { Ev, I1 }, 0 },
2613     { "shrQ",   { Ev, I1 }, 0 },
2614     { "shlQ",   { Ev, I1 }, 0 },
2615     { "sarQ",   { Ev, I1 }, 0 },
2616   },
2617   /* REG_D2 */
2618   {
2619     { "rolA",   { Eb, CL }, 0 },
2620     { "rorA",   { Eb, CL }, 0 },
2621     { "rclA",   { Eb, CL }, 0 },
2622     { "rcrA",   { Eb, CL }, 0 },
2623     { "shlA",   { Eb, CL }, 0 },
2624     { "shrA",   { Eb, CL }, 0 },
2625     { "shlA",   { Eb, CL }, 0 },
2626     { "sarA",   { Eb, CL }, 0 },
2627   },
2628   /* REG_D3 */
2629   {
2630     { "rolQ",   { Ev, CL }, 0 },
2631     { "rorQ",   { Ev, CL }, 0 },
2632     { "rclQ",   { Ev, CL }, 0 },
2633     { "rcrQ",   { Ev, CL }, 0 },
2634     { "shlQ",   { Ev, CL }, 0 },
2635     { "shrQ",   { Ev, CL }, 0 },
2636     { "shlQ",   { Ev, CL }, 0 },
2637     { "sarQ",   { Ev, CL }, 0 },
2638   },
2639   /* REG_F6 */
2640   {
2641     { "testA",  { Eb, Ib }, 0 },
2642     { "testA",  { Eb, Ib }, 0 },
2643     { "notA",   { Ebh1 }, 0 },
2644     { "negA",   { Ebh1 }, 0 },
2645     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
2646     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
2647     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
2648     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
2649   },
2650   /* REG_F7 */
2651   {
2652     { "testQ",  { Ev, Iv }, 0 },
2653     { "testQ",  { Ev, Iv }, 0 },
2654     { "notQ",   { Evh1 }, 0 },
2655     { "negQ",   { Evh1 }, 0 },
2656     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
2657     { "imulQ",  { Ev }, 0 },
2658     { "divQ",   { Ev }, 0 },
2659     { "idivQ",  { Ev }, 0 },
2660   },
2661   /* REG_FE */
2662   {
2663     { "incA",   { Ebh1 }, 0 },
2664     { "decA",   { Ebh1 }, 0 },
2665   },
2666   /* REG_FF */
2667   {
2668     { "incQ",   { Evh1 }, 0 },
2669     { "decQ",   { Evh1 }, 0 },
2670     { "call{@|}", { NOTRACK, indirEv, BND }, 0 },
2671     { MOD_TABLE (MOD_FF_REG_3) },
2672     { "jmp{@|}", { NOTRACK, indirEv, BND }, 0 },
2673     { MOD_TABLE (MOD_FF_REG_5) },
2674     { "push{P|}", { stackEv }, 0 },
2675     { Bad_Opcode },
2676   },
2677   /* REG_0F00 */
2678   {
2679     { "sldtD",  { Sv }, 0 },
2680     { "strD",   { Sv }, 0 },
2681     { "lldt",   { Ew }, 0 },
2682     { "ltr",    { Ew }, 0 },
2683     { "verr",   { Ew }, 0 },
2684     { "verw",   { Ew }, 0 },
2685     { Bad_Opcode },
2686     { Bad_Opcode },
2687   },
2688   /* REG_0F01 */
2689   {
2690     { MOD_TABLE (MOD_0F01_REG_0) },
2691     { MOD_TABLE (MOD_0F01_REG_1) },
2692     { MOD_TABLE (MOD_0F01_REG_2) },
2693     { MOD_TABLE (MOD_0F01_REG_3) },
2694     { "smswD",  { Sv }, 0 },
2695     { MOD_TABLE (MOD_0F01_REG_5) },
2696     { "lmsw",   { Ew }, 0 },
2697     { MOD_TABLE (MOD_0F01_REG_7) },
2698   },
2699   /* REG_0F0D */
2700   {
2701     { "prefetch",       { Mb }, 0 },
2702     { "prefetchw",      { Mb }, 0 },
2703     { "prefetchwt1",    { Mb }, 0 },
2704     { "prefetch",       { Mb }, 0 },
2705     { "prefetch",       { Mb }, 0 },
2706     { "prefetch",       { Mb }, 0 },
2707     { "prefetch",       { Mb }, 0 },
2708     { "prefetch",       { Mb }, 0 },
2709   },
2710   /* REG_0F18 */
2711   {
2712     { MOD_TABLE (MOD_0F18_REG_0) },
2713     { MOD_TABLE (MOD_0F18_REG_1) },
2714     { MOD_TABLE (MOD_0F18_REG_2) },
2715     { MOD_TABLE (MOD_0F18_REG_3) },
2716     { "nopQ",           { Ev }, 0 },
2717     { "nopQ",           { Ev }, 0 },
2718     { "nopQ",           { Ev }, 0 },
2719     { "nopQ",           { Ev }, 0 },
2720   },
2721   /* REG_0F1C_P_0_MOD_0 */
2722   {
2723     { "cldemote",       { Mb }, 0 },
2724     { "nopQ",           { Ev }, 0 },
2725     { "nopQ",           { Ev }, 0 },
2726     { "nopQ",           { Ev }, 0 },
2727     { "nopQ",           { Ev }, 0 },
2728     { "nopQ",           { Ev }, 0 },
2729     { "nopQ",           { Ev }, 0 },
2730     { "nopQ",           { Ev }, 0 },
2731   },
2732   /* REG_0F1E_P_1_MOD_3 */
2733   {
2734     { "nopQ",           { Ev }, PREFIX_IGNORED },
2735     { "rdsspK",         { Edq }, 0 },
2736     { "nopQ",           { Ev }, PREFIX_IGNORED },
2737     { "nopQ",           { Ev }, PREFIX_IGNORED },
2738     { "nopQ",           { Ev }, PREFIX_IGNORED },
2739     { "nopQ",           { Ev }, PREFIX_IGNORED },
2740     { "nopQ",           { Ev }, PREFIX_IGNORED },
2741     { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) },
2742   },
2743   /* REG_0F38D8_PREFIX_1 */
2744   {
2745     { "aesencwide128kl",        { M }, 0 },
2746     { "aesdecwide128kl",        { M }, 0 },
2747     { "aesencwide256kl",        { M }, 0 },
2748     { "aesdecwide256kl",        { M }, 0 },
2749   },
2750   /* REG_0F3A0F_PREFIX_1_MOD_3 */
2751   {
2752     { RM_TABLE (RM_0F3A0F_P_1_MOD_3_REG_0) },
2753   },
2754   /* REG_0F71_MOD_0 */
2755   {
2756     { Bad_Opcode },
2757     { Bad_Opcode },
2758     { "psrlw",          { MS, Ib }, PREFIX_OPCODE },
2759     { Bad_Opcode },
2760     { "psraw",          { MS, Ib }, PREFIX_OPCODE },
2761     { Bad_Opcode },
2762     { "psllw",          { MS, Ib }, PREFIX_OPCODE },
2763   },
2764   /* REG_0F72_MOD_0 */
2765   {
2766     { Bad_Opcode },
2767     { Bad_Opcode },
2768     { "psrld",          { MS, Ib }, PREFIX_OPCODE },
2769     { Bad_Opcode },
2770     { "psrad",          { MS, Ib }, PREFIX_OPCODE },
2771     { Bad_Opcode },
2772     { "pslld",          { MS, Ib }, PREFIX_OPCODE },
2773   },
2774   /* REG_0F73_MOD_0 */
2775   {
2776     { Bad_Opcode },
2777     { Bad_Opcode },
2778     { "psrlq",          { MS, Ib }, PREFIX_OPCODE },
2779     { "psrldq",         { XS, Ib }, PREFIX_DATA },
2780     { Bad_Opcode },
2781     { Bad_Opcode },
2782     { "psllq",          { MS, Ib }, PREFIX_OPCODE },
2783     { "pslldq",         { XS, Ib }, PREFIX_DATA },
2784   },
2785   /* REG_0FA6 */
2786   {
2787     { "montmul",        { { OP_0f07, 0 } }, 0 },
2788     { "xsha1",          { { OP_0f07, 0 } }, 0 },
2789     { "xsha256",        { { OP_0f07, 0 } }, 0 },
2790   },
2791   /* REG_0FA7 */
2792   {
2793     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
2794     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
2795     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
2796     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
2797     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
2798     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
2799   },
2800   /* REG_0FAE */
2801   {
2802     { MOD_TABLE (MOD_0FAE_REG_0) },
2803     { MOD_TABLE (MOD_0FAE_REG_1) },
2804     { MOD_TABLE (MOD_0FAE_REG_2) },
2805     { MOD_TABLE (MOD_0FAE_REG_3) },
2806     { MOD_TABLE (MOD_0FAE_REG_4) },
2807     { MOD_TABLE (MOD_0FAE_REG_5) },
2808     { MOD_TABLE (MOD_0FAE_REG_6) },
2809     { MOD_TABLE (MOD_0FAE_REG_7) },
2810   },
2811   /* REG_0FBA */
2812   {
2813     { Bad_Opcode },
2814     { Bad_Opcode },
2815     { Bad_Opcode },
2816     { Bad_Opcode },
2817     { "btQ",    { Ev, Ib }, 0 },
2818     { "btsQ",   { Evh1, Ib }, 0 },
2819     { "btrQ",   { Evh1, Ib }, 0 },
2820     { "btcQ",   { Evh1, Ib }, 0 },
2821   },
2822   /* REG_0FC7 */
2823   {
2824     { Bad_Opcode },
2825     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
2826     { Bad_Opcode },
2827     { MOD_TABLE (MOD_0FC7_REG_3) },
2828     { MOD_TABLE (MOD_0FC7_REG_4) },
2829     { MOD_TABLE (MOD_0FC7_REG_5) },
2830     { MOD_TABLE (MOD_0FC7_REG_6) },
2831     { MOD_TABLE (MOD_0FC7_REG_7) },
2832   },
2833   /* REG_VEX_0F71_M_0 */
2834   {
2835     { Bad_Opcode },
2836     { Bad_Opcode },
2837     { "vpsrlw",         { Vex, XS, Ib }, PREFIX_DATA },
2838     { Bad_Opcode },
2839     { "vpsraw",         { Vex, XS, Ib }, PREFIX_DATA },
2840     { Bad_Opcode },
2841     { "vpsllw",         { Vex, XS, Ib }, PREFIX_DATA },
2842   },
2843   /* REG_VEX_0F72_M_0 */
2844   {
2845     { Bad_Opcode },
2846     { Bad_Opcode },
2847     { "vpsrld",         { Vex, XS, Ib }, PREFIX_DATA },
2848     { Bad_Opcode },
2849     { "vpsrad",         { Vex, XS, Ib }, PREFIX_DATA },
2850     { Bad_Opcode },
2851     { "vpslld",         { Vex, XS, Ib }, PREFIX_DATA },
2852   },
2853   /* REG_VEX_0F73_M_0 */
2854   {
2855     { Bad_Opcode },
2856     { Bad_Opcode },
2857     { "vpsrlq",         { Vex, XS, Ib }, PREFIX_DATA },
2858     { "vpsrldq",        { Vex, XS, Ib }, PREFIX_DATA },
2859     { Bad_Opcode },
2860     { Bad_Opcode },
2861     { "vpsllq",         { Vex, XS, Ib }, PREFIX_DATA },
2862     { "vpslldq",        { Vex, XS, Ib }, PREFIX_DATA },
2863   },
2864   /* REG_VEX_0FAE */
2865   {
2866     { Bad_Opcode },
2867     { Bad_Opcode },
2868     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
2869     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
2870   },
2871   /* REG_VEX_0F3849_X86_64_P_0_W_0_M_1 */
2872   {
2873     { RM_TABLE (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0) },
2874   },
2875   /* REG_VEX_0F38F3_L_0 */
2876   {
2877     { Bad_Opcode },
2878     { "blsrS",          { VexGdq, Edq }, PREFIX_OPCODE },
2879     { "blsmskS",        { VexGdq, Edq }, PREFIX_OPCODE },
2880     { "blsiS",          { VexGdq, Edq }, PREFIX_OPCODE },
2881   },
2882   /* REG_XOP_09_01_L_0 */
2883   {
2884     { Bad_Opcode },
2885     { "blcfill",        { VexGdq, Edq }, 0 },
2886     { "blsfill",        { VexGdq, Edq }, 0 },
2887     { "blcs",   { VexGdq, Edq }, 0 },
2888     { "tzmsk",  { VexGdq, Edq }, 0 },
2889     { "blcic",  { VexGdq, Edq }, 0 },
2890     { "blsic",  { VexGdq, Edq }, 0 },
2891     { "t1mskc", { VexGdq, Edq }, 0 },
2892   },
2893   /* REG_XOP_09_02_L_0 */
2894   {
2895     { Bad_Opcode },
2896     { "blcmsk", { VexGdq, Edq }, 0 },
2897     { Bad_Opcode },
2898     { Bad_Opcode },
2899     { Bad_Opcode },
2900     { Bad_Opcode },
2901     { "blci",   { VexGdq, Edq }, 0 },
2902   },
2903   /* REG_XOP_09_12_M_1_L_0 */
2904   {
2905     { "llwpcb", { Edq }, 0 },
2906     { "slwpcb", { Edq }, 0 },
2907   },
2908   /* REG_XOP_0A_12_L_0 */
2909   {
2910     { "lwpins", { VexGdq, Ed, Id }, 0 },
2911     { "lwpval", { VexGdq, Ed, Id }, 0 },
2912   },
2913
2914 #include "i386-dis-evex-reg.h"
2915 };
2916
2917 static const struct dis386 prefix_table[][4] = {
2918   /* PREFIX_90 */
2919   {
2920     { "xchgS", { { NOP_Fixup, 0 }, { NOP_Fixup, 1 } }, 0 },
2921     { "pause", { XX }, 0 },
2922     { "xchgS", { { NOP_Fixup, 0 }, { NOP_Fixup, 1 } }, 0 },
2923     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
2924   },
2925
2926   /* PREFIX_0F01_REG_1_RM_4 */
2927   {
2928     { Bad_Opcode },
2929     { Bad_Opcode },
2930     { "tdcall",         { Skip_MODRM }, 0 },
2931     { Bad_Opcode },
2932   },
2933
2934   /* PREFIX_0F01_REG_1_RM_5 */
2935   {
2936     { Bad_Opcode },
2937     { Bad_Opcode },
2938     { X86_64_TABLE (X86_64_0F01_REG_1_RM_5_PREFIX_2) },
2939     { Bad_Opcode },
2940   },
2941
2942   /* PREFIX_0F01_REG_1_RM_6 */
2943   {
2944     { Bad_Opcode },
2945     { Bad_Opcode },
2946     { X86_64_TABLE (X86_64_0F01_REG_1_RM_6_PREFIX_2) },
2947     { Bad_Opcode },
2948   },
2949
2950   /* PREFIX_0F01_REG_1_RM_7 */
2951   {
2952     { "encls",          { Skip_MODRM }, 0 },
2953     { Bad_Opcode },
2954     { X86_64_TABLE (X86_64_0F01_REG_1_RM_7_PREFIX_2) },
2955     { Bad_Opcode },
2956   },
2957
2958   /* PREFIX_0F01_REG_3_RM_1 */
2959   {
2960     { "vmmcall",        { Skip_MODRM }, 0 },
2961     { "vmgexit",        { Skip_MODRM }, 0 },
2962     { Bad_Opcode },
2963     { "vmgexit",        { Skip_MODRM }, 0 },
2964   },
2965
2966   /* PREFIX_0F01_REG_5_MOD_0 */
2967   {
2968     { Bad_Opcode },
2969     { "rstorssp",       { Mq }, PREFIX_OPCODE },
2970   },
2971
2972   /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
2973   {
2974     { "serialize",      { Skip_MODRM }, PREFIX_OPCODE },
2975     { "setssbsy",       { Skip_MODRM }, PREFIX_OPCODE },
2976     { Bad_Opcode },
2977     { "xsusldtrk",      { Skip_MODRM }, PREFIX_OPCODE },
2978   },
2979
2980   /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
2981   {
2982     { Bad_Opcode },
2983     { Bad_Opcode },
2984     { Bad_Opcode },
2985     { "xresldtrk",     { Skip_MODRM }, PREFIX_OPCODE },
2986   },
2987
2988   /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
2989   {
2990     { Bad_Opcode },
2991     { "saveprevssp",    { Skip_MODRM }, PREFIX_OPCODE },
2992   },
2993
2994   /* PREFIX_0F01_REG_5_MOD_3_RM_4 */
2995   {
2996     { Bad_Opcode },
2997     { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1) },
2998   },
2999
3000   /* PREFIX_0F01_REG_5_MOD_3_RM_5 */
3001   {
3002     { Bad_Opcode },
3003     { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1) },
3004   },
3005
3006   /* PREFIX_0F01_REG_5_MOD_3_RM_6 */
3007   {
3008     { "rdpkru", { Skip_MODRM }, 0 },
3009     { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1) },
3010   },
3011
3012   /* PREFIX_0F01_REG_5_MOD_3_RM_7 */
3013   {
3014     { "wrpkru", { Skip_MODRM }, 0 },
3015     { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1) },
3016   },
3017
3018   /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3019   {
3020     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
3021     { "mcommit",        { Skip_MODRM }, 0 },
3022   },
3023
3024   /* PREFIX_0F01_REG_7_MOD_3_RM_6 */
3025   {
3026     { "invlpgb",        { Skip_MODRM }, 0 },
3027     { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1) },
3028     { Bad_Opcode },
3029     { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3) },
3030   },
3031
3032   /* PREFIX_0F01_REG_7_MOD_3_RM_7 */
3033   {
3034     { "tlbsync",        { Skip_MODRM }, 0 },
3035     { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1) },
3036     { Bad_Opcode },
3037     { "pvalidate",      { Skip_MODRM }, 0 },
3038   },
3039
3040   /* PREFIX_0F09 */
3041   {
3042     { "wbinvd",   { XX }, 0 },
3043     { "wbnoinvd", { XX }, 0 },
3044   },
3045
3046   /* PREFIX_0F10 */
3047   {
3048     { "movups", { XM, EXx }, PREFIX_OPCODE },
3049     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3050     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3051     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3052   },
3053
3054   /* PREFIX_0F11 */
3055   {
3056     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3057     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3058     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3059     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3060   },
3061
3062   /* PREFIX_0F12 */
3063   {
3064     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3065     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3066     { MOD_TABLE (MOD_0F12_PREFIX_2) },
3067     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3068   },
3069
3070   /* PREFIX_0F16 */
3071   {
3072     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3073     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3074     { MOD_TABLE (MOD_0F16_PREFIX_2) },
3075   },
3076
3077   /* PREFIX_0F1A */
3078   {
3079     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3080     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3081     { "bndmov", { Gbnd, Ebnd }, 0 },
3082     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3083   },
3084
3085   /* PREFIX_0F1B */
3086   {
3087     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3088     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3089     { "bndmov", { EbndS, Gbnd }, 0 },
3090     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3091   },
3092
3093   /* PREFIX_0F1C */
3094   {
3095     { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3096     { "nopQ",   { Ev }, PREFIX_IGNORED },
3097     { "nopQ",   { Ev }, 0 },
3098     { "nopQ",   { Ev }, PREFIX_IGNORED },
3099   },
3100
3101   /* PREFIX_0F1E */
3102   {
3103     { "nopQ",   { Ev }, 0 },
3104     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3105     { "nopQ",   { Ev }, 0 },
3106     { NULL,     { XX }, PREFIX_IGNORED },
3107   },
3108
3109   /* PREFIX_0F2A */
3110   {
3111     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3112     { "cvtsi2ss{%LQ|}", { XM, Edq }, PREFIX_OPCODE },
3113     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3114     { "cvtsi2sd{%LQ|}", { XM, Edq }, 0 },
3115   },
3116
3117   /* PREFIX_0F2B */
3118   {
3119     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3120     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3121     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3122     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3123   },
3124
3125   /* PREFIX_0F2C */
3126   {
3127     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3128     { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
3129     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3130     { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3131   },
3132
3133   /* PREFIX_0F2D */
3134   {
3135     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3136     { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
3137     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3138     { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3139   },
3140
3141   /* PREFIX_0F2E */
3142   {
3143     { "ucomiss",{ XM, EXd }, 0 },
3144     { Bad_Opcode },
3145     { "ucomisd",{ XM, EXq }, 0 },
3146   },
3147
3148   /* PREFIX_0F2F */
3149   {
3150     { "comiss", { XM, EXd }, 0 },
3151     { Bad_Opcode },
3152     { "comisd", { XM, EXq }, 0 },
3153   },
3154
3155   /* PREFIX_0F51 */
3156   {
3157     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3158     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3159     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3160     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3161   },
3162
3163   /* PREFIX_0F52 */
3164   {
3165     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3166     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3167   },
3168
3169   /* PREFIX_0F53 */
3170   {
3171     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3172     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3173   },
3174
3175   /* PREFIX_0F58 */
3176   {
3177     { "addps", { XM, EXx }, PREFIX_OPCODE },
3178     { "addss", { XM, EXd }, PREFIX_OPCODE },
3179     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3180     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3181   },
3182
3183   /* PREFIX_0F59 */
3184   {
3185     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3186     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3187     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3188     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3189   },
3190
3191   /* PREFIX_0F5A */
3192   {
3193     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3194     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3195     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3196     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3197   },
3198
3199   /* PREFIX_0F5B */
3200   {
3201     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3202     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3203     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3204   },
3205
3206   /* PREFIX_0F5C */
3207   {
3208     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3209     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3210     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3211     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3212   },
3213
3214   /* PREFIX_0F5D */
3215   {
3216     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3217     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3218     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3219     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3220   },
3221
3222   /* PREFIX_0F5E */
3223   {
3224     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3225     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3226     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3227     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3228   },
3229
3230   /* PREFIX_0F5F */
3231   {
3232     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3233     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3234     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3235     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3236   },
3237
3238   /* PREFIX_0F60 */
3239   {
3240     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3241     { Bad_Opcode },
3242     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3243   },
3244
3245   /* PREFIX_0F61 */
3246   {
3247     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3248     { Bad_Opcode },
3249     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3250   },
3251
3252   /* PREFIX_0F62 */
3253   {
3254     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3255     { Bad_Opcode },
3256     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3257   },
3258
3259   /* PREFIX_0F6F */
3260   {
3261     { "movq",   { MX, EM }, PREFIX_OPCODE },
3262     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3263     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3264   },
3265
3266   /* PREFIX_0F70 */
3267   {
3268     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3269     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3270     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3271     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3272   },
3273
3274   /* PREFIX_0F78 */
3275   {
3276     {"vmread",  { Em, Gm }, 0 },
3277     { Bad_Opcode },
3278     {"extrq",   { XS, Ib, Ib }, 0 },
3279     {"insertq", { XM, XS, Ib, Ib }, 0 },
3280   },
3281
3282   /* PREFIX_0F79 */
3283   {
3284     {"vmwrite", { Gm, Em }, 0 },
3285     { Bad_Opcode },
3286     {"extrq",   { XM, XS }, 0 },
3287     {"insertq", { XM, XS }, 0 },
3288   },
3289
3290   /* PREFIX_0F7C */
3291   {
3292     { Bad_Opcode },
3293     { Bad_Opcode },
3294     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3295     { "haddps", { XM, EXx }, PREFIX_OPCODE },
3296   },
3297
3298   /* PREFIX_0F7D */
3299   {
3300     { Bad_Opcode },
3301     { Bad_Opcode },
3302     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3303     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3304   },
3305
3306   /* PREFIX_0F7E */
3307   {
3308     { "movK",   { Edq, MX }, PREFIX_OPCODE },
3309     { "movq",   { XM, EXq }, PREFIX_OPCODE },
3310     { "movK",   { Edq, XM }, PREFIX_OPCODE },
3311   },
3312
3313   /* PREFIX_0F7F */
3314   {
3315     { "movq",   { EMS, MX }, PREFIX_OPCODE },
3316     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3317     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3318   },
3319
3320   /* PREFIX_0FAE_REG_0_MOD_3 */
3321   {
3322     { Bad_Opcode },
3323     { "rdfsbase", { Ev }, 0 },
3324   },
3325
3326   /* PREFIX_0FAE_REG_1_MOD_3 */
3327   {
3328     { Bad_Opcode },
3329     { "rdgsbase", { Ev }, 0 },
3330   },
3331
3332   /* PREFIX_0FAE_REG_2_MOD_3 */
3333   {
3334     { Bad_Opcode },
3335     { "wrfsbase", { Ev }, 0 },
3336   },
3337
3338   /* PREFIX_0FAE_REG_3_MOD_3 */
3339   {
3340     { Bad_Opcode },
3341     { "wrgsbase", { Ev }, 0 },
3342   },
3343
3344   /* PREFIX_0FAE_REG_4_MOD_0 */
3345   {
3346     { "xsave",  { FXSAVE }, 0 },
3347     { "ptwrite{%LQ|}", { Edq }, 0 },
3348   },
3349
3350   /* PREFIX_0FAE_REG_4_MOD_3 */
3351   {
3352     { Bad_Opcode },
3353     { "ptwrite{%LQ|}", { Edq }, 0 },
3354   },
3355
3356   /* PREFIX_0FAE_REG_5_MOD_3 */
3357   {
3358     { "lfence",         { Skip_MODRM }, 0 },
3359     { "incsspK",        { Edq }, PREFIX_OPCODE },
3360   },
3361
3362   /* PREFIX_0FAE_REG_6_MOD_0 */
3363   {
3364     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE },
3365     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
3366     { "clwb",   { Mb }, PREFIX_OPCODE },
3367   },
3368
3369   /* PREFIX_0FAE_REG_6_MOD_3 */
3370   {
3371     { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) },
3372     { "umonitor",       { Eva }, PREFIX_OPCODE },
3373     { "tpause", { Edq }, PREFIX_OPCODE },
3374     { "umwait", { Edq }, PREFIX_OPCODE },
3375   },
3376
3377   /* PREFIX_0FAE_REG_7_MOD_0 */
3378   {
3379     { "clflush",        { Mb }, 0 },
3380     { Bad_Opcode },
3381     { "clflushopt",     { Mb }, 0 },
3382   },
3383
3384   /* PREFIX_0FB8 */
3385   {
3386     { Bad_Opcode },
3387     { "popcntS", { Gv, Ev }, 0 },
3388   },
3389
3390   /* PREFIX_0FBC */
3391   {
3392     { "bsfS",   { Gv, Ev }, 0 },
3393     { "tzcntS", { Gv, Ev }, 0 },
3394     { "bsfS",   { Gv, Ev }, 0 },
3395   },
3396
3397   /* PREFIX_0FBD */
3398   {
3399     { "bsrS",   { Gv, Ev }, 0 },
3400     { "lzcntS", { Gv, Ev }, 0 },
3401     { "bsrS",   { Gv, Ev }, 0 },
3402   },
3403
3404   /* PREFIX_0FC2 */
3405   {
3406     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
3407     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
3408     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
3409     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
3410   },
3411
3412   /* PREFIX_0FC7_REG_6_MOD_0 */
3413   {
3414     { "vmptrld",{ Mq }, 0 },
3415     { "vmxon",  { Mq }, 0 },
3416     { "vmclear",{ Mq }, 0 },
3417   },
3418
3419   /* PREFIX_0FC7_REG_6_MOD_3 */
3420   {
3421     { "rdrand", { Ev }, 0 },
3422     { X86_64_TABLE (X86_64_0FC7_REG_6_MOD_3_PREFIX_1) },
3423     { "rdrand", { Ev }, 0 }
3424   },
3425
3426   /* PREFIX_0FC7_REG_7_MOD_3 */
3427   {
3428     { "rdseed", { Ev }, 0 },
3429     { "rdpid",  { Em }, 0 },
3430     { "rdseed", { Ev }, 0 },
3431   },
3432
3433   /* PREFIX_0FD0 */
3434   {
3435     { Bad_Opcode },
3436     { Bad_Opcode },
3437     { "addsubpd", { XM, EXx }, 0 },
3438     { "addsubps", { XM, EXx }, 0 },
3439   },
3440
3441   /* PREFIX_0FD6 */
3442   {
3443     { Bad_Opcode },
3444     { "movq2dq",{ XM, MS }, 0 },
3445     { "movq",   { EXqS, XM }, 0 },
3446     { "movdq2q",{ MX, XS }, 0 },
3447   },
3448
3449   /* PREFIX_0FE6 */
3450   {
3451     { Bad_Opcode },
3452     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
3453     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
3454     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
3455   },
3456
3457   /* PREFIX_0FE7 */
3458   {
3459     { "movntq", { Mq, MX }, PREFIX_OPCODE },
3460     { Bad_Opcode },
3461     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
3462   },
3463
3464   /* PREFIX_0FF0 */
3465   {
3466     { Bad_Opcode },
3467     { Bad_Opcode },
3468     { Bad_Opcode },
3469     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
3470   },
3471
3472   /* PREFIX_0FF7 */
3473   {
3474     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
3475     { Bad_Opcode },
3476     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
3477   },
3478
3479   /* PREFIX_0F38D8 */
3480   {
3481     { Bad_Opcode },
3482     { REG_TABLE (REG_0F38D8_PREFIX_1) },
3483   },
3484
3485   /* PREFIX_0F38DC */
3486   {
3487     { Bad_Opcode },
3488     { MOD_TABLE (MOD_0F38DC_PREFIX_1) },
3489     { "aesenc", { XM, EXx }, 0 },
3490   },
3491
3492   /* PREFIX_0F38DD */
3493   {
3494     { Bad_Opcode },
3495     { MOD_TABLE (MOD_0F38DD_PREFIX_1) },
3496     { "aesenclast", { XM, EXx }, 0 },
3497   },
3498
3499   /* PREFIX_0F38DE */
3500   {
3501     { Bad_Opcode },
3502     { MOD_TABLE (MOD_0F38DE_PREFIX_1) },
3503     { "aesdec", { XM, EXx }, 0 },
3504   },
3505
3506   /* PREFIX_0F38DF */
3507   {
3508     { Bad_Opcode },
3509     { MOD_TABLE (MOD_0F38DF_PREFIX_1) },
3510     { "aesdeclast", { XM, EXx }, 0 },
3511   },
3512
3513   /* PREFIX_0F38F0 */
3514   {
3515     { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3516     { Bad_Opcode },
3517     { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3518     { "crc32A", { Gdq, Eb }, PREFIX_OPCODE },
3519   },
3520
3521   /* PREFIX_0F38F1 */
3522   {
3523     { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3524     { Bad_Opcode },
3525     { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3526     { "crc32Q", { Gdq, Ev }, PREFIX_OPCODE },
3527   },
3528
3529   /* PREFIX_0F38F6 */
3530   {
3531     { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
3532     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
3533     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
3534     { Bad_Opcode },
3535   },
3536
3537   /* PREFIX_0F38F8 */
3538   {
3539     { Bad_Opcode },
3540     { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
3541     { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
3542     { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
3543   },
3544   /* PREFIX_0F38FA */
3545   {
3546     { Bad_Opcode },
3547     { MOD_TABLE (MOD_0F38FA_PREFIX_1) },
3548   },
3549
3550   /* PREFIX_0F38FB */
3551   {
3552     { Bad_Opcode },
3553     { MOD_TABLE (MOD_0F38FB_PREFIX_1) },
3554   },
3555
3556   /* PREFIX_0F3A0F */
3557   {
3558     { Bad_Opcode },
3559     { MOD_TABLE (MOD_0F3A0F_PREFIX_1)},
3560   },
3561
3562   /* PREFIX_VEX_0F10 */
3563   {
3564     { "vmovupX",        { XM, EXEvexXNoBcst }, PREFIX_OPCODE },
3565     { "vmovs%XS",       { XMScalar, VexScalarR, EXd }, 0 },
3566     { "vmovupX",        { XM, EXEvexXNoBcst }, PREFIX_OPCODE },
3567     { "vmovs%XD",       { XMScalar, VexScalarR, EXq }, 0 },
3568   },
3569
3570   /* PREFIX_VEX_0F11 */
3571   {
3572     { "vmovupX",        { EXxS, XM }, PREFIX_OPCODE },
3573     { "vmovs%XS",       { EXdS, VexScalarR, XMScalar }, 0 },
3574     { "vmovupX",        { EXxS, XM }, PREFIX_OPCODE },
3575     { "vmovs%XD",       { EXqS, VexScalarR, XMScalar }, 0 },
3576   },
3577
3578   /* PREFIX_VEX_0F12 */
3579   {
3580     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
3581     { "vmov%XSldup",    { XM, EXEvexXNoBcst }, 0 },
3582     { MOD_TABLE (MOD_VEX_0F12_PREFIX_2) },
3583     { "vmov%XDdup",     { XM, EXymmq }, 0 },
3584   },
3585
3586   /* PREFIX_VEX_0F16 */
3587   {
3588     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
3589     { "vmov%XShdup",    { XM, EXEvexXNoBcst }, 0 },
3590     { MOD_TABLE (MOD_VEX_0F16_PREFIX_2) },
3591   },
3592
3593   /* PREFIX_VEX_0F2A */
3594   {
3595     { Bad_Opcode },
3596     { "vcvtsi2ss{%LQ|}",        { XMScalar, VexScalar, EXxEVexR, Edq }, 0 },
3597     { Bad_Opcode },
3598     { "vcvtsi2sd{%LQ|}",        { XMScalar, VexScalar, EXxEVexR64, Edq }, 0 },
3599   },
3600
3601   /* PREFIX_VEX_0F2C */
3602   {
3603     { Bad_Opcode },
3604     { "vcvttss2si",     { Gdq, EXd, EXxEVexS }, 0 },
3605     { Bad_Opcode },
3606     { "vcvttsd2si",     { Gdq, EXq, EXxEVexS }, 0 },
3607   },
3608
3609   /* PREFIX_VEX_0F2D */
3610   {
3611     { Bad_Opcode },
3612     { "vcvtss2si",      { Gdq, EXd, EXxEVexR }, 0 },
3613     { Bad_Opcode },
3614     { "vcvtsd2si",      { Gdq, EXq, EXxEVexR }, 0 },
3615   },
3616
3617   /* PREFIX_VEX_0F2E */
3618   {
3619     { "vucomisX",       { XMScalar, EXd, EXxEVexS }, PREFIX_OPCODE },
3620     { Bad_Opcode },
3621     { "vucomisX",       { XMScalar, EXq, EXxEVexS }, PREFIX_OPCODE },
3622   },
3623
3624   /* PREFIX_VEX_0F2F */
3625   {
3626     { "vcomisX",        { XMScalar, EXd, EXxEVexS }, PREFIX_OPCODE },
3627     { Bad_Opcode },
3628     { "vcomisX",        { XMScalar, EXq, EXxEVexS }, PREFIX_OPCODE },
3629   },
3630
3631   /* PREFIX_VEX_0F41_L_1_M_1_W_0 */
3632   {
3633     { "kandw",          { MaskG, MaskVex, MaskE }, 0 },
3634     { Bad_Opcode },
3635     { "kandb",          { MaskG, MaskVex, MaskE }, 0 },
3636   },
3637
3638   /* PREFIX_VEX_0F41_L_1_M_1_W_1 */
3639   {
3640     { "kandq",          { MaskG, MaskVex, MaskE }, 0 },
3641     { Bad_Opcode },
3642     { "kandd",          { MaskG, MaskVex, MaskE }, 0 },
3643   },
3644
3645   /* PREFIX_VEX_0F42_L_1_M_1_W_0 */
3646   {
3647     { "kandnw",         { MaskG, MaskVex, MaskE }, 0 },
3648     { Bad_Opcode },
3649     { "kandnb",         { MaskG, MaskVex, MaskE }, 0 },
3650   },
3651
3652   /* PREFIX_VEX_0F42_L_1_M_1_W_1 */
3653   {
3654     { "kandnq",         { MaskG, MaskVex, MaskE }, 0 },
3655     { Bad_Opcode },
3656     { "kandnd",         { MaskG, MaskVex, MaskE }, 0 },
3657   },
3658
3659   /* PREFIX_VEX_0F44_L_0_M_1_W_0 */
3660   {
3661     { "knotw",          { MaskG, MaskE }, 0 },
3662     { Bad_Opcode },
3663     { "knotb",          { MaskG, MaskE }, 0 },
3664   },
3665
3666   /* PREFIX_VEX_0F44_L_0_M_1_W_1 */
3667   {
3668     { "knotq",          { MaskG, MaskE }, 0 },
3669     { Bad_Opcode },
3670     { "knotd",          { MaskG, MaskE }, 0 },
3671   },
3672
3673   /* PREFIX_VEX_0F45_L_1_M_1_W_0 */
3674   {
3675     { "korw",       { MaskG, MaskVex, MaskE }, 0 },
3676     { Bad_Opcode },
3677     { "korb",       { MaskG, MaskVex, MaskE }, 0 },
3678   },
3679
3680   /* PREFIX_VEX_0F45_L_1_M_1_W_1 */
3681   {
3682     { "korq",       { MaskG, MaskVex, MaskE }, 0 },
3683     { Bad_Opcode },
3684     { "kord",       { MaskG, MaskVex, MaskE }, 0 },
3685   },
3686
3687   /* PREFIX_VEX_0F46_L_1_M_1_W_0 */
3688   {
3689     { "kxnorw",     { MaskG, MaskVex, MaskE }, 0 },
3690     { Bad_Opcode },
3691     { "kxnorb",     { MaskG, MaskVex, MaskE }, 0 },
3692   },
3693
3694   /* PREFIX_VEX_0F46_L_1_M_1_W_1 */
3695   {
3696     { "kxnorq",     { MaskG, MaskVex, MaskE }, 0 },
3697     { Bad_Opcode },
3698     { "kxnord",     { MaskG, MaskVex, MaskE }, 0 },
3699   },
3700
3701   /* PREFIX_VEX_0F47_L_1_M_1_W_0 */
3702   {
3703     { "kxorw",      { MaskG, MaskVex, MaskE }, 0 },
3704     { Bad_Opcode },
3705     { "kxorb",      { MaskG, MaskVex, MaskE }, 0 },
3706   },
3707
3708   /* PREFIX_VEX_0F47_L_1_M_1_W_1 */
3709   {
3710     { "kxorq",      { MaskG, MaskVex, MaskE }, 0 },
3711     { Bad_Opcode },
3712     { "kxord",      { MaskG, MaskVex, MaskE }, 0 },
3713   },
3714
3715   /* PREFIX_VEX_0F4A_L_1_M_1_W_0 */
3716   {
3717     { "kaddw",          { MaskG, MaskVex, MaskE }, 0 },
3718     { Bad_Opcode },
3719     { "kaddb",          { MaskG, MaskVex, MaskE }, 0 },
3720   },
3721
3722   /* PREFIX_VEX_0F4A_L_1_M_1_W_1 */
3723   {
3724     { "kaddq",          { MaskG, MaskVex, MaskE }, 0 },
3725     { Bad_Opcode },
3726     { "kaddd",          { MaskG, MaskVex, MaskE }, 0 },
3727   },
3728
3729   /* PREFIX_VEX_0F4B_L_1_M_1_W_0 */
3730   {
3731     { "kunpckwd",   { MaskG, MaskVex, MaskE }, 0 },
3732     { Bad_Opcode },
3733     { "kunpckbw",   { MaskG, MaskVex, MaskE }, 0 },
3734   },
3735
3736   /* PREFIX_VEX_0F4B_L_1_M_1_W_1 */
3737   {
3738     { "kunpckdq",   { MaskG, MaskVex, MaskE }, 0 },
3739   },
3740
3741   /* PREFIX_VEX_0F51 */
3742   {
3743     { "vsqrtpX",        { XM, EXx, EXxEVexR }, PREFIX_OPCODE },
3744     { "vsqrts%XS",      { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3745     { "vsqrtpX",        { XM, EXx, EXxEVexR }, PREFIX_OPCODE },
3746     { "vsqrts%XD",      { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3747   },
3748
3749   /* PREFIX_VEX_0F52 */
3750   {
3751     { "vrsqrtps",       { XM, EXx }, 0 },
3752     { "vrsqrtss",       { XMScalar, VexScalar, EXd }, 0 },
3753   },
3754
3755   /* PREFIX_VEX_0F53 */
3756   {
3757     { "vrcpps",         { XM, EXx }, 0 },
3758     { "vrcpss",         { XMScalar, VexScalar, EXd }, 0 },
3759   },
3760
3761   /* PREFIX_VEX_0F58 */
3762   {
3763     { "vaddpX",         { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
3764     { "vadds%XS",       { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3765     { "vaddpX",         { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
3766     { "vadds%XD",       { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3767   },
3768
3769   /* PREFIX_VEX_0F59 */
3770   {
3771     { "vmulpX",         { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
3772     { "vmuls%XS",       { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3773     { "vmulpX",         { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
3774     { "vmuls%XD",       { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3775   },
3776
3777   /* PREFIX_VEX_0F5A */
3778   {
3779     { "vcvtp%XS2pd", { XM, EXEvexHalfBcstXmmq, EXxEVexS }, 0 },
3780     { "vcvts%XS2sd", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
3781     { "vcvtp%XD2ps%XY", { XMxmmq, EXx, EXxEVexR }, 0 },
3782     { "vcvts%XD2ss", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3783   },
3784
3785   /* PREFIX_VEX_0F5B */
3786   {
3787     { "vcvtdq2ps",      { XM, EXx }, 0 },
3788     { "vcvttps2dq",     { XM, EXx }, 0 },
3789     { "vcvtps2dq",      { XM, EXx }, 0 },
3790   },
3791
3792   /* PREFIX_VEX_0F5C */
3793   {
3794     { "vsubpX",         { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
3795     { "vsubs%XS",       { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3796     { "vsubpX",         { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
3797     { "vsubs%XD",       { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3798   },
3799
3800   /* PREFIX_VEX_0F5D */
3801   {
3802     { "vminpX",         { XM, Vex, EXx, EXxEVexS }, PREFIX_OPCODE },
3803     { "vmins%XS",       { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
3804     { "vminpX",         { XM, Vex, EXx, EXxEVexS }, PREFIX_OPCODE },
3805     { "vmins%XD",       { XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
3806   },
3807
3808   /* PREFIX_VEX_0F5E */
3809   {
3810     { "vdivpX",         { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
3811     { "vdivs%XS",       { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3812     { "vdivpX",         { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
3813     { "vdivs%XD",       { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3814   },
3815
3816   /* PREFIX_VEX_0F5F */
3817   {
3818     { "vmaxpX",         { XM, Vex, EXx, EXxEVexS }, PREFIX_OPCODE },
3819     { "vmaxs%XS",       { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
3820     { "vmaxpX",         { XM, Vex, EXx, EXxEVexS }, PREFIX_OPCODE },
3821     { "vmaxs%XD",       { XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
3822   },
3823
3824   /* PREFIX_VEX_0F6F */
3825   {
3826     { Bad_Opcode },
3827     { "vmovdqu",        { XM, EXx }, 0 },
3828     { "vmovdqa",        { XM, EXx }, 0 },
3829   },
3830
3831   /* PREFIX_VEX_0F70 */
3832   {
3833     { Bad_Opcode },
3834     { "vpshufhw",       { XM, EXx, Ib }, 0 },
3835     { "vpshufd",        { XM, EXx, Ib }, 0 },
3836     { "vpshuflw",       { XM, EXx, Ib }, 0 },
3837   },
3838
3839   /* PREFIX_VEX_0F7C */
3840   {
3841     { Bad_Opcode },
3842     { Bad_Opcode },
3843     { "vhaddpd",        { XM, Vex, EXx }, 0 },
3844     { "vhaddps",        { XM, Vex, EXx }, 0 },
3845   },
3846
3847   /* PREFIX_VEX_0F7D */
3848   {
3849     { Bad_Opcode },
3850     { Bad_Opcode },
3851     { "vhsubpd",        { XM, Vex, EXx }, 0 },
3852     { "vhsubps",        { XM, Vex, EXx }, 0 },
3853   },
3854
3855   /* PREFIX_VEX_0F7E */
3856   {
3857     { Bad_Opcode },
3858     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
3859     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
3860   },
3861
3862   /* PREFIX_VEX_0F7F */
3863   {
3864     { Bad_Opcode },
3865     { "vmovdqu",        { EXxS, XM }, 0 },
3866     { "vmovdqa",        { EXxS, XM }, 0 },
3867   },
3868
3869   /* PREFIX_VEX_0F90_L_0_W_0 */
3870   {
3871     { "kmovw",          { MaskG, MaskE }, 0 },
3872     { Bad_Opcode },
3873     { "kmovb",          { MaskG, MaskBDE }, 0 },
3874   },
3875
3876   /* PREFIX_VEX_0F90_L_0_W_1 */
3877   {
3878     { "kmovq",          { MaskG, MaskE }, 0 },
3879     { Bad_Opcode },
3880     { "kmovd",          { MaskG, MaskBDE }, 0 },
3881   },
3882
3883   /* PREFIX_VEX_0F91_L_0_M_0_W_0 */
3884   {
3885     { "kmovw",          { Ew, MaskG }, 0 },
3886     { Bad_Opcode },
3887     { "kmovb",          { Eb, MaskG }, 0 },
3888   },
3889
3890   /* PREFIX_VEX_0F91_L_0_M_0_W_1 */
3891   {
3892     { "kmovq",          { Eq, MaskG }, 0 },
3893     { Bad_Opcode },
3894     { "kmovd",          { Ed, MaskG }, 0 },
3895   },
3896
3897   /* PREFIX_VEX_0F92_L_0_M_1_W_0 */
3898   {
3899     { "kmovw",          { MaskG, Edq }, 0 },
3900     { Bad_Opcode },
3901     { "kmovb",          { MaskG, Edq }, 0 },
3902     { "kmovd",          { MaskG, Edq }, 0 },
3903   },
3904
3905   /* PREFIX_VEX_0F92_L_0_M_1_W_1 */
3906   {
3907     { Bad_Opcode },
3908     { Bad_Opcode },
3909     { Bad_Opcode },
3910     { "kmovK",          { MaskG, Edq }, 0 },
3911   },
3912
3913   /* PREFIX_VEX_0F93_L_0_M_1_W_0 */
3914   {
3915     { "kmovw",          { Gdq, MaskE }, 0 },
3916     { Bad_Opcode },
3917     { "kmovb",          { Gdq, MaskE }, 0 },
3918     { "kmovd",          { Gdq, MaskE }, 0 },
3919   },
3920
3921   /* PREFIX_VEX_0F93_L_0_M_1_W_1 */
3922   {
3923     { Bad_Opcode },
3924     { Bad_Opcode },
3925     { Bad_Opcode },
3926     { "kmovK",          { Gdq, MaskE }, 0 },
3927   },
3928
3929   /* PREFIX_VEX_0F98_L_0_M_1_W_0 */
3930   {
3931     { "kortestw", { MaskG, MaskE }, 0 },
3932     { Bad_Opcode },
3933     { "kortestb", { MaskG, MaskE }, 0 },
3934   },
3935
3936   /* PREFIX_VEX_0F98_L_0_M_1_W_1 */
3937   {
3938     { "kortestq", { MaskG, MaskE }, 0 },
3939     { Bad_Opcode },
3940     { "kortestd", { MaskG, MaskE }, 0 },
3941   },
3942
3943   /* PREFIX_VEX_0F99_L_0_M_1_W_0 */
3944   {
3945     { "ktestw", { MaskG, MaskE }, 0 },
3946     { Bad_Opcode },
3947     { "ktestb", { MaskG, MaskE }, 0 },
3948   },
3949
3950   /* PREFIX_VEX_0F99_L_0_M_1_W_1 */
3951   {
3952     { "ktestq", { MaskG, MaskE }, 0 },
3953     { Bad_Opcode },
3954     { "ktestd", { MaskG, MaskE }, 0 },
3955   },
3956
3957   /* PREFIX_VEX_0FC2 */
3958   {
3959     { "vcmpps",         { XM, Vex, EXx, CMP }, 0 },
3960     { "vcmpss",         { XMScalar, VexScalar, EXd, CMP }, 0 },
3961     { "vcmppd",         { XM, Vex, EXx, CMP }, 0 },
3962     { "vcmpsd",         { XMScalar, VexScalar, EXq, CMP }, 0 },
3963   },
3964
3965   /* PREFIX_VEX_0FD0 */
3966   {
3967     { Bad_Opcode },
3968     { Bad_Opcode },
3969     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
3970     { "vaddsubps",      { XM, Vex, EXx }, 0 },
3971   },
3972
3973   /* PREFIX_VEX_0FE6 */
3974   {
3975     { Bad_Opcode },
3976     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
3977     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
3978     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
3979   },
3980
3981   /* PREFIX_VEX_0FF0 */
3982   {
3983     { Bad_Opcode },
3984     { Bad_Opcode },
3985     { Bad_Opcode },
3986     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
3987   },
3988
3989   /* PREFIX_VEX_0F3849_X86_64 */
3990   {
3991     { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_0) },
3992     { Bad_Opcode },
3993     { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_2) },
3994     { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_3) },
3995   },
3996
3997   /* PREFIX_VEX_0F384B_X86_64 */
3998   {
3999     { Bad_Opcode },
4000     { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_1) },
4001     { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_2) },
4002     { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_3) },
4003   },
4004
4005   /* PREFIX_VEX_0F385C_X86_64 */
4006   {
4007     { Bad_Opcode },
4008     { VEX_W_TABLE (VEX_W_0F385C_X86_64_P_1) },
4009     { Bad_Opcode },
4010   },
4011
4012   /* PREFIX_VEX_0F385E_X86_64 */
4013   {
4014     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_0) },
4015     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_1) },
4016     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_2) },
4017     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_3) },
4018   },
4019
4020   /* PREFIX_VEX_0F38F5_L_0 */
4021   {
4022     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
4023     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
4024     { Bad_Opcode },
4025     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
4026   },
4027
4028   /* PREFIX_VEX_0F38F6_L_0 */
4029   {
4030     { Bad_Opcode },
4031     { Bad_Opcode },
4032     { Bad_Opcode },
4033     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
4034   },
4035
4036   /* PREFIX_VEX_0F38F7_L_0 */
4037   {
4038     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
4039     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
4040     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
4041     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
4042   },
4043
4044   /* PREFIX_VEX_0F3AF0_L_0 */
4045   {
4046     { Bad_Opcode },
4047     { Bad_Opcode },
4048     { Bad_Opcode },
4049     { "rorxS",          { Gdq, Edq, Ib }, 0 },
4050   },
4051
4052 #include "i386-dis-evex-prefix.h"
4053 };
4054
4055 static const struct dis386 x86_64_table[][2] = {
4056   /* X86_64_06 */
4057   {
4058     { "pushP", { es }, 0 },
4059   },
4060
4061   /* X86_64_07 */
4062   {
4063     { "popP", { es }, 0 },
4064   },
4065
4066   /* X86_64_0E */
4067   {
4068     { "pushP", { cs }, 0 },
4069   },
4070
4071   /* X86_64_16 */
4072   {
4073     { "pushP", { ss }, 0 },
4074   },
4075
4076   /* X86_64_17 */
4077   {
4078     { "popP", { ss }, 0 },
4079   },
4080
4081   /* X86_64_1E */
4082   {
4083     { "pushP", { ds }, 0 },
4084   },
4085
4086   /* X86_64_1F */
4087   {
4088     { "popP", { ds }, 0 },
4089   },
4090
4091   /* X86_64_27 */
4092   {
4093     { "daa", { XX }, 0 },
4094   },
4095
4096   /* X86_64_2F */
4097   {
4098     { "das", { XX }, 0 },
4099   },
4100
4101   /* X86_64_37 */
4102   {
4103     { "aaa", { XX }, 0 },
4104   },
4105
4106   /* X86_64_3F */
4107   {
4108     { "aas", { XX }, 0 },
4109   },
4110
4111   /* X86_64_60 */
4112   {
4113     { "pushaP", { XX }, 0 },
4114   },
4115
4116   /* X86_64_61 */
4117   {
4118     { "popaP", { XX }, 0 },
4119   },
4120
4121   /* X86_64_62 */
4122   {
4123     { MOD_TABLE (MOD_62_32BIT) },
4124     { EVEX_TABLE (EVEX_0F) },
4125   },
4126
4127   /* X86_64_63 */
4128   {
4129     { "arpl", { Ew, Gw }, 0 },
4130     { "movs", { Gv, { MOVSXD_Fixup, movsxd_mode } }, 0 },
4131   },
4132
4133   /* X86_64_6D */
4134   {
4135     { "ins{R|}", { Yzr, indirDX }, 0 },
4136     { "ins{G|}", { Yzr, indirDX }, 0 },
4137   },
4138
4139   /* X86_64_6F */
4140   {
4141     { "outs{R|}", { indirDXr, Xz }, 0 },
4142     { "outs{G|}", { indirDXr, Xz }, 0 },
4143   },
4144
4145   /* X86_64_82 */
4146   {
4147     /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
4148     { REG_TABLE (REG_80) },
4149   },
4150
4151   /* X86_64_9A */
4152   {
4153     { "{l|}call{P|}", { Ap }, 0 },
4154   },
4155
4156   /* X86_64_C2 */
4157   {
4158     { "retP",           { Iw, BND }, 0 },
4159     { "ret@",           { Iw, BND }, 0 },
4160   },
4161
4162   /* X86_64_C3 */
4163   {
4164     { "retP",           { BND }, 0 },
4165     { "ret@",           { BND }, 0 },
4166   },
4167
4168   /* X86_64_C4 */
4169   {
4170     { MOD_TABLE (MOD_C4_32BIT) },
4171     { VEX_C4_TABLE (VEX_0F) },
4172   },
4173
4174   /* X86_64_C5 */
4175   {
4176     { MOD_TABLE (MOD_C5_32BIT) },
4177     { VEX_C5_TABLE (VEX_0F) },
4178   },
4179
4180   /* X86_64_CE */
4181   {
4182     { "into", { XX }, 0 },
4183   },
4184
4185   /* X86_64_D4 */
4186   {
4187     { "aam", { Ib }, 0 },
4188   },
4189
4190   /* X86_64_D5 */
4191   {
4192     { "aad", { Ib }, 0 },
4193   },
4194
4195   /* X86_64_E8 */
4196   {
4197     { "callP",          { Jv, BND }, 0 },
4198     { "call@",          { Jv, BND }, 0 }
4199   },
4200
4201   /* X86_64_E9 */
4202   {
4203     { "jmpP",           { Jv, BND }, 0 },
4204     { "jmp@",           { Jv, BND }, 0 }
4205   },
4206
4207   /* X86_64_EA */
4208   {
4209     { "{l|}jmp{P|}", { Ap }, 0 },
4210   },
4211
4212   /* X86_64_0F01_REG_0 */
4213   {
4214     { "sgdt{Q|Q}", { M }, 0 },
4215     { "sgdt", { M }, 0 },
4216   },
4217
4218   /* X86_64_0F01_REG_1 */
4219   {
4220     { "sidt{Q|Q}", { M }, 0 },
4221     { "sidt", { M }, 0 },
4222   },
4223
4224   /* X86_64_0F01_REG_1_RM_5_PREFIX_2 */
4225   {
4226     { Bad_Opcode },
4227     { "seamret",        { Skip_MODRM }, 0 },
4228   },
4229
4230   /* X86_64_0F01_REG_1_RM_6_PREFIX_2 */
4231   {
4232     { Bad_Opcode },
4233     { "seamops",        { Skip_MODRM }, 0 },
4234   },
4235
4236   /* X86_64_0F01_REG_1_RM_7_PREFIX_2 */
4237   {
4238     { Bad_Opcode },
4239     { "seamcall",       { Skip_MODRM }, 0 },
4240   },
4241
4242   /* X86_64_0F01_REG_2 */
4243   {
4244     { "lgdt{Q|Q}", { M }, 0 },
4245     { "lgdt", { M }, 0 },
4246   },
4247
4248   /* X86_64_0F01_REG_3 */
4249   {
4250     { "lidt{Q|Q}", { M }, 0 },
4251     { "lidt", { M }, 0 },
4252   },
4253
4254   /* X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1 */
4255   {
4256     { Bad_Opcode },
4257     { "uiret",  { Skip_MODRM }, 0 },
4258   },
4259
4260   /* X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1 */
4261   {
4262     { Bad_Opcode },
4263     { "testui", { Skip_MODRM }, 0 },
4264   },
4265
4266   /* X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1 */
4267   {
4268     { Bad_Opcode },
4269     { "clui",   { Skip_MODRM }, 0 },
4270   },
4271
4272   /* X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1 */
4273   {
4274     { Bad_Opcode },
4275     { "stui",   { Skip_MODRM }, 0 },
4276   },
4277
4278   /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1 */
4279   {
4280     { Bad_Opcode },
4281     { "rmpadjust",      { Skip_MODRM }, 0 },
4282   },
4283
4284   /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3 */
4285   {
4286     { Bad_Opcode },
4287     { "rmpupdate",      { Skip_MODRM }, 0 },
4288   },
4289
4290   /* X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1 */
4291   {
4292     { Bad_Opcode },
4293     { "psmash", { Skip_MODRM }, 0 },
4294   },
4295
4296   {
4297     /* X86_64_0F24 */
4298     { "movZ",           { Em, Td }, 0 },
4299   },
4300
4301   {
4302     /* X86_64_0F26 */
4303     { "movZ",           { Td, Em }, 0 },
4304   },
4305
4306   /* X86_64_0FC7_REG_6_MOD_3_PREFIX_1 */
4307   {
4308     { Bad_Opcode },
4309     { "senduipi",       { Eq }, 0 },
4310   },
4311
4312   /* X86_64_VEX_0F3849 */
4313   {
4314     { Bad_Opcode },
4315     { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64) },
4316   },
4317
4318   /* X86_64_VEX_0F384B */
4319   {
4320     { Bad_Opcode },
4321     { PREFIX_TABLE (PREFIX_VEX_0F384B_X86_64) },
4322   },
4323
4324   /* X86_64_VEX_0F385C */
4325   {
4326     { Bad_Opcode },
4327     { PREFIX_TABLE (PREFIX_VEX_0F385C_X86_64) },
4328   },
4329
4330   /* X86_64_VEX_0F385E */
4331   {
4332     { Bad_Opcode },
4333     { PREFIX_TABLE (PREFIX_VEX_0F385E_X86_64) },
4334   },
4335 };
4336
4337 static const struct dis386 three_byte_table[][256] = {
4338
4339   /* THREE_BYTE_0F38 */
4340   {
4341     /* 00 */
4342     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
4343     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
4344     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
4345     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
4346     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
4347     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
4348     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
4349     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
4350     /* 08 */
4351     { "psignb",         { MX, EM }, PREFIX_OPCODE },
4352     { "psignw",         { MX, EM }, PREFIX_OPCODE },
4353     { "psignd",         { MX, EM }, PREFIX_OPCODE },
4354     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
4355     { Bad_Opcode },
4356     { Bad_Opcode },
4357     { Bad_Opcode },
4358     { Bad_Opcode },
4359     /* 10 */
4360     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_DATA },
4361     { Bad_Opcode },
4362     { Bad_Opcode },
4363     { Bad_Opcode },
4364     { "blendvps", { XM, EXx, XMM0 }, PREFIX_DATA },
4365     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_DATA },
4366     { Bad_Opcode },
4367     { "ptest",  { XM, EXx }, PREFIX_DATA },
4368     /* 18 */
4369     { Bad_Opcode },
4370     { Bad_Opcode },
4371     { Bad_Opcode },
4372     { Bad_Opcode },
4373     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
4374     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
4375     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
4376     { Bad_Opcode },
4377     /* 20 */
4378     { "pmovsxbw", { XM, EXq }, PREFIX_DATA },
4379     { "pmovsxbd", { XM, EXd }, PREFIX_DATA },
4380     { "pmovsxbq", { XM, EXw }, PREFIX_DATA },
4381     { "pmovsxwd", { XM, EXq }, PREFIX_DATA },
4382     { "pmovsxwq", { XM, EXd }, PREFIX_DATA },
4383     { "pmovsxdq", { XM, EXq }, PREFIX_DATA },
4384     { Bad_Opcode },
4385     { Bad_Opcode },
4386     /* 28 */
4387     { "pmuldq", { XM, EXx }, PREFIX_DATA },
4388     { "pcmpeqq", { XM, EXx }, PREFIX_DATA },
4389     { MOD_TABLE (MOD_0F382A) },
4390     { "packusdw", { XM, EXx }, PREFIX_DATA },
4391     { Bad_Opcode },
4392     { Bad_Opcode },
4393     { Bad_Opcode },
4394     { Bad_Opcode },
4395     /* 30 */
4396     { "pmovzxbw", { XM, EXq }, PREFIX_DATA },
4397     { "pmovzxbd", { XM, EXd }, PREFIX_DATA },
4398     { "pmovzxbq", { XM, EXw }, PREFIX_DATA },
4399     { "pmovzxwd", { XM, EXq }, PREFIX_DATA },
4400     { "pmovzxwq", { XM, EXd }, PREFIX_DATA },
4401     { "pmovzxdq", { XM, EXq }, PREFIX_DATA },
4402     { Bad_Opcode },
4403     { "pcmpgtq", { XM, EXx }, PREFIX_DATA },
4404     /* 38 */
4405     { "pminsb", { XM, EXx }, PREFIX_DATA },
4406     { "pminsd", { XM, EXx }, PREFIX_DATA },
4407     { "pminuw", { XM, EXx }, PREFIX_DATA },
4408     { "pminud", { XM, EXx }, PREFIX_DATA },
4409     { "pmaxsb", { XM, EXx }, PREFIX_DATA },
4410     { "pmaxsd", { XM, EXx }, PREFIX_DATA },
4411     { "pmaxuw", { XM, EXx }, PREFIX_DATA },
4412     { "pmaxud", { XM, EXx }, PREFIX_DATA },
4413     /* 40 */
4414     { "pmulld", { XM, EXx }, PREFIX_DATA },
4415     { "phminposuw", { XM, EXx }, PREFIX_DATA },
4416     { Bad_Opcode },
4417     { Bad_Opcode },
4418     { Bad_Opcode },
4419     { Bad_Opcode },
4420     { Bad_Opcode },
4421     { Bad_Opcode },
4422     /* 48 */
4423     { Bad_Opcode },
4424     { Bad_Opcode },
4425     { Bad_Opcode },
4426     { Bad_Opcode },
4427     { Bad_Opcode },
4428     { Bad_Opcode },
4429     { Bad_Opcode },
4430     { Bad_Opcode },
4431     /* 50 */
4432     { Bad_Opcode },
4433     { Bad_Opcode },
4434     { Bad_Opcode },
4435     { Bad_Opcode },
4436     { Bad_Opcode },
4437     { Bad_Opcode },
4438     { Bad_Opcode },
4439     { Bad_Opcode },
4440     /* 58 */
4441     { Bad_Opcode },
4442     { Bad_Opcode },
4443     { Bad_Opcode },
4444     { Bad_Opcode },
4445     { Bad_Opcode },
4446     { Bad_Opcode },
4447     { Bad_Opcode },
4448     { Bad_Opcode },
4449     /* 60 */
4450     { Bad_Opcode },
4451     { Bad_Opcode },
4452     { Bad_Opcode },
4453     { Bad_Opcode },
4454     { Bad_Opcode },
4455     { Bad_Opcode },
4456     { Bad_Opcode },
4457     { Bad_Opcode },
4458     /* 68 */
4459     { Bad_Opcode },
4460     { Bad_Opcode },
4461     { Bad_Opcode },
4462     { Bad_Opcode },
4463     { Bad_Opcode },
4464     { Bad_Opcode },
4465     { Bad_Opcode },
4466     { Bad_Opcode },
4467     /* 70 */
4468     { Bad_Opcode },
4469     { Bad_Opcode },
4470     { Bad_Opcode },
4471     { Bad_Opcode },
4472     { Bad_Opcode },
4473     { Bad_Opcode },
4474     { Bad_Opcode },
4475     { Bad_Opcode },
4476     /* 78 */
4477     { Bad_Opcode },
4478     { Bad_Opcode },
4479     { Bad_Opcode },
4480     { Bad_Opcode },
4481     { Bad_Opcode },
4482     { Bad_Opcode },
4483     { Bad_Opcode },
4484     { Bad_Opcode },
4485     /* 80 */
4486     { "invept", { Gm, Mo }, PREFIX_DATA },
4487     { "invvpid", { Gm, Mo }, PREFIX_DATA },
4488     { "invpcid", { Gm, M }, PREFIX_DATA },
4489     { Bad_Opcode },
4490     { Bad_Opcode },
4491     { Bad_Opcode },
4492     { Bad_Opcode },
4493     { Bad_Opcode },
4494     /* 88 */
4495     { Bad_Opcode },
4496     { Bad_Opcode },
4497     { Bad_Opcode },
4498     { Bad_Opcode },
4499     { Bad_Opcode },
4500     { Bad_Opcode },
4501     { Bad_Opcode },
4502     { Bad_Opcode },
4503     /* 90 */
4504     { Bad_Opcode },
4505     { Bad_Opcode },
4506     { Bad_Opcode },
4507     { Bad_Opcode },
4508     { Bad_Opcode },
4509     { Bad_Opcode },
4510     { Bad_Opcode },
4511     { Bad_Opcode },
4512     /* 98 */
4513     { Bad_Opcode },
4514     { Bad_Opcode },
4515     { Bad_Opcode },
4516     { Bad_Opcode },
4517     { Bad_Opcode },
4518     { Bad_Opcode },
4519     { Bad_Opcode },
4520     { Bad_Opcode },
4521     /* a0 */
4522     { Bad_Opcode },
4523     { Bad_Opcode },
4524     { Bad_Opcode },
4525     { Bad_Opcode },
4526     { Bad_Opcode },
4527     { Bad_Opcode },
4528     { Bad_Opcode },
4529     { Bad_Opcode },
4530     /* a8 */
4531     { Bad_Opcode },
4532     { Bad_Opcode },
4533     { Bad_Opcode },
4534     { Bad_Opcode },
4535     { Bad_Opcode },
4536     { Bad_Opcode },
4537     { Bad_Opcode },
4538     { Bad_Opcode },
4539     /* b0 */
4540     { Bad_Opcode },
4541     { Bad_Opcode },
4542     { Bad_Opcode },
4543     { Bad_Opcode },
4544     { Bad_Opcode },
4545     { Bad_Opcode },
4546     { Bad_Opcode },
4547     { Bad_Opcode },
4548     /* b8 */
4549     { Bad_Opcode },
4550     { Bad_Opcode },
4551     { Bad_Opcode },
4552     { Bad_Opcode },
4553     { Bad_Opcode },
4554     { Bad_Opcode },
4555     { Bad_Opcode },
4556     { Bad_Opcode },
4557     /* c0 */
4558     { Bad_Opcode },
4559     { Bad_Opcode },
4560     { Bad_Opcode },
4561     { Bad_Opcode },
4562     { Bad_Opcode },
4563     { Bad_Opcode },
4564     { Bad_Opcode },
4565     { Bad_Opcode },
4566     /* c8 */
4567     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4568     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4569     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4570     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4571     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4572     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4573     { Bad_Opcode },
4574     { "gf2p8mulb", { XM, EXxmm }, PREFIX_DATA },
4575     /* d0 */
4576     { Bad_Opcode },
4577     { Bad_Opcode },
4578     { Bad_Opcode },
4579     { Bad_Opcode },
4580     { Bad_Opcode },
4581     { Bad_Opcode },
4582     { Bad_Opcode },
4583     { Bad_Opcode },
4584     /* d8 */
4585     { PREFIX_TABLE (PREFIX_0F38D8) },
4586     { Bad_Opcode },
4587     { Bad_Opcode },
4588     { "aesimc", { XM, EXx }, PREFIX_DATA },
4589     { PREFIX_TABLE (PREFIX_0F38DC) },
4590     { PREFIX_TABLE (PREFIX_0F38DD) },
4591     { PREFIX_TABLE (PREFIX_0F38DE) },
4592     { PREFIX_TABLE (PREFIX_0F38DF) },
4593     /* e0 */
4594     { Bad_Opcode },
4595     { Bad_Opcode },
4596     { Bad_Opcode },
4597     { Bad_Opcode },
4598     { Bad_Opcode },
4599     { Bad_Opcode },
4600     { Bad_Opcode },
4601     { Bad_Opcode },
4602     /* e8 */
4603     { Bad_Opcode },
4604     { Bad_Opcode },
4605     { Bad_Opcode },
4606     { Bad_Opcode },
4607     { Bad_Opcode },
4608     { Bad_Opcode },
4609     { Bad_Opcode },
4610     { Bad_Opcode },
4611     /* f0 */
4612     { PREFIX_TABLE (PREFIX_0F38F0) },
4613     { PREFIX_TABLE (PREFIX_0F38F1) },
4614     { Bad_Opcode },
4615     { Bad_Opcode },
4616     { Bad_Opcode },
4617     { MOD_TABLE (MOD_0F38F5) },
4618     { PREFIX_TABLE (PREFIX_0F38F6) },
4619     { Bad_Opcode },
4620     /* f8 */
4621     { PREFIX_TABLE (PREFIX_0F38F8) },
4622     { MOD_TABLE (MOD_0F38F9) },
4623     { PREFIX_TABLE (PREFIX_0F38FA) },
4624     { PREFIX_TABLE (PREFIX_0F38FB) },
4625     { Bad_Opcode },
4626     { Bad_Opcode },
4627     { Bad_Opcode },
4628     { Bad_Opcode },
4629   },
4630   /* THREE_BYTE_0F3A */
4631   {
4632     /* 00 */
4633     { Bad_Opcode },
4634     { Bad_Opcode },
4635     { Bad_Opcode },
4636     { Bad_Opcode },
4637     { Bad_Opcode },
4638     { Bad_Opcode },
4639     { Bad_Opcode },
4640     { Bad_Opcode },
4641     /* 08 */
4642     { "roundps", { XM, EXx, Ib }, PREFIX_DATA },
4643     { "roundpd", { XM, EXx, Ib }, PREFIX_DATA },
4644     { "roundss", { XM, EXd, Ib }, PREFIX_DATA },
4645     { "roundsd", { XM, EXq, Ib }, PREFIX_DATA },
4646     { "blendps", { XM, EXx, Ib }, PREFIX_DATA },
4647     { "blendpd", { XM, EXx, Ib }, PREFIX_DATA },
4648     { "pblendw", { XM, EXx, Ib }, PREFIX_DATA },
4649     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
4650     /* 10 */
4651     { Bad_Opcode },
4652     { Bad_Opcode },
4653     { Bad_Opcode },
4654     { Bad_Opcode },
4655     { "pextrb", { Edb, XM, Ib }, PREFIX_DATA },
4656     { "pextrw", { Edw, XM, Ib }, PREFIX_DATA },
4657     { "pextrK", { Edq, XM, Ib }, PREFIX_DATA },
4658     { "extractps", { Ed, XM, Ib }, PREFIX_DATA },
4659     /* 18 */
4660     { Bad_Opcode },
4661     { Bad_Opcode },
4662     { Bad_Opcode },
4663     { Bad_Opcode },
4664     { Bad_Opcode },
4665     { Bad_Opcode },
4666     { Bad_Opcode },
4667     { Bad_Opcode },
4668     /* 20 */
4669     { "pinsrb", { XM, Edb, Ib }, PREFIX_DATA },
4670     { "insertps", { XM, EXd, Ib }, PREFIX_DATA },
4671     { "pinsrK", { XM, Edq, Ib }, PREFIX_DATA },
4672     { Bad_Opcode },
4673     { Bad_Opcode },
4674     { Bad_Opcode },
4675     { Bad_Opcode },
4676     { Bad_Opcode },
4677     /* 28 */
4678     { Bad_Opcode },
4679     { Bad_Opcode },
4680     { Bad_Opcode },
4681     { Bad_Opcode },
4682     { Bad_Opcode },
4683     { Bad_Opcode },
4684     { Bad_Opcode },
4685     { Bad_Opcode },
4686     /* 30 */
4687     { Bad_Opcode },
4688     { Bad_Opcode },
4689     { Bad_Opcode },
4690     { Bad_Opcode },
4691     { Bad_Opcode },
4692     { Bad_Opcode },
4693     { Bad_Opcode },
4694     { Bad_Opcode },
4695     /* 38 */
4696     { Bad_Opcode },
4697     { Bad_Opcode },
4698     { Bad_Opcode },
4699     { Bad_Opcode },
4700     { Bad_Opcode },
4701     { Bad_Opcode },
4702     { Bad_Opcode },
4703     { Bad_Opcode },
4704     /* 40 */
4705     { "dpps",   { XM, EXx, Ib }, PREFIX_DATA },
4706     { "dppd",   { XM, EXx, Ib }, PREFIX_DATA },
4707     { "mpsadbw", { XM, EXx, Ib }, PREFIX_DATA },
4708     { Bad_Opcode },
4709     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_DATA },
4710     { Bad_Opcode },
4711     { Bad_Opcode },
4712     { Bad_Opcode },
4713     /* 48 */
4714     { Bad_Opcode },
4715     { Bad_Opcode },
4716     { Bad_Opcode },
4717     { Bad_Opcode },
4718     { Bad_Opcode },
4719     { Bad_Opcode },
4720     { Bad_Opcode },
4721     { Bad_Opcode },
4722     /* 50 */
4723     { Bad_Opcode },
4724     { Bad_Opcode },
4725     { Bad_Opcode },
4726     { Bad_Opcode },
4727     { Bad_Opcode },
4728     { Bad_Opcode },
4729     { Bad_Opcode },
4730     { Bad_Opcode },
4731     /* 58 */
4732     { Bad_Opcode },
4733     { Bad_Opcode },
4734     { Bad_Opcode },
4735     { Bad_Opcode },
4736     { Bad_Opcode },
4737     { Bad_Opcode },
4738     { Bad_Opcode },
4739     { Bad_Opcode },
4740     /* 60 */
4741     { "pcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
4742     { "pcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
4743     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_DATA },
4744     { "pcmpistri", { XM, EXx, Ib }, PREFIX_DATA },
4745     { Bad_Opcode },
4746     { Bad_Opcode },
4747     { Bad_Opcode },
4748     { Bad_Opcode },
4749     /* 68 */
4750     { Bad_Opcode },
4751     { Bad_Opcode },
4752     { Bad_Opcode },
4753     { Bad_Opcode },
4754     { Bad_Opcode },
4755     { Bad_Opcode },
4756     { Bad_Opcode },
4757     { Bad_Opcode },
4758     /* 70 */
4759     { Bad_Opcode },
4760     { Bad_Opcode },
4761     { Bad_Opcode },
4762     { Bad_Opcode },
4763     { Bad_Opcode },
4764     { Bad_Opcode },
4765     { Bad_Opcode },
4766     { Bad_Opcode },
4767     /* 78 */
4768     { Bad_Opcode },
4769     { Bad_Opcode },
4770     { Bad_Opcode },
4771     { Bad_Opcode },
4772     { Bad_Opcode },
4773     { Bad_Opcode },
4774     { Bad_Opcode },
4775     { Bad_Opcode },
4776     /* 80 */
4777     { Bad_Opcode },
4778     { Bad_Opcode },
4779     { Bad_Opcode },
4780     { Bad_Opcode },
4781     { Bad_Opcode },
4782     { Bad_Opcode },
4783     { Bad_Opcode },
4784     { Bad_Opcode },
4785     /* 88 */
4786     { Bad_Opcode },
4787     { Bad_Opcode },
4788     { Bad_Opcode },
4789     { Bad_Opcode },
4790     { Bad_Opcode },
4791     { Bad_Opcode },
4792     { Bad_Opcode },
4793     { Bad_Opcode },
4794     /* 90 */
4795     { Bad_Opcode },
4796     { Bad_Opcode },
4797     { Bad_Opcode },
4798     { Bad_Opcode },
4799     { Bad_Opcode },
4800     { Bad_Opcode },
4801     { Bad_Opcode },
4802     { Bad_Opcode },
4803     /* 98 */
4804     { Bad_Opcode },
4805     { Bad_Opcode },
4806     { Bad_Opcode },
4807     { Bad_Opcode },
4808     { Bad_Opcode },
4809     { Bad_Opcode },
4810     { Bad_Opcode },
4811     { Bad_Opcode },
4812     /* a0 */
4813     { Bad_Opcode },
4814     { Bad_Opcode },
4815     { Bad_Opcode },
4816     { Bad_Opcode },
4817     { Bad_Opcode },
4818     { Bad_Opcode },
4819     { Bad_Opcode },
4820     { Bad_Opcode },
4821     /* a8 */
4822     { Bad_Opcode },
4823     { Bad_Opcode },
4824     { Bad_Opcode },
4825     { Bad_Opcode },
4826     { Bad_Opcode },
4827     { Bad_Opcode },
4828     { Bad_Opcode },
4829     { Bad_Opcode },
4830     /* b0 */
4831     { Bad_Opcode },
4832     { Bad_Opcode },
4833     { Bad_Opcode },
4834     { Bad_Opcode },
4835     { Bad_Opcode },
4836     { Bad_Opcode },
4837     { Bad_Opcode },
4838     { Bad_Opcode },
4839     /* b8 */
4840     { Bad_Opcode },
4841     { Bad_Opcode },
4842     { Bad_Opcode },
4843     { Bad_Opcode },
4844     { Bad_Opcode },
4845     { Bad_Opcode },
4846     { Bad_Opcode },
4847     { Bad_Opcode },
4848     /* c0 */
4849     { Bad_Opcode },
4850     { Bad_Opcode },
4851     { Bad_Opcode },
4852     { Bad_Opcode },
4853     { Bad_Opcode },
4854     { Bad_Opcode },
4855     { Bad_Opcode },
4856     { Bad_Opcode },
4857     /* c8 */
4858     { Bad_Opcode },
4859     { Bad_Opcode },
4860     { Bad_Opcode },
4861     { Bad_Opcode },
4862     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4863     { Bad_Opcode },
4864     { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_DATA },
4865     { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_DATA },
4866     /* d0 */
4867     { Bad_Opcode },
4868     { Bad_Opcode },
4869     { Bad_Opcode },
4870     { Bad_Opcode },
4871     { Bad_Opcode },
4872     { Bad_Opcode },
4873     { Bad_Opcode },
4874     { Bad_Opcode },
4875     /* d8 */
4876     { Bad_Opcode },
4877     { Bad_Opcode },
4878     { Bad_Opcode },
4879     { Bad_Opcode },
4880     { Bad_Opcode },
4881     { Bad_Opcode },
4882     { Bad_Opcode },
4883     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
4884     /* e0 */
4885     { Bad_Opcode },
4886     { Bad_Opcode },
4887     { Bad_Opcode },
4888     { Bad_Opcode },
4889     { Bad_Opcode },
4890     { Bad_Opcode },
4891     { Bad_Opcode },
4892     { Bad_Opcode },
4893     /* e8 */
4894     { Bad_Opcode },
4895     { Bad_Opcode },
4896     { Bad_Opcode },
4897     { Bad_Opcode },
4898     { Bad_Opcode },
4899     { Bad_Opcode },
4900     { Bad_Opcode },
4901     { Bad_Opcode },
4902     /* f0 */
4903     { PREFIX_TABLE (PREFIX_0F3A0F) },
4904     { Bad_Opcode },
4905     { Bad_Opcode },
4906     { Bad_Opcode },
4907     { Bad_Opcode },
4908     { Bad_Opcode },
4909     { Bad_Opcode },
4910     { Bad_Opcode },
4911     /* f8 */
4912     { Bad_Opcode },
4913     { Bad_Opcode },
4914     { Bad_Opcode },
4915     { Bad_Opcode },
4916     { Bad_Opcode },
4917     { Bad_Opcode },
4918     { Bad_Opcode },
4919     { Bad_Opcode },
4920   },
4921 };
4922
4923 static const struct dis386 xop_table[][256] = {
4924   /* XOP_08 */
4925   {
4926     /* 00 */
4927     { Bad_Opcode },
4928     { Bad_Opcode },
4929     { Bad_Opcode },
4930     { Bad_Opcode },
4931     { Bad_Opcode },
4932     { Bad_Opcode },
4933     { Bad_Opcode },
4934     { Bad_Opcode },
4935     /* 08 */
4936     { Bad_Opcode },
4937     { Bad_Opcode },
4938     { Bad_Opcode },
4939     { Bad_Opcode },
4940     { Bad_Opcode },
4941     { Bad_Opcode },
4942     { Bad_Opcode },
4943     { Bad_Opcode },
4944     /* 10 */
4945     { Bad_Opcode },
4946     { Bad_Opcode },
4947     { Bad_Opcode },
4948     { Bad_Opcode },
4949     { Bad_Opcode },
4950     { Bad_Opcode },
4951     { Bad_Opcode },
4952     { Bad_Opcode },
4953     /* 18 */
4954     { Bad_Opcode },
4955     { Bad_Opcode },
4956     { Bad_Opcode },
4957     { Bad_Opcode },
4958     { Bad_Opcode },
4959     { Bad_Opcode },
4960     { Bad_Opcode },
4961     { Bad_Opcode },
4962     /* 20 */
4963     { Bad_Opcode },
4964     { Bad_Opcode },
4965     { Bad_Opcode },
4966     { Bad_Opcode },
4967     { Bad_Opcode },
4968     { Bad_Opcode },
4969     { Bad_Opcode },
4970     { Bad_Opcode },
4971     /* 28 */
4972     { Bad_Opcode },
4973     { Bad_Opcode },
4974     { Bad_Opcode },
4975     { Bad_Opcode },
4976     { Bad_Opcode },
4977     { Bad_Opcode },
4978     { Bad_Opcode },
4979     { Bad_Opcode },
4980     /* 30 */
4981     { Bad_Opcode },
4982     { Bad_Opcode },
4983     { Bad_Opcode },
4984     { Bad_Opcode },
4985     { Bad_Opcode },
4986     { Bad_Opcode },
4987     { Bad_Opcode },
4988     { Bad_Opcode },
4989     /* 38 */
4990     { Bad_Opcode },
4991     { Bad_Opcode },
4992     { Bad_Opcode },
4993     { Bad_Opcode },
4994     { Bad_Opcode },
4995     { Bad_Opcode },
4996     { Bad_Opcode },
4997     { Bad_Opcode },
4998     /* 40 */
4999     { Bad_Opcode },
5000     { Bad_Opcode },
5001     { Bad_Opcode },
5002     { Bad_Opcode },
5003     { Bad_Opcode },
5004     { Bad_Opcode },
5005     { Bad_Opcode },
5006     { Bad_Opcode },
5007     /* 48 */
5008     { Bad_Opcode },
5009     { Bad_Opcode },
5010     { Bad_Opcode },
5011     { Bad_Opcode },
5012     { Bad_Opcode },
5013     { Bad_Opcode },
5014     { Bad_Opcode },
5015     { Bad_Opcode },
5016     /* 50 */
5017     { Bad_Opcode },
5018     { Bad_Opcode },
5019     { Bad_Opcode },
5020     { Bad_Opcode },
5021     { Bad_Opcode },
5022     { Bad_Opcode },
5023     { Bad_Opcode },
5024     { Bad_Opcode },
5025     /* 58 */
5026     { Bad_Opcode },
5027     { Bad_Opcode },
5028     { Bad_Opcode },
5029     { Bad_Opcode },
5030     { Bad_Opcode },
5031     { Bad_Opcode },
5032     { Bad_Opcode },
5033     { Bad_Opcode },
5034     /* 60 */
5035     { Bad_Opcode },
5036     { Bad_Opcode },
5037     { Bad_Opcode },
5038     { Bad_Opcode },
5039     { Bad_Opcode },
5040     { Bad_Opcode },
5041     { Bad_Opcode },
5042     { Bad_Opcode },
5043     /* 68 */
5044     { Bad_Opcode },
5045     { Bad_Opcode },
5046     { Bad_Opcode },
5047     { Bad_Opcode },
5048     { Bad_Opcode },
5049     { Bad_Opcode },
5050     { Bad_Opcode },
5051     { Bad_Opcode },
5052     /* 70 */
5053     { Bad_Opcode },
5054     { Bad_Opcode },
5055     { Bad_Opcode },
5056     { Bad_Opcode },
5057     { Bad_Opcode },
5058     { Bad_Opcode },
5059     { Bad_Opcode },
5060     { Bad_Opcode },
5061     /* 78 */
5062     { Bad_Opcode },
5063     { Bad_Opcode },
5064     { Bad_Opcode },
5065     { Bad_Opcode },
5066     { Bad_Opcode },
5067     { Bad_Opcode },
5068     { Bad_Opcode },
5069     { Bad_Opcode },
5070     /* 80 */
5071     { Bad_Opcode },
5072     { Bad_Opcode },
5073     { Bad_Opcode },
5074     { Bad_Opcode },
5075     { Bad_Opcode },
5076     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_85) },
5077     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_86) },
5078     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_87) },
5079     /* 88 */
5080     { Bad_Opcode },
5081     { Bad_Opcode },
5082     { Bad_Opcode },
5083     { Bad_Opcode },
5084     { Bad_Opcode },
5085     { Bad_Opcode },
5086     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8E) },
5087     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8F) },
5088     /* 90 */
5089     { Bad_Opcode },
5090     { Bad_Opcode },
5091     { Bad_Opcode },
5092     { Bad_Opcode },
5093     { Bad_Opcode },
5094     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_95) },
5095     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_96) },
5096     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_97) },
5097     /* 98 */
5098     { Bad_Opcode },
5099     { Bad_Opcode },
5100     { Bad_Opcode },
5101     { Bad_Opcode },
5102     { Bad_Opcode },
5103     { Bad_Opcode },
5104     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9E) },
5105     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9F) },
5106     /* a0 */
5107     { Bad_Opcode },
5108     { Bad_Opcode },
5109     { "vpcmov",         { XM, Vex, EXx, XMVexI4 }, 0 },
5110     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A3) },
5111     { Bad_Opcode },
5112     { Bad_Opcode },
5113     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A6) },
5114     { Bad_Opcode },
5115     /* a8 */
5116     { Bad_Opcode },
5117     { Bad_Opcode },
5118     { Bad_Opcode },
5119     { Bad_Opcode },
5120     { Bad_Opcode },
5121     { Bad_Opcode },
5122     { Bad_Opcode },
5123     { Bad_Opcode },
5124     /* b0 */
5125     { Bad_Opcode },
5126     { Bad_Opcode },
5127     { Bad_Opcode },
5128     { Bad_Opcode },
5129     { Bad_Opcode },
5130     { Bad_Opcode },
5131     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_B6) },
5132     { Bad_Opcode },
5133     /* b8 */
5134     { Bad_Opcode },
5135     { Bad_Opcode },
5136     { Bad_Opcode },
5137     { Bad_Opcode },
5138     { Bad_Opcode },
5139     { Bad_Opcode },
5140     { Bad_Opcode },
5141     { Bad_Opcode },
5142     /* c0 */
5143     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C0) },
5144     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C1) },
5145     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C2) },
5146     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C3) },
5147     { Bad_Opcode },
5148     { Bad_Opcode },
5149     { Bad_Opcode },
5150     { Bad_Opcode },
5151     /* c8 */
5152     { Bad_Opcode },
5153     { Bad_Opcode },
5154     { Bad_Opcode },
5155     { Bad_Opcode },
5156     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
5157     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
5158     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
5159     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
5160     /* d0 */
5161     { Bad_Opcode },
5162     { Bad_Opcode },
5163     { Bad_Opcode },
5164     { Bad_Opcode },
5165     { Bad_Opcode },
5166     { Bad_Opcode },
5167     { Bad_Opcode },
5168     { Bad_Opcode },
5169     /* d8 */
5170     { Bad_Opcode },
5171     { Bad_Opcode },
5172     { Bad_Opcode },
5173     { Bad_Opcode },
5174     { Bad_Opcode },
5175     { Bad_Opcode },
5176     { Bad_Opcode },
5177     { Bad_Opcode },
5178     /* e0 */
5179     { Bad_Opcode },
5180     { Bad_Opcode },
5181     { Bad_Opcode },
5182     { Bad_Opcode },
5183     { Bad_Opcode },
5184     { Bad_Opcode },
5185     { Bad_Opcode },
5186     { Bad_Opcode },
5187     /* e8 */
5188     { Bad_Opcode },
5189     { Bad_Opcode },
5190     { Bad_Opcode },
5191     { Bad_Opcode },
5192     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
5193     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
5194     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
5195     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
5196     /* f0 */
5197     { Bad_Opcode },
5198     { Bad_Opcode },
5199     { Bad_Opcode },
5200     { Bad_Opcode },
5201     { Bad_Opcode },
5202     { Bad_Opcode },
5203     { Bad_Opcode },
5204     { Bad_Opcode },
5205     /* f8 */
5206     { Bad_Opcode },
5207     { Bad_Opcode },
5208     { Bad_Opcode },
5209     { Bad_Opcode },
5210     { Bad_Opcode },
5211     { Bad_Opcode },
5212     { Bad_Opcode },
5213     { Bad_Opcode },
5214   },
5215   /* XOP_09 */
5216   {
5217     /* 00 */
5218     { Bad_Opcode },
5219     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_01) },
5220     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_02) },
5221     { Bad_Opcode },
5222     { Bad_Opcode },
5223     { Bad_Opcode },
5224     { Bad_Opcode },
5225     { Bad_Opcode },
5226     /* 08 */
5227     { Bad_Opcode },
5228     { Bad_Opcode },
5229     { Bad_Opcode },
5230     { Bad_Opcode },
5231     { Bad_Opcode },
5232     { Bad_Opcode },
5233     { Bad_Opcode },
5234     { Bad_Opcode },
5235     /* 10 */
5236     { Bad_Opcode },
5237     { Bad_Opcode },
5238     { MOD_TABLE (MOD_XOP_09_12) },
5239     { Bad_Opcode },
5240     { Bad_Opcode },
5241     { Bad_Opcode },
5242     { Bad_Opcode },
5243     { Bad_Opcode },
5244     /* 18 */
5245     { Bad_Opcode },
5246     { Bad_Opcode },
5247     { Bad_Opcode },
5248     { Bad_Opcode },
5249     { Bad_Opcode },
5250     { Bad_Opcode },
5251     { Bad_Opcode },
5252     { Bad_Opcode },
5253     /* 20 */
5254     { Bad_Opcode },
5255     { Bad_Opcode },
5256     { Bad_Opcode },
5257     { Bad_Opcode },
5258     { Bad_Opcode },
5259     { Bad_Opcode },
5260     { Bad_Opcode },
5261     { Bad_Opcode },
5262     /* 28 */
5263     { Bad_Opcode },
5264     { Bad_Opcode },
5265     { Bad_Opcode },
5266     { Bad_Opcode },
5267     { Bad_Opcode },
5268     { Bad_Opcode },
5269     { Bad_Opcode },
5270     { Bad_Opcode },
5271     /* 30 */
5272     { Bad_Opcode },
5273     { Bad_Opcode },
5274     { Bad_Opcode },
5275     { Bad_Opcode },
5276     { Bad_Opcode },
5277     { Bad_Opcode },
5278     { Bad_Opcode },
5279     { Bad_Opcode },
5280     /* 38 */
5281     { Bad_Opcode },
5282     { Bad_Opcode },
5283     { Bad_Opcode },
5284     { Bad_Opcode },
5285     { Bad_Opcode },
5286     { Bad_Opcode },
5287     { Bad_Opcode },
5288     { Bad_Opcode },
5289     /* 40 */
5290     { Bad_Opcode },
5291     { Bad_Opcode },
5292     { Bad_Opcode },
5293     { Bad_Opcode },
5294     { Bad_Opcode },
5295     { Bad_Opcode },
5296     { Bad_Opcode },
5297     { Bad_Opcode },
5298     /* 48 */
5299     { Bad_Opcode },
5300     { Bad_Opcode },
5301     { Bad_Opcode },
5302     { Bad_Opcode },
5303     { Bad_Opcode },
5304     { Bad_Opcode },
5305     { Bad_Opcode },
5306     { Bad_Opcode },
5307     /* 50 */
5308     { Bad_Opcode },
5309     { Bad_Opcode },
5310     { Bad_Opcode },
5311     { Bad_Opcode },
5312     { Bad_Opcode },
5313     { Bad_Opcode },
5314     { Bad_Opcode },
5315     { Bad_Opcode },
5316     /* 58 */
5317     { Bad_Opcode },
5318     { Bad_Opcode },
5319     { Bad_Opcode },
5320     { Bad_Opcode },
5321     { Bad_Opcode },
5322     { Bad_Opcode },
5323     { Bad_Opcode },
5324     { Bad_Opcode },
5325     /* 60 */
5326     { Bad_Opcode },
5327     { Bad_Opcode },
5328     { Bad_Opcode },
5329     { Bad_Opcode },
5330     { Bad_Opcode },
5331     { Bad_Opcode },
5332     { Bad_Opcode },
5333     { Bad_Opcode },
5334     /* 68 */
5335     { Bad_Opcode },
5336     { Bad_Opcode },
5337     { Bad_Opcode },
5338     { Bad_Opcode },
5339     { Bad_Opcode },
5340     { Bad_Opcode },
5341     { Bad_Opcode },
5342     { Bad_Opcode },
5343     /* 70 */
5344     { Bad_Opcode },
5345     { Bad_Opcode },
5346     { Bad_Opcode },
5347     { Bad_Opcode },
5348     { Bad_Opcode },
5349     { Bad_Opcode },
5350     { Bad_Opcode },
5351     { Bad_Opcode },
5352     /* 78 */
5353     { Bad_Opcode },
5354     { Bad_Opcode },
5355     { Bad_Opcode },
5356     { Bad_Opcode },
5357     { Bad_Opcode },
5358     { Bad_Opcode },
5359     { Bad_Opcode },
5360     { Bad_Opcode },
5361     /* 80 */
5362     { VEX_W_TABLE (VEX_W_0FXOP_09_80) },
5363     { VEX_W_TABLE (VEX_W_0FXOP_09_81) },
5364     { VEX_W_TABLE (VEX_W_0FXOP_09_82) },
5365     { VEX_W_TABLE (VEX_W_0FXOP_09_83) },
5366     { Bad_Opcode },
5367     { Bad_Opcode },
5368     { Bad_Opcode },
5369     { Bad_Opcode },
5370     /* 88 */
5371     { Bad_Opcode },
5372     { Bad_Opcode },
5373     { Bad_Opcode },
5374     { Bad_Opcode },
5375     { Bad_Opcode },
5376     { Bad_Opcode },
5377     { Bad_Opcode },
5378     { Bad_Opcode },
5379     /* 90 */
5380     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_90) },
5381     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_91) },
5382     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_92) },
5383     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_93) },
5384     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_94) },
5385     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_95) },
5386     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_96) },
5387     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_97) },
5388     /* 98 */
5389     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_98) },
5390     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_99) },
5391     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9A) },
5392     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9B) },
5393     { Bad_Opcode },
5394     { Bad_Opcode },
5395     { Bad_Opcode },
5396     { Bad_Opcode },
5397     /* a0 */
5398     { Bad_Opcode },
5399     { Bad_Opcode },
5400     { Bad_Opcode },
5401     { Bad_Opcode },
5402     { Bad_Opcode },
5403     { Bad_Opcode },
5404     { Bad_Opcode },
5405     { Bad_Opcode },
5406     /* a8 */
5407     { Bad_Opcode },
5408     { Bad_Opcode },
5409     { Bad_Opcode },
5410     { Bad_Opcode },
5411     { Bad_Opcode },
5412     { Bad_Opcode },
5413     { Bad_Opcode },
5414     { Bad_Opcode },
5415     /* b0 */
5416     { Bad_Opcode },
5417     { Bad_Opcode },
5418     { Bad_Opcode },
5419     { Bad_Opcode },
5420     { Bad_Opcode },
5421     { Bad_Opcode },
5422     { Bad_Opcode },
5423     { Bad_Opcode },
5424     /* b8 */
5425     { Bad_Opcode },
5426     { Bad_Opcode },
5427     { Bad_Opcode },
5428     { Bad_Opcode },
5429     { Bad_Opcode },
5430     { Bad_Opcode },
5431     { Bad_Opcode },
5432     { Bad_Opcode },
5433     /* c0 */
5434     { Bad_Opcode },
5435     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C1) },
5436     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C2) },
5437     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C3) },
5438     { Bad_Opcode },
5439     { Bad_Opcode },
5440     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C6) },
5441     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C7) },
5442     /* c8 */
5443     { Bad_Opcode },
5444     { Bad_Opcode },
5445     { Bad_Opcode },
5446     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_CB) },
5447     { Bad_Opcode },
5448     { Bad_Opcode },
5449     { Bad_Opcode },
5450     { Bad_Opcode },
5451     /* d0 */
5452     { Bad_Opcode },
5453     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D1) },
5454     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D2) },
5455     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D3) },
5456     { Bad_Opcode },
5457     { Bad_Opcode },
5458     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D6) },
5459     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D7) },
5460     /* d8 */
5461     { Bad_Opcode },
5462     { Bad_Opcode },
5463     { Bad_Opcode },
5464     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_DB) },
5465     { Bad_Opcode },
5466     { Bad_Opcode },
5467     { Bad_Opcode },
5468     { Bad_Opcode },
5469     /* e0 */
5470     { Bad_Opcode },
5471     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E1) },
5472     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E2) },
5473     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E3) },
5474     { Bad_Opcode },
5475     { Bad_Opcode },
5476     { Bad_Opcode },
5477     { Bad_Opcode },
5478     /* e8 */
5479     { Bad_Opcode },
5480     { Bad_Opcode },
5481     { Bad_Opcode },
5482     { Bad_Opcode },
5483     { Bad_Opcode },
5484     { Bad_Opcode },
5485     { Bad_Opcode },
5486     { Bad_Opcode },
5487     /* f0 */
5488     { Bad_Opcode },
5489     { Bad_Opcode },
5490     { Bad_Opcode },
5491     { Bad_Opcode },
5492     { Bad_Opcode },
5493     { Bad_Opcode },
5494     { Bad_Opcode },
5495     { Bad_Opcode },
5496     /* f8 */
5497     { Bad_Opcode },
5498     { Bad_Opcode },
5499     { Bad_Opcode },
5500     { Bad_Opcode },
5501     { Bad_Opcode },
5502     { Bad_Opcode },
5503     { Bad_Opcode },
5504     { Bad_Opcode },
5505   },
5506   /* XOP_0A */
5507   {
5508     /* 00 */
5509     { Bad_Opcode },
5510     { Bad_Opcode },
5511     { Bad_Opcode },
5512     { Bad_Opcode },
5513     { Bad_Opcode },
5514     { Bad_Opcode },
5515     { Bad_Opcode },
5516     { Bad_Opcode },
5517     /* 08 */
5518     { Bad_Opcode },
5519     { Bad_Opcode },
5520     { Bad_Opcode },
5521     { Bad_Opcode },
5522     { Bad_Opcode },
5523     { Bad_Opcode },
5524     { Bad_Opcode },
5525     { Bad_Opcode },
5526     /* 10 */
5527     { "bextrS", { Gdq, Edq, Id }, 0 },
5528     { Bad_Opcode },
5529     { VEX_LEN_TABLE (VEX_LEN_0FXOP_0A_12) },
5530     { Bad_Opcode },
5531     { Bad_Opcode },
5532     { Bad_Opcode },
5533     { Bad_Opcode },
5534     { Bad_Opcode },
5535     /* 18 */
5536     { Bad_Opcode },
5537     { Bad_Opcode },
5538     { Bad_Opcode },
5539     { Bad_Opcode },
5540     { Bad_Opcode },
5541     { Bad_Opcode },
5542     { Bad_Opcode },
5543     { Bad_Opcode },
5544     /* 20 */
5545     { Bad_Opcode },
5546     { Bad_Opcode },
5547     { Bad_Opcode },
5548     { Bad_Opcode },
5549     { Bad_Opcode },
5550     { Bad_Opcode },
5551     { Bad_Opcode },
5552     { Bad_Opcode },
5553     /* 28 */
5554     { Bad_Opcode },
5555     { Bad_Opcode },
5556     { Bad_Opcode },
5557     { Bad_Opcode },
5558     { Bad_Opcode },
5559     { Bad_Opcode },
5560     { Bad_Opcode },
5561     { Bad_Opcode },
5562     /* 30 */
5563     { Bad_Opcode },
5564     { Bad_Opcode },
5565     { Bad_Opcode },
5566     { Bad_Opcode },
5567     { Bad_Opcode },
5568     { Bad_Opcode },
5569     { Bad_Opcode },
5570     { Bad_Opcode },
5571     /* 38 */
5572     { Bad_Opcode },
5573     { Bad_Opcode },
5574     { Bad_Opcode },
5575     { Bad_Opcode },
5576     { Bad_Opcode },
5577     { Bad_Opcode },
5578     { Bad_Opcode },
5579     { Bad_Opcode },
5580     /* 40 */
5581     { Bad_Opcode },
5582     { Bad_Opcode },
5583     { Bad_Opcode },
5584     { Bad_Opcode },
5585     { Bad_Opcode },
5586     { Bad_Opcode },
5587     { Bad_Opcode },
5588     { Bad_Opcode },
5589     /* 48 */
5590     { Bad_Opcode },
5591     { Bad_Opcode },
5592     { Bad_Opcode },
5593     { Bad_Opcode },
5594     { Bad_Opcode },
5595     { Bad_Opcode },
5596     { Bad_Opcode },
5597     { Bad_Opcode },
5598     /* 50 */
5599     { Bad_Opcode },
5600     { Bad_Opcode },
5601     { Bad_Opcode },
5602     { Bad_Opcode },
5603     { Bad_Opcode },
5604     { Bad_Opcode },
5605     { Bad_Opcode },
5606     { Bad_Opcode },
5607     /* 58 */
5608     { Bad_Opcode },
5609     { Bad_Opcode },
5610     { Bad_Opcode },
5611     { Bad_Opcode },
5612     { Bad_Opcode },
5613     { Bad_Opcode },
5614     { Bad_Opcode },
5615     { Bad_Opcode },
5616     /* 60 */
5617     { Bad_Opcode },
5618     { Bad_Opcode },
5619     { Bad_Opcode },
5620     { Bad_Opcode },
5621     { Bad_Opcode },
5622     { Bad_Opcode },
5623     { Bad_Opcode },
5624     { Bad_Opcode },
5625     /* 68 */
5626     { Bad_Opcode },
5627     { Bad_Opcode },
5628     { Bad_Opcode },
5629     { Bad_Opcode },
5630     { Bad_Opcode },
5631     { Bad_Opcode },
5632     { Bad_Opcode },
5633     { Bad_Opcode },
5634     /* 70 */
5635     { Bad_Opcode },
5636     { Bad_Opcode },
5637     { Bad_Opcode },
5638     { Bad_Opcode },
5639     { Bad_Opcode },
5640     { Bad_Opcode },
5641     { Bad_Opcode },
5642     { Bad_Opcode },
5643     /* 78 */
5644     { Bad_Opcode },
5645     { Bad_Opcode },
5646     { Bad_Opcode },
5647     { Bad_Opcode },
5648     { Bad_Opcode },
5649     { Bad_Opcode },
5650     { Bad_Opcode },
5651     { Bad_Opcode },
5652     /* 80 */
5653     { Bad_Opcode },
5654     { Bad_Opcode },
5655     { Bad_Opcode },
5656     { Bad_Opcode },
5657     { Bad_Opcode },
5658     { Bad_Opcode },
5659     { Bad_Opcode },
5660     { Bad_Opcode },
5661     /* 88 */
5662     { Bad_Opcode },
5663     { Bad_Opcode },
5664     { Bad_Opcode },
5665     { Bad_Opcode },
5666     { Bad_Opcode },
5667     { Bad_Opcode },
5668     { Bad_Opcode },
5669     { Bad_Opcode },
5670     /* 90 */
5671     { Bad_Opcode },
5672     { Bad_Opcode },
5673     { Bad_Opcode },
5674     { Bad_Opcode },
5675     { Bad_Opcode },
5676     { Bad_Opcode },
5677     { Bad_Opcode },
5678     { Bad_Opcode },
5679     /* 98 */
5680     { Bad_Opcode },
5681     { Bad_Opcode },
5682     { Bad_Opcode },
5683     { Bad_Opcode },
5684     { Bad_Opcode },
5685     { Bad_Opcode },
5686     { Bad_Opcode },
5687     { Bad_Opcode },
5688     /* a0 */
5689     { Bad_Opcode },
5690     { Bad_Opcode },
5691     { Bad_Opcode },
5692     { Bad_Opcode },
5693     { Bad_Opcode },
5694     { Bad_Opcode },
5695     { Bad_Opcode },
5696     { Bad_Opcode },
5697     /* a8 */
5698     { Bad_Opcode },
5699     { Bad_Opcode },
5700     { Bad_Opcode },
5701     { Bad_Opcode },
5702     { Bad_Opcode },
5703     { Bad_Opcode },
5704     { Bad_Opcode },
5705     { Bad_Opcode },
5706     /* b0 */
5707     { Bad_Opcode },
5708     { Bad_Opcode },
5709     { Bad_Opcode },
5710     { Bad_Opcode },
5711     { Bad_Opcode },
5712     { Bad_Opcode },
5713     { Bad_Opcode },
5714     { Bad_Opcode },
5715     /* b8 */
5716     { Bad_Opcode },
5717     { Bad_Opcode },
5718     { Bad_Opcode },
5719     { Bad_Opcode },
5720     { Bad_Opcode },
5721     { Bad_Opcode },
5722     { Bad_Opcode },
5723     { Bad_Opcode },
5724     /* c0 */
5725     { Bad_Opcode },
5726     { Bad_Opcode },
5727     { Bad_Opcode },
5728     { Bad_Opcode },
5729     { Bad_Opcode },
5730     { Bad_Opcode },
5731     { Bad_Opcode },
5732     { Bad_Opcode },
5733     /* c8 */
5734     { Bad_Opcode },
5735     { Bad_Opcode },
5736     { Bad_Opcode },
5737     { Bad_Opcode },
5738     { Bad_Opcode },
5739     { Bad_Opcode },
5740     { Bad_Opcode },
5741     { Bad_Opcode },
5742     /* d0 */
5743     { Bad_Opcode },
5744     { Bad_Opcode },
5745     { Bad_Opcode },
5746     { Bad_Opcode },
5747     { Bad_Opcode },
5748     { Bad_Opcode },
5749     { Bad_Opcode },
5750     { Bad_Opcode },
5751     /* d8 */
5752     { Bad_Opcode },
5753     { Bad_Opcode },
5754     { Bad_Opcode },
5755     { Bad_Opcode },
5756     { Bad_Opcode },
5757     { Bad_Opcode },
5758     { Bad_Opcode },
5759     { Bad_Opcode },
5760     /* e0 */
5761     { Bad_Opcode },
5762     { Bad_Opcode },
5763     { Bad_Opcode },
5764     { Bad_Opcode },
5765     { Bad_Opcode },
5766     { Bad_Opcode },
5767     { Bad_Opcode },
5768     { Bad_Opcode },
5769     /* e8 */
5770     { Bad_Opcode },
5771     { Bad_Opcode },
5772     { Bad_Opcode },
5773     { Bad_Opcode },
5774     { Bad_Opcode },
5775     { Bad_Opcode },
5776     { Bad_Opcode },
5777     { Bad_Opcode },
5778     /* f0 */
5779     { Bad_Opcode },
5780     { Bad_Opcode },
5781     { Bad_Opcode },
5782     { Bad_Opcode },
5783     { Bad_Opcode },
5784     { Bad_Opcode },
5785     { Bad_Opcode },
5786     { Bad_Opcode },
5787     /* f8 */
5788     { Bad_Opcode },
5789     { Bad_Opcode },
5790     { Bad_Opcode },
5791     { Bad_Opcode },
5792     { Bad_Opcode },
5793     { Bad_Opcode },
5794     { Bad_Opcode },
5795     { Bad_Opcode },
5796   },
5797 };
5798
5799 static const struct dis386 vex_table[][256] = {
5800   /* VEX_0F */
5801   {
5802     /* 00 */
5803     { Bad_Opcode },
5804     { Bad_Opcode },
5805     { Bad_Opcode },
5806     { Bad_Opcode },
5807     { Bad_Opcode },
5808     { Bad_Opcode },
5809     { Bad_Opcode },
5810     { Bad_Opcode },
5811     /* 08 */
5812     { Bad_Opcode },
5813     { Bad_Opcode },
5814     { Bad_Opcode },
5815     { Bad_Opcode },
5816     { Bad_Opcode },
5817     { Bad_Opcode },
5818     { Bad_Opcode },
5819     { Bad_Opcode },
5820     /* 10 */
5821     { PREFIX_TABLE (PREFIX_VEX_0F10) },
5822     { PREFIX_TABLE (PREFIX_VEX_0F11) },
5823     { PREFIX_TABLE (PREFIX_VEX_0F12) },
5824     { MOD_TABLE (MOD_VEX_0F13) },
5825     { "vunpcklpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
5826     { "vunpckhpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
5827     { PREFIX_TABLE (PREFIX_VEX_0F16) },
5828     { MOD_TABLE (MOD_VEX_0F17) },
5829     /* 18 */
5830     { Bad_Opcode },
5831     { Bad_Opcode },
5832     { Bad_Opcode },
5833     { Bad_Opcode },
5834     { Bad_Opcode },
5835     { Bad_Opcode },
5836     { Bad_Opcode },
5837     { Bad_Opcode },
5838     /* 20 */
5839     { Bad_Opcode },
5840     { Bad_Opcode },
5841     { Bad_Opcode },
5842     { Bad_Opcode },
5843     { Bad_Opcode },
5844     { Bad_Opcode },
5845     { Bad_Opcode },
5846     { Bad_Opcode },
5847     /* 28 */
5848     { "vmovapX",        { XM, EXx }, PREFIX_OPCODE },
5849     { "vmovapX",        { EXxS, XM }, PREFIX_OPCODE },
5850     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
5851     { MOD_TABLE (MOD_VEX_0F2B) },
5852     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
5853     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
5854     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
5855     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
5856     /* 30 */
5857     { Bad_Opcode },
5858     { Bad_Opcode },
5859     { Bad_Opcode },
5860     { Bad_Opcode },
5861     { Bad_Opcode },
5862     { Bad_Opcode },
5863     { Bad_Opcode },
5864     { Bad_Opcode },
5865     /* 38 */
5866     { Bad_Opcode },
5867     { Bad_Opcode },
5868     { Bad_Opcode },
5869     { Bad_Opcode },
5870     { Bad_Opcode },
5871     { Bad_Opcode },
5872     { Bad_Opcode },
5873     { Bad_Opcode },
5874     /* 40 */
5875     { Bad_Opcode },
5876     { VEX_LEN_TABLE (VEX_LEN_0F41) },
5877     { VEX_LEN_TABLE (VEX_LEN_0F42) },
5878     { Bad_Opcode },
5879     { VEX_LEN_TABLE (VEX_LEN_0F44) },
5880     { VEX_LEN_TABLE (VEX_LEN_0F45) },
5881     { VEX_LEN_TABLE (VEX_LEN_0F46) },
5882     { VEX_LEN_TABLE (VEX_LEN_0F47) },
5883     /* 48 */
5884     { Bad_Opcode },
5885     { Bad_Opcode },
5886     { VEX_LEN_TABLE (VEX_LEN_0F4A) },
5887     { VEX_LEN_TABLE (VEX_LEN_0F4B) },
5888     { Bad_Opcode },
5889     { Bad_Opcode },
5890     { Bad_Opcode },
5891     { Bad_Opcode },
5892     /* 50 */
5893     { MOD_TABLE (MOD_VEX_0F50) },
5894     { PREFIX_TABLE (PREFIX_VEX_0F51) },
5895     { PREFIX_TABLE (PREFIX_VEX_0F52) },
5896     { PREFIX_TABLE (PREFIX_VEX_0F53) },
5897     { "vandpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
5898     { "vandnpX",        { XM, Vex, EXx }, PREFIX_OPCODE },
5899     { "vorpX",          { XM, Vex, EXx }, PREFIX_OPCODE },
5900     { "vxorpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
5901     /* 58 */
5902     { PREFIX_TABLE (PREFIX_VEX_0F58) },
5903     { PREFIX_TABLE (PREFIX_VEX_0F59) },
5904     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
5905     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
5906     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
5907     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
5908     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
5909     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
5910     /* 60 */
5911     { "vpunpcklbw",     { XM, Vex, EXx }, PREFIX_DATA },
5912     { "vpunpcklwd",     { XM, Vex, EXx }, PREFIX_DATA },
5913     { "vpunpckldq",     { XM, Vex, EXx }, PREFIX_DATA },
5914     { "vpacksswb",      { XM, Vex, EXx }, PREFIX_DATA },
5915     { "vpcmpgtb",       { XM, Vex, EXx }, PREFIX_DATA },
5916     { "vpcmpgtw",       { XM, Vex, EXx }, PREFIX_DATA },
5917     { "vpcmpgtd",       { XM, Vex, EXx }, PREFIX_DATA },
5918     { "vpackuswb",      { XM, Vex, EXx }, PREFIX_DATA },
5919     /* 68 */
5920     { "vpunpckhbw",     { XM, Vex, EXx }, PREFIX_DATA },
5921     { "vpunpckhwd",     { XM, Vex, EXx }, PREFIX_DATA },
5922     { "vpunpckhdq",     { XM, Vex, EXx }, PREFIX_DATA },
5923     { "vpackssdw",      { XM, Vex, EXx }, PREFIX_DATA },
5924     { "vpunpcklqdq",    { XM, Vex, EXx }, PREFIX_DATA },
5925     { "vpunpckhqdq",    { XM, Vex, EXx }, PREFIX_DATA },
5926     { VEX_LEN_TABLE (VEX_LEN_0F6E) },
5927     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
5928     /* 70 */
5929     { PREFIX_TABLE (PREFIX_VEX_0F70) },
5930     { MOD_TABLE (MOD_VEX_0F71) },
5931     { MOD_TABLE (MOD_VEX_0F72) },
5932     { MOD_TABLE (MOD_VEX_0F73) },
5933     { "vpcmpeqb",       { XM, Vex, EXx }, PREFIX_DATA },
5934     { "vpcmpeqw",       { XM, Vex, EXx }, PREFIX_DATA },
5935     { "vpcmpeqd",       { XM, Vex, EXx }, PREFIX_DATA },
5936     { VEX_LEN_TABLE (VEX_LEN_0F77) },
5937     /* 78 */
5938     { Bad_Opcode },
5939     { Bad_Opcode },
5940     { Bad_Opcode },
5941     { Bad_Opcode },
5942     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
5943     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
5944     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
5945     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
5946     /* 80 */
5947     { Bad_Opcode },
5948     { Bad_Opcode },
5949     { Bad_Opcode },
5950     { Bad_Opcode },
5951     { Bad_Opcode },
5952     { Bad_Opcode },
5953     { Bad_Opcode },
5954     { Bad_Opcode },
5955     /* 88 */
5956     { Bad_Opcode },
5957     { Bad_Opcode },
5958     { Bad_Opcode },
5959     { Bad_Opcode },
5960     { Bad_Opcode },
5961     { Bad_Opcode },
5962     { Bad_Opcode },
5963     { Bad_Opcode },
5964     /* 90 */
5965     { VEX_LEN_TABLE (VEX_LEN_0F90) },
5966     { VEX_LEN_TABLE (VEX_LEN_0F91) },
5967     { VEX_LEN_TABLE (VEX_LEN_0F92) },
5968     { VEX_LEN_TABLE (VEX_LEN_0F93) },
5969     { Bad_Opcode },
5970     { Bad_Opcode },
5971     { Bad_Opcode },
5972     { Bad_Opcode },
5973     /* 98 */
5974     { VEX_LEN_TABLE (VEX_LEN_0F98) },
5975     { VEX_LEN_TABLE (VEX_LEN_0F99) },
5976     { Bad_Opcode },
5977     { Bad_Opcode },
5978     { Bad_Opcode },
5979     { Bad_Opcode },
5980     { Bad_Opcode },
5981     { Bad_Opcode },
5982     /* a0 */
5983     { Bad_Opcode },
5984     { Bad_Opcode },
5985     { Bad_Opcode },
5986     { Bad_Opcode },
5987     { Bad_Opcode },
5988     { Bad_Opcode },
5989     { Bad_Opcode },
5990     { Bad_Opcode },
5991     /* a8 */
5992     { Bad_Opcode },
5993     { Bad_Opcode },
5994     { Bad_Opcode },
5995     { Bad_Opcode },
5996     { Bad_Opcode },
5997     { Bad_Opcode },
5998     { REG_TABLE (REG_VEX_0FAE) },
5999     { Bad_Opcode },
6000     /* b0 */
6001     { Bad_Opcode },
6002     { Bad_Opcode },
6003     { Bad_Opcode },
6004     { Bad_Opcode },
6005     { Bad_Opcode },
6006     { Bad_Opcode },
6007     { Bad_Opcode },
6008     { Bad_Opcode },
6009     /* b8 */
6010     { Bad_Opcode },
6011     { Bad_Opcode },
6012     { Bad_Opcode },
6013     { Bad_Opcode },
6014     { Bad_Opcode },
6015     { Bad_Opcode },
6016     { Bad_Opcode },
6017     { Bad_Opcode },
6018     /* c0 */
6019     { Bad_Opcode },
6020     { Bad_Opcode },
6021     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
6022     { Bad_Opcode },
6023     { VEX_LEN_TABLE (VEX_LEN_0FC4) },
6024     { VEX_LEN_TABLE (VEX_LEN_0FC5) },
6025     { "vshufpX",        { XM, Vex, EXx, Ib }, PREFIX_OPCODE },
6026     { Bad_Opcode },
6027     /* c8 */
6028     { Bad_Opcode },
6029     { Bad_Opcode },
6030     { Bad_Opcode },
6031     { Bad_Opcode },
6032     { Bad_Opcode },
6033     { Bad_Opcode },
6034     { Bad_Opcode },
6035     { Bad_Opcode },
6036     /* d0 */
6037     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
6038     { "vpsrlw",         { XM, Vex, EXxmm }, PREFIX_DATA },
6039     { "vpsrld",         { XM, Vex, EXxmm }, PREFIX_DATA },
6040     { "vpsrlq",         { XM, Vex, EXxmm }, PREFIX_DATA },
6041     { "vpaddq",         { XM, Vex, EXx }, PREFIX_DATA },
6042     { "vpmullw",        { XM, Vex, EXx }, PREFIX_DATA },
6043     { VEX_LEN_TABLE (VEX_LEN_0FD6) },
6044     { MOD_TABLE (MOD_VEX_0FD7) },
6045     /* d8 */
6046     { "vpsubusb",       { XM, Vex, EXx }, PREFIX_DATA },
6047     { "vpsubusw",       { XM, Vex, EXx }, PREFIX_DATA },
6048     { "vpminub",        { XM, Vex, EXx }, PREFIX_DATA },
6049     { "vpand",          { XM, Vex, EXx }, PREFIX_DATA },
6050     { "vpaddusb",       { XM, Vex, EXx }, PREFIX_DATA },
6051     { "vpaddusw",       { XM, Vex, EXx }, PREFIX_DATA },
6052     { "vpmaxub",        { XM, Vex, EXx }, PREFIX_DATA },
6053     { "vpandn",         { XM, Vex, EXx }, PREFIX_DATA },
6054     /* e0 */
6055     { "vpavgb",         { XM, Vex, EXx }, PREFIX_DATA },
6056     { "vpsraw",         { XM, Vex, EXxmm }, PREFIX_DATA },
6057     { "vpsrad",         { XM, Vex, EXxmm }, PREFIX_DATA },
6058     { "vpavgw",         { XM, Vex, EXx }, PREFIX_DATA },
6059     { "vpmulhuw",       { XM, Vex, EXx }, PREFIX_DATA },
6060     { "vpmulhw",        { XM, Vex, EXx }, PREFIX_DATA },
6061     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
6062     { MOD_TABLE (MOD_VEX_0FE7) },
6063     /* e8 */
6064     { "vpsubsb",        { XM, Vex, EXx }, PREFIX_DATA },
6065     { "vpsubsw",        { XM, Vex, EXx }, PREFIX_DATA },
6066     { "vpminsw",        { XM, Vex, EXx }, PREFIX_DATA },
6067     { "vpor",           { XM, Vex, EXx }, PREFIX_DATA },
6068     { "vpaddsb",        { XM, Vex, EXx }, PREFIX_DATA },
6069     { "vpaddsw",        { XM, Vex, EXx }, PREFIX_DATA },
6070     { "vpmaxsw",        { XM, Vex, EXx }, PREFIX_DATA },
6071     { "vpxor",          { XM, Vex, EXx }, PREFIX_DATA },
6072     /* f0 */
6073     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
6074     { "vpsllw",         { XM, Vex, EXxmm }, PREFIX_DATA },
6075     { "vpslld",         { XM, Vex, EXxmm }, PREFIX_DATA },
6076     { "vpsllq",         { XM, Vex, EXxmm }, PREFIX_DATA },
6077     { "vpmuludq",       { XM, Vex, EXx }, PREFIX_DATA },
6078     { "vpmaddwd",       { XM, Vex, EXx }, PREFIX_DATA },
6079     { "vpsadbw",        { XM, Vex, EXx }, PREFIX_DATA },
6080     { VEX_LEN_TABLE (VEX_LEN_0FF7) },
6081     /* f8 */
6082     { "vpsubb",         { XM, Vex, EXx }, PREFIX_DATA },
6083     { "vpsubw",         { XM, Vex, EXx }, PREFIX_DATA },
6084     { "vpsubd",         { XM, Vex, EXx }, PREFIX_DATA },
6085     { "vpsubq",         { XM, Vex, EXx }, PREFIX_DATA },
6086     { "vpaddb",         { XM, Vex, EXx }, PREFIX_DATA },
6087     { "vpaddw",         { XM, Vex, EXx }, PREFIX_DATA },
6088     { "vpaddd",         { XM, Vex, EXx }, PREFIX_DATA },
6089     { Bad_Opcode },
6090   },
6091   /* VEX_0F38 */
6092   {
6093     /* 00 */
6094     { "vpshufb",        { XM, Vex, EXx }, PREFIX_DATA },
6095     { "vphaddw",        { XM, Vex, EXx }, PREFIX_DATA },
6096     { "vphaddd",        { XM, Vex, EXx }, PREFIX_DATA },
6097     { "vphaddsw",       { XM, Vex, EXx }, PREFIX_DATA },
6098     { "vpmaddubsw",     { XM, Vex, EXx }, PREFIX_DATA },
6099     { "vphsubw",        { XM, Vex, EXx }, PREFIX_DATA },
6100     { "vphsubd",        { XM, Vex, EXx }, PREFIX_DATA },
6101     { "vphsubsw",       { XM, Vex, EXx }, PREFIX_DATA },
6102     /* 08 */
6103     { "vpsignb",        { XM, Vex, EXx }, PREFIX_DATA },
6104     { "vpsignw",        { XM, Vex, EXx }, PREFIX_DATA },
6105     { "vpsignd",        { XM, Vex, EXx }, PREFIX_DATA },
6106     { "vpmulhrsw",      { XM, Vex, EXx }, PREFIX_DATA },
6107     { VEX_W_TABLE (VEX_W_0F380C) },
6108     { VEX_W_TABLE (VEX_W_0F380D) },
6109     { VEX_W_TABLE (VEX_W_0F380E) },
6110     { VEX_W_TABLE (VEX_W_0F380F) },
6111     /* 10 */
6112     { Bad_Opcode },
6113     { Bad_Opcode },
6114     { Bad_Opcode },
6115     { VEX_W_TABLE (VEX_W_0F3813) },
6116     { Bad_Opcode },
6117     { Bad_Opcode },
6118     { VEX_LEN_TABLE (VEX_LEN_0F3816) },
6119     { "vptest",         { XM, EXx }, PREFIX_DATA },
6120     /* 18 */
6121     { VEX_W_TABLE (VEX_W_0F3818) },
6122     { VEX_LEN_TABLE (VEX_LEN_0F3819) },
6123     { MOD_TABLE (MOD_VEX_0F381A) },
6124     { Bad_Opcode },
6125     { "vpabsb",         { XM, EXx }, PREFIX_DATA },
6126     { "vpabsw",         { XM, EXx }, PREFIX_DATA },
6127     { "vpabsd",         { XM, EXx }, PREFIX_DATA },
6128     { Bad_Opcode },
6129     /* 20 */
6130     { "vpmovsxbw",      { XM, EXxmmq }, PREFIX_DATA },
6131     { "vpmovsxbd",      { XM, EXxmmqd }, PREFIX_DATA },
6132     { "vpmovsxbq",      { XM, EXxmmdw }, PREFIX_DATA },
6133     { "vpmovsxwd",      { XM, EXxmmq }, PREFIX_DATA },
6134     { "vpmovsxwq",      { XM, EXxmmqd }, PREFIX_DATA },
6135     { "vpmovsxdq",      { XM, EXxmmq }, PREFIX_DATA },
6136     { Bad_Opcode },
6137     { Bad_Opcode },
6138     /* 28 */
6139     { "vpmuldq",        { XM, Vex, EXx }, PREFIX_DATA },
6140     { "vpcmpeqq",       { XM, Vex, EXx }, PREFIX_DATA },
6141     { MOD_TABLE (MOD_VEX_0F382A) },
6142     { "vpackusdw",      { XM, Vex, EXx }, PREFIX_DATA },
6143     { MOD_TABLE (MOD_VEX_0F382C) },
6144     { MOD_TABLE (MOD_VEX_0F382D) },
6145     { MOD_TABLE (MOD_VEX_0F382E) },
6146     { MOD_TABLE (MOD_VEX_0F382F) },
6147     /* 30 */
6148     { "vpmovzxbw",      { XM, EXxmmq }, PREFIX_DATA },
6149     { "vpmovzxbd",      { XM, EXxmmqd }, PREFIX_DATA },
6150     { "vpmovzxbq",      { XM, EXxmmdw }, PREFIX_DATA },
6151     { "vpmovzxwd",      { XM, EXxmmq }, PREFIX_DATA },
6152     { "vpmovzxwq",      { XM, EXxmmqd }, PREFIX_DATA },
6153     { "vpmovzxdq",      { XM, EXxmmq }, PREFIX_DATA },
6154     { VEX_LEN_TABLE (VEX_LEN_0F3836) },
6155     { "vpcmpgtq",       { XM, Vex, EXx }, PREFIX_DATA },
6156     /* 38 */
6157     { "vpminsb",        { XM, Vex, EXx }, PREFIX_DATA },
6158     { "vpminsd",        { XM, Vex, EXx }, PREFIX_DATA },
6159     { "vpminuw",        { XM, Vex, EXx }, PREFIX_DATA },
6160     { "vpminud",        { XM, Vex, EXx }, PREFIX_DATA },
6161     { "vpmaxsb",        { XM, Vex, EXx }, PREFIX_DATA },
6162     { "vpmaxsd",        { XM, Vex, EXx }, PREFIX_DATA },
6163     { "vpmaxuw",        { XM, Vex, EXx }, PREFIX_DATA },
6164     { "vpmaxud",        { XM, Vex, EXx }, PREFIX_DATA },
6165     /* 40 */
6166     { "vpmulld",        { XM, Vex, EXx }, PREFIX_DATA },
6167     { VEX_LEN_TABLE (VEX_LEN_0F3841) },
6168     { Bad_Opcode },
6169     { Bad_Opcode },
6170     { Bad_Opcode },
6171     { "vpsrlv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6172     { VEX_W_TABLE (VEX_W_0F3846) },
6173     { "vpsllv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6174     /* 48 */
6175     { Bad_Opcode },
6176     { X86_64_TABLE (X86_64_VEX_0F3849) },
6177     { Bad_Opcode },
6178     { X86_64_TABLE (X86_64_VEX_0F384B) },
6179     { Bad_Opcode },
6180     { Bad_Opcode },
6181     { Bad_Opcode },
6182     { Bad_Opcode },
6183     /* 50 */
6184     { VEX_W_TABLE (VEX_W_0F3850) },
6185     { VEX_W_TABLE (VEX_W_0F3851) },
6186     { VEX_W_TABLE (VEX_W_0F3852) },
6187     { VEX_W_TABLE (VEX_W_0F3853) },
6188     { Bad_Opcode },
6189     { Bad_Opcode },
6190     { Bad_Opcode },
6191     { Bad_Opcode },
6192     /* 58 */
6193     { VEX_W_TABLE (VEX_W_0F3858) },
6194     { VEX_W_TABLE (VEX_W_0F3859) },
6195     { MOD_TABLE (MOD_VEX_0F385A) },
6196     { Bad_Opcode },
6197     { X86_64_TABLE (X86_64_VEX_0F385C) },
6198     { Bad_Opcode },
6199     { X86_64_TABLE (X86_64_VEX_0F385E) },
6200     { Bad_Opcode },
6201     /* 60 */
6202     { Bad_Opcode },
6203     { Bad_Opcode },
6204     { Bad_Opcode },
6205     { Bad_Opcode },
6206     { Bad_Opcode },
6207     { Bad_Opcode },
6208     { Bad_Opcode },
6209     { Bad_Opcode },
6210     /* 68 */
6211     { Bad_Opcode },
6212     { Bad_Opcode },
6213     { Bad_Opcode },
6214     { Bad_Opcode },
6215     { Bad_Opcode },
6216     { Bad_Opcode },
6217     { Bad_Opcode },
6218     { Bad_Opcode },
6219     /* 70 */
6220     { Bad_Opcode },
6221     { Bad_Opcode },
6222     { Bad_Opcode },
6223     { Bad_Opcode },
6224     { Bad_Opcode },
6225     { Bad_Opcode },
6226     { Bad_Opcode },
6227     { Bad_Opcode },
6228     /* 78 */
6229     { VEX_W_TABLE (VEX_W_0F3878) },
6230     { VEX_W_TABLE (VEX_W_0F3879) },
6231     { Bad_Opcode },
6232     { Bad_Opcode },
6233     { Bad_Opcode },
6234     { Bad_Opcode },
6235     { Bad_Opcode },
6236     { Bad_Opcode },
6237     /* 80 */
6238     { Bad_Opcode },
6239     { Bad_Opcode },
6240     { Bad_Opcode },
6241     { Bad_Opcode },
6242     { Bad_Opcode },
6243     { Bad_Opcode },
6244     { Bad_Opcode },
6245     { Bad_Opcode },
6246     /* 88 */
6247     { Bad_Opcode },
6248     { Bad_Opcode },
6249     { Bad_Opcode },
6250     { Bad_Opcode },
6251     { MOD_TABLE (MOD_VEX_0F388C) },
6252     { Bad_Opcode },
6253     { MOD_TABLE (MOD_VEX_0F388E) },
6254     { Bad_Opcode },
6255     /* 90 */
6256     { "vpgatherd%DQ", { XM, MVexVSIBDWpX, VexGatherD }, PREFIX_DATA },
6257     { "vpgatherq%DQ", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6258     { "vgatherdp%XW", { XM, MVexVSIBDWpX, VexGatherD }, PREFIX_DATA },
6259     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6260     { Bad_Opcode },
6261     { Bad_Opcode },
6262     { "vfmaddsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6263     { "vfmsubadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6264     /* 98 */
6265     { "vfmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6266     { "vfmadd132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6267     { "vfmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6268     { "vfmsub132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6269     { "vfnmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6270     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6271     { "vfnmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6272     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6273     /* a0 */
6274     { Bad_Opcode },
6275     { Bad_Opcode },
6276     { Bad_Opcode },
6277     { Bad_Opcode },
6278     { Bad_Opcode },
6279     { Bad_Opcode },
6280     { "vfmaddsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6281     { "vfmsubadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6282     /* a8 */
6283     { "vfmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6284     { "vfmadd213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6285     { "vfmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6286     { "vfmsub213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6287     { "vfnmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6288     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6289     { "vfnmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6290     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6291     /* b0 */
6292     { Bad_Opcode },
6293     { Bad_Opcode },
6294     { Bad_Opcode },
6295     { Bad_Opcode },
6296     { Bad_Opcode },
6297     { Bad_Opcode },
6298     { "vfmaddsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6299     { "vfmsubadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6300     /* b8 */
6301     { "vfmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6302     { "vfmadd231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6303     { "vfmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6304     { "vfmsub231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6305     { "vfnmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6306     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6307     { "vfnmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6308     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6309     /* c0 */
6310     { Bad_Opcode },
6311     { Bad_Opcode },
6312     { Bad_Opcode },
6313     { Bad_Opcode },
6314     { Bad_Opcode },
6315     { Bad_Opcode },
6316     { Bad_Opcode },
6317     { Bad_Opcode },
6318     /* c8 */
6319     { Bad_Opcode },
6320     { Bad_Opcode },
6321     { Bad_Opcode },
6322     { Bad_Opcode },
6323     { Bad_Opcode },
6324     { Bad_Opcode },
6325     { Bad_Opcode },
6326     { VEX_W_TABLE (VEX_W_0F38CF) },
6327     /* d0 */
6328     { Bad_Opcode },
6329     { Bad_Opcode },
6330     { Bad_Opcode },
6331     { Bad_Opcode },
6332     { Bad_Opcode },
6333     { Bad_Opcode },
6334     { Bad_Opcode },
6335     { Bad_Opcode },
6336     /* d8 */
6337     { Bad_Opcode },
6338     { Bad_Opcode },
6339     { Bad_Opcode },
6340     { VEX_LEN_TABLE (VEX_LEN_0F38DB) },
6341     { "vaesenc",        { XM, Vex, EXx }, PREFIX_DATA },
6342     { "vaesenclast",    { XM, Vex, EXx }, PREFIX_DATA },
6343     { "vaesdec",        { XM, Vex, EXx }, PREFIX_DATA },
6344     { "vaesdeclast",    { XM, Vex, EXx }, PREFIX_DATA },
6345     /* e0 */
6346     { Bad_Opcode },
6347     { Bad_Opcode },
6348     { Bad_Opcode },
6349     { Bad_Opcode },
6350     { Bad_Opcode },
6351     { Bad_Opcode },
6352     { Bad_Opcode },
6353     { Bad_Opcode },
6354     /* e8 */
6355     { Bad_Opcode },
6356     { Bad_Opcode },
6357     { Bad_Opcode },
6358     { Bad_Opcode },
6359     { Bad_Opcode },
6360     { Bad_Opcode },
6361     { Bad_Opcode },
6362     { Bad_Opcode },
6363     /* f0 */
6364     { Bad_Opcode },
6365     { Bad_Opcode },
6366     { VEX_LEN_TABLE (VEX_LEN_0F38F2) },
6367     { VEX_LEN_TABLE (VEX_LEN_0F38F3) },
6368     { Bad_Opcode },
6369     { VEX_LEN_TABLE (VEX_LEN_0F38F5) },
6370     { VEX_LEN_TABLE (VEX_LEN_0F38F6) },
6371     { VEX_LEN_TABLE (VEX_LEN_0F38F7) },
6372     /* f8 */
6373     { Bad_Opcode },
6374     { Bad_Opcode },
6375     { Bad_Opcode },
6376     { Bad_Opcode },
6377     { Bad_Opcode },
6378     { Bad_Opcode },
6379     { Bad_Opcode },
6380     { Bad_Opcode },
6381   },
6382   /* VEX_0F3A */
6383   {
6384     /* 00 */
6385     { VEX_LEN_TABLE (VEX_LEN_0F3A00) },
6386     { VEX_LEN_TABLE (VEX_LEN_0F3A01) },
6387     { VEX_W_TABLE (VEX_W_0F3A02) },
6388     { Bad_Opcode },
6389     { VEX_W_TABLE (VEX_W_0F3A04) },
6390     { VEX_W_TABLE (VEX_W_0F3A05) },
6391     { VEX_LEN_TABLE (VEX_LEN_0F3A06) },
6392     { Bad_Opcode },
6393     /* 08 */
6394     { "vroundps",       { XM, EXx, Ib }, PREFIX_DATA },
6395     { "vroundpd",       { XM, EXx, Ib }, PREFIX_DATA },
6396     { "vroundss",       { XMScalar, VexScalar, EXd, Ib }, PREFIX_DATA },
6397     { "vroundsd",       { XMScalar, VexScalar, EXq, Ib }, PREFIX_DATA },
6398     { "vblendps",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6399     { "vblendpd",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6400     { "vpblendw",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6401     { "vpalignr",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6402     /* 10 */
6403     { Bad_Opcode },
6404     { Bad_Opcode },
6405     { Bad_Opcode },
6406     { Bad_Opcode },
6407     { VEX_LEN_TABLE (VEX_LEN_0F3A14) },
6408     { VEX_LEN_TABLE (VEX_LEN_0F3A15) },
6409     { VEX_LEN_TABLE (VEX_LEN_0F3A16) },
6410     { VEX_LEN_TABLE (VEX_LEN_0F3A17) },
6411     /* 18 */
6412     { VEX_LEN_TABLE (VEX_LEN_0F3A18) },
6413     { VEX_LEN_TABLE (VEX_LEN_0F3A19) },
6414     { Bad_Opcode },
6415     { Bad_Opcode },
6416     { Bad_Opcode },
6417     { VEX_W_TABLE (VEX_W_0F3A1D) },
6418     { Bad_Opcode },
6419     { Bad_Opcode },
6420     /* 20 */
6421     { VEX_LEN_TABLE (VEX_LEN_0F3A20) },
6422     { VEX_LEN_TABLE (VEX_LEN_0F3A21) },
6423     { VEX_LEN_TABLE (VEX_LEN_0F3A22) },
6424     { Bad_Opcode },
6425     { Bad_Opcode },
6426     { Bad_Opcode },
6427     { Bad_Opcode },
6428     { Bad_Opcode },
6429     /* 28 */
6430     { Bad_Opcode },
6431     { Bad_Opcode },
6432     { Bad_Opcode },
6433     { Bad_Opcode },
6434     { Bad_Opcode },
6435     { Bad_Opcode },
6436     { Bad_Opcode },
6437     { Bad_Opcode },
6438     /* 30 */
6439     { VEX_LEN_TABLE (VEX_LEN_0F3A30) },
6440     { VEX_LEN_TABLE (VEX_LEN_0F3A31) },
6441     { VEX_LEN_TABLE (VEX_LEN_0F3A32) },
6442     { VEX_LEN_TABLE (VEX_LEN_0F3A33) },
6443     { Bad_Opcode },
6444     { Bad_Opcode },
6445     { Bad_Opcode },
6446     { Bad_Opcode },
6447     /* 38 */
6448     { VEX_LEN_TABLE (VEX_LEN_0F3A38) },
6449     { VEX_LEN_TABLE (VEX_LEN_0F3A39) },
6450     { Bad_Opcode },
6451     { Bad_Opcode },
6452     { Bad_Opcode },
6453     { Bad_Opcode },
6454     { Bad_Opcode },
6455     { Bad_Opcode },
6456     /* 40 */
6457     { "vdpps",          { XM, Vex, EXx, Ib }, PREFIX_DATA },
6458     { VEX_LEN_TABLE (VEX_LEN_0F3A41) },
6459     { "vmpsadbw",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6460     { Bad_Opcode },
6461     { "vpclmulqdq",     { XM, Vex, EXx, PCLMUL }, PREFIX_DATA },
6462     { Bad_Opcode },
6463     { VEX_LEN_TABLE (VEX_LEN_0F3A46) },
6464     { Bad_Opcode },
6465     /* 48 */
6466     { "vpermil2ps",     { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6467     { "vpermil2pd",     { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6468     { VEX_W_TABLE (VEX_W_0F3A4A) },
6469     { VEX_W_TABLE (VEX_W_0F3A4B) },
6470     { VEX_W_TABLE (VEX_W_0F3A4C) },
6471     { Bad_Opcode },
6472     { Bad_Opcode },
6473     { Bad_Opcode },
6474     /* 50 */
6475     { Bad_Opcode },
6476     { Bad_Opcode },
6477     { Bad_Opcode },
6478     { Bad_Opcode },
6479     { Bad_Opcode },
6480     { Bad_Opcode },
6481     { Bad_Opcode },
6482     { Bad_Opcode },
6483     /* 58 */
6484     { Bad_Opcode },
6485     { Bad_Opcode },
6486     { Bad_Opcode },
6487     { Bad_Opcode },
6488     { "vfmaddsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6489     { "vfmaddsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6490     { "vfmsubaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6491     { "vfmsubaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6492     /* 60 */
6493     { VEX_LEN_TABLE (VEX_LEN_0F3A60) },
6494     { VEX_LEN_TABLE (VEX_LEN_0F3A61) },
6495     { VEX_LEN_TABLE (VEX_LEN_0F3A62) },
6496     { VEX_LEN_TABLE (VEX_LEN_0F3A63) },
6497     { Bad_Opcode },
6498     { Bad_Opcode },
6499     { Bad_Opcode },
6500     { Bad_Opcode },
6501     /* 68 */
6502     { "vfmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6503     { "vfmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6504     { "vfmaddss",       { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6505     { "vfmaddsd",       { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6506     { "vfmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6507     { "vfmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6508     { "vfmsubss",       { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6509     { "vfmsubsd",       { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6510     /* 70 */
6511     { Bad_Opcode },
6512     { Bad_Opcode },
6513     { Bad_Opcode },
6514     { Bad_Opcode },
6515     { Bad_Opcode },
6516     { Bad_Opcode },
6517     { Bad_Opcode },
6518     { Bad_Opcode },
6519     /* 78 */
6520     { "vfnmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6521     { "vfnmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6522     { "vfnmaddss",      { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6523     { "vfnmaddsd",      { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6524     { "vfnmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6525     { "vfnmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6526     { "vfnmsubss",      { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6527     { "vfnmsubsd",      { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6528     /* 80 */
6529     { Bad_Opcode },
6530     { Bad_Opcode },
6531     { Bad_Opcode },
6532     { Bad_Opcode },
6533     { Bad_Opcode },
6534     { Bad_Opcode },
6535     { Bad_Opcode },
6536     { Bad_Opcode },
6537     /* 88 */
6538     { Bad_Opcode },
6539     { Bad_Opcode },
6540     { Bad_Opcode },
6541     { Bad_Opcode },
6542     { Bad_Opcode },
6543     { Bad_Opcode },
6544     { Bad_Opcode },
6545     { Bad_Opcode },
6546     /* 90 */
6547     { Bad_Opcode },
6548     { Bad_Opcode },
6549     { Bad_Opcode },
6550     { Bad_Opcode },
6551     { Bad_Opcode },
6552     { Bad_Opcode },
6553     { Bad_Opcode },
6554     { Bad_Opcode },
6555     /* 98 */
6556     { Bad_Opcode },
6557     { Bad_Opcode },
6558     { Bad_Opcode },
6559     { Bad_Opcode },
6560     { Bad_Opcode },
6561     { Bad_Opcode },
6562     { Bad_Opcode },
6563     { Bad_Opcode },
6564     /* a0 */
6565     { Bad_Opcode },
6566     { Bad_Opcode },
6567     { Bad_Opcode },
6568     { Bad_Opcode },
6569     { Bad_Opcode },
6570     { Bad_Opcode },
6571     { Bad_Opcode },
6572     { Bad_Opcode },
6573     /* a8 */
6574     { Bad_Opcode },
6575     { Bad_Opcode },
6576     { Bad_Opcode },
6577     { Bad_Opcode },
6578     { Bad_Opcode },
6579     { Bad_Opcode },
6580     { Bad_Opcode },
6581     { Bad_Opcode },
6582     /* b0 */
6583     { Bad_Opcode },
6584     { Bad_Opcode },
6585     { Bad_Opcode },
6586     { Bad_Opcode },
6587     { Bad_Opcode },
6588     { Bad_Opcode },
6589     { Bad_Opcode },
6590     { Bad_Opcode },
6591     /* b8 */
6592     { Bad_Opcode },
6593     { Bad_Opcode },
6594     { Bad_Opcode },
6595     { Bad_Opcode },
6596     { Bad_Opcode },
6597     { Bad_Opcode },
6598     { Bad_Opcode },
6599     { Bad_Opcode },
6600     /* c0 */
6601     { Bad_Opcode },
6602     { Bad_Opcode },
6603     { Bad_Opcode },
6604     { Bad_Opcode },
6605     { Bad_Opcode },
6606     { Bad_Opcode },
6607     { Bad_Opcode },
6608     { Bad_Opcode },
6609     /* c8 */
6610     { Bad_Opcode },
6611     { Bad_Opcode },
6612     { Bad_Opcode },
6613     { Bad_Opcode },
6614     { Bad_Opcode },
6615     { Bad_Opcode },
6616     { VEX_W_TABLE (VEX_W_0F3ACE) },
6617     { VEX_W_TABLE (VEX_W_0F3ACF) },
6618     /* d0 */
6619     { Bad_Opcode },
6620     { Bad_Opcode },
6621     { Bad_Opcode },
6622     { Bad_Opcode },
6623     { Bad_Opcode },
6624     { Bad_Opcode },
6625     { Bad_Opcode },
6626     { Bad_Opcode },
6627     /* d8 */
6628     { Bad_Opcode },
6629     { Bad_Opcode },
6630     { Bad_Opcode },
6631     { Bad_Opcode },
6632     { Bad_Opcode },
6633     { Bad_Opcode },
6634     { Bad_Opcode },
6635     { VEX_LEN_TABLE (VEX_LEN_0F3ADF) },
6636     /* e0 */
6637     { Bad_Opcode },
6638     { Bad_Opcode },
6639     { Bad_Opcode },
6640     { Bad_Opcode },
6641     { Bad_Opcode },
6642     { Bad_Opcode },
6643     { Bad_Opcode },
6644     { Bad_Opcode },
6645     /* e8 */
6646     { Bad_Opcode },
6647     { Bad_Opcode },
6648     { Bad_Opcode },
6649     { Bad_Opcode },
6650     { Bad_Opcode },
6651     { Bad_Opcode },
6652     { Bad_Opcode },
6653     { Bad_Opcode },
6654     /* f0 */
6655     { VEX_LEN_TABLE (VEX_LEN_0F3AF0) },
6656     { Bad_Opcode },
6657     { Bad_Opcode },
6658     { Bad_Opcode },
6659     { Bad_Opcode },
6660     { Bad_Opcode },
6661     { Bad_Opcode },
6662     { Bad_Opcode },
6663     /* f8 */
6664     { Bad_Opcode },
6665     { Bad_Opcode },
6666     { Bad_Opcode },
6667     { Bad_Opcode },
6668     { Bad_Opcode },
6669     { Bad_Opcode },
6670     { Bad_Opcode },
6671     { Bad_Opcode },
6672   },
6673 };
6674
6675 #include "i386-dis-evex.h"
6676
6677 static const struct dis386 vex_len_table[][2] = {
6678   /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */
6679   {
6680     { "vmovlpX",        { XM, Vex, EXq }, PREFIX_OPCODE },
6681   },
6682
6683   /* VEX_LEN_0F12_P_0_M_1 */
6684   {
6685     { "vmovhlp%XS",     { XM, Vex, EXq }, 0 },
6686   },
6687
6688   /* VEX_LEN_0F13_M_0 */
6689   {
6690     { "vmovlpX",        { EXq, XM }, PREFIX_OPCODE },
6691   },
6692
6693   /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */
6694   {
6695     { "vmovhpX",        { XM, Vex, EXq }, PREFIX_OPCODE },
6696   },
6697
6698   /* VEX_LEN_0F16_P_0_M_1 */
6699   {
6700     { "vmovlhp%XS",     { XM, Vex, EXq }, 0 },
6701   },
6702
6703   /* VEX_LEN_0F17_M_0 */
6704   {
6705     { "vmovhpX",        { EXq, XM }, PREFIX_OPCODE },
6706   },
6707
6708   /* VEX_LEN_0F41 */
6709   {
6710     { Bad_Opcode },
6711     { MOD_TABLE (MOD_VEX_0F41_L_1) },
6712   },
6713
6714   /* VEX_LEN_0F42 */
6715   {
6716     { Bad_Opcode },
6717     { MOD_TABLE (MOD_VEX_0F42_L_1) },
6718   },
6719
6720   /* VEX_LEN_0F44 */
6721   {
6722     { MOD_TABLE (MOD_VEX_0F44_L_0) },
6723   },
6724
6725   /* VEX_LEN_0F45 */
6726   {
6727     { Bad_Opcode },
6728     { MOD_TABLE (MOD_VEX_0F45_L_1) },
6729   },
6730
6731   /* VEX_LEN_0F46 */
6732   {
6733     { Bad_Opcode },
6734     { MOD_TABLE (MOD_VEX_0F46_L_1) },
6735   },
6736
6737   /* VEX_LEN_0F47 */
6738   {
6739     { Bad_Opcode },
6740     { MOD_TABLE (MOD_VEX_0F47_L_1) },
6741   },
6742
6743   /* VEX_LEN_0F4A */
6744   {
6745     { Bad_Opcode },
6746     { MOD_TABLE (MOD_VEX_0F4A_L_1) },
6747   },
6748
6749   /* VEX_LEN_0F4B */
6750   {
6751     { Bad_Opcode },
6752     { MOD_TABLE (MOD_VEX_0F4B_L_1) },
6753   },
6754
6755   /* VEX_LEN_0F6E */
6756   {
6757     { "vmovK",          { XMScalar, Edq }, PREFIX_DATA },
6758   },
6759
6760   /* VEX_LEN_0F77 */
6761   {
6762     { "vzeroupper",     { XX }, 0 },
6763     { "vzeroall",       { XX }, 0 },
6764   },
6765
6766   /* VEX_LEN_0F7E_P_1 */
6767   {
6768     { "vmovq",          { XMScalar, EXq }, 0 },
6769   },
6770
6771   /* VEX_LEN_0F7E_P_2 */
6772   {
6773     { "vmovK",          { Edq, XMScalar }, 0 },
6774   },
6775
6776   /* VEX_LEN_0F90 */
6777   {
6778     { VEX_W_TABLE (VEX_W_0F90_L_0) },
6779   },
6780
6781   /* VEX_LEN_0F91 */
6782   {
6783     { MOD_TABLE (MOD_VEX_0F91_L_0) },
6784   },
6785
6786   /* VEX_LEN_0F92 */
6787   {
6788     { MOD_TABLE (MOD_VEX_0F92_L_0) },
6789   },
6790
6791   /* VEX_LEN_0F93 */
6792   {
6793     { MOD_TABLE (MOD_VEX_0F93_L_0) },
6794   },
6795
6796   /* VEX_LEN_0F98 */
6797   {
6798     { MOD_TABLE (MOD_VEX_0F98_L_0) },
6799   },
6800
6801   /* VEX_LEN_0F99 */
6802   {
6803     { MOD_TABLE (MOD_VEX_0F99_L_0) },
6804   },
6805
6806   /* VEX_LEN_0FAE_R_2_M_0 */
6807   {
6808     { "vldmxcsr",       { Md }, 0 },
6809   },
6810
6811   /* VEX_LEN_0FAE_R_3_M_0 */
6812   {
6813     { "vstmxcsr",       { Md }, 0 },
6814   },
6815
6816   /* VEX_LEN_0FC4 */
6817   {
6818     { "vpinsrw",        { XM, Vex, Edw, Ib }, PREFIX_DATA },
6819   },
6820
6821   /* VEX_LEN_0FC5 */
6822   {
6823     { "vpextrw",        { Gd, XS, Ib }, PREFIX_DATA },
6824   },
6825
6826   /* VEX_LEN_0FD6 */
6827   {
6828     { "vmovq",          { EXqS, XMScalar }, PREFIX_DATA },
6829   },
6830
6831   /* VEX_LEN_0FF7 */
6832   {
6833     { "vmaskmovdqu",    { XM, XS }, PREFIX_DATA },
6834   },
6835
6836   /* VEX_LEN_0F3816 */
6837   {
6838     { Bad_Opcode },
6839     { VEX_W_TABLE (VEX_W_0F3816_L_1) },
6840   },
6841
6842   /* VEX_LEN_0F3819 */
6843   {
6844     { Bad_Opcode },
6845     { VEX_W_TABLE (VEX_W_0F3819_L_1) },
6846   },
6847
6848   /* VEX_LEN_0F381A_M_0 */
6849   {
6850     { Bad_Opcode },
6851     { VEX_W_TABLE (VEX_W_0F381A_M_0_L_1) },
6852   },
6853
6854   /* VEX_LEN_0F3836 */
6855   {
6856     { Bad_Opcode },
6857     { VEX_W_TABLE (VEX_W_0F3836) },
6858   },
6859
6860   /* VEX_LEN_0F3841 */
6861   {
6862     { "vphminposuw",    { XM, EXx }, PREFIX_DATA },
6863   },
6864
6865    /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_0 */
6866   {
6867     { "ldtilecfg", { M }, 0 },
6868   },
6869
6870   /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0 */
6871   {
6872     { "tilerelease", { Skip_MODRM }, 0 },
6873   },
6874
6875   /* VEX_LEN_0F3849_X86_64_P_2_W_0_M_0 */
6876   {
6877     { "sttilecfg", { M }, 0 },
6878   },
6879
6880   /* VEX_LEN_0F3849_X86_64_P_3_W_0_M_0 */
6881   {
6882     { "tilezero", { TMM, Skip_MODRM }, 0 },
6883   },
6884
6885   /* VEX_LEN_0F384B_X86_64_P_1_W_0_M_0 */
6886   {
6887     { "tilestored", { MVexSIBMEM, TMM }, 0 },
6888   },
6889   /* VEX_LEN_0F384B_X86_64_P_2_W_0_M_0 */
6890   {
6891     { "tileloaddt1", { TMM, MVexSIBMEM }, 0 },
6892   },
6893
6894   /* VEX_LEN_0F384B_X86_64_P_3_W_0_M_0 */
6895   {
6896     { "tileloadd", { TMM, MVexSIBMEM }, 0 },
6897   },
6898
6899   /* VEX_LEN_0F385A_M_0 */
6900   {
6901     { Bad_Opcode },
6902     { VEX_W_TABLE (VEX_W_0F385A_M_0_L_0) },
6903   },
6904
6905   /* VEX_LEN_0F385C_X86_64_P_1_W_0_M_0 */
6906   {
6907     { "tdpbf16ps", { TMM, EXtmm, VexTmm }, 0 },
6908   },
6909
6910   /* VEX_LEN_0F385E_X86_64_P_0_W_0_M_0 */
6911   {
6912     { "tdpbuud", {TMM, EXtmm, VexTmm }, 0 },
6913   },
6914
6915   /* VEX_LEN_0F385E_X86_64_P_1_W_0_M_0 */
6916   {
6917     { "tdpbsud", {TMM, EXtmm, VexTmm }, 0 },
6918   },
6919
6920   /* VEX_LEN_0F385E_X86_64_P_2_W_0_M_0 */
6921   {
6922     { "tdpbusd", {TMM, EXtmm, VexTmm }, 0 },
6923   },
6924
6925   /* VEX_LEN_0F385E_X86_64_P_3_W_0_M_0 */
6926   {
6927     { "tdpbssd", {TMM, EXtmm, VexTmm }, 0 },
6928   },
6929
6930   /* VEX_LEN_0F38DB */
6931   {
6932     { "vaesimc",        { XM, EXx }, PREFIX_DATA },
6933   },
6934
6935   /* VEX_LEN_0F38F2 */
6936   {
6937     { "andnS",          { Gdq, VexGdq, Edq }, PREFIX_OPCODE },
6938   },
6939
6940   /* VEX_LEN_0F38F3 */
6941   {
6942     { REG_TABLE(REG_VEX_0F38F3_L_0) },
6943   },
6944
6945   /* VEX_LEN_0F38F5 */
6946   {
6947     { PREFIX_TABLE(PREFIX_VEX_0F38F5_L_0) },
6948   },
6949
6950   /* VEX_LEN_0F38F6 */
6951   {
6952     { PREFIX_TABLE(PREFIX_VEX_0F38F6_L_0) },
6953   },
6954
6955   /* VEX_LEN_0F38F7 */
6956   {
6957     { PREFIX_TABLE(PREFIX_VEX_0F38F7_L_0) },
6958   },
6959
6960   /* VEX_LEN_0F3A00 */
6961   {
6962     { Bad_Opcode },
6963     { VEX_W_TABLE (VEX_W_0F3A00_L_1) },
6964   },
6965
6966   /* VEX_LEN_0F3A01 */
6967   {
6968     { Bad_Opcode },
6969     { VEX_W_TABLE (VEX_W_0F3A01_L_1) },
6970   },
6971
6972   /* VEX_LEN_0F3A06 */
6973   {
6974     { Bad_Opcode },
6975     { VEX_W_TABLE (VEX_W_0F3A06_L_1) },
6976   },
6977
6978   /* VEX_LEN_0F3A14 */
6979   {
6980     { "vpextrb",        { Edb, XM, Ib }, PREFIX_DATA },
6981   },
6982
6983   /* VEX_LEN_0F3A15 */
6984   {
6985     { "vpextrw",        { Edw, XM, Ib }, PREFIX_DATA },
6986   },
6987
6988   /* VEX_LEN_0F3A16  */
6989   {
6990     { "vpextrK",        { Edq, XM, Ib }, PREFIX_DATA },
6991   },
6992
6993   /* VEX_LEN_0F3A17 */
6994   {
6995     { "vextractps",     { Ed, XM, Ib }, PREFIX_DATA },
6996   },
6997
6998   /* VEX_LEN_0F3A18 */
6999   {
7000     { Bad_Opcode },
7001     { VEX_W_TABLE (VEX_W_0F3A18_L_1) },
7002   },
7003
7004   /* VEX_LEN_0F3A19 */
7005   {
7006     { Bad_Opcode },
7007     { VEX_W_TABLE (VEX_W_0F3A19_L_1) },
7008   },
7009
7010   /* VEX_LEN_0F3A20 */
7011   {
7012     { "vpinsrb",        { XM, Vex, Edb, Ib }, PREFIX_DATA },
7013   },
7014
7015   /* VEX_LEN_0F3A21 */
7016   {
7017     { "vinsertps",      { XM, Vex, EXd, Ib }, PREFIX_DATA },
7018   },
7019
7020   /* VEX_LEN_0F3A22 */
7021   {
7022     { "vpinsrK",        { XM, Vex, Edq, Ib }, PREFIX_DATA },
7023   },
7024
7025   /* VEX_LEN_0F3A30 */
7026   {
7027     { MOD_TABLE (MOD_VEX_0F3A30_L_0) },
7028   },
7029
7030   /* VEX_LEN_0F3A31 */
7031   {
7032     { MOD_TABLE (MOD_VEX_0F3A31_L_0) },
7033   },
7034
7035   /* VEX_LEN_0F3A32 */
7036   {
7037     { MOD_TABLE (MOD_VEX_0F3A32_L_0) },
7038   },
7039
7040   /* VEX_LEN_0F3A33 */
7041   {
7042     { MOD_TABLE (MOD_VEX_0F3A33_L_0) },
7043   },
7044
7045   /* VEX_LEN_0F3A38 */
7046   {
7047     { Bad_Opcode },
7048     { VEX_W_TABLE (VEX_W_0F3A38_L_1) },
7049   },
7050
7051   /* VEX_LEN_0F3A39 */
7052   {
7053     { Bad_Opcode },
7054     { VEX_W_TABLE (VEX_W_0F3A39_L_1) },
7055   },
7056
7057   /* VEX_LEN_0F3A41 */
7058   {
7059     { "vdppd",          { XM, Vex, EXx, Ib }, PREFIX_DATA },
7060   },
7061
7062   /* VEX_LEN_0F3A46 */
7063   {
7064     { Bad_Opcode },
7065     { VEX_W_TABLE (VEX_W_0F3A46_L_1) },
7066   },
7067
7068   /* VEX_LEN_0F3A60 */
7069   {
7070     { "vpcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7071   },
7072
7073   /* VEX_LEN_0F3A61 */
7074   {
7075     { "vpcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7076   },
7077
7078   /* VEX_LEN_0F3A62 */
7079   {
7080     { "vpcmpistrm",     { XM, EXx, Ib }, PREFIX_DATA },
7081   },
7082
7083   /* VEX_LEN_0F3A63 */
7084   {
7085     { "vpcmpistri",     { XM, EXx, Ib }, PREFIX_DATA },
7086   },
7087
7088   /* VEX_LEN_0F3ADF */
7089   {
7090     { "vaeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
7091   },
7092
7093   /* VEX_LEN_0F3AF0 */
7094   {
7095     { PREFIX_TABLE (PREFIX_VEX_0F3AF0_L_0) },
7096   },
7097
7098   /* VEX_LEN_0FXOP_08_85 */
7099   {
7100     { VEX_W_TABLE (VEX_W_0FXOP_08_85_L_0) },
7101   },
7102
7103   /* VEX_LEN_0FXOP_08_86 */
7104   {
7105     { VEX_W_TABLE (VEX_W_0FXOP_08_86_L_0) },
7106   },
7107
7108   /* VEX_LEN_0FXOP_08_87 */
7109   {
7110     { VEX_W_TABLE (VEX_W_0FXOP_08_87_L_0) },
7111   },
7112
7113   /* VEX_LEN_0FXOP_08_8E */
7114   {
7115     { VEX_W_TABLE (VEX_W_0FXOP_08_8E_L_0) },
7116   },
7117
7118   /* VEX_LEN_0FXOP_08_8F */
7119   {
7120     { VEX_W_TABLE (VEX_W_0FXOP_08_8F_L_0) },
7121   },
7122
7123   /* VEX_LEN_0FXOP_08_95 */
7124   {
7125     { VEX_W_TABLE (VEX_W_0FXOP_08_95_L_0) },
7126   },
7127
7128   /* VEX_LEN_0FXOP_08_96 */
7129   {
7130     { VEX_W_TABLE (VEX_W_0FXOP_08_96_L_0) },
7131   },
7132
7133   /* VEX_LEN_0FXOP_08_97 */
7134   {
7135     { VEX_W_TABLE (VEX_W_0FXOP_08_97_L_0) },
7136   },
7137
7138   /* VEX_LEN_0FXOP_08_9E */
7139   {
7140     { VEX_W_TABLE (VEX_W_0FXOP_08_9E_L_0) },
7141   },
7142
7143   /* VEX_LEN_0FXOP_08_9F */
7144   {
7145     { VEX_W_TABLE (VEX_W_0FXOP_08_9F_L_0) },
7146   },
7147
7148   /* VEX_LEN_0FXOP_08_A3 */
7149   {
7150     { "vpperm",         { XM, Vex, EXx, XMVexI4 }, 0 },
7151   },
7152
7153   /* VEX_LEN_0FXOP_08_A6 */
7154   {
7155     { VEX_W_TABLE (VEX_W_0FXOP_08_A6_L_0) },
7156   },
7157
7158   /* VEX_LEN_0FXOP_08_B6 */
7159   {
7160     { VEX_W_TABLE (VEX_W_0FXOP_08_B6_L_0) },
7161   },
7162
7163   /* VEX_LEN_0FXOP_08_C0 */
7164   {
7165     { VEX_W_TABLE (VEX_W_0FXOP_08_C0_L_0) },
7166   },
7167
7168   /* VEX_LEN_0FXOP_08_C1 */
7169   {
7170     { VEX_W_TABLE (VEX_W_0FXOP_08_C1_L_0) },
7171   },
7172
7173   /* VEX_LEN_0FXOP_08_C2 */
7174   {
7175     { VEX_W_TABLE (VEX_W_0FXOP_08_C2_L_0) },
7176   },
7177
7178   /* VEX_LEN_0FXOP_08_C3 */
7179   {
7180     { VEX_W_TABLE (VEX_W_0FXOP_08_C3_L_0) },
7181   },
7182
7183   /* VEX_LEN_0FXOP_08_CC */
7184   {
7185     { VEX_W_TABLE (VEX_W_0FXOP_08_CC_L_0) },
7186   },
7187
7188   /* VEX_LEN_0FXOP_08_CD */
7189   {
7190     { VEX_W_TABLE (VEX_W_0FXOP_08_CD_L_0) },
7191   },
7192
7193   /* VEX_LEN_0FXOP_08_CE */
7194   {
7195     { VEX_W_TABLE (VEX_W_0FXOP_08_CE_L_0) },
7196   },
7197
7198   /* VEX_LEN_0FXOP_08_CF */
7199   {
7200     { VEX_W_TABLE (VEX_W_0FXOP_08_CF_L_0) },
7201   },
7202
7203   /* VEX_LEN_0FXOP_08_EC */
7204   {
7205     { VEX_W_TABLE (VEX_W_0FXOP_08_EC_L_0) },
7206   },
7207
7208   /* VEX_LEN_0FXOP_08_ED */
7209   {
7210     { VEX_W_TABLE (VEX_W_0FXOP_08_ED_L_0) },
7211   },
7212
7213   /* VEX_LEN_0FXOP_08_EE */
7214   {
7215     { VEX_W_TABLE (VEX_W_0FXOP_08_EE_L_0) },
7216   },
7217
7218   /* VEX_LEN_0FXOP_08_EF */
7219   {
7220     { VEX_W_TABLE (VEX_W_0FXOP_08_EF_L_0) },
7221   },
7222
7223   /* VEX_LEN_0FXOP_09_01 */
7224   {
7225     { REG_TABLE (REG_XOP_09_01_L_0) },
7226   },
7227
7228   /* VEX_LEN_0FXOP_09_02 */
7229   {
7230     { REG_TABLE (REG_XOP_09_02_L_0) },
7231   },
7232
7233   /* VEX_LEN_0FXOP_09_12_M_1 */
7234   {
7235     { REG_TABLE (REG_XOP_09_12_M_1_L_0) },
7236   },
7237
7238   /* VEX_LEN_0FXOP_09_82_W_0 */
7239   {
7240     { "vfrczss",        { XM, EXd }, 0 },
7241   },
7242
7243   /* VEX_LEN_0FXOP_09_83_W_0 */
7244   {
7245     { "vfrczsd",        { XM, EXq }, 0 },
7246   },
7247
7248   /* VEX_LEN_0FXOP_09_90 */
7249   {
7250     { "vprotb",         { XM, EXx, VexW }, 0 },
7251   },
7252
7253   /* VEX_LEN_0FXOP_09_91 */
7254   {
7255     { "vprotw",         { XM, EXx, VexW }, 0 },
7256   },
7257
7258   /* VEX_LEN_0FXOP_09_92 */
7259   {
7260     { "vprotd",         { XM, EXx, VexW }, 0 },
7261   },
7262
7263   /* VEX_LEN_0FXOP_09_93 */
7264   {
7265     { "vprotq",         { XM, EXx, VexW }, 0 },
7266   },
7267
7268   /* VEX_LEN_0FXOP_09_94 */
7269   {
7270     { "vpshlb",         { XM, EXx, VexW }, 0 },
7271   },
7272
7273   /* VEX_LEN_0FXOP_09_95 */
7274   {
7275     { "vpshlw",         { XM, EXx, VexW }, 0 },
7276   },
7277
7278   /* VEX_LEN_0FXOP_09_96 */
7279   {
7280     { "vpshld",         { XM, EXx, VexW }, 0 },
7281   },
7282
7283   /* VEX_LEN_0FXOP_09_97 */
7284   {
7285     { "vpshlq",         { XM, EXx, VexW }, 0 },
7286   },
7287
7288   /* VEX_LEN_0FXOP_09_98 */
7289   {
7290     { "vpshab",         { XM, EXx, VexW }, 0 },
7291   },
7292
7293   /* VEX_LEN_0FXOP_09_99 */
7294   {
7295     { "vpshaw",         { XM, EXx, VexW }, 0 },
7296   },
7297
7298   /* VEX_LEN_0FXOP_09_9A */
7299   {
7300     { "vpshad",         { XM, EXx, VexW }, 0 },
7301   },
7302
7303   /* VEX_LEN_0FXOP_09_9B */
7304   {
7305     { "vpshaq",         { XM, EXx, VexW }, 0 },
7306   },
7307
7308   /* VEX_LEN_0FXOP_09_C1 */
7309   {
7310     { VEX_W_TABLE (VEX_W_0FXOP_09_C1_L_0) },
7311   },
7312
7313   /* VEX_LEN_0FXOP_09_C2 */
7314   {
7315     { VEX_W_TABLE (VEX_W_0FXOP_09_C2_L_0) },
7316   },
7317
7318   /* VEX_LEN_0FXOP_09_C3 */
7319   {
7320     { VEX_W_TABLE (VEX_W_0FXOP_09_C3_L_0) },
7321   },
7322
7323   /* VEX_LEN_0FXOP_09_C6 */
7324   {
7325     { VEX_W_TABLE (VEX_W_0FXOP_09_C6_L_0) },
7326   },
7327
7328   /* VEX_LEN_0FXOP_09_C7 */
7329   {
7330     { VEX_W_TABLE (VEX_W_0FXOP_09_C7_L_0) },
7331   },
7332
7333   /* VEX_LEN_0FXOP_09_CB */
7334   {
7335     { VEX_W_TABLE (VEX_W_0FXOP_09_CB_L_0) },
7336   },
7337
7338   /* VEX_LEN_0FXOP_09_D1 */
7339   {
7340     { VEX_W_TABLE (VEX_W_0FXOP_09_D1_L_0) },
7341   },
7342
7343   /* VEX_LEN_0FXOP_09_D2 */
7344   {
7345     { VEX_W_TABLE (VEX_W_0FXOP_09_D2_L_0) },
7346   },
7347
7348   /* VEX_LEN_0FXOP_09_D3 */
7349   {
7350     { VEX_W_TABLE (VEX_W_0FXOP_09_D3_L_0) },
7351   },
7352
7353   /* VEX_LEN_0FXOP_09_D6 */
7354   {
7355     { VEX_W_TABLE (VEX_W_0FXOP_09_D6_L_0) },
7356   },
7357
7358   /* VEX_LEN_0FXOP_09_D7 */
7359   {
7360     { VEX_W_TABLE (VEX_W_0FXOP_09_D7_L_0) },
7361   },
7362
7363   /* VEX_LEN_0FXOP_09_DB */
7364   {
7365     { VEX_W_TABLE (VEX_W_0FXOP_09_DB_L_0) },
7366   },
7367
7368   /* VEX_LEN_0FXOP_09_E1 */
7369   {
7370     { VEX_W_TABLE (VEX_W_0FXOP_09_E1_L_0) },
7371   },
7372
7373   /* VEX_LEN_0FXOP_09_E2 */
7374   {
7375     { VEX_W_TABLE (VEX_W_0FXOP_09_E2_L_0) },
7376   },
7377
7378   /* VEX_LEN_0FXOP_09_E3 */
7379   {
7380     { VEX_W_TABLE (VEX_W_0FXOP_09_E3_L_0) },
7381   },
7382
7383   /* VEX_LEN_0FXOP_0A_12 */
7384   {
7385     { REG_TABLE (REG_XOP_0A_12_L_0) },
7386   },
7387 };
7388
7389 #include "i386-dis-evex-len.h"
7390
7391 static const struct dis386 vex_w_table[][2] = {
7392   {
7393     /* VEX_W_0F41_L_1_M_1 */
7394     { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_M_1_W_0) },
7395     { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_M_1_W_1) },
7396   },
7397   {
7398     /* VEX_W_0F42_L_1_M_1 */
7399     { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_M_1_W_0) },
7400     { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_M_1_W_1) },
7401   },
7402   {
7403     /* VEX_W_0F44_L_0_M_1 */
7404     { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_M_1_W_0) },
7405     { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_M_1_W_1) },
7406   },
7407   {
7408     /* VEX_W_0F45_L_1_M_1 */
7409     { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_M_1_W_0) },
7410     { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_M_1_W_1) },
7411   },
7412   {
7413     /* VEX_W_0F46_L_1_M_1 */
7414     { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_M_1_W_0) },
7415     { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_M_1_W_1) },
7416   },
7417   {
7418     /* VEX_W_0F47_L_1_M_1 */
7419     { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_M_1_W_0) },
7420     { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_M_1_W_1) },
7421   },
7422   {
7423     /* VEX_W_0F4A_L_1_M_1 */
7424     { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_M_1_W_0) },
7425     { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_M_1_W_1) },
7426   },
7427   {
7428     /* VEX_W_0F4B_L_1_M_1 */
7429     { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_M_1_W_0) },
7430     { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_M_1_W_1) },
7431   },
7432   {
7433     /* VEX_W_0F90_L_0 */
7434     { PREFIX_TABLE (PREFIX_VEX_0F90_L_0_W_0) },
7435     { PREFIX_TABLE (PREFIX_VEX_0F90_L_0_W_1) },
7436   },
7437   {
7438     /* VEX_W_0F91_L_0_M_0 */
7439     { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_M_0_W_0) },
7440     { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_M_0_W_1) },
7441   },
7442   {
7443     /* VEX_W_0F92_L_0_M_1 */
7444     { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_M_1_W_0) },
7445     { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_M_1_W_1) },
7446   },
7447   {
7448     /* VEX_W_0F93_L_0_M_1 */
7449     { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_M_1_W_0) },
7450     { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_M_1_W_1) },
7451   },
7452   {
7453     /* VEX_W_0F98_L_0_M_1 */
7454     { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_M_1_W_0) },
7455     { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_M_1_W_1) },
7456   },
7457   {
7458     /* VEX_W_0F99_L_0_M_1 */
7459     { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_M_1_W_0) },
7460     { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_M_1_W_1) },
7461   },
7462   {
7463     /* VEX_W_0F380C  */
7464     { "vpermilps",      { XM, Vex, EXx }, PREFIX_DATA },
7465   },
7466   {
7467     /* VEX_W_0F380D  */
7468     { "vpermilpd",      { XM, Vex, EXx }, PREFIX_DATA },
7469   },
7470   {
7471     /* VEX_W_0F380E  */
7472     { "vtestps",        { XM, EXx }, PREFIX_DATA },
7473   },
7474   {
7475     /* VEX_W_0F380F  */
7476     { "vtestpd",        { XM, EXx }, PREFIX_DATA },
7477   },
7478   {
7479     /* VEX_W_0F3813 */
7480     { "vcvtph2ps", { XM, EXxmmq }, PREFIX_DATA },
7481   },
7482   {
7483     /* VEX_W_0F3816_L_1  */
7484     { "vpermps",        { XM, Vex, EXx }, PREFIX_DATA },
7485   },
7486   {
7487     /* VEX_W_0F3818 */
7488     { "vbroadcastss",   { XM, EXd }, PREFIX_DATA },
7489   },
7490   {
7491     /* VEX_W_0F3819_L_1 */
7492     { "vbroadcastsd",   { XM, EXq }, PREFIX_DATA },
7493   },
7494   {
7495     /* VEX_W_0F381A_M_0_L_1 */
7496     { "vbroadcastf128", { XM, Mxmm }, PREFIX_DATA },
7497   },
7498   {
7499     /* VEX_W_0F382C_M_0 */
7500     { "vmaskmovps",     { XM, Vex, Mx }, PREFIX_DATA },
7501   },
7502   {
7503     /* VEX_W_0F382D_M_0 */
7504     { "vmaskmovpd",     { XM, Vex, Mx }, PREFIX_DATA },
7505   },
7506   {
7507     /* VEX_W_0F382E_M_0 */
7508     { "vmaskmovps",     { Mx, Vex, XM }, PREFIX_DATA },
7509   },
7510   {
7511     /* VEX_W_0F382F_M_0 */
7512     { "vmaskmovpd",     { Mx, Vex, XM }, PREFIX_DATA },
7513   },
7514   {
7515     /* VEX_W_0F3836  */
7516     { "vpermd",         { XM, Vex, EXx }, PREFIX_DATA },
7517   },
7518   {
7519     /* VEX_W_0F3846 */
7520     { "vpsravd",        { XM, Vex, EXx }, PREFIX_DATA },
7521   },
7522   {
7523     /* VEX_W_0F3849_X86_64_P_0 */
7524     { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_0_W_0) },
7525   },
7526   {
7527     /* VEX_W_0F3849_X86_64_P_2 */
7528     { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_2_W_0) },
7529   },
7530   {
7531     /* VEX_W_0F3849_X86_64_P_3 */
7532     { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_3_W_0) },
7533   },
7534   {
7535     /* VEX_W_0F384B_X86_64_P_1 */
7536     { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_1_W_0) },
7537   },
7538   {
7539     /* VEX_W_0F384B_X86_64_P_2 */
7540     { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_2_W_0) },
7541   },
7542   {
7543     /* VEX_W_0F384B_X86_64_P_3 */
7544     { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_3_W_0) },
7545   },
7546   {
7547     /* VEX_W_0F3850 */
7548     { "%XV vpdpbusd",   { XM, Vex, EXx }, 0 },
7549   },
7550   {
7551     /* VEX_W_0F3851 */
7552     { "%XV vpdpbusds",  { XM, Vex, EXx }, 0 },
7553   },
7554   {
7555     /* VEX_W_0F3852 */
7556     { "%XV vpdpwssd",   { XM, Vex, EXx }, 0 },
7557   },
7558   {
7559     /* VEX_W_0F3853 */
7560     { "%XV vpdpwssds",  { XM, Vex, EXx }, 0 },
7561   },
7562   {
7563     /* VEX_W_0F3858 */
7564     { "vpbroadcastd", { XM, EXd }, PREFIX_DATA },
7565   },
7566   {
7567     /* VEX_W_0F3859 */
7568     { "vpbroadcastq", { XM, EXq }, PREFIX_DATA },
7569   },
7570   {
7571     /* VEX_W_0F385A_M_0_L_0 */
7572     { "vbroadcasti128", { XM, Mxmm }, PREFIX_DATA },
7573   },
7574   {
7575     /* VEX_W_0F385C_X86_64_P_1 */
7576     { MOD_TABLE (MOD_VEX_0F385C_X86_64_P_1_W_0) },
7577   },
7578   {
7579     /* VEX_W_0F385E_X86_64_P_0 */
7580     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_0_W_0) },
7581   },
7582   {
7583     /* VEX_W_0F385E_X86_64_P_1 */
7584     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_1_W_0) },
7585   },
7586   {
7587     /* VEX_W_0F385E_X86_64_P_2 */
7588     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_2_W_0) },
7589   },
7590   {
7591     /* VEX_W_0F385E_X86_64_P_3 */
7592     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_3_W_0) },
7593   },
7594   {
7595     /* VEX_W_0F3878 */
7596     { "vpbroadcastb",   { XM, EXb }, PREFIX_DATA },
7597   },
7598   {
7599     /* VEX_W_0F3879 */
7600     { "vpbroadcastw",   { XM, EXw }, PREFIX_DATA },
7601   },
7602   {
7603     /* VEX_W_0F38CF */
7604     { "vgf2p8mulb", { XM, Vex, EXx }, PREFIX_DATA },
7605   },
7606   {
7607     /* VEX_W_0F3A00_L_1 */
7608     { Bad_Opcode },
7609     { "vpermq",         { XM, EXx, Ib }, PREFIX_DATA },
7610   },
7611   {
7612     /* VEX_W_0F3A01_L_1 */
7613     { Bad_Opcode },
7614     { "vpermpd",        { XM, EXx, Ib }, PREFIX_DATA },
7615   },
7616   {
7617     /* VEX_W_0F3A02 */
7618     { "vpblendd",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
7619   },
7620   {
7621     /* VEX_W_0F3A04 */
7622     { "vpermilps",      { XM, EXx, Ib }, PREFIX_DATA },
7623   },
7624   {
7625     /* VEX_W_0F3A05 */
7626     { "vpermilpd",      { XM, EXx, Ib }, PREFIX_DATA },
7627   },
7628   {
7629     /* VEX_W_0F3A06_L_1 */
7630     { "vperm2f128",     { XM, Vex, EXx, Ib }, PREFIX_DATA },
7631   },
7632   {
7633     /* VEX_W_0F3A18_L_1 */
7634     { "vinsertf128",    { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7635   },
7636   {
7637     /* VEX_W_0F3A19_L_1 */
7638     { "vextractf128",   { EXxmm, XM, Ib }, PREFIX_DATA },
7639   },
7640   {
7641     /* VEX_W_0F3A1D */
7642     { "vcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, PREFIX_DATA },
7643   },
7644   {
7645     /* VEX_W_0F3A38_L_1 */
7646     { "vinserti128",    { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7647   },
7648   {
7649     /* VEX_W_0F3A39_L_1 */
7650     { "vextracti128",   { EXxmm, XM, Ib }, PREFIX_DATA },
7651   },
7652   {
7653     /* VEX_W_0F3A46_L_1 */
7654     { "vperm2i128",     { XM, Vex, EXx, Ib }, PREFIX_DATA },
7655   },
7656   {
7657     /* VEX_W_0F3A4A */
7658     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7659   },
7660   {
7661     /* VEX_W_0F3A4B */
7662     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7663   },
7664   {
7665     /* VEX_W_0F3A4C */
7666     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7667   },
7668   {
7669     /* VEX_W_0F3ACE */
7670     { Bad_Opcode },
7671     { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7672   },
7673   {
7674     /* VEX_W_0F3ACF */
7675     { Bad_Opcode },
7676     { "vgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, PREFIX_DATA },
7677   },
7678   /* VEX_W_0FXOP_08_85_L_0 */
7679   {
7680     { "vpmacssww",      { XM, Vex, EXx, XMVexI4 }, 0 },
7681   },
7682   /* VEX_W_0FXOP_08_86_L_0 */
7683   {
7684     { "vpmacsswd",      { XM, Vex, EXx, XMVexI4 }, 0 },
7685   },
7686   /* VEX_W_0FXOP_08_87_L_0 */
7687   {
7688     { "vpmacssdql",     { XM, Vex, EXx, XMVexI4 }, 0 },
7689   },
7690   /* VEX_W_0FXOP_08_8E_L_0 */
7691   {
7692     { "vpmacssdd",      { XM, Vex, EXx, XMVexI4 }, 0 },
7693   },
7694   /* VEX_W_0FXOP_08_8F_L_0 */
7695   {
7696     { "vpmacssdqh",     { XM, Vex, EXx, XMVexI4 }, 0 },
7697   },
7698   /* VEX_W_0FXOP_08_95_L_0 */
7699   {
7700     { "vpmacsww",       { XM, Vex, EXx, XMVexI4 }, 0 },
7701   },
7702   /* VEX_W_0FXOP_08_96_L_0 */
7703   {
7704     { "vpmacswd",       { XM, Vex, EXx, XMVexI4 }, 0 },
7705   },
7706   /* VEX_W_0FXOP_08_97_L_0 */
7707   {
7708     { "vpmacsdql",      { XM, Vex, EXx, XMVexI4 }, 0 },
7709   },
7710   /* VEX_W_0FXOP_08_9E_L_0 */
7711   {
7712     { "vpmacsdd",       { XM, Vex, EXx, XMVexI4 }, 0 },
7713   },
7714   /* VEX_W_0FXOP_08_9F_L_0 */
7715   {
7716     { "vpmacsdqh",      { XM, Vex, EXx, XMVexI4 }, 0 },
7717   },
7718   /* VEX_W_0FXOP_08_A6_L_0 */
7719   {
7720     { "vpmadcsswd",     { XM, Vex, EXx, XMVexI4 }, 0 },
7721   },
7722   /* VEX_W_0FXOP_08_B6_L_0 */
7723   {
7724     { "vpmadcswd",      { XM, Vex, EXx, XMVexI4 }, 0 },
7725   },
7726   /* VEX_W_0FXOP_08_C0_L_0 */
7727   {
7728     { "vprotb",         { XM, EXx, Ib }, 0 },
7729   },
7730   /* VEX_W_0FXOP_08_C1_L_0 */
7731   {
7732     { "vprotw",         { XM, EXx, Ib }, 0 },
7733   },
7734   /* VEX_W_0FXOP_08_C2_L_0 */
7735   {
7736     { "vprotd",         { XM, EXx, Ib }, 0 },
7737   },
7738   /* VEX_W_0FXOP_08_C3_L_0 */
7739   {
7740     { "vprotq",         { XM, EXx, Ib }, 0 },
7741   },
7742   /* VEX_W_0FXOP_08_CC_L_0 */
7743   {
7744      { "vpcomb",        { XM, Vex, EXx, VPCOM }, 0 },
7745   },
7746   /* VEX_W_0FXOP_08_CD_L_0 */
7747   {
7748      { "vpcomw",        { XM, Vex, EXx, VPCOM }, 0 },
7749   },
7750   /* VEX_W_0FXOP_08_CE_L_0 */
7751   {
7752      { "vpcomd",        { XM, Vex, EXx, VPCOM }, 0 },
7753   },
7754   /* VEX_W_0FXOP_08_CF_L_0 */
7755   {
7756      { "vpcomq",        { XM, Vex, EXx, VPCOM }, 0 },
7757   },
7758   /* VEX_W_0FXOP_08_EC_L_0 */
7759   {
7760      { "vpcomub",       { XM, Vex, EXx, VPCOM }, 0 },
7761   },
7762   /* VEX_W_0FXOP_08_ED_L_0 */
7763   {
7764      { "vpcomuw",       { XM, Vex, EXx, VPCOM }, 0 },
7765   },
7766   /* VEX_W_0FXOP_08_EE_L_0 */
7767   {
7768      { "vpcomud",       { XM, Vex, EXx, VPCOM }, 0 },
7769   },
7770   /* VEX_W_0FXOP_08_EF_L_0 */
7771   {
7772      { "vpcomuq",       { XM, Vex, EXx, VPCOM }, 0 },
7773   },
7774   /* VEX_W_0FXOP_09_80 */
7775   {
7776     { "vfrczps",        { XM, EXx }, 0 },
7777   },
7778   /* VEX_W_0FXOP_09_81 */
7779   {
7780     { "vfrczpd",        { XM, EXx }, 0 },
7781   },
7782   /* VEX_W_0FXOP_09_82 */
7783   {
7784     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_82_W_0) },
7785   },
7786   /* VEX_W_0FXOP_09_83 */
7787   {
7788     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_83_W_0) },
7789   },
7790   /* VEX_W_0FXOP_09_C1_L_0 */
7791   {
7792     { "vphaddbw",       { XM, EXxmm }, 0 },
7793   },
7794   /* VEX_W_0FXOP_09_C2_L_0 */
7795   {
7796     { "vphaddbd",       { XM, EXxmm }, 0 },
7797   },
7798   /* VEX_W_0FXOP_09_C3_L_0 */
7799   {
7800     { "vphaddbq",       { XM, EXxmm }, 0 },
7801   },
7802   /* VEX_W_0FXOP_09_C6_L_0 */
7803   {
7804     { "vphaddwd",       { XM, EXxmm }, 0 },
7805   },
7806   /* VEX_W_0FXOP_09_C7_L_0 */
7807   {
7808     { "vphaddwq",       { XM, EXxmm }, 0 },
7809   },
7810   /* VEX_W_0FXOP_09_CB_L_0 */
7811   {
7812     { "vphadddq",       { XM, EXxmm }, 0 },
7813   },
7814   /* VEX_W_0FXOP_09_D1_L_0 */
7815   {
7816     { "vphaddubw",      { XM, EXxmm }, 0 },
7817   },
7818   /* VEX_W_0FXOP_09_D2_L_0 */
7819   {
7820     { "vphaddubd",      { XM, EXxmm }, 0 },
7821   },
7822   /* VEX_W_0FXOP_09_D3_L_0 */
7823   {
7824     { "vphaddubq",      { XM, EXxmm }, 0 },
7825   },
7826   /* VEX_W_0FXOP_09_D6_L_0 */
7827   {
7828     { "vphadduwd",      { XM, EXxmm }, 0 },
7829   },
7830   /* VEX_W_0FXOP_09_D7_L_0 */
7831   {
7832     { "vphadduwq",      { XM, EXxmm }, 0 },
7833   },
7834   /* VEX_W_0FXOP_09_DB_L_0 */
7835   {
7836     { "vphaddudq",      { XM, EXxmm }, 0 },
7837   },
7838   /* VEX_W_0FXOP_09_E1_L_0 */
7839   {
7840     { "vphsubbw",       { XM, EXxmm }, 0 },
7841   },
7842   /* VEX_W_0FXOP_09_E2_L_0 */
7843   {
7844     { "vphsubwd",       { XM, EXxmm }, 0 },
7845   },
7846   /* VEX_W_0FXOP_09_E3_L_0 */
7847   {
7848     { "vphsubdq",       { XM, EXxmm }, 0 },
7849   },
7850
7851 #include "i386-dis-evex-w.h"
7852 };
7853
7854 static const struct dis386 mod_table[][2] = {
7855   {
7856     /* MOD_62_32BIT */
7857     { "bound{S|}",      { Gv, Ma }, 0 },
7858     { EVEX_TABLE (EVEX_0F) },
7859   },
7860   {
7861     /* MOD_8D */
7862     { "leaS",           { Gv, M }, 0 },
7863   },
7864   {
7865     /* MOD_C4_32BIT */
7866     { "lesS",           { Gv, Mp }, 0 },
7867     { VEX_C4_TABLE (VEX_0F) },
7868   },
7869   {
7870     /* MOD_C5_32BIT */
7871     { "ldsS",           { Gv, Mp }, 0 },
7872     { VEX_C5_TABLE (VEX_0F) },
7873   },
7874   {
7875     /* MOD_C6_REG_7 */
7876     { Bad_Opcode },
7877     { RM_TABLE (RM_C6_REG_7) },
7878   },
7879   {
7880     /* MOD_C7_REG_7 */
7881     { Bad_Opcode },
7882     { RM_TABLE (RM_C7_REG_7) },
7883   },
7884   {
7885     /* MOD_FF_REG_3 */
7886     { "{l|}call^", { indirEp }, 0 },
7887   },
7888   {
7889     /* MOD_FF_REG_5 */
7890     { "{l|}jmp^", { indirEp }, 0 },
7891   },
7892   {
7893     /* MOD_0F01_REG_0 */
7894     { X86_64_TABLE (X86_64_0F01_REG_0) },
7895     { RM_TABLE (RM_0F01_REG_0) },
7896   },
7897   {
7898     /* MOD_0F01_REG_1 */
7899     { X86_64_TABLE (X86_64_0F01_REG_1) },
7900     { RM_TABLE (RM_0F01_REG_1) },
7901   },
7902   {
7903     /* MOD_0F01_REG_2 */
7904     { X86_64_TABLE (X86_64_0F01_REG_2) },
7905     { RM_TABLE (RM_0F01_REG_2) },
7906   },
7907   {
7908     /* MOD_0F01_REG_3 */
7909     { X86_64_TABLE (X86_64_0F01_REG_3) },
7910     { RM_TABLE (RM_0F01_REG_3) },
7911   },
7912   {
7913     /* MOD_0F01_REG_5 */
7914     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) },
7915     { RM_TABLE (RM_0F01_REG_5_MOD_3) },
7916   },
7917   {
7918     /* MOD_0F01_REG_7 */
7919     { "invlpg",         { Mb }, 0 },
7920     { RM_TABLE (RM_0F01_REG_7_MOD_3) },
7921   },
7922   {
7923     /* MOD_0F12_PREFIX_0 */
7924     { "movlpX",         { XM, EXq }, 0 },
7925     { "movhlps",        { XM, EXq }, 0 },
7926   },
7927   {
7928     /* MOD_0F12_PREFIX_2 */
7929     { "movlpX", { XM, EXq }, 0 },
7930   },
7931   {
7932     /* MOD_0F13 */
7933     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
7934   },
7935   {
7936     /* MOD_0F16_PREFIX_0 */
7937     { "movhpX",         { XM, EXq }, 0 },
7938     { "movlhps",        { XM, EXq }, 0 },
7939   },
7940   {
7941     /* MOD_0F16_PREFIX_2 */
7942     { "movhpX", { XM, EXq }, 0 },
7943   },
7944   {
7945     /* MOD_0F17 */
7946     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
7947   },
7948   {
7949     /* MOD_0F18_REG_0 */
7950     { "prefetchnta",    { Mb }, 0 },
7951     { "nopQ",           { Ev }, 0 },
7952   },
7953   {
7954     /* MOD_0F18_REG_1 */
7955     { "prefetcht0",     { Mb }, 0 },
7956     { "nopQ",           { Ev }, 0 },
7957   },
7958   {
7959     /* MOD_0F18_REG_2 */
7960     { "prefetcht1",     { Mb }, 0 },
7961     { "nopQ",           { Ev }, 0 },
7962   },
7963   {
7964     /* MOD_0F18_REG_3 */
7965     { "prefetcht2",     { Mb }, 0 },
7966     { "nopQ",           { Ev }, 0 },
7967   },
7968   {
7969     /* MOD_0F1A_PREFIX_0 */
7970     { "bndldx",         { Gbnd, Mv_bnd }, 0 },
7971     { "nopQ",           { Ev }, 0 },
7972   },
7973   {
7974     /* MOD_0F1B_PREFIX_0 */
7975     { "bndstx",         { Mv_bnd, Gbnd }, 0 },
7976     { "nopQ",           { Ev }, 0 },
7977   },
7978   {
7979     /* MOD_0F1B_PREFIX_1 */
7980     { "bndmk",          { Gbnd, Mv_bnd }, 0 },
7981     { "nopQ",           { Ev }, PREFIX_IGNORED },
7982   },
7983   {
7984     /* MOD_0F1C_PREFIX_0 */
7985     { REG_TABLE (REG_0F1C_P_0_MOD_0) },
7986     { "nopQ",           { Ev }, 0 },
7987   },
7988   {
7989     /* MOD_0F1E_PREFIX_1 */
7990     { "nopQ",           { Ev }, PREFIX_IGNORED },
7991     { REG_TABLE (REG_0F1E_P_1_MOD_3) },
7992   },
7993   {
7994     /* MOD_0F2B_PREFIX_0 */
7995     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
7996   },
7997   {
7998     /* MOD_0F2B_PREFIX_1 */
7999     {"movntss",         { Md, XM }, PREFIX_OPCODE },
8000   },
8001   {
8002     /* MOD_0F2B_PREFIX_2 */
8003     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
8004   },
8005   {
8006     /* MOD_0F2B_PREFIX_3 */
8007     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
8008   },
8009   {
8010     /* MOD_0F50 */
8011     { Bad_Opcode },
8012     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
8013   },
8014   {
8015     /* MOD_0F71 */
8016     { Bad_Opcode },
8017     { REG_TABLE (REG_0F71_MOD_0) },
8018   },
8019   {
8020     /* MOD_0F72 */
8021     { Bad_Opcode },
8022     { REG_TABLE (REG_0F72_MOD_0) },
8023   },
8024   {
8025     /* MOD_0F73 */
8026     { Bad_Opcode },
8027     { REG_TABLE (REG_0F73_MOD_0) },
8028   },
8029   {
8030     /* MOD_0FAE_REG_0 */
8031     { "fxsave",         { FXSAVE }, 0 },
8032     { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) },
8033   },
8034   {
8035     /* MOD_0FAE_REG_1 */
8036     { "fxrstor",        { FXSAVE }, 0 },
8037     { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) },
8038   },
8039   {
8040     /* MOD_0FAE_REG_2 */
8041     { "ldmxcsr",        { Md }, 0 },
8042     { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) },
8043   },
8044   {
8045     /* MOD_0FAE_REG_3 */
8046     { "stmxcsr",        { Md }, 0 },
8047     { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) },
8048   },
8049   {
8050     /* MOD_0FAE_REG_4 */
8051     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) },
8052     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) },
8053   },
8054   {
8055     /* MOD_0FAE_REG_5 */
8056     { "xrstor",         { FXSAVE }, PREFIX_OPCODE },
8057     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) },
8058   },
8059   {
8060     /* MOD_0FAE_REG_6 */
8061     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) },
8062     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) },
8063   },
8064   {
8065     /* MOD_0FAE_REG_7 */
8066     { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) },
8067     { RM_TABLE (RM_0FAE_REG_7_MOD_3) },
8068   },
8069   {
8070     /* MOD_0FB2 */
8071     { "lssS",           { Gv, Mp }, 0 },
8072   },
8073   {
8074     /* MOD_0FB4 */
8075     { "lfsS",           { Gv, Mp }, 0 },
8076   },
8077   {
8078     /* MOD_0FB5 */
8079     { "lgsS",           { Gv, Mp }, 0 },
8080   },
8081   {
8082     /* MOD_0FC3 */
8083     { "movntiS", { Edq, Gdq }, PREFIX_OPCODE },
8084   },
8085   {
8086     /* MOD_0FC7_REG_3 */
8087     { "xrstors",        { FXSAVE }, 0 },
8088   },
8089   {
8090     /* MOD_0FC7_REG_4 */
8091     { "xsavec",         { FXSAVE }, 0 },
8092   },
8093   {
8094     /* MOD_0FC7_REG_5 */
8095     { "xsaves",         { FXSAVE }, 0 },
8096   },
8097   {
8098     /* MOD_0FC7_REG_6 */
8099     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) },
8100     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) }
8101   },
8102   {
8103     /* MOD_0FC7_REG_7 */
8104     { "vmptrst",        { Mq }, 0 },
8105     { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) }
8106   },
8107   {
8108     /* MOD_0FD7 */
8109     { Bad_Opcode },
8110     { "pmovmskb",       { Gdq, MS }, 0 },
8111   },
8112   {
8113     /* MOD_0FE7_PREFIX_2 */
8114     { "movntdq",        { Mx, XM }, 0 },
8115   },
8116   {
8117     /* MOD_0FF0_PREFIX_3 */
8118     { "lddqu",          { XM, M }, 0 },
8119   },
8120   {
8121     /* MOD_0F382A */
8122     { "movntdqa",       { XM, Mx }, PREFIX_DATA },
8123   },
8124   {
8125     /* MOD_0F38DC_PREFIX_1 */
8126     { "aesenc128kl",    { XM, M }, 0 },
8127     { "loadiwkey",      { XM, EXx }, 0 },
8128   },
8129   {
8130     /* MOD_0F38DD_PREFIX_1 */
8131     { "aesdec128kl",    { XM, M }, 0 },
8132   },
8133   {
8134     /* MOD_0F38DE_PREFIX_1 */
8135     { "aesenc256kl",    { XM, M }, 0 },
8136   },
8137   {
8138     /* MOD_0F38DF_PREFIX_1 */
8139     { "aesdec256kl",    { XM, M }, 0 },
8140   },
8141   {
8142     /* MOD_0F38F5 */
8143     { "wrussK",         { M, Gdq }, PREFIX_DATA },
8144   },
8145   {
8146     /* MOD_0F38F6_PREFIX_0 */
8147     { "wrssK",          { M, Gdq }, PREFIX_OPCODE },
8148   },
8149   {
8150     /* MOD_0F38F8_PREFIX_1 */
8151     { "enqcmds",        { Gva, M }, PREFIX_OPCODE },
8152   },
8153   {
8154     /* MOD_0F38F8_PREFIX_2 */
8155     { "movdir64b",      { Gva, M }, PREFIX_OPCODE },
8156   },
8157   {
8158     /* MOD_0F38F8_PREFIX_3 */
8159     { "enqcmd",         { Gva, M }, PREFIX_OPCODE },
8160   },
8161   {
8162     /* MOD_0F38F9 */
8163     { "movdiri",        { Edq, Gdq }, PREFIX_OPCODE },
8164   },
8165   {
8166     /* MOD_0F38FA_PREFIX_1 */
8167     { Bad_Opcode },
8168     { "encodekey128", { Gd, Ed }, 0 },
8169   },
8170   {
8171     /* MOD_0F38FB_PREFIX_1 */
8172     { Bad_Opcode },
8173     { "encodekey256", { Gd, Ed }, 0 },
8174   },
8175   {
8176     /* MOD_0F3A0F_PREFIX_1 */
8177     { Bad_Opcode },
8178     { REG_TABLE (REG_0F3A0F_PREFIX_1_MOD_3) },
8179   },
8180   {
8181     /* MOD_VEX_0F12_PREFIX_0 */
8182     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
8183     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
8184   },
8185   {
8186     /* MOD_VEX_0F12_PREFIX_2 */
8187     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0) },
8188   },
8189   {
8190     /* MOD_VEX_0F13 */
8191     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
8192   },
8193   {
8194     /* MOD_VEX_0F16_PREFIX_0 */
8195     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
8196     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
8197   },
8198   {
8199     /* MOD_VEX_0F16_PREFIX_2 */
8200     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0) },
8201   },
8202   {
8203     /* MOD_VEX_0F17 */
8204     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
8205   },
8206   {
8207     /* MOD_VEX_0F2B */
8208     { "vmovntpX",       { Mx, XM }, PREFIX_OPCODE },
8209   },
8210   {
8211     /* MOD_VEX_0F41_L_1 */
8212     { Bad_Opcode },
8213     { VEX_W_TABLE (VEX_W_0F41_L_1_M_1) },
8214   },
8215   {
8216     /* MOD_VEX_0F42_L_1 */
8217     { Bad_Opcode },
8218     { VEX_W_TABLE (VEX_W_0F42_L_1_M_1) },
8219   },
8220   {
8221     /* MOD_VEX_0F44_L_0 */
8222     { Bad_Opcode },
8223     { VEX_W_TABLE (VEX_W_0F44_L_0_M_1) },
8224   },
8225   {
8226     /* MOD_VEX_0F45_L_1 */
8227     { Bad_Opcode },
8228     { VEX_W_TABLE (VEX_W_0F45_L_1_M_1) },
8229   },
8230   {
8231     /* MOD_VEX_0F46_L_1 */
8232     { Bad_Opcode },
8233     { VEX_W_TABLE (VEX_W_0F46_L_1_M_1) },
8234   },
8235   {
8236     /* MOD_VEX_0F47_L_1 */
8237     { Bad_Opcode },
8238     { VEX_W_TABLE (VEX_W_0F47_L_1_M_1) },
8239   },
8240   {
8241     /* MOD_VEX_0F4A_L_1 */
8242     { Bad_Opcode },
8243     { VEX_W_TABLE (VEX_W_0F4A_L_1_M_1) },
8244   },
8245   {
8246     /* MOD_VEX_0F4B_L_1 */
8247     { Bad_Opcode },
8248     { VEX_W_TABLE (VEX_W_0F4B_L_1_M_1) },
8249   },
8250   {
8251     /* MOD_VEX_0F50 */
8252     { Bad_Opcode },
8253     { "vmovmskpX",      { Gdq, XS }, PREFIX_OPCODE },
8254   },
8255   {
8256     /* MOD_VEX_0F71 */
8257     { Bad_Opcode },
8258     { REG_TABLE (REG_VEX_0F71_M_0) },
8259   },
8260   {
8261     /* MOD_VEX_0F72 */
8262     { Bad_Opcode },
8263     { REG_TABLE (REG_VEX_0F72_M_0) },
8264   },
8265   {
8266     /* MOD_VEX_0F73 */
8267     { Bad_Opcode },
8268     { REG_TABLE (REG_VEX_0F73_M_0) },
8269   },
8270   {
8271     /* MOD_VEX_0F91_L_0 */
8272     { VEX_W_TABLE (VEX_W_0F91_L_0_M_0) },
8273   },
8274   {
8275     /* MOD_VEX_0F92_L_0 */
8276     { Bad_Opcode },
8277     { VEX_W_TABLE (VEX_W_0F92_L_0_M_1) },
8278   },
8279   {
8280     /* MOD_VEX_0F93_L_0 */
8281     { Bad_Opcode },
8282     { VEX_W_TABLE (VEX_W_0F93_L_0_M_1) },
8283   },
8284   {
8285     /* MOD_VEX_0F98_L_0 */
8286     { Bad_Opcode },
8287     { VEX_W_TABLE (VEX_W_0F98_L_0_M_1) },
8288   },
8289   {
8290     /* MOD_VEX_0F99_L_0 */
8291     { Bad_Opcode },
8292     { VEX_W_TABLE (VEX_W_0F99_L_0_M_1) },
8293   },
8294   {
8295     /* MOD_VEX_0FAE_REG_2 */
8296     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
8297   },
8298   {
8299     /* MOD_VEX_0FAE_REG_3 */
8300     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
8301   },
8302   {
8303     /* MOD_VEX_0FD7 */
8304     { Bad_Opcode },
8305     { "vpmovmskb",      { Gdq, XS }, PREFIX_DATA },
8306   },
8307   {
8308     /* MOD_VEX_0FE7 */
8309     { "vmovntdq",       { Mx, XM }, PREFIX_DATA },
8310   },
8311   {
8312     /* MOD_VEX_0FF0_PREFIX_3 */
8313     { "vlddqu",         { XM, M }, 0 },
8314   },
8315   {
8316     /* MOD_VEX_0F381A */
8317     { VEX_LEN_TABLE (VEX_LEN_0F381A_M_0) },
8318   },
8319   {
8320     /* MOD_VEX_0F382A */
8321     { "vmovntdqa",      { XM, Mx }, PREFIX_DATA },
8322   },
8323   {
8324     /* MOD_VEX_0F382C */
8325     { VEX_W_TABLE (VEX_W_0F382C_M_0) },
8326   },
8327   {
8328     /* MOD_VEX_0F382D */
8329     { VEX_W_TABLE (VEX_W_0F382D_M_0) },
8330   },
8331   {
8332     /* MOD_VEX_0F382E */
8333     { VEX_W_TABLE (VEX_W_0F382E_M_0) },
8334   },
8335   {
8336     /* MOD_VEX_0F382F */
8337     { VEX_W_TABLE (VEX_W_0F382F_M_0) },
8338   },
8339   {
8340     /* MOD_VEX_0F3849_X86_64_P_0_W_0 */
8341     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0) },
8342     { REG_TABLE (REG_VEX_0F3849_X86_64_P_0_W_0_M_1) },
8343   },
8344   {
8345     /* MOD_VEX_0F3849_X86_64_P_2_W_0 */
8346     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0) },
8347   },
8348   {
8349     /* MOD_VEX_0F3849_X86_64_P_3_W_0 */
8350     { Bad_Opcode },
8351     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0) },
8352   },
8353   {
8354     /* MOD_VEX_0F384B_X86_64_P_1_W_0 */
8355     { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0) },
8356   },
8357   {
8358     /* MOD_VEX_0F384B_X86_64_P_2_W_0 */
8359     { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0) },
8360   },
8361   {
8362     /* MOD_VEX_0F384B_X86_64_P_3_W_0 */
8363     { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0) },
8364   },
8365   {
8366     /* MOD_VEX_0F385A */
8367     { VEX_LEN_TABLE (VEX_LEN_0F385A_M_0) },
8368   },
8369   {
8370     /* MOD_VEX_0F385C_X86_64_P_1_W_0 */
8371     { Bad_Opcode },
8372     { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0) },
8373   },
8374   {
8375     /* MOD_VEX_0F385E_X86_64_P_0_W_0 */
8376     { Bad_Opcode },
8377     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0) },
8378   },
8379   {
8380     /* MOD_VEX_0F385E_X86_64_P_1_W_0 */
8381     { Bad_Opcode },
8382     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0) },
8383   },
8384   {
8385     /* MOD_VEX_0F385E_X86_64_P_2_W_0 */
8386     { Bad_Opcode },
8387     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0) },
8388   },
8389   {
8390     /* MOD_VEX_0F385E_X86_64_P_3_W_0 */
8391     { Bad_Opcode },
8392     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0) },
8393   },
8394   {
8395     /* MOD_VEX_0F388C */
8396     { "vpmaskmov%DQ",   { XM, Vex, Mx }, PREFIX_DATA },
8397   },
8398   {
8399     /* MOD_VEX_0F388E */
8400     { "vpmaskmov%DQ",   { Mx, Vex, XM }, PREFIX_DATA },
8401   },
8402   {
8403     /* MOD_VEX_0F3A30_L_0 */
8404     { Bad_Opcode },
8405     { "kshiftr%BW",     { MaskG, MaskE, Ib }, PREFIX_DATA },
8406   },
8407   {
8408     /* MOD_VEX_0F3A31_L_0 */
8409     { Bad_Opcode },
8410     { "kshiftr%DQ",     { MaskG, MaskE, Ib }, PREFIX_DATA },
8411   },
8412   {
8413     /* MOD_VEX_0F3A32_L_0 */
8414     { Bad_Opcode },
8415     { "kshiftl%BW",     { MaskG, MaskE, Ib }, PREFIX_DATA },
8416   },
8417   {
8418     /* MOD_VEX_0F3A33_L_0 */
8419     { Bad_Opcode },
8420     { "kshiftl%DQ",     { MaskG, MaskE, Ib }, PREFIX_DATA },
8421   },
8422   {
8423     /* MOD_XOP_09_12 */
8424     { Bad_Opcode },
8425     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_12_M_1) },
8426   },
8427
8428 #include "i386-dis-evex-mod.h"
8429 };
8430
8431 static const struct dis386 rm_table[][8] = {
8432   {
8433     /* RM_C6_REG_7 */
8434     { "xabort",         { Skip_MODRM, Ib }, 0 },
8435   },
8436   {
8437     /* RM_C7_REG_7 */
8438     { "xbeginT",        { Skip_MODRM, Jdqw }, 0 },
8439   },
8440   {
8441     /* RM_0F01_REG_0 */
8442     { "enclv",          { Skip_MODRM }, 0 },
8443     { "vmcall",         { Skip_MODRM }, 0 },
8444     { "vmlaunch",       { Skip_MODRM }, 0 },
8445     { "vmresume",       { Skip_MODRM }, 0 },
8446     { "vmxoff",         { Skip_MODRM }, 0 },
8447     { "pconfig",        { Skip_MODRM }, 0 },
8448   },
8449   {
8450     /* RM_0F01_REG_1 */
8451     { "monitor",        { { OP_Monitor, 0 } }, 0 },
8452     { "mwait",          { { OP_Mwait, 0 } }, 0 },
8453     { "clac",           { Skip_MODRM }, 0 },
8454     { "stac",           { Skip_MODRM }, 0 },
8455     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_4) },
8456     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_5) },
8457     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_6) },
8458     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_7) },
8459   },
8460   {
8461     /* RM_0F01_REG_2 */
8462     { "xgetbv",         { Skip_MODRM }, 0 },
8463     { "xsetbv",         { Skip_MODRM }, 0 },
8464     { Bad_Opcode },
8465     { Bad_Opcode },
8466     { "vmfunc",         { Skip_MODRM }, 0 },
8467     { "xend",           { Skip_MODRM }, 0 },
8468     { "xtest",          { Skip_MODRM }, 0 },
8469     { "enclu",          { Skip_MODRM }, 0 },
8470   },
8471   {
8472     /* RM_0F01_REG_3 */
8473     { "vmrun",          { Skip_MODRM }, 0 },
8474     { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) },
8475     { "vmload",         { Skip_MODRM }, 0 },
8476     { "vmsave",         { Skip_MODRM }, 0 },
8477     { "stgi",           { Skip_MODRM }, 0 },
8478     { "clgi",           { Skip_MODRM }, 0 },
8479     { "skinit",         { Skip_MODRM }, 0 },
8480     { "invlpga",        { Skip_MODRM }, 0 },
8481   },
8482   {
8483     /* RM_0F01_REG_5_MOD_3 */
8484     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) },
8485     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) },
8486     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) },
8487     { Bad_Opcode },
8488     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_4) },
8489     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_5) },
8490     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_6) },
8491     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_7) },
8492   },
8493   {
8494     /* RM_0F01_REG_7_MOD_3 */
8495     { "swapgs",         { Skip_MODRM }, 0  },
8496     { "rdtscp",         { Skip_MODRM }, 0  },
8497     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) },
8498     { "mwaitx",         { { OP_Mwait, eBX_reg } }, PREFIX_OPCODE },
8499     { "clzero",         { Skip_MODRM }, 0  },
8500     { "rdpru",          { Skip_MODRM }, 0  },
8501     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_6) },
8502     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_7) },
8503   },
8504   {
8505     /* RM_0F1E_P_1_MOD_3_REG_7 */
8506     { "nopQ",           { Ev }, PREFIX_IGNORED },
8507     { "nopQ",           { Ev }, PREFIX_IGNORED },
8508     { "endbr64",        { Skip_MODRM }, 0 },
8509     { "endbr32",        { Skip_MODRM }, 0 },
8510     { "nopQ",           { Ev }, PREFIX_IGNORED },
8511     { "nopQ",           { Ev }, PREFIX_IGNORED },
8512     { "nopQ",           { Ev }, PREFIX_IGNORED },
8513     { "nopQ",           { Ev }, PREFIX_IGNORED },
8514   },
8515   {
8516     /* RM_0FAE_REG_6_MOD_3 */
8517     { "mfence",         { Skip_MODRM }, 0 },
8518   },
8519   {
8520     /* RM_0FAE_REG_7_MOD_3 */
8521     { "sfence",         { Skip_MODRM }, 0 },
8522   },
8523   {
8524     /* RM_0F3A0F_P_1_MOD_3_REG_0 */
8525     { "hreset",         { Skip_MODRM, Ib }, 0 },
8526   },
8527   {
8528     /* RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0 */
8529     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0) },
8530   },
8531 };
8532
8533 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
8534
8535 /* We use the high bit to indicate different name for the same
8536    prefix.  */
8537 #define REP_PREFIX      (0xf3 | 0x100)
8538 #define XACQUIRE_PREFIX (0xf2 | 0x200)
8539 #define XRELEASE_PREFIX (0xf3 | 0x400)
8540 #define BND_PREFIX      (0xf2 | 0x400)
8541 #define NOTRACK_PREFIX  (0x3e | 0x100)
8542
8543 static int
8544 ckprefix (instr_info *ins)
8545 {
8546   int newrex, i, length;
8547
8548   i = 0;
8549   length = 0;
8550   /* The maximum instruction length is 15bytes.  */
8551   while (length < MAX_CODE_LENGTH - 1)
8552     {
8553       FETCH_DATA (ins->info, ins->codep + 1);
8554       newrex = 0;
8555       switch (*ins->codep)
8556         {
8557         /* REX prefixes family.  */
8558         case 0x40:
8559         case 0x41:
8560         case 0x42:
8561         case 0x43:
8562         case 0x44:
8563         case 0x45:
8564         case 0x46:
8565         case 0x47:
8566         case 0x48:
8567         case 0x49:
8568         case 0x4a:
8569         case 0x4b:
8570         case 0x4c:
8571         case 0x4d:
8572         case 0x4e:
8573         case 0x4f:
8574           if (ins->address_mode == mode_64bit)
8575             newrex = *ins->codep;
8576           else
8577             return 1;
8578           ins->last_rex_prefix = i;
8579           break;
8580         case 0xf3:
8581           ins->prefixes |= PREFIX_REPZ;
8582           ins->last_repz_prefix = i;
8583           break;
8584         case 0xf2:
8585           ins->prefixes |= PREFIX_REPNZ;
8586           ins->last_repnz_prefix = i;
8587           break;
8588         case 0xf0:
8589           ins->prefixes |= PREFIX_LOCK;
8590           ins->last_lock_prefix = i;
8591           break;
8592         case 0x2e:
8593           ins->prefixes |= PREFIX_CS;
8594           ins->last_seg_prefix = i;
8595           if (ins->address_mode != mode_64bit)
8596             ins->active_seg_prefix = PREFIX_CS;
8597           break;
8598         case 0x36:
8599           ins->prefixes |= PREFIX_SS;
8600           ins->last_seg_prefix = i;
8601           if (ins->address_mode != mode_64bit)
8602             ins->active_seg_prefix = PREFIX_SS;
8603           break;
8604         case 0x3e:
8605           ins->prefixes |= PREFIX_DS;
8606           ins->last_seg_prefix = i;
8607           if (ins->address_mode != mode_64bit)
8608             ins->active_seg_prefix = PREFIX_DS;
8609           break;
8610         case 0x26:
8611           ins->prefixes |= PREFIX_ES;
8612           ins->last_seg_prefix = i;
8613           if (ins->address_mode != mode_64bit)
8614             ins->active_seg_prefix = PREFIX_ES;
8615           break;
8616         case 0x64:
8617           ins->prefixes |= PREFIX_FS;
8618           ins->last_seg_prefix = i;
8619           ins->active_seg_prefix = PREFIX_FS;
8620           break;
8621         case 0x65:
8622           ins->prefixes |= PREFIX_GS;
8623           ins->last_seg_prefix = i;
8624           ins->active_seg_prefix = PREFIX_GS;
8625           break;
8626         case 0x66:
8627           ins->prefixes |= PREFIX_DATA;
8628           ins->last_data_prefix = i;
8629           break;
8630         case 0x67:
8631           ins->prefixes |= PREFIX_ADDR;
8632           ins->last_addr_prefix = i;
8633           break;
8634         case FWAIT_OPCODE:
8635           /* fwait is really an instruction.  If there are prefixes
8636              before the fwait, they belong to the fwait, *not* to the
8637              following instruction.  */
8638           ins->fwait_prefix = i;
8639           if (ins->prefixes || ins->rex)
8640             {
8641               ins->prefixes |= PREFIX_FWAIT;
8642               ins->codep++;
8643               /* This ensures that the previous REX prefixes are noticed
8644                  as unused prefixes, as in the return case below.  */
8645               ins->rex_used = ins->rex;
8646               return 1;
8647             }
8648           ins->prefixes = PREFIX_FWAIT;
8649           break;
8650         default:
8651           return 1;
8652         }
8653       /* Rex is ignored when followed by another prefix.  */
8654       if (ins->rex)
8655         {
8656           ins->rex_used = ins->rex;
8657           return 1;
8658         }
8659       if (*ins->codep != FWAIT_OPCODE)
8660         ins->all_prefixes[i++] = *ins->codep;
8661       ins->rex = newrex;
8662       ins->codep++;
8663       length++;
8664     }
8665   return 0;
8666 }
8667
8668 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
8669    prefix byte.  */
8670
8671 static const char *
8672 prefix_name (instr_info *ins, int pref, int sizeflag)
8673 {
8674   static const char *rexes [16] =
8675     {
8676       "rex",            /* 0x40 */
8677       "rex.B",          /* 0x41 */
8678       "rex.X",          /* 0x42 */
8679       "rex.XB",         /* 0x43 */
8680       "rex.R",          /* 0x44 */
8681       "rex.RB",         /* 0x45 */
8682       "rex.RX",         /* 0x46 */
8683       "rex.RXB",        /* 0x47 */
8684       "rex.W",          /* 0x48 */
8685       "rex.WB",         /* 0x49 */
8686       "rex.WX",         /* 0x4a */
8687       "rex.WXB",        /* 0x4b */
8688       "rex.WR",         /* 0x4c */
8689       "rex.WRB",        /* 0x4d */
8690       "rex.WRX",        /* 0x4e */
8691       "rex.WRXB",       /* 0x4f */
8692     };
8693
8694   switch (pref)
8695     {
8696     /* REX prefixes family.  */
8697     case 0x40:
8698     case 0x41:
8699     case 0x42:
8700     case 0x43:
8701     case 0x44:
8702     case 0x45:
8703     case 0x46:
8704     case 0x47:
8705     case 0x48:
8706     case 0x49:
8707     case 0x4a:
8708     case 0x4b:
8709     case 0x4c:
8710     case 0x4d:
8711     case 0x4e:
8712     case 0x4f:
8713       return rexes [pref - 0x40];
8714     case 0xf3:
8715       return "repz";
8716     case 0xf2:
8717       return "repnz";
8718     case 0xf0:
8719       return "lock";
8720     case 0x2e:
8721       return "cs";
8722     case 0x36:
8723       return "ss";
8724     case 0x3e:
8725       return "ds";
8726     case 0x26:
8727       return "es";
8728     case 0x64:
8729       return "fs";
8730     case 0x65:
8731       return "gs";
8732     case 0x66:
8733       return (sizeflag & DFLAG) ? "data16" : "data32";
8734     case 0x67:
8735       if (ins->address_mode == mode_64bit)
8736         return (sizeflag & AFLAG) ? "addr32" : "addr64";
8737       else
8738         return (sizeflag & AFLAG) ? "addr16" : "addr32";
8739     case FWAIT_OPCODE:
8740       return "fwait";
8741     case REP_PREFIX:
8742       return "rep";
8743     case XACQUIRE_PREFIX:
8744       return "xacquire";
8745     case XRELEASE_PREFIX:
8746       return "xrelease";
8747     case BND_PREFIX:
8748       return "bnd";
8749     case NOTRACK_PREFIX:
8750       return "notrack";
8751     default:
8752       return NULL;
8753     }
8754 }
8755
8756 void
8757 print_i386_disassembler_options (FILE *stream)
8758 {
8759   fprintf (stream, _("\n\
8760 The following i386/x86-64 specific disassembler options are supported for use\n\
8761 with the -M switch (multiple options should be separated by commas):\n"));
8762
8763   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
8764   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
8765   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
8766   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
8767   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
8768   fprintf (stream, _("  att-mnemonic\n"
8769                      "              Display instruction in AT&T mnemonic\n"));
8770   fprintf (stream, _("  intel-mnemonic\n"
8771                      "              Display instruction in Intel mnemonic\n"));
8772   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
8773   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
8774   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
8775   fprintf (stream, _("  data32      Assume 32bit data size\n"));
8776   fprintf (stream, _("  data16      Assume 16bit data size\n"));
8777   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
8778   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
8779   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
8780 }
8781
8782 /* Bad opcode.  */
8783 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
8784
8785 /* Get a pointer to struct dis386 with a valid name.  */
8786
8787 static const struct dis386 *
8788 get_valid_dis386 (const struct dis386 *dp, instr_info *ins)
8789 {
8790   int vindex, vex_table_index;
8791
8792   if (dp->name != NULL)
8793     return dp;
8794
8795   switch (dp->op[0].bytemode)
8796     {
8797     case USE_REG_TABLE:
8798       dp = &reg_table[dp->op[1].bytemode][ins->modrm.reg];
8799       break;
8800
8801     case USE_MOD_TABLE:
8802       vindex = ins->modrm.mod == 0x3 ? 1 : 0;
8803       dp = &mod_table[dp->op[1].bytemode][vindex];
8804       break;
8805
8806     case USE_RM_TABLE:
8807       dp = &rm_table[dp->op[1].bytemode][ins->modrm.rm];
8808       break;
8809
8810     case USE_PREFIX_TABLE:
8811       if (ins->need_vex)
8812         {
8813           /* The prefix in VEX is implicit.  */
8814           switch (ins->vex.prefix)
8815             {
8816             case 0:
8817               vindex = 0;
8818               break;
8819             case REPE_PREFIX_OPCODE:
8820               vindex = 1;
8821               break;
8822             case DATA_PREFIX_OPCODE:
8823               vindex = 2;
8824               break;
8825             case REPNE_PREFIX_OPCODE:
8826               vindex = 3;
8827               break;
8828             default:
8829               abort ();
8830               break;
8831             }
8832         }
8833       else
8834         {
8835           int last_prefix = -1;
8836           int prefix = 0;
8837           vindex = 0;
8838           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
8839              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
8840              last one wins.  */
8841           if ((ins->prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
8842             {
8843               if (ins->last_repz_prefix > ins->last_repnz_prefix)
8844                 {
8845                   vindex = 1;
8846                   prefix = PREFIX_REPZ;
8847                   last_prefix = ins->last_repz_prefix;
8848                 }
8849               else
8850                 {
8851                   vindex = 3;
8852                   prefix = PREFIX_REPNZ;
8853                   last_prefix = ins->last_repnz_prefix;
8854                 }
8855
8856               /* Check if prefix should be ignored.  */
8857               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
8858                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
8859                    & prefix) != 0
8860                   && !prefix_table[dp->op[1].bytemode][vindex].name)
8861                 vindex = 0;
8862             }
8863
8864           if (vindex == 0 && (ins->prefixes & PREFIX_DATA) != 0)
8865             {
8866               vindex = 2;
8867               prefix = PREFIX_DATA;
8868               last_prefix = ins->last_data_prefix;
8869             }
8870
8871           if (vindex != 0)
8872             {
8873               ins->used_prefixes |= prefix;
8874               ins->all_prefixes[last_prefix] = 0;
8875             }
8876         }
8877       dp = &prefix_table[dp->op[1].bytemode][vindex];
8878       break;
8879
8880     case USE_X86_64_TABLE:
8881       vindex = ins->address_mode == mode_64bit ? 1 : 0;
8882       dp = &x86_64_table[dp->op[1].bytemode][vindex];
8883       break;
8884
8885     case USE_3BYTE_TABLE:
8886       FETCH_DATA (ins->info, ins->codep + 2);
8887       vindex = *ins->codep++;
8888       dp = &three_byte_table[dp->op[1].bytemode][vindex];
8889       ins->end_codep = ins->codep;
8890       ins->modrm.mod = (*ins->codep >> 6) & 3;
8891       ins->modrm.reg = (*ins->codep >> 3) & 7;
8892       ins->modrm.rm = *ins->codep & 7;
8893       break;
8894
8895     case USE_VEX_LEN_TABLE:
8896       if (!ins->need_vex)
8897         abort ();
8898
8899       switch (ins->vex.length)
8900         {
8901         case 128:
8902           vindex = 0;
8903           break;
8904         case 512:
8905           /* This allows re-using in particular table entries where only
8906              128-bit operand size (VEX.L=0 / EVEX.L'L=0) are valid.  */
8907           if (ins->vex.evex)
8908             {
8909         case 256:
8910               vindex = 1;
8911               break;
8912             }
8913         /* Fall through.  */
8914         default:
8915           abort ();
8916           break;
8917         }
8918
8919       dp = &vex_len_table[dp->op[1].bytemode][vindex];
8920       break;
8921
8922     case USE_EVEX_LEN_TABLE:
8923       if (!ins->vex.evex)
8924         abort ();
8925
8926       switch (ins->vex.length)
8927         {
8928         case 128:
8929           vindex = 0;
8930           break;
8931         case 256:
8932           vindex = 1;
8933           break;
8934         case 512:
8935           vindex = 2;
8936           break;
8937         default:
8938           abort ();
8939           break;
8940         }
8941
8942       dp = &evex_len_table[dp->op[1].bytemode][vindex];
8943       break;
8944
8945     case USE_XOP_8F_TABLE:
8946       FETCH_DATA (ins->info, ins->codep + 3);
8947       ins->rex = ~(*ins->codep >> 5) & 0x7;
8948
8949       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
8950       switch ((*ins->codep & 0x1f))
8951         {
8952         default:
8953           dp = &bad_opcode;
8954           return dp;
8955         case 0x8:
8956           vex_table_index = XOP_08;
8957           break;
8958         case 0x9:
8959           vex_table_index = XOP_09;
8960           break;
8961         case 0xa:
8962           vex_table_index = XOP_0A;
8963           break;
8964         }
8965       ins->codep++;
8966       ins->vex.w = *ins->codep & 0x80;
8967       if (ins->vex.w && ins->address_mode == mode_64bit)
8968         ins->rex |= REX_W;
8969
8970       ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
8971       if (ins->address_mode != mode_64bit)
8972         {
8973           /* In 16/32-bit mode REX_B is silently ignored.  */
8974           ins->rex &= ~REX_B;
8975         }
8976
8977       ins->vex.length = (*ins->codep & 0x4) ? 256 : 128;
8978       switch ((*ins->codep & 0x3))
8979         {
8980         case 0:
8981           break;
8982         case 1:
8983           ins->vex.prefix = DATA_PREFIX_OPCODE;
8984           break;
8985         case 2:
8986           ins->vex.prefix = REPE_PREFIX_OPCODE;
8987           break;
8988         case 3:
8989           ins->vex.prefix = REPNE_PREFIX_OPCODE;
8990           break;
8991         }
8992       ins->need_vex = true;
8993       ins->codep++;
8994       vindex = *ins->codep++;
8995       dp = &xop_table[vex_table_index][vindex];
8996
8997       ins->end_codep = ins->codep;
8998       FETCH_DATA (ins->info, ins->codep + 1);
8999       ins->modrm.mod = (*ins->codep >> 6) & 3;
9000       ins->modrm.reg = (*ins->codep >> 3) & 7;
9001       ins->modrm.rm = *ins->codep & 7;
9002
9003       /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid
9004          having to decode the bits for every otherwise valid encoding.  */
9005       if (ins->vex.prefix)
9006         return &bad_opcode;
9007       break;
9008
9009     case USE_VEX_C4_TABLE:
9010       /* VEX prefix.  */
9011       FETCH_DATA (ins->info, ins->codep + 3);
9012       ins->rex = ~(*ins->codep >> 5) & 0x7;
9013       switch ((*ins->codep & 0x1f))
9014         {
9015         default:
9016           dp = &bad_opcode;
9017           return dp;
9018         case 0x1:
9019           vex_table_index = VEX_0F;
9020           break;
9021         case 0x2:
9022           vex_table_index = VEX_0F38;
9023           break;
9024         case 0x3:
9025           vex_table_index = VEX_0F3A;
9026           break;
9027         }
9028       ins->codep++;
9029       ins->vex.w = *ins->codep & 0x80;
9030       if (ins->address_mode == mode_64bit)
9031         {
9032           if (ins->vex.w)
9033             ins->rex |= REX_W;
9034         }
9035       else
9036         {
9037           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
9038              is ignored, other REX bits are 0 and the highest bit in
9039              VEX.vvvv is also ignored (but we mustn't clear it here).  */
9040           ins->rex = 0;
9041         }
9042       ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
9043       ins->vex.length = (*ins->codep & 0x4) ? 256 : 128;
9044       switch ((*ins->codep & 0x3))
9045         {
9046         case 0:
9047           break;
9048         case 1:
9049           ins->vex.prefix = DATA_PREFIX_OPCODE;
9050           break;
9051         case 2:
9052           ins->vex.prefix = REPE_PREFIX_OPCODE;
9053           break;
9054         case 3:
9055           ins->vex.prefix = REPNE_PREFIX_OPCODE;
9056           break;
9057         }
9058       ins->need_vex = true;
9059       ins->codep++;
9060       vindex = *ins->codep++;
9061       dp = &vex_table[vex_table_index][vindex];
9062       ins->end_codep = ins->codep;
9063       /* There is no MODRM byte for VEX0F 77.  */
9064       if (vex_table_index != VEX_0F || vindex != 0x77)
9065         {
9066           FETCH_DATA (ins->info, ins->codep + 1);
9067           ins->modrm.mod = (*ins->codep >> 6) & 3;
9068           ins->modrm.reg = (*ins->codep >> 3) & 7;
9069           ins->modrm.rm = *ins->codep & 7;
9070         }
9071       break;
9072
9073     case USE_VEX_C5_TABLE:
9074       /* VEX prefix.  */
9075       FETCH_DATA (ins->info, ins->codep + 2);
9076       ins->rex = (*ins->codep & 0x80) ? 0 : REX_R;
9077
9078       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
9079          VEX.vvvv is 1.  */
9080       ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
9081       ins->vex.length = (*ins->codep & 0x4) ? 256 : 128;
9082       switch ((*ins->codep & 0x3))
9083         {
9084         case 0:
9085           break;
9086         case 1:
9087           ins->vex.prefix = DATA_PREFIX_OPCODE;
9088           break;
9089         case 2:
9090           ins->vex.prefix = REPE_PREFIX_OPCODE;
9091           break;
9092         case 3:
9093           ins->vex.prefix = REPNE_PREFIX_OPCODE;
9094           break;
9095         }
9096       ins->need_vex = true;
9097       ins->codep++;
9098       vindex = *ins->codep++;
9099       dp = &vex_table[dp->op[1].bytemode][vindex];
9100       ins->end_codep = ins->codep;
9101       /* There is no MODRM byte for VEX 77.  */
9102       if (vindex != 0x77)
9103         {
9104           FETCH_DATA (ins->info, ins->codep + 1);
9105           ins->modrm.mod = (*ins->codep >> 6) & 3;
9106           ins->modrm.reg = (*ins->codep >> 3) & 7;
9107           ins->modrm.rm = *ins->codep & 7;
9108         }
9109       break;
9110
9111     case USE_VEX_W_TABLE:
9112       if (!ins->need_vex)
9113         abort ();
9114
9115       dp = &vex_w_table[dp->op[1].bytemode][ins->vex.w];
9116       break;
9117
9118     case USE_EVEX_TABLE:
9119       ins->two_source_ops = false;
9120       /* EVEX prefix.  */
9121       ins->vex.evex = true;
9122       FETCH_DATA (ins->info, ins->codep + 4);
9123       /* The first byte after 0x62.  */
9124       ins->rex = ~(*ins->codep >> 5) & 0x7;
9125       ins->vex.r = *ins->codep & 0x10;
9126       switch ((*ins->codep & 0xf))
9127         {
9128         default:
9129           return &bad_opcode;
9130         case 0x1:
9131           vex_table_index = EVEX_0F;
9132           break;
9133         case 0x2:
9134           vex_table_index = EVEX_0F38;
9135           break;
9136         case 0x3:
9137           vex_table_index = EVEX_0F3A;
9138           break;
9139         case 0x5:
9140           vex_table_index = EVEX_MAP5;
9141           break;
9142         case 0x6:
9143           vex_table_index = EVEX_MAP6;
9144           break;
9145         }
9146
9147       /* The second byte after 0x62.  */
9148       ins->codep++;
9149       ins->vex.w = *ins->codep & 0x80;
9150       if (ins->vex.w && ins->address_mode == mode_64bit)
9151         ins->rex |= REX_W;
9152
9153       ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
9154
9155       /* The U bit.  */
9156       if (!(*ins->codep & 0x4))
9157         return &bad_opcode;
9158
9159       switch ((*ins->codep & 0x3))
9160         {
9161         case 0:
9162           break;
9163         case 1:
9164           ins->vex.prefix = DATA_PREFIX_OPCODE;
9165           break;
9166         case 2:
9167           ins->vex.prefix = REPE_PREFIX_OPCODE;
9168           break;
9169         case 3:
9170           ins->vex.prefix = REPNE_PREFIX_OPCODE;
9171           break;
9172         }
9173
9174       /* The third byte after 0x62.  */
9175       ins->codep++;
9176
9177       /* Remember the static rounding bits.  */
9178       ins->vex.ll = (*ins->codep >> 5) & 3;
9179       ins->vex.b = *ins->codep & 0x10;
9180
9181       ins->vex.v = *ins->codep & 0x8;
9182       ins->vex.mask_register_specifier = *ins->codep & 0x7;
9183       ins->vex.zeroing = *ins->codep & 0x80;
9184
9185       if (ins->address_mode != mode_64bit)
9186         {
9187           /* In 16/32-bit mode silently ignore following bits.  */
9188           ins->rex &= ~REX_B;
9189           ins->vex.r = true;
9190         }
9191
9192       ins->need_vex = true;
9193       ins->codep++;
9194       vindex = *ins->codep++;
9195       dp = &evex_table[vex_table_index][vindex];
9196       ins->end_codep = ins->codep;
9197       FETCH_DATA (ins->info, ins->codep + 1);
9198       ins->modrm.mod = (*ins->codep >> 6) & 3;
9199       ins->modrm.reg = (*ins->codep >> 3) & 7;
9200       ins->modrm.rm = *ins->codep & 7;
9201
9202       /* Set vector length.  */
9203       if (ins->modrm.mod == 3 && ins->vex.b)
9204         ins->vex.length = 512;
9205       else
9206         {
9207           switch (ins->vex.ll)
9208             {
9209             case 0x0:
9210               ins->vex.length = 128;
9211               break;
9212             case 0x1:
9213               ins->vex.length = 256;
9214               break;
9215             case 0x2:
9216               ins->vex.length = 512;
9217               break;
9218             default:
9219               return &bad_opcode;
9220             }
9221         }
9222       break;
9223
9224     case 0:
9225       dp = &bad_opcode;
9226       break;
9227
9228     default:
9229       abort ();
9230     }
9231
9232   if (dp->name != NULL)
9233     return dp;
9234   else
9235     return get_valid_dis386 (dp, ins);
9236 }
9237
9238 static void
9239 get_sib (instr_info *ins, int sizeflag)
9240 {
9241   /* If modrm.mod == 3, operand must be register.  */
9242   if (ins->need_modrm
9243       && ((sizeflag & AFLAG) || ins->address_mode == mode_64bit)
9244       && ins->modrm.mod != 3
9245       && ins->modrm.rm == 4)
9246     {
9247       FETCH_DATA (ins->info, ins->codep + 2);
9248       ins->sib.index = (ins->codep[1] >> 3) & 7;
9249       ins->sib.scale = (ins->codep[1] >> 6) & 3;
9250       ins->sib.base = ins->codep[1] & 7;
9251       ins->has_sib = true;
9252     }
9253   else
9254     ins->has_sib = false;
9255 }
9256
9257 /* Like oappend (below), but S is a string starting with '%' or '$'.  In
9258    Intel syntax, the '%' or '$' is elided.  STYLE is used when displaying
9259    this part of the output in the disassembler.
9260
9261    This function should not be used directly from the general disassembler
9262    code, instead the helpers oappend_register and oappend_immediate should
9263    be called as appropriate.  */
9264
9265 static void
9266 oappend_maybe_intel_with_style (instr_info *ins, const char *s,
9267                                 enum disassembler_style style)
9268 {
9269   oappend_with_style (ins, s + ins->intel_syntax, style);
9270 }
9271
9272 /* Like oappend_maybe_intel_with_style above, but called when S is the
9273    name of a register.  */
9274
9275 static void
9276 oappend_register (instr_info *ins, const char *s)
9277 {
9278   oappend_maybe_intel_with_style (ins, s, dis_style_register);
9279 }
9280
9281 /* Like oappend_maybe_intel_with_style above, but called when S represents
9282    an immediate.  */
9283
9284 static void
9285 oappend_immediate (instr_info *ins, const char *s)
9286 {
9287   oappend_maybe_intel_with_style (ins, s, dis_style_immediate);
9288 }
9289
9290 /* Wrap around a call to INS->info->fprintf_styled_func, printing FMT.
9291    STYLE is the default style to use in the fprintf_styled_func calls,
9292    however, FMT might include embedded style markers (see oappend_style),
9293    these embedded markers are not printed, but instead change the style
9294    used in the next fprintf_styled_func call.
9295
9296    Return non-zero to indicate the print call was a success.  */
9297
9298 static int ATTRIBUTE_PRINTF_3
9299 i386_dis_printf (instr_info *ins, enum disassembler_style style,
9300                  const char *fmt, ...)
9301 {
9302   va_list ap;
9303   enum disassembler_style curr_style = style;
9304   char *start, *curr;
9305   char staging_area[100];
9306   int res;
9307
9308   va_start (ap, fmt);
9309   res = vsnprintf (staging_area, sizeof (staging_area), fmt, ap);
9310   va_end (ap);
9311
9312   if (res < 0)
9313     return res;
9314
9315   if ((size_t) res >= sizeof (staging_area))
9316     abort ();
9317
9318   start = curr = staging_area;
9319
9320   do
9321     {
9322       if (*curr == '\0'
9323           || (*curr == STYLE_MARKER_CHAR
9324               && ISXDIGIT (*(curr + 1))
9325               && *(curr + 2) == STYLE_MARKER_CHAR))
9326         {
9327           /* Output content between our START position and CURR.  */
9328           int len = curr - start;
9329           int n = (*ins->info->fprintf_styled_func) (ins->info->stream,
9330                                                      curr_style,
9331                                                      "%.*s", len, start);
9332           if (n < 0)
9333             {
9334               res = n;
9335               break;
9336             }
9337
9338           if (*curr == '\0')
9339             break;
9340
9341           /* Skip over the initial STYLE_MARKER_CHAR.  */
9342           ++curr;
9343
9344           /* Update the CURR_STYLE.  As there are less than 16 styles, it
9345              is possible, that if the input is corrupted in some way, that
9346              we might set CURR_STYLE to an invalid value.  Don't worry
9347              though, we check for this situation.  */
9348           if (*curr >= '0' && *curr <= '9')
9349             curr_style = (enum disassembler_style) (*curr - '0');
9350           else if (*curr >= 'a' && *curr <= 'f')
9351             curr_style = (enum disassembler_style) (*curr - 'a' + 10);
9352           else
9353             curr_style = dis_style_text;
9354
9355           /* Check for an invalid style having been selected.  This should
9356              never happen, but it doesn't hurt to be a little paranoid.  */
9357           if (curr_style > dis_style_comment_start)
9358             curr_style = dis_style_text;
9359
9360           /* Skip the hex character, and the closing STYLE_MARKER_CHAR.  */
9361           curr += 2;
9362
9363           /* Reset the START to after the style marker.  */
9364           start = curr;
9365         }
9366       else
9367         ++curr;
9368     }
9369   while (true);
9370
9371   return res;
9372 }
9373
9374 static int
9375 print_insn (bfd_vma pc, disassemble_info *info, int intel_syntax)
9376 {
9377   const struct dis386 *dp;
9378   int i;
9379   char *op_txt[MAX_OPERANDS];
9380   int needcomma;
9381   bool intel_swap_2_3;
9382   int sizeflag, orig_sizeflag;
9383   const char *p;
9384   struct dis_private priv;
9385   int prefix_length;
9386   int op_count;
9387   instr_info ins = {
9388     .info = info,
9389     .intel_syntax = intel_syntax >= 0
9390                     ? intel_syntax
9391                     : (info->mach & bfd_mach_i386_intel_syntax) != 0,
9392     .intel_mnemonic = !SYSV386_COMPAT,
9393     .op_index[0 ... MAX_OPERANDS - 1] = -1,
9394     .start_pc = pc,
9395     .start_codep = priv.the_buffer,
9396     .codep = priv.the_buffer,
9397     .obufp = ins.obuf,
9398     .last_lock_prefix = -1,
9399     .last_repz_prefix = -1,
9400     .last_repnz_prefix = -1,
9401     .last_data_prefix = -1,
9402     .last_addr_prefix = -1,
9403     .last_rex_prefix = -1,
9404     .last_seg_prefix = -1,
9405     .fwait_prefix = -1,
9406   };
9407   char op_out[MAX_OPERANDS][100];
9408
9409   priv.orig_sizeflag = AFLAG | DFLAG;
9410   if ((info->mach & bfd_mach_i386_i386) != 0)
9411     ins.address_mode = mode_32bit;
9412   else if (info->mach == bfd_mach_i386_i8086)
9413     {
9414       ins.address_mode = mode_16bit;
9415       priv.orig_sizeflag = 0;
9416     }
9417   else
9418     ins.address_mode = mode_64bit;
9419
9420   for (p = info->disassembler_options; p != NULL;)
9421     {
9422       if (startswith (p, "amd64"))
9423         ins.isa64 = amd64;
9424       else if (startswith (p, "intel64"))
9425         ins.isa64 = intel64;
9426       else if (startswith (p, "x86-64"))
9427         {
9428           ins.address_mode = mode_64bit;
9429           priv.orig_sizeflag |= AFLAG | DFLAG;
9430         }
9431       else if (startswith (p, "i386"))
9432         {
9433           ins.address_mode = mode_32bit;
9434           priv.orig_sizeflag |= AFLAG | DFLAG;
9435         }
9436       else if (startswith (p, "i8086"))
9437         {
9438           ins.address_mode = mode_16bit;
9439           priv.orig_sizeflag &= ~(AFLAG | DFLAG);
9440         }
9441       else if (startswith (p, "intel"))
9442         {
9443           ins.intel_syntax = 1;
9444           if (startswith (p + 5, "-mnemonic"))
9445             ins.intel_mnemonic = true;
9446         }
9447       else if (startswith (p, "att"))
9448         {
9449           ins.intel_syntax = 0;
9450           if (startswith (p + 3, "-mnemonic"))
9451             ins.intel_mnemonic = false;
9452         }
9453       else if (startswith (p, "addr"))
9454         {
9455           if (ins.address_mode == mode_64bit)
9456             {
9457               if (p[4] == '3' && p[5] == '2')
9458                 priv.orig_sizeflag &= ~AFLAG;
9459               else if (p[4] == '6' && p[5] == '4')
9460                 priv.orig_sizeflag |= AFLAG;
9461             }
9462           else
9463             {
9464               if (p[4] == '1' && p[5] == '6')
9465                 priv.orig_sizeflag &= ~AFLAG;
9466               else if (p[4] == '3' && p[5] == '2')
9467                 priv.orig_sizeflag |= AFLAG;
9468             }
9469         }
9470       else if (startswith (p, "data"))
9471         {
9472           if (p[4] == '1' && p[5] == '6')
9473             priv.orig_sizeflag &= ~DFLAG;
9474           else if (p[4] == '3' && p[5] == '2')
9475             priv.orig_sizeflag |= DFLAG;
9476         }
9477       else if (startswith (p, "suffix"))
9478         priv.orig_sizeflag |= SUFFIX_ALWAYS;
9479
9480       p = strchr (p, ',');
9481       if (p != NULL)
9482         p++;
9483     }
9484
9485   if (ins.address_mode == mode_64bit && sizeof (bfd_vma) < 8)
9486     {
9487       i386_dis_printf (&ins, dis_style_text, _("64-bit address is disabled"));
9488       return -1;
9489     }
9490
9491   if (ins.intel_syntax)
9492     {
9493       ins.open_char = '[';
9494       ins.close_char = ']';
9495       ins.separator_char = '+';
9496       ins.scale_char = '*';
9497     }
9498   else
9499     {
9500       ins.open_char = '(';
9501       ins.close_char =  ')';
9502       ins.separator_char = ',';
9503       ins.scale_char = ',';
9504     }
9505
9506   /* The output looks better if we put 7 bytes on a line, since that
9507      puts most long word instructions on a single line.  */
9508   info->bytes_per_line = 7;
9509
9510   info->private_data = &priv;
9511   priv.max_fetched = priv.the_buffer;
9512   priv.insn_start = pc;
9513
9514   for (i = 0; i < MAX_OPERANDS; ++i)
9515     {
9516       op_out[i][0] = 0;
9517       ins.op_out[i] = op_out[i];
9518     }
9519
9520   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
9521     {
9522       const char *name;
9523
9524       /* Getting here means we tried for data but didn't get it.  That
9525          means we have an incomplete instruction of some sort.  Just
9526          print the first byte as a prefix or a .byte pseudo-op.  */
9527       if (ins.codep > priv.the_buffer)
9528         {
9529           name = prefix_name (&ins, priv.the_buffer[0], priv.orig_sizeflag);
9530           if (name != NULL)
9531             i386_dis_printf (&ins, dis_style_mnemonic, "%s", name);
9532           else
9533             {
9534               /* Just print the first byte as a .byte instruction.  */
9535               i386_dis_printf (&ins, dis_style_assembler_directive,
9536                                ".byte ");
9537               i386_dis_printf (&ins, dis_style_immediate, "0x%x",
9538                                (unsigned int) priv.the_buffer[0]);
9539             }
9540
9541           return 1;
9542         }
9543
9544       return -1;
9545     }
9546
9547   sizeflag = priv.orig_sizeflag;
9548
9549   if (!ckprefix (&ins) || ins.rex_used)
9550     {
9551       /* Too many prefixes or unused REX prefixes.  */
9552       for (i = 0;
9553            i < (int) ARRAY_SIZE (ins.all_prefixes) && ins.all_prefixes[i];
9554            i++)
9555         i386_dis_printf (&ins, dis_style_mnemonic, "%s%s",
9556                          (i == 0 ? "" : " "),
9557                          prefix_name (&ins, ins.all_prefixes[i], sizeflag));
9558       return i;
9559     }
9560
9561   ins.insn_codep = ins.codep;
9562
9563   FETCH_DATA (info, ins.codep + 1);
9564   ins.two_source_ops = (*ins.codep == 0x62) || (*ins.codep == 0xc8);
9565
9566   if (((ins.prefixes & PREFIX_FWAIT)
9567        && ((*ins.codep < 0xd8) || (*ins.codep > 0xdf))))
9568     {
9569       /* Handle ins.prefixes before fwait.  */
9570       for (i = 0; i < ins.fwait_prefix && ins.all_prefixes[i];
9571            i++)
9572         i386_dis_printf (&ins, dis_style_mnemonic, "%s ",
9573                          prefix_name (&ins, ins.all_prefixes[i], sizeflag));
9574       i386_dis_printf (&ins, dis_style_mnemonic, "fwait");
9575       return i + 1;
9576     }
9577
9578   if (*ins.codep == 0x0f)
9579     {
9580       unsigned char threebyte;
9581
9582       ins.codep++;
9583       FETCH_DATA (info, ins.codep + 1);
9584       threebyte = *ins.codep;
9585       dp = &dis386_twobyte[threebyte];
9586       ins.need_modrm = twobyte_has_modrm[threebyte];
9587       ins.codep++;
9588     }
9589   else
9590     {
9591       dp = &dis386[*ins.codep];
9592       ins.need_modrm = onebyte_has_modrm[*ins.codep];
9593       ins.codep++;
9594     }
9595
9596   /* Save sizeflag for printing the extra ins.prefixes later before updating
9597      it for mnemonic and operand processing.  The prefix names depend
9598      only on the address mode.  */
9599   orig_sizeflag = sizeflag;
9600   if (ins.prefixes & PREFIX_ADDR)
9601     sizeflag ^= AFLAG;
9602   if ((ins.prefixes & PREFIX_DATA))
9603     sizeflag ^= DFLAG;
9604
9605   ins.end_codep = ins.codep;
9606   if (ins.need_modrm)
9607     {
9608       FETCH_DATA (info, ins.codep + 1);
9609       ins.modrm.mod = (*ins.codep >> 6) & 3;
9610       ins.modrm.reg = (*ins.codep >> 3) & 7;
9611       ins.modrm.rm = *ins.codep & 7;
9612     }
9613
9614   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
9615     {
9616       get_sib (&ins, sizeflag);
9617       dofloat (&ins, sizeflag);
9618     }
9619   else
9620     {
9621       dp = get_valid_dis386 (dp, &ins);
9622       if (dp != NULL && putop (&ins, dp->name, sizeflag) == 0)
9623         {
9624           get_sib (&ins, sizeflag);
9625           for (i = 0; i < MAX_OPERANDS; ++i)
9626             {
9627               ins.obufp = ins.op_out[i];
9628               ins.op_ad = MAX_OPERANDS - 1 - i;
9629               if (dp->op[i].rtn)
9630                 (*dp->op[i].rtn) (&ins, dp->op[i].bytemode, sizeflag);
9631               /* For EVEX instruction after the last operand masking
9632                  should be printed.  */
9633               if (i == 0 && ins.vex.evex)
9634                 {
9635                   /* Don't print {%k0}.  */
9636                   if (ins.vex.mask_register_specifier)
9637                     {
9638                       const char *reg_name
9639                         = att_names_mask[ins.vex.mask_register_specifier];
9640
9641                       oappend (&ins, "{");
9642                       oappend_register (&ins, reg_name);
9643                       oappend (&ins, "}");
9644                     }
9645                   if (ins.vex.zeroing)
9646                     oappend (&ins, "{z}");
9647
9648                   /* S/G insns require a mask and don't allow
9649                      zeroing-masking.  */
9650                   if ((dp->op[0].bytemode == vex_vsib_d_w_dq_mode
9651                        || dp->op[0].bytemode == vex_vsib_q_w_dq_mode)
9652                       && (ins.vex.mask_register_specifier == 0
9653                           || ins.vex.zeroing))
9654                     oappend (&ins, "/(bad)");
9655                 }
9656             }
9657
9658           /* Check whether rounding control was enabled for an insn not
9659              supporting it.  */
9660           if (ins.modrm.mod == 3 && ins.vex.b
9661               && !(ins.evex_used & EVEX_b_used))
9662             {
9663               for (i = 0; i < MAX_OPERANDS; ++i)
9664                 {
9665                   ins.obufp = ins.op_out[i];
9666                   if (*ins.obufp)
9667                     continue;
9668                   oappend (&ins, names_rounding[ins.vex.ll]);
9669                   oappend (&ins, "bad}");
9670                   break;
9671                 }
9672             }
9673         }
9674     }
9675
9676   /* Clear instruction information.  */
9677   info->insn_info_valid = 0;
9678   info->branch_delay_insns = 0;
9679   info->data_size = 0;
9680   info->insn_type = dis_noninsn;
9681   info->target = 0;
9682   info->target2 = 0;
9683
9684   /* Reset jump operation indicator.  */
9685   ins.op_is_jump = false;
9686   {
9687     int jump_detection = 0;
9688
9689     /* Extract flags.  */
9690     for (i = 0; i < MAX_OPERANDS; ++i)
9691       {
9692         if ((dp->op[i].rtn == OP_J)
9693             || (dp->op[i].rtn == OP_indirE))
9694           jump_detection |= 1;
9695         else if ((dp->op[i].rtn == BND_Fixup)
9696                  || (!dp->op[i].rtn && !dp->op[i].bytemode))
9697           jump_detection |= 2;
9698         else if ((dp->op[i].bytemode == cond_jump_mode)
9699                  || (dp->op[i].bytemode == loop_jcxz_mode))
9700           jump_detection |= 4;
9701       }
9702
9703     /* Determine if this is a jump or branch.  */
9704     if ((jump_detection & 0x3) == 0x3)
9705       {
9706         ins.op_is_jump = true;
9707         if (jump_detection & 0x4)
9708           info->insn_type = dis_condbranch;
9709         else
9710           info->insn_type = (dp->name && !strncmp (dp->name, "call", 4))
9711             ? dis_jsr : dis_branch;
9712       }
9713   }
9714
9715   /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
9716      are all 0s in inverted form.  */
9717   if (ins.need_vex && ins.vex.register_specifier != 0)
9718     {
9719       i386_dis_printf (&ins, dis_style_text, "(bad)");
9720       return ins.end_codep - priv.the_buffer;
9721     }
9722
9723   /* If EVEX.z is set, there must be an actual mask register in use.  */
9724   if (ins.vex.zeroing && ins.vex.mask_register_specifier == 0)
9725     {
9726       i386_dis_printf (&ins, dis_style_text, "(bad)");
9727       return ins.end_codep - priv.the_buffer;
9728     }
9729
9730   switch (dp->prefix_requirement)
9731     {
9732     case PREFIX_DATA:
9733       /* If only the data prefix is marked as mandatory, its absence renders
9734          the encoding invalid.  Most other PREFIX_OPCODE rules still apply.  */
9735       if (ins.need_vex ? !ins.vex.prefix : !(ins.prefixes & PREFIX_DATA))
9736         {
9737           i386_dis_printf (&ins, dis_style_text, "(bad)");
9738           return ins.end_codep - priv.the_buffer;
9739         }
9740       ins.used_prefixes |= PREFIX_DATA;
9741       /* Fall through.  */
9742     case PREFIX_OPCODE:
9743       /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
9744          unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
9745          used by putop and MMX/SSE operand and may be overridden by the
9746          PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
9747          separately.  */
9748       if (((ins.need_vex
9749             ? ins.vex.prefix == REPE_PREFIX_OPCODE
9750               || ins.vex.prefix == REPNE_PREFIX_OPCODE
9751             : (ins.prefixes
9752                & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
9753            && (ins.used_prefixes
9754                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
9755           || (((ins.need_vex
9756                 ? ins.vex.prefix == DATA_PREFIX_OPCODE
9757                 : ((ins.prefixes
9758                     & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
9759                    == PREFIX_DATA))
9760                && (ins.used_prefixes & PREFIX_DATA) == 0))
9761           || (ins.vex.evex && dp->prefix_requirement != PREFIX_DATA
9762               && !ins.vex.w != !(ins.used_prefixes & PREFIX_DATA)))
9763         {
9764           i386_dis_printf (&ins, dis_style_text, "(bad)");
9765           return ins.end_codep - priv.the_buffer;
9766         }
9767       break;
9768
9769     case PREFIX_IGNORED:
9770       /* Zap data size and rep prefixes from used_prefixes and reinstate their
9771          origins in all_prefixes.  */
9772       ins.used_prefixes &= ~PREFIX_OPCODE;
9773       if (ins.last_data_prefix >= 0)
9774         ins.all_prefixes[ins.last_data_prefix] = 0x66;
9775       if (ins.last_repz_prefix >= 0)
9776         ins.all_prefixes[ins.last_repz_prefix] = 0xf3;
9777       if (ins.last_repnz_prefix >= 0)
9778         ins.all_prefixes[ins.last_repnz_prefix] = 0xf2;
9779       break;
9780     }
9781
9782   /* Check if the REX prefix is used.  */
9783   if ((ins.rex ^ ins.rex_used) == 0
9784       && !ins.need_vex && ins.last_rex_prefix >= 0)
9785     ins.all_prefixes[ins.last_rex_prefix] = 0;
9786
9787   /* Check if the SEG prefix is used.  */
9788   if ((ins.prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
9789                        | PREFIX_FS | PREFIX_GS)) != 0
9790       && (ins.used_prefixes & ins.active_seg_prefix) != 0)
9791     ins.all_prefixes[ins.last_seg_prefix] = 0;
9792
9793   /* Check if the ADDR prefix is used.  */
9794   if ((ins.prefixes & PREFIX_ADDR) != 0
9795       && (ins.used_prefixes & PREFIX_ADDR) != 0)
9796     ins.all_prefixes[ins.last_addr_prefix] = 0;
9797
9798   /* Check if the DATA prefix is used.  */
9799   if ((ins.prefixes & PREFIX_DATA) != 0
9800       && (ins.used_prefixes & PREFIX_DATA) != 0
9801       && !ins.need_vex)
9802     ins.all_prefixes[ins.last_data_prefix] = 0;
9803
9804   /* Print the extra ins.prefixes.  */
9805   prefix_length = 0;
9806   for (i = 0; i < (int) ARRAY_SIZE (ins.all_prefixes); i++)
9807     if (ins.all_prefixes[i])
9808       {
9809         const char *name;
9810         name = prefix_name (&ins, ins.all_prefixes[i], orig_sizeflag);
9811         if (name == NULL)
9812           abort ();
9813         prefix_length += strlen (name) + 1;
9814         i386_dis_printf (&ins, dis_style_mnemonic, "%s ", name);
9815       }
9816
9817   /* Check maximum code length.  */
9818   if ((ins.codep - ins.start_codep) > MAX_CODE_LENGTH)
9819     {
9820       i386_dis_printf (&ins, dis_style_text, "(bad)");
9821       return MAX_CODE_LENGTH;
9822     }
9823
9824   /* Calculate the number of operands this instruction has.  */
9825   op_count = 0;
9826   for (i = 0; i < MAX_OPERANDS; ++i)
9827     if (*ins->op_out[i] != '\0')
9828       ++op_count;
9829
9830   /* Calculate the number of spaces to print after the mnemonic.  */
9831   ins.obufp = ins.mnemonicendp;
9832   if (op_count > 0)
9833     {
9834       i = strlen (ins.obuf) + prefix_length;
9835       if (i < 7)
9836         i = 7 - i;
9837       else
9838         i = 1;
9839     }
9840   else
9841     i = 0;
9842
9843   /* Print the instruction mnemonic along with any trailing whitespace.  */
9844   i386_dis_printf (&ins, dis_style_mnemonic, "%s%*s", ins.obuf, i, "");
9845
9846   /* The enter and bound instructions are printed with operands in the same
9847      order as the intel book; everything else is printed in reverse order.  */
9848   intel_swap_2_3 = false;
9849   if (ins.intel_syntax || ins.two_source_ops)
9850     {
9851       for (i = 0; i < MAX_OPERANDS; ++i)
9852         op_txt[i] = ins.op_out[i];
9853
9854       if (ins.intel_syntax && dp && dp->op[2].rtn == OP_Rounding
9855           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
9856         {
9857           op_txt[2] = ins.op_out[3];
9858           op_txt[3] = ins.op_out[2];
9859           intel_swap_2_3 = true;
9860         }
9861
9862       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
9863         {
9864           bool riprel;
9865
9866           ins.op_ad = ins.op_index[i];
9867           ins.op_index[i] = ins.op_index[MAX_OPERANDS - 1 - i];
9868           ins.op_index[MAX_OPERANDS - 1 - i] = ins.op_ad;
9869           riprel = ins.op_riprel[i];
9870           ins.op_riprel[i] = ins.op_riprel[MAX_OPERANDS - 1 - i];
9871           ins.op_riprel[MAX_OPERANDS - 1 - i] = riprel;
9872         }
9873     }
9874   else
9875     {
9876       for (i = 0; i < MAX_OPERANDS; ++i)
9877         op_txt[MAX_OPERANDS - 1 - i] = ins.op_out[i];
9878     }
9879
9880   needcomma = 0;
9881   for (i = 0; i < MAX_OPERANDS; ++i)
9882     if (*op_txt[i])
9883       {
9884         /* In Intel syntax embedded rounding / SAE are not separate operands.
9885            Instead they're attached to the prior register operand.  Simply
9886            suppress emission of the comma to achieve that effect.  */
9887         switch (i & -(ins.intel_syntax && dp))
9888           {
9889           case 2:
9890             if (dp->op[2].rtn == OP_Rounding && !intel_swap_2_3)
9891               needcomma = 0;
9892             break;
9893           case 3:
9894             if (dp->op[3].rtn == OP_Rounding || intel_swap_2_3)
9895               needcomma = 0;
9896             break;
9897           }
9898         if (needcomma)
9899           i386_dis_printf (&ins, dis_style_text, ",");
9900         if (ins.op_index[i] != -1 && !ins.op_riprel[i])
9901           {
9902             bfd_vma target = (bfd_vma) ins.op_address[ins.op_index[i]];
9903
9904             if (ins.op_is_jump)
9905               {
9906                 info->insn_info_valid = 1;
9907                 info->branch_delay_insns = 0;
9908                 info->data_size = 0;
9909                 info->target = target;
9910                 info->target2 = 0;
9911               }
9912             (*info->print_address_func) (target, info);
9913           }
9914         else
9915           i386_dis_printf (&ins, dis_style_text, "%s", op_txt[i]);
9916         needcomma = 1;
9917       }
9918
9919   for (i = 0; i < MAX_OPERANDS; i++)
9920     if (ins.op_index[i] != -1 && ins.op_riprel[i])
9921       {
9922         i386_dis_printf (&ins, dis_style_comment_start, "        # ");
9923         (*info->print_address_func)
9924           ((bfd_vma)(ins.start_pc + (ins.codep - ins.start_codep)
9925                      + ins.op_address[ins.op_index[i]]),
9926           info);
9927         break;
9928       }
9929   return ins.codep - priv.the_buffer;
9930 }
9931
9932 /* Here for backwards compatibility.  When gdb stops using
9933    print_insn_i386_att and print_insn_i386_intel these functions can
9934    disappear, and print_insn_i386 be merged into print_insn.  */
9935 int
9936 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
9937 {
9938   return print_insn (pc, info, 0);
9939 }
9940
9941 int
9942 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
9943 {
9944   return print_insn (pc, info, 1);
9945 }
9946
9947 int
9948 print_insn_i386 (bfd_vma pc, disassemble_info *info)
9949 {
9950   return print_insn (pc, info, -1);
9951 }
9952
9953 static const char *float_mem[] = {
9954   /* d8 */
9955   "fadd{s|}",
9956   "fmul{s|}",
9957   "fcom{s|}",
9958   "fcomp{s|}",
9959   "fsub{s|}",
9960   "fsubr{s|}",
9961   "fdiv{s|}",
9962   "fdivr{s|}",
9963   /* d9 */
9964   "fld{s|}",
9965   "(bad)",
9966   "fst{s|}",
9967   "fstp{s|}",
9968   "fldenv{C|C}",
9969   "fldcw",
9970   "fNstenv{C|C}",
9971   "fNstcw",
9972   /* da */
9973   "fiadd{l|}",
9974   "fimul{l|}",
9975   "ficom{l|}",
9976   "ficomp{l|}",
9977   "fisub{l|}",
9978   "fisubr{l|}",
9979   "fidiv{l|}",
9980   "fidivr{l|}",
9981   /* db */
9982   "fild{l|}",
9983   "fisttp{l|}",
9984   "fist{l|}",
9985   "fistp{l|}",
9986   "(bad)",
9987   "fld{t|}",
9988   "(bad)",
9989   "fstp{t|}",
9990   /* dc */
9991   "fadd{l|}",
9992   "fmul{l|}",
9993   "fcom{l|}",
9994   "fcomp{l|}",
9995   "fsub{l|}",
9996   "fsubr{l|}",
9997   "fdiv{l|}",
9998   "fdivr{l|}",
9999   /* dd */
10000   "fld{l|}",
10001   "fisttp{ll|}",
10002   "fst{l||}",
10003   "fstp{l|}",
10004   "frstor{C|C}",
10005   "(bad)",
10006   "fNsave{C|C}",
10007   "fNstsw",
10008   /* de */
10009   "fiadd{s|}",
10010   "fimul{s|}",
10011   "ficom{s|}",
10012   "ficomp{s|}",
10013   "fisub{s|}",
10014   "fisubr{s|}",
10015   "fidiv{s|}",
10016   "fidivr{s|}",
10017   /* df */
10018   "fild{s|}",
10019   "fisttp{s|}",
10020   "fist{s|}",
10021   "fistp{s|}",
10022   "fbld",
10023   "fild{ll|}",
10024   "fbstp",
10025   "fistp{ll|}",
10026 };
10027
10028 static const unsigned char float_mem_mode[] = {
10029   /* d8 */
10030   d_mode,
10031   d_mode,
10032   d_mode,
10033   d_mode,
10034   d_mode,
10035   d_mode,
10036   d_mode,
10037   d_mode,
10038   /* d9 */
10039   d_mode,
10040   0,
10041   d_mode,
10042   d_mode,
10043   0,
10044   w_mode,
10045   0,
10046   w_mode,
10047   /* da */
10048   d_mode,
10049   d_mode,
10050   d_mode,
10051   d_mode,
10052   d_mode,
10053   d_mode,
10054   d_mode,
10055   d_mode,
10056   /* db */
10057   d_mode,
10058   d_mode,
10059   d_mode,
10060   d_mode,
10061   0,
10062   t_mode,
10063   0,
10064   t_mode,
10065   /* dc */
10066   q_mode,
10067   q_mode,
10068   q_mode,
10069   q_mode,
10070   q_mode,
10071   q_mode,
10072   q_mode,
10073   q_mode,
10074   /* dd */
10075   q_mode,
10076   q_mode,
10077   q_mode,
10078   q_mode,
10079   0,
10080   0,
10081   0,
10082   w_mode,
10083   /* de */
10084   w_mode,
10085   w_mode,
10086   w_mode,
10087   w_mode,
10088   w_mode,
10089   w_mode,
10090   w_mode,
10091   w_mode,
10092   /* df */
10093   w_mode,
10094   w_mode,
10095   w_mode,
10096   w_mode,
10097   t_mode,
10098   q_mode,
10099   t_mode,
10100   q_mode
10101 };
10102
10103 #define ST { OP_ST, 0 }
10104 #define STi { OP_STi, 0 }
10105
10106 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
10107 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
10108 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
10109 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
10110 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
10111 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
10112 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
10113 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
10114 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
10115
10116 static const struct dis386 float_reg[][8] = {
10117   /* d8 */
10118   {
10119     { "fadd",   { ST, STi }, 0 },
10120     { "fmul",   { ST, STi }, 0 },
10121     { "fcom",   { STi }, 0 },
10122     { "fcomp",  { STi }, 0 },
10123     { "fsub",   { ST, STi }, 0 },
10124     { "fsubr",  { ST, STi }, 0 },
10125     { "fdiv",   { ST, STi }, 0 },
10126     { "fdivr",  { ST, STi }, 0 },
10127   },
10128   /* d9 */
10129   {
10130     { "fld",    { STi }, 0 },
10131     { "fxch",   { STi }, 0 },
10132     { FGRPd9_2 },
10133     { Bad_Opcode },
10134     { FGRPd9_4 },
10135     { FGRPd9_5 },
10136     { FGRPd9_6 },
10137     { FGRPd9_7 },
10138   },
10139   /* da */
10140   {
10141     { "fcmovb", { ST, STi }, 0 },
10142     { "fcmove", { ST, STi }, 0 },
10143     { "fcmovbe",{ ST, STi }, 0 },
10144     { "fcmovu", { ST, STi }, 0 },
10145     { Bad_Opcode },
10146     { FGRPda_5 },
10147     { Bad_Opcode },
10148     { Bad_Opcode },
10149   },
10150   /* db */
10151   {
10152     { "fcmovnb",{ ST, STi }, 0 },
10153     { "fcmovne",{ ST, STi }, 0 },
10154     { "fcmovnbe",{ ST, STi }, 0 },
10155     { "fcmovnu",{ ST, STi }, 0 },
10156     { FGRPdb_4 },
10157     { "fucomi", { ST, STi }, 0 },
10158     { "fcomi",  { ST, STi }, 0 },
10159     { Bad_Opcode },
10160   },
10161   /* dc */
10162   {
10163     { "fadd",   { STi, ST }, 0 },
10164     { "fmul",   { STi, ST }, 0 },
10165     { Bad_Opcode },
10166     { Bad_Opcode },
10167     { "fsub{!M|r}",     { STi, ST }, 0 },
10168     { "fsub{M|}",       { STi, ST }, 0 },
10169     { "fdiv{!M|r}",     { STi, ST }, 0 },
10170     { "fdiv{M|}",       { STi, ST }, 0 },
10171   },
10172   /* dd */
10173   {
10174     { "ffree",  { STi }, 0 },
10175     { Bad_Opcode },
10176     { "fst",    { STi }, 0 },
10177     { "fstp",   { STi }, 0 },
10178     { "fucom",  { STi }, 0 },
10179     { "fucomp", { STi }, 0 },
10180     { Bad_Opcode },
10181     { Bad_Opcode },
10182   },
10183   /* de */
10184   {
10185     { "faddp",  { STi, ST }, 0 },
10186     { "fmulp",  { STi, ST }, 0 },
10187     { Bad_Opcode },
10188     { FGRPde_3 },
10189     { "fsub{!M|r}p",    { STi, ST }, 0 },
10190     { "fsub{M|}p",      { STi, ST }, 0 },
10191     { "fdiv{!M|r}p",    { STi, ST }, 0 },
10192     { "fdiv{M|}p",      { STi, ST }, 0 },
10193   },
10194   /* df */
10195   {
10196     { "ffreep", { STi }, 0 },
10197     { Bad_Opcode },
10198     { Bad_Opcode },
10199     { Bad_Opcode },
10200     { FGRPdf_4 },
10201     { "fucomip", { ST, STi }, 0 },
10202     { "fcomip", { ST, STi }, 0 },
10203     { Bad_Opcode },
10204   },
10205 };
10206
10207 static const char *const fgrps[][8] = {
10208   /* Bad opcode 0 */
10209   {
10210     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10211   },
10212
10213   /* d9_2  1 */
10214   {
10215     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10216   },
10217
10218   /* d9_4  2 */
10219   {
10220     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
10221   },
10222
10223   /* d9_5  3 */
10224   {
10225     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
10226   },
10227
10228   /* d9_6  4 */
10229   {
10230     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
10231   },
10232
10233   /* d9_7  5 */
10234   {
10235     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
10236   },
10237
10238   /* da_5  6 */
10239   {
10240     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10241   },
10242
10243   /* db_4  7 */
10244   {
10245     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
10246     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
10247   },
10248
10249   /* de_3  8 */
10250   {
10251     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10252   },
10253
10254   /* df_4  9 */
10255   {
10256     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10257   },
10258 };
10259
10260 static void
10261 swap_operand (instr_info *ins)
10262 {
10263   ins->mnemonicendp[0] = '.';
10264   ins->mnemonicendp[1] = 's';
10265   ins->mnemonicendp[2] = '\0';
10266   ins->mnemonicendp += 2;
10267 }
10268
10269 static void
10270 OP_Skip_MODRM (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
10271                int sizeflag ATTRIBUTE_UNUSED)
10272 {
10273   /* Skip mod/rm byte.  */
10274   MODRM_CHECK;
10275   ins->codep++;
10276 }
10277
10278 static void
10279 dofloat (instr_info *ins, int sizeflag)
10280 {
10281   const struct dis386 *dp;
10282   unsigned char floatop;
10283
10284   floatop = ins->codep[-1];
10285
10286   if (ins->modrm.mod != 3)
10287     {
10288       int fp_indx = (floatop - 0xd8) * 8 + ins->modrm.reg;
10289
10290       putop (ins, float_mem[fp_indx], sizeflag);
10291       ins->obufp = ins->op_out[0];
10292       ins->op_ad = 2;
10293       OP_E (ins, float_mem_mode[fp_indx], sizeflag);
10294       return;
10295     }
10296   /* Skip mod/rm byte.  */
10297   MODRM_CHECK;
10298   ins->codep++;
10299
10300   dp = &float_reg[floatop - 0xd8][ins->modrm.reg];
10301   if (dp->name == NULL)
10302     {
10303       putop (ins, fgrps[dp->op[0].bytemode][ins->modrm.rm], sizeflag);
10304
10305       /* Instruction fnstsw is only one with strange arg.  */
10306       if (floatop == 0xdf && ins->codep[-1] == 0xe0)
10307         strcpy (ins->op_out[0], att_names16[0] + ins->intel_syntax);
10308     }
10309   else
10310     {
10311       putop (ins, dp->name, sizeflag);
10312
10313       ins->obufp = ins->op_out[0];
10314       ins->op_ad = 2;
10315       if (dp->op[0].rtn)
10316         (*dp->op[0].rtn) (ins, dp->op[0].bytemode, sizeflag);
10317
10318       ins->obufp = ins->op_out[1];
10319       ins->op_ad = 1;
10320       if (dp->op[1].rtn)
10321         (*dp->op[1].rtn) (ins, dp->op[1].bytemode, sizeflag);
10322     }
10323 }
10324
10325 static void
10326 OP_ST (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
10327        int sizeflag ATTRIBUTE_UNUSED)
10328 {
10329   oappend_register (ins, "%st");
10330 }
10331
10332 static void
10333 OP_STi (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
10334         int sizeflag ATTRIBUTE_UNUSED)
10335 {
10336   sprintf (ins->scratchbuf, "%%st(%d)", ins->modrm.rm);
10337   oappend_register (ins, ins->scratchbuf);
10338 }
10339
10340 /* Capital letters in template are macros.  */
10341 static int
10342 putop (instr_info *ins, const char *in_template, int sizeflag)
10343 {
10344   const char *p;
10345   int alt = 0;
10346   int cond = 1;
10347   unsigned int l = 0, len = 0;
10348   char last[4];
10349
10350   for (p = in_template; *p; p++)
10351     {
10352       if (len > l)
10353         {
10354           if (l >= sizeof (last) || !ISUPPER (*p))
10355             abort ();
10356           last[l++] = *p;
10357           continue;
10358         }
10359       switch (*p)
10360         {
10361         default:
10362           *ins->obufp++ = *p;
10363           break;
10364         case '%':
10365           len++;
10366           break;
10367         case '!':
10368           cond = 0;
10369           break;
10370         case '{':
10371           if (ins->intel_syntax)
10372             {
10373               while (*++p != '|')
10374                 if (*p == '}' || *p == '\0')
10375                   abort ();
10376               alt = 1;
10377             }
10378           break;
10379         case '|':
10380           while (*++p != '}')
10381             {
10382               if (*p == '\0')
10383                 abort ();
10384             }
10385           break;
10386         case '}':
10387           alt = 0;
10388           break;
10389         case 'A':
10390           if (ins->intel_syntax)
10391             break;
10392           if ((ins->need_modrm && ins->modrm.mod != 3)
10393               || (sizeflag & SUFFIX_ALWAYS))
10394             *ins->obufp++ = 'b';
10395           break;
10396         case 'B':
10397           if (l == 0)
10398             {
10399             case_B:
10400               if (ins->intel_syntax)
10401                 break;
10402               if (sizeflag & SUFFIX_ALWAYS)
10403                 *ins->obufp++ = 'b';
10404             }
10405           else if (l == 1 && last[0] == 'L')
10406             {
10407               if (ins->address_mode == mode_64bit
10408                   && !(ins->prefixes & PREFIX_ADDR))
10409                 {
10410                   *ins->obufp++ = 'a';
10411                   *ins->obufp++ = 'b';
10412                   *ins->obufp++ = 's';
10413                 }
10414
10415               goto case_B;
10416             }
10417           else
10418             abort ();
10419           break;
10420         case 'C':
10421           if (ins->intel_syntax && !alt)
10422             break;
10423           if ((ins->prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10424             {
10425               if (sizeflag & DFLAG)
10426                 *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10427               else
10428                 *ins->obufp++ = ins->intel_syntax ? 'w' : 's';
10429               ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10430             }
10431           break;
10432         case 'D':
10433           if (l == 1)
10434             {
10435               switch (last[0])
10436               {
10437               case 'X':
10438                 if (!ins->vex.evex || ins->vex.w)
10439                   *ins->obufp++ = 'd';
10440                 else
10441                   oappend (ins, "{bad}");
10442                 break;
10443               default:
10444                 abort ();
10445               }
10446               break;
10447             }
10448           if (l)
10449             abort ();
10450           if (ins->intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
10451             break;
10452           USED_REX (REX_W);
10453           if (ins->modrm.mod == 3)
10454             {
10455               if (ins->rex & REX_W)
10456                 *ins->obufp++ = 'q';
10457               else
10458                 {
10459                   if (sizeflag & DFLAG)
10460                     *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10461                   else
10462                     *ins->obufp++ = 'w';
10463                   ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10464                 }
10465             }
10466           else
10467             *ins->obufp++ = 'w';
10468           break;
10469         case 'E':               /* For jcxz/jecxz */
10470           if (ins->address_mode == mode_64bit)
10471             {
10472               if (sizeflag & AFLAG)
10473                 *ins->obufp++ = 'r';
10474               else
10475                 *ins->obufp++ = 'e';
10476             }
10477           else
10478             if (sizeflag & AFLAG)
10479               *ins->obufp++ = 'e';
10480           ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR);
10481           break;
10482         case 'F':
10483           if (ins->intel_syntax)
10484             break;
10485           if ((ins->prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
10486             {
10487               if (sizeflag & AFLAG)
10488                 *ins->obufp++ = ins->address_mode == mode_64bit ? 'q' : 'l';
10489               else
10490                 *ins->obufp++ = ins->address_mode == mode_64bit ? 'l' : 'w';
10491               ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR);
10492             }
10493           break;
10494         case 'G':
10495           if (ins->intel_syntax || (ins->obufp[-1] != 's'
10496                                     && !(sizeflag & SUFFIX_ALWAYS)))
10497             break;
10498           if ((ins->rex & REX_W) || (sizeflag & DFLAG))
10499             *ins->obufp++ = 'l';
10500           else
10501             *ins->obufp++ = 'w';
10502           if (!(ins->rex & REX_W))
10503             ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10504           break;
10505         case 'H':
10506           if (l == 0)
10507             {
10508               if (ins->intel_syntax)
10509                 break;
10510               if ((ins->prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
10511                   || (ins->prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
10512                 {
10513                   ins->used_prefixes |= ins->prefixes & (PREFIX_CS | PREFIX_DS);
10514                   *ins->obufp++ = ',';
10515                   *ins->obufp++ = 'p';
10516
10517                   /* Set active_seg_prefix even if not set in 64-bit mode
10518                      because here it is a valid branch hint. */
10519                   if (ins->prefixes & PREFIX_DS)
10520                     {
10521                       ins->active_seg_prefix = PREFIX_DS;
10522                       *ins->obufp++ = 't';
10523                     }
10524                   else
10525                     {
10526                       ins->active_seg_prefix = PREFIX_CS;
10527                       *ins->obufp++ = 'n';
10528                     }
10529                 }
10530             }
10531           else if (l == 1 && last[0] == 'X')
10532             {
10533               if (!ins->vex.w)
10534                 *ins->obufp++ = 'h';
10535               else
10536                 oappend (ins, "{bad}");
10537             }
10538           else
10539             abort ();
10540           break;
10541         case 'K':
10542           USED_REX (REX_W);
10543           if (ins->rex & REX_W)
10544             *ins->obufp++ = 'q';
10545           else
10546             *ins->obufp++ = 'd';
10547           break;
10548         case 'L':
10549           abort ();
10550         case 'M':
10551           if (ins->intel_mnemonic != cond)
10552             *ins->obufp++ = 'r';
10553           break;
10554         case 'N':
10555           if ((ins->prefixes & PREFIX_FWAIT) == 0)
10556             *ins->obufp++ = 'n';
10557           else
10558             ins->used_prefixes |= PREFIX_FWAIT;
10559           break;
10560         case 'O':
10561           USED_REX (REX_W);
10562           if (ins->rex & REX_W)
10563             *ins->obufp++ = 'o';
10564           else if (ins->intel_syntax && (sizeflag & DFLAG))
10565             *ins->obufp++ = 'q';
10566           else
10567             *ins->obufp++ = 'd';
10568           if (!(ins->rex & REX_W))
10569             ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10570           break;
10571         case '@':
10572           if (ins->address_mode == mode_64bit
10573               && (ins->isa64 == intel64 || (ins->rex & REX_W)
10574                   || !(ins->prefixes & PREFIX_DATA)))
10575             {
10576               if (sizeflag & SUFFIX_ALWAYS)
10577                 *ins->obufp++ = 'q';
10578               break;
10579             }
10580           /* Fall through.  */
10581         case 'P':
10582           if (l == 0)
10583             {
10584               if ((ins->modrm.mod == 3 || !cond)
10585                   && !(sizeflag & SUFFIX_ALWAYS))
10586                 break;
10587           /* Fall through.  */
10588         case 'T':
10589               if ((!(ins->rex & REX_W) && (ins->prefixes & PREFIX_DATA))
10590                   || ((sizeflag & SUFFIX_ALWAYS)
10591                       && ins->address_mode != mode_64bit))
10592                 {
10593                   *ins->obufp++ = (sizeflag & DFLAG)
10594                                   ? ins->intel_syntax ? 'd' : 'l' : 'w';
10595                   ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10596                 }
10597               else if (sizeflag & SUFFIX_ALWAYS)
10598                 *ins->obufp++ = 'q';
10599             }
10600           else if (l == 1 && last[0] == 'L')
10601             {
10602               if ((ins->prefixes & PREFIX_DATA)
10603                   || (ins->rex & REX_W)
10604                   || (sizeflag & SUFFIX_ALWAYS))
10605                 {
10606                   USED_REX (REX_W);
10607                   if (ins->rex & REX_W)
10608                     *ins->obufp++ = 'q';
10609                   else
10610                     {
10611                       if (sizeflag & DFLAG)
10612                         *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10613                       else
10614                         *ins->obufp++ = 'w';
10615                       ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10616                     }
10617                 }
10618             }
10619           else
10620             abort ();
10621           break;
10622         case 'Q':
10623           if (l == 0)
10624             {
10625               if (ins->intel_syntax && !alt)
10626                 break;
10627               USED_REX (REX_W);
10628               if ((ins->need_modrm && ins->modrm.mod != 3)
10629                   || (sizeflag & SUFFIX_ALWAYS))
10630                 {
10631                   if (ins->rex & REX_W)
10632                     *ins->obufp++ = 'q';
10633                   else
10634                     {
10635                       if (sizeflag & DFLAG)
10636                         *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10637                       else
10638                         *ins->obufp++ = 'w';
10639                       ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10640                     }
10641                 }
10642             }
10643           else if (l == 1 && last[0] == 'D')
10644             *ins->obufp++ = ins->vex.w ? 'q' : 'd';
10645           else if (l == 1 && last[0] == 'L')
10646             {
10647               if (cond ? ins->modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)
10648                        : ins->address_mode != mode_64bit)
10649                 break;
10650               if ((ins->rex & REX_W))
10651                 {
10652                   USED_REX (REX_W);
10653                   *ins->obufp++ = 'q';
10654                 }
10655               else if ((ins->address_mode == mode_64bit && cond)
10656                       || (sizeflag & SUFFIX_ALWAYS))
10657                 *ins->obufp++ = ins->intel_syntax? 'd' : 'l';
10658             }
10659           else
10660             abort ();
10661           break;
10662         case 'R':
10663           USED_REX (REX_W);
10664           if (ins->rex & REX_W)
10665             *ins->obufp++ = 'q';
10666           else if (sizeflag & DFLAG)
10667             {
10668               if (ins->intel_syntax)
10669                   *ins->obufp++ = 'd';
10670               else
10671                   *ins->obufp++ = 'l';
10672             }
10673           else
10674             *ins->obufp++ = 'w';
10675           if (ins->intel_syntax && !p[1]
10676               && ((ins->rex & REX_W) || (sizeflag & DFLAG)))
10677             *ins->obufp++ = 'e';
10678           if (!(ins->rex & REX_W))
10679             ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10680           break;
10681         case 'S':
10682           if (l == 0)
10683             {
10684             case_S:
10685               if (ins->intel_syntax)
10686                 break;
10687               if (sizeflag & SUFFIX_ALWAYS)
10688                 {
10689                   if (ins->rex & REX_W)
10690                     *ins->obufp++ = 'q';
10691                   else
10692                     {
10693                       if (sizeflag & DFLAG)
10694                         *ins->obufp++ = 'l';
10695                       else
10696                         *ins->obufp++ = 'w';
10697                       ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10698                     }
10699                 }
10700               break;
10701             }
10702           if (l != 1)
10703             abort ();
10704           switch (last[0])
10705             {
10706             case 'L':
10707               if (ins->address_mode == mode_64bit
10708                   && !(ins->prefixes & PREFIX_ADDR))
10709                 {
10710                   *ins->obufp++ = 'a';
10711                   *ins->obufp++ = 'b';
10712                   *ins->obufp++ = 's';
10713                 }
10714
10715               goto case_S;
10716             case 'X':
10717               if (!ins->vex.evex || !ins->vex.w)
10718                 *ins->obufp++ = 's';
10719               else
10720                 oappend (ins, "{bad}");
10721               break;
10722             default:
10723               abort ();
10724             }
10725           break;
10726         case 'V':
10727           if (l == 0)
10728             abort ();
10729           else if (l == 1
10730                    && (last[0] == 'L' || last[0] == 'X'))
10731             {
10732               if (last[0] == 'X')
10733                 {
10734                   *ins->obufp++ = '{';
10735                   *ins->obufp++ = 'v';
10736                   *ins->obufp++ = 'e';
10737                   *ins->obufp++ = 'x';
10738                   *ins->obufp++ = '}';
10739                 }
10740               else if (ins->rex & REX_W)
10741                 {
10742                   *ins->obufp++ = 'a';
10743                   *ins->obufp++ = 'b';
10744                   *ins->obufp++ = 's';
10745                 }
10746             }
10747           else
10748             abort ();
10749           goto case_S;
10750         case 'W':
10751           if (l == 0)
10752             {
10753               /* operand size flag for cwtl, cbtw */
10754               USED_REX (REX_W);
10755               if (ins->rex & REX_W)
10756                 {
10757                   if (ins->intel_syntax)
10758                     *ins->obufp++ = 'd';
10759                   else
10760                     *ins->obufp++ = 'l';
10761                 }
10762               else if (sizeflag & DFLAG)
10763                 *ins->obufp++ = 'w';
10764               else
10765                 *ins->obufp++ = 'b';
10766               if (!(ins->rex & REX_W))
10767                 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10768             }
10769           else if (l == 1)
10770             {
10771               if (!ins->need_vex)
10772                 abort ();
10773               if (last[0] == 'X')
10774                 *ins->obufp++ = ins->vex.w ? 'd': 's';
10775               else if (last[0] == 'B')
10776                 *ins->obufp++ = ins->vex.w ? 'w': 'b';
10777               else
10778                 abort ();
10779             }
10780           else
10781             abort ();
10782           break;
10783         case 'X':
10784           if (l != 0)
10785             abort ();
10786           if (ins->need_vex
10787               ? ins->vex.prefix == DATA_PREFIX_OPCODE
10788               : ins->prefixes & PREFIX_DATA)
10789             {
10790               *ins->obufp++ = 'd';
10791               ins->used_prefixes |= PREFIX_DATA;
10792             }
10793           else
10794             *ins->obufp++ = 's';
10795           break;
10796         case 'Y':
10797           if (l == 1 && last[0] == 'X')
10798             {
10799               if (!ins->need_vex)
10800                 abort ();
10801               if (ins->intel_syntax
10802                   || ((ins->modrm.mod == 3 || ins->vex.b)
10803                       && !(sizeflag & SUFFIX_ALWAYS)))
10804                 break;
10805               switch (ins->vex.length)
10806                 {
10807                 case 128:
10808                   *ins->obufp++ = 'x';
10809                   break;
10810                 case 256:
10811                   *ins->obufp++ = 'y';
10812                   break;
10813                 case 512:
10814                   if (!ins->vex.evex)
10815                 default:
10816                     abort ();
10817                 }
10818             }
10819           else
10820             abort ();
10821           break;
10822         case 'Z':
10823           if (l == 0)
10824             {
10825               /* These insns ignore ModR/M.mod: Force it to 3 for OP_E().  */
10826               ins->modrm.mod = 3;
10827               if (!ins->intel_syntax && (sizeflag & SUFFIX_ALWAYS))
10828                 *ins->obufp++ = ins->address_mode == mode_64bit ? 'q' : 'l';
10829             }
10830           else if (l == 1 && last[0] == 'X')
10831             {
10832               if (!ins->vex.evex)
10833                 abort ();
10834               if (ins->intel_syntax
10835                   || ((ins->modrm.mod == 3 || ins->vex.b)
10836                       && !(sizeflag & SUFFIX_ALWAYS)))
10837                 break;
10838               switch (ins->vex.length)
10839                 {
10840                 case 128:
10841                   *ins->obufp++ = 'x';
10842                   break;
10843                 case 256:
10844                   *ins->obufp++ = 'y';
10845                   break;
10846                 case 512:
10847                   *ins->obufp++ = 'z';
10848                   break;
10849                 default:
10850                   abort ();
10851                 }
10852             }
10853           else
10854             abort ();
10855           break;
10856         case '^':
10857           if (ins->intel_syntax)
10858             break;
10859           if (ins->isa64 == intel64 && (ins->rex & REX_W))
10860             {
10861               USED_REX (REX_W);
10862               *ins->obufp++ = 'q';
10863               break;
10864             }
10865           if ((ins->prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10866             {
10867               if (sizeflag & DFLAG)
10868                 *ins->obufp++ = 'l';
10869               else
10870                 *ins->obufp++ = 'w';
10871               ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10872             }
10873           break;
10874         }
10875
10876       if (len == l)
10877         len = l = 0;
10878     }
10879   *ins->obufp = 0;
10880   ins->mnemonicendp = ins->obufp;
10881   return 0;
10882 }
10883
10884 /* Add a style marker to *INS->obufp that encodes STYLE.  This assumes that
10885    the buffer pointed to by INS->obufp has space.  A style marker is made
10886    from the STYLE_MARKER_CHAR followed by STYLE converted to a single hex
10887    digit, followed by another STYLE_MARKER_CHAR.  This function assumes
10888    that the number of styles is not greater than 16.  */
10889
10890 static void
10891 oappend_insert_style (instr_info *ins, enum disassembler_style style)
10892 {
10893   unsigned num = (unsigned) style;
10894
10895   /* We currently assume that STYLE can be encoded as a single hex
10896      character.  If more styles are added then this might start to fail,
10897      and we'll need to expand this code.  */
10898   if (num > 0xf)
10899     abort ();
10900
10901   *ins->obufp++ = STYLE_MARKER_CHAR;
10902   *ins->obufp++ = (num < 10 ? ('0' + num)
10903                    : ((num < 16) ? ('a' + (num - 10)) : '0'));
10904   *ins->obufp++ = STYLE_MARKER_CHAR;
10905
10906   /* This final null character is not strictly necessary, after inserting a
10907      style marker we should always be inserting some additional content.
10908      However, having the buffer null terminated doesn't cost much, and make
10909      it easier to debug what's going on.  Also, if we do ever forget to add
10910      any additional content after this style marker, then the buffer will
10911      still be well formed.  */
10912   *ins->obufp = '\0';
10913 }
10914
10915 static void
10916 oappend_with_style (instr_info *ins, const char *s,
10917                     enum disassembler_style style)
10918 {
10919   oappend_insert_style (ins, style);
10920   ins->obufp = stpcpy (ins->obufp, s);
10921 }
10922
10923 /* Like oappend_with_style but always with text style.  */
10924
10925 static void
10926 oappend (instr_info *ins, const char *s)
10927 {
10928   oappend_with_style (ins, s, dis_style_text);
10929 }
10930
10931 /* Add a single character C to the buffer pointer to by INS->obufp, marking
10932    the style for the character as STYLE.  */
10933
10934 static void
10935 oappend_char_with_style (instr_info *ins, const char c,
10936                          enum disassembler_style style)
10937 {
10938   oappend_insert_style (ins, style);
10939   *ins->obufp++ = c;
10940   *ins->obufp = '\0';
10941 }
10942
10943 /* Like oappend_char_with_style, but always uses dis_style_text.  */
10944
10945 static void
10946 oappend_char (instr_info *ins, const char c)
10947 {
10948   oappend_char_with_style (ins, c, dis_style_text);
10949 }
10950
10951 static void
10952 append_seg (instr_info *ins)
10953 {
10954   /* Only print the active segment register.  */
10955   if (!ins->active_seg_prefix)
10956     return;
10957
10958   ins->used_prefixes |= ins->active_seg_prefix;
10959   switch (ins->active_seg_prefix)
10960     {
10961     case PREFIX_CS:
10962       oappend_register (ins, "%cs");
10963       break;
10964     case PREFIX_DS:
10965       oappend_register (ins, "%ds");
10966       break;
10967     case PREFIX_SS:
10968       oappend_register (ins, "%ss");
10969       break;
10970     case PREFIX_ES:
10971       oappend_register (ins, "%es");
10972       break;
10973     case PREFIX_FS:
10974       oappend_register (ins, "%fs");
10975       break;
10976     case PREFIX_GS:
10977       oappend_register (ins, "%gs");
10978       break;
10979     default:
10980       break;
10981     }
10982   oappend_char (ins, ':');
10983 }
10984
10985 static void
10986 OP_indirE (instr_info *ins, int bytemode, int sizeflag)
10987 {
10988   if (!ins->intel_syntax)
10989     oappend (ins, "*");
10990   OP_E (ins, bytemode, sizeflag);
10991 }
10992
10993 static void
10994 print_operand_value (instr_info *ins, char *buf, int hex, bfd_vma disp)
10995 {
10996   if (ins->address_mode == mode_64bit)
10997     {
10998       if (hex)
10999         {
11000           char tmp[30];
11001           int i;
11002           buf[0] = '0';
11003           buf[1] = 'x';
11004           sprintf_vma (tmp, disp);
11005           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
11006           strcpy (buf + 2, tmp + i);
11007         }
11008       else
11009         {
11010           bfd_signed_vma v = disp;
11011           char tmp[30];
11012           int i;
11013           if (v < 0)
11014             {
11015               *(buf++) = '-';
11016               v = -disp;
11017               /* Check for possible overflow on 0x8000000000000000.  */
11018               if (v < 0)
11019                 {
11020                   strcpy (buf, "9223372036854775808");
11021                   return;
11022                 }
11023             }
11024           if (!v)
11025             {
11026               strcpy (buf, "0");
11027               return;
11028             }
11029
11030           i = 0;
11031           tmp[29] = 0;
11032           while (v)
11033             {
11034               tmp[28 - i] = (v % 10) + '0';
11035               v /= 10;
11036               i++;
11037             }
11038           strcpy (buf, tmp + 29 - i);
11039         }
11040     }
11041   else
11042     {
11043       if (hex)
11044         sprintf (buf, "0x%x", (unsigned int) disp);
11045       else
11046         sprintf (buf, "%d", (int) disp);
11047     }
11048 }
11049
11050 /* Put DISP in BUF as signed hex number.  */
11051
11052 static void
11053 print_displacement (instr_info *ins, char *buf, bfd_vma disp)
11054 {
11055   bfd_signed_vma val = disp;
11056   char tmp[30];
11057   int i, j = 0;
11058
11059   if (val < 0)
11060     {
11061       buf[j++] = '-';
11062       val = -disp;
11063
11064       /* Check for possible overflow.  */
11065       if (val < 0)
11066         {
11067           switch (ins->address_mode)
11068             {
11069             case mode_64bit:
11070               strcpy (buf + j, "0x8000000000000000");
11071               break;
11072             case mode_32bit:
11073               strcpy (buf + j, "0x80000000");
11074               break;
11075             case mode_16bit:
11076               strcpy (buf + j, "0x8000");
11077               break;
11078             }
11079           return;
11080         }
11081     }
11082
11083   buf[j++] = '0';
11084   buf[j++] = 'x';
11085
11086   sprintf_vma (tmp, (bfd_vma) val);
11087   for (i = 0; tmp[i] == '0'; i++)
11088     continue;
11089   if (tmp[i] == '\0')
11090     i--;
11091   strcpy (buf + j, tmp + i);
11092 }
11093
11094 static void
11095 intel_operand_size (instr_info *ins, int bytemode, int sizeflag)
11096 {
11097   if (ins->vex.b)
11098     {
11099       if (!ins->vex.no_broadcast)
11100         switch (bytemode)
11101           {
11102           case x_mode:
11103           case evex_half_bcst_xmmq_mode:
11104             if (ins->vex.w)
11105               oappend (ins, "QWORD BCST ");
11106             else
11107               oappend (ins, "DWORD BCST ");
11108             break;
11109           case xh_mode:
11110           case evex_half_bcst_xmmqh_mode:
11111           case evex_half_bcst_xmmqdh_mode:
11112             oappend (ins, "WORD BCST ");
11113             break;
11114           default:
11115             ins->vex.no_broadcast = true;
11116             break;
11117           }
11118       return;
11119     }
11120   switch (bytemode)
11121     {
11122     case b_mode:
11123     case b_swap_mode:
11124     case db_mode:
11125       oappend (ins, "BYTE PTR ");
11126       break;
11127     case w_mode:
11128     case w_swap_mode:
11129     case dw_mode:
11130       oappend (ins, "WORD PTR ");
11131       break;
11132     case indir_v_mode:
11133       if (ins->address_mode == mode_64bit && ins->isa64 == intel64)
11134         {
11135           oappend (ins, "QWORD PTR ");
11136           break;
11137         }
11138       /* Fall through.  */
11139     case stack_v_mode:
11140       if (ins->address_mode == mode_64bit && ((sizeflag & DFLAG)
11141                                               || (ins->rex & REX_W)))
11142         {
11143           oappend (ins, "QWORD PTR ");
11144           break;
11145         }
11146       /* Fall through.  */
11147     case v_mode:
11148     case v_swap_mode:
11149     case dq_mode:
11150       USED_REX (REX_W);
11151       if (ins->rex & REX_W)
11152         oappend (ins, "QWORD PTR ");
11153       else if (bytemode == dq_mode)
11154         oappend (ins, "DWORD PTR ");
11155       else
11156         {
11157           if (sizeflag & DFLAG)
11158             oappend (ins, "DWORD PTR ");
11159           else
11160             oappend (ins, "WORD PTR ");
11161           ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11162         }
11163       break;
11164     case z_mode:
11165       if ((ins->rex & REX_W) || (sizeflag & DFLAG))
11166         *ins->obufp++ = 'D';
11167       oappend (ins, "WORD PTR ");
11168       if (!(ins->rex & REX_W))
11169         ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11170       break;
11171     case a_mode:
11172       if (sizeflag & DFLAG)
11173         oappend (ins, "QWORD PTR ");
11174       else
11175         oappend (ins, "DWORD PTR ");
11176       ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11177       break;
11178     case movsxd_mode:
11179       if (!(sizeflag & DFLAG) && ins->isa64 == intel64)
11180         oappend (ins, "WORD PTR ");
11181       else
11182         oappend (ins, "DWORD PTR ");
11183       ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11184       break;
11185     case d_mode:
11186     case d_swap_mode:
11187       oappend (ins, "DWORD PTR ");
11188       break;
11189     case q_mode:
11190     case q_swap_mode:
11191       oappend (ins, "QWORD PTR ");
11192       break;
11193     case m_mode:
11194       if (ins->address_mode == mode_64bit)
11195         oappend (ins, "QWORD PTR ");
11196       else
11197         oappend (ins, "DWORD PTR ");
11198       break;
11199     case f_mode:
11200       if (sizeflag & DFLAG)
11201         oappend (ins, "FWORD PTR ");
11202       else
11203         oappend (ins, "DWORD PTR ");
11204       ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11205       break;
11206     case t_mode:
11207       oappend (ins, "TBYTE PTR ");
11208       break;
11209     case x_mode:
11210     case xh_mode:
11211     case x_swap_mode:
11212     case evex_x_gscat_mode:
11213     case evex_x_nobcst_mode:
11214     case bw_unit_mode:
11215       if (ins->need_vex)
11216         {
11217           switch (ins->vex.length)
11218             {
11219             case 128:
11220               oappend (ins, "XMMWORD PTR ");
11221               break;
11222             case 256:
11223               oappend (ins, "YMMWORD PTR ");
11224               break;
11225             case 512:
11226               oappend (ins, "ZMMWORD PTR ");
11227               break;
11228             default:
11229               abort ();
11230             }
11231         }
11232       else
11233         oappend (ins, "XMMWORD PTR ");
11234       break;
11235     case xmm_mode:
11236       oappend (ins, "XMMWORD PTR ");
11237       break;
11238     case ymm_mode:
11239       oappend (ins, "YMMWORD PTR ");
11240       break;
11241     case xmmq_mode:
11242     case evex_half_bcst_xmmqh_mode:
11243     case evex_half_bcst_xmmq_mode:
11244       if (!ins->need_vex)
11245         abort ();
11246
11247       switch (ins->vex.length)
11248         {
11249         case 128:
11250           oappend (ins, "QWORD PTR ");
11251           break;
11252         case 256:
11253           oappend (ins, "XMMWORD PTR ");
11254           break;
11255         case 512:
11256           oappend (ins, "YMMWORD PTR ");
11257           break;
11258         default:
11259           abort ();
11260         }
11261       break;
11262     case xmmdw_mode:
11263       if (!ins->need_vex)
11264         abort ();
11265
11266       switch (ins->vex.length)
11267         {
11268         case 128:
11269           oappend (ins, "WORD PTR ");
11270           break;
11271         case 256:
11272           oappend (ins, "DWORD PTR ");
11273           break;
11274         case 512:
11275           oappend (ins, "QWORD PTR ");
11276           break;
11277         default:
11278           abort ();
11279         }
11280       break;
11281     case xmmqd_mode:
11282     case evex_half_bcst_xmmqdh_mode:
11283       if (!ins->need_vex)
11284         abort ();
11285
11286       switch (ins->vex.length)
11287         {
11288         case 128:
11289           oappend (ins, "DWORD PTR ");
11290           break;
11291         case 256:
11292           oappend (ins, "QWORD PTR ");
11293           break;
11294         case 512:
11295           oappend (ins, "XMMWORD PTR ");
11296           break;
11297         default:
11298           abort ();
11299         }
11300       break;
11301     case ymmq_mode:
11302       if (!ins->need_vex)
11303         abort ();
11304
11305       switch (ins->vex.length)
11306         {
11307         case 128:
11308           oappend (ins, "QWORD PTR ");
11309           break;
11310         case 256:
11311           oappend (ins, "YMMWORD PTR ");
11312           break;
11313         case 512:
11314           oappend (ins, "ZMMWORD PTR ");
11315           break;
11316         default:
11317           abort ();
11318         }
11319       break;
11320     case o_mode:
11321       oappend (ins, "OWORD PTR ");
11322       break;
11323     case vex_vsib_d_w_dq_mode:
11324     case vex_vsib_q_w_dq_mode:
11325       if (!ins->need_vex)
11326         abort ();
11327       if (ins->vex.w)
11328         oappend (ins, "QWORD PTR ");
11329       else
11330         oappend (ins, "DWORD PTR ");
11331       break;
11332     case mask_bd_mode:
11333       if (!ins->need_vex || ins->vex.length != 128)
11334         abort ();
11335       if (ins->vex.w)
11336         oappend (ins, "DWORD PTR ");
11337       else
11338         oappend (ins, "BYTE PTR ");
11339       break;
11340     case mask_mode:
11341       if (!ins->need_vex)
11342         abort ();
11343       if (ins->vex.w)
11344         oappend (ins, "QWORD PTR ");
11345       else
11346         oappend (ins, "WORD PTR ");
11347       break;
11348     case v_bnd_mode:
11349     case v_bndmk_mode:
11350     default:
11351       break;
11352     }
11353 }
11354
11355 static void
11356 print_register (instr_info *ins, unsigned int reg, unsigned int rexmask,
11357                 int bytemode, int sizeflag)
11358 {
11359   const char *const *names;
11360
11361   USED_REX (rexmask);
11362   if (ins->rex & rexmask)
11363     reg += 8;
11364
11365   switch (bytemode)
11366     {
11367     case b_mode:
11368     case b_swap_mode:
11369       if (reg & 4)
11370         USED_REX (0);
11371       if (ins->rex)
11372         names = att_names8rex;
11373       else
11374         names = att_names8;
11375       break;
11376     case w_mode:
11377       names = att_names16;
11378       break;
11379     case d_mode:
11380     case dw_mode:
11381     case db_mode:
11382       names = att_names32;
11383       break;
11384     case q_mode:
11385       names = att_names64;
11386       break;
11387     case m_mode:
11388     case v_bnd_mode:
11389       names = ins->address_mode == mode_64bit ? att_names64 : att_names32;
11390       break;
11391     case bnd_mode:
11392     case bnd_swap_mode:
11393       if (reg > 0x3)
11394         {
11395           oappend (ins, "(bad)");
11396           return;
11397         }
11398       names = att_names_bnd;
11399       break;
11400     case indir_v_mode:
11401       if (ins->address_mode == mode_64bit && ins->isa64 == intel64)
11402         {
11403           names = att_names64;
11404           break;
11405         }
11406       /* Fall through.  */
11407     case stack_v_mode:
11408       if (ins->address_mode == mode_64bit && ((sizeflag & DFLAG)
11409                                               || (ins->rex & REX_W)))
11410         {
11411           names = att_names64;
11412           break;
11413         }
11414       bytemode = v_mode;
11415       /* Fall through.  */
11416     case v_mode:
11417     case v_swap_mode:
11418     case dq_mode:
11419       USED_REX (REX_W);
11420       if (ins->rex & REX_W)
11421         names = att_names64;
11422       else if (bytemode != v_mode && bytemode != v_swap_mode)
11423         names = att_names32;
11424       else
11425         {
11426           if (sizeflag & DFLAG)
11427             names = att_names32;
11428           else
11429             names = att_names16;
11430           ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11431         }
11432       break;
11433     case movsxd_mode:
11434       if (!(sizeflag & DFLAG) && ins->isa64 == intel64)
11435         names = att_names16;
11436       else
11437         names = att_names32;
11438       ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11439       break;
11440     case va_mode:
11441       names = (ins->address_mode == mode_64bit
11442                ? att_names64 : att_names32);
11443       if (!(ins->prefixes & PREFIX_ADDR))
11444         names = (ins->address_mode == mode_16bit
11445                      ? att_names16 : names);
11446       else
11447         {
11448           /* Remove "addr16/addr32".  */
11449           ins->all_prefixes[ins->last_addr_prefix] = 0;
11450           names = (ins->address_mode != mode_32bit
11451                        ? att_names32 : att_names16);
11452           ins->used_prefixes |= PREFIX_ADDR;
11453         }
11454       break;
11455     case mask_bd_mode:
11456     case mask_mode:
11457       if (reg > 0x7)
11458         {
11459           oappend (ins, "(bad)");
11460           return;
11461         }
11462       names = att_names_mask;
11463       break;
11464     case 0:
11465       return;
11466     default:
11467       oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
11468       return;
11469     }
11470   oappend_register (ins, names[reg]);
11471 }
11472
11473 static void
11474 OP_E_memory (instr_info *ins, int bytemode, int sizeflag)
11475 {
11476   bfd_vma disp = 0;
11477   int add = (ins->rex & REX_B) ? 8 : 0;
11478   int riprel = 0;
11479   int shift;
11480
11481   if (ins->vex.evex)
11482     {
11483       switch (bytemode)
11484         {
11485         case dw_mode:
11486         case w_mode:
11487         case w_swap_mode:
11488           shift = 1;
11489           break;
11490         case db_mode:
11491         case b_mode:
11492           shift = 0;
11493           break;
11494         case dq_mode:
11495           if (ins->address_mode != mode_64bit)
11496             {
11497         case d_mode:
11498         case d_swap_mode:
11499               shift = 2;
11500               break;
11501             }
11502             /* fall through */
11503         case vex_vsib_d_w_dq_mode:
11504         case vex_vsib_q_w_dq_mode:
11505         case evex_x_gscat_mode:
11506           shift = ins->vex.w ? 3 : 2;
11507           break;
11508         case xh_mode:
11509         case evex_half_bcst_xmmqh_mode:
11510         case evex_half_bcst_xmmqdh_mode:
11511           if (ins->vex.b)
11512             {
11513               shift = ins->vex.w ? 2 : 1;
11514               break;
11515             }
11516           /* Fall through.  */
11517         case x_mode:
11518         case evex_half_bcst_xmmq_mode:
11519           if (ins->vex.b)
11520             {
11521               shift = ins->vex.w ? 3 : 2;
11522               break;
11523             }
11524           /* Fall through.  */
11525         case xmmqd_mode:
11526         case xmmdw_mode:
11527         case xmmq_mode:
11528         case ymmq_mode:
11529         case evex_x_nobcst_mode:
11530         case x_swap_mode:
11531           switch (ins->vex.length)
11532             {
11533             case 128:
11534               shift = 4;
11535               break;
11536             case 256:
11537               shift = 5;
11538               break;
11539             case 512:
11540               shift = 6;
11541               break;
11542             default:
11543               abort ();
11544             }
11545           /* Make necessary corrections to shift for modes that need it.  */
11546           if (bytemode == xmmq_mode
11547               || bytemode == evex_half_bcst_xmmqh_mode
11548               || bytemode == evex_half_bcst_xmmq_mode
11549               || (bytemode == ymmq_mode && ins->vex.length == 128))
11550             shift -= 1;
11551           else if (bytemode == xmmqd_mode
11552                    || bytemode == evex_half_bcst_xmmqdh_mode)
11553             shift -= 2;
11554           else if (bytemode == xmmdw_mode)
11555             shift -= 3;
11556           break;
11557         case ymm_mode:
11558           shift = 5;
11559           break;
11560         case xmm_mode:
11561           shift = 4;
11562           break;
11563         case q_mode:
11564         case q_swap_mode:
11565           shift = 3;
11566           break;
11567         case bw_unit_mode:
11568           shift = ins->vex.w ? 1 : 0;
11569           break;
11570         default:
11571           abort ();
11572         }
11573     }
11574   else
11575     shift = 0;
11576
11577   USED_REX (REX_B);
11578   if (ins->intel_syntax)
11579     intel_operand_size (ins, bytemode, sizeflag);
11580   append_seg (ins);
11581
11582   if ((sizeflag & AFLAG) || ins->address_mode == mode_64bit)
11583     {
11584       /* 32/64 bit address mode */
11585       int havedisp;
11586       int havebase;
11587       int needindex;
11588       int needaddr32;
11589       int base, rbase;
11590       int vindex = 0;
11591       int scale = 0;
11592       int addr32flag = !((sizeflag & AFLAG)
11593                          || bytemode == v_bnd_mode
11594                          || bytemode == v_bndmk_mode
11595                          || bytemode == bnd_mode
11596                          || bytemode == bnd_swap_mode);
11597       bool check_gather = false;
11598       const char *const *indexes = NULL;
11599
11600       havebase = 1;
11601       base = ins->modrm.rm;
11602
11603       if (base == 4)
11604         {
11605           vindex = ins->sib.index;
11606           USED_REX (REX_X);
11607           if (ins->rex & REX_X)
11608             vindex += 8;
11609           switch (bytemode)
11610             {
11611             case vex_vsib_d_w_dq_mode:
11612             case vex_vsib_q_w_dq_mode:
11613               if (!ins->need_vex)
11614                 abort ();
11615               if (ins->vex.evex)
11616                 {
11617                   if (!ins->vex.v)
11618                     vindex += 16;
11619                   check_gather = ins->obufp == ins->op_out[1];
11620                 }
11621
11622               switch (ins->vex.length)
11623                 {
11624                 case 128:
11625                   indexes = att_names_xmm;
11626                   break;
11627                 case 256:
11628                   if (!ins->vex.w
11629                       || bytemode == vex_vsib_q_w_dq_mode)
11630                     indexes = att_names_ymm;
11631                   else
11632                     indexes = att_names_xmm;
11633                   break;
11634                 case 512:
11635                   if (!ins->vex.w
11636                       || bytemode == vex_vsib_q_w_dq_mode)
11637                     indexes = att_names_zmm;
11638                   else
11639                     indexes = att_names_ymm;
11640                   break;
11641                 default:
11642                   abort ();
11643                 }
11644               break;
11645             default:
11646               if (vindex != 4)
11647                 indexes = ins->address_mode == mode_64bit && !addr32flag
11648                           ? att_names64 : att_names32;
11649               break;
11650             }
11651           scale = ins->sib.scale;
11652           base = ins->sib.base;
11653           ins->codep++;
11654         }
11655       else
11656         {
11657           /* Check for mandatory SIB.  */
11658           if (bytemode == vex_vsib_d_w_dq_mode
11659               || bytemode == vex_vsib_q_w_dq_mode
11660               || bytemode == vex_sibmem_mode)
11661             {
11662               oappend (ins, "(bad)");
11663               return;
11664             }
11665         }
11666       rbase = base + add;
11667
11668       switch (ins->modrm.mod)
11669         {
11670         case 0:
11671           if (base == 5)
11672             {
11673               havebase = 0;
11674               if (ins->address_mode == mode_64bit && !ins->has_sib)
11675                 riprel = 1;
11676               disp = get32s (ins);
11677               if (riprel && bytemode == v_bndmk_mode)
11678                 {
11679                   oappend (ins, "(bad)");
11680                   return;
11681                 }
11682             }
11683           break;
11684         case 1:
11685           FETCH_DATA (ins->info, ins->codep + 1);
11686           disp = *ins->codep++;
11687           if ((disp & 0x80) != 0)
11688             disp -= 0x100;
11689           if (ins->vex.evex && shift > 0)
11690             disp <<= shift;
11691           break;
11692         case 2:
11693           disp = get32s (ins);
11694           break;
11695         }
11696
11697       needindex = 0;
11698       needaddr32 = 0;
11699       if (ins->has_sib
11700           && !havebase
11701           && !indexes
11702           && ins->address_mode != mode_16bit)
11703         {
11704           if (ins->address_mode == mode_64bit)
11705             {
11706               if (addr32flag)
11707                 {
11708                   /* Without base nor index registers, zero-extend the
11709                      lower 32-bit displacement to 64 bits.  */
11710                   disp = (unsigned int) disp;
11711                   needindex = 1;
11712                 }
11713               needaddr32 = 1;
11714             }
11715           else
11716             {
11717               /* In 32-bit mode, we need index register to tell [offset]
11718                  from [eiz*1 + offset].  */
11719               needindex = 1;
11720             }
11721         }
11722
11723       havedisp = (havebase
11724                   || needindex
11725                   || (ins->has_sib && (indexes || scale != 0)));
11726
11727       if (!ins->intel_syntax)
11728         if (ins->modrm.mod != 0 || base == 5)
11729           {
11730             if (havedisp || riprel)
11731               print_displacement (ins, ins->scratchbuf, disp);
11732             else
11733               print_operand_value (ins, ins->scratchbuf, 1, disp);
11734             oappend_with_style (ins, ins->scratchbuf,
11735                                 dis_style_address_offset);
11736             if (riprel)
11737               {
11738                 set_op (ins, disp, true);
11739                 oappend_char (ins, '(');
11740                 oappend_with_style (ins, !addr32flag ? "%rip" : "%eip",
11741                                     dis_style_register);
11742                 oappend_char (ins, ')');
11743               }
11744           }
11745
11746       if ((havebase || indexes || needindex || needaddr32 || riprel)
11747           && (ins->address_mode != mode_64bit
11748               || ((bytemode != v_bnd_mode)
11749                   && (bytemode != v_bndmk_mode)
11750                   && (bytemode != bnd_mode)
11751                   && (bytemode != bnd_swap_mode))))
11752         ins->used_prefixes |= PREFIX_ADDR;
11753
11754       if (havedisp || (ins->intel_syntax && riprel))
11755         {
11756           oappend_char (ins, ins->open_char);
11757           if (ins->intel_syntax && riprel)
11758             {
11759               set_op (ins, disp, true);
11760               oappend_with_style (ins, !addr32flag ? "rip" : "eip",
11761                                   dis_style_register);
11762             }
11763           if (havebase)
11764             oappend_register
11765               (ins,
11766                (ins->address_mode == mode_64bit && !addr32flag
11767                 ? att_names64 : att_names32)[rbase]);
11768           if (ins->has_sib)
11769             {
11770               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
11771                  print index to tell base + index from base.  */
11772               if (scale != 0
11773                   || needindex
11774                   || indexes
11775                   || (havebase && base != ESP_REG_NUM))
11776                 {
11777                   if (!ins->intel_syntax || havebase)
11778                     oappend_char (ins, ins->separator_char);
11779                   if (indexes)
11780                     {
11781                       if (ins->address_mode == mode_64bit || vindex < 16)
11782                         oappend_register (ins, indexes[vindex]);
11783                       else
11784                         oappend (ins, "(bad)");
11785                     }
11786                   else
11787                     oappend_register (ins,
11788                                       ins->address_mode == mode_64bit
11789                                       && !addr32flag
11790                                       ? att_index64
11791                                       : att_index32);
11792
11793                   oappend_char (ins, ins->scale_char);
11794                   sprintf (ins->scratchbuf, "%d", 1 << scale);
11795                   oappend_with_style (ins, ins->scratchbuf,
11796                                       dis_style_immediate);
11797                 }
11798             }
11799           if (ins->intel_syntax
11800               && (disp || ins->modrm.mod != 0 || base == 5))
11801             {
11802               if (!havedisp || (bfd_signed_vma) disp >= 0)
11803                   oappend_char (ins, '+');
11804               else if (ins->modrm.mod != 1 && disp != -disp)
11805                 {
11806                   oappend_char (ins, '-');
11807                   disp = -disp;
11808                 }
11809
11810               if (havedisp)
11811                 print_displacement (ins, ins->scratchbuf, disp);
11812               else
11813                 print_operand_value (ins, ins->scratchbuf, 1, disp);
11814               oappend (ins, ins->scratchbuf);
11815             }
11816
11817           oappend_char (ins, ins->close_char);
11818
11819           if (check_gather)
11820             {
11821               /* Both XMM/YMM/ZMM registers must be distinct.  */
11822               int modrm_reg = ins->modrm.reg;
11823
11824               if (ins->rex & REX_R)
11825                 modrm_reg += 8;
11826               if (!ins->vex.r)
11827                 modrm_reg += 16;
11828               if (vindex == modrm_reg)
11829                 oappend (ins, "/(bad)");
11830             }
11831         }
11832       else if (ins->intel_syntax)
11833         {
11834           if (ins->modrm.mod != 0 || base == 5)
11835             {
11836               if (!ins->active_seg_prefix)
11837                 {
11838                   oappend_register (ins, att_names_seg[ds_reg - es_reg]);
11839                   oappend (ins, ":");
11840                 }
11841               print_operand_value (ins, ins->scratchbuf, 1, disp);
11842               oappend (ins, ins->scratchbuf);
11843             }
11844         }
11845     }
11846   else if (bytemode == v_bnd_mode
11847            || bytemode == v_bndmk_mode
11848            || bytemode == bnd_mode
11849            || bytemode == bnd_swap_mode
11850            || bytemode == vex_vsib_d_w_dq_mode
11851            || bytemode == vex_vsib_q_w_dq_mode)
11852     {
11853       oappend (ins, "(bad)");
11854       return;
11855     }
11856   else
11857     {
11858       /* 16 bit address mode */
11859       ins->used_prefixes |= ins->prefixes & PREFIX_ADDR;
11860       switch (ins->modrm.mod)
11861         {
11862         case 0:
11863           if (ins->modrm.rm == 6)
11864             {
11865               disp = get16 (ins);
11866               if ((disp & 0x8000) != 0)
11867                 disp -= 0x10000;
11868             }
11869           break;
11870         case 1:
11871           FETCH_DATA (ins->info, ins->codep + 1);
11872           disp = *ins->codep++;
11873           if ((disp & 0x80) != 0)
11874             disp -= 0x100;
11875           if (ins->vex.evex && shift > 0)
11876             disp <<= shift;
11877           break;
11878         case 2:
11879           disp = get16 (ins);
11880           if ((disp & 0x8000) != 0)
11881             disp -= 0x10000;
11882           break;
11883         }
11884
11885       if (!ins->intel_syntax)
11886         if (ins->modrm.mod != 0 || ins->modrm.rm == 6)
11887           {
11888             print_displacement (ins, ins->scratchbuf, disp);
11889             oappend (ins, ins->scratchbuf);
11890           }
11891
11892       if (ins->modrm.mod != 0 || ins->modrm.rm != 6)
11893         {
11894           oappend_char (ins, ins->open_char);
11895           oappend (ins, (ins->intel_syntax ? intel_index16
11896                          : att_index16)[ins->modrm.rm]);
11897           if (ins->intel_syntax
11898               && (disp || ins->modrm.mod != 0 || ins->modrm.rm == 6))
11899             {
11900               if ((bfd_signed_vma) disp >= 0)
11901                 oappend_char (ins, '+');
11902               else if (ins->modrm.mod != 1)
11903                 {
11904                   oappend_char (ins, '-');
11905                   disp = -disp;
11906                 }
11907
11908               print_displacement (ins, ins->scratchbuf, disp);
11909               oappend (ins, ins->scratchbuf);
11910             }
11911
11912           oappend_char (ins, ins->close_char);
11913         }
11914       else if (ins->intel_syntax)
11915         {
11916           if (!ins->active_seg_prefix)
11917             {
11918               oappend_register (ins, att_names_seg[ds_reg - es_reg]);
11919               oappend (ins, ":");
11920             }
11921           print_operand_value (ins, ins->scratchbuf, 1, disp & 0xffff);
11922           oappend (ins, ins->scratchbuf);
11923         }
11924     }
11925   if (ins->vex.b)
11926     {
11927       ins->evex_used |= EVEX_b_used;
11928
11929       /* Broadcast can only ever be valid for memory sources.  */
11930       if (ins->obufp == ins->op_out[0])
11931         ins->vex.no_broadcast = true;
11932
11933       if (!ins->vex.no_broadcast
11934           && (!ins->intel_syntax || !(ins->evex_used & EVEX_len_used)))
11935         {
11936           if (bytemode == xh_mode)
11937             {
11938               if (ins->vex.w)
11939                 oappend (ins, "{bad}");
11940               else
11941                 {
11942                   switch (ins->vex.length)
11943                     {
11944                     case 128:
11945                       oappend (ins, "{1to8}");
11946                       break;
11947                     case 256:
11948                       oappend (ins, "{1to16}");
11949                       break;
11950                     case 512:
11951                       oappend (ins, "{1to32}");
11952                       break;
11953                     default:
11954                       abort ();
11955                     }
11956                 }
11957             }
11958           else if (bytemode == q_mode
11959                    || bytemode == ymmq_mode)
11960             ins->vex.no_broadcast = true;
11961           else if (ins->vex.w
11962                    || bytemode == evex_half_bcst_xmmqdh_mode
11963                    || bytemode == evex_half_bcst_xmmq_mode)
11964             {
11965               switch (ins->vex.length)
11966                 {
11967                 case 128:
11968                   oappend (ins, "{1to2}");
11969                   break;
11970                 case 256:
11971                   oappend (ins, "{1to4}");
11972                   break;
11973                 case 512:
11974                   oappend (ins, "{1to8}");
11975                   break;
11976                 default:
11977                   abort ();
11978                 }
11979             }
11980           else if (bytemode == x_mode
11981                    || bytemode == evex_half_bcst_xmmqh_mode)
11982             {
11983               switch (ins->vex.length)
11984                 {
11985                 case 128:
11986                   oappend (ins, "{1to4}");
11987                   break;
11988                 case 256:
11989                   oappend (ins, "{1to8}");
11990                   break;
11991                 case 512:
11992                   oappend (ins, "{1to16}");
11993                   break;
11994                 default:
11995                   abort ();
11996                 }
11997             }
11998           else
11999             ins->vex.no_broadcast = true;
12000         }
12001       if (ins->vex.no_broadcast)
12002         oappend (ins, "{bad}");
12003     }
12004 }
12005
12006 static void
12007 OP_E (instr_info *ins, int bytemode, int sizeflag)
12008 {
12009   /* Skip mod/rm byte.  */
12010   MODRM_CHECK;
12011   ins->codep++;
12012
12013   if (ins->modrm.mod == 3)
12014     {
12015       if ((sizeflag & SUFFIX_ALWAYS)
12016           && (bytemode == b_swap_mode
12017               || bytemode == bnd_swap_mode
12018               || bytemode == v_swap_mode))
12019         swap_operand (ins);
12020
12021       print_register (ins, ins->modrm.rm, REX_B, bytemode, sizeflag);
12022     }
12023   else
12024     OP_E_memory (ins, bytemode, sizeflag);
12025 }
12026
12027 static void
12028 OP_G (instr_info *ins, int bytemode, int sizeflag)
12029 {
12030   if (ins->vex.evex && !ins->vex.r && ins->address_mode == mode_64bit)
12031     {
12032       oappend (ins, "(bad)");
12033       return;
12034     }
12035
12036   print_register (ins, ins->modrm.reg, REX_R, bytemode, sizeflag);
12037 }
12038
12039 #ifdef BFD64
12040 static bfd_vma
12041 get64 (instr_info *ins)
12042 {
12043   bfd_vma x;
12044   unsigned int a;
12045   unsigned int b;
12046
12047   FETCH_DATA (ins->info, ins->codep + 8);
12048   a = *ins->codep++ & 0xff;
12049   a |= (*ins->codep++ & 0xff) << 8;
12050   a |= (*ins->codep++ & 0xff) << 16;
12051   a |= (*ins->codep++ & 0xffu) << 24;
12052   b = *ins->codep++ & 0xff;
12053   b |= (*ins->codep++ & 0xff) << 8;
12054   b |= (*ins->codep++ & 0xff) << 16;
12055   b |= (*ins->codep++ & 0xffu) << 24;
12056   x = a + ((bfd_vma) b << 32);
12057   return x;
12058 }
12059 #else
12060 static bfd_vma
12061 get64 (instr_info *ins ATTRIBUTE_UNUSED)
12062 {
12063   abort ();
12064   return 0;
12065 }
12066 #endif
12067
12068 static bfd_signed_vma
12069 get32 (instr_info *ins)
12070 {
12071   bfd_vma x = 0;
12072
12073   FETCH_DATA (ins->info, ins->codep + 4);
12074   x = *ins->codep++ & (bfd_vma) 0xff;
12075   x |= (*ins->codep++ & (bfd_vma) 0xff) << 8;
12076   x |= (*ins->codep++ & (bfd_vma) 0xff) << 16;
12077   x |= (*ins->codep++ & (bfd_vma) 0xff) << 24;
12078   return x;
12079 }
12080
12081 static bfd_signed_vma
12082 get32s (instr_info *ins)
12083 {
12084   bfd_vma x = 0;
12085
12086   FETCH_DATA (ins->info, ins->codep + 4);
12087   x = *ins->codep++ & (bfd_vma) 0xff;
12088   x |= (*ins->codep++ & (bfd_vma) 0xff) << 8;
12089   x |= (*ins->codep++ & (bfd_vma) 0xff) << 16;
12090   x |= (*ins->codep++ & (bfd_vma) 0xff) << 24;
12091
12092   x = (x ^ ((bfd_vma) 1 << 31)) - ((bfd_vma) 1 << 31);
12093
12094   return x;
12095 }
12096
12097 static int
12098 get16 (instr_info *ins)
12099 {
12100   int x = 0;
12101
12102   FETCH_DATA (ins->info, ins->codep + 2);
12103   x = *ins->codep++ & 0xff;
12104   x |= (*ins->codep++ & 0xff) << 8;
12105   return x;
12106 }
12107
12108 static void
12109 set_op (instr_info *ins, bfd_vma op, bool riprel)
12110 {
12111   ins->op_index[ins->op_ad] = ins->op_ad;
12112   if (ins->address_mode == mode_64bit)
12113     ins->op_address[ins->op_ad] = op;
12114   else /* Mask to get a 32-bit address.  */
12115     ins->op_address[ins->op_ad] = op & 0xffffffff;
12116   ins->op_riprel[ins->op_ad] = riprel;
12117 }
12118
12119 static void
12120 OP_REG (instr_info *ins, int code, int sizeflag)
12121 {
12122   const char *s;
12123   int add;
12124
12125   switch (code)
12126     {
12127     case es_reg: case ss_reg: case cs_reg:
12128     case ds_reg: case fs_reg: case gs_reg:
12129       oappend_register (ins, att_names_seg[code - es_reg]);
12130       return;
12131     }
12132
12133   USED_REX (REX_B);
12134   if (ins->rex & REX_B)
12135     add = 8;
12136   else
12137     add = 0;
12138
12139   switch (code)
12140     {
12141     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
12142     case sp_reg: case bp_reg: case si_reg: case di_reg:
12143       s = att_names16[code - ax_reg + add];
12144       break;
12145     case ah_reg: case ch_reg: case dh_reg: case bh_reg:
12146       USED_REX (0);
12147       /* Fall through.  */
12148     case al_reg: case cl_reg: case dl_reg: case bl_reg:
12149       if (ins->rex)
12150         s = att_names8rex[code - al_reg + add];
12151       else
12152         s = att_names8[code - al_reg];
12153       break;
12154     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
12155     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
12156       if (ins->address_mode == mode_64bit
12157           && ((sizeflag & DFLAG) || (ins->rex & REX_W)))
12158         {
12159           s = att_names64[code - rAX_reg + add];
12160           break;
12161         }
12162       code += eAX_reg - rAX_reg;
12163       /* Fall through.  */
12164     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
12165     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
12166       USED_REX (REX_W);
12167       if (ins->rex & REX_W)
12168         s = att_names64[code - eAX_reg + add];
12169       else
12170         {
12171           if (sizeflag & DFLAG)
12172             s = att_names32[code - eAX_reg + add];
12173           else
12174             s = att_names16[code - eAX_reg + add];
12175           ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12176         }
12177       break;
12178     default:
12179       oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12180       return;
12181     }
12182   oappend_register (ins, s);
12183 }
12184
12185 static void
12186 OP_IMREG (instr_info *ins, int code, int sizeflag)
12187 {
12188   const char *s;
12189
12190   switch (code)
12191     {
12192     case indir_dx_reg:
12193       if (!ins->intel_syntax)
12194         {
12195           oappend (ins, "(%dx)");
12196           return;
12197         }
12198       s = att_names16[dx_reg - ax_reg];
12199       break;
12200     case al_reg: case cl_reg:
12201       s = att_names8[code - al_reg];
12202       break;
12203     case eAX_reg:
12204       USED_REX (REX_W);
12205       if (ins->rex & REX_W)
12206         {
12207           s = *att_names64;
12208           break;
12209         }
12210       /* Fall through.  */
12211     case z_mode_ax_reg:
12212       if ((ins->rex & REX_W) || (sizeflag & DFLAG))
12213         s = *att_names32;
12214       else
12215         s = *att_names16;
12216       if (!(ins->rex & REX_W))
12217         ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12218       break;
12219     default:
12220       oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12221       return;
12222     }
12223   oappend_register (ins, s);
12224 }
12225
12226 static void
12227 OP_I (instr_info *ins, int bytemode, int sizeflag)
12228 {
12229   bfd_signed_vma op;
12230   bfd_signed_vma mask = -1;
12231
12232   switch (bytemode)
12233     {
12234     case b_mode:
12235       FETCH_DATA (ins->info, ins->codep + 1);
12236       op = *ins->codep++;
12237       mask = 0xff;
12238       break;
12239     case v_mode:
12240       USED_REX (REX_W);
12241       if (ins->rex & REX_W)
12242         op = get32s (ins);
12243       else
12244         {
12245           if (sizeflag & DFLAG)
12246             {
12247               op = get32 (ins);
12248               mask = 0xffffffff;
12249             }
12250           else
12251             {
12252               op = get16 (ins);
12253               mask = 0xfffff;
12254             }
12255           ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12256         }
12257       break;
12258     case d_mode:
12259       mask = 0xffffffff;
12260       op = get32 (ins);
12261       break;
12262     case w_mode:
12263       mask = 0xfffff;
12264       op = get16 (ins);
12265       break;
12266     case const_1_mode:
12267       if (ins->intel_syntax)
12268         oappend (ins, "1");
12269       return;
12270     default:
12271       oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12272       return;
12273     }
12274
12275   op &= mask;
12276   ins->scratchbuf[0] = '$';
12277   print_operand_value (ins, ins->scratchbuf + 1, 1, op);
12278   oappend_immediate (ins, ins->scratchbuf);
12279   ins->scratchbuf[0] = '\0';
12280 }
12281
12282 static void
12283 OP_I64 (instr_info *ins, int bytemode, int sizeflag)
12284 {
12285   if (bytemode != v_mode || ins->address_mode != mode_64bit
12286       || !(ins->rex & REX_W))
12287     {
12288       OP_I (ins, bytemode, sizeflag);
12289       return;
12290     }
12291
12292   USED_REX (REX_W);
12293
12294   ins->scratchbuf[0] = '$';
12295   print_operand_value (ins, ins->scratchbuf + 1, 1, get64 (ins));
12296   oappend_immediate (ins, ins->scratchbuf);
12297   ins->scratchbuf[0] = '\0';
12298 }
12299
12300 static void
12301 OP_sI (instr_info *ins, int bytemode, int sizeflag)
12302 {
12303   bfd_signed_vma op;
12304
12305   switch (bytemode)
12306     {
12307     case b_mode:
12308     case b_T_mode:
12309       FETCH_DATA (ins->info, ins->codep + 1);
12310       op = *ins->codep++;
12311       if ((op & 0x80) != 0)
12312         op -= 0x100;
12313       if (bytemode == b_T_mode)
12314         {
12315           if (ins->address_mode != mode_64bit
12316               || !((sizeflag & DFLAG) || (ins->rex & REX_W)))
12317             {
12318               /* The operand-size prefix is overridden by a REX prefix.  */
12319               if ((sizeflag & DFLAG) || (ins->rex & REX_W))
12320                 op &= 0xffffffff;
12321               else
12322                 op &= 0xffff;
12323           }
12324         }
12325       else
12326         {
12327           if (!(ins->rex & REX_W))
12328             {
12329               if (sizeflag & DFLAG)
12330                 op &= 0xffffffff;
12331               else
12332                 op &= 0xffff;
12333             }
12334         }
12335       break;
12336     case v_mode:
12337       /* The operand-size prefix is overridden by a REX prefix.  */
12338       if ((sizeflag & DFLAG) || (ins->rex & REX_W))
12339         op = get32s (ins);
12340       else
12341         op = get16 (ins);
12342       break;
12343     default:
12344       oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12345       return;
12346     }
12347
12348   ins->scratchbuf[0] = '$';
12349   print_operand_value (ins, ins->scratchbuf + 1, 1, op);
12350   oappend_immediate (ins, ins->scratchbuf);
12351 }
12352
12353 static void
12354 OP_J (instr_info *ins, int bytemode, int sizeflag)
12355 {
12356   bfd_vma disp;
12357   bfd_vma mask = -1;
12358   bfd_vma segment = 0;
12359
12360   switch (bytemode)
12361     {
12362     case b_mode:
12363       FETCH_DATA (ins->info, ins->codep + 1);
12364       disp = *ins->codep++;
12365       if ((disp & 0x80) != 0)
12366         disp -= 0x100;
12367       break;
12368     case v_mode:
12369     case dqw_mode:
12370       if ((sizeflag & DFLAG)
12371           || (ins->address_mode == mode_64bit
12372               && ((ins->isa64 == intel64 && bytemode != dqw_mode)
12373                   || (ins->rex & REX_W))))
12374         disp = get32s (ins);
12375       else
12376         {
12377           disp = get16 (ins);
12378           if ((disp & 0x8000) != 0)
12379             disp -= 0x10000;
12380           /* In 16bit mode, address is wrapped around at 64k within
12381              the same segment.  Otherwise, a data16 prefix on a jump
12382              instruction means that the pc is masked to 16 bits after
12383              the displacement is added!  */
12384           mask = 0xffff;
12385           if ((ins->prefixes & PREFIX_DATA) == 0)
12386             segment = ((ins->start_pc + (ins->codep - ins->start_codep))
12387                        & ~((bfd_vma) 0xffff));
12388         }
12389       if (ins->address_mode != mode_64bit
12390           || (ins->isa64 != intel64 && !(ins->rex & REX_W)))
12391         ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12392       break;
12393     default:
12394       oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12395       return;
12396     }
12397   disp = ((ins->start_pc + (ins->codep - ins->start_codep) + disp) & mask)
12398          | segment;
12399   set_op (ins, disp, false);
12400   print_operand_value (ins, ins->scratchbuf, 1, disp);
12401   oappend (ins, ins->scratchbuf);
12402 }
12403
12404 static void
12405 OP_SEG (instr_info *ins, int bytemode, int sizeflag)
12406 {
12407   if (bytemode == w_mode)
12408     oappend_register (ins, att_names_seg[ins->modrm.reg]);
12409   else
12410     OP_E (ins, ins->modrm.mod == 3 ? bytemode : w_mode, sizeflag);
12411 }
12412
12413 static void
12414 OP_DIR (instr_info *ins, int dummy ATTRIBUTE_UNUSED, int sizeflag)
12415 {
12416   int seg, offset;
12417
12418   if (sizeflag & DFLAG)
12419     {
12420       offset = get32 (ins);
12421       seg = get16 (ins);
12422     }
12423   else
12424     {
12425       offset = get16 (ins);
12426       seg = get16 (ins);
12427     }
12428   ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12429   if (ins->intel_syntax)
12430     sprintf (ins->scratchbuf, "0x%x:0x%x", seg, offset);
12431   else
12432     sprintf (ins->scratchbuf, "$0x%x,$0x%x", seg, offset);
12433   oappend (ins, ins->scratchbuf);
12434 }
12435
12436 static void
12437 OP_OFF (instr_info *ins, int bytemode, int sizeflag)
12438 {
12439   bfd_vma off;
12440
12441   if (ins->intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12442     intel_operand_size (ins, bytemode, sizeflag);
12443   append_seg (ins);
12444
12445   if ((sizeflag & AFLAG) || ins->address_mode == mode_64bit)
12446     off = get32 (ins);
12447   else
12448     off = get16 (ins);
12449
12450   if (ins->intel_syntax)
12451     {
12452       if (!ins->active_seg_prefix)
12453         {
12454           oappend_register (ins, att_names_seg[ds_reg - es_reg]);
12455           oappend (ins, ":");
12456         }
12457     }
12458   print_operand_value (ins, ins->scratchbuf, 1, off);
12459   oappend_with_style (ins, ins->scratchbuf, dis_style_address_offset);
12460 }
12461
12462 static void
12463 OP_OFF64 (instr_info *ins, int bytemode, int sizeflag)
12464 {
12465   bfd_vma off;
12466
12467   if (ins->address_mode != mode_64bit
12468       || (ins->prefixes & PREFIX_ADDR))
12469     {
12470       OP_OFF (ins, bytemode, sizeflag);
12471       return;
12472     }
12473
12474   if (ins->intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12475     intel_operand_size (ins, bytemode, sizeflag);
12476   append_seg (ins);
12477
12478   off = get64 (ins);
12479
12480   if (ins->intel_syntax)
12481     {
12482       if (!ins->active_seg_prefix)
12483         {
12484           oappend_register (ins, att_names_seg[ds_reg - es_reg]);
12485           oappend (ins, ":");
12486         }
12487     }
12488   print_operand_value (ins, ins->scratchbuf, 1, off);
12489   oappend_with_style (ins, ins->scratchbuf, dis_style_address_offset);
12490 }
12491
12492 static void
12493 ptr_reg (instr_info *ins, int code, int sizeflag)
12494 {
12495   const char *s;
12496
12497   *ins->obufp++ = ins->open_char;
12498   ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR);
12499   if (ins->address_mode == mode_64bit)
12500     {
12501       if (!(sizeflag & AFLAG))
12502         s = att_names32[code - eAX_reg];
12503       else
12504         s = att_names64[code - eAX_reg];
12505     }
12506   else if (sizeflag & AFLAG)
12507     s = att_names32[code - eAX_reg];
12508   else
12509     s = att_names16[code - eAX_reg];
12510   oappend_register (ins, s);
12511   oappend_char (ins, ins->close_char);
12512 }
12513
12514 static void
12515 OP_ESreg (instr_info *ins, int code, int sizeflag)
12516 {
12517   if (ins->intel_syntax)
12518     {
12519       switch (ins->codep[-1])
12520         {
12521         case 0x6d:      /* insw/insl */
12522           intel_operand_size (ins, z_mode, sizeflag);
12523           break;
12524         case 0xa5:      /* movsw/movsl/movsq */
12525         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
12526         case 0xab:      /* stosw/stosl */
12527         case 0xaf:      /* scasw/scasl */
12528           intel_operand_size (ins, v_mode, sizeflag);
12529           break;
12530         default:
12531           intel_operand_size (ins, b_mode, sizeflag);
12532         }
12533     }
12534   oappend_register (ins, "%es");
12535   oappend_char (ins, ':');
12536   ptr_reg (ins, code, sizeflag);
12537 }
12538
12539 static void
12540 OP_DSreg (instr_info *ins, int code, int sizeflag)
12541 {
12542   if (ins->intel_syntax)
12543     {
12544       switch (ins->codep[-1])
12545         {
12546         case 0x6f:      /* outsw/outsl */
12547           intel_operand_size (ins, z_mode, sizeflag);
12548           break;
12549         case 0xa5:      /* movsw/movsl/movsq */
12550         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
12551         case 0xad:      /* lodsw/lodsl/lodsq */
12552           intel_operand_size (ins, v_mode, sizeflag);
12553           break;
12554         default:
12555           intel_operand_size (ins, b_mode, sizeflag);
12556         }
12557     }
12558   /* Set ins->active_seg_prefix to PREFIX_DS if it is unset so that the
12559      default segment register DS is printed.  */
12560   if (!ins->active_seg_prefix)
12561     ins->active_seg_prefix = PREFIX_DS;
12562   append_seg (ins);
12563   ptr_reg (ins, code, sizeflag);
12564 }
12565
12566 static void
12567 OP_C (instr_info *ins, int dummy ATTRIBUTE_UNUSED,
12568       int sizeflag ATTRIBUTE_UNUSED)
12569 {
12570   int add;
12571   if (ins->rex & REX_R)
12572     {
12573       USED_REX (REX_R);
12574       add = 8;
12575     }
12576   else if (ins->address_mode != mode_64bit && (ins->prefixes & PREFIX_LOCK))
12577     {
12578       ins->all_prefixes[ins->last_lock_prefix] = 0;
12579       ins->used_prefixes |= PREFIX_LOCK;
12580       add = 8;
12581     }
12582   else
12583     add = 0;
12584   sprintf (ins->scratchbuf, "%%cr%d", ins->modrm.reg + add);
12585   oappend_register (ins, ins->scratchbuf);
12586 }
12587
12588 static void
12589 OP_D (instr_info *ins, int dummy ATTRIBUTE_UNUSED,
12590       int sizeflag ATTRIBUTE_UNUSED)
12591 {
12592   int add;
12593   USED_REX (REX_R);
12594   if (ins->rex & REX_R)
12595     add = 8;
12596   else
12597     add = 0;
12598   if (ins->intel_syntax)
12599     sprintf (ins->scratchbuf, "dr%d", ins->modrm.reg + add);
12600   else
12601     sprintf (ins->scratchbuf, "%%db%d", ins->modrm.reg + add);
12602   oappend (ins, ins->scratchbuf);
12603 }
12604
12605 static void
12606 OP_T (instr_info *ins, int dummy ATTRIBUTE_UNUSED,
12607       int sizeflag ATTRIBUTE_UNUSED)
12608 {
12609   sprintf (ins->scratchbuf, "%%tr%d", ins->modrm.reg);
12610   oappend_register (ins, ins->scratchbuf);
12611 }
12612
12613 static void
12614 OP_MMX (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
12615         int sizeflag ATTRIBUTE_UNUSED)
12616 {
12617   int reg = ins->modrm.reg;
12618   const char *const *names;
12619
12620   ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12621   if (ins->prefixes & PREFIX_DATA)
12622     {
12623       names = att_names_xmm;
12624       USED_REX (REX_R);
12625       if (ins->rex & REX_R)
12626         reg += 8;
12627     }
12628   else
12629     names = att_names_mm;
12630   oappend_register (ins, names[reg]);
12631 }
12632
12633 static void
12634 print_vector_reg (instr_info *ins, unsigned int reg, int bytemode)
12635 {
12636   const char *const *names;
12637
12638   if (bytemode == xmmq_mode
12639       || bytemode == evex_half_bcst_xmmqh_mode
12640       || bytemode == evex_half_bcst_xmmq_mode)
12641     {
12642       switch (ins->vex.length)
12643         {
12644         case 128:
12645         case 256:
12646           names = att_names_xmm;
12647           break;
12648         case 512:
12649           names = att_names_ymm;
12650           ins->evex_used |= EVEX_len_used;
12651           break;
12652         default:
12653           abort ();
12654         }
12655     }
12656   else if (bytemode == ymm_mode)
12657     names = att_names_ymm;
12658   else if (bytemode == tmm_mode)
12659     {
12660       if (reg >= 8)
12661         {
12662           oappend (ins, "(bad)");
12663           return;
12664         }
12665       names = att_names_tmm;
12666     }
12667   else if (ins->need_vex
12668            && bytemode != xmm_mode
12669            && bytemode != scalar_mode
12670            && bytemode != xmmdw_mode
12671            && bytemode != xmmqd_mode
12672            && bytemode != evex_half_bcst_xmmqdh_mode
12673            && bytemode != w_swap_mode
12674            && bytemode != b_mode
12675            && bytemode != w_mode
12676            && bytemode != d_mode
12677            && bytemode != q_mode)
12678     {
12679       ins->evex_used |= EVEX_len_used;
12680       switch (ins->vex.length)
12681         {
12682         case 128:
12683           names = att_names_xmm;
12684           break;
12685         case 256:
12686           if (ins->vex.w
12687               || bytemode != vex_vsib_q_w_dq_mode)
12688             names = att_names_ymm;
12689           else
12690             names = att_names_xmm;
12691           break;
12692         case 512:
12693           if (ins->vex.w
12694               || bytemode != vex_vsib_q_w_dq_mode)
12695             names = att_names_zmm;
12696           else
12697             names = att_names_ymm;
12698           break;
12699         default:
12700           abort ();
12701         }
12702     }
12703   else
12704     names = att_names_xmm;
12705   oappend_register (ins, names[reg]);
12706 }
12707
12708 static void
12709 OP_XMM (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
12710 {
12711   unsigned int reg = ins->modrm.reg;
12712
12713   USED_REX (REX_R);
12714   if (ins->rex & REX_R)
12715     reg += 8;
12716   if (ins->vex.evex)
12717     {
12718       if (!ins->vex.r)
12719         reg += 16;
12720     }
12721
12722   if (bytemode == tmm_mode)
12723     ins->modrm.reg = reg;
12724   else if (bytemode == scalar_mode)
12725     ins->vex.no_broadcast = true;
12726
12727   print_vector_reg (ins, reg, bytemode);
12728 }
12729
12730 static void
12731 OP_EM (instr_info *ins, int bytemode, int sizeflag)
12732 {
12733   int reg;
12734   const char *const *names;
12735
12736   if (ins->modrm.mod != 3)
12737     {
12738       if (ins->intel_syntax
12739           && (bytemode == v_mode || bytemode == v_swap_mode))
12740         {
12741           bytemode = (ins->prefixes & PREFIX_DATA) ? x_mode : q_mode;
12742           ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12743         }
12744       OP_E (ins, bytemode, sizeflag);
12745       return;
12746     }
12747
12748   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
12749     swap_operand (ins);
12750
12751   /* Skip mod/rm byte.  */
12752   MODRM_CHECK;
12753   ins->codep++;
12754   ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12755   reg = ins->modrm.rm;
12756   if (ins->prefixes & PREFIX_DATA)
12757     {
12758       names = att_names_xmm;
12759       USED_REX (REX_B);
12760       if (ins->rex & REX_B)
12761         reg += 8;
12762     }
12763   else
12764     names = att_names_mm;
12765   oappend_register (ins, names[reg]);
12766 }
12767
12768 /* cvt* are the only instructions in sse2 which have
12769    both SSE and MMX operands and also have 0x66 prefix
12770    in their opcode. 0x66 was originally used to differentiate
12771    between SSE and MMX instruction(operands). So we have to handle the
12772    cvt* separately using OP_EMC and OP_MXC */
12773 static void
12774 OP_EMC (instr_info *ins, int bytemode, int sizeflag)
12775 {
12776   if (ins->modrm.mod != 3)
12777     {
12778       if (ins->intel_syntax && bytemode == v_mode)
12779         {
12780           bytemode = (ins->prefixes & PREFIX_DATA) ? x_mode : q_mode;
12781           ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12782         }
12783       OP_E (ins, bytemode, sizeflag);
12784       return;
12785     }
12786
12787   /* Skip mod/rm byte.  */
12788   MODRM_CHECK;
12789   ins->codep++;
12790   ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12791   oappend_register (ins, att_names_mm[ins->modrm.rm]);
12792 }
12793
12794 static void
12795 OP_MXC (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
12796         int sizeflag ATTRIBUTE_UNUSED)
12797 {
12798   ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12799   oappend_register (ins, att_names_mm[ins->modrm.reg]);
12800 }
12801
12802 static void
12803 OP_EX (instr_info *ins, int bytemode, int sizeflag)
12804 {
12805   int reg;
12806
12807   /* Skip mod/rm byte.  */
12808   MODRM_CHECK;
12809   ins->codep++;
12810
12811   if (bytemode == dq_mode)
12812     bytemode = ins->vex.w ? q_mode : d_mode;
12813
12814   if (ins->modrm.mod != 3)
12815     {
12816       OP_E_memory (ins, bytemode, sizeflag);
12817       return;
12818     }
12819
12820   reg = ins->modrm.rm;
12821   USED_REX (REX_B);
12822   if (ins->rex & REX_B)
12823     reg += 8;
12824   if (ins->vex.evex)
12825     {
12826       USED_REX (REX_X);
12827       if ((ins->rex & REX_X))
12828         reg += 16;
12829     }
12830
12831   if ((sizeflag & SUFFIX_ALWAYS)
12832       && (bytemode == x_swap_mode
12833           || bytemode == w_swap_mode
12834           || bytemode == d_swap_mode
12835           || bytemode == q_swap_mode))
12836     swap_operand (ins);
12837
12838   if (bytemode == tmm_mode)
12839     ins->modrm.rm = reg;
12840
12841   print_vector_reg (ins, reg, bytemode);
12842 }
12843
12844 static void
12845 OP_MS (instr_info *ins, int bytemode, int sizeflag)
12846 {
12847   if (ins->modrm.mod == 3)
12848     OP_EM (ins, bytemode, sizeflag);
12849   else
12850     BadOp (ins);
12851 }
12852
12853 static void
12854 OP_XS (instr_info *ins, int bytemode, int sizeflag)
12855 {
12856   if (ins->modrm.mod == 3)
12857     OP_EX (ins, bytemode, sizeflag);
12858   else
12859     BadOp (ins);
12860 }
12861
12862 static void
12863 OP_M (instr_info *ins, int bytemode, int sizeflag)
12864 {
12865   if (ins->modrm.mod == 3)
12866     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
12867     BadOp (ins);
12868   else
12869     OP_E (ins, bytemode, sizeflag);
12870 }
12871
12872 static void
12873 OP_0f07 (instr_info *ins, int bytemode, int sizeflag)
12874 {
12875   if (ins->modrm.mod != 3 || ins->modrm.rm != 0)
12876     BadOp (ins);
12877   else
12878     OP_E (ins, bytemode, sizeflag);
12879 }
12880
12881 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
12882    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
12883
12884 static void
12885 NOP_Fixup (instr_info *ins, int opnd, int sizeflag)
12886 {
12887   if ((ins->prefixes & PREFIX_DATA) == 0 && (ins->rex & REX_B) == 0)
12888     ins->mnemonicendp = stpcpy (ins->obuf, "nop");
12889   else if (opnd == 0)
12890     OP_REG (ins, eAX_reg, sizeflag);
12891   else
12892     OP_IMREG (ins, eAX_reg, sizeflag);
12893 }
12894
12895 static const char *const Suffix3DNow[] = {
12896 /* 00 */        NULL,           NULL,           NULL,           NULL,
12897 /* 04 */        NULL,           NULL,           NULL,           NULL,
12898 /* 08 */        NULL,           NULL,           NULL,           NULL,
12899 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
12900 /* 10 */        NULL,           NULL,           NULL,           NULL,
12901 /* 14 */        NULL,           NULL,           NULL,           NULL,
12902 /* 18 */        NULL,           NULL,           NULL,           NULL,
12903 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
12904 /* 20 */        NULL,           NULL,           NULL,           NULL,
12905 /* 24 */        NULL,           NULL,           NULL,           NULL,
12906 /* 28 */        NULL,           NULL,           NULL,           NULL,
12907 /* 2C */        NULL,           NULL,           NULL,           NULL,
12908 /* 30 */        NULL,           NULL,           NULL,           NULL,
12909 /* 34 */        NULL,           NULL,           NULL,           NULL,
12910 /* 38 */        NULL,           NULL,           NULL,           NULL,
12911 /* 3C */        NULL,           NULL,           NULL,           NULL,
12912 /* 40 */        NULL,           NULL,           NULL,           NULL,
12913 /* 44 */        NULL,           NULL,           NULL,           NULL,
12914 /* 48 */        NULL,           NULL,           NULL,           NULL,
12915 /* 4C */        NULL,           NULL,           NULL,           NULL,
12916 /* 50 */        NULL,           NULL,           NULL,           NULL,
12917 /* 54 */        NULL,           NULL,           NULL,           NULL,
12918 /* 58 */        NULL,           NULL,           NULL,           NULL,
12919 /* 5C */        NULL,           NULL,           NULL,           NULL,
12920 /* 60 */        NULL,           NULL,           NULL,           NULL,
12921 /* 64 */        NULL,           NULL,           NULL,           NULL,
12922 /* 68 */        NULL,           NULL,           NULL,           NULL,
12923 /* 6C */        NULL,           NULL,           NULL,           NULL,
12924 /* 70 */        NULL,           NULL,           NULL,           NULL,
12925 /* 74 */        NULL,           NULL,           NULL,           NULL,
12926 /* 78 */        NULL,           NULL,           NULL,           NULL,
12927 /* 7C */        NULL,           NULL,           NULL,           NULL,
12928 /* 80 */        NULL,           NULL,           NULL,           NULL,
12929 /* 84 */        NULL,           NULL,           NULL,           NULL,
12930 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
12931 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
12932 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
12933 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
12934 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
12935 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
12936 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
12937 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
12938 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
12939 /* AC */        NULL,           NULL,           "pfacc",        NULL,
12940 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
12941 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
12942 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
12943 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
12944 /* C0 */        NULL,           NULL,           NULL,           NULL,
12945 /* C4 */        NULL,           NULL,           NULL,           NULL,
12946 /* C8 */        NULL,           NULL,           NULL,           NULL,
12947 /* CC */        NULL,           NULL,           NULL,           NULL,
12948 /* D0 */        NULL,           NULL,           NULL,           NULL,
12949 /* D4 */        NULL,           NULL,           NULL,           NULL,
12950 /* D8 */        NULL,           NULL,           NULL,           NULL,
12951 /* DC */        NULL,           NULL,           NULL,           NULL,
12952 /* E0 */        NULL,           NULL,           NULL,           NULL,
12953 /* E4 */        NULL,           NULL,           NULL,           NULL,
12954 /* E8 */        NULL,           NULL,           NULL,           NULL,
12955 /* EC */        NULL,           NULL,           NULL,           NULL,
12956 /* F0 */        NULL,           NULL,           NULL,           NULL,
12957 /* F4 */        NULL,           NULL,           NULL,           NULL,
12958 /* F8 */        NULL,           NULL,           NULL,           NULL,
12959 /* FC */        NULL,           NULL,           NULL,           NULL,
12960 };
12961
12962 static void
12963 OP_3DNowSuffix (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
12964                 int sizeflag ATTRIBUTE_UNUSED)
12965 {
12966   const char *mnemonic;
12967
12968   FETCH_DATA (ins->info, ins->codep + 1);
12969   /* AMD 3DNow! instructions are specified by an opcode suffix in the
12970      place where an 8-bit immediate would normally go.  ie. the last
12971      byte of the instruction.  */
12972   ins->obufp = ins->mnemonicendp;
12973   mnemonic = Suffix3DNow[*ins->codep++ & 0xff];
12974   if (mnemonic)
12975     ins->obufp = stpcpy (ins->obufp, mnemonic);
12976   else
12977     {
12978       /* Since a variable sized ins->modrm/ins->sib chunk is between the start
12979          of the opcode (0x0f0f) and the opcode suffix, we need to do
12980          all the ins->modrm processing first, and don't know until now that
12981          we have a bad opcode.  This necessitates some cleaning up.  */
12982       ins->op_out[0][0] = '\0';
12983       ins->op_out[1][0] = '\0';
12984       BadOp (ins);
12985     }
12986   ins->mnemonicendp = ins->obufp;
12987 }
12988
12989 static const struct op simd_cmp_op[] =
12990 {
12991   { STRING_COMMA_LEN ("eq") },
12992   { STRING_COMMA_LEN ("lt") },
12993   { STRING_COMMA_LEN ("le") },
12994   { STRING_COMMA_LEN ("unord") },
12995   { STRING_COMMA_LEN ("neq") },
12996   { STRING_COMMA_LEN ("nlt") },
12997   { STRING_COMMA_LEN ("nle") },
12998   { STRING_COMMA_LEN ("ord") }
12999 };
13000
13001 static const struct op vex_cmp_op[] =
13002 {
13003   { STRING_COMMA_LEN ("eq_uq") },
13004   { STRING_COMMA_LEN ("nge") },
13005   { STRING_COMMA_LEN ("ngt") },
13006   { STRING_COMMA_LEN ("false") },
13007   { STRING_COMMA_LEN ("neq_oq") },
13008   { STRING_COMMA_LEN ("ge") },
13009   { STRING_COMMA_LEN ("gt") },
13010   { STRING_COMMA_LEN ("true") },
13011   { STRING_COMMA_LEN ("eq_os") },
13012   { STRING_COMMA_LEN ("lt_oq") },
13013   { STRING_COMMA_LEN ("le_oq") },
13014   { STRING_COMMA_LEN ("unord_s") },
13015   { STRING_COMMA_LEN ("neq_us") },
13016   { STRING_COMMA_LEN ("nlt_uq") },
13017   { STRING_COMMA_LEN ("nle_uq") },
13018   { STRING_COMMA_LEN ("ord_s") },
13019   { STRING_COMMA_LEN ("eq_us") },
13020   { STRING_COMMA_LEN ("nge_uq") },
13021   { STRING_COMMA_LEN ("ngt_uq") },
13022   { STRING_COMMA_LEN ("false_os") },
13023   { STRING_COMMA_LEN ("neq_os") },
13024   { STRING_COMMA_LEN ("ge_oq") },
13025   { STRING_COMMA_LEN ("gt_oq") },
13026   { STRING_COMMA_LEN ("true_us") },
13027 };
13028
13029 static void
13030 CMP_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13031            int sizeflag ATTRIBUTE_UNUSED)
13032 {
13033   unsigned int cmp_type;
13034
13035   FETCH_DATA (ins->info, ins->codep + 1);
13036   cmp_type = *ins->codep++ & 0xff;
13037   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
13038     {
13039       char suffix[3];
13040       char *p = ins->mnemonicendp - 2;
13041       suffix[0] = p[0];
13042       suffix[1] = p[1];
13043       suffix[2] = '\0';
13044       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13045       ins->mnemonicendp += simd_cmp_op[cmp_type].len;
13046     }
13047   else if (ins->need_vex
13048            && cmp_type < ARRAY_SIZE (simd_cmp_op) + ARRAY_SIZE (vex_cmp_op))
13049     {
13050       char suffix[3];
13051       char *p = ins->mnemonicendp - 2;
13052       suffix[0] = p[0];
13053       suffix[1] = p[1];
13054       suffix[2] = '\0';
13055       cmp_type -= ARRAY_SIZE (simd_cmp_op);
13056       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
13057       ins->mnemonicendp += vex_cmp_op[cmp_type].len;
13058     }
13059   else
13060     {
13061       /* We have a reserved extension byte.  Output it directly.  */
13062       ins->scratchbuf[0] = '$';
13063       print_operand_value (ins, ins->scratchbuf + 1, 1, cmp_type);
13064       oappend_immediate (ins, ins->scratchbuf);
13065       ins->scratchbuf[0] = '\0';
13066     }
13067 }
13068
13069 static void
13070 OP_Mwait (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13071 {
13072   /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx  */
13073   if (!ins->intel_syntax)
13074     {
13075       strcpy (ins->op_out[0], att_names32[0] + ins->intel_syntax);
13076       strcpy (ins->op_out[1], att_names32[1] + ins->intel_syntax);
13077       if (bytemode == eBX_reg)
13078         strcpy (ins->op_out[2], att_names32[3] + ins->intel_syntax);
13079       ins->two_source_ops = true;
13080     }
13081   /* Skip mod/rm byte.  */
13082   MODRM_CHECK;
13083   ins->codep++;
13084 }
13085
13086 static void
13087 OP_Monitor (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13088             int sizeflag ATTRIBUTE_UNUSED)
13089 {
13090   /* monitor %{e,r,}ax,%ecx,%edx"  */
13091   if (!ins->intel_syntax)
13092     {
13093       const char *const *names = (ins->address_mode == mode_64bit
13094                                   ? att_names64 : att_names32);
13095
13096       if (ins->prefixes & PREFIX_ADDR)
13097         {
13098           /* Remove "addr16/addr32".  */
13099           ins->all_prefixes[ins->last_addr_prefix] = 0;
13100           names = (ins->address_mode != mode_32bit
13101                    ? att_names32 : att_names16);
13102           ins->used_prefixes |= PREFIX_ADDR;
13103         }
13104       else if (ins->address_mode == mode_16bit)
13105         names = att_names16;
13106       strcpy (ins->op_out[0], names[0] + ins->intel_syntax);
13107       strcpy (ins->op_out[1], att_names32[1] + ins->intel_syntax);
13108       strcpy (ins->op_out[2], att_names32[2] + ins->intel_syntax);
13109       ins->two_source_ops = true;
13110     }
13111   /* Skip mod/rm byte.  */
13112   MODRM_CHECK;
13113   ins->codep++;
13114 }
13115
13116 static void
13117 BadOp (instr_info *ins)
13118 {
13119   /* Throw away prefixes and 1st. opcode byte.  */
13120   ins->codep = ins->insn_codep + 1;
13121   ins->obufp = stpcpy (ins->obufp, "(bad)");
13122 }
13123
13124 static void
13125 REP_Fixup (instr_info *ins, int bytemode, int sizeflag)
13126 {
13127   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
13128      lods and stos.  */
13129   if (ins->prefixes & PREFIX_REPZ)
13130     ins->all_prefixes[ins->last_repz_prefix] = REP_PREFIX;
13131
13132   switch (bytemode)
13133     {
13134     case al_reg:
13135     case eAX_reg:
13136     case indir_dx_reg:
13137       OP_IMREG (ins, bytemode, sizeflag);
13138       break;
13139     case eDI_reg:
13140       OP_ESreg (ins, bytemode, sizeflag);
13141       break;
13142     case eSI_reg:
13143       OP_DSreg (ins, bytemode, sizeflag);
13144       break;
13145     default:
13146       abort ();
13147       break;
13148     }
13149 }
13150
13151 static void
13152 SEP_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13153            int sizeflag ATTRIBUTE_UNUSED)
13154 {
13155   if (ins->isa64 != amd64)
13156     return;
13157
13158   ins->obufp = ins->obuf;
13159   BadOp (ins);
13160   ins->mnemonicendp = ins->obufp;
13161   ++ins->codep;
13162 }
13163
13164 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
13165    "bnd".  */
13166
13167 static void
13168 BND_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13169            int sizeflag ATTRIBUTE_UNUSED)
13170 {
13171   if (ins->prefixes & PREFIX_REPNZ)
13172     ins->all_prefixes[ins->last_repnz_prefix] = BND_PREFIX;
13173 }
13174
13175 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
13176    "notrack".  */
13177
13178 static void
13179 NOTRACK_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13180                int sizeflag ATTRIBUTE_UNUSED)
13181 {
13182   /* Since active_seg_prefix is not set in 64-bit mode, check whether
13183      we've seen a PREFIX_DS.  */
13184   if ((ins->prefixes & PREFIX_DS) != 0
13185       && (ins->address_mode != mode_64bit || ins->last_data_prefix < 0))
13186     {
13187       /* NOTRACK prefix is only valid on indirect branch instructions.
13188          NB: DATA prefix is unsupported for Intel64.  */
13189       ins->active_seg_prefix = 0;
13190       ins->all_prefixes[ins->last_seg_prefix] = NOTRACK_PREFIX;
13191     }
13192 }
13193
13194 /* Similar to OP_E.  But the 0xf2/0xf3 ins->prefixes should be displayed as
13195    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
13196  */
13197
13198 static void
13199 HLE_Fixup1 (instr_info *ins, int bytemode, int sizeflag)
13200 {
13201   if (ins->modrm.mod != 3
13202       && (ins->prefixes & PREFIX_LOCK) != 0)
13203     {
13204       if (ins->prefixes & PREFIX_REPZ)
13205         ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13206       if (ins->prefixes & PREFIX_REPNZ)
13207         ins->all_prefixes[ins->last_repnz_prefix] = XACQUIRE_PREFIX;
13208     }
13209
13210   OP_E (ins, bytemode, sizeflag);
13211 }
13212
13213 /* Similar to OP_E.  But the 0xf2/0xf3 ins->prefixes should be displayed as
13214    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
13215  */
13216
13217 static void
13218 HLE_Fixup2 (instr_info *ins, int bytemode, int sizeflag)
13219 {
13220   if (ins->modrm.mod != 3)
13221     {
13222       if (ins->prefixes & PREFIX_REPZ)
13223         ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13224       if (ins->prefixes & PREFIX_REPNZ)
13225         ins->all_prefixes[ins->last_repnz_prefix] = XACQUIRE_PREFIX;
13226     }
13227
13228   OP_E (ins, bytemode, sizeflag);
13229 }
13230
13231 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
13232    "xrelease" for memory operand.  No check for LOCK prefix.   */
13233
13234 static void
13235 HLE_Fixup3 (instr_info *ins, int bytemode, int sizeflag)
13236 {
13237   if (ins->modrm.mod != 3
13238       && ins->last_repz_prefix > ins->last_repnz_prefix
13239       && (ins->prefixes & PREFIX_REPZ) != 0)
13240     ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13241
13242   OP_E (ins, bytemode, sizeflag);
13243 }
13244
13245 static void
13246 CMPXCHG8B_Fixup (instr_info *ins, int bytemode, int sizeflag)
13247 {
13248   USED_REX (REX_W);
13249   if (ins->rex & REX_W)
13250     {
13251       /* Change cmpxchg8b to cmpxchg16b.  */
13252       char *p = ins->mnemonicendp - 2;
13253       ins->mnemonicendp = stpcpy (p, "16b");
13254       bytemode = o_mode;
13255     }
13256   else if ((ins->prefixes & PREFIX_LOCK) != 0)
13257     {
13258       if (ins->prefixes & PREFIX_REPZ)
13259         ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13260       if (ins->prefixes & PREFIX_REPNZ)
13261         ins->all_prefixes[ins->last_repnz_prefix] = XACQUIRE_PREFIX;
13262     }
13263
13264   OP_M (ins, bytemode, sizeflag);
13265 }
13266
13267 static void
13268 XMM_Fixup (instr_info *ins, int reg, int sizeflag ATTRIBUTE_UNUSED)
13269 {
13270   const char *const *names = att_names_xmm;
13271
13272   if (ins->need_vex)
13273     {
13274       switch (ins->vex.length)
13275         {
13276         case 128:
13277           break;
13278         case 256:
13279           names = att_names_ymm;
13280           break;
13281         default:
13282           abort ();
13283         }
13284     }
13285   oappend_register (ins, names[reg]);
13286 }
13287
13288 static void
13289 FXSAVE_Fixup (instr_info *ins, int bytemode, int sizeflag)
13290 {
13291   /* Add proper suffix to "fxsave" and "fxrstor".  */
13292   USED_REX (REX_W);
13293   if (ins->rex & REX_W)
13294     {
13295       char *p = ins->mnemonicendp;
13296       *p++ = '6';
13297       *p++ = '4';
13298       *p = '\0';
13299       ins->mnemonicendp = p;
13300     }
13301   OP_M (ins, bytemode, sizeflag);
13302 }
13303
13304 /* Display the destination register operand for instructions with
13305    VEX. */
13306
13307 static void
13308 OP_VEX (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13309 {
13310   int reg, modrm_reg, sib_index = -1;
13311   const char *const *names;
13312
13313   if (!ins->need_vex)
13314     abort ();
13315
13316   reg = ins->vex.register_specifier;
13317   ins->vex.register_specifier = 0;
13318   if (ins->address_mode != mode_64bit)
13319     {
13320       if (ins->vex.evex && !ins->vex.v)
13321         {
13322           oappend (ins, "(bad)");
13323           return;
13324         }
13325
13326       reg &= 7;
13327     }
13328   else if (ins->vex.evex && !ins->vex.v)
13329     reg += 16;
13330
13331   switch (bytemode)
13332     {
13333     case scalar_mode:
13334       oappend_register (ins, att_names_xmm[reg]);
13335       return;
13336
13337     case vex_vsib_d_w_dq_mode:
13338     case vex_vsib_q_w_dq_mode:
13339       /* This must be the 3rd operand.  */
13340       if (ins->obufp != ins->op_out[2])
13341         abort ();
13342       if (ins->vex.length == 128
13343           || (bytemode != vex_vsib_d_w_dq_mode
13344               && !ins->vex.w))
13345         oappend_register (ins, att_names_xmm[reg]);
13346       else
13347         oappend_register (ins, att_names_ymm[reg]);
13348
13349       /* All 3 XMM/YMM registers must be distinct.  */
13350       modrm_reg = ins->modrm.reg;
13351       if (ins->rex & REX_R)
13352         modrm_reg += 8;
13353
13354       if (ins->has_sib && ins->modrm.rm == 4)
13355         {
13356           sib_index = ins->sib.index;
13357           if (ins->rex & REX_X)
13358             sib_index += 8;
13359         }
13360
13361       if (reg == modrm_reg || reg == sib_index)
13362         strcpy (ins->obufp, "/(bad)");
13363       if (modrm_reg == sib_index || modrm_reg == reg)
13364         strcat (ins->op_out[0], "/(bad)");
13365       if (sib_index == modrm_reg || sib_index == reg)
13366         strcat (ins->op_out[1], "/(bad)");
13367
13368       return;
13369
13370     case tmm_mode:
13371       /* All 3 TMM registers must be distinct.  */
13372       if (reg >= 8)
13373         oappend (ins, "(bad)");
13374       else
13375         {
13376           /* This must be the 3rd operand.  */
13377           if (ins->obufp != ins->op_out[2])
13378             abort ();
13379           oappend_register (ins, att_names_tmm[reg]);
13380           if (reg == ins->modrm.reg || reg == ins->modrm.rm)
13381             strcpy (ins->obufp, "/(bad)");
13382         }
13383
13384       if (ins->modrm.reg == ins->modrm.rm || ins->modrm.reg == reg
13385           || ins->modrm.rm == reg)
13386         {
13387           if (ins->modrm.reg <= 8
13388               && (ins->modrm.reg == ins->modrm.rm || ins->modrm.reg == reg))
13389             strcat (ins->op_out[0], "/(bad)");
13390           if (ins->modrm.rm <= 8
13391               && (ins->modrm.rm == ins->modrm.reg || ins->modrm.rm == reg))
13392             strcat (ins->op_out[1], "/(bad)");
13393         }
13394
13395       return;
13396     }
13397
13398   switch (ins->vex.length)
13399     {
13400     case 128:
13401       switch (bytemode)
13402         {
13403         case x_mode:
13404           names = att_names_xmm;
13405           ins->evex_used |= EVEX_len_used;
13406           break;
13407         case dq_mode:
13408           if (ins->rex & REX_W)
13409             names = att_names64;
13410           else
13411             names = att_names32;
13412           break;
13413         case mask_bd_mode:
13414         case mask_mode:
13415           if (reg > 0x7)
13416             {
13417               oappend (ins, "(bad)");
13418               return;
13419             }
13420           names = att_names_mask;
13421           break;
13422         default:
13423           abort ();
13424           return;
13425         }
13426       break;
13427     case 256:
13428       switch (bytemode)
13429         {
13430         case x_mode:
13431           names = att_names_ymm;
13432           ins->evex_used |= EVEX_len_used;
13433           break;
13434         case mask_bd_mode:
13435         case mask_mode:
13436           if (reg > 0x7)
13437             {
13438               oappend (ins, "(bad)");
13439               return;
13440             }
13441           names = att_names_mask;
13442           break;
13443         default:
13444           /* See PR binutils/20893 for a reproducer.  */
13445           oappend (ins, "(bad)");
13446           return;
13447         }
13448       break;
13449     case 512:
13450       names = att_names_zmm;
13451       ins->evex_used |= EVEX_len_used;
13452       break;
13453     default:
13454       abort ();
13455       break;
13456     }
13457   oappend_register (ins, names[reg]);
13458 }
13459
13460 static void
13461 OP_VexR (instr_info *ins, int bytemode, int sizeflag)
13462 {
13463   if (ins->modrm.mod == 3)
13464     OP_VEX (ins, bytemode, sizeflag);
13465 }
13466
13467 static void
13468 OP_VexW (instr_info *ins, int bytemode, int sizeflag)
13469 {
13470   OP_VEX (ins, bytemode, sizeflag);
13471
13472   if (ins->vex.w)
13473     {
13474       /* Swap 2nd and 3rd operands.  */
13475       strcpy (ins->scratchbuf, ins->op_out[2]);
13476       strcpy (ins->op_out[2], ins->op_out[1]);
13477       strcpy (ins->op_out[1], ins->scratchbuf);
13478     }
13479 }
13480
13481 static void
13482 OP_REG_VexI4 (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13483 {
13484   int reg;
13485   const char *const *names = att_names_xmm;
13486
13487   FETCH_DATA (ins->info, ins->codep + 1);
13488   reg = *ins->codep++;
13489
13490   if (bytemode != x_mode && bytemode != scalar_mode)
13491     abort ();
13492
13493   reg >>= 4;
13494   if (ins->address_mode != mode_64bit)
13495     reg &= 7;
13496
13497   if (bytemode == x_mode && ins->vex.length == 256)
13498     names = att_names_ymm;
13499
13500   oappend_register (ins, names[reg]);
13501
13502   if (ins->vex.w)
13503     {
13504       /* Swap 3rd and 4th operands.  */
13505       strcpy (ins->scratchbuf, ins->op_out[3]);
13506       strcpy (ins->op_out[3], ins->op_out[2]);
13507       strcpy (ins->op_out[2], ins->scratchbuf);
13508     }
13509 }
13510
13511 static void
13512 OP_VexI4 (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13513           int sizeflag ATTRIBUTE_UNUSED)
13514 {
13515   ins->scratchbuf[0] = '$';
13516   print_operand_value (ins, ins->scratchbuf + 1, 1, ins->codep[-1] & 0xf);
13517   oappend_immediate (ins, ins->scratchbuf);
13518 }
13519
13520 static void
13521 VPCMP_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13522              int sizeflag ATTRIBUTE_UNUSED)
13523 {
13524   unsigned int cmp_type;
13525
13526   if (!ins->vex.evex)
13527     abort ();
13528
13529   FETCH_DATA (ins->info, ins->codep + 1);
13530   cmp_type = *ins->codep++ & 0xff;
13531   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
13532      If it's the case, print suffix, otherwise - print the immediate.  */
13533   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
13534       && cmp_type != 3
13535       && cmp_type != 7)
13536     {
13537       char suffix[3];
13538       char *p = ins->mnemonicendp - 2;
13539
13540       /* vpcmp* can have both one- and two-lettered suffix.  */
13541       if (p[0] == 'p')
13542         {
13543           p++;
13544           suffix[0] = p[0];
13545           suffix[1] = '\0';
13546         }
13547       else
13548         {
13549           suffix[0] = p[0];
13550           suffix[1] = p[1];
13551           suffix[2] = '\0';
13552         }
13553
13554       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13555       ins->mnemonicendp += simd_cmp_op[cmp_type].len;
13556     }
13557   else
13558     {
13559       /* We have a reserved extension byte.  Output it directly.  */
13560       ins->scratchbuf[0] = '$';
13561       print_operand_value (ins, ins->scratchbuf + 1, 1, cmp_type);
13562       oappend_immediate (ins, ins->scratchbuf);
13563       ins->scratchbuf[0] = '\0';
13564     }
13565 }
13566
13567 static const struct op xop_cmp_op[] =
13568 {
13569   { STRING_COMMA_LEN ("lt") },
13570   { STRING_COMMA_LEN ("le") },
13571   { STRING_COMMA_LEN ("gt") },
13572   { STRING_COMMA_LEN ("ge") },
13573   { STRING_COMMA_LEN ("eq") },
13574   { STRING_COMMA_LEN ("neq") },
13575   { STRING_COMMA_LEN ("false") },
13576   { STRING_COMMA_LEN ("true") }
13577 };
13578
13579 static void
13580 VPCOM_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13581              int sizeflag ATTRIBUTE_UNUSED)
13582 {
13583   unsigned int cmp_type;
13584
13585   FETCH_DATA (ins->info, ins->codep + 1);
13586   cmp_type = *ins->codep++ & 0xff;
13587   if (cmp_type < ARRAY_SIZE (xop_cmp_op))
13588     {
13589       char suffix[3];
13590       char *p = ins->mnemonicendp - 2;
13591
13592       /* vpcom* can have both one- and two-lettered suffix.  */
13593       if (p[0] == 'm')
13594         {
13595           p++;
13596           suffix[0] = p[0];
13597           suffix[1] = '\0';
13598         }
13599       else
13600         {
13601           suffix[0] = p[0];
13602           suffix[1] = p[1];
13603           suffix[2] = '\0';
13604         }
13605
13606       sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
13607       ins->mnemonicendp += xop_cmp_op[cmp_type].len;
13608     }
13609   else
13610     {
13611       /* We have a reserved extension byte.  Output it directly.  */
13612       ins->scratchbuf[0] = '$';
13613       print_operand_value (ins, ins->scratchbuf + 1, 1, cmp_type);
13614       oappend_immediate (ins, ins->scratchbuf);
13615       ins->scratchbuf[0] = '\0';
13616     }
13617 }
13618
13619 static const struct op pclmul_op[] =
13620 {
13621   { STRING_COMMA_LEN ("lql") },
13622   { STRING_COMMA_LEN ("hql") },
13623   { STRING_COMMA_LEN ("lqh") },
13624   { STRING_COMMA_LEN ("hqh") }
13625 };
13626
13627 static void
13628 PCLMUL_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13629               int sizeflag ATTRIBUTE_UNUSED)
13630 {
13631   unsigned int pclmul_type;
13632
13633   FETCH_DATA (ins->info, ins->codep + 1);
13634   pclmul_type = *ins->codep++ & 0xff;
13635   switch (pclmul_type)
13636     {
13637     case 0x10:
13638       pclmul_type = 2;
13639       break;
13640     case 0x11:
13641       pclmul_type = 3;
13642       break;
13643     default:
13644       break;
13645     }
13646   if (pclmul_type < ARRAY_SIZE (pclmul_op))
13647     {
13648       char suffix[4];
13649       char *p = ins->mnemonicendp - 3;
13650       suffix[0] = p[0];
13651       suffix[1] = p[1];
13652       suffix[2] = p[2];
13653       suffix[3] = '\0';
13654       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
13655       ins->mnemonicendp += pclmul_op[pclmul_type].len;
13656     }
13657   else
13658     {
13659       /* We have a reserved extension byte.  Output it directly.  */
13660       ins->scratchbuf[0] = '$';
13661       print_operand_value (ins, ins->scratchbuf + 1, 1, pclmul_type);
13662       oappend_immediate (ins, ins->scratchbuf);
13663       ins->scratchbuf[0] = '\0';
13664     }
13665 }
13666
13667 static void
13668 MOVSXD_Fixup (instr_info *ins, int bytemode, int sizeflag)
13669 {
13670   /* Add proper suffix to "movsxd".  */
13671   char *p = ins->mnemonicendp;
13672
13673   switch (bytemode)
13674     {
13675     case movsxd_mode:
13676       if (!ins->intel_syntax)
13677         {
13678           USED_REX (REX_W);
13679           if (ins->rex & REX_W)
13680             {
13681               *p++ = 'l';
13682               *p++ = 'q';
13683               break;
13684             }
13685         }
13686
13687       *p++ = 'x';
13688       *p++ = 'd';
13689       break;
13690     default:
13691       oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
13692       break;
13693     }
13694
13695   ins->mnemonicendp = p;
13696   *p = '\0';
13697   OP_E (ins, bytemode, sizeflag);
13698 }
13699
13700 static void
13701 DistinctDest_Fixup (instr_info *ins, int bytemode, int sizeflag)
13702 {
13703   unsigned int reg = ins->vex.register_specifier;
13704   unsigned int modrm_reg = ins->modrm.reg;
13705   unsigned int modrm_rm = ins->modrm.rm;
13706
13707   /* Calc destination register number.  */
13708   if (ins->rex & REX_R)
13709     modrm_reg += 8;
13710   if (!ins->vex.r)
13711     modrm_reg += 16;
13712
13713   /* Calc src1 register number.  */
13714   if (ins->address_mode != mode_64bit)
13715     reg &= 7;
13716   else if (ins->vex.evex && !ins->vex.v)
13717     reg += 16;
13718
13719   /* Calc src2 register number.  */
13720   if (ins->modrm.mod == 3)
13721     {
13722       if (ins->rex & REX_B)
13723         modrm_rm += 8;
13724       if (ins->rex & REX_X)
13725         modrm_rm += 16;
13726     }
13727
13728   /* Destination and source registers must be distinct, output bad if
13729      dest == src1 or dest == src2.  */
13730   if (modrm_reg == reg
13731       || (ins->modrm.mod == 3
13732           && modrm_reg == modrm_rm))
13733     {
13734       oappend (ins, "(bad)");
13735     }
13736   else
13737     OP_XMM (ins, bytemode, sizeflag);
13738 }
13739
13740 static void
13741 OP_Rounding (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13742 {
13743   if (ins->modrm.mod != 3 || !ins->vex.b)
13744     return;
13745
13746   switch (bytemode)
13747     {
13748     case evex_rounding_64_mode:
13749       if (ins->address_mode != mode_64bit || !ins->vex.w)
13750         return;
13751       /* Fall through.  */
13752     case evex_rounding_mode:
13753       ins->evex_used |= EVEX_b_used;
13754       oappend (ins, names_rounding[ins->vex.ll]);
13755       break;
13756     case evex_sae_mode:
13757       ins->evex_used |= EVEX_b_used;
13758       oappend (ins, "{");
13759       break;
13760     default:
13761       abort ();
13762     }
13763   oappend (ins, "sae}");
13764 }